diff --git a/.clang-format b/.clang-format index e6dd111..4730dda 100644 --- a/.clang-format +++ b/.clang-format @@ -20,8 +20,8 @@ NamespaceIndentation: All TabWidth: 4 DerivePointerAlignment: true IndentCaseLabels: true +IndentAccessModifiers: true AllowShortFunctionsOnASingleLine: InlineOnly ConstructorInitializerIndentWidth: 4 ContinuationIndentWidth: 4 UseTab: Never -... diff --git a/doc/example_list.h b/doc/example_list.h index 04c4e13..853c32d 100644 --- a/doc/example_list.h +++ b/doc/example_list.h @@ -4,4 +4,4 @@ * @example knx-hdc1008.ino * @example knx-bme680.ino * -**/ \ No newline at end of file + **/ \ No newline at end of file diff --git a/examples/knx-cc1310/Board.h b/examples/knx-cc1310/Board.h index eef0f0a..bb3d717 100644 --- a/examples/knx-cc1310/Board.h +++ b/examples/knx-cc1310/Board.h @@ -41,7 +41,7 @@ extern "C" { #include -#define Board_initGeneral() Board_init() /* deprecated */ +#define Board_initGeneral() Board_init() /* deprecated */ #include "CC1310_LAUNCHXL.h" @@ -50,100 +50,100 @@ extern "C" { /* These #defines allow us to reuse TI-RTOS across other device families */ -#define Board_ADC0 CC1310_LAUNCHXL_ADC0 -#define Board_ADC1 CC1310_LAUNCHXL_ADC1 +#define Board_ADC0 CC1310_LAUNCHXL_ADC0 +#define Board_ADC1 CC1310_LAUNCHXL_ADC1 -#define Board_ADCBUF0 CC1310_LAUNCHXL_ADCBUF0 -#define Board_ADCBUF0CHANNEL0 CC1310_LAUNCHXL_ADCBUF0CHANNEL0 -#define Board_ADCBUF0CHANNEL1 CC1310_LAUNCHXL_ADCBUF0CHANNEL1 +#define Board_ADCBUF0 CC1310_LAUNCHXL_ADCBUF0 +#define Board_ADCBUF0CHANNEL0 CC1310_LAUNCHXL_ADCBUF0CHANNEL0 +#define Board_ADCBUF0CHANNEL1 CC1310_LAUNCHXL_ADCBUF0CHANNEL1 -#define Board_CRYPTO0 CC1310_LAUNCHXL_CRYPTO0 -#define Board_AESCCM0 CC1310_LAUNCHXL_AESCCM0 -#define Board_AESGCM0 CC1310_LAUNCHXL_AESGCM0 -#define Board_AESCBC0 CC1310_LAUNCHXL_AESCBC0 -#define Board_AESCTR0 CC1310_LAUNCHXL_AESCTR0 -#define Board_AESECB0 CC1310_LAUNCHXL_AESECB0 -#define Board_AESCTRDRBG0 CC1310_LAUNCHXL_AESCTRDRBG0 -#define Board_TRNG0 CC1310_LAUNCHXL_TRNG0 +#define Board_CRYPTO0 CC1310_LAUNCHXL_CRYPTO0 +#define Board_AESCCM0 CC1310_LAUNCHXL_AESCCM0 +#define Board_AESGCM0 CC1310_LAUNCHXL_AESGCM0 +#define Board_AESCBC0 CC1310_LAUNCHXL_AESCBC0 +#define Board_AESCTR0 CC1310_LAUNCHXL_AESCTR0 +#define Board_AESECB0 CC1310_LAUNCHXL_AESECB0 +#define Board_AESCTRDRBG0 CC1310_LAUNCHXL_AESCTRDRBG0 +#define Board_TRNG0 CC1310_LAUNCHXL_TRNG0 -#define Board_DIO0 CC1310_LAUNCHXL_DIO0 -#define Board_DIO1 CC1310_LAUNCHXL_DIO1 -#define Board_DIO12 CC1310_LAUNCHXL_DIO12 -#define Board_DIO15 CC1310_LAUNCHXL_DIO15 -#define Board_DIO16_TDO CC1310_LAUNCHXL_DIO16_TDO -#define Board_DIO17_TDI CC1310_LAUNCHXL_DIO17_TDI -#define Board_DIO21 CC1310_LAUNCHXL_DIO21 -#define Board_DIO22 CC1310_LAUNCHXL_DIO22 +#define Board_DIO0 CC1310_LAUNCHXL_DIO0 +#define Board_DIO1 CC1310_LAUNCHXL_DIO1 +#define Board_DIO12 CC1310_LAUNCHXL_DIO12 +#define Board_DIO15 CC1310_LAUNCHXL_DIO15 +#define Board_DIO16_TDO CC1310_LAUNCHXL_DIO16_TDO +#define Board_DIO17_TDI CC1310_LAUNCHXL_DIO17_TDI +#define Board_DIO21 CC1310_LAUNCHXL_DIO21 +#define Board_DIO22 CC1310_LAUNCHXL_DIO22 -#define Board_GPIO_BUTTON0 CC1310_LAUNCHXL_GPIO_S1 -#define Board_GPIO_BUTTON1 CC1310_LAUNCHXL_GPIO_S2 -#define Board_GPIO_BTN1 CC1310_LAUNCHXL_GPIO_S1 -#define Board_GPIO_BTN2 CC1310_LAUNCHXL_GPIO_S2 -#define Board_GPIO_LED0 CC1310_LAUNCHXL_GPIO_LED_RED -#define Board_GPIO_LED1 CC1310_LAUNCHXL_GPIO_LED_GREEN -#define Board_GPIO_RLED CC1310_LAUNCHXL_GPIO_LED_RED -#define Board_GPIO_GLED CC1310_LAUNCHXL_GPIO_LED_GREEN -#define Board_GPIO_LED_ON CC1310_LAUNCHXL_GPIO_LED_ON -#define Board_GPIO_LED_OFF CC1310_LAUNCHXL_GPIO_LED_OFF -#define Board_GPIO_TMP116_EN CC1310_LAUNCHXL_GPIO_TMP116_EN +#define Board_GPIO_BUTTON0 CC1310_LAUNCHXL_GPIO_S1 +#define Board_GPIO_BUTTON1 CC1310_LAUNCHXL_GPIO_S2 +#define Board_GPIO_BTN1 CC1310_LAUNCHXL_GPIO_S1 +#define Board_GPIO_BTN2 CC1310_LAUNCHXL_GPIO_S2 +#define Board_GPIO_LED0 CC1310_LAUNCHXL_GPIO_LED_RED +#define Board_GPIO_LED1 CC1310_LAUNCHXL_GPIO_LED_GREEN +#define Board_GPIO_RLED CC1310_LAUNCHXL_GPIO_LED_RED +#define Board_GPIO_GLED CC1310_LAUNCHXL_GPIO_LED_GREEN +#define Board_GPIO_LED_ON CC1310_LAUNCHXL_GPIO_LED_ON +#define Board_GPIO_LED_OFF CC1310_LAUNCHXL_GPIO_LED_OFF +#define Board_GPIO_TMP116_EN CC1310_LAUNCHXL_GPIO_TMP116_EN -#define Board_GPTIMER0A CC1310_LAUNCHXL_GPTIMER0A -#define Board_GPTIMER0B CC1310_LAUNCHXL_GPTIMER0B -#define Board_GPTIMER1A CC1310_LAUNCHXL_GPTIMER1A -#define Board_GPTIMER1B CC1310_LAUNCHXL_GPTIMER1B -#define Board_GPTIMER2A CC1310_LAUNCHXL_GPTIMER2A -#define Board_GPTIMER2B CC1310_LAUNCHXL_GPTIMER2B -#define Board_GPTIMER3A CC1310_LAUNCHXL_GPTIMER3A -#define Board_GPTIMER3B CC1310_LAUNCHXL_GPTIMER3B +#define Board_GPTIMER0A CC1310_LAUNCHXL_GPTIMER0A +#define Board_GPTIMER0B CC1310_LAUNCHXL_GPTIMER0B +#define Board_GPTIMER1A CC1310_LAUNCHXL_GPTIMER1A +#define Board_GPTIMER1B CC1310_LAUNCHXL_GPTIMER1B +#define Board_GPTIMER2A CC1310_LAUNCHXL_GPTIMER2A +#define Board_GPTIMER2B CC1310_LAUNCHXL_GPTIMER2B +#define Board_GPTIMER3A CC1310_LAUNCHXL_GPTIMER3A +#define Board_GPTIMER3B CC1310_LAUNCHXL_GPTIMER3B -#define Board_I2C0 CC1310_LAUNCHXL_I2C0 -#define Board_I2C_TMP CC1310_LAUNCHXL_I2C0 +#define Board_I2C0 CC1310_LAUNCHXL_I2C0 +#define Board_I2C_TMP CC1310_LAUNCHXL_I2C0 -#define Board_I2S0 CC1310_LAUNCHXL_I2S0 -#define Board_I2S_ADO CC1310_LAUNCHXL_I2S_ADO -#define Board_I2S_ADI CC1310_LAUNCHXL_I2S_ADI -#define Board_I2S_BCLK CC1310_LAUNCHXL_I2S_BCLK -#define Board_I2S_MCLK CC1310_LAUNCHXL_I2S_MCLK -#define Board_I2S_WCLK CC1310_LAUNCHXL_I2S_WCLK +#define Board_I2S0 CC1310_LAUNCHXL_I2S0 +#define Board_I2S_ADO CC1310_LAUNCHXL_I2S_ADO +#define Board_I2S_ADI CC1310_LAUNCHXL_I2S_ADI +#define Board_I2S_BCLK CC1310_LAUNCHXL_I2S_BCLK +#define Board_I2S_MCLK CC1310_LAUNCHXL_I2S_MCLK +#define Board_I2S_WCLK CC1310_LAUNCHXL_I2S_WCLK -#define Board_NVSINTERNAL CC1310_LAUNCHXL_NVSCC26XX0 -#define Board_NVSEXTERNAL CC1310_LAUNCHXL_NVSSPI25X0 +#define Board_NVSINTERNAL CC1310_LAUNCHXL_NVSCC26XX0 +#define Board_NVSEXTERNAL CC1310_LAUNCHXL_NVSSPI25X0 -#define Board_PIN_BUTTON0 CC1310_LAUNCHXL_PIN_BTN1 -#define Board_PIN_BUTTON1 CC1310_LAUNCHXL_PIN_BTN2 -#define Board_PIN_BTN1 CC1310_LAUNCHXL_PIN_BTN1 -#define Board_PIN_BTN2 CC1310_LAUNCHXL_PIN_BTN2 -#define Board_PIN_LED0 CC1310_LAUNCHXL_PIN_RLED -#define Board_PIN_LED1 CC1310_LAUNCHXL_PIN_GLED -#define Board_PIN_LED2 CC1310_LAUNCHXL_PIN_RLED -#define Board_PIN_RLED CC1310_LAUNCHXL_PIN_RLED -#define Board_PIN_GLED CC1310_LAUNCHXL_PIN_GLED +#define Board_PIN_BUTTON0 CC1310_LAUNCHXL_PIN_BTN1 +#define Board_PIN_BUTTON1 CC1310_LAUNCHXL_PIN_BTN2 +#define Board_PIN_BTN1 CC1310_LAUNCHXL_PIN_BTN1 +#define Board_PIN_BTN2 CC1310_LAUNCHXL_PIN_BTN2 +#define Board_PIN_LED0 CC1310_LAUNCHXL_PIN_RLED +#define Board_PIN_LED1 CC1310_LAUNCHXL_PIN_GLED +#define Board_PIN_LED2 CC1310_LAUNCHXL_PIN_RLED +#define Board_PIN_RLED CC1310_LAUNCHXL_PIN_RLED +#define Board_PIN_GLED CC1310_LAUNCHXL_PIN_GLED -#define Board_PWM0 CC1310_LAUNCHXL_PWM0 -#define Board_PWM1 CC1310_LAUNCHXL_PWM1 -#define Board_PWM2 CC1310_LAUNCHXL_PWM2 -#define Board_PWM3 CC1310_LAUNCHXL_PWM3 -#define Board_PWM4 CC1310_LAUNCHXL_PWM4 -#define Board_PWM5 CC1310_LAUNCHXL_PWM5 -#define Board_PWM6 CC1310_LAUNCHXL_PWM6 -#define Board_PWM7 CC1310_LAUNCHXL_PWM7 +#define Board_PWM0 CC1310_LAUNCHXL_PWM0 +#define Board_PWM1 CC1310_LAUNCHXL_PWM1 +#define Board_PWM2 CC1310_LAUNCHXL_PWM2 +#define Board_PWM3 CC1310_LAUNCHXL_PWM3 +#define Board_PWM4 CC1310_LAUNCHXL_PWM4 +#define Board_PWM5 CC1310_LAUNCHXL_PWM5 +#define Board_PWM6 CC1310_LAUNCHXL_PWM6 +#define Board_PWM7 CC1310_LAUNCHXL_PWM7 -#define Board_SD0 CC1310_LAUNCHXL_SDSPI0 +#define Board_SD0 CC1310_LAUNCHXL_SDSPI0 -#define Board_SPI0 CC1310_LAUNCHXL_SPI0 -#define Board_SPI1 CC1310_LAUNCHXL_SPI1 -#define Board_SPI_FLASH_CS CC1310_LAUNCHXL_SPI_FLASH_CS -#define Board_FLASH_CS_ON 0 -#define Board_FLASH_CS_OFF 1 +#define Board_SPI0 CC1310_LAUNCHXL_SPI0 +#define Board_SPI1 CC1310_LAUNCHXL_SPI1 +#define Board_SPI_FLASH_CS CC1310_LAUNCHXL_SPI_FLASH_CS +#define Board_FLASH_CS_ON 0 +#define Board_FLASH_CS_OFF 1 -#define Board_SPI_MASTER CC1310_LAUNCHXL_SPI0 -#define Board_SPI_SLAVE CC1310_LAUNCHXL_SPI0 -#define Board_SPI_MASTER_READY CC1310_LAUNCHXL_SPI_MASTER_READY -#define Board_SPI_SLAVE_READY CC1310_LAUNCHXL_SPI_SLAVE_READY +#define Board_SPI_MASTER CC1310_LAUNCHXL_SPI0 +#define Board_SPI_SLAVE CC1310_LAUNCHXL_SPI0 +#define Board_SPI_MASTER_READY CC1310_LAUNCHXL_SPI_MASTER_READY +#define Board_SPI_SLAVE_READY CC1310_LAUNCHXL_SPI_SLAVE_READY -#define Board_UART0 CC1310_LAUNCHXL_UART0 +#define Board_UART0 CC1310_LAUNCHXL_UART0 -#define Board_WATCHDOG0 CC1310_LAUNCHXL_WATCHDOG0 +#define Board_WATCHDOG0 CC1310_LAUNCHXL_WATCHDOG0 #ifdef __cplusplus } diff --git a/examples/knx-cc1310/CC1310_LAUNCHXL.h b/examples/knx-cc1310/CC1310_LAUNCHXL.h index 66b7df5..8c8ee8d 100644 --- a/examples/knx-cc1310/CC1310_LAUNCHXL.h +++ b/examples/knx-cc1310/CC1310_LAUNCHXL.h @@ -50,8 +50,8 @@ extern "C" { #endif /* Includes */ -#include #include +#include /* Externs */ extern const PIN_Config BoardGpioInitTable[]; @@ -64,80 +64,80 @@ extern const PIN_Config BoardGpioInitTable[]; */ /* Analog capable DIOs */ -#define CC1310_LAUNCHXL_DIO23_ANALOG IOID_23 -#define CC1310_LAUNCHXL_DIO24_ANALOG IOID_24 -#define CC1310_LAUNCHXL_DIO25_ANALOG IOID_25 -#define CC1310_LAUNCHXL_DIO26_ANALOG IOID_26 -#define CC1310_LAUNCHXL_DIO27_ANALOG IOID_27 -#define CC1310_LAUNCHXL_DIO28_ANALOG IOID_28 -#define CC1310_LAUNCHXL_DIO29_ANALOG IOID_29 -#define CC1310_LAUNCHXL_DIO30_ANALOG IOID_30 +#define CC1310_LAUNCHXL_DIO23_ANALOG IOID_23 +#define CC1310_LAUNCHXL_DIO24_ANALOG IOID_24 +#define CC1310_LAUNCHXL_DIO25_ANALOG IOID_25 +#define CC1310_LAUNCHXL_DIO26_ANALOG IOID_26 +#define CC1310_LAUNCHXL_DIO27_ANALOG IOID_27 +#define CC1310_LAUNCHXL_DIO28_ANALOG IOID_28 +#define CC1310_LAUNCHXL_DIO29_ANALOG IOID_29 +#define CC1310_LAUNCHXL_DIO30_ANALOG IOID_30 /* Digital IOs */ -#define CC1310_LAUNCHXL_DIO0 IOID_0 -#define CC1310_LAUNCHXL_DIO1 IOID_1 -#define CC1310_LAUNCHXL_DIO12 IOID_12 -#define CC1310_LAUNCHXL_DIO15 IOID_15 -#define CC1310_LAUNCHXL_DIO16_TDO IOID_16 -#define CC1310_LAUNCHXL_DIO17_TDI IOID_17 -#define CC1310_LAUNCHXL_DIO21 IOID_21 -#define CC1310_LAUNCHXL_DIO22 IOID_22 +#define CC1310_LAUNCHXL_DIO0 IOID_0 +#define CC1310_LAUNCHXL_DIO1 IOID_1 +#define CC1310_LAUNCHXL_DIO12 IOID_12 +#define CC1310_LAUNCHXL_DIO15 IOID_15 +#define CC1310_LAUNCHXL_DIO16_TDO IOID_16 +#define CC1310_LAUNCHXL_DIO17_TDI IOID_17 +#define CC1310_LAUNCHXL_DIO21 IOID_21 +#define CC1310_LAUNCHXL_DIO22 IOID_22 /* Discrete Inputs */ -#define CC1310_LAUNCHXL_PIN_BTN1 IOID_13 -#define CC1310_LAUNCHXL_PIN_BTN2 IOID_14 +#define CC1310_LAUNCHXL_PIN_BTN1 IOID_13 +#define CC1310_LAUNCHXL_PIN_BTN2 IOID_14 /* GPIO */ -#define CC1310_LAUNCHXL_GPIO_LED_ON 1 -#define CC1310_LAUNCHXL_GPIO_LED_OFF 0 +#define CC1310_LAUNCHXL_GPIO_LED_ON 1 +#define CC1310_LAUNCHXL_GPIO_LED_OFF 0 /* I2C */ -#define CC1310_LAUNCHXL_I2C0_SCL0 IOID_4 -#define CC1310_LAUNCHXL_I2C0_SDA0 IOID_5 +#define CC1310_LAUNCHXL_I2C0_SCL0 IOID_4 +#define CC1310_LAUNCHXL_I2C0_SDA0 IOID_5 /* I2S */ -#define CC1310_LAUNCHXL_I2S_ADO IOID_25 -#define CC1310_LAUNCHXL_I2S_ADI IOID_26 -#define CC1310_LAUNCHXL_I2S_BCLK IOID_27 -#define CC1310_LAUNCHXL_I2S_MCLK PIN_UNASSIGNED -#define CC1310_LAUNCHXL_I2S_WCLK IOID_28 +#define CC1310_LAUNCHXL_I2S_ADO IOID_25 +#define CC1310_LAUNCHXL_I2S_ADI IOID_26 +#define CC1310_LAUNCHXL_I2S_BCLK IOID_27 +#define CC1310_LAUNCHXL_I2S_MCLK PIN_UNASSIGNED +#define CC1310_LAUNCHXL_I2S_WCLK IOID_28 /* LEDs */ -#define CC1310_LAUNCHXL_PIN_LED_ON 1 -#define CC1310_LAUNCHXL_PIN_LED_OFF 0 -#define CC1310_LAUNCHXL_PIN_RLED IOID_6 -#define CC1310_LAUNCHXL_PIN_GLED IOID_7 +#define CC1310_LAUNCHXL_PIN_LED_ON 1 +#define CC1310_LAUNCHXL_PIN_LED_OFF 0 +#define CC1310_LAUNCHXL_PIN_RLED IOID_6 +#define CC1310_LAUNCHXL_PIN_GLED IOID_7 /* PWM Outputs */ -#define CC1310_LAUNCHXL_PWMPIN0 CC1310_LAUNCHXL_PIN_RLED -#define CC1310_LAUNCHXL_PWMPIN1 CC1310_LAUNCHXL_PIN_GLED -#define CC1310_LAUNCHXL_PWMPIN2 PIN_UNASSIGNED -#define CC1310_LAUNCHXL_PWMPIN3 PIN_UNASSIGNED -#define CC1310_LAUNCHXL_PWMPIN4 PIN_UNASSIGNED -#define CC1310_LAUNCHXL_PWMPIN5 PIN_UNASSIGNED -#define CC1310_LAUNCHXL_PWMPIN6 PIN_UNASSIGNED -#define CC1310_LAUNCHXL_PWMPIN7 PIN_UNASSIGNED +#define CC1310_LAUNCHXL_PWMPIN0 CC1310_LAUNCHXL_PIN_RLED +#define CC1310_LAUNCHXL_PWMPIN1 CC1310_LAUNCHXL_PIN_GLED +#define CC1310_LAUNCHXL_PWMPIN2 PIN_UNASSIGNED +#define CC1310_LAUNCHXL_PWMPIN3 PIN_UNASSIGNED +#define CC1310_LAUNCHXL_PWMPIN4 PIN_UNASSIGNED +#define CC1310_LAUNCHXL_PWMPIN5 PIN_UNASSIGNED +#define CC1310_LAUNCHXL_PWMPIN6 PIN_UNASSIGNED +#define CC1310_LAUNCHXL_PWMPIN7 PIN_UNASSIGNED /* SPI */ -#define CC1310_LAUNCHXL_SPI_FLASH_CS IOID_20 -#define CC1310_LAUNCHXL_FLASH_CS_ON 0 -#define CC1310_LAUNCHXL_FLASH_CS_OFF 1 +#define CC1310_LAUNCHXL_SPI_FLASH_CS IOID_20 +#define CC1310_LAUNCHXL_FLASH_CS_ON 0 +#define CC1310_LAUNCHXL_FLASH_CS_OFF 1 /* SPI Board */ -#define CC1310_LAUNCHXL_SPI0_MISO IOID_8 /* RF1.20 */ -#define CC1310_LAUNCHXL_SPI0_MOSI IOID_9 /* RF1.18 */ -#define CC1310_LAUNCHXL_SPI0_CLK IOID_10 /* RF1.16 */ -#define CC1310_LAUNCHXL_SPI0_CSN IOID_11 -#define CC1310_LAUNCHXL_SPI1_MISO PIN_UNASSIGNED -#define CC1310_LAUNCHXL_SPI1_MOSI PIN_UNASSIGNED -#define CC1310_LAUNCHXL_SPI1_CLK PIN_UNASSIGNED -#define CC1310_LAUNCHXL_SPI1_CSN PIN_UNASSIGNED +#define CC1310_LAUNCHXL_SPI0_MISO IOID_8 /* RF1.20 */ +#define CC1310_LAUNCHXL_SPI0_MOSI IOID_9 /* RF1.18 */ +#define CC1310_LAUNCHXL_SPI0_CLK IOID_10 /* RF1.16 */ +#define CC1310_LAUNCHXL_SPI0_CSN IOID_11 +#define CC1310_LAUNCHXL_SPI1_MISO PIN_UNASSIGNED +#define CC1310_LAUNCHXL_SPI1_MOSI PIN_UNASSIGNED +#define CC1310_LAUNCHXL_SPI1_CLK PIN_UNASSIGNED +#define CC1310_LAUNCHXL_SPI1_CSN PIN_UNASSIGNED /* UART Board */ -#define CC1310_LAUNCHXL_UART_RX IOID_2 /* RXD */ -#define CC1310_LAUNCHXL_UART_TX IOID_3 /* TXD */ -#define CC1310_LAUNCHXL_UART_CTS IOID_19 /* CTS */ -#define CC1310_LAUNCHXL_UART_RTS IOID_18 /* RTS */ +#define CC1310_LAUNCHXL_UART_RX IOID_2 /* RXD */ +#define CC1310_LAUNCHXL_UART_TX IOID_3 /* TXD */ +#define CC1310_LAUNCHXL_UART_CTS IOID_19 /* CTS */ +#define CC1310_LAUNCHXL_UART_RTS IOID_18 /* RTS */ /*! * @brief Initialize the general board specific settings @@ -466,7 +466,6 @@ typedef enum CC1310_LAUNCHXL_WatchdogName CC1310_LAUNCHXL_WATCHDOGCOUNT } CC1310_LAUNCHXL_WatchdogName; - #ifdef __cplusplus } #endif diff --git a/examples/knx-cc1310/RTT/SEGGER_RTT.h b/examples/knx-cc1310/RTT/SEGGER_RTT.h index 96a2429..99b1986 100644 --- a/examples/knx-cc1310/RTT/SEGGER_RTT.h +++ b/examples/knx-cc1310/RTT/SEGGER_RTT.h @@ -55,93 +55,91 @@ Revision: $Rev: 20159 $ #include "SEGGER_RTT_Conf.h" - - /********************************************************************* -* -* Defines, defaults -* -********************************************************************** -*/ + * + * Defines, defaults + * + ********************************************************************** + */ #ifndef RTT_USE_ASM - #if (defined __SES_ARM) // SEGGER Embedded Studio - #define _CC_HAS_RTT_ASM_SUPPORT 1 - #elif (defined __CROSSWORKS_ARM) // Rowley Crossworks - #define _CC_HAS_RTT_ASM_SUPPORT 1 - #elif (defined __ARMCC_VERSION) - #define _CC_HAS_RTT_ASM_SUPPORT 0 - #elif (defined __GNUC__) // GCC - #define _CC_HAS_RTT_ASM_SUPPORT 1 - #elif (defined __clang__) // Clang compiler - #define _CC_HAS_RTT_ASM_SUPPORT 1 - #elif ((defined __IASMARM__) || (defined __ICCARM__)) // IAR assembler/compiler - #define _CC_HAS_RTT_ASM_SUPPORT 1 - #else - #define _CC_HAS_RTT_ASM_SUPPORT 0 - #endif - #if ((defined __IASMARM__) || (defined __ICCARM__)) // IAR assembler/compiler - // - // IAR assembler / compiler - // - #if (defined __ARM7M__) // Needed for old versions that do not know the define yet - #if (__CORE__ == __ARM7M__) // Cortex-M3 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #endif - #endif - #if (defined __ARM7EM__) // Needed for old versions that do not know the define yet - #if (__CORE__ == __ARM7EM__) // Cortex-M4/M7 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() asm("DMB"); - #endif - #endif - #if (defined __ARM8M_BASELINE__) // Needed for old versions that do not know the define yet - #if (__CORE__ == __ARM8M_BASELINE__) // Cortex-M23 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() asm("DMB"); - #endif - #endif - #if (defined __ARM8M_MAINLINE__) // Needed for old versions that do not know the define yet - #if (__CORE__ == __ARM8M_MAINLINE__) // Cortex-M33 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() asm("DMB"); - #endif - #endif - #else - // - // GCC / Clang - // - #if (defined __ARM_ARCH_7M__) // Cortex-M3 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33 - #define _CORE_HAS_RTT_ASM_SUPPORT 1 - #define _CORE_NEEDS_DMB 1 - #define RTT__DMB() __asm volatile ("dmb\n" : : :); - #else - #define _CORE_HAS_RTT_ASM_SUPPORT 0 - #endif - #endif - // - // If IDE and core support the ASM version, enable ASM version by default - // - #ifndef _CORE_HAS_RTT_ASM_SUPPORT - #define _CORE_HAS_RTT_ASM_SUPPORT 0 // Default for unknown cores - #endif - #if (_CC_HAS_RTT_ASM_SUPPORT && _CORE_HAS_RTT_ASM_SUPPORT) - #define RTT_USE_ASM (1) - #else - #define RTT_USE_ASM (0) - #endif +#if (defined __SES_ARM) // SEGGER Embedded Studio +#define _CC_HAS_RTT_ASM_SUPPORT 1 +#elif (defined __CROSSWORKS_ARM) // Rowley Crossworks +#define _CC_HAS_RTT_ASM_SUPPORT 1 +#elif (defined __ARMCC_VERSION) +#define _CC_HAS_RTT_ASM_SUPPORT 0 +#elif (defined __GNUC__) // GCC +#define _CC_HAS_RTT_ASM_SUPPORT 1 +#elif (defined __clang__) // Clang compiler +#define _CC_HAS_RTT_ASM_SUPPORT 1 +#elif ((defined __IASMARM__) || (defined __ICCARM__)) // IAR assembler/compiler +#define _CC_HAS_RTT_ASM_SUPPORT 1 +#else +#define _CC_HAS_RTT_ASM_SUPPORT 0 +#endif +#if ((defined __IASMARM__) || (defined __ICCARM__)) // IAR assembler/compiler +// +// IAR assembler / compiler +// +#if (defined __ARM7M__) // Needed for old versions that do not know the define yet +#if (__CORE__ == __ARM7M__) // Cortex-M3 +#define _CORE_HAS_RTT_ASM_SUPPORT 1 +#endif +#endif +#if (defined __ARM7EM__) // Needed for old versions that do not know the define yet +#if (__CORE__ == __ARM7EM__) // Cortex-M4/M7 +#define _CORE_HAS_RTT_ASM_SUPPORT 1 +#define _CORE_NEEDS_DMB 1 +#define RTT__DMB() asm("DMB"); +#endif +#endif +#if (defined __ARM8M_BASELINE__) // Needed for old versions that do not know the define yet +#if (__CORE__ == __ARM8M_BASELINE__) // Cortex-M23 +#define _CORE_HAS_RTT_ASM_SUPPORT 1 +#define _CORE_NEEDS_DMB 1 +#define RTT__DMB() asm("DMB"); +#endif +#endif +#if (defined __ARM8M_MAINLINE__) // Needed for old versions that do not know the define yet +#if (__CORE__ == __ARM8M_MAINLINE__) // Cortex-M33 +#define _CORE_HAS_RTT_ASM_SUPPORT 1 +#define _CORE_NEEDS_DMB 1 +#define RTT__DMB() asm("DMB"); +#endif +#endif +#else +// +// GCC / Clang +// +#if (defined __ARM_ARCH_7M__) // Cortex-M3 +#define _CORE_HAS_RTT_ASM_SUPPORT 1 +#elif (defined __ARM_ARCH_7EM__) // Cortex-M4/M7 +#define _CORE_HAS_RTT_ASM_SUPPORT 1 +#define _CORE_NEEDS_DMB 1 +#define RTT__DMB() __asm volatile("dmb\n" : : :); +#elif (defined __ARM_ARCH_8M_BASE__) // Cortex-M23 +#define _CORE_HAS_RTT_ASM_SUPPORT 1 +#define _CORE_NEEDS_DMB 1 +#define RTT__DMB() __asm volatile("dmb\n" : : :); +#elif (defined __ARM_ARCH_8M_MAIN__) // Cortex-M33 +#define _CORE_HAS_RTT_ASM_SUPPORT 1 +#define _CORE_NEEDS_DMB 1 +#define RTT__DMB() __asm volatile("dmb\n" : : :); +#else +#define _CORE_HAS_RTT_ASM_SUPPORT 0 +#endif +#endif +// +// If IDE and core support the ASM version, enable ASM version by default +// +#ifndef _CORE_HAS_RTT_ASM_SUPPORT +#define _CORE_HAS_RTT_ASM_SUPPORT 0 // Default for unknown cores +#endif +#if (_CC_HAS_RTT_ASM_SUPPORT && _CORE_HAS_RTT_ASM_SUPPORT) +#define RTT_USE_ASM (1) +#else +#define RTT_USE_ASM (0) +#endif #endif // @@ -150,34 +148,34 @@ Revision: $Rev: 20159 $ // Needed for: Cortex-M7, Cortex-M23, Cortex-M33 // #ifndef _CORE_NEEDS_DMB - #define _CORE_NEEDS_DMB 0 +#define _CORE_NEEDS_DMB 0 #endif #ifndef RTT__DMB - #if _CORE_NEEDS_DMB - #error "Don't know how to place inline assembly for DMB" - #else - #define RTT__DMB() - #endif +#if _CORE_NEEDS_DMB +#error "Don't know how to place inline assembly for DMB" +#else +#define RTT__DMB() +#endif #endif -#ifndef SEGGER_RTT_ASM // defined when SEGGER_RTT.h is included from assembly file -#include +#ifndef SEGGER_RTT_ASM // defined when SEGGER_RTT.h is included from assembly file #include +#include /********************************************************************* -* -* Defines, fixed -* -********************************************************************** -*/ + * + * Defines, fixed + * + ********************************************************************** + */ /********************************************************************* -* -* Types -* -********************************************************************** -*/ + * + * Types + * + ********************************************************************** + */ // // Description for a circular buffer (also called "ring buffer") @@ -185,12 +183,12 @@ Revision: $Rev: 20159 $ // typedef struct { - const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" - char* pBuffer; // Pointer to start of buffer - unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. - unsigned WrOff; // Position of next item to be written by either target. - volatile unsigned RdOff; // Position of next item to be read by host. Must be volatile since it may be modified by host. - unsigned Flags; // Contains configuration flags + const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" + char* pBuffer; // Pointer to start of buffer + unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. + unsigned WrOff; // Position of next item to be written by either target. + volatile unsigned RdOff; // Position of next item to be read by host. Must be volatile since it may be modified by host. + unsigned Flags; // Contains configuration flags } SEGGER_RTT_BUFFER_UP; // @@ -199,12 +197,12 @@ typedef struct // typedef struct { - const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" - char* pBuffer; // Pointer to start of buffer - unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. - volatile unsigned WrOff; // Position of next item to be written by host. Must be volatile since it may be modified by host. - unsigned RdOff; // Position of next item to be read by target (down-buffer). - unsigned Flags; // Contains configuration flags + const char* sName; // Optional name. Standard names so far are: "Terminal", "SysView", "J-Scope_t4i4" + char* pBuffer; // Pointer to start of buffer + unsigned SizeOfBuffer; // Buffer size in bytes. Note that one byte is lost, as this implementation does not fill up the buffer in order to avoid the problem of being unable to distinguish between full and empty. + volatile unsigned WrOff; // Position of next item to be written by host. Must be volatile since it may be modified by host. + unsigned RdOff; // Position of next item to be read by target (down-buffer). + unsigned Flags; // Contains configuration flags } SEGGER_RTT_BUFFER_DOWN; // @@ -214,94 +212,94 @@ typedef struct // typedef struct { - char acID[16]; // Initialized to "SEGGER RTT" - int MaxNumUpBuffers; // Initialized to SEGGER_RTT_MAX_NUM_UP_BUFFERS (type. 2) - int MaxNumDownBuffers; // Initialized to SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (type. 2) - SEGGER_RTT_BUFFER_UP aUp[SEGGER_RTT_MAX_NUM_UP_BUFFERS]; // Up buffers, transferring information up from target via debug probe to host - SEGGER_RTT_BUFFER_DOWN aDown[SEGGER_RTT_MAX_NUM_DOWN_BUFFERS]; // Down buffers, transferring information down from host via debug probe to target + char acID[16]; // Initialized to "SEGGER RTT" + int MaxNumUpBuffers; // Initialized to SEGGER_RTT_MAX_NUM_UP_BUFFERS (type. 2) + int MaxNumDownBuffers; // Initialized to SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (type. 2) + SEGGER_RTT_BUFFER_UP aUp[SEGGER_RTT_MAX_NUM_UP_BUFFERS]; // Up buffers, transferring information up from target via debug probe to host + SEGGER_RTT_BUFFER_DOWN aDown[SEGGER_RTT_MAX_NUM_DOWN_BUFFERS]; // Down buffers, transferring information down from host via debug probe to target } SEGGER_RTT_CB; /********************************************************************* -* -* Global data -* -********************************************************************** -*/ + * + * Global data + * + ********************************************************************** + */ extern SEGGER_RTT_CB _SEGGER_RTT; /********************************************************************* -* -* RTT API functions -* -********************************************************************** -*/ + * + * RTT API functions + * + ********************************************************************** + */ #ifdef __cplusplus extern "C" { #endif -int SEGGER_RTT_AllocDownBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); -int SEGGER_RTT_AllocUpBuffer (const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); -int SEGGER_RTT_ConfigUpBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); -int SEGGER_RTT_ConfigDownBuffer (unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); -int SEGGER_RTT_GetKey (void); -unsigned SEGGER_RTT_HasData (unsigned BufferIndex); -int SEGGER_RTT_HasKey (void); -unsigned SEGGER_RTT_HasDataUp (unsigned BufferIndex); -void SEGGER_RTT_Init (void); -unsigned SEGGER_RTT_Read (unsigned BufferIndex, void* pBuffer, unsigned BufferSize); -unsigned SEGGER_RTT_ReadNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize); -int SEGGER_RTT_SetNameDownBuffer (unsigned BufferIndex, const char* sName); -int SEGGER_RTT_SetNameUpBuffer (unsigned BufferIndex, const char* sName); -int SEGGER_RTT_SetFlagsDownBuffer (unsigned BufferIndex, unsigned Flags); -int SEGGER_RTT_SetFlagsUpBuffer (unsigned BufferIndex, unsigned Flags); -int SEGGER_RTT_WaitKey (void); -unsigned SEGGER_RTT_Write (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_WriteNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_ASM_WriteSkipNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_WriteString (unsigned BufferIndex, const char* s); -void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_PutChar (unsigned BufferIndex, char c); -unsigned SEGGER_RTT_PutCharSkip (unsigned BufferIndex, char c); -unsigned SEGGER_RTT_PutCharSkipNoLock (unsigned BufferIndex, char c); -unsigned SEGGER_RTT_GetAvailWriteSpace (unsigned BufferIndex); -unsigned SEGGER_RTT_GetBytesInBuffer (unsigned BufferIndex); +int SEGGER_RTT_AllocDownBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_AllocUpBuffer(const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_ConfigUpBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_ConfigDownBuffer(unsigned BufferIndex, const char* sName, void* pBuffer, unsigned BufferSize, unsigned Flags); +int SEGGER_RTT_GetKey(void); +unsigned SEGGER_RTT_HasData(unsigned BufferIndex); +int SEGGER_RTT_HasKey(void); +unsigned SEGGER_RTT_HasDataUp(unsigned BufferIndex); +void SEGGER_RTT_Init(void); +unsigned SEGGER_RTT_Read(unsigned BufferIndex, void* pBuffer, unsigned BufferSize); +unsigned SEGGER_RTT_ReadNoLock(unsigned BufferIndex, void* pData, unsigned BufferSize); +int SEGGER_RTT_SetNameDownBuffer(unsigned BufferIndex, const char* sName); +int SEGGER_RTT_SetNameUpBuffer(unsigned BufferIndex, const char* sName); +int SEGGER_RTT_SetFlagsDownBuffer(unsigned BufferIndex, unsigned Flags); +int SEGGER_RTT_SetFlagsUpBuffer(unsigned BufferIndex, unsigned Flags); +int SEGGER_RTT_WaitKey(void); +unsigned SEGGER_RTT_Write(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_ASM_WriteSkipNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteString(unsigned BufferIndex, const char* s); +void SEGGER_RTT_WriteWithOverwriteNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_PutChar(unsigned BufferIndex, char c); +unsigned SEGGER_RTT_PutCharSkip(unsigned BufferIndex, char c); +unsigned SEGGER_RTT_PutCharSkipNoLock(unsigned BufferIndex, char c); +unsigned SEGGER_RTT_GetAvailWriteSpace(unsigned BufferIndex); +unsigned SEGGER_RTT_GetBytesInBuffer(unsigned BufferIndex); // // Function macro for performance optimization // -#define SEGGER_RTT_HASDATA(n) (_SEGGER_RTT.aDown[n].WrOff - _SEGGER_RTT.aDown[n].RdOff) +#define SEGGER_RTT_HASDATA(n) (_SEGGER_RTT.aDown[n].WrOff - _SEGGER_RTT.aDown[n].RdOff) #if RTT_USE_ASM -#define SEGGER_RTT_WriteSkipNoLock SEGGER_RTT_ASM_WriteSkipNoLock +#define SEGGER_RTT_WriteSkipNoLock SEGGER_RTT_ASM_WriteSkipNoLock #endif /********************************************************************* -* -* RTT transfer functions to send RTT data via other channels. -* -********************************************************************** -*/ -unsigned SEGGER_RTT_ReadUpBuffer (unsigned BufferIndex, void* pBuffer, unsigned BufferSize); -unsigned SEGGER_RTT_ReadUpBufferNoLock (unsigned BufferIndex, void* pData, unsigned BufferSize); -unsigned SEGGER_RTT_WriteDownBuffer (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -unsigned SEGGER_RTT_WriteDownBufferNoLock (unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); + * + * RTT transfer functions to send RTT data via other channels. + * + ********************************************************************** + */ +unsigned SEGGER_RTT_ReadUpBuffer(unsigned BufferIndex, void* pBuffer, unsigned BufferSize); +unsigned SEGGER_RTT_ReadUpBufferNoLock(unsigned BufferIndex, void* pData, unsigned BufferSize); +unsigned SEGGER_RTT_WriteDownBuffer(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); +unsigned SEGGER_RTT_WriteDownBufferNoLock(unsigned BufferIndex, const void* pBuffer, unsigned NumBytes); -#define SEGGER_RTT_HASDATA_UP(n) (_SEGGER_RTT.aUp[n].WrOff - _SEGGER_RTT.aUp[n].RdOff) +#define SEGGER_RTT_HASDATA_UP(n) (_SEGGER_RTT.aUp[n].WrOff - _SEGGER_RTT.aUp[n].RdOff) /********************************************************************* -* -* RTT "Terminal" API functions -* -********************************************************************** -*/ -int SEGGER_RTT_SetTerminal (unsigned char TerminalId); -int SEGGER_RTT_TerminalOut (unsigned char TerminalId, const char* s); + * + * RTT "Terminal" API functions + * + ********************************************************************** + */ +int SEGGER_RTT_SetTerminal(unsigned char TerminalId); +int SEGGER_RTT_TerminalOut(unsigned char TerminalId, const char* s); /********************************************************************* -* -* RTT printf functions (require SEGGER_RTT_printf.c) -* -********************************************************************** -*/ + * + * RTT printf functions (require SEGGER_RTT_printf.c) + * + ********************************************************************** + */ int SEGGER_RTT_printf(unsigned BufferIndex, const char* sFormat, ...); int SEGGER_RTT_vprintf(unsigned BufferIndex, const char* sFormat, va_list* pParamList); @@ -312,63 +310,62 @@ int SEGGER_RTT_vprintf(unsigned BufferIndex, const char* sFormat, va_list* pPara #endif // ifndef(SEGGER_RTT_ASM) /********************************************************************* -* -* Defines -* -********************************************************************** -*/ + * + * Defines + * + ********************************************************************** + */ // // Operating modes. Define behavior if buffer is full (not enough space for entire message) // -#define SEGGER_RTT_MODE_NO_BLOCK_SKIP (0) // Skip. Do not block, output nothing. (Default) -#define SEGGER_RTT_MODE_NO_BLOCK_TRIM (1) // Trim: Do not block, output as much as fits. -#define SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL (2) // Block: Wait until there is space in the buffer. -#define SEGGER_RTT_MODE_MASK (3) +#define SEGGER_RTT_MODE_NO_BLOCK_SKIP (0) // Skip. Do not block, output nothing. (Default) +#define SEGGER_RTT_MODE_NO_BLOCK_TRIM (1) // Trim: Do not block, output as much as fits. +#define SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL (2) // Block: Wait until there is space in the buffer. +#define SEGGER_RTT_MODE_MASK (3) // // Control sequences, based on ANSI. // Can be used to control color, and clear the screen // -#define RTT_CTRL_RESET "\x1B[0m" // Reset to default colors -#define RTT_CTRL_CLEAR "\x1B[2J" // Clear screen, reposition cursor to top left +#define RTT_CTRL_RESET "\x1B[0m" // Reset to default colors +#define RTT_CTRL_CLEAR "\x1B[2J" // Clear screen, reposition cursor to top left -#define RTT_CTRL_TEXT_BLACK "\x1B[2;30m" -#define RTT_CTRL_TEXT_RED "\x1B[2;31m" -#define RTT_CTRL_TEXT_GREEN "\x1B[2;32m" -#define RTT_CTRL_TEXT_YELLOW "\x1B[2;33m" -#define RTT_CTRL_TEXT_BLUE "\x1B[2;34m" -#define RTT_CTRL_TEXT_MAGENTA "\x1B[2;35m" -#define RTT_CTRL_TEXT_CYAN "\x1B[2;36m" -#define RTT_CTRL_TEXT_WHITE "\x1B[2;37m" +#define RTT_CTRL_TEXT_BLACK "\x1B[2;30m" +#define RTT_CTRL_TEXT_RED "\x1B[2;31m" +#define RTT_CTRL_TEXT_GREEN "\x1B[2;32m" +#define RTT_CTRL_TEXT_YELLOW "\x1B[2;33m" +#define RTT_CTRL_TEXT_BLUE "\x1B[2;34m" +#define RTT_CTRL_TEXT_MAGENTA "\x1B[2;35m" +#define RTT_CTRL_TEXT_CYAN "\x1B[2;36m" +#define RTT_CTRL_TEXT_WHITE "\x1B[2;37m" -#define RTT_CTRL_TEXT_BRIGHT_BLACK "\x1B[1;30m" -#define RTT_CTRL_TEXT_BRIGHT_RED "\x1B[1;31m" -#define RTT_CTRL_TEXT_BRIGHT_GREEN "\x1B[1;32m" -#define RTT_CTRL_TEXT_BRIGHT_YELLOW "\x1B[1;33m" -#define RTT_CTRL_TEXT_BRIGHT_BLUE "\x1B[1;34m" -#define RTT_CTRL_TEXT_BRIGHT_MAGENTA "\x1B[1;35m" -#define RTT_CTRL_TEXT_BRIGHT_CYAN "\x1B[1;36m" -#define RTT_CTRL_TEXT_BRIGHT_WHITE "\x1B[1;37m" +#define RTT_CTRL_TEXT_BRIGHT_BLACK "\x1B[1;30m" +#define RTT_CTRL_TEXT_BRIGHT_RED "\x1B[1;31m" +#define RTT_CTRL_TEXT_BRIGHT_GREEN "\x1B[1;32m" +#define RTT_CTRL_TEXT_BRIGHT_YELLOW "\x1B[1;33m" +#define RTT_CTRL_TEXT_BRIGHT_BLUE "\x1B[1;34m" +#define RTT_CTRL_TEXT_BRIGHT_MAGENTA "\x1B[1;35m" +#define RTT_CTRL_TEXT_BRIGHT_CYAN "\x1B[1;36m" +#define RTT_CTRL_TEXT_BRIGHT_WHITE "\x1B[1;37m" -#define RTT_CTRL_BG_BLACK "\x1B[24;40m" -#define RTT_CTRL_BG_RED "\x1B[24;41m" -#define RTT_CTRL_BG_GREEN "\x1B[24;42m" -#define RTT_CTRL_BG_YELLOW "\x1B[24;43m" -#define RTT_CTRL_BG_BLUE "\x1B[24;44m" -#define RTT_CTRL_BG_MAGENTA "\x1B[24;45m" -#define RTT_CTRL_BG_CYAN "\x1B[24;46m" -#define RTT_CTRL_BG_WHITE "\x1B[24;47m" - -#define RTT_CTRL_BG_BRIGHT_BLACK "\x1B[4;40m" -#define RTT_CTRL_BG_BRIGHT_RED "\x1B[4;41m" -#define RTT_CTRL_BG_BRIGHT_GREEN "\x1B[4;42m" -#define RTT_CTRL_BG_BRIGHT_YELLOW "\x1B[4;43m" -#define RTT_CTRL_BG_BRIGHT_BLUE "\x1B[4;44m" -#define RTT_CTRL_BG_BRIGHT_MAGENTA "\x1B[4;45m" -#define RTT_CTRL_BG_BRIGHT_CYAN "\x1B[4;46m" -#define RTT_CTRL_BG_BRIGHT_WHITE "\x1B[4;47m" +#define RTT_CTRL_BG_BLACK "\x1B[24;40m" +#define RTT_CTRL_BG_RED "\x1B[24;41m" +#define RTT_CTRL_BG_GREEN "\x1B[24;42m" +#define RTT_CTRL_BG_YELLOW "\x1B[24;43m" +#define RTT_CTRL_BG_BLUE "\x1B[24;44m" +#define RTT_CTRL_BG_MAGENTA "\x1B[24;45m" +#define RTT_CTRL_BG_CYAN "\x1B[24;46m" +#define RTT_CTRL_BG_WHITE "\x1B[24;47m" +#define RTT_CTRL_BG_BRIGHT_BLACK "\x1B[4;40m" +#define RTT_CTRL_BG_BRIGHT_RED "\x1B[4;41m" +#define RTT_CTRL_BG_BRIGHT_GREEN "\x1B[4;42m" +#define RTT_CTRL_BG_BRIGHT_YELLOW "\x1B[4;43m" +#define RTT_CTRL_BG_BRIGHT_BLUE "\x1B[4;44m" +#define RTT_CTRL_BG_BRIGHT_MAGENTA "\x1B[4;45m" +#define RTT_CTRL_BG_BRIGHT_CYAN "\x1B[4;46m" +#define RTT_CTRL_BG_BRIGHT_WHITE "\x1B[4;47m" #endif diff --git a/examples/knx-cc1310/RTT/SEGGER_RTT_Conf.h b/examples/knx-cc1310/RTT/SEGGER_RTT_Conf.h index 2a155c8..d2682be 100644 --- a/examples/knx-cc1310/RTT/SEGGER_RTT_Conf.h +++ b/examples/knx-cc1310/RTT/SEGGER_RTT_Conf.h @@ -54,60 +54,60 @@ Revision: $Rev: 18601 $ #define SEGGER_RTT_CONF_H #ifdef __IAR_SYSTEMS_ICC__ - #include +#include #endif /********************************************************************* -* -* Defines, configurable -* -********************************************************************** -*/ -#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS - #define SEGGER_RTT_MAX_NUM_UP_BUFFERS (3) // Max. number of up-buffers (T->H) available on this target (Default: 3) + * + * Defines, configurable + * + ********************************************************************** + */ +#ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS +#define SEGGER_RTT_MAX_NUM_UP_BUFFERS (3) // Max. number of up-buffers (T->H) available on this target (Default: 3) #endif -#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS - #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3) +#ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS +#define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3) #endif -#ifndef BUFFER_SIZE_UP - #define BUFFER_SIZE_UP (128) // Size of the buffer for terminal output of target, up to host (Default: 1k) +#ifndef BUFFER_SIZE_UP +#define BUFFER_SIZE_UP (128) // Size of the buffer for terminal output of target, up to host (Default: 1k) #endif -#ifndef BUFFER_SIZE_DOWN - #define BUFFER_SIZE_DOWN (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) +#ifndef BUFFER_SIZE_DOWN +#define BUFFER_SIZE_DOWN (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16) #endif -#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE - #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) +#ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE +#define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64) #endif -#ifndef SEGGER_RTT_MODE_DEFAULT - #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0) +#ifndef SEGGER_RTT_MODE_DEFAULT +#define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0) #endif /********************************************************************* -* -* RTT memcpy configuration -* -* memcpy() is good for large amounts of data, -* but the overhead is big for small amounts, which are usually stored via RTT. -* With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. -* -* SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. -* This is may be required with memory access restrictions, -* such as on Cortex-A devices with MMU. -*/ -#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP - #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop + * + * RTT memcpy configuration + * + * memcpy() is good for large amounts of data, + * but the overhead is big for small amounts, which are usually stored via RTT. + * With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead. + * + * SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions. + * This is may be required with memory access restrictions, + * such as on Cortex-A devices with MMU. + */ +#ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP +#define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop #endif // // Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets // -//#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) +// #if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__)) // #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes)) -//#endif +// #endif // // Target is not allowed to perform other RTT operations while string still has not been stored completely. @@ -123,96 +123,96 @@ Revision: $Rev: 18601 $ // In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC // or define SEGGER_RTT_LOCK() to completely disable interrupts. // -#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) +#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY +#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20) #endif /********************************************************************* -* -* RTT lock configuration for SEGGER Embedded Studio, -* Rowley CrossStudio and GCC -*/ -#if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32)) + * + * RTT lock configuration for SEGGER Embedded Studio, + * Rowley CrossStudio and GCC + */ +#if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined(__CC_ARM) && !defined(WIN32)) #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__)) -#define SEGGER_RTT_LOCK() { \ - unsigned int LockState; \ - __asm volatile ("mrs %0, primask \n\t" \ - "movs r1, $1 \n\t" \ - "msr primask, r1 \n\t" \ - : "=r" (LockState) \ - : \ - : "r1" \ - ); +#define SEGGER_RTT_LOCK() \ + { \ + unsigned int LockState; \ + __asm volatile("mrs %0, primask \n\t" \ + "movs r1, $1 \n\t" \ + "msr primask, r1 \n\t" \ + : "=r"(LockState) \ + : \ + : "r1"); -#define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \ - : \ - : "r" (LockState) \ - : \ - ); \ -} +#define SEGGER_RTT_UNLOCK() \ + __asm volatile("msr primask, %0 \n\t" \ + : \ + : "r"(LockState) \ + :); \ + } #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)) -#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) +#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY +#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) #endif -#define SEGGER_RTT_LOCK() { \ - unsigned int LockState; \ - __asm volatile ("mrs %0, basepri \n\t" \ - "mov r1, %1 \n\t" \ - "msr basepri, r1 \n\t" \ - : "=r" (LockState) \ - : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ - : "r1" \ - ); +#define SEGGER_RTT_LOCK() \ + { \ + unsigned int LockState; \ + __asm volatile("mrs %0, basepri \n\t" \ + "mov r1, %1 \n\t" \ + "msr basepri, r1 \n\t" \ + : "=r"(LockState) \ + : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \ + : "r1"); -#define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \ - : \ - : "r" (LockState) \ - : \ - ); \ -} +#define SEGGER_RTT_UNLOCK() \ + __asm volatile("msr basepri, %0 \n\t" \ + : \ + : "r"(LockState) \ + :); \ + } #elif defined(__ARM_ARCH_7A__) -#define SEGGER_RTT_LOCK() { \ - unsigned int LockState; \ - __asm volatile ("mrs r1, CPSR \n\t" \ - "mov %0, r1 \n\t" \ - "orr r1, r1, #0xC0 \n\t" \ - "msr CPSR_c, r1 \n\t" \ - : "=r" (LockState) \ - : \ - : "r1" \ - ); +#define SEGGER_RTT_LOCK() \ + { \ + unsigned int LockState; \ + __asm volatile("mrs r1, CPSR \n\t" \ + "mov %0, r1 \n\t" \ + "orr r1, r1, #0xC0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : "=r"(LockState) \ + : \ + : "r1"); -#define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \ - "mrs r1, CPSR \n\t" \ - "bic r1, r1, #0xC0 \n\t" \ - "and r0, r0, #0xC0 \n\t" \ - "orr r1, r1, r0 \n\t" \ - "msr CPSR_c, r1 \n\t" \ - : \ - : "r" (LockState) \ - : "r0", "r1" \ - ); \ -} +#define SEGGER_RTT_UNLOCK() \ + __asm volatile("mov r0, %0 \n\t" \ + "mrs r1, CPSR \n\t" \ + "bic r1, r1, #0xC0 \n\t" \ + "and r0, r0, #0xC0 \n\t" \ + "orr r1, r1, r0 \n\t" \ + "msr CPSR_c, r1 \n\t" \ + : \ + : "r"(LockState) \ + : "r0", "r1"); \ + } #elif defined(__riscv) || defined(__riscv_xlen) -#define SEGGER_RTT_LOCK() { \ - unsigned int LockState; \ - __asm volatile ("csrr %0, mstatus \n\t" \ - "csrci mstatus, 8 \n\t" \ - "andi %0, %0, 8 \n\t" \ - : "=r" (LockState) \ - : \ - : \ - ); +#define SEGGER_RTT_LOCK() \ + { \ + unsigned int LockState; \ + __asm volatile("csrr %0, mstatus \n\t" \ + "csrci mstatus, 8 \n\t" \ + "andi %0, %0, 8 \n\t" \ + : "=r"(LockState) \ + : \ + :); -#define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \ - "or %0, %0, a1 \n\t" \ - "csrs mstatus, %0 \n\t" \ - : \ - : "r" (LockState) \ - : "a1" \ - ); \ -} +#define SEGGER_RTT_UNLOCK() \ + __asm volatile("csrr a1, mstatus \n\t" \ + "or %0, %0, a1 \n\t" \ + "csrs mstatus, %0 \n\t" \ + : \ + : "r"(LockState) \ + : "a1"); \ + } #else #define SEGGER_RTT_LOCK() #define SEGGER_RTT_UNLOCK() @@ -220,164 +220,184 @@ Revision: $Rev: 18601 $ #endif /********************************************************************* -* -* RTT lock configuration for IAR EWARM -*/ + * + * RTT lock configuration for IAR EWARM + */ #ifdef __ICCARM__ -#if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) || \ - (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) -#define SEGGER_RTT_LOCK() { \ - unsigned int LockState; \ - LockState = __get_PRIMASK(); \ +#if (defined(__ARM6M__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__)) +#define SEGGER_RTT_LOCK() \ + { \ + unsigned int LockState; \ + LockState = __get_PRIMASK(); \ __set_PRIMASK(1); -#define SEGGER_RTT_UNLOCK() __set_PRIMASK(LockState); \ +#define SEGGER_RTT_UNLOCK() \ + __set_PRIMASK(LockState); \ } -#elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \ - (defined (__ARM7M__) && (__CORE__ == __ARM7M__)) || \ - (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ - (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) -#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) +#elif (defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \ + (defined(__ARM7M__) && (__CORE__ == __ARM7M__)) || \ + (defined(__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \ + (defined(__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) +#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY +#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) #endif -#define SEGGER_RTT_LOCK() { \ - unsigned int LockState; \ - LockState = __get_BASEPRI(); \ +#define SEGGER_RTT_LOCK() \ + { \ + unsigned int LockState; \ + LockState = __get_BASEPRI(); \ __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); -#define SEGGER_RTT_UNLOCK() __set_BASEPRI(LockState); \ +#define SEGGER_RTT_UNLOCK() \ + __set_BASEPRI(LockState); \ } #endif #endif /********************************************************************* -* -* RTT lock configuration for IAR RX -*/ + * + * RTT lock configuration for IAR RX + */ #ifdef __ICCRX__ -#define SEGGER_RTT_LOCK() { \ - unsigned long LockState; \ - LockState = __get_interrupt_state(); \ +#define SEGGER_RTT_LOCK() \ + { \ + unsigned long LockState; \ + LockState = __get_interrupt_state(); \ __disable_interrupt(); -#define SEGGER_RTT_UNLOCK() __set_interrupt_state(LockState); \ +#define SEGGER_RTT_UNLOCK() \ + __set_interrupt_state(LockState); \ } #endif /********************************************************************* -* -* RTT lock configuration for IAR RL78 -*/ + * + * RTT lock configuration for IAR RL78 + */ #ifdef __ICCRL78__ -#define SEGGER_RTT_LOCK() { \ - __istate_t LockState; \ - LockState = __get_interrupt_state(); \ +#define SEGGER_RTT_LOCK() \ + { \ + __istate_t LockState; \ + LockState = __get_interrupt_state(); \ __disable_interrupt(); -#define SEGGER_RTT_UNLOCK() __set_interrupt_state(LockState); \ +#define SEGGER_RTT_UNLOCK() \ + __set_interrupt_state(LockState); \ } #endif /********************************************************************* -* -* RTT lock configuration for KEIL ARM -*/ + * + * RTT lock configuration for KEIL ARM + */ #ifdef __CC_ARM #if (defined __TARGET_ARCH_6S_M) -#define SEGGER_RTT_LOCK() { \ - unsigned int LockState; \ - register unsigned char PRIMASK __asm( "primask"); \ - LockState = PRIMASK; \ - PRIMASK = 1u; \ +#define SEGGER_RTT_LOCK() \ + { \ + unsigned int LockState; \ + register unsigned char PRIMASK __asm("primask"); \ + LockState = PRIMASK; \ + PRIMASK = 1u; \ __schedule_barrier(); -#define SEGGER_RTT_UNLOCK() PRIMASK = LockState; \ - __schedule_barrier(); \ +#define SEGGER_RTT_UNLOCK() \ + PRIMASK = LockState; \ + __schedule_barrier(); \ } #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) -#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) +#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY +#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) #endif -#define SEGGER_RTT_LOCK() { \ - unsigned int LockState; \ - register unsigned char BASEPRI __asm( "basepri"); \ - LockState = BASEPRI; \ - BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ +#define SEGGER_RTT_LOCK() \ + { \ + unsigned int LockState; \ + register unsigned char BASEPRI __asm("basepri"); \ + LockState = BASEPRI; \ + BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \ __schedule_barrier(); -#define SEGGER_RTT_UNLOCK() BASEPRI = LockState; \ - __schedule_barrier(); \ +#define SEGGER_RTT_UNLOCK() \ + BASEPRI = LockState; \ + __schedule_barrier(); \ } #endif #endif /********************************************************************* -* -* RTT lock configuration for TI ARM -*/ + * + * RTT lock configuration for TI ARM + */ #ifdef __TI_ARM__ -#if defined (__TI_ARM_V6M0__) -#define SEGGER_RTT_LOCK() { \ - unsigned int LockState; \ - LockState = __get_PRIMASK(); \ +#if defined(__TI_ARM_V6M0__) +#define SEGGER_RTT_LOCK() \ + { \ + unsigned int LockState; \ + LockState = __get_PRIMASK(); \ __set_PRIMASK(1); -#define SEGGER_RTT_UNLOCK() __set_PRIMASK(LockState); \ +#define SEGGER_RTT_UNLOCK() \ + __set_PRIMASK(LockState); \ } -#elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__)) -#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY - #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) +#elif (defined(__TI_ARM_V7M3__) || defined(__TI_ARM_V7M4__)) +#ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY +#define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) #endif -#define SEGGER_RTT_LOCK() { \ - unsigned int LockState; \ +#define SEGGER_RTT_LOCK() \ + { \ + unsigned int LockState; \ LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY); -#define SEGGER_RTT_UNLOCK() _set_interrupt_priority(LockState); \ +#define SEGGER_RTT_UNLOCK() \ + _set_interrupt_priority(LockState); \ } #endif #endif /********************************************************************* -* -* RTT lock configuration for CCRX -*/ + * + * RTT lock configuration for CCRX + */ #ifdef __RX -#define SEGGER_RTT_LOCK() { \ - unsigned long LockState; \ - LockState = get_psw() & 0x010000; \ +#define SEGGER_RTT_LOCK() \ + { \ + unsigned long LockState; \ + LockState = get_psw() & 0x010000; \ clrpsw_i(); -#define SEGGER_RTT_UNLOCK() set_psw(get_psw() | LockState); \ +#define SEGGER_RTT_UNLOCK() \ + set_psw(get_psw() | LockState); \ } #endif /********************************************************************* -* -* RTT lock configuration for embOS Simulation on Windows -* (Can also be used for generic RTT locking with embOS) -*/ + * + * RTT lock configuration for embOS Simulation on Windows + * (Can also be used for generic RTT locking with embOS) + */ #if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS) void OS_SIM_EnterCriticalSection(void); void OS_SIM_LeaveCriticalSection(void); -#define SEGGER_RTT_LOCK() { \ +#define SEGGER_RTT_LOCK() \ + { \ OS_SIM_EnterCriticalSection(); -#define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \ +#define SEGGER_RTT_UNLOCK() \ + OS_SIM_LeaveCriticalSection(); \ } #endif /********************************************************************* -* -* RTT lock configuration fallback -*/ -#ifndef SEGGER_RTT_LOCK - #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) + * + * RTT lock configuration fallback + */ +#ifndef SEGGER_RTT_LOCK +#define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts) #endif -#ifndef SEGGER_RTT_UNLOCK - #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) +#ifndef SEGGER_RTT_UNLOCK +#define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state) #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/NoRTOS.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/NoRTOS.h index 1868cb0..78b02cb 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/NoRTOS.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/NoRTOS.h @@ -155,15 +155,15 @@ */ typedef struct _NoRTOS_Config { - /*! Function that is called when a TI Driver "suspends" its operation */ - void (*idleCallback)(void); + /*! Function that is called when a TI Driver "suspends" its operation */ + void (*idleCallback)(void); - /*! Period of the internal Clock module's periodic "tick" (microsecs) */ - uint32_t clockTickPeriod; + /*! Period of the internal Clock module's periodic "tick" (microsecs) */ + uint32_t clockTickPeriod; - /*! Hardware interrupt posted by software to achieve the Swi (Software - interrupt) scheduling paradigm */ - int swiIntNum; + /*! Hardware interrupt posted by software to achieve the Swi (Software + interrupt) scheduling paradigm */ + int swiIntNum; } NoRTOS_Config; /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/QueueP.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/QueueP.h index f19a8bf..3a85b7d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/QueueP.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/QueueP.h @@ -35,13 +35,13 @@ typedef struct _QueueP_Elem { - struct _QueueP_Elem* volatile next; - struct _QueueP_Elem* volatile prev; + struct _QueueP_Elem* volatile next; + struct _QueueP_Elem* volatile prev; } QueueP_Elem; typedef struct _QueueP_Obj { - QueueP_Elem elem; + QueueP_Elem elem; } QueueP_Obj; typedef QueueP_Obj* QueueP_Handle; @@ -52,5 +52,5 @@ uintptr_t QueueP_next(QueueP_Elem* qelem); uintptr_t QueueP_prev(QueueP_Elem* qelem); uintptr_t QueueP_get(QueueP_Obj* obj); void QueueP_put(QueueP_Obj* obj, QueueP_Elem* elem); -void QueueP_remove(QueueP_Elem* qelem) ; +void QueueP_remove(QueueP_Elem* qelem); bool QueueP_empty(QueueP_Obj* obj); diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/TimerP.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/TimerP.h index 69cf1c1..83b9c38 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/TimerP.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/dpl/TimerP.h @@ -52,21 +52,21 @@ typedef enum typedef struct _TimerP_FreqHz { - uint32_t hi; - uint32_t lo; + uint32_t hi; + uint32_t lo; } TimerP_FreqHz; typedef struct _TimerP_Params { - TimerP_StartMode startMode; - uintptr_t arg; - uint32_t period; /* in microseconds */ + TimerP_StartMode startMode; + uintptr_t arg; + uint32_t period; /* in microseconds */ } TimerP_Params; typedef union _TimerP_Struct { - uint64_t dummy; - char data[TimerP_STRUCT_SIZE]; + uint64_t dummy; + char data[TimerP_STRUCT_SIZE]; } TimerP_Struct; void TimerP_Params_init(TimerP_Params* params); diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/posix/sys/types.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/posix/sys/types.h index 217edc0..9c0661c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/posix/sys/types.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/kernel/nortos/posix/sys/types.h @@ -43,7 +43,6 @@ extern "C" { #include #include - #if !defined(__GNUC__) || defined(__ti__) /* * ssize_t is a signed size_t. It is the return type for mqueue diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/DeviceFamily.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/DeviceFamily.h index 8930d83..d535a9f 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/DeviceFamily.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/DeviceFamily.h @@ -57,19 +57,19 @@ extern "C" { * DeviceFamily_ID is set to one of these values based on the top level * DeviceFamily_XYZ define. */ -#define DeviceFamily_ID_CC13X0 1 -#define DeviceFamily_ID_CC26X0 2 -#define DeviceFamily_ID_CC26X0R2 3 -#define DeviceFamily_ID_CC13X2 4 -#define DeviceFamily_ID_CC26X2 5 -#define DeviceFamily_ID_CC3200 8 -#define DeviceFamily_ID_CC3220 9 -#define DeviceFamily_ID_MSP432P401x 10 -#define DeviceFamily_ID_MSP432P4x1xI 11 -#define DeviceFamily_ID_MSP432P4x1xT 12 -#define DeviceFamily_ID_MSP432E401Y 13 -#define DeviceFamily_ID_MSP432E411Y 14 -#define DeviceFamily_ID_MTL 15 +#define DeviceFamily_ID_CC13X0 1 +#define DeviceFamily_ID_CC26X0 2 +#define DeviceFamily_ID_CC26X0R2 3 +#define DeviceFamily_ID_CC13X2 4 +#define DeviceFamily_ID_CC26X2 5 +#define DeviceFamily_ID_CC3200 8 +#define DeviceFamily_ID_CC3220 9 +#define DeviceFamily_ID_MSP432P401x 10 +#define DeviceFamily_ID_MSP432P4x1xI 11 +#define DeviceFamily_ID_MSP432P4x1xT 12 +#define DeviceFamily_ID_MSP432E401Y 13 +#define DeviceFamily_ID_MSP432E411Y 14 +#define DeviceFamily_ID_MTL 15 /* * DeviceFamily_PARENT_XYZ values. @@ -78,12 +78,12 @@ extern "C" { * compilation. DeviceFamily_PARENT is set to one of these values based * on the top-level DeviceFamily_XYZ define. */ -#define DeviceFamily_PARENT_CC13X0_CC26X0 1 -#define DeviceFamily_PARENT_CC13X2_CC26X2 2 -#define DeviceFamily_PARENT_MSP432P401R 3 -#define DeviceFamily_PARENT_MSP432P4111 4 -#define DeviceFamily_PARENT_MTL 5 -#define DeviceFamily_PARENT_MSP432E4X1Y 6 +#define DeviceFamily_PARENT_CC13X0_CC26X0 1 +#define DeviceFamily_PARENT_CC13X2_CC26X2 2 +#define DeviceFamily_PARENT_MSP432P401R 3 +#define DeviceFamily_PARENT_MSP432P4111 4 +#define DeviceFamily_PARENT_MTL 5 +#define DeviceFamily_PARENT_MSP432E4X1Y 6 /* * Lookup table that sets DeviceFamily_ID, DeviceFamily_DIRECTORY, and @@ -92,80 +92,80 @@ extern "C" { * multiple DeviceFamily_XYZ are defined, the first one encountered is used. */ #if defined(DeviceFamily_CC13X0) -#define DeviceFamily_ID DeviceFamily_ID_CC13X0 -#define DeviceFamily_DIRECTORY cc13x0 -#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 +#define DeviceFamily_ID DeviceFamily_ID_CC13X0 +#define DeviceFamily_DIRECTORY cc13x0 +#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 #elif defined(DeviceFamily_CC13X2) -#define DeviceFamily_ID DeviceFamily_ID_CC13X2 -#define DeviceFamily_DIRECTORY cc13x2_cc26x2 -#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 +#define DeviceFamily_ID DeviceFamily_ID_CC13X2 +#define DeviceFamily_DIRECTORY cc13x2_cc26x2 +#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 #elif defined(DeviceFamily_CC26X0) -#define DeviceFamily_ID DeviceFamily_ID_CC26X0 -#define DeviceFamily_DIRECTORY cc26x0 -#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 +#define DeviceFamily_ID DeviceFamily_ID_CC26X0 +#define DeviceFamily_DIRECTORY cc26x0 +#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 #elif defined(DeviceFamily_CC26X0R2) -#define DeviceFamily_ID DeviceFamily_ID_CC26X0R2 -#define DeviceFamily_DIRECTORY cc26x0r2 -#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 +#define DeviceFamily_ID DeviceFamily_ID_CC26X0R2 +#define DeviceFamily_DIRECTORY cc26x0r2 +#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 #elif defined(DeviceFamily_CC26X2) -#define DeviceFamily_ID DeviceFamily_ID_CC26X2 -#define DeviceFamily_DIRECTORY cc13x2_cc26x2 -#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 +#define DeviceFamily_ID DeviceFamily_ID_CC26X2 +#define DeviceFamily_DIRECTORY cc13x2_cc26x2 +#define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 #elif defined(DeviceFamily_CC3200) -#define DeviceFamily_ID DeviceFamily_ID_CC3200 -#define DeviceFamily_DIRECTORY cc32xx +#define DeviceFamily_ID DeviceFamily_ID_CC3200 +#define DeviceFamily_DIRECTORY cc32xx #elif defined(DeviceFamily_CC3220) -#define DeviceFamily_ID DeviceFamily_ID_CC3220 -#define DeviceFamily_DIRECTORY cc32xx +#define DeviceFamily_ID DeviceFamily_ID_CC3220 +#define DeviceFamily_DIRECTORY cc32xx #elif defined(DeviceFamily_MSP432P401x) || defined(__MSP432P401R__) -#define DeviceFamily_ID DeviceFamily_ID_MSP432P401x -#define DeviceFamily_DIRECTORY msp432p4xx -#define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P401R +#define DeviceFamily_ID DeviceFamily_ID_MSP432P401x +#define DeviceFamily_DIRECTORY msp432p4xx +#define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P401R #if !defined(__MSP432P401R__) #define __MSP432P401R__ #endif #elif defined(DeviceFamily_MSP432P4x1xI) -#define DeviceFamily_ID DeviceFamily_ID_MSP432P4x1xI -#define DeviceFamily_DIRECTORY msp432p4xx -#define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P4111 +#define DeviceFamily_ID DeviceFamily_ID_MSP432P4x1xI +#define DeviceFamily_DIRECTORY msp432p4xx +#define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P4111 #if !defined(__MSP432P4111__) #define __MSP432P4111__ #endif #elif defined(DeviceFamily_MSP432P4x1xT) -#define DeviceFamily_ID DeviceFamily_ID_MSP432P4x1xT -#define DeviceFamily_DIRECTORY msp432p4xx -#define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P4111 +#define DeviceFamily_ID DeviceFamily_ID_MSP432P4x1xT +#define DeviceFamily_DIRECTORY msp432p4xx +#define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P4111 #if !defined(__MSP432P4111__) #define __MSP432P4111__ #endif #elif defined(DeviceFamily_MSP432E401Y) -#define DeviceFamily_ID DeviceFamily_ID_MSP432E401Y -#define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432E4X1Y -#define DeviceFamily_DIRECTORY msp432e4 +#define DeviceFamily_ID DeviceFamily_ID_MSP432E401Y +#define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432E4X1Y +#define DeviceFamily_DIRECTORY msp432e4 #if !defined(__MSP432E401Y__) #define __MSP432E401Y__ #endif #elif defined(DeviceFamily_MSP432E411Y) -#define DeviceFamily_ID DeviceFamily_ID_MSP432E411Y -#define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432E4X1Y -#define DeviceFamily_DIRECTORY msp432e4 +#define DeviceFamily_ID DeviceFamily_ID_MSP432E411Y +#define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432E4X1Y +#define DeviceFamily_DIRECTORY msp432e4 #if !defined(__MSP432E411Y__) #define __MSP432E411Y__ #endif #elif defined(DeviceFamily_MTL) -#define DeviceFamily_ID DeviceFamily_ID_MTL -#define DeviceFamily_DIRECTORY mtxx +#define DeviceFamily_ID DeviceFamily_ID_MTL +#define DeviceFamily_DIRECTORY mtxx #if !defined(__MTL__) #define __MTL__ #endif @@ -174,15 +174,7 @@ extern "C" { #endif /* Ensure that only one DeviceFamily was specified */ -#if (defined(DeviceFamily_CC13X0) + defined(DeviceFamily_CC13X2) \ - + defined(DeviceFamily_CC26X0) + defined(DeviceFamily_CC26X0R2) \ - + defined(DeviceFamily_CC26X2) \ - + defined(DeviceFamily_CC3200) + defined(DeviceFamily_CC3220) \ - + defined(DeviceFamily_MSP432P401x) + defined(DeviceFamily_MSP432P4x1xI) \ - + defined(DeviceFamily_MSP432P4x1xT) + defined(DeviceFamily_MSP432E401Y) \ - + defined(DeviceFamily_MSP432E411Y) \ - + defined(DeviceFamily_MTL) \ - ) > 1 +#if (defined(DeviceFamily_CC13X0) + defined(DeviceFamily_CC13X2) + defined(DeviceFamily_CC26X0) + defined(DeviceFamily_CC26X0R2) + defined(DeviceFamily_CC26X2) + defined(DeviceFamily_CC3200) + defined(DeviceFamily_CC3220) + defined(DeviceFamily_MSP432P401x) + defined(DeviceFamily_MSP432P4x1xI) + defined(DeviceFamily_MSP432P4x1xT) + defined(DeviceFamily_MSP432E401Y) + defined(DeviceFamily_MSP432E411Y) + defined(DeviceFamily_MTL)) > 1 #error More then one DeviceFamily has been defined! #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/adi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/adi.h index 03de7e2..feab0b1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/adi.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/adi.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: adi.h -* Revised: 2016-11-17 16:39:28 +0100 (Thu, 17 Nov 2016) -* Revision: 47706 -* -* Description: Defines and prototypes for the ADI master interface. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: adi.h + * Revised: 2016-11-17 16:39:28 +0100 (Thu, 17 Nov 2016) + * Revision: 47706 + * + * Description: Defines and prototypes for the ADI master interface. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,36 +55,34 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include +#include "../inc/hw_adi.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" #include "../inc/hw_types.h" #include "../inc/hw_uart.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_adi.h" -#include "debug.h" #include "ddi.h" +#include "debug.h" +#include +#include //***************************************************************************** // // Number of registers in the ADI slave // //***************************************************************************** -#define ADI_SLAVE_REGS 16 - +#define ADI_SLAVE_REGS 16 //***************************************************************************** // // Defines that is used to control the ADI slave and master // //***************************************************************************** -#define ADI_PROTECT 0x00000080 -#define ADI_ACK 0x00000001 -#define ADI_SYNC 0x00000000 +#define ADI_PROTECT 0x00000080 +#define ADI_ACK 0x00000001 +#define ADI_SYNC 0x00000000 //***************************************************************************** // @@ -114,10 +112,6 @@ ADIBaseValid(uint32_t ui32Base) } #endif - - - - //***************************************************************************** // //! \brief Write an 8 bit value to a register in an ADI slave. @@ -883,8 +877,8 @@ ADI16SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, // "bus arbitration" issue. // //***************************************************************************** -void SafeHapiVoid( FPTR_VOID_VOID_T fPtr ); -void SafeHapiAuxAdiSelect( FPTR_VOID_UINT8_T fPtr, uint8_t ut8Signal ); +void SafeHapiVoid(FPTR_VOID_VOID_T fPtr); +void SafeHapiAuxAdiSelect(FPTR_VOID_UINT8_T fPtr, uint8_t ut8Signal); //***************************************************************************** // diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/adi_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/adi_doc.h index 5543464..cb66827 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/adi_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/adi_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: adi_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: adi_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup adi_api //! @{ //! \section sec_adi Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aes.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aes.h index 2f21964..59b5085 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aes.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aes.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aes.h -* Revised: 2019-01-25 14:45:16 +0100 (Fri, 25 Jan 2019) -* Revision: 54287 -* -* Description: AES header file. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aes.h + * Revised: 2019-01-25 14:45:16 +0100 (Fri, 25 Jan 2019) + * Revision: 54287 + * + * Description: AES header file. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,20 +55,19 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_crypto.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" #include #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_crypto.h" -#include "debug.h" -#include "interrupt.h" -#include "cpu.h" //***************************************************************************** // @@ -84,18 +83,17 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AESStartDMAOperation NOROM_AESStartDMAOperation -#define AESSetInitializationVector NOROM_AESSetInitializationVector +#define AESStartDMAOperation NOROM_AESStartDMAOperation +#define AESSetInitializationVector NOROM_AESSetInitializationVector #define AESWriteCCMInitializationVector NOROM_AESWriteCCMInitializationVector -#define AESReadTag NOROM_AESReadTag -#define AESVerifyTag NOROM_AESVerifyTag -#define AESWriteToKeyStore NOROM_AESWriteToKeyStore -#define AESReadFromKeyStore NOROM_AESReadFromKeyStore -#define AESWaitForIRQFlags NOROM_AESWaitForIRQFlags -#define AESConfigureCCMCtrl NOROM_AESConfigureCCMCtrl +#define AESReadTag NOROM_AESReadTag +#define AESVerifyTag NOROM_AESVerifyTag +#define AESWriteToKeyStore NOROM_AESWriteToKeyStore +#define AESReadFromKeyStore NOROM_AESReadFromKeyStore +#define AESWaitForIRQFlags NOROM_AESWaitForIRQFlags +#define AESConfigureCCMCtrl NOROM_AESConfigureCCMCtrl #endif - //***************************************************************************** // // Values that can be passed to AESIntEnable, AESIntDisable, and AESIntClear @@ -104,12 +102,11 @@ extern "C" // function to see if it supports other interrupt status flags. // //***************************************************************************** -#define AES_DMA_IN_DONE CRYPTO_IRQEN_DMA_IN_DONE_M -#define AES_RESULT_RDY CRYPTO_IRQEN_RESULT_AVAIL_M -#define AES_DMA_BUS_ERR CRYPTO_IRQCLR_DMA_BUS_ERR_M -#define AES_KEY_ST_WR_ERR CRYPTO_IRQCLR_KEY_ST_WR_ERR_M -#define AES_KEY_ST_RD_ERR CRYPTO_IRQCLR_KEY_ST_RD_ERR_M - +#define AES_DMA_IN_DONE CRYPTO_IRQEN_DMA_IN_DONE_M +#define AES_RESULT_RDY CRYPTO_IRQEN_RESULT_AVAIL_M +#define AES_DMA_BUS_ERR CRYPTO_IRQCLR_DMA_BUS_ERR_M +#define AES_KEY_ST_WR_ERR CRYPTO_IRQCLR_KEY_ST_WR_ERR_M +#define AES_KEY_ST_RD_ERR CRYPTO_IRQCLR_KEY_ST_RD_ERR_M //***************************************************************************** // @@ -118,33 +115,32 @@ extern "C" //***************************************************************************** // AES module return codes -#define AES_SUCCESS 0 -#define AES_KEYSTORE_ERROR 1 -#define AES_KEYSTORE_AREA_INVALID 2 -#define AES_DMA_BUSY 3 -#define AES_DMA_ERROR 4 -#define AES_TAG_NOT_READY 5 -#define AES_TAG_VERIFICATION_FAILED 6 +#define AES_SUCCESS 0 +#define AES_KEYSTORE_ERROR 1 +#define AES_KEYSTORE_AREA_INVALID 2 +#define AES_DMA_BUSY 3 +#define AES_DMA_ERROR 4 +#define AES_TAG_NOT_READY 5 +#define AES_TAG_VERIFICATION_FAILED 6 // Key store module defines -#define AES_IV_LENGTH_BYTES 16 -#define AES_TAG_LENGTH_BYTES 16 -#define AES_128_KEY_LENGTH_BYTES (128 / 8) -#define AES_192_KEY_LENGTH_BYTES (192 / 8) -#define AES_256_KEY_LENGTH_BYTES (256 / 8) +#define AES_IV_LENGTH_BYTES 16 +#define AES_TAG_LENGTH_BYTES 16 +#define AES_128_KEY_LENGTH_BYTES (128 / 8) +#define AES_192_KEY_LENGTH_BYTES (192 / 8) +#define AES_256_KEY_LENGTH_BYTES (256 / 8) -#define AES_BLOCK_SIZE 16 +#define AES_BLOCK_SIZE 16 // DMA status codes -#define AES_DMA_CHANNEL0_ACTIVE CRYPTO_DMASTAT_CH0_ACT_M -#define AES_DMA_CHANNEL1_ACTIVE CRYPTO_DMASTAT_CH1_ACT_M -#define AES_DMA_PORT_ERROR CRYPTO_DMASTAT_PORT_ERR_M +#define AES_DMA_CHANNEL0_ACTIVE CRYPTO_DMASTAT_CH0_ACT_M +#define AES_DMA_CHANNEL1_ACTIVE CRYPTO_DMASTAT_CH1_ACT_M +#define AES_DMA_PORT_ERROR CRYPTO_DMASTAT_PORT_ERR_M // Crypto module operation types -#define AES_ALGSEL_AES CRYPTO_ALGSEL_AES_M -#define AES_ALGSEL_KEY_STORE CRYPTO_ALGSEL_KEY_STORE_M -#define AES_ALGSEL_TAG CRYPTO_ALGSEL_TAG_M - +#define AES_ALGSEL_AES CRYPTO_ALGSEL_AES_M +#define AES_ALGSEL_KEY_STORE CRYPTO_ALGSEL_KEY_STORE_M +#define AES_ALGSEL_TAG CRYPTO_ALGSEL_TAG_M //***************************************************************************** // @@ -153,24 +149,24 @@ extern "C" // may be odd. Do not attempt to write a 256-bit key to AES_KEY_AREA_7. // //***************************************************************************** -#define AES_KEY_AREA_0 0 -#define AES_KEY_AREA_1 1 -#define AES_KEY_AREA_2 2 -#define AES_KEY_AREA_3 3 -#define AES_KEY_AREA_4 4 -#define AES_KEY_AREA_5 5 -#define AES_KEY_AREA_6 6 -#define AES_KEY_AREA_7 7 +#define AES_KEY_AREA_0 0 +#define AES_KEY_AREA_1 1 +#define AES_KEY_AREA_2 2 +#define AES_KEY_AREA_3 3 +#define AES_KEY_AREA_4 4 +#define AES_KEY_AREA_5 5 +#define AES_KEY_AREA_6 6 +#define AES_KEY_AREA_7 7 //***************************************************************************** // // Defines for the AES-CTR mode counter width // //***************************************************************************** -#define AES_CTR_WIDTH_32 0x0 -#define AES_CTR_WIDTH_64 0x1 -#define AES_CTR_WIDTH_96 0x2 -#define AES_CTR_WIDTH_128 0x3 +#define AES_CTR_WIDTH_32 0x0 +#define AES_CTR_WIDTH_64 0x1 +#define AES_CTR_WIDTH_96 0x2 +#define AES_CTR_WIDTH_128 0x3 //***************************************************************************** // @@ -213,7 +209,7 @@ extern "C" //! \return None // //***************************************************************************** -extern void AESStartDMAOperation(const uint8_t* channel0Addr, uint32_t channel0Length, uint8_t* channel1Addr, uint32_t channel1Length); +extern void AESStartDMAOperation(const uint8_t* channel0Addr, uint32_t channel0Length, uint8_t* channel1Addr, uint32_t channel1Length); //***************************************************************************** // @@ -406,7 +402,6 @@ extern uint32_t AESWriteToKeyStore(const uint8_t* aesKey, uint32_t aesKeyLength, //***************************************************************************** extern uint32_t AESReadFromKeyStore(uint32_t keyStoreArea); - //***************************************************************************** // //! \brief Poll the interrupt status register and clear when done. @@ -786,40 +781,40 @@ __STATIC_INLINE void AESIntUnregister(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AESStartDMAOperation -#undef AESStartDMAOperation -#define AESStartDMAOperation ROM_AESStartDMAOperation +#undef AESStartDMAOperation +#define AESStartDMAOperation ROM_AESStartDMAOperation #endif #ifdef ROM_AESSetInitializationVector -#undef AESSetInitializationVector -#define AESSetInitializationVector ROM_AESSetInitializationVector +#undef AESSetInitializationVector +#define AESSetInitializationVector ROM_AESSetInitializationVector #endif #ifdef ROM_AESWriteCCMInitializationVector -#undef AESWriteCCMInitializationVector +#undef AESWriteCCMInitializationVector #define AESWriteCCMInitializationVector ROM_AESWriteCCMInitializationVector #endif #ifdef ROM_AESReadTag -#undef AESReadTag -#define AESReadTag ROM_AESReadTag +#undef AESReadTag +#define AESReadTag ROM_AESReadTag #endif #ifdef ROM_AESVerifyTag -#undef AESVerifyTag -#define AESVerifyTag ROM_AESVerifyTag +#undef AESVerifyTag +#define AESVerifyTag ROM_AESVerifyTag #endif #ifdef ROM_AESWriteToKeyStore -#undef AESWriteToKeyStore -#define AESWriteToKeyStore ROM_AESWriteToKeyStore +#undef AESWriteToKeyStore +#define AESWriteToKeyStore ROM_AESWriteToKeyStore #endif #ifdef ROM_AESReadFromKeyStore -#undef AESReadFromKeyStore -#define AESReadFromKeyStore ROM_AESReadFromKeyStore +#undef AESReadFromKeyStore +#define AESReadFromKeyStore ROM_AESReadFromKeyStore #endif #ifdef ROM_AESWaitForIRQFlags -#undef AESWaitForIRQFlags -#define AESWaitForIRQFlags ROM_AESWaitForIRQFlags +#undef AESWaitForIRQFlags +#define AESWaitForIRQFlags ROM_AESWaitForIRQFlags #endif #ifdef ROM_AESConfigureCCMCtrl -#undef AESConfigureCCMCtrl -#define AESConfigureCCMCtrl ROM_AESConfigureCCMCtrl +#undef AESConfigureCCMCtrl +#define AESConfigureCCMCtrl ROM_AESConfigureCCMCtrl #endif #endif @@ -832,7 +827,7 @@ __STATIC_INLINE void AESIntUnregister(void) } #endif -#endif // __AES_H__ +#endif // __AES_H__ //***************************************************************************** // diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_batmon.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_batmon.h index 0a186b6..dc8e0a4 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_batmon.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_batmon.h @@ -1,41 +1,41 @@ /****************************************************************************** -* Filename: aon_batmon.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the AON Battery and Temperature -* Monitor -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_batmon.h + * Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) + * Revision: 47343 + * + * Description: Defines and prototypes for the AON Battery and Temperature + * Monitor + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -56,16 +56,15 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aon_batmon.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aon_batmon.h" -#include "debug.h" //***************************************************************************** // @@ -81,10 +80,9 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC +#define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC #endif - //***************************************************************************** // // API Functions and prototypes @@ -145,7 +143,6 @@ AONBatMonDisable(void) HWREG(AON_BATMON_BASE + AON_BATMON_O_CTL) = 0; } - //***************************************************************************** // //! \brief Get the current temperature measurement as a signed value in Deg Celsius. @@ -163,7 +160,7 @@ AONBatMonDisable(void) //! \sa AONBatMonNewTempMeasureReady() // //***************************************************************************** -extern int32_t AONBatMonTemperatureGetDegC( void ); +extern int32_t AONBatMonTemperatureGetDegC(void); //***************************************************************************** // @@ -221,7 +218,9 @@ AONBatMonNewBatteryMeasureReady(void) // Check the status bit. bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_BATUPD) & - AON_BATMON_BATUPD_STAT ? true : false; + AON_BATMON_BATUPD_STAT + ? true + : false; // Clear status bit if set. if (bStatus) @@ -260,7 +259,9 @@ AONBatMonNewTempMeasureReady(void) // Check the status bit. bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_TEMPUPD) & - AON_BATMON_TEMPUPD_STAT ? true : false; + AON_BATMON_TEMPUPD_STAT + ? true + : false; // Clear status bit if set. if (bStatus) @@ -281,8 +282,8 @@ AONBatMonNewTempMeasureReady(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AONBatMonTemperatureGetDegC -#undef AONBatMonTemperatureGetDegC -#define AONBatMonTemperatureGetDegC ROM_AONBatMonTemperatureGetDegC +#undef AONBatMonTemperatureGetDegC +#define AONBatMonTemperatureGetDegC ROM_AONBatMonTemperatureGetDegC #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_event.h index 4792562..c660d13 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_event.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_event.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aon_event.h -* Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017) -* Revision: 49506 -* -* Description: Defines and prototypes for the AON Event fabric. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_event.h + * Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017) + * Revision: 49506 + * + * Description: Defines and prototypes for the AON Event fabric. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,17 +55,16 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aon_event.h" +#include "../inc/hw_device.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_device.h" -#include "../inc/hw_aon_event.h" -#include "debug.h" //***************************************************************************** // @@ -81,12 +80,12 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet -#define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet -#define AONEventAuxWakeUpSet NOROM_AONEventAuxWakeUpSet -#define AONEventAuxWakeUpGet NOROM_AONEventAuxWakeUpGet -#define AONEventMcuSet NOROM_AONEventMcuSet -#define AONEventMcuGet NOROM_AONEventMcuGet +#define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet +#define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet +#define AONEventAuxWakeUpSet NOROM_AONEventAuxWakeUpSet +#define AONEventAuxWakeUpGet NOROM_AONEventAuxWakeUpGet +#define AONEventMcuSet NOROM_AONEventMcuSet +#define AONEventMcuGet NOROM_AONEventMcuGet #endif //***************************************************************************** @@ -98,36 +97,36 @@ extern "C" // AON_EVENT_DIO0 // Edge detect on DIO0. See hw_device.h // ... // ... // AON_EVENT_DIO31 // Edge detect on DIO31. See hw_device.h -#define AON_EVENT_IO 32 // Edge detect on any DIO. Edge detect is enabled and configured in IOC. +#define AON_EVENT_IO 32 // Edge detect on any DIO. Edge detect is enabled and configured in IOC. // Event ID 33 is reserved for future use // Event ID 34 is reserved for future use -#define AON_EVENT_RTC_CH0 35 // RTC channel 0 -#define AON_EVENT_RTC_CH1 36 // RTC channel 1 -#define AON_EVENT_RTC_CH2 37 // RTC channel 2 -#define AON_EVENT_RTC_CH0_DLY 38 // RTC channel 0 - delayed event -#define AON_EVENT_RTC_CH1_DLY 39 // RTC channel 1 - delayed event -#define AON_EVENT_RTC_CH2_DLY 40 // RTC channel 2 - delayed event -#define AON_EVENT_RTC_COMB_DLY 41 // RTC combined delayed event -#define AON_EVENT_RTC_UPD 42 // RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) -#define AON_EVENT_JTAG 43 // JTAG generated event -#define AON_EVENT_AUX_SWEV0 44 // AUX Software triggered event #0 -#define AON_EVENT_AUX_SWEV1 45 // AUX Software triggered event #1 -#define AON_EVENT_AUX_SWEV2 46 // AUX Software triggered event #2 -#define AON_EVENT_AUX_COMPA 47 // Comparator A triggered (synchronized in AUX) -#define AON_EVENT_AUX_COMPB 48 // Comparator B triggered (synchronized in AUX) -#define AON_EVENT_AUX_ADC_DONE 49 // ADC conversion completed -#define AON_EVENT_AUX_TDC_DONE 50 // TDC completed or timed out -#define AON_EVENT_AUX_TIMER0_EV 51 // Timer 0 event -#define AON_EVENT_AUX_TIMER1_EV 52 // Timer 1 event -#define AON_EVENT_BATMON_TEMP 53 // BATMON temperature update event -#define AON_EVENT_BATMON_VOLT 54 // BATMON voltage update event -#define AON_EVENT_AUX_COMPB_ASYNC 55 // Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +#define AON_EVENT_RTC_CH0 35 // RTC channel 0 +#define AON_EVENT_RTC_CH1 36 // RTC channel 1 +#define AON_EVENT_RTC_CH2 37 // RTC channel 2 +#define AON_EVENT_RTC_CH0_DLY 38 // RTC channel 0 - delayed event +#define AON_EVENT_RTC_CH1_DLY 39 // RTC channel 1 - delayed event +#define AON_EVENT_RTC_CH2_DLY 40 // RTC channel 2 - delayed event +#define AON_EVENT_RTC_COMB_DLY 41 // RTC combined delayed event +#define AON_EVENT_RTC_UPD 42 // RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +#define AON_EVENT_JTAG 43 // JTAG generated event +#define AON_EVENT_AUX_SWEV0 44 // AUX Software triggered event #0 +#define AON_EVENT_AUX_SWEV1 45 // AUX Software triggered event #1 +#define AON_EVENT_AUX_SWEV2 46 // AUX Software triggered event #2 +#define AON_EVENT_AUX_COMPA 47 // Comparator A triggered (synchronized in AUX) +#define AON_EVENT_AUX_COMPB 48 // Comparator B triggered (synchronized in AUX) +#define AON_EVENT_AUX_ADC_DONE 49 // ADC conversion completed +#define AON_EVENT_AUX_TDC_DONE 50 // TDC completed or timed out +#define AON_EVENT_AUX_TIMER0_EV 51 // Timer 0 event +#define AON_EVENT_AUX_TIMER1_EV 52 // Timer 1 event +#define AON_EVENT_BATMON_TEMP 53 // BATMON temperature update event +#define AON_EVENT_BATMON_VOLT 54 // BATMON voltage update event +#define AON_EVENT_AUX_COMPB_ASYNC 55 // Comparator B triggered. Asynchronous signal directly from the AUX Comparator B #define AON_EVENT_AUX_COMPB_ASYNC_N 56 // Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B // Event ID 57-62 is reserved for future use -#define AON_EVENT_NONE 63 // No event, always low +#define AON_EVENT_NONE 63 // No event, always low // Keeping backward compatibility until major revision number is incremented -#define AON_EVENT_RTC0 ( AON_EVENT_RTC_CH0 ) +#define AON_EVENT_RTC0 (AON_EVENT_RTC_CH0) //***************************************************************************** // @@ -135,28 +134,28 @@ extern "C" // by AONEventMCUWakeUpGet(). // //***************************************************************************** -#define AON_EVENT_MCU_WU0 0 // Programmable MCU wake-up event 0 -#define AON_EVENT_MCU_WU1 1 // Programmable MCU wake-up event 1 -#define AON_EVENT_MCU_WU2 2 // Programmable MCU wake-up event 2 -#define AON_EVENT_MCU_WU3 3 // Programmable MCU wake-up event 3 +#define AON_EVENT_MCU_WU0 0 // Programmable MCU wake-up event 0 +#define AON_EVENT_MCU_WU1 1 // Programmable MCU wake-up event 1 +#define AON_EVENT_MCU_WU2 2 // Programmable MCU wake-up event 2 +#define AON_EVENT_MCU_WU3 3 // Programmable MCU wake-up event 3 //***************************************************************************** // // Values that can be passed to AONEventAuxWakeUpSet() and AONEventAuxWakeUpGet() // //***************************************************************************** -#define AON_EVENT_AUX_WU0 0 // Programmable AUX wake-up event 0 -#define AON_EVENT_AUX_WU1 1 // Programmable AUX wake-up event 1 -#define AON_EVENT_AUX_WU2 2 // Programmable AUX wake-up event 2 +#define AON_EVENT_AUX_WU0 0 // Programmable AUX wake-up event 0 +#define AON_EVENT_AUX_WU1 1 // Programmable AUX wake-up event 1 +#define AON_EVENT_AUX_WU2 2 // Programmable AUX wake-up event 2 //***************************************************************************** // // Values that can be passed to AONEventMcuSet() and AONEventMcuGet() // //***************************************************************************** -#define AON_EVENT_MCU_EVENT0 0 // Programmable event source fed to MCU event fabric (first of 3) -#define AON_EVENT_MCU_EVENT1 1 // Programmable event source fed to MCU event fabric (second of 3) -#define AON_EVENT_MCU_EVENT2 2 // Programmable event source fed to MCU event fabric (third of 3) +#define AON_EVENT_MCU_EVENT0 0 // Programmable event source fed to MCU event fabric (first of 3) +#define AON_EVENT_MCU_EVENT1 1 // Programmable event source fed to MCU event fabric (second of 3) +#define AON_EVENT_MCU_EVENT2 2 // Programmable event source fed to MCU event fabric (third of 3) //***************************************************************************** // @@ -575,28 +574,28 @@ AONEventRtcGet(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AONEventMcuWakeUpSet -#undef AONEventMcuWakeUpSet -#define AONEventMcuWakeUpSet ROM_AONEventMcuWakeUpSet +#undef AONEventMcuWakeUpSet +#define AONEventMcuWakeUpSet ROM_AONEventMcuWakeUpSet #endif #ifdef ROM_AONEventMcuWakeUpGet -#undef AONEventMcuWakeUpGet -#define AONEventMcuWakeUpGet ROM_AONEventMcuWakeUpGet +#undef AONEventMcuWakeUpGet +#define AONEventMcuWakeUpGet ROM_AONEventMcuWakeUpGet #endif #ifdef ROM_AONEventAuxWakeUpSet -#undef AONEventAuxWakeUpSet -#define AONEventAuxWakeUpSet ROM_AONEventAuxWakeUpSet +#undef AONEventAuxWakeUpSet +#define AONEventAuxWakeUpSet ROM_AONEventAuxWakeUpSet #endif #ifdef ROM_AONEventAuxWakeUpGet -#undef AONEventAuxWakeUpGet -#define AONEventAuxWakeUpGet ROM_AONEventAuxWakeUpGet +#undef AONEventAuxWakeUpGet +#define AONEventAuxWakeUpGet ROM_AONEventAuxWakeUpGet #endif #ifdef ROM_AONEventMcuSet -#undef AONEventMcuSet -#define AONEventMcuSet ROM_AONEventMcuSet +#undef AONEventMcuSet +#define AONEventMcuSet ROM_AONEventMcuSet #endif #ifdef ROM_AONEventMcuGet -#undef AONEventMcuGet -#define AONEventMcuGet ROM_AONEventMcuGet +#undef AONEventMcuGet +#define AONEventMcuGet ROM_AONEventMcuGet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_event_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_event_doc.h index e1fcea8..dfeed44 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_event_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_event_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: aon_event_doc.h -* Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017) -* Revision: 49506 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_event_doc.h + * Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017) + * Revision: 49506 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup aonevent_api //! @{ //! \section sec_aonevent Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_ioc.h index f60cb03..baffd83 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_ioc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_ioc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aon_ioc.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the AON IO Controller -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_ioc.h + * Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) + * Revision: 47343 + * + * Description: Defines and prototypes for the AON IO Controller + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,34 +55,33 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aon_ioc.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aon_ioc.h" -#include "debug.h" //***************************************************************************** // // Defines for the drive strength // //***************************************************************************** -#define AONIOC_DRV_STR_1 0x00000000 // Lowest drive strength -#define AONIOC_DRV_STR_2 0x00000001 -#define AONIOC_DRV_STR_3 0x00000003 -#define AONIOC_DRV_STR_4 0x00000002 -#define AONIOC_DRV_STR_5 0x00000006 -#define AONIOC_DRV_STR_6 0x00000007 -#define AONIOC_DRV_STR_7 0x00000005 -#define AONIOC_DRV_STR_8 0x00000004 // Highest drive strength +#define AONIOC_DRV_STR_1 0x00000000 // Lowest drive strength +#define AONIOC_DRV_STR_2 0x00000001 +#define AONIOC_DRV_STR_3 0x00000003 +#define AONIOC_DRV_STR_4 0x00000002 +#define AONIOC_DRV_STR_5 0x00000006 +#define AONIOC_DRV_STR_6 0x00000007 +#define AONIOC_DRV_STR_7 0x00000005 +#define AONIOC_DRV_STR_8 0x00000004 // Highest drive strength -#define AONIOC_DRV_LVL_MIN (AON_IOC_O_IOSTRMIN) -#define AONIOC_DRV_LVL_MED (AON_IOC_O_IOSTRMED) -#define AONIOC_DRV_LVL_MAX (AON_IOC_O_IOSTRMAX) +#define AONIOC_DRV_LVL_MIN (AON_IOC_O_IOSTRMIN) +#define AONIOC_DRV_LVL_MED (AON_IOC_O_IOSTRMED) +#define AONIOC_DRV_LVL_MAX (AON_IOC_O_IOSTRMAX) //***************************************************************************** // @@ -186,7 +185,7 @@ AONIOCDriveStrengthGet(uint32_t ui32DriveLevel) (ui32DriveLevel == AONIOC_DRV_LVL_MAX)); // Return the drive strength value. - return ( HWREG(AON_IOC_BASE + ui32DriveLevel) ); + return (HWREG(AON_IOC_BASE + ui32DriveLevel)); } //***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_ioc_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_ioc_doc.h index 7fe0e93..e90c20c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_ioc_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_ioc_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: aon_ioc_doc.h -* Revised: 2016-03-30 11:01:30 +0200 (Wed, 30 Mar 2016) -* Revision: 45969 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_ioc_doc.h + * Revised: 2016-03-30 11:01:30 +0200 (Wed, 30 Mar 2016) + * Revision: 45969 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup aonioc_api //! @{ //! \section sec_aonioc Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_rtc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_rtc.h index 569fe22..9d1654b 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_rtc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_rtc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aon_rtc.h -* Revised: 2017-08-16 15:13:43 +0200 (Wed, 16 Aug 2017) -* Revision: 49593 -* -* Description: Defines and prototypes for the AON RTC -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_rtc.h + * Revised: 2017-08-16 15:13:43 +0200 (Wed, 16 Aug 2017) + * Revision: 49593 + * + * Description: Defines and prototypes for the AON RTC + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,16 +55,15 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aon_rtc.h" -#include "debug.h" //***************************************************************************** // @@ -80,8 +79,8 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AONRTCCurrentCompareValueGet NOROM_AONRTCCurrentCompareValueGet -#define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet +#define AONRTCCurrentCompareValueGet NOROM_AONRTCCurrentCompareValueGet +#define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet #endif //***************************************************************************** @@ -90,11 +89,11 @@ extern "C" // parameter. // //***************************************************************************** -#define AON_RTC_CH_NONE 0x0 // RTC No channel -#define AON_RTC_CH0 0x1 // RTC Channel 0 -#define AON_RTC_CH1 0x2 // RTC Channel 1 -#define AON_RTC_CH2 0x4 // RTC Channel 2 -#define AON_RTC_ACTIVE 0x8 // RTC Active +#define AON_RTC_CH_NONE 0x0 // RTC No channel +#define AON_RTC_CH0 0x1 // RTC Channel 0 +#define AON_RTC_CH1 0x2 // RTC Channel 1 +#define AON_RTC_CH2 0x4 // RTC Channel 2 +#define AON_RTC_ACTIVE 0x8 // RTC Active //***************************************************************************** // @@ -102,19 +101,19 @@ extern "C" // //***************************************************************************** #define AON_RTC_CONFIG_DELAY_NODELAY 0 // NO DELAY -#define AON_RTC_CONFIG_DELAY_1 1 // Delay of 1 clk cycle -#define AON_RTC_CONFIG_DELAY_2 2 // Delay of 2 clk cycles -#define AON_RTC_CONFIG_DELAY_4 3 // Delay of 4 clk cycles -#define AON_RTC_CONFIG_DELAY_8 4 // Delay of 8 clk cycles -#define AON_RTC_CONFIG_DELAY_16 5 // Delay of 16 clk cycles -#define AON_RTC_CONFIG_DELAY_32 6 // Delay of 32 clk cycles -#define AON_RTC_CONFIG_DELAY_48 7 // Delay of 48 clk cycles -#define AON_RTC_CONFIG_DELAY_64 8 // Delay of 64 clk cycles -#define AON_RTC_CONFIG_DELAY_80 9 // Delay of 80 clk cycles -#define AON_RTC_CONFIG_DELAY_96 10 // Delay of 96 clk cycles -#define AON_RTC_CONFIG_DELAY_112 11 // Delay of 112 clk cycles -#define AON_RTC_CONFIG_DELAY_128 12 // Delay of 128 clk cycles -#define AON_RTC_CONFIG_DELAY_144 13 // Delay of 144 clk cycles +#define AON_RTC_CONFIG_DELAY_1 1 // Delay of 1 clk cycle +#define AON_RTC_CONFIG_DELAY_2 2 // Delay of 2 clk cycles +#define AON_RTC_CONFIG_DELAY_4 3 // Delay of 4 clk cycles +#define AON_RTC_CONFIG_DELAY_8 4 // Delay of 8 clk cycles +#define AON_RTC_CONFIG_DELAY_16 5 // Delay of 16 clk cycles +#define AON_RTC_CONFIG_DELAY_32 6 // Delay of 32 clk cycles +#define AON_RTC_CONFIG_DELAY_48 7 // Delay of 48 clk cycles +#define AON_RTC_CONFIG_DELAY_64 8 // Delay of 64 clk cycles +#define AON_RTC_CONFIG_DELAY_80 9 // Delay of 80 clk cycles +#define AON_RTC_CONFIG_DELAY_96 10 // Delay of 96 clk cycles +#define AON_RTC_CONFIG_DELAY_112 11 // Delay of 112 clk cycles +#define AON_RTC_CONFIG_DELAY_128 12 // Delay of 128 clk cycles +#define AON_RTC_CONFIG_DELAY_144 13 // Delay of 144 clk cycles //***************************************************************************** // @@ -122,8 +121,8 @@ extern "C" // parameter. // //***************************************************************************** -#define AON_RTC_MODE_CH1_CAPTURE 1 // Capture mode -#define AON_RTC_MODE_CH1_COMPARE 0 // Compare Mode +#define AON_RTC_MODE_CH1_CAPTURE 1 // Capture mode +#define AON_RTC_MODE_CH1_COMPARE 0 // Compare Mode //***************************************************************************** // @@ -131,7 +130,7 @@ extern "C" // parameter. // //***************************************************************************** -#define AON_RTC_MODE_CH2_CONTINUOUS 1 // Continuous mode +#define AON_RTC_MODE_CH2_CONTINUOUS 1 // Continuous mode #define AON_RTC_MODE_CH2_NORMALCOMPARE 0 // Normal compare mode //***************************************************************************** @@ -148,7 +147,7 @@ extern "C" // ( 4 * FACTOR_SEC_TO_COMP_VAL_FORMAT ) // //***************************************************************************** -#define FACTOR_SEC_TO_COMP_VAL_FORMAT 0x00010000 +#define FACTOR_SEC_TO_COMP_VAL_FORMAT 0x00010000 //***************************************************************************** // @@ -306,8 +305,7 @@ AONRTCDelayConfig(uint32_t ui32Delay) // Check the arguments. ASSERT(ui32Delay <= AON_RTC_CONFIG_DELAY_144); - - ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); + ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); ui32Cfg &= ~(AON_RTC_CTL_EV_DELAY_M); ui32Cfg |= (ui32Delay << AON_RTC_CTL_EV_DELAY_S); @@ -339,10 +337,10 @@ AONRTCCombinedEventConfig(uint32_t ui32Channels) uint32_t ui32Cfg; // Check the arguments. - ASSERT( (ui32Channels & (AON_RTC_CH0 | AON_RTC_CH1 | AON_RTC_CH2)) || - (ui32Channels == AON_RTC_CH_NONE) ); + ASSERT((ui32Channels & (AON_RTC_CH0 | AON_RTC_CH1 | AON_RTC_CH2)) || + (ui32Channels == AON_RTC_CH_NONE)); - ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); + ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); ui32Cfg &= ~(AON_RTC_CTL_COMB_EV_MASK_M); ui32Cfg |= (ui32Channels << AON_RTC_CTL_COMB_EV_MASK_S); @@ -907,12 +905,12 @@ AONRTCCaptureValueCh1Get(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AONRTCCurrentCompareValueGet -#undef AONRTCCurrentCompareValueGet -#define AONRTCCurrentCompareValueGet ROM_AONRTCCurrentCompareValueGet +#undef AONRTCCurrentCompareValueGet +#define AONRTCCurrentCompareValueGet ROM_AONRTCCurrentCompareValueGet #endif #ifdef ROM_AONRTCCurrent64BitValueGet -#undef AONRTCCurrent64BitValueGet -#define AONRTCCurrent64BitValueGet ROM_AONRTCCurrent64BitValueGet +#undef AONRTCCurrent64BitValueGet +#define AONRTCCurrent64BitValueGet ROM_AONRTCCurrent64BitValueGet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_rtc_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_rtc_doc.h index b3c142b..35dd310 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_rtc_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_rtc_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: aon_rtc_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_rtc_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup aonrtc_api //! @{ //! \section sec_aonrtc Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_wuc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_wuc.h index a915840..f507b5c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_wuc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aon_wuc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aon_wuc.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Defines and prototypes for the AON Wake-Up Controller -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_wuc.h + * Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) + * Revision: 49096 + * + * Description: Defines and prototypes for the AON Wake-Up Controller + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,19 +55,18 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_aon_wuc.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" +#include "interrupt.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_aon_wuc.h" -#include "../inc/hw_aon_rtc.h" -#include "interrupt.h" -#include "debug.h" //***************************************************************************** // @@ -83,9 +82,9 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AONWUCAuxReset NOROM_AONWUCAuxReset -#define AONWUCRechargeCtrlConfigSet NOROM_AONWUCRechargeCtrlConfigSet -#define AONWUCOscConfig NOROM_AONWUCOscConfig +#define AONWUCAuxReset NOROM_AONWUCAuxReset +#define AONWUCRechargeCtrlConfigSet NOROM_AONWUCRechargeCtrlConfigSet +#define AONWUCOscConfig NOROM_AONWUCOscConfig #endif //***************************************************************************** @@ -93,11 +92,11 @@ extern "C" // Defines the possible clock source for the MCU and AUX domain. // //***************************************************************************** -#define AONWUC_CLOCK_SRC_HF 0x00000003 // System clock high frequency - +#define AONWUC_CLOCK_SRC_HF 0x00000003 // System clock high frequency - // 48 MHz. -#define AONWUC_CLOCK_SRC_LF 0x00000001 // System clock low frequency - +#define AONWUC_CLOCK_SRC_LF 0x00000001 // System clock low frequency - // 32 kHz. -#define AONWUC_NO_CLOCK 0x00000000 // System clock low frequency - +#define AONWUC_NO_CLOCK 0x00000000 // System clock low frequency - // 32 kHz. //***************************************************************************** @@ -105,30 +104,30 @@ extern "C" // Defines the possible clock division factors for the AUX domain. // //***************************************************************************** -#define AUX_CLOCK_DIV_2 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV2 ) -#define AUX_CLOCK_DIV_4 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV4 ) -#define AUX_CLOCK_DIV_8 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV8 ) -#define AUX_CLOCK_DIV_16 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV16 ) -#define AUX_CLOCK_DIV_32 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV32 ) -#define AUX_CLOCK_DIV_64 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV64 ) -#define AUX_CLOCK_DIV_128 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV128 ) -#define AUX_CLOCK_DIV_256 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV256 ) -#define AUX_CLOCK_DIV_UNUSED ( AON_WUC_AUXCLK_SCLK_HF_DIV_M + ( 1 << AON_WUC_AUXCLK_SCLK_HF_DIV_S )) -#define AUX_CLOCK_DIV_M ( AON_WUC_AUXCLK_SCLK_HF_DIV_M ) +#define AUX_CLOCK_DIV_2 (AON_WUC_AUXCLK_SCLK_HF_DIV_DIV2) +#define AUX_CLOCK_DIV_4 (AON_WUC_AUXCLK_SCLK_HF_DIV_DIV4) +#define AUX_CLOCK_DIV_8 (AON_WUC_AUXCLK_SCLK_HF_DIV_DIV8) +#define AUX_CLOCK_DIV_16 (AON_WUC_AUXCLK_SCLK_HF_DIV_DIV16) +#define AUX_CLOCK_DIV_32 (AON_WUC_AUXCLK_SCLK_HF_DIV_DIV32) +#define AUX_CLOCK_DIV_64 (AON_WUC_AUXCLK_SCLK_HF_DIV_DIV64) +#define AUX_CLOCK_DIV_128 (AON_WUC_AUXCLK_SCLK_HF_DIV_DIV128) +#define AUX_CLOCK_DIV_256 (AON_WUC_AUXCLK_SCLK_HF_DIV_DIV256) +#define AUX_CLOCK_DIV_UNUSED (AON_WUC_AUXCLK_SCLK_HF_DIV_M + (1 << AON_WUC_AUXCLK_SCLK_HF_DIV_S)) +#define AUX_CLOCK_DIV_M (AON_WUC_AUXCLK_SCLK_HF_DIV_M) //***************************************************************************** // // Defines used for configuring the power-off and wake up procedure. // //***************************************************************************** -#define MCU_VIRT_PWOFF_DISABLE 0x00000000 -#define MCU_VIRT_PWOFF_ENABLE 0x00020000 -#define MCU_IMM_WAKE_UP 0x00000000 -#define MCU_FIXED_WAKE_UP 0x00010000 -#define AUX_VIRT_PWOFF_DISABLE 0x00000000 -#define AUX_VIRT_PWOFF_ENABLE 0x00020000 -#define AUX_IMM_WAKE_UP 0x00000000 -#define AUX_FIXED_WAKE_UP 0x00010000 +#define MCU_VIRT_PWOFF_DISABLE 0x00000000 +#define MCU_VIRT_PWOFF_ENABLE 0x00020000 +#define MCU_IMM_WAKE_UP 0x00000000 +#define MCU_FIXED_WAKE_UP 0x00010000 +#define AUX_VIRT_PWOFF_DISABLE 0x00000000 +#define AUX_VIRT_PWOFF_ENABLE 0x00020000 +#define AUX_IMM_WAKE_UP 0x00000000 +#define AUX_FIXED_WAKE_UP 0x00010000 //***************************************************************************** // @@ -136,12 +135,12 @@ extern "C" // retention on the SRAM in both the MCU and the AUX domain. // //***************************************************************************** -#define MCU_RAM0_RETENTION 0x00000001 -#define MCU_RAM1_RETENTION 0x00000002 -#define MCU_RAM2_RETENTION 0x00000004 -#define MCU_RAM3_RETENTION 0x00000008 +#define MCU_RAM0_RETENTION 0x00000001 +#define MCU_RAM1_RETENTION 0x00000002 +#define MCU_RAM2_RETENTION 0x00000004 +#define MCU_RAM3_RETENTION 0x00000008 #define MCU_RAM_BLOCK_RETENTION 0x0000000F -#define MCU_AUX_RET_ENABLE 0x00000001 +#define MCU_AUX_RET_ENABLE 0x00000001 //***************************************************************************** // @@ -149,8 +148,8 @@ extern "C" // AONWUCAuxWakeUpEvent() . // //***************************************************************************** -#define AONWUC_AUX_WAKEUP 0x00000001 -#define AONWUC_AUX_ALLOW_SLEEP 0x00000000 +#define AONWUC_AUX_WAKEUP 0x00000001 +#define AONWUC_AUX_ALLOW_SLEEP 0x00000000 //***************************************************************************** // @@ -158,42 +157,41 @@ extern "C" // AONWUCPowerStatusGet() . // //***************************************************************************** -#define AONWUC_OSC_GBIAS_REQ 0x00400000 // OSC is requesting GBias -#define AONWUC_AUX_GBIAS_REQ 0x00200000 // AUX is requesting GBias -#define AONWUC_MCU_GBIAS_REQ 0x00100000 // MCU is requesting GBias -#define AONWUC_OSC_BGAP_REQ 0x00040000 // OSC is requesting BGap -#define AONWUC_AUX_BGAP_REQ 0x00020000 // AUX is requesting BGap -#define AONWUC_MCU_BGAP_REQ 0x00010000 // MCU is requesting BGap -#define AONWUC_GBIAS_ON 0x00002000 // Global Bias is on -#define AONWUC_BGAP_ON 0x00001000 // Band Gap is on -#define AONWUC_AUX_POWER_DOWN 0x00000200 // AUX is in powerdown mode -#define AONWUC_MCU_POWER_DOWN 0x00000100 // MCU is in powerdown mode -#define AONWUC_JTAG_POWER_ON 0x00000040 // JTAG is powered on -#define AONWUC_AUX_POWER_ON 0x00000020 // AUX is powered on -#define AONWUC_MCU_POWER_ON 0x00000010 // MCU is powered on -#define AONWUC_SPLY_POWER_DOWN 0x00000001 // Power supply is in power down - +#define AONWUC_OSC_GBIAS_REQ 0x00400000 // OSC is requesting GBias +#define AONWUC_AUX_GBIAS_REQ 0x00200000 // AUX is requesting GBias +#define AONWUC_MCU_GBIAS_REQ 0x00100000 // MCU is requesting GBias +#define AONWUC_OSC_BGAP_REQ 0x00040000 // OSC is requesting BGap +#define AONWUC_AUX_BGAP_REQ 0x00020000 // AUX is requesting BGap +#define AONWUC_MCU_BGAP_REQ 0x00010000 // MCU is requesting BGap +#define AONWUC_GBIAS_ON 0x00002000 // Global Bias is on +#define AONWUC_BGAP_ON 0x00001000 // Band Gap is on +#define AONWUC_AUX_POWER_DOWN 0x00000200 // AUX is in powerdown mode +#define AONWUC_MCU_POWER_DOWN 0x00000100 // MCU is in powerdown mode +#define AONWUC_JTAG_POWER_ON 0x00000040 // JTAG is powered on +#define AONWUC_AUX_POWER_ON 0x00000020 // AUX is powered on +#define AONWUC_MCU_POWER_ON 0x00000010 // MCU is powered on +#define AONWUC_SPLY_POWER_DOWN 0x00000001 // Power supply is in power down //***************************************************************************** // // RAM repair status bits. Values are returned by AOXWUCRamRepairStatusGet() . // //***************************************************************************** -#define MCU_RAMREPAIR_DONE 0x00000001 -#define AUX_RAMREPAIR_DONE 0x00000002 +#define MCU_RAMREPAIR_DONE 0x00000001 +#define AUX_RAMREPAIR_DONE 0x00000002 //***************************************************************************** //***************************************************************************** -#define RC_RATE_MAX 768 // Maximum recharge rate for the +#define RC_RATE_MAX 768 // Maximum recharge rate for the // recharge controller. -#define RC_RATE_MIN 2 // Minimum recharge rate for the +#define RC_RATE_MIN 2 // Minimum recharge rate for the // recharge controller. //***************************************************************************** -#define AONWUC_MCU_RESET_SRC 0x00000002 // MCU reset source can be SW or +#define AONWUC_MCU_RESET_SRC 0x00000002 // MCU reset source can be SW or // JTAG -#define AONWUC_MCU_WARM_RESET 0x00000001 // MCU reset type and can be warm +#define AONWUC_MCU_WARM_RESET 0x00000001 // MCU reset type and can be warm // or not warm. //***************************************************************************** @@ -235,8 +233,7 @@ AONWUCMcuPowerDownConfig(uint32_t ui32ClkSrc) ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_MCUCLK); ui32Reg &= ~AON_WUC_MCUCLK_PWR_DWN_SRC_M; HWREG(AON_WUC_BASE + AON_WUC_O_MCUCLK) = ui32Reg | - (ui32ClkSrc << - AON_WUC_MCUCLK_PWR_DWN_SRC_S); + (ui32ClkSrc << AON_WUC_MCUCLK_PWR_DWN_SRC_S); } //***************************************************************************** @@ -338,7 +335,6 @@ AONWUCMcuSRamConfig(uint32_t ui32Retention) HWREG(AON_WUC_BASE + AON_WUC_O_MCUCFG) = ui32Reg; } - //***************************************************************************** // //! \brief Return the clock configuration for the AUX domain. @@ -399,11 +395,9 @@ AONWUCAuxPowerDownConfig(uint32_t ui32ClkSrc) ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK); ui32Reg &= ~AON_WUC_AUXCLK_PWR_DWN_SRC_M; HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK) = ui32Reg | - (ui32ClkSrc << - AON_WUC_AUXCLK_PWR_DWN_SRC_S); + (ui32ClkSrc << AON_WUC_AUXCLK_PWR_DWN_SRC_S); } - //***************************************************************************** // //! \brief Configure the retention on the AUX SRAM. @@ -795,7 +789,6 @@ AONWUCJtagPowerOff(void) HWREG(AON_WUC_BASE + AON_WUC_O_JTAGCFG) = 0; } - //***************************************************************************** // // Support for DriverLib in ROM: @@ -805,16 +798,16 @@ AONWUCJtagPowerOff(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AONWUCAuxReset -#undef AONWUCAuxReset -#define AONWUCAuxReset ROM_AONWUCAuxReset +#undef AONWUCAuxReset +#define AONWUCAuxReset ROM_AONWUCAuxReset #endif #ifdef ROM_AONWUCRechargeCtrlConfigSet -#undef AONWUCRechargeCtrlConfigSet -#define AONWUCRechargeCtrlConfigSet ROM_AONWUCRechargeCtrlConfigSet +#undef AONWUCRechargeCtrlConfigSet +#define AONWUCRechargeCtrlConfigSet ROM_AONWUCRechargeCtrlConfigSet #endif #ifdef ROM_AONWUCOscConfig -#undef AONWUCOscConfig -#define AONWUCOscConfig ROM_AONWUCOscConfig +#undef AONWUCOscConfig +#define AONWUCOscConfig ROM_AONWUCOscConfig #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_adc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_adc.h index 34a0557..c5a3665 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_adc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_adc.h @@ -1,41 +1,41 @@ /****************************************************************************** -* Filename: aux_adc.h -* Revised: 2018-02-07 09:45:39 +0100 (Wed, 07 Feb 2018) -* Revision: 51437 -* -* Description: Defines and prototypes for the AUX Analog-to-Digital -* Converter -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aux_adc.h + * Revised: 2018-02-07 09:45:39 +0100 (Wed, 07 Feb 2018) + * Revision: 51437 + * + * Description: Defines and prototypes for the AUX Analog-to-Digital + * Converter + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -56,19 +56,18 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_event.h" #include "../inc/hw_adi.h" #include "../inc/hw_adi_4_aux.h" #include "../inc/hw_aux_anaif.h" +#include "../inc/hw_event.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "rom.h" +#include +#include //***************************************************************************** // @@ -84,17 +83,17 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AUXADCDisable NOROM_AUXADCDisable -#define AUXADCEnableAsync NOROM_AUXADCEnableAsync -#define AUXADCEnableSync NOROM_AUXADCEnableSync -#define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling -#define AUXADCFlushFifo NOROM_AUXADCFlushFifo -#define AUXADCReadFifo NOROM_AUXADCReadFifo -#define AUXADCPopFifo NOROM_AUXADCPopFifo -#define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain -#define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset -#define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts -#define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue +#define AUXADCDisable NOROM_AUXADCDisable +#define AUXADCEnableAsync NOROM_AUXADCEnableAsync +#define AUXADCEnableSync NOROM_AUXADCEnableSync +#define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling +#define AUXADCFlushFifo NOROM_AUXADCFlushFifo +#define AUXADCReadFifo NOROM_AUXADCReadFifo +#define AUXADCPopFifo NOROM_AUXADCPopFifo +#define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain +#define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset +#define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts +#define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue #define AUXADCAdjustValueForGainAndOffset NOROM_AUXADCAdjustValueForGainAndOffset #define AUXADCUnadjustValueForGainAndOffset NOROM_AUXADCUnadjustValueForGainAndOffset #endif @@ -104,62 +103,61 @@ extern "C" // Defines for ADC reference sources. // //***************************************************************************** -#define AUXADC_REF_FIXED (0 << ADI_4_AUX_ADCREF0_SRC_S) -#define AUXADC_REF_VDDS_REL (1 << ADI_4_AUX_ADCREF0_SRC_S) +#define AUXADC_REF_FIXED (0 << ADI_4_AUX_ADCREF0_SRC_S) +#define AUXADC_REF_VDDS_REL (1 << ADI_4_AUX_ADCREF0_SRC_S) //***************************************************************************** // // Defines for the ADC FIFO status bits. // //***************************************************************************** -#define AUXADC_FIFO_EMPTY_M (AUX_ANAIF_ADCFIFOSTAT_EMPTY_M) -#define AUXADC_FIFO_ALMOST_FULL_M (AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M) -#define AUXADC_FIFO_FULL_M (AUX_ANAIF_ADCFIFOSTAT_FULL_M) -#define AUXADC_FIFO_UNDERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M) -#define AUXADC_FIFO_OVERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M) +#define AUXADC_FIFO_EMPTY_M (AUX_ANAIF_ADCFIFOSTAT_EMPTY_M) +#define AUXADC_FIFO_ALMOST_FULL_M (AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M) +#define AUXADC_FIFO_FULL_M (AUX_ANAIF_ADCFIFOSTAT_FULL_M) +#define AUXADC_FIFO_UNDERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M) +#define AUXADC_FIFO_OVERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M) //***************************************************************************** // // Defines for supported ADC triggers. // //***************************************************************************** -#define AUXADC_TRIGGER_MANUAL (EVENT_AUXSEL0_EV_NONE) -#define AUXADC_TRIGGER_GPT0A (EVENT_AUXSEL0_EV_GPT0A) -#define AUXADC_TRIGGER_GPT0B (EVENT_AUXSEL0_EV_GPT0B) -#define AUXADC_TRIGGER_GPT1A (EVENT_AUXSEL0_EV_GPT1A) -#define AUXADC_TRIGGER_GPT1B (EVENT_AUXSEL0_EV_GPT1B) -#define AUXADC_TRIGGER_GPT2A (EVENT_AUXSEL0_EV_GPT2A) -#define AUXADC_TRIGGER_GPT2B (EVENT_AUXSEL0_EV_GPT2B) -#define AUXADC_TRIGGER_GPT3A (EVENT_AUXSEL0_EV_GPT3A) -#define AUXADC_TRIGGER_GPT3B (EVENT_AUXSEL0_EV_GPT3B) +#define AUXADC_TRIGGER_MANUAL (EVENT_AUXSEL0_EV_NONE) +#define AUXADC_TRIGGER_GPT0A (EVENT_AUXSEL0_EV_GPT0A) +#define AUXADC_TRIGGER_GPT0B (EVENT_AUXSEL0_EV_GPT0B) +#define AUXADC_TRIGGER_GPT1A (EVENT_AUXSEL0_EV_GPT1A) +#define AUXADC_TRIGGER_GPT1B (EVENT_AUXSEL0_EV_GPT1B) +#define AUXADC_TRIGGER_GPT2A (EVENT_AUXSEL0_EV_GPT2A) +#define AUXADC_TRIGGER_GPT2B (EVENT_AUXSEL0_EV_GPT2B) +#define AUXADC_TRIGGER_GPT3A (EVENT_AUXSEL0_EV_GPT3A) +#define AUXADC_TRIGGER_GPT3B (EVENT_AUXSEL0_EV_GPT3B) //***************************************************************************** // // Defines for ADC sampling type for synchronous operation. // //***************************************************************************** -#define AUXADC_SAMPLE_TIME_2P7_US 3 -#define AUXADC_SAMPLE_TIME_5P3_US 4 -#define AUXADC_SAMPLE_TIME_10P6_US 5 -#define AUXADC_SAMPLE_TIME_21P3_US 6 -#define AUXADC_SAMPLE_TIME_42P6_US 7 -#define AUXADC_SAMPLE_TIME_85P3_US 8 -#define AUXADC_SAMPLE_TIME_170_US 9 -#define AUXADC_SAMPLE_TIME_341_US 10 -#define AUXADC_SAMPLE_TIME_682_US 11 -#define AUXADC_SAMPLE_TIME_1P37_MS 12 -#define AUXADC_SAMPLE_TIME_2P73_MS 13 -#define AUXADC_SAMPLE_TIME_5P46_MS 14 -#define AUXADC_SAMPLE_TIME_10P9_MS 15 +#define AUXADC_SAMPLE_TIME_2P7_US 3 +#define AUXADC_SAMPLE_TIME_5P3_US 4 +#define AUXADC_SAMPLE_TIME_10P6_US 5 +#define AUXADC_SAMPLE_TIME_21P3_US 6 +#define AUXADC_SAMPLE_TIME_42P6_US 7 +#define AUXADC_SAMPLE_TIME_85P3_US 8 +#define AUXADC_SAMPLE_TIME_170_US 9 +#define AUXADC_SAMPLE_TIME_341_US 10 +#define AUXADC_SAMPLE_TIME_682_US 11 +#define AUXADC_SAMPLE_TIME_1P37_MS 12 +#define AUXADC_SAMPLE_TIME_2P73_MS 13 +#define AUXADC_SAMPLE_TIME_5P46_MS 14 +#define AUXADC_SAMPLE_TIME_10P9_MS 15 //***************************************************************************** // // Equivalent voltages for fixed ADC reference, in microvolts. // //***************************************************************************** -#define AUXADC_FIXED_REF_VOLTAGE_NORMAL 4300000 -#define AUXADC_FIXED_REF_VOLTAGE_UNSCALED 1478500 - +#define AUXADC_FIXED_REF_VOLTAGE_NORMAL 4300000 +#define AUXADC_FIXED_REF_VOLTAGE_UNSCALED 1478500 //***************************************************************************** // @@ -167,7 +165,6 @@ extern "C" // //***************************************************************************** - //***************************************************************************** // //! \brief Disables the ADC. @@ -517,55 +514,55 @@ extern int32_t AUXADCUnadjustValueForGainAndOffset(int32_t adcValue, int32_t gai #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AUXADCDisable -#undef AUXADCDisable -#define AUXADCDisable ROM_AUXADCDisable +#undef AUXADCDisable +#define AUXADCDisable ROM_AUXADCDisable #endif #ifdef ROM_AUXADCEnableAsync -#undef AUXADCEnableAsync -#define AUXADCEnableAsync ROM_AUXADCEnableAsync +#undef AUXADCEnableAsync +#define AUXADCEnableAsync ROM_AUXADCEnableAsync #endif #ifdef ROM_AUXADCEnableSync -#undef AUXADCEnableSync -#define AUXADCEnableSync ROM_AUXADCEnableSync +#undef AUXADCEnableSync +#define AUXADCEnableSync ROM_AUXADCEnableSync #endif #ifdef ROM_AUXADCDisableInputScaling -#undef AUXADCDisableInputScaling -#define AUXADCDisableInputScaling ROM_AUXADCDisableInputScaling +#undef AUXADCDisableInputScaling +#define AUXADCDisableInputScaling ROM_AUXADCDisableInputScaling #endif #ifdef ROM_AUXADCFlushFifo -#undef AUXADCFlushFifo -#define AUXADCFlushFifo ROM_AUXADCFlushFifo +#undef AUXADCFlushFifo +#define AUXADCFlushFifo ROM_AUXADCFlushFifo #endif #ifdef ROM_AUXADCReadFifo -#undef AUXADCReadFifo -#define AUXADCReadFifo ROM_AUXADCReadFifo +#undef AUXADCReadFifo +#define AUXADCReadFifo ROM_AUXADCReadFifo #endif #ifdef ROM_AUXADCPopFifo -#undef AUXADCPopFifo -#define AUXADCPopFifo ROM_AUXADCPopFifo +#undef AUXADCPopFifo +#define AUXADCPopFifo ROM_AUXADCPopFifo #endif #ifdef ROM_AUXADCGetAdjustmentGain -#undef AUXADCGetAdjustmentGain -#define AUXADCGetAdjustmentGain ROM_AUXADCGetAdjustmentGain +#undef AUXADCGetAdjustmentGain +#define AUXADCGetAdjustmentGain ROM_AUXADCGetAdjustmentGain #endif #ifdef ROM_AUXADCGetAdjustmentOffset -#undef AUXADCGetAdjustmentOffset -#define AUXADCGetAdjustmentOffset ROM_AUXADCGetAdjustmentOffset +#undef AUXADCGetAdjustmentOffset +#define AUXADCGetAdjustmentOffset ROM_AUXADCGetAdjustmentOffset #endif #ifdef ROM_AUXADCValueToMicrovolts -#undef AUXADCValueToMicrovolts -#define AUXADCValueToMicrovolts ROM_AUXADCValueToMicrovolts +#undef AUXADCValueToMicrovolts +#define AUXADCValueToMicrovolts ROM_AUXADCValueToMicrovolts #endif #ifdef ROM_AUXADCMicrovoltsToValue -#undef AUXADCMicrovoltsToValue -#define AUXADCMicrovoltsToValue ROM_AUXADCMicrovoltsToValue +#undef AUXADCMicrovoltsToValue +#define AUXADCMicrovoltsToValue ROM_AUXADCMicrovoltsToValue #endif #ifdef ROM_AUXADCAdjustValueForGainAndOffset -#undef AUXADCAdjustValueForGainAndOffset +#undef AUXADCAdjustValueForGainAndOffset #define AUXADCAdjustValueForGainAndOffset ROM_AUXADCAdjustValueForGainAndOffset #endif #ifdef ROM_AUXADCUnadjustValueForGainAndOffset -#undef AUXADCUnadjustValueForGainAndOffset +#undef AUXADCUnadjustValueForGainAndOffset #define AUXADCUnadjustValueForGainAndOffset ROM_AUXADCUnadjustValueForGainAndOffset #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_smph.h index a83b619..d2c25b4 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_smph.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_smph.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aux_smph.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the AUX Semaphore -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aux_smph.h + * Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) + * Revision: 47343 + * + * Description: Defines and prototypes for the AUX Semaphore + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,24 +55,23 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" #include "../inc/hw_aux_smph.h" #include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "debug.h" +#include +#include //***************************************************************************** // // General constants and defines // //***************************************************************************** -#define AUX_SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed -#define AUX_SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed +#define AUX_SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed +#define AUX_SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed //***************************************************************************** // @@ -80,14 +79,14 @@ extern "C" // as the ui32Semaphore parameter. // //***************************************************************************** -#define AUX_SMPH_0 0 // AUX Semaphore 0 -#define AUX_SMPH_1 1 // AUX Semaphore 1 -#define AUX_SMPH_2 2 // AUX Semaphore 2 -#define AUX_SMPH_3 3 // AUX Semaphore 3 -#define AUX_SMPH_4 4 // AUX Semaphore 4 -#define AUX_SMPH_5 5 // AUX Semaphore 5 -#define AUX_SMPH_6 6 // AUX Semaphore 6 -#define AUX_SMPH_7 7 // AUX Semaphore 7 +#define AUX_SMPH_0 0 // AUX Semaphore 0 +#define AUX_SMPH_1 1 // AUX Semaphore 1 +#define AUX_SMPH_2 2 // AUX Semaphore 2 +#define AUX_SMPH_3 3 // AUX Semaphore 3 +#define AUX_SMPH_4 4 // AUX Semaphore 4 +#define AUX_SMPH_5 5 // AUX Semaphore 5 +#define AUX_SMPH_6 6 // AUX Semaphore 6 +#define AUX_SMPH_7 7 // AUX Semaphore 7 //***************************************************************************** // @@ -138,7 +137,7 @@ AUXSMPHAcquire(uint32_t ui32Semaphore) // Semaphore register reads 1 when lock was acquired otherwise 0 // (i.e. AUX_SMPH_CLAIMED). while (HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore) == - AUX_SMPH_CLAIMED) + AUX_SMPH_CLAIMED) { } } diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_tdc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_tdc.h index 4a6691c..ebb205b 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_tdc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_tdc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aux_tdc.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Defines and prototypes for the AUX Time-to-Digital Converter -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aux_tdc.h + * Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) + * Revision: 49096 + * + * Description: Defines and prototypes for the AUX Time-to-Digital Converter + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,17 +55,16 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aux_tdc.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_aux_tdc.h" -#include "debug.h" //***************************************************************************** // @@ -81,8 +80,8 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AUXTDCConfigSet NOROM_AUXTDCConfigSet -#define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone +#define AUXTDCConfigSet NOROM_AUXTDCConfigSet +#define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone #endif //***************************************************************************** @@ -90,132 +89,132 @@ extern "C" // Defines for the status of a AUX TDC measurement. // //***************************************************************************** -#define AUX_TDC_BUSY 0x00000001 -#define AUX_TDC_TIMEOUT 0x00000002 -#define AUX_TDC_DONE 0x00000004 +#define AUX_TDC_BUSY 0x00000001 +#define AUX_TDC_TIMEOUT 0x00000002 +#define AUX_TDC_DONE 0x00000004 //***************************************************************************** // // Defines for the control of a AUX TDC. // //***************************************************************************** -#define AUX_TDC_RUNSYNC 0x00000001 -#define AUX_TDC_RUN 0x00000002 -#define AUX_TDC_ABORT 0x00000003 +#define AUX_TDC_RUNSYNC 0x00000001 +#define AUX_TDC_RUN 0x00000002 +#define AUX_TDC_ABORT 0x00000003 //***************************************************************************** // // Defines for possible states of the TDC internal state machine. // //***************************************************************************** -#define AUXTDC_WAIT_START (AUX_TDC_STAT_STATE_WAIT_START) -#define AUXTDC_WAIT_START_CNTEN (AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN) -#define AUXTDC_IDLE (AUX_TDC_STAT_STATE_IDLE) -#define AUXTDC_CLRCNT (AUX_TDC_STAT_STATE_CLR_CNT) -#define AUXTDC_WAIT_STOP (AUX_TDC_STAT_STATE_WAIT_STOP) -#define AUXTDC_WAIT_STOP_CNTDOWN (AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN) -#define AUXTDC_GETRESULTS (AUX_TDC_STAT_STATE_GET_RESULT) -#define AUXTDC_POR (AUX_TDC_STAT_STATE_POR) -#define AUXTDC_WAIT_CLRCNT_DONE (AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE) -#define AUXTDC_START_FALL (AUX_TDC_STAT_STATE_START_FALL) -#define AUXTDC_FORCE_STOP (AUX_TDC_STAT_STATE_FORCE_STOP) +#define AUXTDC_WAIT_START (AUX_TDC_STAT_STATE_WAIT_START) +#define AUXTDC_WAIT_START_CNTEN (AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN) +#define AUXTDC_IDLE (AUX_TDC_STAT_STATE_IDLE) +#define AUXTDC_CLRCNT (AUX_TDC_STAT_STATE_CLR_CNT) +#define AUXTDC_WAIT_STOP (AUX_TDC_STAT_STATE_WAIT_STOP) +#define AUXTDC_WAIT_STOP_CNTDOWN (AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN) +#define AUXTDC_GETRESULTS (AUX_TDC_STAT_STATE_GET_RESULT) +#define AUXTDC_POR (AUX_TDC_STAT_STATE_POR) +#define AUXTDC_WAIT_CLRCNT_DONE (AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE) +#define AUXTDC_START_FALL (AUX_TDC_STAT_STATE_START_FALL) +#define AUXTDC_FORCE_STOP (AUX_TDC_STAT_STATE_FORCE_STOP) //***************************************************************************** // // Defines for controlling the AUX TDC. Values can be passed to AUXTDCConfigSet(). // //***************************************************************************** -#define AUXTDC_STOPPOL_RIS (AUX_TDC_TRIGSRC_STOP_POL_HIGH) // Rising edge polarity for stop event -#define AUXTDC_STOPPOL_FALL (AUX_TDC_TRIGSRC_STOP_POL_LOW) // Falling edge polarity for stop event +#define AUXTDC_STOPPOL_RIS (AUX_TDC_TRIGSRC_STOP_POL_HIGH) // Rising edge polarity for stop event +#define AUXTDC_STOPPOL_FALL (AUX_TDC_TRIGSRC_STOP_POL_LOW) // Falling edge polarity for stop event -#define AUXTDC_STOP_AUXIO0 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0) -#define AUXTDC_STOP_AUXIO1 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1) -#define AUXTDC_STOP_AUXIO2 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2) -#define AUXTDC_STOP_AUXIO3 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3) -#define AUXTDC_STOP_AUXIO4 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4) -#define AUXTDC_STOP_AUXIO5 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5) -#define AUXTDC_STOP_AUXIO6 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6) -#define AUXTDC_STOP_AUXIO7 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7) -#define AUXTDC_STOP_AUXIO8 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8) -#define AUXTDC_STOP_AUXIO9 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9) -#define AUXTDC_STOP_AUXIO10 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10) -#define AUXTDC_STOP_AUXIO11 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11) -#define AUXTDC_STOP_AUXIO12 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12) -#define AUXTDC_STOP_AUXIO13 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13) -#define AUXTDC_STOP_AUXIO14 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14) -#define AUXTDC_STOP_AUXIO15 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15) -#define AUXTDC_STOP_ADC_DONE (AUX_TDC_TRIGSRC_STOP_SRC_ADC_DONE) -#define AUXTDC_STOP_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_STOP_SRC_ADC_FIFO_ALMOST_FULL) -#define AUXTDC_STOP_AON_PROG_WU (AUX_TDC_TRIGSRC_STOP_SRC_AON_PROG_WU) -#define AUXTDC_STOP_AON_SW (AUX_TDC_TRIGSRC_STOP_SRC_AON_SW) -#define AUXTDC_STOP_ISRC_RESET (AUX_TDC_TRIGSRC_STOP_SRC_ISRC_RESET) -#define AUXTDC_STOP_OBSMUX0 (AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX0) -#define AUXTDC_STOP_OBSMUX1 (AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX1) -#define AUXTDC_STOP_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_STOP_SRC_SMPH_AUTOTAKE_DONE) -#define AUXTDC_STOP_TDC_PRE (AUX_TDC_TRIGSRC_STOP_SRC_TDC_PRE) -#define AUXTDC_STOP_TIMER0_EV (AUX_TDC_TRIGSRC_STOP_SRC_TIMER0_EV) -#define AUXTDC_STOP_TIMER1_EV (AUX_TDC_TRIGSRC_STOP_SRC_TIMER1_EV) -#define AUXTDC_STOP_AON_RTC_CH2 (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2) -#define AUXTDC_STOP_AUX_COMPA (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA) -#define AUXTDC_STOP_AUX_COMPB (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB) -#define AUXTDC_STOP_ACLK_REF (AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF) -#define AUXTDC_STOP_MCU_EV (AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV) +#define AUXTDC_STOP_AUXIO0 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0) +#define AUXTDC_STOP_AUXIO1 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1) +#define AUXTDC_STOP_AUXIO2 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2) +#define AUXTDC_STOP_AUXIO3 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3) +#define AUXTDC_STOP_AUXIO4 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4) +#define AUXTDC_STOP_AUXIO5 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5) +#define AUXTDC_STOP_AUXIO6 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6) +#define AUXTDC_STOP_AUXIO7 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7) +#define AUXTDC_STOP_AUXIO8 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8) +#define AUXTDC_STOP_AUXIO9 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9) +#define AUXTDC_STOP_AUXIO10 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10) +#define AUXTDC_STOP_AUXIO11 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11) +#define AUXTDC_STOP_AUXIO12 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12) +#define AUXTDC_STOP_AUXIO13 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13) +#define AUXTDC_STOP_AUXIO14 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14) +#define AUXTDC_STOP_AUXIO15 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15) +#define AUXTDC_STOP_ADC_DONE (AUX_TDC_TRIGSRC_STOP_SRC_ADC_DONE) +#define AUXTDC_STOP_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_STOP_SRC_ADC_FIFO_ALMOST_FULL) +#define AUXTDC_STOP_AON_PROG_WU (AUX_TDC_TRIGSRC_STOP_SRC_AON_PROG_WU) +#define AUXTDC_STOP_AON_SW (AUX_TDC_TRIGSRC_STOP_SRC_AON_SW) +#define AUXTDC_STOP_ISRC_RESET (AUX_TDC_TRIGSRC_STOP_SRC_ISRC_RESET) +#define AUXTDC_STOP_OBSMUX0 (AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX0) +#define AUXTDC_STOP_OBSMUX1 (AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX1) +#define AUXTDC_STOP_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_STOP_SRC_SMPH_AUTOTAKE_DONE) +#define AUXTDC_STOP_TDC_PRE (AUX_TDC_TRIGSRC_STOP_SRC_TDC_PRE) +#define AUXTDC_STOP_TIMER0_EV (AUX_TDC_TRIGSRC_STOP_SRC_TIMER0_EV) +#define AUXTDC_STOP_TIMER1_EV (AUX_TDC_TRIGSRC_STOP_SRC_TIMER1_EV) +#define AUXTDC_STOP_AON_RTC_CH2 (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2) +#define AUXTDC_STOP_AUX_COMPA (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA) +#define AUXTDC_STOP_AUX_COMPB (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB) +#define AUXTDC_STOP_ACLK_REF (AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF) +#define AUXTDC_STOP_MCU_EV (AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV) -#define AUXTDC_STARTPOL_RIS (AUX_TDC_TRIGSRC_START_POL_HIGH) // Rising edge polarity for start event -#define AUXTDC_STARTPOL_FALL (AUX_TDC_TRIGSRC_START_POL_LOW) // Falling edge polarity for start event +#define AUXTDC_STARTPOL_RIS (AUX_TDC_TRIGSRC_START_POL_HIGH) // Rising edge polarity for start event +#define AUXTDC_STARTPOL_FALL (AUX_TDC_TRIGSRC_START_POL_LOW) // Falling edge polarity for start event -#define AUXTDC_START_AUXIO0 (AUX_TDC_TRIGSRC_START_SRC_AUXIO0) -#define AUXTDC_START_AUXIO1 (AUX_TDC_TRIGSRC_START_SRC_AUXIO1) -#define AUXTDC_START_AUXIO2 (AUX_TDC_TRIGSRC_START_SRC_AUXIO2) -#define AUXTDC_START_AUXIO3 (AUX_TDC_TRIGSRC_START_SRC_AUXIO3) -#define AUXTDC_START_AUXIO4 (AUX_TDC_TRIGSRC_START_SRC_AUXIO4) -#define AUXTDC_START_AUXIO5 (AUX_TDC_TRIGSRC_START_SRC_AUXIO5) -#define AUXTDC_START_AUXIO6 (AUX_TDC_TRIGSRC_START_SRC_AUXIO6) -#define AUXTDC_START_AUXIO7 (AUX_TDC_TRIGSRC_START_SRC_AUXIO7) -#define AUXTDC_START_AUXIO8 (AUX_TDC_TRIGSRC_START_SRC_AUXIO8) -#define AUXTDC_START_AUXIO9 (AUX_TDC_TRIGSRC_START_SRC_AUXIO9) -#define AUXTDC_START_AUXIO10 (AUX_TDC_TRIGSRC_START_SRC_AUXIO10) -#define AUXTDC_START_AUXIO11 (AUX_TDC_TRIGSRC_START_SRC_AUXIO11) -#define AUXTDC_START_AUXIO12 (AUX_TDC_TRIGSRC_START_SRC_AUXIO12) -#define AUXTDC_START_AUXIO13 (AUX_TDC_TRIGSRC_START_SRC_AUXIO13) -#define AUXTDC_START_AUXIO14 (AUX_TDC_TRIGSRC_START_SRC_AUXIO14) -#define AUXTDC_START_AUXIO15 (AUX_TDC_TRIGSRC_START_SRC_AUXIO15) -#define AUXTDC_START_ADC_DONE (AUX_TDC_TRIGSRC_START_SRC_ADC_DONE) +#define AUXTDC_START_AUXIO0 (AUX_TDC_TRIGSRC_START_SRC_AUXIO0) +#define AUXTDC_START_AUXIO1 (AUX_TDC_TRIGSRC_START_SRC_AUXIO1) +#define AUXTDC_START_AUXIO2 (AUX_TDC_TRIGSRC_START_SRC_AUXIO2) +#define AUXTDC_START_AUXIO3 (AUX_TDC_TRIGSRC_START_SRC_AUXIO3) +#define AUXTDC_START_AUXIO4 (AUX_TDC_TRIGSRC_START_SRC_AUXIO4) +#define AUXTDC_START_AUXIO5 (AUX_TDC_TRIGSRC_START_SRC_AUXIO5) +#define AUXTDC_START_AUXIO6 (AUX_TDC_TRIGSRC_START_SRC_AUXIO6) +#define AUXTDC_START_AUXIO7 (AUX_TDC_TRIGSRC_START_SRC_AUXIO7) +#define AUXTDC_START_AUXIO8 (AUX_TDC_TRIGSRC_START_SRC_AUXIO8) +#define AUXTDC_START_AUXIO9 (AUX_TDC_TRIGSRC_START_SRC_AUXIO9) +#define AUXTDC_START_AUXIO10 (AUX_TDC_TRIGSRC_START_SRC_AUXIO10) +#define AUXTDC_START_AUXIO11 (AUX_TDC_TRIGSRC_START_SRC_AUXIO11) +#define AUXTDC_START_AUXIO12 (AUX_TDC_TRIGSRC_START_SRC_AUXIO12) +#define AUXTDC_START_AUXIO13 (AUX_TDC_TRIGSRC_START_SRC_AUXIO13) +#define AUXTDC_START_AUXIO14 (AUX_TDC_TRIGSRC_START_SRC_AUXIO14) +#define AUXTDC_START_AUXIO15 (AUX_TDC_TRIGSRC_START_SRC_AUXIO15) +#define AUXTDC_START_ADC_DONE (AUX_TDC_TRIGSRC_START_SRC_ADC_DONE) #define AUXTDC_START_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_START_SRC_ADC_FIFO_ALMOST_FULL) -#define AUXTDC_START_AON_PROG_WU (AUX_TDC_TRIGSRC_START_SRC_AON_PROG_WU) -#define AUXTDC_START_AON_SW (AUX_TDC_TRIGSRC_START_SRC_AON_SW) -#define AUXTDC_START_ISRC_RESET (AUX_TDC_TRIGSRC_START_SRC_ISRC_RESET) -#define AUXTDC_START_OBSMUX0 (AUX_TDC_TRIGSRC_START_SRC_OBSMUX0) -#define AUXTDC_START_OBSMUX1 (AUX_TDC_TRIGSRC_START_SRC_OBSMUX1) -#define AUXTDC_START_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_START_SRC_SMPH_AUTOTAKE_DONE) -#define AUXTDC_START_TDC_PRE (AUX_TDC_TRIGSRC_START_SRC_TDC_PRE) -#define AUXTDC_START_TIMER0_EV (AUX_TDC_TRIGSRC_START_SRC_TIMER0_EV) -#define AUXTDC_START_TIMER1_EV (AUX_TDC_TRIGSRC_START_SRC_TIMER1_EV) -#define AUXTDC_START_AON_RTC_CH2 (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2) -#define AUXTDC_START_AUX_COMPA (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA) -#define AUXTDC_START_AUX_COMPB (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB) -#define AUXTDC_START_ACLK_REF (AUX_TDC_TRIGSRC_START_SRC_ACLK_REF) -#define AUXTDC_START_MCU_EV (AUX_TDC_TRIGSRC_START_SRC_MCU_EV) +#define AUXTDC_START_AON_PROG_WU (AUX_TDC_TRIGSRC_START_SRC_AON_PROG_WU) +#define AUXTDC_START_AON_SW (AUX_TDC_TRIGSRC_START_SRC_AON_SW) +#define AUXTDC_START_ISRC_RESET (AUX_TDC_TRIGSRC_START_SRC_ISRC_RESET) +#define AUXTDC_START_OBSMUX0 (AUX_TDC_TRIGSRC_START_SRC_OBSMUX0) +#define AUXTDC_START_OBSMUX1 (AUX_TDC_TRIGSRC_START_SRC_OBSMUX1) +#define AUXTDC_START_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_START_SRC_SMPH_AUTOTAKE_DONE) +#define AUXTDC_START_TDC_PRE (AUX_TDC_TRIGSRC_START_SRC_TDC_PRE) +#define AUXTDC_START_TIMER0_EV (AUX_TDC_TRIGSRC_START_SRC_TIMER0_EV) +#define AUXTDC_START_TIMER1_EV (AUX_TDC_TRIGSRC_START_SRC_TIMER1_EV) +#define AUXTDC_START_AON_RTC_CH2 (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2) +#define AUXTDC_START_AUX_COMPA (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA) +#define AUXTDC_START_AUX_COMPB (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB) +#define AUXTDC_START_ACLK_REF (AUX_TDC_TRIGSRC_START_SRC_ACLK_REF) +#define AUXTDC_START_MCU_EV (AUX_TDC_TRIGSRC_START_SRC_MCU_EV) //***************************************************************************** // // Defines for the possible saturation values set using AUXTDCLimitSet(). // //***************************************************************************** -#define AUXTDC_SAT_4096 (AUX_TDC_SATCFG_LIMIT_R12) -#define AUXTDC_SAT_8192 (AUX_TDC_SATCFG_LIMIT_R13) -#define AUXTDC_SAT_16384 (AUX_TDC_SATCFG_LIMIT_R14) -#define AUXTDC_SAT_32768 (AUX_TDC_SATCFG_LIMIT_R15) -#define AUXTDC_SAT_65536 (AUX_TDC_SATCFG_LIMIT_R16) -#define AUXTDC_SAT_131072 (AUX_TDC_SATCFG_LIMIT_R17) -#define AUXTDC_SAT_262144 (AUX_TDC_SATCFG_LIMIT_R18) -#define AUXTDC_SAT_524288 (AUX_TDC_SATCFG_LIMIT_R19) -#define AUXTDC_SAT_1048576 (AUX_TDC_SATCFG_LIMIT_R20) -#define AUXTDC_SAT_2097152 (AUX_TDC_SATCFG_LIMIT_R21) -#define AUXTDC_SAT_4194304 (AUX_TDC_SATCFG_LIMIT_R22) -#define AUXTDC_SAT_8388608 (AUX_TDC_SATCFG_LIMIT_R23) -#define AUXTDC_SAT_16777216 (AUX_TDC_SATCFG_LIMIT_R24) -#define AUXTDC_NUM_SAT_VALS 16 +#define AUXTDC_SAT_4096 (AUX_TDC_SATCFG_LIMIT_R12) +#define AUXTDC_SAT_8192 (AUX_TDC_SATCFG_LIMIT_R13) +#define AUXTDC_SAT_16384 (AUX_TDC_SATCFG_LIMIT_R14) +#define AUXTDC_SAT_32768 (AUX_TDC_SATCFG_LIMIT_R15) +#define AUXTDC_SAT_65536 (AUX_TDC_SATCFG_LIMIT_R16) +#define AUXTDC_SAT_131072 (AUX_TDC_SATCFG_LIMIT_R17) +#define AUXTDC_SAT_262144 (AUX_TDC_SATCFG_LIMIT_R18) +#define AUXTDC_SAT_524288 (AUX_TDC_SATCFG_LIMIT_R19) +#define AUXTDC_SAT_1048576 (AUX_TDC_SATCFG_LIMIT_R20) +#define AUXTDC_SAT_2097152 (AUX_TDC_SATCFG_LIMIT_R21) +#define AUXTDC_SAT_4194304 (AUX_TDC_SATCFG_LIMIT_R22) +#define AUXTDC_SAT_8388608 (AUX_TDC_SATCFG_LIMIT_R23) +#define AUXTDC_SAT_16777216 (AUX_TDC_SATCFG_LIMIT_R24) +#define AUXTDC_NUM_SAT_VALS 16 //***************************************************************************** // @@ -399,7 +398,9 @@ AUXTDCIdle(uint32_t ui32Base) // Check if the AUX TDC is in the Idle state. return (((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE) ? true : false); + AUX_TDC_STAT_STATE_IDLE) + ? true + : false); } //***************************************************************************** @@ -621,7 +622,7 @@ AUXTDCCounterEnable(uint32_t ui32Base) // Check if the AUX TDC is in idle mode. If not in Idle mode, the counter // will not be enabled. if (!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE)) + AUX_TDC_STAT_STATE_IDLE)) { return false; } @@ -657,7 +658,7 @@ AUXTDCCounterDisable(uint32_t ui32Base) // Check if the AUX TDC is in Idle mode. If not in Idle mode, the counter // will not be disabled. if (!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE)) + AUX_TDC_STAT_STATE_IDLE)) { return false; } @@ -698,7 +699,7 @@ AUXTDCCounterSet(uint32_t ui32Base, uint32_t ui32Events) // Check if the AUX TDC is in idle mode. If not in idle mode, the counter // will not be disabled. if (!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE)) + AUX_TDC_STAT_STATE_IDLE)) { return false; } @@ -747,12 +748,12 @@ AUXTDCCounterGet(uint32_t ui32Base) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AUXTDCConfigSet -#undef AUXTDCConfigSet -#define AUXTDCConfigSet ROM_AUXTDCConfigSet +#undef AUXTDCConfigSet +#define AUXTDCConfigSet ROM_AUXTDCConfigSet #endif #ifdef ROM_AUXTDCMeasurementDone -#undef AUXTDCMeasurementDone -#define AUXTDCMeasurementDone ROM_AUXTDCMeasurementDone +#undef AUXTDCMeasurementDone +#define AUXTDCMeasurementDone ROM_AUXTDCMeasurementDone #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_timer.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_timer.h index 45289b7..f9f4a2b 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_timer.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_timer.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aux_timer.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Defines and prototypes for the AUX Timer -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aux_timer.h + * Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) + * Revision: 49096 + * + * Description: Defines and prototypes for the AUX Timer + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,18 +55,17 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" +#include "../inc/hw_aux_timer.h" #include "../inc/hw_ints.h" #include "../inc/hw_memmap.h" -#include "../inc/hw_aux_timer.h" +#include "../inc/hw_types.h" #include "debug.h" #include "interrupt.h" +#include +#include //***************************************************************************** // @@ -82,11 +81,11 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AUXTimerConfigure NOROM_AUXTimerConfigure -#define AUXTimerStart NOROM_AUXTimerStart -#define AUXTimerStop NOROM_AUXTimerStop -#define AUXTimerPrescaleSet NOROM_AUXTimerPrescaleSet -#define AUXTimerPrescaleGet NOROM_AUXTimerPrescaleGet +#define AUXTimerConfigure NOROM_AUXTimerConfigure +#define AUXTimerStart NOROM_AUXTimerStart +#define AUXTimerStop NOROM_AUXTimerStop +#define AUXTimerPrescaleSet NOROM_AUXTimerPrescaleSet +#define AUXTimerPrescaleGet NOROM_AUXTimerPrescaleGet #endif //***************************************************************************** @@ -94,45 +93,45 @@ extern "C" // Values that can be passed to AUXTimerConfigure(). // //***************************************************************************** -#define AUX_TIMER_CFG_ONE_SHOT (AUX_TIMER_T0CFG_RELOAD_MAN) // One-shot timer mode -#define AUX_TIMER_CFG_PERIODIC (AUX_TIMER_T0CFG_RELOAD_CONT) // Period timer mode -#define AUX_TIMER_CFG_ONE_SHOT_EDGE_COUNT ((AUX_TIMER_T0CFG_RELOAD_MAN) | (AUX_TIMER_T0CFG_MODE_TICK)) // One-shot timer with edge count -#define AUX_TIMER_CFG_PERIODIC_EDGE_COUNT ((AUX_TIMER_T0CFG_RELOAD_CONT) | (AUX_TIMER_T0CFG_MODE_TICK)) // Periodic timer with edge count -#define AUX_TIMER_CFG_RISING_EDGE (AUX_TIMER_T0CFG_TICK_SRC_POL_RISE) // Count rising edges (used with edge count mode) -#define AUX_TIMER_CFG_FALLING_EDGE (AUX_TIMER_T0CFG_TICK_SRC_POL_FALL) // Count falling edges (used with edge count mode) +#define AUX_TIMER_CFG_ONE_SHOT (AUX_TIMER_T0CFG_RELOAD_MAN) // One-shot timer mode +#define AUX_TIMER_CFG_PERIODIC (AUX_TIMER_T0CFG_RELOAD_CONT) // Period timer mode +#define AUX_TIMER_CFG_ONE_SHOT_EDGE_COUNT ((AUX_TIMER_T0CFG_RELOAD_MAN) | (AUX_TIMER_T0CFG_MODE_TICK)) // One-shot timer with edge count +#define AUX_TIMER_CFG_PERIODIC_EDGE_COUNT ((AUX_TIMER_T0CFG_RELOAD_CONT) | (AUX_TIMER_T0CFG_MODE_TICK)) // Periodic timer with edge count +#define AUX_TIMER_CFG_RISING_EDGE (AUX_TIMER_T0CFG_TICK_SRC_POL_RISE) // Count rising edges (used with edge count mode) +#define AUX_TIMER_CFG_FALLING_EDGE (AUX_TIMER_T0CFG_TICK_SRC_POL_FALL) // Count falling edges (used with edge count mode) -#define AUX_TIMER_CFG_TICK_SRC_RTC_EVENT (AUX_TIMER_T0CFG_TICK_SRC_RTC_CH2_EV) // AON wake-up event -#define AUX_TIMER_CFG_TICK_SRC_CMP_A (AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPA) // Comparator A -#define AUX_TIMER_CFG_TICK_SRC_CMP_B (AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPB) // Comparator B -#define AUX_TIMER_CFG_TICK_SRC_TDCDONE (AUX_TIMER_T0CFG_TICK_SRC_TDC_DONE) // TDC Done -#define AUX_TIMER_CFG_TICK_SRC_TIMER0_EVENT (AUX_TIMER_T1CFG_TICK_SRC_TIMER0_EV) // Timer 0 event -#define AUX_TIMER_CFG_TICK_SRC_TIMER1_EVENT (AUX_TIMER_T0CFG_TICK_SRC_TIMER1_EV) // Timer 1 event +#define AUX_TIMER_CFG_TICK_SRC_RTC_EVENT (AUX_TIMER_T0CFG_TICK_SRC_RTC_CH2_EV) // AON wake-up event +#define AUX_TIMER_CFG_TICK_SRC_CMP_A (AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPA) // Comparator A +#define AUX_TIMER_CFG_TICK_SRC_CMP_B (AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPB) // Comparator B +#define AUX_TIMER_CFG_TICK_SRC_TDCDONE (AUX_TIMER_T0CFG_TICK_SRC_TDC_DONE) // TDC Done +#define AUX_TIMER_CFG_TICK_SRC_TIMER0_EVENT (AUX_TIMER_T1CFG_TICK_SRC_TIMER0_EV) // Timer 0 event +#define AUX_TIMER_CFG_TICK_SRC_TIMER1_EVENT (AUX_TIMER_T0CFG_TICK_SRC_TIMER1_EV) // Timer 1 event #define AUX_TIMER_CFG_TICK_SRC_SMPH_RELEASE (AUX_TIMER_T0CFG_TICK_SRC_SMPH_AUTOTAKE_DONE) // Semaphore release -#define AUX_TIMER_CFG_TICK_SRC_ADC_DONE (AUX_TIMER_T0CFG_TICK_SRC_ADC_DONE) // ADC done -#define AUX_TIMER_CFG_TICK_SRC_RTC_4KHZ (AUX_TIMER_T0CFG_TICK_SRC_RTC_4KHZ) -#define AUX_TIMER_CFG_TICK_SRC_OBSMUX0 (AUX_TIMER_T0CFG_TICK_SRC_OBSMUX0) -#define AUX_TIMER_CFG_TICK_SRC_OBSMUX1 (AUX_TIMER_T0CFG_TICK_SRC_OBSMUX1) -#define AUX_TIMER_CFG_TICK_SRC_AON_SW (AUX_TIMER_T0CFG_TICK_SRC_AON_SW) -#define AUX_TIMER_CFG_TICK_SRC_AON_PROG_WU (AUX_TIMER_T0CFG_TICK_SRC_AON_PROG_WU) -#define AUX_TIMER_CFG_TICK_SRC_AIO0 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO0) // AIO_DAT[ 0] -#define AUX_TIMER_CFG_TICK_SRC_AIO1 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO1) // AIO_DAT[ 1] -#define AUX_TIMER_CFG_TICK_SRC_AIO2 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO2) // AIO_DAT[ 2] -#define AUX_TIMER_CFG_TICK_SRC_AIO3 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO3) // AIO_DAT[ 3] -#define AUX_TIMER_CFG_TICK_SRC_AIO4 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO4) // AIO_DAT[ 4] -#define AUX_TIMER_CFG_TICK_SRC_AIO5 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO5) // AIO_DAT[ 5] -#define AUX_TIMER_CFG_TICK_SRC_AIO6 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO6) // AIO_DAT[ 6] -#define AUX_TIMER_CFG_TICK_SRC_AIO7 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO7) // AIO_DAT[ 7] -#define AUX_TIMER_CFG_TICK_SRC_AIO8 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO8) // AIO_DAT[ 8] -#define AUX_TIMER_CFG_TICK_SRC_AIO9 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO9) // AIO_DAT[ 9] -#define AUX_TIMER_CFG_TICK_SRC_AIO10 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO10) // AIO_DAT[10] -#define AUX_TIMER_CFG_TICK_SRC_AIO11 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO11) // AIO_DAT[11] -#define AUX_TIMER_CFG_TICK_SRC_AIO12 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO12) // AIO_DAT[12] -#define AUX_TIMER_CFG_TICK_SRC_AIO13 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO13) // AIO_DAT[13] -#define AUX_TIMER_CFG_TICK_SRC_AIO14 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO14) // AIO_DAT[14] -#define AUX_TIMER_CFG_TICK_SRC_AIO15 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO15) // AIO_DAT[15] -#define AUX_TIMER_CFG_TICK_SRC_ACLK_REF (AUX_TIMER_T0CFG_TICK_SRC_ACLK_REF) // ACLK_REF_i -#define AUX_TIMER_CFG_TICK_SRC_MCU_EVENT (AUX_TIMER_T0CFG_TICK_SRC_MCU_EVENT) // MCU event -#define AUX_TIMER_CFG_TICK_SRC_ADC_IRQ (AUX_TIMER_T0CFG_TICK_SRC_ADC_IRQ) // DMA done +#define AUX_TIMER_CFG_TICK_SRC_ADC_DONE (AUX_TIMER_T0CFG_TICK_SRC_ADC_DONE) // ADC done +#define AUX_TIMER_CFG_TICK_SRC_RTC_4KHZ (AUX_TIMER_T0CFG_TICK_SRC_RTC_4KHZ) +#define AUX_TIMER_CFG_TICK_SRC_OBSMUX0 (AUX_TIMER_T0CFG_TICK_SRC_OBSMUX0) +#define AUX_TIMER_CFG_TICK_SRC_OBSMUX1 (AUX_TIMER_T0CFG_TICK_SRC_OBSMUX1) +#define AUX_TIMER_CFG_TICK_SRC_AON_SW (AUX_TIMER_T0CFG_TICK_SRC_AON_SW) +#define AUX_TIMER_CFG_TICK_SRC_AON_PROG_WU (AUX_TIMER_T0CFG_TICK_SRC_AON_PROG_WU) +#define AUX_TIMER_CFG_TICK_SRC_AIO0 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO0) // AIO_DAT[ 0] +#define AUX_TIMER_CFG_TICK_SRC_AIO1 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO1) // AIO_DAT[ 1] +#define AUX_TIMER_CFG_TICK_SRC_AIO2 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO2) // AIO_DAT[ 2] +#define AUX_TIMER_CFG_TICK_SRC_AIO3 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO3) // AIO_DAT[ 3] +#define AUX_TIMER_CFG_TICK_SRC_AIO4 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO4) // AIO_DAT[ 4] +#define AUX_TIMER_CFG_TICK_SRC_AIO5 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO5) // AIO_DAT[ 5] +#define AUX_TIMER_CFG_TICK_SRC_AIO6 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO6) // AIO_DAT[ 6] +#define AUX_TIMER_CFG_TICK_SRC_AIO7 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO7) // AIO_DAT[ 7] +#define AUX_TIMER_CFG_TICK_SRC_AIO8 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO8) // AIO_DAT[ 8] +#define AUX_TIMER_CFG_TICK_SRC_AIO9 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO9) // AIO_DAT[ 9] +#define AUX_TIMER_CFG_TICK_SRC_AIO10 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO10) // AIO_DAT[10] +#define AUX_TIMER_CFG_TICK_SRC_AIO11 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO11) // AIO_DAT[11] +#define AUX_TIMER_CFG_TICK_SRC_AIO12 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO12) // AIO_DAT[12] +#define AUX_TIMER_CFG_TICK_SRC_AIO13 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO13) // AIO_DAT[13] +#define AUX_TIMER_CFG_TICK_SRC_AIO14 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO14) // AIO_DAT[14] +#define AUX_TIMER_CFG_TICK_SRC_AIO15 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO15) // AIO_DAT[15] +#define AUX_TIMER_CFG_TICK_SRC_ACLK_REF (AUX_TIMER_T0CFG_TICK_SRC_ACLK_REF) // ACLK_REF_i +#define AUX_TIMER_CFG_TICK_SRC_MCU_EVENT (AUX_TIMER_T0CFG_TICK_SRC_MCU_EVENT) // MCU event +#define AUX_TIMER_CFG_TICK_SRC_ADC_IRQ (AUX_TIMER_T0CFG_TICK_SRC_ADC_IRQ) // DMA done //***************************************************************************** // @@ -140,9 +139,9 @@ extern "C" // parameter. // //***************************************************************************** -#define AUX_TIMER_0 0x0000FFFF // AUX Timer 0 -#define AUX_TIMER_1 0x00FF0000 // AUX Timer 1 -#define AUX_TIMER_BOTH 0x00FFFFFF // AUX Timer Both 0 and 1 +#define AUX_TIMER_0 0x0000FFFF // AUX Timer 0 +#define AUX_TIMER_1 0x00FF0000 // AUX Timer 1 +#define AUX_TIMER_BOTH 0x00FFFFFF // AUX Timer Both 0 and 1 //***************************************************************************** // @@ -150,22 +149,22 @@ extern "C" // AUXTimerPrescaleGet. // //***************************************************************************** -#define AUX_TIMER_PRESCALE_DIV_1 0x00000000 // Prescale division ratio 1 -#define AUX_TIMER_PRESCALE_DIV_2 0x00000001 // Prescale division ratio 2 -#define AUX_TIMER_PRESCALE_DIV_4 0x00000002 // Prescale division ratio 4 -#define AUX_TIMER_PRESCALE_DIV_8 0x00000003 // Prescale division ratio 8 -#define AUX_TIMER_PRESCALE_DIV_16 0x00000004 // Prescale division ratio 16 -#define AUX_TIMER_PRESCALE_DIV_32 0x00000005 // Prescale division ratio 32 -#define AUX_TIMER_PRESCALE_DIV_64 0x00000006 // Prescale division ratio 64 -#define AUX_TIMER_PRESCALE_DIV_128 0x00000007 // Prescale division ratio 128 -#define AUX_TIMER_PRESCALE_DIV_256 0x00000008 // Prescale division ratio 256 -#define AUX_TIMER_PRESCALE_DIV_512 0x00000009 // Prescale division ratio 512 -#define AUX_TIMER_PRESCALE_DIV_1028 0x0000000A // Prescale div. ratio 1028 -#define AUX_TIMER_PRESCALE_DIV_2048 0x0000000B // Prescale div. ratio 2048 -#define AUX_TIMER_PRESCALE_DIV_4096 0x0000000C // Prescale div. ratio 4096 -#define AUX_TIMER_PRESCALE_DIV_8192 0x0000000D // Prescale div. ratio 8192 -#define AUX_TIMER_PRESCALE_DIV_16384 0x0000000E // Prescale div. ratio 16384 -#define AUX_TIMER_PRESCALE_DIV_32768 0x0000000F // Prescale div. ratio 32768 +#define AUX_TIMER_PRESCALE_DIV_1 0x00000000 // Prescale division ratio 1 +#define AUX_TIMER_PRESCALE_DIV_2 0x00000001 // Prescale division ratio 2 +#define AUX_TIMER_PRESCALE_DIV_4 0x00000002 // Prescale division ratio 4 +#define AUX_TIMER_PRESCALE_DIV_8 0x00000003 // Prescale division ratio 8 +#define AUX_TIMER_PRESCALE_DIV_16 0x00000004 // Prescale division ratio 16 +#define AUX_TIMER_PRESCALE_DIV_32 0x00000005 // Prescale division ratio 32 +#define AUX_TIMER_PRESCALE_DIV_64 0x00000006 // Prescale division ratio 64 +#define AUX_TIMER_PRESCALE_DIV_128 0x00000007 // Prescale division ratio 128 +#define AUX_TIMER_PRESCALE_DIV_256 0x00000008 // Prescale division ratio 256 +#define AUX_TIMER_PRESCALE_DIV_512 0x00000009 // Prescale division ratio 512 +#define AUX_TIMER_PRESCALE_DIV_1028 0x0000000A // Prescale div. ratio 1028 +#define AUX_TIMER_PRESCALE_DIV_2048 0x0000000B // Prescale div. ratio 2048 +#define AUX_TIMER_PRESCALE_DIV_4096 0x0000000C // Prescale div. ratio 4096 +#define AUX_TIMER_PRESCALE_DIV_8192 0x0000000D // Prescale div. ratio 8192 +#define AUX_TIMER_PRESCALE_DIV_16384 0x0000000E // Prescale div. ratio 16384 +#define AUX_TIMER_PRESCALE_DIV_32768 0x0000000F // Prescale div. ratio 32768 //***************************************************************************** // @@ -325,9 +324,7 @@ AUXTimerTargetValSet(uint32_t ui32Timer, uint32_t ui32Target) ASSERT(((ui32Timer & AUX_TIMER_0) && (ui32Target <= 65535)) || ((ui32Timer & AUX_TIMER_1) && (ui32Target <= 255))); - ui32Addr = (ui32Timer & AUX_TIMER_0) ? - (AUX_TIMER_BASE + AUX_TIMER_O_T0TARGET) : - (AUX_TIMER_BASE + AUX_TIMER_O_T1TARGET); + ui32Addr = (ui32Timer & AUX_TIMER_0) ? (AUX_TIMER_BASE + AUX_TIMER_O_T0TARGET) : (AUX_TIMER_BASE + AUX_TIMER_O_T1TARGET); HWREG(ui32Addr) = ui32Target; } @@ -355,9 +352,7 @@ AUXTimerTargetValGet(uint32_t ui32Timer) // Check the arguments. ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1)); - return (HWREG((ui32Timer & AUX_TIMER_0) ? - (AUX_TIMER_BASE + AUX_TIMER_O_T0TARGET) : - (AUX_TIMER_BASE + AUX_TIMER_O_T1TARGET))); + return (HWREG((ui32Timer & AUX_TIMER_0) ? (AUX_TIMER_BASE + AUX_TIMER_O_T0TARGET) : (AUX_TIMER_BASE + AUX_TIMER_O_T1TARGET))); } //***************************************************************************** @@ -441,24 +436,24 @@ extern uint32_t AUXTimerPrescaleGet(uint32_t ui32Timer); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AUXTimerConfigure -#undef AUXTimerConfigure -#define AUXTimerConfigure ROM_AUXTimerConfigure +#undef AUXTimerConfigure +#define AUXTimerConfigure ROM_AUXTimerConfigure #endif #ifdef ROM_AUXTimerStart -#undef AUXTimerStart -#define AUXTimerStart ROM_AUXTimerStart +#undef AUXTimerStart +#define AUXTimerStart ROM_AUXTimerStart #endif #ifdef ROM_AUXTimerStop -#undef AUXTimerStop -#define AUXTimerStop ROM_AUXTimerStop +#undef AUXTimerStop +#define AUXTimerStop ROM_AUXTimerStop #endif #ifdef ROM_AUXTimerPrescaleSet -#undef AUXTimerPrescaleSet -#define AUXTimerPrescaleSet ROM_AUXTimerPrescaleSet +#undef AUXTimerPrescaleSet +#define AUXTimerPrescaleSet ROM_AUXTimerPrescaleSet #endif #ifdef ROM_AUXTimerPrescaleGet -#undef AUXTimerPrescaleGet -#define AUXTimerPrescaleGet ROM_AUXTimerPrescaleGet +#undef AUXTimerPrescaleGet +#define AUXTimerPrescaleGet ROM_AUXTimerPrescaleGet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_wuc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_wuc.h index a812536..f05b4f8 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_wuc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/aux_wuc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aon_wuc.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Defines and prototypes for the AUX Wakeup Controller -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_wuc.h + * Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) + * Revision: 49096 + * + * Description: Defines and prototypes for the AUX Wakeup Controller + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //**************************************************************************** // @@ -55,16 +55,15 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aux_wuc.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aux_wuc.h" -#include "debug.h" //***************************************************************************** // @@ -80,10 +79,10 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AUXWUCClockEnable NOROM_AUXWUCClockEnable -#define AUXWUCClockDisable NOROM_AUXWUCClockDisable -#define AUXWUCClockStatus NOROM_AUXWUCClockStatus -#define AUXWUCPowerCtrl NOROM_AUXWUCPowerCtrl +#define AUXWUCClockEnable NOROM_AUXWUCClockEnable +#define AUXWUCClockDisable NOROM_AUXWUCClockDisable +#define AUXWUCClockStatus NOROM_AUXWUCClockStatus +#define AUXWUCPowerCtrl NOROM_AUXWUCPowerCtrl #endif //***************************************************************************** @@ -91,35 +90,35 @@ extern "C" // Defines for the AUX power control. // //***************************************************************************** -#define AUX_WUC_POWER_OFF 0x00000001 -#define AUX_WUC_POWER_DOWN 0x00000002 -#define AUX_WUC_POWER_ACTIVE 0x00000004 +#define AUX_WUC_POWER_OFF 0x00000001 +#define AUX_WUC_POWER_DOWN 0x00000002 +#define AUX_WUC_POWER_ACTIVE 0x00000004 //***************************************************************************** // // Defines for the AUX peripherals clock control. // //***************************************************************************** -#define AUX_WUC_SMPH_CLOCK (AUX_WUC_MODCLKEN0_SMPH_EN) -#define AUX_WUC_AIODIO0_CLOCK (AUX_WUC_MODCLKEN0_AIODIO0_EN) -#define AUX_WUC_AIODIO1_CLOCK (AUX_WUC_MODCLKEN0_AIODIO1_EN) -#define AUX_WUC_TIMER_CLOCK (AUX_WUC_MODCLKEN0_TIMER_EN) -#define AUX_WUC_ANAIF_CLOCK (AUX_WUC_MODCLKEN0_ANAIF_EN) -#define AUX_WUC_TDCIF_CLOCK (AUX_WUC_MODCLKEN0_TDC_EN) -#define AUX_WUC_OSCCTRL_CLOCK (AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_EN) -#define AUX_WUC_ADI_CLOCK (AUX_WUC_MODCLKEN0_AUX_ADI4_EN) -#define AUX_WUC_MODCLK_MASK 0x000000FF +#define AUX_WUC_SMPH_CLOCK (AUX_WUC_MODCLKEN0_SMPH_EN) +#define AUX_WUC_AIODIO0_CLOCK (AUX_WUC_MODCLKEN0_AIODIO0_EN) +#define AUX_WUC_AIODIO1_CLOCK (AUX_WUC_MODCLKEN0_AIODIO1_EN) +#define AUX_WUC_TIMER_CLOCK (AUX_WUC_MODCLKEN0_TIMER_EN) +#define AUX_WUC_ANAIF_CLOCK (AUX_WUC_MODCLKEN0_ANAIF_EN) +#define AUX_WUC_TDCIF_CLOCK (AUX_WUC_MODCLKEN0_TDC_EN) +#define AUX_WUC_OSCCTRL_CLOCK (AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_EN) +#define AUX_WUC_ADI_CLOCK (AUX_WUC_MODCLKEN0_AUX_ADI4_EN) +#define AUX_WUC_MODCLK_MASK 0x000000FF -#define AUX_WUC_TDC_CLOCK 0x00000100 -#define AUX_WUC_ADC_CLOCK 0x00000200 -#define AUX_WUC_REF_CLOCK 0x00000400 +#define AUX_WUC_TDC_CLOCK 0x00000100 +#define AUX_WUC_ADC_CLOCK 0x00000200 +#define AUX_WUC_REF_CLOCK 0x00000400 -#define AUX_WUC_CLOCK_OFF 0x00000000 -#define AUX_WUC_CLOCK_UNSTABLE 0x00000001 -#define AUX_WUC_CLOCK_READY 0x00000011 +#define AUX_WUC_CLOCK_OFF 0x00000000 +#define AUX_WUC_CLOCK_UNSTABLE 0x00000001 +#define AUX_WUC_CLOCK_READY 0x00000011 -#define AUX_WUC_CLOCK_HIFREQ 0x00000000 -#define AUX_WUC_CLOCK_LOFREQ 0x00000001 +#define AUX_WUC_CLOCK_HIFREQ 0x00000000 +#define AUX_WUC_CLOCK_LOFREQ 0x00000001 //***************************************************************************** // @@ -310,20 +309,20 @@ AUXWUCFreezeDisable(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AUXWUCClockEnable -#undef AUXWUCClockEnable -#define AUXWUCClockEnable ROM_AUXWUCClockEnable +#undef AUXWUCClockEnable +#define AUXWUCClockEnable ROM_AUXWUCClockEnable #endif #ifdef ROM_AUXWUCClockDisable -#undef AUXWUCClockDisable -#define AUXWUCClockDisable ROM_AUXWUCClockDisable +#undef AUXWUCClockDisable +#define AUXWUCClockDisable ROM_AUXWUCClockDisable #endif #ifdef ROM_AUXWUCClockStatus -#undef AUXWUCClockStatus -#define AUXWUCClockStatus ROM_AUXWUCClockStatus +#undef AUXWUCClockStatus +#define AUXWUCClockStatus ROM_AUXWUCClockStatus #endif #ifdef ROM_AUXWUCPowerCtrl -#undef AUXWUCPowerCtrl -#define AUXWUCPowerCtrl ROM_AUXWUCPowerCtrl +#undef AUXWUCPowerCtrl +#define AUXWUCPowerCtrl ROM_AUXWUCPowerCtrl #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ccfgread.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ccfgread.h index 3dec1eb..291eb62 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ccfgread.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ccfgread.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: ccfgread.h -* Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) -* Revision: 47152 -* -* Description: API for reading CCFG. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: ccfgread.h + * Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) + * Revision: 47152 + * + * Description: API for reading CCFG. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,15 +55,14 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_ccfg.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ccfg.h" //***************************************************************************** // @@ -71,7 +70,6 @@ extern "C" // //***************************************************************************** - //***************************************************************************** // // API Functions and prototypes @@ -86,11 +84,11 @@ extern "C" // //***************************************************************************** __STATIC_INLINE bool -CCFGRead_DIS_GPRAM( void ) +CCFGRead_DIS_GPRAM(void) { - return (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & - CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) >> - CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S ) ; + return ((HWREG(CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS) & + CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M) >> + CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S); } //***************************************************************************** @@ -101,11 +99,11 @@ CCFGRead_DIS_GPRAM( void ) // //***************************************************************************** __STATIC_INLINE bool -CCFGRead_EXT_LF_CLK_DIO( void ) +CCFGRead_EXT_LF_CLK_DIO(void) { - return (( HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK ) & - CCFG_EXT_LF_CLK_DIO_M ) >> - CCFG_EXT_LF_CLK_DIO_S ) ; + return ((HWREG(CCFG_BASE + CCFG_O_EXT_LF_CLK) & + CCFG_EXT_LF_CLK_DIO_M) >> + CCFG_EXT_LF_CLK_DIO_S); } //***************************************************************************** @@ -113,10 +111,10 @@ CCFGRead_EXT_LF_CLK_DIO( void ) // Defines the possible values returned from CCFGRead_SCLK_LF_OPTION() // //***************************************************************************** -#define CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF ( CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) -#define CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) -#define CCFGREAD_SCLK_LF_OPTION_XOSC_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) -#define CCFGREAD_SCLK_LF_OPTION_RCOSC_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) +#define CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF (CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S) +#define CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF (CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S) +#define CCFGREAD_SCLK_LF_OPTION_XOSC_LF (CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S) +#define CCFGREAD_SCLK_LF_OPTION_RCOSC_LF (CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S) //***************************************************************************** // @@ -131,11 +129,11 @@ CCFGRead_EXT_LF_CLK_DIO( void ) // //***************************************************************************** __STATIC_INLINE uint32_t -CCFGRead_SCLK_LF_OPTION( void ) +CCFGRead_SCLK_LF_OPTION(void) { - return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF ) & - CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> - CCFG_MODE_CONF_SCLK_LF_OPTION_S ) ; + return ((HWREG(CCFG_BASE + CCFG_O_MODE_CONF) & + CCFG_MODE_CONF_SCLK_LF_OPTION_M) >> + CCFG_MODE_CONF_SCLK_LF_OPTION_S); } //***************************************************************************** @@ -143,9 +141,9 @@ CCFGRead_SCLK_LF_OPTION( void ) // Defines the possible values returned from CCFGRead_XOSC_FREQ() // //***************************************************************************** -#define CCFGREAD_XOSC_FREQ_24M ( CCFG_MODE_CONF_XOSC_FREQ_24M >> CCFG_MODE_CONF_XOSC_FREQ_S ) -#define CCFGREAD_XOSC_FREQ_48M ( CCFG_MODE_CONF_XOSC_FREQ_48M >> CCFG_MODE_CONF_XOSC_FREQ_S ) -#define CCFGREAD_XOSC_FREQ_HPOSC ( CCFG_MODE_CONF_XOSC_FREQ_HPOSC >> CCFG_MODE_CONF_XOSC_FREQ_S ) +#define CCFGREAD_XOSC_FREQ_24M (CCFG_MODE_CONF_XOSC_FREQ_24M >> CCFG_MODE_CONF_XOSC_FREQ_S) +#define CCFGREAD_XOSC_FREQ_48M (CCFG_MODE_CONF_XOSC_FREQ_48M >> CCFG_MODE_CONF_XOSC_FREQ_S) +#define CCFGREAD_XOSC_FREQ_HPOSC (CCFG_MODE_CONF_XOSC_FREQ_HPOSC >> CCFG_MODE_CONF_XOSC_FREQ_S) //***************************************************************************** // @@ -160,11 +158,11 @@ CCFGRead_SCLK_LF_OPTION( void ) // //***************************************************************************** __STATIC_INLINE uint32_t -CCFGRead_XOSC_FREQ( void ) +CCFGRead_XOSC_FREQ(void) { - return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF ) & - CCFG_MODE_CONF_XOSC_FREQ_M ) >> - CCFG_MODE_CONF_XOSC_FREQ_S ) ; + return ((HWREG(CCFG_BASE + CCFG_O_MODE_CONF) & + CCFG_MODE_CONF_XOSC_FREQ_M) >> + CCFG_MODE_CONF_XOSC_FREQ_S); } //***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ccfgread_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ccfgread_doc.h index f3175fb..f8e9b82 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ccfgread_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ccfgread_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: ccfgread_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: ccfgread_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup ccfgread_api //! @{ //! \section sec_ccfgread Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/chipinfo.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/chipinfo.h index 9efd02c..b6c9f69 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/chipinfo.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/chipinfo.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: chipinfo.h -* Revised: 2018-06-18 10:26:12 +0200 (Mon, 18 Jun 2018) -* Revision: 52189 -* -* Description: Collection of functions returning chip information. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: chipinfo.h + * Revised: 2018-06-18 10:26:12 +0200 (Mon, 18 Jun 2018) + * Revision: 52189 + * + * Description: Collection of functions returning chip information. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,15 +55,14 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" #include "../inc/hw_fcfg1.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include +#include //***************************************************************************** // @@ -80,10 +79,10 @@ extern "C" //***************************************************************************** #if !defined(DOXYGEN) #define ChipInfo_GetSupportedProtocol_BV NOROM_ChipInfo_GetSupportedProtocol_BV -#define ChipInfo_GetPackageType NOROM_ChipInfo_GetPackageType -#define ChipInfo_GetChipType NOROM_ChipInfo_GetChipType -#define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily -#define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision +#define ChipInfo_GetPackageType NOROM_ChipInfo_GetPackageType +#define ChipInfo_GetChipType NOROM_ChipInfo_GetChipType +#define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily +#define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision #define ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated NOROM_ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated #endif @@ -98,10 +97,10 @@ extern "C" //***************************************************************************** typedef enum { - PROTOCOL_Unknown = 0, //!< None of the known protocols are supported. - PROTOCOLBIT_BLE = 0x02, //!< Bit[1] set, indicates that Bluetooth Low Energy is supported. + PROTOCOL_Unknown = 0, //!< None of the known protocols are supported. + PROTOCOLBIT_BLE = 0x02, //!< Bit[1] set, indicates that Bluetooth Low Energy is supported. PROTOCOLBIT_IEEE_802_15_4 = 0x04, //!< Bit[2] set, indicates that IEEE 802.15.4 is supported. - PROTOCOLBIT_Proprietary = 0x08 //!< Bit[3] set, indicates that proprietary protocols are supported. + PROTOCOLBIT_Proprietary = 0x08 //!< Bit[3] set, indicates that proprietary protocols are supported. } ProtocolBitVector_t; //***************************************************************************** @@ -112,7 +111,7 @@ typedef enum //! Returns \ref ProtocolBitVector_t which is a bit vector indicating supported protocols. // //***************************************************************************** -extern ProtocolBitVector_t ChipInfo_GetSupportedProtocol_BV( void ); +extern ProtocolBitVector_t ChipInfo_GetSupportedProtocol_BV(void); //***************************************************************************** // @@ -123,9 +122,9 @@ extern ProtocolBitVector_t ChipInfo_GetSupportedProtocol_BV( void ); // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_SupportsBLE( void ) +ChipInfo_SupportsBLE(void) { - return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_BLE ) != 0 ); + return ((ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_BLE) != 0); } //***************************************************************************** @@ -137,9 +136,9 @@ ChipInfo_SupportsBLE( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_SupportsIEEE_802_15_4( void ) +ChipInfo_SupportsIEEE_802_15_4(void) { - return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_IEEE_802_15_4 ) != 0 ); + return ((ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_IEEE_802_15_4) != 0); } //***************************************************************************** @@ -151,9 +150,9 @@ ChipInfo_SupportsIEEE_802_15_4( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_SupportsPROPRIETARY( void ) +ChipInfo_SupportsPROPRIETARY(void) { - return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_Proprietary ) != 0 ); + return ((ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_Proprietary) != 0); } //***************************************************************************** @@ -166,13 +165,13 @@ ChipInfo_SupportsPROPRIETARY( void ) //***************************************************************************** typedef enum { - PACKAGE_Unknown = -1, //!< -1 means that current package type is unknown. - PACKAGE_4x4 = 0, //!< 0 means that this is a 4x4 mm QFN (RHB) package. - PACKAGE_5x5 = 1, //!< 1 means that this is a 5x5 mm QFN (RSM) package. - PACKAGE_7x7 = 2, //!< 2 means that this is a 7x7 mm QFN (RGZ) package. - PACKAGE_WAFER = 3, //!< 3 means that this is a wafer sale package (naked die). - PACKAGE_WCSP = 4, //!< 4 means that this is a 2.7x2.7 mm WCSP (YFV). - PACKAGE_7x7_Q1 = 5 //!< 5 means that this is a 7x7 mm QFN package with Wettable Flanks. + PACKAGE_Unknown = -1, //!< -1 means that current package type is unknown. + PACKAGE_4x4 = 0, //!< 0 means that this is a 4x4 mm QFN (RHB) package. + PACKAGE_5x5 = 1, //!< 1 means that this is a 5x5 mm QFN (RSM) package. + PACKAGE_7x7 = 2, //!< 2 means that this is a 7x7 mm QFN (RGZ) package. + PACKAGE_WAFER = 3, //!< 3 means that this is a wafer sale package (naked die). + PACKAGE_WCSP = 4, //!< 4 means that this is a 2.7x2.7 mm WCSP (YFV). + PACKAGE_7x7_Q1 = 5 //!< 5 means that this is a 7x7 mm QFN package with Wettable Flanks. } PackageType_t; //***************************************************************************** @@ -183,7 +182,7 @@ typedef enum //! Returns \ref PackageType_t // //***************************************************************************** -extern PackageType_t ChipInfo_GetPackageType( void ); +extern PackageType_t ChipInfo_GetPackageType(void); //***************************************************************************** // @@ -194,9 +193,9 @@ extern PackageType_t ChipInfo_GetPackageType( void ); // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_PackageTypeIs4x4( void ) +ChipInfo_PackageTypeIs4x4(void) { - return ( ChipInfo_GetPackageType() == PACKAGE_4x4 ); + return (ChipInfo_GetPackageType() == PACKAGE_4x4); } //***************************************************************************** @@ -208,9 +207,9 @@ ChipInfo_PackageTypeIs4x4( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_PackageTypeIs5x5( void ) +ChipInfo_PackageTypeIs5x5(void) { - return ( ChipInfo_GetPackageType() == PACKAGE_5x5 ); + return (ChipInfo_GetPackageType() == PACKAGE_5x5); } //***************************************************************************** @@ -222,9 +221,9 @@ ChipInfo_PackageTypeIs5x5( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_PackageTypeIs7x7( void ) +ChipInfo_PackageTypeIs7x7(void) { - return ( ChipInfo_GetPackageType() == PACKAGE_7x7 ); + return (ChipInfo_GetPackageType() == PACKAGE_7x7); } //***************************************************************************** @@ -236,9 +235,9 @@ ChipInfo_PackageTypeIs7x7( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_PackageTypeIsWAFER( void ) +ChipInfo_PackageTypeIsWAFER(void) { - return ( ChipInfo_GetPackageType() == PACKAGE_WAFER ); + return (ChipInfo_GetPackageType() == PACKAGE_WAFER); } //***************************************************************************** @@ -250,9 +249,9 @@ ChipInfo_PackageTypeIsWAFER( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_PackageTypeIsWCSP( void ) +ChipInfo_PackageTypeIsWCSP(void) { - return ( ChipInfo_GetPackageType() == PACKAGE_WCSP ); + return (ChipInfo_GetPackageType() == PACKAGE_WCSP); } //***************************************************************************** @@ -264,9 +263,9 @@ ChipInfo_PackageTypeIsWCSP( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_PackageTypeIs7x7Q1( void ) +ChipInfo_PackageTypeIs7x7Q1(void) { - return ( ChipInfo_GetPackageType() == PACKAGE_7x7_Q1 ); + return (ChipInfo_GetPackageType() == PACKAGE_7x7_Q1); } //***************************************************************************** @@ -277,10 +276,10 @@ ChipInfo_PackageTypeIs7x7Q1( void ) //! Returns the internal chip HW revision code (in range 0-15) //***************************************************************************** __STATIC_INLINE uint32_t -ChipInfo_GetDeviceIdHwRevCode( void ) +ChipInfo_GetDeviceIdHwRevCode(void) { // Returns HwRevCode = FCFG1_O_ICEPICK_DEVICE_ID[31:28] - return ( HWREG( FCFG1_BASE + FCFG1_O_ICEPICK_DEVICE_ID ) >> 28 ); + return (HWREG(FCFG1_BASE + FCFG1_O_ICEPICK_DEVICE_ID) >> 28); } //***************************************************************************** @@ -295,18 +294,18 @@ ChipInfo_GetDeviceIdHwRevCode( void ) // //***************************************************************************** __STATIC_INLINE uint32_t -ChipInfo_GetMinorHwRev( void ) +ChipInfo_GetMinorHwRev(void) { - uint32_t minorRev = (( HWREG( FCFG1_BASE + FCFG1_O_MISC_CONF_1 ) & - FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M ) >> - FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S ) ; + uint32_t minorRev = ((HWREG(FCFG1_BASE + FCFG1_O_MISC_CONF_1) & + FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M) >> + FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S); - if ( minorRev >= 0x80 ) + if (minorRev >= 0x80) { minorRev = 0; } - return ( minorRev ); + return (minorRev); } //***************************************************************************** @@ -320,9 +319,9 @@ ChipInfo_GetMinorHwRev( void ) // //***************************************************************************** __STATIC_INLINE uint32_t -ChipInfo_GetUserId( void ) +ChipInfo_GetUserId(void) { - return ( HWREG( FCFG1_BASE + FCFG1_O_USER_ID )); + return (HWREG(FCFG1_BASE + FCFG1_O_USER_ID)); } //***************************************************************************** @@ -332,22 +331,22 @@ ChipInfo_GetUserId( void ) //***************************************************************************** typedef enum { - CHIP_TYPE_Unknown = -1, //!< -1 means that the chip type is unknown. - CHIP_TYPE_CC1310 = 0, //!< 0 means that this is a CC1310 chip. - CHIP_TYPE_CC1350 = 1, //!< 1 means that this is a CC1350 chip. - CHIP_TYPE_CC2620 = 2, //!< 2 means that this is a CC2620 chip. - CHIP_TYPE_CC2630 = 3, //!< 3 means that this is a CC2630 chip. - CHIP_TYPE_CC2640 = 4, //!< 4 means that this is a CC2640 chip. - CHIP_TYPE_CC2650 = 5, //!< 5 means that this is a CC2650 chip. - CHIP_TYPE_CUSTOM_0 = 6, //!< 6 means that this is a CUSTOM_0 chip. - CHIP_TYPE_CUSTOM_1 = 7, //!< 7 means that this is a CUSTOM_1 chip. - CHIP_TYPE_CC2640R2 = 8, //!< 8 means that this is a CC2640R2 chip. - CHIP_TYPE_CC2642 = 9, //!< 9 means that this is a CC2642 chip. - CHIP_TYPE_unused = 10,//!< 10 unused value - CHIP_TYPE_CC2652 = 11,//!< 11 means that this is a CC2652 chip. - CHIP_TYPE_CC1312 = 12,//!< 12 means that this is a CC1312 chip. - CHIP_TYPE_CC1352 = 13,//!< 13 means that this is a CC1352 chip. - CHIP_TYPE_CC1352P = 14 //!< 14 means that this is a CC1352P chip. + CHIP_TYPE_Unknown = -1, //!< -1 means that the chip type is unknown. + CHIP_TYPE_CC1310 = 0, //!< 0 means that this is a CC1310 chip. + CHIP_TYPE_CC1350 = 1, //!< 1 means that this is a CC1350 chip. + CHIP_TYPE_CC2620 = 2, //!< 2 means that this is a CC2620 chip. + CHIP_TYPE_CC2630 = 3, //!< 3 means that this is a CC2630 chip. + CHIP_TYPE_CC2640 = 4, //!< 4 means that this is a CC2640 chip. + CHIP_TYPE_CC2650 = 5, //!< 5 means that this is a CC2650 chip. + CHIP_TYPE_CUSTOM_0 = 6, //!< 6 means that this is a CUSTOM_0 chip. + CHIP_TYPE_CUSTOM_1 = 7, //!< 7 means that this is a CUSTOM_1 chip. + CHIP_TYPE_CC2640R2 = 8, //!< 8 means that this is a CC2640R2 chip. + CHIP_TYPE_CC2642 = 9, //!< 9 means that this is a CC2642 chip. + CHIP_TYPE_unused = 10, //!< 10 unused value + CHIP_TYPE_CC2652 = 11, //!< 11 means that this is a CC2652 chip. + CHIP_TYPE_CC1312 = 12, //!< 12 means that this is a CC1312 chip. + CHIP_TYPE_CC1352 = 13, //!< 13 means that this is a CC1352 chip. + CHIP_TYPE_CC1352P = 14 //!< 14 means that this is a CC1352P chip. } ChipType_t; //***************************************************************************** @@ -358,7 +357,7 @@ typedef enum //! Returns \ref ChipType_t // //***************************************************************************** -extern ChipType_t ChipInfo_GetChipType( void ); +extern ChipType_t ChipInfo_GetChipType(void); //***************************************************************************** // @@ -367,12 +366,12 @@ extern ChipType_t ChipInfo_GetChipType( void ); //***************************************************************************** typedef enum { - FAMILY_Unknown = -1, //!< -1 means that the chip's family member is unknown. - FAMILY_CC26x0 = 0, //!< 0 means that the chip is a CC26x0 family member. - FAMILY_CC13x0 = 1, //!< 1 means that the chip is a CC13x0 family member. - FAMILY_CC26x1 = 2, //!< 2 means that the chip is a CC26x1 family member. - FAMILY_CC26x0R2 = 3, //!< 3 means that the chip is a CC26x0R2 family (new ROM contents). - FAMILY_CC13x2_CC26x2 = 4 //!< 4 means that the chip is a CC13x2, CC26x2 family member. + FAMILY_Unknown = -1, //!< -1 means that the chip's family member is unknown. + FAMILY_CC26x0 = 0, //!< 0 means that the chip is a CC26x0 family member. + FAMILY_CC13x0 = 1, //!< 1 means that the chip is a CC13x0 family member. + FAMILY_CC26x1 = 2, //!< 2 means that the chip is a CC26x1 family member. + FAMILY_CC26x0R2 = 3, //!< 3 means that the chip is a CC26x0R2 family (new ROM contents). + FAMILY_CC13x2_CC26x2 = 4 //!< 4 means that the chip is a CC13x2, CC26x2 family member. } ChipFamily_t; //***************************************************************************** @@ -383,17 +382,17 @@ typedef enum //! Returns \ref ChipFamily_t // //***************************************************************************** -extern ChipFamily_t ChipInfo_GetChipFamily( void ); +extern ChipFamily_t ChipInfo_GetChipFamily(void); //***************************************************************************** // // Options for the define THIS_DRIVERLIB_BUILD // //***************************************************************************** -#define DRIVERLIB_BUILD_CC26X0 0 //!< 0 is the driverlib build ID for the cc26x0 driverlib. -#define DRIVERLIB_BUILD_CC13X0 1 //!< 1 is the driverlib build ID for the cc13x0 driverlib. -#define DRIVERLIB_BUILD_CC26X1 2 //!< 2 is the driverlib build ID for the cc26x1 driverlib. -#define DRIVERLIB_BUILD_CC26X0R2 3 //!< 3 is the driverlib build ID for the cc26x0r2 driverlib. +#define DRIVERLIB_BUILD_CC26X0 0 //!< 0 is the driverlib build ID for the cc26x0 driverlib. +#define DRIVERLIB_BUILD_CC13X0 1 //!< 1 is the driverlib build ID for the cc13x0 driverlib. +#define DRIVERLIB_BUILD_CC26X1 2 //!< 2 is the driverlib build ID for the cc26x1 driverlib. +#define DRIVERLIB_BUILD_CC26X0R2 3 //!< 3 is the driverlib build ID for the cc26x0r2 driverlib. #define DRIVERLIB_BUILD_CC13X2_CC26X2 4 //!< 4 is the driverlib build ID for the cc13x2_cc26x2 driverlib. //***************************************************************************** @@ -403,7 +402,7 @@ extern ChipFamily_t ChipInfo_GetChipFamily( void ); //! This driverlib build identifier can be useful for compile time checking/optimization (supporting C preprocessor expressions). // //***************************************************************************** -#define THIS_DRIVERLIB_BUILD DRIVERLIB_BUILD_CC13X0 +#define THIS_DRIVERLIB_BUILD DRIVERLIB_BUILD_CC13X0 //***************************************************************************** // @@ -414,9 +413,9 @@ extern ChipFamily_t ChipInfo_GetChipFamily( void ); // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_ChipFamilyIs_CC13x0( void ) +ChipInfo_ChipFamilyIs_CC13x0(void) { - return ( ChipInfo_GetChipFamily() == FAMILY_CC13x0 ); + return (ChipInfo_GetChipFamily() == FAMILY_CC13x0); } //***************************************************************************** @@ -428,9 +427,9 @@ ChipInfo_ChipFamilyIs_CC13x0( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_ChipFamilyIs_CC26x0( void ) +ChipInfo_ChipFamilyIs_CC26x0(void) { - return ( ChipInfo_GetChipFamily() == FAMILY_CC26x0 ); + return (ChipInfo_GetChipFamily() == FAMILY_CC26x0); } //***************************************************************************** @@ -442,9 +441,9 @@ ChipInfo_ChipFamilyIs_CC26x0( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_ChipFamilyIs_CC26x0R2( void ) +ChipInfo_ChipFamilyIs_CC26x0R2(void) { - return ( ChipInfo_GetChipFamily() == FAMILY_CC26x0R2 ); + return (ChipInfo_GetChipFamily() == FAMILY_CC26x0R2); } //***************************************************************************** @@ -456,9 +455,9 @@ ChipInfo_ChipFamilyIs_CC26x0R2( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_ChipFamilyIs_CC26x1( void ) +ChipInfo_ChipFamilyIs_CC26x1(void) { - return ( ChipInfo_GetChipFamily() == FAMILY_CC26x1 ); + return (ChipInfo_GetChipFamily() == FAMILY_CC26x1); } //***************************************************************************** @@ -470,9 +469,9 @@ ChipInfo_ChipFamilyIs_CC26x1( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_ChipFamilyIs_CC13x2_CC26x2( void ) +ChipInfo_ChipFamilyIs_CC13x2_CC26x2(void) { - return ( ChipInfo_GetChipFamily() == FAMILY_CC13x2_CC26x2 ); + return (ChipInfo_GetChipFamily() == FAMILY_CC13x2_CC26x2); } //***************************************************************************** @@ -482,14 +481,14 @@ ChipInfo_ChipFamilyIs_CC13x2_CC26x2( void ) //***************************************************************************** typedef enum { - HWREV_Unknown = -1, //!< -1 means that the chip's HW revision is unknown. - HWREV_1_0 = 10, //!< 10 means that the chip's HW revision is 1.0 - HWREV_1_1 = 11, //!< 11 means that the chip's HW revision is 1.1 - HWREV_2_0 = 20, //!< 20 means that the chip's HW revision is 2.0 - HWREV_2_1 = 21, //!< 21 means that the chip's HW revision is 2.1 - HWREV_2_2 = 22, //!< 22 means that the chip's HW revision is 2.2 - HWREV_2_3 = 23, //!< 23 means that the chip's HW revision is 2.3 - HWREV_2_4 = 24 //!< 24 means that the chip's HW revision is 2.4 + HWREV_Unknown = -1, //!< -1 means that the chip's HW revision is unknown. + HWREV_1_0 = 10, //!< 10 means that the chip's HW revision is 1.0 + HWREV_1_1 = 11, //!< 11 means that the chip's HW revision is 1.1 + HWREV_2_0 = 20, //!< 20 means that the chip's HW revision is 2.0 + HWREV_2_1 = 21, //!< 21 means that the chip's HW revision is 2.1 + HWREV_2_2 = 22, //!< 22 means that the chip's HW revision is 2.2 + HWREV_2_3 = 23, //!< 23 means that the chip's HW revision is 2.3 + HWREV_2_4 = 24 //!< 24 means that the chip's HW revision is 2.4 } HwRevision_t; //***************************************************************************** @@ -500,7 +499,7 @@ typedef enum //! Returns \ref HwRevision_t // //***************************************************************************** -extern HwRevision_t ChipInfo_GetHwRevision( void ); +extern HwRevision_t ChipInfo_GetHwRevision(void); //***************************************************************************** // @@ -511,9 +510,9 @@ extern HwRevision_t ChipInfo_GetHwRevision( void ); // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_1_0( void ) +ChipInfo_HwRevisionIs_1_0(void) { - return ( ChipInfo_GetHwRevision() == HWREV_1_0 ); + return (ChipInfo_GetHwRevision() == HWREV_1_0); } //***************************************************************************** @@ -525,9 +524,9 @@ ChipInfo_HwRevisionIs_1_0( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_2_0( void ) +ChipInfo_HwRevisionIs_2_0(void) { - return ( ChipInfo_GetHwRevision() == HWREV_2_0 ); + return (ChipInfo_GetHwRevision() == HWREV_2_0); } //***************************************************************************** @@ -539,9 +538,9 @@ ChipInfo_HwRevisionIs_2_0( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_GTEQ_2_0( void ) +ChipInfo_HwRevisionIs_GTEQ_2_0(void) { - return ( ChipInfo_GetHwRevision() >= HWREV_2_0 ); + return (ChipInfo_GetHwRevision() >= HWREV_2_0); } //***************************************************************************** @@ -553,9 +552,9 @@ ChipInfo_HwRevisionIs_GTEQ_2_0( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_2_1( void ) +ChipInfo_HwRevisionIs_2_1(void) { - return ( ChipInfo_GetHwRevision() == HWREV_2_1 ); + return (ChipInfo_GetHwRevision() == HWREV_2_1); } //***************************************************************************** @@ -567,9 +566,9 @@ ChipInfo_HwRevisionIs_2_1( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_GTEQ_2_1( void ) +ChipInfo_HwRevisionIs_GTEQ_2_1(void) { - return ( ChipInfo_GetHwRevision() >= HWREV_2_1 ); + return (ChipInfo_GetHwRevision() >= HWREV_2_1); } //***************************************************************************** @@ -581,9 +580,9 @@ ChipInfo_HwRevisionIs_GTEQ_2_1( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_2_2( void ) +ChipInfo_HwRevisionIs_2_2(void) { - return ( ChipInfo_GetHwRevision() == HWREV_2_2 ); + return (ChipInfo_GetHwRevision() == HWREV_2_2); } //***************************************************************************** @@ -595,9 +594,9 @@ ChipInfo_HwRevisionIs_2_2( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_GTEQ_2_2( void ) +ChipInfo_HwRevisionIs_GTEQ_2_2(void) { - return ( ChipInfo_GetHwRevision() >= HWREV_2_2 ); + return (ChipInfo_GetHwRevision() >= HWREV_2_2); } //***************************************************************************** @@ -609,9 +608,9 @@ ChipInfo_HwRevisionIs_GTEQ_2_2( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_GTEQ_2_3( void ) +ChipInfo_HwRevisionIs_GTEQ_2_3(void) { - return ( ChipInfo_GetHwRevision() >= HWREV_2_3 ); + return (ChipInfo_GetHwRevision() >= HWREV_2_3); } //***************************************************************************** @@ -623,9 +622,9 @@ ChipInfo_HwRevisionIs_GTEQ_2_3( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_GTEQ_2_4( void ) +ChipInfo_HwRevisionIs_GTEQ_2_4(void) { - return ( ChipInfo_GetHwRevision() >= HWREV_2_4 ); + return (ChipInfo_GetHwRevision() >= HWREV_2_4); } //***************************************************************************** @@ -635,7 +634,7 @@ ChipInfo_HwRevisionIs_GTEQ_2_4( void ) //! \return None // //***************************************************************************** -extern void ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated( void ); +extern void ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated(void); //***************************************************************************** // @@ -646,27 +645,27 @@ extern void ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated( void ); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_ChipInfo_GetSupportedProtocol_BV -#undef ChipInfo_GetSupportedProtocol_BV +#undef ChipInfo_GetSupportedProtocol_BV #define ChipInfo_GetSupportedProtocol_BV ROM_ChipInfo_GetSupportedProtocol_BV #endif #ifdef ROM_ChipInfo_GetPackageType -#undef ChipInfo_GetPackageType -#define ChipInfo_GetPackageType ROM_ChipInfo_GetPackageType +#undef ChipInfo_GetPackageType +#define ChipInfo_GetPackageType ROM_ChipInfo_GetPackageType #endif #ifdef ROM_ChipInfo_GetChipType -#undef ChipInfo_GetChipType -#define ChipInfo_GetChipType ROM_ChipInfo_GetChipType +#undef ChipInfo_GetChipType +#define ChipInfo_GetChipType ROM_ChipInfo_GetChipType #endif #ifdef ROM_ChipInfo_GetChipFamily -#undef ChipInfo_GetChipFamily -#define ChipInfo_GetChipFamily ROM_ChipInfo_GetChipFamily +#undef ChipInfo_GetChipFamily +#define ChipInfo_GetChipFamily ROM_ChipInfo_GetChipFamily #endif #ifdef ROM_ChipInfo_GetHwRevision -#undef ChipInfo_GetHwRevision -#define ChipInfo_GetHwRevision ROM_ChipInfo_GetHwRevision +#undef ChipInfo_GetHwRevision +#define ChipInfo_GetHwRevision ROM_ChipInfo_GetHwRevision #endif #ifdef ROM_ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated -#undef ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated +#undef ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated #define ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated ROM_ThisLibraryIsFor_CC13x0_HwRev20AndLater_HaltIfViolated #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/cpu.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/cpu.h index 947687f..c039cf7 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/cpu.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/cpu.h @@ -1,41 +1,41 @@ /****************************************************************************** -* Filename: cpu.h -* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) -* Revision: 52111 -* -* Description: Defines and prototypes for the CPU instruction wrapper -* functions. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: cpu.h + * Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) + * Revision: 52111 + * + * Description: Defines and prototypes for the CPU instruction wrapper + * functions. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -56,15 +56,14 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_cpu_scs.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_cpu_scs.h" //***************************************************************************** // @@ -80,11 +79,11 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define CPUcpsid NOROM_CPUcpsid -#define CPUprimask NOROM_CPUprimask -#define CPUcpsie NOROM_CPUcpsie -#define CPUbasepriGet NOROM_CPUbasepriGet -#define CPUdelay NOROM_CPUdelay +#define CPUcpsid NOROM_CPUcpsid +#define CPUprimask NOROM_CPUprimask +#define CPUcpsie NOROM_CPUcpsie +#define CPUbasepriGet NOROM_CPUbasepriGet +#define CPUdelay NOROM_CPUdelay #endif //***************************************************************************** @@ -207,7 +206,7 @@ CPUwfi(void) { // Wait for the next interrupt. wfi; - bx lr + bx lr } #elif defined(__TI_COMPILER_VERSION__) __STATIC_INLINE void @@ -221,7 +220,7 @@ __STATIC_INLINE void __attribute__((always_inline)) CPUwfi(void) { // Wait for the next interrupt. - __asm volatile (" wfi\n"); + __asm volatile(" wfi\n"); } #endif @@ -254,7 +253,7 @@ CPUwfe(void) { // Wait for the next event. wfe; - bx lr + bx lr } #elif defined(__TI_COMPILER_VERSION__) __STATIC_INLINE void @@ -268,7 +267,7 @@ __STATIC_INLINE void __attribute__((always_inline)) CPUwfe(void) { // Wait for the next event. - __asm volatile (" wfe\n"); + __asm volatile(" wfe\n"); } #endif @@ -301,7 +300,7 @@ CPUsev(void) { // Send event. sev; - bx lr + bx lr } #elif defined(__TI_COMPILER_VERSION__) __STATIC_INLINE void @@ -315,11 +314,10 @@ __STATIC_INLINE void __attribute__((always_inline)) CPUsev(void) { // Send event. - __asm volatile (" sev\n"); + __asm volatile(" sev\n"); } #endif - //***************************************************************************** // //! \brief Update the interrupt priority disable level. @@ -350,8 +348,8 @@ __asm __STATIC_INLINE void CPUbasepriSet(uint32_t ui32NewBasepri) { // Set the BASEPRI register. - msr BASEPRI, r0; - bx lr + msr BASEPRI, r0; + bx lr } #elif defined(__TI_COMPILER_VERSION__) __STATIC_INLINE void @@ -363,15 +361,14 @@ CPUbasepriSet(uint32_t ui32NewBasepri) #else #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wattributes" -__STATIC_INLINE void __attribute__ ((naked)) +__STATIC_INLINE void __attribute__((naked)) CPUbasepriSet(uint32_t ui32NewBasepri) { // Set the BASEPRI register. - __asm volatile (" msr BASEPRI, %0\n" - " bx lr\n" - : /* No output */ - : "r" (ui32NewBasepri) - ); + __asm volatile(" msr BASEPRI, %0\n" + " bx lr\n" + : /* No output */ + : "r"(ui32NewBasepri)); } #pragma GCC diagnostic pop #endif @@ -393,9 +390,9 @@ CPUbasepriSet(uint32_t ui32NewBasepri) // //***************************************************************************** __STATIC_INLINE void -CPU_WriteBufferDisable( void ) +CPU_WriteBufferDisable(void) { - HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 1; + HWREGBITW(CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN) = 1; } //***************************************************************************** @@ -411,9 +408,9 @@ CPU_WriteBufferDisable( void ) // //***************************************************************************** __STATIC_INLINE void -CPU_WriteBufferEnable( void ) +CPU_WriteBufferEnable(void) { - HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 0; + HWREGBITW(CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN) = 0; } //***************************************************************************** @@ -425,24 +422,24 @@ CPU_WriteBufferEnable( void ) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_CPUcpsid -#undef CPUcpsid -#define CPUcpsid ROM_CPUcpsid +#undef CPUcpsid +#define CPUcpsid ROM_CPUcpsid #endif #ifdef ROM_CPUprimask -#undef CPUprimask -#define CPUprimask ROM_CPUprimask +#undef CPUprimask +#define CPUprimask ROM_CPUprimask #endif #ifdef ROM_CPUcpsie -#undef CPUcpsie -#define CPUcpsie ROM_CPUcpsie +#undef CPUcpsie +#define CPUcpsie ROM_CPUcpsie #endif #ifdef ROM_CPUbasepriGet -#undef CPUbasepriGet -#define CPUbasepriGet ROM_CPUbasepriGet +#undef CPUbasepriGet +#define CPUbasepriGet ROM_CPUbasepriGet #endif #ifdef ROM_CPUdelay -#undef CPUdelay -#define CPUdelay ROM_CPUdelay +#undef CPUdelay +#define CPUdelay ROM_CPUdelay #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/cpu_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/cpu_doc.h index 7f17aa3..4295c5e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/cpu_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/cpu_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: cpu_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: cpu_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup cpu_api //! @{ //! \section sec_cpu Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/crypto.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/crypto.h index 11760a6..4c64649 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/crypto.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/crypto.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: crypto.h -* Revised: 2018-01-12 18:46:31 +0100 (Fri, 12 Jan 2018) -* Revision: 51161 -* -* Description: AES header file. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: crypto.h + * Revised: 2018-01-12 18:46:31 +0100 (Fri, 12 Jan 2018) + * Revision: 51161 + * + * Description: AES header file. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,19 +55,18 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" #include "../inc/hw_crypto.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "cpu.h" #include "debug.h" #include "interrupt.h" -#include "cpu.h" +#include +#include //***************************************************************************** // @@ -83,19 +82,19 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define CRYPTOAesLoadKey NOROM_CRYPTOAesLoadKey -#define CRYPTOAesCbc NOROM_CRYPTOAesCbc -#define CRYPTOAesCbcStatus NOROM_CRYPTOAesCbcStatus -#define CRYPTOAesEcb NOROM_CRYPTOAesEcb -#define CRYPTOAesEcbStatus NOROM_CRYPTOAesEcbStatus -#define CRYPTOCcmAuthEncrypt NOROM_CRYPTOCcmAuthEncrypt -#define CRYPTOCcmAuthEncryptStatus NOROM_CRYPTOCcmAuthEncryptStatus -#define CRYPTOCcmAuthEncryptResultGet NOROM_CRYPTOCcmAuthEncryptResultGet -#define CRYPTOCcmInvAuthDecrypt NOROM_CRYPTOCcmInvAuthDecrypt -#define CRYPTOCcmInvAuthDecryptStatus NOROM_CRYPTOCcmInvAuthDecryptStatus +#define CRYPTOAesLoadKey NOROM_CRYPTOAesLoadKey +#define CRYPTOAesCbc NOROM_CRYPTOAesCbc +#define CRYPTOAesCbcStatus NOROM_CRYPTOAesCbcStatus +#define CRYPTOAesEcb NOROM_CRYPTOAesEcb +#define CRYPTOAesEcbStatus NOROM_CRYPTOAesEcbStatus +#define CRYPTOCcmAuthEncrypt NOROM_CRYPTOCcmAuthEncrypt +#define CRYPTOCcmAuthEncryptStatus NOROM_CRYPTOCcmAuthEncryptStatus +#define CRYPTOCcmAuthEncryptResultGet NOROM_CRYPTOCcmAuthEncryptResultGet +#define CRYPTOCcmInvAuthDecrypt NOROM_CRYPTOCcmInvAuthDecrypt +#define CRYPTOCcmInvAuthDecryptStatus NOROM_CRYPTOCcmInvAuthDecryptStatus #define CRYPTOCcmInvAuthDecryptResultGet NOROM_CRYPTOCcmInvAuthDecryptResultGet -#define CRYPTODmaEnable NOROM_CRYPTODmaEnable -#define CRYPTODmaDisable NOROM_CRYPTODmaDisable +#define CRYPTODmaEnable NOROM_CRYPTODmaEnable +#define CRYPTODmaDisable NOROM_CRYPTODmaDisable #endif //***************************************************************************** @@ -103,7 +102,7 @@ extern "C" // Length of AES Electronic Code Book (ECB) block in bytes // //***************************************************************************** -#define AES_ECB_LENGTH 16 +#define AES_ECB_LENGTH 16 //***************************************************************************** // @@ -111,24 +110,24 @@ extern "C" // as the ui32IntFlags parameter, and returned from CryptoIntStatus. // //***************************************************************************** -#define CRYPTO_DMA_IN_DONE 0x00000002 // DMA done interrupt mask -#define CRYPTO_RESULT_RDY 0x00000001 // Result ready interrupt mask -#define CRYPTO_DMA_BUS_ERR 0x80000000 // DMA Bus error -#define CRYPTO_KEY_ST_WR_ERR 0x40000000 // Key Store Write failed -#define CRYPTO_KEY_ST_RD_ERR 0x20000000 // Key Store Read failed +#define CRYPTO_DMA_IN_DONE 0x00000002 // DMA done interrupt mask +#define CRYPTO_RESULT_RDY 0x00000001 // Result ready interrupt mask +#define CRYPTO_DMA_BUS_ERR 0x80000000 // DMA Bus error +#define CRYPTO_KEY_ST_WR_ERR 0x40000000 // Key Store Write failed +#define CRYPTO_KEY_ST_RD_ERR 0x20000000 // Key Store Read failed -#define CRYPTO_IRQTYPE_LEVEL 0x00000001 // Crypto Level interrupt enabled -#define CRYPTO_IRQTYPE_PULSE 0x00000000 // Crypto pulse interrupt enabled +#define CRYPTO_IRQTYPE_LEVEL 0x00000001 // Crypto Level interrupt enabled +#define CRYPTO_IRQTYPE_PULSE 0x00000000 // Crypto pulse interrupt enabled -#define CRYPTO_DMA_CHAN0 0x00000001 // Crypto DMA Channel 0 -#define CRYPTO_DMA_CHAN1 0x00000002 // Crypto DMA Channel 1 +#define CRYPTO_DMA_CHAN0 0x00000001 // Crypto DMA Channel 0 +#define CRYPTO_DMA_CHAN1 0x00000002 // Crypto DMA Channel 1 -#define CRYPTO_AES128_ENCRYPT 0x0000000C // -#define CRYPTO_AES128_DECRYPT 0x00000008 // +#define CRYPTO_AES128_ENCRYPT 0x0000000C // +#define CRYPTO_AES128_DECRYPT 0x00000008 // -#define CRYPTO_DMA_READY 0x00000000 // DMA ready -#define CRYPTO_DMA_BSY 0x00000003 // DMA busy -#define CRYPTO_DMA_BUS_ERROR 0x00020000 // DMA encountered bus error +#define CRYPTO_DMA_READY 0x00000000 // DMA ready +#define CRYPTO_DMA_BSY 0x00000003 // DMA busy +#define CRYPTO_DMA_BUS_ERROR 0x00020000 // DMA encountered bus error //***************************************************************************** // @@ -137,25 +136,25 @@ extern "C" //***************************************************************************** // AES module return codes -#define AES_SUCCESS 0 -#define AES_KEYSTORE_READ_ERROR 1 -#define AES_KEYSTORE_WRITE_ERROR 2 -#define AES_DMA_BUS_ERROR 3 -#define CCM_AUTHENTICATION_FAILED 4 -#define AES_ECB_TEST_ERROR 8 -#define AES_NULL_ERROR 9 -#define AES_CCM_TEST_ERROR 10 -#define AES_DMA_BSY 11 +#define AES_SUCCESS 0 +#define AES_KEYSTORE_READ_ERROR 1 +#define AES_KEYSTORE_WRITE_ERROR 2 +#define AES_DMA_BUS_ERROR 3 +#define CCM_AUTHENTICATION_FAILED 4 +#define AES_ECB_TEST_ERROR 8 +#define AES_NULL_ERROR 9 +#define AES_CCM_TEST_ERROR 10 +#define AES_DMA_BSY 11 // Key store module defines -#define STATE_BLENGTH 16 // Number of bytes in State -#define KEY_BLENGTH 16 // Number of bytes in Key -#define KEY_EXP_LENGTH 176 // Nb * (Nr+1) * 4 +#define STATE_BLENGTH 16 // Number of bytes in State +#define KEY_BLENGTH 16 // Number of bytes in Key +#define KEY_EXP_LENGTH 176 // Nb * (Nr+1) * 4 -#define KEY_STORE_SIZE_128 0x00000001 -#define KEY_STORE_SIZE_192 0x00000002 -#define KEY_STORE_SIZE_256 0x00000003 -#define KEY_STORE_SIZE_BITS 0x00000003 +#define KEY_STORE_SIZE_128 0x00000001 +#define KEY_STORE_SIZE_192 0x00000002 +#define KEY_STORE_SIZE_256 0x00000003 +#define KEY_STORE_SIZE_BITS 0x00000003 //***************************************************************************** // @@ -164,36 +163,36 @@ extern "C" // are valid. // //***************************************************************************** -#define CRYPTO_KEY_AREA_0 0 -#define CRYPTO_KEY_AREA_1 1 -#define CRYPTO_KEY_AREA_2 2 -#define CRYPTO_KEY_AREA_3 3 -#define CRYPTO_KEY_AREA_4 4 -#define CRYPTO_KEY_AREA_5 5 -#define CRYPTO_KEY_AREA_6 6 -#define CRYPTO_KEY_AREA_7 7 +#define CRYPTO_KEY_AREA_0 0 +#define CRYPTO_KEY_AREA_1 1 +#define CRYPTO_KEY_AREA_2 2 +#define CRYPTO_KEY_AREA_3 3 +#define CRYPTO_KEY_AREA_4 4 +#define CRYPTO_KEY_AREA_5 5 +#define CRYPTO_KEY_AREA_6 6 +#define CRYPTO_KEY_AREA_7 7 //***************************************************************************** // // Defines for the current AES operation // //***************************************************************************** -#define CRYPTO_AES_NONE 0 -#define CRYPTO_AES_KEYL0AD 1 -#define CRYPTO_AES_ECB 2 -#define CRYPTO_AES_CCM 3 -#define CRYPTO_AES_RNG 4 -#define CRYPTO_AES_CBC 5 +#define CRYPTO_AES_NONE 0 +#define CRYPTO_AES_KEYL0AD 1 +#define CRYPTO_AES_ECB 2 +#define CRYPTO_AES_CCM 3 +#define CRYPTO_AES_RNG 4 +#define CRYPTO_AES_CBC 5 //***************************************************************************** // // Defines for the AES-CTR mode counter width // //***************************************************************************** -#define CRYPTO_AES_CTR_32 0x0 -#define CRYPTO_AES_CTR_64 0x1 -#define CRYPTO_AES_CTR_96 0x2 -#define CRYPTO_AES_CTR_128 0x3 +#define CRYPTO_AES_CTR_32 0x0 +#define CRYPTO_AES_CTR_64 0x1 +#define CRYPTO_AES_CTR_96 0x2 +#define CRYPTO_AES_CTR_128 0x3 //***************************************************************************** // @@ -457,7 +456,7 @@ extern uint32_t CRYPTOCcmAuthEncryptStatus(void); // //***************************************************************************** extern uint32_t CRYPTOCcmAuthEncryptResultGet(uint32_t ui32TagLength, - uint32_t* pui32CcmTag); + uint32_t* pui32CcmTag); //***************************************************************************** // @@ -530,9 +529,9 @@ extern uint32_t CRYPTOCcmInvAuthDecryptStatus(void); // //***************************************************************************** extern uint32_t CRYPTOCcmInvAuthDecryptResultGet(uint32_t ui32AuthLength, - uint32_t* pui32CipherText, - uint32_t ui32CipherTextLength, - uint32_t* pui32CcmTag); + uint32_t* pui32CipherText, + uint32_t ui32CipherTextLength, + uint32_t* pui32CcmTag); //***************************************************************************** // @@ -783,56 +782,56 @@ CRYPTOIntUnregister(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_CRYPTOAesLoadKey -#undef CRYPTOAesLoadKey -#define CRYPTOAesLoadKey ROM_CRYPTOAesLoadKey +#undef CRYPTOAesLoadKey +#define CRYPTOAesLoadKey ROM_CRYPTOAesLoadKey #endif #ifdef ROM_CRYPTOAesCbc -#undef CRYPTOAesCbc -#define CRYPTOAesCbc ROM_CRYPTOAesCbc +#undef CRYPTOAesCbc +#define CRYPTOAesCbc ROM_CRYPTOAesCbc #endif #ifdef ROM_CRYPTOAesCbcStatus -#undef CRYPTOAesCbcStatus -#define CRYPTOAesCbcStatus ROM_CRYPTOAesCbcStatus +#undef CRYPTOAesCbcStatus +#define CRYPTOAesCbcStatus ROM_CRYPTOAesCbcStatus #endif #ifdef ROM_CRYPTOAesEcb -#undef CRYPTOAesEcb -#define CRYPTOAesEcb ROM_CRYPTOAesEcb +#undef CRYPTOAesEcb +#define CRYPTOAesEcb ROM_CRYPTOAesEcb #endif #ifdef ROM_CRYPTOAesEcbStatus -#undef CRYPTOAesEcbStatus -#define CRYPTOAesEcbStatus ROM_CRYPTOAesEcbStatus +#undef CRYPTOAesEcbStatus +#define CRYPTOAesEcbStatus ROM_CRYPTOAesEcbStatus #endif #ifdef ROM_CRYPTOCcmAuthEncrypt -#undef CRYPTOCcmAuthEncrypt -#define CRYPTOCcmAuthEncrypt ROM_CRYPTOCcmAuthEncrypt +#undef CRYPTOCcmAuthEncrypt +#define CRYPTOCcmAuthEncrypt ROM_CRYPTOCcmAuthEncrypt #endif #ifdef ROM_CRYPTOCcmAuthEncryptStatus -#undef CRYPTOCcmAuthEncryptStatus -#define CRYPTOCcmAuthEncryptStatus ROM_CRYPTOCcmAuthEncryptStatus +#undef CRYPTOCcmAuthEncryptStatus +#define CRYPTOCcmAuthEncryptStatus ROM_CRYPTOCcmAuthEncryptStatus #endif #ifdef ROM_CRYPTOCcmAuthEncryptResultGet -#undef CRYPTOCcmAuthEncryptResultGet -#define CRYPTOCcmAuthEncryptResultGet ROM_CRYPTOCcmAuthEncryptResultGet +#undef CRYPTOCcmAuthEncryptResultGet +#define CRYPTOCcmAuthEncryptResultGet ROM_CRYPTOCcmAuthEncryptResultGet #endif #ifdef ROM_CRYPTOCcmInvAuthDecrypt -#undef CRYPTOCcmInvAuthDecrypt -#define CRYPTOCcmInvAuthDecrypt ROM_CRYPTOCcmInvAuthDecrypt +#undef CRYPTOCcmInvAuthDecrypt +#define CRYPTOCcmInvAuthDecrypt ROM_CRYPTOCcmInvAuthDecrypt #endif #ifdef ROM_CRYPTOCcmInvAuthDecryptStatus -#undef CRYPTOCcmInvAuthDecryptStatus -#define CRYPTOCcmInvAuthDecryptStatus ROM_CRYPTOCcmInvAuthDecryptStatus +#undef CRYPTOCcmInvAuthDecryptStatus +#define CRYPTOCcmInvAuthDecryptStatus ROM_CRYPTOCcmInvAuthDecryptStatus #endif #ifdef ROM_CRYPTOCcmInvAuthDecryptResultGet -#undef CRYPTOCcmInvAuthDecryptResultGet +#undef CRYPTOCcmInvAuthDecryptResultGet #define CRYPTOCcmInvAuthDecryptResultGet ROM_CRYPTOCcmInvAuthDecryptResultGet #endif #ifdef ROM_CRYPTODmaEnable -#undef CRYPTODmaEnable -#define CRYPTODmaEnable ROM_CRYPTODmaEnable +#undef CRYPTODmaEnable +#define CRYPTODmaEnable ROM_CRYPTODmaEnable #endif #ifdef ROM_CRYPTODmaDisable -#undef CRYPTODmaDisable -#define CRYPTODmaDisable ROM_CRYPTODmaDisable +#undef CRYPTODmaDisable +#define CRYPTODmaDisable ROM_CRYPTODmaDisable #endif #endif @@ -845,7 +844,7 @@ CRYPTOIntUnregister(void) } #endif -#endif // __CRYPTO_H__ +#endif // __CRYPTO_H__ //***************************************************************************** // diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ddi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ddi.h index e0a3036..d748e1d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ddi.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ddi.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: ddi.h -* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) -* Revision: 52111 -* -* Description: Defines and prototypes for the DDI master interface. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: ddi.h + * Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) + * Revision: 52111 + * + * Description: Defines and prototypes for the DDI master interface. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,18 +55,17 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aux_smph.h" +#include "../inc/hw_ddi.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "cpu.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ddi.h" -#include "../inc/hw_aux_smph.h" -#include "debug.h" -#include "cpu.h" //***************************************************************************** // @@ -82,11 +81,11 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define DDI32RegWrite NOROM_DDI32RegWrite -#define DDI16BitWrite NOROM_DDI16BitWrite -#define DDI16BitfieldWrite NOROM_DDI16BitfieldWrite -#define DDI16BitRead NOROM_DDI16BitRead -#define DDI16BitfieldRead NOROM_DDI16BitfieldRead +#define DDI32RegWrite NOROM_DDI32RegWrite +#define DDI16BitWrite NOROM_DDI16BitWrite +#define DDI16BitfieldWrite NOROM_DDI16BitfieldWrite +#define DDI16BitRead NOROM_DDI16BitRead +#define DDI16BitfieldRead NOROM_DDI16BitfieldRead #endif //***************************************************************************** @@ -94,17 +93,16 @@ extern "C" // Number of register in the DDI slave // //***************************************************************************** -#define DDI_SLAVE_REGS 64 - +#define DDI_SLAVE_REGS 64 //***************************************************************************** // // Defines that is used to control the ADI slave and master // //***************************************************************************** -#define DDI_PROTECT 0x00000080 -#define DDI_ACK 0x00000001 -#define DDI_SYNC 0x00000000 +#define DDI_PROTECT 0x00000080 +#define DDI_ACK 0x00000001 +#define DDI_SYNC 0x00000000 //***************************************************************************** // @@ -112,7 +110,6 @@ extern "C" // //***************************************************************************** - //***************************************************************************** // // Helper functions @@ -140,7 +137,8 @@ AuxAdiDdiSafeWrite(uint32_t nAddr, uint32_t nData, uint32_t nSize) bool bIrqEnabled = !CPUcpsid(); // Acquire semaphore for accessing ADI/DDI in AUX, perform access, release semaphore - while (!HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0)); + while (!HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0)) + ; switch (nSize) { @@ -154,7 +152,7 @@ AuxAdiDdiSafeWrite(uint32_t nAddr, uint32_t nData, uint32_t nSize) case 4: default: - HWREG(nAddr) = nData; + HWREG(nAddr) = nData; break; } @@ -188,7 +186,8 @@ AuxAdiDdiSafeRead(uint32_t nAddr, uint32_t nSize) bool bIrqEnabled = !CPUcpsid(); // Acquire semaphore for accessing ADI/DDI in AUX, perform access, release semaphore - while (!HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0)); + while (!HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0)) + ; switch (nSize) { @@ -241,7 +240,6 @@ DDIBaseValid(uint32_t ui32Base) } #endif - //***************************************************************************** // //! \brief Read the value in a 32 bit register. @@ -480,7 +478,6 @@ extern void DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) extern void DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32WrData); - //***************************************************************************** // //! \brief Write a bit field via the DDI using 16-bit maskable write. @@ -549,24 +546,24 @@ extern uint16_t DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg, #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_DDI32RegWrite -#undef DDI32RegWrite -#define DDI32RegWrite ROM_DDI32RegWrite +#undef DDI32RegWrite +#define DDI32RegWrite ROM_DDI32RegWrite #endif #ifdef ROM_DDI16BitWrite -#undef DDI16BitWrite -#define DDI16BitWrite ROM_DDI16BitWrite +#undef DDI16BitWrite +#define DDI16BitWrite ROM_DDI16BitWrite #endif #ifdef ROM_DDI16BitfieldWrite -#undef DDI16BitfieldWrite -#define DDI16BitfieldWrite ROM_DDI16BitfieldWrite +#undef DDI16BitfieldWrite +#define DDI16BitfieldWrite ROM_DDI16BitfieldWrite #endif #ifdef ROM_DDI16BitRead -#undef DDI16BitRead -#define DDI16BitRead ROM_DDI16BitRead +#undef DDI16BitRead +#define DDI16BitRead ROM_DDI16BitRead #endif #ifdef ROM_DDI16BitfieldRead -#undef DDI16BitfieldRead -#define DDI16BitfieldRead ROM_DDI16BitfieldRead +#undef DDI16BitfieldRead +#define DDI16BitfieldRead ROM_DDI16BitfieldRead #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ddi_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ddi_doc.h index 1c96d73..45760d6 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ddi_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ddi_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: ddi_doc.h -* Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016) -* Revision: 47080 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: ddi_doc.h + * Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016) + * Revision: 47080 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup ddi_api //! @{ //! \section sec_ddi Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/debug.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/debug.h index cbd4527..0f5bbcb 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/debug.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/debug.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: debug.h -* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) -* Revision: 48852 -* -* Description: Macros for assisting debug of the driver library. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: debug.h + * Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) + * Revision: 48852 + * + * Description: Macros for assisting debug of the driver library. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -62,8 +62,9 @@ extern void __error__(char* pcFilename, uint32_t ui32Line); // //***************************************************************************** #ifdef DRIVERLIB_DEBUG -#define ASSERT(expr) { \ - if(!(expr)) \ +#define ASSERT(expr) \ + { \ + if (!(expr)) \ { \ __error__(__FILE__, __LINE__); \ } \ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/driverlib_release.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/driverlib_release.h index b7a0434..2518c30 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/driverlib_release.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/driverlib_release.h @@ -1,41 +1,41 @@ /****************************************************************************** -* Filename: driverlib_release.h -* Revised: $Date: 2015-07-16 12:12:04 +0200 (Thu, 16 Jul 2015) $ -* Revision: $Revision: 44151 $ -* -* Description: Provides macros for ensuring that a specfic release of -* DriverLib is used. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: driverlib_release.h + * Revised: $Date: 2015-07-16 12:12:04 +0200 (Thu, 16 Jul 2015) $ + * Revision: $Revision: 44151 $ + * + * Description: Provides macros for ensuring that a specfic release of + * DriverLib is used. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -49,24 +49,16 @@ #ifndef __DRIVERLIB_RELEASE_H__ #define __DRIVERLIB_RELEASE_H__ - #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include - - - /// DriverLib release group number -#define DRIVERLIB_RELEASE_GROUP 0 +#define DRIVERLIB_RELEASE_GROUP 0 /// DriverLib release build number -#define DRIVERLIB_RELEASE_BUILD 54539 - - - +#define DRIVERLIB_RELEASE_BUILD 54539 //***************************************************************************** // @@ -85,9 +77,6 @@ extern "C" /// External declaration of the DriverLib release locking object extern DRIVERLIB_DECLARE_RELEASE(0, 54539); - - - //***************************************************************************** // //! This macro shall be called once from within a function of a precompiled @@ -112,9 +101,6 @@ extern DRIVERLIB_DECLARE_RELEASE(0, 54539); #define DRIVERLIB_ASSERT_RELEASE(group, build) \ (driverlib_release_##group##_##build) - - - //***************************************************************************** // //! This macro shall be called once from within a function of a precompiled @@ -137,16 +123,12 @@ extern DRIVERLIB_DECLARE_RELEASE(0, 54539); #define DRIVERLIB_ASSERT_CURR_RELEASE() \ DRIVERLIB_ASSERT_RELEASE(0, 54539) - - - #ifdef __cplusplus } #endif #endif // __DRIVERLIB_RELEASE_H__ - //***************************************************************************** // //! Close the Doxygen group. diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/event.h index f8f0c21..2df0cfa 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/event.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/event.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: event.h -* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) -* Revision: 47179 -* -* Description: Defines and prototypes for the Event Handler. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: event.h + * Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) + * Revision: 47179 + * + * Description: Defines and prototypes for the Event Handler. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,17 +55,15 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_event.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_event.h" -#include "debug.h" - //***************************************************************************** // @@ -142,28 +140,28 @@ __STATIC_INLINE void EventRegister(uint32_t ui32EventSubscriber, uint32_t ui32EventSource) { // Check the arguments. - ASSERT(( ui32EventSubscriber == EVENT_O_CPUIRQSEL30 ) || - ( ui32EventSubscriber == EVENT_O_RFCSEL9 ) || - ( ui32EventSubscriber == EVENT_O_GPT0ACAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT0BCAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT1ACAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT1BCAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT2ACAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT2BCAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT3ACAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT3BCAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH9SSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH9BSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH10SSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH10BSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH11SSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH11BSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH12SSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH12BSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH14BSEL ) || - ( ui32EventSubscriber == EVENT_O_AUXSEL0 ) || - ( ui32EventSubscriber == EVENT_O_I2SSTMPSEL0 ) || - ( ui32EventSubscriber == EVENT_O_FRZSEL0 ) ); + ASSERT((ui32EventSubscriber == EVENT_O_CPUIRQSEL30) || + (ui32EventSubscriber == EVENT_O_RFCSEL9) || + (ui32EventSubscriber == EVENT_O_GPT0ACAPTSEL) || + (ui32EventSubscriber == EVENT_O_GPT0BCAPTSEL) || + (ui32EventSubscriber == EVENT_O_GPT1ACAPTSEL) || + (ui32EventSubscriber == EVENT_O_GPT1BCAPTSEL) || + (ui32EventSubscriber == EVENT_O_GPT2ACAPTSEL) || + (ui32EventSubscriber == EVENT_O_GPT2BCAPTSEL) || + (ui32EventSubscriber == EVENT_O_GPT3ACAPTSEL) || + (ui32EventSubscriber == EVENT_O_GPT3BCAPTSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH9SSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH9BSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH10SSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH10BSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH11SSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH11BSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH12SSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH12BSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH14BSEL) || + (ui32EventSubscriber == EVENT_O_AUXSEL0) || + (ui32EventSubscriber == EVENT_O_I2SSTMPSEL0) || + (ui32EventSubscriber == EVENT_O_FRZSEL0)); // Map the event source to the event subscriber HWREG(EVENT_BASE + ui32EventSubscriber) = ui32EventSource; @@ -193,7 +191,7 @@ __STATIC_INLINE void EventSwEventSet(uint32_t ui32SwEvent) { // Check the arguments. - ASSERT( ui32SwEvent <= 3 ); + ASSERT(ui32SwEvent <= 3); // Each software event is byte accessible HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent) = 1; @@ -216,7 +214,7 @@ __STATIC_INLINE void EventSwEventClear(uint32_t ui32SwEvent) { // Check the arguments. - ASSERT( ui32SwEvent <= 3 ); + ASSERT(ui32SwEvent <= 3); // Each software event is byte accessible HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent) = 0; @@ -241,10 +239,10 @@ __STATIC_INLINE uint32_t EventSwEventGet(uint32_t ui32SwEvent) { // Check the arguments. - ASSERT( ui32SwEvent <= 3 ); + ASSERT(ui32SwEvent <= 3); // Each software event is byte accessible - return ( HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent)); + return (HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent)); } //***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/event_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/event_doc.h index a17b238..a410558 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/event_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/event_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: event_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: event_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup event_api //! @{ //! \section sec_event Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/flash.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/flash.h index d9c3aad..54f8358 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/flash.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/flash.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: flash.h -* Revised: 2017-11-02 16:09:32 +0100 (Thu, 02 Nov 2017) -* Revision: 50166 -* -* Description: Defines and prototypes for the Flash driver. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: flash.h + * Revised: 2017-11-02 16:09:32 +0100 (Thu, 02 Nov 2017) + * Revision: 50166 + * + * Description: Defines and prototypes for the Flash driver. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,20 +55,19 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_flash.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" #include "../inc/hw_aon_sysctl.h" #include "../inc/hw_fcfg1.h" -#include "interrupt.h" +#include "../inc/hw_flash.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "debug.h" +#include "interrupt.h" +#include +#include //***************************************************************************** // @@ -84,15 +83,15 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define FlashPowerModeSet NOROM_FlashPowerModeSet -#define FlashPowerModeGet NOROM_FlashPowerModeGet -#define FlashProtectionSet NOROM_FlashProtectionSet -#define FlashProtectionGet NOROM_FlashProtectionGet -#define FlashProtectionSave NOROM_FlashProtectionSave -#define FlashSectorErase NOROM_FlashSectorErase -#define FlashProgram NOROM_FlashProgram -#define FlashEfuseReadRow NOROM_FlashEfuseReadRow -#define FlashDisableSectorsForWrite NOROM_FlashDisableSectorsForWrite +#define FlashPowerModeSet NOROM_FlashPowerModeSet +#define FlashPowerModeGet NOROM_FlashPowerModeGet +#define FlashProtectionSet NOROM_FlashProtectionSet +#define FlashProtectionGet NOROM_FlashProtectionGet +#define FlashProtectionSave NOROM_FlashProtectionSave +#define FlashSectorErase NOROM_FlashSectorErase +#define FlashProgram NOROM_FlashProgram +#define FlashEfuseReadRow NOROM_FlashEfuseReadRow +#define FlashDisableSectorsForWrite NOROM_FlashDisableSectorsForWrite #endif //***************************************************************************** @@ -100,12 +99,12 @@ extern "C" // Values that can be returned from the API functions // //***************************************************************************** -#define FAPI_STATUS_SUCCESS 0x00000000 // Function completed successfully -#define FAPI_STATUS_FSM_BUSY 0x00000001 // FSM is Busy -#define FAPI_STATUS_FSM_READY 0x00000002 // FSM is Ready +#define FAPI_STATUS_SUCCESS 0x00000000 // Function completed successfully +#define FAPI_STATUS_FSM_BUSY 0x00000001 // FSM is Busy +#define FAPI_STATUS_FSM_READY 0x00000002 // FSM is Ready #define FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH \ - 0x00000003 // Incorrect parameter value -#define FAPI_STATUS_FSM_ERROR 0x00000004 // Operation failed + 0x00000003 // Incorrect parameter value +#define FAPI_STATUS_FSM_ERROR 0x00000004 // Operation failed //***************************************************************************** // @@ -113,16 +112,16 @@ extern "C" // returned from FlashIntStatus(). // //***************************************************************************** -#define FLASH_INT_FSM_DONE 0x00400000 // FSM Done Interrupt Mask -#define FLASH_INT_RV 0x00010000 // Read Verify error Interrupt Mask +#define FLASH_INT_FSM_DONE 0x00400000 // FSM Done Interrupt Mask +#define FLASH_INT_RV 0x00010000 // Read Verify error Interrupt Mask //***************************************************************************** // // Values passed to FlashSetPowerMode() and returned from FlashGetPowerMode(). // //***************************************************************************** -#define FLASH_PWR_ACTIVE_MODE 0x00000000 -#define FLASH_PWR_OFF_MODE 0x00000001 +#define FLASH_PWR_ACTIVE_MODE 0x00000000 +#define FLASH_PWR_OFF_MODE 0x00000001 #define FLASH_PWR_DEEP_STDBY_MODE \ 0x00000002 @@ -131,8 +130,8 @@ extern "C" // Values passed to FlashSetProtection() and returned from FlashGetProtection(). // //***************************************************************************** -#define FLASH_NO_PROTECT 0x00000000 // Sector not protected -#define FLASH_WRITE_PROTECT 0x00000001 // Sector erase and program +#define FLASH_NO_PROTECT 0x00000000 // Sector not protected +#define FLASH_WRITE_PROTECT 0x00000001 // Sector erase and program // protected //***************************************************************************** @@ -140,21 +139,21 @@ extern "C" // Define used by the flash programming and erase functions // //***************************************************************************** -#define ADDR_OFFSET (0x1F800000 - FLASHMEM_BASE) +#define ADDR_OFFSET (0x1F800000 - FLASHMEM_BASE) //***************************************************************************** // // Define used for access to factory configuration area. // //***************************************************************************** -#define FCFG1_OFFSET 0x1000 +#define FCFG1_OFFSET 0x1000 //***************************************************************************** // // Define for the clock frequency input to the flash module in number of MHz // //***************************************************************************** -#define FLASH_MODULE_CLK_FREQ 48 +#define FLASH_MODULE_CLK_FREQ 48 //***************************************************************************** // @@ -163,16 +162,16 @@ extern "C" //***************************************************************************** typedef enum { - FAPI_PROGRAM_DATA = 0x0002, //!< Program data. - FAPI_ERASE_SECTOR = 0x0006, //!< Erase sector. - FAPI_ERASE_BANK = 0x0008, //!< Erase bank. + FAPI_PROGRAM_DATA = 0x0002, //!< Program data. + FAPI_ERASE_SECTOR = 0x0006, //!< Erase sector. + FAPI_ERASE_BANK = 0x0008, //!< Erase bank. FAPI_VALIDATE_SECTOR = 0x000E, //!< Validate sector. - FAPI_CLEAR_STATUS = 0x0010, //!< Clear status. - FAPI_PROGRAM_RESUME = 0x0014, //!< Program resume. - FAPI_ERASE_RESUME = 0x0016, //!< Erase resume. - FAPI_CLEAR_MORE = 0x0018, //!< Clear more. - FAPI_PROGRAM_SECTOR = 0x0020, //!< Program sector. - FAPI_ERASE_OTP = 0x0030 //!< Erase OTP. + FAPI_CLEAR_STATUS = 0x0010, //!< Clear status. + FAPI_PROGRAM_RESUME = 0x0014, //!< Program resume. + FAPI_ERASE_RESUME = 0x0016, //!< Erase resume. + FAPI_CLEAR_MORE = 0x0018, //!< Clear more. + FAPI_PROGRAM_SECTOR = 0x0020, //!< Program sector. + FAPI_ERASE_OTP = 0x0030 //!< Erase OTP. } tFlashStateCommandsType; //***************************************************************************** @@ -180,39 +179,39 @@ typedef enum // Defines for values written to the FLASH_O_FSM_WR_ENA register // //***************************************************************************** -#define FSM_REG_WRT_ENABLE 5 -#define FSM_REG_WRT_DISABLE 2 +#define FSM_REG_WRT_ENABLE 5 +#define FSM_REG_WRT_DISABLE 2 //***************************************************************************** // // Defines for the bank power mode field the FLASH_O_FBFALLBACK register // //***************************************************************************** -#define FBFALLBACK_SLEEP 0 -#define FBFALLBACK_DEEP_STDBY 1 -#define FBFALLBACK_ACTIVE 3 +#define FBFALLBACK_SLEEP 0 +#define FBFALLBACK_DEEP_STDBY 1 +#define FBFALLBACK_ACTIVE 3 //***************************************************************************** // // Defines for the bank grace period and pump grace period // //***************************************************************************** -#define FLASH_BAGP 0x14 -#define FLASH_PAGP 0x14 +#define FLASH_BAGP 0x14 +#define FLASH_PAGP 0x14 //***************************************************************************** // // Defines used by the FlashProgramPattern() function // //***************************************************************************** -#define PATTERN_BITS 0x20 // No of bits in data pattern to program +#define PATTERN_BITS 0x20 // No of bits in data pattern to program //***************************************************************************** // // Defines for the FW flag bits in the FLASH_O_FWFLAG register // //***************************************************************************** -#define FW_WRT_TRIMMED 0x00000001 +#define FW_WRT_TRIMMED 0x00000001 //***************************************************************************** // @@ -220,21 +219,21 @@ typedef enum // //***************************************************************************** typedef volatile uint8_t tFwpWriteByte; -#define FWPWRITE_BYTE_ADDRESS ((tFwpWriteByte *)((FLASH_BASE + FLASH_O_FWPWRITE0))) +#define FWPWRITE_BYTE_ADDRESS ((tFwpWriteByte*)((FLASH_BASE + FLASH_O_FWPWRITE0))) //***************************************************************************** // // Define for efuse instruction // //***************************************************************************** -#define DUMPWORD_INSTR 0x04 +#define DUMPWORD_INSTR 0x04 //***************************************************************************** // // Define for FSM command execution // //***************************************************************************** -#define FLASH_CMD_EXEC 0x15 +#define FLASH_CMD_EXEC 0x15 //***************************************************************************** // @@ -671,7 +670,6 @@ FlashIntClear(uint32_t ui32IntFlags) //***************************************************************************** extern uint32_t FlashSectorErase(uint32_t ui32SectorAddress); - //***************************************************************************** // //! \brief Programs unprotected flash sectors in the main bank. @@ -750,7 +748,6 @@ extern bool FlashEfuseReadRow(uint32_t* pui32EfuseData, //***************************************************************************** extern void FlashDisableSectorsForWrite(void); - //***************************************************************************** // // Support for DriverLib in ROM: @@ -760,40 +757,40 @@ extern void FlashDisableSectorsForWrite(void); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_FlashPowerModeSet -#undef FlashPowerModeSet -#define FlashPowerModeSet ROM_FlashPowerModeSet +#undef FlashPowerModeSet +#define FlashPowerModeSet ROM_FlashPowerModeSet #endif #ifdef ROM_FlashPowerModeGet -#undef FlashPowerModeGet -#define FlashPowerModeGet ROM_FlashPowerModeGet +#undef FlashPowerModeGet +#define FlashPowerModeGet ROM_FlashPowerModeGet #endif #ifdef ROM_FlashProtectionSet -#undef FlashProtectionSet -#define FlashProtectionSet ROM_FlashProtectionSet +#undef FlashProtectionSet +#define FlashProtectionSet ROM_FlashProtectionSet #endif #ifdef ROM_FlashProtectionGet -#undef FlashProtectionGet -#define FlashProtectionGet ROM_FlashProtectionGet +#undef FlashProtectionGet +#define FlashProtectionGet ROM_FlashProtectionGet #endif #ifdef ROM_FlashProtectionSave -#undef FlashProtectionSave -#define FlashProtectionSave ROM_FlashProtectionSave +#undef FlashProtectionSave +#define FlashProtectionSave ROM_FlashProtectionSave #endif #ifdef ROM_FlashSectorErase -#undef FlashSectorErase -#define FlashSectorErase ROM_FlashSectorErase +#undef FlashSectorErase +#define FlashSectorErase ROM_FlashSectorErase #endif #ifdef ROM_FlashProgram -#undef FlashProgram -#define FlashProgram ROM_FlashProgram +#undef FlashProgram +#define FlashProgram ROM_FlashProgram #endif #ifdef ROM_FlashEfuseReadRow -#undef FlashEfuseReadRow -#define FlashEfuseReadRow ROM_FlashEfuseReadRow +#undef FlashEfuseReadRow +#define FlashEfuseReadRow ROM_FlashEfuseReadRow #endif #ifdef ROM_FlashDisableSectorsForWrite -#undef FlashDisableSectorsForWrite -#define FlashDisableSectorsForWrite ROM_FlashDisableSectorsForWrite +#undef FlashDisableSectorsForWrite +#define FlashDisableSectorsForWrite ROM_FlashDisableSectorsForWrite #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/gpio.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/gpio.h index ffc16ef..f36f851 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/gpio.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/gpio.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: gpio.h -* Revised: 2018-05-02 11:11:40 +0200 (Wed, 02 May 2018) -* Revision: 51951 -* -* Description: Defines and prototypes for the GPIO. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: gpio.h + * Revised: 2018-05-02 11:11:40 +0200 (Wed, 02 May 2018) + * Revision: 51951 + * + * Description: Defines and prototypes for the GPIO. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,15 +55,14 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" #include "../inc/hw_gpio.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "debug.h" +#include //***************************************************************************** // @@ -75,29 +74,28 @@ extern "C" #include "chipinfo.h" static bool -dioNumberLegal( uint32_t dioNumber ) +dioNumberLegal(uint32_t dioNumber) { uint32_t ioCount = - (( HWREG( FCFG1_BASE + FCFG1_O_IOCONF ) & - FCFG1_IOCONF_GPIO_CNT_M ) >> - FCFG1_IOCONF_GPIO_CNT_S ) ; + ((HWREG(FCFG1_BASE + FCFG1_O_IOCONF) & + FCFG1_IOCONF_GPIO_CNT_M) >> + FCFG1_IOCONF_GPIO_CNT_S); // CC13x2 + CC26x2 - if ( ChipInfo_ChipFamilyIs_CC13x2_CC26x2() ) + if (ChipInfo_ChipFamilyIs_CC13x2_CC26x2()) { - return ( (dioNumber >= (31 - ioCount)) && (dioNumber < 31) ) + return ((dioNumber >= (31 - ioCount)) && (dioNumber < 31)) } // Special handling of CC13x0 7x7, where IO_CNT = 30 and legal range is 1..30 // for all other chips legal range is 0..(dioNumber-1) - else if (( ioCount == 30 ) && ChipInfo_ChipFamilyIs_CC13x0() ) + else if ((ioCount == 30) && ChipInfo_ChipFamilyIs_CC13x0()) { - return (( dioNumber > 0 ) && ( dioNumber <= ioCount )); + return ((dioNumber > 0) && (dioNumber <= ioCount)); } else { - return ( dioNumber < ioCount ); + return (dioNumber < ioCount); } - } #endif @@ -106,39 +104,39 @@ dioNumberLegal( uint32_t dioNumber ) // The following values define the bit field for the GPIO DIOs. // //***************************************************************************** -#define GPIO_DIO_0_MASK 0x00000001 // GPIO DIO 0 mask -#define GPIO_DIO_1_MASK 0x00000002 // GPIO DIO 1 mask -#define GPIO_DIO_2_MASK 0x00000004 // GPIO DIO 2 mask -#define GPIO_DIO_3_MASK 0x00000008 // GPIO DIO 3 mask -#define GPIO_DIO_4_MASK 0x00000010 // GPIO DIO 4 mask -#define GPIO_DIO_5_MASK 0x00000020 // GPIO DIO 5 mask -#define GPIO_DIO_6_MASK 0x00000040 // GPIO DIO 6 mask -#define GPIO_DIO_7_MASK 0x00000080 // GPIO DIO 7 mask -#define GPIO_DIO_8_MASK 0x00000100 // GPIO DIO 8 mask -#define GPIO_DIO_9_MASK 0x00000200 // GPIO DIO 9 mask -#define GPIO_DIO_10_MASK 0x00000400 // GPIO DIO 10 mask -#define GPIO_DIO_11_MASK 0x00000800 // GPIO DIO 11 mask -#define GPIO_DIO_12_MASK 0x00001000 // GPIO DIO 12 mask -#define GPIO_DIO_13_MASK 0x00002000 // GPIO DIO 13 mask -#define GPIO_DIO_14_MASK 0x00004000 // GPIO DIO 14 mask -#define GPIO_DIO_15_MASK 0x00008000 // GPIO DIO 15 mask -#define GPIO_DIO_16_MASK 0x00010000 // GPIO DIO 16 mask -#define GPIO_DIO_17_MASK 0x00020000 // GPIO DIO 17 mask -#define GPIO_DIO_18_MASK 0x00040000 // GPIO DIO 18 mask -#define GPIO_DIO_19_MASK 0x00080000 // GPIO DIO 19 mask -#define GPIO_DIO_20_MASK 0x00100000 // GPIO DIO 20 mask -#define GPIO_DIO_21_MASK 0x00200000 // GPIO DIO 21 mask -#define GPIO_DIO_22_MASK 0x00400000 // GPIO DIO 22 mask -#define GPIO_DIO_23_MASK 0x00800000 // GPIO DIO 23 mask -#define GPIO_DIO_24_MASK 0x01000000 // GPIO DIO 24 mask -#define GPIO_DIO_25_MASK 0x02000000 // GPIO DIO 25 mask -#define GPIO_DIO_26_MASK 0x04000000 // GPIO DIO 26 mask -#define GPIO_DIO_27_MASK 0x08000000 // GPIO DIO 27 mask -#define GPIO_DIO_28_MASK 0x10000000 // GPIO DIO 28 mask -#define GPIO_DIO_29_MASK 0x20000000 // GPIO DIO 29 mask -#define GPIO_DIO_30_MASK 0x40000000 // GPIO DIO 30 mask -#define GPIO_DIO_31_MASK 0x80000000 // GPIO DIO 31 mask -#define GPIO_DIO_ALL_MASK 0xFFFFFFFF // GPIO all DIOs mask +#define GPIO_DIO_0_MASK 0x00000001 // GPIO DIO 0 mask +#define GPIO_DIO_1_MASK 0x00000002 // GPIO DIO 1 mask +#define GPIO_DIO_2_MASK 0x00000004 // GPIO DIO 2 mask +#define GPIO_DIO_3_MASK 0x00000008 // GPIO DIO 3 mask +#define GPIO_DIO_4_MASK 0x00000010 // GPIO DIO 4 mask +#define GPIO_DIO_5_MASK 0x00000020 // GPIO DIO 5 mask +#define GPIO_DIO_6_MASK 0x00000040 // GPIO DIO 6 mask +#define GPIO_DIO_7_MASK 0x00000080 // GPIO DIO 7 mask +#define GPIO_DIO_8_MASK 0x00000100 // GPIO DIO 8 mask +#define GPIO_DIO_9_MASK 0x00000200 // GPIO DIO 9 mask +#define GPIO_DIO_10_MASK 0x00000400 // GPIO DIO 10 mask +#define GPIO_DIO_11_MASK 0x00000800 // GPIO DIO 11 mask +#define GPIO_DIO_12_MASK 0x00001000 // GPIO DIO 12 mask +#define GPIO_DIO_13_MASK 0x00002000 // GPIO DIO 13 mask +#define GPIO_DIO_14_MASK 0x00004000 // GPIO DIO 14 mask +#define GPIO_DIO_15_MASK 0x00008000 // GPIO DIO 15 mask +#define GPIO_DIO_16_MASK 0x00010000 // GPIO DIO 16 mask +#define GPIO_DIO_17_MASK 0x00020000 // GPIO DIO 17 mask +#define GPIO_DIO_18_MASK 0x00040000 // GPIO DIO 18 mask +#define GPIO_DIO_19_MASK 0x00080000 // GPIO DIO 19 mask +#define GPIO_DIO_20_MASK 0x00100000 // GPIO DIO 20 mask +#define GPIO_DIO_21_MASK 0x00200000 // GPIO DIO 21 mask +#define GPIO_DIO_22_MASK 0x00400000 // GPIO DIO 22 mask +#define GPIO_DIO_23_MASK 0x00800000 // GPIO DIO 23 mask +#define GPIO_DIO_24_MASK 0x01000000 // GPIO DIO 24 mask +#define GPIO_DIO_25_MASK 0x02000000 // GPIO DIO 25 mask +#define GPIO_DIO_26_MASK 0x04000000 // GPIO DIO 26 mask +#define GPIO_DIO_27_MASK 0x08000000 // GPIO DIO 27 mask +#define GPIO_DIO_28_MASK 0x10000000 // GPIO DIO 28 mask +#define GPIO_DIO_29_MASK 0x20000000 // GPIO DIO 29 mask +#define GPIO_DIO_30_MASK 0x40000000 // GPIO DIO 30 mask +#define GPIO_DIO_31_MASK 0x80000000 // GPIO DIO 31 mask +#define GPIO_DIO_ALL_MASK 0xFFFFFFFF // GPIO all DIOs mask //***************************************************************************** // @@ -147,8 +145,8 @@ dioNumberLegal( uint32_t dioNumber ) // GPIO_getOutputEnableDio(). // //***************************************************************************** -#define GPIO_OUTPUT_DISABLE 0x00000000 // DIO output is disabled -#define GPIO_OUTPUT_ENABLE 0x00000001 // DIO output is enabled +#define GPIO_OUTPUT_DISABLE 0x00000000 // DIO output is disabled +#define GPIO_OUTPUT_ENABLE 0x00000001 // DIO output is enabled //***************************************************************************** // @@ -168,13 +166,13 @@ dioNumberLegal( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE uint32_t -GPIO_readDio( uint32_t dioNumber ) +GPIO_readDio(uint32_t dioNumber) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); + ASSERT(dioNumberLegal(dioNumber)); // Return the input value from the specified DIO. - return (( HWREG( GPIO_BASE + GPIO_O_DIN31_0 ) >> dioNumber ) & 1 ); + return ((HWREG(GPIO_BASE + GPIO_O_DIN31_0) >> dioNumber) & 1); } //***************************************************************************** @@ -198,13 +196,13 @@ GPIO_readDio( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE uint32_t -GPIO_readMultiDio( uint32_t dioMask ) +GPIO_readMultiDio(uint32_t dioMask) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); // Return the input value from the specified DIOs. - return ( HWREG( GPIO_BASE + GPIO_O_DIN31_0 ) & dioMask ); + return (HWREG(GPIO_BASE + GPIO_O_DIN31_0) & dioMask); } //***************************************************************************** @@ -222,14 +220,14 @@ GPIO_readMultiDio( uint32_t dioMask ) // //***************************************************************************** __STATIC_INLINE void -GPIO_writeDio( uint32_t dioNumber, uint32_t value ) +GPIO_writeDio(uint32_t dioNumber, uint32_t value) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); - ASSERT(( value == 0 ) || ( value == 1 )); + ASSERT(dioNumberLegal(dioNumber)); + ASSERT((value == 0) || (value == 1)); // Write 0 or 1 to the byte indexed DOUT map - HWREGB( GPIO_BASE + dioNumber ) = value; + HWREGB(GPIO_BASE + dioNumber) = value; } //***************************************************************************** @@ -254,14 +252,14 @@ GPIO_writeDio( uint32_t dioNumber, uint32_t value ) // //***************************************************************************** __STATIC_INLINE void -GPIO_writeMultiDio( uint32_t dioMask, uint32_t bitVectoredValue ) +GPIO_writeMultiDio(uint32_t dioMask, uint32_t bitVectoredValue) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); - HWREG( GPIO_BASE + GPIO_O_DOUT31_0 ) = - ( HWREG( GPIO_BASE + GPIO_O_DOUT31_0 ) & ~dioMask ) | - ( bitVectoredValue & dioMask ); + HWREG(GPIO_BASE + GPIO_O_DOUT31_0) = + (HWREG(GPIO_BASE + GPIO_O_DOUT31_0) & ~dioMask) | + (bitVectoredValue & dioMask); } //***************************************************************************** @@ -276,13 +274,13 @@ GPIO_writeMultiDio( uint32_t dioMask, uint32_t bitVectoredValue ) // //***************************************************************************** __STATIC_INLINE void -GPIO_setDio( uint32_t dioNumber ) +GPIO_setDio(uint32_t dioNumber) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); + ASSERT(dioNumberLegal(dioNumber)); // Set the specified DIO. - HWREG( GPIO_BASE + GPIO_O_DOUTSET31_0 ) = ( 1 << dioNumber ); + HWREG(GPIO_BASE + GPIO_O_DOUTSET31_0) = (1 << dioNumber); } //***************************************************************************** @@ -301,13 +299,13 @@ GPIO_setDio( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE void -GPIO_setMultiDio( uint32_t dioMask ) +GPIO_setMultiDio(uint32_t dioMask) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); // Set the DIOs. - HWREG( GPIO_BASE + GPIO_O_DOUTSET31_0 ) = dioMask; + HWREG(GPIO_BASE + GPIO_O_DOUTSET31_0) = dioMask; } //***************************************************************************** @@ -322,13 +320,13 @@ GPIO_setMultiDio( uint32_t dioMask ) // //***************************************************************************** __STATIC_INLINE void -GPIO_clearDio( uint32_t dioNumber ) +GPIO_clearDio(uint32_t dioNumber) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); + ASSERT(dioNumberLegal(dioNumber)); // Clear the specified DIO. - HWREG( GPIO_BASE + GPIO_O_DOUTCLR31_0 ) = ( 1 << dioNumber ); + HWREG(GPIO_BASE + GPIO_O_DOUTCLR31_0) = (1 << dioNumber); } //***************************************************************************** @@ -347,13 +345,13 @@ GPIO_clearDio( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE void -GPIO_clearMultiDio( uint32_t dioMask ) +GPIO_clearMultiDio(uint32_t dioMask) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); // Clear the DIOs. - HWREG( GPIO_BASE + GPIO_O_DOUTCLR31_0 ) = dioMask; + HWREG(GPIO_BASE + GPIO_O_DOUTCLR31_0) = dioMask; } //***************************************************************************** @@ -368,13 +366,13 @@ GPIO_clearMultiDio( uint32_t dioMask ) // //***************************************************************************** __STATIC_INLINE void -GPIO_toggleDio( uint32_t dioNumber ) +GPIO_toggleDio(uint32_t dioNumber) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); + ASSERT(dioNumberLegal(dioNumber)); // Toggle the specified DIO. - HWREG( GPIO_BASE + GPIO_O_DOUTTGL31_0 ) = ( 1 << dioNumber ); + HWREG(GPIO_BASE + GPIO_O_DOUTTGL31_0) = (1 << dioNumber); } //***************************************************************************** @@ -393,13 +391,13 @@ GPIO_toggleDio( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE void -GPIO_toggleMultiDio( uint32_t dioMask ) +GPIO_toggleMultiDio(uint32_t dioMask) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); // Toggle the DIOs. - HWREG( GPIO_BASE + GPIO_O_DOUTTGL31_0 ) = dioMask; + HWREG(GPIO_BASE + GPIO_O_DOUTTGL31_0) = dioMask; } //***************************************************************************** @@ -419,13 +417,13 @@ GPIO_toggleMultiDio( uint32_t dioMask ) // //***************************************************************************** __STATIC_INLINE uint32_t -GPIO_getOutputEnableDio( uint32_t dioNumber ) +GPIO_getOutputEnableDio(uint32_t dioNumber) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); + ASSERT(dioNumberLegal(dioNumber)); // Return the output enable status for the specified DIO. - return (( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) >> dioNumber ) & 1 ); + return ((HWREG(GPIO_BASE + GPIO_O_DOE31_0) >> dioNumber) & 1); } //***************************************************************************** @@ -449,13 +447,13 @@ GPIO_getOutputEnableDio( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE uint32_t -GPIO_getOutputEnableMultiDio( uint32_t dioMask ) +GPIO_getOutputEnableMultiDio(uint32_t dioMask) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); // Return the output enable value for the specified DIOs. - return ( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) & dioMask ); + return (HWREG(GPIO_BASE + GPIO_O_DOE31_0) & dioMask); } //***************************************************************************** @@ -476,15 +474,15 @@ GPIO_getOutputEnableMultiDio( uint32_t dioMask ) // //***************************************************************************** __STATIC_INLINE void -GPIO_setOutputEnableDio( uint32_t dioNumber, uint32_t outputEnableValue ) +GPIO_setOutputEnableDio(uint32_t dioNumber, uint32_t outputEnableValue) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); - ASSERT(( outputEnableValue == GPIO_OUTPUT_DISABLE ) || - ( outputEnableValue == GPIO_OUTPUT_ENABLE ) ); + ASSERT(dioNumberLegal(dioNumber)); + ASSERT((outputEnableValue == GPIO_OUTPUT_DISABLE) || + (outputEnableValue == GPIO_OUTPUT_ENABLE)); // Update the output enable bit for the specified DIO. - HWREGBITW( GPIO_BASE + GPIO_O_DOE31_0, dioNumber ) = outputEnableValue; + HWREGBITW(GPIO_BASE + GPIO_O_DOE31_0, dioNumber) = outputEnableValue; } //***************************************************************************** @@ -512,14 +510,14 @@ GPIO_setOutputEnableDio( uint32_t dioNumber, uint32_t outputEnableValue ) // //***************************************************************************** __STATIC_INLINE void -GPIO_setOutputEnableMultiDio( uint32_t dioMask, uint32_t bitVectoredOutputEnable ) +GPIO_setOutputEnableMultiDio(uint32_t dioMask, uint32_t bitVectoredOutputEnable) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); - HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) = - ( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) & ~dioMask ) | - ( bitVectoredOutputEnable & dioMask ); + HWREG(GPIO_BASE + GPIO_O_DOE31_0) = + (HWREG(GPIO_BASE + GPIO_O_DOE31_0) & ~dioMask) | + (bitVectoredOutputEnable & dioMask); } //***************************************************************************** @@ -536,13 +534,13 @@ GPIO_setOutputEnableMultiDio( uint32_t dioMask, uint32_t bitVectoredOutputEnable // //***************************************************************************** __STATIC_INLINE uint32_t -GPIO_getEventDio( uint32_t dioNumber ) +GPIO_getEventDio(uint32_t dioNumber) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); + ASSERT(dioNumberLegal(dioNumber)); // Return the event status for the specified DIO. - return (( HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) >> dioNumber ) & 1 ); + return ((HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0) >> dioNumber) & 1); } //***************************************************************************** @@ -567,13 +565,13 @@ GPIO_getEventDio( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE uint32_t -GPIO_getEventMultiDio( uint32_t dioMask ) +GPIO_getEventMultiDio(uint32_t dioMask) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); // Return the event status for the specified DIO. - return ( HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) & dioMask ); + return (HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0) & dioMask); } //***************************************************************************** @@ -588,13 +586,13 @@ GPIO_getEventMultiDio( uint32_t dioMask ) // //***************************************************************************** __STATIC_INLINE void -GPIO_clearEventDio( uint32_t dioNumber ) +GPIO_clearEventDio(uint32_t dioNumber) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); + ASSERT(dioNumberLegal(dioNumber)); // Clear the event status for the specified DIO. - HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) = ( 1 << dioNumber ); + HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0) = (1 << dioNumber); } //***************************************************************************** @@ -614,13 +612,13 @@ GPIO_clearEventDio( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE void -GPIO_clearEventMultiDio( uint32_t dioMask ) +GPIO_clearEventMultiDio(uint32_t dioMask) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); // Clear the event status for the specified DIOs. - HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) = dioMask; + HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0) = dioMask; } //***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/gpio_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/gpio_doc.h index b4548af..0fe98bb 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/gpio_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/gpio_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: gpio_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: gpio_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup gpio_api //! @{ //! \section sec_gpio Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/group_analog_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/group_analog_doc.h index d6346b3..755fa72 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/group_analog_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/group_analog_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: group_analog_doc.h -* Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016) -* Revision: 47080 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: group_analog_doc.h + * Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016) + * Revision: 47080 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup analog_group //! @{ //! \section sec_analog Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/group_aon_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/group_aon_doc.h index c5056d9..ee6b114 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/group_aon_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/group_aon_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: group_aon_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: group_aon_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup aon_group //! @{ //! \section sec_aon Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/group_aux_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/group_aux_doc.h index 63ddcfd..b3c5402 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/group_aux_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/group_aux_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: group_aux_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: group_aux_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup aux_group //! @{ //! \section sec_aux Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2c.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2c.h index c4ece78..5361dbf 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2c.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2c.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: i2c.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and prototypes for the I2C. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: i2c.h + * Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) + * Revision: 49048 + * + * Description: Defines and prototypes for the I2C. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,20 +55,19 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" +#include "../inc/hw_i2c.h" #include "../inc/hw_ints.h" #include "../inc/hw_memmap.h" -#include "../inc/hw_i2c.h" #include "../inc/hw_sysctl.h" +#include "../inc/hw_types.h" +#include "cpu.h" #include "debug.h" #include "interrupt.h" -#include "cpu.h" +#include +#include //***************************************************************************** // @@ -84,10 +83,10 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define I2CMasterInitExpClk NOROM_I2CMasterInitExpClk -#define I2CMasterErr NOROM_I2CMasterErr -#define I2CIntRegister NOROM_I2CIntRegister -#define I2CIntUnregister NOROM_I2CIntUnregister +#define I2CMasterInitExpClk NOROM_I2CMasterInitExpClk +#define I2CMasterErr NOROM_I2CMasterErr +#define I2CIntRegister NOROM_I2CIntRegister +#define I2CIntUnregister NOROM_I2CIntUnregister #endif //***************************************************************************** @@ -95,25 +94,25 @@ extern "C" // I2C Master commands // //***************************************************************************** -#define I2C_MASTER_CMD_SINGLE_SEND \ +#define I2C_MASTER_CMD_SINGLE_SEND \ 0x00000007 -#define I2C_MASTER_CMD_SINGLE_RECEIVE \ +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ 0x00000007 -#define I2C_MASTER_CMD_BURST_SEND_START \ +#define I2C_MASTER_CMD_BURST_SEND_START \ 0x00000003 -#define I2C_MASTER_CMD_BURST_SEND_CONT \ +#define I2C_MASTER_CMD_BURST_SEND_CONT \ 0x00000001 -#define I2C_MASTER_CMD_BURST_SEND_FINISH \ +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ 0x00000005 -#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ 0x00000004 -#define I2C_MASTER_CMD_BURST_RECEIVE_START \ +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ 0x0000000b -#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ 0x00000009 -#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ 0x00000005 -#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ 0x00000004 //***************************************************************************** @@ -121,7 +120,7 @@ extern "C" // I2C Master error status // //***************************************************************************** -#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_NONE 0 #define I2C_MASTER_ERR_ADDR_ACK 0x00000004 #define I2C_MASTER_ERR_DATA_ACK 0x00000008 #define I2C_MASTER_ERR_ARB_LOST 0x00000010 @@ -131,19 +130,19 @@ extern "C" // I2C Slave action requests // //***************************************************************************** -#define I2C_SLAVE_ACT_NONE 0 -#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data -#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data -#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data +#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte //***************************************************************************** // // I2C Slave interrupts // //***************************************************************************** -#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt. -#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt. -#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt. +#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt. +#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt. +#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt. //***************************************************************************** // @@ -937,20 +936,20 @@ extern void I2CIntUnregister(uint32_t ui32Base); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_I2CMasterInitExpClk -#undef I2CMasterInitExpClk -#define I2CMasterInitExpClk ROM_I2CMasterInitExpClk +#undef I2CMasterInitExpClk +#define I2CMasterInitExpClk ROM_I2CMasterInitExpClk #endif #ifdef ROM_I2CMasterErr -#undef I2CMasterErr -#define I2CMasterErr ROM_I2CMasterErr +#undef I2CMasterErr +#define I2CMasterErr ROM_I2CMasterErr #endif #ifdef ROM_I2CIntRegister -#undef I2CIntRegister -#define I2CIntRegister ROM_I2CIntRegister +#undef I2CIntRegister +#define I2CIntRegister ROM_I2CIntRegister #endif #ifdef ROM_I2CIntUnregister -#undef I2CIntUnregister -#define I2CIntUnregister ROM_I2CIntUnregister +#undef I2CIntUnregister +#define I2CIntUnregister ROM_I2CIntUnregister #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2c_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2c_doc.h index c339318..c2206dd 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2c_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2c_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: i2c_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: i2c_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup i2c_api //! @{ //! \section sec_i2c Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2s.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2s.h index 116b252..c158837 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2s.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2s.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: i2s.h -* Revised: 2018-11-16 11:16:53 +0100 (Fri, 16 Nov 2018) -* Revision: 53356 -* -* Description: Defines and prototypes for the I2S. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: i2s.h + * Revised: 2018-11-16 11:16:53 +0100 (Fri, 16 Nov 2018) + * Revision: 53356 + * + * Description: Defines and prototypes for the I2S. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //**************************************************************************** // @@ -55,18 +55,17 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" #include "../inc/hw_i2s.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "debug.h" #include "interrupt.h" +#include +#include //***************************************************************************** // @@ -82,14 +81,14 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define I2SEnable NOROM_I2SEnable -#define I2SAudioFormatConfigure NOROM_I2SAudioFormatConfigure -#define I2SChannelConfigure NOROM_I2SChannelConfigure -#define I2SBufferConfig NOROM_I2SBufferConfig -#define I2SPointerUpdate NOROM_I2SPointerUpdate -#define I2SPointerSet NOROM_I2SPointerSet -#define I2SSampleStampConfigure NOROM_I2SSampleStampConfigure -#define I2SSampleStampGet NOROM_I2SSampleStampGet +#define I2SEnable NOROM_I2SEnable +#define I2SAudioFormatConfigure NOROM_I2SAudioFormatConfigure +#define I2SChannelConfigure NOROM_I2SChannelConfigure +#define I2SBufferConfig NOROM_I2SBufferConfig +#define I2SPointerUpdate NOROM_I2SPointerUpdate +#define I2SPointerSet NOROM_I2SPointerSet +#define I2SSampleStampConfigure NOROM_I2SSampleStampConfigure +#define I2SSampleStampGet NOROM_I2SSampleStampGet #endif //***************************************************************************** @@ -118,15 +117,15 @@ extern "C" #ifndef DEPRECATED typedef struct { - uint16_t ui16DMABufSize; //!< Size of DMA buffer in number of samples. - uint16_t ui16ChBufSize; //!< Size of Channel buffer. - uint8_t ui8InChan; //!< Input Channel. - uint8_t ui8OutChan; //!< Output Channel. - uint16_t ui16MemLen; //!< Length of the audio words stored in memory. - uint32_t ui32InBase; //!< Base address of the input buffer. - uint32_t ui32InOffset; //!< Value of the current input pointer offset. - uint32_t ui32OutBase; //!< Base address of the output buffer. - uint32_t ui32OutOffset; //!< Value of the current output pointer offset. + uint16_t ui16DMABufSize; //!< Size of DMA buffer in number of samples. + uint16_t ui16ChBufSize; //!< Size of Channel buffer. + uint8_t ui8InChan; //!< Input Channel. + uint8_t ui8OutChan; //!< Output Channel. + uint16_t ui16MemLen; //!< Length of the audio words stored in memory. + uint32_t ui32InBase; //!< Base address of the input buffer. + uint32_t ui32InOffset; //!< Value of the current input pointer offset. + uint32_t ui32OutBase; //!< Base address of the output buffer. + uint32_t ui32OutOffset; //!< Value of the current output pointer offset. } I2SControlTable; #endif @@ -151,9 +150,9 @@ extern I2SControlTable* g_pControlTable; // //***************************************************************************** #ifndef DEPRECATED -#define I2S_DMA_BUF_SIZE_64 0x00000040 -#define I2S_DMA_BUF_SIZE_128 0x00000080 -#define I2S_DMA_BUF_SIZE_256 0x00000100 +#define I2S_DMA_BUF_SIZE_64 0x00000040 +#define I2S_DMA_BUF_SIZE_128 0x00000080 +#define I2S_DMA_BUF_SIZE_256 0x00000100 #endif //***************************************************************************** @@ -162,10 +161,10 @@ extern I2SControlTable* g_pControlTable; // //***************************************************************************** #ifndef DEPRECATED -#define I2S_EXT_WCLK 0x00000001 -#define I2S_INT_WCLK 0x00000002 -#define I2S_INVERT_WCLK 0x00000004 -#define I2S_NORMAL_WCLK 0x00000000 +#define I2S_EXT_WCLK 0x00000001 +#define I2S_INT_WCLK 0x00000002 +#define I2S_INVERT_WCLK 0x00000004 +#define I2S_NORMAL_WCLK 0x00000000 #endif //***************************************************************************** @@ -174,10 +173,10 @@ extern I2SControlTable* g_pControlTable; // //***************************************************************************** #ifndef DEPRECATED -#define I2S_LINE_UNUSED 0x00000000 -#define I2S_LINE_INPUT 0x00000001 -#define I2S_LINE_OUTPUT 0x00000002 -#define I2S_LINE_MASK 0x00000003 +#define I2S_LINE_UNUSED 0x00000000 +#define I2S_LINE_INPUT 0x00000001 +#define I2S_LINE_OUTPUT 0x00000002 +#define I2S_LINE_MASK 0x00000003 #endif //***************************************************************************** @@ -186,42 +185,42 @@ extern I2SControlTable* g_pControlTable; // //***************************************************************************** #ifndef DEPRECATED -#define I2S_CHAN0_ACT 0x00000100 -#define I2S_CHAN1_ACT 0x00000200 -#define I2S_CHAN2_ACT 0x00000400 -#define I2S_CHAN3_ACT 0x00000800 -#define I2S_CHAN4_ACT 0x00001000 -#define I2S_CHAN5_ACT 0x00002000 -#define I2S_CHAN6_ACT 0x00004000 -#define I2S_CHAN7_ACT 0x00008000 -#define I2S_MONO_MODE 0x00000100 -#define I2S_STEREO_MODE 0x00000300 -#define I2S_CHAN_CFG_MASK 0x0000FF00 +#define I2S_CHAN0_ACT 0x00000100 +#define I2S_CHAN1_ACT 0x00000200 +#define I2S_CHAN2_ACT 0x00000400 +#define I2S_CHAN3_ACT 0x00000800 +#define I2S_CHAN4_ACT 0x00001000 +#define I2S_CHAN5_ACT 0x00002000 +#define I2S_CHAN6_ACT 0x00004000 +#define I2S_CHAN7_ACT 0x00008000 +#define I2S_MONO_MODE 0x00000100 +#define I2S_STEREO_MODE 0x00000300 +#define I2S_CHAN_CFG_MASK 0x0000FF00 #endif -#define I2S_CHAN0_MASK 0x00000001 -#define I2S_CHAN1_MASK 0x00000002 -#define I2S_CHAN2_MASK 0x00000004 -#define I2S_CHAN3_MASK 0x00000008 -#define I2S_CHAN4_MASK 0x00000010 -#define I2S_CHAN5_MASK 0x00000020 -#define I2S_CHAN6_MASK 0x00000040 -#define I2S_CHAN7_MASK 0x00000080 +#define I2S_CHAN0_MASK 0x00000001 +#define I2S_CHAN1_MASK 0x00000002 +#define I2S_CHAN2_MASK 0x00000004 +#define I2S_CHAN3_MASK 0x00000008 +#define I2S_CHAN4_MASK 0x00000010 +#define I2S_CHAN5_MASK 0x00000020 +#define I2S_CHAN6_MASK 0x00000040 +#define I2S_CHAN7_MASK 0x00000080 //***************************************************************************** // // Defines for the audio format configuration // //***************************************************************************** -#define I2S_MEM_LENGTH_16 0x00000000 // 16 bit size of word in memory -#define I2S_MEM_LENGTH_24 0x00000080 // 24 bit size of word in memory -#define I2S_POS_EDGE 0x00000040 // Sample on positive edge -#define I2S_NEG_EDGE 0x00000000 // Sample on negative edge -#define I2S_DUAL_PHASE_FMT 0x00000020 // Dual Phased audio format -#define I2S_SINGLE_PHASE_FMT 0x00000000 // Single Phased audio format -#define I2S_WORD_LENGTH_8 0x00000008 // Word length is 8 bits -#define I2S_WORD_LENGTH_16 0x00000010 // Word length is 16 bits -#define I2S_WORD_LENGTH_24 0x00000018 // Word length is 24 bits +#define I2S_MEM_LENGTH_16 0x00000000 // 16 bit size of word in memory +#define I2S_MEM_LENGTH_24 0x00000080 // 24 bit size of word in memory +#define I2S_POS_EDGE 0x00000040 // Sample on positive edge +#define I2S_NEG_EDGE 0x00000000 // Sample on negative edge +#define I2S_DUAL_PHASE_FMT 0x00000020 // Dual Phased audio format +#define I2S_SINGLE_PHASE_FMT 0x00000000 // Single Phased audio format +#define I2S_WORD_LENGTH_8 0x00000008 // Word length is 8 bits +#define I2S_WORD_LENGTH_16 0x00000010 // Word length is 16 bits +#define I2S_WORD_LENGTH_24 0x00000018 // Word length is 24 bits //***************************************************************************** // @@ -229,10 +228,10 @@ extern I2SControlTable* g_pControlTable; // //***************************************************************************** #ifndef DEPRECATED -#define I2S_STMP0 0x00000001 // Sample stamp counter channel 0 -#define I2S_STMP1 0x00000002 // Sample stamp counter channel 1 +#define I2S_STMP0 0x00000001 // Sample stamp counter channel 0 +#define I2S_STMP1 0x00000002 // Sample stamp counter channel 1 #endif -#define I2S_STMP_SATURATION 0x0000FFFF // The saturation value used when +#define I2S_STMP_SATURATION 0x0000FFFF // The saturation value used when // calculating the sample stamp //***************************************************************************** @@ -240,13 +239,13 @@ extern I2SControlTable* g_pControlTable; // Defines for the interrupt // //***************************************************************************** -#define I2S_INT_DMA_IN 0x00000020 // DMA output buffer full interrupt -#define I2S_INT_DMA_OUT 0x00000010 // DMA input buffer empty interrupt -#define I2S_INT_TIMEOUT 0x00000008 // Word Clock Timeout -#define I2S_INT_BUS_ERR 0x00000004 // DMA Bus error -#define I2S_INT_WCLK_ERR 0x00000002 // Word Clock error -#define I2S_INT_PTR_ERR 0x00000001 // Data pointer error (DMA data was not updated in time). -#define I2S_INT_ALL 0x0000003F // All interrupts +#define I2S_INT_DMA_IN 0x00000020 // DMA output buffer full interrupt +#define I2S_INT_DMA_OUT 0x00000010 // DMA input buffer empty interrupt +#define I2S_INT_TIMEOUT 0x00000008 // Word Clock Timeout +#define I2S_INT_BUS_ERR 0x00000004 // DMA Bus error +#define I2S_INT_WCLK_ERR 0x00000002 // Word Clock error +#define I2S_INT_PTR_ERR 0x00000001 // Data pointer error (DMA data was not updated in time). +#define I2S_INT_ALL 0x0000003F // All interrupts //***************************************************************************** // @@ -842,7 +841,6 @@ I2SSampleStampDisable(uint32_t ui32Base) // Clear the enable bit. HWREG(I2S0_BASE + I2S_O_STMPCTL) = 0; - } //***************************************************************************** @@ -955,11 +953,11 @@ __STATIC_INLINE void I2SStop(uint32_t ui32Base) //***************************************************************************** __STATIC_INLINE void I2SFormatConfigure(uint32_t ui32Base, - uint8_t ui8iDataDelay, - uint8_t ui8iMemory24Bits, - uint8_t ui8iSamplingEdge, - bool boolDualPhase, - uint8_t ui8BitsPerSample, + uint8_t ui8iDataDelay, + uint8_t ui8iMemory24Bits, + uint8_t ui8iSamplingEdge, + bool boolDualPhase, + uint8_t ui8BitsPerSample, uint16_t ui16transmissionDelay) { // Check the arguments. @@ -969,11 +967,11 @@ I2SFormatConfigure(uint32_t ui32Base, // Setup register AIFFMTCFG Source. HWREGH(I2S0_BASE + I2S_O_AIFFMTCFG) = - (ui8iDataDelay << I2S_AIFFMTCFG_DATA_DELAY_S) | - (ui8iMemory24Bits << I2S_AIFFMTCFG_MEM_LEN_24_S) | - (ui8iSamplingEdge << I2S_AIFFMTCFG_SMPL_EDGE_S ) | - (boolDualPhase << I2S_AIFFMTCFG_DUAL_PHASE_S) | - (ui8BitsPerSample << I2S_AIFFMTCFG_WORD_LEN_S ); + (ui8iDataDelay << I2S_AIFFMTCFG_DATA_DELAY_S) | + (ui8iMemory24Bits << I2S_AIFFMTCFG_MEM_LEN_24_S) | + (ui8iSamplingEdge << I2S_AIFFMTCFG_SMPL_EDGE_S) | + (boolDualPhase << I2S_AIFFMTCFG_DUAL_PHASE_S) | + (ui8BitsPerSample << I2S_AIFFMTCFG_WORD_LEN_S); // Number of WCLK periods before the first read / write HWREGH(I2S0_BASE + I2S_O_STMPWPER) = ui16transmissionDelay; @@ -1022,8 +1020,8 @@ I2SFormatConfigure(uint32_t ui32Base, //**************************************************************************** __STATIC_INLINE void I2SFrameConfigure(uint32_t ui32Base, - uint8_t ui8StatusAD0, uint8_t ui8ChanAD0, - uint8_t ui8StatusAD1, uint8_t ui8ChanAD1) + uint8_t ui8StatusAD0, uint8_t ui8ChanAD0, + uint8_t ui8StatusAD1, uint8_t ui8ChanAD1) { // Check the arguments. ASSERT(I2SBaseValid(ui32Base)); @@ -1058,8 +1056,8 @@ I2SFrameConfigure(uint32_t ui32Base, //**************************************************************************** __STATIC_INLINE void I2SWclkConfigure(uint32_t ui32Base, - bool boolMaster, - bool boolWCLKInvert) + bool boolMaster, + bool boolWCLKInvert) { // Check the arguments. ASSERT(I2SBaseValid(ui32Base)); @@ -1071,8 +1069,8 @@ I2SWclkConfigure(uint32_t ui32Base, // Setup register WCLK Source. HWREGB(I2S0_BASE + I2S_O_AIFWCLKSRC) = - ((ui8ClkSource << I2S_AIFWCLKSRC_WCLK_SRC_S) | - (boolWCLKInvert << I2S_AIFWCLKSRC_WCLK_INV_S )); + ((ui8ClkSource << I2S_AIFWCLKSRC_WCLK_SRC_S) | + (boolWCLKInvert << I2S_AIFWCLKSRC_WCLK_INV_S)); } //**************************************************************************** @@ -1151,7 +1149,6 @@ I2SInPointerNextGet(uint32_t ui32Base) return (HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT)); } - //**************************************************************************** // //! \brief Get value stored in PTR NEXT OUT register @@ -1306,36 +1303,36 @@ I2SWclkCounterReset(uint32_t ui32Base) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_I2SEnable -#undef I2SEnable -#define I2SEnable ROM_I2SEnable +#undef I2SEnable +#define I2SEnable ROM_I2SEnable #endif #ifdef ROM_I2SAudioFormatConfigure -#undef I2SAudioFormatConfigure -#define I2SAudioFormatConfigure ROM_I2SAudioFormatConfigure +#undef I2SAudioFormatConfigure +#define I2SAudioFormatConfigure ROM_I2SAudioFormatConfigure #endif #ifdef ROM_I2SChannelConfigure -#undef I2SChannelConfigure -#define I2SChannelConfigure ROM_I2SChannelConfigure +#undef I2SChannelConfigure +#define I2SChannelConfigure ROM_I2SChannelConfigure #endif #ifdef ROM_I2SBufferConfig -#undef I2SBufferConfig -#define I2SBufferConfig ROM_I2SBufferConfig +#undef I2SBufferConfig +#define I2SBufferConfig ROM_I2SBufferConfig #endif #ifdef ROM_I2SPointerUpdate -#undef I2SPointerUpdate -#define I2SPointerUpdate ROM_I2SPointerUpdate +#undef I2SPointerUpdate +#define I2SPointerUpdate ROM_I2SPointerUpdate #endif #ifdef ROM_I2SPointerSet -#undef I2SPointerSet -#define I2SPointerSet ROM_I2SPointerSet +#undef I2SPointerSet +#define I2SPointerSet ROM_I2SPointerSet #endif #ifdef ROM_I2SSampleStampConfigure -#undef I2SSampleStampConfigure -#define I2SSampleStampConfigure ROM_I2SSampleStampConfigure +#undef I2SSampleStampConfigure +#define I2SSampleStampConfigure ROM_I2SSampleStampConfigure #endif #ifdef ROM_I2SSampleStampGet -#undef I2SSampleStampGet -#define I2SSampleStampGet ROM_I2SSampleStampGet +#undef I2SSampleStampGet +#define I2SSampleStampGet ROM_I2SSampleStampGet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2s_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2s_doc.h index 27ddceb..d72ccd4 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2s_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/i2s_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: i2s_doc.h -* Revised: $$ -* Revision: $$ -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: i2s_doc.h + * Revised: $$ + * Revision: $$ + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup i2s_api //! @{ //! \section sec_i2s Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/interrupt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/interrupt.h index c297aeb..031bea1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/interrupt.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/interrupt.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: interrupt.h -* Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017) -* Revision: 50272 -* -* Description: Defines and prototypes for the NVIC Interrupt Controller -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: interrupt.h + * Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017) + * Revision: 50272 + * + * Description: Defines and prototypes for the NVIC Interrupt Controller + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,17 +55,16 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_ints.h" +#include "../inc/hw_nvic.h" +#include "../inc/hw_types.h" +#include "cpu.h" +#include "debug.h" #include #include -#include "../inc/hw_ints.h" -#include "../inc/hw_types.h" -#include "../inc/hw_nvic.h" -#include "debug.h" -#include "cpu.h" //***************************************************************************** // @@ -81,17 +80,17 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define IntRegister NOROM_IntRegister -#define IntUnregister NOROM_IntUnregister -#define IntPriorityGroupingSet NOROM_IntPriorityGroupingSet -#define IntPriorityGroupingGet NOROM_IntPriorityGroupingGet -#define IntPrioritySet NOROM_IntPrioritySet -#define IntPriorityGet NOROM_IntPriorityGet -#define IntEnable NOROM_IntEnable -#define IntDisable NOROM_IntDisable -#define IntPendSet NOROM_IntPendSet -#define IntPendGet NOROM_IntPendGet -#define IntPendClear NOROM_IntPendClear +#define IntRegister NOROM_IntRegister +#define IntUnregister NOROM_IntUnregister +#define IntPriorityGroupingSet NOROM_IntPriorityGroupingSet +#define IntPriorityGroupingGet NOROM_IntPriorityGroupingGet +#define IntPrioritySet NOROM_IntPrioritySet +#define IntPriorityGet NOROM_IntPriorityGet +#define IntEnable NOROM_IntEnable +#define IntDisable NOROM_IntDisable +#define IntPendSet NOROM_IntPendSet +#define IntPendGet NOROM_IntPendGet +#define IntPendClear NOROM_IntPendClear #endif //***************************************************************************** @@ -104,15 +103,15 @@ extern "C" // INT_PRIORITY_MASK = ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) // //***************************************************************************** -#define INT_PRIORITY_MASK 0x000000E0 -#define INT_PRI_LEVEL0 0x00000000 -#define INT_PRI_LEVEL1 0x00000020 -#define INT_PRI_LEVEL2 0x00000040 -#define INT_PRI_LEVEL3 0x00000060 -#define INT_PRI_LEVEL4 0x00000080 -#define INT_PRI_LEVEL5 0x000000A0 -#define INT_PRI_LEVEL6 0x000000C0 -#define INT_PRI_LEVEL7 0x000000E0 +#define INT_PRIORITY_MASK 0x000000E0 +#define INT_PRI_LEVEL0 0x00000000 +#define INT_PRI_LEVEL1 0x00000020 +#define INT_PRI_LEVEL2 0x00000040 +#define INT_PRI_LEVEL3 0x00000060 +#define INT_PRI_LEVEL4 0x00000080 +#define INT_PRI_LEVEL5 0x000000A0 +#define INT_PRI_LEVEL6 0x000000C0 +#define INT_PRI_LEVEL7 0x000000E0 //***************************************************************************** // @@ -637,48 +636,48 @@ IntPriorityMaskGet(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_IntRegister -#undef IntRegister -#define IntRegister ROM_IntRegister +#undef IntRegister +#define IntRegister ROM_IntRegister #endif #ifdef ROM_IntUnregister -#undef IntUnregister -#define IntUnregister ROM_IntUnregister +#undef IntUnregister +#define IntUnregister ROM_IntUnregister #endif #ifdef ROM_IntPriorityGroupingSet -#undef IntPriorityGroupingSet -#define IntPriorityGroupingSet ROM_IntPriorityGroupingSet +#undef IntPriorityGroupingSet +#define IntPriorityGroupingSet ROM_IntPriorityGroupingSet #endif #ifdef ROM_IntPriorityGroupingGet -#undef IntPriorityGroupingGet -#define IntPriorityGroupingGet ROM_IntPriorityGroupingGet +#undef IntPriorityGroupingGet +#define IntPriorityGroupingGet ROM_IntPriorityGroupingGet #endif #ifdef ROM_IntPrioritySet -#undef IntPrioritySet -#define IntPrioritySet ROM_IntPrioritySet +#undef IntPrioritySet +#define IntPrioritySet ROM_IntPrioritySet #endif #ifdef ROM_IntPriorityGet -#undef IntPriorityGet -#define IntPriorityGet ROM_IntPriorityGet +#undef IntPriorityGet +#define IntPriorityGet ROM_IntPriorityGet #endif #ifdef ROM_IntEnable -#undef IntEnable -#define IntEnable ROM_IntEnable +#undef IntEnable +#define IntEnable ROM_IntEnable #endif #ifdef ROM_IntDisable -#undef IntDisable -#define IntDisable ROM_IntDisable +#undef IntDisable +#define IntDisable ROM_IntDisable #endif #ifdef ROM_IntPendSet -#undef IntPendSet -#define IntPendSet ROM_IntPendSet +#undef IntPendSet +#define IntPendSet ROM_IntPendSet #endif #ifdef ROM_IntPendGet -#undef IntPendGet -#define IntPendGet ROM_IntPendGet +#undef IntPendGet +#define IntPendGet ROM_IntPendGet #endif #ifdef ROM_IntPendClear -#undef IntPendClear -#define IntPendClear ROM_IntPendClear +#undef IntPendClear +#define IntPendClear ROM_IntPendClear #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/interrupt_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/interrupt_doc.h index ff02174..903851c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/interrupt_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/interrupt_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: interrupt_doc.h -* Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017) -* Revision: 50272 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: interrupt_doc.h + * Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017) + * Revision: 50272 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup interrupt_api //! @{ //! \section sec_interrupt Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ioc.h index b612410..6002559 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ioc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ioc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: ioc.h -* Revised: 2017-11-02 14:16:14 +0100 (Thu, 02 Nov 2017) -* Revision: 50156 -* -* Description: Defines and prototypes for the IO Controller. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: ioc.h + * Revised: 2017-11-02 14:16:14 +0100 (Thu, 02 Nov 2017) + * Revision: 50156 + * + * Description: Defines and prototypes for the IO Controller. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,19 +55,18 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ioc.h" #include "../inc/hw_ints.h" -#include "interrupt.h" +#include "../inc/hw_ioc.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "debug.h" #include "gpio.h" +#include "interrupt.h" +#include +#include //***************************************************************************** // @@ -83,26 +82,26 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define IOCPortConfigureSet NOROM_IOCPortConfigureSet -#define IOCPortConfigureGet NOROM_IOCPortConfigureGet -#define IOCIOShutdownSet NOROM_IOCIOShutdownSet -#define IOCIOModeSet NOROM_IOCIOModeSet -#define IOCIOIntSet NOROM_IOCIOIntSet -#define IOCIOPortPullSet NOROM_IOCIOPortPullSet -#define IOCIOHystSet NOROM_IOCIOHystSet -#define IOCIOInputSet NOROM_IOCIOInputSet -#define IOCIOSlewCtrlSet NOROM_IOCIOSlewCtrlSet -#define IOCIODrvStrengthSet NOROM_IOCIODrvStrengthSet -#define IOCIOPortIdSet NOROM_IOCIOPortIdSet -#define IOCIntEnable NOROM_IOCIntEnable -#define IOCIntDisable NOROM_IOCIntDisable -#define IOCPinTypeGpioInput NOROM_IOCPinTypeGpioInput -#define IOCPinTypeGpioOutput NOROM_IOCPinTypeGpioOutput -#define IOCPinTypeUart NOROM_IOCPinTypeUart -#define IOCPinTypeSsiMaster NOROM_IOCPinTypeSsiMaster -#define IOCPinTypeSsiSlave NOROM_IOCPinTypeSsiSlave -#define IOCPinTypeI2c NOROM_IOCPinTypeI2c -#define IOCPinTypeAux NOROM_IOCPinTypeAux +#define IOCPortConfigureSet NOROM_IOCPortConfigureSet +#define IOCPortConfigureGet NOROM_IOCPortConfigureGet +#define IOCIOShutdownSet NOROM_IOCIOShutdownSet +#define IOCIOModeSet NOROM_IOCIOModeSet +#define IOCIOIntSet NOROM_IOCIOIntSet +#define IOCIOPortPullSet NOROM_IOCIOPortPullSet +#define IOCIOHystSet NOROM_IOCIOHystSet +#define IOCIOInputSet NOROM_IOCIOInputSet +#define IOCIOSlewCtrlSet NOROM_IOCIOSlewCtrlSet +#define IOCIODrvStrengthSet NOROM_IOCIODrvStrengthSet +#define IOCIOPortIdSet NOROM_IOCIOPortIdSet +#define IOCIntEnable NOROM_IOCIntEnable +#define IOCIntDisable NOROM_IOCIntDisable +#define IOCPinTypeGpioInput NOROM_IOCPinTypeGpioInput +#define IOCPinTypeGpioOutput NOROM_IOCPinTypeGpioOutput +#define IOCPinTypeUart NOROM_IOCPinTypeUart +#define IOCPinTypeSsiMaster NOROM_IOCPinTypeSsiMaster +#define IOCPinTypeSsiSlave NOROM_IOCPinTypeSsiSlave +#define IOCPinTypeI2c NOROM_IOCPinTypeI2c +#define IOCPinTypeAux NOROM_IOCPinTypeAux #endif //***************************************************************************** @@ -117,41 +116,41 @@ extern "C" // The following fields are IO Id for the IOC module // //***************************************************************************** -#define IOID_0 0x00000000 // IO Id 0 -#define IOID_1 0x00000001 // IO Id 1 -#define IOID_2 0x00000002 // IO Id 2 -#define IOID_3 0x00000003 // IO Id 3 -#define IOID_4 0x00000004 // IO Id 4 -#define IOID_5 0x00000005 // IO Id 5 -#define IOID_6 0x00000006 // IO Id 6 -#define IOID_7 0x00000007 // IO Id 7 -#define IOID_8 0x00000008 // IO Id 8 -#define IOID_9 0x00000009 // IO Id 9 -#define IOID_10 0x0000000A // IO Id 10 -#define IOID_11 0x0000000B // IO Id 11 -#define IOID_12 0x0000000C // IO Id 12 -#define IOID_13 0x0000000D // IO Id 13 -#define IOID_14 0x0000000E // IO Id 14 -#define IOID_15 0x0000000F // IO Id 15 -#define IOID_16 0x00000010 // IO Id 16 -#define IOID_17 0x00000011 // IO Id 17 -#define IOID_18 0x00000012 // IO Id 18 -#define IOID_19 0x00000013 // IO Id 19 -#define IOID_20 0x00000014 // IO Id 20 -#define IOID_21 0x00000015 // IO Id 21 -#define IOID_22 0x00000016 // IO Id 22 -#define IOID_23 0x00000017 // IO Id 23 -#define IOID_24 0x00000018 // IO Id 24 -#define IOID_25 0x00000019 // IO Id 25 -#define IOID_26 0x0000001A // IO Id 26 -#define IOID_27 0x0000001B // IO Id 27 -#define IOID_28 0x0000001C // IO Id 28 -#define IOID_29 0x0000001D // IO Id 29 -#define IOID_30 0x0000001E // IO Id 30 -#define IOID_31 0x0000001F // IO Id 31 -#define IOID_UNUSED 0xFFFFFFFF // Unused IO Id +#define IOID_0 0x00000000 // IO Id 0 +#define IOID_1 0x00000001 // IO Id 1 +#define IOID_2 0x00000002 // IO Id 2 +#define IOID_3 0x00000003 // IO Id 3 +#define IOID_4 0x00000004 // IO Id 4 +#define IOID_5 0x00000005 // IO Id 5 +#define IOID_6 0x00000006 // IO Id 6 +#define IOID_7 0x00000007 // IO Id 7 +#define IOID_8 0x00000008 // IO Id 8 +#define IOID_9 0x00000009 // IO Id 9 +#define IOID_10 0x0000000A // IO Id 10 +#define IOID_11 0x0000000B // IO Id 11 +#define IOID_12 0x0000000C // IO Id 12 +#define IOID_13 0x0000000D // IO Id 13 +#define IOID_14 0x0000000E // IO Id 14 +#define IOID_15 0x0000000F // IO Id 15 +#define IOID_16 0x00000010 // IO Id 16 +#define IOID_17 0x00000011 // IO Id 17 +#define IOID_18 0x00000012 // IO Id 18 +#define IOID_19 0x00000013 // IO Id 19 +#define IOID_20 0x00000014 // IO Id 20 +#define IOID_21 0x00000015 // IO Id 21 +#define IOID_22 0x00000016 // IO Id 22 +#define IOID_23 0x00000017 // IO Id 23 +#define IOID_24 0x00000018 // IO Id 24 +#define IOID_25 0x00000019 // IO Id 25 +#define IOID_26 0x0000001A // IO Id 26 +#define IOID_27 0x0000001B // IO Id 27 +#define IOID_28 0x0000001C // IO Id 28 +#define IOID_29 0x0000001D // IO Id 29 +#define IOID_30 0x0000001E // IO Id 30 +#define IOID_31 0x0000001F // IO Id 31 +#define IOID_UNUSED 0xFFFFFFFF // Unused IO Id -#define IOC_IOID_MASK 0x000000FF // IOC IO Id bit mask +#define IOC_IOID_MASK 0x000000FF // IOC IO Id bit mask //***************************************************************************** // @@ -165,86 +164,86 @@ extern "C" // IOC Peripheral Port Mapping // //***************************************************************************** -#define IOC_PORT_GPIO 0x00000000 // Default general purpose IO usage -#define IOC_PORT_AON_CLK32K 0x00000007 // AON External 32kHz clock -#define IOC_PORT_AUX_IO 0x00000008 // AUX IO Pin -#define IOC_PORT_MCU_SSI0_RX 0x00000009 // MCU SSI0 Receive Pin -#define IOC_PORT_MCU_SSI0_TX 0x0000000A // MCU SSI0 Transmit Pin -#define IOC_PORT_MCU_SSI0_FSS 0x0000000B // MCU SSI0 FSS Pin -#define IOC_PORT_MCU_SSI0_CLK 0x0000000C // MCU SSI0 Clock Pin -#define IOC_PORT_MCU_I2C_MSSDA 0x0000000D // MCU I2C Data Pin -#define IOC_PORT_MCU_I2C_MSSCL 0x0000000E // MCU I2C Clock Pin -#define IOC_PORT_MCU_UART0_RX 0x0000000F // MCU UART0 Receive Pin -#define IOC_PORT_MCU_UART0_TX 0x00000010 // MCU UART0 Transmit Pin -#define IOC_PORT_MCU_UART0_CTS 0x00000011 // MCU UART0 Clear To Send Pin -#define IOC_PORT_MCU_UART0_RTS 0x00000012 // MCU UART0 Request To Send Pin -#define IOC_PORT_MCU_PORT_EVENT0 0x00000017 // MCU PORT EVENT 0 -#define IOC_PORT_MCU_PORT_EVENT1 0x00000018 // MCU PORT EVENT 1 -#define IOC_PORT_MCU_PORT_EVENT2 0x00000019 // MCU PORT EVENT 2 -#define IOC_PORT_MCU_PORT_EVENT3 0x0000001A // MCU PORT EVENT 3 -#define IOC_PORT_MCU_PORT_EVENT4 0x0000001B // MCU PORT EVENT 4 -#define IOC_PORT_MCU_PORT_EVENT5 0x0000001C // MCU PORT EVENT 5 -#define IOC_PORT_MCU_PORT_EVENT6 0x0000001D // MCU PORT EVENT 6 -#define IOC_PORT_MCU_PORT_EVENT7 0x0000001E // MCU PORT EVENT 7 -#define IOC_PORT_MCU_SWV 0x00000020 // Serial Wire Viewer -#define IOC_PORT_MCU_SSI1_RX 0x00000021 // MCU SSI1 Receive Pin -#define IOC_PORT_MCU_SSI1_TX 0x00000022 // MCU SSI1 Transmit Pin -#define IOC_PORT_MCU_SSI1_FSS 0x00000023 // MCU SSI1 FSS Pin -#define IOC_PORT_MCU_SSI1_CLK 0x00000024 // MCU SSI1 Clock Pin -#define IOC_PORT_MCU_I2S_AD0 0x00000025 // MCU I2S Data Pin 0 -#define IOC_PORT_MCU_I2S_AD1 0x00000026 // MCU I2S Data Pin 1 -#define IOC_PORT_MCU_I2S_WCLK 0x00000027 // MCU I2S Frame/Word Clock -#define IOC_PORT_MCU_I2S_BCLK 0x00000028 // MCU I2S Bit Clock -#define IOC_PORT_MCU_I2S_MCLK 0x00000029 // MCU I2S Master clock 2 -#define IOC_PORT_RFC_TRC 0x0000002E // RF Core Tracer -#define IOC_PORT_RFC_GPO0 0x0000002F // RC Core Data Out Pin 0 -#define IOC_PORT_RFC_GPO1 0x00000030 // RC Core Data Out Pin 1 -#define IOC_PORT_RFC_GPO2 0x00000031 // RC Core Data Out Pin 2 -#define IOC_PORT_RFC_GPO3 0x00000032 // RC Core Data Out Pin 3 -#define IOC_PORT_RFC_GPI0 0x00000033 // RC Core Data In Pin 0 -#define IOC_PORT_RFC_GPI1 0x00000034 // RC Core Data In Pin 1 -#define IOC_PORT_RFC_SMI_DL_OUT 0x00000035 // RF Core SMI Data Link Out -#define IOC_PORT_RFC_SMI_DL_IN 0x00000036 // RF Core SMI Data Link in -#define IOC_PORT_RFC_SMI_CL_OUT 0x00000037 // RF Core SMI Command Link Out -#define IOC_PORT_RFC_SMI_CL_IN 0x00000038 // RF Core SMI Command Link In +#define IOC_PORT_GPIO 0x00000000 // Default general purpose IO usage +#define IOC_PORT_AON_CLK32K 0x00000007 // AON External 32kHz clock +#define IOC_PORT_AUX_IO 0x00000008 // AUX IO Pin +#define IOC_PORT_MCU_SSI0_RX 0x00000009 // MCU SSI0 Receive Pin +#define IOC_PORT_MCU_SSI0_TX 0x0000000A // MCU SSI0 Transmit Pin +#define IOC_PORT_MCU_SSI0_FSS 0x0000000B // MCU SSI0 FSS Pin +#define IOC_PORT_MCU_SSI0_CLK 0x0000000C // MCU SSI0 Clock Pin +#define IOC_PORT_MCU_I2C_MSSDA 0x0000000D // MCU I2C Data Pin +#define IOC_PORT_MCU_I2C_MSSCL 0x0000000E // MCU I2C Clock Pin +#define IOC_PORT_MCU_UART0_RX 0x0000000F // MCU UART0 Receive Pin +#define IOC_PORT_MCU_UART0_TX 0x00000010 // MCU UART0 Transmit Pin +#define IOC_PORT_MCU_UART0_CTS 0x00000011 // MCU UART0 Clear To Send Pin +#define IOC_PORT_MCU_UART0_RTS 0x00000012 // MCU UART0 Request To Send Pin +#define IOC_PORT_MCU_PORT_EVENT0 0x00000017 // MCU PORT EVENT 0 +#define IOC_PORT_MCU_PORT_EVENT1 0x00000018 // MCU PORT EVENT 1 +#define IOC_PORT_MCU_PORT_EVENT2 0x00000019 // MCU PORT EVENT 2 +#define IOC_PORT_MCU_PORT_EVENT3 0x0000001A // MCU PORT EVENT 3 +#define IOC_PORT_MCU_PORT_EVENT4 0x0000001B // MCU PORT EVENT 4 +#define IOC_PORT_MCU_PORT_EVENT5 0x0000001C // MCU PORT EVENT 5 +#define IOC_PORT_MCU_PORT_EVENT6 0x0000001D // MCU PORT EVENT 6 +#define IOC_PORT_MCU_PORT_EVENT7 0x0000001E // MCU PORT EVENT 7 +#define IOC_PORT_MCU_SWV 0x00000020 // Serial Wire Viewer +#define IOC_PORT_MCU_SSI1_RX 0x00000021 // MCU SSI1 Receive Pin +#define IOC_PORT_MCU_SSI1_TX 0x00000022 // MCU SSI1 Transmit Pin +#define IOC_PORT_MCU_SSI1_FSS 0x00000023 // MCU SSI1 FSS Pin +#define IOC_PORT_MCU_SSI1_CLK 0x00000024 // MCU SSI1 Clock Pin +#define IOC_PORT_MCU_I2S_AD0 0x00000025 // MCU I2S Data Pin 0 +#define IOC_PORT_MCU_I2S_AD1 0x00000026 // MCU I2S Data Pin 1 +#define IOC_PORT_MCU_I2S_WCLK 0x00000027 // MCU I2S Frame/Word Clock +#define IOC_PORT_MCU_I2S_BCLK 0x00000028 // MCU I2S Bit Clock +#define IOC_PORT_MCU_I2S_MCLK 0x00000029 // MCU I2S Master clock 2 +#define IOC_PORT_RFC_TRC 0x0000002E // RF Core Tracer +#define IOC_PORT_RFC_GPO0 0x0000002F // RC Core Data Out Pin 0 +#define IOC_PORT_RFC_GPO1 0x00000030 // RC Core Data Out Pin 1 +#define IOC_PORT_RFC_GPO2 0x00000031 // RC Core Data Out Pin 2 +#define IOC_PORT_RFC_GPO3 0x00000032 // RC Core Data Out Pin 3 +#define IOC_PORT_RFC_GPI0 0x00000033 // RC Core Data In Pin 0 +#define IOC_PORT_RFC_GPI1 0x00000034 // RC Core Data In Pin 1 +#define IOC_PORT_RFC_SMI_DL_OUT 0x00000035 // RF Core SMI Data Link Out +#define IOC_PORT_RFC_SMI_DL_IN 0x00000036 // RF Core SMI Data Link in +#define IOC_PORT_RFC_SMI_CL_OUT 0x00000037 // RF Core SMI Command Link Out +#define IOC_PORT_RFC_SMI_CL_IN 0x00000038 // RF Core SMI Command Link In //***************************************************************************** // // Defines for enabling/disabling an IO // //***************************************************************************** -#define IOC_SLEW_ENABLE 0x00001000 -#define IOC_SLEW_DISABLE 0x00000000 -#define IOC_INPUT_ENABLE 0x20000000 -#define IOC_INPUT_DISABLE 0x00000000 -#define IOC_HYST_ENABLE 0x40000000 -#define IOC_HYST_DISABLE 0x00000000 +#define IOC_SLEW_ENABLE 0x00001000 +#define IOC_SLEW_DISABLE 0x00000000 +#define IOC_INPUT_ENABLE 0x20000000 +#define IOC_INPUT_DISABLE 0x00000000 +#define IOC_HYST_ENABLE 0x40000000 +#define IOC_HYST_DISABLE 0x00000000 //***************************************************************************** // // Defines that can be used to set the shutdown mode of an IO // //***************************************************************************** -#define IOC_NO_WAKE_UP 0x00000000 -#define IOC_WAKE_ON_LOW 0x10000000 -#define IOC_WAKE_ON_HIGH 0x18000000 +#define IOC_NO_WAKE_UP 0x00000000 +#define IOC_WAKE_ON_LOW 0x10000000 +#define IOC_WAKE_ON_HIGH 0x18000000 //***************************************************************************** // // Defines that can be used to set the IO Mode of an IO // //***************************************************************************** -#define IOC_IOMODE_NORMAL 0x00000000 // Normal Input/Output -#define IOC_IOMODE_INV 0x01000000 // Inverted Input/Output +#define IOC_IOMODE_NORMAL 0x00000000 // Normal Input/Output +#define IOC_IOMODE_INV 0x01000000 // Inverted Input/Output #define IOC_IOMODE_OPEN_DRAIN_NORMAL \ - 0x04000000 // Open Drain, Normal Input/Output + 0x04000000 // Open Drain, Normal Input/Output #define IOC_IOMODE_OPEN_DRAIN_INV \ - 0x05000000 // Open Drain, Inverted + 0x05000000 // Open Drain, Inverted // Input/Output #define IOC_IOMODE_OPEN_SRC_NORMAL \ - 0x06000000 // Open Source, Normal Input/Output + 0x06000000 // Open Source, Normal Input/Output #define IOC_IOMODE_OPEN_SRC_INV \ - 0x07000000 // Open Source, Inverted + 0x07000000 // Open Source, Inverted // Input/Output //***************************************************************************** @@ -252,41 +251,41 @@ extern "C" // Defines that can be used to set the edge detection on an IO // //***************************************************************************** -#define IOC_NO_EDGE 0x00000000 // No edge detection -#define IOC_FALLING_EDGE 0x00010000 // Edge detection on falling edge -#define IOC_RISING_EDGE 0x00020000 // Edge detection on rising edge -#define IOC_BOTH_EDGES 0x00030000 // Edge detection on both edges -#define IOC_INT_ENABLE 0x00040000 // Enable interrupt on edge detect -#define IOC_INT_DISABLE 0x00000000 // Disable interrupt on edge detect -#define IOC_INT_M 0x00070000 // Int config mask +#define IOC_NO_EDGE 0x00000000 // No edge detection +#define IOC_FALLING_EDGE 0x00010000 // Edge detection on falling edge +#define IOC_RISING_EDGE 0x00020000 // Edge detection on rising edge +#define IOC_BOTH_EDGES 0x00030000 // Edge detection on both edges +#define IOC_INT_ENABLE 0x00040000 // Enable interrupt on edge detect +#define IOC_INT_DISABLE 0x00000000 // Disable interrupt on edge detect +#define IOC_INT_M 0x00070000 // Int config mask //***************************************************************************** // // Defines that be used to set pull on an IO // //***************************************************************************** -#define IOC_NO_IOPULL 0x00006000 // No IO pull -#define IOC_IOPULL_UP 0x00004000 // Pull up -#define IOC_IOPULL_DOWN 0x00002000 // Pull down -#define IOC_IOPULL_M 0x00006000 // Pull config mask -#define IOC_IOPULL_M 0x00006000 +#define IOC_NO_IOPULL 0x00006000 // No IO pull +#define IOC_IOPULL_UP 0x00004000 // Pull up +#define IOC_IOPULL_DOWN 0x00002000 // Pull down +#define IOC_IOPULL_M 0x00006000 // Pull config mask +#define IOC_IOPULL_M 0x00006000 //***************************************************************************** // // Defines that can be used to select the drive strength of an IO // //***************************************************************************** -#define IOC_CURRENT_2MA 0x00000000 // 2mA drive strength -#define IOC_CURRENT_4MA 0x00000400 // 4mA drive strength -#define IOC_CURRENT_8MA 0x00000800 // 4 or 8mA drive strength +#define IOC_CURRENT_2MA 0x00000000 // 2mA drive strength +#define IOC_CURRENT_4MA 0x00000400 // 4mA drive strength +#define IOC_CURRENT_8MA 0x00000800 // 4 or 8mA drive strength -#define IOC_STRENGTH_AUTO 0x00000000 // Automatic Drive Strength +#define IOC_STRENGTH_AUTO 0x00000000 // Automatic Drive Strength // (2/4/8 mA @ VVDS) -#define IOC_STRENGTH_MAX 0x00000300 // Maximum Drive Strength +#define IOC_STRENGTH_MAX 0x00000300 // Maximum Drive Strength // (2/4/8 mA @ 1.8V) -#define IOC_STRENGTH_MED 0x00000200 // Medium Drive Strength +#define IOC_STRENGTH_MED 0x00000200 // Medium Drive Strength // (2/4/8 mA @ 2.5V) -#define IOC_STRENGTH_MIN 0x00000100 // Minimum Drive Strength +#define IOC_STRENGTH_MIN 0x00000100 // Minimum Drive Strength // (2/4/8 mA @ 3.3V) //***************************************************************************** @@ -294,16 +293,16 @@ extern "C" // Defines for standard IO setup // //***************************************************************************** -#define IOC_STD_INPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ - IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ - IOC_HYST_DISABLE | IOC_NO_EDGE | \ - IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ - IOC_NO_WAKE_UP | IOC_INPUT_ENABLE ) -#define IOC_STD_OUTPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ - IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ - IOC_HYST_DISABLE | IOC_NO_EDGE | \ - IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ - IOC_NO_WAKE_UP | IOC_INPUT_DISABLE ) +#define IOC_STD_INPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ + IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ + IOC_HYST_DISABLE | IOC_NO_EDGE | \ + IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ + IOC_NO_WAKE_UP | IOC_INPUT_ENABLE) +#define IOC_STD_OUTPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ + IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ + IOC_HYST_DISABLE | IOC_NO_EDGE | \ + IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ + IOC_NO_WAKE_UP | IOC_INPUT_DISABLE) //***************************************************************************** // @@ -466,7 +465,6 @@ extern uint32_t IOCPortConfigureGet(uint32_t ui32IOId); //***************************************************************************** extern void IOCIOShutdownSet(uint32_t ui32IOId, uint32_t ui32IOShutdown); - //***************************************************************************** // //! \brief Set the IO Mode of an IO Port. @@ -837,7 +835,6 @@ IOCIntStatus(uint32_t ui32IOId) return (GPIO_getEventDio(ui32IOId)); } - //***************************************************************************** // //! \brief Setup an IO for standard GPIO input. @@ -1021,7 +1018,6 @@ extern void IOCPinTypeSsiSlave(uint32_t ui32Base, uint32_t ui32Rx, extern void IOCPinTypeI2c(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk); - //***************************************************************************** // //! \brief Configure an IO for AUX control. @@ -1053,84 +1049,84 @@ extern void IOCPinTypeAux(uint32_t ui32IOId); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_IOCPortConfigureSet -#undef IOCPortConfigureSet -#define IOCPortConfigureSet ROM_IOCPortConfigureSet +#undef IOCPortConfigureSet +#define IOCPortConfigureSet ROM_IOCPortConfigureSet #endif #ifdef ROM_IOCPortConfigureGet -#undef IOCPortConfigureGet -#define IOCPortConfigureGet ROM_IOCPortConfigureGet +#undef IOCPortConfigureGet +#define IOCPortConfigureGet ROM_IOCPortConfigureGet #endif #ifdef ROM_IOCIOShutdownSet -#undef IOCIOShutdownSet -#define IOCIOShutdownSet ROM_IOCIOShutdownSet +#undef IOCIOShutdownSet +#define IOCIOShutdownSet ROM_IOCIOShutdownSet #endif #ifdef ROM_IOCIOModeSet -#undef IOCIOModeSet -#define IOCIOModeSet ROM_IOCIOModeSet +#undef IOCIOModeSet +#define IOCIOModeSet ROM_IOCIOModeSet #endif #ifdef ROM_IOCIOIntSet -#undef IOCIOIntSet -#define IOCIOIntSet ROM_IOCIOIntSet +#undef IOCIOIntSet +#define IOCIOIntSet ROM_IOCIOIntSet #endif #ifdef ROM_IOCIOPortPullSet -#undef IOCIOPortPullSet -#define IOCIOPortPullSet ROM_IOCIOPortPullSet +#undef IOCIOPortPullSet +#define IOCIOPortPullSet ROM_IOCIOPortPullSet #endif #ifdef ROM_IOCIOHystSet -#undef IOCIOHystSet -#define IOCIOHystSet ROM_IOCIOHystSet +#undef IOCIOHystSet +#define IOCIOHystSet ROM_IOCIOHystSet #endif #ifdef ROM_IOCIOInputSet -#undef IOCIOInputSet -#define IOCIOInputSet ROM_IOCIOInputSet +#undef IOCIOInputSet +#define IOCIOInputSet ROM_IOCIOInputSet #endif #ifdef ROM_IOCIOSlewCtrlSet -#undef IOCIOSlewCtrlSet -#define IOCIOSlewCtrlSet ROM_IOCIOSlewCtrlSet +#undef IOCIOSlewCtrlSet +#define IOCIOSlewCtrlSet ROM_IOCIOSlewCtrlSet #endif #ifdef ROM_IOCIODrvStrengthSet -#undef IOCIODrvStrengthSet -#define IOCIODrvStrengthSet ROM_IOCIODrvStrengthSet +#undef IOCIODrvStrengthSet +#define IOCIODrvStrengthSet ROM_IOCIODrvStrengthSet #endif #ifdef ROM_IOCIOPortIdSet -#undef IOCIOPortIdSet -#define IOCIOPortIdSet ROM_IOCIOPortIdSet +#undef IOCIOPortIdSet +#define IOCIOPortIdSet ROM_IOCIOPortIdSet #endif #ifdef ROM_IOCIntEnable -#undef IOCIntEnable -#define IOCIntEnable ROM_IOCIntEnable +#undef IOCIntEnable +#define IOCIntEnable ROM_IOCIntEnable #endif #ifdef ROM_IOCIntDisable -#undef IOCIntDisable -#define IOCIntDisable ROM_IOCIntDisable +#undef IOCIntDisable +#define IOCIntDisable ROM_IOCIntDisable #endif #ifdef ROM_IOCPinTypeGpioInput -#undef IOCPinTypeGpioInput -#define IOCPinTypeGpioInput ROM_IOCPinTypeGpioInput +#undef IOCPinTypeGpioInput +#define IOCPinTypeGpioInput ROM_IOCPinTypeGpioInput #endif #ifdef ROM_IOCPinTypeGpioOutput -#undef IOCPinTypeGpioOutput -#define IOCPinTypeGpioOutput ROM_IOCPinTypeGpioOutput +#undef IOCPinTypeGpioOutput +#define IOCPinTypeGpioOutput ROM_IOCPinTypeGpioOutput #endif #ifdef ROM_IOCPinTypeUart -#undef IOCPinTypeUart -#define IOCPinTypeUart ROM_IOCPinTypeUart +#undef IOCPinTypeUart +#define IOCPinTypeUart ROM_IOCPinTypeUart #endif #ifdef ROM_IOCPinTypeSsiMaster -#undef IOCPinTypeSsiMaster -#define IOCPinTypeSsiMaster ROM_IOCPinTypeSsiMaster +#undef IOCPinTypeSsiMaster +#define IOCPinTypeSsiMaster ROM_IOCPinTypeSsiMaster #endif #ifdef ROM_IOCPinTypeSsiSlave -#undef IOCPinTypeSsiSlave -#define IOCPinTypeSsiSlave ROM_IOCPinTypeSsiSlave +#undef IOCPinTypeSsiSlave +#define IOCPinTypeSsiSlave ROM_IOCPinTypeSsiSlave #endif #ifdef ROM_IOCPinTypeI2c -#undef IOCPinTypeI2c -#define IOCPinTypeI2c ROM_IOCPinTypeI2c +#undef IOCPinTypeI2c +#define IOCPinTypeI2c ROM_IOCPinTypeI2c #endif #ifdef ROM_IOCPinTypeAux -#undef IOCPinTypeAux -#define IOCPinTypeAux ROM_IOCPinTypeAux +#undef IOCPinTypeAux +#define IOCPinTypeAux ROM_IOCPinTypeAux #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ioc_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ioc_doc.h index cd35eff..1e1a32e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ioc_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ioc_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: ioc_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: ioc_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup ioc_api //! @{ //! \section sec_ioc Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/osc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/osc.h index 3bfb71c..efc0efc 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/osc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/osc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: osc.h -* Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019) -* Revision: 54539 -* -* Description: Defines and prototypes for the system oscillator control. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: osc.h + * Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019) + * Revision: 54539 + * + * Description: Defines and prototypes for the system oscillator control. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,20 +55,19 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include #include "../inc/hw_aon_wuc.h" -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" #include "../inc/hw_ddi.h" #include "../inc/hw_ddi_0_osc.h" -#include "rom.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "ddi.h" #include "debug.h" +#include "rom.h" +#include +#include //***************************************************************************** // @@ -84,16 +83,16 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define OSCClockSourceSet NOROM_OSCClockSourceSet -#define OSCClockSourceGet NOROM_OSCClockSourceGet -#define OSCHF_GetStartupTime NOROM_OSCHF_GetStartupTime -#define OSCHF_TurnOnXosc NOROM_OSCHF_TurnOnXosc -#define OSCHF_AttemptToSwitchToXosc NOROM_OSCHF_AttemptToSwitchToXosc -#define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc -#define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude +#define OSCClockSourceSet NOROM_OSCClockSourceSet +#define OSCClockSourceGet NOROM_OSCClockSourceGet +#define OSCHF_GetStartupTime NOROM_OSCHF_GetStartupTime +#define OSCHF_TurnOnXosc NOROM_OSCHF_TurnOnXosc +#define OSCHF_AttemptToSwitchToXosc NOROM_OSCHF_AttemptToSwitchToXosc +#define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc +#define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude #define OSCHF_DebugGetExpectedAverageCrystalAmplitude NOROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude #define OSC_HPOSCRelativeFrequencyOffsetGet NOROM_OSC_HPOSCRelativeFrequencyOffsetGet -#define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray +#define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert NOROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert #endif @@ -102,33 +101,33 @@ extern "C" // Defines for the High Frequency XTAL Power mode // //***************************************************************************** -#define LOW_POWER_XOSC 1 -#define HIGH_POWER_XOSC 0 +#define LOW_POWER_XOSC 1 +#define HIGH_POWER_XOSC 0 //***************************************************************************** // // Defines for the High Frequency XTAL Power mode // //***************************************************************************** -#define OSC_SRC_CLK_HF 0x00000001 -#define OSC_SRC_CLK_MF 0x00000002 -#define OSC_SRC_CLK_LF 0x00000004 +#define OSC_SRC_CLK_HF 0x00000001 +#define OSC_SRC_CLK_MF 0x00000002 +#define OSC_SRC_CLK_LF 0x00000004 -#define OSC_RCOSC_HF 0x00000000 -#define OSC_XOSC_HF 0x00000001 -#define OSC_RCOSC_LF 0x00000002 -#define OSC_XOSC_LF 0x00000003 +#define OSC_RCOSC_HF 0x00000000 +#define OSC_XOSC_HF 0x00000001 +#define OSC_RCOSC_LF 0x00000002 +#define OSC_XOSC_LF 0x00000003 -#define SCLK_HF_RCOSC_HF 0 -#define SCLK_HF_XOSC_HF 1 +#define SCLK_HF_RCOSC_HF 0 +#define SCLK_HF_XOSC_HF 1 -#define SCLK_MF_RCOSC_HF 0 -#define SCLK_MF_XOSC_HF 1 +#define SCLK_MF_RCOSC_HF 0 +#define SCLK_MF_XOSC_HF 1 -#define SCLK_LF_FROM_RCOSC_HF 0 -#define SCLK_LF_FROM_XOSC_HF 1 -#define SCLK_LF_FROM_RCOSC_LF 2 -#define SCLK_LF_FROM_XOSC_LF 3 +#define SCLK_LF_FROM_RCOSC_HF 0 +#define SCLK_LF_FROM_XOSC_HF 1 +#define SCLK_LF_FROM_RCOSC_LF 2 +#define SCLK_LF_FROM_XOSC_LF 3 //***************************************************************************** // @@ -175,11 +174,11 @@ OSCXHfPowerModeSet(uint32_t ui32Mode) // //***************************************************************************** __STATIC_INLINE void -OSCClockLossEventEnable( void ) +OSCClockLossEventEnable(void) { - DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, - DDI_0_OSC_CTL0_CLK_LOSS_EN_M, - DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 1 ); + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_CLK_LOSS_EN_M, + DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 1); } //***************************************************************************** @@ -198,11 +197,11 @@ OSCClockLossEventEnable( void ) // //***************************************************************************** __STATIC_INLINE void -OSCClockLossEventDisable( void ) +OSCClockLossEventDisable(void) { - DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, - DDI_0_OSC_CTL0_CLK_LOSS_EN_M, - DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 0 ); + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_CLK_LOSS_EN_M, + DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 0); } //***************************************************************************** @@ -289,8 +288,9 @@ OSCHfSourceReady(void) // Return the readiness of the HF clock source return (DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M, - DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S)) ? - true : false; + DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S)) + ? true + : false; } //***************************************************************************** @@ -331,7 +331,7 @@ OSCHfSourceSwitch(void) //! \return Time margin to use in microseconds. // //***************************************************************************** -extern uint32_t OSCHF_GetStartupTime( uint32_t timeUntilWakeupInMs ); +extern uint32_t OSCHF_GetStartupTime(uint32_t timeUntilWakeupInMs); //***************************************************************************** // @@ -343,7 +343,7 @@ extern uint32_t OSCHF_GetStartupTime( uint32_t timeUntilWakeupInMs ); //! \return None // //***************************************************************************** -extern void OSCHF_TurnOnXosc( void ); +extern void OSCHF_TurnOnXosc(void); //***************************************************************************** // @@ -358,7 +358,7 @@ extern void OSCHF_TurnOnXosc( void ); //! - \c false : Switching has not occurred. // //***************************************************************************** -extern bool OSCHF_AttemptToSwitchToXosc( void ); +extern bool OSCHF_AttemptToSwitchToXosc(void); //***************************************************************************** // @@ -370,7 +370,7 @@ extern bool OSCHF_AttemptToSwitchToXosc( void ); //! \return None // //***************************************************************************** -extern void OSCHF_SwitchToRcOscTurnOffXosc( void ); +extern void OSCHF_SwitchToRcOscTurnOffXosc(void); //***************************************************************************** // @@ -390,7 +390,7 @@ extern void OSCHF_SwitchToRcOscTurnOffXosc( void ); //! \sa OSCHF_DebugGetExpectedAverageCrystalAmplitude() // //***************************************************************************** -extern uint32_t OSCHF_DebugGetCrystalAmplitude( void ); +extern uint32_t OSCHF_DebugGetCrystalAmplitude(void); //***************************************************************************** // @@ -407,7 +407,7 @@ extern uint32_t OSCHF_DebugGetCrystalAmplitude( void ); //! \sa OSCHF_DebugGetCrystalAmplitude() // //***************************************************************************** -extern uint32_t OSCHF_DebugGetExpectedAverageCrystalAmplitude( void ); +extern uint32_t OSCHF_DebugGetExpectedAverageCrystalAmplitude(void); //***************************************************************************** // @@ -438,7 +438,7 @@ extern uint32_t OSCHF_DebugGetExpectedAverageCrystalAmplitude( void ); //! \sa OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert(), AONBatMonTemperatureGetDegC() // //***************************************************************************** -extern int32_t OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC ); +extern int32_t OSC_HPOSCRelativeFrequencyOffsetGet(int32_t tempDegC); //***************************************************************************** // @@ -456,7 +456,7 @@ extern int32_t OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC ); //! \return None // //***************************************************************************** -extern void OSC_AdjustXoscHfCapArray( int32_t capArrDelta ); +extern void OSC_AdjustXoscHfCapArray(int32_t capArrDelta); //***************************************************************************** // @@ -486,7 +486,7 @@ extern void OSC_AdjustXoscHfCapArray( int32_t capArrDelta ); //! \sa OSC_HPOSCRelativeFrequencyOffsetGet() // //***************************************************************************** -extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffset ); +extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert(int32_t HPOSC_RelFreqOffset); //***************************************************************************** // @@ -497,47 +497,47 @@ extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HP #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_OSCClockSourceSet -#undef OSCClockSourceSet -#define OSCClockSourceSet ROM_OSCClockSourceSet +#undef OSCClockSourceSet +#define OSCClockSourceSet ROM_OSCClockSourceSet #endif #ifdef ROM_OSCClockSourceGet -#undef OSCClockSourceGet -#define OSCClockSourceGet ROM_OSCClockSourceGet +#undef OSCClockSourceGet +#define OSCClockSourceGet ROM_OSCClockSourceGet #endif #ifdef ROM_OSCHF_GetStartupTime -#undef OSCHF_GetStartupTime -#define OSCHF_GetStartupTime ROM_OSCHF_GetStartupTime +#undef OSCHF_GetStartupTime +#define OSCHF_GetStartupTime ROM_OSCHF_GetStartupTime #endif #ifdef ROM_OSCHF_TurnOnXosc -#undef OSCHF_TurnOnXosc -#define OSCHF_TurnOnXosc ROM_OSCHF_TurnOnXosc +#undef OSCHF_TurnOnXosc +#define OSCHF_TurnOnXosc ROM_OSCHF_TurnOnXosc #endif #ifdef ROM_OSCHF_AttemptToSwitchToXosc -#undef OSCHF_AttemptToSwitchToXosc -#define OSCHF_AttemptToSwitchToXosc ROM_OSCHF_AttemptToSwitchToXosc +#undef OSCHF_AttemptToSwitchToXosc +#define OSCHF_AttemptToSwitchToXosc ROM_OSCHF_AttemptToSwitchToXosc #endif #ifdef ROM_OSCHF_SwitchToRcOscTurnOffXosc -#undef OSCHF_SwitchToRcOscTurnOffXosc -#define OSCHF_SwitchToRcOscTurnOffXosc ROM_OSCHF_SwitchToRcOscTurnOffXosc +#undef OSCHF_SwitchToRcOscTurnOffXosc +#define OSCHF_SwitchToRcOscTurnOffXosc ROM_OSCHF_SwitchToRcOscTurnOffXosc #endif #ifdef ROM_OSCHF_DebugGetCrystalAmplitude -#undef OSCHF_DebugGetCrystalAmplitude -#define OSCHF_DebugGetCrystalAmplitude ROM_OSCHF_DebugGetCrystalAmplitude +#undef OSCHF_DebugGetCrystalAmplitude +#define OSCHF_DebugGetCrystalAmplitude ROM_OSCHF_DebugGetCrystalAmplitude #endif #ifdef ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude -#undef OSCHF_DebugGetExpectedAverageCrystalAmplitude +#undef OSCHF_DebugGetExpectedAverageCrystalAmplitude #define OSCHF_DebugGetExpectedAverageCrystalAmplitude ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude #endif #ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetGet -#undef OSC_HPOSCRelativeFrequencyOffsetGet +#undef OSC_HPOSCRelativeFrequencyOffsetGet #define OSC_HPOSCRelativeFrequencyOffsetGet ROM_OSC_HPOSCRelativeFrequencyOffsetGet #endif #ifdef ROM_OSC_AdjustXoscHfCapArray -#undef OSC_AdjustXoscHfCapArray -#define OSC_AdjustXoscHfCapArray ROM_OSC_AdjustXoscHfCapArray +#undef OSC_AdjustXoscHfCapArray +#define OSC_AdjustXoscHfCapArray ROM_OSC_AdjustXoscHfCapArray #endif #ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert -#undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert +#undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/prcm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/prcm.h index becf1cd..3df189d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/prcm.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/prcm.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: prcm.h -* Revised: 2018-10-23 10:19:14 +0200 (Tue, 23 Oct 2018) -* Revision: 52979 -* -* Description: Defines and prototypes for the PRCM -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: prcm.h + * Revised: 2018-10-23 10:19:14 +0200 (Tue, 23 Oct 2018) + * Revision: 52979 + * + * Description: Defines and prototypes for the PRCM + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,22 +55,20 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_nvic.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_prcm.h" -#include "../inc/hw_nvic.h" -#include "../inc/hw_aon_rtc.h" -#include "interrupt.h" -#include "debug.h" -#include "cpu.h" - //***************************************************************************** // @@ -86,22 +84,22 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet -#define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet -#define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet +#define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet +#define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet +#define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet #define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride -#define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource -#define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource -#define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn -#define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff -#define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable -#define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable -#define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable -#define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable -#define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable -#define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable -#define PRCMPowerDomainStatus NOROM_PRCMPowerDomainStatus -#define PRCMDeepSleep NOROM_PRCMDeepSleep +#define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource +#define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource +#define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn +#define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff +#define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable +#define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable +#define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable +#define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable +#define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable +#define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable +#define PRCMPowerDomainStatus NOROM_PRCMPowerDomainStatus +#define PRCMDeepSleep NOROM_PRCMDeepSleep #endif //***************************************************************************** @@ -109,24 +107,24 @@ extern "C" // Defines for the different System CPU power modes. // //***************************************************************************** -#define PRCM_RUN_MODE 0x00000001 -#define PRCM_SLEEP_MODE 0x00000002 -#define PRCM_DEEP_SLEEP_MODE 0x00000004 +#define PRCM_RUN_MODE 0x00000001 +#define PRCM_SLEEP_MODE 0x00000002 +#define PRCM_DEEP_SLEEP_MODE 0x00000004 //***************************************************************************** // // Defines used for setting the clock division factors // //***************************************************************************** -#define PRCM_CLOCK_DIV_1 PRCM_GPTCLKDIV_RATIO_DIV1 -#define PRCM_CLOCK_DIV_2 PRCM_GPTCLKDIV_RATIO_DIV2 -#define PRCM_CLOCK_DIV_4 PRCM_GPTCLKDIV_RATIO_DIV4 -#define PRCM_CLOCK_DIV_8 PRCM_GPTCLKDIV_RATIO_DIV8 -#define PRCM_CLOCK_DIV_16 PRCM_GPTCLKDIV_RATIO_DIV16 -#define PRCM_CLOCK_DIV_32 PRCM_GPTCLKDIV_RATIO_DIV32 -#define PRCM_CLOCK_DIV_64 PRCM_GPTCLKDIV_RATIO_DIV64 -#define PRCM_CLOCK_DIV_128 PRCM_GPTCLKDIV_RATIO_DIV128 -#define PRCM_CLOCK_DIV_256 PRCM_GPTCLKDIV_RATIO_DIV256 +#define PRCM_CLOCK_DIV_1 PRCM_GPTCLKDIV_RATIO_DIV1 +#define PRCM_CLOCK_DIV_2 PRCM_GPTCLKDIV_RATIO_DIV2 +#define PRCM_CLOCK_DIV_4 PRCM_GPTCLKDIV_RATIO_DIV4 +#define PRCM_CLOCK_DIV_8 PRCM_GPTCLKDIV_RATIO_DIV8 +#define PRCM_CLOCK_DIV_16 PRCM_GPTCLKDIV_RATIO_DIV16 +#define PRCM_CLOCK_DIV_32 PRCM_GPTCLKDIV_RATIO_DIV32 +#define PRCM_CLOCK_DIV_64 PRCM_GPTCLKDIV_RATIO_DIV64 +#define PRCM_CLOCK_DIV_128 PRCM_GPTCLKDIV_RATIO_DIV128 +#define PRCM_CLOCK_DIV_256 PRCM_GPTCLKDIV_RATIO_DIV256 //***************************************************************************** // @@ -134,28 +132,28 @@ extern "C" // domain // //***************************************************************************** -#define PRCM_DOMAIN_RFCORE 0x00000001 // RF Core domain ID for +#define PRCM_DOMAIN_RFCORE 0x00000001 // RF Core domain ID for // clock/power control. -#define PRCM_DOMAIN_SERIAL 0x00000002 // Serial domain ID for +#define PRCM_DOMAIN_SERIAL 0x00000002 // Serial domain ID for // clock/power control. -#define PRCM_DOMAIN_PERIPH 0x00000004 // Peripheral domain ID for +#define PRCM_DOMAIN_PERIPH 0x00000004 // Peripheral domain ID for // clock/power control. -#define PRCM_DOMAIN_SYSBUS 0x00000008 // Bus domain ID for clock/power +#define PRCM_DOMAIN_SYSBUS 0x00000008 // Bus domain ID for clock/power // control. -#define PRCM_DOMAIN_VIMS 0x00000010 // VIMS domain ID for clock/power +#define PRCM_DOMAIN_VIMS 0x00000010 // VIMS domain ID for clock/power // control. -#define PRCM_DOMAIN_CPU 0x00000020 // CPU domain ID for clock/power +#define PRCM_DOMAIN_CPU 0x00000020 // CPU domain ID for clock/power // control. -#define PRCM_DOMAIN_TIMER 0x00000040 // GPT domain ID for clock +#define PRCM_DOMAIN_TIMER 0x00000040 // GPT domain ID for clock // control. -#define PRCM_DOMAIN_CLKCTRL 0x00000080 // Clock Control domain ID for +#define PRCM_DOMAIN_CLKCTRL 0x00000080 // Clock Control domain ID for // clock/power control. -#define PRCM_DOMAIN_MCU 0x00000100 // Reset control for entire MCU +#define PRCM_DOMAIN_MCU 0x00000100 // Reset control for entire MCU // domain. -#define PRCM_DOMAIN_POWER_OFF 0x00000002 // The domain is powered off -#define PRCM_DOMAIN_POWER_ON 0x00000001 // The domain is powered on -#define PRCM_DOMAIN_POWER_DOWN_READY \ - 0x00000000 // The domain is ready to be +#define PRCM_DOMAIN_POWER_OFF 0x00000002 // The domain is powered off +#define PRCM_DOMAIN_POWER_ON 0x00000001 // The domain is powered on +#define PRCM_DOMAIN_POWER_DOWN_READY \ + 0x00000000 // The domain is ready to be // powered down. //***************************************************************************** @@ -163,21 +161,21 @@ extern "C" // Defines for setting up the audio interface in the I2S module. // //***************************************************************************** -#define PRCM_WCLK_NEG_EDGE 0x00000008 -#define PRCM_WCLK_POS_EDGE 0x00000000 -#define PRCM_WCLK_SINGLE_PHASE 0x00000000 -#define PRCM_WCLK_DUAL_PHASE 0x00000002 -#define PRCM_WCLK_USER_DEF 0x00000004 -#define PRCM_I2S_WCLK_NEG_EDGE 0 -#define PRCM_I2S_WCLK_POS_EDGE 1 -#define PRCM_I2S_WCLK_SINGLE_PHASE 0 -#define PRCM_I2S_WCLK_DUAL_PHASE 1 -#define PRCM_I2S_WCLK_USER_DEF 2 +#define PRCM_WCLK_NEG_EDGE 0x00000008 +#define PRCM_WCLK_POS_EDGE 0x00000000 +#define PRCM_WCLK_SINGLE_PHASE 0x00000000 +#define PRCM_WCLK_DUAL_PHASE 0x00000002 +#define PRCM_WCLK_USER_DEF 0x00000004 +#define PRCM_I2S_WCLK_NEG_EDGE 0 +#define PRCM_I2S_WCLK_POS_EDGE 1 +#define PRCM_I2S_WCLK_SINGLE_PHASE 0 +#define PRCM_I2S_WCLK_DUAL_PHASE 1 +#define PRCM_I2S_WCLK_USER_DEF 2 -#define I2S_SAMPLE_RATE_16K 0x00000001 -#define I2S_SAMPLE_RATE_24K 0x00000002 -#define I2S_SAMPLE_RATE_32K 0x00000004 -#define I2S_SAMPLE_RATE_48K 0x00000008 +#define I2S_SAMPLE_RATE_16K 0x00000001 +#define I2S_SAMPLE_RATE_24K 0x00000002 +#define I2S_SAMPLE_RATE_32K 0x00000004 +#define I2S_SAMPLE_RATE_48K 0x00000008 //***************************************************************************** // @@ -187,19 +185,19 @@ extern "C" // bits[4:0] Defines the bit position within the register pointet on in [11:8] // //***************************************************************************** -#define PRCM_PERIPH_TIMER0 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S )) // Peripheral ID for GPT module 0 -#define PRCM_PERIPH_TIMER1 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 1 )) // Peripheral ID for GPT module 1 -#define PRCM_PERIPH_TIMER2 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 2 )) // Peripheral ID for GPT module 2 -#define PRCM_PERIPH_TIMER3 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 3 )) // Peripheral ID for GPT module 3 -#define PRCM_PERIPH_SSI0 ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S )) // Peripheral ID for SSI module 0 -#define PRCM_PERIPH_SSI1 ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S + 1 )) // Peripheral ID for SSI module 1 -#define PRCM_PERIPH_UART0 ( 0x00000200 | ( PRCM_UARTCLKGR_CLK_EN_S )) // Peripheral ID for UART module 0 -#define PRCM_PERIPH_I2C0 ( 0x00000300 | ( PRCM_I2CCLKGR_CLK_EN_S )) // Peripheral ID for I2C module 0 -#define PRCM_PERIPH_CRYPTO ( 0x00000400 | ( PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S )) // Peripheral ID for CRYPTO module -#define PRCM_PERIPH_TRNG ( 0x00000400 | ( PRCM_SECDMACLKGR_TRNG_CLK_EN_S )) // Peripheral ID for TRNG module -#define PRCM_PERIPH_UDMA ( 0x00000400 | ( PRCM_SECDMACLKGR_DMA_CLK_EN_S )) // Peripheral ID for UDMA module -#define PRCM_PERIPH_GPIO ( 0x00000500 | ( PRCM_GPIOCLKGR_CLK_EN_S )) // Peripheral ID for GPIO module -#define PRCM_PERIPH_I2S ( 0x00000600 | ( PRCM_I2SCLKGR_CLK_EN_S )) // Peripheral ID for I2S module +#define PRCM_PERIPH_TIMER0 (0x00000000 | (PRCM_GPTCLKGR_CLK_EN_S)) // Peripheral ID for GPT module 0 +#define PRCM_PERIPH_TIMER1 (0x00000000 | (PRCM_GPTCLKGR_CLK_EN_S + 1)) // Peripheral ID for GPT module 1 +#define PRCM_PERIPH_TIMER2 (0x00000000 | (PRCM_GPTCLKGR_CLK_EN_S + 2)) // Peripheral ID for GPT module 2 +#define PRCM_PERIPH_TIMER3 (0x00000000 | (PRCM_GPTCLKGR_CLK_EN_S + 3)) // Peripheral ID for GPT module 3 +#define PRCM_PERIPH_SSI0 (0x00000100 | (PRCM_SSICLKGR_CLK_EN_S)) // Peripheral ID for SSI module 0 +#define PRCM_PERIPH_SSI1 (0x00000100 | (PRCM_SSICLKGR_CLK_EN_S + 1)) // Peripheral ID for SSI module 1 +#define PRCM_PERIPH_UART0 (0x00000200 | (PRCM_UARTCLKGR_CLK_EN_S)) // Peripheral ID for UART module 0 +#define PRCM_PERIPH_I2C0 (0x00000300 | (PRCM_I2CCLKGR_CLK_EN_S)) // Peripheral ID for I2C module 0 +#define PRCM_PERIPH_CRYPTO (0x00000400 | (PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S)) // Peripheral ID for CRYPTO module +#define PRCM_PERIPH_TRNG (0x00000400 | (PRCM_SECDMACLKGR_TRNG_CLK_EN_S)) // Peripheral ID for TRNG module +#define PRCM_PERIPH_UDMA (0x00000400 | (PRCM_SECDMACLKGR_DMA_CLK_EN_S)) // Peripheral ID for UDMA module +#define PRCM_PERIPH_GPIO (0x00000500 | (PRCM_GPIOCLKGR_CLK_EN_S)) // Peripheral ID for GPIO module +#define PRCM_PERIPH_I2S (0x00000600 | (PRCM_I2SCLKGR_CLK_EN_S)) // Peripheral ID for I2S module //***************************************************************************** // @@ -224,18 +222,18 @@ extern "C" static bool PRCMPeripheralValid(uint32_t ui32Peripheral) { - return ((ui32Peripheral == PRCM_PERIPH_TIMER0) || - (ui32Peripheral == PRCM_PERIPH_TIMER1) || - (ui32Peripheral == PRCM_PERIPH_TIMER2) || - (ui32Peripheral == PRCM_PERIPH_TIMER3) || - (ui32Peripheral == PRCM_PERIPH_SSI0) || - (ui32Peripheral == PRCM_PERIPH_SSI1) || - (ui32Peripheral == PRCM_PERIPH_UART0) || - (ui32Peripheral == PRCM_PERIPH_I2C0) || - (ui32Peripheral == PRCM_PERIPH_CRYPTO) || - (ui32Peripheral == PRCM_PERIPH_TRNG) || - (ui32Peripheral == PRCM_PERIPH_UDMA) || - (ui32Peripheral == PRCM_PERIPH_GPIO) || + return ((ui32Peripheral == PRCM_PERIPH_TIMER0) || + (ui32Peripheral == PRCM_PERIPH_TIMER1) || + (ui32Peripheral == PRCM_PERIPH_TIMER2) || + (ui32Peripheral == PRCM_PERIPH_TIMER3) || + (ui32Peripheral == PRCM_PERIPH_SSI0) || + (ui32Peripheral == PRCM_PERIPH_SSI1) || + (ui32Peripheral == PRCM_PERIPH_UART0) || + (ui32Peripheral == PRCM_PERIPH_I2C0) || + (ui32Peripheral == PRCM_PERIPH_CRYPTO) || + (ui32Peripheral == PRCM_PERIPH_TRNG) || + (ui32Peripheral == PRCM_PERIPH_UDMA) || + (ui32Peripheral == PRCM_PERIPH_GPIO) || (ui32Peripheral == PRCM_PERIPH_I2S)); } #endif @@ -397,11 +395,11 @@ PRCMMcuUldoConfigure(uint32_t ui32Enable) // //***************************************************************************** __STATIC_INLINE void -PRCMGPTimerClockDivisionSet( uint32_t clkDiv ) +PRCMGPTimerClockDivisionSet(uint32_t clkDiv) { - ASSERT( clkDiv <= PRCM_GPTCLKDIV_RATIO_DIV256 ); + ASSERT(clkDiv <= PRCM_GPTCLKDIV_RATIO_DIV256); - HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV ) = clkDiv; + HWREG(PRCM_BASE + PRCM_O_GPTCLKDIV) = clkDiv; } //***************************************************************************** @@ -425,12 +423,11 @@ PRCMGPTimerClockDivisionSet( uint32_t clkDiv ) // //***************************************************************************** __STATIC_INLINE uint32_t -PRCMGPTimerClockDivisionGet( void ) +PRCMGPTimerClockDivisionGet(void) { - return ( HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV )); + return (HWREG(PRCM_BASE + PRCM_O_GPTCLKDIV)); } - //***************************************************************************** // //! \brief Enable the audio clock generation. @@ -530,7 +527,7 @@ extern void PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, //***************************************************************************** #ifndef DEPRECATED extern void PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, - uint32_t ui32BitDiv, uint32_t ui32WordDiv); + uint32_t ui32BitDiv, uint32_t ui32WordDiv); #endif //***************************************************************************** @@ -554,12 +551,11 @@ extern void PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui3 //! \return None //! //***************************************************************************** -extern void PRCMAudioClockConfigOverride -(uint8_t ui8SamplingEdge, - uint8_t ui8WCLKPhase, - uint32_t ui32MstDiv, - uint32_t ui32BitDiv, - uint32_t ui32WordDiv); +extern void PRCMAudioClockConfigOverride(uint8_t ui8SamplingEdge, + uint8_t ui8WCLKPhase, + uint32_t ui32MstDiv, + uint32_t ui32BitDiv, + uint32_t ui32WordDiv); //***************************************************************************** // @@ -636,8 +632,7 @@ __STATIC_INLINE bool PRCMLoadGet(void) { // Return the load status. - return ((HWREG(PRCM_BASE + PRCM_O_CLKLOADCTL) & PRCM_CLKLOADCTL_LOAD_DONE) ? - true : false); + return ((HWREG(PRCM_BASE + PRCM_O_CLKLOADCTL) & PRCM_CLKLOADCTL_LOAD_DONE) ? true : false); } //***************************************************************************** @@ -1088,10 +1083,11 @@ PRCMRfReady(void) { // Return the ready status of the RF Core. return ((HWREG(PRCM_BASE + PRCM_O_PDSTAT1RFC) & - PRCM_PDSTAT1RFC_ON) ? true : false); + PRCM_PDSTAT1RFC_ON) + ? true + : false); } - //***************************************************************************** // //! \brief Put the processor into sleep mode. @@ -1139,9 +1135,9 @@ extern void PRCMDeepSleep(void); // //***************************************************************************** __STATIC_INLINE void -PRCMCacheRetentionEnable( void ) +PRCMCacheRetentionEnable(void) { - HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) |= PRCM_RAMRETEN_VIMS_M; + HWREG(PRCM_BASE + PRCM_O_RAMRETEN) |= PRCM_RAMRETEN_VIMS_M; } //***************************************************************************** @@ -1154,12 +1150,11 @@ PRCMCacheRetentionEnable( void ) // //***************************************************************************** __STATIC_INLINE void -PRCMCacheRetentionDisable( void ) +PRCMCacheRetentionDisable(void) { - HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) &= ~PRCM_RAMRETEN_VIMS_M; + HWREG(PRCM_BASE + PRCM_O_RAMRETEN) &= ~PRCM_RAMRETEN_VIMS_M; } - //***************************************************************************** // // Support for DriverLib in ROM: @@ -1169,68 +1164,68 @@ PRCMCacheRetentionDisable( void ) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_PRCMInfClockConfigureSet -#undef PRCMInfClockConfigureSet -#define PRCMInfClockConfigureSet ROM_PRCMInfClockConfigureSet +#undef PRCMInfClockConfigureSet +#define PRCMInfClockConfigureSet ROM_PRCMInfClockConfigureSet #endif #ifdef ROM_PRCMInfClockConfigureGet -#undef PRCMInfClockConfigureGet -#define PRCMInfClockConfigureGet ROM_PRCMInfClockConfigureGet +#undef PRCMInfClockConfigureGet +#define PRCMInfClockConfigureGet ROM_PRCMInfClockConfigureGet #endif #ifdef ROM_PRCMAudioClockConfigSet -#undef PRCMAudioClockConfigSet -#define PRCMAudioClockConfigSet ROM_PRCMAudioClockConfigSet +#undef PRCMAudioClockConfigSet +#define PRCMAudioClockConfigSet ROM_PRCMAudioClockConfigSet #endif #ifdef ROM_PRCMAudioClockConfigSetOverride -#undef PRCMAudioClockConfigSetOverride +#undef PRCMAudioClockConfigSetOverride #define PRCMAudioClockConfigSetOverride ROM_PRCMAudioClockConfigSetOverride #endif #ifdef ROM_PRCMAudioClockInternalSource -#undef PRCMAudioClockInternalSource -#define PRCMAudioClockInternalSource ROM_PRCMAudioClockInternalSource +#undef PRCMAudioClockInternalSource +#define PRCMAudioClockInternalSource ROM_PRCMAudioClockInternalSource #endif #ifdef ROM_PRCMAudioClockExternalSource -#undef PRCMAudioClockExternalSource -#define PRCMAudioClockExternalSource ROM_PRCMAudioClockExternalSource +#undef PRCMAudioClockExternalSource +#define PRCMAudioClockExternalSource ROM_PRCMAudioClockExternalSource #endif #ifdef ROM_PRCMPowerDomainOn -#undef PRCMPowerDomainOn -#define PRCMPowerDomainOn ROM_PRCMPowerDomainOn +#undef PRCMPowerDomainOn +#define PRCMPowerDomainOn ROM_PRCMPowerDomainOn #endif #ifdef ROM_PRCMPowerDomainOff -#undef PRCMPowerDomainOff -#define PRCMPowerDomainOff ROM_PRCMPowerDomainOff +#undef PRCMPowerDomainOff +#define PRCMPowerDomainOff ROM_PRCMPowerDomainOff #endif #ifdef ROM_PRCMPeripheralRunEnable -#undef PRCMPeripheralRunEnable -#define PRCMPeripheralRunEnable ROM_PRCMPeripheralRunEnable +#undef PRCMPeripheralRunEnable +#define PRCMPeripheralRunEnable ROM_PRCMPeripheralRunEnable #endif #ifdef ROM_PRCMPeripheralRunDisable -#undef PRCMPeripheralRunDisable -#define PRCMPeripheralRunDisable ROM_PRCMPeripheralRunDisable +#undef PRCMPeripheralRunDisable +#define PRCMPeripheralRunDisable ROM_PRCMPeripheralRunDisable #endif #ifdef ROM_PRCMPeripheralSleepEnable -#undef PRCMPeripheralSleepEnable -#define PRCMPeripheralSleepEnable ROM_PRCMPeripheralSleepEnable +#undef PRCMPeripheralSleepEnable +#define PRCMPeripheralSleepEnable ROM_PRCMPeripheralSleepEnable #endif #ifdef ROM_PRCMPeripheralSleepDisable -#undef PRCMPeripheralSleepDisable -#define PRCMPeripheralSleepDisable ROM_PRCMPeripheralSleepDisable +#undef PRCMPeripheralSleepDisable +#define PRCMPeripheralSleepDisable ROM_PRCMPeripheralSleepDisable #endif #ifdef ROM_PRCMPeripheralDeepSleepEnable -#undef PRCMPeripheralDeepSleepEnable -#define PRCMPeripheralDeepSleepEnable ROM_PRCMPeripheralDeepSleepEnable +#undef PRCMPeripheralDeepSleepEnable +#define PRCMPeripheralDeepSleepEnable ROM_PRCMPeripheralDeepSleepEnable #endif #ifdef ROM_PRCMPeripheralDeepSleepDisable -#undef PRCMPeripheralDeepSleepDisable -#define PRCMPeripheralDeepSleepDisable ROM_PRCMPeripheralDeepSleepDisable +#undef PRCMPeripheralDeepSleepDisable +#define PRCMPeripheralDeepSleepDisable ROM_PRCMPeripheralDeepSleepDisable #endif #ifdef ROM_PRCMPowerDomainStatus -#undef PRCMPowerDomainStatus -#define PRCMPowerDomainStatus ROM_PRCMPowerDomainStatus +#undef PRCMPowerDomainStatus +#define PRCMPowerDomainStatus ROM_PRCMPowerDomainStatus #endif #ifdef ROM_PRCMDeepSleep -#undef PRCMDeepSleep -#define PRCMDeepSleep ROM_PRCMDeepSleep +#undef PRCMDeepSleep +#define PRCMDeepSleep ROM_PRCMDeepSleep #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/pwr_ctrl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/pwr_ctrl.h index e0ac7ce..ed94acb 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/pwr_ctrl.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/pwr_ctrl.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: pwr_ctrl.h -* Revised: 2017-11-02 15:41:14 +0100 (Thu, 02 Nov 2017) -* Revision: 50165 -* -* Description: Defines and prototypes for the System Power Control. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: pwr_ctrl.h + * Revised: 2017-11-02 15:41:14 +0100 (Thu, 02 Nov 2017) + * Revision: 50165 + * + * Description: Defines and prototypes for the System Power Control. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,26 +55,25 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_aon_wuc.h" -#include "../inc/hw_aon_sysctl.h" -#include "../inc/hw_aon_rtc.h" #include "../inc/hw_adi_2_refsys.h" +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_aon_sysctl.h" +#include "../inc/hw_aon_wuc.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "adi.h" +#include "aon_ioc.h" +#include "cpu.h" #include "debug.h" #include "interrupt.h" #include "osc.h" -#include "cpu.h" #include "prcm.h" -#include "aon_ioc.h" -#include "adi.h" +#include +#include //***************************************************************************** // @@ -90,7 +89,7 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define PowerCtrlSourceSet NOROM_PowerCtrlSourceSet +#define PowerCtrlSourceSet NOROM_PowerCtrlSourceSet #endif //***************************************************************************** @@ -98,37 +97,37 @@ extern "C" // Defines for the system power states // //***************************************************************************** -#define PWRCTRL_ACTIVE 0x00000001 -#define PWRCTRL_STANDBY 0x00000002 -#define PWRCTRL_POWER_DOWN 0x00000004 -#define PWRCTRL_SHUTDOWN 0x00000008 +#define PWRCTRL_ACTIVE 0x00000001 +#define PWRCTRL_STANDBY 0x00000002 +#define PWRCTRL_POWER_DOWN 0x00000004 +#define PWRCTRL_SHUTDOWN 0x00000008 //***************************************************************************** // // Defines for the power configuration in the AON System Control 1.2 V // //***************************************************************************** -#define PWRCTRL_IOSEG3_ENABLE 0x00000800 -#define PWRCTRL_IOSEG2_ENABLE 0x00000400 -#define PWRCTRL_IOSEG3_DISABLE 0x00000200 -#define PWRCTRL_IOSEG2_DISABLE 0x00000100 -#define PWRCTRL_PWRSRC_DCDC 0x00000001 -#define PWRCTRL_PWRSRC_GLDO 0x00000000 -#define PWRCTRL_PWRSRC_ULDO 0x00000002 +#define PWRCTRL_IOSEG3_ENABLE 0x00000800 +#define PWRCTRL_IOSEG2_ENABLE 0x00000400 +#define PWRCTRL_IOSEG3_DISABLE 0x00000200 +#define PWRCTRL_IOSEG2_DISABLE 0x00000100 +#define PWRCTRL_PWRSRC_DCDC 0x00000001 +#define PWRCTRL_PWRSRC_GLDO 0x00000000 +#define PWRCTRL_PWRSRC_ULDO 0x00000002 //***************************************************************************** // // The following are defines for the various reset source for the device. // //***************************************************************************** -#define PWRCTRL_RST_POWER_ON 0x00000000 // Reset by power on -#define PWRCTRL_RST_PIN 0x00000001 // Pin reset -#define PWRCTRL_RST_VDDS_BOD 0x00000002 // VDDS Brown Out Detect -#define PWRCTRL_RST_VDD_BOD 0x00000003 // VDD Brown Out Detect -#define PWRCTRL_RST_VDDR_BOD 0x00000004 // VDDR Brown Out Detect -#define PWRCTRL_RST_CLK_LOSS 0x00000005 // Clock loss Reset -#define PWRCTRL_RST_SW_PIN 0x00000006 // SYSRESET or pin reset -#define PWRCTRL_RST_WARM 0x00000007 // Reset via PRCM warm reset request +#define PWRCTRL_RST_POWER_ON 0x00000000 // Reset by power on +#define PWRCTRL_RST_PIN 0x00000001 // Pin reset +#define PWRCTRL_RST_VDDS_BOD 0x00000002 // VDDS Brown Out Detect +#define PWRCTRL_RST_VDD_BOD 0x00000003 // VDD Brown Out Detect +#define PWRCTRL_RST_VDDR_BOD 0x00000004 // VDDR Brown Out Detect +#define PWRCTRL_RST_CLK_LOSS 0x00000005 // Clock loss Reset +#define PWRCTRL_RST_SW_PIN 0x00000006 // SYSRESET or pin reset +#define PWRCTRL_RST_WARM 0x00000007 // Reset via PRCM warm reset request //***************************************************************************** // @@ -223,9 +222,9 @@ __STATIC_INLINE uint32_t PowerCtrlResetSourceGet(void) { // Get the reset source. - return (( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) & - AON_SYSCTL_RESETCTL_RESET_SRC_M ) >> - AON_SYSCTL_RESETCTL_RESET_SRC_S ) ; + return ((HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL) & + AON_SYSCTL_RESETCTL_RESET_SRC_M) >> + AON_SYSCTL_RESETCTL_RESET_SRC_S); } //***************************************************************************** @@ -272,8 +271,8 @@ PowerCtrlPadSleepDisable(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_PowerCtrlSourceSet -#undef PowerCtrlSourceSet -#define PowerCtrlSourceSet ROM_PowerCtrlSourceSet +#undef PowerCtrlSourceSet +#define PowerCtrlSourceSet ROM_PowerCtrlSourceSet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_ble_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_ble_cmd.h index 0a61048..7ef71b1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_ble_cmd.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_ble_cmd.h @@ -1,56 +1,56 @@ /****************************************************************************** -* Filename: rf_ble_cmd.h -* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) -* Revision: 18052 -* -* Description: CC13x0 API for Bluetooth Low Energy commands -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_ble_cmd.h + * Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) + * Revision: 18052 + * + * Description: CC13x0 API for Bluetooth Low Energy commands + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __BLE_CMD_H #define __BLE_CMD_H #ifndef __RFC_STRUCT - #define __RFC_STRUCT +#define __RFC_STRUCT #endif #ifndef __RFC_STRUCT_ATTR - #if defined(__GNUC__) - #define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) - #elif defined(__TI_ARM__) - #define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) - #else - #define __RFC_STRUCT_ATTR - #endif +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__((aligned(4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__((__packed__, aligned(4))) +#else +#define __RFC_STRUCT_ATTR +#endif #endif //! \addtogroup rfc @@ -59,9 +59,9 @@ //! \addtogroup ble_cmd //! @{ -#include -#include "rf_mailbox.h" #include "rf_common_cmd.h" +#include "rf_mailbox.h" +#include typedef struct __RFC_STRUCT rfc_bleRadioOp_s rfc_bleRadioOp_t; typedef struct __RFC_STRUCT rfc_CMD_BLE_SLAVE_s rfc_CMD_BLE_SLAVE_t; @@ -97,518 +97,518 @@ typedef struct __RFC_STRUCT rfc_bleRxStatus_s rfc_bleRxStatus_t; //! @{ struct __RFC_STRUCT rfc_bleRadioOp_s { - uint16_t commandNo; //!< The command ID number - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - uint8_t* pParams; //!< Pointer to command specific parameter structure - uint8_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + uint8_t* pParams; //!< Pointer to command specific parameter structure + uint8_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_SLAVE //! @{ -#define CMD_BLE_SLAVE 0x1801 +#define CMD_BLE_SLAVE 0x1801 //! BLE Slave Command struct __RFC_STRUCT rfc_CMD_BLE_SLAVE_s { - uint16_t commandNo; //!< The command ID number 0x1801 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleSlavePar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleMasterSlaveOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleSlavePar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleMasterSlaveOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_MASTER //! @{ -#define CMD_BLE_MASTER 0x1802 +#define CMD_BLE_MASTER 0x1802 //! BLE Master Command struct __RFC_STRUCT rfc_CMD_BLE_MASTER_s { - uint16_t commandNo; //!< The command ID number 0x1802 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleMasterPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleMasterSlaveOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleMasterPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleMasterSlaveOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_ADV //! @{ -#define CMD_BLE_ADV 0x1803 +#define CMD_BLE_ADV 0x1803 //! BLE Connectable Undirected Advertiser Command struct __RFC_STRUCT rfc_CMD_BLE_ADV_s { - uint16_t commandNo; //!< The command ID number 0x1803 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1803 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_ADV_DIR //! @{ -#define CMD_BLE_ADV_DIR 0x1804 +#define CMD_BLE_ADV_DIR 0x1804 //! BLE Connectable Directed Advertiser Command struct __RFC_STRUCT rfc_CMD_BLE_ADV_DIR_s { - uint16_t commandNo; //!< The command ID number 0x1804 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1804 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_ADV_NC //! @{ -#define CMD_BLE_ADV_NC 0x1805 +#define CMD_BLE_ADV_NC 0x1805 //! BLE Non-Connectable Advertiser Command struct __RFC_STRUCT rfc_CMD_BLE_ADV_NC_s { - uint16_t commandNo; //!< The command ID number 0x1805 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1805 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_ADV_SCAN //! @{ -#define CMD_BLE_ADV_SCAN 0x1806 +#define CMD_BLE_ADV_SCAN 0x1806 //! BLE Scannable Undirected Advertiser Command struct __RFC_STRUCT rfc_CMD_BLE_ADV_SCAN_s { - uint16_t commandNo; //!< The command ID number 0x1806 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1806 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_SCANNER //! @{ -#define CMD_BLE_SCANNER 0x1807 +#define CMD_BLE_SCANNER 0x1807 //! BLE Scanner Command struct __RFC_STRUCT rfc_CMD_BLE_SCANNER_s { - uint16_t commandNo; //!< The command ID number 0x1807 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleScannerPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleScannerOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1807 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleScannerPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleScannerOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_INITIATOR //! @{ -#define CMD_BLE_INITIATOR 0x1808 +#define CMD_BLE_INITIATOR 0x1808 //! BLE Initiator Command struct __RFC_STRUCT rfc_CMD_BLE_INITIATOR_s { - uint16_t commandNo; //!< The command ID number 0x1808 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleInitiatorPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleInitiatorOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1808 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleInitiatorPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleInitiatorOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_GENERIC_RX //! @{ -#define CMD_BLE_GENERIC_RX 0x1809 +#define CMD_BLE_GENERIC_RX 0x1809 //! BLE Generic Receiver Command struct __RFC_STRUCT rfc_CMD_BLE_GENERIC_RX_s { - uint16_t commandNo; //!< The command ID number 0x1809 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleGenericRxPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleGenericRxOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1809 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleGenericRxPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleGenericRxOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_TX_TEST //! @{ -#define CMD_BLE_TX_TEST 0x180A +#define CMD_BLE_TX_TEST 0x180A //! BLE PHY Test Transmitter Command struct __RFC_STRUCT rfc_CMD_BLE_TX_TEST_s { - uint16_t commandNo; //!< The command ID number 0x180A - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleTxTestPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleTxTestOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x180A + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleTxTestPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleTxTestOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_ADV_PAYLOAD //! @{ -#define CMD_BLE_ADV_PAYLOAD 0x1001 +#define CMD_BLE_ADV_PAYLOAD 0x1001 //! BLE Update Advertising Payload Command struct __RFC_STRUCT rfc_CMD_BLE_ADV_PAYLOAD_s { - uint16_t commandNo; //!< The command ID number 0x1001 - uint8_t payloadType; //!< \brief 0: Advertising data
- //!< 1: Scan response data - uint8_t newLen; //!< Length of the new payload - uint8_t* pNewData; //!< Pointer to the buffer containing the new data - rfc_bleAdvPar_t* pParams; //!< Pointer to the parameter structure to update + uint16_t commandNo; //!< The command ID number 0x1001 + uint8_t payloadType; //!< \brief 0: Advertising data
+ //!< 1: Scan response data + uint8_t newLen; //!< Length of the new payload + uint8_t* pNewData; //!< Pointer to the buffer containing the new data + rfc_bleAdvPar_t* pParams; //!< Pointer to the parameter structure to update } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE5_RADIO_SETUP //! @{ -#define CMD_BLE5_RADIO_SETUP 0x1820 +#define CMD_BLE5_RADIO_SETUP 0x1820 //! Define only for compatibility with CC26XXR2F family. Command will result in error if sent. struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_s { - uint8_t dummy0; + uint8_t dummy0; } __RFC_STRUCT_ATTR; //! @} @@ -617,36 +617,36 @@ struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_s //! @{ struct __RFC_STRUCT rfc_bleMasterSlavePar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - dataQueue_t* pTxQ; //!< Pointer to transmit queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t lastRxSn: 1; //!< The SN bit of the header of the last packet received with CRC OK - uint8_t lastTxSn: 1; //!< The SN bit of the header of the last transmitted packet - uint8_t nextTxSn: 1; //!< The SN bit of the header of the next packet to transmit - uint8_t bFirstPkt: 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise - uint8_t bAutoEmpty: 1; //!< 1 if the last transmitted packet was an auto-empty packet - uint8_t bLlCtrlTx: 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) - uint8_t bLlCtrlAckRx: 1; //!< 1 if the last received packet was the ACK of an LL control packet - uint8_t bLlCtrlAckPending: 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed - } seqStat; - uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit - uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit - uint32_t accessAddress; //!< Access address used on the connection - uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte - uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte - uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t lastRxSn : 1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn : 1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn : 1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt : 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty : 1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx : 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx : 1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending : 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte } __RFC_STRUCT_ATTR; //! @} @@ -657,47 +657,47 @@ struct __RFC_STRUCT rfc_bleMasterSlavePar_s struct __RFC_STRUCT rfc_bleMasterPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - dataQueue_t* pTxQ; //!< Pointer to transmit queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t lastRxSn: 1; //!< The SN bit of the header of the last packet received with CRC OK - uint8_t lastTxSn: 1; //!< The SN bit of the header of the last transmitted packet - uint8_t nextTxSn: 1; //!< The SN bit of the header of the next packet to transmit - uint8_t bFirstPkt: 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise - uint8_t bAutoEmpty: 1; //!< 1 if the last transmitted packet was an auto-empty packet - uint8_t bLlCtrlTx: 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) - uint8_t bLlCtrlAckRx: 1; //!< 1 if the last received packet was the ACK of an LL control packet - uint8_t bLlCtrlAckPending: 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed - } seqStat; - uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit - uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit - uint32_t accessAddress; //!< Access address used on the connection - uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte - uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte - uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< connection event as soon as allowed + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t lastRxSn : 1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn : 1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn : 1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt : 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty : 1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx : 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx : 1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending : 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< connection event as soon as allowed } __RFC_STRUCT_ATTR; //! @} @@ -708,60 +708,60 @@ struct __RFC_STRUCT rfc_bleMasterPar_s struct __RFC_STRUCT rfc_bleSlavePar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - dataQueue_t* pTxQ; //!< Pointer to transmit queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t lastRxSn: 1; //!< The SN bit of the header of the last packet received with CRC OK - uint8_t lastTxSn: 1; //!< The SN bit of the header of the last transmitted packet - uint8_t nextTxSn: 1; //!< The SN bit of the header of the next packet to transmit - uint8_t bFirstPkt: 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise - uint8_t bAutoEmpty: 1; //!< 1 if the last transmitted packet was an auto-empty packet - uint8_t bLlCtrlTx: 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) - uint8_t bLlCtrlAckRx: 1; //!< 1 if the last received packet was the ACK of an LL control packet - uint8_t bLlCtrlAckPending: 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed - } seqStat; - uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit - uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit - uint32_t accessAddress; //!< Access address used on the connection - uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte - uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte - uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } timeoutTrigger; //!< Trigger that defines timeout of the first receive operation - ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that defines timeout of the first - //!< receive operation - uint16_t __dummy0; - uint8_t __dummy1; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< connection event as soon as allowed + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t lastRxSn : 1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn : 1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn : 1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt : 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty : 1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx : 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx : 1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending : 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that defines timeout of the first receive operation + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that defines timeout of the first + //!< receive operation + uint16_t __dummy0; + uint8_t __dummy1; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< connection event as soon as allowed } __RFC_STRUCT_ATTR; //! @} @@ -772,55 +772,55 @@ struct __RFC_STRUCT rfc_bleSlavePar_s struct __RFC_STRUCT rfc_bleAdvPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t advFilterPolicy: 2; //!< \brief Advertiser filter policy
- //!< 0: Process scan and connect requests from all devices
- //!< 1: Process connect requests from all devices and only scan requests from - //!< devices that are in the white list
- //!< 2: Process scan requests from all devices and only connect requests from - //!< devices that are in the white list
- //!< 3: Process scan and connect requests only from devices in the white list - uint8_t deviceAddrType: 1; //!< The type of the device address -- public (0) or random (1) - uint8_t peerAddrType: 1; //!< Directed advertiser: The type of the peer address -- public (0) or random (1) - uint8_t bStrictLenFilter: 1; //!< \brief 0: Accept any packet with a valid advertising packet length
- //!< 1: Discard messages with illegal length for the given packet type - uint8_t : 2; - uint8_t rpaMode: 1; //!< \brief Resolvable private address mode
- //!< 0: Normal operation
- //!< 1: Use white list for a received RPA regardless of filter policy - } advConfig; - uint8_t advLen; //!< Size of advertiser data - uint8_t scanRspLen; //!< Size of scan response data - uint8_t* pAdvData; //!< Pointer to buffer containing ADV*_IND data - uint8_t* pScanRspData; //!< Pointer to buffer containing SCAN_RSP data - uint16_t* pDeviceAddress; //!< Pointer to device address used for this device - rfc_bleWhiteListEntry_t* pWhiteList; //!< Pointer to white list or peer address (directed advertiser) - uint16_t __dummy0; - uint8_t __dummy1; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the advertiser event as soon as allowed - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< advertiser event as soon as allowed + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t advFilterPolicy : 2; //!< \brief Advertiser filter policy
+ //!< 0: Process scan and connect requests from all devices
+ //!< 1: Process connect requests from all devices and only scan requests from + //!< devices that are in the white list
+ //!< 2: Process scan requests from all devices and only connect requests from + //!< devices that are in the white list
+ //!< 3: Process scan and connect requests only from devices in the white list + uint8_t deviceAddrType : 1; //!< The type of the device address -- public (0) or random (1) + uint8_t peerAddrType : 1; //!< Directed advertiser: The type of the peer address -- public (0) or random (1) + uint8_t bStrictLenFilter : 1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t : 2; + uint8_t rpaMode : 1; //!< \brief Resolvable private address mode
+ //!< 0: Normal operation
+ //!< 1: Use white list for a received RPA regardless of filter policy + } advConfig; + uint8_t advLen; //!< Size of advertiser data + uint8_t scanRspLen; //!< Size of scan response data + uint8_t* pAdvData; //!< Pointer to buffer containing ADV*_IND data + uint8_t* pScanRspData; //!< Pointer to buffer containing SCAN_RSP data + uint16_t* pDeviceAddress; //!< Pointer to device address used for this device + rfc_bleWhiteListEntry_t* pWhiteList; //!< Pointer to white list or peer address (directed advertiser) + uint16_t __dummy0; + uint8_t __dummy1; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the advertiser event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< advertiser event as soon as allowed } __RFC_STRUCT_ATTR; //! @} @@ -831,74 +831,74 @@ struct __RFC_STRUCT rfc_bleAdvPar_s struct __RFC_STRUCT rfc_bleScannerPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t scanFilterPolicy: 1; //!< \brief Scanning filter policy
- //!< 0: Accept all advertisement packets
- //!< 1: Accept only advertisement packets from devices where the advertiser's address - //!< is in the White list. - uint8_t bActiveScan: 1; //!< \brief 0: Passive scan
- //!< 1: Active scan - uint8_t deviceAddrType: 1; //!< The type of the device address -- public (0) or random (1) - uint8_t : 1; - uint8_t bStrictLenFilter: 1; //!< \brief 0: Accept any packet with a valid advertising packet length
- //!< 1: Discard messages with illegal length for the given packet type - uint8_t bAutoWlIgnore: 1; //!< 1: Automatically set ignore bit in white list - uint8_t bEndOnRpt: 1; //!< \brief 0: Continue scanner operation after each reporting ADV*_IND or sending SCAN_RSP
- //!< 1: End scanner operation after each reported ADV*_IND and potentially SCAN_RSP - uint8_t rpaMode: 1; //!< \brief Resolvable private address mode
- //!< 0: Normal operation
- //!< 1: Use white list for a received RPA regardless of filter policy - } scanConfig; - uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure - uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth 4.0 spec - struct - { - uint8_t logUpperLimit: 4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure - uint8_t bLastSucceeded: 1; //!< \brief 1 if the last SCAN_RSP was successfully received and upperLimit - //!< not changed - uint8_t bLastFailed: 1; //!< \brief 1 if reception of the last SCAN_RSP failed and upperLimit was not - //!< changed - } backoffPar; - uint8_t scanReqLen; //!< Size of scan request data - uint8_t* pScanReqData; //!< Pointer to buffer containing SCAN_REQ data - uint16_t* pDeviceAddress; //!< Pointer to device address used for this device - rfc_bleWhiteListEntry_t* pWhiteList; //!< Pointer to white list - uint16_t __dummy0; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_ENDED + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t scanFilterPolicy : 1; //!< \brief Scanning filter policy
+ //!< 0: Accept all advertisement packets
+ //!< 1: Accept only advertisement packets from devices where the advertiser's address + //!< is in the White list. + uint8_t bActiveScan : 1; //!< \brief 0: Passive scan
+ //!< 1: Active scan + uint8_t deviceAddrType : 1; //!< The type of the device address -- public (0) or random (1) + uint8_t : 1; + uint8_t bStrictLenFilter : 1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t bAutoWlIgnore : 1; //!< 1: Automatically set ignore bit in white list + uint8_t bEndOnRpt : 1; //!< \brief 0: Continue scanner operation after each reporting ADV*_IND or sending SCAN_RSP
+ //!< 1: End scanner operation after each reported ADV*_IND and potentially SCAN_RSP + uint8_t rpaMode : 1; //!< \brief Resolvable private address mode
+ //!< 0: Normal operation
+ //!< 1: Use white list for a received RPA regardless of filter policy + } scanConfig; + uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure + uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth 4.0 spec + struct + { + uint8_t logUpperLimit : 4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure + uint8_t bLastSucceeded : 1; //!< \brief 1 if the last SCAN_RSP was successfully received and upperLimit + //!< not changed + uint8_t bLastFailed : 1; //!< \brief 1 if reception of the last SCAN_RSP failed and upperLimit was not + //!< changed + } backoffPar; + uint8_t scanReqLen; //!< Size of scan request data + uint8_t* pScanReqData; //!< Pointer to buffer containing SCAN_REQ data + uint16_t* pDeviceAddress; //!< Pointer to device address used for this device + rfc_bleWhiteListEntry_t* pWhiteList; //!< Pointer to white list + uint16_t __dummy0; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_ENDED } __RFC_STRUCT_ATTR; //! @} @@ -909,61 +909,61 @@ struct __RFC_STRUCT rfc_bleScannerPar_s struct __RFC_STRUCT rfc_bleInitiatorPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t bUseWhiteList: 1; //!< \brief Initiator filter policy
- //!< 0: Use specific peer address
- //!< 1: Use white list - uint8_t bDynamicWinOffset: 1; //!< \brief 0: No dynamic WinOffset insertion
- //!< 1: Use dynamic WinOffset insertion - uint8_t deviceAddrType: 1; //!< The type of the device address -- public (0) or random (1) - uint8_t peerAddrType: 1; //!< The type of the peer address -- public (0) or random (1) - uint8_t bStrictLenFilter: 1; //!< \brief 0: Accept any packet with a valid advertising packet length
- //!< 1: Discard messages with illegal length for the given packet type - } initConfig; - uint8_t __dummy0; - uint8_t connectReqLen; //!< Size of connect request data - uint8_t* pConnectReqData; //!< Pointer to buffer containing LLData to go in the CONNECT_REQ - uint16_t* pDeviceAddress; //!< Pointer to device address used for this device - rfc_bleWhiteListEntry_t* pWhiteList; //!< Pointer to white list or peer address - ratmr_t connectTime; //!< \brief Indication of timer value of the first possible start time of the first connection event. - //!< Set to the calculated value if a connection is made and to the next possible connection - //!< time if not. - uint16_t __dummy1; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_ENDED + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t bUseWhiteList : 1; //!< \brief Initiator filter policy
+ //!< 0: Use specific peer address
+ //!< 1: Use white list + uint8_t bDynamicWinOffset : 1; //!< \brief 0: No dynamic WinOffset insertion
+ //!< 1: Use dynamic WinOffset insertion + uint8_t deviceAddrType : 1; //!< The type of the device address -- public (0) or random (1) + uint8_t peerAddrType : 1; //!< The type of the peer address -- public (0) or random (1) + uint8_t bStrictLenFilter : 1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + } initConfig; + uint8_t __dummy0; + uint8_t connectReqLen; //!< Size of connect request data + uint8_t* pConnectReqData; //!< Pointer to buffer containing LLData to go in the CONNECT_REQ + uint16_t* pDeviceAddress; //!< Pointer to device address used for this device + rfc_bleWhiteListEntry_t* pWhiteList; //!< Pointer to white list or peer address + ratmr_t connectTime; //!< \brief Indication of timer value of the first possible start time of the first connection event. + //!< Set to the calculated value if a connection is made and to the next possible connection + //!< time if not. + uint16_t __dummy1; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_ENDED } __RFC_STRUCT_ATTR; //! @} @@ -974,36 +974,36 @@ struct __RFC_STRUCT rfc_bleInitiatorPar_s struct __RFC_STRUCT rfc_bleGenericRxPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue. May be NULL; if so, received packets are not stored - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - uint8_t bRepeat; //!< \brief 0: End operation after receiving a packet
- //!< 1: Restart receiver after receiving a packet - uint16_t __dummy0; - uint32_t accessAddress; //!< Access address used on the connection - uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte - uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte - uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the Rx operation - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< Rx operation + dataQueue_t* pRxQ; //!< Pointer to receive queue. May be NULL; if so, received packets are not stored + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + uint8_t bRepeat; //!< \brief 0: End operation after receiving a packet
+ //!< 1: Restart receiver after receiving a packet + uint16_t __dummy0; + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Rx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< Rx operation } __RFC_STRUCT_ATTR; //! @} @@ -1014,34 +1014,34 @@ struct __RFC_STRUCT rfc_bleGenericRxPar_s struct __RFC_STRUCT rfc_bleTxTestPar_s { - uint16_t numPackets; //!< \brief Number of packets to transmit
- //!< 0: Transmit unlimited number of packets - uint8_t payloadLength; //!< The number of payload bytes in each packet. - uint8_t packetType; //!< \brief The packet type to be used, encoded according to the Bluetooth 4.0 spec, Volume 2, Part E, - //!< Section 7.8.29 - ratmr_t period; //!< Number of radio timer cycles between the start of each packet - struct - { - uint8_t bOverrideDefault: 1; //!< \brief 0: Use default packet encoding
- //!< 1: Override packet contents - uint8_t bUsePrbs9: 1; //!< \brief If bOverride is 1:
- //!< 1: Use PRBS9 encoding of packet - uint8_t bUsePrbs15: 1; //!< \brief If bOverride is 1:
- //!< 1: Use PRBS15 encoding of packet - } config; - uint8_t byteVal; //!< If config.bOverride is 1, value of each byte to be sent - uint8_t __dummy0; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the Test Tx operation - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< Test Tx operation + uint16_t numPackets; //!< \brief Number of packets to transmit
+ //!< 0: Transmit unlimited number of packets + uint8_t payloadLength; //!< The number of payload bytes in each packet. + uint8_t packetType; //!< \brief The packet type to be used, encoded according to the Bluetooth 4.0 spec, Volume 2, Part E, + //!< Section 7.8.29 + ratmr_t period; //!< Number of radio timer cycles between the start of each packet + struct + { + uint8_t bOverrideDefault : 1; //!< \brief 0: Use default packet encoding
+ //!< 1: Override packet contents + uint8_t bUsePrbs9 : 1; //!< \brief If bOverride is 1:
+ //!< 1: Use PRBS9 encoding of packet + uint8_t bUsePrbs15 : 1; //!< \brief If bOverride is 1:
+ //!< 1: Use PRBS15 encoding of packet + } config; + uint8_t byteVal; //!< If config.bOverride is 1, value of each byte to be sent + uint8_t __dummy0; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Test Tx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< Test Tx operation } __RFC_STRUCT_ATTR; //! @} @@ -1052,37 +1052,37 @@ struct __RFC_STRUCT rfc_bleTxTestPar_s struct __RFC_STRUCT rfc_bleMasterSlaveOutput_s { - uint8_t nTx; //!< \brief Total number of packets (including auto-empty and retransmissions) that have been - //!< transmitted - uint8_t nTxAck; //!< Total number of transmitted packets (including auto-empty) that have been ACK'ed - uint8_t nTxCtrl; //!< Number of unique LL control packets from the Tx queue that have been transmitted - uint8_t nTxCtrlAck; //!< Number of LL control packets from the Tx queue that have been finished (ACK'ed) - uint8_t nTxCtrlAckAck; //!< \brief Number of LL control packets that have been ACK'ed and where an ACK has been sent in - //!< response - uint8_t nTxRetrans; //!< Number of retransmissions that has been done - uint8_t nTxEntryDone; //!< Number of packets from the Tx queue that have been finished (ACK'ed) - uint8_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored - uint8_t nRxCtrl; //!< Number of LL control packets that have been received with CRC OK and not ignored - uint8_t nRxCtrlAck; //!< \brief Number of LL control packets that have been received with CRC OK and not ignored, and - //!< then ACK'ed - uint8_t nRxNok; //!< Number of packets that have been received with CRC error - uint8_t nRxIgnored; //!< \brief Number of packets that have been received with CRC OK and ignored due to repeated - //!< sequence number - uint8_t nRxEmpty; //!< Number of packets that have been received with CRC OK and no payload - uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space - int8_t lastRssi; //!< RSSI of last received packet - struct - { - uint8_t bTimeStampValid: 1; //!< 1 if a valid time stamp has been written to timeStamp; 0 otherwise - uint8_t bLastCrcErr: 1; //!< 1 if the last received packet had CRC error; 0 otherwise - uint8_t bLastIgnored: 1; //!< 1 if the last received packet with CRC OK was ignored; 0 otherwise - uint8_t bLastEmpty: 1; //!< 1 if the last received packet with CRC OK was empty; 0 otherwise - uint8_t bLastCtrl: 1; //!< 1 if the last received packet with CRC OK was empty; 0 otherwise - uint8_t bLastMd: 1; //!< 1 if the last received packet with CRC OK had MD = 1; 0 otherwise - uint8_t bLastAck: 1; //!< \brief 1 if the last received packet with CRC OK was an ACK of a transmitted packet; - //!< 0 otherwise - } pktStatus; - ratmr_t timeStamp; //!< Slave operation: Time stamp of first received packet + uint8_t nTx; //!< \brief Total number of packets (including auto-empty and retransmissions) that have been + //!< transmitted + uint8_t nTxAck; //!< Total number of transmitted packets (including auto-empty) that have been ACK'ed + uint8_t nTxCtrl; //!< Number of unique LL control packets from the Tx queue that have been transmitted + uint8_t nTxCtrlAck; //!< Number of LL control packets from the Tx queue that have been finished (ACK'ed) + uint8_t nTxCtrlAckAck; //!< \brief Number of LL control packets that have been ACK'ed and where an ACK has been sent in + //!< response + uint8_t nTxRetrans; //!< Number of retransmissions that has been done + uint8_t nTxEntryDone; //!< Number of packets from the Tx queue that have been finished (ACK'ed) + uint8_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored + uint8_t nRxCtrl; //!< Number of LL control packets that have been received with CRC OK and not ignored + uint8_t nRxCtrlAck; //!< \brief Number of LL control packets that have been received with CRC OK and not ignored, and + //!< then ACK'ed + uint8_t nRxNok; //!< Number of packets that have been received with CRC error + uint8_t nRxIgnored; //!< \brief Number of packets that have been received with CRC OK and ignored due to repeated + //!< sequence number + uint8_t nRxEmpty; //!< Number of packets that have been received with CRC OK and no payload + uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< RSSI of last received packet + struct + { + uint8_t bTimeStampValid : 1; //!< 1 if a valid time stamp has been written to timeStamp; 0 otherwise + uint8_t bLastCrcErr : 1; //!< 1 if the last received packet had CRC error; 0 otherwise + uint8_t bLastIgnored : 1; //!< 1 if the last received packet with CRC OK was ignored; 0 otherwise + uint8_t bLastEmpty : 1; //!< 1 if the last received packet with CRC OK was empty; 0 otherwise + uint8_t bLastCtrl : 1; //!< 1 if the last received packet with CRC OK was empty; 0 otherwise + uint8_t bLastMd : 1; //!< 1 if the last received packet with CRC OK had MD = 1; 0 otherwise + uint8_t bLastAck : 1; //!< \brief 1 if the last received packet with CRC OK was an ACK of a transmitted packet; + //!< 0 otherwise + } pktStatus; + ratmr_t timeStamp; //!< Slave operation: Time stamp of first received packet } __RFC_STRUCT_ATTR; //! @} @@ -1093,16 +1093,16 @@ struct __RFC_STRUCT rfc_bleMasterSlaveOutput_s struct __RFC_STRUCT rfc_bleAdvOutput_s { - uint16_t nTxAdvInd; //!< Number of ADV*_IND packets completely transmitted - uint8_t nTxScanRsp; //!< Number of SCAN_RSP packets transmitted - uint8_t nRxScanReq; //!< Number of SCAN_REQ packets received OK and not ignored - uint8_t nRxConnectReq; //!< Number of CONNECT_REQ packets received OK and not ignored - uint8_t __dummy0; - uint16_t nRxNok; //!< Number of packets received with CRC error - uint16_t nRxIgnored; //!< Number of packets received with CRC OK, but ignored - uint8_t nRxBufFull; //!< Number of packets received that did not fit in Rx queue - int8_t lastRssi; //!< The RSSI of the last received packet - ratmr_t timeStamp; //!< Time stamp of the last received packet + uint16_t nTxAdvInd; //!< Number of ADV*_IND packets completely transmitted + uint8_t nTxScanRsp; //!< Number of SCAN_RSP packets transmitted + uint8_t nRxScanReq; //!< Number of SCAN_REQ packets received OK and not ignored + uint8_t nRxConnectReq; //!< Number of CONNECT_REQ packets received OK and not ignored + uint8_t __dummy0; + uint16_t nRxNok; //!< Number of packets received with CRC error + uint16_t nRxIgnored; //!< Number of packets received with CRC OK, but ignored + uint8_t nRxBufFull; //!< Number of packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet + ratmr_t timeStamp; //!< Time stamp of the last received packet } __RFC_STRUCT_ATTR; //! @} @@ -1113,19 +1113,19 @@ struct __RFC_STRUCT rfc_bleAdvOutput_s struct __RFC_STRUCT rfc_bleScannerOutput_s { - uint16_t nTxScanReq; //!< Number of transmitted SCAN_REQ packets - uint16_t nBackedOffScanReq; //!< Number of SCAN_REQ packets not sent due to backoff procedure - uint16_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored - uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored - uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error - uint16_t nRxScanRspOk; //!< Number of SCAN_RSP packets received with CRC OK and not ignored - uint16_t nRxScanRspIgnored; //!< Number of SCAN_RSP packets received with CRC OK, but ignored - uint16_t nRxScanRspNok; //!< Number of SCAN_RSP packets received with CRC error - uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue - uint8_t nRxScanRspBufFull; //!< Number of SCAN_RSP packets received that did not fit in Rx queue - int8_t lastRssi; //!< The RSSI of the last received packet - uint8_t __dummy0; - ratmr_t timeStamp; //!< Time stamp of the last successfully received ADV*_IND packet that was not ignored + uint16_t nTxScanReq; //!< Number of transmitted SCAN_REQ packets + uint16_t nBackedOffScanReq; //!< Number of SCAN_REQ packets not sent due to backoff procedure + uint16_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored + uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored + uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error + uint16_t nRxScanRspOk; //!< Number of SCAN_RSP packets received with CRC OK and not ignored + uint16_t nRxScanRspIgnored; //!< Number of SCAN_RSP packets received with CRC OK, but ignored + uint16_t nRxScanRspNok; //!< Number of SCAN_RSP packets received with CRC error + uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue + uint8_t nRxScanRspBufFull; //!< Number of SCAN_RSP packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet + uint8_t __dummy0; + ratmr_t timeStamp; //!< Time stamp of the last successfully received ADV*_IND packet that was not ignored } __RFC_STRUCT_ATTR; //! @} @@ -1136,13 +1136,13 @@ struct __RFC_STRUCT rfc_bleScannerOutput_s struct __RFC_STRUCT rfc_bleInitiatorOutput_s { - uint8_t nTxConnectReq; //!< Number of transmitted CONNECT_REQ packets - uint8_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored - uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored - uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error - uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue - int8_t lastRssi; //!< The RSSI of the last received packet - ratmr_t timeStamp; //!< Time stamp of the received ADV*_IND packet that caused transmission of CONNECT_REQ + uint8_t nTxConnectReq; //!< Number of transmitted CONNECT_REQ packets + uint8_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored + uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored + uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error + uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet + ratmr_t timeStamp; //!< Time stamp of the received ADV*_IND packet that caused transmission of CONNECT_REQ } __RFC_STRUCT_ATTR; //! @} @@ -1153,12 +1153,12 @@ struct __RFC_STRUCT rfc_bleInitiatorOutput_s struct __RFC_STRUCT rfc_bleGenericRxOutput_s { - uint16_t nRxOk; //!< Number of packets received with CRC OK - uint16_t nRxNok; //!< Number of packets received with CRC error - uint16_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space - int8_t lastRssi; //!< The RSSI of the last received packet - uint8_t __dummy0; - ratmr_t timeStamp; //!< Time stamp of the last received packet + uint16_t nRxOk; //!< Number of packets received with CRC OK + uint16_t nRxNok; //!< Number of packets received with CRC error + uint16_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< The RSSI of the last received packet + uint8_t __dummy0; + ratmr_t timeStamp; //!< Time stamp of the last received packet } __RFC_STRUCT_ATTR; //! @} @@ -1169,7 +1169,7 @@ struct __RFC_STRUCT rfc_bleGenericRxOutput_s struct __RFC_STRUCT rfc_bleTxTestOutput_s { - uint16_t nTx; //!< Number of packets transmitted + uint16_t nTx; //!< Number of packets transmitted } __RFC_STRUCT_ATTR; //! @} @@ -1180,19 +1180,19 @@ struct __RFC_STRUCT rfc_bleTxTestOutput_s struct __RFC_STRUCT rfc_bleWhiteListEntry_s { - uint8_t size; //!< Number of while list entries. Used in the first entry of the list only - struct - { - uint8_t bEnable: 1; //!< 1 if the entry is in use, 0 if the entry is not in use - uint8_t addrType: 1; //!< The type address in the entry -- public (0) or random (1) - uint8_t bWlIgn: 1; //!< \brief 1 if the entry is to be ignored by a scanner, 0 otherwise. Used to mask out - //!< entries that have already been scanned and reported. - uint8_t : 1; - uint8_t bIrkValid: 1; //!< \brief 1 if a valid IRK exists, so that the entry is to be ignored by an initiator, - //!< 0 otherwise - } conf; - uint16_t address; //!< Least significant 16 bits of the address contained in the entry - uint32_t addressHi; //!< Most significant 32 bits of the address contained in the entry + uint8_t size; //!< Number of while list entries. Used in the first entry of the list only + struct + { + uint8_t bEnable : 1; //!< 1 if the entry is in use, 0 if the entry is not in use + uint8_t addrType : 1; //!< The type address in the entry -- public (0) or random (1) + uint8_t bWlIgn : 1; //!< \brief 1 if the entry is to be ignored by a scanner, 0 otherwise. Used to mask out + //!< entries that have already been scanned and reported. + uint8_t : 1; + uint8_t bIrkValid : 1; //!< \brief 1 if a valid IRK exists, so that the entry is to be ignored by an initiator, + //!< 0 otherwise + } conf; + uint16_t address; //!< Least significant 16 bits of the address contained in the entry + uint32_t addressHi; //!< Most significant 32 bits of the address contained in the entry } __RFC_STRUCT_ATTR; //! @} @@ -1203,13 +1203,13 @@ struct __RFC_STRUCT rfc_bleWhiteListEntry_s struct __RFC_STRUCT rfc_bleRxStatus_s { - struct - { - uint8_t channel: 6; //!< \brief The channel on which the packet was received, provided channel is in the range - //!< 0--39; otherwise 0x3F - uint8_t bIgnore: 1; //!< 1 if the packet is marked as ignored, 0 otherwise - uint8_t bCrcErr: 1; //!< 1 if the packet was received with CRC error, 0 otherwise - } status; + struct + { + uint8_t channel : 6; //!< \brief The channel on which the packet was received, provided channel is in the range + //!< 0--39; otherwise 0x3F + uint8_t bIgnore : 1; //!< 1 if the packet is marked as ignored, 0 otherwise + uint8_t bCrcErr : 1; //!< 1 if the packet was received with CRC error, 0 otherwise + } status; } __RFC_STRUCT_ATTR; //! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_ble_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_ble_mailbox.h index 4158977..239448e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_ble_mailbox.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_ble_mailbox.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_ble_mailbox.h -* Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) -* Revision: 18032 -* -* Description: Definitions for BLE interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_ble_mailbox.h + * Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) + * Revision: 18032 + * + * Description: Definitions for BLE interface + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _BLE_MAILBOX_H #define _BLE_MAILBOX_H @@ -43,25 +43,25 @@ ///@{ /// \name Operation finished normally ///@{ -#define BLE_DONE_OK 0x1400 ///< Operation ended normally -#define BLE_DONE_RXTIMEOUT 0x1401 ///< Timeout of first Rx of slave operation or end of scan window -#define BLE_DONE_NOSYNC 0x1402 ///< Timeout of subsequent Rx -#define BLE_DONE_RXERR 0x1403 ///< Operation ended because of receive error (CRC or other) -#define BLE_DONE_CONNECT 0x1404 ///< CONNECT_REQ received or transmitted -#define BLE_DONE_MAXNACK 0x1405 ///< Maximum number of retransmissions exceeded -#define BLE_DONE_ENDED 0x1406 ///< Operation stopped after end trigger -#define BLE_DONE_ABORT 0x1407 ///< Operation aborted by command -#define BLE_DONE_STOPPED 0x1408 ///< Operation stopped after stop command +#define BLE_DONE_OK 0x1400 ///< Operation ended normally +#define BLE_DONE_RXTIMEOUT 0x1401 ///< Timeout of first Rx of slave operation or end of scan window +#define BLE_DONE_NOSYNC 0x1402 ///< Timeout of subsequent Rx +#define BLE_DONE_RXERR 0x1403 ///< Operation ended because of receive error (CRC or other) +#define BLE_DONE_CONNECT 0x1404 ///< CONNECT_REQ received or transmitted +#define BLE_DONE_MAXNACK 0x1405 ///< Maximum number of retransmissions exceeded +#define BLE_DONE_ENDED 0x1406 ///< Operation stopped after end trigger +#define BLE_DONE_ABORT 0x1407 ///< Operation aborted by command +#define BLE_DONE_STOPPED 0x1408 ///< Operation stopped after stop command ///@} /// \name Operation finished with error ///@{ -#define BLE_ERROR_PAR 0x1800 ///< Illegal parameter -#define BLE_ERROR_RXBUF 0x1801 ///< No available Rx buffer (Advertiser, Scanner, Initiator) -#define BLE_ERROR_NO_SETUP 0x1802 ///< Operation using Rx or Tx attemted when not in BLE mode -#define BLE_ERROR_NO_FS 0x1803 ///< Operation using Rx or Tx attemted without frequency synth configured -#define BLE_ERROR_SYNTH_PROG 0x1804 ///< Synthesizer programming failed to complete on time -#define BLE_ERROR_RXOVF 0x1805 ///< Receiver overflowed during operation -#define BLE_ERROR_TXUNF 0x1806 ///< Transmitter underflowed during operation +#define BLE_ERROR_PAR 0x1800 ///< Illegal parameter +#define BLE_ERROR_RXBUF 0x1801 ///< No available Rx buffer (Advertiser, Scanner, Initiator) +#define BLE_ERROR_NO_SETUP 0x1802 ///< Operation using Rx or Tx attemted when not in BLE mode +#define BLE_ERROR_NO_FS 0x1803 ///< Operation using Rx or Tx attemted without frequency synth configured +#define BLE_ERROR_SYNTH_PROG 0x1804 ///< Synthesizer programming failed to complete on time +#define BLE_ERROR_RXOVF 0x1805 ///< Receiver overflowed during operation +#define BLE_ERROR_TXUNF 0x1806 ///< Transmitter underflowed during operation ///@} ///@} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_common_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_common_cmd.h index 2eade2b..c91a7b1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_common_cmd.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_common_cmd.h @@ -1,56 +1,56 @@ /****************************************************************************** -* Filename: rf_common_cmd.h -* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) -* Revision: 18052 -* -* Description: CC13x0 API for common/generic commands -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_common_cmd.h + * Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) + * Revision: 18052 + * + * Description: CC13x0 API for common/generic commands + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __COMMON_CMD_H #define __COMMON_CMD_H #ifndef __RFC_STRUCT - #define __RFC_STRUCT +#define __RFC_STRUCT #endif #ifndef __RFC_STRUCT_ATTR - #if defined(__GNUC__) - #define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) - #elif defined(__TI_ARM__) - #define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) - #else - #define __RFC_STRUCT_ATTR - #endif +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__((aligned(4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__((__packed__, aligned(4))) +#else +#define __RFC_STRUCT_ATTR +#endif #endif //! \addtogroup rfc @@ -59,8 +59,8 @@ //! \addtogroup common_cmd //! @{ -#include #include "rf_mailbox.h" +#include typedef struct __RFC_STRUCT rfc_command_s rfc_command_t; typedef struct __RFC_STRUCT rfc_radioOp_s rfc_radioOp_t; @@ -106,7 +106,7 @@ typedef struct __RFC_STRUCT rfc_CMD_BUS_REQUEST_s rfc_CMD_BUS_REQUEST_t; //! @{ struct __RFC_STRUCT rfc_command_s { - uint16_t commandNo; //!< The command ID number + uint16_t commandNo; //!< The command ID number } __RFC_STRUCT_ATTR; //! @} @@ -117,891 +117,891 @@ struct __RFC_STRUCT rfc_command_s struct __RFC_STRUCT rfc_radioOp_s { - uint16_t commandNo; //!< The command ID number - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_NOP //! @{ -#define CMD_NOP 0x0801 +#define CMD_NOP 0x0801 //! No Operation Command struct __RFC_STRUCT rfc_CMD_NOP_s { - uint16_t commandNo; //!< The command ID number 0x0801 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; + uint16_t commandNo; //!< The command ID number 0x0801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_RADIO_SETUP //! @{ -#define CMD_RADIO_SETUP 0x0802 +#define CMD_RADIO_SETUP 0x0802 //! Radio Setup Command for Pre-Defined Schemes struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_s { - uint16_t commandNo; //!< The command ID number 0x0802 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t mode; //!< \brief The main mode to use
- //!< 0x00: BLE
- //!< 0x01: IEEE 802.15.4
- //!< 0x02: 2 Mbps GFSK
- //!< 0x05: 5 Mbps coded 8-FSK
- //!< 0xFF: Keep existing mode; update overrides only
- //!< Others: Reserved - uint8_t loDivider; //!< \brief LO divider setting to use. Supported values: 0 (equivalent to 2), 2, - //!< 5, 6, 10, 12, 15, and 30.
- //!< Value of 0 or 2 only supported for CC1350 - struct - { - uint16_t frontEndMode: 3; //!< \brief 0x00: Differential mode
- //!< 0x01: Single-ended mode RFP
- //!< 0x02: Single-ended mode RFN
- //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
- //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ uint16_t commandNo; //!< The command ID number 0x0802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t mode; //!< \brief The main mode to use
+ //!< 0x00: BLE
+ //!< 0x01: IEEE 802.15.4
+ //!< 0x02: 2 Mbps GFSK
+ //!< 0x05: 5 Mbps coded 8-FSK
+ //!< 0xFF: Keep existing mode; update overrides only
//!< Others: Reserved - uint16_t biasMode: 1; //!< \brief 0: Internal bias
- //!< 1: External bias - uint16_t analogCfgMode: 6; //!< \brief 0x00: Write analog configuration.
- //!< Required first time after boot and when changing frequency band - //!< or front-end configuration
- //!< 0x2D: Keep analog configuration.
- //!< May be used after standby or when changing mode with the same frequency - //!< band and front-end configuration
- //!< Others: Reserved - uint16_t bNoFsPowerUp: 1; //!< \brief 0: Power up frequency synth
- //!< 1: Do not power up frequency synth - } config; //!< Configuration options - uint16_t txPower; //!< Transmit power - uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no - //!< override is used. + uint8_t loDivider; //!< \brief LO divider setting to use. Supported values: 0 (equivalent to 2), 2, + //!< 5, 6, 10, 12, 15, and 30.
+ //!< Value of 0 or 2 only supported for CC1350 + struct + { + uint16_t frontEndMode : 3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode : 1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode : 6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp : 1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_FS //! @{ -#define CMD_FS 0x0803 +#define CMD_FS 0x0803 //! Frequency Synthesizer Programming Command struct __RFC_STRUCT rfc_CMD_FS_s { - uint16_t commandNo; //!< The command ID number 0x0803 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t frequency; //!< The frequency in MHz to tune to - uint16_t fractFreq; //!< Fractional part of the frequency to tune to - struct - { - uint8_t bTxMode: 1; //!< \brief 0: Start synth in RX mode
- //!< 1: Start synth in TX mode - uint8_t refFreq: 6; //!< \brief 0: Use default reference frequency
- //!< Others: Use reference frequency 24 MHz/refFreq - } synthConf; - uint8_t __dummy0; //!< Reserved, always write 0 - uint8_t __dummy1; //!< Reserved - uint8_t __dummy2; //!< Reserved - uint16_t __dummy3; //!< Reserved + uint16_t commandNo; //!< The command ID number 0x0803 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t frequency; //!< The frequency in MHz to tune to + uint16_t fractFreq; //!< Fractional part of the frequency to tune to + struct + { + uint8_t bTxMode : 1; //!< \brief 0: Start synth in RX mode
+ //!< 1: Start synth in TX mode + uint8_t refFreq : 6; //!< \brief 0: Use default reference frequency
+ //!< Others: Use reference frequency 24 MHz/refFreq + } synthConf; + uint8_t __dummy0; //!< Reserved, always write 0 + uint8_t __dummy1; //!< Reserved + uint8_t __dummy2; //!< Reserved + uint16_t __dummy3; //!< Reserved } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_FS_OFF //! @{ -#define CMD_FS_OFF 0x0804 +#define CMD_FS_OFF 0x0804 //! Command for Turning off Frequency Synthesizer struct __RFC_STRUCT rfc_CMD_FS_OFF_s { - uint16_t commandNo; //!< The command ID number 0x0804 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; + uint16_t commandNo; //!< The command ID number 0x0804 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_RX_TEST //! @{ -#define CMD_RX_TEST 0x0807 +#define CMD_RX_TEST 0x0807 //! Receiver Test Command struct __RFC_STRUCT rfc_CMD_RX_TEST_s { - uint16_t commandNo; //!< The command ID number 0x0807 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bEnaFifo: 1; //!< \brief 0: Do not enable FIFO in modem, so that received data is not available
- //!< 1: Enable FIFO in modem -- the data must be read out by the application - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bNoSync: 1; //!< \brief 0: Run sync search as normal for the configured mode
- //!< 1: Write correlation thresholds to the maximum value to avoid getting sync - } config; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - uint32_t syncWord; //!< Sync word to use for receiver - ratmr_t endTime; //!< Time to end the operation + uint16_t commandNo; //!< The command ID number 0x0807 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bEnaFifo : 1; //!< \brief 0: Do not enable FIFO in modem, so that received data is not available
+ //!< 1: Enable FIFO in modem -- the data must be read out by the application + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bNoSync : 1; //!< \brief 0: Run sync search as normal for the configured mode
+ //!< 1: Write correlation thresholds to the maximum value to avoid getting sync + } config; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + uint32_t syncWord; //!< Sync word to use for receiver + ratmr_t endTime; //!< Time to end the operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_TX_TEST //! @{ -#define CMD_TX_TEST 0x0808 +#define CMD_TX_TEST 0x0808 //! Transmitter Test Command struct __RFC_STRUCT rfc_CMD_TX_TEST_s { - uint16_t commandNo; //!< The command ID number 0x0808 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bUseCw: 1; //!< \brief 0: Send modulated signal
- //!< 1: Send continuous wave - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t whitenMode: 2; //!< \brief 0: No whitening
- //!< 1: Default whitening
- //!< 2: PRBS-15
- //!< 3: PRBS-32 - } config; - uint8_t __dummy0; - uint16_t txWord; //!< Value to send to the modem before whitening - uint8_t __dummy1; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - uint32_t syncWord; //!< Sync word to use for transmitter - ratmr_t endTime; //!< Time to end the operation + uint16_t commandNo; //!< The command ID number 0x0808 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bUseCw : 1; //!< \brief 0: Send modulated signal
+ //!< 1: Send continuous wave + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t whitenMode : 2; //!< \brief 0: No whitening
+ //!< 1: Default whitening
+ //!< 2: PRBS-15
+ //!< 3: PRBS-32 + } config; + uint8_t __dummy0; + uint16_t txWord; //!< Value to send to the modem before whitening + uint8_t __dummy1; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + uint32_t syncWord; //!< Sync word to use for transmitter + ratmr_t endTime; //!< Time to end the operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SYNC_STOP_RAT //! @{ -#define CMD_SYNC_STOP_RAT 0x0809 +#define CMD_SYNC_STOP_RAT 0x0809 //! Synchronize and Stop Radio Timer Command struct __RFC_STRUCT rfc_CMD_SYNC_STOP_RAT_s { - uint16_t commandNo; //!< The command ID number 0x0809 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t __dummy0; - ratmr_t rat0; //!< \brief The returned RAT timer value corresponding to the value the RAT would have had when the - //!< RTC was zero + uint16_t commandNo; //!< The command ID number 0x0809 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + ratmr_t rat0; //!< \brief The returned RAT timer value corresponding to the value the RAT would have had when the + //!< RTC was zero } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SYNC_START_RAT //! @{ -#define CMD_SYNC_START_RAT 0x080A +#define CMD_SYNC_START_RAT 0x080A //! Synchrously Start Radio Timer Command struct __RFC_STRUCT rfc_CMD_SYNC_START_RAT_s { - uint16_t commandNo; //!< The command ID number 0x080A - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t __dummy0; - ratmr_t rat0; //!< \brief The desired RAT timer value corresponding to the value the RAT would have had when the - //!< RTC was zero. This parameter is returned by CMD_SYNC_STOP_RAT + uint16_t commandNo; //!< The command ID number 0x080A + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + ratmr_t rat0; //!< \brief The desired RAT timer value corresponding to the value the RAT would have had when the + //!< RTC was zero. This parameter is returned by CMD_SYNC_STOP_RAT } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_COUNT //! @{ -#define CMD_COUNT 0x080B +#define CMD_COUNT 0x080B //! Counter Command struct __RFC_STRUCT rfc_CMD_COUNT_s { - uint16_t commandNo; //!< The command ID number 0x080B - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation - //!< differs if the result is zero + uint16_t commandNo; //!< The command ID number 0x080B + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation + //!< differs if the result is zero } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_FS_POWERUP //! @{ -#define CMD_FS_POWERUP 0x080C +#define CMD_FS_POWERUP 0x080C //! Power up Frequency Syntheszier Command struct __RFC_STRUCT rfc_CMD_FS_POWERUP_s { - uint16_t commandNo; //!< The command ID number 0x080C - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t __dummy0; - uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override. If NULL, no override is used. + uint16_t commandNo; //!< The command ID number 0x080C + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override. If NULL, no override is used. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_FS_POWERDOWN //! @{ -#define CMD_FS_POWERDOWN 0x080D +#define CMD_FS_POWERDOWN 0x080D //! Power down Frequency Syntheszier Command struct __RFC_STRUCT rfc_CMD_FS_POWERDOWN_s { - uint16_t commandNo; //!< The command ID number 0x080D - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; + uint16_t commandNo; //!< The command ID number 0x080D + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SCH_IMM //! @{ -#define CMD_SCH_IMM 0x0810 +#define CMD_SCH_IMM 0x0810 //! Run Immidiate Command as Radio Operation Command struct __RFC_STRUCT rfc_CMD_SCH_IMM_s { - uint16_t commandNo; //!< The command ID number 0x0810 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t __dummy0; - uint32_t cmdrVal; //!< Value as would be written to CMDR - uint32_t cmdstaVal; //!< Value as would be returned in CMDSTA + uint16_t commandNo; //!< The command ID number 0x0810 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + uint32_t cmdrVal; //!< Value as would be written to CMDR + uint32_t cmdstaVal; //!< Value as would be returned in CMDSTA } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_COUNT_BRANCH //! @{ -#define CMD_COUNT_BRANCH 0x0812 +#define CMD_COUNT_BRANCH 0x0812 //! Counter Command with Branch of Command Chain struct __RFC_STRUCT rfc_CMD_COUNT_BRANCH_s { - uint16_t commandNo; //!< The command ID number 0x0812 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation - //!< differs if the result is zero - rfc_radioOp_t* pNextOpIfOk; //!< Pointer to next operation if counter did not expire + uint16_t commandNo; //!< The command ID number 0x0812 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation + //!< differs if the result is zero + rfc_radioOp_t* pNextOpIfOk; //!< Pointer to next operation if counter did not expire } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PATTERN_CHECK //! @{ -#define CMD_PATTERN_CHECK 0x0813 +#define CMD_PATTERN_CHECK 0x0813 //! Command for Checking a Value in Memory aginst a Pattern struct __RFC_STRUCT rfc_CMD_PATTERN_CHECK_s { - uint16_t commandNo; //!< The command ID number 0x0813 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint16_t operation: 2; //!< \brief Operation to perform
- //!< 0: True if value == compareVal
- //!< 1: True if value < compareVal
- //!< 2: True if value > compareVal
- //!< 3: Reserved - uint16_t bByteRev: 1; //!< \brief If 1, interchange the four bytes of the value, so that they are read - //!< most-significant-byte-first. - uint16_t bBitRev: 1; //!< If 1, perform bit reversal of the value - uint16_t signExtend: 5; //!< \brief 0: Treat value and compareVal as unsigned
- //!< 1--31: Treat value and compareVal as signed, where the value - //!< gives the number of the most significant bit in the signed number. - uint16_t bRxVal: 1; //!< \brief 0: Use pValue as a pointer
- //!< 1: Use pValue as a signed offset to the start of the last - //!< committed RX entry element - } patternOpt; //!< Options for comparison - rfc_radioOp_t* pNextOpIfOk; //!< Pointer to next operation if comparison result was true - uint8_t* pValue; //!< Pointer to read from, or offset from last RX entry if patternOpt.bRxVal == 1 - uint32_t mask; //!< Bit mask to apply before comparison - uint32_t compareVal; //!< Value to compare to + uint16_t commandNo; //!< The command ID number 0x0813 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint16_t operation : 2; //!< \brief Operation to perform
+ //!< 0: True if value == compareVal
+ //!< 1: True if value < compareVal
+ //!< 2: True if value > compareVal
+ //!< 3: Reserved + uint16_t bByteRev : 1; //!< \brief If 1, interchange the four bytes of the value, so that they are read + //!< most-significant-byte-first. + uint16_t bBitRev : 1; //!< If 1, perform bit reversal of the value + uint16_t signExtend : 5; //!< \brief 0: Treat value and compareVal as unsigned
+ //!< 1--31: Treat value and compareVal as signed, where the value + //!< gives the number of the most significant bit in the signed number. + uint16_t bRxVal : 1; //!< \brief 0: Use pValue as a pointer
+ //!< 1: Use pValue as a signed offset to the start of the last + //!< committed RX entry element + } patternOpt; //!< Options for comparison + rfc_radioOp_t* pNextOpIfOk; //!< Pointer to next operation if comparison result was true + uint8_t* pValue; //!< Pointer to read from, or offset from last RX entry if patternOpt.bRxVal == 1 + uint32_t mask; //!< Bit mask to apply before comparison + uint32_t compareVal; //!< Value to compare to } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_ABORT //! @{ -#define CMD_ABORT 0x0401 +#define CMD_ABORT 0x0401 //! Abort Running Radio Operation Command struct __RFC_STRUCT rfc_CMD_ABORT_s { - uint16_t commandNo; //!< The command ID number 0x0401 + uint16_t commandNo; //!< The command ID number 0x0401 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_STOP //! @{ -#define CMD_STOP 0x0402 +#define CMD_STOP 0x0402 //! Stop Running Radio Operation Command Gracefully struct __RFC_STRUCT rfc_CMD_STOP_s { - uint16_t commandNo; //!< The command ID number 0x0402 + uint16_t commandNo; //!< The command ID number 0x0402 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_GET_RSSI //! @{ -#define CMD_GET_RSSI 0x0403 +#define CMD_GET_RSSI 0x0403 //! Read RSSI Command struct __RFC_STRUCT rfc_CMD_GET_RSSI_s { - uint16_t commandNo; //!< The command ID number 0x0403 + uint16_t commandNo; //!< The command ID number 0x0403 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_UPDATE_RADIO_SETUP //! @{ -#define CMD_UPDATE_RADIO_SETUP 0x0001 +#define CMD_UPDATE_RADIO_SETUP 0x0001 //! Update Radio Settings Command struct __RFC_STRUCT rfc_CMD_UPDATE_RADIO_SETUP_s { - uint16_t commandNo; //!< The command ID number 0x0001 - uint16_t __dummy0; - uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override + uint16_t commandNo; //!< The command ID number 0x0001 + uint16_t __dummy0; + uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_TRIGGER //! @{ -#define CMD_TRIGGER 0x0404 +#define CMD_TRIGGER 0x0404 //! Generate Command Trigger struct __RFC_STRUCT rfc_CMD_TRIGGER_s { - uint16_t commandNo; //!< The command ID number 0x0404 - uint8_t triggerNo; //!< Command trigger number + uint16_t commandNo; //!< The command ID number 0x0404 + uint8_t triggerNo; //!< Command trigger number } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_GET_FW_INFO //! @{ -#define CMD_GET_FW_INFO 0x0002 +#define CMD_GET_FW_INFO 0x0002 //! Request Information on the RF Core ROM Firmware struct __RFC_STRUCT rfc_CMD_GET_FW_INFO_s { - uint16_t commandNo; //!< The command ID number 0x0002 - uint16_t versionNo; //!< Firmware version number - uint16_t startOffset; //!< The start of free RAM - uint16_t freeRamSz; //!< The size of free RAM - uint16_t availRatCh; //!< Bitmap of available RAT channels + uint16_t commandNo; //!< The command ID number 0x0002 + uint16_t versionNo; //!< Firmware version number + uint16_t startOffset; //!< The start of free RAM + uint16_t freeRamSz; //!< The size of free RAM + uint16_t availRatCh; //!< Bitmap of available RAT channels } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_START_RAT //! @{ -#define CMD_START_RAT 0x0405 +#define CMD_START_RAT 0x0405 //! Asynchronously Start Radio Timer Command struct __RFC_STRUCT rfc_CMD_START_RAT_s { - uint16_t commandNo; //!< The command ID number 0x0405 + uint16_t commandNo; //!< The command ID number 0x0405 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PING //! @{ -#define CMD_PING 0x0406 +#define CMD_PING 0x0406 //! Respond with Command ACK Only struct __RFC_STRUCT rfc_CMD_PING_s { - uint16_t commandNo; //!< The command ID number 0x0406 + uint16_t commandNo; //!< The command ID number 0x0406 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_READ_RFREG //! @{ -#define CMD_READ_RFREG 0x0601 +#define CMD_READ_RFREG 0x0601 //! Read RF Core Hardware Register struct __RFC_STRUCT rfc_CMD_READ_RFREG_s { - uint16_t commandNo; //!< The command ID number 0x0601 - uint16_t address; //!< The offset from the start of the RF core HW register bank (0x40040000) - uint32_t value; //!< Returned value of the register + uint16_t commandNo; //!< The command ID number 0x0601 + uint16_t address; //!< The offset from the start of the RF core HW register bank (0x40040000) + uint32_t value; //!< Returned value of the register } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_ADD_DATA_ENTRY //! @{ -#define CMD_ADD_DATA_ENTRY 0x0005 +#define CMD_ADD_DATA_ENTRY 0x0005 //! Add Data Entry to Queue struct __RFC_STRUCT rfc_CMD_ADD_DATA_ENTRY_s { - uint16_t commandNo; //!< The command ID number 0x0005 - uint16_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to the queue structure to which the entry will be added - uint8_t* pEntry; //!< Pointer to the entry + uint16_t commandNo; //!< The command ID number 0x0005 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to which the entry will be added + uint8_t* pEntry; //!< Pointer to the entry } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_REMOVE_DATA_ENTRY //! @{ -#define CMD_REMOVE_DATA_ENTRY 0x0006 +#define CMD_REMOVE_DATA_ENTRY 0x0006 //! Remove First Data Entry from Queue struct __RFC_STRUCT rfc_CMD_REMOVE_DATA_ENTRY_s { - uint16_t commandNo; //!< The command ID number 0x0006 - uint16_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to the queue structure from which the entry will be removed - uint8_t* pEntry; //!< Pointer to the entry that was removed + uint16_t commandNo; //!< The command ID number 0x0006 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure from which the entry will be removed + uint8_t* pEntry; //!< Pointer to the entry that was removed } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_FLUSH_QUEUE //! @{ -#define CMD_FLUSH_QUEUE 0x0007 +#define CMD_FLUSH_QUEUE 0x0007 //! Flush Data Queue struct __RFC_STRUCT rfc_CMD_FLUSH_QUEUE_s { - uint16_t commandNo; //!< The command ID number 0x0007 - uint16_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed - uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed + uint16_t commandNo; //!< The command ID number 0x0007 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed + uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_CLEAR_RX //! @{ -#define CMD_CLEAR_RX 0x0008 +#define CMD_CLEAR_RX 0x0008 //! Clear all RX Queue Entries struct __RFC_STRUCT rfc_CMD_CLEAR_RX_s { - uint16_t commandNo; //!< The command ID number 0x0008 - uint16_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to the queue structure to be cleared + uint16_t commandNo; //!< The command ID number 0x0008 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to be cleared } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_REMOVE_PENDING_ENTRIES //! @{ -#define CMD_REMOVE_PENDING_ENTRIES 0x0009 +#define CMD_REMOVE_PENDING_ENTRIES 0x0009 //! Remove Pending Entries from Queue struct __RFC_STRUCT rfc_CMD_REMOVE_PENDING_ENTRIES_s { - uint16_t commandNo; //!< The command ID number 0x0009 - uint16_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed - uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed + uint16_t commandNo; //!< The command ID number 0x0009 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed + uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SET_RAT_CMP //! @{ -#define CMD_SET_RAT_CMP 0x000A +#define CMD_SET_RAT_CMP 0x000A //! Set Radio Timer Channel in Compare Mode struct __RFC_STRUCT rfc_CMD_SET_RAT_CMP_s { - uint16_t commandNo; //!< The command ID number 0x000A - uint8_t ratCh; //!< The radio timer channel number - uint8_t __dummy0; - ratmr_t compareTime; //!< The time at which the compare occurs + uint16_t commandNo; //!< The command ID number 0x000A + uint8_t ratCh; //!< The radio timer channel number + uint8_t __dummy0; + ratmr_t compareTime; //!< The time at which the compare occurs } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SET_RAT_CPT //! @{ -#define CMD_SET_RAT_CPT 0x0603 +#define CMD_SET_RAT_CPT 0x0603 //! Set Radio Timer Channel in Capture Mode struct __RFC_STRUCT rfc_CMD_SET_RAT_CPT_s { - uint16_t commandNo; //!< The command ID number 0x0603 - struct - { - uint16_t : 3; - uint16_t inputSrc: 5; //!< Input source indicator - uint16_t ratCh: 4; //!< The radio timer channel number - uint16_t bRepeated: 1; //!< \brief 0: Single capture mode
- //!< 1: Repeated capture mode - uint16_t inputMode: 2; //!< \brief Input mode:
- //!< 0: Capture on rising edge
- //!< 1: Capture on falling edge
- //!< 2: Capture on both edges
- //!< 3: Reserved - } config; + uint16_t commandNo; //!< The command ID number 0x0603 + struct + { + uint16_t : 3; + uint16_t inputSrc : 5; //!< Input source indicator + uint16_t ratCh : 4; //!< The radio timer channel number + uint16_t bRepeated : 1; //!< \brief 0: Single capture mode
+ //!< 1: Repeated capture mode + uint16_t inputMode : 2; //!< \brief Input mode:
+ //!< 0: Capture on rising edge
+ //!< 1: Capture on falling edge
+ //!< 2: Capture on both edges
+ //!< 3: Reserved + } config; } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_DISABLE_RAT_CH //! @{ -#define CMD_DISABLE_RAT_CH 0x0408 +#define CMD_DISABLE_RAT_CH 0x0408 //! Disable Radio Timer Channel struct __RFC_STRUCT rfc_CMD_DISABLE_RAT_CH_s { - uint16_t commandNo; //!< The command ID number 0x0408 - uint8_t ratCh; //!< The radio timer channel number + uint16_t commandNo; //!< The command ID number 0x0408 + uint8_t ratCh; //!< The radio timer channel number } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SET_RAT_OUTPUT //! @{ -#define CMD_SET_RAT_OUTPUT 0x0604 +#define CMD_SET_RAT_OUTPUT 0x0604 //! Set Radio Timer Output to a Specified Mode struct __RFC_STRUCT rfc_CMD_SET_RAT_OUTPUT_s { - uint16_t commandNo; //!< The command ID number 0x0604 - struct - { - uint16_t : 2; - uint16_t outputSel: 3; //!< Output event indicator - uint16_t outputMode: 3; //!< \brief 0: Set output line low as default; and pulse on event. Duration of pulse is one RF Core clock period (ca. 41.67 ns).
- //!< 1: Set output line high on event
- //!< 2: Set output line low on event
- //!< 3: Toggle (invert) output line state on event
- //!< 4: Immediately set output line to low (does not change upon event)
- //!< 5: Immediately set output line to high (does not change upon event)
- //!< Others: Reserved - uint16_t ratCh: 4; //!< The radio timer channel number - } config; + uint16_t commandNo; //!< The command ID number 0x0604 + struct + { + uint16_t : 2; + uint16_t outputSel : 3; //!< Output event indicator + uint16_t outputMode : 3; //!< \brief 0: Set output line low as default; and pulse on event. Duration of pulse is one RF Core clock period (ca. 41.67 ns).
+ //!< 1: Set output line high on event
+ //!< 2: Set output line low on event
+ //!< 3: Toggle (invert) output line state on event
+ //!< 4: Immediately set output line to low (does not change upon event)
+ //!< 5: Immediately set output line to high (does not change upon event)
+ //!< Others: Reserved + uint16_t ratCh : 4; //!< The radio timer channel number + } config; } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_ARM_RAT_CH //! @{ -#define CMD_ARM_RAT_CH 0x0409 +#define CMD_ARM_RAT_CH 0x0409 //! Arm Radio Timer Channel struct __RFC_STRUCT rfc_CMD_ARM_RAT_CH_s { - uint16_t commandNo; //!< The command ID number 0x0409 - uint8_t ratCh; //!< The radio timer channel number + uint16_t commandNo; //!< The command ID number 0x0409 + uint8_t ratCh; //!< The radio timer channel number } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_DISARM_RAT_CH //! @{ -#define CMD_DISARM_RAT_CH 0x040A +#define CMD_DISARM_RAT_CH 0x040A //! Disarm Radio Timer Channel struct __RFC_STRUCT rfc_CMD_DISARM_RAT_CH_s { - uint16_t commandNo; //!< The command ID number 0x040A - uint8_t ratCh; //!< The radio timer channel number + uint16_t commandNo; //!< The command ID number 0x040A + uint8_t ratCh; //!< The radio timer channel number } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SET_TX_POWER //! @{ -#define CMD_SET_TX_POWER 0x0010 +#define CMD_SET_TX_POWER 0x0010 //! Set Transmit Power struct __RFC_STRUCT rfc_CMD_SET_TX_POWER_s { - uint16_t commandNo; //!< The command ID number 0x0010 - uint16_t txPower; //!< New TX power setting + uint16_t commandNo; //!< The command ID number 0x0010 + uint16_t txPower; //!< New TX power setting } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_UPDATE_FS //! @{ -#define CMD_UPDATE_FS 0x0011 +#define CMD_UPDATE_FS 0x0011 //! Set New Synthesizer Frequency without Recalibration struct __RFC_STRUCT rfc_CMD_UPDATE_FS_s { - uint16_t commandNo; //!< The command ID number 0x0011 - uint16_t __dummy0; - uint32_t __dummy1; - uint32_t __dummy2; - uint16_t __dummy3; - uint16_t frequency; //!< The frequency in MHz to tune to, compensated for LO divider setting - uint16_t fractFreq; //!< Fractional part of the frequency to tune to + uint16_t commandNo; //!< The command ID number 0x0011 + uint16_t __dummy0; + uint32_t __dummy1; + uint32_t __dummy2; + uint16_t __dummy3; + uint16_t frequency; //!< The frequency in MHz to tune to, compensated for LO divider setting + uint16_t fractFreq; //!< Fractional part of the frequency to tune to } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BUS_REQUEST //! @{ -#define CMD_BUS_REQUEST 0x040E +#define CMD_BUS_REQUEST 0x040E //! Request System Bus to be Availbale struct __RFC_STRUCT rfc_CMD_BUS_REQUEST_s { - uint16_t commandNo; //!< The command ID number 0x040E - uint8_t bSysBusNeeded; //!< \brief 0: System bus may sleep
- //!< 1: System bus access needed + uint16_t commandNo; //!< The command ID number 0x040E + uint8_t bSysBusNeeded; //!< \brief 0: System bus may sleep
+ //!< 1: System bus access needed } __RFC_STRUCT_ATTR; //! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_data_entry.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_data_entry.h index 137b7b4..d525f3d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_data_entry.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_data_entry.h @@ -1,56 +1,56 @@ /****************************************************************************** -* Filename: rf_data_entry.h -* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) -* Revision: 18052 -* -* Description: Definition of API for data exchange -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_data_entry.h + * Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) + * Revision: 18052 + * + * Description: Definition of API for data exchange + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __DATA_ENTRY_H #define __DATA_ENTRY_H #ifndef __RFC_STRUCT - #define __RFC_STRUCT +#define __RFC_STRUCT #endif #ifndef __RFC_STRUCT_ATTR - #if defined(__GNUC__) - #define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) - #elif defined(__TI_ARM__) - #define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) - #else - #define __RFC_STRUCT_ATTR - #endif +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__((aligned(4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__((__packed__, aligned(4))) +#else +#define __RFC_STRUCT_ATTR +#endif #endif //! \addtogroup rfc @@ -59,8 +59,8 @@ //! \addtogroup data_entry //! @{ -#include #include "rf_mailbox.h" +#include typedef struct __RFC_STRUCT rfc_dataEntry_s rfc_dataEntry_t; typedef struct __RFC_STRUCT rfc_dataEntryGeneral_s rfc_dataEntryGeneral_t; @@ -72,25 +72,25 @@ typedef struct __RFC_STRUCT rfc_dataEntryPartial_s rfc_dataEntryPartial_t; //! @{ struct __RFC_STRUCT rfc_dataEntry_s { - uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry - uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to - struct - { - uint8_t type: 2; //!< \brief Type of data entry structure
- //!< 0: General data entry
- //!< 1: Multi-element Rx entry
- //!< 2: Pointer entry
- //!< 3: Partial read Rx entry - uint8_t lenSz: 2; //!< \brief Size of length word in start of each Rx entry element
- //!< 0: No length indicator
- //!< 1: One byte length indicator
- //!< 2: Two bytes length indicator
- //!< 3: Reserved - uint8_t irqIntv: 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated - //!< by the radio CPU (0: 16 bytes) - } config; - uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
- //!< For other entries: Number of bytes following this length field + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct + { + uint8_t type : 2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz : 2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv : 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field } __RFC_STRUCT_ATTR; //! @} @@ -101,26 +101,26 @@ struct __RFC_STRUCT rfc_dataEntry_s struct __RFC_STRUCT rfc_dataEntryGeneral_s { - uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry - uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to - struct - { - uint8_t type: 2; //!< \brief Type of data entry structure
- //!< 0: General data entry
- //!< 1: Multi-element Rx entry
- //!< 2: Pointer entry
- //!< 3: Partial read Rx entry - uint8_t lenSz: 2; //!< \brief Size of length word in start of each Rx entry element
- //!< 0: No length indicator
- //!< 1: One byte length indicator
- //!< 2: Two bytes length indicator
- //!< 3: Reserved - uint8_t irqIntv: 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated - //!< by the radio CPU (0: 16 bytes) - } config; - uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
- //!< For other entries: Number of bytes following this length field - uint8_t data; //!< First byte of the data array to be received or transmitted + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct + { + uint8_t type : 2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz : 2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv : 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + uint8_t data; //!< First byte of the data array to be received or transmitted } __RFC_STRUCT_ATTR; //! @} @@ -131,28 +131,28 @@ struct __RFC_STRUCT rfc_dataEntryGeneral_s struct __RFC_STRUCT rfc_dataEntryMulti_s { - uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry - uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to - struct - { - uint8_t type: 2; //!< \brief Type of data entry structure
- //!< 0: General data entry
- //!< 1: Multi-element Rx entry
- //!< 2: Pointer entry
- //!< 3: Partial read Rx entry - uint8_t lenSz: 2; //!< \brief Size of length word in start of each Rx entry element
- //!< 0: No length indicator
- //!< 1: One byte length indicator
- //!< 2: Two bytes length indicator
- //!< 3: Reserved - uint8_t irqIntv: 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated - //!< by the radio CPU (0: 16 bytes) - } config; - uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
- //!< For other entries: Number of bytes following this length field - uint16_t numElements; //!< Number of entry elements committed in the entry - uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU - uint8_t rxData; //!< First byte of the data array of received data entry elements + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct + { + uint8_t type : 2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz : 2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv : 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + uint16_t numElements; //!< Number of entry elements committed in the entry + uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU + uint8_t rxData; //!< First byte of the data array of received data entry elements } __RFC_STRUCT_ATTR; //! @} @@ -163,26 +163,26 @@ struct __RFC_STRUCT rfc_dataEntryMulti_s struct __RFC_STRUCT rfc_dataEntryPointer_s { - uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry - uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to - struct - { - uint8_t type: 2; //!< \brief Type of data entry structure
- //!< 0: General data entry
- //!< 1: Multi-element Rx entry
- //!< 2: Pointer entry
- //!< 3: Partial read Rx entry - uint8_t lenSz: 2; //!< \brief Size of length word in start of each Rx entry element
- //!< 0: No length indicator
- //!< 1: One byte length indicator
- //!< 2: Two bytes length indicator
- //!< 3: Reserved - uint8_t irqIntv: 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated - //!< by the radio CPU (0: 16 bytes) - } config; - uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
- //!< For other entries: Number of bytes following this length field - uint8_t* pData; //!< Pointer to data buffer of data to be received ro transmitted + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct + { + uint8_t type : 2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz : 2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv : 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + uint8_t* pData; //!< Pointer to data buffer of data to be received ro transmitted } __RFC_STRUCT_ATTR; //! @} @@ -193,34 +193,34 @@ struct __RFC_STRUCT rfc_dataEntryPointer_s struct __RFC_STRUCT rfc_dataEntryPartial_s { - uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry - uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to - struct - { - uint8_t type: 2; //!< \brief Type of data entry structure
- //!< 0: General data entry
- //!< 1: Multi-element Rx entry
- //!< 2: Pointer entry
- //!< 3: Partial read Rx entry - uint8_t lenSz: 2; //!< \brief Size of length word in start of each Rx entry element
- //!< 0: No length indicator
- //!< 1: One byte length indicator
- //!< 2: Two bytes length indicator
- //!< 3: Reserved - uint8_t irqIntv: 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated - //!< by the radio CPU (0: 16 bytes) - } config; - uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
- //!< For other entries: Number of bytes following this length field - struct - { - uint16_t numElements: 13; //!< Number of entry elements committed in the entry - uint16_t bEntryOpen: 1; //!< 1 if the entry contains an element that is still open for appending data - uint16_t bFirstCont: 1; //!< 1 if the first element is a continuation of the last packet from the previous entry - uint16_t bLastCont: 1; //!< 1 if the packet in the last element continues in the next entry - } pktStatus; - uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU - uint8_t rxData; //!< First byte of the data array of received data entry elements + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct + { + uint8_t type : 2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz : 2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv : 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + struct + { + uint16_t numElements : 13; //!< Number of entry elements committed in the entry + uint16_t bEntryOpen : 1; //!< 1 if the entry contains an element that is still open for appending data + uint16_t bFirstCont : 1; //!< 1 if the first element is a continuation of the last packet from the previous entry + uint16_t bLastCont : 1; //!< 1 if the packet in the last element continues in the next entry + } pktStatus; + uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU + uint8_t rxData; //!< First byte of the data array of received data entry elements } __RFC_STRUCT_ATTR; //! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_hs_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_hs_cmd.h index 78390e4..d180bc5 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_hs_cmd.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_hs_cmd.h @@ -1,56 +1,56 @@ /****************************************************************************** -* Filename: rf_hs_cmd.h -* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) -* Revision: 18052 -* -* Description: CC13x0 API for high-speed mode commands -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_hs_cmd.h + * Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) + * Revision: 18052 + * + * Description: CC13x0 API for high-speed mode commands + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HS_CMD_H #define __HS_CMD_H #ifndef __RFC_STRUCT - #define __RFC_STRUCT +#define __RFC_STRUCT #endif #ifndef __RFC_STRUCT_ATTR - #if defined(__GNUC__) - #define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) - #elif defined(__TI_ARM__) - #define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) - #else - #define __RFC_STRUCT_ATTR - #endif +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__((aligned(4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__((__packed__, aligned(4))) +#else +#define __RFC_STRUCT_ATTR +#endif #endif //! \addtogroup rfc @@ -59,9 +59,9 @@ //! \addtogroup hs_cmd //! @{ -#include -#include "rf_mailbox.h" #include "rf_common_cmd.h" +#include "rf_mailbox.h" +#include typedef struct __RFC_STRUCT rfc_CMD_HS_TX_s rfc_CMD_HS_TX_t; typedef struct __RFC_STRUCT rfc_CMD_HS_RX_s rfc_CMD_HS_RX_t; @@ -70,114 +70,114 @@ typedef struct __RFC_STRUCT rfc_hsRxStatus_s rfc_hsRxStatus_t; //! \addtogroup CMD_HS_TX //! @{ -#define CMD_HS_TX 0x3841 +#define CMD_HS_TX 0x3841 //! High-Speed Transmit Command struct __RFC_STRUCT rfc_CMD_HS_TX_s { - uint16_t commandNo; //!< The command ID number 0x3841 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bUseCrc: 1; //!< \brief 0: Do not append CRC
- //!< 1: Append CRC - uint8_t bVarLen: 1; //!< \brief 0: Fixed length
- //!< 1: Transmit length as first half-word - uint8_t bCheckQAtEnd: 1; //!< \brief 0: Always end with HS_DONE_OK when packet has been transmitted
- //!< 1: Check if Tx queue is empty when packet has been transmitted - } pktConf; - uint8_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to Tx queue + uint16_t commandNo; //!< The command ID number 0x3841 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bUseCrc : 1; //!< \brief 0: Do not append CRC
+ //!< 1: Append CRC + uint8_t bVarLen : 1; //!< \brief 0: Fixed length
+ //!< 1: Transmit length as first half-word + uint8_t bCheckQAtEnd : 1; //!< \brief 0: Always end with HS_DONE_OK when packet has been transmitted
+ //!< 1: Check if Tx queue is empty when packet has been transmitted + } pktConf; + uint8_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to Tx queue } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_HS_RX //! @{ -#define CMD_HS_RX 0x3842 +#define CMD_HS_RX 0x3842 //! High-Speed Receive Command struct __RFC_STRUCT rfc_CMD_HS_RX_s { - uint16_t commandNo; //!< The command ID number 0x3842 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bUseCrc: 1; //!< \brief 0: Do not receive or check CRC
- //!< 1: Receive and check CRC - uint8_t bVarLen: 1; //!< \brief 0: Fixed length
- //!< 1: Receive length as first byte - uint8_t bRepeatOk: 1; //!< \brief 0: End operation after receiving a packet correctly
- //!< 1: Go back to sync search after receiving a packet correctly - uint8_t bRepeatNok: 1; //!< \brief 0: End operation after receiving a packet with CRC error
- //!< 1: Go back to sync search after receiving a packet with CRC error - uint8_t addressMode: 2; //!< \brief 0: No address check
- //!< 1: Accept address0 and address1
- //!< 2: Accept address0, address1, and 0x0000
- //!< 3: Accept address0, address1, 0x0000, and 0xFFFF - } pktConf; - struct - { - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bIncludeLen: 1; //!< If 1, include the received length field in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise 3scard it - uint8_t bAppendStatus: 1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConf; - uint16_t maxPktLen; //!< Packet length for fixed length; maximum packet length for variable length - uint16_t address0; //!< Address - uint16_t address1; //!< Address (set equal to address0 to accept only one address) - uint8_t __dummy0; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - ratmr_t endTime; //!< Time used together with endTrigger for ending the operation - dataQueue_t* pQueue; //!< Pointer to receive queue - rfc_hsRxOutput_t* pOutput; //!< Pointer to output structure + uint16_t commandNo; //!< The command ID number 0x3842 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bUseCrc : 1; //!< \brief 0: Do not receive or check CRC
+ //!< 1: Receive and check CRC + uint8_t bVarLen : 1; //!< \brief 0: Fixed length
+ //!< 1: Receive length as first byte + uint8_t bRepeatOk : 1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok : 1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t addressMode : 2; //!< \brief 0: No address check
+ //!< 1: Accept address0 and address1
+ //!< 2: Accept address0, address1, and 0x0000
+ //!< 3: Accept address0, address1, 0x0000, and 0xFFFF + } pktConf; + struct + { + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bIncludeLen : 1; //!< If 1, include the received length field in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise 3scard it + uint8_t bAppendStatus : 1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConf; + uint16_t maxPktLen; //!< Packet length for fixed length; maximum packet length for variable length + uint16_t address0; //!< Address + uint16_t address1; //!< Address (set equal to address0 to accept only one address) + uint8_t __dummy0; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + dataQueue_t* pQueue; //!< Pointer to receive queue + rfc_hsRxOutput_t* pOutput; //!< Pointer to output structure } __RFC_STRUCT_ATTR; //! @} @@ -188,12 +188,12 @@ struct __RFC_STRUCT rfc_CMD_HS_RX_s struct __RFC_STRUCT rfc_hsRxOutput_s { - uint16_t nRxOk; //!< Number of packets that have been received with CRC OK - uint16_t nRxNok; //!< Number of packets that have been received with CRC error - uint16_t nRxAborted; //!< Number of packets not received due to illegal length or address mismatch - uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space - int8_t lastRssi; //!< RSSI of last received packet - ratmr_t timeStamp; //!< Time stamp of last received packet + uint16_t nRxOk; //!< Number of packets that have been received with CRC OK + uint16_t nRxNok; //!< Number of packets that have been received with CRC error + uint16_t nRxAborted; //!< Number of packets not received due to illegal length or address mismatch + uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< RSSI of last received packet + ratmr_t timeStamp; //!< Time stamp of last received packet } __RFC_STRUCT_ATTR; //! @} @@ -204,16 +204,16 @@ struct __RFC_STRUCT rfc_hsRxOutput_s struct __RFC_STRUCT rfc_hsRxStatus_s { - struct - { - uint16_t rssi: 8; //!< RSSI of the received packet in dBm (signed) - uint16_t bCrcErr: 1; //!< \brief 0: Packet received OK
- //!< 1: Packet received with CRC error - uint16_t addressInd: 2; //!< \brief 0: Received address0 (or no address check)
- //!< 1: Received address1
- //!< 2: Received address 0x0000
- //!< 3: Received address 0xFFFF - } status; + struct + { + uint16_t rssi : 8; //!< RSSI of the received packet in dBm (signed) + uint16_t bCrcErr : 1; //!< \brief 0: Packet received OK
+ //!< 1: Packet received with CRC error + uint16_t addressInd : 2; //!< \brief 0: Received address0 (or no address check)
+ //!< 1: Received address1
+ //!< 2: Received address 0x0000
+ //!< 3: Received address 0xFFFF + } status; } __RFC_STRUCT_ATTR; //! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_hs_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_hs_mailbox.h index 2ad5bcd..7528634 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_hs_mailbox.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_hs_mailbox.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_hs_mailbox.h -* Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) -* Revision: 18032 -* -* Description: Definitions for high-speed mode radio interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_hs_mailbox.h + * Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) + * Revision: 18032 + * + * Description: Definitions for high-speed mode radio interface + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _HS_MAILBOX_H #define _HS_MAILBOX_H @@ -43,22 +43,22 @@ ///@{ /// \name Operation finished normally ///@{ -#define HS_DONE_OK 0x3440 ///< Operation ended normally -#define HS_DONE_RXTIMEOUT 0x3441 ///< Operation stopped after end trigger while waiting for sync -#define HS_DONE_RXERR 0x3442 ///< Operation ended after CRC error -#define HS_DONE_TXBUF 0x3443 ///< Tx queue was empty at start of operation -#define HS_DONE_ENDED 0x3444 ///< Operation stopped after end trigger during reception -#define HS_DONE_STOPPED 0x3445 ///< Operation stopped after stop command -#define HS_DONE_ABORT 0x3446 ///< Operation aborted by abort command +#define HS_DONE_OK 0x3440 ///< Operation ended normally +#define HS_DONE_RXTIMEOUT 0x3441 ///< Operation stopped after end trigger while waiting for sync +#define HS_DONE_RXERR 0x3442 ///< Operation ended after CRC error +#define HS_DONE_TXBUF 0x3443 ///< Tx queue was empty at start of operation +#define HS_DONE_ENDED 0x3444 ///< Operation stopped after end trigger during reception +#define HS_DONE_STOPPED 0x3445 ///< Operation stopped after stop command +#define HS_DONE_ABORT 0x3446 ///< Operation aborted by abort command ///@} /// \name Operation finished with error ///@{ -#define HS_ERROR_PAR 0x3840 ///< Illegal parameter -#define HS_ERROR_RXBUF 0x3841 ///< No available Rx buffer at the start of a packet -#define HS_ERROR_NO_SETUP 0x3842 ///< Radio was not set up in a compatible mode -#define HS_ERROR_NO_FS 0x3843 ///< Synth was not programmed when running Rx or Tx -#define HS_ERROR_RXOVF 0x3844 ///< Rx overflow observed during operation -#define HS_ERROR_TXUNF 0x3845 ///< Tx underflow observed during operation +#define HS_ERROR_PAR 0x3840 ///< Illegal parameter +#define HS_ERROR_RXBUF 0x3841 ///< No available Rx buffer at the start of a packet +#define HS_ERROR_NO_SETUP 0x3842 ///< Radio was not set up in a compatible mode +#define HS_ERROR_NO_FS 0x3843 ///< Synth was not programmed when running Rx or Tx +#define HS_ERROR_RXOVF 0x3844 ///< Rx overflow observed during operation +#define HS_ERROR_TXUNF 0x3845 ///< Tx underflow observed during operation ///@} ///@} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_mailbox.h index 043fc4d..7e18556 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_mailbox.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_mailbox.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_mailbox.h -* Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) -* Revision: 18032 -* -* Description: Definitions for interface between system and radio CPU -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_mailbox.h + * Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) + * Revision: 18032 + * + * Description: Definitions for interface between system and radio CPU + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _MAILBOX_H #define _MAILBOX_H @@ -42,125 +42,115 @@ #include #include - /// \name RF mode values /// Defines used to indicate mode of operation to radio core. ///@{ -#define RF_MODE_PROPRIETARY_SUB_1 0x00 -#define RF_MODE_BLE 0x01 -#define RF_MODE_IEEE_15_4 0x02 -#define RF_MODE_PROPRIETARY_2_4 0x03 -#define RF_MODE_PROPRIETARY RF_MODE_PROPRIETARY_2_4 -#define RF_MODE_MULTIPLE 0x05 +#define RF_MODE_PROPRIETARY_SUB_1 0x00 +#define RF_MODE_BLE 0x01 +#define RF_MODE_IEEE_15_4 0x02 +#define RF_MODE_PROPRIETARY_2_4 0x03 +#define RF_MODE_PROPRIETARY RF_MODE_PROPRIETARY_2_4 +#define RF_MODE_MULTIPLE 0x05 ///@} - /// Type definition for RAT typedef uint32_t ratmr_t; - - /// Type definition for a data queue typedef struct { - uint8_t* pCurrEntry; ///< Pointer to the data queue entry to be used, NULL for an empty queue - uint8_t* pLastEntry; ///< Pointer to the last entry in the queue, NULL for a circular queue + uint8_t* pCurrEntry; ///< Pointer to the data queue entry to be used, NULL for an empty queue + uint8_t* pLastEntry; ///< Pointer to the last entry in the queue, NULL for a circular queue } dataQueue_t; - - /// \name CPE interrupt definitions /// Interrupt masks for the CPE interrupt in RDBELL. ///@{ -#define IRQN_COMMAND_DONE 0 ///< Radio operation command finished -#define IRQN_LAST_COMMAND_DONE 1 ///< Last radio operation command in a chain finished -#define IRQN_FG_COMMAND_DONE 2 ///< FG level Radio operation command finished -#define IRQN_LAST_FG_COMMAND_DONE 3 ///< Last FG level radio operation command in a chain finished -#define IRQN_TX_DONE 4 ///< Packet transmitted -#define IRQN_TX_ACK 5 ///< ACK packet transmitted -#define IRQN_TX_CTRL 6 ///< Control packet transmitted -#define IRQN_TX_CTRL_ACK 7 ///< Acknowledgement received on a transmitted control packet -#define IRQN_TX_CTRL_ACK_ACK 8 ///< Acknowledgement received on a transmitted control packet, and acknowledgement transmitted for that packet -#define IRQN_TX_RETRANS 9 ///< Packet retransmitted -#define IRQN_TX_ENTRY_DONE 10 ///< Tx queue data entry state changed to Finished -#define IRQN_TX_BUFFER_CHANGED 11 ///< A buffer change is complete -#define IRQN_RX_OK 16 ///< Packet received with CRC OK, payload, and not to be ignored -#define IRQN_RX_NOK 17 ///< Packet received with CRC error -#define IRQN_RX_IGNORED 18 ///< Packet received with CRC OK, but to be ignored -#define IRQN_RX_EMPTY 19 ///< Packet received with CRC OK, not to be ignored, no payload -#define IRQN_RX_CTRL 20 ///< Control packet received with CRC OK, not to be ignored -#define IRQN_RX_CTRL_ACK 21 ///< Control packet received with CRC OK, not to be ignored, then ACK sent -#define IRQN_RX_BUF_FULL 22 ///< Packet received that did not fit in the Rx queue -#define IRQN_RX_ENTRY_DONE 23 ///< Rx queue data entry changing state to Finished -#define IRQN_RX_DATA_WRITTEN 24 ///< Data written to partial read Rx buffer -#define IRQN_RX_N_DATA_WRITTEN 25 ///< Specified number of bytes written to partial read Rx buffer -#define IRQN_RX_ABORTED 26 ///< Packet reception stopped before packet was done -#define IRQN_RX_COLLISION_DETECTED 27 ///< A collision was indicated during packet reception -#define IRQN_SYNTH_NO_LOCK 28 ///< The synth has gone out of lock after calibration -#define IRQN_MODULES_UNLOCKED 29 ///< As part of the boot process, the CM0 has opened access to RF core modules and memories -#define IRQN_BOOT_DONE 30 ///< The RF core CPU boot is finished +#define IRQN_COMMAND_DONE 0 ///< Radio operation command finished +#define IRQN_LAST_COMMAND_DONE 1 ///< Last radio operation command in a chain finished +#define IRQN_FG_COMMAND_DONE 2 ///< FG level Radio operation command finished +#define IRQN_LAST_FG_COMMAND_DONE 3 ///< Last FG level radio operation command in a chain finished +#define IRQN_TX_DONE 4 ///< Packet transmitted +#define IRQN_TX_ACK 5 ///< ACK packet transmitted +#define IRQN_TX_CTRL 6 ///< Control packet transmitted +#define IRQN_TX_CTRL_ACK 7 ///< Acknowledgement received on a transmitted control packet +#define IRQN_TX_CTRL_ACK_ACK 8 ///< Acknowledgement received on a transmitted control packet, and acknowledgement transmitted for that packet +#define IRQN_TX_RETRANS 9 ///< Packet retransmitted +#define IRQN_TX_ENTRY_DONE 10 ///< Tx queue data entry state changed to Finished +#define IRQN_TX_BUFFER_CHANGED 11 ///< A buffer change is complete +#define IRQN_RX_OK 16 ///< Packet received with CRC OK, payload, and not to be ignored +#define IRQN_RX_NOK 17 ///< Packet received with CRC error +#define IRQN_RX_IGNORED 18 ///< Packet received with CRC OK, but to be ignored +#define IRQN_RX_EMPTY 19 ///< Packet received with CRC OK, not to be ignored, no payload +#define IRQN_RX_CTRL 20 ///< Control packet received with CRC OK, not to be ignored +#define IRQN_RX_CTRL_ACK 21 ///< Control packet received with CRC OK, not to be ignored, then ACK sent +#define IRQN_RX_BUF_FULL 22 ///< Packet received that did not fit in the Rx queue +#define IRQN_RX_ENTRY_DONE 23 ///< Rx queue data entry changing state to Finished +#define IRQN_RX_DATA_WRITTEN 24 ///< Data written to partial read Rx buffer +#define IRQN_RX_N_DATA_WRITTEN 25 ///< Specified number of bytes written to partial read Rx buffer +#define IRQN_RX_ABORTED 26 ///< Packet reception stopped before packet was done +#define IRQN_RX_COLLISION_DETECTED 27 ///< A collision was indicated during packet reception +#define IRQN_SYNTH_NO_LOCK 28 ///< The synth has gone out of lock after calibration +#define IRQN_MODULES_UNLOCKED 29 ///< As part of the boot process, the CM0 has opened access to RF core modules and memories +#define IRQN_BOOT_DONE 30 ///< The RF core CPU boot is finished -#define IRQN_INTERNAL_ERROR 31 ///< Internal error observed +#define IRQN_INTERNAL_ERROR 31 ///< Internal error observed -#define IRQ_COMMAND_DONE (1U << IRQN_COMMAND_DONE) -#define IRQ_LAST_COMMAND_DONE (1U << IRQN_LAST_COMMAND_DONE) -#define IRQ_FG_COMMAND_DONE (1U << IRQN_FG_COMMAND_DONE) -#define IRQ_LAST_FG_COMMAND_DONE (1U << IRQN_LAST_FG_COMMAND_DONE) +#define IRQ_COMMAND_DONE (1U << IRQN_COMMAND_DONE) +#define IRQ_LAST_COMMAND_DONE (1U << IRQN_LAST_COMMAND_DONE) +#define IRQ_FG_COMMAND_DONE (1U << IRQN_FG_COMMAND_DONE) +#define IRQ_LAST_FG_COMMAND_DONE (1U << IRQN_LAST_FG_COMMAND_DONE) -#define IRQ_TX_DONE (1U << IRQN_TX_DONE) -#define IRQ_TX_ACK (1U << IRQN_TX_ACK) -#define IRQ_TX_CTRL (1U << IRQN_TX_CTRL) -#define IRQ_TX_CTRL_ACK (1U << IRQN_TX_CTRL_ACK) -#define IRQ_TX_CTRL_ACK_ACK (1U << IRQN_TX_CTRL_ACK_ACK) -#define IRQ_TX_RETRANS (1U << IRQN_TX_RETRANS) +#define IRQ_TX_DONE (1U << IRQN_TX_DONE) +#define IRQ_TX_ACK (1U << IRQN_TX_ACK) +#define IRQ_TX_CTRL (1U << IRQN_TX_CTRL) +#define IRQ_TX_CTRL_ACK (1U << IRQN_TX_CTRL_ACK) +#define IRQ_TX_CTRL_ACK_ACK (1U << IRQN_TX_CTRL_ACK_ACK) +#define IRQ_TX_RETRANS (1U << IRQN_TX_RETRANS) -#define IRQ_TX_ENTRY_DONE (1U << IRQN_TX_ENTRY_DONE) -#define IRQ_TX_BUFFER_CHANGED (1U << IRQN_TX_BUFFER_CHANGED) +#define IRQ_TX_ENTRY_DONE (1U << IRQN_TX_ENTRY_DONE) +#define IRQ_TX_BUFFER_CHANGED (1U << IRQN_TX_BUFFER_CHANGED) -#define IRQ_RX_OK (1U << IRQN_RX_OK) -#define IRQ_RX_NOK (1U << IRQN_RX_NOK) -#define IRQ_RX_IGNORED (1U << IRQN_RX_IGNORED) -#define IRQ_RX_EMPTY (1U << IRQN_RX_EMPTY) -#define IRQ_RX_CTRL (1U << IRQN_RX_CTRL) -#define IRQ_RX_CTRL_ACK (1U << IRQN_RX_CTRL_ACK) -#define IRQ_RX_BUF_FULL (1U << IRQN_RX_BUF_FULL) -#define IRQ_RX_ENTRY_DONE (1U << IRQN_RX_ENTRY_DONE) -#define IRQ_RX_DATA_WRITTEN (1U << IRQN_RX_DATA_WRITTEN) -#define IRQ_RX_N_DATA_WRITTEN (1U << IRQN_RX_N_DATA_WRITTEN) -#define IRQ_RX_ABORTED (1U << IRQN_RX_ABORTED) -#define IRQ_RX_COLLISION_DETECTED (1U << IRQN_RX_COLLISION_DETECTED) -#define IRQ_SYNTH_NO_LOCK (1U << IRQN_SYNTH_NO_LOCK) -#define IRQ_MODULES_UNLOCKED (1U << IRQN_MODULES_UNLOCKED) -#define IRQ_BOOT_DONE (1U << IRQN_BOOT_DONE) -#define IRQ_INTERNAL_ERROR (1U << IRQN_INTERNAL_ERROR) +#define IRQ_RX_OK (1U << IRQN_RX_OK) +#define IRQ_RX_NOK (1U << IRQN_RX_NOK) +#define IRQ_RX_IGNORED (1U << IRQN_RX_IGNORED) +#define IRQ_RX_EMPTY (1U << IRQN_RX_EMPTY) +#define IRQ_RX_CTRL (1U << IRQN_RX_CTRL) +#define IRQ_RX_CTRL_ACK (1U << IRQN_RX_CTRL_ACK) +#define IRQ_RX_BUF_FULL (1U << IRQN_RX_BUF_FULL) +#define IRQ_RX_ENTRY_DONE (1U << IRQN_RX_ENTRY_DONE) +#define IRQ_RX_DATA_WRITTEN (1U << IRQN_RX_DATA_WRITTEN) +#define IRQ_RX_N_DATA_WRITTEN (1U << IRQN_RX_N_DATA_WRITTEN) +#define IRQ_RX_ABORTED (1U << IRQN_RX_ABORTED) +#define IRQ_RX_COLLISION_DETECTED (1U << IRQN_RX_COLLISION_DETECTED) +#define IRQ_SYNTH_NO_LOCK (1U << IRQN_SYNTH_NO_LOCK) +#define IRQ_MODULES_UNLOCKED (1U << IRQN_MODULES_UNLOCKED) +#define IRQ_BOOT_DONE (1U << IRQN_BOOT_DONE) +#define IRQ_INTERNAL_ERROR (1U << IRQN_INTERNAL_ERROR) ///@} - - /// \name CMDSTA values /// Values returned in result byte of CMDSTA ///@{ -#define CMDSTA_Pending 0x00 ///< The command has not yet been parsed -#define CMDSTA_Done 0x01 ///< Command successfully parsed +#define CMDSTA_Pending 0x00 ///< The command has not yet been parsed +#define CMDSTA_Done 0x01 ///< Command successfully parsed -#define CMDSTA_IllegalPointer 0x81 ///< The pointer signaled in CMDR is not valid -#define CMDSTA_UnknownCommand 0x82 ///< The command number in the command structure is unknown -#define CMDSTA_UnknownDirCommand 0x83 ///< The command number for a direct command is unknown, or the +#define CMDSTA_IllegalPointer 0x81 ///< The pointer signaled in CMDR is not valid +#define CMDSTA_UnknownCommand 0x82 ///< The command number in the command structure is unknown +#define CMDSTA_UnknownDirCommand 0x83 ///< The command number for a direct command is unknown, or the ///< command is not a direct command -#define CMDSTA_ContextError 0x85 ///< An immediate or direct command was issued in a context +#define CMDSTA_ContextError 0x85 ///< An immediate or direct command was issued in a context ///< where it is not supported -#define CMDSTA_SchedulingError 0x86 ///< A radio operation command was attempted to be scheduled +#define CMDSTA_SchedulingError 0x86 ///< A radio operation command was attempted to be scheduled ///< while another operation was already running in the RF core -#define CMDSTA_ParError 0x87 ///< There were errors in the command parameters that are parsed +#define CMDSTA_ParError 0x87 ///< There were errors in the command parameters that are parsed ///< on submission. -#define CMDSTA_QueueError 0x88 ///< An operation on a data entry queue was attempted that was +#define CMDSTA_QueueError 0x88 ///< An operation on a data entry queue was attempted that was ///< not supported by the queue in its current state -#define CMDSTA_QueueBusy 0x89 ///< An operation on a data entry was attempted while that entry +#define CMDSTA_QueueBusy 0x89 ///< An operation on a data entry was attempted while that entry ///< was busy ///@} - - /// \name Macros for sending direct commands ///@{ /// Direct command with no parameter @@ -174,8 +164,6 @@ typedef struct ///@} - - /// \name Definitions for trigger types ///@{ #define TRIG_NOW 0 ///< Triggers immediately @@ -193,63 +181,59 @@ typedef struct ///< trigger happened in the past ///@} - /// \name Definitions for conditional execution ///@{ -#define COND_ALWAYS 0 ///< Always run next command (except in case of Abort) -#define COND_NEVER 1 ///< Never run next command -#define COND_STOP_ON_FALSE 2 ///< Run next command if this command returned True, stop if it returned +#define COND_ALWAYS 0 ///< Always run next command (except in case of Abort) +#define COND_NEVER 1 ///< Never run next command +#define COND_STOP_ON_FALSE 2 ///< Run next command if this command returned True, stop if it returned ///< False -#define COND_STOP_ON_TRUE 3 ///< Stop if this command returned True, run next command if it returned +#define COND_STOP_ON_TRUE 3 ///< Stop if this command returned True, run next command if it returned ///< False -#define COND_SKIP_ON_FALSE 4 ///< Run next command if this command returned True, skip a number of +#define COND_SKIP_ON_FALSE 4 ///< Run next command if this command returned True, skip a number of ///< commands if it returned False -#define COND_SKIP_ON_TRUE 5 ///< Skip a number of commands if this command returned True, run next +#define COND_SKIP_ON_TRUE 5 ///< Skip a number of commands if this command returned True, run next ///< command if it returned False ///@} - - /// \name Radio operation status ///@{ /// \name Operation not finished ///@{ -#define IDLE 0x0000 ///< Operation not started -#define PENDING 0x0001 ///< Start of command is pending -#define ACTIVE 0x0002 ///< Running -#define SKIPPED 0x0003 ///< Operation skipped due to condition in another command +#define IDLE 0x0000 ///< Operation not started +#define PENDING 0x0001 ///< Start of command is pending +#define ACTIVE 0x0002 ///< Running +#define SKIPPED 0x0003 ///< Operation skipped due to condition in another command ///@} /// \name Operation finished normally ///@{ -#define DONE_OK 0x0400 ///< Operation ended normally -#define DONE_COUNTDOWN 0x0401 ///< Counter reached zero -#define DONE_RXERR 0x0402 ///< Operation ended with CRC error -#define DONE_TIMEOUT 0x0403 ///< Operation ended with timeout -#define DONE_STOPPED 0x0404 ///< Operation stopped after CMD_STOP command -#define DONE_ABORT 0x0405 ///< Operation aborted by CMD_ABORT command -#define DONE_FAILED 0x0406 ///< Scheduled immediate command failed +#define DONE_OK 0x0400 ///< Operation ended normally +#define DONE_COUNTDOWN 0x0401 ///< Counter reached zero +#define DONE_RXERR 0x0402 ///< Operation ended with CRC error +#define DONE_TIMEOUT 0x0403 ///< Operation ended with timeout +#define DONE_STOPPED 0x0404 ///< Operation stopped after CMD_STOP command +#define DONE_ABORT 0x0405 ///< Operation aborted by CMD_ABORT command +#define DONE_FAILED 0x0406 ///< Scheduled immediate command failed ///@} /// \name Operation finished with error ///@{ -#define ERROR_PAST_START 0x0800 ///< The start trigger occurred in the past -#define ERROR_START_TRIG 0x0801 ///< Illegal start trigger parameter -#define ERROR_CONDITION 0x0802 ///< Illegal condition for next operation -#define ERROR_PAR 0x0803 ///< Error in a command specific parameter -#define ERROR_POINTER 0x0804 ///< Invalid pointer to next operation -#define ERROR_CMDID 0x0805 ///< Next operation has a command ID that is undefined or not a radio +#define ERROR_PAST_START 0x0800 ///< The start trigger occurred in the past +#define ERROR_START_TRIG 0x0801 ///< Illegal start trigger parameter +#define ERROR_CONDITION 0x0802 ///< Illegal condition for next operation +#define ERROR_PAR 0x0803 ///< Error in a command specific parameter +#define ERROR_POINTER 0x0804 ///< Invalid pointer to next operation +#define ERROR_CMDID 0x0805 ///< Next operation has a command ID that is undefined or not a radio ///< operation command -#define ERROR_WRONG_BG 0x0806 ///< FG level command not compatible with running BG level command -#define ERROR_NO_SETUP 0x0807 ///< Operation using Rx or Tx attemted without CMD_RADIO_SETUP -#define ERROR_NO_FS 0x0808 ///< Operation using Rx or Tx attemted without frequency synth configured -#define ERROR_SYNTH_PROG 0x0809 ///< Synthesizer calibration failed -#define ERROR_TXUNF 0x080A ///< Tx underflow observed -#define ERROR_RXOVF 0x080B ///< Rx overflow observed -#define ERROR_NO_RX 0x080C ///< Attempted to access data from Rx when no such data was yet received -#define ERROR_PENDING 0x080D ///< Command submitted in the future with another command at different level pending +#define ERROR_WRONG_BG 0x0806 ///< FG level command not compatible with running BG level command +#define ERROR_NO_SETUP 0x0807 ///< Operation using Rx or Tx attemted without CMD_RADIO_SETUP +#define ERROR_NO_FS 0x0808 ///< Operation using Rx or Tx attemted without frequency synth configured +#define ERROR_SYNTH_PROG 0x0809 ///< Synthesizer calibration failed +#define ERROR_TXUNF 0x080A ///< Tx underflow observed +#define ERROR_RXOVF 0x080B ///< Rx overflow observed +#define ERROR_NO_RX 0x080C ///< Attempted to access data from Rx when no such data was yet received +#define ERROR_PENDING 0x080D ///< Command submitted in the future with another command at different level pending ///@} ///@} - /// \name Data entry types ///@{ #define DATA_ENTRY_TYPE_GEN 0 ///< General type: Tx entry or single element Rx entry @@ -258,38 +242,34 @@ typedef struct #define DATA_ENTRY_TYPE_PARTIAL 3 ///< Partial read entry type ///@ - /// \name Data entry statuses ///@{ -#define DATA_ENTRY_PENDING 0 ///< Entry not yet used -#define DATA_ENTRY_ACTIVE 1 ///< Entry in use by radio CPU -#define DATA_ENTRY_BUSY 2 ///< Entry being updated -#define DATA_ENTRY_FINISHED 3 ///< Radio CPU is finished accessing the entry -#define DATA_ENTRY_UNFINISHED 4 ///< Radio CPU is finished accessing the entry, but packet could not be finished +#define DATA_ENTRY_PENDING 0 ///< Entry not yet used +#define DATA_ENTRY_ACTIVE 1 ///< Entry in use by radio CPU +#define DATA_ENTRY_BUSY 2 ///< Entry being updated +#define DATA_ENTRY_FINISHED 3 ///< Radio CPU is finished accessing the entry +#define DATA_ENTRY_UNFINISHED 4 ///< Radio CPU is finished accessing the entry, but packet could not be finished ///@} - - /// \name Macros for RF register override ///@{ /// Macro for ADI half-size value-mask combination #define ADI_VAL_MASK(addr, mask, value) \ - (((addr) & 1) ? (((mask) & 0x0F) | (((value) & 0x0F) << 4)) : \ - ((((mask) & 0x0F) << 4) | ((value) & 0x0F))) + (((addr) & 1) ? (((mask) & 0x0F) | (((value) & 0x0F) << 4)) : ((((mask) & 0x0F) << 4) | ((value) & 0x0F))) /// 32-bit write of 16-bit value -#define HW_REG_OVERRIDE(addr, val) ((((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(val) << 16)) +#define HW_REG_OVERRIDE(addr, val) ((((uintptr_t)(addr)) & 0xFFFC) | ((uint32_t)(val) << 16)) /// ADI register, full-size write #define ADI_REG_OVERRIDE(adiNo, addr, val) (2 | ((uint32_t)(val) << 16) | \ - (((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31)) + (((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31)) /// 2 ADI registers, full-size write -#define ADI_2REG_OVERRIDE(adiNo, addr, val, addr2, val2) \ +#define ADI_2REG_OVERRIDE(adiNo, addr, val, addr2, val2) \ (2 | ((uint32_t)(val2) << 2) | (((addr2) & 0x3F) << 10) | ((uint32_t)(val) << 16) | \ (((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31)) /// ADI register, half-size read-modify-write #define ADI_HALFREG_OVERRIDE(adiNo, addr, mask, val) (2 | (ADI_VAL_MASK(addr, mask, val) << 16) | \ - (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31)) + (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31)) /// 2 ADI registers, half-size read-modify-write -#define ADI_2HALFREG_OVERRIDE(adiNo, addr, mask, val, addr2, mask2, val2) \ +#define ADI_2HALFREG_OVERRIDE(adiNo, addr, mask, val, addr2, mask2, val2) \ (2 | (ADI_VAL_MASK(addr2, mask2, val2) << 2) | (((addr2) & 0x3F) << 10) | \ (ADI_VAL_MASK(addr, mask, val) << 16) | (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31)) @@ -297,37 +277,36 @@ typedef struct #define SW_REG_OVERRIDE(cmd, field, val) (3 | ((_POSITION_##cmd##_##field) << 4) | ((uint32_t)(val) << 16)) /// SW register as defined in radio_par_def.txt with added index (for use with registers > 16 bits). #define SW_REG_IND_OVERRIDE(cmd, field, offset, val) (3 | \ - (((_POSITION_##cmd##_##field) + ((offset) << 1)) << 4) | ((uint32_t)(val) << 16)) + (((_POSITION_##cmd##_##field) + ((offset) << 1)) << 4) | ((uint32_t)(val) << 16)) /// 8-bit SW register as defined in radio_par_def.txt #define SW_REG_BYTE_OVERRIDE(cmd, field, val) (0x8003 | ((_POSITION_##cmd##_##field) << 4) | \ - ((uint32_t)(val) << 16)) + ((uint32_t)(val) << 16)) /// Two 8-bit SW registers as defined in radio_par_def.txt; the one given by field and the next byte. #define SW_REG_2BYTE_OVERRIDE(cmd, field, val0, val1) (3 | (((_POSITION_##cmd##_##field) & 0xFFFE) << 4) | \ - (((uint32_t)(val0) << 16) & 0x00FF0000) | ((uint32_t)(val1) << 24)) -#define HW16_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) -#define HW32_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | \ - ((uint32_t)(length) << 16) | (1U << 30)) + (((uint32_t)(val0) << 16) & 0x00FF0000) | ((uint32_t)(val1) << 24)) +#define HW16_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t)(addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) +#define HW32_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t)(addr)) & 0xFFFC) | \ + ((uint32_t)(length) << 16) | (1U << 30)) #define ADI_ARRAY_OVERRIDE(adiNo, addr, bHalfSize, length) (1 | ((((addr) & 0x3F) << 2)) | \ - ((!!(bHalfSize)) << 8) | ((!!(adiNo)) << 9) | ((uint32_t)(length) << 16) | (2U << 30)) + ((!!(bHalfSize)) << 8) | ((!!(adiNo)) << 9) | ((uint32_t)(length) << 16) | (2U << 30)) #define SW_ARRAY_OVERRIDE(cmd, firstfield, length) (1 | (((_POSITION_##cmd##_##firstfield)) << 2) | \ - ((uint32_t)(length) << 16) | (3U << 30)) -#define MCE_RFE_OVERRIDE(bMceRam, mceRomBank, mceMode, bRfeRam, rfeRomBank, rfeMode) \ + ((uint32_t)(length) << 16) | (3U << 30)) +#define MCE_RFE_OVERRIDE(bMceRam, mceRomBank, mceMode, bRfeRam, rfeRomBank, rfeMode) \ (7 | ((!!(bMceRam)) << 8) | (((mceRomBank) & 0x07) << 9) | ((!!(bRfeRam)) << 12) | (((rfeRomBank) & 0x07) << 13) | \ (((mceMode) & 0x00FF) << 16) | (((rfeMode) & 0x00FF) << 24)) -#define NEW_OVERRIDE_SEGMENT(address) (((((uintptr_t)(address)) & 0x03FFFFFC) << 6) | 0x000F | \ - (((((uintptr_t)(address) >> 24) == 0x20) ? 0x01 : \ - (((uintptr_t)(address) >> 24) == 0x21) ? 0x02 : \ - (((uintptr_t)(address) >> 24) == 0xA0) ? 0x03 : \ - (((uintptr_t)(address) >> 24) == 0x00) ? 0x04 : \ - (((uintptr_t)(address) >> 24) == 0x10) ? 0x05 : \ - (((uintptr_t)(address) >> 24) == 0x11) ? 0x06 : \ - (((uintptr_t)(address) >> 24) == 0x40) ? 0x07 : \ - (((uintptr_t)(address) >> 24) == 0x50) ? 0x08 : \ - 0x09) << 4)) // Use illegal value for illegal address range +#define NEW_OVERRIDE_SEGMENT(address) (((((uintptr_t)(address)) & 0x03FFFFFC) << 6) | 0x000F | \ + (((((uintptr_t)(address) >> 24) == 0x20) ? 0x01 : (((uintptr_t)(address) >> 24) == 0x21) ? 0x02 \ + : (((uintptr_t)(address) >> 24) == 0xA0) ? 0x03 \ + : (((uintptr_t)(address) >> 24) == 0x00) ? 0x04 \ + : (((uintptr_t)(address) >> 24) == 0x10) ? 0x05 \ + : (((uintptr_t)(address) >> 24) == 0x11) ? 0x06 \ + : (((uintptr_t)(address) >> 24) == 0x40) ? 0x07 \ + : (((uintptr_t)(address) >> 24) == 0x50) ? 0x08 \ + : 0x09) \ + << 4)) // Use illegal value for illegal address range /// End of string for override register #define END_OVERRIDE 0xFFFFFFFF - /// ADI address-value pair #define ADI_ADDR_VAL(addr, value) ((((addr) & 0x7F) << 8) | ((value) & 0xFF)) #define ADI_ADDR_VAL_MASK(addr, mask, value) ((((addr) & 0x7F) << 8) | ADI_VAL_MASK(addr, mask, value)) @@ -338,5 +317,4 @@ typedef struct #define HIWORD(value) ((value) >> 16) ///@} - #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_prop_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_prop_cmd.h index 173043b..5e3a60b 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_prop_cmd.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_prop_cmd.h @@ -1,56 +1,56 @@ /****************************************************************************** -* Filename: rf_prop_cmd.h -* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) -* Revision: 18052 -* -* Description: CC13x0 API for Proprietary mode commands -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_prop_cmd.h + * Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) + * Revision: 18052 + * + * Description: CC13x0 API for Proprietary mode commands + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __PROP_CMD_H #define __PROP_CMD_H #ifndef __RFC_STRUCT - #define __RFC_STRUCT +#define __RFC_STRUCT #endif #ifndef __RFC_STRUCT_ATTR - #if defined(__GNUC__) - #define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) - #elif defined(__TI_ARM__) - #define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) - #else - #define __RFC_STRUCT_ATTR - #endif +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__((aligned(4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__((__packed__, aligned(4))) +#else +#define __RFC_STRUCT_ATTR +#endif #endif //! \addtogroup rfc @@ -59,9 +59,9 @@ //! \addtogroup prop_cmd //! @{ -#include -#include "rf_mailbox.h" #include "rf_common_cmd.h" +#include "rf_mailbox.h" +#include typedef struct __RFC_STRUCT rfc_carrierSense_s rfc_carrierSense_t; typedef struct __RFC_STRUCT rfc_CMD_PROP_TX_s rfc_CMD_PROP_TX_t; @@ -82,894 +82,894 @@ typedef struct __RFC_STRUCT rfc_propRxStatus_s rfc_propRxStatus_t; //! @{ struct __RFC_STRUCT rfc_carrierSense_s { - struct - { - uint8_t bEnaRssi: 1; //!< If 1, enable RSSI as a criterion - uint8_t bEnaCorr: 1; //!< If 1, enable correlation as a criterion - uint8_t operation: 1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
- //!< 1: Busy if both RSSI and correlation indicates Busy - uint8_t busyOp: 1; //!< \brief 0: Continue carrier sense on channel Busy
- //!< 1: End carrier sense on channel Busy
- //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle - uint8_t idleOp: 1; //!< \brief 0: Continue on channel Idle
- //!< 1: End on channel Idle - uint8_t timeoutRes: 1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
- //!< 1: Timeout with channel state Invalid treated as Idle - } csConf; - int8_t rssiThr; //!< RSSI threshold - uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is - //!< declared Idle - uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is - //!< declared Busy - uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods - struct - { - uint8_t numCorrInv: 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Idle to Invalid - uint8_t numCorrBusy: 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Invalid to Busy - } corrConfig; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } csEndTrigger; //!< Trigger classifier for ending the carrier sense - ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation + struct + { + uint8_t bEnaRssi : 1; //!< If 1, enable RSSI as a criterion + uint8_t bEnaCorr : 1; //!< If 1, enable correlation as a criterion + uint8_t operation : 1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
+ //!< 1: Busy if both RSSI and correlation indicates Busy + uint8_t busyOp : 1; //!< \brief 0: Continue carrier sense on channel Busy
+ //!< 1: End carrier sense on channel Busy
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle + uint8_t idleOp : 1; //!< \brief 0: Continue on channel Idle
+ //!< 1: End on channel Idle + uint8_t timeoutRes : 1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
+ //!< 1: Timeout with channel state Invalid treated as Idle + } csConf; + int8_t rssiThr; //!< RSSI threshold + uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is + //!< declared Idle + uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is + //!< declared Busy + uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods + struct + { + uint8_t numCorrInv : 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Idle to Invalid + uint8_t numCorrBusy : 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Invalid to Busy + } corrConfig; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } csEndTrigger; //!< Trigger classifier for ending the carrier sense + ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_TX //! @{ -#define CMD_PROP_TX 0x3801 +#define CMD_PROP_TX 0x3801 //! Proprietary Mode Transmit Command struct __RFC_STRUCT rfc_CMD_PROP_TX_s { - uint16_t commandNo; //!< The command ID number 0x3801 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t : 2; - uint8_t bUseCrc: 1; //!< \brief 0: Do not append CRC
- //!< 1: Append CRC - uint8_t bVarLen: 1; //!< \brief 0: Fixed length
- //!< 1: Transmit length as first byte - } pktConf; - uint8_t pktLen; //!< Packet length - uint32_t syncWord; //!< Sync word to transmit - uint8_t* pPkt; //!< Pointer to packet + uint16_t commandNo; //!< The command ID number 0x3801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t : 2; + uint8_t bUseCrc : 1; //!< \brief 0: Do not append CRC
+ //!< 1: Append CRC + uint8_t bVarLen : 1; //!< \brief 0: Fixed length
+ //!< 1: Transmit length as first byte + } pktConf; + uint8_t pktLen; //!< Packet length + uint32_t syncWord; //!< Sync word to transmit + uint8_t* pPkt; //!< Pointer to packet } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_RX //! @{ -#define CMD_PROP_RX 0x3802 +#define CMD_PROP_RX 0x3802 //! Proprietary Mode Receive Command struct __RFC_STRUCT rfc_CMD_PROP_RX_s { - uint16_t commandNo; //!< The command ID number 0x3802 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bRepeatOk: 1; //!< \brief 0: End operation after receiving a packet correctly
- //!< 1: Go back to sync search after receiving a packet correctly - uint8_t bRepeatNok: 1; //!< \brief 0: End operation after receiving a packet with CRC error
- //!< 1: Go back to sync search after receiving a packet with CRC error - uint8_t bUseCrc: 1; //!< \brief 0: Do not check CRC
- //!< 1: Check CRC - uint8_t bVarLen: 1; //!< \brief 0: Fixed length
- //!< 1: Receive length as first byte - uint8_t bChkAddress: 1; //!< \brief 0: No address check
- //!< 1: Check address - uint8_t endType: 1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
- //!< 1: Packet reception is stopped if end trigger happens - uint8_t filterOp: 1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
- //!< 1: Receive packet and mark it as ignored on address mismatch - } pktConf; - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically discard ignored packets from RX queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically discard packets with CRC error from RX queue - uint8_t : 1; - uint8_t bIncludeHdr: 1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the RX queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the RX queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the RX queue - } rxConf; //!< RX configuration - uint32_t syncWord; //!< Sync word to listen for - uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
- //!< 0: Unlimited or unknown length - uint8_t address0; //!< Address - uint8_t address1; //!< \brief Address (set equal to address0 to accept only one address. If 0xFF, accept - //!< 0x00 as well) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - ratmr_t endTime; //!< Time used together with endTrigger for ending the operation - dataQueue_t* pQueue; //!< Pointer to receive queue - uint8_t* pOutput; //!< Pointer to output structure + uint16_t commandNo; //!< The command ID number 0x3802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk : 1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok : 1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc : 1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bVarLen : 1; //!< \brief 0: Fixed length
+ //!< 1: Receive length as first byte + uint8_t bChkAddress : 1; //!< \brief 0: No address check
+ //!< 1: Check address + uint8_t endType : 1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp : 1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t : 1; + uint8_t bIncludeHdr : 1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord; //!< Sync word to listen for + uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + uint8_t address0; //!< Address + uint8_t address1; //!< \brief Address (set equal to address0 to accept only one address. If 0xFF, accept + //!< 0x00 as well) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_TX_ADV //! @{ -#define CMD_PROP_TX_ADV 0x3803 +#define CMD_PROP_TX_ADV 0x3803 //! Proprietary Mode Advanced Transmit Command struct __RFC_STRUCT rfc_CMD_PROP_TX_ADV_s { - uint16_t commandNo; //!< The command ID number 0x3803 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t : 2; - uint8_t bUseCrc: 1; //!< \brief 0: Do not append CRC
- //!< 1: Append CRC - uint8_t bCrcIncSw: 1; //!< \brief 0:Do not include sync word in CRC calculation
- //!< 1: Include sync word in CRC calculation - uint8_t bCrcIncHdr: 1; //!< \brief 0: Do not include header in CRC calculation
- //!< 1: Include header in CRC calculation - } pktConf; - uint8_t numHdrBits; //!< Number of bits in header (0--32) - uint16_t pktLen; //!< Packet length. 0: Unlimited - struct - { - uint8_t bExtTxTrig: 1; //!< \brief 0: Start packet on a fixed time from the command start trigger
- //!< 1: Start packet on an external trigger (input event to RAT) - uint8_t inputMode: 2; //!< \brief Input mode if external trigger is used for TX start
- //!< 0: Rising edge
- //!< 1: Falling edge
- //!< 2: Both edges
- //!< 3: Reserved - uint8_t source: 5; //!< RAT input event number used for capture if external trigger is used for TX start - } startConf; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } preTrigger; //!< Trigger for transition from preamble to sync word - ratmr_t preTime; //!< \brief Time used together with preTrigger for transition from preamble to sync - //!< word. If preTrigger.triggerType is set to "now", one preamble as - //!< configured in the setup will be sent. Otherwise, the preamble will be repeated until - //!< this trigger is observed. - uint32_t syncWord; //!< Sync word to transmit - uint8_t* pPkt; //!< Pointer to packet, or TX queue for unlimited length + uint16_t commandNo; //!< The command ID number 0x3803 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t : 2; + uint8_t bUseCrc : 1; //!< \brief 0: Do not append CRC
+ //!< 1: Append CRC + uint8_t bCrcIncSw : 1; //!< \brief 0:Do not include sync word in CRC calculation
+ //!< 1: Include sync word in CRC calculation + uint8_t bCrcIncHdr : 1; //!< \brief 0: Do not include header in CRC calculation
+ //!< 1: Include header in CRC calculation + } pktConf; + uint8_t numHdrBits; //!< Number of bits in header (0--32) + uint16_t pktLen; //!< Packet length. 0: Unlimited + struct + { + uint8_t bExtTxTrig : 1; //!< \brief 0: Start packet on a fixed time from the command start trigger
+ //!< 1: Start packet on an external trigger (input event to RAT) + uint8_t inputMode : 2; //!< \brief Input mode if external trigger is used for TX start
+ //!< 0: Rising edge
+ //!< 1: Falling edge
+ //!< 2: Both edges
+ //!< 3: Reserved + uint8_t source : 5; //!< RAT input event number used for capture if external trigger is used for TX start + } startConf; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } preTrigger; //!< Trigger for transition from preamble to sync word + ratmr_t preTime; //!< \brief Time used together with preTrigger for transition from preamble to sync + //!< word. If preTrigger.triggerType is set to "now", one preamble as + //!< configured in the setup will be sent. Otherwise, the preamble will be repeated until + //!< this trigger is observed. + uint32_t syncWord; //!< Sync word to transmit + uint8_t* pPkt; //!< Pointer to packet, or TX queue for unlimited length } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_RX_ADV //! @{ -#define CMD_PROP_RX_ADV 0x3804 +#define CMD_PROP_RX_ADV 0x3804 //! Proprietary Mode Advanced Receive Command struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_s { - uint16_t commandNo; //!< The command ID number 0x3804 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bRepeatOk: 1; //!< \brief 0: End operation after receiving a packet correctly
- //!< 1: Go back to sync search after receiving a packet correctly - uint8_t bRepeatNok: 1; //!< \brief 0: End operation after receiving a packet with CRC error
- //!< 1: Go back to sync search after receiving a packet with CRC error - uint8_t bUseCrc: 1; //!< \brief 0: Do not check CRC
- //!< 1: Check CRC - uint8_t bCrcIncSw: 1; //!< \brief 0: Do not include sync word in CRC calculation
- //!< 1: Include sync word in CRC calculation - uint8_t bCrcIncHdr: 1; //!< \brief 0: Do not include header in CRC calculation
- //!< 1: Include header in CRC calculation - uint8_t endType: 1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
- //!< 1: Packet reception is stopped if end trigger happens - uint8_t filterOp: 1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
- //!< 1: Receive packet and mark it as ignored on address mismatch - } pktConf; - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically discard ignored packets from RX queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically discard packets with CRC error from RX queue - uint8_t : 1; - uint8_t bIncludeHdr: 1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the RX queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the RX queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the RX queue - } rxConf; //!< RX configuration - uint32_t syncWord0; //!< Sync word to listen for - uint32_t syncWord1; //!< Alternative sync word if non-zero - uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
- //!< 0: Unlimited or unknown length - struct - { - uint16_t numHdrBits: 6; //!< Number of bits in header (0--32) - uint16_t lenPos: 5; //!< Position of length field in header (0--31) - uint16_t numLenBits: 5; //!< Number of bits in length field (0--16) - } hdrConf; - struct - { - uint16_t addrType: 1; //!< \brief 0: Address after header
- //!< 1: Address in header - uint16_t addrSize: 5; //!< \brief If addrType = 0: Address size in bytes
- //!< If addrType = 1: Address size in bits - uint16_t addrPos: 5; //!< \brief If addrType = 1: Bit position of address in header
- //!< If addrType = 0: Non-zero to extend address with sync word identifier - uint16_t numAddr: 5; //!< Number of addresses in address list - } addrConf; - int8_t lenOffset; //!< Signed value to add to length field - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - ratmr_t endTime; //!< Time used together with endTrigger for ending the operation - uint8_t* pAddr; //!< Pointer to address list - dataQueue_t* pQueue; //!< Pointer to receive queue - uint8_t* pOutput; //!< Pointer to output structure + uint16_t commandNo; //!< The command ID number 0x3804 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk : 1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok : 1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc : 1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bCrcIncSw : 1; //!< \brief 0: Do not include sync word in CRC calculation
+ //!< 1: Include sync word in CRC calculation + uint8_t bCrcIncHdr : 1; //!< \brief 0: Do not include header in CRC calculation
+ //!< 1: Include header in CRC calculation + uint8_t endType : 1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp : 1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t : 1; + uint8_t bIncludeHdr : 1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord0; //!< Sync word to listen for + uint32_t syncWord1; //!< Alternative sync word if non-zero + uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + struct + { + uint16_t numHdrBits : 6; //!< Number of bits in header (0--32) + uint16_t lenPos : 5; //!< Position of length field in header (0--31) + uint16_t numLenBits : 5; //!< Number of bits in length field (0--16) + } hdrConf; + struct + { + uint16_t addrType : 1; //!< \brief 0: Address after header
+ //!< 1: Address in header + uint16_t addrSize : 5; //!< \brief If addrType = 0: Address size in bytes
+ //!< If addrType = 1: Address size in bits + uint16_t addrPos : 5; //!< \brief If addrType = 1: Bit position of address in header
+ //!< If addrType = 0: Non-zero to extend address with sync word identifier + uint16_t numAddr : 5; //!< Number of addresses in address list + } addrConf; + int8_t lenOffset; //!< Signed value to add to length field + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + uint8_t* pAddr; //!< Pointer to address list + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_CS //! @{ -#define CMD_PROP_CS 0x3805 +#define CMD_PROP_CS 0x3805 //! Carrier Sense Command struct __RFC_STRUCT rfc_CMD_PROP_CS_s { - uint16_t commandNo; //!< The command ID number 0x3805 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOffIdle: 1; //!< \brief 0: Keep synth running if command ends with channel Idle
- //!< 1: Turn off synth if command ends with channel Idle - uint8_t bFsOffBusy: 1; //!< \brief 0: Keep synth running if command ends with channel Busy
- //!< 1: Turn off synth if command ends with channel Busy - } csFsConf; - uint8_t __dummy0; - struct - { - uint8_t bEnaRssi: 1; //!< If 1, enable RSSI as a criterion - uint8_t bEnaCorr: 1; //!< If 1, enable correlation as a criterion - uint8_t operation: 1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
- //!< 1: Busy if both RSSI and correlation indicates Busy - uint8_t busyOp: 1; //!< \brief 0: Continue carrier sense on channel Busy
- //!< 1: End carrier sense on channel Busy
- //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle - uint8_t idleOp: 1; //!< \brief 0: Continue on channel Idle
- //!< 1: End on channel Idle - uint8_t timeoutRes: 1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
- //!< 1: Timeout with channel state Invalid treated as Idle - } csConf; - int8_t rssiThr; //!< RSSI threshold - uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is - //!< declared Idle - uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is - //!< declared Busy - uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods - struct - { - uint8_t numCorrInv: 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Idle to Invalid - uint8_t numCorrBusy: 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Invalid to Busy - } corrConfig; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } csEndTrigger; //!< Trigger classifier for ending the carrier sense - ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation + uint16_t commandNo; //!< The command ID number 0x3805 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOffIdle : 1; //!< \brief 0: Keep synth running if command ends with channel Idle
+ //!< 1: Turn off synth if command ends with channel Idle + uint8_t bFsOffBusy : 1; //!< \brief 0: Keep synth running if command ends with channel Busy
+ //!< 1: Turn off synth if command ends with channel Busy + } csFsConf; + uint8_t __dummy0; + struct + { + uint8_t bEnaRssi : 1; //!< If 1, enable RSSI as a criterion + uint8_t bEnaCorr : 1; //!< If 1, enable correlation as a criterion + uint8_t operation : 1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
+ //!< 1: Busy if both RSSI and correlation indicates Busy + uint8_t busyOp : 1; //!< \brief 0: Continue carrier sense on channel Busy
+ //!< 1: End carrier sense on channel Busy
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle + uint8_t idleOp : 1; //!< \brief 0: Continue on channel Idle
+ //!< 1: End on channel Idle + uint8_t timeoutRes : 1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
+ //!< 1: Timeout with channel state Invalid treated as Idle + } csConf; + int8_t rssiThr; //!< RSSI threshold + uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is + //!< declared Idle + uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is + //!< declared Busy + uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods + struct + { + uint8_t numCorrInv : 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Idle to Invalid + uint8_t numCorrBusy : 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Invalid to Busy + } corrConfig; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } csEndTrigger; //!< Trigger classifier for ending the carrier sense + ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_RADIO_SETUP //! @{ -#define CMD_PROP_RADIO_SETUP 0x3806 +#define CMD_PROP_RADIO_SETUP 0x3806 //! Proprietary Mode Radio Setup Command for 2.4 GHz (CC1350 Only) struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_s { - uint16_t commandNo; //!< The command ID number 0x3806 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint16_t modType: 3; //!< \brief 0: FSK
- //!< 1: GFSK
- //!< Others: Reserved - uint16_t deviation: 13; //!< Deviation (250 Hz steps) - } modulation; - struct - { - uint32_t preScale: 4; //!< Prescaler value - uint32_t : 4; - uint32_t rateWord: 21; //!< Rate word - uint32_t decimMode: 3; //!< \brief 0: Use automatic PDIF decimation
- //!< 1: Force PDIF decimation to 0
- //!< 3: Force PDIF decimation to 1
- //!< 5: Force PDIF decimation to 2
- //!< Others: Reserved - } symbolRate; //!< Symbol rate setting - uint8_t rxBw; //!< Receiver bandwidth - struct - { - uint8_t nPreamBytes: 6; //!< \brief 0: 1 preamble bit
- //!< 1--16: Number of preamble bytes
- //!< 18, 20, ..., 30: Number of preamble bytes
- //!< 31: 4 preamble bits
- //!< 32: 32 preamble bytes
- //!< Others: Reserved - uint8_t preamMode: 2; //!< \brief 0: Send 0 as the first preamble bit
- //!< 1: Send 1 as the first preamble bit
- //!< 2: Send same first bit in preamble and sync word
- //!< 3: Send different first bit in preamble and sync word - } preamConf; - struct - { - uint16_t nSwBits: 6; //!< Number of sync word bits (8--32) - uint16_t bBitReversal: 1; //!< \brief 0: Use positive deviation for 1
- //!< 1: Use positive deviation for 0 - uint16_t bMsbFirst: 1; //!< \brief 0: Least significant bit transmitted first
- //!< 1: Most significant bit transmitted first - uint16_t fecMode: 4; //!< \brief Select coding
- //!< 0: Uncoded binary modulation
- //!< 8: Long range mode
- //!< 10: Manchester coded binary modulation
- //!< Others: Reserved - uint16_t : 1; - uint16_t whitenMode: 3; //!< \brief 0: No whitening
- //!< 1: CC1101/CC2500 compatible whitening
- //!< 2: PN9 whitening without byte reversal
- //!< 3: Reserved
- //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
- //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
- //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
- //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC - } formatConf; - struct - { - uint16_t frontEndMode: 3; //!< \brief 0x00: Differential mode
- //!< 0x01: Single-ended mode RFP
- //!< 0x02: Single-ended mode RFN
- //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
- //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
- //!< Others: Reserved - uint16_t biasMode: 1; //!< \brief 0: Internal bias
- //!< 1: External bias - uint16_t analogCfgMode: 6; //!< \brief 0x00: Write analog configuration.
- //!< Required first time after boot and when changing frequency band - //!< or front-end configuration
- //!< 0x2D: Keep analog configuration.
- //!< May be used after standby or when changing mode with the same frequency - //!< band and front-end configuration
- //!< Others: Reserved - uint16_t bNoFsPowerUp: 1; //!< \brief 0: Power up frequency synth
- //!< 1: Do not power up frequency synth - } config; //!< Configuration options - uint16_t txPower; //!< Transmit power - uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no - //!< override is used. + uint16_t commandNo; //!< The command ID number 0x3806 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint16_t modType : 3; //!< \brief 0: FSK
+ //!< 1: GFSK
+ //!< Others: Reserved + uint16_t deviation : 13; //!< Deviation (250 Hz steps) + } modulation; + struct + { + uint32_t preScale : 4; //!< Prescaler value + uint32_t : 4; + uint32_t rateWord : 21; //!< Rate word + uint32_t decimMode : 3; //!< \brief 0: Use automatic PDIF decimation
+ //!< 1: Force PDIF decimation to 0
+ //!< 3: Force PDIF decimation to 1
+ //!< 5: Force PDIF decimation to 2
+ //!< Others: Reserved + } symbolRate; //!< Symbol rate setting + uint8_t rxBw; //!< Receiver bandwidth + struct + { + uint8_t nPreamBytes : 6; //!< \brief 0: 1 preamble bit
+ //!< 1--16: Number of preamble bytes
+ //!< 18, 20, ..., 30: Number of preamble bytes
+ //!< 31: 4 preamble bits
+ //!< 32: 32 preamble bytes
+ //!< Others: Reserved + uint8_t preamMode : 2; //!< \brief 0: Send 0 as the first preamble bit
+ //!< 1: Send 1 as the first preamble bit
+ //!< 2: Send same first bit in preamble and sync word
+ //!< 3: Send different first bit in preamble and sync word + } preamConf; + struct + { + uint16_t nSwBits : 6; //!< Number of sync word bits (8--32) + uint16_t bBitReversal : 1; //!< \brief 0: Use positive deviation for 1
+ //!< 1: Use positive deviation for 0 + uint16_t bMsbFirst : 1; //!< \brief 0: Least significant bit transmitted first
+ //!< 1: Most significant bit transmitted first + uint16_t fecMode : 4; //!< \brief Select coding
+ //!< 0: Uncoded binary modulation
+ //!< 8: Long range mode
+ //!< 10: Manchester coded binary modulation
+ //!< Others: Reserved + uint16_t : 1; + uint16_t whitenMode : 3; //!< \brief 0: No whitening
+ //!< 1: CC1101/CC2500 compatible whitening
+ //!< 2: PN9 whitening without byte reversal
+ //!< 3: Reserved
+ //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
+ //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
+ //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
+ //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC + } formatConf; + struct + { + uint16_t frontEndMode : 3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode : 1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode : 6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp : 1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_RADIO_DIV_SETUP //! @{ -#define CMD_PROP_RADIO_DIV_SETUP 0x3807 +#define CMD_PROP_RADIO_DIV_SETUP 0x3807 //! Proprietary Mode Radio Setup Command for All Frequency Bands struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_s { - uint16_t commandNo; //!< The command ID number 0x3807 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint16_t modType: 3; //!< \brief 0: FSK
- //!< 1: GFSK
- //!< Others: Reserved - uint16_t deviation: 13; //!< Deviation (250 Hz steps) - } modulation; - struct - { - uint32_t preScale: 4; //!< Prescaler value - uint32_t : 4; - uint32_t rateWord: 21; //!< Rate word - uint32_t decimMode: 3; //!< \brief 0: Use automatic PDIF decimation
- //!< 1: Force PDIF decimation to 0
- //!< 3: Force PDIF decimation to 1
- //!< 5: Force PDIF decimation to 2
- //!< Others: Reserved - } symbolRate; //!< Symbol rate setting - uint8_t rxBw; //!< Receiver bandwidth - struct - { - uint8_t nPreamBytes: 6; //!< \brief 0: 1 preamble bit
- //!< 1--16: Number of preamble bytes
- //!< 18, 20, ..., 30: Number of preamble bytes
- //!< 31: 4 preamble bits
- //!< 32: 32 preamble bytes
- //!< Others: Reserved - uint8_t preamMode: 2; //!< \brief 0: Send 0 as the first preamble bit
- //!< 1: Send 1 as the first preamble bit
- //!< 2: Send same first bit in preamble and sync word
- //!< 3: Send different first bit in preamble and sync word - } preamConf; - struct - { - uint16_t nSwBits: 6; //!< Number of sync word bits (8--32) - uint16_t bBitReversal: 1; //!< \brief 0: Use positive deviation for 1
- //!< 1: Use positive deviation for 0 - uint16_t bMsbFirst: 1; //!< \brief 0: Least significant bit transmitted first
- //!< 1: Most significant bit transmitted first - uint16_t fecMode: 4; //!< \brief Select coding
- //!< 0: Uncoded binary modulation
- //!< 8: Long range mode
- //!< 10: Manchester coded binary modulation
- //!< Others: Reserved - uint16_t : 1; - uint16_t whitenMode: 3; //!< \brief 0: No whitening
- //!< 1: CC1101/CC2500 compatible whitening
- //!< 2: PN9 whitening without byte reversal
- //!< 3: Reserved
- //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
- //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
- //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
- //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC - } formatConf; - struct - { - uint16_t frontEndMode: 3; //!< \brief 0x00: Differential mode
- //!< 0x01: Single-ended mode RFP
- //!< 0x02: Single-ended mode RFN
- //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
- //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
- //!< Others: Reserved - uint16_t biasMode: 1; //!< \brief 0: Internal bias
- //!< 1: External bias - uint16_t analogCfgMode: 6; //!< \brief 0x00: Write analog configuration.
- //!< Required first time after boot and when changing frequency band - //!< or front-end configuration
- //!< 0x2D: Keep analog configuration.
- //!< May be used after standby or when changing mode with the same frequency - //!< band and front-end configuration
- //!< Others: Reserved - uint16_t bNoFsPowerUp: 1; //!< \brief 0: Power up frequency synth
- //!< 1: Do not power up frequency synth - } config; //!< Configuration options - uint16_t txPower; //!< Transmit power - uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no - //!< override is used. - uint16_t centerFreq; //!< \brief Center frequency of the frequency band used, in MHz; used for calculating some internal TX and RX parameters. - //!< For a single channel RF system, this should be set equal to the RF frequency used. - //!< For a multi channel RF system (e.g. frequency hopping spread spectrum), this should be set equal - //!< to the center frequency of the frequency band used. - int16_t intFreq; //!< \brief Intermediate frequency to use for RX, in MHz on 4.12 signed format. TX will use same - //!< intermediate frequency if supported, otherwise 0.
- //!< 0x8000: Use default. - uint8_t loDivider; //!< LO frequency divider setting to use. Supported values: 2 (CC1350 only), 5, 6, 10, 12, 15, and 30 + uint16_t commandNo; //!< The command ID number 0x3807 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint16_t modType : 3; //!< \brief 0: FSK
+ //!< 1: GFSK
+ //!< Others: Reserved + uint16_t deviation : 13; //!< Deviation (250 Hz steps) + } modulation; + struct + { + uint32_t preScale : 4; //!< Prescaler value + uint32_t : 4; + uint32_t rateWord : 21; //!< Rate word + uint32_t decimMode : 3; //!< \brief 0: Use automatic PDIF decimation
+ //!< 1: Force PDIF decimation to 0
+ //!< 3: Force PDIF decimation to 1
+ //!< 5: Force PDIF decimation to 2
+ //!< Others: Reserved + } symbolRate; //!< Symbol rate setting + uint8_t rxBw; //!< Receiver bandwidth + struct + { + uint8_t nPreamBytes : 6; //!< \brief 0: 1 preamble bit
+ //!< 1--16: Number of preamble bytes
+ //!< 18, 20, ..., 30: Number of preamble bytes
+ //!< 31: 4 preamble bits
+ //!< 32: 32 preamble bytes
+ //!< Others: Reserved + uint8_t preamMode : 2; //!< \brief 0: Send 0 as the first preamble bit
+ //!< 1: Send 1 as the first preamble bit
+ //!< 2: Send same first bit in preamble and sync word
+ //!< 3: Send different first bit in preamble and sync word + } preamConf; + struct + { + uint16_t nSwBits : 6; //!< Number of sync word bits (8--32) + uint16_t bBitReversal : 1; //!< \brief 0: Use positive deviation for 1
+ //!< 1: Use positive deviation for 0 + uint16_t bMsbFirst : 1; //!< \brief 0: Least significant bit transmitted first
+ //!< 1: Most significant bit transmitted first + uint16_t fecMode : 4; //!< \brief Select coding
+ //!< 0: Uncoded binary modulation
+ //!< 8: Long range mode
+ //!< 10: Manchester coded binary modulation
+ //!< Others: Reserved + uint16_t : 1; + uint16_t whitenMode : 3; //!< \brief 0: No whitening
+ //!< 1: CC1101/CC2500 compatible whitening
+ //!< 2: PN9 whitening without byte reversal
+ //!< 3: Reserved
+ //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
+ //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
+ //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
+ //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC + } formatConf; + struct + { + uint16_t frontEndMode : 3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode : 1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode : 6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp : 1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. + uint16_t centerFreq; //!< \brief Center frequency of the frequency band used, in MHz; used for calculating some internal TX and RX parameters. + //!< For a single channel RF system, this should be set equal to the RF frequency used. + //!< For a multi channel RF system (e.g. frequency hopping spread spectrum), this should be set equal + //!< to the center frequency of the frequency band used. + int16_t intFreq; //!< \brief Intermediate frequency to use for RX, in MHz on 4.12 signed format. TX will use same + //!< intermediate frequency if supported, otherwise 0.
+ //!< 0x8000: Use default. + uint8_t loDivider; //!< LO frequency divider setting to use. Supported values: 2 (CC1350 only), 5, 6, 10, 12, 15, and 30 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_RX_SNIFF //! @{ -#define CMD_PROP_RX_SNIFF 0x3808 +#define CMD_PROP_RX_SNIFF 0x3808 //! Proprietary Mode Receive Command with Sniff Mode struct __RFC_STRUCT rfc_CMD_PROP_RX_SNIFF_s { - uint16_t commandNo; //!< The command ID number 0x3808 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bRepeatOk: 1; //!< \brief 0: End operation after receiving a packet correctly
- //!< 1: Go back to sync search after receiving a packet correctly - uint8_t bRepeatNok: 1; //!< \brief 0: End operation after receiving a packet with CRC error
- //!< 1: Go back to sync search after receiving a packet with CRC error - uint8_t bUseCrc: 1; //!< \brief 0: Do not check CRC
- //!< 1: Check CRC - uint8_t bVarLen: 1; //!< \brief 0: Fixed length
- //!< 1: Receive length as first byte - uint8_t bChkAddress: 1; //!< \brief 0: No address check
- //!< 1: Check address - uint8_t endType: 1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
- //!< 1: Packet reception is stopped if end trigger happens - uint8_t filterOp: 1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
- //!< 1: Receive packet and mark it as ignored on address mismatch - } pktConf; - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically discard ignored packets from RX queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically discard packets with CRC error from RX queue - uint8_t : 1; - uint8_t bIncludeHdr: 1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the RX queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the RX queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the RX queue - } rxConf; //!< RX configuration - uint32_t syncWord; //!< Sync word to listen for - uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
- //!< 0: Unlimited or unknown length - uint8_t address0; //!< Address - uint8_t address1; //!< \brief Address (set equal to address0 to accept only one address. If 0xFF, accept - //!< 0x00 as well) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - ratmr_t endTime; //!< Time used together with endTrigger for ending the operation - dataQueue_t* pQueue; //!< Pointer to receive queue - uint8_t* pOutput; //!< Pointer to output structure - struct - { - uint8_t bEnaRssi: 1; //!< If 1, enable RSSI as a criterion - uint8_t bEnaCorr: 1; //!< If 1, enable correlation as a criterion - uint8_t operation: 1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
- //!< 1: Busy if both RSSI and correlation indicates Busy - uint8_t busyOp: 1; //!< \brief 0: Continue carrier sense on channel Busy
- //!< 1: End carrier sense on channel Busy
- //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle - uint8_t idleOp: 1; //!< \brief 0: Continue on channel Idle
- //!< 1: End on channel Idle - uint8_t timeoutRes: 1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
- //!< 1: Timeout with channel state Invalid treated as Idle - } csConf; - int8_t rssiThr; //!< RSSI threshold - uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is - //!< declared Idle - uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is - //!< declared Busy - uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods - struct - { - uint8_t numCorrInv: 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Idle to Invalid - uint8_t numCorrBusy: 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Invalid to Busy - } corrConfig; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } csEndTrigger; //!< Trigger classifier for ending the carrier sense - ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation + uint16_t commandNo; //!< The command ID number 0x3808 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk : 1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok : 1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc : 1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bVarLen : 1; //!< \brief 0: Fixed length
+ //!< 1: Receive length as first byte + uint8_t bChkAddress : 1; //!< \brief 0: No address check
+ //!< 1: Check address + uint8_t endType : 1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp : 1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t : 1; + uint8_t bIncludeHdr : 1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord; //!< Sync word to listen for + uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + uint8_t address0; //!< Address + uint8_t address1; //!< \brief Address (set equal to address0 to accept only one address. If 0xFF, accept + //!< 0x00 as well) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure + struct + { + uint8_t bEnaRssi : 1; //!< If 1, enable RSSI as a criterion + uint8_t bEnaCorr : 1; //!< If 1, enable correlation as a criterion + uint8_t operation : 1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
+ //!< 1: Busy if both RSSI and correlation indicates Busy + uint8_t busyOp : 1; //!< \brief 0: Continue carrier sense on channel Busy
+ //!< 1: End carrier sense on channel Busy
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle + uint8_t idleOp : 1; //!< \brief 0: Continue on channel Idle
+ //!< 1: End on channel Idle + uint8_t timeoutRes : 1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
+ //!< 1: Timeout with channel state Invalid treated as Idle + } csConf; + int8_t rssiThr; //!< RSSI threshold + uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is + //!< declared Idle + uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is + //!< declared Busy + uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods + struct + { + uint8_t numCorrInv : 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Idle to Invalid + uint8_t numCorrBusy : 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Invalid to Busy + } corrConfig; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } csEndTrigger; //!< Trigger classifier for ending the carrier sense + ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_RX_ADV_SNIFF //! @{ -#define CMD_PROP_RX_ADV_SNIFF 0x3809 +#define CMD_PROP_RX_ADV_SNIFF 0x3809 //! Proprietary Mode Advanced Receive Command with Sniff Mode struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_SNIFF_s { - uint16_t commandNo; //!< The command ID number 0x3809 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bRepeatOk: 1; //!< \brief 0: End operation after receiving a packet correctly
- //!< 1: Go back to sync search after receiving a packet correctly - uint8_t bRepeatNok: 1; //!< \brief 0: End operation after receiving a packet with CRC error
- //!< 1: Go back to sync search after receiving a packet with CRC error - uint8_t bUseCrc: 1; //!< \brief 0: Do not check CRC
- //!< 1: Check CRC - uint8_t bCrcIncSw: 1; //!< \brief 0: Do not include sync word in CRC calculation
- //!< 1: Include sync word in CRC calculation - uint8_t bCrcIncHdr: 1; //!< \brief 0: Do not include header in CRC calculation
- //!< 1: Include header in CRC calculation - uint8_t endType: 1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
- //!< 1: Packet reception is stopped if end trigger happens - uint8_t filterOp: 1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
- //!< 1: Receive packet and mark it as ignored on address mismatch - } pktConf; - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically discard ignored packets from RX queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically discard packets with CRC error from RX queue - uint8_t : 1; - uint8_t bIncludeHdr: 1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the RX queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the RX queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the RX queue - } rxConf; //!< RX configuration - uint32_t syncWord0; //!< Sync word to listen for - uint32_t syncWord1; //!< Alternative sync word if non-zero - uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
- //!< 0: Unlimited or unknown length - struct - { - uint16_t numHdrBits: 6; //!< Number of bits in header (0--32) - uint16_t lenPos: 5; //!< Position of length field in header (0--31) - uint16_t numLenBits: 5; //!< Number of bits in length field (0--16) - } hdrConf; - struct - { - uint16_t addrType: 1; //!< \brief 0: Address after header
- //!< 1: Address in header - uint16_t addrSize: 5; //!< \brief If addrType = 0: Address size in bytes
- //!< If addrType = 1: Address size in bits - uint16_t addrPos: 5; //!< \brief If addrType = 1: Bit position of address in header
- //!< If addrType = 0: Non-zero to extend address with sync word identifier - uint16_t numAddr: 5; //!< Number of addresses in address list - } addrConf; - int8_t lenOffset; //!< Signed value to add to length field - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - ratmr_t endTime; //!< Time used together with endTrigger for ending the operation - uint8_t* pAddr; //!< Pointer to address list - dataQueue_t* pQueue; //!< Pointer to receive queue - uint8_t* pOutput; //!< Pointer to output structure - struct - { - uint8_t bEnaRssi: 1; //!< If 1, enable RSSI as a criterion - uint8_t bEnaCorr: 1; //!< If 1, enable correlation as a criterion - uint8_t operation: 1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
- //!< 1: Busy if both RSSI and correlation indicates Busy - uint8_t busyOp: 1; //!< \brief 0: Continue carrier sense on channel Busy
- //!< 1: End carrier sense on channel Busy
- //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle - uint8_t idleOp: 1; //!< \brief 0: Continue on channel Idle
- //!< 1: End on channel Idle - uint8_t timeoutRes: 1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
- //!< 1: Timeout with channel state Invalid treated as Idle - } csConf; - int8_t rssiThr; //!< RSSI threshold - uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is - //!< declared Idle - uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is - //!< declared Busy - uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods - struct - { - uint8_t numCorrInv: 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Idle to Invalid - uint8_t numCorrBusy: 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Invalid to Busy - } corrConfig; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } csEndTrigger; //!< Trigger classifier for ending the carrier sense - ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation + uint16_t commandNo; //!< The command ID number 0x3809 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk : 1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok : 1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc : 1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bCrcIncSw : 1; //!< \brief 0: Do not include sync word in CRC calculation
+ //!< 1: Include sync word in CRC calculation + uint8_t bCrcIncHdr : 1; //!< \brief 0: Do not include header in CRC calculation
+ //!< 1: Include header in CRC calculation + uint8_t endType : 1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp : 1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t : 1; + uint8_t bIncludeHdr : 1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord0; //!< Sync word to listen for + uint32_t syncWord1; //!< Alternative sync word if non-zero + uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + struct + { + uint16_t numHdrBits : 6; //!< Number of bits in header (0--32) + uint16_t lenPos : 5; //!< Position of length field in header (0--31) + uint16_t numLenBits : 5; //!< Number of bits in length field (0--16) + } hdrConf; + struct + { + uint16_t addrType : 1; //!< \brief 0: Address after header
+ //!< 1: Address in header + uint16_t addrSize : 5; //!< \brief If addrType = 0: Address size in bytes
+ //!< If addrType = 1: Address size in bits + uint16_t addrPos : 5; //!< \brief If addrType = 1: Bit position of address in header
+ //!< If addrType = 0: Non-zero to extend address with sync word identifier + uint16_t numAddr : 5; //!< Number of addresses in address list + } addrConf; + int8_t lenOffset; //!< Signed value to add to length field + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + uint8_t* pAddr; //!< Pointer to address list + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure + struct + { + uint8_t bEnaRssi : 1; //!< If 1, enable RSSI as a criterion + uint8_t bEnaCorr : 1; //!< If 1, enable correlation as a criterion + uint8_t operation : 1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
+ //!< 1: Busy if both RSSI and correlation indicates Busy + uint8_t busyOp : 1; //!< \brief 0: Continue carrier sense on channel Busy
+ //!< 1: End carrier sense on channel Busy
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle + uint8_t idleOp : 1; //!< \brief 0: Continue on channel Idle
+ //!< 1: End on channel Idle + uint8_t timeoutRes : 1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
+ //!< 1: Timeout with channel state Invalid treated as Idle + } csConf; + int8_t rssiThr; //!< RSSI threshold + uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is + //!< declared Idle + uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is + //!< declared Busy + uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods + struct + { + uint8_t numCorrInv : 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Idle to Invalid + uint8_t numCorrBusy : 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Invalid to Busy + } corrConfig; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } csEndTrigger; //!< Trigger classifier for ending the carrier sense + ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_SET_LEN //! @{ -#define CMD_PROP_SET_LEN 0x3401 +#define CMD_PROP_SET_LEN 0x3401 //! Set Packet Length Command struct __RFC_STRUCT rfc_CMD_PROP_SET_LEN_s { - uint16_t commandNo; //!< The command ID number 0x3401 - uint16_t rxLen; //!< Payload length to use + uint16_t commandNo; //!< The command ID number 0x3401 + uint16_t rxLen; //!< Payload length to use } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_RESTART_RX //! @{ -#define CMD_PROP_RESTART_RX 0x3402 +#define CMD_PROP_RESTART_RX 0x3402 //! Restart Packet Command struct __RFC_STRUCT rfc_CMD_PROP_RESTART_RX_s { - uint16_t commandNo; //!< The command ID number 0x3402 + uint16_t commandNo; //!< The command ID number 0x3402 } __RFC_STRUCT_ATTR; //! @} @@ -980,13 +980,13 @@ struct __RFC_STRUCT rfc_CMD_PROP_RESTART_RX_s struct __RFC_STRUCT rfc_propRxOutput_s { - uint16_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored - uint16_t nRxNok; //!< Number of packets that have been received with CRC error - uint8_t nRxIgnored; //!< Number of packets that have been received with CRC OK and ignored due to address mismatch - uint8_t nRxStopped; //!< Number of packets not received due to illegal length or address mismatch with pktConf.filterOp = 1 - uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space - int8_t lastRssi; //!< RSSI of last received packet - ratmr_t timeStamp; //!< Time stamp of last received packet + uint16_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored + uint16_t nRxNok; //!< Number of packets that have been received with CRC error + uint8_t nRxIgnored; //!< Number of packets that have been received with CRC OK and ignored due to address mismatch + uint8_t nRxStopped; //!< Number of packets not received due to illegal length or address mismatch with pktConf.filterOp = 1 + uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< RSSI of last received packet + ratmr_t timeStamp; //!< Time stamp of last received packet } __RFC_STRUCT_ATTR; //! @} @@ -997,15 +997,15 @@ struct __RFC_STRUCT rfc_propRxOutput_s struct __RFC_STRUCT rfc_propRxStatus_s { - struct - { - uint8_t addressInd: 5; //!< Index of address found (0 if not applicable) - uint8_t syncWordId: 1; //!< 0 for primary sync word, 1 for alternate sync word - uint8_t result: 2; //!< \brief 0: Packet received correctly, not ignored
- //!< 1: Packet received with CRC error
- //!< 2: Packet received correctly, but can be ignored
- //!< 3: Packet reception was aborted - } status; + struct + { + uint8_t addressInd : 5; //!< Index of address found (0 if not applicable) + uint8_t syncWordId : 1; //!< 0 for primary sync word, 1 for alternate sync word + uint8_t result : 2; //!< \brief 0: Packet received correctly, not ignored
+ //!< 1: Packet received with CRC error
+ //!< 2: Packet received correctly, but can be ignored
+ //!< 3: Packet reception was aborted + } status; } __RFC_STRUCT_ATTR; //! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_prop_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_prop_mailbox.h index 7eb264b..b009d07 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_prop_mailbox.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rf_prop_mailbox.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_prop_mailbox.h -* Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) -* Revision: 18032 -* -* Description: Definitions for proprietary mode radio interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_prop_mailbox.h + * Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) + * Revision: 18032 + * + * Description: Definitions for proprietary mode radio interface + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _PROP_MAILBOX_H #define _PROP_MAILBOX_H @@ -43,28 +43,28 @@ ///@{ /// \name Operation finished normally ///@{ -#define PROP_DONE_OK 0x3400 ///< Operation ended normally -#define PROP_DONE_RXTIMEOUT 0x3401 ///< Operation stopped after end trigger while waiting for sync -#define PROP_DONE_BREAK 0x3402 ///< Rx stopped due to timeout in the middle of a packet -#define PROP_DONE_ENDED 0x3403 ///< Operation stopped after end trigger during reception -#define PROP_DONE_STOPPED 0x3404 ///< Operation stopped after stop command -#define PROP_DONE_ABORT 0x3405 ///< Operation aborted by abort command -#define PROP_DONE_RXERR 0x3406 ///< Operation ended after receiving packet with CRC error -#define PROP_DONE_IDLE 0x3407 ///< Carrier sense operation ended because of idle channel -#define PROP_DONE_BUSY 0x3408 ///< Carrier sense operation ended because of busy channel -#define PROP_DONE_IDLETIMEOUT 0x3409 ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 1 -#define PROP_DONE_BUSYTIMEOUT 0x340A ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 0 +#define PROP_DONE_OK 0x3400 ///< Operation ended normally +#define PROP_DONE_RXTIMEOUT 0x3401 ///< Operation stopped after end trigger while waiting for sync +#define PROP_DONE_BREAK 0x3402 ///< Rx stopped due to timeout in the middle of a packet +#define PROP_DONE_ENDED 0x3403 ///< Operation stopped after end trigger during reception +#define PROP_DONE_STOPPED 0x3404 ///< Operation stopped after stop command +#define PROP_DONE_ABORT 0x3405 ///< Operation aborted by abort command +#define PROP_DONE_RXERR 0x3406 ///< Operation ended after receiving packet with CRC error +#define PROP_DONE_IDLE 0x3407 ///< Carrier sense operation ended because of idle channel +#define PROP_DONE_BUSY 0x3408 ///< Carrier sense operation ended because of busy channel +#define PROP_DONE_IDLETIMEOUT 0x3409 ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 1 +#define PROP_DONE_BUSYTIMEOUT 0x340A ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 0 ///@} /// \name Operation finished with error ///@{ -#define PROP_ERROR_PAR 0x3800 ///< Illegal parameter -#define PROP_ERROR_RXBUF 0x3801 ///< No available Rx buffer at the start of a packet -#define PROP_ERROR_RXFULL 0x3802 ///< Out of Rx buffer during reception in a partial read buffer -#define PROP_ERROR_NO_SETUP 0x3803 ///< Radio was not set up in proprietary mode -#define PROP_ERROR_NO_FS 0x3804 ///< Synth was not programmed when running Rx or Tx -#define PROP_ERROR_RXOVF 0x3805 ///< Rx overflow observed during operation -#define PROP_ERROR_TXUNF 0x3806 ///< Tx underflow observed during operation +#define PROP_ERROR_PAR 0x3800 ///< Illegal parameter +#define PROP_ERROR_RXBUF 0x3801 ///< No available Rx buffer at the start of a packet +#define PROP_ERROR_RXFULL 0x3802 ///< Out of Rx buffer during reception in a partial read buffer +#define PROP_ERROR_NO_SETUP 0x3803 ///< Radio was not set up in proprietary mode +#define PROP_ERROR_NO_FS 0x3804 ///< Synth was not programmed when running Rx or Tx +#define PROP_ERROR_RXOVF 0x3805 ///< Rx overflow observed during operation +#define PROP_ERROR_TXUNF 0x3806 ///< Tx underflow observed during operation ///@} ///@} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rfc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rfc.h index a2377ce..553afd0 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rfc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rfc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rfc.h -* Revised: 2018-08-08 14:03:25 +0200 (Wed, 08 Aug 2018) -* Revision: 52338 -* -* Description: Defines and prototypes for the RF Core. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rfc.h + * Revised: 2018-08-08 14:03:25 +0200 (Wed, 08 Aug 2018) + * Revision: 52338 + * + * Description: Defines and prototypes for the RF Core. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -53,34 +53,33 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_rfc_pwr.h" -#include "../inc/hw_rfc_dbell.h" -#include "../inc/hw_fcfg1.h" -#include "../inc/hw_adi_3_refsys.h" #include "../inc/hw_adi.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_fcfg1.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_rfc_dbell.h" +#include "../inc/hw_rfc_pwr.h" +#include "../inc/hw_types.h" +#include "rf_ble_cmd.h" #include "rf_common_cmd.h" #include "rf_prop_cmd.h" -#include "rf_ble_cmd.h" +#include +#include // Definition of RFTRIM container typedef struct { - uint32_t configIfAdc; - uint32_t configRfFrontend; - uint32_t configSynth; - uint32_t configMiscAdc; + uint32_t configIfAdc; + uint32_t configRfFrontend; + uint32_t configSynth; + uint32_t configMiscAdc; } rfTrim_t; // Definition of maximum search depth used by the RFCOverrideUpdate function -#define RFC_MAX_SEARCH_DEPTH 5 +#define RFC_MAX_SEARCH_DEPTH 5 //***************************************************************************** // @@ -96,17 +95,17 @@ typedef struct // //***************************************************************************** #if !defined(DOXYGEN) -#define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear -#define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo -#define RFCSynthPowerDown NOROM_RFCSynthPowerDown -#define RFCCpePatchReset NOROM_RFCCpePatchReset -#define RFCOverrideSearch NOROM_RFCOverrideSearch -#define RFCOverrideUpdate NOROM_RFCOverrideUpdate -#define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear -#define RFCRfTrimRead NOROM_RFCRfTrimRead -#define RFCRfTrimSet NOROM_RFCRfTrimSet -#define RFCRTrim NOROM_RFCRTrim -#define RFCAdi3VcoLdoVoltageMode NOROM_RFCAdi3VcoLdoVoltageMode +#define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear +#define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo +#define RFCSynthPowerDown NOROM_RFCSynthPowerDown +#define RFCCpePatchReset NOROM_RFCCpePatchReset +#define RFCOverrideSearch NOROM_RFCOverrideSearch +#define RFCOverrideUpdate NOROM_RFCOverrideUpdate +#define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear +#define RFCRfTrimRead NOROM_RFCRfTrimRead +#define RFCRfTrimSet NOROM_RFCRfTrimSet +#define RFCRTrim NOROM_RFCRTrim +#define RFCAdi3VcoLdoVoltageMode NOROM_RFCAdi3VcoLdoVoltageMode #endif //***************************************************************************** @@ -130,12 +129,9 @@ __STATIC_INLINE void RFCClockEnable(void) { // Enable basic clocks to get the CPE run - HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = RFC_PWR_PWMCLKEN_CPERAM - | RFC_PWR_PWMCLKEN_CPE - | RFC_PWR_PWMCLKEN_RFC; + HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = RFC_PWR_PWMCLKEN_CPERAM | RFC_PWR_PWMCLKEN_CPE | RFC_PWR_PWMCLKEN_RFC; } - //***************************************************************************** // //! \brief Disable the RF core clocks. @@ -158,7 +154,6 @@ RFCClockDisable(void) HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = 0x0; } - //***************************************************************************** // //! Clear HW interrupt flags @@ -174,7 +169,6 @@ RFCCpeIntClear(uint32_t ui32Mask) } while (HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) & ui32Mask); } - //***************************************************************************** // //! Clear CPE interrupt flags. @@ -187,7 +181,6 @@ RFCHwIntClear(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) = ~ui32Mask; } - //***************************************************************************** // //! Select interrupt sources to CPE0 (assign to INT_RFC_CPE_0 interrupt vector). @@ -200,7 +193,6 @@ RFCCpe0IntSelect(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) &= ~ui32Mask; } - //***************************************************************************** // //! Select interrupt sources to CPE1 (assign to INT_RFC_CPE_1 interrupt vector). @@ -213,7 +205,6 @@ RFCCpe1IntSelect(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) |= ui32Mask; } - //***************************************************************************** // //! Enable CPEx interrupt sources. @@ -226,7 +217,6 @@ RFCCpeIntEnable(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) |= ui32Mask; } - //***************************************************************************** // //! Select, clear, and enable interrupt sources to CPE0. @@ -245,7 +235,6 @@ RFCCpe0IntSelectClearEnable(uint32_t ui32Mask) RFCCpeIntEnable(ui32Mask); } - //***************************************************************************** // //! Select, clear, and enable interrupt sources to CPE1. @@ -264,7 +253,6 @@ RFCCpe1IntSelectClearEnable(uint32_t ui32Mask) RFCCpeIntEnable(ui32Mask); } - //***************************************************************************** // //! Enable HW interrupt sources. @@ -277,7 +265,6 @@ RFCHwIntEnable(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) |= ui32Mask; } - //***************************************************************************** // //! Disable CPE interrupt sources. @@ -290,7 +277,6 @@ RFCCpeIntDisable(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) &= ~ui32Mask; } - //***************************************************************************** // //! Disable HW interrupt sources. @@ -303,7 +289,6 @@ RFCHwIntDisable(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) &= ~ui32Mask; } - //***************************************************************************** // //! Get and clear CPE interrupt flags. @@ -311,7 +296,6 @@ RFCHwIntDisable(uint32_t ui32Mask) //***************************************************************************** extern uint32_t RFCCpeIntGetAndClear(uint32_t ui32Mask); - //***************************************************************************** // //! Clear ACK interrupt flag. @@ -324,7 +308,6 @@ RFCAckIntClear(void) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG) = 0x0; } - //***************************************************************************** // //! Send a radio operation to the doorbell and wait for an acknowledgment. @@ -332,7 +315,6 @@ RFCAckIntClear(void) //***************************************************************************** extern uint32_t RFCDoorbellSendTo(uint32_t pOp); - //***************************************************************************** // //! This function implements a fast way to turn off the synthesizer. @@ -340,7 +322,6 @@ extern uint32_t RFCDoorbellSendTo(uint32_t pOp); //***************************************************************************** extern void RFCSynthPowerDown(void); - //***************************************************************************** // //! Reset previously patched CPE RAM to a state where it can be patched again. @@ -348,7 +329,6 @@ extern void RFCSynthPowerDown(void); //***************************************************************************** extern void RFCCpePatchReset(void); - //***************************************************************************** // // Function to search an override list for the provided pattern within the search depth. @@ -356,7 +336,6 @@ extern void RFCCpePatchReset(void); //***************************************************************************** extern uint8_t RFCOverrideSearch(const uint32_t* pOverride, const uint32_t pattern, const uint32_t mask, const uint8_t searchDepth); - //***************************************************************************** // //! Function to update override list @@ -364,7 +343,6 @@ extern uint8_t RFCOverrideSearch(const uint32_t* pOverride, const uint32_t patte //***************************************************************************** extern uint8_t RFCOverrideUpdate(rfc_radioOp_t* pOpSetup, uint32_t* pParams); - //***************************************************************************** // //! Get and clear HW interrupt flags. @@ -372,14 +350,12 @@ extern uint8_t RFCOverrideUpdate(rfc_radioOp_t* pOpSetup, uint32_t* pParams); //***************************************************************************** extern uint32_t RFCHwIntGetAndClear(uint32_t ui32Mask); - //***************************************************************************** // //! Get the type of currently selected PA. // //***************************************************************************** - //***************************************************************************** // //! Read RF trim from flash using CM3. @@ -387,7 +363,6 @@ extern uint32_t RFCHwIntGetAndClear(uint32_t ui32Mask); //***************************************************************************** extern void RFCRfTrimRead(rfc_radioOp_t* pOpSetup, rfTrim_t* rfTrim); - //***************************************************************************** // //! Write preloaded RF trim values directly into CPE. @@ -395,7 +370,6 @@ extern void RFCRfTrimRead(rfc_radioOp_t* pOpSetup, rfTrim_t* rfTrim); //***************************************************************************** extern void RFCRfTrimSet(rfTrim_t* rfTrim); - //***************************************************************************** // //! Check Override RTrim vs FCFG RTrim. @@ -403,7 +377,6 @@ extern void RFCRfTrimSet(rfTrim_t* rfTrim); //***************************************************************************** extern uint8_t RFCRTrim(rfc_radioOp_t* pOpSetup); - //***************************************************************************** // //! Function to set VCOLDO reference to voltage mode. @@ -420,48 +393,48 @@ extern void RFCAdi3VcoLdoVoltageMode(bool bEnable); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_RFCCpeIntGetAndClear -#undef RFCCpeIntGetAndClear -#define RFCCpeIntGetAndClear ROM_RFCCpeIntGetAndClear +#undef RFCCpeIntGetAndClear +#define RFCCpeIntGetAndClear ROM_RFCCpeIntGetAndClear #endif #ifdef ROM_RFCDoorbellSendTo -#undef RFCDoorbellSendTo -#define RFCDoorbellSendTo ROM_RFCDoorbellSendTo +#undef RFCDoorbellSendTo +#define RFCDoorbellSendTo ROM_RFCDoorbellSendTo #endif #ifdef ROM_RFCSynthPowerDown -#undef RFCSynthPowerDown -#define RFCSynthPowerDown ROM_RFCSynthPowerDown +#undef RFCSynthPowerDown +#define RFCSynthPowerDown ROM_RFCSynthPowerDown #endif #ifdef ROM_RFCCpePatchReset -#undef RFCCpePatchReset -#define RFCCpePatchReset ROM_RFCCpePatchReset +#undef RFCCpePatchReset +#define RFCCpePatchReset ROM_RFCCpePatchReset #endif #ifdef ROM_RFCOverrideSearch -#undef RFCOverrideSearch -#define RFCOverrideSearch ROM_RFCOverrideSearch +#undef RFCOverrideSearch +#define RFCOverrideSearch ROM_RFCOverrideSearch #endif #ifdef ROM_RFCOverrideUpdate -#undef RFCOverrideUpdate -#define RFCOverrideUpdate ROM_RFCOverrideUpdate +#undef RFCOverrideUpdate +#define RFCOverrideUpdate ROM_RFCOverrideUpdate #endif #ifdef ROM_RFCHwIntGetAndClear -#undef RFCHwIntGetAndClear -#define RFCHwIntGetAndClear ROM_RFCHwIntGetAndClear +#undef RFCHwIntGetAndClear +#define RFCHwIntGetAndClear ROM_RFCHwIntGetAndClear #endif #ifdef ROM_RFCRfTrimRead -#undef RFCRfTrimRead -#define RFCRfTrimRead ROM_RFCRfTrimRead +#undef RFCRfTrimRead +#define RFCRfTrimRead ROM_RFCRfTrimRead #endif #ifdef ROM_RFCRfTrimSet -#undef RFCRfTrimSet -#define RFCRfTrimSet ROM_RFCRfTrimSet +#undef RFCRfTrimSet +#define RFCRfTrimSet ROM_RFCRfTrimSet #endif #ifdef ROM_RFCRTrim -#undef RFCRTrim -#define RFCRTrim ROM_RFCRTrim +#undef RFCRTrim +#define RFCRTrim ROM_RFCRTrim #endif #ifdef ROM_RFCAdi3VcoLdoVoltageMode -#undef RFCAdi3VcoLdoVoltageMode -#define RFCAdi3VcoLdoVoltageMode ROM_RFCAdi3VcoLdoVoltageMode +#undef RFCAdi3VcoLdoVoltageMode +#define RFCAdi3VcoLdoVoltageMode ROM_RFCAdi3VcoLdoVoltageMode #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rom.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rom.h index 885b07e..e17d186 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rom.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rom.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rom.h -* Revised: 2018-11-02 13:54:49 +0100 (Fri, 02 Nov 2018) -* Revision: 53196 -* -* Description: Prototypes for the ROM utility functions. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rom.h + * Revised: 2018-11-02 13:54:49 +0100 (Fri, 02 Nov 2018) + * Revision: 53196 + * + * Description: Prototypes for the ROM utility functions. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __ROM_H__ #define __ROM_H__ @@ -46,8 +46,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include "../inc/hw_types.h" @@ -59,183 +58,183 @@ extern "C" #define ROM_HAPI_TABLE_ADDR 0x10000048 // ROM Hard-API function interface types -typedef uint32_t (* FPTR_CRC32_T) ( uint8_t* /* pui8Data */, \ - uint32_t /* ui32ByteCount */, \ - uint32_t /* ui32RepeatCount */); +typedef uint32_t (*FPTR_CRC32_T)(uint8_t* /* pui8Data */, + uint32_t /* ui32ByteCount */, + uint32_t /* ui32RepeatCount */); -typedef uint32_t (* FPTR_GETFLSIZE_T) ( void ); +typedef uint32_t (*FPTR_GETFLSIZE_T)(void); -typedef uint32_t (* FPTR_GETCHIPID_T) ( void ); +typedef uint32_t (*FPTR_GETCHIPID_T)(void); -typedef uint32_t (* FPTR_RESERVED1_T) ( uint32_t ); +typedef uint32_t (*FPTR_RESERVED1_T)(uint32_t); -typedef uint32_t (* FPTR_RESERVED2_T) ( void ); +typedef uint32_t (*FPTR_RESERVED2_T)(void); -typedef uint32_t (* FPTR_RESERVED3_T) ( uint8_t*, \ - uint32_t, \ - uint32_t ); -typedef void (* FPTR_RESETDEV_T) ( void ); +typedef uint32_t (*FPTR_RESERVED3_T)(uint8_t*, + uint32_t, + uint32_t); +typedef void (*FPTR_RESETDEV_T)(void); -typedef uint32_t (* FPTR_FLETCHER32_T) ( uint16_t* /* pui16Data */, \ - uint16_t /* ui16WordCount */, \ - uint16_t /* ui16RepeatCount */); +typedef uint32_t (*FPTR_FLETCHER32_T)(uint16_t* /* pui16Data */, + uint16_t /* ui16WordCount */, + uint16_t /* ui16RepeatCount */); -typedef uint32_t (* FPTR_MINVAL_T) ( uint32_t* /* ulpDataBuffer */, \ - uint32_t /* ui32DataCount */); +typedef uint32_t (*FPTR_MINVAL_T)(uint32_t* /* ulpDataBuffer */, + uint32_t /* ui32DataCount */); -typedef uint32_t (* FPTR_MAXVAL_T) ( uint32_t* /* pui32DataBuffer */, \ - uint32_t /* ui32DataCount */); +typedef uint32_t (*FPTR_MAXVAL_T)(uint32_t* /* pui32DataBuffer */, + uint32_t /* ui32DataCount */); -typedef uint32_t (* FPTR_MEANVAL_T) ( uint32_t* /* pui32DataBuffer */, \ - uint32_t /* ui32DataCount */); +typedef uint32_t (*FPTR_MEANVAL_T)(uint32_t* /* pui32DataBuffer */, + uint32_t /* ui32DataCount */); -typedef uint32_t (* FPTR_STDDVAL_T) ( uint32_t* /* pui32DataBuffer */, \ - uint32_t /* ui32DataCount */); +typedef uint32_t (*FPTR_STDDVAL_T)(uint32_t* /* pui32DataBuffer */, + uint32_t /* ui32DataCount */); -typedef void (* FPTR_HFSOURCESAFESWITCH_T) ( void ); +typedef void (*FPTR_HFSOURCESAFESWITCH_T)(void); -typedef void (* FPTR_RESERVED4_T) ( uint32_t ); +typedef void (*FPTR_RESERVED4_T)(uint32_t); -typedef void (* FPTR_RESERVED5_T) ( uint32_t ); +typedef void (*FPTR_RESERVED5_T)(uint32_t); -typedef void (* FPTR_COMPAIN_T) ( uint8_t /* ut8Signal */); +typedef void (*FPTR_COMPAIN_T)(uint8_t /* ut8Signal */); -typedef void (* FPTR_COMPAREF_T) ( uint8_t /* ut8Signal */); +typedef void (*FPTR_COMPAREF_T)(uint8_t /* ut8Signal */); -typedef void (* FPTR_ADCCOMPBIN_T) ( uint8_t /* ut8Signal */); +typedef void (*FPTR_ADCCOMPBIN_T)(uint8_t /* ut8Signal */); -typedef void (* FPTR_COMPBREF_T) ( uint8_t /* ut8Signal */); +typedef void (*FPTR_COMPBREF_T)(uint8_t /* ut8Signal */); extern uint32_t MemBusWrkAroundHapiProgramFlash(uint8_t* pui8DataBuffer, - uint32_t ui32Address, - uint32_t ui32Count); + uint32_t ui32Address, + uint32_t ui32Count); extern uint32_t MemBusWrkAroundHapiEraseSector(uint32_t ui32Address); // ROM Hard-API access table type typedef struct { - FPTR_CRC32_T Crc32; - FPTR_GETFLSIZE_T FlashGetSize; - FPTR_GETCHIPID_T GetChipId; - FPTR_RESERVED1_T ReservedLocation1; - FPTR_RESERVED2_T ReservedLocation2; - FPTR_RESERVED3_T ReservedLocation3; - FPTR_RESETDEV_T ResetDevice; - FPTR_FLETCHER32_T Fletcher32; - FPTR_MINVAL_T MinValue; - FPTR_MAXVAL_T MaxValue; - FPTR_MEANVAL_T MeanValue; - FPTR_STDDVAL_T StandDeviationValue; - FPTR_RESERVED4_T ReservedLocation4; - FPTR_RESERVED5_T ReservedLocation5; - FPTR_HFSOURCESAFESWITCH_T HFSourceSafeSwitch; - FPTR_COMPAIN_T SelectCompAInput; - FPTR_COMPAREF_T SelectCompARef; - FPTR_ADCCOMPBIN_T SelectADCCompBInput; - FPTR_COMPBREF_T SelectCompBRef; + FPTR_CRC32_T Crc32; + FPTR_GETFLSIZE_T FlashGetSize; + FPTR_GETCHIPID_T GetChipId; + FPTR_RESERVED1_T ReservedLocation1; + FPTR_RESERVED2_T ReservedLocation2; + FPTR_RESERVED3_T ReservedLocation3; + FPTR_RESETDEV_T ResetDevice; + FPTR_FLETCHER32_T Fletcher32; + FPTR_MINVAL_T MinValue; + FPTR_MAXVAL_T MaxValue; + FPTR_MEANVAL_T MeanValue; + FPTR_STDDVAL_T StandDeviationValue; + FPTR_RESERVED4_T ReservedLocation4; + FPTR_RESERVED5_T ReservedLocation5; + FPTR_HFSOURCESAFESWITCH_T HFSourceSafeSwitch; + FPTR_COMPAIN_T SelectCompAInput; + FPTR_COMPAREF_T SelectCompARef; + FPTR_ADCCOMPBIN_T SelectADCCompBInput; + FPTR_COMPBREF_T SelectCompBRef; } HARD_API_T; // Pointer to the ROM HAPI table -#define P_HARD_API ((HARD_API_T*) ROM_HAPI_TABLE_ADDR) +#define P_HARD_API ((HARD_API_T*)ROM_HAPI_TABLE_ADDR) // Add wrapper around the Hapi functions needing the "bus arbitration issue" workaround -extern void SafeHapiVoid( FPTR_VOID_VOID_T fPtr ); -extern void SafeHapiAuxAdiSelect( FPTR_VOID_UINT8_T fPtr, uint8_t ut8Signal ); +extern void SafeHapiVoid(FPTR_VOID_VOID_T fPtr); +extern void SafeHapiAuxAdiSelect(FPTR_VOID_UINT8_T fPtr, uint8_t ut8Signal); -#define HapiCrc32(a,b,c) P_HARD_API->Crc32(a,b,c) -#define HapiGetFlashSize() P_HARD_API->FlashGetSize() -#define HapiGetChipId() P_HARD_API->GetChipId() -#define HapiSectorErase(a) MemBusWrkAroundHapiEraseSector(a) -#define HapiProgramFlash(a,b,c) MemBusWrkAroundHapiProgramFlash(a,b,c) -#define HapiResetDevice() P_HARD_API->ResetDevice() -#define HapiFletcher32(a,b,c) P_HARD_API->Fletcher32(a,b,c) -#define HapiMinValue(a,b) P_HARD_API->MinValue(a,b) -#define HapiMaxValue(a,b) P_HARD_API->MaxValue(a,b) -#define HapiMeanValue(a,b) P_HARD_API->MeanValue(a,b) -#define HapiStandDeviationValue(a,b) P_HARD_API->StandDeviationValue(a,b) -#define HapiHFSourceSafeSwitch() SafeHapiVoid( P_HARD_API->HFSourceSafeSwitch ) -#define HapiSelectCompAInput(a) SafeHapiAuxAdiSelect( P_HARD_API->SelectCompAInput , a ) -#define HapiSelectCompARef(a) SafeHapiAuxAdiSelect( P_HARD_API->SelectCompARef , a ) -#define HapiSelectADCCompBInput(a) SafeHapiAuxAdiSelect( P_HARD_API->SelectADCCompBInput, a ) -#define HapiSelectCompBRef(a) SafeHapiAuxAdiSelect( P_HARD_API->SelectCompBRef , a ) +#define HapiCrc32(a, b, c) P_HARD_API->Crc32(a, b, c) +#define HapiGetFlashSize() P_HARD_API->FlashGetSize() +#define HapiGetChipId() P_HARD_API->GetChipId() +#define HapiSectorErase(a) MemBusWrkAroundHapiEraseSector(a) +#define HapiProgramFlash(a, b, c) MemBusWrkAroundHapiProgramFlash(a, b, c) +#define HapiResetDevice() P_HARD_API->ResetDevice() +#define HapiFletcher32(a, b, c) P_HARD_API->Fletcher32(a, b, c) +#define HapiMinValue(a, b) P_HARD_API->MinValue(a, b) +#define HapiMaxValue(a, b) P_HARD_API->MaxValue(a, b) +#define HapiMeanValue(a, b) P_HARD_API->MeanValue(a, b) +#define HapiStandDeviationValue(a, b) P_HARD_API->StandDeviationValue(a, b) +#define HapiHFSourceSafeSwitch() SafeHapiVoid(P_HARD_API->HFSourceSafeSwitch) +#define HapiSelectCompAInput(a) SafeHapiAuxAdiSelect(P_HARD_API->SelectCompAInput, a) +#define HapiSelectCompARef(a) SafeHapiAuxAdiSelect(P_HARD_API->SelectCompARef, a) +#define HapiSelectADCCompBInput(a) SafeHapiAuxAdiSelect(P_HARD_API->SelectADCCompBInput, a) +#define HapiSelectCompBRef(a) SafeHapiAuxAdiSelect(P_HARD_API->SelectCompBRef, a) // Defines for input parameter to the HapiSelectCompAInput function. -#define COMPA_IN_NC 0x00 +#define COMPA_IN_NC 0x00 // Defines used in CC13x0/CC26x0 devices -#define COMPA_IN_AUXIO7 0x09 -#define COMPA_IN_AUXIO6 0x0A -#define COMPA_IN_AUXIO5 0x0B -#define COMPA_IN_AUXIO4 0x0C -#define COMPA_IN_AUXIO3 0x0D -#define COMPA_IN_AUXIO2 0x0E -#define COMPA_IN_AUXIO1 0x0F -#define COMPA_IN_AUXIO0 0x10 +#define COMPA_IN_AUXIO7 0x09 +#define COMPA_IN_AUXIO6 0x0A +#define COMPA_IN_AUXIO5 0x0B +#define COMPA_IN_AUXIO4 0x0C +#define COMPA_IN_AUXIO3 0x0D +#define COMPA_IN_AUXIO2 0x0E +#define COMPA_IN_AUXIO1 0x0F +#define COMPA_IN_AUXIO0 0x10 // Defines used in CC13x2/CC26x2 devices -#define COMPA_IN_AUXIO26 COMPA_IN_AUXIO7 -#define COMPA_IN_AUXIO25 COMPA_IN_AUXIO6 -#define COMPA_IN_AUXIO24 COMPA_IN_AUXIO5 -#define COMPA_IN_AUXIO23 COMPA_IN_AUXIO4 -#define COMPA_IN_AUXIO22 COMPA_IN_AUXIO3 -#define COMPA_IN_AUXIO21 COMPA_IN_AUXIO2 -#define COMPA_IN_AUXIO20 COMPA_IN_AUXIO1 -#define COMPA_IN_AUXIO19 COMPA_IN_AUXIO0 +#define COMPA_IN_AUXIO26 COMPA_IN_AUXIO7 +#define COMPA_IN_AUXIO25 COMPA_IN_AUXIO6 +#define COMPA_IN_AUXIO24 COMPA_IN_AUXIO5 +#define COMPA_IN_AUXIO23 COMPA_IN_AUXIO4 +#define COMPA_IN_AUXIO22 COMPA_IN_AUXIO3 +#define COMPA_IN_AUXIO21 COMPA_IN_AUXIO2 +#define COMPA_IN_AUXIO20 COMPA_IN_AUXIO1 +#define COMPA_IN_AUXIO19 COMPA_IN_AUXIO0 // Defines for input parameter to the HapiSelectCompARef function. -#define COMPA_REF_NC 0x00 -#define COMPA_REF_DCOUPL 0x01 -#define COMPA_REF_VSS 0x02 -#define COMPA_REF_VDDS 0x03 -#define COMPA_REF_ADCVREFP 0x04 +#define COMPA_REF_NC 0x00 +#define COMPA_REF_DCOUPL 0x01 +#define COMPA_REF_VSS 0x02 +#define COMPA_REF_VDDS 0x03 +#define COMPA_REF_ADCVREFP 0x04 // Defines used in CC13x0/CC26x0 devices -#define COMPA_REF_AUXIO7 0x09 -#define COMPA_REF_AUXIO6 0x0A -#define COMPA_REF_AUXIO5 0x0B -#define COMPA_REF_AUXIO4 0x0C -#define COMPA_REF_AUXIO3 0x0D -#define COMPA_REF_AUXIO2 0x0E -#define COMPA_REF_AUXIO1 0x0F -#define COMPA_REF_AUXIO0 0x10 +#define COMPA_REF_AUXIO7 0x09 +#define COMPA_REF_AUXIO6 0x0A +#define COMPA_REF_AUXIO5 0x0B +#define COMPA_REF_AUXIO4 0x0C +#define COMPA_REF_AUXIO3 0x0D +#define COMPA_REF_AUXIO2 0x0E +#define COMPA_REF_AUXIO1 0x0F +#define COMPA_REF_AUXIO0 0x10 // Defines used in CC13x2/CC26x2 devices -#define COMPA_REF_AUXIO26 COMPA_REF_AUXIO7 -#define COMPA_REF_AUXIO25 COMPA_REF_AUXIO6 -#define COMPA_REF_AUXIO24 COMPA_REF_AUXIO5 -#define COMPA_REF_AUXIO23 COMPA_REF_AUXIO4 -#define COMPA_REF_AUXIO22 COMPA_REF_AUXIO3 -#define COMPA_REF_AUXIO21 COMPA_REF_AUXIO2 -#define COMPA_REF_AUXIO20 COMPA_REF_AUXIO1 -#define COMPA_REF_AUXIO19 COMPA_REF_AUXIO0 +#define COMPA_REF_AUXIO26 COMPA_REF_AUXIO7 +#define COMPA_REF_AUXIO25 COMPA_REF_AUXIO6 +#define COMPA_REF_AUXIO24 COMPA_REF_AUXIO5 +#define COMPA_REF_AUXIO23 COMPA_REF_AUXIO4 +#define COMPA_REF_AUXIO22 COMPA_REF_AUXIO3 +#define COMPA_REF_AUXIO21 COMPA_REF_AUXIO2 +#define COMPA_REF_AUXIO20 COMPA_REF_AUXIO1 +#define COMPA_REF_AUXIO19 COMPA_REF_AUXIO0 // Defines for input parameter to the HapiSelectADCCompBInput function. -#define ADC_COMPB_IN_NC 0x00 -#define ADC_COMPB_IN_DCOUPL 0x03 -#define ADC_COMPB_IN_VSS 0x04 -#define ADC_COMPB_IN_VDDS 0x05 +#define ADC_COMPB_IN_NC 0x00 +#define ADC_COMPB_IN_DCOUPL 0x03 +#define ADC_COMPB_IN_VSS 0x04 +#define ADC_COMPB_IN_VDDS 0x05 // Defines used in CC13x0/CC26x0 devices -#define ADC_COMPB_IN_AUXIO7 0x09 -#define ADC_COMPB_IN_AUXIO6 0x0A -#define ADC_COMPB_IN_AUXIO5 0x0B -#define ADC_COMPB_IN_AUXIO4 0x0C -#define ADC_COMPB_IN_AUXIO3 0x0D -#define ADC_COMPB_IN_AUXIO2 0x0E -#define ADC_COMPB_IN_AUXIO1 0x0F -#define ADC_COMPB_IN_AUXIO0 0x10 +#define ADC_COMPB_IN_AUXIO7 0x09 +#define ADC_COMPB_IN_AUXIO6 0x0A +#define ADC_COMPB_IN_AUXIO5 0x0B +#define ADC_COMPB_IN_AUXIO4 0x0C +#define ADC_COMPB_IN_AUXIO3 0x0D +#define ADC_COMPB_IN_AUXIO2 0x0E +#define ADC_COMPB_IN_AUXIO1 0x0F +#define ADC_COMPB_IN_AUXIO0 0x10 // Defines used in CC13x2/CC26x2 devices -#define ADC_COMPB_IN_AUXIO26 ADC_COMPB_IN_AUXIO7 -#define ADC_COMPB_IN_AUXIO25 ADC_COMPB_IN_AUXIO6 -#define ADC_COMPB_IN_AUXIO24 ADC_COMPB_IN_AUXIO5 -#define ADC_COMPB_IN_AUXIO23 ADC_COMPB_IN_AUXIO4 -#define ADC_COMPB_IN_AUXIO22 ADC_COMPB_IN_AUXIO3 -#define ADC_COMPB_IN_AUXIO21 ADC_COMPB_IN_AUXIO2 -#define ADC_COMPB_IN_AUXIO20 ADC_COMPB_IN_AUXIO1 -#define ADC_COMPB_IN_AUXIO19 ADC_COMPB_IN_AUXIO0 +#define ADC_COMPB_IN_AUXIO26 ADC_COMPB_IN_AUXIO7 +#define ADC_COMPB_IN_AUXIO25 ADC_COMPB_IN_AUXIO6 +#define ADC_COMPB_IN_AUXIO24 ADC_COMPB_IN_AUXIO5 +#define ADC_COMPB_IN_AUXIO23 ADC_COMPB_IN_AUXIO4 +#define ADC_COMPB_IN_AUXIO22 ADC_COMPB_IN_AUXIO3 +#define ADC_COMPB_IN_AUXIO21 ADC_COMPB_IN_AUXIO2 +#define ADC_COMPB_IN_AUXIO20 ADC_COMPB_IN_AUXIO1 +#define ADC_COMPB_IN_AUXIO19 ADC_COMPB_IN_AUXIO0 // Defines for input parameter to the HapiSelectCompBRef function. // The define values can not be changed! -#define COMPB_REF_NC 0x00 -#define COMPB_REF_DCOUPL 0x01 -#define COMPB_REF_VSS 0x02 -#define COMPB_REF_VDDS 0x03 +#define COMPB_REF_NC 0x00 +#define COMPB_REF_DCOUPL 0x01 +#define COMPB_REF_VSS 0x02 +#define COMPB_REF_VDDS 0x03 #endif // __HAPI_H__ @@ -244,454 +243,435 @@ extern void SafeHapiAuxAdiSelect( FPTR_VOID_UINT8_T fPtr, uint8_t ut8Signal ); // Pointers to the main API tables. // //***************************************************************************** -#define ROM_API_TABLE ((uint32_t *) 0x10000180) -#define ROM_VERSION (ROM_API_TABLE[0]) +#define ROM_API_TABLE ((uint32_t*)0x10000180) +#define ROM_VERSION (ROM_API_TABLE[0]) - -#define ROM_API_AON_EVENT_TABLE ((uint32_t*) (ROM_API_TABLE[1])) -#define ROM_API_AON_IOC_TABLE ((uint32_t*) (ROM_API_TABLE[2])) -#define ROM_API_AON_RTC_TABLE ((uint32_t*) (ROM_API_TABLE[3])) -#define ROM_API_AON_WUC_TABLE ((uint32_t*) (ROM_API_TABLE[4])) -#define ROM_API_AUX_CTRL_TABLE ((uint32_t*) (ROM_API_TABLE[5])) -#define ROM_API_AUX_TDC_TABLE ((uint32_t*) (ROM_API_TABLE[6])) -#define ROM_API_AUX_TIMER_TABLE ((uint32_t*) (ROM_API_TABLE[7])) -#define ROM_API_AUX_WUC_TABLE ((uint32_t*) (ROM_API_TABLE[8])) -#define ROM_API_DDI_TABLE ((uint32_t*) (ROM_API_TABLE[9])) -#define ROM_API_FLASH_TABLE ((uint32_t*) (ROM_API_TABLE[10])) -#define ROM_API_I2C_TABLE ((uint32_t*) (ROM_API_TABLE[11])) -#define ROM_API_INTERRUPT_TABLE ((uint32_t*) (ROM_API_TABLE[12])) -#define ROM_API_IOC_TABLE ((uint32_t*) (ROM_API_TABLE[13])) -#define ROM_API_PRCM_TABLE ((uint32_t*) (ROM_API_TABLE[14])) -#define ROM_API_SMPH_TABLE ((uint32_t*) (ROM_API_TABLE[15])) -#define ROM_API_SSI_TABLE ((uint32_t*) (ROM_API_TABLE[17])) -#define ROM_API_TIMER_TABLE ((uint32_t*) (ROM_API_TABLE[18])) -#define ROM_API_TRNG_TABLE ((uint32_t*) (ROM_API_TABLE[19])) -#define ROM_API_UART_TABLE ((uint32_t*) (ROM_API_TABLE[20])) -#define ROM_API_UDMA_TABLE ((uint32_t*) (ROM_API_TABLE[21])) -#define ROM_API_VIMS_TABLE ((uint32_t*) (ROM_API_TABLE[22])) +#define ROM_API_AON_EVENT_TABLE ((uint32_t*)(ROM_API_TABLE[1])) +#define ROM_API_AON_IOC_TABLE ((uint32_t*)(ROM_API_TABLE[2])) +#define ROM_API_AON_RTC_TABLE ((uint32_t*)(ROM_API_TABLE[3])) +#define ROM_API_AON_WUC_TABLE ((uint32_t*)(ROM_API_TABLE[4])) +#define ROM_API_AUX_CTRL_TABLE ((uint32_t*)(ROM_API_TABLE[5])) +#define ROM_API_AUX_TDC_TABLE ((uint32_t*)(ROM_API_TABLE[6])) +#define ROM_API_AUX_TIMER_TABLE ((uint32_t*)(ROM_API_TABLE[7])) +#define ROM_API_AUX_WUC_TABLE ((uint32_t*)(ROM_API_TABLE[8])) +#define ROM_API_DDI_TABLE ((uint32_t*)(ROM_API_TABLE[9])) +#define ROM_API_FLASH_TABLE ((uint32_t*)(ROM_API_TABLE[10])) +#define ROM_API_I2C_TABLE ((uint32_t*)(ROM_API_TABLE[11])) +#define ROM_API_INTERRUPT_TABLE ((uint32_t*)(ROM_API_TABLE[12])) +#define ROM_API_IOC_TABLE ((uint32_t*)(ROM_API_TABLE[13])) +#define ROM_API_PRCM_TABLE ((uint32_t*)(ROM_API_TABLE[14])) +#define ROM_API_SMPH_TABLE ((uint32_t*)(ROM_API_TABLE[15])) +#define ROM_API_SSI_TABLE ((uint32_t*)(ROM_API_TABLE[17])) +#define ROM_API_TIMER_TABLE ((uint32_t*)(ROM_API_TABLE[18])) +#define ROM_API_TRNG_TABLE ((uint32_t*)(ROM_API_TABLE[19])) +#define ROM_API_UART_TABLE ((uint32_t*)(ROM_API_TABLE[20])) +#define ROM_API_UDMA_TABLE ((uint32_t*)(ROM_API_TABLE[21])) +#define ROM_API_VIMS_TABLE ((uint32_t*)(ROM_API_TABLE[22])) // AON_EVENT FUNCTIONS -#define ROM_AONEventMcuWakeUpSet \ +#define ROM_AONEventMcuWakeUpSet \ ((void (*)(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc)) \ - ROM_API_AON_EVENT_TABLE[0]) + ROM_API_AON_EVENT_TABLE[0]) -#define ROM_AONEventMcuWakeUpGet \ - ((uint32_t (*)(uint32_t ui32MCUWUEvent)) \ - ROM_API_AON_EVENT_TABLE[1]) +#define ROM_AONEventMcuWakeUpGet \ + ((uint32_t(*)(uint32_t ui32MCUWUEvent)) \ + ROM_API_AON_EVENT_TABLE[1]) -#define ROM_AONEventAuxWakeUpSet \ +#define ROM_AONEventAuxWakeUpSet \ ((void (*)(uint32_t ui32AUXWUEvent, uint32_t ui32EventSrc)) \ - ROM_API_AON_EVENT_TABLE[2]) + ROM_API_AON_EVENT_TABLE[2]) -#define ROM_AONEventAuxWakeUpGet \ - ((uint32_t (*)(uint32_t ui32AUXWUEvent)) \ - ROM_API_AON_EVENT_TABLE[3]) +#define ROM_AONEventAuxWakeUpGet \ + ((uint32_t(*)(uint32_t ui32AUXWUEvent)) \ + ROM_API_AON_EVENT_TABLE[3]) -#define ROM_AONEventMcuSet \ +#define ROM_AONEventMcuSet \ ((void (*)(uint32_t ui32MCUEvent, uint32_t ui32EventSrc)) \ - ROM_API_AON_EVENT_TABLE[4]) - -#define ROM_AONEventMcuGet \ - ((uint32_t (*)(uint32_t ui32MCUEvent)) \ - ROM_API_AON_EVENT_TABLE[5]) + ROM_API_AON_EVENT_TABLE[4]) +#define ROM_AONEventMcuGet \ + ((uint32_t(*)(uint32_t ui32MCUEvent)) \ + ROM_API_AON_EVENT_TABLE[5]) // AON_WUC FUNCTIONS #define ROM_AONWUCAuxReset \ - ((void (*)(void)) \ - ROM_API_AON_WUC_TABLE[3]) + ((void (*)(void)) \ + ROM_API_AON_WUC_TABLE[3]) -#define ROM_AONWUCRechargeCtrlConfigSet \ +#define ROM_AONWUCRechargeCtrlConfigSet \ ((void (*)(bool bAdaptEnable, uint32_t ui32AdaptRate, uint32_t ui32Period, uint32_t ui32MaxPeriod)) \ - ROM_API_AON_WUC_TABLE[4]) + ROM_API_AON_WUC_TABLE[4]) -#define ROM_AONWUCOscConfig \ +#define ROM_AONWUCOscConfig \ ((void (*)(uint32_t ui32Period)) \ - ROM_API_AON_WUC_TABLE[5]) - + ROM_API_AON_WUC_TABLE[5]) // AUX_TDC FUNCTIONS -#define ROM_AUXTDCConfigSet \ +#define ROM_AUXTDCConfigSet \ ((void (*)(uint32_t ui32Base, uint32_t ui32StartCondition, uint32_t ui32StopCondition)) \ - ROM_API_AUX_TDC_TABLE[0]) - -#define ROM_AUXTDCMeasurementDone \ - ((uint32_t (*)(uint32_t ui32Base)) \ - ROM_API_AUX_TDC_TABLE[1]) + ROM_API_AUX_TDC_TABLE[0]) +#define ROM_AUXTDCMeasurementDone \ + ((uint32_t(*)(uint32_t ui32Base)) \ + ROM_API_AUX_TDC_TABLE[1]) // AUX_WUC FUNCTIONS -#define ROM_AUXWUCClockEnable \ +#define ROM_AUXWUCClockEnable \ ((void (*)(uint32_t ui32Clocks)) \ - ROM_API_AUX_WUC_TABLE[0]) + ROM_API_AUX_WUC_TABLE[0]) -#define ROM_AUXWUCClockDisable \ +#define ROM_AUXWUCClockDisable \ ((void (*)(uint32_t ui32Clocks)) \ - ROM_API_AUX_WUC_TABLE[1]) + ROM_API_AUX_WUC_TABLE[1]) -#define ROM_AUXWUCClockStatus \ - ((uint32_t (*)(uint32_t ui32Clocks)) \ - ROM_API_AUX_WUC_TABLE[2]) +#define ROM_AUXWUCClockStatus \ + ((uint32_t(*)(uint32_t ui32Clocks)) \ + ROM_API_AUX_WUC_TABLE[2]) -#define ROM_AUXWUCPowerCtrl \ +#define ROM_AUXWUCPowerCtrl \ ((void (*)(uint32_t ui32PowerMode)) \ - ROM_API_AUX_WUC_TABLE[3]) - + ROM_API_AUX_WUC_TABLE[3]) // DDI FUNCTIONS -#define ROM_DDI16BitWrite \ +#define ROM_DDI16BitWrite \ ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32WrData)) \ - ROM_API_DDI_TABLE[0]) + ROM_API_DDI_TABLE[0]) -#define ROM_DDI16BitfieldWrite \ +#define ROM_DDI16BitfieldWrite \ ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift, uint16_t ui32Data)) \ - ROM_API_DDI_TABLE[1]) + ROM_API_DDI_TABLE[1]) -#define ROM_DDI16BitRead \ - ((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask)) \ - ROM_API_DDI_TABLE[2]) - -#define ROM_DDI16BitfieldRead \ - ((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift)) \ - ROM_API_DDI_TABLE[3]) +#define ROM_DDI16BitRead \ + ((uint16_t(*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask)) \ + ROM_API_DDI_TABLE[2]) +#define ROM_DDI16BitfieldRead \ + ((uint16_t(*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift)) \ + ROM_API_DDI_TABLE[3]) // FLASH FUNCTIONS #define ROM_FlashPowerModeGet \ - ((uint32_t (*)(void)) \ - ROM_API_FLASH_TABLE[1]) + ((uint32_t(*)(void)) \ + ROM_API_FLASH_TABLE[1]) -#define ROM_FlashProtectionSet \ +#define ROM_FlashProtectionSet \ ((void (*)(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode)) \ - ROM_API_FLASH_TABLE[2]) + ROM_API_FLASH_TABLE[2]) -#define ROM_FlashProtectionGet \ - ((uint32_t (*)(uint32_t ui32SectorAddress)) \ - ROM_API_FLASH_TABLE[3]) +#define ROM_FlashProtectionGet \ + ((uint32_t(*)(uint32_t ui32SectorAddress)) \ + ROM_API_FLASH_TABLE[3]) -#define ROM_FlashProtectionSave \ - ((uint32_t (*)(uint32_t ui32SectorAddress)) \ - ROM_API_FLASH_TABLE[4]) +#define ROM_FlashProtectionSave \ + ((uint32_t(*)(uint32_t ui32SectorAddress)) \ + ROM_API_FLASH_TABLE[4]) -#define ROM_FlashEfuseReadRow \ - ((bool (*)(uint32_t *pui32EfuseData, uint32_t ui32RowAddress)) \ - ROM_API_FLASH_TABLE[8]) +#define ROM_FlashEfuseReadRow \ + ((bool (*)(uint32_t * pui32EfuseData, uint32_t ui32RowAddress)) \ + ROM_API_FLASH_TABLE[8]) #define ROM_FlashDisableSectorsForWrite \ - ((void (*)(void)) \ - ROM_API_FLASH_TABLE[9]) - + ((void (*)(void)) \ + ROM_API_FLASH_TABLE[9]) // I2C FUNCTIONS -#define ROM_I2CMasterInitExpClk \ +#define ROM_I2CMasterInitExpClk \ ((void (*)(uint32_t ui32Base, uint32_t ui32I2CClk, bool bFast)) \ - ROM_API_I2C_TABLE[0]) - -#define ROM_I2CMasterErr \ - ((uint32_t (*)(uint32_t ui32Base)) \ - ROM_API_I2C_TABLE[1]) + ROM_API_I2C_TABLE[0]) +#define ROM_I2CMasterErr \ + ((uint32_t(*)(uint32_t ui32Base)) \ + ROM_API_I2C_TABLE[1]) // INTERRUPT FUNCTIONS #define ROM_IntPriorityGroupingSet \ ((void (*)(uint32_t ui32Bits)) \ - ROM_API_INTERRUPT_TABLE[0]) + ROM_API_INTERRUPT_TABLE[0]) #define ROM_IntPriorityGroupingGet \ - ((uint32_t (*)(void)) \ - ROM_API_INTERRUPT_TABLE[1]) + ((uint32_t(*)(void)) \ + ROM_API_INTERRUPT_TABLE[1]) -#define ROM_IntPrioritySet \ +#define ROM_IntPrioritySet \ ((void (*)(uint32_t ui32Interrupt, uint8_t ui8Priority)) \ - ROM_API_INTERRUPT_TABLE[2]) + ROM_API_INTERRUPT_TABLE[2]) -#define ROM_IntPriorityGet \ - ((int32_t (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[3]) +#define ROM_IntPriorityGet \ + ((int32_t(*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[3]) -#define ROM_IntEnable \ +#define ROM_IntEnable \ ((void (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[4]) + ROM_API_INTERRUPT_TABLE[4]) -#define ROM_IntDisable \ +#define ROM_IntDisable \ ((void (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[5]) + ROM_API_INTERRUPT_TABLE[5]) -#define ROM_IntPendSet \ +#define ROM_IntPendSet \ ((void (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[6]) + ROM_API_INTERRUPT_TABLE[6]) -#define ROM_IntPendGet \ +#define ROM_IntPendGet \ ((bool (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[7]) + ROM_API_INTERRUPT_TABLE[7]) -#define ROM_IntPendClear \ +#define ROM_IntPendClear \ ((void (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[8]) - + ROM_API_INTERRUPT_TABLE[8]) // IOC FUNCTIONS -#define ROM_IOCPortConfigureSet \ +#define ROM_IOCPortConfigureSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId, uint32_t ui32IOConfig)) \ - ROM_API_IOC_TABLE[0]) + ROM_API_IOC_TABLE[0]) -#define ROM_IOCPortConfigureGet \ - ((uint32_t (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[1]) +#define ROM_IOCPortConfigureGet \ + ((uint32_t(*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[1]) -#define ROM_IOCIOShutdownSet \ +#define ROM_IOCIOShutdownSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32IOShutdown)) \ - ROM_API_IOC_TABLE[2]) + ROM_API_IOC_TABLE[2]) -#define ROM_IOCIOModeSet \ +#define ROM_IOCIOModeSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32IOMode)) \ - ROM_API_IOC_TABLE[4]) + ROM_API_IOC_TABLE[4]) -#define ROM_IOCIOIntSet \ +#define ROM_IOCIOIntSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet)) \ - ROM_API_IOC_TABLE[5]) + ROM_API_IOC_TABLE[5]) -#define ROM_IOCIOPortPullSet \ +#define ROM_IOCIOPortPullSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32Pull)) \ - ROM_API_IOC_TABLE[6]) + ROM_API_IOC_TABLE[6]) -#define ROM_IOCIOHystSet \ +#define ROM_IOCIOHystSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32Hysteresis)) \ - ROM_API_IOC_TABLE[7]) + ROM_API_IOC_TABLE[7]) -#define ROM_IOCIOInputSet \ +#define ROM_IOCIOInputSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32Input)) \ - ROM_API_IOC_TABLE[8]) + ROM_API_IOC_TABLE[8]) -#define ROM_IOCIOSlewCtrlSet \ +#define ROM_IOCIOSlewCtrlSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32SlewEnable)) \ - ROM_API_IOC_TABLE[9]) + ROM_API_IOC_TABLE[9]) -#define ROM_IOCIODrvStrengthSet \ +#define ROM_IOCIODrvStrengthSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32IOCurrent, uint32_t ui32DrvStrength)) \ - ROM_API_IOC_TABLE[10]) + ROM_API_IOC_TABLE[10]) -#define ROM_IOCIOPortIdSet \ +#define ROM_IOCIOPortIdSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId)) \ - ROM_API_IOC_TABLE[11]) + ROM_API_IOC_TABLE[11]) -#define ROM_IOCIntEnable \ +#define ROM_IOCIntEnable \ ((void (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[12]) + ROM_API_IOC_TABLE[12]) -#define ROM_IOCIntDisable \ +#define ROM_IOCIntDisable \ ((void (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[13]) + ROM_API_IOC_TABLE[13]) -#define ROM_IOCPinTypeGpioInput \ +#define ROM_IOCPinTypeGpioInput \ ((void (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[14]) + ROM_API_IOC_TABLE[14]) -#define ROM_IOCPinTypeGpioOutput \ +#define ROM_IOCPinTypeGpioOutput \ ((void (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[15]) + ROM_API_IOC_TABLE[15]) -#define ROM_IOCPinTypeUart \ +#define ROM_IOCPinTypeUart \ ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Cts, uint32_t ui32Rts)) \ - ROM_API_IOC_TABLE[16]) + ROM_API_IOC_TABLE[16]) -#define ROM_IOCPinTypeSsiMaster \ +#define ROM_IOCPinTypeSsiMaster \ ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ - ROM_API_IOC_TABLE[17]) + ROM_API_IOC_TABLE[17]) -#define ROM_IOCPinTypeSsiSlave \ +#define ROM_IOCPinTypeSsiSlave \ ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ - ROM_API_IOC_TABLE[18]) + ROM_API_IOC_TABLE[18]) -#define ROM_IOCPinTypeI2c \ +#define ROM_IOCPinTypeI2c \ ((void (*)(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk)) \ - ROM_API_IOC_TABLE[19]) + ROM_API_IOC_TABLE[19]) -#define ROM_IOCPinTypeAux \ +#define ROM_IOCPinTypeAux \ ((void (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[21]) - + ROM_API_IOC_TABLE[21]) // PRCM FUNCTIONS -#define ROM_PRCMInfClockConfigureSet \ +#define ROM_PRCMInfClockConfigureSet \ ((void (*)(uint32_t ui32ClkDiv, uint32_t ui32PowerMode)) \ - ROM_API_PRCM_TABLE[0]) + ROM_API_PRCM_TABLE[0]) -#define ROM_PRCMInfClockConfigureGet \ - ((uint32_t (*)(uint32_t ui32PowerMode)) \ - ROM_API_PRCM_TABLE[1]) +#define ROM_PRCMInfClockConfigureGet \ + ((uint32_t(*)(uint32_t ui32PowerMode)) \ + ROM_API_PRCM_TABLE[1]) -#define ROM_PRCMAudioClockConfigSet \ +#define ROM_PRCMAudioClockConfigSet \ ((void (*)(uint32_t ui32ClkConfig, uint32_t ui32SampleRate)) \ - ROM_API_PRCM_TABLE[4]) + ROM_API_PRCM_TABLE[4]) -#define ROM_PRCMPowerDomainOn \ +#define ROM_PRCMPowerDomainOn \ ((void (*)(uint32_t ui32Domains)) \ - ROM_API_PRCM_TABLE[5]) + ROM_API_PRCM_TABLE[5]) -#define ROM_PRCMPowerDomainOff \ +#define ROM_PRCMPowerDomainOff \ ((void (*)(uint32_t ui32Domains)) \ - ROM_API_PRCM_TABLE[6]) + ROM_API_PRCM_TABLE[6]) -#define ROM_PRCMPeripheralRunEnable \ +#define ROM_PRCMPeripheralRunEnable \ ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[7]) + ROM_API_PRCM_TABLE[7]) -#define ROM_PRCMPeripheralRunDisable \ +#define ROM_PRCMPeripheralRunDisable \ ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[8]) + ROM_API_PRCM_TABLE[8]) -#define ROM_PRCMPeripheralSleepEnable \ +#define ROM_PRCMPeripheralSleepEnable \ ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[9]) + ROM_API_PRCM_TABLE[9]) -#define ROM_PRCMPeripheralSleepDisable \ +#define ROM_PRCMPeripheralSleepDisable \ ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[10]) + ROM_API_PRCM_TABLE[10]) #define ROM_PRCMPeripheralDeepSleepEnable \ - ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[11]) + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[11]) #define ROM_PRCMPeripheralDeepSleepDisable \ - ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[12]) + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[12]) -#define ROM_PRCMPowerDomainStatus \ - ((uint32_t (*)(uint32_t ui32Domains)) \ - ROM_API_PRCM_TABLE[13]) +#define ROM_PRCMPowerDomainStatus \ + ((uint32_t(*)(uint32_t ui32Domains)) \ + ROM_API_PRCM_TABLE[13]) #define ROM_PRCMDeepSleep \ - ((void (*)(void)) \ - ROM_API_PRCM_TABLE[14]) - + ((void (*)(void)) \ + ROM_API_PRCM_TABLE[14]) // SMPH FUNCTIONS -#define ROM_SMPHAcquire \ +#define ROM_SMPHAcquire \ ((void (*)(uint32_t ui32Semaphore)) \ - ROM_API_SMPH_TABLE[0]) - + ROM_API_SMPH_TABLE[0]) // SSI FUNCTIONS -#define ROM_SSIConfigSetExpClk \ +#define ROM_SSIConfigSetExpClk \ ((void (*)(uint32_t ui32Base, uint32_t ui32SSIClk, uint32_t ui32Protocol, uint32_t ui32Mode, uint32_t ui32BitRate, uint32_t ui32DataWidth)) \ - ROM_API_SSI_TABLE[0]) + ROM_API_SSI_TABLE[0]) -#define ROM_SSIDataPut \ +#define ROM_SSIDataPut \ ((void (*)(uint32_t ui32Base, uint32_t ui32Data)) \ - ROM_API_SSI_TABLE[1]) + ROM_API_SSI_TABLE[1]) -#define ROM_SSIDataPutNonBlocking \ - ((int32_t (*)(uint32_t ui32Base, uint32_t ui32Data)) \ - ROM_API_SSI_TABLE[2]) +#define ROM_SSIDataPutNonBlocking \ + ((int32_t(*)(uint32_t ui32Base, uint32_t ui32Data)) \ + ROM_API_SSI_TABLE[2]) -#define ROM_SSIDataGet \ - ((void (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ - ROM_API_SSI_TABLE[3]) - -#define ROM_SSIDataGetNonBlocking \ - ((int32_t (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ - ROM_API_SSI_TABLE[4]) +#define ROM_SSIDataGet \ + ((void (*)(uint32_t ui32Base, uint32_t * pui32Data)) \ + ROM_API_SSI_TABLE[3]) +#define ROM_SSIDataGetNonBlocking \ + ((int32_t(*)(uint32_t ui32Base, uint32_t * pui32Data)) \ + ROM_API_SSI_TABLE[4]) // TIMER FUNCTIONS -#define ROM_TimerConfigure \ +#define ROM_TimerConfigure \ ((void (*)(uint32_t ui32Base, uint32_t ui32Config)) \ - ROM_API_TIMER_TABLE[0]) + ROM_API_TIMER_TABLE[0]) -#define ROM_TimerLevelControl \ +#define ROM_TimerLevelControl \ ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert)) \ - ROM_API_TIMER_TABLE[1]) + ROM_API_TIMER_TABLE[1]) -#define ROM_TimerStallControl \ +#define ROM_TimerStallControl \ ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bStall)) \ - ROM_API_TIMER_TABLE[3]) + ROM_API_TIMER_TABLE[3]) -#define ROM_TimerWaitOnTriggerControl \ +#define ROM_TimerWaitOnTriggerControl \ ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bWait)) \ - ROM_API_TIMER_TABLE[4]) - + ROM_API_TIMER_TABLE[4]) // TRNG FUNCTIONS -#define ROM_TRNGNumberGet \ - ((uint32_t (*)(uint32_t ui32Word)) \ - ROM_API_TRNG_TABLE[1]) - +#define ROM_TRNGNumberGet \ + ((uint32_t(*)(uint32_t ui32Word)) \ + ROM_API_TRNG_TABLE[1]) // UART FUNCTIONS -#define ROM_UARTFIFOLevelGet \ - ((void (*)(uint32_t ui32Base, uint32_t *pui32TxLevel, uint32_t *pui32RxLevel)) \ - ROM_API_UART_TABLE[0]) +#define ROM_UARTFIFOLevelGet \ + ((void (*)(uint32_t ui32Base, uint32_t * pui32TxLevel, uint32_t * pui32RxLevel)) \ + ROM_API_UART_TABLE[0]) -#define ROM_UARTConfigSetExpClk \ +#define ROM_UARTConfigSetExpClk \ ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t ui32Baud, uint32_t ui32Config)) \ - ROM_API_UART_TABLE[1]) + ROM_API_UART_TABLE[1]) -#define ROM_UARTConfigGetExpClk \ - ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t *pui32Baud, uint32_t *pui32Config)) \ - ROM_API_UART_TABLE[2]) +#define ROM_UARTConfigGetExpClk \ + ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t * pui32Baud, uint32_t * pui32Config)) \ + ROM_API_UART_TABLE[2]) -#define ROM_UARTDisable \ +#define ROM_UARTDisable \ ((void (*)(uint32_t ui32Base)) \ - ROM_API_UART_TABLE[3]) + ROM_API_UART_TABLE[3]) -#define ROM_UARTCharGetNonBlocking \ - ((int32_t (*)(uint32_t ui32Base)) \ - ROM_API_UART_TABLE[4]) +#define ROM_UARTCharGetNonBlocking \ + ((int32_t(*)(uint32_t ui32Base)) \ + ROM_API_UART_TABLE[4]) -#define ROM_UARTCharGet \ - ((int32_t (*)(uint32_t ui32Base)) \ - ROM_API_UART_TABLE[5]) +#define ROM_UARTCharGet \ + ((int32_t(*)(uint32_t ui32Base)) \ + ROM_API_UART_TABLE[5]) -#define ROM_UARTCharPutNonBlocking \ +#define ROM_UARTCharPutNonBlocking \ ((bool (*)(uint32_t ui32Base, uint8_t ui8Data)) \ - ROM_API_UART_TABLE[6]) + ROM_API_UART_TABLE[6]) -#define ROM_UARTCharPut \ +#define ROM_UARTCharPut \ ((void (*)(uint32_t ui32Base, uint8_t ui8Data)) \ - ROM_API_UART_TABLE[7]) - + ROM_API_UART_TABLE[7]) // UDMA FUNCTIONS -#define ROM_uDMAChannelAttributeEnable \ +#define ROM_uDMAChannelAttributeEnable \ ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ - ROM_API_UDMA_TABLE[0]) + ROM_API_UDMA_TABLE[0]) -#define ROM_uDMAChannelAttributeDisable \ +#define ROM_uDMAChannelAttributeDisable \ ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ - ROM_API_UDMA_TABLE[1]) + ROM_API_UDMA_TABLE[1]) -#define ROM_uDMAChannelAttributeGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelNum)) \ - ROM_API_UDMA_TABLE[2]) +#define ROM_uDMAChannelAttributeGet \ + ((uint32_t(*)(uint32_t ui32Base, uint32_t ui32ChannelNum)) \ + ROM_API_UDMA_TABLE[2]) -#define ROM_uDMAChannelControlSet \ +#define ROM_uDMAChannelControlSet \ ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Control)) \ - ROM_API_UDMA_TABLE[3]) + ROM_API_UDMA_TABLE[3]) -#define ROM_uDMAChannelScatterGatherSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void *pvTaskList, uint32_t ui32IsPeriphSG)) \ - ROM_API_UDMA_TABLE[5]) +#define ROM_uDMAChannelScatterGatherSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void* pvTaskList, uint32_t ui32IsPeriphSG)) \ + ROM_API_UDMA_TABLE[5]) -#define ROM_uDMAChannelSizeGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ - ROM_API_UDMA_TABLE[6]) - -#define ROM_uDMAChannelModeGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ - ROM_API_UDMA_TABLE[7]) +#define ROM_uDMAChannelSizeGet \ + ((uint32_t(*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ + ROM_API_UDMA_TABLE[6]) +#define ROM_uDMAChannelModeGet \ + ((uint32_t(*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ + ROM_API_UDMA_TABLE[7]) // VIMS FUNCTIONS -#define ROM_VIMSConfigure \ +#define ROM_VIMSConfigure \ ((void (*)(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch)) \ - ROM_API_VIMS_TABLE[0]) + ROM_API_VIMS_TABLE[0]) -#define ROM_VIMSModeSet \ +#define ROM_VIMSModeSet \ ((void (*)(uint32_t ui32Base, uint32_t ui32Mode)) \ - ROM_API_VIMS_TABLE[1]) - - + ROM_API_VIMS_TABLE[1]) //***************************************************************************** // diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rom_crypto.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rom_crypto.h index 8974406..ee76fc8 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rom_crypto.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/rom_crypto.h @@ -1,41 +1,41 @@ /****************************************************************************** -* Filename: rom_crypto.h -* Revised: 2018-09-17 09:24:56 +0200 (Mon, 17 Sep 2018) -* Revision: 52624 -* -* Description: This header file is the API to the crypto functions -* built into ROM on the CC13xx/CC26xx. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -*******************************************************************************/ + * Filename: rom_crypto.h + * Revised: 2018-09-17 09:24:56 +0200 (Mon, 17 Sep 2018) + * Revision: 52624 + * + * Description: This header file is the API to the crypto functions + * built into ROM on the CC13xx/CC26xx. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ //***************************************************************************** // @@ -50,8 +50,7 @@ #define ROM_CRYPTO_H #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif ///////////////////////////////////* AES-128 *////////////////////////////////// @@ -188,42 +187,42 @@ extern uint8_t AES_CTR_DecryptData(uint8_t* cipherText, uint16_t textLen, * ECC Return Status Flags. */ // Scalar multiplication status -#define ECC_MODULUS_EVEN 0xDC -#define ECC_MODULUS_LARGER_THAN_255_WORDS 0xD2 -#define ECC_MODULUS_LENGTH_ZERO 0x08 -#define ECC_MODULUS_MSW_IS_ZERO 0x30 -#define ECC_SCALAR_TOO_LONG 0x35 -#define ECC_SCALAR_LENGTH_ZERO 0x53 -#define ECC_ORDER_TOO_LONG 0xC6 -#define ECC_ORDER_LENGTH_ZERO 0x6C -#define ECC_X_COORD_TOO_LONG 0x3C -#define ECC_X_COORD_LENGTH_ZERO 0xC3 -#define ECC_Y_COORD_TOO_LONG 0x65 -#define ECC_Y_COORD_LENGTH_ZERO 0x56 -#define ECC_A_COEF_TOO_LONG 0x5C -#define ECC_A_COEF_LENGTH_ZERO 0xC5 -#define ECC_BAD_WINDOW_SIZE 0x66 -#define ECC_SCALAR_MUL_OK 0x99 +#define ECC_MODULUS_EVEN 0xDC +#define ECC_MODULUS_LARGER_THAN_255_WORDS 0xD2 +#define ECC_MODULUS_LENGTH_ZERO 0x08 +#define ECC_MODULUS_MSW_IS_ZERO 0x30 +#define ECC_SCALAR_TOO_LONG 0x35 +#define ECC_SCALAR_LENGTH_ZERO 0x53 +#define ECC_ORDER_TOO_LONG 0xC6 +#define ECC_ORDER_LENGTH_ZERO 0x6C +#define ECC_X_COORD_TOO_LONG 0x3C +#define ECC_X_COORD_LENGTH_ZERO 0xC3 +#define ECC_Y_COORD_TOO_LONG 0x65 +#define ECC_Y_COORD_LENGTH_ZERO 0x56 +#define ECC_A_COEF_TOO_LONG 0x5C +#define ECC_A_COEF_LENGTH_ZERO 0xC5 +#define ECC_BAD_WINDOW_SIZE 0x66 +#define ECC_SCALAR_MUL_OK 0x99 // ECDSA and ECDH status -#define ECC_ORDER_LARGER_THAN_255_WORDS 0x28 -#define ECC_ORDER_EVEN 0x82 -#define ECC_ORDER_MSW_IS_ZERO 0x23 -#define ECC_ECC_KEY_TOO_LONG 0x25 -#define ECC_ECC_KEY_LENGTH_ZERO 0x52 -#define ECC_DIGEST_TOO_LONG 0x27 -#define ECC_DIGEST_LENGTH_ZERO 0x72 -#define ECC_ECDSA_SIGN_OK 0x32 -#define ECC_ECDSA_INVALID_SIGNATURE 0x5A -#define ECC_ECDSA_VALID_SIGNATURE 0xA5 -#define ECC_SIG_P1_TOO_LONG 0x11 -#define ECC_SIG_P1_LENGTH_ZERO 0x12 -#define ECC_SIG_P2_TOO_LONG 0x22 -#define ECC_SIG_P2_LENGTH_ZERO 0x21 +#define ECC_ORDER_LARGER_THAN_255_WORDS 0x28 +#define ECC_ORDER_EVEN 0x82 +#define ECC_ORDER_MSW_IS_ZERO 0x23 +#define ECC_ECC_KEY_TOO_LONG 0x25 +#define ECC_ECC_KEY_LENGTH_ZERO 0x52 +#define ECC_DIGEST_TOO_LONG 0x27 +#define ECC_DIGEST_LENGTH_ZERO 0x72 +#define ECC_ECDSA_SIGN_OK 0x32 +#define ECC_ECDSA_INVALID_SIGNATURE 0x5A +#define ECC_ECDSA_VALID_SIGNATURE 0xA5 +#define ECC_SIG_P1_TOO_LONG 0x11 +#define ECC_SIG_P1_LENGTH_ZERO 0x12 +#define ECC_SIG_P2_TOO_LONG 0x22 +#define ECC_SIG_P2_LENGTH_ZERO 0x21 -#define ECC_ECDSA_KEYGEN_OK ECC_SCALAR_MUL_OK -#define ECC_ECDH_KEYGEN_OK ECC_SCALAR_MUL_OK -#define ECC_ECDH_COMMON_KEY_OK ECC_SCALAR_MUL_OK +#define ECC_ECDSA_KEYGEN_OK ECC_SCALAR_MUL_OK +#define ECC_ECDH_KEYGEN_OK ECC_SCALAR_MUL_OK +#define ECC_ECDH_COMMON_KEY_OK ECC_SCALAR_MUL_OK //***************************************************************************** /*! @@ -243,17 +242,17 @@ extern void ECC_initialize(uint32_t* pWorkzone); //***************************************************************************** /*! -* \brief Generate a key. -* -* This is used for both ECDH and ECDSA. -* -* \param randString Pointer to random string, input. -* \param privateKey Pointer to the private key, output. -* \param publicKey_x Pointer to public key X-coordinate, output. -* \param publicKey_y Pointer to public key Y-coordinate, output. -* -* \return Status -*/ + * \brief Generate a key. + * + * This is used for both ECDH and ECDSA. + * + * \param randString Pointer to random string, input. + * \param privateKey Pointer to the private key, output. + * \param publicKey_x Pointer to public key X-coordinate, output. + * \param publicKey_y Pointer to public key Y-coordinate, output. + * + * \return Status + */ //***************************************************************************** extern uint8_t ECC_generateKey(uint32_t* randString, uint32_t* privateKey, uint32_t* publicKey_x, uint32_t* publicKey_y); @@ -304,11 +303,10 @@ extern uint8_t ECC_ECDSA_verify(uint32_t* publicKey_x, uint32_t* publicKey_y, */ //***************************************************************************** extern uint8_t ECC_ECDH_computeSharedSecret(uint32_t* privateKey, - uint32_t* publicKey_x, - uint32_t* publicKey_y, - uint32_t* sharedSecret_x, - uint32_t* sharedSecret_y); - + uint32_t* publicKey_x, + uint32_t* publicKey_y, + uint32_t* sharedSecret_x, + uint32_t* sharedSecret_y); ///////////////////////////////////* SHA-256 *////////////////////////////////// @@ -316,9 +314,9 @@ extern uint8_t ECC_ECDH_computeSharedSecret(uint32_t* privateKey, //! SHA256 functions. typedef struct { - uint32_t state[8]; - uint32_t textLen[2]; - uint32_t W[16]; + uint32_t state[8]; + uint32_t textLen[2]; + uint32_t W[16]; } SHA256_memory_t; //***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup.h index 923bc71..db72a66 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: setup.h -* Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) -* Revision: 52993 -* -* Description: Prototypes and defines for the setup API. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: setup.h + * Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) + * Revision: 52993 + * + * Description: Prototypes and defines for the setup API. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,8 +55,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif // Hardware headers @@ -78,7 +77,7 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define SetupTrimDevice NOROM_SetupTrimDevice +#define SetupTrimDevice NOROM_SetupTrimDevice #endif //***************************************************************************** @@ -105,7 +104,7 @@ extern "C" //! \return None // //***************************************************************************** -extern void SetupTrimDevice( void ); +extern void SetupTrimDevice(void); //***************************************************************************** // @@ -116,8 +115,8 @@ extern void SetupTrimDevice( void ); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_SetupTrimDevice -#undef SetupTrimDevice -#define SetupTrimDevice ROM_SetupTrimDevice +#undef SetupTrimDevice +#define SetupTrimDevice ROM_SetupTrimDevice #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_doc.h index 07ab97e..1b46e56 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: setup_doc.h -* Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017) -* Revision: 49096 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: setup_doc.h + * Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017) + * Revision: 49096 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup setup_api //! @{ //! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_rom.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_rom.h index 74c75da..7309515 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_rom.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_rom.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: setup_rom.h -* Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) -* Revision: 52993 -* -* Description: Prototypes and defines for the setup API. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: setup_rom.h + * Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) + * Revision: 52993 + * + * Description: Prototypes and defines for the setup API. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,8 +55,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif // Hardware headers @@ -81,23 +80,23 @@ extern "C" #define SetupAfterColdResetWakeupFromShutDownCfg1 NOROM_SetupAfterColdResetWakeupFromShutDownCfg1 #define SetupAfterColdResetWakeupFromShutDownCfg2 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2 #define SetupAfterColdResetWakeupFromShutDownCfg3 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3 -#define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn -#define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn -#define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl -#define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1 -#define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2 -#define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1 +#define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn +#define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn +#define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl +#define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1 +#define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2 +#define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1 #define SetupGetTrimForDblrLoopFilterResetVoltage NOROM_SetupGetTrimForDblrLoopFilterResetVoltage -#define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg +#define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg #define SetupGetTrimForRcOscLfIBiasTrim NOROM_SetupGetTrimForRcOscLfIBiasTrim #define SetupGetTrimForRcOscLfRtuneCtuneTrim NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim -#define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl -#define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart +#define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl +#define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart #define SetupGetTrimForXoscHfIbiastherm NOROM_SetupGetTrimForXoscHfIbiastherm #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio #define SetupSetCacheModeAccordingToCcfgSetting NOROM_SetupSetCacheModeAccordingToCcfgSetting -#define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc -#define SetupSetVddrLevel NOROM_SetupSetVddrLevel +#define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc +#define SetupSetVddrLevel NOROM_SetupSetVddrLevel #endif //***************************************************************************** @@ -119,7 +118,7 @@ extern "C" //! \return None // //***************************************************************************** -extern void SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg ); +extern void SetupAfterColdResetWakeupFromShutDownCfg1(uint32_t ccfg_ModeConfReg); //***************************************************************************** // @@ -135,7 +134,7 @@ extern void SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg //! \return None // //***************************************************************************** -extern void SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg ); +extern void SetupAfterColdResetWakeupFromShutDownCfg2(uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg); //***************************************************************************** // @@ -155,7 +154,7 @@ extern void SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revisio //! \return None // //***************************************************************************** -extern void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ); +extern void SetupAfterColdResetWakeupFromShutDownCfg3(uint32_t ccfg_ModeConfReg); //***************************************************************************** // @@ -166,7 +165,7 @@ extern void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg //! \return Returns the trim value from FCFG1. // //***************************************************************************** -extern uint32_t SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForAdcShModeEn(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -177,7 +176,7 @@ extern uint32_t SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision ); //! \return Returns the trim value from FCFG1. // //***************************************************************************** -extern uint32_t SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForAdcShVbufEn(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -188,7 +187,7 @@ extern uint32_t SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForAmpcompCtrl(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -197,7 +196,7 @@ extern uint32_t SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForAmpcompTh1( void ); +extern uint32_t SetupGetTrimForAmpcompTh1(void); //***************************************************************************** // @@ -206,7 +205,7 @@ extern uint32_t SetupGetTrimForAmpcompTh1( void ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForAmpcompTh2( void ); +extern uint32_t SetupGetTrimForAmpcompTh2(void); //***************************************************************************** // @@ -217,7 +216,7 @@ extern uint32_t SetupGetTrimForAmpcompTh2( void ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ); +extern uint32_t SetupGetTrimForAnabypassValue1(uint32_t ccfg_ModeConfReg); //***************************************************************************** // @@ -228,7 +227,7 @@ extern uint32_t SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ); //! \return Returns the trim value from FCFG1. // //***************************************************************************** -extern uint32_t SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForDblrLoopFilterResetVoltage(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -239,7 +238,7 @@ extern uint32_t SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Rev //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForRadcExtCfg(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -250,7 +249,7 @@ extern uint32_t SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision ); //! \return Returns the trim value from FCFG1. // //***************************************************************************** -extern uint32_t SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForRcOscLfIBiasTrim(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -260,7 +259,7 @@ extern uint32_t SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim( void ); +extern uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim(void); //***************************************************************************** // @@ -271,7 +270,7 @@ extern uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim( void ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForXoscHfCtl(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -280,7 +279,7 @@ extern uint32_t SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForXoscHfFastStart( void ); +extern uint32_t SetupGetTrimForXoscHfFastStart(void); //***************************************************************************** // @@ -290,7 +289,7 @@ extern uint32_t SetupGetTrimForXoscHfFastStart( void ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForXoscHfIbiastherm( void ); +extern uint32_t SetupGetTrimForXoscHfIbiastherm(void); //***************************************************************************** // @@ -302,7 +301,7 @@ extern uint32_t SetupGetTrimForXoscHfIbiastherm( void ); //! \return Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet. // //***************************************************************************** -extern uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -314,18 +313,18 @@ extern uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg // //***************************************************************************** __STATIC_INLINE int32_t -SetupSignExtendVddrTrimValue( uint32_t ui32VddrTrimVal ) +SetupSignExtendVddrTrimValue(uint32_t ui32VddrTrimVal) { // The VDDR trim value is 5 bits representing the range from -10 to +21 // (where -10=0x16, -1=0x1F, 0=0x00, 1=0x01 and +21=0x15) int32_t i32SignedVddrVal = ui32VddrTrimVal; - if ( i32SignedVddrVal > 0x15 ) + if (i32SignedVddrVal > 0x15) { i32SignedVddrVal -= 0x20; } - return ( i32SignedVddrVal ); + return (i32SignedVddrVal); } //***************************************************************************** @@ -335,7 +334,7 @@ SetupSignExtendVddrTrimValue( uint32_t ui32VddrTrimVal ) //! \return None // //***************************************************************************** -extern void SetupSetCacheModeAccordingToCcfgSetting( void ); +extern void SetupSetCacheModeAccordingToCcfgSetting(void); //***************************************************************************** // @@ -346,7 +345,7 @@ extern void SetupSetCacheModeAccordingToCcfgSetting( void ); //! \return None // //***************************************************************************** -extern void SetupSetAonRtcSubSecInc( uint32_t subSecInc ); +extern void SetupSetAonRtcSubSecInc(uint32_t subSecInc); //***************************************************************************** // @@ -358,7 +357,7 @@ extern void SetupSetAonRtcSubSecInc( uint32_t subSecInc ); //! \return None // //***************************************************************************** -extern void SetupSetVddrLevel( uint32_t ccfg_ModeConfReg ); +extern void SetupSetVddrLevel(uint32_t ccfg_ModeConfReg); //***************************************************************************** // @@ -369,84 +368,84 @@ extern void SetupSetVddrLevel( uint32_t ccfg_ModeConfReg ); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg1 -#undef SetupAfterColdResetWakeupFromShutDownCfg1 +#undef SetupAfterColdResetWakeupFromShutDownCfg1 #define SetupAfterColdResetWakeupFromShutDownCfg1 ROM_SetupAfterColdResetWakeupFromShutDownCfg1 #endif #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg2 -#undef SetupAfterColdResetWakeupFromShutDownCfg2 +#undef SetupAfterColdResetWakeupFromShutDownCfg2 #define SetupAfterColdResetWakeupFromShutDownCfg2 ROM_SetupAfterColdResetWakeupFromShutDownCfg2 #endif #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg3 -#undef SetupAfterColdResetWakeupFromShutDownCfg3 +#undef SetupAfterColdResetWakeupFromShutDownCfg3 #define SetupAfterColdResetWakeupFromShutDownCfg3 ROM_SetupAfterColdResetWakeupFromShutDownCfg3 #endif #ifdef ROM_SetupGetTrimForAdcShModeEn -#undef SetupGetTrimForAdcShModeEn -#define SetupGetTrimForAdcShModeEn ROM_SetupGetTrimForAdcShModeEn +#undef SetupGetTrimForAdcShModeEn +#define SetupGetTrimForAdcShModeEn ROM_SetupGetTrimForAdcShModeEn #endif #ifdef ROM_SetupGetTrimForAdcShVbufEn -#undef SetupGetTrimForAdcShVbufEn -#define SetupGetTrimForAdcShVbufEn ROM_SetupGetTrimForAdcShVbufEn +#undef SetupGetTrimForAdcShVbufEn +#define SetupGetTrimForAdcShVbufEn ROM_SetupGetTrimForAdcShVbufEn #endif #ifdef ROM_SetupGetTrimForAmpcompCtrl -#undef SetupGetTrimForAmpcompCtrl -#define SetupGetTrimForAmpcompCtrl ROM_SetupGetTrimForAmpcompCtrl +#undef SetupGetTrimForAmpcompCtrl +#define SetupGetTrimForAmpcompCtrl ROM_SetupGetTrimForAmpcompCtrl #endif #ifdef ROM_SetupGetTrimForAmpcompTh1 -#undef SetupGetTrimForAmpcompTh1 -#define SetupGetTrimForAmpcompTh1 ROM_SetupGetTrimForAmpcompTh1 +#undef SetupGetTrimForAmpcompTh1 +#define SetupGetTrimForAmpcompTh1 ROM_SetupGetTrimForAmpcompTh1 #endif #ifdef ROM_SetupGetTrimForAmpcompTh2 -#undef SetupGetTrimForAmpcompTh2 -#define SetupGetTrimForAmpcompTh2 ROM_SetupGetTrimForAmpcompTh2 +#undef SetupGetTrimForAmpcompTh2 +#define SetupGetTrimForAmpcompTh2 ROM_SetupGetTrimForAmpcompTh2 #endif #ifdef ROM_SetupGetTrimForAnabypassValue1 -#undef SetupGetTrimForAnabypassValue1 -#define SetupGetTrimForAnabypassValue1 ROM_SetupGetTrimForAnabypassValue1 +#undef SetupGetTrimForAnabypassValue1 +#define SetupGetTrimForAnabypassValue1 ROM_SetupGetTrimForAnabypassValue1 #endif #ifdef ROM_SetupGetTrimForDblrLoopFilterResetVoltage -#undef SetupGetTrimForDblrLoopFilterResetVoltage +#undef SetupGetTrimForDblrLoopFilterResetVoltage #define SetupGetTrimForDblrLoopFilterResetVoltage ROM_SetupGetTrimForDblrLoopFilterResetVoltage #endif #ifdef ROM_SetupGetTrimForRadcExtCfg -#undef SetupGetTrimForRadcExtCfg -#define SetupGetTrimForRadcExtCfg ROM_SetupGetTrimForRadcExtCfg +#undef SetupGetTrimForRadcExtCfg +#define SetupGetTrimForRadcExtCfg ROM_SetupGetTrimForRadcExtCfg #endif #ifdef ROM_SetupGetTrimForRcOscLfIBiasTrim -#undef SetupGetTrimForRcOscLfIBiasTrim +#undef SetupGetTrimForRcOscLfIBiasTrim #define SetupGetTrimForRcOscLfIBiasTrim ROM_SetupGetTrimForRcOscLfIBiasTrim #endif #ifdef ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim -#undef SetupGetTrimForRcOscLfRtuneCtuneTrim +#undef SetupGetTrimForRcOscLfRtuneCtuneTrim #define SetupGetTrimForRcOscLfRtuneCtuneTrim ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim #endif #ifdef ROM_SetupGetTrimForXoscHfCtl -#undef SetupGetTrimForXoscHfCtl -#define SetupGetTrimForXoscHfCtl ROM_SetupGetTrimForXoscHfCtl +#undef SetupGetTrimForXoscHfCtl +#define SetupGetTrimForXoscHfCtl ROM_SetupGetTrimForXoscHfCtl #endif #ifdef ROM_SetupGetTrimForXoscHfFastStart -#undef SetupGetTrimForXoscHfFastStart -#define SetupGetTrimForXoscHfFastStart ROM_SetupGetTrimForXoscHfFastStart +#undef SetupGetTrimForXoscHfFastStart +#define SetupGetTrimForXoscHfFastStart ROM_SetupGetTrimForXoscHfFastStart #endif #ifdef ROM_SetupGetTrimForXoscHfIbiastherm -#undef SetupGetTrimForXoscHfIbiastherm +#undef SetupGetTrimForXoscHfIbiastherm #define SetupGetTrimForXoscHfIbiastherm ROM_SetupGetTrimForXoscHfIbiastherm #endif #ifdef ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio -#undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio +#undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio #endif #ifdef ROM_SetupSetCacheModeAccordingToCcfgSetting -#undef SetupSetCacheModeAccordingToCcfgSetting +#undef SetupSetCacheModeAccordingToCcfgSetting #define SetupSetCacheModeAccordingToCcfgSetting ROM_SetupSetCacheModeAccordingToCcfgSetting #endif #ifdef ROM_SetupSetAonRtcSubSecInc -#undef SetupSetAonRtcSubSecInc -#define SetupSetAonRtcSubSecInc ROM_SetupSetAonRtcSubSecInc +#undef SetupSetAonRtcSubSecInc +#define SetupSetAonRtcSubSecInc ROM_SetupSetAonRtcSubSecInc #endif #ifdef ROM_SetupSetVddrLevel -#undef SetupSetVddrLevel -#define SetupSetVddrLevel ROM_SetupSetVddrLevel +#undef SetupSetVddrLevel +#define SetupSetVddrLevel ROM_SetupSetVddrLevel #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_rom_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_rom_doc.h index bafcf07..c8df48a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_rom_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/setup_rom_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: setup_rom_doc.h -* Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017) -* Revision: 49096 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: setup_rom_doc.h + * Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017) + * Revision: 49096 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup setup_rom_api //! @{ //! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/smph.h index e1bfc44..5e8ebb1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/smph.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/smph.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: smph.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the MCU Semaphore. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: smph.h + * Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) + * Revision: 47343 + * + * Description: Defines and prototypes for the MCU Semaphore. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,16 +55,15 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_memmap.h" +#include "../inc/hw_smph.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_smph.h" -#include "../inc/hw_memmap.h" -#include "debug.h" //***************************************************************************** // @@ -80,7 +79,7 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define SMPHAcquire NOROM_SMPHAcquire +#define SMPHAcquire NOROM_SMPHAcquire #endif //***************************************************************************** @@ -88,8 +87,8 @@ extern "C" // General constants and defines // //***************************************************************************** -#define SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed -#define SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed +#define SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed +#define SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed //***************************************************************************** // @@ -97,38 +96,38 @@ extern "C" // as the ui32Semaphore parameter. // //***************************************************************************** -#define SMPH_0 0 // MCU Semaphore 0 -#define SMPH_1 1 // MCU Semaphore 1 -#define SMPH_2 2 // MCU Semaphore 2 -#define SMPH_3 3 // MCU Semaphore 3 -#define SMPH_4 4 // MCU Semaphore 4 -#define SMPH_5 5 // MCU Semaphore 5 -#define SMPH_6 6 // MCU Semaphore 6 -#define SMPH_7 7 // MCU Semaphore 7 -#define SMPH_8 8 // MCU Semaphore 8 -#define SMPH_9 9 // MCU Semaphore 9 -#define SMPH_10 10 // MCU Semaphore 10 -#define SMPH_11 11 // MCU Semaphore 11 -#define SMPH_12 12 // MCU Semaphore 12 -#define SMPH_13 13 // MCU Semaphore 13 -#define SMPH_14 14 // MCU Semaphore 14 -#define SMPH_15 15 // MCU Semaphore 15 -#define SMPH_16 16 // MCU Semaphore 16 -#define SMPH_17 17 // MCU Semaphore 17 -#define SMPH_18 18 // MCU Semaphore 18 -#define SMPH_19 19 // MCU Semaphore 19 -#define SMPH_20 20 // MCU Semaphore 20 -#define SMPH_21 21 // MCU Semaphore 21 -#define SMPH_22 22 // MCU Semaphore 22 -#define SMPH_23 23 // MCU Semaphore 23 -#define SMPH_24 24 // MCU Semaphore 24 -#define SMPH_25 25 // MCU Semaphore 25 -#define SMPH_26 26 // MCU Semaphore 26 -#define SMPH_27 27 // MCU Semaphore 27 -#define SMPH_28 28 // MCU Semaphore 28 -#define SMPH_29 29 // MCU Semaphore 29 -#define SMPH_30 30 // MCU Semaphore 30 -#define SMPH_31 31 // MCU Semaphore 31 +#define SMPH_0 0 // MCU Semaphore 0 +#define SMPH_1 1 // MCU Semaphore 1 +#define SMPH_2 2 // MCU Semaphore 2 +#define SMPH_3 3 // MCU Semaphore 3 +#define SMPH_4 4 // MCU Semaphore 4 +#define SMPH_5 5 // MCU Semaphore 5 +#define SMPH_6 6 // MCU Semaphore 6 +#define SMPH_7 7 // MCU Semaphore 7 +#define SMPH_8 8 // MCU Semaphore 8 +#define SMPH_9 9 // MCU Semaphore 9 +#define SMPH_10 10 // MCU Semaphore 10 +#define SMPH_11 11 // MCU Semaphore 11 +#define SMPH_12 12 // MCU Semaphore 12 +#define SMPH_13 13 // MCU Semaphore 13 +#define SMPH_14 14 // MCU Semaphore 14 +#define SMPH_15 15 // MCU Semaphore 15 +#define SMPH_16 16 // MCU Semaphore 16 +#define SMPH_17 17 // MCU Semaphore 17 +#define SMPH_18 18 // MCU Semaphore 18 +#define SMPH_19 19 // MCU Semaphore 19 +#define SMPH_20 20 // MCU Semaphore 20 +#define SMPH_21 21 // MCU Semaphore 21 +#define SMPH_22 22 // MCU Semaphore 22 +#define SMPH_23 23 // MCU Semaphore 23 +#define SMPH_24 24 // MCU Semaphore 24 +#define SMPH_25 25 // MCU Semaphore 25 +#define SMPH_26 26 // MCU Semaphore 26 +#define SMPH_27 27 // MCU Semaphore 27 +#define SMPH_28 28 // MCU Semaphore 28 +#define SMPH_29 29 // MCU Semaphore 29 +#define SMPH_30 30 // MCU Semaphore 30 +#define SMPH_31 31 // MCU Semaphore 31 //***************************************************************************** // @@ -287,8 +286,8 @@ SMPHRelease(uint32_t ui32Semaphore) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_SMPHAcquire -#undef SMPHAcquire -#define SMPHAcquire ROM_SMPHAcquire +#undef SMPHAcquire +#define SMPHAcquire ROM_SMPHAcquire #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/smph_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/smph_doc.h index c66ef84..086359e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/smph_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/smph_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: smph_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: smph_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup mcusemaphore_api //! @{ //! \section sec_mcusemaphore Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ssi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ssi.h index 74eaa08..c09fc82 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ssi.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/ssi.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: ssi.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and macros for the SSI. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: ssi.h + * Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) + * Revision: 49048 + * + * Description: Defines and macros for the SSI. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,18 +55,17 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include #include "../inc/hw_ints.h" #include "../inc/hw_memmap.h" -#include "../inc/hw_types.h" #include "../inc/hw_ssi.h" +#include "../inc/hw_types.h" #include "debug.h" #include "interrupt.h" +#include +#include //***************************************************************************** // @@ -82,13 +81,13 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define SSIConfigSetExpClk NOROM_SSIConfigSetExpClk -#define SSIDataPut NOROM_SSIDataPut -#define SSIDataPutNonBlocking NOROM_SSIDataPutNonBlocking -#define SSIDataGet NOROM_SSIDataGet -#define SSIDataGetNonBlocking NOROM_SSIDataGetNonBlocking -#define SSIIntRegister NOROM_SSIIntRegister -#define SSIIntUnregister NOROM_SSIIntUnregister +#define SSIConfigSetExpClk NOROM_SSIConfigSetExpClk +#define SSIDataPut NOROM_SSIDataPut +#define SSIDataPutNonBlocking NOROM_SSIDataPutNonBlocking +#define SSIDataGet NOROM_SSIDataGet +#define SSIDataGetNonBlocking NOROM_SSIDataGetNonBlocking +#define SSIIntRegister NOROM_SSIIntRegister +#define SSIIntUnregister NOROM_SSIIntUnregister #endif //***************************************************************************** @@ -97,45 +96,45 @@ extern "C" // as the ui32IntFlags parameter, and returned by SSIIntStatus. // //***************************************************************************** -#define SSI_TXFF 0x00000008 // TX FIFO half full or less -#define SSI_RXFF 0x00000004 // RX FIFO half full or more -#define SSI_RXTO 0x00000002 // RX timeout -#define SSI_RXOR 0x00000001 // RX overrun +#define SSI_TXFF 0x00000008 // TX FIFO half full or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or more +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun //***************************************************************************** // // Values that are returned from SSIStatus // //***************************************************************************** -#define SSI_RX_FULL 0x00000008 // Receive FIFO full -#define SSI_RX_NOT_EMPTY 0x00000004 // Receive FIFO not empty -#define SSI_TX_NOT_FULL 0x00000002 // Transmit FIFO not full -#define SSI_TX_EMPTY 0x00000001 // Transmit FIFO empty -#define SSI_STATUS_MASK 0x0000000F +#define SSI_RX_FULL 0x00000008 // Receive FIFO full +#define SSI_RX_NOT_EMPTY 0x00000004 // Receive FIFO not empty +#define SSI_TX_NOT_FULL 0x00000002 // Transmit FIFO not full +#define SSI_TX_EMPTY 0x00000001 // Transmit FIFO empty +#define SSI_STATUS_MASK 0x0000000F //***************************************************************************** // // Values that can be passed to SSIConfigSetExpClk. // //***************************************************************************** -#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 -#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 -#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 -#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 -#define SSI_FRF_TI 0x00000010 // TI frame format -#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format -#define SSI_MODE_MASTER 0x00000000 // SSI master -#define SSI_MODE_SLAVE 0x00000001 // SSI slave -#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled //***************************************************************************** // // Values that can be passed to SSIDMAEnable() and SSIDMADisable(). // //***************************************************************************** -#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit -#define SSI_DMA_RX 0x00000001 // Enable DMA for receive +#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit +#define SSI_DMA_RX 0x00000001 // Enable DMA for receive //***************************************************************************** // @@ -651,32 +650,32 @@ SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_SSIConfigSetExpClk -#undef SSIConfigSetExpClk -#define SSIConfigSetExpClk ROM_SSIConfigSetExpClk +#undef SSIConfigSetExpClk +#define SSIConfigSetExpClk ROM_SSIConfigSetExpClk #endif #ifdef ROM_SSIDataPut -#undef SSIDataPut -#define SSIDataPut ROM_SSIDataPut +#undef SSIDataPut +#define SSIDataPut ROM_SSIDataPut #endif #ifdef ROM_SSIDataPutNonBlocking -#undef SSIDataPutNonBlocking -#define SSIDataPutNonBlocking ROM_SSIDataPutNonBlocking +#undef SSIDataPutNonBlocking +#define SSIDataPutNonBlocking ROM_SSIDataPutNonBlocking #endif #ifdef ROM_SSIDataGet -#undef SSIDataGet -#define SSIDataGet ROM_SSIDataGet +#undef SSIDataGet +#define SSIDataGet ROM_SSIDataGet #endif #ifdef ROM_SSIDataGetNonBlocking -#undef SSIDataGetNonBlocking -#define SSIDataGetNonBlocking ROM_SSIDataGetNonBlocking +#undef SSIDataGetNonBlocking +#define SSIDataGetNonBlocking ROM_SSIDataGetNonBlocking #endif #ifdef ROM_SSIIntRegister -#undef SSIIntRegister -#define SSIIntRegister ROM_SSIIntRegister +#undef SSIIntRegister +#define SSIIntRegister ROM_SSIIntRegister #endif #ifdef ROM_SSIIntUnregister -#undef SSIIntUnregister -#define SSIIntUnregister ROM_SSIIntUnregister +#undef SSIIntUnregister +#define SSIIntUnregister ROM_SSIIntUnregister #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-config.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-config.h index 2b338bd..93e071f 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-config.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-config.h @@ -1,8 +1,8 @@ /****************************************************************************** -* Filename: sw_ecrypt-config.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ + * Filename: sw_ecrypt-config.h + * Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) + * Revision: 47308 + ******************************************************************************/ /* ecrypt-config.h */ /* *** Normally, it should not be necessary to edit this file. *** */ @@ -17,46 +17,46 @@ /* * The LITTLE endian machines: */ -#if ( ! defined(ECRYPT_LITTLE_ENDIAN)) - #if defined(__ultrix) /* Older MIPS */ - #define ECRYPT_LITTLE_ENDIAN - #elif defined(__alpha) /* Alpha */ - #define ECRYPT_LITTLE_ENDIAN - #elif defined(i386) /* x86 (gcc) */ - #define ECRYPT_LITTLE_ENDIAN - #elif defined(__i386) /* x86 (gcc) */ - #define ECRYPT_LITTLE_ENDIAN - #elif defined(_M_IX86) /* x86 (MSC, Borland) */ - #define ECRYPT_LITTLE_ENDIAN - #elif defined(_MSC_VER) /* x86 (surely MSC) */ - #define ECRYPT_LITTLE_ENDIAN - #elif defined(__INTEL_COMPILER) /* x86 (surely Intel compiler icl.exe) */ - #define ECRYPT_LITTLE_ENDIAN +#if (!defined(ECRYPT_LITTLE_ENDIAN)) +#if defined(__ultrix) /* Older MIPS */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(__alpha) /* Alpha */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(i386) /* x86 (gcc) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(__i386) /* x86 (gcc) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(_M_IX86) /* x86 (MSC, Borland) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(_MSC_VER) /* x86 (surely MSC) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(__INTEL_COMPILER) /* x86 (surely Intel compiler icl.exe) */ +#define ECRYPT_LITTLE_ENDIAN - /* - * The BIG endian machines: - */ - #elif defined(sun) /* Newer Sparc's */ - #define ECRYPT_BIG_ENDIAN - #elif defined(__ppc__) /* PowerPC */ - #define ECRYPT_BIG_ENDIAN +/* + * The BIG endian machines: + */ +#elif defined(sun) /* Newer Sparc's */ +#define ECRYPT_BIG_ENDIAN +#elif defined(__ppc__) /* PowerPC */ +#define ECRYPT_BIG_ENDIAN - /* - * Finally machines with UNKNOWN endianness: - */ - #elif defined (_AIX) /* RS6000 */ - #define ECRYPT_UNKNOWN - #elif defined(__hpux) /* HP-PA */ - #define ECRYPT_UNKNOWN - #elif defined(__aux) /* 68K */ - #define ECRYPT_UNKNOWN - #elif defined(__dgux) /* 88K (but P6 in latest boxes) */ - #define ECRYPT_UNKNOWN - #elif defined(__sgi) /* Newer MIPS */ - #define ECRYPT_UNKNOWN - #else /* Any other processor */ - #define ECRYPT_UNKNOWN - #endif +/* + * Finally machines with UNKNOWN endianness: + */ +#elif defined(_AIX) /* RS6000 */ +#define ECRYPT_UNKNOWN +#elif defined(__hpux) /* HP-PA */ +#define ECRYPT_UNKNOWN +#elif defined(__aux) /* 68K */ +#define ECRYPT_UNKNOWN +#elif defined(__dgux) /* 88K (but P6 in latest boxes) */ +#define ECRYPT_UNKNOWN +#elif defined(__sgi) /* Newer MIPS */ +#define ECRYPT_UNKNOWN +#else /* Any other processor */ +#define ECRYPT_UNKNOWN +#endif #endif /* ------------------------------------------------------------------------- */ @@ -75,188 +75,188 @@ /* --- check char --- */ #if (UCHAR_MAX / 0xFU > 0xFU) - #ifndef I8T - #define I8T char - #define U8C(v) (v##U) +#ifndef I8T +#define I8T char +#define U8C(v) (v##U) - #if (UCHAR_MAX == 0xFFU) - #define ECRYPT_I8T_IS_BYTE - #endif +#if (UCHAR_MAX == 0xFFU) +#define ECRYPT_I8T_IS_BYTE +#endif - #endif +#endif - #if (UCHAR_MAX / 0xFFU > 0xFFU) - #ifndef I16T - #define I16T char - #define U16C(v) (v##U) - #endif +#if (UCHAR_MAX / 0xFFU > 0xFFU) +#ifndef I16T +#define I16T char +#define U16C(v) (v##U) +#endif - #if (UCHAR_MAX / 0xFFFFU > 0xFFFFU) - #ifndef I32T - #define I32T char - #define U32C(v) (v##U) - #endif +#if (UCHAR_MAX / 0xFFFFU > 0xFFFFU) +#ifndef I32T +#define I32T char +#define U32C(v) (v##U) +#endif - #if (UCHAR_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) - #ifndef I64T - #define I64T char - #define U64C(v) (v##U) - #define ECRYPT_NATIVE64 - #endif +#if (UCHAR_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) +#ifndef I64T +#define I64T char +#define U64C(v) (v##U) +#define ECRYPT_NATIVE64 +#endif - #endif - #endif - #endif +#endif +#endif +#endif #endif /* --- check short --- */ #if (USHRT_MAX / 0xFU > 0xFU) - #ifndef I8T - #define I8T short - #define U8C(v) (v##U) +#ifndef I8T +#define I8T short +#define U8C(v) (v##U) - #if (USHRT_MAX == 0xFFU) - #define ECRYPT_I8T_IS_BYTE - #endif +#if (USHRT_MAX == 0xFFU) +#define ECRYPT_I8T_IS_BYTE +#endif - #endif +#endif - #if (USHRT_MAX / 0xFFU > 0xFFU) - #ifndef I16T - #define I16T short - #define U16C(v) (v##U) - #endif +#if (USHRT_MAX / 0xFFU > 0xFFU) +#ifndef I16T +#define I16T short +#define U16C(v) (v##U) +#endif - #if (USHRT_MAX / 0xFFFFU > 0xFFFFU) - #ifndef I32T - #define I32T short - #define U32C(v) (v##U) - #endif +#if (USHRT_MAX / 0xFFFFU > 0xFFFFU) +#ifndef I32T +#define I32T short +#define U32C(v) (v##U) +#endif - #if (USHRT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) - #ifndef I64T - #define I64T short - #define U64C(v) (v##U) - #define ECRYPT_NATIVE64 - #endif +#if (USHRT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) +#ifndef I64T +#define I64T short +#define U64C(v) (v##U) +#define ECRYPT_NATIVE64 +#endif - #endif - #endif - #endif +#endif +#endif +#endif #endif /* --- check int --- */ #if (UINT_MAX / 0xFU > 0xFU) - #ifndef I8T - #define I8T int - #define U8C(v) (v##U) +#ifndef I8T +#define I8T int +#define U8C(v) (v##U) - #if (ULONG_MAX == 0xFFU) - #define ECRYPT_I8T_IS_BYTE - #endif +#if (ULONG_MAX == 0xFFU) +#define ECRYPT_I8T_IS_BYTE +#endif - #endif +#endif - #if (UINT_MAX / 0xFFU > 0xFFU) - #ifndef I16T - #define I16T int - #define U16C(v) (v##U) - #endif +#if (UINT_MAX / 0xFFU > 0xFFU) +#ifndef I16T +#define I16T int +#define U16C(v) (v##U) +#endif - #if (UINT_MAX / 0xFFFFU > 0xFFFFU) - #ifndef I32T - #define I32T int - #define U32C(v) (v##U) - #endif +#if (UINT_MAX / 0xFFFFU > 0xFFFFU) +#ifndef I32T +#define I32T int +#define U32C(v) (v##U) +#endif - #if (UINT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) - #ifndef I64T - #define I64T int - #define U64C(v) (v##U) - #define ECRYPT_NATIVE64 - #endif +#if (UINT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) +#ifndef I64T +#define I64T int +#define U64C(v) (v##U) +#define ECRYPT_NATIVE64 +#endif - #endif - #endif - #endif +#endif +#endif +#endif #endif /* --- check long --- */ #if (ULONG_MAX / 0xFUL > 0xFUL) - #ifndef I8T - #define I8T long - #define U8C(v) (v##UL) +#ifndef I8T +#define I8T long +#define U8C(v) (v##UL) - #if (ULONG_MAX == 0xFFUL) - #define ECRYPT_I8T_IS_BYTE - #endif +#if (ULONG_MAX == 0xFFUL) +#define ECRYPT_I8T_IS_BYTE +#endif - #endif +#endif - #if (ULONG_MAX / 0xFFUL > 0xFFUL) - #ifndef I16T - #define I16T long - #define U16C(v) (v##UL) - #endif +#if (ULONG_MAX / 0xFFUL > 0xFFUL) +#ifndef I16T +#define I16T long +#define U16C(v) (v##UL) +#endif - #if (ULONG_MAX / 0xFFFFUL > 0xFFFFUL) - #ifndef I32T - #define I32T long - #define U32C(v) (v##UL) - #endif +#if (ULONG_MAX / 0xFFFFUL > 0xFFFFUL) +#ifndef I32T +#define I32T long +#define U32C(v) (v##UL) +#endif - #if (ULONG_MAX / 0xFFFFFFFFUL > 0xFFFFFFFFUL) - #ifndef I64T - #define I64T long - #define U64C(v) (v##UL) - #define ECRYPT_NATIVE64 - #endif +#if (ULONG_MAX / 0xFFFFFFFFUL > 0xFFFFFFFFUL) +#ifndef I64T +#define I64T long +#define U64C(v) (v##UL) +#define ECRYPT_NATIVE64 +#endif - #endif - #endif - #endif +#endif +#endif +#endif #endif /* --- check long long --- */ #ifdef ULLONG_MAX - #if (ULLONG_MAX / 0xFULL > 0xFULL) - #ifndef I8T - #define I8T long long - #define U8C(v) (v##ULL) +#if (ULLONG_MAX / 0xFULL > 0xFULL) +#ifndef I8T +#define I8T long long +#define U8C(v) (v##ULL) - #if (ULLONG_MAX == 0xFFULL) - #define ECRYPT_I8T_IS_BYTE - #endif +#if (ULLONG_MAX == 0xFFULL) +#define ECRYPT_I8T_IS_BYTE +#endif - #endif +#endif - #if (ULLONG_MAX / 0xFFULL > 0xFFULL) - #ifndef I16T - #define I16T long long - #define U16C(v) (v##ULL) - #endif +#if (ULLONG_MAX / 0xFFULL > 0xFFULL) +#ifndef I16T +#define I16T long long +#define U16C(v) (v##ULL) +#endif - #if (ULLONG_MAX / 0xFFFFULL > 0xFFFFULL) - #ifndef I32T - #define I32T long long - #define U32C(v) (v##ULL) - #endif +#if (ULLONG_MAX / 0xFFFFULL > 0xFFFFULL) +#ifndef I32T +#define I32T long long +#define U32C(v) (v##ULL) +#endif - #if (ULLONG_MAX / 0xFFFFFFFFULL > 0xFFFFFFFFULL) - #ifndef I64T - #define I64T long long - #define U64C(v) (v##ULL) - #endif +#if (ULLONG_MAX / 0xFFFFFFFFULL > 0xFFFFFFFFULL) +#ifndef I64T +#define I64T long long +#define U64C(v) (v##ULL) +#endif - #endif - #endif - #endif - #endif +#endif +#endif +#endif +#endif #endif @@ -264,13 +264,13 @@ #ifdef _UI64_MAX - #if (_UI64_MAX / 0xFFFFFFFFui64 > 0xFFFFFFFFui64) - #ifndef I64T - #define I64T __int64 - #define U64C(v) (v##ui64) - #endif +#if (_UI64_MAX / 0xFFFFFFFFui64 > 0xFFFFFFFFui64) +#ifndef I64T +#define I64T __int64 +#define U64C(v) (v##ui64) +#endif - #endif +#endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-machine.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-machine.h index a3eba88..48788a8 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-machine.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-machine.h @@ -1,8 +1,8 @@ /****************************************************************************** -* Filename: sw_ecrypt-machine.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ + * Filename: sw_ecrypt-machine.h + * Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) + * Revision: 47308 + ******************************************************************************/ /* ecrypt-machine.h */ /* @@ -16,23 +16,23 @@ #if (defined(ECRYPT_DEFAULT_ROT) && !defined(ECRYPT_MACHINE_ROT)) - #define ECRYPT_MACHINE_ROT +#define ECRYPT_MACHINE_ROT - #if (defined(WIN32) && defined(_MSC_VER)) +#if (defined(WIN32) && defined(_MSC_VER)) - #undef ROTL32 - #undef ROTR32 - #undef ROTL64 - #undef ROTR64 +#undef ROTL32 +#undef ROTR32 +#undef ROTL64 +#undef ROTR64 - #include +#include - #define ROTL32(v, n) _lrotl(v, n) - #define ROTR32(v, n) _lrotr(v, n) - #define ROTL64(v, n) _rotl64(v, n) - #define ROTR64(v, n) _rotr64(v, n) +#define ROTL32(v, n) _lrotl(v, n) +#define ROTR32(v, n) _lrotr(v, n) +#define ROTL64(v, n) _rotl64(v, n) +#define ROTR64(v, n) _rotr64(v, n) - #endif +#endif #endif @@ -40,11 +40,11 @@ #if (defined(ECRYPT_DEFAULT_SWAP) && !defined(ECRYPT_MACHINE_SWAP)) - #define ECRYPT_MACHINE_SWAP +#define ECRYPT_MACHINE_SWAP - /* - * If you want to overwrite the default swap macros, put it here. And so on. - */ +/* + * If you want to overwrite the default swap macros, put it here. And so on. + */ #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-portable.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-portable.h index 600c718..067451a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-portable.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-portable.h @@ -1,8 +1,8 @@ /****************************************************************************** -* Filename: sw_ecrypt-portable.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ + * Filename: sw_ecrypt-portable.h + * Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) + * Revision: 47308 + ******************************************************************************/ /* ecrypt-portable.h */ /* @@ -46,23 +46,23 @@ */ #ifdef I8T - typedef signed I8T s8; - typedef unsigned I8T u8; +typedef signed I8T s8; +typedef unsigned I8T u8; #endif #ifdef I16T - typedef signed I16T s16; - typedef unsigned I16T u16; +typedef signed I16T s16; +typedef unsigned I16T u16; #endif #ifdef I32T - typedef signed I32T s32; - typedef unsigned I32T u32; +typedef signed I32T s32; +typedef unsigned I32T u32; #endif #ifdef I64T - typedef signed I64T s64; - typedef unsigned I64T u64; +typedef signed I64T s64; +typedef unsigned I64T u64; #endif /* @@ -113,13 +113,13 @@ #define SWAP16(v) \ ROTL16(v, 8) -#define SWAP32(v) \ - ((ROTL32(v, 8) & U32C(0x00FF00FF)) | \ +#define SWAP32(v) \ + ((ROTL32(v, 8) & U32C(0x00FF00FF)) | \ (ROTL32(v, 24) & U32C(0xFF00FF00))) #ifdef ECRYPT_NATIVE64 -#define SWAP64(v) \ - ((ROTL64(v, 8) & U64C(0x000000FF000000FF)) | \ +#define SWAP64(v) \ + ((ROTL64(v, 8) & U64C(0x000000FF000000FF)) | \ (ROTL64(v, 24) & U64C(0x0000FF000000FF00)) | \ (ROTL64(v, 40) & U64C(0x00FF000000FF0000)) | \ (ROTL64(v, 56) & U64C(0xFF000000FF000000))) @@ -133,23 +133,23 @@ #define ECRYPT_DEFAULT_WTOW #ifdef ECRYPT_LITTLE_ENDIAN - #define U16TO16_LITTLE(v) (v) - #define U32TO32_LITTLE(v) (v) - #define U64TO64_LITTLE(v) (v) +#define U16TO16_LITTLE(v) (v) +#define U32TO32_LITTLE(v) (v) +#define U64TO64_LITTLE(v) (v) - #define U16TO16_BIG(v) SWAP16(v) - #define U32TO32_BIG(v) SWAP32(v) - #define U64TO64_BIG(v) SWAP64(v) +#define U16TO16_BIG(v) SWAP16(v) +#define U32TO32_BIG(v) SWAP32(v) +#define U64TO64_BIG(v) SWAP64(v) #endif #ifdef ECRYPT_BIG_ENDIAN - #define U16TO16_LITTLE(v) SWAP16(v) - #define U32TO32_LITTLE(v) SWAP32(v) - #define U64TO64_LITTLE(v) SWAP64(v) +#define U16TO16_LITTLE(v) SWAP16(v) +#define U32TO32_LITTLE(v) SWAP32(v) +#define U64TO64_LITTLE(v) SWAP64(v) - #define U16TO16_BIG(v) (v) - #define U32TO32_BIG(v) (v) - #define U64TO64_BIG(v) (v) +#define U16TO16_BIG(v) (v) +#define U32TO32_BIG(v) (v) +#define U64TO64_BIG(v) (v) #endif #include "sw_ecrypt-machine.h" @@ -163,38 +163,38 @@ #if (!defined(ECRYPT_UNKNOWN) && defined(ECRYPT_I8T_IS_BYTE)) -#define U8TO16_LITTLE(p) U16TO16_LITTLE(((u16*)(p))[0]) -#define U8TO32_LITTLE(p) U32TO32_LITTLE(((u32*)(p))[0]) -#define U8TO64_LITTLE(p) U64TO64_LITTLE(((u64*)(p))[0]) +#define U8TO16_LITTLE(p) U16TO16_LITTLE(((u16 *)(p))[0]) +#define U8TO32_LITTLE(p) U32TO32_LITTLE(((u32 *)(p))[0]) +#define U8TO64_LITTLE(p) U64TO64_LITTLE(((u64 *)(p))[0]) -#define U8TO16_BIG(p) U16TO16_BIG(((u16*)(p))[0]) -#define U8TO32_BIG(p) U32TO32_BIG(((u32*)(p))[0]) -#define U8TO64_BIG(p) U64TO64_BIG(((u64*)(p))[0]) +#define U8TO16_BIG(p) U16TO16_BIG(((u16 *)(p))[0]) +#define U8TO32_BIG(p) U32TO32_BIG(((u32 *)(p))[0]) +#define U8TO64_BIG(p) U64TO64_BIG(((u64 *)(p))[0]) -#define U16TO8_LITTLE(p, v) (((u16*)(p))[0] = U16TO16_LITTLE(v)) -#define U32TO8_LITTLE(p, v) (((u32*)(p))[0] = U32TO32_LITTLE(v)) -#define U64TO8_LITTLE(p, v) (((u64*)(p))[0] = U64TO64_LITTLE(v)) +#define U16TO8_LITTLE(p, v) (((u16 *)(p))[0] = U16TO16_LITTLE(v)) +#define U32TO8_LITTLE(p, v) (((u32 *)(p))[0] = U32TO32_LITTLE(v)) +#define U64TO8_LITTLE(p, v) (((u64 *)(p))[0] = U64TO64_LITTLE(v)) -#define U16TO8_BIG(p, v) (((u16*)(p))[0] = U16TO16_BIG(v)) -#define U32TO8_BIG(p, v) (((u32*)(p))[0] = U32TO32_BIG(v)) -#define U64TO8_BIG(p, v) (((u64*)(p))[0] = U64TO64_BIG(v)) +#define U16TO8_BIG(p, v) (((u16 *)(p))[0] = U16TO16_BIG(v)) +#define U32TO8_BIG(p, v) (((u32 *)(p))[0] = U32TO32_BIG(v)) +#define U64TO8_BIG(p, v) (((u64 *)(p))[0] = U64TO64_BIG(v)) #else #define U8TO16_LITTLE(p) \ - (((u16)((p)[0]) ) | \ - ((u16)((p)[1]) << 8)) + (((u16)((p)[0])) | \ + ((u16)((p)[1]) << 8)) -#define U8TO32_LITTLE(p) \ - (((u32)((p)[0]) ) | \ - ((u32)((p)[1]) << 8) | \ +#define U8TO32_LITTLE(p) \ + (((u32)((p)[0])) | \ + ((u32)((p)[1]) << 8) | \ ((u32)((p)[2]) << 16) | \ ((u32)((p)[3]) << 24)) #ifdef ECRYPT_NATIVE64 -#define U8TO64_LITTLE(p) \ - (((u64)((p)[0]) ) | \ - ((u64)((p)[1]) << 8) | \ +#define U8TO64_LITTLE(p) \ + (((u64)((p)[0])) | \ + ((u64)((p)[1]) << 8) | \ ((u64)((p)[2]) << 16) | \ ((u64)((p)[3]) << 24) | \ ((u64)((p)[4]) << 32) | \ @@ -206,50 +206,53 @@ ((u64)U8TO32_LITTLE(p) | ((u64)U8TO32_LITTLE((p) + 4) << 32)) #endif -#define U8TO16_BIG(p) \ - (((u16)((p)[0]) << 8) | \ - ((u16)((p)[1]) )) +#define U8TO16_BIG(p) \ + (((u16)((p)[0]) << 8) | \ + ((u16)((p)[1]))) -#define U8TO32_BIG(p) \ +#define U8TO32_BIG(p) \ (((u32)((p)[0]) << 24) | \ ((u32)((p)[1]) << 16) | \ - ((u32)((p)[2]) << 8) | \ - ((u32)((p)[3]) )) + ((u32)((p)[2]) << 8) | \ + ((u32)((p)[3]))) #ifdef ECRYPT_NATIVE64 -#define U8TO64_BIG(p) \ +#define U8TO64_BIG(p) \ (((u64)((p)[0]) << 56) | \ ((u64)((p)[1]) << 48) | \ ((u64)((p)[2]) << 40) | \ ((u64)((p)[3]) << 32) | \ ((u64)((p)[4]) << 24) | \ ((u64)((p)[5]) << 16) | \ - ((u64)((p)[6]) << 8) | \ - ((u64)((p)[7]) )) + ((u64)((p)[6]) << 8) | \ + ((u64)((p)[7]))) #else #define U8TO64_BIG(p) \ (((u64)U8TO32_BIG(p) << 32) | (u64)U8TO32_BIG((p) + 4)) #endif -#define U16TO8_LITTLE(p, v) \ - do { \ - (p)[0] = U8V((v) ); \ - (p)[1] = U8V((v) >> 8); \ +#define U16TO8_LITTLE(p, v) \ + do \ + { \ + (p)[0] = U8V((v)); \ + (p)[1] = U8V((v) >> 8); \ } while (0) -#define U32TO8_LITTLE(p, v) \ - do { \ - (p)[0] = U8V((v) ); \ - (p)[1] = U8V((v) >> 8); \ +#define U32TO8_LITTLE(p, v) \ + do \ + { \ + (p)[0] = U8V((v)); \ + (p)[1] = U8V((v) >> 8); \ (p)[2] = U8V((v) >> 16); \ (p)[3] = U8V((v) >> 24); \ } while (0) #ifdef ECRYPT_NATIVE64 -#define U64TO8_LITTLE(p, v) \ - do { \ - (p)[0] = U8V((v) ); \ - (p)[1] = U8V((v) >> 8); \ +#define U64TO8_LITTLE(p, v) \ + do \ + { \ + (p)[0] = U8V((v)); \ + (p)[1] = U8V((v) >> 8); \ (p)[2] = U8V((v) >> 16); \ (p)[3] = U8V((v) >> 24); \ (p)[4] = U8V((v) >> 32); \ @@ -258,44 +261,49 @@ (p)[7] = U8V((v) >> 56); \ } while (0) #else -#define U64TO8_LITTLE(p, v) \ - do { \ - U32TO8_LITTLE((p), U32V((v) )); \ +#define U64TO8_LITTLE(p, v) \ + do \ + { \ + U32TO8_LITTLE((p), U32V((v))); \ U32TO8_LITTLE((p) + 4, U32V((v) >> 32)); \ } while (0) #endif -#define U16TO8_BIG(p, v) \ - do { \ - (p)[0] = U8V((v) ); \ - (p)[1] = U8V((v) >> 8); \ +#define U16TO8_BIG(p, v) \ + do \ + { \ + (p)[0] = U8V((v)); \ + (p)[1] = U8V((v) >> 8); \ } while (0) -#define U32TO8_BIG(p, v) \ - do { \ +#define U32TO8_BIG(p, v) \ + do \ + { \ (p)[0] = U8V((v) >> 24); \ (p)[1] = U8V((v) >> 16); \ - (p)[2] = U8V((v) >> 8); \ - (p)[3] = U8V((v) ); \ + (p)[2] = U8V((v) >> 8); \ + (p)[3] = U8V((v)); \ } while (0) #ifdef ECRYPT_NATIVE64 -#define U64TO8_BIG(p, v) \ - do { \ +#define U64TO8_BIG(p, v) \ + do \ + { \ (p)[0] = U8V((v) >> 56); \ (p)[1] = U8V((v) >> 48); \ (p)[2] = U8V((v) >> 40); \ (p)[3] = U8V((v) >> 32); \ (p)[4] = U8V((v) >> 24); \ (p)[5] = U8V((v) >> 16); \ - (p)[6] = U8V((v) >> 8); \ - (p)[7] = U8V((v) ); \ + (p)[6] = U8V((v) >> 8); \ + (p)[7] = U8V((v)); \ } while (0) #else -#define U64TO8_BIG(p, v) \ - do { \ - U32TO8_BIG((p), U32V((v) >> 32)); \ - U32TO8_BIG((p) + 4, U32V((v) )); \ +#define U64TO8_BIG(p, v) \ + do \ + { \ + U32TO8_BIG((p), U32V((v) >> 32)); \ + U32TO8_BIG((p) + 4, U32V((v))); \ } while (0) #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-sync.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-sync.h index 7d9a344..e3ac4d2 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-sync.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_ecrypt-sync.h @@ -1,8 +1,8 @@ /****************************************************************************** -* Filename: sw_ecrypt-sync.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ + * Filename: sw_ecrypt-sync.h + * Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) + * Revision: 47308 + ******************************************************************************/ /* ecrypt-sync.h */ /* @@ -42,11 +42,11 @@ * All sizes are in bits. */ -#define ECRYPT_MAXKEYSIZE 256 /* [edit] */ -#define ECRYPT_KEYSIZE(i) (128 + (i)*128) /* [edit] */ +#define ECRYPT_MAXKEYSIZE 256 /* [edit] */ +#define ECRYPT_KEYSIZE(i) (128 + (i) * 128) /* [edit] */ -#define ECRYPT_MAXIVSIZE 64 /* [edit] */ -#define ECRYPT_IVSIZE(i) (64 + (i)*64) /* [edit] */ +#define ECRYPT_MAXIVSIZE 64 /* [edit] */ +#define ECRYPT_IVSIZE(i) (64 + (i) * 64) /* [edit] */ /* ------------------------------------------------------------------------- */ @@ -59,12 +59,12 @@ typedef struct { - u32 input[16]; /* could be compressed */ - /* - * [edit] - * - * Put here all state variable needed during the encryption process. - */ + u32 input[16]; /* could be compressed */ + /* + * [edit] + * + * Put here all state variable needed during the encryption process. + */ } ECRYPT_ctx; /* ------------------------------------------------------------------------- */ @@ -86,8 +86,8 @@ void ECRYPT_init(void); void ECRYPT_keysetup( ECRYPT_ctx* ctx, const u8* key, - u32 keysize, /* Key size in bits. */ - u32 ivsize); /* IV size in bits. */ + u32 keysize, /* Key size in bits. */ + u32 ivsize); /* IV size in bits. */ /* * IV setup. After having called ECRYPT_keysetup(), the user is @@ -141,13 +141,13 @@ void ECRYPT_encrypt_bytes( ECRYPT_ctx* ctx, const u8* plaintext, u8* ciphertext, - u32 msglen); /* Message length in bytes. */ + u32 msglen); /* Message length in bytes. */ void ECRYPT_decrypt_bytes( ECRYPT_ctx* ctx, const u8* ciphertext, u8* plaintext, - u32 msglen); /* Message length in bytes. */ + u32 msglen); /* Message length in bytes. */ /* ------------------------------------------------------------------------- */ @@ -167,7 +167,7 @@ void ECRYPT_decrypt_bytes( void ECRYPT_keystream_bytes( ECRYPT_ctx* ctx, u8* keystream, - u32 length); /* Length of keystream in bytes. */ + u32 length); /* Length of keystream in bytes. */ #endif @@ -188,7 +188,7 @@ void ECRYPT_keystream_bytes( * "ecrypt-sync.c". If you want to implement them differently, please * undef the ECRYPT_USES_DEFAULT_ALL_IN_ONE flag. */ -#define ECRYPT_USES_DEFAULT_ALL_IN_ONE /* [edit] */ +#define ECRYPT_USES_DEFAULT_ALL_IN_ONE /* [edit] */ void ECRYPT_encrypt_packet( ECRYPT_ctx* ctx, @@ -213,23 +213,23 @@ void ECRYPT_decrypt_packet( * declared below. */ -#define ECRYPT_BLOCKLENGTH 64 /* [edit] */ +#define ECRYPT_BLOCKLENGTH 64 /* [edit] */ -#define ECRYPT_USES_DEFAULT_BLOCK_MACROS /* [edit] */ +#define ECRYPT_USES_DEFAULT_BLOCK_MACROS /* [edit] */ #ifdef ECRYPT_USES_DEFAULT_BLOCK_MACROS -#define ECRYPT_encrypt_blocks(ctx, plaintext, ciphertext, blocks) \ - ECRYPT_encrypt_bytes(ctx, plaintext, ciphertext, \ +#define ECRYPT_encrypt_blocks(ctx, plaintext, ciphertext, blocks) \ + ECRYPT_encrypt_bytes(ctx, plaintext, ciphertext, \ (blocks) * ECRYPT_BLOCKLENGTH) -#define ECRYPT_decrypt_blocks(ctx, ciphertext, plaintext, blocks) \ - ECRYPT_decrypt_bytes(ctx, ciphertext, plaintext, \ +#define ECRYPT_decrypt_blocks(ctx, ciphertext, plaintext, blocks) \ + ECRYPT_decrypt_bytes(ctx, ciphertext, plaintext, \ (blocks) * ECRYPT_BLOCKLENGTH) #ifdef ECRYPT_GENERATES_KEYSTREAM -#define ECRYPT_keystream_blocks(ctx, keystream, blocks) \ - ECRYPT_keystream_bytes(ctx, keystream, \ +#define ECRYPT_keystream_blocks(ctx, keystream, blocks) \ + ECRYPT_keystream_bytes(ctx, keystream, \ (blocks) * ECRYPT_BLOCKLENGTH) #endif @@ -240,20 +240,20 @@ void ECRYPT_encrypt_blocks( ECRYPT_ctx* ctx, const u8* plaintext, u8* ciphertext, - u32 blocks); /* Message length in blocks. */ + u32 blocks); /* Message length in blocks. */ void ECRYPT_decrypt_blocks( ECRYPT_ctx* ctx, const u8* ciphertext, u8* plaintext, - u32 blocks); /* Message length in blocks. */ + u32 blocks); /* Message length in blocks. */ #ifdef ECRYPT_GENERATES_KEYSTREAM void ECRYPT_keystream_blocks( ECRYPT_ctx* ctx, const u8* keystream, - u32 blocks); /* Keystream length in blocks. */ + u32 blocks); /* Keystream length in blocks. */ #endif @@ -269,14 +269,14 @@ void ECRYPT_keystream_blocks( * 10). Note also that all variants should have exactly the same * external interface (i.e., the same ECRYPT_BLOCKLENGTH, etc.). */ -#define ECRYPT_MAXVARIANT 1 /* [edit] */ +#define ECRYPT_MAXVARIANT 1 /* [edit] */ #ifndef ECRYPT_VARIANT - #define ECRYPT_VARIANT 1 +#define ECRYPT_VARIANT 1 #endif #if (ECRYPT_VARIANT > ECRYPT_MAXVARIANT) - #error this variant does not exist +#error this variant does not exist #endif /* ------------------------------------------------------------------------- */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_poly1305-donna-32.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_poly1305-donna-32.h index 3e4eb10..73b809a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_poly1305-donna-32.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_poly1305-donna-32.h @@ -1,18 +1,18 @@ /****************************************************************************** -* Filename: sw_poly1305-donna-32.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ + * Filename: sw_poly1305-donna-32.h + * Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) + * Revision: 47308 + ******************************************************************************/ /* poly1305 implementation using 32 bit * 32 bit = 64 bit multiplication and 64 bit addition */ #if defined(_MSC_VER) - #define POLY1305_NOINLINE __declspec(noinline) +#define POLY1305_NOINLINE __declspec(noinline) #elif defined(__GNUC__) - #define POLY1305_NOINLINE __attribute__((noinline)) +#define POLY1305_NOINLINE __attribute__((noinline)) #else - #define POLY1305_NOINLINE +#define POLY1305_NOINLINE #endif #define poly1305_block_size 16 @@ -20,29 +20,28 @@ /* 17 + sizeof(size_t) + 14*sizeof(unsigned long) */ typedef struct { - unsigned long r[5]; - unsigned long h[5]; - unsigned long pad[4]; - size_t leftover; - unsigned char buffer[poly1305_block_size]; - unsigned char final; + unsigned long r[5]; + unsigned long h[5]; + unsigned long pad[4]; + size_t leftover; + unsigned char buffer[poly1305_block_size]; + unsigned char final; } poly1305_state_internal_t; /* interpret four 8 bit unsigned integers as a 32 bit unsigned integer in little endian */ static unsigned long U8TO32(const unsigned char* p) { - return - (((unsigned long)(p[0] & 0xff) ) | - ((unsigned long)(p[1] & 0xff) << 8) | - ((unsigned long)(p[2] & 0xff) << 16) | - ((unsigned long)(p[3] & 0xff) << 24)); + return (((unsigned long)(p[0] & 0xff)) | + ((unsigned long)(p[1] & 0xff) << 8) | + ((unsigned long)(p[2] & 0xff) << 16) | + ((unsigned long)(p[3] & 0xff) << 24)); } /* store a 32 bit unsigned integer as four 8 bit unsigned integers in little endian */ static void U32TO8(unsigned char* p, unsigned long v) { - p[0] = (v ) & 0xff; - p[1] = (v >> 8) & 0xff; + p[0] = (v) & 0xff; + p[1] = (v >> 8) & 0xff; p[2] = (v >> 16) & 0xff; p[3] = (v >> 24) & 0xff; } @@ -52,10 +51,10 @@ void poly1305_init(poly1305_context* ctx, const unsigned char key[32]) poly1305_state_internal_t* st = (poly1305_state_internal_t*)ctx; /* r &= 0xffffffc0ffffffc0ffffffc0fffffff */ - st->r[0] = (U8TO32(&key[ 0]) ) & 0x3ffffff; - st->r[1] = (U8TO32(&key[ 3]) >> 2) & 0x3ffff03; - st->r[2] = (U8TO32(&key[ 6]) >> 4) & 0x3ffc0ff; - st->r[3] = (U8TO32(&key[ 9]) >> 6) & 0x3f03fff; + st->r[0] = (U8TO32(&key[0])) & 0x3ffffff; + st->r[1] = (U8TO32(&key[3]) >> 2) & 0x3ffff03; + st->r[2] = (U8TO32(&key[6]) >> 4) & 0x3ffc0ff; + st->r[3] = (U8TO32(&key[9]) >> 6) & 0x3f03fff; st->r[4] = (U8TO32(&key[12]) >> 8) & 0x00fffff; /* h = 0 */ @@ -104,7 +103,7 @@ static void poly1305_blocks(poly1305_state_internal_t* st, const unsigned char* while (bytes >= poly1305_block_size) { /* h += m[i] */ - h0 += (U8TO32(m + 0) ) & 0x3ffffff; + h0 += (U8TO32(m + 0)) & 0x3ffffff; h1 += (U8TO32(m + 3) >> 2) & 0x3ffffff; h2 += (U8TO32(m + 6) >> 4) & 0x3ffffff; h3 += (U8TO32(m + 9) >> 6) & 0x3ffffff; @@ -133,8 +132,8 @@ static void poly1305_blocks(poly1305_state_internal_t* st, const unsigned char* c = (unsigned long)(d4 >> 26); h4 = (unsigned long)d4 & 0x3ffffff; h0 += c * 5; - c = (h0 >> 26); - h0 = h0 & 0x3ffffff; + c = (h0 >> 26); + h0 = h0 & 0x3ffffff; h1 += c; m += poly1305_block_size; @@ -178,19 +177,19 @@ POLY1305_NOINLINE void poly1305_finish(poly1305_context* ctx, unsigned char mac[ c = h1 >> 26; h1 = h1 & 0x3ffffff; - h2 += c; + h2 += c; c = h2 >> 26; h2 = h2 & 0x3ffffff; - h3 += c; + h3 += c; c = h3 >> 26; h3 = h3 & 0x3ffffff; - h4 += c; + h4 += c; c = h4 >> 26; h4 = h4 & 0x3ffffff; h0 += c * 5; c = h0 >> 26; h0 = h0 & 0x3ffffff; - h1 += c; + h1 += c; /* compute h + -p */ g0 = h0 + 5; @@ -222,13 +221,13 @@ POLY1305_NOINLINE void poly1305_finish(poly1305_context* ctx, unsigned char mac[ h4 = (h4 & mask) | g4; /* h = h % (2^128) */ - h0 = ((h0 ) | (h1 << 26)) & 0xffffffff; - h1 = ((h1 >> 6) | (h2 << 20)) & 0xffffffff; + h0 = ((h0) | (h1 << 26)) & 0xffffffff; + h1 = ((h1 >> 6) | (h2 << 20)) & 0xffffffff; h2 = ((h2 >> 12) | (h3 << 14)) & 0xffffffff; - h3 = ((h3 >> 18) | (h4 << 8)) & 0xffffffff; + h3 = ((h3 >> 18) | (h4 << 8)) & 0xffffffff; /* mac = (h + pad) % (2^128) */ - f = (unsigned long long)h0 + st->pad[0] ; + f = (unsigned long long)h0 + st->pad[0]; h0 = (unsigned long)f; f = (unsigned long long)h1 + st->pad[1] + (f >> 32); h1 = (unsigned long)f; @@ -237,9 +236,9 @@ POLY1305_NOINLINE void poly1305_finish(poly1305_context* ctx, unsigned char mac[ f = (unsigned long long)h3 + st->pad[3] + (f >> 32); h3 = (unsigned long)f; - U32TO8(mac + 0, h0); - U32TO8(mac + 4, h1); - U32TO8(mac + 8, h2); + U32TO8(mac + 0, h0); + U32TO8(mac + 4, h1); + U32TO8(mac + 8, h2); U32TO8(mac + 12, h3); /* zero out the state */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_poly1305-donna.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_poly1305-donna.h index a544927..3230064 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_poly1305-donna.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sw_poly1305-donna.h @@ -1,8 +1,8 @@ /****************************************************************************** -* Filename: sw_poly1305-donna.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ + * Filename: sw_poly1305-donna.h + * Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) + * Revision: 47308 + ******************************************************************************/ #ifndef POLY1305_DONNA_H #define POLY1305_DONNA_H @@ -11,8 +11,8 @@ typedef struct { - size_t aligner; - unsigned char opaque[136]; + size_t aligner; + unsigned char opaque[136]; } poly1305_context; void poly1305_init(poly1305_context* ctx, const unsigned char key[32]); diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sys_ctrl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sys_ctrl.h index 7ecddc4..356974c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sys_ctrl.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/sys_ctrl.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: sys_ctrl.h -* Revised: 2018-09-17 14:58:51 +0200 (Mon, 17 Sep 2018) -* Revision: 52634 -* -* Description: Defines and prototypes for the System Controller. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: sys_ctrl.h + * Revised: 2018-09-17 14:58:51 +0200 (Mon, 17 Sep 2018) + * Revision: 52634 + * + * Description: Defines and prototypes for the System Controller. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,39 +55,37 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_sysctl.h" -#include "../inc/hw_prcm.h" -#include "../inc/hw_nvic.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_aon_ioc.h" +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_aon_sysctl.h" #include "../inc/hw_aon_wuc.h" #include "../inc/hw_aux_wuc.h" -#include "../inc/hw_aon_ioc.h" #include "../inc/hw_ddi_0_osc.h" -#include "../inc/hw_rfc_pwr.h" -#include "../inc/hw_prcm.h" -#include "../inc/hw_adi_3_refsys.h" -#include "../inc/hw_aon_sysctl.h" -#include "../inc/hw_aon_rtc.h" #include "../inc/hw_fcfg1.h" -#include "interrupt.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_nvic.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_rfc_pwr.h" +#include "../inc/hw_sysctl.h" +#include "../inc/hw_types.h" +#include "adi.h" +#include "aon_wuc.h" +#include "aux_wuc.h" +#include "cpu.h" +#include "ddi.h" #include "debug.h" -#include "pwr_ctrl.h" +#include "interrupt.h" #include "osc.h" #include "prcm.h" -#include "aux_wuc.h" -#include "aon_wuc.h" -#include "adi.h" -#include "ddi.h" -#include "cpu.h" +#include "pwr_ctrl.h" #include "vims.h" +#include +#include //***************************************************************************** // @@ -106,7 +104,7 @@ extern "C" #define SysCtrlSetRechargeBeforePowerDown NOROM_SysCtrlSetRechargeBeforePowerDown #define SysCtrlAdjustRechargeAfterPowerDown NOROM_SysCtrlAdjustRechargeAfterPowerDown #define SysCtrl_DCDC_VoltageConditionalControl NOROM_SysCtrl_DCDC_VoltageConditionalControl -#define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet +#define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet #endif //***************************************************************************** @@ -114,17 +112,17 @@ extern "C" // Defines for the settings of the main XOSC // //***************************************************************************** -#define SYSCTRL_SYSBUS_ON 0x00000001 -#define SYSCTRL_SYSBUS_OFF 0x00000000 +#define SYSCTRL_SYSBUS_ON 0x00000001 +#define SYSCTRL_SYSBUS_OFF 0x00000000 //***************************************************************************** // // Defines for the different power modes of the System CPU // //***************************************************************************** -#define CPU_RUN 0x00000000 -#define CPU_SLEEP 0x00000001 -#define CPU_DEEP_SLEEP 0x00000002 +#define CPU_RUN 0x00000000 +#define CPU_SLEEP 0x00000001 +#define CPU_DEEP_SLEEP 0x00000002 //***************************************************************************** // @@ -132,7 +130,7 @@ extern "C" // //***************************************************************************** #define XOSC_IN_HIGH_POWER_MODE 0 // When xosc_hf is in HIGH_POWER_XOSC -#define XOSC_IN_LOW_POWER_MODE 1 // When xosc_hf is in LOW_POWER_XOSC +#define XOSC_IN_LOW_POWER_MODE 1 // When xosc_hf is in LOW_POWER_XOSC //***************************************************************************** // @@ -153,10 +151,10 @@ extern "C" // //***************************************************************************** __STATIC_INLINE uint32_t -SysCtrlClockGet( void ) +SysCtrlClockGet(void) { // Return fixed clock speed - return ( GET_MCU_CLOCK ); + return (GET_MCU_CLOCK); } //***************************************************************************** @@ -230,7 +228,7 @@ SysCtrlAonUpdate(void) //! \return None // //***************************************************************************** -extern void SysCtrlSetRechargeBeforePowerDown( uint32_t xoscPowerMode ); +extern void SysCtrlSetRechargeBeforePowerDown(uint32_t xoscPowerMode); //***************************************************************************** // @@ -254,7 +252,7 @@ extern void SysCtrlSetRechargeBeforePowerDown( uint32_t xoscPowerMode ); //! \return None // //***************************************************************************** -extern void SysCtrlAdjustRechargeAfterPowerDown( uint32_t vddrRechargeMargin ); +extern void SysCtrlAdjustRechargeAfterPowerDown(uint32_t vddrRechargeMargin); //***************************************************************************** // @@ -271,20 +269,20 @@ extern void SysCtrlAdjustRechargeAfterPowerDown( uint32_t vddrRechargeMargin ); //! \return None // //***************************************************************************** -extern void SysCtrl_DCDC_VoltageConditionalControl( void ); +extern void SysCtrl_DCDC_VoltageConditionalControl(void); //***************************************************************************** // \name Return values from calling SysCtrlResetSourceGet() //@{ //***************************************************************************** -#define RSTSRC_PWR_ON (( AON_SYSCTL_RESETCTL_RESET_SRC_PWR_ON ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_PIN_RESET (( AON_SYSCTL_RESETCTL_RESET_SRC_PIN_RESET ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_VDDS_LOSS (( AON_SYSCTL_RESETCTL_RESET_SRC_VDDS_LOSS ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_VDDR_LOSS (( AON_SYSCTL_RESETCTL_RESET_SRC_VDDR_LOSS ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_CLK_LOSS (( AON_SYSCTL_RESETCTL_RESET_SRC_CLK_LOSS ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_SYSRESET (( AON_SYSCTL_RESETCTL_RESET_SRC_SYSRESET ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_WARMRESET (( AON_SYSCTL_RESETCTL_RESET_SRC_WARMRESET ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_WAKEUP_FROM_SHUTDOWN ((( AON_SYSCTL_RESETCTL_RESET_SRC_M ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) + 1 ) +#define RSTSRC_PWR_ON ((AON_SYSCTL_RESETCTL_RESET_SRC_PWR_ON) >> (AON_SYSCTL_RESETCTL_RESET_SRC_S)) +#define RSTSRC_PIN_RESET ((AON_SYSCTL_RESETCTL_RESET_SRC_PIN_RESET) >> (AON_SYSCTL_RESETCTL_RESET_SRC_S)) +#define RSTSRC_VDDS_LOSS ((AON_SYSCTL_RESETCTL_RESET_SRC_VDDS_LOSS) >> (AON_SYSCTL_RESETCTL_RESET_SRC_S)) +#define RSTSRC_VDDR_LOSS ((AON_SYSCTL_RESETCTL_RESET_SRC_VDDR_LOSS) >> (AON_SYSCTL_RESETCTL_RESET_SRC_S)) +#define RSTSRC_CLK_LOSS ((AON_SYSCTL_RESETCTL_RESET_SRC_CLK_LOSS) >> (AON_SYSCTL_RESETCTL_RESET_SRC_S)) +#define RSTSRC_SYSRESET ((AON_SYSCTL_RESETCTL_RESET_SRC_SYSRESET) >> (AON_SYSCTL_RESETCTL_RESET_SRC_S)) +#define RSTSRC_WARMRESET ((AON_SYSCTL_RESETCTL_RESET_SRC_WARMRESET) >> (AON_SYSCTL_RESETCTL_RESET_SRC_S)) +#define RSTSRC_WAKEUP_FROM_SHUTDOWN (((AON_SYSCTL_RESETCTL_RESET_SRC_M) >> (AON_SYSCTL_RESETCTL_RESET_SRC_S)) + 1) //@} //***************************************************************************** @@ -306,7 +304,7 @@ extern void SysCtrl_DCDC_VoltageConditionalControl( void ); //! - \ref RSTSRC_WAKEUP_FROM_SHUTDOWN // //***************************************************************************** -extern uint32_t SysCtrlResetSourceGet( void ); +extern uint32_t SysCtrlResetSourceGet(void); //***************************************************************************** // @@ -316,15 +314,15 @@ extern uint32_t SysCtrlResetSourceGet( void ); // //***************************************************************************** __STATIC_INLINE void -SysCtrlSystemReset( void ) +SysCtrlSystemReset(void) { // Disable CPU interrupts CPUcpsid(); // Write reset register - HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL, AON_SYSCTL_RESETCTL_SYSRESET_BITN ) = 1; + HWREGBITW(AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL, AON_SYSCTL_RESETCTL_SYSRESET_BITN) = 1; // Finally, wait until the above write propagates - while ( 1 ) + while (1) { // Do nothing, just wait for the reset (and never return from here) } @@ -383,20 +381,20 @@ SysCtrlClockLossResetDisable(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_SysCtrlSetRechargeBeforePowerDown -#undef SysCtrlSetRechargeBeforePowerDown +#undef SysCtrlSetRechargeBeforePowerDown #define SysCtrlSetRechargeBeforePowerDown ROM_SysCtrlSetRechargeBeforePowerDown #endif #ifdef ROM_SysCtrlAdjustRechargeAfterPowerDown -#undef SysCtrlAdjustRechargeAfterPowerDown +#undef SysCtrlAdjustRechargeAfterPowerDown #define SysCtrlAdjustRechargeAfterPowerDown ROM_SysCtrlAdjustRechargeAfterPowerDown #endif #ifdef ROM_SysCtrl_DCDC_VoltageConditionalControl -#undef SysCtrl_DCDC_VoltageConditionalControl +#undef SysCtrl_DCDC_VoltageConditionalControl #define SysCtrl_DCDC_VoltageConditionalControl ROM_SysCtrl_DCDC_VoltageConditionalControl #endif #ifdef ROM_SysCtrlResetSourceGet -#undef SysCtrlResetSourceGet -#define SysCtrlResetSourceGet ROM_SysCtrlResetSourceGet +#undef SysCtrlResetSourceGet +#define SysCtrlResetSourceGet ROM_SysCtrlResetSourceGet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/systick.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/systick.h index d065440..c471218 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/systick.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/systick.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: systick.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Prototypes for the SysTick driver. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: systick.h + * Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) + * Revision: 49048 + * + * Description: Prototypes for the SysTick driver. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,17 +55,16 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include #include "../inc/hw_ints.h" #include "../inc/hw_nvic.h" #include "../inc/hw_types.h" #include "debug.h" #include "interrupt.h" +#include +#include //***************************************************************************** // diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/systick_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/systick_doc.h index 70848fc..0eaecd3 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/systick_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/systick_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: systick_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: systick_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup systick_api //! @{ //! \section sec_systick Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/timer.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/timer.h index b010b3b..4110801 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/timer.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/timer.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: timer.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: timer.h + * Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) + * Revision: 49048 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //**************************************************************************** // @@ -53,18 +53,17 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_gpt.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" +#include "interrupt.h" #include #include -#include "../inc/hw_ints.h" -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_gpt.h" -#include "interrupt.h" -#include "debug.h" //***************************************************************************** // @@ -80,14 +79,14 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define TimerConfigure NOROM_TimerConfigure -#define TimerLevelControl NOROM_TimerLevelControl -#define TimerStallControl NOROM_TimerStallControl -#define TimerWaitOnTriggerControl NOROM_TimerWaitOnTriggerControl -#define TimerIntRegister NOROM_TimerIntRegister -#define TimerIntUnregister NOROM_TimerIntUnregister -#define TimerMatchUpdateMode NOROM_TimerMatchUpdateMode -#define TimerIntervalLoadMode NOROM_TimerIntervalLoadMode +#define TimerConfigure NOROM_TimerConfigure +#define TimerLevelControl NOROM_TimerLevelControl +#define TimerStallControl NOROM_TimerStallControl +#define TimerWaitOnTriggerControl NOROM_TimerWaitOnTriggerControl +#define TimerIntRegister NOROM_TimerIntRegister +#define TimerIntUnregister NOROM_TimerIntUnregister +#define TimerMatchUpdateMode NOROM_TimerMatchUpdateMode +#define TimerIntervalLoadMode NOROM_TimerIntervalLoadMode #endif //***************************************************************************** @@ -95,29 +94,29 @@ extern "C" // Values that can be passed to TimerConfigure as the ui32Config parameter. // //***************************************************************************** -#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer -#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count timer -#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer -#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count timer -#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers -#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer -#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer -#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer -#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer -#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer -#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer -#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output +#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer +#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count timer +#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer +#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count timer +#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers +#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer +#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer +#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer +#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer +#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer +#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer +#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output //***************************************************************************** // @@ -126,25 +125,25 @@ extern "C" // TimerIntStatus. // //***************************************************************************** -#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt -#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt -#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt +#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt +#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt +#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt //***************************************************************************** // // Values that can be passed to TimerControlEvent as the ui32Event parameter. // //***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges //***************************************************************************** // @@ -152,39 +151,39 @@ extern "C" // parameter. // //***************************************************************************** -#define TIMER_A 0x000000FF // Timer A -#define TIMER_B 0x0000FF00 // Timer B -#define TIMER_BOTH 0x0000FFFF // Timer Both +#define TIMER_A 0x000000FF // Timer A +#define TIMER_B 0x0000FF00 // Timer B +#define TIMER_BOTH 0x0000FFFF // Timer Both //***************************************************************************** // // Values that can be passed to GPTSynchronize as the ui32Timers parameter // //***************************************************************************** -#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A -#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B -#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A -#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B -#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A -#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B -#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A -#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B +#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A +#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B +#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A +#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B +#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A +#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B +#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A +#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B //***************************************************************************** // // Values that can be passed to TimerMatchUpdateMode // //***************************************************************************** -#define TIMER_MATCHUPDATE_NEXTCYCLE 0x00000000 // Apply match register on next cycle -#define TIMER_MATCHUPDATE_TIMEOUT 0x00000001 // Apply match register on next timeout +#define TIMER_MATCHUPDATE_NEXTCYCLE 0x00000000 // Apply match register on next cycle +#define TIMER_MATCHUPDATE_TIMEOUT 0x00000001 // Apply match register on next timeout //***************************************************************************** // // Values that can be passed to TimerIntervalLoad // //***************************************************************************** -#define TIMER_INTERVALLOAD_NEXTCYCLE 0x00000000 // Load TxR register with the value in the TxILR register on the next clock cycle -#define TIMER_INTERVALLOAD_TIMEOUT 0x00000001 // Load TxR register with the value in the TxILR register on next timeout +#define TIMER_INTERVALLOAD_NEXTCYCLE 0x00000000 // Load TxR register with the value in the TxILR register on the next clock cycle +#define TIMER_INTERVALLOAD_TIMEOUT 0x00000001 // Load TxR register with the value in the TxILR register on next timeout //***************************************************************************** // @@ -522,8 +521,7 @@ TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer) (ui32Timer == TIMER_BOTH)); // Return the appropriate prescale value. - return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPR) : - HWREG(ui32Base + GPT_O_TBPR)); + return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPR) : HWREG(ui32Base + GPT_O_TBPR)); } //***************************************************************************** @@ -597,8 +595,7 @@ TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer) ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); // Return the appropriate prescale match value. - return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPMR) : - HWREG(ui32Base + GPT_O_TBPMR)); + return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPMR) : HWREG(ui32Base + GPT_O_TBPMR)); } //***************************************************************************** @@ -674,8 +671,7 @@ TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer) ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); // Return the appropriate load value. - return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAILR) : - HWREG(ui32Base + GPT_O_TBILR)); + return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAILR) : HWREG(ui32Base + GPT_O_TBILR)); } //***************************************************************************** @@ -706,8 +702,7 @@ TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer) ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); // Return the appropriate timer value. - return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAR) : - HWREG(ui32Base + GPT_O_TBR)); + return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAR) : HWREG(ui32Base + GPT_O_TBR)); } //***************************************************************************** @@ -786,8 +781,7 @@ TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer) ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); // Return the appropriate match value. - return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAMATCHR) : - HWREG(ui32Base + GPT_O_TBMATCHR)); + return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAMATCHR) : HWREG(ui32Base + GPT_O_TBMATCHR)); } //***************************************************************************** @@ -936,8 +930,7 @@ TimerIntStatus(uint32_t ui32Base, bool bMasked) // Return either the interrupt status or the raw interrupt status as // requested. - return (bMasked ? HWREG(ui32Base + GPT_O_MIS) : - HWREG(ui32Base + GPT_O_RIS)); + return (bMasked ? HWREG(ui32Base + GPT_O_MIS) : HWREG(ui32Base + GPT_O_RIS)); } //***************************************************************************** @@ -1123,36 +1116,36 @@ extern void TimerIntervalLoadMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_ #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_TimerConfigure -#undef TimerConfigure -#define TimerConfigure ROM_TimerConfigure +#undef TimerConfigure +#define TimerConfigure ROM_TimerConfigure #endif #ifdef ROM_TimerLevelControl -#undef TimerLevelControl -#define TimerLevelControl ROM_TimerLevelControl +#undef TimerLevelControl +#define TimerLevelControl ROM_TimerLevelControl #endif #ifdef ROM_TimerStallControl -#undef TimerStallControl -#define TimerStallControl ROM_TimerStallControl +#undef TimerStallControl +#define TimerStallControl ROM_TimerStallControl #endif #ifdef ROM_TimerWaitOnTriggerControl -#undef TimerWaitOnTriggerControl -#define TimerWaitOnTriggerControl ROM_TimerWaitOnTriggerControl +#undef TimerWaitOnTriggerControl +#define TimerWaitOnTriggerControl ROM_TimerWaitOnTriggerControl #endif #ifdef ROM_TimerIntRegister -#undef TimerIntRegister -#define TimerIntRegister ROM_TimerIntRegister +#undef TimerIntRegister +#define TimerIntRegister ROM_TimerIntRegister #endif #ifdef ROM_TimerIntUnregister -#undef TimerIntUnregister -#define TimerIntUnregister ROM_TimerIntUnregister +#undef TimerIntUnregister +#define TimerIntUnregister ROM_TimerIntUnregister #endif #ifdef ROM_TimerMatchUpdateMode -#undef TimerMatchUpdateMode -#define TimerMatchUpdateMode ROM_TimerMatchUpdateMode +#undef TimerMatchUpdateMode +#define TimerMatchUpdateMode ROM_TimerMatchUpdateMode #endif #ifdef ROM_TimerIntervalLoadMode -#undef TimerIntervalLoadMode -#define TimerIntervalLoadMode ROM_TimerIntervalLoadMode +#undef TimerIntervalLoadMode +#define TimerIntervalLoadMode ROM_TimerIntervalLoadMode #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/timer_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/timer_doc.h index d15c086..b9e9b91 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/timer_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/timer_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: timer_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: timer_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup timer_api //! @{ //! \section sec_timer Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/trng.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/trng.h index e3cfd1e..1723dc7 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/trng.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/trng.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: trng.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and prototypes for the true random number gen. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: trng.h + * Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) + * Revision: 49048 + * + * Description: Defines and prototypes for the true random number gen. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,19 +55,18 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_trng.h" -#include "../inc/hw_memmap.h" #include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_trng.h" +#include "../inc/hw_types.h" +#include "cpu.h" #include "debug.h" #include "interrupt.h" -#include "cpu.h" +#include +#include //***************************************************************************** // @@ -83,8 +82,8 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define TRNGConfigure NOROM_TRNGConfigure -#define TRNGNumberGet NOROM_TRNGNumberGet +#define TRNGConfigure NOROM_TRNGConfigure +#define TRNGNumberGet NOROM_TRNGNumberGet #endif //***************************************************************************** @@ -92,12 +91,12 @@ extern "C" // // //***************************************************************************** -#define TRNG_NUMBER_READY 0x00000001 // -#define TRNG_FRO_SHUTDOWN 0x00000002 // -#define TRNG_NEED_CLOCK 0x80000000 // +#define TRNG_NUMBER_READY 0x00000001 // +#define TRNG_FRO_SHUTDOWN 0x00000002 // +#define TRNG_NEED_CLOCK 0x80000000 // -#define TRNG_HI_WORD 0x00000001 -#define TRNG_LOW_WORD 0x00000002 +#define TRNG_HI_WORD 0x00000001 +#define TRNG_LOW_WORD 0x00000002 //***************************************************************************** // @@ -422,12 +421,12 @@ TRNGIntUnregister(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_TRNGConfigure -#undef TRNGConfigure -#define TRNGConfigure ROM_TRNGConfigure +#undef TRNGConfigure +#define TRNGConfigure ROM_TRNGConfigure #endif #ifdef ROM_TRNGNumberGet -#undef TRNGNumberGet -#define TRNGNumberGet ROM_TRNGNumberGet +#undef TRNGNumberGet +#define TRNGNumberGet ROM_TRNGNumberGet #endif #endif @@ -440,7 +439,7 @@ TRNGIntUnregister(void) } #endif -#endif // __TRNG_H__ +#endif // __TRNG_H__ //***************************************************************************** // diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/uart.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/uart.h index 05cd2eb..2212566 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/uart.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/uart.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: uart.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Defines and prototypes for the UART. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: uart.h + * Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) + * Revision: 49096 + * + * Description: Defines and prototypes for the UART. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,18 +55,17 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" #include "../inc/hw_types.h" #include "../inc/hw_uart.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "interrupt.h" #include "debug.h" +#include "interrupt.h" +#include +#include //***************************************************************************** // @@ -82,16 +81,16 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define UARTFIFOLevelGet NOROM_UARTFIFOLevelGet -#define UARTConfigSetExpClk NOROM_UARTConfigSetExpClk -#define UARTConfigGetExpClk NOROM_UARTConfigGetExpClk -#define UARTDisable NOROM_UARTDisable -#define UARTCharGetNonBlocking NOROM_UARTCharGetNonBlocking -#define UARTCharGet NOROM_UARTCharGet -#define UARTCharPutNonBlocking NOROM_UARTCharPutNonBlocking -#define UARTCharPut NOROM_UARTCharPut -#define UARTIntRegister NOROM_UARTIntRegister -#define UARTIntUnregister NOROM_UARTIntUnregister +#define UARTFIFOLevelGet NOROM_UARTFIFOLevelGet +#define UARTConfigSetExpClk NOROM_UARTConfigSetExpClk +#define UARTConfigGetExpClk NOROM_UARTConfigGetExpClk +#define UARTDisable NOROM_UARTDisable +#define UARTCharGetNonBlocking NOROM_UARTCharGetNonBlocking +#define UARTCharGet NOROM_UARTCharGet +#define UARTCharPutNonBlocking NOROM_UARTCharPutNonBlocking +#define UARTCharPut NOROM_UARTCharPut +#define UARTIntRegister NOROM_UARTIntRegister +#define UARTIntUnregister NOROM_UARTIntUnregister #endif //***************************************************************************** @@ -100,14 +99,14 @@ extern "C" // as the ui32IntFlags parameter, and returned from UARTIntStatus. // //***************************************************************************** -#define UART_INT_OE ( UART_IMSC_OEIM ) // Overrun Error Interrupt Mask -#define UART_INT_BE ( UART_IMSC_BEIM ) // Break Error Interrupt Mask -#define UART_INT_PE ( UART_IMSC_PEIM ) // Parity Error Interrupt Mask -#define UART_INT_FE ( UART_IMSC_FEIM ) // Framing Error Interrupt Mask -#define UART_INT_RT ( UART_IMSC_RTIM ) // Receive Timeout Interrupt Mask -#define UART_INT_TX ( UART_IMSC_TXIM ) // Transmit Interrupt Mask -#define UART_INT_RX ( UART_IMSC_RXIM ) // Receive Interrupt Mask -#define UART_INT_CTS ( UART_IMSC_CTSMIM ) // CTS Modem Interrupt Mask +#define UART_INT_OE (UART_IMSC_OEIM) // Overrun Error Interrupt Mask +#define UART_INT_BE (UART_IMSC_BEIM) // Break Error Interrupt Mask +#define UART_INT_PE (UART_IMSC_PEIM) // Parity Error Interrupt Mask +#define UART_INT_FE (UART_IMSC_FEIM) // Framing Error Interrupt Mask +#define UART_INT_RT (UART_IMSC_RTIM) // Receive Timeout Interrupt Mask +#define UART_INT_TX (UART_IMSC_TXIM) // Transmit Interrupt Mask +#define UART_INT_RX (UART_IMSC_RXIM) // Receive Interrupt Mask +#define UART_INT_CTS (UART_IMSC_CTSMIM) // CTS Modem Interrupt Mask //***************************************************************************** // @@ -118,20 +117,20 @@ extern "C" // UARTParityModeGet. // //***************************************************************************** -#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length -#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data -#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data -#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data -#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data -#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits -#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit -#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits -#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity -#define UART_CONFIG_PAR_NONE 0x00000000 // No parity -#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity -#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity -#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one -#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero +#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero //***************************************************************************** // @@ -139,11 +138,11 @@ extern "C" // and returned by UARTFIFOLevelGet in the pui32TxLevel. // //***************************************************************************** -#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full -#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full -#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full -#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full -#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full +#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full +#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full +#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full +#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full +#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full //***************************************************************************** // @@ -151,38 +150,38 @@ extern "C" // and returned by UARTFIFOLevelGet in the pui32RxLevel. // //***************************************************************************** -#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full -#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full -#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full -#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full -#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full +#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full +#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full +#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full +#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full +#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full //***************************************************************************** // // Values that can be passed to UARTDMAEnable() and UARTDMADisable(). // //***************************************************************************** -#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error -#define UART_DMA_TX 0x00000002 // Enable DMA for transmit -#define UART_DMA_RX 0x00000001 // Enable DMA for receive +#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error +#define UART_DMA_TX 0x00000002 // Enable DMA for transmit +#define UART_DMA_RX 0x00000001 // Enable DMA for receive //***************************************************************************** // // Values returned from UARTRxErrorGet(). // //***************************************************************************** -#define UART_RXERROR_OVERRUN 0x00000008 -#define UART_RXERROR_BREAK 0x00000004 -#define UART_RXERROR_PARITY 0x00000002 -#define UART_RXERROR_FRAMING 0x00000001 +#define UART_RXERROR_OVERRUN 0x00000008 +#define UART_RXERROR_BREAK 0x00000004 +#define UART_RXERROR_PARITY 0x00000002 +#define UART_RXERROR_FRAMING 0x00000001 //***************************************************************************** // // Values returned from the UARTBusy(). // //***************************************************************************** -#define UART_BUSY 0x00000001 -#define UART_IDLE 0x00000000 +#define UART_BUSY 0x00000001 +#define UART_IDLE 0x00000000 //***************************************************************************** // @@ -208,7 +207,7 @@ extern "C" static bool UARTBaseValid(uint32_t ui32Base) { - return (( ui32Base == UART0_BASE ) || ( ui32Base == UART0_NONBUF_BASE )); + return ((ui32Base == UART0_BASE) || (ui32Base == UART0_NONBUF_BASE)); } #endif @@ -246,7 +245,8 @@ UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity) // Set the parity mode. HWREG(ui32Base + UART_O_LCRH) = ((HWREG(ui32Base + UART_O_LCRH) & ~(UART_LCRH_SPS | UART_LCRH_EPS | - UART_LCRH_PEN)) | ui32Parity); + UART_LCRH_PEN)) | + ui32Parity); } //***************************************************************************** @@ -639,8 +639,7 @@ UARTBusy(uint32_t ui32Base) ASSERT(UARTBaseValid(ui32Base)); // Determine if the UART is busy. - return ((HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) ? - UART_BUSY : UART_IDLE); + return ((HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) ? UART_BUSY : UART_IDLE); } //***************************************************************************** @@ -666,9 +665,7 @@ UARTBreakCtl(uint32_t ui32Base, bool bBreakState) // Set the break condition as requested. HWREG(ui32Base + UART_O_LCRH) = - (bBreakState ? - (HWREG(ui32Base + UART_O_LCRH) | UART_LCRH_BRK) : - (HWREG(ui32Base + UART_O_LCRH) & ~(UART_LCRH_BRK))); + (bBreakState ? (HWREG(ui32Base + UART_O_LCRH) | UART_LCRH_BRK) : (HWREG(ui32Base + UART_O_LCRH) & ~(UART_LCRH_BRK))); } //***************************************************************************** @@ -992,12 +989,12 @@ UARTRxErrorClear(uint32_t ui32Base) // //***************************************************************************** __STATIC_INLINE void -UARTHwFlowControlEnable( uint32_t ui32Base ) +UARTHwFlowControlEnable(uint32_t ui32Base) { // Check the arguments. - ASSERT( UARTBaseValid( ui32Base )); + ASSERT(UARTBaseValid(ui32Base)); - HWREG( ui32Base + UART_O_CTL ) |= ( UART_CTL_CTSEN | UART_CTL_RTSEN ); + HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_CTSEN | UART_CTL_RTSEN); } //***************************************************************************** @@ -1012,15 +1009,14 @@ UARTHwFlowControlEnable( uint32_t ui32Base ) // //***************************************************************************** __STATIC_INLINE void -UARTHwFlowControlDisable( uint32_t ui32Base ) +UARTHwFlowControlDisable(uint32_t ui32Base) { // Check the arguments. - ASSERT( UARTBaseValid( ui32Base )); + ASSERT(UARTBaseValid(ui32Base)); - HWREG( ui32Base + UART_O_CTL ) &= ~( UART_CTL_CTSEN | UART_CTL_RTSEN ); + HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_CTSEN | UART_CTL_RTSEN); } - //***************************************************************************** // // Support for DriverLib in ROM: @@ -1030,44 +1026,44 @@ UARTHwFlowControlDisable( uint32_t ui32Base ) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_UARTFIFOLevelGet -#undef UARTFIFOLevelGet -#define UARTFIFOLevelGet ROM_UARTFIFOLevelGet +#undef UARTFIFOLevelGet +#define UARTFIFOLevelGet ROM_UARTFIFOLevelGet #endif #ifdef ROM_UARTConfigSetExpClk -#undef UARTConfigSetExpClk -#define UARTConfigSetExpClk ROM_UARTConfigSetExpClk +#undef UARTConfigSetExpClk +#define UARTConfigSetExpClk ROM_UARTConfigSetExpClk #endif #ifdef ROM_UARTConfigGetExpClk -#undef UARTConfigGetExpClk -#define UARTConfigGetExpClk ROM_UARTConfigGetExpClk +#undef UARTConfigGetExpClk +#define UARTConfigGetExpClk ROM_UARTConfigGetExpClk #endif #ifdef ROM_UARTDisable -#undef UARTDisable -#define UARTDisable ROM_UARTDisable +#undef UARTDisable +#define UARTDisable ROM_UARTDisable #endif #ifdef ROM_UARTCharGetNonBlocking -#undef UARTCharGetNonBlocking -#define UARTCharGetNonBlocking ROM_UARTCharGetNonBlocking +#undef UARTCharGetNonBlocking +#define UARTCharGetNonBlocking ROM_UARTCharGetNonBlocking #endif #ifdef ROM_UARTCharGet -#undef UARTCharGet -#define UARTCharGet ROM_UARTCharGet +#undef UARTCharGet +#define UARTCharGet ROM_UARTCharGet #endif #ifdef ROM_UARTCharPutNonBlocking -#undef UARTCharPutNonBlocking -#define UARTCharPutNonBlocking ROM_UARTCharPutNonBlocking +#undef UARTCharPutNonBlocking +#define UARTCharPutNonBlocking ROM_UARTCharPutNonBlocking #endif #ifdef ROM_UARTCharPut -#undef UARTCharPut -#define UARTCharPut ROM_UARTCharPut +#undef UARTCharPut +#define UARTCharPut ROM_UARTCharPut #endif #ifdef ROM_UARTIntRegister -#undef UARTIntRegister -#define UARTIntRegister ROM_UARTIntRegister +#undef UARTIntRegister +#define UARTIntRegister ROM_UARTIntRegister #endif #ifdef ROM_UARTIntUnregister -#undef UARTIntUnregister -#define UARTIntUnregister ROM_UARTIntUnregister +#undef UARTIntUnregister +#define UARTIntUnregister ROM_UARTIntUnregister #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/uart_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/uart_doc.h index ba77f94..21d1bf9 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/uart_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/uart_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: uart_doc.h -* Revised: 2018-02-09 15:45:36 +0100 (fr, 09 feb 2018) -* Revision: 51470 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: uart_doc.h + * Revised: 2018-02-09 15:45:36 +0100 (fr, 09 feb 2018) + * Revision: 51470 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ /*! \addtogroup uart_api @{ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/udma.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/udma.h index 0ac722a..be36838 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/udma.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/udma.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: udma.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and prototypes for the uDMA controller. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: udma.h + * Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) + * Revision: 49048 + * + * Description: Defines and prototypes for the uDMA controller. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,18 +55,17 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" #include "../inc/hw_ints.h" #include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "../inc/hw_udma.h" #include "debug.h" #include "interrupt.h" +#include +#include //***************************************************************************** // @@ -82,14 +81,14 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable -#define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable -#define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet -#define uDMAChannelControlSet NOROM_uDMAChannelControlSet -#define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet -#define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet -#define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet -#define uDMAChannelModeGet NOROM_uDMAChannelModeGet +#define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable +#define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable +#define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet +#define uDMAChannelControlSet NOROM_uDMAChannelControlSet +#define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet +#define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet +#define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet +#define uDMAChannelModeGet NOROM_uDMAChannelModeGet #endif //***************************************************************************** @@ -102,12 +101,11 @@ extern "C" //***************************************************************************** typedef struct { - volatile void* pvSrcEndAddr; //!< The ending source address of the data transfer. - volatile void* pvDstEndAddr; //!< The ending destination address of the data transfer. - volatile uint32_t ui32Control; //!< The channel control mode. - volatile uint32_t ui32Spare; //!< An unused location. -} -tDMAControlTable; + volatile void* pvSrcEndAddr; //!< The ending source address of the data transfer. + volatile void* pvDstEndAddr; //!< The ending destination address of the data transfer. + volatile uint32_t ui32Control; //!< The channel control mode. + volatile uint32_t ui32Spare; //!< An unused location. +} tDMAControlTable; //***************************************************************************** // @@ -177,42 +175,40 @@ tDMAControlTable; //! \return None (this is not a function) // //***************************************************************************** -#define uDMATaskStructEntry(ui32TransferCount, \ - ui32ItemSize, \ - ui32SrcIncrement, \ - pvSrcAddr, \ - ui32DstIncrement, \ - pvDstAddr, \ - ui32ArbSize, \ - ui32Mode) \ -{ \ - (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (pvSrcAddr) : \ - ((void *)(&((uint8_t *)(pvSrcAddr))[((ui32TransferCount) << \ - ((ui32SrcIncrement) >> 26)) - 1]))), \ - (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (pvDstAddr) : \ - ((void *)(&((uint8_t *)(pvDstAddr))[((ui32TransferCount) << \ - ((ui32DstIncrement) >> 30)) - 1]))), \ - (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \ - (ui32ArbSize) | (((ui32TransferCount) - 1) << 4) | \ - ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ - ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ - (ui32Mode) | UDMA_MODE_ALT_SELECT : (ui32Mode)), 0 \ -} +#define uDMATaskStructEntry(ui32TransferCount, \ + ui32ItemSize, \ + ui32SrcIncrement, \ + pvSrcAddr, \ + ui32DstIncrement, \ + pvDstAddr, \ + ui32ArbSize, \ + ui32Mode) \ + { \ + (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (pvSrcAddr) : ((void*)(&((uint8_t*)(pvSrcAddr))[((ui32TransferCount) << ((ui32SrcIncrement) >> 26)) - 1]))), \ + (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (pvDstAddr) : ((void*)(&((uint8_t*)(pvDstAddr))[((ui32TransferCount) << ((ui32DstIncrement) >> 30)) - 1]))), \ + (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \ + (ui32ArbSize) | (((ui32TransferCount) - 1) << 4) | \ + ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ + ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) \ + ? (ui32Mode) | UDMA_MODE_ALT_SELECT \ + : (ui32Mode)), \ + 0 \ + } //***************************************************************************** // // The hardware configured number of uDMA channels. // //***************************************************************************** -#define UDMA_NUM_CHANNELS 21 +#define UDMA_NUM_CHANNELS 21 //***************************************************************************** // // The level of priority for the uDMA channels // //***************************************************************************** -#define UDMA_PRIORITY_LOW 0x00000000 -#define UDMA_PRIORITY_HIGH 0x00000001 +#define UDMA_PRIORITY_LOW 0x00000000 +#define UDMA_PRIORITY_HIGH 0x00000001 //***************************************************************************** // @@ -220,11 +216,11 @@ tDMAControlTable; // uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). // //***************************************************************************** -#define UDMA_ATTR_USEBURST 0x00000001 -#define UDMA_ATTR_ALTSELECT 0x00000002 +#define UDMA_ATTR_USEBURST 0x00000001 +#define UDMA_ATTR_ALTSELECT 0x00000002 #define UDMA_ATTR_HIGH_PRIORITY 0x00000004 -#define UDMA_ATTR_REQMASK 0x00000008 -#define UDMA_ATTR_ALL 0x0000000F +#define UDMA_ATTR_REQMASK 0x00000008 +#define UDMA_ATTR_ALL 0x0000000F //***************************************************************************** // @@ -232,56 +228,56 @@ tDMAControlTable; // uDMAChannelModeGet(). // //***************************************************************************** -#define UDMA_MODE_STOP 0x00000000 -#define UDMA_MODE_BASIC 0x00000001 -#define UDMA_MODE_AUTO 0x00000002 -#define UDMA_MODE_PINGPONG 0x00000003 -#define UDMA_MODE_MEM_SCATTER_GATHER \ +#define UDMA_MODE_STOP 0x00000000 +#define UDMA_MODE_BASIC 0x00000001 +#define UDMA_MODE_AUTO 0x00000002 +#define UDMA_MODE_PINGPONG 0x00000003 +#define UDMA_MODE_MEM_SCATTER_GATHER \ 0x00000004 -#define UDMA_MODE_PER_SCATTER_GATHER \ +#define UDMA_MODE_PER_SCATTER_GATHER \ 0x00000006 -#define UDMA_MODE_M 0x00000007 // uDMA Transfer Mode -#define UDMA_MODE_ALT_SELECT 0x00000001 +#define UDMA_MODE_M 0x00000007 // uDMA Transfer Mode +#define UDMA_MODE_ALT_SELECT 0x00000001 //***************************************************************************** // // Channel configuration values that can be passed to uDMAControlSet(). // //***************************************************************************** -#define UDMA_DST_INC_8 0x00000000 -#define UDMA_DST_INC_16 0x40000000 -#define UDMA_DST_INC_32 0x80000000 -#define UDMA_DST_INC_NONE 0xC0000000 -#define UDMA_DST_INC_M 0xC0000000 // Destination Address Increment -#define UDMA_DST_INC_S 30 -#define UDMA_SRC_INC_8 0x00000000 -#define UDMA_SRC_INC_16 0x04000000 -#define UDMA_SRC_INC_32 0x08000000 -#define UDMA_SRC_INC_NONE 0x0c000000 -#define UDMA_SRC_INC_M 0x0C000000 // Source Address Increment -#define UDMA_SRC_INC_S 26 -#define UDMA_SIZE_8 0x00000000 -#define UDMA_SIZE_16 0x11000000 -#define UDMA_SIZE_32 0x22000000 -#define UDMA_SIZE_M 0x33000000 // Data Size -#define UDMA_SIZE_S 24 -#define UDMA_ARB_1 0x00000000 -#define UDMA_ARB_2 0x00004000 -#define UDMA_ARB_4 0x00008000 -#define UDMA_ARB_8 0x0000c000 -#define UDMA_ARB_16 0x00010000 -#define UDMA_ARB_32 0x00014000 -#define UDMA_ARB_64 0x00018000 -#define UDMA_ARB_128 0x0001c000 -#define UDMA_ARB_256 0x00020000 -#define UDMA_ARB_512 0x00024000 -#define UDMA_ARB_1024 0x00028000 -#define UDMA_ARB_M 0x0003C000 // Arbitration Size -#define UDMA_ARB_S 14 -#define UDMA_NEXT_USEBURST 0x00000008 -#define UDMA_XFER_SIZE_MAX 1024 -#define UDMA_XFER_SIZE_M 0x00003FF0 // Transfer size -#define UDMA_XFER_SIZE_S 4 +#define UDMA_DST_INC_8 0x00000000 +#define UDMA_DST_INC_16 0x40000000 +#define UDMA_DST_INC_32 0x80000000 +#define UDMA_DST_INC_NONE 0xC0000000 +#define UDMA_DST_INC_M 0xC0000000 // Destination Address Increment +#define UDMA_DST_INC_S 30 +#define UDMA_SRC_INC_8 0x00000000 +#define UDMA_SRC_INC_16 0x04000000 +#define UDMA_SRC_INC_32 0x08000000 +#define UDMA_SRC_INC_NONE 0x0c000000 +#define UDMA_SRC_INC_M 0x0C000000 // Source Address Increment +#define UDMA_SRC_INC_S 26 +#define UDMA_SIZE_8 0x00000000 +#define UDMA_SIZE_16 0x11000000 +#define UDMA_SIZE_32 0x22000000 +#define UDMA_SIZE_M 0x33000000 // Data Size +#define UDMA_SIZE_S 24 +#define UDMA_ARB_1 0x00000000 +#define UDMA_ARB_2 0x00004000 +#define UDMA_ARB_4 0x00008000 +#define UDMA_ARB_8 0x0000c000 +#define UDMA_ARB_16 0x00010000 +#define UDMA_ARB_32 0x00014000 +#define UDMA_ARB_64 0x00018000 +#define UDMA_ARB_128 0x0001c000 +#define UDMA_ARB_256 0x00020000 +#define UDMA_ARB_512 0x00024000 +#define UDMA_ARB_1024 0x00028000 +#define UDMA_ARB_M 0x0003C000 // Arbitration Size +#define UDMA_ARB_S 14 +#define UDMA_NEXT_USEBURST 0x00000008 +#define UDMA_XFER_SIZE_MAX 1024 +#define UDMA_XFER_SIZE_M 0x00003FF0 // Transfer size +#define UDMA_XFER_SIZE_S 4 //***************************************************************************** // @@ -289,25 +285,25 @@ tDMAControlTable; // ID. // //***************************************************************************** -#define UDMA_CHAN_SW_EVT0 0 // Software Event Channel 0 -#define UDMA_CHAN_UART0_RX 1 // UART0 RX Data -#define UDMA_CHAN_UART0_TX 2 // UART0 RX Data -#define UDMA_CHAN_SSI0_RX 3 // SSI0 RX Data -#define UDMA_CHAN_SSI0_TX 4 // SSI0 RX Data -#define UDMA_CHAN_AUX_ADC 7 // AUX ADC event -#define UDMA_CHAN_AUX_SW 8 // AUX Software event -#define UDMA_CHAN_TIMER0_A 9 // Timer0 A event -#define UDMA_CHAN_TIMER0_B 10 // Timer0 B event -#define UDMA_CHAN_TIMER1_A 11 -#define UDMA_CHAN_TIMER1_B 12 -#define UDMA_CHAN_AON_PROG2 13 -#define UDMA_CHAN_DMA_PROG 14 -#define UDMA_CHAN_AON_RTC 15 -#define UDMA_CHAN_SSI1_RX 16 -#define UDMA_CHAN_SSI1_TX 17 -#define UDMA_CHAN_SW_EVT1 18 -#define UDMA_CHAN_SW_EVT2 19 -#define UDMA_CHAN_SW_EVT3 20 +#define UDMA_CHAN_SW_EVT0 0 // Software Event Channel 0 +#define UDMA_CHAN_UART0_RX 1 // UART0 RX Data +#define UDMA_CHAN_UART0_TX 2 // UART0 RX Data +#define UDMA_CHAN_SSI0_RX 3 // SSI0 RX Data +#define UDMA_CHAN_SSI0_TX 4 // SSI0 RX Data +#define UDMA_CHAN_AUX_ADC 7 // AUX ADC event +#define UDMA_CHAN_AUX_SW 8 // AUX Software event +#define UDMA_CHAN_TIMER0_A 9 // Timer0 A event +#define UDMA_CHAN_TIMER0_B 10 // Timer0 B event +#define UDMA_CHAN_TIMER1_A 11 +#define UDMA_CHAN_TIMER1_B 12 +#define UDMA_CHAN_AON_PROG2 13 +#define UDMA_CHAN_DMA_PROG 14 +#define UDMA_CHAN_AON_RTC 15 +#define UDMA_CHAN_SSI1_RX 16 +#define UDMA_CHAN_SSI1_TX 17 +#define UDMA_CHAN_SW_EVT1 18 +#define UDMA_CHAN_SW_EVT2 19 +#define UDMA_CHAN_SW_EVT3 20 //***************************************************************************** // @@ -315,8 +311,8 @@ tDMAControlTable; // control structure should be used. // //***************************************************************************** -#define UDMA_PRI_SELECT 0x00000000 -#define UDMA_ALT_SELECT 0x00000020 +#define UDMA_PRI_SELECT 0x00000000 +#define UDMA_ALT_SELECT 0x00000020 //***************************************************************************** // @@ -514,8 +510,7 @@ uDMAChannelIsEnabled(uint32_t ui32Base, uint32_t ui32ChannelNum) // AND the specified channel bit with the enable register, and return the // result. - return ((HWREG(ui32Base + UDMA_O_SETCHANNELEN) & (1 << ui32ChannelNum)) ? - true : false); + return ((HWREG(ui32Base + UDMA_O_SETCHANNELEN) & (1 << ui32ChannelNum)) ? true : false); } //***************************************************************************** @@ -1150,8 +1145,7 @@ uDMAChannelPriorityGet(uint32_t ui32Base, uint32_t ui32ChannelNum) ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); // Return the channel priority. - return (HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum) ? - UDMA_PRIORITY_HIGH : UDMA_PRIORITY_LOW); + return (HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum) ? UDMA_PRIORITY_HIGH : UDMA_PRIORITY_LOW); } //***************************************************************************** @@ -1187,36 +1181,36 @@ uDMAChannelPriorityClear(uint32_t ui32Base, uint32_t ui32ChannelNum) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_uDMAChannelAttributeEnable -#undef uDMAChannelAttributeEnable -#define uDMAChannelAttributeEnable ROM_uDMAChannelAttributeEnable +#undef uDMAChannelAttributeEnable +#define uDMAChannelAttributeEnable ROM_uDMAChannelAttributeEnable #endif #ifdef ROM_uDMAChannelAttributeDisable -#undef uDMAChannelAttributeDisable -#define uDMAChannelAttributeDisable ROM_uDMAChannelAttributeDisable +#undef uDMAChannelAttributeDisable +#define uDMAChannelAttributeDisable ROM_uDMAChannelAttributeDisable #endif #ifdef ROM_uDMAChannelAttributeGet -#undef uDMAChannelAttributeGet -#define uDMAChannelAttributeGet ROM_uDMAChannelAttributeGet +#undef uDMAChannelAttributeGet +#define uDMAChannelAttributeGet ROM_uDMAChannelAttributeGet #endif #ifdef ROM_uDMAChannelControlSet -#undef uDMAChannelControlSet -#define uDMAChannelControlSet ROM_uDMAChannelControlSet +#undef uDMAChannelControlSet +#define uDMAChannelControlSet ROM_uDMAChannelControlSet #endif #ifdef ROM_uDMAChannelTransferSet -#undef uDMAChannelTransferSet -#define uDMAChannelTransferSet ROM_uDMAChannelTransferSet +#undef uDMAChannelTransferSet +#define uDMAChannelTransferSet ROM_uDMAChannelTransferSet #endif #ifdef ROM_uDMAChannelScatterGatherSet -#undef uDMAChannelScatterGatherSet -#define uDMAChannelScatterGatherSet ROM_uDMAChannelScatterGatherSet +#undef uDMAChannelScatterGatherSet +#define uDMAChannelScatterGatherSet ROM_uDMAChannelScatterGatherSet #endif #ifdef ROM_uDMAChannelSizeGet -#undef uDMAChannelSizeGet -#define uDMAChannelSizeGet ROM_uDMAChannelSizeGet +#undef uDMAChannelSizeGet +#define uDMAChannelSizeGet ROM_uDMAChannelSizeGet #endif #ifdef ROM_uDMAChannelModeGet -#undef uDMAChannelModeGet -#define uDMAChannelModeGet ROM_uDMAChannelModeGet +#undef uDMAChannelModeGet +#define uDMAChannelModeGet ROM_uDMAChannelModeGet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/vims.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/vims.h index ac48eaf..58a72ff 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/vims.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/vims.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: vims.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the VIMS. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: vims.h + * Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) + * Revision: 47343 + * + * Description: Defines and prototypes for the VIMS. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,16 +55,15 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" #include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "../inc/hw_vims.h" #include "debug.h" +#include +#include //***************************************************************************** // @@ -80,10 +79,10 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define VIMSConfigure NOROM_VIMSConfigure -#define VIMSModeSet NOROM_VIMSModeSet -#define VIMSModeGet NOROM_VIMSModeGet -#define VIMSModeSafeSet NOROM_VIMSModeSafeSet +#define VIMSConfigure NOROM_VIMSConfigure +#define VIMSModeSet NOROM_VIMSModeSet +#define VIMSModeGet NOROM_VIMSModeGet +#define VIMSModeSafeSet NOROM_VIMSModeSafeSet #endif //***************************************************************************** @@ -92,11 +91,11 @@ extern "C" // and returned from VIMSModeGet(). // //***************************************************************************** -#define VIMS_MODE_CHANGING 0x4 // VIMS mode is changing now and VIMS_MODE +#define VIMS_MODE_CHANGING 0x4 // VIMS mode is changing now and VIMS_MODE // can not be changed at moment. #define VIMS_MODE_DISABLED (VIMS_CTL_MODE_GPRAM) // Disabled mode (GPRAM enabled). -#define VIMS_MODE_ENABLED (VIMS_CTL_MODE_CACHE) // Enabled mode, only USERCODE is cached. -#define VIMS_MODE_OFF (VIMS_CTL_MODE_OFF) // VIMS Cache RAM is off +#define VIMS_MODE_ENABLED (VIMS_CTL_MODE_CACHE) // Enabled mode, only USERCODE is cached. +#define VIMS_MODE_OFF (VIMS_CTL_MODE_OFF) // VIMS Cache RAM is off //***************************************************************************** // @@ -277,9 +276,9 @@ extern uint32_t VIMSModeGet(uint32_t ui32Base); //! \sa \ref VIMSModeSet() and \ref VIMSModeGet() // //***************************************************************************** -extern void VIMSModeSafeSet( uint32_t ui32Base, - uint32_t ui32NewMode, - bool blocking ); +extern void VIMSModeSafeSet(uint32_t ui32Base, + uint32_t ui32NewMode, + bool blocking); //***************************************************************************** // @@ -334,20 +333,20 @@ VIMSLineBufEnable(uint32_t ui32Base) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_VIMSConfigure -#undef VIMSConfigure -#define VIMSConfigure ROM_VIMSConfigure +#undef VIMSConfigure +#define VIMSConfigure ROM_VIMSConfigure #endif #ifdef ROM_VIMSModeSet -#undef VIMSModeSet -#define VIMSModeSet ROM_VIMSModeSet +#undef VIMSModeSet +#define VIMSModeSet ROM_VIMSModeSet #endif #ifdef ROM_VIMSModeGet -#undef VIMSModeGet -#define VIMSModeGet ROM_VIMSModeGet +#undef VIMSModeGet +#define VIMSModeGet ROM_VIMSModeGet #endif #ifdef ROM_VIMSModeSafeSet -#undef VIMSModeSafeSet -#define VIMSModeSafeSet ROM_VIMSModeSafeSet +#undef VIMSModeSafeSet +#define VIMSModeSafeSet ROM_VIMSModeSafeSet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/watchdog.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/watchdog.h index a964eb3..3db6a6c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/watchdog.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/watchdog.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: wdt.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and prototypes for the Watchdog Timer. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: wdt.h + * Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) + * Revision: 49048 + * + * Description: Defines and prototypes for the Watchdog Timer. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,27 +55,26 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" #include "../inc/hw_ints.h" #include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "../inc/hw_wdt.h" #include "debug.h" #include "interrupt.h" +#include +#include //***************************************************************************** // // The following are defines for the bit fields in the WDT_O_LOCK register. // //***************************************************************************** -#define WATCHDOG_LOCK_UNLOCKED 0x00000000 // Unlocked -#define WATCHDOG_LOCK_LOCKED 0x00000001 // Locked -#define WATCHDOG_LOCK_UNLOCK 0x1ACCE551 // Unlocks the Watchdog Timer +#define WATCHDOG_LOCK_UNLOCKED 0x00000000 // Unlocked +#define WATCHDOG_LOCK_LOCKED 0x00000001 // Locked +#define WATCHDOG_LOCK_UNLOCK 0x1ACCE551 // Unlocks the Watchdog Timer //***************************************************************************** // @@ -83,15 +82,15 @@ extern "C" // WDT_MIS registers. // //***************************************************************************** -#define WATCHDOG_INT_TIMEOUT 0x00000001 // Watchdog timer expired +#define WATCHDOG_INT_TIMEOUT 0x00000001 // Watchdog timer expired //***************************************************************************** // // The type of interrupt that can be generated by the watchdog. // //***************************************************************************** -#define WATCHDOG_INT_TYPE_INT 0x00000000 -#define WATCHDOG_INT_TYPE_NMI 0x00000004 +#define WATCHDOG_INT_TYPE_INT 0x00000000 +#define WATCHDOG_INT_TYPE_NMI 0x00000004 //***************************************************************************** // @@ -231,8 +230,7 @@ __STATIC_INLINE bool WatchdogLockState(void) { // Get the lock state. - return ((HWREG(WDT_BASE + WDT_O_LOCK) == WATCHDOG_LOCK_LOCKED) ? - true : false); + return ((HWREG(WDT_BASE + WDT_O_LOCK) == WATCHDOG_LOCK_LOCKED) ? true : false); } //***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/watchdog_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/watchdog_doc.h index 877bab7..552cd74 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/watchdog_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/driverlib/watchdog_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: watchdog_doc.h -* Revised: 2018-02-09 15:45:36 +0100 (Fri, 09 Feb 2018) -* Revision: 51470 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: watchdog_doc.h + * Revised: 2018-02-09 15:45:36 +0100 (Fri, 09 Feb 2018) + * Revision: 51470 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup wdt_api //! @{ //! \section sec_wdt Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/asmdefs.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/asmdefs.h index ddb5315..1d02ca8 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/asmdefs.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/asmdefs.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: asmdefs.h -* Revised: 2015-06-05 14:39:10 +0200 (Fri, 05 Jun 2015) -* Revision: 43803 -* -* Description: Macros to allow assembly code be portable among tool chains. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: asmdefs.h + * Revised: 2015-06-05 14:39:10 +0200 (Fri, 05 Jun 2015) + * Revision: 43803 + * + * Description: Macros to allow assembly code be portable among tool chains. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __ASMDEFS_H__ #define __ASMDEFS_H__ @@ -46,27 +46,27 @@ //***************************************************************************** #ifdef __IAR_SYSTEMS_ICC__ - // - // Section headers. - // - #define __LIBRARY__ module - #define __TEXT__ rseg CODE:CODE(2) - #define __DATA__ rseg DATA:DATA(2) - #define __BSS__ rseg DATA:DATA(2) - #define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) +// +// Section headers. +// +#define __LIBRARY__ module +#define __TEXT__ rseg CODE : CODE(2) +#define __DATA__ rseg DATA : DATA(2) +#define __BSS__ rseg DATA : DATA(2) +#define __TEXT_NOROOT__ rseg CODE : CODE : NOROOT(2) - // - // Assembler mnemonics. - // - #define __ALIGN__ alignrom 2 - #define __END__ end - #define __EXPORT__ export - #define __IMPORT__ import - #define __LABEL__ - #define __STR__ dcb - #define __THUMB_LABEL__ thumb - #define __WORD__ dcd - #define __INLINE_DATA__ data +// +// Assembler mnemonics. +// +#define __ALIGN__ alignrom 2 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ thumb +#define __WORD__ dcd +#define __INLINE_DATA__ data #endif // __IAR_SYSTEMS_ICC__ @@ -77,34 +77,34 @@ //***************************************************************************** #if defined(__GNUC__) - // - // The assembly code preamble required to put the assembler into the correct - // configuration. - // - .syntax unified +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// +.syntax unified .thumb - // - // Section headers. - // - #define __LIBRARY__ @ - #define __TEXT__ .text - #define __DATA__ .data - #define __BSS__ .bss - #define __TEXT_NOROOT__ .text +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text - // - // Assembler mnemonics. - // - #define __ALIGN__ .balign 4 - #define __END__ .end - #define __EXPORT__ .globl - #define __IMPORT__ .extern - #define __LABEL__ : - #define __STR__ .ascii - #define __THUMB_LABEL__ .thumb_func - #define __WORD__ .word - #define __INLINE_DATA__ +// +// Assembler mnemonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ #endif // __GNUC__ @@ -115,37 +115,35 @@ //***************************************************************************** #if defined(__CC_ARM) - // - // The assembly code preamble required to put the assembler into the correct - // configuration. - // - thumb - require8 - preserve8 + // + // The assembly code preamble required to put the assembler into the correct + // configuration. + // + thumb + require8 preserve8 - // - // Section headers. - // - #define __LIBRARY__ ; - #define __TEXT__ area ||.text||, code, readonly, align=2 - #define __DATA__ area ||.data||, data, align=2 - #define __BSS__ area ||.bss||, noinit, align=2 - #define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 +// +// Section headers. +// +#define __LIBRARY__ ; +#define __TEXT__ area ||.text ||, code, readonly, align = 2 +#define __DATA__ area ||.data ||, data, align = 2 +#define __BSS__ area ||.bss ||, noinit, align = 2 +#define __TEXT_NOROOT__ area ||.text ||, code, readonly, align = 2 - // - // Assembler mnemonics. - // - #define __ALIGN__ align 4 - #define __END__ end - #define __EXPORT__ export - #define __IMPORT__ import - #define __LABEL__ - #define __STR__ dcb - #define __THUMB_LABEL__ - #define __WORD__ dcd - #define __INLINE_DATA__ +// +// Assembler mnemonics. +// +#define __ALIGN__ align 4 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ +#define __WORD__ dcd +#define __INLINE_DATA__ #endif // __CC_ARM - #endif // __ASMDEF_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi.h index 7e7b603..692d892 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_adi.h -* Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) -* Revision: 42365 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_adi.h + * Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) + * Revision: 42365 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_ADI_H__ #define __HW_ADI_H__ @@ -154,21 +154,21 @@ // The following are defines for the ADI master instruction offsets. // //***************************************************************************** -#define ADI_O_DIR 0x00000000 // Offset for the direct access +#define ADI_O_DIR 0x00000000 // Offset for the direct access // instruction -#define ADI_O_SET 0x00000010 // Offset for 'Set' instruction. -#define ADI_O_CLR 0x00000020 // Offset for 'Clear' instruction. -#define ADI_O_MASK4B 0x00000040 // Offset for 4-bit masked access. +#define ADI_O_SET 0x00000010 // Offset for 'Set' instruction. +#define ADI_O_CLR 0x00000020 // Offset for 'Clear' instruction. +#define ADI_O_MASK4B 0x00000040 // Offset for 4-bit masked access. // Data bit[n] is written if mask // bit[n] is set ('1'). // Bits 7:4 are mask. Bits 3:0 are data. // Requires 'byte' write. -#define ADI_O_MASK8B 0x00000060 // Offset for 8-bit masked access. +#define ADI_O_MASK8B 0x00000060 // Offset for 8-bit masked access. // Data bit[n] is written if mask // bit[n] is set ('1'). Bits 15:8 are // mask. Bits 7:0 are data. Requires // 'short' write. -#define ADI_O_MASK16B 0x00000080 // Offset for 16-bit masked access. +#define ADI_O_MASK16B 0x00000080 // Offset for 16-bit masked access. // Data bit[n] is written if mask // bit[n] is set ('1'). Bits 31:16 // are mask. Bits 15:0 are data. @@ -179,8 +179,8 @@ // The following are defines for the ADI register offsets. // //***************************************************************************** -#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register -#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration +#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register +#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration //***************************************************************************** // @@ -188,26 +188,26 @@ // ADI_O_SLAVESTAT register. // //***************************************************************************** -#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ +#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ // signal. Writing 0 to this bit // forces a sync with slave, // ensuring that req will be 0. It // is recommended to write 0 to // this register before power down // of the master. -#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 -#define ADI_SLAVESTAT_DI_REQ_S 1 -#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK +#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 +#define ADI_SLAVESTAT_DI_REQ_S 1 +#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK // signal -#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 -#define ADI_SLAVESTAT_DI_ACK_S 0 +#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 +#define ADI_SLAVESTAT_DI_ACK_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_SLAVECONF register. // //***************************************************************************** -#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer +#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer // accessible when this bit is set. // (unless sticky_bit_overwrite is // asserted on top module) @@ -215,7 +215,7 @@ 0x00000080 #define ADI_SLAVECONF_CONFLOCK_S 7 #define ADI_SLAVECONF_WAITFORACK \ - 0x00000004 // A transaction on the ADI + 0x00000004 // A transaction on the ADI // interface does not end until ack // has been received from the slave // when this bit is set. @@ -224,7 +224,7 @@ 0x00000004 #define ADI_SLAVECONF_WAITFORACK_S 2 #define ADI_SLAVECONF_ADICLKSPEED_M \ - 0x00000003 // Sets the period of an ADI + 0x00000003 // Sets the period of an ADI // transactions. All transactions // takes an even number of clock // cycles,- ADI clock rising edge @@ -250,103 +250,103 @@ // to not use these. // //***************************************************************************** -#define ADI_O_DIR03 0x00000000 // Direct access for adi byte +#define ADI_O_DIR03 0x00000000 // Direct access for adi byte // offsets 0 to 3 -#define ADI_O_DIR47 0x00000004 // Direct access for adi byte +#define ADI_O_DIR47 0x00000004 // Direct access for adi byte // offsets 4 to 7 -#define ADI_O_DIR811 0x00000008 // Direct access for adi byte +#define ADI_O_DIR811 0x00000008 // Direct access for adi byte // offsets 8 to 11 -#define ADI_O_DIR1215 0x0000000C // Direct access for adi byte +#define ADI_O_DIR1215 0x0000000C // Direct access for adi byte // offsets 12 to 15 -#define ADI_O_SET03 0x00000010 // Set register for ADI byte +#define ADI_O_SET03 0x00000010 // Set register for ADI byte // offsets 0 to 3 -#define ADI_O_SET47 0x00000014 // Set register for ADI byte +#define ADI_O_SET47 0x00000014 // Set register for ADI byte // offsets 4 to 7 -#define ADI_O_SET811 0x00000018 // Set register for ADI byte +#define ADI_O_SET811 0x00000018 // Set register for ADI byte // offsets 8 to 11 -#define ADI_O_SET1215 0x0000001C // Set register for ADI byte +#define ADI_O_SET1215 0x0000001C // Set register for ADI byte // offsets 12 to 15 -#define ADI_O_CLR03 0x00000020 // Clear register for ADI byte +#define ADI_O_CLR03 0x00000020 // Clear register for ADI byte // offsets 0 to 3 -#define ADI_O_CLR47 0x00000024 // Clear register for ADI byte +#define ADI_O_CLR47 0x00000024 // Clear register for ADI byte // offsets 4 to 7 -#define ADI_O_CLR811 0x00000028 // Clear register for ADI byte +#define ADI_O_CLR811 0x00000028 // Clear register for ADI byte // offsets 8 to 11 -#define ADI_O_CLR1215 0x0000002C // Clear register for ADI byte +#define ADI_O_CLR1215 0x0000002C // Clear register for ADI byte // offsets 12 to 15 -#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register -#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration +#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register +#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration // register -#define ADI_O_MASK4B01 0x00000040 // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B01 0x00000040 // Masked access (4m/4d) for ADI // Registers at byte offsets 0 and // 1 -#define ADI_O_MASK4B23 0x00000044 // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B23 0x00000044 // Masked access (4m/4d) for ADI // Registers at byte offsets 2 and // 3 -#define ADI_O_MASK4B45 0x00000048 // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B45 0x00000048 // Masked access (4m/4d) for ADI // Registers at byte offsets 4 and // 5 -#define ADI_O_MASK4B67 0x0000004C // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B67 0x0000004C // Masked access (4m/4d) for ADI // Registers at byte offsets 6 and // 7 -#define ADI_O_MASK4B89 0x00000050 // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B89 0x00000050 // Masked access (4m/4d) for ADI // Registers at byte offsets 8 and // 9 -#define ADI_O_MASK4B1011 0x00000054 // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B1011 0x00000054 // Masked access (4m/4d) for ADI // Registers at byte offsets 10 and // 11 -#define ADI_O_MASK4B1213 0x00000058 // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B1213 0x00000058 // Masked access (4m/4d) for ADI // Registers at byte offsets 12 and // 13 -#define ADI_O_MASK4B1415 0x0000005C // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B1415 0x0000005C // Masked access (4m/4d) for ADI // Registers at byte offsets 14 and // 15 -#define ADI_O_MASK8B01 0x00000060 // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B01 0x00000060 // Masked access (8m/8d) for ADI // Registers at byte offsets 0 and // 1 -#define ADI_O_MASK8B23 0x00000064 // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B23 0x00000064 // Masked access (8m/8d) for ADI // Registers at byte offsets 2 and // 3 -#define ADI_O_MASK8B45 0x00000068 // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B45 0x00000068 // Masked access (8m/8d) for ADI // Registers at byte offsets 4 and // 5 -#define ADI_O_MASK8B67 0x0000006C // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B67 0x0000006C // Masked access (8m/8d) for ADI // Registers at byte offsets 6 and // 7 -#define ADI_O_MASK8B89 0x00000070 // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B89 0x00000070 // Masked access (8m/8d) for ADI // Registers at byte offsets 8 and // 9 -#define ADI_O_MASK8B1011 0x00000074 // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B1011 0x00000074 // Masked access (8m/8d) for ADI // Registers at byte offsets 10 and // 11 -#define ADI_O_MASK8B1213 0x00000078 // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B1213 0x00000078 // Masked access (8m/8d) for ADI // Registers at byte offsets 12 and // 13 -#define ADI_O_MASK8B1415 0x0000007C // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B1415 0x0000007C // Masked access (8m/8d) for ADI // Registers at byte offsets 14 and // 15 -#define ADI_O_MASK16B01 0x00000080 // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B01 0x00000080 // Masked access (16m/16d) for ADI // Registers at byte offsets 0 and // 1 -#define ADI_O_MASK16B23 0x00000084 // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B23 0x00000084 // Masked access (16m/16d) for ADI // Registers at byte offsets 2 and // 3 -#define ADI_O_MASK16B45 0x00000088 // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B45 0x00000088 // Masked access (16m/16d) for ADI // Registers at byte offsets 4 and // 5 -#define ADI_O_MASK16B67 0x0000008C // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B67 0x0000008C // Masked access (16m/16d) for ADI // Registers at byte offsets 6 and // 7 -#define ADI_O_MASK16B89 0x00000090 // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B89 0x00000090 // Masked access (16m/16d) for ADI // Registers at byte offsets 8 and // 9 -#define ADI_O_MASK16B1011 0x00000094 // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B1011 0x00000094 // Masked access (16m/16d) for ADI // Registers at byte offsets 10 and // 11 -#define ADI_O_MASK16B1213 0x00000098 // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B1213 0x00000098 // Masked access (16m/16d) for ADI // Registers at byte offsets 12 and // 13 -#define ADI_O_MASK16B1415 0x0000009C // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B1415 0x0000009C // Masked access (16m/16d) for ADI // Registers at byte offsets 14 and // 15 @@ -355,253 +355,253 @@ // The following are defines for the bit fields in the ADI_O_DIR03 register. // //***************************************************************************** -#define ADI_DIR03_B3_M 0xFF000000 // Direct access to ADI register 3 -#define ADI_DIR03_B3_S 24 -#define ADI_DIR03_B2_M 0x00FF0000 // Direct access to ADI register 2 -#define ADI_DIR03_B2_S 16 -#define ADI_DIR03_B1_M 0x0000FF00 // Direct access to ADI register 1 -#define ADI_DIR03_B1_S 8 -#define ADI_DIR03_B0_M 0x000000FF // Direct access to ADI register 0 -#define ADI_DIR03_B0_S 0 +#define ADI_DIR03_B3_M 0xFF000000 // Direct access to ADI register 3 +#define ADI_DIR03_B3_S 24 +#define ADI_DIR03_B2_M 0x00FF0000 // Direct access to ADI register 2 +#define ADI_DIR03_B2_S 16 +#define ADI_DIR03_B1_M 0x0000FF00 // Direct access to ADI register 1 +#define ADI_DIR03_B1_S 8 +#define ADI_DIR03_B0_M 0x000000FF // Direct access to ADI register 0 +#define ADI_DIR03_B0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_DIR47 register. // //***************************************************************************** -#define ADI_DIR47_B3_M 0xFF000000 // Direct access to ADI register 7 -#define ADI_DIR47_B3_S 24 -#define ADI_DIR47_B2_M 0x00FF0000 // Direct access to ADI register 6 -#define ADI_DIR47_B2_S 16 -#define ADI_DIR47_B1_M 0x0000FF00 // Direct access to ADI register 5 -#define ADI_DIR47_B1_S 8 -#define ADI_DIR47_B0_M 0x000000FF // Direct access to ADI register 4 -#define ADI_DIR47_B0_S 0 +#define ADI_DIR47_B3_M 0xFF000000 // Direct access to ADI register 7 +#define ADI_DIR47_B3_S 24 +#define ADI_DIR47_B2_M 0x00FF0000 // Direct access to ADI register 6 +#define ADI_DIR47_B2_S 16 +#define ADI_DIR47_B1_M 0x0000FF00 // Direct access to ADI register 5 +#define ADI_DIR47_B1_S 8 +#define ADI_DIR47_B0_M 0x000000FF // Direct access to ADI register 4 +#define ADI_DIR47_B0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_DIR811 register. // //***************************************************************************** -#define ADI_DIR811_B3_M 0xFF000000 // Direct access to ADI register +#define ADI_DIR811_B3_M 0xFF000000 // Direct access to ADI register // 11 -#define ADI_DIR811_B3_S 24 -#define ADI_DIR811_B2_M 0x00FF0000 // Direct access to ADI register +#define ADI_DIR811_B3_S 24 +#define ADI_DIR811_B2_M 0x00FF0000 // Direct access to ADI register // 10 -#define ADI_DIR811_B2_S 16 -#define ADI_DIR811_B1_M 0x0000FF00 // Direct access to ADI register 9 -#define ADI_DIR811_B1_S 8 -#define ADI_DIR811_B0_M 0x000000FF // Direct access to ADI register 8 -#define ADI_DIR811_B0_S 0 +#define ADI_DIR811_B2_S 16 +#define ADI_DIR811_B1_M 0x0000FF00 // Direct access to ADI register 9 +#define ADI_DIR811_B1_S 8 +#define ADI_DIR811_B0_M 0x000000FF // Direct access to ADI register 8 +#define ADI_DIR811_B0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_DIR1215 register. // //***************************************************************************** -#define ADI_DIR1215_B3_M 0xFF000000 // Direct access to ADI register +#define ADI_DIR1215_B3_M 0xFF000000 // Direct access to ADI register // 15 -#define ADI_DIR1215_B3_S 24 -#define ADI_DIR1215_B2_M 0x00FF0000 // Direct access to ADI register +#define ADI_DIR1215_B3_S 24 +#define ADI_DIR1215_B2_M 0x00FF0000 // Direct access to ADI register // 14 -#define ADI_DIR1215_B2_S 16 -#define ADI_DIR1215_B1_M 0x0000FF00 // Direct access to ADI register +#define ADI_DIR1215_B2_S 16 +#define ADI_DIR1215_B1_M 0x0000FF00 // Direct access to ADI register // 13 -#define ADI_DIR1215_B1_S 8 -#define ADI_DIR1215_B0_M 0x000000FF // Direct access to ADI register +#define ADI_DIR1215_B1_S 8 +#define ADI_DIR1215_B0_M 0x000000FF // Direct access to ADI register // 12 -#define ADI_DIR1215_B0_S 0 +#define ADI_DIR1215_B0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_SET03 register. // //***************************************************************************** -#define ADI_SET03_S3_M 0xFF000000 // A high bit value will set the +#define ADI_SET03_S3_M 0xFF000000 // A high bit value will set the // corresponding bit in ADI // register 3. Read returns 0. -#define ADI_SET03_S3_S 24 -#define ADI_SET03_S2_M 0x00FF0000 // A high bit value will set the +#define ADI_SET03_S3_S 24 +#define ADI_SET03_S2_M 0x00FF0000 // A high bit value will set the // corresponding bit in ADI // register 2. Read returns 0. -#define ADI_SET03_S2_S 16 -#define ADI_SET03_S1_M 0x0000FF00 // A high bit value will set the +#define ADI_SET03_S2_S 16 +#define ADI_SET03_S1_M 0x0000FF00 // A high bit value will set the // corresponding bit in ADI // register 1. Read returns 0. -#define ADI_SET03_S1_S 8 -#define ADI_SET03_S0_M 0x000000FF // A high bit value will set the +#define ADI_SET03_S1_S 8 +#define ADI_SET03_S0_M 0x000000FF // A high bit value will set the // corresponding bit in ADI // register 0. Read returns 0. -#define ADI_SET03_S0_S 0 +#define ADI_SET03_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_SET47 register. // //***************************************************************************** -#define ADI_SET47_S3_M 0xFF000000 // A high bit value will set the +#define ADI_SET47_S3_M 0xFF000000 // A high bit value will set the // corresponding bit in ADI // register 7. Read returns 0. -#define ADI_SET47_S3_S 24 -#define ADI_SET47_S2_M 0x00FF0000 // A high bit value will set the +#define ADI_SET47_S3_S 24 +#define ADI_SET47_S2_M 0x00FF0000 // A high bit value will set the // corresponding bit in ADI // register 6. Read returns 0. -#define ADI_SET47_S2_S 16 -#define ADI_SET47_S1_M 0x0000FF00 // A high bit value will set the +#define ADI_SET47_S2_S 16 +#define ADI_SET47_S1_M 0x0000FF00 // A high bit value will set the // corresponding bit in ADI // register 5. Read returns 0. -#define ADI_SET47_S1_S 8 -#define ADI_SET47_S0_M 0x000000FF // A high bit value will set the +#define ADI_SET47_S1_S 8 +#define ADI_SET47_S0_M 0x000000FF // A high bit value will set the // corresponding bit in ADI // register 4. Read returns 0. -#define ADI_SET47_S0_S 0 +#define ADI_SET47_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_SET811 register. // //***************************************************************************** -#define ADI_SET811_S3_M 0xFF000000 // A high bit value will set the +#define ADI_SET811_S3_M 0xFF000000 // A high bit value will set the // corresponding bit in ADI // register 11. Read returns 0. -#define ADI_SET811_S3_S 24 -#define ADI_SET811_S2_M 0x00FF0000 // A high bit value will set the +#define ADI_SET811_S3_S 24 +#define ADI_SET811_S2_M 0x00FF0000 // A high bit value will set the // corresponding bit in ADI // register 10. Read returns 0. -#define ADI_SET811_S2_S 16 -#define ADI_SET811_S1_M 0x0000FF00 // A high bit value will set the +#define ADI_SET811_S2_S 16 +#define ADI_SET811_S1_M 0x0000FF00 // A high bit value will set the // corresponding bit in ADI // register 9. Read returns 0. -#define ADI_SET811_S1_S 8 -#define ADI_SET811_S0_M 0x000000FF // A high bit value will set the +#define ADI_SET811_S1_S 8 +#define ADI_SET811_S0_M 0x000000FF // A high bit value will set the // corresponding bit in ADI // register 8. Read returns 0. -#define ADI_SET811_S0_S 0 +#define ADI_SET811_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_SET1215 register. // //***************************************************************************** -#define ADI_SET1215_S3_M 0xFF000000 // A high bit value will set the +#define ADI_SET1215_S3_M 0xFF000000 // A high bit value will set the // corresponding bit in ADI // register 15. Read returns 0. -#define ADI_SET1215_S3_S 24 -#define ADI_SET1215_S2_M 0x00FF0000 // A high bit value will set the +#define ADI_SET1215_S3_S 24 +#define ADI_SET1215_S2_M 0x00FF0000 // A high bit value will set the // corresponding bit in ADI // register 14. Read returns 0. -#define ADI_SET1215_S2_S 16 -#define ADI_SET1215_S1_M 0x0000FF00 // A high bit value will set the +#define ADI_SET1215_S2_S 16 +#define ADI_SET1215_S1_M 0x0000FF00 // A high bit value will set the // corresponding bit in ADI // register 13. Read returns 0. -#define ADI_SET1215_S1_S 8 -#define ADI_SET1215_S0_M 0x000000FF // A high bit value will set the +#define ADI_SET1215_S1_S 8 +#define ADI_SET1215_S0_M 0x000000FF // A high bit value will set the // corresponding bit in ADI // register 12. Read returns 0. -#define ADI_SET1215_S0_S 0 +#define ADI_SET1215_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_CLR03 register. // //***************************************************************************** -#define ADI_CLR03_S3_M 0xFF000000 // A high bit value will clear the +#define ADI_CLR03_S3_M 0xFF000000 // A high bit value will clear the // corresponding bit in ADI // register 3 -#define ADI_CLR03_S3_S 24 -#define ADI_CLR03_S2_M 0x00FF0000 // A high bit value will clear the +#define ADI_CLR03_S3_S 24 +#define ADI_CLR03_S2_M 0x00FF0000 // A high bit value will clear the // corresponding bit in ADI // register 2 -#define ADI_CLR03_S2_S 16 -#define ADI_CLR03_S1_M 0x0000FF00 // A high bit value will clear the +#define ADI_CLR03_S2_S 16 +#define ADI_CLR03_S1_M 0x0000FF00 // A high bit value will clear the // corresponding bit in ADI // register 1 -#define ADI_CLR03_S1_S 8 -#define ADI_CLR03_S0_M 0x000000FF // A high bit value will clear the +#define ADI_CLR03_S1_S 8 +#define ADI_CLR03_S0_M 0x000000FF // A high bit value will clear the // corresponding bit in ADI // register 0 -#define ADI_CLR03_S0_S 0 +#define ADI_CLR03_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_CLR47 register. // //***************************************************************************** -#define ADI_CLR47_S3_M 0xFF000000 // A high bit value will clear the +#define ADI_CLR47_S3_M 0xFF000000 // A high bit value will clear the // corresponding bit in ADI // register 7 -#define ADI_CLR47_S3_S 24 -#define ADI_CLR47_S2_M 0x00FF0000 // A high bit value will clear the +#define ADI_CLR47_S3_S 24 +#define ADI_CLR47_S2_M 0x00FF0000 // A high bit value will clear the // corresponding bit in ADI // register 6 -#define ADI_CLR47_S2_S 16 -#define ADI_CLR47_S1_M 0x0000FF00 // A high bit value will clear the +#define ADI_CLR47_S2_S 16 +#define ADI_CLR47_S1_M 0x0000FF00 // A high bit value will clear the // corresponding bit in ADI // register 5 -#define ADI_CLR47_S1_S 8 -#define ADI_CLR47_S0_M 0x000000FF // A high bit value will clear the +#define ADI_CLR47_S1_S 8 +#define ADI_CLR47_S0_M 0x000000FF // A high bit value will clear the // corresponding bit in ADI // register 4 -#define ADI_CLR47_S0_S 0 +#define ADI_CLR47_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_CLR811 register. // //***************************************************************************** -#define ADI_CLR811_S3_M 0xFF000000 // A high bit value will clear the +#define ADI_CLR811_S3_M 0xFF000000 // A high bit value will clear the // corresponding bit in ADI // register 11 -#define ADI_CLR811_S3_S 24 -#define ADI_CLR811_S2_M 0x00FF0000 // A high bit value will clear the +#define ADI_CLR811_S3_S 24 +#define ADI_CLR811_S2_M 0x00FF0000 // A high bit value will clear the // corresponding bit in ADI // register 10 -#define ADI_CLR811_S2_S 16 -#define ADI_CLR811_S1_M 0x0000FF00 // A high bit value will clear the +#define ADI_CLR811_S2_S 16 +#define ADI_CLR811_S1_M 0x0000FF00 // A high bit value will clear the // corresponding bit in ADI // register 9 -#define ADI_CLR811_S1_S 8 -#define ADI_CLR811_S0_M 0x000000FF // A high bit value will clear the +#define ADI_CLR811_S1_S 8 +#define ADI_CLR811_S0_M 0x000000FF // A high bit value will clear the // corresponding bit in ADI // register 8 -#define ADI_CLR811_S0_S 0 +#define ADI_CLR811_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_CLR1215 register. // //***************************************************************************** -#define ADI_CLR1215_S3_M 0xFF000000 // A high bit value will clear the +#define ADI_CLR1215_S3_M 0xFF000000 // A high bit value will clear the // corresponding bit in ADI // register 15 -#define ADI_CLR1215_S3_S 24 -#define ADI_CLR1215_S2_M 0x00FF0000 // A high bit value will clear the +#define ADI_CLR1215_S3_S 24 +#define ADI_CLR1215_S2_M 0x00FF0000 // A high bit value will clear the // corresponding bit in ADI // register 14 -#define ADI_CLR1215_S2_S 16 -#define ADI_CLR1215_S1_M 0x0000FF00 // A high bit value will clear the +#define ADI_CLR1215_S2_S 16 +#define ADI_CLR1215_S1_M 0x0000FF00 // A high bit value will clear the // corresponding bit in ADI // register 13 -#define ADI_CLR1215_S1_S 8 -#define ADI_CLR1215_S0_M 0x000000FF // A high bit value will clear the +#define ADI_CLR1215_S1_S 8 +#define ADI_CLR1215_S0_M 0x000000FF // A high bit value will clear the // corresponding bit in ADI // register 12 -#define ADI_CLR1215_S0_S 0 +#define ADI_CLR1215_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_SLAVESTAT register. // //***************************************************************************** -#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ +#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ // signal. Writing 0 to this bit // forces a sync with slave, // ensuring that req will be 0. It // is recommended to write 0 to // this register before power down // of the master. -#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 -#define ADI_SLAVESTAT_DI_REQ_S 1 -#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK +#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 +#define ADI_SLAVESTAT_DI_REQ_S 1 +#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK // signal -#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 -#define ADI_SLAVESTAT_DI_ACK_S 0 +#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 +#define ADI_SLAVESTAT_DI_ACK_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_SLAVECONF register. // //***************************************************************************** -#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer +#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer // accessible when this bit is set. // (unless sticky_bit_overwrite is // asserted on top module) @@ -609,7 +609,7 @@ 0x00000080 #define ADI_SLAVECONF_CONFLOCK_S 7 #define ADI_SLAVECONF_WAITFORACK \ - 0x00000004 // A transaction on the ADI + 0x00000004 // A transaction on the ADI // interface does not end until ack // has been received from the slave // when this bit is set. @@ -618,7 +618,7 @@ 0x00000004 #define ADI_SLAVECONF_WAITFORACK_S 2 #define ADI_SLAVECONF_ADICLKSPEED_M \ - 0x00000003 // Sets the period of an ADI + 0x00000003 // Sets the period of an ADI // transactions. All transactions // takes an even number of clock // cycles,- ADI clock rising edge @@ -641,542 +641,542 @@ // The following are defines for the bit fields in the ADI_O_MASK4B01 register. // //***************************************************************************** -#define ADI_MASK4B01_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B01_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 1 -#define ADI_MASK4B01_M1H_S 28 -#define ADI_MASK4B01_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B01_M1H_S 28 +#define ADI_MASK4B01_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 1, - only bits selected // by mask M1H will be affected by // access -#define ADI_MASK4B01_D1H_S 24 -#define ADI_MASK4B01_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B01_D1H_S 24 +#define ADI_MASK4B01_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 1 -#define ADI_MASK4B01_M1L_S 20 -#define ADI_MASK4B01_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B01_M1L_S 20 +#define ADI_MASK4B01_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 1, - only bits selected // by mask M1L will be affected by // access -#define ADI_MASK4B01_D1L_S 16 -#define ADI_MASK4B01_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B01_D1L_S 16 +#define ADI_MASK4B01_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 0 -#define ADI_MASK4B01_M0H_S 12 -#define ADI_MASK4B01_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B01_M0H_S 12 +#define ADI_MASK4B01_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 0, - only bits selected // by mask M0H will be affected by // access -#define ADI_MASK4B01_D0H_S 8 -#define ADI_MASK4B01_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B01_D0H_S 8 +#define ADI_MASK4B01_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 0 -#define ADI_MASK4B01_M0L_S 4 -#define ADI_MASK4B01_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B01_M0L_S 4 +#define ADI_MASK4B01_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 0, - only bits selected // by mask M0L will be affected by // access -#define ADI_MASK4B01_D0L_S 0 +#define ADI_MASK4B01_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK4B23 register. // //***************************************************************************** -#define ADI_MASK4B23_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B23_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 3 -#define ADI_MASK4B23_M1H_S 28 -#define ADI_MASK4B23_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B23_M1H_S 28 +#define ADI_MASK4B23_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 3, - only bits selected // by mask M1H will be affected by // access -#define ADI_MASK4B23_D1H_S 24 -#define ADI_MASK4B23_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B23_D1H_S 24 +#define ADI_MASK4B23_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 3 -#define ADI_MASK4B23_M1L_S 20 -#define ADI_MASK4B23_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B23_M1L_S 20 +#define ADI_MASK4B23_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 3, - only bits selected // by mask M1L will be affected by // access -#define ADI_MASK4B23_D1L_S 16 -#define ADI_MASK4B23_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B23_D1L_S 16 +#define ADI_MASK4B23_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 2 -#define ADI_MASK4B23_M0H_S 12 -#define ADI_MASK4B23_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B23_M0H_S 12 +#define ADI_MASK4B23_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 2, - only bits selected // by mask M0H will be affected by // access -#define ADI_MASK4B23_D0H_S 8 -#define ADI_MASK4B23_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B23_D0H_S 8 +#define ADI_MASK4B23_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 2 -#define ADI_MASK4B23_M0L_S 4 -#define ADI_MASK4B23_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B23_M0L_S 4 +#define ADI_MASK4B23_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 2, - only bits selected // by mask M0L will be affected by // access -#define ADI_MASK4B23_D0L_S 0 +#define ADI_MASK4B23_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK4B45 register. // //***************************************************************************** -#define ADI_MASK4B45_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B45_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 5 -#define ADI_MASK4B45_M1H_S 28 -#define ADI_MASK4B45_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B45_M1H_S 28 +#define ADI_MASK4B45_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 5, - only bits selected // by mask M1H will be affected by // access -#define ADI_MASK4B45_D1H_S 24 -#define ADI_MASK4B45_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B45_D1H_S 24 +#define ADI_MASK4B45_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 5 -#define ADI_MASK4B45_M1L_S 20 -#define ADI_MASK4B45_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B45_M1L_S 20 +#define ADI_MASK4B45_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 5, - only bits selected // by mask M1L will be affected by // access -#define ADI_MASK4B45_D1L_S 16 -#define ADI_MASK4B45_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B45_D1L_S 16 +#define ADI_MASK4B45_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 4 -#define ADI_MASK4B45_M0H_S 12 -#define ADI_MASK4B45_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B45_M0H_S 12 +#define ADI_MASK4B45_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 4, - only bits selected // by mask M0H will be affected by // access -#define ADI_MASK4B45_D0H_S 8 -#define ADI_MASK4B45_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B45_D0H_S 8 +#define ADI_MASK4B45_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 4 -#define ADI_MASK4B45_M0L_S 4 -#define ADI_MASK4B45_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B45_M0L_S 4 +#define ADI_MASK4B45_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 4, - only bits selected // by mask M0L will be affected by // access -#define ADI_MASK4B45_D0L_S 0 +#define ADI_MASK4B45_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK4B67 register. // //***************************************************************************** -#define ADI_MASK4B67_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B67_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 7 -#define ADI_MASK4B67_M1H_S 28 -#define ADI_MASK4B67_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B67_M1H_S 28 +#define ADI_MASK4B67_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 7, - only bits selected // by mask M1H will be affected by // access -#define ADI_MASK4B67_D1H_S 24 -#define ADI_MASK4B67_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B67_D1H_S 24 +#define ADI_MASK4B67_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 7 -#define ADI_MASK4B67_M1L_S 20 -#define ADI_MASK4B67_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B67_M1L_S 20 +#define ADI_MASK4B67_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 7, - only bits selected // by mask M1L will be affected by // access -#define ADI_MASK4B67_D1L_S 16 -#define ADI_MASK4B67_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B67_D1L_S 16 +#define ADI_MASK4B67_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 6 -#define ADI_MASK4B67_M0H_S 12 -#define ADI_MASK4B67_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B67_M0H_S 12 +#define ADI_MASK4B67_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 6, - only bits selected // by mask M0H will be affected by // access -#define ADI_MASK4B67_D0H_S 8 -#define ADI_MASK4B67_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B67_D0H_S 8 +#define ADI_MASK4B67_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 6 -#define ADI_MASK4B67_M0L_S 4 -#define ADI_MASK4B67_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B67_M0L_S 4 +#define ADI_MASK4B67_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 6, - only bits selected // by mask M0L will be affected by // access -#define ADI_MASK4B67_D0L_S 0 +#define ADI_MASK4B67_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK4B89 register. // //***************************************************************************** -#define ADI_MASK4B89_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B89_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 9 -#define ADI_MASK4B89_M1H_S 28 -#define ADI_MASK4B89_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B89_M1H_S 28 +#define ADI_MASK4B89_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 9, - only bits selected // by mask M1H will be affected by // access -#define ADI_MASK4B89_D1H_S 24 -#define ADI_MASK4B89_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B89_D1H_S 24 +#define ADI_MASK4B89_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 9 -#define ADI_MASK4B89_M1L_S 20 -#define ADI_MASK4B89_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B89_M1L_S 20 +#define ADI_MASK4B89_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 9, - only bits selected // by mask M1L will be affected by // access -#define ADI_MASK4B89_D1L_S 16 -#define ADI_MASK4B89_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B89_D1L_S 16 +#define ADI_MASK4B89_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 8 -#define ADI_MASK4B89_M0H_S 12 -#define ADI_MASK4B89_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B89_M0H_S 12 +#define ADI_MASK4B89_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 8, - only bits selected // by mask M0H will be affected by // access -#define ADI_MASK4B89_D0H_S 8 -#define ADI_MASK4B89_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B89_D0H_S 8 +#define ADI_MASK4B89_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 8 -#define ADI_MASK4B89_M0L_S 4 -#define ADI_MASK4B89_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B89_M0L_S 4 +#define ADI_MASK4B89_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 8, - only bits selected // by mask M0L will be affected by // access -#define ADI_MASK4B89_D0L_S 0 +#define ADI_MASK4B89_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK4B1011 register. // //***************************************************************************** -#define ADI_MASK4B1011_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B1011_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 11 -#define ADI_MASK4B1011_M1H_S 28 -#define ADI_MASK4B1011_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B1011_M1H_S 28 +#define ADI_MASK4B1011_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 11, - only bits // selected by mask M1H will be // affected by access -#define ADI_MASK4B1011_D1H_S 24 -#define ADI_MASK4B1011_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B1011_D1H_S 24 +#define ADI_MASK4B1011_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 11 -#define ADI_MASK4B1011_M1L_S 20 -#define ADI_MASK4B1011_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B1011_M1L_S 20 +#define ADI_MASK4B1011_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 11, - only bits // selected by mask M1L will be // affected by access -#define ADI_MASK4B1011_D1L_S 16 -#define ADI_MASK4B1011_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B1011_D1L_S 16 +#define ADI_MASK4B1011_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 10 -#define ADI_MASK4B1011_M0H_S 12 -#define ADI_MASK4B1011_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B1011_M0H_S 12 +#define ADI_MASK4B1011_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 10, - only bits // selected by mask M0H will be // affected by access -#define ADI_MASK4B1011_D0H_S 8 -#define ADI_MASK4B1011_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B1011_D0H_S 8 +#define ADI_MASK4B1011_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 10 -#define ADI_MASK4B1011_M0L_S 4 -#define ADI_MASK4B1011_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B1011_M0L_S 4 +#define ADI_MASK4B1011_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 10, - only bits // selected by mask M0L will be // affected by access -#define ADI_MASK4B1011_D0L_S 0 +#define ADI_MASK4B1011_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK4B1213 register. // //***************************************************************************** -#define ADI_MASK4B1213_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B1213_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 13 -#define ADI_MASK4B1213_M1H_S 28 -#define ADI_MASK4B1213_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B1213_M1H_S 28 +#define ADI_MASK4B1213_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 13, - only bits // selected by mask M1H will be // affected by access -#define ADI_MASK4B1213_D1H_S 24 -#define ADI_MASK4B1213_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B1213_D1H_S 24 +#define ADI_MASK4B1213_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 13 -#define ADI_MASK4B1213_M1L_S 20 -#define ADI_MASK4B1213_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B1213_M1L_S 20 +#define ADI_MASK4B1213_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 13, - only bits // selected by mask M1L will be // affected by access -#define ADI_MASK4B1213_D1L_S 16 -#define ADI_MASK4B1213_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B1213_D1L_S 16 +#define ADI_MASK4B1213_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 12 -#define ADI_MASK4B1213_M0H_S 12 -#define ADI_MASK4B1213_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B1213_M0H_S 12 +#define ADI_MASK4B1213_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 12, - only bits // selected by mask M0H will be // affected by access -#define ADI_MASK4B1213_D0H_S 8 -#define ADI_MASK4B1213_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B1213_D0H_S 8 +#define ADI_MASK4B1213_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 12 -#define ADI_MASK4B1213_M0L_S 4 -#define ADI_MASK4B1213_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B1213_M0L_S 4 +#define ADI_MASK4B1213_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 12, - only bits // selected by mask M0L will be // affected by access -#define ADI_MASK4B1213_D0L_S 0 +#define ADI_MASK4B1213_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK4B1415 register. // //***************************************************************************** -#define ADI_MASK4B1415_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B1415_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 15 -#define ADI_MASK4B1415_M1H_S 28 -#define ADI_MASK4B1415_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B1415_M1H_S 28 +#define ADI_MASK4B1415_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 15, - only bits // selected by mask M1H will be // affected by access -#define ADI_MASK4B1415_D1H_S 24 -#define ADI_MASK4B1415_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B1415_D1H_S 24 +#define ADI_MASK4B1415_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 15 -#define ADI_MASK4B1415_M1L_S 20 -#define ADI_MASK4B1415_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B1415_M1L_S 20 +#define ADI_MASK4B1415_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 15, - only bits // selected by mask M1L will be // affected by access -#define ADI_MASK4B1415_D1L_S 16 -#define ADI_MASK4B1415_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B1415_D1L_S 16 +#define ADI_MASK4B1415_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 14 -#define ADI_MASK4B1415_M0H_S 12 -#define ADI_MASK4B1415_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B1415_M0H_S 12 +#define ADI_MASK4B1415_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 14, - only bits // selected by mask M0H will be // affected by access -#define ADI_MASK4B1415_D0H_S 8 -#define ADI_MASK4B1415_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B1415_D0H_S 8 +#define ADI_MASK4B1415_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 14 -#define ADI_MASK4B1415_M0L_S 4 -#define ADI_MASK4B1415_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B1415_M0L_S 4 +#define ADI_MASK4B1415_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 14, - only bits // selected by mask M0L will be // affected by access -#define ADI_MASK4B1415_D0L_S 0 +#define ADI_MASK4B1415_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK8B01 register. // //***************************************************************************** -#define ADI_MASK8B01_M1_M 0xFF000000 // Mask for ADI register 1 -#define ADI_MASK8B01_M1_S 24 -#define ADI_MASK8B01_D1_M 0x00FF0000 // Data for ADI register 1, - only +#define ADI_MASK8B01_M1_M 0xFF000000 // Mask for ADI register 1 +#define ADI_MASK8B01_M1_S 24 +#define ADI_MASK8B01_D1_M 0x00FF0000 // Data for ADI register 1, - only // bits selected by mask M1 will be // affected by access -#define ADI_MASK8B01_D1_S 16 -#define ADI_MASK8B01_M0_M 0x0000FF00 // Mask for ADI register 0 -#define ADI_MASK8B01_M0_S 8 -#define ADI_MASK8B01_D0_M 0x000000FF // Data for ADI register 0, - only +#define ADI_MASK8B01_D1_S 16 +#define ADI_MASK8B01_M0_M 0x0000FF00 // Mask for ADI register 0 +#define ADI_MASK8B01_M0_S 8 +#define ADI_MASK8B01_D0_M 0x000000FF // Data for ADI register 0, - only // bits selected by mask M0 will be // affected by access -#define ADI_MASK8B01_D0_S 0 +#define ADI_MASK8B01_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK8B23 register. // //***************************************************************************** -#define ADI_MASK8B23_M1_M 0xFF000000 // Mask for ADI register 3 -#define ADI_MASK8B23_M1_S 24 -#define ADI_MASK8B23_D1_M 0x00FF0000 // Data for ADI register 3, - only +#define ADI_MASK8B23_M1_M 0xFF000000 // Mask for ADI register 3 +#define ADI_MASK8B23_M1_S 24 +#define ADI_MASK8B23_D1_M 0x00FF0000 // Data for ADI register 3, - only // bits selected by mask M1 will be // affected by access -#define ADI_MASK8B23_D1_S 16 -#define ADI_MASK8B23_M0_M 0x0000FF00 // Mask for ADI register 2 -#define ADI_MASK8B23_M0_S 8 -#define ADI_MASK8B23_D0_M 0x000000FF // Data for ADI register 2, - only +#define ADI_MASK8B23_D1_S 16 +#define ADI_MASK8B23_M0_M 0x0000FF00 // Mask for ADI register 2 +#define ADI_MASK8B23_M0_S 8 +#define ADI_MASK8B23_D0_M 0x000000FF // Data for ADI register 2, - only // bits selected by mask M0 will be // affected by access -#define ADI_MASK8B23_D0_S 0 +#define ADI_MASK8B23_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK8B45 register. // //***************************************************************************** -#define ADI_MASK8B45_M1_M 0xFF000000 // Mask for ADI register 5 -#define ADI_MASK8B45_M1_S 24 -#define ADI_MASK8B45_D1_M 0x00FF0000 // Data for ADI register 5, - only +#define ADI_MASK8B45_M1_M 0xFF000000 // Mask for ADI register 5 +#define ADI_MASK8B45_M1_S 24 +#define ADI_MASK8B45_D1_M 0x00FF0000 // Data for ADI register 5, - only // bits selected by mask M1 will be // affected by access -#define ADI_MASK8B45_D1_S 16 -#define ADI_MASK8B45_M0_M 0x0000FF00 // Mask for ADI register 4 -#define ADI_MASK8B45_M0_S 8 -#define ADI_MASK8B45_D0_M 0x000000FF // Data for ADI register 4, - only +#define ADI_MASK8B45_D1_S 16 +#define ADI_MASK8B45_M0_M 0x0000FF00 // Mask for ADI register 4 +#define ADI_MASK8B45_M0_S 8 +#define ADI_MASK8B45_D0_M 0x000000FF // Data for ADI register 4, - only // bits selected by mask M0 will be // affected by access -#define ADI_MASK8B45_D0_S 0 +#define ADI_MASK8B45_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK8B67 register. // //***************************************************************************** -#define ADI_MASK8B67_M1_M 0xFF000000 // Mask for ADI register 7 -#define ADI_MASK8B67_M1_S 24 -#define ADI_MASK8B67_D1_M 0x00FF0000 // Data for ADI register 7, - only +#define ADI_MASK8B67_M1_M 0xFF000000 // Mask for ADI register 7 +#define ADI_MASK8B67_M1_S 24 +#define ADI_MASK8B67_D1_M 0x00FF0000 // Data for ADI register 7, - only // bits selected by mask M1 will be // affected by access -#define ADI_MASK8B67_D1_S 16 -#define ADI_MASK8B67_M0_M 0x0000FF00 // Mask for ADI register 6 -#define ADI_MASK8B67_M0_S 8 -#define ADI_MASK8B67_D0_M 0x000000FF // Data for ADI register 6, - only +#define ADI_MASK8B67_D1_S 16 +#define ADI_MASK8B67_M0_M 0x0000FF00 // Mask for ADI register 6 +#define ADI_MASK8B67_M0_S 8 +#define ADI_MASK8B67_D0_M 0x000000FF // Data for ADI register 6, - only // bits selected by mask M0 will be // affected by access -#define ADI_MASK8B67_D0_S 0 +#define ADI_MASK8B67_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK8B89 register. // //***************************************************************************** -#define ADI_MASK8B89_M1_M 0xFF000000 // Mask for ADI register 9 -#define ADI_MASK8B89_M1_S 24 -#define ADI_MASK8B89_D1_M 0x00FF0000 // Data for ADI register 9, - only +#define ADI_MASK8B89_M1_M 0xFF000000 // Mask for ADI register 9 +#define ADI_MASK8B89_M1_S 24 +#define ADI_MASK8B89_D1_M 0x00FF0000 // Data for ADI register 9, - only // bits selected by mask M1 will be // affected by access -#define ADI_MASK8B89_D1_S 16 -#define ADI_MASK8B89_M0_M 0x0000FF00 // Mask for ADI register 8 -#define ADI_MASK8B89_M0_S 8 -#define ADI_MASK8B89_D0_M 0x000000FF // Data for ADI register 8, - only +#define ADI_MASK8B89_D1_S 16 +#define ADI_MASK8B89_M0_M 0x0000FF00 // Mask for ADI register 8 +#define ADI_MASK8B89_M0_S 8 +#define ADI_MASK8B89_D0_M 0x000000FF // Data for ADI register 8, - only // bits selected by mask M0 will be // affected by access -#define ADI_MASK8B89_D0_S 0 +#define ADI_MASK8B89_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK8B1011 register. // //***************************************************************************** -#define ADI_MASK8B1011_M1_M 0xFF000000 // Mask for ADI register 11 -#define ADI_MASK8B1011_M1_S 24 -#define ADI_MASK8B1011_D1_M 0x00FF0000 // Data for ADI register 11, - +#define ADI_MASK8B1011_M1_M 0xFF000000 // Mask for ADI register 11 +#define ADI_MASK8B1011_M1_S 24 +#define ADI_MASK8B1011_D1_M 0x00FF0000 // Data for ADI register 11, - // only bits selected by mask M1 // will be affected by access -#define ADI_MASK8B1011_D1_S 16 -#define ADI_MASK8B1011_M0_M 0x0000FF00 // Mask for ADI register 10 -#define ADI_MASK8B1011_M0_S 8 -#define ADI_MASK8B1011_D0_M 0x000000FF // Data for ADI register 10, - +#define ADI_MASK8B1011_D1_S 16 +#define ADI_MASK8B1011_M0_M 0x0000FF00 // Mask for ADI register 10 +#define ADI_MASK8B1011_M0_S 8 +#define ADI_MASK8B1011_D0_M 0x000000FF // Data for ADI register 10, - // only bits selected by mask M0 // will be affected by access -#define ADI_MASK8B1011_D0_S 0 +#define ADI_MASK8B1011_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK8B1213 register. // //***************************************************************************** -#define ADI_MASK8B1213_M1_M 0xFF000000 // Mask for ADI register 13 -#define ADI_MASK8B1213_M1_S 24 -#define ADI_MASK8B1213_D1_M 0x00FF0000 // Data for ADI register 13, - +#define ADI_MASK8B1213_M1_M 0xFF000000 // Mask for ADI register 13 +#define ADI_MASK8B1213_M1_S 24 +#define ADI_MASK8B1213_D1_M 0x00FF0000 // Data for ADI register 13, - // only bits selected by mask M1 // will be affected by access -#define ADI_MASK8B1213_D1_S 16 -#define ADI_MASK8B1213_M0_M 0x0000FF00 // Mask for ADI register 12 -#define ADI_MASK8B1213_M0_S 8 -#define ADI_MASK8B1213_D0_M 0x000000FF // Data for ADI register 12, - +#define ADI_MASK8B1213_D1_S 16 +#define ADI_MASK8B1213_M0_M 0x0000FF00 // Mask for ADI register 12 +#define ADI_MASK8B1213_M0_S 8 +#define ADI_MASK8B1213_D0_M 0x000000FF // Data for ADI register 12, - // only bits selected by mask M0 // will be affected by access -#define ADI_MASK8B1213_D0_S 0 +#define ADI_MASK8B1213_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK8B1415 register. // //***************************************************************************** -#define ADI_MASK8B1415_M1_M 0xFF000000 // Mask for ADI register 15 -#define ADI_MASK8B1415_M1_S 24 -#define ADI_MASK8B1415_D1_M 0x00FF0000 // Data for ADI register 15, - +#define ADI_MASK8B1415_M1_M 0xFF000000 // Mask for ADI register 15 +#define ADI_MASK8B1415_M1_S 24 +#define ADI_MASK8B1415_D1_M 0x00FF0000 // Data for ADI register 15, - // only bits selected by mask M1 // will be affected by access -#define ADI_MASK8B1415_D1_S 16 -#define ADI_MASK8B1415_M0_M 0x0000FF00 // Mask for ADI register 14 -#define ADI_MASK8B1415_M0_S 8 -#define ADI_MASK8B1415_D0_M 0x000000FF // Data for ADI register 14, - +#define ADI_MASK8B1415_D1_S 16 +#define ADI_MASK8B1415_M0_M 0x0000FF00 // Mask for ADI register 14 +#define ADI_MASK8B1415_M0_S 8 +#define ADI_MASK8B1415_D0_M 0x000000FF // Data for ADI register 14, - // only bits selected by mask M0 // will be affected by access -#define ADI_MASK8B1415_D0_S 0 +#define ADI_MASK8B1415_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B01 register. // //***************************************************************************** -#define ADI_MASK16B01_M_M 0xFFFF0000 // Mask for ADI register 0 and 1 -#define ADI_MASK16B01_M_S 16 -#define ADI_MASK16B01_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B01_M_M 0xFFFF0000 // Mask for ADI register 0 and 1 +#define ADI_MASK16B01_M_S 16 +#define ADI_MASK16B01_D_M 0x0000FFFF // Data for ADI register at // offsets 0 and 1, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B01_D_S 0 +#define ADI_MASK16B01_D_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B23 register. // //***************************************************************************** -#define ADI_MASK16B23_M_M 0xFFFF0000 // Mask for ADI register 2 and 3 -#define ADI_MASK16B23_M_S 16 -#define ADI_MASK16B23_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B23_M_M 0xFFFF0000 // Mask for ADI register 2 and 3 +#define ADI_MASK16B23_M_S 16 +#define ADI_MASK16B23_D_M 0x0000FFFF // Data for ADI register at // offsets 2 and 3, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B23_D_S 0 +#define ADI_MASK16B23_D_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B45 register. // //***************************************************************************** -#define ADI_MASK16B45_M_M 0xFFFF0000 // Mask for ADI register 4 and 5 -#define ADI_MASK16B45_M_S 16 -#define ADI_MASK16B45_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B45_M_M 0xFFFF0000 // Mask for ADI register 4 and 5 +#define ADI_MASK16B45_M_S 16 +#define ADI_MASK16B45_D_M 0x0000FFFF // Data for ADI register at // offsets 4 and 5, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B45_D_S 0 +#define ADI_MASK16B45_D_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B67 register. // //***************************************************************************** -#define ADI_MASK16B67_M_M 0xFFFF0000 // Mask for ADI register 6 and 7 -#define ADI_MASK16B67_M_S 16 -#define ADI_MASK16B67_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B67_M_M 0xFFFF0000 // Mask for ADI register 6 and 7 +#define ADI_MASK16B67_M_S 16 +#define ADI_MASK16B67_D_M 0x0000FFFF // Data for ADI register at // offsets 6 and 7, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B67_D_S 0 +#define ADI_MASK16B67_D_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B89 register. // //***************************************************************************** -#define ADI_MASK16B89_M_M 0xFFFF0000 // Mask for ADI register 8 and 9 -#define ADI_MASK16B89_M_S 16 -#define ADI_MASK16B89_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B89_M_M 0xFFFF0000 // Mask for ADI register 8 and 9 +#define ADI_MASK16B89_M_S 16 +#define ADI_MASK16B89_D_M 0x0000FFFF // Data for ADI register at // offsets 8 and 9, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B89_D_S 0 +#define ADI_MASK16B89_D_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B1011 register. // //***************************************************************************** -#define ADI_MASK16B1011_M_M 0xFFFF0000 // Mask for ADI register 10 and 11 -#define ADI_MASK16B1011_M_S 16 -#define ADI_MASK16B1011_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B1011_M_M 0xFFFF0000 // Mask for ADI register 10 and 11 +#define ADI_MASK16B1011_M_S 16 +#define ADI_MASK16B1011_D_M 0x0000FFFF // Data for ADI register at // offsets 10 and 11, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B1011_D_S 0 +#define ADI_MASK16B1011_D_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B1213 register. // //***************************************************************************** -#define ADI_MASK16B1213_M_M 0xFFFF0000 // Mask for ADI register 12 and 13 -#define ADI_MASK16B1213_M_S 16 -#define ADI_MASK16B1213_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B1213_M_M 0xFFFF0000 // Mask for ADI register 12 and 13 +#define ADI_MASK16B1213_M_S 16 +#define ADI_MASK16B1213_D_M 0x0000FFFF // Data for ADI register at // offsets 12 and 13, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B1213_D_S 0 +#define ADI_MASK16B1213_D_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B1415 register. // //***************************************************************************** -#define ADI_MASK16B1415_M_M 0xFFFF0000 // Mask for ADI register 14 and 15 -#define ADI_MASK16B1415_M_S 16 -#define ADI_MASK16B1415_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B1415_M_M 0xFFFF0000 // Mask for ADI register 14 and 15 +#define ADI_MASK16B1415_M_S 16 +#define ADI_MASK16B1415_D_M 0x0000FFFF // Data for ADI register at // offsets 14 and 15, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B1415_D_S 0 +#define ADI_MASK16B1415_D_S 0 #endif // __HW_ADI_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi_2_refsys.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi_2_refsys.h index 72ae2eb..2af8af2 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi_2_refsys.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi_2_refsys.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_adi_2_refsys_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_adi_2_refsys_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_ADI_2_REFSYS_H__ #define __HW_ADI_2_REFSYS_H__ @@ -44,34 +44,34 @@ // //***************************************************************************** // Internal -#define ADI_2_REFSYS_O_REFSYSCTL0 0x00000000 +#define ADI_2_REFSYS_O_REFSYSCTL0 0x00000000 // Internal -#define ADI_2_REFSYS_O_SOCLDOCTL0 0x00000002 +#define ADI_2_REFSYS_O_SOCLDOCTL0 0x00000002 // Internal -#define ADI_2_REFSYS_O_SOCLDOCTL1 0x00000003 +#define ADI_2_REFSYS_O_SOCLDOCTL1 0x00000003 // Internal -#define ADI_2_REFSYS_O_SOCLDOCTL2 0x00000004 +#define ADI_2_REFSYS_O_SOCLDOCTL2 0x00000004 // Internal -#define ADI_2_REFSYS_O_SOCLDOCTL3 0x00000005 +#define ADI_2_REFSYS_O_SOCLDOCTL3 0x00000005 // Internal -#define ADI_2_REFSYS_O_SOCLDOCTL4 0x00000006 +#define ADI_2_REFSYS_O_SOCLDOCTL4 0x00000006 // Internal -#define ADI_2_REFSYS_O_SOCLDOCTL5 0x00000007 +#define ADI_2_REFSYS_O_SOCLDOCTL5 0x00000007 // Internal -#define ADI_2_REFSYS_O_HPOSCCTL0 0x0000000A +#define ADI_2_REFSYS_O_HPOSCCTL0 0x0000000A // Internal -#define ADI_2_REFSYS_O_HPOSCCTL1 0x0000000B +#define ADI_2_REFSYS_O_HPOSCCTL1 0x0000000B // Internal -#define ADI_2_REFSYS_O_HPOSCCTL2 0x0000000C +#define ADI_2_REFSYS_O_HPOSCCTL2 0x0000000C //***************************************************************************** // @@ -81,9 +81,9 @@ // Field: [4:0] TRIM_IREF // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_W 5 -#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_M 0x0000001F -#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_S 0 +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_W 5 +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_M 0x0000001F +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_S 0 //***************************************************************************** // @@ -93,16 +93,16 @@ // Field: [7:4] VTRIM_UDIG // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_W 4 -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_M 0x000000F0 -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_S 4 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_W 4 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_M 0x000000F0 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_S 4 // Field: [3:0] VTRIM_BOD // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_W 4 -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_M 0x0000000F -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_S 0 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_W 4 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_M 0x0000000F +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_S 0 //***************************************************************************** // @@ -112,16 +112,16 @@ // Field: [7:4] VTRIM_COARSE // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_W 4 -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_M 0x000000F0 -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_S 4 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_W 4 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_M 0x000000F0 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_S 4 // Field: [3:0] VTRIM_DIG // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_W 4 -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_M 0x0000000F -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_S 0 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_W 4 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_M 0x0000000F +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_S 0 //***************************************************************************** // @@ -131,9 +131,9 @@ // Field: [2:0] VTRIM_DELTA // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_W 3 -#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_M 0x00000007 -#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_S 0 +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_W 3 +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_S 0 //***************************************************************************** // @@ -143,9 +143,9 @@ // Field: [7:6] ITRIM_DIGLDO_LOAD // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_W 2 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_M 0x000000C0 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_S 6 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_W 2 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_M 0x000000C0 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_S 6 // Field: [5:3] ITRIM_DIGLDO // @@ -155,20 +155,20 @@ // BIAS_100P Internal. Only to be used through TI provided API. // BIAS_80P Internal. Only to be used through TI provided API. // BIAS_60P Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_W 3 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_M 0x00000038 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_S 3 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_120P 0x00000038 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_100P 0x00000028 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_80P 0x00000018 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_60P 0x00000000 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_W 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_M 0x00000038 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_S 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_120P 0x00000038 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_100P 0x00000028 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_80P 0x00000018 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_60P 0x00000000 // Field: [2:0] ITRIM_UDIGLDO // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_W 3 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_M 0x00000007 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_S 0 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_W 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_S 0 //***************************************************************************** // @@ -178,23 +178,23 @@ // Field: [6:5] UDIG_ITEST_EN // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_W 2 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_M 0x00000060 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_S 5 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_W 2 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_M 0x00000060 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_S 5 // Field: [4:2] DIG_ITEST_EN // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_W 3 -#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_M 0x0000001C -#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_S 2 +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_W 3 +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_M 0x0000001C +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_S 2 // Field: [1] BIAS_DIS // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS 0x00000002 -#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_M 0x00000002 -#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_S 1 +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_M 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_S 1 // Field: [0] UDIG_LDO_EN // @@ -202,11 +202,11 @@ // ENUMs: // EN Internal. Only to be used through TI provided API. // DIS Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN 0x00000001 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_M 0x00000001 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_S 0 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_EN 0x00000001 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_DIS 0x00000000 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_M 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_S 0 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_EN 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_DIS 0x00000000 //***************************************************************************** // @@ -216,9 +216,9 @@ // Field: [3] IMON_ITEST_EN // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN 0x00000008 -#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_M 0x00000008 -#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_S 3 +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN 0x00000008 +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_M 0x00000008 +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_S 3 // Field: [2:0] TESTSEL // @@ -228,13 +228,13 @@ // VREF_AMP Internal. Only to be used through TI provided API. // ITEST Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_W 3 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_M 0x00000007 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_S 0 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VDD_AON 0x00000004 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VREF_AMP 0x00000002 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_ITEST 0x00000001 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_NC 0x00000000 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_W 3 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_S 0 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VDD_AON 0x00000004 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VREF_AMP 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_ITEST 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_NC 0x00000000 //***************************************************************************** // @@ -244,9 +244,9 @@ // Field: [7] FILTER_EN // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN 0x00000080 -#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M 0x00000080 -#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S 7 +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S 7 // Field: [6:5] BIAS_RECHARGE_DLY // @@ -256,13 +256,13 @@ // MIN_DLY_X4 Internal. Only to be used through TI provided API. // MIN_DLY_X2 Internal. Only to be used through TI provided API. // MIN_DLY_X1 Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_W 2 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M 0x00000060 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S 5 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X8 0x00000060 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X4 0x00000040 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X2 0x00000020 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X1 0x00000000 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M 0x00000060 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S 5 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X8 0x00000060 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X4 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X2 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X1 0x00000000 // Field: [4:3] TUNE_CAP // @@ -272,20 +272,20 @@ // SHIFT_M70 Internal. Only to be used through TI provided API. // SHIFT_M35 Internal. Only to be used through TI provided API. // SHIFT_0 Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_W 2 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_M 0x00000018 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_S 3 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M108 0x00000018 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M70 0x00000010 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M35 0x00000008 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_0 0x00000000 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_M 0x00000018 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_S 3 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M108 0x00000018 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M70 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M35 0x00000008 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_0 0x00000000 // Field: [2:1] SERIES_CAP // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_W 2 -#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M 0x00000006 -#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S 1 +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M 0x00000006 +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S 1 // Field: [0] DIV3_BYPASS // @@ -293,11 +293,11 @@ // ENUMs: // HPOSC_2520MHZ Internal. Only to be used through TI provided API. // HPOSC_840MHZ Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS 0x00000001 -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M 0x00000001 -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S 0 -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_2520MHZ 0x00000001 -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_840MHZ 0x00000000 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S 0 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_2520MHZ 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_840MHZ 0x00000000 //***************************************************************************** // @@ -307,23 +307,23 @@ // Field: [5] BIAS_DIS // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS 0x00000020 -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_M 0x00000020 -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_S 5 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_M 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_S 5 // Field: [4] PWRDET_EN // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN 0x00000010 -#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_M 0x00000010 -#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_S 4 +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_M 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_S 4 // Field: [3:0] BIAS_RES_SET // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_W 4 -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M 0x0000000F -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S 0 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_W 4 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M 0x0000000F +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S 0 //***************************************************************************** // @@ -333,30 +333,29 @@ // Field: [7] BIAS_HOLD_MODE_EN // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN 0x00000080 -#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M 0x00000080 -#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S 7 +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S 7 // Field: [6] TESTMUX_EN // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN 0x00000040 -#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_M 0x00000040 -#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_S 6 +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_M 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_S 6 // Field: [5:4] ATEST_SEL // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_W 2 -#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_M 0x00000030 -#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_S 4 +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_W 2 +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_M 0x00000030 +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_S 4 // Field: [3:0] CURRMIRR_RATIO // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_W 4 -#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M 0x0000000F -#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S 0 - +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_W 4 +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M 0x0000000F +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S 0 #endif // __ADI_2_REFSYS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi_3_refsys.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi_3_refsys.h index deedeba..2af46aa 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi_3_refsys.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi_3_refsys.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_adi_3_refsys_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_adi_3_refsys_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_ADI_3_REFSYS_H__ #define __HW_ADI_3_REFSYS_H__ @@ -44,37 +44,37 @@ // //***************************************************************************** // Analog Test Control -#define ADI_3_REFSYS_O_SPARE0 0x00000001 +#define ADI_3_REFSYS_O_SPARE0 0x00000001 // Internal -#define ADI_3_REFSYS_O_REFSYSCTL0 0x00000002 +#define ADI_3_REFSYS_O_REFSYSCTL0 0x00000002 // Internal -#define ADI_3_REFSYS_O_REFSYSCTL1 0x00000003 +#define ADI_3_REFSYS_O_REFSYSCTL1 0x00000003 // Internal -#define ADI_3_REFSYS_O_REFSYSCTL2 0x00000004 +#define ADI_3_REFSYS_O_REFSYSCTL2 0x00000004 // Internal -#define ADI_3_REFSYS_O_REFSYSCTL3 0x00000005 +#define ADI_3_REFSYS_O_REFSYSCTL3 0x00000005 // DCDC Control 0 -#define ADI_3_REFSYS_O_DCDCCTL0 0x00000006 +#define ADI_3_REFSYS_O_DCDCCTL0 0x00000006 // DCDC Control 1 -#define ADI_3_REFSYS_O_DCDCCTL1 0x00000007 +#define ADI_3_REFSYS_O_DCDCCTL1 0x00000007 // DCDC Control 2 -#define ADI_3_REFSYS_O_DCDCCTL2 0x00000008 +#define ADI_3_REFSYS_O_DCDCCTL2 0x00000008 // DCDC Control 3 -#define ADI_3_REFSYS_O_DCDCCTL3 0x00000009 +#define ADI_3_REFSYS_O_DCDCCTL3 0x00000009 // Internal -#define ADI_3_REFSYS_O_DCDCCTL4 0x0000000A +#define ADI_3_REFSYS_O_DCDCCTL4 0x0000000A // Internal -#define ADI_3_REFSYS_O_DCDCCTL5 0x0000000B +#define ADI_3_REFSYS_O_DCDCCTL5 0x0000000B //***************************************************************************** // @@ -85,9 +85,9 @@ // // Software should not rely on the value of a reserved. Writing any other value // than the reset value may result in undefined behavior. -#define ADI_3_REFSYS_SPARE0_SPARE0_W 8 -#define ADI_3_REFSYS_SPARE0_SPARE0_M 0x000000FF -#define ADI_3_REFSYS_SPARE0_SPARE0_S 0 +#define ADI_3_REFSYS_SPARE0_SPARE0_W 8 +#define ADI_3_REFSYS_SPARE0_SPARE0_M 0x000000FF +#define ADI_3_REFSYS_SPARE0_SPARE0_S 0 //***************************************************************************** // @@ -107,18 +107,18 @@ // IVREF4U Internal. Only to be used through TI provided API. // IPTAT2U Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_W 8 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_M 0x000000FF -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_S 0 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_BMCOMPOUT 0x00000080 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VTEMP 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VREF0P8V 0x00000020 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBGUNBUFF 0x00000010 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBG 0x00000008 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IREF4U 0x00000004 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IVREF4U 0x00000002 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IPTAT2U 0x00000001 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_NC 0x00000000 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_W 8 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_M 0x000000FF +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_S 0 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_BMCOMPOUT 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VTEMP 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VREF0P8V 0x00000020 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBGUNBUFF 0x00000010 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBG 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IREF4U 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IVREF4U 0x00000002 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IPTAT2U 0x00000001 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_NC 0x00000000 //***************************************************************************** // @@ -161,41 +161,41 @@ // POS_6 Internal. Only to be used through TI provided API. // POS_5 Internal. Only to be used through TI provided API. // POS_4 Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_W 5 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M 0x000000F8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S 3 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_27 0x000000F8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_26 0x000000F0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_25 0x000000E8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_24 0x000000E0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 0x000000D8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_30 0x000000D0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_29 0x000000C8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_28 0x000000C0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_19 0x000000B8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_18 0x000000B0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_17 0x000000A8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_16 0x000000A0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_23 0x00000098 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_22 0x00000090 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_21 0x00000088 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_20 0x00000080 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_11 0x00000078 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_10 0x00000070 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_9 0x00000068 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_8 0x00000060 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_15 0x00000058 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_14 0x00000050 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_13 0x00000048 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_12 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_3 0x00000038 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_2 0x00000030 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_1 0x00000028 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_0 0x00000020 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_7 0x00000018 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_6 0x00000010 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_5 0x00000008 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_4 0x00000000 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_W 5 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M 0x000000F8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S 3 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_27 0x000000F8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_26 0x000000F0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_25 0x000000E8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_24 0x000000E0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 0x000000D8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_30 0x000000D0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_29 0x000000C8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_28 0x000000C0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_19 0x000000B8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_18 0x000000B0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_17 0x000000A8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_16 0x000000A0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_23 0x00000098 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_22 0x00000090 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_21 0x00000088 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_20 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_11 0x00000078 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_10 0x00000070 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_9 0x00000068 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_8 0x00000060 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_15 0x00000058 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_14 0x00000050 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_13 0x00000048 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_12 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_3 0x00000038 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_2 0x00000030 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_1 0x00000028 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_0 0x00000020 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_7 0x00000018 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_6 0x00000010 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_5 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_4 0x00000000 // Field: [2] BATMON_COMP_TEST_EN // @@ -203,11 +203,11 @@ // ENUMs: // EN Internal. Only to be used through TI provided API. // DIS Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN 0x00000004 -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_M 0x00000004 -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_S 2 -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_EN 0x00000004 -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_DIS 0x00000000 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_M 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_S 2 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_EN 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_DIS 0x00000000 // Field: [1:0] TESTCTL // @@ -216,12 +216,12 @@ // IPTAT1U Internal. Only to be used through TI provided API. // BMCOMPIN Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_W 2 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_M 0x00000003 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_S 0 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_IPTAT1U 0x00000002 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_BMCOMPIN 0x00000001 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_NC 0x00000000 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_W 2 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_M 0x00000003 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_S 0 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_IPTAT1U 0x00000002 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_BMCOMPIN 0x00000001 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_NC 0x00000000 //***************************************************************************** // @@ -231,16 +231,16 @@ // Field: [7:4] TRIM_VREF // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_W 4 -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_M 0x000000F0 -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_S 4 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_W 4 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_M 0x000000F0 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_S 4 // Field: [1:0] TRIM_TSENSE // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_W 2 -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_M 0x00000003 -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_S 0 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_W 2 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_M 0x00000003 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_S 0 //***************************************************************************** // @@ -250,9 +250,9 @@ // Field: [7] BOD_BG_TRIM_EN // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN 0x00000080 -#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_M 0x00000080 -#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_S 7 +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_M 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_S 7 // Field: [6] VTEMP_EN // @@ -260,18 +260,18 @@ // ENUMs: // EN Internal. Only to be used through TI provided API. // DIS Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_M 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_S 6 -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_EN 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_DIS 0x00000000 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_M 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_S 6 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_EN 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_DIS 0x00000000 // Field: [5:0] TRIM_VBG // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W 6 -#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M 0x0000003F -#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S 0 +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W 6 +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M 0x0000003F +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S 0 //***************************************************************************** // @@ -286,9 +286,9 @@ // 0x0: Default 11mA. // 0x3: Max 15mA. // 0x4: Max 5mA -#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_W 3 -#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_M 0x000000E0 -#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_S 5 +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_W 3 +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_M 0x000000E0 +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_S 5 // Field: [4:0] VDDR_TRIM // @@ -303,9 +303,9 @@ // 0x05: Typical voltage after trim voltage 1.71V. // 0x15: Max voltage 1.96V. // 0x16: Min voltage 1.47V. -#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_W 5 -#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M 0x0000001F -#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S 0 +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_W 5 +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M 0x0000001F +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S 0 //***************************************************************************** // @@ -321,9 +321,9 @@ // 0x1: Increase GLDO bias by 1.3x. // 0x2: Increase GLDO bias by 1.6x. // 0x3: Decrease GLDO bias by 0.7x. -#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_W 2 -#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_M 0x000000C0 -#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_S 6 +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_W 2 +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_M 0x000000C0 +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_S 6 // Field: [5] VDDR_OK_HYST // @@ -331,9 +331,9 @@ // // 0: Hysteresis = 60mV // 1: Hysteresis = 70mV -#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST 0x00000020 -#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_M 0x00000020 -#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_S 5 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST 0x00000020 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_S 5 // Field: [4:0] VDDR_TRIM_SLEEP // @@ -348,9 +348,9 @@ // 0x19: Typical voltage after trim voltage 1.52V. // 0x15: Max voltage 1.96V. // 0x16: Min voltage 1.47V. -#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_W 5 -#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M 0x0000001F -#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S 0 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_W 5 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M 0x0000001F +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S 0 //***************************************************************************** // @@ -363,9 +363,9 @@ // // 0: Erroramp Off (Default) // 1: Erroramp On. Turns on GLDO error amp switch. -#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW 0x00000040 -#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_M 0x00000040 -#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_S 6 +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW 0x00000040 +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_M 0x00000040 +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_S 6 // Field: [5] TEST_VDDR // @@ -375,9 +375,9 @@ // 1: Connected // // Set TESTSEL = 0x0 first before setting this bit. -#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR 0x00000020 -#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_M 0x00000020 -#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_S 5 +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR 0x00000020 +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_S 5 // Field: [4] BIAS_DIS // @@ -385,9 +385,9 @@ // // 0: Dummy bias current on (Default) // 1: Dummy bias current off -#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS 0x00000010 -#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_M 0x00000010 -#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_S 4 +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS 0x00000010 +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_M 0x00000010 +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_S 4 // Field: [3:0] TESTSEL // @@ -399,14 +399,14 @@ // bus. // ERRAMP_OUT Error amp output voltage connected to test bus. // NC No signal connected to test bus. -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_W 4 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_M 0x0000000F -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_S 0 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_VDDROK 0x00000008 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_IB1U 0x00000004 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_PASSGATE 0x00000002 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_ERRAMP_OUT 0x00000001 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_NC 0x00000000 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_W 4 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_M 0x0000000F +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_S 0 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_VDDROK 0x00000008 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_IB1U 0x00000004 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_PASSGATE 0x00000002 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_ERRAMP_OUT 0x00000001 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_NC 0x00000000 //***************************************************************************** // @@ -421,23 +421,23 @@ // Field: [7:6] DEADTIME_TRIM // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_W 2 -#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_M 0x000000C0 -#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_S 6 +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_W 2 +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_M 0x000000C0 +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_S 6 // Field: [5:3] LOW_EN_SEL // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_W 3 -#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_M 0x00000038 -#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_S 3 +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_W 3 +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_M 0x00000038 +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_S 3 // Field: [2:0] HIGH_EN_SEL // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_W 3 -#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_M 0x00000007 -#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_S 0 +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_W 3 +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_M 0x00000007 +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_S 0 //***************************************************************************** // @@ -447,16 +447,16 @@ // Field: [5] TESTN // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL5_TESTN 0x00000020 -#define ADI_3_REFSYS_DCDCCTL5_TESTN_M 0x00000020 -#define ADI_3_REFSYS_DCDCCTL5_TESTN_S 5 +#define ADI_3_REFSYS_DCDCCTL5_TESTN 0x00000020 +#define ADI_3_REFSYS_DCDCCTL5_TESTN_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL5_TESTN_S 5 // Field: [4] TESTP // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL5_TESTP 0x00000010 -#define ADI_3_REFSYS_DCDCCTL5_TESTP_M 0x00000010 -#define ADI_3_REFSYS_DCDCCTL5_TESTP_S 4 +#define ADI_3_REFSYS_DCDCCTL5_TESTP 0x00000010 +#define ADI_3_REFSYS_DCDCCTL5_TESTP_M 0x00000010 +#define ADI_3_REFSYS_DCDCCTL5_TESTP_S 4 // Field: [3] DITHER_EN // @@ -464,18 +464,17 @@ // ENUMs: // EN Internal. Only to be used through TI provided API. // DIS Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN 0x00000008 -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_M 0x00000008 -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_S 3 -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_EN 0x00000008 -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_DIS 0x00000000 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_M 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_S 3 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_EN 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_DIS 0x00000000 // Field: [2:0] IPEAK // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL5_IPEAK_W 3 -#define ADI_3_REFSYS_DCDCCTL5_IPEAK_M 0x00000007 -#define ADI_3_REFSYS_DCDCCTL5_IPEAK_S 0 - +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_W 3 +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_M 0x00000007 +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_S 0 #endif // __ADI_3_REFSYS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi_4_aux.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi_4_aux.h index af14ac4..59f3ffb 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi_4_aux.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_adi_4_aux.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_adi_4_aux_h -* Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) -* Revision: 48904 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_adi_4_aux_h + * Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) + * Revision: 48904 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_ADI_4_AUX_H__ #define __HW_ADI_4_AUX_H__ @@ -44,37 +44,37 @@ // //***************************************************************************** // Internal -#define ADI_4_AUX_O_MUX0 0x00000000 +#define ADI_4_AUX_O_MUX0 0x00000000 // Internal -#define ADI_4_AUX_O_MUX1 0x00000001 +#define ADI_4_AUX_O_MUX1 0x00000001 // Internal -#define ADI_4_AUX_O_MUX2 0x00000002 +#define ADI_4_AUX_O_MUX2 0x00000002 // Internal -#define ADI_4_AUX_O_MUX3 0x00000003 +#define ADI_4_AUX_O_MUX3 0x00000003 // Current Source -#define ADI_4_AUX_O_ISRC 0x00000004 +#define ADI_4_AUX_O_ISRC 0x00000004 // Comparator -#define ADI_4_AUX_O_COMP 0x00000005 +#define ADI_4_AUX_O_COMP 0x00000005 // Internal -#define ADI_4_AUX_O_MUX4 0x00000007 +#define ADI_4_AUX_O_MUX4 0x00000007 // ADC Control 0 -#define ADI_4_AUX_O_ADC0 0x00000008 +#define ADI_4_AUX_O_ADC0 0x00000008 // ADC Control 1 -#define ADI_4_AUX_O_ADC1 0x00000009 +#define ADI_4_AUX_O_ADC1 0x00000009 // ADC Reference 0 -#define ADI_4_AUX_O_ADCREF0 0x0000000A +#define ADI_4_AUX_O_ADCREF0 0x0000000A // ADC Reference 1 -#define ADI_4_AUX_O_ADCREF1 0x0000000B +#define ADI_4_AUX_O_ADCREF1 0x0000000B //***************************************************************************** // @@ -90,14 +90,14 @@ // VSS Internal. Only to be used through TI provided API. // DCOUPL Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX0_COMPA_REF_W 4 -#define ADI_4_AUX_MUX0_COMPA_REF_M 0x0000000F -#define ADI_4_AUX_MUX0_COMPA_REF_S 0 -#define ADI_4_AUX_MUX0_COMPA_REF_ADCVREFP 0x00000008 -#define ADI_4_AUX_MUX0_COMPA_REF_VDDS 0x00000004 -#define ADI_4_AUX_MUX0_COMPA_REF_VSS 0x00000002 -#define ADI_4_AUX_MUX0_COMPA_REF_DCOUPL 0x00000001 -#define ADI_4_AUX_MUX0_COMPA_REF_NC 0x00000000 +#define ADI_4_AUX_MUX0_COMPA_REF_W 4 +#define ADI_4_AUX_MUX0_COMPA_REF_M 0x0000000F +#define ADI_4_AUX_MUX0_COMPA_REF_S 0 +#define ADI_4_AUX_MUX0_COMPA_REF_ADCVREFP 0x00000008 +#define ADI_4_AUX_MUX0_COMPA_REF_VDDS 0x00000004 +#define ADI_4_AUX_MUX0_COMPA_REF_VSS 0x00000002 +#define ADI_4_AUX_MUX0_COMPA_REF_DCOUPL 0x00000001 +#define ADI_4_AUX_MUX0_COMPA_REF_NC 0x00000000 //***************************************************************************** // @@ -117,18 +117,18 @@ // AUXIO6 Internal. Only to be used through TI provided API. // AUXIO7 Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX1_COMPA_IN_W 8 -#define ADI_4_AUX_MUX1_COMPA_IN_M 0x000000FF -#define ADI_4_AUX_MUX1_COMPA_IN_S 0 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO0 0x00000080 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO1 0x00000040 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO2 0x00000020 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO3 0x00000010 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO4 0x00000008 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO5 0x00000004 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO6 0x00000002 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO7 0x00000001 -#define ADI_4_AUX_MUX1_COMPA_IN_NC 0x00000000 +#define ADI_4_AUX_MUX1_COMPA_IN_W 8 +#define ADI_4_AUX_MUX1_COMPA_IN_M 0x000000FF +#define ADI_4_AUX_MUX1_COMPA_IN_S 0 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO0 0x00000080 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO1 0x00000040 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO2 0x00000020 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO3 0x00000010 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO4 0x00000008 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO5 0x00000004 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO6 0x00000002 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO7 0x00000001 +#define ADI_4_AUX_MUX1_COMPA_IN_NC 0x00000000 //***************************************************************************** // @@ -145,15 +145,15 @@ // ATEST1 Internal. Only to be used through TI provided API. // ATEST0 Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_W 5 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_M 0x000000F8 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_S 3 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VDDS 0x00000080 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VSS 0x00000040 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_DCOUPL 0x00000020 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST1 0x00000010 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST0 0x00000008 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_NC 0x00000000 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_W 5 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_M 0x000000F8 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_S 3 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VDDS 0x00000080 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VSS 0x00000040 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_DCOUPL 0x00000020 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST1 0x00000010 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST0 0x00000008 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_NC 0x00000000 // Field: [2:0] COMPB_REF // @@ -163,13 +163,13 @@ // VSS Internal. Only to be used through TI provided API. // DCOUPL Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX2_COMPB_REF_W 3 -#define ADI_4_AUX_MUX2_COMPB_REF_M 0x00000007 -#define ADI_4_AUX_MUX2_COMPB_REF_S 0 -#define ADI_4_AUX_MUX2_COMPB_REF_VDDS 0x00000004 -#define ADI_4_AUX_MUX2_COMPB_REF_VSS 0x00000002 -#define ADI_4_AUX_MUX2_COMPB_REF_DCOUPL 0x00000001 -#define ADI_4_AUX_MUX2_COMPB_REF_NC 0x00000000 +#define ADI_4_AUX_MUX2_COMPB_REF_W 3 +#define ADI_4_AUX_MUX2_COMPB_REF_M 0x00000007 +#define ADI_4_AUX_MUX2_COMPB_REF_S 0 +#define ADI_4_AUX_MUX2_COMPB_REF_VDDS 0x00000004 +#define ADI_4_AUX_MUX2_COMPB_REF_VSS 0x00000002 +#define ADI_4_AUX_MUX2_COMPB_REF_DCOUPL 0x00000001 +#define ADI_4_AUX_MUX2_COMPB_REF_NC 0x00000000 //***************************************************************************** // @@ -189,18 +189,18 @@ // AUXIO6 Internal. Only to be used through TI provided API. // AUXIO7 Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_W 8 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_M 0x000000FF -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_S 0 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO0 0x00000080 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO1 0x00000040 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO2 0x00000020 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO3 0x00000010 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO4 0x00000008 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO5 0x00000004 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO6 0x00000002 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO7 0x00000001 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_NC 0x00000000 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_W 8 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_M 0x000000FF +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_S 0 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO0 0x00000080 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO1 0x00000040 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO2 0x00000020 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO3 0x00000010 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO4 0x00000008 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO5 0x00000004 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO6 0x00000002 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO7 0x00000001 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_NC 0x00000000 //***************************************************************************** // @@ -220,23 +220,23 @@ // 0P5U 0.5 uA // 0P25U 0.25 uA // NC No current connected -#define ADI_4_AUX_ISRC_TRIM_W 6 -#define ADI_4_AUX_ISRC_TRIM_M 0x000000FC -#define ADI_4_AUX_ISRC_TRIM_S 2 -#define ADI_4_AUX_ISRC_TRIM_11P75U 0x00000080 -#define ADI_4_AUX_ISRC_TRIM_4P5U 0x00000040 -#define ADI_4_AUX_ISRC_TRIM_2P0U 0x00000020 -#define ADI_4_AUX_ISRC_TRIM_1P0U 0x00000010 -#define ADI_4_AUX_ISRC_TRIM_0P5U 0x00000008 -#define ADI_4_AUX_ISRC_TRIM_0P25U 0x00000004 -#define ADI_4_AUX_ISRC_TRIM_NC 0x00000000 +#define ADI_4_AUX_ISRC_TRIM_W 6 +#define ADI_4_AUX_ISRC_TRIM_M 0x000000FC +#define ADI_4_AUX_ISRC_TRIM_S 2 +#define ADI_4_AUX_ISRC_TRIM_11P75U 0x00000080 +#define ADI_4_AUX_ISRC_TRIM_4P5U 0x00000040 +#define ADI_4_AUX_ISRC_TRIM_2P0U 0x00000020 +#define ADI_4_AUX_ISRC_TRIM_1P0U 0x00000010 +#define ADI_4_AUX_ISRC_TRIM_0P5U 0x00000008 +#define ADI_4_AUX_ISRC_TRIM_0P25U 0x00000004 +#define ADI_4_AUX_ISRC_TRIM_NC 0x00000000 // Field: [0] EN // // Current source enable -#define ADI_4_AUX_ISRC_EN 0x00000001 -#define ADI_4_AUX_ISRC_EN_M 0x00000001 -#define ADI_4_AUX_ISRC_EN_S 0 +#define ADI_4_AUX_ISRC_EN 0x00000001 +#define ADI_4_AUX_ISRC_EN_M 0x00000001 +#define ADI_4_AUX_ISRC_EN_S 0 //***************************************************************************** // @@ -247,18 +247,18 @@ // // Enables 400kohm resistance from COMPA reference node to ground. Used with // COMPA_REF_CURR_EN to generate voltage reference for cap-sense. -#define ADI_4_AUX_COMP_COMPA_REF_RES_EN 0x00000080 -#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_M 0x00000080 -#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_S 7 +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN 0x00000080 +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_M 0x00000080 +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_S 7 // Field: [6] COMPA_REF_CURR_EN // // Enables 2uA IPTAT current from ISRC to COMPA reference node. Requires // ISRC.EN = 1. Used with COMPA_REF_RES_EN to generate voltage reference for // cap-sense. -#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN 0x00000040 -#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_M 0x00000040 -#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_S 6 +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN 0x00000040 +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_M 0x00000040 +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_S 6 // Field: [5:3] COMPB_TRIM // @@ -268,27 +268,27 @@ // DIV3 Divide reference by 3 // DIV2 Divide reference by 2 // DIV1 No reference division -#define ADI_4_AUX_COMP_COMPB_TRIM_W 3 -#define ADI_4_AUX_COMP_COMPB_TRIM_M 0x00000038 -#define ADI_4_AUX_COMP_COMPB_TRIM_S 3 -#define ADI_4_AUX_COMP_COMPB_TRIM_DIV4 0x00000038 -#define ADI_4_AUX_COMP_COMPB_TRIM_DIV3 0x00000018 -#define ADI_4_AUX_COMP_COMPB_TRIM_DIV2 0x00000008 -#define ADI_4_AUX_COMP_COMPB_TRIM_DIV1 0x00000000 +#define ADI_4_AUX_COMP_COMPB_TRIM_W 3 +#define ADI_4_AUX_COMP_COMPB_TRIM_M 0x00000038 +#define ADI_4_AUX_COMP_COMPB_TRIM_S 3 +#define ADI_4_AUX_COMP_COMPB_TRIM_DIV4 0x00000038 +#define ADI_4_AUX_COMP_COMPB_TRIM_DIV3 0x00000018 +#define ADI_4_AUX_COMP_COMPB_TRIM_DIV2 0x00000008 +#define ADI_4_AUX_COMP_COMPB_TRIM_DIV1 0x00000000 // Field: [2] COMPB_EN // // COMPB enable -#define ADI_4_AUX_COMP_COMPB_EN 0x00000004 -#define ADI_4_AUX_COMP_COMPB_EN_M 0x00000004 -#define ADI_4_AUX_COMP_COMPB_EN_S 2 +#define ADI_4_AUX_COMP_COMPB_EN 0x00000004 +#define ADI_4_AUX_COMP_COMPB_EN_M 0x00000004 +#define ADI_4_AUX_COMP_COMPB_EN_S 2 // Field: [0] COMPA_EN // // COMPA enable -#define ADI_4_AUX_COMP_COMPA_EN 0x00000001 -#define ADI_4_AUX_COMP_COMPA_EN_M 0x00000001 -#define ADI_4_AUX_COMP_COMPA_EN_S 0 +#define ADI_4_AUX_COMP_COMPA_EN 0x00000001 +#define ADI_4_AUX_COMP_COMPA_EN_M 0x00000001 +#define ADI_4_AUX_COMP_COMPA_EN_S 0 //***************************************************************************** // @@ -308,18 +308,18 @@ // AUXIO6 Internal. Only to be used through TI provided API. // AUXIO7 Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX4_COMPA_REF_W 8 -#define ADI_4_AUX_MUX4_COMPA_REF_M 0x000000FF -#define ADI_4_AUX_MUX4_COMPA_REF_S 0 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO0 0x00000080 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO1 0x00000040 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO2 0x00000020 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO3 0x00000010 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO4 0x00000008 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO5 0x00000004 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO6 0x00000002 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO7 0x00000001 -#define ADI_4_AUX_MUX4_COMPA_REF_NC 0x00000000 +#define ADI_4_AUX_MUX4_COMPA_REF_W 8 +#define ADI_4_AUX_MUX4_COMPA_REF_M 0x000000FF +#define ADI_4_AUX_MUX4_COMPA_REF_S 0 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO0 0x00000080 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO1 0x00000040 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO2 0x00000020 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO3 0x00000010 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO4 0x00000008 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO5 0x00000004 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO6 0x00000002 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO7 0x00000001 +#define ADI_4_AUX_MUX4_COMPA_REF_NC 0x00000000 //***************************************************************************** // @@ -345,9 +345,9 @@ // signal. Sampling restarts when the conversion has finished. // Asynchronous mode is useful when it is important to avoid jitter in the // sampling instant of an externally driven signal -#define ADI_4_AUX_ADC0_SMPL_MODE 0x00000080 -#define ADI_4_AUX_ADC0_SMPL_MODE_M 0x00000080 -#define ADI_4_AUX_ADC0_SMPL_MODE_S 7 +#define ADI_4_AUX_ADC0_SMPL_MODE 0x00000080 +#define ADI_4_AUX_ADC0_SMPL_MODE_M 0x00000080 +#define ADI_4_AUX_ADC0_SMPL_MODE_S 7 // Field: [6:3] SMPL_CYCLE_EXP // @@ -368,22 +368,22 @@ // 10P6_US 64x 6 MHz clock periods = 10.6us // 5P3_US 32x 6 MHz clock periods = 5.3us // 2P7_US 16x 6 MHz clock periods = 2.7us -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_W 4 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M 0x00000078 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S 3 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P9_MS 0x00000078 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P46_MS 0x00000070 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P73_MS 0x00000068 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_1P37_MS 0x00000060 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_682_US 0x00000058 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_341_US 0x00000050 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_170_US 0x00000048 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_85P3_US 0x00000040 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_42P6_US 0x00000038 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_21P3_US 0x00000030 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P6_US 0x00000028 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P3_US 0x00000020 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P7_US 0x00000018 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_W 4 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M 0x00000078 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S 3 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P9_MS 0x00000078 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P46_MS 0x00000070 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P73_MS 0x00000068 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_1P37_MS 0x00000060 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_682_US 0x00000058 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_341_US 0x00000050 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_170_US 0x00000048 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_85P3_US 0x00000040 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_42P6_US 0x00000038 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_21P3_US 0x00000030 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P6_US 0x00000028 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P3_US 0x00000020 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P7_US 0x00000018 // Field: [1] RESET_N // @@ -392,9 +392,9 @@ // // 0: Reset // 1: Normal operation -#define ADI_4_AUX_ADC0_RESET_N 0x00000002 -#define ADI_4_AUX_ADC0_RESET_N_M 0x00000002 -#define ADI_4_AUX_ADC0_RESET_N_S 1 +#define ADI_4_AUX_ADC0_RESET_N 0x00000002 +#define ADI_4_AUX_ADC0_RESET_N_M 0x00000002 +#define ADI_4_AUX_ADC0_RESET_N_S 1 // Field: [0] EN // @@ -402,9 +402,9 @@ // // 0: Disable // 1: Enable -#define ADI_4_AUX_ADC0_EN 0x00000001 -#define ADI_4_AUX_ADC0_EN_M 0x00000001 -#define ADI_4_AUX_ADC0_EN_S 0 +#define ADI_4_AUX_ADC0_EN 0x00000001 +#define ADI_4_AUX_ADC0_EN_M 0x00000001 +#define ADI_4_AUX_ADC0_EN_S 0 //***************************************************************************** // @@ -414,9 +414,9 @@ // Field: [0] SCALE_DIS // // Internal. Only to be used through TI provided API. -#define ADI_4_AUX_ADC1_SCALE_DIS 0x00000001 -#define ADI_4_AUX_ADC1_SCALE_DIS_M 0x00000001 -#define ADI_4_AUX_ADC1_SCALE_DIS_S 0 +#define ADI_4_AUX_ADC1_SCALE_DIS 0x00000001 +#define ADI_4_AUX_ADC1_SCALE_DIS_M 0x00000001 +#define ADI_4_AUX_ADC1_SCALE_DIS_S 0 //***************************************************************************** // @@ -428,23 +428,23 @@ // Keep ADCREF powered up in IDLE state when ADC0.SMPL_MODE = 0. // // Set to 1 if ADC0.SMPL_CYCLE_EXP is less than 6 (21.3us sampling time) -#define ADI_4_AUX_ADCREF0_REF_ON_IDLE 0x00000040 -#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_M 0x00000040 -#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_S 6 +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE 0x00000040 +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_M 0x00000040 +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_S 6 // Field: [5] IOMUX // // Internal. Only to be used through TI provided API. -#define ADI_4_AUX_ADCREF0_IOMUX 0x00000020 -#define ADI_4_AUX_ADCREF0_IOMUX_M 0x00000020 -#define ADI_4_AUX_ADCREF0_IOMUX_S 5 +#define ADI_4_AUX_ADCREF0_IOMUX 0x00000020 +#define ADI_4_AUX_ADCREF0_IOMUX_M 0x00000020 +#define ADI_4_AUX_ADCREF0_IOMUX_S 5 // Field: [4] EXT // // Internal. Only to be used through TI provided API. -#define ADI_4_AUX_ADCREF0_EXT 0x00000010 -#define ADI_4_AUX_ADCREF0_EXT_M 0x00000010 -#define ADI_4_AUX_ADCREF0_EXT_S 4 +#define ADI_4_AUX_ADCREF0_EXT 0x00000010 +#define ADI_4_AUX_ADCREF0_EXT_M 0x00000010 +#define ADI_4_AUX_ADCREF0_EXT_S 4 // Field: [3] SRC // @@ -452,9 +452,9 @@ // // 0: Fixed reference = 4.3V // 1: Relative reference = VDDS -#define ADI_4_AUX_ADCREF0_SRC 0x00000008 -#define ADI_4_AUX_ADCREF0_SRC_M 0x00000008 -#define ADI_4_AUX_ADCREF0_SRC_S 3 +#define ADI_4_AUX_ADCREF0_SRC 0x00000008 +#define ADI_4_AUX_ADCREF0_SRC_M 0x00000008 +#define ADI_4_AUX_ADCREF0_SRC_S 3 // Field: [0] EN // @@ -462,9 +462,9 @@ // // 0: ADC reference module powered down // 1: ADC reference module enabled -#define ADI_4_AUX_ADCREF0_EN 0x00000001 -#define ADI_4_AUX_ADCREF0_EN_M 0x00000001 -#define ADI_4_AUX_ADCREF0_EN_S 0 +#define ADI_4_AUX_ADCREF0_EN 0x00000001 +#define ADI_4_AUX_ADCREF0_EN_M 0x00000001 +#define ADI_4_AUX_ADCREF0_EN_S 0 //***************************************************************************** // @@ -482,9 +482,8 @@ // 0x3F - nominal - 0.4% 1.425V // 0x1F - maximum voltage 1.6V // 0x20 - minimum voltage 1.3V -#define ADI_4_AUX_ADCREF1_VTRIM_W 6 -#define ADI_4_AUX_ADCREF1_VTRIM_M 0x0000003F -#define ADI_4_AUX_ADCREF1_VTRIM_S 0 - +#define ADI_4_AUX_ADCREF1_VTRIM_W 6 +#define ADI_4_AUX_ADCREF1_VTRIM_M 0x0000003F +#define ADI_4_AUX_ADCREF1_VTRIM_S 0 #endif // __ADI_4_AUX__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_batmon.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_batmon.h index f09256d..a167301 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_batmon.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_batmon.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aon_batmon_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aon_batmon_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AON_BATMON_H__ #define __HW_AON_BATMON_H__ @@ -44,43 +44,43 @@ // //***************************************************************************** // Internal -#define AON_BATMON_O_CTL 0x00000000 +#define AON_BATMON_O_CTL 0x00000000 // Internal -#define AON_BATMON_O_MEASCFG 0x00000004 +#define AON_BATMON_O_MEASCFG 0x00000004 // Internal -#define AON_BATMON_O_TEMPP0 0x0000000C +#define AON_BATMON_O_TEMPP0 0x0000000C // Internal -#define AON_BATMON_O_TEMPP1 0x00000010 +#define AON_BATMON_O_TEMPP1 0x00000010 // Internal -#define AON_BATMON_O_TEMPP2 0x00000014 +#define AON_BATMON_O_TEMPP2 0x00000014 // Internal -#define AON_BATMON_O_BATMONP0 0x00000018 +#define AON_BATMON_O_BATMONP0 0x00000018 // Internal -#define AON_BATMON_O_BATMONP1 0x0000001C +#define AON_BATMON_O_BATMONP1 0x0000001C // Internal -#define AON_BATMON_O_IOSTRP0 0x00000020 +#define AON_BATMON_O_IOSTRP0 0x00000020 // Internal -#define AON_BATMON_O_FLASHPUMPP0 0x00000024 +#define AON_BATMON_O_FLASHPUMPP0 0x00000024 // Last Measured Battery Voltage -#define AON_BATMON_O_BAT 0x00000028 +#define AON_BATMON_O_BAT 0x00000028 // Battery Update -#define AON_BATMON_O_BATUPD 0x0000002C +#define AON_BATMON_O_BATUPD 0x0000002C // Temperature -#define AON_BATMON_O_TEMP 0x00000030 +#define AON_BATMON_O_TEMP 0x00000030 // Temperature Update -#define AON_BATMON_O_TEMPUPD 0x00000034 +#define AON_BATMON_O_TEMPUPD 0x00000034 //***************************************************************************** // @@ -90,18 +90,18 @@ // Field: [1] CALC_EN // // Internal. Only to be used through TI provided API. -#define AON_BATMON_CTL_CALC_EN 0x00000002 -#define AON_BATMON_CTL_CALC_EN_BITN 1 -#define AON_BATMON_CTL_CALC_EN_M 0x00000002 -#define AON_BATMON_CTL_CALC_EN_S 1 +#define AON_BATMON_CTL_CALC_EN 0x00000002 +#define AON_BATMON_CTL_CALC_EN_BITN 1 +#define AON_BATMON_CTL_CALC_EN_M 0x00000002 +#define AON_BATMON_CTL_CALC_EN_S 1 // Field: [0] MEAS_EN // // Internal. Only to be used through TI provided API. -#define AON_BATMON_CTL_MEAS_EN 0x00000001 -#define AON_BATMON_CTL_MEAS_EN_BITN 0 -#define AON_BATMON_CTL_MEAS_EN_M 0x00000001 -#define AON_BATMON_CTL_MEAS_EN_S 0 +#define AON_BATMON_CTL_MEAS_EN 0x00000001 +#define AON_BATMON_CTL_MEAS_EN_BITN 0 +#define AON_BATMON_CTL_MEAS_EN_M 0x00000001 +#define AON_BATMON_CTL_MEAS_EN_S 0 //***************************************************************************** // @@ -116,13 +116,13 @@ // 16CYC Internal. Only to be used through TI provided API. // 8CYC Internal. Only to be used through TI provided API. // CONT Internal. Only to be used through TI provided API. -#define AON_BATMON_MEASCFG_PER_W 2 -#define AON_BATMON_MEASCFG_PER_M 0x00000003 -#define AON_BATMON_MEASCFG_PER_S 0 -#define AON_BATMON_MEASCFG_PER_32CYC 0x00000003 -#define AON_BATMON_MEASCFG_PER_16CYC 0x00000002 -#define AON_BATMON_MEASCFG_PER_8CYC 0x00000001 -#define AON_BATMON_MEASCFG_PER_CONT 0x00000000 +#define AON_BATMON_MEASCFG_PER_W 2 +#define AON_BATMON_MEASCFG_PER_M 0x00000003 +#define AON_BATMON_MEASCFG_PER_S 0 +#define AON_BATMON_MEASCFG_PER_32CYC 0x00000003 +#define AON_BATMON_MEASCFG_PER_16CYC 0x00000002 +#define AON_BATMON_MEASCFG_PER_8CYC 0x00000001 +#define AON_BATMON_MEASCFG_PER_CONT 0x00000000 //***************************************************************************** // @@ -132,9 +132,9 @@ // Field: [7:0] CFG // // Internal. Only to be used through TI provided API. -#define AON_BATMON_TEMPP0_CFG_W 8 -#define AON_BATMON_TEMPP0_CFG_M 0x000000FF -#define AON_BATMON_TEMPP0_CFG_S 0 +#define AON_BATMON_TEMPP0_CFG_W 8 +#define AON_BATMON_TEMPP0_CFG_M 0x000000FF +#define AON_BATMON_TEMPP0_CFG_S 0 //***************************************************************************** // @@ -144,9 +144,9 @@ // Field: [5:0] CFG // // Internal. Only to be used through TI provided API. -#define AON_BATMON_TEMPP1_CFG_W 6 -#define AON_BATMON_TEMPP1_CFG_M 0x0000003F -#define AON_BATMON_TEMPP1_CFG_S 0 +#define AON_BATMON_TEMPP1_CFG_W 6 +#define AON_BATMON_TEMPP1_CFG_M 0x0000003F +#define AON_BATMON_TEMPP1_CFG_S 0 //***************************************************************************** // @@ -156,9 +156,9 @@ // Field: [4:0] CFG // // Internal. Only to be used through TI provided API. -#define AON_BATMON_TEMPP2_CFG_W 5 -#define AON_BATMON_TEMPP2_CFG_M 0x0000001F -#define AON_BATMON_TEMPP2_CFG_S 0 +#define AON_BATMON_TEMPP2_CFG_W 5 +#define AON_BATMON_TEMPP2_CFG_M 0x0000001F +#define AON_BATMON_TEMPP2_CFG_S 0 //***************************************************************************** // @@ -168,9 +168,9 @@ // Field: [5:0] CFG // // Internal. Only to be used through TI provided API. -#define AON_BATMON_BATMONP0_CFG_W 6 -#define AON_BATMON_BATMONP0_CFG_M 0x0000003F -#define AON_BATMON_BATMONP0_CFG_S 0 +#define AON_BATMON_BATMONP0_CFG_W 6 +#define AON_BATMON_BATMONP0_CFG_M 0x0000003F +#define AON_BATMON_BATMONP0_CFG_S 0 //***************************************************************************** // @@ -180,9 +180,9 @@ // Field: [5:0] CFG // // Internal. Only to be used through TI provided API. -#define AON_BATMON_BATMONP1_CFG_W 6 -#define AON_BATMON_BATMONP1_CFG_M 0x0000003F -#define AON_BATMON_BATMONP1_CFG_S 0 +#define AON_BATMON_BATMONP1_CFG_W 6 +#define AON_BATMON_BATMONP1_CFG_M 0x0000003F +#define AON_BATMON_BATMONP1_CFG_S 0 //***************************************************************************** // @@ -192,16 +192,16 @@ // Field: [5:4] CFG2 // // Internal. Only to be used through TI provided API. -#define AON_BATMON_IOSTRP0_CFG2_W 2 -#define AON_BATMON_IOSTRP0_CFG2_M 0x00000030 -#define AON_BATMON_IOSTRP0_CFG2_S 4 +#define AON_BATMON_IOSTRP0_CFG2_W 2 +#define AON_BATMON_IOSTRP0_CFG2_M 0x00000030 +#define AON_BATMON_IOSTRP0_CFG2_S 4 // Field: [3:0] CFG1 // // Internal. Only to be used through TI provided API. -#define AON_BATMON_IOSTRP0_CFG1_W 4 -#define AON_BATMON_IOSTRP0_CFG1_M 0x0000000F -#define AON_BATMON_IOSTRP0_CFG1_S 0 +#define AON_BATMON_IOSTRP0_CFG1_W 4 +#define AON_BATMON_IOSTRP0_CFG1_M 0x0000000F +#define AON_BATMON_IOSTRP0_CFG1_S 0 //***************************************************************************** // @@ -211,40 +211,40 @@ // Field: [8] FALLB // // Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_FALLB 0x00000100 -#define AON_BATMON_FLASHPUMPP0_FALLB_BITN 8 -#define AON_BATMON_FLASHPUMPP0_FALLB_M 0x00000100 -#define AON_BATMON_FLASHPUMPP0_FALLB_S 8 +#define AON_BATMON_FLASHPUMPP0_FALLB 0x00000100 +#define AON_BATMON_FLASHPUMPP0_FALLB_BITN 8 +#define AON_BATMON_FLASHPUMPP0_FALLB_M 0x00000100 +#define AON_BATMON_FLASHPUMPP0_FALLB_S 8 // Field: [7:6] HIGHLIM // // Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_HIGHLIM_W 2 -#define AON_BATMON_FLASHPUMPP0_HIGHLIM_M 0x000000C0 -#define AON_BATMON_FLASHPUMPP0_HIGHLIM_S 6 +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_W 2 +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_M 0x000000C0 +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_S 6 // Field: [5] LOWLIM // // Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_LOWLIM 0x00000020 -#define AON_BATMON_FLASHPUMPP0_LOWLIM_BITN 5 -#define AON_BATMON_FLASHPUMPP0_LOWLIM_M 0x00000020 -#define AON_BATMON_FLASHPUMPP0_LOWLIM_S 5 +#define AON_BATMON_FLASHPUMPP0_LOWLIM 0x00000020 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_BITN 5 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_M 0x00000020 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_S 5 // Field: [4] OVR // // Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_OVR 0x00000010 -#define AON_BATMON_FLASHPUMPP0_OVR_BITN 4 -#define AON_BATMON_FLASHPUMPP0_OVR_M 0x00000010 -#define AON_BATMON_FLASHPUMPP0_OVR_S 4 +#define AON_BATMON_FLASHPUMPP0_OVR 0x00000010 +#define AON_BATMON_FLASHPUMPP0_OVR_BITN 4 +#define AON_BATMON_FLASHPUMPP0_OVR_M 0x00000010 +#define AON_BATMON_FLASHPUMPP0_OVR_S 4 // Field: [3:0] CFG // // Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_CFG_W 4 -#define AON_BATMON_FLASHPUMPP0_CFG_M 0x0000000F -#define AON_BATMON_FLASHPUMPP0_CFG_S 0 +#define AON_BATMON_FLASHPUMPP0_CFG_W 4 +#define AON_BATMON_FLASHPUMPP0_CFG_M 0x0000000F +#define AON_BATMON_FLASHPUMPP0_CFG_S 0 //***************************************************************************** // @@ -259,9 +259,9 @@ // ... // 0x3: 3V + fractional part // 0x4: 4V + fractional part -#define AON_BATMON_BAT_INT_W 3 -#define AON_BATMON_BAT_INT_M 0x00000700 -#define AON_BATMON_BAT_INT_S 8 +#define AON_BATMON_BAT_INT_W 3 +#define AON_BATMON_BAT_INT_M 0x00000700 +#define AON_BATMON_BAT_INT_S 8 // Field: [7:0] FRAC // @@ -276,9 +276,9 @@ // 0xA0: 1/2 + 1/8 = .625V // ... // 0xFF: Max -#define AON_BATMON_BAT_FRAC_W 8 -#define AON_BATMON_BAT_FRAC_M 0x000000FF -#define AON_BATMON_BAT_FRAC_S 0 +#define AON_BATMON_BAT_FRAC_W 8 +#define AON_BATMON_BAT_FRAC_M 0x000000FF +#define AON_BATMON_BAT_FRAC_S 0 //***************************************************************************** // @@ -292,10 +292,10 @@ // 1: New battery voltage is present. // // Write 1 to clear the status. -#define AON_BATMON_BATUPD_STAT 0x00000001 -#define AON_BATMON_BATUPD_STAT_BITN 0 -#define AON_BATMON_BATUPD_STAT_M 0x00000001 -#define AON_BATMON_BATUPD_STAT_S 0 +#define AON_BATMON_BATUPD_STAT 0x00000001 +#define AON_BATMON_BATUPD_STAT_BITN 0 +#define AON_BATMON_BATUPD_STAT_M 0x00000001 +#define AON_BATMON_BATUPD_STAT_S 0 //***************************************************************************** // @@ -315,9 +315,9 @@ // 0x1B: 27C // 0x55: 85C // 0xFF: Max value -#define AON_BATMON_TEMP_INT_W 9 -#define AON_BATMON_TEMP_INT_M 0x0001FF00 -#define AON_BATMON_TEMP_INT_S 8 +#define AON_BATMON_TEMP_INT_W 9 +#define AON_BATMON_TEMP_INT_M 0x0001FF00 +#define AON_BATMON_TEMP_INT_S 8 //***************************************************************************** // @@ -331,10 +331,9 @@ // 1: New temperature is present. // // Write 1 to clear the status. -#define AON_BATMON_TEMPUPD_STAT 0x00000001 -#define AON_BATMON_TEMPUPD_STAT_BITN 0 -#define AON_BATMON_TEMPUPD_STAT_M 0x00000001 -#define AON_BATMON_TEMPUPD_STAT_S 0 - +#define AON_BATMON_TEMPUPD_STAT 0x00000001 +#define AON_BATMON_TEMPUPD_STAT_BITN 0 +#define AON_BATMON_TEMPUPD_STAT_M 0x00000001 +#define AON_BATMON_TEMPUPD_STAT_S 0 #endif // __AON_BATMON__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_event.h index 2896b81..1ea66b9 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_event.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_event.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aon_event_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aon_event_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AON_EVENT_H__ #define __HW_AON_EVENT_H__ @@ -44,16 +44,16 @@ // //***************************************************************************** // Wake-up Selector For MCU -#define AON_EVENT_O_MCUWUSEL 0x00000000 +#define AON_EVENT_O_MCUWUSEL 0x00000000 // Wake-up Selector For AUX -#define AON_EVENT_O_AUXWUSEL 0x00000004 +#define AON_EVENT_O_AUXWUSEL 0x00000004 // Event Selector For MCU Event Fabric -#define AON_EVENT_O_EVTOMCUSEL 0x00000008 +#define AON_EVENT_O_EVTOMCUSEL 0x00000008 // RTC Capture Event Selector For AON_RTC -#define AON_EVENT_O_RTCSEL 0x0000000C +#define AON_EVENT_O_RTCSEL 0x0000000C //***************************************************************************** // @@ -133,65 +133,65 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_MCUWUSEL_WU3_EV_W 6 -#define AON_EVENT_MCUWUSEL_WU3_EV_M 0x3F000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_S 24 -#define AON_EVENT_MCUWUSEL_WU3_EV_NONE 0x3F000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC_N 0x38000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC 0x37000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_VOLT 0x36000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP 0x35000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER1_EV 0x34000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER0_EV 0x33000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TDC_DONE 0x32000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_ADC_DONE 0x31000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB 0x30000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPA 0x2F000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV2 0x2E000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV1 0x2D000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV0 0x2C000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_JTAG 0x2B000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_UPD 0x2A000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_COMB_DLY 0x29000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2_DLY 0x28000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1_DLY 0x27000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0_DLY 0x26000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2 0x25000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1 0x24000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0 0x23000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD 0x20000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD31 0x1F000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD30 0x1E000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD29 0x1D000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD28 0x1C000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD27 0x1B000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD26 0x1A000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD25 0x19000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD24 0x18000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD23 0x17000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD22 0x16000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD21 0x15000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD20 0x14000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD19 0x13000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD18 0x12000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD17 0x11000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD16 0x10000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD15 0x0F000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD14 0x0E000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD13 0x0D000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD12 0x0C000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD11 0x0B000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD10 0x0A000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD9 0x09000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD8 0x08000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD7 0x07000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD6 0x06000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD5 0x05000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD4 0x04000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD3 0x03000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD2 0x02000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD1 0x01000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD0 0x00000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU3_EV_M 0x3F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_S 24 +#define AON_EVENT_MCUWUSEL_WU3_EV_NONE 0x3F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC_N 0x38000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC 0x37000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_VOLT 0x36000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP 0x35000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER1_EV 0x34000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER0_EV 0x33000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TDC_DONE 0x32000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_ADC_DONE 0x31000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB 0x30000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPA 0x2F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV2 0x2E000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV1 0x2D000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV0 0x2C000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_JTAG 0x2B000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_UPD 0x2A000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_COMB_DLY 0x29000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2_DLY 0x28000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1_DLY 0x27000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0_DLY 0x26000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2 0x25000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1 0x24000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0 0x23000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD 0x20000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD31 0x1F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD30 0x1E000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD29 0x1D000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD28 0x1C000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD27 0x1B000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD26 0x1A000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD25 0x19000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD24 0x18000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD23 0x17000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD22 0x16000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD21 0x15000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD20 0x14000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD19 0x13000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD18 0x12000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD17 0x11000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD16 0x10000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD15 0x0F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD14 0x0E000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD13 0x0D000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD12 0x0C000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD11 0x0B000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD10 0x0A000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD9 0x09000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD8 0x08000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD7 0x07000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD6 0x06000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD5 0x05000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD4 0x04000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD3 0x03000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD2 0x02000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD1 0x01000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD0 0x00000000 // Field: [21:16] WU2_EV // @@ -266,65 +266,65 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_MCUWUSEL_WU2_EV_W 6 -#define AON_EVENT_MCUWUSEL_WU2_EV_M 0x003F0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_S 16 -#define AON_EVENT_MCUWUSEL_WU2_EV_NONE 0x003F0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000 -#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_VOLT 0x00360000 -#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP 0x00350000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB 0x00300000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPA 0x002F0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV2 0x002E0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV1 0x002D0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV0 0x002C0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_JTAG 0x002B0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_UPD 0x002A0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2 0x00250000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1 0x00240000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0 0x00230000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD 0x00200000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD31 0x001F0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD30 0x001E0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD29 0x001D0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD28 0x001C0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD27 0x001B0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD26 0x001A0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD25 0x00190000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD24 0x00180000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD23 0x00170000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD22 0x00160000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD21 0x00150000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD20 0x00140000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD19 0x00130000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD18 0x00120000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD17 0x00110000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD16 0x00100000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD15 0x000F0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD14 0x000E0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD13 0x000D0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD12 0x000C0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD11 0x000B0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD10 0x000A0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD9 0x00090000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD8 0x00080000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD7 0x00070000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD6 0x00060000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD5 0x00050000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD4 0x00040000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD3 0x00030000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD2 0x00020000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD1 0x00010000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD0 0x00000000 +#define AON_EVENT_MCUWUSEL_WU2_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU2_EV_M 0x003F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_S 16 +#define AON_EVENT_MCUWUSEL_WU2_EV_NONE 0x003F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_JTAG 0x002B0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2 0x00250000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1 0x00240000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0 0x00230000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD 0x00200000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD31 0x001F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD30 0x001E0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD29 0x001D0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD28 0x001C0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD27 0x001B0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD26 0x001A0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD25 0x00190000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD24 0x00180000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD23 0x00170000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD22 0x00160000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD21 0x00150000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD20 0x00140000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD19 0x00130000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD18 0x00120000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD17 0x00110000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD16 0x00100000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD15 0x000F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD14 0x000E0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD13 0x000D0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD12 0x000C0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD11 0x000B0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD10 0x000A0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD9 0x00090000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD8 0x00080000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD7 0x00070000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD6 0x00060000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD5 0x00050000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD4 0x00040000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD3 0x00030000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD2 0x00020000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD1 0x00010000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD0 0x00000000 // Field: [13:8] WU1_EV // @@ -399,65 +399,65 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_MCUWUSEL_WU1_EV_W 6 -#define AON_EVENT_MCUWUSEL_WU1_EV_M 0x00003F00 -#define AON_EVENT_MCUWUSEL_WU1_EV_S 8 -#define AON_EVENT_MCUWUSEL_WU1_EV_NONE 0x00003F00 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700 -#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_VOLT 0x00003600 -#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP 0x00003500 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB 0x00003000 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPA 0x00002F00 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV2 0x00002E00 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV1 0x00002D00 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV0 0x00002C00 -#define AON_EVENT_MCUWUSEL_WU1_EV_JTAG 0x00002B00 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_UPD 0x00002A00 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2 0x00002500 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1 0x00002400 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0 0x00002300 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD 0x00002000 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD31 0x00001F00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD30 0x00001E00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD29 0x00001D00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD28 0x00001C00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD27 0x00001B00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD26 0x00001A00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD25 0x00001900 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD24 0x00001800 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD23 0x00001700 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD22 0x00001600 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD21 0x00001500 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD20 0x00001400 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD19 0x00001300 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD18 0x00001200 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD17 0x00001100 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD16 0x00001000 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD15 0x00000F00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD14 0x00000E00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD13 0x00000D00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD12 0x00000C00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD11 0x00000B00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD10 0x00000A00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD9 0x00000900 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD8 0x00000800 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD7 0x00000700 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD6 0x00000600 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD5 0x00000500 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD4 0x00000400 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD3 0x00000300 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD2 0x00000200 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD1 0x00000100 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD0 0x00000000 +#define AON_EVENT_MCUWUSEL_WU1_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU1_EV_M 0x00003F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_S 8 +#define AON_EVENT_MCUWUSEL_WU1_EV_NONE 0x00003F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_MCUWUSEL_WU1_EV_JTAG 0x00002B00 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2 0x00002500 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1 0x00002400 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0 0x00002300 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD 0x00002000 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD31 0x00001F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD30 0x00001E00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD29 0x00001D00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD28 0x00001C00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD27 0x00001B00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD26 0x00001A00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD25 0x00001900 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD24 0x00001800 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD23 0x00001700 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD22 0x00001600 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD21 0x00001500 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD20 0x00001400 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD19 0x00001300 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD18 0x00001200 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD17 0x00001100 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD16 0x00001000 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD15 0x00000F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD14 0x00000E00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD13 0x00000D00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD12 0x00000C00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD11 0x00000B00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD10 0x00000A00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD9 0x00000900 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD8 0x00000800 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD7 0x00000700 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD6 0x00000600 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD5 0x00000500 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD4 0x00000400 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD3 0x00000300 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD2 0x00000200 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD1 0x00000100 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD0 0x00000000 // Field: [5:0] WU0_EV // @@ -532,65 +532,65 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_MCUWUSEL_WU0_EV_W 6 -#define AON_EVENT_MCUWUSEL_WU0_EV_M 0x0000003F -#define AON_EVENT_MCUWUSEL_WU0_EV_S 0 -#define AON_EVENT_MCUWUSEL_WU0_EV_NONE 0x0000003F -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037 -#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_VOLT 0x00000036 -#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP 0x00000035 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB 0x00000030 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPA 0x0000002F -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV2 0x0000002E -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV1 0x0000002D -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV0 0x0000002C -#define AON_EVENT_MCUWUSEL_WU0_EV_JTAG 0x0000002B -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_UPD 0x0000002A -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2 0x00000025 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1 0x00000024 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0 0x00000023 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD 0x00000020 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD31 0x0000001F -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD30 0x0000001E -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD29 0x0000001D -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD28 0x0000001C -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD27 0x0000001B -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD26 0x0000001A -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD25 0x00000019 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD24 0x00000018 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD23 0x00000017 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD22 0x00000016 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD21 0x00000015 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD20 0x00000014 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD19 0x00000013 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD18 0x00000012 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD17 0x00000011 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD16 0x00000010 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD15 0x0000000F -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD14 0x0000000E -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD13 0x0000000D -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD12 0x0000000C -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD11 0x0000000B -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD10 0x0000000A -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD9 0x00000009 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD8 0x00000008 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD7 0x00000007 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD6 0x00000006 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD5 0x00000005 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD4 0x00000004 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD3 0x00000003 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD2 0x00000002 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD1 0x00000001 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD0 0x00000000 +#define AON_EVENT_MCUWUSEL_WU0_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU0_EV_M 0x0000003F +#define AON_EVENT_MCUWUSEL_WU0_EV_S 0 +#define AON_EVENT_MCUWUSEL_WU0_EV_NONE 0x0000003F +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_MCUWUSEL_WU0_EV_JTAG 0x0000002B +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_UPD 0x0000002A +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2 0x00000025 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1 0x00000024 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0 0x00000023 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD 0x00000020 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD31 0x0000001F +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD30 0x0000001E +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD29 0x0000001D +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD28 0x0000001C +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD27 0x0000001B +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD26 0x0000001A +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD25 0x00000019 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD24 0x00000018 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD23 0x00000017 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD22 0x00000016 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD21 0x00000015 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD20 0x00000014 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD19 0x00000013 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD18 0x00000012 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD17 0x00000011 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD16 0x00000010 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD15 0x0000000F +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD14 0x0000000E +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD13 0x0000000D +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD12 0x0000000C +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD11 0x0000000B +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD10 0x0000000A +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD9 0x00000009 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD8 0x00000008 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD7 0x00000007 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD6 0x00000006 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD5 0x00000005 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD4 0x00000004 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD3 0x00000003 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD2 0x00000002 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD1 0x00000001 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD0 0x00000000 //***************************************************************************** // @@ -670,65 +670,65 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_AUXWUSEL_WU2_EV_W 6 -#define AON_EVENT_AUXWUSEL_WU2_EV_M 0x003F0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_S 16 -#define AON_EVENT_AUXWUSEL_WU2_EV_NONE 0x003F0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000 -#define AON_EVENT_AUXWUSEL_WU2_EV_BATMON_VOLT 0x00360000 -#define AON_EVENT_AUXWUSEL_WU2_EV_BATMON_TEMP 0x00350000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB 0x00300000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPA 0x002F0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV2 0x002E0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV1 0x002D0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV0 0x002C0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_JTAG 0x002B0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_UPD 0x002A0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH2 0x00250000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH1 0x00240000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH0 0x00230000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD 0x00200000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD31 0x001F0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD30 0x001E0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD29 0x001D0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD28 0x001C0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD27 0x001B0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD26 0x001A0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD25 0x00190000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD24 0x00180000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD23 0x00170000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD22 0x00160000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD21 0x00150000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD20 0x00140000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD19 0x00130000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD18 0x00120000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD17 0x00110000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD16 0x00100000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD15 0x000F0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD14 0x000E0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD13 0x000D0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD12 0x000C0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD11 0x000B0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD10 0x000A0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD9 0x00090000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD8 0x00080000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD7 0x00070000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD6 0x00060000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD5 0x00050000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD4 0x00040000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD3 0x00030000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD2 0x00020000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD1 0x00010000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD0 0x00000000 +#define AON_EVENT_AUXWUSEL_WU2_EV_W 6 +#define AON_EVENT_AUXWUSEL_WU2_EV_M 0x003F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_S 16 +#define AON_EVENT_AUXWUSEL_WU2_EV_NONE 0x003F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_AUXWUSEL_WU2_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_AUXWUSEL_WU2_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_JTAG 0x002B0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH2 0x00250000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH1 0x00240000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH0 0x00230000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD 0x00200000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD31 0x001F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD30 0x001E0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD29 0x001D0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD28 0x001C0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD27 0x001B0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD26 0x001A0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD25 0x00190000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD24 0x00180000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD23 0x00170000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD22 0x00160000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD21 0x00150000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD20 0x00140000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD19 0x00130000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD18 0x00120000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD17 0x00110000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD16 0x00100000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD15 0x000F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD14 0x000E0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD13 0x000D0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD12 0x000C0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD11 0x000B0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD10 0x000A0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD9 0x00090000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD8 0x00080000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD7 0x00070000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD6 0x00060000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD5 0x00050000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD4 0x00040000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD3 0x00030000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD2 0x00020000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD1 0x00010000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD0 0x00000000 // Field: [13:8] WU1_EV // @@ -803,65 +803,65 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_AUXWUSEL_WU1_EV_W 6 -#define AON_EVENT_AUXWUSEL_WU1_EV_M 0x00003F00 -#define AON_EVENT_AUXWUSEL_WU1_EV_S 8 -#define AON_EVENT_AUXWUSEL_WU1_EV_NONE 0x00003F00 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700 -#define AON_EVENT_AUXWUSEL_WU1_EV_BATMON_VOLT 0x00003600 -#define AON_EVENT_AUXWUSEL_WU1_EV_BATMON_TEMP 0x00003500 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB 0x00003000 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPA 0x00002F00 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV2 0x00002E00 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV1 0x00002D00 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV0 0x00002C00 -#define AON_EVENT_AUXWUSEL_WU1_EV_JTAG 0x00002B00 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_UPD 0x00002A00 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH2 0x00002500 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH1 0x00002400 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH0 0x00002300 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD 0x00002000 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD31 0x00001F00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD30 0x00001E00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD29 0x00001D00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD28 0x00001C00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD27 0x00001B00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD26 0x00001A00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD25 0x00001900 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD24 0x00001800 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD23 0x00001700 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD22 0x00001600 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD21 0x00001500 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD20 0x00001400 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD19 0x00001300 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD18 0x00001200 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD17 0x00001100 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD16 0x00001000 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD15 0x00000F00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD14 0x00000E00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD13 0x00000D00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD12 0x00000C00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD11 0x00000B00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD10 0x00000A00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD9 0x00000900 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD8 0x00000800 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD7 0x00000700 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD6 0x00000600 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD5 0x00000500 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD4 0x00000400 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD3 0x00000300 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD2 0x00000200 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD1 0x00000100 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD0 0x00000000 +#define AON_EVENT_AUXWUSEL_WU1_EV_W 6 +#define AON_EVENT_AUXWUSEL_WU1_EV_M 0x00003F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_S 8 +#define AON_EVENT_AUXWUSEL_WU1_EV_NONE 0x00003F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_AUXWUSEL_WU1_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_AUXWUSEL_WU1_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_AUXWUSEL_WU1_EV_JTAG 0x00002B00 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH2 0x00002500 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH1 0x00002400 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH0 0x00002300 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD 0x00002000 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD31 0x00001F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD30 0x00001E00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD29 0x00001D00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD28 0x00001C00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD27 0x00001B00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD26 0x00001A00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD25 0x00001900 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD24 0x00001800 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD23 0x00001700 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD22 0x00001600 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD21 0x00001500 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD20 0x00001400 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD19 0x00001300 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD18 0x00001200 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD17 0x00001100 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD16 0x00001000 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD15 0x00000F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD14 0x00000E00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD13 0x00000D00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD12 0x00000C00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD11 0x00000B00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD10 0x00000A00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD9 0x00000900 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD8 0x00000800 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD7 0x00000700 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD6 0x00000600 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD5 0x00000500 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD4 0x00000400 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD3 0x00000300 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD2 0x00000200 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD1 0x00000100 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD0 0x00000000 // Field: [5:0] WU0_EV // @@ -936,65 +936,65 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_AUXWUSEL_WU0_EV_W 6 -#define AON_EVENT_AUXWUSEL_WU0_EV_M 0x0000003F -#define AON_EVENT_AUXWUSEL_WU0_EV_S 0 -#define AON_EVENT_AUXWUSEL_WU0_EV_NONE 0x0000003F -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038 -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037 -#define AON_EVENT_AUXWUSEL_WU0_EV_BATMON_VOLT 0x00000036 -#define AON_EVENT_AUXWUSEL_WU0_EV_BATMON_TEMP 0x00000035 -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034 -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033 -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032 -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031 -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB 0x00000030 -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPA 0x0000002F -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV2 0x0000002E -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV1 0x0000002D -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV0 0x0000002C -#define AON_EVENT_AUXWUSEL_WU0_EV_JTAG 0x0000002B -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_UPD 0x0000002A -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029 -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028 -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027 -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026 -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH2 0x00000025 -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH1 0x00000024 -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH0 0x00000023 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD 0x00000020 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD31 0x0000001F -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD30 0x0000001E -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD29 0x0000001D -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD28 0x0000001C -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD27 0x0000001B -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD26 0x0000001A -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD25 0x00000019 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD24 0x00000018 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD23 0x00000017 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD22 0x00000016 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD21 0x00000015 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD20 0x00000014 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD19 0x00000013 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD18 0x00000012 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD17 0x00000011 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD16 0x00000010 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD15 0x0000000F -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD14 0x0000000E -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD13 0x0000000D -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD12 0x0000000C -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD11 0x0000000B -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD10 0x0000000A -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD9 0x00000009 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD8 0x00000008 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD7 0x00000007 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD6 0x00000006 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD5 0x00000005 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD4 0x00000004 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD3 0x00000003 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD2 0x00000002 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD1 0x00000001 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD0 0x00000000 +#define AON_EVENT_AUXWUSEL_WU0_EV_W 6 +#define AON_EVENT_AUXWUSEL_WU0_EV_M 0x0000003F +#define AON_EVENT_AUXWUSEL_WU0_EV_S 0 +#define AON_EVENT_AUXWUSEL_WU0_EV_NONE 0x0000003F +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_AUXWUSEL_WU0_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_AUXWUSEL_WU0_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_AUXWUSEL_WU0_EV_JTAG 0x0000002B +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_UPD 0x0000002A +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH2 0x00000025 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH1 0x00000024 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH0 0x00000023 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD 0x00000020 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD31 0x0000001F +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD30 0x0000001E +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD29 0x0000001D +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD28 0x0000001C +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD27 0x0000001B +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD26 0x0000001A +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD25 0x00000019 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD24 0x00000018 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD23 0x00000017 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD22 0x00000016 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD21 0x00000015 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD20 0x00000014 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD19 0x00000013 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD18 0x00000012 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD17 0x00000011 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD16 0x00000010 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD15 0x0000000F +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD14 0x0000000E +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD13 0x0000000D +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD12 0x0000000C +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD11 0x0000000B +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD10 0x0000000A +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD9 0x00000009 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD8 0x00000008 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD7 0x00000007 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD6 0x00000006 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD5 0x00000005 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD4 0x00000004 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD3 0x00000003 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD2 0x00000002 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD1 0x00000001 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD0 0x00000000 //***************************************************************************** // @@ -1072,65 +1072,65 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_W 6 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M 0x003F0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S 16 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_NONE 0x003F0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC_N 0x00380000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC 0x00370000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_VOLT 0x00360000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP 0x00350000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER1_EV 0x00340000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER0_EV 0x00330000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TDC_DONE 0x00320000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_ADC_DONE 0x00310000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB 0x00300000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPA 0x002F0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV2 0x002E0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV1 0x002D0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV0 0x002C0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_JTAG 0x002B0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_UPD 0x002A0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_COMB_DLY 0x00290000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2_DLY 0x00280000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1_DLY 0x00270000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0_DLY 0x00260000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2 0x00250000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1 0x00240000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0 0x00230000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD 0x00200000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD31 0x001F0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD30 0x001E0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD29 0x001D0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD28 0x001C0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD27 0x001B0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD26 0x001A0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD25 0x00190000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD24 0x00180000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD23 0x00170000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD22 0x00160000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD21 0x00150000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD20 0x00140000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD19 0x00130000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD18 0x00120000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD17 0x00110000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD16 0x00100000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD15 0x000F0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD14 0x000E0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD13 0x000D0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD12 0x000C0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD11 0x000B0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD10 0x000A0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD9 0x00090000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD8 0x00080000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD7 0x00070000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD6 0x00060000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD5 0x00050000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD4 0x00040000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD3 0x00030000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD2 0x00020000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD1 0x00010000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD0 0x00000000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M 0x003F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S 16 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_NONE 0x003F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_JTAG 0x002B0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2 0x00250000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1 0x00240000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0 0x00230000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD 0x00200000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD31 0x001F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD30 0x001E0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD29 0x001D0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD28 0x001C0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD27 0x001B0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD26 0x001A0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD25 0x00190000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD24 0x00180000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD23 0x00170000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD22 0x00160000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD21 0x00150000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD20 0x00140000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD19 0x00130000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD18 0x00120000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD17 0x00110000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD16 0x00100000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD15 0x000F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD14 0x000E0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD13 0x000D0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD12 0x000C0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD11 0x000B0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD10 0x000A0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD9 0x00090000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD8 0x00080000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD7 0x00070000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD6 0x00060000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD5 0x00050000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD4 0x00040000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD3 0x00030000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD2 0x00020000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD1 0x00010000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD0 0x00000000 // Field: [13:8] AON_PROG1_EV // @@ -1203,65 +1203,65 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_W 6 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M 0x00003F00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S 8 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_NONE 0x00003F00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC_N 0x00003800 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC 0x00003700 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_VOLT 0x00003600 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP 0x00003500 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER1_EV 0x00003400 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER0_EV 0x00003300 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TDC_DONE 0x00003200 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_ADC_DONE 0x00003100 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB 0x00003000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPA 0x00002F00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV2 0x00002E00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV1 0x00002D00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV0 0x00002C00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_JTAG 0x00002B00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_UPD 0x00002A00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_COMB_DLY 0x00002900 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2_DLY 0x00002800 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1_DLY 0x00002700 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0_DLY 0x00002600 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2 0x00002500 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1 0x00002400 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0 0x00002300 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD 0x00002000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD31 0x00001F00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD30 0x00001E00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD29 0x00001D00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD28 0x00001C00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD27 0x00001B00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD26 0x00001A00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD25 0x00001900 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD24 0x00001800 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD23 0x00001700 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD22 0x00001600 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD21 0x00001500 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD20 0x00001400 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD19 0x00001300 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD18 0x00001200 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD17 0x00001100 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD16 0x00001000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD15 0x00000F00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD14 0x00000E00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD13 0x00000D00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD12 0x00000C00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD11 0x00000B00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD10 0x00000A00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD9 0x00000900 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD8 0x00000800 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD7 0x00000700 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD6 0x00000600 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD5 0x00000500 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD4 0x00000400 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD3 0x00000300 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD2 0x00000200 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD1 0x00000100 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD0 0x00000000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M 0x00003F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S 8 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_NONE 0x00003F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_JTAG 0x00002B00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2 0x00002500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1 0x00002400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0 0x00002300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD 0x00002000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD31 0x00001F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD30 0x00001E00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD29 0x00001D00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD28 0x00001C00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD27 0x00001B00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD26 0x00001A00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD25 0x00001900 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD24 0x00001800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD23 0x00001700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD22 0x00001600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD21 0x00001500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD20 0x00001400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD19 0x00001300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD18 0x00001200 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD17 0x00001100 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD16 0x00001000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD15 0x00000F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD14 0x00000E00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD13 0x00000D00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD12 0x00000C00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD11 0x00000B00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD10 0x00000A00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD9 0x00000900 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD8 0x00000800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD7 0x00000700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD6 0x00000600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD5 0x00000500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD4 0x00000400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD3 0x00000300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD2 0x00000200 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD1 0x00000100 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD0 0x00000000 // Field: [5:0] AON_PROG0_EV // @@ -1334,65 +1334,65 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_W 6 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M 0x0000003F -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S 0 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_NONE 0x0000003F -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC_N 0x00000038 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC 0x00000037 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_VOLT 0x00000036 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP 0x00000035 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER1_EV 0x00000034 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER0_EV 0x00000033 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TDC_DONE 0x00000032 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_ADC_DONE 0x00000031 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB 0x00000030 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPA 0x0000002F -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV2 0x0000002E -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV1 0x0000002D -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV0 0x0000002C -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_JTAG 0x0000002B -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_UPD 0x0000002A -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_COMB_DLY 0x00000029 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2_DLY 0x00000028 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1_DLY 0x00000027 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0_DLY 0x00000026 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2 0x00000025 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1 0x00000024 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0 0x00000023 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD 0x00000020 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD31 0x0000001F -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD30 0x0000001E -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD29 0x0000001D -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD28 0x0000001C -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD27 0x0000001B -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD26 0x0000001A -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD25 0x00000019 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD24 0x00000018 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD23 0x00000017 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD22 0x00000016 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD21 0x00000015 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD20 0x00000014 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD19 0x00000013 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD18 0x00000012 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD17 0x00000011 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD16 0x00000010 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD15 0x0000000F -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD14 0x0000000E -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD13 0x0000000D -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD12 0x0000000C -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD11 0x0000000B -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD10 0x0000000A -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD9 0x00000009 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD8 0x00000008 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD7 0x00000007 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD6 0x00000006 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD5 0x00000005 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD4 0x00000004 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD3 0x00000003 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD2 0x00000002 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD1 0x00000001 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD0 0x00000000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M 0x0000003F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S 0 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_NONE 0x0000003F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_JTAG 0x0000002B +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_UPD 0x0000002A +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2 0x00000025 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1 0x00000024 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0 0x00000023 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD 0x00000020 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD31 0x0000001F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD30 0x0000001E +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD29 0x0000001D +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD28 0x0000001C +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD27 0x0000001B +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD26 0x0000001A +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD25 0x00000019 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD24 0x00000018 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD23 0x00000017 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD22 0x00000016 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD21 0x00000015 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD20 0x00000014 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD19 0x00000013 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD18 0x00000012 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD17 0x00000011 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD16 0x00000010 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD15 0x0000000F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD14 0x0000000E +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD13 0x0000000D +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD12 0x0000000C +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD11 0x0000000B +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD10 0x0000000A +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD9 0x00000009 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD8 0x00000008 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD7 0x00000007 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD6 0x00000006 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD5 0x00000005 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD4 0x00000004 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD3 0x00000003 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD2 0x00000002 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD1 0x00000001 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD0 0x00000000 //***************************************************************************** // @@ -1469,65 +1469,64 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_W 6 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M 0x0000003F -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S 0 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_NONE 0x0000003F -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC_N 0x00000038 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC 0x00000037 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_VOLT 0x00000036 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP 0x00000035 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER1_EV 0x00000034 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER0_EV 0x00000033 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TDC_DONE 0x00000032 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_ADC_DONE 0x00000031 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB 0x00000030 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPA 0x0000002F -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV2 0x0000002E -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV1 0x0000002D -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV0 0x0000002C -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_JTAG 0x0000002B -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_UPD 0x0000002A -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_COMB_DLY 0x00000029 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2_DLY 0x00000028 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1_DLY 0x00000027 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0_DLY 0x00000026 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2 0x00000025 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1 0x00000024 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0 0x00000023 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD 0x00000020 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD31 0x0000001F -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD30 0x0000001E -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD29 0x0000001D -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD28 0x0000001C -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD27 0x0000001B -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD26 0x0000001A -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD25 0x00000019 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD24 0x00000018 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD23 0x00000017 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD22 0x00000016 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD21 0x00000015 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD20 0x00000014 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD19 0x00000013 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD18 0x00000012 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD17 0x00000011 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD16 0x00000010 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD15 0x0000000F -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD14 0x0000000E -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD13 0x0000000D -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD12 0x0000000C -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD11 0x0000000B -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD10 0x0000000A -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD9 0x00000009 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD8 0x00000008 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD7 0x00000007 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD6 0x00000006 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD5 0x00000005 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD4 0x00000004 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD3 0x00000003 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD2 0x00000002 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD1 0x00000001 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD0 0x00000000 - +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_W 6 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M 0x0000003F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S 0 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_NONE 0x0000003F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_JTAG 0x0000002B +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_UPD 0x0000002A +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2 0x00000025 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1 0x00000024 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0 0x00000023 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD 0x00000020 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD31 0x0000001F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD30 0x0000001E +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD29 0x0000001D +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD28 0x0000001C +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD27 0x0000001B +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD26 0x0000001A +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD25 0x00000019 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD24 0x00000018 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD23 0x00000017 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD22 0x00000016 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD21 0x00000015 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD20 0x00000014 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD19 0x00000013 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD18 0x00000012 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD17 0x00000011 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD16 0x00000010 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD15 0x0000000F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD14 0x0000000E +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD13 0x0000000D +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD12 0x0000000C +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD11 0x0000000B +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD10 0x0000000A +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD9 0x00000009 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD8 0x00000008 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD7 0x00000007 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD6 0x00000006 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD5 0x00000005 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD4 0x00000004 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD3 0x00000003 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD2 0x00000002 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD1 0x00000001 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD0 0x00000000 #endif // __AON_EVENT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_ioc.h index 98ecbed..115c4f0 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_ioc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_ioc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aon_ioc_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aon_ioc_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AON_IOC_H__ #define __HW_AON_IOC_H__ @@ -44,19 +44,19 @@ // //***************************************************************************** // Internal -#define AON_IOC_O_IOSTRMIN 0x00000000 +#define AON_IOC_O_IOSTRMIN 0x00000000 // Internal -#define AON_IOC_O_IOSTRMED 0x00000004 +#define AON_IOC_O_IOSTRMED 0x00000004 // Internal -#define AON_IOC_O_IOSTRMAX 0x00000008 +#define AON_IOC_O_IOSTRMAX 0x00000008 // IO Latch Control -#define AON_IOC_O_IOCLATCH 0x0000000C +#define AON_IOC_O_IOCLATCH 0x0000000C // SCLK_LF External Output Control -#define AON_IOC_O_CLK32KCTL 0x00000010 +#define AON_IOC_O_CLK32KCTL 0x00000010 //***************************************************************************** // @@ -66,9 +66,9 @@ // Field: [2:0] GRAY_CODE // // Internal. Only to be used through TI provided API. -#define AON_IOC_IOSTRMIN_GRAY_CODE_W 3 -#define AON_IOC_IOSTRMIN_GRAY_CODE_M 0x00000007 -#define AON_IOC_IOSTRMIN_GRAY_CODE_S 0 +#define AON_IOC_IOSTRMIN_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMIN_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMIN_GRAY_CODE_S 0 //***************************************************************************** // @@ -78,9 +78,9 @@ // Field: [2:0] GRAY_CODE // // Internal. Only to be used through TI provided API. -#define AON_IOC_IOSTRMED_GRAY_CODE_W 3 -#define AON_IOC_IOSTRMED_GRAY_CODE_M 0x00000007 -#define AON_IOC_IOSTRMED_GRAY_CODE_S 0 +#define AON_IOC_IOSTRMED_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMED_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMED_GRAY_CODE_S 0 //***************************************************************************** // @@ -90,9 +90,9 @@ // Field: [2:0] GRAY_CODE // // Internal. Only to be used through TI provided API. -#define AON_IOC_IOSTRMAX_GRAY_CODE_W 3 -#define AON_IOC_IOSTRMAX_GRAY_CODE_M 0x00000007 -#define AON_IOC_IOSTRMAX_GRAY_CODE_S 0 +#define AON_IOC_IOSTRMAX_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMAX_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMAX_GRAY_CODE_S 0 //***************************************************************************** // @@ -115,12 +115,12 @@ // the IO pin is frozen by latches and kept even // if GPIO module or a peripheral module is turned // off -#define AON_IOC_IOCLATCH_EN 0x00000001 -#define AON_IOC_IOCLATCH_EN_BITN 0 -#define AON_IOC_IOCLATCH_EN_M 0x00000001 -#define AON_IOC_IOCLATCH_EN_S 0 -#define AON_IOC_IOCLATCH_EN_TRANSP 0x00000001 -#define AON_IOC_IOCLATCH_EN_STATIC 0x00000000 +#define AON_IOC_IOCLATCH_EN 0x00000001 +#define AON_IOC_IOCLATCH_EN_BITN 0 +#define AON_IOC_IOCLATCH_EN_M 0x00000001 +#define AON_IOC_IOCLATCH_EN_S 0 +#define AON_IOC_IOCLATCH_EN_TRANSP 0x00000001 +#define AON_IOC_IOCLATCH_EN_STATIC 0x00000000 //***************************************************************************** // @@ -132,10 +132,9 @@ // 0: Output enable active. SCLK_LF output on IO pin that has PORT_ID (e.g. // IOC:IOCFG0.PORT_ID) set to AON_CLK32K. // 1: Output enable not active -#define AON_IOC_CLK32KCTL_OE_N 0x00000001 -#define AON_IOC_CLK32KCTL_OE_N_BITN 0 -#define AON_IOC_CLK32KCTL_OE_N_M 0x00000001 -#define AON_IOC_CLK32KCTL_OE_N_S 0 - +#define AON_IOC_CLK32KCTL_OE_N 0x00000001 +#define AON_IOC_CLK32KCTL_OE_N_BITN 0 +#define AON_IOC_CLK32KCTL_OE_N_M 0x00000001 +#define AON_IOC_CLK32KCTL_OE_N_S 0 #endif // __AON_IOC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_rtc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_rtc.h index 521504d..e413a43 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_rtc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_rtc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aon_rtc_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aon_rtc_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AON_RTC_H__ #define __HW_AON_RTC_H__ @@ -44,40 +44,40 @@ // //***************************************************************************** // Control -#define AON_RTC_O_CTL 0x00000000 +#define AON_RTC_O_CTL 0x00000000 // Event Flags, RTC Status -#define AON_RTC_O_EVFLAGS 0x00000004 +#define AON_RTC_O_EVFLAGS 0x00000004 // Second Counter Value, Integer Part -#define AON_RTC_O_SEC 0x00000008 +#define AON_RTC_O_SEC 0x00000008 // Second Counter Value, Fractional Part -#define AON_RTC_O_SUBSEC 0x0000000C +#define AON_RTC_O_SUBSEC 0x0000000C // Subseconds Increment -#define AON_RTC_O_SUBSECINC 0x00000010 +#define AON_RTC_O_SUBSECINC 0x00000010 // Channel Configuration -#define AON_RTC_O_CHCTL 0x00000014 +#define AON_RTC_O_CHCTL 0x00000014 // Channel 0 Compare Value -#define AON_RTC_O_CH0CMP 0x00000018 +#define AON_RTC_O_CH0CMP 0x00000018 // Channel 1 Compare Value -#define AON_RTC_O_CH1CMP 0x0000001C +#define AON_RTC_O_CH1CMP 0x0000001C // Channel 2 Compare Value -#define AON_RTC_O_CH2CMP 0x00000020 +#define AON_RTC_O_CH2CMP 0x00000020 // Channel 2 Compare Value Auto-increment -#define AON_RTC_O_CH2CMPINC 0x00000024 +#define AON_RTC_O_CH2CMPINC 0x00000024 // Channel 1 Capture Value -#define AON_RTC_O_CH1CAPT 0x00000028 +#define AON_RTC_O_CH1CAPT 0x00000028 // AON Synchronization -#define AON_RTC_O_SYNC 0x0000002C +#define AON_RTC_O_SYNC 0x0000002C //***************************************************************************** // @@ -92,13 +92,13 @@ // CH1 Use Channel 1 delayed event in combined event // CH0 Use Channel 0 delayed event in combined event // NONE No event is selected for combined event. -#define AON_RTC_CTL_COMB_EV_MASK_W 3 -#define AON_RTC_CTL_COMB_EV_MASK_M 0x00070000 -#define AON_RTC_CTL_COMB_EV_MASK_S 16 -#define AON_RTC_CTL_COMB_EV_MASK_CH2 0x00040000 -#define AON_RTC_CTL_COMB_EV_MASK_CH1 0x00020000 -#define AON_RTC_CTL_COMB_EV_MASK_CH0 0x00010000 -#define AON_RTC_CTL_COMB_EV_MASK_NONE 0x00000000 +#define AON_RTC_CTL_COMB_EV_MASK_W 3 +#define AON_RTC_CTL_COMB_EV_MASK_M 0x00070000 +#define AON_RTC_CTL_COMB_EV_MASK_S 16 +#define AON_RTC_CTL_COMB_EV_MASK_CH2 0x00040000 +#define AON_RTC_CTL_COMB_EV_MASK_CH1 0x00020000 +#define AON_RTC_CTL_COMB_EV_MASK_CH0 0x00010000 +#define AON_RTC_CTL_COMB_EV_MASK_NONE 0x00000000 // Field: [11:8] EV_DELAY // @@ -119,23 +119,23 @@ // D2 Delay by 2 clock cycles // D1 Delay by 1 clock cycles // D0 No delay on delayed event -#define AON_RTC_CTL_EV_DELAY_W 4 -#define AON_RTC_CTL_EV_DELAY_M 0x00000F00 -#define AON_RTC_CTL_EV_DELAY_S 8 -#define AON_RTC_CTL_EV_DELAY_D144 0x00000D00 -#define AON_RTC_CTL_EV_DELAY_D128 0x00000C00 -#define AON_RTC_CTL_EV_DELAY_D112 0x00000B00 -#define AON_RTC_CTL_EV_DELAY_D96 0x00000A00 -#define AON_RTC_CTL_EV_DELAY_D80 0x00000900 -#define AON_RTC_CTL_EV_DELAY_D64 0x00000800 -#define AON_RTC_CTL_EV_DELAY_D48 0x00000700 -#define AON_RTC_CTL_EV_DELAY_D32 0x00000600 -#define AON_RTC_CTL_EV_DELAY_D16 0x00000500 -#define AON_RTC_CTL_EV_DELAY_D8 0x00000400 -#define AON_RTC_CTL_EV_DELAY_D4 0x00000300 -#define AON_RTC_CTL_EV_DELAY_D2 0x00000200 -#define AON_RTC_CTL_EV_DELAY_D1 0x00000100 -#define AON_RTC_CTL_EV_DELAY_D0 0x00000000 +#define AON_RTC_CTL_EV_DELAY_W 4 +#define AON_RTC_CTL_EV_DELAY_M 0x00000F00 +#define AON_RTC_CTL_EV_DELAY_S 8 +#define AON_RTC_CTL_EV_DELAY_D144 0x00000D00 +#define AON_RTC_CTL_EV_DELAY_D128 0x00000C00 +#define AON_RTC_CTL_EV_DELAY_D112 0x00000B00 +#define AON_RTC_CTL_EV_DELAY_D96 0x00000A00 +#define AON_RTC_CTL_EV_DELAY_D80 0x00000900 +#define AON_RTC_CTL_EV_DELAY_D64 0x00000800 +#define AON_RTC_CTL_EV_DELAY_D48 0x00000700 +#define AON_RTC_CTL_EV_DELAY_D32 0x00000600 +#define AON_RTC_CTL_EV_DELAY_D16 0x00000500 +#define AON_RTC_CTL_EV_DELAY_D8 0x00000400 +#define AON_RTC_CTL_EV_DELAY_D4 0x00000300 +#define AON_RTC_CTL_EV_DELAY_D2 0x00000200 +#define AON_RTC_CTL_EV_DELAY_D1 0x00000100 +#define AON_RTC_CTL_EV_DELAY_D0 0x00000000 // Field: [7] RESET // @@ -144,10 +144,10 @@ // Writing 1 to this bit will reset the RTC counter. // // This bit is cleared when reset takes effect -#define AON_RTC_CTL_RESET 0x00000080 -#define AON_RTC_CTL_RESET_BITN 7 -#define AON_RTC_CTL_RESET_M 0x00000080 -#define AON_RTC_CTL_RESET_S 7 +#define AON_RTC_CTL_RESET 0x00000080 +#define AON_RTC_CTL_RESET_BITN 7 +#define AON_RTC_CTL_RESET_M 0x00000080 +#define AON_RTC_CTL_RESET_S 7 // Field: [2] RTC_4KHZ_EN // @@ -156,10 +156,10 @@ // // 0: RTC_4KHZ signal is forced to 0 // 1: RTC_4KHZ is enabled ( provied that RTC is enabled EN) -#define AON_RTC_CTL_RTC_4KHZ_EN 0x00000004 -#define AON_RTC_CTL_RTC_4KHZ_EN_BITN 2 -#define AON_RTC_CTL_RTC_4KHZ_EN_M 0x00000004 -#define AON_RTC_CTL_RTC_4KHZ_EN_S 2 +#define AON_RTC_CTL_RTC_4KHZ_EN 0x00000004 +#define AON_RTC_CTL_RTC_4KHZ_EN_BITN 2 +#define AON_RTC_CTL_RTC_4KHZ_EN_M 0x00000004 +#define AON_RTC_CTL_RTC_4KHZ_EN_S 2 // Field: [1] RTC_UPD_EN // @@ -168,10 +168,10 @@ // // 0: RTC_UPD signal is forced to 0 // 1: RTC_UPD signal is toggling @16 kHz -#define AON_RTC_CTL_RTC_UPD_EN 0x00000002 -#define AON_RTC_CTL_RTC_UPD_EN_BITN 1 -#define AON_RTC_CTL_RTC_UPD_EN_M 0x00000002 -#define AON_RTC_CTL_RTC_UPD_EN_S 1 +#define AON_RTC_CTL_RTC_UPD_EN 0x00000002 +#define AON_RTC_CTL_RTC_UPD_EN_BITN 1 +#define AON_RTC_CTL_RTC_UPD_EN_M 0x00000002 +#define AON_RTC_CTL_RTC_UPD_EN_S 1 // Field: [0] EN // @@ -179,10 +179,10 @@ // // 0: Halted (frozen) // 1: Running -#define AON_RTC_CTL_EN 0x00000001 -#define AON_RTC_CTL_EN_BITN 0 -#define AON_RTC_CTL_EN_M 0x00000001 -#define AON_RTC_CTL_EN_S 0 +#define AON_RTC_CTL_EN 0x00000001 +#define AON_RTC_CTL_EN_BITN 0 +#define AON_RTC_CTL_EN_M 0x00000001 +#define AON_RTC_CTL_EN_S 0 //***************************************************************************** // @@ -203,10 +203,10 @@ // // AUX_SCE can read the flag through AUX_WUC:WUEVFLAGS.AON_RTC_CH2 and clear it // using AUX_WUC:WUEVCLR.AON_RTC_CH2. -#define AON_RTC_EVFLAGS_CH2 0x00010000 -#define AON_RTC_EVFLAGS_CH2_BITN 16 -#define AON_RTC_EVFLAGS_CH2_M 0x00010000 -#define AON_RTC_EVFLAGS_CH2_S 16 +#define AON_RTC_EVFLAGS_CH2 0x00010000 +#define AON_RTC_EVFLAGS_CH2_BITN 16 +#define AON_RTC_EVFLAGS_CH2_M 0x00010000 +#define AON_RTC_EVFLAGS_CH2_S 16 // Field: [8] CH1 // @@ -221,10 +221,10 @@ // // Writing 1 clears this flag. Note that a new event can not occur on this // channel in first 2 SCLK_LF cycles after a clearance. -#define AON_RTC_EVFLAGS_CH1 0x00000100 -#define AON_RTC_EVFLAGS_CH1_BITN 8 -#define AON_RTC_EVFLAGS_CH1_M 0x00000100 -#define AON_RTC_EVFLAGS_CH1_S 8 +#define AON_RTC_EVFLAGS_CH1 0x00000100 +#define AON_RTC_EVFLAGS_CH1_BITN 8 +#define AON_RTC_EVFLAGS_CH1_M 0x00000100 +#define AON_RTC_EVFLAGS_CH1_S 8 // Field: [0] CH0 // @@ -237,10 +237,10 @@ // // Writing 1 clears this flag. Note that a new event can not occur on this // channel in first 2 SCLK_LF cycles after a clearance. -#define AON_RTC_EVFLAGS_CH0 0x00000001 -#define AON_RTC_EVFLAGS_CH0_BITN 0 -#define AON_RTC_EVFLAGS_CH0_M 0x00000001 -#define AON_RTC_EVFLAGS_CH0_S 0 +#define AON_RTC_EVFLAGS_CH0 0x00000001 +#define AON_RTC_EVFLAGS_CH0_BITN 0 +#define AON_RTC_EVFLAGS_CH0_M 0x00000001 +#define AON_RTC_EVFLAGS_CH0_S 0 //***************************************************************************** // @@ -254,9 +254,9 @@ // When reading this register the content of SUBSEC.VALUE is simultaneously // latched. A consistent reading of the combined Real Time Clock can be // obtained by first reading this register, then reading SUBSEC register. -#define AON_RTC_SEC_VALUE_W 32 -#define AON_RTC_SEC_VALUE_M 0xFFFFFFFF -#define AON_RTC_SEC_VALUE_S 0 +#define AON_RTC_SEC_VALUE_W 32 +#define AON_RTC_SEC_VALUE_M 0xFFFFFFFF +#define AON_RTC_SEC_VALUE_S 0 //***************************************************************************** // @@ -273,9 +273,9 @@ // - 0x4000_0000 = 0.25 sec // - 0x8000_0000 = 0.5 sec // - 0xC000_0000 = 0.75 sec -#define AON_RTC_SUBSEC_VALUE_W 32 -#define AON_RTC_SUBSEC_VALUE_M 0xFFFFFFFF -#define AON_RTC_SUBSEC_VALUE_S 0 +#define AON_RTC_SUBSEC_VALUE_W 32 +#define AON_RTC_SUBSEC_VALUE_M 0xFFFFFFFF +#define AON_RTC_SUBSEC_VALUE_S 0 //***************************************************************************** // @@ -301,9 +301,9 @@ // NOTE: This register is read only. Modification of the register value must be // done using registers AUX_WUC:RTCSUBSECINC1 , AUX_WUC:RTCSUBSECINC0 and // AUX_WUC:RTCSUBSECINCCTL -#define AON_RTC_SUBSECINC_VALUEINC_W 24 -#define AON_RTC_SUBSECINC_VALUEINC_M 0x00FFFFFF -#define AON_RTC_SUBSECINC_VALUEINC_S 0 +#define AON_RTC_SUBSECINC_VALUEINC_W 24 +#define AON_RTC_SUBSECINC_VALUEINC_M 0x00FFFFFF +#define AON_RTC_SUBSECINC_VALUEINC_S 0 //***************************************************************************** // @@ -313,10 +313,10 @@ // Field: [18] CH2_CONT_EN // // Set to enable continuous operation of Channel 2 -#define AON_RTC_CHCTL_CH2_CONT_EN 0x00040000 -#define AON_RTC_CHCTL_CH2_CONT_EN_BITN 18 -#define AON_RTC_CHCTL_CH2_CONT_EN_M 0x00040000 -#define AON_RTC_CHCTL_CH2_CONT_EN_S 18 +#define AON_RTC_CHCTL_CH2_CONT_EN 0x00040000 +#define AON_RTC_CHCTL_CH2_CONT_EN_BITN 18 +#define AON_RTC_CHCTL_CH2_CONT_EN_M 0x00040000 +#define AON_RTC_CHCTL_CH2_CONT_EN_S 18 // Field: [16] CH2_EN // @@ -324,10 +324,10 @@ // // 0: Disable RTC Channel 2 // 1: Enable RTC Channel 2 -#define AON_RTC_CHCTL_CH2_EN 0x00010000 -#define AON_RTC_CHCTL_CH2_EN_BITN 16 -#define AON_RTC_CHCTL_CH2_EN_M 0x00010000 -#define AON_RTC_CHCTL_CH2_EN_S 16 +#define AON_RTC_CHCTL_CH2_EN 0x00010000 +#define AON_RTC_CHCTL_CH2_EN_BITN 16 +#define AON_RTC_CHCTL_CH2_EN_M 0x00010000 +#define AON_RTC_CHCTL_CH2_EN_S 16 // Field: [9] CH1_CAPT_EN // @@ -335,10 +335,10 @@ // // 0: Compare mode (default) // 1: Capture mode -#define AON_RTC_CHCTL_CH1_CAPT_EN 0x00000200 -#define AON_RTC_CHCTL_CH1_CAPT_EN_BITN 9 -#define AON_RTC_CHCTL_CH1_CAPT_EN_M 0x00000200 -#define AON_RTC_CHCTL_CH1_CAPT_EN_S 9 +#define AON_RTC_CHCTL_CH1_CAPT_EN 0x00000200 +#define AON_RTC_CHCTL_CH1_CAPT_EN_BITN 9 +#define AON_RTC_CHCTL_CH1_CAPT_EN_M 0x00000200 +#define AON_RTC_CHCTL_CH1_CAPT_EN_S 9 // Field: [8] CH1_EN // @@ -346,10 +346,10 @@ // // 0: Disable RTC Channel 1 // 1: Enable RTC Channel 1 -#define AON_RTC_CHCTL_CH1_EN 0x00000100 -#define AON_RTC_CHCTL_CH1_EN_BITN 8 -#define AON_RTC_CHCTL_CH1_EN_M 0x00000100 -#define AON_RTC_CHCTL_CH1_EN_S 8 +#define AON_RTC_CHCTL_CH1_EN 0x00000100 +#define AON_RTC_CHCTL_CH1_EN_BITN 8 +#define AON_RTC_CHCTL_CH1_EN_M 0x00000100 +#define AON_RTC_CHCTL_CH1_EN_S 8 // Field: [0] CH0_EN // @@ -357,10 +357,10 @@ // // 0: Disable RTC Channel 0 // 1: Enable RTC Channel 0 -#define AON_RTC_CHCTL_CH0_EN 0x00000001 -#define AON_RTC_CHCTL_CH0_EN_BITN 0 -#define AON_RTC_CHCTL_CH0_EN_M 0x00000001 -#define AON_RTC_CHCTL_CH0_EN_S 0 +#define AON_RTC_CHCTL_CH0_EN 0x00000001 +#define AON_RTC_CHCTL_CH0_EN_BITN 0 +#define AON_RTC_CHCTL_CH0_EN_M 0x00000001 +#define AON_RTC_CHCTL_CH0_EN_S 0 //***************************************************************************** // @@ -388,9 +388,9 @@ // // *) It can take up to 2 SCLK_LF clock cycles before event occurs due to // synchronization. -#define AON_RTC_CH0CMP_VALUE_W 32 -#define AON_RTC_CH0CMP_VALUE_M 0xFFFFFFFF -#define AON_RTC_CH0CMP_VALUE_S 0 +#define AON_RTC_CH0CMP_VALUE_W 32 +#define AON_RTC_CH0CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH0CMP_VALUE_S 0 //***************************************************************************** // @@ -418,9 +418,9 @@ // // *) It can take up to 2 SCLK_LF clock cycles before event occurs due to // synchronization. -#define AON_RTC_CH1CMP_VALUE_W 32 -#define AON_RTC_CH1CMP_VALUE_M 0xFFFFFFFF -#define AON_RTC_CH1CMP_VALUE_S 0 +#define AON_RTC_CH1CMP_VALUE_W 32 +#define AON_RTC_CH1CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH1CMP_VALUE_S 0 //***************************************************************************** // @@ -448,9 +448,9 @@ // // *) It can take up to 2 SCLK_LF clock cycles before event occurs due to // synchronization. -#define AON_RTC_CH2CMP_VALUE_W 32 -#define AON_RTC_CH2CMP_VALUE_M 0xFFFFFFFF -#define AON_RTC_CH2CMP_VALUE_S 0 +#define AON_RTC_CH2CMP_VALUE_W 32 +#define AON_RTC_CH2CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH2CMP_VALUE_S 0 //***************************************************************************** // @@ -461,9 +461,9 @@ // // If CHCTL.CH2_CONT_EN is set, this value is added to CH2CMP.VALUE on every // channel 2 compare event. -#define AON_RTC_CH2CMPINC_VALUE_W 32 -#define AON_RTC_CH2CMPINC_VALUE_M 0xFFFFFFFF -#define AON_RTC_CH2CMPINC_VALUE_S 0 +#define AON_RTC_CH2CMPINC_VALUE_W 32 +#define AON_RTC_CH2CMPINC_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH2CMPINC_VALUE_S 0 //***************************************************************************** // @@ -473,16 +473,16 @@ // Field: [31:16] SEC // // Value of SEC.VALUE bits 15:0 at capture time. -#define AON_RTC_CH1CAPT_SEC_W 16 -#define AON_RTC_CH1CAPT_SEC_M 0xFFFF0000 -#define AON_RTC_CH1CAPT_SEC_S 16 +#define AON_RTC_CH1CAPT_SEC_W 16 +#define AON_RTC_CH1CAPT_SEC_M 0xFFFF0000 +#define AON_RTC_CH1CAPT_SEC_S 16 // Field: [15:0] SUBSEC // // Value of SUBSEC.VALUE bits 31:16 at capture time. -#define AON_RTC_CH1CAPT_SUBSEC_W 16 -#define AON_RTC_CH1CAPT_SUBSEC_M 0x0000FFFF -#define AON_RTC_CH1CAPT_SUBSEC_S 0 +#define AON_RTC_CH1CAPT_SUBSEC_W 16 +#define AON_RTC_CH1CAPT_SUBSEC_M 0x0000FFFF +#define AON_RTC_CH1CAPT_SUBSEC_S 0 //***************************************************************************** // @@ -499,10 +499,9 @@ // waking up from sleep // Failure to do so may result in reading AON values from prior to going to // sleep -#define AON_RTC_SYNC_WBUSY 0x00000001 -#define AON_RTC_SYNC_WBUSY_BITN 0 -#define AON_RTC_SYNC_WBUSY_M 0x00000001 -#define AON_RTC_SYNC_WBUSY_S 0 - +#define AON_RTC_SYNC_WBUSY 0x00000001 +#define AON_RTC_SYNC_WBUSY_BITN 0 +#define AON_RTC_SYNC_WBUSY_M 0x00000001 +#define AON_RTC_SYNC_WBUSY_S 0 #endif // __AON_RTC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_sysctl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_sysctl.h index c8352c1..ff92824 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_sysctl.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_sysctl.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aon_sysctl_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aon_sysctl_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AON_SYSCTL_H__ #define __HW_AON_SYSCTL_H__ @@ -44,13 +44,13 @@ // //***************************************************************************** // Power Management -#define AON_SYSCTL_O_PWRCTL 0x00000000 +#define AON_SYSCTL_O_PWRCTL 0x00000000 // Reset Management -#define AON_SYSCTL_O_RESETCTL 0x00000004 +#define AON_SYSCTL_O_RESETCTL 0x00000004 // Sleep Mode -#define AON_SYSCTL_O_SLEEPCTL 0x00000008 +#define AON_SYSCTL_O_SLEEPCTL 0x00000008 //***************************************************************************** // @@ -63,10 +63,10 @@ // // 0: Use GLDO for regulation of VDDRin active mode. // 1: Use DCDC for regulation of VDDRin active mode. -#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE 0x00000004 -#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_BITN 2 -#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M 0x00000004 -#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_S 2 +#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE 0x00000004 +#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_BITN 2 +#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M 0x00000004 +#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_S 2 // Field: [1] EXT_REG_MODE // @@ -74,10 +74,10 @@ // // 0: DCDC/GLDO are generating VDDR // 1: DCDC/GLDO are bypassed, external regulator supplies VDDR -#define AON_SYSCTL_PWRCTL_EXT_REG_MODE 0x00000002 -#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_BITN 1 -#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_M 0x00000002 -#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_S 1 +#define AON_SYSCTL_PWRCTL_EXT_REG_MODE 0x00000002 +#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_BITN 1 +#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_M 0x00000002 +#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_S 1 // Field: [0] DCDC_EN // @@ -87,10 +87,10 @@ // 1: Use DCDC for recharge of VDDR // // Note: This bitfield should be set to the same as DCDC_ACTIVE -#define AON_SYSCTL_PWRCTL_DCDC_EN 0x00000001 -#define AON_SYSCTL_PWRCTL_DCDC_EN_BITN 0 -#define AON_SYSCTL_PWRCTL_DCDC_EN_M 0x00000001 -#define AON_SYSCTL_PWRCTL_DCDC_EN_S 0 +#define AON_SYSCTL_PWRCTL_DCDC_EN 0x00000001 +#define AON_SYSCTL_PWRCTL_DCDC_EN_BITN 0 +#define AON_SYSCTL_PWRCTL_DCDC_EN_M 0x00000001 +#define AON_SYSCTL_PWRCTL_DCDC_EN_S 0 //***************************************************************************** // @@ -104,42 +104,42 @@ // // 0: No effect // 1: Generate system reset. Appears as SYSRESET in RESET_SRC. -#define AON_SYSCTL_RESETCTL_SYSRESET 0x80000000 -#define AON_SYSCTL_RESETCTL_SYSRESET_BITN 31 -#define AON_SYSCTL_RESETCTL_SYSRESET_M 0x80000000 -#define AON_SYSCTL_RESETCTL_SYSRESET_S 31 +#define AON_SYSCTL_RESETCTL_SYSRESET 0x80000000 +#define AON_SYSCTL_RESETCTL_SYSRESET_BITN 31 +#define AON_SYSCTL_RESETCTL_SYSRESET_M 0x80000000 +#define AON_SYSCTL_RESETCTL_SYSRESET_S 31 // Field: [25] BOOT_DET_1_CLR // // Internal. Only to be used through TI provided API. -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR 0x02000000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_BITN 25 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_M 0x02000000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_S 25 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR 0x02000000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_BITN 25 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_M 0x02000000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_S 25 // Field: [24] BOOT_DET_0_CLR // // Internal. Only to be used through TI provided API. -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR 0x01000000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_BITN 24 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_M 0x01000000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_S 24 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR 0x01000000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_BITN 24 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_M 0x01000000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_S 24 // Field: [17] BOOT_DET_1_SET // // Internal. Only to be used through TI provided API. -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET 0x00020000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_BITN 17 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M 0x00020000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_S 17 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET 0x00020000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_BITN 17 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M 0x00020000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_S 17 // Field: [16] BOOT_DET_0_SET // // Internal. Only to be used through TI provided API. -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET 0x00010000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_BITN 16 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_M 0x00010000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_S 16 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET 0x00010000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_BITN 16 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_M 0x00010000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_S 16 // Field: [15] WU_FROM_SD // @@ -155,10 +155,10 @@ // // Note: This flag can not be cleared and will therefor remain valid untill // poweroff/reset -#define AON_SYSCTL_RESETCTL_WU_FROM_SD 0x00008000 -#define AON_SYSCTL_RESETCTL_WU_FROM_SD_BITN 15 -#define AON_SYSCTL_RESETCTL_WU_FROM_SD_M 0x00008000 -#define AON_SYSCTL_RESETCTL_WU_FROM_SD_S 15 +#define AON_SYSCTL_RESETCTL_WU_FROM_SD 0x00008000 +#define AON_SYSCTL_RESETCTL_WU_FROM_SD_BITN 15 +#define AON_SYSCTL_RESETCTL_WU_FROM_SD_M 0x00008000 +#define AON_SYSCTL_RESETCTL_WU_FROM_SD_S 15 // Field: [14] GPIO_WU_FROM_SD // @@ -176,26 +176,26 @@ // // Note: This flag can not be cleared and will therefor remain valid untill // poweroff/reset -#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD 0x00004000 -#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_BITN 14 -#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_M 0x00004000 -#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_S 14 +#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD 0x00004000 +#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_BITN 14 +#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_M 0x00004000 +#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_S 14 // Field: [13] BOOT_DET_1 // // Internal. Only to be used through TI provided API. -#define AON_SYSCTL_RESETCTL_BOOT_DET_1 0x00002000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_BITN 13 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_M 0x00002000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_S 13 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1 0x00002000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_BITN 13 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_M 0x00002000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_S 13 // Field: [12] BOOT_DET_0 // // Internal. Only to be used through TI provided API. -#define AON_SYSCTL_RESETCTL_BOOT_DET_0 0x00001000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_BITN 12 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_M 0x00001000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_S 12 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0 0x00001000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_BITN 12 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_M 0x00001000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_S 12 // Field: [11] VDDS_LOSS_EN_OVR // @@ -206,10 +206,10 @@ // VDDS_LOSS_EN) // // This bit can be locked -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR 0x00000800 -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_BITN 11 -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_M 0x00000800 -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_S 11 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR 0x00000800 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_BITN 11 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_M 0x00000800 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_S 11 // Field: [10] VDDR_LOSS_EN_OVR // @@ -220,10 +220,10 @@ // VDDR_LOSS_EN) // // This bit can be locked -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR 0x00000400 -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_BITN 10 -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_M 0x00000400 -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_S 10 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR 0x00000400 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_BITN 10 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_M 0x00000400 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_S 10 // Field: [9] VDD_LOSS_EN_OVR // @@ -234,10 +234,10 @@ // VDD_LOSS_EN) // // This bit can be locked -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR 0x00000200 -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_BITN 9 -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_M 0x00000200 -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_S 9 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR 0x00000200 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_BITN 9 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_M 0x00000200 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_S 9 // Field: [7] VDDS_LOSS_EN // @@ -245,10 +245,10 @@ // // 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1 // 1: Brown out detect of VDDS generates system reset -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN 0x00000080 -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_BITN 7 -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_M 0x00000080 -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_S 7 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN 0x00000080 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_BITN 7 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_M 0x00000080 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_S 7 // Field: [6] VDDR_LOSS_EN // @@ -256,10 +256,10 @@ // // 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1 // 1: Brown out detect of VDDR generates system reset -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN 0x00000040 -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_BITN 6 -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_M 0x00000040 -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_S 6 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN 0x00000040 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_BITN 6 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_M 0x00000040 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_S 6 // Field: [5] VDD_LOSS_EN // @@ -267,10 +267,10 @@ // // 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1 // 1: Brown out detect of VDD generates system reset -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN 0x00000020 -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_BITN 5 -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_M 0x00000020 -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_S 5 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN 0x00000020 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_BITN 5 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_M 0x00000020 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_S 5 // Field: [4] CLK_LOSS_EN // @@ -285,10 +285,10 @@ // // 0: Clock loss is ignored // 1: Clock loss generates system reset -#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN 0x00000010 -#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_BITN 4 -#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_M 0x00000010 -#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_S 4 +#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN 0x00000010 +#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_BITN 4 +#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_M 0x00000010 +#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_S 4 // Field: [3:1] RESET_SRC // @@ -310,17 +310,17 @@ // VDDS_LOSS Brown out detect on VDDS // PIN_RESET Reset pin // PWR_ON Power on reset -#define AON_SYSCTL_RESETCTL_RESET_SRC_W 3 -#define AON_SYSCTL_RESETCTL_RESET_SRC_M 0x0000000E -#define AON_SYSCTL_RESETCTL_RESET_SRC_S 1 -#define AON_SYSCTL_RESETCTL_RESET_SRC_WARMRESET 0x0000000E -#define AON_SYSCTL_RESETCTL_RESET_SRC_SYSRESET 0x0000000C -#define AON_SYSCTL_RESETCTL_RESET_SRC_CLK_LOSS 0x0000000A -#define AON_SYSCTL_RESETCTL_RESET_SRC_VDDR_LOSS 0x00000008 -#define AON_SYSCTL_RESETCTL_RESET_SRC_VDD_LOSS 0x00000006 -#define AON_SYSCTL_RESETCTL_RESET_SRC_VDDS_LOSS 0x00000004 -#define AON_SYSCTL_RESETCTL_RESET_SRC_PIN_RESET 0x00000002 -#define AON_SYSCTL_RESETCTL_RESET_SRC_PWR_ON 0x00000000 +#define AON_SYSCTL_RESETCTL_RESET_SRC_W 3 +#define AON_SYSCTL_RESETCTL_RESET_SRC_M 0x0000000E +#define AON_SYSCTL_RESETCTL_RESET_SRC_S 1 +#define AON_SYSCTL_RESETCTL_RESET_SRC_WARMRESET 0x0000000E +#define AON_SYSCTL_RESETCTL_RESET_SRC_SYSRESET 0x0000000C +#define AON_SYSCTL_RESETCTL_RESET_SRC_CLK_LOSS 0x0000000A +#define AON_SYSCTL_RESETCTL_RESET_SRC_VDDR_LOSS 0x00000008 +#define AON_SYSCTL_RESETCTL_RESET_SRC_VDD_LOSS 0x00000006 +#define AON_SYSCTL_RESETCTL_RESET_SRC_VDDS_LOSS 0x00000004 +#define AON_SYSCTL_RESETCTL_RESET_SRC_PIN_RESET 0x00000002 +#define AON_SYSCTL_RESETCTL_RESET_SRC_PWR_ON 0x00000000 //***************************************************************************** // @@ -339,10 +339,9 @@ // // Application software may want to reconfigure the state for all IO's before // setting this bitfield upon waking up from a SHUTDOWN. -#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS 0x00000001 -#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN 0 -#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_M 0x00000001 -#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_S 0 - +#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS 0x00000001 +#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN 0 +#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_M 0x00000001 +#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_S 0 #endif // __AON_SYSCTL__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_wuc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_wuc.h index 9642cae..0b47dca 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_wuc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aon_wuc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aon_wuc_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aon_wuc_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AON_WUC_H__ #define __HW_AON_WUC_H__ @@ -44,46 +44,46 @@ // //***************************************************************************** // MCU Clock Management -#define AON_WUC_O_MCUCLK 0x00000000 +#define AON_WUC_O_MCUCLK 0x00000000 // AUX Clock Management -#define AON_WUC_O_AUXCLK 0x00000004 +#define AON_WUC_O_AUXCLK 0x00000004 // MCU Configuration -#define AON_WUC_O_MCUCFG 0x00000008 +#define AON_WUC_O_MCUCFG 0x00000008 // AUX Configuration -#define AON_WUC_O_AUXCFG 0x0000000C +#define AON_WUC_O_AUXCFG 0x0000000C // AUX Control -#define AON_WUC_O_AUXCTL 0x00000010 +#define AON_WUC_O_AUXCTL 0x00000010 // Power Status -#define AON_WUC_O_PWRSTAT 0x00000014 +#define AON_WUC_O_PWRSTAT 0x00000014 // Shutdown Control -#define AON_WUC_O_SHUTDOWN 0x00000018 +#define AON_WUC_O_SHUTDOWN 0x00000018 // Control 0 -#define AON_WUC_O_CTL0 0x00000020 +#define AON_WUC_O_CTL0 0x00000020 // Control 1 -#define AON_WUC_O_CTL1 0x00000024 +#define AON_WUC_O_CTL1 0x00000024 // Recharge Controller Configuration -#define AON_WUC_O_RECHARGECFG 0x00000030 +#define AON_WUC_O_RECHARGECFG 0x00000030 // Recharge Controller Status -#define AON_WUC_O_RECHARGESTAT 0x00000034 +#define AON_WUC_O_RECHARGESTAT 0x00000034 // Oscillator Configuration -#define AON_WUC_O_OSCCFG 0x00000038 +#define AON_WUC_O_OSCCFG 0x00000038 // JTAG Configuration -#define AON_WUC_O_JTAGCFG 0x00000040 +#define AON_WUC_O_JTAGCFG 0x00000040 // JTAG USERCODE -#define AON_WUC_O_JTAGUSERCODE 0x00000044 +#define AON_WUC_O_JTAGUSERCODE 0x00000044 //***************************************************************************** // @@ -98,10 +98,10 @@ // 1: RCOSC_HF is calibrated to 48 MHz, allowing FLASH to power up. // 0: RCOSC_HF is not yet calibrated, ie FLASH must not assume that the SCLK_HF // is safe -#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE 0x00000004 -#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_BITN 2 -#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_M 0x00000004 -#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_S 2 +#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE 0x00000004 +#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_BITN 2 +#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_M 0x00000004 +#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_S 2 // Field: [1:0] PWR_DWN_SRC // @@ -115,11 +115,11 @@ // ENUMs: // SCLK_LF Use SCLK_LF in Powerdown // NONE No clock in Powerdown -#define AON_WUC_MCUCLK_PWR_DWN_SRC_W 2 -#define AON_WUC_MCUCLK_PWR_DWN_SRC_M 0x00000003 -#define AON_WUC_MCUCLK_PWR_DWN_SRC_S 0 -#define AON_WUC_MCUCLK_PWR_DWN_SRC_SCLK_LF 0x00000001 -#define AON_WUC_MCUCLK_PWR_DWN_SRC_NONE 0x00000000 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_W 2 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_M 0x00000003 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_S 0 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_SCLK_LF 0x00000001 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_NONE 0x00000000 //***************************************************************************** // @@ -134,11 +134,11 @@ // ENUMs: // SCLK_LF Use SCLK_LF in Powerdown // NONE No clock in Powerdown -#define AON_WUC_AUXCLK_PWR_DWN_SRC_W 2 -#define AON_WUC_AUXCLK_PWR_DWN_SRC_M 0x00001800 -#define AON_WUC_AUXCLK_PWR_DWN_SRC_S 11 -#define AON_WUC_AUXCLK_PWR_DWN_SRC_SCLK_LF 0x00000800 -#define AON_WUC_AUXCLK_PWR_DWN_SRC_NONE 0x00000000 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_W 2 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_M 0x00001800 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_S 11 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_SCLK_LF 0x00000800 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_NONE 0x00000000 // Field: [10:8] SCLK_HF_DIV // @@ -155,17 +155,17 @@ // DIV8 Divide by 8 // DIV4 Divide by 4 // DIV2 Divide by 2 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_W 3 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_M 0x00000700 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_S 8 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV256 0x00000700 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV128 0x00000600 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV64 0x00000500 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV32 0x00000400 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV16 0x00000300 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV8 0x00000200 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV4 0x00000100 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV2 0x00000000 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_W 3 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_M 0x00000700 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_S 8 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV256 0x00000700 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV128 0x00000600 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV64 0x00000500 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV32 0x00000400 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV16 0x00000300 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV8 0x00000200 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV4 0x00000100 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV2 0x00000000 // Field: [2:0] SRC // @@ -175,11 +175,11 @@ // ENUMs: // SCLK_LF LF Clock (SCLK_LF) // SCLK_HF HF Clock (SCLK_HF) -#define AON_WUC_AUXCLK_SRC_W 3 -#define AON_WUC_AUXCLK_SRC_M 0x00000007 -#define AON_WUC_AUXCLK_SRC_S 0 -#define AON_WUC_AUXCLK_SRC_SCLK_LF 0x00000004 -#define AON_WUC_AUXCLK_SRC_SCLK_HF 0x00000001 +#define AON_WUC_AUXCLK_SRC_W 3 +#define AON_WUC_AUXCLK_SRC_M 0x00000007 +#define AON_WUC_AUXCLK_SRC_S 0 +#define AON_WUC_AUXCLK_SRC_SCLK_LF 0x00000004 +#define AON_WUC_AUXCLK_SRC_SCLK_HF 0x00000001 //***************************************************************************** // @@ -189,18 +189,18 @@ // Field: [17] VIRT_OFF // // Internal. Only to be used through TI provided API. -#define AON_WUC_MCUCFG_VIRT_OFF 0x00020000 -#define AON_WUC_MCUCFG_VIRT_OFF_BITN 17 -#define AON_WUC_MCUCFG_VIRT_OFF_M 0x00020000 -#define AON_WUC_MCUCFG_VIRT_OFF_S 17 +#define AON_WUC_MCUCFG_VIRT_OFF 0x00020000 +#define AON_WUC_MCUCFG_VIRT_OFF_BITN 17 +#define AON_WUC_MCUCFG_VIRT_OFF_M 0x00020000 +#define AON_WUC_MCUCFG_VIRT_OFF_S 17 // Field: [16] FIXED_WU_EN // // Internal. Only to be used through TI provided API. -#define AON_WUC_MCUCFG_FIXED_WU_EN 0x00010000 -#define AON_WUC_MCUCFG_FIXED_WU_EN_BITN 16 -#define AON_WUC_MCUCFG_FIXED_WU_EN_M 0x00010000 -#define AON_WUC_MCUCFG_FIXED_WU_EN_S 16 +#define AON_WUC_MCUCFG_FIXED_WU_EN 0x00010000 +#define AON_WUC_MCUCFG_FIXED_WU_EN_BITN 16 +#define AON_WUC_MCUCFG_FIXED_WU_EN_M 0x00010000 +#define AON_WUC_MCUCFG_FIXED_WU_EN_S 16 // Field: [3:0] SRAM_RET_EN // @@ -214,14 +214,14 @@ // RET_LEVEL2 Retention on for SRAM:BANK0 and SRAM:BANK1 // RET_LEVEL1 Retention on for SRAM:BANK0 // RET_NONE Retention is disabled -#define AON_WUC_MCUCFG_SRAM_RET_EN_W 4 -#define AON_WUC_MCUCFG_SRAM_RET_EN_M 0x0000000F -#define AON_WUC_MCUCFG_SRAM_RET_EN_S 0 -#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_FULL 0x0000000F -#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL3 0x00000007 -#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL2 0x00000003 -#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL1 0x00000001 -#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_NONE 0x00000000 +#define AON_WUC_MCUCFG_SRAM_RET_EN_W 4 +#define AON_WUC_MCUCFG_SRAM_RET_EN_M 0x0000000F +#define AON_WUC_MCUCFG_SRAM_RET_EN_S 0 +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_FULL 0x0000000F +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL3 0x00000007 +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL2 0x00000003 +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL1 0x00000001 +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_NONE 0x00000000 //***************************************************************************** // @@ -237,10 +237,10 @@ // // NB: If retention is disabled, the AUX_RAM will be powered off when it would // otherwise be put in retention mode -#define AON_WUC_AUXCFG_RAM_RET_EN 0x00000001 -#define AON_WUC_AUXCFG_RAM_RET_EN_BITN 0 -#define AON_WUC_AUXCFG_RAM_RET_EN_M 0x00000001 -#define AON_WUC_AUXCFG_RAM_RET_EN_S 0 +#define AON_WUC_AUXCFG_RAM_RET_EN 0x00000001 +#define AON_WUC_AUXCFG_RAM_RET_EN_BITN 0 +#define AON_WUC_AUXCFG_RAM_RET_EN_M 0x00000001 +#define AON_WUC_AUXCFG_RAM_RET_EN_S 0 //***************************************************************************** // @@ -254,10 +254,10 @@ // // 0: AUX reset pin will be deasserted // 1: AUX reset pin will be asserted -#define AON_WUC_AUXCTL_RESET_REQ 0x80000000 -#define AON_WUC_AUXCTL_RESET_REQ_BITN 31 -#define AON_WUC_AUXCTL_RESET_REQ_M 0x80000000 -#define AON_WUC_AUXCTL_RESET_REQ_S 31 +#define AON_WUC_AUXCTL_RESET_REQ 0x80000000 +#define AON_WUC_AUXCTL_RESET_REQ_BITN 31 +#define AON_WUC_AUXCTL_RESET_REQ_M 0x80000000 +#define AON_WUC_AUXCTL_RESET_REQ_S 31 // Field: [2] SCE_RUN_EN // @@ -270,10 +270,10 @@ // // 0: AUX_SCE execution will be disabled if AUX_SCE:CTL.CLK_EN is 0 // 1: AUX_SCE execution is enabled. -#define AON_WUC_AUXCTL_SCE_RUN_EN 0x00000004 -#define AON_WUC_AUXCTL_SCE_RUN_EN_BITN 2 -#define AON_WUC_AUXCTL_SCE_RUN_EN_M 0x00000004 -#define AON_WUC_AUXCTL_SCE_RUN_EN_S 2 +#define AON_WUC_AUXCTL_SCE_RUN_EN 0x00000004 +#define AON_WUC_AUXCTL_SCE_RUN_EN_BITN 2 +#define AON_WUC_AUXCTL_SCE_RUN_EN_M 0x00000004 +#define AON_WUC_AUXCTL_SCE_RUN_EN_S 2 // Field: [1] SWEV // @@ -288,10 +288,10 @@ // // Note that it can take up to 1,5 SCLK_LF clock cycles to clear the event from // AUX. -#define AON_WUC_AUXCTL_SWEV 0x00000002 -#define AON_WUC_AUXCTL_SWEV_BITN 1 -#define AON_WUC_AUXCTL_SWEV_M 0x00000002 -#define AON_WUC_AUXCTL_SWEV_S 1 +#define AON_WUC_AUXCTL_SWEV 0x00000002 +#define AON_WUC_AUXCTL_SWEV_BITN 1 +#define AON_WUC_AUXCTL_SWEV_M 0x00000002 +#define AON_WUC_AUXCTL_SWEV_S 1 // Field: [0] AUX_FORCE_ON // @@ -305,10 +305,10 @@ // // 0: AUX is allowed to Power Off, Power Down or Disconnect. // 1: AUX Power OFF, Power Down or Disconnect requests will be overruled -#define AON_WUC_AUXCTL_AUX_FORCE_ON 0x00000001 -#define AON_WUC_AUXCTL_AUX_FORCE_ON_BITN 0 -#define AON_WUC_AUXCTL_AUX_FORCE_ON_M 0x00000001 -#define AON_WUC_AUXCTL_AUX_FORCE_ON_S 0 +#define AON_WUC_AUXCTL_AUX_FORCE_ON 0x00000001 +#define AON_WUC_AUXCTL_AUX_FORCE_ON_BITN 0 +#define AON_WUC_AUXCTL_AUX_FORCE_ON_M 0x00000001 +#define AON_WUC_AUXCTL_AUX_FORCE_ON_S 0 //***************************************************************************** // @@ -321,10 +321,10 @@ // // 0: Active mode // 1: AUX Powerdown request has been granted -#define AON_WUC_PWRSTAT_AUX_PWR_DWN 0x00000200 -#define AON_WUC_PWRSTAT_AUX_PWR_DWN_BITN 9 -#define AON_WUC_PWRSTAT_AUX_PWR_DWN_M 0x00000200 -#define AON_WUC_PWRSTAT_AUX_PWR_DWN_S 9 +#define AON_WUC_PWRSTAT_AUX_PWR_DWN 0x00000200 +#define AON_WUC_PWRSTAT_AUX_PWR_DWN_BITN 9 +#define AON_WUC_PWRSTAT_AUX_PWR_DWN_M 0x00000200 +#define AON_WUC_PWRSTAT_AUX_PWR_DWN_S 9 // Field: [6] JTAG_PD_ON // @@ -332,10 +332,10 @@ // // 0: JTAG is powered off // 1: JTAG is powered on -#define AON_WUC_PWRSTAT_JTAG_PD_ON 0x00000040 -#define AON_WUC_PWRSTAT_JTAG_PD_ON_BITN 6 -#define AON_WUC_PWRSTAT_JTAG_PD_ON_M 0x00000040 -#define AON_WUC_PWRSTAT_JTAG_PD_ON_S 6 +#define AON_WUC_PWRSTAT_JTAG_PD_ON 0x00000040 +#define AON_WUC_PWRSTAT_JTAG_PD_ON_BITN 6 +#define AON_WUC_PWRSTAT_JTAG_PD_ON_M 0x00000040 +#define AON_WUC_PWRSTAT_JTAG_PD_ON_S 6 // Field: [5] AUX_PD_ON // @@ -344,10 +344,10 @@ // 0: AUX is not ready for use ( may be powered off or in power state // transition ) // 1: AUX is powered on, connected to bus and ready for use, -#define AON_WUC_PWRSTAT_AUX_PD_ON 0x00000020 -#define AON_WUC_PWRSTAT_AUX_PD_ON_BITN 5 -#define AON_WUC_PWRSTAT_AUX_PD_ON_M 0x00000020 -#define AON_WUC_PWRSTAT_AUX_PD_ON_S 5 +#define AON_WUC_PWRSTAT_AUX_PD_ON 0x00000020 +#define AON_WUC_PWRSTAT_AUX_PD_ON_BITN 5 +#define AON_WUC_PWRSTAT_AUX_PD_ON_M 0x00000020 +#define AON_WUC_PWRSTAT_AUX_PD_ON_S 5 // Field: [4] MCU_PD_ON // @@ -357,10 +357,10 @@ // be reliable // 1: MCU Power sequencing is finalized and all MCU_AONIF registers are // reliable -#define AON_WUC_PWRSTAT_MCU_PD_ON 0x00000010 -#define AON_WUC_PWRSTAT_MCU_PD_ON_BITN 4 -#define AON_WUC_PWRSTAT_MCU_PD_ON_M 0x00000010 -#define AON_WUC_PWRSTAT_MCU_PD_ON_S 4 +#define AON_WUC_PWRSTAT_MCU_PD_ON 0x00000010 +#define AON_WUC_PWRSTAT_MCU_PD_ON_BITN 4 +#define AON_WUC_PWRSTAT_MCU_PD_ON_M 0x00000010 +#define AON_WUC_PWRSTAT_MCU_PD_ON_S 4 // Field: [2] AUX_BUS_CONNECTED // @@ -368,10 +368,10 @@ // // 0: AUX bus is not connected // 1: AUX bus is connected ( idle_ack = 0 ) -#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED 0x00000004 -#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_BITN 2 -#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_M 0x00000004 -#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_S 2 +#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED 0x00000004 +#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_BITN 2 +#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_M 0x00000004 +#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_S 2 // Field: [1] AUX_RESET_DONE // @@ -379,10 +379,10 @@ // // 0: AUX is being reset // 1: AUX reset is released -#define AON_WUC_PWRSTAT_AUX_RESET_DONE 0x00000002 -#define AON_WUC_PWRSTAT_AUX_RESET_DONE_BITN 1 -#define AON_WUC_PWRSTAT_AUX_RESET_DONE_M 0x00000002 -#define AON_WUC_PWRSTAT_AUX_RESET_DONE_S 1 +#define AON_WUC_PWRSTAT_AUX_RESET_DONE 0x00000002 +#define AON_WUC_PWRSTAT_AUX_RESET_DONE_BITN 1 +#define AON_WUC_PWRSTAT_AUX_RESET_DONE_M 0x00000002 +#define AON_WUC_PWRSTAT_AUX_RESET_DONE_S 1 //***************************************************************************** // @@ -400,10 +400,10 @@ // conditions exists. At this time, the will not enter Powerdown mode, but // instead it will turn off all internal powersupplies, effectively putting the // device into Shutdown mode. -#define AON_WUC_SHUTDOWN_EN 0x00000001 -#define AON_WUC_SHUTDOWN_EN_BITN 0 -#define AON_WUC_SHUTDOWN_EN_M 0x00000001 -#define AON_WUC_SHUTDOWN_EN_S 0 +#define AON_WUC_SHUTDOWN_EN 0x00000001 +#define AON_WUC_SHUTDOWN_EN_BITN 0 +#define AON_WUC_SHUTDOWN_EN_M 0x00000001 +#define AON_WUC_SHUTDOWN_EN_S 0 //***************************************************************************** // @@ -417,26 +417,26 @@ // // 0: Enabled // 1: Disabled -#define AON_WUC_CTL0_PWR_DWN_DIS 0x00000100 -#define AON_WUC_CTL0_PWR_DWN_DIS_BITN 8 -#define AON_WUC_CTL0_PWR_DWN_DIS_M 0x00000100 -#define AON_WUC_CTL0_PWR_DWN_DIS_S 8 +#define AON_WUC_CTL0_PWR_DWN_DIS 0x00000100 +#define AON_WUC_CTL0_PWR_DWN_DIS_BITN 8 +#define AON_WUC_CTL0_PWR_DWN_DIS_M 0x00000100 +#define AON_WUC_CTL0_PWR_DWN_DIS_S 8 // Field: [3] AUX_SRAM_ERASE // // Internal. Only to be used through TI provided API. -#define AON_WUC_CTL0_AUX_SRAM_ERASE 0x00000008 -#define AON_WUC_CTL0_AUX_SRAM_ERASE_BITN 3 -#define AON_WUC_CTL0_AUX_SRAM_ERASE_M 0x00000008 -#define AON_WUC_CTL0_AUX_SRAM_ERASE_S 3 +#define AON_WUC_CTL0_AUX_SRAM_ERASE 0x00000008 +#define AON_WUC_CTL0_AUX_SRAM_ERASE_BITN 3 +#define AON_WUC_CTL0_AUX_SRAM_ERASE_M 0x00000008 +#define AON_WUC_CTL0_AUX_SRAM_ERASE_S 3 // Field: [2] MCU_SRAM_ERASE // // Internal. Only to be used through TI provided API. -#define AON_WUC_CTL0_MCU_SRAM_ERASE 0x00000004 -#define AON_WUC_CTL0_MCU_SRAM_ERASE_BITN 2 -#define AON_WUC_CTL0_MCU_SRAM_ERASE_M 0x00000004 -#define AON_WUC_CTL0_MCU_SRAM_ERASE_S 2 +#define AON_WUC_CTL0_MCU_SRAM_ERASE 0x00000004 +#define AON_WUC_CTL0_MCU_SRAM_ERASE_BITN 2 +#define AON_WUC_CTL0_MCU_SRAM_ERASE_M 0x00000004 +#define AON_WUC_CTL0_MCU_SRAM_ERASE_S 2 //***************************************************************************** // @@ -451,10 +451,10 @@ // 1: JTAG reset // // This bit can only be cleared by writing a 1 to it -#define AON_WUC_CTL1_MCU_RESET_SRC 0x00000002 -#define AON_WUC_CTL1_MCU_RESET_SRC_BITN 1 -#define AON_WUC_CTL1_MCU_RESET_SRC_M 0x00000002 -#define AON_WUC_CTL1_MCU_RESET_SRC_S 1 +#define AON_WUC_CTL1_MCU_RESET_SRC 0x00000002 +#define AON_WUC_CTL1_MCU_RESET_SRC_BITN 1 +#define AON_WUC_CTL1_MCU_RESET_SRC_M 0x00000002 +#define AON_WUC_CTL1_MCU_RESET_SRC_S 1 // Field: [0] MCU_WARM_RESET // @@ -465,10 +465,10 @@ // in MCU_RESET_SRC) // // This bit can only be cleared by writing a 1 to it -#define AON_WUC_CTL1_MCU_WARM_RESET 0x00000001 -#define AON_WUC_CTL1_MCU_WARM_RESET_BITN 0 -#define AON_WUC_CTL1_MCU_WARM_RESET_M 0x00000001 -#define AON_WUC_CTL1_MCU_WARM_RESET_S 0 +#define AON_WUC_CTL1_MCU_WARM_RESET 0x00000001 +#define AON_WUC_CTL1_MCU_WARM_RESET_BITN 0 +#define AON_WUC_CTL1_MCU_WARM_RESET_M 0x00000001 +#define AON_WUC_CTL1_MCU_WARM_RESET_S 0 //***************************************************************************** // @@ -481,10 +481,10 @@ // // Note: Recharge can be turned completely of by setting MAX_PER_E=7 and // MAX_PER_M=31 and this bitfield to 0 -#define AON_WUC_RECHARGECFG_ADAPTIVE_EN 0x80000000 -#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_BITN 31 -#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_M 0x80000000 -#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_S 31 +#define AON_WUC_RECHARGECFG_ADAPTIVE_EN 0x80000000 +#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_BITN 31 +#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_M 0x80000000 +#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_S 31 // Field: [23:20] C2 // @@ -496,9 +496,9 @@ // Note: Rounding may cause adaptive recharge not to start for very small // values of both Gain and Initial period. Criteria for algorithm to start is // MAX(PERIOD*2^-C1,PERIOD*2^-C2) >= 1 -#define AON_WUC_RECHARGECFG_C2_W 4 -#define AON_WUC_RECHARGECFG_C2_M 0x00F00000 -#define AON_WUC_RECHARGECFG_C2_S 20 +#define AON_WUC_RECHARGECFG_C2_W 4 +#define AON_WUC_RECHARGECFG_C2_M 0x00F00000 +#define AON_WUC_RECHARGECFG_C2_S 20 // Field: [19:16] C1 // @@ -510,9 +510,9 @@ // Note: Rounding may cause adaptive recharge not to start for very small // values of both Gain and Initial period. Criteria for algorithm to start is // MAX(PERIOD*2^-C1,PERIOD*2^-C2) >= 1 -#define AON_WUC_RECHARGECFG_C1_W 4 -#define AON_WUC_RECHARGECFG_C1_M 0x000F0000 -#define AON_WUC_RECHARGECFG_C1_S 16 +#define AON_WUC_RECHARGECFG_C1_W 4 +#define AON_WUC_RECHARGECFG_C1_M 0x000F0000 +#define AON_WUC_RECHARGECFG_C1_S 16 // Field: [15:11] MAX_PER_M // @@ -522,9 +522,9 @@ // exponent: // MAXCYCLES=(MAX_PER_M*16+15)*2^MAX_PER_E // This field sets the mantissa of MAXCYCLES -#define AON_WUC_RECHARGECFG_MAX_PER_M_W 5 -#define AON_WUC_RECHARGECFG_MAX_PER_M_M 0x0000F800 -#define AON_WUC_RECHARGECFG_MAX_PER_M_S 11 +#define AON_WUC_RECHARGECFG_MAX_PER_M_W 5 +#define AON_WUC_RECHARGECFG_MAX_PER_M_M 0x0000F800 +#define AON_WUC_RECHARGECFG_MAX_PER_M_S 11 // Field: [10:8] MAX_PER_E // @@ -534,9 +534,9 @@ // exponent: // MAXCYCLES=(MAX_PER_M*16+15)*2^MAX_PER_E // This field sets the exponent MAXCYCLES -#define AON_WUC_RECHARGECFG_MAX_PER_E_W 3 -#define AON_WUC_RECHARGECFG_MAX_PER_E_M 0x00000700 -#define AON_WUC_RECHARGECFG_MAX_PER_E_S 8 +#define AON_WUC_RECHARGECFG_MAX_PER_E_W 3 +#define AON_WUC_RECHARGECFG_MAX_PER_E_M 0x00000700 +#define AON_WUC_RECHARGECFG_MAX_PER_E_S 8 // Field: [7:3] PER_M // @@ -547,9 +547,9 @@ // bit exponent: // This field sets the Mantissa of the Period. // PERIOD=(PER_M*16+15)*2^PER_E -#define AON_WUC_RECHARGECFG_PER_M_W 5 -#define AON_WUC_RECHARGECFG_PER_M_M 0x000000F8 -#define AON_WUC_RECHARGECFG_PER_M_S 3 +#define AON_WUC_RECHARGECFG_PER_M_W 5 +#define AON_WUC_RECHARGECFG_PER_M_M 0x000000F8 +#define AON_WUC_RECHARGECFG_PER_M_S 3 // Field: [2:0] PER_E // @@ -560,9 +560,9 @@ // bit exponent: // This field sets the Exponent of the Period. // PERIOD=(PER_M*16+15)*2^PER_E -#define AON_WUC_RECHARGECFG_PER_E_W 3 -#define AON_WUC_RECHARGECFG_PER_E_M 0x00000007 -#define AON_WUC_RECHARGECFG_PER_E_S 0 +#define AON_WUC_RECHARGECFG_PER_E_W 3 +#define AON_WUC_RECHARGECFG_PER_E_M 0x00000007 +#define AON_WUC_RECHARGECFG_PER_E_S 0 //***************************************************************************** // @@ -577,9 +577,9 @@ // and bit 0 is updated with the last VDDR sample, ie a 1 is shiftet in in case // VDDR > VDDR_threshold just before recharge starts. Otherwise a 0 will be // shifted in. -#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_W 4 -#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_M 0x000F0000 -#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_S 16 +#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_W 4 +#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_M 0x000F0000 +#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_S 16 // Field: [15:0] MAX_USED_PER // @@ -593,9 +593,9 @@ // recharge. // // This bitfield is cleared to 0 when writing this register. -#define AON_WUC_RECHARGESTAT_MAX_USED_PER_W 16 -#define AON_WUC_RECHARGESTAT_MAX_USED_PER_M 0x0000FFFF -#define AON_WUC_RECHARGESTAT_MAX_USED_PER_S 0 +#define AON_WUC_RECHARGESTAT_MAX_USED_PER_W 16 +#define AON_WUC_RECHARGESTAT_MAX_USED_PER_M 0x0000FFFF +#define AON_WUC_RECHARGESTAT_MAX_USED_PER_S 0 //***************************************************************************** // @@ -616,9 +616,9 @@ // This field sets the mantissa // Note: Oscillator amplitude calibration is turned of when both this bitfield // and PER_E are set to 0 -#define AON_WUC_OSCCFG_PER_M_W 5 -#define AON_WUC_OSCCFG_PER_M_M 0x000000F8 -#define AON_WUC_OSCCFG_PER_M_S 3 +#define AON_WUC_OSCCFG_PER_M_W 5 +#define AON_WUC_OSCCFG_PER_M_M 0x000000F8 +#define AON_WUC_OSCCFG_PER_M_S 3 // Field: [2:0] PER_E // @@ -633,9 +633,9 @@ // This field sets the exponent // Note: Oscillator amplitude calibration is turned of when both PER_M and // this bitfield are set to 0 -#define AON_WUC_OSCCFG_PER_E_W 3 -#define AON_WUC_OSCCFG_PER_E_M 0x00000007 -#define AON_WUC_OSCCFG_PER_E_S 0 +#define AON_WUC_OSCCFG_PER_E_W 3 +#define AON_WUC_OSCCFG_PER_E_M 0x00000007 +#define AON_WUC_OSCCFG_PER_E_S 0 //***************************************************************************** // @@ -652,10 +652,10 @@ // // NB: The reset value causes JTAG Power Domain to be powered on by default. // Software must clear this bit to turn off the JTAG Power Domain -#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON 0x00000100 -#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_BITN 8 -#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_M 0x00000100 -#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_S 8 +#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON 0x00000100 +#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_BITN 8 +#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_M 0x00000100 +#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_S 8 //***************************************************************************** // @@ -666,9 +666,8 @@ // // 32-bit JTAG USERCODE register feeding main JTAG TAP // NB: This field can be locked -#define AON_WUC_JTAGUSERCODE_USER_CODE_W 32 -#define AON_WUC_JTAGUSERCODE_USER_CODE_M 0xFFFFFFFF -#define AON_WUC_JTAGUSERCODE_USER_CODE_S 0 - +#define AON_WUC_JTAGUSERCODE_USER_CODE_W 32 +#define AON_WUC_JTAGUSERCODE_USER_CODE_M 0xFFFFFFFF +#define AON_WUC_JTAGUSERCODE_USER_CODE_S 0 #endif // __AON_WUC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_aiodio.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_aiodio.h index 7d6b08f..a62ce47 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_aiodio.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_aiodio.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_aiodio_h -* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) -* Revision: 49005 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_aiodio_h + * Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) + * Revision: 49005 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_AIODIO_H__ #define __HW_AUX_AIODIO_H__ @@ -44,25 +44,25 @@ // //***************************************************************************** // General Purpose Input Output Data Out -#define AUX_AIODIO_O_GPIODOUT 0x00000000 +#define AUX_AIODIO_O_GPIODOUT 0x00000000 // Input Output Mode -#define AUX_AIODIO_O_IOMODE 0x00000004 +#define AUX_AIODIO_O_IOMODE 0x00000004 // General Purpose Input Output Data In -#define AUX_AIODIO_O_GPIODIN 0x00000008 +#define AUX_AIODIO_O_GPIODIN 0x00000008 // General Purpose Input Output Data Out Set -#define AUX_AIODIO_O_GPIODOUTSET 0x0000000C +#define AUX_AIODIO_O_GPIODOUTSET 0x0000000C // General Purpose Input Output Data Out Clear -#define AUX_AIODIO_O_GPIODOUTCLR 0x00000010 +#define AUX_AIODIO_O_GPIODOUTCLR 0x00000010 // General Purpose Input Output Data Out Toggle -#define AUX_AIODIO_O_GPIODOUTTGL 0x00000014 +#define AUX_AIODIO_O_GPIODOUTTGL 0x00000014 // General Purpose Input Output Digital Input Enable -#define AUX_AIODIO_O_GPIODIE 0x00000018 +#define AUX_AIODIO_O_GPIODIE 0x00000018 //***************************************************************************** // @@ -73,9 +73,9 @@ // // Write 1 to bit index n in this bit vector to set AUXIO[8i+n]. // Write 0 to bit index n in this bit vector to clear AUXIO[8i+n]. -#define AUX_AIODIO_GPIODOUT_IO7_0_W 8 -#define AUX_AIODIO_GPIODOUT_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODOUT_IO7_0_S 0 +#define AUX_AIODIO_GPIODOUT_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUT_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUT_IO7_0_S 0 //***************************************************************************** // @@ -114,13 +114,13 @@ // // GPIODOUT bit 7 drives // AUXIO[8i+7]. -#define AUX_AIODIO_IOMODE_IO7_W 2 -#define AUX_AIODIO_IOMODE_IO7_M 0x0000C000 -#define AUX_AIODIO_IOMODE_IO7_S 14 -#define AUX_AIODIO_IOMODE_IO7_OPEN_SOURCE 0x0000C000 -#define AUX_AIODIO_IOMODE_IO7_OPEN_DRAIN 0x00008000 -#define AUX_AIODIO_IOMODE_IO7_IN 0x00004000 -#define AUX_AIODIO_IOMODE_IO7_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO7_W 2 +#define AUX_AIODIO_IOMODE_IO7_M 0x0000C000 +#define AUX_AIODIO_IOMODE_IO7_S 14 +#define AUX_AIODIO_IOMODE_IO7_OPEN_SOURCE 0x0000C000 +#define AUX_AIODIO_IOMODE_IO7_OPEN_DRAIN 0x00008000 +#define AUX_AIODIO_IOMODE_IO7_IN 0x00004000 +#define AUX_AIODIO_IOMODE_IO7_OUT 0x00000000 // Field: [13:12] IO6 // @@ -154,13 +154,13 @@ // // GPIODOUT bit 6 drives // AUXIO[8i+6]. -#define AUX_AIODIO_IOMODE_IO6_W 2 -#define AUX_AIODIO_IOMODE_IO6_M 0x00003000 -#define AUX_AIODIO_IOMODE_IO6_S 12 -#define AUX_AIODIO_IOMODE_IO6_OPEN_SOURCE 0x00003000 -#define AUX_AIODIO_IOMODE_IO6_OPEN_DRAIN 0x00002000 -#define AUX_AIODIO_IOMODE_IO6_IN 0x00001000 -#define AUX_AIODIO_IOMODE_IO6_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO6_W 2 +#define AUX_AIODIO_IOMODE_IO6_M 0x00003000 +#define AUX_AIODIO_IOMODE_IO6_S 12 +#define AUX_AIODIO_IOMODE_IO6_OPEN_SOURCE 0x00003000 +#define AUX_AIODIO_IOMODE_IO6_OPEN_DRAIN 0x00002000 +#define AUX_AIODIO_IOMODE_IO6_IN 0x00001000 +#define AUX_AIODIO_IOMODE_IO6_OUT 0x00000000 // Field: [11:10] IO5 // @@ -194,13 +194,13 @@ // // GPIODOUT bit 5 drives // AUXIO[8i+5]. -#define AUX_AIODIO_IOMODE_IO5_W 2 -#define AUX_AIODIO_IOMODE_IO5_M 0x00000C00 -#define AUX_AIODIO_IOMODE_IO5_S 10 -#define AUX_AIODIO_IOMODE_IO5_OPEN_SOURCE 0x00000C00 -#define AUX_AIODIO_IOMODE_IO5_OPEN_DRAIN 0x00000800 -#define AUX_AIODIO_IOMODE_IO5_IN 0x00000400 -#define AUX_AIODIO_IOMODE_IO5_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO5_W 2 +#define AUX_AIODIO_IOMODE_IO5_M 0x00000C00 +#define AUX_AIODIO_IOMODE_IO5_S 10 +#define AUX_AIODIO_IOMODE_IO5_OPEN_SOURCE 0x00000C00 +#define AUX_AIODIO_IOMODE_IO5_OPEN_DRAIN 0x00000800 +#define AUX_AIODIO_IOMODE_IO5_IN 0x00000400 +#define AUX_AIODIO_IOMODE_IO5_OUT 0x00000000 // Field: [9:8] IO4 // @@ -234,13 +234,13 @@ // // GPIODOUT bit 4 drives // AUXIO[8i+4]. -#define AUX_AIODIO_IOMODE_IO4_W 2 -#define AUX_AIODIO_IOMODE_IO4_M 0x00000300 -#define AUX_AIODIO_IOMODE_IO4_S 8 -#define AUX_AIODIO_IOMODE_IO4_OPEN_SOURCE 0x00000300 -#define AUX_AIODIO_IOMODE_IO4_OPEN_DRAIN 0x00000200 -#define AUX_AIODIO_IOMODE_IO4_IN 0x00000100 -#define AUX_AIODIO_IOMODE_IO4_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO4_W 2 +#define AUX_AIODIO_IOMODE_IO4_M 0x00000300 +#define AUX_AIODIO_IOMODE_IO4_S 8 +#define AUX_AIODIO_IOMODE_IO4_OPEN_SOURCE 0x00000300 +#define AUX_AIODIO_IOMODE_IO4_OPEN_DRAIN 0x00000200 +#define AUX_AIODIO_IOMODE_IO4_IN 0x00000100 +#define AUX_AIODIO_IOMODE_IO4_OUT 0x00000000 // Field: [7:6] IO3 // @@ -274,13 +274,13 @@ // // GPIODOUT bit 3 drives // AUXIO[8i+3]. -#define AUX_AIODIO_IOMODE_IO3_W 2 -#define AUX_AIODIO_IOMODE_IO3_M 0x000000C0 -#define AUX_AIODIO_IOMODE_IO3_S 6 -#define AUX_AIODIO_IOMODE_IO3_OPEN_SOURCE 0x000000C0 -#define AUX_AIODIO_IOMODE_IO3_OPEN_DRAIN 0x00000080 -#define AUX_AIODIO_IOMODE_IO3_IN 0x00000040 -#define AUX_AIODIO_IOMODE_IO3_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO3_W 2 +#define AUX_AIODIO_IOMODE_IO3_M 0x000000C0 +#define AUX_AIODIO_IOMODE_IO3_S 6 +#define AUX_AIODIO_IOMODE_IO3_OPEN_SOURCE 0x000000C0 +#define AUX_AIODIO_IOMODE_IO3_OPEN_DRAIN 0x00000080 +#define AUX_AIODIO_IOMODE_IO3_IN 0x00000040 +#define AUX_AIODIO_IOMODE_IO3_OUT 0x00000000 // Field: [5:4] IO2 // @@ -314,13 +314,13 @@ // // GPIODOUT bit 2 drives // AUXIO[8i+2]. -#define AUX_AIODIO_IOMODE_IO2_W 2 -#define AUX_AIODIO_IOMODE_IO2_M 0x00000030 -#define AUX_AIODIO_IOMODE_IO2_S 4 -#define AUX_AIODIO_IOMODE_IO2_OPEN_SOURCE 0x00000030 -#define AUX_AIODIO_IOMODE_IO2_OPEN_DRAIN 0x00000020 -#define AUX_AIODIO_IOMODE_IO2_IN 0x00000010 -#define AUX_AIODIO_IOMODE_IO2_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO2_W 2 +#define AUX_AIODIO_IOMODE_IO2_M 0x00000030 +#define AUX_AIODIO_IOMODE_IO2_S 4 +#define AUX_AIODIO_IOMODE_IO2_OPEN_SOURCE 0x00000030 +#define AUX_AIODIO_IOMODE_IO2_OPEN_DRAIN 0x00000020 +#define AUX_AIODIO_IOMODE_IO2_IN 0x00000010 +#define AUX_AIODIO_IOMODE_IO2_OUT 0x00000000 // Field: [3:2] IO1 // @@ -354,13 +354,13 @@ // // GPIODOUT bit 1 drives // AUXIO[8i+1]. -#define AUX_AIODIO_IOMODE_IO1_W 2 -#define AUX_AIODIO_IOMODE_IO1_M 0x0000000C -#define AUX_AIODIO_IOMODE_IO1_S 2 -#define AUX_AIODIO_IOMODE_IO1_OPEN_SOURCE 0x0000000C -#define AUX_AIODIO_IOMODE_IO1_OPEN_DRAIN 0x00000008 -#define AUX_AIODIO_IOMODE_IO1_IN 0x00000004 -#define AUX_AIODIO_IOMODE_IO1_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO1_W 2 +#define AUX_AIODIO_IOMODE_IO1_M 0x0000000C +#define AUX_AIODIO_IOMODE_IO1_S 2 +#define AUX_AIODIO_IOMODE_IO1_OPEN_SOURCE 0x0000000C +#define AUX_AIODIO_IOMODE_IO1_OPEN_DRAIN 0x00000008 +#define AUX_AIODIO_IOMODE_IO1_IN 0x00000004 +#define AUX_AIODIO_IOMODE_IO1_OUT 0x00000000 // Field: [1:0] IO0 // @@ -394,13 +394,13 @@ // // GPIODOUT bit 0 drives // AUXIO[8i+0]. -#define AUX_AIODIO_IOMODE_IO0_W 2 -#define AUX_AIODIO_IOMODE_IO0_M 0x00000003 -#define AUX_AIODIO_IOMODE_IO0_S 0 -#define AUX_AIODIO_IOMODE_IO0_OPEN_SOURCE 0x00000003 -#define AUX_AIODIO_IOMODE_IO0_OPEN_DRAIN 0x00000002 -#define AUX_AIODIO_IOMODE_IO0_IN 0x00000001 -#define AUX_AIODIO_IOMODE_IO0_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO0_W 2 +#define AUX_AIODIO_IOMODE_IO0_M 0x00000003 +#define AUX_AIODIO_IOMODE_IO0_S 0 +#define AUX_AIODIO_IOMODE_IO0_OPEN_SOURCE 0x00000003 +#define AUX_AIODIO_IOMODE_IO0_OPEN_DRAIN 0x00000002 +#define AUX_AIODIO_IOMODE_IO0_IN 0x00000001 +#define AUX_AIODIO_IOMODE_IO0_OUT 0x00000000 //***************************************************************************** // @@ -411,9 +411,9 @@ // // Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit // n is set. Otherwise, bit n value is old. -#define AUX_AIODIO_GPIODIN_IO7_0_W 8 -#define AUX_AIODIO_GPIODIN_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODIN_IO7_0_S 0 +#define AUX_AIODIO_GPIODIN_IO7_0_W 8 +#define AUX_AIODIO_GPIODIN_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODIN_IO7_0_S 0 //***************************************************************************** // @@ -425,9 +425,9 @@ // Write 1 to bit index n in this bit vector to set GPIODOUT bit n. // // Read value is 0. -#define AUX_AIODIO_GPIODOUTSET_IO7_0_W 8 -#define AUX_AIODIO_GPIODOUTSET_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODOUTSET_IO7_0_S 0 +#define AUX_AIODIO_GPIODOUTSET_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTSET_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTSET_IO7_0_S 0 //***************************************************************************** // @@ -439,9 +439,9 @@ // Write 1 to bit index n in this bit vector to clear GPIODOUT bit n. // // Read value is 0. -#define AUX_AIODIO_GPIODOUTCLR_IO7_0_W 8 -#define AUX_AIODIO_GPIODOUTCLR_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODOUTCLR_IO7_0_S 0 +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_S 0 //***************************************************************************** // @@ -453,9 +453,9 @@ // Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n. // // Read value is 0. -#define AUX_AIODIO_GPIODOUTTGL_IO7_0_W 8 -#define AUX_AIODIO_GPIODOUTTGL_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODOUTTGL_IO7_0_S 0 +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_S 0 //***************************************************************************** // @@ -473,9 +473,8 @@ // value in GPIODIN. // You must disable the digital input buffer for analog input or pins that // float to avoid current leakage. -#define AUX_AIODIO_GPIODIE_IO7_0_W 8 -#define AUX_AIODIO_GPIODIE_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODIE_IO7_0_S 0 - +#define AUX_AIODIO_GPIODIE_IO7_0_W 8 +#define AUX_AIODIO_GPIODIE_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODIE_IO7_0_S 0 #endif // __AUX_AIODIO__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_anaif.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_anaif.h index f96db07..52a8103 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_anaif.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_anaif.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_anaif_h -* Revised: 2017-05-30 11:42:02 +0200 (Tue, 30 May 2017) -* Revision: 49074 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_anaif_h + * Revised: 2017-05-30 11:42:02 +0200 (Tue, 30 May 2017) + * Revision: 49074 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_ANAIF_H__ #define __HW_AUX_ANAIF_H__ @@ -44,19 +44,19 @@ // //***************************************************************************** // ADC Control -#define AUX_ANAIF_O_ADCCTL 0x00000010 +#define AUX_ANAIF_O_ADCCTL 0x00000010 // ADC FIFO Status -#define AUX_ANAIF_O_ADCFIFOSTAT 0x00000014 +#define AUX_ANAIF_O_ADCFIFOSTAT 0x00000014 // ADC FIFO -#define AUX_ANAIF_O_ADCFIFO 0x00000018 +#define AUX_ANAIF_O_ADCFIFO 0x00000018 // ADC Trigger -#define AUX_ANAIF_O_ADCTRIG 0x0000001C +#define AUX_ANAIF_O_ADCTRIG 0x0000001C // Current Source Control -#define AUX_ANAIF_O_ISRCCTL 0x00000020 +#define AUX_ANAIF_O_ISRCCTL 0x00000020 //***************************************************************************** // @@ -69,12 +69,12 @@ // ENUMs: // FALL Set ADC trigger on falling edge of event source. // RISE Set ADC trigger on rising edge of event source. -#define AUX_ANAIF_ADCCTL_START_POL 0x00002000 -#define AUX_ANAIF_ADCCTL_START_POL_BITN 13 -#define AUX_ANAIF_ADCCTL_START_POL_M 0x00002000 -#define AUX_ANAIF_ADCCTL_START_POL_S 13 -#define AUX_ANAIF_ADCCTL_START_POL_FALL 0x00002000 -#define AUX_ANAIF_ADCCTL_START_POL_RISE 0x00000000 +#define AUX_ANAIF_ADCCTL_START_POL 0x00002000 +#define AUX_ANAIF_ADCCTL_START_POL_BITN 13 +#define AUX_ANAIF_ADCCTL_START_POL_M 0x00002000 +#define AUX_ANAIF_ADCCTL_START_POL_S 13 +#define AUX_ANAIF_ADCCTL_START_POL_FALL 0x00002000 +#define AUX_ANAIF_ADCCTL_START_POL_RISE 0x00000000 // Field: [12:8] START_SRC // @@ -115,41 +115,41 @@ // AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB // AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA // RTC_CH2_EV AUX_EVCTL:EVSTAT0.AON_RTC_CH2 -#define AUX_ANAIF_ADCCTL_START_SRC_W 5 -#define AUX_ANAIF_ADCCTL_START_SRC_M 0x00001F00 -#define AUX_ANAIF_ADCCTL_START_SRC_S 8 -#define AUX_ANAIF_ADCCTL_START_SRC_ADC_IRQ 0x00001F00 -#define AUX_ANAIF_ADCCTL_START_SRC_MCU_EV 0x00001E00 -#define AUX_ANAIF_ADCCTL_START_SRC_ACLK_REF 0x00001D00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO15 0x00001C00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO14 0x00001B00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO13 0x00001A00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO12 0x00001900 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO11 0x00001800 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO10 0x00001700 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO9 0x00001600 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO8 0x00001500 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO7 0x00001400 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO6 0x00001300 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO5 0x00001200 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO4 0x00001100 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO3 0x00001000 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO2 0x00000F00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO1 0x00000E00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO0 0x00000D00 -#define AUX_ANAIF_ADCCTL_START_SRC_AON_PROG_WU 0x00000C00 -#define AUX_ANAIF_ADCCTL_START_SRC_AON_SW 0x00000B00 -#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT1 0x00000A00 -#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT0 0x00000900 -#define AUX_ANAIF_ADCCTL_START_SRC_RESERVED1 0x00000800 -#define AUX_ANAIF_ADCCTL_START_SRC_RESERVED0 0x00000700 -#define AUX_ANAIF_ADCCTL_START_SRC_SMPH_AUTOTAKE_DONE 0x00000600 -#define AUX_ANAIF_ADCCTL_START_SRC_TIMER1_EV 0x00000500 -#define AUX_ANAIF_ADCCTL_START_SRC_TIMER0_EV 0x00000400 -#define AUX_ANAIF_ADCCTL_START_SRC_TDC_DONE 0x00000300 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPB 0x00000200 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPA 0x00000100 -#define AUX_ANAIF_ADCCTL_START_SRC_RTC_CH2_EV 0x00000000 +#define AUX_ANAIF_ADCCTL_START_SRC_W 5 +#define AUX_ANAIF_ADCCTL_START_SRC_M 0x00001F00 +#define AUX_ANAIF_ADCCTL_START_SRC_S 8 +#define AUX_ANAIF_ADCCTL_START_SRC_ADC_IRQ 0x00001F00 +#define AUX_ANAIF_ADCCTL_START_SRC_MCU_EV 0x00001E00 +#define AUX_ANAIF_ADCCTL_START_SRC_ACLK_REF 0x00001D00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO15 0x00001C00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO14 0x00001B00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO13 0x00001A00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO12 0x00001900 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO11 0x00001800 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO10 0x00001700 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO9 0x00001600 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO8 0x00001500 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO7 0x00001400 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO6 0x00001300 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO5 0x00001200 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO4 0x00001100 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO3 0x00001000 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO2 0x00000F00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO1 0x00000E00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO0 0x00000D00 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_PROG_WU 0x00000C00 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_SW 0x00000B00 +#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT1 0x00000A00 +#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT0 0x00000900 +#define AUX_ANAIF_ADCCTL_START_SRC_RESERVED1 0x00000800 +#define AUX_ANAIF_ADCCTL_START_SRC_RESERVED0 0x00000700 +#define AUX_ANAIF_ADCCTL_START_SRC_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_ANAIF_ADCCTL_START_SRC_TIMER1_EV 0x00000500 +#define AUX_ANAIF_ADCCTL_START_SRC_TIMER0_EV 0x00000400 +#define AUX_ANAIF_ADCCTL_START_SRC_TDC_DONE 0x00000300 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPB 0x00000200 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPA 0x00000100 +#define AUX_ANAIF_ADCCTL_START_SRC_RTC_CH2_EV 0x00000000 // Field: [1:0] CMD // @@ -167,12 +167,12 @@ // clock cycles before it sets CMD to EN or DIS. // EN Enable ADC interface. // DIS Disable ADC interface. -#define AUX_ANAIF_ADCCTL_CMD_W 2 -#define AUX_ANAIF_ADCCTL_CMD_M 0x00000003 -#define AUX_ANAIF_ADCCTL_CMD_S 0 -#define AUX_ANAIF_ADCCTL_CMD_FLUSH 0x00000003 -#define AUX_ANAIF_ADCCTL_CMD_EN 0x00000001 -#define AUX_ANAIF_ADCCTL_CMD_DIS 0x00000000 +#define AUX_ANAIF_ADCCTL_CMD_W 2 +#define AUX_ANAIF_ADCCTL_CMD_M 0x00000003 +#define AUX_ANAIF_ADCCTL_CMD_S 0 +#define AUX_ANAIF_ADCCTL_CMD_FLUSH 0x00000003 +#define AUX_ANAIF_ADCCTL_CMD_EN 0x00000001 +#define AUX_ANAIF_ADCCTL_CMD_DIS 0x00000000 //***************************************************************************** // @@ -188,10 +188,10 @@ // // When the flag is set, the ADC FIFO write pointer is static. It is not // possible to add more samples to the ADC FIFO. Flush FIFO to clear the flag. -#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW 0x00000010 -#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_BITN 4 -#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M 0x00000010 -#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_S 4 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW 0x00000010 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_BITN 4 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M 0x00000010 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_S 4 // Field: [3] UNDERFLOW // @@ -202,10 +202,10 @@ // // When the flag is set, the ADC FIFO read pointer is static. Read returns the // previous sample that was read. Flush FIFO to clear the flag. -#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW 0x00000008 -#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_BITN 3 -#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M 0x00000008 -#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_S 3 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW 0x00000008 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_BITN 3 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M 0x00000008 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_S 3 // Field: [2] FULL // @@ -216,10 +216,10 @@ // // When the flag is set, it is not possible to add more samples to the ADC // FIFO. An attempt to add samples sets the OVERFLOW flag. -#define AUX_ANAIF_ADCFIFOSTAT_FULL 0x00000004 -#define AUX_ANAIF_ADCFIFOSTAT_FULL_BITN 2 -#define AUX_ANAIF_ADCFIFOSTAT_FULL_M 0x00000004 -#define AUX_ANAIF_ADCFIFOSTAT_FULL_S 2 +#define AUX_ANAIF_ADCFIFOSTAT_FULL 0x00000004 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_BITN 2 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_M 0x00000004 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_S 2 // Field: [1] ALMOST_FULL // @@ -228,10 +228,10 @@ // 0: There are less than 3 samples in the FIFO, or the FIFO is full. The FULL // flag is also asserted in the latter case. // 1: There are 3 samples in the FIFO, there is room for one more sample. -#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL 0x00000002 -#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_BITN 1 -#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M 0x00000002 -#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_S 1 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL 0x00000002 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_BITN 1 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M 0x00000002 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_S 1 // Field: [0] EMPTY // @@ -242,10 +242,10 @@ // // When the flag is set, read returns the previous sample that was read and // sets the UNDERFLOW flag. -#define AUX_ANAIF_ADCFIFOSTAT_EMPTY 0x00000001 -#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_BITN 0 -#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_M 0x00000001 -#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_S 0 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY 0x00000001 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_BITN 0 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_M 0x00000001 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_S 0 //***************************************************************************** // @@ -262,9 +262,9 @@ // Write: // Write dummy sample to FIFO. This is useful for code development when you do // not have real ADC samples. -#define AUX_ANAIF_ADCFIFO_DATA_W 12 -#define AUX_ANAIF_ADCFIFO_DATA_M 0x00000FFF -#define AUX_ANAIF_ADCFIFO_DATA_S 0 +#define AUX_ANAIF_ADCFIFO_DATA_W 12 +#define AUX_ANAIF_ADCFIFO_DATA_M 0x00000FFF +#define AUX_ANAIF_ADCFIFO_DATA_S 0 //***************************************************************************** // @@ -280,10 +280,10 @@ // // To manually trigger the ADC, you must set ADCCTL.START_SRC to NO_EVENT to // avoid conflict with event-driven ADC trigger. -#define AUX_ANAIF_ADCTRIG_START 0x00000001 -#define AUX_ANAIF_ADCTRIG_START_BITN 0 -#define AUX_ANAIF_ADCTRIG_START_M 0x00000001 -#define AUX_ANAIF_ADCTRIG_START_S 0 +#define AUX_ANAIF_ADCTRIG_START 0x00000001 +#define AUX_ANAIF_ADCTRIG_START_BITN 0 +#define AUX_ANAIF_ADCTRIG_START_M 0x00000001 +#define AUX_ANAIF_ADCTRIG_START_S 0 //***************************************************************************** // @@ -296,10 +296,9 @@ // // 0: ISRC drives 0 uA. // 1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN. -#define AUX_ANAIF_ISRCCTL_RESET_N 0x00000001 -#define AUX_ANAIF_ISRCCTL_RESET_N_BITN 0 -#define AUX_ANAIF_ISRCCTL_RESET_N_M 0x00000001 -#define AUX_ANAIF_ISRCCTL_RESET_N_S 0 - +#define AUX_ANAIF_ISRCCTL_RESET_N 0x00000001 +#define AUX_ANAIF_ISRCCTL_RESET_N_BITN 0 +#define AUX_ANAIF_ISRCCTL_RESET_N_M 0x00000001 +#define AUX_ANAIF_ISRCCTL_RESET_N_S 0 #endif // __AUX_ANAIF__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_evctl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_evctl.h index 0969dfc..188554b 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_evctl.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_evctl.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_evctl_h -* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) -* Revision: 49005 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_evctl_h + * Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) + * Revision: 49005 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_EVCTL_H__ #define __HW_AUX_EVCTL_H__ @@ -44,52 +44,52 @@ // //***************************************************************************** // Vector Configuration 0 -#define AUX_EVCTL_O_VECCFG0 0x00000000 +#define AUX_EVCTL_O_VECCFG0 0x00000000 // Vector Configuration 1 -#define AUX_EVCTL_O_VECCFG1 0x00000004 +#define AUX_EVCTL_O_VECCFG1 0x00000004 // Sensor Controller Engine Wait Event Selection -#define AUX_EVCTL_O_SCEWEVSEL 0x00000008 +#define AUX_EVCTL_O_SCEWEVSEL 0x00000008 // Events To AON Flags -#define AUX_EVCTL_O_EVTOAONFLAGS 0x0000000C +#define AUX_EVCTL_O_EVTOAONFLAGS 0x0000000C // Events To AON Polarity -#define AUX_EVCTL_O_EVTOAONPOL 0x00000010 +#define AUX_EVCTL_O_EVTOAONPOL 0x00000010 // Direct Memory Access Control -#define AUX_EVCTL_O_DMACTL 0x00000014 +#define AUX_EVCTL_O_DMACTL 0x00000014 // Software Event Set -#define AUX_EVCTL_O_SWEVSET 0x00000018 +#define AUX_EVCTL_O_SWEVSET 0x00000018 // Event Status 0 -#define AUX_EVCTL_O_EVSTAT0 0x0000001C +#define AUX_EVCTL_O_EVSTAT0 0x0000001C // Event Status 1 -#define AUX_EVCTL_O_EVSTAT1 0x00000020 +#define AUX_EVCTL_O_EVSTAT1 0x00000020 // Event To MCU Polarity -#define AUX_EVCTL_O_EVTOMCUPOL 0x00000024 +#define AUX_EVCTL_O_EVTOMCUPOL 0x00000024 // Events to MCU Flags -#define AUX_EVCTL_O_EVTOMCUFLAGS 0x00000028 +#define AUX_EVCTL_O_EVTOMCUFLAGS 0x00000028 // Combined Event To MCU Mask -#define AUX_EVCTL_O_COMBEVTOMCUMASK 0x0000002C +#define AUX_EVCTL_O_COMBEVTOMCUMASK 0x0000002C // Vector Flags -#define AUX_EVCTL_O_VECFLAGS 0x00000034 +#define AUX_EVCTL_O_VECFLAGS 0x00000034 // Events To MCU Flags Clear -#define AUX_EVCTL_O_EVTOMCUFLAGSCLR 0x00000038 +#define AUX_EVCTL_O_EVTOMCUFLAGSCLR 0x00000038 // Events To AON Clear -#define AUX_EVCTL_O_EVTOAONFLAGSCLR 0x0000003C +#define AUX_EVCTL_O_EVTOAONFLAGSCLR 0x0000003C // Vector Flags Clear -#define AUX_EVCTL_O_VECFLAGSCLR 0x00000040 +#define AUX_EVCTL_O_VECFLAGSCLR 0x00000040 //***************************************************************************** // @@ -107,12 +107,12 @@ // ENUMs: // FALL Falling edge triggers vector 1 execution. // RISE Rising edge triggers vector 1 execution. -#define AUX_EVCTL_VECCFG0_VEC1_POL 0x00004000 -#define AUX_EVCTL_VECCFG0_VEC1_POL_BITN 14 -#define AUX_EVCTL_VECCFG0_VEC1_POL_M 0x00004000 -#define AUX_EVCTL_VECCFG0_VEC1_POL_S 14 -#define AUX_EVCTL_VECCFG0_VEC1_POL_FALL 0x00004000 -#define AUX_EVCTL_VECCFG0_VEC1_POL_RISE 0x00000000 +#define AUX_EVCTL_VECCFG0_VEC1_POL 0x00004000 +#define AUX_EVCTL_VECCFG0_VEC1_POL_BITN 14 +#define AUX_EVCTL_VECCFG0_VEC1_POL_M 0x00004000 +#define AUX_EVCTL_VECCFG0_VEC1_POL_S 14 +#define AUX_EVCTL_VECCFG0_VEC1_POL_FALL 0x00004000 +#define AUX_EVCTL_VECCFG0_VEC1_POL_RISE 0x00000000 // Field: [13] VEC1_EN // @@ -125,12 +125,12 @@ // ENUMs: // EN Enable vector 1 trigger. // DIS Disable vector 1 trigger. -#define AUX_EVCTL_VECCFG0_VEC1_EN 0x00002000 -#define AUX_EVCTL_VECCFG0_VEC1_EN_BITN 13 -#define AUX_EVCTL_VECCFG0_VEC1_EN_M 0x00002000 -#define AUX_EVCTL_VECCFG0_VEC1_EN_S 13 -#define AUX_EVCTL_VECCFG0_VEC1_EN_EN 0x00002000 -#define AUX_EVCTL_VECCFG0_VEC1_EN_DIS 0x00000000 +#define AUX_EVCTL_VECCFG0_VEC1_EN 0x00002000 +#define AUX_EVCTL_VECCFG0_VEC1_EN_BITN 13 +#define AUX_EVCTL_VECCFG0_VEC1_EN_M 0x00002000 +#define AUX_EVCTL_VECCFG0_VEC1_EN_S 13 +#define AUX_EVCTL_VECCFG0_VEC1_EN_EN 0x00002000 +#define AUX_EVCTL_VECCFG0_VEC1_EN_DIS 0x00000000 // Field: [12:8] VEC1_EV // @@ -168,41 +168,41 @@ // AUX_COMPB EVSTAT0.AUX_COMPB // AUX_COMPA EVSTAT0.AUX_COMPA // AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 -#define AUX_EVCTL_VECCFG0_VEC1_EV_W 5 -#define AUX_EVCTL_VECCFG0_VEC1_EV_M 0x00001F00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_S 8 -#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_IRQ 0x00001F00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_MCU_EV 0x00001E00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_ACLK_REF 0x00001D00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO15 0x00001C00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO14 0x00001B00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO13 0x00001A00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO12 0x00001900 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO11 0x00001800 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO10 0x00001700 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO9 0x00001600 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO8 0x00001500 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO7 0x00001400 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO6 0x00001300 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO5 0x00001200 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO4 0x00001100 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO3 0x00001000 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO2 0x00000F00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO1 0x00000E00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO0 0x00000D00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_PROG_WU 0x00000C00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_SW 0x00000B00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_OBSMUX1 0x00000A00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_OBSMUX0 0x00000900 -#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_FIFO_ALMOST_FULL 0x00000800 -#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_DONE 0x00000700 -#define AUX_EVCTL_VECCFG0_VEC1_EV_SMPH_AUTOTAKE_DONE 0x00000600 -#define AUX_EVCTL_VECCFG0_VEC1_EV_TIMER1_EV 0x00000500 -#define AUX_EVCTL_VECCFG0_VEC1_EV_TIMER0_EV 0x00000400 -#define AUX_EVCTL_VECCFG0_VEC1_EV_TDC_DONE 0x00000300 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUX_COMPB 0x00000200 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUX_COMPA 0x00000100 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_RTC_CH2 0x00000000 +#define AUX_EVCTL_VECCFG0_VEC1_EV_W 5 +#define AUX_EVCTL_VECCFG0_VEC1_EV_M 0x00001F00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_S 8 +#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_IRQ 0x00001F00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_MCU_EV 0x00001E00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_ACLK_REF 0x00001D00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO15 0x00001C00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO14 0x00001B00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO13 0x00001A00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO12 0x00001900 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO11 0x00001800 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO10 0x00001700 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO9 0x00001600 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO8 0x00001500 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO7 0x00001400 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO6 0x00001300 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO5 0x00001200 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO4 0x00001100 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO3 0x00001000 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO2 0x00000F00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO1 0x00000E00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO0 0x00000D00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_PROG_WU 0x00000C00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_SW 0x00000B00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_OBSMUX1 0x00000A00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_OBSMUX0 0x00000900 +#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_FIFO_ALMOST_FULL 0x00000800 +#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_DONE 0x00000700 +#define AUX_EVCTL_VECCFG0_VEC1_EV_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_EVCTL_VECCFG0_VEC1_EV_TIMER1_EV 0x00000500 +#define AUX_EVCTL_VECCFG0_VEC1_EV_TIMER0_EV 0x00000400 +#define AUX_EVCTL_VECCFG0_VEC1_EV_TDC_DONE 0x00000300 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUX_COMPB 0x00000200 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUX_COMPA 0x00000100 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_RTC_CH2 0x00000000 // Field: [6] VEC0_POL // @@ -215,12 +215,12 @@ // ENUMs: // FALL Falling edge triggers vector 0 execution. // RISE Rising edge triggers vector 0 execution. -#define AUX_EVCTL_VECCFG0_VEC0_POL 0x00000040 -#define AUX_EVCTL_VECCFG0_VEC0_POL_BITN 6 -#define AUX_EVCTL_VECCFG0_VEC0_POL_M 0x00000040 -#define AUX_EVCTL_VECCFG0_VEC0_POL_S 6 -#define AUX_EVCTL_VECCFG0_VEC0_POL_FALL 0x00000040 -#define AUX_EVCTL_VECCFG0_VEC0_POL_RISE 0x00000000 +#define AUX_EVCTL_VECCFG0_VEC0_POL 0x00000040 +#define AUX_EVCTL_VECCFG0_VEC0_POL_BITN 6 +#define AUX_EVCTL_VECCFG0_VEC0_POL_M 0x00000040 +#define AUX_EVCTL_VECCFG0_VEC0_POL_S 6 +#define AUX_EVCTL_VECCFG0_VEC0_POL_FALL 0x00000040 +#define AUX_EVCTL_VECCFG0_VEC0_POL_RISE 0x00000000 // Field: [5] VEC0_EN // @@ -231,12 +231,12 @@ // ENUMs: // EN Enable vector 0 trigger. // DIS Disable vector 0 trigger. -#define AUX_EVCTL_VECCFG0_VEC0_EN 0x00000020 -#define AUX_EVCTL_VECCFG0_VEC0_EN_BITN 5 -#define AUX_EVCTL_VECCFG0_VEC0_EN_M 0x00000020 -#define AUX_EVCTL_VECCFG0_VEC0_EN_S 5 -#define AUX_EVCTL_VECCFG0_VEC0_EN_EN 0x00000020 -#define AUX_EVCTL_VECCFG0_VEC0_EN_DIS 0x00000000 +#define AUX_EVCTL_VECCFG0_VEC0_EN 0x00000020 +#define AUX_EVCTL_VECCFG0_VEC0_EN_BITN 5 +#define AUX_EVCTL_VECCFG0_VEC0_EN_M 0x00000020 +#define AUX_EVCTL_VECCFG0_VEC0_EN_S 5 +#define AUX_EVCTL_VECCFG0_VEC0_EN_EN 0x00000020 +#define AUX_EVCTL_VECCFG0_VEC0_EN_DIS 0x00000000 // Field: [4:0] VEC0_EV // @@ -274,41 +274,41 @@ // AUX_COMPB EVSTAT0.AUX_COMPB // AUX_COMPA EVSTAT0.AUX_COMPA // AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 -#define AUX_EVCTL_VECCFG0_VEC0_EV_W 5 -#define AUX_EVCTL_VECCFG0_VEC0_EV_M 0x0000001F -#define AUX_EVCTL_VECCFG0_VEC0_EV_S 0 -#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_IRQ 0x0000001F -#define AUX_EVCTL_VECCFG0_VEC0_EV_MCU_EV 0x0000001E -#define AUX_EVCTL_VECCFG0_VEC0_EV_ACLK_REF 0x0000001D -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO15 0x0000001C -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO14 0x0000001B -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO13 0x0000001A -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO12 0x00000019 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO11 0x00000018 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO10 0x00000017 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO9 0x00000016 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO8 0x00000015 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO7 0x00000014 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO6 0x00000013 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO5 0x00000012 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO4 0x00000011 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO3 0x00000010 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO2 0x0000000F -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO1 0x0000000E -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO0 0x0000000D -#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_PROG_WU 0x0000000C -#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_SW 0x0000000B -#define AUX_EVCTL_VECCFG0_VEC0_EV_OBSMUX1 0x0000000A -#define AUX_EVCTL_VECCFG0_VEC0_EV_OBSMUX0 0x00000009 -#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_FIFO_ALMOST_FULL 0x00000008 -#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_DONE 0x00000007 -#define AUX_EVCTL_VECCFG0_VEC0_EV_SMPH_AUTOTAKE_DONE 0x00000006 -#define AUX_EVCTL_VECCFG0_VEC0_EV_TIMER1_EV 0x00000005 -#define AUX_EVCTL_VECCFG0_VEC0_EV_TIMER0_EV 0x00000004 -#define AUX_EVCTL_VECCFG0_VEC0_EV_TDC_DONE 0x00000003 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUX_COMPB 0x00000002 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUX_COMPA 0x00000001 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_RTC_CH2 0x00000000 +#define AUX_EVCTL_VECCFG0_VEC0_EV_W 5 +#define AUX_EVCTL_VECCFG0_VEC0_EV_M 0x0000001F +#define AUX_EVCTL_VECCFG0_VEC0_EV_S 0 +#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_IRQ 0x0000001F +#define AUX_EVCTL_VECCFG0_VEC0_EV_MCU_EV 0x0000001E +#define AUX_EVCTL_VECCFG0_VEC0_EV_ACLK_REF 0x0000001D +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO15 0x0000001C +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO14 0x0000001B +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO13 0x0000001A +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO12 0x00000019 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO11 0x00000018 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO10 0x00000017 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO9 0x00000016 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO8 0x00000015 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO7 0x00000014 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO6 0x00000013 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO5 0x00000012 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO4 0x00000011 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO3 0x00000010 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO2 0x0000000F +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO1 0x0000000E +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO0 0x0000000D +#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_PROG_WU 0x0000000C +#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_SW 0x0000000B +#define AUX_EVCTL_VECCFG0_VEC0_EV_OBSMUX1 0x0000000A +#define AUX_EVCTL_VECCFG0_VEC0_EV_OBSMUX0 0x00000009 +#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_DONE 0x00000007 +#define AUX_EVCTL_VECCFG0_VEC0_EV_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_EVCTL_VECCFG0_VEC0_EV_TIMER1_EV 0x00000005 +#define AUX_EVCTL_VECCFG0_VEC0_EV_TIMER0_EV 0x00000004 +#define AUX_EVCTL_VECCFG0_VEC0_EV_TDC_DONE 0x00000003 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUX_COMPB 0x00000002 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUX_COMPA 0x00000001 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_RTC_CH2 0x00000000 //***************************************************************************** // @@ -326,12 +326,12 @@ // ENUMs: // FALL Falling edge triggers vector 3 execution. // RISE Rising edge triggers vector 3 execution. -#define AUX_EVCTL_VECCFG1_VEC3_POL 0x00004000 -#define AUX_EVCTL_VECCFG1_VEC3_POL_BITN 14 -#define AUX_EVCTL_VECCFG1_VEC3_POL_M 0x00004000 -#define AUX_EVCTL_VECCFG1_VEC3_POL_S 14 -#define AUX_EVCTL_VECCFG1_VEC3_POL_FALL 0x00004000 -#define AUX_EVCTL_VECCFG1_VEC3_POL_RISE 0x00000000 +#define AUX_EVCTL_VECCFG1_VEC3_POL 0x00004000 +#define AUX_EVCTL_VECCFG1_VEC3_POL_BITN 14 +#define AUX_EVCTL_VECCFG1_VEC3_POL_M 0x00004000 +#define AUX_EVCTL_VECCFG1_VEC3_POL_S 14 +#define AUX_EVCTL_VECCFG1_VEC3_POL_FALL 0x00004000 +#define AUX_EVCTL_VECCFG1_VEC3_POL_RISE 0x00000000 // Field: [13] VEC3_EN // @@ -344,12 +344,12 @@ // ENUMs: // EN Enable vector 3 trigger. // DIS Disable vector 3 trigger. -#define AUX_EVCTL_VECCFG1_VEC3_EN 0x00002000 -#define AUX_EVCTL_VECCFG1_VEC3_EN_BITN 13 -#define AUX_EVCTL_VECCFG1_VEC3_EN_M 0x00002000 -#define AUX_EVCTL_VECCFG1_VEC3_EN_S 13 -#define AUX_EVCTL_VECCFG1_VEC3_EN_EN 0x00002000 -#define AUX_EVCTL_VECCFG1_VEC3_EN_DIS 0x00000000 +#define AUX_EVCTL_VECCFG1_VEC3_EN 0x00002000 +#define AUX_EVCTL_VECCFG1_VEC3_EN_BITN 13 +#define AUX_EVCTL_VECCFG1_VEC3_EN_M 0x00002000 +#define AUX_EVCTL_VECCFG1_VEC3_EN_S 13 +#define AUX_EVCTL_VECCFG1_VEC3_EN_EN 0x00002000 +#define AUX_EVCTL_VECCFG1_VEC3_EN_DIS 0x00000000 // Field: [12:8] VEC3_EV // @@ -387,41 +387,41 @@ // AUX_COMPB EVSTAT0.AUX_COMPB // AUX_COMPA EVSTAT0.AUX_COMPA // AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 -#define AUX_EVCTL_VECCFG1_VEC3_EV_W 5 -#define AUX_EVCTL_VECCFG1_VEC3_EV_M 0x00001F00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_S 8 -#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_IRQ 0x00001F00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_MCU_EV 0x00001E00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_ACLK_REF 0x00001D00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO15 0x00001C00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO14 0x00001B00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO13 0x00001A00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO12 0x00001900 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO11 0x00001800 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO10 0x00001700 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO9 0x00001600 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO8 0x00001500 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO7 0x00001400 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO6 0x00001300 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO5 0x00001200 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO4 0x00001100 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO3 0x00001000 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO2 0x00000F00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO1 0x00000E00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO0 0x00000D00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_PROG_WU 0x00000C00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_SW 0x00000B00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_OBSMUX1 0x00000A00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_OBSMUX0 0x00000900 -#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_FIFO_ALMOST_FULL 0x00000800 -#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_DONE 0x00000700 -#define AUX_EVCTL_VECCFG1_VEC3_EV_SMPH_AUTOTAKE_DONE 0x00000600 -#define AUX_EVCTL_VECCFG1_VEC3_EV_TIMER1_EV 0x00000500 -#define AUX_EVCTL_VECCFG1_VEC3_EV_TIMER0_EV 0x00000400 -#define AUX_EVCTL_VECCFG1_VEC3_EV_TDC_DONE 0x00000300 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUX_COMPB 0x00000200 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUX_COMPA 0x00000100 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_RTC_CH2 0x00000000 +#define AUX_EVCTL_VECCFG1_VEC3_EV_W 5 +#define AUX_EVCTL_VECCFG1_VEC3_EV_M 0x00001F00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_S 8 +#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_IRQ 0x00001F00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_MCU_EV 0x00001E00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_ACLK_REF 0x00001D00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO15 0x00001C00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO14 0x00001B00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO13 0x00001A00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO12 0x00001900 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO11 0x00001800 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO10 0x00001700 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO9 0x00001600 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO8 0x00001500 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO7 0x00001400 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO6 0x00001300 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO5 0x00001200 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO4 0x00001100 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO3 0x00001000 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO2 0x00000F00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO1 0x00000E00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO0 0x00000D00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_PROG_WU 0x00000C00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_SW 0x00000B00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_OBSMUX1 0x00000A00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_OBSMUX0 0x00000900 +#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_FIFO_ALMOST_FULL 0x00000800 +#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_DONE 0x00000700 +#define AUX_EVCTL_VECCFG1_VEC3_EV_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_EVCTL_VECCFG1_VEC3_EV_TIMER1_EV 0x00000500 +#define AUX_EVCTL_VECCFG1_VEC3_EV_TIMER0_EV 0x00000400 +#define AUX_EVCTL_VECCFG1_VEC3_EV_TDC_DONE 0x00000300 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUX_COMPB 0x00000200 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUX_COMPA 0x00000100 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_RTC_CH2 0x00000000 // Field: [6] VEC2_POL // @@ -434,12 +434,12 @@ // ENUMs: // FALL Falling edge triggers vector 2 execution. // RISE Rising edge triggers vector 2 execution. -#define AUX_EVCTL_VECCFG1_VEC2_POL 0x00000040 -#define AUX_EVCTL_VECCFG1_VEC2_POL_BITN 6 -#define AUX_EVCTL_VECCFG1_VEC2_POL_M 0x00000040 -#define AUX_EVCTL_VECCFG1_VEC2_POL_S 6 -#define AUX_EVCTL_VECCFG1_VEC2_POL_FALL 0x00000040 -#define AUX_EVCTL_VECCFG1_VEC2_POL_RISE 0x00000000 +#define AUX_EVCTL_VECCFG1_VEC2_POL 0x00000040 +#define AUX_EVCTL_VECCFG1_VEC2_POL_BITN 6 +#define AUX_EVCTL_VECCFG1_VEC2_POL_M 0x00000040 +#define AUX_EVCTL_VECCFG1_VEC2_POL_S 6 +#define AUX_EVCTL_VECCFG1_VEC2_POL_FALL 0x00000040 +#define AUX_EVCTL_VECCFG1_VEC2_POL_RISE 0x00000000 // Field: [5] VEC2_EN // @@ -452,12 +452,12 @@ // ENUMs: // EN Enable vector 2 trigger. // DIS Disable vector 2 trigger. -#define AUX_EVCTL_VECCFG1_VEC2_EN 0x00000020 -#define AUX_EVCTL_VECCFG1_VEC2_EN_BITN 5 -#define AUX_EVCTL_VECCFG1_VEC2_EN_M 0x00000020 -#define AUX_EVCTL_VECCFG1_VEC2_EN_S 5 -#define AUX_EVCTL_VECCFG1_VEC2_EN_EN 0x00000020 -#define AUX_EVCTL_VECCFG1_VEC2_EN_DIS 0x00000000 +#define AUX_EVCTL_VECCFG1_VEC2_EN 0x00000020 +#define AUX_EVCTL_VECCFG1_VEC2_EN_BITN 5 +#define AUX_EVCTL_VECCFG1_VEC2_EN_M 0x00000020 +#define AUX_EVCTL_VECCFG1_VEC2_EN_S 5 +#define AUX_EVCTL_VECCFG1_VEC2_EN_EN 0x00000020 +#define AUX_EVCTL_VECCFG1_VEC2_EN_DIS 0x00000000 // Field: [4:0] VEC2_EV // @@ -495,41 +495,41 @@ // AUX_COMPB EVSTAT0.AUX_COMPB // AUX_COMPA EVSTAT0.AUX_COMPA // AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 -#define AUX_EVCTL_VECCFG1_VEC2_EV_W 5 -#define AUX_EVCTL_VECCFG1_VEC2_EV_M 0x0000001F -#define AUX_EVCTL_VECCFG1_VEC2_EV_S 0 -#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_IRQ 0x0000001F -#define AUX_EVCTL_VECCFG1_VEC2_EV_MCU_EV 0x0000001E -#define AUX_EVCTL_VECCFG1_VEC2_EV_ACLK_REF 0x0000001D -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO15 0x0000001C -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO14 0x0000001B -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO13 0x0000001A -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO12 0x00000019 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO11 0x00000018 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO10 0x00000017 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO9 0x00000016 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO8 0x00000015 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO7 0x00000014 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO6 0x00000013 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO5 0x00000012 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO4 0x00000011 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO3 0x00000010 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO2 0x0000000F -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO1 0x0000000E -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO0 0x0000000D -#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_PROG_WU 0x0000000C -#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_SW 0x0000000B -#define AUX_EVCTL_VECCFG1_VEC2_EV_OBSMUX1 0x0000000A -#define AUX_EVCTL_VECCFG1_VEC2_EV_OBSMUX0 0x00000009 -#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_FIFO_ALMOST_FULL 0x00000008 -#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_DONE 0x00000007 -#define AUX_EVCTL_VECCFG1_VEC2_EV_SMPH_AUTOTAKE_DONE 0x00000006 -#define AUX_EVCTL_VECCFG1_VEC2_EV_TIMER1_EV 0x00000005 -#define AUX_EVCTL_VECCFG1_VEC2_EV_TIMER0_EV 0x00000004 -#define AUX_EVCTL_VECCFG1_VEC2_EV_TDC_DONE 0x00000003 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUX_COMPB 0x00000002 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUX_COMPA 0x00000001 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_RTC_CH2 0x00000000 +#define AUX_EVCTL_VECCFG1_VEC2_EV_W 5 +#define AUX_EVCTL_VECCFG1_VEC2_EV_M 0x0000001F +#define AUX_EVCTL_VECCFG1_VEC2_EV_S 0 +#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_IRQ 0x0000001F +#define AUX_EVCTL_VECCFG1_VEC2_EV_MCU_EV 0x0000001E +#define AUX_EVCTL_VECCFG1_VEC2_EV_ACLK_REF 0x0000001D +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO15 0x0000001C +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO14 0x0000001B +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO13 0x0000001A +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO12 0x00000019 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO11 0x00000018 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO10 0x00000017 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO9 0x00000016 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO8 0x00000015 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO7 0x00000014 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO6 0x00000013 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO5 0x00000012 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO4 0x00000011 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO3 0x00000010 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO2 0x0000000F +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO1 0x0000000E +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO0 0x0000000D +#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_PROG_WU 0x0000000C +#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_SW 0x0000000B +#define AUX_EVCTL_VECCFG1_VEC2_EV_OBSMUX1 0x0000000A +#define AUX_EVCTL_VECCFG1_VEC2_EV_OBSMUX0 0x00000009 +#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_DONE 0x00000007 +#define AUX_EVCTL_VECCFG1_VEC2_EV_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_EVCTL_VECCFG1_VEC2_EV_TIMER1_EV 0x00000005 +#define AUX_EVCTL_VECCFG1_VEC2_EV_TIMER0_EV 0x00000004 +#define AUX_EVCTL_VECCFG1_VEC2_EV_TDC_DONE 0x00000003 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUX_COMPB 0x00000002 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUX_COMPA 0x00000001 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_RTC_CH2 0x00000000 //***************************************************************************** // @@ -572,41 +572,41 @@ // AUX_COMPB EVSTAT0.AUX_COMPB // AUX_COMPA EVSTAT0.AUX_COMPA // AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_W 5 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_M 0x0000001F -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_S 0 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_IRQ 0x0000001F -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_MCU_EV 0x0000001E -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ACLK_REF 0x0000001D -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO15 0x0000001C -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO14 0x0000001B -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO13 0x0000001A -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO12 0x00000019 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO11 0x00000018 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO10 0x00000017 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO9 0x00000016 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO8 0x00000015 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO7 0x00000014 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO6 0x00000013 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO5 0x00000012 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO4 0x00000011 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO3 0x00000010 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO2 0x0000000F -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO1 0x0000000E -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO0 0x0000000D -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_PROG_WU 0x0000000C -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_SW 0x0000000B -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_OBSMUX1 0x0000000A -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_OBSMUX0 0x00000009 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_FIFO_ALMOST_FULL 0x00000008 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_DONE 0x00000007 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_SMPH_AUTOTAKE_DONE 0x00000006 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TIMER1_EV 0x00000005 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TIMER0_EV 0x00000004 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TDC_DONE 0x00000003 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUX_COMPB 0x00000002 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUX_COMPA 0x00000001 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_RTC_CH2 0x00000000 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_W 5 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_M 0x0000001F +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_S 0 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_IRQ 0x0000001F +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_MCU_EV 0x0000001E +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ACLK_REF 0x0000001D +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO15 0x0000001C +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO14 0x0000001B +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO13 0x0000001A +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO12 0x00000019 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO11 0x00000018 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO10 0x00000017 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO9 0x00000016 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO8 0x00000015 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO7 0x00000014 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO6 0x00000013 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO5 0x00000012 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO4 0x00000011 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO3 0x00000010 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO2 0x0000000F +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO1 0x0000000E +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO0 0x0000000D +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_PROG_WU 0x0000000C +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_SW 0x0000000B +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_OBSMUX1 0x0000000A +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_OBSMUX0 0x00000009 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_DONE 0x00000007 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TIMER1_EV 0x00000005 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TIMER0_EV 0x00000004 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TDC_DONE 0x00000003 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUX_COMPB 0x00000002 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUX_COMPA 0x00000001 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_RTC_CH2 0x00000000 //***************************************************************************** // @@ -617,79 +617,79 @@ // // This event flag is set when level selected by EVTOAONPOL.TIMER1_EV occurs on // EVSTAT0.TIMER1_EV. -#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV 0x00000100 -#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_BITN 8 -#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_M 0x00000100 -#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_S 8 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_S 8 // Field: [7] TIMER0_EV // // This event flag is set when level selected by EVTOAONPOL.TIMER0_EV occurs on // EVSTAT0.TIMER0_EV. -#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV 0x00000080 -#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_BITN 7 -#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_M 0x00000080 -#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_S 7 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_S 7 // Field: [6] TDC_DONE // // This event flag is set when level selected by EVTOAONPOL.TDC_DONE occurs on // EVSTAT0.TDC_DONE. -#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE 0x00000040 -#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_BITN 6 -#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_S 6 +#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_S 6 // Field: [5] ADC_DONE // // This event flag is set when level selected by EVTOAONPOL.ADC_DONE occurs on // EVSTAT0.ADC_DONE. -#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE 0x00000020 -#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_BITN 5 -#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_M 0x00000020 -#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_S 5 +#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_S 5 // Field: [4] AUX_COMPB // // This event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on // EVSTAT0.AUX_COMPB. -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB 0x00000010 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_BITN 4 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_M 0x00000010 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_S 4 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_S 4 // Field: [3] AUX_COMPA // // This event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on // EVSTAT0.AUX_COMPA. -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA 0x00000008 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_BITN 3 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_M 0x00000008 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_S 3 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_S 3 // Field: [2] SWEV2 // // This event flag is set when software writes a 1 to SWEVSET.SWEV2. -#define AUX_EVCTL_EVTOAONFLAGS_SWEV2 0x00000004 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_BITN 2 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_M 0x00000004 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_S 2 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_BITN 2 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_M 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_S 2 // Field: [1] SWEV1 // // This event flag is set when software writes a 1 to SWEVSET.SWEV1. -#define AUX_EVCTL_EVTOAONFLAGS_SWEV1 0x00000002 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_BITN 1 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_M 0x00000002 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_S 1 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_BITN 1 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_M 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_S 1 // Field: [0] SWEV0 // // This event flag is set when software writes a 1 to SWEVSET.SWEV0. -#define AUX_EVCTL_EVTOAONFLAGS_SWEV0 0x00000001 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_BITN 0 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_M 0x00000001 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_S 0 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_BITN 0 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_M 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_S 0 //***************************************************************************** // @@ -702,12 +702,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV 0x00000100 -#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_BITN 8 -#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_M 0x00000100 -#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_S 8 -#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_LOW 0x00000100 -#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_HIGH 0x00000000 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_S 8 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_LOW 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_HIGH 0x00000000 // Field: [7] TIMER0_EV // @@ -715,12 +715,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV 0x00000080 -#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_BITN 7 -#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_M 0x00000080 -#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_S 7 -#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_LOW 0x00000080 -#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_HIGH 0x00000000 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_S 7 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_LOW 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_HIGH 0x00000000 // Field: [6] TDC_DONE // @@ -728,12 +728,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOAONPOL_TDC_DONE 0x00000040 -#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_BITN 6 -#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_S 6 -#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_LOW 0x00000040 -#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_HIGH 0x00000000 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_S 6 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_LOW 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_HIGH 0x00000000 // Field: [5] ADC_DONE // @@ -741,12 +741,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOAONPOL_ADC_DONE 0x00000020 -#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_BITN 5 -#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_M 0x00000020 -#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_S 5 -#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_LOW 0x00000020 -#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_HIGH 0x00000000 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_S 5 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_LOW 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_HIGH 0x00000000 // Field: [4] AUX_COMPB // @@ -754,12 +754,12 @@ // ENUMs: // LOW Falling edge // HIGH Rising edge -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB 0x00000010 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_BITN 4 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_M 0x00000010 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_S 4 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_LOW 0x00000010 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_HIGH 0x00000000 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_S 4 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_LOW 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_HIGH 0x00000000 // Field: [3] AUX_COMPA // @@ -767,12 +767,12 @@ // ENUMs: // LOW Falling edge // HIGH Rising edge -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA 0x00000008 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_BITN 3 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_M 0x00000008 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_S 3 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_LOW 0x00000008 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_HIGH 0x00000000 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_S 3 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_LOW 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_HIGH 0x00000000 //***************************************************************************** // @@ -787,12 +787,12 @@ // when the condition configured in SEL is met. // BURST Burst requests are generated on UDMA0 channel 7 // when the condition configured in SEL is met. -#define AUX_EVCTL_DMACTL_REQ_MODE 0x00000004 -#define AUX_EVCTL_DMACTL_REQ_MODE_BITN 2 -#define AUX_EVCTL_DMACTL_REQ_MODE_M 0x00000004 -#define AUX_EVCTL_DMACTL_REQ_MODE_S 2 -#define AUX_EVCTL_DMACTL_REQ_MODE_SINGLE 0x00000004 -#define AUX_EVCTL_DMACTL_REQ_MODE_BURST 0x00000000 +#define AUX_EVCTL_DMACTL_REQ_MODE 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_BITN 2 +#define AUX_EVCTL_DMACTL_REQ_MODE_M 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_S 2 +#define AUX_EVCTL_DMACTL_REQ_MODE_SINGLE 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_BURST 0x00000000 // Field: [1] EN // @@ -800,10 +800,10 @@ // // 0: Disable UDMA0 interface to ADC. // 1: Enable UDMA0 interface to ADC. -#define AUX_EVCTL_DMACTL_EN 0x00000002 -#define AUX_EVCTL_DMACTL_EN_BITN 1 -#define AUX_EVCTL_DMACTL_EN_M 0x00000002 -#define AUX_EVCTL_DMACTL_EN_S 1 +#define AUX_EVCTL_DMACTL_EN 0x00000002 +#define AUX_EVCTL_DMACTL_EN_BITN 1 +#define AUX_EVCTL_DMACTL_EN_M 0x00000002 +#define AUX_EVCTL_DMACTL_EN_S 1 // Field: [0] SEL // @@ -814,12 +814,12 @@ // FIFO is almost full (3/4 full). // FIFO_NOT_EMPTY UDMA0 trigger event will be generated when there // are samples in the ADC FIFO. -#define AUX_EVCTL_DMACTL_SEL 0x00000001 -#define AUX_EVCTL_DMACTL_SEL_BITN 0 -#define AUX_EVCTL_DMACTL_SEL_M 0x00000001 -#define AUX_EVCTL_DMACTL_SEL_S 0 -#define AUX_EVCTL_DMACTL_SEL_FIFO_ALMOST_FULL 0x00000001 -#define AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY 0x00000000 +#define AUX_EVCTL_DMACTL_SEL 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_BITN 0 +#define AUX_EVCTL_DMACTL_SEL_M 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_S 0 +#define AUX_EVCTL_DMACTL_SEL_FIFO_ALMOST_FULL 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY 0x00000000 //***************************************************************************** // @@ -832,10 +832,10 @@ // // 0: No effect. // 1: Set software event flag 2. -#define AUX_EVCTL_SWEVSET_SWEV2 0x00000004 -#define AUX_EVCTL_SWEVSET_SWEV2_BITN 2 -#define AUX_EVCTL_SWEVSET_SWEV2_M 0x00000004 -#define AUX_EVCTL_SWEVSET_SWEV2_S 2 +#define AUX_EVCTL_SWEVSET_SWEV2 0x00000004 +#define AUX_EVCTL_SWEVSET_SWEV2_BITN 2 +#define AUX_EVCTL_SWEVSET_SWEV2_M 0x00000004 +#define AUX_EVCTL_SWEVSET_SWEV2_S 2 // Field: [1] SWEV1 // @@ -843,10 +843,10 @@ // // 0: No effect. // 1: Set software event flag 1. -#define AUX_EVCTL_SWEVSET_SWEV1 0x00000002 -#define AUX_EVCTL_SWEVSET_SWEV1_BITN 1 -#define AUX_EVCTL_SWEVSET_SWEV1_M 0x00000002 -#define AUX_EVCTL_SWEVSET_SWEV1_S 1 +#define AUX_EVCTL_SWEVSET_SWEV1 0x00000002 +#define AUX_EVCTL_SWEVSET_SWEV1_BITN 1 +#define AUX_EVCTL_SWEVSET_SWEV1_M 0x00000002 +#define AUX_EVCTL_SWEVSET_SWEV1_S 1 // Field: [0] SWEV0 // @@ -854,10 +854,10 @@ // // 0: No effect. // 1: Set software event flag 0. -#define AUX_EVCTL_SWEVSET_SWEV0 0x00000001 -#define AUX_EVCTL_SWEVSET_SWEV0_BITN 0 -#define AUX_EVCTL_SWEVSET_SWEV0_M 0x00000001 -#define AUX_EVCTL_SWEVSET_SWEV0_S 0 +#define AUX_EVCTL_SWEVSET_SWEV0 0x00000001 +#define AUX_EVCTL_SWEVSET_SWEV0_BITN 0 +#define AUX_EVCTL_SWEVSET_SWEV0_M 0x00000001 +#define AUX_EVCTL_SWEVSET_SWEV0_S 0 //***************************************************************************** // @@ -867,134 +867,134 @@ // Field: [15] AUXIO2 // // AUXIO2 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 2. -#define AUX_EVCTL_EVSTAT0_AUXIO2 0x00008000 -#define AUX_EVCTL_EVSTAT0_AUXIO2_BITN 15 -#define AUX_EVCTL_EVSTAT0_AUXIO2_M 0x00008000 -#define AUX_EVCTL_EVSTAT0_AUXIO2_S 15 +#define AUX_EVCTL_EVSTAT0_AUXIO2 0x00008000 +#define AUX_EVCTL_EVSTAT0_AUXIO2_BITN 15 +#define AUX_EVCTL_EVSTAT0_AUXIO2_M 0x00008000 +#define AUX_EVCTL_EVSTAT0_AUXIO2_S 15 // Field: [14] AUXIO1 // // AUXIO1 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 1. -#define AUX_EVCTL_EVSTAT0_AUXIO1 0x00004000 -#define AUX_EVCTL_EVSTAT0_AUXIO1_BITN 14 -#define AUX_EVCTL_EVSTAT0_AUXIO1_M 0x00004000 -#define AUX_EVCTL_EVSTAT0_AUXIO1_S 14 +#define AUX_EVCTL_EVSTAT0_AUXIO1 0x00004000 +#define AUX_EVCTL_EVSTAT0_AUXIO1_BITN 14 +#define AUX_EVCTL_EVSTAT0_AUXIO1_M 0x00004000 +#define AUX_EVCTL_EVSTAT0_AUXIO1_S 14 // Field: [13] AUXIO0 // // AUXIO0 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 0. -#define AUX_EVCTL_EVSTAT0_AUXIO0 0x00002000 -#define AUX_EVCTL_EVSTAT0_AUXIO0_BITN 13 -#define AUX_EVCTL_EVSTAT0_AUXIO0_M 0x00002000 -#define AUX_EVCTL_EVSTAT0_AUXIO0_S 13 +#define AUX_EVCTL_EVSTAT0_AUXIO0 0x00002000 +#define AUX_EVCTL_EVSTAT0_AUXIO0_BITN 13 +#define AUX_EVCTL_EVSTAT0_AUXIO0_M 0x00002000 +#define AUX_EVCTL_EVSTAT0_AUXIO0_S 13 // Field: [12] AON_PROG_WU // // AON_EVENT:AUXWUSEL.WU2_EV OR AON_EVENT:AUXWUSEL.WU1_EV OR // AON_EVENT:AUXWUSEL.WU0_EV -#define AUX_EVCTL_EVSTAT0_AON_PROG_WU 0x00001000 -#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_BITN 12 -#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_M 0x00001000 -#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_S 12 +#define AUX_EVCTL_EVSTAT0_AON_PROG_WU 0x00001000 +#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_BITN 12 +#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_M 0x00001000 +#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_S 12 // Field: [11] AON_SW // // AON_WUC:AUXCTL.SWEV -#define AUX_EVCTL_EVSTAT0_AON_SW 0x00000800 -#define AUX_EVCTL_EVSTAT0_AON_SW_BITN 11 -#define AUX_EVCTL_EVSTAT0_AON_SW_M 0x00000800 -#define AUX_EVCTL_EVSTAT0_AON_SW_S 11 +#define AUX_EVCTL_EVSTAT0_AON_SW 0x00000800 +#define AUX_EVCTL_EVSTAT0_AON_SW_BITN 11 +#define AUX_EVCTL_EVSTAT0_AON_SW_M 0x00000800 +#define AUX_EVCTL_EVSTAT0_AON_SW_S 11 // Field: [10] OBSMUX1 // // Observation input 1 from IOC. // This event is configured by IOC:OBSAUXOUTPUT.SEL1. -#define AUX_EVCTL_EVSTAT0_OBSMUX1 0x00000400 -#define AUX_EVCTL_EVSTAT0_OBSMUX1_BITN 10 -#define AUX_EVCTL_EVSTAT0_OBSMUX1_M 0x00000400 -#define AUX_EVCTL_EVSTAT0_OBSMUX1_S 10 +#define AUX_EVCTL_EVSTAT0_OBSMUX1 0x00000400 +#define AUX_EVCTL_EVSTAT0_OBSMUX1_BITN 10 +#define AUX_EVCTL_EVSTAT0_OBSMUX1_M 0x00000400 +#define AUX_EVCTL_EVSTAT0_OBSMUX1_S 10 // Field: [9] OBSMUX0 // // Observation input 0 from IOC. // This event is configured by IOC:OBSAUXOUTPUT.SEL0 and can be overridden by // IOC:OBSAUXOUTPUT.SEL_MISC. -#define AUX_EVCTL_EVSTAT0_OBSMUX0 0x00000200 -#define AUX_EVCTL_EVSTAT0_OBSMUX0_BITN 9 -#define AUX_EVCTL_EVSTAT0_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_EVSTAT0_OBSMUX0_S 9 +#define AUX_EVCTL_EVSTAT0_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVSTAT0_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVSTAT0_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVSTAT0_OBSMUX0_S 9 // Field: [8] ADC_FIFO_ALMOST_FULL // // AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL -#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_S 8 +#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_S 8 // Field: [7] ADC_DONE // // AUX_ANAIF ADC conversion done event. -#define AUX_EVCTL_EVSTAT0_ADC_DONE 0x00000080 -#define AUX_EVCTL_EVSTAT0_ADC_DONE_BITN 7 -#define AUX_EVCTL_EVSTAT0_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_EVSTAT0_ADC_DONE_S 7 +#define AUX_EVCTL_EVSTAT0_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVSTAT0_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVSTAT0_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVSTAT0_ADC_DONE_S 7 // Field: [6] SMPH_AUTOTAKE_DONE // // See AUX_SMPH:AUTOTAKE.SMPH_ID for description. -#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_S 6 +#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_S 6 // Field: [5] TIMER1_EV // // AUX_TIMER1_EV event, see AUX_TIMER:T1TARGET for description. -#define AUX_EVCTL_EVSTAT0_TIMER1_EV 0x00000020 -#define AUX_EVCTL_EVSTAT0_TIMER1_EV_BITN 5 -#define AUX_EVCTL_EVSTAT0_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_EVSTAT0_TIMER1_EV_S 5 +#define AUX_EVCTL_EVSTAT0_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVSTAT0_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVSTAT0_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVSTAT0_TIMER1_EV_S 5 // Field: [4] TIMER0_EV // // AUX_TIMER0_EV event, see AUX_TIMER:T0TARGET for description. -#define AUX_EVCTL_EVSTAT0_TIMER0_EV 0x00000010 -#define AUX_EVCTL_EVSTAT0_TIMER0_EV_BITN 4 -#define AUX_EVCTL_EVSTAT0_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_EVSTAT0_TIMER0_EV_S 4 +#define AUX_EVCTL_EVSTAT0_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVSTAT0_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVSTAT0_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVSTAT0_TIMER0_EV_S 4 // Field: [3] TDC_DONE // // AUX_TDC:STAT.DONE -#define AUX_EVCTL_EVSTAT0_TDC_DONE 0x00000008 -#define AUX_EVCTL_EVSTAT0_TDC_DONE_BITN 3 -#define AUX_EVCTL_EVSTAT0_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_EVSTAT0_TDC_DONE_S 3 +#define AUX_EVCTL_EVSTAT0_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVSTAT0_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVSTAT0_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVSTAT0_TDC_DONE_S 3 // Field: [2] AUX_COMPB // // Comparator B output -#define AUX_EVCTL_EVSTAT0_AUX_COMPB 0x00000004 -#define AUX_EVCTL_EVSTAT0_AUX_COMPB_BITN 2 -#define AUX_EVCTL_EVSTAT0_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_EVSTAT0_AUX_COMPB_S 2 +#define AUX_EVCTL_EVSTAT0_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVSTAT0_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVSTAT0_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVSTAT0_AUX_COMPB_S 2 // Field: [1] AUX_COMPA // // Comparator A output -#define AUX_EVCTL_EVSTAT0_AUX_COMPA 0x00000002 -#define AUX_EVCTL_EVSTAT0_AUX_COMPA_BITN 1 -#define AUX_EVCTL_EVSTAT0_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_EVSTAT0_AUX_COMPA_S 1 +#define AUX_EVCTL_EVSTAT0_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVSTAT0_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVSTAT0_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVSTAT0_AUX_COMPA_S 1 // Field: [0] AON_RTC_CH2 // // AON_RTC:EVFLAGS.CH2 -#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2 0x00000001 -#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_BITN 0 -#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_M 0x00000001 -#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_S 0 +#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2 0x00000001 +#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_BITN 0 +#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_M 0x00000001 +#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_S 0 //***************************************************************************** // @@ -1014,132 +1014,132 @@ // AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW // // Bit 7 in UDMA0:DONEMASK must be 0. -#define AUX_EVCTL_EVSTAT1_ADC_IRQ 0x00008000 -#define AUX_EVCTL_EVSTAT1_ADC_IRQ_BITN 15 -#define AUX_EVCTL_EVSTAT1_ADC_IRQ_M 0x00008000 -#define AUX_EVCTL_EVSTAT1_ADC_IRQ_S 15 +#define AUX_EVCTL_EVSTAT1_ADC_IRQ 0x00008000 +#define AUX_EVCTL_EVSTAT1_ADC_IRQ_BITN 15 +#define AUX_EVCTL_EVSTAT1_ADC_IRQ_M 0x00008000 +#define AUX_EVCTL_EVSTAT1_ADC_IRQ_S 15 // Field: [14] MCU_EV // // Event from EVENT configured by EVENT:AUXSEL0. -#define AUX_EVCTL_EVSTAT1_MCU_EV 0x00004000 -#define AUX_EVCTL_EVSTAT1_MCU_EV_BITN 14 -#define AUX_EVCTL_EVSTAT1_MCU_EV_M 0x00004000 -#define AUX_EVCTL_EVSTAT1_MCU_EV_S 14 +#define AUX_EVCTL_EVSTAT1_MCU_EV 0x00004000 +#define AUX_EVCTL_EVSTAT1_MCU_EV_BITN 14 +#define AUX_EVCTL_EVSTAT1_MCU_EV_M 0x00004000 +#define AUX_EVCTL_EVSTAT1_MCU_EV_S 14 // Field: [13] ACLK_REF // // TDC reference clock. // It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by // AUX_WUC:REFCLKCTL.REQ. -#define AUX_EVCTL_EVSTAT1_ACLK_REF 0x00002000 -#define AUX_EVCTL_EVSTAT1_ACLK_REF_BITN 13 -#define AUX_EVCTL_EVSTAT1_ACLK_REF_M 0x00002000 -#define AUX_EVCTL_EVSTAT1_ACLK_REF_S 13 +#define AUX_EVCTL_EVSTAT1_ACLK_REF 0x00002000 +#define AUX_EVCTL_EVSTAT1_ACLK_REF_BITN 13 +#define AUX_EVCTL_EVSTAT1_ACLK_REF_M 0x00002000 +#define AUX_EVCTL_EVSTAT1_ACLK_REF_S 13 // Field: [12] AUXIO15 // // AUXIO15 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 7. -#define AUX_EVCTL_EVSTAT1_AUXIO15 0x00001000 -#define AUX_EVCTL_EVSTAT1_AUXIO15_BITN 12 -#define AUX_EVCTL_EVSTAT1_AUXIO15_M 0x00001000 -#define AUX_EVCTL_EVSTAT1_AUXIO15_S 12 +#define AUX_EVCTL_EVSTAT1_AUXIO15 0x00001000 +#define AUX_EVCTL_EVSTAT1_AUXIO15_BITN 12 +#define AUX_EVCTL_EVSTAT1_AUXIO15_M 0x00001000 +#define AUX_EVCTL_EVSTAT1_AUXIO15_S 12 // Field: [11] AUXIO14 // // AUXIO14 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 6. -#define AUX_EVCTL_EVSTAT1_AUXIO14 0x00000800 -#define AUX_EVCTL_EVSTAT1_AUXIO14_BITN 11 -#define AUX_EVCTL_EVSTAT1_AUXIO14_M 0x00000800 -#define AUX_EVCTL_EVSTAT1_AUXIO14_S 11 +#define AUX_EVCTL_EVSTAT1_AUXIO14 0x00000800 +#define AUX_EVCTL_EVSTAT1_AUXIO14_BITN 11 +#define AUX_EVCTL_EVSTAT1_AUXIO14_M 0x00000800 +#define AUX_EVCTL_EVSTAT1_AUXIO14_S 11 // Field: [10] AUXIO13 // // AUXIO13 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 5. -#define AUX_EVCTL_EVSTAT1_AUXIO13 0x00000400 -#define AUX_EVCTL_EVSTAT1_AUXIO13_BITN 10 -#define AUX_EVCTL_EVSTAT1_AUXIO13_M 0x00000400 -#define AUX_EVCTL_EVSTAT1_AUXIO13_S 10 +#define AUX_EVCTL_EVSTAT1_AUXIO13 0x00000400 +#define AUX_EVCTL_EVSTAT1_AUXIO13_BITN 10 +#define AUX_EVCTL_EVSTAT1_AUXIO13_M 0x00000400 +#define AUX_EVCTL_EVSTAT1_AUXIO13_S 10 // Field: [9] AUXIO12 // // AUXIO12 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 4. -#define AUX_EVCTL_EVSTAT1_AUXIO12 0x00000200 -#define AUX_EVCTL_EVSTAT1_AUXIO12_BITN 9 -#define AUX_EVCTL_EVSTAT1_AUXIO12_M 0x00000200 -#define AUX_EVCTL_EVSTAT1_AUXIO12_S 9 +#define AUX_EVCTL_EVSTAT1_AUXIO12 0x00000200 +#define AUX_EVCTL_EVSTAT1_AUXIO12_BITN 9 +#define AUX_EVCTL_EVSTAT1_AUXIO12_M 0x00000200 +#define AUX_EVCTL_EVSTAT1_AUXIO12_S 9 // Field: [8] AUXIO11 // // AUXIO11 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 3. -#define AUX_EVCTL_EVSTAT1_AUXIO11 0x00000100 -#define AUX_EVCTL_EVSTAT1_AUXIO11_BITN 8 -#define AUX_EVCTL_EVSTAT1_AUXIO11_M 0x00000100 -#define AUX_EVCTL_EVSTAT1_AUXIO11_S 8 +#define AUX_EVCTL_EVSTAT1_AUXIO11 0x00000100 +#define AUX_EVCTL_EVSTAT1_AUXIO11_BITN 8 +#define AUX_EVCTL_EVSTAT1_AUXIO11_M 0x00000100 +#define AUX_EVCTL_EVSTAT1_AUXIO11_S 8 // Field: [7] AUXIO10 // // AUXIO10 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 2. -#define AUX_EVCTL_EVSTAT1_AUXIO10 0x00000080 -#define AUX_EVCTL_EVSTAT1_AUXIO10_BITN 7 -#define AUX_EVCTL_EVSTAT1_AUXIO10_M 0x00000080 -#define AUX_EVCTL_EVSTAT1_AUXIO10_S 7 +#define AUX_EVCTL_EVSTAT1_AUXIO10 0x00000080 +#define AUX_EVCTL_EVSTAT1_AUXIO10_BITN 7 +#define AUX_EVCTL_EVSTAT1_AUXIO10_M 0x00000080 +#define AUX_EVCTL_EVSTAT1_AUXIO10_S 7 // Field: [6] AUXIO9 // // AUXIO9 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 1. -#define AUX_EVCTL_EVSTAT1_AUXIO9 0x00000040 -#define AUX_EVCTL_EVSTAT1_AUXIO9_BITN 6 -#define AUX_EVCTL_EVSTAT1_AUXIO9_M 0x00000040 -#define AUX_EVCTL_EVSTAT1_AUXIO9_S 6 +#define AUX_EVCTL_EVSTAT1_AUXIO9 0x00000040 +#define AUX_EVCTL_EVSTAT1_AUXIO9_BITN 6 +#define AUX_EVCTL_EVSTAT1_AUXIO9_M 0x00000040 +#define AUX_EVCTL_EVSTAT1_AUXIO9_S 6 // Field: [5] AUXIO8 // // AUXIO8 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 0. -#define AUX_EVCTL_EVSTAT1_AUXIO8 0x00000020 -#define AUX_EVCTL_EVSTAT1_AUXIO8_BITN 5 -#define AUX_EVCTL_EVSTAT1_AUXIO8_M 0x00000020 -#define AUX_EVCTL_EVSTAT1_AUXIO8_S 5 +#define AUX_EVCTL_EVSTAT1_AUXIO8 0x00000020 +#define AUX_EVCTL_EVSTAT1_AUXIO8_BITN 5 +#define AUX_EVCTL_EVSTAT1_AUXIO8_M 0x00000020 +#define AUX_EVCTL_EVSTAT1_AUXIO8_S 5 // Field: [4] AUXIO7 // // AUXIO7 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 7. -#define AUX_EVCTL_EVSTAT1_AUXIO7 0x00000010 -#define AUX_EVCTL_EVSTAT1_AUXIO7_BITN 4 -#define AUX_EVCTL_EVSTAT1_AUXIO7_M 0x00000010 -#define AUX_EVCTL_EVSTAT1_AUXIO7_S 4 +#define AUX_EVCTL_EVSTAT1_AUXIO7 0x00000010 +#define AUX_EVCTL_EVSTAT1_AUXIO7_BITN 4 +#define AUX_EVCTL_EVSTAT1_AUXIO7_M 0x00000010 +#define AUX_EVCTL_EVSTAT1_AUXIO7_S 4 // Field: [3] AUXIO6 // // AUXIO6 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 6. -#define AUX_EVCTL_EVSTAT1_AUXIO6 0x00000008 -#define AUX_EVCTL_EVSTAT1_AUXIO6_BITN 3 -#define AUX_EVCTL_EVSTAT1_AUXIO6_M 0x00000008 -#define AUX_EVCTL_EVSTAT1_AUXIO6_S 3 +#define AUX_EVCTL_EVSTAT1_AUXIO6 0x00000008 +#define AUX_EVCTL_EVSTAT1_AUXIO6_BITN 3 +#define AUX_EVCTL_EVSTAT1_AUXIO6_M 0x00000008 +#define AUX_EVCTL_EVSTAT1_AUXIO6_S 3 // Field: [2] AUXIO5 // // AUXIO5 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 5. -#define AUX_EVCTL_EVSTAT1_AUXIO5 0x00000004 -#define AUX_EVCTL_EVSTAT1_AUXIO5_BITN 2 -#define AUX_EVCTL_EVSTAT1_AUXIO5_M 0x00000004 -#define AUX_EVCTL_EVSTAT1_AUXIO5_S 2 +#define AUX_EVCTL_EVSTAT1_AUXIO5 0x00000004 +#define AUX_EVCTL_EVSTAT1_AUXIO5_BITN 2 +#define AUX_EVCTL_EVSTAT1_AUXIO5_M 0x00000004 +#define AUX_EVCTL_EVSTAT1_AUXIO5_S 2 // Field: [1] AUXIO4 // // AUXIO4 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 4. -#define AUX_EVCTL_EVSTAT1_AUXIO4 0x00000002 -#define AUX_EVCTL_EVSTAT1_AUXIO4_BITN 1 -#define AUX_EVCTL_EVSTAT1_AUXIO4_M 0x00000002 -#define AUX_EVCTL_EVSTAT1_AUXIO4_S 1 +#define AUX_EVCTL_EVSTAT1_AUXIO4 0x00000002 +#define AUX_EVCTL_EVSTAT1_AUXIO4_BITN 1 +#define AUX_EVCTL_EVSTAT1_AUXIO4_M 0x00000002 +#define AUX_EVCTL_EVSTAT1_AUXIO4_S 1 // Field: [0] AUXIO3 // // AUXIO3 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 3. -#define AUX_EVCTL_EVSTAT1_AUXIO3 0x00000001 -#define AUX_EVCTL_EVSTAT1_AUXIO3_BITN 0 -#define AUX_EVCTL_EVSTAT1_AUXIO3_M 0x00000001 -#define AUX_EVCTL_EVSTAT1_AUXIO3_S 0 +#define AUX_EVCTL_EVSTAT1_AUXIO3 0x00000001 +#define AUX_EVCTL_EVSTAT1_AUXIO3_BITN 0 +#define AUX_EVCTL_EVSTAT1_AUXIO3_M 0x00000001 +#define AUX_EVCTL_EVSTAT1_AUXIO3_S 0 //***************************************************************************** // @@ -1152,12 +1152,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ 0x00000400 -#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_BITN 10 -#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_S 10 -#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_LOW 0x00000400 -#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_S 10 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_LOW 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_HIGH 0x00000000 // Field: [9] OBSMUX0 // @@ -1165,12 +1165,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0 0x00000200 -#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_BITN 9 -#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_S 9 -#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_LOW 0x00000200 -#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_S 9 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_LOW 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_HIGH 0x00000000 // Field: [8] ADC_FIFO_ALMOST_FULL // @@ -1178,12 +1178,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_S 8 -#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_LOW 0x00000100 -#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_S 8 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_LOW 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_HIGH 0x00000000 // Field: [7] ADC_DONE // @@ -1191,12 +1191,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE 0x00000080 -#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_BITN 7 -#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_S 7 -#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_LOW 0x00000080 -#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_S 7 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_LOW 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_HIGH 0x00000000 // Field: [6] SMPH_AUTOTAKE_DONE // @@ -1204,12 +1204,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_S 6 -#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_LOW 0x00000040 -#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_S 6 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_LOW 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_HIGH 0x00000000 // Field: [5] TIMER1_EV // @@ -1217,12 +1217,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV 0x00000020 -#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_BITN 5 -#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_S 5 -#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_LOW 0x00000020 -#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_S 5 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_LOW 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_HIGH 0x00000000 // Field: [4] TIMER0_EV // @@ -1230,12 +1230,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV 0x00000010 -#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_BITN 4 -#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_S 4 -#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_LOW 0x00000010 -#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_S 4 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_LOW 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_HIGH 0x00000000 // Field: [3] TDC_DONE // @@ -1243,12 +1243,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE 0x00000008 -#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_BITN 3 -#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_S 3 -#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_LOW 0x00000008 -#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_S 3 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_LOW 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_HIGH 0x00000000 // Field: [2] AUX_COMPB // @@ -1256,12 +1256,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB 0x00000004 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_BITN 2 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_S 2 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_LOW 0x00000004 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_S 2 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_LOW 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_HIGH 0x00000000 // Field: [1] AUX_COMPA // @@ -1269,12 +1269,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA 0x00000002 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_BITN 1 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_S 1 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_LOW 0x00000002 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_S 1 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_LOW 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_HIGH 0x00000000 // Field: [0] AON_WU_EV // @@ -1282,12 +1282,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV 0x00000001 -#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_BITN 0 -#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_M 0x00000001 -#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_S 0 -#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_LOW 0x00000001 -#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_S 0 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_LOW 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_HIGH 0x00000000 //***************************************************************************** // @@ -1298,101 +1298,101 @@ // // This event flag is set when level selected by EVTOMCUPOL.ADC_IRQ occurs on // EVSTAT0.ADC_IRQ. -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ 0x00000400 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_BITN 10 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_S 10 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_S 10 // Field: [9] OBSMUX0 // // This event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs // on EVSTAT0.MCU_OBSMUX0. -#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0 0x00000200 -#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_BITN 9 -#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_S 9 +#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_S 9 // Field: [8] ADC_FIFO_ALMOST_FULL // // This event flag is set when level selected by // EVTOMCUPOL.ADC_FIFO_ALMOST_FULL occurs on EVSTAT0.ADC_FIFO_ALMOST_FULL. -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_S 8 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_S 8 // Field: [7] ADC_DONE // // This event flag is set when level selected by EVTOMCUPOL.ADC_DONE occurs on // EVSTAT0.ADC_DONE. -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE 0x00000080 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_BITN 7 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_S 7 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_S 7 // Field: [6] SMPH_AUTOTAKE_DONE // // This event flag is set when level selected by EVTOMCUPOL.SMPH_AUTOTAKE_DONE // occurs on EVSTAT0.SMPH_AUTOTAKE_DONE. -#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_S 6 +#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_S 6 // Field: [5] TIMER1_EV // // This event flag is set when level selected by EVTOMCUPOL.TIMER1_EV occurs on // EVSTAT0.TIMER1_EV. -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV 0x00000020 -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_BITN 5 -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_S 5 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_S 5 // Field: [4] TIMER0_EV // // This event flag is set when level selected by EVTOMCUPOL.TIMER0_EV occurs on // EVSTAT0.TIMER0_EV. -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV 0x00000010 -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_BITN 4 -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_S 4 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_S 4 // Field: [3] TDC_DONE // // This event flag is set when level selected by EVTOMCUPOL.TDC_DONE occurs on // EVSTAT0.TDC_DONE. -#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE 0x00000008 -#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_BITN 3 -#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_S 3 +#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_S 3 // Field: [2] AUX_COMPB // // This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on // EVSTAT0.AUX_COMPB. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB 0x00000004 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_BITN 2 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_S 2 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_S 2 // Field: [1] AUX_COMPA // // This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on // EVSTAT0.AUX_COMPA. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA 0x00000002 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_BITN 1 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_S 1 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_S 1 // Field: [0] AON_WU_EV // // This event flag is set when level selected by EVTOMCUPOL.AON_WU_EV occurs on // the reduction-OR of the AUX_EVCTL:EVSTAT0.RTC_CH2_EV, // AUX_EVCTL:EVSTAT0.AON_SW, and AUX_EVCTL:EVSTAT0.AON_PROG_WU events. -#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV 0x00000001 -#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_BITN 0 -#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_M 0x00000001 -#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_S 0 +#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_S 0 //***************************************************************************** // @@ -1405,10 +1405,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ 0x00000400 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_BITN 10 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_S 10 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ 0x00000400 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_BITN 10 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_S 10 // Field: [9] OBSMUX0 // @@ -1416,10 +1416,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0 0x00000200 -#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_BITN 9 -#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_S 9 +#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0 0x00000200 +#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_BITN 9 +#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_S 9 // Field: [8] ADC_FIFO_ALMOST_FULL // @@ -1427,10 +1427,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_S 8 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_S 8 // Field: [7] ADC_DONE // @@ -1438,10 +1438,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE 0x00000080 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_BITN 7 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_S 7 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE 0x00000080 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_BITN 7 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_S 7 // Field: [6] SMPH_AUTOTAKE_DONE // @@ -1449,10 +1449,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_S 6 +#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_S 6 // Field: [5] TIMER1_EV // @@ -1460,10 +1460,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV 0x00000020 -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_BITN 5 -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_S 5 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV 0x00000020 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_BITN 5 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_S 5 // Field: [4] TIMER0_EV // @@ -1471,10 +1471,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV 0x00000010 -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_BITN 4 -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_S 4 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV 0x00000010 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_BITN 4 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_S 4 // Field: [3] TDC_DONE // @@ -1482,10 +1482,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE 0x00000008 -#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_BITN 3 -#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_S 3 +#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE 0x00000008 +#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_BITN 3 +#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_S 3 // Field: [2] AUX_COMPB // @@ -1493,10 +1493,10 @@ // // 0: Exclude // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB 0x00000004 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_BITN 2 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_S 2 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB 0x00000004 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_BITN 2 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_S 2 // Field: [1] AUX_COMPA // @@ -1504,10 +1504,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA 0x00000002 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_BITN 1 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_S 1 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA 0x00000002 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_BITN 1 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_S 1 // Field: [0] AON_WU_EV // @@ -1515,10 +1515,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV 0x00000001 -#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_BITN 0 -#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_M 0x00000001 -#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_S 0 +#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV 0x00000001 +#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_BITN 0 +#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_M 0x00000001 +#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_S 0 //***************************************************************************** // @@ -1534,10 +1534,10 @@ // // The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to // VECFLAGSCLR.VEC3. -#define AUX_EVCTL_VECFLAGS_VEC3 0x00000008 -#define AUX_EVCTL_VECFLAGS_VEC3_BITN 3 -#define AUX_EVCTL_VECFLAGS_VEC3_M 0x00000008 -#define AUX_EVCTL_VECFLAGS_VEC3_S 3 +#define AUX_EVCTL_VECFLAGS_VEC3 0x00000008 +#define AUX_EVCTL_VECFLAGS_VEC3_BITN 3 +#define AUX_EVCTL_VECFLAGS_VEC3_M 0x00000008 +#define AUX_EVCTL_VECFLAGS_VEC3_S 3 // Field: [2] VEC2 // @@ -1548,10 +1548,10 @@ // // The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to // VECFLAGSCLR.VEC2. -#define AUX_EVCTL_VECFLAGS_VEC2 0x00000004 -#define AUX_EVCTL_VECFLAGS_VEC2_BITN 2 -#define AUX_EVCTL_VECFLAGS_VEC2_M 0x00000004 -#define AUX_EVCTL_VECFLAGS_VEC2_S 2 +#define AUX_EVCTL_VECFLAGS_VEC2 0x00000004 +#define AUX_EVCTL_VECFLAGS_VEC2_BITN 2 +#define AUX_EVCTL_VECFLAGS_VEC2_M 0x00000004 +#define AUX_EVCTL_VECFLAGS_VEC2_S 2 // Field: [1] VEC1 // @@ -1562,10 +1562,10 @@ // // The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to // VECFLAGSCLR.VEC1. -#define AUX_EVCTL_VECFLAGS_VEC1 0x00000002 -#define AUX_EVCTL_VECFLAGS_VEC1_BITN 1 -#define AUX_EVCTL_VECFLAGS_VEC1_M 0x00000002 -#define AUX_EVCTL_VECFLAGS_VEC1_S 1 +#define AUX_EVCTL_VECFLAGS_VEC1 0x00000002 +#define AUX_EVCTL_VECFLAGS_VEC1_BITN 1 +#define AUX_EVCTL_VECFLAGS_VEC1_M 0x00000002 +#define AUX_EVCTL_VECFLAGS_VEC1_S 1 // Field: [0] VEC0 // @@ -1576,10 +1576,10 @@ // // The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to // VECFLAGSCLR.VEC0. -#define AUX_EVCTL_VECFLAGS_VEC0 0x00000001 -#define AUX_EVCTL_VECFLAGS_VEC0_BITN 0 -#define AUX_EVCTL_VECFLAGS_VEC0_M 0x00000001 -#define AUX_EVCTL_VECFLAGS_VEC0_S 0 +#define AUX_EVCTL_VECFLAGS_VEC0 0x00000001 +#define AUX_EVCTL_VECFLAGS_VEC0_BITN 0 +#define AUX_EVCTL_VECFLAGS_VEC0_M 0x00000001 +#define AUX_EVCTL_VECFLAGS_VEC0_S 0 //***************************************************************************** // @@ -1591,110 +1591,110 @@ // Write 1 to clear EVTOMCUFLAGS.ADC_IRQ. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ 0x00000400 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_BITN 10 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_S 10 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_S 10 // Field: [9] OBSMUX0 // // Write 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0 0x00000200 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_BITN 9 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_S 9 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_S 9 // Field: [8] ADC_FIFO_ALMOST_FULL // // Write 1 to clear EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_S 8 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_S 8 // Field: [7] ADC_DONE // // Write 1 to clear EVTOMCUFLAGS.ADC_DONE. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE 0x00000080 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_BITN 7 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_S 7 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_S 7 // Field: [6] SMPH_AUTOTAKE_DONE // // Write 1 to clear EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_S 6 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_S 6 // Field: [5] TIMER1_EV // // Write 1 to clear EVTOMCUFLAGS.TIMER1_EV. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV 0x00000020 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_BITN 5 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_S 5 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_S 5 // Field: [4] TIMER0_EV // // Write 1 to clear EVTOMCUFLAGS.TIMER0_EV. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV 0x00000010 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_BITN 4 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_S 4 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_S 4 // Field: [3] TDC_DONE // // Write 1 to clear EVTOMCUFLAGS.TDC_DONE. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE 0x00000008 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_BITN 3 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_S 3 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_S 3 // Field: [2] AUX_COMPB // // Write 1 to clear EVTOMCUFLAGS.AUX_COMPB. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB 0x00000004 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_BITN 2 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_S 2 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_S 2 // Field: [1] AUX_COMPA // // Write 1 to clear EVTOMCUFLAGS.AUX_COMPA. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA 0x00000002 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_BITN 1 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_S 1 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_S 1 // Field: [0] AON_WU_EV // // Write 1 to clear EVTOMCUFLAGS.AON_WU_EV. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV 0x00000001 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_BITN 0 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_M 0x00000001 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_S 0 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_S 0 //***************************************************************************** // @@ -1706,90 +1706,90 @@ // Write 1 to clear EVTOAONFLAGS.TIMER1_EV. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV 0x00000100 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_BITN 8 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_M 0x00000100 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_S 8 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_S 8 // Field: [7] TIMER0_EV // // Write 1 to clear EVTOAONFLAGS.TIMER0_EV. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV 0x00000080 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_BITN 7 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_M 0x00000080 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_S 7 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_S 7 // Field: [6] TDC_DONE // // Write 1 to clear EVTOAONFLAGS.TDC_DONE. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE 0x00000040 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_BITN 6 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_S 6 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_S 6 // Field: [5] ADC_DONE // // Write 1 to clear EVTOAONFLAGS.ADC_DONE. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE 0x00000020 -#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_BITN 5 -#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_M 0x00000020 -#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_S 5 +#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_S 5 // Field: [4] AUX_COMPB // // Write 1 to clear EVTOAONFLAGS.AUX_COMPB. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB 0x00000010 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_BITN 4 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_M 0x00000010 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_S 4 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_S 4 // Field: [3] AUX_COMPA // // Write 1 to clear EVTOAONFLAGS.AUX_COMPA. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA 0x00000008 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_BITN 3 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_M 0x00000008 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_S 3 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_S 3 // Field: [2] SWEV2 // // Write 1 to clear EVTOAONFLAGS.SWEV2. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2 0x00000004 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_BITN 2 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_M 0x00000004 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_S 2 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_BITN 2 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_M 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_S 2 // Field: [1] SWEV1 // // Write 1 to clear EVTOAONFLAGS.SWEV1. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1 0x00000002 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_BITN 1 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_M 0x00000002 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_S 1 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_BITN 1 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_M 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_S 1 // Field: [0] SWEV0 // // Write 1 to clear EVTOAONFLAGS.SWEV0. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0 0x00000001 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_BITN 0 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_M 0x00000001 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_S 0 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_BITN 0 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_M 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_S 0 //***************************************************************************** // @@ -1804,10 +1804,10 @@ // 1: Clear VECFLAGS.VEC3. // // Read value is 0. -#define AUX_EVCTL_VECFLAGSCLR_VEC3 0x00000008 -#define AUX_EVCTL_VECFLAGSCLR_VEC3_BITN 3 -#define AUX_EVCTL_VECFLAGSCLR_VEC3_M 0x00000008 -#define AUX_EVCTL_VECFLAGSCLR_VEC3_S 3 +#define AUX_EVCTL_VECFLAGSCLR_VEC3 0x00000008 +#define AUX_EVCTL_VECFLAGSCLR_VEC3_BITN 3 +#define AUX_EVCTL_VECFLAGSCLR_VEC3_M 0x00000008 +#define AUX_EVCTL_VECFLAGSCLR_VEC3_S 3 // Field: [2] VEC2 // @@ -1817,10 +1817,10 @@ // 1: Clear VECFLAGS.VEC2. // // Read value is 0. -#define AUX_EVCTL_VECFLAGSCLR_VEC2 0x00000004 -#define AUX_EVCTL_VECFLAGSCLR_VEC2_BITN 2 -#define AUX_EVCTL_VECFLAGSCLR_VEC2_M 0x00000004 -#define AUX_EVCTL_VECFLAGSCLR_VEC2_S 2 +#define AUX_EVCTL_VECFLAGSCLR_VEC2 0x00000004 +#define AUX_EVCTL_VECFLAGSCLR_VEC2_BITN 2 +#define AUX_EVCTL_VECFLAGSCLR_VEC2_M 0x00000004 +#define AUX_EVCTL_VECFLAGSCLR_VEC2_S 2 // Field: [1] VEC1 // @@ -1830,10 +1830,10 @@ // 1: Clear VECFLAGS.VEC1. // // Read value is 0. -#define AUX_EVCTL_VECFLAGSCLR_VEC1 0x00000002 -#define AUX_EVCTL_VECFLAGSCLR_VEC1_BITN 1 -#define AUX_EVCTL_VECFLAGSCLR_VEC1_M 0x00000002 -#define AUX_EVCTL_VECFLAGSCLR_VEC1_S 1 +#define AUX_EVCTL_VECFLAGSCLR_VEC1 0x00000002 +#define AUX_EVCTL_VECFLAGSCLR_VEC1_BITN 1 +#define AUX_EVCTL_VECFLAGSCLR_VEC1_M 0x00000002 +#define AUX_EVCTL_VECFLAGSCLR_VEC1_S 1 // Field: [0] VEC0 // @@ -1843,10 +1843,9 @@ // 1: Clear VECFLAGS.VEC0. // // Read value is 0. -#define AUX_EVCTL_VECFLAGSCLR_VEC0 0x00000001 -#define AUX_EVCTL_VECFLAGSCLR_VEC0_BITN 0 -#define AUX_EVCTL_VECFLAGSCLR_VEC0_M 0x00000001 -#define AUX_EVCTL_VECFLAGSCLR_VEC0_S 0 - +#define AUX_EVCTL_VECFLAGSCLR_VEC0 0x00000001 +#define AUX_EVCTL_VECFLAGSCLR_VEC0_BITN 0 +#define AUX_EVCTL_VECFLAGSCLR_VEC0_M 0x00000001 +#define AUX_EVCTL_VECFLAGSCLR_VEC0_S 0 #endif // __AUX_EVCTL__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_sce.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_sce.h index 002242a..a39b085 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_sce.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_sce.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_sce_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_sce_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_SCE_H__ #define __HW_AUX_SCE_H__ @@ -44,34 +44,34 @@ // //***************************************************************************** // Internal -#define AUX_SCE_O_CTL 0x00000000 +#define AUX_SCE_O_CTL 0x00000000 // Internal -#define AUX_SCE_O_FETCHSTAT 0x00000004 +#define AUX_SCE_O_FETCHSTAT 0x00000004 // Internal -#define AUX_SCE_O_CPUSTAT 0x00000008 +#define AUX_SCE_O_CPUSTAT 0x00000008 // Internal -#define AUX_SCE_O_WUSTAT 0x0000000C +#define AUX_SCE_O_WUSTAT 0x0000000C // Internal -#define AUX_SCE_O_REG1_0 0x00000010 +#define AUX_SCE_O_REG1_0 0x00000010 // Internal -#define AUX_SCE_O_REG3_2 0x00000014 +#define AUX_SCE_O_REG3_2 0x00000014 // Internal -#define AUX_SCE_O_REG5_4 0x00000018 +#define AUX_SCE_O_REG5_4 0x00000018 // Internal -#define AUX_SCE_O_REG7_6 0x0000001C +#define AUX_SCE_O_REG7_6 0x0000001C // Internal -#define AUX_SCE_O_LOOPADDR 0x00000020 +#define AUX_SCE_O_LOOPADDR 0x00000020 // Internal -#define AUX_SCE_O_LOOPCNT 0x00000024 +#define AUX_SCE_O_LOOPCNT 0x00000024 //***************************************************************************** // @@ -81,79 +81,79 @@ // Field: [31:24] FORCE_EV_LOW // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_FORCE_EV_LOW_W 8 -#define AUX_SCE_CTL_FORCE_EV_LOW_M 0xFF000000 -#define AUX_SCE_CTL_FORCE_EV_LOW_S 24 +#define AUX_SCE_CTL_FORCE_EV_LOW_W 8 +#define AUX_SCE_CTL_FORCE_EV_LOW_M 0xFF000000 +#define AUX_SCE_CTL_FORCE_EV_LOW_S 24 // Field: [23:16] FORCE_EV_HIGH // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_FORCE_EV_HIGH_W 8 -#define AUX_SCE_CTL_FORCE_EV_HIGH_M 0x00FF0000 -#define AUX_SCE_CTL_FORCE_EV_HIGH_S 16 +#define AUX_SCE_CTL_FORCE_EV_HIGH_W 8 +#define AUX_SCE_CTL_FORCE_EV_HIGH_M 0x00FF0000 +#define AUX_SCE_CTL_FORCE_EV_HIGH_S 16 // Field: [11:8] RESET_VECTOR // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_RESET_VECTOR_W 4 -#define AUX_SCE_CTL_RESET_VECTOR_M 0x00000F00 -#define AUX_SCE_CTL_RESET_VECTOR_S 8 +#define AUX_SCE_CTL_RESET_VECTOR_W 4 +#define AUX_SCE_CTL_RESET_VECTOR_M 0x00000F00 +#define AUX_SCE_CTL_RESET_VECTOR_S 8 // Field: [6] DBG_FREEZE_EN // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_DBG_FREEZE_EN 0x00000040 -#define AUX_SCE_CTL_DBG_FREEZE_EN_BITN 6 -#define AUX_SCE_CTL_DBG_FREEZE_EN_M 0x00000040 -#define AUX_SCE_CTL_DBG_FREEZE_EN_S 6 +#define AUX_SCE_CTL_DBG_FREEZE_EN 0x00000040 +#define AUX_SCE_CTL_DBG_FREEZE_EN_BITN 6 +#define AUX_SCE_CTL_DBG_FREEZE_EN_M 0x00000040 +#define AUX_SCE_CTL_DBG_FREEZE_EN_S 6 // Field: [5] FORCE_WU_LOW // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_FORCE_WU_LOW 0x00000020 -#define AUX_SCE_CTL_FORCE_WU_LOW_BITN 5 -#define AUX_SCE_CTL_FORCE_WU_LOW_M 0x00000020 -#define AUX_SCE_CTL_FORCE_WU_LOW_S 5 +#define AUX_SCE_CTL_FORCE_WU_LOW 0x00000020 +#define AUX_SCE_CTL_FORCE_WU_LOW_BITN 5 +#define AUX_SCE_CTL_FORCE_WU_LOW_M 0x00000020 +#define AUX_SCE_CTL_FORCE_WU_LOW_S 5 // Field: [4] FORCE_WU_HIGH // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_FORCE_WU_HIGH 0x00000010 -#define AUX_SCE_CTL_FORCE_WU_HIGH_BITN 4 -#define AUX_SCE_CTL_FORCE_WU_HIGH_M 0x00000010 -#define AUX_SCE_CTL_FORCE_WU_HIGH_S 4 +#define AUX_SCE_CTL_FORCE_WU_HIGH 0x00000010 +#define AUX_SCE_CTL_FORCE_WU_HIGH_BITN 4 +#define AUX_SCE_CTL_FORCE_WU_HIGH_M 0x00000010 +#define AUX_SCE_CTL_FORCE_WU_HIGH_S 4 // Field: [3] RESTART // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_RESTART 0x00000008 -#define AUX_SCE_CTL_RESTART_BITN 3 -#define AUX_SCE_CTL_RESTART_M 0x00000008 -#define AUX_SCE_CTL_RESTART_S 3 +#define AUX_SCE_CTL_RESTART 0x00000008 +#define AUX_SCE_CTL_RESTART_BITN 3 +#define AUX_SCE_CTL_RESTART_M 0x00000008 +#define AUX_SCE_CTL_RESTART_S 3 // Field: [2] SINGLE_STEP // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_SINGLE_STEP 0x00000004 -#define AUX_SCE_CTL_SINGLE_STEP_BITN 2 -#define AUX_SCE_CTL_SINGLE_STEP_M 0x00000004 -#define AUX_SCE_CTL_SINGLE_STEP_S 2 +#define AUX_SCE_CTL_SINGLE_STEP 0x00000004 +#define AUX_SCE_CTL_SINGLE_STEP_BITN 2 +#define AUX_SCE_CTL_SINGLE_STEP_M 0x00000004 +#define AUX_SCE_CTL_SINGLE_STEP_S 2 // Field: [1] SUSPEND // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_SUSPEND 0x00000002 -#define AUX_SCE_CTL_SUSPEND_BITN 1 -#define AUX_SCE_CTL_SUSPEND_M 0x00000002 -#define AUX_SCE_CTL_SUSPEND_S 1 +#define AUX_SCE_CTL_SUSPEND 0x00000002 +#define AUX_SCE_CTL_SUSPEND_BITN 1 +#define AUX_SCE_CTL_SUSPEND_M 0x00000002 +#define AUX_SCE_CTL_SUSPEND_S 1 // Field: [0] CLK_EN // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_CLK_EN 0x00000001 -#define AUX_SCE_CTL_CLK_EN_BITN 0 -#define AUX_SCE_CTL_CLK_EN_M 0x00000001 -#define AUX_SCE_CTL_CLK_EN_S 0 +#define AUX_SCE_CTL_CLK_EN 0x00000001 +#define AUX_SCE_CTL_CLK_EN_BITN 0 +#define AUX_SCE_CTL_CLK_EN_M 0x00000001 +#define AUX_SCE_CTL_CLK_EN_S 0 //***************************************************************************** // @@ -163,16 +163,16 @@ // Field: [31:16] OPCODE // // Internal. Only to be used through TI provided API. -#define AUX_SCE_FETCHSTAT_OPCODE_W 16 -#define AUX_SCE_FETCHSTAT_OPCODE_M 0xFFFF0000 -#define AUX_SCE_FETCHSTAT_OPCODE_S 16 +#define AUX_SCE_FETCHSTAT_OPCODE_W 16 +#define AUX_SCE_FETCHSTAT_OPCODE_M 0xFFFF0000 +#define AUX_SCE_FETCHSTAT_OPCODE_S 16 // Field: [15:0] PC // // Internal. Only to be used through TI provided API. -#define AUX_SCE_FETCHSTAT_PC_W 16 -#define AUX_SCE_FETCHSTAT_PC_M 0x0000FFFF -#define AUX_SCE_FETCHSTAT_PC_S 0 +#define AUX_SCE_FETCHSTAT_PC_W 16 +#define AUX_SCE_FETCHSTAT_PC_M 0x0000FFFF +#define AUX_SCE_FETCHSTAT_PC_S 0 //***************************************************************************** // @@ -182,66 +182,66 @@ // Field: [11] BUS_ERROR // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_BUS_ERROR 0x00000800 -#define AUX_SCE_CPUSTAT_BUS_ERROR_BITN 11 -#define AUX_SCE_CPUSTAT_BUS_ERROR_M 0x00000800 -#define AUX_SCE_CPUSTAT_BUS_ERROR_S 11 +#define AUX_SCE_CPUSTAT_BUS_ERROR 0x00000800 +#define AUX_SCE_CPUSTAT_BUS_ERROR_BITN 11 +#define AUX_SCE_CPUSTAT_BUS_ERROR_M 0x00000800 +#define AUX_SCE_CPUSTAT_BUS_ERROR_S 11 // Field: [10] SLEEP // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_SLEEP 0x00000400 -#define AUX_SCE_CPUSTAT_SLEEP_BITN 10 -#define AUX_SCE_CPUSTAT_SLEEP_M 0x00000400 -#define AUX_SCE_CPUSTAT_SLEEP_S 10 +#define AUX_SCE_CPUSTAT_SLEEP 0x00000400 +#define AUX_SCE_CPUSTAT_SLEEP_BITN 10 +#define AUX_SCE_CPUSTAT_SLEEP_M 0x00000400 +#define AUX_SCE_CPUSTAT_SLEEP_S 10 // Field: [9] WEV // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_WEV 0x00000200 -#define AUX_SCE_CPUSTAT_WEV_BITN 9 -#define AUX_SCE_CPUSTAT_WEV_M 0x00000200 -#define AUX_SCE_CPUSTAT_WEV_S 9 +#define AUX_SCE_CPUSTAT_WEV 0x00000200 +#define AUX_SCE_CPUSTAT_WEV_BITN 9 +#define AUX_SCE_CPUSTAT_WEV_M 0x00000200 +#define AUX_SCE_CPUSTAT_WEV_S 9 // Field: [8] SELF_STOP // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_SELF_STOP 0x00000100 -#define AUX_SCE_CPUSTAT_SELF_STOP_BITN 8 -#define AUX_SCE_CPUSTAT_SELF_STOP_M 0x00000100 -#define AUX_SCE_CPUSTAT_SELF_STOP_S 8 +#define AUX_SCE_CPUSTAT_SELF_STOP 0x00000100 +#define AUX_SCE_CPUSTAT_SELF_STOP_BITN 8 +#define AUX_SCE_CPUSTAT_SELF_STOP_M 0x00000100 +#define AUX_SCE_CPUSTAT_SELF_STOP_S 8 // Field: [3] V_FLAG // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_V_FLAG 0x00000008 -#define AUX_SCE_CPUSTAT_V_FLAG_BITN 3 -#define AUX_SCE_CPUSTAT_V_FLAG_M 0x00000008 -#define AUX_SCE_CPUSTAT_V_FLAG_S 3 +#define AUX_SCE_CPUSTAT_V_FLAG 0x00000008 +#define AUX_SCE_CPUSTAT_V_FLAG_BITN 3 +#define AUX_SCE_CPUSTAT_V_FLAG_M 0x00000008 +#define AUX_SCE_CPUSTAT_V_FLAG_S 3 // Field: [2] C_FLAG // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_C_FLAG 0x00000004 -#define AUX_SCE_CPUSTAT_C_FLAG_BITN 2 -#define AUX_SCE_CPUSTAT_C_FLAG_M 0x00000004 -#define AUX_SCE_CPUSTAT_C_FLAG_S 2 +#define AUX_SCE_CPUSTAT_C_FLAG 0x00000004 +#define AUX_SCE_CPUSTAT_C_FLAG_BITN 2 +#define AUX_SCE_CPUSTAT_C_FLAG_M 0x00000004 +#define AUX_SCE_CPUSTAT_C_FLAG_S 2 // Field: [1] N_FLAG // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_N_FLAG 0x00000002 -#define AUX_SCE_CPUSTAT_N_FLAG_BITN 1 -#define AUX_SCE_CPUSTAT_N_FLAG_M 0x00000002 -#define AUX_SCE_CPUSTAT_N_FLAG_S 1 +#define AUX_SCE_CPUSTAT_N_FLAG 0x00000002 +#define AUX_SCE_CPUSTAT_N_FLAG_BITN 1 +#define AUX_SCE_CPUSTAT_N_FLAG_M 0x00000002 +#define AUX_SCE_CPUSTAT_N_FLAG_S 1 // Field: [0] Z_FLAG // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_Z_FLAG 0x00000001 -#define AUX_SCE_CPUSTAT_Z_FLAG_BITN 0 -#define AUX_SCE_CPUSTAT_Z_FLAG_M 0x00000001 -#define AUX_SCE_CPUSTAT_Z_FLAG_S 0 +#define AUX_SCE_CPUSTAT_Z_FLAG 0x00000001 +#define AUX_SCE_CPUSTAT_Z_FLAG_BITN 0 +#define AUX_SCE_CPUSTAT_Z_FLAG_M 0x00000001 +#define AUX_SCE_CPUSTAT_Z_FLAG_S 0 //***************************************************************************** // @@ -251,24 +251,24 @@ // Field: [17:16] EXC_VECTOR // // Internal. Only to be used through TI provided API. -#define AUX_SCE_WUSTAT_EXC_VECTOR_W 2 -#define AUX_SCE_WUSTAT_EXC_VECTOR_M 0x00030000 -#define AUX_SCE_WUSTAT_EXC_VECTOR_S 16 +#define AUX_SCE_WUSTAT_EXC_VECTOR_W 2 +#define AUX_SCE_WUSTAT_EXC_VECTOR_M 0x00030000 +#define AUX_SCE_WUSTAT_EXC_VECTOR_S 16 // Field: [8] WU_SIGNAL // // Internal. Only to be used through TI provided API. -#define AUX_SCE_WUSTAT_WU_SIGNAL 0x00000100 -#define AUX_SCE_WUSTAT_WU_SIGNAL_BITN 8 -#define AUX_SCE_WUSTAT_WU_SIGNAL_M 0x00000100 -#define AUX_SCE_WUSTAT_WU_SIGNAL_S 8 +#define AUX_SCE_WUSTAT_WU_SIGNAL 0x00000100 +#define AUX_SCE_WUSTAT_WU_SIGNAL_BITN 8 +#define AUX_SCE_WUSTAT_WU_SIGNAL_M 0x00000100 +#define AUX_SCE_WUSTAT_WU_SIGNAL_S 8 // Field: [7:0] EV_SIGNALS // // Internal. Only to be used through TI provided API. -#define AUX_SCE_WUSTAT_EV_SIGNALS_W 8 -#define AUX_SCE_WUSTAT_EV_SIGNALS_M 0x000000FF -#define AUX_SCE_WUSTAT_EV_SIGNALS_S 0 +#define AUX_SCE_WUSTAT_EV_SIGNALS_W 8 +#define AUX_SCE_WUSTAT_EV_SIGNALS_M 0x000000FF +#define AUX_SCE_WUSTAT_EV_SIGNALS_S 0 //***************************************************************************** // @@ -278,16 +278,16 @@ // Field: [31:16] REG1 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG1_0_REG1_W 16 -#define AUX_SCE_REG1_0_REG1_M 0xFFFF0000 -#define AUX_SCE_REG1_0_REG1_S 16 +#define AUX_SCE_REG1_0_REG1_W 16 +#define AUX_SCE_REG1_0_REG1_M 0xFFFF0000 +#define AUX_SCE_REG1_0_REG1_S 16 // Field: [15:0] REG0 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG1_0_REG0_W 16 -#define AUX_SCE_REG1_0_REG0_M 0x0000FFFF -#define AUX_SCE_REG1_0_REG0_S 0 +#define AUX_SCE_REG1_0_REG0_W 16 +#define AUX_SCE_REG1_0_REG0_M 0x0000FFFF +#define AUX_SCE_REG1_0_REG0_S 0 //***************************************************************************** // @@ -297,16 +297,16 @@ // Field: [31:16] REG3 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG3_2_REG3_W 16 -#define AUX_SCE_REG3_2_REG3_M 0xFFFF0000 -#define AUX_SCE_REG3_2_REG3_S 16 +#define AUX_SCE_REG3_2_REG3_W 16 +#define AUX_SCE_REG3_2_REG3_M 0xFFFF0000 +#define AUX_SCE_REG3_2_REG3_S 16 // Field: [15:0] REG2 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG3_2_REG2_W 16 -#define AUX_SCE_REG3_2_REG2_M 0x0000FFFF -#define AUX_SCE_REG3_2_REG2_S 0 +#define AUX_SCE_REG3_2_REG2_W 16 +#define AUX_SCE_REG3_2_REG2_M 0x0000FFFF +#define AUX_SCE_REG3_2_REG2_S 0 //***************************************************************************** // @@ -316,16 +316,16 @@ // Field: [31:16] REG5 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG5_4_REG5_W 16 -#define AUX_SCE_REG5_4_REG5_M 0xFFFF0000 -#define AUX_SCE_REG5_4_REG5_S 16 +#define AUX_SCE_REG5_4_REG5_W 16 +#define AUX_SCE_REG5_4_REG5_M 0xFFFF0000 +#define AUX_SCE_REG5_4_REG5_S 16 // Field: [15:0] REG4 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG5_4_REG4_W 16 -#define AUX_SCE_REG5_4_REG4_M 0x0000FFFF -#define AUX_SCE_REG5_4_REG4_S 0 +#define AUX_SCE_REG5_4_REG4_W 16 +#define AUX_SCE_REG5_4_REG4_M 0x0000FFFF +#define AUX_SCE_REG5_4_REG4_S 0 //***************************************************************************** // @@ -335,16 +335,16 @@ // Field: [31:16] REG7 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG7_6_REG7_W 16 -#define AUX_SCE_REG7_6_REG7_M 0xFFFF0000 -#define AUX_SCE_REG7_6_REG7_S 16 +#define AUX_SCE_REG7_6_REG7_W 16 +#define AUX_SCE_REG7_6_REG7_M 0xFFFF0000 +#define AUX_SCE_REG7_6_REG7_S 16 // Field: [15:0] REG6 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG7_6_REG6_W 16 -#define AUX_SCE_REG7_6_REG6_M 0x0000FFFF -#define AUX_SCE_REG7_6_REG6_S 0 +#define AUX_SCE_REG7_6_REG6_W 16 +#define AUX_SCE_REG7_6_REG6_M 0x0000FFFF +#define AUX_SCE_REG7_6_REG6_S 0 //***************************************************************************** // @@ -354,16 +354,16 @@ // Field: [31:16] STOP // // Internal. Only to be used through TI provided API. -#define AUX_SCE_LOOPADDR_STOP_W 16 -#define AUX_SCE_LOOPADDR_STOP_M 0xFFFF0000 -#define AUX_SCE_LOOPADDR_STOP_S 16 +#define AUX_SCE_LOOPADDR_STOP_W 16 +#define AUX_SCE_LOOPADDR_STOP_M 0xFFFF0000 +#define AUX_SCE_LOOPADDR_STOP_S 16 // Field: [15:0] START // // Internal. Only to be used through TI provided API. -#define AUX_SCE_LOOPADDR_START_W 16 -#define AUX_SCE_LOOPADDR_START_M 0x0000FFFF -#define AUX_SCE_LOOPADDR_START_S 0 +#define AUX_SCE_LOOPADDR_START_W 16 +#define AUX_SCE_LOOPADDR_START_M 0x0000FFFF +#define AUX_SCE_LOOPADDR_START_S 0 //***************************************************************************** // @@ -373,9 +373,8 @@ // Field: [7:0] ITER_LEFT // // Internal. Only to be used through TI provided API. -#define AUX_SCE_LOOPCNT_ITER_LEFT_W 8 -#define AUX_SCE_LOOPCNT_ITER_LEFT_M 0x000000FF -#define AUX_SCE_LOOPCNT_ITER_LEFT_S 0 - +#define AUX_SCE_LOOPCNT_ITER_LEFT_W 8 +#define AUX_SCE_LOOPCNT_ITER_LEFT_M 0x000000FF +#define AUX_SCE_LOOPCNT_ITER_LEFT_S 0 #endif // __AUX_SCE__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_smph.h index ec7fa57..d00d843 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_smph.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_smph.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_smph_h -* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) -* Revision: 49005 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_smph_h + * Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) + * Revision: 49005 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_SMPH_H__ #define __HW_AUX_SMPH_H__ @@ -44,31 +44,31 @@ // //***************************************************************************** // Semaphore 0 -#define AUX_SMPH_O_SMPH0 0x00000000 +#define AUX_SMPH_O_SMPH0 0x00000000 // Semaphore 1 -#define AUX_SMPH_O_SMPH1 0x00000004 +#define AUX_SMPH_O_SMPH1 0x00000004 // Semaphore 2 -#define AUX_SMPH_O_SMPH2 0x00000008 +#define AUX_SMPH_O_SMPH2 0x00000008 // Semaphore 3 -#define AUX_SMPH_O_SMPH3 0x0000000C +#define AUX_SMPH_O_SMPH3 0x0000000C // Semaphore 4 -#define AUX_SMPH_O_SMPH4 0x00000010 +#define AUX_SMPH_O_SMPH4 0x00000010 // Semaphore 5 -#define AUX_SMPH_O_SMPH5 0x00000014 +#define AUX_SMPH_O_SMPH5 0x00000014 // Semaphore 6 -#define AUX_SMPH_O_SMPH6 0x00000018 +#define AUX_SMPH_O_SMPH6 0x00000018 // Semaphore 7 -#define AUX_SMPH_O_SMPH7 0x0000001C +#define AUX_SMPH_O_SMPH7 0x0000001C // Auto Take -#define AUX_SMPH_O_AUTOTAKE 0x00000020 +#define AUX_SMPH_O_AUTOTAKE 0x00000020 //***************************************************************************** // @@ -88,10 +88,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH0_STAT 0x00000001 -#define AUX_SMPH_SMPH0_STAT_BITN 0 -#define AUX_SMPH_SMPH0_STAT_M 0x00000001 -#define AUX_SMPH_SMPH0_STAT_S 0 +#define AUX_SMPH_SMPH0_STAT 0x00000001 +#define AUX_SMPH_SMPH0_STAT_BITN 0 +#define AUX_SMPH_SMPH0_STAT_M 0x00000001 +#define AUX_SMPH_SMPH0_STAT_S 0 //***************************************************************************** // @@ -111,10 +111,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH1_STAT 0x00000001 -#define AUX_SMPH_SMPH1_STAT_BITN 0 -#define AUX_SMPH_SMPH1_STAT_M 0x00000001 -#define AUX_SMPH_SMPH1_STAT_S 0 +#define AUX_SMPH_SMPH1_STAT 0x00000001 +#define AUX_SMPH_SMPH1_STAT_BITN 0 +#define AUX_SMPH_SMPH1_STAT_M 0x00000001 +#define AUX_SMPH_SMPH1_STAT_S 0 //***************************************************************************** // @@ -134,10 +134,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH2_STAT 0x00000001 -#define AUX_SMPH_SMPH2_STAT_BITN 0 -#define AUX_SMPH_SMPH2_STAT_M 0x00000001 -#define AUX_SMPH_SMPH2_STAT_S 0 +#define AUX_SMPH_SMPH2_STAT 0x00000001 +#define AUX_SMPH_SMPH2_STAT_BITN 0 +#define AUX_SMPH_SMPH2_STAT_M 0x00000001 +#define AUX_SMPH_SMPH2_STAT_S 0 //***************************************************************************** // @@ -157,10 +157,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH3_STAT 0x00000001 -#define AUX_SMPH_SMPH3_STAT_BITN 0 -#define AUX_SMPH_SMPH3_STAT_M 0x00000001 -#define AUX_SMPH_SMPH3_STAT_S 0 +#define AUX_SMPH_SMPH3_STAT 0x00000001 +#define AUX_SMPH_SMPH3_STAT_BITN 0 +#define AUX_SMPH_SMPH3_STAT_M 0x00000001 +#define AUX_SMPH_SMPH3_STAT_S 0 //***************************************************************************** // @@ -180,10 +180,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH4_STAT 0x00000001 -#define AUX_SMPH_SMPH4_STAT_BITN 0 -#define AUX_SMPH_SMPH4_STAT_M 0x00000001 -#define AUX_SMPH_SMPH4_STAT_S 0 +#define AUX_SMPH_SMPH4_STAT 0x00000001 +#define AUX_SMPH_SMPH4_STAT_BITN 0 +#define AUX_SMPH_SMPH4_STAT_M 0x00000001 +#define AUX_SMPH_SMPH4_STAT_S 0 //***************************************************************************** // @@ -203,10 +203,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH5_STAT 0x00000001 -#define AUX_SMPH_SMPH5_STAT_BITN 0 -#define AUX_SMPH_SMPH5_STAT_M 0x00000001 -#define AUX_SMPH_SMPH5_STAT_S 0 +#define AUX_SMPH_SMPH5_STAT 0x00000001 +#define AUX_SMPH_SMPH5_STAT_BITN 0 +#define AUX_SMPH_SMPH5_STAT_M 0x00000001 +#define AUX_SMPH_SMPH5_STAT_S 0 //***************************************************************************** // @@ -226,10 +226,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH6_STAT 0x00000001 -#define AUX_SMPH_SMPH6_STAT_BITN 0 -#define AUX_SMPH_SMPH6_STAT_M 0x00000001 -#define AUX_SMPH_SMPH6_STAT_S 0 +#define AUX_SMPH_SMPH6_STAT 0x00000001 +#define AUX_SMPH_SMPH6_STAT_BITN 0 +#define AUX_SMPH_SMPH6_STAT_M 0x00000001 +#define AUX_SMPH_SMPH6_STAT_S 0 //***************************************************************************** // @@ -249,10 +249,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH7_STAT 0x00000001 -#define AUX_SMPH_SMPH7_STAT_BITN 0 -#define AUX_SMPH_SMPH7_STAT_M 0x00000001 -#define AUX_SMPH_SMPH7_STAT_S 0 +#define AUX_SMPH_SMPH7_STAT 0x00000001 +#define AUX_SMPH_SMPH7_STAT_BITN 0 +#define AUX_SMPH_SMPH7_STAT_M 0x00000001 +#define AUX_SMPH_SMPH7_STAT_S 0 //***************************************************************************** // @@ -274,9 +274,8 @@ // - Usage of this functionality must be restricted to one CPU core. // - Software must wait until AUX_EVCTL:EVSTAT0.AUX_SMPH_AUTOTAKE_DONE is 1 // before it writes a new value to SMPH_ID. -#define AUX_SMPH_AUTOTAKE_SMPH_ID_W 3 -#define AUX_SMPH_AUTOTAKE_SMPH_ID_M 0x00000007 -#define AUX_SMPH_AUTOTAKE_SMPH_ID_S 0 - +#define AUX_SMPH_AUTOTAKE_SMPH_ID_W 3 +#define AUX_SMPH_AUTOTAKE_SMPH_ID_M 0x00000007 +#define AUX_SMPH_AUTOTAKE_SMPH_ID_S 0 #endif // __AUX_SMPH__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_tdc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_tdc.h index 21d490e..ac99cb6 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_tdc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_tdc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_tdc_h -* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) -* Revision: 49005 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_tdc_h + * Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) + * Revision: 49005 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_TDC_H__ #define __HW_AUX_TDC_H__ @@ -44,34 +44,34 @@ // //***************************************************************************** // Control -#define AUX_TDC_O_CTL 0x00000000 +#define AUX_TDC_O_CTL 0x00000000 // Status -#define AUX_TDC_O_STAT 0x00000004 +#define AUX_TDC_O_STAT 0x00000004 // Result -#define AUX_TDC_O_RESULT 0x00000008 +#define AUX_TDC_O_RESULT 0x00000008 // Saturation Configuration -#define AUX_TDC_O_SATCFG 0x0000000C +#define AUX_TDC_O_SATCFG 0x0000000C // Trigger Source -#define AUX_TDC_O_TRIGSRC 0x00000010 +#define AUX_TDC_O_TRIGSRC 0x00000010 // Trigger Counter -#define AUX_TDC_O_TRIGCNT 0x00000014 +#define AUX_TDC_O_TRIGCNT 0x00000014 // Trigger Counter Load -#define AUX_TDC_O_TRIGCNTLOAD 0x00000018 +#define AUX_TDC_O_TRIGCNTLOAD 0x00000018 // Trigger Counter Configuration -#define AUX_TDC_O_TRIGCNTCFG 0x0000001C +#define AUX_TDC_O_TRIGCNTCFG 0x0000001C // Prescaler Control -#define AUX_TDC_O_PRECTL 0x00000020 +#define AUX_TDC_O_PRECTL 0x00000020 // Prescaler Counter -#define AUX_TDC_O_PRECNT 0x00000024 +#define AUX_TDC_O_PRECNT 0x00000024 //***************************************************************************** // @@ -107,13 +107,13 @@ // This is not needed as // prerequisite for a measurement. Reliable clear // is only guaranteed from IDLE state. -#define AUX_TDC_CTL_CMD_W 2 -#define AUX_TDC_CTL_CMD_M 0x00000003 -#define AUX_TDC_CTL_CMD_S 0 -#define AUX_TDC_CTL_CMD_ABORT 0x00000003 -#define AUX_TDC_CTL_CMD_RUN 0x00000002 -#define AUX_TDC_CTL_CMD_RUN_SYNC_START 0x00000001 -#define AUX_TDC_CTL_CMD_CLR_RESULT 0x00000000 +#define AUX_TDC_CTL_CMD_W 2 +#define AUX_TDC_CTL_CMD_M 0x00000003 +#define AUX_TDC_CTL_CMD_S 0 +#define AUX_TDC_CTL_CMD_ABORT 0x00000003 +#define AUX_TDC_CTL_CMD_RUN 0x00000002 +#define AUX_TDC_CTL_CMD_RUN_SYNC_START 0x00000001 +#define AUX_TDC_CTL_CMD_CLR_RESULT 0x00000000 //***************************************************************************** // @@ -129,10 +129,10 @@ // // This field is cleared when a new measurement is started or when CLR_RESULT // is written to CTL.CMD. -#define AUX_TDC_STAT_SAT 0x00000080 -#define AUX_TDC_STAT_SAT_BITN 7 -#define AUX_TDC_STAT_SAT_M 0x00000080 -#define AUX_TDC_STAT_SAT_S 7 +#define AUX_TDC_STAT_SAT 0x00000080 +#define AUX_TDC_STAT_SAT_BITN 7 +#define AUX_TDC_STAT_SAT_M 0x00000080 +#define AUX_TDC_STAT_SAT_S 7 // Field: [6] DONE // @@ -143,10 +143,10 @@ // // This field clears when a new TDC measurement starts or when you write // CLR_RESULT to CTL.CMD. -#define AUX_TDC_STAT_DONE 0x00000040 -#define AUX_TDC_STAT_DONE_BITN 6 -#define AUX_TDC_STAT_DONE_M 0x00000040 -#define AUX_TDC_STAT_DONE_S 6 +#define AUX_TDC_STAT_DONE 0x00000040 +#define AUX_TDC_STAT_DONE_BITN 6 +#define AUX_TDC_STAT_DONE_M 0x00000040 +#define AUX_TDC_STAT_DONE_S 6 // Field: [5:0] STATE // @@ -192,20 +192,20 @@ // looks for the start condition. The state // machine waits for the fast-counter to // increment. -#define AUX_TDC_STAT_STATE_W 6 -#define AUX_TDC_STAT_STATE_M 0x0000003F -#define AUX_TDC_STAT_STATE_S 0 -#define AUX_TDC_STAT_STATE_FORCE_STOP 0x0000002E -#define AUX_TDC_STAT_STATE_START_FALL 0x0000001E -#define AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE 0x00000016 -#define AUX_TDC_STAT_STATE_POR 0x0000000F -#define AUX_TDC_STAT_STATE_GET_RESULT 0x0000000E -#define AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN 0x0000000C -#define AUX_TDC_STAT_STATE_WAIT_STOP 0x00000008 -#define AUX_TDC_STAT_STATE_CLR_CNT 0x00000007 -#define AUX_TDC_STAT_STATE_IDLE 0x00000006 -#define AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN 0x00000004 -#define AUX_TDC_STAT_STATE_WAIT_START 0x00000000 +#define AUX_TDC_STAT_STATE_W 6 +#define AUX_TDC_STAT_STATE_M 0x0000003F +#define AUX_TDC_STAT_STATE_S 0 +#define AUX_TDC_STAT_STATE_FORCE_STOP 0x0000002E +#define AUX_TDC_STAT_STATE_START_FALL 0x0000001E +#define AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE 0x00000016 +#define AUX_TDC_STAT_STATE_POR 0x0000000F +#define AUX_TDC_STAT_STATE_GET_RESULT 0x0000000E +#define AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN 0x0000000C +#define AUX_TDC_STAT_STATE_WAIT_STOP 0x00000008 +#define AUX_TDC_STAT_STATE_CLR_CNT 0x00000007 +#define AUX_TDC_STAT_STATE_IDLE 0x00000006 +#define AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN 0x00000004 +#define AUX_TDC_STAT_STATE_WAIT_START 0x00000000 //***************************************************************************** // @@ -224,9 +224,9 @@ // takes a non-zero time to stop the measurement. Hence, the maximum value of // this field becomes slightly higher than 2^24 if you configure SATCFG.LIMIT // to R24. -#define AUX_TDC_RESULT_VALUE_W 25 -#define AUX_TDC_RESULT_VALUE_M 0x01FFFFFF -#define AUX_TDC_RESULT_VALUE_S 0 +#define AUX_TDC_RESULT_VALUE_W 25 +#define AUX_TDC_RESULT_VALUE_M 0x01FFFFFF +#define AUX_TDC_RESULT_VALUE_S 0 //***************************************************************************** // @@ -267,22 +267,22 @@ // when RESULT.VALUE[13] is set. // R12 Result bit 12: TDC conversion saturates and stops // when RESULT.VALUE[12] is set. -#define AUX_TDC_SATCFG_LIMIT_W 4 -#define AUX_TDC_SATCFG_LIMIT_M 0x0000000F -#define AUX_TDC_SATCFG_LIMIT_S 0 -#define AUX_TDC_SATCFG_LIMIT_R24 0x0000000F -#define AUX_TDC_SATCFG_LIMIT_R23 0x0000000E -#define AUX_TDC_SATCFG_LIMIT_R22 0x0000000D -#define AUX_TDC_SATCFG_LIMIT_R21 0x0000000C -#define AUX_TDC_SATCFG_LIMIT_R20 0x0000000B -#define AUX_TDC_SATCFG_LIMIT_R19 0x0000000A -#define AUX_TDC_SATCFG_LIMIT_R18 0x00000009 -#define AUX_TDC_SATCFG_LIMIT_R17 0x00000008 -#define AUX_TDC_SATCFG_LIMIT_R16 0x00000007 -#define AUX_TDC_SATCFG_LIMIT_R15 0x00000006 -#define AUX_TDC_SATCFG_LIMIT_R14 0x00000005 -#define AUX_TDC_SATCFG_LIMIT_R13 0x00000004 -#define AUX_TDC_SATCFG_LIMIT_R12 0x00000003 +#define AUX_TDC_SATCFG_LIMIT_W 4 +#define AUX_TDC_SATCFG_LIMIT_M 0x0000000F +#define AUX_TDC_SATCFG_LIMIT_S 0 +#define AUX_TDC_SATCFG_LIMIT_R24 0x0000000F +#define AUX_TDC_SATCFG_LIMIT_R23 0x0000000E +#define AUX_TDC_SATCFG_LIMIT_R22 0x0000000D +#define AUX_TDC_SATCFG_LIMIT_R21 0x0000000C +#define AUX_TDC_SATCFG_LIMIT_R20 0x0000000B +#define AUX_TDC_SATCFG_LIMIT_R19 0x0000000A +#define AUX_TDC_SATCFG_LIMIT_R18 0x00000009 +#define AUX_TDC_SATCFG_LIMIT_R17 0x00000008 +#define AUX_TDC_SATCFG_LIMIT_R16 0x00000007 +#define AUX_TDC_SATCFG_LIMIT_R15 0x00000006 +#define AUX_TDC_SATCFG_LIMIT_R14 0x00000005 +#define AUX_TDC_SATCFG_LIMIT_R13 0x00000004 +#define AUX_TDC_SATCFG_LIMIT_R12 0x00000003 //***************************************************************************** // @@ -297,12 +297,12 @@ // ENUMs: // LOW TDC conversion stops when low level is detected. // HIGH TDC conversion stops when high level is detected. -#define AUX_TDC_TRIGSRC_STOP_POL 0x00002000 -#define AUX_TDC_TRIGSRC_STOP_POL_BITN 13 -#define AUX_TDC_TRIGSRC_STOP_POL_M 0x00002000 -#define AUX_TDC_TRIGSRC_STOP_POL_S 13 -#define AUX_TDC_TRIGSRC_STOP_POL_LOW 0x00002000 -#define AUX_TDC_TRIGSRC_STOP_POL_HIGH 0x00000000 +#define AUX_TDC_TRIGSRC_STOP_POL 0x00002000 +#define AUX_TDC_TRIGSRC_STOP_POL_BITN 13 +#define AUX_TDC_TRIGSRC_STOP_POL_M 0x00002000 +#define AUX_TDC_TRIGSRC_STOP_POL_S 13 +#define AUX_TDC_TRIGSRC_STOP_POL_LOW 0x00002000 +#define AUX_TDC_TRIGSRC_STOP_POL_HIGH 0x00000000 // Field: [12:8] STOP_SRC // @@ -343,41 +343,41 @@ // AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB // AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA // AON_RTC_CH2 AUX_EVCTL:EVSTAT0.AON_RTC_CH2 -#define AUX_TDC_TRIGSRC_STOP_SRC_W 5 -#define AUX_TDC_TRIGSRC_STOP_SRC_M 0x00001F00 -#define AUX_TDC_TRIGSRC_STOP_SRC_S 8 -#define AUX_TDC_TRIGSRC_STOP_SRC_TDC_PRE 0x00001F00 -#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV 0x00001E00 -#define AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF 0x00001D00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15 0x00001C00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14 0x00001B00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13 0x00001A00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12 0x00001900 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11 0x00001800 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10 0x00001700 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9 0x00001600 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8 0x00001500 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7 0x00001400 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6 0x00001300 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5 0x00001200 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4 0x00001100 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3 0x00001000 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2 0x00000F00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1 0x00000E00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0 0x00000D00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AON_PROG_WU 0x00000C00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AON_SW 0x00000B00 -#define AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX1 0x00000A00 -#define AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX0 0x00000900 -#define AUX_TDC_TRIGSRC_STOP_SRC_ADC_FIFO_ALMOST_FULL 0x00000800 -#define AUX_TDC_TRIGSRC_STOP_SRC_ADC_DONE 0x00000700 -#define AUX_TDC_TRIGSRC_STOP_SRC_SMPH_AUTOTAKE_DONE 0x00000600 -#define AUX_TDC_TRIGSRC_STOP_SRC_TIMER1_EV 0x00000500 -#define AUX_TDC_TRIGSRC_STOP_SRC_TIMER0_EV 0x00000400 -#define AUX_TDC_TRIGSRC_STOP_SRC_ISRC_RESET 0x00000300 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB 0x00000200 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA 0x00000100 -#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2 0x00000000 +#define AUX_TDC_TRIGSRC_STOP_SRC_W 5 +#define AUX_TDC_TRIGSRC_STOP_SRC_M 0x00001F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_S 8 +#define AUX_TDC_TRIGSRC_STOP_SRC_TDC_PRE 0x00001F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV 0x00001E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF 0x00001D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15 0x00001C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14 0x00001B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13 0x00001A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12 0x00001900 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11 0x00001800 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10 0x00001700 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9 0x00001600 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8 0x00001500 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7 0x00001400 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6 0x00001300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5 0x00001200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4 0x00001100 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3 0x00001000 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2 0x00000F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1 0x00000E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0 0x00000D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_PROG_WU 0x00000C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_SW 0x00000B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX1 0x00000A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX0 0x00000900 +#define AUX_TDC_TRIGSRC_STOP_SRC_ADC_FIFO_ALMOST_FULL 0x00000800 +#define AUX_TDC_TRIGSRC_STOP_SRC_ADC_DONE 0x00000700 +#define AUX_TDC_TRIGSRC_STOP_SRC_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_TDC_TRIGSRC_STOP_SRC_TIMER1_EV 0x00000500 +#define AUX_TDC_TRIGSRC_STOP_SRC_TIMER0_EV 0x00000400 +#define AUX_TDC_TRIGSRC_STOP_SRC_ISRC_RESET 0x00000300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB 0x00000200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA 0x00000100 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2 0x00000000 // Field: [5] START_POL // @@ -387,12 +387,12 @@ // ENUMs: // LOW TDC conversion starts when low level is detected. // HIGH TDC conversion starts when high level is detected. -#define AUX_TDC_TRIGSRC_START_POL 0x00000020 -#define AUX_TDC_TRIGSRC_START_POL_BITN 5 -#define AUX_TDC_TRIGSRC_START_POL_M 0x00000020 -#define AUX_TDC_TRIGSRC_START_POL_S 5 -#define AUX_TDC_TRIGSRC_START_POL_LOW 0x00000020 -#define AUX_TDC_TRIGSRC_START_POL_HIGH 0x00000000 +#define AUX_TDC_TRIGSRC_START_POL 0x00000020 +#define AUX_TDC_TRIGSRC_START_POL_BITN 5 +#define AUX_TDC_TRIGSRC_START_POL_M 0x00000020 +#define AUX_TDC_TRIGSRC_START_POL_S 5 +#define AUX_TDC_TRIGSRC_START_POL_LOW 0x00000020 +#define AUX_TDC_TRIGSRC_START_POL_HIGH 0x00000000 // Field: [4:0] START_SRC // @@ -433,41 +433,41 @@ // AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB // AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA // AON_RTC_CH2 AUX_EVCTL:EVSTAT0.AON_RTC_CH2 -#define AUX_TDC_TRIGSRC_START_SRC_W 5 -#define AUX_TDC_TRIGSRC_START_SRC_M 0x0000001F -#define AUX_TDC_TRIGSRC_START_SRC_S 0 -#define AUX_TDC_TRIGSRC_START_SRC_TDC_PRE 0x0000001F -#define AUX_TDC_TRIGSRC_START_SRC_MCU_EV 0x0000001E -#define AUX_TDC_TRIGSRC_START_SRC_ACLK_REF 0x0000001D -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO15 0x0000001C -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO14 0x0000001B -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO13 0x0000001A -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO12 0x00000019 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO11 0x00000018 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO10 0x00000017 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO9 0x00000016 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO8 0x00000015 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO7 0x00000014 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO6 0x00000013 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO5 0x00000012 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO4 0x00000011 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO3 0x00000010 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO2 0x0000000F -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO1 0x0000000E -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO0 0x0000000D -#define AUX_TDC_TRIGSRC_START_SRC_AON_PROG_WU 0x0000000C -#define AUX_TDC_TRIGSRC_START_SRC_AON_SW 0x0000000B -#define AUX_TDC_TRIGSRC_START_SRC_OBSMUX1 0x0000000A -#define AUX_TDC_TRIGSRC_START_SRC_OBSMUX0 0x00000009 -#define AUX_TDC_TRIGSRC_START_SRC_ADC_FIFO_ALMOST_FULL 0x00000008 -#define AUX_TDC_TRIGSRC_START_SRC_ADC_DONE 0x00000007 -#define AUX_TDC_TRIGSRC_START_SRC_SMPH_AUTOTAKE_DONE 0x00000006 -#define AUX_TDC_TRIGSRC_START_SRC_TIMER1_EV 0x00000005 -#define AUX_TDC_TRIGSRC_START_SRC_TIMER0_EV 0x00000004 -#define AUX_TDC_TRIGSRC_START_SRC_ISRC_RESET 0x00000003 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB 0x00000002 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA 0x00000001 -#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2 0x00000000 +#define AUX_TDC_TRIGSRC_START_SRC_W 5 +#define AUX_TDC_TRIGSRC_START_SRC_M 0x0000001F +#define AUX_TDC_TRIGSRC_START_SRC_S 0 +#define AUX_TDC_TRIGSRC_START_SRC_TDC_PRE 0x0000001F +#define AUX_TDC_TRIGSRC_START_SRC_MCU_EV 0x0000001E +#define AUX_TDC_TRIGSRC_START_SRC_ACLK_REF 0x0000001D +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO15 0x0000001C +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO14 0x0000001B +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO13 0x0000001A +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO12 0x00000019 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO11 0x00000018 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO10 0x00000017 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO9 0x00000016 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO8 0x00000015 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO7 0x00000014 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO6 0x00000013 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO5 0x00000012 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO4 0x00000011 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO3 0x00000010 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO2 0x0000000F +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO1 0x0000000E +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO0 0x0000000D +#define AUX_TDC_TRIGSRC_START_SRC_AON_PROG_WU 0x0000000C +#define AUX_TDC_TRIGSRC_START_SRC_AON_SW 0x0000000B +#define AUX_TDC_TRIGSRC_START_SRC_OBSMUX1 0x0000000A +#define AUX_TDC_TRIGSRC_START_SRC_OBSMUX0 0x00000009 +#define AUX_TDC_TRIGSRC_START_SRC_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_TDC_TRIGSRC_START_SRC_ADC_DONE 0x00000007 +#define AUX_TDC_TRIGSRC_START_SRC_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_TDC_TRIGSRC_START_SRC_TIMER1_EV 0x00000005 +#define AUX_TDC_TRIGSRC_START_SRC_TIMER0_EV 0x00000004 +#define AUX_TDC_TRIGSRC_START_SRC_ISRC_RESET 0x00000003 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB 0x00000002 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA 0x00000001 +#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2 0x00000000 //***************************************************************************** // @@ -487,9 +487,9 @@ // // When AUX_TDC:TRIGCNTCFG.EN is 1, TRIGCNTLOAD.CNT is loaded into CNT at the // start of the measurement. -#define AUX_TDC_TRIGCNT_CNT_W 16 -#define AUX_TDC_TRIGCNT_CNT_M 0x0000FFFF -#define AUX_TDC_TRIGCNT_CNT_S 0 +#define AUX_TDC_TRIGCNT_CNT_W 16 +#define AUX_TDC_TRIGCNT_CNT_M 0x0000FFFF +#define AUX_TDC_TRIGCNT_CNT_S 0 //***************************************************************************** // @@ -518,9 +518,9 @@ // // When AUX_TDC:TRIGCNTCFG.EN is 1, CNT is loaded into TRIGCNT.CNT at the start // of the measurement. -#define AUX_TDC_TRIGCNTLOAD_CNT_W 16 -#define AUX_TDC_TRIGCNTLOAD_CNT_M 0x0000FFFF -#define AUX_TDC_TRIGCNTLOAD_CNT_S 0 +#define AUX_TDC_TRIGCNTLOAD_CNT_W 16 +#define AUX_TDC_TRIGCNTLOAD_CNT_M 0x0000FFFF +#define AUX_TDC_TRIGCNTLOAD_CNT_S 0 //***************************************************************************** // @@ -535,10 +535,10 @@ // 1: Enable stop-counter. // // Change only while STAT.STATE is IDLE. -#define AUX_TDC_TRIGCNTCFG_EN 0x00000001 -#define AUX_TDC_TRIGCNTCFG_EN_BITN 0 -#define AUX_TDC_TRIGCNTCFG_EN_M 0x00000001 -#define AUX_TDC_TRIGCNTCFG_EN_S 0 +#define AUX_TDC_TRIGCNTCFG_EN 0x00000001 +#define AUX_TDC_TRIGCNTCFG_EN_BITN 0 +#define AUX_TDC_TRIGCNTCFG_EN_M 0x00000001 +#define AUX_TDC_TRIGCNTCFG_EN_S 0 //***************************************************************************** // @@ -553,10 +553,10 @@ // 1: Release reset of prescaler. // // AUX_TDC_PRE event becomes 0 when you reset the prescaler. -#define AUX_TDC_PRECTL_RESET_N 0x00000080 -#define AUX_TDC_PRECTL_RESET_N_BITN 7 -#define AUX_TDC_PRECTL_RESET_N_M 0x00000080 -#define AUX_TDC_PRECTL_RESET_N_S 7 +#define AUX_TDC_PRECTL_RESET_N 0x00000080 +#define AUX_TDC_PRECTL_RESET_N_BITN 7 +#define AUX_TDC_PRECTL_RESET_N_M 0x00000080 +#define AUX_TDC_PRECTL_RESET_N_S 7 // Field: [6] RATIO // @@ -576,12 +576,12 @@ // rising edge for every 16 rising edges of the // input. AUX_TDC_PRE event toggles on every 8th // rising edge of the input. -#define AUX_TDC_PRECTL_RATIO 0x00000040 -#define AUX_TDC_PRECTL_RATIO_BITN 6 -#define AUX_TDC_PRECTL_RATIO_M 0x00000040 -#define AUX_TDC_PRECTL_RATIO_S 6 -#define AUX_TDC_PRECTL_RATIO_DIV64 0x00000040 -#define AUX_TDC_PRECTL_RATIO_DIV16 0x00000000 +#define AUX_TDC_PRECTL_RATIO 0x00000040 +#define AUX_TDC_PRECTL_RATIO_BITN 6 +#define AUX_TDC_PRECTL_RATIO_M 0x00000040 +#define AUX_TDC_PRECTL_RATIO_S 6 +#define AUX_TDC_PRECTL_RATIO_DIV64 0x00000040 +#define AUX_TDC_PRECTL_RATIO_DIV16 0x00000000 // Field: [4:0] SRC // @@ -624,41 +624,41 @@ // AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB // AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA // AON_RTC_CH2 AUX_EVCTL:EVSTAT0.AON_RTC_CH2 -#define AUX_TDC_PRECTL_SRC_W 5 -#define AUX_TDC_PRECTL_SRC_M 0x0000001F -#define AUX_TDC_PRECTL_SRC_S 0 -#define AUX_TDC_PRECTL_SRC_ADC_IRQ 0x0000001F -#define AUX_TDC_PRECTL_SRC_MCU_EV 0x0000001E -#define AUX_TDC_PRECTL_SRC_ACLK_REF 0x0000001D -#define AUX_TDC_PRECTL_SRC_AUXIO15 0x0000001C -#define AUX_TDC_PRECTL_SRC_AUXIO14 0x0000001B -#define AUX_TDC_PRECTL_SRC_AUXIO13 0x0000001A -#define AUX_TDC_PRECTL_SRC_AUXIO12 0x00000019 -#define AUX_TDC_PRECTL_SRC_AUXIO11 0x00000018 -#define AUX_TDC_PRECTL_SRC_AUXIO10 0x00000017 -#define AUX_TDC_PRECTL_SRC_AUXIO9 0x00000016 -#define AUX_TDC_PRECTL_SRC_AUXIO8 0x00000015 -#define AUX_TDC_PRECTL_SRC_AUXIO7 0x00000014 -#define AUX_TDC_PRECTL_SRC_AUXIO6 0x00000013 -#define AUX_TDC_PRECTL_SRC_AUXIO5 0x00000012 -#define AUX_TDC_PRECTL_SRC_AUXIO4 0x00000011 -#define AUX_TDC_PRECTL_SRC_AUXIO3 0x00000010 -#define AUX_TDC_PRECTL_SRC_AUXIO2 0x0000000F -#define AUX_TDC_PRECTL_SRC_AUXIO1 0x0000000E -#define AUX_TDC_PRECTL_SRC_AUXIO0 0x0000000D -#define AUX_TDC_PRECTL_SRC_AON_PROG_WU 0x0000000C -#define AUX_TDC_PRECTL_SRC_AON_SW 0x0000000B -#define AUX_TDC_PRECTL_SRC_OBSMUX1 0x0000000A -#define AUX_TDC_PRECTL_SRC_OBSMUX0 0x00000009 -#define AUX_TDC_PRECTL_SRC_ADC_FIFO_ALMOST_FULL 0x00000008 -#define AUX_TDC_PRECTL_SRC_ADC_DONE 0x00000007 -#define AUX_TDC_PRECTL_SRC_SMPH_AUTOTAKE_DONE 0x00000006 -#define AUX_TDC_PRECTL_SRC_TIMER1_EV 0x00000005 -#define AUX_TDC_PRECTL_SRC_TIMER0_EV 0x00000004 -#define AUX_TDC_PRECTL_SRC_ISRC_RESET 0x00000003 -#define AUX_TDC_PRECTL_SRC_AUX_COMPB 0x00000002 -#define AUX_TDC_PRECTL_SRC_AUX_COMPA 0x00000001 -#define AUX_TDC_PRECTL_SRC_AON_RTC_CH2 0x00000000 +#define AUX_TDC_PRECTL_SRC_W 5 +#define AUX_TDC_PRECTL_SRC_M 0x0000001F +#define AUX_TDC_PRECTL_SRC_S 0 +#define AUX_TDC_PRECTL_SRC_ADC_IRQ 0x0000001F +#define AUX_TDC_PRECTL_SRC_MCU_EV 0x0000001E +#define AUX_TDC_PRECTL_SRC_ACLK_REF 0x0000001D +#define AUX_TDC_PRECTL_SRC_AUXIO15 0x0000001C +#define AUX_TDC_PRECTL_SRC_AUXIO14 0x0000001B +#define AUX_TDC_PRECTL_SRC_AUXIO13 0x0000001A +#define AUX_TDC_PRECTL_SRC_AUXIO12 0x00000019 +#define AUX_TDC_PRECTL_SRC_AUXIO11 0x00000018 +#define AUX_TDC_PRECTL_SRC_AUXIO10 0x00000017 +#define AUX_TDC_PRECTL_SRC_AUXIO9 0x00000016 +#define AUX_TDC_PRECTL_SRC_AUXIO8 0x00000015 +#define AUX_TDC_PRECTL_SRC_AUXIO7 0x00000014 +#define AUX_TDC_PRECTL_SRC_AUXIO6 0x00000013 +#define AUX_TDC_PRECTL_SRC_AUXIO5 0x00000012 +#define AUX_TDC_PRECTL_SRC_AUXIO4 0x00000011 +#define AUX_TDC_PRECTL_SRC_AUXIO3 0x00000010 +#define AUX_TDC_PRECTL_SRC_AUXIO2 0x0000000F +#define AUX_TDC_PRECTL_SRC_AUXIO1 0x0000000E +#define AUX_TDC_PRECTL_SRC_AUXIO0 0x0000000D +#define AUX_TDC_PRECTL_SRC_AON_PROG_WU 0x0000000C +#define AUX_TDC_PRECTL_SRC_AON_SW 0x0000000B +#define AUX_TDC_PRECTL_SRC_OBSMUX1 0x0000000A +#define AUX_TDC_PRECTL_SRC_OBSMUX0 0x00000009 +#define AUX_TDC_PRECTL_SRC_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_TDC_PRECTL_SRC_ADC_DONE 0x00000007 +#define AUX_TDC_PRECTL_SRC_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_TDC_PRECTL_SRC_TIMER1_EV 0x00000005 +#define AUX_TDC_PRECTL_SRC_TIMER0_EV 0x00000004 +#define AUX_TDC_PRECTL_SRC_ISRC_RESET 0x00000003 +#define AUX_TDC_PRECTL_SRC_AUX_COMPB 0x00000002 +#define AUX_TDC_PRECTL_SRC_AUX_COMPA 0x00000001 +#define AUX_TDC_PRECTL_SRC_AON_RTC_CH2 0x00000000 //***************************************************************************** // @@ -686,9 +686,8 @@ // - The prescaler counter is reset to 2 by PRECTL.RESET_N. // - The captured value is 2 when the number of rising edges on prescaler input // is less than 3. Otherwise, captured value equals number of event pulses - 1. -#define AUX_TDC_PRECNT_CNT_W 16 -#define AUX_TDC_PRECNT_CNT_M 0x0000FFFF -#define AUX_TDC_PRECNT_CNT_S 0 - +#define AUX_TDC_PRECNT_CNT_W 16 +#define AUX_TDC_PRECNT_CNT_M 0x0000FFFF +#define AUX_TDC_PRECNT_CNT_S 0 #endif // __AUX_TDC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_timer.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_timer.h index ad0aa1e..3342ade 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_timer.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_timer.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_timer_h -* Revised: 2017-05-22 18:50:33 +0200 (Mon, 22 May 2017) -* Revision: 49040 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_timer_h + * Revised: 2017-05-22 18:50:33 +0200 (Mon, 22 May 2017) + * Revision: 49040 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_TIMER_H__ #define __HW_AUX_TIMER_H__ @@ -44,22 +44,22 @@ // //***************************************************************************** // Timer 0 Configuration -#define AUX_TIMER_O_T0CFG 0x00000000 +#define AUX_TIMER_O_T0CFG 0x00000000 // Timer 1 Configuration -#define AUX_TIMER_O_T1CFG 0x00000004 +#define AUX_TIMER_O_T1CFG 0x00000004 // Timer 0 Control -#define AUX_TIMER_O_T0CTL 0x00000008 +#define AUX_TIMER_O_T0CTL 0x00000008 // Timer 0 Target -#define AUX_TIMER_O_T0TARGET 0x0000000C +#define AUX_TIMER_O_T0TARGET 0x0000000C // Timer 1 Target -#define AUX_TIMER_O_T1TARGET 0x00000010 +#define AUX_TIMER_O_T1TARGET 0x00000010 // Timer 1 Control -#define AUX_TIMER_O_T1CTL 0x00000014 +#define AUX_TIMER_O_T1CTL 0x00000014 //***************************************************************************** // @@ -72,12 +72,12 @@ // ENUMs: // FALL Count on falling edges of TICK_SRC. // RISE Count on rising edges of TICK_SRC. -#define AUX_TIMER_T0CFG_TICK_SRC_POL 0x00002000 -#define AUX_TIMER_T0CFG_TICK_SRC_POL_BITN 13 -#define AUX_TIMER_T0CFG_TICK_SRC_POL_M 0x00002000 -#define AUX_TIMER_T0CFG_TICK_SRC_POL_S 13 -#define AUX_TIMER_T0CFG_TICK_SRC_POL_FALL 0x00002000 -#define AUX_TIMER_T0CFG_TICK_SRC_POL_RISE 0x00000000 +#define AUX_TIMER_T0CFG_TICK_SRC_POL 0x00002000 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_BITN 13 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_M 0x00002000 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_S 13 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_FALL 0x00002000 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_RISE 0x00000000 // Field: [12:8] TICK_SRC // @@ -115,40 +115,40 @@ // AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB // AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA // RTC_CH2_EV AUX_EVCTL:EVSTAT0.AON_RTC_CH2 -#define AUX_TIMER_T0CFG_TICK_SRC_W 5 -#define AUX_TIMER_T0CFG_TICK_SRC_M 0x00001F00 -#define AUX_TIMER_T0CFG_TICK_SRC_S 8 -#define AUX_TIMER_T0CFG_TICK_SRC_ADC_IRQ 0x00001F00 -#define AUX_TIMER_T0CFG_TICK_SRC_MCU_EVENT 0x00001E00 -#define AUX_TIMER_T0CFG_TICK_SRC_ACLK_REF 0x00001D00 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO15 0x00001C00 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO14 0x00001B00 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO13 0x00001A00 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO12 0x00001900 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO11 0x00001800 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO10 0x00001700 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO9 0x00001600 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO8 0x00001500 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO7 0x00001400 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO6 0x00001300 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO5 0x00001200 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO4 0x00001100 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO3 0x00001000 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO2 0x00000F00 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO1 0x00000E00 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO0 0x00000D00 -#define AUX_TIMER_T0CFG_TICK_SRC_AON_PROG_WU 0x00000C00 -#define AUX_TIMER_T0CFG_TICK_SRC_AON_SW 0x00000B00 -#define AUX_TIMER_T0CFG_TICK_SRC_OBSMUX1 0x00000A00 -#define AUX_TIMER_T0CFG_TICK_SRC_OBSMUX0 0x00000900 -#define AUX_TIMER_T0CFG_TICK_SRC_RTC_4KHZ 0x00000800 -#define AUX_TIMER_T0CFG_TICK_SRC_ADC_DONE 0x00000700 -#define AUX_TIMER_T0CFG_TICK_SRC_SMPH_AUTOTAKE_DONE 0x00000600 -#define AUX_TIMER_T0CFG_TICK_SRC_TIMER1_EV 0x00000500 -#define AUX_TIMER_T0CFG_TICK_SRC_TDC_DONE 0x00000300 -#define AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPB 0x00000200 -#define AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPA 0x00000100 -#define AUX_TIMER_T0CFG_TICK_SRC_RTC_CH2_EV 0x00000000 +#define AUX_TIMER_T0CFG_TICK_SRC_W 5 +#define AUX_TIMER_T0CFG_TICK_SRC_M 0x00001F00 +#define AUX_TIMER_T0CFG_TICK_SRC_S 8 +#define AUX_TIMER_T0CFG_TICK_SRC_ADC_IRQ 0x00001F00 +#define AUX_TIMER_T0CFG_TICK_SRC_MCU_EVENT 0x00001E00 +#define AUX_TIMER_T0CFG_TICK_SRC_ACLK_REF 0x00001D00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO15 0x00001C00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO14 0x00001B00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO13 0x00001A00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO12 0x00001900 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO11 0x00001800 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO10 0x00001700 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO9 0x00001600 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO8 0x00001500 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO7 0x00001400 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO6 0x00001300 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO5 0x00001200 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO4 0x00001100 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO3 0x00001000 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO2 0x00000F00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO1 0x00000E00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO0 0x00000D00 +#define AUX_TIMER_T0CFG_TICK_SRC_AON_PROG_WU 0x00000C00 +#define AUX_TIMER_T0CFG_TICK_SRC_AON_SW 0x00000B00 +#define AUX_TIMER_T0CFG_TICK_SRC_OBSMUX1 0x00000A00 +#define AUX_TIMER_T0CFG_TICK_SRC_OBSMUX0 0x00000900 +#define AUX_TIMER_T0CFG_TICK_SRC_RTC_4KHZ 0x00000800 +#define AUX_TIMER_T0CFG_TICK_SRC_ADC_DONE 0x00000700 +#define AUX_TIMER_T0CFG_TICK_SRC_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_TIMER_T0CFG_TICK_SRC_TIMER1_EV 0x00000500 +#define AUX_TIMER_T0CFG_TICK_SRC_TDC_DONE 0x00000300 +#define AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPB 0x00000200 +#define AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPA 0x00000100 +#define AUX_TIMER_T0CFG_TICK_SRC_RTC_CH2_EV 0x00000000 // Field: [7:4] PRE // @@ -159,9 +159,9 @@ // 0x2: Divide by 4. // ... // 0xF: Divide by 32,768. -#define AUX_TIMER_T0CFG_PRE_W 4 -#define AUX_TIMER_T0CFG_PRE_M 0x000000F0 -#define AUX_TIMER_T0CFG_PRE_S 4 +#define AUX_TIMER_T0CFG_PRE_W 4 +#define AUX_TIMER_T0CFG_PRE_M 0x000000F0 +#define AUX_TIMER_T0CFG_PRE_S 4 // Field: [1] MODE // @@ -171,12 +171,12 @@ // ENUMs: // TICK Use event set by TICK_SRC as source for prescaler. // CLK Use AUX clock as source for prescaler. -#define AUX_TIMER_T0CFG_MODE 0x00000002 -#define AUX_TIMER_T0CFG_MODE_BITN 1 -#define AUX_TIMER_T0CFG_MODE_M 0x00000002 -#define AUX_TIMER_T0CFG_MODE_S 1 -#define AUX_TIMER_T0CFG_MODE_TICK 0x00000002 -#define AUX_TIMER_T0CFG_MODE_CLK 0x00000000 +#define AUX_TIMER_T0CFG_MODE 0x00000002 +#define AUX_TIMER_T0CFG_MODE_BITN 1 +#define AUX_TIMER_T0CFG_MODE_M 0x00000002 +#define AUX_TIMER_T0CFG_MODE_S 1 +#define AUX_TIMER_T0CFG_MODE_TICK 0x00000002 +#define AUX_TIMER_T0CFG_MODE_CLK 0x00000000 // Field: [0] RELOAD // @@ -193,12 +193,12 @@ // T0CTL.EN becomes 0 when the counter value // becomes equal to or greater than // T0TARGET.VALUE. -#define AUX_TIMER_T0CFG_RELOAD 0x00000001 -#define AUX_TIMER_T0CFG_RELOAD_BITN 0 -#define AUX_TIMER_T0CFG_RELOAD_M 0x00000001 -#define AUX_TIMER_T0CFG_RELOAD_S 0 -#define AUX_TIMER_T0CFG_RELOAD_CONT 0x00000001 -#define AUX_TIMER_T0CFG_RELOAD_MAN 0x00000000 +#define AUX_TIMER_T0CFG_RELOAD 0x00000001 +#define AUX_TIMER_T0CFG_RELOAD_BITN 0 +#define AUX_TIMER_T0CFG_RELOAD_M 0x00000001 +#define AUX_TIMER_T0CFG_RELOAD_S 0 +#define AUX_TIMER_T0CFG_RELOAD_CONT 0x00000001 +#define AUX_TIMER_T0CFG_RELOAD_MAN 0x00000000 //***************************************************************************** // @@ -211,12 +211,12 @@ // ENUMs: // FALL Count on falling edges of TICK_SRC. // RISE Count on rising edges of TICK_SRC. -#define AUX_TIMER_T1CFG_TICK_SRC_POL 0x00002000 -#define AUX_TIMER_T1CFG_TICK_SRC_POL_BITN 13 -#define AUX_TIMER_T1CFG_TICK_SRC_POL_M 0x00002000 -#define AUX_TIMER_T1CFG_TICK_SRC_POL_S 13 -#define AUX_TIMER_T1CFG_TICK_SRC_POL_FALL 0x00002000 -#define AUX_TIMER_T1CFG_TICK_SRC_POL_RISE 0x00000000 +#define AUX_TIMER_T1CFG_TICK_SRC_POL 0x00002000 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_BITN 13 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_M 0x00002000 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_S 13 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_FALL 0x00002000 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_RISE 0x00000000 // Field: [12:8] TICK_SRC // @@ -254,40 +254,40 @@ // AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB // AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA // RTC_CH2_EV AUX_EVCTL:EVSTAT0.AON_RTC_CH2 -#define AUX_TIMER_T1CFG_TICK_SRC_W 5 -#define AUX_TIMER_T1CFG_TICK_SRC_M 0x00001F00 -#define AUX_TIMER_T1CFG_TICK_SRC_S 8 -#define AUX_TIMER_T1CFG_TICK_SRC_ADC_IRQ 0x00001F00 -#define AUX_TIMER_T1CFG_TICK_SRC_MCU_EVENT 0x00001E00 -#define AUX_TIMER_T1CFG_TICK_SRC_ACLK_REF 0x00001D00 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO15 0x00001C00 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO14 0x00001B00 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO13 0x00001A00 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO12 0x00001900 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO11 0x00001800 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO10 0x00001700 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO9 0x00001600 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO8 0x00001500 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO7 0x00001400 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO6 0x00001300 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO5 0x00001200 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO4 0x00001100 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO3 0x00001000 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO2 0x00000F00 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO1 0x00000E00 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO0 0x00000D00 -#define AUX_TIMER_T1CFG_TICK_SRC_AON_PROG_WU 0x00000C00 -#define AUX_TIMER_T1CFG_TICK_SRC_AON_SW 0x00000B00 -#define AUX_TIMER_T1CFG_TICK_SRC_OBSMUX1 0x00000A00 -#define AUX_TIMER_T1CFG_TICK_SRC_OBSMUX0 0x00000900 -#define AUX_TIMER_T1CFG_TICK_SRC_RTC_4KHZ 0x00000800 -#define AUX_TIMER_T1CFG_TICK_SRC_ADC_DONE 0x00000700 -#define AUX_TIMER_T1CFG_TICK_SRC_SMPH_AUTOTAKE_DONE 0x00000600 -#define AUX_TIMER_T1CFG_TICK_SRC_TIMER0_EV 0x00000400 -#define AUX_TIMER_T1CFG_TICK_SRC_TDC_DONE 0x00000300 -#define AUX_TIMER_T1CFG_TICK_SRC_AUX_COMPB 0x00000200 -#define AUX_TIMER_T1CFG_TICK_SRC_AUX_COMPA 0x00000100 -#define AUX_TIMER_T1CFG_TICK_SRC_RTC_CH2_EV 0x00000000 +#define AUX_TIMER_T1CFG_TICK_SRC_W 5 +#define AUX_TIMER_T1CFG_TICK_SRC_M 0x00001F00 +#define AUX_TIMER_T1CFG_TICK_SRC_S 8 +#define AUX_TIMER_T1CFG_TICK_SRC_ADC_IRQ 0x00001F00 +#define AUX_TIMER_T1CFG_TICK_SRC_MCU_EVENT 0x00001E00 +#define AUX_TIMER_T1CFG_TICK_SRC_ACLK_REF 0x00001D00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO15 0x00001C00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO14 0x00001B00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO13 0x00001A00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO12 0x00001900 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO11 0x00001800 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO10 0x00001700 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO9 0x00001600 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO8 0x00001500 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO7 0x00001400 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO6 0x00001300 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO5 0x00001200 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO4 0x00001100 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO3 0x00001000 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO2 0x00000F00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO1 0x00000E00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO0 0x00000D00 +#define AUX_TIMER_T1CFG_TICK_SRC_AON_PROG_WU 0x00000C00 +#define AUX_TIMER_T1CFG_TICK_SRC_AON_SW 0x00000B00 +#define AUX_TIMER_T1CFG_TICK_SRC_OBSMUX1 0x00000A00 +#define AUX_TIMER_T1CFG_TICK_SRC_OBSMUX0 0x00000900 +#define AUX_TIMER_T1CFG_TICK_SRC_RTC_4KHZ 0x00000800 +#define AUX_TIMER_T1CFG_TICK_SRC_ADC_DONE 0x00000700 +#define AUX_TIMER_T1CFG_TICK_SRC_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_TIMER_T1CFG_TICK_SRC_TIMER0_EV 0x00000400 +#define AUX_TIMER_T1CFG_TICK_SRC_TDC_DONE 0x00000300 +#define AUX_TIMER_T1CFG_TICK_SRC_AUX_COMPB 0x00000200 +#define AUX_TIMER_T1CFG_TICK_SRC_AUX_COMPA 0x00000100 +#define AUX_TIMER_T1CFG_TICK_SRC_RTC_CH2_EV 0x00000000 // Field: [7:4] PRE // @@ -298,9 +298,9 @@ // 0x2: Divide by 4. // ... // 0xF: Divide by 32,768. -#define AUX_TIMER_T1CFG_PRE_W 4 -#define AUX_TIMER_T1CFG_PRE_M 0x000000F0 -#define AUX_TIMER_T1CFG_PRE_S 4 +#define AUX_TIMER_T1CFG_PRE_W 4 +#define AUX_TIMER_T1CFG_PRE_M 0x000000F0 +#define AUX_TIMER_T1CFG_PRE_S 4 // Field: [1] MODE // @@ -310,12 +310,12 @@ // ENUMs: // TICK Use event set by TICK_SRC as source for prescaler. // CLK Use AUX clock as source for prescaler. -#define AUX_TIMER_T1CFG_MODE 0x00000002 -#define AUX_TIMER_T1CFG_MODE_BITN 1 -#define AUX_TIMER_T1CFG_MODE_M 0x00000002 -#define AUX_TIMER_T1CFG_MODE_S 1 -#define AUX_TIMER_T1CFG_MODE_TICK 0x00000002 -#define AUX_TIMER_T1CFG_MODE_CLK 0x00000000 +#define AUX_TIMER_T1CFG_MODE 0x00000002 +#define AUX_TIMER_T1CFG_MODE_BITN 1 +#define AUX_TIMER_T1CFG_MODE_M 0x00000002 +#define AUX_TIMER_T1CFG_MODE_S 1 +#define AUX_TIMER_T1CFG_MODE_TICK 0x00000002 +#define AUX_TIMER_T1CFG_MODE_CLK 0x00000000 // Field: [0] RELOAD // @@ -332,12 +332,12 @@ // T1CTL.EN becomes 0 when the counter value // becomes equal to or greater than // T1TARGET.VALUE. -#define AUX_TIMER_T1CFG_RELOAD 0x00000001 -#define AUX_TIMER_T1CFG_RELOAD_BITN 0 -#define AUX_TIMER_T1CFG_RELOAD_M 0x00000001 -#define AUX_TIMER_T1CFG_RELOAD_S 0 -#define AUX_TIMER_T1CFG_RELOAD_CONT 0x00000001 -#define AUX_TIMER_T1CFG_RELOAD_MAN 0x00000000 +#define AUX_TIMER_T1CFG_RELOAD 0x00000001 +#define AUX_TIMER_T1CFG_RELOAD_BITN 0 +#define AUX_TIMER_T1CFG_RELOAD_M 0x00000001 +#define AUX_TIMER_T1CFG_RELOAD_S 0 +#define AUX_TIMER_T1CFG_RELOAD_CONT 0x00000001 +#define AUX_TIMER_T1CFG_RELOAD_MAN 0x00000000 //***************************************************************************** // @@ -352,10 +352,10 @@ // 1: Enable Timer 0. // // The counter restarts from 0 when you enable Timer 0. -#define AUX_TIMER_T0CTL_EN 0x00000001 -#define AUX_TIMER_T0CTL_EN_BITN 0 -#define AUX_TIMER_T0CTL_EN_M 0x00000001 -#define AUX_TIMER_T0CTL_EN_S 0 +#define AUX_TIMER_T0CTL_EN 0x00000001 +#define AUX_TIMER_T0CTL_EN_BITN 0 +#define AUX_TIMER_T0CTL_EN_M 0x00000001 +#define AUX_TIMER_T0CTL_EN_S 0 //***************************************************************************** // @@ -387,9 +387,9 @@ // // // It is allowed to update the VALUE while the timer runs. -#define AUX_TIMER_T0TARGET_VALUE_W 16 -#define AUX_TIMER_T0TARGET_VALUE_M 0x0000FFFF -#define AUX_TIMER_T0TARGET_VALUE_S 0 +#define AUX_TIMER_T0TARGET_VALUE_W 16 +#define AUX_TIMER_T0TARGET_VALUE_M 0x0000FFFF +#define AUX_TIMER_T0TARGET_VALUE_S 0 //***************************************************************************** // @@ -421,9 +421,9 @@ // // // It is allowed to update the VALUE while the timer runs. -#define AUX_TIMER_T1TARGET_VALUE_W 8 -#define AUX_TIMER_T1TARGET_VALUE_M 0x000000FF -#define AUX_TIMER_T1TARGET_VALUE_S 0 +#define AUX_TIMER_T1TARGET_VALUE_W 8 +#define AUX_TIMER_T1TARGET_VALUE_M 0x000000FF +#define AUX_TIMER_T1TARGET_VALUE_S 0 //***************************************************************************** // @@ -438,10 +438,9 @@ // 1: Enable Timer 1. // // The counter restarts from 0 when you enable Timer 1. -#define AUX_TIMER_T1CTL_EN 0x00000001 -#define AUX_TIMER_T1CTL_EN_BITN 0 -#define AUX_TIMER_T1CTL_EN_M 0x00000001 -#define AUX_TIMER_T1CTL_EN_S 0 - +#define AUX_TIMER_T1CTL_EN 0x00000001 +#define AUX_TIMER_T1CTL_EN_BITN 0 +#define AUX_TIMER_T1CTL_EN_M 0x00000001 +#define AUX_TIMER_T1CTL_EN_S 0 #endif // __AUX_TIMER__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_wuc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_wuc.h index f7dd3b0..db554b7 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_wuc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_aux_wuc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_wuc_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_wuc_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_WUC_H__ #define __HW_AUX_WUC_H__ @@ -44,61 +44,61 @@ // //***************************************************************************** // Module Clock Enable -#define AUX_WUC_O_MODCLKEN0 0x00000000 +#define AUX_WUC_O_MODCLKEN0 0x00000000 // Power Off Request -#define AUX_WUC_O_PWROFFREQ 0x00000004 +#define AUX_WUC_O_PWROFFREQ 0x00000004 // Power Down Request -#define AUX_WUC_O_PWRDWNREQ 0x00000008 +#define AUX_WUC_O_PWRDWNREQ 0x00000008 // Power Down Acknowledgment -#define AUX_WUC_O_PWRDWNACK 0x0000000C +#define AUX_WUC_O_PWRDWNACK 0x0000000C // Low Frequency Clock Request -#define AUX_WUC_O_CLKLFREQ 0x00000010 +#define AUX_WUC_O_CLKLFREQ 0x00000010 // Low Frequency Clock Acknowledgment -#define AUX_WUC_O_CLKLFACK 0x00000014 +#define AUX_WUC_O_CLKLFACK 0x00000014 // Wake-up Event Flags -#define AUX_WUC_O_WUEVFLAGS 0x00000028 +#define AUX_WUC_O_WUEVFLAGS 0x00000028 // Wake-up Event Clear -#define AUX_WUC_O_WUEVCLR 0x0000002C +#define AUX_WUC_O_WUEVCLR 0x0000002C // ADC Clock Control -#define AUX_WUC_O_ADCCLKCTL 0x00000030 +#define AUX_WUC_O_ADCCLKCTL 0x00000030 // TDC Clock Control -#define AUX_WUC_O_TDCCLKCTL 0x00000034 +#define AUX_WUC_O_TDCCLKCTL 0x00000034 // Reference Clock Control -#define AUX_WUC_O_REFCLKCTL 0x00000038 +#define AUX_WUC_O_REFCLKCTL 0x00000038 // Real Time Counter Sub Second Increment 0 -#define AUX_WUC_O_RTCSUBSECINC0 0x0000003C +#define AUX_WUC_O_RTCSUBSECINC0 0x0000003C // Real Time Counter Sub Second Increment 1 -#define AUX_WUC_O_RTCSUBSECINC1 0x00000040 +#define AUX_WUC_O_RTCSUBSECINC1 0x00000040 // Real Time Counter Sub Second Increment Control -#define AUX_WUC_O_RTCSUBSECINCCTL 0x00000044 +#define AUX_WUC_O_RTCSUBSECINCCTL 0x00000044 // MCU Bus Control -#define AUX_WUC_O_MCUBUSCTL 0x00000048 +#define AUX_WUC_O_MCUBUSCTL 0x00000048 // MCU Bus Status -#define AUX_WUC_O_MCUBUSSTAT 0x0000004C +#define AUX_WUC_O_MCUBUSSTAT 0x0000004C // AON Domain Control Status -#define AUX_WUC_O_AONCTLSTAT 0x00000050 +#define AUX_WUC_O_AONCTLSTAT 0x00000050 // AUX Input Output Latch -#define AUX_WUC_O_AUXIOLATCH 0x00000054 +#define AUX_WUC_O_AUXIOLATCH 0x00000054 // Module Clock Enable 1 -#define AUX_WUC_O_MODCLKEN1 0x0000005C +#define AUX_WUC_O_MODCLKEN1 0x0000005C //***************************************************************************** // @@ -111,12 +111,12 @@ // ENUMs: // EN System CPU has requested clock for AUX_ADI4 // DIS System CPU has not requested clock for AUX_ADI4 -#define AUX_WUC_MODCLKEN0_AUX_ADI4 0x00000080 -#define AUX_WUC_MODCLKEN0_AUX_ADI4_BITN 7 -#define AUX_WUC_MODCLKEN0_AUX_ADI4_M 0x00000080 -#define AUX_WUC_MODCLKEN0_AUX_ADI4_S 7 -#define AUX_WUC_MODCLKEN0_AUX_ADI4_EN 0x00000080 -#define AUX_WUC_MODCLKEN0_AUX_ADI4_DIS 0x00000000 +#define AUX_WUC_MODCLKEN0_AUX_ADI4 0x00000080 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_BITN 7 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_M 0x00000080 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_S 7 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_EN 0x00000080 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_DIS 0x00000000 // Field: [6] AUX_DDI0_OSC // @@ -125,12 +125,12 @@ // EN System CPU has requested clock for AUX_DDI0_OSC // DIS System CPU has not requested clock for // AUX_DDI0_OSC -#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC 0x00000040 -#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_BITN 6 -#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_M 0x00000040 -#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_S 6 -#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_EN 0x00000040 -#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_DIS 0x00000000 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC 0x00000040 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_BITN 6 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_M 0x00000040 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_S 6 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_EN 0x00000040 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_DIS 0x00000000 // Field: [5] TDC // @@ -141,12 +141,12 @@ // ENUMs: // EN System CPU has requested clock for TDC // DIS System CPU has not requested clock for TDC -#define AUX_WUC_MODCLKEN0_TDC 0x00000020 -#define AUX_WUC_MODCLKEN0_TDC_BITN 5 -#define AUX_WUC_MODCLKEN0_TDC_M 0x00000020 -#define AUX_WUC_MODCLKEN0_TDC_S 5 -#define AUX_WUC_MODCLKEN0_TDC_EN 0x00000020 -#define AUX_WUC_MODCLKEN0_TDC_DIS 0x00000000 +#define AUX_WUC_MODCLKEN0_TDC 0x00000020 +#define AUX_WUC_MODCLKEN0_TDC_BITN 5 +#define AUX_WUC_MODCLKEN0_TDC_M 0x00000020 +#define AUX_WUC_MODCLKEN0_TDC_S 5 +#define AUX_WUC_MODCLKEN0_TDC_EN 0x00000020 +#define AUX_WUC_MODCLKEN0_TDC_DIS 0x00000000 // Field: [4] ANAIF // @@ -157,12 +157,12 @@ // ENUMs: // EN System CPU has requested clock for ANAIF // DIS System CPU has not requested clock for ANAIF -#define AUX_WUC_MODCLKEN0_ANAIF 0x00000010 -#define AUX_WUC_MODCLKEN0_ANAIF_BITN 4 -#define AUX_WUC_MODCLKEN0_ANAIF_M 0x00000010 -#define AUX_WUC_MODCLKEN0_ANAIF_S 4 -#define AUX_WUC_MODCLKEN0_ANAIF_EN 0x00000010 -#define AUX_WUC_MODCLKEN0_ANAIF_DIS 0x00000000 +#define AUX_WUC_MODCLKEN0_ANAIF 0x00000010 +#define AUX_WUC_MODCLKEN0_ANAIF_BITN 4 +#define AUX_WUC_MODCLKEN0_ANAIF_M 0x00000010 +#define AUX_WUC_MODCLKEN0_ANAIF_S 4 +#define AUX_WUC_MODCLKEN0_ANAIF_EN 0x00000010 +#define AUX_WUC_MODCLKEN0_ANAIF_DIS 0x00000000 // Field: [3] TIMER // @@ -170,12 +170,12 @@ // ENUMs: // EN System CPU has requested clock for TIMER // DIS System CPU has not requested clock for TIMER -#define AUX_WUC_MODCLKEN0_TIMER 0x00000008 -#define AUX_WUC_MODCLKEN0_TIMER_BITN 3 -#define AUX_WUC_MODCLKEN0_TIMER_M 0x00000008 -#define AUX_WUC_MODCLKEN0_TIMER_S 3 -#define AUX_WUC_MODCLKEN0_TIMER_EN 0x00000008 -#define AUX_WUC_MODCLKEN0_TIMER_DIS 0x00000000 +#define AUX_WUC_MODCLKEN0_TIMER 0x00000008 +#define AUX_WUC_MODCLKEN0_TIMER_BITN 3 +#define AUX_WUC_MODCLKEN0_TIMER_M 0x00000008 +#define AUX_WUC_MODCLKEN0_TIMER_S 3 +#define AUX_WUC_MODCLKEN0_TIMER_EN 0x00000008 +#define AUX_WUC_MODCLKEN0_TIMER_DIS 0x00000000 // Field: [2] AIODIO1 // @@ -183,12 +183,12 @@ // ENUMs: // EN System CPU has requested clock for AIODIO1 // DIS System CPU has not requested clock for AIODIO1 -#define AUX_WUC_MODCLKEN0_AIODIO1 0x00000004 -#define AUX_WUC_MODCLKEN0_AIODIO1_BITN 2 -#define AUX_WUC_MODCLKEN0_AIODIO1_M 0x00000004 -#define AUX_WUC_MODCLKEN0_AIODIO1_S 2 -#define AUX_WUC_MODCLKEN0_AIODIO1_EN 0x00000004 -#define AUX_WUC_MODCLKEN0_AIODIO1_DIS 0x00000000 +#define AUX_WUC_MODCLKEN0_AIODIO1 0x00000004 +#define AUX_WUC_MODCLKEN0_AIODIO1_BITN 2 +#define AUX_WUC_MODCLKEN0_AIODIO1_M 0x00000004 +#define AUX_WUC_MODCLKEN0_AIODIO1_S 2 +#define AUX_WUC_MODCLKEN0_AIODIO1_EN 0x00000004 +#define AUX_WUC_MODCLKEN0_AIODIO1_DIS 0x00000000 // Field: [1] AIODIO0 // @@ -196,12 +196,12 @@ // ENUMs: // EN System CPU has requested clock for AIODIO0 // DIS System CPU has not requested clock for AIODIO0 -#define AUX_WUC_MODCLKEN0_AIODIO0 0x00000002 -#define AUX_WUC_MODCLKEN0_AIODIO0_BITN 1 -#define AUX_WUC_MODCLKEN0_AIODIO0_M 0x00000002 -#define AUX_WUC_MODCLKEN0_AIODIO0_S 1 -#define AUX_WUC_MODCLKEN0_AIODIO0_EN 0x00000002 -#define AUX_WUC_MODCLKEN0_AIODIO0_DIS 0x00000000 +#define AUX_WUC_MODCLKEN0_AIODIO0 0x00000002 +#define AUX_WUC_MODCLKEN0_AIODIO0_BITN 1 +#define AUX_WUC_MODCLKEN0_AIODIO0_M 0x00000002 +#define AUX_WUC_MODCLKEN0_AIODIO0_S 1 +#define AUX_WUC_MODCLKEN0_AIODIO0_EN 0x00000002 +#define AUX_WUC_MODCLKEN0_AIODIO0_DIS 0x00000000 // Field: [0] SMPH // @@ -209,12 +209,12 @@ // ENUMs: // EN System CPU has requested clock for SMPH // DIS System CPU has not requested clock for SMPH -#define AUX_WUC_MODCLKEN0_SMPH 0x00000001 -#define AUX_WUC_MODCLKEN0_SMPH_BITN 0 -#define AUX_WUC_MODCLKEN0_SMPH_M 0x00000001 -#define AUX_WUC_MODCLKEN0_SMPH_S 0 -#define AUX_WUC_MODCLKEN0_SMPH_EN 0x00000001 -#define AUX_WUC_MODCLKEN0_SMPH_DIS 0x00000000 +#define AUX_WUC_MODCLKEN0_SMPH 0x00000001 +#define AUX_WUC_MODCLKEN0_SMPH_BITN 0 +#define AUX_WUC_MODCLKEN0_SMPH_M 0x00000001 +#define AUX_WUC_MODCLKEN0_SMPH_S 0 +#define AUX_WUC_MODCLKEN0_SMPH_EN 0x00000001 +#define AUX_WUC_MODCLKEN0_SMPH_DIS 0x00000000 //***************************************************************************** // @@ -231,10 +231,10 @@ // // The request will only happen if AONCTLSTAT.AUX_FORCE_ON = 0 and // MCUBUSSTAT.DISCONNECTED=1. -#define AUX_WUC_PWROFFREQ_REQ 0x00000001 -#define AUX_WUC_PWROFFREQ_REQ_BITN 0 -#define AUX_WUC_PWROFFREQ_REQ_M 0x00000001 -#define AUX_WUC_PWROFFREQ_REQ_S 0 +#define AUX_WUC_PWROFFREQ_REQ 0x00000001 +#define AUX_WUC_PWROFFREQ_REQ_BITN 0 +#define AUX_WUC_PWROFFREQ_REQ_M 0x00000001 +#define AUX_WUC_PWROFFREQ_REQ_S 0 //***************************************************************************** // @@ -251,10 +251,10 @@ // When REQ is 1 one shall assume that the system is in power down, and that // current supply is limited. When setting REQ = 0, one shall assume that the // system is in power down until PWRDWNACK.ACK = 0 -#define AUX_WUC_PWRDWNREQ_REQ 0x00000001 -#define AUX_WUC_PWRDWNREQ_REQ_BITN 0 -#define AUX_WUC_PWRDWNREQ_REQ_M 0x00000001 -#define AUX_WUC_PWRDWNREQ_REQ_S 0 +#define AUX_WUC_PWRDWNREQ_REQ 0x00000001 +#define AUX_WUC_PWRDWNREQ_REQ_BITN 0 +#define AUX_WUC_PWRDWNREQ_REQ_M 0x00000001 +#define AUX_WUC_PWRDWNREQ_REQ_S 0 //***************************************************************************** // @@ -273,10 +273,10 @@ // The system CPU cannot use this bit since the bus bridge between MCU domain // and AUX domain is always disconnected when this bit is set. For AUX_SCE use // only -#define AUX_WUC_PWRDWNACK_ACK 0x00000001 -#define AUX_WUC_PWRDWNACK_ACK_BITN 0 -#define AUX_WUC_PWRDWNACK_ACK_M 0x00000001 -#define AUX_WUC_PWRDWNACK_ACK_S 0 +#define AUX_WUC_PWRDWNACK_ACK 0x00000001 +#define AUX_WUC_PWRDWNACK_ACK_BITN 0 +#define AUX_WUC_PWRDWNACK_ACK_M 0x00000001 +#define AUX_WUC_PWRDWNACK_ACK_S 0 //***************************************************************************** // @@ -292,10 +292,10 @@ // 1: Request low frequency clock SCLK_LF as the clock source for AUX // // This bit must not be modified unless CLKLFACK.ACK matches the current value -#define AUX_WUC_CLKLFREQ_REQ 0x00000001 -#define AUX_WUC_CLKLFREQ_REQ_BITN 0 -#define AUX_WUC_CLKLFREQ_REQ_M 0x00000001 -#define AUX_WUC_CLKLFREQ_REQ_S 0 +#define AUX_WUC_CLKLFREQ_REQ 0x00000001 +#define AUX_WUC_CLKLFREQ_REQ_BITN 0 +#define AUX_WUC_CLKLFREQ_REQ_M 0x00000001 +#define AUX_WUC_CLKLFREQ_REQ_S 0 //***************************************************************************** // @@ -310,10 +310,10 @@ // the system state // 1: Acknowledgement that the low frequency clock SCLK_LF is the clock source // for AUX -#define AUX_WUC_CLKLFACK_ACK 0x00000001 -#define AUX_WUC_CLKLFACK_ACK_BITN 0 -#define AUX_WUC_CLKLFACK_ACK_M 0x00000001 -#define AUX_WUC_CLKLFACK_ACK_S 0 +#define AUX_WUC_CLKLFACK_ACK 0x00000001 +#define AUX_WUC_CLKLFACK_ACK_BITN 0 +#define AUX_WUC_CLKLFACK_ACK_M 0x00000001 +#define AUX_WUC_CLKLFACK_ACK_S 0 //***************************************************************************** // @@ -327,29 +327,29 @@ // this event is a wake-up event. To make the AON_RTC_CH2 a wake-up event for // the AUX domain configure it as a wake-up event in AON_EVENT:AUXWUSEL.WU0_EV, // AON_EVENT:AUXWUSEL.WU1_EV or AON_EVENT:AUXWUSEL.WU2_EV. -#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2 0x00000004 -#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_BITN 2 -#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_M 0x00000004 -#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_S 2 +#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2 0x00000004 +#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_BITN 2 +#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_M 0x00000004 +#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_S 2 // Field: [1] AON_SW // // Indicates pending event triggered by system CPU writing a 1 to // AON_WUC:AUXCTL.SWEV. -#define AUX_WUC_WUEVFLAGS_AON_SW 0x00000002 -#define AUX_WUC_WUEVFLAGS_AON_SW_BITN 1 -#define AUX_WUC_WUEVFLAGS_AON_SW_M 0x00000002 -#define AUX_WUC_WUEVFLAGS_AON_SW_S 1 +#define AUX_WUC_WUEVFLAGS_AON_SW 0x00000002 +#define AUX_WUC_WUEVFLAGS_AON_SW_BITN 1 +#define AUX_WUC_WUEVFLAGS_AON_SW_M 0x00000002 +#define AUX_WUC_WUEVFLAGS_AON_SW_S 1 // Field: [0] AON_PROG_WU // // Indicates pending event triggered by the sources selected in // AON_EVENT:AUXWUSEL.WU0_EV, AON_EVENT:AUXWUSEL.WU1_EV and // AON_EVENT:AUXWUSEL.WU2_EV. -#define AUX_WUC_WUEVFLAGS_AON_PROG_WU 0x00000001 -#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_BITN 0 -#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_M 0x00000001 -#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_S 0 +#define AUX_WUC_WUEVFLAGS_AON_PROG_WU 0x00000001 +#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_BITN 0 +#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_M 0x00000001 +#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_S 0 //***************************************************************************** // @@ -363,20 +363,20 @@ // WUEVFLAGS.AON_PROG_WU // // This bit must remain set until WUEVFLAGS.AON_RTC_CH2 returns to 0. -#define AUX_WUC_WUEVCLR_AON_RTC_CH2 0x00000004 -#define AUX_WUC_WUEVCLR_AON_RTC_CH2_BITN 2 -#define AUX_WUC_WUEVCLR_AON_RTC_CH2_M 0x00000004 -#define AUX_WUC_WUEVCLR_AON_RTC_CH2_S 2 +#define AUX_WUC_WUEVCLR_AON_RTC_CH2 0x00000004 +#define AUX_WUC_WUEVCLR_AON_RTC_CH2_BITN 2 +#define AUX_WUC_WUEVCLR_AON_RTC_CH2_M 0x00000004 +#define AUX_WUC_WUEVCLR_AON_RTC_CH2_S 2 // Field: [1] AON_SW // // Set to clear the WUEVFLAGS.AON_SW wake-up event. // // This bit must remain set until WUEVFLAGS.AON_SW returns to 0. -#define AUX_WUC_WUEVCLR_AON_SW 0x00000002 -#define AUX_WUC_WUEVCLR_AON_SW_BITN 1 -#define AUX_WUC_WUEVCLR_AON_SW_M 0x00000002 -#define AUX_WUC_WUEVCLR_AON_SW_S 1 +#define AUX_WUC_WUEVCLR_AON_SW 0x00000002 +#define AUX_WUC_WUEVCLR_AON_SW_BITN 1 +#define AUX_WUC_WUEVCLR_AON_SW_M 0x00000002 +#define AUX_WUC_WUEVCLR_AON_SW_S 1 // Field: [0] AON_PROG_WU // @@ -389,10 +389,10 @@ // effect. // // This bit must remain set until WUEVFLAGS.AON_PROG_WU returns to 0. -#define AUX_WUC_WUEVCLR_AON_PROG_WU 0x00000001 -#define AUX_WUC_WUEVCLR_AON_PROG_WU_BITN 0 -#define AUX_WUC_WUEVCLR_AON_PROG_WU_M 0x00000001 -#define AUX_WUC_WUEVCLR_AON_PROG_WU_S 0 +#define AUX_WUC_WUEVCLR_AON_PROG_WU 0x00000001 +#define AUX_WUC_WUEVCLR_AON_PROG_WU_BITN 0 +#define AUX_WUC_WUEVCLR_AON_PROG_WU_M 0x00000001 +#define AUX_WUC_WUEVCLR_AON_PROG_WU_S 0 //***************************************************************************** // @@ -402,20 +402,20 @@ // Field: [1] ACK // // Acknowledges the last value written to REQ. -#define AUX_WUC_ADCCLKCTL_ACK 0x00000002 -#define AUX_WUC_ADCCLKCTL_ACK_BITN 1 -#define AUX_WUC_ADCCLKCTL_ACK_M 0x00000002 -#define AUX_WUC_ADCCLKCTL_ACK_S 1 +#define AUX_WUC_ADCCLKCTL_ACK 0x00000002 +#define AUX_WUC_ADCCLKCTL_ACK_BITN 1 +#define AUX_WUC_ADCCLKCTL_ACK_M 0x00000002 +#define AUX_WUC_ADCCLKCTL_ACK_S 1 // Field: [0] REQ // // Enables(1) or disables (0) the ADC internal clock. // // This bit must not be modified unless ACK matches the current value. -#define AUX_WUC_ADCCLKCTL_REQ 0x00000001 -#define AUX_WUC_ADCCLKCTL_REQ_BITN 0 -#define AUX_WUC_ADCCLKCTL_REQ_M 0x00000001 -#define AUX_WUC_ADCCLKCTL_REQ_S 0 +#define AUX_WUC_ADCCLKCTL_REQ 0x00000001 +#define AUX_WUC_ADCCLKCTL_REQ_BITN 0 +#define AUX_WUC_ADCCLKCTL_REQ_M 0x00000001 +#define AUX_WUC_ADCCLKCTL_REQ_S 0 //***************************************************************************** // @@ -425,20 +425,20 @@ // Field: [1] ACK // // Acknowledges the last value written to REQ. -#define AUX_WUC_TDCCLKCTL_ACK 0x00000002 -#define AUX_WUC_TDCCLKCTL_ACK_BITN 1 -#define AUX_WUC_TDCCLKCTL_ACK_M 0x00000002 -#define AUX_WUC_TDCCLKCTL_ACK_S 1 +#define AUX_WUC_TDCCLKCTL_ACK 0x00000002 +#define AUX_WUC_TDCCLKCTL_ACK_BITN 1 +#define AUX_WUC_TDCCLKCTL_ACK_M 0x00000002 +#define AUX_WUC_TDCCLKCTL_ACK_S 1 // Field: [0] REQ // // Enables(1) or disables (0) the TDC counter clock source. // // This bit must not be modified unless ACK matches the current value. -#define AUX_WUC_TDCCLKCTL_REQ 0x00000001 -#define AUX_WUC_TDCCLKCTL_REQ_BITN 0 -#define AUX_WUC_TDCCLKCTL_REQ_M 0x00000001 -#define AUX_WUC_TDCCLKCTL_REQ_S 0 +#define AUX_WUC_TDCCLKCTL_REQ 0x00000001 +#define AUX_WUC_TDCCLKCTL_REQ_BITN 0 +#define AUX_WUC_TDCCLKCTL_REQ_M 0x00000001 +#define AUX_WUC_TDCCLKCTL_REQ_S 0 //***************************************************************************** // @@ -448,20 +448,20 @@ // Field: [1] ACK // // Acknowledges the last value written to REQ. -#define AUX_WUC_REFCLKCTL_ACK 0x00000002 -#define AUX_WUC_REFCLKCTL_ACK_BITN 1 -#define AUX_WUC_REFCLKCTL_ACK_M 0x00000002 -#define AUX_WUC_REFCLKCTL_ACK_S 1 +#define AUX_WUC_REFCLKCTL_ACK 0x00000002 +#define AUX_WUC_REFCLKCTL_ACK_BITN 1 +#define AUX_WUC_REFCLKCTL_ACK_M 0x00000002 +#define AUX_WUC_REFCLKCTL_ACK_S 1 // Field: [0] REQ // // Enables(1) or disables (0) the TDC reference clock source. // // This bit must not be modified unless ACK matches the current value. -#define AUX_WUC_REFCLKCTL_REQ 0x00000001 -#define AUX_WUC_REFCLKCTL_REQ_BITN 0 -#define AUX_WUC_REFCLKCTL_REQ_M 0x00000001 -#define AUX_WUC_REFCLKCTL_REQ_S 0 +#define AUX_WUC_REFCLKCTL_REQ 0x00000001 +#define AUX_WUC_REFCLKCTL_REQ_BITN 0 +#define AUX_WUC_REFCLKCTL_REQ_M 0x00000001 +#define AUX_WUC_REFCLKCTL_REQ_S 0 //***************************************************************************** // @@ -471,9 +471,9 @@ // Field: [15:0] INC15_0 // // Bits 15:0 of the RTC sub-second increment value. -#define AUX_WUC_RTCSUBSECINC0_INC15_0_W 16 -#define AUX_WUC_RTCSUBSECINC0_INC15_0_M 0x0000FFFF -#define AUX_WUC_RTCSUBSECINC0_INC15_0_S 0 +#define AUX_WUC_RTCSUBSECINC0_INC15_0_W 16 +#define AUX_WUC_RTCSUBSECINC0_INC15_0_M 0x0000FFFF +#define AUX_WUC_RTCSUBSECINC0_INC15_0_S 0 //***************************************************************************** // @@ -483,9 +483,9 @@ // Field: [7:0] INC23_16 // // Bits 23:16 of the RTC sub-second increment value. -#define AUX_WUC_RTCSUBSECINC1_INC23_16_W 8 -#define AUX_WUC_RTCSUBSECINC1_INC23_16_M 0x000000FF -#define AUX_WUC_RTCSUBSECINC1_INC23_16_S 0 +#define AUX_WUC_RTCSUBSECINC1_INC23_16_W 8 +#define AUX_WUC_RTCSUBSECINC1_INC23_16_M 0x000000FF +#define AUX_WUC_RTCSUBSECINC1_INC23_16_S 0 //***************************************************************************** // @@ -495,10 +495,10 @@ // Field: [1] UPD_ACK // // Acknowledgment of the UPD_REQ. -#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK 0x00000002 -#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_BITN 1 -#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_M 0x00000002 -#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_S 1 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK 0x00000002 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_BITN 1 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_M 0x00000002 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_S 1 // Field: [0] UPD_REQ // @@ -508,10 +508,10 @@ // 1: New sub second increment is available // // This bit must not be modified unless UPD_ACK matches the current value. -#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ 0x00000001 -#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_BITN 0 -#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_M 0x00000001 -#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_S 0 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ 0x00000001 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_BITN 0 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_M 0x00000001 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_S 0 //***************************************************************************** // @@ -529,10 +529,10 @@ // It is recommended that this bit is set and remains set after initial // power-up, and that the system CPU uses AON_WUC:AUX_CTL.AUX_FORCE_ON to // connect/disconnect the bus. -#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ 0x00000001 -#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_BITN 0 -#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_M 0x00000001 -#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_S 0 +#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ 0x00000001 +#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_BITN 0 +#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_M 0x00000001 +#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_S 0 //***************************************************************************** // @@ -543,10 +543,10 @@ // // Indicates whether the AUX domain and MCU domain buses are currently // disconnected (1) or connected (0). -#define AUX_WUC_MCUBUSSTAT_DISCONNECTED 0x00000002 -#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_BITN 1 -#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_M 0x00000002 -#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_S 1 +#define AUX_WUC_MCUBUSSTAT_DISCONNECTED 0x00000002 +#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_BITN 1 +#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_M 0x00000002 +#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_S 1 // Field: [0] DISCONNECT_ACK // @@ -555,10 +555,10 @@ // // Note that if AON_WUC:AUXCTL.AUX_FORCE_ON = 1 a reconnect to the MCU domain // bus will be made regardless of the state of MCUBUSCTL.DISCONNECT_REQ -#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK 0x00000001 -#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_BITN 0 -#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_M 0x00000001 -#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_S 0 +#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK 0x00000001 +#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_BITN 0 +#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_M 0x00000001 +#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_S 0 //***************************************************************************** // @@ -568,18 +568,18 @@ // Field: [1] AUX_FORCE_ON // // Status of AON_WUC:AUX_CTL.AUX_FORCE_ON. -#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON 0x00000002 -#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_BITN 1 -#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_M 0x00000002 -#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_S 1 +#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON 0x00000002 +#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_BITN 1 +#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_M 0x00000002 +#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_S 1 // Field: [0] SCE_RUN_EN // // Status of AON_WUC:AUX_CTL.SCE_RUN_EN. -#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN 0x00000001 -#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_BITN 0 -#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_M 0x00000001 -#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_S 0 +#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN 0x00000001 +#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_BITN 0 +#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_M 0x00000001 +#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_S 0 //***************************************************************************** // @@ -598,12 +598,12 @@ // ENUMs: // TRANSP Latches are transparent ( open ) // STATIC Latches are static ( closed ) -#define AUX_WUC_AUXIOLATCH_EN 0x00000001 -#define AUX_WUC_AUXIOLATCH_EN_BITN 0 -#define AUX_WUC_AUXIOLATCH_EN_M 0x00000001 -#define AUX_WUC_AUXIOLATCH_EN_S 0 -#define AUX_WUC_AUXIOLATCH_EN_TRANSP 0x00000001 -#define AUX_WUC_AUXIOLATCH_EN_STATIC 0x00000000 +#define AUX_WUC_AUXIOLATCH_EN 0x00000001 +#define AUX_WUC_AUXIOLATCH_EN_BITN 0 +#define AUX_WUC_AUXIOLATCH_EN_M 0x00000001 +#define AUX_WUC_AUXIOLATCH_EN_S 0 +#define AUX_WUC_AUXIOLATCH_EN_TRANSP 0x00000001 +#define AUX_WUC_AUXIOLATCH_EN_STATIC 0x00000000 //***************************************************************************** // @@ -616,12 +616,12 @@ // ENUMs: // EN AUX_SCE has requested clock for AUX_ADI4 // DIS AUX_SCE has not requested clock for AUX_ADI4 -#define AUX_WUC_MODCLKEN1_AUX_ADI4 0x00000080 -#define AUX_WUC_MODCLKEN1_AUX_ADI4_BITN 7 -#define AUX_WUC_MODCLKEN1_AUX_ADI4_M 0x00000080 -#define AUX_WUC_MODCLKEN1_AUX_ADI4_S 7 -#define AUX_WUC_MODCLKEN1_AUX_ADI4_EN 0x00000080 -#define AUX_WUC_MODCLKEN1_AUX_ADI4_DIS 0x00000000 +#define AUX_WUC_MODCLKEN1_AUX_ADI4 0x00000080 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_BITN 7 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_M 0x00000080 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_S 7 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_EN 0x00000080 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_DIS 0x00000000 // Field: [6] AUX_DDI0_OSC // @@ -629,12 +629,12 @@ // ENUMs: // EN AUX_SCE has requested clock for AUX_DDI0_OSC // DIS AUX_SCE has not requested clock for AUX_DDI0_OSC -#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC 0x00000040 -#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_BITN 6 -#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_M 0x00000040 -#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_S 6 -#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_EN 0x00000040 -#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_DIS 0x00000000 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC 0x00000040 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_BITN 6 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_M 0x00000040 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_S 6 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_EN 0x00000040 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_DIS 0x00000000 // Field: [4] ANAIF // @@ -642,12 +642,12 @@ // ENUMs: // EN AUX_SCE has requested clock for ANAIF // DIS AUX_SCE has not requested clock for ANAIF -#define AUX_WUC_MODCLKEN1_ANAIF 0x00000010 -#define AUX_WUC_MODCLKEN1_ANAIF_BITN 4 -#define AUX_WUC_MODCLKEN1_ANAIF_M 0x00000010 -#define AUX_WUC_MODCLKEN1_ANAIF_S 4 -#define AUX_WUC_MODCLKEN1_ANAIF_EN 0x00000010 -#define AUX_WUC_MODCLKEN1_ANAIF_DIS 0x00000000 +#define AUX_WUC_MODCLKEN1_ANAIF 0x00000010 +#define AUX_WUC_MODCLKEN1_ANAIF_BITN 4 +#define AUX_WUC_MODCLKEN1_ANAIF_M 0x00000010 +#define AUX_WUC_MODCLKEN1_ANAIF_S 4 +#define AUX_WUC_MODCLKEN1_ANAIF_EN 0x00000010 +#define AUX_WUC_MODCLKEN1_ANAIF_DIS 0x00000000 // Field: [3] TIMER // @@ -655,12 +655,12 @@ // ENUMs: // EN AUX_SCE has requested clock for TIMER // DIS AUX_SCE has not requested clock for TIMER -#define AUX_WUC_MODCLKEN1_TIMER 0x00000008 -#define AUX_WUC_MODCLKEN1_TIMER_BITN 3 -#define AUX_WUC_MODCLKEN1_TIMER_M 0x00000008 -#define AUX_WUC_MODCLKEN1_TIMER_S 3 -#define AUX_WUC_MODCLKEN1_TIMER_EN 0x00000008 -#define AUX_WUC_MODCLKEN1_TIMER_DIS 0x00000000 +#define AUX_WUC_MODCLKEN1_TIMER 0x00000008 +#define AUX_WUC_MODCLKEN1_TIMER_BITN 3 +#define AUX_WUC_MODCLKEN1_TIMER_M 0x00000008 +#define AUX_WUC_MODCLKEN1_TIMER_S 3 +#define AUX_WUC_MODCLKEN1_TIMER_EN 0x00000008 +#define AUX_WUC_MODCLKEN1_TIMER_DIS 0x00000000 // Field: [2] AIODIO1 // @@ -668,12 +668,12 @@ // ENUMs: // EN AUX_SCE has requested clock for AIODIO1 // DIS AUX_SCE has not requested clock for AIODIO1 -#define AUX_WUC_MODCLKEN1_AIODIO1 0x00000004 -#define AUX_WUC_MODCLKEN1_AIODIO1_BITN 2 -#define AUX_WUC_MODCLKEN1_AIODIO1_M 0x00000004 -#define AUX_WUC_MODCLKEN1_AIODIO1_S 2 -#define AUX_WUC_MODCLKEN1_AIODIO1_EN 0x00000004 -#define AUX_WUC_MODCLKEN1_AIODIO1_DIS 0x00000000 +#define AUX_WUC_MODCLKEN1_AIODIO1 0x00000004 +#define AUX_WUC_MODCLKEN1_AIODIO1_BITN 2 +#define AUX_WUC_MODCLKEN1_AIODIO1_M 0x00000004 +#define AUX_WUC_MODCLKEN1_AIODIO1_S 2 +#define AUX_WUC_MODCLKEN1_AIODIO1_EN 0x00000004 +#define AUX_WUC_MODCLKEN1_AIODIO1_DIS 0x00000000 // Field: [1] AIODIO0 // @@ -681,12 +681,12 @@ // ENUMs: // EN AUX_SCE has requested clock for AIODIO0 // DIS AUX_SCE has not requested clock for AIODIO0 -#define AUX_WUC_MODCLKEN1_AIODIO0 0x00000002 -#define AUX_WUC_MODCLKEN1_AIODIO0_BITN 1 -#define AUX_WUC_MODCLKEN1_AIODIO0_M 0x00000002 -#define AUX_WUC_MODCLKEN1_AIODIO0_S 1 -#define AUX_WUC_MODCLKEN1_AIODIO0_EN 0x00000002 -#define AUX_WUC_MODCLKEN1_AIODIO0_DIS 0x00000000 +#define AUX_WUC_MODCLKEN1_AIODIO0 0x00000002 +#define AUX_WUC_MODCLKEN1_AIODIO0_BITN 1 +#define AUX_WUC_MODCLKEN1_AIODIO0_M 0x00000002 +#define AUX_WUC_MODCLKEN1_AIODIO0_S 1 +#define AUX_WUC_MODCLKEN1_AIODIO0_EN 0x00000002 +#define AUX_WUC_MODCLKEN1_AIODIO0_DIS 0x00000000 // Field: [0] SMPH // @@ -694,12 +694,11 @@ // ENUMs: // EN AUX_SCE has requested clock for SMPH // DIS AUX_SCE has not requested clock for SMPH -#define AUX_WUC_MODCLKEN1_SMPH 0x00000001 -#define AUX_WUC_MODCLKEN1_SMPH_BITN 0 -#define AUX_WUC_MODCLKEN1_SMPH_M 0x00000001 -#define AUX_WUC_MODCLKEN1_SMPH_S 0 -#define AUX_WUC_MODCLKEN1_SMPH_EN 0x00000001 -#define AUX_WUC_MODCLKEN1_SMPH_DIS 0x00000000 - +#define AUX_WUC_MODCLKEN1_SMPH 0x00000001 +#define AUX_WUC_MODCLKEN1_SMPH_BITN 0 +#define AUX_WUC_MODCLKEN1_SMPH_M 0x00000001 +#define AUX_WUC_MODCLKEN1_SMPH_S 0 +#define AUX_WUC_MODCLKEN1_SMPH_EN 0x00000001 +#define AUX_WUC_MODCLKEN1_SMPH_DIS 0x00000000 #endif // __AUX_WUC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ccfg.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ccfg.h index 31b9b2a..4542dc1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ccfg.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ccfg.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_ccfg_h -* Revised: 2017-02-06 19:32:22 +0100 (Mon, 06 Feb 2017) -* Revision: 48408 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_ccfg_h + * Revised: 2017-02-06 19:32:22 +0100 (Mon, 06 Feb 2017) + * Revision: 48408 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CCFG_H__ #define __HW_CCFG_H__ @@ -44,70 +44,70 @@ // //***************************************************************************** // Extern LF clock configuration -#define CCFG_O_EXT_LF_CLK 0x00000FA8 +#define CCFG_O_EXT_LF_CLK 0x00000FA8 // Mode Configuration 1 -#define CCFG_O_MODE_CONF_1 0x00000FAC +#define CCFG_O_MODE_CONF_1 0x00000FAC // CCFG Size and Disable Flags -#define CCFG_O_SIZE_AND_DIS_FLAGS 0x00000FB0 +#define CCFG_O_SIZE_AND_DIS_FLAGS 0x00000FB0 // Mode Configuration 0 -#define CCFG_O_MODE_CONF 0x00000FB4 +#define CCFG_O_MODE_CONF 0x00000FB4 // Voltage Load 0 -#define CCFG_O_VOLT_LOAD_0 0x00000FB8 +#define CCFG_O_VOLT_LOAD_0 0x00000FB8 // Voltage Load 1 -#define CCFG_O_VOLT_LOAD_1 0x00000FBC +#define CCFG_O_VOLT_LOAD_1 0x00000FBC // Real Time Clock Offset -#define CCFG_O_RTC_OFFSET 0x00000FC0 +#define CCFG_O_RTC_OFFSET 0x00000FC0 // Frequency Offset -#define CCFG_O_FREQ_OFFSET 0x00000FC4 +#define CCFG_O_FREQ_OFFSET 0x00000FC4 // IEEE MAC Address 0 -#define CCFG_O_IEEE_MAC_0 0x00000FC8 +#define CCFG_O_IEEE_MAC_0 0x00000FC8 // IEEE MAC Address 1 -#define CCFG_O_IEEE_MAC_1 0x00000FCC +#define CCFG_O_IEEE_MAC_1 0x00000FCC // IEEE BLE Address 0 -#define CCFG_O_IEEE_BLE_0 0x00000FD0 +#define CCFG_O_IEEE_BLE_0 0x00000FD0 // IEEE BLE Address 1 -#define CCFG_O_IEEE_BLE_1 0x00000FD4 +#define CCFG_O_IEEE_BLE_1 0x00000FD4 // Bootloader Configuration -#define CCFG_O_BL_CONFIG 0x00000FD8 +#define CCFG_O_BL_CONFIG 0x00000FD8 // Erase Configuration -#define CCFG_O_ERASE_CONF 0x00000FDC +#define CCFG_O_ERASE_CONF 0x00000FDC // TI Options -#define CCFG_O_CCFG_TI_OPTIONS 0x00000FE0 +#define CCFG_O_CCFG_TI_OPTIONS 0x00000FE0 // Test Access Points Enable 0 -#define CCFG_O_CCFG_TAP_DAP_0 0x00000FE4 +#define CCFG_O_CCFG_TAP_DAP_0 0x00000FE4 // Test Access Points Enable 1 -#define CCFG_O_CCFG_TAP_DAP_1 0x00000FE8 +#define CCFG_O_CCFG_TAP_DAP_1 0x00000FE8 // Image Valid -#define CCFG_O_IMAGE_VALID_CONF 0x00000FEC +#define CCFG_O_IMAGE_VALID_CONF 0x00000FEC // Protect Sectors 0-31 -#define CCFG_O_CCFG_PROT_31_0 0x00000FF0 +#define CCFG_O_CCFG_PROT_31_0 0x00000FF0 // Protect Sectors 32-63 -#define CCFG_O_CCFG_PROT_63_32 0x00000FF4 +#define CCFG_O_CCFG_PROT_63_32 0x00000FF4 // Protect Sectors 64-95 -#define CCFG_O_CCFG_PROT_95_64 0x00000FF8 +#define CCFG_O_CCFG_PROT_95_64 0x00000FF8 // Protect Sectors 96-127 -#define CCFG_O_CCFG_PROT_127_96 0x00000FFC +#define CCFG_O_CCFG_PROT_127_96 0x00000FFC //***************************************************************************** // @@ -120,9 +120,9 @@ // SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL. The selected DIO // will be marked as reserved by the pin driver (TI-RTOS environment) and hence // not selectable for other usage. -#define CCFG_EXT_LF_CLK_DIO_W 8 -#define CCFG_EXT_LF_CLK_DIO_M 0xFF000000 -#define CCFG_EXT_LF_CLK_DIO_S 24 +#define CCFG_EXT_LF_CLK_DIO_W 8 +#define CCFG_EXT_LF_CLK_DIO_M 0xFF000000 +#define CCFG_EXT_LF_CLK_DIO_S 24 // Field: [23:0] RTC_INCREMENT // @@ -130,9 +130,9 @@ // written to AON_RTC:SUBSECINC.VALUEINC. Defined as follows: // EXT_LF_CLK.RTC_INCREMENT = 2^38/InputClockFrequency in Hertz (e.g.: // RTC_INCREMENT=0x800000 for InputClockFrequency=32768 Hz) -#define CCFG_EXT_LF_CLK_RTC_INCREMENT_W 24 -#define CCFG_EXT_LF_CLK_RTC_INCREMENT_M 0x00FFFFFF -#define CCFG_EXT_LF_CLK_RTC_INCREMENT_S 0 +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_W 24 +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_M 0x00FFFFFF +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_S 0 //***************************************************************************** // @@ -153,9 +153,9 @@ // NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must // be called regularly to apply this field (handled automatically if using TI // RTOS!). -#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_W 4 -#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M 0x00F00000 -#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S 20 +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_W 4 +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M 0x00F00000 +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S 20 // Field: [19] ALT_DCDC_DITHER_EN // @@ -163,10 +163,10 @@ // (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). // 0: Dither disable // 1: Dither enable -#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x00080000 -#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_BITN 19 -#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M 0x00080000 -#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S 19 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x00080000 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_BITN 19 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M 0x00080000 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S 19 // Field: [18:16] ALT_DCDC_IPEAK // @@ -179,35 +179,35 @@ // 4: 47mA // ... // 7: 59mA (max) -#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_W 3 -#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M 0x00070000 -#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S 16 +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_W 3 +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M 0x00070000 +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S 16 // Field: [15:12] DELTA_IBIAS_INIT // // Signed delta value for IBIAS_INIT. Delta value only applies if // SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. // See FCFG1:AMPCOMP_CTRL1.IBIAS_INIT -#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W 4 -#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M 0x0000F000 -#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S 12 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W 4 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M 0x0000F000 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S 12 // Field: [11:8] DELTA_IBIAS_OFFSET // // Signed delta value for IBIAS_OFFSET. Delta value only applies if // SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. // See FCFG1:AMPCOMP_CTRL1.IBIAS_OFFSET -#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W 4 -#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M 0x00000F00 -#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S 8 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W 4 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M 0x00000F00 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S 8 // Field: [7:0] XOSC_MAX_START // // Unsigned value of maximum XOSC startup time (worst case) in units of 100us. // Value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. -#define CCFG_MODE_CONF_1_XOSC_MAX_START_W 8 -#define CCFG_MODE_CONF_1_XOSC_MAX_START_M 0x000000FF -#define CCFG_MODE_CONF_1_XOSC_MAX_START_S 0 +#define CCFG_MODE_CONF_1_XOSC_MAX_START_W 8 +#define CCFG_MODE_CONF_1_XOSC_MAX_START_M 0x000000FF +#define CCFG_MODE_CONF_1_XOSC_MAX_START_S 0 //***************************************************************************** // @@ -217,18 +217,18 @@ // Field: [31:16] SIZE_OF_CCFG // // Total size of CCFG in bytes. -#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_W 16 -#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M 0xFFFF0000 -#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S 16 +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_W 16 +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M 0xFFFF0000 +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S 16 // Field: [15:4] DISABLE_FLAGS // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_W 12 -#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M 0x0000FFF0 -#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S 4 +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_W 12 +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M 0x0000FFF0 +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S 4 // Field: [3] DIS_TCXO // @@ -237,10 +237,10 @@ // 1: TCXO functionality disabled. // Note: // An external TCXO is required if DIS_TCXO = 0. -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x00000008 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_BITN 3 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M 0x00000008 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S 3 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x00000008 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_BITN 3 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M 0x00000008 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S 3 // Field: [2] DIS_GPRAM // @@ -253,10 +253,10 @@ // enabled. // See: // VIMS:CTL.MODE -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x00000004 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_BITN 2 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M 0x00000004 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S 2 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x00000004 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_BITN 2 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M 0x00000004 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S 2 // Field: [1] DIS_ALT_DCDC_SETTING // @@ -271,10 +271,10 @@ // NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must // be called regularly to apply this field (handled automatically if using TI // RTOS!). -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x00000002 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_BITN 1 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M 0x00000002 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S 1 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x00000002 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_BITN 1 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M 0x00000002 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S 1 // Field: [0] DIS_XOSC_OVR // @@ -285,10 +285,10 @@ // MODE_CONF_1.DELTA_IBIAS_INIT // MODE_CONF_1.DELTA_IBIAS_OFFSET // MODE_CONF_1.XOSC_MAX_START -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x00000001 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_BITN 0 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M 0x00000001 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S 0 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x00000001 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_BITN 0 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M 0x00000001 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S 0 //***************************************************************************** // @@ -305,9 +305,9 @@ // 0x0 (0) : Delta = +1 // ... // 0x7 (7) : Delta = +8 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W 4 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M 0xF0000000 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S 28 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W 4 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M 0xF0000000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S 28 // Field: [27] DCDC_RECHARGE // @@ -318,10 +318,10 @@ // NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must // be called regularly to apply this field (handled automatically if using TI // RTOS!). -#define CCFG_MODE_CONF_DCDC_RECHARGE 0x08000000 -#define CCFG_MODE_CONF_DCDC_RECHARGE_BITN 27 -#define CCFG_MODE_CONF_DCDC_RECHARGE_M 0x08000000 -#define CCFG_MODE_CONF_DCDC_RECHARGE_S 27 +#define CCFG_MODE_CONF_DCDC_RECHARGE 0x08000000 +#define CCFG_MODE_CONF_DCDC_RECHARGE_BITN 27 +#define CCFG_MODE_CONF_DCDC_RECHARGE_M 0x08000000 +#define CCFG_MODE_CONF_DCDC_RECHARGE_S 27 // Field: [26] DCDC_ACTIVE // @@ -332,20 +332,20 @@ // NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must // be called regularly to apply this field (handled automatically if using TI // RTOS!). -#define CCFG_MODE_CONF_DCDC_ACTIVE 0x04000000 -#define CCFG_MODE_CONF_DCDC_ACTIVE_BITN 26 -#define CCFG_MODE_CONF_DCDC_ACTIVE_M 0x04000000 -#define CCFG_MODE_CONF_DCDC_ACTIVE_S 26 +#define CCFG_MODE_CONF_DCDC_ACTIVE 0x04000000 +#define CCFG_MODE_CONF_DCDC_ACTIVE_BITN 26 +#define CCFG_MODE_CONF_DCDC_ACTIVE_M 0x04000000 +#define CCFG_MODE_CONF_DCDC_ACTIVE_S 26 // Field: [25] VDDR_EXT_LOAD // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_MODE_CONF_VDDR_EXT_LOAD 0x02000000 -#define CCFG_MODE_CONF_VDDR_EXT_LOAD_BITN 25 -#define CCFG_MODE_CONF_VDDR_EXT_LOAD_M 0x02000000 -#define CCFG_MODE_CONF_VDDR_EXT_LOAD_S 25 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD 0x02000000 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_BITN 25 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_M 0x02000000 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_S 25 // Field: [24] VDDS_BOD_LEVEL // @@ -353,10 +353,10 @@ // 0: VDDS BOD level is 2.0 V (necessary for maximum PA output power on // CC13x0). // 1: VDDS BOD level is 1.8 V (or 1.7 V for external regulator mode) (default). -#define CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x01000000 -#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_BITN 24 -#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_M 0x01000000 -#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_S 24 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x01000000 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_BITN 24 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_M 0x01000000 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_S 24 // Field: [23:22] SCLK_LF_OPTION // @@ -378,13 +378,13 @@ // trimDevice() xxWare boot function). Standby // power mode is not supported when using this // clock source. -#define CCFG_MODE_CONF_SCLK_LF_OPTION_W 2 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_M 0x00C00000 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_S 22 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF 0x00C00000 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF 0x00800000 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF 0x00400000 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF 0x00000000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_W 2 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_M 0x00C00000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_S 22 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF 0x00C00000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF 0x00800000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF 0x00400000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF 0x00000000 // Field: [21] VDDR_TRIM_SLEEP_TC // @@ -398,20 +398,20 @@ // Delta = max (delta, min(8, floor(62-temp)/8)) // Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is the current // temperature in degrees C. -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x00200000 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_BITN 21 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M 0x00200000 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S 21 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x00200000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_BITN 21 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M 0x00200000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S 21 // Field: [20] RTC_COMP // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_MODE_CONF_RTC_COMP 0x00100000 -#define CCFG_MODE_CONF_RTC_COMP_BITN 20 -#define CCFG_MODE_CONF_RTC_COMP_M 0x00100000 -#define CCFG_MODE_CONF_RTC_COMP_S 20 +#define CCFG_MODE_CONF_RTC_COMP 0x00100000 +#define CCFG_MODE_CONF_RTC_COMP_BITN 20 +#define CCFG_MODE_CONF_RTC_COMP_M 0x00100000 +#define CCFG_MODE_CONF_RTC_COMP_S 20 // Field: [19:18] XOSC_FREQ // @@ -422,12 +422,12 @@ // 24M 24 MHz XOSC_HF // 48M 48 MHz XOSC_HF // HPOSC HPOSC -#define CCFG_MODE_CONF_XOSC_FREQ_W 2 -#define CCFG_MODE_CONF_XOSC_FREQ_M 0x000C0000 -#define CCFG_MODE_CONF_XOSC_FREQ_S 18 -#define CCFG_MODE_CONF_XOSC_FREQ_24M 0x000C0000 -#define CCFG_MODE_CONF_XOSC_FREQ_48M 0x00080000 -#define CCFG_MODE_CONF_XOSC_FREQ_HPOSC 0x00040000 +#define CCFG_MODE_CONF_XOSC_FREQ_W 2 +#define CCFG_MODE_CONF_XOSC_FREQ_M 0x000C0000 +#define CCFG_MODE_CONF_XOSC_FREQ_S 18 +#define CCFG_MODE_CONF_XOSC_FREQ_24M 0x000C0000 +#define CCFG_MODE_CONF_XOSC_FREQ_48M 0x00080000 +#define CCFG_MODE_CONF_XOSC_FREQ_HPOSC 0x00040000 // Field: [17] XOSC_CAP_MOD // @@ -435,28 +435,28 @@ // XOSC_CAPARRAY_DELTA. // 0: Apply cap-array delta // 1: Do not apply cap-array delta (default) -#define CCFG_MODE_CONF_XOSC_CAP_MOD 0x00020000 -#define CCFG_MODE_CONF_XOSC_CAP_MOD_BITN 17 -#define CCFG_MODE_CONF_XOSC_CAP_MOD_M 0x00020000 -#define CCFG_MODE_CONF_XOSC_CAP_MOD_S 17 +#define CCFG_MODE_CONF_XOSC_CAP_MOD 0x00020000 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_BITN 17 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_M 0x00020000 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_S 17 // Field: [16] HF_COMP // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_MODE_CONF_HF_COMP 0x00010000 -#define CCFG_MODE_CONF_HF_COMP_BITN 16 -#define CCFG_MODE_CONF_HF_COMP_M 0x00010000 -#define CCFG_MODE_CONF_HF_COMP_S 16 +#define CCFG_MODE_CONF_HF_COMP 0x00010000 +#define CCFG_MODE_CONF_HF_COMP_BITN 16 +#define CCFG_MODE_CONF_HF_COMP_M 0x00010000 +#define CCFG_MODE_CONF_HF_COMP_S 16 // Field: [15:8] XOSC_CAPARRAY_DELTA // // Signed 8-bit value, directly modifying trimmed XOSC cap-array step value. // Enabled by XOSC_CAP_MOD. -#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W 8 -#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M 0x0000FF00 -#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S 8 +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W 8 +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M 0x0000FF00 +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S 8 // Field: [7:0] VDDR_CAP // @@ -469,9 +469,9 @@ // NOTE! If using the following functions this field must be configured (used // by TI RTOS): // SysCtrlSetRechargeBeforePowerDown() SysCtrlAdjustRechargeAfterPowerDown() -#define CCFG_MODE_CONF_VDDR_CAP_W 8 -#define CCFG_MODE_CONF_VDDR_CAP_M 0x000000FF -#define CCFG_MODE_CONF_VDDR_CAP_S 0 +#define CCFG_MODE_CONF_VDDR_CAP_W 8 +#define CCFG_MODE_CONF_VDDR_CAP_M 0x000000FF +#define CCFG_MODE_CONF_VDDR_CAP_S 0 //***************************************************************************** // @@ -483,36 +483,36 @@ // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_W 8 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M 0xFF000000 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S 24 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M 0xFF000000 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S 24 // Field: [23:16] VDDR_EXT_TP25 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_W 8 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M 0x00FF0000 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S 16 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M 0x00FF0000 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S 16 // Field: [15:8] VDDR_EXT_TP5 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_W 8 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M 0x0000FF00 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M 0x0000FF00 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S 8 // Field: [7:0] VDDR_EXT_TM15 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_W 8 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M 0x000000FF -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S 0 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M 0x000000FF +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S 0 //***************************************************************************** // @@ -524,36 +524,36 @@ // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_W 8 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M 0xFF000000 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S 24 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M 0xFF000000 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S 24 // Field: [23:16] VDDR_EXT_TP105 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_W 8 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M 0x00FF0000 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S 16 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M 0x00FF0000 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S 16 // Field: [15:8] VDDR_EXT_TP85 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_W 8 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M 0x0000FF00 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M 0x0000FF00 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S 8 // Field: [7:0] VDDR_EXT_TP65 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_W 8 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M 0x000000FF -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S 0 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M 0x000000FF +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S 0 //***************************************************************************** // @@ -565,27 +565,27 @@ // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_RTC_OFFSET_RTC_COMP_P0_W 16 -#define CCFG_RTC_OFFSET_RTC_COMP_P0_M 0xFFFF0000 -#define CCFG_RTC_OFFSET_RTC_COMP_P0_S 16 +#define CCFG_RTC_OFFSET_RTC_COMP_P0_W 16 +#define CCFG_RTC_OFFSET_RTC_COMP_P0_M 0xFFFF0000 +#define CCFG_RTC_OFFSET_RTC_COMP_P0_S 16 // Field: [15:8] RTC_COMP_P1 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_RTC_OFFSET_RTC_COMP_P1_W 8 -#define CCFG_RTC_OFFSET_RTC_COMP_P1_M 0x0000FF00 -#define CCFG_RTC_OFFSET_RTC_COMP_P1_S 8 +#define CCFG_RTC_OFFSET_RTC_COMP_P1_W 8 +#define CCFG_RTC_OFFSET_RTC_COMP_P1_M 0x0000FF00 +#define CCFG_RTC_OFFSET_RTC_COMP_P1_S 8 // Field: [7:0] RTC_COMP_P2 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_RTC_OFFSET_RTC_COMP_P2_W 8 -#define CCFG_RTC_OFFSET_RTC_COMP_P2_M 0x000000FF -#define CCFG_RTC_OFFSET_RTC_COMP_P2_S 0 +#define CCFG_RTC_OFFSET_RTC_COMP_P2_W 8 +#define CCFG_RTC_OFFSET_RTC_COMP_P2_M 0x000000FF +#define CCFG_RTC_OFFSET_RTC_COMP_P2_S 0 //***************************************************************************** // @@ -597,27 +597,27 @@ // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_FREQ_OFFSET_HF_COMP_P0_W 16 -#define CCFG_FREQ_OFFSET_HF_COMP_P0_M 0xFFFF0000 -#define CCFG_FREQ_OFFSET_HF_COMP_P0_S 16 +#define CCFG_FREQ_OFFSET_HF_COMP_P0_W 16 +#define CCFG_FREQ_OFFSET_HF_COMP_P0_M 0xFFFF0000 +#define CCFG_FREQ_OFFSET_HF_COMP_P0_S 16 // Field: [15:8] HF_COMP_P1 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_FREQ_OFFSET_HF_COMP_P1_W 8 -#define CCFG_FREQ_OFFSET_HF_COMP_P1_M 0x0000FF00 -#define CCFG_FREQ_OFFSET_HF_COMP_P1_S 8 +#define CCFG_FREQ_OFFSET_HF_COMP_P1_W 8 +#define CCFG_FREQ_OFFSET_HF_COMP_P1_M 0x0000FF00 +#define CCFG_FREQ_OFFSET_HF_COMP_P1_S 8 // Field: [7:0] HF_COMP_P2 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_FREQ_OFFSET_HF_COMP_P2_W 8 -#define CCFG_FREQ_OFFSET_HF_COMP_P2_M 0x000000FF -#define CCFG_FREQ_OFFSET_HF_COMP_P2_S 0 +#define CCFG_FREQ_OFFSET_HF_COMP_P2_W 8 +#define CCFG_FREQ_OFFSET_HF_COMP_P2_M 0x000000FF +#define CCFG_FREQ_OFFSET_HF_COMP_P2_S 0 //***************************************************************************** // @@ -629,9 +629,9 @@ // Bits[31:0] of the 64-bits custom IEEE MAC address. // If different from 0xFFFFFFFF then the value of this field is applied; // otherwise use value from FCFG. -#define CCFG_IEEE_MAC_0_ADDR_W 32 -#define CCFG_IEEE_MAC_0_ADDR_M 0xFFFFFFFF -#define CCFG_IEEE_MAC_0_ADDR_S 0 +#define CCFG_IEEE_MAC_0_ADDR_W 32 +#define CCFG_IEEE_MAC_0_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_MAC_0_ADDR_S 0 //***************************************************************************** // @@ -643,9 +643,9 @@ // Bits[63:32] of the 64-bits custom IEEE MAC address. // If different from 0xFFFFFFFF then the value of this field is applied; // otherwise use value from FCFG. -#define CCFG_IEEE_MAC_1_ADDR_W 32 -#define CCFG_IEEE_MAC_1_ADDR_M 0xFFFFFFFF -#define CCFG_IEEE_MAC_1_ADDR_S 0 +#define CCFG_IEEE_MAC_1_ADDR_W 32 +#define CCFG_IEEE_MAC_1_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_MAC_1_ADDR_S 0 //***************************************************************************** // @@ -657,9 +657,9 @@ // Bits[31:0] of the 64-bits custom IEEE BLE address. // If different from 0xFFFFFFFF then the value of this field is applied; // otherwise use value from FCFG. -#define CCFG_IEEE_BLE_0_ADDR_W 32 -#define CCFG_IEEE_BLE_0_ADDR_M 0xFFFFFFFF -#define CCFG_IEEE_BLE_0_ADDR_S 0 +#define CCFG_IEEE_BLE_0_ADDR_W 32 +#define CCFG_IEEE_BLE_0_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_BLE_0_ADDR_S 0 //***************************************************************************** // @@ -671,9 +671,9 @@ // Bits[63:32] of the 64-bits custom IEEE BLE address. // If different from 0xFFFFFFFF then the value of this field is applied; // otherwise use value from FCFG. -#define CCFG_IEEE_BLE_1_ADDR_W 32 -#define CCFG_IEEE_BLE_1_ADDR_M 0xFFFFFFFF -#define CCFG_IEEE_BLE_1_ADDR_S 0 +#define CCFG_IEEE_BLE_1_ADDR_W 32 +#define CCFG_IEEE_BLE_1_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_BLE_1_ADDR_S 0 //***************************************************************************** // @@ -687,9 +687,9 @@ // conditions for boot loader backdoor are met). // 0xC5: Boot loader is enabled. // Any other value: Boot loader is disabled. -#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_W 8 -#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M 0xFF000000 -#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S 24 +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_W 8 +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M 0xFF000000 +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S 24 // Field: [16] BL_LEVEL // @@ -697,18 +697,18 @@ // loader backdoor is enabled by the BL_ENABLE field. // 0: Active low. // 1: Active high. -#define CCFG_BL_CONFIG_BL_LEVEL 0x00010000 -#define CCFG_BL_CONFIG_BL_LEVEL_BITN 16 -#define CCFG_BL_CONFIG_BL_LEVEL_M 0x00010000 -#define CCFG_BL_CONFIG_BL_LEVEL_S 16 +#define CCFG_BL_CONFIG_BL_LEVEL 0x00010000 +#define CCFG_BL_CONFIG_BL_LEVEL_BITN 16 +#define CCFG_BL_CONFIG_BL_LEVEL_M 0x00010000 +#define CCFG_BL_CONFIG_BL_LEVEL_S 16 // Field: [15:8] BL_PIN_NUMBER // // DIO number that is level checked if the boot loader backdoor is enabled by // the BL_ENABLE field. -#define CCFG_BL_CONFIG_BL_PIN_NUMBER_W 8 -#define CCFG_BL_CONFIG_BL_PIN_NUMBER_M 0x0000FF00 -#define CCFG_BL_CONFIG_BL_PIN_NUMBER_S 8 +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_W 8 +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_M 0x0000FF00 +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_S 8 // Field: [7:0] BL_ENABLE // @@ -718,9 +718,9 @@ // // NOTE! Boot loader must be enabled (see BOOTLOADER_ENABLE) if boot loader // backdoor is enabled. -#define CCFG_BL_CONFIG_BL_ENABLE_W 8 -#define CCFG_BL_CONFIG_BL_ENABLE_M 0x000000FF -#define CCFG_BL_CONFIG_BL_ENABLE_S 0 +#define CCFG_BL_CONFIG_BL_ENABLE_W 8 +#define CCFG_BL_CONFIG_BL_ENABLE_M 0x000000FF +#define CCFG_BL_CONFIG_BL_ENABLE_S 0 //***************************************************************************** // @@ -737,10 +737,10 @@ // 0: Disable. Any chip erase request detected during boot will be ignored. // 1: Enable. Any chip erase request detected during boot will be performed by // the boot FW. -#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x00000100 -#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_BITN 8 -#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M 0x00000100 -#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S 8 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x00000100 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_BITN 8 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M 0x00000100 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S 8 // Field: [0] BANK_ERASE_DIS_N // @@ -751,10 +751,10 @@ // protected by write protect configuration bits in CCFG. // 0: Disable the boot loader bank erase function. // 1: Enable the boot loader bank erase function. -#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x00000001 -#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_BITN 0 -#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M 0x00000001 -#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S 0 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x00000001 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_BITN 0 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M 0x00000001 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S 0 //***************************************************************************** // @@ -768,9 +768,9 @@ // option with the unlock code. // All other values: Disable the functionality of unlocking the TI FA option // with the unlock code. -#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_W 8 -#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M 0x000000FF -#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S 0 +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_W 8 +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M 0x000000FF +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S 0 //***************************************************************************** // @@ -784,9 +784,9 @@ // boot FW. // Any other value: Main CPU DAP access will remain disabled out of // power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M 0x00FF0000 -#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S 16 +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M 0x00FF0000 +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S 16 // Field: [15:8] PRCM_TAP_ENABLE // @@ -795,9 +795,9 @@ // if enabled by corresponding configuration value in FCFG1 defined by TI. // Any other value: PRCM TAP access will remain disabled out of // power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_M 0x0000FF00 -#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_S 8 +#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_M 0x0000FF00 +#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_S 8 // Field: [7:0] TEST_TAP_ENABLE // @@ -806,9 +806,9 @@ // if enabled by corresponding configuration value in FCFG1 defined by TI. // Any other value: TEST TAP access will remain disabled out of // power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M 0x000000FF -#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S 0 +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M 0x000000FF +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S 0 //***************************************************************************** // @@ -822,9 +822,9 @@ // FW if enabled by corresponding configuration value in FCFG1 defined by TI. // Any other value: PBIST2 TAP access will remain disabled out of // power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M 0x00FF0000 -#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S 16 +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M 0x00FF0000 +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S 16 // Field: [15:8] PBIST1_TAP_ENABLE // @@ -833,9 +833,9 @@ // FW if enabled by corresponding configuration value in FCFG1 defined by TI. // Any other value: PBIST1 TAP access will remain disabled out of // power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M 0x0000FF00 -#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S 8 +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M 0x0000FF00 +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S 8 // Field: [7:0] WUC_TAP_ENABLE // @@ -844,9 +844,9 @@ // if enabled by corresponding configuration value in FCFG1 defined by TI. // Any other value: WUC TAP access will remain disabled out of // power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_M 0x000000FF -#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_S 0 +#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_M 0x000000FF +#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_S 0 //***************************************************************************** // @@ -867,9 +867,9 @@ // call the boot loader. // Note that if any other legal vector table start address value than 0x0 is // selected the PRCM:WARMRESET.WR_TO_PINRESET must be set to 1. -#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_W 32 -#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_M 0xFFFFFFFF -#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_S 0 +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_W 32 +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_M 0xFFFFFFFF +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_S 0 //***************************************************************************** // @@ -879,258 +879,258 @@ // Field: [31] WRT_PROT_SEC_31 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31 0x80000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_BITN 31 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_M 0x80000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_S 31 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31 0x80000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_BITN 31 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_M 0x80000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_S 31 // Field: [30] WRT_PROT_SEC_30 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30 0x40000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_BITN 30 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_M 0x40000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_S 30 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30 0x40000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_BITN 30 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_M 0x40000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_S 30 // Field: [29] WRT_PROT_SEC_29 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29 0x20000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_BITN 29 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_M 0x20000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_S 29 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29 0x20000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_BITN 29 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_M 0x20000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_S 29 // Field: [28] WRT_PROT_SEC_28 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28 0x10000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_BITN 28 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_M 0x10000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_S 28 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28 0x10000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_BITN 28 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_M 0x10000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_S 28 // Field: [27] WRT_PROT_SEC_27 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27 0x08000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_BITN 27 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_M 0x08000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_S 27 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27 0x08000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_BITN 27 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_M 0x08000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_S 27 // Field: [26] WRT_PROT_SEC_26 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26 0x04000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_BITN 26 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_M 0x04000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_S 26 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26 0x04000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_BITN 26 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_M 0x04000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_S 26 // Field: [25] WRT_PROT_SEC_25 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25 0x02000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_BITN 25 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_M 0x02000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_S 25 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25 0x02000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_BITN 25 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_M 0x02000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_S 25 // Field: [24] WRT_PROT_SEC_24 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24 0x01000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_BITN 24 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_M 0x01000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_S 24 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24 0x01000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_BITN 24 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_M 0x01000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_S 24 // Field: [23] WRT_PROT_SEC_23 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23 0x00800000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_BITN 23 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_M 0x00800000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_S 23 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23 0x00800000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_BITN 23 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_M 0x00800000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_S 23 // Field: [22] WRT_PROT_SEC_22 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22 0x00400000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_BITN 22 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_M 0x00400000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_S 22 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22 0x00400000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_BITN 22 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_M 0x00400000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_S 22 // Field: [21] WRT_PROT_SEC_21 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21 0x00200000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_BITN 21 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_M 0x00200000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_S 21 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21 0x00200000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_BITN 21 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_M 0x00200000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_S 21 // Field: [20] WRT_PROT_SEC_20 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20 0x00100000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_BITN 20 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_M 0x00100000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_S 20 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20 0x00100000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_BITN 20 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_M 0x00100000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_S 20 // Field: [19] WRT_PROT_SEC_19 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19 0x00080000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_BITN 19 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_M 0x00080000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_S 19 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19 0x00080000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_BITN 19 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_M 0x00080000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_S 19 // Field: [18] WRT_PROT_SEC_18 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18 0x00040000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_BITN 18 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_M 0x00040000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_S 18 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18 0x00040000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_BITN 18 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_M 0x00040000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_S 18 // Field: [17] WRT_PROT_SEC_17 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17 0x00020000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_BITN 17 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_M 0x00020000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_S 17 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17 0x00020000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_BITN 17 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_M 0x00020000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_S 17 // Field: [16] WRT_PROT_SEC_16 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16 0x00010000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_BITN 16 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_M 0x00010000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_S 16 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16 0x00010000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_BITN 16 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_M 0x00010000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_S 16 // Field: [15] WRT_PROT_SEC_15 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15 0x00008000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_BITN 15 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_M 0x00008000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_S 15 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15 0x00008000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_BITN 15 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_M 0x00008000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_S 15 // Field: [14] WRT_PROT_SEC_14 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14 0x00004000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_BITN 14 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_M 0x00004000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_S 14 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14 0x00004000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_BITN 14 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_M 0x00004000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_S 14 // Field: [13] WRT_PROT_SEC_13 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13 0x00002000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_BITN 13 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_M 0x00002000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_S 13 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13 0x00002000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_BITN 13 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_M 0x00002000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_S 13 // Field: [12] WRT_PROT_SEC_12 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12 0x00001000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_BITN 12 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_M 0x00001000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_S 12 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12 0x00001000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_BITN 12 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_M 0x00001000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_S 12 // Field: [11] WRT_PROT_SEC_11 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11 0x00000800 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_BITN 11 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_M 0x00000800 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_S 11 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11 0x00000800 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_BITN 11 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_M 0x00000800 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_S 11 // Field: [10] WRT_PROT_SEC_10 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10 0x00000400 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_BITN 10 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_M 0x00000400 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_S 10 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10 0x00000400 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_BITN 10 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_M 0x00000400 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_S 10 // Field: [9] WRT_PROT_SEC_9 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9 0x00000200 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_BITN 9 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_M 0x00000200 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_S 9 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9 0x00000200 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_BITN 9 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_M 0x00000200 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_S 9 // Field: [8] WRT_PROT_SEC_8 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8 0x00000100 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_BITN 8 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_M 0x00000100 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_S 8 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8 0x00000100 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_BITN 8 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_M 0x00000100 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_S 8 // Field: [7] WRT_PROT_SEC_7 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7 0x00000080 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_BITN 7 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_M 0x00000080 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_S 7 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7 0x00000080 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_BITN 7 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_M 0x00000080 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_S 7 // Field: [6] WRT_PROT_SEC_6 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6 0x00000040 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_BITN 6 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_M 0x00000040 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_S 6 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6 0x00000040 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_BITN 6 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_M 0x00000040 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_S 6 // Field: [5] WRT_PROT_SEC_5 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5 0x00000020 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_BITN 5 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_M 0x00000020 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_S 5 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5 0x00000020 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_BITN 5 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_M 0x00000020 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_S 5 // Field: [4] WRT_PROT_SEC_4 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4 0x00000010 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_BITN 4 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_M 0x00000010 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_S 4 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4 0x00000010 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_BITN 4 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_M 0x00000010 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_S 4 // Field: [3] WRT_PROT_SEC_3 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3 0x00000008 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_BITN 3 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_M 0x00000008 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_S 3 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3 0x00000008 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_BITN 3 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_M 0x00000008 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_S 3 // Field: [2] WRT_PROT_SEC_2 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2 0x00000004 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_BITN 2 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_M 0x00000004 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_S 2 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2 0x00000004 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_BITN 2 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_M 0x00000004 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_S 2 // Field: [1] WRT_PROT_SEC_1 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1 0x00000002 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_BITN 1 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_M 0x00000002 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_S 1 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1 0x00000002 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_BITN 1 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_M 0x00000002 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_S 1 // Field: [0] WRT_PROT_SEC_0 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0 0x00000001 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_BITN 0 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_M 0x00000001 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_S 0 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0 0x00000001 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_BITN 0 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_M 0x00000001 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_S 0 //***************************************************************************** // @@ -1140,258 +1140,258 @@ // Field: [31] WRT_PROT_SEC_63 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63 0x80000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_BITN 31 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_M 0x80000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_S 31 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63 0x80000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_BITN 31 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_M 0x80000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_S 31 // Field: [30] WRT_PROT_SEC_62 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62 0x40000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_BITN 30 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_M 0x40000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_S 30 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62 0x40000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_BITN 30 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_M 0x40000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_S 30 // Field: [29] WRT_PROT_SEC_61 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61 0x20000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_BITN 29 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_M 0x20000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_S 29 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61 0x20000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_BITN 29 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_M 0x20000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_S 29 // Field: [28] WRT_PROT_SEC_60 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60 0x10000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_BITN 28 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_M 0x10000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_S 28 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60 0x10000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_BITN 28 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_M 0x10000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_S 28 // Field: [27] WRT_PROT_SEC_59 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59 0x08000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_BITN 27 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_M 0x08000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_S 27 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59 0x08000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_BITN 27 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_M 0x08000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_S 27 // Field: [26] WRT_PROT_SEC_58 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58 0x04000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_BITN 26 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_M 0x04000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_S 26 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58 0x04000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_BITN 26 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_M 0x04000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_S 26 // Field: [25] WRT_PROT_SEC_57 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57 0x02000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_BITN 25 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_M 0x02000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_S 25 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57 0x02000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_BITN 25 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_M 0x02000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_S 25 // Field: [24] WRT_PROT_SEC_56 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56 0x01000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_BITN 24 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_M 0x01000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_S 24 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56 0x01000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_BITN 24 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_M 0x01000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_S 24 // Field: [23] WRT_PROT_SEC_55 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55 0x00800000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_BITN 23 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_M 0x00800000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_S 23 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55 0x00800000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_BITN 23 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_M 0x00800000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_S 23 // Field: [22] WRT_PROT_SEC_54 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54 0x00400000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_BITN 22 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_M 0x00400000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_S 22 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54 0x00400000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_BITN 22 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_M 0x00400000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_S 22 // Field: [21] WRT_PROT_SEC_53 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53 0x00200000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_BITN 21 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_M 0x00200000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_S 21 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53 0x00200000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_BITN 21 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_M 0x00200000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_S 21 // Field: [20] WRT_PROT_SEC_52 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52 0x00100000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_BITN 20 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_M 0x00100000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_S 20 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52 0x00100000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_BITN 20 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_M 0x00100000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_S 20 // Field: [19] WRT_PROT_SEC_51 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51 0x00080000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_BITN 19 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_M 0x00080000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_S 19 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51 0x00080000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_BITN 19 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_M 0x00080000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_S 19 // Field: [18] WRT_PROT_SEC_50 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50 0x00040000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_BITN 18 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_M 0x00040000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_S 18 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50 0x00040000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_BITN 18 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_M 0x00040000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_S 18 // Field: [17] WRT_PROT_SEC_49 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49 0x00020000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_BITN 17 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_M 0x00020000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_S 17 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49 0x00020000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_BITN 17 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_M 0x00020000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_S 17 // Field: [16] WRT_PROT_SEC_48 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48 0x00010000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_BITN 16 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_M 0x00010000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_S 16 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48 0x00010000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_BITN 16 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_M 0x00010000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_S 16 // Field: [15] WRT_PROT_SEC_47 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47 0x00008000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_BITN 15 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_M 0x00008000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_S 15 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47 0x00008000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_BITN 15 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_M 0x00008000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_S 15 // Field: [14] WRT_PROT_SEC_46 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46 0x00004000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_BITN 14 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_M 0x00004000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_S 14 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46 0x00004000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_BITN 14 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_M 0x00004000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_S 14 // Field: [13] WRT_PROT_SEC_45 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45 0x00002000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_BITN 13 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_M 0x00002000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_S 13 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45 0x00002000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_BITN 13 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_M 0x00002000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_S 13 // Field: [12] WRT_PROT_SEC_44 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44 0x00001000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_BITN 12 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_M 0x00001000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_S 12 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44 0x00001000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_BITN 12 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_M 0x00001000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_S 12 // Field: [11] WRT_PROT_SEC_43 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43 0x00000800 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_BITN 11 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_M 0x00000800 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_S 11 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43 0x00000800 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_BITN 11 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_M 0x00000800 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_S 11 // Field: [10] WRT_PROT_SEC_42 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42 0x00000400 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_BITN 10 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_M 0x00000400 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_S 10 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42 0x00000400 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_BITN 10 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_M 0x00000400 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_S 10 // Field: [9] WRT_PROT_SEC_41 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41 0x00000200 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_BITN 9 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_M 0x00000200 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_S 9 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41 0x00000200 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_BITN 9 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_M 0x00000200 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_S 9 // Field: [8] WRT_PROT_SEC_40 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40 0x00000100 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_BITN 8 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_M 0x00000100 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_S 8 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40 0x00000100 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_BITN 8 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_M 0x00000100 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_S 8 // Field: [7] WRT_PROT_SEC_39 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39 0x00000080 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_BITN 7 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_M 0x00000080 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_S 7 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39 0x00000080 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_BITN 7 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_M 0x00000080 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_S 7 // Field: [6] WRT_PROT_SEC_38 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38 0x00000040 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_BITN 6 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_M 0x00000040 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_S 6 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38 0x00000040 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_BITN 6 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_M 0x00000040 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_S 6 // Field: [5] WRT_PROT_SEC_37 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37 0x00000020 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_BITN 5 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_M 0x00000020 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_S 5 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37 0x00000020 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_BITN 5 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_M 0x00000020 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_S 5 // Field: [4] WRT_PROT_SEC_36 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36 0x00000010 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_BITN 4 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_M 0x00000010 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_S 4 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36 0x00000010 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_BITN 4 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_M 0x00000010 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_S 4 // Field: [3] WRT_PROT_SEC_35 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35 0x00000008 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_BITN 3 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_M 0x00000008 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_S 3 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35 0x00000008 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_BITN 3 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_M 0x00000008 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_S 3 // Field: [2] WRT_PROT_SEC_34 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34 0x00000004 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_BITN 2 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_M 0x00000004 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_S 2 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34 0x00000004 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_BITN 2 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_M 0x00000004 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_S 2 // Field: [1] WRT_PROT_SEC_33 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33 0x00000002 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_BITN 1 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_M 0x00000002 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_S 1 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33 0x00000002 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_BITN 1 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_M 0x00000002 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_S 1 // Field: [0] WRT_PROT_SEC_32 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32 0x00000001 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_BITN 0 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_M 0x00000001 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_S 0 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32 0x00000001 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_BITN 0 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_M 0x00000001 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_S 0 //***************************************************************************** // @@ -1401,258 +1401,258 @@ // Field: [31] WRT_PROT_SEC_95 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95 0x80000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_BITN 31 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_M 0x80000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_S 31 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95 0x80000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_BITN 31 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_M 0x80000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_S 31 // Field: [30] WRT_PROT_SEC_94 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94 0x40000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_BITN 30 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_M 0x40000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_S 30 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94 0x40000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_BITN 30 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_M 0x40000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_S 30 // Field: [29] WRT_PROT_SEC_93 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93 0x20000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_BITN 29 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_M 0x20000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_S 29 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93 0x20000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_BITN 29 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_M 0x20000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_S 29 // Field: [28] WRT_PROT_SEC_92 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92 0x10000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_BITN 28 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_M 0x10000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_S 28 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92 0x10000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_BITN 28 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_M 0x10000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_S 28 // Field: [27] WRT_PROT_SEC_91 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91 0x08000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_BITN 27 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_M 0x08000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_S 27 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91 0x08000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_BITN 27 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_M 0x08000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_S 27 // Field: [26] WRT_PROT_SEC_90 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90 0x04000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_BITN 26 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_M 0x04000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_S 26 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90 0x04000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_BITN 26 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_M 0x04000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_S 26 // Field: [25] WRT_PROT_SEC_89 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89 0x02000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_BITN 25 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_M 0x02000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_S 25 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89 0x02000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_BITN 25 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_M 0x02000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_S 25 // Field: [24] WRT_PROT_SEC_88 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88 0x01000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_BITN 24 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_M 0x01000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_S 24 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88 0x01000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_BITN 24 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_M 0x01000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_S 24 // Field: [23] WRT_PROT_SEC_87 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87 0x00800000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_BITN 23 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_M 0x00800000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_S 23 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87 0x00800000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_BITN 23 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_M 0x00800000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_S 23 // Field: [22] WRT_PROT_SEC_86 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86 0x00400000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_BITN 22 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_M 0x00400000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_S 22 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86 0x00400000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_BITN 22 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_M 0x00400000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_S 22 // Field: [21] WRT_PROT_SEC_85 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85 0x00200000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_BITN 21 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_M 0x00200000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_S 21 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85 0x00200000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_BITN 21 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_M 0x00200000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_S 21 // Field: [20] WRT_PROT_SEC_84 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84 0x00100000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_BITN 20 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_M 0x00100000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_S 20 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84 0x00100000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_BITN 20 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_M 0x00100000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_S 20 // Field: [19] WRT_PROT_SEC_83 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83 0x00080000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_BITN 19 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_M 0x00080000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_S 19 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83 0x00080000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_BITN 19 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_M 0x00080000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_S 19 // Field: [18] WRT_PROT_SEC_82 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82 0x00040000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_BITN 18 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_M 0x00040000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_S 18 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82 0x00040000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_BITN 18 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_M 0x00040000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_S 18 // Field: [17] WRT_PROT_SEC_81 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81 0x00020000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_BITN 17 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_M 0x00020000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_S 17 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81 0x00020000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_BITN 17 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_M 0x00020000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_S 17 // Field: [16] WRT_PROT_SEC_80 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80 0x00010000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_BITN 16 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_M 0x00010000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_S 16 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80 0x00010000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_BITN 16 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_M 0x00010000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_S 16 // Field: [15] WRT_PROT_SEC_79 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79 0x00008000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_BITN 15 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_M 0x00008000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_S 15 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79 0x00008000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_BITN 15 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_M 0x00008000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_S 15 // Field: [14] WRT_PROT_SEC_78 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78 0x00004000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_BITN 14 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_M 0x00004000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_S 14 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78 0x00004000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_BITN 14 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_M 0x00004000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_S 14 // Field: [13] WRT_PROT_SEC_77 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77 0x00002000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_BITN 13 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_M 0x00002000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_S 13 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77 0x00002000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_BITN 13 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_M 0x00002000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_S 13 // Field: [12] WRT_PROT_SEC_76 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76 0x00001000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_BITN 12 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_M 0x00001000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_S 12 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76 0x00001000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_BITN 12 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_M 0x00001000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_S 12 // Field: [11] WRT_PROT_SEC_75 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75 0x00000800 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_BITN 11 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_M 0x00000800 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_S 11 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75 0x00000800 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_BITN 11 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_M 0x00000800 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_S 11 // Field: [10] WRT_PROT_SEC_74 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74 0x00000400 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_BITN 10 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_M 0x00000400 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_S 10 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74 0x00000400 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_BITN 10 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_M 0x00000400 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_S 10 // Field: [9] WRT_PROT_SEC_73 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73 0x00000200 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_BITN 9 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_M 0x00000200 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_S 9 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73 0x00000200 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_BITN 9 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_M 0x00000200 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_S 9 // Field: [8] WRT_PROT_SEC_72 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72 0x00000100 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_BITN 8 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_M 0x00000100 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_S 8 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72 0x00000100 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_BITN 8 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_M 0x00000100 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_S 8 // Field: [7] WRT_PROT_SEC_71 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71 0x00000080 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_BITN 7 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_M 0x00000080 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_S 7 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71 0x00000080 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_BITN 7 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_M 0x00000080 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_S 7 // Field: [6] WRT_PROT_SEC_70 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70 0x00000040 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_BITN 6 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_M 0x00000040 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_S 6 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70 0x00000040 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_BITN 6 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_M 0x00000040 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_S 6 // Field: [5] WRT_PROT_SEC_69 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69 0x00000020 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_BITN 5 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_M 0x00000020 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_S 5 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69 0x00000020 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_BITN 5 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_M 0x00000020 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_S 5 // Field: [4] WRT_PROT_SEC_68 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68 0x00000010 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_BITN 4 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_M 0x00000010 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_S 4 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68 0x00000010 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_BITN 4 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_M 0x00000010 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_S 4 // Field: [3] WRT_PROT_SEC_67 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67 0x00000008 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_BITN 3 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_M 0x00000008 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_S 3 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67 0x00000008 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_BITN 3 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_M 0x00000008 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_S 3 // Field: [2] WRT_PROT_SEC_66 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66 0x00000004 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_BITN 2 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_M 0x00000004 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_S 2 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66 0x00000004 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_BITN 2 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_M 0x00000004 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_S 2 // Field: [1] WRT_PROT_SEC_65 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65 0x00000002 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_BITN 1 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_M 0x00000002 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_S 1 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65 0x00000002 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_BITN 1 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_M 0x00000002 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_S 1 // Field: [0] WRT_PROT_SEC_64 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64 0x00000001 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_BITN 0 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_M 0x00000001 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_S 0 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64 0x00000001 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_BITN 0 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_M 0x00000001 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_S 0 //***************************************************************************** // @@ -1662,258 +1662,257 @@ // Field: [31] WRT_PROT_SEC_127 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127 0x80000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_BITN 31 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_M 0x80000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_S 31 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127 0x80000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_BITN 31 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_M 0x80000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_S 31 // Field: [30] WRT_PROT_SEC_126 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126 0x40000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_BITN 30 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_M 0x40000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_S 30 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126 0x40000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_BITN 30 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_M 0x40000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_S 30 // Field: [29] WRT_PROT_SEC_125 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125 0x20000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_BITN 29 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_M 0x20000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_S 29 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125 0x20000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_BITN 29 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_M 0x20000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_S 29 // Field: [28] WRT_PROT_SEC_124 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124 0x10000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_BITN 28 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_M 0x10000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_S 28 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124 0x10000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_BITN 28 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_M 0x10000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_S 28 // Field: [27] WRT_PROT_SEC_123 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123 0x08000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_BITN 27 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_M 0x08000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_S 27 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123 0x08000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_BITN 27 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_M 0x08000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_S 27 // Field: [26] WRT_PROT_SEC_122 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122 0x04000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_BITN 26 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_M 0x04000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_S 26 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122 0x04000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_BITN 26 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_M 0x04000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_S 26 // Field: [25] WRT_PROT_SEC_121 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121 0x02000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_BITN 25 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_M 0x02000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_S 25 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121 0x02000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_BITN 25 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_M 0x02000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_S 25 // Field: [24] WRT_PROT_SEC_120 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120 0x01000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_BITN 24 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_M 0x01000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_S 24 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120 0x01000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_BITN 24 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_M 0x01000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_S 24 // Field: [23] WRT_PROT_SEC_119 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119 0x00800000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_BITN 23 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_M 0x00800000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_S 23 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119 0x00800000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_BITN 23 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_M 0x00800000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_S 23 // Field: [22] WRT_PROT_SEC_118 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118 0x00400000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_BITN 22 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_M 0x00400000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_S 22 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118 0x00400000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_BITN 22 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_M 0x00400000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_S 22 // Field: [21] WRT_PROT_SEC_117 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117 0x00200000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_BITN 21 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_M 0x00200000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_S 21 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117 0x00200000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_BITN 21 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_M 0x00200000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_S 21 // Field: [20] WRT_PROT_SEC_116 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116 0x00100000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_BITN 20 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_M 0x00100000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_S 20 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116 0x00100000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_BITN 20 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_M 0x00100000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_S 20 // Field: [19] WRT_PROT_SEC_115 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115 0x00080000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_BITN 19 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_M 0x00080000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_S 19 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115 0x00080000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_BITN 19 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_M 0x00080000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_S 19 // Field: [18] WRT_PROT_SEC_114 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114 0x00040000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_BITN 18 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_M 0x00040000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_S 18 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114 0x00040000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_BITN 18 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_M 0x00040000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_S 18 // Field: [17] WRT_PROT_SEC_113 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113 0x00020000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_BITN 17 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_M 0x00020000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_S 17 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113 0x00020000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_BITN 17 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_M 0x00020000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_S 17 // Field: [16] WRT_PROT_SEC_112 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112 0x00010000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_BITN 16 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_M 0x00010000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_S 16 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112 0x00010000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_BITN 16 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_M 0x00010000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_S 16 // Field: [15] WRT_PROT_SEC_111 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111 0x00008000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_BITN 15 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_M 0x00008000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_S 15 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111 0x00008000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_BITN 15 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_M 0x00008000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_S 15 // Field: [14] WRT_PROT_SEC_110 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110 0x00004000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_BITN 14 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_M 0x00004000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_S 14 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110 0x00004000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_BITN 14 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_M 0x00004000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_S 14 // Field: [13] WRT_PROT_SEC_109 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109 0x00002000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_BITN 13 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_M 0x00002000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_S 13 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109 0x00002000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_BITN 13 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_M 0x00002000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_S 13 // Field: [12] WRT_PROT_SEC_108 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108 0x00001000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_BITN 12 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_M 0x00001000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_S 12 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108 0x00001000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_BITN 12 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_M 0x00001000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_S 12 // Field: [11] WRT_PROT_SEC_107 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107 0x00000800 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_BITN 11 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_M 0x00000800 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_S 11 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107 0x00000800 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_BITN 11 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_M 0x00000800 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_S 11 // Field: [10] WRT_PROT_SEC_106 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106 0x00000400 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_BITN 10 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_M 0x00000400 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_S 10 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106 0x00000400 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_BITN 10 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_M 0x00000400 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_S 10 // Field: [9] WRT_PROT_SEC_105 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105 0x00000200 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_BITN 9 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_M 0x00000200 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_S 9 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105 0x00000200 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_BITN 9 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_M 0x00000200 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_S 9 // Field: [8] WRT_PROT_SEC_104 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104 0x00000100 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_BITN 8 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_M 0x00000100 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_S 8 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104 0x00000100 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_BITN 8 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_M 0x00000100 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_S 8 // Field: [7] WRT_PROT_SEC_103 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103 0x00000080 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_BITN 7 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_M 0x00000080 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_S 7 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103 0x00000080 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_BITN 7 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_M 0x00000080 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_S 7 // Field: [6] WRT_PROT_SEC_102 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102 0x00000040 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_BITN 6 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_M 0x00000040 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_S 6 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102 0x00000040 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_BITN 6 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_M 0x00000040 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_S 6 // Field: [5] WRT_PROT_SEC_101 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101 0x00000020 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_BITN 5 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_M 0x00000020 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_S 5 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101 0x00000020 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_BITN 5 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_M 0x00000020 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_S 5 // Field: [4] WRT_PROT_SEC_100 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100 0x00000010 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_BITN 4 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_M 0x00000010 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_S 4 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100 0x00000010 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_BITN 4 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_M 0x00000010 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_S 4 // Field: [3] WRT_PROT_SEC_99 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99 0x00000008 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_BITN 3 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_M 0x00000008 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_S 3 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99 0x00000008 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_BITN 3 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_M 0x00000008 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_S 3 // Field: [2] WRT_PROT_SEC_98 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98 0x00000004 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_BITN 2 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_M 0x00000004 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_S 2 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98 0x00000004 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_BITN 2 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_M 0x00000004 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_S 2 // Field: [1] WRT_PROT_SEC_97 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97 0x00000002 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_BITN 1 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_M 0x00000002 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_S 1 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97 0x00000002 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_BITN 1 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_M 0x00000002 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_S 1 // Field: [0] WRT_PROT_SEC_96 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96 0x00000001 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_BITN 0 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_M 0x00000001 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_S 0 - +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96 0x00000001 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_BITN 0 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_M 0x00000001 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_S 0 #endif // __CCFG__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ccfg_simple_struct.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ccfg_simple_struct.h index 1a2c740..ea1fc90 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ccfg_simple_struct.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ccfg_simple_struct.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_ccfg_simple_struct_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_ccfg_simple_struct_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CCFG_SIMPLE_STRUCT_H__ #define __HW_CCFG_SIMPLE_STRUCT_H__ @@ -46,29 +46,29 @@ //***************************************************************************** typedef struct { - // Mapped to address - uint32_t CCFG_EXT_LF_CLK ; // 0x50003FA8 - uint32_t CCFG_MODE_CONF_1 ; // 0x50003FAC - uint32_t CCFG_SIZE_AND_DIS_FLAGS ; // 0x50003FB0 - uint32_t CCFG_MODE_CONF ; // 0x50003FB4 - uint32_t CCFG_VOLT_LOAD_0 ; // 0x50003FB8 - uint32_t CCFG_VOLT_LOAD_1 ; // 0x50003FBC - uint32_t CCFG_RTC_OFFSET ; // 0x50003FC0 - uint32_t CCFG_FREQ_OFFSET ; // 0x50003FC4 - uint32_t CCFG_IEEE_MAC_0 ; // 0x50003FC8 - uint32_t CCFG_IEEE_MAC_1 ; // 0x50003FCC - uint32_t CCFG_IEEE_BLE_0 ; // 0x50003FD0 - uint32_t CCFG_IEEE_BLE_1 ; // 0x50003FD4 - uint32_t CCFG_BL_CONFIG ; // 0x50003FD8 - uint32_t CCFG_ERASE_CONF ; // 0x50003FDC - uint32_t CCFG_CCFG_TI_OPTIONS ; // 0x50003FE0 - uint32_t CCFG_CCFG_TAP_DAP_0 ; // 0x50003FE4 - uint32_t CCFG_CCFG_TAP_DAP_1 ; // 0x50003FE8 - uint32_t CCFG_IMAGE_VALID_CONF ; // 0x50003FEC - uint32_t CCFG_CCFG_PROT_31_0 ; // 0x50003FF0 - uint32_t CCFG_CCFG_PROT_63_32 ; // 0x50003FF4 - uint32_t CCFG_CCFG_PROT_95_64 ; // 0x50003FF8 - uint32_t CCFG_CCFG_PROT_127_96 ; // 0x50003FFC + // Mapped to address + uint32_t CCFG_EXT_LF_CLK; // 0x50003FA8 + uint32_t CCFG_MODE_CONF_1; // 0x50003FAC + uint32_t CCFG_SIZE_AND_DIS_FLAGS; // 0x50003FB0 + uint32_t CCFG_MODE_CONF; // 0x50003FB4 + uint32_t CCFG_VOLT_LOAD_0; // 0x50003FB8 + uint32_t CCFG_VOLT_LOAD_1; // 0x50003FBC + uint32_t CCFG_RTC_OFFSET; // 0x50003FC0 + uint32_t CCFG_FREQ_OFFSET; // 0x50003FC4 + uint32_t CCFG_IEEE_MAC_0; // 0x50003FC8 + uint32_t CCFG_IEEE_MAC_1; // 0x50003FCC + uint32_t CCFG_IEEE_BLE_0; // 0x50003FD0 + uint32_t CCFG_IEEE_BLE_1; // 0x50003FD4 + uint32_t CCFG_BL_CONFIG; // 0x50003FD8 + uint32_t CCFG_ERASE_CONF; // 0x50003FDC + uint32_t CCFG_CCFG_TI_OPTIONS; // 0x50003FE0 + uint32_t CCFG_CCFG_TAP_DAP_0; // 0x50003FE4 + uint32_t CCFG_CCFG_TAP_DAP_1; // 0x50003FE8 + uint32_t CCFG_IMAGE_VALID_CONF; // 0x50003FEC + uint32_t CCFG_CCFG_PROT_31_0; // 0x50003FF0 + uint32_t CCFG_CCFG_PROT_63_32; // 0x50003FF4 + uint32_t CCFG_CCFG_PROT_95_64; // 0x50003FF8 + uint32_t CCFG_CCFG_PROT_127_96; // 0x50003FFC } ccfg_t; //***************************************************************************** @@ -78,5 +78,4 @@ typedef struct //***************************************************************************** extern const ccfg_t __ccfg; - #endif // __HW_CCFG_SIMPLE_STRUCT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_chip_def.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_chip_def.h index 542a651..4bbbb15 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_chip_def.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_chip_def.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: hw_chip_def.h -* Revised: 2017-06-26 09:33:33 +0200 (Mon, 26 Jun 2017) -* Revision: 49227 -* -* Description: Defines for device properties. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_chip_def.h + * Revised: 2017-06-26 09:33:33 +0200 (Mon, 26 Jun 2017) + * Revision: 49227 + * + * Description: Defines for device properties. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -53,8 +53,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif //***************************************************************************** @@ -64,13 +63,13 @@ extern "C" // //***************************************************************************** /* CC2620F128 */ -#if defined(CC2620F128RGZ_R20) || defined(CC2620F128RGZ_R21) +#if defined(CC2620F128RGZ_R20) || defined(CC2620F128RGZ_R21) #define CC_CHIP_ID 0x26200720 #elif defined(CC2620F128RHB_R20) || defined(CC2620F128RHB_R21) #define CC_CHIP_ID 0x26200520 #elif defined(CC2620F128RSM_R20) || defined(CC2620F128RSM_R21) #define CC_CHIP_ID 0x26200420 -#elif defined(CC2620F128_R20) || defined(CC2620F128_R21) +#elif defined(CC2620F128_R20) || defined(CC2620F128_R21) #define CC_CHIP_ID 0x26200020 #elif defined(CC2620F128RGZ_R22) || defined(CC2620F128RGZ) #define CC_CHIP_ID 0x26200722 @@ -78,7 +77,7 @@ extern "C" #define CC_CHIP_ID 0x26200522 #elif defined(CC2620F128RSM_R22) || defined(CC2620F128RSM) #define CC_CHIP_ID 0x26200422 -#elif defined(CC2620F128_R22) || defined(CC2620F128) +#elif defined(CC2620F128_R22) || defined(CC2620F128) #define CC_CHIP_ID 0x26200022 /* CC2630F128 */ #elif defined(CC2630F128RGZ_R20) || defined(CC2630F128RGZ_R21) @@ -87,7 +86,7 @@ extern "C" #define CC_CHIP_ID 0x26300520 #elif defined(CC2630F128RSM_R20) || defined(CC2630F128RSM_R21) #define CC_CHIP_ID 0x26300420 -#elif defined(CC2630F128_R20) || defined(CC2630F128_R21) +#elif defined(CC2630F128_R20) || defined(CC2630F128_R21) #define CC_CHIP_ID 0x26300020 #elif defined(CC2630F128RGZ_R22) || defined(CC2630F128RGZ) #define CC_CHIP_ID 0x26300722 @@ -95,7 +94,7 @@ extern "C" #define CC_CHIP_ID 0x26300522 #elif defined(CC2630F128RSM_R22) || defined(CC2630F128RSM) #define CC_CHIP_ID 0x26300422 -#elif defined(CC2630F128_R22) || defined(CC2630F128) +#elif defined(CC2630F128_R22) || defined(CC2630F128) #define CC_CHIP_ID 0x26300022 /* CC2640F128 */ #elif defined(CC2640F128RGZ_R20) || defined(CC2640F128RGZ_R21) @@ -104,7 +103,7 @@ extern "C" #define CC_CHIP_ID 0x26400520 #elif defined(CC2640F128RSM_R20) || defined(CC2640F128RSM_R21) #define CC_CHIP_ID 0x26400420 -#elif defined(CC2640F128_R20) || defined(CC2640F128_R21) +#elif defined(CC2640F128_R20) || defined(CC2640F128_R21) #define CC_CHIP_ID 0x26400020 #elif defined(CC2640F128RGZ_R22) || defined(CC2640F128RGZ) #define CC_CHIP_ID 0x26400722 @@ -112,7 +111,7 @@ extern "C" #define CC_CHIP_ID 0x26400522 #elif defined(CC2640F128RSM_R22) || defined(CC2640F128RSM) #define CC_CHIP_ID 0x26400422 -#elif defined(CC2640F128_R22) || defined(CC2640F128) +#elif defined(CC2640F128_R22) || defined(CC2640F128) #define CC_CHIP_ID 0x26400022 /* CC2650F128 */ #elif defined(CC2650F128RGZ_R20) || defined(CC2650F128RGZ_R21) @@ -121,7 +120,7 @@ extern "C" #define CC_CHIP_ID 0x26500520 #elif defined(CC2650F128RSM_R20) || defined(CC2650F128RSM_R21) #define CC_CHIP_ID 0x26500420 -#elif defined(CC2650F128_R20) || defined(CC2650F128_R21) +#elif defined(CC2650F128_R20) || defined(CC2650F128_R21) #define CC_CHIP_ID 0x26500020 #elif defined(CC2650F128RGZ_R22) || defined(CC2650F128RGZ) #define CC_CHIP_ID 0x26500722 @@ -129,7 +128,7 @@ extern "C" #define CC_CHIP_ID 0x26500522 #elif defined(CC2650F128RSM_R22) || defined(CC2650F128RSM) #define CC_CHIP_ID 0x26500422 -#elif defined(CC2650F128_R22) || defined(CC2650F128) +#elif defined(CC2650F128_R22) || defined(CC2650F128) #define CC_CHIP_ID 0x26500022 /* CC2650L128 (OTP) */ #elif defined(CC2650L128) @@ -141,7 +140,7 @@ extern "C" #define CC_CHIP_ID 0x13100520 #elif defined(CC1310F128RSM_R20) || defined(CC1310F128RSM) #define CC_CHIP_ID 0x13100420 -#elif defined(CC1310F128_R20) || defined(CC1310F128) +#elif defined(CC1310F128_R20) || defined(CC1310F128) #define CC_CHIP_ID 0x13100020 /* CC1350F128 */ #elif defined(CC1350F128RGZ_R20) || defined(CC1350F128RGZ) @@ -150,7 +149,7 @@ extern "C" #define CC_CHIP_ID 0x13500520 #elif defined(CC1350F128RSM_R20) || defined(CC1350F128RSM) #define CC_CHIP_ID 0x13500420 -#elif defined(CC1350F128_R20) || defined(CC1350F128) +#elif defined(CC1350F128_R20) || defined(CC1350F128) #define CC_CHIP_ID 0x13500020 /* CC2640R2F */ #elif defined(CC2640R2FRGZ_R25) || defined(CC2640R2FRGZ) @@ -159,37 +158,37 @@ extern "C" #define CC_CHIP_ID 0x26401510 #elif defined(CC2640R2FRSM_R25) || defined(CC2640R2FRSM) #define CC_CHIP_ID 0x26401410 -#elif defined(CC2640R2F_R25) || defined(CC2640R2F) +#elif defined(CC2640R2F_R25) || defined(CC2640R2F) #define CC_CHIP_ID 0x26401010 /* CC2652R1F */ #elif defined(CC2652R1FRGZ_R10) || defined(CC2652R1FRGZ) #define CC_CHIP_ID 0x26523710 -#elif defined(CC2652R1F_R10) || defined(CC2652R1F) +#elif defined(CC2652R1F_R10) || defined(CC2652R1F) #define CC_CHIP_ID 0x26523010 /* CC2644R1F */ #elif defined(CC2644R1FRGZ_R10) || defined(CC2644R1FRGZ) #define CC_CHIP_ID 0x26443710 -#elif defined(CC2644R1F_R10) || defined(CC2644R1F) +#elif defined(CC2644R1F_R10) || defined(CC2644R1F) #define CC_CHIP_ID 0x26443010 /* CC2642R1F */ #elif defined(CC2642R1FRGZ_R10) || defined(CC2642R1FRGZ) #define CC_CHIP_ID 0x26423710 -#elif defined(CC2642R1F_R10) || defined(CC2642R1F) +#elif defined(CC2642R1F_R10) || defined(CC2642R1F) #define CC_CHIP_ID 0x26423010 /* CC1354R1F */ #elif defined(CC1354R1FRGZ_R10) || defined(CC1354R1FRGZ) #define CC_CHIP_ID 0x13543710 -#elif defined(CC1354R1F_R10) || defined(CC1354R1F) +#elif defined(CC1354R1F_R10) || defined(CC1354R1F) #define CC_CHIP_ID 0x13543010 /* CC1352R1F */ #elif defined(CC1352R1FRGZ_R10) || defined(CC1352R1FRGZ) #define CC_CHIP_ID 0x13523710 -#elif defined(CC1352R1F_R10) || defined(CC1352R1F) +#elif defined(CC1352R1F_R10) || defined(CC1352R1F) #define CC_CHIP_ID 0x13523010 /* CC1312R1F */ #elif defined(CC1312R1FRGZ_R10) || defined(CC1312R1FRGZ) #define CC_CHIP_ID 0x13123710 -#elif defined(CC1312R1F_R10) || defined(CC1312R1F) +#elif defined(CC1312R1F_R10) || defined(CC1312R1F) #define CC_CHIP_ID 0x13123010 #endif @@ -213,7 +212,7 @@ extern "C" #if (CC_GET_CHIP_OPTION != ((CC_CHIP_ID & 0x0000F000) >> 12)) #error "Specified chip option does not match DriverLib release" #endif -#if (CC_GET_CHIP_HWREV != ((CC_CHIP_ID & 0x000000FF) >> 0)) +#if (CC_GET_CHIP_HWREV != ((CC_CHIP_ID & 0x000000FF) >> 0)) #error "Specified chip hardware revision does not match DriverLib release" #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_dwt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_dwt.h index 1721748..4ae2807 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_dwt.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_dwt.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_cpu_dwt_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_cpu_dwt_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CPU_DWT_H__ #define __HW_CPU_DWT_H__ @@ -44,64 +44,64 @@ // //***************************************************************************** // Control -#define CPU_DWT_O_CTRL 0x00000000 +#define CPU_DWT_O_CTRL 0x00000000 // Current PC Sampler Cycle Count -#define CPU_DWT_O_CYCCNT 0x00000004 +#define CPU_DWT_O_CYCCNT 0x00000004 // CPI Count -#define CPU_DWT_O_CPICNT 0x00000008 +#define CPU_DWT_O_CPICNT 0x00000008 // Exception Overhead Count -#define CPU_DWT_O_EXCCNT 0x0000000C +#define CPU_DWT_O_EXCCNT 0x0000000C // Sleep Count -#define CPU_DWT_O_SLEEPCNT 0x00000010 +#define CPU_DWT_O_SLEEPCNT 0x00000010 // LSU Count -#define CPU_DWT_O_LSUCNT 0x00000014 +#define CPU_DWT_O_LSUCNT 0x00000014 // Fold Count -#define CPU_DWT_O_FOLDCNT 0x00000018 +#define CPU_DWT_O_FOLDCNT 0x00000018 // Program Counter Sample -#define CPU_DWT_O_PCSR 0x0000001C +#define CPU_DWT_O_PCSR 0x0000001C // Comparator 0 -#define CPU_DWT_O_COMP0 0x00000020 +#define CPU_DWT_O_COMP0 0x00000020 // Mask 0 -#define CPU_DWT_O_MASK0 0x00000024 +#define CPU_DWT_O_MASK0 0x00000024 // Function 0 -#define CPU_DWT_O_FUNCTION0 0x00000028 +#define CPU_DWT_O_FUNCTION0 0x00000028 // Comparator 1 -#define CPU_DWT_O_COMP1 0x00000030 +#define CPU_DWT_O_COMP1 0x00000030 // Mask 1 -#define CPU_DWT_O_MASK1 0x00000034 +#define CPU_DWT_O_MASK1 0x00000034 // Function 1 -#define CPU_DWT_O_FUNCTION1 0x00000038 +#define CPU_DWT_O_FUNCTION1 0x00000038 // Comparator 2 -#define CPU_DWT_O_COMP2 0x00000040 +#define CPU_DWT_O_COMP2 0x00000040 // Mask 2 -#define CPU_DWT_O_MASK2 0x00000044 +#define CPU_DWT_O_MASK2 0x00000044 // Function 2 -#define CPU_DWT_O_FUNCTION2 0x00000048 +#define CPU_DWT_O_FUNCTION2 0x00000048 // Comparator 3 -#define CPU_DWT_O_COMP3 0x00000050 +#define CPU_DWT_O_COMP3 0x00000050 // Mask 3 -#define CPU_DWT_O_MASK3 0x00000054 +#define CPU_DWT_O_MASK3 0x00000054 // Function 3 -#define CPU_DWT_O_FUNCTION3 0x00000058 +#define CPU_DWT_O_FUNCTION3 0x00000058 //***************************************************************************** // @@ -111,18 +111,18 @@ // Field: [25] NOCYCCNT // // When set, CYCCNT is not supported. -#define CPU_DWT_CTRL_NOCYCCNT 0x02000000 -#define CPU_DWT_CTRL_NOCYCCNT_BITN 25 -#define CPU_DWT_CTRL_NOCYCCNT_M 0x02000000 -#define CPU_DWT_CTRL_NOCYCCNT_S 25 +#define CPU_DWT_CTRL_NOCYCCNT 0x02000000 +#define CPU_DWT_CTRL_NOCYCCNT_BITN 25 +#define CPU_DWT_CTRL_NOCYCCNT_M 0x02000000 +#define CPU_DWT_CTRL_NOCYCCNT_S 25 // Field: [24] NOPRFCNT // // When set, FOLDCNT, LSUCNT, SLEEPCNT, EXCCNT, and CPICNT are not supported. -#define CPU_DWT_CTRL_NOPRFCNT 0x01000000 -#define CPU_DWT_CTRL_NOPRFCNT_BITN 24 -#define CPU_DWT_CTRL_NOPRFCNT_M 0x01000000 -#define CPU_DWT_CTRL_NOPRFCNT_S 24 +#define CPU_DWT_CTRL_NOPRFCNT 0x01000000 +#define CPU_DWT_CTRL_NOPRFCNT_BITN 24 +#define CPU_DWT_CTRL_NOPRFCNT_M 0x01000000 +#define CPU_DWT_CTRL_NOPRFCNT_S 24 // Field: [22] CYCEVTENA // @@ -132,10 +132,10 @@ // // 0: Cycle count events disabled // 1: Cycle count events enabled -#define CPU_DWT_CTRL_CYCEVTENA 0x00400000 -#define CPU_DWT_CTRL_CYCEVTENA_BITN 22 -#define CPU_DWT_CTRL_CYCEVTENA_M 0x00400000 -#define CPU_DWT_CTRL_CYCEVTENA_S 22 +#define CPU_DWT_CTRL_CYCEVTENA 0x00400000 +#define CPU_DWT_CTRL_CYCEVTENA_BITN 22 +#define CPU_DWT_CTRL_CYCEVTENA_M 0x00400000 +#define CPU_DWT_CTRL_CYCEVTENA_S 22 // Field: [21] FOLDEVTENA // @@ -146,10 +146,10 @@ // // 0: Folded instruction count events disabled. // 1: Folded instruction count events enabled. -#define CPU_DWT_CTRL_FOLDEVTENA 0x00200000 -#define CPU_DWT_CTRL_FOLDEVTENA_BITN 21 -#define CPU_DWT_CTRL_FOLDEVTENA_M 0x00200000 -#define CPU_DWT_CTRL_FOLDEVTENA_S 21 +#define CPU_DWT_CTRL_FOLDEVTENA 0x00200000 +#define CPU_DWT_CTRL_FOLDEVTENA_BITN 21 +#define CPU_DWT_CTRL_FOLDEVTENA_M 0x00200000 +#define CPU_DWT_CTRL_FOLDEVTENA_S 21 // Field: [20] LSUEVTENA // @@ -159,10 +159,10 @@ // // 0: LSU count events disabled. // 1: LSU count events enabled. -#define CPU_DWT_CTRL_LSUEVTENA 0x00100000 -#define CPU_DWT_CTRL_LSUEVTENA_BITN 20 -#define CPU_DWT_CTRL_LSUEVTENA_M 0x00100000 -#define CPU_DWT_CTRL_LSUEVTENA_S 20 +#define CPU_DWT_CTRL_LSUEVTENA 0x00100000 +#define CPU_DWT_CTRL_LSUEVTENA_BITN 20 +#define CPU_DWT_CTRL_LSUEVTENA_M 0x00100000 +#define CPU_DWT_CTRL_LSUEVTENA_S 20 // Field: [19] SLEEPEVTENA // @@ -171,10 +171,10 @@ // // 0: Sleep count events disabled. // 1: Sleep count events enabled. -#define CPU_DWT_CTRL_SLEEPEVTENA 0x00080000 -#define CPU_DWT_CTRL_SLEEPEVTENA_BITN 19 -#define CPU_DWT_CTRL_SLEEPEVTENA_M 0x00080000 -#define CPU_DWT_CTRL_SLEEPEVTENA_S 19 +#define CPU_DWT_CTRL_SLEEPEVTENA 0x00080000 +#define CPU_DWT_CTRL_SLEEPEVTENA_BITN 19 +#define CPU_DWT_CTRL_SLEEPEVTENA_M 0x00080000 +#define CPU_DWT_CTRL_SLEEPEVTENA_S 19 // Field: [18] EXCEVTENA // @@ -183,10 +183,10 @@ // // 0x0: Interrupt overhead event disabled. // 0x1: Interrupt overhead event enabled. -#define CPU_DWT_CTRL_EXCEVTENA 0x00040000 -#define CPU_DWT_CTRL_EXCEVTENA_BITN 18 -#define CPU_DWT_CTRL_EXCEVTENA_M 0x00040000 -#define CPU_DWT_CTRL_EXCEVTENA_S 18 +#define CPU_DWT_CTRL_EXCEVTENA 0x00040000 +#define CPU_DWT_CTRL_EXCEVTENA_BITN 18 +#define CPU_DWT_CTRL_EXCEVTENA_M 0x00040000 +#define CPU_DWT_CTRL_EXCEVTENA_S 18 // Field: [17] CPIEVTENA // @@ -195,10 +195,10 @@ // // 0: CPI counter events disabled. // 1: CPI counter events enabled. -#define CPU_DWT_CTRL_CPIEVTENA 0x00020000 -#define CPU_DWT_CTRL_CPIEVTENA_BITN 17 -#define CPU_DWT_CTRL_CPIEVTENA_M 0x00020000 -#define CPU_DWT_CTRL_CPIEVTENA_S 17 +#define CPU_DWT_CTRL_CPIEVTENA 0x00020000 +#define CPU_DWT_CTRL_CPIEVTENA_BITN 17 +#define CPU_DWT_CTRL_CPIEVTENA_M 0x00020000 +#define CPU_DWT_CTRL_CPIEVTENA_S 17 // Field: [16] EXCTRCENA // @@ -206,10 +206,10 @@ // // 0: Interrupt event trace disabled. // 1: Interrupt event trace enabled. -#define CPU_DWT_CTRL_EXCTRCENA 0x00010000 -#define CPU_DWT_CTRL_EXCTRCENA_BITN 16 -#define CPU_DWT_CTRL_EXCTRCENA_M 0x00010000 -#define CPU_DWT_CTRL_EXCTRCENA_S 16 +#define CPU_DWT_CTRL_EXCTRCENA 0x00010000 +#define CPU_DWT_CTRL_EXCTRCENA_BITN 16 +#define CPU_DWT_CTRL_EXCTRCENA_M 0x00010000 +#define CPU_DWT_CTRL_EXCTRCENA_S 16 // Field: [12] PCSAMPLEENA // @@ -219,10 +219,10 @@ // // 0: PC Sampling event disabled. // 1: Sampling event enabled. -#define CPU_DWT_CTRL_PCSAMPLEENA 0x00001000 -#define CPU_DWT_CTRL_PCSAMPLEENA_BITN 12 -#define CPU_DWT_CTRL_PCSAMPLEENA_M 0x00001000 -#define CPU_DWT_CTRL_PCSAMPLEENA_S 12 +#define CPU_DWT_CTRL_PCSAMPLEENA 0x00001000 +#define CPU_DWT_CTRL_PCSAMPLEENA_BITN 12 +#define CPU_DWT_CTRL_PCSAMPLEENA_M 0x00001000 +#define CPU_DWT_CTRL_PCSAMPLEENA_S 12 // Field: [11:10] SYNCTAP // @@ -235,13 +235,13 @@ // BIT26 Tap at bit 26 of CYCCNT // BIT24 Tap at bit 24 of CYCCNT // DIS Disabled. No synchronization packets -#define CPU_DWT_CTRL_SYNCTAP_W 2 -#define CPU_DWT_CTRL_SYNCTAP_M 0x00000C00 -#define CPU_DWT_CTRL_SYNCTAP_S 10 -#define CPU_DWT_CTRL_SYNCTAP_BIT28 0x00000C00 -#define CPU_DWT_CTRL_SYNCTAP_BIT26 0x00000800 -#define CPU_DWT_CTRL_SYNCTAP_BIT24 0x00000400 -#define CPU_DWT_CTRL_SYNCTAP_DIS 0x00000000 +#define CPU_DWT_CTRL_SYNCTAP_W 2 +#define CPU_DWT_CTRL_SYNCTAP_M 0x00000C00 +#define CPU_DWT_CTRL_SYNCTAP_S 10 +#define CPU_DWT_CTRL_SYNCTAP_BIT28 0x00000C00 +#define CPU_DWT_CTRL_SYNCTAP_BIT26 0x00000800 +#define CPU_DWT_CTRL_SYNCTAP_BIT24 0x00000400 +#define CPU_DWT_CTRL_SYNCTAP_DIS 0x00000000 // Field: [9] CYCTAP // @@ -253,12 +253,12 @@ // ENUMs: // BIT10 Selects bit [10] to tap // BIT6 Selects bit [6] to tap -#define CPU_DWT_CTRL_CYCTAP 0x00000200 -#define CPU_DWT_CTRL_CYCTAP_BITN 9 -#define CPU_DWT_CTRL_CYCTAP_M 0x00000200 -#define CPU_DWT_CTRL_CYCTAP_S 9 -#define CPU_DWT_CTRL_CYCTAP_BIT10 0x00000200 -#define CPU_DWT_CTRL_CYCTAP_BIT6 0x00000000 +#define CPU_DWT_CTRL_CYCTAP 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_BITN 9 +#define CPU_DWT_CTRL_CYCTAP_M 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_S 9 +#define CPU_DWT_CTRL_CYCTAP_BIT10 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_BIT6 0x00000000 // Field: [8:5] POSTCNT // @@ -266,9 +266,9 @@ // to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it // triggers an event for PCSAMPLEENA or CYCEVTENA use. It also reloads with the // value from POSTPRESET. -#define CPU_DWT_CTRL_POSTCNT_W 4 -#define CPU_DWT_CTRL_POSTCNT_M 0x000001E0 -#define CPU_DWT_CTRL_POSTCNT_S 5 +#define CPU_DWT_CTRL_POSTCNT_W 4 +#define CPU_DWT_CTRL_POSTCNT_M 0x000001E0 +#define CPU_DWT_CTRL_POSTCNT_S 5 // Field: [4:1] POSTPRESET // @@ -277,18 +277,18 @@ // a count-down value, to be reloaded into POSTCNT each time it reaches 0. For // example, a value 1 in this register means an event is formed every other tap // change. -#define CPU_DWT_CTRL_POSTPRESET_W 4 -#define CPU_DWT_CTRL_POSTPRESET_M 0x0000001E -#define CPU_DWT_CTRL_POSTPRESET_S 1 +#define CPU_DWT_CTRL_POSTPRESET_W 4 +#define CPU_DWT_CTRL_POSTPRESET_M 0x0000001E +#define CPU_DWT_CTRL_POSTPRESET_S 1 // Field: [0] CYCCNTENA // // Enable CYCCNT, allowing it to increment and generate synchronization and // count events. If NOCYCCNT = 1, this bit reads zero and ignore writes. -#define CPU_DWT_CTRL_CYCCNTENA 0x00000001 -#define CPU_DWT_CTRL_CYCCNTENA_BITN 0 -#define CPU_DWT_CTRL_CYCCNTENA_M 0x00000001 -#define CPU_DWT_CTRL_CYCCNTENA_S 0 +#define CPU_DWT_CTRL_CYCCNTENA 0x00000001 +#define CPU_DWT_CTRL_CYCCNTENA_BITN 0 +#define CPU_DWT_CTRL_CYCCNTENA_M 0x00000001 +#define CPU_DWT_CTRL_CYCCNTENA_S 0 //***************************************************************************** // @@ -303,9 +303,9 @@ // advance in power modes where free-running clock to CPU stops). It wraps // around to 0 on overflow. The debugger must initialize this to 0 when first // enabling. -#define CPU_DWT_CYCCNT_CYCCNT_W 32 -#define CPU_DWT_CYCCNT_CYCCNT_M 0xFFFFFFFF -#define CPU_DWT_CYCCNT_CYCCNT_S 0 +#define CPU_DWT_CYCCNT_CYCCNT_W 32 +#define CPU_DWT_CYCCNT_CYCCNT_M 0xFFFFFFFF +#define CPU_DWT_CYCCNT_CYCCNT_S 0 //***************************************************************************** // @@ -320,9 +320,9 @@ // stalls. If CTRL.CPIEVTENA is set, an event is emitted when the counter // overflows. This counter initializes to 0 when it is enabled using // CTRL.CPIEVTENA. -#define CPU_DWT_CPICNT_CPICNT_W 8 -#define CPU_DWT_CPICNT_CPICNT_M 0x000000FF -#define CPU_DWT_CPICNT_CPICNT_S 0 +#define CPU_DWT_CPICNT_CPICNT_W 8 +#define CPU_DWT_CPICNT_CPICNT_M 0x000000FF +#define CPU_DWT_CPICNT_CPICNT_S 0 //***************************************************************************** // @@ -335,9 +335,9 @@ // interrupt processing (for example entry stacking, return unstacking, // pre-emption). An event is emitted on counter overflow (every 256 cycles). // This counter initializes to 0 when it is enabled using CTRL.EXCEVTENA. -#define CPU_DWT_EXCCNT_EXCCNT_W 8 -#define CPU_DWT_EXCCNT_EXCCNT_M 0x000000FF -#define CPU_DWT_EXCCNT_EXCCNT_S 0 +#define CPU_DWT_EXCCNT_EXCCNT_W 8 +#define CPU_DWT_EXCCNT_EXCCNT_M 0x000000FF +#define CPU_DWT_EXCCNT_EXCCNT_S 0 //***************************************************************************** // @@ -353,9 +353,9 @@ // power modes the free-running clock to CPU is gated to minimize power // consumption. This means that the sleep counter will be invalid in these // power modes. -#define CPU_DWT_SLEEPCNT_SLEEPCNT_W 8 -#define CPU_DWT_SLEEPCNT_SLEEPCNT_M 0x000000FF -#define CPU_DWT_SLEEPCNT_SLEEPCNT_S 0 +#define CPU_DWT_SLEEPCNT_SLEEPCNT_W 8 +#define CPU_DWT_SLEEPCNT_SLEEPCNT_M 0x000000FF +#define CPU_DWT_SLEEPCNT_SLEEPCNT_S 0 //***************************************************************************** // @@ -371,9 +371,9 @@ // cycles (i.e. takes four cycles to execute), increments this counter three // times. An event is emitted on counter overflow (every 256 cycles). This // counter initializes to 0 when it is enabled using CTRL.LSUEVTENA. -#define CPU_DWT_LSUCNT_LSUCNT_W 8 -#define CPU_DWT_LSUCNT_LSUCNT_M 0x000000FF -#define CPU_DWT_LSUCNT_LSUCNT_S 0 +#define CPU_DWT_LSUCNT_LSUCNT_W 8 +#define CPU_DWT_LSUCNT_LSUCNT_M 0x000000FF +#define CPU_DWT_LSUCNT_LSUCNT_S 0 //***************************************************************************** // @@ -384,9 +384,9 @@ // // This counts the total number folded instructions. This counter initializes // to 0 when it is enabled using CTRL.FOLDEVTENA. -#define CPU_DWT_FOLDCNT_FOLDCNT_W 8 -#define CPU_DWT_FOLDCNT_FOLDCNT_M 0x000000FF -#define CPU_DWT_FOLDCNT_FOLDCNT_S 0 +#define CPU_DWT_FOLDCNT_FOLDCNT_W 8 +#define CPU_DWT_FOLDCNT_FOLDCNT_M 0x000000FF +#define CPU_DWT_FOLDCNT_FOLDCNT_S 0 //***************************************************************************** // @@ -396,9 +396,9 @@ // Field: [31:0] EIASAMPLE // // Execution instruction address sample, or 0xFFFFFFFF if the core is halted. -#define CPU_DWT_PCSR_EIASAMPLE_W 32 -#define CPU_DWT_PCSR_EIASAMPLE_M 0xFFFFFFFF -#define CPU_DWT_PCSR_EIASAMPLE_S 0 +#define CPU_DWT_PCSR_EIASAMPLE_W 32 +#define CPU_DWT_PCSR_EIASAMPLE_M 0xFFFFFFFF +#define CPU_DWT_PCSR_EIASAMPLE_S 0 //***************************************************************************** // @@ -410,9 +410,9 @@ // Reference value to compare against PC or the data address as given by // FUNCTION0. Comparator 0 can also compare against the value of the PC Sampler // Counter (CYCCNT). -#define CPU_DWT_COMP0_COMP_W 32 -#define CPU_DWT_COMP0_COMP_M 0xFFFFFFFF -#define CPU_DWT_COMP0_COMP_S 0 +#define CPU_DWT_COMP0_COMP_W 32 +#define CPU_DWT_COMP0_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP0_COMP_S 0 //***************************************************************************** // @@ -427,9 +427,9 @@ // slightly more complex to enable matching an address wherever it appears on a // bus. So, if COMP0 is 3, this matches a word access of 0, because 3 would be // within the word. -#define CPU_DWT_MASK0_MASK_W 4 -#define CPU_DWT_MASK0_MASK_M 0x0000000F -#define CPU_DWT_MASK0_MASK_S 0 +#define CPU_DWT_MASK0_MASK_W 4 +#define CPU_DWT_MASK0_MASK_M 0x0000000F +#define CPU_DWT_MASK0_MASK_S 0 //***************************************************************************** // @@ -441,29 +441,29 @@ // This bit is set when the comparator matches, and indicates that the // operation defined by FUNCTION has occurred since this bit was last read. // This bit is cleared on read. -#define CPU_DWT_FUNCTION0_MATCHED 0x01000000 -#define CPU_DWT_FUNCTION0_MATCHED_BITN 24 -#define CPU_DWT_FUNCTION0_MATCHED_M 0x01000000 -#define CPU_DWT_FUNCTION0_MATCHED_S 24 +#define CPU_DWT_FUNCTION0_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION0_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION0_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION0_MATCHED_S 24 // Field: [7] CYCMATCH // // This bit is only available in comparator 0. When set, COMP0 will compare // against the cycle counter (CYCCNT). -#define CPU_DWT_FUNCTION0_CYCMATCH 0x00000080 -#define CPU_DWT_FUNCTION0_CYCMATCH_BITN 7 -#define CPU_DWT_FUNCTION0_CYCMATCH_M 0x00000080 -#define CPU_DWT_FUNCTION0_CYCMATCH_S 7 +#define CPU_DWT_FUNCTION0_CYCMATCH 0x00000080 +#define CPU_DWT_FUNCTION0_CYCMATCH_BITN 7 +#define CPU_DWT_FUNCTION0_CYCMATCH_M 0x00000080 +#define CPU_DWT_FUNCTION0_CYCMATCH_S 7 // Field: [5] EMITRANGE // // Emit range field. This bit permits emitting offset when range match occurs. // PC sampling is not supported when emit range is enabled. // This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. -#define CPU_DWT_FUNCTION0_EMITRANGE 0x00000020 -#define CPU_DWT_FUNCTION0_EMITRANGE_BITN 5 -#define CPU_DWT_FUNCTION0_EMITRANGE_M 0x00000020 -#define CPU_DWT_FUNCTION0_EMITRANGE_S 5 +#define CPU_DWT_FUNCTION0_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION0_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION0_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION0_EMITRANGE_S 5 // Field: [3:0] FUNCTION // @@ -500,9 +500,9 @@ // sampled for the first address of a burst. // Note 3: PC match is not recommended for watchpoints because it stops after // the instruction. It mainly guards and triggers the ETM. -#define CPU_DWT_FUNCTION0_FUNCTION_W 4 -#define CPU_DWT_FUNCTION0_FUNCTION_M 0x0000000F -#define CPU_DWT_FUNCTION0_FUNCTION_S 0 +#define CPU_DWT_FUNCTION0_FUNCTION_W 4 +#define CPU_DWT_FUNCTION0_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION0_FUNCTION_S 0 //***************************************************************************** // @@ -515,9 +515,9 @@ // FUNCTION1. // Comparator 1 can also compare data values. So this register can contain // reference values for data matching. -#define CPU_DWT_COMP1_COMP_W 32 -#define CPU_DWT_COMP1_COMP_M 0xFFFFFFFF -#define CPU_DWT_COMP1_COMP_S 0 +#define CPU_DWT_COMP1_COMP_W 32 +#define CPU_DWT_COMP1_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP1_COMP_S 0 //***************************************************************************** // @@ -532,9 +532,9 @@ // slightly more complex to enable matching an address wherever it appears on a // bus. So, if COMP1 is 3, this matches a word access of 0, because 3 would be // within the word. -#define CPU_DWT_MASK1_MASK_W 4 -#define CPU_DWT_MASK1_MASK_M 0x0000000F -#define CPU_DWT_MASK1_MASK_S 0 +#define CPU_DWT_MASK1_MASK_W 4 +#define CPU_DWT_MASK1_MASK_M 0x0000000F +#define CPU_DWT_MASK1_MASK_S 0 //***************************************************************************** // @@ -546,26 +546,26 @@ // This bit is set when the comparator matches, and indicates that the // operation defined by FUNCTION has occurred since this bit was last read. // This bit is cleared on read. -#define CPU_DWT_FUNCTION1_MATCHED 0x01000000 -#define CPU_DWT_FUNCTION1_MATCHED_BITN 24 -#define CPU_DWT_FUNCTION1_MATCHED_M 0x01000000 -#define CPU_DWT_FUNCTION1_MATCHED_S 24 +#define CPU_DWT_FUNCTION1_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION1_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION1_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION1_MATCHED_S 24 // Field: [19:16] DATAVADDR1 // // Identity of a second linked address comparator for data value matching when // DATAVMATCH == 1 and LNK1ENA == 1. -#define CPU_DWT_FUNCTION1_DATAVADDR1_W 4 -#define CPU_DWT_FUNCTION1_DATAVADDR1_M 0x000F0000 -#define CPU_DWT_FUNCTION1_DATAVADDR1_S 16 +#define CPU_DWT_FUNCTION1_DATAVADDR1_W 4 +#define CPU_DWT_FUNCTION1_DATAVADDR1_M 0x000F0000 +#define CPU_DWT_FUNCTION1_DATAVADDR1_S 16 // Field: [15:12] DATAVADDR0 // // Identity of a linked address comparator for data value matching when // DATAVMATCH == 1. -#define CPU_DWT_FUNCTION1_DATAVADDR0_W 4 -#define CPU_DWT_FUNCTION1_DATAVADDR0_M 0x0000F000 -#define CPU_DWT_FUNCTION1_DATAVADDR0_S 12 +#define CPU_DWT_FUNCTION1_DATAVADDR0_W 4 +#define CPU_DWT_FUNCTION1_DATAVADDR0_M 0x0000F000 +#define CPU_DWT_FUNCTION1_DATAVADDR0_S 12 // Field: [11:10] DATAVSIZE // @@ -575,9 +575,9 @@ // 0x1: Halfword // 0x2: Word // 0x3: Unpredictable. -#define CPU_DWT_FUNCTION1_DATAVSIZE_W 2 -#define CPU_DWT_FUNCTION1_DATAVSIZE_M 0x00000C00 -#define CPU_DWT_FUNCTION1_DATAVSIZE_S 10 +#define CPU_DWT_FUNCTION1_DATAVSIZE_W 2 +#define CPU_DWT_FUNCTION1_DATAVSIZE_M 0x00000C00 +#define CPU_DWT_FUNCTION1_DATAVSIZE_S 10 // Field: [9] LNK1ENA // @@ -585,10 +585,10 @@ // // 0: DATAVADDR1 not supported // 1: DATAVADDR1 supported (enabled) -#define CPU_DWT_FUNCTION1_LNK1ENA 0x00000200 -#define CPU_DWT_FUNCTION1_LNK1ENA_BITN 9 -#define CPU_DWT_FUNCTION1_LNK1ENA_M 0x00000200 -#define CPU_DWT_FUNCTION1_LNK1ENA_S 9 +#define CPU_DWT_FUNCTION1_LNK1ENA 0x00000200 +#define CPU_DWT_FUNCTION1_LNK1ENA_BITN 9 +#define CPU_DWT_FUNCTION1_LNK1ENA_M 0x00000200 +#define CPU_DWT_FUNCTION1_LNK1ENA_S 9 // Field: [8] DATAVMATCH // @@ -601,20 +601,20 @@ // those comparators only provide the address match for the data comparison. // // This bit is only available in comparator 1. -#define CPU_DWT_FUNCTION1_DATAVMATCH 0x00000100 -#define CPU_DWT_FUNCTION1_DATAVMATCH_BITN 8 -#define CPU_DWT_FUNCTION1_DATAVMATCH_M 0x00000100 -#define CPU_DWT_FUNCTION1_DATAVMATCH_S 8 +#define CPU_DWT_FUNCTION1_DATAVMATCH 0x00000100 +#define CPU_DWT_FUNCTION1_DATAVMATCH_BITN 8 +#define CPU_DWT_FUNCTION1_DATAVMATCH_M 0x00000100 +#define CPU_DWT_FUNCTION1_DATAVMATCH_S 8 // Field: [5] EMITRANGE // // Emit range field. This bit permits emitting offset when range match occurs. // PC sampling is not supported when emit range is enabled. // This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. -#define CPU_DWT_FUNCTION1_EMITRANGE 0x00000020 -#define CPU_DWT_FUNCTION1_EMITRANGE_BITN 5 -#define CPU_DWT_FUNCTION1_EMITRANGE_M 0x00000020 -#define CPU_DWT_FUNCTION1_EMITRANGE_S 5 +#define CPU_DWT_FUNCTION1_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION1_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION1_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION1_EMITRANGE_S 5 // Field: [3:0] FUNCTION // @@ -660,9 +660,9 @@ // reading DATAVMATCH. If it is not settable then data matching is unavailable. // Note 5: PC match is not recommended for watchpoints because it stops after // the instruction. It mainly guards and triggers the ETM. -#define CPU_DWT_FUNCTION1_FUNCTION_W 4 -#define CPU_DWT_FUNCTION1_FUNCTION_M 0x0000000F -#define CPU_DWT_FUNCTION1_FUNCTION_S 0 +#define CPU_DWT_FUNCTION1_FUNCTION_W 4 +#define CPU_DWT_FUNCTION1_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION1_FUNCTION_S 0 //***************************************************************************** // @@ -673,9 +673,9 @@ // // Reference value to compare against PC or the data address as given by // FUNCTION2. -#define CPU_DWT_COMP2_COMP_W 32 -#define CPU_DWT_COMP2_COMP_M 0xFFFFFFFF -#define CPU_DWT_COMP2_COMP_S 0 +#define CPU_DWT_COMP2_COMP_W 32 +#define CPU_DWT_COMP2_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP2_COMP_S 0 //***************************************************************************** // @@ -690,9 +690,9 @@ // slightly more complex to enable matching an address wherever it appears on a // bus. So, if COMP2 is 3, this matches a word access of 0, because 3 would be // within the word. -#define CPU_DWT_MASK2_MASK_W 4 -#define CPU_DWT_MASK2_MASK_M 0x0000000F -#define CPU_DWT_MASK2_MASK_S 0 +#define CPU_DWT_MASK2_MASK_W 4 +#define CPU_DWT_MASK2_MASK_M 0x0000000F +#define CPU_DWT_MASK2_MASK_S 0 //***************************************************************************** // @@ -704,20 +704,20 @@ // This bit is set when the comparator matches, and indicates that the // operation defined by FUNCTION has occurred since this bit was last read. // This bit is cleared on read. -#define CPU_DWT_FUNCTION2_MATCHED 0x01000000 -#define CPU_DWT_FUNCTION2_MATCHED_BITN 24 -#define CPU_DWT_FUNCTION2_MATCHED_M 0x01000000 -#define CPU_DWT_FUNCTION2_MATCHED_S 24 +#define CPU_DWT_FUNCTION2_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION2_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION2_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION2_MATCHED_S 24 // Field: [5] EMITRANGE // // Emit range field. This bit permits emitting offset when range match occurs. // PC sampling is not supported when emit range is enabled. // This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. -#define CPU_DWT_FUNCTION2_EMITRANGE 0x00000020 -#define CPU_DWT_FUNCTION2_EMITRANGE_BITN 5 -#define CPU_DWT_FUNCTION2_EMITRANGE_M 0x00000020 -#define CPU_DWT_FUNCTION2_EMITRANGE_S 5 +#define CPU_DWT_FUNCTION2_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION2_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION2_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION2_EMITRANGE_S 5 // Field: [3:0] FUNCTION // @@ -754,9 +754,9 @@ // sampled for the first address of a burst. // Note 3: PC match is not recommended for watchpoints because it stops after // the instruction. It mainly guards and triggers the ETM. -#define CPU_DWT_FUNCTION2_FUNCTION_W 4 -#define CPU_DWT_FUNCTION2_FUNCTION_M 0x0000000F -#define CPU_DWT_FUNCTION2_FUNCTION_S 0 +#define CPU_DWT_FUNCTION2_FUNCTION_W 4 +#define CPU_DWT_FUNCTION2_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION2_FUNCTION_S 0 //***************************************************************************** // @@ -767,9 +767,9 @@ // // Reference value to compare against PC or the data address as given by // FUNCTION3. -#define CPU_DWT_COMP3_COMP_W 32 -#define CPU_DWT_COMP3_COMP_M 0xFFFFFFFF -#define CPU_DWT_COMP3_COMP_S 0 +#define CPU_DWT_COMP3_COMP_W 32 +#define CPU_DWT_COMP3_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP3_COMP_S 0 //***************************************************************************** // @@ -784,9 +784,9 @@ // slightly more complex to enable matching an address wherever it appears on a // bus. So, if COMP3 is 3, this matches a word access of 0, because 3 would be // within the word. -#define CPU_DWT_MASK3_MASK_W 4 -#define CPU_DWT_MASK3_MASK_M 0x0000000F -#define CPU_DWT_MASK3_MASK_S 0 +#define CPU_DWT_MASK3_MASK_W 4 +#define CPU_DWT_MASK3_MASK_M 0x0000000F +#define CPU_DWT_MASK3_MASK_S 0 //***************************************************************************** // @@ -798,20 +798,20 @@ // This bit is set when the comparator matches, and indicates that the // operation defined by FUNCTION has occurred since this bit was last read. // This bit is cleared on read. -#define CPU_DWT_FUNCTION3_MATCHED 0x01000000 -#define CPU_DWT_FUNCTION3_MATCHED_BITN 24 -#define CPU_DWT_FUNCTION3_MATCHED_M 0x01000000 -#define CPU_DWT_FUNCTION3_MATCHED_S 24 +#define CPU_DWT_FUNCTION3_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION3_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION3_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION3_MATCHED_S 24 // Field: [5] EMITRANGE // // Emit range field. This bit permits emitting offset when range match occurs. // PC sampling is not supported when emit range is enabled. // This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. -#define CPU_DWT_FUNCTION3_EMITRANGE 0x00000020 -#define CPU_DWT_FUNCTION3_EMITRANGE_BITN 5 -#define CPU_DWT_FUNCTION3_EMITRANGE_M 0x00000020 -#define CPU_DWT_FUNCTION3_EMITRANGE_S 5 +#define CPU_DWT_FUNCTION3_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION3_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION3_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION3_EMITRANGE_S 5 // Field: [3:0] FUNCTION // @@ -848,9 +848,8 @@ // sampled for the first address of a burst. // Note 3: PC match is not recommended for watchpoints because it stops after // the instruction. It mainly guards and triggers the ETM. -#define CPU_DWT_FUNCTION3_FUNCTION_W 4 -#define CPU_DWT_FUNCTION3_FUNCTION_M 0x0000000F -#define CPU_DWT_FUNCTION3_FUNCTION_S 0 - +#define CPU_DWT_FUNCTION3_FUNCTION_W 4 +#define CPU_DWT_FUNCTION3_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION3_FUNCTION_S 0 #endif // __CPU_DWT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_fpb.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_fpb.h index f70d8bd..712f034 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_fpb.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_fpb.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_cpu_fpb_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_cpu_fpb_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CPU_FPB_H__ #define __HW_CPU_FPB_H__ @@ -44,34 +44,34 @@ // //***************************************************************************** // Control -#define CPU_FPB_O_CTRL 0x00000000 +#define CPU_FPB_O_CTRL 0x00000000 // Remap -#define CPU_FPB_O_REMAP 0x00000004 +#define CPU_FPB_O_REMAP 0x00000004 // Comparator 0 -#define CPU_FPB_O_COMP0 0x00000008 +#define CPU_FPB_O_COMP0 0x00000008 // Comparator 1 -#define CPU_FPB_O_COMP1 0x0000000C +#define CPU_FPB_O_COMP1 0x0000000C // Comparator 2 -#define CPU_FPB_O_COMP2 0x00000010 +#define CPU_FPB_O_COMP2 0x00000010 // Comparator 3 -#define CPU_FPB_O_COMP3 0x00000014 +#define CPU_FPB_O_COMP3 0x00000014 // Comparator 4 -#define CPU_FPB_O_COMP4 0x00000018 +#define CPU_FPB_O_COMP4 0x00000018 // Comparator 5 -#define CPU_FPB_O_COMP5 0x0000001C +#define CPU_FPB_O_COMP5 0x0000001C // Comparator 6 -#define CPU_FPB_O_COMP6 0x00000020 +#define CPU_FPB_O_COMP6 0x00000020 // Comparator 7 -#define CPU_FPB_O_COMP7 0x00000024 +#define CPU_FPB_O_COMP7 0x00000024 //***************************************************************************** // @@ -84,9 +84,9 @@ // Where less than sixteen code comparators are provided, the bank count is // zero, and the number present indicated by NUM_CODE1. This read only field // contains 3'b000 to indicate 0 banks for Cortex-M processor. -#define CPU_FPB_CTRL_NUM_CODE2_W 2 -#define CPU_FPB_CTRL_NUM_CODE2_M 0x00003000 -#define CPU_FPB_CTRL_NUM_CODE2_S 12 +#define CPU_FPB_CTRL_NUM_CODE2_W 2 +#define CPU_FPB_CTRL_NUM_CODE2_M 0x00003000 +#define CPU_FPB_CTRL_NUM_CODE2_S 12 // Field: [11:8] NUM_LIT // @@ -94,9 +94,9 @@ // // 0x0: No literal slots // 0x2: Two literal slots -#define CPU_FPB_CTRL_NUM_LIT_W 4 -#define CPU_FPB_CTRL_NUM_LIT_M 0x00000F00 -#define CPU_FPB_CTRL_NUM_LIT_S 8 +#define CPU_FPB_CTRL_NUM_LIT_W 4 +#define CPU_FPB_CTRL_NUM_LIT_M 0x00000F00 +#define CPU_FPB_CTRL_NUM_LIT_S 8 // Field: [7:4] NUM_CODE1 // @@ -105,18 +105,18 @@ // 0x0: No code slots // 0x2: Two code slots // 0x6: Six code slots -#define CPU_FPB_CTRL_NUM_CODE1_W 4 -#define CPU_FPB_CTRL_NUM_CODE1_M 0x000000F0 -#define CPU_FPB_CTRL_NUM_CODE1_S 4 +#define CPU_FPB_CTRL_NUM_CODE1_W 4 +#define CPU_FPB_CTRL_NUM_CODE1_M 0x000000F0 +#define CPU_FPB_CTRL_NUM_CODE1_S 4 // Field: [1] KEY // // Key field. In order to write to this register, this bit-field must be // written to '1'. This bit always reads 0. -#define CPU_FPB_CTRL_KEY 0x00000002 -#define CPU_FPB_CTRL_KEY_BITN 1 -#define CPU_FPB_CTRL_KEY_M 0x00000002 -#define CPU_FPB_CTRL_KEY_S 1 +#define CPU_FPB_CTRL_KEY 0x00000002 +#define CPU_FPB_CTRL_KEY_BITN 1 +#define CPU_FPB_CTRL_KEY_M 0x00000002 +#define CPU_FPB_CTRL_KEY_S 1 // Field: [0] ENABLE // @@ -124,10 +124,10 @@ // // 0x0: Flash patch unit disabled // 0x1: Flash patch unit enabled -#define CPU_FPB_CTRL_ENABLE 0x00000001 -#define CPU_FPB_CTRL_ENABLE_BITN 0 -#define CPU_FPB_CTRL_ENABLE_M 0x00000001 -#define CPU_FPB_CTRL_ENABLE_S 0 +#define CPU_FPB_CTRL_ENABLE 0x00000001 +#define CPU_FPB_CTRL_ENABLE_BITN 0 +#define CPU_FPB_CTRL_ENABLE_M 0x00000001 +#define CPU_FPB_CTRL_ENABLE_S 0 //***************************************************************************** // @@ -137,9 +137,9 @@ // Field: [28:5] REMAP // // Remap base address field. -#define CPU_FPB_REMAP_REMAP_W 24 -#define CPU_FPB_REMAP_REMAP_M 0x1FFFFFE0 -#define CPU_FPB_REMAP_REMAP_S 5 +#define CPU_FPB_REMAP_REMAP_W 24 +#define CPU_FPB_REMAP_REMAP_M 0x1FFFFFE0 +#define CPU_FPB_REMAP_REMAP_S 5 //***************************************************************************** // @@ -155,16 +155,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP0_REPLACE_W 2 -#define CPU_FPB_COMP0_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP0_REPLACE_S 30 +#define CPU_FPB_COMP0_REPLACE_W 2 +#define CPU_FPB_COMP0_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP0_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP0_COMP_W 27 -#define CPU_FPB_COMP0_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP0_COMP_S 2 +#define CPU_FPB_COMP0_COMP_W 27 +#define CPU_FPB_COMP0_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP0_COMP_S 2 // Field: [0] ENABLE // @@ -173,10 +173,10 @@ // // 0x0: Compare and remap for comparator 0 disabled // 0x1: Compare and remap for comparator 0 enabled -#define CPU_FPB_COMP0_ENABLE 0x00000001 -#define CPU_FPB_COMP0_ENABLE_BITN 0 -#define CPU_FPB_COMP0_ENABLE_M 0x00000001 -#define CPU_FPB_COMP0_ENABLE_S 0 +#define CPU_FPB_COMP0_ENABLE 0x00000001 +#define CPU_FPB_COMP0_ENABLE_BITN 0 +#define CPU_FPB_COMP0_ENABLE_M 0x00000001 +#define CPU_FPB_COMP0_ENABLE_S 0 //***************************************************************************** // @@ -192,16 +192,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP1_REPLACE_W 2 -#define CPU_FPB_COMP1_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP1_REPLACE_S 30 +#define CPU_FPB_COMP1_REPLACE_W 2 +#define CPU_FPB_COMP1_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP1_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP1_COMP_W 27 -#define CPU_FPB_COMP1_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP1_COMP_S 2 +#define CPU_FPB_COMP1_COMP_W 27 +#define CPU_FPB_COMP1_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP1_COMP_S 2 // Field: [0] ENABLE // @@ -210,10 +210,10 @@ // // 0x0: Compare and remap for comparator 1 disabled // 0x1: Compare and remap for comparator 1 enabled -#define CPU_FPB_COMP1_ENABLE 0x00000001 -#define CPU_FPB_COMP1_ENABLE_BITN 0 -#define CPU_FPB_COMP1_ENABLE_M 0x00000001 -#define CPU_FPB_COMP1_ENABLE_S 0 +#define CPU_FPB_COMP1_ENABLE 0x00000001 +#define CPU_FPB_COMP1_ENABLE_BITN 0 +#define CPU_FPB_COMP1_ENABLE_M 0x00000001 +#define CPU_FPB_COMP1_ENABLE_S 0 //***************************************************************************** // @@ -229,16 +229,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP2_REPLACE_W 2 -#define CPU_FPB_COMP2_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP2_REPLACE_S 30 +#define CPU_FPB_COMP2_REPLACE_W 2 +#define CPU_FPB_COMP2_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP2_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP2_COMP_W 27 -#define CPU_FPB_COMP2_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP2_COMP_S 2 +#define CPU_FPB_COMP2_COMP_W 27 +#define CPU_FPB_COMP2_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP2_COMP_S 2 // Field: [0] ENABLE // @@ -247,10 +247,10 @@ // // 0x0: Compare and remap for comparator 2 disabled // 0x1: Compare and remap for comparator 2 enabled -#define CPU_FPB_COMP2_ENABLE 0x00000001 -#define CPU_FPB_COMP2_ENABLE_BITN 0 -#define CPU_FPB_COMP2_ENABLE_M 0x00000001 -#define CPU_FPB_COMP2_ENABLE_S 0 +#define CPU_FPB_COMP2_ENABLE 0x00000001 +#define CPU_FPB_COMP2_ENABLE_BITN 0 +#define CPU_FPB_COMP2_ENABLE_M 0x00000001 +#define CPU_FPB_COMP2_ENABLE_S 0 //***************************************************************************** // @@ -266,16 +266,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP3_REPLACE_W 2 -#define CPU_FPB_COMP3_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP3_REPLACE_S 30 +#define CPU_FPB_COMP3_REPLACE_W 2 +#define CPU_FPB_COMP3_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP3_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP3_COMP_W 27 -#define CPU_FPB_COMP3_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP3_COMP_S 2 +#define CPU_FPB_COMP3_COMP_W 27 +#define CPU_FPB_COMP3_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP3_COMP_S 2 // Field: [0] ENABLE // @@ -284,10 +284,10 @@ // // 0x0: Compare and remap for comparator 3 disabled // 0x1: Compare and remap for comparator 3 enabled -#define CPU_FPB_COMP3_ENABLE 0x00000001 -#define CPU_FPB_COMP3_ENABLE_BITN 0 -#define CPU_FPB_COMP3_ENABLE_M 0x00000001 -#define CPU_FPB_COMP3_ENABLE_S 0 +#define CPU_FPB_COMP3_ENABLE 0x00000001 +#define CPU_FPB_COMP3_ENABLE_BITN 0 +#define CPU_FPB_COMP3_ENABLE_M 0x00000001 +#define CPU_FPB_COMP3_ENABLE_S 0 //***************************************************************************** // @@ -303,16 +303,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP4_REPLACE_W 2 -#define CPU_FPB_COMP4_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP4_REPLACE_S 30 +#define CPU_FPB_COMP4_REPLACE_W 2 +#define CPU_FPB_COMP4_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP4_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP4_COMP_W 27 -#define CPU_FPB_COMP4_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP4_COMP_S 2 +#define CPU_FPB_COMP4_COMP_W 27 +#define CPU_FPB_COMP4_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP4_COMP_S 2 // Field: [0] ENABLE // @@ -321,10 +321,10 @@ // // 0x0: Compare and remap for comparator 4 disabled // 0x1: Compare and remap for comparator 4 enabled -#define CPU_FPB_COMP4_ENABLE 0x00000001 -#define CPU_FPB_COMP4_ENABLE_BITN 0 -#define CPU_FPB_COMP4_ENABLE_M 0x00000001 -#define CPU_FPB_COMP4_ENABLE_S 0 +#define CPU_FPB_COMP4_ENABLE 0x00000001 +#define CPU_FPB_COMP4_ENABLE_BITN 0 +#define CPU_FPB_COMP4_ENABLE_M 0x00000001 +#define CPU_FPB_COMP4_ENABLE_S 0 //***************************************************************************** // @@ -340,16 +340,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP5_REPLACE_W 2 -#define CPU_FPB_COMP5_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP5_REPLACE_S 30 +#define CPU_FPB_COMP5_REPLACE_W 2 +#define CPU_FPB_COMP5_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP5_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP5_COMP_W 27 -#define CPU_FPB_COMP5_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP5_COMP_S 2 +#define CPU_FPB_COMP5_COMP_W 27 +#define CPU_FPB_COMP5_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP5_COMP_S 2 // Field: [0] ENABLE // @@ -358,10 +358,10 @@ // // 0x0: Compare and remap for comparator 5 disabled // 0x1: Compare and remap for comparator 5 enabled -#define CPU_FPB_COMP5_ENABLE 0x00000001 -#define CPU_FPB_COMP5_ENABLE_BITN 0 -#define CPU_FPB_COMP5_ENABLE_M 0x00000001 -#define CPU_FPB_COMP5_ENABLE_S 0 +#define CPU_FPB_COMP5_ENABLE 0x00000001 +#define CPU_FPB_COMP5_ENABLE_BITN 0 +#define CPU_FPB_COMP5_ENABLE_M 0x00000001 +#define CPU_FPB_COMP5_ENABLE_S 0 //***************************************************************************** // @@ -378,16 +378,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP6_REPLACE_W 2 -#define CPU_FPB_COMP6_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP6_REPLACE_S 30 +#define CPU_FPB_COMP6_REPLACE_W 2 +#define CPU_FPB_COMP6_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP6_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP6_COMP_W 27 -#define CPU_FPB_COMP6_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP6_COMP_S 2 +#define CPU_FPB_COMP6_COMP_W 27 +#define CPU_FPB_COMP6_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP6_COMP_S 2 // Field: [0] ENABLE // @@ -396,10 +396,10 @@ // // 0x0: Compare and remap for comparator 6 disabled // 0x1: Compare and remap for comparator 6 enabled -#define CPU_FPB_COMP6_ENABLE 0x00000001 -#define CPU_FPB_COMP6_ENABLE_BITN 0 -#define CPU_FPB_COMP6_ENABLE_M 0x00000001 -#define CPU_FPB_COMP6_ENABLE_S 0 +#define CPU_FPB_COMP6_ENABLE 0x00000001 +#define CPU_FPB_COMP6_ENABLE_BITN 0 +#define CPU_FPB_COMP6_ENABLE_M 0x00000001 +#define CPU_FPB_COMP6_ENABLE_S 0 //***************************************************************************** // @@ -416,16 +416,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP7_REPLACE_W 2 -#define CPU_FPB_COMP7_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP7_REPLACE_S 30 +#define CPU_FPB_COMP7_REPLACE_W 2 +#define CPU_FPB_COMP7_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP7_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP7_COMP_W 27 -#define CPU_FPB_COMP7_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP7_COMP_S 2 +#define CPU_FPB_COMP7_COMP_W 27 +#define CPU_FPB_COMP7_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP7_COMP_S 2 // Field: [0] ENABLE // @@ -434,10 +434,9 @@ // // 0x0: Compare and remap for comparator 7 disabled // 0x1: Compare and remap for comparator 7 enabled -#define CPU_FPB_COMP7_ENABLE 0x00000001 -#define CPU_FPB_COMP7_ENABLE_BITN 0 -#define CPU_FPB_COMP7_ENABLE_M 0x00000001 -#define CPU_FPB_COMP7_ENABLE_S 0 - +#define CPU_FPB_COMP7_ENABLE 0x00000001 +#define CPU_FPB_COMP7_ENABLE_BITN 0 +#define CPU_FPB_COMP7_ENABLE_M 0x00000001 +#define CPU_FPB_COMP7_ENABLE_S 0 #endif // __CPU_FPB__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_itm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_itm.h index 9996da5..d64c35d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_itm.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_itm.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_cpu_itm_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_cpu_itm_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CPU_ITM_H__ #define __HW_CPU_ITM_H__ @@ -44,115 +44,115 @@ // //***************************************************************************** // Stimulus Port 0 -#define CPU_ITM_O_STIM0 0x00000000 +#define CPU_ITM_O_STIM0 0x00000000 // Stimulus Port 1 -#define CPU_ITM_O_STIM1 0x00000004 +#define CPU_ITM_O_STIM1 0x00000004 // Stimulus Port 2 -#define CPU_ITM_O_STIM2 0x00000008 +#define CPU_ITM_O_STIM2 0x00000008 // Stimulus Port 3 -#define CPU_ITM_O_STIM3 0x0000000C +#define CPU_ITM_O_STIM3 0x0000000C // Stimulus Port 4 -#define CPU_ITM_O_STIM4 0x00000010 +#define CPU_ITM_O_STIM4 0x00000010 // Stimulus Port 5 -#define CPU_ITM_O_STIM5 0x00000014 +#define CPU_ITM_O_STIM5 0x00000014 // Stimulus Port 6 -#define CPU_ITM_O_STIM6 0x00000018 +#define CPU_ITM_O_STIM6 0x00000018 // Stimulus Port 7 -#define CPU_ITM_O_STIM7 0x0000001C +#define CPU_ITM_O_STIM7 0x0000001C // Stimulus Port 8 -#define CPU_ITM_O_STIM8 0x00000020 +#define CPU_ITM_O_STIM8 0x00000020 // Stimulus Port 9 -#define CPU_ITM_O_STIM9 0x00000024 +#define CPU_ITM_O_STIM9 0x00000024 // Stimulus Port 10 -#define CPU_ITM_O_STIM10 0x00000028 +#define CPU_ITM_O_STIM10 0x00000028 // Stimulus Port 11 -#define CPU_ITM_O_STIM11 0x0000002C +#define CPU_ITM_O_STIM11 0x0000002C // Stimulus Port 12 -#define CPU_ITM_O_STIM12 0x00000030 +#define CPU_ITM_O_STIM12 0x00000030 // Stimulus Port 13 -#define CPU_ITM_O_STIM13 0x00000034 +#define CPU_ITM_O_STIM13 0x00000034 // Stimulus Port 14 -#define CPU_ITM_O_STIM14 0x00000038 +#define CPU_ITM_O_STIM14 0x00000038 // Stimulus Port 15 -#define CPU_ITM_O_STIM15 0x0000003C +#define CPU_ITM_O_STIM15 0x0000003C // Stimulus Port 16 -#define CPU_ITM_O_STIM16 0x00000040 +#define CPU_ITM_O_STIM16 0x00000040 // Stimulus Port 17 -#define CPU_ITM_O_STIM17 0x00000044 +#define CPU_ITM_O_STIM17 0x00000044 // Stimulus Port 18 -#define CPU_ITM_O_STIM18 0x00000048 +#define CPU_ITM_O_STIM18 0x00000048 // Stimulus Port 19 -#define CPU_ITM_O_STIM19 0x0000004C +#define CPU_ITM_O_STIM19 0x0000004C // Stimulus Port 20 -#define CPU_ITM_O_STIM20 0x00000050 +#define CPU_ITM_O_STIM20 0x00000050 // Stimulus Port 21 -#define CPU_ITM_O_STIM21 0x00000054 +#define CPU_ITM_O_STIM21 0x00000054 // Stimulus Port 22 -#define CPU_ITM_O_STIM22 0x00000058 +#define CPU_ITM_O_STIM22 0x00000058 // Stimulus Port 23 -#define CPU_ITM_O_STIM23 0x0000005C +#define CPU_ITM_O_STIM23 0x0000005C // Stimulus Port 24 -#define CPU_ITM_O_STIM24 0x00000060 +#define CPU_ITM_O_STIM24 0x00000060 // Stimulus Port 25 -#define CPU_ITM_O_STIM25 0x00000064 +#define CPU_ITM_O_STIM25 0x00000064 // Stimulus Port 26 -#define CPU_ITM_O_STIM26 0x00000068 +#define CPU_ITM_O_STIM26 0x00000068 // Stimulus Port 27 -#define CPU_ITM_O_STIM27 0x0000006C +#define CPU_ITM_O_STIM27 0x0000006C // Stimulus Port 28 -#define CPU_ITM_O_STIM28 0x00000070 +#define CPU_ITM_O_STIM28 0x00000070 // Stimulus Port 29 -#define CPU_ITM_O_STIM29 0x00000074 +#define CPU_ITM_O_STIM29 0x00000074 // Stimulus Port 30 -#define CPU_ITM_O_STIM30 0x00000078 +#define CPU_ITM_O_STIM30 0x00000078 // Stimulus Port 31 -#define CPU_ITM_O_STIM31 0x0000007C +#define CPU_ITM_O_STIM31 0x0000007C // Trace Enable -#define CPU_ITM_O_TER 0x00000E00 +#define CPU_ITM_O_TER 0x00000E00 // Trace Privilege -#define CPU_ITM_O_TPR 0x00000E40 +#define CPU_ITM_O_TPR 0x00000E40 // Trace Control -#define CPU_ITM_O_TCR 0x00000E80 +#define CPU_ITM_O_TCR 0x00000E80 // Lock Access -#define CPU_ITM_O_LAR 0x00000FB0 +#define CPU_ITM_O_LAR 0x00000FB0 // Lock Status -#define CPU_ITM_O_LSR 0x00000FB4 +#define CPU_ITM_O_LSR 0x00000FB4 //***************************************************************************** // @@ -167,9 +167,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM0_STIM0_W 32 -#define CPU_ITM_STIM0_STIM0_M 0xFFFFFFFF -#define CPU_ITM_STIM0_STIM0_S 0 +#define CPU_ITM_STIM0_STIM0_W 32 +#define CPU_ITM_STIM0_STIM0_M 0xFFFFFFFF +#define CPU_ITM_STIM0_STIM0_S 0 //***************************************************************************** // @@ -184,9 +184,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM1_STIM1_W 32 -#define CPU_ITM_STIM1_STIM1_M 0xFFFFFFFF -#define CPU_ITM_STIM1_STIM1_S 0 +#define CPU_ITM_STIM1_STIM1_W 32 +#define CPU_ITM_STIM1_STIM1_M 0xFFFFFFFF +#define CPU_ITM_STIM1_STIM1_S 0 //***************************************************************************** // @@ -201,9 +201,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM2_STIM2_W 32 -#define CPU_ITM_STIM2_STIM2_M 0xFFFFFFFF -#define CPU_ITM_STIM2_STIM2_S 0 +#define CPU_ITM_STIM2_STIM2_W 32 +#define CPU_ITM_STIM2_STIM2_M 0xFFFFFFFF +#define CPU_ITM_STIM2_STIM2_S 0 //***************************************************************************** // @@ -218,9 +218,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM3_STIM3_W 32 -#define CPU_ITM_STIM3_STIM3_M 0xFFFFFFFF -#define CPU_ITM_STIM3_STIM3_S 0 +#define CPU_ITM_STIM3_STIM3_W 32 +#define CPU_ITM_STIM3_STIM3_M 0xFFFFFFFF +#define CPU_ITM_STIM3_STIM3_S 0 //***************************************************************************** // @@ -235,9 +235,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM4_STIM4_W 32 -#define CPU_ITM_STIM4_STIM4_M 0xFFFFFFFF -#define CPU_ITM_STIM4_STIM4_S 0 +#define CPU_ITM_STIM4_STIM4_W 32 +#define CPU_ITM_STIM4_STIM4_M 0xFFFFFFFF +#define CPU_ITM_STIM4_STIM4_S 0 //***************************************************************************** // @@ -252,9 +252,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM5_STIM5_W 32 -#define CPU_ITM_STIM5_STIM5_M 0xFFFFFFFF -#define CPU_ITM_STIM5_STIM5_S 0 +#define CPU_ITM_STIM5_STIM5_W 32 +#define CPU_ITM_STIM5_STIM5_M 0xFFFFFFFF +#define CPU_ITM_STIM5_STIM5_S 0 //***************************************************************************** // @@ -269,9 +269,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM6_STIM6_W 32 -#define CPU_ITM_STIM6_STIM6_M 0xFFFFFFFF -#define CPU_ITM_STIM6_STIM6_S 0 +#define CPU_ITM_STIM6_STIM6_W 32 +#define CPU_ITM_STIM6_STIM6_M 0xFFFFFFFF +#define CPU_ITM_STIM6_STIM6_S 0 //***************************************************************************** // @@ -286,9 +286,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM7_STIM7_W 32 -#define CPU_ITM_STIM7_STIM7_M 0xFFFFFFFF -#define CPU_ITM_STIM7_STIM7_S 0 +#define CPU_ITM_STIM7_STIM7_W 32 +#define CPU_ITM_STIM7_STIM7_M 0xFFFFFFFF +#define CPU_ITM_STIM7_STIM7_S 0 //***************************************************************************** // @@ -303,9 +303,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM8_STIM8_W 32 -#define CPU_ITM_STIM8_STIM8_M 0xFFFFFFFF -#define CPU_ITM_STIM8_STIM8_S 0 +#define CPU_ITM_STIM8_STIM8_W 32 +#define CPU_ITM_STIM8_STIM8_M 0xFFFFFFFF +#define CPU_ITM_STIM8_STIM8_S 0 //***************************************************************************** // @@ -320,9 +320,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM9_STIM9_W 32 -#define CPU_ITM_STIM9_STIM9_M 0xFFFFFFFF -#define CPU_ITM_STIM9_STIM9_S 0 +#define CPU_ITM_STIM9_STIM9_W 32 +#define CPU_ITM_STIM9_STIM9_M 0xFFFFFFFF +#define CPU_ITM_STIM9_STIM9_S 0 //***************************************************************************** // @@ -337,9 +337,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM10_STIM10_W 32 -#define CPU_ITM_STIM10_STIM10_M 0xFFFFFFFF -#define CPU_ITM_STIM10_STIM10_S 0 +#define CPU_ITM_STIM10_STIM10_W 32 +#define CPU_ITM_STIM10_STIM10_M 0xFFFFFFFF +#define CPU_ITM_STIM10_STIM10_S 0 //***************************************************************************** // @@ -354,9 +354,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM11_STIM11_W 32 -#define CPU_ITM_STIM11_STIM11_M 0xFFFFFFFF -#define CPU_ITM_STIM11_STIM11_S 0 +#define CPU_ITM_STIM11_STIM11_W 32 +#define CPU_ITM_STIM11_STIM11_M 0xFFFFFFFF +#define CPU_ITM_STIM11_STIM11_S 0 //***************************************************************************** // @@ -371,9 +371,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM12_STIM12_W 32 -#define CPU_ITM_STIM12_STIM12_M 0xFFFFFFFF -#define CPU_ITM_STIM12_STIM12_S 0 +#define CPU_ITM_STIM12_STIM12_W 32 +#define CPU_ITM_STIM12_STIM12_M 0xFFFFFFFF +#define CPU_ITM_STIM12_STIM12_S 0 //***************************************************************************** // @@ -388,9 +388,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM13_STIM13_W 32 -#define CPU_ITM_STIM13_STIM13_M 0xFFFFFFFF -#define CPU_ITM_STIM13_STIM13_S 0 +#define CPU_ITM_STIM13_STIM13_W 32 +#define CPU_ITM_STIM13_STIM13_M 0xFFFFFFFF +#define CPU_ITM_STIM13_STIM13_S 0 //***************************************************************************** // @@ -405,9 +405,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM14_STIM14_W 32 -#define CPU_ITM_STIM14_STIM14_M 0xFFFFFFFF -#define CPU_ITM_STIM14_STIM14_S 0 +#define CPU_ITM_STIM14_STIM14_W 32 +#define CPU_ITM_STIM14_STIM14_M 0xFFFFFFFF +#define CPU_ITM_STIM14_STIM14_S 0 //***************************************************************************** // @@ -422,9 +422,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM15_STIM15_W 32 -#define CPU_ITM_STIM15_STIM15_M 0xFFFFFFFF -#define CPU_ITM_STIM15_STIM15_S 0 +#define CPU_ITM_STIM15_STIM15_W 32 +#define CPU_ITM_STIM15_STIM15_M 0xFFFFFFFF +#define CPU_ITM_STIM15_STIM15_S 0 //***************************************************************************** // @@ -439,9 +439,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM16_STIM16_W 32 -#define CPU_ITM_STIM16_STIM16_M 0xFFFFFFFF -#define CPU_ITM_STIM16_STIM16_S 0 +#define CPU_ITM_STIM16_STIM16_W 32 +#define CPU_ITM_STIM16_STIM16_M 0xFFFFFFFF +#define CPU_ITM_STIM16_STIM16_S 0 //***************************************************************************** // @@ -456,9 +456,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM17_STIM17_W 32 -#define CPU_ITM_STIM17_STIM17_M 0xFFFFFFFF -#define CPU_ITM_STIM17_STIM17_S 0 +#define CPU_ITM_STIM17_STIM17_W 32 +#define CPU_ITM_STIM17_STIM17_M 0xFFFFFFFF +#define CPU_ITM_STIM17_STIM17_S 0 //***************************************************************************** // @@ -473,9 +473,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM18_STIM18_W 32 -#define CPU_ITM_STIM18_STIM18_M 0xFFFFFFFF -#define CPU_ITM_STIM18_STIM18_S 0 +#define CPU_ITM_STIM18_STIM18_W 32 +#define CPU_ITM_STIM18_STIM18_M 0xFFFFFFFF +#define CPU_ITM_STIM18_STIM18_S 0 //***************************************************************************** // @@ -490,9 +490,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM19_STIM19_W 32 -#define CPU_ITM_STIM19_STIM19_M 0xFFFFFFFF -#define CPU_ITM_STIM19_STIM19_S 0 +#define CPU_ITM_STIM19_STIM19_W 32 +#define CPU_ITM_STIM19_STIM19_M 0xFFFFFFFF +#define CPU_ITM_STIM19_STIM19_S 0 //***************************************************************************** // @@ -507,9 +507,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM20_STIM20_W 32 -#define CPU_ITM_STIM20_STIM20_M 0xFFFFFFFF -#define CPU_ITM_STIM20_STIM20_S 0 +#define CPU_ITM_STIM20_STIM20_W 32 +#define CPU_ITM_STIM20_STIM20_M 0xFFFFFFFF +#define CPU_ITM_STIM20_STIM20_S 0 //***************************************************************************** // @@ -524,9 +524,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM21_STIM21_W 32 -#define CPU_ITM_STIM21_STIM21_M 0xFFFFFFFF -#define CPU_ITM_STIM21_STIM21_S 0 +#define CPU_ITM_STIM21_STIM21_W 32 +#define CPU_ITM_STIM21_STIM21_M 0xFFFFFFFF +#define CPU_ITM_STIM21_STIM21_S 0 //***************************************************************************** // @@ -541,9 +541,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM22_STIM22_W 32 -#define CPU_ITM_STIM22_STIM22_M 0xFFFFFFFF -#define CPU_ITM_STIM22_STIM22_S 0 +#define CPU_ITM_STIM22_STIM22_W 32 +#define CPU_ITM_STIM22_STIM22_M 0xFFFFFFFF +#define CPU_ITM_STIM22_STIM22_S 0 //***************************************************************************** // @@ -558,9 +558,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM23_STIM23_W 32 -#define CPU_ITM_STIM23_STIM23_M 0xFFFFFFFF -#define CPU_ITM_STIM23_STIM23_S 0 +#define CPU_ITM_STIM23_STIM23_W 32 +#define CPU_ITM_STIM23_STIM23_M 0xFFFFFFFF +#define CPU_ITM_STIM23_STIM23_S 0 //***************************************************************************** // @@ -575,9 +575,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM24_STIM24_W 32 -#define CPU_ITM_STIM24_STIM24_M 0xFFFFFFFF -#define CPU_ITM_STIM24_STIM24_S 0 +#define CPU_ITM_STIM24_STIM24_W 32 +#define CPU_ITM_STIM24_STIM24_M 0xFFFFFFFF +#define CPU_ITM_STIM24_STIM24_S 0 //***************************************************************************** // @@ -592,9 +592,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM25_STIM25_W 32 -#define CPU_ITM_STIM25_STIM25_M 0xFFFFFFFF -#define CPU_ITM_STIM25_STIM25_S 0 +#define CPU_ITM_STIM25_STIM25_W 32 +#define CPU_ITM_STIM25_STIM25_M 0xFFFFFFFF +#define CPU_ITM_STIM25_STIM25_S 0 //***************************************************************************** // @@ -609,9 +609,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM26_STIM26_W 32 -#define CPU_ITM_STIM26_STIM26_M 0xFFFFFFFF -#define CPU_ITM_STIM26_STIM26_S 0 +#define CPU_ITM_STIM26_STIM26_W 32 +#define CPU_ITM_STIM26_STIM26_M 0xFFFFFFFF +#define CPU_ITM_STIM26_STIM26_S 0 //***************************************************************************** // @@ -626,9 +626,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM27_STIM27_W 32 -#define CPU_ITM_STIM27_STIM27_M 0xFFFFFFFF -#define CPU_ITM_STIM27_STIM27_S 0 +#define CPU_ITM_STIM27_STIM27_W 32 +#define CPU_ITM_STIM27_STIM27_M 0xFFFFFFFF +#define CPU_ITM_STIM27_STIM27_S 0 //***************************************************************************** // @@ -643,9 +643,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM28_STIM28_W 32 -#define CPU_ITM_STIM28_STIM28_M 0xFFFFFFFF -#define CPU_ITM_STIM28_STIM28_S 0 +#define CPU_ITM_STIM28_STIM28_W 32 +#define CPU_ITM_STIM28_STIM28_M 0xFFFFFFFF +#define CPU_ITM_STIM28_STIM28_S 0 //***************************************************************************** // @@ -660,9 +660,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM29_STIM29_W 32 -#define CPU_ITM_STIM29_STIM29_M 0xFFFFFFFF -#define CPU_ITM_STIM29_STIM29_S 0 +#define CPU_ITM_STIM29_STIM29_W 32 +#define CPU_ITM_STIM29_STIM29_M 0xFFFFFFFF +#define CPU_ITM_STIM29_STIM29_S 0 //***************************************************************************** // @@ -677,9 +677,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM30_STIM30_W 32 -#define CPU_ITM_STIM30_STIM30_M 0xFFFFFFFF -#define CPU_ITM_STIM30_STIM30_S 0 +#define CPU_ITM_STIM30_STIM30_W 32 +#define CPU_ITM_STIM30_STIM30_M 0xFFFFFFFF +#define CPU_ITM_STIM30_STIM30_S 0 //***************************************************************************** // @@ -694,9 +694,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM31_STIM31_W 32 -#define CPU_ITM_STIM31_STIM31_M 0xFFFFFFFF -#define CPU_ITM_STIM31_STIM31_S 0 +#define CPU_ITM_STIM31_STIM31_W 32 +#define CPU_ITM_STIM31_STIM31_M 0xFFFFFFFF +#define CPU_ITM_STIM31_STIM31_S 0 //***************************************************************************** // @@ -706,258 +706,258 @@ // Field: [31] STIMENA31 // // Bit mask to enable tracing on ITM stimulus port 31. -#define CPU_ITM_TER_STIMENA31 0x80000000 -#define CPU_ITM_TER_STIMENA31_BITN 31 -#define CPU_ITM_TER_STIMENA31_M 0x80000000 -#define CPU_ITM_TER_STIMENA31_S 31 +#define CPU_ITM_TER_STIMENA31 0x80000000 +#define CPU_ITM_TER_STIMENA31_BITN 31 +#define CPU_ITM_TER_STIMENA31_M 0x80000000 +#define CPU_ITM_TER_STIMENA31_S 31 // Field: [30] STIMENA30 // // Bit mask to enable tracing on ITM stimulus port 30. -#define CPU_ITM_TER_STIMENA30 0x40000000 -#define CPU_ITM_TER_STIMENA30_BITN 30 -#define CPU_ITM_TER_STIMENA30_M 0x40000000 -#define CPU_ITM_TER_STIMENA30_S 30 +#define CPU_ITM_TER_STIMENA30 0x40000000 +#define CPU_ITM_TER_STIMENA30_BITN 30 +#define CPU_ITM_TER_STIMENA30_M 0x40000000 +#define CPU_ITM_TER_STIMENA30_S 30 // Field: [29] STIMENA29 // // Bit mask to enable tracing on ITM stimulus port 29. -#define CPU_ITM_TER_STIMENA29 0x20000000 -#define CPU_ITM_TER_STIMENA29_BITN 29 -#define CPU_ITM_TER_STIMENA29_M 0x20000000 -#define CPU_ITM_TER_STIMENA29_S 29 +#define CPU_ITM_TER_STIMENA29 0x20000000 +#define CPU_ITM_TER_STIMENA29_BITN 29 +#define CPU_ITM_TER_STIMENA29_M 0x20000000 +#define CPU_ITM_TER_STIMENA29_S 29 // Field: [28] STIMENA28 // // Bit mask to enable tracing on ITM stimulus port 28. -#define CPU_ITM_TER_STIMENA28 0x10000000 -#define CPU_ITM_TER_STIMENA28_BITN 28 -#define CPU_ITM_TER_STIMENA28_M 0x10000000 -#define CPU_ITM_TER_STIMENA28_S 28 +#define CPU_ITM_TER_STIMENA28 0x10000000 +#define CPU_ITM_TER_STIMENA28_BITN 28 +#define CPU_ITM_TER_STIMENA28_M 0x10000000 +#define CPU_ITM_TER_STIMENA28_S 28 // Field: [27] STIMENA27 // // Bit mask to enable tracing on ITM stimulus port 27. -#define CPU_ITM_TER_STIMENA27 0x08000000 -#define CPU_ITM_TER_STIMENA27_BITN 27 -#define CPU_ITM_TER_STIMENA27_M 0x08000000 -#define CPU_ITM_TER_STIMENA27_S 27 +#define CPU_ITM_TER_STIMENA27 0x08000000 +#define CPU_ITM_TER_STIMENA27_BITN 27 +#define CPU_ITM_TER_STIMENA27_M 0x08000000 +#define CPU_ITM_TER_STIMENA27_S 27 // Field: [26] STIMENA26 // // Bit mask to enable tracing on ITM stimulus port 26. -#define CPU_ITM_TER_STIMENA26 0x04000000 -#define CPU_ITM_TER_STIMENA26_BITN 26 -#define CPU_ITM_TER_STIMENA26_M 0x04000000 -#define CPU_ITM_TER_STIMENA26_S 26 +#define CPU_ITM_TER_STIMENA26 0x04000000 +#define CPU_ITM_TER_STIMENA26_BITN 26 +#define CPU_ITM_TER_STIMENA26_M 0x04000000 +#define CPU_ITM_TER_STIMENA26_S 26 // Field: [25] STIMENA25 // // Bit mask to enable tracing on ITM stimulus port 25. -#define CPU_ITM_TER_STIMENA25 0x02000000 -#define CPU_ITM_TER_STIMENA25_BITN 25 -#define CPU_ITM_TER_STIMENA25_M 0x02000000 -#define CPU_ITM_TER_STIMENA25_S 25 +#define CPU_ITM_TER_STIMENA25 0x02000000 +#define CPU_ITM_TER_STIMENA25_BITN 25 +#define CPU_ITM_TER_STIMENA25_M 0x02000000 +#define CPU_ITM_TER_STIMENA25_S 25 // Field: [24] STIMENA24 // // Bit mask to enable tracing on ITM stimulus port 24. -#define CPU_ITM_TER_STIMENA24 0x01000000 -#define CPU_ITM_TER_STIMENA24_BITN 24 -#define CPU_ITM_TER_STIMENA24_M 0x01000000 -#define CPU_ITM_TER_STIMENA24_S 24 +#define CPU_ITM_TER_STIMENA24 0x01000000 +#define CPU_ITM_TER_STIMENA24_BITN 24 +#define CPU_ITM_TER_STIMENA24_M 0x01000000 +#define CPU_ITM_TER_STIMENA24_S 24 // Field: [23] STIMENA23 // // Bit mask to enable tracing on ITM stimulus port 23. -#define CPU_ITM_TER_STIMENA23 0x00800000 -#define CPU_ITM_TER_STIMENA23_BITN 23 -#define CPU_ITM_TER_STIMENA23_M 0x00800000 -#define CPU_ITM_TER_STIMENA23_S 23 +#define CPU_ITM_TER_STIMENA23 0x00800000 +#define CPU_ITM_TER_STIMENA23_BITN 23 +#define CPU_ITM_TER_STIMENA23_M 0x00800000 +#define CPU_ITM_TER_STIMENA23_S 23 // Field: [22] STIMENA22 // // Bit mask to enable tracing on ITM stimulus port 22. -#define CPU_ITM_TER_STIMENA22 0x00400000 -#define CPU_ITM_TER_STIMENA22_BITN 22 -#define CPU_ITM_TER_STIMENA22_M 0x00400000 -#define CPU_ITM_TER_STIMENA22_S 22 +#define CPU_ITM_TER_STIMENA22 0x00400000 +#define CPU_ITM_TER_STIMENA22_BITN 22 +#define CPU_ITM_TER_STIMENA22_M 0x00400000 +#define CPU_ITM_TER_STIMENA22_S 22 // Field: [21] STIMENA21 // // Bit mask to enable tracing on ITM stimulus port 21. -#define CPU_ITM_TER_STIMENA21 0x00200000 -#define CPU_ITM_TER_STIMENA21_BITN 21 -#define CPU_ITM_TER_STIMENA21_M 0x00200000 -#define CPU_ITM_TER_STIMENA21_S 21 +#define CPU_ITM_TER_STIMENA21 0x00200000 +#define CPU_ITM_TER_STIMENA21_BITN 21 +#define CPU_ITM_TER_STIMENA21_M 0x00200000 +#define CPU_ITM_TER_STIMENA21_S 21 // Field: [20] STIMENA20 // // Bit mask to enable tracing on ITM stimulus port 20. -#define CPU_ITM_TER_STIMENA20 0x00100000 -#define CPU_ITM_TER_STIMENA20_BITN 20 -#define CPU_ITM_TER_STIMENA20_M 0x00100000 -#define CPU_ITM_TER_STIMENA20_S 20 +#define CPU_ITM_TER_STIMENA20 0x00100000 +#define CPU_ITM_TER_STIMENA20_BITN 20 +#define CPU_ITM_TER_STIMENA20_M 0x00100000 +#define CPU_ITM_TER_STIMENA20_S 20 // Field: [19] STIMENA19 // // Bit mask to enable tracing on ITM stimulus port 19. -#define CPU_ITM_TER_STIMENA19 0x00080000 -#define CPU_ITM_TER_STIMENA19_BITN 19 -#define CPU_ITM_TER_STIMENA19_M 0x00080000 -#define CPU_ITM_TER_STIMENA19_S 19 +#define CPU_ITM_TER_STIMENA19 0x00080000 +#define CPU_ITM_TER_STIMENA19_BITN 19 +#define CPU_ITM_TER_STIMENA19_M 0x00080000 +#define CPU_ITM_TER_STIMENA19_S 19 // Field: [18] STIMENA18 // // Bit mask to enable tracing on ITM stimulus port 18. -#define CPU_ITM_TER_STIMENA18 0x00040000 -#define CPU_ITM_TER_STIMENA18_BITN 18 -#define CPU_ITM_TER_STIMENA18_M 0x00040000 -#define CPU_ITM_TER_STIMENA18_S 18 +#define CPU_ITM_TER_STIMENA18 0x00040000 +#define CPU_ITM_TER_STIMENA18_BITN 18 +#define CPU_ITM_TER_STIMENA18_M 0x00040000 +#define CPU_ITM_TER_STIMENA18_S 18 // Field: [17] STIMENA17 // // Bit mask to enable tracing on ITM stimulus port 17. -#define CPU_ITM_TER_STIMENA17 0x00020000 -#define CPU_ITM_TER_STIMENA17_BITN 17 -#define CPU_ITM_TER_STIMENA17_M 0x00020000 -#define CPU_ITM_TER_STIMENA17_S 17 +#define CPU_ITM_TER_STIMENA17 0x00020000 +#define CPU_ITM_TER_STIMENA17_BITN 17 +#define CPU_ITM_TER_STIMENA17_M 0x00020000 +#define CPU_ITM_TER_STIMENA17_S 17 // Field: [16] STIMENA16 // // Bit mask to enable tracing on ITM stimulus port 16. -#define CPU_ITM_TER_STIMENA16 0x00010000 -#define CPU_ITM_TER_STIMENA16_BITN 16 -#define CPU_ITM_TER_STIMENA16_M 0x00010000 -#define CPU_ITM_TER_STIMENA16_S 16 +#define CPU_ITM_TER_STIMENA16 0x00010000 +#define CPU_ITM_TER_STIMENA16_BITN 16 +#define CPU_ITM_TER_STIMENA16_M 0x00010000 +#define CPU_ITM_TER_STIMENA16_S 16 // Field: [15] STIMENA15 // // Bit mask to enable tracing on ITM stimulus port 15. -#define CPU_ITM_TER_STIMENA15 0x00008000 -#define CPU_ITM_TER_STIMENA15_BITN 15 -#define CPU_ITM_TER_STIMENA15_M 0x00008000 -#define CPU_ITM_TER_STIMENA15_S 15 +#define CPU_ITM_TER_STIMENA15 0x00008000 +#define CPU_ITM_TER_STIMENA15_BITN 15 +#define CPU_ITM_TER_STIMENA15_M 0x00008000 +#define CPU_ITM_TER_STIMENA15_S 15 // Field: [14] STIMENA14 // // Bit mask to enable tracing on ITM stimulus port 14. -#define CPU_ITM_TER_STIMENA14 0x00004000 -#define CPU_ITM_TER_STIMENA14_BITN 14 -#define CPU_ITM_TER_STIMENA14_M 0x00004000 -#define CPU_ITM_TER_STIMENA14_S 14 +#define CPU_ITM_TER_STIMENA14 0x00004000 +#define CPU_ITM_TER_STIMENA14_BITN 14 +#define CPU_ITM_TER_STIMENA14_M 0x00004000 +#define CPU_ITM_TER_STIMENA14_S 14 // Field: [13] STIMENA13 // // Bit mask to enable tracing on ITM stimulus port 13. -#define CPU_ITM_TER_STIMENA13 0x00002000 -#define CPU_ITM_TER_STIMENA13_BITN 13 -#define CPU_ITM_TER_STIMENA13_M 0x00002000 -#define CPU_ITM_TER_STIMENA13_S 13 +#define CPU_ITM_TER_STIMENA13 0x00002000 +#define CPU_ITM_TER_STIMENA13_BITN 13 +#define CPU_ITM_TER_STIMENA13_M 0x00002000 +#define CPU_ITM_TER_STIMENA13_S 13 // Field: [12] STIMENA12 // // Bit mask to enable tracing on ITM stimulus port 12. -#define CPU_ITM_TER_STIMENA12 0x00001000 -#define CPU_ITM_TER_STIMENA12_BITN 12 -#define CPU_ITM_TER_STIMENA12_M 0x00001000 -#define CPU_ITM_TER_STIMENA12_S 12 +#define CPU_ITM_TER_STIMENA12 0x00001000 +#define CPU_ITM_TER_STIMENA12_BITN 12 +#define CPU_ITM_TER_STIMENA12_M 0x00001000 +#define CPU_ITM_TER_STIMENA12_S 12 // Field: [11] STIMENA11 // // Bit mask to enable tracing on ITM stimulus port 11. -#define CPU_ITM_TER_STIMENA11 0x00000800 -#define CPU_ITM_TER_STIMENA11_BITN 11 -#define CPU_ITM_TER_STIMENA11_M 0x00000800 -#define CPU_ITM_TER_STIMENA11_S 11 +#define CPU_ITM_TER_STIMENA11 0x00000800 +#define CPU_ITM_TER_STIMENA11_BITN 11 +#define CPU_ITM_TER_STIMENA11_M 0x00000800 +#define CPU_ITM_TER_STIMENA11_S 11 // Field: [10] STIMENA10 // // Bit mask to enable tracing on ITM stimulus port 10. -#define CPU_ITM_TER_STIMENA10 0x00000400 -#define CPU_ITM_TER_STIMENA10_BITN 10 -#define CPU_ITM_TER_STIMENA10_M 0x00000400 -#define CPU_ITM_TER_STIMENA10_S 10 +#define CPU_ITM_TER_STIMENA10 0x00000400 +#define CPU_ITM_TER_STIMENA10_BITN 10 +#define CPU_ITM_TER_STIMENA10_M 0x00000400 +#define CPU_ITM_TER_STIMENA10_S 10 // Field: [9] STIMENA9 // // Bit mask to enable tracing on ITM stimulus port 9. -#define CPU_ITM_TER_STIMENA9 0x00000200 -#define CPU_ITM_TER_STIMENA9_BITN 9 -#define CPU_ITM_TER_STIMENA9_M 0x00000200 -#define CPU_ITM_TER_STIMENA9_S 9 +#define CPU_ITM_TER_STIMENA9 0x00000200 +#define CPU_ITM_TER_STIMENA9_BITN 9 +#define CPU_ITM_TER_STIMENA9_M 0x00000200 +#define CPU_ITM_TER_STIMENA9_S 9 // Field: [8] STIMENA8 // // Bit mask to enable tracing on ITM stimulus port 8. -#define CPU_ITM_TER_STIMENA8 0x00000100 -#define CPU_ITM_TER_STIMENA8_BITN 8 -#define CPU_ITM_TER_STIMENA8_M 0x00000100 -#define CPU_ITM_TER_STIMENA8_S 8 +#define CPU_ITM_TER_STIMENA8 0x00000100 +#define CPU_ITM_TER_STIMENA8_BITN 8 +#define CPU_ITM_TER_STIMENA8_M 0x00000100 +#define CPU_ITM_TER_STIMENA8_S 8 // Field: [7] STIMENA7 // // Bit mask to enable tracing on ITM stimulus port 7. -#define CPU_ITM_TER_STIMENA7 0x00000080 -#define CPU_ITM_TER_STIMENA7_BITN 7 -#define CPU_ITM_TER_STIMENA7_M 0x00000080 -#define CPU_ITM_TER_STIMENA7_S 7 +#define CPU_ITM_TER_STIMENA7 0x00000080 +#define CPU_ITM_TER_STIMENA7_BITN 7 +#define CPU_ITM_TER_STIMENA7_M 0x00000080 +#define CPU_ITM_TER_STIMENA7_S 7 // Field: [6] STIMENA6 // // Bit mask to enable tracing on ITM stimulus port 6. -#define CPU_ITM_TER_STIMENA6 0x00000040 -#define CPU_ITM_TER_STIMENA6_BITN 6 -#define CPU_ITM_TER_STIMENA6_M 0x00000040 -#define CPU_ITM_TER_STIMENA6_S 6 +#define CPU_ITM_TER_STIMENA6 0x00000040 +#define CPU_ITM_TER_STIMENA6_BITN 6 +#define CPU_ITM_TER_STIMENA6_M 0x00000040 +#define CPU_ITM_TER_STIMENA6_S 6 // Field: [5] STIMENA5 // // Bit mask to enable tracing on ITM stimulus port 5. -#define CPU_ITM_TER_STIMENA5 0x00000020 -#define CPU_ITM_TER_STIMENA5_BITN 5 -#define CPU_ITM_TER_STIMENA5_M 0x00000020 -#define CPU_ITM_TER_STIMENA5_S 5 +#define CPU_ITM_TER_STIMENA5 0x00000020 +#define CPU_ITM_TER_STIMENA5_BITN 5 +#define CPU_ITM_TER_STIMENA5_M 0x00000020 +#define CPU_ITM_TER_STIMENA5_S 5 // Field: [4] STIMENA4 // // Bit mask to enable tracing on ITM stimulus port 4. -#define CPU_ITM_TER_STIMENA4 0x00000010 -#define CPU_ITM_TER_STIMENA4_BITN 4 -#define CPU_ITM_TER_STIMENA4_M 0x00000010 -#define CPU_ITM_TER_STIMENA4_S 4 +#define CPU_ITM_TER_STIMENA4 0x00000010 +#define CPU_ITM_TER_STIMENA4_BITN 4 +#define CPU_ITM_TER_STIMENA4_M 0x00000010 +#define CPU_ITM_TER_STIMENA4_S 4 // Field: [3] STIMENA3 // // Bit mask to enable tracing on ITM stimulus port 3. -#define CPU_ITM_TER_STIMENA3 0x00000008 -#define CPU_ITM_TER_STIMENA3_BITN 3 -#define CPU_ITM_TER_STIMENA3_M 0x00000008 -#define CPU_ITM_TER_STIMENA3_S 3 +#define CPU_ITM_TER_STIMENA3 0x00000008 +#define CPU_ITM_TER_STIMENA3_BITN 3 +#define CPU_ITM_TER_STIMENA3_M 0x00000008 +#define CPU_ITM_TER_STIMENA3_S 3 // Field: [2] STIMENA2 // // Bit mask to enable tracing on ITM stimulus port 2. -#define CPU_ITM_TER_STIMENA2 0x00000004 -#define CPU_ITM_TER_STIMENA2_BITN 2 -#define CPU_ITM_TER_STIMENA2_M 0x00000004 -#define CPU_ITM_TER_STIMENA2_S 2 +#define CPU_ITM_TER_STIMENA2 0x00000004 +#define CPU_ITM_TER_STIMENA2_BITN 2 +#define CPU_ITM_TER_STIMENA2_M 0x00000004 +#define CPU_ITM_TER_STIMENA2_S 2 // Field: [1] STIMENA1 // // Bit mask to enable tracing on ITM stimulus port 1. -#define CPU_ITM_TER_STIMENA1 0x00000002 -#define CPU_ITM_TER_STIMENA1_BITN 1 -#define CPU_ITM_TER_STIMENA1_M 0x00000002 -#define CPU_ITM_TER_STIMENA1_S 1 +#define CPU_ITM_TER_STIMENA1 0x00000002 +#define CPU_ITM_TER_STIMENA1_BITN 1 +#define CPU_ITM_TER_STIMENA1_M 0x00000002 +#define CPU_ITM_TER_STIMENA1_S 1 // Field: [0] STIMENA0 // // Bit mask to enable tracing on ITM stimulus port 0. -#define CPU_ITM_TER_STIMENA0 0x00000001 -#define CPU_ITM_TER_STIMENA0_BITN 0 -#define CPU_ITM_TER_STIMENA0_M 0x00000001 -#define CPU_ITM_TER_STIMENA0_S 0 +#define CPU_ITM_TER_STIMENA0 0x00000001 +#define CPU_ITM_TER_STIMENA0_BITN 0 +#define CPU_ITM_TER_STIMENA0_M 0x00000001 +#define CPU_ITM_TER_STIMENA0_S 0 //***************************************************************************** // @@ -975,9 +975,9 @@ // // 0: User access allowed to stimulus ports // 1: Privileged access only to stimulus ports -#define CPU_ITM_TPR_PRIVMASK_W 4 -#define CPU_ITM_TPR_PRIVMASK_M 0x0000000F -#define CPU_ITM_TPR_PRIVMASK_S 0 +#define CPU_ITM_TPR_PRIVMASK_W 4 +#define CPU_ITM_TPR_PRIVMASK_M 0x0000000F +#define CPU_ITM_TPR_PRIVMASK_S 0 //***************************************************************************** // @@ -987,19 +987,19 @@ // Field: [23] BUSY // // Set when ITM events present and being drained. -#define CPU_ITM_TCR_BUSY 0x00800000 -#define CPU_ITM_TCR_BUSY_BITN 23 -#define CPU_ITM_TCR_BUSY_M 0x00800000 -#define CPU_ITM_TCR_BUSY_S 23 +#define CPU_ITM_TCR_BUSY 0x00800000 +#define CPU_ITM_TCR_BUSY_BITN 23 +#define CPU_ITM_TCR_BUSY_M 0x00800000 +#define CPU_ITM_TCR_BUSY_S 23 // Field: [22:16] ATBID // // Trace Bus ID for CoreSight system. Optional identifier for multi-source // trace stream formatting. If multi-source trace is in use, this field must be // written with a non-zero value. -#define CPU_ITM_TCR_ATBID_W 7 -#define CPU_ITM_TCR_ATBID_M 0x007F0000 -#define CPU_ITM_TCR_ATBID_S 16 +#define CPU_ITM_TCR_ATBID_W 7 +#define CPU_ITM_TCR_ATBID_M 0x007F0000 +#define CPU_ITM_TCR_ATBID_S 16 // Field: [9:8] TSPRESCALE // @@ -1009,13 +1009,13 @@ // DIV16 Divide by 16 // DIV4 Divide by 4 // NOPRESCALING No prescaling -#define CPU_ITM_TCR_TSPRESCALE_W 2 -#define CPU_ITM_TCR_TSPRESCALE_M 0x00000300 -#define CPU_ITM_TCR_TSPRESCALE_S 8 -#define CPU_ITM_TCR_TSPRESCALE_DIV64 0x00000300 -#define CPU_ITM_TCR_TSPRESCALE_DIV16 0x00000200 -#define CPU_ITM_TCR_TSPRESCALE_DIV4 0x00000100 -#define CPU_ITM_TCR_TSPRESCALE_NOPRESCALING 0x00000000 +#define CPU_ITM_TCR_TSPRESCALE_W 2 +#define CPU_ITM_TCR_TSPRESCALE_M 0x00000300 +#define CPU_ITM_TCR_TSPRESCALE_S 8 +#define CPU_ITM_TCR_TSPRESCALE_DIV64 0x00000300 +#define CPU_ITM_TCR_TSPRESCALE_DIV16 0x00000200 +#define CPU_ITM_TCR_TSPRESCALE_DIV4 0x00000100 +#define CPU_ITM_TCR_TSPRESCALE_NOPRESCALING 0x00000000 // Field: [4] SWOENA // @@ -1028,29 +1028,29 @@ // 0x1: Timestamp counter uses lineout (data related) clock from TPIU // interface. The timestamp counter is held in reset while the output line is // idle. -#define CPU_ITM_TCR_SWOENA 0x00000010 -#define CPU_ITM_TCR_SWOENA_BITN 4 -#define CPU_ITM_TCR_SWOENA_M 0x00000010 -#define CPU_ITM_TCR_SWOENA_S 4 +#define CPU_ITM_TCR_SWOENA 0x00000010 +#define CPU_ITM_TCR_SWOENA_BITN 4 +#define CPU_ITM_TCR_SWOENA_M 0x00000010 +#define CPU_ITM_TCR_SWOENA_S 4 // Field: [3] DWTENA // // Enables the DWT stimulus (hardware event packet emission to the TPIU from // the DWT) -#define CPU_ITM_TCR_DWTENA 0x00000008 -#define CPU_ITM_TCR_DWTENA_BITN 3 -#define CPU_ITM_TCR_DWTENA_M 0x00000008 -#define CPU_ITM_TCR_DWTENA_S 3 +#define CPU_ITM_TCR_DWTENA 0x00000008 +#define CPU_ITM_TCR_DWTENA_BITN 3 +#define CPU_ITM_TCR_DWTENA_M 0x00000008 +#define CPU_ITM_TCR_DWTENA_S 3 // Field: [2] SYNCENA // // Enables synchronization packet transmission for a synchronous TPIU. // CPU_DWT:CTRL.SYNCTAP must be configured for the correct synchronization // speed. -#define CPU_ITM_TCR_SYNCENA 0x00000004 -#define CPU_ITM_TCR_SYNCENA_BITN 2 -#define CPU_ITM_TCR_SYNCENA_M 0x00000004 -#define CPU_ITM_TCR_SYNCENA_S 2 +#define CPU_ITM_TCR_SYNCENA 0x00000004 +#define CPU_ITM_TCR_SYNCENA_BITN 2 +#define CPU_ITM_TCR_SYNCENA_M 0x00000004 +#define CPU_ITM_TCR_SYNCENA_S 2 // Field: [1] TSENA // @@ -1061,19 +1061,19 @@ // for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps // are triggered by activity on the internal trace bus only. In this case there // is no regular timestamp output when the ITM is idle. -#define CPU_ITM_TCR_TSENA 0x00000002 -#define CPU_ITM_TCR_TSENA_BITN 1 -#define CPU_ITM_TCR_TSENA_M 0x00000002 -#define CPU_ITM_TCR_TSENA_S 1 +#define CPU_ITM_TCR_TSENA 0x00000002 +#define CPU_ITM_TCR_TSENA_BITN 1 +#define CPU_ITM_TCR_TSENA_M 0x00000002 +#define CPU_ITM_TCR_TSENA_S 1 // Field: [0] ITMENA // // Enables ITM. This is the master enable, and must be set before ITM Stimulus // and Trace Enable registers can be written. -#define CPU_ITM_TCR_ITMENA 0x00000001 -#define CPU_ITM_TCR_ITMENA_BITN 0 -#define CPU_ITM_TCR_ITMENA_M 0x00000001 -#define CPU_ITM_TCR_ITMENA_S 0 +#define CPU_ITM_TCR_ITMENA 0x00000001 +#define CPU_ITM_TCR_ITMENA_BITN 0 +#define CPU_ITM_TCR_ITMENA_M 0x00000001 +#define CPU_ITM_TCR_ITMENA_S 0 //***************************************************************************** // @@ -1084,9 +1084,9 @@ // // A privileged write of 0xC5ACCE55 enables more write access to Control // Registers TER, TPR and TCR. An invalid write removes write access. -#define CPU_ITM_LAR_LOCK_ACCESS_W 32 -#define CPU_ITM_LAR_LOCK_ACCESS_M 0xFFFFFFFF -#define CPU_ITM_LAR_LOCK_ACCESS_S 0 +#define CPU_ITM_LAR_LOCK_ACCESS_W 32 +#define CPU_ITM_LAR_LOCK_ACCESS_M 0xFFFFFFFF +#define CPU_ITM_LAR_LOCK_ACCESS_S 0 //***************************************************************************** // @@ -1096,27 +1096,26 @@ // Field: [2] BYTEACC // // Reads 0 which means 8-bit lock access is not be implemented. -#define CPU_ITM_LSR_BYTEACC 0x00000004 -#define CPU_ITM_LSR_BYTEACC_BITN 2 -#define CPU_ITM_LSR_BYTEACC_M 0x00000004 -#define CPU_ITM_LSR_BYTEACC_S 2 +#define CPU_ITM_LSR_BYTEACC 0x00000004 +#define CPU_ITM_LSR_BYTEACC_BITN 2 +#define CPU_ITM_LSR_BYTEACC_M 0x00000004 +#define CPU_ITM_LSR_BYTEACC_S 2 // Field: [1] ACCESS // // Write access to component is blocked. All writes are ignored, reads are // permitted. -#define CPU_ITM_LSR_ACCESS 0x00000002 -#define CPU_ITM_LSR_ACCESS_BITN 1 -#define CPU_ITM_LSR_ACCESS_M 0x00000002 -#define CPU_ITM_LSR_ACCESS_S 1 +#define CPU_ITM_LSR_ACCESS 0x00000002 +#define CPU_ITM_LSR_ACCESS_BITN 1 +#define CPU_ITM_LSR_ACCESS_M 0x00000002 +#define CPU_ITM_LSR_ACCESS_S 1 // Field: [0] PRESENT // // Indicates that a lock mechanism exists for this component. -#define CPU_ITM_LSR_PRESENT 0x00000001 -#define CPU_ITM_LSR_PRESENT_BITN 0 -#define CPU_ITM_LSR_PRESENT_M 0x00000001 -#define CPU_ITM_LSR_PRESENT_S 0 - +#define CPU_ITM_LSR_PRESENT 0x00000001 +#define CPU_ITM_LSR_PRESENT_BITN 0 +#define CPU_ITM_LSR_PRESENT_M 0x00000001 +#define CPU_ITM_LSR_PRESENT_S 0 #endif // __CPU_ITM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_rom_table.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_rom_table.h index 43c9a9f..25fef6f 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_rom_table.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_rom_table.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_cpu_rom_table_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_cpu_rom_table_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CPU_ROM_TABLE_H__ #define __HW_CPU_ROM_TABLE_H__ @@ -44,28 +44,28 @@ // //***************************************************************************** // System Control Space Component -#define CPU_ROM_TABLE_O_SCS 0x00000000 +#define CPU_ROM_TABLE_O_SCS 0x00000000 // Data Watchpoint and Trace Component -#define CPU_ROM_TABLE_O_DWT 0x00000004 +#define CPU_ROM_TABLE_O_DWT 0x00000004 // Flash Patch and Breakpoint Component -#define CPU_ROM_TABLE_O_FPB 0x00000008 +#define CPU_ROM_TABLE_O_FPB 0x00000008 // Instrumentation Trace Component -#define CPU_ROM_TABLE_O_ITM 0x0000000C +#define CPU_ROM_TABLE_O_ITM 0x0000000C // Trace Port Interface Component -#define CPU_ROM_TABLE_O_TPIU 0x00000010 +#define CPU_ROM_TABLE_O_TPIU 0x00000010 // Enhanced Trace Component -#define CPU_ROM_TABLE_O_ETM 0x00000014 +#define CPU_ROM_TABLE_O_ETM 0x00000014 // End Marker -#define CPU_ROM_TABLE_O_END 0x00000018 +#define CPU_ROM_TABLE_O_END 0x00000018 // System Memory Map Access for DAP -#define CPU_ROM_TABLE_O_SYSTEM_ACCESS 0x00000FCC +#define CPU_ROM_TABLE_O_SYSTEM_ACCESS 0x00000FCC //***************************************************************************** // @@ -76,9 +76,9 @@ // // Points to the SCS at 0xE000E000. // (SCS + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE000E000. -#define CPU_ROM_TABLE_SCS_SCS_W 32 -#define CPU_ROM_TABLE_SCS_SCS_M 0xFFFFFFFF -#define CPU_ROM_TABLE_SCS_SCS_S 0 +#define CPU_ROM_TABLE_SCS_SCS_W 32 +#define CPU_ROM_TABLE_SCS_SCS_M 0xFFFFFFFF +#define CPU_ROM_TABLE_SCS_SCS_S 0 //***************************************************************************** // @@ -89,18 +89,18 @@ // // Points to the Data Watchpoint and Trace block at 0xE0001000. // (2*DWT + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0001000. -#define CPU_ROM_TABLE_DWT_DWT_W 31 -#define CPU_ROM_TABLE_DWT_DWT_M 0xFFFFFFFE -#define CPU_ROM_TABLE_DWT_DWT_S 1 +#define CPU_ROM_TABLE_DWT_DWT_W 31 +#define CPU_ROM_TABLE_DWT_DWT_M 0xFFFFFFFE +#define CPU_ROM_TABLE_DWT_DWT_S 1 // Field: [0] DWT_PRESENT // // 0: DWT is not present // 1: DWT is present. -#define CPU_ROM_TABLE_DWT_DWT_PRESENT 0x00000001 -#define CPU_ROM_TABLE_DWT_DWT_PRESENT_BITN 0 -#define CPU_ROM_TABLE_DWT_DWT_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_DWT_DWT_PRESENT_S 0 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT 0x00000001 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_BITN 0 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_S 0 //***************************************************************************** // @@ -111,18 +111,18 @@ // // Points to the Flash Patch and Breakpoint block at 0xE0002000. // (2*FPB + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0002000. -#define CPU_ROM_TABLE_FPB_FPB_W 31 -#define CPU_ROM_TABLE_FPB_FPB_M 0xFFFFFFFE -#define CPU_ROM_TABLE_FPB_FPB_S 1 +#define CPU_ROM_TABLE_FPB_FPB_W 31 +#define CPU_ROM_TABLE_FPB_FPB_M 0xFFFFFFFE +#define CPU_ROM_TABLE_FPB_FPB_S 1 // Field: [0] FPB_PRESENT // // 0: FPB is not present // 1: FPB is present. -#define CPU_ROM_TABLE_FPB_FPB_PRESENT 0x00000001 -#define CPU_ROM_TABLE_FPB_FPB_PRESENT_BITN 0 -#define CPU_ROM_TABLE_FPB_FPB_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_FPB_FPB_PRESENT_S 0 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT 0x00000001 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_BITN 0 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_S 0 //***************************************************************************** // @@ -133,18 +133,18 @@ // // Points to the Instrumentation Trace block at 0xE0000000. // (2*ITM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0000000. -#define CPU_ROM_TABLE_ITM_ITM_W 31 -#define CPU_ROM_TABLE_ITM_ITM_M 0xFFFFFFFE -#define CPU_ROM_TABLE_ITM_ITM_S 1 +#define CPU_ROM_TABLE_ITM_ITM_W 31 +#define CPU_ROM_TABLE_ITM_ITM_M 0xFFFFFFFE +#define CPU_ROM_TABLE_ITM_ITM_S 1 // Field: [0] ITM_PRESENT // // 0: ITM is not present // 1: ITM is present. -#define CPU_ROM_TABLE_ITM_ITM_PRESENT 0x00000001 -#define CPU_ROM_TABLE_ITM_ITM_PRESENT_BITN 0 -#define CPU_ROM_TABLE_ITM_ITM_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_ITM_ITM_PRESENT_S 0 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT 0x00000001 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_BITN 0 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_S 0 //***************************************************************************** // @@ -155,18 +155,18 @@ // // Points to the TPIU. TPIU is at 0xE0040000. // (2*TPIU + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0040000. -#define CPU_ROM_TABLE_TPIU_TPIU_W 31 -#define CPU_ROM_TABLE_TPIU_TPIU_M 0xFFFFFFFE -#define CPU_ROM_TABLE_TPIU_TPIU_S 1 +#define CPU_ROM_TABLE_TPIU_TPIU_W 31 +#define CPU_ROM_TABLE_TPIU_TPIU_M 0xFFFFFFFE +#define CPU_ROM_TABLE_TPIU_TPIU_S 1 // Field: [0] TPIU_PRESENT // // 0: TPIU is not present // 1: TPIU is present. -#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT 0x00000001 -#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_BITN 0 -#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_S 0 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT 0x00000001 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_BITN 0 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_S 0 //***************************************************************************** // @@ -177,18 +177,18 @@ // // Points to the ETM. ETM is at 0xE0041000. // (2*ETM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0041000. -#define CPU_ROM_TABLE_ETM_ETM_W 31 -#define CPU_ROM_TABLE_ETM_ETM_M 0xFFFFFFFE -#define CPU_ROM_TABLE_ETM_ETM_S 1 +#define CPU_ROM_TABLE_ETM_ETM_W 31 +#define CPU_ROM_TABLE_ETM_ETM_M 0xFFFFFFFE +#define CPU_ROM_TABLE_ETM_ETM_S 1 // Field: [0] ETM_PRESENT // // 0: ETM is not present // 1: ETM is present. -#define CPU_ROM_TABLE_ETM_ETM_PRESENT 0x00000001 -#define CPU_ROM_TABLE_ETM_ETM_PRESENT_BITN 0 -#define CPU_ROM_TABLE_ETM_ETM_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_ETM_ETM_PRESENT_S 0 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT 0x00000001 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_BITN 0 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_S 0 //***************************************************************************** // @@ -198,9 +198,9 @@ // Field: [31:0] END // // End of the ROM table -#define CPU_ROM_TABLE_END_END_W 32 -#define CPU_ROM_TABLE_END_END_M 0xFFFFFFFF -#define CPU_ROM_TABLE_END_END_S 0 +#define CPU_ROM_TABLE_END_END_W 32 +#define CPU_ROM_TABLE_END_END_M 0xFFFFFFFF +#define CPU_ROM_TABLE_END_END_S 0 //***************************************************************************** // @@ -211,10 +211,9 @@ // // 1: The system memory map is accessible using the DAP // 0: Only debug resources are accessible using the DAP -#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS 0x00000001 -#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_BITN 0 -#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_M 0x00000001 -#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_S 0 - +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS 0x00000001 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_BITN 0 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_M 0x00000001 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_S 0 #endif // __CPU_ROM_TABLE__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_scs.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_scs.h index c7fa660..18afd7c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_scs.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_scs.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_cpu_scs_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_cpu_scs_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CPU_SCS_H__ #define __HW_CPU_SCS_H__ @@ -44,184 +44,184 @@ // //***************************************************************************** // Interrupt Control Type -#define CPU_SCS_O_ICTR 0x00000004 +#define CPU_SCS_O_ICTR 0x00000004 // Auxiliary Control -#define CPU_SCS_O_ACTLR 0x00000008 +#define CPU_SCS_O_ACTLR 0x00000008 // SysTick Control and Status -#define CPU_SCS_O_STCSR 0x00000010 +#define CPU_SCS_O_STCSR 0x00000010 // SysTick Reload Value -#define CPU_SCS_O_STRVR 0x00000014 +#define CPU_SCS_O_STRVR 0x00000014 // SysTick Current Value -#define CPU_SCS_O_STCVR 0x00000018 +#define CPU_SCS_O_STCVR 0x00000018 // SysTick Calibration Value -#define CPU_SCS_O_STCR 0x0000001C +#define CPU_SCS_O_STCR 0x0000001C // Irq 0 to 31 Set Enable -#define CPU_SCS_O_NVIC_ISER0 0x00000100 +#define CPU_SCS_O_NVIC_ISER0 0x00000100 // Irq 32 to 63 Set Enable -#define CPU_SCS_O_NVIC_ISER1 0x00000104 +#define CPU_SCS_O_NVIC_ISER1 0x00000104 // Irq 0 to 31 Clear Enable -#define CPU_SCS_O_NVIC_ICER0 0x00000180 +#define CPU_SCS_O_NVIC_ICER0 0x00000180 // Irq 32 to 63 Clear Enable -#define CPU_SCS_O_NVIC_ICER1 0x00000184 +#define CPU_SCS_O_NVIC_ICER1 0x00000184 // Irq 0 to 31 Set Pending -#define CPU_SCS_O_NVIC_ISPR0 0x00000200 +#define CPU_SCS_O_NVIC_ISPR0 0x00000200 // Irq 32 to 63 Set Pending -#define CPU_SCS_O_NVIC_ISPR1 0x00000204 +#define CPU_SCS_O_NVIC_ISPR1 0x00000204 // Irq 0 to 31 Clear Pending -#define CPU_SCS_O_NVIC_ICPR0 0x00000280 +#define CPU_SCS_O_NVIC_ICPR0 0x00000280 // Irq 32 to 63 Clear Pending -#define CPU_SCS_O_NVIC_ICPR1 0x00000284 +#define CPU_SCS_O_NVIC_ICPR1 0x00000284 // Irq 0 to 31 Active Bit -#define CPU_SCS_O_NVIC_IABR0 0x00000300 +#define CPU_SCS_O_NVIC_IABR0 0x00000300 // Irq 32 to 63 Active Bit -#define CPU_SCS_O_NVIC_IABR1 0x00000304 +#define CPU_SCS_O_NVIC_IABR1 0x00000304 // Irq 0 to 3 Priority -#define CPU_SCS_O_NVIC_IPR0 0x00000400 +#define CPU_SCS_O_NVIC_IPR0 0x00000400 // Irq 4 to 7 Priority -#define CPU_SCS_O_NVIC_IPR1 0x00000404 +#define CPU_SCS_O_NVIC_IPR1 0x00000404 // Irq 8 to 11 Priority -#define CPU_SCS_O_NVIC_IPR2 0x00000408 +#define CPU_SCS_O_NVIC_IPR2 0x00000408 // Irq 12 to 15 Priority -#define CPU_SCS_O_NVIC_IPR3 0x0000040C +#define CPU_SCS_O_NVIC_IPR3 0x0000040C // Irq 16 to 19 Priority -#define CPU_SCS_O_NVIC_IPR4 0x00000410 +#define CPU_SCS_O_NVIC_IPR4 0x00000410 // Irq 20 to 23 Priority -#define CPU_SCS_O_NVIC_IPR5 0x00000414 +#define CPU_SCS_O_NVIC_IPR5 0x00000414 // Irq 24 to 27 Priority -#define CPU_SCS_O_NVIC_IPR6 0x00000418 +#define CPU_SCS_O_NVIC_IPR6 0x00000418 // Irq 28 to 31 Priority -#define CPU_SCS_O_NVIC_IPR7 0x0000041C +#define CPU_SCS_O_NVIC_IPR7 0x0000041C // Irq 32 to 35 Priority -#define CPU_SCS_O_NVIC_IPR8 0x00000420 +#define CPU_SCS_O_NVIC_IPR8 0x00000420 // CPUID Base -#define CPU_SCS_O_CPUID 0x00000D00 +#define CPU_SCS_O_CPUID 0x00000D00 // Interrupt Control State -#define CPU_SCS_O_ICSR 0x00000D04 +#define CPU_SCS_O_ICSR 0x00000D04 // Vector Table Offset -#define CPU_SCS_O_VTOR 0x00000D08 +#define CPU_SCS_O_VTOR 0x00000D08 // Application Interrupt/Reset Control -#define CPU_SCS_O_AIRCR 0x00000D0C +#define CPU_SCS_O_AIRCR 0x00000D0C // System Control -#define CPU_SCS_O_SCR 0x00000D10 +#define CPU_SCS_O_SCR 0x00000D10 // Configuration Control -#define CPU_SCS_O_CCR 0x00000D14 +#define CPU_SCS_O_CCR 0x00000D14 // System Handlers 4-7 Priority -#define CPU_SCS_O_SHPR1 0x00000D18 +#define CPU_SCS_O_SHPR1 0x00000D18 // System Handlers 8-11 Priority -#define CPU_SCS_O_SHPR2 0x00000D1C +#define CPU_SCS_O_SHPR2 0x00000D1C // System Handlers 12-15 Priority -#define CPU_SCS_O_SHPR3 0x00000D20 +#define CPU_SCS_O_SHPR3 0x00000D20 // System Handler Control and State -#define CPU_SCS_O_SHCSR 0x00000D24 +#define CPU_SCS_O_SHCSR 0x00000D24 // Configurable Fault Status -#define CPU_SCS_O_CFSR 0x00000D28 +#define CPU_SCS_O_CFSR 0x00000D28 // Hard Fault Status -#define CPU_SCS_O_HFSR 0x00000D2C +#define CPU_SCS_O_HFSR 0x00000D2C // Debug Fault Status -#define CPU_SCS_O_DFSR 0x00000D30 +#define CPU_SCS_O_DFSR 0x00000D30 // Mem Manage Fault Address -#define CPU_SCS_O_MMFAR 0x00000D34 +#define CPU_SCS_O_MMFAR 0x00000D34 // Bus Fault Address -#define CPU_SCS_O_BFAR 0x00000D38 +#define CPU_SCS_O_BFAR 0x00000D38 // Auxiliary Fault Status -#define CPU_SCS_O_AFSR 0x00000D3C +#define CPU_SCS_O_AFSR 0x00000D3C // Processor Feature 0 -#define CPU_SCS_O_ID_PFR0 0x00000D40 +#define CPU_SCS_O_ID_PFR0 0x00000D40 // Processor Feature 1 -#define CPU_SCS_O_ID_PFR1 0x00000D44 +#define CPU_SCS_O_ID_PFR1 0x00000D44 // Debug Feature 0 -#define CPU_SCS_O_ID_DFR0 0x00000D48 +#define CPU_SCS_O_ID_DFR0 0x00000D48 // Auxiliary Feature 0 -#define CPU_SCS_O_ID_AFR0 0x00000D4C +#define CPU_SCS_O_ID_AFR0 0x00000D4C // Memory Model Feature 0 -#define CPU_SCS_O_ID_MMFR0 0x00000D50 +#define CPU_SCS_O_ID_MMFR0 0x00000D50 // Memory Model Feature 1 -#define CPU_SCS_O_ID_MMFR1 0x00000D54 +#define CPU_SCS_O_ID_MMFR1 0x00000D54 // Memory Model Feature 2 -#define CPU_SCS_O_ID_MMFR2 0x00000D58 +#define CPU_SCS_O_ID_MMFR2 0x00000D58 // Memory Model Feature 3 -#define CPU_SCS_O_ID_MMFR3 0x00000D5C +#define CPU_SCS_O_ID_MMFR3 0x00000D5C // ISA Feature 0 -#define CPU_SCS_O_ID_ISAR0 0x00000D60 +#define CPU_SCS_O_ID_ISAR0 0x00000D60 // ISA Feature 1 -#define CPU_SCS_O_ID_ISAR1 0x00000D64 +#define CPU_SCS_O_ID_ISAR1 0x00000D64 // ISA Feature 2 -#define CPU_SCS_O_ID_ISAR2 0x00000D68 +#define CPU_SCS_O_ID_ISAR2 0x00000D68 // ISA Feature 3 -#define CPU_SCS_O_ID_ISAR3 0x00000D6C +#define CPU_SCS_O_ID_ISAR3 0x00000D6C // ISA Feature 4 -#define CPU_SCS_O_ID_ISAR4 0x00000D70 +#define CPU_SCS_O_ID_ISAR4 0x00000D70 // Coprocessor Access Control -#define CPU_SCS_O_CPACR 0x00000D88 +#define CPU_SCS_O_CPACR 0x00000D88 // Debug Halting Control and Status -#define CPU_SCS_O_DHCSR 0x00000DF0 +#define CPU_SCS_O_DHCSR 0x00000DF0 // Deubg Core Register Selector -#define CPU_SCS_O_DCRSR 0x00000DF4 +#define CPU_SCS_O_DCRSR 0x00000DF4 // Debug Core Register Data -#define CPU_SCS_O_DCRDR 0x00000DF8 +#define CPU_SCS_O_DCRDR 0x00000DF8 // Debug Exception and Monitor Control -#define CPU_SCS_O_DEMCR 0x00000DFC +#define CPU_SCS_O_DEMCR 0x00000DFC // Software Trigger Interrupt -#define CPU_SCS_O_STIR 0x00000F00 +#define CPU_SCS_O_STIR 0x00000F00 //***************************************************************************** // @@ -240,9 +240,9 @@ // 5: 161...192 // 6: 193...224 // 7: 225...256 -#define CPU_SCS_ICTR_INTLINESNUM_W 3 -#define CPU_SCS_ICTR_INTLINESNUM_M 0x00000007 -#define CPU_SCS_ICTR_INTLINESNUM_S 0 +#define CPU_SCS_ICTR_INTLINESNUM_W 3 +#define CPU_SCS_ICTR_INTLINESNUM_M 0x00000007 +#define CPU_SCS_ICTR_INTLINESNUM_S 0 //***************************************************************************** // @@ -252,10 +252,10 @@ // Field: [2] DISFOLD // // Disables folding of IT instruction. -#define CPU_SCS_ACTLR_DISFOLD 0x00000004 -#define CPU_SCS_ACTLR_DISFOLD_BITN 2 -#define CPU_SCS_ACTLR_DISFOLD_M 0x00000004 -#define CPU_SCS_ACTLR_DISFOLD_S 2 +#define CPU_SCS_ACTLR_DISFOLD 0x00000004 +#define CPU_SCS_ACTLR_DISFOLD_BITN 2 +#define CPU_SCS_ACTLR_DISFOLD_M 0x00000004 +#define CPU_SCS_ACTLR_DISFOLD_S 2 // Field: [1] DISDEFWBUF // @@ -263,20 +263,20 @@ // all bus faults to be precise bus faults but decreases the performance of the // processor because the stores to memory have to complete before the next // instruction can be executed. -#define CPU_SCS_ACTLR_DISDEFWBUF 0x00000002 -#define CPU_SCS_ACTLR_DISDEFWBUF_BITN 1 -#define CPU_SCS_ACTLR_DISDEFWBUF_M 0x00000002 -#define CPU_SCS_ACTLR_DISDEFWBUF_S 1 +#define CPU_SCS_ACTLR_DISDEFWBUF 0x00000002 +#define CPU_SCS_ACTLR_DISDEFWBUF_BITN 1 +#define CPU_SCS_ACTLR_DISDEFWBUF_M 0x00000002 +#define CPU_SCS_ACTLR_DISDEFWBUF_S 1 // Field: [0] DISMCYCINT // // Disables interruption of multi-cycle instructions. This increases the // interrupt latency of the processor becuase LDM/STM completes before // interrupt stacking occurs. -#define CPU_SCS_ACTLR_DISMCYCINT 0x00000001 -#define CPU_SCS_ACTLR_DISMCYCINT_BITN 0 -#define CPU_SCS_ACTLR_DISMCYCINT_M 0x00000001 -#define CPU_SCS_ACTLR_DISMCYCINT_S 0 +#define CPU_SCS_ACTLR_DISMCYCINT 0x00000001 +#define CPU_SCS_ACTLR_DISMCYCINT_BITN 0 +#define CPU_SCS_ACTLR_DISMCYCINT_M 0x00000001 +#define CPU_SCS_ACTLR_DISMCYCINT_S 0 //***************************************************************************** // @@ -290,10 +290,10 @@ // If read by the debugger using the DAP, this bit is cleared on read-only if // the MasterType bit in the **AHB-AP** Control Register is set to 0. // Otherwise, COUNTFLAG is not changed by the debugger read. -#define CPU_SCS_STCSR_COUNTFLAG 0x00010000 -#define CPU_SCS_STCSR_COUNTFLAG_BITN 16 -#define CPU_SCS_STCSR_COUNTFLAG_M 0x00010000 -#define CPU_SCS_STCSR_COUNTFLAG_S 16 +#define CPU_SCS_STCSR_COUNTFLAG 0x00010000 +#define CPU_SCS_STCSR_COUNTFLAG_BITN 16 +#define CPU_SCS_STCSR_COUNTFLAG_M 0x00010000 +#define CPU_SCS_STCSR_COUNTFLAG_S 16 // Field: [2] CLKSOURCE // @@ -304,20 +304,20 @@ // // External clock is not available in this device. Writes to this field will be // ignored. -#define CPU_SCS_STCSR_CLKSOURCE 0x00000004 -#define CPU_SCS_STCSR_CLKSOURCE_BITN 2 -#define CPU_SCS_STCSR_CLKSOURCE_M 0x00000004 -#define CPU_SCS_STCSR_CLKSOURCE_S 2 +#define CPU_SCS_STCSR_CLKSOURCE 0x00000004 +#define CPU_SCS_STCSR_CLKSOURCE_BITN 2 +#define CPU_SCS_STCSR_CLKSOURCE_M 0x00000004 +#define CPU_SCS_STCSR_CLKSOURCE_S 2 // Field: [1] TICKINT // // 0: Counting down to zero does not pend the SysTick handler. Software can use // COUNTFLAG to determine if the SysTick handler has ever counted to zero. // 1: Counting down to zero pends the SysTick handler. -#define CPU_SCS_STCSR_TICKINT 0x00000002 -#define CPU_SCS_STCSR_TICKINT_BITN 1 -#define CPU_SCS_STCSR_TICKINT_M 0x00000002 -#define CPU_SCS_STCSR_TICKINT_S 1 +#define CPU_SCS_STCSR_TICKINT 0x00000002 +#define CPU_SCS_STCSR_TICKINT_BITN 1 +#define CPU_SCS_STCSR_TICKINT_M 0x00000002 +#define CPU_SCS_STCSR_TICKINT_S 1 // Field: [0] ENABLE // @@ -328,10 +328,10 @@ // Reload value STRVR.RELOAD and then begins counting down. On reaching 0, it // sets COUNTFLAG to 1 and optionally pends the SysTick handler, based on // TICKINT. It then loads STRVR.RELOAD again, and begins counting. -#define CPU_SCS_STCSR_ENABLE 0x00000001 -#define CPU_SCS_STCSR_ENABLE_BITN 0 -#define CPU_SCS_STCSR_ENABLE_M 0x00000001 -#define CPU_SCS_STCSR_ENABLE_S 0 +#define CPU_SCS_STCSR_ENABLE 0x00000001 +#define CPU_SCS_STCSR_ENABLE_BITN 0 +#define CPU_SCS_STCSR_ENABLE_M 0x00000001 +#define CPU_SCS_STCSR_ENABLE_S 0 //***************************************************************************** // @@ -342,9 +342,9 @@ // // Value to load into the SysTick Current Value Register STCVR.CURRENT when the // counter reaches 0. -#define CPU_SCS_STRVR_RELOAD_W 24 -#define CPU_SCS_STRVR_RELOAD_M 0x00FFFFFF -#define CPU_SCS_STRVR_RELOAD_S 0 +#define CPU_SCS_STRVR_RELOAD_W 24 +#define CPU_SCS_STRVR_RELOAD_M 0x00FFFFFF +#define CPU_SCS_STRVR_RELOAD_S 0 //***************************************************************************** // @@ -357,9 +357,9 @@ // protection is provided, so change with care. Writing to it with any value // clears the register to 0. Clearing this register also clears // STCSR.COUNTFLAG. -#define CPU_SCS_STCVR_CURRENT_W 24 -#define CPU_SCS_STCVR_CURRENT_M 0x00FFFFFF -#define CPU_SCS_STCVR_CURRENT_S 0 +#define CPU_SCS_STCVR_CURRENT_W 24 +#define CPU_SCS_STCVR_CURRENT_M 0x00FFFFFF +#define CPU_SCS_STCVR_CURRENT_S 0 //***************************************************************************** // @@ -369,28 +369,28 @@ // Field: [31] NOREF // // Reads as one. Indicates that no separate reference clock is provided. -#define CPU_SCS_STCR_NOREF 0x80000000 -#define CPU_SCS_STCR_NOREF_BITN 31 -#define CPU_SCS_STCR_NOREF_M 0x80000000 -#define CPU_SCS_STCR_NOREF_S 31 +#define CPU_SCS_STCR_NOREF 0x80000000 +#define CPU_SCS_STCR_NOREF_BITN 31 +#define CPU_SCS_STCR_NOREF_M 0x80000000 +#define CPU_SCS_STCR_NOREF_S 31 // Field: [30] SKEW // // Reads as one. The calibration value is not exactly 10ms because of clock // frequency. This could affect its suitability as a software real time clock. -#define CPU_SCS_STCR_SKEW 0x40000000 -#define CPU_SCS_STCR_SKEW_BITN 30 -#define CPU_SCS_STCR_SKEW_M 0x40000000 -#define CPU_SCS_STCR_SKEW_S 30 +#define CPU_SCS_STCR_SKEW 0x40000000 +#define CPU_SCS_STCR_SKEW_BITN 30 +#define CPU_SCS_STCR_SKEW_M 0x40000000 +#define CPU_SCS_STCR_SKEW_S 30 // Field: [23:0] TENMS // // An optional Reload value to be used for 10ms (100Hz) timing, subject to // system clock skew errors. The value read is valid only when core clock is at // 48MHz. -#define CPU_SCS_STCR_TENMS_W 24 -#define CPU_SCS_STCR_TENMS_M 0x00FFFFFF -#define CPU_SCS_STCR_TENMS_S 0 +#define CPU_SCS_STCR_TENMS_W 24 +#define CPU_SCS_STCR_TENMS_M 0x00FFFFFF +#define CPU_SCS_STCR_TENMS_S 0 //***************************************************************************** // @@ -402,320 +402,320 @@ // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA31 0x80000000 -#define CPU_SCS_NVIC_ISER0_SETENA31_BITN 31 -#define CPU_SCS_NVIC_ISER0_SETENA31_M 0x80000000 -#define CPU_SCS_NVIC_ISER0_SETENA31_S 31 +#define CPU_SCS_NVIC_ISER0_SETENA31 0x80000000 +#define CPU_SCS_NVIC_ISER0_SETENA31_BITN 31 +#define CPU_SCS_NVIC_ISER0_SETENA31_M 0x80000000 +#define CPU_SCS_NVIC_ISER0_SETENA31_S 31 // Field: [30] SETENA30 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA30 0x40000000 -#define CPU_SCS_NVIC_ISER0_SETENA30_BITN 30 -#define CPU_SCS_NVIC_ISER0_SETENA30_M 0x40000000 -#define CPU_SCS_NVIC_ISER0_SETENA30_S 30 +#define CPU_SCS_NVIC_ISER0_SETENA30 0x40000000 +#define CPU_SCS_NVIC_ISER0_SETENA30_BITN 30 +#define CPU_SCS_NVIC_ISER0_SETENA30_M 0x40000000 +#define CPU_SCS_NVIC_ISER0_SETENA30_S 30 // Field: [29] SETENA29 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA29 0x20000000 -#define CPU_SCS_NVIC_ISER0_SETENA29_BITN 29 -#define CPU_SCS_NVIC_ISER0_SETENA29_M 0x20000000 -#define CPU_SCS_NVIC_ISER0_SETENA29_S 29 +#define CPU_SCS_NVIC_ISER0_SETENA29 0x20000000 +#define CPU_SCS_NVIC_ISER0_SETENA29_BITN 29 +#define CPU_SCS_NVIC_ISER0_SETENA29_M 0x20000000 +#define CPU_SCS_NVIC_ISER0_SETENA29_S 29 // Field: [28] SETENA28 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA28 0x10000000 -#define CPU_SCS_NVIC_ISER0_SETENA28_BITN 28 -#define CPU_SCS_NVIC_ISER0_SETENA28_M 0x10000000 -#define CPU_SCS_NVIC_ISER0_SETENA28_S 28 +#define CPU_SCS_NVIC_ISER0_SETENA28 0x10000000 +#define CPU_SCS_NVIC_ISER0_SETENA28_BITN 28 +#define CPU_SCS_NVIC_ISER0_SETENA28_M 0x10000000 +#define CPU_SCS_NVIC_ISER0_SETENA28_S 28 // Field: [27] SETENA27 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA27 0x08000000 -#define CPU_SCS_NVIC_ISER0_SETENA27_BITN 27 -#define CPU_SCS_NVIC_ISER0_SETENA27_M 0x08000000 -#define CPU_SCS_NVIC_ISER0_SETENA27_S 27 +#define CPU_SCS_NVIC_ISER0_SETENA27 0x08000000 +#define CPU_SCS_NVIC_ISER0_SETENA27_BITN 27 +#define CPU_SCS_NVIC_ISER0_SETENA27_M 0x08000000 +#define CPU_SCS_NVIC_ISER0_SETENA27_S 27 // Field: [26] SETENA26 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA26 0x04000000 -#define CPU_SCS_NVIC_ISER0_SETENA26_BITN 26 -#define CPU_SCS_NVIC_ISER0_SETENA26_M 0x04000000 -#define CPU_SCS_NVIC_ISER0_SETENA26_S 26 +#define CPU_SCS_NVIC_ISER0_SETENA26 0x04000000 +#define CPU_SCS_NVIC_ISER0_SETENA26_BITN 26 +#define CPU_SCS_NVIC_ISER0_SETENA26_M 0x04000000 +#define CPU_SCS_NVIC_ISER0_SETENA26_S 26 // Field: [25] SETENA25 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA25 0x02000000 -#define CPU_SCS_NVIC_ISER0_SETENA25_BITN 25 -#define CPU_SCS_NVIC_ISER0_SETENA25_M 0x02000000 -#define CPU_SCS_NVIC_ISER0_SETENA25_S 25 +#define CPU_SCS_NVIC_ISER0_SETENA25 0x02000000 +#define CPU_SCS_NVIC_ISER0_SETENA25_BITN 25 +#define CPU_SCS_NVIC_ISER0_SETENA25_M 0x02000000 +#define CPU_SCS_NVIC_ISER0_SETENA25_S 25 // Field: [24] SETENA24 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA24 0x01000000 -#define CPU_SCS_NVIC_ISER0_SETENA24_BITN 24 -#define CPU_SCS_NVIC_ISER0_SETENA24_M 0x01000000 -#define CPU_SCS_NVIC_ISER0_SETENA24_S 24 +#define CPU_SCS_NVIC_ISER0_SETENA24 0x01000000 +#define CPU_SCS_NVIC_ISER0_SETENA24_BITN 24 +#define CPU_SCS_NVIC_ISER0_SETENA24_M 0x01000000 +#define CPU_SCS_NVIC_ISER0_SETENA24_S 24 // Field: [23] SETENA23 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA23 0x00800000 -#define CPU_SCS_NVIC_ISER0_SETENA23_BITN 23 -#define CPU_SCS_NVIC_ISER0_SETENA23_M 0x00800000 -#define CPU_SCS_NVIC_ISER0_SETENA23_S 23 +#define CPU_SCS_NVIC_ISER0_SETENA23 0x00800000 +#define CPU_SCS_NVIC_ISER0_SETENA23_BITN 23 +#define CPU_SCS_NVIC_ISER0_SETENA23_M 0x00800000 +#define CPU_SCS_NVIC_ISER0_SETENA23_S 23 // Field: [22] SETENA22 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA22 0x00400000 -#define CPU_SCS_NVIC_ISER0_SETENA22_BITN 22 -#define CPU_SCS_NVIC_ISER0_SETENA22_M 0x00400000 -#define CPU_SCS_NVIC_ISER0_SETENA22_S 22 +#define CPU_SCS_NVIC_ISER0_SETENA22 0x00400000 +#define CPU_SCS_NVIC_ISER0_SETENA22_BITN 22 +#define CPU_SCS_NVIC_ISER0_SETENA22_M 0x00400000 +#define CPU_SCS_NVIC_ISER0_SETENA22_S 22 // Field: [21] SETENA21 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA21 0x00200000 -#define CPU_SCS_NVIC_ISER0_SETENA21_BITN 21 -#define CPU_SCS_NVIC_ISER0_SETENA21_M 0x00200000 -#define CPU_SCS_NVIC_ISER0_SETENA21_S 21 +#define CPU_SCS_NVIC_ISER0_SETENA21 0x00200000 +#define CPU_SCS_NVIC_ISER0_SETENA21_BITN 21 +#define CPU_SCS_NVIC_ISER0_SETENA21_M 0x00200000 +#define CPU_SCS_NVIC_ISER0_SETENA21_S 21 // Field: [20] SETENA20 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA20 0x00100000 -#define CPU_SCS_NVIC_ISER0_SETENA20_BITN 20 -#define CPU_SCS_NVIC_ISER0_SETENA20_M 0x00100000 -#define CPU_SCS_NVIC_ISER0_SETENA20_S 20 +#define CPU_SCS_NVIC_ISER0_SETENA20 0x00100000 +#define CPU_SCS_NVIC_ISER0_SETENA20_BITN 20 +#define CPU_SCS_NVIC_ISER0_SETENA20_M 0x00100000 +#define CPU_SCS_NVIC_ISER0_SETENA20_S 20 // Field: [19] SETENA19 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA19 0x00080000 -#define CPU_SCS_NVIC_ISER0_SETENA19_BITN 19 -#define CPU_SCS_NVIC_ISER0_SETENA19_M 0x00080000 -#define CPU_SCS_NVIC_ISER0_SETENA19_S 19 +#define CPU_SCS_NVIC_ISER0_SETENA19 0x00080000 +#define CPU_SCS_NVIC_ISER0_SETENA19_BITN 19 +#define CPU_SCS_NVIC_ISER0_SETENA19_M 0x00080000 +#define CPU_SCS_NVIC_ISER0_SETENA19_S 19 // Field: [18] SETENA18 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA18 0x00040000 -#define CPU_SCS_NVIC_ISER0_SETENA18_BITN 18 -#define CPU_SCS_NVIC_ISER0_SETENA18_M 0x00040000 -#define CPU_SCS_NVIC_ISER0_SETENA18_S 18 +#define CPU_SCS_NVIC_ISER0_SETENA18 0x00040000 +#define CPU_SCS_NVIC_ISER0_SETENA18_BITN 18 +#define CPU_SCS_NVIC_ISER0_SETENA18_M 0x00040000 +#define CPU_SCS_NVIC_ISER0_SETENA18_S 18 // Field: [17] SETENA17 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA17 0x00020000 -#define CPU_SCS_NVIC_ISER0_SETENA17_BITN 17 -#define CPU_SCS_NVIC_ISER0_SETENA17_M 0x00020000 -#define CPU_SCS_NVIC_ISER0_SETENA17_S 17 +#define CPU_SCS_NVIC_ISER0_SETENA17 0x00020000 +#define CPU_SCS_NVIC_ISER0_SETENA17_BITN 17 +#define CPU_SCS_NVIC_ISER0_SETENA17_M 0x00020000 +#define CPU_SCS_NVIC_ISER0_SETENA17_S 17 // Field: [16] SETENA16 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA16 0x00010000 -#define CPU_SCS_NVIC_ISER0_SETENA16_BITN 16 -#define CPU_SCS_NVIC_ISER0_SETENA16_M 0x00010000 -#define CPU_SCS_NVIC_ISER0_SETENA16_S 16 +#define CPU_SCS_NVIC_ISER0_SETENA16 0x00010000 +#define CPU_SCS_NVIC_ISER0_SETENA16_BITN 16 +#define CPU_SCS_NVIC_ISER0_SETENA16_M 0x00010000 +#define CPU_SCS_NVIC_ISER0_SETENA16_S 16 // Field: [15] SETENA15 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA15 0x00008000 -#define CPU_SCS_NVIC_ISER0_SETENA15_BITN 15 -#define CPU_SCS_NVIC_ISER0_SETENA15_M 0x00008000 -#define CPU_SCS_NVIC_ISER0_SETENA15_S 15 +#define CPU_SCS_NVIC_ISER0_SETENA15 0x00008000 +#define CPU_SCS_NVIC_ISER0_SETENA15_BITN 15 +#define CPU_SCS_NVIC_ISER0_SETENA15_M 0x00008000 +#define CPU_SCS_NVIC_ISER0_SETENA15_S 15 // Field: [14] SETENA14 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA14 0x00004000 -#define CPU_SCS_NVIC_ISER0_SETENA14_BITN 14 -#define CPU_SCS_NVIC_ISER0_SETENA14_M 0x00004000 -#define CPU_SCS_NVIC_ISER0_SETENA14_S 14 +#define CPU_SCS_NVIC_ISER0_SETENA14 0x00004000 +#define CPU_SCS_NVIC_ISER0_SETENA14_BITN 14 +#define CPU_SCS_NVIC_ISER0_SETENA14_M 0x00004000 +#define CPU_SCS_NVIC_ISER0_SETENA14_S 14 // Field: [13] SETENA13 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA13 0x00002000 -#define CPU_SCS_NVIC_ISER0_SETENA13_BITN 13 -#define CPU_SCS_NVIC_ISER0_SETENA13_M 0x00002000 -#define CPU_SCS_NVIC_ISER0_SETENA13_S 13 +#define CPU_SCS_NVIC_ISER0_SETENA13 0x00002000 +#define CPU_SCS_NVIC_ISER0_SETENA13_BITN 13 +#define CPU_SCS_NVIC_ISER0_SETENA13_M 0x00002000 +#define CPU_SCS_NVIC_ISER0_SETENA13_S 13 // Field: [12] SETENA12 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA12 0x00001000 -#define CPU_SCS_NVIC_ISER0_SETENA12_BITN 12 -#define CPU_SCS_NVIC_ISER0_SETENA12_M 0x00001000 -#define CPU_SCS_NVIC_ISER0_SETENA12_S 12 +#define CPU_SCS_NVIC_ISER0_SETENA12 0x00001000 +#define CPU_SCS_NVIC_ISER0_SETENA12_BITN 12 +#define CPU_SCS_NVIC_ISER0_SETENA12_M 0x00001000 +#define CPU_SCS_NVIC_ISER0_SETENA12_S 12 // Field: [11] SETENA11 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA11 0x00000800 -#define CPU_SCS_NVIC_ISER0_SETENA11_BITN 11 -#define CPU_SCS_NVIC_ISER0_SETENA11_M 0x00000800 -#define CPU_SCS_NVIC_ISER0_SETENA11_S 11 +#define CPU_SCS_NVIC_ISER0_SETENA11 0x00000800 +#define CPU_SCS_NVIC_ISER0_SETENA11_BITN 11 +#define CPU_SCS_NVIC_ISER0_SETENA11_M 0x00000800 +#define CPU_SCS_NVIC_ISER0_SETENA11_S 11 // Field: [10] SETENA10 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA10 0x00000400 -#define CPU_SCS_NVIC_ISER0_SETENA10_BITN 10 -#define CPU_SCS_NVIC_ISER0_SETENA10_M 0x00000400 -#define CPU_SCS_NVIC_ISER0_SETENA10_S 10 +#define CPU_SCS_NVIC_ISER0_SETENA10 0x00000400 +#define CPU_SCS_NVIC_ISER0_SETENA10_BITN 10 +#define CPU_SCS_NVIC_ISER0_SETENA10_M 0x00000400 +#define CPU_SCS_NVIC_ISER0_SETENA10_S 10 // Field: [9] SETENA9 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA9 0x00000200 -#define CPU_SCS_NVIC_ISER0_SETENA9_BITN 9 -#define CPU_SCS_NVIC_ISER0_SETENA9_M 0x00000200 -#define CPU_SCS_NVIC_ISER0_SETENA9_S 9 +#define CPU_SCS_NVIC_ISER0_SETENA9 0x00000200 +#define CPU_SCS_NVIC_ISER0_SETENA9_BITN 9 +#define CPU_SCS_NVIC_ISER0_SETENA9_M 0x00000200 +#define CPU_SCS_NVIC_ISER0_SETENA9_S 9 // Field: [8] SETENA8 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA8 0x00000100 -#define CPU_SCS_NVIC_ISER0_SETENA8_BITN 8 -#define CPU_SCS_NVIC_ISER0_SETENA8_M 0x00000100 -#define CPU_SCS_NVIC_ISER0_SETENA8_S 8 +#define CPU_SCS_NVIC_ISER0_SETENA8 0x00000100 +#define CPU_SCS_NVIC_ISER0_SETENA8_BITN 8 +#define CPU_SCS_NVIC_ISER0_SETENA8_M 0x00000100 +#define CPU_SCS_NVIC_ISER0_SETENA8_S 8 // Field: [7] SETENA7 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA7 0x00000080 -#define CPU_SCS_NVIC_ISER0_SETENA7_BITN 7 -#define CPU_SCS_NVIC_ISER0_SETENA7_M 0x00000080 -#define CPU_SCS_NVIC_ISER0_SETENA7_S 7 +#define CPU_SCS_NVIC_ISER0_SETENA7 0x00000080 +#define CPU_SCS_NVIC_ISER0_SETENA7_BITN 7 +#define CPU_SCS_NVIC_ISER0_SETENA7_M 0x00000080 +#define CPU_SCS_NVIC_ISER0_SETENA7_S 7 // Field: [6] SETENA6 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA6 0x00000040 -#define CPU_SCS_NVIC_ISER0_SETENA6_BITN 6 -#define CPU_SCS_NVIC_ISER0_SETENA6_M 0x00000040 -#define CPU_SCS_NVIC_ISER0_SETENA6_S 6 +#define CPU_SCS_NVIC_ISER0_SETENA6 0x00000040 +#define CPU_SCS_NVIC_ISER0_SETENA6_BITN 6 +#define CPU_SCS_NVIC_ISER0_SETENA6_M 0x00000040 +#define CPU_SCS_NVIC_ISER0_SETENA6_S 6 // Field: [5] SETENA5 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA5 0x00000020 -#define CPU_SCS_NVIC_ISER0_SETENA5_BITN 5 -#define CPU_SCS_NVIC_ISER0_SETENA5_M 0x00000020 -#define CPU_SCS_NVIC_ISER0_SETENA5_S 5 +#define CPU_SCS_NVIC_ISER0_SETENA5 0x00000020 +#define CPU_SCS_NVIC_ISER0_SETENA5_BITN 5 +#define CPU_SCS_NVIC_ISER0_SETENA5_M 0x00000020 +#define CPU_SCS_NVIC_ISER0_SETENA5_S 5 // Field: [4] SETENA4 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA4 0x00000010 -#define CPU_SCS_NVIC_ISER0_SETENA4_BITN 4 -#define CPU_SCS_NVIC_ISER0_SETENA4_M 0x00000010 -#define CPU_SCS_NVIC_ISER0_SETENA4_S 4 +#define CPU_SCS_NVIC_ISER0_SETENA4 0x00000010 +#define CPU_SCS_NVIC_ISER0_SETENA4_BITN 4 +#define CPU_SCS_NVIC_ISER0_SETENA4_M 0x00000010 +#define CPU_SCS_NVIC_ISER0_SETENA4_S 4 // Field: [3] SETENA3 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA3 0x00000008 -#define CPU_SCS_NVIC_ISER0_SETENA3_BITN 3 -#define CPU_SCS_NVIC_ISER0_SETENA3_M 0x00000008 -#define CPU_SCS_NVIC_ISER0_SETENA3_S 3 +#define CPU_SCS_NVIC_ISER0_SETENA3 0x00000008 +#define CPU_SCS_NVIC_ISER0_SETENA3_BITN 3 +#define CPU_SCS_NVIC_ISER0_SETENA3_M 0x00000008 +#define CPU_SCS_NVIC_ISER0_SETENA3_S 3 // Field: [2] SETENA2 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA2 0x00000004 -#define CPU_SCS_NVIC_ISER0_SETENA2_BITN 2 -#define CPU_SCS_NVIC_ISER0_SETENA2_M 0x00000004 -#define CPU_SCS_NVIC_ISER0_SETENA2_S 2 +#define CPU_SCS_NVIC_ISER0_SETENA2 0x00000004 +#define CPU_SCS_NVIC_ISER0_SETENA2_BITN 2 +#define CPU_SCS_NVIC_ISER0_SETENA2_M 0x00000004 +#define CPU_SCS_NVIC_ISER0_SETENA2_S 2 // Field: [1] SETENA1 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA1 0x00000002 -#define CPU_SCS_NVIC_ISER0_SETENA1_BITN 1 -#define CPU_SCS_NVIC_ISER0_SETENA1_M 0x00000002 -#define CPU_SCS_NVIC_ISER0_SETENA1_S 1 +#define CPU_SCS_NVIC_ISER0_SETENA1 0x00000002 +#define CPU_SCS_NVIC_ISER0_SETENA1_BITN 1 +#define CPU_SCS_NVIC_ISER0_SETENA1_M 0x00000002 +#define CPU_SCS_NVIC_ISER0_SETENA1_S 1 // Field: [0] SETENA0 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA0 0x00000001 -#define CPU_SCS_NVIC_ISER0_SETENA0_BITN 0 -#define CPU_SCS_NVIC_ISER0_SETENA0_M 0x00000001 -#define CPU_SCS_NVIC_ISER0_SETENA0_S 0 +#define CPU_SCS_NVIC_ISER0_SETENA0 0x00000001 +#define CPU_SCS_NVIC_ISER0_SETENA0_BITN 0 +#define CPU_SCS_NVIC_ISER0_SETENA0_M 0x00000001 +#define CPU_SCS_NVIC_ISER0_SETENA0_S 0 //***************************************************************************** // @@ -727,20 +727,20 @@ // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER1_SETENA33 0x00000002 -#define CPU_SCS_NVIC_ISER1_SETENA33_BITN 1 -#define CPU_SCS_NVIC_ISER1_SETENA33_M 0x00000002 -#define CPU_SCS_NVIC_ISER1_SETENA33_S 1 +#define CPU_SCS_NVIC_ISER1_SETENA33 0x00000002 +#define CPU_SCS_NVIC_ISER1_SETENA33_BITN 1 +#define CPU_SCS_NVIC_ISER1_SETENA33_M 0x00000002 +#define CPU_SCS_NVIC_ISER1_SETENA33_S 1 // Field: [0] SETENA32 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER1_SETENA32 0x00000001 -#define CPU_SCS_NVIC_ISER1_SETENA32_BITN 0 -#define CPU_SCS_NVIC_ISER1_SETENA32_M 0x00000001 -#define CPU_SCS_NVIC_ISER1_SETENA32_S 0 +#define CPU_SCS_NVIC_ISER1_SETENA32 0x00000001 +#define CPU_SCS_NVIC_ISER1_SETENA32_BITN 0 +#define CPU_SCS_NVIC_ISER1_SETENA32_M 0x00000001 +#define CPU_SCS_NVIC_ISER1_SETENA32_S 0 //***************************************************************************** // @@ -752,320 +752,320 @@ // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA31 0x80000000 -#define CPU_SCS_NVIC_ICER0_CLRENA31_BITN 31 -#define CPU_SCS_NVIC_ICER0_CLRENA31_M 0x80000000 -#define CPU_SCS_NVIC_ICER0_CLRENA31_S 31 +#define CPU_SCS_NVIC_ICER0_CLRENA31 0x80000000 +#define CPU_SCS_NVIC_ICER0_CLRENA31_BITN 31 +#define CPU_SCS_NVIC_ICER0_CLRENA31_M 0x80000000 +#define CPU_SCS_NVIC_ICER0_CLRENA31_S 31 // Field: [30] CLRENA30 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA30 0x40000000 -#define CPU_SCS_NVIC_ICER0_CLRENA30_BITN 30 -#define CPU_SCS_NVIC_ICER0_CLRENA30_M 0x40000000 -#define CPU_SCS_NVIC_ICER0_CLRENA30_S 30 +#define CPU_SCS_NVIC_ICER0_CLRENA30 0x40000000 +#define CPU_SCS_NVIC_ICER0_CLRENA30_BITN 30 +#define CPU_SCS_NVIC_ICER0_CLRENA30_M 0x40000000 +#define CPU_SCS_NVIC_ICER0_CLRENA30_S 30 // Field: [29] CLRENA29 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA29 0x20000000 -#define CPU_SCS_NVIC_ICER0_CLRENA29_BITN 29 -#define CPU_SCS_NVIC_ICER0_CLRENA29_M 0x20000000 -#define CPU_SCS_NVIC_ICER0_CLRENA29_S 29 +#define CPU_SCS_NVIC_ICER0_CLRENA29 0x20000000 +#define CPU_SCS_NVIC_ICER0_CLRENA29_BITN 29 +#define CPU_SCS_NVIC_ICER0_CLRENA29_M 0x20000000 +#define CPU_SCS_NVIC_ICER0_CLRENA29_S 29 // Field: [28] CLRENA28 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA28 0x10000000 -#define CPU_SCS_NVIC_ICER0_CLRENA28_BITN 28 -#define CPU_SCS_NVIC_ICER0_CLRENA28_M 0x10000000 -#define CPU_SCS_NVIC_ICER0_CLRENA28_S 28 +#define CPU_SCS_NVIC_ICER0_CLRENA28 0x10000000 +#define CPU_SCS_NVIC_ICER0_CLRENA28_BITN 28 +#define CPU_SCS_NVIC_ICER0_CLRENA28_M 0x10000000 +#define CPU_SCS_NVIC_ICER0_CLRENA28_S 28 // Field: [27] CLRENA27 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA27 0x08000000 -#define CPU_SCS_NVIC_ICER0_CLRENA27_BITN 27 -#define CPU_SCS_NVIC_ICER0_CLRENA27_M 0x08000000 -#define CPU_SCS_NVIC_ICER0_CLRENA27_S 27 +#define CPU_SCS_NVIC_ICER0_CLRENA27 0x08000000 +#define CPU_SCS_NVIC_ICER0_CLRENA27_BITN 27 +#define CPU_SCS_NVIC_ICER0_CLRENA27_M 0x08000000 +#define CPU_SCS_NVIC_ICER0_CLRENA27_S 27 // Field: [26] CLRENA26 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA26 0x04000000 -#define CPU_SCS_NVIC_ICER0_CLRENA26_BITN 26 -#define CPU_SCS_NVIC_ICER0_CLRENA26_M 0x04000000 -#define CPU_SCS_NVIC_ICER0_CLRENA26_S 26 +#define CPU_SCS_NVIC_ICER0_CLRENA26 0x04000000 +#define CPU_SCS_NVIC_ICER0_CLRENA26_BITN 26 +#define CPU_SCS_NVIC_ICER0_CLRENA26_M 0x04000000 +#define CPU_SCS_NVIC_ICER0_CLRENA26_S 26 // Field: [25] CLRENA25 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA25 0x02000000 -#define CPU_SCS_NVIC_ICER0_CLRENA25_BITN 25 -#define CPU_SCS_NVIC_ICER0_CLRENA25_M 0x02000000 -#define CPU_SCS_NVIC_ICER0_CLRENA25_S 25 +#define CPU_SCS_NVIC_ICER0_CLRENA25 0x02000000 +#define CPU_SCS_NVIC_ICER0_CLRENA25_BITN 25 +#define CPU_SCS_NVIC_ICER0_CLRENA25_M 0x02000000 +#define CPU_SCS_NVIC_ICER0_CLRENA25_S 25 // Field: [24] CLRENA24 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA24 0x01000000 -#define CPU_SCS_NVIC_ICER0_CLRENA24_BITN 24 -#define CPU_SCS_NVIC_ICER0_CLRENA24_M 0x01000000 -#define CPU_SCS_NVIC_ICER0_CLRENA24_S 24 +#define CPU_SCS_NVIC_ICER0_CLRENA24 0x01000000 +#define CPU_SCS_NVIC_ICER0_CLRENA24_BITN 24 +#define CPU_SCS_NVIC_ICER0_CLRENA24_M 0x01000000 +#define CPU_SCS_NVIC_ICER0_CLRENA24_S 24 // Field: [23] CLRENA23 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA23 0x00800000 -#define CPU_SCS_NVIC_ICER0_CLRENA23_BITN 23 -#define CPU_SCS_NVIC_ICER0_CLRENA23_M 0x00800000 -#define CPU_SCS_NVIC_ICER0_CLRENA23_S 23 +#define CPU_SCS_NVIC_ICER0_CLRENA23 0x00800000 +#define CPU_SCS_NVIC_ICER0_CLRENA23_BITN 23 +#define CPU_SCS_NVIC_ICER0_CLRENA23_M 0x00800000 +#define CPU_SCS_NVIC_ICER0_CLRENA23_S 23 // Field: [22] CLRENA22 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA22 0x00400000 -#define CPU_SCS_NVIC_ICER0_CLRENA22_BITN 22 -#define CPU_SCS_NVIC_ICER0_CLRENA22_M 0x00400000 -#define CPU_SCS_NVIC_ICER0_CLRENA22_S 22 +#define CPU_SCS_NVIC_ICER0_CLRENA22 0x00400000 +#define CPU_SCS_NVIC_ICER0_CLRENA22_BITN 22 +#define CPU_SCS_NVIC_ICER0_CLRENA22_M 0x00400000 +#define CPU_SCS_NVIC_ICER0_CLRENA22_S 22 // Field: [21] CLRENA21 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA21 0x00200000 -#define CPU_SCS_NVIC_ICER0_CLRENA21_BITN 21 -#define CPU_SCS_NVIC_ICER0_CLRENA21_M 0x00200000 -#define CPU_SCS_NVIC_ICER0_CLRENA21_S 21 +#define CPU_SCS_NVIC_ICER0_CLRENA21 0x00200000 +#define CPU_SCS_NVIC_ICER0_CLRENA21_BITN 21 +#define CPU_SCS_NVIC_ICER0_CLRENA21_M 0x00200000 +#define CPU_SCS_NVIC_ICER0_CLRENA21_S 21 // Field: [20] CLRENA20 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA20 0x00100000 -#define CPU_SCS_NVIC_ICER0_CLRENA20_BITN 20 -#define CPU_SCS_NVIC_ICER0_CLRENA20_M 0x00100000 -#define CPU_SCS_NVIC_ICER0_CLRENA20_S 20 +#define CPU_SCS_NVIC_ICER0_CLRENA20 0x00100000 +#define CPU_SCS_NVIC_ICER0_CLRENA20_BITN 20 +#define CPU_SCS_NVIC_ICER0_CLRENA20_M 0x00100000 +#define CPU_SCS_NVIC_ICER0_CLRENA20_S 20 // Field: [19] CLRENA19 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA19 0x00080000 -#define CPU_SCS_NVIC_ICER0_CLRENA19_BITN 19 -#define CPU_SCS_NVIC_ICER0_CLRENA19_M 0x00080000 -#define CPU_SCS_NVIC_ICER0_CLRENA19_S 19 +#define CPU_SCS_NVIC_ICER0_CLRENA19 0x00080000 +#define CPU_SCS_NVIC_ICER0_CLRENA19_BITN 19 +#define CPU_SCS_NVIC_ICER0_CLRENA19_M 0x00080000 +#define CPU_SCS_NVIC_ICER0_CLRENA19_S 19 // Field: [18] CLRENA18 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA18 0x00040000 -#define CPU_SCS_NVIC_ICER0_CLRENA18_BITN 18 -#define CPU_SCS_NVIC_ICER0_CLRENA18_M 0x00040000 -#define CPU_SCS_NVIC_ICER0_CLRENA18_S 18 +#define CPU_SCS_NVIC_ICER0_CLRENA18 0x00040000 +#define CPU_SCS_NVIC_ICER0_CLRENA18_BITN 18 +#define CPU_SCS_NVIC_ICER0_CLRENA18_M 0x00040000 +#define CPU_SCS_NVIC_ICER0_CLRENA18_S 18 // Field: [17] CLRENA17 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA17 0x00020000 -#define CPU_SCS_NVIC_ICER0_CLRENA17_BITN 17 -#define CPU_SCS_NVIC_ICER0_CLRENA17_M 0x00020000 -#define CPU_SCS_NVIC_ICER0_CLRENA17_S 17 +#define CPU_SCS_NVIC_ICER0_CLRENA17 0x00020000 +#define CPU_SCS_NVIC_ICER0_CLRENA17_BITN 17 +#define CPU_SCS_NVIC_ICER0_CLRENA17_M 0x00020000 +#define CPU_SCS_NVIC_ICER0_CLRENA17_S 17 // Field: [16] CLRENA16 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA16 0x00010000 -#define CPU_SCS_NVIC_ICER0_CLRENA16_BITN 16 -#define CPU_SCS_NVIC_ICER0_CLRENA16_M 0x00010000 -#define CPU_SCS_NVIC_ICER0_CLRENA16_S 16 +#define CPU_SCS_NVIC_ICER0_CLRENA16 0x00010000 +#define CPU_SCS_NVIC_ICER0_CLRENA16_BITN 16 +#define CPU_SCS_NVIC_ICER0_CLRENA16_M 0x00010000 +#define CPU_SCS_NVIC_ICER0_CLRENA16_S 16 // Field: [15] CLRENA15 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA15 0x00008000 -#define CPU_SCS_NVIC_ICER0_CLRENA15_BITN 15 -#define CPU_SCS_NVIC_ICER0_CLRENA15_M 0x00008000 -#define CPU_SCS_NVIC_ICER0_CLRENA15_S 15 +#define CPU_SCS_NVIC_ICER0_CLRENA15 0x00008000 +#define CPU_SCS_NVIC_ICER0_CLRENA15_BITN 15 +#define CPU_SCS_NVIC_ICER0_CLRENA15_M 0x00008000 +#define CPU_SCS_NVIC_ICER0_CLRENA15_S 15 // Field: [14] CLRENA14 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA14 0x00004000 -#define CPU_SCS_NVIC_ICER0_CLRENA14_BITN 14 -#define CPU_SCS_NVIC_ICER0_CLRENA14_M 0x00004000 -#define CPU_SCS_NVIC_ICER0_CLRENA14_S 14 +#define CPU_SCS_NVIC_ICER0_CLRENA14 0x00004000 +#define CPU_SCS_NVIC_ICER0_CLRENA14_BITN 14 +#define CPU_SCS_NVIC_ICER0_CLRENA14_M 0x00004000 +#define CPU_SCS_NVIC_ICER0_CLRENA14_S 14 // Field: [13] CLRENA13 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA13 0x00002000 -#define CPU_SCS_NVIC_ICER0_CLRENA13_BITN 13 -#define CPU_SCS_NVIC_ICER0_CLRENA13_M 0x00002000 -#define CPU_SCS_NVIC_ICER0_CLRENA13_S 13 +#define CPU_SCS_NVIC_ICER0_CLRENA13 0x00002000 +#define CPU_SCS_NVIC_ICER0_CLRENA13_BITN 13 +#define CPU_SCS_NVIC_ICER0_CLRENA13_M 0x00002000 +#define CPU_SCS_NVIC_ICER0_CLRENA13_S 13 // Field: [12] CLRENA12 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA12 0x00001000 -#define CPU_SCS_NVIC_ICER0_CLRENA12_BITN 12 -#define CPU_SCS_NVIC_ICER0_CLRENA12_M 0x00001000 -#define CPU_SCS_NVIC_ICER0_CLRENA12_S 12 +#define CPU_SCS_NVIC_ICER0_CLRENA12 0x00001000 +#define CPU_SCS_NVIC_ICER0_CLRENA12_BITN 12 +#define CPU_SCS_NVIC_ICER0_CLRENA12_M 0x00001000 +#define CPU_SCS_NVIC_ICER0_CLRENA12_S 12 // Field: [11] CLRENA11 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA11 0x00000800 -#define CPU_SCS_NVIC_ICER0_CLRENA11_BITN 11 -#define CPU_SCS_NVIC_ICER0_CLRENA11_M 0x00000800 -#define CPU_SCS_NVIC_ICER0_CLRENA11_S 11 +#define CPU_SCS_NVIC_ICER0_CLRENA11 0x00000800 +#define CPU_SCS_NVIC_ICER0_CLRENA11_BITN 11 +#define CPU_SCS_NVIC_ICER0_CLRENA11_M 0x00000800 +#define CPU_SCS_NVIC_ICER0_CLRENA11_S 11 // Field: [10] CLRENA10 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA10 0x00000400 -#define CPU_SCS_NVIC_ICER0_CLRENA10_BITN 10 -#define CPU_SCS_NVIC_ICER0_CLRENA10_M 0x00000400 -#define CPU_SCS_NVIC_ICER0_CLRENA10_S 10 +#define CPU_SCS_NVIC_ICER0_CLRENA10 0x00000400 +#define CPU_SCS_NVIC_ICER0_CLRENA10_BITN 10 +#define CPU_SCS_NVIC_ICER0_CLRENA10_M 0x00000400 +#define CPU_SCS_NVIC_ICER0_CLRENA10_S 10 // Field: [9] CLRENA9 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA9 0x00000200 -#define CPU_SCS_NVIC_ICER0_CLRENA9_BITN 9 -#define CPU_SCS_NVIC_ICER0_CLRENA9_M 0x00000200 -#define CPU_SCS_NVIC_ICER0_CLRENA9_S 9 +#define CPU_SCS_NVIC_ICER0_CLRENA9 0x00000200 +#define CPU_SCS_NVIC_ICER0_CLRENA9_BITN 9 +#define CPU_SCS_NVIC_ICER0_CLRENA9_M 0x00000200 +#define CPU_SCS_NVIC_ICER0_CLRENA9_S 9 // Field: [8] CLRENA8 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA8 0x00000100 -#define CPU_SCS_NVIC_ICER0_CLRENA8_BITN 8 -#define CPU_SCS_NVIC_ICER0_CLRENA8_M 0x00000100 -#define CPU_SCS_NVIC_ICER0_CLRENA8_S 8 +#define CPU_SCS_NVIC_ICER0_CLRENA8 0x00000100 +#define CPU_SCS_NVIC_ICER0_CLRENA8_BITN 8 +#define CPU_SCS_NVIC_ICER0_CLRENA8_M 0x00000100 +#define CPU_SCS_NVIC_ICER0_CLRENA8_S 8 // Field: [7] CLRENA7 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA7 0x00000080 -#define CPU_SCS_NVIC_ICER0_CLRENA7_BITN 7 -#define CPU_SCS_NVIC_ICER0_CLRENA7_M 0x00000080 -#define CPU_SCS_NVIC_ICER0_CLRENA7_S 7 +#define CPU_SCS_NVIC_ICER0_CLRENA7 0x00000080 +#define CPU_SCS_NVIC_ICER0_CLRENA7_BITN 7 +#define CPU_SCS_NVIC_ICER0_CLRENA7_M 0x00000080 +#define CPU_SCS_NVIC_ICER0_CLRENA7_S 7 // Field: [6] CLRENA6 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA6 0x00000040 -#define CPU_SCS_NVIC_ICER0_CLRENA6_BITN 6 -#define CPU_SCS_NVIC_ICER0_CLRENA6_M 0x00000040 -#define CPU_SCS_NVIC_ICER0_CLRENA6_S 6 +#define CPU_SCS_NVIC_ICER0_CLRENA6 0x00000040 +#define CPU_SCS_NVIC_ICER0_CLRENA6_BITN 6 +#define CPU_SCS_NVIC_ICER0_CLRENA6_M 0x00000040 +#define CPU_SCS_NVIC_ICER0_CLRENA6_S 6 // Field: [5] CLRENA5 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA5 0x00000020 -#define CPU_SCS_NVIC_ICER0_CLRENA5_BITN 5 -#define CPU_SCS_NVIC_ICER0_CLRENA5_M 0x00000020 -#define CPU_SCS_NVIC_ICER0_CLRENA5_S 5 +#define CPU_SCS_NVIC_ICER0_CLRENA5 0x00000020 +#define CPU_SCS_NVIC_ICER0_CLRENA5_BITN 5 +#define CPU_SCS_NVIC_ICER0_CLRENA5_M 0x00000020 +#define CPU_SCS_NVIC_ICER0_CLRENA5_S 5 // Field: [4] CLRENA4 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA4 0x00000010 -#define CPU_SCS_NVIC_ICER0_CLRENA4_BITN 4 -#define CPU_SCS_NVIC_ICER0_CLRENA4_M 0x00000010 -#define CPU_SCS_NVIC_ICER0_CLRENA4_S 4 +#define CPU_SCS_NVIC_ICER0_CLRENA4 0x00000010 +#define CPU_SCS_NVIC_ICER0_CLRENA4_BITN 4 +#define CPU_SCS_NVIC_ICER0_CLRENA4_M 0x00000010 +#define CPU_SCS_NVIC_ICER0_CLRENA4_S 4 // Field: [3] CLRENA3 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA3 0x00000008 -#define CPU_SCS_NVIC_ICER0_CLRENA3_BITN 3 -#define CPU_SCS_NVIC_ICER0_CLRENA3_M 0x00000008 -#define CPU_SCS_NVIC_ICER0_CLRENA3_S 3 +#define CPU_SCS_NVIC_ICER0_CLRENA3 0x00000008 +#define CPU_SCS_NVIC_ICER0_CLRENA3_BITN 3 +#define CPU_SCS_NVIC_ICER0_CLRENA3_M 0x00000008 +#define CPU_SCS_NVIC_ICER0_CLRENA3_S 3 // Field: [2] CLRENA2 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA2 0x00000004 -#define CPU_SCS_NVIC_ICER0_CLRENA2_BITN 2 -#define CPU_SCS_NVIC_ICER0_CLRENA2_M 0x00000004 -#define CPU_SCS_NVIC_ICER0_CLRENA2_S 2 +#define CPU_SCS_NVIC_ICER0_CLRENA2 0x00000004 +#define CPU_SCS_NVIC_ICER0_CLRENA2_BITN 2 +#define CPU_SCS_NVIC_ICER0_CLRENA2_M 0x00000004 +#define CPU_SCS_NVIC_ICER0_CLRENA2_S 2 // Field: [1] CLRENA1 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA1 0x00000002 -#define CPU_SCS_NVIC_ICER0_CLRENA1_BITN 1 -#define CPU_SCS_NVIC_ICER0_CLRENA1_M 0x00000002 -#define CPU_SCS_NVIC_ICER0_CLRENA1_S 1 +#define CPU_SCS_NVIC_ICER0_CLRENA1 0x00000002 +#define CPU_SCS_NVIC_ICER0_CLRENA1_BITN 1 +#define CPU_SCS_NVIC_ICER0_CLRENA1_M 0x00000002 +#define CPU_SCS_NVIC_ICER0_CLRENA1_S 1 // Field: [0] CLRENA0 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA0 0x00000001 -#define CPU_SCS_NVIC_ICER0_CLRENA0_BITN 0 -#define CPU_SCS_NVIC_ICER0_CLRENA0_M 0x00000001 -#define CPU_SCS_NVIC_ICER0_CLRENA0_S 0 +#define CPU_SCS_NVIC_ICER0_CLRENA0 0x00000001 +#define CPU_SCS_NVIC_ICER0_CLRENA0_BITN 0 +#define CPU_SCS_NVIC_ICER0_CLRENA0_M 0x00000001 +#define CPU_SCS_NVIC_ICER0_CLRENA0_S 0 //***************************************************************************** // @@ -1077,20 +1077,20 @@ // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER1_CLRENA33 0x00000002 -#define CPU_SCS_NVIC_ICER1_CLRENA33_BITN 1 -#define CPU_SCS_NVIC_ICER1_CLRENA33_M 0x00000002 -#define CPU_SCS_NVIC_ICER1_CLRENA33_S 1 +#define CPU_SCS_NVIC_ICER1_CLRENA33 0x00000002 +#define CPU_SCS_NVIC_ICER1_CLRENA33_BITN 1 +#define CPU_SCS_NVIC_ICER1_CLRENA33_M 0x00000002 +#define CPU_SCS_NVIC_ICER1_CLRENA33_S 1 // Field: [0] CLRENA32 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER1_CLRENA32 0x00000001 -#define CPU_SCS_NVIC_ICER1_CLRENA32_BITN 0 -#define CPU_SCS_NVIC_ICER1_CLRENA32_M 0x00000001 -#define CPU_SCS_NVIC_ICER1_CLRENA32_S 0 +#define CPU_SCS_NVIC_ICER1_CLRENA32 0x00000001 +#define CPU_SCS_NVIC_ICER1_CLRENA32_BITN 0 +#define CPU_SCS_NVIC_ICER1_CLRENA32_M 0x00000001 +#define CPU_SCS_NVIC_ICER1_CLRENA32_S 0 //***************************************************************************** // @@ -1102,320 +1102,320 @@ // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND31 0x80000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND31_BITN 31 -#define CPU_SCS_NVIC_ISPR0_SETPEND31_M 0x80000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND31_S 31 +#define CPU_SCS_NVIC_ISPR0_SETPEND31 0x80000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_BITN 31 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_M 0x80000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_S 31 // Field: [30] SETPEND30 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND30 0x40000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND30_BITN 30 -#define CPU_SCS_NVIC_ISPR0_SETPEND30_M 0x40000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND30_S 30 +#define CPU_SCS_NVIC_ISPR0_SETPEND30 0x40000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_BITN 30 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_M 0x40000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_S 30 // Field: [29] SETPEND29 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND29 0x20000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND29_BITN 29 -#define CPU_SCS_NVIC_ISPR0_SETPEND29_M 0x20000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND29_S 29 +#define CPU_SCS_NVIC_ISPR0_SETPEND29 0x20000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_BITN 29 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_M 0x20000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_S 29 // Field: [28] SETPEND28 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND28 0x10000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND28_BITN 28 -#define CPU_SCS_NVIC_ISPR0_SETPEND28_M 0x10000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND28_S 28 +#define CPU_SCS_NVIC_ISPR0_SETPEND28 0x10000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_BITN 28 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_M 0x10000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_S 28 // Field: [27] SETPEND27 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND27 0x08000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND27_BITN 27 -#define CPU_SCS_NVIC_ISPR0_SETPEND27_M 0x08000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND27_S 27 +#define CPU_SCS_NVIC_ISPR0_SETPEND27 0x08000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_BITN 27 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_M 0x08000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_S 27 // Field: [26] SETPEND26 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND26 0x04000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND26_BITN 26 -#define CPU_SCS_NVIC_ISPR0_SETPEND26_M 0x04000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND26_S 26 +#define CPU_SCS_NVIC_ISPR0_SETPEND26 0x04000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_BITN 26 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_M 0x04000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_S 26 // Field: [25] SETPEND25 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND25 0x02000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND25_BITN 25 -#define CPU_SCS_NVIC_ISPR0_SETPEND25_M 0x02000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND25_S 25 +#define CPU_SCS_NVIC_ISPR0_SETPEND25 0x02000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_BITN 25 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_M 0x02000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_S 25 // Field: [24] SETPEND24 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND24 0x01000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND24_BITN 24 -#define CPU_SCS_NVIC_ISPR0_SETPEND24_M 0x01000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND24_S 24 +#define CPU_SCS_NVIC_ISPR0_SETPEND24 0x01000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_BITN 24 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_M 0x01000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_S 24 // Field: [23] SETPEND23 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND23 0x00800000 -#define CPU_SCS_NVIC_ISPR0_SETPEND23_BITN 23 -#define CPU_SCS_NVIC_ISPR0_SETPEND23_M 0x00800000 -#define CPU_SCS_NVIC_ISPR0_SETPEND23_S 23 +#define CPU_SCS_NVIC_ISPR0_SETPEND23 0x00800000 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_BITN 23 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_M 0x00800000 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_S 23 // Field: [22] SETPEND22 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND22 0x00400000 -#define CPU_SCS_NVIC_ISPR0_SETPEND22_BITN 22 -#define CPU_SCS_NVIC_ISPR0_SETPEND22_M 0x00400000 -#define CPU_SCS_NVIC_ISPR0_SETPEND22_S 22 +#define CPU_SCS_NVIC_ISPR0_SETPEND22 0x00400000 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_BITN 22 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_M 0x00400000 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_S 22 // Field: [21] SETPEND21 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND21 0x00200000 -#define CPU_SCS_NVIC_ISPR0_SETPEND21_BITN 21 -#define CPU_SCS_NVIC_ISPR0_SETPEND21_M 0x00200000 -#define CPU_SCS_NVIC_ISPR0_SETPEND21_S 21 +#define CPU_SCS_NVIC_ISPR0_SETPEND21 0x00200000 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_BITN 21 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_M 0x00200000 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_S 21 // Field: [20] SETPEND20 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND20 0x00100000 -#define CPU_SCS_NVIC_ISPR0_SETPEND20_BITN 20 -#define CPU_SCS_NVIC_ISPR0_SETPEND20_M 0x00100000 -#define CPU_SCS_NVIC_ISPR0_SETPEND20_S 20 +#define CPU_SCS_NVIC_ISPR0_SETPEND20 0x00100000 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_BITN 20 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_M 0x00100000 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_S 20 // Field: [19] SETPEND19 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND19 0x00080000 -#define CPU_SCS_NVIC_ISPR0_SETPEND19_BITN 19 -#define CPU_SCS_NVIC_ISPR0_SETPEND19_M 0x00080000 -#define CPU_SCS_NVIC_ISPR0_SETPEND19_S 19 +#define CPU_SCS_NVIC_ISPR0_SETPEND19 0x00080000 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_BITN 19 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_M 0x00080000 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_S 19 // Field: [18] SETPEND18 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND18 0x00040000 -#define CPU_SCS_NVIC_ISPR0_SETPEND18_BITN 18 -#define CPU_SCS_NVIC_ISPR0_SETPEND18_M 0x00040000 -#define CPU_SCS_NVIC_ISPR0_SETPEND18_S 18 +#define CPU_SCS_NVIC_ISPR0_SETPEND18 0x00040000 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_BITN 18 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_M 0x00040000 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_S 18 // Field: [17] SETPEND17 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND17 0x00020000 -#define CPU_SCS_NVIC_ISPR0_SETPEND17_BITN 17 -#define CPU_SCS_NVIC_ISPR0_SETPEND17_M 0x00020000 -#define CPU_SCS_NVIC_ISPR0_SETPEND17_S 17 +#define CPU_SCS_NVIC_ISPR0_SETPEND17 0x00020000 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_BITN 17 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_M 0x00020000 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_S 17 // Field: [16] SETPEND16 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND16 0x00010000 -#define CPU_SCS_NVIC_ISPR0_SETPEND16_BITN 16 -#define CPU_SCS_NVIC_ISPR0_SETPEND16_M 0x00010000 -#define CPU_SCS_NVIC_ISPR0_SETPEND16_S 16 +#define CPU_SCS_NVIC_ISPR0_SETPEND16 0x00010000 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_BITN 16 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_M 0x00010000 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_S 16 // Field: [15] SETPEND15 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND15 0x00008000 -#define CPU_SCS_NVIC_ISPR0_SETPEND15_BITN 15 -#define CPU_SCS_NVIC_ISPR0_SETPEND15_M 0x00008000 -#define CPU_SCS_NVIC_ISPR0_SETPEND15_S 15 +#define CPU_SCS_NVIC_ISPR0_SETPEND15 0x00008000 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_BITN 15 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_M 0x00008000 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_S 15 // Field: [14] SETPEND14 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND14 0x00004000 -#define CPU_SCS_NVIC_ISPR0_SETPEND14_BITN 14 -#define CPU_SCS_NVIC_ISPR0_SETPEND14_M 0x00004000 -#define CPU_SCS_NVIC_ISPR0_SETPEND14_S 14 +#define CPU_SCS_NVIC_ISPR0_SETPEND14 0x00004000 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_BITN 14 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_M 0x00004000 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_S 14 // Field: [13] SETPEND13 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND13 0x00002000 -#define CPU_SCS_NVIC_ISPR0_SETPEND13_BITN 13 -#define CPU_SCS_NVIC_ISPR0_SETPEND13_M 0x00002000 -#define CPU_SCS_NVIC_ISPR0_SETPEND13_S 13 +#define CPU_SCS_NVIC_ISPR0_SETPEND13 0x00002000 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_BITN 13 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_M 0x00002000 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_S 13 // Field: [12] SETPEND12 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND12 0x00001000 -#define CPU_SCS_NVIC_ISPR0_SETPEND12_BITN 12 -#define CPU_SCS_NVIC_ISPR0_SETPEND12_M 0x00001000 -#define CPU_SCS_NVIC_ISPR0_SETPEND12_S 12 +#define CPU_SCS_NVIC_ISPR0_SETPEND12 0x00001000 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_BITN 12 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_M 0x00001000 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_S 12 // Field: [11] SETPEND11 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND11 0x00000800 -#define CPU_SCS_NVIC_ISPR0_SETPEND11_BITN 11 -#define CPU_SCS_NVIC_ISPR0_SETPEND11_M 0x00000800 -#define CPU_SCS_NVIC_ISPR0_SETPEND11_S 11 +#define CPU_SCS_NVIC_ISPR0_SETPEND11 0x00000800 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_BITN 11 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_M 0x00000800 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_S 11 // Field: [10] SETPEND10 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND10 0x00000400 -#define CPU_SCS_NVIC_ISPR0_SETPEND10_BITN 10 -#define CPU_SCS_NVIC_ISPR0_SETPEND10_M 0x00000400 -#define CPU_SCS_NVIC_ISPR0_SETPEND10_S 10 +#define CPU_SCS_NVIC_ISPR0_SETPEND10 0x00000400 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_BITN 10 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_M 0x00000400 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_S 10 // Field: [9] SETPEND9 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND9 0x00000200 -#define CPU_SCS_NVIC_ISPR0_SETPEND9_BITN 9 -#define CPU_SCS_NVIC_ISPR0_SETPEND9_M 0x00000200 -#define CPU_SCS_NVIC_ISPR0_SETPEND9_S 9 +#define CPU_SCS_NVIC_ISPR0_SETPEND9 0x00000200 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_BITN 9 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_M 0x00000200 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_S 9 // Field: [8] SETPEND8 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND8 0x00000100 -#define CPU_SCS_NVIC_ISPR0_SETPEND8_BITN 8 -#define CPU_SCS_NVIC_ISPR0_SETPEND8_M 0x00000100 -#define CPU_SCS_NVIC_ISPR0_SETPEND8_S 8 +#define CPU_SCS_NVIC_ISPR0_SETPEND8 0x00000100 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_BITN 8 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_M 0x00000100 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_S 8 // Field: [7] SETPEND7 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND7 0x00000080 -#define CPU_SCS_NVIC_ISPR0_SETPEND7_BITN 7 -#define CPU_SCS_NVIC_ISPR0_SETPEND7_M 0x00000080 -#define CPU_SCS_NVIC_ISPR0_SETPEND7_S 7 +#define CPU_SCS_NVIC_ISPR0_SETPEND7 0x00000080 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_BITN 7 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_M 0x00000080 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_S 7 // Field: [6] SETPEND6 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND6 0x00000040 -#define CPU_SCS_NVIC_ISPR0_SETPEND6_BITN 6 -#define CPU_SCS_NVIC_ISPR0_SETPEND6_M 0x00000040 -#define CPU_SCS_NVIC_ISPR0_SETPEND6_S 6 +#define CPU_SCS_NVIC_ISPR0_SETPEND6 0x00000040 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_BITN 6 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_M 0x00000040 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_S 6 // Field: [5] SETPEND5 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND5 0x00000020 -#define CPU_SCS_NVIC_ISPR0_SETPEND5_BITN 5 -#define CPU_SCS_NVIC_ISPR0_SETPEND5_M 0x00000020 -#define CPU_SCS_NVIC_ISPR0_SETPEND5_S 5 +#define CPU_SCS_NVIC_ISPR0_SETPEND5 0x00000020 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_BITN 5 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_M 0x00000020 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_S 5 // Field: [4] SETPEND4 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND4 0x00000010 -#define CPU_SCS_NVIC_ISPR0_SETPEND4_BITN 4 -#define CPU_SCS_NVIC_ISPR0_SETPEND4_M 0x00000010 -#define CPU_SCS_NVIC_ISPR0_SETPEND4_S 4 +#define CPU_SCS_NVIC_ISPR0_SETPEND4 0x00000010 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_BITN 4 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_M 0x00000010 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_S 4 // Field: [3] SETPEND3 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND3 0x00000008 -#define CPU_SCS_NVIC_ISPR0_SETPEND3_BITN 3 -#define CPU_SCS_NVIC_ISPR0_SETPEND3_M 0x00000008 -#define CPU_SCS_NVIC_ISPR0_SETPEND3_S 3 +#define CPU_SCS_NVIC_ISPR0_SETPEND3 0x00000008 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_BITN 3 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_M 0x00000008 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_S 3 // Field: [2] SETPEND2 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND2 0x00000004 -#define CPU_SCS_NVIC_ISPR0_SETPEND2_BITN 2 -#define CPU_SCS_NVIC_ISPR0_SETPEND2_M 0x00000004 -#define CPU_SCS_NVIC_ISPR0_SETPEND2_S 2 +#define CPU_SCS_NVIC_ISPR0_SETPEND2 0x00000004 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_BITN 2 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_M 0x00000004 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_S 2 // Field: [1] SETPEND1 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND1 0x00000002 -#define CPU_SCS_NVIC_ISPR0_SETPEND1_BITN 1 -#define CPU_SCS_NVIC_ISPR0_SETPEND1_M 0x00000002 -#define CPU_SCS_NVIC_ISPR0_SETPEND1_S 1 +#define CPU_SCS_NVIC_ISPR0_SETPEND1 0x00000002 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_BITN 1 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_M 0x00000002 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_S 1 // Field: [0] SETPEND0 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND0 0x00000001 -#define CPU_SCS_NVIC_ISPR0_SETPEND0_BITN 0 -#define CPU_SCS_NVIC_ISPR0_SETPEND0_M 0x00000001 -#define CPU_SCS_NVIC_ISPR0_SETPEND0_S 0 +#define CPU_SCS_NVIC_ISPR0_SETPEND0 0x00000001 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_BITN 0 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_M 0x00000001 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_S 0 //***************************************************************************** // @@ -1427,20 +1427,20 @@ // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR1_SETPEND33 0x00000002 -#define CPU_SCS_NVIC_ISPR1_SETPEND33_BITN 1 -#define CPU_SCS_NVIC_ISPR1_SETPEND33_M 0x00000002 -#define CPU_SCS_NVIC_ISPR1_SETPEND33_S 1 +#define CPU_SCS_NVIC_ISPR1_SETPEND33 0x00000002 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_BITN 1 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_M 0x00000002 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_S 1 // Field: [0] SETPEND32 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR1_SETPEND32 0x00000001 -#define CPU_SCS_NVIC_ISPR1_SETPEND32_BITN 0 -#define CPU_SCS_NVIC_ISPR1_SETPEND32_M 0x00000001 -#define CPU_SCS_NVIC_ISPR1_SETPEND32_S 0 +#define CPU_SCS_NVIC_ISPR1_SETPEND32 0x00000001 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_BITN 0 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_M 0x00000001 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_S 0 //***************************************************************************** // @@ -1452,320 +1452,320 @@ // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND31 0x80000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND31_BITN 31 -#define CPU_SCS_NVIC_ICPR0_CLRPEND31_M 0x80000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND31_S 31 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31 0x80000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_BITN 31 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_M 0x80000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_S 31 // Field: [30] CLRPEND30 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND30 0x40000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND30_BITN 30 -#define CPU_SCS_NVIC_ICPR0_CLRPEND30_M 0x40000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND30_S 30 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30 0x40000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_BITN 30 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_M 0x40000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_S 30 // Field: [29] CLRPEND29 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND29 0x20000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND29_BITN 29 -#define CPU_SCS_NVIC_ICPR0_CLRPEND29_M 0x20000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND29_S 29 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29 0x20000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_BITN 29 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_M 0x20000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_S 29 // Field: [28] CLRPEND28 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND28 0x10000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND28_BITN 28 -#define CPU_SCS_NVIC_ICPR0_CLRPEND28_M 0x10000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND28_S 28 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28 0x10000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_BITN 28 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_M 0x10000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_S 28 // Field: [27] CLRPEND27 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND27 0x08000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND27_BITN 27 -#define CPU_SCS_NVIC_ICPR0_CLRPEND27_M 0x08000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND27_S 27 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27 0x08000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_BITN 27 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_M 0x08000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_S 27 // Field: [26] CLRPEND26 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND26 0x04000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND26_BITN 26 -#define CPU_SCS_NVIC_ICPR0_CLRPEND26_M 0x04000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND26_S 26 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26 0x04000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_BITN 26 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_M 0x04000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_S 26 // Field: [25] CLRPEND25 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND25 0x02000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND25_BITN 25 -#define CPU_SCS_NVIC_ICPR0_CLRPEND25_M 0x02000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND25_S 25 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25 0x02000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_BITN 25 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_M 0x02000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_S 25 // Field: [24] CLRPEND24 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND24 0x01000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND24_BITN 24 -#define CPU_SCS_NVIC_ICPR0_CLRPEND24_M 0x01000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND24_S 24 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24 0x01000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_BITN 24 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_M 0x01000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_S 24 // Field: [23] CLRPEND23 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND23 0x00800000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND23_BITN 23 -#define CPU_SCS_NVIC_ICPR0_CLRPEND23_M 0x00800000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND23_S 23 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23 0x00800000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_BITN 23 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_M 0x00800000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_S 23 // Field: [22] CLRPEND22 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND22 0x00400000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND22_BITN 22 -#define CPU_SCS_NVIC_ICPR0_CLRPEND22_M 0x00400000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND22_S 22 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22 0x00400000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_BITN 22 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_M 0x00400000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_S 22 // Field: [21] CLRPEND21 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND21 0x00200000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND21_BITN 21 -#define CPU_SCS_NVIC_ICPR0_CLRPEND21_M 0x00200000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND21_S 21 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21 0x00200000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_BITN 21 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_M 0x00200000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_S 21 // Field: [20] CLRPEND20 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND20 0x00100000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND20_BITN 20 -#define CPU_SCS_NVIC_ICPR0_CLRPEND20_M 0x00100000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND20_S 20 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20 0x00100000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_BITN 20 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_M 0x00100000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_S 20 // Field: [19] CLRPEND19 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND19 0x00080000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND19_BITN 19 -#define CPU_SCS_NVIC_ICPR0_CLRPEND19_M 0x00080000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND19_S 19 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19 0x00080000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_BITN 19 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_M 0x00080000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_S 19 // Field: [18] CLRPEND18 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND18 0x00040000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND18_BITN 18 -#define CPU_SCS_NVIC_ICPR0_CLRPEND18_M 0x00040000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND18_S 18 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18 0x00040000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_BITN 18 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_M 0x00040000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_S 18 // Field: [17] CLRPEND17 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND17 0x00020000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND17_BITN 17 -#define CPU_SCS_NVIC_ICPR0_CLRPEND17_M 0x00020000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND17_S 17 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17 0x00020000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_BITN 17 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_M 0x00020000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_S 17 // Field: [16] CLRPEND16 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND16 0x00010000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND16_BITN 16 -#define CPU_SCS_NVIC_ICPR0_CLRPEND16_M 0x00010000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND16_S 16 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16 0x00010000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_BITN 16 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_M 0x00010000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_S 16 // Field: [15] CLRPEND15 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND15 0x00008000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND15_BITN 15 -#define CPU_SCS_NVIC_ICPR0_CLRPEND15_M 0x00008000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND15_S 15 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15 0x00008000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_BITN 15 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_M 0x00008000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_S 15 // Field: [14] CLRPEND14 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND14 0x00004000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND14_BITN 14 -#define CPU_SCS_NVIC_ICPR0_CLRPEND14_M 0x00004000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND14_S 14 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14 0x00004000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_BITN 14 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_M 0x00004000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_S 14 // Field: [13] CLRPEND13 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND13 0x00002000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND13_BITN 13 -#define CPU_SCS_NVIC_ICPR0_CLRPEND13_M 0x00002000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND13_S 13 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13 0x00002000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_BITN 13 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_M 0x00002000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_S 13 // Field: [12] CLRPEND12 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND12 0x00001000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND12_BITN 12 -#define CPU_SCS_NVIC_ICPR0_CLRPEND12_M 0x00001000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND12_S 12 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12 0x00001000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_BITN 12 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_M 0x00001000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_S 12 // Field: [11] CLRPEND11 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND11 0x00000800 -#define CPU_SCS_NVIC_ICPR0_CLRPEND11_BITN 11 -#define CPU_SCS_NVIC_ICPR0_CLRPEND11_M 0x00000800 -#define CPU_SCS_NVIC_ICPR0_CLRPEND11_S 11 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11 0x00000800 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_BITN 11 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_M 0x00000800 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_S 11 // Field: [10] CLRPEND10 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND10 0x00000400 -#define CPU_SCS_NVIC_ICPR0_CLRPEND10_BITN 10 -#define CPU_SCS_NVIC_ICPR0_CLRPEND10_M 0x00000400 -#define CPU_SCS_NVIC_ICPR0_CLRPEND10_S 10 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10 0x00000400 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_BITN 10 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_M 0x00000400 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_S 10 // Field: [9] CLRPEND9 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND9 0x00000200 -#define CPU_SCS_NVIC_ICPR0_CLRPEND9_BITN 9 -#define CPU_SCS_NVIC_ICPR0_CLRPEND9_M 0x00000200 -#define CPU_SCS_NVIC_ICPR0_CLRPEND9_S 9 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9 0x00000200 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_BITN 9 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_M 0x00000200 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_S 9 // Field: [8] CLRPEND8 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND8 0x00000100 -#define CPU_SCS_NVIC_ICPR0_CLRPEND8_BITN 8 -#define CPU_SCS_NVIC_ICPR0_CLRPEND8_M 0x00000100 -#define CPU_SCS_NVIC_ICPR0_CLRPEND8_S 8 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8 0x00000100 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_BITN 8 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_M 0x00000100 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_S 8 // Field: [7] CLRPEND7 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND7 0x00000080 -#define CPU_SCS_NVIC_ICPR0_CLRPEND7_BITN 7 -#define CPU_SCS_NVIC_ICPR0_CLRPEND7_M 0x00000080 -#define CPU_SCS_NVIC_ICPR0_CLRPEND7_S 7 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7 0x00000080 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_BITN 7 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_M 0x00000080 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_S 7 // Field: [6] CLRPEND6 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND6 0x00000040 -#define CPU_SCS_NVIC_ICPR0_CLRPEND6_BITN 6 -#define CPU_SCS_NVIC_ICPR0_CLRPEND6_M 0x00000040 -#define CPU_SCS_NVIC_ICPR0_CLRPEND6_S 6 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6 0x00000040 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_BITN 6 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_M 0x00000040 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_S 6 // Field: [5] CLRPEND5 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND5 0x00000020 -#define CPU_SCS_NVIC_ICPR0_CLRPEND5_BITN 5 -#define CPU_SCS_NVIC_ICPR0_CLRPEND5_M 0x00000020 -#define CPU_SCS_NVIC_ICPR0_CLRPEND5_S 5 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5 0x00000020 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_BITN 5 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_M 0x00000020 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_S 5 // Field: [4] CLRPEND4 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND4 0x00000010 -#define CPU_SCS_NVIC_ICPR0_CLRPEND4_BITN 4 -#define CPU_SCS_NVIC_ICPR0_CLRPEND4_M 0x00000010 -#define CPU_SCS_NVIC_ICPR0_CLRPEND4_S 4 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4 0x00000010 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_BITN 4 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_M 0x00000010 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_S 4 // Field: [3] CLRPEND3 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND3 0x00000008 -#define CPU_SCS_NVIC_ICPR0_CLRPEND3_BITN 3 -#define CPU_SCS_NVIC_ICPR0_CLRPEND3_M 0x00000008 -#define CPU_SCS_NVIC_ICPR0_CLRPEND3_S 3 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3 0x00000008 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_BITN 3 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_M 0x00000008 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_S 3 // Field: [2] CLRPEND2 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND2 0x00000004 -#define CPU_SCS_NVIC_ICPR0_CLRPEND2_BITN 2 -#define CPU_SCS_NVIC_ICPR0_CLRPEND2_M 0x00000004 -#define CPU_SCS_NVIC_ICPR0_CLRPEND2_S 2 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2 0x00000004 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_BITN 2 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_M 0x00000004 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_S 2 // Field: [1] CLRPEND1 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND1 0x00000002 -#define CPU_SCS_NVIC_ICPR0_CLRPEND1_BITN 1 -#define CPU_SCS_NVIC_ICPR0_CLRPEND1_M 0x00000002 -#define CPU_SCS_NVIC_ICPR0_CLRPEND1_S 1 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1 0x00000002 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_BITN 1 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_M 0x00000002 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_S 1 // Field: [0] CLRPEND0 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND0 0x00000001 -#define CPU_SCS_NVIC_ICPR0_CLRPEND0_BITN 0 -#define CPU_SCS_NVIC_ICPR0_CLRPEND0_M 0x00000001 -#define CPU_SCS_NVIC_ICPR0_CLRPEND0_S 0 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0 0x00000001 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_BITN 0 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_M 0x00000001 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_S 0 //***************************************************************************** // @@ -1777,20 +1777,20 @@ // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR1_CLRPEND33 0x00000002 -#define CPU_SCS_NVIC_ICPR1_CLRPEND33_BITN 1 -#define CPU_SCS_NVIC_ICPR1_CLRPEND33_M 0x00000002 -#define CPU_SCS_NVIC_ICPR1_CLRPEND33_S 1 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33 0x00000002 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_BITN 1 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_M 0x00000002 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_S 1 // Field: [0] CLRPEND32 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR1_CLRPEND32 0x00000001 -#define CPU_SCS_NVIC_ICPR1_CLRPEND32_BITN 0 -#define CPU_SCS_NVIC_ICPR1_CLRPEND32_M 0x00000001 -#define CPU_SCS_NVIC_ICPR1_CLRPEND32_S 0 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32 0x00000001 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_BITN 0 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_M 0x00000001 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_S 0 //***************************************************************************** // @@ -1802,320 +1802,320 @@ // Reading 0 from this bit implies that interrupt line 31 is not active. // Reading 1 from this bit implies that the interrupt line 31 is active (See // EVENT:CPUIRQSEL31.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE31 0x80000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE31_BITN 31 -#define CPU_SCS_NVIC_IABR0_ACTIVE31_M 0x80000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE31_S 31 +#define CPU_SCS_NVIC_IABR0_ACTIVE31 0x80000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_BITN 31 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_M 0x80000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_S 31 // Field: [30] ACTIVE30 // // Reading 0 from this bit implies that interrupt line 30 is not active. // Reading 1 from this bit implies that the interrupt line 30 is active (See // EVENT:CPUIRQSEL30.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE30 0x40000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE30_BITN 30 -#define CPU_SCS_NVIC_IABR0_ACTIVE30_M 0x40000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE30_S 30 +#define CPU_SCS_NVIC_IABR0_ACTIVE30 0x40000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_BITN 30 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_M 0x40000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_S 30 // Field: [29] ACTIVE29 // // Reading 0 from this bit implies that interrupt line 29 is not active. // Reading 1 from this bit implies that the interrupt line 29 is active (See // EVENT:CPUIRQSEL29.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE29 0x20000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE29_BITN 29 -#define CPU_SCS_NVIC_IABR0_ACTIVE29_M 0x20000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE29_S 29 +#define CPU_SCS_NVIC_IABR0_ACTIVE29 0x20000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_BITN 29 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_M 0x20000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_S 29 // Field: [28] ACTIVE28 // // Reading 0 from this bit implies that interrupt line 28 is not active. // Reading 1 from this bit implies that the interrupt line 28 is active (See // EVENT:CPUIRQSEL28.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE28 0x10000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE28_BITN 28 -#define CPU_SCS_NVIC_IABR0_ACTIVE28_M 0x10000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE28_S 28 +#define CPU_SCS_NVIC_IABR0_ACTIVE28 0x10000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_BITN 28 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_M 0x10000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_S 28 // Field: [27] ACTIVE27 // // Reading 0 from this bit implies that interrupt line 27 is not active. // Reading 1 from this bit implies that the interrupt line 27 is active (See // EVENT:CPUIRQSEL27.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE27 0x08000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE27_BITN 27 -#define CPU_SCS_NVIC_IABR0_ACTIVE27_M 0x08000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE27_S 27 +#define CPU_SCS_NVIC_IABR0_ACTIVE27 0x08000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_BITN 27 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_M 0x08000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_S 27 // Field: [26] ACTIVE26 // // Reading 0 from this bit implies that interrupt line 26 is not active. // Reading 1 from this bit implies that the interrupt line 26 is active (See // EVENT:CPUIRQSEL26.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE26 0x04000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE26_BITN 26 -#define CPU_SCS_NVIC_IABR0_ACTIVE26_M 0x04000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE26_S 26 +#define CPU_SCS_NVIC_IABR0_ACTIVE26 0x04000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_BITN 26 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_M 0x04000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_S 26 // Field: [25] ACTIVE25 // // Reading 0 from this bit implies that interrupt line 25 is not active. // Reading 1 from this bit implies that the interrupt line 25 is active (See // EVENT:CPUIRQSEL25.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE25 0x02000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE25_BITN 25 -#define CPU_SCS_NVIC_IABR0_ACTIVE25_M 0x02000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE25_S 25 +#define CPU_SCS_NVIC_IABR0_ACTIVE25 0x02000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_BITN 25 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_M 0x02000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_S 25 // Field: [24] ACTIVE24 // // Reading 0 from this bit implies that interrupt line 24 is not active. // Reading 1 from this bit implies that the interrupt line 24 is active (See // EVENT:CPUIRQSEL24.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE24 0x01000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE24_BITN 24 -#define CPU_SCS_NVIC_IABR0_ACTIVE24_M 0x01000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE24_S 24 +#define CPU_SCS_NVIC_IABR0_ACTIVE24 0x01000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_BITN 24 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_M 0x01000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_S 24 // Field: [23] ACTIVE23 // // Reading 0 from this bit implies that interrupt line 23 is not active. // Reading 1 from this bit implies that the interrupt line 23 is active (See // EVENT:CPUIRQSEL23.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE23 0x00800000 -#define CPU_SCS_NVIC_IABR0_ACTIVE23_BITN 23 -#define CPU_SCS_NVIC_IABR0_ACTIVE23_M 0x00800000 -#define CPU_SCS_NVIC_IABR0_ACTIVE23_S 23 +#define CPU_SCS_NVIC_IABR0_ACTIVE23 0x00800000 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_BITN 23 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_M 0x00800000 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_S 23 // Field: [22] ACTIVE22 // // Reading 0 from this bit implies that interrupt line 22 is not active. // Reading 1 from this bit implies that the interrupt line 22 is active (See // EVENT:CPUIRQSEL22.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE22 0x00400000 -#define CPU_SCS_NVIC_IABR0_ACTIVE22_BITN 22 -#define CPU_SCS_NVIC_IABR0_ACTIVE22_M 0x00400000 -#define CPU_SCS_NVIC_IABR0_ACTIVE22_S 22 +#define CPU_SCS_NVIC_IABR0_ACTIVE22 0x00400000 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_BITN 22 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_M 0x00400000 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_S 22 // Field: [21] ACTIVE21 // // Reading 0 from this bit implies that interrupt line 21 is not active. // Reading 1 from this bit implies that the interrupt line 21 is active (See // EVENT:CPUIRQSEL21.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE21 0x00200000 -#define CPU_SCS_NVIC_IABR0_ACTIVE21_BITN 21 -#define CPU_SCS_NVIC_IABR0_ACTIVE21_M 0x00200000 -#define CPU_SCS_NVIC_IABR0_ACTIVE21_S 21 +#define CPU_SCS_NVIC_IABR0_ACTIVE21 0x00200000 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_BITN 21 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_M 0x00200000 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_S 21 // Field: [20] ACTIVE20 // // Reading 0 from this bit implies that interrupt line 20 is not active. // Reading 1 from this bit implies that the interrupt line 20 is active (See // EVENT:CPUIRQSEL20.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE20 0x00100000 -#define CPU_SCS_NVIC_IABR0_ACTIVE20_BITN 20 -#define CPU_SCS_NVIC_IABR0_ACTIVE20_M 0x00100000 -#define CPU_SCS_NVIC_IABR0_ACTIVE20_S 20 +#define CPU_SCS_NVIC_IABR0_ACTIVE20 0x00100000 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_BITN 20 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_M 0x00100000 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_S 20 // Field: [19] ACTIVE19 // // Reading 0 from this bit implies that interrupt line 19 is not active. // Reading 1 from this bit implies that the interrupt line 19 is active (See // EVENT:CPUIRQSEL19.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE19 0x00080000 -#define CPU_SCS_NVIC_IABR0_ACTIVE19_BITN 19 -#define CPU_SCS_NVIC_IABR0_ACTIVE19_M 0x00080000 -#define CPU_SCS_NVIC_IABR0_ACTIVE19_S 19 +#define CPU_SCS_NVIC_IABR0_ACTIVE19 0x00080000 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_BITN 19 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_M 0x00080000 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_S 19 // Field: [18] ACTIVE18 // // Reading 0 from this bit implies that interrupt line 18 is not active. // Reading 1 from this bit implies that the interrupt line 18 is active (See // EVENT:CPUIRQSEL18.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE18 0x00040000 -#define CPU_SCS_NVIC_IABR0_ACTIVE18_BITN 18 -#define CPU_SCS_NVIC_IABR0_ACTIVE18_M 0x00040000 -#define CPU_SCS_NVIC_IABR0_ACTIVE18_S 18 +#define CPU_SCS_NVIC_IABR0_ACTIVE18 0x00040000 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_BITN 18 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_M 0x00040000 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_S 18 // Field: [17] ACTIVE17 // // Reading 0 from this bit implies that interrupt line 17 is not active. // Reading 1 from this bit implies that the interrupt line 17 is active (See // EVENT:CPUIRQSEL17.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE17 0x00020000 -#define CPU_SCS_NVIC_IABR0_ACTIVE17_BITN 17 -#define CPU_SCS_NVIC_IABR0_ACTIVE17_M 0x00020000 -#define CPU_SCS_NVIC_IABR0_ACTIVE17_S 17 +#define CPU_SCS_NVIC_IABR0_ACTIVE17 0x00020000 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_BITN 17 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_M 0x00020000 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_S 17 // Field: [16] ACTIVE16 // // Reading 0 from this bit implies that interrupt line 16 is not active. // Reading 1 from this bit implies that the interrupt line 16 is active (See // EVENT:CPUIRQSEL16.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE16 0x00010000 -#define CPU_SCS_NVIC_IABR0_ACTIVE16_BITN 16 -#define CPU_SCS_NVIC_IABR0_ACTIVE16_M 0x00010000 -#define CPU_SCS_NVIC_IABR0_ACTIVE16_S 16 +#define CPU_SCS_NVIC_IABR0_ACTIVE16 0x00010000 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_BITN 16 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_M 0x00010000 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_S 16 // Field: [15] ACTIVE15 // // Reading 0 from this bit implies that interrupt line 15 is not active. // Reading 1 from this bit implies that the interrupt line 15 is active (See // EVENT:CPUIRQSEL15.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE15 0x00008000 -#define CPU_SCS_NVIC_IABR0_ACTIVE15_BITN 15 -#define CPU_SCS_NVIC_IABR0_ACTIVE15_M 0x00008000 -#define CPU_SCS_NVIC_IABR0_ACTIVE15_S 15 +#define CPU_SCS_NVIC_IABR0_ACTIVE15 0x00008000 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_BITN 15 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_M 0x00008000 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_S 15 // Field: [14] ACTIVE14 // // Reading 0 from this bit implies that interrupt line 14 is not active. // Reading 1 from this bit implies that the interrupt line 14 is active (See // EVENT:CPUIRQSEL14.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE14 0x00004000 -#define CPU_SCS_NVIC_IABR0_ACTIVE14_BITN 14 -#define CPU_SCS_NVIC_IABR0_ACTIVE14_M 0x00004000 -#define CPU_SCS_NVIC_IABR0_ACTIVE14_S 14 +#define CPU_SCS_NVIC_IABR0_ACTIVE14 0x00004000 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_BITN 14 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_M 0x00004000 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_S 14 // Field: [13] ACTIVE13 // // Reading 0 from this bit implies that interrupt line 13 is not active. // Reading 1 from this bit implies that the interrupt line 13 is active (See // EVENT:CPUIRQSEL13.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE13 0x00002000 -#define CPU_SCS_NVIC_IABR0_ACTIVE13_BITN 13 -#define CPU_SCS_NVIC_IABR0_ACTIVE13_M 0x00002000 -#define CPU_SCS_NVIC_IABR0_ACTIVE13_S 13 +#define CPU_SCS_NVIC_IABR0_ACTIVE13 0x00002000 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_BITN 13 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_M 0x00002000 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_S 13 // Field: [12] ACTIVE12 // // Reading 0 from this bit implies that interrupt line 12 is not active. // Reading 1 from this bit implies that the interrupt line 12 is active (See // EVENT:CPUIRQSEL12.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE12 0x00001000 -#define CPU_SCS_NVIC_IABR0_ACTIVE12_BITN 12 -#define CPU_SCS_NVIC_IABR0_ACTIVE12_M 0x00001000 -#define CPU_SCS_NVIC_IABR0_ACTIVE12_S 12 +#define CPU_SCS_NVIC_IABR0_ACTIVE12 0x00001000 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_BITN 12 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_M 0x00001000 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_S 12 // Field: [11] ACTIVE11 // // Reading 0 from this bit implies that interrupt line 11 is not active. // Reading 1 from this bit implies that the interrupt line 11 is active (See // EVENT:CPUIRQSEL11.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE11 0x00000800 -#define CPU_SCS_NVIC_IABR0_ACTIVE11_BITN 11 -#define CPU_SCS_NVIC_IABR0_ACTIVE11_M 0x00000800 -#define CPU_SCS_NVIC_IABR0_ACTIVE11_S 11 +#define CPU_SCS_NVIC_IABR0_ACTIVE11 0x00000800 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_BITN 11 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_M 0x00000800 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_S 11 // Field: [10] ACTIVE10 // // Reading 0 from this bit implies that interrupt line 10 is not active. // Reading 1 from this bit implies that the interrupt line 10 is active (See // EVENT:CPUIRQSEL10.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE10 0x00000400 -#define CPU_SCS_NVIC_IABR0_ACTIVE10_BITN 10 -#define CPU_SCS_NVIC_IABR0_ACTIVE10_M 0x00000400 -#define CPU_SCS_NVIC_IABR0_ACTIVE10_S 10 +#define CPU_SCS_NVIC_IABR0_ACTIVE10 0x00000400 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_BITN 10 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_M 0x00000400 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_S 10 // Field: [9] ACTIVE9 // // Reading 0 from this bit implies that interrupt line 9 is not active. Reading // 1 from this bit implies that the interrupt line 9 is active (See // EVENT:CPUIRQSEL9.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE9 0x00000200 -#define CPU_SCS_NVIC_IABR0_ACTIVE9_BITN 9 -#define CPU_SCS_NVIC_IABR0_ACTIVE9_M 0x00000200 -#define CPU_SCS_NVIC_IABR0_ACTIVE9_S 9 +#define CPU_SCS_NVIC_IABR0_ACTIVE9 0x00000200 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_BITN 9 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_M 0x00000200 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_S 9 // Field: [8] ACTIVE8 // // Reading 0 from this bit implies that interrupt line 8 is not active. Reading // 1 from this bit implies that the interrupt line 8 is active (See // EVENT:CPUIRQSEL8.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE8 0x00000100 -#define CPU_SCS_NVIC_IABR0_ACTIVE8_BITN 8 -#define CPU_SCS_NVIC_IABR0_ACTIVE8_M 0x00000100 -#define CPU_SCS_NVIC_IABR0_ACTIVE8_S 8 +#define CPU_SCS_NVIC_IABR0_ACTIVE8 0x00000100 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_BITN 8 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_M 0x00000100 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_S 8 // Field: [7] ACTIVE7 // // Reading 0 from this bit implies that interrupt line 7 is not active. Reading // 1 from this bit implies that the interrupt line 7 is active (See // EVENT:CPUIRQSEL7.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE7 0x00000080 -#define CPU_SCS_NVIC_IABR0_ACTIVE7_BITN 7 -#define CPU_SCS_NVIC_IABR0_ACTIVE7_M 0x00000080 -#define CPU_SCS_NVIC_IABR0_ACTIVE7_S 7 +#define CPU_SCS_NVIC_IABR0_ACTIVE7 0x00000080 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_BITN 7 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_M 0x00000080 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_S 7 // Field: [6] ACTIVE6 // // Reading 0 from this bit implies that interrupt line 6 is not active. Reading // 1 from this bit implies that the interrupt line 6 is active (See // EVENT:CPUIRQSEL6.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE6 0x00000040 -#define CPU_SCS_NVIC_IABR0_ACTIVE6_BITN 6 -#define CPU_SCS_NVIC_IABR0_ACTIVE6_M 0x00000040 -#define CPU_SCS_NVIC_IABR0_ACTIVE6_S 6 +#define CPU_SCS_NVIC_IABR0_ACTIVE6 0x00000040 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_BITN 6 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_M 0x00000040 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_S 6 // Field: [5] ACTIVE5 // // Reading 0 from this bit implies that interrupt line 5 is not active. Reading // 1 from this bit implies that the interrupt line 5 is active (See // EVENT:CPUIRQSEL5.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE5 0x00000020 -#define CPU_SCS_NVIC_IABR0_ACTIVE5_BITN 5 -#define CPU_SCS_NVIC_IABR0_ACTIVE5_M 0x00000020 -#define CPU_SCS_NVIC_IABR0_ACTIVE5_S 5 +#define CPU_SCS_NVIC_IABR0_ACTIVE5 0x00000020 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_BITN 5 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_M 0x00000020 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_S 5 // Field: [4] ACTIVE4 // // Reading 0 from this bit implies that interrupt line 4 is not active. Reading // 1 from this bit implies that the interrupt line 4 is active (See // EVENT:CPUIRQSEL4.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE4 0x00000010 -#define CPU_SCS_NVIC_IABR0_ACTIVE4_BITN 4 -#define CPU_SCS_NVIC_IABR0_ACTIVE4_M 0x00000010 -#define CPU_SCS_NVIC_IABR0_ACTIVE4_S 4 +#define CPU_SCS_NVIC_IABR0_ACTIVE4 0x00000010 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_BITN 4 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_M 0x00000010 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_S 4 // Field: [3] ACTIVE3 // // Reading 0 from this bit implies that interrupt line 3 is not active. Reading // 1 from this bit implies that the interrupt line 3 is active (See // EVENT:CPUIRQSEL3.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE3 0x00000008 -#define CPU_SCS_NVIC_IABR0_ACTIVE3_BITN 3 -#define CPU_SCS_NVIC_IABR0_ACTIVE3_M 0x00000008 -#define CPU_SCS_NVIC_IABR0_ACTIVE3_S 3 +#define CPU_SCS_NVIC_IABR0_ACTIVE3 0x00000008 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_BITN 3 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_M 0x00000008 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_S 3 // Field: [2] ACTIVE2 // // Reading 0 from this bit implies that interrupt line 2 is not active. Reading // 1 from this bit implies that the interrupt line 2 is active (See // EVENT:CPUIRQSEL2.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE2 0x00000004 -#define CPU_SCS_NVIC_IABR0_ACTIVE2_BITN 2 -#define CPU_SCS_NVIC_IABR0_ACTIVE2_M 0x00000004 -#define CPU_SCS_NVIC_IABR0_ACTIVE2_S 2 +#define CPU_SCS_NVIC_IABR0_ACTIVE2 0x00000004 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_BITN 2 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_M 0x00000004 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_S 2 // Field: [1] ACTIVE1 // // Reading 0 from this bit implies that interrupt line 1 is not active. Reading // 1 from this bit implies that the interrupt line 1 is active (See // EVENT:CPUIRQSEL1.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE1 0x00000002 -#define CPU_SCS_NVIC_IABR0_ACTIVE1_BITN 1 -#define CPU_SCS_NVIC_IABR0_ACTIVE1_M 0x00000002 -#define CPU_SCS_NVIC_IABR0_ACTIVE1_S 1 +#define CPU_SCS_NVIC_IABR0_ACTIVE1 0x00000002 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_BITN 1 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_M 0x00000002 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_S 1 // Field: [0] ACTIVE0 // // Reading 0 from this bit implies that interrupt line 0 is not active. Reading // 1 from this bit implies that the interrupt line 0 is active (See // EVENT:CPUIRQSEL0.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE0 0x00000001 -#define CPU_SCS_NVIC_IABR0_ACTIVE0_BITN 0 -#define CPU_SCS_NVIC_IABR0_ACTIVE0_M 0x00000001 -#define CPU_SCS_NVIC_IABR0_ACTIVE0_S 0 +#define CPU_SCS_NVIC_IABR0_ACTIVE0 0x00000001 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_BITN 0 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_M 0x00000001 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_S 0 //***************************************************************************** // @@ -2127,20 +2127,20 @@ // Reading 0 from this bit implies that interrupt line 33 is not active. // Reading 1 from this bit implies that the interrupt line 33 is active (See // EVENT:CPUIRQSEL33.EV for details). -#define CPU_SCS_NVIC_IABR1_ACTIVE33 0x00000002 -#define CPU_SCS_NVIC_IABR1_ACTIVE33_BITN 1 -#define CPU_SCS_NVIC_IABR1_ACTIVE33_M 0x00000002 -#define CPU_SCS_NVIC_IABR1_ACTIVE33_S 1 +#define CPU_SCS_NVIC_IABR1_ACTIVE33 0x00000002 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_BITN 1 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_M 0x00000002 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_S 1 // Field: [0] ACTIVE32 // // Reading 0 from this bit implies that interrupt line 32 is not active. // Reading 1 from this bit implies that the interrupt line 32 is active (See // EVENT:CPUIRQSEL32.EV for details). -#define CPU_SCS_NVIC_IABR1_ACTIVE32 0x00000001 -#define CPU_SCS_NVIC_IABR1_ACTIVE32_BITN 0 -#define CPU_SCS_NVIC_IABR1_ACTIVE32_M 0x00000001 -#define CPU_SCS_NVIC_IABR1_ACTIVE32_S 0 +#define CPU_SCS_NVIC_IABR1_ACTIVE32 0x00000001 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_BITN 0 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_M 0x00000001 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_S 0 //***************************************************************************** // @@ -2150,30 +2150,30 @@ // Field: [31:24] PRI_3 // // Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). -#define CPU_SCS_NVIC_IPR0_PRI_3_W 8 -#define CPU_SCS_NVIC_IPR0_PRI_3_M 0xFF000000 -#define CPU_SCS_NVIC_IPR0_PRI_3_S 24 +#define CPU_SCS_NVIC_IPR0_PRI_3_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_3_M 0xFF000000 +#define CPU_SCS_NVIC_IPR0_PRI_3_S 24 // Field: [23:16] PRI_2 // // Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). -#define CPU_SCS_NVIC_IPR0_PRI_2_W 8 -#define CPU_SCS_NVIC_IPR0_PRI_2_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR0_PRI_2_S 16 +#define CPU_SCS_NVIC_IPR0_PRI_2_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_2_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR0_PRI_2_S 16 // Field: [15:8] PRI_1 // // Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). -#define CPU_SCS_NVIC_IPR0_PRI_1_W 8 -#define CPU_SCS_NVIC_IPR0_PRI_1_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR0_PRI_1_S 8 +#define CPU_SCS_NVIC_IPR0_PRI_1_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_1_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR0_PRI_1_S 8 // Field: [7:0] PRI_0 // // Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). -#define CPU_SCS_NVIC_IPR0_PRI_0_W 8 -#define CPU_SCS_NVIC_IPR0_PRI_0_M 0x000000FF -#define CPU_SCS_NVIC_IPR0_PRI_0_S 0 +#define CPU_SCS_NVIC_IPR0_PRI_0_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_0_M 0x000000FF +#define CPU_SCS_NVIC_IPR0_PRI_0_S 0 //***************************************************************************** // @@ -2183,30 +2183,30 @@ // Field: [31:24] PRI_7 // // Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). -#define CPU_SCS_NVIC_IPR1_PRI_7_W 8 -#define CPU_SCS_NVIC_IPR1_PRI_7_M 0xFF000000 -#define CPU_SCS_NVIC_IPR1_PRI_7_S 24 +#define CPU_SCS_NVIC_IPR1_PRI_7_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_7_M 0xFF000000 +#define CPU_SCS_NVIC_IPR1_PRI_7_S 24 // Field: [23:16] PRI_6 // // Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). -#define CPU_SCS_NVIC_IPR1_PRI_6_W 8 -#define CPU_SCS_NVIC_IPR1_PRI_6_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR1_PRI_6_S 16 +#define CPU_SCS_NVIC_IPR1_PRI_6_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_6_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR1_PRI_6_S 16 // Field: [15:8] PRI_5 // // Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). -#define CPU_SCS_NVIC_IPR1_PRI_5_W 8 -#define CPU_SCS_NVIC_IPR1_PRI_5_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR1_PRI_5_S 8 +#define CPU_SCS_NVIC_IPR1_PRI_5_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_5_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR1_PRI_5_S 8 // Field: [7:0] PRI_4 // // Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). -#define CPU_SCS_NVIC_IPR1_PRI_4_W 8 -#define CPU_SCS_NVIC_IPR1_PRI_4_M 0x000000FF -#define CPU_SCS_NVIC_IPR1_PRI_4_S 0 +#define CPU_SCS_NVIC_IPR1_PRI_4_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_4_M 0x000000FF +#define CPU_SCS_NVIC_IPR1_PRI_4_S 0 //***************************************************************************** // @@ -2216,30 +2216,30 @@ // Field: [31:24] PRI_11 // // Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). -#define CPU_SCS_NVIC_IPR2_PRI_11_W 8 -#define CPU_SCS_NVIC_IPR2_PRI_11_M 0xFF000000 -#define CPU_SCS_NVIC_IPR2_PRI_11_S 24 +#define CPU_SCS_NVIC_IPR2_PRI_11_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_11_M 0xFF000000 +#define CPU_SCS_NVIC_IPR2_PRI_11_S 24 // Field: [23:16] PRI_10 // // Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). -#define CPU_SCS_NVIC_IPR2_PRI_10_W 8 -#define CPU_SCS_NVIC_IPR2_PRI_10_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR2_PRI_10_S 16 +#define CPU_SCS_NVIC_IPR2_PRI_10_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_10_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR2_PRI_10_S 16 // Field: [15:8] PRI_9 // // Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). -#define CPU_SCS_NVIC_IPR2_PRI_9_W 8 -#define CPU_SCS_NVIC_IPR2_PRI_9_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR2_PRI_9_S 8 +#define CPU_SCS_NVIC_IPR2_PRI_9_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_9_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR2_PRI_9_S 8 // Field: [7:0] PRI_8 // // Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). -#define CPU_SCS_NVIC_IPR2_PRI_8_W 8 -#define CPU_SCS_NVIC_IPR2_PRI_8_M 0x000000FF -#define CPU_SCS_NVIC_IPR2_PRI_8_S 0 +#define CPU_SCS_NVIC_IPR2_PRI_8_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_8_M 0x000000FF +#define CPU_SCS_NVIC_IPR2_PRI_8_S 0 //***************************************************************************** // @@ -2249,30 +2249,30 @@ // Field: [31:24] PRI_15 // // Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). -#define CPU_SCS_NVIC_IPR3_PRI_15_W 8 -#define CPU_SCS_NVIC_IPR3_PRI_15_M 0xFF000000 -#define CPU_SCS_NVIC_IPR3_PRI_15_S 24 +#define CPU_SCS_NVIC_IPR3_PRI_15_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_15_M 0xFF000000 +#define CPU_SCS_NVIC_IPR3_PRI_15_S 24 // Field: [23:16] PRI_14 // // Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). -#define CPU_SCS_NVIC_IPR3_PRI_14_W 8 -#define CPU_SCS_NVIC_IPR3_PRI_14_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR3_PRI_14_S 16 +#define CPU_SCS_NVIC_IPR3_PRI_14_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_14_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR3_PRI_14_S 16 // Field: [15:8] PRI_13 // // Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). -#define CPU_SCS_NVIC_IPR3_PRI_13_W 8 -#define CPU_SCS_NVIC_IPR3_PRI_13_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR3_PRI_13_S 8 +#define CPU_SCS_NVIC_IPR3_PRI_13_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_13_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR3_PRI_13_S 8 // Field: [7:0] PRI_12 // // Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). -#define CPU_SCS_NVIC_IPR3_PRI_12_W 8 -#define CPU_SCS_NVIC_IPR3_PRI_12_M 0x000000FF -#define CPU_SCS_NVIC_IPR3_PRI_12_S 0 +#define CPU_SCS_NVIC_IPR3_PRI_12_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_12_M 0x000000FF +#define CPU_SCS_NVIC_IPR3_PRI_12_S 0 //***************************************************************************** // @@ -2282,30 +2282,30 @@ // Field: [31:24] PRI_19 // // Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). -#define CPU_SCS_NVIC_IPR4_PRI_19_W 8 -#define CPU_SCS_NVIC_IPR4_PRI_19_M 0xFF000000 -#define CPU_SCS_NVIC_IPR4_PRI_19_S 24 +#define CPU_SCS_NVIC_IPR4_PRI_19_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_19_M 0xFF000000 +#define CPU_SCS_NVIC_IPR4_PRI_19_S 24 // Field: [23:16] PRI_18 // // Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). -#define CPU_SCS_NVIC_IPR4_PRI_18_W 8 -#define CPU_SCS_NVIC_IPR4_PRI_18_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR4_PRI_18_S 16 +#define CPU_SCS_NVIC_IPR4_PRI_18_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_18_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR4_PRI_18_S 16 // Field: [15:8] PRI_17 // // Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). -#define CPU_SCS_NVIC_IPR4_PRI_17_W 8 -#define CPU_SCS_NVIC_IPR4_PRI_17_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR4_PRI_17_S 8 +#define CPU_SCS_NVIC_IPR4_PRI_17_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_17_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR4_PRI_17_S 8 // Field: [7:0] PRI_16 // // Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). -#define CPU_SCS_NVIC_IPR4_PRI_16_W 8 -#define CPU_SCS_NVIC_IPR4_PRI_16_M 0x000000FF -#define CPU_SCS_NVIC_IPR4_PRI_16_S 0 +#define CPU_SCS_NVIC_IPR4_PRI_16_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_16_M 0x000000FF +#define CPU_SCS_NVIC_IPR4_PRI_16_S 0 //***************************************************************************** // @@ -2315,30 +2315,30 @@ // Field: [31:24] PRI_23 // // Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). -#define CPU_SCS_NVIC_IPR5_PRI_23_W 8 -#define CPU_SCS_NVIC_IPR5_PRI_23_M 0xFF000000 -#define CPU_SCS_NVIC_IPR5_PRI_23_S 24 +#define CPU_SCS_NVIC_IPR5_PRI_23_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_23_M 0xFF000000 +#define CPU_SCS_NVIC_IPR5_PRI_23_S 24 // Field: [23:16] PRI_22 // // Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). -#define CPU_SCS_NVIC_IPR5_PRI_22_W 8 -#define CPU_SCS_NVIC_IPR5_PRI_22_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR5_PRI_22_S 16 +#define CPU_SCS_NVIC_IPR5_PRI_22_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_22_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR5_PRI_22_S 16 // Field: [15:8] PRI_21 // // Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). -#define CPU_SCS_NVIC_IPR5_PRI_21_W 8 -#define CPU_SCS_NVIC_IPR5_PRI_21_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR5_PRI_21_S 8 +#define CPU_SCS_NVIC_IPR5_PRI_21_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_21_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR5_PRI_21_S 8 // Field: [7:0] PRI_20 // // Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). -#define CPU_SCS_NVIC_IPR5_PRI_20_W 8 -#define CPU_SCS_NVIC_IPR5_PRI_20_M 0x000000FF -#define CPU_SCS_NVIC_IPR5_PRI_20_S 0 +#define CPU_SCS_NVIC_IPR5_PRI_20_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_20_M 0x000000FF +#define CPU_SCS_NVIC_IPR5_PRI_20_S 0 //***************************************************************************** // @@ -2348,30 +2348,30 @@ // Field: [31:24] PRI_27 // // Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). -#define CPU_SCS_NVIC_IPR6_PRI_27_W 8 -#define CPU_SCS_NVIC_IPR6_PRI_27_M 0xFF000000 -#define CPU_SCS_NVIC_IPR6_PRI_27_S 24 +#define CPU_SCS_NVIC_IPR6_PRI_27_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_27_M 0xFF000000 +#define CPU_SCS_NVIC_IPR6_PRI_27_S 24 // Field: [23:16] PRI_26 // // Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). -#define CPU_SCS_NVIC_IPR6_PRI_26_W 8 -#define CPU_SCS_NVIC_IPR6_PRI_26_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR6_PRI_26_S 16 +#define CPU_SCS_NVIC_IPR6_PRI_26_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_26_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR6_PRI_26_S 16 // Field: [15:8] PRI_25 // // Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). -#define CPU_SCS_NVIC_IPR6_PRI_25_W 8 -#define CPU_SCS_NVIC_IPR6_PRI_25_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR6_PRI_25_S 8 +#define CPU_SCS_NVIC_IPR6_PRI_25_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_25_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR6_PRI_25_S 8 // Field: [7:0] PRI_24 // // Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). -#define CPU_SCS_NVIC_IPR6_PRI_24_W 8 -#define CPU_SCS_NVIC_IPR6_PRI_24_M 0x000000FF -#define CPU_SCS_NVIC_IPR6_PRI_24_S 0 +#define CPU_SCS_NVIC_IPR6_PRI_24_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_24_M 0x000000FF +#define CPU_SCS_NVIC_IPR6_PRI_24_S 0 //***************************************************************************** // @@ -2381,30 +2381,30 @@ // Field: [31:24] PRI_31 // // Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). -#define CPU_SCS_NVIC_IPR7_PRI_31_W 8 -#define CPU_SCS_NVIC_IPR7_PRI_31_M 0xFF000000 -#define CPU_SCS_NVIC_IPR7_PRI_31_S 24 +#define CPU_SCS_NVIC_IPR7_PRI_31_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_31_M 0xFF000000 +#define CPU_SCS_NVIC_IPR7_PRI_31_S 24 // Field: [23:16] PRI_30 // // Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). -#define CPU_SCS_NVIC_IPR7_PRI_30_W 8 -#define CPU_SCS_NVIC_IPR7_PRI_30_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR7_PRI_30_S 16 +#define CPU_SCS_NVIC_IPR7_PRI_30_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_30_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR7_PRI_30_S 16 // Field: [15:8] PRI_29 // // Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). -#define CPU_SCS_NVIC_IPR7_PRI_29_W 8 -#define CPU_SCS_NVIC_IPR7_PRI_29_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR7_PRI_29_S 8 +#define CPU_SCS_NVIC_IPR7_PRI_29_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_29_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR7_PRI_29_S 8 // Field: [7:0] PRI_28 // // Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). -#define CPU_SCS_NVIC_IPR7_PRI_28_W 8 -#define CPU_SCS_NVIC_IPR7_PRI_28_M 0x000000FF -#define CPU_SCS_NVIC_IPR7_PRI_28_S 0 +#define CPU_SCS_NVIC_IPR7_PRI_28_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_28_M 0x000000FF +#define CPU_SCS_NVIC_IPR7_PRI_28_S 0 //***************************************************************************** // @@ -2414,16 +2414,16 @@ // Field: [15:8] PRI_33 // // Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). -#define CPU_SCS_NVIC_IPR8_PRI_33_W 8 -#define CPU_SCS_NVIC_IPR8_PRI_33_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR8_PRI_33_S 8 +#define CPU_SCS_NVIC_IPR8_PRI_33_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_33_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR8_PRI_33_S 8 // Field: [7:0] PRI_32 // // Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). -#define CPU_SCS_NVIC_IPR8_PRI_32_W 8 -#define CPU_SCS_NVIC_IPR8_PRI_32_M 0x000000FF -#define CPU_SCS_NVIC_IPR8_PRI_32_S 0 +#define CPU_SCS_NVIC_IPR8_PRI_32_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_32_M 0x000000FF +#define CPU_SCS_NVIC_IPR8_PRI_32_S 0 //***************************************************************************** // @@ -2433,37 +2433,37 @@ // Field: [31:24] IMPLEMENTER // // Implementor code. -#define CPU_SCS_CPUID_IMPLEMENTER_W 8 -#define CPU_SCS_CPUID_IMPLEMENTER_M 0xFF000000 -#define CPU_SCS_CPUID_IMPLEMENTER_S 24 +#define CPU_SCS_CPUID_IMPLEMENTER_W 8 +#define CPU_SCS_CPUID_IMPLEMENTER_M 0xFF000000 +#define CPU_SCS_CPUID_IMPLEMENTER_S 24 // Field: [23:20] VARIANT // // Implementation defined variant number. -#define CPU_SCS_CPUID_VARIANT_W 4 -#define CPU_SCS_CPUID_VARIANT_M 0x00F00000 -#define CPU_SCS_CPUID_VARIANT_S 20 +#define CPU_SCS_CPUID_VARIANT_W 4 +#define CPU_SCS_CPUID_VARIANT_M 0x00F00000 +#define CPU_SCS_CPUID_VARIANT_S 20 // Field: [19:16] CONSTANT // // Reads as 0xF -#define CPU_SCS_CPUID_CONSTANT_W 4 -#define CPU_SCS_CPUID_CONSTANT_M 0x000F0000 -#define CPU_SCS_CPUID_CONSTANT_S 16 +#define CPU_SCS_CPUID_CONSTANT_W 4 +#define CPU_SCS_CPUID_CONSTANT_M 0x000F0000 +#define CPU_SCS_CPUID_CONSTANT_S 16 // Field: [15:4] PARTNO // // Number of processor within family. -#define CPU_SCS_CPUID_PARTNO_W 12 -#define CPU_SCS_CPUID_PARTNO_M 0x0000FFF0 -#define CPU_SCS_CPUID_PARTNO_S 4 +#define CPU_SCS_CPUID_PARTNO_W 12 +#define CPU_SCS_CPUID_PARTNO_M 0x0000FFF0 +#define CPU_SCS_CPUID_PARTNO_S 4 // Field: [3:0] REVISION // // Implementation defined revision number. -#define CPU_SCS_CPUID_REVISION_W 4 -#define CPU_SCS_CPUID_REVISION_M 0x0000000F -#define CPU_SCS_CPUID_REVISION_S 0 +#define CPU_SCS_CPUID_REVISION_W 4 +#define CPU_SCS_CPUID_REVISION_M 0x0000000F +#define CPU_SCS_CPUID_REVISION_S 0 //***************************************************************************** // @@ -2478,10 +2478,10 @@ // // 0: No action // 1: Set pending NMI -#define CPU_SCS_ICSR_NMIPENDSET 0x80000000 -#define CPU_SCS_ICSR_NMIPENDSET_BITN 31 -#define CPU_SCS_ICSR_NMIPENDSET_M 0x80000000 -#define CPU_SCS_ICSR_NMIPENDSET_S 31 +#define CPU_SCS_ICSR_NMIPENDSET 0x80000000 +#define CPU_SCS_ICSR_NMIPENDSET_BITN 31 +#define CPU_SCS_ICSR_NMIPENDSET_M 0x80000000 +#define CPU_SCS_ICSR_NMIPENDSET_S 31 // Field: [28] PENDSVSET // @@ -2489,10 +2489,10 @@ // // 0: No action // 1: Set pending PendSV -#define CPU_SCS_ICSR_PENDSVSET 0x10000000 -#define CPU_SCS_ICSR_PENDSVSET_BITN 28 -#define CPU_SCS_ICSR_PENDSVSET_M 0x10000000 -#define CPU_SCS_ICSR_PENDSVSET_S 28 +#define CPU_SCS_ICSR_PENDSVSET 0x10000000 +#define CPU_SCS_ICSR_PENDSVSET_BITN 28 +#define CPU_SCS_ICSR_PENDSVSET_M 0x10000000 +#define CPU_SCS_ICSR_PENDSVSET_S 28 // Field: [27] PENDSVCLR // @@ -2500,10 +2500,10 @@ // // 0: No action // 1: Clear pending pendSV -#define CPU_SCS_ICSR_PENDSVCLR 0x08000000 -#define CPU_SCS_ICSR_PENDSVCLR_BITN 27 -#define CPU_SCS_ICSR_PENDSVCLR_M 0x08000000 -#define CPU_SCS_ICSR_PENDSVCLR_S 27 +#define CPU_SCS_ICSR_PENDSVCLR 0x08000000 +#define CPU_SCS_ICSR_PENDSVCLR_BITN 27 +#define CPU_SCS_ICSR_PENDSVCLR_M 0x08000000 +#define CPU_SCS_ICSR_PENDSVCLR_S 27 // Field: [26] PENDSTSET // @@ -2511,10 +2511,10 @@ // // 0: No action // 1: Set pending SysTick -#define CPU_SCS_ICSR_PENDSTSET 0x04000000 -#define CPU_SCS_ICSR_PENDSTSET_BITN 26 -#define CPU_SCS_ICSR_PENDSTSET_M 0x04000000 -#define CPU_SCS_ICSR_PENDSTSET_S 26 +#define CPU_SCS_ICSR_PENDSTSET 0x04000000 +#define CPU_SCS_ICSR_PENDSTSET_BITN 26 +#define CPU_SCS_ICSR_PENDSTSET_M 0x04000000 +#define CPU_SCS_ICSR_PENDSTSET_S 26 // Field: [25] PENDSTCLR // @@ -2522,10 +2522,10 @@ // // 0: No action // 1: Clear pending SysTick -#define CPU_SCS_ICSR_PENDSTCLR 0x02000000 -#define CPU_SCS_ICSR_PENDSTCLR_BITN 25 -#define CPU_SCS_ICSR_PENDSTCLR_M 0x02000000 -#define CPU_SCS_ICSR_PENDSTCLR_S 25 +#define CPU_SCS_ICSR_PENDSTCLR 0x02000000 +#define CPU_SCS_ICSR_PENDSTCLR_BITN 25 +#define CPU_SCS_ICSR_PENDSTCLR_M 0x02000000 +#define CPU_SCS_ICSR_PENDSTCLR_S 25 // Field: [23] ISRPREEMPT // @@ -2535,10 +2535,10 @@ // // 0: A pending exception is not serviced. // 1: A pending exception is serviced on exit from the debug halt state -#define CPU_SCS_ICSR_ISRPREEMPT 0x00800000 -#define CPU_SCS_ICSR_ISRPREEMPT_BITN 23 -#define CPU_SCS_ICSR_ISRPREEMPT_M 0x00800000 -#define CPU_SCS_ICSR_ISRPREEMPT_S 23 +#define CPU_SCS_ICSR_ISRPREEMPT 0x00800000 +#define CPU_SCS_ICSR_ISRPREEMPT_BITN 23 +#define CPU_SCS_ICSR_ISRPREEMPT_M 0x00800000 +#define CPU_SCS_ICSR_ISRPREEMPT_S 23 // Field: [22] ISRPENDING // @@ -2546,18 +2546,18 @@ // // 0x0: Interrupt not pending // 0x1: Interrupt pending -#define CPU_SCS_ICSR_ISRPENDING 0x00400000 -#define CPU_SCS_ICSR_ISRPENDING_BITN 22 -#define CPU_SCS_ICSR_ISRPENDING_M 0x00400000 -#define CPU_SCS_ICSR_ISRPENDING_S 22 +#define CPU_SCS_ICSR_ISRPENDING 0x00400000 +#define CPU_SCS_ICSR_ISRPENDING_BITN 22 +#define CPU_SCS_ICSR_ISRPENDING_M 0x00400000 +#define CPU_SCS_ICSR_ISRPENDING_S 22 // Field: [17:12] VECTPENDING // // Pending ISR number field. This field contains the interrupt number of the // highest priority pending ISR. -#define CPU_SCS_ICSR_VECTPENDING_W 6 -#define CPU_SCS_ICSR_VECTPENDING_M 0x0003F000 -#define CPU_SCS_ICSR_VECTPENDING_S 12 +#define CPU_SCS_ICSR_VECTPENDING_W 6 +#define CPU_SCS_ICSR_VECTPENDING_M 0x0003F000 +#define CPU_SCS_ICSR_VECTPENDING_S 12 // Field: [11] RETTOBASE // @@ -2566,17 +2566,17 @@ // 0: There are preempted active exceptions to execute // 1: There are no active exceptions, or the currently-executing exception is // the only active exception. -#define CPU_SCS_ICSR_RETTOBASE 0x00000800 -#define CPU_SCS_ICSR_RETTOBASE_BITN 11 -#define CPU_SCS_ICSR_RETTOBASE_M 0x00000800 -#define CPU_SCS_ICSR_RETTOBASE_S 11 +#define CPU_SCS_ICSR_RETTOBASE 0x00000800 +#define CPU_SCS_ICSR_RETTOBASE_BITN 11 +#define CPU_SCS_ICSR_RETTOBASE_M 0x00000800 +#define CPU_SCS_ICSR_RETTOBASE_S 11 // Field: [8:0] VECTACTIVE // // Active ISR number field. Reset clears this field. -#define CPU_SCS_ICSR_VECTACTIVE_W 9 -#define CPU_SCS_ICSR_VECTACTIVE_M 0x000001FF -#define CPU_SCS_ICSR_VECTACTIVE_S 0 +#define CPU_SCS_ICSR_VECTACTIVE_W 9 +#define CPU_SCS_ICSR_VECTACTIVE_M 0x000001FF +#define CPU_SCS_ICSR_VECTACTIVE_S 0 //***************************************************************************** // @@ -2586,9 +2586,9 @@ // Field: [29:7] TBLOFF // // Bits 29 down to 7 of the vector table base offset. -#define CPU_SCS_VTOR_TBLOFF_W 23 -#define CPU_SCS_VTOR_TBLOFF_M 0x3FFFFF80 -#define CPU_SCS_VTOR_TBLOFF_S 7 +#define CPU_SCS_VTOR_TBLOFF_W 23 +#define CPU_SCS_VTOR_TBLOFF_M 0x3FFFFF80 +#define CPU_SCS_VTOR_TBLOFF_S 7 //***************************************************************************** // @@ -2599,9 +2599,9 @@ // // Register key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. // Otherwise the write value is ignored. Read always returns 0xFA05. -#define CPU_SCS_AIRCR_VECTKEY_W 16 -#define CPU_SCS_AIRCR_VECTKEY_M 0xFFFF0000 -#define CPU_SCS_AIRCR_VECTKEY_S 16 +#define CPU_SCS_AIRCR_VECTKEY_W 16 +#define CPU_SCS_AIRCR_VECTKEY_M 0xFFFF0000 +#define CPU_SCS_AIRCR_VECTKEY_S 16 // Field: [15] ENDIANESS // @@ -2609,12 +2609,12 @@ // ENUMs: // BIG Big endian // LITTLE Little endian -#define CPU_SCS_AIRCR_ENDIANESS 0x00008000 -#define CPU_SCS_AIRCR_ENDIANESS_BITN 15 -#define CPU_SCS_AIRCR_ENDIANESS_M 0x00008000 -#define CPU_SCS_AIRCR_ENDIANESS_S 15 -#define CPU_SCS_AIRCR_ENDIANESS_BIG 0x00008000 -#define CPU_SCS_AIRCR_ENDIANESS_LITTLE 0x00000000 +#define CPU_SCS_AIRCR_ENDIANESS 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_BITN 15 +#define CPU_SCS_AIRCR_ENDIANESS_M 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_S 15 +#define CPU_SCS_AIRCR_ENDIANESS_BIG 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_LITTLE 0x00000000 // Field: [10:8] PRIGROUP // @@ -2626,18 +2626,18 @@ // means that the PRIGROUP value represents a point starting at the left of the // Least Significant Bit (LSB). The lowest value might not be 0 depending on // the number of bits allocated for priorities, and implementation choices. -#define CPU_SCS_AIRCR_PRIGROUP_W 3 -#define CPU_SCS_AIRCR_PRIGROUP_M 0x00000700 -#define CPU_SCS_AIRCR_PRIGROUP_S 8 +#define CPU_SCS_AIRCR_PRIGROUP_W 3 +#define CPU_SCS_AIRCR_PRIGROUP_M 0x00000700 +#define CPU_SCS_AIRCR_PRIGROUP_S 8 // Field: [2] SYSRESETREQ // // Requests a warm reset. Setting this bit does not prevent Halting Debug from // running. -#define CPU_SCS_AIRCR_SYSRESETREQ 0x00000004 -#define CPU_SCS_AIRCR_SYSRESETREQ_BITN 2 -#define CPU_SCS_AIRCR_SYSRESETREQ_M 0x00000004 -#define CPU_SCS_AIRCR_SYSRESETREQ_S 2 +#define CPU_SCS_AIRCR_SYSRESETREQ 0x00000004 +#define CPU_SCS_AIRCR_SYSRESETREQ_BITN 2 +#define CPU_SCS_AIRCR_SYSRESETREQ_M 0x00000004 +#define CPU_SCS_AIRCR_SYSRESETREQ_S 2 // Field: [1] VECTCLRACTIVE // @@ -2647,10 +2647,10 @@ // IPSR is not cleared by this operation. So, if used by an application, it // must only be used at the base level of activation, or within a system // handler whose active bit can be set. -#define CPU_SCS_AIRCR_VECTCLRACTIVE 0x00000002 -#define CPU_SCS_AIRCR_VECTCLRACTIVE_BITN 1 -#define CPU_SCS_AIRCR_VECTCLRACTIVE_M 0x00000002 -#define CPU_SCS_AIRCR_VECTCLRACTIVE_S 1 +#define CPU_SCS_AIRCR_VECTCLRACTIVE 0x00000002 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_BITN 1 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_M 0x00000002 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_S 1 // Field: [0] VECTRESET // @@ -2658,10 +2658,10 @@ // This bit is reserved for debug use and can be written to 1 only when the // core is halted. The bit self-clears. Writing this bit to 1 while core is not // halted may result in unpredictable behavior. -#define CPU_SCS_AIRCR_VECTRESET 0x00000001 -#define CPU_SCS_AIRCR_VECTRESET_BITN 0 -#define CPU_SCS_AIRCR_VECTRESET_M 0x00000001 -#define CPU_SCS_AIRCR_VECTRESET_S 0 +#define CPU_SCS_AIRCR_VECTRESET 0x00000001 +#define CPU_SCS_AIRCR_VECTRESET_BITN 0 +#define CPU_SCS_AIRCR_VECTRESET_M 0x00000001 +#define CPU_SCS_AIRCR_VECTRESET_S 0 //***************************************************************************** // @@ -2682,10 +2682,10 @@ // the processor is not waiting for an event, the event is registered and // affects the next WFE. // The processor also wakes up on execution of an SEV instruction. -#define CPU_SCS_SCR_SEVONPEND 0x00000010 -#define CPU_SCS_SCR_SEVONPEND_BITN 4 -#define CPU_SCS_SCR_SEVONPEND_M 0x00000010 -#define CPU_SCS_SCR_SEVONPEND_S 4 +#define CPU_SCS_SCR_SEVONPEND 0x00000010 +#define CPU_SCS_SCR_SEVONPEND_BITN 4 +#define CPU_SCS_SCR_SEVONPEND_M 0x00000010 +#define CPU_SCS_SCR_SEVONPEND_S 4 // Field: [2] SLEEPDEEP // @@ -2694,12 +2694,12 @@ // ENUMs: // DEEPSLEEP Deep sleep // SLEEP Sleep -#define CPU_SCS_SCR_SLEEPDEEP 0x00000004 -#define CPU_SCS_SCR_SLEEPDEEP_BITN 2 -#define CPU_SCS_SCR_SLEEPDEEP_M 0x00000004 -#define CPU_SCS_SCR_SLEEPDEEP_S 2 -#define CPU_SCS_SCR_SLEEPDEEP_DEEPSLEEP 0x00000004 -#define CPU_SCS_SCR_SLEEPDEEP_SLEEP 0x00000000 +#define CPU_SCS_SCR_SLEEPDEEP 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_BITN 2 +#define CPU_SCS_SCR_SLEEPDEEP_M 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_S 2 +#define CPU_SCS_SCR_SLEEPDEEP_DEEPSLEEP 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_SLEEP 0x00000000 // Field: [1] SLEEPONEXIT // @@ -2708,10 +2708,10 @@ // // 0: Do not sleep when returning to thread mode // 1: Sleep on ISR exit -#define CPU_SCS_SCR_SLEEPONEXIT 0x00000002 -#define CPU_SCS_SCR_SLEEPONEXIT_BITN 1 -#define CPU_SCS_SCR_SLEEPONEXIT_M 0x00000002 -#define CPU_SCS_SCR_SLEEPONEXIT_S 1 +#define CPU_SCS_SCR_SLEEPONEXIT 0x00000002 +#define CPU_SCS_SCR_SLEEPONEXIT_BITN 1 +#define CPU_SCS_SCR_SLEEPONEXIT_M 0x00000002 +#define CPU_SCS_SCR_SLEEPONEXIT_S 1 //***************************************************************************** // @@ -2727,10 +2727,10 @@ // 1: On exception entry, the SP used prior to the exception is adjusted to be // 8-byte aligned and the context to restore it is saved. The SP is restored on // the associated exception return. -#define CPU_SCS_CCR_STKALIGN 0x00000200 -#define CPU_SCS_CCR_STKALIGN_BITN 9 -#define CPU_SCS_CCR_STKALIGN_M 0x00000200 -#define CPU_SCS_CCR_STKALIGN_S 9 +#define CPU_SCS_CCR_STKALIGN 0x00000200 +#define CPU_SCS_CCR_STKALIGN_BITN 9 +#define CPU_SCS_CCR_STKALIGN_M 0x00000200 +#define CPU_SCS_CCR_STKALIGN_S 9 // Field: [8] BFHFNMIGN // @@ -2744,10 +2744,10 @@ // Set this bit to 1 only when the handler and its data are in absolutely safe // memory. The normal use // of this bit is to probe system devices and bridges to detect problems. -#define CPU_SCS_CCR_BFHFNMIGN 0x00000100 -#define CPU_SCS_CCR_BFHFNMIGN_BITN 8 -#define CPU_SCS_CCR_BFHFNMIGN_M 0x00000100 -#define CPU_SCS_CCR_BFHFNMIGN_S 8 +#define CPU_SCS_CCR_BFHFNMIGN 0x00000100 +#define CPU_SCS_CCR_BFHFNMIGN_BITN 8 +#define CPU_SCS_CCR_BFHFNMIGN_M 0x00000100 +#define CPU_SCS_CCR_BFHFNMIGN_S 8 // Field: [4] DIV_0_TRP // @@ -2758,10 +2758,10 @@ // quotient of 0. // 1: Trap divide by 0. The relevant Usage Fault Status Register bit is // CFSR.DIVBYZERO. -#define CPU_SCS_CCR_DIV_0_TRP 0x00000010 -#define CPU_SCS_CCR_DIV_0_TRP_BITN 4 -#define CPU_SCS_CCR_DIV_0_TRP_M 0x00000010 -#define CPU_SCS_CCR_DIV_0_TRP_S 4 +#define CPU_SCS_CCR_DIV_0_TRP 0x00000010 +#define CPU_SCS_CCR_DIV_0_TRP_BITN 4 +#define CPU_SCS_CCR_DIV_0_TRP_M 0x00000010 +#define CPU_SCS_CCR_DIV_0_TRP_S 4 // Field: [3] UNALIGN_TRP // @@ -2774,10 +2774,10 @@ // If this bit is set to 1, an unaligned access generates a UsageFault. // Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of // the value in UNALIGN_TRP. -#define CPU_SCS_CCR_UNALIGN_TRP 0x00000008 -#define CPU_SCS_CCR_UNALIGN_TRP_BITN 3 -#define CPU_SCS_CCR_UNALIGN_TRP_M 0x00000008 -#define CPU_SCS_CCR_UNALIGN_TRP_S 3 +#define CPU_SCS_CCR_UNALIGN_TRP 0x00000008 +#define CPU_SCS_CCR_UNALIGN_TRP_BITN 3 +#define CPU_SCS_CCR_UNALIGN_TRP_M 0x00000008 +#define CPU_SCS_CCR_UNALIGN_TRP_S 3 // Field: [1] USERSETMPEND // @@ -2788,10 +2788,10 @@ // 1: User code can write the Software Trigger Interrupt register (STIR) to // trigger (pend) a Main exception, which is associated with the Main stack // pointer. -#define CPU_SCS_CCR_USERSETMPEND 0x00000002 -#define CPU_SCS_CCR_USERSETMPEND_BITN 1 -#define CPU_SCS_CCR_USERSETMPEND_M 0x00000002 -#define CPU_SCS_CCR_USERSETMPEND_S 1 +#define CPU_SCS_CCR_USERSETMPEND 0x00000002 +#define CPU_SCS_CCR_USERSETMPEND_BITN 1 +#define CPU_SCS_CCR_USERSETMPEND_M 0x00000002 +#define CPU_SCS_CCR_USERSETMPEND_S 1 // Field: [0] NONBASETHREDENA // @@ -2808,10 +2808,10 @@ // - BX with any register. // The value written to the PC is intercepted and is referred to as the // EXC_RETURN value. -#define CPU_SCS_CCR_NONBASETHREDENA 0x00000001 -#define CPU_SCS_CCR_NONBASETHREDENA_BITN 0 -#define CPU_SCS_CCR_NONBASETHREDENA_M 0x00000001 -#define CPU_SCS_CCR_NONBASETHREDENA_S 0 +#define CPU_SCS_CCR_NONBASETHREDENA 0x00000001 +#define CPU_SCS_CCR_NONBASETHREDENA_BITN 0 +#define CPU_SCS_CCR_NONBASETHREDENA_M 0x00000001 +#define CPU_SCS_CCR_NONBASETHREDENA_S 0 //***************************************************************************** // @@ -2821,23 +2821,23 @@ // Field: [23:16] PRI_6 // // Priority of system handler 6. UsageFault -#define CPU_SCS_SHPR1_PRI_6_W 8 -#define CPU_SCS_SHPR1_PRI_6_M 0x00FF0000 -#define CPU_SCS_SHPR1_PRI_6_S 16 +#define CPU_SCS_SHPR1_PRI_6_W 8 +#define CPU_SCS_SHPR1_PRI_6_M 0x00FF0000 +#define CPU_SCS_SHPR1_PRI_6_S 16 // Field: [15:8] PRI_5 // // Priority of system handler 5: BusFault -#define CPU_SCS_SHPR1_PRI_5_W 8 -#define CPU_SCS_SHPR1_PRI_5_M 0x0000FF00 -#define CPU_SCS_SHPR1_PRI_5_S 8 +#define CPU_SCS_SHPR1_PRI_5_W 8 +#define CPU_SCS_SHPR1_PRI_5_M 0x0000FF00 +#define CPU_SCS_SHPR1_PRI_5_S 8 // Field: [7:0] PRI_4 // // Priority of system handler 4: MemManage -#define CPU_SCS_SHPR1_PRI_4_W 8 -#define CPU_SCS_SHPR1_PRI_4_M 0x000000FF -#define CPU_SCS_SHPR1_PRI_4_S 0 +#define CPU_SCS_SHPR1_PRI_4_W 8 +#define CPU_SCS_SHPR1_PRI_4_M 0x000000FF +#define CPU_SCS_SHPR1_PRI_4_S 0 //***************************************************************************** // @@ -2847,9 +2847,9 @@ // Field: [31:24] PRI_11 // // Priority of system handler 11. SVCall -#define CPU_SCS_SHPR2_PRI_11_W 8 -#define CPU_SCS_SHPR2_PRI_11_M 0xFF000000 -#define CPU_SCS_SHPR2_PRI_11_S 24 +#define CPU_SCS_SHPR2_PRI_11_W 8 +#define CPU_SCS_SHPR2_PRI_11_M 0xFF000000 +#define CPU_SCS_SHPR2_PRI_11_S 24 //***************************************************************************** // @@ -2859,23 +2859,23 @@ // Field: [31:24] PRI_15 // // Priority of system handler 15. SysTick exception -#define CPU_SCS_SHPR3_PRI_15_W 8 -#define CPU_SCS_SHPR3_PRI_15_M 0xFF000000 -#define CPU_SCS_SHPR3_PRI_15_S 24 +#define CPU_SCS_SHPR3_PRI_15_W 8 +#define CPU_SCS_SHPR3_PRI_15_M 0xFF000000 +#define CPU_SCS_SHPR3_PRI_15_S 24 // Field: [23:16] PRI_14 // // Priority of system handler 14. Pend SV -#define CPU_SCS_SHPR3_PRI_14_W 8 -#define CPU_SCS_SHPR3_PRI_14_M 0x00FF0000 -#define CPU_SCS_SHPR3_PRI_14_S 16 +#define CPU_SCS_SHPR3_PRI_14_W 8 +#define CPU_SCS_SHPR3_PRI_14_M 0x00FF0000 +#define CPU_SCS_SHPR3_PRI_14_S 16 // Field: [7:0] PRI_12 // // Priority of system handler 12. Debug Monitor -#define CPU_SCS_SHPR3_PRI_12_W 8 -#define CPU_SCS_SHPR3_PRI_12_M 0x000000FF -#define CPU_SCS_SHPR3_PRI_12_S 0 +#define CPU_SCS_SHPR3_PRI_12_W 8 +#define CPU_SCS_SHPR3_PRI_12_M 0x000000FF +#define CPU_SCS_SHPR3_PRI_12_S 0 //***************************************************************************** // @@ -2888,12 +2888,12 @@ // ENUMs: // EN Exception enabled // DIS Exception disabled -#define CPU_SCS_SHCSR_USGFAULTENA 0x00040000 -#define CPU_SCS_SHCSR_USGFAULTENA_BITN 18 -#define CPU_SCS_SHCSR_USGFAULTENA_M 0x00040000 -#define CPU_SCS_SHCSR_USGFAULTENA_S 18 -#define CPU_SCS_SHCSR_USGFAULTENA_EN 0x00040000 -#define CPU_SCS_SHCSR_USGFAULTENA_DIS 0x00000000 +#define CPU_SCS_SHCSR_USGFAULTENA 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_BITN 18 +#define CPU_SCS_SHCSR_USGFAULTENA_M 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_S 18 +#define CPU_SCS_SHCSR_USGFAULTENA_EN 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_DIS 0x00000000 // Field: [17] BUSFAULTENA // @@ -2901,12 +2901,12 @@ // ENUMs: // EN Exception enabled // DIS Exception disabled -#define CPU_SCS_SHCSR_BUSFAULTENA 0x00020000 -#define CPU_SCS_SHCSR_BUSFAULTENA_BITN 17 -#define CPU_SCS_SHCSR_BUSFAULTENA_M 0x00020000 -#define CPU_SCS_SHCSR_BUSFAULTENA_S 17 -#define CPU_SCS_SHCSR_BUSFAULTENA_EN 0x00020000 -#define CPU_SCS_SHCSR_BUSFAULTENA_DIS 0x00000000 +#define CPU_SCS_SHCSR_BUSFAULTENA 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_BITN 17 +#define CPU_SCS_SHCSR_BUSFAULTENA_M 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_S 17 +#define CPU_SCS_SHCSR_BUSFAULTENA_EN 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_DIS 0x00000000 // Field: [16] MEMFAULTENA // @@ -2914,12 +2914,12 @@ // ENUMs: // EN Exception enabled // DIS Exception disabled -#define CPU_SCS_SHCSR_MEMFAULTENA 0x00010000 -#define CPU_SCS_SHCSR_MEMFAULTENA_BITN 16 -#define CPU_SCS_SHCSR_MEMFAULTENA_M 0x00010000 -#define CPU_SCS_SHCSR_MEMFAULTENA_S 16 -#define CPU_SCS_SHCSR_MEMFAULTENA_EN 0x00010000 -#define CPU_SCS_SHCSR_MEMFAULTENA_DIS 0x00000000 +#define CPU_SCS_SHCSR_MEMFAULTENA 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_BITN 16 +#define CPU_SCS_SHCSR_MEMFAULTENA_M 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_S 16 +#define CPU_SCS_SHCSR_MEMFAULTENA_EN 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_DIS 0x00000000 // Field: [15] SVCALLPENDED // @@ -2927,12 +2927,12 @@ // ENUMs: // PENDING Exception is pending. // NOTPENDING Exception is not active -#define CPU_SCS_SHCSR_SVCALLPENDED 0x00008000 -#define CPU_SCS_SHCSR_SVCALLPENDED_BITN 15 -#define CPU_SCS_SHCSR_SVCALLPENDED_M 0x00008000 -#define CPU_SCS_SHCSR_SVCALLPENDED_S 15 -#define CPU_SCS_SHCSR_SVCALLPENDED_PENDING 0x00008000 -#define CPU_SCS_SHCSR_SVCALLPENDED_NOTPENDING 0x00000000 +#define CPU_SCS_SHCSR_SVCALLPENDED 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_BITN 15 +#define CPU_SCS_SHCSR_SVCALLPENDED_M 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_S 15 +#define CPU_SCS_SHCSR_SVCALLPENDED_PENDING 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_NOTPENDING 0x00000000 // Field: [14] BUSFAULTPENDED // @@ -2940,12 +2940,12 @@ // ENUMs: // PENDING Exception is pending. // NOTPENDING Exception is not active -#define CPU_SCS_SHCSR_BUSFAULTPENDED 0x00004000 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_BITN 14 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_M 0x00004000 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_S 14 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_PENDING 0x00004000 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_NOTPENDING 0x00000000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_BITN 14 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_M 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_S 14 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_PENDING 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_NOTPENDING 0x00000000 // Field: [13] MEMFAULTPENDED // @@ -2953,12 +2953,12 @@ // ENUMs: // PENDING Exception is pending. // NOTPENDING Exception is not active -#define CPU_SCS_SHCSR_MEMFAULTPENDED 0x00002000 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_BITN 13 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_M 0x00002000 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_S 13 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_PENDING 0x00002000 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_NOTPENDING 0x00000000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_BITN 13 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_M 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_S 13 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_PENDING 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_NOTPENDING 0x00000000 // Field: [12] USGFAULTPENDED // @@ -2966,12 +2966,12 @@ // ENUMs: // PENDING Exception is pending. // NOTPENDING Exception is not active -#define CPU_SCS_SHCSR_USGFAULTPENDED 0x00001000 -#define CPU_SCS_SHCSR_USGFAULTPENDED_BITN 12 -#define CPU_SCS_SHCSR_USGFAULTPENDED_M 0x00001000 -#define CPU_SCS_SHCSR_USGFAULTPENDED_S 12 -#define CPU_SCS_SHCSR_USGFAULTPENDED_PENDING 0x00001000 -#define CPU_SCS_SHCSR_USGFAULTPENDED_NOTPENDING 0x00000000 +#define CPU_SCS_SHCSR_USGFAULTPENDED 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_BITN 12 +#define CPU_SCS_SHCSR_USGFAULTPENDED_M 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_S 12 +#define CPU_SCS_SHCSR_USGFAULTPENDED_PENDING 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_NOTPENDING 0x00000000 // Field: [11] SYSTICKACT // @@ -2982,12 +2982,12 @@ // ENUMs: // ACTIVE Exception is active // NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_SYSTICKACT 0x00000800 -#define CPU_SCS_SHCSR_SYSTICKACT_BITN 11 -#define CPU_SCS_SHCSR_SYSTICKACT_M 0x00000800 -#define CPU_SCS_SHCSR_SYSTICKACT_S 11 -#define CPU_SCS_SHCSR_SYSTICKACT_ACTIVE 0x00000800 -#define CPU_SCS_SHCSR_SYSTICKACT_NOTACTIVE 0x00000000 +#define CPU_SCS_SHCSR_SYSTICKACT 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_BITN 11 +#define CPU_SCS_SHCSR_SYSTICKACT_M 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_S 11 +#define CPU_SCS_SHCSR_SYSTICKACT_ACTIVE 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_NOTACTIVE 0x00000000 // Field: [10] PENDSVACT // @@ -2995,10 +2995,10 @@ // // 0x0: Not active // 0x1: Active -#define CPU_SCS_SHCSR_PENDSVACT 0x00000400 -#define CPU_SCS_SHCSR_PENDSVACT_BITN 10 -#define CPU_SCS_SHCSR_PENDSVACT_M 0x00000400 -#define CPU_SCS_SHCSR_PENDSVACT_S 10 +#define CPU_SCS_SHCSR_PENDSVACT 0x00000400 +#define CPU_SCS_SHCSR_PENDSVACT_BITN 10 +#define CPU_SCS_SHCSR_PENDSVACT_M 0x00000400 +#define CPU_SCS_SHCSR_PENDSVACT_S 10 // Field: [8] MONITORACT // @@ -3006,12 +3006,12 @@ // ENUMs: // ACTIVE Exception is active // NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_MONITORACT 0x00000100 -#define CPU_SCS_SHCSR_MONITORACT_BITN 8 -#define CPU_SCS_SHCSR_MONITORACT_M 0x00000100 -#define CPU_SCS_SHCSR_MONITORACT_S 8 -#define CPU_SCS_SHCSR_MONITORACT_ACTIVE 0x00000100 -#define CPU_SCS_SHCSR_MONITORACT_NOTACTIVE 0x00000000 +#define CPU_SCS_SHCSR_MONITORACT 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_BITN 8 +#define CPU_SCS_SHCSR_MONITORACT_M 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_S 8 +#define CPU_SCS_SHCSR_MONITORACT_ACTIVE 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_NOTACTIVE 0x00000000 // Field: [7] SVCALLACT // @@ -3019,12 +3019,12 @@ // ENUMs: // ACTIVE Exception is active // NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_SVCALLACT 0x00000080 -#define CPU_SCS_SHCSR_SVCALLACT_BITN 7 -#define CPU_SCS_SHCSR_SVCALLACT_M 0x00000080 -#define CPU_SCS_SHCSR_SVCALLACT_S 7 -#define CPU_SCS_SHCSR_SVCALLACT_ACTIVE 0x00000080 -#define CPU_SCS_SHCSR_SVCALLACT_NOTACTIVE 0x00000000 +#define CPU_SCS_SHCSR_SVCALLACT 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_BITN 7 +#define CPU_SCS_SHCSR_SVCALLACT_M 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_S 7 +#define CPU_SCS_SHCSR_SVCALLACT_ACTIVE 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_NOTACTIVE 0x00000000 // Field: [3] USGFAULTACT // @@ -3032,12 +3032,12 @@ // ENUMs: // ACTIVE Exception is active // NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_USGFAULTACT 0x00000008 -#define CPU_SCS_SHCSR_USGFAULTACT_BITN 3 -#define CPU_SCS_SHCSR_USGFAULTACT_M 0x00000008 -#define CPU_SCS_SHCSR_USGFAULTACT_S 3 -#define CPU_SCS_SHCSR_USGFAULTACT_ACTIVE 0x00000008 -#define CPU_SCS_SHCSR_USGFAULTACT_NOTACTIVE 0x00000000 +#define CPU_SCS_SHCSR_USGFAULTACT 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_BITN 3 +#define CPU_SCS_SHCSR_USGFAULTACT_M 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_S 3 +#define CPU_SCS_SHCSR_USGFAULTACT_ACTIVE 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_NOTACTIVE 0x00000000 // Field: [1] BUSFAULTACT // @@ -3045,12 +3045,12 @@ // ENUMs: // ACTIVE Exception is active // NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_BUSFAULTACT 0x00000002 -#define CPU_SCS_SHCSR_BUSFAULTACT_BITN 1 -#define CPU_SCS_SHCSR_BUSFAULTACT_M 0x00000002 -#define CPU_SCS_SHCSR_BUSFAULTACT_S 1 -#define CPU_SCS_SHCSR_BUSFAULTACT_ACTIVE 0x00000002 -#define CPU_SCS_SHCSR_BUSFAULTACT_NOTACTIVE 0x00000000 +#define CPU_SCS_SHCSR_BUSFAULTACT 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_BITN 1 +#define CPU_SCS_SHCSR_BUSFAULTACT_M 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_S 1 +#define CPU_SCS_SHCSR_BUSFAULTACT_ACTIVE 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_NOTACTIVE 0x00000000 // Field: [0] MEMFAULTACT // @@ -3058,12 +3058,12 @@ // ENUMs: // ACTIVE Exception is active // NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_MEMFAULTACT 0x00000001 -#define CPU_SCS_SHCSR_MEMFAULTACT_BITN 0 -#define CPU_SCS_SHCSR_MEMFAULTACT_M 0x00000001 -#define CPU_SCS_SHCSR_MEMFAULTACT_S 0 -#define CPU_SCS_SHCSR_MEMFAULTACT_ACTIVE 0x00000001 -#define CPU_SCS_SHCSR_MEMFAULTACT_NOTACTIVE 0x00000000 +#define CPU_SCS_SHCSR_MEMFAULTACT 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_BITN 0 +#define CPU_SCS_SHCSR_MEMFAULTACT_M 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_S 0 +#define CPU_SCS_SHCSR_MEMFAULTACT_ACTIVE 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_NOTACTIVE 0x00000000 //***************************************************************************** // @@ -3076,39 +3076,39 @@ // enabled and an SDIV or UDIV instruction is used with a divisor of 0, this // fault occurs The instruction is executed and the return PC points to it. If // CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0. -#define CPU_SCS_CFSR_DIVBYZERO 0x02000000 -#define CPU_SCS_CFSR_DIVBYZERO_BITN 25 -#define CPU_SCS_CFSR_DIVBYZERO_M 0x02000000 -#define CPU_SCS_CFSR_DIVBYZERO_S 25 +#define CPU_SCS_CFSR_DIVBYZERO 0x02000000 +#define CPU_SCS_CFSR_DIVBYZERO_BITN 25 +#define CPU_SCS_CFSR_DIVBYZERO_M 0x02000000 +#define CPU_SCS_CFSR_DIVBYZERO_S 25 // Field: [24] UNALIGNED // // When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an // unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD // instructions always fault irrespective of the setting of CCR.UNALIGN_TRP. -#define CPU_SCS_CFSR_UNALIGNED 0x01000000 -#define CPU_SCS_CFSR_UNALIGNED_BITN 24 -#define CPU_SCS_CFSR_UNALIGNED_M 0x01000000 -#define CPU_SCS_CFSR_UNALIGNED_S 24 +#define CPU_SCS_CFSR_UNALIGNED 0x01000000 +#define CPU_SCS_CFSR_UNALIGNED_BITN 24 +#define CPU_SCS_CFSR_UNALIGNED_M 0x01000000 +#define CPU_SCS_CFSR_UNALIGNED_S 24 // Field: [19] NOCP // // Attempt to use a coprocessor instruction. The processor does not support // coprocessor instructions. -#define CPU_SCS_CFSR_NOCP 0x00080000 -#define CPU_SCS_CFSR_NOCP_BITN 19 -#define CPU_SCS_CFSR_NOCP_M 0x00080000 -#define CPU_SCS_CFSR_NOCP_S 19 +#define CPU_SCS_CFSR_NOCP 0x00080000 +#define CPU_SCS_CFSR_NOCP_BITN 19 +#define CPU_SCS_CFSR_NOCP_M 0x00080000 +#define CPU_SCS_CFSR_NOCP_S 19 // Field: [18] INVPC // // Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid // context, invalid value. The return PC points to the instruction that tried // to set the PC. -#define CPU_SCS_CFSR_INVPC 0x00040000 -#define CPU_SCS_CFSR_INVPC_BITN 18 -#define CPU_SCS_CFSR_INVPC_M 0x00040000 -#define CPU_SCS_CFSR_INVPC_S 18 +#define CPU_SCS_CFSR_INVPC 0x00040000 +#define CPU_SCS_CFSR_INVPC_BITN 18 +#define CPU_SCS_CFSR_INVPC_M 0x00040000 +#define CPU_SCS_CFSR_INVPC_S 18 // Field: [17] INVSTATE // @@ -3116,20 +3116,20 @@ // type instruction has changed state). This includes state change after entry // to or return from exception, as well as from inter-working instructions. // Return PC points to faulting instruction, with the invalid state. -#define CPU_SCS_CFSR_INVSTATE 0x00020000 -#define CPU_SCS_CFSR_INVSTATE_BITN 17 -#define CPU_SCS_CFSR_INVSTATE_M 0x00020000 -#define CPU_SCS_CFSR_INVSTATE_S 17 +#define CPU_SCS_CFSR_INVSTATE 0x00020000 +#define CPU_SCS_CFSR_INVSTATE_BITN 17 +#define CPU_SCS_CFSR_INVSTATE_M 0x00020000 +#define CPU_SCS_CFSR_INVSTATE_S 17 // Field: [16] UNDEFINSTR // // This bit is set when the processor attempts to execute an undefined // instruction. This is an instruction that the processor cannot decode. The // return PC points to the undefined instruction. -#define CPU_SCS_CFSR_UNDEFINSTR 0x00010000 -#define CPU_SCS_CFSR_UNDEFINSTR_BITN 16 -#define CPU_SCS_CFSR_UNDEFINSTR_M 0x00010000 -#define CPU_SCS_CFSR_UNDEFINSTR_S 16 +#define CPU_SCS_CFSR_UNDEFINSTR 0x00010000 +#define CPU_SCS_CFSR_UNDEFINSTR_BITN 16 +#define CPU_SCS_CFSR_UNDEFINSTR_M 0x00010000 +#define CPU_SCS_CFSR_UNDEFINSTR_S 16 // Field: [15] BFARVALID // @@ -3139,20 +3139,20 @@ // Bus fault occurs that is escalated to a Hard Fault because of priority, the // Hard Fault handler must clear this bit. This prevents problems if returning // to a stacked active Bus fault handler whose BFAR value has been overwritten. -#define CPU_SCS_CFSR_BFARVALID 0x00008000 -#define CPU_SCS_CFSR_BFARVALID_BITN 15 -#define CPU_SCS_CFSR_BFARVALID_M 0x00008000 -#define CPU_SCS_CFSR_BFARVALID_S 15 +#define CPU_SCS_CFSR_BFARVALID 0x00008000 +#define CPU_SCS_CFSR_BFARVALID_BITN 15 +#define CPU_SCS_CFSR_BFARVALID_M 0x00008000 +#define CPU_SCS_CFSR_BFARVALID_S 15 // Field: [12] STKERR // // Stacking from exception has caused one or more bus faults. The SP is still // adjusted and the values in the context area on the stack might be incorrect. // BFAR is not written. -#define CPU_SCS_CFSR_STKERR 0x00001000 -#define CPU_SCS_CFSR_STKERR_BITN 12 -#define CPU_SCS_CFSR_STKERR_M 0x00001000 -#define CPU_SCS_CFSR_STKERR_S 12 +#define CPU_SCS_CFSR_STKERR 0x00001000 +#define CPU_SCS_CFSR_STKERR_BITN 12 +#define CPU_SCS_CFSR_STKERR_M 0x00001000 +#define CPU_SCS_CFSR_STKERR_S 12 // Field: [11] UNSTKERR // @@ -3160,10 +3160,10 @@ // chained to the handler, so that the original return stack is still present. // SP is not adjusted from failing return and new save is not performed. BFAR // is not written. -#define CPU_SCS_CFSR_UNSTKERR 0x00000800 -#define CPU_SCS_CFSR_UNSTKERR_BITN 11 -#define CPU_SCS_CFSR_UNSTKERR_M 0x00000800 -#define CPU_SCS_CFSR_UNSTKERR_S 11 +#define CPU_SCS_CFSR_UNSTKERR 0x00000800 +#define CPU_SCS_CFSR_UNSTKERR_BITN 11 +#define CPU_SCS_CFSR_UNSTKERR_M 0x00000800 +#define CPU_SCS_CFSR_UNSTKERR_S 11 // Field: [10] IMPRECISERR // @@ -3174,28 +3174,28 @@ // activation. If a precise fault occurs before returning to a lower priority // exception, the handler detects both IMPRECISERR set and one of the precise // fault status bits set at the same time. BFAR is not written. -#define CPU_SCS_CFSR_IMPRECISERR 0x00000400 -#define CPU_SCS_CFSR_IMPRECISERR_BITN 10 -#define CPU_SCS_CFSR_IMPRECISERR_M 0x00000400 -#define CPU_SCS_CFSR_IMPRECISERR_S 10 +#define CPU_SCS_CFSR_IMPRECISERR 0x00000400 +#define CPU_SCS_CFSR_IMPRECISERR_BITN 10 +#define CPU_SCS_CFSR_IMPRECISERR_M 0x00000400 +#define CPU_SCS_CFSR_IMPRECISERR_S 10 // Field: [9] PRECISERR // // Precise data bus error return. -#define CPU_SCS_CFSR_PRECISERR 0x00000200 -#define CPU_SCS_CFSR_PRECISERR_BITN 9 -#define CPU_SCS_CFSR_PRECISERR_M 0x00000200 -#define CPU_SCS_CFSR_PRECISERR_S 9 +#define CPU_SCS_CFSR_PRECISERR 0x00000200 +#define CPU_SCS_CFSR_PRECISERR_BITN 9 +#define CPU_SCS_CFSR_PRECISERR_M 0x00000200 +#define CPU_SCS_CFSR_PRECISERR_S 9 // Field: [8] IBUSERR // // Instruction bus error flag. This flag is set by a prefetch error. The fault // stops on the instruction, so if the error occurs under a branch shadow, no // fault occurs. BFAR is not written. -#define CPU_SCS_CFSR_IBUSERR 0x00000100 -#define CPU_SCS_CFSR_IBUSERR_BITN 8 -#define CPU_SCS_CFSR_IBUSERR_M 0x00000100 -#define CPU_SCS_CFSR_IBUSERR_S 8 +#define CPU_SCS_CFSR_IBUSERR 0x00000100 +#define CPU_SCS_CFSR_IBUSERR_BITN 8 +#define CPU_SCS_CFSR_IBUSERR_M 0x00000100 +#define CPU_SCS_CFSR_IBUSERR_S 8 // Field: [7] MMARVALID // @@ -3204,20 +3204,20 @@ // fault occurs that is escalated to a Hard Fault because of priority, the Hard // Fault handler must clear this bit. This prevents problems on return to a // stacked active MemManage handler whose MMFAR value has been overwritten. -#define CPU_SCS_CFSR_MMARVALID 0x00000080 -#define CPU_SCS_CFSR_MMARVALID_BITN 7 -#define CPU_SCS_CFSR_MMARVALID_M 0x00000080 -#define CPU_SCS_CFSR_MMARVALID_S 7 +#define CPU_SCS_CFSR_MMARVALID 0x00000080 +#define CPU_SCS_CFSR_MMARVALID_BITN 7 +#define CPU_SCS_CFSR_MMARVALID_M 0x00000080 +#define CPU_SCS_CFSR_MMARVALID_S 7 // Field: [4] MSTKERR // // Stacking from exception has caused one or more access violations. The SP is // still adjusted and the values in the context area on the stack might be // incorrect. MMFAR is not written. -#define CPU_SCS_CFSR_MSTKERR 0x00000010 -#define CPU_SCS_CFSR_MSTKERR_BITN 4 -#define CPU_SCS_CFSR_MSTKERR_M 0x00000010 -#define CPU_SCS_CFSR_MSTKERR_S 4 +#define CPU_SCS_CFSR_MSTKERR 0x00000010 +#define CPU_SCS_CFSR_MSTKERR_BITN 4 +#define CPU_SCS_CFSR_MSTKERR_M 0x00000010 +#define CPU_SCS_CFSR_MSTKERR_S 4 // Field: [3] MUNSTKERR // @@ -3225,10 +3225,10 @@ // is chained to the handler, so that the original return stack is still // present. SP is not adjusted from failing return and new save is not // performed. MMFAR is not written. -#define CPU_SCS_CFSR_MUNSTKERR 0x00000008 -#define CPU_SCS_CFSR_MUNSTKERR_BITN 3 -#define CPU_SCS_CFSR_MUNSTKERR_M 0x00000008 -#define CPU_SCS_CFSR_MUNSTKERR_S 3 +#define CPU_SCS_CFSR_MUNSTKERR 0x00000008 +#define CPU_SCS_CFSR_MUNSTKERR_BITN 3 +#define CPU_SCS_CFSR_MUNSTKERR_M 0x00000008 +#define CPU_SCS_CFSR_MUNSTKERR_S 3 // Field: [1] DACCVIOL // @@ -3236,10 +3236,10 @@ // does not permit the operation sets this flag. The return PC points to the // faulting instruction. This error loads MMFAR with the address of the // attempted access. -#define CPU_SCS_CFSR_DACCVIOL 0x00000002 -#define CPU_SCS_CFSR_DACCVIOL_BITN 1 -#define CPU_SCS_CFSR_DACCVIOL_M 0x00000002 -#define CPU_SCS_CFSR_DACCVIOL_S 1 +#define CPU_SCS_CFSR_DACCVIOL 0x00000002 +#define CPU_SCS_CFSR_DACCVIOL_BITN 1 +#define CPU_SCS_CFSR_DACCVIOL_M 0x00000002 +#define CPU_SCS_CFSR_DACCVIOL_S 1 // Field: [0] IACCVIOL // @@ -3247,10 +3247,10 @@ // location that does not permit execution sets this flag. This occurs on any // access to an XN region, even when the MPU is disabled or not present. The // return PC points to the faulting instruction. MMFAR is not written. -#define CPU_SCS_CFSR_IACCVIOL 0x00000001 -#define CPU_SCS_CFSR_IACCVIOL_BITN 0 -#define CPU_SCS_CFSR_IACCVIOL_M 0x00000001 -#define CPU_SCS_CFSR_IACCVIOL_S 0 +#define CPU_SCS_CFSR_IACCVIOL 0x00000001 +#define CPU_SCS_CFSR_IACCVIOL_BITN 0 +#define CPU_SCS_CFSR_IACCVIOL_M 0x00000001 +#define CPU_SCS_CFSR_IACCVIOL_S 0 //***************************************************************************** // @@ -3265,10 +3265,10 @@ // both halting and monitor debug are disabled, it only happens for debug // events that are not ignored (minimally, BKPT). The Debug Fault Status // Register is updated. -#define CPU_SCS_HFSR_DEBUGEVT 0x80000000 -#define CPU_SCS_HFSR_DEBUGEVT_BITN 31 -#define CPU_SCS_HFSR_DEBUGEVT_M 0x80000000 -#define CPU_SCS_HFSR_DEBUGEVT_S 31 +#define CPU_SCS_HFSR_DEBUGEVT 0x80000000 +#define CPU_SCS_HFSR_DEBUGEVT_BITN 31 +#define CPU_SCS_HFSR_DEBUGEVT_M 0x80000000 +#define CPU_SCS_HFSR_DEBUGEVT_S 31 // Field: [30] FORCED // @@ -3276,20 +3276,20 @@ // activate because of priority or because the Configurable Fault is disabled. // The Hard Fault handler then has to read the other fault status registers to // determine cause. -#define CPU_SCS_HFSR_FORCED 0x40000000 -#define CPU_SCS_HFSR_FORCED_BITN 30 -#define CPU_SCS_HFSR_FORCED_M 0x40000000 -#define CPU_SCS_HFSR_FORCED_S 30 +#define CPU_SCS_HFSR_FORCED 0x40000000 +#define CPU_SCS_HFSR_FORCED_BITN 30 +#define CPU_SCS_HFSR_FORCED_M 0x40000000 +#define CPU_SCS_HFSR_FORCED_S 30 // Field: [1] VECTTBL // // This bit is set if there is a fault because of vector table read on // exception processing (Bus Fault). This case is always a Hard Fault. The // return PC points to the pre-empted instruction. -#define CPU_SCS_HFSR_VECTTBL 0x00000002 -#define CPU_SCS_HFSR_VECTTBL_BITN 1 -#define CPU_SCS_HFSR_VECTTBL_M 0x00000002 -#define CPU_SCS_HFSR_VECTTBL_S 1 +#define CPU_SCS_HFSR_VECTTBL 0x00000002 +#define CPU_SCS_HFSR_VECTTBL_BITN 1 +#define CPU_SCS_HFSR_VECTTBL_M 0x00000002 +#define CPU_SCS_HFSR_VECTTBL_S 1 //***************************************************************************** // @@ -3303,10 +3303,10 @@ // // 0x0: External debug request signal not asserted // 0x1: External debug request signal asserted -#define CPU_SCS_DFSR_EXTERNAL 0x00000010 -#define CPU_SCS_DFSR_EXTERNAL_BITN 4 -#define CPU_SCS_DFSR_EXTERNAL_M 0x00000010 -#define CPU_SCS_DFSR_EXTERNAL_S 4 +#define CPU_SCS_DFSR_EXTERNAL 0x00000010 +#define CPU_SCS_DFSR_EXTERNAL_BITN 4 +#define CPU_SCS_DFSR_EXTERNAL_M 0x00000010 +#define CPU_SCS_DFSR_EXTERNAL_S 4 // Field: [3] VCATCH // @@ -3315,10 +3315,10 @@ // // 0x0: No vector catch occurred // 0x1: Vector catch occurred -#define CPU_SCS_DFSR_VCATCH 0x00000008 -#define CPU_SCS_DFSR_VCATCH_BITN 3 -#define CPU_SCS_DFSR_VCATCH_M 0x00000008 -#define CPU_SCS_DFSR_VCATCH_S 3 +#define CPU_SCS_DFSR_VCATCH 0x00000008 +#define CPU_SCS_DFSR_VCATCH_BITN 3 +#define CPU_SCS_DFSR_VCATCH_M 0x00000008 +#define CPU_SCS_DFSR_VCATCH_S 3 // Field: [2] DWTTRAP // @@ -3327,10 +3327,10 @@ // // 0x0: No DWT match // 0x1: DWT match -#define CPU_SCS_DFSR_DWTTRAP 0x00000004 -#define CPU_SCS_DFSR_DWTTRAP_BITN 2 -#define CPU_SCS_DFSR_DWTTRAP_M 0x00000004 -#define CPU_SCS_DFSR_DWTTRAP_S 2 +#define CPU_SCS_DFSR_DWTTRAP 0x00000004 +#define CPU_SCS_DFSR_DWTTRAP_BITN 2 +#define CPU_SCS_DFSR_DWTTRAP_M 0x00000004 +#define CPU_SCS_DFSR_DWTTRAP_S 2 // Field: [1] BKPT // @@ -3340,10 +3340,10 @@ // // 0x0: No BKPT instruction execution // 0x1: BKPT instruction execution -#define CPU_SCS_DFSR_BKPT 0x00000002 -#define CPU_SCS_DFSR_BKPT_BITN 1 -#define CPU_SCS_DFSR_BKPT_M 0x00000002 -#define CPU_SCS_DFSR_BKPT_S 1 +#define CPU_SCS_DFSR_BKPT 0x00000002 +#define CPU_SCS_DFSR_BKPT_BITN 1 +#define CPU_SCS_DFSR_BKPT_M 0x00000002 +#define CPU_SCS_DFSR_BKPT_S 1 // Field: [0] HALTED // @@ -3351,10 +3351,10 @@ // // 0x0: No halt request // 0x1: Halt requested by NVIC, including step -#define CPU_SCS_DFSR_HALTED 0x00000001 -#define CPU_SCS_DFSR_HALTED_BITN 0 -#define CPU_SCS_DFSR_HALTED_M 0x00000001 -#define CPU_SCS_DFSR_HALTED_S 0 +#define CPU_SCS_DFSR_HALTED 0x00000001 +#define CPU_SCS_DFSR_HALTED_BITN 0 +#define CPU_SCS_DFSR_HALTED_M 0x00000001 +#define CPU_SCS_DFSR_HALTED_S 0 //***************************************************************************** // @@ -3370,9 +3370,9 @@ // address can be any offset in the range of the requested size. Flags // CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination // with CFSR.MMARVALIDindicate the cause of the fault. -#define CPU_SCS_MMFAR_ADDRESS_W 32 -#define CPU_SCS_MMFAR_ADDRESS_M 0xFFFFFFFF -#define CPU_SCS_MMFAR_ADDRESS_S 0 +#define CPU_SCS_MMFAR_ADDRESS_W 32 +#define CPU_SCS_MMFAR_ADDRESS_M 0xFFFFFFFF +#define CPU_SCS_MMFAR_ADDRESS_S 0 //***************************************************************************** // @@ -3387,9 +3387,9 @@ // Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and // CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the // fault. -#define CPU_SCS_BFAR_ADDRESS_W 32 -#define CPU_SCS_BFAR_ADDRESS_M 0xFFFFFFFF -#define CPU_SCS_BFAR_ADDRESS_S 0 +#define CPU_SCS_BFAR_ADDRESS_W 32 +#define CPU_SCS_BFAR_ADDRESS_M 0xFFFFFFFF +#define CPU_SCS_BFAR_ADDRESS_S 0 //***************************************************************************** // @@ -3400,9 +3400,9 @@ // // Implementation defined. The bits map directly onto the signal assignment to // the auxiliary fault inputs. Tied to 0 -#define CPU_SCS_AFSR_IMPDEF_W 32 -#define CPU_SCS_AFSR_IMPDEF_M 0xFFFFFFFF -#define CPU_SCS_AFSR_IMPDEF_S 0 +#define CPU_SCS_AFSR_IMPDEF_W 32 +#define CPU_SCS_AFSR_IMPDEF_M 0xFFFFFFFF +#define CPU_SCS_AFSR_IMPDEF_S 0 //***************************************************************************** // @@ -3420,9 +3420,9 @@ // instructions can be added using the appropriate instruction attribute, but // other 32-bit basic instructions cannot.) // 0x3: Thumb-2 encoding with all Thumb-2 basic instructions -#define CPU_SCS_ID_PFR0_STATE1_W 4 -#define CPU_SCS_ID_PFR0_STATE1_M 0x000000F0 -#define CPU_SCS_ID_PFR0_STATE1_S 4 +#define CPU_SCS_ID_PFR0_STATE1_W 4 +#define CPU_SCS_ID_PFR0_STATE1_M 0x000000F0 +#define CPU_SCS_ID_PFR0_STATE1_S 4 // Field: [3:0] STATE0 // @@ -3430,9 +3430,9 @@ // // 0x0: No ARM encoding // 0x1: N/A -#define CPU_SCS_ID_PFR0_STATE0_W 4 -#define CPU_SCS_ID_PFR0_STATE0_M 0x0000000F -#define CPU_SCS_ID_PFR0_STATE0_S 0 +#define CPU_SCS_ID_PFR0_STATE0_W 4 +#define CPU_SCS_ID_PFR0_STATE0_M 0x0000000F +#define CPU_SCS_ID_PFR0_STATE0_S 0 //***************************************************************************** // @@ -3445,9 +3445,9 @@ // // 0x0: Not supported // 0x2: Two-stack support -#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_W 4 -#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M 0x00000F00 -#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_S 8 +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_W 4 +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M 0x00000F00 +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_S 8 //***************************************************************************** // @@ -3460,9 +3460,9 @@ // // 0x0: Not supported // 0x1: Microcontroller debug v1 (ITMv1 and DWTv1) -#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_W 4 -#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_M 0x00F00000 -#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_S 20 +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_W 4 +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_M 0x00F00000 +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_S 20 //***************************************************************************** // @@ -3490,10 +3490,10 @@ // // 0x0: Not supported // 0x1: Wait for interrupt supported -#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING 0x01000000 -#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_BITN 24 -#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M 0x01000000 -#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_S 24 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING 0x01000000 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_BITN 24 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M 0x01000000 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_S 24 //***************************************************************************** // @@ -3544,10 +3544,10 @@ // reset still). // When writing to this register, 0 must be written this bit-field, otherwise // the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_RESET_ST 0x02000000 -#define CPU_SCS_DHCSR_S_RESET_ST_BITN 25 -#define CPU_SCS_DHCSR_S_RESET_ST_M 0x02000000 -#define CPU_SCS_DHCSR_S_RESET_ST_S 25 +#define CPU_SCS_DHCSR_S_RESET_ST 0x02000000 +#define CPU_SCS_DHCSR_S_RESET_ST_BITN 25 +#define CPU_SCS_DHCSR_S_RESET_ST_M 0x02000000 +#define CPU_SCS_DHCSR_S_RESET_ST_S 25 // Field: [24] S_RETIRE_ST // @@ -3556,10 +3556,10 @@ // load/store or fetch. // When writing to this register, 0 must be written this bit-field, otherwise // the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_RETIRE_ST 0x01000000 -#define CPU_SCS_DHCSR_S_RETIRE_ST_BITN 24 -#define CPU_SCS_DHCSR_S_RETIRE_ST_M 0x01000000 -#define CPU_SCS_DHCSR_S_RETIRE_ST_S 24 +#define CPU_SCS_DHCSR_S_RETIRE_ST 0x01000000 +#define CPU_SCS_DHCSR_S_RETIRE_ST_BITN 24 +#define CPU_SCS_DHCSR_S_RETIRE_ST_M 0x01000000 +#define CPU_SCS_DHCSR_S_RETIRE_ST_S 24 // Field: [19] S_LOCKUP // @@ -3567,10 +3567,10 @@ // present. // When writing to this register, 1 must be written this bit-field, otherwise // the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_LOCKUP 0x00080000 -#define CPU_SCS_DHCSR_S_LOCKUP_BITN 19 -#define CPU_SCS_DHCSR_S_LOCKUP_M 0x00080000 -#define CPU_SCS_DHCSR_S_LOCKUP_S 19 +#define CPU_SCS_DHCSR_S_LOCKUP 0x00080000 +#define CPU_SCS_DHCSR_S_LOCKUP_BITN 19 +#define CPU_SCS_DHCSR_S_LOCKUP_M 0x00080000 +#define CPU_SCS_DHCSR_S_LOCKUP_S 19 // Field: [18] S_SLEEP // @@ -3578,20 +3578,20 @@ // use C_HALT to gain control or wait for interrupt to wake-up. // When writing to this register, 1 must be written this bit-field, otherwise // the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_SLEEP 0x00040000 -#define CPU_SCS_DHCSR_S_SLEEP_BITN 18 -#define CPU_SCS_DHCSR_S_SLEEP_M 0x00040000 -#define CPU_SCS_DHCSR_S_SLEEP_S 18 +#define CPU_SCS_DHCSR_S_SLEEP 0x00040000 +#define CPU_SCS_DHCSR_S_SLEEP_BITN 18 +#define CPU_SCS_DHCSR_S_SLEEP_M 0x00040000 +#define CPU_SCS_DHCSR_S_SLEEP_S 18 // Field: [17] S_HALT // // The core is in debug state when this bit is set. // When writing to this register, 1 must be written this bit-field, otherwise // the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_HALT 0x00020000 -#define CPU_SCS_DHCSR_S_HALT_BITN 17 -#define CPU_SCS_DHCSR_S_HALT_M 0x00020000 -#define CPU_SCS_DHCSR_S_HALT_S 17 +#define CPU_SCS_DHCSR_S_HALT 0x00020000 +#define CPU_SCS_DHCSR_S_HALT_BITN 17 +#define CPU_SCS_DHCSR_S_HALT_M 0x00020000 +#define CPU_SCS_DHCSR_S_HALT_S 17 // Field: [16] S_REGRDY // @@ -3599,10 +3599,10 @@ // available. Last transfer is complete. // When writing to this register, 1 must be written this bit-field, otherwise // the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_REGRDY 0x00010000 -#define CPU_SCS_DHCSR_S_REGRDY_BITN 16 -#define CPU_SCS_DHCSR_S_REGRDY_M 0x00010000 -#define CPU_SCS_DHCSR_S_REGRDY_S 16 +#define CPU_SCS_DHCSR_S_REGRDY 0x00010000 +#define CPU_SCS_DHCSR_S_REGRDY_BITN 16 +#define CPU_SCS_DHCSR_S_REGRDY_M 0x00010000 +#define CPU_SCS_DHCSR_S_REGRDY_S 16 // Field: [5] C_SNAPSTALL // @@ -3612,10 +3612,10 @@ // The core reads S_RETIRE_ST as 0. This indicates that no instruction has // advanced. This prevents misuse. The bus state is Unpredictable when this is // used. S_RETIRE_ST can detect core stalls on load/store operations. -#define CPU_SCS_DHCSR_C_SNAPSTALL 0x00000020 -#define CPU_SCS_DHCSR_C_SNAPSTALL_BITN 5 -#define CPU_SCS_DHCSR_C_SNAPSTALL_M 0x00000020 -#define CPU_SCS_DHCSR_C_SNAPSTALL_S 5 +#define CPU_SCS_DHCSR_C_SNAPSTALL 0x00000020 +#define CPU_SCS_DHCSR_C_SNAPSTALL_BITN 5 +#define CPU_SCS_DHCSR_C_SNAPSTALL_M 0x00000020 +#define CPU_SCS_DHCSR_C_SNAPSTALL_S 5 // Field: [3] C_MASKINTS // @@ -3627,10 +3627,10 @@ // be separate). Modifying C_MASKINTS while the system is running with halting // debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable // behavior. -#define CPU_SCS_DHCSR_C_MASKINTS 0x00000008 -#define CPU_SCS_DHCSR_C_MASKINTS_BITN 3 -#define CPU_SCS_DHCSR_C_MASKINTS_M 0x00000008 -#define CPU_SCS_DHCSR_C_MASKINTS_S 3 +#define CPU_SCS_DHCSR_C_MASKINTS 0x00000008 +#define CPU_SCS_DHCSR_C_MASKINTS_BITN 3 +#define CPU_SCS_DHCSR_C_MASKINTS_M 0x00000008 +#define CPU_SCS_DHCSR_C_MASKINTS_S 3 // Field: [2] C_STEP // @@ -3638,19 +3638,19 @@ // Must only be modified when the processor is halted (S_HALT == 1). // Modifying C_STEP while the system is running with halting debug support // enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior. -#define CPU_SCS_DHCSR_C_STEP 0x00000004 -#define CPU_SCS_DHCSR_C_STEP_BITN 2 -#define CPU_SCS_DHCSR_C_STEP_M 0x00000004 -#define CPU_SCS_DHCSR_C_STEP_S 2 +#define CPU_SCS_DHCSR_C_STEP 0x00000004 +#define CPU_SCS_DHCSR_C_STEP_BITN 2 +#define CPU_SCS_DHCSR_C_STEP_M 0x00000004 +#define CPU_SCS_DHCSR_C_STEP_S 2 // Field: [1] C_HALT // // Halts the core. This bit is set automatically when the core Halts. For // example Breakpoint. This bit clears on core reset. -#define CPU_SCS_DHCSR_C_HALT 0x00000002 -#define CPU_SCS_DHCSR_C_HALT_BITN 1 -#define CPU_SCS_DHCSR_C_HALT_M 0x00000002 -#define CPU_SCS_DHCSR_C_HALT_S 1 +#define CPU_SCS_DHCSR_C_HALT 0x00000002 +#define CPU_SCS_DHCSR_C_HALT_BITN 1 +#define CPU_SCS_DHCSR_C_HALT_M 0x00000002 +#define CPU_SCS_DHCSR_C_HALT_S 1 // Field: [0] C_DEBUGEN // @@ -3660,10 +3660,10 @@ // The values of C_HALT, C_STEP and C_MASKINTS are ignored by hardware when // C_DEBUGEN = 0. The read values for C_HALT, C_STEP and C_MASKINTS fields will // be unknown to software when C_DEBUGEN = 0. -#define CPU_SCS_DHCSR_C_DEBUGEN 0x00000001 -#define CPU_SCS_DHCSR_C_DEBUGEN_BITN 0 -#define CPU_SCS_DHCSR_C_DEBUGEN_M 0x00000001 -#define CPU_SCS_DHCSR_C_DEBUGEN_S 0 +#define CPU_SCS_DHCSR_C_DEBUGEN 0x00000001 +#define CPU_SCS_DHCSR_C_DEBUGEN_BITN 0 +#define CPU_SCS_DHCSR_C_DEBUGEN_M 0x00000001 +#define CPU_SCS_DHCSR_C_DEBUGEN_S 0 //***************************************************************************** // @@ -3674,10 +3674,10 @@ // // 1: Write // 0: Read -#define CPU_SCS_DCRSR_REGWNR 0x00010000 -#define CPU_SCS_DCRSR_REGWNR_BITN 16 -#define CPU_SCS_DCRSR_REGWNR_M 0x00010000 -#define CPU_SCS_DCRSR_REGWNR_S 16 +#define CPU_SCS_DCRSR_REGWNR 0x00010000 +#define CPU_SCS_DCRSR_REGWNR_BITN 16 +#define CPU_SCS_DCRSR_REGWNR_M 0x00010000 +#define CPU_SCS_DCRSR_REGWNR_S 16 // Field: [4:0] REGSEL // @@ -3703,9 +3703,9 @@ // 0x11: MSP (Main SP) // 0x12: PSP (Process SP) // 0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 | PRIMASK -#define CPU_SCS_DCRSR_REGSEL_W 5 -#define CPU_SCS_DCRSR_REGSEL_M 0x0000001F -#define CPU_SCS_DCRSR_REGSEL_S 0 +#define CPU_SCS_DCRSR_REGSEL_W 5 +#define CPU_SCS_DCRSR_REGSEL_M 0x0000001F +#define CPU_SCS_DCRSR_REGSEL_S 0 //***************************************************************************** // @@ -3722,9 +3722,9 @@ // can use this register for communication in non-halting debug. This enables // flags and bits to acknowledge state and indicate if commands have been // accepted to, replied to, or accepted and replied to. -#define CPU_SCS_DCRDR_DCRDR_W 32 -#define CPU_SCS_DCRDR_DCRDR_M 0xFFFFFFFF -#define CPU_SCS_DCRDR_DCRDR_S 0 +#define CPU_SCS_DCRDR_DCRDR_W 32 +#define CPU_SCS_DCRDR_DCRDR_M 0xFFFFFFFF +#define CPU_SCS_DCRDR_DCRDR_S 0 //***************************************************************************** // @@ -3737,10 +3737,10 @@ // ITM, ETM and TPIU. This enables control of power usage unless tracing is // required. The application can enable this, for ITM use, or use by a // debugger. -#define CPU_SCS_DEMCR_TRCENA 0x01000000 -#define CPU_SCS_DEMCR_TRCENA_BITN 24 -#define CPU_SCS_DEMCR_TRCENA_M 0x01000000 -#define CPU_SCS_DEMCR_TRCENA_S 24 +#define CPU_SCS_DEMCR_TRCENA 0x01000000 +#define CPU_SCS_DEMCR_TRCENA_BITN 24 +#define CPU_SCS_DEMCR_TRCENA_M 0x01000000 +#define CPU_SCS_DEMCR_TRCENA_S 24 // Field: [19] MON_REQ // @@ -3749,10 +3749,10 @@ // // 0x0: Woken up by debug exception. // 0x1: Woken up by MON_PEND -#define CPU_SCS_DEMCR_MON_REQ 0x00080000 -#define CPU_SCS_DEMCR_MON_REQ_BITN 19 -#define CPU_SCS_DEMCR_MON_REQ_M 0x00080000 -#define CPU_SCS_DEMCR_MON_REQ_S 19 +#define CPU_SCS_DEMCR_MON_REQ 0x00080000 +#define CPU_SCS_DEMCR_MON_REQ_BITN 19 +#define CPU_SCS_DEMCR_MON_REQ_M 0x00080000 +#define CPU_SCS_DEMCR_MON_REQ_S 19 // Field: [18] MON_STEP // @@ -3760,10 +3760,10 @@ // This is the equivalent to DHCSR.C_STEP. Interrupts are only stepped // according to the priority of the monitor and settings of PRIMASK, FAULTMASK, // or BASEPRI. -#define CPU_SCS_DEMCR_MON_STEP 0x00040000 -#define CPU_SCS_DEMCR_MON_STEP_BITN 18 -#define CPU_SCS_DEMCR_MON_STEP_M 0x00040000 -#define CPU_SCS_DEMCR_MON_STEP_S 18 +#define CPU_SCS_DEMCR_MON_STEP 0x00040000 +#define CPU_SCS_DEMCR_MON_STEP_BITN 18 +#define CPU_SCS_DEMCR_MON_STEP_M 0x00040000 +#define CPU_SCS_DEMCR_MON_STEP_S 18 // Field: [17] MON_PEND // @@ -3772,10 +3772,10 @@ // Monitor debug. This register does not reset on a system reset. It is only // reset by a power-on reset. Software in the reset handler or later, or by the // DAP must enable the debug monitor. -#define CPU_SCS_DEMCR_MON_PEND 0x00020000 -#define CPU_SCS_DEMCR_MON_PEND_BITN 17 -#define CPU_SCS_DEMCR_MON_PEND_M 0x00020000 -#define CPU_SCS_DEMCR_MON_PEND_S 17 +#define CPU_SCS_DEMCR_MON_PEND 0x00020000 +#define CPU_SCS_DEMCR_MON_PEND_BITN 17 +#define CPU_SCS_DEMCR_MON_PEND_M 0x00020000 +#define CPU_SCS_DEMCR_MON_PEND_S 17 // Field: [16] MON_EN // @@ -3792,80 +3792,80 @@ // push. 2. If a late arriving interrupt comes in during vectoring, it is not // taken. That is, an implementation that supports the late arrival // optimization must suppress it in this case. -#define CPU_SCS_DEMCR_MON_EN 0x00010000 -#define CPU_SCS_DEMCR_MON_EN_BITN 16 -#define CPU_SCS_DEMCR_MON_EN_M 0x00010000 -#define CPU_SCS_DEMCR_MON_EN_S 16 +#define CPU_SCS_DEMCR_MON_EN 0x00010000 +#define CPU_SCS_DEMCR_MON_EN_BITN 16 +#define CPU_SCS_DEMCR_MON_EN_M 0x00010000 +#define CPU_SCS_DEMCR_MON_EN_S 16 // Field: [10] VC_HARDERR // // Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_HARDERR 0x00000400 -#define CPU_SCS_DEMCR_VC_HARDERR_BITN 10 -#define CPU_SCS_DEMCR_VC_HARDERR_M 0x00000400 -#define CPU_SCS_DEMCR_VC_HARDERR_S 10 +#define CPU_SCS_DEMCR_VC_HARDERR 0x00000400 +#define CPU_SCS_DEMCR_VC_HARDERR_BITN 10 +#define CPU_SCS_DEMCR_VC_HARDERR_M 0x00000400 +#define CPU_SCS_DEMCR_VC_HARDERR_S 10 // Field: [9] VC_INTERR // // Debug trap on a fault occurring during an exception entry or return // sequence. Ignored when DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_INTERR 0x00000200 -#define CPU_SCS_DEMCR_VC_INTERR_BITN 9 -#define CPU_SCS_DEMCR_VC_INTERR_M 0x00000200 -#define CPU_SCS_DEMCR_VC_INTERR_S 9 +#define CPU_SCS_DEMCR_VC_INTERR 0x00000200 +#define CPU_SCS_DEMCR_VC_INTERR_BITN 9 +#define CPU_SCS_DEMCR_VC_INTERR_M 0x00000200 +#define CPU_SCS_DEMCR_VC_INTERR_S 9 // Field: [8] VC_BUSERR // // Debug Trap on normal Bus error. Ignored when DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_BUSERR 0x00000100 -#define CPU_SCS_DEMCR_VC_BUSERR_BITN 8 -#define CPU_SCS_DEMCR_VC_BUSERR_M 0x00000100 -#define CPU_SCS_DEMCR_VC_BUSERR_S 8 +#define CPU_SCS_DEMCR_VC_BUSERR 0x00000100 +#define CPU_SCS_DEMCR_VC_BUSERR_BITN 8 +#define CPU_SCS_DEMCR_VC_BUSERR_M 0x00000100 +#define CPU_SCS_DEMCR_VC_BUSERR_S 8 // Field: [7] VC_STATERR // // Debug trap on Usage Fault state errors. Ignored when DHCSR.C_DEBUGEN is // cleared. -#define CPU_SCS_DEMCR_VC_STATERR 0x00000080 -#define CPU_SCS_DEMCR_VC_STATERR_BITN 7 -#define CPU_SCS_DEMCR_VC_STATERR_M 0x00000080 -#define CPU_SCS_DEMCR_VC_STATERR_S 7 +#define CPU_SCS_DEMCR_VC_STATERR 0x00000080 +#define CPU_SCS_DEMCR_VC_STATERR_BITN 7 +#define CPU_SCS_DEMCR_VC_STATERR_M 0x00000080 +#define CPU_SCS_DEMCR_VC_STATERR_S 7 // Field: [6] VC_CHKERR // // Debug trap on Usage Fault enabled checking errors. Ignored when // DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_CHKERR 0x00000040 -#define CPU_SCS_DEMCR_VC_CHKERR_BITN 6 -#define CPU_SCS_DEMCR_VC_CHKERR_M 0x00000040 -#define CPU_SCS_DEMCR_VC_CHKERR_S 6 +#define CPU_SCS_DEMCR_VC_CHKERR 0x00000040 +#define CPU_SCS_DEMCR_VC_CHKERR_BITN 6 +#define CPU_SCS_DEMCR_VC_CHKERR_M 0x00000040 +#define CPU_SCS_DEMCR_VC_CHKERR_S 6 // Field: [5] VC_NOCPERR // // Debug trap on a UsageFault access to a Coprocessor. Ignored when // DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_NOCPERR 0x00000020 -#define CPU_SCS_DEMCR_VC_NOCPERR_BITN 5 -#define CPU_SCS_DEMCR_VC_NOCPERR_M 0x00000020 -#define CPU_SCS_DEMCR_VC_NOCPERR_S 5 +#define CPU_SCS_DEMCR_VC_NOCPERR 0x00000020 +#define CPU_SCS_DEMCR_VC_NOCPERR_BITN 5 +#define CPU_SCS_DEMCR_VC_NOCPERR_M 0x00000020 +#define CPU_SCS_DEMCR_VC_NOCPERR_S 5 // Field: [4] VC_MMERR // // Debug trap on Memory Management faults. Ignored when DHCSR.C_DEBUGEN is // cleared. -#define CPU_SCS_DEMCR_VC_MMERR 0x00000010 -#define CPU_SCS_DEMCR_VC_MMERR_BITN 4 -#define CPU_SCS_DEMCR_VC_MMERR_M 0x00000010 -#define CPU_SCS_DEMCR_VC_MMERR_S 4 +#define CPU_SCS_DEMCR_VC_MMERR 0x00000010 +#define CPU_SCS_DEMCR_VC_MMERR_BITN 4 +#define CPU_SCS_DEMCR_VC_MMERR_M 0x00000010 +#define CPU_SCS_DEMCR_VC_MMERR_S 4 // Field: [0] VC_CORERESET // // Reset Vector Catch. Halt running system if Core reset occurs. Ignored when // DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_CORERESET 0x00000001 -#define CPU_SCS_DEMCR_VC_CORERESET_BITN 0 -#define CPU_SCS_DEMCR_VC_CORERESET_M 0x00000001 -#define CPU_SCS_DEMCR_VC_CORERESET_S 0 +#define CPU_SCS_DEMCR_VC_CORERESET 0x00000001 +#define CPU_SCS_DEMCR_VC_CORERESET_BITN 0 +#define CPU_SCS_DEMCR_VC_CORERESET_M 0x00000001 +#define CPU_SCS_DEMCR_VC_CORERESET_S 0 //***************************************************************************** // @@ -3877,9 +3877,8 @@ // Interrupt ID field. Writing a value to this bit-field is the same as // manually pending an interrupt by setting the corresponding interrupt bit in // an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1. -#define CPU_SCS_STIR_INTID_W 9 -#define CPU_SCS_STIR_INTID_M 0x000001FF -#define CPU_SCS_STIR_INTID_S 0 - +#define CPU_SCS_STIR_INTID_W 9 +#define CPU_SCS_STIR_INTID_M 0x000001FF +#define CPU_SCS_STIR_INTID_S 0 #endif // __CPU_SCS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_tiprop.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_tiprop.h index 3b011f7..c9be150 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_tiprop.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_tiprop.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_cpu_tiprop_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_cpu_tiprop_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CPU_TIPROP_H__ #define __HW_CPU_TIPROP_H__ @@ -44,10 +44,10 @@ // //***************************************************************************** // Internal -#define CPU_TIPROP_O_TRACECLKMUX 0x00000FF8 +#define CPU_TIPROP_O_TRACECLKMUX 0x00000FF8 // Internal -#define CPU_TIPROP_O_DYN_CG 0x00000FFC +#define CPU_TIPROP_O_DYN_CG 0x00000FFC //***************************************************************************** // @@ -60,12 +60,12 @@ // ENUMs: // TRACECLK Internal. Only to be used through TI provided API. // SWV Internal. Only to be used through TI provided API. -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV 0x00000001 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_BITN 0 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_M 0x00000001 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_S 0 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_TRACECLK 0x00000001 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_SWV 0x00000000 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_BITN 0 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_M 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_S 0 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_TRACECLK 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_SWV 0x00000000 //***************************************************************************** // @@ -75,9 +75,8 @@ // Field: [1:0] DYN_CG // // Internal. Only to be used through TI provided API. -#define CPU_TIPROP_DYN_CG_DYN_CG_W 2 -#define CPU_TIPROP_DYN_CG_DYN_CG_M 0x00000003 -#define CPU_TIPROP_DYN_CG_DYN_CG_S 0 - +#define CPU_TIPROP_DYN_CG_DYN_CG_W 2 +#define CPU_TIPROP_DYN_CG_DYN_CG_M 0x00000003 +#define CPU_TIPROP_DYN_CG_DYN_CG_S 0 #endif // __CPU_TIPROP__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_tpiu.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_tpiu.h index b91c2e8..ed9398b 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_tpiu.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_cpu_tpiu.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_cpu_tpiu_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_cpu_tpiu_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CPU_TPIU_H__ #define __HW_CPU_TPIU_H__ @@ -44,40 +44,40 @@ // //***************************************************************************** // Supported Sync Port Sizes -#define CPU_TPIU_O_SSPSR 0x00000000 +#define CPU_TPIU_O_SSPSR 0x00000000 // Current Sync Port Size -#define CPU_TPIU_O_CSPSR 0x00000004 +#define CPU_TPIU_O_CSPSR 0x00000004 // Async Clock Prescaler -#define CPU_TPIU_O_ACPR 0x00000010 +#define CPU_TPIU_O_ACPR 0x00000010 // Selected Pin Protocol -#define CPU_TPIU_O_SPPR 0x000000F0 +#define CPU_TPIU_O_SPPR 0x000000F0 // Formatter and Flush Status -#define CPU_TPIU_O_FFSR 0x00000300 +#define CPU_TPIU_O_FFSR 0x00000300 // Formatter and Flush Control -#define CPU_TPIU_O_FFCR 0x00000304 +#define CPU_TPIU_O_FFCR 0x00000304 // Formatter Synchronization Counter -#define CPU_TPIU_O_FSCR 0x00000308 +#define CPU_TPIU_O_FSCR 0x00000308 // Claim Tag Mask -#define CPU_TPIU_O_CLAIMMASK 0x00000FA0 +#define CPU_TPIU_O_CLAIMMASK 0x00000FA0 // Claim Tag Set -#define CPU_TPIU_O_CLAIMSET 0x00000FA0 +#define CPU_TPIU_O_CLAIMSET 0x00000FA0 // Current Claim Tag -#define CPU_TPIU_O_CLAIMTAG 0x00000FA4 +#define CPU_TPIU_O_CLAIMTAG 0x00000FA4 // Claim Tag Clear -#define CPU_TPIU_O_CLAIMCLR 0x00000FA4 +#define CPU_TPIU_O_CLAIMCLR 0x00000FA4 // Device ID -#define CPU_TPIU_O_DEVID 0x00000FC8 +#define CPU_TPIU_O_DEVID 0x00000FC8 //***************************************************************************** // @@ -90,10 +90,10 @@ // // 0x0: Not supported // 0x1: Supported -#define CPU_TPIU_SSPSR_FOUR 0x00000008 -#define CPU_TPIU_SSPSR_FOUR_BITN 3 -#define CPU_TPIU_SSPSR_FOUR_M 0x00000008 -#define CPU_TPIU_SSPSR_FOUR_S 3 +#define CPU_TPIU_SSPSR_FOUR 0x00000008 +#define CPU_TPIU_SSPSR_FOUR_BITN 3 +#define CPU_TPIU_SSPSR_FOUR_M 0x00000008 +#define CPU_TPIU_SSPSR_FOUR_S 3 // Field: [2] THREE // @@ -101,10 +101,10 @@ // // 0x0: Not supported // 0x1: Supported -#define CPU_TPIU_SSPSR_THREE 0x00000004 -#define CPU_TPIU_SSPSR_THREE_BITN 2 -#define CPU_TPIU_SSPSR_THREE_M 0x00000004 -#define CPU_TPIU_SSPSR_THREE_S 2 +#define CPU_TPIU_SSPSR_THREE 0x00000004 +#define CPU_TPIU_SSPSR_THREE_BITN 2 +#define CPU_TPIU_SSPSR_THREE_M 0x00000004 +#define CPU_TPIU_SSPSR_THREE_S 2 // Field: [1] TWO // @@ -112,10 +112,10 @@ // // 0x0: Not supported // 0x1: Supported -#define CPU_TPIU_SSPSR_TWO 0x00000002 -#define CPU_TPIU_SSPSR_TWO_BITN 1 -#define CPU_TPIU_SSPSR_TWO_M 0x00000002 -#define CPU_TPIU_SSPSR_TWO_S 1 +#define CPU_TPIU_SSPSR_TWO 0x00000002 +#define CPU_TPIU_SSPSR_TWO_BITN 1 +#define CPU_TPIU_SSPSR_TWO_M 0x00000002 +#define CPU_TPIU_SSPSR_TWO_S 1 // Field: [0] ONE // @@ -123,10 +123,10 @@ // // 0x0: Not supported // 0x1: Supported -#define CPU_TPIU_SSPSR_ONE 0x00000001 -#define CPU_TPIU_SSPSR_ONE_BITN 0 -#define CPU_TPIU_SSPSR_ONE_M 0x00000001 -#define CPU_TPIU_SSPSR_ONE_S 0 +#define CPU_TPIU_SSPSR_ONE 0x00000001 +#define CPU_TPIU_SSPSR_ONE_BITN 0 +#define CPU_TPIU_SSPSR_ONE_M 0x00000001 +#define CPU_TPIU_SSPSR_ONE_S 0 //***************************************************************************** // @@ -138,40 +138,40 @@ // 4-bit port enable // Writing values with more than one bit set in CSPSR, or setting a bit that is // not indicated as supported in SSPSR can cause Unpredictable behavior. -#define CPU_TPIU_CSPSR_FOUR 0x00000008 -#define CPU_TPIU_CSPSR_FOUR_BITN 3 -#define CPU_TPIU_CSPSR_FOUR_M 0x00000008 -#define CPU_TPIU_CSPSR_FOUR_S 3 +#define CPU_TPIU_CSPSR_FOUR 0x00000008 +#define CPU_TPIU_CSPSR_FOUR_BITN 3 +#define CPU_TPIU_CSPSR_FOUR_M 0x00000008 +#define CPU_TPIU_CSPSR_FOUR_S 3 // Field: [2] THREE // // 3-bit port enable // Writing values with more than one bit set in CSPSR, or setting a bit that is // not indicated as supported in SSPSR can cause Unpredictable behavior. -#define CPU_TPIU_CSPSR_THREE 0x00000004 -#define CPU_TPIU_CSPSR_THREE_BITN 2 -#define CPU_TPIU_CSPSR_THREE_M 0x00000004 -#define CPU_TPIU_CSPSR_THREE_S 2 +#define CPU_TPIU_CSPSR_THREE 0x00000004 +#define CPU_TPIU_CSPSR_THREE_BITN 2 +#define CPU_TPIU_CSPSR_THREE_M 0x00000004 +#define CPU_TPIU_CSPSR_THREE_S 2 // Field: [1] TWO // // 2-bit port enable // Writing values with more than one bit set in CSPSR, or setting a bit that is // not indicated as supported in SSPSR can cause Unpredictable behavior. -#define CPU_TPIU_CSPSR_TWO 0x00000002 -#define CPU_TPIU_CSPSR_TWO_BITN 1 -#define CPU_TPIU_CSPSR_TWO_M 0x00000002 -#define CPU_TPIU_CSPSR_TWO_S 1 +#define CPU_TPIU_CSPSR_TWO 0x00000002 +#define CPU_TPIU_CSPSR_TWO_BITN 1 +#define CPU_TPIU_CSPSR_TWO_M 0x00000002 +#define CPU_TPIU_CSPSR_TWO_S 1 // Field: [0] ONE // // 1-bit port enable // Writing values with more than one bit set in CSPSR, or setting a bit that is // not indicated as supported in SSPSR can cause Unpredictable behavior. -#define CPU_TPIU_CSPSR_ONE 0x00000001 -#define CPU_TPIU_CSPSR_ONE_BITN 0 -#define CPU_TPIU_CSPSR_ONE_M 0x00000001 -#define CPU_TPIU_CSPSR_ONE_S 0 +#define CPU_TPIU_CSPSR_ONE 0x00000001 +#define CPU_TPIU_CSPSR_ONE_BITN 0 +#define CPU_TPIU_CSPSR_ONE_M 0x00000001 +#define CPU_TPIU_CSPSR_ONE_S 0 //***************************************************************************** // @@ -181,9 +181,9 @@ // Field: [12:0] PRESCALER // // Divisor for input trace clock is (PRESCALER + 1). -#define CPU_TPIU_ACPR_PRESCALER_W 13 -#define CPU_TPIU_ACPR_PRESCALER_M 0x00001FFF -#define CPU_TPIU_ACPR_PRESCALER_S 0 +#define CPU_TPIU_ACPR_PRESCALER_W 13 +#define CPU_TPIU_ACPR_PRESCALER_M 0x00001FFF +#define CPU_TPIU_ACPR_PRESCALER_S 0 //***************************************************************************** // @@ -198,12 +198,12 @@ // SWO_MANCHESTER SerialWire Output (Manchester). This is the reset // value. // TRACEPORT TracePort mode -#define CPU_TPIU_SPPR_PROTOCOL_W 2 -#define CPU_TPIU_SPPR_PROTOCOL_M 0x00000003 -#define CPU_TPIU_SPPR_PROTOCOL_S 0 -#define CPU_TPIU_SPPR_PROTOCOL_SWO_NRZ 0x00000002 -#define CPU_TPIU_SPPR_PROTOCOL_SWO_MANCHESTER 0x00000001 -#define CPU_TPIU_SPPR_PROTOCOL_TRACEPORT 0x00000000 +#define CPU_TPIU_SPPR_PROTOCOL_W 2 +#define CPU_TPIU_SPPR_PROTOCOL_M 0x00000003 +#define CPU_TPIU_SPPR_PROTOCOL_S 0 +#define CPU_TPIU_SPPR_PROTOCOL_SWO_NRZ 0x00000002 +#define CPU_TPIU_SPPR_PROTOCOL_SWO_MANCHESTER 0x00000001 +#define CPU_TPIU_SPPR_PROTOCOL_TRACEPORT 0x00000000 //***************************************************************************** // @@ -214,10 +214,10 @@ // // 0: Formatter can be stopped // 1: Formatter cannot be stopped -#define CPU_TPIU_FFSR_FTNONSTOP 0x00000008 -#define CPU_TPIU_FFSR_FTNONSTOP_BITN 3 -#define CPU_TPIU_FFSR_FTNONSTOP_M 0x00000008 -#define CPU_TPIU_FFSR_FTNONSTOP_S 3 +#define CPU_TPIU_FFSR_FTNONSTOP 0x00000008 +#define CPU_TPIU_FFSR_FTNONSTOP_BITN 3 +#define CPU_TPIU_FFSR_FTNONSTOP_M 0x00000008 +#define CPU_TPIU_FFSR_FTNONSTOP_S 3 //***************************************************************************** // @@ -227,10 +227,10 @@ // Field: [8] TRIGIN // // Indicates that triggers are inserted when a trigger pin is asserted. -#define CPU_TPIU_FFCR_TRIGIN 0x00000100 -#define CPU_TPIU_FFCR_TRIGIN_BITN 8 -#define CPU_TPIU_FFCR_TRIGIN_M 0x00000100 -#define CPU_TPIU_FFCR_TRIGIN_S 8 +#define CPU_TPIU_FFCR_TRIGIN 0x00000100 +#define CPU_TPIU_FFCR_TRIGIN_BITN 8 +#define CPU_TPIU_FFCR_TRIGIN_M 0x00000100 +#define CPU_TPIU_FFCR_TRIGIN_S 8 // Field: [1] ENFCONT // @@ -238,10 +238,10 @@ // // 0: Continuous formatting disabled // 1: Continuous formatting enabled -#define CPU_TPIU_FFCR_ENFCONT 0x00000002 -#define CPU_TPIU_FFCR_ENFCONT_BITN 1 -#define CPU_TPIU_FFCR_ENFCONT_M 0x00000002 -#define CPU_TPIU_FFCR_ENFCONT_S 1 +#define CPU_TPIU_FFCR_ENFCONT 0x00000002 +#define CPU_TPIU_FFCR_ENFCONT_BITN 1 +#define CPU_TPIU_FFCR_ENFCONT_M 0x00000002 +#define CPU_TPIU_FFCR_ENFCONT_S 1 //***************************************************************************** // @@ -253,9 +253,9 @@ // The global synchronization trigger is generated by the Program Counter (PC) // Sampler block. This means that there is no synchronization counter in the // TPIU. -#define CPU_TPIU_FSCR_FSCR_W 32 -#define CPU_TPIU_FSCR_FSCR_M 0xFFFFFFFF -#define CPU_TPIU_FSCR_FSCR_S 0 +#define CPU_TPIU_FSCR_FSCR_W 32 +#define CPU_TPIU_FSCR_FSCR_M 0xFFFFFFFF +#define CPU_TPIU_FSCR_FSCR_S 0 //***************************************************************************** // @@ -272,9 +272,9 @@ // 1: This claim tag bit is not implemented // // The behavior when writing to this register is described in CLAIMSET. -#define CPU_TPIU_CLAIMMASK_CLAIMMASK_W 32 -#define CPU_TPIU_CLAIMMASK_CLAIMMASK_M 0xFFFFFFFF -#define CPU_TPIU_CLAIMMASK_CLAIMMASK_S 0 +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_W 32 +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_S 0 //***************************************************************************** // @@ -291,9 +291,9 @@ // 1: Set this bit in the claim tag // // The behavior when reading from this location is described in CLAIMMASK. -#define CPU_TPIU_CLAIMSET_CLAIMSET_W 32 -#define CPU_TPIU_CLAIMSET_CLAIMSET_M 0xFFFFFFFF -#define CPU_TPIU_CLAIMSET_CLAIMSET_S 0 +#define CPU_TPIU_CLAIMSET_CLAIMSET_W 32 +#define CPU_TPIU_CLAIMSET_CLAIMSET_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMSET_CLAIMSET_S 0 //***************************************************************************** // @@ -307,9 +307,9 @@ // Reading CLAIMMASK determines how many bits from this register must be used. // // The behavior when writing to this register is described in CLAIMCLR. -#define CPU_TPIU_CLAIMTAG_CLAIMTAG_W 32 -#define CPU_TPIU_CLAIMTAG_CLAIMTAG_M 0xFFFFFFFF -#define CPU_TPIU_CLAIMTAG_CLAIMTAG_S 0 +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_W 32 +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_S 0 //***************************************************************************** // @@ -326,9 +326,9 @@ // 1: Clear this bit in the claim tag. // // The behavior when reading from this location is described in CLAIMTAG. -#define CPU_TPIU_CLAIMCLR_CLAIMCLR_W 32 -#define CPU_TPIU_CLAIMCLR_CLAIMCLR_M 0xFFFFFFFF -#define CPU_TPIU_CLAIMCLR_CLAIMCLR_S 0 +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_W 32 +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_S 0 //***************************************************************************** // @@ -339,9 +339,8 @@ // // This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there is no // ETM present. -#define CPU_TPIU_DEVID_DEVID_W 32 -#define CPU_TPIU_DEVID_DEVID_M 0xFFFFFFFF -#define CPU_TPIU_DEVID_DEVID_S 0 - +#define CPU_TPIU_DEVID_DEVID_W 32 +#define CPU_TPIU_DEVID_DEVID_M 0xFFFFFFFF +#define CPU_TPIU_DEVID_DEVID_S 0 #endif // __CPU_TPIU__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_crypto.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_crypto.h index 80bc5fc..4693e95 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_crypto.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_crypto.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_crypto_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_crypto_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CRYPTO_H__ #define __HW_CRYPTO_H__ @@ -44,160 +44,160 @@ // //***************************************************************************** // DMA Channel 0 Control -#define CRYPTO_O_DMACH0CTL 0x00000000 +#define CRYPTO_O_DMACH0CTL 0x00000000 // DMA Channel 0 External Address -#define CRYPTO_O_DMACH0EXTADDR 0x00000004 +#define CRYPTO_O_DMACH0EXTADDR 0x00000004 // DMA Channel 0 Length -#define CRYPTO_O_DMACH0LEN 0x0000000C +#define CRYPTO_O_DMACH0LEN 0x0000000C // DMA Controller Status -#define CRYPTO_O_DMASTAT 0x00000018 +#define CRYPTO_O_DMASTAT 0x00000018 // DMA Controller Software Reset -#define CRYPTO_O_DMASWRESET 0x0000001C +#define CRYPTO_O_DMASWRESET 0x0000001C // DMA Channel 1 Control -#define CRYPTO_O_DMACH1CTL 0x00000020 +#define CRYPTO_O_DMACH1CTL 0x00000020 // DMA Channel 1 External Address -#define CRYPTO_O_DMACH1EXTADDR 0x00000024 +#define CRYPTO_O_DMACH1EXTADDR 0x00000024 // DMA Channel 1 Length -#define CRYPTO_O_DMACH1LEN 0x0000002C +#define CRYPTO_O_DMACH1LEN 0x0000002C // DMA Controller Master Configuration -#define CRYPTO_O_DMABUSCFG 0x00000078 +#define CRYPTO_O_DMABUSCFG 0x00000078 // DMA Controller Port Error -#define CRYPTO_O_DMAPORTERR 0x0000007C +#define CRYPTO_O_DMAPORTERR 0x0000007C // DMA Controller Version -#define CRYPTO_O_DMAHWVER 0x000000FC +#define CRYPTO_O_DMAHWVER 0x000000FC // Key Write Area -#define CRYPTO_O_KEYWRITEAREA 0x00000400 +#define CRYPTO_O_KEYWRITEAREA 0x00000400 // Key Written Area Status -#define CRYPTO_O_KEYWRITTENAREA 0x00000404 +#define CRYPTO_O_KEYWRITTENAREA 0x00000404 // Key Size -#define CRYPTO_O_KEYSIZE 0x00000408 +#define CRYPTO_O_KEYSIZE 0x00000408 // Key Read Area -#define CRYPTO_O_KEYREADAREA 0x0000040C +#define CRYPTO_O_KEYREADAREA 0x0000040C // Clear AES_KEY2/GHASH Key -#define CRYPTO_O_AESKEY20 0x00000500 +#define CRYPTO_O_AESKEY20 0x00000500 // Clear AES_KEY2/GHASH Key -#define CRYPTO_O_AESKEY21 0x00000504 +#define CRYPTO_O_AESKEY21 0x00000504 // Clear AES_KEY2/GHASH Key -#define CRYPTO_O_AESKEY22 0x00000508 +#define CRYPTO_O_AESKEY22 0x00000508 // Clear AES_KEY2/GHASH Key -#define CRYPTO_O_AESKEY23 0x0000050C +#define CRYPTO_O_AESKEY23 0x0000050C // Clear AES_KEY3 -#define CRYPTO_O_AESKEY30 0x00000510 +#define CRYPTO_O_AESKEY30 0x00000510 // Clear AES_KEY3 -#define CRYPTO_O_AESKEY31 0x00000514 +#define CRYPTO_O_AESKEY31 0x00000514 // Clear AES_KEY3 -#define CRYPTO_O_AESKEY32 0x00000518 +#define CRYPTO_O_AESKEY32 0x00000518 // Clear AES_KEY3 -#define CRYPTO_O_AESKEY33 0x0000051C +#define CRYPTO_O_AESKEY33 0x0000051C // AES Initialization Vector -#define CRYPTO_O_AESIV0 0x00000540 +#define CRYPTO_O_AESIV0 0x00000540 // AES Initialization Vector -#define CRYPTO_O_AESIV1 0x00000544 +#define CRYPTO_O_AESIV1 0x00000544 // AES Initialization Vector -#define CRYPTO_O_AESIV2 0x00000548 +#define CRYPTO_O_AESIV2 0x00000548 // AES Initialization Vector -#define CRYPTO_O_AESIV3 0x0000054C +#define CRYPTO_O_AESIV3 0x0000054C // AES Input/Output Buffer Control -#define CRYPTO_O_AESCTL 0x00000550 +#define CRYPTO_O_AESCTL 0x00000550 // Crypto Data Length LSW -#define CRYPTO_O_AESDATALEN0 0x00000554 +#define CRYPTO_O_AESDATALEN0 0x00000554 // Crypto Data Length MSW -#define CRYPTO_O_AESDATALEN1 0x00000558 +#define CRYPTO_O_AESDATALEN1 0x00000558 // AES Authentication Length -#define CRYPTO_O_AESAUTHLEN 0x0000055C +#define CRYPTO_O_AESAUTHLEN 0x0000055C // Data Input/Output -#define CRYPTO_O_AESDATAOUT0 0x00000560 +#define CRYPTO_O_AESDATAOUT0 0x00000560 // AES Data Input/Output 0 -#define CRYPTO_O_AESDATAIN0 0x00000560 +#define CRYPTO_O_AESDATAIN0 0x00000560 // AES Data Input/Output 3 -#define CRYPTO_O_AESDATAOUT1 0x00000564 +#define CRYPTO_O_AESDATAOUT1 0x00000564 // AES Data Input/Output 1 -#define CRYPTO_O_AESDATAIN1 0x00000564 +#define CRYPTO_O_AESDATAIN1 0x00000564 // AES Data Input/Output 2 -#define CRYPTO_O_AESDATAOUT2 0x00000568 +#define CRYPTO_O_AESDATAOUT2 0x00000568 // AES Data Input/Output 2 -#define CRYPTO_O_AESDATAIN2 0x00000568 +#define CRYPTO_O_AESDATAIN2 0x00000568 // AES Data Input/Output 3 -#define CRYPTO_O_AESDATAOUT3 0x0000056C +#define CRYPTO_O_AESDATAOUT3 0x0000056C // Data Input/Output -#define CRYPTO_O_AESDATAIN3 0x0000056C +#define CRYPTO_O_AESDATAIN3 0x0000056C // AES Tag Output -#define CRYPTO_O_AESTAGOUT0 0x00000570 +#define CRYPTO_O_AESTAGOUT0 0x00000570 // AES Tag Output -#define CRYPTO_O_AESTAGOUT1 0x00000574 +#define CRYPTO_O_AESTAGOUT1 0x00000574 // AES Tag Output -#define CRYPTO_O_AESTAGOUT2 0x00000578 +#define CRYPTO_O_AESTAGOUT2 0x00000578 // AES Tag Output -#define CRYPTO_O_AESTAGOUT3 0x0000057C +#define CRYPTO_O_AESTAGOUT3 0x0000057C // Master Algorithm Select -#define CRYPTO_O_ALGSEL 0x00000700 +#define CRYPTO_O_ALGSEL 0x00000700 // Master Protection Control -#define CRYPTO_O_DMAPROTCTL 0x00000704 +#define CRYPTO_O_DMAPROTCTL 0x00000704 // Software Reset -#define CRYPTO_O_SWRESET 0x00000740 +#define CRYPTO_O_SWRESET 0x00000740 // Control Interrupt Configuration -#define CRYPTO_O_IRQTYPE 0x00000780 +#define CRYPTO_O_IRQTYPE 0x00000780 // Interrupt Enable -#define CRYPTO_O_IRQEN 0x00000784 +#define CRYPTO_O_IRQEN 0x00000784 // Interrupt Clear -#define CRYPTO_O_IRQCLR 0x00000788 +#define CRYPTO_O_IRQCLR 0x00000788 // Interrupt Set -#define CRYPTO_O_IRQSET 0x0000078C +#define CRYPTO_O_IRQSET 0x0000078C // Interrupt Status -#define CRYPTO_O_IRQSTAT 0x00000790 +#define CRYPTO_O_IRQSTAT 0x00000790 // CTRL Module Version -#define CRYPTO_O_HWVER 0x000007FC +#define CRYPTO_O_HWVER 0x000007FC //***************************************************************************** // @@ -215,12 +215,12 @@ // ENUMs: // HIGH Priority high // LOW Priority low -#define CRYPTO_DMACH0CTL_PRIO 0x00000002 -#define CRYPTO_DMACH0CTL_PRIO_BITN 1 -#define CRYPTO_DMACH0CTL_PRIO_M 0x00000002 -#define CRYPTO_DMACH0CTL_PRIO_S 1 -#define CRYPTO_DMACH0CTL_PRIO_HIGH 0x00000002 -#define CRYPTO_DMACH0CTL_PRIO_LOW 0x00000000 +#define CRYPTO_DMACH0CTL_PRIO 0x00000002 +#define CRYPTO_DMACH0CTL_PRIO_BITN 1 +#define CRYPTO_DMACH0CTL_PRIO_M 0x00000002 +#define CRYPTO_DMACH0CTL_PRIO_S 1 +#define CRYPTO_DMACH0CTL_PRIO_HIGH 0x00000002 +#define CRYPTO_DMACH0CTL_PRIO_LOW 0x00000000 // Field: [0] EN // @@ -228,12 +228,12 @@ // ENUMs: // EN Channel enabled // DIS Channel disabled -#define CRYPTO_DMACH0CTL_EN 0x00000001 -#define CRYPTO_DMACH0CTL_EN_BITN 0 -#define CRYPTO_DMACH0CTL_EN_M 0x00000001 -#define CRYPTO_DMACH0CTL_EN_S 0 -#define CRYPTO_DMACH0CTL_EN_EN 0x00000001 -#define CRYPTO_DMACH0CTL_EN_DIS 0x00000000 +#define CRYPTO_DMACH0CTL_EN 0x00000001 +#define CRYPTO_DMACH0CTL_EN_BITN 0 +#define CRYPTO_DMACH0CTL_EN_M 0x00000001 +#define CRYPTO_DMACH0CTL_EN_S 0 +#define CRYPTO_DMACH0CTL_EN_EN 0x00000001 +#define CRYPTO_DMACH0CTL_EN_DIS 0x00000000 //***************************************************************************** // @@ -245,9 +245,9 @@ // Channel external address value. // Holds the last updated external address after being sent to the master // interface. -#define CRYPTO_DMACH0EXTADDR_ADDR_W 32 -#define CRYPTO_DMACH0EXTADDR_ADDR_M 0xFFFFFFFF -#define CRYPTO_DMACH0EXTADDR_ADDR_S 0 +#define CRYPTO_DMACH0EXTADDR_ADDR_W 32 +#define CRYPTO_DMACH0EXTADDR_ADDR_M 0xFFFFFFFF +#define CRYPTO_DMACH0EXTADDR_ADDR_S 0 //***************************************************************************** // @@ -262,9 +262,9 @@ // transfer length after being sent to the master interface. // Note: Writing a non-zero value to this register field starts the transfer if // the channel is enabled by setting DMACH0CTL.EN. -#define CRYPTO_DMACH0LEN_LEN_W 16 -#define CRYPTO_DMACH0LEN_LEN_M 0x0000FFFF -#define CRYPTO_DMACH0LEN_LEN_S 0 +#define CRYPTO_DMACH0LEN_LEN_W 16 +#define CRYPTO_DMACH0LEN_LEN_M 0x0000FFFF +#define CRYPTO_DMACH0LEN_LEN_S 0 //***************************************************************************** // @@ -274,30 +274,30 @@ // Field: [17] PORT_ERR // // Reflects possible transfer errors on the AHB port. -#define CRYPTO_DMASTAT_PORT_ERR 0x00020000 -#define CRYPTO_DMASTAT_PORT_ERR_BITN 17 -#define CRYPTO_DMASTAT_PORT_ERR_M 0x00020000 -#define CRYPTO_DMASTAT_PORT_ERR_S 17 +#define CRYPTO_DMASTAT_PORT_ERR 0x00020000 +#define CRYPTO_DMASTAT_PORT_ERR_BITN 17 +#define CRYPTO_DMASTAT_PORT_ERR_M 0x00020000 +#define CRYPTO_DMASTAT_PORT_ERR_S 17 // Field: [1] CH1_ACTIVE // // This register field indicates if DMA channel 1 is active or not. // 0: Not active // 1: Active -#define CRYPTO_DMASTAT_CH1_ACTIVE 0x00000002 -#define CRYPTO_DMASTAT_CH1_ACTIVE_BITN 1 -#define CRYPTO_DMASTAT_CH1_ACTIVE_M 0x00000002 -#define CRYPTO_DMASTAT_CH1_ACTIVE_S 1 +#define CRYPTO_DMASTAT_CH1_ACTIVE 0x00000002 +#define CRYPTO_DMASTAT_CH1_ACTIVE_BITN 1 +#define CRYPTO_DMASTAT_CH1_ACTIVE_M 0x00000002 +#define CRYPTO_DMASTAT_CH1_ACTIVE_S 1 // Field: [0] CH0_ACTIVE // // This register field indicates if DMA channel 0 is active or not. // 0: Not active // 1: Active -#define CRYPTO_DMASTAT_CH0_ACTIVE 0x00000001 -#define CRYPTO_DMASTAT_CH0_ACTIVE_BITN 0 -#define CRYPTO_DMASTAT_CH0_ACTIVE_M 0x00000001 -#define CRYPTO_DMASTAT_CH0_ACTIVE_S 0 +#define CRYPTO_DMASTAT_CH0_ACTIVE 0x00000001 +#define CRYPTO_DMASTAT_CH0_ACTIVE_BITN 0 +#define CRYPTO_DMASTAT_CH0_ACTIVE_M 0x00000001 +#define CRYPTO_DMASTAT_CH0_ACTIVE_S 0 //***************************************************************************** // @@ -313,10 +313,10 @@ // // Note: Completion of the software reset must be checked in DMASTAT.CH0_ACTIVE // and DMASTAT.CH1_ACTIVE. -#define CRYPTO_DMASWRESET_RESET 0x00000001 -#define CRYPTO_DMASWRESET_RESET_BITN 0 -#define CRYPTO_DMASWRESET_RESET_M 0x00000001 -#define CRYPTO_DMASWRESET_RESET_S 0 +#define CRYPTO_DMASWRESET_RESET 0x00000001 +#define CRYPTO_DMASWRESET_RESET_BITN 0 +#define CRYPTO_DMASWRESET_RESET_M 0x00000001 +#define CRYPTO_DMASWRESET_RESET_S 0 //***************************************************************************** // @@ -334,12 +334,12 @@ // ENUMs: // HIGH Priority high // LOW Priority low -#define CRYPTO_DMACH1CTL_PRIO 0x00000002 -#define CRYPTO_DMACH1CTL_PRIO_BITN 1 -#define CRYPTO_DMACH1CTL_PRIO_M 0x00000002 -#define CRYPTO_DMACH1CTL_PRIO_S 1 -#define CRYPTO_DMACH1CTL_PRIO_HIGH 0x00000002 -#define CRYPTO_DMACH1CTL_PRIO_LOW 0x00000000 +#define CRYPTO_DMACH1CTL_PRIO 0x00000002 +#define CRYPTO_DMACH1CTL_PRIO_BITN 1 +#define CRYPTO_DMACH1CTL_PRIO_M 0x00000002 +#define CRYPTO_DMACH1CTL_PRIO_S 1 +#define CRYPTO_DMACH1CTL_PRIO_HIGH 0x00000002 +#define CRYPTO_DMACH1CTL_PRIO_LOW 0x00000000 // Field: [0] EN // @@ -351,12 +351,12 @@ // ENUMs: // EN Channel enabled // DIS Channel disabled -#define CRYPTO_DMACH1CTL_EN 0x00000001 -#define CRYPTO_DMACH1CTL_EN_BITN 0 -#define CRYPTO_DMACH1CTL_EN_M 0x00000001 -#define CRYPTO_DMACH1CTL_EN_S 0 -#define CRYPTO_DMACH1CTL_EN_EN 0x00000001 -#define CRYPTO_DMACH1CTL_EN_DIS 0x00000000 +#define CRYPTO_DMACH1CTL_EN 0x00000001 +#define CRYPTO_DMACH1CTL_EN_BITN 0 +#define CRYPTO_DMACH1CTL_EN_M 0x00000001 +#define CRYPTO_DMACH1CTL_EN_S 0 +#define CRYPTO_DMACH1CTL_EN_EN 0x00000001 +#define CRYPTO_DMACH1CTL_EN_DIS 0x00000000 //***************************************************************************** // @@ -368,9 +368,9 @@ // Channel external address value. // Holds the last updated external address after being sent to the master // interface. -#define CRYPTO_DMACH1EXTADDR_ADDR_W 32 -#define CRYPTO_DMACH1EXTADDR_ADDR_M 0xFFFFFFFF -#define CRYPTO_DMACH1EXTADDR_ADDR_S 0 +#define CRYPTO_DMACH1EXTADDR_ADDR_W 32 +#define CRYPTO_DMACH1EXTADDR_ADDR_M 0xFFFFFFFF +#define CRYPTO_DMACH1EXTADDR_ADDR_S 0 //***************************************************************************** // @@ -385,9 +385,9 @@ // transfer length after being sent to the master interface. // Note: Writing a non-zero value to this register field starts the transfer if // the channel is enabled by setting DMACH1CTL.EN. -#define CRYPTO_DMACH1LEN_LEN_W 16 -#define CRYPTO_DMACH1LEN_LEN_M 0x0000FFFF -#define CRYPTO_DMACH1LEN_LEN_S 0 +#define CRYPTO_DMACH1LEN_LEN_W 16 +#define CRYPTO_DMACH1LEN_LEN_M 0x0000FFFF +#define CRYPTO_DMACH1LEN_LEN_S 0 //***************************************************************************** // @@ -403,14 +403,14 @@ // 16_BYTE 16 bytes // 8_BYTE 8 bytes // 4_BYTE 4 bytes -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_W 4 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_M 0x0000F000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_S 12 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_64_BYTE 0x00006000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_32_BYTE 0x00005000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_16_BYTE 0x00004000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_8_BYTE 0x00003000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_4_BYTE 0x00002000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_W 4 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_M 0x0000F000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_S 12 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_64_BYTE 0x00006000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_32_BYTE 0x00005000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_16_BYTE 0x00004000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_8_BYTE 0x00003000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_4_BYTE 0x00002000 // Field: [11] AHB_MST1_IDLE_EN // @@ -418,12 +418,12 @@ // ENUMs: // IDLE Idle transfer insertion enabled // NO_IDLE Do not insert idle transfers. -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN 0x00000800 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_BITN 11 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_M 0x00000800 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_S 11 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_IDLE 0x00000800 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_NO_IDLE 0x00000000 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_BITN 11 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_M 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_S 11 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_IDLE 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_NO_IDLE 0x00000000 // Field: [10] AHB_MST1_INCR_EN // @@ -431,12 +431,12 @@ // ENUMs: // SPECIFIED Fixed length bursts or single transfers // UNSPECIFIED Unspecified length burst transfers -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN 0x00000400 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_BITN 10 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_M 0x00000400 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_S 10 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_SPECIFIED 0x00000400 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_UNSPECIFIED 0x00000000 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_BITN 10 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_M 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_S 10 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_SPECIFIED 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_UNSPECIFIED 0x00000000 // Field: [9] AHB_MST1_LOCK_EN // @@ -444,12 +444,12 @@ // ENUMs: // LOCKED Transfers are locked // NOT_LOCKED Transfers are not locked -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN 0x00000200 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_BITN 9 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_M 0x00000200 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_S 9 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_LOCKED 0x00000200 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_NOT_LOCKED 0x00000000 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_BITN 9 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_M 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_S 9 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_LOCKED 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_NOT_LOCKED 0x00000000 // Field: [8] AHB_MST1_BIGEND // @@ -457,12 +457,12 @@ // ENUMs: // BIG_ENDIAN Big Endian // LITTLE_ENDIAN Little Endian -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND 0x00000100 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BITN 8 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_M 0x00000100 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_S 8 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BIG_ENDIAN 0x00000100 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_LITTLE_ENDIAN 0x00000000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BITN 8 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_M 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_S 8 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BIG_ENDIAN 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_LITTLE_ENDIAN 0x00000000 //***************************************************************************** // @@ -472,19 +472,19 @@ // Field: [12] AHB_ERR // // A 1 indicates that the Crypto peripheral has detected an AHB bus error -#define CRYPTO_DMAPORTERR_AHB_ERR 0x00001000 -#define CRYPTO_DMAPORTERR_AHB_ERR_BITN 12 -#define CRYPTO_DMAPORTERR_AHB_ERR_M 0x00001000 -#define CRYPTO_DMAPORTERR_AHB_ERR_S 12 +#define CRYPTO_DMAPORTERR_AHB_ERR 0x00001000 +#define CRYPTO_DMAPORTERR_AHB_ERR_BITN 12 +#define CRYPTO_DMAPORTERR_AHB_ERR_M 0x00001000 +#define CRYPTO_DMAPORTERR_AHB_ERR_S 12 // Field: [9] LAST_CH // // Indicates which channel was serviced last (channel 0 or channel 1) by the // AHB master port. -#define CRYPTO_DMAPORTERR_LAST_CH 0x00000200 -#define CRYPTO_DMAPORTERR_LAST_CH_BITN 9 -#define CRYPTO_DMAPORTERR_LAST_CH_M 0x00000200 -#define CRYPTO_DMAPORTERR_LAST_CH_S 9 +#define CRYPTO_DMAPORTERR_LAST_CH 0x00000200 +#define CRYPTO_DMAPORTERR_LAST_CH_BITN 9 +#define CRYPTO_DMAPORTERR_LAST_CH_M 0x00000200 +#define CRYPTO_DMAPORTERR_LAST_CH_S 9 //***************************************************************************** // @@ -494,37 +494,37 @@ // Field: [27:24] HW_MAJOR_VER // // Major version number -#define CRYPTO_DMAHWVER_HW_MAJOR_VER_W 4 -#define CRYPTO_DMAHWVER_HW_MAJOR_VER_M 0x0F000000 -#define CRYPTO_DMAHWVER_HW_MAJOR_VER_S 24 +#define CRYPTO_DMAHWVER_HW_MAJOR_VER_W 4 +#define CRYPTO_DMAHWVER_HW_MAJOR_VER_M 0x0F000000 +#define CRYPTO_DMAHWVER_HW_MAJOR_VER_S 24 // Field: [23:20] HW_MINOR_VER // // Minor version number -#define CRYPTO_DMAHWVER_HW_MINOR_VER_W 4 -#define CRYPTO_DMAHWVER_HW_MINOR_VER_M 0x00F00000 -#define CRYPTO_DMAHWVER_HW_MINOR_VER_S 20 +#define CRYPTO_DMAHWVER_HW_MINOR_VER_W 4 +#define CRYPTO_DMAHWVER_HW_MINOR_VER_M 0x00F00000 +#define CRYPTO_DMAHWVER_HW_MINOR_VER_S 20 // Field: [19:16] HW_PATCH_LVL // // Patch level. -#define CRYPTO_DMAHWVER_HW_PATCH_LVL_W 4 -#define CRYPTO_DMAHWVER_HW_PATCH_LVL_M 0x000F0000 -#define CRYPTO_DMAHWVER_HW_PATCH_LVL_S 16 +#define CRYPTO_DMAHWVER_HW_PATCH_LVL_W 4 +#define CRYPTO_DMAHWVER_HW_PATCH_LVL_M 0x000F0000 +#define CRYPTO_DMAHWVER_HW_PATCH_LVL_S 16 // Field: [15:8] VER_NUM_COMPL // // Bit-by-bit complement of the VER_NUM field bits. -#define CRYPTO_DMAHWVER_VER_NUM_COMPL_W 8 -#define CRYPTO_DMAHWVER_VER_NUM_COMPL_M 0x0000FF00 -#define CRYPTO_DMAHWVER_VER_NUM_COMPL_S 8 +#define CRYPTO_DMAHWVER_VER_NUM_COMPL_W 8 +#define CRYPTO_DMAHWVER_VER_NUM_COMPL_M 0x0000FF00 +#define CRYPTO_DMAHWVER_VER_NUM_COMPL_S 8 // Field: [7:0] VER_NUM // // Version number of the DMA Controller (209) -#define CRYPTO_DMAHWVER_VER_NUM_W 8 -#define CRYPTO_DMAHWVER_VER_NUM_M 0x000000FF -#define CRYPTO_DMAHWVER_VER_NUM_S 0 +#define CRYPTO_DMAHWVER_VER_NUM_W 8 +#define CRYPTO_DMAHWVER_VER_NUM_M 0x000000FF +#define CRYPTO_DMAHWVER_VER_NUM_S 0 //***************************************************************************** // @@ -541,12 +541,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA7 0x00000080 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_BITN 7 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_M 0x00000080 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_S 7 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_SEL 0x00000080 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_BITN 7 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_M 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_S 7 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_SEL 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_NOT_SEL 0x00000000 // Field: [6] RAM_AREA6 // @@ -558,12 +558,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA6 0x00000040 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_BITN 6 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_M 0x00000040 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_S 6 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_SEL 0x00000040 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_BITN 6 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_M 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_S 6 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_SEL 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_NOT_SEL 0x00000000 // Field: [5] RAM_AREA5 // @@ -575,12 +575,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA5 0x00000020 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_BITN 5 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_M 0x00000020 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_S 5 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_SEL 0x00000020 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_BITN 5 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_M 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_S 5 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_SEL 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_NOT_SEL 0x00000000 // Field: [4] RAM_AREA4 // @@ -592,12 +592,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA4 0x00000010 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_BITN 4 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_M 0x00000010 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_S 4 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_SEL 0x00000010 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_BITN 4 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_M 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_S 4 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_SEL 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_NOT_SEL 0x00000000 // Field: [3] RAM_AREA3 // @@ -609,12 +609,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA3 0x00000008 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_BITN 3 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_M 0x00000008 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_S 3 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_SEL 0x00000008 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_BITN 3 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_M 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_S 3 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_SEL 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_NOT_SEL 0x00000000 // Field: [2] RAM_AREA2 // @@ -626,12 +626,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA2 0x00000004 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_BITN 2 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_M 0x00000004 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_S 2 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_SEL 0x00000004 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_BITN 2 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_M 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_S 2 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_SEL 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_NOT_SEL 0x00000000 // Field: [1] RAM_AREA1 // @@ -643,12 +643,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA1 0x00000002 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_BITN 1 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_M 0x00000002 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_S 1 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_SEL 0x00000002 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_BITN 1 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_M 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_S 1 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_SEL 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_NOT_SEL 0x00000000 // Field: [0] RAM_AREA0 // @@ -660,12 +660,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA0 0x00000001 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_BITN 0 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_M 0x00000001 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_S 0 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_SEL 0x00000001 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_BITN 0 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_M 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_S 0 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_SEL 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_NOT_SEL 0x00000000 //***************************************************************************** // @@ -686,12 +686,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7 0x00000080 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_BITN 7 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_M 0x00000080 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_S 7 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_WRITTEN 0x00000080 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_BITN 7 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_M 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_S 7 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_WRITTEN 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_NOT_WRITTEN 0x00000000 // Field: [6] RAM_AREA_WRITTEN6 // @@ -707,12 +707,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6 0x00000040 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_BITN 6 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_M 0x00000040 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_S 6 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_WRITTEN 0x00000040 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_BITN 6 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_M 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_S 6 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_WRITTEN 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_NOT_WRITTEN 0x00000000 // Field: [5] RAM_AREA_WRITTEN5 // @@ -728,12 +728,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5 0x00000020 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_BITN 5 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_M 0x00000020 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_S 5 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_WRITTEN 0x00000020 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_BITN 5 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_M 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_S 5 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_WRITTEN 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_NOT_WRITTEN 0x00000000 // Field: [4] RAM_AREA_WRITTEN4 // @@ -749,12 +749,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4 0x00000010 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_BITN 4 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_M 0x00000010 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_S 4 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_WRITTEN 0x00000010 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_BITN 4 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_M 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_S 4 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_WRITTEN 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_NOT_WRITTEN 0x00000000 // Field: [3] RAM_AREA_WRITTEN3 // @@ -770,12 +770,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3 0x00000008 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_BITN 3 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_M 0x00000008 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_S 3 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_WRITTEN 0x00000008 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_BITN 3 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_M 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_S 3 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_WRITTEN 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_NOT_WRITTEN 0x00000000 // Field: [2] RAM_AREA_WRITTEN2 // @@ -791,12 +791,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2 0x00000004 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_BITN 2 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_M 0x00000004 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_S 2 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_WRITTEN 0x00000004 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_BITN 2 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_M 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_S 2 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_WRITTEN 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_NOT_WRITTEN 0x00000000 // Field: [1] RAM_AREA_WRITTEN1 // @@ -812,12 +812,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1 0x00000002 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_BITN 1 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_M 0x00000002 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_S 1 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_WRITTEN 0x00000002 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_BITN 1 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_M 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_S 1 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_WRITTEN 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_NOT_WRITTEN 0x00000000 // Field: [0] RAM_AREA_WRITTEN0 // @@ -834,12 +834,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0 0x00000001 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_BITN 0 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_M 0x00000001 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_S 0 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_WRITTEN 0x00000001 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0 0x00000001 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_BITN 0 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_M 0x00000001 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_S 0 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_WRITTEN 0x00000001 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_NOT_WRITTEN 0x00000000 //***************************************************************************** // @@ -859,12 +859,12 @@ // 256_BIT Not supported // 192_BIT Not supported // 128_BIT 128 bits -#define CRYPTO_KEYSIZE_SIZE_W 2 -#define CRYPTO_KEYSIZE_SIZE_M 0x00000003 -#define CRYPTO_KEYSIZE_SIZE_S 0 -#define CRYPTO_KEYSIZE_SIZE_256_BIT 0x00000003 -#define CRYPTO_KEYSIZE_SIZE_192_BIT 0x00000002 -#define CRYPTO_KEYSIZE_SIZE_128_BIT 0x00000001 +#define CRYPTO_KEYSIZE_SIZE_W 2 +#define CRYPTO_KEYSIZE_SIZE_M 0x00000003 +#define CRYPTO_KEYSIZE_SIZE_S 0 +#define CRYPTO_KEYSIZE_SIZE_256_BIT 0x00000003 +#define CRYPTO_KEYSIZE_SIZE_192_BIT 0x00000002 +#define CRYPTO_KEYSIZE_SIZE_128_BIT 0x00000001 //***************************************************************************** // @@ -877,10 +877,10 @@ // // 0: operation is completed. // 1: operation is not completed and the key store is busy. -#define CRYPTO_KEYREADAREA_BUSY 0x80000000 -#define CRYPTO_KEYREADAREA_BUSY_BITN 31 -#define CRYPTO_KEYREADAREA_BUSY_M 0x80000000 -#define CRYPTO_KEYREADAREA_BUSY_S 31 +#define CRYPTO_KEYREADAREA_BUSY 0x80000000 +#define CRYPTO_KEYREADAREA_BUSY_BITN 31 +#define CRYPTO_KEYREADAREA_BUSY_M 0x80000000 +#define CRYPTO_KEYREADAREA_BUSY_S 31 // Field: [3:0] RAM_AREA // @@ -898,18 +898,18 @@ // RAM_AREA2 RAM Area 2 // RAM_AREA1 RAM Area 1 // RAM_AREA0 RAM Area 0 -#define CRYPTO_KEYREADAREA_RAM_AREA_W 4 -#define CRYPTO_KEYREADAREA_RAM_AREA_M 0x0000000F -#define CRYPTO_KEYREADAREA_RAM_AREA_S 0 -#define CRYPTO_KEYREADAREA_RAM_AREA_NO_RAM 0x00000008 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA7 0x00000007 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA6 0x00000006 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA5 0x00000005 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA4 0x00000004 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA3 0x00000003 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA2 0x00000002 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA1 0x00000001 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA0 0x00000000 +#define CRYPTO_KEYREADAREA_RAM_AREA_W 4 +#define CRYPTO_KEYREADAREA_RAM_AREA_M 0x0000000F +#define CRYPTO_KEYREADAREA_RAM_AREA_S 0 +#define CRYPTO_KEYREADAREA_RAM_AREA_NO_RAM 0x00000008 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA7 0x00000007 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA6 0x00000006 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA5 0x00000005 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA4 0x00000004 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA3 0x00000003 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA2 0x00000002 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA1 0x00000001 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA0 0x00000000 //***************************************************************************** // @@ -921,9 +921,9 @@ // AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, // 96 ordered from the LSW entry of this 4-deep register array. // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY20_KEY2_W 32 -#define CRYPTO_AESKEY20_KEY2_M 0xFFFFFFFF -#define CRYPTO_AESKEY20_KEY2_S 0 +#define CRYPTO_AESKEY20_KEY2_W 32 +#define CRYPTO_AESKEY20_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY20_KEY2_S 0 //***************************************************************************** // @@ -935,9 +935,9 @@ // AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, // 96 ordered from the LSW entry of this 4-deep register array. // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY21_KEY2_W 32 -#define CRYPTO_AESKEY21_KEY2_M 0xFFFFFFFF -#define CRYPTO_AESKEY21_KEY2_S 0 +#define CRYPTO_AESKEY21_KEY2_W 32 +#define CRYPTO_AESKEY21_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY21_KEY2_S 0 //***************************************************************************** // @@ -949,9 +949,9 @@ // AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, // 96 ordered from the LSW entry of this 4-deep register array. // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY22_KEY2_W 32 -#define CRYPTO_AESKEY22_KEY2_M 0xFFFFFFFF -#define CRYPTO_AESKEY22_KEY2_S 0 +#define CRYPTO_AESKEY22_KEY2_W 32 +#define CRYPTO_AESKEY22_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY22_KEY2_S 0 //***************************************************************************** // @@ -963,9 +963,9 @@ // AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, // 96 ordered from the LSW entry of this 4-deep register array. // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY23_KEY2_W 32 -#define CRYPTO_AESKEY23_KEY2_M 0xFFFFFFFF -#define CRYPTO_AESKEY23_KEY2_S 0 +#define CRYPTO_AESKEY23_KEY2_W 32 +#define CRYPTO_AESKEY23_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY23_KEY2_S 0 //***************************************************************************** // @@ -977,9 +977,9 @@ // AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, // 96 ordered from the LSW entry of this 4-deep register arrary. // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY30_KEY3_W 32 -#define CRYPTO_AESKEY30_KEY3_M 0xFFFFFFFF -#define CRYPTO_AESKEY30_KEY3_S 0 +#define CRYPTO_AESKEY30_KEY3_W 32 +#define CRYPTO_AESKEY30_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY30_KEY3_S 0 //***************************************************************************** // @@ -991,9 +991,9 @@ // AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, // 96 ordered from the LSW entry of this 4-deep register arrary. // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY31_KEY3_W 32 -#define CRYPTO_AESKEY31_KEY3_M 0xFFFFFFFF -#define CRYPTO_AESKEY31_KEY3_S 0 +#define CRYPTO_AESKEY31_KEY3_W 32 +#define CRYPTO_AESKEY31_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY31_KEY3_S 0 //***************************************************************************** // @@ -1005,9 +1005,9 @@ // AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, // 96 ordered from the LSW entry of this 4-deep register arrary. // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY32_KEY3_W 32 -#define CRYPTO_AESKEY32_KEY3_M 0xFFFFFFFF -#define CRYPTO_AESKEY32_KEY3_S 0 +#define CRYPTO_AESKEY32_KEY3_W 32 +#define CRYPTO_AESKEY32_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY32_KEY3_S 0 //***************************************************************************** // @@ -1019,9 +1019,9 @@ // AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, // 96 ordered from the LSW entry of this 4-deep register arrary. // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY33_KEY3_W 32 -#define CRYPTO_AESKEY33_KEY3_M 0xFFFFFFFF -#define CRYPTO_AESKEY33_KEY3_S 0 +#define CRYPTO_AESKEY33_KEY3_W 32 +#define CRYPTO_AESKEY33_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY33_KEY3_S 0 //***************************************************************************** // @@ -1031,9 +1031,9 @@ // Field: [31:0] IV // // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESIV0_IV_W 32 -#define CRYPTO_AESIV0_IV_M 0xFFFFFFFF -#define CRYPTO_AESIV0_IV_S 0 +#define CRYPTO_AESIV0_IV_W 32 +#define CRYPTO_AESIV0_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV0_IV_S 0 //***************************************************************************** // @@ -1043,9 +1043,9 @@ // Field: [31:0] IV // // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESIV1_IV_W 32 -#define CRYPTO_AESIV1_IV_M 0xFFFFFFFF -#define CRYPTO_AESIV1_IV_S 0 +#define CRYPTO_AESIV1_IV_W 32 +#define CRYPTO_AESIV1_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV1_IV_S 0 //***************************************************************************** // @@ -1055,9 +1055,9 @@ // Field: [31:0] IV // // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESIV2_IV_W 32 -#define CRYPTO_AESIV2_IV_M 0xFFFFFFFF -#define CRYPTO_AESIV2_IV_S 0 +#define CRYPTO_AESIV2_IV_W 32 +#define CRYPTO_AESIV2_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV2_IV_S 0 //***************************************************************************** // @@ -1067,9 +1067,9 @@ // Field: [31:0] IV // // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESIV3_IV_W 32 -#define CRYPTO_AESIV3_IV_M 0xFFFFFFFF -#define CRYPTO_AESIV3_IV_S 0 +#define CRYPTO_AESIV3_IV_W 32 +#define CRYPTO_AESIV3_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV3_IV_S 0 //***************************************************************************** // @@ -1082,10 +1082,10 @@ // overwritten and the Host is permitted to write the next context. Writing a // context means writing either a mode, the crypto length or // AESDATALEN1.LEN_MSW, AESDATALEN0.LEN_LSW length registers -#define CRYPTO_AESCTL_CONTEXT_RDY 0x80000000 -#define CRYPTO_AESCTL_CONTEXT_RDY_BITN 31 -#define CRYPTO_AESCTL_CONTEXT_RDY_M 0x80000000 -#define CRYPTO_AESCTL_CONTEXT_RDY_S 31 +#define CRYPTO_AESCTL_CONTEXT_RDY 0x80000000 +#define CRYPTO_AESCTL_CONTEXT_RDY_BITN 31 +#define CRYPTO_AESCTL_CONTEXT_RDY_M 0x80000000 +#define CRYPTO_AESCTL_CONTEXT_RDY_S 31 // Field: [30] SAVED_CONTEXT_RDY // @@ -1107,18 +1107,18 @@ // For typical use, this bit does NOT need to be written, but is used for // status reading only. In this case, this status bit is automatically // maintained by the Crypto peripheral. -#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY 0x40000000 -#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_BITN 30 -#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M 0x40000000 -#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_S 30 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY 0x40000000 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_BITN 30 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M 0x40000000 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_S 30 // Field: [29] SAVE_CONTEXT // // IV must be read before the AES engine can start a new operation. -#define CRYPTO_AESCTL_SAVE_CONTEXT 0x20000000 -#define CRYPTO_AESCTL_SAVE_CONTEXT_BITN 29 -#define CRYPTO_AESCTL_SAVE_CONTEXT_M 0x20000000 -#define CRYPTO_AESCTL_SAVE_CONTEXT_S 29 +#define CRYPTO_AESCTL_SAVE_CONTEXT 0x20000000 +#define CRYPTO_AESCTL_SAVE_CONTEXT_BITN 29 +#define CRYPTO_AESCTL_SAVE_CONTEXT_M 0x20000000 +#define CRYPTO_AESCTL_SAVE_CONTEXT_S 29 // Field: [24:22] CCM_M // @@ -1127,18 +1127,18 @@ // CCM_M plus one. // Note: The Crypto peripheral always returns a 128-bit authentication field, // of which the M least significant bytes are valid. All values are supported. -#define CRYPTO_AESCTL_CCM_M_W 3 -#define CRYPTO_AESCTL_CCM_M_M 0x01C00000 -#define CRYPTO_AESCTL_CCM_M_S 22 +#define CRYPTO_AESCTL_CCM_M_W 3 +#define CRYPTO_AESCTL_CCM_M_M 0x01C00000 +#define CRYPTO_AESCTL_CCM_M_S 22 // Field: [21:19] CCM_L // // Defines L that indicates the width of the length field for CCM operations; // the length field in bytes equals the value of CMM_L plus one. All values are // supported. -#define CRYPTO_AESCTL_CCM_L_W 3 -#define CRYPTO_AESCTL_CCM_L_M 0x00380000 -#define CRYPTO_AESCTL_CCM_L_S 19 +#define CRYPTO_AESCTL_CCM_L_W 3 +#define CRYPTO_AESCTL_CCM_L_M 0x00380000 +#define CRYPTO_AESCTL_CCM_L_S 19 // Field: [18] CCM // @@ -1149,10 +1149,10 @@ // AESDATALEN0.LEN_LSW after all other registers. // Note: The CTR mode bit in this register must also be set to 1 to enable // AES-CTR; selecting other AES modes than CTR mode is invalid. -#define CRYPTO_AESCTL_CCM 0x00040000 -#define CRYPTO_AESCTL_CCM_BITN 18 -#define CRYPTO_AESCTL_CCM_M 0x00040000 -#define CRYPTO_AESCTL_CCM_S 18 +#define CRYPTO_AESCTL_CCM 0x00040000 +#define CRYPTO_AESCTL_CCM_BITN 18 +#define CRYPTO_AESCTL_CCM_M 0x00040000 +#define CRYPTO_AESCTL_CCM_S 18 // Field: [15] CBC_MAC // @@ -1160,10 +1160,10 @@ // The DIR bit must be set to 1 for this mode. // Selecting this mode requires writing the AESDATALEN1.LEN_MSW and // AESDATALEN0.LEN_LSW registers after all other registers. -#define CRYPTO_AESCTL_CBC_MAC 0x00008000 -#define CRYPTO_AESCTL_CBC_MAC_BITN 15 -#define CRYPTO_AESCTL_CBC_MAC_M 0x00008000 -#define CRYPTO_AESCTL_CBC_MAC_S 15 +#define CRYPTO_AESCTL_CBC_MAC 0x00008000 +#define CRYPTO_AESCTL_CBC_MAC_BITN 15 +#define CRYPTO_AESCTL_CBC_MAC_M 0x00008000 +#define CRYPTO_AESCTL_CBC_MAC_S 15 // Field: [8:7] CTR_WIDTH // @@ -1173,30 +1173,30 @@ // 96_BIT 96 bits // 64_BIT 64 bits // 32_BIT 32 bits -#define CRYPTO_AESCTL_CTR_WIDTH_W 2 -#define CRYPTO_AESCTL_CTR_WIDTH_M 0x00000180 -#define CRYPTO_AESCTL_CTR_WIDTH_S 7 -#define CRYPTO_AESCTL_CTR_WIDTH_128_BIT 0x00000180 -#define CRYPTO_AESCTL_CTR_WIDTH_96_BIT 0x00000100 -#define CRYPTO_AESCTL_CTR_WIDTH_64_BIT 0x00000080 -#define CRYPTO_AESCTL_CTR_WIDTH_32_BIT 0x00000000 +#define CRYPTO_AESCTL_CTR_WIDTH_W 2 +#define CRYPTO_AESCTL_CTR_WIDTH_M 0x00000180 +#define CRYPTO_AESCTL_CTR_WIDTH_S 7 +#define CRYPTO_AESCTL_CTR_WIDTH_128_BIT 0x00000180 +#define CRYPTO_AESCTL_CTR_WIDTH_96_BIT 0x00000100 +#define CRYPTO_AESCTL_CTR_WIDTH_64_BIT 0x00000080 +#define CRYPTO_AESCTL_CTR_WIDTH_32_BIT 0x00000000 // Field: [6] CTR // // AES-CTR mode enable // This bit must also be set for CCM, when encryption/decryption is required. -#define CRYPTO_AESCTL_CTR 0x00000040 -#define CRYPTO_AESCTL_CTR_BITN 6 -#define CRYPTO_AESCTL_CTR_M 0x00000040 -#define CRYPTO_AESCTL_CTR_S 6 +#define CRYPTO_AESCTL_CTR 0x00000040 +#define CRYPTO_AESCTL_CTR_BITN 6 +#define CRYPTO_AESCTL_CTR_M 0x00000040 +#define CRYPTO_AESCTL_CTR_S 6 // Field: [5] CBC // // CBC mode enable -#define CRYPTO_AESCTL_CBC 0x00000020 -#define CRYPTO_AESCTL_CBC_BITN 5 -#define CRYPTO_AESCTL_CBC_M 0x00000020 -#define CRYPTO_AESCTL_CBC_S 5 +#define CRYPTO_AESCTL_CBC 0x00000020 +#define CRYPTO_AESCTL_CBC_BITN 5 +#define CRYPTO_AESCTL_CBC_M 0x00000020 +#define CRYPTO_AESCTL_CBC_S 5 // Field: [4:3] KEY_SIZE // @@ -1208,9 +1208,9 @@ // 10 = N/A - reserved // 11 = N/A - reserved // For the Crypto peripheral this field is fixed to 128 bits. -#define CRYPTO_AESCTL_KEY_SIZE_W 2 -#define CRYPTO_AESCTL_KEY_SIZE_M 0x00000018 -#define CRYPTO_AESCTL_KEY_SIZE_S 3 +#define CRYPTO_AESCTL_KEY_SIZE_W 2 +#define CRYPTO_AESCTL_KEY_SIZE_M 0x00000018 +#define CRYPTO_AESCTL_KEY_SIZE_S 3 // Field: [2] DIR // @@ -1219,10 +1219,10 @@ // 1 : Encrypt operation is performed. // // This bit must be written with a 1 when CBC-MAC is selected. -#define CRYPTO_AESCTL_DIR 0x00000004 -#define CRYPTO_AESCTL_DIR_BITN 2 -#define CRYPTO_AESCTL_DIR_M 0x00000004 -#define CRYPTO_AESCTL_DIR_S 2 +#define CRYPTO_AESCTL_DIR 0x00000004 +#define CRYPTO_AESCTL_DIR_BITN 2 +#define CRYPTO_AESCTL_DIR_M 0x00000004 +#define CRYPTO_AESCTL_DIR_S 2 // Field: [1] INPUT_RDY // @@ -1242,10 +1242,10 @@ // For typical use, this bit does NOT need to be written, but is used for // status reading only. In this case, this status bit is automatically // maintained by the Crypto peripheral. -#define CRYPTO_AESCTL_INPUT_RDY 0x00000002 -#define CRYPTO_AESCTL_INPUT_RDY_BITN 1 -#define CRYPTO_AESCTL_INPUT_RDY_M 0x00000002 -#define CRYPTO_AESCTL_INPUT_RDY_S 1 +#define CRYPTO_AESCTL_INPUT_RDY 0x00000002 +#define CRYPTO_AESCTL_INPUT_RDY_BITN 1 +#define CRYPTO_AESCTL_INPUT_RDY_M 0x00000002 +#define CRYPTO_AESCTL_INPUT_RDY_S 1 // Field: [0] OUTPUT_RDY // @@ -1263,10 +1263,10 @@ // For typical use, this bit does NOT need to be written, but is used for // status reading only. In this case, this status bit is automatically // maintained by the Crypto peripheral. -#define CRYPTO_AESCTL_OUTPUT_RDY 0x00000001 -#define CRYPTO_AESCTL_OUTPUT_RDY_BITN 0 -#define CRYPTO_AESCTL_OUTPUT_RDY_M 0x00000001 -#define CRYPTO_AESCTL_OUTPUT_RDY_S 0 +#define CRYPTO_AESCTL_OUTPUT_RDY 0x00000001 +#define CRYPTO_AESCTL_OUTPUT_RDY_BITN 0 +#define CRYPTO_AESCTL_OUTPUT_RDY_M 0x00000001 +#define CRYPTO_AESCTL_OUTPUT_RDY_S 0 //***************************************************************************** // @@ -1278,9 +1278,9 @@ // Used to write the Length values to the Crypto peripheral. // // This register contains bits [31:0] of the combined data length. -#define CRYPTO_AESDATALEN0_LEN_LSW_W 32 -#define CRYPTO_AESDATALEN0_LEN_LSW_M 0xFFFFFFFF -#define CRYPTO_AESDATALEN0_LEN_LSW_S 0 +#define CRYPTO_AESDATALEN0_LEN_LSW_W 32 +#define CRYPTO_AESDATALEN0_LEN_LSW_M 0xFFFFFFFF +#define CRYPTO_AESDATALEN0_LEN_LSW_S 0 //***************************************************************************** // @@ -1311,9 +1311,9 @@ // data streams are not supported by the Crypto peripheral. For block cipher // modes, the data length must be programmed in multiples of the block cipher // size, 16 bytes. -#define CRYPTO_AESDATALEN1_LEN_MSW_W 29 -#define CRYPTO_AESDATALEN1_LEN_MSW_M 0x1FFFFFFF -#define CRYPTO_AESDATALEN1_LEN_MSW_S 0 +#define CRYPTO_AESDATALEN1_LEN_MSW_W 29 +#define CRYPTO_AESDATALEN1_LEN_MSW_M 0x1FFFFFFF +#define CRYPTO_AESDATALEN1_LEN_MSW_S 0 //***************************************************************************** // @@ -1327,9 +1327,9 @@ // processing with this context is started, this length decrements to zero. // Writing this register triggers the engine to start using this context for // CCM. -#define CRYPTO_AESAUTHLEN_LEN_W 32 -#define CRYPTO_AESAUTHLEN_LEN_M 0xFFFFFFFF -#define CRYPTO_AESAUTHLEN_LEN_S 0 +#define CRYPTO_AESAUTHLEN_LEN_W 32 +#define CRYPTO_AESAUTHLEN_LEN_M 0xFFFFFFFF +#define CRYPTO_AESAUTHLEN_LEN_S 0 //***************************************************************************** // @@ -1356,9 +1356,9 @@ // // Note: The AAD / authentication only data is not copied to the output buffer // but only used for authentication. -#define CRYPTO_AESDATAOUT0_DATA_W 32 -#define CRYPTO_AESDATAOUT0_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAOUT0_DATA_S 0 +#define CRYPTO_AESDATAOUT0_DATA_W 32 +#define CRYPTO_AESDATAOUT0_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT0_DATA_S 0 //***************************************************************************** // @@ -1390,9 +1390,9 @@ // pads or masks misaligned ending data blocks with zeroes for GCM, CCM and // CBC-MAC. For CTR mode, the remaining data in an unaligned data block is // ignored. -#define CRYPTO_AESDATAIN0_DATA_W 32 -#define CRYPTO_AESDATAIN0_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAIN0_DATA_S 0 +#define CRYPTO_AESDATAIN0_DATA_W 32 +#define CRYPTO_AESDATAIN0_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN0_DATA_S 0 //***************************************************************************** // @@ -1419,9 +1419,9 @@ // // Note: The AAD / authentication only data is not copied to the output buffer // but only used for authentication. -#define CRYPTO_AESDATAOUT1_DATA_W 32 -#define CRYPTO_AESDATAOUT1_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAOUT1_DATA_S 0 +#define CRYPTO_AESDATAOUT1_DATA_W 32 +#define CRYPTO_AESDATAOUT1_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT1_DATA_S 0 //***************************************************************************** // @@ -1453,9 +1453,9 @@ // pads or masks misaligned ending data blocks with zeroes for GCM, CCM and // CBC-MAC. For CTR mode, the remaining data in an unaligned data block is // ignored. -#define CRYPTO_AESDATAIN1_DATA_W 32 -#define CRYPTO_AESDATAIN1_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAIN1_DATA_S 0 +#define CRYPTO_AESDATAIN1_DATA_W 32 +#define CRYPTO_AESDATAIN1_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN1_DATA_S 0 //***************************************************************************** // @@ -1482,9 +1482,9 @@ // // Note: The AAD / authentication only data is not copied to the output buffer // but only used for authentication. -#define CRYPTO_AESDATAOUT2_DATA_W 32 -#define CRYPTO_AESDATAOUT2_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAOUT2_DATA_S 0 +#define CRYPTO_AESDATAOUT2_DATA_W 32 +#define CRYPTO_AESDATAOUT2_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT2_DATA_S 0 //***************************************************************************** // @@ -1516,9 +1516,9 @@ // pads or masks misaligned ending data blocks with zeroes for GCM, CCM and // CBC-MAC. For CTR mode, the remaining data in an unaligned data block is // ignored. -#define CRYPTO_AESDATAIN2_DATA_W 32 -#define CRYPTO_AESDATAIN2_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAIN2_DATA_S 0 +#define CRYPTO_AESDATAIN2_DATA_W 32 +#define CRYPTO_AESDATAIN2_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN2_DATA_S 0 //***************************************************************************** // @@ -1545,9 +1545,9 @@ // // Note: The AAD / authentication only data is not copied to the output buffer // but only used for authentication. -#define CRYPTO_AESDATAOUT3_DATA_W 32 -#define CRYPTO_AESDATAOUT3_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAOUT3_DATA_S 0 +#define CRYPTO_AESDATAOUT3_DATA_W 32 +#define CRYPTO_AESDATAOUT3_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT3_DATA_S 0 //***************************************************************************** // @@ -1579,9 +1579,9 @@ // pads or masks misaligned ending data blocks with zeroes for GCM, CCM and // CBC-MAC. For CTR mode, the remaining data in an unaligned data block is // ignored. -#define CRYPTO_AESDATAIN3_DATA_W 32 -#define CRYPTO_AESDATAIN3_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAIN3_DATA_S 0 +#define CRYPTO_AESDATAIN3_DATA_W 32 +#define CRYPTO_AESDATAIN3_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN3_DATA_S 0 //***************************************************************************** // @@ -1592,9 +1592,9 @@ // // This register contains the authentication TAG for the combined and // authentication-only modes. -#define CRYPTO_AESTAGOUT0_TAG_W 32 -#define CRYPTO_AESTAGOUT0_TAG_M 0xFFFFFFFF -#define CRYPTO_AESTAGOUT0_TAG_S 0 +#define CRYPTO_AESTAGOUT0_TAG_W 32 +#define CRYPTO_AESTAGOUT0_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT0_TAG_S 0 //***************************************************************************** // @@ -1605,9 +1605,9 @@ // // This register contains the authentication TAG for the combined and // authentication-only modes. -#define CRYPTO_AESTAGOUT1_TAG_W 32 -#define CRYPTO_AESTAGOUT1_TAG_M 0xFFFFFFFF -#define CRYPTO_AESTAGOUT1_TAG_S 0 +#define CRYPTO_AESTAGOUT1_TAG_W 32 +#define CRYPTO_AESTAGOUT1_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT1_TAG_S 0 //***************************************************************************** // @@ -1618,9 +1618,9 @@ // // This register contains the authentication TAG for the combined and // authentication-only modes. -#define CRYPTO_AESTAGOUT2_TAG_W 32 -#define CRYPTO_AESTAGOUT2_TAG_M 0xFFFFFFFF -#define CRYPTO_AESTAGOUT2_TAG_S 0 +#define CRYPTO_AESTAGOUT2_TAG_W 32 +#define CRYPTO_AESTAGOUT2_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT2_TAG_S 0 //***************************************************************************** // @@ -1631,9 +1631,9 @@ // // This register contains the authentication TAG for the combined and // authentication-only modes. -#define CRYPTO_AESTAGOUT3_TAG_W 32 -#define CRYPTO_AESTAGOUT3_TAG_M 0xFFFFFFFF -#define CRYPTO_AESTAGOUT3_TAG_S 0 +#define CRYPTO_AESTAGOUT3_TAG_W 32 +#define CRYPTO_AESTAGOUT3_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT3_TAG_S 0 //***************************************************************************** // @@ -1645,29 +1645,29 @@ // If this bit is cleared to 0, the DMA operation involves only data. // If this bit is set, the DMA operation includes a TAG (Authentication Result // / Digest). -#define CRYPTO_ALGSEL_TAG 0x80000000 -#define CRYPTO_ALGSEL_TAG_BITN 31 -#define CRYPTO_ALGSEL_TAG_M 0x80000000 -#define CRYPTO_ALGSEL_TAG_S 31 +#define CRYPTO_ALGSEL_TAG 0x80000000 +#define CRYPTO_ALGSEL_TAG_BITN 31 +#define CRYPTO_ALGSEL_TAG_M 0x80000000 +#define CRYPTO_ALGSEL_TAG_S 31 // Field: [1] AES // // If set to 1, the AES data is loaded via DMA // Both Read and Write maximum transfer size to DMA engine is set to 16 bytes -#define CRYPTO_ALGSEL_AES 0x00000002 -#define CRYPTO_ALGSEL_AES_BITN 1 -#define CRYPTO_ALGSEL_AES_M 0x00000002 -#define CRYPTO_ALGSEL_AES_S 1 +#define CRYPTO_ALGSEL_AES 0x00000002 +#define CRYPTO_ALGSEL_AES_BITN 1 +#define CRYPTO_ALGSEL_AES_M 0x00000002 +#define CRYPTO_ALGSEL_AES_S 1 // Field: [0] KEY_STORE // // If set to 1, selects the Key Store to be loaded via DMA. // The maximum transfer size to DMA engine is set to 32 bytes (however // transfers of 16, 24 and 32 bytes are allowed) -#define CRYPTO_ALGSEL_KEY_STORE 0x00000001 -#define CRYPTO_ALGSEL_KEY_STORE_BITN 0 -#define CRYPTO_ALGSEL_KEY_STORE_M 0x00000001 -#define CRYPTO_ALGSEL_KEY_STORE_S 0 +#define CRYPTO_ALGSEL_KEY_STORE 0x00000001 +#define CRYPTO_ALGSEL_KEY_STORE_BITN 0 +#define CRYPTO_ALGSEL_KEY_STORE_M 0x00000001 +#define CRYPTO_ALGSEL_KEY_STORE_S 0 //***************************************************************************** // @@ -1680,10 +1680,10 @@ // area as destination. // 0 : transfers use 'USER' type access. // 1 : transfers use 'PRIVILEGED' type access. -#define CRYPTO_DMAPROTCTL_EN 0x00000001 -#define CRYPTO_DMAPROTCTL_EN_BITN 0 -#define CRYPTO_DMAPROTCTL_EN_M 0x00000001 -#define CRYPTO_DMAPROTCTL_EN_S 0 +#define CRYPTO_DMAPROTCTL_EN 0x00000001 +#define CRYPTO_DMAPROTCTL_EN_BITN 0 +#define CRYPTO_DMAPROTCTL_EN_M 0x00000001 +#define CRYPTO_DMAPROTCTL_EN_S 0 //***************************************************************************** // @@ -1699,10 +1699,10 @@ // flags; therefore the keys must be reloaded to the key store module. // Writing 0 has no effect. // The bit is self cleared after executing the reset. -#define CRYPTO_SWRESET_RESET 0x00000001 -#define CRYPTO_SWRESET_RESET_BITN 0 -#define CRYPTO_SWRESET_RESET_M 0x00000001 -#define CRYPTO_SWRESET_RESET_S 0 +#define CRYPTO_SWRESET_RESET 0x00000001 +#define CRYPTO_SWRESET_RESET_BITN 0 +#define CRYPTO_SWRESET_RESET_M 0x00000001 +#define CRYPTO_SWRESET_RESET_S 0 //***************************************************************************** // @@ -1715,10 +1715,10 @@ // If this bit is set to 1, the interrupt is a level interrupt that must be // cleared by writing the interrupt clear register. // This bit is applicable for both interrupt output signals. -#define CRYPTO_IRQTYPE_LEVEL 0x00000001 -#define CRYPTO_IRQTYPE_LEVEL_BITN 0 -#define CRYPTO_IRQTYPE_LEVEL_M 0x00000001 -#define CRYPTO_IRQTYPE_LEVEL_S 0 +#define CRYPTO_IRQTYPE_LEVEL 0x00000001 +#define CRYPTO_IRQTYPE_LEVEL_BITN 0 +#define CRYPTO_IRQTYPE_LEVEL_M 0x00000001 +#define CRYPTO_IRQTYPE_LEVEL_S 0 //***************************************************************************** // @@ -1728,18 +1728,18 @@ // Field: [1] DMA_IN_DONE // // This bit enables IRQSTAT.DMA_IN_DONE as source for IRQ. -#define CRYPTO_IRQEN_DMA_IN_DONE 0x00000002 -#define CRYPTO_IRQEN_DMA_IN_DONE_BITN 1 -#define CRYPTO_IRQEN_DMA_IN_DONE_M 0x00000002 -#define CRYPTO_IRQEN_DMA_IN_DONE_S 1 +#define CRYPTO_IRQEN_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQEN_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQEN_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQEN_DMA_IN_DONE_S 1 // Field: [0] RESULT_AVAIL // // This bit enables IRQSTAT.RESULT_AVAIL as source for IRQ. -#define CRYPTO_IRQEN_RESULT_AVAIL 0x00000001 -#define CRYPTO_IRQEN_RESULT_AVAIL_BITN 0 -#define CRYPTO_IRQEN_RESULT_AVAIL_M 0x00000001 -#define CRYPTO_IRQEN_RESULT_AVAIL_S 0 +#define CRYPTO_IRQEN_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQEN_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQEN_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQEN_RESULT_AVAIL_S 0 //***************************************************************************** // @@ -1749,42 +1749,42 @@ // Field: [31] DMA_BUS_ERR // // If 1 is written to this bit, IRQSTAT.DMA_BUS_ERR is cleared. -#define CRYPTO_IRQCLR_DMA_BUS_ERR 0x80000000 -#define CRYPTO_IRQCLR_DMA_BUS_ERR_BITN 31 -#define CRYPTO_IRQCLR_DMA_BUS_ERR_M 0x80000000 -#define CRYPTO_IRQCLR_DMA_BUS_ERR_S 31 +#define CRYPTO_IRQCLR_DMA_BUS_ERR 0x80000000 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_BITN 31 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_M 0x80000000 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_S 31 // Field: [30] KEY_ST_WR_ERR // // If 1 is written to this bit, IRQSTAT.KEY_ST_WR_ERR is cleared. -#define CRYPTO_IRQCLR_KEY_ST_WR_ERR 0x40000000 -#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_BITN 30 -#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_M 0x40000000 -#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_S 30 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR 0x40000000 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_BITN 30 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_M 0x40000000 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_S 30 // Field: [29] KEY_ST_RD_ERR // // If 1 is written to this bit, IRQSTAT.KEY_ST_RD_ERR is cleared. -#define CRYPTO_IRQCLR_KEY_ST_RD_ERR 0x20000000 -#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_BITN 29 -#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_M 0x20000000 -#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_S 29 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR 0x20000000 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_BITN 29 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_M 0x20000000 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_S 29 // Field: [1] DMA_IN_DONE // // If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is cleared. -#define CRYPTO_IRQCLR_DMA_IN_DONE 0x00000002 -#define CRYPTO_IRQCLR_DMA_IN_DONE_BITN 1 -#define CRYPTO_IRQCLR_DMA_IN_DONE_M 0x00000002 -#define CRYPTO_IRQCLR_DMA_IN_DONE_S 1 +#define CRYPTO_IRQCLR_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQCLR_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQCLR_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQCLR_DMA_IN_DONE_S 1 // Field: [0] RESULT_AVAIL // // If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is cleared. -#define CRYPTO_IRQCLR_RESULT_AVAIL 0x00000001 -#define CRYPTO_IRQCLR_RESULT_AVAIL_BITN 0 -#define CRYPTO_IRQCLR_RESULT_AVAIL_M 0x00000001 -#define CRYPTO_IRQCLR_RESULT_AVAIL_S 0 +#define CRYPTO_IRQCLR_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQCLR_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQCLR_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQCLR_RESULT_AVAIL_S 0 //***************************************************************************** // @@ -1795,19 +1795,19 @@ // // If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is set. // Writing 0 has no effect. -#define CRYPTO_IRQSET_DMA_IN_DONE 0x00000002 -#define CRYPTO_IRQSET_DMA_IN_DONE_BITN 1 -#define CRYPTO_IRQSET_DMA_IN_DONE_M 0x00000002 -#define CRYPTO_IRQSET_DMA_IN_DONE_S 1 +#define CRYPTO_IRQSET_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQSET_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQSET_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQSET_DMA_IN_DONE_S 1 // Field: [0] RESULT_AVAIL // // If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is set. // Writing 0 has no effect. -#define CRYPTO_IRQSET_RESULT_AVAIL 0x00000001 -#define CRYPTO_IRQSET_RESULT_AVAIL_BITN 0 -#define CRYPTO_IRQSET_RESULT_AVAIL_M 0x00000001 -#define CRYPTO_IRQSET_RESULT_AVAIL_S 0 +#define CRYPTO_IRQSET_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQSET_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQSET_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQSET_RESULT_AVAIL_S 0 //***************************************************************************** // @@ -1821,10 +1821,10 @@ // Note: This error is asserted if an error is detected on the AHB master // interface during a DMA operation. // Note: This is not an interrupt source. -#define CRYPTO_IRQSTAT_DMA_BUS_ERR 0x80000000 -#define CRYPTO_IRQSTAT_DMA_BUS_ERR_BITN 31 -#define CRYPTO_IRQSTAT_DMA_BUS_ERR_M 0x80000000 -#define CRYPTO_IRQSTAT_DMA_BUS_ERR_S 31 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR 0x80000000 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_BITN 31 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_M 0x80000000 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_S 31 // Field: [30] KEY_ST_WR_ERR // @@ -1834,10 +1834,10 @@ // Note: This error is asserted if a DMA operation does not cover a full key // area or more areas are written than expected. // Note: This is not an interrupt source. -#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR 0x40000000 -#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_BITN 30 -#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M 0x40000000 -#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_S 30 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR 0x40000000 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_BITN 30 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M 0x40000000 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_S 30 // Field: [29] KEY_ST_RD_ERR // @@ -1847,26 +1847,26 @@ // Note: This error is asserted if a key location is selected in the key store // that is not available. // Note: This is not an interrupt source. -#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR 0x20000000 -#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_BITN 29 -#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M 0x20000000 -#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_S 29 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR 0x20000000 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_BITN 29 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M 0x20000000 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_S 29 // Field: [1] DMA_IN_DONE // // This bit returns the status of DMA data in done interrupt. -#define CRYPTO_IRQSTAT_DMA_IN_DONE 0x00000002 -#define CRYPTO_IRQSTAT_DMA_IN_DONE_BITN 1 -#define CRYPTO_IRQSTAT_DMA_IN_DONE_M 0x00000002 -#define CRYPTO_IRQSTAT_DMA_IN_DONE_S 1 +#define CRYPTO_IRQSTAT_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_S 1 // Field: [0] RESULT_AVAIL // // This bit is set high when the Crypto peripheral has a result available. -#define CRYPTO_IRQSTAT_RESULT_AVAIL 0x00000001 -#define CRYPTO_IRQSTAT_RESULT_AVAIL_BITN 0 -#define CRYPTO_IRQSTAT_RESULT_AVAIL_M 0x00000001 -#define CRYPTO_IRQSTAT_RESULT_AVAIL_S 0 +#define CRYPTO_IRQSTAT_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_S 0 //***************************************************************************** // @@ -1876,39 +1876,38 @@ // Field: [27:24] HW_MAJOR_VER // // Major version number -#define CRYPTO_HWVER_HW_MAJOR_VER_W 4 -#define CRYPTO_HWVER_HW_MAJOR_VER_M 0x0F000000 -#define CRYPTO_HWVER_HW_MAJOR_VER_S 24 +#define CRYPTO_HWVER_HW_MAJOR_VER_W 4 +#define CRYPTO_HWVER_HW_MAJOR_VER_M 0x0F000000 +#define CRYPTO_HWVER_HW_MAJOR_VER_S 24 // Field: [23:20] HW_MINOR_VER // // Minor version number -#define CRYPTO_HWVER_HW_MINOR_VER_W 4 -#define CRYPTO_HWVER_HW_MINOR_VER_M 0x00F00000 -#define CRYPTO_HWVER_HW_MINOR_VER_S 20 +#define CRYPTO_HWVER_HW_MINOR_VER_W 4 +#define CRYPTO_HWVER_HW_MINOR_VER_M 0x00F00000 +#define CRYPTO_HWVER_HW_MINOR_VER_S 20 // Field: [19:16] HW_PATCH_LVL // // Patch level, starts at 0 at first delivery of this version. -#define CRYPTO_HWVER_HW_PATCH_LVL_W 4 -#define CRYPTO_HWVER_HW_PATCH_LVL_M 0x000F0000 -#define CRYPTO_HWVER_HW_PATCH_LVL_S 16 +#define CRYPTO_HWVER_HW_PATCH_LVL_W 4 +#define CRYPTO_HWVER_HW_PATCH_LVL_M 0x000F0000 +#define CRYPTO_HWVER_HW_PATCH_LVL_S 16 // Field: [15:8] VER_NUM_COMPL // // These bits simply contain the complement of VER_NUM (0x87), used by a driver // to ascertain that the Crypto peripheral register is indeed read. -#define CRYPTO_HWVER_VER_NUM_COMPL_W 8 -#define CRYPTO_HWVER_VER_NUM_COMPL_M 0x0000FF00 -#define CRYPTO_HWVER_VER_NUM_COMPL_S 8 +#define CRYPTO_HWVER_VER_NUM_COMPL_W 8 +#define CRYPTO_HWVER_VER_NUM_COMPL_M 0x0000FF00 +#define CRYPTO_HWVER_VER_NUM_COMPL_S 8 // Field: [7:0] VER_NUM // // The version number for the Crypto peripheral, this field contains the value // 120 (decimal) or 0x78. -#define CRYPTO_HWVER_VER_NUM_W 8 -#define CRYPTO_HWVER_VER_NUM_M 0x000000FF -#define CRYPTO_HWVER_VER_NUM_S 0 - +#define CRYPTO_HWVER_VER_NUM_W 8 +#define CRYPTO_HWVER_VER_NUM_M 0x000000FF +#define CRYPTO_HWVER_VER_NUM_S 0 #endif // __CRYPTO__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ddi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ddi.h index d81a93a..6113118 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ddi.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ddi.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_ddi.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_ddi.h + * Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) + * Revision: 49096 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_DDI_H__ #define __HW_DDI_H__ @@ -176,22 +176,20 @@ // The following are defines for the DDI master instruction offsets. // //***************************************************************************** -#define DDI_O_DIR 0x00000000 // Offset for the direct access instruction -#define DDI_O_SET 0x00000040 // Offset for 'Set' instruction. -#define DDI_O_CLR 0x00000080 // Offset for 'Clear' instruction. -#define DDI_O_MASK4B 0x00000100 // Offset for 4-bit masked access. +#define DDI_O_DIR 0x00000000 // Offset for the direct access instruction +#define DDI_O_SET 0x00000040 // Offset for 'Set' instruction. +#define DDI_O_CLR 0x00000080 // Offset for 'Clear' instruction. +#define DDI_O_MASK4B 0x00000100 // Offset for 4-bit masked access. // Data bit[n] is written if mask bit[n] is set ('1'). // Bits 7:4 are mask. Bits 3:0 are data. // Requires 'byte' write. -#define DDI_O_MASK8B 0x00000180 // Offset for 8-bit masked access. +#define DDI_O_MASK8B 0x00000180 // Offset for 8-bit masked access. // Data bit[n] is written if mask bit[n] is set ('1'). // Bits 15:8 are mask. Bits 7:0 are data. // Requires 'short' write. -#define DDI_O_MASK16B 0x00000200 // Offset for 16-bit masked access. +#define DDI_O_MASK16B 0x00000200 // Offset for 16-bit masked access. // Data bit[n] is written if mask bit[n] is set ('1'). // Bits 31:16 are mask. Bits 15:0 are data. // Requires 'long' write. - - #endif // __HW_DDI_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ddi_0_osc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ddi_0_osc.h index 9363ec1..78e638b 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ddi_0_osc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ddi_0_osc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_ddi_0_osc_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_ddi_0_osc_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_DDI_0_OSC_H__ #define __HW_DDI_0_OSC_H__ @@ -44,52 +44,52 @@ // //***************************************************************************** // Control 0 -#define DDI_0_OSC_O_CTL0 0x00000000 +#define DDI_0_OSC_O_CTL0 0x00000000 // Control 1 -#define DDI_0_OSC_O_CTL1 0x00000004 +#define DDI_0_OSC_O_CTL1 0x00000004 // RADC External Configuration -#define DDI_0_OSC_O_RADCEXTCFG 0x00000008 +#define DDI_0_OSC_O_RADCEXTCFG 0x00000008 // Amplitude Compensation Control -#define DDI_0_OSC_O_AMPCOMPCTL 0x0000000C +#define DDI_0_OSC_O_AMPCOMPCTL 0x0000000C // Amplitude Compensation Threshold 1 -#define DDI_0_OSC_O_AMPCOMPTH1 0x00000010 +#define DDI_0_OSC_O_AMPCOMPTH1 0x00000010 // Amplitude Compensation Threshold 2 -#define DDI_0_OSC_O_AMPCOMPTH2 0x00000014 +#define DDI_0_OSC_O_AMPCOMPTH2 0x00000014 // Analog Bypass Values 1 -#define DDI_0_OSC_O_ANABYPASSVAL1 0x00000018 +#define DDI_0_OSC_O_ANABYPASSVAL1 0x00000018 // Internal -#define DDI_0_OSC_O_ANABYPASSVAL2 0x0000001C +#define DDI_0_OSC_O_ANABYPASSVAL2 0x0000001C // Analog Test Control -#define DDI_0_OSC_O_ATESTCTL 0x00000020 +#define DDI_0_OSC_O_ATESTCTL 0x00000020 // ADC Doubler Nanoamp Control -#define DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL 0x00000024 +#define DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL 0x00000024 // XOSCHF Control -#define DDI_0_OSC_O_XOSCHFCTL 0x00000028 +#define DDI_0_OSC_O_XOSCHFCTL 0x00000028 // Low Frequency Oscillator Control -#define DDI_0_OSC_O_LFOSCCTL 0x0000002C +#define DDI_0_OSC_O_LFOSCCTL 0x0000002C // RCOSCHF Control -#define DDI_0_OSC_O_RCOSCHFCTL 0x00000030 +#define DDI_0_OSC_O_RCOSCHFCTL 0x00000030 // Status 0 -#define DDI_0_OSC_O_STAT0 0x00000034 +#define DDI_0_OSC_O_STAT0 0x00000034 // Status 1 -#define DDI_0_OSC_O_STAT1 0x00000038 +#define DDI_0_OSC_O_STAT1 0x00000038 // Status 2 -#define DDI_0_OSC_O_STAT2 0x0000003C +#define DDI_0_OSC_O_STAT2 0x0000003C //***************************************************************************** // @@ -102,46 +102,46 @@ // ENUMs: // 24M Internal. Only to be used through TI provided API. // 48M Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000 -#define DDI_0_OSC_CTL0_XTAL_IS_24M_M 0x80000000 -#define DDI_0_OSC_CTL0_XTAL_IS_24M_S 31 -#define DDI_0_OSC_CTL0_XTAL_IS_24M_24M 0x80000000 -#define DDI_0_OSC_CTL0_XTAL_IS_24M_48M 0x00000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_S 31 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_24M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_48M 0x00000000 // Field: [29] BYPASS_XOSC_LF_CLK_QUAL // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000 -#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M 0x20000000 -#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_S 29 +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000 +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M 0x20000000 +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_S 29 // Field: [28] BYPASS_RCOSC_LF_CLK_QUAL // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000 -#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M 0x10000000 -#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S 28 +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000 +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M 0x10000000 +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S 28 // Field: [27:26] DOUBLER_START_DURATION // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_W 2 -#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_M 0x0C000000 -#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_S 26 +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_W 2 +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_M 0x0C000000 +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_S 26 // Field: [25] DOUBLER_RESET_DURATION // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x02000000 -#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_M 0x02000000 -#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_S 25 +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x02000000 +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_M 0x02000000 +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_S 25 // Field: [22] FORCE_KICKSTART_EN // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN 0x00400000 -#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN_M 0x00400000 -#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN_S 22 +#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN 0x00400000 +#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN_M 0x00400000 +#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN_S 22 // Field: [16] ALLOW_SCLK_HF_SWITCHING // @@ -157,30 +157,30 @@ // indicated by STAT0.PENDINGSCLKHFSWITCHING) sclk_hf switching should be // disabled to prevent flash corruption. Switching should not be enabled when // running from flash. -#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING 0x00010000 -#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING_M 0x00010000 -#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING_S 16 +#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING 0x00010000 +#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING_M 0x00010000 +#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING_S 16 // Field: [14] HPOSC_MODE_EN // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_HPOSC_MODE_EN 0x00004000 -#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_M 0x00004000 -#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_S 14 +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN 0x00004000 +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_M 0x00004000 +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_S 14 // Field: [12] RCOSC_LF_TRIMMED // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x00001000 -#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_M 0x00001000 -#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_S 12 +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x00001000 +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_M 0x00001000 +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_S 12 // Field: [11] XOSC_HF_POWER_MODE // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x00000800 -#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_M 0x00000800 -#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_S 11 +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x00000800 +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_M 0x00000800 +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_S 11 // Field: [10] XOSC_LF_DIG_BYPASS // @@ -203,9 +203,9 @@ // It is recommended that either the rcosc_hf or xosc_hf (whichever is // currently active) be selected as the source in step 1 above. This provides a // faster clock change. -#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x00000400 -#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_M 0x00000400 -#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_S 10 +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x00000400 +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_M 0x00000400 +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_S 10 // Field: [9] CLK_LOSS_EN // @@ -218,9 +218,9 @@ // Clock loss detection must be disabled when changing the sclk_lf source. // STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf // source has completed. -#define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x00000200 -#define DDI_0_OSC_CTL0_CLK_LOSS_EN_M 0x00000200 -#define DDI_0_OSC_CTL0_CLK_LOSS_EN_S 9 +#define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x00000200 +#define DDI_0_OSC_CTL0_CLK_LOSS_EN_M 0x00000200 +#define DDI_0_OSC_CTL0_CLK_LOSS_EN_S 9 // Field: [8:7] ACLK_TDC_SRC_SEL // @@ -230,9 +230,9 @@ // 01: RCOSC_HF (24MHz) // 10: XOSC_HF (24MHz) // 11: Not used -#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_W 2 -#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M 0x00000180 -#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S 7 +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_W 2 +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M 0x00000180 +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S 7 // Field: [6:5] ACLK_REF_SRC_SEL // @@ -242,9 +242,9 @@ // 01: XOSC_HF derived (31.25kHz) // 10: RCOSC_LF (32kHz) // 11: XOSC_LF (32.768kHz) -#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_W 2 -#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M 0x00000060 -#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S 5 +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_W 2 +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M 0x00000060 +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S 5 // Field: [3:2] SCLK_LF_SRC_SEL // @@ -256,13 +256,13 @@ // XOSC // RCOSCHFDLF Low frequency clock derived from High Frequency // RCOSC -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_W 2 -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M 0x0000000C -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S 2 -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCLF 0x0000000C -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCLF 0x00000008 -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF 0x00000004 -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCHFDLF 0x00000000 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_W 2 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M 0x0000000C +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S 2 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCLF 0x0000000C +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCLF 0x00000008 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF 0x00000004 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCHFDLF 0x00000000 // Field: [1] SCLK_MF_SRC_SEL // @@ -271,11 +271,11 @@ // XCOSCHFDMF Medium frequency clock derived from high frequency // XOSC. // RCOSCHFDMF Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL 0x00000002 -#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_M 0x00000002 -#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_S 1 -#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_XCOSCHFDMF 0x00000002 -#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_RCOSCHFDMF 0x00000000 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL 0x00000002 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_M 0x00000002 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_S 1 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_XCOSCHFDMF 0x00000002 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_RCOSCHFDMF 0x00000000 // Field: [0] SCLK_HF_SRC_SEL // @@ -284,11 +284,11 @@ // ENUMs: // XOSC High frequency XOSC clk // RCOSC High frequency RCOSC clock -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL 0x00000001 -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M 0x00000001 -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S 0 -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC 0x00000001 -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC 0x00000000 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S 0 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC 0x00000000 //***************************************************************************** // @@ -298,23 +298,23 @@ // Field: [22:18] RCOSCHFCTRIMFRACT // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_W 5 -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_M 0x007C0000 -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_S 18 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_W 5 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_M 0x007C0000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_S 18 // Field: [17] RCOSCHFCTRIMFRACT_EN // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN 0x00020000 -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_M 0x00020000 -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_S 17 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN 0x00020000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_M 0x00020000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_S 17 // Field: [1:0] XOSC_HF_FAST_START // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_W 2 -#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_M 0x00000003 -#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_S 0 +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_W 2 +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_M 0x00000003 +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_S 0 //***************************************************************************** // @@ -324,37 +324,37 @@ // Field: [31:22] HPM_IBIAS_WAIT_CNT // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_W 10 -#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_M 0xFFC00000 -#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S 22 +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_W 10 +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_M 0xFFC00000 +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S 22 // Field: [21:16] LPM_IBIAS_WAIT_CNT // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_W 6 -#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_M 0x003F0000 -#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S 16 +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_W 6 +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_M 0x003F0000 +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S 16 // Field: [15:12] IDAC_STEP // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_W 4 -#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_M 0x0000F000 -#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S 12 +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_W 4 +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_M 0x0000F000 +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S 12 // Field: [11:6] RADC_DAC_TH // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_W 6 -#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_M 0x00000FC0 -#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_S 6 +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_W 6 +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_M 0x00000FC0 +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_S 6 // Field: [5] RADC_MODE_IS_SAR // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR 0x00000020 -#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_M 0x00000020 -#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_S 5 +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR 0x00000020 +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_M 0x00000020 +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_S 5 //***************************************************************************** // @@ -364,9 +364,9 @@ // Field: [30] AMPCOMP_REQ_MODE // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE 0x40000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_M 0x40000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S 30 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE 0x40000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_M 0x40000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S 30 // Field: [29:28] AMPCOMP_FSM_UPDATE_RATE // @@ -376,62 +376,62 @@ // 500KHZ Internal. Only to be used through TI provided API. // 1MHZ Internal. Only to be used through TI provided API. // 2MHZ Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_W 2 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_M 0x30000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_S 28 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_250KHZ 0x30000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_500KHZ 0x20000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_1MHZ 0x10000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_2MHZ 0x00000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_W 2 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_M 0x30000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_S 28 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_250KHZ 0x30000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_500KHZ 0x20000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_1MHZ 0x10000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_2MHZ 0x00000000 // Field: [27] AMPCOMP_SW_CTRL // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL 0x08000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_M 0x08000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_S 27 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL 0x08000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_M 0x08000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_S 27 // Field: [26] AMPCOMP_SW_EN // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN 0x04000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_M 0x04000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_S 26 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN 0x04000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_M 0x04000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_S 26 // Field: [23:20] IBIAS_OFFSET // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_W 4 -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M 0x00F00000 -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S 20 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M 0x00F00000 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S 20 // Field: [19:16] IBIAS_INIT // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_W 4 -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M 0x000F0000 -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S 16 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M 0x000F0000 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S 16 // Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_W 8 -#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 -#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S 8 +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_W 8 +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S 8 // Field: [7:4] CAP_STEP // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_W 4 -#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_M 0x000000F0 -#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S 4 +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_W 4 +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_M 0x000000F0 +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S 4 // Field: [3:0] IBIASCAP_HPTOLP_OL_CNT // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_W 4 -#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F -#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S 0 +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S 0 //***************************************************************************** // @@ -441,30 +441,30 @@ // Field: [23:18] HPMRAMP3_LTH // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_W 6 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M 0x00FC0000 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S 18 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M 0x00FC0000 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S 18 // Field: [15:10] HPMRAMP3_HTH // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_W 6 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M 0x0000FC00 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S 10 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M 0x0000FC00 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S 10 // Field: [9:6] IBIASCAP_LPTOHP_OL_CNT // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_W 4 -#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 -#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S 6 +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_W 4 +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S 6 // Field: [5:0] HPMRAMP1_TH // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_W 6 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_M 0x0000003F -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S 0 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_M 0x0000003F +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S 0 //***************************************************************************** // @@ -474,30 +474,30 @@ // Field: [31:26] LPMUPDATE_LTH // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_W 6 -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_M 0xFC000000 -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S 26 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_W 6 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_M 0xFC000000 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S 26 // Field: [23:18] LPMUPDATE_HTH // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_W 6 -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_M 0x00FC0000 -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S 18 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_W 6 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_M 0x00FC0000 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S 18 // Field: [15:10] ADC_COMP_AMPTH_LPM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_W 6 -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S 10 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_W 6 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S 10 // Field: [7:2] ADC_COMP_AMPTH_HPM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_W 6 -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_M 0x000000FC -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S 2 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_W 6 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_M 0x000000FC +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S 2 //***************************************************************************** // @@ -507,16 +507,16 @@ // Field: [19:16] XOSC_HF_ROW_Q12 // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_W 4 -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_M 0x000F0000 -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S 16 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_W 4 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_M 0x000F0000 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S 16 // Field: [15:0] XOSC_HF_COLUMN_Q12 // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_W 16 -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_M 0x0000FFFF -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S 0 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_W 16 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_M 0x0000FFFF +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S 0 //***************************************************************************** // @@ -526,9 +526,9 @@ // Field: [13:0] XOSC_HF_IBIASTHERM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_W 14 -#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_M 0x00003FFF -#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S 0 +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_W 14 +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_M 0x00003FFF +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S 0 //***************************************************************************** // @@ -538,9 +538,9 @@ // Field: [29] SCLK_LF_AUX_EN // // Enable 32 kHz clock to AUX_COMPB. -#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN 0x20000000 -#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_M 0x20000000 -#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_S 29 +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN 0x20000000 +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_M 0x20000000 +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_S 29 //***************************************************************************** // @@ -550,38 +550,38 @@ // Field: [24] NANOAMP_BIAS_ENABLE // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE 0x01000000 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_M 0x01000000 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_S 24 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE 0x01000000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_M 0x01000000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_S 24 // Field: [23] SPARE23 // // Software should not rely on the value of a reserved. Writing any other value // than the reset value may result in undefined behavior -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23 0x00800000 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_M 0x00800000 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_S 23 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23 0x00800000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_M 0x00800000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_S 23 // Field: [5] ADC_SH_MODE_EN // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN 0x00000020 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_M 0x00000020 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_S 5 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN 0x00000020 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_M 0x00000020 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_S 5 // Field: [4] ADC_SH_VBUF_EN // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN 0x00000010 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_M 0x00000010 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_S 4 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN 0x00000010 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_M 0x00000010 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_S 4 // Field: [1:0] ADC_IREF_CTRL // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_W 2 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_M 0x00000003 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_S 0 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_W 2 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_M 0x00000003 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_S 0 //***************************************************************************** // @@ -591,30 +591,30 @@ // Field: [9:8] PEAK_DET_ITRIM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_W 2 -#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_M 0x00000300 -#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S 8 +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_W 2 +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_M 0x00000300 +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S 8 // Field: [6] BYPASS // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_XOSCHFCTL_BYPASS 0x00000040 -#define DDI_0_OSC_XOSCHFCTL_BYPASS_M 0x00000040 -#define DDI_0_OSC_XOSCHFCTL_BYPASS_S 6 +#define DDI_0_OSC_XOSCHFCTL_BYPASS 0x00000040 +#define DDI_0_OSC_XOSCHFCTL_BYPASS_M 0x00000040 +#define DDI_0_OSC_XOSCHFCTL_BYPASS_S 6 // Field: [4:2] HP_BUF_ITRIM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_W 3 -#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_M 0x0000001C -#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S 2 +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_W 3 +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_M 0x0000001C +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S 2 // Field: [1:0] LP_BUF_ITRIM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_W 2 -#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_M 0x00000003 -#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S 0 +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_W 2 +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_M 0x00000003 +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S 0 //***************************************************************************** // @@ -624,16 +624,16 @@ // Field: [23:22] XOSCLF_REGULATOR_TRIM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_W 2 -#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_M 0x00C00000 -#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_S 22 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_W 2 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_M 0x00C00000 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_S 22 // Field: [21:18] XOSCLF_CMIRRWR_RATIO // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_W 4 -#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_M 0x003C0000 -#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_S 18 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_W 4 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_M 0x003C0000 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_S 18 // Field: [9:8] RCOSCLF_RTUNE_TRIM // @@ -643,20 +643,20 @@ // 6P5MEG Internal. Only to be used through TI provided API. // 7P0MEG Internal. Only to be used through TI provided API. // 7P5MEG Internal. Only to be used through TI provided API. -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_W 2 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M 0x00000300 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S 8 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P0MEG 0x00000300 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P5MEG 0x00000200 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P0MEG 0x00000100 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P5MEG 0x00000000 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_W 2 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M 0x00000300 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S 8 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P0MEG 0x00000300 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P5MEG 0x00000200 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P0MEG 0x00000100 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P5MEG 0x00000000 // Field: [7:0] RCOSCLF_CTUNE_TRIM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_W 8 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M 0x000000FF -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S 0 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_W 8 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M 0x000000FF +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S 0 //***************************************************************************** // @@ -666,9 +666,9 @@ // Field: [15:8] RCOSCHF_CTRIM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_W 8 -#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M 0x0000FF00 -#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S 8 +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_W 8 +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M 0x0000FF00 +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S 8 //***************************************************************************** // @@ -685,13 +685,13 @@ // XOSC // RCOSCHFDLF Low frequency clock derived from High Frequency // RCOSC -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_W 2 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_M 0x60000000 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_S 29 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCLF 0x60000000 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCLF 0x40000000 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCHFDLF 0x20000000 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCHFDLF 0x00000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_W 2 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_M 0x60000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_S 29 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCLF 0x60000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCLF 0x40000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCHFDLF 0x20000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCHFDLF 0x00000000 // Field: [28] SCLK_HF_SRC // @@ -699,67 +699,67 @@ // ENUMs: // XOSC High frequency XOSC // RCOSC High frequency RCOSC clock -#define DDI_0_OSC_STAT0_SCLK_HF_SRC 0x10000000 -#define DDI_0_OSC_STAT0_SCLK_HF_SRC_M 0x10000000 -#define DDI_0_OSC_STAT0_SCLK_HF_SRC_S 28 -#define DDI_0_OSC_STAT0_SCLK_HF_SRC_XOSC 0x10000000 -#define DDI_0_OSC_STAT0_SCLK_HF_SRC_RCOSC 0x00000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_M 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_S 28 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_XOSC 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_RCOSC 0x00000000 // Field: [22] RCOSC_HF_EN // // RCOSC_HF_EN -#define DDI_0_OSC_STAT0_RCOSC_HF_EN 0x00400000 -#define DDI_0_OSC_STAT0_RCOSC_HF_EN_M 0x00400000 -#define DDI_0_OSC_STAT0_RCOSC_HF_EN_S 22 +#define DDI_0_OSC_STAT0_RCOSC_HF_EN 0x00400000 +#define DDI_0_OSC_STAT0_RCOSC_HF_EN_M 0x00400000 +#define DDI_0_OSC_STAT0_RCOSC_HF_EN_S 22 // Field: [21] RCOSC_LF_EN // // RCOSC_LF_EN -#define DDI_0_OSC_STAT0_RCOSC_LF_EN 0x00200000 -#define DDI_0_OSC_STAT0_RCOSC_LF_EN_M 0x00200000 -#define DDI_0_OSC_STAT0_RCOSC_LF_EN_S 21 +#define DDI_0_OSC_STAT0_RCOSC_LF_EN 0x00200000 +#define DDI_0_OSC_STAT0_RCOSC_LF_EN_M 0x00200000 +#define DDI_0_OSC_STAT0_RCOSC_LF_EN_S 21 // Field: [20] XOSC_LF_EN // // XOSC_LF_EN -#define DDI_0_OSC_STAT0_XOSC_LF_EN 0x00100000 -#define DDI_0_OSC_STAT0_XOSC_LF_EN_M 0x00100000 -#define DDI_0_OSC_STAT0_XOSC_LF_EN_S 20 +#define DDI_0_OSC_STAT0_XOSC_LF_EN 0x00100000 +#define DDI_0_OSC_STAT0_XOSC_LF_EN_M 0x00100000 +#define DDI_0_OSC_STAT0_XOSC_LF_EN_S 20 // Field: [19] CLK_DCDC_RDY // // CLK_DCDC_RDY -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY 0x00080000 -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_M 0x00080000 -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_S 19 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY 0x00080000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_M 0x00080000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_S 19 // Field: [18] CLK_DCDC_RDY_ACK // // CLK_DCDC_RDY_ACK -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK 0x00040000 -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_M 0x00040000 -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_S 18 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK 0x00040000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_M 0x00040000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_S 18 // Field: [17] SCLK_HF_LOSS // // Indicates sclk_hf is lost -#define DDI_0_OSC_STAT0_SCLK_HF_LOSS 0x00020000 -#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_M 0x00020000 -#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_S 17 +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS 0x00020000 +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_M 0x00020000 +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_S 17 // Field: [16] SCLK_LF_LOSS // // Indicates sclk_lf is lost -#define DDI_0_OSC_STAT0_SCLK_LF_LOSS 0x00010000 -#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_M 0x00010000 -#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_S 16 +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS 0x00010000 +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_M 0x00010000 +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_S 16 // Field: [15] XOSC_HF_EN // // Indicates that XOSC_HF is enabled. -#define DDI_0_OSC_STAT0_XOSC_HF_EN 0x00008000 -#define DDI_0_OSC_STAT0_XOSC_HF_EN_M 0x00008000 -#define DDI_0_OSC_STAT0_XOSC_HF_EN_S 15 +#define DDI_0_OSC_STAT0_XOSC_HF_EN 0x00008000 +#define DDI_0_OSC_STAT0_XOSC_HF_EN_M 0x00008000 +#define DDI_0_OSC_STAT0_XOSC_HF_EN_S 15 // Field: [13] XB_48M_CLK_EN // @@ -767,51 +767,51 @@ // // It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler // bypass for the 48MHz crystal). -#define DDI_0_OSC_STAT0_XB_48M_CLK_EN 0x00002000 -#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_M 0x00002000 -#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_S 13 +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN 0x00002000 +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_M 0x00002000 +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_S 13 // Field: [11] XOSC_HF_LP_BUF_EN // // XOSC_HF_LP_BUF_EN -#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN 0x00000800 -#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_M 0x00000800 -#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_S 11 +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN 0x00000800 +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_M 0x00000800 +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_S 11 // Field: [10] XOSC_HF_HP_BUF_EN // // XOSC_HF_HP_BUF_EN -#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN 0x00000400 -#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_M 0x00000400 -#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_S 10 +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN 0x00000400 +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_M 0x00000400 +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_S 10 // Field: [8] ADC_THMET // // ADC_THMET -#define DDI_0_OSC_STAT0_ADC_THMET 0x00000100 -#define DDI_0_OSC_STAT0_ADC_THMET_M 0x00000100 -#define DDI_0_OSC_STAT0_ADC_THMET_S 8 +#define DDI_0_OSC_STAT0_ADC_THMET 0x00000100 +#define DDI_0_OSC_STAT0_ADC_THMET_M 0x00000100 +#define DDI_0_OSC_STAT0_ADC_THMET_S 8 // Field: [7] ADC_DATA_READY // // indicates when adc_data is ready. -#define DDI_0_OSC_STAT0_ADC_DATA_READY 0x00000080 -#define DDI_0_OSC_STAT0_ADC_DATA_READY_M 0x00000080 -#define DDI_0_OSC_STAT0_ADC_DATA_READY_S 7 +#define DDI_0_OSC_STAT0_ADC_DATA_READY 0x00000080 +#define DDI_0_OSC_STAT0_ADC_DATA_READY_M 0x00000080 +#define DDI_0_OSC_STAT0_ADC_DATA_READY_S 7 // Field: [6:1] ADC_DATA // // adc_data -#define DDI_0_OSC_STAT0_ADC_DATA_W 6 -#define DDI_0_OSC_STAT0_ADC_DATA_M 0x0000007E -#define DDI_0_OSC_STAT0_ADC_DATA_S 1 +#define DDI_0_OSC_STAT0_ADC_DATA_W 6 +#define DDI_0_OSC_STAT0_ADC_DATA_M 0x0000007E +#define DDI_0_OSC_STAT0_ADC_DATA_S 1 // Field: [0] PENDINGSCLKHFSWITCHING // // Indicates when sclk_hf is ready to be switched -#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING 0x00000001 -#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M 0x00000001 -#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S 0 +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING 0x00000001 +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M 0x00000001 +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S 0 //***************************************************************************** // @@ -837,24 +837,24 @@ // HPM_RAMP1 HPM_RAMP1 // INITIALIZATION INITIALIZATION // RESET RESET -#define DDI_0_OSC_STAT1_RAMPSTATE_W 4 -#define DDI_0_OSC_STAT1_RAMPSTATE_M 0xF0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_S 28 -#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START_SETTLE 0xE0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START 0xD0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_DUMMY_TO_INIT_1 0xC0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_DEC_W_MEASURE 0xB0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_INC 0xA0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_LPM_UPDATE 0x90000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_DEC_W_MEASURE 0x80000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_CAP_UPDATE 0x70000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_INCREMENT 0x60000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_UPDATE 0x50000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP3 0x40000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP2 0x30000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP1 0x20000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_INITIALIZATION 0x10000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_RESET 0x00000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_W 4 +#define DDI_0_OSC_STAT1_RAMPSTATE_M 0xF0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_S 28 +#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START_SETTLE 0xE0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START 0xD0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_DUMMY_TO_INIT_1 0xC0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_DEC_W_MEASURE 0xB0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_INC 0xA0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_LPM_UPDATE 0x90000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_DEC_W_MEASURE 0x80000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_CAP_UPDATE 0x70000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_INCREMENT 0x60000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_UPDATE 0x50000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP3 0x40000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP2 0x30000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP1 0x20000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_INITIALIZATION 0x10000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_RESET 0x00000000 // Field: [27:22] HPM_UPDATE_AMP // @@ -865,9 +865,9 @@ // would indicate that the amplitude of the crystal is approximately 480 mV. // To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero // value. -#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_W 6 -#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M 0x0FC00000 -#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S 22 +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_W 6 +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M 0x0FC00000 +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S 22 // Field: [21:16] LPM_UPDATE_AMP // @@ -878,121 +878,121 @@ // indicate that the amplitude of the crystal is approximately 480 mV. To // enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero // value. -#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_W 6 -#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_M 0x003F0000 -#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_S 16 +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_W 6 +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_M 0x003F0000 +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_S 16 // Field: [15] FORCE_RCOSC_HF // // force_rcosc_hf -#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF 0x00008000 -#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_M 0x00008000 -#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_S 15 +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF 0x00008000 +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_M 0x00008000 +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_S 15 // Field: [14] SCLK_HF_EN // // SCLK_HF_EN -#define DDI_0_OSC_STAT1_SCLK_HF_EN 0x00004000 -#define DDI_0_OSC_STAT1_SCLK_HF_EN_M 0x00004000 -#define DDI_0_OSC_STAT1_SCLK_HF_EN_S 14 +#define DDI_0_OSC_STAT1_SCLK_HF_EN 0x00004000 +#define DDI_0_OSC_STAT1_SCLK_HF_EN_M 0x00004000 +#define DDI_0_OSC_STAT1_SCLK_HF_EN_S 14 // Field: [13] SCLK_MF_EN // // SCLK_MF_EN -#define DDI_0_OSC_STAT1_SCLK_MF_EN 0x00002000 -#define DDI_0_OSC_STAT1_SCLK_MF_EN_M 0x00002000 -#define DDI_0_OSC_STAT1_SCLK_MF_EN_S 13 +#define DDI_0_OSC_STAT1_SCLK_MF_EN 0x00002000 +#define DDI_0_OSC_STAT1_SCLK_MF_EN_M 0x00002000 +#define DDI_0_OSC_STAT1_SCLK_MF_EN_S 13 // Field: [12] ACLK_ADC_EN // // ACLK_ADC_EN -#define DDI_0_OSC_STAT1_ACLK_ADC_EN 0x00001000 -#define DDI_0_OSC_STAT1_ACLK_ADC_EN_M 0x00001000 -#define DDI_0_OSC_STAT1_ACLK_ADC_EN_S 12 +#define DDI_0_OSC_STAT1_ACLK_ADC_EN 0x00001000 +#define DDI_0_OSC_STAT1_ACLK_ADC_EN_M 0x00001000 +#define DDI_0_OSC_STAT1_ACLK_ADC_EN_S 12 // Field: [11] ACLK_TDC_EN // // ACLK_TDC_EN -#define DDI_0_OSC_STAT1_ACLK_TDC_EN 0x00000800 -#define DDI_0_OSC_STAT1_ACLK_TDC_EN_M 0x00000800 -#define DDI_0_OSC_STAT1_ACLK_TDC_EN_S 11 +#define DDI_0_OSC_STAT1_ACLK_TDC_EN 0x00000800 +#define DDI_0_OSC_STAT1_ACLK_TDC_EN_M 0x00000800 +#define DDI_0_OSC_STAT1_ACLK_TDC_EN_S 11 // Field: [10] ACLK_REF_EN // // ACLK_REF_EN -#define DDI_0_OSC_STAT1_ACLK_REF_EN 0x00000400 -#define DDI_0_OSC_STAT1_ACLK_REF_EN_M 0x00000400 -#define DDI_0_OSC_STAT1_ACLK_REF_EN_S 10 +#define DDI_0_OSC_STAT1_ACLK_REF_EN 0x00000400 +#define DDI_0_OSC_STAT1_ACLK_REF_EN_M 0x00000400 +#define DDI_0_OSC_STAT1_ACLK_REF_EN_S 10 // Field: [9] CLK_CHP_EN // // CLK_CHP_EN -#define DDI_0_OSC_STAT1_CLK_CHP_EN 0x00000200 -#define DDI_0_OSC_STAT1_CLK_CHP_EN_M 0x00000200 -#define DDI_0_OSC_STAT1_CLK_CHP_EN_S 9 +#define DDI_0_OSC_STAT1_CLK_CHP_EN 0x00000200 +#define DDI_0_OSC_STAT1_CLK_CHP_EN_M 0x00000200 +#define DDI_0_OSC_STAT1_CLK_CHP_EN_S 9 // Field: [8] CLK_DCDC_EN // // CLK_DCDC_EN -#define DDI_0_OSC_STAT1_CLK_DCDC_EN 0x00000100 -#define DDI_0_OSC_STAT1_CLK_DCDC_EN_M 0x00000100 -#define DDI_0_OSC_STAT1_CLK_DCDC_EN_S 8 +#define DDI_0_OSC_STAT1_CLK_DCDC_EN 0x00000100 +#define DDI_0_OSC_STAT1_CLK_DCDC_EN_M 0x00000100 +#define DDI_0_OSC_STAT1_CLK_DCDC_EN_S 8 // Field: [7] SCLK_HF_GOOD // // SCLK_HF_GOOD -#define DDI_0_OSC_STAT1_SCLK_HF_GOOD 0x00000080 -#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_M 0x00000080 -#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_S 7 +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD 0x00000080 +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_M 0x00000080 +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_S 7 // Field: [6] SCLK_MF_GOOD // // SCLK_MF_GOOD -#define DDI_0_OSC_STAT1_SCLK_MF_GOOD 0x00000040 -#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_M 0x00000040 -#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_S 6 +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD 0x00000040 +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_M 0x00000040 +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_S 6 // Field: [5] SCLK_LF_GOOD // // SCLK_LF_GOOD -#define DDI_0_OSC_STAT1_SCLK_LF_GOOD 0x00000020 -#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_M 0x00000020 -#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_S 5 +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD 0x00000020 +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_M 0x00000020 +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_S 5 // Field: [4] ACLK_ADC_GOOD // // ACLK_ADC_GOOD -#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD 0x00000010 -#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_M 0x00000010 -#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_S 4 +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD 0x00000010 +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_M 0x00000010 +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_S 4 // Field: [3] ACLK_TDC_GOOD // // ACLK_TDC_GOOD -#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD 0x00000008 -#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_M 0x00000008 -#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_S 3 +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD 0x00000008 +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_M 0x00000008 +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_S 3 // Field: [2] ACLK_REF_GOOD // // ACLK_REF_GOOD -#define DDI_0_OSC_STAT1_ACLK_REF_GOOD 0x00000004 -#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_M 0x00000004 -#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_S 2 +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD 0x00000004 +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_M 0x00000004 +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_S 2 // Field: [1] CLK_CHP_GOOD // // CLK_CHP_GOOD -#define DDI_0_OSC_STAT1_CLK_CHP_GOOD 0x00000002 -#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_M 0x00000002 -#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_S 1 +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD 0x00000002 +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_M 0x00000002 +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_S 1 // Field: [0] CLK_DCDC_GOOD // // CLK_DCDC_GOOD -#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD 0x00000001 -#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_M 0x00000001 -#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_S 0 +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD 0x00000001 +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_M 0x00000001 +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_S 0 //***************************************************************************** // @@ -1003,69 +1003,68 @@ // // DC Bias read by RADC during SAR mode // The value is an unsigned integer. It is used for debug only. -#define DDI_0_OSC_STAT2_ADC_DCBIAS_W 6 -#define DDI_0_OSC_STAT2_ADC_DCBIAS_M 0xFC000000 -#define DDI_0_OSC_STAT2_ADC_DCBIAS_S 26 +#define DDI_0_OSC_STAT2_ADC_DCBIAS_W 6 +#define DDI_0_OSC_STAT2_ADC_DCBIAS_M 0xFC000000 +#define DDI_0_OSC_STAT2_ADC_DCBIAS_S 26 // Field: [25] HPM_RAMP1_THMET // // Indication of threshold is met for hpm_ramp1 -#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET 0x02000000 -#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_M 0x02000000 -#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_S 25 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET 0x02000000 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_M 0x02000000 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_S 25 // Field: [24] HPM_RAMP2_THMET // // Indication of threshold is met for hpm_ramp2 -#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET 0x01000000 -#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_M 0x01000000 -#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_S 24 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET 0x01000000 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_M 0x01000000 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_S 24 // Field: [23] HPM_RAMP3_THMET // // Indication of threshold is met for hpm_ramp3 -#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET 0x00800000 -#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_M 0x00800000 -#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_S 23 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET 0x00800000 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_M 0x00800000 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_S 23 // Field: [15:12] RAMPSTATE // // xosc_hf amplitude compensation FSM // // This is identical to STAT1.RAMPSTATE. See that description for encoding. -#define DDI_0_OSC_STAT2_RAMPSTATE_W 4 -#define DDI_0_OSC_STAT2_RAMPSTATE_M 0x0000F000 -#define DDI_0_OSC_STAT2_RAMPSTATE_S 12 +#define DDI_0_OSC_STAT2_RAMPSTATE_W 4 +#define DDI_0_OSC_STAT2_RAMPSTATE_M 0x0000F000 +#define DDI_0_OSC_STAT2_RAMPSTATE_S 12 // Field: [3] AMPCOMP_REQ // // ampcomp_req -#define DDI_0_OSC_STAT2_AMPCOMP_REQ 0x00000008 -#define DDI_0_OSC_STAT2_AMPCOMP_REQ_M 0x00000008 -#define DDI_0_OSC_STAT2_AMPCOMP_REQ_S 3 +#define DDI_0_OSC_STAT2_AMPCOMP_REQ 0x00000008 +#define DDI_0_OSC_STAT2_AMPCOMP_REQ_M 0x00000008 +#define DDI_0_OSC_STAT2_AMPCOMP_REQ_S 3 // Field: [2] XOSC_HF_AMPGOOD // // amplitude of xosc_hf is within the required threshold (set by DDI). Not used // for anything just for debug/status -#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD 0x00000004 -#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_M 0x00000004 -#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_S 2 +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD 0x00000004 +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_M 0x00000004 +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_S 2 // Field: [1] XOSC_HF_FREQGOOD // // frequency of xosc_hf is good to use for the digital clocks -#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD 0x00000002 -#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_M 0x00000002 -#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_S 1 +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD 0x00000002 +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_M 0x00000002 +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_S 1 // Field: [0] XOSC_HF_RF_FREQGOOD // // frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio // operations. Used for SW to start synthesizer. -#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD 0x00000001 -#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_M 0x00000001 -#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_S 0 - +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD 0x00000001 +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_M 0x00000001 +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_S 0 #endif // __DDI_0_OSC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_device.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_device.h index c8c3e6c..c4f92e4 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_device.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_device.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_device.h -* Revised: 2017-06-21 10:06:25 +0200 (Wed, 21 Jun 2017) -* Revision: 49177 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_device.h + * Revised: 2017-06-21 10:06:25 +0200 (Wed, 21 Jun 2017) + * Revision: 49177 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_DEVICE_H__ #define __HW_DEVICE_H__ @@ -41,128 +41,128 @@ #ifdef CC_GET_CHIP_PACKAGE - #if ( CC_GET_CHIP_PACKAGE == 0x7 ) - //***************************************************************************** - // - // The following are defines for edge detection on wake up events for the - // CC26xx 7x7 packaged device. - // - //***************************************************************************** - #define AON_EVENT_DIO0 0x3F - #define AON_EVENT_DIO1 17 - #define AON_EVENT_DIO2 16 - #define AON_EVENT_DIO3 15 - #define AON_EVENT_DIO4 14 - #define AON_EVENT_DIO5 13 - #define AON_EVENT_DIO6 12 - #define AON_EVENT_DIO7 11 - #define AON_EVENT_DIO8 10 - #define AON_EVENT_DIO9 9 - #define AON_EVENT_DIO10 8 - #define AON_EVENT_DIO11 7 - #define AON_EVENT_DIO12 6 - #define AON_EVENT_DIO13 5 - #define AON_EVENT_DIO14 4 - #define AON_EVENT_DIO15 3 - #define AON_EVENT_DIO16 2 - #define AON_EVENT_DIO17 1 - #define AON_EVENT_DIO18 31 - #define AON_EVENT_DIO19 30 - #define AON_EVENT_DIO20 29 - #define AON_EVENT_DIO21 28 - #define AON_EVENT_DIO22 27 - #define AON_EVENT_DIO23 26 - #define AON_EVENT_DIO24 25 - #define AON_EVENT_DIO25 24 - #define AON_EVENT_DIO26 23 - #define AON_EVENT_DIO27 22 - #define AON_EVENT_DIO28 21 - #define AON_EVENT_DIO29 20 - #define AON_EVENT_DIO30 19 - #define AON_EVENT_DIO31 0x3F - #endif // ( CC_GET_CHIP_PACKAGE == 0x7 ) +#if (CC_GET_CHIP_PACKAGE == 0x7) +//***************************************************************************** +// +// The following are defines for edge detection on wake up events for the +// CC26xx 7x7 packaged device. +// +//***************************************************************************** +#define AON_EVENT_DIO0 0x3F +#define AON_EVENT_DIO1 17 +#define AON_EVENT_DIO2 16 +#define AON_EVENT_DIO3 15 +#define AON_EVENT_DIO4 14 +#define AON_EVENT_DIO5 13 +#define AON_EVENT_DIO6 12 +#define AON_EVENT_DIO7 11 +#define AON_EVENT_DIO8 10 +#define AON_EVENT_DIO9 9 +#define AON_EVENT_DIO10 8 +#define AON_EVENT_DIO11 7 +#define AON_EVENT_DIO12 6 +#define AON_EVENT_DIO13 5 +#define AON_EVENT_DIO14 4 +#define AON_EVENT_DIO15 3 +#define AON_EVENT_DIO16 2 +#define AON_EVENT_DIO17 1 +#define AON_EVENT_DIO18 31 +#define AON_EVENT_DIO19 30 +#define AON_EVENT_DIO20 29 +#define AON_EVENT_DIO21 28 +#define AON_EVENT_DIO22 27 +#define AON_EVENT_DIO23 26 +#define AON_EVENT_DIO24 25 +#define AON_EVENT_DIO25 24 +#define AON_EVENT_DIO26 23 +#define AON_EVENT_DIO27 22 +#define AON_EVENT_DIO28 21 +#define AON_EVENT_DIO29 20 +#define AON_EVENT_DIO30 19 +#define AON_EVENT_DIO31 0x3F +#endif // ( CC_GET_CHIP_PACKAGE == 0x7 ) - #if ( CC_GET_CHIP_PACKAGE == 0x5 ) - //***************************************************************************** - // - // The following are defines for edge detection on wake up events for the - // CC26xx 5x5 packaged device. - // - //***************************************************************************** - #define AON_EVENT_DIO0 15 - #define AON_EVENT_DIO1 14 - #define AON_EVENT_DIO2 13 - #define AON_EVENT_DIO3 12 - #define AON_EVENT_DIO4 11 - #define AON_EVENT_DIO5 2 - #define AON_EVENT_DIO6 1 - #define AON_EVENT_DIO7 26 - #define AON_EVENT_DIO8 25 - #define AON_EVENT_DIO9 23 - #define AON_EVENT_DIO10 24 - #define AON_EVENT_DIO11 22 - #define AON_EVENT_DIO12 21 - #define AON_EVENT_DIO13 20 - #define AON_EVENT_DIO14 19 - #define AON_EVENT_DIO15 0x3F - #define AON_EVENT_DIO16 0x3F - #define AON_EVENT_DIO17 0x3F - #define AON_EVENT_DIO18 0x3F - #define AON_EVENT_DIO19 0x3F - #define AON_EVENT_DIO20 0x3F - #define AON_EVENT_DIO21 0x3F - #define AON_EVENT_DIO22 0x3F - #define AON_EVENT_DIO23 0x3F - #define AON_EVENT_DIO24 0x3F - #define AON_EVENT_DIO25 0x3F - #define AON_EVENT_DIO26 0x3F - #define AON_EVENT_DIO27 0x3F - #define AON_EVENT_DIO28 0x3F - #define AON_EVENT_DIO29 0x3F - #define AON_EVENT_DIO30 0x3F - #define AON_EVENT_DIO31 0x3F - #endif // ( CC_GET_CHIP_PACKAGE == 0x5 ) +#if (CC_GET_CHIP_PACKAGE == 0x5) +//***************************************************************************** +// +// The following are defines for edge detection on wake up events for the +// CC26xx 5x5 packaged device. +// +//***************************************************************************** +#define AON_EVENT_DIO0 15 +#define AON_EVENT_DIO1 14 +#define AON_EVENT_DIO2 13 +#define AON_EVENT_DIO3 12 +#define AON_EVENT_DIO4 11 +#define AON_EVENT_DIO5 2 +#define AON_EVENT_DIO6 1 +#define AON_EVENT_DIO7 26 +#define AON_EVENT_DIO8 25 +#define AON_EVENT_DIO9 23 +#define AON_EVENT_DIO10 24 +#define AON_EVENT_DIO11 22 +#define AON_EVENT_DIO12 21 +#define AON_EVENT_DIO13 20 +#define AON_EVENT_DIO14 19 +#define AON_EVENT_DIO15 0x3F +#define AON_EVENT_DIO16 0x3F +#define AON_EVENT_DIO17 0x3F +#define AON_EVENT_DIO18 0x3F +#define AON_EVENT_DIO19 0x3F +#define AON_EVENT_DIO20 0x3F +#define AON_EVENT_DIO21 0x3F +#define AON_EVENT_DIO22 0x3F +#define AON_EVENT_DIO23 0x3F +#define AON_EVENT_DIO24 0x3F +#define AON_EVENT_DIO25 0x3F +#define AON_EVENT_DIO26 0x3F +#define AON_EVENT_DIO27 0x3F +#define AON_EVENT_DIO28 0x3F +#define AON_EVENT_DIO29 0x3F +#define AON_EVENT_DIO30 0x3F +#define AON_EVENT_DIO31 0x3F +#endif // ( CC_GET_CHIP_PACKAGE == 0x5 ) - #if ( CC_GET_CHIP_PACKAGE == 0x4 ) - //***************************************************************************** - // - // The following are defines for edge detection on wake up events for the - // CC26xx 4x4 packaged device. - // - //***************************************************************************** - #define AON_EVENT_DIO0 13 - #define AON_EVENT_DIO1 12 - #define AON_EVENT_DIO2 11 - #define AON_EVENT_DIO3 2 - #define AON_EVENT_DIO4 1 - #define AON_EVENT_DIO5 26 - #define AON_EVENT_DIO6 25 - #define AON_EVENT_DIO7 24 - #define AON_EVENT_DIO8 23 - #define AON_EVENT_DIO9 22 - #define AON_EVENT_DIO10 0x3F - #define AON_EVENT_DIO11 0x3F - #define AON_EVENT_DIO12 0x3F - #define AON_EVENT_DIO13 0x3F - #define AON_EVENT_DIO14 0x3F - #define AON_EVENT_DIO15 0x3F - #define AON_EVENT_DIO16 0x3F - #define AON_EVENT_DIO17 0x3F - #define AON_EVENT_DIO18 0x3F - #define AON_EVENT_DIO19 0x3F - #define AON_EVENT_DIO20 0x3F - #define AON_EVENT_DIO21 0x3F - #define AON_EVENT_DIO22 0x3F - #define AON_EVENT_DIO23 0x3F - #define AON_EVENT_DIO24 0x3F - #define AON_EVENT_DIO25 0x3F - #define AON_EVENT_DIO26 0x3F - #define AON_EVENT_DIO27 0x3F - #define AON_EVENT_DIO28 0x3F - #define AON_EVENT_DIO29 0x3F - #define AON_EVENT_DIO30 0x3F - #define AON_EVENT_DIO31 0x3F - #endif // ( CC_GET_CHIP_PACKAGE == 0x4 ) +#if (CC_GET_CHIP_PACKAGE == 0x4) +//***************************************************************************** +// +// The following are defines for edge detection on wake up events for the +// CC26xx 4x4 packaged device. +// +//***************************************************************************** +#define AON_EVENT_DIO0 13 +#define AON_EVENT_DIO1 12 +#define AON_EVENT_DIO2 11 +#define AON_EVENT_DIO3 2 +#define AON_EVENT_DIO4 1 +#define AON_EVENT_DIO5 26 +#define AON_EVENT_DIO6 25 +#define AON_EVENT_DIO7 24 +#define AON_EVENT_DIO8 23 +#define AON_EVENT_DIO9 22 +#define AON_EVENT_DIO10 0x3F +#define AON_EVENT_DIO11 0x3F +#define AON_EVENT_DIO12 0x3F +#define AON_EVENT_DIO13 0x3F +#define AON_EVENT_DIO14 0x3F +#define AON_EVENT_DIO15 0x3F +#define AON_EVENT_DIO16 0x3F +#define AON_EVENT_DIO17 0x3F +#define AON_EVENT_DIO18 0x3F +#define AON_EVENT_DIO19 0x3F +#define AON_EVENT_DIO20 0x3F +#define AON_EVENT_DIO21 0x3F +#define AON_EVENT_DIO22 0x3F +#define AON_EVENT_DIO23 0x3F +#define AON_EVENT_DIO24 0x3F +#define AON_EVENT_DIO25 0x3F +#define AON_EVENT_DIO26 0x3F +#define AON_EVENT_DIO27 0x3F +#define AON_EVENT_DIO28 0x3F +#define AON_EVENT_DIO29 0x3F +#define AON_EVENT_DIO30 0x3F +#define AON_EVENT_DIO31 0x3F +#endif // ( CC_GET_CHIP_PACKAGE == 0x4 ) #endif // defined( CC_GET_CHIP_PACKAGE ) #endif // __HW_DEVICE_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_event.h index 288b54b..8635b19 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_event.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_event.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_event_h -* Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) -* Revision: 48904 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_event_h + * Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) + * Revision: 48904 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_EVENT_H__ #define __HW_EVENT_H__ @@ -44,292 +44,292 @@ // //***************************************************************************** // Output Selection for CPU Interrupt 0 -#define EVENT_O_CPUIRQSEL0 0x00000000 +#define EVENT_O_CPUIRQSEL0 0x00000000 // Output Selection for CPU Interrupt 1 -#define EVENT_O_CPUIRQSEL1 0x00000004 +#define EVENT_O_CPUIRQSEL1 0x00000004 // Output Selection for CPU Interrupt 2 -#define EVENT_O_CPUIRQSEL2 0x00000008 +#define EVENT_O_CPUIRQSEL2 0x00000008 // Output Selection for CPU Interrupt 3 -#define EVENT_O_CPUIRQSEL3 0x0000000C +#define EVENT_O_CPUIRQSEL3 0x0000000C // Output Selection for CPU Interrupt 4 -#define EVENT_O_CPUIRQSEL4 0x00000010 +#define EVENT_O_CPUIRQSEL4 0x00000010 // Output Selection for CPU Interrupt 5 -#define EVENT_O_CPUIRQSEL5 0x00000014 +#define EVENT_O_CPUIRQSEL5 0x00000014 // Output Selection for CPU Interrupt 6 -#define EVENT_O_CPUIRQSEL6 0x00000018 +#define EVENT_O_CPUIRQSEL6 0x00000018 // Output Selection for CPU Interrupt 7 -#define EVENT_O_CPUIRQSEL7 0x0000001C +#define EVENT_O_CPUIRQSEL7 0x0000001C // Output Selection for CPU Interrupt 8 -#define EVENT_O_CPUIRQSEL8 0x00000020 +#define EVENT_O_CPUIRQSEL8 0x00000020 // Output Selection for CPU Interrupt 9 -#define EVENT_O_CPUIRQSEL9 0x00000024 +#define EVENT_O_CPUIRQSEL9 0x00000024 // Output Selection for CPU Interrupt 10 -#define EVENT_O_CPUIRQSEL10 0x00000028 +#define EVENT_O_CPUIRQSEL10 0x00000028 // Output Selection for CPU Interrupt 11 -#define EVENT_O_CPUIRQSEL11 0x0000002C +#define EVENT_O_CPUIRQSEL11 0x0000002C // Output Selection for CPU Interrupt 12 -#define EVENT_O_CPUIRQSEL12 0x00000030 +#define EVENT_O_CPUIRQSEL12 0x00000030 // Output Selection for CPU Interrupt 13 -#define EVENT_O_CPUIRQSEL13 0x00000034 +#define EVENT_O_CPUIRQSEL13 0x00000034 // Output Selection for CPU Interrupt 14 -#define EVENT_O_CPUIRQSEL14 0x00000038 +#define EVENT_O_CPUIRQSEL14 0x00000038 // Output Selection for CPU Interrupt 15 -#define EVENT_O_CPUIRQSEL15 0x0000003C +#define EVENT_O_CPUIRQSEL15 0x0000003C // Output Selection for CPU Interrupt 16 -#define EVENT_O_CPUIRQSEL16 0x00000040 +#define EVENT_O_CPUIRQSEL16 0x00000040 // Output Selection for CPU Interrupt 17 -#define EVENT_O_CPUIRQSEL17 0x00000044 +#define EVENT_O_CPUIRQSEL17 0x00000044 // Output Selection for CPU Interrupt 18 -#define EVENT_O_CPUIRQSEL18 0x00000048 +#define EVENT_O_CPUIRQSEL18 0x00000048 // Output Selection for CPU Interrupt 19 -#define EVENT_O_CPUIRQSEL19 0x0000004C +#define EVENT_O_CPUIRQSEL19 0x0000004C // Output Selection for CPU Interrupt 20 -#define EVENT_O_CPUIRQSEL20 0x00000050 +#define EVENT_O_CPUIRQSEL20 0x00000050 // Output Selection for CPU Interrupt 21 -#define EVENT_O_CPUIRQSEL21 0x00000054 +#define EVENT_O_CPUIRQSEL21 0x00000054 // Output Selection for CPU Interrupt 22 -#define EVENT_O_CPUIRQSEL22 0x00000058 +#define EVENT_O_CPUIRQSEL22 0x00000058 // Output Selection for CPU Interrupt 23 -#define EVENT_O_CPUIRQSEL23 0x0000005C +#define EVENT_O_CPUIRQSEL23 0x0000005C // Output Selection for CPU Interrupt 24 -#define EVENT_O_CPUIRQSEL24 0x00000060 +#define EVENT_O_CPUIRQSEL24 0x00000060 // Output Selection for CPU Interrupt 25 -#define EVENT_O_CPUIRQSEL25 0x00000064 +#define EVENT_O_CPUIRQSEL25 0x00000064 // Output Selection for CPU Interrupt 26 -#define EVENT_O_CPUIRQSEL26 0x00000068 +#define EVENT_O_CPUIRQSEL26 0x00000068 // Output Selection for CPU Interrupt 27 -#define EVENT_O_CPUIRQSEL27 0x0000006C +#define EVENT_O_CPUIRQSEL27 0x0000006C // Output Selection for CPU Interrupt 28 -#define EVENT_O_CPUIRQSEL28 0x00000070 +#define EVENT_O_CPUIRQSEL28 0x00000070 // Output Selection for CPU Interrupt 29 -#define EVENT_O_CPUIRQSEL29 0x00000074 +#define EVENT_O_CPUIRQSEL29 0x00000074 // Output Selection for CPU Interrupt 30 -#define EVENT_O_CPUIRQSEL30 0x00000078 +#define EVENT_O_CPUIRQSEL30 0x00000078 // Output Selection for CPU Interrupt 31 -#define EVENT_O_CPUIRQSEL31 0x0000007C +#define EVENT_O_CPUIRQSEL31 0x0000007C // Output Selection for CPU Interrupt 32 -#define EVENT_O_CPUIRQSEL32 0x00000080 +#define EVENT_O_CPUIRQSEL32 0x00000080 // Output Selection for CPU Interrupt 33 -#define EVENT_O_CPUIRQSEL33 0x00000084 +#define EVENT_O_CPUIRQSEL33 0x00000084 // Output Selection for RFC Event 0 -#define EVENT_O_RFCSEL0 0x00000100 +#define EVENT_O_RFCSEL0 0x00000100 // Output Selection for RFC Event 1 -#define EVENT_O_RFCSEL1 0x00000104 +#define EVENT_O_RFCSEL1 0x00000104 // Output Selection for RFC Event 2 -#define EVENT_O_RFCSEL2 0x00000108 +#define EVENT_O_RFCSEL2 0x00000108 // Output Selection for RFC Event 3 -#define EVENT_O_RFCSEL3 0x0000010C +#define EVENT_O_RFCSEL3 0x0000010C // Output Selection for RFC Event 4 -#define EVENT_O_RFCSEL4 0x00000110 +#define EVENT_O_RFCSEL4 0x00000110 // Output Selection for RFC Event 5 -#define EVENT_O_RFCSEL5 0x00000114 +#define EVENT_O_RFCSEL5 0x00000114 // Output Selection for RFC Event 6 -#define EVENT_O_RFCSEL6 0x00000118 +#define EVENT_O_RFCSEL6 0x00000118 // Output Selection for RFC Event 7 -#define EVENT_O_RFCSEL7 0x0000011C +#define EVENT_O_RFCSEL7 0x0000011C // Output Selection for RFC Event 8 -#define EVENT_O_RFCSEL8 0x00000120 +#define EVENT_O_RFCSEL8 0x00000120 // Output Selection for RFC Event 9 -#define EVENT_O_RFCSEL9 0x00000124 +#define EVENT_O_RFCSEL9 0x00000124 // Output Selection for GPT0 0 -#define EVENT_O_GPT0ACAPTSEL 0x00000200 +#define EVENT_O_GPT0ACAPTSEL 0x00000200 // Output Selection for GPT0 1 -#define EVENT_O_GPT0BCAPTSEL 0x00000204 +#define EVENT_O_GPT0BCAPTSEL 0x00000204 // Output Selection for GPT1 0 -#define EVENT_O_GPT1ACAPTSEL 0x00000300 +#define EVENT_O_GPT1ACAPTSEL 0x00000300 // Output Selection for GPT1 1 -#define EVENT_O_GPT1BCAPTSEL 0x00000304 +#define EVENT_O_GPT1BCAPTSEL 0x00000304 // Output Selection for GPT2 0 -#define EVENT_O_GPT2ACAPTSEL 0x00000400 +#define EVENT_O_GPT2ACAPTSEL 0x00000400 // Output Selection for GPT2 1 -#define EVENT_O_GPT2BCAPTSEL 0x00000404 +#define EVENT_O_GPT2BCAPTSEL 0x00000404 // Output Selection for DMA Channel 1 SREQ -#define EVENT_O_UDMACH1SSEL 0x00000508 +#define EVENT_O_UDMACH1SSEL 0x00000508 // Output Selection for DMA Channel 1 REQ -#define EVENT_O_UDMACH1BSEL 0x0000050C +#define EVENT_O_UDMACH1BSEL 0x0000050C // Output Selection for DMA Channel 2 SREQ -#define EVENT_O_UDMACH2SSEL 0x00000510 +#define EVENT_O_UDMACH2SSEL 0x00000510 // Output Selection for DMA Channel 2 REQ -#define EVENT_O_UDMACH2BSEL 0x00000514 +#define EVENT_O_UDMACH2BSEL 0x00000514 // Output Selection for DMA Channel 3 SREQ -#define EVENT_O_UDMACH3SSEL 0x00000518 +#define EVENT_O_UDMACH3SSEL 0x00000518 // Output Selection for DMA Channel 3 REQ -#define EVENT_O_UDMACH3BSEL 0x0000051C +#define EVENT_O_UDMACH3BSEL 0x0000051C // Output Selection for DMA Channel 4 SREQ -#define EVENT_O_UDMACH4SSEL 0x00000520 +#define EVENT_O_UDMACH4SSEL 0x00000520 // Output Selection for DMA Channel 4 REQ -#define EVENT_O_UDMACH4BSEL 0x00000524 +#define EVENT_O_UDMACH4BSEL 0x00000524 // Output Selection for DMA Channel 5 SREQ -#define EVENT_O_UDMACH5SSEL 0x00000528 +#define EVENT_O_UDMACH5SSEL 0x00000528 // Output Selection for DMA Channel 5 REQ -#define EVENT_O_UDMACH5BSEL 0x0000052C +#define EVENT_O_UDMACH5BSEL 0x0000052C // Output Selection for DMA Channel 6 SREQ -#define EVENT_O_UDMACH6SSEL 0x00000530 +#define EVENT_O_UDMACH6SSEL 0x00000530 // Output Selection for DMA Channel 6 REQ -#define EVENT_O_UDMACH6BSEL 0x00000534 +#define EVENT_O_UDMACH6BSEL 0x00000534 // Output Selection for DMA Channel 7 SREQ -#define EVENT_O_UDMACH7SSEL 0x00000538 +#define EVENT_O_UDMACH7SSEL 0x00000538 // Output Selection for DMA Channel 7 REQ -#define EVENT_O_UDMACH7BSEL 0x0000053C +#define EVENT_O_UDMACH7BSEL 0x0000053C // Output Selection for DMA Channel 8 SREQ -#define EVENT_O_UDMACH8SSEL 0x00000540 +#define EVENT_O_UDMACH8SSEL 0x00000540 // Output Selection for DMA Channel 8 REQ -#define EVENT_O_UDMACH8BSEL 0x00000544 +#define EVENT_O_UDMACH8BSEL 0x00000544 // Output Selection for DMA Channel 9 SREQ -#define EVENT_O_UDMACH9SSEL 0x00000548 +#define EVENT_O_UDMACH9SSEL 0x00000548 // Output Selection for DMA Channel 9 REQ -#define EVENT_O_UDMACH9BSEL 0x0000054C +#define EVENT_O_UDMACH9BSEL 0x0000054C // Output Selection for DMA Channel 10 SREQ -#define EVENT_O_UDMACH10SSEL 0x00000550 +#define EVENT_O_UDMACH10SSEL 0x00000550 // Output Selection for DMA Channel 10 REQ -#define EVENT_O_UDMACH10BSEL 0x00000554 +#define EVENT_O_UDMACH10BSEL 0x00000554 // Output Selection for DMA Channel 11 SREQ -#define EVENT_O_UDMACH11SSEL 0x00000558 +#define EVENT_O_UDMACH11SSEL 0x00000558 // Output Selection for DMA Channel 11 REQ -#define EVENT_O_UDMACH11BSEL 0x0000055C +#define EVENT_O_UDMACH11BSEL 0x0000055C // Output Selection for DMA Channel 12 SREQ -#define EVENT_O_UDMACH12SSEL 0x00000560 +#define EVENT_O_UDMACH12SSEL 0x00000560 // Output Selection for DMA Channel 12 REQ -#define EVENT_O_UDMACH12BSEL 0x00000564 +#define EVENT_O_UDMACH12BSEL 0x00000564 // Output Selection for DMA Channel 13 REQ -#define EVENT_O_UDMACH13BSEL 0x0000056C +#define EVENT_O_UDMACH13BSEL 0x0000056C // Output Selection for DMA Channel 14 REQ -#define EVENT_O_UDMACH14BSEL 0x00000574 +#define EVENT_O_UDMACH14BSEL 0x00000574 // Output Selection for DMA Channel 15 REQ -#define EVENT_O_UDMACH15BSEL 0x0000057C +#define EVENT_O_UDMACH15BSEL 0x0000057C // Output Selection for DMA Channel 16 SREQ -#define EVENT_O_UDMACH16SSEL 0x00000580 +#define EVENT_O_UDMACH16SSEL 0x00000580 // Output Selection for DMA Channel 16 REQ -#define EVENT_O_UDMACH16BSEL 0x00000584 +#define EVENT_O_UDMACH16BSEL 0x00000584 // Output Selection for DMA Channel 17 SREQ -#define EVENT_O_UDMACH17SSEL 0x00000588 +#define EVENT_O_UDMACH17SSEL 0x00000588 // Output Selection for DMA Channel 17 REQ -#define EVENT_O_UDMACH17BSEL 0x0000058C +#define EVENT_O_UDMACH17BSEL 0x0000058C // Output Selection for DMA Channel 21 SREQ -#define EVENT_O_UDMACH21SSEL 0x000005A8 +#define EVENT_O_UDMACH21SSEL 0x000005A8 // Output Selection for DMA Channel 21 REQ -#define EVENT_O_UDMACH21BSEL 0x000005AC +#define EVENT_O_UDMACH21BSEL 0x000005AC // Output Selection for DMA Channel 22 SREQ -#define EVENT_O_UDMACH22SSEL 0x000005B0 +#define EVENT_O_UDMACH22SSEL 0x000005B0 // Output Selection for DMA Channel 22 REQ -#define EVENT_O_UDMACH22BSEL 0x000005B4 +#define EVENT_O_UDMACH22BSEL 0x000005B4 // Output Selection for DMA Channel 23 SREQ -#define EVENT_O_UDMACH23SSEL 0x000005B8 +#define EVENT_O_UDMACH23SSEL 0x000005B8 // Output Selection for DMA Channel 23 REQ -#define EVENT_O_UDMACH23BSEL 0x000005BC +#define EVENT_O_UDMACH23BSEL 0x000005BC // Output Selection for DMA Channel 24 SREQ -#define EVENT_O_UDMACH24SSEL 0x000005C0 +#define EVENT_O_UDMACH24SSEL 0x000005C0 // Output Selection for DMA Channel 24 REQ -#define EVENT_O_UDMACH24BSEL 0x000005C4 +#define EVENT_O_UDMACH24BSEL 0x000005C4 // Output Selection for GPT3 0 -#define EVENT_O_GPT3ACAPTSEL 0x00000600 +#define EVENT_O_GPT3ACAPTSEL 0x00000600 // Output Selection for GPT3 1 -#define EVENT_O_GPT3BCAPTSEL 0x00000604 +#define EVENT_O_GPT3BCAPTSEL 0x00000604 // Output Selection for AUX Subscriber 0 -#define EVENT_O_AUXSEL0 0x00000700 +#define EVENT_O_AUXSEL0 0x00000700 // Output Selection for NMI Subscriber 0 -#define EVENT_O_CM3NMISEL0 0x00000800 +#define EVENT_O_CM3NMISEL0 0x00000800 // Output Selection for I2S Subscriber 0 -#define EVENT_O_I2SSTMPSEL0 0x00000900 +#define EVENT_O_I2SSTMPSEL0 0x00000900 // Output Selection for FRZ Subscriber -#define EVENT_O_FRZSEL0 0x00000A00 +#define EVENT_O_FRZSEL0 0x00000A00 // Set or Clear Software Events -#define EVENT_O_SWEV 0x00000F00 +#define EVENT_O_SWEV 0x00000F00 //***************************************************************************** // @@ -343,10 +343,10 @@ // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings -#define EVENT_CPUIRQSEL0_EV_W 7 -#define EVENT_CPUIRQSEL0_EV_M 0x0000007F -#define EVENT_CPUIRQSEL0_EV_S 0 -#define EVENT_CPUIRQSEL0_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_CPUIRQSEL0_EV_W 7 +#define EVENT_CPUIRQSEL0_EV_M 0x0000007F +#define EVENT_CPUIRQSEL0_EV_S 0 +#define EVENT_CPUIRQSEL0_EV_AON_GPIO_EDGE 0x00000004 //***************************************************************************** // @@ -358,10 +358,10 @@ // Read only selection value // ENUMs: // I2C_IRQ Interrupt event from I2C -#define EVENT_CPUIRQSEL1_EV_W 7 -#define EVENT_CPUIRQSEL1_EV_M 0x0000007F -#define EVENT_CPUIRQSEL1_EV_S 0 -#define EVENT_CPUIRQSEL1_EV_I2C_IRQ 0x00000009 +#define EVENT_CPUIRQSEL1_EV_W 7 +#define EVENT_CPUIRQSEL1_EV_M 0x0000007F +#define EVENT_CPUIRQSEL1_EV_S 0 +#define EVENT_CPUIRQSEL1_EV_I2C_IRQ 0x00000009 //***************************************************************************** // @@ -377,10 +377,10 @@ // RFC_DBELL:RFCPEIFG. Only interrupts selected // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a // RFC_CPE_1 event -#define EVENT_CPUIRQSEL2_EV_W 7 -#define EVENT_CPUIRQSEL2_EV_M 0x0000007F -#define EVENT_CPUIRQSEL2_EV_S 0 -#define EVENT_CPUIRQSEL2_EV_RFC_CPE_1 0x0000001E +#define EVENT_CPUIRQSEL2_EV_W 7 +#define EVENT_CPUIRQSEL2_EV_M 0x0000007F +#define EVENT_CPUIRQSEL2_EV_S 0 +#define EVENT_CPUIRQSEL2_EV_RFC_CPE_1 0x0000001E //***************************************************************************** // @@ -398,10 +398,10 @@ // ENUMs: // AON_RTC_COMB Event from AON_RTC, controlled by the // AON_RTC:CTL.COMB_EV_MASK setting -#define EVENT_CPUIRQSEL4_EV_W 7 -#define EVENT_CPUIRQSEL4_EV_M 0x0000007F -#define EVENT_CPUIRQSEL4_EV_S 0 -#define EVENT_CPUIRQSEL4_EV_AON_RTC_COMB 0x00000007 +#define EVENT_CPUIRQSEL4_EV_W 7 +#define EVENT_CPUIRQSEL4_EV_M 0x0000007F +#define EVENT_CPUIRQSEL4_EV_S 0 +#define EVENT_CPUIRQSEL4_EV_AON_RTC_COMB 0x00000007 //***************************************************************************** // @@ -414,10 +414,10 @@ // ENUMs: // UART0_COMB UART0 combined interrupt, interrupt flags are // found here UART0:MIS -#define EVENT_CPUIRQSEL5_EV_W 7 -#define EVENT_CPUIRQSEL5_EV_M 0x0000007F -#define EVENT_CPUIRQSEL5_EV_S 0 -#define EVENT_CPUIRQSEL5_EV_UART0_COMB 0x00000024 +#define EVENT_CPUIRQSEL5_EV_W 7 +#define EVENT_CPUIRQSEL5_EV_M 0x0000007F +#define EVENT_CPUIRQSEL5_EV_S 0 +#define EVENT_CPUIRQSEL5_EV_UART0_COMB 0x00000024 //***************************************************************************** // @@ -435,10 +435,10 @@ // AON_EVENT:MCUWUSEL // AUX domain wakeup control // AON_EVENT:AUXWUSEL -#define EVENT_CPUIRQSEL6_EV_W 7 -#define EVENT_CPUIRQSEL6_EV_M 0x0000007F -#define EVENT_CPUIRQSEL6_EV_S 0 -#define EVENT_CPUIRQSEL6_EV_AUX_SWEV0 0x0000001C +#define EVENT_CPUIRQSEL6_EV_W 7 +#define EVENT_CPUIRQSEL6_EV_M 0x0000007F +#define EVENT_CPUIRQSEL6_EV_S 0 +#define EVENT_CPUIRQSEL6_EV_AUX_SWEV0 0x0000001C //***************************************************************************** // @@ -451,10 +451,10 @@ // ENUMs: // SSI0_COMB SSI0 combined interrupt, interrupt flags are found // here SSI0:MIS -#define EVENT_CPUIRQSEL7_EV_W 7 -#define EVENT_CPUIRQSEL7_EV_M 0x0000007F -#define EVENT_CPUIRQSEL7_EV_S 0 -#define EVENT_CPUIRQSEL7_EV_SSI0_COMB 0x00000022 +#define EVENT_CPUIRQSEL7_EV_W 7 +#define EVENT_CPUIRQSEL7_EV_M 0x0000007F +#define EVENT_CPUIRQSEL7_EV_S 0 +#define EVENT_CPUIRQSEL7_EV_SSI0_COMB 0x00000022 //***************************************************************************** // @@ -467,10 +467,10 @@ // ENUMs: // SSI1_COMB SSI1 combined interrupt, interrupt flags are found // here SSI1:MIS -#define EVENT_CPUIRQSEL8_EV_W 7 -#define EVENT_CPUIRQSEL8_EV_M 0x0000007F -#define EVENT_CPUIRQSEL8_EV_S 0 -#define EVENT_CPUIRQSEL8_EV_SSI1_COMB 0x00000023 +#define EVENT_CPUIRQSEL8_EV_W 7 +#define EVENT_CPUIRQSEL8_EV_M 0x0000007F +#define EVENT_CPUIRQSEL8_EV_S 0 +#define EVENT_CPUIRQSEL8_EV_SSI1_COMB 0x00000023 //***************************************************************************** // @@ -486,10 +486,10 @@ // RFC_DBELL:RFCPEIFG. Only interrupts selected // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a // RFC_CPE_0 event -#define EVENT_CPUIRQSEL9_EV_W 7 -#define EVENT_CPUIRQSEL9_EV_M 0x0000007F -#define EVENT_CPUIRQSEL9_EV_S 0 -#define EVENT_CPUIRQSEL9_EV_RFC_CPE_0 0x0000001B +#define EVENT_CPUIRQSEL9_EV_W 7 +#define EVENT_CPUIRQSEL9_EV_M 0x0000007F +#define EVENT_CPUIRQSEL9_EV_S 0 +#define EVENT_CPUIRQSEL9_EV_RFC_CPE_0 0x0000001B //***************************************************************************** // @@ -502,10 +502,10 @@ // ENUMs: // RFC_HW_COMB Combined RFC hardware interrupt, corresponding // flag is here RFC_DBELL:RFHWIFG -#define EVENT_CPUIRQSEL10_EV_W 7 -#define EVENT_CPUIRQSEL10_EV_M 0x0000007F -#define EVENT_CPUIRQSEL10_EV_S 0 -#define EVENT_CPUIRQSEL10_EV_RFC_HW_COMB 0x0000001A +#define EVENT_CPUIRQSEL10_EV_W 7 +#define EVENT_CPUIRQSEL10_EV_M 0x0000007F +#define EVENT_CPUIRQSEL10_EV_S 0 +#define EVENT_CPUIRQSEL10_EV_RFC_HW_COMB 0x0000001A //***************************************************************************** // @@ -518,10 +518,10 @@ // ENUMs: // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -#define EVENT_CPUIRQSEL11_EV_W 7 -#define EVENT_CPUIRQSEL11_EV_M 0x0000007F -#define EVENT_CPUIRQSEL11_EV_S 0 -#define EVENT_CPUIRQSEL11_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_CPUIRQSEL11_EV_W 7 +#define EVENT_CPUIRQSEL11_EV_M 0x0000007F +#define EVENT_CPUIRQSEL11_EV_S 0 +#define EVENT_CPUIRQSEL11_EV_RFC_CMD_ACK 0x00000019 //***************************************************************************** // @@ -533,10 +533,10 @@ // Read only selection value // ENUMs: // I2S_IRQ Interrupt event from I2S -#define EVENT_CPUIRQSEL12_EV_W 7 -#define EVENT_CPUIRQSEL12_EV_M 0x0000007F -#define EVENT_CPUIRQSEL12_EV_S 0 -#define EVENT_CPUIRQSEL12_EV_I2S_IRQ 0x00000008 +#define EVENT_CPUIRQSEL12_EV_W 7 +#define EVENT_CPUIRQSEL12_EV_M 0x0000007F +#define EVENT_CPUIRQSEL12_EV_S 0 +#define EVENT_CPUIRQSEL12_EV_I2S_IRQ 0x00000008 //***************************************************************************** // @@ -554,10 +554,10 @@ // AON_EVENT:MCUWUSEL // AUX domain wakeup control // AON_EVENT:AUXWUSEL -#define EVENT_CPUIRQSEL13_EV_W 7 -#define EVENT_CPUIRQSEL13_EV_M 0x0000007F -#define EVENT_CPUIRQSEL13_EV_S 0 -#define EVENT_CPUIRQSEL13_EV_AUX_SWEV1 0x0000001D +#define EVENT_CPUIRQSEL13_EV_W 7 +#define EVENT_CPUIRQSEL13_EV_M 0x0000007F +#define EVENT_CPUIRQSEL13_EV_S 0 +#define EVENT_CPUIRQSEL13_EV_AUX_SWEV1 0x0000001D //***************************************************************************** // @@ -570,10 +570,10 @@ // ENUMs: // WDT_IRQ Watchdog interrupt event, controlled by // WDT:CTL.INTEN -#define EVENT_CPUIRQSEL14_EV_W 7 -#define EVENT_CPUIRQSEL14_EV_M 0x0000007F -#define EVENT_CPUIRQSEL14_EV_S 0 -#define EVENT_CPUIRQSEL14_EV_WDT_IRQ 0x00000018 +#define EVENT_CPUIRQSEL14_EV_W 7 +#define EVENT_CPUIRQSEL14_EV_M 0x0000007F +#define EVENT_CPUIRQSEL14_EV_S 0 +#define EVENT_CPUIRQSEL14_EV_WDT_IRQ 0x00000018 //***************************************************************************** // @@ -585,10 +585,10 @@ // Read only selection value // ENUMs: // GPT0A GPT0A interrupt event, controlled by GPT0:TAMR -#define EVENT_CPUIRQSEL15_EV_W 7 -#define EVENT_CPUIRQSEL15_EV_M 0x0000007F -#define EVENT_CPUIRQSEL15_EV_S 0 -#define EVENT_CPUIRQSEL15_EV_GPT0A 0x00000010 +#define EVENT_CPUIRQSEL15_EV_W 7 +#define EVENT_CPUIRQSEL15_EV_M 0x0000007F +#define EVENT_CPUIRQSEL15_EV_S 0 +#define EVENT_CPUIRQSEL15_EV_GPT0A 0x00000010 //***************************************************************************** // @@ -600,10 +600,10 @@ // Read only selection value // ENUMs: // GPT0B GPT0B interrupt event, controlled by GPT0:TBMR -#define EVENT_CPUIRQSEL16_EV_W 7 -#define EVENT_CPUIRQSEL16_EV_M 0x0000007F -#define EVENT_CPUIRQSEL16_EV_S 0 -#define EVENT_CPUIRQSEL16_EV_GPT0B 0x00000011 +#define EVENT_CPUIRQSEL16_EV_W 7 +#define EVENT_CPUIRQSEL16_EV_M 0x0000007F +#define EVENT_CPUIRQSEL16_EV_S 0 +#define EVENT_CPUIRQSEL16_EV_GPT0B 0x00000011 //***************************************************************************** // @@ -615,10 +615,10 @@ // Read only selection value // ENUMs: // GPT1A GPT1A interrupt event, controlled by GPT1:TAMR -#define EVENT_CPUIRQSEL17_EV_W 7 -#define EVENT_CPUIRQSEL17_EV_M 0x0000007F -#define EVENT_CPUIRQSEL17_EV_S 0 -#define EVENT_CPUIRQSEL17_EV_GPT1A 0x00000012 +#define EVENT_CPUIRQSEL17_EV_W 7 +#define EVENT_CPUIRQSEL17_EV_M 0x0000007F +#define EVENT_CPUIRQSEL17_EV_S 0 +#define EVENT_CPUIRQSEL17_EV_GPT1A 0x00000012 //***************************************************************************** // @@ -630,10 +630,10 @@ // Read only selection value // ENUMs: // GPT1B GPT1B interrupt event, controlled by GPT1:TBMR -#define EVENT_CPUIRQSEL18_EV_W 7 -#define EVENT_CPUIRQSEL18_EV_M 0x0000007F -#define EVENT_CPUIRQSEL18_EV_S 0 -#define EVENT_CPUIRQSEL18_EV_GPT1B 0x00000013 +#define EVENT_CPUIRQSEL18_EV_W 7 +#define EVENT_CPUIRQSEL18_EV_M 0x0000007F +#define EVENT_CPUIRQSEL18_EV_S 0 +#define EVENT_CPUIRQSEL18_EV_GPT1B 0x00000013 //***************************************************************************** // @@ -645,10 +645,10 @@ // Read only selection value // ENUMs: // GPT2A GPT2A interrupt event, controlled by GPT2:TAMR -#define EVENT_CPUIRQSEL19_EV_W 7 -#define EVENT_CPUIRQSEL19_EV_M 0x0000007F -#define EVENT_CPUIRQSEL19_EV_S 0 -#define EVENT_CPUIRQSEL19_EV_GPT2A 0x0000000C +#define EVENT_CPUIRQSEL19_EV_W 7 +#define EVENT_CPUIRQSEL19_EV_M 0x0000007F +#define EVENT_CPUIRQSEL19_EV_S 0 +#define EVENT_CPUIRQSEL19_EV_GPT2A 0x0000000C //***************************************************************************** // @@ -660,10 +660,10 @@ // Read only selection value // ENUMs: // GPT2B GPT2B interrupt event, controlled by GPT2:TBMR -#define EVENT_CPUIRQSEL20_EV_W 7 -#define EVENT_CPUIRQSEL20_EV_M 0x0000007F -#define EVENT_CPUIRQSEL20_EV_S 0 -#define EVENT_CPUIRQSEL20_EV_GPT2B 0x0000000D +#define EVENT_CPUIRQSEL20_EV_W 7 +#define EVENT_CPUIRQSEL20_EV_M 0x0000007F +#define EVENT_CPUIRQSEL20_EV_S 0 +#define EVENT_CPUIRQSEL20_EV_GPT2B 0x0000000D //***************************************************************************** // @@ -675,10 +675,10 @@ // Read only selection value // ENUMs: // GPT3A GPT3A interrupt event, controlled by GPT3:TAMR -#define EVENT_CPUIRQSEL21_EV_W 7 -#define EVENT_CPUIRQSEL21_EV_M 0x0000007F -#define EVENT_CPUIRQSEL21_EV_S 0 -#define EVENT_CPUIRQSEL21_EV_GPT3A 0x0000000E +#define EVENT_CPUIRQSEL21_EV_W 7 +#define EVENT_CPUIRQSEL21_EV_M 0x0000007F +#define EVENT_CPUIRQSEL21_EV_S 0 +#define EVENT_CPUIRQSEL21_EV_GPT3A 0x0000000E //***************************************************************************** // @@ -690,10 +690,10 @@ // Read only selection value // ENUMs: // GPT3B GPT3B interrupt event, controlled by GPT3:TBMR -#define EVENT_CPUIRQSEL22_EV_W 7 -#define EVENT_CPUIRQSEL22_EV_M 0x0000007F -#define EVENT_CPUIRQSEL22_EV_S 0 -#define EVENT_CPUIRQSEL22_EV_GPT3B 0x0000000F +#define EVENT_CPUIRQSEL22_EV_W 7 +#define EVENT_CPUIRQSEL22_EV_M 0x0000007F +#define EVENT_CPUIRQSEL22_EV_S 0 +#define EVENT_CPUIRQSEL22_EV_GPT3B 0x0000000F //***************************************************************************** // @@ -708,10 +708,10 @@ // corresponding flag is found here // CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by // CRYPTO:IRQSTAT.RESULT_AVAIL -#define EVENT_CPUIRQSEL23_EV_W 7 -#define EVENT_CPUIRQSEL23_EV_M 0x0000007F -#define EVENT_CPUIRQSEL23_EV_S 0 -#define EVENT_CPUIRQSEL23_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D +#define EVENT_CPUIRQSEL23_EV_W 7 +#define EVENT_CPUIRQSEL23_EV_M 0x0000007F +#define EVENT_CPUIRQSEL23_EV_S 0 +#define EVENT_CPUIRQSEL23_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D //***************************************************************************** // @@ -724,10 +724,10 @@ // ENUMs: // DMA_DONE_COMB Combined DMA done, corresponding flags are here // UDMA0:REQDONE -#define EVENT_CPUIRQSEL24_EV_W 7 -#define EVENT_CPUIRQSEL24_EV_M 0x0000007F -#define EVENT_CPUIRQSEL24_EV_S 0 -#define EVENT_CPUIRQSEL24_EV_DMA_DONE_COMB 0x00000027 +#define EVENT_CPUIRQSEL24_EV_W 7 +#define EVENT_CPUIRQSEL24_EV_M 0x0000007F +#define EVENT_CPUIRQSEL24_EV_S 0 +#define EVENT_CPUIRQSEL24_EV_DMA_DONE_COMB 0x00000027 //***************************************************************************** // @@ -739,10 +739,10 @@ // Read only selection value // ENUMs: // DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS -#define EVENT_CPUIRQSEL25_EV_W 7 -#define EVENT_CPUIRQSEL25_EV_M 0x0000007F -#define EVENT_CPUIRQSEL25_EV_S 0 -#define EVENT_CPUIRQSEL25_EV_DMA_ERR 0x00000026 +#define EVENT_CPUIRQSEL25_EV_W 7 +#define EVENT_CPUIRQSEL25_EV_M 0x0000007F +#define EVENT_CPUIRQSEL25_EV_S 0 +#define EVENT_CPUIRQSEL25_EV_DMA_ERR 0x00000026 //***************************************************************************** // @@ -756,10 +756,10 @@ // FLASH FLASH controller error event, the status flags // are FLASH:FEDACSTAT.FSM_DONE and // FLASH:FEDACSTAT.RVF_INT -#define EVENT_CPUIRQSEL26_EV_W 7 -#define EVENT_CPUIRQSEL26_EV_M 0x0000007F -#define EVENT_CPUIRQSEL26_EV_S 0 -#define EVENT_CPUIRQSEL26_EV_FLASH 0x00000015 +#define EVENT_CPUIRQSEL26_EV_W 7 +#define EVENT_CPUIRQSEL26_EV_M 0x0000007F +#define EVENT_CPUIRQSEL26_EV_S 0 +#define EVENT_CPUIRQSEL26_EV_FLASH 0x00000015 //***************************************************************************** // @@ -771,10 +771,10 @@ // Read only selection value // ENUMs: // SWEV0 Software event 0, triggered by SWEV.SWEV0 -#define EVENT_CPUIRQSEL27_EV_W 7 -#define EVENT_CPUIRQSEL27_EV_M 0x0000007F -#define EVENT_CPUIRQSEL27_EV_S 0 -#define EVENT_CPUIRQSEL27_EV_SWEV0 0x00000064 +#define EVENT_CPUIRQSEL27_EV_W 7 +#define EVENT_CPUIRQSEL27_EV_M 0x0000007F +#define EVENT_CPUIRQSEL27_EV_S 0 +#define EVENT_CPUIRQSEL27_EV_SWEV0 0x00000064 //***************************************************************************** // @@ -787,10 +787,10 @@ // ENUMs: // AUX_COMB AUX combined event, the corresponding flag // register is here AUX_EVCTL:EVTOMCUFLAGS -#define EVENT_CPUIRQSEL28_EV_W 7 -#define EVENT_CPUIRQSEL28_EV_M 0x0000007F -#define EVENT_CPUIRQSEL28_EV_S 0 -#define EVENT_CPUIRQSEL28_EV_AUX_COMB 0x0000000B +#define EVENT_CPUIRQSEL28_EV_W 7 +#define EVENT_CPUIRQSEL28_EV_M 0x0000007F +#define EVENT_CPUIRQSEL28_EV_S 0 +#define EVENT_CPUIRQSEL28_EV_AUX_COMB 0x0000000B //***************************************************************************** // @@ -804,10 +804,10 @@ // AON_PROG0 AON programmable event 0. Event selected by // AON_EVENT MCU event selector, // AON_EVENT:EVTOMCUSEL.AON_PROG0_EV -#define EVENT_CPUIRQSEL29_EV_W 7 -#define EVENT_CPUIRQSEL29_EV_M 0x0000007F -#define EVENT_CPUIRQSEL29_EV_S 0 -#define EVENT_CPUIRQSEL29_EV_AON_PROG0 0x00000001 +#define EVENT_CPUIRQSEL29_EV_W 7 +#define EVENT_CPUIRQSEL29_EV_M 0x0000007F +#define EVENT_CPUIRQSEL29_EV_S 0 +#define EVENT_CPUIRQSEL29_EV_AON_PROG0 0x00000001 //***************************************************************************** // @@ -859,28 +859,28 @@ // AON_EVENT MCU event selector, // AON_EVENT:EVTOMCUSEL.AON_PROG1_EV // NONE Always inactive -#define EVENT_CPUIRQSEL30_EV_W 7 -#define EVENT_CPUIRQSEL30_EV_M 0x0000007F -#define EVENT_CPUIRQSEL30_EV_S 0 -#define EVENT_CPUIRQSEL30_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_CPUIRQSEL30_EV_AON_RTC_UPD 0x00000077 -#define EVENT_CPUIRQSEL30_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_CPUIRQSEL30_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_CPUIRQSEL30_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_CPUIRQSEL30_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_CPUIRQSEL30_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_CPUIRQSEL30_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_CPUIRQSEL30_EV_AUX_COMPB 0x0000006B -#define EVENT_CPUIRQSEL30_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_CPUIRQSEL30_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E -#define EVENT_CPUIRQSEL30_EV_DMA_CH18_DONE 0x00000016 -#define EVENT_CPUIRQSEL30_EV_DMA_CH0_DONE 0x00000014 -#define EVENT_CPUIRQSEL30_EV_AON_AUX_SWEV0 0x0000000A -#define EVENT_CPUIRQSEL30_EV_I2S_IRQ 0x00000008 -#define EVENT_CPUIRQSEL30_EV_AON_PROG2 0x00000003 -#define EVENT_CPUIRQSEL30_EV_AON_PROG1 0x00000002 -#define EVENT_CPUIRQSEL30_EV_NONE 0x00000000 +#define EVENT_CPUIRQSEL30_EV_W 7 +#define EVENT_CPUIRQSEL30_EV_M 0x0000007F +#define EVENT_CPUIRQSEL30_EV_S 0 +#define EVENT_CPUIRQSEL30_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_CPUIRQSEL30_EV_AON_RTC_UPD 0x00000077 +#define EVENT_CPUIRQSEL30_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_CPUIRQSEL30_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_CPUIRQSEL30_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_CPUIRQSEL30_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_CPUIRQSEL30_EV_AUX_COMPB 0x0000006B +#define EVENT_CPUIRQSEL30_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_CPUIRQSEL30_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E +#define EVENT_CPUIRQSEL30_EV_DMA_CH18_DONE 0x00000016 +#define EVENT_CPUIRQSEL30_EV_DMA_CH0_DONE 0x00000014 +#define EVENT_CPUIRQSEL30_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_CPUIRQSEL30_EV_I2S_IRQ 0x00000008 +#define EVENT_CPUIRQSEL30_EV_AON_PROG2 0x00000003 +#define EVENT_CPUIRQSEL30_EV_AON_PROG1 0x00000002 +#define EVENT_CPUIRQSEL30_EV_NONE 0x00000000 //***************************************************************************** // @@ -893,10 +893,10 @@ // ENUMs: // AUX_COMPA AUX Compare A event, corresponds to // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -#define EVENT_CPUIRQSEL31_EV_W 7 -#define EVENT_CPUIRQSEL31_EV_M 0x0000007F -#define EVENT_CPUIRQSEL31_EV_S 0 -#define EVENT_CPUIRQSEL31_EV_AUX_COMPA 0x0000006A +#define EVENT_CPUIRQSEL31_EV_W 7 +#define EVENT_CPUIRQSEL31_EV_M 0x0000007F +#define EVENT_CPUIRQSEL31_EV_S 0 +#define EVENT_CPUIRQSEL31_EV_AUX_COMPA 0x0000006A //***************************************************************************** // @@ -910,10 +910,10 @@ // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to // AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags // are found here AUX_EVCTL:EVTOMCUFLAGS -#define EVENT_CPUIRQSEL32_EV_W 7 -#define EVENT_CPUIRQSEL32_EV_M 0x0000007F -#define EVENT_CPUIRQSEL32_EV_S 0 -#define EVENT_CPUIRQSEL32_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_CPUIRQSEL32_EV_W 7 +#define EVENT_CPUIRQSEL32_EV_M 0x0000007F +#define EVENT_CPUIRQSEL32_EV_S 0 +#define EVENT_CPUIRQSEL32_EV_AUX_ADC_IRQ 0x00000073 //***************************************************************************** // @@ -925,10 +925,10 @@ // Read only selection value // ENUMs: // TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN -#define EVENT_CPUIRQSEL33_EV_W 7 -#define EVENT_CPUIRQSEL33_EV_M 0x0000007F -#define EVENT_CPUIRQSEL33_EV_S 0 -#define EVENT_CPUIRQSEL33_EV_TRNG_IRQ 0x00000068 +#define EVENT_CPUIRQSEL33_EV_W 7 +#define EVENT_CPUIRQSEL33_EV_M 0x0000007F +#define EVENT_CPUIRQSEL33_EV_S 0 +#define EVENT_CPUIRQSEL33_EV_TRNG_IRQ 0x00000068 //***************************************************************************** // @@ -940,10 +940,10 @@ // Read only selection value // ENUMs: // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -#define EVENT_RFCSEL0_EV_W 7 -#define EVENT_RFCSEL0_EV_M 0x0000007F -#define EVENT_RFCSEL0_EV_S 0 -#define EVENT_RFCSEL0_EV_GPT0A_CMP 0x0000003D +#define EVENT_RFCSEL0_EV_W 7 +#define EVENT_RFCSEL0_EV_M 0x0000007F +#define EVENT_RFCSEL0_EV_S 0 +#define EVENT_RFCSEL0_EV_GPT0A_CMP 0x0000003D //***************************************************************************** // @@ -955,10 +955,10 @@ // Read only selection value // ENUMs: // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -#define EVENT_RFCSEL1_EV_W 7 -#define EVENT_RFCSEL1_EV_M 0x0000007F -#define EVENT_RFCSEL1_EV_S 0 -#define EVENT_RFCSEL1_EV_GPT0B_CMP 0x0000003E +#define EVENT_RFCSEL1_EV_W 7 +#define EVENT_RFCSEL1_EV_M 0x0000007F +#define EVENT_RFCSEL1_EV_S 0 +#define EVENT_RFCSEL1_EV_GPT0B_CMP 0x0000003E //***************************************************************************** // @@ -970,10 +970,10 @@ // Read only selection value // ENUMs: // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -#define EVENT_RFCSEL2_EV_W 7 -#define EVENT_RFCSEL2_EV_M 0x0000007F -#define EVENT_RFCSEL2_EV_S 0 -#define EVENT_RFCSEL2_EV_GPT1A_CMP 0x0000003F +#define EVENT_RFCSEL2_EV_W 7 +#define EVENT_RFCSEL2_EV_M 0x0000007F +#define EVENT_RFCSEL2_EV_S 0 +#define EVENT_RFCSEL2_EV_GPT1A_CMP 0x0000003F //***************************************************************************** // @@ -985,10 +985,10 @@ // Read only selection value // ENUMs: // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -#define EVENT_RFCSEL3_EV_W 7 -#define EVENT_RFCSEL3_EV_M 0x0000007F -#define EVENT_RFCSEL3_EV_S 0 -#define EVENT_RFCSEL3_EV_GPT1B_CMP 0x00000040 +#define EVENT_RFCSEL3_EV_W 7 +#define EVENT_RFCSEL3_EV_M 0x0000007F +#define EVENT_RFCSEL3_EV_S 0 +#define EVENT_RFCSEL3_EV_GPT1B_CMP 0x00000040 //***************************************************************************** // @@ -1000,10 +1000,10 @@ // Read only selection value // ENUMs: // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -#define EVENT_RFCSEL4_EV_W 7 -#define EVENT_RFCSEL4_EV_M 0x0000007F -#define EVENT_RFCSEL4_EV_S 0 -#define EVENT_RFCSEL4_EV_GPT2A_CMP 0x00000041 +#define EVENT_RFCSEL4_EV_W 7 +#define EVENT_RFCSEL4_EV_M 0x0000007F +#define EVENT_RFCSEL4_EV_S 0 +#define EVENT_RFCSEL4_EV_GPT2A_CMP 0x00000041 //***************************************************************************** // @@ -1015,10 +1015,10 @@ // Read only selection value // ENUMs: // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -#define EVENT_RFCSEL5_EV_W 7 -#define EVENT_RFCSEL5_EV_M 0x0000007F -#define EVENT_RFCSEL5_EV_S 0 -#define EVENT_RFCSEL5_EV_GPT2B_CMP 0x00000042 +#define EVENT_RFCSEL5_EV_W 7 +#define EVENT_RFCSEL5_EV_M 0x0000007F +#define EVENT_RFCSEL5_EV_S 0 +#define EVENT_RFCSEL5_EV_GPT2B_CMP 0x00000042 //***************************************************************************** // @@ -1030,10 +1030,10 @@ // Read only selection value // ENUMs: // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -#define EVENT_RFCSEL6_EV_W 7 -#define EVENT_RFCSEL6_EV_M 0x0000007F -#define EVENT_RFCSEL6_EV_S 0 -#define EVENT_RFCSEL6_EV_GPT3A_CMP 0x00000043 +#define EVENT_RFCSEL6_EV_W 7 +#define EVENT_RFCSEL6_EV_M 0x0000007F +#define EVENT_RFCSEL6_EV_S 0 +#define EVENT_RFCSEL6_EV_GPT3A_CMP 0x00000043 //***************************************************************************** // @@ -1045,10 +1045,10 @@ // Read only selection value // ENUMs: // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -#define EVENT_RFCSEL7_EV_W 7 -#define EVENT_RFCSEL7_EV_M 0x0000007F -#define EVENT_RFCSEL7_EV_S 0 -#define EVENT_RFCSEL7_EV_GPT3B_CMP 0x00000044 +#define EVENT_RFCSEL7_EV_W 7 +#define EVENT_RFCSEL7_EV_M 0x0000007F +#define EVENT_RFCSEL7_EV_S 0 +#define EVENT_RFCSEL7_EV_GPT3B_CMP 0x00000044 //***************************************************************************** // @@ -1061,10 +1061,10 @@ // ENUMs: // AON_RTC_UPD RTC periodic event controlled by // AON_RTC:CTL.RTC_UPD_EN -#define EVENT_RFCSEL8_EV_W 7 -#define EVENT_RFCSEL8_EV_M 0x0000007F -#define EVENT_RFCSEL8_EV_S 0 -#define EVENT_RFCSEL8_EV_AON_RTC_UPD 0x00000077 +#define EVENT_RFCSEL8_EV_W 7 +#define EVENT_RFCSEL8_EV_M 0x0000007F +#define EVENT_RFCSEL8_EV_S 0 +#define EVENT_RFCSEL8_EV_AON_RTC_UPD 0x00000077 //***************************************************************************** // @@ -1128,34 +1128,34 @@ // AON_EVENT MCU event selector, // AON_EVENT:EVTOMCUSEL.AON_PROG0_EV // NONE Always inactive -#define EVENT_RFCSEL9_EV_W 7 -#define EVENT_RFCSEL9_EV_M 0x0000007F -#define EVENT_RFCSEL9_EV_S 0 -#define EVENT_RFCSEL9_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_RFCSEL9_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_RFCSEL9_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_RFCSEL9_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_RFCSEL9_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_RFCSEL9_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_RFCSEL9_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_RFCSEL9_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_RFCSEL9_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_RFCSEL9_EV_AUX_COMPB 0x0000006B -#define EVENT_RFCSEL9_EV_AUX_COMPA 0x0000006A -#define EVENT_RFCSEL9_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_RFCSEL9_EV_SWEV1 0x00000065 -#define EVENT_RFCSEL9_EV_SWEV0 0x00000064 -#define EVENT_RFCSEL9_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D -#define EVENT_RFCSEL9_EV_DMA_DONE_COMB 0x00000027 -#define EVENT_RFCSEL9_EV_UART0_COMB 0x00000024 -#define EVENT_RFCSEL9_EV_SSI1_COMB 0x00000023 -#define EVENT_RFCSEL9_EV_SSI0_COMB 0x00000022 -#define EVENT_RFCSEL9_EV_WDT_IRQ 0x00000018 -#define EVENT_RFCSEL9_EV_AON_AUX_SWEV0 0x0000000A -#define EVENT_RFCSEL9_EV_I2S_IRQ 0x00000008 -#define EVENT_RFCSEL9_EV_AON_PROG1 0x00000002 -#define EVENT_RFCSEL9_EV_AON_PROG0 0x00000001 -#define EVENT_RFCSEL9_EV_NONE 0x00000000 +#define EVENT_RFCSEL9_EV_W 7 +#define EVENT_RFCSEL9_EV_M 0x0000007F +#define EVENT_RFCSEL9_EV_S 0 +#define EVENT_RFCSEL9_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_RFCSEL9_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_RFCSEL9_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_RFCSEL9_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_RFCSEL9_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_RFCSEL9_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_RFCSEL9_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_RFCSEL9_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_RFCSEL9_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_RFCSEL9_EV_AUX_COMPB 0x0000006B +#define EVENT_RFCSEL9_EV_AUX_COMPA 0x0000006A +#define EVENT_RFCSEL9_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_RFCSEL9_EV_SWEV1 0x00000065 +#define EVENT_RFCSEL9_EV_SWEV0 0x00000064 +#define EVENT_RFCSEL9_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D +#define EVENT_RFCSEL9_EV_DMA_DONE_COMB 0x00000027 +#define EVENT_RFCSEL9_EV_UART0_COMB 0x00000024 +#define EVENT_RFCSEL9_EV_SSI1_COMB 0x00000023 +#define EVENT_RFCSEL9_EV_SSI0_COMB 0x00000022 +#define EVENT_RFCSEL9_EV_WDT_IRQ 0x00000018 +#define EVENT_RFCSEL9_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_RFCSEL9_EV_I2S_IRQ 0x00000008 +#define EVENT_RFCSEL9_EV_AON_PROG1 0x00000002 +#define EVENT_RFCSEL9_EV_AON_PROG0 0x00000001 +#define EVENT_RFCSEL9_EV_NONE 0x00000000 //***************************************************************************** // @@ -1242,45 +1242,45 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT0ACAPTSEL_EV_W 7 -#define EVENT_GPT0ACAPTSEL_EV_M 0x0000007F -#define EVENT_GPT0ACAPTSEL_EV_S 0 -#define EVENT_GPT0ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT0ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT0ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT0ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT0ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT1 0x00000056 -#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT0 0x00000055 -#define EVENT_GPT0ACAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT0ACAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT0ACAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT0ACAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT0ACAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT0ACAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT0ACAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT0ACAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT0ACAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT0ACAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT0ACAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT0ACAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT0ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT0ACAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT0ACAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT0ACAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT0ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT0ACAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT0ACAPTSEL_EV_W 7 +#define EVENT_GPT0ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT0ACAPTSEL_EV_S 0 +#define EVENT_GPT0ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT0ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT0ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT0ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT0ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_GPT0ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT0ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT0ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT0ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT0ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT0ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT0ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT0ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT0ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT0ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT0ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT0ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT0ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT0ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT0ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT0ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT0ACAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -1367,45 +1367,45 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT0BCAPTSEL_EV_W 7 -#define EVENT_GPT0BCAPTSEL_EV_M 0x0000007F -#define EVENT_GPT0BCAPTSEL_EV_S 0 -#define EVENT_GPT0BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT0BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT0BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT0BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT0BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT1 0x00000056 -#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT0 0x00000055 -#define EVENT_GPT0BCAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT0BCAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT0BCAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT0BCAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT0BCAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT0BCAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT0BCAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT0BCAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT0BCAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT0BCAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT0BCAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT0BCAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT0BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT0BCAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT0BCAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT0BCAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT0BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT0BCAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT0BCAPTSEL_EV_W 7 +#define EVENT_GPT0BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT0BCAPTSEL_EV_S 0 +#define EVENT_GPT0BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT0BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT0BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT0BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT0BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_GPT0BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT0BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT0BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT0BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT0BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT0BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT0BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT0BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT0BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT0BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT0BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT0BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT0BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT0BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT0BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT0BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT0BCAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -1492,45 +1492,45 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT1ACAPTSEL_EV_W 7 -#define EVENT_GPT1ACAPTSEL_EV_M 0x0000007F -#define EVENT_GPT1ACAPTSEL_EV_S 0 -#define EVENT_GPT1ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT1ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT1ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT1ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT1ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT3 0x00000058 -#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT2 0x00000057 -#define EVENT_GPT1ACAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT1ACAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT1ACAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT1ACAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT1ACAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT1ACAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT1ACAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT1ACAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT1ACAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT1ACAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT1ACAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT1ACAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT1ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT1ACAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT1ACAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT1ACAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT1ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT1ACAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT1ACAPTSEL_EV_W 7 +#define EVENT_GPT1ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT1ACAPTSEL_EV_S 0 +#define EVENT_GPT1ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT1ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT1ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT1ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT1ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_GPT1ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT1ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT1ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT1ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT1ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT1ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT1ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT1ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT1ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT1ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT1ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT1ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT1ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT1ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT1ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT1ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT1ACAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -1617,45 +1617,45 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT1BCAPTSEL_EV_W 7 -#define EVENT_GPT1BCAPTSEL_EV_M 0x0000007F -#define EVENT_GPT1BCAPTSEL_EV_S 0 -#define EVENT_GPT1BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT1BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT1BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT1BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT1BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT3 0x00000058 -#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT2 0x00000057 -#define EVENT_GPT1BCAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT1BCAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT1BCAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT1BCAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT1BCAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT1BCAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT1BCAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT1BCAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT1BCAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT1BCAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT1BCAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT1BCAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT1BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT1BCAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT1BCAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT1BCAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT1BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT1BCAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT1BCAPTSEL_EV_W 7 +#define EVENT_GPT1BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT1BCAPTSEL_EV_S 0 +#define EVENT_GPT1BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT1BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT1BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT1BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT1BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_GPT1BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT1BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT1BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT1BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT1BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT1BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT1BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT1BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT1BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT1BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT1BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT1BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT1BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT1BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT1BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT1BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT1BCAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -1742,45 +1742,45 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT2ACAPTSEL_EV_W 7 -#define EVENT_GPT2ACAPTSEL_EV_M 0x0000007F -#define EVENT_GPT2ACAPTSEL_EV_S 0 -#define EVENT_GPT2ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT2ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT2ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT2ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT2ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT5 0x0000005A -#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT4 0x00000059 -#define EVENT_GPT2ACAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT2ACAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT2ACAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT2ACAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT2ACAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT2ACAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT2ACAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT2ACAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT2ACAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT2ACAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT2ACAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT2ACAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT2ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT2ACAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT2ACAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT2ACAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT2ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT2ACAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT2ACAPTSEL_EV_W 7 +#define EVENT_GPT2ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT2ACAPTSEL_EV_S 0 +#define EVENT_GPT2ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT2ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT2ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT2ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT2ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_GPT2ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT2ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT2ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT2ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT2ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT2ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT2ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT2ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT2ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT2ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT2ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT2ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT2ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT2ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT2ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT2ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT2ACAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -1867,45 +1867,45 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT2BCAPTSEL_EV_W 7 -#define EVENT_GPT2BCAPTSEL_EV_M 0x0000007F -#define EVENT_GPT2BCAPTSEL_EV_S 0 -#define EVENT_GPT2BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT2BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT2BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT2BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT2BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT5 0x0000005A -#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT4 0x00000059 -#define EVENT_GPT2BCAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT2BCAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT2BCAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT2BCAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT2BCAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT2BCAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT2BCAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT2BCAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT2BCAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT2BCAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT2BCAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT2BCAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT2BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT2BCAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT2BCAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT2BCAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT2BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT2BCAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT2BCAPTSEL_EV_W 7 +#define EVENT_GPT2BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT2BCAPTSEL_EV_S 0 +#define EVENT_GPT2BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT2BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT2BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT2BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT2BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_GPT2BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT2BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT2BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT2BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT2BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT2BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT2BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT2BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT2BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT2BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT2BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT2BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT2BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT2BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT2BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT2BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT2BCAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -1918,10 +1918,10 @@ // ENUMs: // UART0_RX_DMASREQ UART0 RX DMA single request, controlled by // UART0:DMACTL.RXDMAE -#define EVENT_UDMACH1SSEL_EV_W 7 -#define EVENT_UDMACH1SSEL_EV_M 0x0000007F -#define EVENT_UDMACH1SSEL_EV_S 0 -#define EVENT_UDMACH1SSEL_EV_UART0_RX_DMASREQ 0x00000031 +#define EVENT_UDMACH1SSEL_EV_W 7 +#define EVENT_UDMACH1SSEL_EV_M 0x0000007F +#define EVENT_UDMACH1SSEL_EV_S 0 +#define EVENT_UDMACH1SSEL_EV_UART0_RX_DMASREQ 0x00000031 //***************************************************************************** // @@ -1934,10 +1934,10 @@ // ENUMs: // UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by // UART0:DMACTL.RXDMAE -#define EVENT_UDMACH1BSEL_EV_W 7 -#define EVENT_UDMACH1BSEL_EV_M 0x0000007F -#define EVENT_UDMACH1BSEL_EV_S 0 -#define EVENT_UDMACH1BSEL_EV_UART0_RX_DMABREQ 0x00000030 +#define EVENT_UDMACH1BSEL_EV_W 7 +#define EVENT_UDMACH1BSEL_EV_M 0x0000007F +#define EVENT_UDMACH1BSEL_EV_S 0 +#define EVENT_UDMACH1BSEL_EV_UART0_RX_DMABREQ 0x00000030 //***************************************************************************** // @@ -1950,10 +1950,10 @@ // ENUMs: // UART0_TX_DMASREQ UART0 TX DMA single request, controlled by // UART0:DMACTL.TXDMAE -#define EVENT_UDMACH2SSEL_EV_W 7 -#define EVENT_UDMACH2SSEL_EV_M 0x0000007F -#define EVENT_UDMACH2SSEL_EV_S 0 -#define EVENT_UDMACH2SSEL_EV_UART0_TX_DMASREQ 0x00000033 +#define EVENT_UDMACH2SSEL_EV_W 7 +#define EVENT_UDMACH2SSEL_EV_M 0x0000007F +#define EVENT_UDMACH2SSEL_EV_S 0 +#define EVENT_UDMACH2SSEL_EV_UART0_TX_DMASREQ 0x00000033 //***************************************************************************** // @@ -1966,10 +1966,10 @@ // ENUMs: // UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by // UART0:DMACTL.TXDMAE -#define EVENT_UDMACH2BSEL_EV_W 7 -#define EVENT_UDMACH2BSEL_EV_M 0x0000007F -#define EVENT_UDMACH2BSEL_EV_S 0 -#define EVENT_UDMACH2BSEL_EV_UART0_TX_DMABREQ 0x00000032 +#define EVENT_UDMACH2BSEL_EV_W 7 +#define EVENT_UDMACH2BSEL_EV_M 0x0000007F +#define EVENT_UDMACH2BSEL_EV_S 0 +#define EVENT_UDMACH2BSEL_EV_UART0_TX_DMABREQ 0x00000032 //***************************************************************************** // @@ -1982,10 +1982,10 @@ // ENUMs: // SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by // SSI0:DMACR.RXDMAE -#define EVENT_UDMACH3SSEL_EV_W 7 -#define EVENT_UDMACH3SSEL_EV_M 0x0000007F -#define EVENT_UDMACH3SSEL_EV_S 0 -#define EVENT_UDMACH3SSEL_EV_SSI0_RX_DMASREQ 0x00000029 +#define EVENT_UDMACH3SSEL_EV_W 7 +#define EVENT_UDMACH3SSEL_EV_M 0x0000007F +#define EVENT_UDMACH3SSEL_EV_S 0 +#define EVENT_UDMACH3SSEL_EV_SSI0_RX_DMASREQ 0x00000029 //***************************************************************************** // @@ -1998,10 +1998,10 @@ // ENUMs: // SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by // SSI0:DMACR.RXDMAE -#define EVENT_UDMACH3BSEL_EV_W 7 -#define EVENT_UDMACH3BSEL_EV_M 0x0000007F -#define EVENT_UDMACH3BSEL_EV_S 0 -#define EVENT_UDMACH3BSEL_EV_SSI0_RX_DMABREQ 0x00000028 +#define EVENT_UDMACH3BSEL_EV_W 7 +#define EVENT_UDMACH3BSEL_EV_M 0x0000007F +#define EVENT_UDMACH3BSEL_EV_S 0 +#define EVENT_UDMACH3BSEL_EV_SSI0_RX_DMABREQ 0x00000028 //***************************************************************************** // @@ -2014,10 +2014,10 @@ // ENUMs: // SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by // SSI0:DMACR.TXDMAE -#define EVENT_UDMACH4SSEL_EV_W 7 -#define EVENT_UDMACH4SSEL_EV_M 0x0000007F -#define EVENT_UDMACH4SSEL_EV_S 0 -#define EVENT_UDMACH4SSEL_EV_SSI0_TX_DMASREQ 0x0000002B +#define EVENT_UDMACH4SSEL_EV_W 7 +#define EVENT_UDMACH4SSEL_EV_M 0x0000007F +#define EVENT_UDMACH4SSEL_EV_S 0 +#define EVENT_UDMACH4SSEL_EV_SSI0_TX_DMASREQ 0x0000002B //***************************************************************************** // @@ -2030,10 +2030,10 @@ // ENUMs: // SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by // SSI0:DMACR.TXDMAE -#define EVENT_UDMACH4BSEL_EV_W 7 -#define EVENT_UDMACH4BSEL_EV_M 0x0000007F -#define EVENT_UDMACH4BSEL_EV_S 0 -#define EVENT_UDMACH4BSEL_EV_SSI0_TX_DMABREQ 0x0000002A +#define EVENT_UDMACH4BSEL_EV_W 7 +#define EVENT_UDMACH4BSEL_EV_M 0x0000007F +#define EVENT_UDMACH4BSEL_EV_S 0 +#define EVENT_UDMACH4BSEL_EV_SSI0_TX_DMABREQ 0x0000002A //***************************************************************************** // @@ -2066,10 +2066,10 @@ // ENUMs: // AUX_DMASREQ DMA single request event from AUX, configured by // AUX_EVCTL:DMACTL -#define EVENT_UDMACH7SSEL_EV_W 7 -#define EVENT_UDMACH7SSEL_EV_M 0x0000007F -#define EVENT_UDMACH7SSEL_EV_S 0 -#define EVENT_UDMACH7SSEL_EV_AUX_DMASREQ 0x00000075 +#define EVENT_UDMACH7SSEL_EV_W 7 +#define EVENT_UDMACH7SSEL_EV_M 0x0000007F +#define EVENT_UDMACH7SSEL_EV_S 0 +#define EVENT_UDMACH7SSEL_EV_AUX_DMASREQ 0x00000075 //***************************************************************************** // @@ -2082,10 +2082,10 @@ // ENUMs: // AUX_DMABREQ DMA burst request event from AUX, configured by // AUX_EVCTL:DMACTL -#define EVENT_UDMACH7BSEL_EV_W 7 -#define EVENT_UDMACH7BSEL_EV_M 0x0000007F -#define EVENT_UDMACH7BSEL_EV_S 0 -#define EVENT_UDMACH7BSEL_EV_AUX_DMABREQ 0x00000076 +#define EVENT_UDMACH7BSEL_EV_W 7 +#define EVENT_UDMACH7BSEL_EV_M 0x0000007F +#define EVENT_UDMACH7BSEL_EV_S 0 +#define EVENT_UDMACH7BSEL_EV_AUX_DMABREQ 0x00000076 //***************************************************************************** // @@ -2098,10 +2098,10 @@ // ENUMs: // AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by // AUX_EVCTL:DMASWREQ.START -#define EVENT_UDMACH8SSEL_EV_W 7 -#define EVENT_UDMACH8SSEL_EV_M 0x0000007F -#define EVENT_UDMACH8SSEL_EV_S 0 -#define EVENT_UDMACH8SSEL_EV_AUX_SW_DMABREQ 0x00000074 +#define EVENT_UDMACH8SSEL_EV_W 7 +#define EVENT_UDMACH8SSEL_EV_M 0x0000007F +#define EVENT_UDMACH8SSEL_EV_S 0 +#define EVENT_UDMACH8SSEL_EV_AUX_SW_DMABREQ 0x00000074 //***************************************************************************** // @@ -2114,10 +2114,10 @@ // ENUMs: // AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by // AUX_EVCTL:DMASWREQ.START -#define EVENT_UDMACH8BSEL_EV_W 7 -#define EVENT_UDMACH8BSEL_EV_M 0x0000007F -#define EVENT_UDMACH8BSEL_EV_S 0 -#define EVENT_UDMACH8BSEL_EV_AUX_SW_DMABREQ 0x00000074 +#define EVENT_UDMACH8BSEL_EV_W 7 +#define EVENT_UDMACH8BSEL_EV_M 0x0000007F +#define EVENT_UDMACH8BSEL_EV_S 0 +#define EVENT_UDMACH8BSEL_EV_AUX_SW_DMABREQ 0x00000074 //***************************************************************************** // @@ -2142,20 +2142,20 @@ // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // TIE_LOW Not used tied to 0 // NONE Always inactive -#define EVENT_UDMACH9SSEL_EV_W 7 -#define EVENT_UDMACH9SSEL_EV_M 0x0000007F -#define EVENT_UDMACH9SSEL_EV_S 0 -#define EVENT_UDMACH9SSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH9SSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH9SSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH9SSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH9SSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH9SSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH9SSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH9SSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH9SSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH9SSEL_EV_TIE_LOW 0x00000045 -#define EVENT_UDMACH9SSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH9SSEL_EV_W 7 +#define EVENT_UDMACH9SSEL_EV_M 0x0000007F +#define EVENT_UDMACH9SSEL_EV_S 0 +#define EVENT_UDMACH9SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH9SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH9SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH9SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH9SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH9SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH9SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH9SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH9SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH9SSEL_EV_TIE_LOW 0x00000045 +#define EVENT_UDMACH9SSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2179,19 +2179,19 @@ // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // NONE Always inactive -#define EVENT_UDMACH9BSEL_EV_W 7 -#define EVENT_UDMACH9BSEL_EV_M 0x0000007F -#define EVENT_UDMACH9BSEL_EV_S 0 -#define EVENT_UDMACH9BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH9BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH9BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH9BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH9BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH9BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH9BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH9BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH9BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH9BSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH9BSEL_EV_W 7 +#define EVENT_UDMACH9BSEL_EV_M 0x0000007F +#define EVENT_UDMACH9BSEL_EV_S 0 +#define EVENT_UDMACH9BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH9BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH9BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH9BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH9BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH9BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH9BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH9BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH9BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH9BSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2216,20 +2216,20 @@ // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // TIE_LOW Not used tied to 0 // NONE Always inactive -#define EVENT_UDMACH10SSEL_EV_W 7 -#define EVENT_UDMACH10SSEL_EV_M 0x0000007F -#define EVENT_UDMACH10SSEL_EV_S 0 -#define EVENT_UDMACH10SSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH10SSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH10SSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH10SSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH10SSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH10SSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH10SSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH10SSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH10SSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH10SSEL_EV_TIE_LOW 0x00000046 -#define EVENT_UDMACH10SSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH10SSEL_EV_W 7 +#define EVENT_UDMACH10SSEL_EV_M 0x0000007F +#define EVENT_UDMACH10SSEL_EV_S 0 +#define EVENT_UDMACH10SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH10SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH10SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH10SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH10SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH10SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH10SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH10SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH10SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH10SSEL_EV_TIE_LOW 0x00000046 +#define EVENT_UDMACH10SSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2253,19 +2253,19 @@ // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // NONE Always inactive -#define EVENT_UDMACH10BSEL_EV_W 7 -#define EVENT_UDMACH10BSEL_EV_M 0x0000007F -#define EVENT_UDMACH10BSEL_EV_S 0 -#define EVENT_UDMACH10BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH10BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH10BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH10BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH10BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH10BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH10BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH10BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH10BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH10BSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH10BSEL_EV_W 7 +#define EVENT_UDMACH10BSEL_EV_M 0x0000007F +#define EVENT_UDMACH10BSEL_EV_S 0 +#define EVENT_UDMACH10BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH10BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH10BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH10BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH10BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH10BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH10BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH10BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH10BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH10BSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2290,20 +2290,20 @@ // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // TIE_LOW Not used tied to 0 // NONE Always inactive -#define EVENT_UDMACH11SSEL_EV_W 7 -#define EVENT_UDMACH11SSEL_EV_M 0x0000007F -#define EVENT_UDMACH11SSEL_EV_S 0 -#define EVENT_UDMACH11SSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH11SSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH11SSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH11SSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH11SSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH11SSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH11SSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH11SSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH11SSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH11SSEL_EV_TIE_LOW 0x00000047 -#define EVENT_UDMACH11SSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH11SSEL_EV_W 7 +#define EVENT_UDMACH11SSEL_EV_M 0x0000007F +#define EVENT_UDMACH11SSEL_EV_S 0 +#define EVENT_UDMACH11SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH11SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH11SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH11SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH11SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH11SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH11SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH11SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH11SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH11SSEL_EV_TIE_LOW 0x00000047 +#define EVENT_UDMACH11SSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2327,19 +2327,19 @@ // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // NONE Always inactive -#define EVENT_UDMACH11BSEL_EV_W 7 -#define EVENT_UDMACH11BSEL_EV_M 0x0000007F -#define EVENT_UDMACH11BSEL_EV_S 0 -#define EVENT_UDMACH11BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH11BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH11BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH11BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH11BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH11BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH11BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH11BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH11BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH11BSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH11BSEL_EV_W 7 +#define EVENT_UDMACH11BSEL_EV_M 0x0000007F +#define EVENT_UDMACH11BSEL_EV_S 0 +#define EVENT_UDMACH11BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH11BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH11BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH11BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH11BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH11BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH11BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH11BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH11BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH11BSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2364,20 +2364,20 @@ // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // TIE_LOW Not used tied to 0 // NONE Always inactive -#define EVENT_UDMACH12SSEL_EV_W 7 -#define EVENT_UDMACH12SSEL_EV_M 0x0000007F -#define EVENT_UDMACH12SSEL_EV_S 0 -#define EVENT_UDMACH12SSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH12SSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH12SSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH12SSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH12SSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH12SSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH12SSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH12SSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH12SSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH12SSEL_EV_TIE_LOW 0x00000048 -#define EVENT_UDMACH12SSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH12SSEL_EV_W 7 +#define EVENT_UDMACH12SSEL_EV_M 0x0000007F +#define EVENT_UDMACH12SSEL_EV_S 0 +#define EVENT_UDMACH12SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH12SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH12SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH12SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH12SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH12SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH12SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH12SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH12SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH12SSEL_EV_TIE_LOW 0x00000048 +#define EVENT_UDMACH12SSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2401,19 +2401,19 @@ // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // NONE Always inactive -#define EVENT_UDMACH12BSEL_EV_W 7 -#define EVENT_UDMACH12BSEL_EV_M 0x0000007F -#define EVENT_UDMACH12BSEL_EV_S 0 -#define EVENT_UDMACH12BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH12BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH12BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH12BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH12BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH12BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH12BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH12BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH12BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH12BSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH12BSEL_EV_W 7 +#define EVENT_UDMACH12BSEL_EV_M 0x0000007F +#define EVENT_UDMACH12BSEL_EV_S 0 +#define EVENT_UDMACH12BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH12BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH12BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH12BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH12BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH12BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH12BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH12BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH12BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH12BSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2427,10 +2427,10 @@ // AON_PROG2 AON programmable event 2. Event selected by // AON_EVENT MCU event selector, // AON_EVENT:EVTOMCUSEL.AON_PROG2_EV -#define EVENT_UDMACH13BSEL_EV_W 7 -#define EVENT_UDMACH13BSEL_EV_M 0x0000007F -#define EVENT_UDMACH13BSEL_EV_S 0 -#define EVENT_UDMACH13BSEL_EV_AON_PROG2 0x00000003 +#define EVENT_UDMACH13BSEL_EV_W 7 +#define EVENT_UDMACH13BSEL_EV_M 0x0000007F +#define EVENT_UDMACH13BSEL_EV_S 0 +#define EVENT_UDMACH13BSEL_EV_AON_PROG2 0x00000003 //***************************************************************************** // @@ -2623,102 +2623,102 @@ // AON_EVENT MCU event selector, // AON_EVENT:EVTOMCUSEL.AON_PROG0_EV // NONE Always inactive -#define EVENT_UDMACH14BSEL_EV_W 7 -#define EVENT_UDMACH14BSEL_EV_M 0x0000007F -#define EVENT_UDMACH14BSEL_EV_S 0 -#define EVENT_UDMACH14BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH14BSEL_EV_CPU_HALTED 0x00000078 -#define EVENT_UDMACH14BSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_UDMACH14BSEL_EV_AUX_DMABREQ 0x00000076 -#define EVENT_UDMACH14BSEL_EV_AUX_DMASREQ 0x00000075 -#define EVENT_UDMACH14BSEL_EV_AUX_SW_DMABREQ 0x00000074 -#define EVENT_UDMACH14BSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_UDMACH14BSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_UDMACH14BSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_UDMACH14BSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_UDMACH14BSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_UDMACH14BSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_UDMACH14BSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_UDMACH14BSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_UDMACH14BSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_UDMACH14BSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_UDMACH14BSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_UDMACH14BSEL_EV_TRNG_IRQ 0x00000068 -#define EVENT_UDMACH14BSEL_EV_SWEV3 0x00000067 -#define EVENT_UDMACH14BSEL_EV_SWEV2 0x00000066 -#define EVENT_UDMACH14BSEL_EV_SWEV1 0x00000065 -#define EVENT_UDMACH14BSEL_EV_SWEV0 0x00000064 -#define EVENT_UDMACH14BSEL_EV_WDT_NMI 0x00000063 -#define EVENT_UDMACH14BSEL_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E -#define EVENT_UDMACH14BSEL_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT7 0x0000005C -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT6 0x0000005B -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT5 0x0000005A -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT4 0x00000059 -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT3 0x00000058 -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT2 0x00000057 -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT1 0x00000056 -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT0 0x00000055 -#define EVENT_UDMACH14BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH14BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH14BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH14BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH14BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH14BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH14BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH14BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH14BSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_UDMACH14BSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_UDMACH14BSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_UDMACH14BSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_UDMACH14BSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_UDMACH14BSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_UDMACH14BSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_UDMACH14BSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMASREQ 0x00000033 -#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMABREQ 0x00000032 -#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMASREQ 0x00000031 -#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMABREQ 0x00000030 -#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMASREQ 0x0000002F -#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMABREQ 0x0000002E -#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMASREQ 0x0000002D -#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMABREQ 0x0000002C -#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMASREQ 0x0000002B -#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMABREQ 0x0000002A -#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMASREQ 0x00000029 -#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMABREQ 0x00000028 -#define EVENT_UDMACH14BSEL_EV_DMA_DONE_COMB 0x00000027 -#define EVENT_UDMACH14BSEL_EV_DMA_ERR 0x00000026 -#define EVENT_UDMACH14BSEL_EV_UART0_COMB 0x00000024 -#define EVENT_UDMACH14BSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_UDMACH14BSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_UDMACH14BSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_UDMACH14BSEL_EV_AUX_SWEV1 0x0000001D -#define EVENT_UDMACH14BSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_UDMACH14BSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_UDMACH14BSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_UDMACH14BSEL_EV_WDT_IRQ 0x00000018 -#define EVENT_UDMACH14BSEL_EV_DMA_CH18_DONE 0x00000016 -#define EVENT_UDMACH14BSEL_EV_FLASH 0x00000015 -#define EVENT_UDMACH14BSEL_EV_DMA_CH0_DONE 0x00000014 -#define EVENT_UDMACH14BSEL_EV_GPT1B 0x00000013 -#define EVENT_UDMACH14BSEL_EV_GPT1A 0x00000012 -#define EVENT_UDMACH14BSEL_EV_GPT0B 0x00000011 -#define EVENT_UDMACH14BSEL_EV_GPT0A 0x00000010 -#define EVENT_UDMACH14BSEL_EV_GPT3B 0x0000000F -#define EVENT_UDMACH14BSEL_EV_GPT3A 0x0000000E -#define EVENT_UDMACH14BSEL_EV_GPT2B 0x0000000D -#define EVENT_UDMACH14BSEL_EV_GPT2A 0x0000000C -#define EVENT_UDMACH14BSEL_EV_AUX_COMB 0x0000000B -#define EVENT_UDMACH14BSEL_EV_AON_AUX_SWEV0 0x0000000A -#define EVENT_UDMACH14BSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_UDMACH14BSEL_EV_I2S_IRQ 0x00000008 -#define EVENT_UDMACH14BSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_UDMACH14BSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_UDMACH14BSEL_EV_AON_PROG2 0x00000003 -#define EVENT_UDMACH14BSEL_EV_AON_PROG1 0x00000002 -#define EVENT_UDMACH14BSEL_EV_AON_PROG0 0x00000001 -#define EVENT_UDMACH14BSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH14BSEL_EV_W 7 +#define EVENT_UDMACH14BSEL_EV_M 0x0000007F +#define EVENT_UDMACH14BSEL_EV_S 0 +#define EVENT_UDMACH14BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH14BSEL_EV_CPU_HALTED 0x00000078 +#define EVENT_UDMACH14BSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_UDMACH14BSEL_EV_AUX_DMABREQ 0x00000076 +#define EVENT_UDMACH14BSEL_EV_AUX_DMASREQ 0x00000075 +#define EVENT_UDMACH14BSEL_EV_AUX_SW_DMABREQ 0x00000074 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_UDMACH14BSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_UDMACH14BSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_UDMACH14BSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_UDMACH14BSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_UDMACH14BSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_UDMACH14BSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_UDMACH14BSEL_EV_TRNG_IRQ 0x00000068 +#define EVENT_UDMACH14BSEL_EV_SWEV3 0x00000067 +#define EVENT_UDMACH14BSEL_EV_SWEV2 0x00000066 +#define EVENT_UDMACH14BSEL_EV_SWEV1 0x00000065 +#define EVENT_UDMACH14BSEL_EV_SWEV0 0x00000064 +#define EVENT_UDMACH14BSEL_EV_WDT_NMI 0x00000063 +#define EVENT_UDMACH14BSEL_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E +#define EVENT_UDMACH14BSEL_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_UDMACH14BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH14BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH14BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH14BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH14BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH14BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH14BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH14BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH14BSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_UDMACH14BSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_UDMACH14BSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_UDMACH14BSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_UDMACH14BSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_UDMACH14BSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_UDMACH14BSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_UDMACH14BSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMASREQ 0x00000033 +#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMABREQ 0x00000032 +#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMASREQ 0x00000031 +#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMABREQ 0x00000030 +#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMASREQ 0x0000002F +#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMABREQ 0x0000002E +#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMASREQ 0x0000002D +#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMABREQ 0x0000002C +#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMASREQ 0x0000002B +#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMABREQ 0x0000002A +#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMASREQ 0x00000029 +#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMABREQ 0x00000028 +#define EVENT_UDMACH14BSEL_EV_DMA_DONE_COMB 0x00000027 +#define EVENT_UDMACH14BSEL_EV_DMA_ERR 0x00000026 +#define EVENT_UDMACH14BSEL_EV_UART0_COMB 0x00000024 +#define EVENT_UDMACH14BSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_UDMACH14BSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_UDMACH14BSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_UDMACH14BSEL_EV_AUX_SWEV1 0x0000001D +#define EVENT_UDMACH14BSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_UDMACH14BSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_UDMACH14BSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_UDMACH14BSEL_EV_WDT_IRQ 0x00000018 +#define EVENT_UDMACH14BSEL_EV_DMA_CH18_DONE 0x00000016 +#define EVENT_UDMACH14BSEL_EV_FLASH 0x00000015 +#define EVENT_UDMACH14BSEL_EV_DMA_CH0_DONE 0x00000014 +#define EVENT_UDMACH14BSEL_EV_GPT1B 0x00000013 +#define EVENT_UDMACH14BSEL_EV_GPT1A 0x00000012 +#define EVENT_UDMACH14BSEL_EV_GPT0B 0x00000011 +#define EVENT_UDMACH14BSEL_EV_GPT0A 0x00000010 +#define EVENT_UDMACH14BSEL_EV_GPT3B 0x0000000F +#define EVENT_UDMACH14BSEL_EV_GPT3A 0x0000000E +#define EVENT_UDMACH14BSEL_EV_GPT2B 0x0000000D +#define EVENT_UDMACH14BSEL_EV_GPT2A 0x0000000C +#define EVENT_UDMACH14BSEL_EV_AUX_COMB 0x0000000B +#define EVENT_UDMACH14BSEL_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_UDMACH14BSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_UDMACH14BSEL_EV_I2S_IRQ 0x00000008 +#define EVENT_UDMACH14BSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_UDMACH14BSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_UDMACH14BSEL_EV_AON_PROG2 0x00000003 +#define EVENT_UDMACH14BSEL_EV_AON_PROG1 0x00000002 +#define EVENT_UDMACH14BSEL_EV_AON_PROG0 0x00000001 +#define EVENT_UDMACH14BSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2731,10 +2731,10 @@ // ENUMs: // AON_RTC_COMB Event from AON_RTC, controlled by the // AON_RTC:CTL.COMB_EV_MASK setting -#define EVENT_UDMACH15BSEL_EV_W 7 -#define EVENT_UDMACH15BSEL_EV_M 0x0000007F -#define EVENT_UDMACH15BSEL_EV_S 0 -#define EVENT_UDMACH15BSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_UDMACH15BSEL_EV_W 7 +#define EVENT_UDMACH15BSEL_EV_M 0x0000007F +#define EVENT_UDMACH15BSEL_EV_S 0 +#define EVENT_UDMACH15BSEL_EV_AON_RTC_COMB 0x00000007 //***************************************************************************** // @@ -2747,10 +2747,10 @@ // ENUMs: // SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by // SSI0:DMACR.RXDMAE -#define EVENT_UDMACH16SSEL_EV_W 7 -#define EVENT_UDMACH16SSEL_EV_M 0x0000007F -#define EVENT_UDMACH16SSEL_EV_S 0 -#define EVENT_UDMACH16SSEL_EV_SSI1_RX_DMASREQ 0x0000002D +#define EVENT_UDMACH16SSEL_EV_W 7 +#define EVENT_UDMACH16SSEL_EV_M 0x0000007F +#define EVENT_UDMACH16SSEL_EV_S 0 +#define EVENT_UDMACH16SSEL_EV_SSI1_RX_DMASREQ 0x0000002D //***************************************************************************** // @@ -2763,10 +2763,10 @@ // ENUMs: // SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by // SSI0:DMACR.RXDMAE -#define EVENT_UDMACH16BSEL_EV_W 7 -#define EVENT_UDMACH16BSEL_EV_M 0x0000007F -#define EVENT_UDMACH16BSEL_EV_S 0 -#define EVENT_UDMACH16BSEL_EV_SSI1_RX_DMABREQ 0x0000002C +#define EVENT_UDMACH16BSEL_EV_W 7 +#define EVENT_UDMACH16BSEL_EV_M 0x0000007F +#define EVENT_UDMACH16BSEL_EV_S 0 +#define EVENT_UDMACH16BSEL_EV_SSI1_RX_DMABREQ 0x0000002C //***************************************************************************** // @@ -2779,10 +2779,10 @@ // ENUMs: // SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by // SSI0:DMACR.TXDMAE -#define EVENT_UDMACH17SSEL_EV_W 7 -#define EVENT_UDMACH17SSEL_EV_M 0x0000007F -#define EVENT_UDMACH17SSEL_EV_S 0 -#define EVENT_UDMACH17SSEL_EV_SSI1_TX_DMASREQ 0x0000002F +#define EVENT_UDMACH17SSEL_EV_W 7 +#define EVENT_UDMACH17SSEL_EV_M 0x0000007F +#define EVENT_UDMACH17SSEL_EV_S 0 +#define EVENT_UDMACH17SSEL_EV_SSI1_TX_DMASREQ 0x0000002F //***************************************************************************** // @@ -2795,10 +2795,10 @@ // ENUMs: // SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by // SSI0:DMACR.TXDMAE -#define EVENT_UDMACH17BSEL_EV_W 7 -#define EVENT_UDMACH17BSEL_EV_M 0x0000007F -#define EVENT_UDMACH17BSEL_EV_S 0 -#define EVENT_UDMACH17BSEL_EV_SSI1_TX_DMABREQ 0x0000002E +#define EVENT_UDMACH17BSEL_EV_W 7 +#define EVENT_UDMACH17BSEL_EV_M 0x0000007F +#define EVENT_UDMACH17BSEL_EV_S 0 +#define EVENT_UDMACH17BSEL_EV_SSI1_TX_DMABREQ 0x0000002E //***************************************************************************** // @@ -2810,10 +2810,10 @@ // Read only selection value // ENUMs: // SWEV0 Software event 0, triggered by SWEV.SWEV0 -#define EVENT_UDMACH21SSEL_EV_W 7 -#define EVENT_UDMACH21SSEL_EV_M 0x0000007F -#define EVENT_UDMACH21SSEL_EV_S 0 -#define EVENT_UDMACH21SSEL_EV_SWEV0 0x00000064 +#define EVENT_UDMACH21SSEL_EV_W 7 +#define EVENT_UDMACH21SSEL_EV_M 0x0000007F +#define EVENT_UDMACH21SSEL_EV_S 0 +#define EVENT_UDMACH21SSEL_EV_SWEV0 0x00000064 //***************************************************************************** // @@ -2825,10 +2825,10 @@ // Read only selection value // ENUMs: // SWEV0 Software event 0, triggered by SWEV.SWEV0 -#define EVENT_UDMACH21BSEL_EV_W 7 -#define EVENT_UDMACH21BSEL_EV_M 0x0000007F -#define EVENT_UDMACH21BSEL_EV_S 0 -#define EVENT_UDMACH21BSEL_EV_SWEV0 0x00000064 +#define EVENT_UDMACH21BSEL_EV_W 7 +#define EVENT_UDMACH21BSEL_EV_M 0x0000007F +#define EVENT_UDMACH21BSEL_EV_S 0 +#define EVENT_UDMACH21BSEL_EV_SWEV0 0x00000064 //***************************************************************************** // @@ -2840,10 +2840,10 @@ // Read only selection value // ENUMs: // SWEV1 Software event 1, triggered by SWEV.SWEV1 -#define EVENT_UDMACH22SSEL_EV_W 7 -#define EVENT_UDMACH22SSEL_EV_M 0x0000007F -#define EVENT_UDMACH22SSEL_EV_S 0 -#define EVENT_UDMACH22SSEL_EV_SWEV1 0x00000065 +#define EVENT_UDMACH22SSEL_EV_W 7 +#define EVENT_UDMACH22SSEL_EV_M 0x0000007F +#define EVENT_UDMACH22SSEL_EV_S 0 +#define EVENT_UDMACH22SSEL_EV_SWEV1 0x00000065 //***************************************************************************** // @@ -2855,10 +2855,10 @@ // Read only selection value // ENUMs: // SWEV1 Software event 1, triggered by SWEV.SWEV1 -#define EVENT_UDMACH22BSEL_EV_W 7 -#define EVENT_UDMACH22BSEL_EV_M 0x0000007F -#define EVENT_UDMACH22BSEL_EV_S 0 -#define EVENT_UDMACH22BSEL_EV_SWEV1 0x00000065 +#define EVENT_UDMACH22BSEL_EV_W 7 +#define EVENT_UDMACH22BSEL_EV_M 0x0000007F +#define EVENT_UDMACH22BSEL_EV_S 0 +#define EVENT_UDMACH22BSEL_EV_SWEV1 0x00000065 //***************************************************************************** // @@ -2870,10 +2870,10 @@ // Read only selection value // ENUMs: // SWEV2 Software event 2, triggered by SWEV.SWEV2 -#define EVENT_UDMACH23SSEL_EV_W 7 -#define EVENT_UDMACH23SSEL_EV_M 0x0000007F -#define EVENT_UDMACH23SSEL_EV_S 0 -#define EVENT_UDMACH23SSEL_EV_SWEV2 0x00000066 +#define EVENT_UDMACH23SSEL_EV_W 7 +#define EVENT_UDMACH23SSEL_EV_M 0x0000007F +#define EVENT_UDMACH23SSEL_EV_S 0 +#define EVENT_UDMACH23SSEL_EV_SWEV2 0x00000066 //***************************************************************************** // @@ -2885,10 +2885,10 @@ // Read only selection value // ENUMs: // SWEV2 Software event 2, triggered by SWEV.SWEV2 -#define EVENT_UDMACH23BSEL_EV_W 7 -#define EVENT_UDMACH23BSEL_EV_M 0x0000007F -#define EVENT_UDMACH23BSEL_EV_S 0 -#define EVENT_UDMACH23BSEL_EV_SWEV2 0x00000066 +#define EVENT_UDMACH23BSEL_EV_W 7 +#define EVENT_UDMACH23BSEL_EV_M 0x0000007F +#define EVENT_UDMACH23BSEL_EV_S 0 +#define EVENT_UDMACH23BSEL_EV_SWEV2 0x00000066 //***************************************************************************** // @@ -2900,10 +2900,10 @@ // Read only selection value // ENUMs: // SWEV3 Software event 3, triggered by SWEV.SWEV3 -#define EVENT_UDMACH24SSEL_EV_W 7 -#define EVENT_UDMACH24SSEL_EV_M 0x0000007F -#define EVENT_UDMACH24SSEL_EV_S 0 -#define EVENT_UDMACH24SSEL_EV_SWEV3 0x00000067 +#define EVENT_UDMACH24SSEL_EV_W 7 +#define EVENT_UDMACH24SSEL_EV_M 0x0000007F +#define EVENT_UDMACH24SSEL_EV_S 0 +#define EVENT_UDMACH24SSEL_EV_SWEV3 0x00000067 //***************************************************************************** // @@ -2915,10 +2915,10 @@ // Read only selection value // ENUMs: // SWEV3 Software event 3, triggered by SWEV.SWEV3 -#define EVENT_UDMACH24BSEL_EV_W 7 -#define EVENT_UDMACH24BSEL_EV_M 0x0000007F -#define EVENT_UDMACH24BSEL_EV_S 0 -#define EVENT_UDMACH24BSEL_EV_SWEV3 0x00000067 +#define EVENT_UDMACH24BSEL_EV_W 7 +#define EVENT_UDMACH24BSEL_EV_M 0x0000007F +#define EVENT_UDMACH24BSEL_EV_S 0 +#define EVENT_UDMACH24BSEL_EV_SWEV3 0x00000067 //***************************************************************************** // @@ -3004,44 +3004,44 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT3ACAPTSEL_EV_W 7 -#define EVENT_GPT3ACAPTSEL_EV_M 0x0000007F -#define EVENT_GPT3ACAPTSEL_EV_S 0 -#define EVENT_GPT3ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT3ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT3ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT3ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT3ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT7 0x0000005C -#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT6 0x0000005B -#define EVENT_GPT3ACAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT3ACAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT3ACAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT3ACAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT3ACAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT3ACAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT3ACAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT3ACAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT3ACAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT3ACAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT3ACAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT3ACAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT3ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT3ACAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT3ACAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT3ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT3ACAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT3ACAPTSEL_EV_W 7 +#define EVENT_GPT3ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT3ACAPTSEL_EV_S 0 +#define EVENT_GPT3ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT3ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT3ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT3ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT3ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_GPT3ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT3ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT3ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT3ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT3ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT3ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT3ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT3ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT3ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT3ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT3ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT3ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT3ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT3ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT3ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT3ACAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -3127,44 +3127,44 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT3BCAPTSEL_EV_W 7 -#define EVENT_GPT3BCAPTSEL_EV_M 0x0000007F -#define EVENT_GPT3BCAPTSEL_EV_S 0 -#define EVENT_GPT3BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT3BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT3BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT3BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT3BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT7 0x0000005C -#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT6 0x0000005B -#define EVENT_GPT3BCAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT3BCAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT3BCAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT3BCAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT3BCAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT3BCAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT3BCAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT3BCAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT3BCAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT3BCAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT3BCAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT3BCAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT3BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT3BCAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT3BCAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT3BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT3BCAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT3BCAPTSEL_EV_W 7 +#define EVENT_GPT3BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT3BCAPTSEL_EV_S 0 +#define EVENT_GPT3BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT3BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT3BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT3BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT3BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_GPT3BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT3BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT3BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT3BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT3BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT3BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT3BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT3BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT3BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT3BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT3BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT3BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT3BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT3BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT3BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT3BCAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -3188,19 +3188,19 @@ // GPT2B GPT2B interrupt event, controlled by GPT2:TBMR // GPT2A GPT2A interrupt event, controlled by GPT2:TAMR // NONE Always inactive -#define EVENT_AUXSEL0_EV_W 7 -#define EVENT_AUXSEL0_EV_M 0x0000007F -#define EVENT_AUXSEL0_EV_S 0 -#define EVENT_AUXSEL0_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_AUXSEL0_EV_GPT1B 0x00000013 -#define EVENT_AUXSEL0_EV_GPT1A 0x00000012 -#define EVENT_AUXSEL0_EV_GPT0B 0x00000011 -#define EVENT_AUXSEL0_EV_GPT0A 0x00000010 -#define EVENT_AUXSEL0_EV_GPT3B 0x0000000F -#define EVENT_AUXSEL0_EV_GPT3A 0x0000000E -#define EVENT_AUXSEL0_EV_GPT2B 0x0000000D -#define EVENT_AUXSEL0_EV_GPT2A 0x0000000C -#define EVENT_AUXSEL0_EV_NONE 0x00000000 +#define EVENT_AUXSEL0_EV_W 7 +#define EVENT_AUXSEL0_EV_M 0x0000007F +#define EVENT_AUXSEL0_EV_S 0 +#define EVENT_AUXSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_AUXSEL0_EV_GPT1B 0x00000013 +#define EVENT_AUXSEL0_EV_GPT1A 0x00000012 +#define EVENT_AUXSEL0_EV_GPT0B 0x00000011 +#define EVENT_AUXSEL0_EV_GPT0A 0x00000010 +#define EVENT_AUXSEL0_EV_GPT3B 0x0000000F +#define EVENT_AUXSEL0_EV_GPT3A 0x0000000E +#define EVENT_AUXSEL0_EV_GPT2B 0x0000000D +#define EVENT_AUXSEL0_EV_GPT2A 0x0000000C +#define EVENT_AUXSEL0_EV_NONE 0x00000000 //***************************************************************************** // @@ -3213,10 +3213,10 @@ // ENUMs: // WDT_NMI Watchdog non maskable interrupt event, controlled // by WDT:CTL.INTTYPE -#define EVENT_CM3NMISEL0_EV_W 7 -#define EVENT_CM3NMISEL0_EV_M 0x0000007F -#define EVENT_CM3NMISEL0_EV_S 0 -#define EVENT_CM3NMISEL0_EV_WDT_NMI 0x00000063 +#define EVENT_CM3NMISEL0_EV_W 7 +#define EVENT_CM3NMISEL0_EV_M 0x0000007F +#define EVENT_CM3NMISEL0_EV_S 0 +#define EVENT_CM3NMISEL0_EV_WDT_NMI 0x00000063 //***************************************************************************** // @@ -3232,11 +3232,11 @@ // ENUMs: // ALWAYS_ACTIVE Always asserted // NONE Always inactive -#define EVENT_I2SSTMPSEL0_EV_W 7 -#define EVENT_I2SSTMPSEL0_EV_M 0x0000007F -#define EVENT_I2SSTMPSEL0_EV_S 0 -#define EVENT_I2SSTMPSEL0_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_I2SSTMPSEL0_EV_NONE 0x00000000 +#define EVENT_I2SSTMPSEL0_EV_W 7 +#define EVENT_I2SSTMPSEL0_EV_M 0x0000007F +#define EVENT_I2SSTMPSEL0_EV_S 0 +#define EVENT_I2SSTMPSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_I2SSTMPSEL0_EV_NONE 0x00000000 //***************************************************************************** // @@ -3253,12 +3253,12 @@ // ALWAYS_ACTIVE Always asserted // CPU_HALTED CPU halted // NONE Always inactive -#define EVENT_FRZSEL0_EV_W 7 -#define EVENT_FRZSEL0_EV_M 0x0000007F -#define EVENT_FRZSEL0_EV_S 0 -#define EVENT_FRZSEL0_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_FRZSEL0_EV_CPU_HALTED 0x00000078 -#define EVENT_FRZSEL0_EV_NONE 0x00000000 +#define EVENT_FRZSEL0_EV_W 7 +#define EVENT_FRZSEL0_EV_M 0x0000007F +#define EVENT_FRZSEL0_EV_S 0 +#define EVENT_FRZSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_FRZSEL0_EV_CPU_HALTED 0x00000078 +#define EVENT_FRZSEL0_EV_NONE 0x00000000 //***************************************************************************** // @@ -3268,34 +3268,33 @@ // Field: [24] SWEV3 // // Writing "1" to this bit when the value is "0" triggers the Software 3 event. -#define EVENT_SWEV_SWEV3 0x01000000 -#define EVENT_SWEV_SWEV3_BITN 24 -#define EVENT_SWEV_SWEV3_M 0x01000000 -#define EVENT_SWEV_SWEV3_S 24 +#define EVENT_SWEV_SWEV3 0x01000000 +#define EVENT_SWEV_SWEV3_BITN 24 +#define EVENT_SWEV_SWEV3_M 0x01000000 +#define EVENT_SWEV_SWEV3_S 24 // Field: [16] SWEV2 // // Writing "1" to this bit when the value is "0" triggers the Software 2 event. -#define EVENT_SWEV_SWEV2 0x00010000 -#define EVENT_SWEV_SWEV2_BITN 16 -#define EVENT_SWEV_SWEV2_M 0x00010000 -#define EVENT_SWEV_SWEV2_S 16 +#define EVENT_SWEV_SWEV2 0x00010000 +#define EVENT_SWEV_SWEV2_BITN 16 +#define EVENT_SWEV_SWEV2_M 0x00010000 +#define EVENT_SWEV_SWEV2_S 16 // Field: [8] SWEV1 // // Writing "1" to this bit when the value is "0" triggers the Software 1 event. -#define EVENT_SWEV_SWEV1 0x00000100 -#define EVENT_SWEV_SWEV1_BITN 8 -#define EVENT_SWEV_SWEV1_M 0x00000100 -#define EVENT_SWEV_SWEV1_S 8 +#define EVENT_SWEV_SWEV1 0x00000100 +#define EVENT_SWEV_SWEV1_BITN 8 +#define EVENT_SWEV_SWEV1_M 0x00000100 +#define EVENT_SWEV_SWEV1_S 8 // Field: [0] SWEV0 // // Writing "1" to this bit when the value is "0" triggers the Software 0 event. -#define EVENT_SWEV_SWEV0 0x00000001 -#define EVENT_SWEV_SWEV0_BITN 0 -#define EVENT_SWEV_SWEV0_M 0x00000001 -#define EVENT_SWEV_SWEV0_S 0 - +#define EVENT_SWEV_SWEV0 0x00000001 +#define EVENT_SWEV_SWEV0_BITN 0 +#define EVENT_SWEV_SWEV0_M 0x00000001 +#define EVENT_SWEV_SWEV0_S 0 #endif // __EVENT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_fcfg1.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_fcfg1.h index 273b87c..c86b7a3 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_fcfg1.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_fcfg1.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_fcfg1_h -* Revised: 2017-02-06 19:32:22 +0100 (Mon, 06 Feb 2017) -* Revision: 48408 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_fcfg1_h + * Revised: 2017-02-06 19:32:22 +0100 (Mon, 06 Feb 2017) + * Revision: 48408 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_FCFG1_H__ #define __HW_FCFG1_H__ @@ -44,248 +44,248 @@ // //***************************************************************************** // Misc configurations -#define FCFG1_O_MISC_CONF_1 0x000000A0 +#define FCFG1_O_MISC_CONF_1 0x000000A0 // Internal -#define FCFG1_O_MISC_CONF_2 0x000000A4 +#define FCFG1_O_MISC_CONF_2 0x000000A4 // Internal -#define FCFG1_O_CONFIG_RF_FRONTEND_DIV5 0x000000C4 +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV5 0x000000C4 // Internal -#define FCFG1_O_CONFIG_RF_FRONTEND_DIV6 0x000000C8 +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV6 0x000000C8 // Internal -#define FCFG1_O_CONFIG_RF_FRONTEND_DIV10 0x000000CC +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV10 0x000000CC // Internal -#define FCFG1_O_CONFIG_RF_FRONTEND_DIV12 0x000000D0 +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV12 0x000000D0 // Internal -#define FCFG1_O_CONFIG_RF_FRONTEND_DIV15 0x000000D4 +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV15 0x000000D4 // Internal -#define FCFG1_O_CONFIG_RF_FRONTEND_DIV30 0x000000D8 +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV30 0x000000D8 // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV5 0x000000DC +#define FCFG1_O_CONFIG_SYNTH_DIV5 0x000000DC // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV6 0x000000E0 +#define FCFG1_O_CONFIG_SYNTH_DIV6 0x000000E0 // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV10 0x000000E4 +#define FCFG1_O_CONFIG_SYNTH_DIV10 0x000000E4 // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV12 0x000000E8 +#define FCFG1_O_CONFIG_SYNTH_DIV12 0x000000E8 // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV15 0x000000EC +#define FCFG1_O_CONFIG_SYNTH_DIV15 0x000000EC // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV30 0x000000F0 +#define FCFG1_O_CONFIG_SYNTH_DIV30 0x000000F0 // Internal -#define FCFG1_O_CONFIG_MISC_ADC_DIV5 0x000000F4 +#define FCFG1_O_CONFIG_MISC_ADC_DIV5 0x000000F4 // Internal -#define FCFG1_O_CONFIG_MISC_ADC_DIV6 0x000000F8 +#define FCFG1_O_CONFIG_MISC_ADC_DIV6 0x000000F8 // Internal -#define FCFG1_O_CONFIG_MISC_ADC_DIV10 0x000000FC +#define FCFG1_O_CONFIG_MISC_ADC_DIV10 0x000000FC // Internal -#define FCFG1_O_CONFIG_MISC_ADC_DIV12 0x00000100 +#define FCFG1_O_CONFIG_MISC_ADC_DIV12 0x00000100 // Internal -#define FCFG1_O_CONFIG_MISC_ADC_DIV15 0x00000104 +#define FCFG1_O_CONFIG_MISC_ADC_DIV15 0x00000104 // Internal -#define FCFG1_O_CONFIG_MISC_ADC_DIV30 0x00000108 +#define FCFG1_O_CONFIG_MISC_ADC_DIV30 0x00000108 // Shadow of EFUSE:DIE_ID_0 -#define FCFG1_O_SHDW_DIE_ID_0 0x00000118 +#define FCFG1_O_SHDW_DIE_ID_0 0x00000118 // Shadow of EFUSE:DIE_ID_1 -#define FCFG1_O_SHDW_DIE_ID_1 0x0000011C +#define FCFG1_O_SHDW_DIE_ID_1 0x0000011C // Shadow of EFUSE:DIE_ID_2 -#define FCFG1_O_SHDW_DIE_ID_2 0x00000120 +#define FCFG1_O_SHDW_DIE_ID_2 0x00000120 // Shadow of EFUSE:DIE_ID_3 -#define FCFG1_O_SHDW_DIE_ID_3 0x00000124 +#define FCFG1_O_SHDW_DIE_ID_3 0x00000124 // Internal -#define FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM 0x00000138 +#define FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM 0x00000138 // Internal -#define FCFG1_O_SHDW_ANA_TRIM 0x0000013C +#define FCFG1_O_SHDW_ANA_TRIM 0x0000013C -#define FCFG1_O_FLASH_NUMBER 0x00000164 +#define FCFG1_O_FLASH_NUMBER 0x00000164 -#define FCFG1_O_FLASH_COORDINATE 0x0000016C +#define FCFG1_O_FLASH_COORDINATE 0x0000016C // Internal -#define FCFG1_O_FLASH_E_P 0x00000170 +#define FCFG1_O_FLASH_E_P 0x00000170 // Internal -#define FCFG1_O_FLASH_C_E_P_R 0x00000174 +#define FCFG1_O_FLASH_C_E_P_R 0x00000174 // Internal -#define FCFG1_O_FLASH_P_R_PV 0x00000178 +#define FCFG1_O_FLASH_P_R_PV 0x00000178 // Internal -#define FCFG1_O_FLASH_EH_SEQ 0x0000017C +#define FCFG1_O_FLASH_EH_SEQ 0x0000017C // Internal -#define FCFG1_O_FLASH_VHV_E 0x00000180 +#define FCFG1_O_FLASH_VHV_E 0x00000180 // Internal -#define FCFG1_O_FLASH_PP 0x00000184 +#define FCFG1_O_FLASH_PP 0x00000184 // Internal -#define FCFG1_O_FLASH_PROG_EP 0x00000188 +#define FCFG1_O_FLASH_PROG_EP 0x00000188 // Internal -#define FCFG1_O_FLASH_ERA_PW 0x0000018C +#define FCFG1_O_FLASH_ERA_PW 0x0000018C // Internal -#define FCFG1_O_FLASH_VHV 0x00000190 +#define FCFG1_O_FLASH_VHV 0x00000190 // Internal -#define FCFG1_O_FLASH_VHV_PV 0x00000194 +#define FCFG1_O_FLASH_VHV_PV 0x00000194 // Internal -#define FCFG1_O_FLASH_V 0x00000198 +#define FCFG1_O_FLASH_V 0x00000198 // User Identification. -#define FCFG1_O_USER_ID 0x00000294 +#define FCFG1_O_USER_ID 0x00000294 // Internal -#define FCFG1_O_FLASH_OTP_DATA3 0x000002B0 +#define FCFG1_O_FLASH_OTP_DATA3 0x000002B0 // Internal -#define FCFG1_O_ANA2_TRIM 0x000002B4 +#define FCFG1_O_ANA2_TRIM 0x000002B4 // Internal -#define FCFG1_O_LDO_TRIM 0x000002B8 +#define FCFG1_O_LDO_TRIM 0x000002B8 // Internal -#define FCFG1_O_BAT_RC_LDO_TRIM 0x000002BC +#define FCFG1_O_BAT_RC_LDO_TRIM 0x000002BC // MAC BLE Address 0 -#define FCFG1_O_MAC_BLE_0 0x000002E8 +#define FCFG1_O_MAC_BLE_0 0x000002E8 // MAC BLE Address 1 -#define FCFG1_O_MAC_BLE_1 0x000002EC +#define FCFG1_O_MAC_BLE_1 0x000002EC // MAC IEEE 802.15.4 Address 0 -#define FCFG1_O_MAC_15_4_0 0x000002F0 +#define FCFG1_O_MAC_15_4_0 0x000002F0 // MAC IEEE 802.15.4 Address 1 -#define FCFG1_O_MAC_15_4_1 0x000002F4 +#define FCFG1_O_MAC_15_4_1 0x000002F4 // Internal -#define FCFG1_O_FLASH_OTP_DATA4 0x00000308 +#define FCFG1_O_FLASH_OTP_DATA4 0x00000308 // Miscellaneous Trim Parameters -#define FCFG1_O_MISC_TRIM 0x0000030C +#define FCFG1_O_MISC_TRIM 0x0000030C // Internal -#define FCFG1_O_RCOSC_HF_TEMPCOMP 0x00000310 +#define FCFG1_O_RCOSC_HF_TEMPCOMP 0x00000310 // Internal -#define FCFG1_O_TRIM_CAL_REVISION 0x00000314 +#define FCFG1_O_TRIM_CAL_REVISION 0x00000314 // IcePick Device Identification -#define FCFG1_O_ICEPICK_DEVICE_ID 0x00000318 +#define FCFG1_O_ICEPICK_DEVICE_ID 0x00000318 // Factory Configuration (FCFG1) Revision -#define FCFG1_O_FCFG1_REVISION 0x0000031C +#define FCFG1_O_FCFG1_REVISION 0x0000031C // Misc OTP Data -#define FCFG1_O_MISC_OTP_DATA 0x00000320 +#define FCFG1_O_MISC_OTP_DATA 0x00000320 // IO Configuration -#define FCFG1_O_IOCONF 0x00000344 +#define FCFG1_O_IOCONF 0x00000344 // Internal -#define FCFG1_O_CONFIG_IF_ADC 0x0000034C +#define FCFG1_O_CONFIG_IF_ADC 0x0000034C // Internal -#define FCFG1_O_CONFIG_OSC_TOP 0x00000350 +#define FCFG1_O_CONFIG_OSC_TOP 0x00000350 // Internal -#define FCFG1_O_CONFIG_RF_FRONTEND 0x00000354 +#define FCFG1_O_CONFIG_RF_FRONTEND 0x00000354 // Internal -#define FCFG1_O_CONFIG_SYNTH 0x00000358 +#define FCFG1_O_CONFIG_SYNTH 0x00000358 // AUX_ADC Gain in Absolute Reference Mode -#define FCFG1_O_SOC_ADC_ABS_GAIN 0x0000035C +#define FCFG1_O_SOC_ADC_ABS_GAIN 0x0000035C // AUX_ADC Gain in Relative Reference Mode -#define FCFG1_O_SOC_ADC_REL_GAIN 0x00000360 +#define FCFG1_O_SOC_ADC_REL_GAIN 0x00000360 // AUX_ADC Temperature Offsets in Absolute Reference Mode -#define FCFG1_O_SOC_ADC_OFFSET_INT 0x00000368 +#define FCFG1_O_SOC_ADC_OFFSET_INT 0x00000368 // Internal -#define FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT 0x0000036C +#define FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT 0x0000036C // Internal -#define FCFG1_O_AMPCOMP_TH1 0x00000370 +#define FCFG1_O_AMPCOMP_TH1 0x00000370 // Internal -#define FCFG1_O_AMPCOMP_TH2 0x00000374 +#define FCFG1_O_AMPCOMP_TH2 0x00000374 // Internal -#define FCFG1_O_AMPCOMP_CTRL1 0x00000378 +#define FCFG1_O_AMPCOMP_CTRL1 0x00000378 // Internal -#define FCFG1_O_ANABYPASS_VALUE2 0x0000037C +#define FCFG1_O_ANABYPASS_VALUE2 0x0000037C // Internal -#define FCFG1_O_CONFIG_MISC_ADC 0x00000380 +#define FCFG1_O_CONFIG_MISC_ADC 0x00000380 // Internal -#define FCFG1_O_VOLT_TRIM 0x00000388 +#define FCFG1_O_VOLT_TRIM 0x00000388 // OSC Configuration -#define FCFG1_O_OSC_CONF 0x0000038C +#define FCFG1_O_OSC_CONF 0x0000038C // Internal -#define FCFG1_O_FREQ_OFFSET 0x00000390 +#define FCFG1_O_FREQ_OFFSET 0x00000390 // Internal -#define FCFG1_O_CAP_TRIM 0x00000394 +#define FCFG1_O_CAP_TRIM 0x00000394 // Internal -#define FCFG1_O_MISC_OTP_DATA_1 0x00000398 +#define FCFG1_O_MISC_OTP_DATA_1 0x00000398 // Power Down Current Control 20C -#define FCFG1_O_PWD_CURR_20C 0x0000039C +#define FCFG1_O_PWD_CURR_20C 0x0000039C // Power Down Current Control 35C -#define FCFG1_O_PWD_CURR_35C 0x000003A0 +#define FCFG1_O_PWD_CURR_35C 0x000003A0 // Power Down Current Control 50C -#define FCFG1_O_PWD_CURR_50C 0x000003A4 +#define FCFG1_O_PWD_CURR_50C 0x000003A4 // Power Down Current Control 65C -#define FCFG1_O_PWD_CURR_65C 0x000003A8 +#define FCFG1_O_PWD_CURR_65C 0x000003A8 // Power Down Current Control 80C -#define FCFG1_O_PWD_CURR_80C 0x000003AC +#define FCFG1_O_PWD_CURR_80C 0x000003AC // Power Down Current Control 95C -#define FCFG1_O_PWD_CURR_95C 0x000003B0 +#define FCFG1_O_PWD_CURR_95C 0x000003B0 // Power Down Current Control 110C -#define FCFG1_O_PWD_CURR_110C 0x000003B4 +#define FCFG1_O_PWD_CURR_110C 0x000003B4 // Power Down Current Control 125C -#define FCFG1_O_PWD_CURR_125C 0x000003B8 +#define FCFG1_O_PWD_CURR_125C 0x000003B8 //***************************************************************************** // @@ -298,9 +298,9 @@ // Any test of this field by SW should be implemented as a 'greater or equal' // comparison as signed integer. // Value may change without warning. -#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_W 8 -#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M 0x000000FF -#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S 0 +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_W 8 +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M 0x000000FF +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S 0 //***************************************************************************** // @@ -310,9 +310,9 @@ // Field: [7:0] HPOSC_COMP_P3 // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W 8 -#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_M 0x000000FF -#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S 0 +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W 8 +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_M 0x000000FF +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S 0 //***************************************************************************** // @@ -322,37 +322,37 @@ // Field: [31:28] IFAMP_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_S 28 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_S 28 // Field: [27:24] LNA_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_S 24 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_S 24 // Field: [23:19] IFAMP_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_S 19 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_S 19 // Field: [18:14] CTL_PA0_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_S 14 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_S 14 // Field: [6:0] RFLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_M 0x0000007F -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -362,37 +362,37 @@ // Field: [31:28] IFAMP_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_S 28 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_S 28 // Field: [27:24] LNA_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_S 24 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_S 24 // Field: [23:19] IFAMP_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_S 19 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_S 19 // Field: [18:14] CTL_PA0_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_S 14 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_S 14 // Field: [6:0] RFLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_M 0x0000007F -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -402,37 +402,37 @@ // Field: [31:28] IFAMP_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_S 28 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_S 28 // Field: [27:24] LNA_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_S 24 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_S 24 // Field: [23:19] IFAMP_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_S 19 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_S 19 // Field: [18:14] CTL_PA0_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_S 14 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_S 14 // Field: [6:0] RFLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_M 0x0000007F -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -442,37 +442,37 @@ // Field: [31:28] IFAMP_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_S 28 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_S 28 // Field: [27:24] LNA_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_S 24 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_S 24 // Field: [23:19] IFAMP_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_S 19 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_S 19 // Field: [18:14] CTL_PA0_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_S 14 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_S 14 // Field: [6:0] RFLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_M 0x0000007F -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -482,37 +482,37 @@ // Field: [31:28] IFAMP_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_S 28 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_S 28 // Field: [27:24] LNA_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_S 24 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_S 24 // Field: [23:19] IFAMP_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_S 19 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_S 19 // Field: [18:14] CTL_PA0_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_S 14 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_S 14 // Field: [6:0] RFLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_M 0x0000007F -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -522,37 +522,37 @@ // Field: [31:28] IFAMP_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_S 28 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_S 28 // Field: [27:24] LNA_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_S 24 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_S 24 // Field: [23:19] IFAMP_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_S 19 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_S 19 // Field: [18:14] CTL_PA0_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_S 14 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_S 14 // Field: [6:0] RFLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_M 0x0000007F -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -562,32 +562,32 @@ // Field: [28] DISABLE_CORNER_CAP // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV5_DISABLE_CORNER_CAP 0x10000000 -#define FCFG1_CONFIG_SYNTH_DIV5_DISABLE_CORNER_CAP_BITN 28 -#define FCFG1_CONFIG_SYNTH_DIV5_DISABLE_CORNER_CAP_M 0x10000000 -#define FCFG1_CONFIG_SYNTH_DIV5_DISABLE_CORNER_CAP_S 28 +#define FCFG1_CONFIG_SYNTH_DIV5_DISABLE_CORNER_CAP 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV5_DISABLE_CORNER_CAP_BITN 28 +#define FCFG1_CONFIG_SYNTH_DIV5_DISABLE_CORNER_CAP_M 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV5_DISABLE_CORNER_CAP_S 28 // Field: [27:12] RFC_MDM_DEMIQMC0 // // Trim value for RF Core. // Value is read by RF Core ROM FW during RF Core initialization. -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5:0] SLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_M 0x0000003F -#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -597,32 +597,32 @@ // Field: [28] DISABLE_CORNER_CAP // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV6_DISABLE_CORNER_CAP 0x10000000 -#define FCFG1_CONFIG_SYNTH_DIV6_DISABLE_CORNER_CAP_BITN 28 -#define FCFG1_CONFIG_SYNTH_DIV6_DISABLE_CORNER_CAP_M 0x10000000 -#define FCFG1_CONFIG_SYNTH_DIV6_DISABLE_CORNER_CAP_S 28 +#define FCFG1_CONFIG_SYNTH_DIV6_DISABLE_CORNER_CAP 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV6_DISABLE_CORNER_CAP_BITN 28 +#define FCFG1_CONFIG_SYNTH_DIV6_DISABLE_CORNER_CAP_M 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV6_DISABLE_CORNER_CAP_S 28 // Field: [27:12] RFC_MDM_DEMIQMC0 // // Trim value for RF Core. // Value is read by RF Core ROM FW during RF Core initialization. -#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5:0] SLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_M 0x0000003F -#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -632,32 +632,32 @@ // Field: [28] DISABLE_CORNER_CAP // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV10_DISABLE_CORNER_CAP 0x10000000 -#define FCFG1_CONFIG_SYNTH_DIV10_DISABLE_CORNER_CAP_BITN 28 -#define FCFG1_CONFIG_SYNTH_DIV10_DISABLE_CORNER_CAP_M 0x10000000 -#define FCFG1_CONFIG_SYNTH_DIV10_DISABLE_CORNER_CAP_S 28 +#define FCFG1_CONFIG_SYNTH_DIV10_DISABLE_CORNER_CAP 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV10_DISABLE_CORNER_CAP_BITN 28 +#define FCFG1_CONFIG_SYNTH_DIV10_DISABLE_CORNER_CAP_M 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV10_DISABLE_CORNER_CAP_S 28 // Field: [27:12] RFC_MDM_DEMIQMC0 // // Trim value for RF Core. // Value is read by RF Core ROM FW during RF Core initialization. -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5:0] SLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_M 0x0000003F -#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -667,32 +667,32 @@ // Field: [28] DISABLE_CORNER_CAP // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV12_DISABLE_CORNER_CAP 0x10000000 -#define FCFG1_CONFIG_SYNTH_DIV12_DISABLE_CORNER_CAP_BITN 28 -#define FCFG1_CONFIG_SYNTH_DIV12_DISABLE_CORNER_CAP_M 0x10000000 -#define FCFG1_CONFIG_SYNTH_DIV12_DISABLE_CORNER_CAP_S 28 +#define FCFG1_CONFIG_SYNTH_DIV12_DISABLE_CORNER_CAP 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV12_DISABLE_CORNER_CAP_BITN 28 +#define FCFG1_CONFIG_SYNTH_DIV12_DISABLE_CORNER_CAP_M 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV12_DISABLE_CORNER_CAP_S 28 // Field: [27:12] RFC_MDM_DEMIQMC0 // // Trim value for RF Core. // Value is read by RF Core ROM FW during RF Core initialization. -#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5:0] SLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_M 0x0000003F -#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -702,32 +702,32 @@ // Field: [28] DISABLE_CORNER_CAP // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV15_DISABLE_CORNER_CAP 0x10000000 -#define FCFG1_CONFIG_SYNTH_DIV15_DISABLE_CORNER_CAP_BITN 28 -#define FCFG1_CONFIG_SYNTH_DIV15_DISABLE_CORNER_CAP_M 0x10000000 -#define FCFG1_CONFIG_SYNTH_DIV15_DISABLE_CORNER_CAP_S 28 +#define FCFG1_CONFIG_SYNTH_DIV15_DISABLE_CORNER_CAP 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV15_DISABLE_CORNER_CAP_BITN 28 +#define FCFG1_CONFIG_SYNTH_DIV15_DISABLE_CORNER_CAP_M 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV15_DISABLE_CORNER_CAP_S 28 // Field: [27:12] RFC_MDM_DEMIQMC0 // // Trim value for RF Core. // Value is read by RF Core ROM FW during RF Core initialization. -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5:0] SLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_M 0x0000003F -#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -737,32 +737,32 @@ // Field: [28] DISABLE_CORNER_CAP // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV30_DISABLE_CORNER_CAP 0x10000000 -#define FCFG1_CONFIG_SYNTH_DIV30_DISABLE_CORNER_CAP_BITN 28 -#define FCFG1_CONFIG_SYNTH_DIV30_DISABLE_CORNER_CAP_M 0x10000000 -#define FCFG1_CONFIG_SYNTH_DIV30_DISABLE_CORNER_CAP_S 28 +#define FCFG1_CONFIG_SYNTH_DIV30_DISABLE_CORNER_CAP 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV30_DISABLE_CORNER_CAP_BITN 28 +#define FCFG1_CONFIG_SYNTH_DIV30_DISABLE_CORNER_CAP_M 0x10000000 +#define FCFG1_CONFIG_SYNTH_DIV30_DISABLE_CORNER_CAP_S 28 // Field: [27:12] RFC_MDM_DEMIQMC0 // // Trim value for RF Core. // Value is read by RF Core ROM FW during RF Core initialization. -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5:0] SLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_M 0x0000003F -#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -772,30 +772,30 @@ // Field: [21:18] MIN_ALLOWED_RTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV5_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_MISC_ADC_DIV5_MIN_ALLOWED_RTRIM_M 0x003C0000 -#define FCFG1_CONFIG_MISC_ADC_DIV5_MIN_ALLOWED_RTRIM_S 18 +#define FCFG1_CONFIG_MISC_ADC_DIV5_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_MISC_ADC_DIV5_MIN_ALLOWED_RTRIM_M 0x003C0000 +#define FCFG1_CONFIG_MISC_ADC_DIV5_MIN_ALLOWED_RTRIM_S 18 // Field: [16:9] RSSI_OFFSET // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_M 0x0001FE00 -#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_S 9 +#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_S 9 // Field: [8:6] QUANTCTLTHRES // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_S 6 +#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_S 6 // Field: [5:0] DACTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_W 6 -#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_S 0 +#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_S 0 //***************************************************************************** // @@ -805,30 +805,30 @@ // Field: [21:18] MIN_ALLOWED_RTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV6_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_MISC_ADC_DIV6_MIN_ALLOWED_RTRIM_M 0x003C0000 -#define FCFG1_CONFIG_MISC_ADC_DIV6_MIN_ALLOWED_RTRIM_S 18 +#define FCFG1_CONFIG_MISC_ADC_DIV6_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_MISC_ADC_DIV6_MIN_ALLOWED_RTRIM_M 0x003C0000 +#define FCFG1_CONFIG_MISC_ADC_DIV6_MIN_ALLOWED_RTRIM_S 18 // Field: [16:9] RSSI_OFFSET // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_M 0x0001FE00 -#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_S 9 +#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_S 9 // Field: [8:6] QUANTCTLTHRES // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_S 6 +#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_S 6 // Field: [5:0] DACTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_W 6 -#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_S 0 +#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_S 0 //***************************************************************************** // @@ -838,30 +838,30 @@ // Field: [21:18] MIN_ALLOWED_RTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV10_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_MISC_ADC_DIV10_MIN_ALLOWED_RTRIM_M 0x003C0000 -#define FCFG1_CONFIG_MISC_ADC_DIV10_MIN_ALLOWED_RTRIM_S 18 +#define FCFG1_CONFIG_MISC_ADC_DIV10_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_MISC_ADC_DIV10_MIN_ALLOWED_RTRIM_M 0x003C0000 +#define FCFG1_CONFIG_MISC_ADC_DIV10_MIN_ALLOWED_RTRIM_S 18 // Field: [16:9] RSSI_OFFSET // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_M 0x0001FE00 -#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_S 9 +#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_S 9 // Field: [8:6] QUANTCTLTHRES // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_S 6 +#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_S 6 // Field: [5:0] DACTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_W 6 -#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_S 0 +#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_S 0 //***************************************************************************** // @@ -871,30 +871,30 @@ // Field: [21:18] MIN_ALLOWED_RTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV12_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_MISC_ADC_DIV12_MIN_ALLOWED_RTRIM_M 0x003C0000 -#define FCFG1_CONFIG_MISC_ADC_DIV12_MIN_ALLOWED_RTRIM_S 18 +#define FCFG1_CONFIG_MISC_ADC_DIV12_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_MISC_ADC_DIV12_MIN_ALLOWED_RTRIM_M 0x003C0000 +#define FCFG1_CONFIG_MISC_ADC_DIV12_MIN_ALLOWED_RTRIM_S 18 // Field: [16:9] RSSI_OFFSET // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_M 0x0001FE00 -#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_S 9 +#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_S 9 // Field: [8:6] QUANTCTLTHRES // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_S 6 +#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_S 6 // Field: [5:0] DACTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_W 6 -#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_S 0 +#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_S 0 //***************************************************************************** // @@ -904,30 +904,30 @@ // Field: [21:18] MIN_ALLOWED_RTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV15_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_MISC_ADC_DIV15_MIN_ALLOWED_RTRIM_M 0x003C0000 -#define FCFG1_CONFIG_MISC_ADC_DIV15_MIN_ALLOWED_RTRIM_S 18 +#define FCFG1_CONFIG_MISC_ADC_DIV15_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_MISC_ADC_DIV15_MIN_ALLOWED_RTRIM_M 0x003C0000 +#define FCFG1_CONFIG_MISC_ADC_DIV15_MIN_ALLOWED_RTRIM_S 18 // Field: [16:9] RSSI_OFFSET // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_M 0x0001FE00 -#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_S 9 +#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_S 9 // Field: [8:6] QUANTCTLTHRES // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_S 6 +#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_S 6 // Field: [5:0] DACTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_W 6 -#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_S 0 +#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_S 0 //***************************************************************************** // @@ -937,30 +937,30 @@ // Field: [21:18] MIN_ALLOWED_RTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_M 0x003C0000 -#define FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_S 18 +#define FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_M 0x003C0000 +#define FCFG1_CONFIG_MISC_ADC_DIV30_MIN_ALLOWED_RTRIM_S 18 // Field: [16:9] RSSI_OFFSET // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_M 0x0001FE00 -#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_S 9 +#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_S 9 // Field: [8:6] QUANTCTLTHRES // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_S 6 +#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_S 6 // Field: [5:0] DACTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_W 6 -#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_S 0 +#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_S 0 //***************************************************************************** // @@ -970,9 +970,9 @@ // Field: [31:0] ID_31_0 // // Shadow of the DIE_ID_0 register in eFuse row number 3 -#define FCFG1_SHDW_DIE_ID_0_ID_31_0_W 32 -#define FCFG1_SHDW_DIE_ID_0_ID_31_0_M 0xFFFFFFFF -#define FCFG1_SHDW_DIE_ID_0_ID_31_0_S 0 +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_W 32 +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_S 0 //***************************************************************************** // @@ -982,9 +982,9 @@ // Field: [31:0] ID_63_32 // // Shadow of the DIE_ID_1 register in eFuse row number 4 -#define FCFG1_SHDW_DIE_ID_1_ID_63_32_W 32 -#define FCFG1_SHDW_DIE_ID_1_ID_63_32_M 0xFFFFFFFF -#define FCFG1_SHDW_DIE_ID_1_ID_63_32_S 0 +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_W 32 +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_S 0 //***************************************************************************** // @@ -994,9 +994,9 @@ // Field: [31:0] ID_95_64 // // Shadow of the DIE_ID_2 register in eFuse row number 5 -#define FCFG1_SHDW_DIE_ID_2_ID_95_64_W 32 -#define FCFG1_SHDW_DIE_ID_2_ID_95_64_M 0xFFFFFFFF -#define FCFG1_SHDW_DIE_ID_2_ID_95_64_S 0 +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_W 32 +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_S 0 //***************************************************************************** // @@ -1006,9 +1006,9 @@ // Field: [31:0] ID_127_96 // // Shadow of the DIE_ID_3 register in eFuse row number 6 -#define FCFG1_SHDW_DIE_ID_3_ID_127_96_W 32 -#define FCFG1_SHDW_DIE_ID_3_ID_127_96_M 0xFFFFFFFF -#define FCFG1_SHDW_DIE_ID_3_ID_127_96_S 0 +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_W 32 +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_S 0 //***************************************************************************** // @@ -1018,54 +1018,54 @@ // Field: [28:27] SET_RCOSC_HF_COARSE_RESISTOR // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_W \ +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_W \ 2 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_M \ +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_M \ 0x18000000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_S \ +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_S \ 27 // Field: [26:23] TRIMMAG // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_W 4 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_M 0x07800000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_S 23 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_M 0x07800000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_S 23 // Field: [22:18] TRIMIREF // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_W 5 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_M 0x007C0000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_S 18 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_W 5 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_M 0x007C0000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_S 18 // Field: [17:16] ITRIM_DIG_LDO // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_W 2 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_M 0x00030000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_S 16 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_W 2 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_M 0x00030000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_S 16 // Field: [15:12] VTRIM_DIG // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_W 4 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_M 0x0000F000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_S 12 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_M 0x0000F000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_S 12 // Field: [11:8] VTRIM_COARSE // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_W 4 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_M 0x00000F00 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_S 8 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_M 0x00000F00 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_S 8 // Field: [7:0] RCOSCHF_CTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_W 8 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M 0x000000FF -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S 0 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_W 8 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M 0x000000FF +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S 0 //***************************************************************************** // @@ -1075,60 +1075,60 @@ // Field: [26:25] BOD_BANDGAP_TRIM_CNF // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_W 2 -#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_M 0x06000000 -#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_S 25 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_W 2 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_M 0x06000000 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_S 25 // Field: [24] VDDR_ENABLE_PG1 // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1 0x01000000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_BITN 24 -#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_M 0x01000000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_S 24 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1 0x01000000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_BITN 24 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_M 0x01000000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_S 24 // Field: [23] VDDR_OK_HYS // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS 0x00800000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_BITN 23 -#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_M 0x00800000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_S 23 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS 0x00800000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_BITN 23 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_M 0x00800000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_S 23 // Field: [22:21] IPTAT_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_W 2 -#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_M 0x00600000 -#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_S 21 +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_W 2 +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_M 0x00600000 +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_S 21 // Field: [20:16] VDDR_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_W 5 -#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M 0x001F0000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S 16 +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_W 5 +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M 0x001F0000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S 16 // Field: [15:11] TRIMBOD_INTMODE // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_W 5 -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_M 0x0000F800 -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_S 11 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_W 5 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_M 0x0000F800 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_S 11 // Field: [10:6] TRIMBOD_EXTMODE // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_W 5 -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_M 0x000007C0 -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_S 6 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_W 5 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_M 0x000007C0 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_S 6 // Field: [5:0] TRIMTEMP // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W 6 -#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_M 0x0000003F -#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_S 0 +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W 6 +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_M 0x0000003F +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_S 0 //***************************************************************************** // @@ -1138,9 +1138,9 @@ // Field: [31:0] LOT_NUMBER // // Number of the manufacturing lot that produced this unit. -#define FCFG1_FLASH_NUMBER_LOT_NUMBER_W 32 -#define FCFG1_FLASH_NUMBER_LOT_NUMBER_M 0xFFFFFFFF -#define FCFG1_FLASH_NUMBER_LOT_NUMBER_S 0 +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_W 32 +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_M 0xFFFFFFFF +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_S 0 //***************************************************************************** // @@ -1150,16 +1150,16 @@ // Field: [31:16] XCOORDINATE // // X coordinate of this unit on the wafer. -#define FCFG1_FLASH_COORDINATE_XCOORDINATE_W 16 -#define FCFG1_FLASH_COORDINATE_XCOORDINATE_M 0xFFFF0000 -#define FCFG1_FLASH_COORDINATE_XCOORDINATE_S 16 +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_W 16 +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_M 0xFFFF0000 +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_S 16 // Field: [15:0] YCOORDINATE // // Y coordinate of this unit on the wafer. -#define FCFG1_FLASH_COORDINATE_YCOORDINATE_W 16 -#define FCFG1_FLASH_COORDINATE_YCOORDINATE_M 0x0000FFFF -#define FCFG1_FLASH_COORDINATE_YCOORDINATE_S 0 +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_W 16 +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_M 0x0000FFFF +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_S 0 //***************************************************************************** // @@ -1169,30 +1169,30 @@ // Field: [31:24] PSU // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_E_P_PSU_W 8 -#define FCFG1_FLASH_E_P_PSU_M 0xFF000000 -#define FCFG1_FLASH_E_P_PSU_S 24 +#define FCFG1_FLASH_E_P_PSU_W 8 +#define FCFG1_FLASH_E_P_PSU_M 0xFF000000 +#define FCFG1_FLASH_E_P_PSU_S 24 // Field: [23:16] ESU // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_E_P_ESU_W 8 -#define FCFG1_FLASH_E_P_ESU_M 0x00FF0000 -#define FCFG1_FLASH_E_P_ESU_S 16 +#define FCFG1_FLASH_E_P_ESU_W 8 +#define FCFG1_FLASH_E_P_ESU_M 0x00FF0000 +#define FCFG1_FLASH_E_P_ESU_S 16 // Field: [15:8] PVSU // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_E_P_PVSU_W 8 -#define FCFG1_FLASH_E_P_PVSU_M 0x0000FF00 -#define FCFG1_FLASH_E_P_PVSU_S 8 +#define FCFG1_FLASH_E_P_PVSU_W 8 +#define FCFG1_FLASH_E_P_PVSU_M 0x0000FF00 +#define FCFG1_FLASH_E_P_PVSU_S 8 // Field: [7:0] EVSU // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_E_P_EVSU_W 8 -#define FCFG1_FLASH_E_P_EVSU_M 0x000000FF -#define FCFG1_FLASH_E_P_EVSU_S 0 +#define FCFG1_FLASH_E_P_EVSU_W 8 +#define FCFG1_FLASH_E_P_EVSU_M 0x000000FF +#define FCFG1_FLASH_E_P_EVSU_S 0 //***************************************************************************** // @@ -1202,30 +1202,30 @@ // Field: [31:24] RVSU // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_C_E_P_R_RVSU_W 8 -#define FCFG1_FLASH_C_E_P_R_RVSU_M 0xFF000000 -#define FCFG1_FLASH_C_E_P_R_RVSU_S 24 +#define FCFG1_FLASH_C_E_P_R_RVSU_W 8 +#define FCFG1_FLASH_C_E_P_R_RVSU_M 0xFF000000 +#define FCFG1_FLASH_C_E_P_R_RVSU_S 24 // Field: [23:16] PV_ACCESS // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_W 8 -#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_M 0x00FF0000 -#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_S 16 +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_W 8 +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_M 0x00FF0000 +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_S 16 // Field: [15:12] A_EXEZ_SETUP // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_W 4 -#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M 0x0000F000 -#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S 12 +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_W 4 +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M 0x0000F000 +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S 12 // Field: [11:0] CVSU // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_C_E_P_R_CVSU_W 12 -#define FCFG1_FLASH_C_E_P_R_CVSU_M 0x00000FFF -#define FCFG1_FLASH_C_E_P_R_CVSU_S 0 +#define FCFG1_FLASH_C_E_P_R_CVSU_W 12 +#define FCFG1_FLASH_C_E_P_R_CVSU_M 0x00000FFF +#define FCFG1_FLASH_C_E_P_R_CVSU_S 0 //***************************************************************************** // @@ -1235,30 +1235,30 @@ // Field: [31:24] PH // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_P_R_PV_PH_W 8 -#define FCFG1_FLASH_P_R_PV_PH_M 0xFF000000 -#define FCFG1_FLASH_P_R_PV_PH_S 24 +#define FCFG1_FLASH_P_R_PV_PH_W 8 +#define FCFG1_FLASH_P_R_PV_PH_M 0xFF000000 +#define FCFG1_FLASH_P_R_PV_PH_S 24 // Field: [23:16] RH // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_P_R_PV_RH_W 8 -#define FCFG1_FLASH_P_R_PV_RH_M 0x00FF0000 -#define FCFG1_FLASH_P_R_PV_RH_S 16 +#define FCFG1_FLASH_P_R_PV_RH_W 8 +#define FCFG1_FLASH_P_R_PV_RH_M 0x00FF0000 +#define FCFG1_FLASH_P_R_PV_RH_S 16 // Field: [15:8] PVH // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_P_R_PV_PVH_W 8 -#define FCFG1_FLASH_P_R_PV_PVH_M 0x0000FF00 -#define FCFG1_FLASH_P_R_PV_PVH_S 8 +#define FCFG1_FLASH_P_R_PV_PVH_W 8 +#define FCFG1_FLASH_P_R_PV_PVH_M 0x0000FF00 +#define FCFG1_FLASH_P_R_PV_PVH_S 8 // Field: [7:0] PVH2 // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_P_R_PV_PVH2_W 8 -#define FCFG1_FLASH_P_R_PV_PVH2_M 0x000000FF -#define FCFG1_FLASH_P_R_PV_PVH2_S 0 +#define FCFG1_FLASH_P_R_PV_PVH2_W 8 +#define FCFG1_FLASH_P_R_PV_PVH2_M 0x000000FF +#define FCFG1_FLASH_P_R_PV_PVH2_S 0 //***************************************************************************** // @@ -1268,30 +1268,30 @@ // Field: [31:24] EH // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_EH_SEQ_EH_W 8 -#define FCFG1_FLASH_EH_SEQ_EH_M 0xFF000000 -#define FCFG1_FLASH_EH_SEQ_EH_S 24 +#define FCFG1_FLASH_EH_SEQ_EH_W 8 +#define FCFG1_FLASH_EH_SEQ_EH_M 0xFF000000 +#define FCFG1_FLASH_EH_SEQ_EH_S 24 // Field: [23:16] SEQ // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_EH_SEQ_SEQ_W 8 -#define FCFG1_FLASH_EH_SEQ_SEQ_M 0x00FF0000 -#define FCFG1_FLASH_EH_SEQ_SEQ_S 16 +#define FCFG1_FLASH_EH_SEQ_SEQ_W 8 +#define FCFG1_FLASH_EH_SEQ_SEQ_M 0x00FF0000 +#define FCFG1_FLASH_EH_SEQ_SEQ_S 16 // Field: [15:12] VSTAT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_EH_SEQ_VSTAT_W 4 -#define FCFG1_FLASH_EH_SEQ_VSTAT_M 0x0000F000 -#define FCFG1_FLASH_EH_SEQ_VSTAT_S 12 +#define FCFG1_FLASH_EH_SEQ_VSTAT_W 4 +#define FCFG1_FLASH_EH_SEQ_VSTAT_M 0x0000F000 +#define FCFG1_FLASH_EH_SEQ_VSTAT_S 12 // Field: [11:0] SM_FREQUENCY // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_W 12 -#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_M 0x00000FFF -#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_S 0 +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_W 12 +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_M 0x00000FFF +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_S 0 //***************************************************************************** // @@ -1301,16 +1301,16 @@ // Field: [31:16] VHV_E_START // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_E_VHV_E_START_W 16 -#define FCFG1_FLASH_VHV_E_VHV_E_START_M 0xFFFF0000 -#define FCFG1_FLASH_VHV_E_VHV_E_START_S 16 +#define FCFG1_FLASH_VHV_E_VHV_E_START_W 16 +#define FCFG1_FLASH_VHV_E_VHV_E_START_M 0xFFFF0000 +#define FCFG1_FLASH_VHV_E_VHV_E_START_S 16 // Field: [15:0] VHV_E_STEP_HIGHT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_W 16 -#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M 0x0000FFFF -#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S 0 +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_W 16 +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M 0x0000FFFF +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S 0 //***************************************************************************** // @@ -1320,16 +1320,16 @@ // Field: [31:24] PUMP_SU // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PP_PUMP_SU_W 8 -#define FCFG1_FLASH_PP_PUMP_SU_M 0xFF000000 -#define FCFG1_FLASH_PP_PUMP_SU_S 24 +#define FCFG1_FLASH_PP_PUMP_SU_W 8 +#define FCFG1_FLASH_PP_PUMP_SU_M 0xFF000000 +#define FCFG1_FLASH_PP_PUMP_SU_S 24 // Field: [15:0] MAX_PP // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PP_MAX_PP_W 16 -#define FCFG1_FLASH_PP_MAX_PP_M 0x0000FFFF -#define FCFG1_FLASH_PP_MAX_PP_S 0 +#define FCFG1_FLASH_PP_MAX_PP_W 16 +#define FCFG1_FLASH_PP_MAX_PP_M 0x0000FFFF +#define FCFG1_FLASH_PP_MAX_PP_S 0 //***************************************************************************** // @@ -1339,16 +1339,16 @@ // Field: [31:16] MAX_EP // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PROG_EP_MAX_EP_W 16 -#define FCFG1_FLASH_PROG_EP_MAX_EP_M 0xFFFF0000 -#define FCFG1_FLASH_PROG_EP_MAX_EP_S 16 +#define FCFG1_FLASH_PROG_EP_MAX_EP_W 16 +#define FCFG1_FLASH_PROG_EP_MAX_EP_M 0xFFFF0000 +#define FCFG1_FLASH_PROG_EP_MAX_EP_S 16 // Field: [15:0] PROGRAM_PW // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_W 16 -#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_M 0x0000FFFF -#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_S 0 +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_W 16 +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_M 0x0000FFFF +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_S 0 //***************************************************************************** // @@ -1358,9 +1358,9 @@ // Field: [31:0] ERASE_PW // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_ERA_PW_ERASE_PW_W 32 -#define FCFG1_FLASH_ERA_PW_ERASE_PW_M 0xFFFFFFFF -#define FCFG1_FLASH_ERA_PW_ERASE_PW_S 0 +#define FCFG1_FLASH_ERA_PW_ERASE_PW_W 32 +#define FCFG1_FLASH_ERA_PW_ERASE_PW_M 0xFFFFFFFF +#define FCFG1_FLASH_ERA_PW_ERASE_PW_S 0 //***************************************************************************** // @@ -1370,30 +1370,30 @@ // Field: [27:24] TRIM13_P // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_TRIM13_P_W 4 -#define FCFG1_FLASH_VHV_TRIM13_P_M 0x0F000000 -#define FCFG1_FLASH_VHV_TRIM13_P_S 24 +#define FCFG1_FLASH_VHV_TRIM13_P_W 4 +#define FCFG1_FLASH_VHV_TRIM13_P_M 0x0F000000 +#define FCFG1_FLASH_VHV_TRIM13_P_S 24 // Field: [19:16] VHV_P // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_VHV_P_W 4 -#define FCFG1_FLASH_VHV_VHV_P_M 0x000F0000 -#define FCFG1_FLASH_VHV_VHV_P_S 16 +#define FCFG1_FLASH_VHV_VHV_P_W 4 +#define FCFG1_FLASH_VHV_VHV_P_M 0x000F0000 +#define FCFG1_FLASH_VHV_VHV_P_S 16 // Field: [11:8] TRIM13_E // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_TRIM13_E_W 4 -#define FCFG1_FLASH_VHV_TRIM13_E_M 0x00000F00 -#define FCFG1_FLASH_VHV_TRIM13_E_S 8 +#define FCFG1_FLASH_VHV_TRIM13_E_W 4 +#define FCFG1_FLASH_VHV_TRIM13_E_M 0x00000F00 +#define FCFG1_FLASH_VHV_TRIM13_E_S 8 // Field: [3:0] VHV_E // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_VHV_E_W 4 -#define FCFG1_FLASH_VHV_VHV_E_M 0x0000000F -#define FCFG1_FLASH_VHV_VHV_E_S 0 +#define FCFG1_FLASH_VHV_VHV_E_W 4 +#define FCFG1_FLASH_VHV_VHV_E_M 0x0000000F +#define FCFG1_FLASH_VHV_VHV_E_S 0 //***************************************************************************** // @@ -1403,30 +1403,30 @@ // Field: [27:24] TRIM13_PV // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_PV_TRIM13_PV_W 4 -#define FCFG1_FLASH_VHV_PV_TRIM13_PV_M 0x0F000000 -#define FCFG1_FLASH_VHV_PV_TRIM13_PV_S 24 +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_W 4 +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_M 0x0F000000 +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_S 24 // Field: [19:16] VHV_PV // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_PV_VHV_PV_W 4 -#define FCFG1_FLASH_VHV_PV_VHV_PV_M 0x000F0000 -#define FCFG1_FLASH_VHV_PV_VHV_PV_S 16 +#define FCFG1_FLASH_VHV_PV_VHV_PV_W 4 +#define FCFG1_FLASH_VHV_PV_VHV_PV_M 0x000F0000 +#define FCFG1_FLASH_VHV_PV_VHV_PV_S 16 // Field: [15:8] VCG2P5 // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_PV_VCG2P5_W 8 -#define FCFG1_FLASH_VHV_PV_VCG2P5_M 0x0000FF00 -#define FCFG1_FLASH_VHV_PV_VCG2P5_S 8 +#define FCFG1_FLASH_VHV_PV_VCG2P5_W 8 +#define FCFG1_FLASH_VHV_PV_VCG2P5_M 0x0000FF00 +#define FCFG1_FLASH_VHV_PV_VCG2P5_S 8 // Field: [7:0] VINH // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_PV_VINH_W 8 -#define FCFG1_FLASH_VHV_PV_VINH_M 0x000000FF -#define FCFG1_FLASH_VHV_PV_VINH_S 0 +#define FCFG1_FLASH_VHV_PV_VINH_W 8 +#define FCFG1_FLASH_VHV_PV_VINH_M 0x000000FF +#define FCFG1_FLASH_VHV_PV_VINH_S 0 //***************************************************************************** // @@ -1436,23 +1436,23 @@ // Field: [31:24] VSL_P // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_V_VSL_P_W 8 -#define FCFG1_FLASH_V_VSL_P_M 0xFF000000 -#define FCFG1_FLASH_V_VSL_P_S 24 +#define FCFG1_FLASH_V_VSL_P_W 8 +#define FCFG1_FLASH_V_VSL_P_M 0xFF000000 +#define FCFG1_FLASH_V_VSL_P_S 24 // Field: [23:16] VWL_P // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_V_VWL_P_W 8 -#define FCFG1_FLASH_V_VWL_P_M 0x00FF0000 -#define FCFG1_FLASH_V_VWL_P_S 16 +#define FCFG1_FLASH_V_VWL_P_W 8 +#define FCFG1_FLASH_V_VWL_P_M 0x00FF0000 +#define FCFG1_FLASH_V_VWL_P_S 16 // Field: [15:8] V_READ // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_V_V_READ_W 8 -#define FCFG1_FLASH_V_V_READ_M 0x0000FF00 -#define FCFG1_FLASH_V_V_READ_S 8 +#define FCFG1_FLASH_V_V_READ_W 8 +#define FCFG1_FLASH_V_V_READ_M 0x0000FF00 +#define FCFG1_FLASH_V_V_READ_S 8 //***************************************************************************** // @@ -1462,9 +1462,9 @@ // Field: [31:28] PG_REV // // Field used to distinguish revisions of the device. -#define FCFG1_USER_ID_PG_REV_W 4 -#define FCFG1_USER_ID_PG_REV_M 0xF0000000 -#define FCFG1_USER_ID_PG_REV_S 28 +#define FCFG1_USER_ID_PG_REV_W 4 +#define FCFG1_USER_ID_PG_REV_M 0xF0000000 +#define FCFG1_USER_ID_PG_REV_S 28 // Field: [27:26] VER // @@ -1473,9 +1473,9 @@ // 0x0: Bits [25:12] of this register has the stated meaning. // // Any other setting indicate a different encoding of these bits. -#define FCFG1_USER_ID_VER_W 2 -#define FCFG1_USER_ID_VER_M 0x0C000000 -#define FCFG1_USER_ID_VER_S 26 +#define FCFG1_USER_ID_VER_W 2 +#define FCFG1_USER_ID_VER_M 0x0C000000 +#define FCFG1_USER_ID_VER_S 26 // Field: [22:19] SEQUENCE // @@ -1483,9 +1483,9 @@ // // Used to differentiate between marketing/orderable product where other fields // of USER_ID is the same (temp range, flash size, voltage range etc) -#define FCFG1_USER_ID_SEQUENCE_W 4 -#define FCFG1_USER_ID_SEQUENCE_M 0x00780000 -#define FCFG1_USER_ID_SEQUENCE_S 19 +#define FCFG1_USER_ID_SEQUENCE_W 4 +#define FCFG1_USER_ID_SEQUENCE_M 0x00780000 +#define FCFG1_USER_ID_SEQUENCE_S 19 // Field: [18:16] PKG // @@ -1500,9 +1500,9 @@ // // Other values are reserved for future use. // Packages available for a specific device are shown in the device datasheet. -#define FCFG1_USER_ID_PKG_W 3 -#define FCFG1_USER_ID_PKG_M 0x00070000 -#define FCFG1_USER_ID_PKG_S 16 +#define FCFG1_USER_ID_PKG_W 3 +#define FCFG1_USER_ID_PKG_M 0x00070000 +#define FCFG1_USER_ID_PKG_S 16 // Field: [15:12] PROTOCOL // @@ -1515,9 +1515,9 @@ // // More than one protocol can be supported on same device - values above are // then combined. -#define FCFG1_USER_ID_PROTOCOL_W 4 -#define FCFG1_USER_ID_PROTOCOL_M 0x0000F000 -#define FCFG1_USER_ID_PROTOCOL_S 12 +#define FCFG1_USER_ID_PROTOCOL_W 4 +#define FCFG1_USER_ID_PROTOCOL_M 0x0000F000 +#define FCFG1_USER_ID_PROTOCOL_S 12 //***************************************************************************** // @@ -1527,45 +1527,45 @@ // Field: [31:23] EC_STEP_SIZE // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_W 9 -#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M 0xFF800000 -#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S 23 +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_W 9 +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M 0xFF800000 +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S 23 // Field: [22] DO_PRECOND // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND 0x00400000 -#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_BITN 22 -#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M 0x00400000 -#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S 22 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND 0x00400000 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_BITN 22 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M 0x00400000 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S 22 // Field: [21:18] MAX_EC_LEVEL // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_W 4 -#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M 0x003C0000 -#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S 18 +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_W 4 +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M 0x003C0000 +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S 18 // Field: [17:16] TRIM_1P7 // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_W 2 -#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M 0x00030000 -#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S 16 +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_W 2 +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M 0x00030000 +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S 16 // Field: [15:8] FLASH_SIZE // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_W 8 -#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_M 0x0000FF00 -#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_S 8 +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_W 8 +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_M 0x0000FF00 +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_S 8 // Field: [7:0] WAIT_SYSCODE // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_W 8 -#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_M 0x000000FF -#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_S 0 +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_W 8 +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_M 0x000000FF +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_S 0 //***************************************************************************** // @@ -1575,75 +1575,75 @@ // Field: [31] RCOSCHFCTRIMFRACT_EN // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN 0x80000000 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_BITN 31 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_M 0x80000000 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_S 31 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN 0x80000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_BITN 31 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_M 0x80000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_S 31 // Field: [30:26] RCOSCHFCTRIMFRACT // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_W 5 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_M 0x7C000000 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_S 26 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_W 5 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_M 0x7C000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_S 26 // Field: [24:23] SET_RCOSC_HF_FINE_RESISTOR // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_W 2 -#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_M 0x01800000 -#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_S 23 +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_W 2 +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_M 0x01800000 +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_S 23 // Field: [22] ATESTLF_UDIGLDO_IBIAS_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM 0x00400000 -#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_BITN 22 -#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_M 0x00400000 -#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_S 22 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM 0x00400000 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_BITN 22 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_M 0x00400000 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_S 22 // Field: [21:16] NANOAMP_RES_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_W 6 -#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_M 0x003F0000 -#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_S 16 +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_W 6 +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_M 0x003F0000 +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_S 16 // Field: [11] DITHER_EN // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DITHER_EN 0x00000800 -#define FCFG1_ANA2_TRIM_DITHER_EN_BITN 11 -#define FCFG1_ANA2_TRIM_DITHER_EN_M 0x00000800 -#define FCFG1_ANA2_TRIM_DITHER_EN_S 11 +#define FCFG1_ANA2_TRIM_DITHER_EN 0x00000800 +#define FCFG1_ANA2_TRIM_DITHER_EN_BITN 11 +#define FCFG1_ANA2_TRIM_DITHER_EN_M 0x00000800 +#define FCFG1_ANA2_TRIM_DITHER_EN_S 11 // Field: [10:8] DCDC_IPEAK // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DCDC_IPEAK_W 3 -#define FCFG1_ANA2_TRIM_DCDC_IPEAK_M 0x00000700 -#define FCFG1_ANA2_TRIM_DCDC_IPEAK_S 8 +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_W 3 +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_M 0x00000700 +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_S 8 // Field: [7:6] DEAD_TIME_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_W 2 -#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_M 0x000000C0 -#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_S 6 +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_W 2 +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_M 0x000000C0 +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_S 6 // Field: [5:3] DCDC_LOW_EN_SEL // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_W 3 -#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_M 0x00000038 -#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_S 3 +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_W 3 +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_M 0x00000038 +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_S 3 // Field: [2:0] DCDC_HIGH_EN_SEL // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_W 3 -#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_M 0x00000007 -#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_S 0 +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_W 3 +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_M 0x00000007 +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_S 0 //***************************************************************************** // @@ -1653,37 +1653,37 @@ // Field: [28:24] VDDR_TRIM_SLEEP // // Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_W 5 -#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M 0x1F000000 -#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S 24 +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_W 5 +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M 0x1F000000 +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S 24 // Field: [18:16] GLDO_CURSRC // // Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_GLDO_CURSRC_W 3 -#define FCFG1_LDO_TRIM_GLDO_CURSRC_M 0x00070000 -#define FCFG1_LDO_TRIM_GLDO_CURSRC_S 16 +#define FCFG1_LDO_TRIM_GLDO_CURSRC_W 3 +#define FCFG1_LDO_TRIM_GLDO_CURSRC_M 0x00070000 +#define FCFG1_LDO_TRIM_GLDO_CURSRC_S 16 // Field: [12:11] ITRIM_DIGLDO_LOAD // // Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_W 2 -#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_M 0x00001800 -#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_S 11 +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_W 2 +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_M 0x00001800 +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_S 11 // Field: [10:8] ITRIM_UDIGLDO // // Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_W 3 -#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_M 0x00000700 -#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_S 8 +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_W 3 +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_M 0x00000700 +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_S 8 // Field: [2:0] VTRIM_DELTA // // Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_VTRIM_DELTA_W 3 -#define FCFG1_LDO_TRIM_VTRIM_DELTA_M 0x00000007 -#define FCFG1_LDO_TRIM_VTRIM_DELTA_S 0 +#define FCFG1_LDO_TRIM_VTRIM_DELTA_W 3 +#define FCFG1_LDO_TRIM_VTRIM_DELTA_M 0x00000007 +#define FCFG1_LDO_TRIM_VTRIM_DELTA_S 0 //***************************************************************************** // @@ -1693,30 +1693,30 @@ // Field: [27:24] VTRIM_BOD // // Internal. Only to be used through TI provided API. -#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_W 4 -#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_M 0x0F000000 -#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_S 24 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_W 4 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_M 0x0F000000 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_S 24 // Field: [19:16] VTRIM_UDIG // // Internal. Only to be used through TI provided API. -#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_W 4 -#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_M 0x000F0000 -#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_S 16 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_W 4 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_M 0x000F0000 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_S 16 // Field: [11:8] RCOSCHF_ITUNE_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_W 4 -#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_M 0x00000F00 -#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_S 8 +#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_W 4 +#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_M 0x00000F00 +#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_S 8 // Field: [1:0] MEASUREPER // // Internal. Only to be used through TI provided API. -#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_W 2 -#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_M 0x00000003 -#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_S 0 +#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_W 2 +#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_M 0x00000003 +#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_S 0 //***************************************************************************** // @@ -1726,9 +1726,9 @@ // Field: [31:0] ADDR_0_31 // // The first 32-bits of the 64-bit MAC BLE address -#define FCFG1_MAC_BLE_0_ADDR_0_31_W 32 -#define FCFG1_MAC_BLE_0_ADDR_0_31_M 0xFFFFFFFF -#define FCFG1_MAC_BLE_0_ADDR_0_31_S 0 +#define FCFG1_MAC_BLE_0_ADDR_0_31_W 32 +#define FCFG1_MAC_BLE_0_ADDR_0_31_M 0xFFFFFFFF +#define FCFG1_MAC_BLE_0_ADDR_0_31_S 0 //***************************************************************************** // @@ -1738,9 +1738,9 @@ // Field: [31:0] ADDR_32_63 // // The last 32-bits of the 64-bit MAC BLE address -#define FCFG1_MAC_BLE_1_ADDR_32_63_W 32 -#define FCFG1_MAC_BLE_1_ADDR_32_63_M 0xFFFFFFFF -#define FCFG1_MAC_BLE_1_ADDR_32_63_S 0 +#define FCFG1_MAC_BLE_1_ADDR_32_63_W 32 +#define FCFG1_MAC_BLE_1_ADDR_32_63_M 0xFFFFFFFF +#define FCFG1_MAC_BLE_1_ADDR_32_63_S 0 //***************************************************************************** // @@ -1750,9 +1750,9 @@ // Field: [31:0] ADDR_0_31 // // The first 32-bits of the 64-bit MAC 15.4 address -#define FCFG1_MAC_15_4_0_ADDR_0_31_W 32 -#define FCFG1_MAC_15_4_0_ADDR_0_31_M 0xFFFFFFFF -#define FCFG1_MAC_15_4_0_ADDR_0_31_S 0 +#define FCFG1_MAC_15_4_0_ADDR_0_31_W 32 +#define FCFG1_MAC_15_4_0_ADDR_0_31_M 0xFFFFFFFF +#define FCFG1_MAC_15_4_0_ADDR_0_31_S 0 //***************************************************************************** // @@ -1762,9 +1762,9 @@ // Field: [31:0] ADDR_32_63 // // The last 32-bits of the 64-bit MAC 15.4 address -#define FCFG1_MAC_15_4_1_ADDR_32_63_W 32 -#define FCFG1_MAC_15_4_1_ADDR_32_63_M 0xFFFFFFFF -#define FCFG1_MAC_15_4_1_ADDR_32_63_S 0 +#define FCFG1_MAC_15_4_1_ADDR_32_63_W 32 +#define FCFG1_MAC_15_4_1_ADDR_32_63_M 0xFFFFFFFF +#define FCFG1_MAC_15_4_1_ADDR_32_63_S 0 //***************************************************************************** // @@ -1774,154 +1774,154 @@ // Field: [31] STANDBY_MODE_SEL_INT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT 0x80000000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_BITN 31 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M 0x80000000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S 31 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT 0x80000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_BITN 31 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M 0x80000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S 31 // Field: [30:29] STANDBY_PW_SEL_INT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_W 2 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M 0x60000000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S 29 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M 0x60000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S 29 // Field: [28] DIS_STANDBY_INT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT 0x10000000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_BITN 28 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M 0x10000000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_S 28 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT 0x10000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_BITN 28 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M 0x10000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_S 28 // Field: [27] DIS_IDLE_INT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT 0x08000000 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_BITN 27 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M 0x08000000 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S 27 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT 0x08000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_BITN 27 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M 0x08000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S 27 // Field: [26:24] VIN_AT_X_INT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_W 3 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M 0x07000000 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S 24 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M 0x07000000 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S 24 // Field: [23] STANDBY_MODE_SEL_EXT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT 0x00800000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_BITN 23 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M 0x00800000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S 23 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT 0x00800000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_BITN 23 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M 0x00800000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S 23 // Field: [22:21] STANDBY_PW_SEL_EXT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_W 2 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M 0x00600000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S 21 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M 0x00600000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S 21 // Field: [20] DIS_STANDBY_EXT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT 0x00100000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_BITN 20 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M 0x00100000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_S 20 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT 0x00100000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_BITN 20 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M 0x00100000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_S 20 // Field: [19] DIS_IDLE_EXT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT 0x00080000 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_BITN 19 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M 0x00080000 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S 19 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT 0x00080000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_BITN 19 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M 0x00080000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S 19 // Field: [18:16] VIN_AT_X_EXT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_W 3 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M 0x00070000 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S 16 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M 0x00070000 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S 16 // Field: [15] STANDBY_MODE_SEL_INT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD 0x00008000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_BITN 15 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M 0x00008000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S 15 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD 0x00008000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_BITN 15 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M 0x00008000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S 15 // Field: [14:13] STANDBY_PW_SEL_INT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_W 2 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M 0x00006000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S 13 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M 0x00006000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S 13 // Field: [12] DIS_STANDBY_INT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD 0x00001000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_BITN 12 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M 0x00001000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_S 12 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD 0x00001000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_BITN 12 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M 0x00001000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_S 12 // Field: [11] DIS_IDLE_INT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD 0x00000800 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_BITN 11 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M 0x00000800 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S 11 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD 0x00000800 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_BITN 11 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M 0x00000800 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S 11 // Field: [10:8] VIN_AT_X_INT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_W 3 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M 0x00000700 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S 8 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M 0x00000700 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S 8 // Field: [7] STANDBY_MODE_SEL_EXT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD 0x00000080 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_BITN 7 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M 0x00000080 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S 7 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD 0x00000080 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_BITN 7 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M 0x00000080 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S 7 // Field: [6:5] STANDBY_PW_SEL_EXT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_W 2 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M 0x00000060 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S 5 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M 0x00000060 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S 5 // Field: [4] DIS_STANDBY_EXT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD 0x00000010 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_BITN 4 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M 0x00000010 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_S 4 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD 0x00000010 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_BITN 4 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M 0x00000010 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_S 4 // Field: [3] DIS_IDLE_EXT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD 0x00000008 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_BITN 3 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M 0x00000008 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S 3 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD 0x00000008 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_BITN 3 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M 0x00000008 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S 3 // Field: [2:0] VIN_AT_X_EXT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_W 3 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M 0x00000007 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S 0 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M 0x00000007 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S 0 //***************************************************************************** // @@ -1932,9 +1932,9 @@ // // Signed byte value representing the TEMP slope with battery voltage, in // degrees C / V, with four fractional bits. -#define FCFG1_MISC_TRIM_TEMPVSLOPE_W 8 -#define FCFG1_MISC_TRIM_TEMPVSLOPE_M 0x000000FF -#define FCFG1_MISC_TRIM_TEMPVSLOPE_S 0 +#define FCFG1_MISC_TRIM_TEMPVSLOPE_W 8 +#define FCFG1_MISC_TRIM_TEMPVSLOPE_M 0x000000FF +#define FCFG1_MISC_TRIM_TEMPVSLOPE_S 0 //***************************************************************************** // @@ -1944,30 +1944,30 @@ // Field: [31:24] FINE_RESISTOR // // Internal. Only to be used through TI provided API. -#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_W 8 -#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_M 0xFF000000 -#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_S 24 +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_M 0xFF000000 +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_S 24 // Field: [23:16] CTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_W 8 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_M 0x00FF0000 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_S 16 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_M 0x00FF0000 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_S 16 // Field: [15:8] CTRIMFRACT_QUAD // // Internal. Only to be used through TI provided API. -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_W 8 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_M 0x0000FF00 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_S 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_M 0x0000FF00 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_S 8 // Field: [7:0] CTRIMFRACT_SLOPE // // Internal. Only to be used through TI provided API. -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_W 8 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_M 0x000000FF -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_S 0 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_M 0x000000FF +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_S 0 //***************************************************************************** // @@ -1977,16 +1977,16 @@ // Field: [31:16] FT1 // // Internal. Only to be used through TI provided API. -#define FCFG1_TRIM_CAL_REVISION_FT1_W 16 -#define FCFG1_TRIM_CAL_REVISION_FT1_M 0xFFFF0000 -#define FCFG1_TRIM_CAL_REVISION_FT1_S 16 +#define FCFG1_TRIM_CAL_REVISION_FT1_W 16 +#define FCFG1_TRIM_CAL_REVISION_FT1_M 0xFFFF0000 +#define FCFG1_TRIM_CAL_REVISION_FT1_S 16 // Field: [15:0] MP1 // // Internal. Only to be used through TI provided API. -#define FCFG1_TRIM_CAL_REVISION_MP1_W 16 -#define FCFG1_TRIM_CAL_REVISION_MP1_M 0x0000FFFF -#define FCFG1_TRIM_CAL_REVISION_MP1_S 0 +#define FCFG1_TRIM_CAL_REVISION_MP1_W 16 +#define FCFG1_TRIM_CAL_REVISION_MP1_M 0x0000FFFF +#define FCFG1_TRIM_CAL_REVISION_MP1_S 0 //***************************************************************************** // @@ -1996,25 +1996,25 @@ // Field: [31:28] PG_REV // // Field used to distinguish revisions of the device. -#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_W 4 -#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_M 0xF0000000 -#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_S 28 +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_W 4 +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_M 0xF0000000 +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_S 28 // Field: [27:12] WAFER_ID // // Field used to identify silicon die. -#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_W 16 -#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M 0x0FFFF000 -#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S 12 +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_W 16 +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M 0x0FFFF000 +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S 12 // Field: [11:0] MANUFACTURER_ID // // Manufacturer code. // // 0x02F: Texas Instruments -#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_W 12 -#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_M 0x00000FFF -#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_S 0 +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_W 12 +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_M 0x00000FFF +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_S 0 //***************************************************************************** // @@ -2029,9 +2029,9 @@ // to be produced if the FCFG1 layout has changed since the previous production // of devices. // Value migth change without warning. -#define FCFG1_FCFG1_REVISION_REV_W 32 -#define FCFG1_FCFG1_REVISION_REV_M 0xFFFFFFFF -#define FCFG1_FCFG1_REVISION_REV_S 0 +#define FCFG1_FCFG1_REVISION_REV_W 32 +#define FCFG1_FCFG1_REVISION_REV_M 0xFFFFFFFF +#define FCFG1_FCFG1_REVISION_REV_S 0 //***************************************************************************** // @@ -2041,46 +2041,46 @@ // Field: [31:28] RCOSC_HF_ITUNE // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_W 4 -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_M 0xF0000000 -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_S 28 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_W 4 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_M 0xF0000000 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_S 28 // Field: [27:20] RCOSC_HF_CRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_W 8 -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_M 0x0FF00000 -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_S 20 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_W 8 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_M 0x0FF00000 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_S 20 // Field: [19:15] PER_M // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_PER_M_W 5 -#define FCFG1_MISC_OTP_DATA_PER_M_M 0x000F8000 -#define FCFG1_MISC_OTP_DATA_PER_M_S 15 +#define FCFG1_MISC_OTP_DATA_PER_M_W 5 +#define FCFG1_MISC_OTP_DATA_PER_M_M 0x000F8000 +#define FCFG1_MISC_OTP_DATA_PER_M_S 15 // Field: [14:12] PER_E // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_PER_E_W 3 -#define FCFG1_MISC_OTP_DATA_PER_E_M 0x00007000 -#define FCFG1_MISC_OTP_DATA_PER_E_S 12 +#define FCFG1_MISC_OTP_DATA_PER_E_W 3 +#define FCFG1_MISC_OTP_DATA_PER_E_M 0x00007000 +#define FCFG1_MISC_OTP_DATA_PER_E_S 12 // Field: [11:8] MIN_ALLOWED_RTRIM_DIV5 // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_MIN_ALLOWED_RTRIM_DIV5_W 4 -#define FCFG1_MISC_OTP_DATA_MIN_ALLOWED_RTRIM_DIV5_M 0x00000F00 -#define FCFG1_MISC_OTP_DATA_MIN_ALLOWED_RTRIM_DIV5_S 8 +#define FCFG1_MISC_OTP_DATA_MIN_ALLOWED_RTRIM_DIV5_W 4 +#define FCFG1_MISC_OTP_DATA_MIN_ALLOWED_RTRIM_DIV5_M 0x00000F00 +#define FCFG1_MISC_OTP_DATA_MIN_ALLOWED_RTRIM_DIV5_S 8 // Field: [7:0] TEST_PROGRAM_REV // // The revision of the test program used in the production process when FCFG1 // was programmed. // Value migth change without warning. -#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_W 8 -#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_M 0x000000FF -#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_S 0 +#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_W 8 +#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_M 0x000000FF +#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_S 0 //***************************************************************************** // @@ -2090,9 +2090,9 @@ // Field: [6:0] GPIO_CNT // // Number of available DIOs. -#define FCFG1_IOCONF_GPIO_CNT_W 7 -#define FCFG1_IOCONF_GPIO_CNT_M 0x0000007F -#define FCFG1_IOCONF_GPIO_CNT_S 0 +#define FCFG1_IOCONF_GPIO_CNT_W 7 +#define FCFG1_IOCONF_GPIO_CNT_M 0x0000007F +#define FCFG1_IOCONF_GPIO_CNT_S 0 //***************************************************************************** // @@ -2102,58 +2102,58 @@ // Field: [31:28] FF2ADJ // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_FF2ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_FF2ADJ_M 0xF0000000 -#define FCFG1_CONFIG_IF_ADC_FF2ADJ_S 28 +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_M 0xF0000000 +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_S 28 // Field: [27:24] FF3ADJ // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_FF3ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_FF3ADJ_M 0x0F000000 -#define FCFG1_CONFIG_IF_ADC_FF3ADJ_S 24 +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_M 0x0F000000 +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_S 24 // Field: [23:20] INT3ADJ // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_INT3ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_INT3ADJ_M 0x00F00000 -#define FCFG1_CONFIG_IF_ADC_INT3ADJ_S 20 +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_M 0x00F00000 +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_S 20 // Field: [19:16] FF1ADJ // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_FF1ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_FF1ADJ_M 0x000F0000 -#define FCFG1_CONFIG_IF_ADC_FF1ADJ_S 16 +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_M 0x000F0000 +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_S 16 // Field: [15:14] AAFCAP // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_AAFCAP_W 2 -#define FCFG1_CONFIG_IF_ADC_AAFCAP_M 0x0000C000 -#define FCFG1_CONFIG_IF_ADC_AAFCAP_S 14 +#define FCFG1_CONFIG_IF_ADC_AAFCAP_W 2 +#define FCFG1_CONFIG_IF_ADC_AAFCAP_M 0x0000C000 +#define FCFG1_CONFIG_IF_ADC_AAFCAP_S 14 // Field: [13:10] INT2ADJ // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_INT2ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_INT2ADJ_M 0x00003C00 -#define FCFG1_CONFIG_IF_ADC_INT2ADJ_S 10 +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_M 0x00003C00 +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_S 10 // Field: [9:5] IFDIGLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_W 5 -#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_M 0x000003E0 -#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_S 5 +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_W 5 +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_M 0x000003E0 +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_S 5 // Field: [4:0] IFANALDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_W 5 -#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_M 0x0000001F -#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_W 5 +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_M 0x0000001F +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -2163,30 +2163,30 @@ // Field: [29:26] XOSC_HF_ROW_Q12 // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_W 4 -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M 0x3C000000 -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S 26 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_W 4 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M 0x3C000000 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S 26 // Field: [25:10] XOSC_HF_COLUMN_Q12 // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_W 16 -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M 0x03FFFC00 -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S 10 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_W 16 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M 0x03FFFC00 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S 10 // Field: [9:2] RCOSCLF_CTUNE_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_W 8 -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M 0x000003FC -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S 2 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_W 8 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M 0x000003FC +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S 2 // Field: [1:0] RCOSCLF_RTUNE_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_W 2 -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M 0x00000003 -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S 0 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_W 2 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M 0x00000003 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S 0 //***************************************************************************** // @@ -2196,45 +2196,45 @@ // Field: [31:28] IFAMP_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_S 28 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_S 28 // Field: [27:24] LNA_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_S 24 +#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_S 24 // Field: [23:19] IFAMP_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_S 19 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_S 19 // Field: [18:14] CTL_PA0_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_S 14 +#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_S 14 // Field: [13] PATRIMCOMPLETE_N // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N 0x00002000 -#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_BITN 13 -#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_M 0x00002000 -#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_S 13 +#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N 0x00002000 +#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_BITN 13 +#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_M 0x00002000 +#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_S 13 // Field: [6:0] RFLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_M 0x0000007F -#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -2244,33 +2244,33 @@ // Field: [28] DISABLE_CORNER_CAP // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DISABLE_CORNER_CAP 0x10000000 -#define FCFG1_CONFIG_SYNTH_DISABLE_CORNER_CAP_BITN 28 -#define FCFG1_CONFIG_SYNTH_DISABLE_CORNER_CAP_M 0x10000000 -#define FCFG1_CONFIG_SYNTH_DISABLE_CORNER_CAP_S 28 +#define FCFG1_CONFIG_SYNTH_DISABLE_CORNER_CAP 0x10000000 +#define FCFG1_CONFIG_SYNTH_DISABLE_CORNER_CAP_BITN 28 +#define FCFG1_CONFIG_SYNTH_DISABLE_CORNER_CAP_M 0x10000000 +#define FCFG1_CONFIG_SYNTH_DISABLE_CORNER_CAP_S 28 // Field: [27:12] RFC_MDM_DEMIQMC0 // // Trim value for RF Core. // Value is read by RF Core ROM FW during RF Core initialization only on // cc13x0. -#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5:0] SLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_M 0x0000003F -#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -2281,9 +2281,9 @@ // // SOC_ADC gain in absolute reference mode at temperature 1 (30C). Calculated // in production test.. -#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_W 16 -#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M 0x0000FFFF -#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S 0 +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_W 16 +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M 0x0000FFFF +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S 0 //***************************************************************************** // @@ -2294,9 +2294,9 @@ // // SOC_ADC gain in relative reference mode at temperature 1 (30C). Calculated // in production test.. -#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_W 16 -#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M 0x0000FFFF -#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S 0 +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_W 16 +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M 0x0000FFFF +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S 0 //***************************************************************************** // @@ -2307,17 +2307,17 @@ // // SOC_ADC offset in relative reference mode at temperature 1 (30C). Signed // 8-bit number. Calculated in production test.. -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_W 8 -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_M 0x00FF0000 -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S 16 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_W 8 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_M 0x00FF0000 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S 16 // Field: [7:0] SOC_ADC_ABS_OFFSET_TEMP1 // // SOC_ADC offset in absolute reference mode at temperature 1 (30C). Signed // 8-bit number. Calculated in production test.. -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_W 8 -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_M 0x000000FF -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S 0 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_W 8 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_M 0x000000FF +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S 0 //***************************************************************************** // @@ -2342,30 +2342,30 @@ // Field: [23:18] HPMRAMP3_LTH // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_W 6 -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M 0x00FC0000 -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S 18 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M 0x00FC0000 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S 18 // Field: [15:10] HPMRAMP3_HTH // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_W 6 -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M 0x0000FC00 -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S 10 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M 0x0000FC00 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S 10 // Field: [9:6] IBIASCAP_LPTOHP_OL_CNT // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_W 4 -#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 -#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S 6 +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_W 4 +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S 6 // Field: [5:0] HPMRAMP1_TH // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_W 6 -#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M 0x0000003F -#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S 0 +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M 0x0000003F +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S 0 //***************************************************************************** // @@ -2375,30 +2375,30 @@ // Field: [31:26] LPMUPDATE_LTH // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_W 6 -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M 0xFC000000 -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S 26 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_W 6 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M 0xFC000000 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S 26 // Field: [23:18] LPMUPDATE_HTM // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_W 6 -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M 0x00FC0000 -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S 18 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_W 6 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M 0x00FC0000 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S 18 // Field: [15:10] ADC_COMP_AMPTH_LPM // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_W 6 -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S 10 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_W 6 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S 10 // Field: [7:2] ADC_COMP_AMPTH_HPM // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_W 6 -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M 0x000000FC -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S 2 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_W 6 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M 0x000000FC +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S 2 //***************************************************************************** // @@ -2408,45 +2408,45 @@ // Field: [30] AMPCOMP_REQ_MODE // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE 0x40000000 -#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_BITN 30 -#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M 0x40000000 -#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S 30 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE 0x40000000 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_BITN 30 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M 0x40000000 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S 30 // Field: [23:20] IBIAS_OFFSET // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_W 4 -#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M 0x00F00000 -#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S 20 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M 0x00F00000 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S 20 // Field: [19:16] IBIAS_INIT // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_W 4 -#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M 0x000F0000 -#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S 16 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M 0x000F0000 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S 16 // Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_W 8 -#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 -#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S 8 +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_W 8 +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S 8 // Field: [7:4] CAP_STEP // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_W 4 -#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_M 0x000000F0 -#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_S 4 +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_W 4 +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_M 0x000000F0 +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_S 4 // Field: [3:0] IBIASCAP_HPTOLP_OL_CNT // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_W 4 -#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F -#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S 0 +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S 0 //***************************************************************************** // @@ -2456,9 +2456,9 @@ // Field: [13:0] XOSC_HF_IBIASTHERM // // Internal. Only to be used through TI provided API. -#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_W 14 -#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M 0x00003FFF -#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S 0 +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_W 14 +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M 0x00003FFF +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S 0 //***************************************************************************** // @@ -2468,38 +2468,38 @@ // Field: [21:18] MIN_ALLOWED_RTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_M 0x003C0000 -#define FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_S 18 +#define FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_M 0x003C0000 +#define FCFG1_CONFIG_MISC_ADC_MIN_ALLOWED_RTRIM_S 18 // Field: [17] RSSITRIMCOMPLETE_N // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N 0x00020000 -#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_BITN 17 -#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_M 0x00020000 -#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_S 17 +#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N 0x00020000 +#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_BITN 17 +#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_M 0x00020000 +#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_S 17 // Field: [16:9] RSSI_OFFSET // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_M 0x0001FE00 -#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_S 9 +#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_S 9 // Field: [8:6] QUANTCTLTHRES // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_S 6 +#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_S 6 // Field: [5:0] DACTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DACTRIM_W 6 -#define FCFG1_CONFIG_MISC_ADC_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_MISC_ADC_DACTRIM_S 0 +#define FCFG1_CONFIG_MISC_ADC_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DACTRIM_S 0 //***************************************************************************** // @@ -2509,30 +2509,30 @@ // Field: [28:24] VDDR_TRIM_HH // // Internal. Only to be used through TI provided API. -#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_W 5 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M 0x1F000000 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S 24 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M 0x1F000000 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S 24 // Field: [20:16] VDDR_TRIM_H // // Internal. Only to be used through TI provided API. -#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_W 5 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_M 0x001F0000 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_S 16 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_M 0x001F0000 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_S 16 // Field: [12:8] VDDR_TRIM_SLEEP_H // // Internal. Only to be used through TI provided API. -#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_W 5 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_M 0x00001F00 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_S 8 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_M 0x00001F00 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_S 8 // Field: [4:0] TRIMBOD_H // // Internal. Only to be used through TI provided API. -#define FCFG1_VOLT_TRIM_TRIMBOD_H_W 5 -#define FCFG1_VOLT_TRIM_TRIMBOD_H_M 0x0000001F -#define FCFG1_VOLT_TRIM_TRIMBOD_H_S 0 +#define FCFG1_VOLT_TRIM_TRIMBOD_H_W 5 +#define FCFG1_VOLT_TRIM_TRIMBOD_H_M 0x0000001F +#define FCFG1_VOLT_TRIM_TRIMBOD_H_S 0 //***************************************************************************** // @@ -2542,116 +2542,116 @@ // Field: [29] ADC_SH_VBUF_EN // // Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN. -#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN 0x20000000 -#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_BITN 29 -#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M 0x20000000 -#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S 29 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN 0x20000000 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_BITN 29 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M 0x20000000 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S 29 // Field: [28] ADC_SH_MODE_EN // // Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN. -#define FCFG1_OSC_CONF_ADC_SH_MODE_EN 0x10000000 -#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_BITN 28 -#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_M 0x10000000 -#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_S 28 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN 0x10000000 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_BITN 28 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_M 0x10000000 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_S 28 // Field: [27] ATESTLF_RCOSCLF_IBIAS_TRIM // // Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM. -#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM 0x08000000 -#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_BITN 27 -#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M 0x08000000 -#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S 27 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM 0x08000000 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_BITN 27 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M 0x08000000 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S 27 // Field: [26:25] XOSCLF_REGULATOR_TRIM // // Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM. -#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_W 2 -#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M 0x06000000 -#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_S 25 +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_W 2 +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M 0x06000000 +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_S 25 // Field: [24:21] XOSCLF_CMIRRWR_RATIO // // Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO. -#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_W 4 -#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M 0x01E00000 -#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S 21 +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_W 4 +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M 0x01E00000 +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S 21 // Field: [20:19] XOSC_HF_FAST_START // // Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START. -#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_W 2 -#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_M 0x00180000 -#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_S 19 +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_W 2 +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_M 0x00180000 +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_S 19 // Field: [18] XOSC_OPTION // // 0: XOSC_HF unavailable (may not be bonded out) // 1: XOSC_HF available (default) -#define FCFG1_OSC_CONF_XOSC_OPTION 0x00040000 -#define FCFG1_OSC_CONF_XOSC_OPTION_BITN 18 -#define FCFG1_OSC_CONF_XOSC_OPTION_M 0x00040000 -#define FCFG1_OSC_CONF_XOSC_OPTION_S 18 +#define FCFG1_OSC_CONF_XOSC_OPTION 0x00040000 +#define FCFG1_OSC_CONF_XOSC_OPTION_BITN 18 +#define FCFG1_OSC_CONF_XOSC_OPTION_M 0x00040000 +#define FCFG1_OSC_CONF_XOSC_OPTION_S 18 // Field: [17] HPOSC_OPTION // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_OPTION 0x00020000 -#define FCFG1_OSC_CONF_HPOSC_OPTION_BITN 17 -#define FCFG1_OSC_CONF_HPOSC_OPTION_M 0x00020000 -#define FCFG1_OSC_CONF_HPOSC_OPTION_S 17 +#define FCFG1_OSC_CONF_HPOSC_OPTION 0x00020000 +#define FCFG1_OSC_CONF_HPOSC_OPTION_BITN 17 +#define FCFG1_OSC_CONF_HPOSC_OPTION_M 0x00020000 +#define FCFG1_OSC_CONF_HPOSC_OPTION_S 17 // Field: [16] HPOSC_BIAS_HOLD_MODE_EN // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN 0x00010000 -#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_BITN 16 -#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M 0x00010000 -#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S 16 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN 0x00010000 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_BITN 16 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M 0x00010000 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S 16 // Field: [15:12] HPOSC_CURRMIRR_RATIO // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_W 4 -#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M 0x0000F000 -#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S 12 +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_W 4 +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M 0x0000F000 +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S 12 // Field: [11:8] HPOSC_BIAS_RES_SET // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_W 4 -#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M 0x00000F00 -#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S 8 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_W 4 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M 0x00000F00 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S 8 // Field: [7] HPOSC_FILTER_EN // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_FILTER_EN 0x00000080 -#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_BITN 7 -#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_M 0x00000080 -#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_S 7 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN 0x00000080 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_BITN 7 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_M 0x00000080 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_S 7 // Field: [6:5] HPOSC_BIAS_RECHARGE_DELAY // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_W 2 -#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M 0x00000060 -#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S 5 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_W 2 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M 0x00000060 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S 5 // Field: [2:1] HPOSC_SERIES_CAP // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_W 2 -#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M 0x00000006 -#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S 1 +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_W 2 +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M 0x00000006 +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S 1 // Field: [0] HPOSC_DIV3_BYPASS // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS 0x00000001 -#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_BITN 0 -#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M 0x00000001 -#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S 0 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS 0x00000001 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_BITN 0 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M 0x00000001 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S 0 //***************************************************************************** // @@ -2661,23 +2661,23 @@ // Field: [31:16] HPOSC_COMP_P0 // // Internal. Only to be used through TI provided API. -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W 16 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_M 0xFFFF0000 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S 16 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W 16 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_M 0xFFFF0000 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S 16 // Field: [15:8] HPOSC_COMP_P1 // // Internal. Only to be used through TI provided API. -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W 8 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_M 0x0000FF00 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S 8 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W 8 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_M 0x0000FF00 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S 8 // Field: [7:0] HPOSC_COMP_P2 // // Internal. Only to be used through TI provided API. -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W 8 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_M 0x000000FF -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S 0 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W 8 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_M 0x000000FF +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S 0 //***************************************************************************** // @@ -2687,16 +2687,16 @@ // Field: [31:16] FLUX_CAP_0P28_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_W 16 -#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_M 0xFFFF0000 -#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_S 16 +#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_W 16 +#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_M 0xFFFF0000 +#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_S 16 // Field: [15:0] FLUX_CAP_0P4_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_W 16 -#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_M 0x0000FFFF -#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_S 0 +#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_W 16 +#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_M 0x0000FFFF +#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_S 0 //***************************************************************************** // @@ -2706,51 +2706,51 @@ // Field: [28:27] PEAK_DET_ITRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_W 2 -#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M 0x18000000 -#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S 27 +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_W 2 +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M 0x18000000 +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S 27 // Field: [26:24] HP_BUF_ITRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_W 3 -#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M 0x07000000 -#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S 24 +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_W 3 +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M 0x07000000 +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S 24 // Field: [23:22] LP_BUF_ITRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_W 2 -#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M 0x00C00000 -#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S 22 +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_W 2 +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M 0x00C00000 +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S 22 // Field: [21:20] DBLR_LOOP_FILTER_RESET_VOLTAGE // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_W 2 -#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M 0x00300000 -#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S 20 +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_W 2 +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M 0x00300000 +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S 20 // Field: [19:10] HPM_IBIAS_WAIT_CNT // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_W 10 -#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M 0x000FFC00 -#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S 10 +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_W 10 +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M 0x000FFC00 +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S 10 // Field: [9:4] LPM_IBIAS_WAIT_CNT // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_W 6 -#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M 0x000003F0 -#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S 4 +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_W 6 +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M 0x000003F0 +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S 4 // Field: [3:0] IDAC_STEP // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_W 4 -#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M 0x0000000F -#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S 0 +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_W 4 +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M 0x0000000F +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S 0 //***************************************************************************** // @@ -2760,31 +2760,31 @@ // Field: [31:24] DELTA_CACHE_REF // // Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_S 24 +#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_S 24 // Field: [23:16] DELTA_RFMEM_RET // // Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_S 16 +#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_S 16 // Field: [15:8] DELTA_XOSC_LPM // // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power // mode -#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_S 8 +#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_S 8 // Field: [7:0] BASELINE // // Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_20C_BASELINE_W 8 -#define FCFG1_PWD_CURR_20C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_20C_BASELINE_S 0 +#define FCFG1_PWD_CURR_20C_BASELINE_W 8 +#define FCFG1_PWD_CURR_20C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_20C_BASELINE_S 0 //***************************************************************************** // @@ -2794,31 +2794,31 @@ // Field: [31:24] DELTA_CACHE_REF // // Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_S 24 +#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_S 24 // Field: [23:16] DELTA_RFMEM_RET // // Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_S 16 +#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_S 16 // Field: [15:8] DELTA_XOSC_LPM // // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power // mode -#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_S 8 +#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_S 8 // Field: [7:0] BASELINE // // Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_35C_BASELINE_W 8 -#define FCFG1_PWD_CURR_35C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_35C_BASELINE_S 0 +#define FCFG1_PWD_CURR_35C_BASELINE_W 8 +#define FCFG1_PWD_CURR_35C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_35C_BASELINE_S 0 //***************************************************************************** // @@ -2828,31 +2828,31 @@ // Field: [31:24] DELTA_CACHE_REF // // Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_S 24 +#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_S 24 // Field: [23:16] DELTA_RFMEM_RET // // Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_S 16 +#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_S 16 // Field: [15:8] DELTA_XOSC_LPM // // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power // mode -#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_S 8 +#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_S 8 // Field: [7:0] BASELINE // // Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_50C_BASELINE_W 8 -#define FCFG1_PWD_CURR_50C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_50C_BASELINE_S 0 +#define FCFG1_PWD_CURR_50C_BASELINE_W 8 +#define FCFG1_PWD_CURR_50C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_50C_BASELINE_S 0 //***************************************************************************** // @@ -2862,31 +2862,31 @@ // Field: [31:24] DELTA_CACHE_REF // // Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_S 24 +#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_S 24 // Field: [23:16] DELTA_RFMEM_RET // // Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_S 16 +#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_S 16 // Field: [15:8] DELTA_XOSC_LPM // // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power // mode -#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_S 8 +#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_S 8 // Field: [7:0] BASELINE // // Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_65C_BASELINE_W 8 -#define FCFG1_PWD_CURR_65C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_65C_BASELINE_S 0 +#define FCFG1_PWD_CURR_65C_BASELINE_W 8 +#define FCFG1_PWD_CURR_65C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_65C_BASELINE_S 0 //***************************************************************************** // @@ -2896,31 +2896,31 @@ // Field: [31:24] DELTA_CACHE_REF // // Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_S 24 +#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_S 24 // Field: [23:16] DELTA_RFMEM_RET // // Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_S 16 +#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_S 16 // Field: [15:8] DELTA_XOSC_LPM // // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power // mode -#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_S 8 +#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_S 8 // Field: [7:0] BASELINE // // Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_80C_BASELINE_W 8 -#define FCFG1_PWD_CURR_80C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_80C_BASELINE_S 0 +#define FCFG1_PWD_CURR_80C_BASELINE_W 8 +#define FCFG1_PWD_CURR_80C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_80C_BASELINE_S 0 //***************************************************************************** // @@ -2930,31 +2930,31 @@ // Field: [31:24] DELTA_CACHE_REF // // Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_S 24 +#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_S 24 // Field: [23:16] DELTA_RFMEM_RET // // Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_S 16 +#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_S 16 // Field: [15:8] DELTA_XOSC_LPM // // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power // mode -#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_S 8 +#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_S 8 // Field: [7:0] BASELINE // // Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_95C_BASELINE_W 8 -#define FCFG1_PWD_CURR_95C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_95C_BASELINE_S 0 +#define FCFG1_PWD_CURR_95C_BASELINE_W 8 +#define FCFG1_PWD_CURR_95C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_95C_BASELINE_S 0 //***************************************************************************** // @@ -2964,31 +2964,31 @@ // Field: [31:24] DELTA_CACHE_REF // // Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_S 24 +#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_S 24 // Field: [23:16] DELTA_RFMEM_RET // // Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_S 16 +#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_S 16 // Field: [15:8] DELTA_XOSC_LPM // // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power // mode -#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_S 8 +#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_S 8 // Field: [7:0] BASELINE // // Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_110C_BASELINE_W 8 -#define FCFG1_PWD_CURR_110C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_110C_BASELINE_S 0 +#define FCFG1_PWD_CURR_110C_BASELINE_W 8 +#define FCFG1_PWD_CURR_110C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_110C_BASELINE_S 0 //***************************************************************************** // @@ -2998,31 +2998,30 @@ // Field: [31:24] DELTA_CACHE_REF // // Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_S 24 +#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_S 24 // Field: [23:16] DELTA_RFMEM_RET // // Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_S 16 +#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_S 16 // Field: [15:8] DELTA_XOSC_LPM // // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power // mode -#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_S 8 +#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_S 8 // Field: [7:0] BASELINE // // Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_125C_BASELINE_W 8 -#define FCFG1_PWD_CURR_125C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_125C_BASELINE_S 0 - +#define FCFG1_PWD_CURR_125C_BASELINE_W 8 +#define FCFG1_PWD_CURR_125C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_125C_BASELINE_S 0 #endif // __FCFG1__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_flash.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_flash.h index 03ce768..dbaa180 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_flash.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_flash.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_flash_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_flash_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_FLASH_H__ #define __HW_FLASH_H__ @@ -44,373 +44,373 @@ // //***************************************************************************** // FMC and Efuse Status -#define FLASH_O_STAT 0x0000001C +#define FLASH_O_STAT 0x0000001C // Internal -#define FLASH_O_CFG 0x00000024 +#define FLASH_O_CFG 0x00000024 // Internal -#define FLASH_O_SYSCODE_START 0x00000028 +#define FLASH_O_SYSCODE_START 0x00000028 // Internal -#define FLASH_O_FLASH_SIZE 0x0000002C +#define FLASH_O_FLASH_SIZE 0x0000002C // Internal -#define FLASH_O_FWLOCK 0x0000003C +#define FLASH_O_FWLOCK 0x0000003C // Internal -#define FLASH_O_FWFLAG 0x00000040 +#define FLASH_O_FWFLAG 0x00000040 // Internal -#define FLASH_O_EFUSE 0x00001000 +#define FLASH_O_EFUSE 0x00001000 // Internal -#define FLASH_O_EFUSEADDR 0x00001004 +#define FLASH_O_EFUSEADDR 0x00001004 // Internal -#define FLASH_O_DATAUPPER 0x00001008 +#define FLASH_O_DATAUPPER 0x00001008 // Internal -#define FLASH_O_DATALOWER 0x0000100C +#define FLASH_O_DATALOWER 0x0000100C // Internal -#define FLASH_O_EFUSECFG 0x00001010 +#define FLASH_O_EFUSECFG 0x00001010 // Internal -#define FLASH_O_EFUSESTAT 0x00001014 +#define FLASH_O_EFUSESTAT 0x00001014 // Internal -#define FLASH_O_ACC 0x00001018 +#define FLASH_O_ACC 0x00001018 // Internal -#define FLASH_O_BOUNDARY 0x0000101C +#define FLASH_O_BOUNDARY 0x0000101C // Internal -#define FLASH_O_EFUSEFLAG 0x00001020 +#define FLASH_O_EFUSEFLAG 0x00001020 // Internal -#define FLASH_O_EFUSEKEY 0x00001024 +#define FLASH_O_EFUSEKEY 0x00001024 // Internal -#define FLASH_O_EFUSERELEASE 0x00001028 +#define FLASH_O_EFUSERELEASE 0x00001028 // Internal -#define FLASH_O_EFUSEPINS 0x0000102C +#define FLASH_O_EFUSEPINS 0x0000102C // Internal -#define FLASH_O_EFUSECRA 0x00001030 +#define FLASH_O_EFUSECRA 0x00001030 // Internal -#define FLASH_O_EFUSEREAD 0x00001034 +#define FLASH_O_EFUSEREAD 0x00001034 // Internal -#define FLASH_O_EFUSEPROGRAM 0x00001038 +#define FLASH_O_EFUSEPROGRAM 0x00001038 // Internal -#define FLASH_O_EFUSEERROR 0x0000103C +#define FLASH_O_EFUSEERROR 0x0000103C // Internal -#define FLASH_O_SINGLEBIT 0x00001040 +#define FLASH_O_SINGLEBIT 0x00001040 // Internal -#define FLASH_O_TWOBIT 0x00001044 +#define FLASH_O_TWOBIT 0x00001044 // Internal -#define FLASH_O_SELFTESTCYC 0x00001048 +#define FLASH_O_SELFTESTCYC 0x00001048 // Internal -#define FLASH_O_SELFTESTSIGN 0x0000104C +#define FLASH_O_SELFTESTSIGN 0x0000104C // Internal -#define FLASH_O_FRDCTL 0x00002000 +#define FLASH_O_FRDCTL 0x00002000 // Internal -#define FLASH_O_FSPRD 0x00002004 +#define FLASH_O_FSPRD 0x00002004 // Internal -#define FLASH_O_FEDACCTL1 0x00002008 +#define FLASH_O_FEDACCTL1 0x00002008 // Internal -#define FLASH_O_FEDACSTAT 0x0000201C +#define FLASH_O_FEDACSTAT 0x0000201C // Internal -#define FLASH_O_FBPROT 0x00002030 +#define FLASH_O_FBPROT 0x00002030 // Internal -#define FLASH_O_FBSE 0x00002034 +#define FLASH_O_FBSE 0x00002034 // Internal -#define FLASH_O_FBBUSY 0x00002038 +#define FLASH_O_FBBUSY 0x00002038 // Internal -#define FLASH_O_FBAC 0x0000203C +#define FLASH_O_FBAC 0x0000203C // Internal -#define FLASH_O_FBFALLBACK 0x00002040 +#define FLASH_O_FBFALLBACK 0x00002040 // Internal -#define FLASH_O_FBPRDY 0x00002044 +#define FLASH_O_FBPRDY 0x00002044 // Internal -#define FLASH_O_FPAC1 0x00002048 +#define FLASH_O_FPAC1 0x00002048 // Internal -#define FLASH_O_FPAC2 0x0000204C +#define FLASH_O_FPAC2 0x0000204C // Internal -#define FLASH_O_FMAC 0x00002050 +#define FLASH_O_FMAC 0x00002050 // Internal -#define FLASH_O_FMSTAT 0x00002054 +#define FLASH_O_FMSTAT 0x00002054 // Internal -#define FLASH_O_FLOCK 0x00002064 +#define FLASH_O_FLOCK 0x00002064 // Internal -#define FLASH_O_FVREADCT 0x00002080 +#define FLASH_O_FVREADCT 0x00002080 // Internal -#define FLASH_O_FVHVCT1 0x00002084 +#define FLASH_O_FVHVCT1 0x00002084 // Internal -#define FLASH_O_FVHVCT2 0x00002088 +#define FLASH_O_FVHVCT2 0x00002088 // Internal -#define FLASH_O_FVHVCT3 0x0000208C +#define FLASH_O_FVHVCT3 0x0000208C // Internal -#define FLASH_O_FVNVCT 0x00002090 +#define FLASH_O_FVNVCT 0x00002090 // Internal -#define FLASH_O_FVSLP 0x00002094 +#define FLASH_O_FVSLP 0x00002094 // Internal -#define FLASH_O_FVWLCT 0x00002098 +#define FLASH_O_FVWLCT 0x00002098 // Internal -#define FLASH_O_FEFUSECTL 0x0000209C +#define FLASH_O_FEFUSECTL 0x0000209C // Internal -#define FLASH_O_FEFUSESTAT 0x000020A0 +#define FLASH_O_FEFUSESTAT 0x000020A0 // Internal -#define FLASH_O_FEFUSEDATA 0x000020A4 +#define FLASH_O_FEFUSEDATA 0x000020A4 // Internal -#define FLASH_O_FSEQPMP 0x000020A8 +#define FLASH_O_FSEQPMP 0x000020A8 // Internal -#define FLASH_O_FBSTROBES 0x00002100 +#define FLASH_O_FBSTROBES 0x00002100 // Internal -#define FLASH_O_FPSTROBES 0x00002104 +#define FLASH_O_FPSTROBES 0x00002104 // Internal -#define FLASH_O_FBMODE 0x00002108 +#define FLASH_O_FBMODE 0x00002108 // Internal -#define FLASH_O_FTCR 0x0000210C +#define FLASH_O_FTCR 0x0000210C // Internal -#define FLASH_O_FADDR 0x00002110 +#define FLASH_O_FADDR 0x00002110 // Internal -#define FLASH_O_FTCTL 0x0000211C +#define FLASH_O_FTCTL 0x0000211C // Internal -#define FLASH_O_FWPWRITE0 0x00002120 +#define FLASH_O_FWPWRITE0 0x00002120 // Internal -#define FLASH_O_FWPWRITE1 0x00002124 +#define FLASH_O_FWPWRITE1 0x00002124 // Internal -#define FLASH_O_FWPWRITE2 0x00002128 +#define FLASH_O_FWPWRITE2 0x00002128 // Internal -#define FLASH_O_FWPWRITE3 0x0000212C +#define FLASH_O_FWPWRITE3 0x0000212C // Internal -#define FLASH_O_FWPWRITE4 0x00002130 +#define FLASH_O_FWPWRITE4 0x00002130 // Internal -#define FLASH_O_FWPWRITE5 0x00002134 +#define FLASH_O_FWPWRITE5 0x00002134 // Internal -#define FLASH_O_FWPWRITE6 0x00002138 +#define FLASH_O_FWPWRITE6 0x00002138 // Internal -#define FLASH_O_FWPWRITE7 0x0000213C +#define FLASH_O_FWPWRITE7 0x0000213C // Internal -#define FLASH_O_FWPWRITE_ECC 0x00002140 +#define FLASH_O_FWPWRITE_ECC 0x00002140 // Internal -#define FLASH_O_FSWSTAT 0x00002144 +#define FLASH_O_FSWSTAT 0x00002144 // Internal -#define FLASH_O_FSM_GLBCTL 0x00002200 +#define FLASH_O_FSM_GLBCTL 0x00002200 // Internal -#define FLASH_O_FSM_STATE 0x00002204 +#define FLASH_O_FSM_STATE 0x00002204 // Internal -#define FLASH_O_FSM_STAT 0x00002208 +#define FLASH_O_FSM_STAT 0x00002208 // Internal -#define FLASH_O_FSM_CMD 0x0000220C +#define FLASH_O_FSM_CMD 0x0000220C // Internal -#define FLASH_O_FSM_PE_OSU 0x00002210 +#define FLASH_O_FSM_PE_OSU 0x00002210 // Internal -#define FLASH_O_FSM_VSTAT 0x00002214 +#define FLASH_O_FSM_VSTAT 0x00002214 // Internal -#define FLASH_O_FSM_PE_VSU 0x00002218 +#define FLASH_O_FSM_PE_VSU 0x00002218 // Internal -#define FLASH_O_FSM_CMP_VSU 0x0000221C +#define FLASH_O_FSM_CMP_VSU 0x0000221C // Internal -#define FLASH_O_FSM_EX_VAL 0x00002220 +#define FLASH_O_FSM_EX_VAL 0x00002220 // Internal -#define FLASH_O_FSM_RD_H 0x00002224 +#define FLASH_O_FSM_RD_H 0x00002224 // Internal -#define FLASH_O_FSM_P_OH 0x00002228 +#define FLASH_O_FSM_P_OH 0x00002228 // Internal -#define FLASH_O_FSM_ERA_OH 0x0000222C +#define FLASH_O_FSM_ERA_OH 0x0000222C // Internal -#define FLASH_O_FSM_SAV_PPUL 0x00002230 +#define FLASH_O_FSM_SAV_PPUL 0x00002230 // Internal -#define FLASH_O_FSM_PE_VH 0x00002234 +#define FLASH_O_FSM_PE_VH 0x00002234 // Internal -#define FLASH_O_FSM_PRG_PW 0x00002240 +#define FLASH_O_FSM_PRG_PW 0x00002240 // Internal -#define FLASH_O_FSM_ERA_PW 0x00002244 +#define FLASH_O_FSM_ERA_PW 0x00002244 // Internal -#define FLASH_O_FSM_SAV_ERA_PUL 0x00002254 +#define FLASH_O_FSM_SAV_ERA_PUL 0x00002254 // Internal -#define FLASH_O_FSM_TIMER 0x00002258 +#define FLASH_O_FSM_TIMER 0x00002258 // Internal -#define FLASH_O_FSM_MODE 0x0000225C +#define FLASH_O_FSM_MODE 0x0000225C // Internal -#define FLASH_O_FSM_PGM 0x00002260 +#define FLASH_O_FSM_PGM 0x00002260 // Internal -#define FLASH_O_FSM_ERA 0x00002264 +#define FLASH_O_FSM_ERA 0x00002264 // Internal -#define FLASH_O_FSM_PRG_PUL 0x00002268 +#define FLASH_O_FSM_PRG_PUL 0x00002268 // Internal -#define FLASH_O_FSM_ERA_PUL 0x0000226C +#define FLASH_O_FSM_ERA_PUL 0x0000226C // Internal -#define FLASH_O_FSM_STEP_SIZE 0x00002270 +#define FLASH_O_FSM_STEP_SIZE 0x00002270 // Internal -#define FLASH_O_FSM_PUL_CNTR 0x00002274 +#define FLASH_O_FSM_PUL_CNTR 0x00002274 // Internal -#define FLASH_O_FSM_EC_STEP_HEIGHT 0x00002278 +#define FLASH_O_FSM_EC_STEP_HEIGHT 0x00002278 // Internal -#define FLASH_O_FSM_ST_MACHINE 0x0000227C +#define FLASH_O_FSM_ST_MACHINE 0x0000227C // Internal -#define FLASH_O_FSM_FLES 0x00002280 +#define FLASH_O_FSM_FLES 0x00002280 // Internal -#define FLASH_O_FSM_WR_ENA 0x00002288 +#define FLASH_O_FSM_WR_ENA 0x00002288 // Internal -#define FLASH_O_FSM_ACC_PP 0x0000228C +#define FLASH_O_FSM_ACC_PP 0x0000228C // Internal -#define FLASH_O_FSM_ACC_EP 0x00002290 +#define FLASH_O_FSM_ACC_EP 0x00002290 // Internal -#define FLASH_O_FSM_ADDR 0x000022A0 +#define FLASH_O_FSM_ADDR 0x000022A0 // Internal -#define FLASH_O_FSM_SECTOR 0x000022A4 +#define FLASH_O_FSM_SECTOR 0x000022A4 // Internal -#define FLASH_O_FMC_REV_ID 0x000022A8 +#define FLASH_O_FMC_REV_ID 0x000022A8 // Internal -#define FLASH_O_FSM_ERR_ADDR 0x000022AC +#define FLASH_O_FSM_ERR_ADDR 0x000022AC // Internal -#define FLASH_O_FSM_PGM_MAXPUL 0x000022B0 +#define FLASH_O_FSM_PGM_MAXPUL 0x000022B0 // Internal -#define FLASH_O_FSM_EXECUTE 0x000022B4 +#define FLASH_O_FSM_EXECUTE 0x000022B4 // Internal -#define FLASH_O_FSM_SECTOR1 0x000022C0 +#define FLASH_O_FSM_SECTOR1 0x000022C0 // Internal -#define FLASH_O_FSM_SECTOR2 0x000022C4 +#define FLASH_O_FSM_SECTOR2 0x000022C4 // Internal -#define FLASH_O_FSM_BSLE0 0x000022E0 +#define FLASH_O_FSM_BSLE0 0x000022E0 // Internal -#define FLASH_O_FSM_BSLE1 0x000022E4 +#define FLASH_O_FSM_BSLE1 0x000022E4 // Internal -#define FLASH_O_FSM_BSLP0 0x000022F0 +#define FLASH_O_FSM_BSLP0 0x000022F0 // Internal -#define FLASH_O_FSM_BSLP1 0x000022F4 +#define FLASH_O_FSM_BSLP1 0x000022F4 // Internal -#define FLASH_O_FCFG_BANK 0x00002400 +#define FLASH_O_FCFG_BANK 0x00002400 // Internal -#define FLASH_O_FCFG_WRAPPER 0x00002404 +#define FLASH_O_FCFG_WRAPPER 0x00002404 // Internal -#define FLASH_O_FCFG_BNK_TYPE 0x00002408 +#define FLASH_O_FCFG_BNK_TYPE 0x00002408 // Internal -#define FLASH_O_FCFG_B0_START 0x00002410 +#define FLASH_O_FCFG_B0_START 0x00002410 // Internal -#define FLASH_O_FCFG_B1_START 0x00002414 +#define FLASH_O_FCFG_B1_START 0x00002414 // Internal -#define FLASH_O_FCFG_B2_START 0x00002418 +#define FLASH_O_FCFG_B2_START 0x00002418 // Internal -#define FLASH_O_FCFG_B3_START 0x0000241C +#define FLASH_O_FCFG_B3_START 0x0000241C // Internal -#define FLASH_O_FCFG_B4_START 0x00002420 +#define FLASH_O_FCFG_B4_START 0x00002420 // Internal -#define FLASH_O_FCFG_B5_START 0x00002424 +#define FLASH_O_FCFG_B5_START 0x00002424 // Internal -#define FLASH_O_FCFG_B6_START 0x00002428 +#define FLASH_O_FCFG_B6_START 0x00002428 // Internal -#define FLASH_O_FCFG_B7_START 0x0000242C +#define FLASH_O_FCFG_B7_START 0x0000242C // Internal -#define FLASH_O_FCFG_B0_SSIZE0 0x00002430 +#define FLASH_O_FCFG_B0_SSIZE0 0x00002430 //***************************************************************************** // @@ -422,37 +422,37 @@ // Efuse scanning detected if fuse ROM is blank: // 0 : Not blank // 1 : Blank -#define FLASH_STAT_EFUSE_BLANK 0x00008000 -#define FLASH_STAT_EFUSE_BLANK_BITN 15 -#define FLASH_STAT_EFUSE_BLANK_M 0x00008000 -#define FLASH_STAT_EFUSE_BLANK_S 15 +#define FLASH_STAT_EFUSE_BLANK 0x00008000 +#define FLASH_STAT_EFUSE_BLANK_BITN 15 +#define FLASH_STAT_EFUSE_BLANK_M 0x00008000 +#define FLASH_STAT_EFUSE_BLANK_S 15 // Field: [14] EFUSE_TIMEOUT // // Efuse scanning resulted in timeout error. // 0 : No Timeout error // 1 : Timeout Error -#define FLASH_STAT_EFUSE_TIMEOUT 0x00004000 -#define FLASH_STAT_EFUSE_TIMEOUT_BITN 14 -#define FLASH_STAT_EFUSE_TIMEOUT_M 0x00004000 -#define FLASH_STAT_EFUSE_TIMEOUT_S 14 +#define FLASH_STAT_EFUSE_TIMEOUT 0x00004000 +#define FLASH_STAT_EFUSE_TIMEOUT_BITN 14 +#define FLASH_STAT_EFUSE_TIMEOUT_M 0x00004000 +#define FLASH_STAT_EFUSE_TIMEOUT_S 14 // Field: [13] EFUSE_CRC_ERROR // // Efuse scanning resulted in scan chain CRC error. // 0 : No CRC error // 1 : CRC Error -#define FLASH_STAT_EFUSE_CRC_ERROR 0x00002000 -#define FLASH_STAT_EFUSE_CRC_ERROR_BITN 13 -#define FLASH_STAT_EFUSE_CRC_ERROR_M 0x00002000 -#define FLASH_STAT_EFUSE_CRC_ERROR_S 13 +#define FLASH_STAT_EFUSE_CRC_ERROR 0x00002000 +#define FLASH_STAT_EFUSE_CRC_ERROR_BITN 13 +#define FLASH_STAT_EFUSE_CRC_ERROR_M 0x00002000 +#define FLASH_STAT_EFUSE_CRC_ERROR_S 13 // Field: [12:8] EFUSE_ERRCODE // // Same as EFUSEERROR.CODE -#define FLASH_STAT_EFUSE_ERRCODE_W 5 -#define FLASH_STAT_EFUSE_ERRCODE_M 0x00001F00 -#define FLASH_STAT_EFUSE_ERRCODE_S 8 +#define FLASH_STAT_EFUSE_ERRCODE_W 5 +#define FLASH_STAT_EFUSE_ERRCODE_M 0x00001F00 +#define FLASH_STAT_EFUSE_ERRCODE_S 8 // Field: [2] SAMHOLD_DIS // @@ -460,10 +460,10 @@ // to 1 some delay after CFG.DIS_IDLE is set to 1. // 0: Not disabled // 1: Sample and hold disabled and stable -#define FLASH_STAT_SAMHOLD_DIS 0x00000004 -#define FLASH_STAT_SAMHOLD_DIS_BITN 2 -#define FLASH_STAT_SAMHOLD_DIS_M 0x00000004 -#define FLASH_STAT_SAMHOLD_DIS_S 2 +#define FLASH_STAT_SAMHOLD_DIS 0x00000004 +#define FLASH_STAT_SAMHOLD_DIS_BITN 2 +#define FLASH_STAT_SAMHOLD_DIS_M 0x00000004 +#define FLASH_STAT_SAMHOLD_DIS_S 2 // Field: [1] BUSY // @@ -472,20 +472,20 @@ // is delayed some cycles) // 0 : Not busy // 1 : Busy -#define FLASH_STAT_BUSY 0x00000002 -#define FLASH_STAT_BUSY_BITN 1 -#define FLASH_STAT_BUSY_M 0x00000002 -#define FLASH_STAT_BUSY_S 1 +#define FLASH_STAT_BUSY 0x00000002 +#define FLASH_STAT_BUSY_BITN 1 +#define FLASH_STAT_BUSY_M 0x00000002 +#define FLASH_STAT_BUSY_S 1 // Field: [0] POWER_MODE // // Power state of the flash sub-system. // 0 : Active // 1 : Low power -#define FLASH_STAT_POWER_MODE 0x00000001 -#define FLASH_STAT_POWER_MODE_BITN 0 -#define FLASH_STAT_POWER_MODE_M 0x00000001 -#define FLASH_STAT_POWER_MODE_S 0 +#define FLASH_STAT_POWER_MODE 0x00000001 +#define FLASH_STAT_POWER_MODE_BITN 0 +#define FLASH_STAT_POWER_MODE_M 0x00000001 +#define FLASH_STAT_POWER_MODE_S 0 //***************************************************************************** // @@ -495,57 +495,57 @@ // Field: [8] STANDBY_MODE_SEL // // Internal. Only to be used through TI provided API. -#define FLASH_CFG_STANDBY_MODE_SEL 0x00000100 -#define FLASH_CFG_STANDBY_MODE_SEL_BITN 8 -#define FLASH_CFG_STANDBY_MODE_SEL_M 0x00000100 -#define FLASH_CFG_STANDBY_MODE_SEL_S 8 +#define FLASH_CFG_STANDBY_MODE_SEL 0x00000100 +#define FLASH_CFG_STANDBY_MODE_SEL_BITN 8 +#define FLASH_CFG_STANDBY_MODE_SEL_M 0x00000100 +#define FLASH_CFG_STANDBY_MODE_SEL_S 8 // Field: [7:6] STANDBY_PW_SEL // // Internal. Only to be used through TI provided API. -#define FLASH_CFG_STANDBY_PW_SEL_W 2 -#define FLASH_CFG_STANDBY_PW_SEL_M 0x000000C0 -#define FLASH_CFG_STANDBY_PW_SEL_S 6 +#define FLASH_CFG_STANDBY_PW_SEL_W 2 +#define FLASH_CFG_STANDBY_PW_SEL_M 0x000000C0 +#define FLASH_CFG_STANDBY_PW_SEL_S 6 // Field: [5] DIS_EFUSECLK // // Internal. Only to be used through TI provided API. -#define FLASH_CFG_DIS_EFUSECLK 0x00000020 -#define FLASH_CFG_DIS_EFUSECLK_BITN 5 -#define FLASH_CFG_DIS_EFUSECLK_M 0x00000020 -#define FLASH_CFG_DIS_EFUSECLK_S 5 +#define FLASH_CFG_DIS_EFUSECLK 0x00000020 +#define FLASH_CFG_DIS_EFUSECLK_BITN 5 +#define FLASH_CFG_DIS_EFUSECLK_M 0x00000020 +#define FLASH_CFG_DIS_EFUSECLK_S 5 // Field: [4] DIS_READACCESS // // Internal. Only to be used through TI provided API. -#define FLASH_CFG_DIS_READACCESS 0x00000010 -#define FLASH_CFG_DIS_READACCESS_BITN 4 -#define FLASH_CFG_DIS_READACCESS_M 0x00000010 -#define FLASH_CFG_DIS_READACCESS_S 4 +#define FLASH_CFG_DIS_READACCESS 0x00000010 +#define FLASH_CFG_DIS_READACCESS_BITN 4 +#define FLASH_CFG_DIS_READACCESS_M 0x00000010 +#define FLASH_CFG_DIS_READACCESS_S 4 // Field: [3] ENABLE_SWINTF // // Internal. Only to be used through TI provided API. -#define FLASH_CFG_ENABLE_SWINTF 0x00000008 -#define FLASH_CFG_ENABLE_SWINTF_BITN 3 -#define FLASH_CFG_ENABLE_SWINTF_M 0x00000008 -#define FLASH_CFG_ENABLE_SWINTF_S 3 +#define FLASH_CFG_ENABLE_SWINTF 0x00000008 +#define FLASH_CFG_ENABLE_SWINTF_BITN 3 +#define FLASH_CFG_ENABLE_SWINTF_M 0x00000008 +#define FLASH_CFG_ENABLE_SWINTF_S 3 // Field: [1] DIS_STANDBY // // Internal. Only to be used through TI provided API. -#define FLASH_CFG_DIS_STANDBY 0x00000002 -#define FLASH_CFG_DIS_STANDBY_BITN 1 -#define FLASH_CFG_DIS_STANDBY_M 0x00000002 -#define FLASH_CFG_DIS_STANDBY_S 1 +#define FLASH_CFG_DIS_STANDBY 0x00000002 +#define FLASH_CFG_DIS_STANDBY_BITN 1 +#define FLASH_CFG_DIS_STANDBY_M 0x00000002 +#define FLASH_CFG_DIS_STANDBY_S 1 // Field: [0] DIS_IDLE // // Internal. Only to be used through TI provided API. -#define FLASH_CFG_DIS_IDLE 0x00000001 -#define FLASH_CFG_DIS_IDLE_BITN 0 -#define FLASH_CFG_DIS_IDLE_M 0x00000001 -#define FLASH_CFG_DIS_IDLE_S 0 +#define FLASH_CFG_DIS_IDLE 0x00000001 +#define FLASH_CFG_DIS_IDLE_BITN 0 +#define FLASH_CFG_DIS_IDLE_M 0x00000001 +#define FLASH_CFG_DIS_IDLE_S 0 //***************************************************************************** // @@ -555,9 +555,9 @@ // Field: [4:0] SYSCODE_START // // Internal. Only to be used through TI provided API. -#define FLASH_SYSCODE_START_SYSCODE_START_W 5 -#define FLASH_SYSCODE_START_SYSCODE_START_M 0x0000001F -#define FLASH_SYSCODE_START_SYSCODE_START_S 0 +#define FLASH_SYSCODE_START_SYSCODE_START_W 5 +#define FLASH_SYSCODE_START_SYSCODE_START_M 0x0000001F +#define FLASH_SYSCODE_START_SYSCODE_START_S 0 //***************************************************************************** // @@ -567,9 +567,9 @@ // Field: [7:0] SECTORS // // Internal. Only to be used through TI provided API. -#define FLASH_FLASH_SIZE_SECTORS_W 8 -#define FLASH_FLASH_SIZE_SECTORS_M 0x000000FF -#define FLASH_FLASH_SIZE_SECTORS_S 0 +#define FLASH_FLASH_SIZE_SECTORS_W 8 +#define FLASH_FLASH_SIZE_SECTORS_M 0x000000FF +#define FLASH_FLASH_SIZE_SECTORS_S 0 //***************************************************************************** // @@ -579,9 +579,9 @@ // Field: [2:0] FWLOCK // // Internal. Only to be used through TI provided API. -#define FLASH_FWLOCK_FWLOCK_W 3 -#define FLASH_FWLOCK_FWLOCK_M 0x00000007 -#define FLASH_FWLOCK_FWLOCK_S 0 +#define FLASH_FWLOCK_FWLOCK_W 3 +#define FLASH_FWLOCK_FWLOCK_M 0x00000007 +#define FLASH_FWLOCK_FWLOCK_S 0 //***************************************************************************** // @@ -591,9 +591,9 @@ // Field: [2:0] FWFLAG // // Internal. Only to be used through TI provided API. -#define FLASH_FWFLAG_FWFLAG_W 3 -#define FLASH_FWFLAG_FWFLAG_M 0x00000007 -#define FLASH_FWFLAG_FWFLAG_S 0 +#define FLASH_FWFLAG_FWFLAG_W 3 +#define FLASH_FWFLAG_FWFLAG_M 0x00000007 +#define FLASH_FWFLAG_FWFLAG_S 0 //***************************************************************************** // @@ -603,16 +603,16 @@ // Field: [28:24] INSTRUCTION // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSE_INSTRUCTION_W 5 -#define FLASH_EFUSE_INSTRUCTION_M 0x1F000000 -#define FLASH_EFUSE_INSTRUCTION_S 24 +#define FLASH_EFUSE_INSTRUCTION_W 5 +#define FLASH_EFUSE_INSTRUCTION_M 0x1F000000 +#define FLASH_EFUSE_INSTRUCTION_S 24 // Field: [15:0] DUMPWORD // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSE_DUMPWORD_W 16 -#define FLASH_EFUSE_DUMPWORD_M 0x0000FFFF -#define FLASH_EFUSE_DUMPWORD_S 0 +#define FLASH_EFUSE_DUMPWORD_W 16 +#define FLASH_EFUSE_DUMPWORD_M 0x0000FFFF +#define FLASH_EFUSE_DUMPWORD_S 0 //***************************************************************************** // @@ -622,16 +622,16 @@ // Field: [15:11] BLOCK // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEADDR_BLOCK_W 5 -#define FLASH_EFUSEADDR_BLOCK_M 0x0000F800 -#define FLASH_EFUSEADDR_BLOCK_S 11 +#define FLASH_EFUSEADDR_BLOCK_W 5 +#define FLASH_EFUSEADDR_BLOCK_M 0x0000F800 +#define FLASH_EFUSEADDR_BLOCK_S 11 // Field: [10:0] ROW // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEADDR_ROW_W 11 -#define FLASH_EFUSEADDR_ROW_M 0x000007FF -#define FLASH_EFUSEADDR_ROW_S 0 +#define FLASH_EFUSEADDR_ROW_W 11 +#define FLASH_EFUSEADDR_ROW_M 0x000007FF +#define FLASH_EFUSEADDR_ROW_S 0 //***************************************************************************** // @@ -641,33 +641,33 @@ // Field: [7:3] SPARE // // Internal. Only to be used through TI provided API. -#define FLASH_DATAUPPER_SPARE_W 5 -#define FLASH_DATAUPPER_SPARE_M 0x000000F8 -#define FLASH_DATAUPPER_SPARE_S 3 +#define FLASH_DATAUPPER_SPARE_W 5 +#define FLASH_DATAUPPER_SPARE_M 0x000000F8 +#define FLASH_DATAUPPER_SPARE_S 3 // Field: [2] P // // Internal. Only to be used through TI provided API. -#define FLASH_DATAUPPER_P 0x00000004 -#define FLASH_DATAUPPER_P_BITN 2 -#define FLASH_DATAUPPER_P_M 0x00000004 -#define FLASH_DATAUPPER_P_S 2 +#define FLASH_DATAUPPER_P 0x00000004 +#define FLASH_DATAUPPER_P_BITN 2 +#define FLASH_DATAUPPER_P_M 0x00000004 +#define FLASH_DATAUPPER_P_S 2 // Field: [1] R // // Internal. Only to be used through TI provided API. -#define FLASH_DATAUPPER_R 0x00000002 -#define FLASH_DATAUPPER_R_BITN 1 -#define FLASH_DATAUPPER_R_M 0x00000002 -#define FLASH_DATAUPPER_R_S 1 +#define FLASH_DATAUPPER_R 0x00000002 +#define FLASH_DATAUPPER_R_BITN 1 +#define FLASH_DATAUPPER_R_M 0x00000002 +#define FLASH_DATAUPPER_R_S 1 // Field: [0] EEN // // Internal. Only to be used through TI provided API. -#define FLASH_DATAUPPER_EEN 0x00000001 -#define FLASH_DATAUPPER_EEN_BITN 0 -#define FLASH_DATAUPPER_EEN_M 0x00000001 -#define FLASH_DATAUPPER_EEN_S 0 +#define FLASH_DATAUPPER_EEN 0x00000001 +#define FLASH_DATAUPPER_EEN_BITN 0 +#define FLASH_DATAUPPER_EEN_M 0x00000001 +#define FLASH_DATAUPPER_EEN_S 0 //***************************************************************************** // @@ -677,9 +677,9 @@ // Field: [31:0] DATA // // Internal. Only to be used through TI provided API. -#define FLASH_DATALOWER_DATA_W 32 -#define FLASH_DATALOWER_DATA_M 0xFFFFFFFF -#define FLASH_DATALOWER_DATA_S 0 +#define FLASH_DATALOWER_DATA_W 32 +#define FLASH_DATALOWER_DATA_M 0xFFFFFFFF +#define FLASH_DATALOWER_DATA_S 0 //***************************************************************************** // @@ -689,25 +689,25 @@ // Field: [8] IDLEGATING // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSECFG_IDLEGATING 0x00000100 -#define FLASH_EFUSECFG_IDLEGATING_BITN 8 -#define FLASH_EFUSECFG_IDLEGATING_M 0x00000100 -#define FLASH_EFUSECFG_IDLEGATING_S 8 +#define FLASH_EFUSECFG_IDLEGATING 0x00000100 +#define FLASH_EFUSECFG_IDLEGATING_BITN 8 +#define FLASH_EFUSECFG_IDLEGATING_M 0x00000100 +#define FLASH_EFUSECFG_IDLEGATING_S 8 // Field: [4:3] SLAVEPOWER // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSECFG_SLAVEPOWER_W 2 -#define FLASH_EFUSECFG_SLAVEPOWER_M 0x00000018 -#define FLASH_EFUSECFG_SLAVEPOWER_S 3 +#define FLASH_EFUSECFG_SLAVEPOWER_W 2 +#define FLASH_EFUSECFG_SLAVEPOWER_M 0x00000018 +#define FLASH_EFUSECFG_SLAVEPOWER_S 3 // Field: [0] GATING // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSECFG_GATING 0x00000001 -#define FLASH_EFUSECFG_GATING_BITN 0 -#define FLASH_EFUSECFG_GATING_M 0x00000001 -#define FLASH_EFUSECFG_GATING_S 0 +#define FLASH_EFUSECFG_GATING 0x00000001 +#define FLASH_EFUSECFG_GATING_BITN 0 +#define FLASH_EFUSECFG_GATING_M 0x00000001 +#define FLASH_EFUSECFG_GATING_S 0 //***************************************************************************** // @@ -717,10 +717,10 @@ // Field: [0] RESETDONE // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSESTAT_RESETDONE 0x00000001 -#define FLASH_EFUSESTAT_RESETDONE_BITN 0 -#define FLASH_EFUSESTAT_RESETDONE_M 0x00000001 -#define FLASH_EFUSESTAT_RESETDONE_S 0 +#define FLASH_EFUSESTAT_RESETDONE 0x00000001 +#define FLASH_EFUSESTAT_RESETDONE_BITN 0 +#define FLASH_EFUSESTAT_RESETDONE_M 0x00000001 +#define FLASH_EFUSESTAT_RESETDONE_S 0 //***************************************************************************** // @@ -730,9 +730,9 @@ // Field: [23:0] ACCUMULATOR // // Internal. Only to be used through TI provided API. -#define FLASH_ACC_ACCUMULATOR_W 24 -#define FLASH_ACC_ACCUMULATOR_M 0x00FFFFFF -#define FLASH_ACC_ACCUMULATOR_S 0 +#define FLASH_ACC_ACCUMULATOR_W 24 +#define FLASH_ACC_ACCUMULATOR_M 0x00FFFFFF +#define FLASH_ACC_ACCUMULATOR_S 0 //***************************************************************************** // @@ -742,110 +742,110 @@ // Field: [23] DISROW0 // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_DISROW0 0x00800000 -#define FLASH_BOUNDARY_DISROW0_BITN 23 -#define FLASH_BOUNDARY_DISROW0_M 0x00800000 -#define FLASH_BOUNDARY_DISROW0_S 23 +#define FLASH_BOUNDARY_DISROW0 0x00800000 +#define FLASH_BOUNDARY_DISROW0_BITN 23 +#define FLASH_BOUNDARY_DISROW0_M 0x00800000 +#define FLASH_BOUNDARY_DISROW0_S 23 // Field: [22] SPARE // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SPARE 0x00400000 -#define FLASH_BOUNDARY_SPARE_BITN 22 -#define FLASH_BOUNDARY_SPARE_M 0x00400000 -#define FLASH_BOUNDARY_SPARE_S 22 +#define FLASH_BOUNDARY_SPARE 0x00400000 +#define FLASH_BOUNDARY_SPARE_BITN 22 +#define FLASH_BOUNDARY_SPARE_M 0x00400000 +#define FLASH_BOUNDARY_SPARE_S 22 // Field: [21] EFC_SELF_TEST_ERROR // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR 0x00200000 -#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_BITN 21 -#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_M 0x00200000 -#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_S 21 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR 0x00200000 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_BITN 21 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_M 0x00200000 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_S 21 // Field: [20] EFC_INSTRUCTION_INFO // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO 0x00100000 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_BITN 20 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_M 0x00100000 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_S 20 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO 0x00100000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_BITN 20 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_M 0x00100000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_S 20 // Field: [19] EFC_INSTRUCTION_ERROR // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR 0x00080000 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_BITN 19 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_M 0x00080000 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_S 19 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR 0x00080000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_BITN 19 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_M 0x00080000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_S 19 // Field: [18] EFC_AUTOLOAD_ERROR // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR 0x00040000 -#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_BITN 18 -#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_M 0x00040000 -#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_S 18 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR 0x00040000 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_BITN 18 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_M 0x00040000 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_S 18 // Field: [17:14] OUTPUTENABLE // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_OUTPUTENABLE_W 4 -#define FLASH_BOUNDARY_OUTPUTENABLE_M 0x0003C000 -#define FLASH_BOUNDARY_OUTPUTENABLE_S 14 +#define FLASH_BOUNDARY_OUTPUTENABLE_W 4 +#define FLASH_BOUNDARY_OUTPUTENABLE_M 0x0003C000 +#define FLASH_BOUNDARY_OUTPUTENABLE_S 14 // Field: [13] SYS_ECC_SELF_TEST_EN // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN 0x00002000 -#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_BITN 13 -#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_M 0x00002000 -#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_S 13 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN 0x00002000 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_BITN 13 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_M 0x00002000 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_S 13 // Field: [12] SYS_ECC_OVERRIDE_EN // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN 0x00001000 -#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_BITN 12 -#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_M 0x00001000 -#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_S 12 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN 0x00001000 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_BITN 12 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_M 0x00001000 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_S 12 // Field: [11] EFC_FDI // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_FDI 0x00000800 -#define FLASH_BOUNDARY_EFC_FDI_BITN 11 -#define FLASH_BOUNDARY_EFC_FDI_M 0x00000800 -#define FLASH_BOUNDARY_EFC_FDI_S 11 +#define FLASH_BOUNDARY_EFC_FDI 0x00000800 +#define FLASH_BOUNDARY_EFC_FDI_BITN 11 +#define FLASH_BOUNDARY_EFC_FDI_M 0x00000800 +#define FLASH_BOUNDARY_EFC_FDI_S 11 // Field: [10] SYS_DIEID_AUTOLOAD_EN // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN 0x00000400 -#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_BITN 10 -#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_M 0x00000400 -#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_S 10 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN 0x00000400 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_BITN 10 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_M 0x00000400 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_S 10 // Field: [9:8] SYS_REPAIR_EN // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_REPAIR_EN_W 2 -#define FLASH_BOUNDARY_SYS_REPAIR_EN_M 0x00000300 -#define FLASH_BOUNDARY_SYS_REPAIR_EN_S 8 +#define FLASH_BOUNDARY_SYS_REPAIR_EN_W 2 +#define FLASH_BOUNDARY_SYS_REPAIR_EN_M 0x00000300 +#define FLASH_BOUNDARY_SYS_REPAIR_EN_S 8 // Field: [7:4] SYS_WS_READ_STATES // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_WS_READ_STATES_W 4 -#define FLASH_BOUNDARY_SYS_WS_READ_STATES_M 0x000000F0 -#define FLASH_BOUNDARY_SYS_WS_READ_STATES_S 4 +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_W 4 +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_M 0x000000F0 +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_S 4 // Field: [3:0] INPUTENABLE // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_INPUTENABLE_W 4 -#define FLASH_BOUNDARY_INPUTENABLE_M 0x0000000F -#define FLASH_BOUNDARY_INPUTENABLE_S 0 +#define FLASH_BOUNDARY_INPUTENABLE_W 4 +#define FLASH_BOUNDARY_INPUTENABLE_M 0x0000000F +#define FLASH_BOUNDARY_INPUTENABLE_S 0 //***************************************************************************** // @@ -855,10 +855,10 @@ // Field: [0] KEY // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEFLAG_KEY 0x00000001 -#define FLASH_EFUSEFLAG_KEY_BITN 0 -#define FLASH_EFUSEFLAG_KEY_M 0x00000001 -#define FLASH_EFUSEFLAG_KEY_S 0 +#define FLASH_EFUSEFLAG_KEY 0x00000001 +#define FLASH_EFUSEFLAG_KEY_BITN 0 +#define FLASH_EFUSEFLAG_KEY_M 0x00000001 +#define FLASH_EFUSEFLAG_KEY_S 0 //***************************************************************************** // @@ -868,9 +868,9 @@ // Field: [31:0] CODE // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEKEY_CODE_W 32 -#define FLASH_EFUSEKEY_CODE_M 0xFFFFFFFF -#define FLASH_EFUSEKEY_CODE_S 0 +#define FLASH_EFUSEKEY_CODE_W 32 +#define FLASH_EFUSEKEY_CODE_M 0xFFFFFFFF +#define FLASH_EFUSEKEY_CODE_S 0 //***************************************************************************** // @@ -880,44 +880,44 @@ // Field: [31:25] ODPYEAR // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_ODPYEAR_W 7 -#define FLASH_EFUSERELEASE_ODPYEAR_M 0xFE000000 -#define FLASH_EFUSERELEASE_ODPYEAR_S 25 +#define FLASH_EFUSERELEASE_ODPYEAR_W 7 +#define FLASH_EFUSERELEASE_ODPYEAR_M 0xFE000000 +#define FLASH_EFUSERELEASE_ODPYEAR_S 25 // Field: [24:21] ODPMONTH // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_ODPMONTH_W 4 -#define FLASH_EFUSERELEASE_ODPMONTH_M 0x01E00000 -#define FLASH_EFUSERELEASE_ODPMONTH_S 21 +#define FLASH_EFUSERELEASE_ODPMONTH_W 4 +#define FLASH_EFUSERELEASE_ODPMONTH_M 0x01E00000 +#define FLASH_EFUSERELEASE_ODPMONTH_S 21 // Field: [20:16] ODPDAY // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_ODPDAY_W 5 -#define FLASH_EFUSERELEASE_ODPDAY_M 0x001F0000 -#define FLASH_EFUSERELEASE_ODPDAY_S 16 +#define FLASH_EFUSERELEASE_ODPDAY_W 5 +#define FLASH_EFUSERELEASE_ODPDAY_M 0x001F0000 +#define FLASH_EFUSERELEASE_ODPDAY_S 16 // Field: [15:9] EFUSEYEAR // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_EFUSEYEAR_W 7 -#define FLASH_EFUSERELEASE_EFUSEYEAR_M 0x0000FE00 -#define FLASH_EFUSERELEASE_EFUSEYEAR_S 9 +#define FLASH_EFUSERELEASE_EFUSEYEAR_W 7 +#define FLASH_EFUSERELEASE_EFUSEYEAR_M 0x0000FE00 +#define FLASH_EFUSERELEASE_EFUSEYEAR_S 9 // Field: [8:5] EFUSEMONTH // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_EFUSEMONTH_W 4 -#define FLASH_EFUSERELEASE_EFUSEMONTH_M 0x000001E0 -#define FLASH_EFUSERELEASE_EFUSEMONTH_S 5 +#define FLASH_EFUSERELEASE_EFUSEMONTH_W 4 +#define FLASH_EFUSERELEASE_EFUSEMONTH_M 0x000001E0 +#define FLASH_EFUSERELEASE_EFUSEMONTH_S 5 // Field: [4:0] EFUSEDAY // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_EFUSEDAY_W 5 -#define FLASH_EFUSERELEASE_EFUSEDAY_M 0x0000001F -#define FLASH_EFUSERELEASE_EFUSEDAY_S 0 +#define FLASH_EFUSERELEASE_EFUSEDAY_W 5 +#define FLASH_EFUSERELEASE_EFUSEDAY_M 0x0000001F +#define FLASH_EFUSERELEASE_EFUSEDAY_S 0 //***************************************************************************** // @@ -927,96 +927,96 @@ // Field: [15] EFC_SELF_TEST_DONE // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE 0x00008000 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_BITN 15 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_M 0x00008000 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_S 15 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE 0x00008000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_BITN 15 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_M 0x00008000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_S 15 // Field: [14] EFC_SELF_TEST_ERROR // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR 0x00004000 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_BITN 14 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_M 0x00004000 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_S 14 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR 0x00004000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_BITN 14 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_M 0x00004000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_S 14 // Field: [13] SYS_ECC_SELF_TEST_EN // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN 0x00002000 -#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_BITN 13 -#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_M 0x00002000 -#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_S 13 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN 0x00002000 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_BITN 13 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_M 0x00002000 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_S 13 // Field: [12] EFC_INSTRUCTION_INFO // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO 0x00001000 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_BITN 12 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_M 0x00001000 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_S 12 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO 0x00001000 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_BITN 12 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_M 0x00001000 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_S 12 // Field: [11] EFC_INSTRUCTION_ERROR // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR 0x00000800 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_BITN 11 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_M 0x00000800 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_S 11 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR 0x00000800 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_BITN 11 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_M 0x00000800 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_S 11 // Field: [10] EFC_AUTOLOAD_ERROR // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR 0x00000400 -#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_BITN 10 -#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_M 0x00000400 -#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_S 10 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR 0x00000400 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_BITN 10 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_M 0x00000400 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_S 10 // Field: [9] SYS_ECC_OVERRIDE_EN // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN 0x00000200 -#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_BITN 9 -#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_M 0x00000200 -#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_S 9 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN 0x00000200 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_BITN 9 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_M 0x00000200 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_S 9 // Field: [8] EFC_READY // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_READY 0x00000100 -#define FLASH_EFUSEPINS_EFC_READY_BITN 8 -#define FLASH_EFUSEPINS_EFC_READY_M 0x00000100 -#define FLASH_EFUSEPINS_EFC_READY_S 8 +#define FLASH_EFUSEPINS_EFC_READY 0x00000100 +#define FLASH_EFUSEPINS_EFC_READY_BITN 8 +#define FLASH_EFUSEPINS_EFC_READY_M 0x00000100 +#define FLASH_EFUSEPINS_EFC_READY_S 8 // Field: [7] EFC_FCLRZ // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_FCLRZ 0x00000080 -#define FLASH_EFUSEPINS_EFC_FCLRZ_BITN 7 -#define FLASH_EFUSEPINS_EFC_FCLRZ_M 0x00000080 -#define FLASH_EFUSEPINS_EFC_FCLRZ_S 7 +#define FLASH_EFUSEPINS_EFC_FCLRZ 0x00000080 +#define FLASH_EFUSEPINS_EFC_FCLRZ_BITN 7 +#define FLASH_EFUSEPINS_EFC_FCLRZ_M 0x00000080 +#define FLASH_EFUSEPINS_EFC_FCLRZ_S 7 // Field: [6] SYS_DIEID_AUTOLOAD_EN // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN 0x00000040 -#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_BITN 6 -#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_M 0x00000040 -#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_S 6 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN 0x00000040 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_BITN 6 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_M 0x00000040 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_S 6 // Field: [5:4] SYS_REPAIR_EN // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_REPAIR_EN_W 2 -#define FLASH_EFUSEPINS_SYS_REPAIR_EN_M 0x00000030 -#define FLASH_EFUSEPINS_SYS_REPAIR_EN_S 4 +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_W 2 +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_M 0x00000030 +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_S 4 // Field: [3:0] SYS_WS_READ_STATES // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_W 4 -#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_M 0x0000000F -#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_S 0 +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_W 4 +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_M 0x0000000F +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_S 0 //***************************************************************************** // @@ -1026,9 +1026,9 @@ // Field: [5:0] DATA // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSECRA_DATA_W 6 -#define FLASH_EFUSECRA_DATA_M 0x0000003F -#define FLASH_EFUSECRA_DATA_S 0 +#define FLASH_EFUSECRA_DATA_W 6 +#define FLASH_EFUSECRA_DATA_M 0x0000003F +#define FLASH_EFUSECRA_DATA_S 0 //***************************************************************************** // @@ -1038,39 +1038,39 @@ // Field: [9:8] DATABIT // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_DATABIT_W 2 -#define FLASH_EFUSEREAD_DATABIT_M 0x00000300 -#define FLASH_EFUSEREAD_DATABIT_S 8 +#define FLASH_EFUSEREAD_DATABIT_W 2 +#define FLASH_EFUSEREAD_DATABIT_M 0x00000300 +#define FLASH_EFUSEREAD_DATABIT_S 8 // Field: [7:4] READCLOCK // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_READCLOCK_W 4 -#define FLASH_EFUSEREAD_READCLOCK_M 0x000000F0 -#define FLASH_EFUSEREAD_READCLOCK_S 4 +#define FLASH_EFUSEREAD_READCLOCK_W 4 +#define FLASH_EFUSEREAD_READCLOCK_M 0x000000F0 +#define FLASH_EFUSEREAD_READCLOCK_S 4 // Field: [3] DEBUG // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_DEBUG 0x00000008 -#define FLASH_EFUSEREAD_DEBUG_BITN 3 -#define FLASH_EFUSEREAD_DEBUG_M 0x00000008 -#define FLASH_EFUSEREAD_DEBUG_S 3 +#define FLASH_EFUSEREAD_DEBUG 0x00000008 +#define FLASH_EFUSEREAD_DEBUG_BITN 3 +#define FLASH_EFUSEREAD_DEBUG_M 0x00000008 +#define FLASH_EFUSEREAD_DEBUG_S 3 // Field: [2] SPARE // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_SPARE 0x00000004 -#define FLASH_EFUSEREAD_SPARE_BITN 2 -#define FLASH_EFUSEREAD_SPARE_M 0x00000004 -#define FLASH_EFUSEREAD_SPARE_S 2 +#define FLASH_EFUSEREAD_SPARE 0x00000004 +#define FLASH_EFUSEREAD_SPARE_BITN 2 +#define FLASH_EFUSEREAD_SPARE_M 0x00000004 +#define FLASH_EFUSEREAD_SPARE_S 2 // Field: [1:0] MARGIN // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_MARGIN_W 2 -#define FLASH_EFUSEREAD_MARGIN_M 0x00000003 -#define FLASH_EFUSEREAD_MARGIN_S 0 +#define FLASH_EFUSEREAD_MARGIN_W 2 +#define FLASH_EFUSEREAD_MARGIN_M 0x00000003 +#define FLASH_EFUSEREAD_MARGIN_S 0 //***************************************************************************** // @@ -1080,39 +1080,39 @@ // Field: [30] COMPAREDISABLE // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_COMPAREDISABLE 0x40000000 -#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_BITN 30 -#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_M 0x40000000 -#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_S 30 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE 0x40000000 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_BITN 30 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_M 0x40000000 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_S 30 // Field: [29:14] CLOCKSTALL // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_CLOCKSTALL_W 16 -#define FLASH_EFUSEPROGRAM_CLOCKSTALL_M 0x3FFFC000 -#define FLASH_EFUSEPROGRAM_CLOCKSTALL_S 14 +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_W 16 +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_M 0x3FFFC000 +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_S 14 // Field: [13] VPPTOVDD // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_VPPTOVDD 0x00002000 -#define FLASH_EFUSEPROGRAM_VPPTOVDD_BITN 13 -#define FLASH_EFUSEPROGRAM_VPPTOVDD_M 0x00002000 -#define FLASH_EFUSEPROGRAM_VPPTOVDD_S 13 +#define FLASH_EFUSEPROGRAM_VPPTOVDD 0x00002000 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_BITN 13 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_M 0x00002000 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_S 13 // Field: [12:9] ITERATIONS // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_ITERATIONS_W 4 -#define FLASH_EFUSEPROGRAM_ITERATIONS_M 0x00001E00 -#define FLASH_EFUSEPROGRAM_ITERATIONS_S 9 +#define FLASH_EFUSEPROGRAM_ITERATIONS_W 4 +#define FLASH_EFUSEPROGRAM_ITERATIONS_M 0x00001E00 +#define FLASH_EFUSEPROGRAM_ITERATIONS_S 9 // Field: [8:0] WRITECLOCK // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_WRITECLOCK_W 9 -#define FLASH_EFUSEPROGRAM_WRITECLOCK_M 0x000001FF -#define FLASH_EFUSEPROGRAM_WRITECLOCK_S 0 +#define FLASH_EFUSEPROGRAM_WRITECLOCK_W 9 +#define FLASH_EFUSEPROGRAM_WRITECLOCK_M 0x000001FF +#define FLASH_EFUSEPROGRAM_WRITECLOCK_S 0 //***************************************************************************** // @@ -1122,17 +1122,17 @@ // Field: [5] DONE // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEERROR_DONE 0x00000020 -#define FLASH_EFUSEERROR_DONE_BITN 5 -#define FLASH_EFUSEERROR_DONE_M 0x00000020 -#define FLASH_EFUSEERROR_DONE_S 5 +#define FLASH_EFUSEERROR_DONE 0x00000020 +#define FLASH_EFUSEERROR_DONE_BITN 5 +#define FLASH_EFUSEERROR_DONE_M 0x00000020 +#define FLASH_EFUSEERROR_DONE_S 5 // Field: [4:0] CODE // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEERROR_CODE_W 5 -#define FLASH_EFUSEERROR_CODE_M 0x0000001F -#define FLASH_EFUSEERROR_CODE_S 0 +#define FLASH_EFUSEERROR_CODE_W 5 +#define FLASH_EFUSEERROR_CODE_M 0x0000001F +#define FLASH_EFUSEERROR_CODE_S 0 //***************************************************************************** // @@ -1142,17 +1142,17 @@ // Field: [31:1] FROMN // // Internal. Only to be used through TI provided API. -#define FLASH_SINGLEBIT_FROMN_W 31 -#define FLASH_SINGLEBIT_FROMN_M 0xFFFFFFFE -#define FLASH_SINGLEBIT_FROMN_S 1 +#define FLASH_SINGLEBIT_FROMN_W 31 +#define FLASH_SINGLEBIT_FROMN_M 0xFFFFFFFE +#define FLASH_SINGLEBIT_FROMN_S 1 // Field: [0] FROM0 // // Internal. Only to be used through TI provided API. -#define FLASH_SINGLEBIT_FROM0 0x00000001 -#define FLASH_SINGLEBIT_FROM0_BITN 0 -#define FLASH_SINGLEBIT_FROM0_M 0x00000001 -#define FLASH_SINGLEBIT_FROM0_S 0 +#define FLASH_SINGLEBIT_FROM0 0x00000001 +#define FLASH_SINGLEBIT_FROM0_BITN 0 +#define FLASH_SINGLEBIT_FROM0_M 0x00000001 +#define FLASH_SINGLEBIT_FROM0_S 0 //***************************************************************************** // @@ -1162,17 +1162,17 @@ // Field: [31:1] FROMN // // Internal. Only to be used through TI provided API. -#define FLASH_TWOBIT_FROMN_W 31 -#define FLASH_TWOBIT_FROMN_M 0xFFFFFFFE -#define FLASH_TWOBIT_FROMN_S 1 +#define FLASH_TWOBIT_FROMN_W 31 +#define FLASH_TWOBIT_FROMN_M 0xFFFFFFFE +#define FLASH_TWOBIT_FROMN_S 1 // Field: [0] FROM0 // // Internal. Only to be used through TI provided API. -#define FLASH_TWOBIT_FROM0 0x00000001 -#define FLASH_TWOBIT_FROM0_BITN 0 -#define FLASH_TWOBIT_FROM0_M 0x00000001 -#define FLASH_TWOBIT_FROM0_S 0 +#define FLASH_TWOBIT_FROM0 0x00000001 +#define FLASH_TWOBIT_FROM0_BITN 0 +#define FLASH_TWOBIT_FROM0_M 0x00000001 +#define FLASH_TWOBIT_FROM0_S 0 //***************************************************************************** // @@ -1182,9 +1182,9 @@ // Field: [31:0] CYCLES // // Internal. Only to be used through TI provided API. -#define FLASH_SELFTESTCYC_CYCLES_W 32 -#define FLASH_SELFTESTCYC_CYCLES_M 0xFFFFFFFF -#define FLASH_SELFTESTCYC_CYCLES_S 0 +#define FLASH_SELFTESTCYC_CYCLES_W 32 +#define FLASH_SELFTESTCYC_CYCLES_M 0xFFFFFFFF +#define FLASH_SELFTESTCYC_CYCLES_S 0 //***************************************************************************** // @@ -1194,9 +1194,9 @@ // Field: [31:0] SIGNATURE // // Internal. Only to be used through TI provided API. -#define FLASH_SELFTESTSIGN_SIGNATURE_W 32 -#define FLASH_SELFTESTSIGN_SIGNATURE_M 0xFFFFFFFF -#define FLASH_SELFTESTSIGN_SIGNATURE_S 0 +#define FLASH_SELFTESTSIGN_SIGNATURE_W 32 +#define FLASH_SELFTESTSIGN_SIGNATURE_M 0xFFFFFFFF +#define FLASH_SELFTESTSIGN_SIGNATURE_S 0 //***************************************************************************** // @@ -1206,9 +1206,9 @@ // Field: [11:8] RWAIT // // Internal. Only to be used through TI provided API. -#define FLASH_FRDCTL_RWAIT_W 4 -#define FLASH_FRDCTL_RWAIT_M 0x00000F00 -#define FLASH_FRDCTL_RWAIT_S 8 +#define FLASH_FRDCTL_RWAIT_W 4 +#define FLASH_FRDCTL_RWAIT_M 0x00000F00 +#define FLASH_FRDCTL_RWAIT_S 8 //***************************************************************************** // @@ -1218,25 +1218,25 @@ // Field: [15:8] RMBSEM // // Internal. Only to be used through TI provided API. -#define FLASH_FSPRD_RMBSEM_W 8 -#define FLASH_FSPRD_RMBSEM_M 0x0000FF00 -#define FLASH_FSPRD_RMBSEM_S 8 +#define FLASH_FSPRD_RMBSEM_W 8 +#define FLASH_FSPRD_RMBSEM_M 0x0000FF00 +#define FLASH_FSPRD_RMBSEM_S 8 // Field: [1] RM1 // // Internal. Only to be used through TI provided API. -#define FLASH_FSPRD_RM1 0x00000002 -#define FLASH_FSPRD_RM1_BITN 1 -#define FLASH_FSPRD_RM1_M 0x00000002 -#define FLASH_FSPRD_RM1_S 1 +#define FLASH_FSPRD_RM1 0x00000002 +#define FLASH_FSPRD_RM1_BITN 1 +#define FLASH_FSPRD_RM1_M 0x00000002 +#define FLASH_FSPRD_RM1_S 1 // Field: [0] RM0 // // Internal. Only to be used through TI provided API. -#define FLASH_FSPRD_RM0 0x00000001 -#define FLASH_FSPRD_RM0_BITN 0 -#define FLASH_FSPRD_RM0_M 0x00000001 -#define FLASH_FSPRD_RM0_S 0 +#define FLASH_FSPRD_RM0 0x00000001 +#define FLASH_FSPRD_RM0_BITN 0 +#define FLASH_FSPRD_RM0_M 0x00000001 +#define FLASH_FSPRD_RM0_S 0 //***************************************************************************** // @@ -1246,10 +1246,10 @@ // Field: [24] SUSP_IGNR // // Internal. Only to be used through TI provided API. -#define FLASH_FEDACCTL1_SUSP_IGNR 0x01000000 -#define FLASH_FEDACCTL1_SUSP_IGNR_BITN 24 -#define FLASH_FEDACCTL1_SUSP_IGNR_M 0x01000000 -#define FLASH_FEDACCTL1_SUSP_IGNR_S 24 +#define FLASH_FEDACCTL1_SUSP_IGNR 0x01000000 +#define FLASH_FEDACCTL1_SUSP_IGNR_BITN 24 +#define FLASH_FEDACCTL1_SUSP_IGNR_M 0x01000000 +#define FLASH_FEDACCTL1_SUSP_IGNR_S 24 //***************************************************************************** // @@ -1259,18 +1259,18 @@ // Field: [25] RVF_INT // // Internal. Only to be used through TI provided API. -#define FLASH_FEDACSTAT_RVF_INT 0x02000000 -#define FLASH_FEDACSTAT_RVF_INT_BITN 25 -#define FLASH_FEDACSTAT_RVF_INT_M 0x02000000 -#define FLASH_FEDACSTAT_RVF_INT_S 25 +#define FLASH_FEDACSTAT_RVF_INT 0x02000000 +#define FLASH_FEDACSTAT_RVF_INT_BITN 25 +#define FLASH_FEDACSTAT_RVF_INT_M 0x02000000 +#define FLASH_FEDACSTAT_RVF_INT_S 25 // Field: [24] FSM_DONE // // Internal. Only to be used through TI provided API. -#define FLASH_FEDACSTAT_FSM_DONE 0x01000000 -#define FLASH_FEDACSTAT_FSM_DONE_BITN 24 -#define FLASH_FEDACSTAT_FSM_DONE_M 0x01000000 -#define FLASH_FEDACSTAT_FSM_DONE_S 24 +#define FLASH_FEDACSTAT_FSM_DONE 0x01000000 +#define FLASH_FEDACSTAT_FSM_DONE_BITN 24 +#define FLASH_FEDACSTAT_FSM_DONE_M 0x01000000 +#define FLASH_FEDACSTAT_FSM_DONE_S 24 //***************************************************************************** // @@ -1280,10 +1280,10 @@ // Field: [0] PROTL1DIS // // Internal. Only to be used through TI provided API. -#define FLASH_FBPROT_PROTL1DIS 0x00000001 -#define FLASH_FBPROT_PROTL1DIS_BITN 0 -#define FLASH_FBPROT_PROTL1DIS_M 0x00000001 -#define FLASH_FBPROT_PROTL1DIS_S 0 +#define FLASH_FBPROT_PROTL1DIS 0x00000001 +#define FLASH_FBPROT_PROTL1DIS_BITN 0 +#define FLASH_FBPROT_PROTL1DIS_M 0x00000001 +#define FLASH_FBPROT_PROTL1DIS_S 0 //***************************************************************************** // @@ -1293,9 +1293,9 @@ // Field: [15:0] BSE // // Internal. Only to be used through TI provided API. -#define FLASH_FBSE_BSE_W 16 -#define FLASH_FBSE_BSE_M 0x0000FFFF -#define FLASH_FBSE_BSE_S 0 +#define FLASH_FBSE_BSE_W 16 +#define FLASH_FBSE_BSE_M 0x0000FFFF +#define FLASH_FBSE_BSE_S 0 //***************************************************************************** // @@ -1305,9 +1305,9 @@ // Field: [7:0] BUSY // // Internal. Only to be used through TI provided API. -#define FLASH_FBBUSY_BUSY_W 8 -#define FLASH_FBBUSY_BUSY_M 0x000000FF -#define FLASH_FBBUSY_BUSY_S 0 +#define FLASH_FBBUSY_BUSY_W 8 +#define FLASH_FBBUSY_BUSY_M 0x000000FF +#define FLASH_FBBUSY_BUSY_S 0 //***************************************************************************** // @@ -1317,24 +1317,24 @@ // Field: [16] OTPPROTDIS // // Internal. Only to be used through TI provided API. -#define FLASH_FBAC_OTPPROTDIS 0x00010000 -#define FLASH_FBAC_OTPPROTDIS_BITN 16 -#define FLASH_FBAC_OTPPROTDIS_M 0x00010000 -#define FLASH_FBAC_OTPPROTDIS_S 16 +#define FLASH_FBAC_OTPPROTDIS 0x00010000 +#define FLASH_FBAC_OTPPROTDIS_BITN 16 +#define FLASH_FBAC_OTPPROTDIS_M 0x00010000 +#define FLASH_FBAC_OTPPROTDIS_S 16 // Field: [15:8] BAGP // // Internal. Only to be used through TI provided API. -#define FLASH_FBAC_BAGP_W 8 -#define FLASH_FBAC_BAGP_M 0x0000FF00 -#define FLASH_FBAC_BAGP_S 8 +#define FLASH_FBAC_BAGP_W 8 +#define FLASH_FBAC_BAGP_M 0x0000FF00 +#define FLASH_FBAC_BAGP_S 8 // Field: [7:0] VREADS // // Internal. Only to be used through TI provided API. -#define FLASH_FBAC_VREADS_W 8 -#define FLASH_FBAC_VREADS_M 0x000000FF -#define FLASH_FBAC_VREADS_S 0 +#define FLASH_FBAC_VREADS_W 8 +#define FLASH_FBAC_VREADS_M 0x000000FF +#define FLASH_FBAC_VREADS_S 0 //***************************************************************************** // @@ -1344,72 +1344,72 @@ // Field: [27:24] FSM_PWRSAV // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_FSM_PWRSAV_W 4 -#define FLASH_FBFALLBACK_FSM_PWRSAV_M 0x0F000000 -#define FLASH_FBFALLBACK_FSM_PWRSAV_S 24 +#define FLASH_FBFALLBACK_FSM_PWRSAV_W 4 +#define FLASH_FBFALLBACK_FSM_PWRSAV_M 0x0F000000 +#define FLASH_FBFALLBACK_FSM_PWRSAV_S 24 // Field: [19:16] REG_PWRSAV // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_REG_PWRSAV_W 4 -#define FLASH_FBFALLBACK_REG_PWRSAV_M 0x000F0000 -#define FLASH_FBFALLBACK_REG_PWRSAV_S 16 +#define FLASH_FBFALLBACK_REG_PWRSAV_W 4 +#define FLASH_FBFALLBACK_REG_PWRSAV_M 0x000F0000 +#define FLASH_FBFALLBACK_REG_PWRSAV_S 16 // Field: [15:14] BANKPWR7 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR7_W 2 -#define FLASH_FBFALLBACK_BANKPWR7_M 0x0000C000 -#define FLASH_FBFALLBACK_BANKPWR7_S 14 +#define FLASH_FBFALLBACK_BANKPWR7_W 2 +#define FLASH_FBFALLBACK_BANKPWR7_M 0x0000C000 +#define FLASH_FBFALLBACK_BANKPWR7_S 14 // Field: [13:12] BANKPWR6 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR6_W 2 -#define FLASH_FBFALLBACK_BANKPWR6_M 0x00003000 -#define FLASH_FBFALLBACK_BANKPWR6_S 12 +#define FLASH_FBFALLBACK_BANKPWR6_W 2 +#define FLASH_FBFALLBACK_BANKPWR6_M 0x00003000 +#define FLASH_FBFALLBACK_BANKPWR6_S 12 // Field: [11:10] BANKPWR5 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR5_W 2 -#define FLASH_FBFALLBACK_BANKPWR5_M 0x00000C00 -#define FLASH_FBFALLBACK_BANKPWR5_S 10 +#define FLASH_FBFALLBACK_BANKPWR5_W 2 +#define FLASH_FBFALLBACK_BANKPWR5_M 0x00000C00 +#define FLASH_FBFALLBACK_BANKPWR5_S 10 // Field: [9:8] BANKPWR4 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR4_W 2 -#define FLASH_FBFALLBACK_BANKPWR4_M 0x00000300 -#define FLASH_FBFALLBACK_BANKPWR4_S 8 +#define FLASH_FBFALLBACK_BANKPWR4_W 2 +#define FLASH_FBFALLBACK_BANKPWR4_M 0x00000300 +#define FLASH_FBFALLBACK_BANKPWR4_S 8 // Field: [7:6] BANKPWR3 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR3_W 2 -#define FLASH_FBFALLBACK_BANKPWR3_M 0x000000C0 -#define FLASH_FBFALLBACK_BANKPWR3_S 6 +#define FLASH_FBFALLBACK_BANKPWR3_W 2 +#define FLASH_FBFALLBACK_BANKPWR3_M 0x000000C0 +#define FLASH_FBFALLBACK_BANKPWR3_S 6 // Field: [5:4] BANKPWR2 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR2_W 2 -#define FLASH_FBFALLBACK_BANKPWR2_M 0x00000030 -#define FLASH_FBFALLBACK_BANKPWR2_S 4 +#define FLASH_FBFALLBACK_BANKPWR2_W 2 +#define FLASH_FBFALLBACK_BANKPWR2_M 0x00000030 +#define FLASH_FBFALLBACK_BANKPWR2_S 4 // Field: [3:2] BANKPWR1 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR1_W 2 -#define FLASH_FBFALLBACK_BANKPWR1_M 0x0000000C -#define FLASH_FBFALLBACK_BANKPWR1_S 2 +#define FLASH_FBFALLBACK_BANKPWR1_W 2 +#define FLASH_FBFALLBACK_BANKPWR1_M 0x0000000C +#define FLASH_FBFALLBACK_BANKPWR1_S 2 // Field: [1:0] BANKPWR0 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR0_W 2 -#define FLASH_FBFALLBACK_BANKPWR0_M 0x00000003 -#define FLASH_FBFALLBACK_BANKPWR0_S 0 +#define FLASH_FBFALLBACK_BANKPWR0_W 2 +#define FLASH_FBFALLBACK_BANKPWR0_M 0x00000003 +#define FLASH_FBFALLBACK_BANKPWR0_S 0 //***************************************************************************** // @@ -1419,26 +1419,26 @@ // Field: [16] BANKBUSY // // Internal. Only to be used through TI provided API. -#define FLASH_FBPRDY_BANKBUSY 0x00010000 -#define FLASH_FBPRDY_BANKBUSY_BITN 16 -#define FLASH_FBPRDY_BANKBUSY_M 0x00010000 -#define FLASH_FBPRDY_BANKBUSY_S 16 +#define FLASH_FBPRDY_BANKBUSY 0x00010000 +#define FLASH_FBPRDY_BANKBUSY_BITN 16 +#define FLASH_FBPRDY_BANKBUSY_M 0x00010000 +#define FLASH_FBPRDY_BANKBUSY_S 16 // Field: [15] PUMPRDY // // Internal. Only to be used through TI provided API. -#define FLASH_FBPRDY_PUMPRDY 0x00008000 -#define FLASH_FBPRDY_PUMPRDY_BITN 15 -#define FLASH_FBPRDY_PUMPRDY_M 0x00008000 -#define FLASH_FBPRDY_PUMPRDY_S 15 +#define FLASH_FBPRDY_PUMPRDY 0x00008000 +#define FLASH_FBPRDY_PUMPRDY_BITN 15 +#define FLASH_FBPRDY_PUMPRDY_M 0x00008000 +#define FLASH_FBPRDY_PUMPRDY_S 15 // Field: [0] BANKRDY // // Internal. Only to be used through TI provided API. -#define FLASH_FBPRDY_BANKRDY 0x00000001 -#define FLASH_FBPRDY_BANKRDY_BITN 0 -#define FLASH_FBPRDY_BANKRDY_M 0x00000001 -#define FLASH_FBPRDY_BANKRDY_S 0 +#define FLASH_FBPRDY_BANKRDY 0x00000001 +#define FLASH_FBPRDY_BANKRDY_BITN 0 +#define FLASH_FBPRDY_BANKRDY_M 0x00000001 +#define FLASH_FBPRDY_BANKRDY_S 0 //***************************************************************************** // @@ -1448,23 +1448,23 @@ // Field: [27:16] PSLEEPTDIS // // Internal. Only to be used through TI provided API. -#define FLASH_FPAC1_PSLEEPTDIS_W 12 -#define FLASH_FPAC1_PSLEEPTDIS_M 0x0FFF0000 -#define FLASH_FPAC1_PSLEEPTDIS_S 16 +#define FLASH_FPAC1_PSLEEPTDIS_W 12 +#define FLASH_FPAC1_PSLEEPTDIS_M 0x0FFF0000 +#define FLASH_FPAC1_PSLEEPTDIS_S 16 // Field: [15:4] PUMPRESET_PW // // Internal. Only to be used through TI provided API. -#define FLASH_FPAC1_PUMPRESET_PW_W 12 -#define FLASH_FPAC1_PUMPRESET_PW_M 0x0000FFF0 -#define FLASH_FPAC1_PUMPRESET_PW_S 4 +#define FLASH_FPAC1_PUMPRESET_PW_W 12 +#define FLASH_FPAC1_PUMPRESET_PW_M 0x0000FFF0 +#define FLASH_FPAC1_PUMPRESET_PW_S 4 // Field: [1:0] PUMPPWR // // Internal. Only to be used through TI provided API. -#define FLASH_FPAC1_PUMPPWR_W 2 -#define FLASH_FPAC1_PUMPPWR_M 0x00000003 -#define FLASH_FPAC1_PUMPPWR_S 0 +#define FLASH_FPAC1_PUMPPWR_W 2 +#define FLASH_FPAC1_PUMPPWR_M 0x00000003 +#define FLASH_FPAC1_PUMPPWR_S 0 //***************************************************************************** // @@ -1474,9 +1474,9 @@ // Field: [15:0] PAGP // // Internal. Only to be used through TI provided API. -#define FLASH_FPAC2_PAGP_W 16 -#define FLASH_FPAC2_PAGP_M 0x0000FFFF -#define FLASH_FPAC2_PAGP_S 0 +#define FLASH_FPAC2_PAGP_W 16 +#define FLASH_FPAC2_PAGP_M 0x0000FFFF +#define FLASH_FPAC2_PAGP_S 0 //***************************************************************************** // @@ -1486,9 +1486,9 @@ // Field: [2:0] BANK // // Internal. Only to be used through TI provided API. -#define FLASH_FMAC_BANK_W 3 -#define FLASH_FMAC_BANK_M 0x00000007 -#define FLASH_FMAC_BANK_S 0 +#define FLASH_FMAC_BANK_W 3 +#define FLASH_FMAC_BANK_M 0x00000007 +#define FLASH_FMAC_BANK_S 0 //***************************************************************************** // @@ -1498,146 +1498,146 @@ // Field: [17] RVSUSP // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_RVSUSP 0x00020000 -#define FLASH_FMSTAT_RVSUSP_BITN 17 -#define FLASH_FMSTAT_RVSUSP_M 0x00020000 -#define FLASH_FMSTAT_RVSUSP_S 17 +#define FLASH_FMSTAT_RVSUSP 0x00020000 +#define FLASH_FMSTAT_RVSUSP_BITN 17 +#define FLASH_FMSTAT_RVSUSP_M 0x00020000 +#define FLASH_FMSTAT_RVSUSP_S 17 // Field: [16] RDVER // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_RDVER 0x00010000 -#define FLASH_FMSTAT_RDVER_BITN 16 -#define FLASH_FMSTAT_RDVER_M 0x00010000 -#define FLASH_FMSTAT_RDVER_S 16 +#define FLASH_FMSTAT_RDVER 0x00010000 +#define FLASH_FMSTAT_RDVER_BITN 16 +#define FLASH_FMSTAT_RDVER_M 0x00010000 +#define FLASH_FMSTAT_RDVER_S 16 // Field: [15] RVF // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_RVF 0x00008000 -#define FLASH_FMSTAT_RVF_BITN 15 -#define FLASH_FMSTAT_RVF_M 0x00008000 -#define FLASH_FMSTAT_RVF_S 15 +#define FLASH_FMSTAT_RVF 0x00008000 +#define FLASH_FMSTAT_RVF_BITN 15 +#define FLASH_FMSTAT_RVF_M 0x00008000 +#define FLASH_FMSTAT_RVF_S 15 // Field: [14] ILA // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_ILA 0x00004000 -#define FLASH_FMSTAT_ILA_BITN 14 -#define FLASH_FMSTAT_ILA_M 0x00004000 -#define FLASH_FMSTAT_ILA_S 14 +#define FLASH_FMSTAT_ILA 0x00004000 +#define FLASH_FMSTAT_ILA_BITN 14 +#define FLASH_FMSTAT_ILA_M 0x00004000 +#define FLASH_FMSTAT_ILA_S 14 // Field: [13] DBF // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_DBF 0x00002000 -#define FLASH_FMSTAT_DBF_BITN 13 -#define FLASH_FMSTAT_DBF_M 0x00002000 -#define FLASH_FMSTAT_DBF_S 13 +#define FLASH_FMSTAT_DBF 0x00002000 +#define FLASH_FMSTAT_DBF_BITN 13 +#define FLASH_FMSTAT_DBF_M 0x00002000 +#define FLASH_FMSTAT_DBF_S 13 // Field: [12] PGV // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_PGV 0x00001000 -#define FLASH_FMSTAT_PGV_BITN 12 -#define FLASH_FMSTAT_PGV_M 0x00001000 -#define FLASH_FMSTAT_PGV_S 12 +#define FLASH_FMSTAT_PGV 0x00001000 +#define FLASH_FMSTAT_PGV_BITN 12 +#define FLASH_FMSTAT_PGV_M 0x00001000 +#define FLASH_FMSTAT_PGV_S 12 // Field: [11] PCV // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_PCV 0x00000800 -#define FLASH_FMSTAT_PCV_BITN 11 -#define FLASH_FMSTAT_PCV_M 0x00000800 -#define FLASH_FMSTAT_PCV_S 11 +#define FLASH_FMSTAT_PCV 0x00000800 +#define FLASH_FMSTAT_PCV_BITN 11 +#define FLASH_FMSTAT_PCV_M 0x00000800 +#define FLASH_FMSTAT_PCV_S 11 // Field: [10] EV // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_EV 0x00000400 -#define FLASH_FMSTAT_EV_BITN 10 -#define FLASH_FMSTAT_EV_M 0x00000400 -#define FLASH_FMSTAT_EV_S 10 +#define FLASH_FMSTAT_EV 0x00000400 +#define FLASH_FMSTAT_EV_BITN 10 +#define FLASH_FMSTAT_EV_M 0x00000400 +#define FLASH_FMSTAT_EV_S 10 // Field: [9] CV // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_CV 0x00000200 -#define FLASH_FMSTAT_CV_BITN 9 -#define FLASH_FMSTAT_CV_M 0x00000200 -#define FLASH_FMSTAT_CV_S 9 +#define FLASH_FMSTAT_CV 0x00000200 +#define FLASH_FMSTAT_CV_BITN 9 +#define FLASH_FMSTAT_CV_M 0x00000200 +#define FLASH_FMSTAT_CV_S 9 // Field: [8] BUSY // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_BUSY 0x00000100 -#define FLASH_FMSTAT_BUSY_BITN 8 -#define FLASH_FMSTAT_BUSY_M 0x00000100 -#define FLASH_FMSTAT_BUSY_S 8 +#define FLASH_FMSTAT_BUSY 0x00000100 +#define FLASH_FMSTAT_BUSY_BITN 8 +#define FLASH_FMSTAT_BUSY_M 0x00000100 +#define FLASH_FMSTAT_BUSY_S 8 // Field: [7] ERS // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_ERS 0x00000080 -#define FLASH_FMSTAT_ERS_BITN 7 -#define FLASH_FMSTAT_ERS_M 0x00000080 -#define FLASH_FMSTAT_ERS_S 7 +#define FLASH_FMSTAT_ERS 0x00000080 +#define FLASH_FMSTAT_ERS_BITN 7 +#define FLASH_FMSTAT_ERS_M 0x00000080 +#define FLASH_FMSTAT_ERS_S 7 // Field: [6] PGM // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_PGM 0x00000040 -#define FLASH_FMSTAT_PGM_BITN 6 -#define FLASH_FMSTAT_PGM_M 0x00000040 -#define FLASH_FMSTAT_PGM_S 6 +#define FLASH_FMSTAT_PGM 0x00000040 +#define FLASH_FMSTAT_PGM_BITN 6 +#define FLASH_FMSTAT_PGM_M 0x00000040 +#define FLASH_FMSTAT_PGM_S 6 // Field: [5] INVDAT // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_INVDAT 0x00000020 -#define FLASH_FMSTAT_INVDAT_BITN 5 -#define FLASH_FMSTAT_INVDAT_M 0x00000020 -#define FLASH_FMSTAT_INVDAT_S 5 +#define FLASH_FMSTAT_INVDAT 0x00000020 +#define FLASH_FMSTAT_INVDAT_BITN 5 +#define FLASH_FMSTAT_INVDAT_M 0x00000020 +#define FLASH_FMSTAT_INVDAT_S 5 // Field: [4] CSTAT // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_CSTAT 0x00000010 -#define FLASH_FMSTAT_CSTAT_BITN 4 -#define FLASH_FMSTAT_CSTAT_M 0x00000010 -#define FLASH_FMSTAT_CSTAT_S 4 +#define FLASH_FMSTAT_CSTAT 0x00000010 +#define FLASH_FMSTAT_CSTAT_BITN 4 +#define FLASH_FMSTAT_CSTAT_M 0x00000010 +#define FLASH_FMSTAT_CSTAT_S 4 // Field: [3] VOLSTAT // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_VOLSTAT 0x00000008 -#define FLASH_FMSTAT_VOLSTAT_BITN 3 -#define FLASH_FMSTAT_VOLSTAT_M 0x00000008 -#define FLASH_FMSTAT_VOLSTAT_S 3 +#define FLASH_FMSTAT_VOLSTAT 0x00000008 +#define FLASH_FMSTAT_VOLSTAT_BITN 3 +#define FLASH_FMSTAT_VOLSTAT_M 0x00000008 +#define FLASH_FMSTAT_VOLSTAT_S 3 // Field: [2] ESUSP // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_ESUSP 0x00000004 -#define FLASH_FMSTAT_ESUSP_BITN 2 -#define FLASH_FMSTAT_ESUSP_M 0x00000004 -#define FLASH_FMSTAT_ESUSP_S 2 +#define FLASH_FMSTAT_ESUSP 0x00000004 +#define FLASH_FMSTAT_ESUSP_BITN 2 +#define FLASH_FMSTAT_ESUSP_M 0x00000004 +#define FLASH_FMSTAT_ESUSP_S 2 // Field: [1] PSUSP // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_PSUSP 0x00000002 -#define FLASH_FMSTAT_PSUSP_BITN 1 -#define FLASH_FMSTAT_PSUSP_M 0x00000002 -#define FLASH_FMSTAT_PSUSP_S 1 +#define FLASH_FMSTAT_PSUSP 0x00000002 +#define FLASH_FMSTAT_PSUSP_BITN 1 +#define FLASH_FMSTAT_PSUSP_M 0x00000002 +#define FLASH_FMSTAT_PSUSP_S 1 // Field: [0] SLOCK // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_SLOCK 0x00000001 -#define FLASH_FMSTAT_SLOCK_BITN 0 -#define FLASH_FMSTAT_SLOCK_M 0x00000001 -#define FLASH_FMSTAT_SLOCK_S 0 +#define FLASH_FMSTAT_SLOCK 0x00000001 +#define FLASH_FMSTAT_SLOCK_BITN 0 +#define FLASH_FMSTAT_SLOCK_M 0x00000001 +#define FLASH_FMSTAT_SLOCK_S 0 //***************************************************************************** // @@ -1647,9 +1647,9 @@ // Field: [15:0] ENCOM // // Internal. Only to be used through TI provided API. -#define FLASH_FLOCK_ENCOM_W 16 -#define FLASH_FLOCK_ENCOM_M 0x0000FFFF -#define FLASH_FLOCK_ENCOM_S 0 +#define FLASH_FLOCK_ENCOM_W 16 +#define FLASH_FLOCK_ENCOM_M 0x0000FFFF +#define FLASH_FLOCK_ENCOM_S 0 //***************************************************************************** // @@ -1659,9 +1659,9 @@ // Field: [3:0] VREADCT // // Internal. Only to be used through TI provided API. -#define FLASH_FVREADCT_VREADCT_W 4 -#define FLASH_FVREADCT_VREADCT_M 0x0000000F -#define FLASH_FVREADCT_VREADCT_S 0 +#define FLASH_FVREADCT_VREADCT_W 4 +#define FLASH_FVREADCT_VREADCT_M 0x0000000F +#define FLASH_FVREADCT_VREADCT_S 0 //***************************************************************************** // @@ -1671,30 +1671,30 @@ // Field: [23:20] TRIM13_E // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT1_TRIM13_E_W 4 -#define FLASH_FVHVCT1_TRIM13_E_M 0x00F00000 -#define FLASH_FVHVCT1_TRIM13_E_S 20 +#define FLASH_FVHVCT1_TRIM13_E_W 4 +#define FLASH_FVHVCT1_TRIM13_E_M 0x00F00000 +#define FLASH_FVHVCT1_TRIM13_E_S 20 // Field: [19:16] VHVCT_E // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT1_VHVCT_E_W 4 -#define FLASH_FVHVCT1_VHVCT_E_M 0x000F0000 -#define FLASH_FVHVCT1_VHVCT_E_S 16 +#define FLASH_FVHVCT1_VHVCT_E_W 4 +#define FLASH_FVHVCT1_VHVCT_E_M 0x000F0000 +#define FLASH_FVHVCT1_VHVCT_E_S 16 // Field: [7:4] TRIM13_PV // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT1_TRIM13_PV_W 4 -#define FLASH_FVHVCT1_TRIM13_PV_M 0x000000F0 -#define FLASH_FVHVCT1_TRIM13_PV_S 4 +#define FLASH_FVHVCT1_TRIM13_PV_W 4 +#define FLASH_FVHVCT1_TRIM13_PV_M 0x000000F0 +#define FLASH_FVHVCT1_TRIM13_PV_S 4 // Field: [3:0] VHVCT_PV // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT1_VHVCT_PV_W 4 -#define FLASH_FVHVCT1_VHVCT_PV_M 0x0000000F -#define FLASH_FVHVCT1_VHVCT_PV_S 0 +#define FLASH_FVHVCT1_VHVCT_PV_W 4 +#define FLASH_FVHVCT1_VHVCT_PV_M 0x0000000F +#define FLASH_FVHVCT1_VHVCT_PV_S 0 //***************************************************************************** // @@ -1704,16 +1704,16 @@ // Field: [23:20] TRIM13_P // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT2_TRIM13_P_W 4 -#define FLASH_FVHVCT2_TRIM13_P_M 0x00F00000 -#define FLASH_FVHVCT2_TRIM13_P_S 20 +#define FLASH_FVHVCT2_TRIM13_P_W 4 +#define FLASH_FVHVCT2_TRIM13_P_M 0x00F00000 +#define FLASH_FVHVCT2_TRIM13_P_S 20 // Field: [19:16] VHVCT_P // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT2_VHVCT_P_W 4 -#define FLASH_FVHVCT2_VHVCT_P_M 0x000F0000 -#define FLASH_FVHVCT2_VHVCT_P_S 16 +#define FLASH_FVHVCT2_VHVCT_P_W 4 +#define FLASH_FVHVCT2_VHVCT_P_M 0x000F0000 +#define FLASH_FVHVCT2_VHVCT_P_S 16 //***************************************************************************** // @@ -1723,16 +1723,16 @@ // Field: [19:16] WCT // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT3_WCT_W 4 -#define FLASH_FVHVCT3_WCT_M 0x000F0000 -#define FLASH_FVHVCT3_WCT_S 16 +#define FLASH_FVHVCT3_WCT_W 4 +#define FLASH_FVHVCT3_WCT_M 0x000F0000 +#define FLASH_FVHVCT3_WCT_S 16 // Field: [3:0] VHVCT_READ // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT3_VHVCT_READ_W 4 -#define FLASH_FVHVCT3_VHVCT_READ_M 0x0000000F -#define FLASH_FVHVCT3_VHVCT_READ_S 0 +#define FLASH_FVHVCT3_VHVCT_READ_W 4 +#define FLASH_FVHVCT3_VHVCT_READ_M 0x0000000F +#define FLASH_FVHVCT3_VHVCT_READ_S 0 //***************************************************************************** // @@ -1742,16 +1742,16 @@ // Field: [12:8] VCG2P5CT // // Internal. Only to be used through TI provided API. -#define FLASH_FVNVCT_VCG2P5CT_W 5 -#define FLASH_FVNVCT_VCG2P5CT_M 0x00001F00 -#define FLASH_FVNVCT_VCG2P5CT_S 8 +#define FLASH_FVNVCT_VCG2P5CT_W 5 +#define FLASH_FVNVCT_VCG2P5CT_M 0x00001F00 +#define FLASH_FVNVCT_VCG2P5CT_S 8 // Field: [4:0] VIN_CT // // Internal. Only to be used through TI provided API. -#define FLASH_FVNVCT_VIN_CT_W 5 -#define FLASH_FVNVCT_VIN_CT_M 0x0000001F -#define FLASH_FVNVCT_VIN_CT_S 0 +#define FLASH_FVNVCT_VIN_CT_W 5 +#define FLASH_FVNVCT_VIN_CT_M 0x0000001F +#define FLASH_FVNVCT_VIN_CT_S 0 //***************************************************************************** // @@ -1761,9 +1761,9 @@ // Field: [15:12] VSL_P // // Internal. Only to be used through TI provided API. -#define FLASH_FVSLP_VSL_P_W 4 -#define FLASH_FVSLP_VSL_P_M 0x0000F000 -#define FLASH_FVSLP_VSL_P_S 12 +#define FLASH_FVSLP_VSL_P_W 4 +#define FLASH_FVSLP_VSL_P_M 0x0000F000 +#define FLASH_FVSLP_VSL_P_S 12 //***************************************************************************** // @@ -1773,9 +1773,9 @@ // Field: [4:0] VWLCT_P // // Internal. Only to be used through TI provided API. -#define FLASH_FVWLCT_VWLCT_P_W 5 -#define FLASH_FVWLCT_VWLCT_P_M 0x0000001F -#define FLASH_FVWLCT_VWLCT_P_S 0 +#define FLASH_FVWLCT_VWLCT_P_W 5 +#define FLASH_FVWLCT_VWLCT_P_M 0x0000001F +#define FLASH_FVWLCT_VWLCT_P_S 0 //***************************************************************************** // @@ -1785,48 +1785,48 @@ // Field: [26:24] CHAIN_SEL // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_CHAIN_SEL_W 3 -#define FLASH_FEFUSECTL_CHAIN_SEL_M 0x07000000 -#define FLASH_FEFUSECTL_CHAIN_SEL_S 24 +#define FLASH_FEFUSECTL_CHAIN_SEL_W 3 +#define FLASH_FEFUSECTL_CHAIN_SEL_M 0x07000000 +#define FLASH_FEFUSECTL_CHAIN_SEL_S 24 // Field: [17] WRITE_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_WRITE_EN 0x00020000 -#define FLASH_FEFUSECTL_WRITE_EN_BITN 17 -#define FLASH_FEFUSECTL_WRITE_EN_M 0x00020000 -#define FLASH_FEFUSECTL_WRITE_EN_S 17 +#define FLASH_FEFUSECTL_WRITE_EN 0x00020000 +#define FLASH_FEFUSECTL_WRITE_EN_BITN 17 +#define FLASH_FEFUSECTL_WRITE_EN_M 0x00020000 +#define FLASH_FEFUSECTL_WRITE_EN_S 17 // Field: [16] BP_SEL // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_BP_SEL 0x00010000 -#define FLASH_FEFUSECTL_BP_SEL_BITN 16 -#define FLASH_FEFUSECTL_BP_SEL_M 0x00010000 -#define FLASH_FEFUSECTL_BP_SEL_S 16 +#define FLASH_FEFUSECTL_BP_SEL 0x00010000 +#define FLASH_FEFUSECTL_BP_SEL_BITN 16 +#define FLASH_FEFUSECTL_BP_SEL_M 0x00010000 +#define FLASH_FEFUSECTL_BP_SEL_S 16 // Field: [8] EF_CLRZ // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_EF_CLRZ 0x00000100 -#define FLASH_FEFUSECTL_EF_CLRZ_BITN 8 -#define FLASH_FEFUSECTL_EF_CLRZ_M 0x00000100 -#define FLASH_FEFUSECTL_EF_CLRZ_S 8 +#define FLASH_FEFUSECTL_EF_CLRZ 0x00000100 +#define FLASH_FEFUSECTL_EF_CLRZ_BITN 8 +#define FLASH_FEFUSECTL_EF_CLRZ_M 0x00000100 +#define FLASH_FEFUSECTL_EF_CLRZ_S 8 // Field: [4] EF_TEST // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_EF_TEST 0x00000010 -#define FLASH_FEFUSECTL_EF_TEST_BITN 4 -#define FLASH_FEFUSECTL_EF_TEST_M 0x00000010 -#define FLASH_FEFUSECTL_EF_TEST_S 4 +#define FLASH_FEFUSECTL_EF_TEST 0x00000010 +#define FLASH_FEFUSECTL_EF_TEST_BITN 4 +#define FLASH_FEFUSECTL_EF_TEST_M 0x00000010 +#define FLASH_FEFUSECTL_EF_TEST_S 4 // Field: [3:0] EFUSE_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_EFUSE_EN_W 4 -#define FLASH_FEFUSECTL_EFUSE_EN_M 0x0000000F -#define FLASH_FEFUSECTL_EFUSE_EN_S 0 +#define FLASH_FEFUSECTL_EFUSE_EN_W 4 +#define FLASH_FEFUSECTL_EFUSE_EN_M 0x0000000F +#define FLASH_FEFUSECTL_EFUSE_EN_S 0 //***************************************************************************** // @@ -1836,10 +1836,10 @@ // Field: [0] SHIFT_DONE // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSESTAT_SHIFT_DONE 0x00000001 -#define FLASH_FEFUSESTAT_SHIFT_DONE_BITN 0 -#define FLASH_FEFUSESTAT_SHIFT_DONE_M 0x00000001 -#define FLASH_FEFUSESTAT_SHIFT_DONE_S 0 +#define FLASH_FEFUSESTAT_SHIFT_DONE 0x00000001 +#define FLASH_FEFUSESTAT_SHIFT_DONE_BITN 0 +#define FLASH_FEFUSESTAT_SHIFT_DONE_M 0x00000001 +#define FLASH_FEFUSESTAT_SHIFT_DONE_S 0 //***************************************************************************** // @@ -1849,9 +1849,9 @@ // Field: [31:0] FEFUSEDATA // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSEDATA_FEFUSEDATA_W 32 -#define FLASH_FEFUSEDATA_FEFUSEDATA_M 0xFFFFFFFF -#define FLASH_FEFUSEDATA_FEFUSEDATA_S 0 +#define FLASH_FEFUSEDATA_FEFUSEDATA_W 32 +#define FLASH_FEFUSEDATA_FEFUSEDATA_M 0xFFFFFFFF +#define FLASH_FEFUSEDATA_FEFUSEDATA_S 0 //***************************************************************************** // @@ -1861,38 +1861,38 @@ // Field: [27:24] TRIM_3P4 // // Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_TRIM_3P4_W 4 -#define FLASH_FSEQPMP_TRIM_3P4_M 0x0F000000 -#define FLASH_FSEQPMP_TRIM_3P4_S 24 +#define FLASH_FSEQPMP_TRIM_3P4_W 4 +#define FLASH_FSEQPMP_TRIM_3P4_M 0x0F000000 +#define FLASH_FSEQPMP_TRIM_3P4_S 24 // Field: [21:20] TRIM_1P7 // // Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_TRIM_1P7_W 2 -#define FLASH_FSEQPMP_TRIM_1P7_M 0x00300000 -#define FLASH_FSEQPMP_TRIM_1P7_S 20 +#define FLASH_FSEQPMP_TRIM_1P7_W 2 +#define FLASH_FSEQPMP_TRIM_1P7_M 0x00300000 +#define FLASH_FSEQPMP_TRIM_1P7_S 20 // Field: [19:16] TRIM_0P8 // // Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_TRIM_0P8_W 4 -#define FLASH_FSEQPMP_TRIM_0P8_M 0x000F0000 -#define FLASH_FSEQPMP_TRIM_0P8_S 16 +#define FLASH_FSEQPMP_TRIM_0P8_W 4 +#define FLASH_FSEQPMP_TRIM_0P8_M 0x000F0000 +#define FLASH_FSEQPMP_TRIM_0P8_S 16 // Field: [14:12] VIN_AT_X // // Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_VIN_AT_X_W 3 -#define FLASH_FSEQPMP_VIN_AT_X_M 0x00007000 -#define FLASH_FSEQPMP_VIN_AT_X_S 12 +#define FLASH_FSEQPMP_VIN_AT_X_W 3 +#define FLASH_FSEQPMP_VIN_AT_X_M 0x00007000 +#define FLASH_FSEQPMP_VIN_AT_X_S 12 // Field: [8] VIN_BY_PASS // // Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_VIN_BY_PASS 0x00000100 -#define FLASH_FSEQPMP_VIN_BY_PASS_BITN 8 -#define FLASH_FSEQPMP_VIN_BY_PASS_M 0x00000100 -#define FLASH_FSEQPMP_VIN_BY_PASS_S 8 +#define FLASH_FSEQPMP_VIN_BY_PASS 0x00000100 +#define FLASH_FSEQPMP_VIN_BY_PASS_BITN 8 +#define FLASH_FSEQPMP_VIN_BY_PASS_M 0x00000100 +#define FLASH_FSEQPMP_VIN_BY_PASS_S 8 //***************************************************************************** // @@ -1902,82 +1902,82 @@ // Field: [24] ECBIT // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_ECBIT 0x01000000 -#define FLASH_FBSTROBES_ECBIT_BITN 24 -#define FLASH_FBSTROBES_ECBIT_M 0x01000000 -#define FLASH_FBSTROBES_ECBIT_S 24 +#define FLASH_FBSTROBES_ECBIT 0x01000000 +#define FLASH_FBSTROBES_ECBIT_BITN 24 +#define FLASH_FBSTROBES_ECBIT_M 0x01000000 +#define FLASH_FBSTROBES_ECBIT_S 24 // Field: [18] RWAIT2_FLCLK // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_RWAIT2_FLCLK 0x00040000 -#define FLASH_FBSTROBES_RWAIT2_FLCLK_BITN 18 -#define FLASH_FBSTROBES_RWAIT2_FLCLK_M 0x00040000 -#define FLASH_FBSTROBES_RWAIT2_FLCLK_S 18 +#define FLASH_FBSTROBES_RWAIT2_FLCLK 0x00040000 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_BITN 18 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_M 0x00040000 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_S 18 // Field: [17] RWAIT_FLCLK // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_RWAIT_FLCLK 0x00020000 -#define FLASH_FBSTROBES_RWAIT_FLCLK_BITN 17 -#define FLASH_FBSTROBES_RWAIT_FLCLK_M 0x00020000 -#define FLASH_FBSTROBES_RWAIT_FLCLK_S 17 +#define FLASH_FBSTROBES_RWAIT_FLCLK 0x00020000 +#define FLASH_FBSTROBES_RWAIT_FLCLK_BITN 17 +#define FLASH_FBSTROBES_RWAIT_FLCLK_M 0x00020000 +#define FLASH_FBSTROBES_RWAIT_FLCLK_S 17 // Field: [16] FLCLKEN // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_FLCLKEN 0x00010000 -#define FLASH_FBSTROBES_FLCLKEN_BITN 16 -#define FLASH_FBSTROBES_FLCLKEN_M 0x00010000 -#define FLASH_FBSTROBES_FLCLKEN_S 16 +#define FLASH_FBSTROBES_FLCLKEN 0x00010000 +#define FLASH_FBSTROBES_FLCLKEN_BITN 16 +#define FLASH_FBSTROBES_FLCLKEN_M 0x00010000 +#define FLASH_FBSTROBES_FLCLKEN_S 16 // Field: [8] CTRLENZ // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_CTRLENZ 0x00000100 -#define FLASH_FBSTROBES_CTRLENZ_BITN 8 -#define FLASH_FBSTROBES_CTRLENZ_M 0x00000100 -#define FLASH_FBSTROBES_CTRLENZ_S 8 +#define FLASH_FBSTROBES_CTRLENZ 0x00000100 +#define FLASH_FBSTROBES_CTRLENZ_BITN 8 +#define FLASH_FBSTROBES_CTRLENZ_M 0x00000100 +#define FLASH_FBSTROBES_CTRLENZ_S 8 // Field: [6] NOCOLRED // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_NOCOLRED 0x00000040 -#define FLASH_FBSTROBES_NOCOLRED_BITN 6 -#define FLASH_FBSTROBES_NOCOLRED_M 0x00000040 -#define FLASH_FBSTROBES_NOCOLRED_S 6 +#define FLASH_FBSTROBES_NOCOLRED 0x00000040 +#define FLASH_FBSTROBES_NOCOLRED_BITN 6 +#define FLASH_FBSTROBES_NOCOLRED_M 0x00000040 +#define FLASH_FBSTROBES_NOCOLRED_S 6 // Field: [5] PRECOL // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_PRECOL 0x00000020 -#define FLASH_FBSTROBES_PRECOL_BITN 5 -#define FLASH_FBSTROBES_PRECOL_M 0x00000020 -#define FLASH_FBSTROBES_PRECOL_S 5 +#define FLASH_FBSTROBES_PRECOL 0x00000020 +#define FLASH_FBSTROBES_PRECOL_BITN 5 +#define FLASH_FBSTROBES_PRECOL_M 0x00000020 +#define FLASH_FBSTROBES_PRECOL_S 5 // Field: [4] TI_OTP // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_TI_OTP 0x00000010 -#define FLASH_FBSTROBES_TI_OTP_BITN 4 -#define FLASH_FBSTROBES_TI_OTP_M 0x00000010 -#define FLASH_FBSTROBES_TI_OTP_S 4 +#define FLASH_FBSTROBES_TI_OTP 0x00000010 +#define FLASH_FBSTROBES_TI_OTP_BITN 4 +#define FLASH_FBSTROBES_TI_OTP_M 0x00000010 +#define FLASH_FBSTROBES_TI_OTP_S 4 // Field: [3] OTP // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_OTP 0x00000008 -#define FLASH_FBSTROBES_OTP_BITN 3 -#define FLASH_FBSTROBES_OTP_M 0x00000008 -#define FLASH_FBSTROBES_OTP_S 3 +#define FLASH_FBSTROBES_OTP 0x00000008 +#define FLASH_FBSTROBES_OTP_BITN 3 +#define FLASH_FBSTROBES_OTP_M 0x00000008 +#define FLASH_FBSTROBES_OTP_S 3 // Field: [2] TEZ // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_TEZ 0x00000004 -#define FLASH_FBSTROBES_TEZ_BITN 2 -#define FLASH_FBSTROBES_TEZ_M 0x00000004 -#define FLASH_FBSTROBES_TEZ_S 2 +#define FLASH_FBSTROBES_TEZ 0x00000004 +#define FLASH_FBSTROBES_TEZ_BITN 2 +#define FLASH_FBSTROBES_TEZ_M 0x00000004 +#define FLASH_FBSTROBES_TEZ_S 2 //***************************************************************************** // @@ -1987,26 +1987,26 @@ // Field: [8] EXECUTEZ // // Internal. Only to be used through TI provided API. -#define FLASH_FPSTROBES_EXECUTEZ 0x00000100 -#define FLASH_FPSTROBES_EXECUTEZ_BITN 8 -#define FLASH_FPSTROBES_EXECUTEZ_M 0x00000100 -#define FLASH_FPSTROBES_EXECUTEZ_S 8 +#define FLASH_FPSTROBES_EXECUTEZ 0x00000100 +#define FLASH_FPSTROBES_EXECUTEZ_BITN 8 +#define FLASH_FPSTROBES_EXECUTEZ_M 0x00000100 +#define FLASH_FPSTROBES_EXECUTEZ_S 8 // Field: [1] V3PWRDNZ // // Internal. Only to be used through TI provided API. -#define FLASH_FPSTROBES_V3PWRDNZ 0x00000002 -#define FLASH_FPSTROBES_V3PWRDNZ_BITN 1 -#define FLASH_FPSTROBES_V3PWRDNZ_M 0x00000002 -#define FLASH_FPSTROBES_V3PWRDNZ_S 1 +#define FLASH_FPSTROBES_V3PWRDNZ 0x00000002 +#define FLASH_FPSTROBES_V3PWRDNZ_BITN 1 +#define FLASH_FPSTROBES_V3PWRDNZ_M 0x00000002 +#define FLASH_FPSTROBES_V3PWRDNZ_S 1 // Field: [0] V5PWRDNZ // // Internal. Only to be used through TI provided API. -#define FLASH_FPSTROBES_V5PWRDNZ 0x00000001 -#define FLASH_FPSTROBES_V5PWRDNZ_BITN 0 -#define FLASH_FPSTROBES_V5PWRDNZ_M 0x00000001 -#define FLASH_FPSTROBES_V5PWRDNZ_S 0 +#define FLASH_FPSTROBES_V5PWRDNZ 0x00000001 +#define FLASH_FPSTROBES_V5PWRDNZ_BITN 0 +#define FLASH_FPSTROBES_V5PWRDNZ_M 0x00000001 +#define FLASH_FPSTROBES_V5PWRDNZ_S 0 //***************************************************************************** // @@ -2016,9 +2016,9 @@ // Field: [2:0] MODE // // Internal. Only to be used through TI provided API. -#define FLASH_FBMODE_MODE_W 3 -#define FLASH_FBMODE_MODE_M 0x00000007 -#define FLASH_FBMODE_MODE_S 0 +#define FLASH_FBMODE_MODE_W 3 +#define FLASH_FBMODE_MODE_M 0x00000007 +#define FLASH_FBMODE_MODE_S 0 //***************************************************************************** // @@ -2028,9 +2028,9 @@ // Field: [6:0] TCR // // Internal. Only to be used through TI provided API. -#define FLASH_FTCR_TCR_W 7 -#define FLASH_FTCR_TCR_M 0x0000007F -#define FLASH_FTCR_TCR_S 0 +#define FLASH_FTCR_TCR_W 7 +#define FLASH_FTCR_TCR_M 0x0000007F +#define FLASH_FTCR_TCR_S 0 //***************************************************************************** // @@ -2040,9 +2040,9 @@ // Field: [31:0] FADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FADDR_FADDR_W 32 -#define FLASH_FADDR_FADDR_M 0xFFFFFFFF -#define FLASH_FADDR_FADDR_S 0 +#define FLASH_FADDR_FADDR_W 32 +#define FLASH_FADDR_FADDR_M 0xFFFFFFFF +#define FLASH_FADDR_FADDR_S 0 //***************************************************************************** // @@ -2052,18 +2052,18 @@ // Field: [16] WDATA_BLK_CLR // // Internal. Only to be used through TI provided API. -#define FLASH_FTCTL_WDATA_BLK_CLR 0x00010000 -#define FLASH_FTCTL_WDATA_BLK_CLR_BITN 16 -#define FLASH_FTCTL_WDATA_BLK_CLR_M 0x00010000 -#define FLASH_FTCTL_WDATA_BLK_CLR_S 16 +#define FLASH_FTCTL_WDATA_BLK_CLR 0x00010000 +#define FLASH_FTCTL_WDATA_BLK_CLR_BITN 16 +#define FLASH_FTCTL_WDATA_BLK_CLR_M 0x00010000 +#define FLASH_FTCTL_WDATA_BLK_CLR_S 16 // Field: [1] TEST_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FTCTL_TEST_EN 0x00000002 -#define FLASH_FTCTL_TEST_EN_BITN 1 -#define FLASH_FTCTL_TEST_EN_M 0x00000002 -#define FLASH_FTCTL_TEST_EN_S 1 +#define FLASH_FTCTL_TEST_EN 0x00000002 +#define FLASH_FTCTL_TEST_EN_BITN 1 +#define FLASH_FTCTL_TEST_EN_M 0x00000002 +#define FLASH_FTCTL_TEST_EN_S 1 //***************************************************************************** // @@ -2073,9 +2073,9 @@ // Field: [31:0] FWPWRITE0 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE0_FWPWRITE0_W 32 -#define FLASH_FWPWRITE0_FWPWRITE0_M 0xFFFFFFFF -#define FLASH_FWPWRITE0_FWPWRITE0_S 0 +#define FLASH_FWPWRITE0_FWPWRITE0_W 32 +#define FLASH_FWPWRITE0_FWPWRITE0_M 0xFFFFFFFF +#define FLASH_FWPWRITE0_FWPWRITE0_S 0 //***************************************************************************** // @@ -2085,9 +2085,9 @@ // Field: [31:0] FWPWRITE1 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE1_FWPWRITE1_W 32 -#define FLASH_FWPWRITE1_FWPWRITE1_M 0xFFFFFFFF -#define FLASH_FWPWRITE1_FWPWRITE1_S 0 +#define FLASH_FWPWRITE1_FWPWRITE1_W 32 +#define FLASH_FWPWRITE1_FWPWRITE1_M 0xFFFFFFFF +#define FLASH_FWPWRITE1_FWPWRITE1_S 0 //***************************************************************************** // @@ -2097,9 +2097,9 @@ // Field: [31:0] FWPWRITE2 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE2_FWPWRITE2_W 32 -#define FLASH_FWPWRITE2_FWPWRITE2_M 0xFFFFFFFF -#define FLASH_FWPWRITE2_FWPWRITE2_S 0 +#define FLASH_FWPWRITE2_FWPWRITE2_W 32 +#define FLASH_FWPWRITE2_FWPWRITE2_M 0xFFFFFFFF +#define FLASH_FWPWRITE2_FWPWRITE2_S 0 //***************************************************************************** // @@ -2109,9 +2109,9 @@ // Field: [31:0] FWPWRITE3 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE3_FWPWRITE3_W 32 -#define FLASH_FWPWRITE3_FWPWRITE3_M 0xFFFFFFFF -#define FLASH_FWPWRITE3_FWPWRITE3_S 0 +#define FLASH_FWPWRITE3_FWPWRITE3_W 32 +#define FLASH_FWPWRITE3_FWPWRITE3_M 0xFFFFFFFF +#define FLASH_FWPWRITE3_FWPWRITE3_S 0 //***************************************************************************** // @@ -2121,9 +2121,9 @@ // Field: [31:0] FWPWRITE4 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE4_FWPWRITE4_W 32 -#define FLASH_FWPWRITE4_FWPWRITE4_M 0xFFFFFFFF -#define FLASH_FWPWRITE4_FWPWRITE4_S 0 +#define FLASH_FWPWRITE4_FWPWRITE4_W 32 +#define FLASH_FWPWRITE4_FWPWRITE4_M 0xFFFFFFFF +#define FLASH_FWPWRITE4_FWPWRITE4_S 0 //***************************************************************************** // @@ -2133,9 +2133,9 @@ // Field: [31:0] FWPWRITE5 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE5_FWPWRITE5_W 32 -#define FLASH_FWPWRITE5_FWPWRITE5_M 0xFFFFFFFF -#define FLASH_FWPWRITE5_FWPWRITE5_S 0 +#define FLASH_FWPWRITE5_FWPWRITE5_W 32 +#define FLASH_FWPWRITE5_FWPWRITE5_M 0xFFFFFFFF +#define FLASH_FWPWRITE5_FWPWRITE5_S 0 //***************************************************************************** // @@ -2145,9 +2145,9 @@ // Field: [31:0] FWPWRITE6 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE6_FWPWRITE6_W 32 -#define FLASH_FWPWRITE6_FWPWRITE6_M 0xFFFFFFFF -#define FLASH_FWPWRITE6_FWPWRITE6_S 0 +#define FLASH_FWPWRITE6_FWPWRITE6_W 32 +#define FLASH_FWPWRITE6_FWPWRITE6_M 0xFFFFFFFF +#define FLASH_FWPWRITE6_FWPWRITE6_S 0 //***************************************************************************** // @@ -2157,9 +2157,9 @@ // Field: [31:0] FWPWRITE7 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE7_FWPWRITE7_W 32 -#define FLASH_FWPWRITE7_FWPWRITE7_M 0xFFFFFFFF -#define FLASH_FWPWRITE7_FWPWRITE7_S 0 +#define FLASH_FWPWRITE7_FWPWRITE7_W 32 +#define FLASH_FWPWRITE7_FWPWRITE7_M 0xFFFFFFFF +#define FLASH_FWPWRITE7_FWPWRITE7_S 0 //***************************************************************************** // @@ -2169,30 +2169,30 @@ // Field: [31:24] ECCBYTES07_00 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_W 8 -#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_M 0xFF000000 -#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_S 24 +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_M 0xFF000000 +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_S 24 // Field: [23:16] ECCBYTES15_08 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_W 8 -#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_M 0x00FF0000 -#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_S 16 +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_M 0x00FF0000 +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_S 16 // Field: [15:8] ECCBYTES23_16 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_W 8 -#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_M 0x0000FF00 -#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_S 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_M 0x0000FF00 +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_S 8 // Field: [7:0] ECCBYTES31_24 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_W 8 -#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_M 0x000000FF -#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_S 0 +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_M 0x000000FF +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_S 0 //***************************************************************************** // @@ -2202,10 +2202,10 @@ // Field: [0] SAFELV // // Internal. Only to be used through TI provided API. -#define FLASH_FSWSTAT_SAFELV 0x00000001 -#define FLASH_FSWSTAT_SAFELV_BITN 0 -#define FLASH_FSWSTAT_SAFELV_M 0x00000001 -#define FLASH_FSWSTAT_SAFELV_S 0 +#define FLASH_FSWSTAT_SAFELV 0x00000001 +#define FLASH_FSWSTAT_SAFELV_BITN 0 +#define FLASH_FSWSTAT_SAFELV_M 0x00000001 +#define FLASH_FSWSTAT_SAFELV_S 0 //***************************************************************************** // @@ -2215,10 +2215,10 @@ // Field: [0] CLKSEL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_GLBCTL_CLKSEL 0x00000001 -#define FLASH_FSM_GLBCTL_CLKSEL_BITN 0 -#define FLASH_FSM_GLBCTL_CLKSEL_M 0x00000001 -#define FLASH_FSM_GLBCTL_CLKSEL_S 0 +#define FLASH_FSM_GLBCTL_CLKSEL 0x00000001 +#define FLASH_FSM_GLBCTL_CLKSEL_BITN 0 +#define FLASH_FSM_GLBCTL_CLKSEL_M 0x00000001 +#define FLASH_FSM_GLBCTL_CLKSEL_S 0 //***************************************************************************** // @@ -2228,42 +2228,42 @@ // Field: [11] CTRLENZ // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_CTRLENZ 0x00000800 -#define FLASH_FSM_STATE_CTRLENZ_BITN 11 -#define FLASH_FSM_STATE_CTRLENZ_M 0x00000800 -#define FLASH_FSM_STATE_CTRLENZ_S 11 +#define FLASH_FSM_STATE_CTRLENZ 0x00000800 +#define FLASH_FSM_STATE_CTRLENZ_BITN 11 +#define FLASH_FSM_STATE_CTRLENZ_M 0x00000800 +#define FLASH_FSM_STATE_CTRLENZ_S 11 // Field: [10] EXECUTEZ // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_EXECUTEZ 0x00000400 -#define FLASH_FSM_STATE_EXECUTEZ_BITN 10 -#define FLASH_FSM_STATE_EXECUTEZ_M 0x00000400 -#define FLASH_FSM_STATE_EXECUTEZ_S 10 +#define FLASH_FSM_STATE_EXECUTEZ 0x00000400 +#define FLASH_FSM_STATE_EXECUTEZ_BITN 10 +#define FLASH_FSM_STATE_EXECUTEZ_M 0x00000400 +#define FLASH_FSM_STATE_EXECUTEZ_S 10 // Field: [8] FSM_ACT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_FSM_ACT 0x00000100 -#define FLASH_FSM_STATE_FSM_ACT_BITN 8 -#define FLASH_FSM_STATE_FSM_ACT_M 0x00000100 -#define FLASH_FSM_STATE_FSM_ACT_S 8 +#define FLASH_FSM_STATE_FSM_ACT 0x00000100 +#define FLASH_FSM_STATE_FSM_ACT_BITN 8 +#define FLASH_FSM_STATE_FSM_ACT_M 0x00000100 +#define FLASH_FSM_STATE_FSM_ACT_S 8 // Field: [7] TIOTP_ACT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_TIOTP_ACT 0x00000080 -#define FLASH_FSM_STATE_TIOTP_ACT_BITN 7 -#define FLASH_FSM_STATE_TIOTP_ACT_M 0x00000080 -#define FLASH_FSM_STATE_TIOTP_ACT_S 7 +#define FLASH_FSM_STATE_TIOTP_ACT 0x00000080 +#define FLASH_FSM_STATE_TIOTP_ACT_BITN 7 +#define FLASH_FSM_STATE_TIOTP_ACT_M 0x00000080 +#define FLASH_FSM_STATE_TIOTP_ACT_S 7 // Field: [6] OTP_ACT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_OTP_ACT 0x00000040 -#define FLASH_FSM_STATE_OTP_ACT_BITN 6 -#define FLASH_FSM_STATE_OTP_ACT_M 0x00000040 -#define FLASH_FSM_STATE_OTP_ACT_S 6 +#define FLASH_FSM_STATE_OTP_ACT 0x00000040 +#define FLASH_FSM_STATE_OTP_ACT_BITN 6 +#define FLASH_FSM_STATE_OTP_ACT_M 0x00000040 +#define FLASH_FSM_STATE_OTP_ACT_S 6 //***************************************************************************** // @@ -2273,26 +2273,26 @@ // Field: [2] NON_OP // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STAT_NON_OP 0x00000004 -#define FLASH_FSM_STAT_NON_OP_BITN 2 -#define FLASH_FSM_STAT_NON_OP_M 0x00000004 -#define FLASH_FSM_STAT_NON_OP_S 2 +#define FLASH_FSM_STAT_NON_OP 0x00000004 +#define FLASH_FSM_STAT_NON_OP_BITN 2 +#define FLASH_FSM_STAT_NON_OP_M 0x00000004 +#define FLASH_FSM_STAT_NON_OP_S 2 // Field: [1] OVR_PUL_CNT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STAT_OVR_PUL_CNT 0x00000002 -#define FLASH_FSM_STAT_OVR_PUL_CNT_BITN 1 -#define FLASH_FSM_STAT_OVR_PUL_CNT_M 0x00000002 -#define FLASH_FSM_STAT_OVR_PUL_CNT_S 1 +#define FLASH_FSM_STAT_OVR_PUL_CNT 0x00000002 +#define FLASH_FSM_STAT_OVR_PUL_CNT_BITN 1 +#define FLASH_FSM_STAT_OVR_PUL_CNT_M 0x00000002 +#define FLASH_FSM_STAT_OVR_PUL_CNT_S 1 // Field: [0] INV_DAT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STAT_INV_DAT 0x00000001 -#define FLASH_FSM_STAT_INV_DAT_BITN 0 -#define FLASH_FSM_STAT_INV_DAT_M 0x00000001 -#define FLASH_FSM_STAT_INV_DAT_S 0 +#define FLASH_FSM_STAT_INV_DAT 0x00000001 +#define FLASH_FSM_STAT_INV_DAT_BITN 0 +#define FLASH_FSM_STAT_INV_DAT_M 0x00000001 +#define FLASH_FSM_STAT_INV_DAT_S 0 //***************************************************************************** // @@ -2302,9 +2302,9 @@ // Field: [5:0] FSMCMD // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_CMD_FSMCMD_W 6 -#define FLASH_FSM_CMD_FSMCMD_M 0x0000003F -#define FLASH_FSM_CMD_FSMCMD_S 0 +#define FLASH_FSM_CMD_FSMCMD_W 6 +#define FLASH_FSM_CMD_FSMCMD_M 0x0000003F +#define FLASH_FSM_CMD_FSMCMD_S 0 //***************************************************************************** // @@ -2314,16 +2314,16 @@ // Field: [15:8] PGM_OSU // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_OSU_PGM_OSU_W 8 -#define FLASH_FSM_PE_OSU_PGM_OSU_M 0x0000FF00 -#define FLASH_FSM_PE_OSU_PGM_OSU_S 8 +#define FLASH_FSM_PE_OSU_PGM_OSU_W 8 +#define FLASH_FSM_PE_OSU_PGM_OSU_M 0x0000FF00 +#define FLASH_FSM_PE_OSU_PGM_OSU_S 8 // Field: [7:0] ERA_OSU // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_OSU_ERA_OSU_W 8 -#define FLASH_FSM_PE_OSU_ERA_OSU_M 0x000000FF -#define FLASH_FSM_PE_OSU_ERA_OSU_S 0 +#define FLASH_FSM_PE_OSU_ERA_OSU_W 8 +#define FLASH_FSM_PE_OSU_ERA_OSU_M 0x000000FF +#define FLASH_FSM_PE_OSU_ERA_OSU_S 0 //***************************************************************************** // @@ -2333,9 +2333,9 @@ // Field: [15:12] VSTAT_CNT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_VSTAT_VSTAT_CNT_W 4 -#define FLASH_FSM_VSTAT_VSTAT_CNT_M 0x0000F000 -#define FLASH_FSM_VSTAT_VSTAT_CNT_S 12 +#define FLASH_FSM_VSTAT_VSTAT_CNT_W 4 +#define FLASH_FSM_VSTAT_VSTAT_CNT_M 0x0000F000 +#define FLASH_FSM_VSTAT_VSTAT_CNT_S 12 //***************************************************************************** // @@ -2345,16 +2345,16 @@ // Field: [15:8] PGM_VSU // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_VSU_PGM_VSU_W 8 -#define FLASH_FSM_PE_VSU_PGM_VSU_M 0x0000FF00 -#define FLASH_FSM_PE_VSU_PGM_VSU_S 8 +#define FLASH_FSM_PE_VSU_PGM_VSU_W 8 +#define FLASH_FSM_PE_VSU_PGM_VSU_M 0x0000FF00 +#define FLASH_FSM_PE_VSU_PGM_VSU_S 8 // Field: [7:0] ERA_VSU // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_VSU_ERA_VSU_W 8 -#define FLASH_FSM_PE_VSU_ERA_VSU_M 0x000000FF -#define FLASH_FSM_PE_VSU_ERA_VSU_S 0 +#define FLASH_FSM_PE_VSU_ERA_VSU_W 8 +#define FLASH_FSM_PE_VSU_ERA_VSU_M 0x000000FF +#define FLASH_FSM_PE_VSU_ERA_VSU_S 0 //***************************************************************************** // @@ -2364,9 +2364,9 @@ // Field: [15:12] ADD_EXZ // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_CMP_VSU_ADD_EXZ_W 4 -#define FLASH_FSM_CMP_VSU_ADD_EXZ_M 0x0000F000 -#define FLASH_FSM_CMP_VSU_ADD_EXZ_S 12 +#define FLASH_FSM_CMP_VSU_ADD_EXZ_W 4 +#define FLASH_FSM_CMP_VSU_ADD_EXZ_M 0x0000F000 +#define FLASH_FSM_CMP_VSU_ADD_EXZ_S 12 //***************************************************************************** // @@ -2376,16 +2376,16 @@ // Field: [15:8] REP_VSU // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_EX_VAL_REP_VSU_W 8 -#define FLASH_FSM_EX_VAL_REP_VSU_M 0x0000FF00 -#define FLASH_FSM_EX_VAL_REP_VSU_S 8 +#define FLASH_FSM_EX_VAL_REP_VSU_W 8 +#define FLASH_FSM_EX_VAL_REP_VSU_M 0x0000FF00 +#define FLASH_FSM_EX_VAL_REP_VSU_S 8 // Field: [7:0] EXE_VALD // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_EX_VAL_EXE_VALD_W 8 -#define FLASH_FSM_EX_VAL_EXE_VALD_M 0x000000FF -#define FLASH_FSM_EX_VAL_EXE_VALD_S 0 +#define FLASH_FSM_EX_VAL_EXE_VALD_W 8 +#define FLASH_FSM_EX_VAL_EXE_VALD_M 0x000000FF +#define FLASH_FSM_EX_VAL_EXE_VALD_S 0 //***************************************************************************** // @@ -2395,9 +2395,9 @@ // Field: [7:0] RD_H // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_RD_H_RD_H_W 8 -#define FLASH_FSM_RD_H_RD_H_M 0x000000FF -#define FLASH_FSM_RD_H_RD_H_S 0 +#define FLASH_FSM_RD_H_RD_H_W 8 +#define FLASH_FSM_RD_H_RD_H_M 0x000000FF +#define FLASH_FSM_RD_H_RD_H_S 0 //***************************************************************************** // @@ -2407,9 +2407,9 @@ // Field: [15:8] PGM_OH // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_P_OH_PGM_OH_W 8 -#define FLASH_FSM_P_OH_PGM_OH_M 0x0000FF00 -#define FLASH_FSM_P_OH_PGM_OH_S 8 +#define FLASH_FSM_P_OH_PGM_OH_W 8 +#define FLASH_FSM_P_OH_PGM_OH_M 0x0000FF00 +#define FLASH_FSM_P_OH_PGM_OH_S 8 //***************************************************************************** // @@ -2419,9 +2419,9 @@ // Field: [15:0] ERA_OH // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_OH_ERA_OH_W 16 -#define FLASH_FSM_ERA_OH_ERA_OH_M 0x0000FFFF -#define FLASH_FSM_ERA_OH_ERA_OH_S 0 +#define FLASH_FSM_ERA_OH_ERA_OH_W 16 +#define FLASH_FSM_ERA_OH_ERA_OH_M 0x0000FFFF +#define FLASH_FSM_ERA_OH_ERA_OH_S 0 //***************************************************************************** // @@ -2431,9 +2431,9 @@ // Field: [11:0] SAV_P_PUL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_W 12 -#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_M 0x00000FFF -#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_S 0 +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_W 12 +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_M 0x00000FFF +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_S 0 //***************************************************************************** // @@ -2443,9 +2443,9 @@ // Field: [15:8] PGM_VH // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_VH_PGM_VH_W 8 -#define FLASH_FSM_PE_VH_PGM_VH_M 0x0000FF00 -#define FLASH_FSM_PE_VH_PGM_VH_S 8 +#define FLASH_FSM_PE_VH_PGM_VH_W 8 +#define FLASH_FSM_PE_VH_PGM_VH_M 0x0000FF00 +#define FLASH_FSM_PE_VH_PGM_VH_S 8 //***************************************************************************** // @@ -2455,9 +2455,9 @@ // Field: [15:0] PROG_PUL_WIDTH // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_W 16 -#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M 0x0000FFFF -#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S 0 +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_W 16 +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M 0x0000FFFF +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S 0 //***************************************************************************** // @@ -2467,9 +2467,9 @@ // Field: [31:0] FSM_ERA_PW // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_PW_FSM_ERA_PW_W 32 -#define FLASH_FSM_ERA_PW_FSM_ERA_PW_M 0xFFFFFFFF -#define FLASH_FSM_ERA_PW_FSM_ERA_PW_S 0 +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_W 32 +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_M 0xFFFFFFFF +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_S 0 //***************************************************************************** // @@ -2479,9 +2479,9 @@ // Field: [11:0] SAV_ERA_PUL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_W 12 -#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_M 0x00000FFF -#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_S 0 +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_W 12 +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_M 0x00000FFF +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_S 0 //***************************************************************************** // @@ -2491,9 +2491,9 @@ // Field: [31:0] FSM_TIMER // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_TIMER_FSM_TIMER_W 32 -#define FLASH_FSM_TIMER_FSM_TIMER_M 0xFFFFFFFF -#define FLASH_FSM_TIMER_FSM_TIMER_S 0 +#define FLASH_FSM_TIMER_FSM_TIMER_W 32 +#define FLASH_FSM_TIMER_FSM_TIMER_M 0xFFFFFFFF +#define FLASH_FSM_TIMER_FSM_TIMER_S 0 //***************************************************************************** // @@ -2503,58 +2503,58 @@ // Field: [19:18] RDV_SUBMODE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_RDV_SUBMODE_W 2 -#define FLASH_FSM_MODE_RDV_SUBMODE_M 0x000C0000 -#define FLASH_FSM_MODE_RDV_SUBMODE_S 18 +#define FLASH_FSM_MODE_RDV_SUBMODE_W 2 +#define FLASH_FSM_MODE_RDV_SUBMODE_M 0x000C0000 +#define FLASH_FSM_MODE_RDV_SUBMODE_S 18 // Field: [17:16] PGM_SUBMODE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_PGM_SUBMODE_W 2 -#define FLASH_FSM_MODE_PGM_SUBMODE_M 0x00030000 -#define FLASH_FSM_MODE_PGM_SUBMODE_S 16 +#define FLASH_FSM_MODE_PGM_SUBMODE_W 2 +#define FLASH_FSM_MODE_PGM_SUBMODE_M 0x00030000 +#define FLASH_FSM_MODE_PGM_SUBMODE_S 16 // Field: [15:14] ERA_SUBMODE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_ERA_SUBMODE_W 2 -#define FLASH_FSM_MODE_ERA_SUBMODE_M 0x0000C000 -#define FLASH_FSM_MODE_ERA_SUBMODE_S 14 +#define FLASH_FSM_MODE_ERA_SUBMODE_W 2 +#define FLASH_FSM_MODE_ERA_SUBMODE_M 0x0000C000 +#define FLASH_FSM_MODE_ERA_SUBMODE_S 14 // Field: [13:12] SUBMODE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_SUBMODE_W 2 -#define FLASH_FSM_MODE_SUBMODE_M 0x00003000 -#define FLASH_FSM_MODE_SUBMODE_S 12 +#define FLASH_FSM_MODE_SUBMODE_W 2 +#define FLASH_FSM_MODE_SUBMODE_M 0x00003000 +#define FLASH_FSM_MODE_SUBMODE_S 12 // Field: [11:9] SAV_PGM_CMD // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_SAV_PGM_CMD_W 3 -#define FLASH_FSM_MODE_SAV_PGM_CMD_M 0x00000E00 -#define FLASH_FSM_MODE_SAV_PGM_CMD_S 9 +#define FLASH_FSM_MODE_SAV_PGM_CMD_W 3 +#define FLASH_FSM_MODE_SAV_PGM_CMD_M 0x00000E00 +#define FLASH_FSM_MODE_SAV_PGM_CMD_S 9 // Field: [8:6] SAV_ERA_MODE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_SAV_ERA_MODE_W 3 -#define FLASH_FSM_MODE_SAV_ERA_MODE_M 0x000001C0 -#define FLASH_FSM_MODE_SAV_ERA_MODE_S 6 +#define FLASH_FSM_MODE_SAV_ERA_MODE_W 3 +#define FLASH_FSM_MODE_SAV_ERA_MODE_M 0x000001C0 +#define FLASH_FSM_MODE_SAV_ERA_MODE_S 6 // Field: [5:3] MODE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_MODE_W 3 -#define FLASH_FSM_MODE_MODE_M 0x00000038 -#define FLASH_FSM_MODE_MODE_S 3 +#define FLASH_FSM_MODE_MODE_W 3 +#define FLASH_FSM_MODE_MODE_M 0x00000038 +#define FLASH_FSM_MODE_MODE_S 3 // Field: [2:0] CMD // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_CMD_W 3 -#define FLASH_FSM_MODE_CMD_M 0x00000007 -#define FLASH_FSM_MODE_CMD_S 0 +#define FLASH_FSM_MODE_CMD_W 3 +#define FLASH_FSM_MODE_CMD_M 0x00000007 +#define FLASH_FSM_MODE_CMD_S 0 //***************************************************************************** // @@ -2564,16 +2564,16 @@ // Field: [25:23] PGM_BANK // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PGM_PGM_BANK_W 3 -#define FLASH_FSM_PGM_PGM_BANK_M 0x03800000 -#define FLASH_FSM_PGM_PGM_BANK_S 23 +#define FLASH_FSM_PGM_PGM_BANK_W 3 +#define FLASH_FSM_PGM_PGM_BANK_M 0x03800000 +#define FLASH_FSM_PGM_PGM_BANK_S 23 // Field: [22:0] PGM_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PGM_PGM_ADDR_W 23 -#define FLASH_FSM_PGM_PGM_ADDR_M 0x007FFFFF -#define FLASH_FSM_PGM_PGM_ADDR_S 0 +#define FLASH_FSM_PGM_PGM_ADDR_W 23 +#define FLASH_FSM_PGM_PGM_ADDR_M 0x007FFFFF +#define FLASH_FSM_PGM_PGM_ADDR_S 0 //***************************************************************************** // @@ -2583,16 +2583,16 @@ // Field: [25:23] ERA_BANK // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_ERA_BANK_W 3 -#define FLASH_FSM_ERA_ERA_BANK_M 0x03800000 -#define FLASH_FSM_ERA_ERA_BANK_S 23 +#define FLASH_FSM_ERA_ERA_BANK_W 3 +#define FLASH_FSM_ERA_ERA_BANK_M 0x03800000 +#define FLASH_FSM_ERA_ERA_BANK_S 23 // Field: [22:0] ERA_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_ERA_ADDR_W 23 -#define FLASH_FSM_ERA_ERA_ADDR_M 0x007FFFFF -#define FLASH_FSM_ERA_ERA_ADDR_S 0 +#define FLASH_FSM_ERA_ERA_ADDR_W 23 +#define FLASH_FSM_ERA_ERA_ADDR_M 0x007FFFFF +#define FLASH_FSM_ERA_ERA_ADDR_S 0 //***************************************************************************** // @@ -2602,16 +2602,16 @@ // Field: [19:16] BEG_EC_LEVEL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_W 4 -#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M 0x000F0000 -#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S 16 +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_W 4 +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M 0x000F0000 +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S 16 // Field: [11:0] MAX_PRG_PUL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_W 12 -#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M 0x00000FFF -#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S 0 +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_W 12 +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M 0x00000FFF +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S 0 //***************************************************************************** // @@ -2621,16 +2621,16 @@ // Field: [19:16] MAX_EC_LEVEL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_W 4 -#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M 0x000F0000 -#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S 16 +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_W 4 +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M 0x000F0000 +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S 16 // Field: [11:0] MAX_ERA_PUL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_W 12 -#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M 0x00000FFF -#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S 0 +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_W 12 +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M 0x00000FFF +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S 0 //***************************************************************************** // @@ -2640,9 +2640,9 @@ // Field: [24:16] EC_STEP_SIZE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_W 9 -#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M 0x01FF0000 -#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S 16 +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_W 9 +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M 0x01FF0000 +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S 16 //***************************************************************************** // @@ -2652,16 +2652,16 @@ // Field: [24:16] CUR_EC_LEVEL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_W 9 -#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_M 0x01FF0000 -#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_S 16 +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_W 9 +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_M 0x01FF0000 +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_S 16 // Field: [11:0] PUL_CNTR // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PUL_CNTR_PUL_CNTR_W 12 -#define FLASH_FSM_PUL_CNTR_PUL_CNTR_M 0x00000FFF -#define FLASH_FSM_PUL_CNTR_PUL_CNTR_S 0 +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_W 12 +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_M 0x00000FFF +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_S 0 //***************************************************************************** // @@ -2671,9 +2671,9 @@ // Field: [3:0] EC_STEP_HEIGHT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_W 4 -#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M 0x0000000F -#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_S 0 +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_W 4 +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M 0x0000000F +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_S 0 //***************************************************************************** // @@ -2683,137 +2683,137 @@ // Field: [23] DO_PRECOND // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_DO_PRECOND 0x00800000 -#define FLASH_FSM_ST_MACHINE_DO_PRECOND_BITN 23 -#define FLASH_FSM_ST_MACHINE_DO_PRECOND_M 0x00800000 -#define FLASH_FSM_ST_MACHINE_DO_PRECOND_S 23 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND 0x00800000 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_BITN 23 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_M 0x00800000 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_S 23 // Field: [22] FSM_INT_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_FSM_INT_EN 0x00400000 -#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_BITN 22 -#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_M 0x00400000 -#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_S 22 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN 0x00400000 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_BITN 22 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_M 0x00400000 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_S 22 // Field: [21] ALL_BANKS // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_ALL_BANKS 0x00200000 -#define FLASH_FSM_ST_MACHINE_ALL_BANKS_BITN 21 -#define FLASH_FSM_ST_MACHINE_ALL_BANKS_M 0x00200000 -#define FLASH_FSM_ST_MACHINE_ALL_BANKS_S 21 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS 0x00200000 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_BITN 21 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_M 0x00200000 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_S 21 // Field: [20] CMPV_ALLOWED // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED 0x00100000 -#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_BITN 20 -#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_M 0x00100000 -#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_S 20 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED 0x00100000 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_BITN 20 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_M 0x00100000 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_S 20 // Field: [19] RANDOM // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_RANDOM 0x00080000 -#define FLASH_FSM_ST_MACHINE_RANDOM_BITN 19 -#define FLASH_FSM_ST_MACHINE_RANDOM_M 0x00080000 -#define FLASH_FSM_ST_MACHINE_RANDOM_S 19 +#define FLASH_FSM_ST_MACHINE_RANDOM 0x00080000 +#define FLASH_FSM_ST_MACHINE_RANDOM_BITN 19 +#define FLASH_FSM_ST_MACHINE_RANDOM_M 0x00080000 +#define FLASH_FSM_ST_MACHINE_RANDOM_S 19 // Field: [18] RV_SEC_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_RV_SEC_EN 0x00040000 -#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_BITN 18 -#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_M 0x00040000 -#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_S 18 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN 0x00040000 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_BITN 18 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_M 0x00040000 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_S 18 // Field: [17] RV_RES // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_RV_RES 0x00020000 -#define FLASH_FSM_ST_MACHINE_RV_RES_BITN 17 -#define FLASH_FSM_ST_MACHINE_RV_RES_M 0x00020000 -#define FLASH_FSM_ST_MACHINE_RV_RES_S 17 +#define FLASH_FSM_ST_MACHINE_RV_RES 0x00020000 +#define FLASH_FSM_ST_MACHINE_RV_RES_BITN 17 +#define FLASH_FSM_ST_MACHINE_RV_RES_M 0x00020000 +#define FLASH_FSM_ST_MACHINE_RV_RES_S 17 // Field: [16] RV_INT_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_RV_INT_EN 0x00010000 -#define FLASH_FSM_ST_MACHINE_RV_INT_EN_BITN 16 -#define FLASH_FSM_ST_MACHINE_RV_INT_EN_M 0x00010000 -#define FLASH_FSM_ST_MACHINE_RV_INT_EN_S 16 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN 0x00010000 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_BITN 16 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_M 0x00010000 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_S 16 // Field: [14] ONE_TIME_GOOD // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD 0x00004000 -#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_BITN 14 -#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_M 0x00004000 -#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_S 14 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD 0x00004000 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_BITN 14 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_M 0x00004000 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_S 14 // Field: [11] DO_REDU_COL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_DO_REDU_COL 0x00000800 -#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_BITN 11 -#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_M 0x00000800 -#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_S 11 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL 0x00000800 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_BITN 11 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_M 0x00000800 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_S 11 // Field: [10:7] DBG_SHORT_ROW // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_W 4 -#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_M 0x00000780 -#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_S 7 +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_W 4 +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_M 0x00000780 +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_S 7 // Field: [5] PGM_SEC_COF_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN 0x00000020 -#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_BITN 5 -#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_M 0x00000020 -#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_S 5 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN 0x00000020 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_BITN 5 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_M 0x00000020 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_S 5 // Field: [4] PREC_STOP_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN 0x00000010 -#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_BITN 4 -#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_M 0x00000010 -#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_S 4 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN 0x00000010 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_BITN 4 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_M 0x00000010 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_S 4 // Field: [3] DIS_TST_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_DIS_TST_EN 0x00000008 -#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_BITN 3 -#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_M 0x00000008 -#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_S 3 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN 0x00000008 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_BITN 3 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_M 0x00000008 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_S 3 // Field: [2] CMD_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_CMD_EN 0x00000004 -#define FLASH_FSM_ST_MACHINE_CMD_EN_BITN 2 -#define FLASH_FSM_ST_MACHINE_CMD_EN_M 0x00000004 -#define FLASH_FSM_ST_MACHINE_CMD_EN_S 2 +#define FLASH_FSM_ST_MACHINE_CMD_EN 0x00000004 +#define FLASH_FSM_ST_MACHINE_CMD_EN_BITN 2 +#define FLASH_FSM_ST_MACHINE_CMD_EN_M 0x00000004 +#define FLASH_FSM_ST_MACHINE_CMD_EN_S 2 // Field: [1] INV_DATA // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_INV_DATA 0x00000002 -#define FLASH_FSM_ST_MACHINE_INV_DATA_BITN 1 -#define FLASH_FSM_ST_MACHINE_INV_DATA_M 0x00000002 -#define FLASH_FSM_ST_MACHINE_INV_DATA_S 1 +#define FLASH_FSM_ST_MACHINE_INV_DATA 0x00000002 +#define FLASH_FSM_ST_MACHINE_INV_DATA_BITN 1 +#define FLASH_FSM_ST_MACHINE_INV_DATA_M 0x00000002 +#define FLASH_FSM_ST_MACHINE_INV_DATA_S 1 // Field: [0] OVERRIDE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_OVERRIDE 0x00000001 -#define FLASH_FSM_ST_MACHINE_OVERRIDE_BITN 0 -#define FLASH_FSM_ST_MACHINE_OVERRIDE_M 0x00000001 -#define FLASH_FSM_ST_MACHINE_OVERRIDE_S 0 +#define FLASH_FSM_ST_MACHINE_OVERRIDE 0x00000001 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_BITN 0 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_M 0x00000001 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_S 0 //***************************************************************************** // @@ -2823,16 +2823,16 @@ // Field: [11:8] BLK_TIOTP // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_FLES_BLK_TIOTP_W 4 -#define FLASH_FSM_FLES_BLK_TIOTP_M 0x00000F00 -#define FLASH_FSM_FLES_BLK_TIOTP_S 8 +#define FLASH_FSM_FLES_BLK_TIOTP_W 4 +#define FLASH_FSM_FLES_BLK_TIOTP_M 0x00000F00 +#define FLASH_FSM_FLES_BLK_TIOTP_S 8 // Field: [7:0] BLK_OTP // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_FLES_BLK_OTP_W 8 -#define FLASH_FSM_FLES_BLK_OTP_M 0x000000FF -#define FLASH_FSM_FLES_BLK_OTP_S 0 +#define FLASH_FSM_FLES_BLK_OTP_W 8 +#define FLASH_FSM_FLES_BLK_OTP_M 0x000000FF +#define FLASH_FSM_FLES_BLK_OTP_S 0 //***************************************************************************** // @@ -2842,9 +2842,9 @@ // Field: [2:0] WR_ENA // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_WR_ENA_WR_ENA_W 3 -#define FLASH_FSM_WR_ENA_WR_ENA_M 0x00000007 -#define FLASH_FSM_WR_ENA_WR_ENA_S 0 +#define FLASH_FSM_WR_ENA_WR_ENA_W 3 +#define FLASH_FSM_WR_ENA_WR_ENA_M 0x00000007 +#define FLASH_FSM_WR_ENA_WR_ENA_S 0 //***************************************************************************** // @@ -2854,9 +2854,9 @@ // Field: [31:0] FSM_ACC_PP // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ACC_PP_FSM_ACC_PP_W 32 -#define FLASH_FSM_ACC_PP_FSM_ACC_PP_M 0xFFFFFFFF -#define FLASH_FSM_ACC_PP_FSM_ACC_PP_S 0 +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_W 32 +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_M 0xFFFFFFFF +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_S 0 //***************************************************************************** // @@ -2866,9 +2866,9 @@ // Field: [15:0] ACC_EP // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ACC_EP_ACC_EP_W 16 -#define FLASH_FSM_ACC_EP_ACC_EP_M 0x0000FFFF -#define FLASH_FSM_ACC_EP_ACC_EP_S 0 +#define FLASH_FSM_ACC_EP_ACC_EP_W 16 +#define FLASH_FSM_ACC_EP_ACC_EP_M 0x0000FFFF +#define FLASH_FSM_ACC_EP_ACC_EP_S 0 //***************************************************************************** // @@ -2878,16 +2878,16 @@ // Field: [30:28] BANK // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ADDR_BANK_W 3 -#define FLASH_FSM_ADDR_BANK_M 0x70000000 -#define FLASH_FSM_ADDR_BANK_S 28 +#define FLASH_FSM_ADDR_BANK_W 3 +#define FLASH_FSM_ADDR_BANK_M 0x70000000 +#define FLASH_FSM_ADDR_BANK_S 28 // Field: [27:0] CUR_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ADDR_CUR_ADDR_W 28 -#define FLASH_FSM_ADDR_CUR_ADDR_M 0x0FFFFFFF -#define FLASH_FSM_ADDR_CUR_ADDR_S 0 +#define FLASH_FSM_ADDR_CUR_ADDR_W 28 +#define FLASH_FSM_ADDR_CUR_ADDR_M 0x0FFFFFFF +#define FLASH_FSM_ADDR_CUR_ADDR_S 0 //***************************************************************************** // @@ -2897,30 +2897,30 @@ // Field: [31:16] SECT_ERASED // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR_SECT_ERASED_W 16 -#define FLASH_FSM_SECTOR_SECT_ERASED_M 0xFFFF0000 -#define FLASH_FSM_SECTOR_SECT_ERASED_S 16 +#define FLASH_FSM_SECTOR_SECT_ERASED_W 16 +#define FLASH_FSM_SECTOR_SECT_ERASED_M 0xFFFF0000 +#define FLASH_FSM_SECTOR_SECT_ERASED_S 16 // Field: [15:8] FSM_SECTOR_EXTENSION // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_W 8 -#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_M 0x0000FF00 -#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_S 8 +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_W 8 +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_M 0x0000FF00 +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_S 8 // Field: [7:4] SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR_SECTOR_W 4 -#define FLASH_FSM_SECTOR_SECTOR_M 0x000000F0 -#define FLASH_FSM_SECTOR_SECTOR_S 4 +#define FLASH_FSM_SECTOR_SECTOR_W 4 +#define FLASH_FSM_SECTOR_SECTOR_M 0x000000F0 +#define FLASH_FSM_SECTOR_SECTOR_S 4 // Field: [3:0] SEC_OUT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR_SEC_OUT_W 4 -#define FLASH_FSM_SECTOR_SEC_OUT_M 0x0000000F -#define FLASH_FSM_SECTOR_SEC_OUT_S 0 +#define FLASH_FSM_SECTOR_SEC_OUT_W 4 +#define FLASH_FSM_SECTOR_SEC_OUT_M 0x0000000F +#define FLASH_FSM_SECTOR_SEC_OUT_S 0 //***************************************************************************** // @@ -2930,16 +2930,16 @@ // Field: [31:12] MOD_VERSION // // Internal. Only to be used through TI provided API. -#define FLASH_FMC_REV_ID_MOD_VERSION_W 20 -#define FLASH_FMC_REV_ID_MOD_VERSION_M 0xFFFFF000 -#define FLASH_FMC_REV_ID_MOD_VERSION_S 12 +#define FLASH_FMC_REV_ID_MOD_VERSION_W 20 +#define FLASH_FMC_REV_ID_MOD_VERSION_M 0xFFFFF000 +#define FLASH_FMC_REV_ID_MOD_VERSION_S 12 // Field: [11:0] CONFIG_CRC // // Internal. Only to be used through TI provided API. -#define FLASH_FMC_REV_ID_CONFIG_CRC_W 12 -#define FLASH_FMC_REV_ID_CONFIG_CRC_M 0x00000FFF -#define FLASH_FMC_REV_ID_CONFIG_CRC_S 0 +#define FLASH_FMC_REV_ID_CONFIG_CRC_W 12 +#define FLASH_FMC_REV_ID_CONFIG_CRC_M 0x00000FFF +#define FLASH_FMC_REV_ID_CONFIG_CRC_S 0 //***************************************************************************** // @@ -2949,16 +2949,16 @@ // Field: [31:8] FSM_ERR_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_W 24 -#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_M 0xFFFFFF00 -#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_S 8 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_W 24 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_M 0xFFFFFF00 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_S 8 // Field: [3:0] FSM_ERR_BANK // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_W 4 -#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_M 0x0000000F -#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_S 0 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_W 4 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_M 0x0000000F +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_S 0 //***************************************************************************** // @@ -2968,9 +2968,9 @@ // Field: [11:0] FSM_PGM_MAXPUL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_W 12 -#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_M 0x00000FFF -#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_S 0 +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_W 12 +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_M 0x00000FFF +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_S 0 //***************************************************************************** // @@ -2980,16 +2980,16 @@ // Field: [19:16] SUSPEND_NOW // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_EXECUTE_SUSPEND_NOW_W 4 -#define FLASH_FSM_EXECUTE_SUSPEND_NOW_M 0x000F0000 -#define FLASH_FSM_EXECUTE_SUSPEND_NOW_S 16 +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_W 4 +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_M 0x000F0000 +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_S 16 // Field: [4:0] FSMEXECUTE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_EXECUTE_FSMEXECUTE_W 5 -#define FLASH_FSM_EXECUTE_FSMEXECUTE_M 0x0000001F -#define FLASH_FSM_EXECUTE_FSMEXECUTE_S 0 +#define FLASH_FSM_EXECUTE_FSMEXECUTE_W 5 +#define FLASH_FSM_EXECUTE_FSMEXECUTE_M 0x0000001F +#define FLASH_FSM_EXECUTE_FSMEXECUTE_S 0 //***************************************************************************** // @@ -2999,9 +2999,9 @@ // Field: [31:0] FSM_SECTOR1 // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR1_FSM_SECTOR1_W 32 -#define FLASH_FSM_SECTOR1_FSM_SECTOR1_M 0xFFFFFFFF -#define FLASH_FSM_SECTOR1_FSM_SECTOR1_S 0 +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_W 32 +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_M 0xFFFFFFFF +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_S 0 //***************************************************************************** // @@ -3011,9 +3011,9 @@ // Field: [31:0] FSM_SECTOR2 // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR2_FSM_SECTOR2_W 32 -#define FLASH_FSM_SECTOR2_FSM_SECTOR2_M 0xFFFFFFFF -#define FLASH_FSM_SECTOR2_FSM_SECTOR2_S 0 +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_W 32 +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_M 0xFFFFFFFF +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_S 0 //***************************************************************************** // @@ -3023,9 +3023,9 @@ // Field: [31:0] FSM_BSLE0 // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_BSLE0_FSM_BSLE0_W 32 -#define FLASH_FSM_BSLE0_FSM_BSLE0_M 0xFFFFFFFF -#define FLASH_FSM_BSLE0_FSM_BSLE0_S 0 +#define FLASH_FSM_BSLE0_FSM_BSLE0_W 32 +#define FLASH_FSM_BSLE0_FSM_BSLE0_M 0xFFFFFFFF +#define FLASH_FSM_BSLE0_FSM_BSLE0_S 0 //***************************************************************************** // @@ -3035,9 +3035,9 @@ // Field: [31:0] FSM_BSL1 // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_BSLE1_FSM_BSL1_W 32 -#define FLASH_FSM_BSLE1_FSM_BSL1_M 0xFFFFFFFF -#define FLASH_FSM_BSLE1_FSM_BSL1_S 0 +#define FLASH_FSM_BSLE1_FSM_BSL1_W 32 +#define FLASH_FSM_BSLE1_FSM_BSL1_M 0xFFFFFFFF +#define FLASH_FSM_BSLE1_FSM_BSL1_S 0 //***************************************************************************** // @@ -3047,9 +3047,9 @@ // Field: [31:0] FSM_BSLP0 // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_BSLP0_FSM_BSLP0_W 32 -#define FLASH_FSM_BSLP0_FSM_BSLP0_M 0xFFFFFFFF -#define FLASH_FSM_BSLP0_FSM_BSLP0_S 0 +#define FLASH_FSM_BSLP0_FSM_BSLP0_W 32 +#define FLASH_FSM_BSLP0_FSM_BSLP0_M 0xFFFFFFFF +#define FLASH_FSM_BSLP0_FSM_BSLP0_S 0 //***************************************************************************** // @@ -3059,9 +3059,9 @@ // Field: [31:0] FSM_BSL1 // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_BSLP1_FSM_BSL1_W 32 -#define FLASH_FSM_BSLP1_FSM_BSL1_M 0xFFFFFFFF -#define FLASH_FSM_BSLP1_FSM_BSL1_S 0 +#define FLASH_FSM_BSLP1_FSM_BSL1_W 32 +#define FLASH_FSM_BSLP1_FSM_BSL1_M 0xFFFFFFFF +#define FLASH_FSM_BSLP1_FSM_BSL1_S 0 //***************************************************************************** // @@ -3071,30 +3071,30 @@ // Field: [31:20] EE_BANK_WIDTH // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BANK_EE_BANK_WIDTH_W 12 -#define FLASH_FCFG_BANK_EE_BANK_WIDTH_M 0xFFF00000 -#define FLASH_FCFG_BANK_EE_BANK_WIDTH_S 20 +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_W 12 +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_M 0xFFF00000 +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_S 20 // Field: [19:16] EE_NUM_BANK // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BANK_EE_NUM_BANK_W 4 -#define FLASH_FCFG_BANK_EE_NUM_BANK_M 0x000F0000 -#define FLASH_FCFG_BANK_EE_NUM_BANK_S 16 +#define FLASH_FCFG_BANK_EE_NUM_BANK_W 4 +#define FLASH_FCFG_BANK_EE_NUM_BANK_M 0x000F0000 +#define FLASH_FCFG_BANK_EE_NUM_BANK_S 16 // Field: [15:4] MAIN_BANK_WIDTH // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_W 12 -#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M 0x0000FFF0 -#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S 4 +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_W 12 +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M 0x0000FFF0 +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S 4 // Field: [3:0] MAIN_NUM_BANK // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BANK_MAIN_NUM_BANK_W 4 -#define FLASH_FCFG_BANK_MAIN_NUM_BANK_M 0x0000000F -#define FLASH_FCFG_BANK_MAIN_NUM_BANK_S 0 +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_W 4 +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_M 0x0000000F +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_S 0 //***************************************************************************** // @@ -3104,84 +3104,84 @@ // Field: [31:24] FAMILY_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_W 8 -#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_M 0xFF000000 -#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_S 24 +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_W 8 +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_M 0xFF000000 +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_S 24 // Field: [20] MEM_MAP // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_MEM_MAP 0x00100000 -#define FLASH_FCFG_WRAPPER_MEM_MAP_BITN 20 -#define FLASH_FCFG_WRAPPER_MEM_MAP_M 0x00100000 -#define FLASH_FCFG_WRAPPER_MEM_MAP_S 20 +#define FLASH_FCFG_WRAPPER_MEM_MAP 0x00100000 +#define FLASH_FCFG_WRAPPER_MEM_MAP_BITN 20 +#define FLASH_FCFG_WRAPPER_MEM_MAP_M 0x00100000 +#define FLASH_FCFG_WRAPPER_MEM_MAP_S 20 // Field: [19:16] CPU2 // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_CPU2_W 4 -#define FLASH_FCFG_WRAPPER_CPU2_M 0x000F0000 -#define FLASH_FCFG_WRAPPER_CPU2_S 16 +#define FLASH_FCFG_WRAPPER_CPU2_W 4 +#define FLASH_FCFG_WRAPPER_CPU2_M 0x000F0000 +#define FLASH_FCFG_WRAPPER_CPU2_S 16 // Field: [15:12] EE_IN_MAIN // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_W 4 -#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_M 0x0000F000 -#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_S 12 +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_W 4 +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_M 0x0000F000 +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_S 12 // Field: [11] ROM // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_ROM 0x00000800 -#define FLASH_FCFG_WRAPPER_ROM_BITN 11 -#define FLASH_FCFG_WRAPPER_ROM_M 0x00000800 -#define FLASH_FCFG_WRAPPER_ROM_S 11 +#define FLASH_FCFG_WRAPPER_ROM 0x00000800 +#define FLASH_FCFG_WRAPPER_ROM_BITN 11 +#define FLASH_FCFG_WRAPPER_ROM_M 0x00000800 +#define FLASH_FCFG_WRAPPER_ROM_S 11 // Field: [10] IFLUSH // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_IFLUSH 0x00000400 -#define FLASH_FCFG_WRAPPER_IFLUSH_BITN 10 -#define FLASH_FCFG_WRAPPER_IFLUSH_M 0x00000400 -#define FLASH_FCFG_WRAPPER_IFLUSH_S 10 +#define FLASH_FCFG_WRAPPER_IFLUSH 0x00000400 +#define FLASH_FCFG_WRAPPER_IFLUSH_BITN 10 +#define FLASH_FCFG_WRAPPER_IFLUSH_M 0x00000400 +#define FLASH_FCFG_WRAPPER_IFLUSH_S 10 // Field: [9] SIL3 // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_SIL3 0x00000200 -#define FLASH_FCFG_WRAPPER_SIL3_BITN 9 -#define FLASH_FCFG_WRAPPER_SIL3_M 0x00000200 -#define FLASH_FCFG_WRAPPER_SIL3_S 9 +#define FLASH_FCFG_WRAPPER_SIL3 0x00000200 +#define FLASH_FCFG_WRAPPER_SIL3_BITN 9 +#define FLASH_FCFG_WRAPPER_SIL3_M 0x00000200 +#define FLASH_FCFG_WRAPPER_SIL3_S 9 // Field: [8] ECCA // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_ECCA 0x00000100 -#define FLASH_FCFG_WRAPPER_ECCA_BITN 8 -#define FLASH_FCFG_WRAPPER_ECCA_M 0x00000100 -#define FLASH_FCFG_WRAPPER_ECCA_S 8 +#define FLASH_FCFG_WRAPPER_ECCA 0x00000100 +#define FLASH_FCFG_WRAPPER_ECCA_BITN 8 +#define FLASH_FCFG_WRAPPER_ECCA_M 0x00000100 +#define FLASH_FCFG_WRAPPER_ECCA_S 8 // Field: [7:6] AUTO_SUSP // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_AUTO_SUSP_W 2 -#define FLASH_FCFG_WRAPPER_AUTO_SUSP_M 0x000000C0 -#define FLASH_FCFG_WRAPPER_AUTO_SUSP_S 6 +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_W 2 +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_M 0x000000C0 +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_S 6 // Field: [5:4] UERR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_UERR_W 2 -#define FLASH_FCFG_WRAPPER_UERR_M 0x00000030 -#define FLASH_FCFG_WRAPPER_UERR_S 4 +#define FLASH_FCFG_WRAPPER_UERR_W 2 +#define FLASH_FCFG_WRAPPER_UERR_M 0x00000030 +#define FLASH_FCFG_WRAPPER_UERR_S 4 // Field: [3:0] CPU_TYPE1 // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_CPU_TYPE1_W 4 -#define FLASH_FCFG_WRAPPER_CPU_TYPE1_M 0x0000000F -#define FLASH_FCFG_WRAPPER_CPU_TYPE1_S 0 +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_W 4 +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_M 0x0000000F +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_S 0 //***************************************************************************** // @@ -3191,58 +3191,58 @@ // Field: [31:28] B7_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B7_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B7_TYPE_M 0xF0000000 -#define FLASH_FCFG_BNK_TYPE_B7_TYPE_S 28 +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_M 0xF0000000 +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_S 28 // Field: [27:24] B6_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B6_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B6_TYPE_M 0x0F000000 -#define FLASH_FCFG_BNK_TYPE_B6_TYPE_S 24 +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_M 0x0F000000 +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_S 24 // Field: [23:20] B5_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B5_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B5_TYPE_M 0x00F00000 -#define FLASH_FCFG_BNK_TYPE_B5_TYPE_S 20 +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_M 0x00F00000 +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_S 20 // Field: [19:16] B4_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B4_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B4_TYPE_M 0x000F0000 -#define FLASH_FCFG_BNK_TYPE_B4_TYPE_S 16 +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_M 0x000F0000 +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_S 16 // Field: [15:12] B3_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B3_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B3_TYPE_M 0x0000F000 -#define FLASH_FCFG_BNK_TYPE_B3_TYPE_S 12 +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_M 0x0000F000 +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_S 12 // Field: [11:8] B2_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B2_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B2_TYPE_M 0x00000F00 -#define FLASH_FCFG_BNK_TYPE_B2_TYPE_S 8 +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_M 0x00000F00 +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_S 8 // Field: [7:4] B1_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B1_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B1_TYPE_M 0x000000F0 -#define FLASH_FCFG_BNK_TYPE_B1_TYPE_S 4 +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_M 0x000000F0 +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_S 4 // Field: [3:0] B0_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B0_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B0_TYPE_M 0x0000000F -#define FLASH_FCFG_BNK_TYPE_B0_TYPE_S 0 +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_M 0x0000000F +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_S 0 //***************************************************************************** // @@ -3252,23 +3252,23 @@ // Field: [31:28] B0_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_W 4 -#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_S 28 +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_W 4 +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_S 28 // Field: [27:24] B0_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_W 4 -#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_S 24 +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_W 4 +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_S 24 // Field: [23:0] B0_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_START_B0_START_ADDR_W 24 -#define FLASH_FCFG_B0_START_B0_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B0_START_B0_START_ADDR_S 0 +#define FLASH_FCFG_B0_START_B0_START_ADDR_W 24 +#define FLASH_FCFG_B0_START_B0_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B0_START_B0_START_ADDR_S 0 //***************************************************************************** // @@ -3278,23 +3278,23 @@ // Field: [31:28] B1_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_W 4 -#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_S 28 +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_W 4 +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_S 28 // Field: [27:24] B1_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_W 4 -#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_S 24 +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_W 4 +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_S 24 // Field: [23:0] B1_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B1_START_B1_START_ADDR_W 24 -#define FLASH_FCFG_B1_START_B1_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B1_START_B1_START_ADDR_S 0 +#define FLASH_FCFG_B1_START_B1_START_ADDR_W 24 +#define FLASH_FCFG_B1_START_B1_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B1_START_B1_START_ADDR_S 0 //***************************************************************************** // @@ -3304,23 +3304,23 @@ // Field: [31:28] B2_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_W 4 -#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_S 28 +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_W 4 +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_S 28 // Field: [27:24] B2_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_W 4 -#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_S 24 +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_W 4 +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_S 24 // Field: [23:0] B2_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B2_START_B2_START_ADDR_W 24 -#define FLASH_FCFG_B2_START_B2_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B2_START_B2_START_ADDR_S 0 +#define FLASH_FCFG_B2_START_B2_START_ADDR_W 24 +#define FLASH_FCFG_B2_START_B2_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B2_START_B2_START_ADDR_S 0 //***************************************************************************** // @@ -3330,23 +3330,23 @@ // Field: [31:28] B3_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_W 4 -#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_S 28 +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_W 4 +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_S 28 // Field: [27:24] B3_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_W 4 -#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_S 24 +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_W 4 +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_S 24 // Field: [23:0] B3_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B3_START_B3_START_ADDR_W 24 -#define FLASH_FCFG_B3_START_B3_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B3_START_B3_START_ADDR_S 0 +#define FLASH_FCFG_B3_START_B3_START_ADDR_W 24 +#define FLASH_FCFG_B3_START_B3_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B3_START_B3_START_ADDR_S 0 //***************************************************************************** // @@ -3356,23 +3356,23 @@ // Field: [31:28] B4_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_W 4 -#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_S 28 +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_W 4 +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_S 28 // Field: [27:24] B4_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_W 4 -#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_S 24 +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_W 4 +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_S 24 // Field: [23:0] B4_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B4_START_B4_START_ADDR_W 24 -#define FLASH_FCFG_B4_START_B4_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B4_START_B4_START_ADDR_S 0 +#define FLASH_FCFG_B4_START_B4_START_ADDR_W 24 +#define FLASH_FCFG_B4_START_B4_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B4_START_B4_START_ADDR_S 0 //***************************************************************************** // @@ -3382,23 +3382,23 @@ // Field: [31:28] B5_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_W 4 -#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_S 28 +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_W 4 +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_S 28 // Field: [27:24] B5_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_W 4 -#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_S 24 +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_W 4 +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_S 24 // Field: [23:0] B5_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B5_START_B5_START_ADDR_W 24 -#define FLASH_FCFG_B5_START_B5_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B5_START_B5_START_ADDR_S 0 +#define FLASH_FCFG_B5_START_B5_START_ADDR_W 24 +#define FLASH_FCFG_B5_START_B5_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B5_START_B5_START_ADDR_S 0 //***************************************************************************** // @@ -3408,23 +3408,23 @@ // Field: [31:28] B6_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_W 4 -#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_S 28 +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_W 4 +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_S 28 // Field: [27:24] B6_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_W 4 -#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_S 24 +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_W 4 +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_S 24 // Field: [23:0] B6_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B6_START_B6_START_ADDR_W 24 -#define FLASH_FCFG_B6_START_B6_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B6_START_B6_START_ADDR_S 0 +#define FLASH_FCFG_B6_START_B6_START_ADDR_W 24 +#define FLASH_FCFG_B6_START_B6_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B6_START_B6_START_ADDR_S 0 //***************************************************************************** // @@ -3434,23 +3434,23 @@ // Field: [31:28] B7_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_W 4 -#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_S 28 +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_W 4 +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_S 28 // Field: [27:24] B7_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_W 4 -#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_S 24 +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_W 4 +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_S 24 // Field: [23:0] B7_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B7_START_B7_START_ADDR_W 24 -#define FLASH_FCFG_B7_START_B7_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B7_START_B7_START_ADDR_S 0 +#define FLASH_FCFG_B7_START_B7_START_ADDR_W 24 +#define FLASH_FCFG_B7_START_B7_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B7_START_B7_START_ADDR_S 0 //***************************************************************************** // @@ -3460,16 +3460,15 @@ // Field: [27:16] B0_NUM_SECTORS // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_W 12 -#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_M 0x0FFF0000 -#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_S 16 +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_W 12 +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_M 0x0FFF0000 +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_S 16 // Field: [3:0] B0_SECT_SIZE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_W 4 -#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M 0x0000000F -#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S 0 - +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_W 4 +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M 0x0000000F +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S 0 #endif // __FLASH__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_gpio.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_gpio.h index 98f51c9..e0603f1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_gpio.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_gpio.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_gpio_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_gpio_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_GPIO_H__ #define __HW_GPIO_H__ @@ -44,49 +44,49 @@ // //***************************************************************************** // Data Out 0 to 3 -#define GPIO_O_DOUT3_0 0x00000000 +#define GPIO_O_DOUT3_0 0x00000000 // Data Out 4 to 7 -#define GPIO_O_DOUT7_4 0x00000004 +#define GPIO_O_DOUT7_4 0x00000004 // Data Out 8 to 11 -#define GPIO_O_DOUT11_8 0x00000008 +#define GPIO_O_DOUT11_8 0x00000008 // Data Out 12 to 15 -#define GPIO_O_DOUT15_12 0x0000000C +#define GPIO_O_DOUT15_12 0x0000000C // Data Out 16 to 19 -#define GPIO_O_DOUT19_16 0x00000010 +#define GPIO_O_DOUT19_16 0x00000010 // Data Out 20 to 23 -#define GPIO_O_DOUT23_20 0x00000014 +#define GPIO_O_DOUT23_20 0x00000014 // Data Out 24 to 27 -#define GPIO_O_DOUT27_24 0x00000018 +#define GPIO_O_DOUT27_24 0x00000018 // Data Out 28 to 31 -#define GPIO_O_DOUT31_28 0x0000001C +#define GPIO_O_DOUT31_28 0x0000001C // Data Output for DIO 0 to 31 -#define GPIO_O_DOUT31_0 0x00000080 +#define GPIO_O_DOUT31_0 0x00000080 // Data Out Set -#define GPIO_O_DOUTSET31_0 0x00000090 +#define GPIO_O_DOUTSET31_0 0x00000090 // Data Out Clear -#define GPIO_O_DOUTCLR31_0 0x000000A0 +#define GPIO_O_DOUTCLR31_0 0x000000A0 // Data Out Toggle -#define GPIO_O_DOUTTGL31_0 0x000000B0 +#define GPIO_O_DOUTTGL31_0 0x000000B0 // Data Input from DIO 0 to 31 -#define GPIO_O_DIN31_0 0x000000C0 +#define GPIO_O_DIN31_0 0x000000C0 // Data Output Enable for DIO 0 to 31 -#define GPIO_O_DOE31_0 0x000000D0 +#define GPIO_O_DOE31_0 0x000000D0 // Event Register for DIO 0 to 31 -#define GPIO_O_EVFLAGS31_0 0x000000E0 +#define GPIO_O_EVFLAGS31_0 0x000000E0 //***************************************************************************** // @@ -97,37 +97,37 @@ // // Sets the state of the pin that is configured as DIO#3, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT3_0_DIO3 0x01000000 -#define GPIO_DOUT3_0_DIO3_BITN 24 -#define GPIO_DOUT3_0_DIO3_M 0x01000000 -#define GPIO_DOUT3_0_DIO3_S 24 +#define GPIO_DOUT3_0_DIO3 0x01000000 +#define GPIO_DOUT3_0_DIO3_BITN 24 +#define GPIO_DOUT3_0_DIO3_M 0x01000000 +#define GPIO_DOUT3_0_DIO3_S 24 // Field: [16] DIO2 // // Sets the state of the pin that is configured as DIO#2, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT3_0_DIO2 0x00010000 -#define GPIO_DOUT3_0_DIO2_BITN 16 -#define GPIO_DOUT3_0_DIO2_M 0x00010000 -#define GPIO_DOUT3_0_DIO2_S 16 +#define GPIO_DOUT3_0_DIO2 0x00010000 +#define GPIO_DOUT3_0_DIO2_BITN 16 +#define GPIO_DOUT3_0_DIO2_M 0x00010000 +#define GPIO_DOUT3_0_DIO2_S 16 // Field: [8] DIO1 // // Sets the state of the pin that is configured as DIO#1, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT3_0_DIO1 0x00000100 -#define GPIO_DOUT3_0_DIO1_BITN 8 -#define GPIO_DOUT3_0_DIO1_M 0x00000100 -#define GPIO_DOUT3_0_DIO1_S 8 +#define GPIO_DOUT3_0_DIO1 0x00000100 +#define GPIO_DOUT3_0_DIO1_BITN 8 +#define GPIO_DOUT3_0_DIO1_M 0x00000100 +#define GPIO_DOUT3_0_DIO1_S 8 // Field: [0] DIO0 // // Sets the state of the pin that is configured as DIO#0, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT3_0_DIO0 0x00000001 -#define GPIO_DOUT3_0_DIO0_BITN 0 -#define GPIO_DOUT3_0_DIO0_M 0x00000001 -#define GPIO_DOUT3_0_DIO0_S 0 +#define GPIO_DOUT3_0_DIO0 0x00000001 +#define GPIO_DOUT3_0_DIO0_BITN 0 +#define GPIO_DOUT3_0_DIO0_M 0x00000001 +#define GPIO_DOUT3_0_DIO0_S 0 //***************************************************************************** // @@ -138,37 +138,37 @@ // // Sets the state of the pin that is configured as DIO#7, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT7_4_DIO7 0x01000000 -#define GPIO_DOUT7_4_DIO7_BITN 24 -#define GPIO_DOUT7_4_DIO7_M 0x01000000 -#define GPIO_DOUT7_4_DIO7_S 24 +#define GPIO_DOUT7_4_DIO7 0x01000000 +#define GPIO_DOUT7_4_DIO7_BITN 24 +#define GPIO_DOUT7_4_DIO7_M 0x01000000 +#define GPIO_DOUT7_4_DIO7_S 24 // Field: [16] DIO6 // // Sets the state of the pin that is configured as DIO#6, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT7_4_DIO6 0x00010000 -#define GPIO_DOUT7_4_DIO6_BITN 16 -#define GPIO_DOUT7_4_DIO6_M 0x00010000 -#define GPIO_DOUT7_4_DIO6_S 16 +#define GPIO_DOUT7_4_DIO6 0x00010000 +#define GPIO_DOUT7_4_DIO6_BITN 16 +#define GPIO_DOUT7_4_DIO6_M 0x00010000 +#define GPIO_DOUT7_4_DIO6_S 16 // Field: [8] DIO5 // // Sets the state of the pin that is configured as DIO#5, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT7_4_DIO5 0x00000100 -#define GPIO_DOUT7_4_DIO5_BITN 8 -#define GPIO_DOUT7_4_DIO5_M 0x00000100 -#define GPIO_DOUT7_4_DIO5_S 8 +#define GPIO_DOUT7_4_DIO5 0x00000100 +#define GPIO_DOUT7_4_DIO5_BITN 8 +#define GPIO_DOUT7_4_DIO5_M 0x00000100 +#define GPIO_DOUT7_4_DIO5_S 8 // Field: [0] DIO4 // // Sets the state of the pin that is configured as DIO#4, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT7_4_DIO4 0x00000001 -#define GPIO_DOUT7_4_DIO4_BITN 0 -#define GPIO_DOUT7_4_DIO4_M 0x00000001 -#define GPIO_DOUT7_4_DIO4_S 0 +#define GPIO_DOUT7_4_DIO4 0x00000001 +#define GPIO_DOUT7_4_DIO4_BITN 0 +#define GPIO_DOUT7_4_DIO4_M 0x00000001 +#define GPIO_DOUT7_4_DIO4_S 0 //***************************************************************************** // @@ -179,37 +179,37 @@ // // Sets the state of the pin that is configured as DIO#11, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT11_8_DIO11 0x01000000 -#define GPIO_DOUT11_8_DIO11_BITN 24 -#define GPIO_DOUT11_8_DIO11_M 0x01000000 -#define GPIO_DOUT11_8_DIO11_S 24 +#define GPIO_DOUT11_8_DIO11 0x01000000 +#define GPIO_DOUT11_8_DIO11_BITN 24 +#define GPIO_DOUT11_8_DIO11_M 0x01000000 +#define GPIO_DOUT11_8_DIO11_S 24 // Field: [16] DIO10 // // Sets the state of the pin that is configured as DIO#10, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT11_8_DIO10 0x00010000 -#define GPIO_DOUT11_8_DIO10_BITN 16 -#define GPIO_DOUT11_8_DIO10_M 0x00010000 -#define GPIO_DOUT11_8_DIO10_S 16 +#define GPIO_DOUT11_8_DIO10 0x00010000 +#define GPIO_DOUT11_8_DIO10_BITN 16 +#define GPIO_DOUT11_8_DIO10_M 0x00010000 +#define GPIO_DOUT11_8_DIO10_S 16 // Field: [8] DIO9 // // Sets the state of the pin that is configured as DIO#9, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT11_8_DIO9 0x00000100 -#define GPIO_DOUT11_8_DIO9_BITN 8 -#define GPIO_DOUT11_8_DIO9_M 0x00000100 -#define GPIO_DOUT11_8_DIO9_S 8 +#define GPIO_DOUT11_8_DIO9 0x00000100 +#define GPIO_DOUT11_8_DIO9_BITN 8 +#define GPIO_DOUT11_8_DIO9_M 0x00000100 +#define GPIO_DOUT11_8_DIO9_S 8 // Field: [0] DIO8 // // Sets the state of the pin that is configured as DIO#8, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT11_8_DIO8 0x00000001 -#define GPIO_DOUT11_8_DIO8_BITN 0 -#define GPIO_DOUT11_8_DIO8_M 0x00000001 -#define GPIO_DOUT11_8_DIO8_S 0 +#define GPIO_DOUT11_8_DIO8 0x00000001 +#define GPIO_DOUT11_8_DIO8_BITN 0 +#define GPIO_DOUT11_8_DIO8_M 0x00000001 +#define GPIO_DOUT11_8_DIO8_S 0 //***************************************************************************** // @@ -220,37 +220,37 @@ // // Sets the state of the pin that is configured as DIO#15, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT15_12_DIO15 0x01000000 -#define GPIO_DOUT15_12_DIO15_BITN 24 -#define GPIO_DOUT15_12_DIO15_M 0x01000000 -#define GPIO_DOUT15_12_DIO15_S 24 +#define GPIO_DOUT15_12_DIO15 0x01000000 +#define GPIO_DOUT15_12_DIO15_BITN 24 +#define GPIO_DOUT15_12_DIO15_M 0x01000000 +#define GPIO_DOUT15_12_DIO15_S 24 // Field: [16] DIO14 // // Sets the state of the pin that is configured as DIO#14, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT15_12_DIO14 0x00010000 -#define GPIO_DOUT15_12_DIO14_BITN 16 -#define GPIO_DOUT15_12_DIO14_M 0x00010000 -#define GPIO_DOUT15_12_DIO14_S 16 +#define GPIO_DOUT15_12_DIO14 0x00010000 +#define GPIO_DOUT15_12_DIO14_BITN 16 +#define GPIO_DOUT15_12_DIO14_M 0x00010000 +#define GPIO_DOUT15_12_DIO14_S 16 // Field: [8] DIO13 // // Sets the state of the pin that is configured as DIO#13, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT15_12_DIO13 0x00000100 -#define GPIO_DOUT15_12_DIO13_BITN 8 -#define GPIO_DOUT15_12_DIO13_M 0x00000100 -#define GPIO_DOUT15_12_DIO13_S 8 +#define GPIO_DOUT15_12_DIO13 0x00000100 +#define GPIO_DOUT15_12_DIO13_BITN 8 +#define GPIO_DOUT15_12_DIO13_M 0x00000100 +#define GPIO_DOUT15_12_DIO13_S 8 // Field: [0] DIO12 // // Sets the state of the pin that is configured as DIO#12, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT15_12_DIO12 0x00000001 -#define GPIO_DOUT15_12_DIO12_BITN 0 -#define GPIO_DOUT15_12_DIO12_M 0x00000001 -#define GPIO_DOUT15_12_DIO12_S 0 +#define GPIO_DOUT15_12_DIO12 0x00000001 +#define GPIO_DOUT15_12_DIO12_BITN 0 +#define GPIO_DOUT15_12_DIO12_M 0x00000001 +#define GPIO_DOUT15_12_DIO12_S 0 //***************************************************************************** // @@ -261,37 +261,37 @@ // // Sets the state of the pin that is configured as DIO#19, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT19_16_DIO19 0x01000000 -#define GPIO_DOUT19_16_DIO19_BITN 24 -#define GPIO_DOUT19_16_DIO19_M 0x01000000 -#define GPIO_DOUT19_16_DIO19_S 24 +#define GPIO_DOUT19_16_DIO19 0x01000000 +#define GPIO_DOUT19_16_DIO19_BITN 24 +#define GPIO_DOUT19_16_DIO19_M 0x01000000 +#define GPIO_DOUT19_16_DIO19_S 24 // Field: [16] DIO18 // // Sets the state of the pin that is configured as DIO#18, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT19_16_DIO18 0x00010000 -#define GPIO_DOUT19_16_DIO18_BITN 16 -#define GPIO_DOUT19_16_DIO18_M 0x00010000 -#define GPIO_DOUT19_16_DIO18_S 16 +#define GPIO_DOUT19_16_DIO18 0x00010000 +#define GPIO_DOUT19_16_DIO18_BITN 16 +#define GPIO_DOUT19_16_DIO18_M 0x00010000 +#define GPIO_DOUT19_16_DIO18_S 16 // Field: [8] DIO17 // // Sets the state of the pin that is configured as DIO#17, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT19_16_DIO17 0x00000100 -#define GPIO_DOUT19_16_DIO17_BITN 8 -#define GPIO_DOUT19_16_DIO17_M 0x00000100 -#define GPIO_DOUT19_16_DIO17_S 8 +#define GPIO_DOUT19_16_DIO17 0x00000100 +#define GPIO_DOUT19_16_DIO17_BITN 8 +#define GPIO_DOUT19_16_DIO17_M 0x00000100 +#define GPIO_DOUT19_16_DIO17_S 8 // Field: [0] DIO16 // // Sets the state of the pin that is configured as DIO#16, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT19_16_DIO16 0x00000001 -#define GPIO_DOUT19_16_DIO16_BITN 0 -#define GPIO_DOUT19_16_DIO16_M 0x00000001 -#define GPIO_DOUT19_16_DIO16_S 0 +#define GPIO_DOUT19_16_DIO16 0x00000001 +#define GPIO_DOUT19_16_DIO16_BITN 0 +#define GPIO_DOUT19_16_DIO16_M 0x00000001 +#define GPIO_DOUT19_16_DIO16_S 0 //***************************************************************************** // @@ -302,37 +302,37 @@ // // Sets the state of the pin that is configured as DIO#23, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT23_20_DIO23 0x01000000 -#define GPIO_DOUT23_20_DIO23_BITN 24 -#define GPIO_DOUT23_20_DIO23_M 0x01000000 -#define GPIO_DOUT23_20_DIO23_S 24 +#define GPIO_DOUT23_20_DIO23 0x01000000 +#define GPIO_DOUT23_20_DIO23_BITN 24 +#define GPIO_DOUT23_20_DIO23_M 0x01000000 +#define GPIO_DOUT23_20_DIO23_S 24 // Field: [16] DIO22 // // Sets the state of the pin that is configured as DIO#22, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT23_20_DIO22 0x00010000 -#define GPIO_DOUT23_20_DIO22_BITN 16 -#define GPIO_DOUT23_20_DIO22_M 0x00010000 -#define GPIO_DOUT23_20_DIO22_S 16 +#define GPIO_DOUT23_20_DIO22 0x00010000 +#define GPIO_DOUT23_20_DIO22_BITN 16 +#define GPIO_DOUT23_20_DIO22_M 0x00010000 +#define GPIO_DOUT23_20_DIO22_S 16 // Field: [8] DIO21 // // Sets the state of the pin that is configured as DIO#21, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT23_20_DIO21 0x00000100 -#define GPIO_DOUT23_20_DIO21_BITN 8 -#define GPIO_DOUT23_20_DIO21_M 0x00000100 -#define GPIO_DOUT23_20_DIO21_S 8 +#define GPIO_DOUT23_20_DIO21 0x00000100 +#define GPIO_DOUT23_20_DIO21_BITN 8 +#define GPIO_DOUT23_20_DIO21_M 0x00000100 +#define GPIO_DOUT23_20_DIO21_S 8 // Field: [0] DIO20 // // Sets the state of the pin that is configured as DIO#20, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT23_20_DIO20 0x00000001 -#define GPIO_DOUT23_20_DIO20_BITN 0 -#define GPIO_DOUT23_20_DIO20_M 0x00000001 -#define GPIO_DOUT23_20_DIO20_S 0 +#define GPIO_DOUT23_20_DIO20 0x00000001 +#define GPIO_DOUT23_20_DIO20_BITN 0 +#define GPIO_DOUT23_20_DIO20_M 0x00000001 +#define GPIO_DOUT23_20_DIO20_S 0 //***************************************************************************** // @@ -343,37 +343,37 @@ // // Sets the state of the pin that is configured as DIO#27, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT27_24_DIO27 0x01000000 -#define GPIO_DOUT27_24_DIO27_BITN 24 -#define GPIO_DOUT27_24_DIO27_M 0x01000000 -#define GPIO_DOUT27_24_DIO27_S 24 +#define GPIO_DOUT27_24_DIO27 0x01000000 +#define GPIO_DOUT27_24_DIO27_BITN 24 +#define GPIO_DOUT27_24_DIO27_M 0x01000000 +#define GPIO_DOUT27_24_DIO27_S 24 // Field: [16] DIO26 // // Sets the state of the pin that is configured as DIO#26, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT27_24_DIO26 0x00010000 -#define GPIO_DOUT27_24_DIO26_BITN 16 -#define GPIO_DOUT27_24_DIO26_M 0x00010000 -#define GPIO_DOUT27_24_DIO26_S 16 +#define GPIO_DOUT27_24_DIO26 0x00010000 +#define GPIO_DOUT27_24_DIO26_BITN 16 +#define GPIO_DOUT27_24_DIO26_M 0x00010000 +#define GPIO_DOUT27_24_DIO26_S 16 // Field: [8] DIO25 // // Sets the state of the pin that is configured as DIO#25, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT27_24_DIO25 0x00000100 -#define GPIO_DOUT27_24_DIO25_BITN 8 -#define GPIO_DOUT27_24_DIO25_M 0x00000100 -#define GPIO_DOUT27_24_DIO25_S 8 +#define GPIO_DOUT27_24_DIO25 0x00000100 +#define GPIO_DOUT27_24_DIO25_BITN 8 +#define GPIO_DOUT27_24_DIO25_M 0x00000100 +#define GPIO_DOUT27_24_DIO25_S 8 // Field: [0] DIO24 // // Sets the state of the pin that is configured as DIO#24, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT27_24_DIO24 0x00000001 -#define GPIO_DOUT27_24_DIO24_BITN 0 -#define GPIO_DOUT27_24_DIO24_M 0x00000001 -#define GPIO_DOUT27_24_DIO24_S 0 +#define GPIO_DOUT27_24_DIO24 0x00000001 +#define GPIO_DOUT27_24_DIO24_BITN 0 +#define GPIO_DOUT27_24_DIO24_M 0x00000001 +#define GPIO_DOUT27_24_DIO24_S 0 //***************************************************************************** // @@ -384,37 +384,37 @@ // // Sets the state of the pin that is configured as DIO#31, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT31_28_DIO31 0x01000000 -#define GPIO_DOUT31_28_DIO31_BITN 24 -#define GPIO_DOUT31_28_DIO31_M 0x01000000 -#define GPIO_DOUT31_28_DIO31_S 24 +#define GPIO_DOUT31_28_DIO31 0x01000000 +#define GPIO_DOUT31_28_DIO31_BITN 24 +#define GPIO_DOUT31_28_DIO31_M 0x01000000 +#define GPIO_DOUT31_28_DIO31_S 24 // Field: [16] DIO30 // // Sets the state of the pin that is configured as DIO#30, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT31_28_DIO30 0x00010000 -#define GPIO_DOUT31_28_DIO30_BITN 16 -#define GPIO_DOUT31_28_DIO30_M 0x00010000 -#define GPIO_DOUT31_28_DIO30_S 16 +#define GPIO_DOUT31_28_DIO30 0x00010000 +#define GPIO_DOUT31_28_DIO30_BITN 16 +#define GPIO_DOUT31_28_DIO30_M 0x00010000 +#define GPIO_DOUT31_28_DIO30_S 16 // Field: [8] DIO29 // // Sets the state of the pin that is configured as DIO#29, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT31_28_DIO29 0x00000100 -#define GPIO_DOUT31_28_DIO29_BITN 8 -#define GPIO_DOUT31_28_DIO29_M 0x00000100 -#define GPIO_DOUT31_28_DIO29_S 8 +#define GPIO_DOUT31_28_DIO29 0x00000100 +#define GPIO_DOUT31_28_DIO29_BITN 8 +#define GPIO_DOUT31_28_DIO29_M 0x00000100 +#define GPIO_DOUT31_28_DIO29_S 8 // Field: [0] DIO28 // // Sets the state of the pin that is configured as DIO#28, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT31_28_DIO28 0x00000001 -#define GPIO_DOUT31_28_DIO28_BITN 0 -#define GPIO_DOUT31_28_DIO28_M 0x00000001 -#define GPIO_DOUT31_28_DIO28_S 0 +#define GPIO_DOUT31_28_DIO28 0x00000001 +#define GPIO_DOUT31_28_DIO28_BITN 0 +#define GPIO_DOUT31_28_DIO28_M 0x00000001 +#define GPIO_DOUT31_28_DIO28_S 0 //***************************************************************************** // @@ -424,258 +424,258 @@ // Field: [31] DIO31 // // Data output for DIO 31 -#define GPIO_DOUT31_0_DIO31 0x80000000 -#define GPIO_DOUT31_0_DIO31_BITN 31 -#define GPIO_DOUT31_0_DIO31_M 0x80000000 -#define GPIO_DOUT31_0_DIO31_S 31 +#define GPIO_DOUT31_0_DIO31 0x80000000 +#define GPIO_DOUT31_0_DIO31_BITN 31 +#define GPIO_DOUT31_0_DIO31_M 0x80000000 +#define GPIO_DOUT31_0_DIO31_S 31 // Field: [30] DIO30 // // Data output for DIO 30 -#define GPIO_DOUT31_0_DIO30 0x40000000 -#define GPIO_DOUT31_0_DIO30_BITN 30 -#define GPIO_DOUT31_0_DIO30_M 0x40000000 -#define GPIO_DOUT31_0_DIO30_S 30 +#define GPIO_DOUT31_0_DIO30 0x40000000 +#define GPIO_DOUT31_0_DIO30_BITN 30 +#define GPIO_DOUT31_0_DIO30_M 0x40000000 +#define GPIO_DOUT31_0_DIO30_S 30 // Field: [29] DIO29 // // Data output for DIO 29 -#define GPIO_DOUT31_0_DIO29 0x20000000 -#define GPIO_DOUT31_0_DIO29_BITN 29 -#define GPIO_DOUT31_0_DIO29_M 0x20000000 -#define GPIO_DOUT31_0_DIO29_S 29 +#define GPIO_DOUT31_0_DIO29 0x20000000 +#define GPIO_DOUT31_0_DIO29_BITN 29 +#define GPIO_DOUT31_0_DIO29_M 0x20000000 +#define GPIO_DOUT31_0_DIO29_S 29 // Field: [28] DIO28 // // Data output for DIO 28 -#define GPIO_DOUT31_0_DIO28 0x10000000 -#define GPIO_DOUT31_0_DIO28_BITN 28 -#define GPIO_DOUT31_0_DIO28_M 0x10000000 -#define GPIO_DOUT31_0_DIO28_S 28 +#define GPIO_DOUT31_0_DIO28 0x10000000 +#define GPIO_DOUT31_0_DIO28_BITN 28 +#define GPIO_DOUT31_0_DIO28_M 0x10000000 +#define GPIO_DOUT31_0_DIO28_S 28 // Field: [27] DIO27 // // Data output for DIO 27 -#define GPIO_DOUT31_0_DIO27 0x08000000 -#define GPIO_DOUT31_0_DIO27_BITN 27 -#define GPIO_DOUT31_0_DIO27_M 0x08000000 -#define GPIO_DOUT31_0_DIO27_S 27 +#define GPIO_DOUT31_0_DIO27 0x08000000 +#define GPIO_DOUT31_0_DIO27_BITN 27 +#define GPIO_DOUT31_0_DIO27_M 0x08000000 +#define GPIO_DOUT31_0_DIO27_S 27 // Field: [26] DIO26 // // Data output for DIO 26 -#define GPIO_DOUT31_0_DIO26 0x04000000 -#define GPIO_DOUT31_0_DIO26_BITN 26 -#define GPIO_DOUT31_0_DIO26_M 0x04000000 -#define GPIO_DOUT31_0_DIO26_S 26 +#define GPIO_DOUT31_0_DIO26 0x04000000 +#define GPIO_DOUT31_0_DIO26_BITN 26 +#define GPIO_DOUT31_0_DIO26_M 0x04000000 +#define GPIO_DOUT31_0_DIO26_S 26 // Field: [25] DIO25 // // Data output for DIO 25 -#define GPIO_DOUT31_0_DIO25 0x02000000 -#define GPIO_DOUT31_0_DIO25_BITN 25 -#define GPIO_DOUT31_0_DIO25_M 0x02000000 -#define GPIO_DOUT31_0_DIO25_S 25 +#define GPIO_DOUT31_0_DIO25 0x02000000 +#define GPIO_DOUT31_0_DIO25_BITN 25 +#define GPIO_DOUT31_0_DIO25_M 0x02000000 +#define GPIO_DOUT31_0_DIO25_S 25 // Field: [24] DIO24 // // Data output for DIO 24 -#define GPIO_DOUT31_0_DIO24 0x01000000 -#define GPIO_DOUT31_0_DIO24_BITN 24 -#define GPIO_DOUT31_0_DIO24_M 0x01000000 -#define GPIO_DOUT31_0_DIO24_S 24 +#define GPIO_DOUT31_0_DIO24 0x01000000 +#define GPIO_DOUT31_0_DIO24_BITN 24 +#define GPIO_DOUT31_0_DIO24_M 0x01000000 +#define GPIO_DOUT31_0_DIO24_S 24 // Field: [23] DIO23 // // Data output for DIO 23 -#define GPIO_DOUT31_0_DIO23 0x00800000 -#define GPIO_DOUT31_0_DIO23_BITN 23 -#define GPIO_DOUT31_0_DIO23_M 0x00800000 -#define GPIO_DOUT31_0_DIO23_S 23 +#define GPIO_DOUT31_0_DIO23 0x00800000 +#define GPIO_DOUT31_0_DIO23_BITN 23 +#define GPIO_DOUT31_0_DIO23_M 0x00800000 +#define GPIO_DOUT31_0_DIO23_S 23 // Field: [22] DIO22 // // Data output for DIO 22 -#define GPIO_DOUT31_0_DIO22 0x00400000 -#define GPIO_DOUT31_0_DIO22_BITN 22 -#define GPIO_DOUT31_0_DIO22_M 0x00400000 -#define GPIO_DOUT31_0_DIO22_S 22 +#define GPIO_DOUT31_0_DIO22 0x00400000 +#define GPIO_DOUT31_0_DIO22_BITN 22 +#define GPIO_DOUT31_0_DIO22_M 0x00400000 +#define GPIO_DOUT31_0_DIO22_S 22 // Field: [21] DIO21 // // Data output for DIO 21 -#define GPIO_DOUT31_0_DIO21 0x00200000 -#define GPIO_DOUT31_0_DIO21_BITN 21 -#define GPIO_DOUT31_0_DIO21_M 0x00200000 -#define GPIO_DOUT31_0_DIO21_S 21 +#define GPIO_DOUT31_0_DIO21 0x00200000 +#define GPIO_DOUT31_0_DIO21_BITN 21 +#define GPIO_DOUT31_0_DIO21_M 0x00200000 +#define GPIO_DOUT31_0_DIO21_S 21 // Field: [20] DIO20 // // Data output for DIO 20 -#define GPIO_DOUT31_0_DIO20 0x00100000 -#define GPIO_DOUT31_0_DIO20_BITN 20 -#define GPIO_DOUT31_0_DIO20_M 0x00100000 -#define GPIO_DOUT31_0_DIO20_S 20 +#define GPIO_DOUT31_0_DIO20 0x00100000 +#define GPIO_DOUT31_0_DIO20_BITN 20 +#define GPIO_DOUT31_0_DIO20_M 0x00100000 +#define GPIO_DOUT31_0_DIO20_S 20 // Field: [19] DIO19 // // Data output for DIO 19 -#define GPIO_DOUT31_0_DIO19 0x00080000 -#define GPIO_DOUT31_0_DIO19_BITN 19 -#define GPIO_DOUT31_0_DIO19_M 0x00080000 -#define GPIO_DOUT31_0_DIO19_S 19 +#define GPIO_DOUT31_0_DIO19 0x00080000 +#define GPIO_DOUT31_0_DIO19_BITN 19 +#define GPIO_DOUT31_0_DIO19_M 0x00080000 +#define GPIO_DOUT31_0_DIO19_S 19 // Field: [18] DIO18 // // Data output for DIO 18 -#define GPIO_DOUT31_0_DIO18 0x00040000 -#define GPIO_DOUT31_0_DIO18_BITN 18 -#define GPIO_DOUT31_0_DIO18_M 0x00040000 -#define GPIO_DOUT31_0_DIO18_S 18 +#define GPIO_DOUT31_0_DIO18 0x00040000 +#define GPIO_DOUT31_0_DIO18_BITN 18 +#define GPIO_DOUT31_0_DIO18_M 0x00040000 +#define GPIO_DOUT31_0_DIO18_S 18 // Field: [17] DIO17 // // Data output for DIO 17 -#define GPIO_DOUT31_0_DIO17 0x00020000 -#define GPIO_DOUT31_0_DIO17_BITN 17 -#define GPIO_DOUT31_0_DIO17_M 0x00020000 -#define GPIO_DOUT31_0_DIO17_S 17 +#define GPIO_DOUT31_0_DIO17 0x00020000 +#define GPIO_DOUT31_0_DIO17_BITN 17 +#define GPIO_DOUT31_0_DIO17_M 0x00020000 +#define GPIO_DOUT31_0_DIO17_S 17 // Field: [16] DIO16 // // Data output for DIO 16 -#define GPIO_DOUT31_0_DIO16 0x00010000 -#define GPIO_DOUT31_0_DIO16_BITN 16 -#define GPIO_DOUT31_0_DIO16_M 0x00010000 -#define GPIO_DOUT31_0_DIO16_S 16 +#define GPIO_DOUT31_0_DIO16 0x00010000 +#define GPIO_DOUT31_0_DIO16_BITN 16 +#define GPIO_DOUT31_0_DIO16_M 0x00010000 +#define GPIO_DOUT31_0_DIO16_S 16 // Field: [15] DIO15 // // Data output for DIO 15 -#define GPIO_DOUT31_0_DIO15 0x00008000 -#define GPIO_DOUT31_0_DIO15_BITN 15 -#define GPIO_DOUT31_0_DIO15_M 0x00008000 -#define GPIO_DOUT31_0_DIO15_S 15 +#define GPIO_DOUT31_0_DIO15 0x00008000 +#define GPIO_DOUT31_0_DIO15_BITN 15 +#define GPIO_DOUT31_0_DIO15_M 0x00008000 +#define GPIO_DOUT31_0_DIO15_S 15 // Field: [14] DIO14 // // Data output for DIO 14 -#define GPIO_DOUT31_0_DIO14 0x00004000 -#define GPIO_DOUT31_0_DIO14_BITN 14 -#define GPIO_DOUT31_0_DIO14_M 0x00004000 -#define GPIO_DOUT31_0_DIO14_S 14 +#define GPIO_DOUT31_0_DIO14 0x00004000 +#define GPIO_DOUT31_0_DIO14_BITN 14 +#define GPIO_DOUT31_0_DIO14_M 0x00004000 +#define GPIO_DOUT31_0_DIO14_S 14 // Field: [13] DIO13 // // Data output for DIO 13 -#define GPIO_DOUT31_0_DIO13 0x00002000 -#define GPIO_DOUT31_0_DIO13_BITN 13 -#define GPIO_DOUT31_0_DIO13_M 0x00002000 -#define GPIO_DOUT31_0_DIO13_S 13 +#define GPIO_DOUT31_0_DIO13 0x00002000 +#define GPIO_DOUT31_0_DIO13_BITN 13 +#define GPIO_DOUT31_0_DIO13_M 0x00002000 +#define GPIO_DOUT31_0_DIO13_S 13 // Field: [12] DIO12 // // Data output for DIO 12 -#define GPIO_DOUT31_0_DIO12 0x00001000 -#define GPIO_DOUT31_0_DIO12_BITN 12 -#define GPIO_DOUT31_0_DIO12_M 0x00001000 -#define GPIO_DOUT31_0_DIO12_S 12 +#define GPIO_DOUT31_0_DIO12 0x00001000 +#define GPIO_DOUT31_0_DIO12_BITN 12 +#define GPIO_DOUT31_0_DIO12_M 0x00001000 +#define GPIO_DOUT31_0_DIO12_S 12 // Field: [11] DIO11 // // Data output for DIO 11 -#define GPIO_DOUT31_0_DIO11 0x00000800 -#define GPIO_DOUT31_0_DIO11_BITN 11 -#define GPIO_DOUT31_0_DIO11_M 0x00000800 -#define GPIO_DOUT31_0_DIO11_S 11 +#define GPIO_DOUT31_0_DIO11 0x00000800 +#define GPIO_DOUT31_0_DIO11_BITN 11 +#define GPIO_DOUT31_0_DIO11_M 0x00000800 +#define GPIO_DOUT31_0_DIO11_S 11 // Field: [10] DIO10 // // Data output for DIO 10 -#define GPIO_DOUT31_0_DIO10 0x00000400 -#define GPIO_DOUT31_0_DIO10_BITN 10 -#define GPIO_DOUT31_0_DIO10_M 0x00000400 -#define GPIO_DOUT31_0_DIO10_S 10 +#define GPIO_DOUT31_0_DIO10 0x00000400 +#define GPIO_DOUT31_0_DIO10_BITN 10 +#define GPIO_DOUT31_0_DIO10_M 0x00000400 +#define GPIO_DOUT31_0_DIO10_S 10 // Field: [9] DIO9 // // Data output for DIO 9 -#define GPIO_DOUT31_0_DIO9 0x00000200 -#define GPIO_DOUT31_0_DIO9_BITN 9 -#define GPIO_DOUT31_0_DIO9_M 0x00000200 -#define GPIO_DOUT31_0_DIO9_S 9 +#define GPIO_DOUT31_0_DIO9 0x00000200 +#define GPIO_DOUT31_0_DIO9_BITN 9 +#define GPIO_DOUT31_0_DIO9_M 0x00000200 +#define GPIO_DOUT31_0_DIO9_S 9 // Field: [8] DIO8 // // Data output for DIO 8 -#define GPIO_DOUT31_0_DIO8 0x00000100 -#define GPIO_DOUT31_0_DIO8_BITN 8 -#define GPIO_DOUT31_0_DIO8_M 0x00000100 -#define GPIO_DOUT31_0_DIO8_S 8 +#define GPIO_DOUT31_0_DIO8 0x00000100 +#define GPIO_DOUT31_0_DIO8_BITN 8 +#define GPIO_DOUT31_0_DIO8_M 0x00000100 +#define GPIO_DOUT31_0_DIO8_S 8 // Field: [7] DIO7 // // Data output for DIO 7 -#define GPIO_DOUT31_0_DIO7 0x00000080 -#define GPIO_DOUT31_0_DIO7_BITN 7 -#define GPIO_DOUT31_0_DIO7_M 0x00000080 -#define GPIO_DOUT31_0_DIO7_S 7 +#define GPIO_DOUT31_0_DIO7 0x00000080 +#define GPIO_DOUT31_0_DIO7_BITN 7 +#define GPIO_DOUT31_0_DIO7_M 0x00000080 +#define GPIO_DOUT31_0_DIO7_S 7 // Field: [6] DIO6 // // Data output for DIO 6 -#define GPIO_DOUT31_0_DIO6 0x00000040 -#define GPIO_DOUT31_0_DIO6_BITN 6 -#define GPIO_DOUT31_0_DIO6_M 0x00000040 -#define GPIO_DOUT31_0_DIO6_S 6 +#define GPIO_DOUT31_0_DIO6 0x00000040 +#define GPIO_DOUT31_0_DIO6_BITN 6 +#define GPIO_DOUT31_0_DIO6_M 0x00000040 +#define GPIO_DOUT31_0_DIO6_S 6 // Field: [5] DIO5 // // Data output for DIO 5 -#define GPIO_DOUT31_0_DIO5 0x00000020 -#define GPIO_DOUT31_0_DIO5_BITN 5 -#define GPIO_DOUT31_0_DIO5_M 0x00000020 -#define GPIO_DOUT31_0_DIO5_S 5 +#define GPIO_DOUT31_0_DIO5 0x00000020 +#define GPIO_DOUT31_0_DIO5_BITN 5 +#define GPIO_DOUT31_0_DIO5_M 0x00000020 +#define GPIO_DOUT31_0_DIO5_S 5 // Field: [4] DIO4 // // Data output for DIO 4 -#define GPIO_DOUT31_0_DIO4 0x00000010 -#define GPIO_DOUT31_0_DIO4_BITN 4 -#define GPIO_DOUT31_0_DIO4_M 0x00000010 -#define GPIO_DOUT31_0_DIO4_S 4 +#define GPIO_DOUT31_0_DIO4 0x00000010 +#define GPIO_DOUT31_0_DIO4_BITN 4 +#define GPIO_DOUT31_0_DIO4_M 0x00000010 +#define GPIO_DOUT31_0_DIO4_S 4 // Field: [3] DIO3 // // Data output for DIO 3 -#define GPIO_DOUT31_0_DIO3 0x00000008 -#define GPIO_DOUT31_0_DIO3_BITN 3 -#define GPIO_DOUT31_0_DIO3_M 0x00000008 -#define GPIO_DOUT31_0_DIO3_S 3 +#define GPIO_DOUT31_0_DIO3 0x00000008 +#define GPIO_DOUT31_0_DIO3_BITN 3 +#define GPIO_DOUT31_0_DIO3_M 0x00000008 +#define GPIO_DOUT31_0_DIO3_S 3 // Field: [2] DIO2 // // Data output for DIO 2 -#define GPIO_DOUT31_0_DIO2 0x00000004 -#define GPIO_DOUT31_0_DIO2_BITN 2 -#define GPIO_DOUT31_0_DIO2_M 0x00000004 -#define GPIO_DOUT31_0_DIO2_S 2 +#define GPIO_DOUT31_0_DIO2 0x00000004 +#define GPIO_DOUT31_0_DIO2_BITN 2 +#define GPIO_DOUT31_0_DIO2_M 0x00000004 +#define GPIO_DOUT31_0_DIO2_S 2 // Field: [1] DIO1 // // Data output for DIO 1 -#define GPIO_DOUT31_0_DIO1 0x00000002 -#define GPIO_DOUT31_0_DIO1_BITN 1 -#define GPIO_DOUT31_0_DIO1_M 0x00000002 -#define GPIO_DOUT31_0_DIO1_S 1 +#define GPIO_DOUT31_0_DIO1 0x00000002 +#define GPIO_DOUT31_0_DIO1_BITN 1 +#define GPIO_DOUT31_0_DIO1_M 0x00000002 +#define GPIO_DOUT31_0_DIO1_S 1 // Field: [0] DIO0 // // Data output for DIO 0 -#define GPIO_DOUT31_0_DIO0 0x00000001 -#define GPIO_DOUT31_0_DIO0_BITN 0 -#define GPIO_DOUT31_0_DIO0_M 0x00000001 -#define GPIO_DOUT31_0_DIO0_S 0 +#define GPIO_DOUT31_0_DIO0 0x00000001 +#define GPIO_DOUT31_0_DIO0_BITN 0 +#define GPIO_DOUT31_0_DIO0_M 0x00000001 +#define GPIO_DOUT31_0_DIO0_S 0 //***************************************************************************** // @@ -685,258 +685,258 @@ // Field: [31] DIO31 // // Set bit 31 -#define GPIO_DOUTSET31_0_DIO31 0x80000000 -#define GPIO_DOUTSET31_0_DIO31_BITN 31 -#define GPIO_DOUTSET31_0_DIO31_M 0x80000000 -#define GPIO_DOUTSET31_0_DIO31_S 31 +#define GPIO_DOUTSET31_0_DIO31 0x80000000 +#define GPIO_DOUTSET31_0_DIO31_BITN 31 +#define GPIO_DOUTSET31_0_DIO31_M 0x80000000 +#define GPIO_DOUTSET31_0_DIO31_S 31 // Field: [30] DIO30 // // Set bit 30 -#define GPIO_DOUTSET31_0_DIO30 0x40000000 -#define GPIO_DOUTSET31_0_DIO30_BITN 30 -#define GPIO_DOUTSET31_0_DIO30_M 0x40000000 -#define GPIO_DOUTSET31_0_DIO30_S 30 +#define GPIO_DOUTSET31_0_DIO30 0x40000000 +#define GPIO_DOUTSET31_0_DIO30_BITN 30 +#define GPIO_DOUTSET31_0_DIO30_M 0x40000000 +#define GPIO_DOUTSET31_0_DIO30_S 30 // Field: [29] DIO29 // // Set bit 29 -#define GPIO_DOUTSET31_0_DIO29 0x20000000 -#define GPIO_DOUTSET31_0_DIO29_BITN 29 -#define GPIO_DOUTSET31_0_DIO29_M 0x20000000 -#define GPIO_DOUTSET31_0_DIO29_S 29 +#define GPIO_DOUTSET31_0_DIO29 0x20000000 +#define GPIO_DOUTSET31_0_DIO29_BITN 29 +#define GPIO_DOUTSET31_0_DIO29_M 0x20000000 +#define GPIO_DOUTSET31_0_DIO29_S 29 // Field: [28] DIO28 // // Set bit 28 -#define GPIO_DOUTSET31_0_DIO28 0x10000000 -#define GPIO_DOUTSET31_0_DIO28_BITN 28 -#define GPIO_DOUTSET31_0_DIO28_M 0x10000000 -#define GPIO_DOUTSET31_0_DIO28_S 28 +#define GPIO_DOUTSET31_0_DIO28 0x10000000 +#define GPIO_DOUTSET31_0_DIO28_BITN 28 +#define GPIO_DOUTSET31_0_DIO28_M 0x10000000 +#define GPIO_DOUTSET31_0_DIO28_S 28 // Field: [27] DIO27 // // Set bit 27 -#define GPIO_DOUTSET31_0_DIO27 0x08000000 -#define GPIO_DOUTSET31_0_DIO27_BITN 27 -#define GPIO_DOUTSET31_0_DIO27_M 0x08000000 -#define GPIO_DOUTSET31_0_DIO27_S 27 +#define GPIO_DOUTSET31_0_DIO27 0x08000000 +#define GPIO_DOUTSET31_0_DIO27_BITN 27 +#define GPIO_DOUTSET31_0_DIO27_M 0x08000000 +#define GPIO_DOUTSET31_0_DIO27_S 27 // Field: [26] DIO26 // // Set bit 26 -#define GPIO_DOUTSET31_0_DIO26 0x04000000 -#define GPIO_DOUTSET31_0_DIO26_BITN 26 -#define GPIO_DOUTSET31_0_DIO26_M 0x04000000 -#define GPIO_DOUTSET31_0_DIO26_S 26 +#define GPIO_DOUTSET31_0_DIO26 0x04000000 +#define GPIO_DOUTSET31_0_DIO26_BITN 26 +#define GPIO_DOUTSET31_0_DIO26_M 0x04000000 +#define GPIO_DOUTSET31_0_DIO26_S 26 // Field: [25] DIO25 // // Set bit 25 -#define GPIO_DOUTSET31_0_DIO25 0x02000000 -#define GPIO_DOUTSET31_0_DIO25_BITN 25 -#define GPIO_DOUTSET31_0_DIO25_M 0x02000000 -#define GPIO_DOUTSET31_0_DIO25_S 25 +#define GPIO_DOUTSET31_0_DIO25 0x02000000 +#define GPIO_DOUTSET31_0_DIO25_BITN 25 +#define GPIO_DOUTSET31_0_DIO25_M 0x02000000 +#define GPIO_DOUTSET31_0_DIO25_S 25 // Field: [24] DIO24 // // Set bit 24 -#define GPIO_DOUTSET31_0_DIO24 0x01000000 -#define GPIO_DOUTSET31_0_DIO24_BITN 24 -#define GPIO_DOUTSET31_0_DIO24_M 0x01000000 -#define GPIO_DOUTSET31_0_DIO24_S 24 +#define GPIO_DOUTSET31_0_DIO24 0x01000000 +#define GPIO_DOUTSET31_0_DIO24_BITN 24 +#define GPIO_DOUTSET31_0_DIO24_M 0x01000000 +#define GPIO_DOUTSET31_0_DIO24_S 24 // Field: [23] DIO23 // // Set bit 23 -#define GPIO_DOUTSET31_0_DIO23 0x00800000 -#define GPIO_DOUTSET31_0_DIO23_BITN 23 -#define GPIO_DOUTSET31_0_DIO23_M 0x00800000 -#define GPIO_DOUTSET31_0_DIO23_S 23 +#define GPIO_DOUTSET31_0_DIO23 0x00800000 +#define GPIO_DOUTSET31_0_DIO23_BITN 23 +#define GPIO_DOUTSET31_0_DIO23_M 0x00800000 +#define GPIO_DOUTSET31_0_DIO23_S 23 // Field: [22] DIO22 // // Set bit 22 -#define GPIO_DOUTSET31_0_DIO22 0x00400000 -#define GPIO_DOUTSET31_0_DIO22_BITN 22 -#define GPIO_DOUTSET31_0_DIO22_M 0x00400000 -#define GPIO_DOUTSET31_0_DIO22_S 22 +#define GPIO_DOUTSET31_0_DIO22 0x00400000 +#define GPIO_DOUTSET31_0_DIO22_BITN 22 +#define GPIO_DOUTSET31_0_DIO22_M 0x00400000 +#define GPIO_DOUTSET31_0_DIO22_S 22 // Field: [21] DIO21 // // Set bit 21 -#define GPIO_DOUTSET31_0_DIO21 0x00200000 -#define GPIO_DOUTSET31_0_DIO21_BITN 21 -#define GPIO_DOUTSET31_0_DIO21_M 0x00200000 -#define GPIO_DOUTSET31_0_DIO21_S 21 +#define GPIO_DOUTSET31_0_DIO21 0x00200000 +#define GPIO_DOUTSET31_0_DIO21_BITN 21 +#define GPIO_DOUTSET31_0_DIO21_M 0x00200000 +#define GPIO_DOUTSET31_0_DIO21_S 21 // Field: [20] DIO20 // // Set bit 20 -#define GPIO_DOUTSET31_0_DIO20 0x00100000 -#define GPIO_DOUTSET31_0_DIO20_BITN 20 -#define GPIO_DOUTSET31_0_DIO20_M 0x00100000 -#define GPIO_DOUTSET31_0_DIO20_S 20 +#define GPIO_DOUTSET31_0_DIO20 0x00100000 +#define GPIO_DOUTSET31_0_DIO20_BITN 20 +#define GPIO_DOUTSET31_0_DIO20_M 0x00100000 +#define GPIO_DOUTSET31_0_DIO20_S 20 // Field: [19] DIO19 // // Set bit 19 -#define GPIO_DOUTSET31_0_DIO19 0x00080000 -#define GPIO_DOUTSET31_0_DIO19_BITN 19 -#define GPIO_DOUTSET31_0_DIO19_M 0x00080000 -#define GPIO_DOUTSET31_0_DIO19_S 19 +#define GPIO_DOUTSET31_0_DIO19 0x00080000 +#define GPIO_DOUTSET31_0_DIO19_BITN 19 +#define GPIO_DOUTSET31_0_DIO19_M 0x00080000 +#define GPIO_DOUTSET31_0_DIO19_S 19 // Field: [18] DIO18 // // Set bit 18 -#define GPIO_DOUTSET31_0_DIO18 0x00040000 -#define GPIO_DOUTSET31_0_DIO18_BITN 18 -#define GPIO_DOUTSET31_0_DIO18_M 0x00040000 -#define GPIO_DOUTSET31_0_DIO18_S 18 +#define GPIO_DOUTSET31_0_DIO18 0x00040000 +#define GPIO_DOUTSET31_0_DIO18_BITN 18 +#define GPIO_DOUTSET31_0_DIO18_M 0x00040000 +#define GPIO_DOUTSET31_0_DIO18_S 18 // Field: [17] DIO17 // // Set bit 17 -#define GPIO_DOUTSET31_0_DIO17 0x00020000 -#define GPIO_DOUTSET31_0_DIO17_BITN 17 -#define GPIO_DOUTSET31_0_DIO17_M 0x00020000 -#define GPIO_DOUTSET31_0_DIO17_S 17 +#define GPIO_DOUTSET31_0_DIO17 0x00020000 +#define GPIO_DOUTSET31_0_DIO17_BITN 17 +#define GPIO_DOUTSET31_0_DIO17_M 0x00020000 +#define GPIO_DOUTSET31_0_DIO17_S 17 // Field: [16] DIO16 // // Set bit 16 -#define GPIO_DOUTSET31_0_DIO16 0x00010000 -#define GPIO_DOUTSET31_0_DIO16_BITN 16 -#define GPIO_DOUTSET31_0_DIO16_M 0x00010000 -#define GPIO_DOUTSET31_0_DIO16_S 16 +#define GPIO_DOUTSET31_0_DIO16 0x00010000 +#define GPIO_DOUTSET31_0_DIO16_BITN 16 +#define GPIO_DOUTSET31_0_DIO16_M 0x00010000 +#define GPIO_DOUTSET31_0_DIO16_S 16 // Field: [15] DIO15 // // Set bit 15 -#define GPIO_DOUTSET31_0_DIO15 0x00008000 -#define GPIO_DOUTSET31_0_DIO15_BITN 15 -#define GPIO_DOUTSET31_0_DIO15_M 0x00008000 -#define GPIO_DOUTSET31_0_DIO15_S 15 +#define GPIO_DOUTSET31_0_DIO15 0x00008000 +#define GPIO_DOUTSET31_0_DIO15_BITN 15 +#define GPIO_DOUTSET31_0_DIO15_M 0x00008000 +#define GPIO_DOUTSET31_0_DIO15_S 15 // Field: [14] DIO14 // // Set bit 14 -#define GPIO_DOUTSET31_0_DIO14 0x00004000 -#define GPIO_DOUTSET31_0_DIO14_BITN 14 -#define GPIO_DOUTSET31_0_DIO14_M 0x00004000 -#define GPIO_DOUTSET31_0_DIO14_S 14 +#define GPIO_DOUTSET31_0_DIO14 0x00004000 +#define GPIO_DOUTSET31_0_DIO14_BITN 14 +#define GPIO_DOUTSET31_0_DIO14_M 0x00004000 +#define GPIO_DOUTSET31_0_DIO14_S 14 // Field: [13] DIO13 // // Set bit 13 -#define GPIO_DOUTSET31_0_DIO13 0x00002000 -#define GPIO_DOUTSET31_0_DIO13_BITN 13 -#define GPIO_DOUTSET31_0_DIO13_M 0x00002000 -#define GPIO_DOUTSET31_0_DIO13_S 13 +#define GPIO_DOUTSET31_0_DIO13 0x00002000 +#define GPIO_DOUTSET31_0_DIO13_BITN 13 +#define GPIO_DOUTSET31_0_DIO13_M 0x00002000 +#define GPIO_DOUTSET31_0_DIO13_S 13 // Field: [12] DIO12 // // Set bit 12 -#define GPIO_DOUTSET31_0_DIO12 0x00001000 -#define GPIO_DOUTSET31_0_DIO12_BITN 12 -#define GPIO_DOUTSET31_0_DIO12_M 0x00001000 -#define GPIO_DOUTSET31_0_DIO12_S 12 +#define GPIO_DOUTSET31_0_DIO12 0x00001000 +#define GPIO_DOUTSET31_0_DIO12_BITN 12 +#define GPIO_DOUTSET31_0_DIO12_M 0x00001000 +#define GPIO_DOUTSET31_0_DIO12_S 12 // Field: [11] DIO11 // // Set bit 11 -#define GPIO_DOUTSET31_0_DIO11 0x00000800 -#define GPIO_DOUTSET31_0_DIO11_BITN 11 -#define GPIO_DOUTSET31_0_DIO11_M 0x00000800 -#define GPIO_DOUTSET31_0_DIO11_S 11 +#define GPIO_DOUTSET31_0_DIO11 0x00000800 +#define GPIO_DOUTSET31_0_DIO11_BITN 11 +#define GPIO_DOUTSET31_0_DIO11_M 0x00000800 +#define GPIO_DOUTSET31_0_DIO11_S 11 // Field: [10] DIO10 // // Set bit 10 -#define GPIO_DOUTSET31_0_DIO10 0x00000400 -#define GPIO_DOUTSET31_0_DIO10_BITN 10 -#define GPIO_DOUTSET31_0_DIO10_M 0x00000400 -#define GPIO_DOUTSET31_0_DIO10_S 10 +#define GPIO_DOUTSET31_0_DIO10 0x00000400 +#define GPIO_DOUTSET31_0_DIO10_BITN 10 +#define GPIO_DOUTSET31_0_DIO10_M 0x00000400 +#define GPIO_DOUTSET31_0_DIO10_S 10 // Field: [9] DIO9 // // Set bit 9 -#define GPIO_DOUTSET31_0_DIO9 0x00000200 -#define GPIO_DOUTSET31_0_DIO9_BITN 9 -#define GPIO_DOUTSET31_0_DIO9_M 0x00000200 -#define GPIO_DOUTSET31_0_DIO9_S 9 +#define GPIO_DOUTSET31_0_DIO9 0x00000200 +#define GPIO_DOUTSET31_0_DIO9_BITN 9 +#define GPIO_DOUTSET31_0_DIO9_M 0x00000200 +#define GPIO_DOUTSET31_0_DIO9_S 9 // Field: [8] DIO8 // // Set bit 8 -#define GPIO_DOUTSET31_0_DIO8 0x00000100 -#define GPIO_DOUTSET31_0_DIO8_BITN 8 -#define GPIO_DOUTSET31_0_DIO8_M 0x00000100 -#define GPIO_DOUTSET31_0_DIO8_S 8 +#define GPIO_DOUTSET31_0_DIO8 0x00000100 +#define GPIO_DOUTSET31_0_DIO8_BITN 8 +#define GPIO_DOUTSET31_0_DIO8_M 0x00000100 +#define GPIO_DOUTSET31_0_DIO8_S 8 // Field: [7] DIO7 // // Set bit 7 -#define GPIO_DOUTSET31_0_DIO7 0x00000080 -#define GPIO_DOUTSET31_0_DIO7_BITN 7 -#define GPIO_DOUTSET31_0_DIO7_M 0x00000080 -#define GPIO_DOUTSET31_0_DIO7_S 7 +#define GPIO_DOUTSET31_0_DIO7 0x00000080 +#define GPIO_DOUTSET31_0_DIO7_BITN 7 +#define GPIO_DOUTSET31_0_DIO7_M 0x00000080 +#define GPIO_DOUTSET31_0_DIO7_S 7 // Field: [6] DIO6 // // Set bit 6 -#define GPIO_DOUTSET31_0_DIO6 0x00000040 -#define GPIO_DOUTSET31_0_DIO6_BITN 6 -#define GPIO_DOUTSET31_0_DIO6_M 0x00000040 -#define GPIO_DOUTSET31_0_DIO6_S 6 +#define GPIO_DOUTSET31_0_DIO6 0x00000040 +#define GPIO_DOUTSET31_0_DIO6_BITN 6 +#define GPIO_DOUTSET31_0_DIO6_M 0x00000040 +#define GPIO_DOUTSET31_0_DIO6_S 6 // Field: [5] DIO5 // // Set bit 5 -#define GPIO_DOUTSET31_0_DIO5 0x00000020 -#define GPIO_DOUTSET31_0_DIO5_BITN 5 -#define GPIO_DOUTSET31_0_DIO5_M 0x00000020 -#define GPIO_DOUTSET31_0_DIO5_S 5 +#define GPIO_DOUTSET31_0_DIO5 0x00000020 +#define GPIO_DOUTSET31_0_DIO5_BITN 5 +#define GPIO_DOUTSET31_0_DIO5_M 0x00000020 +#define GPIO_DOUTSET31_0_DIO5_S 5 // Field: [4] DIO4 // // Set bit 4 -#define GPIO_DOUTSET31_0_DIO4 0x00000010 -#define GPIO_DOUTSET31_0_DIO4_BITN 4 -#define GPIO_DOUTSET31_0_DIO4_M 0x00000010 -#define GPIO_DOUTSET31_0_DIO4_S 4 +#define GPIO_DOUTSET31_0_DIO4 0x00000010 +#define GPIO_DOUTSET31_0_DIO4_BITN 4 +#define GPIO_DOUTSET31_0_DIO4_M 0x00000010 +#define GPIO_DOUTSET31_0_DIO4_S 4 // Field: [3] DIO3 // // Set bit 3 -#define GPIO_DOUTSET31_0_DIO3 0x00000008 -#define GPIO_DOUTSET31_0_DIO3_BITN 3 -#define GPIO_DOUTSET31_0_DIO3_M 0x00000008 -#define GPIO_DOUTSET31_0_DIO3_S 3 +#define GPIO_DOUTSET31_0_DIO3 0x00000008 +#define GPIO_DOUTSET31_0_DIO3_BITN 3 +#define GPIO_DOUTSET31_0_DIO3_M 0x00000008 +#define GPIO_DOUTSET31_0_DIO3_S 3 // Field: [2] DIO2 // // Set bit 2 -#define GPIO_DOUTSET31_0_DIO2 0x00000004 -#define GPIO_DOUTSET31_0_DIO2_BITN 2 -#define GPIO_DOUTSET31_0_DIO2_M 0x00000004 -#define GPIO_DOUTSET31_0_DIO2_S 2 +#define GPIO_DOUTSET31_0_DIO2 0x00000004 +#define GPIO_DOUTSET31_0_DIO2_BITN 2 +#define GPIO_DOUTSET31_0_DIO2_M 0x00000004 +#define GPIO_DOUTSET31_0_DIO2_S 2 // Field: [1] DIO1 // // Set bit 1 -#define GPIO_DOUTSET31_0_DIO1 0x00000002 -#define GPIO_DOUTSET31_0_DIO1_BITN 1 -#define GPIO_DOUTSET31_0_DIO1_M 0x00000002 -#define GPIO_DOUTSET31_0_DIO1_S 1 +#define GPIO_DOUTSET31_0_DIO1 0x00000002 +#define GPIO_DOUTSET31_0_DIO1_BITN 1 +#define GPIO_DOUTSET31_0_DIO1_M 0x00000002 +#define GPIO_DOUTSET31_0_DIO1_S 1 // Field: [0] DIO0 // // Set bit 0 -#define GPIO_DOUTSET31_0_DIO0 0x00000001 -#define GPIO_DOUTSET31_0_DIO0_BITN 0 -#define GPIO_DOUTSET31_0_DIO0_M 0x00000001 -#define GPIO_DOUTSET31_0_DIO0_S 0 +#define GPIO_DOUTSET31_0_DIO0 0x00000001 +#define GPIO_DOUTSET31_0_DIO0_BITN 0 +#define GPIO_DOUTSET31_0_DIO0_M 0x00000001 +#define GPIO_DOUTSET31_0_DIO0_S 0 //***************************************************************************** // @@ -946,258 +946,258 @@ // Field: [31] DIO31 // // Clears bit 31 -#define GPIO_DOUTCLR31_0_DIO31 0x80000000 -#define GPIO_DOUTCLR31_0_DIO31_BITN 31 -#define GPIO_DOUTCLR31_0_DIO31_M 0x80000000 -#define GPIO_DOUTCLR31_0_DIO31_S 31 +#define GPIO_DOUTCLR31_0_DIO31 0x80000000 +#define GPIO_DOUTCLR31_0_DIO31_BITN 31 +#define GPIO_DOUTCLR31_0_DIO31_M 0x80000000 +#define GPIO_DOUTCLR31_0_DIO31_S 31 // Field: [30] DIO30 // // Clears bit 30 -#define GPIO_DOUTCLR31_0_DIO30 0x40000000 -#define GPIO_DOUTCLR31_0_DIO30_BITN 30 -#define GPIO_DOUTCLR31_0_DIO30_M 0x40000000 -#define GPIO_DOUTCLR31_0_DIO30_S 30 +#define GPIO_DOUTCLR31_0_DIO30 0x40000000 +#define GPIO_DOUTCLR31_0_DIO30_BITN 30 +#define GPIO_DOUTCLR31_0_DIO30_M 0x40000000 +#define GPIO_DOUTCLR31_0_DIO30_S 30 // Field: [29] DIO29 // // Clears bit 29 -#define GPIO_DOUTCLR31_0_DIO29 0x20000000 -#define GPIO_DOUTCLR31_0_DIO29_BITN 29 -#define GPIO_DOUTCLR31_0_DIO29_M 0x20000000 -#define GPIO_DOUTCLR31_0_DIO29_S 29 +#define GPIO_DOUTCLR31_0_DIO29 0x20000000 +#define GPIO_DOUTCLR31_0_DIO29_BITN 29 +#define GPIO_DOUTCLR31_0_DIO29_M 0x20000000 +#define GPIO_DOUTCLR31_0_DIO29_S 29 // Field: [28] DIO28 // // Clears bit 28 -#define GPIO_DOUTCLR31_0_DIO28 0x10000000 -#define GPIO_DOUTCLR31_0_DIO28_BITN 28 -#define GPIO_DOUTCLR31_0_DIO28_M 0x10000000 -#define GPIO_DOUTCLR31_0_DIO28_S 28 +#define GPIO_DOUTCLR31_0_DIO28 0x10000000 +#define GPIO_DOUTCLR31_0_DIO28_BITN 28 +#define GPIO_DOUTCLR31_0_DIO28_M 0x10000000 +#define GPIO_DOUTCLR31_0_DIO28_S 28 // Field: [27] DIO27 // // Clears bit 27 -#define GPIO_DOUTCLR31_0_DIO27 0x08000000 -#define GPIO_DOUTCLR31_0_DIO27_BITN 27 -#define GPIO_DOUTCLR31_0_DIO27_M 0x08000000 -#define GPIO_DOUTCLR31_0_DIO27_S 27 +#define GPIO_DOUTCLR31_0_DIO27 0x08000000 +#define GPIO_DOUTCLR31_0_DIO27_BITN 27 +#define GPIO_DOUTCLR31_0_DIO27_M 0x08000000 +#define GPIO_DOUTCLR31_0_DIO27_S 27 // Field: [26] DIO26 // // Clears bit 26 -#define GPIO_DOUTCLR31_0_DIO26 0x04000000 -#define GPIO_DOUTCLR31_0_DIO26_BITN 26 -#define GPIO_DOUTCLR31_0_DIO26_M 0x04000000 -#define GPIO_DOUTCLR31_0_DIO26_S 26 +#define GPIO_DOUTCLR31_0_DIO26 0x04000000 +#define GPIO_DOUTCLR31_0_DIO26_BITN 26 +#define GPIO_DOUTCLR31_0_DIO26_M 0x04000000 +#define GPIO_DOUTCLR31_0_DIO26_S 26 // Field: [25] DIO25 // // Clears bit 25 -#define GPIO_DOUTCLR31_0_DIO25 0x02000000 -#define GPIO_DOUTCLR31_0_DIO25_BITN 25 -#define GPIO_DOUTCLR31_0_DIO25_M 0x02000000 -#define GPIO_DOUTCLR31_0_DIO25_S 25 +#define GPIO_DOUTCLR31_0_DIO25 0x02000000 +#define GPIO_DOUTCLR31_0_DIO25_BITN 25 +#define GPIO_DOUTCLR31_0_DIO25_M 0x02000000 +#define GPIO_DOUTCLR31_0_DIO25_S 25 // Field: [24] DIO24 // // Clears bit 24 -#define GPIO_DOUTCLR31_0_DIO24 0x01000000 -#define GPIO_DOUTCLR31_0_DIO24_BITN 24 -#define GPIO_DOUTCLR31_0_DIO24_M 0x01000000 -#define GPIO_DOUTCLR31_0_DIO24_S 24 +#define GPIO_DOUTCLR31_0_DIO24 0x01000000 +#define GPIO_DOUTCLR31_0_DIO24_BITN 24 +#define GPIO_DOUTCLR31_0_DIO24_M 0x01000000 +#define GPIO_DOUTCLR31_0_DIO24_S 24 // Field: [23] DIO23 // // Clears bit 23 -#define GPIO_DOUTCLR31_0_DIO23 0x00800000 -#define GPIO_DOUTCLR31_0_DIO23_BITN 23 -#define GPIO_DOUTCLR31_0_DIO23_M 0x00800000 -#define GPIO_DOUTCLR31_0_DIO23_S 23 +#define GPIO_DOUTCLR31_0_DIO23 0x00800000 +#define GPIO_DOUTCLR31_0_DIO23_BITN 23 +#define GPIO_DOUTCLR31_0_DIO23_M 0x00800000 +#define GPIO_DOUTCLR31_0_DIO23_S 23 // Field: [22] DIO22 // // Clears bit 22 -#define GPIO_DOUTCLR31_0_DIO22 0x00400000 -#define GPIO_DOUTCLR31_0_DIO22_BITN 22 -#define GPIO_DOUTCLR31_0_DIO22_M 0x00400000 -#define GPIO_DOUTCLR31_0_DIO22_S 22 +#define GPIO_DOUTCLR31_0_DIO22 0x00400000 +#define GPIO_DOUTCLR31_0_DIO22_BITN 22 +#define GPIO_DOUTCLR31_0_DIO22_M 0x00400000 +#define GPIO_DOUTCLR31_0_DIO22_S 22 // Field: [21] DIO21 // // Clears bit 21 -#define GPIO_DOUTCLR31_0_DIO21 0x00200000 -#define GPIO_DOUTCLR31_0_DIO21_BITN 21 -#define GPIO_DOUTCLR31_0_DIO21_M 0x00200000 -#define GPIO_DOUTCLR31_0_DIO21_S 21 +#define GPIO_DOUTCLR31_0_DIO21 0x00200000 +#define GPIO_DOUTCLR31_0_DIO21_BITN 21 +#define GPIO_DOUTCLR31_0_DIO21_M 0x00200000 +#define GPIO_DOUTCLR31_0_DIO21_S 21 // Field: [20] DIO20 // // Clears bit 20 -#define GPIO_DOUTCLR31_0_DIO20 0x00100000 -#define GPIO_DOUTCLR31_0_DIO20_BITN 20 -#define GPIO_DOUTCLR31_0_DIO20_M 0x00100000 -#define GPIO_DOUTCLR31_0_DIO20_S 20 +#define GPIO_DOUTCLR31_0_DIO20 0x00100000 +#define GPIO_DOUTCLR31_0_DIO20_BITN 20 +#define GPIO_DOUTCLR31_0_DIO20_M 0x00100000 +#define GPIO_DOUTCLR31_0_DIO20_S 20 // Field: [19] DIO19 // // Clears bit 19 -#define GPIO_DOUTCLR31_0_DIO19 0x00080000 -#define GPIO_DOUTCLR31_0_DIO19_BITN 19 -#define GPIO_DOUTCLR31_0_DIO19_M 0x00080000 -#define GPIO_DOUTCLR31_0_DIO19_S 19 +#define GPIO_DOUTCLR31_0_DIO19 0x00080000 +#define GPIO_DOUTCLR31_0_DIO19_BITN 19 +#define GPIO_DOUTCLR31_0_DIO19_M 0x00080000 +#define GPIO_DOUTCLR31_0_DIO19_S 19 // Field: [18] DIO18 // // Clears bit 18 -#define GPIO_DOUTCLR31_0_DIO18 0x00040000 -#define GPIO_DOUTCLR31_0_DIO18_BITN 18 -#define GPIO_DOUTCLR31_0_DIO18_M 0x00040000 -#define GPIO_DOUTCLR31_0_DIO18_S 18 +#define GPIO_DOUTCLR31_0_DIO18 0x00040000 +#define GPIO_DOUTCLR31_0_DIO18_BITN 18 +#define GPIO_DOUTCLR31_0_DIO18_M 0x00040000 +#define GPIO_DOUTCLR31_0_DIO18_S 18 // Field: [17] DIO17 // // Clears bit 17 -#define GPIO_DOUTCLR31_0_DIO17 0x00020000 -#define GPIO_DOUTCLR31_0_DIO17_BITN 17 -#define GPIO_DOUTCLR31_0_DIO17_M 0x00020000 -#define GPIO_DOUTCLR31_0_DIO17_S 17 +#define GPIO_DOUTCLR31_0_DIO17 0x00020000 +#define GPIO_DOUTCLR31_0_DIO17_BITN 17 +#define GPIO_DOUTCLR31_0_DIO17_M 0x00020000 +#define GPIO_DOUTCLR31_0_DIO17_S 17 // Field: [16] DIO16 // // Clears bit 16 -#define GPIO_DOUTCLR31_0_DIO16 0x00010000 -#define GPIO_DOUTCLR31_0_DIO16_BITN 16 -#define GPIO_DOUTCLR31_0_DIO16_M 0x00010000 -#define GPIO_DOUTCLR31_0_DIO16_S 16 +#define GPIO_DOUTCLR31_0_DIO16 0x00010000 +#define GPIO_DOUTCLR31_0_DIO16_BITN 16 +#define GPIO_DOUTCLR31_0_DIO16_M 0x00010000 +#define GPIO_DOUTCLR31_0_DIO16_S 16 // Field: [15] DIO15 // // Clears bit 15 -#define GPIO_DOUTCLR31_0_DIO15 0x00008000 -#define GPIO_DOUTCLR31_0_DIO15_BITN 15 -#define GPIO_DOUTCLR31_0_DIO15_M 0x00008000 -#define GPIO_DOUTCLR31_0_DIO15_S 15 +#define GPIO_DOUTCLR31_0_DIO15 0x00008000 +#define GPIO_DOUTCLR31_0_DIO15_BITN 15 +#define GPIO_DOUTCLR31_0_DIO15_M 0x00008000 +#define GPIO_DOUTCLR31_0_DIO15_S 15 // Field: [14] DIO14 // // Clears bit 14 -#define GPIO_DOUTCLR31_0_DIO14 0x00004000 -#define GPIO_DOUTCLR31_0_DIO14_BITN 14 -#define GPIO_DOUTCLR31_0_DIO14_M 0x00004000 -#define GPIO_DOUTCLR31_0_DIO14_S 14 +#define GPIO_DOUTCLR31_0_DIO14 0x00004000 +#define GPIO_DOUTCLR31_0_DIO14_BITN 14 +#define GPIO_DOUTCLR31_0_DIO14_M 0x00004000 +#define GPIO_DOUTCLR31_0_DIO14_S 14 // Field: [13] DIO13 // // Clears bit 13 -#define GPIO_DOUTCLR31_0_DIO13 0x00002000 -#define GPIO_DOUTCLR31_0_DIO13_BITN 13 -#define GPIO_DOUTCLR31_0_DIO13_M 0x00002000 -#define GPIO_DOUTCLR31_0_DIO13_S 13 +#define GPIO_DOUTCLR31_0_DIO13 0x00002000 +#define GPIO_DOUTCLR31_0_DIO13_BITN 13 +#define GPIO_DOUTCLR31_0_DIO13_M 0x00002000 +#define GPIO_DOUTCLR31_0_DIO13_S 13 // Field: [12] DIO12 // // Clears bit 12 -#define GPIO_DOUTCLR31_0_DIO12 0x00001000 -#define GPIO_DOUTCLR31_0_DIO12_BITN 12 -#define GPIO_DOUTCLR31_0_DIO12_M 0x00001000 -#define GPIO_DOUTCLR31_0_DIO12_S 12 +#define GPIO_DOUTCLR31_0_DIO12 0x00001000 +#define GPIO_DOUTCLR31_0_DIO12_BITN 12 +#define GPIO_DOUTCLR31_0_DIO12_M 0x00001000 +#define GPIO_DOUTCLR31_0_DIO12_S 12 // Field: [11] DIO11 // // Clears bit 11 -#define GPIO_DOUTCLR31_0_DIO11 0x00000800 -#define GPIO_DOUTCLR31_0_DIO11_BITN 11 -#define GPIO_DOUTCLR31_0_DIO11_M 0x00000800 -#define GPIO_DOUTCLR31_0_DIO11_S 11 +#define GPIO_DOUTCLR31_0_DIO11 0x00000800 +#define GPIO_DOUTCLR31_0_DIO11_BITN 11 +#define GPIO_DOUTCLR31_0_DIO11_M 0x00000800 +#define GPIO_DOUTCLR31_0_DIO11_S 11 // Field: [10] DIO10 // // Clears bit 10 -#define GPIO_DOUTCLR31_0_DIO10 0x00000400 -#define GPIO_DOUTCLR31_0_DIO10_BITN 10 -#define GPIO_DOUTCLR31_0_DIO10_M 0x00000400 -#define GPIO_DOUTCLR31_0_DIO10_S 10 +#define GPIO_DOUTCLR31_0_DIO10 0x00000400 +#define GPIO_DOUTCLR31_0_DIO10_BITN 10 +#define GPIO_DOUTCLR31_0_DIO10_M 0x00000400 +#define GPIO_DOUTCLR31_0_DIO10_S 10 // Field: [9] DIO9 // // Clears bit 9 -#define GPIO_DOUTCLR31_0_DIO9 0x00000200 -#define GPIO_DOUTCLR31_0_DIO9_BITN 9 -#define GPIO_DOUTCLR31_0_DIO9_M 0x00000200 -#define GPIO_DOUTCLR31_0_DIO9_S 9 +#define GPIO_DOUTCLR31_0_DIO9 0x00000200 +#define GPIO_DOUTCLR31_0_DIO9_BITN 9 +#define GPIO_DOUTCLR31_0_DIO9_M 0x00000200 +#define GPIO_DOUTCLR31_0_DIO9_S 9 // Field: [8] DIO8 // // Clears bit 8 -#define GPIO_DOUTCLR31_0_DIO8 0x00000100 -#define GPIO_DOUTCLR31_0_DIO8_BITN 8 -#define GPIO_DOUTCLR31_0_DIO8_M 0x00000100 -#define GPIO_DOUTCLR31_0_DIO8_S 8 +#define GPIO_DOUTCLR31_0_DIO8 0x00000100 +#define GPIO_DOUTCLR31_0_DIO8_BITN 8 +#define GPIO_DOUTCLR31_0_DIO8_M 0x00000100 +#define GPIO_DOUTCLR31_0_DIO8_S 8 // Field: [7] DIO7 // // Clears bit 7 -#define GPIO_DOUTCLR31_0_DIO7 0x00000080 -#define GPIO_DOUTCLR31_0_DIO7_BITN 7 -#define GPIO_DOUTCLR31_0_DIO7_M 0x00000080 -#define GPIO_DOUTCLR31_0_DIO7_S 7 +#define GPIO_DOUTCLR31_0_DIO7 0x00000080 +#define GPIO_DOUTCLR31_0_DIO7_BITN 7 +#define GPIO_DOUTCLR31_0_DIO7_M 0x00000080 +#define GPIO_DOUTCLR31_0_DIO7_S 7 // Field: [6] DIO6 // // Clears bit 6 -#define GPIO_DOUTCLR31_0_DIO6 0x00000040 -#define GPIO_DOUTCLR31_0_DIO6_BITN 6 -#define GPIO_DOUTCLR31_0_DIO6_M 0x00000040 -#define GPIO_DOUTCLR31_0_DIO6_S 6 +#define GPIO_DOUTCLR31_0_DIO6 0x00000040 +#define GPIO_DOUTCLR31_0_DIO6_BITN 6 +#define GPIO_DOUTCLR31_0_DIO6_M 0x00000040 +#define GPIO_DOUTCLR31_0_DIO6_S 6 // Field: [5] DIO5 // // Clears bit 5 -#define GPIO_DOUTCLR31_0_DIO5 0x00000020 -#define GPIO_DOUTCLR31_0_DIO5_BITN 5 -#define GPIO_DOUTCLR31_0_DIO5_M 0x00000020 -#define GPIO_DOUTCLR31_0_DIO5_S 5 +#define GPIO_DOUTCLR31_0_DIO5 0x00000020 +#define GPIO_DOUTCLR31_0_DIO5_BITN 5 +#define GPIO_DOUTCLR31_0_DIO5_M 0x00000020 +#define GPIO_DOUTCLR31_0_DIO5_S 5 // Field: [4] DIO4 // // Clears bit 4 -#define GPIO_DOUTCLR31_0_DIO4 0x00000010 -#define GPIO_DOUTCLR31_0_DIO4_BITN 4 -#define GPIO_DOUTCLR31_0_DIO4_M 0x00000010 -#define GPIO_DOUTCLR31_0_DIO4_S 4 +#define GPIO_DOUTCLR31_0_DIO4 0x00000010 +#define GPIO_DOUTCLR31_0_DIO4_BITN 4 +#define GPIO_DOUTCLR31_0_DIO4_M 0x00000010 +#define GPIO_DOUTCLR31_0_DIO4_S 4 // Field: [3] DIO3 // // Clears bit 3 -#define GPIO_DOUTCLR31_0_DIO3 0x00000008 -#define GPIO_DOUTCLR31_0_DIO3_BITN 3 -#define GPIO_DOUTCLR31_0_DIO3_M 0x00000008 -#define GPIO_DOUTCLR31_0_DIO3_S 3 +#define GPIO_DOUTCLR31_0_DIO3 0x00000008 +#define GPIO_DOUTCLR31_0_DIO3_BITN 3 +#define GPIO_DOUTCLR31_0_DIO3_M 0x00000008 +#define GPIO_DOUTCLR31_0_DIO3_S 3 // Field: [2] DIO2 // // Clears bit 2 -#define GPIO_DOUTCLR31_0_DIO2 0x00000004 -#define GPIO_DOUTCLR31_0_DIO2_BITN 2 -#define GPIO_DOUTCLR31_0_DIO2_M 0x00000004 -#define GPIO_DOUTCLR31_0_DIO2_S 2 +#define GPIO_DOUTCLR31_0_DIO2 0x00000004 +#define GPIO_DOUTCLR31_0_DIO2_BITN 2 +#define GPIO_DOUTCLR31_0_DIO2_M 0x00000004 +#define GPIO_DOUTCLR31_0_DIO2_S 2 // Field: [1] DIO1 // // Clears bit 1 -#define GPIO_DOUTCLR31_0_DIO1 0x00000002 -#define GPIO_DOUTCLR31_0_DIO1_BITN 1 -#define GPIO_DOUTCLR31_0_DIO1_M 0x00000002 -#define GPIO_DOUTCLR31_0_DIO1_S 1 +#define GPIO_DOUTCLR31_0_DIO1 0x00000002 +#define GPIO_DOUTCLR31_0_DIO1_BITN 1 +#define GPIO_DOUTCLR31_0_DIO1_M 0x00000002 +#define GPIO_DOUTCLR31_0_DIO1_S 1 // Field: [0] DIO0 // // Clears bit 0 -#define GPIO_DOUTCLR31_0_DIO0 0x00000001 -#define GPIO_DOUTCLR31_0_DIO0_BITN 0 -#define GPIO_DOUTCLR31_0_DIO0_M 0x00000001 -#define GPIO_DOUTCLR31_0_DIO0_S 0 +#define GPIO_DOUTCLR31_0_DIO0 0x00000001 +#define GPIO_DOUTCLR31_0_DIO0_BITN 0 +#define GPIO_DOUTCLR31_0_DIO0_M 0x00000001 +#define GPIO_DOUTCLR31_0_DIO0_S 0 //***************************************************************************** // @@ -1207,258 +1207,258 @@ // Field: [31] DIO31 // // Toggles bit 31 -#define GPIO_DOUTTGL31_0_DIO31 0x80000000 -#define GPIO_DOUTTGL31_0_DIO31_BITN 31 -#define GPIO_DOUTTGL31_0_DIO31_M 0x80000000 -#define GPIO_DOUTTGL31_0_DIO31_S 31 +#define GPIO_DOUTTGL31_0_DIO31 0x80000000 +#define GPIO_DOUTTGL31_0_DIO31_BITN 31 +#define GPIO_DOUTTGL31_0_DIO31_M 0x80000000 +#define GPIO_DOUTTGL31_0_DIO31_S 31 // Field: [30] DIO30 // // Toggles bit 30 -#define GPIO_DOUTTGL31_0_DIO30 0x40000000 -#define GPIO_DOUTTGL31_0_DIO30_BITN 30 -#define GPIO_DOUTTGL31_0_DIO30_M 0x40000000 -#define GPIO_DOUTTGL31_0_DIO30_S 30 +#define GPIO_DOUTTGL31_0_DIO30 0x40000000 +#define GPIO_DOUTTGL31_0_DIO30_BITN 30 +#define GPIO_DOUTTGL31_0_DIO30_M 0x40000000 +#define GPIO_DOUTTGL31_0_DIO30_S 30 // Field: [29] DIO29 // // Toggles bit 29 -#define GPIO_DOUTTGL31_0_DIO29 0x20000000 -#define GPIO_DOUTTGL31_0_DIO29_BITN 29 -#define GPIO_DOUTTGL31_0_DIO29_M 0x20000000 -#define GPIO_DOUTTGL31_0_DIO29_S 29 +#define GPIO_DOUTTGL31_0_DIO29 0x20000000 +#define GPIO_DOUTTGL31_0_DIO29_BITN 29 +#define GPIO_DOUTTGL31_0_DIO29_M 0x20000000 +#define GPIO_DOUTTGL31_0_DIO29_S 29 // Field: [28] DIO28 // // Toggles bit 28 -#define GPIO_DOUTTGL31_0_DIO28 0x10000000 -#define GPIO_DOUTTGL31_0_DIO28_BITN 28 -#define GPIO_DOUTTGL31_0_DIO28_M 0x10000000 -#define GPIO_DOUTTGL31_0_DIO28_S 28 +#define GPIO_DOUTTGL31_0_DIO28 0x10000000 +#define GPIO_DOUTTGL31_0_DIO28_BITN 28 +#define GPIO_DOUTTGL31_0_DIO28_M 0x10000000 +#define GPIO_DOUTTGL31_0_DIO28_S 28 // Field: [27] DIO27 // // Toggles bit 27 -#define GPIO_DOUTTGL31_0_DIO27 0x08000000 -#define GPIO_DOUTTGL31_0_DIO27_BITN 27 -#define GPIO_DOUTTGL31_0_DIO27_M 0x08000000 -#define GPIO_DOUTTGL31_0_DIO27_S 27 +#define GPIO_DOUTTGL31_0_DIO27 0x08000000 +#define GPIO_DOUTTGL31_0_DIO27_BITN 27 +#define GPIO_DOUTTGL31_0_DIO27_M 0x08000000 +#define GPIO_DOUTTGL31_0_DIO27_S 27 // Field: [26] DIO26 // // Toggles bit 26 -#define GPIO_DOUTTGL31_0_DIO26 0x04000000 -#define GPIO_DOUTTGL31_0_DIO26_BITN 26 -#define GPIO_DOUTTGL31_0_DIO26_M 0x04000000 -#define GPIO_DOUTTGL31_0_DIO26_S 26 +#define GPIO_DOUTTGL31_0_DIO26 0x04000000 +#define GPIO_DOUTTGL31_0_DIO26_BITN 26 +#define GPIO_DOUTTGL31_0_DIO26_M 0x04000000 +#define GPIO_DOUTTGL31_0_DIO26_S 26 // Field: [25] DIO25 // // Toggles bit 25 -#define GPIO_DOUTTGL31_0_DIO25 0x02000000 -#define GPIO_DOUTTGL31_0_DIO25_BITN 25 -#define GPIO_DOUTTGL31_0_DIO25_M 0x02000000 -#define GPIO_DOUTTGL31_0_DIO25_S 25 +#define GPIO_DOUTTGL31_0_DIO25 0x02000000 +#define GPIO_DOUTTGL31_0_DIO25_BITN 25 +#define GPIO_DOUTTGL31_0_DIO25_M 0x02000000 +#define GPIO_DOUTTGL31_0_DIO25_S 25 // Field: [24] DIO24 // // Toggles bit 24 -#define GPIO_DOUTTGL31_0_DIO24 0x01000000 -#define GPIO_DOUTTGL31_0_DIO24_BITN 24 -#define GPIO_DOUTTGL31_0_DIO24_M 0x01000000 -#define GPIO_DOUTTGL31_0_DIO24_S 24 +#define GPIO_DOUTTGL31_0_DIO24 0x01000000 +#define GPIO_DOUTTGL31_0_DIO24_BITN 24 +#define GPIO_DOUTTGL31_0_DIO24_M 0x01000000 +#define GPIO_DOUTTGL31_0_DIO24_S 24 // Field: [23] DIO23 // // Toggles bit 23 -#define GPIO_DOUTTGL31_0_DIO23 0x00800000 -#define GPIO_DOUTTGL31_0_DIO23_BITN 23 -#define GPIO_DOUTTGL31_0_DIO23_M 0x00800000 -#define GPIO_DOUTTGL31_0_DIO23_S 23 +#define GPIO_DOUTTGL31_0_DIO23 0x00800000 +#define GPIO_DOUTTGL31_0_DIO23_BITN 23 +#define GPIO_DOUTTGL31_0_DIO23_M 0x00800000 +#define GPIO_DOUTTGL31_0_DIO23_S 23 // Field: [22] DIO22 // // Toggles bit 22 -#define GPIO_DOUTTGL31_0_DIO22 0x00400000 -#define GPIO_DOUTTGL31_0_DIO22_BITN 22 -#define GPIO_DOUTTGL31_0_DIO22_M 0x00400000 -#define GPIO_DOUTTGL31_0_DIO22_S 22 +#define GPIO_DOUTTGL31_0_DIO22 0x00400000 +#define GPIO_DOUTTGL31_0_DIO22_BITN 22 +#define GPIO_DOUTTGL31_0_DIO22_M 0x00400000 +#define GPIO_DOUTTGL31_0_DIO22_S 22 // Field: [21] DIO21 // // Toggles bit 21 -#define GPIO_DOUTTGL31_0_DIO21 0x00200000 -#define GPIO_DOUTTGL31_0_DIO21_BITN 21 -#define GPIO_DOUTTGL31_0_DIO21_M 0x00200000 -#define GPIO_DOUTTGL31_0_DIO21_S 21 +#define GPIO_DOUTTGL31_0_DIO21 0x00200000 +#define GPIO_DOUTTGL31_0_DIO21_BITN 21 +#define GPIO_DOUTTGL31_0_DIO21_M 0x00200000 +#define GPIO_DOUTTGL31_0_DIO21_S 21 // Field: [20] DIO20 // // Toggles bit 20 -#define GPIO_DOUTTGL31_0_DIO20 0x00100000 -#define GPIO_DOUTTGL31_0_DIO20_BITN 20 -#define GPIO_DOUTTGL31_0_DIO20_M 0x00100000 -#define GPIO_DOUTTGL31_0_DIO20_S 20 +#define GPIO_DOUTTGL31_0_DIO20 0x00100000 +#define GPIO_DOUTTGL31_0_DIO20_BITN 20 +#define GPIO_DOUTTGL31_0_DIO20_M 0x00100000 +#define GPIO_DOUTTGL31_0_DIO20_S 20 // Field: [19] DIO19 // // Toggles bit 19 -#define GPIO_DOUTTGL31_0_DIO19 0x00080000 -#define GPIO_DOUTTGL31_0_DIO19_BITN 19 -#define GPIO_DOUTTGL31_0_DIO19_M 0x00080000 -#define GPIO_DOUTTGL31_0_DIO19_S 19 +#define GPIO_DOUTTGL31_0_DIO19 0x00080000 +#define GPIO_DOUTTGL31_0_DIO19_BITN 19 +#define GPIO_DOUTTGL31_0_DIO19_M 0x00080000 +#define GPIO_DOUTTGL31_0_DIO19_S 19 // Field: [18] DIO18 // // Toggles bit 18 -#define GPIO_DOUTTGL31_0_DIO18 0x00040000 -#define GPIO_DOUTTGL31_0_DIO18_BITN 18 -#define GPIO_DOUTTGL31_0_DIO18_M 0x00040000 -#define GPIO_DOUTTGL31_0_DIO18_S 18 +#define GPIO_DOUTTGL31_0_DIO18 0x00040000 +#define GPIO_DOUTTGL31_0_DIO18_BITN 18 +#define GPIO_DOUTTGL31_0_DIO18_M 0x00040000 +#define GPIO_DOUTTGL31_0_DIO18_S 18 // Field: [17] DIO17 // // Toggles bit 17 -#define GPIO_DOUTTGL31_0_DIO17 0x00020000 -#define GPIO_DOUTTGL31_0_DIO17_BITN 17 -#define GPIO_DOUTTGL31_0_DIO17_M 0x00020000 -#define GPIO_DOUTTGL31_0_DIO17_S 17 +#define GPIO_DOUTTGL31_0_DIO17 0x00020000 +#define GPIO_DOUTTGL31_0_DIO17_BITN 17 +#define GPIO_DOUTTGL31_0_DIO17_M 0x00020000 +#define GPIO_DOUTTGL31_0_DIO17_S 17 // Field: [16] DIO16 // // Toggles bit 16 -#define GPIO_DOUTTGL31_0_DIO16 0x00010000 -#define GPIO_DOUTTGL31_0_DIO16_BITN 16 -#define GPIO_DOUTTGL31_0_DIO16_M 0x00010000 -#define GPIO_DOUTTGL31_0_DIO16_S 16 +#define GPIO_DOUTTGL31_0_DIO16 0x00010000 +#define GPIO_DOUTTGL31_0_DIO16_BITN 16 +#define GPIO_DOUTTGL31_0_DIO16_M 0x00010000 +#define GPIO_DOUTTGL31_0_DIO16_S 16 // Field: [15] DIO15 // // Toggles bit 15 -#define GPIO_DOUTTGL31_0_DIO15 0x00008000 -#define GPIO_DOUTTGL31_0_DIO15_BITN 15 -#define GPIO_DOUTTGL31_0_DIO15_M 0x00008000 -#define GPIO_DOUTTGL31_0_DIO15_S 15 +#define GPIO_DOUTTGL31_0_DIO15 0x00008000 +#define GPIO_DOUTTGL31_0_DIO15_BITN 15 +#define GPIO_DOUTTGL31_0_DIO15_M 0x00008000 +#define GPIO_DOUTTGL31_0_DIO15_S 15 // Field: [14] DIO14 // // Toggles bit 14 -#define GPIO_DOUTTGL31_0_DIO14 0x00004000 -#define GPIO_DOUTTGL31_0_DIO14_BITN 14 -#define GPIO_DOUTTGL31_0_DIO14_M 0x00004000 -#define GPIO_DOUTTGL31_0_DIO14_S 14 +#define GPIO_DOUTTGL31_0_DIO14 0x00004000 +#define GPIO_DOUTTGL31_0_DIO14_BITN 14 +#define GPIO_DOUTTGL31_0_DIO14_M 0x00004000 +#define GPIO_DOUTTGL31_0_DIO14_S 14 // Field: [13] DIO13 // // Toggles bit 13 -#define GPIO_DOUTTGL31_0_DIO13 0x00002000 -#define GPIO_DOUTTGL31_0_DIO13_BITN 13 -#define GPIO_DOUTTGL31_0_DIO13_M 0x00002000 -#define GPIO_DOUTTGL31_0_DIO13_S 13 +#define GPIO_DOUTTGL31_0_DIO13 0x00002000 +#define GPIO_DOUTTGL31_0_DIO13_BITN 13 +#define GPIO_DOUTTGL31_0_DIO13_M 0x00002000 +#define GPIO_DOUTTGL31_0_DIO13_S 13 // Field: [12] DIO12 // // Toggles bit 12 -#define GPIO_DOUTTGL31_0_DIO12 0x00001000 -#define GPIO_DOUTTGL31_0_DIO12_BITN 12 -#define GPIO_DOUTTGL31_0_DIO12_M 0x00001000 -#define GPIO_DOUTTGL31_0_DIO12_S 12 +#define GPIO_DOUTTGL31_0_DIO12 0x00001000 +#define GPIO_DOUTTGL31_0_DIO12_BITN 12 +#define GPIO_DOUTTGL31_0_DIO12_M 0x00001000 +#define GPIO_DOUTTGL31_0_DIO12_S 12 // Field: [11] DIO11 // // Toggles bit 11 -#define GPIO_DOUTTGL31_0_DIO11 0x00000800 -#define GPIO_DOUTTGL31_0_DIO11_BITN 11 -#define GPIO_DOUTTGL31_0_DIO11_M 0x00000800 -#define GPIO_DOUTTGL31_0_DIO11_S 11 +#define GPIO_DOUTTGL31_0_DIO11 0x00000800 +#define GPIO_DOUTTGL31_0_DIO11_BITN 11 +#define GPIO_DOUTTGL31_0_DIO11_M 0x00000800 +#define GPIO_DOUTTGL31_0_DIO11_S 11 // Field: [10] DIO10 // // Toggles bit 10 -#define GPIO_DOUTTGL31_0_DIO10 0x00000400 -#define GPIO_DOUTTGL31_0_DIO10_BITN 10 -#define GPIO_DOUTTGL31_0_DIO10_M 0x00000400 -#define GPIO_DOUTTGL31_0_DIO10_S 10 +#define GPIO_DOUTTGL31_0_DIO10 0x00000400 +#define GPIO_DOUTTGL31_0_DIO10_BITN 10 +#define GPIO_DOUTTGL31_0_DIO10_M 0x00000400 +#define GPIO_DOUTTGL31_0_DIO10_S 10 // Field: [9] DIO9 // // Toggles bit 9 -#define GPIO_DOUTTGL31_0_DIO9 0x00000200 -#define GPIO_DOUTTGL31_0_DIO9_BITN 9 -#define GPIO_DOUTTGL31_0_DIO9_M 0x00000200 -#define GPIO_DOUTTGL31_0_DIO9_S 9 +#define GPIO_DOUTTGL31_0_DIO9 0x00000200 +#define GPIO_DOUTTGL31_0_DIO9_BITN 9 +#define GPIO_DOUTTGL31_0_DIO9_M 0x00000200 +#define GPIO_DOUTTGL31_0_DIO9_S 9 // Field: [8] DIO8 // // Toggles bit 8 -#define GPIO_DOUTTGL31_0_DIO8 0x00000100 -#define GPIO_DOUTTGL31_0_DIO8_BITN 8 -#define GPIO_DOUTTGL31_0_DIO8_M 0x00000100 -#define GPIO_DOUTTGL31_0_DIO8_S 8 +#define GPIO_DOUTTGL31_0_DIO8 0x00000100 +#define GPIO_DOUTTGL31_0_DIO8_BITN 8 +#define GPIO_DOUTTGL31_0_DIO8_M 0x00000100 +#define GPIO_DOUTTGL31_0_DIO8_S 8 // Field: [7] DIO7 // // Toggles bit 7 -#define GPIO_DOUTTGL31_0_DIO7 0x00000080 -#define GPIO_DOUTTGL31_0_DIO7_BITN 7 -#define GPIO_DOUTTGL31_0_DIO7_M 0x00000080 -#define GPIO_DOUTTGL31_0_DIO7_S 7 +#define GPIO_DOUTTGL31_0_DIO7 0x00000080 +#define GPIO_DOUTTGL31_0_DIO7_BITN 7 +#define GPIO_DOUTTGL31_0_DIO7_M 0x00000080 +#define GPIO_DOUTTGL31_0_DIO7_S 7 // Field: [6] DIO6 // // Toggles bit 6 -#define GPIO_DOUTTGL31_0_DIO6 0x00000040 -#define GPIO_DOUTTGL31_0_DIO6_BITN 6 -#define GPIO_DOUTTGL31_0_DIO6_M 0x00000040 -#define GPIO_DOUTTGL31_0_DIO6_S 6 +#define GPIO_DOUTTGL31_0_DIO6 0x00000040 +#define GPIO_DOUTTGL31_0_DIO6_BITN 6 +#define GPIO_DOUTTGL31_0_DIO6_M 0x00000040 +#define GPIO_DOUTTGL31_0_DIO6_S 6 // Field: [5] DIO5 // // Toggles bit 5 -#define GPIO_DOUTTGL31_0_DIO5 0x00000020 -#define GPIO_DOUTTGL31_0_DIO5_BITN 5 -#define GPIO_DOUTTGL31_0_DIO5_M 0x00000020 -#define GPIO_DOUTTGL31_0_DIO5_S 5 +#define GPIO_DOUTTGL31_0_DIO5 0x00000020 +#define GPIO_DOUTTGL31_0_DIO5_BITN 5 +#define GPIO_DOUTTGL31_0_DIO5_M 0x00000020 +#define GPIO_DOUTTGL31_0_DIO5_S 5 // Field: [4] DIO4 // // Toggles bit 4 -#define GPIO_DOUTTGL31_0_DIO4 0x00000010 -#define GPIO_DOUTTGL31_0_DIO4_BITN 4 -#define GPIO_DOUTTGL31_0_DIO4_M 0x00000010 -#define GPIO_DOUTTGL31_0_DIO4_S 4 +#define GPIO_DOUTTGL31_0_DIO4 0x00000010 +#define GPIO_DOUTTGL31_0_DIO4_BITN 4 +#define GPIO_DOUTTGL31_0_DIO4_M 0x00000010 +#define GPIO_DOUTTGL31_0_DIO4_S 4 // Field: [3] DIO3 // // Toggles bit 3 -#define GPIO_DOUTTGL31_0_DIO3 0x00000008 -#define GPIO_DOUTTGL31_0_DIO3_BITN 3 -#define GPIO_DOUTTGL31_0_DIO3_M 0x00000008 -#define GPIO_DOUTTGL31_0_DIO3_S 3 +#define GPIO_DOUTTGL31_0_DIO3 0x00000008 +#define GPIO_DOUTTGL31_0_DIO3_BITN 3 +#define GPIO_DOUTTGL31_0_DIO3_M 0x00000008 +#define GPIO_DOUTTGL31_0_DIO3_S 3 // Field: [2] DIO2 // // Toggles bit 2 -#define GPIO_DOUTTGL31_0_DIO2 0x00000004 -#define GPIO_DOUTTGL31_0_DIO2_BITN 2 -#define GPIO_DOUTTGL31_0_DIO2_M 0x00000004 -#define GPIO_DOUTTGL31_0_DIO2_S 2 +#define GPIO_DOUTTGL31_0_DIO2 0x00000004 +#define GPIO_DOUTTGL31_0_DIO2_BITN 2 +#define GPIO_DOUTTGL31_0_DIO2_M 0x00000004 +#define GPIO_DOUTTGL31_0_DIO2_S 2 // Field: [1] DIO1 // // Toggles bit 1 -#define GPIO_DOUTTGL31_0_DIO1 0x00000002 -#define GPIO_DOUTTGL31_0_DIO1_BITN 1 -#define GPIO_DOUTTGL31_0_DIO1_M 0x00000002 -#define GPIO_DOUTTGL31_0_DIO1_S 1 +#define GPIO_DOUTTGL31_0_DIO1 0x00000002 +#define GPIO_DOUTTGL31_0_DIO1_BITN 1 +#define GPIO_DOUTTGL31_0_DIO1_M 0x00000002 +#define GPIO_DOUTTGL31_0_DIO1_S 1 // Field: [0] DIO0 // // Toggles bit 0 -#define GPIO_DOUTTGL31_0_DIO0 0x00000001 -#define GPIO_DOUTTGL31_0_DIO0_BITN 0 -#define GPIO_DOUTTGL31_0_DIO0_M 0x00000001 -#define GPIO_DOUTTGL31_0_DIO0_S 0 +#define GPIO_DOUTTGL31_0_DIO0 0x00000001 +#define GPIO_DOUTTGL31_0_DIO0_BITN 0 +#define GPIO_DOUTTGL31_0_DIO0_M 0x00000001 +#define GPIO_DOUTTGL31_0_DIO0_S 0 //***************************************************************************** // @@ -1468,258 +1468,258 @@ // Field: [31] DIO31 // // Data input from DIO 31 -#define GPIO_DIN31_0_DIO31 0x80000000 -#define GPIO_DIN31_0_DIO31_BITN 31 -#define GPIO_DIN31_0_DIO31_M 0x80000000 -#define GPIO_DIN31_0_DIO31_S 31 +#define GPIO_DIN31_0_DIO31 0x80000000 +#define GPIO_DIN31_0_DIO31_BITN 31 +#define GPIO_DIN31_0_DIO31_M 0x80000000 +#define GPIO_DIN31_0_DIO31_S 31 // Field: [30] DIO30 // // Data input from DIO 30 -#define GPIO_DIN31_0_DIO30 0x40000000 -#define GPIO_DIN31_0_DIO30_BITN 30 -#define GPIO_DIN31_0_DIO30_M 0x40000000 -#define GPIO_DIN31_0_DIO30_S 30 +#define GPIO_DIN31_0_DIO30 0x40000000 +#define GPIO_DIN31_0_DIO30_BITN 30 +#define GPIO_DIN31_0_DIO30_M 0x40000000 +#define GPIO_DIN31_0_DIO30_S 30 // Field: [29] DIO29 // // Data input from DIO 29 -#define GPIO_DIN31_0_DIO29 0x20000000 -#define GPIO_DIN31_0_DIO29_BITN 29 -#define GPIO_DIN31_0_DIO29_M 0x20000000 -#define GPIO_DIN31_0_DIO29_S 29 +#define GPIO_DIN31_0_DIO29 0x20000000 +#define GPIO_DIN31_0_DIO29_BITN 29 +#define GPIO_DIN31_0_DIO29_M 0x20000000 +#define GPIO_DIN31_0_DIO29_S 29 // Field: [28] DIO28 // // Data input from DIO 28 -#define GPIO_DIN31_0_DIO28 0x10000000 -#define GPIO_DIN31_0_DIO28_BITN 28 -#define GPIO_DIN31_0_DIO28_M 0x10000000 -#define GPIO_DIN31_0_DIO28_S 28 +#define GPIO_DIN31_0_DIO28 0x10000000 +#define GPIO_DIN31_0_DIO28_BITN 28 +#define GPIO_DIN31_0_DIO28_M 0x10000000 +#define GPIO_DIN31_0_DIO28_S 28 // Field: [27] DIO27 // // Data input from DIO 27 -#define GPIO_DIN31_0_DIO27 0x08000000 -#define GPIO_DIN31_0_DIO27_BITN 27 -#define GPIO_DIN31_0_DIO27_M 0x08000000 -#define GPIO_DIN31_0_DIO27_S 27 +#define GPIO_DIN31_0_DIO27 0x08000000 +#define GPIO_DIN31_0_DIO27_BITN 27 +#define GPIO_DIN31_0_DIO27_M 0x08000000 +#define GPIO_DIN31_0_DIO27_S 27 // Field: [26] DIO26 // // Data input from DIO 26 -#define GPIO_DIN31_0_DIO26 0x04000000 -#define GPIO_DIN31_0_DIO26_BITN 26 -#define GPIO_DIN31_0_DIO26_M 0x04000000 -#define GPIO_DIN31_0_DIO26_S 26 +#define GPIO_DIN31_0_DIO26 0x04000000 +#define GPIO_DIN31_0_DIO26_BITN 26 +#define GPIO_DIN31_0_DIO26_M 0x04000000 +#define GPIO_DIN31_0_DIO26_S 26 // Field: [25] DIO25 // // Data input from DIO 25 -#define GPIO_DIN31_0_DIO25 0x02000000 -#define GPIO_DIN31_0_DIO25_BITN 25 -#define GPIO_DIN31_0_DIO25_M 0x02000000 -#define GPIO_DIN31_0_DIO25_S 25 +#define GPIO_DIN31_0_DIO25 0x02000000 +#define GPIO_DIN31_0_DIO25_BITN 25 +#define GPIO_DIN31_0_DIO25_M 0x02000000 +#define GPIO_DIN31_0_DIO25_S 25 // Field: [24] DIO24 // // Data input from DIO 24 -#define GPIO_DIN31_0_DIO24 0x01000000 -#define GPIO_DIN31_0_DIO24_BITN 24 -#define GPIO_DIN31_0_DIO24_M 0x01000000 -#define GPIO_DIN31_0_DIO24_S 24 +#define GPIO_DIN31_0_DIO24 0x01000000 +#define GPIO_DIN31_0_DIO24_BITN 24 +#define GPIO_DIN31_0_DIO24_M 0x01000000 +#define GPIO_DIN31_0_DIO24_S 24 // Field: [23] DIO23 // // Data input from DIO 23 -#define GPIO_DIN31_0_DIO23 0x00800000 -#define GPIO_DIN31_0_DIO23_BITN 23 -#define GPIO_DIN31_0_DIO23_M 0x00800000 -#define GPIO_DIN31_0_DIO23_S 23 +#define GPIO_DIN31_0_DIO23 0x00800000 +#define GPIO_DIN31_0_DIO23_BITN 23 +#define GPIO_DIN31_0_DIO23_M 0x00800000 +#define GPIO_DIN31_0_DIO23_S 23 // Field: [22] DIO22 // // Data input from DIO 22 -#define GPIO_DIN31_0_DIO22 0x00400000 -#define GPIO_DIN31_0_DIO22_BITN 22 -#define GPIO_DIN31_0_DIO22_M 0x00400000 -#define GPIO_DIN31_0_DIO22_S 22 +#define GPIO_DIN31_0_DIO22 0x00400000 +#define GPIO_DIN31_0_DIO22_BITN 22 +#define GPIO_DIN31_0_DIO22_M 0x00400000 +#define GPIO_DIN31_0_DIO22_S 22 // Field: [21] DIO21 // // Data input from DIO 21 -#define GPIO_DIN31_0_DIO21 0x00200000 -#define GPIO_DIN31_0_DIO21_BITN 21 -#define GPIO_DIN31_0_DIO21_M 0x00200000 -#define GPIO_DIN31_0_DIO21_S 21 +#define GPIO_DIN31_0_DIO21 0x00200000 +#define GPIO_DIN31_0_DIO21_BITN 21 +#define GPIO_DIN31_0_DIO21_M 0x00200000 +#define GPIO_DIN31_0_DIO21_S 21 // Field: [20] DIO20 // // Data input from DIO 20 -#define GPIO_DIN31_0_DIO20 0x00100000 -#define GPIO_DIN31_0_DIO20_BITN 20 -#define GPIO_DIN31_0_DIO20_M 0x00100000 -#define GPIO_DIN31_0_DIO20_S 20 +#define GPIO_DIN31_0_DIO20 0x00100000 +#define GPIO_DIN31_0_DIO20_BITN 20 +#define GPIO_DIN31_0_DIO20_M 0x00100000 +#define GPIO_DIN31_0_DIO20_S 20 // Field: [19] DIO19 // // Data input from DIO 19 -#define GPIO_DIN31_0_DIO19 0x00080000 -#define GPIO_DIN31_0_DIO19_BITN 19 -#define GPIO_DIN31_0_DIO19_M 0x00080000 -#define GPIO_DIN31_0_DIO19_S 19 +#define GPIO_DIN31_0_DIO19 0x00080000 +#define GPIO_DIN31_0_DIO19_BITN 19 +#define GPIO_DIN31_0_DIO19_M 0x00080000 +#define GPIO_DIN31_0_DIO19_S 19 // Field: [18] DIO18 // // Data input from DIO 18 -#define GPIO_DIN31_0_DIO18 0x00040000 -#define GPIO_DIN31_0_DIO18_BITN 18 -#define GPIO_DIN31_0_DIO18_M 0x00040000 -#define GPIO_DIN31_0_DIO18_S 18 +#define GPIO_DIN31_0_DIO18 0x00040000 +#define GPIO_DIN31_0_DIO18_BITN 18 +#define GPIO_DIN31_0_DIO18_M 0x00040000 +#define GPIO_DIN31_0_DIO18_S 18 // Field: [17] DIO17 // // Data input from DIO 17 -#define GPIO_DIN31_0_DIO17 0x00020000 -#define GPIO_DIN31_0_DIO17_BITN 17 -#define GPIO_DIN31_0_DIO17_M 0x00020000 -#define GPIO_DIN31_0_DIO17_S 17 +#define GPIO_DIN31_0_DIO17 0x00020000 +#define GPIO_DIN31_0_DIO17_BITN 17 +#define GPIO_DIN31_0_DIO17_M 0x00020000 +#define GPIO_DIN31_0_DIO17_S 17 // Field: [16] DIO16 // // Data input from DIO 16 -#define GPIO_DIN31_0_DIO16 0x00010000 -#define GPIO_DIN31_0_DIO16_BITN 16 -#define GPIO_DIN31_0_DIO16_M 0x00010000 -#define GPIO_DIN31_0_DIO16_S 16 +#define GPIO_DIN31_0_DIO16 0x00010000 +#define GPIO_DIN31_0_DIO16_BITN 16 +#define GPIO_DIN31_0_DIO16_M 0x00010000 +#define GPIO_DIN31_0_DIO16_S 16 // Field: [15] DIO15 // // Data input from DIO 15 -#define GPIO_DIN31_0_DIO15 0x00008000 -#define GPIO_DIN31_0_DIO15_BITN 15 -#define GPIO_DIN31_0_DIO15_M 0x00008000 -#define GPIO_DIN31_0_DIO15_S 15 +#define GPIO_DIN31_0_DIO15 0x00008000 +#define GPIO_DIN31_0_DIO15_BITN 15 +#define GPIO_DIN31_0_DIO15_M 0x00008000 +#define GPIO_DIN31_0_DIO15_S 15 // Field: [14] DIO14 // // Data input from DIO 14 -#define GPIO_DIN31_0_DIO14 0x00004000 -#define GPIO_DIN31_0_DIO14_BITN 14 -#define GPIO_DIN31_0_DIO14_M 0x00004000 -#define GPIO_DIN31_0_DIO14_S 14 +#define GPIO_DIN31_0_DIO14 0x00004000 +#define GPIO_DIN31_0_DIO14_BITN 14 +#define GPIO_DIN31_0_DIO14_M 0x00004000 +#define GPIO_DIN31_0_DIO14_S 14 // Field: [13] DIO13 // // Data input from DIO 13 -#define GPIO_DIN31_0_DIO13 0x00002000 -#define GPIO_DIN31_0_DIO13_BITN 13 -#define GPIO_DIN31_0_DIO13_M 0x00002000 -#define GPIO_DIN31_0_DIO13_S 13 +#define GPIO_DIN31_0_DIO13 0x00002000 +#define GPIO_DIN31_0_DIO13_BITN 13 +#define GPIO_DIN31_0_DIO13_M 0x00002000 +#define GPIO_DIN31_0_DIO13_S 13 // Field: [12] DIO12 // // Data input from DIO 12 -#define GPIO_DIN31_0_DIO12 0x00001000 -#define GPIO_DIN31_0_DIO12_BITN 12 -#define GPIO_DIN31_0_DIO12_M 0x00001000 -#define GPIO_DIN31_0_DIO12_S 12 +#define GPIO_DIN31_0_DIO12 0x00001000 +#define GPIO_DIN31_0_DIO12_BITN 12 +#define GPIO_DIN31_0_DIO12_M 0x00001000 +#define GPIO_DIN31_0_DIO12_S 12 // Field: [11] DIO11 // // Data input from DIO 11 -#define GPIO_DIN31_0_DIO11 0x00000800 -#define GPIO_DIN31_0_DIO11_BITN 11 -#define GPIO_DIN31_0_DIO11_M 0x00000800 -#define GPIO_DIN31_0_DIO11_S 11 +#define GPIO_DIN31_0_DIO11 0x00000800 +#define GPIO_DIN31_0_DIO11_BITN 11 +#define GPIO_DIN31_0_DIO11_M 0x00000800 +#define GPIO_DIN31_0_DIO11_S 11 // Field: [10] DIO10 // // Data input from DIO 10 -#define GPIO_DIN31_0_DIO10 0x00000400 -#define GPIO_DIN31_0_DIO10_BITN 10 -#define GPIO_DIN31_0_DIO10_M 0x00000400 -#define GPIO_DIN31_0_DIO10_S 10 +#define GPIO_DIN31_0_DIO10 0x00000400 +#define GPIO_DIN31_0_DIO10_BITN 10 +#define GPIO_DIN31_0_DIO10_M 0x00000400 +#define GPIO_DIN31_0_DIO10_S 10 // Field: [9] DIO9 // // Data input from DIO 9 -#define GPIO_DIN31_0_DIO9 0x00000200 -#define GPIO_DIN31_0_DIO9_BITN 9 -#define GPIO_DIN31_0_DIO9_M 0x00000200 -#define GPIO_DIN31_0_DIO9_S 9 +#define GPIO_DIN31_0_DIO9 0x00000200 +#define GPIO_DIN31_0_DIO9_BITN 9 +#define GPIO_DIN31_0_DIO9_M 0x00000200 +#define GPIO_DIN31_0_DIO9_S 9 // Field: [8] DIO8 // // Data input from DIO 8 -#define GPIO_DIN31_0_DIO8 0x00000100 -#define GPIO_DIN31_0_DIO8_BITN 8 -#define GPIO_DIN31_0_DIO8_M 0x00000100 -#define GPIO_DIN31_0_DIO8_S 8 +#define GPIO_DIN31_0_DIO8 0x00000100 +#define GPIO_DIN31_0_DIO8_BITN 8 +#define GPIO_DIN31_0_DIO8_M 0x00000100 +#define GPIO_DIN31_0_DIO8_S 8 // Field: [7] DIO7 // // Data input from DIO 7 -#define GPIO_DIN31_0_DIO7 0x00000080 -#define GPIO_DIN31_0_DIO7_BITN 7 -#define GPIO_DIN31_0_DIO7_M 0x00000080 -#define GPIO_DIN31_0_DIO7_S 7 +#define GPIO_DIN31_0_DIO7 0x00000080 +#define GPIO_DIN31_0_DIO7_BITN 7 +#define GPIO_DIN31_0_DIO7_M 0x00000080 +#define GPIO_DIN31_0_DIO7_S 7 // Field: [6] DIO6 // // Data input from DIO 6 -#define GPIO_DIN31_0_DIO6 0x00000040 -#define GPIO_DIN31_0_DIO6_BITN 6 -#define GPIO_DIN31_0_DIO6_M 0x00000040 -#define GPIO_DIN31_0_DIO6_S 6 +#define GPIO_DIN31_0_DIO6 0x00000040 +#define GPIO_DIN31_0_DIO6_BITN 6 +#define GPIO_DIN31_0_DIO6_M 0x00000040 +#define GPIO_DIN31_0_DIO6_S 6 // Field: [5] DIO5 // // Data input from DIO 5 -#define GPIO_DIN31_0_DIO5 0x00000020 -#define GPIO_DIN31_0_DIO5_BITN 5 -#define GPIO_DIN31_0_DIO5_M 0x00000020 -#define GPIO_DIN31_0_DIO5_S 5 +#define GPIO_DIN31_0_DIO5 0x00000020 +#define GPIO_DIN31_0_DIO5_BITN 5 +#define GPIO_DIN31_0_DIO5_M 0x00000020 +#define GPIO_DIN31_0_DIO5_S 5 // Field: [4] DIO4 // // Data input from DIO 4 -#define GPIO_DIN31_0_DIO4 0x00000010 -#define GPIO_DIN31_0_DIO4_BITN 4 -#define GPIO_DIN31_0_DIO4_M 0x00000010 -#define GPIO_DIN31_0_DIO4_S 4 +#define GPIO_DIN31_0_DIO4 0x00000010 +#define GPIO_DIN31_0_DIO4_BITN 4 +#define GPIO_DIN31_0_DIO4_M 0x00000010 +#define GPIO_DIN31_0_DIO4_S 4 // Field: [3] DIO3 // // Data input from DIO 3 -#define GPIO_DIN31_0_DIO3 0x00000008 -#define GPIO_DIN31_0_DIO3_BITN 3 -#define GPIO_DIN31_0_DIO3_M 0x00000008 -#define GPIO_DIN31_0_DIO3_S 3 +#define GPIO_DIN31_0_DIO3 0x00000008 +#define GPIO_DIN31_0_DIO3_BITN 3 +#define GPIO_DIN31_0_DIO3_M 0x00000008 +#define GPIO_DIN31_0_DIO3_S 3 // Field: [2] DIO2 // // Data input from DIO 2 -#define GPIO_DIN31_0_DIO2 0x00000004 -#define GPIO_DIN31_0_DIO2_BITN 2 -#define GPIO_DIN31_0_DIO2_M 0x00000004 -#define GPIO_DIN31_0_DIO2_S 2 +#define GPIO_DIN31_0_DIO2 0x00000004 +#define GPIO_DIN31_0_DIO2_BITN 2 +#define GPIO_DIN31_0_DIO2_M 0x00000004 +#define GPIO_DIN31_0_DIO2_S 2 // Field: [1] DIO1 // // Data input from DIO 1 -#define GPIO_DIN31_0_DIO1 0x00000002 -#define GPIO_DIN31_0_DIO1_BITN 1 -#define GPIO_DIN31_0_DIO1_M 0x00000002 -#define GPIO_DIN31_0_DIO1_S 1 +#define GPIO_DIN31_0_DIO1 0x00000002 +#define GPIO_DIN31_0_DIO1_BITN 1 +#define GPIO_DIN31_0_DIO1_M 0x00000002 +#define GPIO_DIN31_0_DIO1_S 1 // Field: [0] DIO0 // // Data input from DIO 0 -#define GPIO_DIN31_0_DIO0 0x00000001 -#define GPIO_DIN31_0_DIO0_BITN 0 -#define GPIO_DIN31_0_DIO0_M 0x00000001 -#define GPIO_DIN31_0_DIO0_S 0 +#define GPIO_DIN31_0_DIO0 0x00000001 +#define GPIO_DIN31_0_DIO0_BITN 0 +#define GPIO_DIN31_0_DIO0_M 0x00000001 +#define GPIO_DIN31_0_DIO0_S 0 //***************************************************************************** // @@ -1729,258 +1729,258 @@ // Field: [31] DIO31 // // Data output enable for DIO 31 -#define GPIO_DOE31_0_DIO31 0x80000000 -#define GPIO_DOE31_0_DIO31_BITN 31 -#define GPIO_DOE31_0_DIO31_M 0x80000000 -#define GPIO_DOE31_0_DIO31_S 31 +#define GPIO_DOE31_0_DIO31 0x80000000 +#define GPIO_DOE31_0_DIO31_BITN 31 +#define GPIO_DOE31_0_DIO31_M 0x80000000 +#define GPIO_DOE31_0_DIO31_S 31 // Field: [30] DIO30 // // Data output enable for DIO 30 -#define GPIO_DOE31_0_DIO30 0x40000000 -#define GPIO_DOE31_0_DIO30_BITN 30 -#define GPIO_DOE31_0_DIO30_M 0x40000000 -#define GPIO_DOE31_0_DIO30_S 30 +#define GPIO_DOE31_0_DIO30 0x40000000 +#define GPIO_DOE31_0_DIO30_BITN 30 +#define GPIO_DOE31_0_DIO30_M 0x40000000 +#define GPIO_DOE31_0_DIO30_S 30 // Field: [29] DIO29 // // Data output enable for DIO 29 -#define GPIO_DOE31_0_DIO29 0x20000000 -#define GPIO_DOE31_0_DIO29_BITN 29 -#define GPIO_DOE31_0_DIO29_M 0x20000000 -#define GPIO_DOE31_0_DIO29_S 29 +#define GPIO_DOE31_0_DIO29 0x20000000 +#define GPIO_DOE31_0_DIO29_BITN 29 +#define GPIO_DOE31_0_DIO29_M 0x20000000 +#define GPIO_DOE31_0_DIO29_S 29 // Field: [28] DIO28 // // Data output enable for DIO 28 -#define GPIO_DOE31_0_DIO28 0x10000000 -#define GPIO_DOE31_0_DIO28_BITN 28 -#define GPIO_DOE31_0_DIO28_M 0x10000000 -#define GPIO_DOE31_0_DIO28_S 28 +#define GPIO_DOE31_0_DIO28 0x10000000 +#define GPIO_DOE31_0_DIO28_BITN 28 +#define GPIO_DOE31_0_DIO28_M 0x10000000 +#define GPIO_DOE31_0_DIO28_S 28 // Field: [27] DIO27 // // Data output enable for DIO 27 -#define GPIO_DOE31_0_DIO27 0x08000000 -#define GPIO_DOE31_0_DIO27_BITN 27 -#define GPIO_DOE31_0_DIO27_M 0x08000000 -#define GPIO_DOE31_0_DIO27_S 27 +#define GPIO_DOE31_0_DIO27 0x08000000 +#define GPIO_DOE31_0_DIO27_BITN 27 +#define GPIO_DOE31_0_DIO27_M 0x08000000 +#define GPIO_DOE31_0_DIO27_S 27 // Field: [26] DIO26 // // Data output enable for DIO 26 -#define GPIO_DOE31_0_DIO26 0x04000000 -#define GPIO_DOE31_0_DIO26_BITN 26 -#define GPIO_DOE31_0_DIO26_M 0x04000000 -#define GPIO_DOE31_0_DIO26_S 26 +#define GPIO_DOE31_0_DIO26 0x04000000 +#define GPIO_DOE31_0_DIO26_BITN 26 +#define GPIO_DOE31_0_DIO26_M 0x04000000 +#define GPIO_DOE31_0_DIO26_S 26 // Field: [25] DIO25 // // Data output enable for DIO 25 -#define GPIO_DOE31_0_DIO25 0x02000000 -#define GPIO_DOE31_0_DIO25_BITN 25 -#define GPIO_DOE31_0_DIO25_M 0x02000000 -#define GPIO_DOE31_0_DIO25_S 25 +#define GPIO_DOE31_0_DIO25 0x02000000 +#define GPIO_DOE31_0_DIO25_BITN 25 +#define GPIO_DOE31_0_DIO25_M 0x02000000 +#define GPIO_DOE31_0_DIO25_S 25 // Field: [24] DIO24 // // Data output enable for DIO 24 -#define GPIO_DOE31_0_DIO24 0x01000000 -#define GPIO_DOE31_0_DIO24_BITN 24 -#define GPIO_DOE31_0_DIO24_M 0x01000000 -#define GPIO_DOE31_0_DIO24_S 24 +#define GPIO_DOE31_0_DIO24 0x01000000 +#define GPIO_DOE31_0_DIO24_BITN 24 +#define GPIO_DOE31_0_DIO24_M 0x01000000 +#define GPIO_DOE31_0_DIO24_S 24 // Field: [23] DIO23 // // Data output enable for DIO 23 -#define GPIO_DOE31_0_DIO23 0x00800000 -#define GPIO_DOE31_0_DIO23_BITN 23 -#define GPIO_DOE31_0_DIO23_M 0x00800000 -#define GPIO_DOE31_0_DIO23_S 23 +#define GPIO_DOE31_0_DIO23 0x00800000 +#define GPIO_DOE31_0_DIO23_BITN 23 +#define GPIO_DOE31_0_DIO23_M 0x00800000 +#define GPIO_DOE31_0_DIO23_S 23 // Field: [22] DIO22 // // Data output enable for DIO 22 -#define GPIO_DOE31_0_DIO22 0x00400000 -#define GPIO_DOE31_0_DIO22_BITN 22 -#define GPIO_DOE31_0_DIO22_M 0x00400000 -#define GPIO_DOE31_0_DIO22_S 22 +#define GPIO_DOE31_0_DIO22 0x00400000 +#define GPIO_DOE31_0_DIO22_BITN 22 +#define GPIO_DOE31_0_DIO22_M 0x00400000 +#define GPIO_DOE31_0_DIO22_S 22 // Field: [21] DIO21 // // Data output enable for DIO 21 -#define GPIO_DOE31_0_DIO21 0x00200000 -#define GPIO_DOE31_0_DIO21_BITN 21 -#define GPIO_DOE31_0_DIO21_M 0x00200000 -#define GPIO_DOE31_0_DIO21_S 21 +#define GPIO_DOE31_0_DIO21 0x00200000 +#define GPIO_DOE31_0_DIO21_BITN 21 +#define GPIO_DOE31_0_DIO21_M 0x00200000 +#define GPIO_DOE31_0_DIO21_S 21 // Field: [20] DIO20 // // Data output enable for DIO 20 -#define GPIO_DOE31_0_DIO20 0x00100000 -#define GPIO_DOE31_0_DIO20_BITN 20 -#define GPIO_DOE31_0_DIO20_M 0x00100000 -#define GPIO_DOE31_0_DIO20_S 20 +#define GPIO_DOE31_0_DIO20 0x00100000 +#define GPIO_DOE31_0_DIO20_BITN 20 +#define GPIO_DOE31_0_DIO20_M 0x00100000 +#define GPIO_DOE31_0_DIO20_S 20 // Field: [19] DIO19 // // Data output enable for DIO 19 -#define GPIO_DOE31_0_DIO19 0x00080000 -#define GPIO_DOE31_0_DIO19_BITN 19 -#define GPIO_DOE31_0_DIO19_M 0x00080000 -#define GPIO_DOE31_0_DIO19_S 19 +#define GPIO_DOE31_0_DIO19 0x00080000 +#define GPIO_DOE31_0_DIO19_BITN 19 +#define GPIO_DOE31_0_DIO19_M 0x00080000 +#define GPIO_DOE31_0_DIO19_S 19 // Field: [18] DIO18 // // Data output enable for DIO 18 -#define GPIO_DOE31_0_DIO18 0x00040000 -#define GPIO_DOE31_0_DIO18_BITN 18 -#define GPIO_DOE31_0_DIO18_M 0x00040000 -#define GPIO_DOE31_0_DIO18_S 18 +#define GPIO_DOE31_0_DIO18 0x00040000 +#define GPIO_DOE31_0_DIO18_BITN 18 +#define GPIO_DOE31_0_DIO18_M 0x00040000 +#define GPIO_DOE31_0_DIO18_S 18 // Field: [17] DIO17 // // Data output enable for DIO 17 -#define GPIO_DOE31_0_DIO17 0x00020000 -#define GPIO_DOE31_0_DIO17_BITN 17 -#define GPIO_DOE31_0_DIO17_M 0x00020000 -#define GPIO_DOE31_0_DIO17_S 17 +#define GPIO_DOE31_0_DIO17 0x00020000 +#define GPIO_DOE31_0_DIO17_BITN 17 +#define GPIO_DOE31_0_DIO17_M 0x00020000 +#define GPIO_DOE31_0_DIO17_S 17 // Field: [16] DIO16 // // Data output enable for DIO 16 -#define GPIO_DOE31_0_DIO16 0x00010000 -#define GPIO_DOE31_0_DIO16_BITN 16 -#define GPIO_DOE31_0_DIO16_M 0x00010000 -#define GPIO_DOE31_0_DIO16_S 16 +#define GPIO_DOE31_0_DIO16 0x00010000 +#define GPIO_DOE31_0_DIO16_BITN 16 +#define GPIO_DOE31_0_DIO16_M 0x00010000 +#define GPIO_DOE31_0_DIO16_S 16 // Field: [15] DIO15 // // Data output enable for DIO 15 -#define GPIO_DOE31_0_DIO15 0x00008000 -#define GPIO_DOE31_0_DIO15_BITN 15 -#define GPIO_DOE31_0_DIO15_M 0x00008000 -#define GPIO_DOE31_0_DIO15_S 15 +#define GPIO_DOE31_0_DIO15 0x00008000 +#define GPIO_DOE31_0_DIO15_BITN 15 +#define GPIO_DOE31_0_DIO15_M 0x00008000 +#define GPIO_DOE31_0_DIO15_S 15 // Field: [14] DIO14 // // Data output enable for DIO 14 -#define GPIO_DOE31_0_DIO14 0x00004000 -#define GPIO_DOE31_0_DIO14_BITN 14 -#define GPIO_DOE31_0_DIO14_M 0x00004000 -#define GPIO_DOE31_0_DIO14_S 14 +#define GPIO_DOE31_0_DIO14 0x00004000 +#define GPIO_DOE31_0_DIO14_BITN 14 +#define GPIO_DOE31_0_DIO14_M 0x00004000 +#define GPIO_DOE31_0_DIO14_S 14 // Field: [13] DIO13 // // Data output enable for DIO 13 -#define GPIO_DOE31_0_DIO13 0x00002000 -#define GPIO_DOE31_0_DIO13_BITN 13 -#define GPIO_DOE31_0_DIO13_M 0x00002000 -#define GPIO_DOE31_0_DIO13_S 13 +#define GPIO_DOE31_0_DIO13 0x00002000 +#define GPIO_DOE31_0_DIO13_BITN 13 +#define GPIO_DOE31_0_DIO13_M 0x00002000 +#define GPIO_DOE31_0_DIO13_S 13 // Field: [12] DIO12 // // Data output enable for DIO 12 -#define GPIO_DOE31_0_DIO12 0x00001000 -#define GPIO_DOE31_0_DIO12_BITN 12 -#define GPIO_DOE31_0_DIO12_M 0x00001000 -#define GPIO_DOE31_0_DIO12_S 12 +#define GPIO_DOE31_0_DIO12 0x00001000 +#define GPIO_DOE31_0_DIO12_BITN 12 +#define GPIO_DOE31_0_DIO12_M 0x00001000 +#define GPIO_DOE31_0_DIO12_S 12 // Field: [11] DIO11 // // Data output enable for DIO 11 -#define GPIO_DOE31_0_DIO11 0x00000800 -#define GPIO_DOE31_0_DIO11_BITN 11 -#define GPIO_DOE31_0_DIO11_M 0x00000800 -#define GPIO_DOE31_0_DIO11_S 11 +#define GPIO_DOE31_0_DIO11 0x00000800 +#define GPIO_DOE31_0_DIO11_BITN 11 +#define GPIO_DOE31_0_DIO11_M 0x00000800 +#define GPIO_DOE31_0_DIO11_S 11 // Field: [10] DIO10 // // Data output enable for DIO 10 -#define GPIO_DOE31_0_DIO10 0x00000400 -#define GPIO_DOE31_0_DIO10_BITN 10 -#define GPIO_DOE31_0_DIO10_M 0x00000400 -#define GPIO_DOE31_0_DIO10_S 10 +#define GPIO_DOE31_0_DIO10 0x00000400 +#define GPIO_DOE31_0_DIO10_BITN 10 +#define GPIO_DOE31_0_DIO10_M 0x00000400 +#define GPIO_DOE31_0_DIO10_S 10 // Field: [9] DIO9 // // Data output enable for DIO 9 -#define GPIO_DOE31_0_DIO9 0x00000200 -#define GPIO_DOE31_0_DIO9_BITN 9 -#define GPIO_DOE31_0_DIO9_M 0x00000200 -#define GPIO_DOE31_0_DIO9_S 9 +#define GPIO_DOE31_0_DIO9 0x00000200 +#define GPIO_DOE31_0_DIO9_BITN 9 +#define GPIO_DOE31_0_DIO9_M 0x00000200 +#define GPIO_DOE31_0_DIO9_S 9 // Field: [8] DIO8 // // Data output enable for DIO 8 -#define GPIO_DOE31_0_DIO8 0x00000100 -#define GPIO_DOE31_0_DIO8_BITN 8 -#define GPIO_DOE31_0_DIO8_M 0x00000100 -#define GPIO_DOE31_0_DIO8_S 8 +#define GPIO_DOE31_0_DIO8 0x00000100 +#define GPIO_DOE31_0_DIO8_BITN 8 +#define GPIO_DOE31_0_DIO8_M 0x00000100 +#define GPIO_DOE31_0_DIO8_S 8 // Field: [7] DIO7 // // Data output enable for DIO 7 -#define GPIO_DOE31_0_DIO7 0x00000080 -#define GPIO_DOE31_0_DIO7_BITN 7 -#define GPIO_DOE31_0_DIO7_M 0x00000080 -#define GPIO_DOE31_0_DIO7_S 7 +#define GPIO_DOE31_0_DIO7 0x00000080 +#define GPIO_DOE31_0_DIO7_BITN 7 +#define GPIO_DOE31_0_DIO7_M 0x00000080 +#define GPIO_DOE31_0_DIO7_S 7 // Field: [6] DIO6 // // Data output enable for DIO 6 -#define GPIO_DOE31_0_DIO6 0x00000040 -#define GPIO_DOE31_0_DIO6_BITN 6 -#define GPIO_DOE31_0_DIO6_M 0x00000040 -#define GPIO_DOE31_0_DIO6_S 6 +#define GPIO_DOE31_0_DIO6 0x00000040 +#define GPIO_DOE31_0_DIO6_BITN 6 +#define GPIO_DOE31_0_DIO6_M 0x00000040 +#define GPIO_DOE31_0_DIO6_S 6 // Field: [5] DIO5 // // Data output enable for DIO 5 -#define GPIO_DOE31_0_DIO5 0x00000020 -#define GPIO_DOE31_0_DIO5_BITN 5 -#define GPIO_DOE31_0_DIO5_M 0x00000020 -#define GPIO_DOE31_0_DIO5_S 5 +#define GPIO_DOE31_0_DIO5 0x00000020 +#define GPIO_DOE31_0_DIO5_BITN 5 +#define GPIO_DOE31_0_DIO5_M 0x00000020 +#define GPIO_DOE31_0_DIO5_S 5 // Field: [4] DIO4 // // Data output enable for DIO 4 -#define GPIO_DOE31_0_DIO4 0x00000010 -#define GPIO_DOE31_0_DIO4_BITN 4 -#define GPIO_DOE31_0_DIO4_M 0x00000010 -#define GPIO_DOE31_0_DIO4_S 4 +#define GPIO_DOE31_0_DIO4 0x00000010 +#define GPIO_DOE31_0_DIO4_BITN 4 +#define GPIO_DOE31_0_DIO4_M 0x00000010 +#define GPIO_DOE31_0_DIO4_S 4 // Field: [3] DIO3 // // Data output enable for DIO 3 -#define GPIO_DOE31_0_DIO3 0x00000008 -#define GPIO_DOE31_0_DIO3_BITN 3 -#define GPIO_DOE31_0_DIO3_M 0x00000008 -#define GPIO_DOE31_0_DIO3_S 3 +#define GPIO_DOE31_0_DIO3 0x00000008 +#define GPIO_DOE31_0_DIO3_BITN 3 +#define GPIO_DOE31_0_DIO3_M 0x00000008 +#define GPIO_DOE31_0_DIO3_S 3 // Field: [2] DIO2 // // Data output enable for DIO 2 -#define GPIO_DOE31_0_DIO2 0x00000004 -#define GPIO_DOE31_0_DIO2_BITN 2 -#define GPIO_DOE31_0_DIO2_M 0x00000004 -#define GPIO_DOE31_0_DIO2_S 2 +#define GPIO_DOE31_0_DIO2 0x00000004 +#define GPIO_DOE31_0_DIO2_BITN 2 +#define GPIO_DOE31_0_DIO2_M 0x00000004 +#define GPIO_DOE31_0_DIO2_S 2 // Field: [1] DIO1 // // Data output enable for DIO 1 -#define GPIO_DOE31_0_DIO1 0x00000002 -#define GPIO_DOE31_0_DIO1_BITN 1 -#define GPIO_DOE31_0_DIO1_M 0x00000002 -#define GPIO_DOE31_0_DIO1_S 1 +#define GPIO_DOE31_0_DIO1 0x00000002 +#define GPIO_DOE31_0_DIO1_BITN 1 +#define GPIO_DOE31_0_DIO1_M 0x00000002 +#define GPIO_DOE31_0_DIO1_S 1 // Field: [0] DIO0 // // Data output enable for DIO 0 -#define GPIO_DOE31_0_DIO0 0x00000001 -#define GPIO_DOE31_0_DIO0_BITN 0 -#define GPIO_DOE31_0_DIO0_M 0x00000001 -#define GPIO_DOE31_0_DIO0_S 0 +#define GPIO_DOE31_0_DIO0 0x00000001 +#define GPIO_DOE31_0_DIO0_BITN 0 +#define GPIO_DOE31_0_DIO0_M 0x00000001 +#define GPIO_DOE31_0_DIO0_S 0 //***************************************************************************** // @@ -1990,258 +1990,257 @@ // Field: [31] DIO31 // // Event for DIO 31 -#define GPIO_EVFLAGS31_0_DIO31 0x80000000 -#define GPIO_EVFLAGS31_0_DIO31_BITN 31 -#define GPIO_EVFLAGS31_0_DIO31_M 0x80000000 -#define GPIO_EVFLAGS31_0_DIO31_S 31 +#define GPIO_EVFLAGS31_0_DIO31 0x80000000 +#define GPIO_EVFLAGS31_0_DIO31_BITN 31 +#define GPIO_EVFLAGS31_0_DIO31_M 0x80000000 +#define GPIO_EVFLAGS31_0_DIO31_S 31 // Field: [30] DIO30 // // Event for DIO 30 -#define GPIO_EVFLAGS31_0_DIO30 0x40000000 -#define GPIO_EVFLAGS31_0_DIO30_BITN 30 -#define GPIO_EVFLAGS31_0_DIO30_M 0x40000000 -#define GPIO_EVFLAGS31_0_DIO30_S 30 +#define GPIO_EVFLAGS31_0_DIO30 0x40000000 +#define GPIO_EVFLAGS31_0_DIO30_BITN 30 +#define GPIO_EVFLAGS31_0_DIO30_M 0x40000000 +#define GPIO_EVFLAGS31_0_DIO30_S 30 // Field: [29] DIO29 // // Event for DIO 29 -#define GPIO_EVFLAGS31_0_DIO29 0x20000000 -#define GPIO_EVFLAGS31_0_DIO29_BITN 29 -#define GPIO_EVFLAGS31_0_DIO29_M 0x20000000 -#define GPIO_EVFLAGS31_0_DIO29_S 29 +#define GPIO_EVFLAGS31_0_DIO29 0x20000000 +#define GPIO_EVFLAGS31_0_DIO29_BITN 29 +#define GPIO_EVFLAGS31_0_DIO29_M 0x20000000 +#define GPIO_EVFLAGS31_0_DIO29_S 29 // Field: [28] DIO28 // // Event for DIO 28 -#define GPIO_EVFLAGS31_0_DIO28 0x10000000 -#define GPIO_EVFLAGS31_0_DIO28_BITN 28 -#define GPIO_EVFLAGS31_0_DIO28_M 0x10000000 -#define GPIO_EVFLAGS31_0_DIO28_S 28 +#define GPIO_EVFLAGS31_0_DIO28 0x10000000 +#define GPIO_EVFLAGS31_0_DIO28_BITN 28 +#define GPIO_EVFLAGS31_0_DIO28_M 0x10000000 +#define GPIO_EVFLAGS31_0_DIO28_S 28 // Field: [27] DIO27 // // Event for DIO 27 -#define GPIO_EVFLAGS31_0_DIO27 0x08000000 -#define GPIO_EVFLAGS31_0_DIO27_BITN 27 -#define GPIO_EVFLAGS31_0_DIO27_M 0x08000000 -#define GPIO_EVFLAGS31_0_DIO27_S 27 +#define GPIO_EVFLAGS31_0_DIO27 0x08000000 +#define GPIO_EVFLAGS31_0_DIO27_BITN 27 +#define GPIO_EVFLAGS31_0_DIO27_M 0x08000000 +#define GPIO_EVFLAGS31_0_DIO27_S 27 // Field: [26] DIO26 // // Event for DIO 26 -#define GPIO_EVFLAGS31_0_DIO26 0x04000000 -#define GPIO_EVFLAGS31_0_DIO26_BITN 26 -#define GPIO_EVFLAGS31_0_DIO26_M 0x04000000 -#define GPIO_EVFLAGS31_0_DIO26_S 26 +#define GPIO_EVFLAGS31_0_DIO26 0x04000000 +#define GPIO_EVFLAGS31_0_DIO26_BITN 26 +#define GPIO_EVFLAGS31_0_DIO26_M 0x04000000 +#define GPIO_EVFLAGS31_0_DIO26_S 26 // Field: [25] DIO25 // // Event for DIO 25 -#define GPIO_EVFLAGS31_0_DIO25 0x02000000 -#define GPIO_EVFLAGS31_0_DIO25_BITN 25 -#define GPIO_EVFLAGS31_0_DIO25_M 0x02000000 -#define GPIO_EVFLAGS31_0_DIO25_S 25 +#define GPIO_EVFLAGS31_0_DIO25 0x02000000 +#define GPIO_EVFLAGS31_0_DIO25_BITN 25 +#define GPIO_EVFLAGS31_0_DIO25_M 0x02000000 +#define GPIO_EVFLAGS31_0_DIO25_S 25 // Field: [24] DIO24 // // Event for DIO 24 -#define GPIO_EVFLAGS31_0_DIO24 0x01000000 -#define GPIO_EVFLAGS31_0_DIO24_BITN 24 -#define GPIO_EVFLAGS31_0_DIO24_M 0x01000000 -#define GPIO_EVFLAGS31_0_DIO24_S 24 +#define GPIO_EVFLAGS31_0_DIO24 0x01000000 +#define GPIO_EVFLAGS31_0_DIO24_BITN 24 +#define GPIO_EVFLAGS31_0_DIO24_M 0x01000000 +#define GPIO_EVFLAGS31_0_DIO24_S 24 // Field: [23] DIO23 // // Event for DIO 23 -#define GPIO_EVFLAGS31_0_DIO23 0x00800000 -#define GPIO_EVFLAGS31_0_DIO23_BITN 23 -#define GPIO_EVFLAGS31_0_DIO23_M 0x00800000 -#define GPIO_EVFLAGS31_0_DIO23_S 23 +#define GPIO_EVFLAGS31_0_DIO23 0x00800000 +#define GPIO_EVFLAGS31_0_DIO23_BITN 23 +#define GPIO_EVFLAGS31_0_DIO23_M 0x00800000 +#define GPIO_EVFLAGS31_0_DIO23_S 23 // Field: [22] DIO22 // // Event for DIO 22 -#define GPIO_EVFLAGS31_0_DIO22 0x00400000 -#define GPIO_EVFLAGS31_0_DIO22_BITN 22 -#define GPIO_EVFLAGS31_0_DIO22_M 0x00400000 -#define GPIO_EVFLAGS31_0_DIO22_S 22 +#define GPIO_EVFLAGS31_0_DIO22 0x00400000 +#define GPIO_EVFLAGS31_0_DIO22_BITN 22 +#define GPIO_EVFLAGS31_0_DIO22_M 0x00400000 +#define GPIO_EVFLAGS31_0_DIO22_S 22 // Field: [21] DIO21 // // Event for DIO 21 -#define GPIO_EVFLAGS31_0_DIO21 0x00200000 -#define GPIO_EVFLAGS31_0_DIO21_BITN 21 -#define GPIO_EVFLAGS31_0_DIO21_M 0x00200000 -#define GPIO_EVFLAGS31_0_DIO21_S 21 +#define GPIO_EVFLAGS31_0_DIO21 0x00200000 +#define GPIO_EVFLAGS31_0_DIO21_BITN 21 +#define GPIO_EVFLAGS31_0_DIO21_M 0x00200000 +#define GPIO_EVFLAGS31_0_DIO21_S 21 // Field: [20] DIO20 // // Event for DIO 20 -#define GPIO_EVFLAGS31_0_DIO20 0x00100000 -#define GPIO_EVFLAGS31_0_DIO20_BITN 20 -#define GPIO_EVFLAGS31_0_DIO20_M 0x00100000 -#define GPIO_EVFLAGS31_0_DIO20_S 20 +#define GPIO_EVFLAGS31_0_DIO20 0x00100000 +#define GPIO_EVFLAGS31_0_DIO20_BITN 20 +#define GPIO_EVFLAGS31_0_DIO20_M 0x00100000 +#define GPIO_EVFLAGS31_0_DIO20_S 20 // Field: [19] DIO19 // // Event for DIO 19 -#define GPIO_EVFLAGS31_0_DIO19 0x00080000 -#define GPIO_EVFLAGS31_0_DIO19_BITN 19 -#define GPIO_EVFLAGS31_0_DIO19_M 0x00080000 -#define GPIO_EVFLAGS31_0_DIO19_S 19 +#define GPIO_EVFLAGS31_0_DIO19 0x00080000 +#define GPIO_EVFLAGS31_0_DIO19_BITN 19 +#define GPIO_EVFLAGS31_0_DIO19_M 0x00080000 +#define GPIO_EVFLAGS31_0_DIO19_S 19 // Field: [18] DIO18 // // Event for DIO 18 -#define GPIO_EVFLAGS31_0_DIO18 0x00040000 -#define GPIO_EVFLAGS31_0_DIO18_BITN 18 -#define GPIO_EVFLAGS31_0_DIO18_M 0x00040000 -#define GPIO_EVFLAGS31_0_DIO18_S 18 +#define GPIO_EVFLAGS31_0_DIO18 0x00040000 +#define GPIO_EVFLAGS31_0_DIO18_BITN 18 +#define GPIO_EVFLAGS31_0_DIO18_M 0x00040000 +#define GPIO_EVFLAGS31_0_DIO18_S 18 // Field: [17] DIO17 // // Event for DIO 17 -#define GPIO_EVFLAGS31_0_DIO17 0x00020000 -#define GPIO_EVFLAGS31_0_DIO17_BITN 17 -#define GPIO_EVFLAGS31_0_DIO17_M 0x00020000 -#define GPIO_EVFLAGS31_0_DIO17_S 17 +#define GPIO_EVFLAGS31_0_DIO17 0x00020000 +#define GPIO_EVFLAGS31_0_DIO17_BITN 17 +#define GPIO_EVFLAGS31_0_DIO17_M 0x00020000 +#define GPIO_EVFLAGS31_0_DIO17_S 17 // Field: [16] DIO16 // // Event for DIO 16 -#define GPIO_EVFLAGS31_0_DIO16 0x00010000 -#define GPIO_EVFLAGS31_0_DIO16_BITN 16 -#define GPIO_EVFLAGS31_0_DIO16_M 0x00010000 -#define GPIO_EVFLAGS31_0_DIO16_S 16 +#define GPIO_EVFLAGS31_0_DIO16 0x00010000 +#define GPIO_EVFLAGS31_0_DIO16_BITN 16 +#define GPIO_EVFLAGS31_0_DIO16_M 0x00010000 +#define GPIO_EVFLAGS31_0_DIO16_S 16 // Field: [15] DIO15 // // Event for DIO 15 -#define GPIO_EVFLAGS31_0_DIO15 0x00008000 -#define GPIO_EVFLAGS31_0_DIO15_BITN 15 -#define GPIO_EVFLAGS31_0_DIO15_M 0x00008000 -#define GPIO_EVFLAGS31_0_DIO15_S 15 +#define GPIO_EVFLAGS31_0_DIO15 0x00008000 +#define GPIO_EVFLAGS31_0_DIO15_BITN 15 +#define GPIO_EVFLAGS31_0_DIO15_M 0x00008000 +#define GPIO_EVFLAGS31_0_DIO15_S 15 // Field: [14] DIO14 // // Event for DIO 14 -#define GPIO_EVFLAGS31_0_DIO14 0x00004000 -#define GPIO_EVFLAGS31_0_DIO14_BITN 14 -#define GPIO_EVFLAGS31_0_DIO14_M 0x00004000 -#define GPIO_EVFLAGS31_0_DIO14_S 14 +#define GPIO_EVFLAGS31_0_DIO14 0x00004000 +#define GPIO_EVFLAGS31_0_DIO14_BITN 14 +#define GPIO_EVFLAGS31_0_DIO14_M 0x00004000 +#define GPIO_EVFLAGS31_0_DIO14_S 14 // Field: [13] DIO13 // // Event for DIO 13 -#define GPIO_EVFLAGS31_0_DIO13 0x00002000 -#define GPIO_EVFLAGS31_0_DIO13_BITN 13 -#define GPIO_EVFLAGS31_0_DIO13_M 0x00002000 -#define GPIO_EVFLAGS31_0_DIO13_S 13 +#define GPIO_EVFLAGS31_0_DIO13 0x00002000 +#define GPIO_EVFLAGS31_0_DIO13_BITN 13 +#define GPIO_EVFLAGS31_0_DIO13_M 0x00002000 +#define GPIO_EVFLAGS31_0_DIO13_S 13 // Field: [12] DIO12 // // Event for DIO 12 -#define GPIO_EVFLAGS31_0_DIO12 0x00001000 -#define GPIO_EVFLAGS31_0_DIO12_BITN 12 -#define GPIO_EVFLAGS31_0_DIO12_M 0x00001000 -#define GPIO_EVFLAGS31_0_DIO12_S 12 +#define GPIO_EVFLAGS31_0_DIO12 0x00001000 +#define GPIO_EVFLAGS31_0_DIO12_BITN 12 +#define GPIO_EVFLAGS31_0_DIO12_M 0x00001000 +#define GPIO_EVFLAGS31_0_DIO12_S 12 // Field: [11] DIO11 // // Event for DIO 11 -#define GPIO_EVFLAGS31_0_DIO11 0x00000800 -#define GPIO_EVFLAGS31_0_DIO11_BITN 11 -#define GPIO_EVFLAGS31_0_DIO11_M 0x00000800 -#define GPIO_EVFLAGS31_0_DIO11_S 11 +#define GPIO_EVFLAGS31_0_DIO11 0x00000800 +#define GPIO_EVFLAGS31_0_DIO11_BITN 11 +#define GPIO_EVFLAGS31_0_DIO11_M 0x00000800 +#define GPIO_EVFLAGS31_0_DIO11_S 11 // Field: [10] DIO10 // // Event for DIO 10 -#define GPIO_EVFLAGS31_0_DIO10 0x00000400 -#define GPIO_EVFLAGS31_0_DIO10_BITN 10 -#define GPIO_EVFLAGS31_0_DIO10_M 0x00000400 -#define GPIO_EVFLAGS31_0_DIO10_S 10 +#define GPIO_EVFLAGS31_0_DIO10 0x00000400 +#define GPIO_EVFLAGS31_0_DIO10_BITN 10 +#define GPIO_EVFLAGS31_0_DIO10_M 0x00000400 +#define GPIO_EVFLAGS31_0_DIO10_S 10 // Field: [9] DIO9 // // Event for DIO 9 -#define GPIO_EVFLAGS31_0_DIO9 0x00000200 -#define GPIO_EVFLAGS31_0_DIO9_BITN 9 -#define GPIO_EVFLAGS31_0_DIO9_M 0x00000200 -#define GPIO_EVFLAGS31_0_DIO9_S 9 +#define GPIO_EVFLAGS31_0_DIO9 0x00000200 +#define GPIO_EVFLAGS31_0_DIO9_BITN 9 +#define GPIO_EVFLAGS31_0_DIO9_M 0x00000200 +#define GPIO_EVFLAGS31_0_DIO9_S 9 // Field: [8] DIO8 // // Event for DIO 8 -#define GPIO_EVFLAGS31_0_DIO8 0x00000100 -#define GPIO_EVFLAGS31_0_DIO8_BITN 8 -#define GPIO_EVFLAGS31_0_DIO8_M 0x00000100 -#define GPIO_EVFLAGS31_0_DIO8_S 8 +#define GPIO_EVFLAGS31_0_DIO8 0x00000100 +#define GPIO_EVFLAGS31_0_DIO8_BITN 8 +#define GPIO_EVFLAGS31_0_DIO8_M 0x00000100 +#define GPIO_EVFLAGS31_0_DIO8_S 8 // Field: [7] DIO7 // // Event for DIO 7 -#define GPIO_EVFLAGS31_0_DIO7 0x00000080 -#define GPIO_EVFLAGS31_0_DIO7_BITN 7 -#define GPIO_EVFLAGS31_0_DIO7_M 0x00000080 -#define GPIO_EVFLAGS31_0_DIO7_S 7 +#define GPIO_EVFLAGS31_0_DIO7 0x00000080 +#define GPIO_EVFLAGS31_0_DIO7_BITN 7 +#define GPIO_EVFLAGS31_0_DIO7_M 0x00000080 +#define GPIO_EVFLAGS31_0_DIO7_S 7 // Field: [6] DIO6 // // Event for DIO 6 -#define GPIO_EVFLAGS31_0_DIO6 0x00000040 -#define GPIO_EVFLAGS31_0_DIO6_BITN 6 -#define GPIO_EVFLAGS31_0_DIO6_M 0x00000040 -#define GPIO_EVFLAGS31_0_DIO6_S 6 +#define GPIO_EVFLAGS31_0_DIO6 0x00000040 +#define GPIO_EVFLAGS31_0_DIO6_BITN 6 +#define GPIO_EVFLAGS31_0_DIO6_M 0x00000040 +#define GPIO_EVFLAGS31_0_DIO6_S 6 // Field: [5] DIO5 // // Event for DIO 5 -#define GPIO_EVFLAGS31_0_DIO5 0x00000020 -#define GPIO_EVFLAGS31_0_DIO5_BITN 5 -#define GPIO_EVFLAGS31_0_DIO5_M 0x00000020 -#define GPIO_EVFLAGS31_0_DIO5_S 5 +#define GPIO_EVFLAGS31_0_DIO5 0x00000020 +#define GPIO_EVFLAGS31_0_DIO5_BITN 5 +#define GPIO_EVFLAGS31_0_DIO5_M 0x00000020 +#define GPIO_EVFLAGS31_0_DIO5_S 5 // Field: [4] DIO4 // // Event for DIO 4 -#define GPIO_EVFLAGS31_0_DIO4 0x00000010 -#define GPIO_EVFLAGS31_0_DIO4_BITN 4 -#define GPIO_EVFLAGS31_0_DIO4_M 0x00000010 -#define GPIO_EVFLAGS31_0_DIO4_S 4 +#define GPIO_EVFLAGS31_0_DIO4 0x00000010 +#define GPIO_EVFLAGS31_0_DIO4_BITN 4 +#define GPIO_EVFLAGS31_0_DIO4_M 0x00000010 +#define GPIO_EVFLAGS31_0_DIO4_S 4 // Field: [3] DIO3 // // Event for DIO 3 -#define GPIO_EVFLAGS31_0_DIO3 0x00000008 -#define GPIO_EVFLAGS31_0_DIO3_BITN 3 -#define GPIO_EVFLAGS31_0_DIO3_M 0x00000008 -#define GPIO_EVFLAGS31_0_DIO3_S 3 +#define GPIO_EVFLAGS31_0_DIO3 0x00000008 +#define GPIO_EVFLAGS31_0_DIO3_BITN 3 +#define GPIO_EVFLAGS31_0_DIO3_M 0x00000008 +#define GPIO_EVFLAGS31_0_DIO3_S 3 // Field: [2] DIO2 // // Event for DIO 2 -#define GPIO_EVFLAGS31_0_DIO2 0x00000004 -#define GPIO_EVFLAGS31_0_DIO2_BITN 2 -#define GPIO_EVFLAGS31_0_DIO2_M 0x00000004 -#define GPIO_EVFLAGS31_0_DIO2_S 2 +#define GPIO_EVFLAGS31_0_DIO2 0x00000004 +#define GPIO_EVFLAGS31_0_DIO2_BITN 2 +#define GPIO_EVFLAGS31_0_DIO2_M 0x00000004 +#define GPIO_EVFLAGS31_0_DIO2_S 2 // Field: [1] DIO1 // // Event for DIO 1 -#define GPIO_EVFLAGS31_0_DIO1 0x00000002 -#define GPIO_EVFLAGS31_0_DIO1_BITN 1 -#define GPIO_EVFLAGS31_0_DIO1_M 0x00000002 -#define GPIO_EVFLAGS31_0_DIO1_S 1 +#define GPIO_EVFLAGS31_0_DIO1 0x00000002 +#define GPIO_EVFLAGS31_0_DIO1_BITN 1 +#define GPIO_EVFLAGS31_0_DIO1_M 0x00000002 +#define GPIO_EVFLAGS31_0_DIO1_S 1 // Field: [0] DIO0 // // Event for DIO 0 -#define GPIO_EVFLAGS31_0_DIO0 0x00000001 -#define GPIO_EVFLAGS31_0_DIO0_BITN 0 -#define GPIO_EVFLAGS31_0_DIO0_M 0x00000001 -#define GPIO_EVFLAGS31_0_DIO0_S 0 - +#define GPIO_EVFLAGS31_0_DIO0 0x00000001 +#define GPIO_EVFLAGS31_0_DIO0_BITN 0 +#define GPIO_EVFLAGS31_0_DIO0_M 0x00000001 +#define GPIO_EVFLAGS31_0_DIO0_S 0 #endif // __GPIO__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_gpt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_gpt.h index 710edd8..4836c50 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_gpt.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_gpt.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_gpt_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_gpt_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_GPT_H__ #define __HW_GPT_H__ @@ -44,88 +44,88 @@ // //***************************************************************************** // Configuration -#define GPT_O_CFG 0x00000000 +#define GPT_O_CFG 0x00000000 // Timer A Mode -#define GPT_O_TAMR 0x00000004 +#define GPT_O_TAMR 0x00000004 // Timer B Mode -#define GPT_O_TBMR 0x00000008 +#define GPT_O_TBMR 0x00000008 // Control -#define GPT_O_CTL 0x0000000C +#define GPT_O_CTL 0x0000000C // Synch Register -#define GPT_O_SYNC 0x00000010 +#define GPT_O_SYNC 0x00000010 // Interrupt Mask -#define GPT_O_IMR 0x00000018 +#define GPT_O_IMR 0x00000018 // Raw Interrupt Status -#define GPT_O_RIS 0x0000001C +#define GPT_O_RIS 0x0000001C // Masked Interrupt Status -#define GPT_O_MIS 0x00000020 +#define GPT_O_MIS 0x00000020 // Interrupt Clear -#define GPT_O_ICLR 0x00000024 +#define GPT_O_ICLR 0x00000024 // Timer A Interval Load Register -#define GPT_O_TAILR 0x00000028 +#define GPT_O_TAILR 0x00000028 // Timer B Interval Load Register -#define GPT_O_TBILR 0x0000002C +#define GPT_O_TBILR 0x0000002C // Timer A Match Register -#define GPT_O_TAMATCHR 0x00000030 +#define GPT_O_TAMATCHR 0x00000030 // Timer B Match Register -#define GPT_O_TBMATCHR 0x00000034 +#define GPT_O_TBMATCHR 0x00000034 // Timer A Pre-scale -#define GPT_O_TAPR 0x00000038 +#define GPT_O_TAPR 0x00000038 // Timer B Pre-scale -#define GPT_O_TBPR 0x0000003C +#define GPT_O_TBPR 0x0000003C // Timer A Pre-scale Match -#define GPT_O_TAPMR 0x00000040 +#define GPT_O_TAPMR 0x00000040 // Timer B Pre-scale Match -#define GPT_O_TBPMR 0x00000044 +#define GPT_O_TBPMR 0x00000044 // Timer A Register -#define GPT_O_TAR 0x00000048 +#define GPT_O_TAR 0x00000048 // Timer B Register -#define GPT_O_TBR 0x0000004C +#define GPT_O_TBR 0x0000004C // Timer A Value -#define GPT_O_TAV 0x00000050 +#define GPT_O_TAV 0x00000050 // Timer B Value -#define GPT_O_TBV 0x00000054 +#define GPT_O_TBV 0x00000054 // Timer A Pre-scale Snap-shot -#define GPT_O_TAPS 0x0000005C +#define GPT_O_TAPS 0x0000005C // Timer B Pre-scale Snap-shot -#define GPT_O_TBPS 0x00000060 +#define GPT_O_TBPS 0x00000060 // Timer A Pre-scale Value -#define GPT_O_TAPV 0x00000064 +#define GPT_O_TAPV 0x00000064 // Timer B Pre-scale Value -#define GPT_O_TBPV 0x00000068 +#define GPT_O_TBPV 0x00000068 // DMA Event -#define GPT_O_DMAEV 0x0000006C +#define GPT_O_DMAEV 0x0000006C // Peripheral Version -#define GPT_O_VERSION 0x00000FB0 +#define GPT_O_VERSION 0x00000FB0 // Combined CCP Output -#define GPT_O_ANDCCP 0x00000FB4 +#define GPT_O_ANDCCP 0x00000FB4 //***************************************************************************** // @@ -144,11 +144,11 @@ // Also see TAMR.TAMR and // TBMR.TBMR. // 32BIT_TIMER 32-bit timer configuration -#define GPT_CFG_CFG_W 3 -#define GPT_CFG_CFG_M 0x00000007 -#define GPT_CFG_CFG_S 0 -#define GPT_CFG_CFG_16BIT_TIMER 0x00000004 -#define GPT_CFG_CFG_32BIT_TIMER 0x00000000 +#define GPT_CFG_CFG_W 3 +#define GPT_CFG_CFG_M 0x00000007 +#define GPT_CFG_CFG_S 0 +#define GPT_CFG_CFG_16BIT_TIMER 0x00000004 +#define GPT_CFG_CFG_32BIT_TIMER 0x00000000 //***************************************************************************** // @@ -171,17 +171,17 @@ // CLR_ON_TO Clear CCP output pin on Time-Out // TOG_ON_TO Toggle State on Time-Out // DIS_CMP Disable compare operations -#define GPT_TAMR_TCACT_W 3 -#define GPT_TAMR_TCACT_M 0x0000E000 -#define GPT_TAMR_TCACT_S 13 -#define GPT_TAMR_TCACT_CLRSET_ON_TO 0x0000E000 -#define GPT_TAMR_TCACT_SETCLR_ON_TO 0x0000C000 -#define GPT_TAMR_TCACT_CLRTOG_ON_TO 0x0000A000 -#define GPT_TAMR_TCACT_SETTOG_ON_TO 0x00008000 -#define GPT_TAMR_TCACT_SET_ON_TO 0x00006000 -#define GPT_TAMR_TCACT_CLR_ON_TO 0x00004000 -#define GPT_TAMR_TCACT_TOG_ON_TO 0x00002000 -#define GPT_TAMR_TCACT_DIS_CMP 0x00000000 +#define GPT_TAMR_TCACT_W 3 +#define GPT_TAMR_TCACT_M 0x0000E000 +#define GPT_TAMR_TCACT_S 13 +#define GPT_TAMR_TCACT_CLRSET_ON_TO 0x0000E000 +#define GPT_TAMR_TCACT_SETCLR_ON_TO 0x0000C000 +#define GPT_TAMR_TCACT_CLRTOG_ON_TO 0x0000A000 +#define GPT_TAMR_TCACT_SETTOG_ON_TO 0x00008000 +#define GPT_TAMR_TCACT_SET_ON_TO 0x00006000 +#define GPT_TAMR_TCACT_CLR_ON_TO 0x00004000 +#define GPT_TAMR_TCACT_TOG_ON_TO 0x00002000 +#define GPT_TAMR_TCACT_DIS_CMP 0x00000000 // Field: [12] TACINTD // @@ -189,12 +189,12 @@ // ENUMs: // DIS_TO_INTR Time-out interrupt are disabled // EN_TO_INTR Time-out interrupt function as normal -#define GPT_TAMR_TACINTD 0x00001000 -#define GPT_TAMR_TACINTD_BITN 12 -#define GPT_TAMR_TACINTD_M 0x00001000 -#define GPT_TAMR_TACINTD_S 12 -#define GPT_TAMR_TACINTD_DIS_TO_INTR 0x00001000 -#define GPT_TAMR_TACINTD_EN_TO_INTR 0x00000000 +#define GPT_TAMR_TACINTD 0x00001000 +#define GPT_TAMR_TACINTD_BITN 12 +#define GPT_TAMR_TACINTD_M 0x00001000 +#define GPT_TAMR_TACINTD_S 12 +#define GPT_TAMR_TACINTD_DIS_TO_INTR 0x00001000 +#define GPT_TAMR_TACINTD_EN_TO_INTR 0x00000000 // Field: [11] TAPLO // @@ -210,12 +210,12 @@ // ENUMs: // CCP_ON_TO CCP output pin is set to 1 on time-out // LEGACY Legacy operation -#define GPT_TAMR_TAPLO 0x00000800 -#define GPT_TAMR_TAPLO_BITN 11 -#define GPT_TAMR_TAPLO_M 0x00000800 -#define GPT_TAMR_TAPLO_S 11 -#define GPT_TAMR_TAPLO_CCP_ON_TO 0x00000800 -#define GPT_TAMR_TAPLO_LEGACY 0x00000000 +#define GPT_TAMR_TAPLO 0x00000800 +#define GPT_TAMR_TAPLO_BITN 11 +#define GPT_TAMR_TAPLO_M 0x00000800 +#define GPT_TAMR_TAPLO_S 11 +#define GPT_TAMR_TAPLO_CCP_ON_TO 0x00000800 +#define GPT_TAMR_TAPLO_LEGACY 0x00000000 // Field: [10] TAMRSU // @@ -232,12 +232,12 @@ // time-out. // CYCLEUPDATE Update TAMATCHR and TAPR, if used, on the next // cycle. -#define GPT_TAMR_TAMRSU 0x00000400 -#define GPT_TAMR_TAMRSU_BITN 10 -#define GPT_TAMR_TAMRSU_M 0x00000400 -#define GPT_TAMR_TAMRSU_S 10 -#define GPT_TAMR_TAMRSU_TOUPDATE 0x00000400 -#define GPT_TAMR_TAMRSU_CYCLEUPDATE 0x00000000 +#define GPT_TAMR_TAMRSU 0x00000400 +#define GPT_TAMR_TAMRSU_BITN 10 +#define GPT_TAMR_TAMRSU_M 0x00000400 +#define GPT_TAMR_TAMRSU_S 10 +#define GPT_TAMR_TAMRSU_TOUPDATE 0x00000400 +#define GPT_TAMR_TAMRSU_CYCLEUPDATE 0x00000000 // Field: [9] TAPWMIE // @@ -256,12 +256,12 @@ // EN Interrupt is enabled. This bit is only valid in // PWM mode. // DIS Interrupt is disabled. -#define GPT_TAMR_TAPWMIE 0x00000200 -#define GPT_TAMR_TAPWMIE_BITN 9 -#define GPT_TAMR_TAPWMIE_M 0x00000200 -#define GPT_TAMR_TAPWMIE_S 9 -#define GPT_TAMR_TAPWMIE_EN 0x00000200 -#define GPT_TAMR_TAPWMIE_DIS 0x00000000 +#define GPT_TAMR_TAPWMIE 0x00000200 +#define GPT_TAMR_TAPWMIE_BITN 9 +#define GPT_TAMR_TAPWMIE_M 0x00000200 +#define GPT_TAMR_TAPWMIE_S 9 +#define GPT_TAMR_TAPWMIE_EN 0x00000200 +#define GPT_TAMR_TAPWMIE_DIS 0x00000000 // Field: [8] TAILD // @@ -277,12 +277,12 @@ // pre-scaler is used, update the TAPS register // with the value in the TAPR register on the next // clock cycle. -#define GPT_TAMR_TAILD 0x00000100 -#define GPT_TAMR_TAILD_BITN 8 -#define GPT_TAMR_TAILD_M 0x00000100 -#define GPT_TAMR_TAILD_S 8 -#define GPT_TAMR_TAILD_TOUPDATE 0x00000100 -#define GPT_TAMR_TAILD_CYCLEUPDATE 0x00000000 +#define GPT_TAMR_TAILD 0x00000100 +#define GPT_TAMR_TAILD_BITN 8 +#define GPT_TAMR_TAILD_M 0x00000100 +#define GPT_TAMR_TAILD_S 8 +#define GPT_TAMR_TAILD_TOUPDATE 0x00000100 +#define GPT_TAMR_TAILD_CYCLEUPDATE 0x00000000 // Field: [7] TASNAPS // @@ -293,12 +293,12 @@ // at the time-out event into the GPT Timer A // (TAR) register. // DIS Snap-shot mode is disabled. -#define GPT_TAMR_TASNAPS 0x00000080 -#define GPT_TAMR_TASNAPS_BITN 7 -#define GPT_TAMR_TASNAPS_M 0x00000080 -#define GPT_TAMR_TASNAPS_S 7 -#define GPT_TAMR_TASNAPS_EN 0x00000080 -#define GPT_TAMR_TASNAPS_DIS 0x00000000 +#define GPT_TAMR_TASNAPS 0x00000080 +#define GPT_TAMR_TASNAPS_BITN 7 +#define GPT_TAMR_TASNAPS_M 0x00000080 +#define GPT_TAMR_TASNAPS_S 7 +#define GPT_TAMR_TASNAPS_EN 0x00000080 +#define GPT_TAMR_TASNAPS_DIS 0x00000000 // Field: [6] TAWOT // @@ -311,12 +311,12 @@ // Module 0, Timer A. This function is valid for // one-shot, periodic, and PWM modes // NOWAIT Timer A begins counting as soon as it is enabled. -#define GPT_TAMR_TAWOT 0x00000040 -#define GPT_TAMR_TAWOT_BITN 6 -#define GPT_TAMR_TAWOT_M 0x00000040 -#define GPT_TAMR_TAWOT_S 6 -#define GPT_TAMR_TAWOT_WAIT 0x00000040 -#define GPT_TAMR_TAWOT_NOWAIT 0x00000000 +#define GPT_TAMR_TAWOT 0x00000040 +#define GPT_TAMR_TAWOT_BITN 6 +#define GPT_TAMR_TAWOT_M 0x00000040 +#define GPT_TAMR_TAWOT_S 6 +#define GPT_TAMR_TAWOT_WAIT 0x00000040 +#define GPT_TAMR_TAWOT_NOWAIT 0x00000000 // Field: [5] TAMIE // @@ -328,12 +328,12 @@ // DIS The match interrupt is disabled for match events. // Additionally, output triggers on match events // are prevented. -#define GPT_TAMR_TAMIE 0x00000020 -#define GPT_TAMR_TAMIE_BITN 5 -#define GPT_TAMR_TAMIE_M 0x00000020 -#define GPT_TAMR_TAMIE_S 5 -#define GPT_TAMR_TAMIE_EN 0x00000020 -#define GPT_TAMR_TAMIE_DIS 0x00000000 +#define GPT_TAMR_TAMIE 0x00000020 +#define GPT_TAMR_TAMIE_BITN 5 +#define GPT_TAMR_TAMIE_M 0x00000020 +#define GPT_TAMR_TAMIE_S 5 +#define GPT_TAMR_TAMIE_EN 0x00000020 +#define GPT_TAMR_TAMIE_DIS 0x00000000 // Field: [4] TACDIR // @@ -342,12 +342,12 @@ // UP The timer counts up. When counting up, the timer // starts from a value of 0x0. // DOWN The timer counts down. -#define GPT_TAMR_TACDIR 0x00000010 -#define GPT_TAMR_TACDIR_BITN 4 -#define GPT_TAMR_TACDIR_M 0x00000010 -#define GPT_TAMR_TACDIR_S 4 -#define GPT_TAMR_TACDIR_UP 0x00000010 -#define GPT_TAMR_TACDIR_DOWN 0x00000000 +#define GPT_TAMR_TACDIR 0x00000010 +#define GPT_TAMR_TACDIR_BITN 4 +#define GPT_TAMR_TACDIR_M 0x00000010 +#define GPT_TAMR_TACDIR_S 4 +#define GPT_TAMR_TACDIR_UP 0x00000010 +#define GPT_TAMR_TACDIR_DOWN 0x00000000 // Field: [3] TAAMS // @@ -358,12 +358,12 @@ // ENUMs: // PWM PWM mode is enabled // CAP_COMP Capture/Compare mode is enabled. -#define GPT_TAMR_TAAMS 0x00000008 -#define GPT_TAMR_TAAMS_BITN 3 -#define GPT_TAMR_TAAMS_M 0x00000008 -#define GPT_TAMR_TAAMS_S 3 -#define GPT_TAMR_TAAMS_PWM 0x00000008 -#define GPT_TAMR_TAAMS_CAP_COMP 0x00000000 +#define GPT_TAMR_TAAMS 0x00000008 +#define GPT_TAMR_TAAMS_BITN 3 +#define GPT_TAMR_TAAMS_M 0x00000008 +#define GPT_TAMR_TAAMS_S 3 +#define GPT_TAMR_TAAMS_PWM 0x00000008 +#define GPT_TAMR_TAAMS_CAP_COMP 0x00000000 // Field: [2] TACM // @@ -371,12 +371,12 @@ // ENUMs: // EDGTIME Edge-Time mode // EDGCNT Edge-Count mode -#define GPT_TAMR_TACM 0x00000004 -#define GPT_TAMR_TACM_BITN 2 -#define GPT_TAMR_TACM_M 0x00000004 -#define GPT_TAMR_TACM_S 2 -#define GPT_TAMR_TACM_EDGTIME 0x00000004 -#define GPT_TAMR_TACM_EDGCNT 0x00000000 +#define GPT_TAMR_TACM 0x00000004 +#define GPT_TAMR_TACM_BITN 2 +#define GPT_TAMR_TACM_M 0x00000004 +#define GPT_TAMR_TACM_S 2 +#define GPT_TAMR_TACM_EDGTIME 0x00000004 +#define GPT_TAMR_TACM_EDGCNT 0x00000000 // Field: [1:0] TAMR // @@ -392,12 +392,12 @@ // CAPTURE Capture mode // PERIODIC Periodic Timer mode // ONE_SHOT One-Shot Timer mode -#define GPT_TAMR_TAMR_W 2 -#define GPT_TAMR_TAMR_M 0x00000003 -#define GPT_TAMR_TAMR_S 0 -#define GPT_TAMR_TAMR_CAPTURE 0x00000003 -#define GPT_TAMR_TAMR_PERIODIC 0x00000002 -#define GPT_TAMR_TAMR_ONE_SHOT 0x00000001 +#define GPT_TAMR_TAMR_W 2 +#define GPT_TAMR_TAMR_M 0x00000003 +#define GPT_TAMR_TAMR_S 0 +#define GPT_TAMR_TAMR_CAPTURE 0x00000003 +#define GPT_TAMR_TAMR_PERIODIC 0x00000002 +#define GPT_TAMR_TAMR_ONE_SHOT 0x00000001 //***************************************************************************** // @@ -420,17 +420,17 @@ // CLR_ON_TO Clear CCP output pin on Time-Out // TOG_ON_TO Toggle State on Time-Out // DIS_CMP Disable compare operations -#define GPT_TBMR_TCACT_W 3 -#define GPT_TBMR_TCACT_M 0x0000E000 -#define GPT_TBMR_TCACT_S 13 -#define GPT_TBMR_TCACT_CLRSET_ON_TO 0x0000E000 -#define GPT_TBMR_TCACT_SETCLR_ON_TO 0x0000C000 -#define GPT_TBMR_TCACT_CLRTOG_ON_TO 0x0000A000 -#define GPT_TBMR_TCACT_SETTOG_ON_TO 0x00008000 -#define GPT_TBMR_TCACT_SET_ON_TO 0x00006000 -#define GPT_TBMR_TCACT_CLR_ON_TO 0x00004000 -#define GPT_TBMR_TCACT_TOG_ON_TO 0x00002000 -#define GPT_TBMR_TCACT_DIS_CMP 0x00000000 +#define GPT_TBMR_TCACT_W 3 +#define GPT_TBMR_TCACT_M 0x0000E000 +#define GPT_TBMR_TCACT_S 13 +#define GPT_TBMR_TCACT_CLRSET_ON_TO 0x0000E000 +#define GPT_TBMR_TCACT_SETCLR_ON_TO 0x0000C000 +#define GPT_TBMR_TCACT_CLRTOG_ON_TO 0x0000A000 +#define GPT_TBMR_TCACT_SETTOG_ON_TO 0x00008000 +#define GPT_TBMR_TCACT_SET_ON_TO 0x00006000 +#define GPT_TBMR_TCACT_CLR_ON_TO 0x00004000 +#define GPT_TBMR_TCACT_TOG_ON_TO 0x00002000 +#define GPT_TBMR_TCACT_DIS_CMP 0x00000000 // Field: [12] TBCINTD // @@ -438,12 +438,12 @@ // ENUMs: // DIS_TO_INTR Mask Time-Out Interrupt // EN_TO_INTR Normal Time-Out Interrupt -#define GPT_TBMR_TBCINTD 0x00001000 -#define GPT_TBMR_TBCINTD_BITN 12 -#define GPT_TBMR_TBCINTD_M 0x00001000 -#define GPT_TBMR_TBCINTD_S 12 -#define GPT_TBMR_TBCINTD_DIS_TO_INTR 0x00001000 -#define GPT_TBMR_TBCINTD_EN_TO_INTR 0x00000000 +#define GPT_TBMR_TBCINTD 0x00001000 +#define GPT_TBMR_TBCINTD_BITN 12 +#define GPT_TBMR_TBCINTD_M 0x00001000 +#define GPT_TBMR_TBCINTD_S 12 +#define GPT_TBMR_TBCINTD_DIS_TO_INTR 0x00001000 +#define GPT_TBMR_TBCINTD_EN_TO_INTR 0x00000000 // Field: [11] TBPLO // @@ -459,12 +459,12 @@ // ENUMs: // CCP_ON_TO CCP output pin is set to 1 on time-out // LEGACY Legacy operation -#define GPT_TBMR_TBPLO 0x00000800 -#define GPT_TBMR_TBPLO_BITN 11 -#define GPT_TBMR_TBPLO_M 0x00000800 -#define GPT_TBMR_TBPLO_S 11 -#define GPT_TBMR_TBPLO_CCP_ON_TO 0x00000800 -#define GPT_TBMR_TBPLO_LEGACY 0x00000000 +#define GPT_TBMR_TBPLO 0x00000800 +#define GPT_TBMR_TBPLO_BITN 11 +#define GPT_TBMR_TBPLO_M 0x00000800 +#define GPT_TBMR_TBPLO_S 11 +#define GPT_TBMR_TBPLO_CCP_ON_TO 0x00000800 +#define GPT_TBMR_TBPLO_LEGACY 0x00000000 // Field: [10] TBMRSU // @@ -481,12 +481,12 @@ // time-out. // CYCLEUPDATE Update TBMATCHR and TBPR, if used, on the next // cycle. -#define GPT_TBMR_TBMRSU 0x00000400 -#define GPT_TBMR_TBMRSU_BITN 10 -#define GPT_TBMR_TBMRSU_M 0x00000400 -#define GPT_TBMR_TBMRSU_S 10 -#define GPT_TBMR_TBMRSU_TOUPDATE 0x00000400 -#define GPT_TBMR_TBMRSU_CYCLEUPDATE 0x00000000 +#define GPT_TBMR_TBMRSU 0x00000400 +#define GPT_TBMR_TBMRSU_BITN 10 +#define GPT_TBMR_TBMRSU_M 0x00000400 +#define GPT_TBMR_TBMRSU_S 10 +#define GPT_TBMR_TBMRSU_TOUPDATE 0x00000400 +#define GPT_TBMR_TBMRSU_CYCLEUPDATE 0x00000000 // Field: [9] TBPWMIE // @@ -505,12 +505,12 @@ // EN Interrupt is enabled. This bit is only valid in // PWM mode. // DIS Interrupt is disabled. -#define GPT_TBMR_TBPWMIE 0x00000200 -#define GPT_TBMR_TBPWMIE_BITN 9 -#define GPT_TBMR_TBPWMIE_M 0x00000200 -#define GPT_TBMR_TBPWMIE_S 9 -#define GPT_TBMR_TBPWMIE_EN 0x00000200 -#define GPT_TBMR_TBPWMIE_DIS 0x00000000 +#define GPT_TBMR_TBPWMIE 0x00000200 +#define GPT_TBMR_TBPWMIE_BITN 9 +#define GPT_TBMR_TBPWMIE_M 0x00000200 +#define GPT_TBMR_TBPWMIE_S 9 +#define GPT_TBMR_TBPWMIE_EN 0x00000200 +#define GPT_TBMR_TBPWMIE_DIS 0x00000000 // Field: [8] TBILD // @@ -526,12 +526,12 @@ // pre-scaler is used, update the TBPS register // with the value in the TBPR register on the next // clock cycle. -#define GPT_TBMR_TBILD 0x00000100 -#define GPT_TBMR_TBILD_BITN 8 -#define GPT_TBMR_TBILD_M 0x00000100 -#define GPT_TBMR_TBILD_S 8 -#define GPT_TBMR_TBILD_TOUPDATE 0x00000100 -#define GPT_TBMR_TBILD_CYCLEUPDATE 0x00000000 +#define GPT_TBMR_TBILD 0x00000100 +#define GPT_TBMR_TBILD_BITN 8 +#define GPT_TBMR_TBILD_M 0x00000100 +#define GPT_TBMR_TBILD_S 8 +#define GPT_TBMR_TBILD_TOUPDATE 0x00000100 +#define GPT_TBMR_TBILD_CYCLEUPDATE 0x00000000 // Field: [7] TBSNAPS // @@ -539,12 +539,12 @@ // ENUMs: // EN If Timer B is configured in the periodic mode // DIS Snap-shot mode is disabled. -#define GPT_TBMR_TBSNAPS 0x00000080 -#define GPT_TBMR_TBSNAPS_BITN 7 -#define GPT_TBMR_TBSNAPS_M 0x00000080 -#define GPT_TBMR_TBSNAPS_S 7 -#define GPT_TBMR_TBSNAPS_EN 0x00000080 -#define GPT_TBMR_TBSNAPS_DIS 0x00000000 +#define GPT_TBMR_TBSNAPS 0x00000080 +#define GPT_TBMR_TBSNAPS_BITN 7 +#define GPT_TBMR_TBSNAPS_M 0x00000080 +#define GPT_TBMR_TBSNAPS_S 7 +#define GPT_TBMR_TBSNAPS_EN 0x00000080 +#define GPT_TBMR_TBSNAPS_DIS 0x00000000 // Field: [6] TBWOT // @@ -556,12 +556,12 @@ // in the daisy chain. This function is valid for // one-shot, periodic, and PWM modes // NOWAIT Timer B begins counting as soon as it is enabled. -#define GPT_TBMR_TBWOT 0x00000040 -#define GPT_TBMR_TBWOT_BITN 6 -#define GPT_TBMR_TBWOT_M 0x00000040 -#define GPT_TBMR_TBWOT_S 6 -#define GPT_TBMR_TBWOT_WAIT 0x00000040 -#define GPT_TBMR_TBWOT_NOWAIT 0x00000000 +#define GPT_TBMR_TBWOT 0x00000040 +#define GPT_TBMR_TBWOT_BITN 6 +#define GPT_TBMR_TBWOT_M 0x00000040 +#define GPT_TBMR_TBWOT_S 6 +#define GPT_TBMR_TBWOT_WAIT 0x00000040 +#define GPT_TBMR_TBWOT_NOWAIT 0x00000000 // Field: [5] TBMIE // @@ -573,12 +573,12 @@ // DIS The match interrupt is disabled for match events. // Additionally, output triggers on match events // are prevented. -#define GPT_TBMR_TBMIE 0x00000020 -#define GPT_TBMR_TBMIE_BITN 5 -#define GPT_TBMR_TBMIE_M 0x00000020 -#define GPT_TBMR_TBMIE_S 5 -#define GPT_TBMR_TBMIE_EN 0x00000020 -#define GPT_TBMR_TBMIE_DIS 0x00000000 +#define GPT_TBMR_TBMIE 0x00000020 +#define GPT_TBMR_TBMIE_BITN 5 +#define GPT_TBMR_TBMIE_M 0x00000020 +#define GPT_TBMR_TBMIE_S 5 +#define GPT_TBMR_TBMIE_EN 0x00000020 +#define GPT_TBMR_TBMIE_DIS 0x00000000 // Field: [4] TBCDIR // @@ -587,12 +587,12 @@ // UP The timer counts up. When counting up, the timer // starts from a value of 0x0. // DOWN The timer counts down. -#define GPT_TBMR_TBCDIR 0x00000010 -#define GPT_TBMR_TBCDIR_BITN 4 -#define GPT_TBMR_TBCDIR_M 0x00000010 -#define GPT_TBMR_TBCDIR_S 4 -#define GPT_TBMR_TBCDIR_UP 0x00000010 -#define GPT_TBMR_TBCDIR_DOWN 0x00000000 +#define GPT_TBMR_TBCDIR 0x00000010 +#define GPT_TBMR_TBCDIR_BITN 4 +#define GPT_TBMR_TBCDIR_M 0x00000010 +#define GPT_TBMR_TBCDIR_S 4 +#define GPT_TBMR_TBCDIR_UP 0x00000010 +#define GPT_TBMR_TBCDIR_DOWN 0x00000000 // Field: [3] TBAMS // @@ -603,12 +603,12 @@ // ENUMs: // PWM PWM mode is enabled // CAP_COMP Capture/Compare mode is enabled. -#define GPT_TBMR_TBAMS 0x00000008 -#define GPT_TBMR_TBAMS_BITN 3 -#define GPT_TBMR_TBAMS_M 0x00000008 -#define GPT_TBMR_TBAMS_S 3 -#define GPT_TBMR_TBAMS_PWM 0x00000008 -#define GPT_TBMR_TBAMS_CAP_COMP 0x00000000 +#define GPT_TBMR_TBAMS 0x00000008 +#define GPT_TBMR_TBAMS_BITN 3 +#define GPT_TBMR_TBAMS_M 0x00000008 +#define GPT_TBMR_TBAMS_S 3 +#define GPT_TBMR_TBAMS_PWM 0x00000008 +#define GPT_TBMR_TBAMS_CAP_COMP 0x00000000 // Field: [2] TBCM // @@ -616,12 +616,12 @@ // ENUMs: // EDGTIME Edge-Time mode // EDGCNT Edge-Count mode -#define GPT_TBMR_TBCM 0x00000004 -#define GPT_TBMR_TBCM_BITN 2 -#define GPT_TBMR_TBCM_M 0x00000004 -#define GPT_TBMR_TBCM_S 2 -#define GPT_TBMR_TBCM_EDGTIME 0x00000004 -#define GPT_TBMR_TBCM_EDGCNT 0x00000000 +#define GPT_TBMR_TBCM 0x00000004 +#define GPT_TBMR_TBCM_BITN 2 +#define GPT_TBMR_TBCM_M 0x00000004 +#define GPT_TBMR_TBCM_S 2 +#define GPT_TBMR_TBCM_EDGTIME 0x00000004 +#define GPT_TBMR_TBCM_EDGCNT 0x00000000 // Field: [1:0] TBMR // @@ -637,12 +637,12 @@ // CAPTURE Capture mode // PERIODIC Periodic Timer mode // ONE_SHOT One-Shot Timer mode -#define GPT_TBMR_TBMR_W 2 -#define GPT_TBMR_TBMR_M 0x00000003 -#define GPT_TBMR_TBMR_S 0 -#define GPT_TBMR_TBMR_CAPTURE 0x00000003 -#define GPT_TBMR_TBMR_PERIODIC 0x00000002 -#define GPT_TBMR_TBMR_ONE_SHOT 0x00000001 +#define GPT_TBMR_TBMR_W 2 +#define GPT_TBMR_TBMR_M 0x00000003 +#define GPT_TBMR_TBMR_S 0 +#define GPT_TBMR_TBMR_CAPTURE 0x00000003 +#define GPT_TBMR_TBMR_PERIODIC 0x00000002 +#define GPT_TBMR_TBMR_ONE_SHOT 0x00000001 //***************************************************************************** // @@ -658,12 +658,12 @@ // ENUMs: // INVERTED Inverted // NORMAL Not inverted -#define GPT_CTL_TBPWML 0x00004000 -#define GPT_CTL_TBPWML_BITN 14 -#define GPT_CTL_TBPWML_M 0x00004000 -#define GPT_CTL_TBPWML_S 14 -#define GPT_CTL_TBPWML_INVERTED 0x00004000 -#define GPT_CTL_TBPWML_NORMAL 0x00000000 +#define GPT_CTL_TBPWML 0x00004000 +#define GPT_CTL_TBPWML_BITN 14 +#define GPT_CTL_TBPWML_M 0x00004000 +#define GPT_CTL_TBPWML_S 14 +#define GPT_CTL_TBPWML_INVERTED 0x00004000 +#define GPT_CTL_TBPWML_NORMAL 0x00000000 // Field: [11:10] TBEVENT // @@ -684,12 +684,12 @@ // BOTH Both edges // NEG Negative edge // POS Positive edge -#define GPT_CTL_TBEVENT_W 2 -#define GPT_CTL_TBEVENT_M 0x00000C00 -#define GPT_CTL_TBEVENT_S 10 -#define GPT_CTL_TBEVENT_BOTH 0x00000C00 -#define GPT_CTL_TBEVENT_NEG 0x00000400 -#define GPT_CTL_TBEVENT_POS 0x00000000 +#define GPT_CTL_TBEVENT_W 2 +#define GPT_CTL_TBEVENT_M 0x00000C00 +#define GPT_CTL_TBEVENT_S 10 +#define GPT_CTL_TBEVENT_BOTH 0x00000C00 +#define GPT_CTL_TBEVENT_NEG 0x00000400 +#define GPT_CTL_TBEVENT_POS 0x00000000 // Field: [9] TBSTALL // @@ -699,12 +699,12 @@ // halted by the debugger. // DIS Timer B continues counting while the processor is // halted by the debugger. -#define GPT_CTL_TBSTALL 0x00000200 -#define GPT_CTL_TBSTALL_BITN 9 -#define GPT_CTL_TBSTALL_M 0x00000200 -#define GPT_CTL_TBSTALL_S 9 -#define GPT_CTL_TBSTALL_EN 0x00000200 -#define GPT_CTL_TBSTALL_DIS 0x00000000 +#define GPT_CTL_TBSTALL 0x00000200 +#define GPT_CTL_TBSTALL_BITN 9 +#define GPT_CTL_TBSTALL_M 0x00000200 +#define GPT_CTL_TBSTALL_S 9 +#define GPT_CTL_TBSTALL_EN 0x00000200 +#define GPT_CTL_TBSTALL_DIS 0x00000000 // Field: [8] TBEN // @@ -713,12 +713,12 @@ // EN Timer B is enabled and begins counting or the // capture logic is enabled based on CFG register. // DIS Timer B is disabled. -#define GPT_CTL_TBEN 0x00000100 -#define GPT_CTL_TBEN_BITN 8 -#define GPT_CTL_TBEN_M 0x00000100 -#define GPT_CTL_TBEN_S 8 -#define GPT_CTL_TBEN_EN 0x00000100 -#define GPT_CTL_TBEN_DIS 0x00000000 +#define GPT_CTL_TBEN 0x00000100 +#define GPT_CTL_TBEN_BITN 8 +#define GPT_CTL_TBEN_M 0x00000100 +#define GPT_CTL_TBEN_S 8 +#define GPT_CTL_TBEN_EN 0x00000100 +#define GPT_CTL_TBEN_DIS 0x00000000 // Field: [6] TAPWML // @@ -726,12 +726,12 @@ // ENUMs: // INVERTED Inverted // NORMAL Not inverted -#define GPT_CTL_TAPWML 0x00000040 -#define GPT_CTL_TAPWML_BITN 6 -#define GPT_CTL_TAPWML_M 0x00000040 -#define GPT_CTL_TAPWML_S 6 -#define GPT_CTL_TAPWML_INVERTED 0x00000040 -#define GPT_CTL_TAPWML_NORMAL 0x00000000 +#define GPT_CTL_TAPWML 0x00000040 +#define GPT_CTL_TAPWML_BITN 6 +#define GPT_CTL_TAPWML_M 0x00000040 +#define GPT_CTL_TAPWML_S 6 +#define GPT_CTL_TAPWML_INVERTED 0x00000040 +#define GPT_CTL_TAPWML_NORMAL 0x00000000 // Field: [3:2] TAEVENT // @@ -752,12 +752,12 @@ // BOTH Both edges // NEG Negative edge // POS Positive edge -#define GPT_CTL_TAEVENT_W 2 -#define GPT_CTL_TAEVENT_M 0x0000000C -#define GPT_CTL_TAEVENT_S 2 -#define GPT_CTL_TAEVENT_BOTH 0x0000000C -#define GPT_CTL_TAEVENT_NEG 0x00000004 -#define GPT_CTL_TAEVENT_POS 0x00000000 +#define GPT_CTL_TAEVENT_W 2 +#define GPT_CTL_TAEVENT_M 0x0000000C +#define GPT_CTL_TAEVENT_S 2 +#define GPT_CTL_TAEVENT_BOTH 0x0000000C +#define GPT_CTL_TAEVENT_NEG 0x00000004 +#define GPT_CTL_TAEVENT_POS 0x00000000 // Field: [1] TASTALL // @@ -767,12 +767,12 @@ // halted by the debugger. // DIS Timer A continues counting while the processor is // halted by the debugger. -#define GPT_CTL_TASTALL 0x00000002 -#define GPT_CTL_TASTALL_BITN 1 -#define GPT_CTL_TASTALL_M 0x00000002 -#define GPT_CTL_TASTALL_S 1 -#define GPT_CTL_TASTALL_EN 0x00000002 -#define GPT_CTL_TASTALL_DIS 0x00000000 +#define GPT_CTL_TASTALL 0x00000002 +#define GPT_CTL_TASTALL_BITN 1 +#define GPT_CTL_TASTALL_M 0x00000002 +#define GPT_CTL_TASTALL_S 1 +#define GPT_CTL_TASTALL_EN 0x00000002 +#define GPT_CTL_TASTALL_DIS 0x00000000 // Field: [0] TAEN // @@ -782,12 +782,12 @@ // capture logic is enabled based on the CFG // register. // DIS Timer A is disabled. -#define GPT_CTL_TAEN 0x00000001 -#define GPT_CTL_TAEN_BITN 0 -#define GPT_CTL_TAEN_M 0x00000001 -#define GPT_CTL_TAEN_S 0 -#define GPT_CTL_TAEN_EN 0x00000001 -#define GPT_CTL_TAEN_DIS 0x00000000 +#define GPT_CTL_TAEN 0x00000001 +#define GPT_CTL_TAEN_BITN 0 +#define GPT_CTL_TAEN_M 0x00000001 +#define GPT_CTL_TAEN_S 0 +#define GPT_CTL_TAEN_EN 0x00000001 +#define GPT_CTL_TAEN_DIS 0x00000000 //***************************************************************************** // @@ -803,13 +803,13 @@ // TIMERB A timeout event for Timer B of GPT3 is triggered // TIMERA A timeout event for Timer A of GPT3 is triggered // NOSYNC No Sync. GPT3 is not affected. -#define GPT_SYNC_SYNC3_W 2 -#define GPT_SYNC_SYNC3_M 0x000000C0 -#define GPT_SYNC_SYNC3_S 6 -#define GPT_SYNC_SYNC3_BOTH 0x000000C0 -#define GPT_SYNC_SYNC3_TIMERB 0x00000080 -#define GPT_SYNC_SYNC3_TIMERA 0x00000040 -#define GPT_SYNC_SYNC3_NOSYNC 0x00000000 +#define GPT_SYNC_SYNC3_W 2 +#define GPT_SYNC_SYNC3_M 0x000000C0 +#define GPT_SYNC_SYNC3_S 6 +#define GPT_SYNC_SYNC3_BOTH 0x000000C0 +#define GPT_SYNC_SYNC3_TIMERB 0x00000080 +#define GPT_SYNC_SYNC3_TIMERA 0x00000040 +#define GPT_SYNC_SYNC3_NOSYNC 0x00000000 // Field: [5:4] SYNC2 // @@ -820,13 +820,13 @@ // TIMERB A timeout event for Timer B of GPT2 is triggered // TIMERA A timeout event for Timer A of GPT2 is triggered // NOSYNC No Sync. GPT2 is not affected. -#define GPT_SYNC_SYNC2_W 2 -#define GPT_SYNC_SYNC2_M 0x00000030 -#define GPT_SYNC_SYNC2_S 4 -#define GPT_SYNC_SYNC2_BOTH 0x00000030 -#define GPT_SYNC_SYNC2_TIMERB 0x00000020 -#define GPT_SYNC_SYNC2_TIMERA 0x00000010 -#define GPT_SYNC_SYNC2_NOSYNC 0x00000000 +#define GPT_SYNC_SYNC2_W 2 +#define GPT_SYNC_SYNC2_M 0x00000030 +#define GPT_SYNC_SYNC2_S 4 +#define GPT_SYNC_SYNC2_BOTH 0x00000030 +#define GPT_SYNC_SYNC2_TIMERB 0x00000020 +#define GPT_SYNC_SYNC2_TIMERA 0x00000010 +#define GPT_SYNC_SYNC2_NOSYNC 0x00000000 // Field: [3:2] SYNC1 // @@ -837,13 +837,13 @@ // TIMERB A timeout event for Timer B of GPT1 is triggered // TIMERA A timeout event for Timer A of GPT1 is triggered // NOSYNC No Sync. GPT1 is not affected. -#define GPT_SYNC_SYNC1_W 2 -#define GPT_SYNC_SYNC1_M 0x0000000C -#define GPT_SYNC_SYNC1_S 2 -#define GPT_SYNC_SYNC1_BOTH 0x0000000C -#define GPT_SYNC_SYNC1_TIMERB 0x00000008 -#define GPT_SYNC_SYNC1_TIMERA 0x00000004 -#define GPT_SYNC_SYNC1_NOSYNC 0x00000000 +#define GPT_SYNC_SYNC1_W 2 +#define GPT_SYNC_SYNC1_M 0x0000000C +#define GPT_SYNC_SYNC1_S 2 +#define GPT_SYNC_SYNC1_BOTH 0x0000000C +#define GPT_SYNC_SYNC1_TIMERB 0x00000008 +#define GPT_SYNC_SYNC1_TIMERA 0x00000004 +#define GPT_SYNC_SYNC1_NOSYNC 0x00000000 // Field: [1:0] SYNC0 // @@ -854,13 +854,13 @@ // TIMERB A timeout event for Timer B of GPT0 is triggered // TIMERA A timeout event for Timer A of GPT0 is triggered // NOSYNC No Sync. GPT0 is not affected. -#define GPT_SYNC_SYNC0_W 2 -#define GPT_SYNC_SYNC0_M 0x00000003 -#define GPT_SYNC_SYNC0_S 0 -#define GPT_SYNC_SYNC0_BOTH 0x00000003 -#define GPT_SYNC_SYNC0_TIMERB 0x00000002 -#define GPT_SYNC_SYNC0_TIMERA 0x00000001 -#define GPT_SYNC_SYNC0_NOSYNC 0x00000000 +#define GPT_SYNC_SYNC0_W 2 +#define GPT_SYNC_SYNC0_M 0x00000003 +#define GPT_SYNC_SYNC0_S 0 +#define GPT_SYNC_SYNC0_BOTH 0x00000003 +#define GPT_SYNC_SYNC0_TIMERB 0x00000002 +#define GPT_SYNC_SYNC0_TIMERA 0x00000001 +#define GPT_SYNC_SYNC0_NOSYNC 0x00000000 //***************************************************************************** // @@ -874,12 +874,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_DMABIM 0x00002000 -#define GPT_IMR_DMABIM_BITN 13 -#define GPT_IMR_DMABIM_M 0x00002000 -#define GPT_IMR_DMABIM_S 13 -#define GPT_IMR_DMABIM_EN 0x00002000 -#define GPT_IMR_DMABIM_DIS 0x00000000 +#define GPT_IMR_DMABIM 0x00002000 +#define GPT_IMR_DMABIM_BITN 13 +#define GPT_IMR_DMABIM_M 0x00002000 +#define GPT_IMR_DMABIM_S 13 +#define GPT_IMR_DMABIM_EN 0x00002000 +#define GPT_IMR_DMABIM_DIS 0x00000000 // Field: [11] TBMIM // @@ -887,12 +887,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_TBMIM 0x00000800 -#define GPT_IMR_TBMIM_BITN 11 -#define GPT_IMR_TBMIM_M 0x00000800 -#define GPT_IMR_TBMIM_S 11 -#define GPT_IMR_TBMIM_EN 0x00000800 -#define GPT_IMR_TBMIM_DIS 0x00000000 +#define GPT_IMR_TBMIM 0x00000800 +#define GPT_IMR_TBMIM_BITN 11 +#define GPT_IMR_TBMIM_M 0x00000800 +#define GPT_IMR_TBMIM_S 11 +#define GPT_IMR_TBMIM_EN 0x00000800 +#define GPT_IMR_TBMIM_DIS 0x00000000 // Field: [10] CBEIM // @@ -900,12 +900,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_CBEIM 0x00000400 -#define GPT_IMR_CBEIM_BITN 10 -#define GPT_IMR_CBEIM_M 0x00000400 -#define GPT_IMR_CBEIM_S 10 -#define GPT_IMR_CBEIM_EN 0x00000400 -#define GPT_IMR_CBEIM_DIS 0x00000000 +#define GPT_IMR_CBEIM 0x00000400 +#define GPT_IMR_CBEIM_BITN 10 +#define GPT_IMR_CBEIM_M 0x00000400 +#define GPT_IMR_CBEIM_S 10 +#define GPT_IMR_CBEIM_EN 0x00000400 +#define GPT_IMR_CBEIM_DIS 0x00000000 // Field: [9] CBMIM // @@ -913,12 +913,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_CBMIM 0x00000200 -#define GPT_IMR_CBMIM_BITN 9 -#define GPT_IMR_CBMIM_M 0x00000200 -#define GPT_IMR_CBMIM_S 9 -#define GPT_IMR_CBMIM_EN 0x00000200 -#define GPT_IMR_CBMIM_DIS 0x00000000 +#define GPT_IMR_CBMIM 0x00000200 +#define GPT_IMR_CBMIM_BITN 9 +#define GPT_IMR_CBMIM_M 0x00000200 +#define GPT_IMR_CBMIM_S 9 +#define GPT_IMR_CBMIM_EN 0x00000200 +#define GPT_IMR_CBMIM_DIS 0x00000000 // Field: [8] TBTOIM // @@ -927,12 +927,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_TBTOIM 0x00000100 -#define GPT_IMR_TBTOIM_BITN 8 -#define GPT_IMR_TBTOIM_M 0x00000100 -#define GPT_IMR_TBTOIM_S 8 -#define GPT_IMR_TBTOIM_EN 0x00000100 -#define GPT_IMR_TBTOIM_DIS 0x00000000 +#define GPT_IMR_TBTOIM 0x00000100 +#define GPT_IMR_TBTOIM_BITN 8 +#define GPT_IMR_TBTOIM_M 0x00000100 +#define GPT_IMR_TBTOIM_S 8 +#define GPT_IMR_TBTOIM_EN 0x00000100 +#define GPT_IMR_TBTOIM_DIS 0x00000000 // Field: [5] DMAAIM // @@ -941,12 +941,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_DMAAIM 0x00000020 -#define GPT_IMR_DMAAIM_BITN 5 -#define GPT_IMR_DMAAIM_M 0x00000020 -#define GPT_IMR_DMAAIM_S 5 -#define GPT_IMR_DMAAIM_EN 0x00000020 -#define GPT_IMR_DMAAIM_DIS 0x00000000 +#define GPT_IMR_DMAAIM 0x00000020 +#define GPT_IMR_DMAAIM_BITN 5 +#define GPT_IMR_DMAAIM_M 0x00000020 +#define GPT_IMR_DMAAIM_S 5 +#define GPT_IMR_DMAAIM_EN 0x00000020 +#define GPT_IMR_DMAAIM_DIS 0x00000000 // Field: [4] TAMIM // @@ -954,12 +954,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_TAMIM 0x00000010 -#define GPT_IMR_TAMIM_BITN 4 -#define GPT_IMR_TAMIM_M 0x00000010 -#define GPT_IMR_TAMIM_S 4 -#define GPT_IMR_TAMIM_EN 0x00000010 -#define GPT_IMR_TAMIM_DIS 0x00000000 +#define GPT_IMR_TAMIM 0x00000010 +#define GPT_IMR_TAMIM_BITN 4 +#define GPT_IMR_TAMIM_M 0x00000010 +#define GPT_IMR_TAMIM_S 4 +#define GPT_IMR_TAMIM_EN 0x00000010 +#define GPT_IMR_TAMIM_DIS 0x00000000 // Field: [2] CAEIM // @@ -967,12 +967,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_CAEIM 0x00000004 -#define GPT_IMR_CAEIM_BITN 2 -#define GPT_IMR_CAEIM_M 0x00000004 -#define GPT_IMR_CAEIM_S 2 -#define GPT_IMR_CAEIM_EN 0x00000004 -#define GPT_IMR_CAEIM_DIS 0x00000000 +#define GPT_IMR_CAEIM 0x00000004 +#define GPT_IMR_CAEIM_BITN 2 +#define GPT_IMR_CAEIM_M 0x00000004 +#define GPT_IMR_CAEIM_S 2 +#define GPT_IMR_CAEIM_EN 0x00000004 +#define GPT_IMR_CAEIM_DIS 0x00000000 // Field: [1] CAMIM // @@ -980,12 +980,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_CAMIM 0x00000002 -#define GPT_IMR_CAMIM_BITN 1 -#define GPT_IMR_CAMIM_M 0x00000002 -#define GPT_IMR_CAMIM_S 1 -#define GPT_IMR_CAMIM_EN 0x00000002 -#define GPT_IMR_CAMIM_DIS 0x00000000 +#define GPT_IMR_CAMIM 0x00000002 +#define GPT_IMR_CAMIM_BITN 1 +#define GPT_IMR_CAMIM_M 0x00000002 +#define GPT_IMR_CAMIM_S 1 +#define GPT_IMR_CAMIM_EN 0x00000002 +#define GPT_IMR_CAMIM_DIS 0x00000000 // Field: [0] TATOIM // @@ -994,12 +994,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_TATOIM 0x00000001 -#define GPT_IMR_TATOIM_BITN 0 -#define GPT_IMR_TATOIM_M 0x00000001 -#define GPT_IMR_TATOIM_S 0 -#define GPT_IMR_TATOIM_EN 0x00000001 -#define GPT_IMR_TATOIM_DIS 0x00000000 +#define GPT_IMR_TATOIM 0x00000001 +#define GPT_IMR_TATOIM_BITN 0 +#define GPT_IMR_TATOIM_M 0x00000001 +#define GPT_IMR_TATOIM_S 0 +#define GPT_IMR_TATOIM_EN 0x00000001 +#define GPT_IMR_TATOIM_DIS 0x00000000 //***************************************************************************** // @@ -1012,10 +1012,10 @@ // // 0: Transfer has not completed // 1: Transfer has completed -#define GPT_RIS_DMABRIS 0x00002000 -#define GPT_RIS_DMABRIS_BITN 13 -#define GPT_RIS_DMABRIS_M 0x00002000 -#define GPT_RIS_DMABRIS_S 13 +#define GPT_RIS_DMABRIS 0x00002000 +#define GPT_RIS_DMABRIS_BITN 13 +#define GPT_RIS_DMABRIS_M 0x00002000 +#define GPT_RIS_DMABRIS_S 13 // Field: [11] TBMRIS // @@ -1026,10 +1026,10 @@ // // TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR // have been reached when configured in one-shot or periodic mode. -#define GPT_RIS_TBMRIS 0x00000800 -#define GPT_RIS_TBMRIS_BITN 11 -#define GPT_RIS_TBMRIS_M 0x00000800 -#define GPT_RIS_TBMRIS_S 11 +#define GPT_RIS_TBMRIS 0x00000800 +#define GPT_RIS_TBMRIS_BITN 11 +#define GPT_RIS_TBMRIS_M 0x00000800 +#define GPT_RIS_TBMRIS_S 11 // Field: [10] CBERIS // @@ -1040,10 +1040,10 @@ // // This interrupt asserts when the subtimer is configured in Input Edge-Time // mode -#define GPT_RIS_CBERIS 0x00000400 -#define GPT_RIS_CBERIS_BITN 10 -#define GPT_RIS_CBERIS_M 0x00000400 -#define GPT_RIS_CBERIS_S 10 +#define GPT_RIS_CBERIS 0x00000400 +#define GPT_RIS_CBERIS_BITN 10 +#define GPT_RIS_CBERIS_M 0x00000400 +#define GPT_RIS_CBERIS_S 10 // Field: [9] CBMRIS // @@ -1056,10 +1056,10 @@ // when configured in Input Edge-Time mode. // // This bit is cleared by writing a 1 to the ICLR.CBMCINT bit. -#define GPT_RIS_CBMRIS 0x00000200 -#define GPT_RIS_CBMRIS_BITN 9 -#define GPT_RIS_CBMRIS_M 0x00000200 -#define GPT_RIS_CBMRIS_S 9 +#define GPT_RIS_CBMRIS 0x00000200 +#define GPT_RIS_CBMRIS_BITN 9 +#define GPT_RIS_CBMRIS_M 0x00000200 +#define GPT_RIS_CBMRIS_S 9 // Field: [8] TBTORIS // @@ -1071,10 +1071,10 @@ // This interrupt is asserted when a one-shot or periodic mode timer reaches // its count limit. The count limit is 0 or the value loaded into TBILR, // depending on the count direction. -#define GPT_RIS_TBTORIS 0x00000100 -#define GPT_RIS_TBTORIS_BITN 8 -#define GPT_RIS_TBTORIS_M 0x00000100 -#define GPT_RIS_TBTORIS_S 8 +#define GPT_RIS_TBTORIS 0x00000100 +#define GPT_RIS_TBTORIS_BITN 8 +#define GPT_RIS_TBTORIS_M 0x00000100 +#define GPT_RIS_TBTORIS_S 8 // Field: [5] DMAARIS // @@ -1082,10 +1082,10 @@ // // 0: Transfer has not completed // 1: Transfer has completed -#define GPT_RIS_DMAARIS 0x00000020 -#define GPT_RIS_DMAARIS_BITN 5 -#define GPT_RIS_DMAARIS_M 0x00000020 -#define GPT_RIS_DMAARIS_S 5 +#define GPT_RIS_DMAARIS 0x00000020 +#define GPT_RIS_DMAARIS_BITN 5 +#define GPT_RIS_DMAARIS_M 0x00000020 +#define GPT_RIS_DMAARIS_S 5 // Field: [4] TAMRIS // @@ -1096,10 +1096,10 @@ // // TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR // have been reached when configured in one-shot or periodic mode. -#define GPT_RIS_TAMRIS 0x00000010 -#define GPT_RIS_TAMRIS_BITN 4 -#define GPT_RIS_TAMRIS_M 0x00000010 -#define GPT_RIS_TAMRIS_S 4 +#define GPT_RIS_TAMRIS 0x00000010 +#define GPT_RIS_TAMRIS_BITN 4 +#define GPT_RIS_TAMRIS_M 0x00000010 +#define GPT_RIS_TAMRIS_S 4 // Field: [2] CAERIS // @@ -1110,10 +1110,10 @@ // // This interrupt asserts when the subtimer is configured in Input Edge-Time // mode -#define GPT_RIS_CAERIS 0x00000004 -#define GPT_RIS_CAERIS_BITN 2 -#define GPT_RIS_CAERIS_M 0x00000004 -#define GPT_RIS_CAERIS_S 2 +#define GPT_RIS_CAERIS 0x00000004 +#define GPT_RIS_CAERIS_BITN 2 +#define GPT_RIS_CAERIS_M 0x00000004 +#define GPT_RIS_CAERIS_S 2 // Field: [1] CAMRIS // @@ -1126,10 +1126,10 @@ // when configured in Input Edge-Time mode. // // This bit is cleared by writing a 1 to the ICLR.CAMCINT bit. -#define GPT_RIS_CAMRIS 0x00000002 -#define GPT_RIS_CAMRIS_BITN 1 -#define GPT_RIS_CAMRIS_M 0x00000002 -#define GPT_RIS_CAMRIS_S 1 +#define GPT_RIS_CAMRIS 0x00000002 +#define GPT_RIS_CAMRIS_BITN 1 +#define GPT_RIS_CAMRIS_M 0x00000002 +#define GPT_RIS_CAMRIS_S 1 // Field: [0] TATORIS // @@ -1141,10 +1141,10 @@ // This interrupt is asserted when a one-shot or periodic mode timer reaches // its count limit. The count limit is 0 or the value loaded into TAILR, // depending on the count direction. -#define GPT_RIS_TATORIS 0x00000001 -#define GPT_RIS_TATORIS_BITN 0 -#define GPT_RIS_TATORIS_M 0x00000001 -#define GPT_RIS_TATORIS_S 0 +#define GPT_RIS_TATORIS 0x00000001 +#define GPT_RIS_TATORIS_BITN 0 +#define GPT_RIS_TATORIS_M 0x00000001 +#define GPT_RIS_TATORIS_S 0 //***************************************************************************** // @@ -1155,91 +1155,91 @@ // // 0: No interrupt or interrupt not enabled // 1: RIS.DMABRIS = 1 && IMR.DMABIM = 1 -#define GPT_MIS_DMABMIS 0x00002000 -#define GPT_MIS_DMABMIS_BITN 13 -#define GPT_MIS_DMABMIS_M 0x00002000 -#define GPT_MIS_DMABMIS_S 13 +#define GPT_MIS_DMABMIS 0x00002000 +#define GPT_MIS_DMABMIS_BITN 13 +#define GPT_MIS_DMABMIS_M 0x00002000 +#define GPT_MIS_DMABMIS_S 13 // Field: [11] TBMMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.TBMRIS = 1 && IMR.TBMIM = 1 -#define GPT_MIS_TBMMIS 0x00000800 -#define GPT_MIS_TBMMIS_BITN 11 -#define GPT_MIS_TBMMIS_M 0x00000800 -#define GPT_MIS_TBMMIS_S 11 +#define GPT_MIS_TBMMIS 0x00000800 +#define GPT_MIS_TBMMIS_BITN 11 +#define GPT_MIS_TBMMIS_M 0x00000800 +#define GPT_MIS_TBMMIS_S 11 // Field: [10] CBEMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.CBERIS = 1 && IMR.CBEIM = 1 -#define GPT_MIS_CBEMIS 0x00000400 -#define GPT_MIS_CBEMIS_BITN 10 -#define GPT_MIS_CBEMIS_M 0x00000400 -#define GPT_MIS_CBEMIS_S 10 +#define GPT_MIS_CBEMIS 0x00000400 +#define GPT_MIS_CBEMIS_BITN 10 +#define GPT_MIS_CBEMIS_M 0x00000400 +#define GPT_MIS_CBEMIS_S 10 // Field: [9] CBMMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.CBMRIS = 1 && IMR.CBMIM = 1 -#define GPT_MIS_CBMMIS 0x00000200 -#define GPT_MIS_CBMMIS_BITN 9 -#define GPT_MIS_CBMMIS_M 0x00000200 -#define GPT_MIS_CBMMIS_S 9 +#define GPT_MIS_CBMMIS 0x00000200 +#define GPT_MIS_CBMMIS_BITN 9 +#define GPT_MIS_CBMMIS_M 0x00000200 +#define GPT_MIS_CBMMIS_S 9 // Field: [8] TBTOMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1 -#define GPT_MIS_TBTOMIS 0x00000100 -#define GPT_MIS_TBTOMIS_BITN 8 -#define GPT_MIS_TBTOMIS_M 0x00000100 -#define GPT_MIS_TBTOMIS_S 8 +#define GPT_MIS_TBTOMIS 0x00000100 +#define GPT_MIS_TBTOMIS_BITN 8 +#define GPT_MIS_TBTOMIS_M 0x00000100 +#define GPT_MIS_TBTOMIS_S 8 // Field: [5] DMAAMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1 -#define GPT_MIS_DMAAMIS 0x00000020 -#define GPT_MIS_DMAAMIS_BITN 5 -#define GPT_MIS_DMAAMIS_M 0x00000020 -#define GPT_MIS_DMAAMIS_S 5 +#define GPT_MIS_DMAAMIS 0x00000020 +#define GPT_MIS_DMAAMIS_BITN 5 +#define GPT_MIS_DMAAMIS_M 0x00000020 +#define GPT_MIS_DMAAMIS_S 5 // Field: [4] TAMMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.TAMRIS = 1 && IMR.TAMIM = 1 -#define GPT_MIS_TAMMIS 0x00000010 -#define GPT_MIS_TAMMIS_BITN 4 -#define GPT_MIS_TAMMIS_M 0x00000010 -#define GPT_MIS_TAMMIS_S 4 +#define GPT_MIS_TAMMIS 0x00000010 +#define GPT_MIS_TAMMIS_BITN 4 +#define GPT_MIS_TAMMIS_M 0x00000010 +#define GPT_MIS_TAMMIS_S 4 // Field: [2] CAEMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.CAERIS = 1 && IMR.CAEIM = 1 -#define GPT_MIS_CAEMIS 0x00000004 -#define GPT_MIS_CAEMIS_BITN 2 -#define GPT_MIS_CAEMIS_M 0x00000004 -#define GPT_MIS_CAEMIS_S 2 +#define GPT_MIS_CAEMIS 0x00000004 +#define GPT_MIS_CAEMIS_BITN 2 +#define GPT_MIS_CAEMIS_M 0x00000004 +#define GPT_MIS_CAEMIS_S 2 // Field: [1] CAMMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.CAMRIS = 1 && IMR.CAMIM = 1 -#define GPT_MIS_CAMMIS 0x00000002 -#define GPT_MIS_CAMMIS_BITN 1 -#define GPT_MIS_CAMMIS_M 0x00000002 -#define GPT_MIS_CAMMIS_S 1 +#define GPT_MIS_CAMMIS 0x00000002 +#define GPT_MIS_CAMMIS_BITN 1 +#define GPT_MIS_CAMMIS_M 0x00000002 +#define GPT_MIS_CAMMIS_S 1 // Field: [0] TATOMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.TATORIS = 1 && IMR.TATOIM = 1 -#define GPT_MIS_TATOMIS 0x00000001 -#define GPT_MIS_TATOMIS_BITN 0 -#define GPT_MIS_TATOMIS_M 0x00000001 -#define GPT_MIS_TATOMIS_S 0 +#define GPT_MIS_TATOMIS 0x00000001 +#define GPT_MIS_TATOMIS_BITN 0 +#define GPT_MIS_TATOMIS_M 0x00000001 +#define GPT_MIS_TATOMIS_S 0 //***************************************************************************** // @@ -1250,91 +1250,91 @@ // // 0: Do nothing. // 1: Clear RIS.DMABRIS and MIS.DMABMIS -#define GPT_ICLR_DMABINT 0x00002000 -#define GPT_ICLR_DMABINT_BITN 13 -#define GPT_ICLR_DMABINT_M 0x00002000 -#define GPT_ICLR_DMABINT_S 13 +#define GPT_ICLR_DMABINT 0x00002000 +#define GPT_ICLR_DMABINT_BITN 13 +#define GPT_ICLR_DMABINT_M 0x00002000 +#define GPT_ICLR_DMABINT_S 13 // Field: [11] TBMCINT // // 0: Do nothing. // 1: Clear RIS.TBMRIS and MIS.TBMMIS -#define GPT_ICLR_TBMCINT 0x00000800 -#define GPT_ICLR_TBMCINT_BITN 11 -#define GPT_ICLR_TBMCINT_M 0x00000800 -#define GPT_ICLR_TBMCINT_S 11 +#define GPT_ICLR_TBMCINT 0x00000800 +#define GPT_ICLR_TBMCINT_BITN 11 +#define GPT_ICLR_TBMCINT_M 0x00000800 +#define GPT_ICLR_TBMCINT_S 11 // Field: [10] CBECINT // // 0: Do nothing. // 1: Clear RIS.CBERIS and MIS.CBEMIS -#define GPT_ICLR_CBECINT 0x00000400 -#define GPT_ICLR_CBECINT_BITN 10 -#define GPT_ICLR_CBECINT_M 0x00000400 -#define GPT_ICLR_CBECINT_S 10 +#define GPT_ICLR_CBECINT 0x00000400 +#define GPT_ICLR_CBECINT_BITN 10 +#define GPT_ICLR_CBECINT_M 0x00000400 +#define GPT_ICLR_CBECINT_S 10 // Field: [9] CBMCINT // // 0: Do nothing. // 1: Clear RIS.CBMRIS and MIS.CBMMIS -#define GPT_ICLR_CBMCINT 0x00000200 -#define GPT_ICLR_CBMCINT_BITN 9 -#define GPT_ICLR_CBMCINT_M 0x00000200 -#define GPT_ICLR_CBMCINT_S 9 +#define GPT_ICLR_CBMCINT 0x00000200 +#define GPT_ICLR_CBMCINT_BITN 9 +#define GPT_ICLR_CBMCINT_M 0x00000200 +#define GPT_ICLR_CBMCINT_S 9 // Field: [8] TBTOCINT // // 0: Do nothing. // 1: Clear RIS.TBTORIS and MIS.TBTOMIS -#define GPT_ICLR_TBTOCINT 0x00000100 -#define GPT_ICLR_TBTOCINT_BITN 8 -#define GPT_ICLR_TBTOCINT_M 0x00000100 -#define GPT_ICLR_TBTOCINT_S 8 +#define GPT_ICLR_TBTOCINT 0x00000100 +#define GPT_ICLR_TBTOCINT_BITN 8 +#define GPT_ICLR_TBTOCINT_M 0x00000100 +#define GPT_ICLR_TBTOCINT_S 8 // Field: [5] DMAAINT // // 0: Do nothing. // 1: Clear RIS.DMAARIS and MIS.DMAAMIS -#define GPT_ICLR_DMAAINT 0x00000020 -#define GPT_ICLR_DMAAINT_BITN 5 -#define GPT_ICLR_DMAAINT_M 0x00000020 -#define GPT_ICLR_DMAAINT_S 5 +#define GPT_ICLR_DMAAINT 0x00000020 +#define GPT_ICLR_DMAAINT_BITN 5 +#define GPT_ICLR_DMAAINT_M 0x00000020 +#define GPT_ICLR_DMAAINT_S 5 // Field: [4] TAMCINT // // 0: Do nothing. // 1: Clear RIS.TAMRIS and MIS.TAMMIS -#define GPT_ICLR_TAMCINT 0x00000010 -#define GPT_ICLR_TAMCINT_BITN 4 -#define GPT_ICLR_TAMCINT_M 0x00000010 -#define GPT_ICLR_TAMCINT_S 4 +#define GPT_ICLR_TAMCINT 0x00000010 +#define GPT_ICLR_TAMCINT_BITN 4 +#define GPT_ICLR_TAMCINT_M 0x00000010 +#define GPT_ICLR_TAMCINT_S 4 // Field: [2] CAECINT // // 0: Do nothing. // 1: Clear RIS.CAERIS and MIS.CAEMIS -#define GPT_ICLR_CAECINT 0x00000004 -#define GPT_ICLR_CAECINT_BITN 2 -#define GPT_ICLR_CAECINT_M 0x00000004 -#define GPT_ICLR_CAECINT_S 2 +#define GPT_ICLR_CAECINT 0x00000004 +#define GPT_ICLR_CAECINT_BITN 2 +#define GPT_ICLR_CAECINT_M 0x00000004 +#define GPT_ICLR_CAECINT_S 2 // Field: [1] CAMCINT // // 0: Do nothing. // 1: Clear RIS.CAMRIS and MIS.CAMMIS -#define GPT_ICLR_CAMCINT 0x00000002 -#define GPT_ICLR_CAMCINT_BITN 1 -#define GPT_ICLR_CAMCINT_M 0x00000002 -#define GPT_ICLR_CAMCINT_S 1 +#define GPT_ICLR_CAMCINT 0x00000002 +#define GPT_ICLR_CAMCINT_BITN 1 +#define GPT_ICLR_CAMCINT_M 0x00000002 +#define GPT_ICLR_CAMCINT_S 1 // Field: [0] TATOCINT // // 0: Do nothing. // 1: Clear RIS.TATORIS and MIS.TATOMIS -#define GPT_ICLR_TATOCINT 0x00000001 -#define GPT_ICLR_TATOCINT_BITN 0 -#define GPT_ICLR_TATOCINT_M 0x00000001 -#define GPT_ICLR_TATOCINT_S 0 +#define GPT_ICLR_TATOCINT 0x00000001 +#define GPT_ICLR_TATOCINT_BITN 0 +#define GPT_ICLR_TATOCINT_M 0x00000001 +#define GPT_ICLR_TATOCINT_S 0 //***************************************************************************** // @@ -1347,9 +1347,9 @@ // // Writing this field loads the counter for Timer A. A read returns the current // value of TAILR. -#define GPT_TAILR_TAILR_W 32 -#define GPT_TAILR_TAILR_M 0xFFFFFFFF -#define GPT_TAILR_TAILR_S 0 +#define GPT_TAILR_TAILR_W 32 +#define GPT_TAILR_TAILR_M 0xFFFFFFFF +#define GPT_TAILR_TAILR_S 0 //***************************************************************************** // @@ -1362,9 +1362,9 @@ // // Writing this field loads the counter for Timer B. A read returns the current // value of TBILR. -#define GPT_TBILR_TBILR_W 32 -#define GPT_TBILR_TBILR_M 0xFFFFFFFF -#define GPT_TBILR_TBILR_S 0 +#define GPT_TBILR_TBILR_W 32 +#define GPT_TBILR_TBILR_M 0xFFFFFFFF +#define GPT_TBILR_TBILR_S 0 //***************************************************************************** // @@ -1374,9 +1374,9 @@ // Field: [31:0] TAMATCHR // // GPT Timer A Match Register -#define GPT_TAMATCHR_TAMATCHR_W 32 -#define GPT_TAMATCHR_TAMATCHR_M 0xFFFFFFFF -#define GPT_TAMATCHR_TAMATCHR_S 0 +#define GPT_TAMATCHR_TAMATCHR_W 32 +#define GPT_TAMATCHR_TAMATCHR_M 0xFFFFFFFF +#define GPT_TAMATCHR_TAMATCHR_S 0 //***************************************************************************** // @@ -1386,9 +1386,9 @@ // Field: [15:0] TBMATCHR // // GPT Timer B Match Register -#define GPT_TBMATCHR_TBMATCHR_W 16 -#define GPT_TBMATCHR_TBMATCHR_M 0x0000FFFF -#define GPT_TBMATCHR_TBMATCHR_S 0 +#define GPT_TBMATCHR_TBMATCHR_W 16 +#define GPT_TBMATCHR_TBMATCHR_M 0x0000FFFF +#define GPT_TBMATCHR_TBMATCHR_S 0 //***************************************************************************** // @@ -1406,9 +1406,9 @@ // 2: Prescaler ratio = 3 // ... // 255: Prescaler ratio = 256 -#define GPT_TAPR_TAPSR_W 8 -#define GPT_TAPR_TAPSR_M 0x000000FF -#define GPT_TAPR_TAPSR_S 0 +#define GPT_TAPR_TAPSR_W 8 +#define GPT_TAPR_TAPSR_M 0x000000FF +#define GPT_TAPR_TAPSR_S 0 //***************************************************************************** // @@ -1426,9 +1426,9 @@ // 2: Prescaler ratio = 3 // ... // 255: Prescaler ratio = 256 -#define GPT_TBPR_TBPSR_W 8 -#define GPT_TBPR_TBPSR_M 0x000000FF -#define GPT_TBPR_TBPSR_S 0 +#define GPT_TBPR_TBPSR_W 8 +#define GPT_TBPR_TBPSR_M 0x000000FF +#define GPT_TBPR_TBPSR_S 0 //***************************************************************************** // @@ -1438,9 +1438,9 @@ // Field: [7:0] TAPSMR // // GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16. -#define GPT_TAPMR_TAPSMR_W 8 -#define GPT_TAPMR_TAPSMR_M 0x000000FF -#define GPT_TAPMR_TAPSMR_S 0 +#define GPT_TAPMR_TAPSMR_W 8 +#define GPT_TAPMR_TAPSMR_M 0x000000FF +#define GPT_TAPMR_TAPSMR_S 0 //***************************************************************************** // @@ -1451,9 +1451,9 @@ // // GPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits // 23 to 16. -#define GPT_TBPMR_TBPSMR_W 8 -#define GPT_TBPMR_TBPSMR_M 0x000000FF -#define GPT_TBPMR_TBPSMR_S 0 +#define GPT_TBPMR_TBPSMR_W 8 +#define GPT_TBPMR_TBPSMR_M 0x000000FF +#define GPT_TBPMR_TBPSMR_S 0 //***************************************************************************** // @@ -1473,9 +1473,9 @@ // In the Input Edge Count Mode, this register contains the number of edges // that have occurred. In the Input Edge Time mode, this register contains the // time at which the last edge event took place. -#define GPT_TAR_TAR_W 32 -#define GPT_TAR_TAR_M 0xFFFFFFFF -#define GPT_TAR_TAR_S 0 +#define GPT_TAR_TAR_W 32 +#define GPT_TAR_TAR_M 0xFFFFFFFF +#define GPT_TAR_TAR_S 0 //***************************************************************************** // @@ -1495,9 +1495,9 @@ // In the Input Edge Count Mode, this register contains the number of edges // that have occurred. In the Input Edge Time mode, this register contains the // time at which the last edge event took place. -#define GPT_TBR_TBR_W 32 -#define GPT_TBR_TBR_M 0xFFFFFFFF -#define GPT_TBR_TBR_S 0 +#define GPT_TBR_TBR_W 32 +#define GPT_TBR_TBR_M 0xFFFFFFFF +#define GPT_TBR_TBR_S 0 //***************************************************************************** // @@ -1513,9 +1513,9 @@ // Note: In 16-bit mode, only the lower 16-bits of this // register can be written with a new value. Writes to the prescaler bits have // no effect -#define GPT_TAV_TAV_W 32 -#define GPT_TAV_TAV_M 0xFFFFFFFF -#define GPT_TAV_TAV_S 0 +#define GPT_TAV_TAV_W 32 +#define GPT_TAV_TAV_M 0xFFFFFFFF +#define GPT_TAV_TAV_S 0 //***************************************************************************** // @@ -1531,9 +1531,9 @@ // Note: In 16-bit mode, only the lower 16-bits of this // register can be written with a new value. Writes to the prescaler bits have // no effect -#define GPT_TBV_TBV_W 32 -#define GPT_TBV_TBV_M 0xFFFFFFFF -#define GPT_TBV_TBV_S 0 +#define GPT_TBV_TBV_W 32 +#define GPT_TBV_TBV_M 0xFFFFFFFF +#define GPT_TBV_TBV_S 0 //***************************************************************************** // @@ -1543,9 +1543,9 @@ // Field: [7:0] PSS // // GPT Timer A Pre-scaler -#define GPT_TAPS_PSS_W 8 -#define GPT_TAPS_PSS_M 0x000000FF -#define GPT_TAPS_PSS_S 0 +#define GPT_TAPS_PSS_W 8 +#define GPT_TAPS_PSS_M 0x000000FF +#define GPT_TAPS_PSS_S 0 //***************************************************************************** // @@ -1555,9 +1555,9 @@ // Field: [7:0] PSS // // GPT Timer B Pre-scaler -#define GPT_TBPS_PSS_W 8 -#define GPT_TBPS_PSS_M 0x000000FF -#define GPT_TBPS_PSS_S 0 +#define GPT_TBPS_PSS_W 8 +#define GPT_TBPS_PSS_M 0x000000FF +#define GPT_TBPS_PSS_S 0 //***************************************************************************** // @@ -1567,9 +1567,9 @@ // Field: [7:0] PSV // // GPT Timer A Pre-scaler Value -#define GPT_TAPV_PSV_W 8 -#define GPT_TAPV_PSV_M 0x000000FF -#define GPT_TAPV_PSV_S 0 +#define GPT_TAPV_PSV_W 8 +#define GPT_TAPV_PSV_M 0x000000FF +#define GPT_TAPV_PSV_S 0 //***************************************************************************** // @@ -1579,9 +1579,9 @@ // Field: [7:0] PSV // // GPT Timer B Pre-scaler Value -#define GPT_TBPV_PSV_W 8 -#define GPT_TBPV_PSV_M 0x000000FF -#define GPT_TBPV_PSV_S 0 +#define GPT_TBPV_PSV_W 8 +#define GPT_TBPV_PSV_M 0x000000FF +#define GPT_TBPV_PSV_S 0 //***************************************************************************** // @@ -1591,66 +1591,66 @@ // Field: [11] TBMDMAEN // // GPT Timer B Match DMA Trigger Enable -#define GPT_DMAEV_TBMDMAEN 0x00000800 -#define GPT_DMAEV_TBMDMAEN_BITN 11 -#define GPT_DMAEV_TBMDMAEN_M 0x00000800 -#define GPT_DMAEV_TBMDMAEN_S 11 +#define GPT_DMAEV_TBMDMAEN 0x00000800 +#define GPT_DMAEV_TBMDMAEN_BITN 11 +#define GPT_DMAEV_TBMDMAEN_M 0x00000800 +#define GPT_DMAEV_TBMDMAEN_S 11 // Field: [10] CBEDMAEN // // GPT Timer B Capture Event DMA Trigger Enable -#define GPT_DMAEV_CBEDMAEN 0x00000400 -#define GPT_DMAEV_CBEDMAEN_BITN 10 -#define GPT_DMAEV_CBEDMAEN_M 0x00000400 -#define GPT_DMAEV_CBEDMAEN_S 10 +#define GPT_DMAEV_CBEDMAEN 0x00000400 +#define GPT_DMAEV_CBEDMAEN_BITN 10 +#define GPT_DMAEV_CBEDMAEN_M 0x00000400 +#define GPT_DMAEV_CBEDMAEN_S 10 // Field: [9] CBMDMAEN // // GPT Timer B Capture Match DMA Trigger Enable -#define GPT_DMAEV_CBMDMAEN 0x00000200 -#define GPT_DMAEV_CBMDMAEN_BITN 9 -#define GPT_DMAEV_CBMDMAEN_M 0x00000200 -#define GPT_DMAEV_CBMDMAEN_S 9 +#define GPT_DMAEV_CBMDMAEN 0x00000200 +#define GPT_DMAEV_CBMDMAEN_BITN 9 +#define GPT_DMAEV_CBMDMAEN_M 0x00000200 +#define GPT_DMAEV_CBMDMAEN_S 9 // Field: [8] TBTODMAEN // // GPT Timer B Time-Out DMA Trigger Enable -#define GPT_DMAEV_TBTODMAEN 0x00000100 -#define GPT_DMAEV_TBTODMAEN_BITN 8 -#define GPT_DMAEV_TBTODMAEN_M 0x00000100 -#define GPT_DMAEV_TBTODMAEN_S 8 +#define GPT_DMAEV_TBTODMAEN 0x00000100 +#define GPT_DMAEV_TBTODMAEN_BITN 8 +#define GPT_DMAEV_TBTODMAEN_M 0x00000100 +#define GPT_DMAEV_TBTODMAEN_S 8 // Field: [4] TAMDMAEN // // GPT Timer A Match DMA Trigger Enable -#define GPT_DMAEV_TAMDMAEN 0x00000010 -#define GPT_DMAEV_TAMDMAEN_BITN 4 -#define GPT_DMAEV_TAMDMAEN_M 0x00000010 -#define GPT_DMAEV_TAMDMAEN_S 4 +#define GPT_DMAEV_TAMDMAEN 0x00000010 +#define GPT_DMAEV_TAMDMAEN_BITN 4 +#define GPT_DMAEV_TAMDMAEN_M 0x00000010 +#define GPT_DMAEV_TAMDMAEN_S 4 // Field: [2] CAEDMAEN // // GPT Timer A Capture Event DMA Trigger Enable -#define GPT_DMAEV_CAEDMAEN 0x00000004 -#define GPT_DMAEV_CAEDMAEN_BITN 2 -#define GPT_DMAEV_CAEDMAEN_M 0x00000004 -#define GPT_DMAEV_CAEDMAEN_S 2 +#define GPT_DMAEV_CAEDMAEN 0x00000004 +#define GPT_DMAEV_CAEDMAEN_BITN 2 +#define GPT_DMAEV_CAEDMAEN_M 0x00000004 +#define GPT_DMAEV_CAEDMAEN_S 2 // Field: [1] CAMDMAEN // // GPT Timer A Capture Match DMA Trigger Enable -#define GPT_DMAEV_CAMDMAEN 0x00000002 -#define GPT_DMAEV_CAMDMAEN_BITN 1 -#define GPT_DMAEV_CAMDMAEN_M 0x00000002 -#define GPT_DMAEV_CAMDMAEN_S 1 +#define GPT_DMAEV_CAMDMAEN 0x00000002 +#define GPT_DMAEV_CAMDMAEN_BITN 1 +#define GPT_DMAEV_CAMDMAEN_M 0x00000002 +#define GPT_DMAEV_CAMDMAEN_S 1 // Field: [0] TATODMAEN // // GPT Timer A Time-Out DMA Trigger Enable -#define GPT_DMAEV_TATODMAEN 0x00000001 -#define GPT_DMAEV_TATODMAEN_BITN 0 -#define GPT_DMAEV_TATODMAEN_M 0x00000001 -#define GPT_DMAEV_TATODMAEN_S 0 +#define GPT_DMAEV_TATODMAEN 0x00000001 +#define GPT_DMAEV_TATODMAEN_BITN 0 +#define GPT_DMAEV_TATODMAEN_M 0x00000001 +#define GPT_DMAEV_TATODMAEN_S 0 //***************************************************************************** // @@ -1660,9 +1660,9 @@ // Field: [31:0] VERSION // // Timer Revision. -#define GPT_VERSION_VERSION_W 32 -#define GPT_VERSION_VERSION_M 0xFFFFFFFF -#define GPT_VERSION_VERSION_S 0 +#define GPT_VERSION_VERSION_W 32 +#define GPT_VERSION_VERSION_M 0xFFFFFFFF +#define GPT_VERSION_VERSION_S 0 //***************************************************************************** // @@ -1677,10 +1677,9 @@ // signals of the respective timers. // 1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM // signals and Timer B PWM ouput is Timer B PWM signal only. -#define GPT_ANDCCP_CCP_AND_EN 0x00000001 -#define GPT_ANDCCP_CCP_AND_EN_BITN 0 -#define GPT_ANDCCP_CCP_AND_EN_M 0x00000001 -#define GPT_ANDCCP_CCP_AND_EN_S 0 - +#define GPT_ANDCCP_CCP_AND_EN 0x00000001 +#define GPT_ANDCCP_CCP_AND_EN_BITN 0 +#define GPT_ANDCCP_CCP_AND_EN_M 0x00000001 +#define GPT_ANDCCP_CCP_AND_EN_S 0 #endif // __GPT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_i2c.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_i2c.h index 9d0d30e..d37b80d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_i2c.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_i2c.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_i2c_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_i2c_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_I2C_H__ #define __HW_I2C_H__ @@ -44,58 +44,58 @@ // //***************************************************************************** // Slave Own Address -#define I2C_O_SOAR 0x00000000 +#define I2C_O_SOAR 0x00000000 // Slave Status -#define I2C_O_SSTAT 0x00000004 +#define I2C_O_SSTAT 0x00000004 // Slave Control -#define I2C_O_SCTL 0x00000004 +#define I2C_O_SCTL 0x00000004 // Slave Data -#define I2C_O_SDR 0x00000008 +#define I2C_O_SDR 0x00000008 // Slave Interrupt Mask -#define I2C_O_SIMR 0x0000000C +#define I2C_O_SIMR 0x0000000C // Slave Raw Interrupt Status -#define I2C_O_SRIS 0x00000010 +#define I2C_O_SRIS 0x00000010 // Slave Masked Interrupt Status -#define I2C_O_SMIS 0x00000014 +#define I2C_O_SMIS 0x00000014 // Slave Interrupt Clear -#define I2C_O_SICR 0x00000018 +#define I2C_O_SICR 0x00000018 // Master Salve Address -#define I2C_O_MSA 0x00000800 +#define I2C_O_MSA 0x00000800 // Master Status -#define I2C_O_MSTAT 0x00000804 +#define I2C_O_MSTAT 0x00000804 // Master Control -#define I2C_O_MCTRL 0x00000804 +#define I2C_O_MCTRL 0x00000804 // Master Data -#define I2C_O_MDR 0x00000808 +#define I2C_O_MDR 0x00000808 // I2C Master Timer Period -#define I2C_O_MTPR 0x0000080C +#define I2C_O_MTPR 0x0000080C // Master Interrupt Mask -#define I2C_O_MIMR 0x00000810 +#define I2C_O_MIMR 0x00000810 // Master Raw Interrupt Status -#define I2C_O_MRIS 0x00000814 +#define I2C_O_MRIS 0x00000814 // Master Masked Interrupt Status -#define I2C_O_MMIS 0x00000818 +#define I2C_O_MMIS 0x00000818 // Master Interrupt Clear -#define I2C_O_MICR 0x0000081C +#define I2C_O_MICR 0x0000081C // Master Configuration -#define I2C_O_MCR 0x00000820 +#define I2C_O_MCR 0x00000820 //***************************************************************************** // @@ -106,9 +106,9 @@ // // I2C slave own address // This field specifies bits a6 through a0 of the slave address. -#define I2C_SOAR_OAR_W 7 -#define I2C_SOAR_OAR_M 0x0000007F -#define I2C_SOAR_OAR_S 0 +#define I2C_SOAR_OAR_W 7 +#define I2C_SOAR_OAR_M 0x0000007F +#define I2C_SOAR_OAR_S 0 //***************************************************************************** // @@ -125,10 +125,10 @@ // This bit is only valid when the RREQ bit is set and is automatically cleared // when data has been read from the SDR register. // Note: This bit is not used for slave transmit operations. -#define I2C_SSTAT_FBR 0x00000004 -#define I2C_SSTAT_FBR_BITN 2 -#define I2C_SSTAT_FBR_M 0x00000004 -#define I2C_SSTAT_FBR_S 2 +#define I2C_SSTAT_FBR 0x00000004 +#define I2C_SSTAT_FBR_BITN 2 +#define I2C_SSTAT_FBR_M 0x00000004 +#define I2C_SSTAT_FBR_S 2 // Field: [1] TREQ // @@ -138,10 +138,10 @@ // 1: The I2C controller has been addressed as a slave transmitter and is using // clock stretching to delay the master until data has been written to the SDR // register. -#define I2C_SSTAT_TREQ 0x00000002 -#define I2C_SSTAT_TREQ_BITN 1 -#define I2C_SSTAT_TREQ_M 0x00000002 -#define I2C_SSTAT_TREQ_S 1 +#define I2C_SSTAT_TREQ 0x00000002 +#define I2C_SSTAT_TREQ_BITN 1 +#define I2C_SSTAT_TREQ_M 0x00000002 +#define I2C_SSTAT_TREQ_S 1 // Field: [0] RREQ // @@ -151,10 +151,10 @@ // 1: The I2C controller has outstanding receive data from the I2C master and // is using clock stretching to delay the master until data has been read from // the SDR register. -#define I2C_SSTAT_RREQ 0x00000001 -#define I2C_SSTAT_RREQ_BITN 0 -#define I2C_SSTAT_RREQ_M 0x00000001 -#define I2C_SSTAT_RREQ_S 0 +#define I2C_SSTAT_RREQ 0x00000001 +#define I2C_SSTAT_RREQ_BITN 0 +#define I2C_SSTAT_RREQ_M 0x00000001 +#define I2C_SSTAT_RREQ_S 0 //***************************************************************************** // @@ -167,10 +167,10 @@ // // 0: Disables the I2C slave operation // 1: Enables the I2C slave operation -#define I2C_SCTL_DA 0x00000001 -#define I2C_SCTL_DA_BITN 0 -#define I2C_SCTL_DA_M 0x00000001 -#define I2C_SCTL_DA_S 0 +#define I2C_SCTL_DA 0x00000001 +#define I2C_SCTL_DA_BITN 0 +#define I2C_SCTL_DA_M 0x00000001 +#define I2C_SCTL_DA_S 0 //***************************************************************************** // @@ -185,9 +185,9 @@ // read, this register returns the last data received. // Data is stored until next update, either by a system write for transmit or // by an external master for receive. -#define I2C_SDR_DATA_W 8 -#define I2C_SDR_DATA_M 0x000000FF -#define I2C_SDR_DATA_S 0 +#define I2C_SDR_DATA_W 8 +#define I2C_SDR_DATA_M 0x000000FF +#define I2C_SDR_DATA_S 0 //***************************************************************************** // @@ -205,12 +205,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define I2C_SIMR_STOPIM 0x00000004 -#define I2C_SIMR_STOPIM_BITN 2 -#define I2C_SIMR_STOPIM_M 0x00000004 -#define I2C_SIMR_STOPIM_S 2 -#define I2C_SIMR_STOPIM_EN 0x00000004 -#define I2C_SIMR_STOPIM_DIS 0x00000000 +#define I2C_SIMR_STOPIM 0x00000004 +#define I2C_SIMR_STOPIM_BITN 2 +#define I2C_SIMR_STOPIM_M 0x00000004 +#define I2C_SIMR_STOPIM_S 2 +#define I2C_SIMR_STOPIM_EN 0x00000004 +#define I2C_SIMR_STOPIM_DIS 0x00000000 // Field: [1] STARTIM // @@ -223,12 +223,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define I2C_SIMR_STARTIM 0x00000002 -#define I2C_SIMR_STARTIM_BITN 1 -#define I2C_SIMR_STARTIM_M 0x00000002 -#define I2C_SIMR_STARTIM_S 1 -#define I2C_SIMR_STARTIM_EN 0x00000002 -#define I2C_SIMR_STARTIM_DIS 0x00000000 +#define I2C_SIMR_STARTIM 0x00000002 +#define I2C_SIMR_STARTIM_BITN 1 +#define I2C_SIMR_STARTIM_M 0x00000002 +#define I2C_SIMR_STARTIM_S 1 +#define I2C_SIMR_STARTIM_EN 0x00000002 +#define I2C_SIMR_STARTIM_DIS 0x00000000 // Field: [0] DATAIM // @@ -238,10 +238,10 @@ // controller. // 1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt // controller. -#define I2C_SIMR_DATAIM 0x00000001 -#define I2C_SIMR_DATAIM_BITN 0 -#define I2C_SIMR_DATAIM_M 0x00000001 -#define I2C_SIMR_DATAIM_S 0 +#define I2C_SIMR_DATAIM 0x00000001 +#define I2C_SIMR_DATAIM_BITN 0 +#define I2C_SIMR_DATAIM_M 0x00000001 +#define I2C_SIMR_DATAIM_S 0 //***************************************************************************** // @@ -256,10 +256,10 @@ // 1: A Stop condition interrupt is pending. // // This bit is cleared by writing a 1 to SICR.STOPIC. -#define I2C_SRIS_STOPRIS 0x00000004 -#define I2C_SRIS_STOPRIS_BITN 2 -#define I2C_SRIS_STOPRIS_M 0x00000004 -#define I2C_SRIS_STOPRIS_S 2 +#define I2C_SRIS_STOPRIS 0x00000004 +#define I2C_SRIS_STOPRIS_BITN 2 +#define I2C_SRIS_STOPRIS_M 0x00000004 +#define I2C_SRIS_STOPRIS_S 2 // Field: [1] STARTRIS // @@ -269,10 +269,10 @@ // 1: A Start condition interrupt is pending. // // This bit is cleared by writing a 1 to SICR.STARTIC. -#define I2C_SRIS_STARTRIS 0x00000002 -#define I2C_SRIS_STARTRIS_BITN 1 -#define I2C_SRIS_STARTRIS_M 0x00000002 -#define I2C_SRIS_STARTRIS_S 1 +#define I2C_SRIS_STARTRIS 0x00000002 +#define I2C_SRIS_STARTRIS_BITN 1 +#define I2C_SRIS_STARTRIS_M 0x00000002 +#define I2C_SRIS_STARTRIS_S 1 // Field: [0] DATARIS // @@ -282,10 +282,10 @@ // 1: A data received or data requested interrupt is pending. // // This bit is cleared by writing a 1 to the SICR.DATAIC. -#define I2C_SRIS_DATARIS 0x00000001 -#define I2C_SRIS_DATARIS_BITN 0 -#define I2C_SRIS_DATARIS_M 0x00000001 -#define I2C_SRIS_DATARIS_S 0 +#define I2C_SRIS_DATARIS 0x00000001 +#define I2C_SRIS_DATARIS_BITN 0 +#define I2C_SRIS_DATARIS_M 0x00000001 +#define I2C_SRIS_DATARIS_S 0 //***************************************************************************** // @@ -300,10 +300,10 @@ // 1: An unmasked Stop condition interrupt is pending. // // This bit is cleared by writing a 1 to the SICR.STOPIC. -#define I2C_SMIS_STOPMIS 0x00000004 -#define I2C_SMIS_STOPMIS_BITN 2 -#define I2C_SMIS_STOPMIS_M 0x00000004 -#define I2C_SMIS_STOPMIS_S 2 +#define I2C_SMIS_STOPMIS 0x00000004 +#define I2C_SMIS_STOPMIS_BITN 2 +#define I2C_SMIS_STOPMIS_M 0x00000004 +#define I2C_SMIS_STOPMIS_S 2 // Field: [1] STARTMIS // @@ -313,10 +313,10 @@ // 1: An unmasked Start condition interrupt is pending. // // This bit is cleared by writing a 1 to the SICR.STARTIC. -#define I2C_SMIS_STARTMIS 0x00000002 -#define I2C_SMIS_STARTMIS_BITN 1 -#define I2C_SMIS_STARTMIS_M 0x00000002 -#define I2C_SMIS_STARTMIS_S 1 +#define I2C_SMIS_STARTMIS 0x00000002 +#define I2C_SMIS_STARTMIS_BITN 1 +#define I2C_SMIS_STARTMIS_M 0x00000002 +#define I2C_SMIS_STARTMIS_S 1 // Field: [0] DATAMIS // @@ -326,10 +326,10 @@ // 1: An unmasked data received or data requested interrupt is pending. // // This bit is cleared by writing a 1 to the SICR.DATAIC. -#define I2C_SMIS_DATAMIS 0x00000001 -#define I2C_SMIS_DATAMIS_BITN 0 -#define I2C_SMIS_DATAMIS_M 0x00000001 -#define I2C_SMIS_DATAMIS_S 0 +#define I2C_SMIS_DATAMIS 0x00000001 +#define I2C_SMIS_DATAMIS_BITN 0 +#define I2C_SMIS_DATAMIS_M 0x00000001 +#define I2C_SMIS_DATAMIS_S 0 //***************************************************************************** // @@ -341,30 +341,30 @@ // Stop condition interrupt clear // // Writing 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS. -#define I2C_SICR_STOPIC 0x00000004 -#define I2C_SICR_STOPIC_BITN 2 -#define I2C_SICR_STOPIC_M 0x00000004 -#define I2C_SICR_STOPIC_S 2 +#define I2C_SICR_STOPIC 0x00000004 +#define I2C_SICR_STOPIC_BITN 2 +#define I2C_SICR_STOPIC_M 0x00000004 +#define I2C_SICR_STOPIC_S 2 // Field: [1] STARTIC // // Start condition interrupt clear // // Writing 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS. -#define I2C_SICR_STARTIC 0x00000002 -#define I2C_SICR_STARTIC_BITN 1 -#define I2C_SICR_STARTIC_M 0x00000002 -#define I2C_SICR_STARTIC_S 1 +#define I2C_SICR_STARTIC 0x00000002 +#define I2C_SICR_STARTIC_BITN 1 +#define I2C_SICR_STARTIC_M 0x00000002 +#define I2C_SICR_STARTIC_S 1 // Field: [0] DATAIC // // Data interrupt clear // // Writing 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS. -#define I2C_SICR_DATAIC 0x00000001 -#define I2C_SICR_DATAIC_BITN 0 -#define I2C_SICR_DATAIC_M 0x00000001 -#define I2C_SICR_DATAIC_S 0 +#define I2C_SICR_DATAIC 0x00000001 +#define I2C_SICR_DATAIC_BITN 0 +#define I2C_SICR_DATAIC_M 0x00000001 +#define I2C_SICR_DATAIC_S 0 //***************************************************************************** // @@ -375,9 +375,9 @@ // // I2C master slave address // Defines which slave is addressed for the transaction in master mode -#define I2C_MSA_SA_W 7 -#define I2C_MSA_SA_M 0x000000FE -#define I2C_MSA_SA_S 1 +#define I2C_MSA_SA_W 7 +#define I2C_MSA_SA_M 0x000000FE +#define I2C_MSA_SA_S 1 // Field: [0] RS // @@ -387,12 +387,12 @@ // ENUMs: // RX Receive data from slave // TX Transmit/send data to slave -#define I2C_MSA_RS 0x00000001 -#define I2C_MSA_RS_BITN 0 -#define I2C_MSA_RS_M 0x00000001 -#define I2C_MSA_RS_S 0 -#define I2C_MSA_RS_RX 0x00000001 -#define I2C_MSA_RS_TX 0x00000000 +#define I2C_MSA_RS 0x00000001 +#define I2C_MSA_RS_BITN 0 +#define I2C_MSA_RS_M 0x00000001 +#define I2C_MSA_RS_S 0 +#define I2C_MSA_RS_RX 0x00000001 +#define I2C_MSA_RS_TX 0x00000000 //***************************************************************************** // @@ -407,10 +407,10 @@ // 1: The I2C bus is busy. // // The bit changes based on the MCTRL.START and MCTRL.STOP conditions. -#define I2C_MSTAT_BUSBSY 0x00000040 -#define I2C_MSTAT_BUSBSY_BITN 6 -#define I2C_MSTAT_BUSBSY_M 0x00000040 -#define I2C_MSTAT_BUSBSY_S 6 +#define I2C_MSTAT_BUSBSY 0x00000040 +#define I2C_MSTAT_BUSBSY_BITN 6 +#define I2C_MSTAT_BUSBSY_M 0x00000040 +#define I2C_MSTAT_BUSBSY_S 6 // Field: [5] IDLE // @@ -418,10 +418,10 @@ // // 0: The I2C controller is not idle. // 1: The I2C controller is idle. -#define I2C_MSTAT_IDLE 0x00000020 -#define I2C_MSTAT_IDLE_BITN 5 -#define I2C_MSTAT_IDLE_M 0x00000020 -#define I2C_MSTAT_IDLE_S 5 +#define I2C_MSTAT_IDLE 0x00000020 +#define I2C_MSTAT_IDLE_BITN 5 +#define I2C_MSTAT_IDLE_M 0x00000020 +#define I2C_MSTAT_IDLE_S 5 // Field: [4] ARBLST // @@ -429,10 +429,10 @@ // // 0: The I2C controller won arbitration. // 1: The I2C controller lost arbitration. -#define I2C_MSTAT_ARBLST 0x00000010 -#define I2C_MSTAT_ARBLST_BITN 4 -#define I2C_MSTAT_ARBLST_M 0x00000010 -#define I2C_MSTAT_ARBLST_S 4 +#define I2C_MSTAT_ARBLST 0x00000010 +#define I2C_MSTAT_ARBLST_BITN 4 +#define I2C_MSTAT_ARBLST_M 0x00000010 +#define I2C_MSTAT_ARBLST_S 4 // Field: [3] DATACK_N // @@ -440,10 +440,10 @@ // // 0: The transmitted data was acknowledged. // 1: The transmitted data was not acknowledged. -#define I2C_MSTAT_DATACK_N 0x00000008 -#define I2C_MSTAT_DATACK_N_BITN 3 -#define I2C_MSTAT_DATACK_N_M 0x00000008 -#define I2C_MSTAT_DATACK_N_S 3 +#define I2C_MSTAT_DATACK_N 0x00000008 +#define I2C_MSTAT_DATACK_N_BITN 3 +#define I2C_MSTAT_DATACK_N_M 0x00000008 +#define I2C_MSTAT_DATACK_N_S 3 // Field: [2] ADRACK_N // @@ -451,10 +451,10 @@ // // 0: The transmitted address was acknowledged. // 1: The transmitted address was not acknowledged. -#define I2C_MSTAT_ADRACK_N 0x00000004 -#define I2C_MSTAT_ADRACK_N_BITN 2 -#define I2C_MSTAT_ADRACK_N_M 0x00000004 -#define I2C_MSTAT_ADRACK_N_S 2 +#define I2C_MSTAT_ADRACK_N 0x00000004 +#define I2C_MSTAT_ADRACK_N_BITN 2 +#define I2C_MSTAT_ADRACK_N_M 0x00000004 +#define I2C_MSTAT_ADRACK_N_S 2 // Field: [1] ERR // @@ -462,10 +462,10 @@ // // 0: No error was detected on the last operation. // 1: An error occurred on the last operation. -#define I2C_MSTAT_ERR 0x00000002 -#define I2C_MSTAT_ERR_BITN 1 -#define I2C_MSTAT_ERR_M 0x00000002 -#define I2C_MSTAT_ERR_S 1 +#define I2C_MSTAT_ERR 0x00000002 +#define I2C_MSTAT_ERR_BITN 1 +#define I2C_MSTAT_ERR_M 0x00000002 +#define I2C_MSTAT_ERR_S 1 // Field: [0] BUSY // @@ -483,10 +483,10 @@ // four SYSBUS clock cycles before issuing a controller status inquiry through // MSTAT register. // Any prior inquiry would result in wrong status being reported. -#define I2C_MSTAT_BUSY 0x00000001 -#define I2C_MSTAT_BUSY_BITN 0 -#define I2C_MSTAT_BUSY_M 0x00000001 -#define I2C_MSTAT_BUSY_S 0 +#define I2C_MSTAT_BUSY 0x00000001 +#define I2C_MSTAT_BUSY_BITN 0 +#define I2C_MSTAT_BUSY_M 0x00000001 +#define I2C_MSTAT_BUSY_S 0 //***************************************************************************** // @@ -505,12 +505,12 @@ // ENUMs: // EN Enable acknowledge // DIS Disable acknowledge -#define I2C_MCTRL_ACK 0x00000008 -#define I2C_MCTRL_ACK_BITN 3 -#define I2C_MCTRL_ACK_M 0x00000008 -#define I2C_MCTRL_ACK_S 3 -#define I2C_MCTRL_ACK_EN 0x00000008 -#define I2C_MCTRL_ACK_DIS 0x00000000 +#define I2C_MCTRL_ACK 0x00000008 +#define I2C_MCTRL_ACK_BITN 3 +#define I2C_MCTRL_ACK_M 0x00000008 +#define I2C_MCTRL_ACK_S 3 +#define I2C_MCTRL_ACK_EN 0x00000008 +#define I2C_MCTRL_ACK_DIS 0x00000000 // Field: [2] STOP // @@ -522,12 +522,12 @@ // ENUMs: // EN Enable STOP // DIS Disable STOP -#define I2C_MCTRL_STOP 0x00000004 -#define I2C_MCTRL_STOP_BITN 2 -#define I2C_MCTRL_STOP_M 0x00000004 -#define I2C_MCTRL_STOP_S 2 -#define I2C_MCTRL_STOP_EN 0x00000004 -#define I2C_MCTRL_STOP_DIS 0x00000000 +#define I2C_MCTRL_STOP 0x00000004 +#define I2C_MCTRL_STOP_BITN 2 +#define I2C_MCTRL_STOP_M 0x00000004 +#define I2C_MCTRL_STOP_S 2 +#define I2C_MCTRL_STOP_EN 0x00000004 +#define I2C_MCTRL_STOP_DIS 0x00000000 // Field: [1] START // @@ -538,12 +538,12 @@ // ENUMs: // EN Enable START // DIS Disable START -#define I2C_MCTRL_START 0x00000002 -#define I2C_MCTRL_START_BITN 1 -#define I2C_MCTRL_START_M 0x00000002 -#define I2C_MCTRL_START_S 1 -#define I2C_MCTRL_START_EN 0x00000002 -#define I2C_MCTRL_START_DIS 0x00000000 +#define I2C_MCTRL_START 0x00000002 +#define I2C_MCTRL_START_BITN 1 +#define I2C_MCTRL_START_M 0x00000002 +#define I2C_MCTRL_START_S 1 +#define I2C_MCTRL_START_EN 0x00000002 +#define I2C_MCTRL_START_DIS 0x00000000 // Field: [0] RUN // @@ -554,12 +554,12 @@ // ENUMs: // EN Enable Master // DIS Disable Master -#define I2C_MCTRL_RUN 0x00000001 -#define I2C_MCTRL_RUN_BITN 0 -#define I2C_MCTRL_RUN_M 0x00000001 -#define I2C_MCTRL_RUN_S 0 -#define I2C_MCTRL_RUN_EN 0x00000001 -#define I2C_MCTRL_RUN_DIS 0x00000000 +#define I2C_MCTRL_RUN 0x00000001 +#define I2C_MCTRL_RUN_BITN 0 +#define I2C_MCTRL_RUN_M 0x00000001 +#define I2C_MCTRL_RUN_S 0 +#define I2C_MCTRL_RUN_EN 0x00000001 +#define I2C_MCTRL_RUN_DIS 0x00000000 //***************************************************************************** // @@ -570,9 +570,9 @@ // // When Read: Last RX Data is returned // When Written: Data is transferred during TX transaction -#define I2C_MDR_DATA_W 8 -#define I2C_MDR_DATA_M 0x000000FF -#define I2C_MDR_DATA_S 0 +#define I2C_MDR_DATA_W 8 +#define I2C_MDR_DATA_M 0x000000FF +#define I2C_MDR_DATA_S 0 //***************************************************************************** // @@ -582,10 +582,10 @@ // Field: [7] TPR_7 // // Must be set to 0 to set TPR. If set to 1, a write to TPR will be ignored. -#define I2C_MTPR_TPR_7 0x00000080 -#define I2C_MTPR_TPR_7_BITN 7 -#define I2C_MTPR_TPR_7_M 0x00000080 -#define I2C_MTPR_TPR_7_S 7 +#define I2C_MTPR_TPR_7 0x00000080 +#define I2C_MTPR_TPR_7_BITN 7 +#define I2C_MTPR_TPR_7_M 0x00000080 +#define I2C_MTPR_TPR_7_S 7 // Field: [6:0] TPR // @@ -598,9 +598,9 @@ // SCL_LP is the SCL low period (fixed at 6). // SCL_HP is the SCL high period (fixed at 4). // CLK_PRD is the system clock period in ns. -#define I2C_MTPR_TPR_W 7 -#define I2C_MTPR_TPR_M 0x0000007F -#define I2C_MTPR_TPR_S 0 +#define I2C_MTPR_TPR_W 7 +#define I2C_MTPR_TPR_M 0x0000007F +#define I2C_MTPR_TPR_S 0 //***************************************************************************** // @@ -618,12 +618,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define I2C_MIMR_IM 0x00000001 -#define I2C_MIMR_IM_BITN 0 -#define I2C_MIMR_IM_M 0x00000001 -#define I2C_MIMR_IM_S 0 -#define I2C_MIMR_IM_EN 0x00000001 -#define I2C_MIMR_IM_DIS 0x00000000 +#define I2C_MIMR_IM 0x00000001 +#define I2C_MIMR_IM_BITN 0 +#define I2C_MIMR_IM_M 0x00000001 +#define I2C_MIMR_IM_S 0 +#define I2C_MIMR_IM_EN 0x00000001 +#define I2C_MIMR_IM_DIS 0x00000000 //***************************************************************************** // @@ -638,10 +638,10 @@ // 1: A master interrupt is pending. // // This bit is cleared by writing 1 to the MICR.IC bit . -#define I2C_MRIS_RIS 0x00000001 -#define I2C_MRIS_RIS_BITN 0 -#define I2C_MRIS_RIS_M 0x00000001 -#define I2C_MRIS_RIS_S 0 +#define I2C_MRIS_RIS 0x00000001 +#define I2C_MRIS_RIS_BITN 0 +#define I2C_MRIS_RIS_M 0x00000001 +#define I2C_MRIS_RIS_S 0 //***************************************************************************** // @@ -656,10 +656,10 @@ // 1: A master interrupt is pending. // // This bit is cleared by writing 1 to the MICR.IC bit . -#define I2C_MMIS_MIS 0x00000001 -#define I2C_MMIS_MIS_BITN 0 -#define I2C_MMIS_MIS_M 0x00000001 -#define I2C_MMIS_MIS_S 0 +#define I2C_MMIS_MIS 0x00000001 +#define I2C_MMIS_MIS_BITN 0 +#define I2C_MMIS_MIS_M 0x00000001 +#define I2C_MMIS_MIS_S 0 //***************************************************************************** // @@ -672,10 +672,10 @@ // Writing 1 to this bit clears MRIS.RIS and MMIS.MIS . // // Reading this register returns no meaningful data. -#define I2C_MICR_IC 0x00000001 -#define I2C_MICR_IC_BITN 0 -#define I2C_MICR_IC_M 0x00000001 -#define I2C_MICR_IC_S 0 +#define I2C_MICR_IC 0x00000001 +#define I2C_MICR_IC_BITN 0 +#define I2C_MICR_IC_M 0x00000001 +#define I2C_MICR_IC_S 0 //***************************************************************************** // @@ -688,12 +688,12 @@ // ENUMs: // EN Slave mode is enabled. // DIS Slave mode is disabled. -#define I2C_MCR_SFE 0x00000020 -#define I2C_MCR_SFE_BITN 5 -#define I2C_MCR_SFE_M 0x00000020 -#define I2C_MCR_SFE_S 5 -#define I2C_MCR_SFE_EN 0x00000020 -#define I2C_MCR_SFE_DIS 0x00000000 +#define I2C_MCR_SFE 0x00000020 +#define I2C_MCR_SFE_BITN 5 +#define I2C_MCR_SFE_M 0x00000020 +#define I2C_MCR_SFE_S 5 +#define I2C_MCR_SFE_EN 0x00000020 +#define I2C_MCR_SFE_DIS 0x00000000 // Field: [4] MFE // @@ -701,12 +701,12 @@ // ENUMs: // EN Master mode is enabled. // DIS Master mode is disabled. -#define I2C_MCR_MFE 0x00000010 -#define I2C_MCR_MFE_BITN 4 -#define I2C_MCR_MFE_M 0x00000010 -#define I2C_MCR_MFE_S 4 -#define I2C_MCR_MFE_EN 0x00000010 -#define I2C_MCR_MFE_DIS 0x00000000 +#define I2C_MCR_MFE 0x00000010 +#define I2C_MCR_MFE_BITN 4 +#define I2C_MCR_MFE_M 0x00000010 +#define I2C_MCR_MFE_S 4 +#define I2C_MCR_MFE_EN 0x00000010 +#define I2C_MCR_MFE_DIS 0x00000000 // Field: [0] LPBK // @@ -717,12 +717,11 @@ // ENUMs: // EN Enable Test Mode // DIS Disable Test Mode -#define I2C_MCR_LPBK 0x00000001 -#define I2C_MCR_LPBK_BITN 0 -#define I2C_MCR_LPBK_M 0x00000001 -#define I2C_MCR_LPBK_S 0 -#define I2C_MCR_LPBK_EN 0x00000001 -#define I2C_MCR_LPBK_DIS 0x00000000 - +#define I2C_MCR_LPBK 0x00000001 +#define I2C_MCR_LPBK_BITN 0 +#define I2C_MCR_LPBK_M 0x00000001 +#define I2C_MCR_LPBK_S 0 +#define I2C_MCR_LPBK_EN 0x00000001 +#define I2C_MCR_LPBK_DIS 0x00000000 #endif // __I2C__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_i2s.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_i2s.h index ee850c7..7d5d7da 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_i2s.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_i2s.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_i2s_h -* Revised: 2017-11-02 10:21:28 +0100 (Thu, 02 Nov 2017) -* Revision: 50141 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_i2s_h + * Revised: 2017-11-02 10:21:28 +0100 (Thu, 02 Nov 2017) + * Revision: 50141 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_I2S_H__ #define __HW_I2S_H__ @@ -44,91 +44,91 @@ // //***************************************************************************** // WCLK Source Selection -#define I2S_O_AIFWCLKSRC 0x00000000 +#define I2S_O_AIFWCLKSRC 0x00000000 // DMA Buffer Size Configuration -#define I2S_O_AIFDMACFG 0x00000004 +#define I2S_O_AIFDMACFG 0x00000004 // Pin Direction -#define I2S_O_AIFDIRCFG 0x00000008 +#define I2S_O_AIFDIRCFG 0x00000008 // Serial Interface Format Configuration -#define I2S_O_AIFFMTCFG 0x0000000C +#define I2S_O_AIFFMTCFG 0x0000000C // Word Selection Bit Mask for Pin 0 -#define I2S_O_AIFWMASK0 0x00000010 +#define I2S_O_AIFWMASK0 0x00000010 // Word Selection Bit Mask for Pin 1 -#define I2S_O_AIFWMASK1 0x00000014 +#define I2S_O_AIFWMASK1 0x00000014 // Audio Interface PWM Debug Value -#define I2S_O_AIFPWMVALUE 0x0000001C +#define I2S_O_AIFPWMVALUE 0x0000001C // DMA Input Buffer Next Pointer -#define I2S_O_AIFINPTRNEXT 0x00000020 +#define I2S_O_AIFINPTRNEXT 0x00000020 // DMA Input Buffer Current Pointer -#define I2S_O_AIFINPTR 0x00000024 +#define I2S_O_AIFINPTR 0x00000024 // DMA Output Buffer Next Pointer -#define I2S_O_AIFOUTPTRNEXT 0x00000028 +#define I2S_O_AIFOUTPTRNEXT 0x00000028 // DMA Output Buffer Current Pointer -#define I2S_O_AIFOUTPTR 0x0000002C +#define I2S_O_AIFOUTPTR 0x0000002C // Samplestamp Generator Control Register -#define I2S_O_STMPCTL 0x00000034 +#define I2S_O_STMPCTL 0x00000034 // Captured XOSC Counter Value, Capture Channel 0 -#define I2S_O_STMPXCNTCAPT0 0x00000038 +#define I2S_O_STMPXCNTCAPT0 0x00000038 // XOSC Period Value -#define I2S_O_STMPXPER 0x0000003C +#define I2S_O_STMPXPER 0x0000003C // Captured WCLK Counter Value, Capture Channel 0 -#define I2S_O_STMPWCNTCAPT0 0x00000040 +#define I2S_O_STMPWCNTCAPT0 0x00000040 // WCLK Counter Period Value -#define I2S_O_STMPWPER 0x00000044 +#define I2S_O_STMPWPER 0x00000044 // WCLK Counter Trigger Value for Input Pins -#define I2S_O_STMPINTRIG 0x00000048 +#define I2S_O_STMPINTRIG 0x00000048 // WCLK Counter Trigger Value for Output Pins -#define I2S_O_STMPOUTTRIG 0x0000004C +#define I2S_O_STMPOUTTRIG 0x0000004C // WCLK Counter Set Operation -#define I2S_O_STMPWSET 0x00000050 +#define I2S_O_STMPWSET 0x00000050 // WCLK Counter Add Operation -#define I2S_O_STMPWADD 0x00000054 +#define I2S_O_STMPWADD 0x00000054 // XOSC Minimum Period Value -#define I2S_O_STMPXPERMIN 0x00000058 +#define I2S_O_STMPXPERMIN 0x00000058 // Current Value of WCNT -#define I2S_O_STMPWCNT 0x0000005C +#define I2S_O_STMPWCNT 0x0000005C // Current Value of XCNT -#define I2S_O_STMPXCNT 0x00000060 +#define I2S_O_STMPXCNT 0x00000060 // Internal -#define I2S_O_STMPXCNTCAPT1 0x00000064 +#define I2S_O_STMPXCNTCAPT1 0x00000064 // Internal -#define I2S_O_STMPWCNTCAPT1 0x00000068 +#define I2S_O_STMPWCNTCAPT1 0x00000068 // Interrupt Mask Register -#define I2S_O_IRQMASK 0x00000070 +#define I2S_O_IRQMASK 0x00000070 // Raw Interrupt Status Register -#define I2S_O_IRQFLAGS 0x00000074 +#define I2S_O_IRQFLAGS 0x00000074 // Interrupt Set Register -#define I2S_O_IRQSET 0x00000078 +#define I2S_O_IRQSET 0x00000078 // Interrupt Clear Register -#define I2S_O_IRQCLR 0x0000007C +#define I2S_O_IRQCLR 0x0000007C //***************************************************************************** // @@ -141,10 +141,10 @@ // // 0: Not inverted // 1: Inverted -#define I2S_AIFWCLKSRC_WCLK_INV 0x00000004 -#define I2S_AIFWCLKSRC_WCLK_INV_BITN 2 -#define I2S_AIFWCLKSRC_WCLK_INV_M 0x00000004 -#define I2S_AIFWCLKSRC_WCLK_INV_S 2 +#define I2S_AIFWCLKSRC_WCLK_INV 0x00000004 +#define I2S_AIFWCLKSRC_WCLK_INV_BITN 2 +#define I2S_AIFWCLKSRC_WCLK_INV_M 0x00000004 +#define I2S_AIFWCLKSRC_WCLK_INV_S 2 // Field: [1:0] WCLK_SRC // @@ -156,13 +156,13 @@ // INT Internal WCLK generator, from module PRCM // EXT External WCLK generator, from pad // NONE None ('0') -#define I2S_AIFWCLKSRC_WCLK_SRC_W 2 -#define I2S_AIFWCLKSRC_WCLK_SRC_M 0x00000003 -#define I2S_AIFWCLKSRC_WCLK_SRC_S 0 -#define I2S_AIFWCLKSRC_WCLK_SRC_RESERVED 0x00000003 -#define I2S_AIFWCLKSRC_WCLK_SRC_INT 0x00000002 -#define I2S_AIFWCLKSRC_WCLK_SRC_EXT 0x00000001 -#define I2S_AIFWCLKSRC_WCLK_SRC_NONE 0x00000000 +#define I2S_AIFWCLKSRC_WCLK_SRC_W 2 +#define I2S_AIFWCLKSRC_WCLK_SRC_M 0x00000003 +#define I2S_AIFWCLKSRC_WCLK_SRC_S 0 +#define I2S_AIFWCLKSRC_WCLK_SRC_RESERVED 0x00000003 +#define I2S_AIFWCLKSRC_WCLK_SRC_INT 0x00000002 +#define I2S_AIFWCLKSRC_WCLK_SRC_EXT 0x00000001 +#define I2S_AIFWCLKSRC_WCLK_SRC_NONE 0x00000000 //***************************************************************************** // @@ -175,9 +175,9 @@ // register field enables and initializes AIF. Note that before doing so, all // other configuration must have been done, and AIFINPTRNEXT/AIFOUTPTRNEXT must // have been loaded. -#define I2S_AIFDMACFG_END_FRAME_IDX_W 8 -#define I2S_AIFDMACFG_END_FRAME_IDX_M 0x000000FF -#define I2S_AIFDMACFG_END_FRAME_IDX_S 0 +#define I2S_AIFDMACFG_END_FRAME_IDX_W 8 +#define I2S_AIFDMACFG_END_FRAME_IDX_M 0x000000FF +#define I2S_AIFDMACFG_END_FRAME_IDX_S 0 //***************************************************************************** // @@ -193,12 +193,12 @@ // OUT Output mode // IN Input mode // DIS Not in use (disabled) -#define I2S_AIFDIRCFG_AD1_W 2 -#define I2S_AIFDIRCFG_AD1_M 0x00000030 -#define I2S_AIFDIRCFG_AD1_S 4 -#define I2S_AIFDIRCFG_AD1_OUT 0x00000020 -#define I2S_AIFDIRCFG_AD1_IN 0x00000010 -#define I2S_AIFDIRCFG_AD1_DIS 0x00000000 +#define I2S_AIFDIRCFG_AD1_W 2 +#define I2S_AIFDIRCFG_AD1_M 0x00000030 +#define I2S_AIFDIRCFG_AD1_S 4 +#define I2S_AIFDIRCFG_AD1_OUT 0x00000020 +#define I2S_AIFDIRCFG_AD1_IN 0x00000010 +#define I2S_AIFDIRCFG_AD1_DIS 0x00000000 // Field: [1:0] AD0 // @@ -209,12 +209,12 @@ // OUT Output mode // IN Input mode // DIS Not in use (disabled) -#define I2S_AIFDIRCFG_AD0_W 2 -#define I2S_AIFDIRCFG_AD0_M 0x00000003 -#define I2S_AIFDIRCFG_AD0_S 0 -#define I2S_AIFDIRCFG_AD0_OUT 0x00000002 -#define I2S_AIFDIRCFG_AD0_IN 0x00000001 -#define I2S_AIFDIRCFG_AD0_DIS 0x00000000 +#define I2S_AIFDIRCFG_AD0_W 2 +#define I2S_AIFDIRCFG_AD0_M 0x00000003 +#define I2S_AIFDIRCFG_AD0_S 0 +#define I2S_AIFDIRCFG_AD0_OUT 0x00000002 +#define I2S_AIFDIRCFG_AD0_IN 0x00000001 +#define I2S_AIFDIRCFG_AD0_DIS 0x00000000 //***************************************************************************** // @@ -235,9 +235,9 @@ // Note: When 0, MSB of the next word will be output in the idle period between // LSB of the previous word and the start of the next word. Otherwise logical 0 // will be output until the data delay has expired. -#define I2S_AIFFMTCFG_DATA_DELAY_W 8 -#define I2S_AIFFMTCFG_DATA_DELAY_M 0x0000FF00 -#define I2S_AIFFMTCFG_DATA_DELAY_S 8 +#define I2S_AIFFMTCFG_DATA_DELAY_W 8 +#define I2S_AIFFMTCFG_DATA_DELAY_M 0x0000FF00 +#define I2S_AIFFMTCFG_DATA_DELAY_S 8 // Field: [7] MEM_LEN_24 // @@ -246,12 +246,12 @@ // 24BIT 24-bit (one 8 bit and one 16 bit locked access per // sample) // 16BIT 16-bit (one 16 bit access per sample) -#define I2S_AIFFMTCFG_MEM_LEN_24 0x00000080 -#define I2S_AIFFMTCFG_MEM_LEN_24_BITN 7 -#define I2S_AIFFMTCFG_MEM_LEN_24_M 0x00000080 -#define I2S_AIFFMTCFG_MEM_LEN_24_S 7 -#define I2S_AIFFMTCFG_MEM_LEN_24_24BIT 0x00000080 -#define I2S_AIFFMTCFG_MEM_LEN_24_16BIT 0x00000000 +#define I2S_AIFFMTCFG_MEM_LEN_24 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_BITN 7 +#define I2S_AIFFMTCFG_MEM_LEN_24_M 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_S 7 +#define I2S_AIFFMTCFG_MEM_LEN_24_24BIT 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_16BIT 0x00000000 // Field: [6] SMPL_EDGE // @@ -262,12 +262,12 @@ // out on the negative edge. // NEG Data is sampled on the negative edge and clocked // out on the positive edge. -#define I2S_AIFFMTCFG_SMPL_EDGE 0x00000040 -#define I2S_AIFFMTCFG_SMPL_EDGE_BITN 6 -#define I2S_AIFFMTCFG_SMPL_EDGE_M 0x00000040 -#define I2S_AIFFMTCFG_SMPL_EDGE_S 6 -#define I2S_AIFFMTCFG_SMPL_EDGE_POS 0x00000040 -#define I2S_AIFFMTCFG_SMPL_EDGE_NEG 0x00000000 +#define I2S_AIFFMTCFG_SMPL_EDGE 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_BITN 6 +#define I2S_AIFFMTCFG_SMPL_EDGE_M 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_S 6 +#define I2S_AIFFMTCFG_SMPL_EDGE_POS 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_NEG 0x00000000 // Field: [5] DUAL_PHASE // @@ -275,10 +275,10 @@ // // 0: Single-phase: DSP format // 1: Dual-phase: I2S, LJF and RJF formats -#define I2S_AIFFMTCFG_DUAL_PHASE 0x00000020 -#define I2S_AIFFMTCFG_DUAL_PHASE_BITN 5 -#define I2S_AIFFMTCFG_DUAL_PHASE_M 0x00000020 -#define I2S_AIFFMTCFG_DUAL_PHASE_S 5 +#define I2S_AIFFMTCFG_DUAL_PHASE 0x00000020 +#define I2S_AIFFMTCFG_DUAL_PHASE_BITN 5 +#define I2S_AIFFMTCFG_DUAL_PHASE_M 0x00000020 +#define I2S_AIFFMTCFG_DUAL_PHASE_S 5 // Field: [4:0] WORD_LEN // @@ -289,9 +289,9 @@ // Values below 8 and above 24 give undefined behavior. Data written to memory // is always aligned to 16 or 24 bits as defined by MEM_LEN_24. Bit widths that // differ from this alignment will either be truncated or zero padded. -#define I2S_AIFFMTCFG_WORD_LEN_W 5 -#define I2S_AIFFMTCFG_WORD_LEN_M 0x0000001F -#define I2S_AIFFMTCFG_WORD_LEN_S 0 +#define I2S_AIFFMTCFG_WORD_LEN_W 5 +#define I2S_AIFFMTCFG_WORD_LEN_M 0x0000001F +#define I2S_AIFFMTCFG_WORD_LEN_S 0 //***************************************************************************** // @@ -318,9 +318,9 @@ // If all bits are zero, no input words will be stored to memory, and the // output data lines will be constant '0'. This can be utilized when PWM debug // output is desired without any actively used output pins. -#define I2S_AIFWMASK0_MASK_W 8 -#define I2S_AIFWMASK0_MASK_M 0x000000FF -#define I2S_AIFWMASK0_MASK_S 0 +#define I2S_AIFWMASK0_MASK_W 8 +#define I2S_AIFWMASK0_MASK_M 0x000000FF +#define I2S_AIFWMASK0_MASK_S 0 //***************************************************************************** // @@ -347,9 +347,9 @@ // If all bits are zero, no input words will be stored to memory, and the // output data lines will be constant '0'. This can be utilized when PWM debug // output is desired without any actively used output pins. -#define I2S_AIFWMASK1_MASK_W 8 -#define I2S_AIFWMASK1_MASK_M 0x000000FF -#define I2S_AIFWMASK1_MASK_S 0 +#define I2S_AIFWMASK1_MASK_W 8 +#define I2S_AIFWMASK1_MASK_M 0x000000FF +#define I2S_AIFWMASK1_MASK_S 0 //***************************************************************************** // @@ -367,9 +367,9 @@ // ... // 0xFFFE: Width of the pulse (number of BCLK cycles, here 65534). // 0xFFFF: Constant high -#define I2S_AIFPWMVALUE_PULSE_WIDTH_W 16 -#define I2S_AIFPWMVALUE_PULSE_WIDTH_M 0x0000FFFF -#define I2S_AIFPWMVALUE_PULSE_WIDTH_S 0 +#define I2S_AIFPWMVALUE_PULSE_WIDTH_W 16 +#define I2S_AIFPWMVALUE_PULSE_WIDTH_M 0x0000FFFF +#define I2S_AIFPWMVALUE_PULSE_WIDTH_S 0 //***************************************************************************** // @@ -391,9 +391,9 @@ // The next pointer must be written to this register while the DMA function // uses the previously written pointer. If not written in time, // IRQFLAGS.PTR_ERR will be raised and all input pins will be disabled. -#define I2S_AIFINPTRNEXT_PTR_W 32 -#define I2S_AIFINPTRNEXT_PTR_M 0xFFFFFFFF -#define I2S_AIFINPTRNEXT_PTR_S 0 +#define I2S_AIFINPTRNEXT_PTR_W 32 +#define I2S_AIFINPTRNEXT_PTR_M 0xFFFFFFFF +#define I2S_AIFINPTRNEXT_PTR_S 0 //***************************************************************************** // @@ -404,9 +404,9 @@ // // Value of the DMA input buffer pointer currently used by the DMA controller. // Incremented by 1 (byte) or 2 (word) for each AHB access. -#define I2S_AIFINPTR_PTR_W 32 -#define I2S_AIFINPTR_PTR_M 0xFFFFFFFF -#define I2S_AIFINPTR_PTR_S 0 +#define I2S_AIFINPTR_PTR_W 32 +#define I2S_AIFINPTR_PTR_M 0xFFFFFFFF +#define I2S_AIFINPTR_PTR_S 0 //***************************************************************************** // @@ -429,9 +429,9 @@ // The next pointer must be written to this register while the DMA function // uses the previously written pointer. If not written in time, // IRQFLAGS.PTR_ERR will be raised and all output pins will be disabled. -#define I2S_AIFOUTPTRNEXT_PTR_W 32 -#define I2S_AIFOUTPTRNEXT_PTR_M 0xFFFFFFFF -#define I2S_AIFOUTPTRNEXT_PTR_S 0 +#define I2S_AIFOUTPTRNEXT_PTR_W 32 +#define I2S_AIFOUTPTRNEXT_PTR_M 0xFFFFFFFF +#define I2S_AIFOUTPTRNEXT_PTR_S 0 //***************************************************************************** // @@ -442,9 +442,9 @@ // // Value of the DMA output buffer pointer currently used by the DMA controller // Incremented by 1 (byte) or 2 (word) for each AHB access. -#define I2S_AIFOUTPTR_PTR_W 32 -#define I2S_AIFOUTPTR_PTR_M 0xFFFFFFFF -#define I2S_AIFOUTPTR_PTR_S 0 +#define I2S_AIFOUTPTR_PTR_W 32 +#define I2S_AIFOUTPTR_PTR_M 0xFFFFFFFF +#define I2S_AIFOUTPTR_PTR_S 0 //***************************************************************************** // @@ -456,20 +456,20 @@ // Low until the output pins are ready to be started by the samplestamp // generator. When started (that is STMPOUTTRIG equals the WCLK counter) the // bit goes back low. -#define I2S_STMPCTL_OUT_RDY 0x00000004 -#define I2S_STMPCTL_OUT_RDY_BITN 2 -#define I2S_STMPCTL_OUT_RDY_M 0x00000004 -#define I2S_STMPCTL_OUT_RDY_S 2 +#define I2S_STMPCTL_OUT_RDY 0x00000004 +#define I2S_STMPCTL_OUT_RDY_BITN 2 +#define I2S_STMPCTL_OUT_RDY_M 0x00000004 +#define I2S_STMPCTL_OUT_RDY_S 2 // Field: [1] IN_RDY // // Low until the input pins are ready to be started by the samplestamp // generator. When started (that is STMPINTRIG equals the WCLK counter) the bit // goes back low. -#define I2S_STMPCTL_IN_RDY 0x00000002 -#define I2S_STMPCTL_IN_RDY_BITN 1 -#define I2S_STMPCTL_IN_RDY_M 0x00000002 -#define I2S_STMPCTL_IN_RDY_S 1 +#define I2S_STMPCTL_IN_RDY 0x00000002 +#define I2S_STMPCTL_IN_RDY_BITN 1 +#define I2S_STMPCTL_IN_RDY_M 0x00000002 +#define I2S_STMPCTL_IN_RDY_S 1 // Field: [0] STMP_EN // @@ -477,10 +477,10 @@ // enabled after it has been properly configured. // When cleared, all samplestamp generator counters and capture values are // cleared. -#define I2S_STMPCTL_STMP_EN 0x00000001 -#define I2S_STMPCTL_STMP_EN_BITN 0 -#define I2S_STMPCTL_STMP_EN_M 0x00000001 -#define I2S_STMPCTL_STMP_EN_S 0 +#define I2S_STMPCTL_STMP_EN 0x00000001 +#define I2S_STMPCTL_STMP_EN_BITN 0 +#define I2S_STMPCTL_STMP_EN_M 0x00000001 +#define I2S_STMPCTL_STMP_EN_S 0 //***************************************************************************** // @@ -498,9 +498,9 @@ // number of BCLK periods and clk periods. // Note: When calculating the fractional part of the sample stamp, STMPXPER may // be less than this bit field. -#define I2S_STMPXCNTCAPT0_CAPT_VALUE_W 16 -#define I2S_STMPXCNTCAPT0_CAPT_VALUE_M 0x0000FFFF -#define I2S_STMPXCNTCAPT0_CAPT_VALUE_S 0 +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_W 16 +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_S 0 //***************************************************************************** // @@ -513,9 +513,9 @@ // the next value of the XOSC counter at the positive WCLK edge, had it not // been reset to 0). // The value is cleared when STMPCTL.STMP_EN = 0. -#define I2S_STMPXPER_VALUE_W 16 -#define I2S_STMPXPER_VALUE_M 0x0000FFFF -#define I2S_STMPXPER_VALUE_S 0 +#define I2S_STMPXPER_VALUE_W 16 +#define I2S_STMPXPER_VALUE_M 0x0000FFFF +#define I2S_STMPXPER_VALUE_S 0 //***************************************************************************** // @@ -530,9 +530,9 @@ // samplestamp generator was enabled (not taking modification through // STMPWADD/STMPWSET into account). // The value is cleared when STMPCTL.STMP_EN = 0. -#define I2S_STMPWCNTCAPT0_CAPT_VALUE_W 16 -#define I2S_STMPWCNTCAPT0_CAPT_VALUE_M 0x0000FFFF -#define I2S_STMPWCNTCAPT0_CAPT_VALUE_S 0 +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_W 16 +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_S 0 //***************************************************************************** // @@ -545,9 +545,9 @@ // found for the size of the sample buffer. This is thus a modulo value for the // WCLK counter. This number must correspond to the size of the sample buffer // used by the system (that is the index of the last sample plus 1). -#define I2S_STMPWPER_VALUE_W 16 -#define I2S_STMPWPER_VALUE_M 0x0000FFFF -#define I2S_STMPWPER_VALUE_S 0 +#define I2S_STMPWPER_VALUE_W 16 +#define I2S_STMPWPER_VALUE_M 0x0000FFFF +#define I2S_STMPWPER_VALUE_S 0 //***************************************************************************** // @@ -569,9 +569,9 @@ // // Note: To avoid false triggers, this bit field should be set higher than // STMPWPER.VALUE. -#define I2S_STMPINTRIG_IN_START_WCNT_W 16 -#define I2S_STMPINTRIG_IN_START_WCNT_M 0x0000FFFF -#define I2S_STMPINTRIG_IN_START_WCNT_S 0 +#define I2S_STMPINTRIG_IN_START_WCNT_W 16 +#define I2S_STMPINTRIG_IN_START_WCNT_M 0x0000FFFF +#define I2S_STMPINTRIG_IN_START_WCNT_S 0 //***************************************************************************** // @@ -598,9 +598,9 @@ // // Note: To avoid false triggers, this bit field should be set higher than // STMPWPER.VALUE. -#define I2S_STMPOUTTRIG_OUT_START_WCNT_W 16 -#define I2S_STMPOUTTRIG_OUT_START_WCNT_M 0x0000FFFF -#define I2S_STMPOUTTRIG_OUT_START_WCNT_S 0 +#define I2S_STMPOUTTRIG_OUT_START_WCNT_W 16 +#define I2S_STMPOUTTRIG_OUT_START_WCNT_M 0x0000FFFF +#define I2S_STMPOUTTRIG_OUT_START_WCNT_S 0 //***************************************************************************** // @@ -611,9 +611,9 @@ // // WCLK counter modification: Sets the running WCLK counter equal to the // written value. -#define I2S_STMPWSET_VALUE_W 16 -#define I2S_STMPWSET_VALUE_M 0x0000FFFF -#define I2S_STMPWSET_VALUE_S 0 +#define I2S_STMPWSET_VALUE_W 16 +#define I2S_STMPWSET_VALUE_M 0x0000FFFF +#define I2S_STMPWSET_VALUE_S 0 //***************************************************************************** // @@ -627,9 +627,9 @@ // operation, this will be taken into account. // To add a negative value, write "STMPWPER.VALUE - value". // -#define I2S_STMPWADD_VALUE_INC_W 16 -#define I2S_STMPWADD_VALUE_INC_M 0x0000FFFF -#define I2S_STMPWADD_VALUE_INC_S 0 +#define I2S_STMPWADD_VALUE_INC_W 16 +#define I2S_STMPWADD_VALUE_INC_M 0x0000FFFF +#define I2S_STMPWADD_VALUE_INC_S 0 //***************************************************************************** // @@ -644,9 +644,9 @@ // value written. // The minimum value can be used to detect extra WCLK pulses (this registers // value will be significantly smaller than STMPXPER.VALUE). -#define I2S_STMPXPERMIN_VALUE_W 16 -#define I2S_STMPXPERMIN_VALUE_M 0x0000FFFF -#define I2S_STMPXPERMIN_VALUE_S 0 +#define I2S_STMPXPERMIN_VALUE_W 16 +#define I2S_STMPXPERMIN_VALUE_M 0x0000FFFF +#define I2S_STMPXPERMIN_VALUE_S 0 //***************************************************************************** // @@ -656,9 +656,9 @@ // Field: [15:0] CURR_VALUE // // Current value of the WCLK counter -#define I2S_STMPWCNT_CURR_VALUE_W 16 -#define I2S_STMPWCNT_CURR_VALUE_M 0x0000FFFF -#define I2S_STMPWCNT_CURR_VALUE_S 0 +#define I2S_STMPWCNT_CURR_VALUE_W 16 +#define I2S_STMPWCNT_CURR_VALUE_M 0x0000FFFF +#define I2S_STMPWCNT_CURR_VALUE_S 0 //***************************************************************************** // @@ -668,9 +668,9 @@ // Field: [15:0] CURR_VALUE // // Current value of the XOSC counter, latched when reading STMPWCNT. -#define I2S_STMPXCNT_CURR_VALUE_W 16 -#define I2S_STMPXCNT_CURR_VALUE_M 0x0000FFFF -#define I2S_STMPXCNT_CURR_VALUE_S 0 +#define I2S_STMPXCNT_CURR_VALUE_W 16 +#define I2S_STMPXCNT_CURR_VALUE_M 0x0000FFFF +#define I2S_STMPXCNT_CURR_VALUE_S 0 //***************************************************************************** // @@ -680,9 +680,9 @@ // Field: [15:0] CAPT_VALUE // // Internal. Only to be used through TI provided API. -#define I2S_STMPXCNTCAPT1_CAPT_VALUE_W 16 -#define I2S_STMPXCNTCAPT1_CAPT_VALUE_M 0x0000FFFF -#define I2S_STMPXCNTCAPT1_CAPT_VALUE_S 0 +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_W 16 +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_S 0 //***************************************************************************** // @@ -692,9 +692,9 @@ // Field: [15:0] CAPT_VALUE // // Internal. Only to be used through TI provided API. -#define I2S_STMPWCNTCAPT1_CAPT_VALUE_W 16 -#define I2S_STMPWCNTCAPT1_CAPT_VALUE_M 0x0000FFFF -#define I2S_STMPWCNTCAPT1_CAPT_VALUE_S 0 +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_W 16 +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_S 0 //***************************************************************************** // @@ -707,10 +707,10 @@ // // 0: Disable // 1: Enable -#define I2S_IRQMASK_AIF_DMA_IN 0x00000020 -#define I2S_IRQMASK_AIF_DMA_IN_BITN 5 -#define I2S_IRQMASK_AIF_DMA_IN_M 0x00000020 -#define I2S_IRQMASK_AIF_DMA_IN_S 5 +#define I2S_IRQMASK_AIF_DMA_IN 0x00000020 +#define I2S_IRQMASK_AIF_DMA_IN_BITN 5 +#define I2S_IRQMASK_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQMASK_AIF_DMA_IN_S 5 // Field: [4] AIF_DMA_OUT // @@ -718,10 +718,10 @@ // // 0: Disable // 1: Enable -#define I2S_IRQMASK_AIF_DMA_OUT 0x00000010 -#define I2S_IRQMASK_AIF_DMA_OUT_BITN 4 -#define I2S_IRQMASK_AIF_DMA_OUT_M 0x00000010 -#define I2S_IRQMASK_AIF_DMA_OUT_S 4 +#define I2S_IRQMASK_AIF_DMA_OUT 0x00000010 +#define I2S_IRQMASK_AIF_DMA_OUT_BITN 4 +#define I2S_IRQMASK_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQMASK_AIF_DMA_OUT_S 4 // Field: [3] WCLK_TIMEOUT // @@ -729,10 +729,10 @@ // // 0: Disable // 1: Enable -#define I2S_IRQMASK_WCLK_TIMEOUT 0x00000008 -#define I2S_IRQMASK_WCLK_TIMEOUT_BITN 3 -#define I2S_IRQMASK_WCLK_TIMEOUT_M 0x00000008 -#define I2S_IRQMASK_WCLK_TIMEOUT_S 3 +#define I2S_IRQMASK_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQMASK_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQMASK_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQMASK_WCLK_TIMEOUT_S 3 // Field: [2] BUS_ERR // @@ -740,10 +740,10 @@ // // 0: Disable // 1: Enable -#define I2S_IRQMASK_BUS_ERR 0x00000004 -#define I2S_IRQMASK_BUS_ERR_BITN 2 -#define I2S_IRQMASK_BUS_ERR_M 0x00000004 -#define I2S_IRQMASK_BUS_ERR_S 2 +#define I2S_IRQMASK_BUS_ERR 0x00000004 +#define I2S_IRQMASK_BUS_ERR_BITN 2 +#define I2S_IRQMASK_BUS_ERR_M 0x00000004 +#define I2S_IRQMASK_BUS_ERR_S 2 // Field: [1] WCLK_ERR // @@ -751,10 +751,10 @@ // // 0: Disable // 1: Enable -#define I2S_IRQMASK_WCLK_ERR 0x00000002 -#define I2S_IRQMASK_WCLK_ERR_BITN 1 -#define I2S_IRQMASK_WCLK_ERR_M 0x00000002 -#define I2S_IRQMASK_WCLK_ERR_S 1 +#define I2S_IRQMASK_WCLK_ERR 0x00000002 +#define I2S_IRQMASK_WCLK_ERR_BITN 1 +#define I2S_IRQMASK_WCLK_ERR_M 0x00000002 +#define I2S_IRQMASK_WCLK_ERR_S 1 // Field: [0] PTR_ERR // @@ -762,10 +762,10 @@ // // 0: Disable // 1: Enable -#define I2S_IRQMASK_PTR_ERR 0x00000001 -#define I2S_IRQMASK_PTR_ERR_BITN 0 -#define I2S_IRQMASK_PTR_ERR_M 0x00000001 -#define I2S_IRQMASK_PTR_ERR_S 0 +#define I2S_IRQMASK_PTR_ERR 0x00000001 +#define I2S_IRQMASK_PTR_ERR_BITN 0 +#define I2S_IRQMASK_PTR_ERR_M 0x00000001 +#define I2S_IRQMASK_PTR_ERR_S 0 //***************************************************************************** // @@ -777,20 +777,20 @@ // Set when condition for this bit field event occurs (auto cleared when input // pointer is updated - AIFINPTRNEXT), see description of AIFINPTRNEXT register // for details. -#define I2S_IRQFLAGS_AIF_DMA_IN 0x00000020 -#define I2S_IRQFLAGS_AIF_DMA_IN_BITN 5 -#define I2S_IRQFLAGS_AIF_DMA_IN_M 0x00000020 -#define I2S_IRQFLAGS_AIF_DMA_IN_S 5 +#define I2S_IRQFLAGS_AIF_DMA_IN 0x00000020 +#define I2S_IRQFLAGS_AIF_DMA_IN_BITN 5 +#define I2S_IRQFLAGS_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQFLAGS_AIF_DMA_IN_S 5 // Field: [4] AIF_DMA_OUT // // Set when condition for this bit field event occurs (auto cleared when output // pointer is updated - AIFOUTPTRNEXT), see description of AIFOUTPTRNEXT // register for details -#define I2S_IRQFLAGS_AIF_DMA_OUT 0x00000010 -#define I2S_IRQFLAGS_AIF_DMA_OUT_BITN 4 -#define I2S_IRQFLAGS_AIF_DMA_OUT_M 0x00000010 -#define I2S_IRQFLAGS_AIF_DMA_OUT_S 4 +#define I2S_IRQFLAGS_AIF_DMA_OUT 0x00000010 +#define I2S_IRQFLAGS_AIF_DMA_OUT_BITN 4 +#define I2S_IRQFLAGS_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQFLAGS_AIF_DMA_OUT_S 4 // Field: [3] WCLK_TIMEOUT // @@ -800,10 +800,10 @@ // // The bit is sticky and may only be cleared by software (by writing '1' to // IRQCLR.WCLK_TIMEOUT). -#define I2S_IRQFLAGS_WCLK_TIMEOUT 0x00000008 -#define I2S_IRQFLAGS_WCLK_TIMEOUT_BITN 3 -#define I2S_IRQFLAGS_WCLK_TIMEOUT_M 0x00000008 -#define I2S_IRQFLAGS_WCLK_TIMEOUT_S 3 +#define I2S_IRQFLAGS_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_S 3 // Field: [2] BUS_ERR // @@ -815,10 +815,10 @@ // // Note that DMA initiated transactions to illegal addresses will not trigger // an interrupt. The response to such transactions is undefined. -#define I2S_IRQFLAGS_BUS_ERR 0x00000004 -#define I2S_IRQFLAGS_BUS_ERR_BITN 2 -#define I2S_IRQFLAGS_BUS_ERR_M 0x00000004 -#define I2S_IRQFLAGS_BUS_ERR_S 2 +#define I2S_IRQFLAGS_BUS_ERR 0x00000004 +#define I2S_IRQFLAGS_BUS_ERR_BITN 2 +#define I2S_IRQFLAGS_BUS_ERR_M 0x00000004 +#define I2S_IRQFLAGS_BUS_ERR_S 2 // Field: [1] WCLK_ERR // @@ -832,10 +832,10 @@ // This error requires a complete restart since word synchronization has been // lost. The bit is sticky and may only be cleared by software (by writing '1' // to IRQCLR.WCLK_ERR). -#define I2S_IRQFLAGS_WCLK_ERR 0x00000002 -#define I2S_IRQFLAGS_WCLK_ERR_BITN 1 -#define I2S_IRQFLAGS_WCLK_ERR_M 0x00000002 -#define I2S_IRQFLAGS_WCLK_ERR_S 1 +#define I2S_IRQFLAGS_WCLK_ERR 0x00000002 +#define I2S_IRQFLAGS_WCLK_ERR_BITN 1 +#define I2S_IRQFLAGS_WCLK_ERR_M 0x00000002 +#define I2S_IRQFLAGS_WCLK_ERR_S 1 // Field: [0] PTR_ERR // @@ -844,10 +844,10 @@ // This error requires a complete restart since word synchronization has been // lost. The bit is sticky and may only be cleared by software (by writing '1' // to IRQCLR.PTR_ERR). -#define I2S_IRQFLAGS_PTR_ERR 0x00000001 -#define I2S_IRQFLAGS_PTR_ERR_BITN 0 -#define I2S_IRQFLAGS_PTR_ERR_M 0x00000001 -#define I2S_IRQFLAGS_PTR_ERR_S 0 +#define I2S_IRQFLAGS_PTR_ERR 0x00000001 +#define I2S_IRQFLAGS_PTR_ERR_BITN 0 +#define I2S_IRQFLAGS_PTR_ERR_M 0x00000001 +#define I2S_IRQFLAGS_PTR_ERR_S 0 //***************************************************************************** // @@ -858,51 +858,51 @@ // // 1: Sets the interrupt of IRQFLAGS.AIF_DMA_IN (unless a auto clear criteria // was given at the same time, in which the set will be ignored) -#define I2S_IRQSET_AIF_DMA_IN 0x00000020 -#define I2S_IRQSET_AIF_DMA_IN_BITN 5 -#define I2S_IRQSET_AIF_DMA_IN_M 0x00000020 -#define I2S_IRQSET_AIF_DMA_IN_S 5 +#define I2S_IRQSET_AIF_DMA_IN 0x00000020 +#define I2S_IRQSET_AIF_DMA_IN_BITN 5 +#define I2S_IRQSET_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQSET_AIF_DMA_IN_S 5 // Field: [4] AIF_DMA_OUT // // 1: Sets the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a auto clear criteria // was given at the same time, in which the set will be ignored) -#define I2S_IRQSET_AIF_DMA_OUT 0x00000010 -#define I2S_IRQSET_AIF_DMA_OUT_BITN 4 -#define I2S_IRQSET_AIF_DMA_OUT_M 0x00000010 -#define I2S_IRQSET_AIF_DMA_OUT_S 4 +#define I2S_IRQSET_AIF_DMA_OUT 0x00000010 +#define I2S_IRQSET_AIF_DMA_OUT_BITN 4 +#define I2S_IRQSET_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQSET_AIF_DMA_OUT_S 4 // Field: [3] WCLK_TIMEOUT // // 1: Sets the interrupt of IRQFLAGS.WCLK_TIMEOUT -#define I2S_IRQSET_WCLK_TIMEOUT 0x00000008 -#define I2S_IRQSET_WCLK_TIMEOUT_BITN 3 -#define I2S_IRQSET_WCLK_TIMEOUT_M 0x00000008 -#define I2S_IRQSET_WCLK_TIMEOUT_S 3 +#define I2S_IRQSET_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQSET_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQSET_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQSET_WCLK_TIMEOUT_S 3 // Field: [2] BUS_ERR // // 1: Sets the interrupt of IRQFLAGS.BUS_ERR -#define I2S_IRQSET_BUS_ERR 0x00000004 -#define I2S_IRQSET_BUS_ERR_BITN 2 -#define I2S_IRQSET_BUS_ERR_M 0x00000004 -#define I2S_IRQSET_BUS_ERR_S 2 +#define I2S_IRQSET_BUS_ERR 0x00000004 +#define I2S_IRQSET_BUS_ERR_BITN 2 +#define I2S_IRQSET_BUS_ERR_M 0x00000004 +#define I2S_IRQSET_BUS_ERR_S 2 // Field: [1] WCLK_ERR // // 1: Sets the interrupt of IRQFLAGS.WCLK_ERR -#define I2S_IRQSET_WCLK_ERR 0x00000002 -#define I2S_IRQSET_WCLK_ERR_BITN 1 -#define I2S_IRQSET_WCLK_ERR_M 0x00000002 -#define I2S_IRQSET_WCLK_ERR_S 1 +#define I2S_IRQSET_WCLK_ERR 0x00000002 +#define I2S_IRQSET_WCLK_ERR_BITN 1 +#define I2S_IRQSET_WCLK_ERR_M 0x00000002 +#define I2S_IRQSET_WCLK_ERR_S 1 // Field: [0] PTR_ERR // // 1: Sets the interrupt of IRQFLAGS.PTR_ERR -#define I2S_IRQSET_PTR_ERR 0x00000001 -#define I2S_IRQSET_PTR_ERR_BITN 0 -#define I2S_IRQSET_PTR_ERR_M 0x00000001 -#define I2S_IRQSET_PTR_ERR_S 0 +#define I2S_IRQSET_PTR_ERR 0x00000001 +#define I2S_IRQSET_PTR_ERR_BITN 0 +#define I2S_IRQSET_PTR_ERR_M 0x00000001 +#define I2S_IRQSET_PTR_ERR_S 0 //***************************************************************************** // @@ -913,55 +913,54 @@ // // 1: Clears the interrupt of IRQFLAGS.AIF_DMA_IN (unless a set criteria was // given at the same time in which the clear will be ignored) -#define I2S_IRQCLR_AIF_DMA_IN 0x00000020 -#define I2S_IRQCLR_AIF_DMA_IN_BITN 5 -#define I2S_IRQCLR_AIF_DMA_IN_M 0x00000020 -#define I2S_IRQCLR_AIF_DMA_IN_S 5 +#define I2S_IRQCLR_AIF_DMA_IN 0x00000020 +#define I2S_IRQCLR_AIF_DMA_IN_BITN 5 +#define I2S_IRQCLR_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQCLR_AIF_DMA_IN_S 5 // Field: [4] AIF_DMA_OUT // // 1: Clears the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a set criteria was // given at the same time in which the clear will be ignored) -#define I2S_IRQCLR_AIF_DMA_OUT 0x00000010 -#define I2S_IRQCLR_AIF_DMA_OUT_BITN 4 -#define I2S_IRQCLR_AIF_DMA_OUT_M 0x00000010 -#define I2S_IRQCLR_AIF_DMA_OUT_S 4 +#define I2S_IRQCLR_AIF_DMA_OUT 0x00000010 +#define I2S_IRQCLR_AIF_DMA_OUT_BITN 4 +#define I2S_IRQCLR_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQCLR_AIF_DMA_OUT_S 4 // Field: [3] WCLK_TIMEOUT // // 1: Clears the interrupt of IRQFLAGS.WCLK_TIMEOUT (unless a set criteria was // given at the same time in which the clear will be ignored) -#define I2S_IRQCLR_WCLK_TIMEOUT 0x00000008 -#define I2S_IRQCLR_WCLK_TIMEOUT_BITN 3 -#define I2S_IRQCLR_WCLK_TIMEOUT_M 0x00000008 -#define I2S_IRQCLR_WCLK_TIMEOUT_S 3 +#define I2S_IRQCLR_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQCLR_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQCLR_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQCLR_WCLK_TIMEOUT_S 3 // Field: [2] BUS_ERR // // 1: Clears the interrupt of IRQFLAGS.BUS_ERR (unless a set criteria was given // at the same time in which the clear will be ignored) -#define I2S_IRQCLR_BUS_ERR 0x00000004 -#define I2S_IRQCLR_BUS_ERR_BITN 2 -#define I2S_IRQCLR_BUS_ERR_M 0x00000004 -#define I2S_IRQCLR_BUS_ERR_S 2 +#define I2S_IRQCLR_BUS_ERR 0x00000004 +#define I2S_IRQCLR_BUS_ERR_BITN 2 +#define I2S_IRQCLR_BUS_ERR_M 0x00000004 +#define I2S_IRQCLR_BUS_ERR_S 2 // Field: [1] WCLK_ERR // // 1: Clears the interrupt of IRQFLAGS.WCLK_ERR (unless a set criteria was // given at the same time in which the clear will be ignored) -#define I2S_IRQCLR_WCLK_ERR 0x00000002 -#define I2S_IRQCLR_WCLK_ERR_BITN 1 -#define I2S_IRQCLR_WCLK_ERR_M 0x00000002 -#define I2S_IRQCLR_WCLK_ERR_S 1 +#define I2S_IRQCLR_WCLK_ERR 0x00000002 +#define I2S_IRQCLR_WCLK_ERR_BITN 1 +#define I2S_IRQCLR_WCLK_ERR_M 0x00000002 +#define I2S_IRQCLR_WCLK_ERR_S 1 // Field: [0] PTR_ERR // // 1: Clears the interrupt of IRQFLAGS.PTR_ERR (unless a set criteria was given // at the same time in which the clear will be ignored) -#define I2S_IRQCLR_PTR_ERR 0x00000001 -#define I2S_IRQCLR_PTR_ERR_BITN 0 -#define I2S_IRQCLR_PTR_ERR_M 0x00000001 -#define I2S_IRQCLR_PTR_ERR_S 0 - +#define I2S_IRQCLR_PTR_ERR 0x00000001 +#define I2S_IRQCLR_PTR_ERR_BITN 0 +#define I2S_IRQCLR_PTR_ERR_M 0x00000001 +#define I2S_IRQCLR_PTR_ERR_S 0 #endif // __I2S__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ints.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ints.h index 8fc6fdd..e494299 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ints.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ints.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_ints_h -* Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) -* Revision: 48904 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_ints_h + * Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) + * Revision: 48904 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_INTS_H__ #define __HW_INTS_H__ @@ -42,64 +42,63 @@ // The following are defines for the interrupt assignments. // //***************************************************************************** -#define INT_NMI_FAULT 2 // NMI Fault -#define INT_HARD_FAULT 3 // Hard Fault -#define INT_MEMMANAGE_FAULT 4 // Memory Management (MemManage) +#define INT_NMI_FAULT 2 // NMI Fault +#define INT_HARD_FAULT 3 // Hard Fault +#define INT_MEMMANAGE_FAULT 4 // Memory Management (MemManage) // Fault -#define INT_BUS_FAULT 5 // Bus Fault -#define INT_USAGE_FAULT 6 // Usage Fault -#define INT_SVCALL 11 // Supervisor Call (SVCall) -#define INT_DEBUG 12 // Debug Monitor -#define INT_PENDSV 14 // Pending Service Call (PendSV) -#define INT_SYSTICK 15 // SysTick Interrupt from the +#define INT_BUS_FAULT 5 // Bus Fault +#define INT_USAGE_FAULT 6 // Usage Fault +#define INT_SVCALL 11 // Supervisor Call (SVCall) +#define INT_DEBUG 12 // Debug Monitor +#define INT_PENDSV 14 // Pending Service Call (PendSV) +#define INT_SYSTICK 15 // SysTick Interrupt from the // System Timer in NVIC. -#define INT_AON_GPIO_EDGE 16 // Edge detect event from IOC -#define INT_I2C_IRQ 17 // Interrupt event from I2C -#define INT_RFC_CPE_1 18 // Combined Interrupt for CPE +#define INT_AON_GPIO_EDGE 16 // Edge detect event from IOC +#define INT_I2C_IRQ 17 // Interrupt event from I2C +#define INT_RFC_CPE_1 18 // Combined Interrupt for CPE // Generated events -#define INT_AON_RTC_COMB 20 // Event from AON_RTC -#define INT_UART0_COMB 21 // UART0 combined interrupt -#define INT_AUX_SWEV0 22 // AUX software event 0 -#define INT_SSI0_COMB 23 // SSI0 combined interrupt -#define INT_SSI1_COMB 24 // SSI1 combined interrupt -#define INT_RFC_CPE_0 25 // Combined Interrupt for CPE +#define INT_AON_RTC_COMB 20 // Event from AON_RTC +#define INT_UART0_COMB 21 // UART0 combined interrupt +#define INT_AUX_SWEV0 22 // AUX software event 0 +#define INT_SSI0_COMB 23 // SSI0 combined interrupt +#define INT_SSI1_COMB 24 // SSI1 combined interrupt +#define INT_RFC_CPE_0 25 // Combined Interrupt for CPE // Generated events -#define INT_RFC_HW_COMB 26 // Combined RFC hardware interrupt -#define INT_RFC_CMD_ACK 27 // RFC Doorbell Command +#define INT_RFC_HW_COMB 26 // Combined RFC hardware interrupt +#define INT_RFC_CMD_ACK 27 // RFC Doorbell Command // Acknowledgement Interrupt -#define INT_I2S_IRQ 28 // Interrupt event from I2S -#define INT_AUX_SWEV1 29 // AUX software event 1 -#define INT_WDT_IRQ 30 // Watchdog interrupt event -#define INT_GPT0A 31 // GPT0A interrupt event -#define INT_GPT0B 32 // GPT0B interrupt event -#define INT_GPT1A 33 // GPT1A interrupt event -#define INT_GPT1B 34 // GPT1B interrupt event -#define INT_GPT2A 35 // GPT2A interrupt event -#define INT_GPT2B 36 // GPT2B interrupt event -#define INT_GPT3A 37 // GPT3A interrupt event -#define INT_GPT3B 38 // GPT3B interrupt event -#define INT_CRYPTO_RESULT_AVAIL_IRQ 39 // CRYPTO result available interupt +#define INT_I2S_IRQ 28 // Interrupt event from I2S +#define INT_AUX_SWEV1 29 // AUX software event 1 +#define INT_WDT_IRQ 30 // Watchdog interrupt event +#define INT_GPT0A 31 // GPT0A interrupt event +#define INT_GPT0B 32 // GPT0B interrupt event +#define INT_GPT1A 33 // GPT1A interrupt event +#define INT_GPT1B 34 // GPT1B interrupt event +#define INT_GPT2A 35 // GPT2A interrupt event +#define INT_GPT2B 36 // GPT2B interrupt event +#define INT_GPT3A 37 // GPT3A interrupt event +#define INT_GPT3B 38 // GPT3B interrupt event +#define INT_CRYPTO_RESULT_AVAIL_IRQ 39 // CRYPTO result available interupt // event -#define INT_DMA_DONE_COMB 40 // Combined DMA done -#define INT_DMA_ERR 41 // DMA bus error -#define INT_FLASH 42 // FLASH controller error event -#define INT_SWEV0 43 // Software event 0 -#define INT_AUX_COMB 44 // AUX combined event -#define INT_AON_PROG0 45 // AON programmable event 0 -#define INT_PROG0 46 // Programmable Interrupt 0 -#define INT_AUX_COMPA 47 // AUX Compare A event -#define INT_AUX_ADC_IRQ 48 // AUX ADC interrupt event -#define INT_TRNG_IRQ 49 // TRNG Interrupt event +#define INT_DMA_DONE_COMB 40 // Combined DMA done +#define INT_DMA_ERR 41 // DMA bus error +#define INT_FLASH 42 // FLASH controller error event +#define INT_SWEV0 43 // Software event 0 +#define INT_AUX_COMB 44 // AUX combined event +#define INT_AON_PROG0 45 // AON programmable event 0 +#define INT_PROG0 46 // Programmable Interrupt 0 +#define INT_AUX_COMPA 47 // AUX Compare A event +#define INT_AUX_ADC_IRQ 48 // AUX ADC interrupt event +#define INT_TRNG_IRQ 49 // TRNG Interrupt event //***************************************************************************** // // The following are defines for number of interrupts and priority levels. // //***************************************************************************** -#define NUM_INTERRUPTS 50 // Number of interrupts -#define NUM_PRIORITY_BITS 3 // Number of Priority bits -#define NUM_PRIORITY 8 // Number of priority levels - +#define NUM_INTERRUPTS 50 // Number of interrupts +#define NUM_PRIORITY_BITS 3 // Number of Priority bits +#define NUM_PRIORITY 8 // Number of priority levels //***************************************************************************** // @@ -107,7 +106,7 @@ // //***************************************************************************** -#define INT_AON_AUX_SWEV0 INT_AUX_SWEV0 -#define INT_AON_AUX_SWEV1 INT_AUX_SWEV1 +#define INT_AON_AUX_SWEV0 INT_AUX_SWEV0 +#define INT_AON_AUX_SWEV1 INT_AUX_SWEV1 #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ioc.h index 16a800a..edf2a14 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ioc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ioc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_ioc_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_ioc_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_IOC_H__ #define __HW_IOC_H__ @@ -44,100 +44,100 @@ // //***************************************************************************** // Configuration of DIO0 -#define IOC_O_IOCFG0 0x00000000 +#define IOC_O_IOCFG0 0x00000000 // Configuration of DIO1 -#define IOC_O_IOCFG1 0x00000004 +#define IOC_O_IOCFG1 0x00000004 // Configuration of DIO2 -#define IOC_O_IOCFG2 0x00000008 +#define IOC_O_IOCFG2 0x00000008 // Configuration of DIO3 -#define IOC_O_IOCFG3 0x0000000C +#define IOC_O_IOCFG3 0x0000000C // Configuration of DIO4 -#define IOC_O_IOCFG4 0x00000010 +#define IOC_O_IOCFG4 0x00000010 // Configuration of DIO5 -#define IOC_O_IOCFG5 0x00000014 +#define IOC_O_IOCFG5 0x00000014 // Configuration of DIO6 -#define IOC_O_IOCFG6 0x00000018 +#define IOC_O_IOCFG6 0x00000018 // Configuration of DIO7 -#define IOC_O_IOCFG7 0x0000001C +#define IOC_O_IOCFG7 0x0000001C // Configuration of DIO8 -#define IOC_O_IOCFG8 0x00000020 +#define IOC_O_IOCFG8 0x00000020 // Configuration of DIO9 -#define IOC_O_IOCFG9 0x00000024 +#define IOC_O_IOCFG9 0x00000024 // Configuration of DIO10 -#define IOC_O_IOCFG10 0x00000028 +#define IOC_O_IOCFG10 0x00000028 // Configuration of DIO11 -#define IOC_O_IOCFG11 0x0000002C +#define IOC_O_IOCFG11 0x0000002C // Configuration of DIO12 -#define IOC_O_IOCFG12 0x00000030 +#define IOC_O_IOCFG12 0x00000030 // Configuration of DIO13 -#define IOC_O_IOCFG13 0x00000034 +#define IOC_O_IOCFG13 0x00000034 // Configuration of DIO14 -#define IOC_O_IOCFG14 0x00000038 +#define IOC_O_IOCFG14 0x00000038 // Configuration of DIO15 -#define IOC_O_IOCFG15 0x0000003C +#define IOC_O_IOCFG15 0x0000003C // Configuration of DIO16 -#define IOC_O_IOCFG16 0x00000040 +#define IOC_O_IOCFG16 0x00000040 // Configuration of DIO17 -#define IOC_O_IOCFG17 0x00000044 +#define IOC_O_IOCFG17 0x00000044 // Configuration of DIO18 -#define IOC_O_IOCFG18 0x00000048 +#define IOC_O_IOCFG18 0x00000048 // Configuration of DIO19 -#define IOC_O_IOCFG19 0x0000004C +#define IOC_O_IOCFG19 0x0000004C // Configuration of DIO20 -#define IOC_O_IOCFG20 0x00000050 +#define IOC_O_IOCFG20 0x00000050 // Configuration of DIO21 -#define IOC_O_IOCFG21 0x00000054 +#define IOC_O_IOCFG21 0x00000054 // Configuration of DIO22 -#define IOC_O_IOCFG22 0x00000058 +#define IOC_O_IOCFG22 0x00000058 // Configuration of DIO23 -#define IOC_O_IOCFG23 0x0000005C +#define IOC_O_IOCFG23 0x0000005C // Configuration of DIO24 -#define IOC_O_IOCFG24 0x00000060 +#define IOC_O_IOCFG24 0x00000060 // Configuration of DIO25 -#define IOC_O_IOCFG25 0x00000064 +#define IOC_O_IOCFG25 0x00000064 // Configuration of DIO26 -#define IOC_O_IOCFG26 0x00000068 +#define IOC_O_IOCFG26 0x00000068 // Configuration of DIO27 -#define IOC_O_IOCFG27 0x0000006C +#define IOC_O_IOCFG27 0x0000006C // Configuration of DIO28 -#define IOC_O_IOCFG28 0x00000070 +#define IOC_O_IOCFG28 0x00000070 // Configuration of DIO29 -#define IOC_O_IOCFG29 0x00000074 +#define IOC_O_IOCFG29 0x00000074 // Configuration of DIO30 -#define IOC_O_IOCFG30 0x00000078 +#define IOC_O_IOCFG30 0x00000078 // Configuration of DIO31 -#define IOC_O_IOCFG31 0x0000007C +#define IOC_O_IOCFG31 0x0000007C //***************************************************************************** // @@ -148,10 +148,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG0_HYST_EN 0x40000000 -#define IOC_IOCFG0_HYST_EN_BITN 30 -#define IOC_IOCFG0_HYST_EN_M 0x40000000 -#define IOC_IOCFG0_HYST_EN_S 30 +#define IOC_IOCFG0_HYST_EN 0x40000000 +#define IOC_IOCFG0_HYST_EN_BITN 30 +#define IOC_IOCFG0_HYST_EN_M 0x40000000 +#define IOC_IOCFG0_HYST_EN_S 30 // Field: [29] IE // @@ -160,10 +160,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG0_IE 0x20000000 -#define IOC_IOCFG0_IE_BITN 29 -#define IOC_IOCFG0_IE_M 0x20000000 -#define IOC_IOCFG0_IE_S 29 +#define IOC_IOCFG0_IE 0x20000000 +#define IOC_IOCFG0_IE_BITN 29 +#define IOC_IOCFG0_IE_M 0x20000000 +#define IOC_IOCFG0_IE_S 29 // Field: [28:27] WU_CFG // @@ -185,9 +185,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG0_WU_CFG_W 2 -#define IOC_IOCFG0_WU_CFG_M 0x18000000 -#define IOC_IOCFG0_WU_CFG_S 27 +#define IOC_IOCFG0_WU_CFG_W 2 +#define IOC_IOCFG0_WU_CFG_M 0x18000000 +#define IOC_IOCFG0_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -208,25 +208,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG0_IOMODE_W 3 -#define IOC_IOCFG0_IOMODE_M 0x07000000 -#define IOC_IOCFG0_IOMODE_S 24 -#define IOC_IOCFG0_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG0_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG0_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG0_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG0_IOMODE_INV 0x01000000 -#define IOC_IOCFG0_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG0_IOMODE_W 3 +#define IOC_IOCFG0_IOMODE_M 0x07000000 +#define IOC_IOCFG0_IOMODE_S 24 +#define IOC_IOCFG0_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG0_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG0_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG0_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG0_IOMODE_INV 0x01000000 +#define IOC_IOCFG0_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG0_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG0_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG0_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG0_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG0_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG0_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG0_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG0_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -236,13 +236,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG0_EDGE_DET_W 2 -#define IOC_IOCFG0_EDGE_DET_M 0x00030000 -#define IOC_IOCFG0_EDGE_DET_S 16 -#define IOC_IOCFG0_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG0_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG0_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG0_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG0_EDGE_DET_W 2 +#define IOC_IOCFG0_EDGE_DET_M 0x00030000 +#define IOC_IOCFG0_EDGE_DET_S 16 +#define IOC_IOCFG0_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG0_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG0_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG0_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -251,21 +251,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG0_PULL_CTL_W 2 -#define IOC_IOCFG0_PULL_CTL_M 0x00006000 -#define IOC_IOCFG0_PULL_CTL_S 13 -#define IOC_IOCFG0_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG0_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG0_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG0_PULL_CTL_W 2 +#define IOC_IOCFG0_PULL_CTL_M 0x00006000 +#define IOC_IOCFG0_PULL_CTL_S 13 +#define IOC_IOCFG0_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG0_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG0_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG0_SLEW_RED 0x00001000 -#define IOC_IOCFG0_SLEW_RED_BITN 12 -#define IOC_IOCFG0_SLEW_RED_M 0x00001000 -#define IOC_IOCFG0_SLEW_RED_S 12 +#define IOC_IOCFG0_SLEW_RED 0x00001000 +#define IOC_IOCFG0_SLEW_RED_BITN 12 +#define IOC_IOCFG0_SLEW_RED_M 0x00001000 +#define IOC_IOCFG0_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -278,12 +278,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG0_IOCURR_W 2 -#define IOC_IOCFG0_IOCURR_M 0x00000C00 -#define IOC_IOCFG0_IOCURR_S 10 -#define IOC_IOCFG0_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG0_IOCURR_4MA 0x00000400 -#define IOC_IOCFG0_IOCURR_2MA 0x00000000 +#define IOC_IOCFG0_IOCURR_W 2 +#define IOC_IOCFG0_IOCURR_M 0x00000C00 +#define IOC_IOCFG0_IOCURR_S 10 +#define IOC_IOCFG0_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG0_IOCURR_4MA 0x00000400 +#define IOC_IOCFG0_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -302,13 +302,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG0_IOSTR_W 2 -#define IOC_IOCFG0_IOSTR_M 0x00000300 -#define IOC_IOCFG0_IOSTR_S 8 -#define IOC_IOCFG0_IOSTR_MAX 0x00000300 -#define IOC_IOCFG0_IOSTR_MED 0x00000200 -#define IOC_IOCFG0_IOSTR_MIN 0x00000100 -#define IOC_IOCFG0_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG0_IOSTR_W 2 +#define IOC_IOCFG0_IOSTR_M 0x00000300 +#define IOC_IOCFG0_IOSTR_S 8 +#define IOC_IOCFG0_IOSTR_MAX 0x00000300 +#define IOC_IOCFG0_IOSTR_MED 0x00000200 +#define IOC_IOCFG0_IOSTR_MIN 0x00000100 +#define IOC_IOCFG0_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -396,51 +396,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG0_PORT_ID_W 6 -#define IOC_IOCFG0_PORT_ID_M 0x0000003F -#define IOC_IOCFG0_PORT_ID_S 0 -#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG0_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG0_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG0_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG0_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG0_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG0_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG0_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG0_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG0_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG0_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG0_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG0_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG0_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG0_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG0_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG0_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG0_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG0_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG0_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG0_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG0_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG0_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG0_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG0_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG0_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG0_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG0_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG0_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG0_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG0_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG0_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG0_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG0_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG0_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG0_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG0_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG0_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG0_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG0_PORT_ID_W 6 +#define IOC_IOCFG0_PORT_ID_M 0x0000003F +#define IOC_IOCFG0_PORT_ID_S 0 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG0_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG0_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG0_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG0_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG0_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG0_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG0_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG0_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG0_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG0_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG0_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG0_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG0_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG0_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG0_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG0_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG0_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG0_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG0_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG0_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG0_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG0_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG0_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG0_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG0_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG0_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG0_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG0_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG0_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG0_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG0_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG0_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG0_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG0_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG0_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -451,10 +451,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG1_HYST_EN 0x40000000 -#define IOC_IOCFG1_HYST_EN_BITN 30 -#define IOC_IOCFG1_HYST_EN_M 0x40000000 -#define IOC_IOCFG1_HYST_EN_S 30 +#define IOC_IOCFG1_HYST_EN 0x40000000 +#define IOC_IOCFG1_HYST_EN_BITN 30 +#define IOC_IOCFG1_HYST_EN_M 0x40000000 +#define IOC_IOCFG1_HYST_EN_S 30 // Field: [29] IE // @@ -463,10 +463,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG1_IE 0x20000000 -#define IOC_IOCFG1_IE_BITN 29 -#define IOC_IOCFG1_IE_M 0x20000000 -#define IOC_IOCFG1_IE_S 29 +#define IOC_IOCFG1_IE 0x20000000 +#define IOC_IOCFG1_IE_BITN 29 +#define IOC_IOCFG1_IE_M 0x20000000 +#define IOC_IOCFG1_IE_S 29 // Field: [28:27] WU_CFG // @@ -488,9 +488,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG1_WU_CFG_W 2 -#define IOC_IOCFG1_WU_CFG_M 0x18000000 -#define IOC_IOCFG1_WU_CFG_S 27 +#define IOC_IOCFG1_WU_CFG_W 2 +#define IOC_IOCFG1_WU_CFG_M 0x18000000 +#define IOC_IOCFG1_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -511,25 +511,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG1_IOMODE_W 3 -#define IOC_IOCFG1_IOMODE_M 0x07000000 -#define IOC_IOCFG1_IOMODE_S 24 -#define IOC_IOCFG1_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG1_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG1_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG1_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG1_IOMODE_INV 0x01000000 -#define IOC_IOCFG1_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG1_IOMODE_W 3 +#define IOC_IOCFG1_IOMODE_M 0x07000000 +#define IOC_IOCFG1_IOMODE_S 24 +#define IOC_IOCFG1_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG1_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG1_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG1_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG1_IOMODE_INV 0x01000000 +#define IOC_IOCFG1_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG1_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG1_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG1_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG1_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG1_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG1_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG1_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG1_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -539,13 +539,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG1_EDGE_DET_W 2 -#define IOC_IOCFG1_EDGE_DET_M 0x00030000 -#define IOC_IOCFG1_EDGE_DET_S 16 -#define IOC_IOCFG1_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG1_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG1_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG1_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG1_EDGE_DET_W 2 +#define IOC_IOCFG1_EDGE_DET_M 0x00030000 +#define IOC_IOCFG1_EDGE_DET_S 16 +#define IOC_IOCFG1_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG1_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG1_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG1_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -554,21 +554,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG1_PULL_CTL_W 2 -#define IOC_IOCFG1_PULL_CTL_M 0x00006000 -#define IOC_IOCFG1_PULL_CTL_S 13 -#define IOC_IOCFG1_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG1_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG1_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG1_PULL_CTL_W 2 +#define IOC_IOCFG1_PULL_CTL_M 0x00006000 +#define IOC_IOCFG1_PULL_CTL_S 13 +#define IOC_IOCFG1_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG1_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG1_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG1_SLEW_RED 0x00001000 -#define IOC_IOCFG1_SLEW_RED_BITN 12 -#define IOC_IOCFG1_SLEW_RED_M 0x00001000 -#define IOC_IOCFG1_SLEW_RED_S 12 +#define IOC_IOCFG1_SLEW_RED 0x00001000 +#define IOC_IOCFG1_SLEW_RED_BITN 12 +#define IOC_IOCFG1_SLEW_RED_M 0x00001000 +#define IOC_IOCFG1_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -581,12 +581,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG1_IOCURR_W 2 -#define IOC_IOCFG1_IOCURR_M 0x00000C00 -#define IOC_IOCFG1_IOCURR_S 10 -#define IOC_IOCFG1_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG1_IOCURR_4MA 0x00000400 -#define IOC_IOCFG1_IOCURR_2MA 0x00000000 +#define IOC_IOCFG1_IOCURR_W 2 +#define IOC_IOCFG1_IOCURR_M 0x00000C00 +#define IOC_IOCFG1_IOCURR_S 10 +#define IOC_IOCFG1_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG1_IOCURR_4MA 0x00000400 +#define IOC_IOCFG1_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -605,13 +605,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG1_IOSTR_W 2 -#define IOC_IOCFG1_IOSTR_M 0x00000300 -#define IOC_IOCFG1_IOSTR_S 8 -#define IOC_IOCFG1_IOSTR_MAX 0x00000300 -#define IOC_IOCFG1_IOSTR_MED 0x00000200 -#define IOC_IOCFG1_IOSTR_MIN 0x00000100 -#define IOC_IOCFG1_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG1_IOSTR_W 2 +#define IOC_IOCFG1_IOSTR_M 0x00000300 +#define IOC_IOCFG1_IOSTR_S 8 +#define IOC_IOCFG1_IOSTR_MAX 0x00000300 +#define IOC_IOCFG1_IOSTR_MED 0x00000200 +#define IOC_IOCFG1_IOSTR_MIN 0x00000100 +#define IOC_IOCFG1_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -699,51 +699,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG1_PORT_ID_W 6 -#define IOC_IOCFG1_PORT_ID_M 0x0000003F -#define IOC_IOCFG1_PORT_ID_S 0 -#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG1_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG1_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG1_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG1_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG1_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG1_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG1_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG1_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG1_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG1_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG1_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG1_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG1_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG1_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG1_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG1_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG1_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG1_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG1_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG1_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG1_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG1_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG1_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG1_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG1_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG1_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG1_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG1_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG1_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG1_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG1_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG1_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG1_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG1_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG1_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG1_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG1_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG1_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG1_PORT_ID_W 6 +#define IOC_IOCFG1_PORT_ID_M 0x0000003F +#define IOC_IOCFG1_PORT_ID_S 0 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG1_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG1_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG1_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG1_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG1_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG1_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG1_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG1_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG1_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG1_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG1_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG1_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG1_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG1_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG1_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG1_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG1_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG1_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG1_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG1_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG1_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG1_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG1_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG1_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG1_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG1_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG1_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG1_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG1_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG1_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG1_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG1_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG1_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG1_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG1_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -754,10 +754,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG2_HYST_EN 0x40000000 -#define IOC_IOCFG2_HYST_EN_BITN 30 -#define IOC_IOCFG2_HYST_EN_M 0x40000000 -#define IOC_IOCFG2_HYST_EN_S 30 +#define IOC_IOCFG2_HYST_EN 0x40000000 +#define IOC_IOCFG2_HYST_EN_BITN 30 +#define IOC_IOCFG2_HYST_EN_M 0x40000000 +#define IOC_IOCFG2_HYST_EN_S 30 // Field: [29] IE // @@ -766,10 +766,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG2_IE 0x20000000 -#define IOC_IOCFG2_IE_BITN 29 -#define IOC_IOCFG2_IE_M 0x20000000 -#define IOC_IOCFG2_IE_S 29 +#define IOC_IOCFG2_IE 0x20000000 +#define IOC_IOCFG2_IE_BITN 29 +#define IOC_IOCFG2_IE_M 0x20000000 +#define IOC_IOCFG2_IE_S 29 // Field: [28:27] WU_CFG // @@ -791,9 +791,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG2_WU_CFG_W 2 -#define IOC_IOCFG2_WU_CFG_M 0x18000000 -#define IOC_IOCFG2_WU_CFG_S 27 +#define IOC_IOCFG2_WU_CFG_W 2 +#define IOC_IOCFG2_WU_CFG_M 0x18000000 +#define IOC_IOCFG2_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -814,25 +814,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG2_IOMODE_W 3 -#define IOC_IOCFG2_IOMODE_M 0x07000000 -#define IOC_IOCFG2_IOMODE_S 24 -#define IOC_IOCFG2_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG2_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG2_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG2_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG2_IOMODE_INV 0x01000000 -#define IOC_IOCFG2_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG2_IOMODE_W 3 +#define IOC_IOCFG2_IOMODE_M 0x07000000 +#define IOC_IOCFG2_IOMODE_S 24 +#define IOC_IOCFG2_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG2_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG2_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG2_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG2_IOMODE_INV 0x01000000 +#define IOC_IOCFG2_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG2_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG2_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG2_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG2_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG2_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG2_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG2_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG2_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -842,13 +842,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG2_EDGE_DET_W 2 -#define IOC_IOCFG2_EDGE_DET_M 0x00030000 -#define IOC_IOCFG2_EDGE_DET_S 16 -#define IOC_IOCFG2_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG2_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG2_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG2_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG2_EDGE_DET_W 2 +#define IOC_IOCFG2_EDGE_DET_M 0x00030000 +#define IOC_IOCFG2_EDGE_DET_S 16 +#define IOC_IOCFG2_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG2_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG2_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG2_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -857,21 +857,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG2_PULL_CTL_W 2 -#define IOC_IOCFG2_PULL_CTL_M 0x00006000 -#define IOC_IOCFG2_PULL_CTL_S 13 -#define IOC_IOCFG2_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG2_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG2_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG2_PULL_CTL_W 2 +#define IOC_IOCFG2_PULL_CTL_M 0x00006000 +#define IOC_IOCFG2_PULL_CTL_S 13 +#define IOC_IOCFG2_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG2_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG2_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG2_SLEW_RED 0x00001000 -#define IOC_IOCFG2_SLEW_RED_BITN 12 -#define IOC_IOCFG2_SLEW_RED_M 0x00001000 -#define IOC_IOCFG2_SLEW_RED_S 12 +#define IOC_IOCFG2_SLEW_RED 0x00001000 +#define IOC_IOCFG2_SLEW_RED_BITN 12 +#define IOC_IOCFG2_SLEW_RED_M 0x00001000 +#define IOC_IOCFG2_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -884,12 +884,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG2_IOCURR_W 2 -#define IOC_IOCFG2_IOCURR_M 0x00000C00 -#define IOC_IOCFG2_IOCURR_S 10 -#define IOC_IOCFG2_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG2_IOCURR_4MA 0x00000400 -#define IOC_IOCFG2_IOCURR_2MA 0x00000000 +#define IOC_IOCFG2_IOCURR_W 2 +#define IOC_IOCFG2_IOCURR_M 0x00000C00 +#define IOC_IOCFG2_IOCURR_S 10 +#define IOC_IOCFG2_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG2_IOCURR_4MA 0x00000400 +#define IOC_IOCFG2_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -908,13 +908,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG2_IOSTR_W 2 -#define IOC_IOCFG2_IOSTR_M 0x00000300 -#define IOC_IOCFG2_IOSTR_S 8 -#define IOC_IOCFG2_IOSTR_MAX 0x00000300 -#define IOC_IOCFG2_IOSTR_MED 0x00000200 -#define IOC_IOCFG2_IOSTR_MIN 0x00000100 -#define IOC_IOCFG2_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG2_IOSTR_W 2 +#define IOC_IOCFG2_IOSTR_M 0x00000300 +#define IOC_IOCFG2_IOSTR_S 8 +#define IOC_IOCFG2_IOSTR_MAX 0x00000300 +#define IOC_IOCFG2_IOSTR_MED 0x00000200 +#define IOC_IOCFG2_IOSTR_MIN 0x00000100 +#define IOC_IOCFG2_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -1002,51 +1002,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG2_PORT_ID_W 6 -#define IOC_IOCFG2_PORT_ID_M 0x0000003F -#define IOC_IOCFG2_PORT_ID_S 0 -#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG2_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG2_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG2_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG2_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG2_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG2_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG2_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG2_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG2_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG2_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG2_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG2_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG2_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG2_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG2_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG2_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG2_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG2_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG2_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG2_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG2_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG2_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG2_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG2_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG2_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG2_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG2_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG2_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG2_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG2_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG2_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG2_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG2_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG2_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG2_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG2_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG2_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG2_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG2_PORT_ID_W 6 +#define IOC_IOCFG2_PORT_ID_M 0x0000003F +#define IOC_IOCFG2_PORT_ID_S 0 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG2_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG2_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG2_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG2_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG2_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG2_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG2_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG2_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG2_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG2_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG2_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG2_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG2_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG2_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG2_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG2_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG2_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG2_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG2_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG2_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG2_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG2_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG2_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG2_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG2_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG2_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG2_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG2_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG2_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG2_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG2_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG2_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG2_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG2_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG2_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -1057,10 +1057,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG3_HYST_EN 0x40000000 -#define IOC_IOCFG3_HYST_EN_BITN 30 -#define IOC_IOCFG3_HYST_EN_M 0x40000000 -#define IOC_IOCFG3_HYST_EN_S 30 +#define IOC_IOCFG3_HYST_EN 0x40000000 +#define IOC_IOCFG3_HYST_EN_BITN 30 +#define IOC_IOCFG3_HYST_EN_M 0x40000000 +#define IOC_IOCFG3_HYST_EN_S 30 // Field: [29] IE // @@ -1069,10 +1069,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG3_IE 0x20000000 -#define IOC_IOCFG3_IE_BITN 29 -#define IOC_IOCFG3_IE_M 0x20000000 -#define IOC_IOCFG3_IE_S 29 +#define IOC_IOCFG3_IE 0x20000000 +#define IOC_IOCFG3_IE_BITN 29 +#define IOC_IOCFG3_IE_M 0x20000000 +#define IOC_IOCFG3_IE_S 29 // Field: [28:27] WU_CFG // @@ -1094,9 +1094,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG3_WU_CFG_W 2 -#define IOC_IOCFG3_WU_CFG_M 0x18000000 -#define IOC_IOCFG3_WU_CFG_S 27 +#define IOC_IOCFG3_WU_CFG_W 2 +#define IOC_IOCFG3_WU_CFG_M 0x18000000 +#define IOC_IOCFG3_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -1117,25 +1117,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG3_IOMODE_W 3 -#define IOC_IOCFG3_IOMODE_M 0x07000000 -#define IOC_IOCFG3_IOMODE_S 24 -#define IOC_IOCFG3_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG3_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG3_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG3_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG3_IOMODE_INV 0x01000000 -#define IOC_IOCFG3_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG3_IOMODE_W 3 +#define IOC_IOCFG3_IOMODE_M 0x07000000 +#define IOC_IOCFG3_IOMODE_S 24 +#define IOC_IOCFG3_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG3_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG3_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG3_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG3_IOMODE_INV 0x01000000 +#define IOC_IOCFG3_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG3_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG3_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG3_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG3_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG3_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG3_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG3_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG3_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -1145,13 +1145,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG3_EDGE_DET_W 2 -#define IOC_IOCFG3_EDGE_DET_M 0x00030000 -#define IOC_IOCFG3_EDGE_DET_S 16 -#define IOC_IOCFG3_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG3_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG3_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG3_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG3_EDGE_DET_W 2 +#define IOC_IOCFG3_EDGE_DET_M 0x00030000 +#define IOC_IOCFG3_EDGE_DET_S 16 +#define IOC_IOCFG3_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG3_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG3_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG3_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -1160,21 +1160,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG3_PULL_CTL_W 2 -#define IOC_IOCFG3_PULL_CTL_M 0x00006000 -#define IOC_IOCFG3_PULL_CTL_S 13 -#define IOC_IOCFG3_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG3_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG3_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG3_PULL_CTL_W 2 +#define IOC_IOCFG3_PULL_CTL_M 0x00006000 +#define IOC_IOCFG3_PULL_CTL_S 13 +#define IOC_IOCFG3_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG3_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG3_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG3_SLEW_RED 0x00001000 -#define IOC_IOCFG3_SLEW_RED_BITN 12 -#define IOC_IOCFG3_SLEW_RED_M 0x00001000 -#define IOC_IOCFG3_SLEW_RED_S 12 +#define IOC_IOCFG3_SLEW_RED 0x00001000 +#define IOC_IOCFG3_SLEW_RED_BITN 12 +#define IOC_IOCFG3_SLEW_RED_M 0x00001000 +#define IOC_IOCFG3_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -1187,12 +1187,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG3_IOCURR_W 2 -#define IOC_IOCFG3_IOCURR_M 0x00000C00 -#define IOC_IOCFG3_IOCURR_S 10 -#define IOC_IOCFG3_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG3_IOCURR_4MA 0x00000400 -#define IOC_IOCFG3_IOCURR_2MA 0x00000000 +#define IOC_IOCFG3_IOCURR_W 2 +#define IOC_IOCFG3_IOCURR_M 0x00000C00 +#define IOC_IOCFG3_IOCURR_S 10 +#define IOC_IOCFG3_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG3_IOCURR_4MA 0x00000400 +#define IOC_IOCFG3_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -1211,13 +1211,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG3_IOSTR_W 2 -#define IOC_IOCFG3_IOSTR_M 0x00000300 -#define IOC_IOCFG3_IOSTR_S 8 -#define IOC_IOCFG3_IOSTR_MAX 0x00000300 -#define IOC_IOCFG3_IOSTR_MED 0x00000200 -#define IOC_IOCFG3_IOSTR_MIN 0x00000100 -#define IOC_IOCFG3_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG3_IOSTR_W 2 +#define IOC_IOCFG3_IOSTR_M 0x00000300 +#define IOC_IOCFG3_IOSTR_S 8 +#define IOC_IOCFG3_IOSTR_MAX 0x00000300 +#define IOC_IOCFG3_IOSTR_MED 0x00000200 +#define IOC_IOCFG3_IOSTR_MIN 0x00000100 +#define IOC_IOCFG3_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -1305,51 +1305,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG3_PORT_ID_W 6 -#define IOC_IOCFG3_PORT_ID_M 0x0000003F -#define IOC_IOCFG3_PORT_ID_S 0 -#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG3_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG3_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG3_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG3_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG3_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG3_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG3_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG3_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG3_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG3_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG3_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG3_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG3_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG3_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG3_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG3_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG3_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG3_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG3_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG3_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG3_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG3_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG3_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG3_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG3_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG3_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG3_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG3_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG3_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG3_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG3_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG3_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG3_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG3_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG3_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG3_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG3_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG3_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG3_PORT_ID_W 6 +#define IOC_IOCFG3_PORT_ID_M 0x0000003F +#define IOC_IOCFG3_PORT_ID_S 0 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG3_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG3_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG3_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG3_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG3_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG3_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG3_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG3_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG3_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG3_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG3_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG3_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG3_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG3_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG3_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG3_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG3_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG3_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG3_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG3_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG3_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG3_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG3_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG3_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG3_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG3_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG3_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG3_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG3_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG3_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG3_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG3_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG3_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG3_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG3_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -1360,10 +1360,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG4_HYST_EN 0x40000000 -#define IOC_IOCFG4_HYST_EN_BITN 30 -#define IOC_IOCFG4_HYST_EN_M 0x40000000 -#define IOC_IOCFG4_HYST_EN_S 30 +#define IOC_IOCFG4_HYST_EN 0x40000000 +#define IOC_IOCFG4_HYST_EN_BITN 30 +#define IOC_IOCFG4_HYST_EN_M 0x40000000 +#define IOC_IOCFG4_HYST_EN_S 30 // Field: [29] IE // @@ -1372,10 +1372,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG4_IE 0x20000000 -#define IOC_IOCFG4_IE_BITN 29 -#define IOC_IOCFG4_IE_M 0x20000000 -#define IOC_IOCFG4_IE_S 29 +#define IOC_IOCFG4_IE 0x20000000 +#define IOC_IOCFG4_IE_BITN 29 +#define IOC_IOCFG4_IE_M 0x20000000 +#define IOC_IOCFG4_IE_S 29 // Field: [28:27] WU_CFG // @@ -1397,9 +1397,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG4_WU_CFG_W 2 -#define IOC_IOCFG4_WU_CFG_M 0x18000000 -#define IOC_IOCFG4_WU_CFG_S 27 +#define IOC_IOCFG4_WU_CFG_W 2 +#define IOC_IOCFG4_WU_CFG_M 0x18000000 +#define IOC_IOCFG4_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -1420,25 +1420,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG4_IOMODE_W 3 -#define IOC_IOCFG4_IOMODE_M 0x07000000 -#define IOC_IOCFG4_IOMODE_S 24 -#define IOC_IOCFG4_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG4_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG4_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG4_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG4_IOMODE_INV 0x01000000 -#define IOC_IOCFG4_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG4_IOMODE_W 3 +#define IOC_IOCFG4_IOMODE_M 0x07000000 +#define IOC_IOCFG4_IOMODE_S 24 +#define IOC_IOCFG4_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG4_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG4_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG4_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG4_IOMODE_INV 0x01000000 +#define IOC_IOCFG4_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG4_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG4_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG4_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG4_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG4_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG4_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG4_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG4_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -1448,13 +1448,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG4_EDGE_DET_W 2 -#define IOC_IOCFG4_EDGE_DET_M 0x00030000 -#define IOC_IOCFG4_EDGE_DET_S 16 -#define IOC_IOCFG4_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG4_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG4_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG4_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG4_EDGE_DET_W 2 +#define IOC_IOCFG4_EDGE_DET_M 0x00030000 +#define IOC_IOCFG4_EDGE_DET_S 16 +#define IOC_IOCFG4_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG4_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG4_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG4_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -1463,21 +1463,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG4_PULL_CTL_W 2 -#define IOC_IOCFG4_PULL_CTL_M 0x00006000 -#define IOC_IOCFG4_PULL_CTL_S 13 -#define IOC_IOCFG4_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG4_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG4_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG4_PULL_CTL_W 2 +#define IOC_IOCFG4_PULL_CTL_M 0x00006000 +#define IOC_IOCFG4_PULL_CTL_S 13 +#define IOC_IOCFG4_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG4_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG4_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG4_SLEW_RED 0x00001000 -#define IOC_IOCFG4_SLEW_RED_BITN 12 -#define IOC_IOCFG4_SLEW_RED_M 0x00001000 -#define IOC_IOCFG4_SLEW_RED_S 12 +#define IOC_IOCFG4_SLEW_RED 0x00001000 +#define IOC_IOCFG4_SLEW_RED_BITN 12 +#define IOC_IOCFG4_SLEW_RED_M 0x00001000 +#define IOC_IOCFG4_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -1490,12 +1490,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG4_IOCURR_W 2 -#define IOC_IOCFG4_IOCURR_M 0x00000C00 -#define IOC_IOCFG4_IOCURR_S 10 -#define IOC_IOCFG4_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG4_IOCURR_4MA 0x00000400 -#define IOC_IOCFG4_IOCURR_2MA 0x00000000 +#define IOC_IOCFG4_IOCURR_W 2 +#define IOC_IOCFG4_IOCURR_M 0x00000C00 +#define IOC_IOCFG4_IOCURR_S 10 +#define IOC_IOCFG4_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG4_IOCURR_4MA 0x00000400 +#define IOC_IOCFG4_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -1514,13 +1514,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG4_IOSTR_W 2 -#define IOC_IOCFG4_IOSTR_M 0x00000300 -#define IOC_IOCFG4_IOSTR_S 8 -#define IOC_IOCFG4_IOSTR_MAX 0x00000300 -#define IOC_IOCFG4_IOSTR_MED 0x00000200 -#define IOC_IOCFG4_IOSTR_MIN 0x00000100 -#define IOC_IOCFG4_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG4_IOSTR_W 2 +#define IOC_IOCFG4_IOSTR_M 0x00000300 +#define IOC_IOCFG4_IOSTR_S 8 +#define IOC_IOCFG4_IOSTR_MAX 0x00000300 +#define IOC_IOCFG4_IOSTR_MED 0x00000200 +#define IOC_IOCFG4_IOSTR_MIN 0x00000100 +#define IOC_IOCFG4_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -1608,51 +1608,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG4_PORT_ID_W 6 -#define IOC_IOCFG4_PORT_ID_M 0x0000003F -#define IOC_IOCFG4_PORT_ID_S 0 -#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG4_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG4_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG4_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG4_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG4_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG4_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG4_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG4_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG4_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG4_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG4_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG4_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG4_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG4_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG4_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG4_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG4_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG4_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG4_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG4_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG4_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG4_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG4_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG4_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG4_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG4_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG4_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG4_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG4_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG4_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG4_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG4_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG4_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG4_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG4_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG4_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG4_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG4_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG4_PORT_ID_W 6 +#define IOC_IOCFG4_PORT_ID_M 0x0000003F +#define IOC_IOCFG4_PORT_ID_S 0 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG4_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG4_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG4_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG4_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG4_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG4_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG4_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG4_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG4_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG4_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG4_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG4_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG4_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG4_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG4_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG4_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG4_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG4_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG4_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG4_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG4_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG4_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG4_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG4_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG4_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG4_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG4_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG4_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG4_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG4_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG4_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG4_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG4_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG4_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG4_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -1663,10 +1663,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG5_HYST_EN 0x40000000 -#define IOC_IOCFG5_HYST_EN_BITN 30 -#define IOC_IOCFG5_HYST_EN_M 0x40000000 -#define IOC_IOCFG5_HYST_EN_S 30 +#define IOC_IOCFG5_HYST_EN 0x40000000 +#define IOC_IOCFG5_HYST_EN_BITN 30 +#define IOC_IOCFG5_HYST_EN_M 0x40000000 +#define IOC_IOCFG5_HYST_EN_S 30 // Field: [29] IE // @@ -1675,10 +1675,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG5_IE 0x20000000 -#define IOC_IOCFG5_IE_BITN 29 -#define IOC_IOCFG5_IE_M 0x20000000 -#define IOC_IOCFG5_IE_S 29 +#define IOC_IOCFG5_IE 0x20000000 +#define IOC_IOCFG5_IE_BITN 29 +#define IOC_IOCFG5_IE_M 0x20000000 +#define IOC_IOCFG5_IE_S 29 // Field: [28:27] WU_CFG // @@ -1700,9 +1700,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG5_WU_CFG_W 2 -#define IOC_IOCFG5_WU_CFG_M 0x18000000 -#define IOC_IOCFG5_WU_CFG_S 27 +#define IOC_IOCFG5_WU_CFG_W 2 +#define IOC_IOCFG5_WU_CFG_M 0x18000000 +#define IOC_IOCFG5_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -1723,25 +1723,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG5_IOMODE_W 3 -#define IOC_IOCFG5_IOMODE_M 0x07000000 -#define IOC_IOCFG5_IOMODE_S 24 -#define IOC_IOCFG5_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG5_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG5_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG5_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG5_IOMODE_INV 0x01000000 -#define IOC_IOCFG5_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG5_IOMODE_W 3 +#define IOC_IOCFG5_IOMODE_M 0x07000000 +#define IOC_IOCFG5_IOMODE_S 24 +#define IOC_IOCFG5_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG5_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG5_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG5_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG5_IOMODE_INV 0x01000000 +#define IOC_IOCFG5_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG5_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG5_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG5_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG5_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG5_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG5_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG5_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG5_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -1751,13 +1751,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG5_EDGE_DET_W 2 -#define IOC_IOCFG5_EDGE_DET_M 0x00030000 -#define IOC_IOCFG5_EDGE_DET_S 16 -#define IOC_IOCFG5_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG5_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG5_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG5_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG5_EDGE_DET_W 2 +#define IOC_IOCFG5_EDGE_DET_M 0x00030000 +#define IOC_IOCFG5_EDGE_DET_S 16 +#define IOC_IOCFG5_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG5_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG5_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG5_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -1766,21 +1766,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG5_PULL_CTL_W 2 -#define IOC_IOCFG5_PULL_CTL_M 0x00006000 -#define IOC_IOCFG5_PULL_CTL_S 13 -#define IOC_IOCFG5_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG5_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG5_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG5_PULL_CTL_W 2 +#define IOC_IOCFG5_PULL_CTL_M 0x00006000 +#define IOC_IOCFG5_PULL_CTL_S 13 +#define IOC_IOCFG5_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG5_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG5_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG5_SLEW_RED 0x00001000 -#define IOC_IOCFG5_SLEW_RED_BITN 12 -#define IOC_IOCFG5_SLEW_RED_M 0x00001000 -#define IOC_IOCFG5_SLEW_RED_S 12 +#define IOC_IOCFG5_SLEW_RED 0x00001000 +#define IOC_IOCFG5_SLEW_RED_BITN 12 +#define IOC_IOCFG5_SLEW_RED_M 0x00001000 +#define IOC_IOCFG5_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -1793,12 +1793,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG5_IOCURR_W 2 -#define IOC_IOCFG5_IOCURR_M 0x00000C00 -#define IOC_IOCFG5_IOCURR_S 10 -#define IOC_IOCFG5_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG5_IOCURR_4MA 0x00000400 -#define IOC_IOCFG5_IOCURR_2MA 0x00000000 +#define IOC_IOCFG5_IOCURR_W 2 +#define IOC_IOCFG5_IOCURR_M 0x00000C00 +#define IOC_IOCFG5_IOCURR_S 10 +#define IOC_IOCFG5_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG5_IOCURR_4MA 0x00000400 +#define IOC_IOCFG5_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -1817,13 +1817,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG5_IOSTR_W 2 -#define IOC_IOCFG5_IOSTR_M 0x00000300 -#define IOC_IOCFG5_IOSTR_S 8 -#define IOC_IOCFG5_IOSTR_MAX 0x00000300 -#define IOC_IOCFG5_IOSTR_MED 0x00000200 -#define IOC_IOCFG5_IOSTR_MIN 0x00000100 -#define IOC_IOCFG5_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG5_IOSTR_W 2 +#define IOC_IOCFG5_IOSTR_M 0x00000300 +#define IOC_IOCFG5_IOSTR_S 8 +#define IOC_IOCFG5_IOSTR_MAX 0x00000300 +#define IOC_IOCFG5_IOSTR_MED 0x00000200 +#define IOC_IOCFG5_IOSTR_MIN 0x00000100 +#define IOC_IOCFG5_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -1911,51 +1911,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG5_PORT_ID_W 6 -#define IOC_IOCFG5_PORT_ID_M 0x0000003F -#define IOC_IOCFG5_PORT_ID_S 0 -#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG5_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG5_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG5_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG5_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG5_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG5_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG5_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG5_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG5_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG5_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG5_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG5_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG5_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG5_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG5_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG5_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG5_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG5_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG5_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG5_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG5_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG5_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG5_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG5_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG5_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG5_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG5_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG5_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG5_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG5_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG5_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG5_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG5_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG5_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG5_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG5_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG5_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG5_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG5_PORT_ID_W 6 +#define IOC_IOCFG5_PORT_ID_M 0x0000003F +#define IOC_IOCFG5_PORT_ID_S 0 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG5_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG5_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG5_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG5_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG5_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG5_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG5_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG5_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG5_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG5_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG5_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG5_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG5_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG5_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG5_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG5_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG5_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG5_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG5_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG5_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG5_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG5_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG5_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG5_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG5_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG5_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG5_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG5_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG5_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG5_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG5_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG5_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG5_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG5_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG5_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -1966,10 +1966,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG6_HYST_EN 0x40000000 -#define IOC_IOCFG6_HYST_EN_BITN 30 -#define IOC_IOCFG6_HYST_EN_M 0x40000000 -#define IOC_IOCFG6_HYST_EN_S 30 +#define IOC_IOCFG6_HYST_EN 0x40000000 +#define IOC_IOCFG6_HYST_EN_BITN 30 +#define IOC_IOCFG6_HYST_EN_M 0x40000000 +#define IOC_IOCFG6_HYST_EN_S 30 // Field: [29] IE // @@ -1978,10 +1978,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG6_IE 0x20000000 -#define IOC_IOCFG6_IE_BITN 29 -#define IOC_IOCFG6_IE_M 0x20000000 -#define IOC_IOCFG6_IE_S 29 +#define IOC_IOCFG6_IE 0x20000000 +#define IOC_IOCFG6_IE_BITN 29 +#define IOC_IOCFG6_IE_M 0x20000000 +#define IOC_IOCFG6_IE_S 29 // Field: [28:27] WU_CFG // @@ -2003,9 +2003,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG6_WU_CFG_W 2 -#define IOC_IOCFG6_WU_CFG_M 0x18000000 -#define IOC_IOCFG6_WU_CFG_S 27 +#define IOC_IOCFG6_WU_CFG_W 2 +#define IOC_IOCFG6_WU_CFG_M 0x18000000 +#define IOC_IOCFG6_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -2026,25 +2026,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG6_IOMODE_W 3 -#define IOC_IOCFG6_IOMODE_M 0x07000000 -#define IOC_IOCFG6_IOMODE_S 24 -#define IOC_IOCFG6_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG6_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG6_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG6_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG6_IOMODE_INV 0x01000000 -#define IOC_IOCFG6_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG6_IOMODE_W 3 +#define IOC_IOCFG6_IOMODE_M 0x07000000 +#define IOC_IOCFG6_IOMODE_S 24 +#define IOC_IOCFG6_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG6_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG6_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG6_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG6_IOMODE_INV 0x01000000 +#define IOC_IOCFG6_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG6_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG6_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG6_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG6_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG6_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG6_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG6_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG6_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -2054,13 +2054,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG6_EDGE_DET_W 2 -#define IOC_IOCFG6_EDGE_DET_M 0x00030000 -#define IOC_IOCFG6_EDGE_DET_S 16 -#define IOC_IOCFG6_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG6_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG6_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG6_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG6_EDGE_DET_W 2 +#define IOC_IOCFG6_EDGE_DET_M 0x00030000 +#define IOC_IOCFG6_EDGE_DET_S 16 +#define IOC_IOCFG6_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG6_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG6_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG6_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -2069,21 +2069,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG6_PULL_CTL_W 2 -#define IOC_IOCFG6_PULL_CTL_M 0x00006000 -#define IOC_IOCFG6_PULL_CTL_S 13 -#define IOC_IOCFG6_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG6_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG6_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG6_PULL_CTL_W 2 +#define IOC_IOCFG6_PULL_CTL_M 0x00006000 +#define IOC_IOCFG6_PULL_CTL_S 13 +#define IOC_IOCFG6_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG6_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG6_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG6_SLEW_RED 0x00001000 -#define IOC_IOCFG6_SLEW_RED_BITN 12 -#define IOC_IOCFG6_SLEW_RED_M 0x00001000 -#define IOC_IOCFG6_SLEW_RED_S 12 +#define IOC_IOCFG6_SLEW_RED 0x00001000 +#define IOC_IOCFG6_SLEW_RED_BITN 12 +#define IOC_IOCFG6_SLEW_RED_M 0x00001000 +#define IOC_IOCFG6_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -2096,12 +2096,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG6_IOCURR_W 2 -#define IOC_IOCFG6_IOCURR_M 0x00000C00 -#define IOC_IOCFG6_IOCURR_S 10 -#define IOC_IOCFG6_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG6_IOCURR_4MA 0x00000400 -#define IOC_IOCFG6_IOCURR_2MA 0x00000000 +#define IOC_IOCFG6_IOCURR_W 2 +#define IOC_IOCFG6_IOCURR_M 0x00000C00 +#define IOC_IOCFG6_IOCURR_S 10 +#define IOC_IOCFG6_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG6_IOCURR_4MA 0x00000400 +#define IOC_IOCFG6_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -2120,13 +2120,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG6_IOSTR_W 2 -#define IOC_IOCFG6_IOSTR_M 0x00000300 -#define IOC_IOCFG6_IOSTR_S 8 -#define IOC_IOCFG6_IOSTR_MAX 0x00000300 -#define IOC_IOCFG6_IOSTR_MED 0x00000200 -#define IOC_IOCFG6_IOSTR_MIN 0x00000100 -#define IOC_IOCFG6_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG6_IOSTR_W 2 +#define IOC_IOCFG6_IOSTR_M 0x00000300 +#define IOC_IOCFG6_IOSTR_S 8 +#define IOC_IOCFG6_IOSTR_MAX 0x00000300 +#define IOC_IOCFG6_IOSTR_MED 0x00000200 +#define IOC_IOCFG6_IOSTR_MIN 0x00000100 +#define IOC_IOCFG6_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -2214,51 +2214,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG6_PORT_ID_W 6 -#define IOC_IOCFG6_PORT_ID_M 0x0000003F -#define IOC_IOCFG6_PORT_ID_S 0 -#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG6_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG6_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG6_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG6_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG6_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG6_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG6_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG6_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG6_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG6_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG6_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG6_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG6_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG6_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG6_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG6_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG6_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG6_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG6_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG6_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG6_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG6_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG6_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG6_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG6_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG6_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG6_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG6_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG6_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG6_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG6_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG6_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG6_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG6_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG6_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG6_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG6_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG6_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG6_PORT_ID_W 6 +#define IOC_IOCFG6_PORT_ID_M 0x0000003F +#define IOC_IOCFG6_PORT_ID_S 0 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG6_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG6_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG6_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG6_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG6_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG6_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG6_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG6_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG6_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG6_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG6_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG6_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG6_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG6_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG6_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG6_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG6_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG6_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG6_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG6_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG6_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG6_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG6_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG6_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG6_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG6_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG6_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG6_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG6_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG6_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG6_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG6_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG6_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG6_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG6_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -2269,10 +2269,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG7_HYST_EN 0x40000000 -#define IOC_IOCFG7_HYST_EN_BITN 30 -#define IOC_IOCFG7_HYST_EN_M 0x40000000 -#define IOC_IOCFG7_HYST_EN_S 30 +#define IOC_IOCFG7_HYST_EN 0x40000000 +#define IOC_IOCFG7_HYST_EN_BITN 30 +#define IOC_IOCFG7_HYST_EN_M 0x40000000 +#define IOC_IOCFG7_HYST_EN_S 30 // Field: [29] IE // @@ -2281,10 +2281,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG7_IE 0x20000000 -#define IOC_IOCFG7_IE_BITN 29 -#define IOC_IOCFG7_IE_M 0x20000000 -#define IOC_IOCFG7_IE_S 29 +#define IOC_IOCFG7_IE 0x20000000 +#define IOC_IOCFG7_IE_BITN 29 +#define IOC_IOCFG7_IE_M 0x20000000 +#define IOC_IOCFG7_IE_S 29 // Field: [28:27] WU_CFG // @@ -2306,9 +2306,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG7_WU_CFG_W 2 -#define IOC_IOCFG7_WU_CFG_M 0x18000000 -#define IOC_IOCFG7_WU_CFG_S 27 +#define IOC_IOCFG7_WU_CFG_W 2 +#define IOC_IOCFG7_WU_CFG_M 0x18000000 +#define IOC_IOCFG7_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -2329,25 +2329,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG7_IOMODE_W 3 -#define IOC_IOCFG7_IOMODE_M 0x07000000 -#define IOC_IOCFG7_IOMODE_S 24 -#define IOC_IOCFG7_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG7_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG7_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG7_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG7_IOMODE_INV 0x01000000 -#define IOC_IOCFG7_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG7_IOMODE_W 3 +#define IOC_IOCFG7_IOMODE_M 0x07000000 +#define IOC_IOCFG7_IOMODE_S 24 +#define IOC_IOCFG7_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG7_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG7_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG7_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG7_IOMODE_INV 0x01000000 +#define IOC_IOCFG7_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG7_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG7_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG7_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG7_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG7_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG7_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG7_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG7_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -2357,13 +2357,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG7_EDGE_DET_W 2 -#define IOC_IOCFG7_EDGE_DET_M 0x00030000 -#define IOC_IOCFG7_EDGE_DET_S 16 -#define IOC_IOCFG7_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG7_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG7_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG7_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG7_EDGE_DET_W 2 +#define IOC_IOCFG7_EDGE_DET_M 0x00030000 +#define IOC_IOCFG7_EDGE_DET_S 16 +#define IOC_IOCFG7_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG7_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG7_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG7_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -2372,21 +2372,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG7_PULL_CTL_W 2 -#define IOC_IOCFG7_PULL_CTL_M 0x00006000 -#define IOC_IOCFG7_PULL_CTL_S 13 -#define IOC_IOCFG7_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG7_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG7_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG7_PULL_CTL_W 2 +#define IOC_IOCFG7_PULL_CTL_M 0x00006000 +#define IOC_IOCFG7_PULL_CTL_S 13 +#define IOC_IOCFG7_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG7_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG7_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG7_SLEW_RED 0x00001000 -#define IOC_IOCFG7_SLEW_RED_BITN 12 -#define IOC_IOCFG7_SLEW_RED_M 0x00001000 -#define IOC_IOCFG7_SLEW_RED_S 12 +#define IOC_IOCFG7_SLEW_RED 0x00001000 +#define IOC_IOCFG7_SLEW_RED_BITN 12 +#define IOC_IOCFG7_SLEW_RED_M 0x00001000 +#define IOC_IOCFG7_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -2399,12 +2399,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG7_IOCURR_W 2 -#define IOC_IOCFG7_IOCURR_M 0x00000C00 -#define IOC_IOCFG7_IOCURR_S 10 -#define IOC_IOCFG7_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG7_IOCURR_4MA 0x00000400 -#define IOC_IOCFG7_IOCURR_2MA 0x00000000 +#define IOC_IOCFG7_IOCURR_W 2 +#define IOC_IOCFG7_IOCURR_M 0x00000C00 +#define IOC_IOCFG7_IOCURR_S 10 +#define IOC_IOCFG7_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG7_IOCURR_4MA 0x00000400 +#define IOC_IOCFG7_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -2423,13 +2423,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG7_IOSTR_W 2 -#define IOC_IOCFG7_IOSTR_M 0x00000300 -#define IOC_IOCFG7_IOSTR_S 8 -#define IOC_IOCFG7_IOSTR_MAX 0x00000300 -#define IOC_IOCFG7_IOSTR_MED 0x00000200 -#define IOC_IOCFG7_IOSTR_MIN 0x00000100 -#define IOC_IOCFG7_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG7_IOSTR_W 2 +#define IOC_IOCFG7_IOSTR_M 0x00000300 +#define IOC_IOCFG7_IOSTR_S 8 +#define IOC_IOCFG7_IOSTR_MAX 0x00000300 +#define IOC_IOCFG7_IOSTR_MED 0x00000200 +#define IOC_IOCFG7_IOSTR_MIN 0x00000100 +#define IOC_IOCFG7_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -2517,51 +2517,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG7_PORT_ID_W 6 -#define IOC_IOCFG7_PORT_ID_M 0x0000003F -#define IOC_IOCFG7_PORT_ID_S 0 -#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG7_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG7_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG7_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG7_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG7_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG7_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG7_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG7_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG7_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG7_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG7_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG7_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG7_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG7_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG7_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG7_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG7_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG7_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG7_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG7_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG7_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG7_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG7_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG7_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG7_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG7_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG7_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG7_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG7_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG7_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG7_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG7_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG7_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG7_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG7_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG7_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG7_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG7_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG7_PORT_ID_W 6 +#define IOC_IOCFG7_PORT_ID_M 0x0000003F +#define IOC_IOCFG7_PORT_ID_S 0 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG7_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG7_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG7_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG7_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG7_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG7_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG7_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG7_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG7_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG7_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG7_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG7_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG7_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG7_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG7_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG7_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG7_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG7_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG7_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG7_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG7_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG7_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG7_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG7_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG7_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG7_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG7_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG7_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG7_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG7_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG7_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG7_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG7_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG7_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG7_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -2572,10 +2572,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG8_HYST_EN 0x40000000 -#define IOC_IOCFG8_HYST_EN_BITN 30 -#define IOC_IOCFG8_HYST_EN_M 0x40000000 -#define IOC_IOCFG8_HYST_EN_S 30 +#define IOC_IOCFG8_HYST_EN 0x40000000 +#define IOC_IOCFG8_HYST_EN_BITN 30 +#define IOC_IOCFG8_HYST_EN_M 0x40000000 +#define IOC_IOCFG8_HYST_EN_S 30 // Field: [29] IE // @@ -2584,10 +2584,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG8_IE 0x20000000 -#define IOC_IOCFG8_IE_BITN 29 -#define IOC_IOCFG8_IE_M 0x20000000 -#define IOC_IOCFG8_IE_S 29 +#define IOC_IOCFG8_IE 0x20000000 +#define IOC_IOCFG8_IE_BITN 29 +#define IOC_IOCFG8_IE_M 0x20000000 +#define IOC_IOCFG8_IE_S 29 // Field: [28:27] WU_CFG // @@ -2609,9 +2609,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG8_WU_CFG_W 2 -#define IOC_IOCFG8_WU_CFG_M 0x18000000 -#define IOC_IOCFG8_WU_CFG_S 27 +#define IOC_IOCFG8_WU_CFG_W 2 +#define IOC_IOCFG8_WU_CFG_M 0x18000000 +#define IOC_IOCFG8_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -2632,25 +2632,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG8_IOMODE_W 3 -#define IOC_IOCFG8_IOMODE_M 0x07000000 -#define IOC_IOCFG8_IOMODE_S 24 -#define IOC_IOCFG8_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG8_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG8_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG8_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG8_IOMODE_INV 0x01000000 -#define IOC_IOCFG8_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG8_IOMODE_W 3 +#define IOC_IOCFG8_IOMODE_M 0x07000000 +#define IOC_IOCFG8_IOMODE_S 24 +#define IOC_IOCFG8_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG8_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG8_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG8_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG8_IOMODE_INV 0x01000000 +#define IOC_IOCFG8_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG8_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG8_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG8_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG8_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG8_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG8_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG8_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG8_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -2660,13 +2660,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG8_EDGE_DET_W 2 -#define IOC_IOCFG8_EDGE_DET_M 0x00030000 -#define IOC_IOCFG8_EDGE_DET_S 16 -#define IOC_IOCFG8_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG8_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG8_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG8_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG8_EDGE_DET_W 2 +#define IOC_IOCFG8_EDGE_DET_M 0x00030000 +#define IOC_IOCFG8_EDGE_DET_S 16 +#define IOC_IOCFG8_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG8_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG8_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG8_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -2675,21 +2675,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG8_PULL_CTL_W 2 -#define IOC_IOCFG8_PULL_CTL_M 0x00006000 -#define IOC_IOCFG8_PULL_CTL_S 13 -#define IOC_IOCFG8_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG8_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG8_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG8_PULL_CTL_W 2 +#define IOC_IOCFG8_PULL_CTL_M 0x00006000 +#define IOC_IOCFG8_PULL_CTL_S 13 +#define IOC_IOCFG8_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG8_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG8_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG8_SLEW_RED 0x00001000 -#define IOC_IOCFG8_SLEW_RED_BITN 12 -#define IOC_IOCFG8_SLEW_RED_M 0x00001000 -#define IOC_IOCFG8_SLEW_RED_S 12 +#define IOC_IOCFG8_SLEW_RED 0x00001000 +#define IOC_IOCFG8_SLEW_RED_BITN 12 +#define IOC_IOCFG8_SLEW_RED_M 0x00001000 +#define IOC_IOCFG8_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -2702,12 +2702,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG8_IOCURR_W 2 -#define IOC_IOCFG8_IOCURR_M 0x00000C00 -#define IOC_IOCFG8_IOCURR_S 10 -#define IOC_IOCFG8_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG8_IOCURR_4MA 0x00000400 -#define IOC_IOCFG8_IOCURR_2MA 0x00000000 +#define IOC_IOCFG8_IOCURR_W 2 +#define IOC_IOCFG8_IOCURR_M 0x00000C00 +#define IOC_IOCFG8_IOCURR_S 10 +#define IOC_IOCFG8_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG8_IOCURR_4MA 0x00000400 +#define IOC_IOCFG8_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -2726,13 +2726,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG8_IOSTR_W 2 -#define IOC_IOCFG8_IOSTR_M 0x00000300 -#define IOC_IOCFG8_IOSTR_S 8 -#define IOC_IOCFG8_IOSTR_MAX 0x00000300 -#define IOC_IOCFG8_IOSTR_MED 0x00000200 -#define IOC_IOCFG8_IOSTR_MIN 0x00000100 -#define IOC_IOCFG8_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG8_IOSTR_W 2 +#define IOC_IOCFG8_IOSTR_M 0x00000300 +#define IOC_IOCFG8_IOSTR_S 8 +#define IOC_IOCFG8_IOSTR_MAX 0x00000300 +#define IOC_IOCFG8_IOSTR_MED 0x00000200 +#define IOC_IOCFG8_IOSTR_MIN 0x00000100 +#define IOC_IOCFG8_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -2820,51 +2820,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG8_PORT_ID_W 6 -#define IOC_IOCFG8_PORT_ID_M 0x0000003F -#define IOC_IOCFG8_PORT_ID_S 0 -#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG8_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG8_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG8_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG8_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG8_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG8_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG8_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG8_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG8_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG8_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG8_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG8_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG8_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG8_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG8_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG8_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG8_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG8_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG8_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG8_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG8_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG8_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG8_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG8_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG8_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG8_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG8_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG8_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG8_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG8_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG8_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG8_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG8_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG8_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG8_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG8_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG8_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG8_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG8_PORT_ID_W 6 +#define IOC_IOCFG8_PORT_ID_M 0x0000003F +#define IOC_IOCFG8_PORT_ID_S 0 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG8_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG8_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG8_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG8_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG8_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG8_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG8_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG8_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG8_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG8_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG8_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG8_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG8_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG8_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG8_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG8_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG8_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG8_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG8_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG8_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG8_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG8_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG8_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG8_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG8_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG8_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG8_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG8_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG8_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG8_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG8_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG8_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG8_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG8_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG8_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -2875,10 +2875,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG9_HYST_EN 0x40000000 -#define IOC_IOCFG9_HYST_EN_BITN 30 -#define IOC_IOCFG9_HYST_EN_M 0x40000000 -#define IOC_IOCFG9_HYST_EN_S 30 +#define IOC_IOCFG9_HYST_EN 0x40000000 +#define IOC_IOCFG9_HYST_EN_BITN 30 +#define IOC_IOCFG9_HYST_EN_M 0x40000000 +#define IOC_IOCFG9_HYST_EN_S 30 // Field: [29] IE // @@ -2887,10 +2887,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG9_IE 0x20000000 -#define IOC_IOCFG9_IE_BITN 29 -#define IOC_IOCFG9_IE_M 0x20000000 -#define IOC_IOCFG9_IE_S 29 +#define IOC_IOCFG9_IE 0x20000000 +#define IOC_IOCFG9_IE_BITN 29 +#define IOC_IOCFG9_IE_M 0x20000000 +#define IOC_IOCFG9_IE_S 29 // Field: [28:27] WU_CFG // @@ -2912,9 +2912,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG9_WU_CFG_W 2 -#define IOC_IOCFG9_WU_CFG_M 0x18000000 -#define IOC_IOCFG9_WU_CFG_S 27 +#define IOC_IOCFG9_WU_CFG_W 2 +#define IOC_IOCFG9_WU_CFG_M 0x18000000 +#define IOC_IOCFG9_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -2935,25 +2935,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG9_IOMODE_W 3 -#define IOC_IOCFG9_IOMODE_M 0x07000000 -#define IOC_IOCFG9_IOMODE_S 24 -#define IOC_IOCFG9_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG9_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG9_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG9_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG9_IOMODE_INV 0x01000000 -#define IOC_IOCFG9_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG9_IOMODE_W 3 +#define IOC_IOCFG9_IOMODE_M 0x07000000 +#define IOC_IOCFG9_IOMODE_S 24 +#define IOC_IOCFG9_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG9_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG9_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG9_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG9_IOMODE_INV 0x01000000 +#define IOC_IOCFG9_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG9_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG9_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG9_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG9_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG9_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG9_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG9_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG9_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -2963,13 +2963,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG9_EDGE_DET_W 2 -#define IOC_IOCFG9_EDGE_DET_M 0x00030000 -#define IOC_IOCFG9_EDGE_DET_S 16 -#define IOC_IOCFG9_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG9_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG9_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG9_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG9_EDGE_DET_W 2 +#define IOC_IOCFG9_EDGE_DET_M 0x00030000 +#define IOC_IOCFG9_EDGE_DET_S 16 +#define IOC_IOCFG9_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG9_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG9_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG9_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -2978,21 +2978,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG9_PULL_CTL_W 2 -#define IOC_IOCFG9_PULL_CTL_M 0x00006000 -#define IOC_IOCFG9_PULL_CTL_S 13 -#define IOC_IOCFG9_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG9_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG9_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG9_PULL_CTL_W 2 +#define IOC_IOCFG9_PULL_CTL_M 0x00006000 +#define IOC_IOCFG9_PULL_CTL_S 13 +#define IOC_IOCFG9_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG9_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG9_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG9_SLEW_RED 0x00001000 -#define IOC_IOCFG9_SLEW_RED_BITN 12 -#define IOC_IOCFG9_SLEW_RED_M 0x00001000 -#define IOC_IOCFG9_SLEW_RED_S 12 +#define IOC_IOCFG9_SLEW_RED 0x00001000 +#define IOC_IOCFG9_SLEW_RED_BITN 12 +#define IOC_IOCFG9_SLEW_RED_M 0x00001000 +#define IOC_IOCFG9_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -3005,12 +3005,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG9_IOCURR_W 2 -#define IOC_IOCFG9_IOCURR_M 0x00000C00 -#define IOC_IOCFG9_IOCURR_S 10 -#define IOC_IOCFG9_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG9_IOCURR_4MA 0x00000400 -#define IOC_IOCFG9_IOCURR_2MA 0x00000000 +#define IOC_IOCFG9_IOCURR_W 2 +#define IOC_IOCFG9_IOCURR_M 0x00000C00 +#define IOC_IOCFG9_IOCURR_S 10 +#define IOC_IOCFG9_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG9_IOCURR_4MA 0x00000400 +#define IOC_IOCFG9_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -3029,13 +3029,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG9_IOSTR_W 2 -#define IOC_IOCFG9_IOSTR_M 0x00000300 -#define IOC_IOCFG9_IOSTR_S 8 -#define IOC_IOCFG9_IOSTR_MAX 0x00000300 -#define IOC_IOCFG9_IOSTR_MED 0x00000200 -#define IOC_IOCFG9_IOSTR_MIN 0x00000100 -#define IOC_IOCFG9_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG9_IOSTR_W 2 +#define IOC_IOCFG9_IOSTR_M 0x00000300 +#define IOC_IOCFG9_IOSTR_S 8 +#define IOC_IOCFG9_IOSTR_MAX 0x00000300 +#define IOC_IOCFG9_IOSTR_MED 0x00000200 +#define IOC_IOCFG9_IOSTR_MIN 0x00000100 +#define IOC_IOCFG9_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -3123,51 +3123,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG9_PORT_ID_W 6 -#define IOC_IOCFG9_PORT_ID_M 0x0000003F -#define IOC_IOCFG9_PORT_ID_S 0 -#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG9_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG9_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG9_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG9_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG9_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG9_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG9_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG9_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG9_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG9_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG9_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG9_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG9_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG9_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG9_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG9_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG9_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG9_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG9_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG9_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG9_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG9_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG9_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG9_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG9_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG9_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG9_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG9_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG9_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG9_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG9_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG9_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG9_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG9_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG9_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG9_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG9_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG9_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG9_PORT_ID_W 6 +#define IOC_IOCFG9_PORT_ID_M 0x0000003F +#define IOC_IOCFG9_PORT_ID_S 0 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG9_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG9_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG9_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG9_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG9_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG9_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG9_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG9_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG9_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG9_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG9_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG9_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG9_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG9_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG9_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG9_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG9_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG9_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG9_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG9_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG9_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG9_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG9_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG9_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG9_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG9_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG9_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG9_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG9_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG9_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG9_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG9_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG9_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG9_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG9_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -3178,10 +3178,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG10_HYST_EN 0x40000000 -#define IOC_IOCFG10_HYST_EN_BITN 30 -#define IOC_IOCFG10_HYST_EN_M 0x40000000 -#define IOC_IOCFG10_HYST_EN_S 30 +#define IOC_IOCFG10_HYST_EN 0x40000000 +#define IOC_IOCFG10_HYST_EN_BITN 30 +#define IOC_IOCFG10_HYST_EN_M 0x40000000 +#define IOC_IOCFG10_HYST_EN_S 30 // Field: [29] IE // @@ -3190,10 +3190,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG10_IE 0x20000000 -#define IOC_IOCFG10_IE_BITN 29 -#define IOC_IOCFG10_IE_M 0x20000000 -#define IOC_IOCFG10_IE_S 29 +#define IOC_IOCFG10_IE 0x20000000 +#define IOC_IOCFG10_IE_BITN 29 +#define IOC_IOCFG10_IE_M 0x20000000 +#define IOC_IOCFG10_IE_S 29 // Field: [28:27] WU_CFG // @@ -3215,9 +3215,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG10_WU_CFG_W 2 -#define IOC_IOCFG10_WU_CFG_M 0x18000000 -#define IOC_IOCFG10_WU_CFG_S 27 +#define IOC_IOCFG10_WU_CFG_W 2 +#define IOC_IOCFG10_WU_CFG_M 0x18000000 +#define IOC_IOCFG10_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -3238,25 +3238,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG10_IOMODE_W 3 -#define IOC_IOCFG10_IOMODE_M 0x07000000 -#define IOC_IOCFG10_IOMODE_S 24 -#define IOC_IOCFG10_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG10_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG10_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG10_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG10_IOMODE_INV 0x01000000 -#define IOC_IOCFG10_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG10_IOMODE_W 3 +#define IOC_IOCFG10_IOMODE_M 0x07000000 +#define IOC_IOCFG10_IOMODE_S 24 +#define IOC_IOCFG10_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG10_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG10_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG10_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG10_IOMODE_INV 0x01000000 +#define IOC_IOCFG10_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG10_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG10_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG10_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG10_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG10_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG10_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG10_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG10_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -3266,13 +3266,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG10_EDGE_DET_W 2 -#define IOC_IOCFG10_EDGE_DET_M 0x00030000 -#define IOC_IOCFG10_EDGE_DET_S 16 -#define IOC_IOCFG10_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG10_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG10_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG10_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG10_EDGE_DET_W 2 +#define IOC_IOCFG10_EDGE_DET_M 0x00030000 +#define IOC_IOCFG10_EDGE_DET_S 16 +#define IOC_IOCFG10_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG10_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG10_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG10_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -3281,21 +3281,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG10_PULL_CTL_W 2 -#define IOC_IOCFG10_PULL_CTL_M 0x00006000 -#define IOC_IOCFG10_PULL_CTL_S 13 -#define IOC_IOCFG10_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG10_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG10_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG10_PULL_CTL_W 2 +#define IOC_IOCFG10_PULL_CTL_M 0x00006000 +#define IOC_IOCFG10_PULL_CTL_S 13 +#define IOC_IOCFG10_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG10_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG10_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG10_SLEW_RED 0x00001000 -#define IOC_IOCFG10_SLEW_RED_BITN 12 -#define IOC_IOCFG10_SLEW_RED_M 0x00001000 -#define IOC_IOCFG10_SLEW_RED_S 12 +#define IOC_IOCFG10_SLEW_RED 0x00001000 +#define IOC_IOCFG10_SLEW_RED_BITN 12 +#define IOC_IOCFG10_SLEW_RED_M 0x00001000 +#define IOC_IOCFG10_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -3308,12 +3308,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG10_IOCURR_W 2 -#define IOC_IOCFG10_IOCURR_M 0x00000C00 -#define IOC_IOCFG10_IOCURR_S 10 -#define IOC_IOCFG10_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG10_IOCURR_4MA 0x00000400 -#define IOC_IOCFG10_IOCURR_2MA 0x00000000 +#define IOC_IOCFG10_IOCURR_W 2 +#define IOC_IOCFG10_IOCURR_M 0x00000C00 +#define IOC_IOCFG10_IOCURR_S 10 +#define IOC_IOCFG10_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG10_IOCURR_4MA 0x00000400 +#define IOC_IOCFG10_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -3332,13 +3332,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG10_IOSTR_W 2 -#define IOC_IOCFG10_IOSTR_M 0x00000300 -#define IOC_IOCFG10_IOSTR_S 8 -#define IOC_IOCFG10_IOSTR_MAX 0x00000300 -#define IOC_IOCFG10_IOSTR_MED 0x00000200 -#define IOC_IOCFG10_IOSTR_MIN 0x00000100 -#define IOC_IOCFG10_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG10_IOSTR_W 2 +#define IOC_IOCFG10_IOSTR_M 0x00000300 +#define IOC_IOCFG10_IOSTR_S 8 +#define IOC_IOCFG10_IOSTR_MAX 0x00000300 +#define IOC_IOCFG10_IOSTR_MED 0x00000200 +#define IOC_IOCFG10_IOSTR_MIN 0x00000100 +#define IOC_IOCFG10_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -3426,51 +3426,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG10_PORT_ID_W 6 -#define IOC_IOCFG10_PORT_ID_M 0x0000003F -#define IOC_IOCFG10_PORT_ID_S 0 -#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG10_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG10_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG10_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG10_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG10_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG10_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG10_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG10_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG10_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG10_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG10_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG10_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG10_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG10_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG10_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG10_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG10_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG10_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG10_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG10_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG10_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG10_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG10_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG10_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG10_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG10_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG10_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG10_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG10_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG10_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG10_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG10_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG10_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG10_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG10_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG10_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG10_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG10_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG10_PORT_ID_W 6 +#define IOC_IOCFG10_PORT_ID_M 0x0000003F +#define IOC_IOCFG10_PORT_ID_S 0 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG10_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG10_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG10_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG10_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG10_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG10_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG10_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG10_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG10_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG10_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG10_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG10_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG10_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG10_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG10_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG10_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG10_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG10_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG10_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG10_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG10_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG10_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG10_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG10_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG10_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG10_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG10_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG10_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG10_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG10_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG10_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG10_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG10_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG10_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG10_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -3481,10 +3481,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG11_HYST_EN 0x40000000 -#define IOC_IOCFG11_HYST_EN_BITN 30 -#define IOC_IOCFG11_HYST_EN_M 0x40000000 -#define IOC_IOCFG11_HYST_EN_S 30 +#define IOC_IOCFG11_HYST_EN 0x40000000 +#define IOC_IOCFG11_HYST_EN_BITN 30 +#define IOC_IOCFG11_HYST_EN_M 0x40000000 +#define IOC_IOCFG11_HYST_EN_S 30 // Field: [29] IE // @@ -3493,10 +3493,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG11_IE 0x20000000 -#define IOC_IOCFG11_IE_BITN 29 -#define IOC_IOCFG11_IE_M 0x20000000 -#define IOC_IOCFG11_IE_S 29 +#define IOC_IOCFG11_IE 0x20000000 +#define IOC_IOCFG11_IE_BITN 29 +#define IOC_IOCFG11_IE_M 0x20000000 +#define IOC_IOCFG11_IE_S 29 // Field: [28:27] WU_CFG // @@ -3518,9 +3518,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG11_WU_CFG_W 2 -#define IOC_IOCFG11_WU_CFG_M 0x18000000 -#define IOC_IOCFG11_WU_CFG_S 27 +#define IOC_IOCFG11_WU_CFG_W 2 +#define IOC_IOCFG11_WU_CFG_M 0x18000000 +#define IOC_IOCFG11_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -3541,25 +3541,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG11_IOMODE_W 3 -#define IOC_IOCFG11_IOMODE_M 0x07000000 -#define IOC_IOCFG11_IOMODE_S 24 -#define IOC_IOCFG11_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG11_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG11_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG11_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG11_IOMODE_INV 0x01000000 -#define IOC_IOCFG11_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG11_IOMODE_W 3 +#define IOC_IOCFG11_IOMODE_M 0x07000000 +#define IOC_IOCFG11_IOMODE_S 24 +#define IOC_IOCFG11_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG11_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG11_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG11_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG11_IOMODE_INV 0x01000000 +#define IOC_IOCFG11_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG11_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG11_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG11_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG11_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG11_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG11_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG11_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG11_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -3569,13 +3569,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG11_EDGE_DET_W 2 -#define IOC_IOCFG11_EDGE_DET_M 0x00030000 -#define IOC_IOCFG11_EDGE_DET_S 16 -#define IOC_IOCFG11_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG11_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG11_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG11_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG11_EDGE_DET_W 2 +#define IOC_IOCFG11_EDGE_DET_M 0x00030000 +#define IOC_IOCFG11_EDGE_DET_S 16 +#define IOC_IOCFG11_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG11_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG11_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG11_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -3584,21 +3584,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG11_PULL_CTL_W 2 -#define IOC_IOCFG11_PULL_CTL_M 0x00006000 -#define IOC_IOCFG11_PULL_CTL_S 13 -#define IOC_IOCFG11_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG11_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG11_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG11_PULL_CTL_W 2 +#define IOC_IOCFG11_PULL_CTL_M 0x00006000 +#define IOC_IOCFG11_PULL_CTL_S 13 +#define IOC_IOCFG11_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG11_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG11_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG11_SLEW_RED 0x00001000 -#define IOC_IOCFG11_SLEW_RED_BITN 12 -#define IOC_IOCFG11_SLEW_RED_M 0x00001000 -#define IOC_IOCFG11_SLEW_RED_S 12 +#define IOC_IOCFG11_SLEW_RED 0x00001000 +#define IOC_IOCFG11_SLEW_RED_BITN 12 +#define IOC_IOCFG11_SLEW_RED_M 0x00001000 +#define IOC_IOCFG11_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -3611,12 +3611,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG11_IOCURR_W 2 -#define IOC_IOCFG11_IOCURR_M 0x00000C00 -#define IOC_IOCFG11_IOCURR_S 10 -#define IOC_IOCFG11_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG11_IOCURR_4MA 0x00000400 -#define IOC_IOCFG11_IOCURR_2MA 0x00000000 +#define IOC_IOCFG11_IOCURR_W 2 +#define IOC_IOCFG11_IOCURR_M 0x00000C00 +#define IOC_IOCFG11_IOCURR_S 10 +#define IOC_IOCFG11_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG11_IOCURR_4MA 0x00000400 +#define IOC_IOCFG11_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -3635,13 +3635,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG11_IOSTR_W 2 -#define IOC_IOCFG11_IOSTR_M 0x00000300 -#define IOC_IOCFG11_IOSTR_S 8 -#define IOC_IOCFG11_IOSTR_MAX 0x00000300 -#define IOC_IOCFG11_IOSTR_MED 0x00000200 -#define IOC_IOCFG11_IOSTR_MIN 0x00000100 -#define IOC_IOCFG11_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG11_IOSTR_W 2 +#define IOC_IOCFG11_IOSTR_M 0x00000300 +#define IOC_IOCFG11_IOSTR_S 8 +#define IOC_IOCFG11_IOSTR_MAX 0x00000300 +#define IOC_IOCFG11_IOSTR_MED 0x00000200 +#define IOC_IOCFG11_IOSTR_MIN 0x00000100 +#define IOC_IOCFG11_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -3729,51 +3729,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG11_PORT_ID_W 6 -#define IOC_IOCFG11_PORT_ID_M 0x0000003F -#define IOC_IOCFG11_PORT_ID_S 0 -#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG11_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG11_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG11_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG11_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG11_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG11_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG11_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG11_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG11_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG11_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG11_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG11_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG11_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG11_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG11_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG11_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG11_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG11_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG11_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG11_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG11_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG11_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG11_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG11_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG11_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG11_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG11_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG11_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG11_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG11_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG11_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG11_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG11_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG11_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG11_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG11_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG11_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG11_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG11_PORT_ID_W 6 +#define IOC_IOCFG11_PORT_ID_M 0x0000003F +#define IOC_IOCFG11_PORT_ID_S 0 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG11_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG11_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG11_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG11_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG11_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG11_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG11_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG11_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG11_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG11_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG11_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG11_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG11_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG11_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG11_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG11_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG11_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG11_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG11_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG11_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG11_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG11_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG11_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG11_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG11_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG11_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG11_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG11_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG11_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG11_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG11_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG11_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG11_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG11_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG11_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -3784,10 +3784,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG12_HYST_EN 0x40000000 -#define IOC_IOCFG12_HYST_EN_BITN 30 -#define IOC_IOCFG12_HYST_EN_M 0x40000000 -#define IOC_IOCFG12_HYST_EN_S 30 +#define IOC_IOCFG12_HYST_EN 0x40000000 +#define IOC_IOCFG12_HYST_EN_BITN 30 +#define IOC_IOCFG12_HYST_EN_M 0x40000000 +#define IOC_IOCFG12_HYST_EN_S 30 // Field: [29] IE // @@ -3796,10 +3796,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG12_IE 0x20000000 -#define IOC_IOCFG12_IE_BITN 29 -#define IOC_IOCFG12_IE_M 0x20000000 -#define IOC_IOCFG12_IE_S 29 +#define IOC_IOCFG12_IE 0x20000000 +#define IOC_IOCFG12_IE_BITN 29 +#define IOC_IOCFG12_IE_M 0x20000000 +#define IOC_IOCFG12_IE_S 29 // Field: [28:27] WU_CFG // @@ -3821,9 +3821,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG12_WU_CFG_W 2 -#define IOC_IOCFG12_WU_CFG_M 0x18000000 -#define IOC_IOCFG12_WU_CFG_S 27 +#define IOC_IOCFG12_WU_CFG_W 2 +#define IOC_IOCFG12_WU_CFG_M 0x18000000 +#define IOC_IOCFG12_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -3844,25 +3844,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG12_IOMODE_W 3 -#define IOC_IOCFG12_IOMODE_M 0x07000000 -#define IOC_IOCFG12_IOMODE_S 24 -#define IOC_IOCFG12_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG12_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG12_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG12_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG12_IOMODE_INV 0x01000000 -#define IOC_IOCFG12_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG12_IOMODE_W 3 +#define IOC_IOCFG12_IOMODE_M 0x07000000 +#define IOC_IOCFG12_IOMODE_S 24 +#define IOC_IOCFG12_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG12_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG12_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG12_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG12_IOMODE_INV 0x01000000 +#define IOC_IOCFG12_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG12_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG12_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG12_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG12_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG12_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG12_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG12_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG12_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -3872,13 +3872,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG12_EDGE_DET_W 2 -#define IOC_IOCFG12_EDGE_DET_M 0x00030000 -#define IOC_IOCFG12_EDGE_DET_S 16 -#define IOC_IOCFG12_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG12_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG12_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG12_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG12_EDGE_DET_W 2 +#define IOC_IOCFG12_EDGE_DET_M 0x00030000 +#define IOC_IOCFG12_EDGE_DET_S 16 +#define IOC_IOCFG12_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG12_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG12_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG12_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -3887,21 +3887,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG12_PULL_CTL_W 2 -#define IOC_IOCFG12_PULL_CTL_M 0x00006000 -#define IOC_IOCFG12_PULL_CTL_S 13 -#define IOC_IOCFG12_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG12_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG12_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG12_PULL_CTL_W 2 +#define IOC_IOCFG12_PULL_CTL_M 0x00006000 +#define IOC_IOCFG12_PULL_CTL_S 13 +#define IOC_IOCFG12_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG12_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG12_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG12_SLEW_RED 0x00001000 -#define IOC_IOCFG12_SLEW_RED_BITN 12 -#define IOC_IOCFG12_SLEW_RED_M 0x00001000 -#define IOC_IOCFG12_SLEW_RED_S 12 +#define IOC_IOCFG12_SLEW_RED 0x00001000 +#define IOC_IOCFG12_SLEW_RED_BITN 12 +#define IOC_IOCFG12_SLEW_RED_M 0x00001000 +#define IOC_IOCFG12_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -3914,12 +3914,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG12_IOCURR_W 2 -#define IOC_IOCFG12_IOCURR_M 0x00000C00 -#define IOC_IOCFG12_IOCURR_S 10 -#define IOC_IOCFG12_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG12_IOCURR_4MA 0x00000400 -#define IOC_IOCFG12_IOCURR_2MA 0x00000000 +#define IOC_IOCFG12_IOCURR_W 2 +#define IOC_IOCFG12_IOCURR_M 0x00000C00 +#define IOC_IOCFG12_IOCURR_S 10 +#define IOC_IOCFG12_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG12_IOCURR_4MA 0x00000400 +#define IOC_IOCFG12_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -3938,13 +3938,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG12_IOSTR_W 2 -#define IOC_IOCFG12_IOSTR_M 0x00000300 -#define IOC_IOCFG12_IOSTR_S 8 -#define IOC_IOCFG12_IOSTR_MAX 0x00000300 -#define IOC_IOCFG12_IOSTR_MED 0x00000200 -#define IOC_IOCFG12_IOSTR_MIN 0x00000100 -#define IOC_IOCFG12_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG12_IOSTR_W 2 +#define IOC_IOCFG12_IOSTR_M 0x00000300 +#define IOC_IOCFG12_IOSTR_S 8 +#define IOC_IOCFG12_IOSTR_MAX 0x00000300 +#define IOC_IOCFG12_IOSTR_MED 0x00000200 +#define IOC_IOCFG12_IOSTR_MIN 0x00000100 +#define IOC_IOCFG12_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -4032,51 +4032,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG12_PORT_ID_W 6 -#define IOC_IOCFG12_PORT_ID_M 0x0000003F -#define IOC_IOCFG12_PORT_ID_S 0 -#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG12_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG12_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG12_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG12_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG12_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG12_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG12_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG12_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG12_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG12_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG12_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG12_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG12_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG12_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG12_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG12_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG12_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG12_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG12_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG12_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG12_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG12_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG12_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG12_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG12_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG12_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG12_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG12_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG12_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG12_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG12_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG12_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG12_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG12_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG12_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG12_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG12_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG12_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG12_PORT_ID_W 6 +#define IOC_IOCFG12_PORT_ID_M 0x0000003F +#define IOC_IOCFG12_PORT_ID_S 0 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG12_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG12_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG12_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG12_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG12_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG12_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG12_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG12_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG12_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG12_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG12_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG12_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG12_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG12_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG12_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG12_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG12_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG12_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG12_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG12_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG12_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG12_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG12_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG12_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG12_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG12_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG12_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG12_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG12_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG12_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG12_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG12_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG12_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG12_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG12_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -4087,10 +4087,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG13_HYST_EN 0x40000000 -#define IOC_IOCFG13_HYST_EN_BITN 30 -#define IOC_IOCFG13_HYST_EN_M 0x40000000 -#define IOC_IOCFG13_HYST_EN_S 30 +#define IOC_IOCFG13_HYST_EN 0x40000000 +#define IOC_IOCFG13_HYST_EN_BITN 30 +#define IOC_IOCFG13_HYST_EN_M 0x40000000 +#define IOC_IOCFG13_HYST_EN_S 30 // Field: [29] IE // @@ -4099,10 +4099,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG13_IE 0x20000000 -#define IOC_IOCFG13_IE_BITN 29 -#define IOC_IOCFG13_IE_M 0x20000000 -#define IOC_IOCFG13_IE_S 29 +#define IOC_IOCFG13_IE 0x20000000 +#define IOC_IOCFG13_IE_BITN 29 +#define IOC_IOCFG13_IE_M 0x20000000 +#define IOC_IOCFG13_IE_S 29 // Field: [28:27] WU_CFG // @@ -4124,9 +4124,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG13_WU_CFG_W 2 -#define IOC_IOCFG13_WU_CFG_M 0x18000000 -#define IOC_IOCFG13_WU_CFG_S 27 +#define IOC_IOCFG13_WU_CFG_W 2 +#define IOC_IOCFG13_WU_CFG_M 0x18000000 +#define IOC_IOCFG13_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -4147,25 +4147,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG13_IOMODE_W 3 -#define IOC_IOCFG13_IOMODE_M 0x07000000 -#define IOC_IOCFG13_IOMODE_S 24 -#define IOC_IOCFG13_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG13_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG13_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG13_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG13_IOMODE_INV 0x01000000 -#define IOC_IOCFG13_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG13_IOMODE_W 3 +#define IOC_IOCFG13_IOMODE_M 0x07000000 +#define IOC_IOCFG13_IOMODE_S 24 +#define IOC_IOCFG13_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG13_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG13_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG13_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG13_IOMODE_INV 0x01000000 +#define IOC_IOCFG13_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG13_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG13_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG13_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG13_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG13_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG13_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG13_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG13_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -4175,13 +4175,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG13_EDGE_DET_W 2 -#define IOC_IOCFG13_EDGE_DET_M 0x00030000 -#define IOC_IOCFG13_EDGE_DET_S 16 -#define IOC_IOCFG13_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG13_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG13_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG13_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG13_EDGE_DET_W 2 +#define IOC_IOCFG13_EDGE_DET_M 0x00030000 +#define IOC_IOCFG13_EDGE_DET_S 16 +#define IOC_IOCFG13_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG13_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG13_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG13_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -4190,21 +4190,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG13_PULL_CTL_W 2 -#define IOC_IOCFG13_PULL_CTL_M 0x00006000 -#define IOC_IOCFG13_PULL_CTL_S 13 -#define IOC_IOCFG13_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG13_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG13_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG13_PULL_CTL_W 2 +#define IOC_IOCFG13_PULL_CTL_M 0x00006000 +#define IOC_IOCFG13_PULL_CTL_S 13 +#define IOC_IOCFG13_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG13_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG13_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG13_SLEW_RED 0x00001000 -#define IOC_IOCFG13_SLEW_RED_BITN 12 -#define IOC_IOCFG13_SLEW_RED_M 0x00001000 -#define IOC_IOCFG13_SLEW_RED_S 12 +#define IOC_IOCFG13_SLEW_RED 0x00001000 +#define IOC_IOCFG13_SLEW_RED_BITN 12 +#define IOC_IOCFG13_SLEW_RED_M 0x00001000 +#define IOC_IOCFG13_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -4217,12 +4217,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG13_IOCURR_W 2 -#define IOC_IOCFG13_IOCURR_M 0x00000C00 -#define IOC_IOCFG13_IOCURR_S 10 -#define IOC_IOCFG13_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG13_IOCURR_4MA 0x00000400 -#define IOC_IOCFG13_IOCURR_2MA 0x00000000 +#define IOC_IOCFG13_IOCURR_W 2 +#define IOC_IOCFG13_IOCURR_M 0x00000C00 +#define IOC_IOCFG13_IOCURR_S 10 +#define IOC_IOCFG13_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG13_IOCURR_4MA 0x00000400 +#define IOC_IOCFG13_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -4241,13 +4241,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG13_IOSTR_W 2 -#define IOC_IOCFG13_IOSTR_M 0x00000300 -#define IOC_IOCFG13_IOSTR_S 8 -#define IOC_IOCFG13_IOSTR_MAX 0x00000300 -#define IOC_IOCFG13_IOSTR_MED 0x00000200 -#define IOC_IOCFG13_IOSTR_MIN 0x00000100 -#define IOC_IOCFG13_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG13_IOSTR_W 2 +#define IOC_IOCFG13_IOSTR_M 0x00000300 +#define IOC_IOCFG13_IOSTR_S 8 +#define IOC_IOCFG13_IOSTR_MAX 0x00000300 +#define IOC_IOCFG13_IOSTR_MED 0x00000200 +#define IOC_IOCFG13_IOSTR_MIN 0x00000100 +#define IOC_IOCFG13_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -4335,51 +4335,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG13_PORT_ID_W 6 -#define IOC_IOCFG13_PORT_ID_M 0x0000003F -#define IOC_IOCFG13_PORT_ID_S 0 -#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG13_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG13_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG13_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG13_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG13_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG13_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG13_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG13_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG13_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG13_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG13_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG13_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG13_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG13_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG13_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG13_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG13_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG13_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG13_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG13_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG13_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG13_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG13_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG13_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG13_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG13_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG13_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG13_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG13_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG13_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG13_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG13_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG13_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG13_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG13_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG13_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG13_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG13_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG13_PORT_ID_W 6 +#define IOC_IOCFG13_PORT_ID_M 0x0000003F +#define IOC_IOCFG13_PORT_ID_S 0 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG13_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG13_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG13_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG13_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG13_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG13_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG13_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG13_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG13_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG13_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG13_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG13_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG13_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG13_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG13_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG13_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG13_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG13_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG13_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG13_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG13_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG13_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG13_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG13_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG13_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG13_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG13_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG13_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG13_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG13_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG13_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG13_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG13_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG13_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG13_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -4390,10 +4390,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG14_HYST_EN 0x40000000 -#define IOC_IOCFG14_HYST_EN_BITN 30 -#define IOC_IOCFG14_HYST_EN_M 0x40000000 -#define IOC_IOCFG14_HYST_EN_S 30 +#define IOC_IOCFG14_HYST_EN 0x40000000 +#define IOC_IOCFG14_HYST_EN_BITN 30 +#define IOC_IOCFG14_HYST_EN_M 0x40000000 +#define IOC_IOCFG14_HYST_EN_S 30 // Field: [29] IE // @@ -4402,10 +4402,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG14_IE 0x20000000 -#define IOC_IOCFG14_IE_BITN 29 -#define IOC_IOCFG14_IE_M 0x20000000 -#define IOC_IOCFG14_IE_S 29 +#define IOC_IOCFG14_IE 0x20000000 +#define IOC_IOCFG14_IE_BITN 29 +#define IOC_IOCFG14_IE_M 0x20000000 +#define IOC_IOCFG14_IE_S 29 // Field: [28:27] WU_CFG // @@ -4427,9 +4427,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG14_WU_CFG_W 2 -#define IOC_IOCFG14_WU_CFG_M 0x18000000 -#define IOC_IOCFG14_WU_CFG_S 27 +#define IOC_IOCFG14_WU_CFG_W 2 +#define IOC_IOCFG14_WU_CFG_M 0x18000000 +#define IOC_IOCFG14_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -4450,25 +4450,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG14_IOMODE_W 3 -#define IOC_IOCFG14_IOMODE_M 0x07000000 -#define IOC_IOCFG14_IOMODE_S 24 -#define IOC_IOCFG14_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG14_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG14_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG14_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG14_IOMODE_INV 0x01000000 -#define IOC_IOCFG14_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG14_IOMODE_W 3 +#define IOC_IOCFG14_IOMODE_M 0x07000000 +#define IOC_IOCFG14_IOMODE_S 24 +#define IOC_IOCFG14_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG14_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG14_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG14_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG14_IOMODE_INV 0x01000000 +#define IOC_IOCFG14_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG14_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG14_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG14_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG14_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG14_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG14_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG14_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG14_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -4478,13 +4478,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG14_EDGE_DET_W 2 -#define IOC_IOCFG14_EDGE_DET_M 0x00030000 -#define IOC_IOCFG14_EDGE_DET_S 16 -#define IOC_IOCFG14_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG14_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG14_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG14_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG14_EDGE_DET_W 2 +#define IOC_IOCFG14_EDGE_DET_M 0x00030000 +#define IOC_IOCFG14_EDGE_DET_S 16 +#define IOC_IOCFG14_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG14_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG14_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG14_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -4493,21 +4493,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG14_PULL_CTL_W 2 -#define IOC_IOCFG14_PULL_CTL_M 0x00006000 -#define IOC_IOCFG14_PULL_CTL_S 13 -#define IOC_IOCFG14_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG14_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG14_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG14_PULL_CTL_W 2 +#define IOC_IOCFG14_PULL_CTL_M 0x00006000 +#define IOC_IOCFG14_PULL_CTL_S 13 +#define IOC_IOCFG14_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG14_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG14_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG14_SLEW_RED 0x00001000 -#define IOC_IOCFG14_SLEW_RED_BITN 12 -#define IOC_IOCFG14_SLEW_RED_M 0x00001000 -#define IOC_IOCFG14_SLEW_RED_S 12 +#define IOC_IOCFG14_SLEW_RED 0x00001000 +#define IOC_IOCFG14_SLEW_RED_BITN 12 +#define IOC_IOCFG14_SLEW_RED_M 0x00001000 +#define IOC_IOCFG14_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -4520,12 +4520,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG14_IOCURR_W 2 -#define IOC_IOCFG14_IOCURR_M 0x00000C00 -#define IOC_IOCFG14_IOCURR_S 10 -#define IOC_IOCFG14_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG14_IOCURR_4MA 0x00000400 -#define IOC_IOCFG14_IOCURR_2MA 0x00000000 +#define IOC_IOCFG14_IOCURR_W 2 +#define IOC_IOCFG14_IOCURR_M 0x00000C00 +#define IOC_IOCFG14_IOCURR_S 10 +#define IOC_IOCFG14_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG14_IOCURR_4MA 0x00000400 +#define IOC_IOCFG14_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -4544,13 +4544,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG14_IOSTR_W 2 -#define IOC_IOCFG14_IOSTR_M 0x00000300 -#define IOC_IOCFG14_IOSTR_S 8 -#define IOC_IOCFG14_IOSTR_MAX 0x00000300 -#define IOC_IOCFG14_IOSTR_MED 0x00000200 -#define IOC_IOCFG14_IOSTR_MIN 0x00000100 -#define IOC_IOCFG14_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG14_IOSTR_W 2 +#define IOC_IOCFG14_IOSTR_M 0x00000300 +#define IOC_IOCFG14_IOSTR_S 8 +#define IOC_IOCFG14_IOSTR_MAX 0x00000300 +#define IOC_IOCFG14_IOSTR_MED 0x00000200 +#define IOC_IOCFG14_IOSTR_MIN 0x00000100 +#define IOC_IOCFG14_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -4638,51 +4638,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG14_PORT_ID_W 6 -#define IOC_IOCFG14_PORT_ID_M 0x0000003F -#define IOC_IOCFG14_PORT_ID_S 0 -#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG14_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG14_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG14_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG14_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG14_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG14_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG14_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG14_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG14_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG14_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG14_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG14_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG14_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG14_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG14_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG14_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG14_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG14_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG14_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG14_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG14_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG14_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG14_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG14_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG14_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG14_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG14_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG14_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG14_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG14_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG14_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG14_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG14_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG14_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG14_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG14_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG14_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG14_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG14_PORT_ID_W 6 +#define IOC_IOCFG14_PORT_ID_M 0x0000003F +#define IOC_IOCFG14_PORT_ID_S 0 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG14_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG14_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG14_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG14_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG14_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG14_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG14_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG14_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG14_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG14_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG14_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG14_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG14_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG14_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG14_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG14_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG14_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG14_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG14_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG14_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG14_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG14_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG14_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG14_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG14_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG14_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG14_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG14_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG14_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG14_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG14_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG14_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG14_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG14_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG14_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -4693,10 +4693,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG15_HYST_EN 0x40000000 -#define IOC_IOCFG15_HYST_EN_BITN 30 -#define IOC_IOCFG15_HYST_EN_M 0x40000000 -#define IOC_IOCFG15_HYST_EN_S 30 +#define IOC_IOCFG15_HYST_EN 0x40000000 +#define IOC_IOCFG15_HYST_EN_BITN 30 +#define IOC_IOCFG15_HYST_EN_M 0x40000000 +#define IOC_IOCFG15_HYST_EN_S 30 // Field: [29] IE // @@ -4705,10 +4705,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG15_IE 0x20000000 -#define IOC_IOCFG15_IE_BITN 29 -#define IOC_IOCFG15_IE_M 0x20000000 -#define IOC_IOCFG15_IE_S 29 +#define IOC_IOCFG15_IE 0x20000000 +#define IOC_IOCFG15_IE_BITN 29 +#define IOC_IOCFG15_IE_M 0x20000000 +#define IOC_IOCFG15_IE_S 29 // Field: [28:27] WU_CFG // @@ -4730,9 +4730,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG15_WU_CFG_W 2 -#define IOC_IOCFG15_WU_CFG_M 0x18000000 -#define IOC_IOCFG15_WU_CFG_S 27 +#define IOC_IOCFG15_WU_CFG_W 2 +#define IOC_IOCFG15_WU_CFG_M 0x18000000 +#define IOC_IOCFG15_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -4753,25 +4753,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG15_IOMODE_W 3 -#define IOC_IOCFG15_IOMODE_M 0x07000000 -#define IOC_IOCFG15_IOMODE_S 24 -#define IOC_IOCFG15_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG15_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG15_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG15_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG15_IOMODE_INV 0x01000000 -#define IOC_IOCFG15_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG15_IOMODE_W 3 +#define IOC_IOCFG15_IOMODE_M 0x07000000 +#define IOC_IOCFG15_IOMODE_S 24 +#define IOC_IOCFG15_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG15_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG15_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG15_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG15_IOMODE_INV 0x01000000 +#define IOC_IOCFG15_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG15_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG15_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG15_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG15_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG15_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG15_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG15_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG15_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -4781,13 +4781,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG15_EDGE_DET_W 2 -#define IOC_IOCFG15_EDGE_DET_M 0x00030000 -#define IOC_IOCFG15_EDGE_DET_S 16 -#define IOC_IOCFG15_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG15_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG15_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG15_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG15_EDGE_DET_W 2 +#define IOC_IOCFG15_EDGE_DET_M 0x00030000 +#define IOC_IOCFG15_EDGE_DET_S 16 +#define IOC_IOCFG15_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG15_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG15_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG15_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -4796,21 +4796,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG15_PULL_CTL_W 2 -#define IOC_IOCFG15_PULL_CTL_M 0x00006000 -#define IOC_IOCFG15_PULL_CTL_S 13 -#define IOC_IOCFG15_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG15_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG15_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG15_PULL_CTL_W 2 +#define IOC_IOCFG15_PULL_CTL_M 0x00006000 +#define IOC_IOCFG15_PULL_CTL_S 13 +#define IOC_IOCFG15_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG15_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG15_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG15_SLEW_RED 0x00001000 -#define IOC_IOCFG15_SLEW_RED_BITN 12 -#define IOC_IOCFG15_SLEW_RED_M 0x00001000 -#define IOC_IOCFG15_SLEW_RED_S 12 +#define IOC_IOCFG15_SLEW_RED 0x00001000 +#define IOC_IOCFG15_SLEW_RED_BITN 12 +#define IOC_IOCFG15_SLEW_RED_M 0x00001000 +#define IOC_IOCFG15_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -4823,12 +4823,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG15_IOCURR_W 2 -#define IOC_IOCFG15_IOCURR_M 0x00000C00 -#define IOC_IOCFG15_IOCURR_S 10 -#define IOC_IOCFG15_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG15_IOCURR_4MA 0x00000400 -#define IOC_IOCFG15_IOCURR_2MA 0x00000000 +#define IOC_IOCFG15_IOCURR_W 2 +#define IOC_IOCFG15_IOCURR_M 0x00000C00 +#define IOC_IOCFG15_IOCURR_S 10 +#define IOC_IOCFG15_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG15_IOCURR_4MA 0x00000400 +#define IOC_IOCFG15_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -4847,13 +4847,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG15_IOSTR_W 2 -#define IOC_IOCFG15_IOSTR_M 0x00000300 -#define IOC_IOCFG15_IOSTR_S 8 -#define IOC_IOCFG15_IOSTR_MAX 0x00000300 -#define IOC_IOCFG15_IOSTR_MED 0x00000200 -#define IOC_IOCFG15_IOSTR_MIN 0x00000100 -#define IOC_IOCFG15_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG15_IOSTR_W 2 +#define IOC_IOCFG15_IOSTR_M 0x00000300 +#define IOC_IOCFG15_IOSTR_S 8 +#define IOC_IOCFG15_IOSTR_MAX 0x00000300 +#define IOC_IOCFG15_IOSTR_MED 0x00000200 +#define IOC_IOCFG15_IOSTR_MIN 0x00000100 +#define IOC_IOCFG15_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -4941,51 +4941,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG15_PORT_ID_W 6 -#define IOC_IOCFG15_PORT_ID_M 0x0000003F -#define IOC_IOCFG15_PORT_ID_S 0 -#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG15_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG15_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG15_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG15_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG15_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG15_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG15_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG15_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG15_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG15_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG15_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG15_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG15_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG15_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG15_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG15_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG15_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG15_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG15_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG15_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG15_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG15_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG15_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG15_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG15_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG15_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG15_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG15_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG15_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG15_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG15_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG15_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG15_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG15_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG15_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG15_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG15_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG15_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG15_PORT_ID_W 6 +#define IOC_IOCFG15_PORT_ID_M 0x0000003F +#define IOC_IOCFG15_PORT_ID_S 0 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG15_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG15_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG15_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG15_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG15_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG15_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG15_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG15_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG15_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG15_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG15_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG15_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG15_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG15_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG15_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG15_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG15_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG15_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG15_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG15_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG15_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG15_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG15_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG15_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG15_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG15_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG15_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG15_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG15_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG15_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG15_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG15_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG15_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG15_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG15_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -4996,10 +4996,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG16_HYST_EN 0x40000000 -#define IOC_IOCFG16_HYST_EN_BITN 30 -#define IOC_IOCFG16_HYST_EN_M 0x40000000 -#define IOC_IOCFG16_HYST_EN_S 30 +#define IOC_IOCFG16_HYST_EN 0x40000000 +#define IOC_IOCFG16_HYST_EN_BITN 30 +#define IOC_IOCFG16_HYST_EN_M 0x40000000 +#define IOC_IOCFG16_HYST_EN_S 30 // Field: [29] IE // @@ -5008,10 +5008,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG16_IE 0x20000000 -#define IOC_IOCFG16_IE_BITN 29 -#define IOC_IOCFG16_IE_M 0x20000000 -#define IOC_IOCFG16_IE_S 29 +#define IOC_IOCFG16_IE 0x20000000 +#define IOC_IOCFG16_IE_BITN 29 +#define IOC_IOCFG16_IE_M 0x20000000 +#define IOC_IOCFG16_IE_S 29 // Field: [28:27] WU_CFG // @@ -5033,9 +5033,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG16_WU_CFG_W 2 -#define IOC_IOCFG16_WU_CFG_M 0x18000000 -#define IOC_IOCFG16_WU_CFG_S 27 +#define IOC_IOCFG16_WU_CFG_W 2 +#define IOC_IOCFG16_WU_CFG_M 0x18000000 +#define IOC_IOCFG16_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -5056,25 +5056,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG16_IOMODE_W 3 -#define IOC_IOCFG16_IOMODE_M 0x07000000 -#define IOC_IOCFG16_IOMODE_S 24 -#define IOC_IOCFG16_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG16_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG16_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG16_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG16_IOMODE_INV 0x01000000 -#define IOC_IOCFG16_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG16_IOMODE_W 3 +#define IOC_IOCFG16_IOMODE_M 0x07000000 +#define IOC_IOCFG16_IOMODE_S 24 +#define IOC_IOCFG16_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG16_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG16_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG16_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG16_IOMODE_INV 0x01000000 +#define IOC_IOCFG16_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG16_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG16_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG16_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG16_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG16_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG16_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG16_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG16_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -5084,13 +5084,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG16_EDGE_DET_W 2 -#define IOC_IOCFG16_EDGE_DET_M 0x00030000 -#define IOC_IOCFG16_EDGE_DET_S 16 -#define IOC_IOCFG16_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG16_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG16_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG16_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG16_EDGE_DET_W 2 +#define IOC_IOCFG16_EDGE_DET_M 0x00030000 +#define IOC_IOCFG16_EDGE_DET_S 16 +#define IOC_IOCFG16_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG16_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG16_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG16_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -5099,21 +5099,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG16_PULL_CTL_W 2 -#define IOC_IOCFG16_PULL_CTL_M 0x00006000 -#define IOC_IOCFG16_PULL_CTL_S 13 -#define IOC_IOCFG16_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG16_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG16_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG16_PULL_CTL_W 2 +#define IOC_IOCFG16_PULL_CTL_M 0x00006000 +#define IOC_IOCFG16_PULL_CTL_S 13 +#define IOC_IOCFG16_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG16_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG16_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG16_SLEW_RED 0x00001000 -#define IOC_IOCFG16_SLEW_RED_BITN 12 -#define IOC_IOCFG16_SLEW_RED_M 0x00001000 -#define IOC_IOCFG16_SLEW_RED_S 12 +#define IOC_IOCFG16_SLEW_RED 0x00001000 +#define IOC_IOCFG16_SLEW_RED_BITN 12 +#define IOC_IOCFG16_SLEW_RED_M 0x00001000 +#define IOC_IOCFG16_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -5126,12 +5126,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG16_IOCURR_W 2 -#define IOC_IOCFG16_IOCURR_M 0x00000C00 -#define IOC_IOCFG16_IOCURR_S 10 -#define IOC_IOCFG16_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG16_IOCURR_4MA 0x00000400 -#define IOC_IOCFG16_IOCURR_2MA 0x00000000 +#define IOC_IOCFG16_IOCURR_W 2 +#define IOC_IOCFG16_IOCURR_M 0x00000C00 +#define IOC_IOCFG16_IOCURR_S 10 +#define IOC_IOCFG16_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG16_IOCURR_4MA 0x00000400 +#define IOC_IOCFG16_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -5150,13 +5150,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG16_IOSTR_W 2 -#define IOC_IOCFG16_IOSTR_M 0x00000300 -#define IOC_IOCFG16_IOSTR_S 8 -#define IOC_IOCFG16_IOSTR_MAX 0x00000300 -#define IOC_IOCFG16_IOSTR_MED 0x00000200 -#define IOC_IOCFG16_IOSTR_MIN 0x00000100 -#define IOC_IOCFG16_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG16_IOSTR_W 2 +#define IOC_IOCFG16_IOSTR_M 0x00000300 +#define IOC_IOCFG16_IOSTR_S 8 +#define IOC_IOCFG16_IOSTR_MAX 0x00000300 +#define IOC_IOCFG16_IOSTR_MED 0x00000200 +#define IOC_IOCFG16_IOSTR_MIN 0x00000100 +#define IOC_IOCFG16_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -5244,51 +5244,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG16_PORT_ID_W 6 -#define IOC_IOCFG16_PORT_ID_M 0x0000003F -#define IOC_IOCFG16_PORT_ID_S 0 -#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG16_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG16_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG16_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG16_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG16_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG16_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG16_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG16_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG16_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG16_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG16_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG16_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG16_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG16_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG16_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG16_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG16_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG16_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG16_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG16_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG16_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG16_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG16_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG16_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG16_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG16_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG16_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG16_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG16_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG16_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG16_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG16_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG16_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG16_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG16_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG16_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG16_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG16_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG16_PORT_ID_W 6 +#define IOC_IOCFG16_PORT_ID_M 0x0000003F +#define IOC_IOCFG16_PORT_ID_S 0 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG16_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG16_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG16_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG16_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG16_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG16_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG16_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG16_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG16_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG16_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG16_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG16_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG16_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG16_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG16_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG16_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG16_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG16_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG16_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG16_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG16_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG16_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG16_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG16_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG16_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG16_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG16_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG16_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG16_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG16_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG16_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG16_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG16_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG16_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG16_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -5299,10 +5299,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG17_HYST_EN 0x40000000 -#define IOC_IOCFG17_HYST_EN_BITN 30 -#define IOC_IOCFG17_HYST_EN_M 0x40000000 -#define IOC_IOCFG17_HYST_EN_S 30 +#define IOC_IOCFG17_HYST_EN 0x40000000 +#define IOC_IOCFG17_HYST_EN_BITN 30 +#define IOC_IOCFG17_HYST_EN_M 0x40000000 +#define IOC_IOCFG17_HYST_EN_S 30 // Field: [29] IE // @@ -5311,10 +5311,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG17_IE 0x20000000 -#define IOC_IOCFG17_IE_BITN 29 -#define IOC_IOCFG17_IE_M 0x20000000 -#define IOC_IOCFG17_IE_S 29 +#define IOC_IOCFG17_IE 0x20000000 +#define IOC_IOCFG17_IE_BITN 29 +#define IOC_IOCFG17_IE_M 0x20000000 +#define IOC_IOCFG17_IE_S 29 // Field: [28:27] WU_CFG // @@ -5336,9 +5336,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG17_WU_CFG_W 2 -#define IOC_IOCFG17_WU_CFG_M 0x18000000 -#define IOC_IOCFG17_WU_CFG_S 27 +#define IOC_IOCFG17_WU_CFG_W 2 +#define IOC_IOCFG17_WU_CFG_M 0x18000000 +#define IOC_IOCFG17_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -5359,25 +5359,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG17_IOMODE_W 3 -#define IOC_IOCFG17_IOMODE_M 0x07000000 -#define IOC_IOCFG17_IOMODE_S 24 -#define IOC_IOCFG17_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG17_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG17_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG17_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG17_IOMODE_INV 0x01000000 -#define IOC_IOCFG17_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG17_IOMODE_W 3 +#define IOC_IOCFG17_IOMODE_M 0x07000000 +#define IOC_IOCFG17_IOMODE_S 24 +#define IOC_IOCFG17_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG17_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG17_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG17_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG17_IOMODE_INV 0x01000000 +#define IOC_IOCFG17_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG17_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG17_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG17_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG17_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG17_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG17_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG17_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG17_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -5387,13 +5387,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG17_EDGE_DET_W 2 -#define IOC_IOCFG17_EDGE_DET_M 0x00030000 -#define IOC_IOCFG17_EDGE_DET_S 16 -#define IOC_IOCFG17_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG17_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG17_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG17_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG17_EDGE_DET_W 2 +#define IOC_IOCFG17_EDGE_DET_M 0x00030000 +#define IOC_IOCFG17_EDGE_DET_S 16 +#define IOC_IOCFG17_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG17_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG17_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG17_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -5402,21 +5402,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG17_PULL_CTL_W 2 -#define IOC_IOCFG17_PULL_CTL_M 0x00006000 -#define IOC_IOCFG17_PULL_CTL_S 13 -#define IOC_IOCFG17_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG17_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG17_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG17_PULL_CTL_W 2 +#define IOC_IOCFG17_PULL_CTL_M 0x00006000 +#define IOC_IOCFG17_PULL_CTL_S 13 +#define IOC_IOCFG17_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG17_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG17_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG17_SLEW_RED 0x00001000 -#define IOC_IOCFG17_SLEW_RED_BITN 12 -#define IOC_IOCFG17_SLEW_RED_M 0x00001000 -#define IOC_IOCFG17_SLEW_RED_S 12 +#define IOC_IOCFG17_SLEW_RED 0x00001000 +#define IOC_IOCFG17_SLEW_RED_BITN 12 +#define IOC_IOCFG17_SLEW_RED_M 0x00001000 +#define IOC_IOCFG17_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -5429,12 +5429,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG17_IOCURR_W 2 -#define IOC_IOCFG17_IOCURR_M 0x00000C00 -#define IOC_IOCFG17_IOCURR_S 10 -#define IOC_IOCFG17_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG17_IOCURR_4MA 0x00000400 -#define IOC_IOCFG17_IOCURR_2MA 0x00000000 +#define IOC_IOCFG17_IOCURR_W 2 +#define IOC_IOCFG17_IOCURR_M 0x00000C00 +#define IOC_IOCFG17_IOCURR_S 10 +#define IOC_IOCFG17_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG17_IOCURR_4MA 0x00000400 +#define IOC_IOCFG17_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -5453,13 +5453,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG17_IOSTR_W 2 -#define IOC_IOCFG17_IOSTR_M 0x00000300 -#define IOC_IOCFG17_IOSTR_S 8 -#define IOC_IOCFG17_IOSTR_MAX 0x00000300 -#define IOC_IOCFG17_IOSTR_MED 0x00000200 -#define IOC_IOCFG17_IOSTR_MIN 0x00000100 -#define IOC_IOCFG17_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG17_IOSTR_W 2 +#define IOC_IOCFG17_IOSTR_M 0x00000300 +#define IOC_IOCFG17_IOSTR_S 8 +#define IOC_IOCFG17_IOSTR_MAX 0x00000300 +#define IOC_IOCFG17_IOSTR_MED 0x00000200 +#define IOC_IOCFG17_IOSTR_MIN 0x00000100 +#define IOC_IOCFG17_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -5547,51 +5547,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG17_PORT_ID_W 6 -#define IOC_IOCFG17_PORT_ID_M 0x0000003F -#define IOC_IOCFG17_PORT_ID_S 0 -#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG17_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG17_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG17_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG17_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG17_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG17_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG17_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG17_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG17_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG17_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG17_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG17_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG17_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG17_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG17_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG17_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG17_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG17_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG17_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG17_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG17_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG17_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG17_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG17_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG17_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG17_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG17_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG17_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG17_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG17_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG17_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG17_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG17_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG17_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG17_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG17_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG17_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG17_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG17_PORT_ID_W 6 +#define IOC_IOCFG17_PORT_ID_M 0x0000003F +#define IOC_IOCFG17_PORT_ID_S 0 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG17_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG17_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG17_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG17_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG17_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG17_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG17_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG17_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG17_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG17_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG17_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG17_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG17_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG17_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG17_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG17_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG17_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG17_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG17_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG17_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG17_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG17_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG17_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG17_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG17_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG17_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG17_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG17_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG17_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG17_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG17_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG17_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG17_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG17_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG17_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -5602,10 +5602,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG18_HYST_EN 0x40000000 -#define IOC_IOCFG18_HYST_EN_BITN 30 -#define IOC_IOCFG18_HYST_EN_M 0x40000000 -#define IOC_IOCFG18_HYST_EN_S 30 +#define IOC_IOCFG18_HYST_EN 0x40000000 +#define IOC_IOCFG18_HYST_EN_BITN 30 +#define IOC_IOCFG18_HYST_EN_M 0x40000000 +#define IOC_IOCFG18_HYST_EN_S 30 // Field: [29] IE // @@ -5614,10 +5614,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG18_IE 0x20000000 -#define IOC_IOCFG18_IE_BITN 29 -#define IOC_IOCFG18_IE_M 0x20000000 -#define IOC_IOCFG18_IE_S 29 +#define IOC_IOCFG18_IE 0x20000000 +#define IOC_IOCFG18_IE_BITN 29 +#define IOC_IOCFG18_IE_M 0x20000000 +#define IOC_IOCFG18_IE_S 29 // Field: [28:27] WU_CFG // @@ -5639,9 +5639,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG18_WU_CFG_W 2 -#define IOC_IOCFG18_WU_CFG_M 0x18000000 -#define IOC_IOCFG18_WU_CFG_S 27 +#define IOC_IOCFG18_WU_CFG_W 2 +#define IOC_IOCFG18_WU_CFG_M 0x18000000 +#define IOC_IOCFG18_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -5662,25 +5662,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG18_IOMODE_W 3 -#define IOC_IOCFG18_IOMODE_M 0x07000000 -#define IOC_IOCFG18_IOMODE_S 24 -#define IOC_IOCFG18_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG18_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG18_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG18_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG18_IOMODE_INV 0x01000000 -#define IOC_IOCFG18_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG18_IOMODE_W 3 +#define IOC_IOCFG18_IOMODE_M 0x07000000 +#define IOC_IOCFG18_IOMODE_S 24 +#define IOC_IOCFG18_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG18_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG18_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG18_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG18_IOMODE_INV 0x01000000 +#define IOC_IOCFG18_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG18_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG18_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG18_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG18_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG18_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG18_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG18_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG18_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -5690,13 +5690,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG18_EDGE_DET_W 2 -#define IOC_IOCFG18_EDGE_DET_M 0x00030000 -#define IOC_IOCFG18_EDGE_DET_S 16 -#define IOC_IOCFG18_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG18_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG18_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG18_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG18_EDGE_DET_W 2 +#define IOC_IOCFG18_EDGE_DET_M 0x00030000 +#define IOC_IOCFG18_EDGE_DET_S 16 +#define IOC_IOCFG18_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG18_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG18_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG18_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -5705,21 +5705,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG18_PULL_CTL_W 2 -#define IOC_IOCFG18_PULL_CTL_M 0x00006000 -#define IOC_IOCFG18_PULL_CTL_S 13 -#define IOC_IOCFG18_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG18_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG18_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG18_PULL_CTL_W 2 +#define IOC_IOCFG18_PULL_CTL_M 0x00006000 +#define IOC_IOCFG18_PULL_CTL_S 13 +#define IOC_IOCFG18_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG18_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG18_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG18_SLEW_RED 0x00001000 -#define IOC_IOCFG18_SLEW_RED_BITN 12 -#define IOC_IOCFG18_SLEW_RED_M 0x00001000 -#define IOC_IOCFG18_SLEW_RED_S 12 +#define IOC_IOCFG18_SLEW_RED 0x00001000 +#define IOC_IOCFG18_SLEW_RED_BITN 12 +#define IOC_IOCFG18_SLEW_RED_M 0x00001000 +#define IOC_IOCFG18_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -5732,12 +5732,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG18_IOCURR_W 2 -#define IOC_IOCFG18_IOCURR_M 0x00000C00 -#define IOC_IOCFG18_IOCURR_S 10 -#define IOC_IOCFG18_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG18_IOCURR_4MA 0x00000400 -#define IOC_IOCFG18_IOCURR_2MA 0x00000000 +#define IOC_IOCFG18_IOCURR_W 2 +#define IOC_IOCFG18_IOCURR_M 0x00000C00 +#define IOC_IOCFG18_IOCURR_S 10 +#define IOC_IOCFG18_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG18_IOCURR_4MA 0x00000400 +#define IOC_IOCFG18_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -5756,13 +5756,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG18_IOSTR_W 2 -#define IOC_IOCFG18_IOSTR_M 0x00000300 -#define IOC_IOCFG18_IOSTR_S 8 -#define IOC_IOCFG18_IOSTR_MAX 0x00000300 -#define IOC_IOCFG18_IOSTR_MED 0x00000200 -#define IOC_IOCFG18_IOSTR_MIN 0x00000100 -#define IOC_IOCFG18_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG18_IOSTR_W 2 +#define IOC_IOCFG18_IOSTR_M 0x00000300 +#define IOC_IOCFG18_IOSTR_S 8 +#define IOC_IOCFG18_IOSTR_MAX 0x00000300 +#define IOC_IOCFG18_IOSTR_MED 0x00000200 +#define IOC_IOCFG18_IOSTR_MIN 0x00000100 +#define IOC_IOCFG18_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -5850,51 +5850,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG18_PORT_ID_W 6 -#define IOC_IOCFG18_PORT_ID_M 0x0000003F -#define IOC_IOCFG18_PORT_ID_S 0 -#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG18_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG18_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG18_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG18_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG18_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG18_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG18_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG18_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG18_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG18_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG18_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG18_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG18_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG18_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG18_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG18_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG18_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG18_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG18_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG18_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG18_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG18_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG18_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG18_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG18_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG18_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG18_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG18_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG18_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG18_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG18_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG18_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG18_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG18_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG18_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG18_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG18_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG18_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG18_PORT_ID_W 6 +#define IOC_IOCFG18_PORT_ID_M 0x0000003F +#define IOC_IOCFG18_PORT_ID_S 0 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG18_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG18_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG18_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG18_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG18_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG18_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG18_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG18_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG18_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG18_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG18_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG18_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG18_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG18_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG18_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG18_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG18_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG18_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG18_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG18_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG18_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG18_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG18_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG18_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG18_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG18_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG18_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG18_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG18_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG18_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG18_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG18_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG18_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG18_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG18_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -5905,10 +5905,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG19_HYST_EN 0x40000000 -#define IOC_IOCFG19_HYST_EN_BITN 30 -#define IOC_IOCFG19_HYST_EN_M 0x40000000 -#define IOC_IOCFG19_HYST_EN_S 30 +#define IOC_IOCFG19_HYST_EN 0x40000000 +#define IOC_IOCFG19_HYST_EN_BITN 30 +#define IOC_IOCFG19_HYST_EN_M 0x40000000 +#define IOC_IOCFG19_HYST_EN_S 30 // Field: [29] IE // @@ -5917,10 +5917,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG19_IE 0x20000000 -#define IOC_IOCFG19_IE_BITN 29 -#define IOC_IOCFG19_IE_M 0x20000000 -#define IOC_IOCFG19_IE_S 29 +#define IOC_IOCFG19_IE 0x20000000 +#define IOC_IOCFG19_IE_BITN 29 +#define IOC_IOCFG19_IE_M 0x20000000 +#define IOC_IOCFG19_IE_S 29 // Field: [28:27] WU_CFG // @@ -5942,9 +5942,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG19_WU_CFG_W 2 -#define IOC_IOCFG19_WU_CFG_M 0x18000000 -#define IOC_IOCFG19_WU_CFG_S 27 +#define IOC_IOCFG19_WU_CFG_W 2 +#define IOC_IOCFG19_WU_CFG_M 0x18000000 +#define IOC_IOCFG19_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -5965,25 +5965,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG19_IOMODE_W 3 -#define IOC_IOCFG19_IOMODE_M 0x07000000 -#define IOC_IOCFG19_IOMODE_S 24 -#define IOC_IOCFG19_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG19_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG19_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG19_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG19_IOMODE_INV 0x01000000 -#define IOC_IOCFG19_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG19_IOMODE_W 3 +#define IOC_IOCFG19_IOMODE_M 0x07000000 +#define IOC_IOCFG19_IOMODE_S 24 +#define IOC_IOCFG19_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG19_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG19_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG19_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG19_IOMODE_INV 0x01000000 +#define IOC_IOCFG19_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG19_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG19_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG19_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG19_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG19_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG19_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG19_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG19_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -5993,13 +5993,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG19_EDGE_DET_W 2 -#define IOC_IOCFG19_EDGE_DET_M 0x00030000 -#define IOC_IOCFG19_EDGE_DET_S 16 -#define IOC_IOCFG19_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG19_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG19_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG19_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG19_EDGE_DET_W 2 +#define IOC_IOCFG19_EDGE_DET_M 0x00030000 +#define IOC_IOCFG19_EDGE_DET_S 16 +#define IOC_IOCFG19_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG19_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG19_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG19_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -6008,21 +6008,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG19_PULL_CTL_W 2 -#define IOC_IOCFG19_PULL_CTL_M 0x00006000 -#define IOC_IOCFG19_PULL_CTL_S 13 -#define IOC_IOCFG19_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG19_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG19_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG19_PULL_CTL_W 2 +#define IOC_IOCFG19_PULL_CTL_M 0x00006000 +#define IOC_IOCFG19_PULL_CTL_S 13 +#define IOC_IOCFG19_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG19_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG19_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG19_SLEW_RED 0x00001000 -#define IOC_IOCFG19_SLEW_RED_BITN 12 -#define IOC_IOCFG19_SLEW_RED_M 0x00001000 -#define IOC_IOCFG19_SLEW_RED_S 12 +#define IOC_IOCFG19_SLEW_RED 0x00001000 +#define IOC_IOCFG19_SLEW_RED_BITN 12 +#define IOC_IOCFG19_SLEW_RED_M 0x00001000 +#define IOC_IOCFG19_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -6035,12 +6035,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG19_IOCURR_W 2 -#define IOC_IOCFG19_IOCURR_M 0x00000C00 -#define IOC_IOCFG19_IOCURR_S 10 -#define IOC_IOCFG19_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG19_IOCURR_4MA 0x00000400 -#define IOC_IOCFG19_IOCURR_2MA 0x00000000 +#define IOC_IOCFG19_IOCURR_W 2 +#define IOC_IOCFG19_IOCURR_M 0x00000C00 +#define IOC_IOCFG19_IOCURR_S 10 +#define IOC_IOCFG19_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG19_IOCURR_4MA 0x00000400 +#define IOC_IOCFG19_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -6059,13 +6059,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG19_IOSTR_W 2 -#define IOC_IOCFG19_IOSTR_M 0x00000300 -#define IOC_IOCFG19_IOSTR_S 8 -#define IOC_IOCFG19_IOSTR_MAX 0x00000300 -#define IOC_IOCFG19_IOSTR_MED 0x00000200 -#define IOC_IOCFG19_IOSTR_MIN 0x00000100 -#define IOC_IOCFG19_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG19_IOSTR_W 2 +#define IOC_IOCFG19_IOSTR_M 0x00000300 +#define IOC_IOCFG19_IOSTR_S 8 +#define IOC_IOCFG19_IOSTR_MAX 0x00000300 +#define IOC_IOCFG19_IOSTR_MED 0x00000200 +#define IOC_IOCFG19_IOSTR_MIN 0x00000100 +#define IOC_IOCFG19_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -6153,51 +6153,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG19_PORT_ID_W 6 -#define IOC_IOCFG19_PORT_ID_M 0x0000003F -#define IOC_IOCFG19_PORT_ID_S 0 -#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG19_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG19_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG19_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG19_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG19_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG19_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG19_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG19_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG19_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG19_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG19_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG19_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG19_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG19_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG19_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG19_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG19_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG19_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG19_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG19_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG19_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG19_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG19_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG19_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG19_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG19_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG19_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG19_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG19_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG19_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG19_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG19_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG19_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG19_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG19_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG19_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG19_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG19_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG19_PORT_ID_W 6 +#define IOC_IOCFG19_PORT_ID_M 0x0000003F +#define IOC_IOCFG19_PORT_ID_S 0 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG19_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG19_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG19_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG19_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG19_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG19_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG19_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG19_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG19_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG19_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG19_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG19_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG19_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG19_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG19_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG19_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG19_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG19_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG19_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG19_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG19_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG19_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG19_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG19_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG19_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG19_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG19_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG19_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG19_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG19_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG19_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG19_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG19_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG19_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG19_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -6208,10 +6208,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG20_HYST_EN 0x40000000 -#define IOC_IOCFG20_HYST_EN_BITN 30 -#define IOC_IOCFG20_HYST_EN_M 0x40000000 -#define IOC_IOCFG20_HYST_EN_S 30 +#define IOC_IOCFG20_HYST_EN 0x40000000 +#define IOC_IOCFG20_HYST_EN_BITN 30 +#define IOC_IOCFG20_HYST_EN_M 0x40000000 +#define IOC_IOCFG20_HYST_EN_S 30 // Field: [29] IE // @@ -6220,10 +6220,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG20_IE 0x20000000 -#define IOC_IOCFG20_IE_BITN 29 -#define IOC_IOCFG20_IE_M 0x20000000 -#define IOC_IOCFG20_IE_S 29 +#define IOC_IOCFG20_IE 0x20000000 +#define IOC_IOCFG20_IE_BITN 29 +#define IOC_IOCFG20_IE_M 0x20000000 +#define IOC_IOCFG20_IE_S 29 // Field: [28:27] WU_CFG // @@ -6245,9 +6245,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG20_WU_CFG_W 2 -#define IOC_IOCFG20_WU_CFG_M 0x18000000 -#define IOC_IOCFG20_WU_CFG_S 27 +#define IOC_IOCFG20_WU_CFG_W 2 +#define IOC_IOCFG20_WU_CFG_M 0x18000000 +#define IOC_IOCFG20_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -6268,25 +6268,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG20_IOMODE_W 3 -#define IOC_IOCFG20_IOMODE_M 0x07000000 -#define IOC_IOCFG20_IOMODE_S 24 -#define IOC_IOCFG20_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG20_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG20_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG20_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG20_IOMODE_INV 0x01000000 -#define IOC_IOCFG20_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG20_IOMODE_W 3 +#define IOC_IOCFG20_IOMODE_M 0x07000000 +#define IOC_IOCFG20_IOMODE_S 24 +#define IOC_IOCFG20_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG20_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG20_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG20_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG20_IOMODE_INV 0x01000000 +#define IOC_IOCFG20_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG20_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG20_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG20_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG20_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG20_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG20_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG20_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG20_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -6296,13 +6296,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG20_EDGE_DET_W 2 -#define IOC_IOCFG20_EDGE_DET_M 0x00030000 -#define IOC_IOCFG20_EDGE_DET_S 16 -#define IOC_IOCFG20_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG20_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG20_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG20_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG20_EDGE_DET_W 2 +#define IOC_IOCFG20_EDGE_DET_M 0x00030000 +#define IOC_IOCFG20_EDGE_DET_S 16 +#define IOC_IOCFG20_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG20_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG20_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG20_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -6311,21 +6311,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG20_PULL_CTL_W 2 -#define IOC_IOCFG20_PULL_CTL_M 0x00006000 -#define IOC_IOCFG20_PULL_CTL_S 13 -#define IOC_IOCFG20_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG20_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG20_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG20_PULL_CTL_W 2 +#define IOC_IOCFG20_PULL_CTL_M 0x00006000 +#define IOC_IOCFG20_PULL_CTL_S 13 +#define IOC_IOCFG20_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG20_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG20_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG20_SLEW_RED 0x00001000 -#define IOC_IOCFG20_SLEW_RED_BITN 12 -#define IOC_IOCFG20_SLEW_RED_M 0x00001000 -#define IOC_IOCFG20_SLEW_RED_S 12 +#define IOC_IOCFG20_SLEW_RED 0x00001000 +#define IOC_IOCFG20_SLEW_RED_BITN 12 +#define IOC_IOCFG20_SLEW_RED_M 0x00001000 +#define IOC_IOCFG20_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -6338,12 +6338,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG20_IOCURR_W 2 -#define IOC_IOCFG20_IOCURR_M 0x00000C00 -#define IOC_IOCFG20_IOCURR_S 10 -#define IOC_IOCFG20_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG20_IOCURR_4MA 0x00000400 -#define IOC_IOCFG20_IOCURR_2MA 0x00000000 +#define IOC_IOCFG20_IOCURR_W 2 +#define IOC_IOCFG20_IOCURR_M 0x00000C00 +#define IOC_IOCFG20_IOCURR_S 10 +#define IOC_IOCFG20_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG20_IOCURR_4MA 0x00000400 +#define IOC_IOCFG20_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -6362,13 +6362,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG20_IOSTR_W 2 -#define IOC_IOCFG20_IOSTR_M 0x00000300 -#define IOC_IOCFG20_IOSTR_S 8 -#define IOC_IOCFG20_IOSTR_MAX 0x00000300 -#define IOC_IOCFG20_IOSTR_MED 0x00000200 -#define IOC_IOCFG20_IOSTR_MIN 0x00000100 -#define IOC_IOCFG20_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG20_IOSTR_W 2 +#define IOC_IOCFG20_IOSTR_M 0x00000300 +#define IOC_IOCFG20_IOSTR_S 8 +#define IOC_IOCFG20_IOSTR_MAX 0x00000300 +#define IOC_IOCFG20_IOSTR_MED 0x00000200 +#define IOC_IOCFG20_IOSTR_MIN 0x00000100 +#define IOC_IOCFG20_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -6456,51 +6456,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG20_PORT_ID_W 6 -#define IOC_IOCFG20_PORT_ID_M 0x0000003F -#define IOC_IOCFG20_PORT_ID_S 0 -#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG20_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG20_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG20_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG20_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG20_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG20_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG20_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG20_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG20_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG20_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG20_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG20_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG20_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG20_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG20_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG20_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG20_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG20_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG20_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG20_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG20_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG20_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG20_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG20_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG20_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG20_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG20_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG20_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG20_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG20_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG20_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG20_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG20_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG20_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG20_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG20_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG20_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG20_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG20_PORT_ID_W 6 +#define IOC_IOCFG20_PORT_ID_M 0x0000003F +#define IOC_IOCFG20_PORT_ID_S 0 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG20_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG20_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG20_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG20_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG20_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG20_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG20_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG20_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG20_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG20_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG20_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG20_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG20_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG20_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG20_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG20_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG20_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG20_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG20_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG20_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG20_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG20_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG20_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG20_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG20_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG20_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG20_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG20_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG20_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG20_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG20_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG20_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG20_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG20_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG20_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -6511,10 +6511,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG21_HYST_EN 0x40000000 -#define IOC_IOCFG21_HYST_EN_BITN 30 -#define IOC_IOCFG21_HYST_EN_M 0x40000000 -#define IOC_IOCFG21_HYST_EN_S 30 +#define IOC_IOCFG21_HYST_EN 0x40000000 +#define IOC_IOCFG21_HYST_EN_BITN 30 +#define IOC_IOCFG21_HYST_EN_M 0x40000000 +#define IOC_IOCFG21_HYST_EN_S 30 // Field: [29] IE // @@ -6523,10 +6523,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG21_IE 0x20000000 -#define IOC_IOCFG21_IE_BITN 29 -#define IOC_IOCFG21_IE_M 0x20000000 -#define IOC_IOCFG21_IE_S 29 +#define IOC_IOCFG21_IE 0x20000000 +#define IOC_IOCFG21_IE_BITN 29 +#define IOC_IOCFG21_IE_M 0x20000000 +#define IOC_IOCFG21_IE_S 29 // Field: [28:27] WU_CFG // @@ -6548,9 +6548,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG21_WU_CFG_W 2 -#define IOC_IOCFG21_WU_CFG_M 0x18000000 -#define IOC_IOCFG21_WU_CFG_S 27 +#define IOC_IOCFG21_WU_CFG_W 2 +#define IOC_IOCFG21_WU_CFG_M 0x18000000 +#define IOC_IOCFG21_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -6571,25 +6571,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG21_IOMODE_W 3 -#define IOC_IOCFG21_IOMODE_M 0x07000000 -#define IOC_IOCFG21_IOMODE_S 24 -#define IOC_IOCFG21_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG21_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG21_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG21_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG21_IOMODE_INV 0x01000000 -#define IOC_IOCFG21_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG21_IOMODE_W 3 +#define IOC_IOCFG21_IOMODE_M 0x07000000 +#define IOC_IOCFG21_IOMODE_S 24 +#define IOC_IOCFG21_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG21_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG21_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG21_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG21_IOMODE_INV 0x01000000 +#define IOC_IOCFG21_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG21_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG21_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG21_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG21_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG21_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG21_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG21_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG21_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -6599,13 +6599,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG21_EDGE_DET_W 2 -#define IOC_IOCFG21_EDGE_DET_M 0x00030000 -#define IOC_IOCFG21_EDGE_DET_S 16 -#define IOC_IOCFG21_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG21_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG21_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG21_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG21_EDGE_DET_W 2 +#define IOC_IOCFG21_EDGE_DET_M 0x00030000 +#define IOC_IOCFG21_EDGE_DET_S 16 +#define IOC_IOCFG21_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG21_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG21_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG21_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -6614,21 +6614,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG21_PULL_CTL_W 2 -#define IOC_IOCFG21_PULL_CTL_M 0x00006000 -#define IOC_IOCFG21_PULL_CTL_S 13 -#define IOC_IOCFG21_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG21_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG21_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG21_PULL_CTL_W 2 +#define IOC_IOCFG21_PULL_CTL_M 0x00006000 +#define IOC_IOCFG21_PULL_CTL_S 13 +#define IOC_IOCFG21_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG21_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG21_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG21_SLEW_RED 0x00001000 -#define IOC_IOCFG21_SLEW_RED_BITN 12 -#define IOC_IOCFG21_SLEW_RED_M 0x00001000 -#define IOC_IOCFG21_SLEW_RED_S 12 +#define IOC_IOCFG21_SLEW_RED 0x00001000 +#define IOC_IOCFG21_SLEW_RED_BITN 12 +#define IOC_IOCFG21_SLEW_RED_M 0x00001000 +#define IOC_IOCFG21_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -6641,12 +6641,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG21_IOCURR_W 2 -#define IOC_IOCFG21_IOCURR_M 0x00000C00 -#define IOC_IOCFG21_IOCURR_S 10 -#define IOC_IOCFG21_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG21_IOCURR_4MA 0x00000400 -#define IOC_IOCFG21_IOCURR_2MA 0x00000000 +#define IOC_IOCFG21_IOCURR_W 2 +#define IOC_IOCFG21_IOCURR_M 0x00000C00 +#define IOC_IOCFG21_IOCURR_S 10 +#define IOC_IOCFG21_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG21_IOCURR_4MA 0x00000400 +#define IOC_IOCFG21_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -6665,13 +6665,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG21_IOSTR_W 2 -#define IOC_IOCFG21_IOSTR_M 0x00000300 -#define IOC_IOCFG21_IOSTR_S 8 -#define IOC_IOCFG21_IOSTR_MAX 0x00000300 -#define IOC_IOCFG21_IOSTR_MED 0x00000200 -#define IOC_IOCFG21_IOSTR_MIN 0x00000100 -#define IOC_IOCFG21_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG21_IOSTR_W 2 +#define IOC_IOCFG21_IOSTR_M 0x00000300 +#define IOC_IOCFG21_IOSTR_S 8 +#define IOC_IOCFG21_IOSTR_MAX 0x00000300 +#define IOC_IOCFG21_IOSTR_MED 0x00000200 +#define IOC_IOCFG21_IOSTR_MIN 0x00000100 +#define IOC_IOCFG21_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -6759,51 +6759,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG21_PORT_ID_W 6 -#define IOC_IOCFG21_PORT_ID_M 0x0000003F -#define IOC_IOCFG21_PORT_ID_S 0 -#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG21_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG21_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG21_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG21_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG21_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG21_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG21_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG21_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG21_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG21_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG21_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG21_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG21_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG21_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG21_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG21_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG21_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG21_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG21_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG21_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG21_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG21_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG21_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG21_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG21_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG21_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG21_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG21_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG21_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG21_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG21_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG21_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG21_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG21_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG21_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG21_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG21_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG21_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG21_PORT_ID_W 6 +#define IOC_IOCFG21_PORT_ID_M 0x0000003F +#define IOC_IOCFG21_PORT_ID_S 0 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG21_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG21_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG21_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG21_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG21_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG21_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG21_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG21_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG21_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG21_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG21_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG21_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG21_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG21_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG21_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG21_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG21_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG21_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG21_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG21_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG21_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG21_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG21_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG21_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG21_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG21_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG21_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG21_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG21_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG21_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG21_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG21_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG21_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG21_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG21_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -6814,10 +6814,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG22_HYST_EN 0x40000000 -#define IOC_IOCFG22_HYST_EN_BITN 30 -#define IOC_IOCFG22_HYST_EN_M 0x40000000 -#define IOC_IOCFG22_HYST_EN_S 30 +#define IOC_IOCFG22_HYST_EN 0x40000000 +#define IOC_IOCFG22_HYST_EN_BITN 30 +#define IOC_IOCFG22_HYST_EN_M 0x40000000 +#define IOC_IOCFG22_HYST_EN_S 30 // Field: [29] IE // @@ -6826,10 +6826,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG22_IE 0x20000000 -#define IOC_IOCFG22_IE_BITN 29 -#define IOC_IOCFG22_IE_M 0x20000000 -#define IOC_IOCFG22_IE_S 29 +#define IOC_IOCFG22_IE 0x20000000 +#define IOC_IOCFG22_IE_BITN 29 +#define IOC_IOCFG22_IE_M 0x20000000 +#define IOC_IOCFG22_IE_S 29 // Field: [28:27] WU_CFG // @@ -6851,9 +6851,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG22_WU_CFG_W 2 -#define IOC_IOCFG22_WU_CFG_M 0x18000000 -#define IOC_IOCFG22_WU_CFG_S 27 +#define IOC_IOCFG22_WU_CFG_W 2 +#define IOC_IOCFG22_WU_CFG_M 0x18000000 +#define IOC_IOCFG22_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -6874,25 +6874,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG22_IOMODE_W 3 -#define IOC_IOCFG22_IOMODE_M 0x07000000 -#define IOC_IOCFG22_IOMODE_S 24 -#define IOC_IOCFG22_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG22_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG22_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG22_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG22_IOMODE_INV 0x01000000 -#define IOC_IOCFG22_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG22_IOMODE_W 3 +#define IOC_IOCFG22_IOMODE_M 0x07000000 +#define IOC_IOCFG22_IOMODE_S 24 +#define IOC_IOCFG22_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG22_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG22_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG22_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG22_IOMODE_INV 0x01000000 +#define IOC_IOCFG22_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG22_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG22_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG22_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG22_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG22_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG22_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG22_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG22_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -6902,13 +6902,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG22_EDGE_DET_W 2 -#define IOC_IOCFG22_EDGE_DET_M 0x00030000 -#define IOC_IOCFG22_EDGE_DET_S 16 -#define IOC_IOCFG22_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG22_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG22_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG22_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG22_EDGE_DET_W 2 +#define IOC_IOCFG22_EDGE_DET_M 0x00030000 +#define IOC_IOCFG22_EDGE_DET_S 16 +#define IOC_IOCFG22_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG22_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG22_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG22_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -6917,21 +6917,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG22_PULL_CTL_W 2 -#define IOC_IOCFG22_PULL_CTL_M 0x00006000 -#define IOC_IOCFG22_PULL_CTL_S 13 -#define IOC_IOCFG22_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG22_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG22_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG22_PULL_CTL_W 2 +#define IOC_IOCFG22_PULL_CTL_M 0x00006000 +#define IOC_IOCFG22_PULL_CTL_S 13 +#define IOC_IOCFG22_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG22_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG22_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG22_SLEW_RED 0x00001000 -#define IOC_IOCFG22_SLEW_RED_BITN 12 -#define IOC_IOCFG22_SLEW_RED_M 0x00001000 -#define IOC_IOCFG22_SLEW_RED_S 12 +#define IOC_IOCFG22_SLEW_RED 0x00001000 +#define IOC_IOCFG22_SLEW_RED_BITN 12 +#define IOC_IOCFG22_SLEW_RED_M 0x00001000 +#define IOC_IOCFG22_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -6944,12 +6944,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG22_IOCURR_W 2 -#define IOC_IOCFG22_IOCURR_M 0x00000C00 -#define IOC_IOCFG22_IOCURR_S 10 -#define IOC_IOCFG22_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG22_IOCURR_4MA 0x00000400 -#define IOC_IOCFG22_IOCURR_2MA 0x00000000 +#define IOC_IOCFG22_IOCURR_W 2 +#define IOC_IOCFG22_IOCURR_M 0x00000C00 +#define IOC_IOCFG22_IOCURR_S 10 +#define IOC_IOCFG22_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG22_IOCURR_4MA 0x00000400 +#define IOC_IOCFG22_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -6968,13 +6968,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG22_IOSTR_W 2 -#define IOC_IOCFG22_IOSTR_M 0x00000300 -#define IOC_IOCFG22_IOSTR_S 8 -#define IOC_IOCFG22_IOSTR_MAX 0x00000300 -#define IOC_IOCFG22_IOSTR_MED 0x00000200 -#define IOC_IOCFG22_IOSTR_MIN 0x00000100 -#define IOC_IOCFG22_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG22_IOSTR_W 2 +#define IOC_IOCFG22_IOSTR_M 0x00000300 +#define IOC_IOCFG22_IOSTR_S 8 +#define IOC_IOCFG22_IOSTR_MAX 0x00000300 +#define IOC_IOCFG22_IOSTR_MED 0x00000200 +#define IOC_IOCFG22_IOSTR_MIN 0x00000100 +#define IOC_IOCFG22_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -7062,51 +7062,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG22_PORT_ID_W 6 -#define IOC_IOCFG22_PORT_ID_M 0x0000003F -#define IOC_IOCFG22_PORT_ID_S 0 -#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG22_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG22_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG22_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG22_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG22_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG22_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG22_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG22_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG22_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG22_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG22_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG22_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG22_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG22_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG22_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG22_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG22_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG22_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG22_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG22_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG22_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG22_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG22_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG22_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG22_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG22_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG22_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG22_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG22_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG22_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG22_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG22_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG22_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG22_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG22_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG22_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG22_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG22_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG22_PORT_ID_W 6 +#define IOC_IOCFG22_PORT_ID_M 0x0000003F +#define IOC_IOCFG22_PORT_ID_S 0 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG22_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG22_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG22_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG22_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG22_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG22_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG22_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG22_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG22_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG22_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG22_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG22_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG22_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG22_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG22_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG22_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG22_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG22_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG22_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG22_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG22_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG22_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG22_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG22_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG22_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG22_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG22_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG22_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG22_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG22_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG22_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG22_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG22_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG22_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG22_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -7117,10 +7117,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG23_HYST_EN 0x40000000 -#define IOC_IOCFG23_HYST_EN_BITN 30 -#define IOC_IOCFG23_HYST_EN_M 0x40000000 -#define IOC_IOCFG23_HYST_EN_S 30 +#define IOC_IOCFG23_HYST_EN 0x40000000 +#define IOC_IOCFG23_HYST_EN_BITN 30 +#define IOC_IOCFG23_HYST_EN_M 0x40000000 +#define IOC_IOCFG23_HYST_EN_S 30 // Field: [29] IE // @@ -7129,10 +7129,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG23_IE 0x20000000 -#define IOC_IOCFG23_IE_BITN 29 -#define IOC_IOCFG23_IE_M 0x20000000 -#define IOC_IOCFG23_IE_S 29 +#define IOC_IOCFG23_IE 0x20000000 +#define IOC_IOCFG23_IE_BITN 29 +#define IOC_IOCFG23_IE_M 0x20000000 +#define IOC_IOCFG23_IE_S 29 // Field: [28:27] WU_CFG // @@ -7154,9 +7154,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG23_WU_CFG_W 2 -#define IOC_IOCFG23_WU_CFG_M 0x18000000 -#define IOC_IOCFG23_WU_CFG_S 27 +#define IOC_IOCFG23_WU_CFG_W 2 +#define IOC_IOCFG23_WU_CFG_M 0x18000000 +#define IOC_IOCFG23_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -7177,25 +7177,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG23_IOMODE_W 3 -#define IOC_IOCFG23_IOMODE_M 0x07000000 -#define IOC_IOCFG23_IOMODE_S 24 -#define IOC_IOCFG23_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG23_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG23_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG23_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG23_IOMODE_INV 0x01000000 -#define IOC_IOCFG23_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG23_IOMODE_W 3 +#define IOC_IOCFG23_IOMODE_M 0x07000000 +#define IOC_IOCFG23_IOMODE_S 24 +#define IOC_IOCFG23_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG23_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG23_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG23_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG23_IOMODE_INV 0x01000000 +#define IOC_IOCFG23_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG23_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG23_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG23_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG23_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG23_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG23_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG23_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG23_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -7205,13 +7205,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG23_EDGE_DET_W 2 -#define IOC_IOCFG23_EDGE_DET_M 0x00030000 -#define IOC_IOCFG23_EDGE_DET_S 16 -#define IOC_IOCFG23_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG23_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG23_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG23_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG23_EDGE_DET_W 2 +#define IOC_IOCFG23_EDGE_DET_M 0x00030000 +#define IOC_IOCFG23_EDGE_DET_S 16 +#define IOC_IOCFG23_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG23_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG23_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG23_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -7220,21 +7220,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG23_PULL_CTL_W 2 -#define IOC_IOCFG23_PULL_CTL_M 0x00006000 -#define IOC_IOCFG23_PULL_CTL_S 13 -#define IOC_IOCFG23_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG23_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG23_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG23_PULL_CTL_W 2 +#define IOC_IOCFG23_PULL_CTL_M 0x00006000 +#define IOC_IOCFG23_PULL_CTL_S 13 +#define IOC_IOCFG23_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG23_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG23_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG23_SLEW_RED 0x00001000 -#define IOC_IOCFG23_SLEW_RED_BITN 12 -#define IOC_IOCFG23_SLEW_RED_M 0x00001000 -#define IOC_IOCFG23_SLEW_RED_S 12 +#define IOC_IOCFG23_SLEW_RED 0x00001000 +#define IOC_IOCFG23_SLEW_RED_BITN 12 +#define IOC_IOCFG23_SLEW_RED_M 0x00001000 +#define IOC_IOCFG23_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -7247,12 +7247,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG23_IOCURR_W 2 -#define IOC_IOCFG23_IOCURR_M 0x00000C00 -#define IOC_IOCFG23_IOCURR_S 10 -#define IOC_IOCFG23_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG23_IOCURR_4MA 0x00000400 -#define IOC_IOCFG23_IOCURR_2MA 0x00000000 +#define IOC_IOCFG23_IOCURR_W 2 +#define IOC_IOCFG23_IOCURR_M 0x00000C00 +#define IOC_IOCFG23_IOCURR_S 10 +#define IOC_IOCFG23_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG23_IOCURR_4MA 0x00000400 +#define IOC_IOCFG23_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -7271,13 +7271,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG23_IOSTR_W 2 -#define IOC_IOCFG23_IOSTR_M 0x00000300 -#define IOC_IOCFG23_IOSTR_S 8 -#define IOC_IOCFG23_IOSTR_MAX 0x00000300 -#define IOC_IOCFG23_IOSTR_MED 0x00000200 -#define IOC_IOCFG23_IOSTR_MIN 0x00000100 -#define IOC_IOCFG23_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG23_IOSTR_W 2 +#define IOC_IOCFG23_IOSTR_M 0x00000300 +#define IOC_IOCFG23_IOSTR_S 8 +#define IOC_IOCFG23_IOSTR_MAX 0x00000300 +#define IOC_IOCFG23_IOSTR_MED 0x00000200 +#define IOC_IOCFG23_IOSTR_MIN 0x00000100 +#define IOC_IOCFG23_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -7365,51 +7365,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG23_PORT_ID_W 6 -#define IOC_IOCFG23_PORT_ID_M 0x0000003F -#define IOC_IOCFG23_PORT_ID_S 0 -#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG23_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG23_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG23_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG23_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG23_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG23_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG23_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG23_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG23_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG23_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG23_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG23_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG23_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG23_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG23_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG23_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG23_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG23_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG23_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG23_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG23_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG23_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG23_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG23_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG23_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG23_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG23_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG23_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG23_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG23_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG23_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG23_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG23_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG23_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG23_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG23_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG23_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG23_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG23_PORT_ID_W 6 +#define IOC_IOCFG23_PORT_ID_M 0x0000003F +#define IOC_IOCFG23_PORT_ID_S 0 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG23_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG23_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG23_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG23_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG23_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG23_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG23_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG23_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG23_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG23_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG23_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG23_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG23_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG23_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG23_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG23_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG23_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG23_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG23_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG23_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG23_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG23_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG23_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG23_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG23_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG23_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG23_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG23_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG23_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG23_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG23_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG23_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG23_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG23_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG23_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -7420,10 +7420,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG24_HYST_EN 0x40000000 -#define IOC_IOCFG24_HYST_EN_BITN 30 -#define IOC_IOCFG24_HYST_EN_M 0x40000000 -#define IOC_IOCFG24_HYST_EN_S 30 +#define IOC_IOCFG24_HYST_EN 0x40000000 +#define IOC_IOCFG24_HYST_EN_BITN 30 +#define IOC_IOCFG24_HYST_EN_M 0x40000000 +#define IOC_IOCFG24_HYST_EN_S 30 // Field: [29] IE // @@ -7432,10 +7432,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG24_IE 0x20000000 -#define IOC_IOCFG24_IE_BITN 29 -#define IOC_IOCFG24_IE_M 0x20000000 -#define IOC_IOCFG24_IE_S 29 +#define IOC_IOCFG24_IE 0x20000000 +#define IOC_IOCFG24_IE_BITN 29 +#define IOC_IOCFG24_IE_M 0x20000000 +#define IOC_IOCFG24_IE_S 29 // Field: [28:27] WU_CFG // @@ -7457,9 +7457,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG24_WU_CFG_W 2 -#define IOC_IOCFG24_WU_CFG_M 0x18000000 -#define IOC_IOCFG24_WU_CFG_S 27 +#define IOC_IOCFG24_WU_CFG_W 2 +#define IOC_IOCFG24_WU_CFG_M 0x18000000 +#define IOC_IOCFG24_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -7480,25 +7480,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG24_IOMODE_W 3 -#define IOC_IOCFG24_IOMODE_M 0x07000000 -#define IOC_IOCFG24_IOMODE_S 24 -#define IOC_IOCFG24_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG24_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG24_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG24_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG24_IOMODE_INV 0x01000000 -#define IOC_IOCFG24_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG24_IOMODE_W 3 +#define IOC_IOCFG24_IOMODE_M 0x07000000 +#define IOC_IOCFG24_IOMODE_S 24 +#define IOC_IOCFG24_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG24_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG24_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG24_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG24_IOMODE_INV 0x01000000 +#define IOC_IOCFG24_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG24_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG24_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG24_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG24_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG24_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG24_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG24_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG24_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -7508,13 +7508,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG24_EDGE_DET_W 2 -#define IOC_IOCFG24_EDGE_DET_M 0x00030000 -#define IOC_IOCFG24_EDGE_DET_S 16 -#define IOC_IOCFG24_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG24_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG24_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG24_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG24_EDGE_DET_W 2 +#define IOC_IOCFG24_EDGE_DET_M 0x00030000 +#define IOC_IOCFG24_EDGE_DET_S 16 +#define IOC_IOCFG24_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG24_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG24_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG24_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -7523,21 +7523,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG24_PULL_CTL_W 2 -#define IOC_IOCFG24_PULL_CTL_M 0x00006000 -#define IOC_IOCFG24_PULL_CTL_S 13 -#define IOC_IOCFG24_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG24_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG24_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG24_PULL_CTL_W 2 +#define IOC_IOCFG24_PULL_CTL_M 0x00006000 +#define IOC_IOCFG24_PULL_CTL_S 13 +#define IOC_IOCFG24_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG24_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG24_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG24_SLEW_RED 0x00001000 -#define IOC_IOCFG24_SLEW_RED_BITN 12 -#define IOC_IOCFG24_SLEW_RED_M 0x00001000 -#define IOC_IOCFG24_SLEW_RED_S 12 +#define IOC_IOCFG24_SLEW_RED 0x00001000 +#define IOC_IOCFG24_SLEW_RED_BITN 12 +#define IOC_IOCFG24_SLEW_RED_M 0x00001000 +#define IOC_IOCFG24_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -7550,12 +7550,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG24_IOCURR_W 2 -#define IOC_IOCFG24_IOCURR_M 0x00000C00 -#define IOC_IOCFG24_IOCURR_S 10 -#define IOC_IOCFG24_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG24_IOCURR_4MA 0x00000400 -#define IOC_IOCFG24_IOCURR_2MA 0x00000000 +#define IOC_IOCFG24_IOCURR_W 2 +#define IOC_IOCFG24_IOCURR_M 0x00000C00 +#define IOC_IOCFG24_IOCURR_S 10 +#define IOC_IOCFG24_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG24_IOCURR_4MA 0x00000400 +#define IOC_IOCFG24_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -7574,13 +7574,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG24_IOSTR_W 2 -#define IOC_IOCFG24_IOSTR_M 0x00000300 -#define IOC_IOCFG24_IOSTR_S 8 -#define IOC_IOCFG24_IOSTR_MAX 0x00000300 -#define IOC_IOCFG24_IOSTR_MED 0x00000200 -#define IOC_IOCFG24_IOSTR_MIN 0x00000100 -#define IOC_IOCFG24_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG24_IOSTR_W 2 +#define IOC_IOCFG24_IOSTR_M 0x00000300 +#define IOC_IOCFG24_IOSTR_S 8 +#define IOC_IOCFG24_IOSTR_MAX 0x00000300 +#define IOC_IOCFG24_IOSTR_MED 0x00000200 +#define IOC_IOCFG24_IOSTR_MIN 0x00000100 +#define IOC_IOCFG24_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -7668,51 +7668,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG24_PORT_ID_W 6 -#define IOC_IOCFG24_PORT_ID_M 0x0000003F -#define IOC_IOCFG24_PORT_ID_S 0 -#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG24_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG24_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG24_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG24_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG24_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG24_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG24_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG24_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG24_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG24_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG24_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG24_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG24_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG24_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG24_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG24_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG24_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG24_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG24_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG24_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG24_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG24_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG24_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG24_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG24_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG24_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG24_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG24_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG24_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG24_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG24_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG24_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG24_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG24_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG24_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG24_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG24_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG24_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG24_PORT_ID_W 6 +#define IOC_IOCFG24_PORT_ID_M 0x0000003F +#define IOC_IOCFG24_PORT_ID_S 0 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG24_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG24_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG24_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG24_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG24_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG24_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG24_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG24_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG24_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG24_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG24_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG24_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG24_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG24_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG24_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG24_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG24_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG24_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG24_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG24_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG24_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG24_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG24_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG24_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG24_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG24_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG24_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG24_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG24_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG24_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG24_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG24_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG24_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG24_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG24_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -7723,10 +7723,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG25_HYST_EN 0x40000000 -#define IOC_IOCFG25_HYST_EN_BITN 30 -#define IOC_IOCFG25_HYST_EN_M 0x40000000 -#define IOC_IOCFG25_HYST_EN_S 30 +#define IOC_IOCFG25_HYST_EN 0x40000000 +#define IOC_IOCFG25_HYST_EN_BITN 30 +#define IOC_IOCFG25_HYST_EN_M 0x40000000 +#define IOC_IOCFG25_HYST_EN_S 30 // Field: [29] IE // @@ -7735,10 +7735,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG25_IE 0x20000000 -#define IOC_IOCFG25_IE_BITN 29 -#define IOC_IOCFG25_IE_M 0x20000000 -#define IOC_IOCFG25_IE_S 29 +#define IOC_IOCFG25_IE 0x20000000 +#define IOC_IOCFG25_IE_BITN 29 +#define IOC_IOCFG25_IE_M 0x20000000 +#define IOC_IOCFG25_IE_S 29 // Field: [28:27] WU_CFG // @@ -7760,9 +7760,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG25_WU_CFG_W 2 -#define IOC_IOCFG25_WU_CFG_M 0x18000000 -#define IOC_IOCFG25_WU_CFG_S 27 +#define IOC_IOCFG25_WU_CFG_W 2 +#define IOC_IOCFG25_WU_CFG_M 0x18000000 +#define IOC_IOCFG25_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -7783,25 +7783,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG25_IOMODE_W 3 -#define IOC_IOCFG25_IOMODE_M 0x07000000 -#define IOC_IOCFG25_IOMODE_S 24 -#define IOC_IOCFG25_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG25_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG25_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG25_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG25_IOMODE_INV 0x01000000 -#define IOC_IOCFG25_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG25_IOMODE_W 3 +#define IOC_IOCFG25_IOMODE_M 0x07000000 +#define IOC_IOCFG25_IOMODE_S 24 +#define IOC_IOCFG25_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG25_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG25_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG25_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG25_IOMODE_INV 0x01000000 +#define IOC_IOCFG25_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG25_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG25_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG25_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG25_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG25_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG25_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG25_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG25_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -7811,13 +7811,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG25_EDGE_DET_W 2 -#define IOC_IOCFG25_EDGE_DET_M 0x00030000 -#define IOC_IOCFG25_EDGE_DET_S 16 -#define IOC_IOCFG25_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG25_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG25_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG25_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG25_EDGE_DET_W 2 +#define IOC_IOCFG25_EDGE_DET_M 0x00030000 +#define IOC_IOCFG25_EDGE_DET_S 16 +#define IOC_IOCFG25_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG25_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG25_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG25_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -7826,21 +7826,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG25_PULL_CTL_W 2 -#define IOC_IOCFG25_PULL_CTL_M 0x00006000 -#define IOC_IOCFG25_PULL_CTL_S 13 -#define IOC_IOCFG25_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG25_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG25_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG25_PULL_CTL_W 2 +#define IOC_IOCFG25_PULL_CTL_M 0x00006000 +#define IOC_IOCFG25_PULL_CTL_S 13 +#define IOC_IOCFG25_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG25_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG25_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG25_SLEW_RED 0x00001000 -#define IOC_IOCFG25_SLEW_RED_BITN 12 -#define IOC_IOCFG25_SLEW_RED_M 0x00001000 -#define IOC_IOCFG25_SLEW_RED_S 12 +#define IOC_IOCFG25_SLEW_RED 0x00001000 +#define IOC_IOCFG25_SLEW_RED_BITN 12 +#define IOC_IOCFG25_SLEW_RED_M 0x00001000 +#define IOC_IOCFG25_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -7853,12 +7853,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG25_IOCURR_W 2 -#define IOC_IOCFG25_IOCURR_M 0x00000C00 -#define IOC_IOCFG25_IOCURR_S 10 -#define IOC_IOCFG25_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG25_IOCURR_4MA 0x00000400 -#define IOC_IOCFG25_IOCURR_2MA 0x00000000 +#define IOC_IOCFG25_IOCURR_W 2 +#define IOC_IOCFG25_IOCURR_M 0x00000C00 +#define IOC_IOCFG25_IOCURR_S 10 +#define IOC_IOCFG25_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG25_IOCURR_4MA 0x00000400 +#define IOC_IOCFG25_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -7877,13 +7877,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG25_IOSTR_W 2 -#define IOC_IOCFG25_IOSTR_M 0x00000300 -#define IOC_IOCFG25_IOSTR_S 8 -#define IOC_IOCFG25_IOSTR_MAX 0x00000300 -#define IOC_IOCFG25_IOSTR_MED 0x00000200 -#define IOC_IOCFG25_IOSTR_MIN 0x00000100 -#define IOC_IOCFG25_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG25_IOSTR_W 2 +#define IOC_IOCFG25_IOSTR_M 0x00000300 +#define IOC_IOCFG25_IOSTR_S 8 +#define IOC_IOCFG25_IOSTR_MAX 0x00000300 +#define IOC_IOCFG25_IOSTR_MED 0x00000200 +#define IOC_IOCFG25_IOSTR_MIN 0x00000100 +#define IOC_IOCFG25_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -7971,51 +7971,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG25_PORT_ID_W 6 -#define IOC_IOCFG25_PORT_ID_M 0x0000003F -#define IOC_IOCFG25_PORT_ID_S 0 -#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG25_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG25_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG25_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG25_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG25_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG25_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG25_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG25_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG25_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG25_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG25_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG25_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG25_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG25_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG25_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG25_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG25_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG25_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG25_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG25_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG25_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG25_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG25_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG25_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG25_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG25_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG25_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG25_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG25_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG25_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG25_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG25_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG25_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG25_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG25_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG25_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG25_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG25_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG25_PORT_ID_W 6 +#define IOC_IOCFG25_PORT_ID_M 0x0000003F +#define IOC_IOCFG25_PORT_ID_S 0 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG25_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG25_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG25_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG25_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG25_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG25_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG25_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG25_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG25_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG25_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG25_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG25_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG25_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG25_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG25_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG25_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG25_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG25_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG25_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG25_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG25_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG25_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG25_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG25_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG25_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG25_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG25_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG25_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG25_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG25_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG25_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG25_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG25_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG25_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG25_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -8026,10 +8026,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG26_HYST_EN 0x40000000 -#define IOC_IOCFG26_HYST_EN_BITN 30 -#define IOC_IOCFG26_HYST_EN_M 0x40000000 -#define IOC_IOCFG26_HYST_EN_S 30 +#define IOC_IOCFG26_HYST_EN 0x40000000 +#define IOC_IOCFG26_HYST_EN_BITN 30 +#define IOC_IOCFG26_HYST_EN_M 0x40000000 +#define IOC_IOCFG26_HYST_EN_S 30 // Field: [29] IE // @@ -8038,10 +8038,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG26_IE 0x20000000 -#define IOC_IOCFG26_IE_BITN 29 -#define IOC_IOCFG26_IE_M 0x20000000 -#define IOC_IOCFG26_IE_S 29 +#define IOC_IOCFG26_IE 0x20000000 +#define IOC_IOCFG26_IE_BITN 29 +#define IOC_IOCFG26_IE_M 0x20000000 +#define IOC_IOCFG26_IE_S 29 // Field: [28:27] WU_CFG // @@ -8063,9 +8063,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG26_WU_CFG_W 2 -#define IOC_IOCFG26_WU_CFG_M 0x18000000 -#define IOC_IOCFG26_WU_CFG_S 27 +#define IOC_IOCFG26_WU_CFG_W 2 +#define IOC_IOCFG26_WU_CFG_M 0x18000000 +#define IOC_IOCFG26_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -8086,25 +8086,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG26_IOMODE_W 3 -#define IOC_IOCFG26_IOMODE_M 0x07000000 -#define IOC_IOCFG26_IOMODE_S 24 -#define IOC_IOCFG26_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG26_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG26_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG26_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG26_IOMODE_INV 0x01000000 -#define IOC_IOCFG26_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG26_IOMODE_W 3 +#define IOC_IOCFG26_IOMODE_M 0x07000000 +#define IOC_IOCFG26_IOMODE_S 24 +#define IOC_IOCFG26_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG26_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG26_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG26_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG26_IOMODE_INV 0x01000000 +#define IOC_IOCFG26_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG26_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG26_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG26_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG26_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG26_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG26_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG26_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG26_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -8114,13 +8114,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG26_EDGE_DET_W 2 -#define IOC_IOCFG26_EDGE_DET_M 0x00030000 -#define IOC_IOCFG26_EDGE_DET_S 16 -#define IOC_IOCFG26_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG26_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG26_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG26_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG26_EDGE_DET_W 2 +#define IOC_IOCFG26_EDGE_DET_M 0x00030000 +#define IOC_IOCFG26_EDGE_DET_S 16 +#define IOC_IOCFG26_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG26_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG26_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG26_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -8129,21 +8129,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG26_PULL_CTL_W 2 -#define IOC_IOCFG26_PULL_CTL_M 0x00006000 -#define IOC_IOCFG26_PULL_CTL_S 13 -#define IOC_IOCFG26_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG26_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG26_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG26_PULL_CTL_W 2 +#define IOC_IOCFG26_PULL_CTL_M 0x00006000 +#define IOC_IOCFG26_PULL_CTL_S 13 +#define IOC_IOCFG26_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG26_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG26_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG26_SLEW_RED 0x00001000 -#define IOC_IOCFG26_SLEW_RED_BITN 12 -#define IOC_IOCFG26_SLEW_RED_M 0x00001000 -#define IOC_IOCFG26_SLEW_RED_S 12 +#define IOC_IOCFG26_SLEW_RED 0x00001000 +#define IOC_IOCFG26_SLEW_RED_BITN 12 +#define IOC_IOCFG26_SLEW_RED_M 0x00001000 +#define IOC_IOCFG26_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -8156,12 +8156,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG26_IOCURR_W 2 -#define IOC_IOCFG26_IOCURR_M 0x00000C00 -#define IOC_IOCFG26_IOCURR_S 10 -#define IOC_IOCFG26_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG26_IOCURR_4MA 0x00000400 -#define IOC_IOCFG26_IOCURR_2MA 0x00000000 +#define IOC_IOCFG26_IOCURR_W 2 +#define IOC_IOCFG26_IOCURR_M 0x00000C00 +#define IOC_IOCFG26_IOCURR_S 10 +#define IOC_IOCFG26_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG26_IOCURR_4MA 0x00000400 +#define IOC_IOCFG26_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -8180,13 +8180,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG26_IOSTR_W 2 -#define IOC_IOCFG26_IOSTR_M 0x00000300 -#define IOC_IOCFG26_IOSTR_S 8 -#define IOC_IOCFG26_IOSTR_MAX 0x00000300 -#define IOC_IOCFG26_IOSTR_MED 0x00000200 -#define IOC_IOCFG26_IOSTR_MIN 0x00000100 -#define IOC_IOCFG26_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG26_IOSTR_W 2 +#define IOC_IOCFG26_IOSTR_M 0x00000300 +#define IOC_IOCFG26_IOSTR_S 8 +#define IOC_IOCFG26_IOSTR_MAX 0x00000300 +#define IOC_IOCFG26_IOSTR_MED 0x00000200 +#define IOC_IOCFG26_IOSTR_MIN 0x00000100 +#define IOC_IOCFG26_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -8274,51 +8274,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG26_PORT_ID_W 6 -#define IOC_IOCFG26_PORT_ID_M 0x0000003F -#define IOC_IOCFG26_PORT_ID_S 0 -#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG26_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG26_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG26_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG26_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG26_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG26_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG26_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG26_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG26_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG26_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG26_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG26_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG26_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG26_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG26_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG26_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG26_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG26_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG26_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG26_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG26_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG26_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG26_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG26_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG26_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG26_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG26_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG26_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG26_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG26_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG26_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG26_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG26_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG26_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG26_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG26_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG26_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG26_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG26_PORT_ID_W 6 +#define IOC_IOCFG26_PORT_ID_M 0x0000003F +#define IOC_IOCFG26_PORT_ID_S 0 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG26_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG26_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG26_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG26_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG26_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG26_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG26_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG26_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG26_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG26_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG26_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG26_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG26_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG26_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG26_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG26_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG26_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG26_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG26_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG26_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG26_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG26_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG26_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG26_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG26_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG26_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG26_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG26_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG26_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG26_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG26_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG26_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG26_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG26_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG26_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -8329,10 +8329,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG27_HYST_EN 0x40000000 -#define IOC_IOCFG27_HYST_EN_BITN 30 -#define IOC_IOCFG27_HYST_EN_M 0x40000000 -#define IOC_IOCFG27_HYST_EN_S 30 +#define IOC_IOCFG27_HYST_EN 0x40000000 +#define IOC_IOCFG27_HYST_EN_BITN 30 +#define IOC_IOCFG27_HYST_EN_M 0x40000000 +#define IOC_IOCFG27_HYST_EN_S 30 // Field: [29] IE // @@ -8341,10 +8341,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG27_IE 0x20000000 -#define IOC_IOCFG27_IE_BITN 29 -#define IOC_IOCFG27_IE_M 0x20000000 -#define IOC_IOCFG27_IE_S 29 +#define IOC_IOCFG27_IE 0x20000000 +#define IOC_IOCFG27_IE_BITN 29 +#define IOC_IOCFG27_IE_M 0x20000000 +#define IOC_IOCFG27_IE_S 29 // Field: [28:27] WU_CFG // @@ -8366,9 +8366,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG27_WU_CFG_W 2 -#define IOC_IOCFG27_WU_CFG_M 0x18000000 -#define IOC_IOCFG27_WU_CFG_S 27 +#define IOC_IOCFG27_WU_CFG_W 2 +#define IOC_IOCFG27_WU_CFG_M 0x18000000 +#define IOC_IOCFG27_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -8389,25 +8389,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG27_IOMODE_W 3 -#define IOC_IOCFG27_IOMODE_M 0x07000000 -#define IOC_IOCFG27_IOMODE_S 24 -#define IOC_IOCFG27_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG27_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG27_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG27_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG27_IOMODE_INV 0x01000000 -#define IOC_IOCFG27_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG27_IOMODE_W 3 +#define IOC_IOCFG27_IOMODE_M 0x07000000 +#define IOC_IOCFG27_IOMODE_S 24 +#define IOC_IOCFG27_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG27_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG27_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG27_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG27_IOMODE_INV 0x01000000 +#define IOC_IOCFG27_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG27_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG27_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG27_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG27_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG27_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG27_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG27_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG27_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -8417,13 +8417,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG27_EDGE_DET_W 2 -#define IOC_IOCFG27_EDGE_DET_M 0x00030000 -#define IOC_IOCFG27_EDGE_DET_S 16 -#define IOC_IOCFG27_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG27_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG27_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG27_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG27_EDGE_DET_W 2 +#define IOC_IOCFG27_EDGE_DET_M 0x00030000 +#define IOC_IOCFG27_EDGE_DET_S 16 +#define IOC_IOCFG27_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG27_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG27_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG27_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -8432,21 +8432,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG27_PULL_CTL_W 2 -#define IOC_IOCFG27_PULL_CTL_M 0x00006000 -#define IOC_IOCFG27_PULL_CTL_S 13 -#define IOC_IOCFG27_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG27_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG27_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG27_PULL_CTL_W 2 +#define IOC_IOCFG27_PULL_CTL_M 0x00006000 +#define IOC_IOCFG27_PULL_CTL_S 13 +#define IOC_IOCFG27_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG27_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG27_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG27_SLEW_RED 0x00001000 -#define IOC_IOCFG27_SLEW_RED_BITN 12 -#define IOC_IOCFG27_SLEW_RED_M 0x00001000 -#define IOC_IOCFG27_SLEW_RED_S 12 +#define IOC_IOCFG27_SLEW_RED 0x00001000 +#define IOC_IOCFG27_SLEW_RED_BITN 12 +#define IOC_IOCFG27_SLEW_RED_M 0x00001000 +#define IOC_IOCFG27_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -8459,12 +8459,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG27_IOCURR_W 2 -#define IOC_IOCFG27_IOCURR_M 0x00000C00 -#define IOC_IOCFG27_IOCURR_S 10 -#define IOC_IOCFG27_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG27_IOCURR_4MA 0x00000400 -#define IOC_IOCFG27_IOCURR_2MA 0x00000000 +#define IOC_IOCFG27_IOCURR_W 2 +#define IOC_IOCFG27_IOCURR_M 0x00000C00 +#define IOC_IOCFG27_IOCURR_S 10 +#define IOC_IOCFG27_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG27_IOCURR_4MA 0x00000400 +#define IOC_IOCFG27_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -8483,13 +8483,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG27_IOSTR_W 2 -#define IOC_IOCFG27_IOSTR_M 0x00000300 -#define IOC_IOCFG27_IOSTR_S 8 -#define IOC_IOCFG27_IOSTR_MAX 0x00000300 -#define IOC_IOCFG27_IOSTR_MED 0x00000200 -#define IOC_IOCFG27_IOSTR_MIN 0x00000100 -#define IOC_IOCFG27_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG27_IOSTR_W 2 +#define IOC_IOCFG27_IOSTR_M 0x00000300 +#define IOC_IOCFG27_IOSTR_S 8 +#define IOC_IOCFG27_IOSTR_MAX 0x00000300 +#define IOC_IOCFG27_IOSTR_MED 0x00000200 +#define IOC_IOCFG27_IOSTR_MIN 0x00000100 +#define IOC_IOCFG27_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -8577,51 +8577,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG27_PORT_ID_W 6 -#define IOC_IOCFG27_PORT_ID_M 0x0000003F -#define IOC_IOCFG27_PORT_ID_S 0 -#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG27_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG27_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG27_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG27_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG27_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG27_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG27_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG27_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG27_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG27_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG27_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG27_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG27_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG27_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG27_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG27_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG27_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG27_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG27_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG27_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG27_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG27_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG27_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG27_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG27_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG27_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG27_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG27_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG27_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG27_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG27_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG27_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG27_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG27_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG27_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG27_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG27_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG27_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG27_PORT_ID_W 6 +#define IOC_IOCFG27_PORT_ID_M 0x0000003F +#define IOC_IOCFG27_PORT_ID_S 0 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG27_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG27_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG27_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG27_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG27_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG27_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG27_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG27_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG27_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG27_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG27_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG27_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG27_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG27_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG27_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG27_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG27_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG27_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG27_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG27_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG27_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG27_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG27_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG27_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG27_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG27_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG27_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG27_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG27_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG27_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG27_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG27_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG27_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG27_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG27_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -8632,10 +8632,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG28_HYST_EN 0x40000000 -#define IOC_IOCFG28_HYST_EN_BITN 30 -#define IOC_IOCFG28_HYST_EN_M 0x40000000 -#define IOC_IOCFG28_HYST_EN_S 30 +#define IOC_IOCFG28_HYST_EN 0x40000000 +#define IOC_IOCFG28_HYST_EN_BITN 30 +#define IOC_IOCFG28_HYST_EN_M 0x40000000 +#define IOC_IOCFG28_HYST_EN_S 30 // Field: [29] IE // @@ -8644,10 +8644,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG28_IE 0x20000000 -#define IOC_IOCFG28_IE_BITN 29 -#define IOC_IOCFG28_IE_M 0x20000000 -#define IOC_IOCFG28_IE_S 29 +#define IOC_IOCFG28_IE 0x20000000 +#define IOC_IOCFG28_IE_BITN 29 +#define IOC_IOCFG28_IE_M 0x20000000 +#define IOC_IOCFG28_IE_S 29 // Field: [28:27] WU_CFG // @@ -8669,9 +8669,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG28_WU_CFG_W 2 -#define IOC_IOCFG28_WU_CFG_M 0x18000000 -#define IOC_IOCFG28_WU_CFG_S 27 +#define IOC_IOCFG28_WU_CFG_W 2 +#define IOC_IOCFG28_WU_CFG_M 0x18000000 +#define IOC_IOCFG28_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -8692,25 +8692,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG28_IOMODE_W 3 -#define IOC_IOCFG28_IOMODE_M 0x07000000 -#define IOC_IOCFG28_IOMODE_S 24 -#define IOC_IOCFG28_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG28_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG28_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG28_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG28_IOMODE_INV 0x01000000 -#define IOC_IOCFG28_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG28_IOMODE_W 3 +#define IOC_IOCFG28_IOMODE_M 0x07000000 +#define IOC_IOCFG28_IOMODE_S 24 +#define IOC_IOCFG28_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG28_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG28_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG28_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG28_IOMODE_INV 0x01000000 +#define IOC_IOCFG28_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG28_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG28_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG28_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG28_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG28_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG28_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG28_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG28_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -8720,13 +8720,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG28_EDGE_DET_W 2 -#define IOC_IOCFG28_EDGE_DET_M 0x00030000 -#define IOC_IOCFG28_EDGE_DET_S 16 -#define IOC_IOCFG28_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG28_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG28_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG28_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG28_EDGE_DET_W 2 +#define IOC_IOCFG28_EDGE_DET_M 0x00030000 +#define IOC_IOCFG28_EDGE_DET_S 16 +#define IOC_IOCFG28_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG28_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG28_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG28_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -8735,21 +8735,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG28_PULL_CTL_W 2 -#define IOC_IOCFG28_PULL_CTL_M 0x00006000 -#define IOC_IOCFG28_PULL_CTL_S 13 -#define IOC_IOCFG28_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG28_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG28_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG28_PULL_CTL_W 2 +#define IOC_IOCFG28_PULL_CTL_M 0x00006000 +#define IOC_IOCFG28_PULL_CTL_S 13 +#define IOC_IOCFG28_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG28_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG28_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG28_SLEW_RED 0x00001000 -#define IOC_IOCFG28_SLEW_RED_BITN 12 -#define IOC_IOCFG28_SLEW_RED_M 0x00001000 -#define IOC_IOCFG28_SLEW_RED_S 12 +#define IOC_IOCFG28_SLEW_RED 0x00001000 +#define IOC_IOCFG28_SLEW_RED_BITN 12 +#define IOC_IOCFG28_SLEW_RED_M 0x00001000 +#define IOC_IOCFG28_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -8762,12 +8762,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG28_IOCURR_W 2 -#define IOC_IOCFG28_IOCURR_M 0x00000C00 -#define IOC_IOCFG28_IOCURR_S 10 -#define IOC_IOCFG28_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG28_IOCURR_4MA 0x00000400 -#define IOC_IOCFG28_IOCURR_2MA 0x00000000 +#define IOC_IOCFG28_IOCURR_W 2 +#define IOC_IOCFG28_IOCURR_M 0x00000C00 +#define IOC_IOCFG28_IOCURR_S 10 +#define IOC_IOCFG28_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG28_IOCURR_4MA 0x00000400 +#define IOC_IOCFG28_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -8786,13 +8786,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG28_IOSTR_W 2 -#define IOC_IOCFG28_IOSTR_M 0x00000300 -#define IOC_IOCFG28_IOSTR_S 8 -#define IOC_IOCFG28_IOSTR_MAX 0x00000300 -#define IOC_IOCFG28_IOSTR_MED 0x00000200 -#define IOC_IOCFG28_IOSTR_MIN 0x00000100 -#define IOC_IOCFG28_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG28_IOSTR_W 2 +#define IOC_IOCFG28_IOSTR_M 0x00000300 +#define IOC_IOCFG28_IOSTR_S 8 +#define IOC_IOCFG28_IOSTR_MAX 0x00000300 +#define IOC_IOCFG28_IOSTR_MED 0x00000200 +#define IOC_IOCFG28_IOSTR_MIN 0x00000100 +#define IOC_IOCFG28_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -8880,51 +8880,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG28_PORT_ID_W 6 -#define IOC_IOCFG28_PORT_ID_M 0x0000003F -#define IOC_IOCFG28_PORT_ID_S 0 -#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG28_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG28_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG28_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG28_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG28_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG28_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG28_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG28_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG28_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG28_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG28_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG28_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG28_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG28_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG28_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG28_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG28_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG28_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG28_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG28_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG28_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG28_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG28_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG28_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG28_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG28_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG28_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG28_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG28_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG28_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG28_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG28_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG28_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG28_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG28_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG28_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG28_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG28_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG28_PORT_ID_W 6 +#define IOC_IOCFG28_PORT_ID_M 0x0000003F +#define IOC_IOCFG28_PORT_ID_S 0 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG28_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG28_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG28_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG28_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG28_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG28_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG28_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG28_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG28_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG28_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG28_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG28_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG28_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG28_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG28_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG28_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG28_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG28_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG28_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG28_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG28_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG28_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG28_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG28_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG28_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG28_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG28_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG28_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG28_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG28_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG28_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG28_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG28_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG28_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG28_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -8935,10 +8935,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG29_HYST_EN 0x40000000 -#define IOC_IOCFG29_HYST_EN_BITN 30 -#define IOC_IOCFG29_HYST_EN_M 0x40000000 -#define IOC_IOCFG29_HYST_EN_S 30 +#define IOC_IOCFG29_HYST_EN 0x40000000 +#define IOC_IOCFG29_HYST_EN_BITN 30 +#define IOC_IOCFG29_HYST_EN_M 0x40000000 +#define IOC_IOCFG29_HYST_EN_S 30 // Field: [29] IE // @@ -8947,10 +8947,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG29_IE 0x20000000 -#define IOC_IOCFG29_IE_BITN 29 -#define IOC_IOCFG29_IE_M 0x20000000 -#define IOC_IOCFG29_IE_S 29 +#define IOC_IOCFG29_IE 0x20000000 +#define IOC_IOCFG29_IE_BITN 29 +#define IOC_IOCFG29_IE_M 0x20000000 +#define IOC_IOCFG29_IE_S 29 // Field: [28:27] WU_CFG // @@ -8972,9 +8972,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG29_WU_CFG_W 2 -#define IOC_IOCFG29_WU_CFG_M 0x18000000 -#define IOC_IOCFG29_WU_CFG_S 27 +#define IOC_IOCFG29_WU_CFG_W 2 +#define IOC_IOCFG29_WU_CFG_M 0x18000000 +#define IOC_IOCFG29_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -8995,25 +8995,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG29_IOMODE_W 3 -#define IOC_IOCFG29_IOMODE_M 0x07000000 -#define IOC_IOCFG29_IOMODE_S 24 -#define IOC_IOCFG29_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG29_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG29_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG29_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG29_IOMODE_INV 0x01000000 -#define IOC_IOCFG29_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG29_IOMODE_W 3 +#define IOC_IOCFG29_IOMODE_M 0x07000000 +#define IOC_IOCFG29_IOMODE_S 24 +#define IOC_IOCFG29_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG29_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG29_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG29_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG29_IOMODE_INV 0x01000000 +#define IOC_IOCFG29_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG29_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG29_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG29_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG29_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG29_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG29_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG29_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG29_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -9023,13 +9023,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG29_EDGE_DET_W 2 -#define IOC_IOCFG29_EDGE_DET_M 0x00030000 -#define IOC_IOCFG29_EDGE_DET_S 16 -#define IOC_IOCFG29_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG29_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG29_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG29_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG29_EDGE_DET_W 2 +#define IOC_IOCFG29_EDGE_DET_M 0x00030000 +#define IOC_IOCFG29_EDGE_DET_S 16 +#define IOC_IOCFG29_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG29_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG29_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG29_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -9038,21 +9038,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG29_PULL_CTL_W 2 -#define IOC_IOCFG29_PULL_CTL_M 0x00006000 -#define IOC_IOCFG29_PULL_CTL_S 13 -#define IOC_IOCFG29_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG29_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG29_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG29_PULL_CTL_W 2 +#define IOC_IOCFG29_PULL_CTL_M 0x00006000 +#define IOC_IOCFG29_PULL_CTL_S 13 +#define IOC_IOCFG29_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG29_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG29_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG29_SLEW_RED 0x00001000 -#define IOC_IOCFG29_SLEW_RED_BITN 12 -#define IOC_IOCFG29_SLEW_RED_M 0x00001000 -#define IOC_IOCFG29_SLEW_RED_S 12 +#define IOC_IOCFG29_SLEW_RED 0x00001000 +#define IOC_IOCFG29_SLEW_RED_BITN 12 +#define IOC_IOCFG29_SLEW_RED_M 0x00001000 +#define IOC_IOCFG29_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -9065,12 +9065,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG29_IOCURR_W 2 -#define IOC_IOCFG29_IOCURR_M 0x00000C00 -#define IOC_IOCFG29_IOCURR_S 10 -#define IOC_IOCFG29_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG29_IOCURR_4MA 0x00000400 -#define IOC_IOCFG29_IOCURR_2MA 0x00000000 +#define IOC_IOCFG29_IOCURR_W 2 +#define IOC_IOCFG29_IOCURR_M 0x00000C00 +#define IOC_IOCFG29_IOCURR_S 10 +#define IOC_IOCFG29_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG29_IOCURR_4MA 0x00000400 +#define IOC_IOCFG29_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -9089,13 +9089,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG29_IOSTR_W 2 -#define IOC_IOCFG29_IOSTR_M 0x00000300 -#define IOC_IOCFG29_IOSTR_S 8 -#define IOC_IOCFG29_IOSTR_MAX 0x00000300 -#define IOC_IOCFG29_IOSTR_MED 0x00000200 -#define IOC_IOCFG29_IOSTR_MIN 0x00000100 -#define IOC_IOCFG29_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG29_IOSTR_W 2 +#define IOC_IOCFG29_IOSTR_M 0x00000300 +#define IOC_IOCFG29_IOSTR_S 8 +#define IOC_IOCFG29_IOSTR_MAX 0x00000300 +#define IOC_IOCFG29_IOSTR_MED 0x00000200 +#define IOC_IOCFG29_IOSTR_MIN 0x00000100 +#define IOC_IOCFG29_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -9183,51 +9183,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG29_PORT_ID_W 6 -#define IOC_IOCFG29_PORT_ID_M 0x0000003F -#define IOC_IOCFG29_PORT_ID_S 0 -#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG29_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG29_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG29_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG29_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG29_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG29_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG29_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG29_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG29_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG29_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG29_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG29_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG29_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG29_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG29_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG29_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG29_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG29_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG29_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG29_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG29_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG29_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG29_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG29_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG29_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG29_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG29_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG29_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG29_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG29_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG29_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG29_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG29_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG29_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG29_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG29_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG29_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG29_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG29_PORT_ID_W 6 +#define IOC_IOCFG29_PORT_ID_M 0x0000003F +#define IOC_IOCFG29_PORT_ID_S 0 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG29_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG29_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG29_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG29_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG29_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG29_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG29_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG29_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG29_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG29_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG29_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG29_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG29_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG29_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG29_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG29_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG29_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG29_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG29_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG29_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG29_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG29_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG29_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG29_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG29_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG29_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG29_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG29_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG29_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG29_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG29_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG29_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG29_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG29_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG29_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -9238,10 +9238,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG30_HYST_EN 0x40000000 -#define IOC_IOCFG30_HYST_EN_BITN 30 -#define IOC_IOCFG30_HYST_EN_M 0x40000000 -#define IOC_IOCFG30_HYST_EN_S 30 +#define IOC_IOCFG30_HYST_EN 0x40000000 +#define IOC_IOCFG30_HYST_EN_BITN 30 +#define IOC_IOCFG30_HYST_EN_M 0x40000000 +#define IOC_IOCFG30_HYST_EN_S 30 // Field: [29] IE // @@ -9250,10 +9250,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG30_IE 0x20000000 -#define IOC_IOCFG30_IE_BITN 29 -#define IOC_IOCFG30_IE_M 0x20000000 -#define IOC_IOCFG30_IE_S 29 +#define IOC_IOCFG30_IE 0x20000000 +#define IOC_IOCFG30_IE_BITN 29 +#define IOC_IOCFG30_IE_M 0x20000000 +#define IOC_IOCFG30_IE_S 29 // Field: [28:27] WU_CFG // @@ -9275,9 +9275,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG30_WU_CFG_W 2 -#define IOC_IOCFG30_WU_CFG_M 0x18000000 -#define IOC_IOCFG30_WU_CFG_S 27 +#define IOC_IOCFG30_WU_CFG_W 2 +#define IOC_IOCFG30_WU_CFG_M 0x18000000 +#define IOC_IOCFG30_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -9298,25 +9298,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG30_IOMODE_W 3 -#define IOC_IOCFG30_IOMODE_M 0x07000000 -#define IOC_IOCFG30_IOMODE_S 24 -#define IOC_IOCFG30_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG30_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG30_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG30_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG30_IOMODE_INV 0x01000000 -#define IOC_IOCFG30_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG30_IOMODE_W 3 +#define IOC_IOCFG30_IOMODE_M 0x07000000 +#define IOC_IOCFG30_IOMODE_S 24 +#define IOC_IOCFG30_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG30_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG30_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG30_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG30_IOMODE_INV 0x01000000 +#define IOC_IOCFG30_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG30_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG30_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG30_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG30_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG30_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG30_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG30_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG30_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -9326,13 +9326,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG30_EDGE_DET_W 2 -#define IOC_IOCFG30_EDGE_DET_M 0x00030000 -#define IOC_IOCFG30_EDGE_DET_S 16 -#define IOC_IOCFG30_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG30_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG30_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG30_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG30_EDGE_DET_W 2 +#define IOC_IOCFG30_EDGE_DET_M 0x00030000 +#define IOC_IOCFG30_EDGE_DET_S 16 +#define IOC_IOCFG30_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG30_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG30_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG30_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -9341,21 +9341,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG30_PULL_CTL_W 2 -#define IOC_IOCFG30_PULL_CTL_M 0x00006000 -#define IOC_IOCFG30_PULL_CTL_S 13 -#define IOC_IOCFG30_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG30_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG30_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG30_PULL_CTL_W 2 +#define IOC_IOCFG30_PULL_CTL_M 0x00006000 +#define IOC_IOCFG30_PULL_CTL_S 13 +#define IOC_IOCFG30_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG30_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG30_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG30_SLEW_RED 0x00001000 -#define IOC_IOCFG30_SLEW_RED_BITN 12 -#define IOC_IOCFG30_SLEW_RED_M 0x00001000 -#define IOC_IOCFG30_SLEW_RED_S 12 +#define IOC_IOCFG30_SLEW_RED 0x00001000 +#define IOC_IOCFG30_SLEW_RED_BITN 12 +#define IOC_IOCFG30_SLEW_RED_M 0x00001000 +#define IOC_IOCFG30_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -9368,12 +9368,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG30_IOCURR_W 2 -#define IOC_IOCFG30_IOCURR_M 0x00000C00 -#define IOC_IOCFG30_IOCURR_S 10 -#define IOC_IOCFG30_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG30_IOCURR_4MA 0x00000400 -#define IOC_IOCFG30_IOCURR_2MA 0x00000000 +#define IOC_IOCFG30_IOCURR_W 2 +#define IOC_IOCFG30_IOCURR_M 0x00000C00 +#define IOC_IOCFG30_IOCURR_S 10 +#define IOC_IOCFG30_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG30_IOCURR_4MA 0x00000400 +#define IOC_IOCFG30_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -9392,13 +9392,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG30_IOSTR_W 2 -#define IOC_IOCFG30_IOSTR_M 0x00000300 -#define IOC_IOCFG30_IOSTR_S 8 -#define IOC_IOCFG30_IOSTR_MAX 0x00000300 -#define IOC_IOCFG30_IOSTR_MED 0x00000200 -#define IOC_IOCFG30_IOSTR_MIN 0x00000100 -#define IOC_IOCFG30_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG30_IOSTR_W 2 +#define IOC_IOCFG30_IOSTR_M 0x00000300 +#define IOC_IOCFG30_IOSTR_S 8 +#define IOC_IOCFG30_IOSTR_MAX 0x00000300 +#define IOC_IOCFG30_IOSTR_MED 0x00000200 +#define IOC_IOCFG30_IOSTR_MIN 0x00000100 +#define IOC_IOCFG30_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -9486,51 +9486,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG30_PORT_ID_W 6 -#define IOC_IOCFG30_PORT_ID_M 0x0000003F -#define IOC_IOCFG30_PORT_ID_S 0 -#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG30_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG30_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG30_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG30_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG30_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG30_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG30_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG30_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG30_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG30_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG30_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG30_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG30_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG30_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG30_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG30_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG30_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG30_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG30_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG30_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG30_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG30_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG30_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG30_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG30_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG30_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG30_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG30_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG30_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG30_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG30_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG30_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG30_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG30_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG30_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG30_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG30_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG30_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG30_PORT_ID_W 6 +#define IOC_IOCFG30_PORT_ID_M 0x0000003F +#define IOC_IOCFG30_PORT_ID_S 0 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG30_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG30_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG30_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG30_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG30_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG30_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG30_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG30_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG30_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG30_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG30_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG30_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG30_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG30_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG30_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG30_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG30_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG30_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG30_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG30_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG30_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG30_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG30_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG30_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG30_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG30_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG30_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG30_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG30_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG30_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG30_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG30_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG30_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG30_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG30_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -9541,10 +9541,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG31_HYST_EN 0x40000000 -#define IOC_IOCFG31_HYST_EN_BITN 30 -#define IOC_IOCFG31_HYST_EN_M 0x40000000 -#define IOC_IOCFG31_HYST_EN_S 30 +#define IOC_IOCFG31_HYST_EN 0x40000000 +#define IOC_IOCFG31_HYST_EN_BITN 30 +#define IOC_IOCFG31_HYST_EN_M 0x40000000 +#define IOC_IOCFG31_HYST_EN_S 30 // Field: [29] IE // @@ -9553,10 +9553,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG31_IE 0x20000000 -#define IOC_IOCFG31_IE_BITN 29 -#define IOC_IOCFG31_IE_M 0x20000000 -#define IOC_IOCFG31_IE_S 29 +#define IOC_IOCFG31_IE 0x20000000 +#define IOC_IOCFG31_IE_BITN 29 +#define IOC_IOCFG31_IE_M 0x20000000 +#define IOC_IOCFG31_IE_S 29 // Field: [28:27] WU_CFG // @@ -9578,9 +9578,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG31_WU_CFG_W 2 -#define IOC_IOCFG31_WU_CFG_M 0x18000000 -#define IOC_IOCFG31_WU_CFG_S 27 +#define IOC_IOCFG31_WU_CFG_W 2 +#define IOC_IOCFG31_WU_CFG_M 0x18000000 +#define IOC_IOCFG31_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -9601,25 +9601,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG31_IOMODE_W 3 -#define IOC_IOCFG31_IOMODE_M 0x07000000 -#define IOC_IOCFG31_IOMODE_S 24 -#define IOC_IOCFG31_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG31_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG31_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG31_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG31_IOMODE_INV 0x01000000 -#define IOC_IOCFG31_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG31_IOMODE_W 3 +#define IOC_IOCFG31_IOMODE_M 0x07000000 +#define IOC_IOCFG31_IOMODE_S 24 +#define IOC_IOCFG31_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG31_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG31_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG31_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG31_IOMODE_INV 0x01000000 +#define IOC_IOCFG31_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG31_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG31_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG31_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG31_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG31_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG31_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG31_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG31_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -9629,13 +9629,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG31_EDGE_DET_W 2 -#define IOC_IOCFG31_EDGE_DET_M 0x00030000 -#define IOC_IOCFG31_EDGE_DET_S 16 -#define IOC_IOCFG31_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG31_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG31_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG31_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG31_EDGE_DET_W 2 +#define IOC_IOCFG31_EDGE_DET_M 0x00030000 +#define IOC_IOCFG31_EDGE_DET_S 16 +#define IOC_IOCFG31_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG31_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG31_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG31_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -9644,21 +9644,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG31_PULL_CTL_W 2 -#define IOC_IOCFG31_PULL_CTL_M 0x00006000 -#define IOC_IOCFG31_PULL_CTL_S 13 -#define IOC_IOCFG31_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG31_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG31_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG31_PULL_CTL_W 2 +#define IOC_IOCFG31_PULL_CTL_M 0x00006000 +#define IOC_IOCFG31_PULL_CTL_S 13 +#define IOC_IOCFG31_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG31_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG31_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG31_SLEW_RED 0x00001000 -#define IOC_IOCFG31_SLEW_RED_BITN 12 -#define IOC_IOCFG31_SLEW_RED_M 0x00001000 -#define IOC_IOCFG31_SLEW_RED_S 12 +#define IOC_IOCFG31_SLEW_RED 0x00001000 +#define IOC_IOCFG31_SLEW_RED_BITN 12 +#define IOC_IOCFG31_SLEW_RED_M 0x00001000 +#define IOC_IOCFG31_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -9671,12 +9671,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG31_IOCURR_W 2 -#define IOC_IOCFG31_IOCURR_M 0x00000C00 -#define IOC_IOCFG31_IOCURR_S 10 -#define IOC_IOCFG31_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG31_IOCURR_4MA 0x00000400 -#define IOC_IOCFG31_IOCURR_2MA 0x00000000 +#define IOC_IOCFG31_IOCURR_W 2 +#define IOC_IOCFG31_IOCURR_M 0x00000C00 +#define IOC_IOCFG31_IOCURR_S 10 +#define IOC_IOCFG31_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG31_IOCURR_4MA 0x00000400 +#define IOC_IOCFG31_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -9695,13 +9695,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG31_IOSTR_W 2 -#define IOC_IOCFG31_IOSTR_M 0x00000300 -#define IOC_IOCFG31_IOSTR_S 8 -#define IOC_IOCFG31_IOSTR_MAX 0x00000300 -#define IOC_IOCFG31_IOSTR_MED 0x00000200 -#define IOC_IOCFG31_IOSTR_MIN 0x00000100 -#define IOC_IOCFG31_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG31_IOSTR_W 2 +#define IOC_IOCFG31_IOSTR_M 0x00000300 +#define IOC_IOCFG31_IOSTR_S 8 +#define IOC_IOCFG31_IOSTR_MAX 0x00000300 +#define IOC_IOCFG31_IOSTR_MED 0x00000200 +#define IOC_IOCFG31_IOSTR_MIN 0x00000100 +#define IOC_IOCFG31_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -9789,51 +9789,50 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG31_PORT_ID_W 6 -#define IOC_IOCFG31_PORT_ID_M 0x0000003F -#define IOC_IOCFG31_PORT_ID_S 0 -#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG31_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG31_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG31_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG31_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG31_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG31_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG31_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG31_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG31_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG31_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG31_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG31_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG31_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG31_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG31_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG31_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG31_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG31_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG31_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG31_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG31_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG31_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG31_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG31_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG31_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG31_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG31_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG31_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG31_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG31_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG31_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG31_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG31_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG31_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG31_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG31_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG31_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG31_PORT_ID_GPIO 0x00000000 - +#define IOC_IOCFG31_PORT_ID_W 6 +#define IOC_IOCFG31_PORT_ID_M 0x0000003F +#define IOC_IOCFG31_PORT_ID_S 0 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG31_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG31_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG31_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG31_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG31_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG31_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG31_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG31_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG31_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG31_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG31_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG31_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG31_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG31_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG31_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG31_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG31_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG31_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG31_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG31_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG31_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG31_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG31_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG31_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG31_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG31_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG31_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG31_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG31_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG31_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG31_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG31_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG31_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG31_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG31_PORT_ID_GPIO 0x00000000 #endif // __IOC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_memmap.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_memmap.h index cfad06d..ef94ddc 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_memmap.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_memmap.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_memmap_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_memmap_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_MEMMAP_H__ #define __HW_MEMMAP_H__ @@ -43,116 +43,116 @@ // peripherals on the CPU_MMAP interface // //***************************************************************************** -#define FLASHMEM_BASE 0x00000000 // FLASHMEM -#define BROM_BASE 0x10000000 // BROM -#define GPRAM_BASE 0x11000000 // GPRAM -#define SRAM_BASE 0x20000000 // SRAM -#define RFC_RAM_BASE 0x21000000 // RFC_RAM -#define SSI0_BASE 0x40000000 // SSI -#define UART0_BASE 0x40001000 // UART -#define I2C0_BASE 0x40002000 // I2C -#define SSI1_BASE 0x40008000 // SSI -#define GPT0_BASE 0x40010000 // GPT -#define GPT1_BASE 0x40011000 // GPT -#define GPT2_BASE 0x40012000 // GPT -#define GPT3_BASE 0x40013000 // GPT -#define UDMA0_BASE 0x40020000 // UDMA -#define I2S0_BASE 0x40021000 // I2S -#define GPIO_BASE 0x40022000 // GPIO -#define CRYPTO_BASE 0x40024000 // CRYPTO -#define TRNG_BASE 0x40028000 // TRNG -#define FLASH_BASE 0x40030000 // FLASH -#define VIMS_BASE 0x40034000 // VIMS -#define RFC_PWR_BASE 0x40040000 // RFC_PWR -#define RFC_DBELL_BASE 0x40041000 // RFC_DBELL -#define RFC_RAT_BASE 0x40043000 // RFC_RAT -#define RFC_FSCA_BASE 0x40044000 // RFC_FSCA -#define WDT_BASE 0x40080000 // WDT -#define IOC_BASE 0x40081000 // IOC -#define PRCM_BASE 0x40082000 // PRCM -#define EVENT_BASE 0x40083000 // EVENT -#define SMPH_BASE 0x40084000 // SMPH -#define ADI2_BASE 0x40086000 // ADI -#define ADI3_BASE 0x40086200 // ADI -#define AON_SYSCTL_BASE 0x40090000 // AON_SYSCTL -#define AON_WUC_BASE 0x40091000 // AON_WUC -#define AON_RTC_BASE 0x40092000 // AON_RTC -#define AON_EVENT_BASE 0x40093000 // AON_EVENT -#define AON_IOC_BASE 0x40094000 // AON_IOC -#define AON_BATMON_BASE 0x40095000 // AON_BATMON -#define AUX_AIODIO0_BASE 0x400C1000 // AUX_AIODIO -#define AUX_AIODIO1_BASE 0x400C2000 // AUX_AIODIO -#define AUX_TDC_BASE 0x400C4000 // AUX_TDC -#define AUX_EVCTL_BASE 0x400C5000 // AUX_EVCTL -#define AUX_WUC_BASE 0x400C6000 // AUX_WUC -#define AUX_TIMER_BASE 0x400C7000 // AUX_TIMER -#define AUX_SMPH_BASE 0x400C8000 // AUX_SMPH -#define AUX_ANAIF_BASE 0x400C9000 // AUX_ANAIF -#define AUX_DDI0_OSC_BASE 0x400CA000 // DDI -#define AUX_ADI4_BASE 0x400CB000 // ADI -#define AUX_RAM_BASE 0x400E0000 // AUX_RAM -#define AUX_SCE_BASE 0x400E1000 // AUX_SCE -#define FLASH_CFG_BASE 0x50000000 // CC26_DUMMY_COMP -#define FCFG1_BASE 0x50001000 // FCFG1 -#define FCFG2_BASE 0x50002000 // FCFG2 +#define FLASHMEM_BASE 0x00000000 // FLASHMEM +#define BROM_BASE 0x10000000 // BROM +#define GPRAM_BASE 0x11000000 // GPRAM +#define SRAM_BASE 0x20000000 // SRAM +#define RFC_RAM_BASE 0x21000000 // RFC_RAM +#define SSI0_BASE 0x40000000 // SSI +#define UART0_BASE 0x40001000 // UART +#define I2C0_BASE 0x40002000 // I2C +#define SSI1_BASE 0x40008000 // SSI +#define GPT0_BASE 0x40010000 // GPT +#define GPT1_BASE 0x40011000 // GPT +#define GPT2_BASE 0x40012000 // GPT +#define GPT3_BASE 0x40013000 // GPT +#define UDMA0_BASE 0x40020000 // UDMA +#define I2S0_BASE 0x40021000 // I2S +#define GPIO_BASE 0x40022000 // GPIO +#define CRYPTO_BASE 0x40024000 // CRYPTO +#define TRNG_BASE 0x40028000 // TRNG +#define FLASH_BASE 0x40030000 // FLASH +#define VIMS_BASE 0x40034000 // VIMS +#define RFC_PWR_BASE 0x40040000 // RFC_PWR +#define RFC_DBELL_BASE 0x40041000 // RFC_DBELL +#define RFC_RAT_BASE 0x40043000 // RFC_RAT +#define RFC_FSCA_BASE 0x40044000 // RFC_FSCA +#define WDT_BASE 0x40080000 // WDT +#define IOC_BASE 0x40081000 // IOC +#define PRCM_BASE 0x40082000 // PRCM +#define EVENT_BASE 0x40083000 // EVENT +#define SMPH_BASE 0x40084000 // SMPH +#define ADI2_BASE 0x40086000 // ADI +#define ADI3_BASE 0x40086200 // ADI +#define AON_SYSCTL_BASE 0x40090000 // AON_SYSCTL +#define AON_WUC_BASE 0x40091000 // AON_WUC +#define AON_RTC_BASE 0x40092000 // AON_RTC +#define AON_EVENT_BASE 0x40093000 // AON_EVENT +#define AON_IOC_BASE 0x40094000 // AON_IOC +#define AON_BATMON_BASE 0x40095000 // AON_BATMON +#define AUX_AIODIO0_BASE 0x400C1000 // AUX_AIODIO +#define AUX_AIODIO1_BASE 0x400C2000 // AUX_AIODIO +#define AUX_TDC_BASE 0x400C4000 // AUX_TDC +#define AUX_EVCTL_BASE 0x400C5000 // AUX_EVCTL +#define AUX_WUC_BASE 0x400C6000 // AUX_WUC +#define AUX_TIMER_BASE 0x400C7000 // AUX_TIMER +#define AUX_SMPH_BASE 0x400C8000 // AUX_SMPH +#define AUX_ANAIF_BASE 0x400C9000 // AUX_ANAIF +#define AUX_DDI0_OSC_BASE 0x400CA000 // DDI +#define AUX_ADI4_BASE 0x400CB000 // ADI +#define AUX_RAM_BASE 0x400E0000 // AUX_RAM +#define AUX_SCE_BASE 0x400E1000 // AUX_SCE +#define FLASH_CFG_BASE 0x50000000 // CC26_DUMMY_COMP +#define FCFG1_BASE 0x50001000 // FCFG1 +#define FCFG2_BASE 0x50002000 // FCFG2 #ifndef CCFG_BASE - #define CCFG_BASE 0x50003000 // CCFG +#define CCFG_BASE 0x50003000 // CCFG #endif -#define CCFG_BASE_DEFAULT 0x50003000 // CCFG -#define SSI0_NONBUF_BASE 0x60000000 // SSI CPU nonbuf base -#define UART0_NONBUF_BASE 0x60001000 // UART CPU nonbuf base -#define I2C0_NONBUF_BASE 0x60002000 // I2C CPU nonbuf base -#define SSI1_NONBUF_BASE 0x60008000 // SSI CPU nonbuf base -#define GPT0_NONBUF_BASE 0x60010000 // GPT CPU nonbuf base -#define GPT1_NONBUF_BASE 0x60011000 // GPT CPU nonbuf base -#define GPT2_NONBUF_BASE 0x60012000 // GPT CPU nonbuf base -#define GPT3_NONBUF_BASE 0x60013000 // GPT CPU nonbuf base -#define UDMA0_NONBUF_BASE 0x60020000 // UDMA CPU nonbuf base -#define I2S0_NONBUF_BASE 0x60021000 // I2S CPU nonbuf base -#define GPIO_NONBUF_BASE 0x60022000 // GPIO CPU nonbuf base -#define CRYPTO_NONBUF_BASE 0x60024000 // CRYPTO CPU nonbuf base -#define TRNG_NONBUF_BASE 0x60028000 // TRNG CPU nonbuf base -#define FLASH_NONBUF_BASE 0x60030000 // FLASH CPU nonbuf base -#define VIMS_NONBUF_BASE 0x60034000 // VIMS CPU nonbuf base -#define RFC_PWR_NONBUF_BASE 0x60040000 // RFC_PWR CPU nonbuf base -#define RFC_DBELL_NONBUF_BASE 0x60041000 // RFC_DBELL CPU nonbuf base -#define RFC_RAT_NONBUF_BASE 0x60043000 // RFC_RAT CPU nonbuf base -#define RFC_FSCA_NONBUF_BASE 0x60044000 // RFC_FSCA CPU nonbuf base -#define WDT_NONBUF_BASE 0x60080000 // WDT CPU nonbuf base -#define IOC_NONBUF_BASE 0x60081000 // IOC CPU nonbuf base -#define PRCM_NONBUF_BASE 0x60082000 // PRCM CPU nonbuf base -#define EVENT_NONBUF_BASE 0x60083000 // EVENT CPU nonbuf base -#define SMPH_NONBUF_BASE 0x60084000 // SMPH CPU nonbuf base -#define ADI2_NONBUF_BASE 0x60086000 // ADI CPU nonbuf base -#define ADI3_NONBUF_BASE 0x60086200 // ADI CPU nonbuf base -#define AON_SYSCTL_NONBUF_BASE 0x60090000 // AON_SYSCTL CPU nonbuf base -#define AON_WUC_NONBUF_BASE 0x60091000 // AON_WUC CPU nonbuf base -#define AON_RTC_NONBUF_BASE 0x60092000 // AON_RTC CPU nonbuf base -#define AON_EVENT_NONBUF_BASE 0x60093000 // AON_EVENT CPU nonbuf base -#define AON_IOC_NONBUF_BASE 0x60094000 // AON_IOC CPU nonbuf base -#define AON_BATMON_NONBUF_BASE 0x60095000 // AON_BATMON CPU nonbuf base +#define CCFG_BASE_DEFAULT 0x50003000 // CCFG +#define SSI0_NONBUF_BASE 0x60000000 // SSI CPU nonbuf base +#define UART0_NONBUF_BASE 0x60001000 // UART CPU nonbuf base +#define I2C0_NONBUF_BASE 0x60002000 // I2C CPU nonbuf base +#define SSI1_NONBUF_BASE 0x60008000 // SSI CPU nonbuf base +#define GPT0_NONBUF_BASE 0x60010000 // GPT CPU nonbuf base +#define GPT1_NONBUF_BASE 0x60011000 // GPT CPU nonbuf base +#define GPT2_NONBUF_BASE 0x60012000 // GPT CPU nonbuf base +#define GPT3_NONBUF_BASE 0x60013000 // GPT CPU nonbuf base +#define UDMA0_NONBUF_BASE 0x60020000 // UDMA CPU nonbuf base +#define I2S0_NONBUF_BASE 0x60021000 // I2S CPU nonbuf base +#define GPIO_NONBUF_BASE 0x60022000 // GPIO CPU nonbuf base +#define CRYPTO_NONBUF_BASE 0x60024000 // CRYPTO CPU nonbuf base +#define TRNG_NONBUF_BASE 0x60028000 // TRNG CPU nonbuf base +#define FLASH_NONBUF_BASE 0x60030000 // FLASH CPU nonbuf base +#define VIMS_NONBUF_BASE 0x60034000 // VIMS CPU nonbuf base +#define RFC_PWR_NONBUF_BASE 0x60040000 // RFC_PWR CPU nonbuf base +#define RFC_DBELL_NONBUF_BASE 0x60041000 // RFC_DBELL CPU nonbuf base +#define RFC_RAT_NONBUF_BASE 0x60043000 // RFC_RAT CPU nonbuf base +#define RFC_FSCA_NONBUF_BASE 0x60044000 // RFC_FSCA CPU nonbuf base +#define WDT_NONBUF_BASE 0x60080000 // WDT CPU nonbuf base +#define IOC_NONBUF_BASE 0x60081000 // IOC CPU nonbuf base +#define PRCM_NONBUF_BASE 0x60082000 // PRCM CPU nonbuf base +#define EVENT_NONBUF_BASE 0x60083000 // EVENT CPU nonbuf base +#define SMPH_NONBUF_BASE 0x60084000 // SMPH CPU nonbuf base +#define ADI2_NONBUF_BASE 0x60086000 // ADI CPU nonbuf base +#define ADI3_NONBUF_BASE 0x60086200 // ADI CPU nonbuf base +#define AON_SYSCTL_NONBUF_BASE 0x60090000 // AON_SYSCTL CPU nonbuf base +#define AON_WUC_NONBUF_BASE 0x60091000 // AON_WUC CPU nonbuf base +#define AON_RTC_NONBUF_BASE 0x60092000 // AON_RTC CPU nonbuf base +#define AON_EVENT_NONBUF_BASE 0x60093000 // AON_EVENT CPU nonbuf base +#define AON_IOC_NONBUF_BASE 0x60094000 // AON_IOC CPU nonbuf base +#define AON_BATMON_NONBUF_BASE 0x60095000 // AON_BATMON CPU nonbuf base #define AUX_AIODIO0_NONBUF_BASE \ 0x600C1000 // AUX_AIODIO CPU nonbuf base #define AUX_AIODIO1_NONBUF_BASE \ - 0x600C2000 // AUX_AIODIO CPU nonbuf base -#define AUX_TDC_NONBUF_BASE 0x600C4000 // AUX_TDC CPU nonbuf base -#define AUX_EVCTL_NONBUF_BASE 0x600C5000 // AUX_EVCTL CPU nonbuf base -#define AUX_WUC_NONBUF_BASE 0x600C6000 // AUX_WUC CPU nonbuf base -#define AUX_TIMER_NONBUF_BASE 0x600C7000 // AUX_TIMER CPU nonbuf base -#define AUX_SMPH_NONBUF_BASE 0x600C8000 // AUX_SMPH CPU nonbuf base -#define AUX_ANAIF_NONBUF_BASE 0x600C9000 // AUX_ANAIF CPU nonbuf base + 0x600C2000 // AUX_AIODIO CPU nonbuf base +#define AUX_TDC_NONBUF_BASE 0x600C4000 // AUX_TDC CPU nonbuf base +#define AUX_EVCTL_NONBUF_BASE 0x600C5000 // AUX_EVCTL CPU nonbuf base +#define AUX_WUC_NONBUF_BASE 0x600C6000 // AUX_WUC CPU nonbuf base +#define AUX_TIMER_NONBUF_BASE 0x600C7000 // AUX_TIMER CPU nonbuf base +#define AUX_SMPH_NONBUF_BASE 0x600C8000 // AUX_SMPH CPU nonbuf base +#define AUX_ANAIF_NONBUF_BASE 0x600C9000 // AUX_ANAIF CPU nonbuf base #define AUX_DDI0_OSC_NONBUF_BASE \ - 0x600CA000 // DDI CPU nonbuf base -#define AUX_ADI4_NONBUF_BASE 0x600CB000 // ADI CPU nonbuf base -#define AUX_RAM_NONBUF_BASE 0x600E0000 // AUX_RAM CPU nonbuf base -#define AUX_SCE_NONBUF_BASE 0x600E1000 // AUX_SCE CPU nonbuf base -#define FLASHMEM_ALIAS_BASE 0xA0000000 // FLASHMEM Alias base -#define CPU_ITM_BASE 0xE0000000 // CPU_ITM -#define CPU_DWT_BASE 0xE0001000 // CPU_DWT -#define CPU_FPB_BASE 0xE0002000 // CPU_FPB -#define CPU_SCS_BASE 0xE000E000 // CPU_SCS -#define CPU_TPIU_BASE 0xE0040000 // CPU_TPIU -#define CPU_TIPROP_BASE 0xE00FE000 // CPU_TIPROP -#define CPU_ROM_TABLE_BASE 0xE00FF000 // CPU_ROM_TABLE + 0x600CA000 // DDI CPU nonbuf base +#define AUX_ADI4_NONBUF_BASE 0x600CB000 // ADI CPU nonbuf base +#define AUX_RAM_NONBUF_BASE 0x600E0000 // AUX_RAM CPU nonbuf base +#define AUX_SCE_NONBUF_BASE 0x600E1000 // AUX_SCE CPU nonbuf base +#define FLASHMEM_ALIAS_BASE 0xA0000000 // FLASHMEM Alias base +#define CPU_ITM_BASE 0xE0000000 // CPU_ITM +#define CPU_DWT_BASE 0xE0001000 // CPU_DWT +#define CPU_FPB_BASE 0xE0002000 // CPU_FPB +#define CPU_SCS_BASE 0xE000E000 // CPU_SCS +#define CPU_TPIU_BASE 0xE0040000 // CPU_TPIU +#define CPU_TIPROP_BASE 0xE00FE000 // CPU_TIPROP +#define CPU_ROM_TABLE_BASE 0xE00FF000 // CPU_ROM_TABLE #endif // __HW_MEMMAP__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_nvic.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_nvic.h index 6f1f2d0..4ee246d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_nvic.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_nvic.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_nvic.h -* Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) -* Revision: 42365 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_nvic.h + * Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) + * Revision: 42365 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_NVIC_H__ #define __HW_NVIC_H__ @@ -42,89 +42,89 @@ // The following are defines for the NVIC register addresses. // //***************************************************************************** -#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg -#define NVIC_ACTLR 0xE000E008 // Auxiliary Control -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg +#define NVIC_ACTLR 0xE000E008 // Auxiliary Control +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status // Register -#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register -#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register -#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg -#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable -#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable -#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable -#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable -#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending -#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending -#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending -#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending -#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit -#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit -#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority -#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority -#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority -#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority -#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority -#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority -#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority -#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority -#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority -#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority -#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority -#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority -#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority -#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority -#define NVIC_CPUID 0xE000ED00 // CPU ID Base -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset -#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg +#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable +#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable +#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable +#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable +#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending +#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending +#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending +#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending +#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit +#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit +#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority +#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority +#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority +#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority +#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority +#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority +#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority +#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority +#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority +#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority +#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority +#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority +#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority +#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority +#define NVIC_CPUID 0xE000ED00 // CPU ID Base +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset +#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset // Control -#define NVIC_SYS_CTRL 0xE000ED10 // System Control -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control -#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 -#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 -#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 -#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status -#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size -#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 -#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size +#define NVIC_SYS_CTRL 0xE000ED10 // System Control +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control +#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 +#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 +#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size +#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 +#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size // Alias 1 -#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 -#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size +#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 +#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size // Alias 2 -#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 -#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size +#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 +#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size // Alias 3 -#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg -#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select -#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data -#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt //***************************************************************************** // // The following are defines for the bit fields in the NVIC_INT_TYPE register. // //***************************************************************************** -#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) -#define NVIC_INT_TYPE_LINES_S 0 +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_ACTLR register. // //***************************************************************************** -#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding -#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer -#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple // Cycle Instructions //***************************************************************************** @@ -132,18 +132,18 @@ // The following are defines for the bit fields in the NVIC_ST_CTRL register. // //***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable //***************************************************************************** // // The following are defines for the bit fields in the NVIC_ST_RELOAD register. // //***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value -#define NVIC_ST_RELOAD_S 0 +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value +#define NVIC_ST_RELOAD_S 0 //***************************************************************************** // @@ -151,609 +151,609 @@ // register. // //***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value -#define NVIC_ST_CURRENT_S 0 +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value +#define NVIC_ST_CURRENT_S 0 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_ST_CAL register. // //***************************************************************************** -#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock -#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew -#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value -#define NVIC_ST_CAL_ONEMS_S 0 +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_EN0 register. // //***************************************************************************** -#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable -#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable //***************************************************************************** // // The following are defines for the bit fields in the NVIC_EN1 register. // //***************************************************************************** -#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable -#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable -#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable -#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable -#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable -#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable -#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable -#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable -#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable -#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable -#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable -#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable -#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable -#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable -#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable -#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable -#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable -#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable -#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable -#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable -#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable -#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable -#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable -#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable +#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable +#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable +#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable +#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable +#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable +#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable +#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable +#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable +#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable +#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable +#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable +#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable +#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable +#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable +#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable +#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable +#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable +#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable +#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable +#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable +#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable +#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable +#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable +#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable //***************************************************************************** // // The following are defines for the bit fields in the NVIC_DIS0 register. // //***************************************************************************** -#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable -#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable //***************************************************************************** // // The following are defines for the bit fields in the NVIC_DIS1 register. // //***************************************************************************** -#define NVIC_DIS1_INT_M 0x007FFFFF // Interrupt Disable -#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable -#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable -#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable -#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable -#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable -#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable -#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable -#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable -#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable -#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable -#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable -#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable -#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable -#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable -#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable -#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable -#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable -#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable -#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable -#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable -#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable -#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable -#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable +#define NVIC_DIS1_INT_M 0x007FFFFF // Interrupt Disable +#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable +#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable +#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable +#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable +#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable +#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable +#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable +#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable +#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable +#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable +#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable +#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable +#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable +#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable +#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable +#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable +#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable +#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable +#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable +#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable +#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable +#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable +#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PEND0 register. // //***************************************************************************** -#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending -#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PEND1 register. // //***************************************************************************** -#define NVIC_PEND1_INT_M 0x007FFFFF // Interrupt Set Pending -#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend -#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend -#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend -#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend -#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend -#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend -#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend -#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend -#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend -#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend -#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend -#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend -#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend -#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend -#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend -#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend -#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend -#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend -#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend -#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend -#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend -#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend -#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend +#define NVIC_PEND1_INT_M 0x007FFFFF // Interrupt Set Pending +#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend +#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend +#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend +#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend +#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend +#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend +#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend +#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend +#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend +#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend +#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend +#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend +#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend +#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend +#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend +#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend +#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend +#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend +#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend +#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend +#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend +#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend +#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend //***************************************************************************** // // The following are defines for the bit fields in the NVIC_UNPEND0 register. // //***************************************************************************** -#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending -#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend //***************************************************************************** // // The following are defines for the bit fields in the NVIC_UNPEND1 register. // //***************************************************************************** -#define NVIC_UNPEND1_INT_M 0x007FFFFF // Interrupt Clear Pending -#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend -#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend -#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend -#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend -#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend -#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend -#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend -#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend -#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend -#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend -#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend -#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend -#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend -#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend -#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend -#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend -#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend -#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend -#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend -#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend -#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend -#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend -#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend +#define NVIC_UNPEND1_INT_M 0x007FFFFF // Interrupt Clear Pending +#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend +#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend +#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend +#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend +#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend +#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend +#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend +#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend +#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend +#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend +#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend +#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend +#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend +#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend +#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend +#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend +#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend +#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend +#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend +#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend +#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend +#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend +#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend //***************************************************************************** // // The following are defines for the bit fields in the NVIC_ACTIVE0 register. // //***************************************************************************** -#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active -#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active //***************************************************************************** // // The following are defines for the bit fields in the NVIC_ACTIVE1 register. // //***************************************************************************** -#define NVIC_ACTIVE1_INT_M 0x007FFFFF // Interrupt Active -#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active -#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active -#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active -#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active -#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active -#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active -#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active -#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active -#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active -#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active -#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active -#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active -#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active -#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active -#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active -#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active -#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active -#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active -#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active -#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active -#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active -#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active -#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active +#define NVIC_ACTIVE1_INT_M 0x007FFFFF // Interrupt Active +#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active +#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active +#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active +#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active +#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active +#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active +#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active +#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active +#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active +#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active +#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active +#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active +#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active +#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active +#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active +#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active +#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active +#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active +#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active +#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active +#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active +#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active +#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI0 register. // //***************************************************************************** -#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask -#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask -#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask -#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask -#define NVIC_PRI0_INT3_S 29 -#define NVIC_PRI0_INT2_S 21 -#define NVIC_PRI0_INT1_S 13 -#define NVIC_PRI0_INT0_S 5 +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI1 register. // //***************************************************************************** -#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask -#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask -#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask -#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask -#define NVIC_PRI1_INT7_S 29 -#define NVIC_PRI1_INT6_S 21 -#define NVIC_PRI1_INT5_S 13 -#define NVIC_PRI1_INT4_S 5 +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI2 register. // //***************************************************************************** -#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask -#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask -#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask -#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask -#define NVIC_PRI2_INT11_S 29 -#define NVIC_PRI2_INT10_S 21 -#define NVIC_PRI2_INT9_S 13 -#define NVIC_PRI2_INT8_S 5 +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI3 register. // //***************************************************************************** -#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask -#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask -#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask -#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask -#define NVIC_PRI3_INT15_S 29 -#define NVIC_PRI3_INT14_S 21 -#define NVIC_PRI3_INT13_S 13 -#define NVIC_PRI3_INT12_S 5 +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI4 register. // //***************************************************************************** -#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask -#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask -#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask -#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask -#define NVIC_PRI4_INT19_S 29 -#define NVIC_PRI4_INT18_S 21 -#define NVIC_PRI4_INT17_S 13 -#define NVIC_PRI4_INT16_S 5 +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI5 register. // //***************************************************************************** -#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask -#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask -#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask -#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask -#define NVIC_PRI5_INT23_S 29 -#define NVIC_PRI5_INT22_S 21 -#define NVIC_PRI5_INT21_S 13 -#define NVIC_PRI5_INT20_S 5 +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI6 register. // //***************************************************************************** -#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask -#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask -#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask -#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask -#define NVIC_PRI6_INT27_S 29 -#define NVIC_PRI6_INT26_S 21 -#define NVIC_PRI6_INT25_S 13 -#define NVIC_PRI6_INT24_S 5 +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI7 register. // //***************************************************************************** -#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask -#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask -#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask -#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask -#define NVIC_PRI7_INT31_S 29 -#define NVIC_PRI7_INT30_S 21 -#define NVIC_PRI7_INT29_S 13 -#define NVIC_PRI7_INT28_S 5 +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI8 register. // //***************************************************************************** -#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask -#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask -#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask -#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask -#define NVIC_PRI8_INT35_S 29 -#define NVIC_PRI8_INT34_S 21 -#define NVIC_PRI8_INT33_S 13 -#define NVIC_PRI8_INT32_S 5 +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI9 register. // //***************************************************************************** -#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask -#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask -#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask -#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask -#define NVIC_PRI9_INT39_S 29 -#define NVIC_PRI9_INT38_S 21 -#define NVIC_PRI9_INT37_S 13 -#define NVIC_PRI9_INT36_S 5 +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI10 register. // //***************************************************************************** -#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask -#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask -#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask -#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask -#define NVIC_PRI10_INT43_S 29 -#define NVIC_PRI10_INT42_S 21 -#define NVIC_PRI10_INT41_S 13 -#define NVIC_PRI10_INT40_S 5 +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI11 register. // //***************************************************************************** -#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask -#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask -#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask -#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask -#define NVIC_PRI11_INT47_S 29 -#define NVIC_PRI11_INT46_S 21 -#define NVIC_PRI11_INT45_S 13 -#define NVIC_PRI11_INT44_S 5 +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI12 register. // //***************************************************************************** -#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask -#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask -#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask -#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask -#define NVIC_PRI12_INT51_S 29 -#define NVIC_PRI12_INT50_S 21 -#define NVIC_PRI12_INT49_S 13 -#define NVIC_PRI12_INT48_S 5 +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI13 register. // //***************************************************************************** -#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask -#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask -#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask -#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask -#define NVIC_PRI13_INT55_S 29 -#define NVIC_PRI13_INT54_S 21 -#define NVIC_PRI13_INT53_S 13 -#define NVIC_PRI13_INT52_S 5 +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_CPUID register. // //***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code -#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number -#define NVIC_CPUID_CON_M 0x000F0000 // Constant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number -#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor -#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor -#define NVIC_CPUID_REV_M 0x0000000F // Revision Number +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number //***************************************************************************** // // The following are defines for the bit fields in the NVIC_INT_CTRL register. // //***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending -#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending -#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number #undef NVIC_INT_CTRL_VEC_PEN_M -#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number #define NVIC_INT_CTRL_VEC_PEN_NMI \ - 0x00002000 // NMI + 0x00002000 // NMI #define NVIC_INT_CTRL_VEC_PEN_HARD \ - 0x00003000 // Hard fault + 0x00003000 // Hard fault #define NVIC_INT_CTRL_VEC_PEN_MEM \ - 0x00004000 // Memory management fault + 0x00004000 // Memory management fault #define NVIC_INT_CTRL_VEC_PEN_BUS \ - 0x00005000 // Bus fault + 0x00005000 // Bus fault #define NVIC_INT_CTRL_VEC_PEN_USG \ - 0x00006000 // Usage fault + 0x00006000 // Usage fault #define NVIC_INT_CTRL_VEC_PEN_SVC \ - 0x0000B000 // SVCall + 0x0000B000 // SVCall #define NVIC_INT_CTRL_VEC_PEN_PNDSV \ - 0x0000E000 // PendSV + 0x0000E000 // PendSV #define NVIC_INT_CTRL_VEC_PEN_TICK \ - 0x0000F000 // SysTick -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base -#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number #undef NVIC_INT_CTRL_VEC_ACT_M -#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number #define NVIC_INT_CTRL_VEC_PEN_S 12 #define NVIC_INT_CTRL_VEC_ACT_S 0 @@ -762,89 +762,89 @@ // The following are defines for the bit fields in the NVIC_VTABLE register. // //***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset +#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset #undef NVIC_VTABLE_OFFSET_M -#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset -#define NVIC_VTABLE_OFFSET_S 9 +#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset +#define NVIC_VTABLE_OFFSET_S 9 #undef NVIC_VTABLE_OFFSET_S -#define NVIC_VTABLE_OFFSET_S 10 +#define NVIC_VTABLE_OFFSET_S 10 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_APINT register. // //***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault -#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset //***************************************************************************** // // The following are defines for the bit fields in the NVIC_SYS_CTRL register. // //***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit //***************************************************************************** // // The following are defines for the bit fields in the NVIC_CFG_CTRL register. // //***************************************************************************** -#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception // Entry -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and // Fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control //***************************************************************************** // // The following are defines for the bit fields in the NVIC_SYS_PRI1 register. // //***************************************************************************** -#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority -#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority -#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority -#define NVIC_SYS_PRI1_USAGE_S 21 -#define NVIC_SYS_PRI1_BUS_S 13 -#define NVIC_SYS_PRI1_MEM_S 5 +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_SYS_PRI2 register. // //***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority -#define NVIC_SYS_PRI2_SVC_S 29 +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_SYS_PRI3 register. // //***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority -#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority -#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority -#define NVIC_SYS_PRI3_TICK_S 29 -#define NVIC_SYS_PRI3_PENDSV_S 21 -#define NVIC_SYS_PRI3_DEBUG_S 5 +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 //***************************************************************************** // @@ -852,21 +852,21 @@ // register. // //***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending -#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending #define NVIC_SYS_HND_CTRL_USAGEP \ - 0x00001000 // Usage Fault Pending -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active //***************************************************************************** // @@ -874,30 +874,30 @@ // register. // //***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage // Fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid -#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy // State Preservation -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error -#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address // Register Valid -#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on // Floating-Point Lazy State // Preservation -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation //***************************************************************************** // @@ -905,9 +905,9 @@ // register. // //***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault //***************************************************************************** // @@ -915,19 +915,19 @@ // register. // //***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request //***************************************************************************** // // The following are defines for the bit fields in the NVIC_MM_ADDR register. // //***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_MM_ADDR_S 0 +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_MM_ADDR_S 0 //***************************************************************************** // @@ -935,92 +935,92 @@ // register. // //***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_FAULT_ADDR_S 0 +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_FAULT_ADDR_S 0 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_DBG_CTRL register. // //***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key #define NVIC_DBG_CTRL_S_RESET_ST \ - 0x02000000 // Core has reset since last read + 0x02000000 // Core has reset since last read #define NVIC_DBG_CTRL_S_RETIRE_ST \ - 0x01000000 // Core has executed insruction + 0x01000000 // Core has executed insruction // since last read -#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up -#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available #define NVIC_DBG_CTRL_C_SNAPSTALL \ - 0x00000020 // Breaks a stalled load/store -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug //***************************************************************************** // // The following are defines for the bit fields in the NVIC_DBG_XFER register. // //***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask //***************************************************************************** // // The following are defines for the bit fields in the NVIC_DBG_DATA register. // //***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_DBG_INT register. // //***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch //***************************************************************************** // // The following are defines for the bit fields in the NVIC_SW_TRIG register. // //***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID -#define NVIC_SW_TRIG_INTID_S 0 +#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID +#define NVIC_SW_TRIG_INTID_S 0 #endif // __HW_NVIC_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_prcm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_prcm.h index 7974ad0..535f69d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_prcm.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_prcm.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_prcm_h -* Revised: 2017-09-14 10:33:07 +0200 (Thu, 14 Sep 2017) -* Revision: 49733 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_prcm_h + * Revised: 2017-09-14 10:33:07 +0200 (Thu, 14 Sep 2017) + * Revision: 49733 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_PRCM_H__ #define __HW_PRCM_H__ @@ -44,181 +44,181 @@ // //***************************************************************************** // Infrastructure Clock Division Factor For Run Mode -#define PRCM_O_INFRCLKDIVR 0x00000000 +#define PRCM_O_INFRCLKDIVR 0x00000000 // Infrastructure Clock Division Factor For Sleep Mode -#define PRCM_O_INFRCLKDIVS 0x00000004 +#define PRCM_O_INFRCLKDIVS 0x00000004 // Infrastructure Clock Division Factor For DeepSleep Mode -#define PRCM_O_INFRCLKDIVDS 0x00000008 +#define PRCM_O_INFRCLKDIVDS 0x00000008 // MCU Voltage Domain Control -#define PRCM_O_VDCTL 0x0000000C +#define PRCM_O_VDCTL 0x0000000C // Load PRCM Settings To CLKCTRL Power Domain -#define PRCM_O_CLKLOADCTL 0x00000028 +#define PRCM_O_CLKLOADCTL 0x00000028 // RFC Clock Gate -#define PRCM_O_RFCCLKG 0x0000002C +#define PRCM_O_RFCCLKG 0x0000002C // VIMS Clock Gate -#define PRCM_O_VIMSCLKG 0x00000030 +#define PRCM_O_VIMSCLKG 0x00000030 // TRNG, CRYPTO And UDMA Clock Gate For Run Mode -#define PRCM_O_SECDMACLKGR 0x0000003C +#define PRCM_O_SECDMACLKGR 0x0000003C // TRNG, CRYPTO And UDMA Clock Gate For Sleep Mode -#define PRCM_O_SECDMACLKGS 0x00000040 +#define PRCM_O_SECDMACLKGS 0x00000040 // TRNG, CRYPTO And UDMA Clock Gate For Deep Sleep Mode -#define PRCM_O_SECDMACLKGDS 0x00000044 +#define PRCM_O_SECDMACLKGDS 0x00000044 // GPIO Clock Gate For Run Mode -#define PRCM_O_GPIOCLKGR 0x00000048 +#define PRCM_O_GPIOCLKGR 0x00000048 // GPIO Clock Gate For Sleep Mode -#define PRCM_O_GPIOCLKGS 0x0000004C +#define PRCM_O_GPIOCLKGS 0x0000004C // GPIO Clock Gate For Deep Sleep Mode -#define PRCM_O_GPIOCLKGDS 0x00000050 +#define PRCM_O_GPIOCLKGDS 0x00000050 // GPT Clock Gate For Run Mode -#define PRCM_O_GPTCLKGR 0x00000054 +#define PRCM_O_GPTCLKGR 0x00000054 // GPT Clock Gate For Sleep Mode -#define PRCM_O_GPTCLKGS 0x00000058 +#define PRCM_O_GPTCLKGS 0x00000058 // GPT Clock Gate For Deep Sleep Mode -#define PRCM_O_GPTCLKGDS 0x0000005C +#define PRCM_O_GPTCLKGDS 0x0000005C // I2C Clock Gate For Run Mode -#define PRCM_O_I2CCLKGR 0x00000060 +#define PRCM_O_I2CCLKGR 0x00000060 // I2C Clock Gate For Sleep Mode -#define PRCM_O_I2CCLKGS 0x00000064 +#define PRCM_O_I2CCLKGS 0x00000064 // I2C Clock Gate For Deep Sleep Mode -#define PRCM_O_I2CCLKGDS 0x00000068 +#define PRCM_O_I2CCLKGDS 0x00000068 // UART Clock Gate For Run Mode -#define PRCM_O_UARTCLKGR 0x0000006C +#define PRCM_O_UARTCLKGR 0x0000006C // UART Clock Gate For Sleep Mode -#define PRCM_O_UARTCLKGS 0x00000070 +#define PRCM_O_UARTCLKGS 0x00000070 // UART Clock Gate For Deep Sleep Mode -#define PRCM_O_UARTCLKGDS 0x00000074 +#define PRCM_O_UARTCLKGDS 0x00000074 // SSI Clock Gate For Run Mode -#define PRCM_O_SSICLKGR 0x00000078 +#define PRCM_O_SSICLKGR 0x00000078 // SSI Clock Gate For Sleep Mode -#define PRCM_O_SSICLKGS 0x0000007C +#define PRCM_O_SSICLKGS 0x0000007C // SSI Clock Gate For Deep Sleep Mode -#define PRCM_O_SSICLKGDS 0x00000080 +#define PRCM_O_SSICLKGDS 0x00000080 // I2S Clock Gate For Run Mode -#define PRCM_O_I2SCLKGR 0x00000084 +#define PRCM_O_I2SCLKGR 0x00000084 // I2S Clock Gate For Sleep Mode -#define PRCM_O_I2SCLKGS 0x00000088 +#define PRCM_O_I2SCLKGS 0x00000088 // I2S Clock Gate For Deep Sleep Mode -#define PRCM_O_I2SCLKGDS 0x0000008C +#define PRCM_O_I2SCLKGDS 0x0000008C // Internal -#define PRCM_O_CPUCLKDIV 0x000000B8 +#define PRCM_O_CPUCLKDIV 0x000000B8 // I2S Clock Control -#define PRCM_O_I2SBCLKSEL 0x000000C8 +#define PRCM_O_I2SBCLKSEL 0x000000C8 // GPT Scalar -#define PRCM_O_GPTCLKDIV 0x000000CC +#define PRCM_O_GPTCLKDIV 0x000000CC // I2S Clock Control -#define PRCM_O_I2SCLKCTL 0x000000D0 +#define PRCM_O_I2SCLKCTL 0x000000D0 // MCLK Division Ratio -#define PRCM_O_I2SMCLKDIV 0x000000D4 +#define PRCM_O_I2SMCLKDIV 0x000000D4 // BCLK Division Ratio -#define PRCM_O_I2SBCLKDIV 0x000000D8 +#define PRCM_O_I2SBCLKDIV 0x000000D8 // WCLK Division Ratio -#define PRCM_O_I2SWCLKDIV 0x000000DC +#define PRCM_O_I2SWCLKDIV 0x000000DC // SW Initiated Resets -#define PRCM_O_SWRESET 0x0000010C +#define PRCM_O_SWRESET 0x0000010C // WARM Reset Control And Status -#define PRCM_O_WARMRESET 0x00000110 +#define PRCM_O_WARMRESET 0x00000110 // Power Domain Control -#define PRCM_O_PDCTL0 0x0000012C +#define PRCM_O_PDCTL0 0x0000012C // RFC Power Domain Control -#define PRCM_O_PDCTL0RFC 0x00000130 +#define PRCM_O_PDCTL0RFC 0x00000130 // SERIAL Power Domain Control -#define PRCM_O_PDCTL0SERIAL 0x00000134 +#define PRCM_O_PDCTL0SERIAL 0x00000134 // PERIPH Power Domain Control -#define PRCM_O_PDCTL0PERIPH 0x00000138 +#define PRCM_O_PDCTL0PERIPH 0x00000138 // Power Domain Status -#define PRCM_O_PDSTAT0 0x00000140 +#define PRCM_O_PDSTAT0 0x00000140 // RFC Power Domain Status -#define PRCM_O_PDSTAT0RFC 0x00000144 +#define PRCM_O_PDSTAT0RFC 0x00000144 // SERIAL Power Domain Status -#define PRCM_O_PDSTAT0SERIAL 0x00000148 +#define PRCM_O_PDSTAT0SERIAL 0x00000148 // PERIPH Power Domain Status -#define PRCM_O_PDSTAT0PERIPH 0x0000014C +#define PRCM_O_PDSTAT0PERIPH 0x0000014C // Power Domain Control -#define PRCM_O_PDCTL1 0x0000017C +#define PRCM_O_PDCTL1 0x0000017C // CPU Power Domain Direct Control -#define PRCM_O_PDCTL1CPU 0x00000184 +#define PRCM_O_PDCTL1CPU 0x00000184 // RFC Power Domain Direct Control -#define PRCM_O_PDCTL1RFC 0x00000188 +#define PRCM_O_PDCTL1RFC 0x00000188 // VIMS Mode Direct Control -#define PRCM_O_PDCTL1VIMS 0x0000018C +#define PRCM_O_PDCTL1VIMS 0x0000018C // Power Manager Status -#define PRCM_O_PDSTAT1 0x00000194 +#define PRCM_O_PDSTAT1 0x00000194 // BUS Power Domain Direct Read Status -#define PRCM_O_PDSTAT1BUS 0x00000198 +#define PRCM_O_PDSTAT1BUS 0x00000198 // RFC Power Domain Direct Read Status -#define PRCM_O_PDSTAT1RFC 0x0000019C +#define PRCM_O_PDSTAT1RFC 0x0000019C // CPU Power Domain Direct Read Status -#define PRCM_O_PDSTAT1CPU 0x000001A0 +#define PRCM_O_PDSTAT1CPU 0x000001A0 // VIMS Mode Direct Read Status -#define PRCM_O_PDSTAT1VIMS 0x000001A4 +#define PRCM_O_PDSTAT1VIMS 0x000001A4 // Control To RFC -#define PRCM_O_RFCBITS 0x000001CC +#define PRCM_O_RFCBITS 0x000001CC // Selected RFC Mode -#define PRCM_O_RFCMODESEL 0x000001D0 +#define PRCM_O_RFCMODESEL 0x000001D0 // Allowed RFC Modes -#define PRCM_O_RFCMODEHWOPT 0x000001D4 +#define PRCM_O_RFCMODEHWOPT 0x000001D4 // Power Profiler Register -#define PRCM_O_PWRPROFSTAT 0x000001E0 +#define PRCM_O_PWRPROFSTAT 0x000001E0 // Memory Retention Control -#define PRCM_O_RAMRETEN 0x00000224 +#define PRCM_O_RAMRETEN 0x00000224 //***************************************************************************** // @@ -235,13 +235,13 @@ // DIV8 Divide by 8 // DIV2 Divide by 2 // DIV1 Divide by 1 -#define PRCM_INFRCLKDIVR_RATIO_W 2 -#define PRCM_INFRCLKDIVR_RATIO_M 0x00000003 -#define PRCM_INFRCLKDIVR_RATIO_S 0 -#define PRCM_INFRCLKDIVR_RATIO_DIV32 0x00000003 -#define PRCM_INFRCLKDIVR_RATIO_DIV8 0x00000002 -#define PRCM_INFRCLKDIVR_RATIO_DIV2 0x00000001 -#define PRCM_INFRCLKDIVR_RATIO_DIV1 0x00000000 +#define PRCM_INFRCLKDIVR_RATIO_W 2 +#define PRCM_INFRCLKDIVR_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVR_RATIO_S 0 +#define PRCM_INFRCLKDIVR_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVR_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVR_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVR_RATIO_DIV1 0x00000000 //***************************************************************************** // @@ -258,13 +258,13 @@ // DIV8 Divide by 8 // DIV2 Divide by 2 // DIV1 Divide by 1 -#define PRCM_INFRCLKDIVS_RATIO_W 2 -#define PRCM_INFRCLKDIVS_RATIO_M 0x00000003 -#define PRCM_INFRCLKDIVS_RATIO_S 0 -#define PRCM_INFRCLKDIVS_RATIO_DIV32 0x00000003 -#define PRCM_INFRCLKDIVS_RATIO_DIV8 0x00000002 -#define PRCM_INFRCLKDIVS_RATIO_DIV2 0x00000001 -#define PRCM_INFRCLKDIVS_RATIO_DIV1 0x00000000 +#define PRCM_INFRCLKDIVS_RATIO_W 2 +#define PRCM_INFRCLKDIVS_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVS_RATIO_S 0 +#define PRCM_INFRCLKDIVS_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVS_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVS_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVS_RATIO_DIV1 0x00000000 //***************************************************************************** // @@ -281,13 +281,13 @@ // DIV8 Divide by 8 // DIV2 Divide by 2 // DIV1 Divide by 1 -#define PRCM_INFRCLKDIVDS_RATIO_W 2 -#define PRCM_INFRCLKDIVDS_RATIO_M 0x00000003 -#define PRCM_INFRCLKDIVDS_RATIO_S 0 -#define PRCM_INFRCLKDIVDS_RATIO_DIV32 0x00000003 -#define PRCM_INFRCLKDIVDS_RATIO_DIV8 0x00000002 -#define PRCM_INFRCLKDIVDS_RATIO_DIV2 0x00000001 -#define PRCM_INFRCLKDIVDS_RATIO_DIV1 0x00000000 +#define PRCM_INFRCLKDIVDS_RATIO_W 2 +#define PRCM_INFRCLKDIVDS_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVDS_RATIO_S 0 +#define PRCM_INFRCLKDIVDS_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVDS_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVDS_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVDS_RATIO_DIV1 0x00000000 //***************************************************************************** // @@ -311,10 +311,10 @@ // CLKLOADCTL.LOAD) // 5. RFC do no request access to BUS // 6. System CPU in deepsleep -#define PRCM_VDCTL_MCU_VD 0x00000004 -#define PRCM_VDCTL_MCU_VD_BITN 2 -#define PRCM_VDCTL_MCU_VD_M 0x00000004 -#define PRCM_VDCTL_MCU_VD_S 2 +#define PRCM_VDCTL_MCU_VD 0x00000004 +#define PRCM_VDCTL_MCU_VD_BITN 2 +#define PRCM_VDCTL_MCU_VD_M 0x00000004 +#define PRCM_VDCTL_MCU_VD_S 2 // Field: [0] ULDO // @@ -332,10 +332,10 @@ // CLKLOADCTL.LOAD) // 5. RFC do no request access to BUS // 6. System CPU in deepsleep -#define PRCM_VDCTL_ULDO 0x00000001 -#define PRCM_VDCTL_ULDO_BITN 0 -#define PRCM_VDCTL_ULDO_M 0x00000001 -#define PRCM_VDCTL_ULDO_S 0 +#define PRCM_VDCTL_ULDO 0x00000001 +#define PRCM_VDCTL_ULDO_BITN 0 +#define PRCM_VDCTL_ULDO_M 0x00000001 +#define PRCM_VDCTL_ULDO_S 0 //***************************************************************************** // @@ -352,10 +352,10 @@ // // 0 : One or more registers have been write accessed after last LOAD // 1 : No registers are write accessed after last LOAD -#define PRCM_CLKLOADCTL_LOAD_DONE 0x00000002 -#define PRCM_CLKLOADCTL_LOAD_DONE_BITN 1 -#define PRCM_CLKLOADCTL_LOAD_DONE_M 0x00000002 -#define PRCM_CLKLOADCTL_LOAD_DONE_S 1 +#define PRCM_CLKLOADCTL_LOAD_DONE 0x00000002 +#define PRCM_CLKLOADCTL_LOAD_DONE_BITN 1 +#define PRCM_CLKLOADCTL_LOAD_DONE_M 0x00000002 +#define PRCM_CLKLOADCTL_LOAD_DONE_S 1 // Field: [0] LOAD // @@ -397,10 +397,10 @@ // - I2SMCLKDIV // - I2SBCLKDIV // - I2SWCLKDIV -#define PRCM_CLKLOADCTL_LOAD 0x00000001 -#define PRCM_CLKLOADCTL_LOAD_BITN 0 -#define PRCM_CLKLOADCTL_LOAD_M 0x00000001 -#define PRCM_CLKLOADCTL_LOAD_S 0 +#define PRCM_CLKLOADCTL_LOAD 0x00000001 +#define PRCM_CLKLOADCTL_LOAD_BITN 0 +#define PRCM_CLKLOADCTL_LOAD_M 0x00000001 +#define PRCM_CLKLOADCTL_LOAD_S 0 //***************************************************************************** // @@ -414,10 +414,10 @@ // 1: Enable clock if RFC power domain is on // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_RFCCLKG_CLK_EN 0x00000001 -#define PRCM_RFCCLKG_CLK_EN_BITN 0 -#define PRCM_RFCCLKG_CLK_EN_M 0x00000001 -#define PRCM_RFCCLKG_CLK_EN_S 0 +#define PRCM_RFCCLKG_CLK_EN 0x00000001 +#define PRCM_RFCCLKG_CLK_EN_BITN 0 +#define PRCM_RFCCLKG_CLK_EN_M 0x00000001 +#define PRCM_RFCCLKG_CLK_EN_S 0 //***************************************************************************** // @@ -432,9 +432,9 @@ // 11: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_VIMSCLKG_CLK_EN_W 2 -#define PRCM_VIMSCLKG_CLK_EN_M 0x00000003 -#define PRCM_VIMSCLKG_CLK_EN_S 0 +#define PRCM_VIMSCLKG_CLK_EN_W 2 +#define PRCM_VIMSCLKG_CLK_EN_M 0x00000003 +#define PRCM_VIMSCLKG_CLK_EN_S 0 //***************************************************************************** // @@ -448,10 +448,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_DMA_CLK_EN 0x00000100 -#define PRCM_SECDMACLKGR_DMA_CLK_EN_BITN 8 -#define PRCM_SECDMACLKGR_DMA_CLK_EN_M 0x00000100 -#define PRCM_SECDMACLKGR_DMA_CLK_EN_S 8 +#define PRCM_SECDMACLKGR_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_S 8 // Field: [1] TRNG_CLK_EN // @@ -460,10 +460,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_TRNG_CLK_EN 0x00000002 -#define PRCM_SECDMACLKGR_TRNG_CLK_EN_BITN 1 -#define PRCM_SECDMACLKGR_TRNG_CLK_EN_M 0x00000002 -#define PRCM_SECDMACLKGR_TRNG_CLK_EN_S 1 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_S 1 // Field: [0] CRYPTO_CLK_EN // @@ -472,10 +472,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN 0x00000001 -#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_BITN 0 -#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_M 0x00000001 -#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S 0 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S 0 //***************************************************************************** // @@ -489,10 +489,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGS_DMA_CLK_EN 0x00000100 -#define PRCM_SECDMACLKGS_DMA_CLK_EN_BITN 8 -#define PRCM_SECDMACLKGS_DMA_CLK_EN_M 0x00000100 -#define PRCM_SECDMACLKGS_DMA_CLK_EN_S 8 +#define PRCM_SECDMACLKGS_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_S 8 // Field: [1] TRNG_CLK_EN // @@ -501,10 +501,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGS_TRNG_CLK_EN 0x00000002 -#define PRCM_SECDMACLKGS_TRNG_CLK_EN_BITN 1 -#define PRCM_SECDMACLKGS_TRNG_CLK_EN_M 0x00000002 -#define PRCM_SECDMACLKGS_TRNG_CLK_EN_S 1 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_S 1 // Field: [0] CRYPTO_CLK_EN // @@ -513,10 +513,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN 0x00000001 -#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_BITN 0 -#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_M 0x00000001 -#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_S 0 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_S 0 //***************************************************************************** // @@ -530,10 +530,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGDS_DMA_CLK_EN 0x00000100 -#define PRCM_SECDMACLKGDS_DMA_CLK_EN_BITN 8 -#define PRCM_SECDMACLKGDS_DMA_CLK_EN_M 0x00000100 -#define PRCM_SECDMACLKGDS_DMA_CLK_EN_S 8 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_S 8 // Field: [1] TRNG_CLK_EN // @@ -542,10 +542,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGDS_TRNG_CLK_EN 0x00000002 -#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_BITN 1 -#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_M 0x00000002 -#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_S 1 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_S 1 // Field: [0] CRYPTO_CLK_EN // @@ -554,10 +554,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN 0x00000001 -#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_BITN 0 -#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_M 0x00000001 -#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_S 0 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_S 0 //***************************************************************************** // @@ -571,10 +571,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_GPIOCLKGR_CLK_EN 0x00000001 -#define PRCM_GPIOCLKGR_CLK_EN_BITN 0 -#define PRCM_GPIOCLKGR_CLK_EN_M 0x00000001 -#define PRCM_GPIOCLKGR_CLK_EN_S 0 +#define PRCM_GPIOCLKGR_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGR_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGR_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGR_CLK_EN_S 0 //***************************************************************************** // @@ -588,10 +588,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_GPIOCLKGS_CLK_EN 0x00000001 -#define PRCM_GPIOCLKGS_CLK_EN_BITN 0 -#define PRCM_GPIOCLKGS_CLK_EN_M 0x00000001 -#define PRCM_GPIOCLKGS_CLK_EN_S 0 +#define PRCM_GPIOCLKGS_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGS_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGS_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGS_CLK_EN_S 0 //***************************************************************************** // @@ -605,10 +605,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_GPIOCLKGDS_CLK_EN 0x00000001 -#define PRCM_GPIOCLKGDS_CLK_EN_BITN 0 -#define PRCM_GPIOCLKGDS_CLK_EN_M 0x00000001 -#define PRCM_GPIOCLKGDS_CLK_EN_S 0 +#define PRCM_GPIOCLKGDS_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGDS_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGDS_CLK_EN_S 0 //***************************************************************************** // @@ -629,13 +629,13 @@ // GPT2 Enable clock for GPT2 // GPT1 Enable clock for GPT1 // GPT0 Enable clock for GPT0 -#define PRCM_GPTCLKGR_CLK_EN_W 4 -#define PRCM_GPTCLKGR_CLK_EN_M 0x0000000F -#define PRCM_GPTCLKGR_CLK_EN_S 0 -#define PRCM_GPTCLKGR_CLK_EN_GPT3 0x00000008 -#define PRCM_GPTCLKGR_CLK_EN_GPT2 0x00000004 -#define PRCM_GPTCLKGR_CLK_EN_GPT1 0x00000002 -#define PRCM_GPTCLKGR_CLK_EN_GPT0 0x00000001 +#define PRCM_GPTCLKGR_CLK_EN_W 4 +#define PRCM_GPTCLKGR_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGR_CLK_EN_S 0 +#define PRCM_GPTCLKGR_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGR_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGR_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGR_CLK_EN_GPT0 0x00000001 //***************************************************************************** // @@ -656,13 +656,13 @@ // GPT2 Enable clock for GPT2 // GPT1 Enable clock for GPT1 // GPT0 Enable clock for GPT0 -#define PRCM_GPTCLKGS_CLK_EN_W 4 -#define PRCM_GPTCLKGS_CLK_EN_M 0x0000000F -#define PRCM_GPTCLKGS_CLK_EN_S 0 -#define PRCM_GPTCLKGS_CLK_EN_GPT3 0x00000008 -#define PRCM_GPTCLKGS_CLK_EN_GPT2 0x00000004 -#define PRCM_GPTCLKGS_CLK_EN_GPT1 0x00000002 -#define PRCM_GPTCLKGS_CLK_EN_GPT0 0x00000001 +#define PRCM_GPTCLKGS_CLK_EN_W 4 +#define PRCM_GPTCLKGS_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGS_CLK_EN_S 0 +#define PRCM_GPTCLKGS_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGS_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGS_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGS_CLK_EN_GPT0 0x00000001 //***************************************************************************** // @@ -683,13 +683,13 @@ // GPT2 Enable clock for GPT2 // GPT1 Enable clock for GPT1 // GPT0 Enable clock for GPT0 -#define PRCM_GPTCLKGDS_CLK_EN_W 4 -#define PRCM_GPTCLKGDS_CLK_EN_M 0x0000000F -#define PRCM_GPTCLKGDS_CLK_EN_S 0 -#define PRCM_GPTCLKGDS_CLK_EN_GPT3 0x00000008 -#define PRCM_GPTCLKGDS_CLK_EN_GPT2 0x00000004 -#define PRCM_GPTCLKGDS_CLK_EN_GPT1 0x00000002 -#define PRCM_GPTCLKGDS_CLK_EN_GPT0 0x00000001 +#define PRCM_GPTCLKGDS_CLK_EN_W 4 +#define PRCM_GPTCLKGDS_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGDS_CLK_EN_S 0 +#define PRCM_GPTCLKGDS_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGDS_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGDS_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGDS_CLK_EN_GPT0 0x00000001 //***************************************************************************** // @@ -703,10 +703,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2CCLKGR_CLK_EN 0x00000001 -#define PRCM_I2CCLKGR_CLK_EN_BITN 0 -#define PRCM_I2CCLKGR_CLK_EN_M 0x00000001 -#define PRCM_I2CCLKGR_CLK_EN_S 0 +#define PRCM_I2CCLKGR_CLK_EN 0x00000001 +#define PRCM_I2CCLKGR_CLK_EN_BITN 0 +#define PRCM_I2CCLKGR_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGR_CLK_EN_S 0 //***************************************************************************** // @@ -720,10 +720,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2CCLKGS_CLK_EN 0x00000001 -#define PRCM_I2CCLKGS_CLK_EN_BITN 0 -#define PRCM_I2CCLKGS_CLK_EN_M 0x00000001 -#define PRCM_I2CCLKGS_CLK_EN_S 0 +#define PRCM_I2CCLKGS_CLK_EN 0x00000001 +#define PRCM_I2CCLKGS_CLK_EN_BITN 0 +#define PRCM_I2CCLKGS_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGS_CLK_EN_S 0 //***************************************************************************** // @@ -737,10 +737,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2CCLKGDS_CLK_EN 0x00000001 -#define PRCM_I2CCLKGDS_CLK_EN_BITN 0 -#define PRCM_I2CCLKGDS_CLK_EN_M 0x00000001 -#define PRCM_I2CCLKGDS_CLK_EN_S 0 +#define PRCM_I2CCLKGDS_CLK_EN 0x00000001 +#define PRCM_I2CCLKGDS_CLK_EN_BITN 0 +#define PRCM_I2CCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGDS_CLK_EN_S 0 //***************************************************************************** // @@ -754,10 +754,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_UARTCLKGR_CLK_EN 0x00000001 -#define PRCM_UARTCLKGR_CLK_EN_BITN 0 -#define PRCM_UARTCLKGR_CLK_EN_M 0x00000001 -#define PRCM_UARTCLKGR_CLK_EN_S 0 +#define PRCM_UARTCLKGR_CLK_EN 0x00000001 +#define PRCM_UARTCLKGR_CLK_EN_BITN 0 +#define PRCM_UARTCLKGR_CLK_EN_M 0x00000001 +#define PRCM_UARTCLKGR_CLK_EN_S 0 //***************************************************************************** // @@ -771,10 +771,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_UARTCLKGS_CLK_EN 0x00000001 -#define PRCM_UARTCLKGS_CLK_EN_BITN 0 -#define PRCM_UARTCLKGS_CLK_EN_M 0x00000001 -#define PRCM_UARTCLKGS_CLK_EN_S 0 +#define PRCM_UARTCLKGS_CLK_EN 0x00000001 +#define PRCM_UARTCLKGS_CLK_EN_BITN 0 +#define PRCM_UARTCLKGS_CLK_EN_M 0x00000001 +#define PRCM_UARTCLKGS_CLK_EN_S 0 //***************************************************************************** // @@ -788,10 +788,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_UARTCLKGDS_CLK_EN 0x00000001 -#define PRCM_UARTCLKGDS_CLK_EN_BITN 0 -#define PRCM_UARTCLKGDS_CLK_EN_M 0x00000001 -#define PRCM_UARTCLKGDS_CLK_EN_S 0 +#define PRCM_UARTCLKGDS_CLK_EN 0x00000001 +#define PRCM_UARTCLKGDS_CLK_EN_BITN 0 +#define PRCM_UARTCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_UARTCLKGDS_CLK_EN_S 0 //***************************************************************************** // @@ -808,11 +808,11 @@ // ENUMs: // SSI1 Enable clock for SSI1 // SSI0 Enable clock for SSI0 -#define PRCM_SSICLKGR_CLK_EN_W 2 -#define PRCM_SSICLKGR_CLK_EN_M 0x00000003 -#define PRCM_SSICLKGR_CLK_EN_S 0 -#define PRCM_SSICLKGR_CLK_EN_SSI1 0x00000002 -#define PRCM_SSICLKGR_CLK_EN_SSI0 0x00000001 +#define PRCM_SSICLKGR_CLK_EN_W 2 +#define PRCM_SSICLKGR_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGR_CLK_EN_S 0 +#define PRCM_SSICLKGR_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGR_CLK_EN_SSI0 0x00000001 //***************************************************************************** // @@ -829,11 +829,11 @@ // ENUMs: // SSI1 Enable clock for SSI1 // SSI0 Enable clock for SSI0 -#define PRCM_SSICLKGS_CLK_EN_W 2 -#define PRCM_SSICLKGS_CLK_EN_M 0x00000003 -#define PRCM_SSICLKGS_CLK_EN_S 0 -#define PRCM_SSICLKGS_CLK_EN_SSI1 0x00000002 -#define PRCM_SSICLKGS_CLK_EN_SSI0 0x00000001 +#define PRCM_SSICLKGS_CLK_EN_W 2 +#define PRCM_SSICLKGS_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGS_CLK_EN_S 0 +#define PRCM_SSICLKGS_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGS_CLK_EN_SSI0 0x00000001 //***************************************************************************** // @@ -850,11 +850,11 @@ // ENUMs: // SSI1 Enable clock for SSI1 // SSI0 Enable clock for SSI0 -#define PRCM_SSICLKGDS_CLK_EN_W 2 -#define PRCM_SSICLKGDS_CLK_EN_M 0x00000003 -#define PRCM_SSICLKGDS_CLK_EN_S 0 -#define PRCM_SSICLKGDS_CLK_EN_SSI1 0x00000002 -#define PRCM_SSICLKGDS_CLK_EN_SSI0 0x00000001 +#define PRCM_SSICLKGDS_CLK_EN_W 2 +#define PRCM_SSICLKGDS_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGDS_CLK_EN_S 0 +#define PRCM_SSICLKGDS_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGDS_CLK_EN_SSI0 0x00000001 //***************************************************************************** // @@ -868,10 +868,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKGR_CLK_EN 0x00000001 -#define PRCM_I2SCLKGR_CLK_EN_BITN 0 -#define PRCM_I2SCLKGR_CLK_EN_M 0x00000001 -#define PRCM_I2SCLKGR_CLK_EN_S 0 +#define PRCM_I2SCLKGR_CLK_EN 0x00000001 +#define PRCM_I2SCLKGR_CLK_EN_BITN 0 +#define PRCM_I2SCLKGR_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGR_CLK_EN_S 0 //***************************************************************************** // @@ -885,10 +885,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKGS_CLK_EN 0x00000001 -#define PRCM_I2SCLKGS_CLK_EN_BITN 0 -#define PRCM_I2SCLKGS_CLK_EN_M 0x00000001 -#define PRCM_I2SCLKGS_CLK_EN_S 0 +#define PRCM_I2SCLKGS_CLK_EN 0x00000001 +#define PRCM_I2SCLKGS_CLK_EN_BITN 0 +#define PRCM_I2SCLKGS_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGS_CLK_EN_S 0 //***************************************************************************** // @@ -902,10 +902,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKGDS_CLK_EN 0x00000001 -#define PRCM_I2SCLKGDS_CLK_EN_BITN 0 -#define PRCM_I2SCLKGDS_CLK_EN_M 0x00000001 -#define PRCM_I2SCLKGDS_CLK_EN_S 0 +#define PRCM_I2SCLKGDS_CLK_EN 0x00000001 +#define PRCM_I2SCLKGDS_CLK_EN_BITN 0 +#define PRCM_I2SCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGDS_CLK_EN_S 0 //***************************************************************************** // @@ -918,12 +918,12 @@ // ENUMs: // DIV2 Internal. Only to be used through TI provided API. // DIV1 Internal. Only to be used through TI provided API. -#define PRCM_CPUCLKDIV_RATIO 0x00000001 -#define PRCM_CPUCLKDIV_RATIO_BITN 0 -#define PRCM_CPUCLKDIV_RATIO_M 0x00000001 -#define PRCM_CPUCLKDIV_RATIO_S 0 -#define PRCM_CPUCLKDIV_RATIO_DIV2 0x00000001 -#define PRCM_CPUCLKDIV_RATIO_DIV1 0x00000000 +#define PRCM_CPUCLKDIV_RATIO 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_BITN 0 +#define PRCM_CPUCLKDIV_RATIO_M 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_S 0 +#define PRCM_CPUCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_DIV1 0x00000000 //***************************************************************************** // @@ -938,10 +938,10 @@ // 1: Use internally generated clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SBCLKSEL_SRC 0x00000001 -#define PRCM_I2SBCLKSEL_SRC_BITN 0 -#define PRCM_I2SBCLKSEL_SRC_M 0x00000001 -#define PRCM_I2SBCLKSEL_SRC_S 0 +#define PRCM_I2SBCLKSEL_SRC 0x00000001 +#define PRCM_I2SBCLKSEL_SRC_BITN 0 +#define PRCM_I2SBCLKSEL_SRC_M 0x00000001 +#define PRCM_I2SBCLKSEL_SRC_S 0 //***************************************************************************** // @@ -965,18 +965,18 @@ // DIV4 Divide by 4 // DIV2 Divide by 2 // DIV1 Divide by 1 -#define PRCM_GPTCLKDIV_RATIO_W 4 -#define PRCM_GPTCLKDIV_RATIO_M 0x0000000F -#define PRCM_GPTCLKDIV_RATIO_S 0 -#define PRCM_GPTCLKDIV_RATIO_DIV256 0x00000008 -#define PRCM_GPTCLKDIV_RATIO_DIV128 0x00000007 -#define PRCM_GPTCLKDIV_RATIO_DIV64 0x00000006 -#define PRCM_GPTCLKDIV_RATIO_DIV32 0x00000005 -#define PRCM_GPTCLKDIV_RATIO_DIV16 0x00000004 -#define PRCM_GPTCLKDIV_RATIO_DIV8 0x00000003 -#define PRCM_GPTCLKDIV_RATIO_DIV4 0x00000002 -#define PRCM_GPTCLKDIV_RATIO_DIV2 0x00000001 -#define PRCM_GPTCLKDIV_RATIO_DIV1 0x00000000 +#define PRCM_GPTCLKDIV_RATIO_W 4 +#define PRCM_GPTCLKDIV_RATIO_M 0x0000000F +#define PRCM_GPTCLKDIV_RATIO_S 0 +#define PRCM_GPTCLKDIV_RATIO_DIV256 0x00000008 +#define PRCM_GPTCLKDIV_RATIO_DIV128 0x00000007 +#define PRCM_GPTCLKDIV_RATIO_DIV64 0x00000006 +#define PRCM_GPTCLKDIV_RATIO_DIV32 0x00000005 +#define PRCM_GPTCLKDIV_RATIO_DIV16 0x00000004 +#define PRCM_GPTCLKDIV_RATIO_DIV8 0x00000003 +#define PRCM_GPTCLKDIV_RATIO_DIV4 0x00000002 +#define PRCM_GPTCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_GPTCLKDIV_RATIO_DIV1 0x00000000 //***************************************************************************** // @@ -994,10 +994,10 @@ // negative edge. // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE 0x00000008 -#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_BITN 3 -#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M 0x00000008 -#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S 3 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE 0x00000008 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_BITN 3 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M 0x00000008 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S 3 // Field: [2:1] WCLK_PHASE // @@ -1010,9 +1010,9 @@ // 3: Reserved/Undefined // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKCTL_WCLK_PHASE_W 2 -#define PRCM_I2SCLKCTL_WCLK_PHASE_M 0x00000006 -#define PRCM_I2SCLKCTL_WCLK_PHASE_S 1 +#define PRCM_I2SCLKCTL_WCLK_PHASE_W 2 +#define PRCM_I2SCLKCTL_WCLK_PHASE_M 0x00000006 +#define PRCM_I2SCLKCTL_WCLK_PHASE_S 1 // Field: [0] EN // @@ -1021,10 +1021,10 @@ // 1: Enables the generation of MCLK, BCLK and WCLK // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKCTL_EN 0x00000001 -#define PRCM_I2SCLKCTL_EN_BITN 0 -#define PRCM_I2SCLKCTL_EN_M 0x00000001 -#define PRCM_I2SCLKCTL_EN_S 0 +#define PRCM_I2SCLKCTL_EN 0x00000001 +#define PRCM_I2SCLKCTL_EN_BITN 0 +#define PRCM_I2SCLKCTL_EN_M 0x00000001 +#define PRCM_I2SCLKCTL_EN_S 0 //***************************************************************************** // @@ -1045,9 +1045,9 @@ // the high phase. // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SMCLKDIV_MDIV_W 10 -#define PRCM_I2SMCLKDIV_MDIV_M 0x000003FF -#define PRCM_I2SMCLKDIV_MDIV_S 0 +#define PRCM_I2SMCLKDIV_MDIV_W 10 +#define PRCM_I2SMCLKDIV_MDIV_M 0x000003FF +#define PRCM_I2SMCLKDIV_MDIV_S 0 //***************************************************************************** // @@ -1070,9 +1070,9 @@ // clock is one MCUCLK period longer than the low phase. // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SBCLKDIV_BDIV_W 10 -#define PRCM_I2SBCLKDIV_BDIV_M 0x000003FF -#define PRCM_I2SBCLKDIV_BDIV_S 0 +#define PRCM_I2SBCLKDIV_BDIV_W 10 +#define PRCM_I2SBCLKDIV_BDIV_M 0x000003FF +#define PRCM_I2SBCLKDIV_BDIV_S 0 //***************************************************************************** // @@ -1102,9 +1102,9 @@ // WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz] // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SWCLKDIV_WDIV_W 16 -#define PRCM_I2SWCLKDIV_WDIV_M 0x0000FFFF -#define PRCM_I2SWCLKDIV_WDIV_S 0 +#define PRCM_I2SWCLKDIV_WDIV_W 16 +#define PRCM_I2SWCLKDIV_WDIV_M 0x0000FFFF +#define PRCM_I2SWCLKDIV_WDIV_S 0 //***************************************************************************** // @@ -1114,10 +1114,10 @@ // Field: [2] MCU // // Internal. Only to be used through TI provided API. -#define PRCM_SWRESET_MCU 0x00000004 -#define PRCM_SWRESET_MCU_BITN 2 -#define PRCM_SWRESET_MCU_M 0x00000004 -#define PRCM_SWRESET_MCU_S 2 +#define PRCM_SWRESET_MCU 0x00000004 +#define PRCM_SWRESET_MCU_BITN 2 +#define PRCM_SWRESET_MCU_M 0x00000004 +#define PRCM_SWRESET_MCU_S 2 //***************************************************************************** // @@ -1143,10 +1143,10 @@ // reset resulting in a full power up sequence. WARMRESET in this register is // set in the scenario that WR_TO_PINRESET=1 and one of the above listed // sources is triggered. -#define PRCM_WARMRESET_WR_TO_PINRESET 0x00000004 -#define PRCM_WARMRESET_WR_TO_PINRESET_BITN 2 -#define PRCM_WARMRESET_WR_TO_PINRESET_M 0x00000004 -#define PRCM_WARMRESET_WR_TO_PINRESET_S 2 +#define PRCM_WARMRESET_WR_TO_PINRESET 0x00000004 +#define PRCM_WARMRESET_WR_TO_PINRESET_BITN 2 +#define PRCM_WARMRESET_WR_TO_PINRESET_M 0x00000004 +#define PRCM_WARMRESET_WR_TO_PINRESET_S 2 // Field: [1] LOCKUP_STAT // @@ -1156,10 +1156,10 @@ // register. // // A read of this register clears both WDT_STAT and LOCKUP_STAT. -#define PRCM_WARMRESET_LOCKUP_STAT 0x00000002 -#define PRCM_WARMRESET_LOCKUP_STAT_BITN 1 -#define PRCM_WARMRESET_LOCKUP_STAT_M 0x00000002 -#define PRCM_WARMRESET_LOCKUP_STAT_S 1 +#define PRCM_WARMRESET_LOCKUP_STAT 0x00000002 +#define PRCM_WARMRESET_LOCKUP_STAT_BITN 1 +#define PRCM_WARMRESET_LOCKUP_STAT_M 0x00000002 +#define PRCM_WARMRESET_LOCKUP_STAT_S 1 // Field: [0] WDT_STAT // @@ -1168,10 +1168,10 @@ // 1: A WDT event has occured since last SW clear of the register. // // A read of this register clears both WDT_STAT and LOCKUP_STAT. -#define PRCM_WARMRESET_WDT_STAT 0x00000001 -#define PRCM_WARMRESET_WDT_STAT_BITN 0 -#define PRCM_WARMRESET_WDT_STAT_M 0x00000001 -#define PRCM_WARMRESET_WDT_STAT_S 0 +#define PRCM_WARMRESET_WDT_STAT 0x00000001 +#define PRCM_WARMRESET_WDT_STAT_BITN 0 +#define PRCM_WARMRESET_WDT_STAT_M 0x00000001 +#define PRCM_WARMRESET_WDT_STAT_S 0 //***************************************************************************** // @@ -1184,10 +1184,10 @@ // // 0: PERIPH power domain is powered down // 1: PERIPH power domain is powered up -#define PRCM_PDCTL0_PERIPH_ON 0x00000004 -#define PRCM_PDCTL0_PERIPH_ON_BITN 2 -#define PRCM_PDCTL0_PERIPH_ON_M 0x00000004 -#define PRCM_PDCTL0_PERIPH_ON_S 2 +#define PRCM_PDCTL0_PERIPH_ON 0x00000004 +#define PRCM_PDCTL0_PERIPH_ON_BITN 2 +#define PRCM_PDCTL0_PERIPH_ON_M 0x00000004 +#define PRCM_PDCTL0_PERIPH_ON_S 2 // Field: [1] SERIAL_ON // @@ -1195,20 +1195,20 @@ // // 0: SERIAL power domain is powered down // 1: SERIAL power domain is powered up -#define PRCM_PDCTL0_SERIAL_ON 0x00000002 -#define PRCM_PDCTL0_SERIAL_ON_BITN 1 -#define PRCM_PDCTL0_SERIAL_ON_M 0x00000002 -#define PRCM_PDCTL0_SERIAL_ON_S 1 +#define PRCM_PDCTL0_SERIAL_ON 0x00000002 +#define PRCM_PDCTL0_SERIAL_ON_BITN 1 +#define PRCM_PDCTL0_SERIAL_ON_M 0x00000002 +#define PRCM_PDCTL0_SERIAL_ON_S 1 // Field: [0] RFC_ON // // // 0: RFC power domain powered off if also PDCTL1.RFC_ON = 0 // 1: RFC power domain powered on -#define PRCM_PDCTL0_RFC_ON 0x00000001 -#define PRCM_PDCTL0_RFC_ON_BITN 0 -#define PRCM_PDCTL0_RFC_ON_M 0x00000001 -#define PRCM_PDCTL0_RFC_ON_S 0 +#define PRCM_PDCTL0_RFC_ON 0x00000001 +#define PRCM_PDCTL0_RFC_ON_BITN 0 +#define PRCM_PDCTL0_RFC_ON_M 0x00000001 +#define PRCM_PDCTL0_RFC_ON_S 0 //***************************************************************************** // @@ -1218,10 +1218,10 @@ // Field: [0] ON // // Alias for PDCTL0.RFC_ON -#define PRCM_PDCTL0RFC_ON 0x00000001 -#define PRCM_PDCTL0RFC_ON_BITN 0 -#define PRCM_PDCTL0RFC_ON_M 0x00000001 -#define PRCM_PDCTL0RFC_ON_S 0 +#define PRCM_PDCTL0RFC_ON 0x00000001 +#define PRCM_PDCTL0RFC_ON_BITN 0 +#define PRCM_PDCTL0RFC_ON_M 0x00000001 +#define PRCM_PDCTL0RFC_ON_S 0 //***************************************************************************** // @@ -1231,10 +1231,10 @@ // Field: [0] ON // // Alias for PDCTL0.SERIAL_ON -#define PRCM_PDCTL0SERIAL_ON 0x00000001 -#define PRCM_PDCTL0SERIAL_ON_BITN 0 -#define PRCM_PDCTL0SERIAL_ON_M 0x00000001 -#define PRCM_PDCTL0SERIAL_ON_S 0 +#define PRCM_PDCTL0SERIAL_ON 0x00000001 +#define PRCM_PDCTL0SERIAL_ON_BITN 0 +#define PRCM_PDCTL0SERIAL_ON_M 0x00000001 +#define PRCM_PDCTL0SERIAL_ON_S 0 //***************************************************************************** // @@ -1244,10 +1244,10 @@ // Field: [0] ON // // Alias for PDCTL0.PERIPH_ON -#define PRCM_PDCTL0PERIPH_ON 0x00000001 -#define PRCM_PDCTL0PERIPH_ON_BITN 0 -#define PRCM_PDCTL0PERIPH_ON_M 0x00000001 -#define PRCM_PDCTL0PERIPH_ON_S 0 +#define PRCM_PDCTL0PERIPH_ON 0x00000001 +#define PRCM_PDCTL0PERIPH_ON_BITN 0 +#define PRCM_PDCTL0PERIPH_ON_M 0x00000001 +#define PRCM_PDCTL0PERIPH_ON_S 0 //***************************************************************************** // @@ -1260,10 +1260,10 @@ // // 0: Domain may be powered down // 1: Domain powered up (guaranteed) -#define PRCM_PDSTAT0_PERIPH_ON 0x00000004 -#define PRCM_PDSTAT0_PERIPH_ON_BITN 2 -#define PRCM_PDSTAT0_PERIPH_ON_M 0x00000004 -#define PRCM_PDSTAT0_PERIPH_ON_S 2 +#define PRCM_PDSTAT0_PERIPH_ON 0x00000004 +#define PRCM_PDSTAT0_PERIPH_ON_BITN 2 +#define PRCM_PDSTAT0_PERIPH_ON_M 0x00000004 +#define PRCM_PDSTAT0_PERIPH_ON_S 2 // Field: [1] SERIAL_ON // @@ -1271,10 +1271,10 @@ // // 0: Domain may be powered down // 1: Domain powered up (guaranteed) -#define PRCM_PDSTAT0_SERIAL_ON 0x00000002 -#define PRCM_PDSTAT0_SERIAL_ON_BITN 1 -#define PRCM_PDSTAT0_SERIAL_ON_M 0x00000002 -#define PRCM_PDSTAT0_SERIAL_ON_S 1 +#define PRCM_PDSTAT0_SERIAL_ON 0x00000002 +#define PRCM_PDSTAT0_SERIAL_ON_BITN 1 +#define PRCM_PDSTAT0_SERIAL_ON_M 0x00000002 +#define PRCM_PDSTAT0_SERIAL_ON_S 1 // Field: [0] RFC_ON // @@ -1282,10 +1282,10 @@ // // 0: Domain may be powered down // 1: Domain powered up (guaranteed) -#define PRCM_PDSTAT0_RFC_ON 0x00000001 -#define PRCM_PDSTAT0_RFC_ON_BITN 0 -#define PRCM_PDSTAT0_RFC_ON_M 0x00000001 -#define PRCM_PDSTAT0_RFC_ON_S 0 +#define PRCM_PDSTAT0_RFC_ON 0x00000001 +#define PRCM_PDSTAT0_RFC_ON_BITN 0 +#define PRCM_PDSTAT0_RFC_ON_M 0x00000001 +#define PRCM_PDSTAT0_RFC_ON_S 0 //***************************************************************************** // @@ -1295,10 +1295,10 @@ // Field: [0] ON // // Alias for PDSTAT0.RFC_ON -#define PRCM_PDSTAT0RFC_ON 0x00000001 -#define PRCM_PDSTAT0RFC_ON_BITN 0 -#define PRCM_PDSTAT0RFC_ON_M 0x00000001 -#define PRCM_PDSTAT0RFC_ON_S 0 +#define PRCM_PDSTAT0RFC_ON 0x00000001 +#define PRCM_PDSTAT0RFC_ON_BITN 0 +#define PRCM_PDSTAT0RFC_ON_M 0x00000001 +#define PRCM_PDSTAT0RFC_ON_S 0 //***************************************************************************** // @@ -1308,10 +1308,10 @@ // Field: [0] ON // // Alias for PDSTAT0.SERIAL_ON -#define PRCM_PDSTAT0SERIAL_ON 0x00000001 -#define PRCM_PDSTAT0SERIAL_ON_BITN 0 -#define PRCM_PDSTAT0SERIAL_ON_M 0x00000001 -#define PRCM_PDSTAT0SERIAL_ON_S 0 +#define PRCM_PDSTAT0SERIAL_ON 0x00000001 +#define PRCM_PDSTAT0SERIAL_ON_BITN 0 +#define PRCM_PDSTAT0SERIAL_ON_M 0x00000001 +#define PRCM_PDSTAT0SERIAL_ON_S 0 //***************************************************************************** // @@ -1321,10 +1321,10 @@ // Field: [0] ON // // Alias for PDSTAT0.PERIPH_ON -#define PRCM_PDSTAT0PERIPH_ON 0x00000001 -#define PRCM_PDSTAT0PERIPH_ON_BITN 0 -#define PRCM_PDSTAT0PERIPH_ON_M 0x00000001 -#define PRCM_PDSTAT0PERIPH_ON_S 0 +#define PRCM_PDSTAT0PERIPH_ON 0x00000001 +#define PRCM_PDSTAT0PERIPH_ON_BITN 0 +#define PRCM_PDSTAT0PERIPH_ON_M 0x00000001 +#define PRCM_PDSTAT0PERIPH_ON_S 0 //***************************************************************************** // @@ -1336,10 +1336,10 @@ // // 0: VIMS power domain is only powered when CPU power domain is powered. // 1: VIMS power domain is powered whenever the BUS power domain is powered. -#define PRCM_PDCTL1_VIMS_MODE 0x00000008 -#define PRCM_PDCTL1_VIMS_MODE_BITN 3 -#define PRCM_PDCTL1_VIMS_MODE_M 0x00000008 -#define PRCM_PDCTL1_VIMS_MODE_S 3 +#define PRCM_PDCTL1_VIMS_MODE 0x00000008 +#define PRCM_PDCTL1_VIMS_MODE_BITN 3 +#define PRCM_PDCTL1_VIMS_MODE_M 0x00000008 +#define PRCM_PDCTL1_VIMS_MODE_S 3 // Field: [2] RFC_ON // @@ -1349,10 +1349,10 @@ // // Bit shall be used by RFC in autonomus mode but there is no HW restrictions // fom system CPU to access the bit. -#define PRCM_PDCTL1_RFC_ON 0x00000004 -#define PRCM_PDCTL1_RFC_ON_BITN 2 -#define PRCM_PDCTL1_RFC_ON_M 0x00000004 -#define PRCM_PDCTL1_RFC_ON_S 2 +#define PRCM_PDCTL1_RFC_ON 0x00000004 +#define PRCM_PDCTL1_RFC_ON_BITN 2 +#define PRCM_PDCTL1_RFC_ON_M 0x00000004 +#define PRCM_PDCTL1_RFC_ON_S 2 // Field: [1] CPU_ON // @@ -1362,10 +1362,10 @@ // 1: Initiates power-on of the CPU power domain. // // This bit is automatically set by a WIC power-on event. -#define PRCM_PDCTL1_CPU_ON 0x00000002 -#define PRCM_PDCTL1_CPU_ON_BITN 1 -#define PRCM_PDCTL1_CPU_ON_M 0x00000002 -#define PRCM_PDCTL1_CPU_ON_S 1 +#define PRCM_PDCTL1_CPU_ON 0x00000002 +#define PRCM_PDCTL1_CPU_ON_BITN 1 +#define PRCM_PDCTL1_CPU_ON_M 0x00000002 +#define PRCM_PDCTL1_CPU_ON_S 1 //***************************************************************************** // @@ -1375,10 +1375,10 @@ // Field: [0] ON // // This is an alias for PDCTL1.CPU_ON -#define PRCM_PDCTL1CPU_ON 0x00000001 -#define PRCM_PDCTL1CPU_ON_BITN 0 -#define PRCM_PDCTL1CPU_ON_M 0x00000001 -#define PRCM_PDCTL1CPU_ON_S 0 +#define PRCM_PDCTL1CPU_ON 0x00000001 +#define PRCM_PDCTL1CPU_ON_BITN 0 +#define PRCM_PDCTL1CPU_ON_M 0x00000001 +#define PRCM_PDCTL1CPU_ON_S 0 //***************************************************************************** // @@ -1388,10 +1388,10 @@ // Field: [0] ON // // This is an alias for PDCTL1.RFC_ON -#define PRCM_PDCTL1RFC_ON 0x00000001 -#define PRCM_PDCTL1RFC_ON_BITN 0 -#define PRCM_PDCTL1RFC_ON_M 0x00000001 -#define PRCM_PDCTL1RFC_ON_S 0 +#define PRCM_PDCTL1RFC_ON 0x00000001 +#define PRCM_PDCTL1RFC_ON_BITN 0 +#define PRCM_PDCTL1RFC_ON_M 0x00000001 +#define PRCM_PDCTL1RFC_ON_S 0 //***************************************************************************** // @@ -1401,10 +1401,10 @@ // Field: [0] ON // // This is an alias for PDCTL1.VIMS_MODE -#define PRCM_PDCTL1VIMS_ON 0x00000001 -#define PRCM_PDCTL1VIMS_ON_BITN 0 -#define PRCM_PDCTL1VIMS_ON_M 0x00000001 -#define PRCM_PDCTL1VIMS_ON_S 0 +#define PRCM_PDCTL1VIMS_ON 0x00000001 +#define PRCM_PDCTL1VIMS_ON_BITN 0 +#define PRCM_PDCTL1VIMS_ON_M 0x00000001 +#define PRCM_PDCTL1VIMS_ON_S 0 //***************************************************************************** // @@ -1416,40 +1416,40 @@ // // 0: BUS domain not accessible // 1: BUS domain is currently accessible -#define PRCM_PDSTAT1_BUS_ON 0x00000010 -#define PRCM_PDSTAT1_BUS_ON_BITN 4 -#define PRCM_PDSTAT1_BUS_ON_M 0x00000010 -#define PRCM_PDSTAT1_BUS_ON_S 4 +#define PRCM_PDSTAT1_BUS_ON 0x00000010 +#define PRCM_PDSTAT1_BUS_ON_BITN 4 +#define PRCM_PDSTAT1_BUS_ON_M 0x00000010 +#define PRCM_PDSTAT1_BUS_ON_S 4 // Field: [3] VIMS_MODE // // // 0: VIMS domain not accessible // 1: VIMS domain is currently accessible -#define PRCM_PDSTAT1_VIMS_MODE 0x00000008 -#define PRCM_PDSTAT1_VIMS_MODE_BITN 3 -#define PRCM_PDSTAT1_VIMS_MODE_M 0x00000008 -#define PRCM_PDSTAT1_VIMS_MODE_S 3 +#define PRCM_PDSTAT1_VIMS_MODE 0x00000008 +#define PRCM_PDSTAT1_VIMS_MODE_BITN 3 +#define PRCM_PDSTAT1_VIMS_MODE_M 0x00000008 +#define PRCM_PDSTAT1_VIMS_MODE_S 3 // Field: [2] RFC_ON // // // 0: RFC domain not accessible // 1: RFC domain is currently accessible -#define PRCM_PDSTAT1_RFC_ON 0x00000004 -#define PRCM_PDSTAT1_RFC_ON_BITN 2 -#define PRCM_PDSTAT1_RFC_ON_M 0x00000004 -#define PRCM_PDSTAT1_RFC_ON_S 2 +#define PRCM_PDSTAT1_RFC_ON 0x00000004 +#define PRCM_PDSTAT1_RFC_ON_BITN 2 +#define PRCM_PDSTAT1_RFC_ON_M 0x00000004 +#define PRCM_PDSTAT1_RFC_ON_S 2 // Field: [1] CPU_ON // // // 0: CPU and BUS domain not accessible // 1: CPU and BUS domains are both currently accessible -#define PRCM_PDSTAT1_CPU_ON 0x00000002 -#define PRCM_PDSTAT1_CPU_ON_BITN 1 -#define PRCM_PDSTAT1_CPU_ON_M 0x00000002 -#define PRCM_PDSTAT1_CPU_ON_S 1 +#define PRCM_PDSTAT1_CPU_ON 0x00000002 +#define PRCM_PDSTAT1_CPU_ON_BITN 1 +#define PRCM_PDSTAT1_CPU_ON_M 0x00000002 +#define PRCM_PDSTAT1_CPU_ON_S 1 //***************************************************************************** // @@ -1459,10 +1459,10 @@ // Field: [0] ON // // This is an alias for PDSTAT1.BUS_ON -#define PRCM_PDSTAT1BUS_ON 0x00000001 -#define PRCM_PDSTAT1BUS_ON_BITN 0 -#define PRCM_PDSTAT1BUS_ON_M 0x00000001 -#define PRCM_PDSTAT1BUS_ON_S 0 +#define PRCM_PDSTAT1BUS_ON 0x00000001 +#define PRCM_PDSTAT1BUS_ON_BITN 0 +#define PRCM_PDSTAT1BUS_ON_M 0x00000001 +#define PRCM_PDSTAT1BUS_ON_S 0 //***************************************************************************** // @@ -1472,10 +1472,10 @@ // Field: [0] ON // // This is an alias for PDSTAT1.RFC_ON -#define PRCM_PDSTAT1RFC_ON 0x00000001 -#define PRCM_PDSTAT1RFC_ON_BITN 0 -#define PRCM_PDSTAT1RFC_ON_M 0x00000001 -#define PRCM_PDSTAT1RFC_ON_S 0 +#define PRCM_PDSTAT1RFC_ON 0x00000001 +#define PRCM_PDSTAT1RFC_ON_BITN 0 +#define PRCM_PDSTAT1RFC_ON_M 0x00000001 +#define PRCM_PDSTAT1RFC_ON_S 0 //***************************************************************************** // @@ -1485,10 +1485,10 @@ // Field: [0] ON // // This is an alias for PDSTAT1.CPU_ON -#define PRCM_PDSTAT1CPU_ON 0x00000001 -#define PRCM_PDSTAT1CPU_ON_BITN 0 -#define PRCM_PDSTAT1CPU_ON_M 0x00000001 -#define PRCM_PDSTAT1CPU_ON_S 0 +#define PRCM_PDSTAT1CPU_ON 0x00000001 +#define PRCM_PDSTAT1CPU_ON_BITN 0 +#define PRCM_PDSTAT1CPU_ON_M 0x00000001 +#define PRCM_PDSTAT1CPU_ON_S 0 //***************************************************************************** // @@ -1498,10 +1498,10 @@ // Field: [0] ON // // This is an alias for PDSTAT1.VIMS_MODE -#define PRCM_PDSTAT1VIMS_ON 0x00000001 -#define PRCM_PDSTAT1VIMS_ON_BITN 0 -#define PRCM_PDSTAT1VIMS_ON_M 0x00000001 -#define PRCM_PDSTAT1VIMS_ON_S 0 +#define PRCM_PDSTAT1VIMS_ON 0x00000001 +#define PRCM_PDSTAT1VIMS_ON_BITN 0 +#define PRCM_PDSTAT1VIMS_ON_M 0x00000001 +#define PRCM_PDSTAT1VIMS_ON_S 0 //***************************************************************************** // @@ -1515,9 +1515,9 @@ // to perform some tasks at its start-up. The supported functionality is // ROM-defined and may vary. See the technical reference manual for more // details. -#define PRCM_RFCBITS_READ_W 32 -#define PRCM_RFCBITS_READ_M 0xFFFFFFFF -#define PRCM_RFCBITS_READ_S 0 +#define PRCM_RFCBITS_READ_W 32 +#define PRCM_RFCBITS_READ_M 0xFFFFFFFF +#define PRCM_RFCBITS_READ_S 0 //***************************************************************************** // @@ -1538,17 +1538,17 @@ // MODE2 Select Mode 2 // MODE1 Select Mode 1 // MODE0 Select Mode 0 -#define PRCM_RFCMODESEL_CURR_W 3 -#define PRCM_RFCMODESEL_CURR_M 0x00000007 -#define PRCM_RFCMODESEL_CURR_S 0 -#define PRCM_RFCMODESEL_CURR_MODE7 0x00000007 -#define PRCM_RFCMODESEL_CURR_MODE6 0x00000006 -#define PRCM_RFCMODESEL_CURR_MODE5 0x00000005 -#define PRCM_RFCMODESEL_CURR_MODE4 0x00000004 -#define PRCM_RFCMODESEL_CURR_MODE3 0x00000003 -#define PRCM_RFCMODESEL_CURR_MODE2 0x00000002 -#define PRCM_RFCMODESEL_CURR_MODE1 0x00000001 -#define PRCM_RFCMODESEL_CURR_MODE0 0x00000000 +#define PRCM_RFCMODESEL_CURR_W 3 +#define PRCM_RFCMODESEL_CURR_M 0x00000007 +#define PRCM_RFCMODESEL_CURR_S 0 +#define PRCM_RFCMODESEL_CURR_MODE7 0x00000007 +#define PRCM_RFCMODESEL_CURR_MODE6 0x00000006 +#define PRCM_RFCMODESEL_CURR_MODE5 0x00000005 +#define PRCM_RFCMODESEL_CURR_MODE4 0x00000004 +#define PRCM_RFCMODESEL_CURR_MODE3 0x00000003 +#define PRCM_RFCMODESEL_CURR_MODE2 0x00000002 +#define PRCM_RFCMODESEL_CURR_MODE1 0x00000001 +#define PRCM_RFCMODESEL_CURR_MODE0 0x00000000 //***************************************************************************** // @@ -1567,17 +1567,17 @@ // MODE2 Mode 2 permitted // MODE1 Mode 1 permitted // MODE0 Mode 0 permitted -#define PRCM_RFCMODEHWOPT_AVAIL_W 8 -#define PRCM_RFCMODEHWOPT_AVAIL_M 0x000000FF -#define PRCM_RFCMODEHWOPT_AVAIL_S 0 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE7 0x00000080 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE6 0x00000040 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE5 0x00000020 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE4 0x00000010 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE3 0x00000008 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE2 0x00000004 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE1 0x00000002 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE0 0x00000001 +#define PRCM_RFCMODEHWOPT_AVAIL_W 8 +#define PRCM_RFCMODEHWOPT_AVAIL_M 0x000000FF +#define PRCM_RFCMODEHWOPT_AVAIL_S 0 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE7 0x00000080 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE6 0x00000040 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE5 0x00000020 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE4 0x00000010 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE3 0x00000008 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE2 0x00000004 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE1 0x00000002 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE0 0x00000001 //***************************************************************************** // @@ -1589,9 +1589,9 @@ // SW can use these bits to timestamp the application. These bits are also // available through the testtap and can thus be used by the emulator to // profile in real time. -#define PRCM_PWRPROFSTAT_VALUE_W 8 -#define PRCM_PWRPROFSTAT_VALUE_M 0x000000FF -#define PRCM_PWRPROFSTAT_VALUE_S 0 +#define PRCM_PWRPROFSTAT_VALUE_W 8 +#define PRCM_PWRPROFSTAT_VALUE_M 0x000000FF +#define PRCM_PWRPROFSTAT_VALUE_S 0 //***************************************************************************** // @@ -1605,10 +1605,10 @@ // 1: Retention for RFC SRAM enabled // // Memories controlled: CPERAM MCERAM RFERAM -#define PRCM_RAMRETEN_RFC 0x00000004 -#define PRCM_RAMRETEN_RFC_BITN 2 -#define PRCM_RAMRETEN_RFC_M 0x00000004 -#define PRCM_RAMRETEN_RFC_S 2 +#define PRCM_RAMRETEN_RFC 0x00000004 +#define PRCM_RAMRETEN_RFC_BITN 2 +#define PRCM_RAMRETEN_RFC_M 0x00000004 +#define PRCM_RAMRETEN_RFC_S 2 // Field: [1:0] VIMS // @@ -1628,9 +1628,8 @@ // or SPILT mode. // 10: Illegal mode // 11: No restrictions -#define PRCM_RAMRETEN_VIMS_W 2 -#define PRCM_RAMRETEN_VIMS_M 0x00000003 -#define PRCM_RAMRETEN_VIMS_S 0 - +#define PRCM_RAMRETEN_VIMS_W 2 +#define PRCM_RAMRETEN_VIMS_M 0x00000003 +#define PRCM_RAMRETEN_VIMS_S 0 #endif // __PRCM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_rfc_dbell.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_rfc_dbell.h index 9ac876c..52a2cf0 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_rfc_dbell.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_rfc_dbell.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_rfc_dbell_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_rfc_dbell_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_RFC_DBELL_H__ #define __HW_RFC_DBELL_H__ @@ -44,32 +44,32 @@ // //***************************************************************************** // Doorbell Command Register -#define RFC_DBELL_O_CMDR 0x00000000 +#define RFC_DBELL_O_CMDR 0x00000000 // Doorbell Command Status Register -#define RFC_DBELL_O_CMDSTA 0x00000004 +#define RFC_DBELL_O_CMDSTA 0x00000004 // Interrupt Flags From RF Hardware Modules -#define RFC_DBELL_O_RFHWIFG 0x00000008 +#define RFC_DBELL_O_RFHWIFG 0x00000008 // Interrupt Enable For RF Hardware Modules -#define RFC_DBELL_O_RFHWIEN 0x0000000C +#define RFC_DBELL_O_RFHWIEN 0x0000000C // Interrupt Flags For Command and Packet Engine Generated Interrupts -#define RFC_DBELL_O_RFCPEIFG 0x00000010 +#define RFC_DBELL_O_RFCPEIFG 0x00000010 // Interrupt Enable For Command and Packet Engine Generated Interrupts -#define RFC_DBELL_O_RFCPEIEN 0x00000014 +#define RFC_DBELL_O_RFCPEIEN 0x00000014 // Interrupt Vector Selection For Command and Packet Engine Generated // Interrupts -#define RFC_DBELL_O_RFCPEISL 0x00000018 +#define RFC_DBELL_O_RFCPEISL 0x00000018 // Doorbell Command Acknowledgement Interrupt Flag -#define RFC_DBELL_O_RFACKIFG 0x0000001C +#define RFC_DBELL_O_RFACKIFG 0x0000001C // RF Core General Purpose Output Control -#define RFC_DBELL_O_SYSGPOCTL 0x00000020 +#define RFC_DBELL_O_SYSGPOCTL 0x00000020 //***************************************************************************** // @@ -80,9 +80,9 @@ // // Command register. Raises an interrupt to the Command and packet engine (CPE) // upon write. -#define RFC_DBELL_CMDR_CMD_W 32 -#define RFC_DBELL_CMDR_CMD_M 0xFFFFFFFF -#define RFC_DBELL_CMDR_CMD_S 0 +#define RFC_DBELL_CMDR_CMD_W 32 +#define RFC_DBELL_CMDR_CMD_M 0xFFFFFFFF +#define RFC_DBELL_CMDR_CMD_S 0 //***************************************************************************** // @@ -92,9 +92,9 @@ // Field: [31:0] STAT // // Status of the last command used -#define RFC_DBELL_CMDSTA_STAT_W 32 -#define RFC_DBELL_CMDSTA_STAT_M 0xFFFFFFFF -#define RFC_DBELL_CMDSTA_STAT_S 0 +#define RFC_DBELL_CMDSTA_STAT_W 32 +#define RFC_DBELL_CMDSTA_STAT_M 0xFFFFFFFF +#define RFC_DBELL_CMDSTA_STAT_S 0 //***************************************************************************** // @@ -105,118 +105,118 @@ // // Radio timer channel 7 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH7 0x00080000 -#define RFC_DBELL_RFHWIFG_RATCH7_BITN 19 -#define RFC_DBELL_RFHWIFG_RATCH7_M 0x00080000 -#define RFC_DBELL_RFHWIFG_RATCH7_S 19 +#define RFC_DBELL_RFHWIFG_RATCH7 0x00080000 +#define RFC_DBELL_RFHWIFG_RATCH7_BITN 19 +#define RFC_DBELL_RFHWIFG_RATCH7_M 0x00080000 +#define RFC_DBELL_RFHWIFG_RATCH7_S 19 // Field: [18] RATCH6 // // Radio timer channel 6 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH6 0x00040000 -#define RFC_DBELL_RFHWIFG_RATCH6_BITN 18 -#define RFC_DBELL_RFHWIFG_RATCH6_M 0x00040000 -#define RFC_DBELL_RFHWIFG_RATCH6_S 18 +#define RFC_DBELL_RFHWIFG_RATCH6 0x00040000 +#define RFC_DBELL_RFHWIFG_RATCH6_BITN 18 +#define RFC_DBELL_RFHWIFG_RATCH6_M 0x00040000 +#define RFC_DBELL_RFHWIFG_RATCH6_S 18 // Field: [17] RATCH5 // // Radio timer channel 5 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH5 0x00020000 -#define RFC_DBELL_RFHWIFG_RATCH5_BITN 17 -#define RFC_DBELL_RFHWIFG_RATCH5_M 0x00020000 -#define RFC_DBELL_RFHWIFG_RATCH5_S 17 +#define RFC_DBELL_RFHWIFG_RATCH5 0x00020000 +#define RFC_DBELL_RFHWIFG_RATCH5_BITN 17 +#define RFC_DBELL_RFHWIFG_RATCH5_M 0x00020000 +#define RFC_DBELL_RFHWIFG_RATCH5_S 17 // Field: [16] RATCH4 // // Radio timer channel 4 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH4 0x00010000 -#define RFC_DBELL_RFHWIFG_RATCH4_BITN 16 -#define RFC_DBELL_RFHWIFG_RATCH4_M 0x00010000 -#define RFC_DBELL_RFHWIFG_RATCH4_S 16 +#define RFC_DBELL_RFHWIFG_RATCH4 0x00010000 +#define RFC_DBELL_RFHWIFG_RATCH4_BITN 16 +#define RFC_DBELL_RFHWIFG_RATCH4_M 0x00010000 +#define RFC_DBELL_RFHWIFG_RATCH4_S 16 // Field: [15] RATCH3 // // Radio timer channel 3 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH3 0x00008000 -#define RFC_DBELL_RFHWIFG_RATCH3_BITN 15 -#define RFC_DBELL_RFHWIFG_RATCH3_M 0x00008000 -#define RFC_DBELL_RFHWIFG_RATCH3_S 15 +#define RFC_DBELL_RFHWIFG_RATCH3 0x00008000 +#define RFC_DBELL_RFHWIFG_RATCH3_BITN 15 +#define RFC_DBELL_RFHWIFG_RATCH3_M 0x00008000 +#define RFC_DBELL_RFHWIFG_RATCH3_S 15 // Field: [14] RATCH2 // // Radio timer channel 2 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH2 0x00004000 -#define RFC_DBELL_RFHWIFG_RATCH2_BITN 14 -#define RFC_DBELL_RFHWIFG_RATCH2_M 0x00004000 -#define RFC_DBELL_RFHWIFG_RATCH2_S 14 +#define RFC_DBELL_RFHWIFG_RATCH2 0x00004000 +#define RFC_DBELL_RFHWIFG_RATCH2_BITN 14 +#define RFC_DBELL_RFHWIFG_RATCH2_M 0x00004000 +#define RFC_DBELL_RFHWIFG_RATCH2_S 14 // Field: [13] RATCH1 // // Radio timer channel 1 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH1 0x00002000 -#define RFC_DBELL_RFHWIFG_RATCH1_BITN 13 -#define RFC_DBELL_RFHWIFG_RATCH1_M 0x00002000 -#define RFC_DBELL_RFHWIFG_RATCH1_S 13 +#define RFC_DBELL_RFHWIFG_RATCH1 0x00002000 +#define RFC_DBELL_RFHWIFG_RATCH1_BITN 13 +#define RFC_DBELL_RFHWIFG_RATCH1_M 0x00002000 +#define RFC_DBELL_RFHWIFG_RATCH1_S 13 // Field: [12] RATCH0 // // Radio timer channel 0 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH0 0x00001000 -#define RFC_DBELL_RFHWIFG_RATCH0_BITN 12 -#define RFC_DBELL_RFHWIFG_RATCH0_M 0x00001000 -#define RFC_DBELL_RFHWIFG_RATCH0_S 12 +#define RFC_DBELL_RFHWIFG_RATCH0 0x00001000 +#define RFC_DBELL_RFHWIFG_RATCH0_BITN 12 +#define RFC_DBELL_RFHWIFG_RATCH0_M 0x00001000 +#define RFC_DBELL_RFHWIFG_RATCH0_S 12 // Field: [11] RFESOFT2 // // RF engine software defined interrupt 2 flag. Write zero to clear flag. Write // to one has no effect. -#define RFC_DBELL_RFHWIFG_RFESOFT2 0x00000800 -#define RFC_DBELL_RFHWIFG_RFESOFT2_BITN 11 -#define RFC_DBELL_RFHWIFG_RFESOFT2_M 0x00000800 -#define RFC_DBELL_RFHWIFG_RFESOFT2_S 11 +#define RFC_DBELL_RFHWIFG_RFESOFT2 0x00000800 +#define RFC_DBELL_RFHWIFG_RFESOFT2_BITN 11 +#define RFC_DBELL_RFHWIFG_RFESOFT2_M 0x00000800 +#define RFC_DBELL_RFHWIFG_RFESOFT2_S 11 // Field: [10] RFESOFT1 // // RF engine software defined interrupt 1 flag. Write zero to clear flag. Write // to one has no effect. -#define RFC_DBELL_RFHWIFG_RFESOFT1 0x00000400 -#define RFC_DBELL_RFHWIFG_RFESOFT1_BITN 10 -#define RFC_DBELL_RFHWIFG_RFESOFT1_M 0x00000400 -#define RFC_DBELL_RFHWIFG_RFESOFT1_S 10 +#define RFC_DBELL_RFHWIFG_RFESOFT1 0x00000400 +#define RFC_DBELL_RFHWIFG_RFESOFT1_BITN 10 +#define RFC_DBELL_RFHWIFG_RFESOFT1_M 0x00000400 +#define RFC_DBELL_RFHWIFG_RFESOFT1_S 10 // Field: [9] RFESOFT0 // // RF engine software defined interrupt 0 flag. Write zero to clear flag. Write // to one has no effect. -#define RFC_DBELL_RFHWIFG_RFESOFT0 0x00000200 -#define RFC_DBELL_RFHWIFG_RFESOFT0_BITN 9 -#define RFC_DBELL_RFHWIFG_RFESOFT0_M 0x00000200 -#define RFC_DBELL_RFHWIFG_RFESOFT0_S 9 +#define RFC_DBELL_RFHWIFG_RFESOFT0 0x00000200 +#define RFC_DBELL_RFHWIFG_RFESOFT0_BITN 9 +#define RFC_DBELL_RFHWIFG_RFESOFT0_M 0x00000200 +#define RFC_DBELL_RFHWIFG_RFESOFT0_S 9 // Field: [8] RFEDONE // // RF engine command done interrupt flag. Write zero to clear flag. Write to // one has no effect. -#define RFC_DBELL_RFHWIFG_RFEDONE 0x00000100 -#define RFC_DBELL_RFHWIFG_RFEDONE_BITN 8 -#define RFC_DBELL_RFHWIFG_RFEDONE_M 0x00000100 -#define RFC_DBELL_RFHWIFG_RFEDONE_S 8 +#define RFC_DBELL_RFHWIFG_RFEDONE 0x00000100 +#define RFC_DBELL_RFHWIFG_RFEDONE_BITN 8 +#define RFC_DBELL_RFHWIFG_RFEDONE_M 0x00000100 +#define RFC_DBELL_RFHWIFG_RFEDONE_S 8 // Field: [6] TRCTK // // Debug tracer system tick interrupt flag. Write zero to clear flag. Write to // one has no effect. -#define RFC_DBELL_RFHWIFG_TRCTK 0x00000040 -#define RFC_DBELL_RFHWIFG_TRCTK_BITN 6 -#define RFC_DBELL_RFHWIFG_TRCTK_M 0x00000040 -#define RFC_DBELL_RFHWIFG_TRCTK_S 6 +#define RFC_DBELL_RFHWIFG_TRCTK 0x00000040 +#define RFC_DBELL_RFHWIFG_TRCTK_BITN 6 +#define RFC_DBELL_RFHWIFG_TRCTK_M 0x00000040 +#define RFC_DBELL_RFHWIFG_TRCTK_S 6 // Field: [5] MDMSOFT // @@ -224,46 +224,46 @@ // raised by modem when the synchronization word is received. The CPE may // decide to reject the packet based on its header (protocol specific). Write // zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFHWIFG_MDMSOFT 0x00000020 -#define RFC_DBELL_RFHWIFG_MDMSOFT_BITN 5 -#define RFC_DBELL_RFHWIFG_MDMSOFT_M 0x00000020 -#define RFC_DBELL_RFHWIFG_MDMSOFT_S 5 +#define RFC_DBELL_RFHWIFG_MDMSOFT 0x00000020 +#define RFC_DBELL_RFHWIFG_MDMSOFT_BITN 5 +#define RFC_DBELL_RFHWIFG_MDMSOFT_M 0x00000020 +#define RFC_DBELL_RFHWIFG_MDMSOFT_S 5 // Field: [4] MDMOUT // // Modem FIFO output interrupt flag. Write zero to clear flag. Write to one has // no effect. -#define RFC_DBELL_RFHWIFG_MDMOUT 0x00000010 -#define RFC_DBELL_RFHWIFG_MDMOUT_BITN 4 -#define RFC_DBELL_RFHWIFG_MDMOUT_M 0x00000010 -#define RFC_DBELL_RFHWIFG_MDMOUT_S 4 +#define RFC_DBELL_RFHWIFG_MDMOUT 0x00000010 +#define RFC_DBELL_RFHWIFG_MDMOUT_BITN 4 +#define RFC_DBELL_RFHWIFG_MDMOUT_M 0x00000010 +#define RFC_DBELL_RFHWIFG_MDMOUT_S 4 // Field: [3] MDMIN // // Modem FIFO input interrupt flag. Write zero to clear flag. Write to one has // no effect. -#define RFC_DBELL_RFHWIFG_MDMIN 0x00000008 -#define RFC_DBELL_RFHWIFG_MDMIN_BITN 3 -#define RFC_DBELL_RFHWIFG_MDMIN_M 0x00000008 -#define RFC_DBELL_RFHWIFG_MDMIN_S 3 +#define RFC_DBELL_RFHWIFG_MDMIN 0x00000008 +#define RFC_DBELL_RFHWIFG_MDMIN_BITN 3 +#define RFC_DBELL_RFHWIFG_MDMIN_M 0x00000008 +#define RFC_DBELL_RFHWIFG_MDMIN_S 3 // Field: [2] MDMDONE // // Modem command done interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_MDMDONE 0x00000004 -#define RFC_DBELL_RFHWIFG_MDMDONE_BITN 2 -#define RFC_DBELL_RFHWIFG_MDMDONE_M 0x00000004 -#define RFC_DBELL_RFHWIFG_MDMDONE_S 2 +#define RFC_DBELL_RFHWIFG_MDMDONE 0x00000004 +#define RFC_DBELL_RFHWIFG_MDMDONE_BITN 2 +#define RFC_DBELL_RFHWIFG_MDMDONE_M 0x00000004 +#define RFC_DBELL_RFHWIFG_MDMDONE_S 2 // Field: [1] FSCA // // Frequency synthesizer calibration accelerator interrupt flag. Write zero to // clear flag. Write to one has no effect. -#define RFC_DBELL_RFHWIFG_FSCA 0x00000002 -#define RFC_DBELL_RFHWIFG_FSCA_BITN 1 -#define RFC_DBELL_RFHWIFG_FSCA_M 0x00000002 -#define RFC_DBELL_RFHWIFG_FSCA_S 1 +#define RFC_DBELL_RFHWIFG_FSCA 0x00000002 +#define RFC_DBELL_RFHWIFG_FSCA_BITN 1 +#define RFC_DBELL_RFHWIFG_FSCA_M 0x00000002 +#define RFC_DBELL_RFHWIFG_FSCA_S 1 //***************************************************************************** // @@ -273,146 +273,146 @@ // Field: [19] RATCH7 // // Interrupt enable for RFHWIFG.RATCH7. -#define RFC_DBELL_RFHWIEN_RATCH7 0x00080000 -#define RFC_DBELL_RFHWIEN_RATCH7_BITN 19 -#define RFC_DBELL_RFHWIEN_RATCH7_M 0x00080000 -#define RFC_DBELL_RFHWIEN_RATCH7_S 19 +#define RFC_DBELL_RFHWIEN_RATCH7 0x00080000 +#define RFC_DBELL_RFHWIEN_RATCH7_BITN 19 +#define RFC_DBELL_RFHWIEN_RATCH7_M 0x00080000 +#define RFC_DBELL_RFHWIEN_RATCH7_S 19 // Field: [18] RATCH6 // // Interrupt enable for RFHWIFG.RATCH6. -#define RFC_DBELL_RFHWIEN_RATCH6 0x00040000 -#define RFC_DBELL_RFHWIEN_RATCH6_BITN 18 -#define RFC_DBELL_RFHWIEN_RATCH6_M 0x00040000 -#define RFC_DBELL_RFHWIEN_RATCH6_S 18 +#define RFC_DBELL_RFHWIEN_RATCH6 0x00040000 +#define RFC_DBELL_RFHWIEN_RATCH6_BITN 18 +#define RFC_DBELL_RFHWIEN_RATCH6_M 0x00040000 +#define RFC_DBELL_RFHWIEN_RATCH6_S 18 // Field: [17] RATCH5 // // Interrupt enable for RFHWIFG.RATCH5. -#define RFC_DBELL_RFHWIEN_RATCH5 0x00020000 -#define RFC_DBELL_RFHWIEN_RATCH5_BITN 17 -#define RFC_DBELL_RFHWIEN_RATCH5_M 0x00020000 -#define RFC_DBELL_RFHWIEN_RATCH5_S 17 +#define RFC_DBELL_RFHWIEN_RATCH5 0x00020000 +#define RFC_DBELL_RFHWIEN_RATCH5_BITN 17 +#define RFC_DBELL_RFHWIEN_RATCH5_M 0x00020000 +#define RFC_DBELL_RFHWIEN_RATCH5_S 17 // Field: [16] RATCH4 // // Interrupt enable for RFHWIFG.RATCH4. -#define RFC_DBELL_RFHWIEN_RATCH4 0x00010000 -#define RFC_DBELL_RFHWIEN_RATCH4_BITN 16 -#define RFC_DBELL_RFHWIEN_RATCH4_M 0x00010000 -#define RFC_DBELL_RFHWIEN_RATCH4_S 16 +#define RFC_DBELL_RFHWIEN_RATCH4 0x00010000 +#define RFC_DBELL_RFHWIEN_RATCH4_BITN 16 +#define RFC_DBELL_RFHWIEN_RATCH4_M 0x00010000 +#define RFC_DBELL_RFHWIEN_RATCH4_S 16 // Field: [15] RATCH3 // // Interrupt enable for RFHWIFG.RATCH3. -#define RFC_DBELL_RFHWIEN_RATCH3 0x00008000 -#define RFC_DBELL_RFHWIEN_RATCH3_BITN 15 -#define RFC_DBELL_RFHWIEN_RATCH3_M 0x00008000 -#define RFC_DBELL_RFHWIEN_RATCH3_S 15 +#define RFC_DBELL_RFHWIEN_RATCH3 0x00008000 +#define RFC_DBELL_RFHWIEN_RATCH3_BITN 15 +#define RFC_DBELL_RFHWIEN_RATCH3_M 0x00008000 +#define RFC_DBELL_RFHWIEN_RATCH3_S 15 // Field: [14] RATCH2 // // Interrupt enable for RFHWIFG.RATCH2. -#define RFC_DBELL_RFHWIEN_RATCH2 0x00004000 -#define RFC_DBELL_RFHWIEN_RATCH2_BITN 14 -#define RFC_DBELL_RFHWIEN_RATCH2_M 0x00004000 -#define RFC_DBELL_RFHWIEN_RATCH2_S 14 +#define RFC_DBELL_RFHWIEN_RATCH2 0x00004000 +#define RFC_DBELL_RFHWIEN_RATCH2_BITN 14 +#define RFC_DBELL_RFHWIEN_RATCH2_M 0x00004000 +#define RFC_DBELL_RFHWIEN_RATCH2_S 14 // Field: [13] RATCH1 // // Interrupt enable for RFHWIFG.RATCH1. -#define RFC_DBELL_RFHWIEN_RATCH1 0x00002000 -#define RFC_DBELL_RFHWIEN_RATCH1_BITN 13 -#define RFC_DBELL_RFHWIEN_RATCH1_M 0x00002000 -#define RFC_DBELL_RFHWIEN_RATCH1_S 13 +#define RFC_DBELL_RFHWIEN_RATCH1 0x00002000 +#define RFC_DBELL_RFHWIEN_RATCH1_BITN 13 +#define RFC_DBELL_RFHWIEN_RATCH1_M 0x00002000 +#define RFC_DBELL_RFHWIEN_RATCH1_S 13 // Field: [12] RATCH0 // // Interrupt enable for RFHWIFG.RATCH0. -#define RFC_DBELL_RFHWIEN_RATCH0 0x00001000 -#define RFC_DBELL_RFHWIEN_RATCH0_BITN 12 -#define RFC_DBELL_RFHWIEN_RATCH0_M 0x00001000 -#define RFC_DBELL_RFHWIEN_RATCH0_S 12 +#define RFC_DBELL_RFHWIEN_RATCH0 0x00001000 +#define RFC_DBELL_RFHWIEN_RATCH0_BITN 12 +#define RFC_DBELL_RFHWIEN_RATCH0_M 0x00001000 +#define RFC_DBELL_RFHWIEN_RATCH0_S 12 // Field: [11] RFESOFT2 // // Interrupt enable for RFHWIFG.RFESOFT2. -#define RFC_DBELL_RFHWIEN_RFESOFT2 0x00000800 -#define RFC_DBELL_RFHWIEN_RFESOFT2_BITN 11 -#define RFC_DBELL_RFHWIEN_RFESOFT2_M 0x00000800 -#define RFC_DBELL_RFHWIEN_RFESOFT2_S 11 +#define RFC_DBELL_RFHWIEN_RFESOFT2 0x00000800 +#define RFC_DBELL_RFHWIEN_RFESOFT2_BITN 11 +#define RFC_DBELL_RFHWIEN_RFESOFT2_M 0x00000800 +#define RFC_DBELL_RFHWIEN_RFESOFT2_S 11 // Field: [10] RFESOFT1 // // Interrupt enable for RFHWIFG.RFESOFT1. -#define RFC_DBELL_RFHWIEN_RFESOFT1 0x00000400 -#define RFC_DBELL_RFHWIEN_RFESOFT1_BITN 10 -#define RFC_DBELL_RFHWIEN_RFESOFT1_M 0x00000400 -#define RFC_DBELL_RFHWIEN_RFESOFT1_S 10 +#define RFC_DBELL_RFHWIEN_RFESOFT1 0x00000400 +#define RFC_DBELL_RFHWIEN_RFESOFT1_BITN 10 +#define RFC_DBELL_RFHWIEN_RFESOFT1_M 0x00000400 +#define RFC_DBELL_RFHWIEN_RFESOFT1_S 10 // Field: [9] RFESOFT0 // // Interrupt enable for RFHWIFG.RFESOFT0. -#define RFC_DBELL_RFHWIEN_RFESOFT0 0x00000200 -#define RFC_DBELL_RFHWIEN_RFESOFT0_BITN 9 -#define RFC_DBELL_RFHWIEN_RFESOFT0_M 0x00000200 -#define RFC_DBELL_RFHWIEN_RFESOFT0_S 9 +#define RFC_DBELL_RFHWIEN_RFESOFT0 0x00000200 +#define RFC_DBELL_RFHWIEN_RFESOFT0_BITN 9 +#define RFC_DBELL_RFHWIEN_RFESOFT0_M 0x00000200 +#define RFC_DBELL_RFHWIEN_RFESOFT0_S 9 // Field: [8] RFEDONE // // Interrupt enable for RFHWIFG.RFEDONE. -#define RFC_DBELL_RFHWIEN_RFEDONE 0x00000100 -#define RFC_DBELL_RFHWIEN_RFEDONE_BITN 8 -#define RFC_DBELL_RFHWIEN_RFEDONE_M 0x00000100 -#define RFC_DBELL_RFHWIEN_RFEDONE_S 8 +#define RFC_DBELL_RFHWIEN_RFEDONE 0x00000100 +#define RFC_DBELL_RFHWIEN_RFEDONE_BITN 8 +#define RFC_DBELL_RFHWIEN_RFEDONE_M 0x00000100 +#define RFC_DBELL_RFHWIEN_RFEDONE_S 8 // Field: [6] TRCTK // // Interrupt enable for RFHWIFG.TRCTK. -#define RFC_DBELL_RFHWIEN_TRCTK 0x00000040 -#define RFC_DBELL_RFHWIEN_TRCTK_BITN 6 -#define RFC_DBELL_RFHWIEN_TRCTK_M 0x00000040 -#define RFC_DBELL_RFHWIEN_TRCTK_S 6 +#define RFC_DBELL_RFHWIEN_TRCTK 0x00000040 +#define RFC_DBELL_RFHWIEN_TRCTK_BITN 6 +#define RFC_DBELL_RFHWIEN_TRCTK_M 0x00000040 +#define RFC_DBELL_RFHWIEN_TRCTK_S 6 // Field: [5] MDMSOFT // // Interrupt enable for RFHWIFG.MDMSOFT. -#define RFC_DBELL_RFHWIEN_MDMSOFT 0x00000020 -#define RFC_DBELL_RFHWIEN_MDMSOFT_BITN 5 -#define RFC_DBELL_RFHWIEN_MDMSOFT_M 0x00000020 -#define RFC_DBELL_RFHWIEN_MDMSOFT_S 5 +#define RFC_DBELL_RFHWIEN_MDMSOFT 0x00000020 +#define RFC_DBELL_RFHWIEN_MDMSOFT_BITN 5 +#define RFC_DBELL_RFHWIEN_MDMSOFT_M 0x00000020 +#define RFC_DBELL_RFHWIEN_MDMSOFT_S 5 // Field: [4] MDMOUT // // Interrupt enable for RFHWIFG.MDMOUT. -#define RFC_DBELL_RFHWIEN_MDMOUT 0x00000010 -#define RFC_DBELL_RFHWIEN_MDMOUT_BITN 4 -#define RFC_DBELL_RFHWIEN_MDMOUT_M 0x00000010 -#define RFC_DBELL_RFHWIEN_MDMOUT_S 4 +#define RFC_DBELL_RFHWIEN_MDMOUT 0x00000010 +#define RFC_DBELL_RFHWIEN_MDMOUT_BITN 4 +#define RFC_DBELL_RFHWIEN_MDMOUT_M 0x00000010 +#define RFC_DBELL_RFHWIEN_MDMOUT_S 4 // Field: [3] MDMIN // // Interrupt enable for RFHWIFG.MDMIN. -#define RFC_DBELL_RFHWIEN_MDMIN 0x00000008 -#define RFC_DBELL_RFHWIEN_MDMIN_BITN 3 -#define RFC_DBELL_RFHWIEN_MDMIN_M 0x00000008 -#define RFC_DBELL_RFHWIEN_MDMIN_S 3 +#define RFC_DBELL_RFHWIEN_MDMIN 0x00000008 +#define RFC_DBELL_RFHWIEN_MDMIN_BITN 3 +#define RFC_DBELL_RFHWIEN_MDMIN_M 0x00000008 +#define RFC_DBELL_RFHWIEN_MDMIN_S 3 // Field: [2] MDMDONE // // Interrupt enable for RFHWIFG.MDMDONE. -#define RFC_DBELL_RFHWIEN_MDMDONE 0x00000004 -#define RFC_DBELL_RFHWIEN_MDMDONE_BITN 2 -#define RFC_DBELL_RFHWIEN_MDMDONE_M 0x00000004 -#define RFC_DBELL_RFHWIEN_MDMDONE_S 2 +#define RFC_DBELL_RFHWIEN_MDMDONE 0x00000004 +#define RFC_DBELL_RFHWIEN_MDMDONE_BITN 2 +#define RFC_DBELL_RFHWIEN_MDMDONE_M 0x00000004 +#define RFC_DBELL_RFHWIEN_MDMDONE_S 2 // Field: [1] FSCA // // Interrupt enable for RFHWIFG.FSCA. -#define RFC_DBELL_RFHWIEN_FSCA 0x00000002 -#define RFC_DBELL_RFHWIEN_FSCA_BITN 1 -#define RFC_DBELL_RFHWIEN_FSCA_M 0x00000002 -#define RFC_DBELL_RFHWIEN_FSCA_S 1 +#define RFC_DBELL_RFHWIEN_FSCA 0x00000002 +#define RFC_DBELL_RFHWIEN_FSCA_BITN 1 +#define RFC_DBELL_RFHWIEN_FSCA_M 0x00000002 +#define RFC_DBELL_RFHWIEN_FSCA_S 1 //***************************************************************************** // @@ -425,82 +425,82 @@ // unexpected error. A reset of the CPE is needed. This can be done by // switching the RF Core power domain off and on in PRCM:PDCTL1RFC. Write zero // to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR 0x80000000 -#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_BITN 31 -#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_M 0x80000000 -#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_S 31 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_S 31 // Field: [30] BOOT_DONE // // Interrupt flag 30. The command and packet engine (CPE) boot is finished. // Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_BOOT_DONE 0x40000000 -#define RFC_DBELL_RFCPEIFG_BOOT_DONE_BITN 30 -#define RFC_DBELL_RFCPEIFG_BOOT_DONE_M 0x40000000 -#define RFC_DBELL_RFCPEIFG_BOOT_DONE_S 30 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_S 30 // Field: [29] MODULES_UNLOCKED // // Interrupt flag 29. As part of command and packet engine (CPE) boot process, // it has opened access to RF Core modules and memories. Write zero to clear // flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED 0x20000000 -#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_BITN 29 -#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_M 0x20000000 -#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_S 29 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_S 29 // Field: [28] SYNTH_NO_LOCK // // Interrupt flag 28. The phase-locked loop in frequency synthesizer has // reported loss of lock. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK 0x10000000 -#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_BITN 28 -#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_M 0x10000000 -#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_S 28 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_S 28 // Field: [27] IRQ27 // // Interrupt flag 27. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_IRQ27 0x08000000 -#define RFC_DBELL_RFCPEIFG_IRQ27_BITN 27 -#define RFC_DBELL_RFCPEIFG_IRQ27_M 0x08000000 -#define RFC_DBELL_RFCPEIFG_IRQ27_S 27 +#define RFC_DBELL_RFCPEIFG_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEIFG_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEIFG_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEIFG_IRQ27_S 27 // Field: [26] RX_ABORTED // // Interrupt flag 26. Packet reception stopped before packet was done. Write // zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_ABORTED 0x04000000 -#define RFC_DBELL_RFCPEIFG_RX_ABORTED_BITN 26 -#define RFC_DBELL_RFCPEIFG_RX_ABORTED_M 0x04000000 -#define RFC_DBELL_RFCPEIFG_RX_ABORTED_S 26 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_S 26 // Field: [25] RX_N_DATA_WRITTEN // // Interrupt flag 25. Specified number of bytes written to partial read Rx // buffer. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN 0x02000000 -#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_BITN 25 -#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_M 0x02000000 -#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_S 25 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_S 25 // Field: [24] RX_DATA_WRITTEN // // Interrupt flag 24. Data written to partial read Rx buffer. Write zero to // clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN 0x01000000 -#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_BITN 24 -#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_M 0x01000000 -#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_S 24 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_S 24 // Field: [23] RX_ENTRY_DONE // // Interrupt flag 23. Rx queue data entry changing state to finished. Write // zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE 0x00800000 -#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_BITN 23 -#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_M 0x00800000 -#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_S 23 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_S 23 // Field: [22] RX_BUF_FULL // @@ -508,194 +508,194 @@ // Packet received that did not fit in the Rx queue. IEEE 802.15.4 mode: Frame // received that did not fit in the Rx queue. Write zero to clear flag. Write // to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL 0x00400000 -#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_BITN 22 -#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_M 0x00400000 -#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_S 22 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_S 22 // Field: [21] RX_CTRL_ACK // // Interrupt flag 21. BLE mode only: LL control packet received with CRC OK, // not to be ignored, then acknowledgement sent. Write zero to clear flag. // Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK 0x00200000 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_BITN 21 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_M 0x00200000 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_S 21 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_S 21 // Field: [20] RX_CTRL // // Interrupt flag 20. BLE mode only: LL control packet received with CRC OK, // not to be ignored. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_CTRL 0x00100000 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_BITN 20 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_M 0x00100000 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_S 20 +#define RFC_DBELL_RFCPEIFG_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_S 20 // Field: [19] RX_EMPTY // // Interrupt flag 19. BLE mode only: Packet received with CRC OK, not to be // ignored, no payload. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_EMPTY 0x00080000 -#define RFC_DBELL_RFCPEIFG_RX_EMPTY_BITN 19 -#define RFC_DBELL_RFCPEIFG_RX_EMPTY_M 0x00080000 -#define RFC_DBELL_RFCPEIFG_RX_EMPTY_S 19 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_S 19 // Field: [18] RX_IGNORED // // Interrupt flag 18. Packet received, but can be ignored. BLE mode: Packet // received with CRC OK, but to be ignored. IEEE 802.15.4 mode: Frame received // with ignore flag set. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_IGNORED 0x00040000 -#define RFC_DBELL_RFCPEIFG_RX_IGNORED_BITN 18 -#define RFC_DBELL_RFCPEIFG_RX_IGNORED_M 0x00040000 -#define RFC_DBELL_RFCPEIFG_RX_IGNORED_S 18 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_S 18 // Field: [17] RX_NOK // // Interrupt flag 17. Packet received with CRC error. BLE mode: Packet received // with CRC error. IEEE 802.15.4 mode: Frame received with CRC error. Write // zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_NOK 0x00020000 -#define RFC_DBELL_RFCPEIFG_RX_NOK_BITN 17 -#define RFC_DBELL_RFCPEIFG_RX_NOK_M 0x00020000 -#define RFC_DBELL_RFCPEIFG_RX_NOK_S 17 +#define RFC_DBELL_RFCPEIFG_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEIFG_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEIFG_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEIFG_RX_NOK_S 17 // Field: [16] RX_OK // // Interrupt flag 16. Packet received correctly. BLE mode: Packet received with // CRC OK, payload, and not to be ignored. IEEE 802.15.4 mode: Frame received // with CRC OK. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_OK 0x00010000 -#define RFC_DBELL_RFCPEIFG_RX_OK_BITN 16 -#define RFC_DBELL_RFCPEIFG_RX_OK_M 0x00010000 -#define RFC_DBELL_RFCPEIFG_RX_OK_S 16 +#define RFC_DBELL_RFCPEIFG_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEIFG_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEIFG_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEIFG_RX_OK_S 16 // Field: [15] IRQ15 // // Interrupt flag 15. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_IRQ15 0x00008000 -#define RFC_DBELL_RFCPEIFG_IRQ15_BITN 15 -#define RFC_DBELL_RFCPEIFG_IRQ15_M 0x00008000 -#define RFC_DBELL_RFCPEIFG_IRQ15_S 15 +#define RFC_DBELL_RFCPEIFG_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEIFG_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEIFG_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEIFG_IRQ15_S 15 // Field: [14] IRQ14 // // Interrupt flag 14. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_IRQ14 0x00004000 -#define RFC_DBELL_RFCPEIFG_IRQ14_BITN 14 -#define RFC_DBELL_RFCPEIFG_IRQ14_M 0x00004000 -#define RFC_DBELL_RFCPEIFG_IRQ14_S 14 +#define RFC_DBELL_RFCPEIFG_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEIFG_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEIFG_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEIFG_IRQ14_S 14 // Field: [13] IRQ13 // // Interrupt flag 13. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_IRQ13 0x00002000 -#define RFC_DBELL_RFCPEIFG_IRQ13_BITN 13 -#define RFC_DBELL_RFCPEIFG_IRQ13_M 0x00002000 -#define RFC_DBELL_RFCPEIFG_IRQ13_S 13 +#define RFC_DBELL_RFCPEIFG_IRQ13 0x00002000 +#define RFC_DBELL_RFCPEIFG_IRQ13_BITN 13 +#define RFC_DBELL_RFCPEIFG_IRQ13_M 0x00002000 +#define RFC_DBELL_RFCPEIFG_IRQ13_S 13 // Field: [12] IRQ12 // // Interrupt flag 12. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_IRQ12 0x00001000 -#define RFC_DBELL_RFCPEIFG_IRQ12_BITN 12 -#define RFC_DBELL_RFCPEIFG_IRQ12_M 0x00001000 -#define RFC_DBELL_RFCPEIFG_IRQ12_S 12 +#define RFC_DBELL_RFCPEIFG_IRQ12 0x00001000 +#define RFC_DBELL_RFCPEIFG_IRQ12_BITN 12 +#define RFC_DBELL_RFCPEIFG_IRQ12_M 0x00001000 +#define RFC_DBELL_RFCPEIFG_IRQ12_S 12 // Field: [11] TX_BUFFER_CHANGED // // Interrupt flag 11. BLE mode only: A buffer change is complete after // CMD_BLE_ADV_PAYLOAD. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED 0x00000800 -#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_BITN 11 -#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_M 0x00000800 -#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_S 11 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_S 11 // Field: [10] TX_ENTRY_DONE // // Interrupt flag 10. Tx queue data entry state changed to finished. Write zero // to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE 0x00000400 -#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_BITN 10 -#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_M 0x00000400 -#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_S 10 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_S 10 // Field: [9] TX_RETRANS // // Interrupt flag 9. BLE mode only: Packet retransmitted. Write zero to clear // flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_RETRANS 0x00000200 -#define RFC_DBELL_RFCPEIFG_TX_RETRANS_BITN 9 -#define RFC_DBELL_RFCPEIFG_TX_RETRANS_M 0x00000200 -#define RFC_DBELL_RFCPEIFG_TX_RETRANS_S 9 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_S 9 // Field: [8] TX_CTRL_ACK_ACK // // Interrupt flag 8. BLE mode only: Acknowledgement received on a transmitted // LL control packet, and acknowledgement transmitted for that packet. Write // zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK 0x00000100 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_BITN 8 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_M 0x00000100 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_S 8 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_S 8 // Field: [7] TX_CTRL_ACK // // Interrupt flag 7. BLE mode: Acknowledgement received on a transmitted LL // control packet. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK 0x00000080 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_BITN 7 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_M 0x00000080 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_S 7 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_S 7 // Field: [6] TX_CTRL // // Interrupt flag 6. BLE mode: Transmitted LL control packet. Write zero to // clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_CTRL 0x00000040 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_BITN 6 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_M 0x00000040 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_S 6 +#define RFC_DBELL_RFCPEIFG_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_S 6 // Field: [5] TX_ACK // // Interrupt flag 5. BLE mode: Acknowledgement received on a transmitted // packet. IEEE 802.15.4 mode: Transmitted automatic ACK frame. Write zero to // clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_ACK 0x00000020 -#define RFC_DBELL_RFCPEIFG_TX_ACK_BITN 5 -#define RFC_DBELL_RFCPEIFG_TX_ACK_M 0x00000020 -#define RFC_DBELL_RFCPEIFG_TX_ACK_S 5 +#define RFC_DBELL_RFCPEIFG_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEIFG_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEIFG_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEIFG_TX_ACK_S 5 // Field: [4] TX_DONE // // Interrupt flag 4. Packet transmitted. (BLE mode: A packet has been // transmitted.) (IEEE 802.15.4 mode: A frame has been transmitted). Write zero // to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_DONE 0x00000010 -#define RFC_DBELL_RFCPEIFG_TX_DONE_BITN 4 -#define RFC_DBELL_RFCPEIFG_TX_DONE_M 0x00000010 -#define RFC_DBELL_RFCPEIFG_TX_DONE_S 4 +#define RFC_DBELL_RFCPEIFG_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEIFG_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEIFG_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEIFG_TX_DONE_S 4 // Field: [3] LAST_FG_COMMAND_DONE // // Interrupt flag 3. IEEE 802.15.4 mode only: The last foreground radio // operation command in a chain of commands has finished. Write zero to clear // flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE 0x00000008 -#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_BITN 3 -#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M 0x00000008 -#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_S 3 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_S 3 // Field: [2] FG_COMMAND_DONE // // Interrupt flag 2. IEEE 802.15.4 mode only: A foreground radio operation // command has finished. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE 0x00000004 -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_BITN 2 -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_M 0x00000004 -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_S 2 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_S 2 // Field: [1] LAST_COMMAND_DONE // @@ -703,20 +703,20 @@ // has finished. (IEEE 802.15.4 mode: The last background level radio operation // command in a chain of commands has finished.) Write zero to clear flag. // Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE 0x00000002 -#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_BITN 1 -#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M 0x00000002 -#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_S 1 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_S 1 // Field: [0] COMMAND_DONE // // Interrupt flag 0. A radio operation has finished. (IEEE 802.15.4 mode: A // background level radio operation command has finished.) Write zero to clear // flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_COMMAND_DONE 0x00000001 -#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_BITN 0 -#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_M 0x00000001 -#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_S 0 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_S 0 //***************************************************************************** // @@ -726,258 +726,258 @@ // Field: [31] INTERNAL_ERROR // // Interrupt enable for RFCPEIFG.INTERNAL_ERROR. -#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR 0x80000000 -#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_BITN 31 -#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_M 0x80000000 -#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_S 31 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_S 31 // Field: [30] BOOT_DONE // // Interrupt enable for RFCPEIFG.BOOT_DONE. -#define RFC_DBELL_RFCPEIEN_BOOT_DONE 0x40000000 -#define RFC_DBELL_RFCPEIEN_BOOT_DONE_BITN 30 -#define RFC_DBELL_RFCPEIEN_BOOT_DONE_M 0x40000000 -#define RFC_DBELL_RFCPEIEN_BOOT_DONE_S 30 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_S 30 // Field: [29] MODULES_UNLOCKED // // Interrupt enable for RFCPEIFG.MODULES_UNLOCKED. -#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED 0x20000000 -#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_BITN 29 -#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_M 0x20000000 -#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_S 29 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_S 29 // Field: [28] SYNTH_NO_LOCK // // Interrupt enable for RFCPEIFG.SYNTH_NO_LOCK. -#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK 0x10000000 -#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_BITN 28 -#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_M 0x10000000 -#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_S 28 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_S 28 // Field: [27] IRQ27 // // Interrupt enable for RFCPEIFG.IRQ27. -#define RFC_DBELL_RFCPEIEN_IRQ27 0x08000000 -#define RFC_DBELL_RFCPEIEN_IRQ27_BITN 27 -#define RFC_DBELL_RFCPEIEN_IRQ27_M 0x08000000 -#define RFC_DBELL_RFCPEIEN_IRQ27_S 27 +#define RFC_DBELL_RFCPEIEN_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEIEN_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEIEN_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEIEN_IRQ27_S 27 // Field: [26] RX_ABORTED // // Interrupt enable for RFCPEIFG.RX_ABORTED. -#define RFC_DBELL_RFCPEIEN_RX_ABORTED 0x04000000 -#define RFC_DBELL_RFCPEIEN_RX_ABORTED_BITN 26 -#define RFC_DBELL_RFCPEIEN_RX_ABORTED_M 0x04000000 -#define RFC_DBELL_RFCPEIEN_RX_ABORTED_S 26 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_S 26 // Field: [25] RX_N_DATA_WRITTEN // // Interrupt enable for RFCPEIFG.RX_N_DATA_WRITTEN. -#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN 0x02000000 -#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_BITN 25 -#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_M 0x02000000 -#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_S 25 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_S 25 // Field: [24] RX_DATA_WRITTEN // // Interrupt enable for RFCPEIFG.RX_DATA_WRITTEN. -#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN 0x01000000 -#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_BITN 24 -#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_M 0x01000000 -#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_S 24 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_S 24 // Field: [23] RX_ENTRY_DONE // // Interrupt enable for RFCPEIFG.RX_ENTRY_DONE. -#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE 0x00800000 -#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_BITN 23 -#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_M 0x00800000 -#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_S 23 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_S 23 // Field: [22] RX_BUF_FULL // // Interrupt enable for RFCPEIFG.RX_BUF_FULL. -#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL 0x00400000 -#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_BITN 22 -#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_M 0x00400000 -#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_S 22 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_S 22 // Field: [21] RX_CTRL_ACK // // Interrupt enable for RFCPEIFG.RX_CTRL_ACK. -#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK 0x00200000 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_BITN 21 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_M 0x00200000 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_S 21 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_S 21 // Field: [20] RX_CTRL // // Interrupt enable for RFCPEIFG.RX_CTRL. -#define RFC_DBELL_RFCPEIEN_RX_CTRL 0x00100000 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_BITN 20 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_M 0x00100000 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_S 20 +#define RFC_DBELL_RFCPEIEN_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_S 20 // Field: [19] RX_EMPTY // // Interrupt enable for RFCPEIFG.RX_EMPTY. -#define RFC_DBELL_RFCPEIEN_RX_EMPTY 0x00080000 -#define RFC_DBELL_RFCPEIEN_RX_EMPTY_BITN 19 -#define RFC_DBELL_RFCPEIEN_RX_EMPTY_M 0x00080000 -#define RFC_DBELL_RFCPEIEN_RX_EMPTY_S 19 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_S 19 // Field: [18] RX_IGNORED // // Interrupt enable for RFCPEIFG.RX_IGNORED. -#define RFC_DBELL_RFCPEIEN_RX_IGNORED 0x00040000 -#define RFC_DBELL_RFCPEIEN_RX_IGNORED_BITN 18 -#define RFC_DBELL_RFCPEIEN_RX_IGNORED_M 0x00040000 -#define RFC_DBELL_RFCPEIEN_RX_IGNORED_S 18 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_S 18 // Field: [17] RX_NOK // // Interrupt enable for RFCPEIFG.RX_NOK. -#define RFC_DBELL_RFCPEIEN_RX_NOK 0x00020000 -#define RFC_DBELL_RFCPEIEN_RX_NOK_BITN 17 -#define RFC_DBELL_RFCPEIEN_RX_NOK_M 0x00020000 -#define RFC_DBELL_RFCPEIEN_RX_NOK_S 17 +#define RFC_DBELL_RFCPEIEN_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEIEN_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEIEN_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEIEN_RX_NOK_S 17 // Field: [16] RX_OK // // Interrupt enable for RFCPEIFG.RX_OK. -#define RFC_DBELL_RFCPEIEN_RX_OK 0x00010000 -#define RFC_DBELL_RFCPEIEN_RX_OK_BITN 16 -#define RFC_DBELL_RFCPEIEN_RX_OK_M 0x00010000 -#define RFC_DBELL_RFCPEIEN_RX_OK_S 16 +#define RFC_DBELL_RFCPEIEN_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEIEN_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEIEN_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEIEN_RX_OK_S 16 // Field: [15] IRQ15 // // Interrupt enable for RFCPEIFG.IRQ15. -#define RFC_DBELL_RFCPEIEN_IRQ15 0x00008000 -#define RFC_DBELL_RFCPEIEN_IRQ15_BITN 15 -#define RFC_DBELL_RFCPEIEN_IRQ15_M 0x00008000 -#define RFC_DBELL_RFCPEIEN_IRQ15_S 15 +#define RFC_DBELL_RFCPEIEN_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEIEN_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEIEN_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEIEN_IRQ15_S 15 // Field: [14] IRQ14 // // Interrupt enable for RFCPEIFG.IRQ14. -#define RFC_DBELL_RFCPEIEN_IRQ14 0x00004000 -#define RFC_DBELL_RFCPEIEN_IRQ14_BITN 14 -#define RFC_DBELL_RFCPEIEN_IRQ14_M 0x00004000 -#define RFC_DBELL_RFCPEIEN_IRQ14_S 14 +#define RFC_DBELL_RFCPEIEN_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEIEN_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEIEN_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEIEN_IRQ14_S 14 // Field: [13] IRQ13 // // Interrupt enable for RFCPEIFG.IRQ13. -#define RFC_DBELL_RFCPEIEN_IRQ13 0x00002000 -#define RFC_DBELL_RFCPEIEN_IRQ13_BITN 13 -#define RFC_DBELL_RFCPEIEN_IRQ13_M 0x00002000 -#define RFC_DBELL_RFCPEIEN_IRQ13_S 13 +#define RFC_DBELL_RFCPEIEN_IRQ13 0x00002000 +#define RFC_DBELL_RFCPEIEN_IRQ13_BITN 13 +#define RFC_DBELL_RFCPEIEN_IRQ13_M 0x00002000 +#define RFC_DBELL_RFCPEIEN_IRQ13_S 13 // Field: [12] IRQ12 // // Interrupt enable for RFCPEIFG.IRQ12. -#define RFC_DBELL_RFCPEIEN_IRQ12 0x00001000 -#define RFC_DBELL_RFCPEIEN_IRQ12_BITN 12 -#define RFC_DBELL_RFCPEIEN_IRQ12_M 0x00001000 -#define RFC_DBELL_RFCPEIEN_IRQ12_S 12 +#define RFC_DBELL_RFCPEIEN_IRQ12 0x00001000 +#define RFC_DBELL_RFCPEIEN_IRQ12_BITN 12 +#define RFC_DBELL_RFCPEIEN_IRQ12_M 0x00001000 +#define RFC_DBELL_RFCPEIEN_IRQ12_S 12 // Field: [11] TX_BUFFER_CHANGED // // Interrupt enable for RFCPEIFG.TX_BUFFER_CHANGED. -#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED 0x00000800 -#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_BITN 11 -#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_M 0x00000800 -#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_S 11 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_S 11 // Field: [10] TX_ENTRY_DONE // // Interrupt enable for RFCPEIFG.TX_ENTRY_DONE. -#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE 0x00000400 -#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_BITN 10 -#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_M 0x00000400 -#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_S 10 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_S 10 // Field: [9] TX_RETRANS // // Interrupt enable for RFCPEIFG.TX_RETRANS. -#define RFC_DBELL_RFCPEIEN_TX_RETRANS 0x00000200 -#define RFC_DBELL_RFCPEIEN_TX_RETRANS_BITN 9 -#define RFC_DBELL_RFCPEIEN_TX_RETRANS_M 0x00000200 -#define RFC_DBELL_RFCPEIEN_TX_RETRANS_S 9 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_S 9 // Field: [8] TX_CTRL_ACK_ACK // // Interrupt enable for RFCPEIFG.TX_CTRL_ACK_ACK. -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK 0x00000100 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_BITN 8 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_M 0x00000100 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_S 8 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_S 8 // Field: [7] TX_CTRL_ACK // // Interrupt enable for RFCPEIFG.TX_CTRL_ACK. -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK 0x00000080 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_BITN 7 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_M 0x00000080 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_S 7 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_S 7 // Field: [6] TX_CTRL // // Interrupt enable for RFCPEIFG.TX_CTRL. -#define RFC_DBELL_RFCPEIEN_TX_CTRL 0x00000040 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_BITN 6 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_M 0x00000040 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_S 6 +#define RFC_DBELL_RFCPEIEN_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_S 6 // Field: [5] TX_ACK // // Interrupt enable for RFCPEIFG.TX_ACK. -#define RFC_DBELL_RFCPEIEN_TX_ACK 0x00000020 -#define RFC_DBELL_RFCPEIEN_TX_ACK_BITN 5 -#define RFC_DBELL_RFCPEIEN_TX_ACK_M 0x00000020 -#define RFC_DBELL_RFCPEIEN_TX_ACK_S 5 +#define RFC_DBELL_RFCPEIEN_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEIEN_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEIEN_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEIEN_TX_ACK_S 5 // Field: [4] TX_DONE // // Interrupt enable for RFCPEIFG.TX_DONE. -#define RFC_DBELL_RFCPEIEN_TX_DONE 0x00000010 -#define RFC_DBELL_RFCPEIEN_TX_DONE_BITN 4 -#define RFC_DBELL_RFCPEIEN_TX_DONE_M 0x00000010 -#define RFC_DBELL_RFCPEIEN_TX_DONE_S 4 +#define RFC_DBELL_RFCPEIEN_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEIEN_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEIEN_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEIEN_TX_DONE_S 4 // Field: [3] LAST_FG_COMMAND_DONE // // Interrupt enable for RFCPEIFG.LAST_FG_COMMAND_DONE. -#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE 0x00000008 -#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_BITN 3 -#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_M 0x00000008 -#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_S 3 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_S 3 // Field: [2] FG_COMMAND_DONE // // Interrupt enable for RFCPEIFG.FG_COMMAND_DONE. -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE 0x00000004 -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_BITN 2 -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_M 0x00000004 -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_S 2 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_S 2 // Field: [1] LAST_COMMAND_DONE // // Interrupt enable for RFCPEIFG.LAST_COMMAND_DONE. -#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE 0x00000002 -#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_BITN 1 -#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_M 0x00000002 -#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_S 1 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_S 1 // Field: [0] COMMAND_DONE // // Interrupt enable for RFCPEIFG.COMMAND_DONE. -#define RFC_DBELL_RFCPEIEN_COMMAND_DONE 0x00000001 -#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_BITN 0 -#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_M 0x00000001 -#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_S 0 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_S 0 //***************************************************************************** // @@ -993,12 +993,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR 0x80000000 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_BITN 31 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_M 0x80000000 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_S 31 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE1 0x80000000 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_S 31 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE1 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE0 0x00000000 // Field: [30] BOOT_DONE // @@ -1009,12 +1009,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_BOOT_DONE 0x40000000 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_BITN 30 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_M 0x40000000 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_S 30 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE1 0x40000000 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_S 30 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE1 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE0 0x00000000 // Field: [29] MODULES_UNLOCKED // @@ -1025,12 +1025,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED 0x20000000 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_BITN 29 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_M 0x20000000 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_S 29 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE1 0x20000000 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_S 29 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE1 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE0 0x00000000 // Field: [28] SYNTH_NO_LOCK // @@ -1041,12 +1041,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK 0x10000000 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_BITN 28 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_M 0x10000000 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_S 28 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE1 0x10000000 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_S 28 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE1 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE0 0x00000000 // Field: [27] IRQ27 // @@ -1056,12 +1056,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_IRQ27 0x08000000 -#define RFC_DBELL_RFCPEISL_IRQ27_BITN 27 -#define RFC_DBELL_RFCPEISL_IRQ27_M 0x08000000 -#define RFC_DBELL_RFCPEISL_IRQ27_S 27 -#define RFC_DBELL_RFCPEISL_IRQ27_CPE1 0x08000000 -#define RFC_DBELL_RFCPEISL_IRQ27_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEISL_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_S 27 +#define RFC_DBELL_RFCPEISL_IRQ27_CPE1 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_CPE0 0x00000000 // Field: [26] RX_ABORTED // @@ -1072,12 +1072,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_ABORTED 0x04000000 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_BITN 26 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_M 0x04000000 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_S 26 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE1 0x04000000 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_S 26 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE1 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE0 0x00000000 // Field: [25] RX_N_DATA_WRITTEN // @@ -1088,12 +1088,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN 0x02000000 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_BITN 25 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_M 0x02000000 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_S 25 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE1 0x02000000 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_S 25 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE1 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE0 0x00000000 // Field: [24] RX_DATA_WRITTEN // @@ -1104,12 +1104,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN 0x01000000 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_BITN 24 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_M 0x01000000 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_S 24 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE1 0x01000000 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_S 24 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE1 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE0 0x00000000 // Field: [23] RX_ENTRY_DONE // @@ -1120,12 +1120,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE 0x00800000 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_BITN 23 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_M 0x00800000 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_S 23 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE1 0x00800000 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_S 23 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE1 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE0 0x00000000 // Field: [22] RX_BUF_FULL // @@ -1136,12 +1136,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL 0x00400000 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_BITN 22 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_M 0x00400000 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_S 22 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE1 0x00400000 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_S 22 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE1 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE0 0x00000000 // Field: [21] RX_CTRL_ACK // @@ -1152,12 +1152,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK 0x00200000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_BITN 21 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_M 0x00200000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_S 21 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE1 0x00200000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_S 21 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE1 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE0 0x00000000 // Field: [20] RX_CTRL // @@ -1167,12 +1167,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_CTRL 0x00100000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_BITN 20 -#define RFC_DBELL_RFCPEISL_RX_CTRL_M 0x00100000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_S 20 -#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE1 0x00100000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEISL_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_S 20 +#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE1 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE0 0x00000000 // Field: [19] RX_EMPTY // @@ -1183,12 +1183,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_EMPTY 0x00080000 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_BITN 19 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_M 0x00080000 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_S 19 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE1 0x00080000 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_S 19 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE1 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE0 0x00000000 // Field: [18] RX_IGNORED // @@ -1199,12 +1199,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_IGNORED 0x00040000 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_BITN 18 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_M 0x00040000 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_S 18 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE1 0x00040000 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_S 18 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE1 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE0 0x00000000 // Field: [17] RX_NOK // @@ -1214,12 +1214,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_NOK 0x00020000 -#define RFC_DBELL_RFCPEISL_RX_NOK_BITN 17 -#define RFC_DBELL_RFCPEISL_RX_NOK_M 0x00020000 -#define RFC_DBELL_RFCPEISL_RX_NOK_S 17 -#define RFC_DBELL_RFCPEISL_RX_NOK_CPE1 0x00020000 -#define RFC_DBELL_RFCPEISL_RX_NOK_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEISL_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_S 17 +#define RFC_DBELL_RFCPEISL_RX_NOK_CPE1 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_CPE0 0x00000000 // Field: [16] RX_OK // @@ -1229,12 +1229,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_OK 0x00010000 -#define RFC_DBELL_RFCPEISL_RX_OK_BITN 16 -#define RFC_DBELL_RFCPEISL_RX_OK_M 0x00010000 -#define RFC_DBELL_RFCPEISL_RX_OK_S 16 -#define RFC_DBELL_RFCPEISL_RX_OK_CPE1 0x00010000 -#define RFC_DBELL_RFCPEISL_RX_OK_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEISL_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_S 16 +#define RFC_DBELL_RFCPEISL_RX_OK_CPE1 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_CPE0 0x00000000 // Field: [15] IRQ15 // @@ -1244,12 +1244,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_IRQ15 0x00008000 -#define RFC_DBELL_RFCPEISL_IRQ15_BITN 15 -#define RFC_DBELL_RFCPEISL_IRQ15_M 0x00008000 -#define RFC_DBELL_RFCPEISL_IRQ15_S 15 -#define RFC_DBELL_RFCPEISL_IRQ15_CPE1 0x00008000 -#define RFC_DBELL_RFCPEISL_IRQ15_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEISL_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_S 15 +#define RFC_DBELL_RFCPEISL_IRQ15_CPE1 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_CPE0 0x00000000 // Field: [14] IRQ14 // @@ -1259,12 +1259,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_IRQ14 0x00004000 -#define RFC_DBELL_RFCPEISL_IRQ14_BITN 14 -#define RFC_DBELL_RFCPEISL_IRQ14_M 0x00004000 -#define RFC_DBELL_RFCPEISL_IRQ14_S 14 -#define RFC_DBELL_RFCPEISL_IRQ14_CPE1 0x00004000 -#define RFC_DBELL_RFCPEISL_IRQ14_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEISL_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_S 14 +#define RFC_DBELL_RFCPEISL_IRQ14_CPE1 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_CPE0 0x00000000 // Field: [13] IRQ13 // @@ -1274,12 +1274,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_IRQ13 0x00002000 -#define RFC_DBELL_RFCPEISL_IRQ13_BITN 13 -#define RFC_DBELL_RFCPEISL_IRQ13_M 0x00002000 -#define RFC_DBELL_RFCPEISL_IRQ13_S 13 -#define RFC_DBELL_RFCPEISL_IRQ13_CPE1 0x00002000 -#define RFC_DBELL_RFCPEISL_IRQ13_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_IRQ13 0x00002000 +#define RFC_DBELL_RFCPEISL_IRQ13_BITN 13 +#define RFC_DBELL_RFCPEISL_IRQ13_M 0x00002000 +#define RFC_DBELL_RFCPEISL_IRQ13_S 13 +#define RFC_DBELL_RFCPEISL_IRQ13_CPE1 0x00002000 +#define RFC_DBELL_RFCPEISL_IRQ13_CPE0 0x00000000 // Field: [12] IRQ12 // @@ -1289,12 +1289,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_IRQ12 0x00001000 -#define RFC_DBELL_RFCPEISL_IRQ12_BITN 12 -#define RFC_DBELL_RFCPEISL_IRQ12_M 0x00001000 -#define RFC_DBELL_RFCPEISL_IRQ12_S 12 -#define RFC_DBELL_RFCPEISL_IRQ12_CPE1 0x00001000 -#define RFC_DBELL_RFCPEISL_IRQ12_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_IRQ12 0x00001000 +#define RFC_DBELL_RFCPEISL_IRQ12_BITN 12 +#define RFC_DBELL_RFCPEISL_IRQ12_M 0x00001000 +#define RFC_DBELL_RFCPEISL_IRQ12_S 12 +#define RFC_DBELL_RFCPEISL_IRQ12_CPE1 0x00001000 +#define RFC_DBELL_RFCPEISL_IRQ12_CPE0 0x00000000 // Field: [11] TX_BUFFER_CHANGED // @@ -1305,12 +1305,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED 0x00000800 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_BITN 11 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_M 0x00000800 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_S 11 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE1 0x00000800 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_S 11 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE1 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE0 0x00000000 // Field: [10] TX_ENTRY_DONE // @@ -1321,12 +1321,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE 0x00000400 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_BITN 10 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_M 0x00000400 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_S 10 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE1 0x00000400 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_S 10 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE1 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE0 0x00000000 // Field: [9] TX_RETRANS // @@ -1337,12 +1337,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_RETRANS 0x00000200 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_BITN 9 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_M 0x00000200 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_S 9 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE1 0x00000200 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_S 9 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE1 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE0 0x00000000 // Field: [8] TX_CTRL_ACK_ACK // @@ -1353,12 +1353,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK 0x00000100 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_BITN 8 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_M 0x00000100 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_S 8 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE1 0x00000100 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_S 8 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE1 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE0 0x00000000 // Field: [7] TX_CTRL_ACK // @@ -1369,12 +1369,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK 0x00000080 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_BITN 7 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_M 0x00000080 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_S 7 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE1 0x00000080 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_S 7 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE1 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE0 0x00000000 // Field: [6] TX_CTRL // @@ -1384,12 +1384,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_CTRL 0x00000040 -#define RFC_DBELL_RFCPEISL_TX_CTRL_BITN 6 -#define RFC_DBELL_RFCPEISL_TX_CTRL_M 0x00000040 -#define RFC_DBELL_RFCPEISL_TX_CTRL_S 6 -#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE1 0x00000040 -#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEISL_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_S 6 +#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE1 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE0 0x00000000 // Field: [5] TX_ACK // @@ -1399,12 +1399,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_ACK 0x00000020 -#define RFC_DBELL_RFCPEISL_TX_ACK_BITN 5 -#define RFC_DBELL_RFCPEISL_TX_ACK_M 0x00000020 -#define RFC_DBELL_RFCPEISL_TX_ACK_S 5 -#define RFC_DBELL_RFCPEISL_TX_ACK_CPE1 0x00000020 -#define RFC_DBELL_RFCPEISL_TX_ACK_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEISL_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_S 5 +#define RFC_DBELL_RFCPEISL_TX_ACK_CPE1 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_CPE0 0x00000000 // Field: [4] TX_DONE // @@ -1414,12 +1414,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_DONE 0x00000010 -#define RFC_DBELL_RFCPEISL_TX_DONE_BITN 4 -#define RFC_DBELL_RFCPEISL_TX_DONE_M 0x00000010 -#define RFC_DBELL_RFCPEISL_TX_DONE_S 4 -#define RFC_DBELL_RFCPEISL_TX_DONE_CPE1 0x00000010 -#define RFC_DBELL_RFCPEISL_TX_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEISL_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_S 4 +#define RFC_DBELL_RFCPEISL_TX_DONE_CPE1 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_CPE0 0x00000000 // Field: [3] LAST_FG_COMMAND_DONE // @@ -1430,12 +1430,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE 0x00000008 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_BITN 3 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_M 0x00000008 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_S 3 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE1 0x00000008 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_S 3 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE1 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE0 0x00000000 // Field: [2] FG_COMMAND_DONE // @@ -1446,12 +1446,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE 0x00000004 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_BITN 2 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_M 0x00000004 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_S 2 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE1 0x00000004 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_S 2 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE1 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE0 0x00000000 // Field: [1] LAST_COMMAND_DONE // @@ -1462,12 +1462,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE 0x00000002 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_BITN 1 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_M 0x00000002 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_S 1 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE1 0x00000002 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_S 1 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE1 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE0 0x00000000 // Field: [0] COMMAND_DONE // @@ -1478,12 +1478,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_COMMAND_DONE 0x00000001 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_BITN 0 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_M 0x00000001 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_S 0 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE1 0x00000001 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_S 0 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE1 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE0 0x00000000 //***************************************************************************** // @@ -1493,10 +1493,10 @@ // Field: [0] ACKFLAG // // Interrupt flag for Command ACK -#define RFC_DBELL_RFACKIFG_ACKFLAG 0x00000001 -#define RFC_DBELL_RFACKIFG_ACKFLAG_BITN 0 -#define RFC_DBELL_RFACKIFG_ACKFLAG_M 0x00000001 -#define RFC_DBELL_RFACKIFG_ACKFLAG_S 0 +#define RFC_DBELL_RFACKIFG_ACKFLAG 0x00000001 +#define RFC_DBELL_RFACKIFG_ACKFLAG_BITN 0 +#define RFC_DBELL_RFACKIFG_ACKFLAG_M 0x00000001 +#define RFC_DBELL_RFACKIFG_ACKFLAG_S 0 //***************************************************************************** // @@ -1524,25 +1524,25 @@ // CPEGPO2 CPE GPO line 2 // CPEGPO1 CPE GPO line 1 // CPEGPO0 CPE GPO line 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_W 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_M 0x0000F000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_S 12 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO3 0x0000F000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO2 0x0000E000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO1 0x0000D000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO0 0x0000C000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO3 0x0000B000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO2 0x0000A000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO1 0x00009000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO0 0x00008000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO3 0x00007000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO2 0x00006000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO1 0x00005000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO0 0x00004000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO3 0x00003000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO2 0x00002000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO1 0x00001000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO0 0x00000000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_M 0x0000F000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_S 12 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO3 0x0000F000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO2 0x0000E000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO1 0x0000D000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO0 0x0000C000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO3 0x0000B000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO2 0x0000A000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO1 0x00009000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO0 0x00008000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO3 0x00007000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO2 0x00006000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO1 0x00005000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO0 0x00004000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO3 0x00003000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO2 0x00002000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO1 0x00001000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO0 0x00000000 // Field: [11:8] GPOCTL2 // @@ -1565,25 +1565,25 @@ // CPEGPO2 CPE GPO line 2 // CPEGPO1 CPE GPO line 1 // CPEGPO0 CPE GPO line 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_W 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_M 0x00000F00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_S 8 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO3 0x00000F00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO2 0x00000E00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO1 0x00000D00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO0 0x00000C00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO3 0x00000B00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO2 0x00000A00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO1 0x00000900 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO0 0x00000800 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO3 0x00000700 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO2 0x00000600 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO1 0x00000500 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO0 0x00000400 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO3 0x00000300 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO2 0x00000200 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO1 0x00000100 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO0 0x00000000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_M 0x00000F00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_S 8 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO3 0x00000F00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO2 0x00000E00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO1 0x00000D00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO0 0x00000C00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO3 0x00000B00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO2 0x00000A00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO1 0x00000900 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO0 0x00000800 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO3 0x00000700 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO2 0x00000600 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO1 0x00000500 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO0 0x00000400 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO3 0x00000300 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO2 0x00000200 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO1 0x00000100 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO0 0x00000000 // Field: [7:4] GPOCTL1 // @@ -1606,25 +1606,25 @@ // CPEGPO2 CPE GPO line 2 // CPEGPO1 CPE GPO line 1 // CPEGPO0 CPE GPO line 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_W 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_M 0x000000F0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_S 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO3 0x000000F0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO2 0x000000E0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO1 0x000000D0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO0 0x000000C0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO3 0x000000B0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO2 0x000000A0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO1 0x00000090 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO0 0x00000080 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO3 0x00000070 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO2 0x00000060 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO1 0x00000050 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO0 0x00000040 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO3 0x00000030 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO2 0x00000020 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO1 0x00000010 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO0 0x00000000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_M 0x000000F0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_S 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO3 0x000000F0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO2 0x000000E0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO1 0x000000D0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO0 0x000000C0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO3 0x000000B0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO2 0x000000A0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO1 0x00000090 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO0 0x00000080 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO3 0x00000070 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO2 0x00000060 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO1 0x00000050 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO0 0x00000040 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO3 0x00000030 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO2 0x00000020 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO1 0x00000010 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO0 0x00000000 // Field: [3:0] GPOCTL0 // @@ -1647,25 +1647,24 @@ // CPEGPO2 CPE GPO line 2 // CPEGPO1 CPE GPO line 1 // CPEGPO0 CPE GPO line 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_W 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_M 0x0000000F -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_S 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO3 0x0000000F -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO2 0x0000000E -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO1 0x0000000D -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO0 0x0000000C -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO3 0x0000000B -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO2 0x0000000A -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO1 0x00000009 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO0 0x00000008 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO3 0x00000007 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO2 0x00000006 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO1 0x00000005 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO0 0x00000004 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO3 0x00000003 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO2 0x00000002 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO1 0x00000001 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO0 0x00000000 - +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_M 0x0000000F +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_S 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO3 0x0000000F +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO2 0x0000000E +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO1 0x0000000D +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO0 0x0000000C +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO3 0x0000000B +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO2 0x0000000A +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO1 0x00000009 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO0 0x00000008 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO3 0x00000007 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO2 0x00000006 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO1 0x00000005 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO0 0x00000004 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO3 0x00000003 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO2 0x00000002 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO1 0x00000001 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO0 0x00000000 #endif // __RFC_DBELL__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_rfc_pwr.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_rfc_pwr.h index ad91fb3..1856b2e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_rfc_pwr.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_rfc_pwr.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_rfc_pwr_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_rfc_pwr_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_RFC_PWR_H__ #define __HW_RFC_PWR_H__ @@ -44,7 +44,7 @@ // //***************************************************************************** // RF Core Power Management and Clock Enable -#define RFC_PWR_O_PWMCLKEN 0x00000000 +#define RFC_PWR_O_PWMCLKEN 0x00000000 //***************************************************************************** // @@ -54,87 +54,87 @@ // Field: [10] RFCTRC // // Enable clock to the RF Core Tracer (RFCTRC) module. -#define RFC_PWR_PWMCLKEN_RFCTRC 0x00000400 -#define RFC_PWR_PWMCLKEN_RFCTRC_BITN 10 -#define RFC_PWR_PWMCLKEN_RFCTRC_M 0x00000400 -#define RFC_PWR_PWMCLKEN_RFCTRC_S 10 +#define RFC_PWR_PWMCLKEN_RFCTRC 0x00000400 +#define RFC_PWR_PWMCLKEN_RFCTRC_BITN 10 +#define RFC_PWR_PWMCLKEN_RFCTRC_M 0x00000400 +#define RFC_PWR_PWMCLKEN_RFCTRC_S 10 // Field: [9] FSCA // // Enable clock to the Frequency Synthesizer Calibration Accelerator (FSCA) // module. -#define RFC_PWR_PWMCLKEN_FSCA 0x00000200 -#define RFC_PWR_PWMCLKEN_FSCA_BITN 9 -#define RFC_PWR_PWMCLKEN_FSCA_M 0x00000200 -#define RFC_PWR_PWMCLKEN_FSCA_S 9 +#define RFC_PWR_PWMCLKEN_FSCA 0x00000200 +#define RFC_PWR_PWMCLKEN_FSCA_BITN 9 +#define RFC_PWR_PWMCLKEN_FSCA_M 0x00000200 +#define RFC_PWR_PWMCLKEN_FSCA_S 9 // Field: [8] PHA // // Enable clock to the Packet Handling Accelerator (PHA) module. -#define RFC_PWR_PWMCLKEN_PHA 0x00000100 -#define RFC_PWR_PWMCLKEN_PHA_BITN 8 -#define RFC_PWR_PWMCLKEN_PHA_M 0x00000100 -#define RFC_PWR_PWMCLKEN_PHA_S 8 +#define RFC_PWR_PWMCLKEN_PHA 0x00000100 +#define RFC_PWR_PWMCLKEN_PHA_BITN 8 +#define RFC_PWR_PWMCLKEN_PHA_M 0x00000100 +#define RFC_PWR_PWMCLKEN_PHA_S 8 // Field: [7] RAT // // Enable clock to the Radio Timer (RAT) module. -#define RFC_PWR_PWMCLKEN_RAT 0x00000080 -#define RFC_PWR_PWMCLKEN_RAT_BITN 7 -#define RFC_PWR_PWMCLKEN_RAT_M 0x00000080 -#define RFC_PWR_PWMCLKEN_RAT_S 7 +#define RFC_PWR_PWMCLKEN_RAT 0x00000080 +#define RFC_PWR_PWMCLKEN_RAT_BITN 7 +#define RFC_PWR_PWMCLKEN_RAT_M 0x00000080 +#define RFC_PWR_PWMCLKEN_RAT_S 7 // Field: [6] RFERAM // // Enable clock to the RF Engine RAM module. -#define RFC_PWR_PWMCLKEN_RFERAM 0x00000040 -#define RFC_PWR_PWMCLKEN_RFERAM_BITN 6 -#define RFC_PWR_PWMCLKEN_RFERAM_M 0x00000040 -#define RFC_PWR_PWMCLKEN_RFERAM_S 6 +#define RFC_PWR_PWMCLKEN_RFERAM 0x00000040 +#define RFC_PWR_PWMCLKEN_RFERAM_BITN 6 +#define RFC_PWR_PWMCLKEN_RFERAM_M 0x00000040 +#define RFC_PWR_PWMCLKEN_RFERAM_S 6 // Field: [5] RFE // // Enable clock to the RF Engine (RFE) module. -#define RFC_PWR_PWMCLKEN_RFE 0x00000020 -#define RFC_PWR_PWMCLKEN_RFE_BITN 5 -#define RFC_PWR_PWMCLKEN_RFE_M 0x00000020 -#define RFC_PWR_PWMCLKEN_RFE_S 5 +#define RFC_PWR_PWMCLKEN_RFE 0x00000020 +#define RFC_PWR_PWMCLKEN_RFE_BITN 5 +#define RFC_PWR_PWMCLKEN_RFE_M 0x00000020 +#define RFC_PWR_PWMCLKEN_RFE_S 5 // Field: [4] MDMRAM // // Enable clock to the Modem RAM module. -#define RFC_PWR_PWMCLKEN_MDMRAM 0x00000010 -#define RFC_PWR_PWMCLKEN_MDMRAM_BITN 4 -#define RFC_PWR_PWMCLKEN_MDMRAM_M 0x00000010 -#define RFC_PWR_PWMCLKEN_MDMRAM_S 4 +#define RFC_PWR_PWMCLKEN_MDMRAM 0x00000010 +#define RFC_PWR_PWMCLKEN_MDMRAM_BITN 4 +#define RFC_PWR_PWMCLKEN_MDMRAM_M 0x00000010 +#define RFC_PWR_PWMCLKEN_MDMRAM_S 4 // Field: [3] MDM // // Enable clock to the Modem (MDM) module. -#define RFC_PWR_PWMCLKEN_MDM 0x00000008 -#define RFC_PWR_PWMCLKEN_MDM_BITN 3 -#define RFC_PWR_PWMCLKEN_MDM_M 0x00000008 -#define RFC_PWR_PWMCLKEN_MDM_S 3 +#define RFC_PWR_PWMCLKEN_MDM 0x00000008 +#define RFC_PWR_PWMCLKEN_MDM_BITN 3 +#define RFC_PWR_PWMCLKEN_MDM_M 0x00000008 +#define RFC_PWR_PWMCLKEN_MDM_S 3 // Field: [2] CPERAM // // Enable clock to the Command and Packet Engine (CPE) RAM module. As part of // RF Core initialization, set this bit together with CPE bit to enable CPE to // boot. -#define RFC_PWR_PWMCLKEN_CPERAM 0x00000004 -#define RFC_PWR_PWMCLKEN_CPERAM_BITN 2 -#define RFC_PWR_PWMCLKEN_CPERAM_M 0x00000004 -#define RFC_PWR_PWMCLKEN_CPERAM_S 2 +#define RFC_PWR_PWMCLKEN_CPERAM 0x00000004 +#define RFC_PWR_PWMCLKEN_CPERAM_BITN 2 +#define RFC_PWR_PWMCLKEN_CPERAM_M 0x00000004 +#define RFC_PWR_PWMCLKEN_CPERAM_S 2 // Field: [1] CPE // // Enable processor clock (hclk) to the Command and Packet Engine (CPE). As // part of RF Core initialization, set this bit together with CPERAM bit to // enable CPE to boot. -#define RFC_PWR_PWMCLKEN_CPE 0x00000002 -#define RFC_PWR_PWMCLKEN_CPE_BITN 1 -#define RFC_PWR_PWMCLKEN_CPE_M 0x00000002 -#define RFC_PWR_PWMCLKEN_CPE_S 1 +#define RFC_PWR_PWMCLKEN_CPE 0x00000002 +#define RFC_PWR_PWMCLKEN_CPE_BITN 1 +#define RFC_PWR_PWMCLKEN_CPE_M 0x00000002 +#define RFC_PWR_PWMCLKEN_CPE_S 1 // Field: [0] RFC // @@ -144,10 +144,9 @@ // remove possibility of locking yourself out from the RF Core, this bit can // not be cleared. If you need to disable all clocks to the RF Core, see the // PRCM:RFCCLKG.CLK_EN register. -#define RFC_PWR_PWMCLKEN_RFC 0x00000001 -#define RFC_PWR_PWMCLKEN_RFC_BITN 0 -#define RFC_PWR_PWMCLKEN_RFC_M 0x00000001 -#define RFC_PWR_PWMCLKEN_RFC_S 0 - +#define RFC_PWR_PWMCLKEN_RFC 0x00000001 +#define RFC_PWR_PWMCLKEN_RFC_BITN 0 +#define RFC_PWR_PWMCLKEN_RFC_M 0x00000001 +#define RFC_PWR_PWMCLKEN_RFC_S 0 #endif // __RFC_PWR__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_rfc_rat.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_rfc_rat.h index 83f131c..35e8f17 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_rfc_rat.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_rfc_rat.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_rfc_rat_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_rfc_rat_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_RFC_RAT_H__ #define __HW_RFC_RAT_H__ @@ -44,31 +44,31 @@ // //***************************************************************************** // Radio Timer Counter Value -#define RFC_RAT_O_RATCNT 0x00000004 +#define RFC_RAT_O_RATCNT 0x00000004 // Timer Channel 0 Capture/Compare Register -#define RFC_RAT_O_RATCH0VAL 0x00000080 +#define RFC_RAT_O_RATCH0VAL 0x00000080 // Timer Channel 1 Capture/Compare Register -#define RFC_RAT_O_RATCH1VAL 0x00000084 +#define RFC_RAT_O_RATCH1VAL 0x00000084 // Timer Channel 2 Capture/Compare Register -#define RFC_RAT_O_RATCH2VAL 0x00000088 +#define RFC_RAT_O_RATCH2VAL 0x00000088 // Timer Channel 3 Capture/Compare Register -#define RFC_RAT_O_RATCH3VAL 0x0000008C +#define RFC_RAT_O_RATCH3VAL 0x0000008C // Timer Channel 4 Capture/Compare Register -#define RFC_RAT_O_RATCH4VAL 0x00000090 +#define RFC_RAT_O_RATCH4VAL 0x00000090 // Timer Channel 5 Capture/Compare Register -#define RFC_RAT_O_RATCH5VAL 0x00000094 +#define RFC_RAT_O_RATCH5VAL 0x00000094 // Timer Channel 6 Capture/Compare Register -#define RFC_RAT_O_RATCH6VAL 0x00000098 +#define RFC_RAT_O_RATCH6VAL 0x00000098 // Timer Channel 7 Capture/Compare Register -#define RFC_RAT_O_RATCH7VAL 0x0000009C +#define RFC_RAT_O_RATCH7VAL 0x0000009C //***************************************************************************** // @@ -78,9 +78,9 @@ // Field: [31:0] CNT // // Counter value. This is not writable while radio timer counter is enabled. -#define RFC_RAT_RATCNT_CNT_W 32 -#define RFC_RAT_RATCNT_CNT_M 0xFFFFFFFF -#define RFC_RAT_RATCNT_CNT_S 0 +#define RFC_RAT_RATCNT_CNT_W 32 +#define RFC_RAT_RATCNT_CNT_M 0xFFFFFFFF +#define RFC_RAT_RATCNT_CNT_S 0 //***************************************************************************** // @@ -91,9 +91,9 @@ // // Capture/compare value. The system CPU can safely read this register, but it // is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH0VAL_VAL_W 32 -#define RFC_RAT_RATCH0VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH0VAL_VAL_S 0 +#define RFC_RAT_RATCH0VAL_VAL_W 32 +#define RFC_RAT_RATCH0VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH0VAL_VAL_S 0 //***************************************************************************** // @@ -104,9 +104,9 @@ // // Capture/compare value. The system CPU can safely read this register, but it // is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH1VAL_VAL_W 32 -#define RFC_RAT_RATCH1VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH1VAL_VAL_S 0 +#define RFC_RAT_RATCH1VAL_VAL_W 32 +#define RFC_RAT_RATCH1VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH1VAL_VAL_S 0 //***************************************************************************** // @@ -117,9 +117,9 @@ // // Capture/compare value. The system CPU can safely read this register, but it // is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH2VAL_VAL_W 32 -#define RFC_RAT_RATCH2VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH2VAL_VAL_S 0 +#define RFC_RAT_RATCH2VAL_VAL_W 32 +#define RFC_RAT_RATCH2VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH2VAL_VAL_S 0 //***************************************************************************** // @@ -130,9 +130,9 @@ // // Capture/compare value. The system CPU can safely read this register, but it // is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH3VAL_VAL_W 32 -#define RFC_RAT_RATCH3VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH3VAL_VAL_S 0 +#define RFC_RAT_RATCH3VAL_VAL_W 32 +#define RFC_RAT_RATCH3VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH3VAL_VAL_S 0 //***************************************************************************** // @@ -143,9 +143,9 @@ // // Capture/compare value. The system CPU can safely read this register, but it // is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH4VAL_VAL_W 32 -#define RFC_RAT_RATCH4VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH4VAL_VAL_S 0 +#define RFC_RAT_RATCH4VAL_VAL_W 32 +#define RFC_RAT_RATCH4VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH4VAL_VAL_S 0 //***************************************************************************** // @@ -156,9 +156,9 @@ // // Capture/compare value. The system CPU can safely read this register, but it // is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH5VAL_VAL_W 32 -#define RFC_RAT_RATCH5VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH5VAL_VAL_S 0 +#define RFC_RAT_RATCH5VAL_VAL_W 32 +#define RFC_RAT_RATCH5VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH5VAL_VAL_S 0 //***************************************************************************** // @@ -169,9 +169,9 @@ // // Capture/compare value. The system CPU can safely read this register, but it // is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH6VAL_VAL_W 32 -#define RFC_RAT_RATCH6VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH6VAL_VAL_S 0 +#define RFC_RAT_RATCH6VAL_VAL_W 32 +#define RFC_RAT_RATCH6VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH6VAL_VAL_S 0 //***************************************************************************** // @@ -182,9 +182,8 @@ // // Capture/compare value. The system CPU can safely read this register, but it // is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH7VAL_VAL_W 32 -#define RFC_RAT_RATCH7VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH7VAL_VAL_S 0 - +#define RFC_RAT_RATCH7VAL_VAL_W 32 +#define RFC_RAT_RATCH7VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH7VAL_VAL_S 0 #endif // __RFC_RAT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_smph.h index 669eb26..38487b4 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_smph.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_smph.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_smph_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_smph_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_SMPH_H__ #define __HW_SMPH_H__ @@ -44,196 +44,196 @@ // //***************************************************************************** // MCU SEMAPHORE 0 -#define SMPH_O_SMPH0 0x00000000 +#define SMPH_O_SMPH0 0x00000000 // MCU SEMAPHORE 1 -#define SMPH_O_SMPH1 0x00000004 +#define SMPH_O_SMPH1 0x00000004 // MCU SEMAPHORE 2 -#define SMPH_O_SMPH2 0x00000008 +#define SMPH_O_SMPH2 0x00000008 // MCU SEMAPHORE 3 -#define SMPH_O_SMPH3 0x0000000C +#define SMPH_O_SMPH3 0x0000000C // MCU SEMAPHORE 4 -#define SMPH_O_SMPH4 0x00000010 +#define SMPH_O_SMPH4 0x00000010 // MCU SEMAPHORE 5 -#define SMPH_O_SMPH5 0x00000014 +#define SMPH_O_SMPH5 0x00000014 // MCU SEMAPHORE 6 -#define SMPH_O_SMPH6 0x00000018 +#define SMPH_O_SMPH6 0x00000018 // MCU SEMAPHORE 7 -#define SMPH_O_SMPH7 0x0000001C +#define SMPH_O_SMPH7 0x0000001C // MCU SEMAPHORE 8 -#define SMPH_O_SMPH8 0x00000020 +#define SMPH_O_SMPH8 0x00000020 // MCU SEMAPHORE 9 -#define SMPH_O_SMPH9 0x00000024 +#define SMPH_O_SMPH9 0x00000024 // MCU SEMAPHORE 10 -#define SMPH_O_SMPH10 0x00000028 +#define SMPH_O_SMPH10 0x00000028 // MCU SEMAPHORE 11 -#define SMPH_O_SMPH11 0x0000002C +#define SMPH_O_SMPH11 0x0000002C // MCU SEMAPHORE 12 -#define SMPH_O_SMPH12 0x00000030 +#define SMPH_O_SMPH12 0x00000030 // MCU SEMAPHORE 13 -#define SMPH_O_SMPH13 0x00000034 +#define SMPH_O_SMPH13 0x00000034 // MCU SEMAPHORE 14 -#define SMPH_O_SMPH14 0x00000038 +#define SMPH_O_SMPH14 0x00000038 // MCU SEMAPHORE 15 -#define SMPH_O_SMPH15 0x0000003C +#define SMPH_O_SMPH15 0x0000003C // MCU SEMAPHORE 16 -#define SMPH_O_SMPH16 0x00000040 +#define SMPH_O_SMPH16 0x00000040 // MCU SEMAPHORE 17 -#define SMPH_O_SMPH17 0x00000044 +#define SMPH_O_SMPH17 0x00000044 // MCU SEMAPHORE 18 -#define SMPH_O_SMPH18 0x00000048 +#define SMPH_O_SMPH18 0x00000048 // MCU SEMAPHORE 19 -#define SMPH_O_SMPH19 0x0000004C +#define SMPH_O_SMPH19 0x0000004C // MCU SEMAPHORE 20 -#define SMPH_O_SMPH20 0x00000050 +#define SMPH_O_SMPH20 0x00000050 // MCU SEMAPHORE 21 -#define SMPH_O_SMPH21 0x00000054 +#define SMPH_O_SMPH21 0x00000054 // MCU SEMAPHORE 22 -#define SMPH_O_SMPH22 0x00000058 +#define SMPH_O_SMPH22 0x00000058 // MCU SEMAPHORE 23 -#define SMPH_O_SMPH23 0x0000005C +#define SMPH_O_SMPH23 0x0000005C // MCU SEMAPHORE 24 -#define SMPH_O_SMPH24 0x00000060 +#define SMPH_O_SMPH24 0x00000060 // MCU SEMAPHORE 25 -#define SMPH_O_SMPH25 0x00000064 +#define SMPH_O_SMPH25 0x00000064 // MCU SEMAPHORE 26 -#define SMPH_O_SMPH26 0x00000068 +#define SMPH_O_SMPH26 0x00000068 // MCU SEMAPHORE 27 -#define SMPH_O_SMPH27 0x0000006C +#define SMPH_O_SMPH27 0x0000006C // MCU SEMAPHORE 28 -#define SMPH_O_SMPH28 0x00000070 +#define SMPH_O_SMPH28 0x00000070 // MCU SEMAPHORE 29 -#define SMPH_O_SMPH29 0x00000074 +#define SMPH_O_SMPH29 0x00000074 // MCU SEMAPHORE 30 -#define SMPH_O_SMPH30 0x00000078 +#define SMPH_O_SMPH30 0x00000078 // MCU SEMAPHORE 31 -#define SMPH_O_SMPH31 0x0000007C +#define SMPH_O_SMPH31 0x0000007C // MCU SEMAPHORE 0 ALIAS -#define SMPH_O_PEEK0 0x00000800 +#define SMPH_O_PEEK0 0x00000800 // MCU SEMAPHORE 1 ALIAS -#define SMPH_O_PEEK1 0x00000804 +#define SMPH_O_PEEK1 0x00000804 // MCU SEMAPHORE 2 ALIAS -#define SMPH_O_PEEK2 0x00000808 +#define SMPH_O_PEEK2 0x00000808 // MCU SEMAPHORE 3 ALIAS -#define SMPH_O_PEEK3 0x0000080C +#define SMPH_O_PEEK3 0x0000080C // MCU SEMAPHORE 4 ALIAS -#define SMPH_O_PEEK4 0x00000810 +#define SMPH_O_PEEK4 0x00000810 // MCU SEMAPHORE 5 ALIAS -#define SMPH_O_PEEK5 0x00000814 +#define SMPH_O_PEEK5 0x00000814 // MCU SEMAPHORE 6 ALIAS -#define SMPH_O_PEEK6 0x00000818 +#define SMPH_O_PEEK6 0x00000818 // MCU SEMAPHORE 7 ALIAS -#define SMPH_O_PEEK7 0x0000081C +#define SMPH_O_PEEK7 0x0000081C // MCU SEMAPHORE 8 ALIAS -#define SMPH_O_PEEK8 0x00000820 +#define SMPH_O_PEEK8 0x00000820 // MCU SEMAPHORE 9 ALIAS -#define SMPH_O_PEEK9 0x00000824 +#define SMPH_O_PEEK9 0x00000824 // MCU SEMAPHORE 10 ALIAS -#define SMPH_O_PEEK10 0x00000828 +#define SMPH_O_PEEK10 0x00000828 // MCU SEMAPHORE 11 ALIAS -#define SMPH_O_PEEK11 0x0000082C +#define SMPH_O_PEEK11 0x0000082C // MCU SEMAPHORE 12 ALIAS -#define SMPH_O_PEEK12 0x00000830 +#define SMPH_O_PEEK12 0x00000830 // MCU SEMAPHORE 13 ALIAS -#define SMPH_O_PEEK13 0x00000834 +#define SMPH_O_PEEK13 0x00000834 // MCU SEMAPHORE 14 ALIAS -#define SMPH_O_PEEK14 0x00000838 +#define SMPH_O_PEEK14 0x00000838 // MCU SEMAPHORE 15 ALIAS -#define SMPH_O_PEEK15 0x0000083C +#define SMPH_O_PEEK15 0x0000083C // MCU SEMAPHORE 16 ALIAS -#define SMPH_O_PEEK16 0x00000840 +#define SMPH_O_PEEK16 0x00000840 // MCU SEMAPHORE 17 ALIAS -#define SMPH_O_PEEK17 0x00000844 +#define SMPH_O_PEEK17 0x00000844 // MCU SEMAPHORE 18 ALIAS -#define SMPH_O_PEEK18 0x00000848 +#define SMPH_O_PEEK18 0x00000848 // MCU SEMAPHORE 19 ALIAS -#define SMPH_O_PEEK19 0x0000084C +#define SMPH_O_PEEK19 0x0000084C // MCU SEMAPHORE 20 ALIAS -#define SMPH_O_PEEK20 0x00000850 +#define SMPH_O_PEEK20 0x00000850 // MCU SEMAPHORE 21 ALIAS -#define SMPH_O_PEEK21 0x00000854 +#define SMPH_O_PEEK21 0x00000854 // MCU SEMAPHORE 22 ALIAS -#define SMPH_O_PEEK22 0x00000858 +#define SMPH_O_PEEK22 0x00000858 // MCU SEMAPHORE 23 ALIAS -#define SMPH_O_PEEK23 0x0000085C +#define SMPH_O_PEEK23 0x0000085C // MCU SEMAPHORE 24 ALIAS -#define SMPH_O_PEEK24 0x00000860 +#define SMPH_O_PEEK24 0x00000860 // MCU SEMAPHORE 25 ALIAS -#define SMPH_O_PEEK25 0x00000864 +#define SMPH_O_PEEK25 0x00000864 // MCU SEMAPHORE 26 ALIAS -#define SMPH_O_PEEK26 0x00000868 +#define SMPH_O_PEEK26 0x00000868 // MCU SEMAPHORE 27 ALIAS -#define SMPH_O_PEEK27 0x0000086C +#define SMPH_O_PEEK27 0x0000086C // MCU SEMAPHORE 28 ALIAS -#define SMPH_O_PEEK28 0x00000870 +#define SMPH_O_PEEK28 0x00000870 // MCU SEMAPHORE 29 ALIAS -#define SMPH_O_PEEK29 0x00000874 +#define SMPH_O_PEEK29 0x00000874 // MCU SEMAPHORE 30 ALIAS -#define SMPH_O_PEEK30 0x00000878 +#define SMPH_O_PEEK30 0x00000878 // MCU SEMAPHORE 31 ALIAS -#define SMPH_O_PEEK31 0x0000087C +#define SMPH_O_PEEK31 0x0000087C //***************************************************************************** // @@ -249,10 +249,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH0_STAT 0x00000001 -#define SMPH_SMPH0_STAT_BITN 0 -#define SMPH_SMPH0_STAT_M 0x00000001 -#define SMPH_SMPH0_STAT_S 0 +#define SMPH_SMPH0_STAT 0x00000001 +#define SMPH_SMPH0_STAT_BITN 0 +#define SMPH_SMPH0_STAT_M 0x00000001 +#define SMPH_SMPH0_STAT_S 0 //***************************************************************************** // @@ -268,10 +268,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH1_STAT 0x00000001 -#define SMPH_SMPH1_STAT_BITN 0 -#define SMPH_SMPH1_STAT_M 0x00000001 -#define SMPH_SMPH1_STAT_S 0 +#define SMPH_SMPH1_STAT 0x00000001 +#define SMPH_SMPH1_STAT_BITN 0 +#define SMPH_SMPH1_STAT_M 0x00000001 +#define SMPH_SMPH1_STAT_S 0 //***************************************************************************** // @@ -287,10 +287,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH2_STAT 0x00000001 -#define SMPH_SMPH2_STAT_BITN 0 -#define SMPH_SMPH2_STAT_M 0x00000001 -#define SMPH_SMPH2_STAT_S 0 +#define SMPH_SMPH2_STAT 0x00000001 +#define SMPH_SMPH2_STAT_BITN 0 +#define SMPH_SMPH2_STAT_M 0x00000001 +#define SMPH_SMPH2_STAT_S 0 //***************************************************************************** // @@ -306,10 +306,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH3_STAT 0x00000001 -#define SMPH_SMPH3_STAT_BITN 0 -#define SMPH_SMPH3_STAT_M 0x00000001 -#define SMPH_SMPH3_STAT_S 0 +#define SMPH_SMPH3_STAT 0x00000001 +#define SMPH_SMPH3_STAT_BITN 0 +#define SMPH_SMPH3_STAT_M 0x00000001 +#define SMPH_SMPH3_STAT_S 0 //***************************************************************************** // @@ -325,10 +325,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH4_STAT 0x00000001 -#define SMPH_SMPH4_STAT_BITN 0 -#define SMPH_SMPH4_STAT_M 0x00000001 -#define SMPH_SMPH4_STAT_S 0 +#define SMPH_SMPH4_STAT 0x00000001 +#define SMPH_SMPH4_STAT_BITN 0 +#define SMPH_SMPH4_STAT_M 0x00000001 +#define SMPH_SMPH4_STAT_S 0 //***************************************************************************** // @@ -344,10 +344,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH5_STAT 0x00000001 -#define SMPH_SMPH5_STAT_BITN 0 -#define SMPH_SMPH5_STAT_M 0x00000001 -#define SMPH_SMPH5_STAT_S 0 +#define SMPH_SMPH5_STAT 0x00000001 +#define SMPH_SMPH5_STAT_BITN 0 +#define SMPH_SMPH5_STAT_M 0x00000001 +#define SMPH_SMPH5_STAT_S 0 //***************************************************************************** // @@ -363,10 +363,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH6_STAT 0x00000001 -#define SMPH_SMPH6_STAT_BITN 0 -#define SMPH_SMPH6_STAT_M 0x00000001 -#define SMPH_SMPH6_STAT_S 0 +#define SMPH_SMPH6_STAT 0x00000001 +#define SMPH_SMPH6_STAT_BITN 0 +#define SMPH_SMPH6_STAT_M 0x00000001 +#define SMPH_SMPH6_STAT_S 0 //***************************************************************************** // @@ -382,10 +382,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH7_STAT 0x00000001 -#define SMPH_SMPH7_STAT_BITN 0 -#define SMPH_SMPH7_STAT_M 0x00000001 -#define SMPH_SMPH7_STAT_S 0 +#define SMPH_SMPH7_STAT 0x00000001 +#define SMPH_SMPH7_STAT_BITN 0 +#define SMPH_SMPH7_STAT_M 0x00000001 +#define SMPH_SMPH7_STAT_S 0 //***************************************************************************** // @@ -401,10 +401,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH8_STAT 0x00000001 -#define SMPH_SMPH8_STAT_BITN 0 -#define SMPH_SMPH8_STAT_M 0x00000001 -#define SMPH_SMPH8_STAT_S 0 +#define SMPH_SMPH8_STAT 0x00000001 +#define SMPH_SMPH8_STAT_BITN 0 +#define SMPH_SMPH8_STAT_M 0x00000001 +#define SMPH_SMPH8_STAT_S 0 //***************************************************************************** // @@ -420,10 +420,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH9_STAT 0x00000001 -#define SMPH_SMPH9_STAT_BITN 0 -#define SMPH_SMPH9_STAT_M 0x00000001 -#define SMPH_SMPH9_STAT_S 0 +#define SMPH_SMPH9_STAT 0x00000001 +#define SMPH_SMPH9_STAT_BITN 0 +#define SMPH_SMPH9_STAT_M 0x00000001 +#define SMPH_SMPH9_STAT_S 0 //***************************************************************************** // @@ -439,10 +439,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH10_STAT 0x00000001 -#define SMPH_SMPH10_STAT_BITN 0 -#define SMPH_SMPH10_STAT_M 0x00000001 -#define SMPH_SMPH10_STAT_S 0 +#define SMPH_SMPH10_STAT 0x00000001 +#define SMPH_SMPH10_STAT_BITN 0 +#define SMPH_SMPH10_STAT_M 0x00000001 +#define SMPH_SMPH10_STAT_S 0 //***************************************************************************** // @@ -458,10 +458,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH11_STAT 0x00000001 -#define SMPH_SMPH11_STAT_BITN 0 -#define SMPH_SMPH11_STAT_M 0x00000001 -#define SMPH_SMPH11_STAT_S 0 +#define SMPH_SMPH11_STAT 0x00000001 +#define SMPH_SMPH11_STAT_BITN 0 +#define SMPH_SMPH11_STAT_M 0x00000001 +#define SMPH_SMPH11_STAT_S 0 //***************************************************************************** // @@ -477,10 +477,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH12_STAT 0x00000001 -#define SMPH_SMPH12_STAT_BITN 0 -#define SMPH_SMPH12_STAT_M 0x00000001 -#define SMPH_SMPH12_STAT_S 0 +#define SMPH_SMPH12_STAT 0x00000001 +#define SMPH_SMPH12_STAT_BITN 0 +#define SMPH_SMPH12_STAT_M 0x00000001 +#define SMPH_SMPH12_STAT_S 0 //***************************************************************************** // @@ -496,10 +496,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH13_STAT 0x00000001 -#define SMPH_SMPH13_STAT_BITN 0 -#define SMPH_SMPH13_STAT_M 0x00000001 -#define SMPH_SMPH13_STAT_S 0 +#define SMPH_SMPH13_STAT 0x00000001 +#define SMPH_SMPH13_STAT_BITN 0 +#define SMPH_SMPH13_STAT_M 0x00000001 +#define SMPH_SMPH13_STAT_S 0 //***************************************************************************** // @@ -515,10 +515,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH14_STAT 0x00000001 -#define SMPH_SMPH14_STAT_BITN 0 -#define SMPH_SMPH14_STAT_M 0x00000001 -#define SMPH_SMPH14_STAT_S 0 +#define SMPH_SMPH14_STAT 0x00000001 +#define SMPH_SMPH14_STAT_BITN 0 +#define SMPH_SMPH14_STAT_M 0x00000001 +#define SMPH_SMPH14_STAT_S 0 //***************************************************************************** // @@ -534,10 +534,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH15_STAT 0x00000001 -#define SMPH_SMPH15_STAT_BITN 0 -#define SMPH_SMPH15_STAT_M 0x00000001 -#define SMPH_SMPH15_STAT_S 0 +#define SMPH_SMPH15_STAT 0x00000001 +#define SMPH_SMPH15_STAT_BITN 0 +#define SMPH_SMPH15_STAT_M 0x00000001 +#define SMPH_SMPH15_STAT_S 0 //***************************************************************************** // @@ -553,10 +553,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH16_STAT 0x00000001 -#define SMPH_SMPH16_STAT_BITN 0 -#define SMPH_SMPH16_STAT_M 0x00000001 -#define SMPH_SMPH16_STAT_S 0 +#define SMPH_SMPH16_STAT 0x00000001 +#define SMPH_SMPH16_STAT_BITN 0 +#define SMPH_SMPH16_STAT_M 0x00000001 +#define SMPH_SMPH16_STAT_S 0 //***************************************************************************** // @@ -572,10 +572,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH17_STAT 0x00000001 -#define SMPH_SMPH17_STAT_BITN 0 -#define SMPH_SMPH17_STAT_M 0x00000001 -#define SMPH_SMPH17_STAT_S 0 +#define SMPH_SMPH17_STAT 0x00000001 +#define SMPH_SMPH17_STAT_BITN 0 +#define SMPH_SMPH17_STAT_M 0x00000001 +#define SMPH_SMPH17_STAT_S 0 //***************************************************************************** // @@ -591,10 +591,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH18_STAT 0x00000001 -#define SMPH_SMPH18_STAT_BITN 0 -#define SMPH_SMPH18_STAT_M 0x00000001 -#define SMPH_SMPH18_STAT_S 0 +#define SMPH_SMPH18_STAT 0x00000001 +#define SMPH_SMPH18_STAT_BITN 0 +#define SMPH_SMPH18_STAT_M 0x00000001 +#define SMPH_SMPH18_STAT_S 0 //***************************************************************************** // @@ -610,10 +610,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH19_STAT 0x00000001 -#define SMPH_SMPH19_STAT_BITN 0 -#define SMPH_SMPH19_STAT_M 0x00000001 -#define SMPH_SMPH19_STAT_S 0 +#define SMPH_SMPH19_STAT 0x00000001 +#define SMPH_SMPH19_STAT_BITN 0 +#define SMPH_SMPH19_STAT_M 0x00000001 +#define SMPH_SMPH19_STAT_S 0 //***************************************************************************** // @@ -629,10 +629,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH20_STAT 0x00000001 -#define SMPH_SMPH20_STAT_BITN 0 -#define SMPH_SMPH20_STAT_M 0x00000001 -#define SMPH_SMPH20_STAT_S 0 +#define SMPH_SMPH20_STAT 0x00000001 +#define SMPH_SMPH20_STAT_BITN 0 +#define SMPH_SMPH20_STAT_M 0x00000001 +#define SMPH_SMPH20_STAT_S 0 //***************************************************************************** // @@ -648,10 +648,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH21_STAT 0x00000001 -#define SMPH_SMPH21_STAT_BITN 0 -#define SMPH_SMPH21_STAT_M 0x00000001 -#define SMPH_SMPH21_STAT_S 0 +#define SMPH_SMPH21_STAT 0x00000001 +#define SMPH_SMPH21_STAT_BITN 0 +#define SMPH_SMPH21_STAT_M 0x00000001 +#define SMPH_SMPH21_STAT_S 0 //***************************************************************************** // @@ -667,10 +667,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH22_STAT 0x00000001 -#define SMPH_SMPH22_STAT_BITN 0 -#define SMPH_SMPH22_STAT_M 0x00000001 -#define SMPH_SMPH22_STAT_S 0 +#define SMPH_SMPH22_STAT 0x00000001 +#define SMPH_SMPH22_STAT_BITN 0 +#define SMPH_SMPH22_STAT_M 0x00000001 +#define SMPH_SMPH22_STAT_S 0 //***************************************************************************** // @@ -686,10 +686,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH23_STAT 0x00000001 -#define SMPH_SMPH23_STAT_BITN 0 -#define SMPH_SMPH23_STAT_M 0x00000001 -#define SMPH_SMPH23_STAT_S 0 +#define SMPH_SMPH23_STAT 0x00000001 +#define SMPH_SMPH23_STAT_BITN 0 +#define SMPH_SMPH23_STAT_M 0x00000001 +#define SMPH_SMPH23_STAT_S 0 //***************************************************************************** // @@ -705,10 +705,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH24_STAT 0x00000001 -#define SMPH_SMPH24_STAT_BITN 0 -#define SMPH_SMPH24_STAT_M 0x00000001 -#define SMPH_SMPH24_STAT_S 0 +#define SMPH_SMPH24_STAT 0x00000001 +#define SMPH_SMPH24_STAT_BITN 0 +#define SMPH_SMPH24_STAT_M 0x00000001 +#define SMPH_SMPH24_STAT_S 0 //***************************************************************************** // @@ -724,10 +724,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH25_STAT 0x00000001 -#define SMPH_SMPH25_STAT_BITN 0 -#define SMPH_SMPH25_STAT_M 0x00000001 -#define SMPH_SMPH25_STAT_S 0 +#define SMPH_SMPH25_STAT 0x00000001 +#define SMPH_SMPH25_STAT_BITN 0 +#define SMPH_SMPH25_STAT_M 0x00000001 +#define SMPH_SMPH25_STAT_S 0 //***************************************************************************** // @@ -743,10 +743,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH26_STAT 0x00000001 -#define SMPH_SMPH26_STAT_BITN 0 -#define SMPH_SMPH26_STAT_M 0x00000001 -#define SMPH_SMPH26_STAT_S 0 +#define SMPH_SMPH26_STAT 0x00000001 +#define SMPH_SMPH26_STAT_BITN 0 +#define SMPH_SMPH26_STAT_M 0x00000001 +#define SMPH_SMPH26_STAT_S 0 //***************************************************************************** // @@ -762,10 +762,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH27_STAT 0x00000001 -#define SMPH_SMPH27_STAT_BITN 0 -#define SMPH_SMPH27_STAT_M 0x00000001 -#define SMPH_SMPH27_STAT_S 0 +#define SMPH_SMPH27_STAT 0x00000001 +#define SMPH_SMPH27_STAT_BITN 0 +#define SMPH_SMPH27_STAT_M 0x00000001 +#define SMPH_SMPH27_STAT_S 0 //***************************************************************************** // @@ -781,10 +781,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH28_STAT 0x00000001 -#define SMPH_SMPH28_STAT_BITN 0 -#define SMPH_SMPH28_STAT_M 0x00000001 -#define SMPH_SMPH28_STAT_S 0 +#define SMPH_SMPH28_STAT 0x00000001 +#define SMPH_SMPH28_STAT_BITN 0 +#define SMPH_SMPH28_STAT_M 0x00000001 +#define SMPH_SMPH28_STAT_S 0 //***************************************************************************** // @@ -800,10 +800,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH29_STAT 0x00000001 -#define SMPH_SMPH29_STAT_BITN 0 -#define SMPH_SMPH29_STAT_M 0x00000001 -#define SMPH_SMPH29_STAT_S 0 +#define SMPH_SMPH29_STAT 0x00000001 +#define SMPH_SMPH29_STAT_BITN 0 +#define SMPH_SMPH29_STAT_M 0x00000001 +#define SMPH_SMPH29_STAT_S 0 //***************************************************************************** // @@ -819,10 +819,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH30_STAT 0x00000001 -#define SMPH_SMPH30_STAT_BITN 0 -#define SMPH_SMPH30_STAT_M 0x00000001 -#define SMPH_SMPH30_STAT_S 0 +#define SMPH_SMPH30_STAT 0x00000001 +#define SMPH_SMPH30_STAT_BITN 0 +#define SMPH_SMPH30_STAT_M 0x00000001 +#define SMPH_SMPH30_STAT_S 0 //***************************************************************************** // @@ -838,10 +838,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH31_STAT 0x00000001 -#define SMPH_SMPH31_STAT_BITN 0 -#define SMPH_SMPH31_STAT_M 0x00000001 -#define SMPH_SMPH31_STAT_S 0 +#define SMPH_SMPH31_STAT 0x00000001 +#define SMPH_SMPH31_STAT_BITN 0 +#define SMPH_SMPH31_STAT_M 0x00000001 +#define SMPH_SMPH31_STAT_S 0 //***************************************************************************** // @@ -857,10 +857,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK0_STAT 0x00000001 -#define SMPH_PEEK0_STAT_BITN 0 -#define SMPH_PEEK0_STAT_M 0x00000001 -#define SMPH_PEEK0_STAT_S 0 +#define SMPH_PEEK0_STAT 0x00000001 +#define SMPH_PEEK0_STAT_BITN 0 +#define SMPH_PEEK0_STAT_M 0x00000001 +#define SMPH_PEEK0_STAT_S 0 //***************************************************************************** // @@ -876,10 +876,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK1_STAT 0x00000001 -#define SMPH_PEEK1_STAT_BITN 0 -#define SMPH_PEEK1_STAT_M 0x00000001 -#define SMPH_PEEK1_STAT_S 0 +#define SMPH_PEEK1_STAT 0x00000001 +#define SMPH_PEEK1_STAT_BITN 0 +#define SMPH_PEEK1_STAT_M 0x00000001 +#define SMPH_PEEK1_STAT_S 0 //***************************************************************************** // @@ -895,10 +895,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK2_STAT 0x00000001 -#define SMPH_PEEK2_STAT_BITN 0 -#define SMPH_PEEK2_STAT_M 0x00000001 -#define SMPH_PEEK2_STAT_S 0 +#define SMPH_PEEK2_STAT 0x00000001 +#define SMPH_PEEK2_STAT_BITN 0 +#define SMPH_PEEK2_STAT_M 0x00000001 +#define SMPH_PEEK2_STAT_S 0 //***************************************************************************** // @@ -914,10 +914,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK3_STAT 0x00000001 -#define SMPH_PEEK3_STAT_BITN 0 -#define SMPH_PEEK3_STAT_M 0x00000001 -#define SMPH_PEEK3_STAT_S 0 +#define SMPH_PEEK3_STAT 0x00000001 +#define SMPH_PEEK3_STAT_BITN 0 +#define SMPH_PEEK3_STAT_M 0x00000001 +#define SMPH_PEEK3_STAT_S 0 //***************************************************************************** // @@ -933,10 +933,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK4_STAT 0x00000001 -#define SMPH_PEEK4_STAT_BITN 0 -#define SMPH_PEEK4_STAT_M 0x00000001 -#define SMPH_PEEK4_STAT_S 0 +#define SMPH_PEEK4_STAT 0x00000001 +#define SMPH_PEEK4_STAT_BITN 0 +#define SMPH_PEEK4_STAT_M 0x00000001 +#define SMPH_PEEK4_STAT_S 0 //***************************************************************************** // @@ -952,10 +952,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK5_STAT 0x00000001 -#define SMPH_PEEK5_STAT_BITN 0 -#define SMPH_PEEK5_STAT_M 0x00000001 -#define SMPH_PEEK5_STAT_S 0 +#define SMPH_PEEK5_STAT 0x00000001 +#define SMPH_PEEK5_STAT_BITN 0 +#define SMPH_PEEK5_STAT_M 0x00000001 +#define SMPH_PEEK5_STAT_S 0 //***************************************************************************** // @@ -971,10 +971,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK6_STAT 0x00000001 -#define SMPH_PEEK6_STAT_BITN 0 -#define SMPH_PEEK6_STAT_M 0x00000001 -#define SMPH_PEEK6_STAT_S 0 +#define SMPH_PEEK6_STAT 0x00000001 +#define SMPH_PEEK6_STAT_BITN 0 +#define SMPH_PEEK6_STAT_M 0x00000001 +#define SMPH_PEEK6_STAT_S 0 //***************************************************************************** // @@ -990,10 +990,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK7_STAT 0x00000001 -#define SMPH_PEEK7_STAT_BITN 0 -#define SMPH_PEEK7_STAT_M 0x00000001 -#define SMPH_PEEK7_STAT_S 0 +#define SMPH_PEEK7_STAT 0x00000001 +#define SMPH_PEEK7_STAT_BITN 0 +#define SMPH_PEEK7_STAT_M 0x00000001 +#define SMPH_PEEK7_STAT_S 0 //***************************************************************************** // @@ -1009,10 +1009,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK8_STAT 0x00000001 -#define SMPH_PEEK8_STAT_BITN 0 -#define SMPH_PEEK8_STAT_M 0x00000001 -#define SMPH_PEEK8_STAT_S 0 +#define SMPH_PEEK8_STAT 0x00000001 +#define SMPH_PEEK8_STAT_BITN 0 +#define SMPH_PEEK8_STAT_M 0x00000001 +#define SMPH_PEEK8_STAT_S 0 //***************************************************************************** // @@ -1028,10 +1028,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK9_STAT 0x00000001 -#define SMPH_PEEK9_STAT_BITN 0 -#define SMPH_PEEK9_STAT_M 0x00000001 -#define SMPH_PEEK9_STAT_S 0 +#define SMPH_PEEK9_STAT 0x00000001 +#define SMPH_PEEK9_STAT_BITN 0 +#define SMPH_PEEK9_STAT_M 0x00000001 +#define SMPH_PEEK9_STAT_S 0 //***************************************************************************** // @@ -1047,10 +1047,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK10_STAT 0x00000001 -#define SMPH_PEEK10_STAT_BITN 0 -#define SMPH_PEEK10_STAT_M 0x00000001 -#define SMPH_PEEK10_STAT_S 0 +#define SMPH_PEEK10_STAT 0x00000001 +#define SMPH_PEEK10_STAT_BITN 0 +#define SMPH_PEEK10_STAT_M 0x00000001 +#define SMPH_PEEK10_STAT_S 0 //***************************************************************************** // @@ -1066,10 +1066,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK11_STAT 0x00000001 -#define SMPH_PEEK11_STAT_BITN 0 -#define SMPH_PEEK11_STAT_M 0x00000001 -#define SMPH_PEEK11_STAT_S 0 +#define SMPH_PEEK11_STAT 0x00000001 +#define SMPH_PEEK11_STAT_BITN 0 +#define SMPH_PEEK11_STAT_M 0x00000001 +#define SMPH_PEEK11_STAT_S 0 //***************************************************************************** // @@ -1085,10 +1085,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK12_STAT 0x00000001 -#define SMPH_PEEK12_STAT_BITN 0 -#define SMPH_PEEK12_STAT_M 0x00000001 -#define SMPH_PEEK12_STAT_S 0 +#define SMPH_PEEK12_STAT 0x00000001 +#define SMPH_PEEK12_STAT_BITN 0 +#define SMPH_PEEK12_STAT_M 0x00000001 +#define SMPH_PEEK12_STAT_S 0 //***************************************************************************** // @@ -1104,10 +1104,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK13_STAT 0x00000001 -#define SMPH_PEEK13_STAT_BITN 0 -#define SMPH_PEEK13_STAT_M 0x00000001 -#define SMPH_PEEK13_STAT_S 0 +#define SMPH_PEEK13_STAT 0x00000001 +#define SMPH_PEEK13_STAT_BITN 0 +#define SMPH_PEEK13_STAT_M 0x00000001 +#define SMPH_PEEK13_STAT_S 0 //***************************************************************************** // @@ -1123,10 +1123,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK14_STAT 0x00000001 -#define SMPH_PEEK14_STAT_BITN 0 -#define SMPH_PEEK14_STAT_M 0x00000001 -#define SMPH_PEEK14_STAT_S 0 +#define SMPH_PEEK14_STAT 0x00000001 +#define SMPH_PEEK14_STAT_BITN 0 +#define SMPH_PEEK14_STAT_M 0x00000001 +#define SMPH_PEEK14_STAT_S 0 //***************************************************************************** // @@ -1142,10 +1142,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK15_STAT 0x00000001 -#define SMPH_PEEK15_STAT_BITN 0 -#define SMPH_PEEK15_STAT_M 0x00000001 -#define SMPH_PEEK15_STAT_S 0 +#define SMPH_PEEK15_STAT 0x00000001 +#define SMPH_PEEK15_STAT_BITN 0 +#define SMPH_PEEK15_STAT_M 0x00000001 +#define SMPH_PEEK15_STAT_S 0 //***************************************************************************** // @@ -1161,10 +1161,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK16_STAT 0x00000001 -#define SMPH_PEEK16_STAT_BITN 0 -#define SMPH_PEEK16_STAT_M 0x00000001 -#define SMPH_PEEK16_STAT_S 0 +#define SMPH_PEEK16_STAT 0x00000001 +#define SMPH_PEEK16_STAT_BITN 0 +#define SMPH_PEEK16_STAT_M 0x00000001 +#define SMPH_PEEK16_STAT_S 0 //***************************************************************************** // @@ -1180,10 +1180,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK17_STAT 0x00000001 -#define SMPH_PEEK17_STAT_BITN 0 -#define SMPH_PEEK17_STAT_M 0x00000001 -#define SMPH_PEEK17_STAT_S 0 +#define SMPH_PEEK17_STAT 0x00000001 +#define SMPH_PEEK17_STAT_BITN 0 +#define SMPH_PEEK17_STAT_M 0x00000001 +#define SMPH_PEEK17_STAT_S 0 //***************************************************************************** // @@ -1199,10 +1199,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK18_STAT 0x00000001 -#define SMPH_PEEK18_STAT_BITN 0 -#define SMPH_PEEK18_STAT_M 0x00000001 -#define SMPH_PEEK18_STAT_S 0 +#define SMPH_PEEK18_STAT 0x00000001 +#define SMPH_PEEK18_STAT_BITN 0 +#define SMPH_PEEK18_STAT_M 0x00000001 +#define SMPH_PEEK18_STAT_S 0 //***************************************************************************** // @@ -1218,10 +1218,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK19_STAT 0x00000001 -#define SMPH_PEEK19_STAT_BITN 0 -#define SMPH_PEEK19_STAT_M 0x00000001 -#define SMPH_PEEK19_STAT_S 0 +#define SMPH_PEEK19_STAT 0x00000001 +#define SMPH_PEEK19_STAT_BITN 0 +#define SMPH_PEEK19_STAT_M 0x00000001 +#define SMPH_PEEK19_STAT_S 0 //***************************************************************************** // @@ -1237,10 +1237,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK20_STAT 0x00000001 -#define SMPH_PEEK20_STAT_BITN 0 -#define SMPH_PEEK20_STAT_M 0x00000001 -#define SMPH_PEEK20_STAT_S 0 +#define SMPH_PEEK20_STAT 0x00000001 +#define SMPH_PEEK20_STAT_BITN 0 +#define SMPH_PEEK20_STAT_M 0x00000001 +#define SMPH_PEEK20_STAT_S 0 //***************************************************************************** // @@ -1256,10 +1256,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK21_STAT 0x00000001 -#define SMPH_PEEK21_STAT_BITN 0 -#define SMPH_PEEK21_STAT_M 0x00000001 -#define SMPH_PEEK21_STAT_S 0 +#define SMPH_PEEK21_STAT 0x00000001 +#define SMPH_PEEK21_STAT_BITN 0 +#define SMPH_PEEK21_STAT_M 0x00000001 +#define SMPH_PEEK21_STAT_S 0 //***************************************************************************** // @@ -1275,10 +1275,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK22_STAT 0x00000001 -#define SMPH_PEEK22_STAT_BITN 0 -#define SMPH_PEEK22_STAT_M 0x00000001 -#define SMPH_PEEK22_STAT_S 0 +#define SMPH_PEEK22_STAT 0x00000001 +#define SMPH_PEEK22_STAT_BITN 0 +#define SMPH_PEEK22_STAT_M 0x00000001 +#define SMPH_PEEK22_STAT_S 0 //***************************************************************************** // @@ -1294,10 +1294,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK23_STAT 0x00000001 -#define SMPH_PEEK23_STAT_BITN 0 -#define SMPH_PEEK23_STAT_M 0x00000001 -#define SMPH_PEEK23_STAT_S 0 +#define SMPH_PEEK23_STAT 0x00000001 +#define SMPH_PEEK23_STAT_BITN 0 +#define SMPH_PEEK23_STAT_M 0x00000001 +#define SMPH_PEEK23_STAT_S 0 //***************************************************************************** // @@ -1313,10 +1313,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK24_STAT 0x00000001 -#define SMPH_PEEK24_STAT_BITN 0 -#define SMPH_PEEK24_STAT_M 0x00000001 -#define SMPH_PEEK24_STAT_S 0 +#define SMPH_PEEK24_STAT 0x00000001 +#define SMPH_PEEK24_STAT_BITN 0 +#define SMPH_PEEK24_STAT_M 0x00000001 +#define SMPH_PEEK24_STAT_S 0 //***************************************************************************** // @@ -1332,10 +1332,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK25_STAT 0x00000001 -#define SMPH_PEEK25_STAT_BITN 0 -#define SMPH_PEEK25_STAT_M 0x00000001 -#define SMPH_PEEK25_STAT_S 0 +#define SMPH_PEEK25_STAT 0x00000001 +#define SMPH_PEEK25_STAT_BITN 0 +#define SMPH_PEEK25_STAT_M 0x00000001 +#define SMPH_PEEK25_STAT_S 0 //***************************************************************************** // @@ -1351,10 +1351,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK26_STAT 0x00000001 -#define SMPH_PEEK26_STAT_BITN 0 -#define SMPH_PEEK26_STAT_M 0x00000001 -#define SMPH_PEEK26_STAT_S 0 +#define SMPH_PEEK26_STAT 0x00000001 +#define SMPH_PEEK26_STAT_BITN 0 +#define SMPH_PEEK26_STAT_M 0x00000001 +#define SMPH_PEEK26_STAT_S 0 //***************************************************************************** // @@ -1370,10 +1370,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK27_STAT 0x00000001 -#define SMPH_PEEK27_STAT_BITN 0 -#define SMPH_PEEK27_STAT_M 0x00000001 -#define SMPH_PEEK27_STAT_S 0 +#define SMPH_PEEK27_STAT 0x00000001 +#define SMPH_PEEK27_STAT_BITN 0 +#define SMPH_PEEK27_STAT_M 0x00000001 +#define SMPH_PEEK27_STAT_S 0 //***************************************************************************** // @@ -1389,10 +1389,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK28_STAT 0x00000001 -#define SMPH_PEEK28_STAT_BITN 0 -#define SMPH_PEEK28_STAT_M 0x00000001 -#define SMPH_PEEK28_STAT_S 0 +#define SMPH_PEEK28_STAT 0x00000001 +#define SMPH_PEEK28_STAT_BITN 0 +#define SMPH_PEEK28_STAT_M 0x00000001 +#define SMPH_PEEK28_STAT_S 0 //***************************************************************************** // @@ -1408,10 +1408,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK29_STAT 0x00000001 -#define SMPH_PEEK29_STAT_BITN 0 -#define SMPH_PEEK29_STAT_M 0x00000001 -#define SMPH_PEEK29_STAT_S 0 +#define SMPH_PEEK29_STAT 0x00000001 +#define SMPH_PEEK29_STAT_BITN 0 +#define SMPH_PEEK29_STAT_M 0x00000001 +#define SMPH_PEEK29_STAT_S 0 //***************************************************************************** // @@ -1427,10 +1427,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK30_STAT 0x00000001 -#define SMPH_PEEK30_STAT_BITN 0 -#define SMPH_PEEK30_STAT_M 0x00000001 -#define SMPH_PEEK30_STAT_S 0 +#define SMPH_PEEK30_STAT 0x00000001 +#define SMPH_PEEK30_STAT_BITN 0 +#define SMPH_PEEK30_STAT_M 0x00000001 +#define SMPH_PEEK30_STAT_S 0 //***************************************************************************** // @@ -1446,10 +1446,9 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK31_STAT 0x00000001 -#define SMPH_PEEK31_STAT_BITN 0 -#define SMPH_PEEK31_STAT_M 0x00000001 -#define SMPH_PEEK31_STAT_S 0 - +#define SMPH_PEEK31_STAT 0x00000001 +#define SMPH_PEEK31_STAT_BITN 0 +#define SMPH_PEEK31_STAT_M 0x00000001 +#define SMPH_PEEK31_STAT_S 0 #endif // __SMPH__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ssi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ssi.h index a83b856..3d617c7 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ssi.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_ssi.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_ssi_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_ssi_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_SSI_H__ #define __HW_SSI_H__ @@ -44,34 +44,34 @@ // //***************************************************************************** // Control 0 -#define SSI_O_CR0 0x00000000 +#define SSI_O_CR0 0x00000000 // Control 1 -#define SSI_O_CR1 0x00000004 +#define SSI_O_CR1 0x00000004 // Data -#define SSI_O_DR 0x00000008 +#define SSI_O_DR 0x00000008 // Status -#define SSI_O_SR 0x0000000C +#define SSI_O_SR 0x0000000C // Clock Prescale -#define SSI_O_CPSR 0x00000010 +#define SSI_O_CPSR 0x00000010 // Interrupt Mask Set and Clear -#define SSI_O_IMSC 0x00000014 +#define SSI_O_IMSC 0x00000014 // Raw Interrupt Status -#define SSI_O_RIS 0x00000018 +#define SSI_O_RIS 0x00000018 // Masked Interrupt Status -#define SSI_O_MIS 0x0000001C +#define SSI_O_MIS 0x0000001C // Interrupt Clear -#define SSI_O_ICR 0x00000020 +#define SSI_O_ICR 0x00000020 // DMA Control -#define SSI_O_DMACR 0x00000024 +#define SSI_O_DMACR 0x00000024 //***************************************************************************** // @@ -85,9 +85,9 @@ // bit rate is // (SSI's clock frequency)/((SCR+1)*CPSR.CPSDVSR). // SCR is a value from 0-255. -#define SSI_CR0_SCR_W 8 -#define SSI_CR0_SCR_M 0x0000FF00 -#define SSI_CR0_SCR_S 8 +#define SSI_CR0_SCR_W 8 +#define SSI_CR0_SCR_M 0x0000FF00 +#define SSI_CR0_SCR_S 8 // Field: [7] SPH // @@ -101,12 +101,12 @@ // transition. // 1ST_CLK_EDGE Data is captured on the first clock edge // transition. -#define SSI_CR0_SPH 0x00000080 -#define SSI_CR0_SPH_BITN 7 -#define SSI_CR0_SPH_M 0x00000080 -#define SSI_CR0_SPH_S 7 -#define SSI_CR0_SPH_2ND_CLK_EDGE 0x00000080 -#define SSI_CR0_SPH_1ST_CLK_EDGE 0x00000000 +#define SSI_CR0_SPH 0x00000080 +#define SSI_CR0_SPH_BITN 7 +#define SSI_CR0_SPH_M 0x00000080 +#define SSI_CR0_SPH_S 7 +#define SSI_CR0_SPH_2ND_CLK_EDGE 0x00000080 +#define SSI_CR0_SPH_1ST_CLK_EDGE 0x00000000 // Field: [6] SPO // @@ -117,12 +117,12 @@ // LOW SSI produces a steady state LOW value on the // CLKOUT pin when data is // not being transferred. -#define SSI_CR0_SPO 0x00000040 -#define SSI_CR0_SPO_BITN 6 -#define SSI_CR0_SPO_M 0x00000040 -#define SSI_CR0_SPO_S 6 -#define SSI_CR0_SPO_HIGH 0x00000040 -#define SSI_CR0_SPO_LOW 0x00000000 +#define SSI_CR0_SPO 0x00000040 +#define SSI_CR0_SPO_BITN 6 +#define SSI_CR0_SPO_M 0x00000040 +#define SSI_CR0_SPO_S 6 +#define SSI_CR0_SPO_HIGH 0x00000040 +#define SSI_CR0_SPO_LOW 0x00000000 // Field: [5:4] FRF // @@ -134,12 +134,12 @@ // NATIONAL_MICROWIRE National Microwire frame format // TI_SYNC_SERIAL TI synchronous serial frame format // MOTOROLA_SPI Motorola SPI frame format -#define SSI_CR0_FRF_W 2 -#define SSI_CR0_FRF_M 0x00000030 -#define SSI_CR0_FRF_S 4 -#define SSI_CR0_FRF_NATIONAL_MICROWIRE 0x00000020 -#define SSI_CR0_FRF_TI_SYNC_SERIAL 0x00000010 -#define SSI_CR0_FRF_MOTOROLA_SPI 0x00000000 +#define SSI_CR0_FRF_W 2 +#define SSI_CR0_FRF_M 0x00000030 +#define SSI_CR0_FRF_S 4 +#define SSI_CR0_FRF_NATIONAL_MICROWIRE 0x00000020 +#define SSI_CR0_FRF_TI_SYNC_SERIAL 0x00000010 +#define SSI_CR0_FRF_MOTOROLA_SPI 0x00000000 // Field: [3:0] DSS // @@ -159,22 +159,22 @@ // 6_BIT 6-bit data // 5_BIT 5-bit data // 4_BIT 4-bit data -#define SSI_CR0_DSS_W 4 -#define SSI_CR0_DSS_M 0x0000000F -#define SSI_CR0_DSS_S 0 -#define SSI_CR0_DSS_16_BIT 0x0000000F -#define SSI_CR0_DSS_15_BIT 0x0000000E -#define SSI_CR0_DSS_14_BIT 0x0000000D -#define SSI_CR0_DSS_13_BIT 0x0000000C -#define SSI_CR0_DSS_12_BIT 0x0000000B -#define SSI_CR0_DSS_11_BIT 0x0000000A -#define SSI_CR0_DSS_10_BIT 0x00000009 -#define SSI_CR0_DSS_9_BIT 0x00000008 -#define SSI_CR0_DSS_8_BIT 0x00000007 -#define SSI_CR0_DSS_7_BIT 0x00000006 -#define SSI_CR0_DSS_6_BIT 0x00000005 -#define SSI_CR0_DSS_5_BIT 0x00000004 -#define SSI_CR0_DSS_4_BIT 0x00000003 +#define SSI_CR0_DSS_W 4 +#define SSI_CR0_DSS_M 0x0000000F +#define SSI_CR0_DSS_S 0 +#define SSI_CR0_DSS_16_BIT 0x0000000F +#define SSI_CR0_DSS_15_BIT 0x0000000E +#define SSI_CR0_DSS_14_BIT 0x0000000D +#define SSI_CR0_DSS_13_BIT 0x0000000C +#define SSI_CR0_DSS_12_BIT 0x0000000B +#define SSI_CR0_DSS_11_BIT 0x0000000A +#define SSI_CR0_DSS_10_BIT 0x00000009 +#define SSI_CR0_DSS_9_BIT 0x00000008 +#define SSI_CR0_DSS_8_BIT 0x00000007 +#define SSI_CR0_DSS_7_BIT 0x00000006 +#define SSI_CR0_DSS_6_BIT 0x00000005 +#define SSI_CR0_DSS_5_BIT 0x00000004 +#define SSI_CR0_DSS_4_BIT 0x00000003 //***************************************************************************** // @@ -193,10 +193,10 @@ // // 0: SSI can drive the TXD output in slave mode. // 1: SSI cannot drive the TXD output in slave mode. -#define SSI_CR1_SOD 0x00000008 -#define SSI_CR1_SOD_BITN 3 -#define SSI_CR1_SOD_M 0x00000008 -#define SSI_CR1_SOD_S 3 +#define SSI_CR1_SOD 0x00000008 +#define SSI_CR1_SOD_BITN 3 +#define SSI_CR1_SOD_M 0x00000008 +#define SSI_CR1_SOD_S 3 // Field: [2] MS // @@ -205,12 +205,12 @@ // ENUMs: // SLAVE Device configured as slave // MASTER Device configured as master -#define SSI_CR1_MS 0x00000004 -#define SSI_CR1_MS_BITN 2 -#define SSI_CR1_MS_M 0x00000004 -#define SSI_CR1_MS_S 2 -#define SSI_CR1_MS_SLAVE 0x00000004 -#define SSI_CR1_MS_MASTER 0x00000000 +#define SSI_CR1_MS 0x00000004 +#define SSI_CR1_MS_BITN 2 +#define SSI_CR1_MS_M 0x00000004 +#define SSI_CR1_MS_S 2 +#define SSI_CR1_MS_SLAVE 0x00000004 +#define SSI_CR1_MS_MASTER 0x00000000 // Field: [1] SSE // @@ -218,12 +218,12 @@ // ENUMs: // SSI_ENABLED Operation enabled // SSI_DISABLED Operation disabled -#define SSI_CR1_SSE 0x00000002 -#define SSI_CR1_SSE_BITN 1 -#define SSI_CR1_SSE_M 0x00000002 -#define SSI_CR1_SSE_S 1 -#define SSI_CR1_SSE_SSI_ENABLED 0x00000002 -#define SSI_CR1_SSE_SSI_DISABLED 0x00000000 +#define SSI_CR1_SSE 0x00000002 +#define SSI_CR1_SSE_BITN 1 +#define SSI_CR1_SSE_M 0x00000002 +#define SSI_CR1_SSE_S 1 +#define SSI_CR1_SSE_SSI_ENABLED 0x00000002 +#define SSI_CR1_SSE_SSI_DISABLED 0x00000000 // Field: [0] LBM // @@ -232,10 +232,10 @@ // 0: Normal serial port operation enabled. // 1: Output of transmit serial shifter is connected to input of receive serial // shifter internally. -#define SSI_CR1_LBM 0x00000001 -#define SSI_CR1_LBM_BITN 0 -#define SSI_CR1_LBM_M 0x00000001 -#define SSI_CR1_LBM_S 0 +#define SSI_CR1_LBM 0x00000001 +#define SSI_CR1_LBM_BITN 0 +#define SSI_CR1_LBM_M 0x00000001 +#define SSI_CR1_LBM_S 0 //***************************************************************************** // @@ -249,9 +249,9 @@ // right-justified when SSI is programmed for a data size that is less than 16 // bits (CR0.DSS != 0b1111). Unused bits at the top are ignored by transmit // logic. The receive logic automatically right-justifies. -#define SSI_DR_DATA_W 16 -#define SSI_DR_DATA_M 0x0000FFFF -#define SSI_DR_DATA_S 0 +#define SSI_DR_DATA_W 16 +#define SSI_DR_DATA_M 0x0000FFFF +#define SSI_DR_DATA_S 0 //***************************************************************************** // @@ -265,10 +265,10 @@ // 0: SSI is idle // 1: SSI is currently transmitting and/or receiving a frame or the transmit // FIFO is not empty. -#define SSI_SR_BSY 0x00000010 -#define SSI_SR_BSY_BITN 4 -#define SSI_SR_BSY_M 0x00000010 -#define SSI_SR_BSY_S 4 +#define SSI_SR_BSY 0x00000010 +#define SSI_SR_BSY_BITN 4 +#define SSI_SR_BSY_M 0x00000010 +#define SSI_SR_BSY_S 4 // Field: [3] RFF // @@ -276,10 +276,10 @@ // // 0: Receive FIFO is not full. // 1: Receive FIFO is full. -#define SSI_SR_RFF 0x00000008 -#define SSI_SR_RFF_BITN 3 -#define SSI_SR_RFF_M 0x00000008 -#define SSI_SR_RFF_S 3 +#define SSI_SR_RFF 0x00000008 +#define SSI_SR_RFF_BITN 3 +#define SSI_SR_RFF_M 0x00000008 +#define SSI_SR_RFF_S 3 // Field: [2] RNE // @@ -287,10 +287,10 @@ // // 0: Receive FIFO is empty. // 1: Receive FIFO is not empty. -#define SSI_SR_RNE 0x00000004 -#define SSI_SR_RNE_BITN 2 -#define SSI_SR_RNE_M 0x00000004 -#define SSI_SR_RNE_S 2 +#define SSI_SR_RNE 0x00000004 +#define SSI_SR_RNE_BITN 2 +#define SSI_SR_RNE_M 0x00000004 +#define SSI_SR_RNE_S 2 // Field: [1] TNF // @@ -298,10 +298,10 @@ // // 0: Transmit FIFO is full. // 1: Transmit FIFO is not full. -#define SSI_SR_TNF 0x00000002 -#define SSI_SR_TNF_BITN 1 -#define SSI_SR_TNF_M 0x00000002 -#define SSI_SR_TNF_S 1 +#define SSI_SR_TNF 0x00000002 +#define SSI_SR_TNF_BITN 1 +#define SSI_SR_TNF_M 0x00000002 +#define SSI_SR_TNF_S 1 // Field: [0] TFE // @@ -309,10 +309,10 @@ // // 0: Transmit FIFO is not empty. // 1: Transmit FIFO is empty. -#define SSI_SR_TFE 0x00000001 -#define SSI_SR_TFE_BITN 0 -#define SSI_SR_TFE_M 0x00000001 -#define SSI_SR_TFE_S 0 +#define SSI_SR_TFE 0x00000001 +#define SSI_SR_TFE_BITN 0 +#define SSI_SR_TFE_M 0x00000001 +#define SSI_SR_TFE_S 0 //***************************************************************************** // @@ -328,9 +328,9 @@ // (2-254). The least significant bit of the programmed number is hard-coded to // zero. If an odd number is written to this register, data read back from // this register has the least significant bit as zero. -#define SSI_CPSR_CPSDVSR_W 8 -#define SSI_CPSR_CPSDVSR_M 0x000000FF -#define SSI_CPSR_CPSDVSR_S 0 +#define SSI_CPSR_CPSDVSR_W 8 +#define SSI_CPSR_CPSDVSR_M 0x000000FF +#define SSI_CPSR_CPSDVSR_S 0 //***************************************************************************** // @@ -344,10 +344,10 @@ // 1, the mask for transmit FIFO interrupt is set which means the interrupt // state will be reflected in MIS.TXMIS. A write of 0 clears the mask which // means MIS.TXMIS will not reflect the interrupt. -#define SSI_IMSC_TXIM 0x00000008 -#define SSI_IMSC_TXIM_BITN 3 -#define SSI_IMSC_TXIM_M 0x00000008 -#define SSI_IMSC_TXIM_S 3 +#define SSI_IMSC_TXIM 0x00000008 +#define SSI_IMSC_TXIM_BITN 3 +#define SSI_IMSC_TXIM_M 0x00000008 +#define SSI_IMSC_TXIM_S 3 // Field: [2] RXIM // @@ -356,10 +356,10 @@ // the mask for receive FIFO interrupt is set which means the interrupt state // will be reflected in MIS.RXMIS. A write of 0 clears the mask which means // MIS.RXMIS will not reflect the interrupt. -#define SSI_IMSC_RXIM 0x00000004 -#define SSI_IMSC_RXIM_BITN 2 -#define SSI_IMSC_RXIM_M 0x00000004 -#define SSI_IMSC_RXIM_S 2 +#define SSI_IMSC_RXIM 0x00000004 +#define SSI_IMSC_RXIM_BITN 2 +#define SSI_IMSC_RXIM_M 0x00000004 +#define SSI_IMSC_RXIM_S 2 // Field: [1] RTIM // @@ -368,10 +368,10 @@ // 1, the mask for receive timeout interrupt is set which means the interrupt // state will be reflected in MIS.RTMIS. A write of 0 clears the mask which // means MIS.RTMIS will not reflect the interrupt. -#define SSI_IMSC_RTIM 0x00000002 -#define SSI_IMSC_RTIM_BITN 1 -#define SSI_IMSC_RTIM_M 0x00000002 -#define SSI_IMSC_RTIM_S 1 +#define SSI_IMSC_RTIM 0x00000002 +#define SSI_IMSC_RTIM_BITN 1 +#define SSI_IMSC_RTIM_M 0x00000002 +#define SSI_IMSC_RTIM_S 1 // Field: [0] RORIM // @@ -380,10 +380,10 @@ // 1, the mask for receive overrun interrupt is set which means the interrupt // state will be reflected in MIS.RORMIS. A write of 0 clears the mask which // means MIS.RORMIS will not reflect the interrupt. -#define SSI_IMSC_RORIM 0x00000001 -#define SSI_IMSC_RORIM_BITN 0 -#define SSI_IMSC_RORIM_M 0x00000001 -#define SSI_IMSC_RORIM_S 0 +#define SSI_IMSC_RORIM 0x00000001 +#define SSI_IMSC_RORIM_BITN 0 +#define SSI_IMSC_RORIM_M 0x00000001 +#define SSI_IMSC_RORIM_S 0 //***************************************************************************** // @@ -401,20 +401,20 @@ // interrupts. // - SSI and interrupts can be enabled so that data can be written to the // transmit FIFO by an interrupt service routine. -#define SSI_RIS_TXRIS 0x00000008 -#define SSI_RIS_TXRIS_BITN 3 -#define SSI_RIS_TXRIS_M 0x00000008 -#define SSI_RIS_TXRIS_S 3 +#define SSI_RIS_TXRIS 0x00000008 +#define SSI_RIS_TXRIS_BITN 3 +#define SSI_RIS_TXRIS_M 0x00000008 +#define SSI_RIS_TXRIS_S 3 // Field: [2] RXRIS // // Raw interrupt state of receive FIFO interrupt: // The receive interrupt is asserted when there are four or more valid entries // in the receive FIFO. -#define SSI_RIS_RXRIS 0x00000004 -#define SSI_RIS_RXRIS_BITN 2 -#define SSI_RIS_RXRIS_M 0x00000004 -#define SSI_RIS_RXRIS_S 2 +#define SSI_RIS_RXRIS 0x00000004 +#define SSI_RIS_RXRIS_BITN 2 +#define SSI_RIS_RXRIS_M 0x00000004 +#define SSI_RIS_RXRIS_S 2 // Field: [1] RTRIS // @@ -425,10 +425,10 @@ // requires servicing. This interrupt is deasserted if the receive FIFO becomes // empty by subsequent reads, or if new data is received on RXD. // It can also be cleared by writing to ICR.RTIC. -#define SSI_RIS_RTRIS 0x00000002 -#define SSI_RIS_RTRIS_BITN 1 -#define SSI_RIS_RTRIS_M 0x00000002 -#define SSI_RIS_RTRIS_S 1 +#define SSI_RIS_RTRIS 0x00000002 +#define SSI_RIS_RTRIS_BITN 1 +#define SSI_RIS_RTRIS_M 0x00000002 +#define SSI_RIS_RTRIS_S 1 // Field: [0] RORRIS // @@ -438,10 +438,10 @@ // is over-written in the // receive shift register, but not the FIFO so the FIFO contents stay valid. // It can also be cleared by writing to ICR.RORIC. -#define SSI_RIS_RORRIS 0x00000001 -#define SSI_RIS_RORRIS_BITN 0 -#define SSI_RIS_RORRIS_M 0x00000001 -#define SSI_RIS_RORRIS_S 0 +#define SSI_RIS_RORRIS 0x00000001 +#define SSI_RIS_RORRIS_BITN 0 +#define SSI_RIS_RORRIS_M 0x00000001 +#define SSI_RIS_RORRIS_S 0 //***************************************************************************** // @@ -454,10 +454,10 @@ // This field returns the masked interrupt state of transmit FIFO interrupt // which is the AND product of raw interrupt state RIS.TXRIS and the mask // setting IMSC.TXIM. -#define SSI_MIS_TXMIS 0x00000008 -#define SSI_MIS_TXMIS_BITN 3 -#define SSI_MIS_TXMIS_M 0x00000008 -#define SSI_MIS_TXMIS_S 3 +#define SSI_MIS_TXMIS 0x00000008 +#define SSI_MIS_TXMIS_BITN 3 +#define SSI_MIS_TXMIS_M 0x00000008 +#define SSI_MIS_TXMIS_S 3 // Field: [2] RXMIS // @@ -465,10 +465,10 @@ // This field returns the masked interrupt state of receive FIFO interrupt // which is the AND product of raw interrupt state RIS.RXRIS and the mask // setting IMSC.RXIM. -#define SSI_MIS_RXMIS 0x00000004 -#define SSI_MIS_RXMIS_BITN 2 -#define SSI_MIS_RXMIS_M 0x00000004 -#define SSI_MIS_RXMIS_S 2 +#define SSI_MIS_RXMIS 0x00000004 +#define SSI_MIS_RXMIS_BITN 2 +#define SSI_MIS_RXMIS_M 0x00000004 +#define SSI_MIS_RXMIS_S 2 // Field: [1] RTMIS // @@ -476,10 +476,10 @@ // This field returns the masked interrupt state of receive timeout interrupt // which is the AND product of raw interrupt state RIS.RTRIS and the mask // setting IMSC.RTIM. -#define SSI_MIS_RTMIS 0x00000002 -#define SSI_MIS_RTMIS_BITN 1 -#define SSI_MIS_RTMIS_M 0x00000002 -#define SSI_MIS_RTMIS_S 1 +#define SSI_MIS_RTMIS 0x00000002 +#define SSI_MIS_RTMIS_BITN 1 +#define SSI_MIS_RTMIS_M 0x00000002 +#define SSI_MIS_RTMIS_S 1 // Field: [0] RORMIS // @@ -487,10 +487,10 @@ // This field returns the masked interrupt state of receive overrun interrupt // which is the AND product of raw interrupt state RIS.RORRIS and the mask // setting IMSC.RORIM. -#define SSI_MIS_RORMIS 0x00000001 -#define SSI_MIS_RORMIS_BITN 0 -#define SSI_MIS_RORMIS_M 0x00000001 -#define SSI_MIS_RORMIS_S 0 +#define SSI_MIS_RORMIS 0x00000001 +#define SSI_MIS_RORMIS_BITN 0 +#define SSI_MIS_RORMIS_M 0x00000001 +#define SSI_MIS_RORMIS_S 0 //***************************************************************************** // @@ -502,20 +502,20 @@ // Clear the receive timeout interrupt: // Writing 1 to this field clears the timeout interrupt (RIS.RTRIS). Writing 0 // has no effect. -#define SSI_ICR_RTIC 0x00000002 -#define SSI_ICR_RTIC_BITN 1 -#define SSI_ICR_RTIC_M 0x00000002 -#define SSI_ICR_RTIC_S 1 +#define SSI_ICR_RTIC 0x00000002 +#define SSI_ICR_RTIC_BITN 1 +#define SSI_ICR_RTIC_M 0x00000002 +#define SSI_ICR_RTIC_S 1 // Field: [0] RORIC // // Clear the receive overrun interrupt: // Writing 1 to this field clears the overrun error interrupt (RIS.RORRIS). // Writing 0 has no effect. -#define SSI_ICR_RORIC 0x00000001 -#define SSI_ICR_RORIC_BITN 0 -#define SSI_ICR_RORIC_M 0x00000001 -#define SSI_ICR_RORIC_S 0 +#define SSI_ICR_RORIC 0x00000001 +#define SSI_ICR_RORIC_BITN 0 +#define SSI_ICR_RORIC_M 0x00000001 +#define SSI_ICR_RORIC_S 0 //***************************************************************************** // @@ -526,19 +526,18 @@ // // Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is // enabled. -#define SSI_DMACR_TXDMAE 0x00000002 -#define SSI_DMACR_TXDMAE_BITN 1 -#define SSI_DMACR_TXDMAE_M 0x00000002 -#define SSI_DMACR_TXDMAE_S 1 +#define SSI_DMACR_TXDMAE 0x00000002 +#define SSI_DMACR_TXDMAE_BITN 1 +#define SSI_DMACR_TXDMAE_M 0x00000002 +#define SSI_DMACR_TXDMAE_S 1 // Field: [0] RXDMAE // // Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is // enabled. -#define SSI_DMACR_RXDMAE 0x00000001 -#define SSI_DMACR_RXDMAE_BITN 0 -#define SSI_DMACR_RXDMAE_M 0x00000001 -#define SSI_DMACR_RXDMAE_S 0 - +#define SSI_DMACR_RXDMAE 0x00000001 +#define SSI_DMACR_RXDMAE_BITN 0 +#define SSI_DMACR_RXDMAE_M 0x00000001 +#define SSI_DMACR_RXDMAE_S 0 #endif // __SSI__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_sysctl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_sysctl.h index 1ddd6bb..9a8fada 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_sysctl.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_sysctl.h @@ -1,49 +1,47 @@ /****************************************************************************** -* Filename: hw_sysctl.h -* Revised: 2015-03-16 14:43:45 +0100 (Mon, 16 Mar 2015) -* Revision: 42989 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_sysctl.h + * Revised: 2015-03-16 14:43:45 +0100 (Mon, 16 Mar 2015) + * Revision: 42989 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_SYSCTL_H__ #define __HW_SYSCTL_H__ - //***************************************************************************** // // The following are initial defines for the MCU clock // //***************************************************************************** -#define GET_MCU_CLOCK 48000000 - +#define GET_MCU_CLOCK 48000000 #endif // __HW_SYSCTL_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_trng.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_trng.h index 21aa93c..8f07c40 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_trng.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_trng.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_trng_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_trng_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_TRNG_H__ #define __HW_TRNG_H__ @@ -44,70 +44,70 @@ // //***************************************************************************** // Random Number Lower Word Readout Value -#define TRNG_O_OUT0 0x00000000 +#define TRNG_O_OUT0 0x00000000 // Random Number Upper Word Readout Value -#define TRNG_O_OUT1 0x00000004 +#define TRNG_O_OUT1 0x00000004 // Interrupt Status -#define TRNG_O_IRQFLAGSTAT 0x00000008 +#define TRNG_O_IRQFLAGSTAT 0x00000008 // Interrupt Mask -#define TRNG_O_IRQFLAGMASK 0x0000000C +#define TRNG_O_IRQFLAGMASK 0x0000000C // Interrupt Flag Clear -#define TRNG_O_IRQFLAGCLR 0x00000010 +#define TRNG_O_IRQFLAGCLR 0x00000010 // Control -#define TRNG_O_CTL 0x00000014 +#define TRNG_O_CTL 0x00000014 // Configuration 0 -#define TRNG_O_CFG0 0x00000018 +#define TRNG_O_CFG0 0x00000018 // Alarm Control -#define TRNG_O_ALARMCNT 0x0000001C +#define TRNG_O_ALARMCNT 0x0000001C // FRO Enable -#define TRNG_O_FROEN 0x00000020 +#define TRNG_O_FROEN 0x00000020 // FRO De-tune Bit -#define TRNG_O_FRODETUNE 0x00000024 +#define TRNG_O_FRODETUNE 0x00000024 // Alarm Event -#define TRNG_O_ALARMMASK 0x00000028 +#define TRNG_O_ALARMMASK 0x00000028 // Alarm Shutdown -#define TRNG_O_ALARMSTOP 0x0000002C +#define TRNG_O_ALARMSTOP 0x0000002C // LFSR Readout Value -#define TRNG_O_LFSR0 0x00000030 +#define TRNG_O_LFSR0 0x00000030 // LFSR Readout Value -#define TRNG_O_LFSR1 0x00000034 +#define TRNG_O_LFSR1 0x00000034 // LFSR Readout Value -#define TRNG_O_LFSR2 0x00000038 +#define TRNG_O_LFSR2 0x00000038 // TRNG Engine Options Information -#define TRNG_O_HWOPT 0x00000078 +#define TRNG_O_HWOPT 0x00000078 // HW Version 0 -#define TRNG_O_HWVER0 0x0000007C +#define TRNG_O_HWVER0 0x0000007C // Interrupt Status After Masking -#define TRNG_O_IRQSTATMASK 0x00001FD8 +#define TRNG_O_IRQSTATMASK 0x00001FD8 // HW Version 1 -#define TRNG_O_HWVER1 0x00001FE0 +#define TRNG_O_HWVER1 0x00001FE0 // Interrupt Set -#define TRNG_O_IRQSET 0x00001FEC +#define TRNG_O_IRQSET 0x00001FEC // SW Reset Control -#define TRNG_O_SWRESET 0x00001FF0 +#define TRNG_O_SWRESET 0x00001FF0 // Interrupt Status -#define TRNG_O_IRQSTAT 0x00001FF8 +#define TRNG_O_IRQSTAT 0x00001FF8 //***************************************************************************** // @@ -117,9 +117,9 @@ // Field: [31:0] VALUE_31_0 // // LSW of 64- bit random value. New value ready when IRQFLAGSTAT.RDY = 1. -#define TRNG_OUT0_VALUE_31_0_W 32 -#define TRNG_OUT0_VALUE_31_0_M 0xFFFFFFFF -#define TRNG_OUT0_VALUE_31_0_S 0 +#define TRNG_OUT0_VALUE_31_0_W 32 +#define TRNG_OUT0_VALUE_31_0_M 0xFFFFFFFF +#define TRNG_OUT0_VALUE_31_0_S 0 //***************************************************************************** // @@ -129,9 +129,9 @@ // Field: [31:0] VALUE_63_32 // // MSW of 64-bit random value. New value ready when IRQFLAGSTAT.RDY = 1. -#define TRNG_OUT1_VALUE_63_32_W 32 -#define TRNG_OUT1_VALUE_63_32_M 0xFFFFFFFF -#define TRNG_OUT1_VALUE_63_32_S 0 +#define TRNG_OUT1_VALUE_63_32_W 32 +#define TRNG_OUT1_VALUE_63_32_M 0xFFFFFFFF +#define TRNG_OUT1_VALUE_63_32_S 0 //***************************************************************************** // @@ -144,10 +144,10 @@ // test modes - clocks may not be turned off and the power supply voltage must // be kept stable. // 0: TRNG is idle and can be shut down -#define TRNG_IRQFLAGSTAT_NEED_CLOCK 0x80000000 -#define TRNG_IRQFLAGSTAT_NEED_CLOCK_BITN 31 -#define TRNG_IRQFLAGSTAT_NEED_CLOCK_M 0x80000000 -#define TRNG_IRQFLAGSTAT_NEED_CLOCK_S 31 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK 0x80000000 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_BITN 31 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_M 0x80000000 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_S 31 // Field: [1] SHUTDOWN_OVF // @@ -155,10 +155,10 @@ // ALARMSTOP register) has exceeded the threshold set by ALARMCNT.SHUTDOWN_THR // // Writing '1' to IRQFLAGCLR.SHUTDOWN_OVF clears this bit to '0' again. -#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF 0x00000002 -#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_BITN 1 -#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_M 0x00000002 -#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_S 1 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_S 1 // Field: [0] RDY // @@ -169,10 +169,10 @@ // If a new number is already available in the internal register of the TRNG, // the number is directly clocked into the result register. In this case the // status bit is asserted again, after one clock cycle. -#define TRNG_IRQFLAGSTAT_RDY 0x00000001 -#define TRNG_IRQFLAGSTAT_RDY_BITN 0 -#define TRNG_IRQFLAGSTAT_RDY_M 0x00000001 -#define TRNG_IRQFLAGSTAT_RDY_S 0 +#define TRNG_IRQFLAGSTAT_RDY 0x00000001 +#define TRNG_IRQFLAGSTAT_RDY_BITN 0 +#define TRNG_IRQFLAGSTAT_RDY_M 0x00000001 +#define TRNG_IRQFLAGSTAT_RDY_S 0 //***************************************************************************** // @@ -183,18 +183,18 @@ // // 1: Allow IRQFLAGSTAT.SHUTDOWN_OVF to activate the interrupt from this // module. -#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF 0x00000002 -#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_BITN 1 -#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_M 0x00000002 -#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_S 1 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_S 1 // Field: [0] RDY // // 1: Allow IRQFLAGSTAT.RDY to activate the interrupt from this module. -#define TRNG_IRQFLAGMASK_RDY 0x00000001 -#define TRNG_IRQFLAGMASK_RDY_BITN 0 -#define TRNG_IRQFLAGMASK_RDY_M 0x00000001 -#define TRNG_IRQFLAGMASK_RDY_S 0 +#define TRNG_IRQFLAGMASK_RDY 0x00000001 +#define TRNG_IRQFLAGMASK_RDY_BITN 0 +#define TRNG_IRQFLAGMASK_RDY_M 0x00000001 +#define TRNG_IRQFLAGMASK_RDY_S 0 //***************************************************************************** // @@ -204,18 +204,18 @@ // Field: [1] SHUTDOWN_OVF // // 1: Clear IRQFLAGSTAT.SHUTDOWN_OVF. -#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF 0x00000002 -#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_BITN 1 -#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_M 0x00000002 -#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_S 1 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_S 1 // Field: [0] RDY // // 1: Clear IRQFLAGSTAT.RDY. -#define TRNG_IRQFLAGCLR_RDY 0x00000001 -#define TRNG_IRQFLAGCLR_RDY_BITN 0 -#define TRNG_IRQFLAGCLR_RDY_M 0x00000001 -#define TRNG_IRQFLAGCLR_RDY_S 0 +#define TRNG_IRQFLAGCLR_RDY 0x00000001 +#define TRNG_IRQFLAGCLR_RDY_BITN 0 +#define TRNG_IRQFLAGCLR_RDY_M 0x00000001 +#define TRNG_IRQFLAGCLR_RDY_S 0 //***************************************************************************** // @@ -241,19 +241,19 @@ // // This field can only be modified while TRNG_EN is 0. If 1 an update will be // ignored. -#define TRNG_CTL_STARTUP_CYCLES_W 16 -#define TRNG_CTL_STARTUP_CYCLES_M 0xFFFF0000 -#define TRNG_CTL_STARTUP_CYCLES_S 16 +#define TRNG_CTL_STARTUP_CYCLES_W 16 +#define TRNG_CTL_STARTUP_CYCLES_M 0xFFFF0000 +#define TRNG_CTL_STARTUP_CYCLES_S 16 // Field: [10] TRNG_EN // // 0: Forces all TRNG logic back into the idle state immediately. // 1: Starts TRNG, gathering entropy from the FROs for the number of samples // determined by STARTUP_CYCLES. -#define TRNG_CTL_TRNG_EN 0x00000400 -#define TRNG_CTL_TRNG_EN_BITN 10 -#define TRNG_CTL_TRNG_EN_M 0x00000400 -#define TRNG_CTL_TRNG_EN_S 10 +#define TRNG_CTL_TRNG_EN 0x00000400 +#define TRNG_CTL_TRNG_EN_BITN 10 +#define TRNG_CTL_TRNG_EN_M 0x00000400 +#define TRNG_CTL_TRNG_EN_S 10 // Field: [2] NO_LFSR_FB // @@ -263,10 +263,10 @@ // // This bit can only be set to '1' when TEST_MODE is also set to '1' and should // not be used for other than test purposes -#define TRNG_CTL_NO_LFSR_FB 0x00000004 -#define TRNG_CTL_NO_LFSR_FB_BITN 2 -#define TRNG_CTL_NO_LFSR_FB_M 0x00000004 -#define TRNG_CTL_NO_LFSR_FB_S 2 +#define TRNG_CTL_NO_LFSR_FB 0x00000004 +#define TRNG_CTL_NO_LFSR_FB_BITN 2 +#define TRNG_CTL_NO_LFSR_FB_M 0x00000004 +#define TRNG_CTL_NO_LFSR_FB_S 2 // Field: [1] TEST_MODE // @@ -277,10 +277,10 @@ // This bit shall not be used unless you need to change the LFSR seed prior to // creating a new random value. All other testing is done external to register // control. -#define TRNG_CTL_TEST_MODE 0x00000002 -#define TRNG_CTL_TEST_MODE_BITN 1 -#define TRNG_CTL_TEST_MODE_M 0x00000002 -#define TRNG_CTL_TEST_MODE_S 1 +#define TRNG_CTL_TEST_MODE 0x00000002 +#define TRNG_CTL_TEST_MODE_BITN 1 +#define TRNG_CTL_TEST_MODE_M 0x00000002 +#define TRNG_CTL_TEST_MODE_S 1 //***************************************************************************** // @@ -306,9 +306,9 @@ // 0xFFFF: 65535*2^8 samples // // This field can only be modified while CTL.TRNG_EN is 0. -#define TRNG_CFG0_MAX_REFILL_CYCLES_W 16 -#define TRNG_CFG0_MAX_REFILL_CYCLES_M 0xFFFF0000 -#define TRNG_CFG0_MAX_REFILL_CYCLES_S 16 +#define TRNG_CFG0_MAX_REFILL_CYCLES_W 16 +#define TRNG_CFG0_MAX_REFILL_CYCLES_M 0xFFFF0000 +#define TRNG_CFG0_MAX_REFILL_CYCLES_S 16 // Field: [11:8] SMPL_DIV // @@ -321,9 +321,9 @@ // conditions) has a cycle time less than twice the sample period. // // This field can only be modified while CTL.TRNG_EN is '0'. -#define TRNG_CFG0_SMPL_DIV_W 4 -#define TRNG_CFG0_SMPL_DIV_M 0x00000F00 -#define TRNG_CFG0_SMPL_DIV_S 8 +#define TRNG_CFG0_SMPL_DIV_W 4 +#define TRNG_CFG0_SMPL_DIV_M 0x00000F00 +#define TRNG_CFG0_SMPL_DIV_S 8 // Field: [7:0] MIN_REFILL_CYCLES // @@ -345,9 +345,9 @@ // 0x02: 2*2^6 samples // ... // 0xFF: 255*2^6 samples -#define TRNG_CFG0_MIN_REFILL_CYCLES_W 8 -#define TRNG_CFG0_MIN_REFILL_CYCLES_M 0x000000FF -#define TRNG_CFG0_MIN_REFILL_CYCLES_S 0 +#define TRNG_CFG0_MIN_REFILL_CYCLES_W 8 +#define TRNG_CFG0_MIN_REFILL_CYCLES_M 0x000000FF +#define TRNG_CFG0_MIN_REFILL_CYCLES_S 0 //***************************************************************************** // @@ -358,17 +358,17 @@ // // Read-only, indicates the number of '1' bits in ALARMSTOP register. // The maximum value equals the number of FROs. -#define TRNG_ALARMCNT_SHUTDOWN_CNT_W 6 -#define TRNG_ALARMCNT_SHUTDOWN_CNT_M 0x3F000000 -#define TRNG_ALARMCNT_SHUTDOWN_CNT_S 24 +#define TRNG_ALARMCNT_SHUTDOWN_CNT_W 6 +#define TRNG_ALARMCNT_SHUTDOWN_CNT_M 0x3F000000 +#define TRNG_ALARMCNT_SHUTDOWN_CNT_S 24 // Field: [20:16] SHUTDOWN_THR // // Threshold setting for generating IRQFLAGSTAT.SHUTDOWN_OVF interrupt. The // interrupt is triggered when SHUTDOWN_CNT value exceeds this bit field. -#define TRNG_ALARMCNT_SHUTDOWN_THR_W 5 -#define TRNG_ALARMCNT_SHUTDOWN_THR_M 0x001F0000 -#define TRNG_ALARMCNT_SHUTDOWN_THR_S 16 +#define TRNG_ALARMCNT_SHUTDOWN_THR_W 5 +#define TRNG_ALARMCNT_SHUTDOWN_THR_M 0x001F0000 +#define TRNG_ALARMCNT_SHUTDOWN_THR_S 16 // Field: [7:0] ALARM_THR // @@ -377,9 +377,9 @@ // samples length) is detected continuously for the number of samples defined // by this field's value. Reset value 0xFF should keep the number of 'alarm // events' to a manageable level. -#define TRNG_ALARMCNT_ALARM_THR_W 8 -#define TRNG_ALARMCNT_ALARM_THR_M 0x000000FF -#define TRNG_ALARMCNT_ALARM_THR_S 0 +#define TRNG_ALARMCNT_ALARM_THR_W 8 +#define TRNG_ALARMCNT_ALARM_THR_M 0x000000FF +#define TRNG_ALARMCNT_ALARM_THR_S 0 //***************************************************************************** // @@ -394,9 +394,9 @@ // // Bits are automatically forced to '0' here (and cannot be written to '1') // while the corresponding bit in ALARMSTOP.FRO_FLAGS has value '1'. -#define TRNG_FROEN_FRO_MASK_W 24 -#define TRNG_FROEN_FRO_MASK_M 0x00FFFFFF -#define TRNG_FROEN_FRO_MASK_S 0 +#define TRNG_FROEN_FRO_MASK_W 24 +#define TRNG_FROEN_FRO_MASK_M 0x00FFFFFF +#define TRNG_FROEN_FRO_MASK_S 0 //***************************************************************************** // @@ -410,9 +410,9 @@ // while the corresponding FRO is turned off (by temporarily writing a '0' in // the corresponding // bit of the FROEN.FRO_MASK register). -#define TRNG_FRODETUNE_FRO_MASK_W 24 -#define TRNG_FRODETUNE_FRO_MASK_M 0x00FFFFFF -#define TRNG_FRODETUNE_FRO_MASK_S 0 +#define TRNG_FRODETUNE_FRO_MASK_W 24 +#define TRNG_FRODETUNE_FRO_MASK_M 0x00FFFFFF +#define TRNG_FRODETUNE_FRO_MASK_S 0 //***************************************************************************** // @@ -423,9 +423,9 @@ // // Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] // indicates FRO 'n' experienced an 'alarm event'. -#define TRNG_ALARMMASK_FRO_MASK_W 24 -#define TRNG_ALARMMASK_FRO_MASK_M 0x00FFFFFF -#define TRNG_ALARMMASK_FRO_MASK_S 0 +#define TRNG_ALARMMASK_FRO_MASK_W 24 +#define TRNG_ALARMMASK_FRO_MASK_M 0x00FFFFFF +#define TRNG_ALARMMASK_FRO_MASK_S 0 //***************************************************************************** // @@ -438,9 +438,9 @@ // indicates FRO 'n' experienced more than one 'alarm event' in quick // succession and has been turned off. A '1' in this field forces the // corresponding bit in FROEN.FRO_MASK to '0'. -#define TRNG_ALARMSTOP_FRO_FLAGS_W 24 -#define TRNG_ALARMSTOP_FRO_FLAGS_M 0x00FFFFFF -#define TRNG_ALARMSTOP_FRO_FLAGS_S 0 +#define TRNG_ALARMSTOP_FRO_FLAGS_W 24 +#define TRNG_ALARMSTOP_FRO_FLAGS_M 0x00FFFFFF +#define TRNG_ALARMSTOP_FRO_FLAGS_S 0 //***************************************************************************** // @@ -452,9 +452,9 @@ // Bits [31:0] of the main entropy accumulation LFSR. Register can only be // accessed when CTL.TEST_MODE = 1. // Register contents will be cleared to zero before access is enabled. -#define TRNG_LFSR0_LFSR_31_0_W 32 -#define TRNG_LFSR0_LFSR_31_0_M 0xFFFFFFFF -#define TRNG_LFSR0_LFSR_31_0_S 0 +#define TRNG_LFSR0_LFSR_31_0_W 32 +#define TRNG_LFSR0_LFSR_31_0_M 0xFFFFFFFF +#define TRNG_LFSR0_LFSR_31_0_S 0 //***************************************************************************** // @@ -466,9 +466,9 @@ // Bits [63:32] of the main entropy accumulation LFSR. Register can only be // accessed when CTL.TEST_MODE = 1. // Register contents will be cleared to zero before access is enabled. -#define TRNG_LFSR1_LFSR_63_32_W 32 -#define TRNG_LFSR1_LFSR_63_32_M 0xFFFFFFFF -#define TRNG_LFSR1_LFSR_63_32_S 0 +#define TRNG_LFSR1_LFSR_63_32_W 32 +#define TRNG_LFSR1_LFSR_63_32_M 0xFFFFFFFF +#define TRNG_LFSR1_LFSR_63_32_S 0 //***************************************************************************** // @@ -480,9 +480,9 @@ // Bits [80:64] of the main entropy accumulation LFSR. Register can only be // accessed when CTL.TEST_MODE = 1. // Register contents will be cleared to zero before access is enabled. -#define TRNG_LFSR2_LFSR_80_64_W 17 -#define TRNG_LFSR2_LFSR_80_64_M 0x0001FFFF -#define TRNG_LFSR2_LFSR_80_64_S 0 +#define TRNG_LFSR2_LFSR_80_64_W 17 +#define TRNG_LFSR2_LFSR_80_64_M 0x0001FFFF +#define TRNG_LFSR2_LFSR_80_64_S 0 //***************************************************************************** // @@ -492,9 +492,9 @@ // Field: [11:6] NR_OF_FROS // // Number of FROs implemented in this TRNG, value 24 (decimal). -#define TRNG_HWOPT_NR_OF_FROS_W 6 -#define TRNG_HWOPT_NR_OF_FROS_M 0x00000FC0 -#define TRNG_HWOPT_NR_OF_FROS_S 6 +#define TRNG_HWOPT_NR_OF_FROS_W 6 +#define TRNG_HWOPT_NR_OF_FROS_M 0x00000FC0 +#define TRNG_HWOPT_NR_OF_FROS_S 6 //***************************************************************************** // @@ -504,38 +504,38 @@ // Field: [27:24] HW_MAJOR_VER // // 4 bits binary encoding of the major hardware revision number. -#define TRNG_HWVER0_HW_MAJOR_VER_W 4 -#define TRNG_HWVER0_HW_MAJOR_VER_M 0x0F000000 -#define TRNG_HWVER0_HW_MAJOR_VER_S 24 +#define TRNG_HWVER0_HW_MAJOR_VER_W 4 +#define TRNG_HWVER0_HW_MAJOR_VER_M 0x0F000000 +#define TRNG_HWVER0_HW_MAJOR_VER_S 24 // Field: [23:20] HW_MINOR_VER // // 4 bits binary encoding of the minor hardware revision number. -#define TRNG_HWVER0_HW_MINOR_VER_W 4 -#define TRNG_HWVER0_HW_MINOR_VER_M 0x00F00000 -#define TRNG_HWVER0_HW_MINOR_VER_S 20 +#define TRNG_HWVER0_HW_MINOR_VER_W 4 +#define TRNG_HWVER0_HW_MINOR_VER_M 0x00F00000 +#define TRNG_HWVER0_HW_MINOR_VER_S 20 // Field: [19:16] HW_PATCH_LVL // // 4 bits binary encoding of the hardware patch level, initial release will // carry value zero. -#define TRNG_HWVER0_HW_PATCH_LVL_W 4 -#define TRNG_HWVER0_HW_PATCH_LVL_M 0x000F0000 -#define TRNG_HWVER0_HW_PATCH_LVL_S 16 +#define TRNG_HWVER0_HW_PATCH_LVL_W 4 +#define TRNG_HWVER0_HW_PATCH_LVL_M 0x000F0000 +#define TRNG_HWVER0_HW_PATCH_LVL_S 16 // Field: [15:8] EIP_NUM_COMPL // // Bit-by-bit logic complement of bits [7:0]. This TRNG gives 0xB4. -#define TRNG_HWVER0_EIP_NUM_COMPL_W 8 -#define TRNG_HWVER0_EIP_NUM_COMPL_M 0x0000FF00 -#define TRNG_HWVER0_EIP_NUM_COMPL_S 8 +#define TRNG_HWVER0_EIP_NUM_COMPL_W 8 +#define TRNG_HWVER0_EIP_NUM_COMPL_M 0x0000FF00 +#define TRNG_HWVER0_EIP_NUM_COMPL_S 8 // Field: [7:0] EIP_NUM // // 8 bits binary encoding of the module number. This TRNG gives 0x4B. -#define TRNG_HWVER0_EIP_NUM_W 8 -#define TRNG_HWVER0_EIP_NUM_M 0x000000FF -#define TRNG_HWVER0_EIP_NUM_S 0 +#define TRNG_HWVER0_EIP_NUM_W 8 +#define TRNG_HWVER0_EIP_NUM_M 0x000000FF +#define TRNG_HWVER0_EIP_NUM_S 0 //***************************************************************************** // @@ -546,19 +546,19 @@ // // Shutdown Overflow (result of IRQFLAGSTAT.SHUTDOWN_OVF AND'ed with // IRQFLAGMASK.SHUTDOWN_OVF) -#define TRNG_IRQSTATMASK_SHUTDOWN_OVF 0x00000002 -#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_BITN 1 -#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_M 0x00000002 -#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_S 1 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_S 1 // Field: [0] RDY // // New random value available (result of IRQFLAGSTAT.RDY AND'ed with // IRQFLAGMASK.RDY) -#define TRNG_IRQSTATMASK_RDY 0x00000001 -#define TRNG_IRQSTATMASK_RDY_BITN 0 -#define TRNG_IRQSTATMASK_RDY_M 0x00000001 -#define TRNG_IRQSTATMASK_RDY_S 0 +#define TRNG_IRQSTATMASK_RDY 0x00000001 +#define TRNG_IRQSTATMASK_RDY_BITN 0 +#define TRNG_IRQSTATMASK_RDY_M 0x00000001 +#define TRNG_IRQSTATMASK_RDY_S 0 //***************************************************************************** // @@ -568,9 +568,9 @@ // Field: [7:0] REV // // The revision number of this module is Rev 2.0. -#define TRNG_HWVER1_REV_W 8 -#define TRNG_HWVER1_REV_M 0x000000FF -#define TRNG_HWVER1_REV_S 0 +#define TRNG_HWVER1_REV_W 8 +#define TRNG_HWVER1_REV_M 0x000000FF +#define TRNG_HWVER1_REV_S 0 //***************************************************************************** // @@ -586,10 +586,10 @@ // // Write '1' to soft reset , reset will be low for 4-5 clock cycles. Poll to 0 // for reset to be completed. -#define TRNG_SWRESET_RESET 0x00000001 -#define TRNG_SWRESET_RESET_BITN 0 -#define TRNG_SWRESET_RESET_M 0x00000001 -#define TRNG_SWRESET_RESET_S 0 +#define TRNG_SWRESET_RESET 0x00000001 +#define TRNG_SWRESET_RESET_BITN 0 +#define TRNG_SWRESET_RESET_M 0x00000001 +#define TRNG_SWRESET_RESET_S 0 //***************************************************************************** // @@ -600,10 +600,9 @@ // // TRNG Interrupt status. OR'ed version of IRQFLAGSTAT.SHUTDOWN_OVF and // IRQFLAGSTAT.RDY -#define TRNG_IRQSTAT_STAT 0x00000001 -#define TRNG_IRQSTAT_STAT_BITN 0 -#define TRNG_IRQSTAT_STAT_M 0x00000001 -#define TRNG_IRQSTAT_STAT_S 0 - +#define TRNG_IRQSTAT_STAT 0x00000001 +#define TRNG_IRQSTAT_STAT_BITN 0 +#define TRNG_IRQSTAT_STAT_M 0x00000001 +#define TRNG_IRQSTAT_STAT_S 0 #endif // __TRNG__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_types.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_types.h index 142601b..c92d027 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_types.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_types.h @@ -1,55 +1,55 @@ /****************************************************************************** -* Filename: hw_types.h -* Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) -* Revision: 47152 -* -* Description: Common types and macros. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_types.h + * Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) + * Revision: 47152 + * + * Description: Common types and macros. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_TYPES_H__ #define __HW_TYPES_H__ -#include -#include #include "../inc/hw_chip_def.h" +#include +#include //***************************************************************************** // // Common driverlib types // //***************************************************************************** -typedef void (* FPTR_VOID_VOID_T) (void); -typedef void (* FPTR_VOID_UINT8_T) (uint8_t); +typedef void (*FPTR_VOID_VOID_T)(void); +typedef void (*FPTR_VOID_UINT8_T)(uint8_t); //***************************************************************************** // @@ -58,7 +58,7 @@ typedef void (* FPTR_VOID_UINT8_T) (uint8_t); // //***************************************************************************** #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline +#define __STATIC_INLINE static inline #endif //***************************************************************************** @@ -66,7 +66,7 @@ typedef void (* FPTR_VOID_UINT8_T) (uint8_t); // C99 types only allows bitfield defintions on certain datatypes. // //***************************************************************************** -typedef unsigned int __UINT32; +typedef unsigned int __UINT32; //***************************************************************************** // @@ -79,19 +79,19 @@ typedef unsigned int __UINT32; // Word (32 bit) access to address x // Read example : my32BitVar = HWREG(base_addr + offset) ; // Write example : HWREG(base_addr + offset) = my32BitVar ; -#define HWREG(x) \ +#define HWREG(x) \ (*((volatile unsigned long *)(x))) // Half word (16 bit) access to address x // Read example : my16BitVar = HWREGH(base_addr + offset) ; // Write example : HWREGH(base_addr + offset) = my16BitVar ; -#define HWREGH(x) \ +#define HWREGH(x) \ (*((volatile unsigned short *)(x))) // Byte (8 bit) access to address x // Read example : my8BitVar = HWREGB(base_addr + offset) ; // Write example : HWREGB(base_addr + offset) = my8BitVar ; -#define HWREGB(x) \ +#define HWREGB(x) \ (*((volatile unsigned char *)(x))) //***************************************************************************** @@ -105,19 +105,18 @@ typedef unsigned int __UINT32; // //***************************************************************************** // Bit-band access to address x bit number b using word access (32 bit) -#define HWREGBITW(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) // Bit-band access to address x bit number b using half word access (16 bit) -#define HWREGBITH(x, b) \ - HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) // Bit-band access to address x bit number b using byte access (8 bit) -#define HWREGBITB(x, b) \ - HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - #endif // __HW_TYPES_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_uart.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_uart.h index 05c49a7..69e23ff 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_uart.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_uart.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_uart_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_uart_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_UART_H__ #define __HW_UART_H__ @@ -44,46 +44,46 @@ // //***************************************************************************** // Data -#define UART_O_DR 0x00000000 +#define UART_O_DR 0x00000000 // Status -#define UART_O_RSR 0x00000004 +#define UART_O_RSR 0x00000004 // Error Clear -#define UART_O_ECR 0x00000004 +#define UART_O_ECR 0x00000004 // Flag -#define UART_O_FR 0x00000018 +#define UART_O_FR 0x00000018 // Integer Baud-Rate Divisor -#define UART_O_IBRD 0x00000024 +#define UART_O_IBRD 0x00000024 // Fractional Baud-Rate Divisor -#define UART_O_FBRD 0x00000028 +#define UART_O_FBRD 0x00000028 // Line Control -#define UART_O_LCRH 0x0000002C +#define UART_O_LCRH 0x0000002C // Control -#define UART_O_CTL 0x00000030 +#define UART_O_CTL 0x00000030 // Interrupt FIFO Level Select -#define UART_O_IFLS 0x00000034 +#define UART_O_IFLS 0x00000034 // Interrupt Mask Set/Clear -#define UART_O_IMSC 0x00000038 +#define UART_O_IMSC 0x00000038 // Raw Interrupt Status -#define UART_O_RIS 0x0000003C +#define UART_O_RIS 0x0000003C // Masked Interrupt Status -#define UART_O_MIS 0x00000040 +#define UART_O_MIS 0x00000040 // Interrupt Clear -#define UART_O_ICR 0x00000044 +#define UART_O_ICR 0x00000044 // DMA Control -#define UART_O_DMACTL 0x00000048 +#define UART_O_DMACTL 0x00000048 //***************************************************************************** // @@ -98,10 +98,10 @@ // the FIFO is full, , only the contents of the shift register are overwritten. // This is cleared to 0 once there is an empty space in the FIFO and a new // character can be written to it. -#define UART_DR_OE 0x00000800 -#define UART_DR_OE_BITN 11 -#define UART_DR_OE_M 0x00000800 -#define UART_DR_OE_S 11 +#define UART_DR_OE 0x00000800 +#define UART_DR_OE_BITN 11 +#define UART_DR_OE_M 0x00000800 +#define UART_DR_OE_S 11 // Field: [10] BE // @@ -114,10 +114,10 @@ // break occurs, a 0 character is loaded into the FIFO. The next character is // enabled after the receive data input (UARTRXD input pin) goes to a 1 // (marking state), and the next valid start bit is received. -#define UART_DR_BE 0x00000400 -#define UART_DR_BE_BITN 10 -#define UART_DR_BE_M 0x00000400 -#define UART_DR_BE_S 10 +#define UART_DR_BE 0x00000400 +#define UART_DR_BE_BITN 10 +#define UART_DR_BE_M 0x00000400 +#define UART_DR_BE_S 10 // Field: [9] PE // @@ -126,10 +126,10 @@ // does not match the parity that the LCRH.EPS and LCRH.SPS select. // In FIFO mode, this error is associated with the character at the top of the // FIFO (i.e., the oldest received data character since last read). -#define UART_DR_PE 0x00000200 -#define UART_DR_PE_BITN 9 -#define UART_DR_PE_M 0x00000200 -#define UART_DR_PE_S 9 +#define UART_DR_PE 0x00000200 +#define UART_DR_PE_BITN 9 +#define UART_DR_PE_M 0x00000200 +#define UART_DR_PE_S 9 // Field: [8] FE // @@ -138,10 +138,10 @@ // stop bit (a valid stop bit is 1). // In FIFO mode, this error is associated with the character at the top of the // FIFO (i.e., the oldest received data character since last read). -#define UART_DR_FE 0x00000100 -#define UART_DR_FE_BITN 8 -#define UART_DR_FE_M 0x00000100 -#define UART_DR_FE_S 8 +#define UART_DR_FE 0x00000100 +#define UART_DR_FE_BITN 8 +#define UART_DR_FE_M 0x00000100 +#define UART_DR_FE_S 8 // Field: [7:0] DATA // @@ -149,9 +149,9 @@ // On writes, the transmit data character is pushed into the FIFO. // On reads, the oldest received data character since the last read is // returned. -#define UART_DR_DATA_W 8 -#define UART_DR_DATA_M 0x000000FF -#define UART_DR_DATA_S 0 +#define UART_DR_DATA_W 8 +#define UART_DR_DATA_M 0x000000FF +#define UART_DR_DATA_S 0 //***************************************************************************** // @@ -166,10 +166,10 @@ // the FIFO is full, , only the contents of the shift register are overwritten. // This is cleared to 0 once there is an empty space in the FIFO and a new // character can be written to it. -#define UART_RSR_OE 0x00000008 -#define UART_RSR_OE_BITN 3 -#define UART_RSR_OE_M 0x00000008 -#define UART_RSR_OE_S 3 +#define UART_RSR_OE 0x00000008 +#define UART_RSR_OE_BITN 3 +#define UART_RSR_OE_M 0x00000008 +#define UART_RSR_OE_S 3 // Field: [2] BE // @@ -180,30 +180,30 @@ // When a break occurs, a 0 character is loaded into the FIFO. The next // character is enabled after the receive data input (UARTRXD input pin) goes // to a 1 (marking state), and the next valid start bit is received. -#define UART_RSR_BE 0x00000004 -#define UART_RSR_BE_BITN 2 -#define UART_RSR_BE_M 0x00000004 -#define UART_RSR_BE_S 2 +#define UART_RSR_BE 0x00000004 +#define UART_RSR_BE_BITN 2 +#define UART_RSR_BE_M 0x00000004 +#define UART_RSR_BE_S 2 // Field: [1] PE // // UART Parity Error: // When set to 1, it indicates that the parity of the received data character // does not match the parity that the LCRH.EPS and LCRH.SPS select. -#define UART_RSR_PE 0x00000002 -#define UART_RSR_PE_BITN 1 -#define UART_RSR_PE_M 0x00000002 -#define UART_RSR_PE_S 1 +#define UART_RSR_PE 0x00000002 +#define UART_RSR_PE_BITN 1 +#define UART_RSR_PE_M 0x00000002 +#define UART_RSR_PE_S 1 // Field: [0] FE // // UART Framing Error: // When set to 1, it indicates that the received character did not have a valid // stop bit (a valid stop bit is 1). -#define UART_RSR_FE 0x00000001 -#define UART_RSR_FE_BITN 0 -#define UART_RSR_FE_M 0x00000001 -#define UART_RSR_FE_S 0 +#define UART_RSR_FE 0x00000001 +#define UART_RSR_FE_BITN 0 +#define UART_RSR_FE_M 0x00000001 +#define UART_RSR_FE_S 0 //***************************************************************************** // @@ -214,37 +214,37 @@ // // The framing (FE), parity (PE), break (BE) and overrun (OE) errors are // cleared to 0 by any write to this register. -#define UART_ECR_OE 0x00000008 -#define UART_ECR_OE_BITN 3 -#define UART_ECR_OE_M 0x00000008 -#define UART_ECR_OE_S 3 +#define UART_ECR_OE 0x00000008 +#define UART_ECR_OE_BITN 3 +#define UART_ECR_OE_M 0x00000008 +#define UART_ECR_OE_S 3 // Field: [2] BE // // The framing (FE), parity (PE), break (BE) and overrun (OE) errors are // cleared to 0 by any write to this register. -#define UART_ECR_BE 0x00000004 -#define UART_ECR_BE_BITN 2 -#define UART_ECR_BE_M 0x00000004 -#define UART_ECR_BE_S 2 +#define UART_ECR_BE 0x00000004 +#define UART_ECR_BE_BITN 2 +#define UART_ECR_BE_M 0x00000004 +#define UART_ECR_BE_S 2 // Field: [1] PE // // The framing (FE), parity (PE), break (BE) and overrun (OE) errors are // cleared to 0 by any write to this register. -#define UART_ECR_PE 0x00000002 -#define UART_ECR_PE_BITN 1 -#define UART_ECR_PE_M 0x00000002 -#define UART_ECR_PE_S 1 +#define UART_ECR_PE 0x00000002 +#define UART_ECR_PE_BITN 1 +#define UART_ECR_PE_M 0x00000002 +#define UART_ECR_PE_S 1 // Field: [0] FE // // The framing (FE), parity (PE), break (BE) and overrun (OE) errors are // cleared to 0 by any write to this register. -#define UART_ECR_FE 0x00000001 -#define UART_ECR_FE_BITN 0 -#define UART_ECR_FE_M 0x00000001 -#define UART_ECR_FE_S 0 +#define UART_ECR_FE 0x00000001 +#define UART_ECR_FE_BITN 0 +#define UART_ECR_FE_M 0x00000001 +#define UART_ECR_FE_S 0 //***************************************************************************** // @@ -259,10 +259,10 @@ // register is empty. // - If the FIFO is enabled, this bit is set when the transmit FIFO is empty. // This bit does not indicate if there is data in the transmit shift register. -#define UART_FR_TXFE 0x00000080 -#define UART_FR_TXFE_BITN 7 -#define UART_FR_TXFE_M 0x00000080 -#define UART_FR_TXFE_S 7 +#define UART_FR_TXFE 0x00000080 +#define UART_FR_TXFE_BITN 7 +#define UART_FR_TXFE_M 0x00000080 +#define UART_FR_TXFE_S 7 // Field: [6] RXFF // @@ -271,10 +271,10 @@ // - If the FIFO is disabled, this bit is set when the receive holding // register is full. // - If the FIFO is enabled, this bit is set when the receive FIFO is full. -#define UART_FR_RXFF 0x00000040 -#define UART_FR_RXFF_BITN 6 -#define UART_FR_RXFF_M 0x00000040 -#define UART_FR_RXFF_S 6 +#define UART_FR_RXFF 0x00000040 +#define UART_FR_RXFF_BITN 6 +#define UART_FR_RXFF_M 0x00000040 +#define UART_FR_RXFF_S 6 // Field: [5] TXFF // @@ -284,10 +284,10 @@ // - If the FIFO is disabled, this bit is set when the transmit holding // register is full. // - If the FIFO is enabled, this bit is set when the transmit FIFO is full. -#define UART_FR_TXFF 0x00000020 -#define UART_FR_TXFF_BITN 5 -#define UART_FR_TXFF_M 0x00000020 -#define UART_FR_TXFF_S 5 +#define UART_FR_TXFF 0x00000020 +#define UART_FR_TXFF_BITN 5 +#define UART_FR_TXFF_M 0x00000020 +#define UART_FR_TXFF_S 5 // Field: [4] RXFE // @@ -297,10 +297,10 @@ // - If the FIFO is disabled, this bit is set when the receive holding // register is empty. // - If the FIFO is enabled, this bit is set when the receive FIFO is empty. -#define UART_FR_RXFE 0x00000010 -#define UART_FR_RXFE_BITN 4 -#define UART_FR_RXFE_M 0x00000010 -#define UART_FR_RXFE_S 4 +#define UART_FR_RXFE 0x00000010 +#define UART_FR_RXFE_BITN 4 +#define UART_FR_RXFE_M 0x00000010 +#define UART_FR_RXFE_S 4 // Field: [3] BUSY // @@ -310,20 +310,20 @@ // sent from the shift register. // This bit is set as soon as the transmit FIFO becomes non-empty, regardless // of whether the UART is enabled or not. -#define UART_FR_BUSY 0x00000008 -#define UART_FR_BUSY_BITN 3 -#define UART_FR_BUSY_M 0x00000008 -#define UART_FR_BUSY_S 3 +#define UART_FR_BUSY 0x00000008 +#define UART_FR_BUSY_BITN 3 +#define UART_FR_BUSY_M 0x00000008 +#define UART_FR_BUSY_S 3 // Field: [0] CTS // // Clear To Send: // This bit is the complement of the active-low UART CTS input pin. // That is, the bit is 1 when CTS input pin is LOW. -#define UART_FR_CTS 0x00000001 -#define UART_FR_CTS_BITN 0 -#define UART_FR_CTS_M 0x00000001 -#define UART_FR_CTS_S 0 +#define UART_FR_CTS 0x00000001 +#define UART_FR_CTS_BITN 0 +#define UART_FR_CTS_M 0x00000001 +#define UART_FR_CTS_S 0 //***************************************************************************** // @@ -341,9 +341,9 @@ // illegal. // A valid value must be written to this field before the UART can be used for // RX or TX operations. -#define UART_IBRD_DIVINT_W 16 -#define UART_IBRD_DIVINT_M 0x0000FFFF -#define UART_IBRD_DIVINT_S 0 +#define UART_IBRD_DIVINT_W 16 +#define UART_IBRD_DIVINT_M 0x0000FFFF +#define UART_IBRD_DIVINT_S 0 //***************************************************************************** // @@ -361,9 +361,9 @@ // illegal. // A valid value must be written to this field before the UART can be used for // RX or TX operations. -#define UART_FBRD_DIVFRAC_W 6 -#define UART_FBRD_DIVFRAC_M 0x0000003F -#define UART_FBRD_DIVFRAC_S 0 +#define UART_FBRD_DIVFRAC_W 6 +#define UART_FBRD_DIVFRAC_M 0x0000003F +#define UART_FBRD_DIVFRAC_S 0 //***************************************************************************** // @@ -379,10 +379,10 @@ // the parity bit is transmitted and checked as 1 when EPS = 0). // // This bit has no effect when PEN disables parity checking and generation. -#define UART_LCRH_SPS 0x00000080 -#define UART_LCRH_SPS_BITN 7 -#define UART_LCRH_SPS_M 0x00000080 -#define UART_LCRH_SPS_S 7 +#define UART_LCRH_SPS 0x00000080 +#define UART_LCRH_SPS_BITN 7 +#define UART_LCRH_SPS_M 0x00000080 +#define UART_LCRH_SPS_S 7 // Field: [6:5] WLEN // @@ -394,13 +394,13 @@ // 7 Word Length 7 bits // 6 Word Length 6 bits // 5 Word Length 5 bits -#define UART_LCRH_WLEN_W 2 -#define UART_LCRH_WLEN_M 0x00000060 -#define UART_LCRH_WLEN_S 5 -#define UART_LCRH_WLEN_8 0x00000060 -#define UART_LCRH_WLEN_7 0x00000040 -#define UART_LCRH_WLEN_6 0x00000020 -#define UART_LCRH_WLEN_5 0x00000000 +#define UART_LCRH_WLEN_W 2 +#define UART_LCRH_WLEN_M 0x00000060 +#define UART_LCRH_WLEN_S 5 +#define UART_LCRH_WLEN_8 0x00000060 +#define UART_LCRH_WLEN_7 0x00000040 +#define UART_LCRH_WLEN_6 0x00000020 +#define UART_LCRH_WLEN_5 0x00000000 // Field: [4] FEN // @@ -410,22 +410,22 @@ // (FIFO mode) // DIS FIFOs are disabled (character mode) that is, the // FIFOs become 1-byte-deep holding registers. -#define UART_LCRH_FEN 0x00000010 -#define UART_LCRH_FEN_BITN 4 -#define UART_LCRH_FEN_M 0x00000010 -#define UART_LCRH_FEN_S 4 -#define UART_LCRH_FEN_EN 0x00000010 -#define UART_LCRH_FEN_DIS 0x00000000 +#define UART_LCRH_FEN 0x00000010 +#define UART_LCRH_FEN_BITN 4 +#define UART_LCRH_FEN_M 0x00000010 +#define UART_LCRH_FEN_S 4 +#define UART_LCRH_FEN_EN 0x00000010 +#define UART_LCRH_FEN_DIS 0x00000000 // Field: [3] STP2 // // UART Two Stop Bits Select: // If this bit is set to 1, two stop bits are transmitted at the end of the // frame. The receive logic does not check for two stop bits being received. -#define UART_LCRH_STP2 0x00000008 -#define UART_LCRH_STP2_BITN 3 -#define UART_LCRH_STP2_M 0x00000008 -#define UART_LCRH_STP2_S 3 +#define UART_LCRH_STP2 0x00000008 +#define UART_LCRH_STP2_BITN 3 +#define UART_LCRH_STP2_M 0x00000008 +#define UART_LCRH_STP2_S 3 // Field: [2] EPS // @@ -435,12 +435,12 @@ // even number of 1s in the data and parity bits. // ODD Odd parity: The UART generates or checks for an // odd number of 1s in the data and parity bits. -#define UART_LCRH_EPS 0x00000004 -#define UART_LCRH_EPS_BITN 2 -#define UART_LCRH_EPS_M 0x00000004 -#define UART_LCRH_EPS_S 2 -#define UART_LCRH_EPS_EVEN 0x00000004 -#define UART_LCRH_EPS_ODD 0x00000000 +#define UART_LCRH_EPS 0x00000004 +#define UART_LCRH_EPS_BITN 2 +#define UART_LCRH_EPS_M 0x00000004 +#define UART_LCRH_EPS_S 2 +#define UART_LCRH_EPS_EVEN 0x00000004 +#define UART_LCRH_EPS_ODD 0x00000000 // Field: [1] PEN // @@ -450,12 +450,12 @@ // EN Parity checking and generation is enabled. // DIS Parity is disabled and no parity bit is added to // the data frame -#define UART_LCRH_PEN 0x00000002 -#define UART_LCRH_PEN_BITN 1 -#define UART_LCRH_PEN_M 0x00000002 -#define UART_LCRH_PEN_S 1 -#define UART_LCRH_PEN_EN 0x00000002 -#define UART_LCRH_PEN_DIS 0x00000000 +#define UART_LCRH_PEN 0x00000002 +#define UART_LCRH_PEN_BITN 1 +#define UART_LCRH_PEN_M 0x00000002 +#define UART_LCRH_PEN_S 1 +#define UART_LCRH_PEN_EN 0x00000002 +#define UART_LCRH_PEN_DIS 0x00000000 // Field: [0] BRK // @@ -465,10 +465,10 @@ // proper execution of the break command, the // software must set this bit for at least two complete frames. For normal use, // this bit must be cleared to 0. -#define UART_LCRH_BRK 0x00000001 -#define UART_LCRH_BRK_BITN 0 -#define UART_LCRH_BRK_M 0x00000001 -#define UART_LCRH_BRK_S 0 +#define UART_LCRH_BRK 0x00000001 +#define UART_LCRH_BRK_BITN 0 +#define UART_LCRH_BRK_M 0x00000001 +#define UART_LCRH_BRK_S 0 //***************************************************************************** // @@ -481,12 +481,12 @@ // ENUMs: // EN CTS hardware flow control enabled // DIS CTS hardware flow control disabled -#define UART_CTL_CTSEN 0x00008000 -#define UART_CTL_CTSEN_BITN 15 -#define UART_CTL_CTSEN_M 0x00008000 -#define UART_CTL_CTSEN_S 15 -#define UART_CTL_CTSEN_EN 0x00008000 -#define UART_CTL_CTSEN_DIS 0x00000000 +#define UART_CTL_CTSEN 0x00008000 +#define UART_CTL_CTSEN_BITN 15 +#define UART_CTL_CTSEN_M 0x00008000 +#define UART_CTL_CTSEN_S 15 +#define UART_CTL_CTSEN_EN 0x00008000 +#define UART_CTL_CTSEN_DIS 0x00000000 // Field: [14] RTSEN // @@ -494,22 +494,22 @@ // ENUMs: // EN RTS hardware flow control enabled // DIS RTS hardware flow control disabled -#define UART_CTL_RTSEN 0x00004000 -#define UART_CTL_RTSEN_BITN 14 -#define UART_CTL_RTSEN_M 0x00004000 -#define UART_CTL_RTSEN_S 14 -#define UART_CTL_RTSEN_EN 0x00004000 -#define UART_CTL_RTSEN_DIS 0x00000000 +#define UART_CTL_RTSEN 0x00004000 +#define UART_CTL_RTSEN_BITN 14 +#define UART_CTL_RTSEN_M 0x00004000 +#define UART_CTL_RTSEN_S 14 +#define UART_CTL_RTSEN_EN 0x00004000 +#define UART_CTL_RTSEN_DIS 0x00000000 // Field: [11] RTS // // Request to Send // This bit is the complement of the active-low UART RTS output. That is, when // the bit is programmed to a 1 then RTS output on the pins is LOW. -#define UART_CTL_RTS 0x00000800 -#define UART_CTL_RTS_BITN 11 -#define UART_CTL_RTS_M 0x00000800 -#define UART_CTL_RTS_S 11 +#define UART_CTL_RTS 0x00000800 +#define UART_CTL_RTS_BITN 11 +#define UART_CTL_RTS_M 0x00000800 +#define UART_CTL_RTS_S 11 // Field: [9] RXE // @@ -519,12 +519,12 @@ // ENUMs: // EN UART Receive enabled // DIS UART Receive disabled -#define UART_CTL_RXE 0x00000200 -#define UART_CTL_RXE_BITN 9 -#define UART_CTL_RXE_M 0x00000200 -#define UART_CTL_RXE_S 9 -#define UART_CTL_RXE_EN 0x00000200 -#define UART_CTL_RXE_DIS 0x00000000 +#define UART_CTL_RXE 0x00000200 +#define UART_CTL_RXE_BITN 9 +#define UART_CTL_RXE_M 0x00000200 +#define UART_CTL_RXE_S 9 +#define UART_CTL_RXE_EN 0x00000200 +#define UART_CTL_RXE_DIS 0x00000000 // Field: [8] TXE // @@ -534,12 +534,12 @@ // ENUMs: // EN UART Transmit enabled // DIS UART Transmit disabled -#define UART_CTL_TXE 0x00000100 -#define UART_CTL_TXE_BITN 8 -#define UART_CTL_TXE_M 0x00000100 -#define UART_CTL_TXE_S 8 -#define UART_CTL_TXE_EN 0x00000100 -#define UART_CTL_TXE_DIS 0x00000000 +#define UART_CTL_TXE 0x00000100 +#define UART_CTL_TXE_BITN 8 +#define UART_CTL_TXE_M 0x00000100 +#define UART_CTL_TXE_S 8 +#define UART_CTL_TXE_EN 0x00000100 +#define UART_CTL_TXE_DIS 0x00000000 // Field: [7] LBE // @@ -549,12 +549,12 @@ // ENUMs: // EN Loop Back enabled // DIS Loop Back disabled -#define UART_CTL_LBE 0x00000080 -#define UART_CTL_LBE_BITN 7 -#define UART_CTL_LBE_M 0x00000080 -#define UART_CTL_LBE_S 7 -#define UART_CTL_LBE_EN 0x00000080 -#define UART_CTL_LBE_DIS 0x00000000 +#define UART_CTL_LBE 0x00000080 +#define UART_CTL_LBE_BITN 7 +#define UART_CTL_LBE_M 0x00000080 +#define UART_CTL_LBE_S 7 +#define UART_CTL_LBE_EN 0x00000080 +#define UART_CTL_LBE_DIS 0x00000000 // Field: [0] UARTEN // @@ -562,12 +562,12 @@ // ENUMs: // EN UART enabled // DIS UART disabled -#define UART_CTL_UARTEN 0x00000001 -#define UART_CTL_UARTEN_BITN 0 -#define UART_CTL_UARTEN_M 0x00000001 -#define UART_CTL_UARTEN_S 0 -#define UART_CTL_UARTEN_EN 0x00000001 -#define UART_CTL_UARTEN_DIS 0x00000000 +#define UART_CTL_UARTEN 0x00000001 +#define UART_CTL_UARTEN_BITN 0 +#define UART_CTL_UARTEN_M 0x00000001 +#define UART_CTL_UARTEN_S 0 +#define UART_CTL_UARTEN_EN 0x00000001 +#define UART_CTL_UARTEN_DIS 0x00000000 //***************************************************************************** // @@ -585,14 +585,14 @@ // 4_8 Receive FIFO becomes >= 1/2 full // 2_8 Receive FIFO becomes >= 1/4 full // 1_8 Receive FIFO becomes >= 1/8 full -#define UART_IFLS_RXSEL_W 3 -#define UART_IFLS_RXSEL_M 0x00000038 -#define UART_IFLS_RXSEL_S 3 -#define UART_IFLS_RXSEL_7_8 0x00000020 -#define UART_IFLS_RXSEL_6_8 0x00000018 -#define UART_IFLS_RXSEL_4_8 0x00000010 -#define UART_IFLS_RXSEL_2_8 0x00000008 -#define UART_IFLS_RXSEL_1_8 0x00000000 +#define UART_IFLS_RXSEL_W 3 +#define UART_IFLS_RXSEL_M 0x00000038 +#define UART_IFLS_RXSEL_S 3 +#define UART_IFLS_RXSEL_7_8 0x00000020 +#define UART_IFLS_RXSEL_6_8 0x00000018 +#define UART_IFLS_RXSEL_4_8 0x00000010 +#define UART_IFLS_RXSEL_2_8 0x00000008 +#define UART_IFLS_RXSEL_1_8 0x00000000 // Field: [2:0] TXSEL // @@ -605,14 +605,14 @@ // 4_8 Transmit FIFO becomes <= 1/2 full // 2_8 Transmit FIFO becomes <= 1/4 full // 1_8 Transmit FIFO becomes <= 1/8 full -#define UART_IFLS_TXSEL_W 3 -#define UART_IFLS_TXSEL_M 0x00000007 -#define UART_IFLS_TXSEL_S 0 -#define UART_IFLS_TXSEL_7_8 0x00000004 -#define UART_IFLS_TXSEL_6_8 0x00000003 -#define UART_IFLS_TXSEL_4_8 0x00000002 -#define UART_IFLS_TXSEL_2_8 0x00000001 -#define UART_IFLS_TXSEL_1_8 0x00000000 +#define UART_IFLS_TXSEL_W 3 +#define UART_IFLS_TXSEL_M 0x00000007 +#define UART_IFLS_TXSEL_S 0 +#define UART_IFLS_TXSEL_7_8 0x00000004 +#define UART_IFLS_TXSEL_6_8 0x00000003 +#define UART_IFLS_TXSEL_4_8 0x00000002 +#define UART_IFLS_TXSEL_2_8 0x00000001 +#define UART_IFLS_TXSEL_1_8 0x00000000 //***************************************************************************** // @@ -626,10 +626,10 @@ // interrupt is set which means the interrupt state will be reflected in // MIS.OEMIS. A write of 0 clears the mask which means MIS.OEMIS will not // reflect the interrupt. -#define UART_IMSC_OEIM 0x00000400 -#define UART_IMSC_OEIM_BITN 10 -#define UART_IMSC_OEIM_M 0x00000400 -#define UART_IMSC_OEIM_S 10 +#define UART_IMSC_OEIM 0x00000400 +#define UART_IMSC_OEIM_BITN 10 +#define UART_IMSC_OEIM_M 0x00000400 +#define UART_IMSC_OEIM_S 10 // Field: [9] BEIM // @@ -637,10 +637,10 @@ // error interrupt. On a write of 1, the mask of the overrun error interrupt is // set which means the interrupt state will be reflected in MIS.BEMIS. A write // of 0 clears the mask which means MIS.BEMIS will not reflect the interrupt. -#define UART_IMSC_BEIM 0x00000200 -#define UART_IMSC_BEIM_BITN 9 -#define UART_IMSC_BEIM_M 0x00000200 -#define UART_IMSC_BEIM_S 9 +#define UART_IMSC_BEIM 0x00000200 +#define UART_IMSC_BEIM_BITN 9 +#define UART_IMSC_BEIM_M 0x00000200 +#define UART_IMSC_BEIM_S 9 // Field: [8] PEIM // @@ -649,10 +649,10 @@ // interrupt is set which means the interrupt state will be reflected in // MIS.PEMIS. A write of 0 clears the mask which means MIS.PEMIS will not // reflect the interrupt. -#define UART_IMSC_PEIM 0x00000100 -#define UART_IMSC_PEIM_BITN 8 -#define UART_IMSC_PEIM_M 0x00000100 -#define UART_IMSC_PEIM_S 8 +#define UART_IMSC_PEIM 0x00000100 +#define UART_IMSC_PEIM_BITN 8 +#define UART_IMSC_PEIM_M 0x00000100 +#define UART_IMSC_PEIM_S 8 // Field: [7] FEIM // @@ -661,10 +661,10 @@ // interrupt is set which means the interrupt state will be reflected in // MIS.FEMIS. A write of 0 clears the mask which means MIS.FEMIS will not // reflect the interrupt. -#define UART_IMSC_FEIM 0x00000080 -#define UART_IMSC_FEIM_BITN 7 -#define UART_IMSC_FEIM_M 0x00000080 -#define UART_IMSC_FEIM_S 7 +#define UART_IMSC_FEIM 0x00000080 +#define UART_IMSC_FEIM_BITN 7 +#define UART_IMSC_FEIM_M 0x00000080 +#define UART_IMSC_FEIM_S 7 // Field: [6] RTIM // @@ -676,10 +676,10 @@ // The raw interrupt for receive timeout RIS.RTRIS cannot be set unless the // mask is set (RTIM = 1). This is because the mask acts as an enable for power // saving. That is, the same status can be read from MIS.RTMIS and RIS.RTRIS. -#define UART_IMSC_RTIM 0x00000040 -#define UART_IMSC_RTIM_BITN 6 -#define UART_IMSC_RTIM_M 0x00000040 -#define UART_IMSC_RTIM_S 6 +#define UART_IMSC_RTIM 0x00000040 +#define UART_IMSC_RTIM_BITN 6 +#define UART_IMSC_RTIM_M 0x00000040 +#define UART_IMSC_RTIM_S 6 // Field: [5] TXIM // @@ -687,10 +687,10 @@ // interrupt. On a write of 1, the mask of the overrun error interrupt is set // which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 // clears the mask which means MIS.TXMIS will not reflect the interrupt. -#define UART_IMSC_TXIM 0x00000020 -#define UART_IMSC_TXIM_BITN 5 -#define UART_IMSC_TXIM_M 0x00000020 -#define UART_IMSC_TXIM_S 5 +#define UART_IMSC_TXIM 0x00000020 +#define UART_IMSC_TXIM_BITN 5 +#define UART_IMSC_TXIM_M 0x00000020 +#define UART_IMSC_TXIM_S 5 // Field: [4] RXIM // @@ -698,10 +698,10 @@ // interrupt. On a write of 1, the mask of the overrun error interrupt is set // which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 // clears the mask which means MIS.RXMIS will not reflect the interrupt. -#define UART_IMSC_RXIM 0x00000010 -#define UART_IMSC_RXIM_BITN 4 -#define UART_IMSC_RXIM_M 0x00000010 -#define UART_IMSC_RXIM_S 4 +#define UART_IMSC_RXIM 0x00000010 +#define UART_IMSC_RXIM_BITN 4 +#define UART_IMSC_RXIM_M 0x00000010 +#define UART_IMSC_RXIM_S 4 // Field: [1] CTSMIM // @@ -710,10 +710,10 @@ // error interrupt is set which means the interrupt state will be reflected in // MIS.CTSMMIS. A write of 0 clears the mask which means MIS.CTSMMIS will not // reflect the interrupt. -#define UART_IMSC_CTSMIM 0x00000002 -#define UART_IMSC_CTSMIM_BITN 1 -#define UART_IMSC_CTSMIM_M 0x00000002 -#define UART_IMSC_CTSMIM_S 1 +#define UART_IMSC_CTSMIM 0x00000002 +#define UART_IMSC_CTSMIM_BITN 1 +#define UART_IMSC_CTSMIM_M 0x00000002 +#define UART_IMSC_CTSMIM_S 1 //***************************************************************************** // @@ -726,10 +726,10 @@ // This field returns the raw interrupt state of UART's overrun error // interrupt. Overrun error occurs if data is received and the receive FIFO is // full. -#define UART_RIS_OERIS 0x00000400 -#define UART_RIS_OERIS_BITN 10 -#define UART_RIS_OERIS_M 0x00000400 -#define UART_RIS_OERIS_S 10 +#define UART_RIS_OERIS 0x00000400 +#define UART_RIS_OERIS_BITN 10 +#define UART_RIS_OERIS_M 0x00000400 +#define UART_RIS_OERIS_S 10 // Field: [9] BERIS // @@ -738,10 +738,10 @@ // Break error is set when a break condition is detected, indicating that the // received data input (UARTRXD input pin) was held LOW for longer than a // full-word transmission time (defined as start, data, parity and stop bits). -#define UART_RIS_BERIS 0x00000200 -#define UART_RIS_BERIS_BITN 9 -#define UART_RIS_BERIS_M 0x00000200 -#define UART_RIS_BERIS_S 9 +#define UART_RIS_BERIS 0x00000200 +#define UART_RIS_BERIS_BITN 9 +#define UART_RIS_BERIS_M 0x00000200 +#define UART_RIS_BERIS_S 9 // Field: [8] PERIS // @@ -749,10 +749,10 @@ // This field returns the raw interrupt state of UART's parity error interrupt. // Parity error is set if the parity of the received data character does not // match the parity that the LCRH.EPS and LCRH.SPS select. -#define UART_RIS_PERIS 0x00000100 -#define UART_RIS_PERIS_BITN 8 -#define UART_RIS_PERIS_M 0x00000100 -#define UART_RIS_PERIS_S 8 +#define UART_RIS_PERIS 0x00000100 +#define UART_RIS_PERIS_BITN 8 +#define UART_RIS_PERIS_M 0x00000100 +#define UART_RIS_PERIS_S 8 // Field: [7] FERIS // @@ -760,10 +760,10 @@ // This field returns the raw interrupt state of UART's framing error // interrupt. Framing error is set if the received character does not have a // valid stop bit (a valid stop bit is 1). -#define UART_RIS_FERIS 0x00000080 -#define UART_RIS_FERIS_BITN 7 -#define UART_RIS_FERIS_M 0x00000080 -#define UART_RIS_FERIS_S 7 +#define UART_RIS_FERIS 0x00000080 +#define UART_RIS_FERIS_BITN 7 +#define UART_RIS_FERIS_M 0x00000080 +#define UART_RIS_FERIS_S 7 // Field: [6] RTRIS // @@ -776,10 +776,10 @@ // The raw interrupt for receive timeout cannot be set unless the mask is set // (IMSC.RTIM = 1). This is because the mask acts as an enable for power // saving. That is, the same status can be read from MIS.RTMIS and RTRIS. -#define UART_RIS_RTRIS 0x00000040 -#define UART_RIS_RTRIS_BITN 6 -#define UART_RIS_RTRIS_M 0x00000040 -#define UART_RIS_RTRIS_S 6 +#define UART_RIS_RTRIS 0x00000040 +#define UART_RIS_RTRIS_BITN 6 +#define UART_RIS_RTRIS_M 0x00000040 +#define UART_RIS_RTRIS_S 6 // Field: [5] TXRIS // @@ -794,10 +794,10 @@ // location, the transmit interrupt is asserted if there is no data present in // the transmitters single location. It is cleared by performing a single write // to the transmit FIFO, or by clearing the interrupt through ICR.TXIC. -#define UART_RIS_TXRIS 0x00000020 -#define UART_RIS_TXRIS_BITN 5 -#define UART_RIS_TXRIS_M 0x00000020 -#define UART_RIS_TXRIS_S 5 +#define UART_RIS_TXRIS 0x00000020 +#define UART_RIS_TXRIS_BITN 5 +#define UART_RIS_TXRIS_M 0x00000020 +#define UART_RIS_TXRIS_S 5 // Field: [4] RXRIS // @@ -813,20 +813,20 @@ // thereby filling the location. The receive interrupt is cleared by performing // a single read of the receive FIFO, or by clearing the interrupt through // ICR.RXIC. -#define UART_RIS_RXRIS 0x00000010 -#define UART_RIS_RXRIS_BITN 4 -#define UART_RIS_RXRIS_M 0x00000010 -#define UART_RIS_RXRIS_S 4 +#define UART_RIS_RXRIS 0x00000010 +#define UART_RIS_RXRIS_BITN 4 +#define UART_RIS_RXRIS_M 0x00000010 +#define UART_RIS_RXRIS_S 4 // Field: [1] CTSRMIS // // Clear to Send (CTS) modem interrupt status: // This field returns the raw interrupt state of UART's clear to send // interrupt. -#define UART_RIS_CTSRMIS 0x00000002 -#define UART_RIS_CTSRMIS_BITN 1 -#define UART_RIS_CTSRMIS_M 0x00000002 -#define UART_RIS_CTSRMIS_S 1 +#define UART_RIS_CTSRMIS 0x00000002 +#define UART_RIS_CTSRMIS_BITN 1 +#define UART_RIS_CTSRMIS_M 0x00000002 +#define UART_RIS_CTSRMIS_S 1 //***************************************************************************** // @@ -839,10 +839,10 @@ // This field returns the masked interrupt state of the overrun interrupt which // is the AND product of raw interrupt state RIS.OERIS and the mask setting // IMSC.OEIM. -#define UART_MIS_OEMIS 0x00000400 -#define UART_MIS_OEMIS_BITN 10 -#define UART_MIS_OEMIS_M 0x00000400 -#define UART_MIS_OEMIS_S 10 +#define UART_MIS_OEMIS 0x00000400 +#define UART_MIS_OEMIS_BITN 10 +#define UART_MIS_OEMIS_M 0x00000400 +#define UART_MIS_OEMIS_S 10 // Field: [9] BEMIS // @@ -850,10 +850,10 @@ // This field returns the masked interrupt state of the break error interrupt // which is the AND product of raw interrupt state RIS.BERIS and the mask // setting IMSC.BEIM. -#define UART_MIS_BEMIS 0x00000200 -#define UART_MIS_BEMIS_BITN 9 -#define UART_MIS_BEMIS_M 0x00000200 -#define UART_MIS_BEMIS_S 9 +#define UART_MIS_BEMIS 0x00000200 +#define UART_MIS_BEMIS_BITN 9 +#define UART_MIS_BEMIS_M 0x00000200 +#define UART_MIS_BEMIS_S 9 // Field: [8] PEMIS // @@ -861,20 +861,20 @@ // This field returns the masked interrupt state of the parity error interrupt // which is the AND product of raw interrupt state RIS.PERIS and the mask // setting IMSC.PEIM. -#define UART_MIS_PEMIS 0x00000100 -#define UART_MIS_PEMIS_BITN 8 -#define UART_MIS_PEMIS_M 0x00000100 -#define UART_MIS_PEMIS_S 8 +#define UART_MIS_PEMIS 0x00000100 +#define UART_MIS_PEMIS_BITN 8 +#define UART_MIS_PEMIS_M 0x00000100 +#define UART_MIS_PEMIS_S 8 // Field: [7] FEMIS // // Framing error masked interrupt status: Returns the masked interrupt state of // the framing error interrupt which is the AND product of raw interrupt state // RIS.FERIS and the mask setting IMSC.FEIM. -#define UART_MIS_FEMIS 0x00000080 -#define UART_MIS_FEMIS_BITN 7 -#define UART_MIS_FEMIS_M 0x00000080 -#define UART_MIS_FEMIS_S 7 +#define UART_MIS_FEMIS 0x00000080 +#define UART_MIS_FEMIS_BITN 7 +#define UART_MIS_FEMIS_M 0x00000080 +#define UART_MIS_FEMIS_S 7 // Field: [6] RTMIS // @@ -883,10 +883,10 @@ // The raw interrupt for receive timeout cannot be set unless the mask is set // (IMSC.RTIM = 1). This is because the mask acts as an enable for power // saving. That is, the same status can be read from RTMIS and RIS.RTRIS. -#define UART_MIS_RTMIS 0x00000040 -#define UART_MIS_RTMIS_BITN 6 -#define UART_MIS_RTMIS_M 0x00000040 -#define UART_MIS_RTMIS_S 6 +#define UART_MIS_RTMIS 0x00000040 +#define UART_MIS_RTMIS_BITN 6 +#define UART_MIS_RTMIS_M 0x00000040 +#define UART_MIS_RTMIS_S 6 // Field: [5] TXMIS // @@ -894,10 +894,10 @@ // This field returns the masked interrupt state of the transmit interrupt // which is the AND product of raw interrupt state RIS.TXRIS and the mask // setting IMSC.TXIM. -#define UART_MIS_TXMIS 0x00000020 -#define UART_MIS_TXMIS_BITN 5 -#define UART_MIS_TXMIS_M 0x00000020 -#define UART_MIS_TXMIS_S 5 +#define UART_MIS_TXMIS 0x00000020 +#define UART_MIS_TXMIS_BITN 5 +#define UART_MIS_TXMIS_M 0x00000020 +#define UART_MIS_TXMIS_S 5 // Field: [4] RXMIS // @@ -905,10 +905,10 @@ // This field returns the masked interrupt state of the receive interrupt // which is the AND product of raw interrupt state RIS.RXRIS and the mask // setting IMSC.RXIM. -#define UART_MIS_RXMIS 0x00000010 -#define UART_MIS_RXMIS_BITN 4 -#define UART_MIS_RXMIS_M 0x00000010 -#define UART_MIS_RXMIS_S 4 +#define UART_MIS_RXMIS 0x00000010 +#define UART_MIS_RXMIS_BITN 4 +#define UART_MIS_RXMIS_M 0x00000010 +#define UART_MIS_RXMIS_S 4 // Field: [1] CTSMMIS // @@ -916,10 +916,10 @@ // This field returns the masked interrupt state of the clear to send interrupt // which is the AND product of raw interrupt state RIS.CTSRMIS and the mask // setting IMSC.CTSMIM. -#define UART_MIS_CTSMMIS 0x00000002 -#define UART_MIS_CTSMMIS_BITN 1 -#define UART_MIS_CTSMMIS_M 0x00000002 -#define UART_MIS_CTSMMIS_S 1 +#define UART_MIS_CTSMMIS 0x00000002 +#define UART_MIS_CTSMMIS_BITN 1 +#define UART_MIS_CTSMMIS_M 0x00000002 +#define UART_MIS_CTSMMIS_S 1 //***************************************************************************** // @@ -931,80 +931,80 @@ // Overrun error interrupt clear: // Writing 1 to this field clears the overrun error interrupt (RIS.OERIS). // Writing 0 has no effect. -#define UART_ICR_OEIC 0x00000400 -#define UART_ICR_OEIC_BITN 10 -#define UART_ICR_OEIC_M 0x00000400 -#define UART_ICR_OEIC_S 10 +#define UART_ICR_OEIC 0x00000400 +#define UART_ICR_OEIC_BITN 10 +#define UART_ICR_OEIC_M 0x00000400 +#define UART_ICR_OEIC_S 10 // Field: [9] BEIC // // Break error interrupt clear: // Writing 1 to this field clears the break error interrupt (RIS.BERIS). // Writing 0 has no effect. -#define UART_ICR_BEIC 0x00000200 -#define UART_ICR_BEIC_BITN 9 -#define UART_ICR_BEIC_M 0x00000200 -#define UART_ICR_BEIC_S 9 +#define UART_ICR_BEIC 0x00000200 +#define UART_ICR_BEIC_BITN 9 +#define UART_ICR_BEIC_M 0x00000200 +#define UART_ICR_BEIC_S 9 // Field: [8] PEIC // // Parity error interrupt clear: // Writing 1 to this field clears the parity error interrupt (RIS.PERIS). // Writing 0 has no effect. -#define UART_ICR_PEIC 0x00000100 -#define UART_ICR_PEIC_BITN 8 -#define UART_ICR_PEIC_M 0x00000100 -#define UART_ICR_PEIC_S 8 +#define UART_ICR_PEIC 0x00000100 +#define UART_ICR_PEIC_BITN 8 +#define UART_ICR_PEIC_M 0x00000100 +#define UART_ICR_PEIC_S 8 // Field: [7] FEIC // // Framing error interrupt clear: // Writing 1 to this field clears the framing error interrupt (RIS.FERIS). // Writing 0 has no effect. -#define UART_ICR_FEIC 0x00000080 -#define UART_ICR_FEIC_BITN 7 -#define UART_ICR_FEIC_M 0x00000080 -#define UART_ICR_FEIC_S 7 +#define UART_ICR_FEIC 0x00000080 +#define UART_ICR_FEIC_BITN 7 +#define UART_ICR_FEIC_M 0x00000080 +#define UART_ICR_FEIC_S 7 // Field: [6] RTIC // // Receive timeout interrupt clear: // Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS). // Writing 0 has no effect. -#define UART_ICR_RTIC 0x00000040 -#define UART_ICR_RTIC_BITN 6 -#define UART_ICR_RTIC_M 0x00000040 -#define UART_ICR_RTIC_S 6 +#define UART_ICR_RTIC 0x00000040 +#define UART_ICR_RTIC_BITN 6 +#define UART_ICR_RTIC_M 0x00000040 +#define UART_ICR_RTIC_S 6 // Field: [5] TXIC // // Transmit interrupt clear: // Writing 1 to this field clears the transmit interrupt (RIS.TXRIS). Writing 0 // has no effect. -#define UART_ICR_TXIC 0x00000020 -#define UART_ICR_TXIC_BITN 5 -#define UART_ICR_TXIC_M 0x00000020 -#define UART_ICR_TXIC_S 5 +#define UART_ICR_TXIC 0x00000020 +#define UART_ICR_TXIC_BITN 5 +#define UART_ICR_TXIC_M 0x00000020 +#define UART_ICR_TXIC_S 5 // Field: [4] RXIC // // Receive interrupt clear: // Writing 1 to this field clears the receive interrupt (RIS.RXRIS). Writing 0 // has no effect. -#define UART_ICR_RXIC 0x00000010 -#define UART_ICR_RXIC_BITN 4 -#define UART_ICR_RXIC_M 0x00000010 -#define UART_ICR_RXIC_S 4 +#define UART_ICR_RXIC 0x00000010 +#define UART_ICR_RXIC_BITN 4 +#define UART_ICR_RXIC_M 0x00000010 +#define UART_ICR_RXIC_S 4 // Field: [1] CTSMIC // // Clear to Send (CTS) modem interrupt clear: // Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS). // Writing 0 has no effect. -#define UART_ICR_CTSMIC 0x00000002 -#define UART_ICR_CTSMIC_BITN 1 -#define UART_ICR_CTSMIC_M 0x00000002 -#define UART_ICR_CTSMIC_S 1 +#define UART_ICR_CTSMIC 0x00000002 +#define UART_ICR_CTSMIC_BITN 1 +#define UART_ICR_CTSMIC_M 0x00000002 +#define UART_ICR_CTSMIC_S 1 //***************************************************************************** // @@ -1017,28 +1017,27 @@ // single and burst requests) are disabled when the UART error interrupt is // asserted (more specifically if any of the error interrupts RIS.PERIS, // RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted). -#define UART_DMACTL_DMAONERR 0x00000004 -#define UART_DMACTL_DMAONERR_BITN 2 -#define UART_DMACTL_DMAONERR_M 0x00000004 -#define UART_DMACTL_DMAONERR_S 2 +#define UART_DMACTL_DMAONERR 0x00000004 +#define UART_DMACTL_DMAONERR_BITN 2 +#define UART_DMACTL_DMAONERR_M 0x00000004 +#define UART_DMACTL_DMAONERR_S 2 // Field: [1] TXDMAE // // Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is // enabled. -#define UART_DMACTL_TXDMAE 0x00000002 -#define UART_DMACTL_TXDMAE_BITN 1 -#define UART_DMACTL_TXDMAE_M 0x00000002 -#define UART_DMACTL_TXDMAE_S 1 +#define UART_DMACTL_TXDMAE 0x00000002 +#define UART_DMACTL_TXDMAE_BITN 1 +#define UART_DMACTL_TXDMAE_M 0x00000002 +#define UART_DMACTL_TXDMAE_S 1 // Field: [0] RXDMAE // // Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is // enabled. -#define UART_DMACTL_RXDMAE 0x00000001 -#define UART_DMACTL_RXDMAE_BITN 0 -#define UART_DMACTL_RXDMAE_M 0x00000001 -#define UART_DMACTL_RXDMAE_S 0 - +#define UART_DMACTL_RXDMAE 0x00000001 +#define UART_DMACTL_RXDMAE_BITN 0 +#define UART_DMACTL_RXDMAE_M 0x00000001 +#define UART_DMACTL_RXDMAE_S 0 #endif // __UART__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_udma.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_udma.h index 63d0a54..84ebe4d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_udma.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_udma.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_udma_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_udma_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_UDMA_H__ #define __HW_UDMA_H__ @@ -44,61 +44,61 @@ // //***************************************************************************** // Status -#define UDMA_O_STATUS 0x00000000 +#define UDMA_O_STATUS 0x00000000 // Configuration -#define UDMA_O_CFG 0x00000004 +#define UDMA_O_CFG 0x00000004 // Channel Control Data Base Pointer -#define UDMA_O_CTRL 0x00000008 +#define UDMA_O_CTRL 0x00000008 // Channel Alternate Control Data Base Pointer -#define UDMA_O_ALTCTRL 0x0000000C +#define UDMA_O_ALTCTRL 0x0000000C // Channel Wait On Request Status -#define UDMA_O_WAITONREQ 0x00000010 +#define UDMA_O_WAITONREQ 0x00000010 // Channel Software Request -#define UDMA_O_SOFTREQ 0x00000014 +#define UDMA_O_SOFTREQ 0x00000014 // Channel Set UseBurst -#define UDMA_O_SETBURST 0x00000018 +#define UDMA_O_SETBURST 0x00000018 // Channel Clear UseBurst -#define UDMA_O_CLEARBURST 0x0000001C +#define UDMA_O_CLEARBURST 0x0000001C // Channel Set Request Mask -#define UDMA_O_SETREQMASK 0x00000020 +#define UDMA_O_SETREQMASK 0x00000020 // Clear Channel Request Mask -#define UDMA_O_CLEARREQMASK 0x00000024 +#define UDMA_O_CLEARREQMASK 0x00000024 // Set Channel Enable -#define UDMA_O_SETCHANNELEN 0x00000028 +#define UDMA_O_SETCHANNELEN 0x00000028 // Clear Channel Enable -#define UDMA_O_CLEARCHANNELEN 0x0000002C +#define UDMA_O_CLEARCHANNELEN 0x0000002C // Channel Set Primary-Alternate -#define UDMA_O_SETCHNLPRIALT 0x00000030 +#define UDMA_O_SETCHNLPRIALT 0x00000030 // Channel Clear Primary-Alternate -#define UDMA_O_CLEARCHNLPRIALT 0x00000034 +#define UDMA_O_CLEARCHNLPRIALT 0x00000034 // Set Channel Priority -#define UDMA_O_SETCHNLPRIORITY 0x00000038 +#define UDMA_O_SETCHNLPRIORITY 0x00000038 // Clear Channel Priority -#define UDMA_O_CLEARCHNLPRIORITY 0x0000003C +#define UDMA_O_CLEARCHNLPRIORITY 0x0000003C // Error Status and Clear -#define UDMA_O_ERROR 0x0000004C +#define UDMA_O_ERROR 0x0000004C // Channel Request Done -#define UDMA_O_REQDONE 0x00000504 +#define UDMA_O_REQDONE 0x00000504 // Channel Request Done Mask -#define UDMA_O_DONEMASK 0x00000520 +#define UDMA_O_DONEMASK 0x00000520 //***************************************************************************** // @@ -113,9 +113,9 @@ // 0x2: Undefined // ... // 0xF: Undefined -#define UDMA_STATUS_TEST_W 4 -#define UDMA_STATUS_TEST_M 0xF0000000 -#define UDMA_STATUS_TEST_S 28 +#define UDMA_STATUS_TEST_W 4 +#define UDMA_STATUS_TEST_M 0xF0000000 +#define UDMA_STATUS_TEST_S 28 // Field: [20:16] TOTALCHANNELS // @@ -127,9 +127,9 @@ // ... // 0x1F: Shows that the controller is configured to use 32 uDMA channels // (32-1=31=0x1F) -#define UDMA_STATUS_TOTALCHANNELS_W 5 -#define UDMA_STATUS_TOTALCHANNELS_M 0x001F0000 -#define UDMA_STATUS_TOTALCHANNELS_S 16 +#define UDMA_STATUS_TOTALCHANNELS_W 5 +#define UDMA_STATUS_TOTALCHANNELS_M 0x001F0000 +#define UDMA_STATUS_TOTALCHANNELS_S 16 // Field: [7:4] STATE // @@ -150,9 +150,9 @@ // 0xB: Undefined // ... // 0xF: Undefined. -#define UDMA_STATUS_STATE_W 4 -#define UDMA_STATUS_STATE_M 0x000000F0 -#define UDMA_STATUS_STATE_S 4 +#define UDMA_STATUS_STATE_W 4 +#define UDMA_STATUS_STATE_M 0x000000F0 +#define UDMA_STATUS_STATE_S 4 // Field: [0] MASTERENABLE // @@ -160,10 +160,10 @@ // // 0: Controller is disabled // 1: Controller is enabled -#define UDMA_STATUS_MASTERENABLE 0x00000001 -#define UDMA_STATUS_MASTERENABLE_BITN 0 -#define UDMA_STATUS_MASTERENABLE_M 0x00000001 -#define UDMA_STATUS_MASTERENABLE_S 0 +#define UDMA_STATUS_MASTERENABLE 0x00000001 +#define UDMA_STATUS_MASTERENABLE_BITN 0 +#define UDMA_STATUS_MASTERENABLE_M 0x00000001 +#define UDMA_STATUS_MASTERENABLE_S 0 //***************************************************************************** // @@ -188,9 +188,9 @@ // - the write to the address indicated by destination address pointer // HProt[3:1] for these two exceptions can be controlled by dedicated fields in // the channel configutation descriptor. -#define UDMA_CFG_PRTOCTRL_W 3 -#define UDMA_CFG_PRTOCTRL_M 0x000000E0 -#define UDMA_CFG_PRTOCTRL_S 5 +#define UDMA_CFG_PRTOCTRL_W 3 +#define UDMA_CFG_PRTOCTRL_M 0x000000E0 +#define UDMA_CFG_PRTOCTRL_S 5 // Field: [0] MASTERENABLE // @@ -198,10 +198,10 @@ // // 0: Disables the controller // 1: Enables the controller -#define UDMA_CFG_MASTERENABLE 0x00000001 -#define UDMA_CFG_MASTERENABLE_BITN 0 -#define UDMA_CFG_MASTERENABLE_M 0x00000001 -#define UDMA_CFG_MASTERENABLE_S 0 +#define UDMA_CFG_MASTERENABLE 0x00000001 +#define UDMA_CFG_MASTERENABLE_BITN 0 +#define UDMA_CFG_MASTERENABLE_M 0x00000001 +#define UDMA_CFG_MASTERENABLE_S 0 //***************************************************************************** // @@ -213,9 +213,9 @@ // This register point to the base address for the primary data structures of // each DMA channel. This is not stored in module, but in system memory, thus // space must be allocated for this usage when DMA is in usage -#define UDMA_CTRL_BASEPTR_W 22 -#define UDMA_CTRL_BASEPTR_M 0xFFFFFC00 -#define UDMA_CTRL_BASEPTR_S 10 +#define UDMA_CTRL_BASEPTR_W 22 +#define UDMA_CTRL_BASEPTR_M 0xFFFFFC00 +#define UDMA_CTRL_BASEPTR_S 10 //***************************************************************************** // @@ -226,9 +226,9 @@ // // This register shows the base address for the alternate data structures and // is calculated by module, thus read only -#define UDMA_ALTCTRL_BASEPTR_W 32 -#define UDMA_ALTCTRL_BASEPTR_M 0xFFFFFFFF -#define UDMA_ALTCTRL_BASEPTR_S 0 +#define UDMA_ALTCTRL_BASEPTR_W 32 +#define UDMA_ALTCTRL_BASEPTR_M 0xFFFFFFFF +#define UDMA_ALTCTRL_BASEPTR_S 0 //***************************************************************************** // @@ -245,9 +245,9 @@ // keeps channel Ch in active state until the requests are deasserted. This // handshake is necessary for channels where the requester is in an // asynchronous domain or can run at slower clock speed than uDMA -#define UDMA_WAITONREQ_CHNLSTATUS_W 32 -#define UDMA_WAITONREQ_CHNLSTATUS_M 0xFFFFFFFF -#define UDMA_WAITONREQ_CHNLSTATUS_S 0 +#define UDMA_WAITONREQ_CHNLSTATUS_W 32 +#define UDMA_WAITONREQ_CHNLSTATUS_M 0xFFFFFFFF +#define UDMA_WAITONREQ_CHNLSTATUS_S 0 //***************************************************************************** // @@ -264,9 +264,9 @@ // // Writing to a bit where a uDMA channel is not implemented does not create a // uDMA request for that channel -#define UDMA_SOFTREQ_CHNLS_W 32 -#define UDMA_SOFTREQ_CHNLS_M 0xFFFFFFFF -#define UDMA_SOFTREQ_CHNLS_S 0 +#define UDMA_SOFTREQ_CHNLS_W 32 +#define UDMA_SOFTREQ_CHNLS_M 0xFFFFFFFF +#define UDMA_SOFTREQ_CHNLS_S 0 //***************************************************************************** // @@ -294,9 +294,9 @@ // controller performs 2^R transfers for burst requests. // // Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_SETBURST_CHNLS_W 32 -#define UDMA_SETBURST_CHNLS_M 0xFFFFFFFF -#define UDMA_SETBURST_CHNLS_S 0 +#define UDMA_SETBURST_CHNLS_W 32 +#define UDMA_SETBURST_CHNLS_M 0xFFFFFFFF +#define UDMA_SETBURST_CHNLS_S 0 //***************************************************************************** // @@ -315,9 +315,9 @@ // Bit [Ch] = 1: Enables single transfer requests on channel Ch. // // Writing to a bit where a DMA channel is not implemented has no effect. -#define UDMA_CLEARBURST_CHNLS_W 32 -#define UDMA_CLEARBURST_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARBURST_CHNLS_S 0 +#define UDMA_CLEARBURST_CHNLS_W 32 +#define UDMA_CLEARBURST_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARBURST_CHNLS_S 0 //***************************************************************************** // @@ -339,9 +339,9 @@ // request channel [C] input from generating uDMA requests. // // Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_SETREQMASK_CHNLS_W 32 -#define UDMA_SETREQMASK_CHNLS_M 0xFFFFFFFF -#define UDMA_SETREQMASK_CHNLS_S 0 +#define UDMA_SETREQMASK_CHNLS_W 32 +#define UDMA_SETREQMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_SETREQMASK_CHNLS_S 0 //***************************************************************************** // @@ -358,9 +358,9 @@ // Bit [Ch] = 1: Enables channel [C] to generate DMA requests. // // Writing to a bit where a DMA channel is not implemented has no effect. -#define UDMA_CLEARREQMASK_CHNLS_W 32 -#define UDMA_CLEARREQMASK_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARREQMASK_CHNLS_S 0 +#define UDMA_CLEARREQMASK_CHNLS_W 32 +#define UDMA_CLEARREQMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARREQMASK_CHNLS_S 0 //***************************************************************************** // @@ -381,9 +381,9 @@ // Bit [Ch] = 1: Enables channel Ch // // Writing to a bit where a DMA channel is not implemented has no effect -#define UDMA_SETCHANNELEN_CHNLS_W 32 -#define UDMA_SETCHANNELEN_CHNLS_M 0xFFFFFFFF -#define UDMA_SETCHANNELEN_CHNLS_S 0 +#define UDMA_SETCHANNELEN_CHNLS_W 32 +#define UDMA_SETCHANNELEN_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHANNELEN_CHNLS_S 0 //***************************************************************************** // @@ -399,9 +399,9 @@ // Bit [Ch] = 1: Disables channel Ch // // Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_CLEARCHANNELEN_CHNLS_W 32 -#define UDMA_CLEARCHANNELEN_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARCHANNELEN_CHNLS_S 0 +#define UDMA_CLEARCHANNELEN_CHNLS_W 32 +#define UDMA_CLEARCHANNELEN_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHANNELEN_CHNLS_S 0 //***************************************************************************** // @@ -422,9 +422,9 @@ // Bit [Ch] = 1: Selects the alternate data structure for channel Ch // // Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_SETCHNLPRIALT_CHNLS_W 32 -#define UDMA_SETCHNLPRIALT_CHNLS_M 0xFFFFFFFF -#define UDMA_SETCHNLPRIALT_CHNLS_S 0 +#define UDMA_SETCHNLPRIALT_CHNLS_W 32 +#define UDMA_SETCHNLPRIALT_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHNLPRIALT_CHNLS_S 0 //***************************************************************************** // @@ -442,9 +442,9 @@ // Bit [Ch] = 1: Selects the primary data structure for channel Ch. // // Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_CLEARCHNLPRIALT_CHNLS_W 32 -#define UDMA_CLEARCHNLPRIALT_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARCHNLPRIALT_CHNLS_S 0 +#define UDMA_CLEARCHNLPRIALT_CHNLS_W 32 +#define UDMA_CLEARCHNLPRIALT_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHNLPRIALT_CHNLS_S 0 //***************************************************************************** // @@ -466,9 +466,9 @@ // Bit [Ch] = 1: Channel Ch uses the high priority level. // // Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_SETCHNLPRIORITY_CHNLS_W 32 -#define UDMA_SETCHNLPRIORITY_CHNLS_M 0xFFFFFFFF -#define UDMA_SETCHNLPRIORITY_CHNLS_S 0 +#define UDMA_SETCHNLPRIORITY_CHNLS_W 32 +#define UDMA_SETCHNLPRIORITY_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHNLPRIORITY_CHNLS_S 0 //***************************************************************************** // @@ -486,9 +486,9 @@ // Bit [Ch] = 1: Channel Ch uses the default priority level. // // Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_CLEARCHNLPRIORITY_CHNLS_W 32 -#define UDMA_CLEARCHNLPRIORITY_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARCHNLPRIORITY_CHNLS_S 0 +#define UDMA_CLEARCHNLPRIORITY_CHNLS_W 32 +#define UDMA_CLEARCHNLPRIORITY_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHNLPRIORITY_CHNLS_S 0 //***************************************************************************** // @@ -508,10 +508,10 @@ // // 0: No effect, status of bus error flag is unchanged. // 1: Clears the bus error flag. -#define UDMA_ERROR_STATUS 0x00000001 -#define UDMA_ERROR_STATUS_BITN 0 -#define UDMA_ERROR_STATUS_M 0x00000001 -#define UDMA_ERROR_STATUS_S 0 +#define UDMA_ERROR_STATUS 0x00000001 +#define UDMA_ERROR_STATUS_BITN 0 +#define UDMA_ERROR_STATUS_M 0x00000001 +#define UDMA_ERROR_STATUS_S 0 //***************************************************************************** // @@ -532,9 +532,9 @@ // Write as: // Bit [Ch] = 0: No effect. // Bit [Ch] = 1: The corresponding [Ch] bit is cleared and is set to 0 -#define UDMA_REQDONE_CHNLS_W 32 -#define UDMA_REQDONE_CHNLS_M 0xFFFFFFFF -#define UDMA_REQDONE_CHNLS_S 0 +#define UDMA_REQDONE_CHNLS_W 32 +#define UDMA_REQDONE_CHNLS_M 0xFFFFFFFF +#define UDMA_REQDONE_CHNLS_S 0 //***************************************************************************** // @@ -567,9 +567,8 @@ // peripherals. // Note that this enables uDMA done for channel [Ch] to contribute to // generation of combined uDMA done signal. -#define UDMA_DONEMASK_CHNLS_W 32 -#define UDMA_DONEMASK_CHNLS_M 0xFFFFFFFF -#define UDMA_DONEMASK_CHNLS_S 0 - +#define UDMA_DONEMASK_CHNLS_W 32 +#define UDMA_DONEMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_DONEMASK_CHNLS_S 0 #endif // __UDMA__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_vims.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_vims.h index 8ba5b60..a36fbae 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_vims.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_vims.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_vims_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_vims_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_VIMS_H__ #define __HW_VIMS_H__ @@ -44,10 +44,10 @@ // //***************************************************************************** // Status -#define VIMS_O_STAT 0x00000000 +#define VIMS_O_STAT 0x00000000 // Control -#define VIMS_O_CTL 0x00000004 +#define VIMS_O_CTL 0x00000004 //***************************************************************************** // @@ -60,10 +60,10 @@ // // 0: Enabled or in transition to disabled // 1: Disabled and flushed -#define VIMS_STAT_IDCODE_LB_DIS 0x00000020 -#define VIMS_STAT_IDCODE_LB_DIS_BITN 5 -#define VIMS_STAT_IDCODE_LB_DIS_M 0x00000020 -#define VIMS_STAT_IDCODE_LB_DIS_S 5 +#define VIMS_STAT_IDCODE_LB_DIS 0x00000020 +#define VIMS_STAT_IDCODE_LB_DIS_BITN 5 +#define VIMS_STAT_IDCODE_LB_DIS_M 0x00000020 +#define VIMS_STAT_IDCODE_LB_DIS_S 5 // Field: [4] SYSBUS_LB_DIS // @@ -71,10 +71,10 @@ // // 0: Enabled or in transition to disabled // 1: Disabled and flushed -#define VIMS_STAT_SYSBUS_LB_DIS 0x00000010 -#define VIMS_STAT_SYSBUS_LB_DIS_BITN 4 -#define VIMS_STAT_SYSBUS_LB_DIS_M 0x00000010 -#define VIMS_STAT_SYSBUS_LB_DIS_S 4 +#define VIMS_STAT_SYSBUS_LB_DIS 0x00000010 +#define VIMS_STAT_SYSBUS_LB_DIS_BITN 4 +#define VIMS_STAT_SYSBUS_LB_DIS_M 0x00000010 +#define VIMS_STAT_SYSBUS_LB_DIS_S 4 // Field: [3] MODE_CHANGING // @@ -82,18 +82,18 @@ // // 0: VIMS is in the mode defined by MODE // 1: VIMS is in the process of changing to the mode given in CTL.MODE -#define VIMS_STAT_MODE_CHANGING 0x00000008 -#define VIMS_STAT_MODE_CHANGING_BITN 3 -#define VIMS_STAT_MODE_CHANGING_M 0x00000008 -#define VIMS_STAT_MODE_CHANGING_S 3 +#define VIMS_STAT_MODE_CHANGING 0x00000008 +#define VIMS_STAT_MODE_CHANGING_BITN 3 +#define VIMS_STAT_MODE_CHANGING_M 0x00000008 +#define VIMS_STAT_MODE_CHANGING_S 3 // Field: [2] INV // // This bit is set when invalidation of the cache memory is active / ongoing -#define VIMS_STAT_INV 0x00000004 -#define VIMS_STAT_INV_BITN 2 -#define VIMS_STAT_INV_M 0x00000004 -#define VIMS_STAT_INV_S 2 +#define VIMS_STAT_INV 0x00000004 +#define VIMS_STAT_INV_BITN 2 +#define VIMS_STAT_INV_M 0x00000004 +#define VIMS_STAT_INV_S 2 // Field: [1:0] MODE // @@ -102,12 +102,12 @@ // OFF VIMS Off mode // CACHE VIMS Cache mode // GPRAM VIMS GPRAM mode -#define VIMS_STAT_MODE_W 2 -#define VIMS_STAT_MODE_M 0x00000003 -#define VIMS_STAT_MODE_S 0 -#define VIMS_STAT_MODE_OFF 0x00000003 -#define VIMS_STAT_MODE_CACHE 0x00000001 -#define VIMS_STAT_MODE_GPRAM 0x00000000 +#define VIMS_STAT_MODE_W 2 +#define VIMS_STAT_MODE_M 0x00000003 +#define VIMS_STAT_MODE_S 0 +#define VIMS_STAT_MODE_OFF 0x00000003 +#define VIMS_STAT_MODE_CACHE 0x00000001 +#define VIMS_STAT_MODE_GPRAM 0x00000000 //***************************************************************************** // @@ -117,28 +117,28 @@ // Field: [31] STATS_CLR // // Set this bit to clear statistic counters. -#define VIMS_CTL_STATS_CLR 0x80000000 -#define VIMS_CTL_STATS_CLR_BITN 31 -#define VIMS_CTL_STATS_CLR_M 0x80000000 -#define VIMS_CTL_STATS_CLR_S 31 +#define VIMS_CTL_STATS_CLR 0x80000000 +#define VIMS_CTL_STATS_CLR_BITN 31 +#define VIMS_CTL_STATS_CLR_M 0x80000000 +#define VIMS_CTL_STATS_CLR_S 31 // Field: [30] STATS_EN // // Set this bit to enable statistic counters. -#define VIMS_CTL_STATS_EN 0x40000000 -#define VIMS_CTL_STATS_EN_BITN 30 -#define VIMS_CTL_STATS_EN_M 0x40000000 -#define VIMS_CTL_STATS_EN_S 30 +#define VIMS_CTL_STATS_EN 0x40000000 +#define VIMS_CTL_STATS_EN_BITN 30 +#define VIMS_CTL_STATS_EN_M 0x40000000 +#define VIMS_CTL_STATS_EN_S 30 // Field: [29] DYN_CG_EN // // 0: The in-built clock gate functionality is bypassed. // 1: The in-built clock gate functionality is enabled, automatically gating // the clock when not needed. -#define VIMS_CTL_DYN_CG_EN 0x20000000 -#define VIMS_CTL_DYN_CG_EN_BITN 29 -#define VIMS_CTL_DYN_CG_EN_M 0x20000000 -#define VIMS_CTL_DYN_CG_EN_S 29 +#define VIMS_CTL_DYN_CG_EN 0x20000000 +#define VIMS_CTL_DYN_CG_EN_BITN 29 +#define VIMS_CTL_DYN_CG_EN_M 0x20000000 +#define VIMS_CTL_DYN_CG_EN_S 29 // Field: [5] IDCODE_LB_DIS // @@ -146,10 +146,10 @@ // // 0: Enable // 1: Disable -#define VIMS_CTL_IDCODE_LB_DIS 0x00000020 -#define VIMS_CTL_IDCODE_LB_DIS_BITN 5 -#define VIMS_CTL_IDCODE_LB_DIS_M 0x00000020 -#define VIMS_CTL_IDCODE_LB_DIS_S 5 +#define VIMS_CTL_IDCODE_LB_DIS 0x00000020 +#define VIMS_CTL_IDCODE_LB_DIS_BITN 5 +#define VIMS_CTL_IDCODE_LB_DIS_M 0x00000020 +#define VIMS_CTL_IDCODE_LB_DIS_S 5 // Field: [4] SYSBUS_LB_DIS // @@ -157,10 +157,10 @@ // // 0: Enable // 1: Disable -#define VIMS_CTL_SYSBUS_LB_DIS 0x00000010 -#define VIMS_CTL_SYSBUS_LB_DIS_BITN 4 -#define VIMS_CTL_SYSBUS_LB_DIS_M 0x00000010 -#define VIMS_CTL_SYSBUS_LB_DIS_S 4 +#define VIMS_CTL_SYSBUS_LB_DIS 0x00000010 +#define VIMS_CTL_SYSBUS_LB_DIS_BITN 4 +#define VIMS_CTL_SYSBUS_LB_DIS_M 0x00000010 +#define VIMS_CTL_SYSBUS_LB_DIS_S 4 // Field: [3] ARB_CFG // @@ -168,10 +168,10 @@ // // 0: Static arbitration (icode/docde > sysbus) // 1: Round-robin arbitration -#define VIMS_CTL_ARB_CFG 0x00000008 -#define VIMS_CTL_ARB_CFG_BITN 3 -#define VIMS_CTL_ARB_CFG_M 0x00000008 -#define VIMS_CTL_ARB_CFG_S 3 +#define VIMS_CTL_ARB_CFG 0x00000008 +#define VIMS_CTL_ARB_CFG_BITN 3 +#define VIMS_CTL_ARB_CFG_M 0x00000008 +#define VIMS_CTL_ARB_CFG_S 3 // Field: [2] PREF_EN // @@ -179,10 +179,10 @@ // // 0: Disabled // 1: Enabled -#define VIMS_CTL_PREF_EN 0x00000004 -#define VIMS_CTL_PREF_EN_BITN 2 -#define VIMS_CTL_PREF_EN_M 0x00000004 -#define VIMS_CTL_PREF_EN_S 2 +#define VIMS_CTL_PREF_EN 0x00000004 +#define VIMS_CTL_PREF_EN_BITN 2 +#define VIMS_CTL_PREF_EN_M 0x00000004 +#define VIMS_CTL_PREF_EN_S 2 // Field: [1:0] MODE // @@ -195,12 +195,11 @@ // OFF VIMS Off mode // CACHE VIMS Cache mode // GPRAM VIMS GPRAM mode -#define VIMS_CTL_MODE_W 2 -#define VIMS_CTL_MODE_M 0x00000003 -#define VIMS_CTL_MODE_S 0 -#define VIMS_CTL_MODE_OFF 0x00000003 -#define VIMS_CTL_MODE_CACHE 0x00000001 -#define VIMS_CTL_MODE_GPRAM 0x00000000 - +#define VIMS_CTL_MODE_W 2 +#define VIMS_CTL_MODE_M 0x00000003 +#define VIMS_CTL_MODE_S 0 +#define VIMS_CTL_MODE_OFF 0x00000003 +#define VIMS_CTL_MODE_CACHE 0x00000001 +#define VIMS_CTL_MODE_GPRAM 0x00000000 #endif // __VIMS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_wdt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_wdt.h index 3a67579..3d678d8 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_wdt.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/inc/hw_wdt.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_wdt_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_wdt_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_WDT_H__ #define __HW_WDT_H__ @@ -44,31 +44,31 @@ // //***************************************************************************** // Configuration -#define WDT_O_LOAD 0x00000000 +#define WDT_O_LOAD 0x00000000 // Current Count Value -#define WDT_O_VALUE 0x00000004 +#define WDT_O_VALUE 0x00000004 // Control -#define WDT_O_CTL 0x00000008 +#define WDT_O_CTL 0x00000008 // Interrupt Clear -#define WDT_O_ICR 0x0000000C +#define WDT_O_ICR 0x0000000C // Raw Interrupt Status -#define WDT_O_RIS 0x00000010 +#define WDT_O_RIS 0x00000010 // Masked Interrupt Status -#define WDT_O_MIS 0x00000014 +#define WDT_O_MIS 0x00000014 // Test Mode -#define WDT_O_TEST 0x00000418 +#define WDT_O_TEST 0x00000418 // Interrupt Cause Test Mode -#define WDT_O_INT_CAUS 0x0000041C +#define WDT_O_INT_CAUS 0x0000041C // Lock -#define WDT_O_LOCK 0x00000C00 +#define WDT_O_LOCK 0x00000C00 //***************************************************************************** // @@ -81,9 +81,9 @@ // this register is written, the value is immediately loaded and the counter is // restarted to count down from the new value. If this register is loaded with // 0x0000.0000, an interrupt is immediately generated. -#define WDT_LOAD_WDTLOAD_W 32 -#define WDT_LOAD_WDTLOAD_M 0xFFFFFFFF -#define WDT_LOAD_WDTLOAD_S 0 +#define WDT_LOAD_WDTLOAD_W 32 +#define WDT_LOAD_WDTLOAD_M 0xFFFFFFFF +#define WDT_LOAD_WDTLOAD_S 0 //***************************************************************************** // @@ -93,9 +93,9 @@ // Field: [31:0] WDTVALUE // // This register contains the current count value of the timer. -#define WDT_VALUE_WDTVALUE_W 32 -#define WDT_VALUE_WDTVALUE_M 0xFFFFFFFF -#define WDT_VALUE_WDTVALUE_S 0 +#define WDT_VALUE_WDTVALUE_W 32 +#define WDT_VALUE_WDTVALUE_M 0xFFFFFFFF +#define WDT_VALUE_WDTVALUE_S 0 //***************************************************************************** // @@ -111,12 +111,12 @@ // ENUMs: // NONMASKABLE Non-maskable interrupt // MASKABLE Maskable interrupt -#define WDT_CTL_INTTYPE 0x00000004 -#define WDT_CTL_INTTYPE_BITN 2 -#define WDT_CTL_INTTYPE_M 0x00000004 -#define WDT_CTL_INTTYPE_S 2 -#define WDT_CTL_INTTYPE_NONMASKABLE 0x00000004 -#define WDT_CTL_INTTYPE_MASKABLE 0x00000000 +#define WDT_CTL_INTTYPE 0x00000004 +#define WDT_CTL_INTTYPE_BITN 2 +#define WDT_CTL_INTTYPE_M 0x00000004 +#define WDT_CTL_INTTYPE_S 2 +#define WDT_CTL_INTTYPE_NONMASKABLE 0x00000004 +#define WDT_CTL_INTTYPE_MASKABLE 0x00000000 // Field: [1] RESEN // @@ -128,12 +128,12 @@ // ENUMs: // EN Reset output Enabled // DIS Reset output Disabled -#define WDT_CTL_RESEN 0x00000002 -#define WDT_CTL_RESEN_BITN 1 -#define WDT_CTL_RESEN_M 0x00000002 -#define WDT_CTL_RESEN_S 1 -#define WDT_CTL_RESEN_EN 0x00000002 -#define WDT_CTL_RESEN_DIS 0x00000000 +#define WDT_CTL_RESEN 0x00000002 +#define WDT_CTL_RESEN_BITN 1 +#define WDT_CTL_RESEN_M 0x00000002 +#define WDT_CTL_RESEN_S 1 +#define WDT_CTL_RESEN_EN 0x00000002 +#define WDT_CTL_RESEN_DIS 0x00000000 // Field: [0] INTEN // @@ -145,12 +145,12 @@ // ENUMs: // EN Interrupt Enabled // DIS Interrupt Disabled -#define WDT_CTL_INTEN 0x00000001 -#define WDT_CTL_INTEN_BITN 0 -#define WDT_CTL_INTEN_M 0x00000001 -#define WDT_CTL_INTEN_S 0 -#define WDT_CTL_INTEN_EN 0x00000001 -#define WDT_CTL_INTEN_DIS 0x00000000 +#define WDT_CTL_INTEN 0x00000001 +#define WDT_CTL_INTEN_BITN 0 +#define WDT_CTL_INTEN_M 0x00000001 +#define WDT_CTL_INTEN_S 0 +#define WDT_CTL_INTEN_EN 0x00000001 +#define WDT_CTL_INTEN_DIS 0x00000000 //***************************************************************************** // @@ -162,9 +162,9 @@ // This register is the interrupt clear register. A write of any value to this // register clears the WDT interrupt and reloads the 32-bit counter from the // LOAD register. -#define WDT_ICR_WDTICR_W 32 -#define WDT_ICR_WDTICR_M 0xFFFFFFFF -#define WDT_ICR_WDTICR_S 0 +#define WDT_ICR_WDTICR_W 32 +#define WDT_ICR_WDTICR_M 0xFFFFFFFF +#define WDT_ICR_WDTICR_S 0 //***************************************************************************** // @@ -181,10 +181,10 @@ // 0: The WDT has not timed out // 1: A WDT time-out event has occurred // -#define WDT_RIS_WDTRIS 0x00000001 -#define WDT_RIS_WDTRIS_BITN 0 -#define WDT_RIS_WDTRIS_M 0x00000001 -#define WDT_RIS_WDTRIS_S 0 +#define WDT_RIS_WDTRIS 0x00000001 +#define WDT_RIS_WDTRIS_BITN 0 +#define WDT_RIS_WDTRIS_M 0x00000001 +#define WDT_RIS_WDTRIS_S 0 //***************************************************************************** // @@ -201,10 +201,10 @@ // // 0: The WDT has not timed out or is masked. // 1: An unmasked WDT time-out event has occurred. -#define WDT_MIS_WDTMIS 0x00000001 -#define WDT_MIS_WDTMIS_BITN 0 -#define WDT_MIS_WDTMIS_M 0x00000001 -#define WDT_MIS_WDTMIS_S 0 +#define WDT_MIS_WDTMIS 0x00000001 +#define WDT_MIS_WDTMIS_BITN 0 +#define WDT_MIS_WDTMIS_M 0x00000001 +#define WDT_MIS_WDTMIS_S 0 //***************************************************************************** // @@ -221,12 +221,12 @@ // ENUMs: // EN Enable STALL // DIS Disable STALL -#define WDT_TEST_STALL 0x00000100 -#define WDT_TEST_STALL_BITN 8 -#define WDT_TEST_STALL_M 0x00000100 -#define WDT_TEST_STALL_S 8 -#define WDT_TEST_STALL_EN 0x00000100 -#define WDT_TEST_STALL_DIS 0x00000000 +#define WDT_TEST_STALL 0x00000100 +#define WDT_TEST_STALL_BITN 8 +#define WDT_TEST_STALL_M 0x00000100 +#define WDT_TEST_STALL_S 8 +#define WDT_TEST_STALL_EN 0x00000100 +#define WDT_TEST_STALL_DIS 0x00000000 // Field: [0] TEST_EN // @@ -238,12 +238,12 @@ // ENUMs: // EN Test mode Enabled // DIS Test mode Disabled -#define WDT_TEST_TEST_EN 0x00000001 -#define WDT_TEST_TEST_EN_BITN 0 -#define WDT_TEST_TEST_EN_M 0x00000001 -#define WDT_TEST_TEST_EN_S 0 -#define WDT_TEST_TEST_EN_EN 0x00000001 -#define WDT_TEST_TEST_EN_DIS 0x00000000 +#define WDT_TEST_TEST_EN 0x00000001 +#define WDT_TEST_TEST_EN_BITN 0 +#define WDT_TEST_TEST_EN_M 0x00000001 +#define WDT_TEST_TEST_EN_S 0 +#define WDT_TEST_TEST_EN_EN 0x00000001 +#define WDT_TEST_TEST_EN_DIS 0x00000000 //***************************************************************************** // @@ -254,18 +254,18 @@ // // Indicates that the cause of an interrupt was a reset generated but blocked // due to TEST.TEST_EN (only possible when TEST.TEST_EN is set). -#define WDT_INT_CAUS_CAUSE_RESET 0x00000002 -#define WDT_INT_CAUS_CAUSE_RESET_BITN 1 -#define WDT_INT_CAUS_CAUSE_RESET_M 0x00000002 -#define WDT_INT_CAUS_CAUSE_RESET_S 1 +#define WDT_INT_CAUS_CAUSE_RESET 0x00000002 +#define WDT_INT_CAUS_CAUSE_RESET_BITN 1 +#define WDT_INT_CAUS_CAUSE_RESET_M 0x00000002 +#define WDT_INT_CAUS_CAUSE_RESET_S 1 // Field: [0] CAUSE_INTR // // Replica of RIS.WDTRIS -#define WDT_INT_CAUS_CAUSE_INTR 0x00000001 -#define WDT_INT_CAUS_CAUSE_INTR_BITN 0 -#define WDT_INT_CAUS_CAUSE_INTR_M 0x00000001 -#define WDT_INT_CAUS_CAUSE_INTR_S 0 +#define WDT_INT_CAUS_CAUSE_INTR 0x00000001 +#define WDT_INT_CAUS_CAUSE_INTR_BITN 0 +#define WDT_INT_CAUS_CAUSE_INTR_M 0x00000001 +#define WDT_INT_CAUS_CAUSE_INTR_S 0 //***************************************************************************** // @@ -282,9 +282,8 @@ // // 0x0000.0000: Unlocked // 0x0000.0001: Locked -#define WDT_LOCK_WDTLOCK_W 32 -#define WDT_LOCK_WDTLOCK_M 0xFFFFFFFF -#define WDT_LOCK_WDTLOCK_S 0 - +#define WDT_LOCK_WDTLOCK_W 32 +#define WDT_LOCK_WDTLOCK_M 0xFFFFFFFF +#define WDT_LOCK_WDTLOCK_S 0 #endif // __WDT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ant_div.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ant_div.h index dd9f1e1..fdab578 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ant_div.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ant_div.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_patch_cpe_ant_div.h -* Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ -* Revision: $Revision: 18756 $ -* -* Description: RF core patch for CC13x0 Generic FSK antenna diversity -* -* Copyright (c) 2015, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_cpe_ant_div.h + * Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ + * Revision: $Revision: 18756 $ + * + * Description: RF core patch for CC13x0 Generic FSK antenna diversity + * + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_CPE_ANT_DIV_H #define _RF_PATCH_CPE_ANT_DIV_H @@ -46,8 +46,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include @@ -69,256 +68,255 @@ extern "C" #define _APPLY_PATCH_TAB #endif - CPE_PATCH_TYPE patchImageAntDiv[] = -{ - 0x21000569, - 0x2100045d, - 0x21000491, - 0x21000495, - 0x210004bd, - 0x2100064d, - 0x210006fd, - 0x21000725, - 0x2100052b, - 0x210004f1, - 0x21000767, - 0x21000789, - 0x4710b5f8, - 0x460eb5f8, - 0x25012100, - 0x473004ad, - 0x7803480a, - 0xf80ff000, - 0xd00b079b, - 0x78204c12, - 0xd00728ff, - 0x702121ff, - 0x240f490e, - 0x43200224, - 0x82c83160, - 0xb5f8bdf8, - 0x47004801, - 0x2100026b, - 0x00004ce5, - 0xe0014809, - 0x0c004808, - 0x49054c06, - 0x2aff7822, - 0x7acad101, - 0x31607022, - 0x467082c8, - 0x47001c80, - 0x40086200, - 0x210007f4, - 0x08080f07, - 0xf886f000, - 0x0a0a9905, - 0xd1092a6c, - 0x61782008, - 0x1c406920, - 0x310a6038, - 0x91056120, - 0x61782000, - 0x0000bdf8, - 0x4708b4f0, - 0x4801b510, - 0x00004700, - 0x00000989, - 0xf818f000, - 0x2950b2e1, - 0x2804d00b, - 0x2806d001, - 0x490dd107, - 0x07c97809, - 0x7821d103, - 0xd4000709, - 0x490a2002, - 0x210c780a, - 0xd0024211, - 0x22804908, - 0xbdfe600a, - 0x4907b5fe, - 0x48044708, - 0x22407801, - 0x70014391, - 0x47004804, - 0x210000c8, - 0x21000117, - 0xe000e200, - 0x0000ccf1, - 0x0000d103, - 0x4605b5ff, - 0x4c03b085, - 0xb5ff4720, - 0x01deb085, - 0x47204c01, - 0x00003ff7, - 0x000041cb, - 0x4603b570, - 0x29014615, - 0x2900d006, - 0x4a11d006, - 0xf7ff4628, - 0xbd70ff67, - 0xe000480f, - 0x2405480f, - 0xd8034283, - 0x1e640840, - 0xdcf92c00, - 0x200140e3, - 0x18180340, - 0x29010b82, - 0x4906d007, - 0x31802300, - 0xf7ff4628, - 0xb2e0ff51, - 0x4902bd70, - 0x316c4b04, - 0x0000e7f6, - 0x00005c83, - 0x2386bca0, - 0x230d8300, - 0x210007c4, - 0x4e1ab5f8, - 0x6b714605, - 0x09cc4819, - 0x2d0001e4, - 0x4918d011, - 0x29027809, - 0x7b00d00f, - 0xb6724304, - 0x4f152001, - 0x47b80240, - 0x38204811, - 0x09c18800, - 0xd00407c9, - 0x7ac0e016, - 0x7b40e7f0, - 0x490fe7ee, - 0x61cc6374, - 0x07c00a40, - 0x2001d00c, - 0x6b310380, - 0xd0012d00, - 0xe0004301, - 0x46084381, - 0x49076331, - 0x63483940, - 0x47b82000, - 0xbdf8b662, - 0x21000280, - 0x21000088, - 0x2100029b, - 0x00003f7b, - 0x40044040, - 0x4a22b510, - 0x61512100, - 0x68894921, - 0xd40900c9, - 0x4b204921, - 0x429805ca, - 0xd8016b4b, - 0xe0004313, - 0x634b4393, - 0xf7ff491d, - 0xbd10ff35, - 0x4d1ab538, - 0x28007f28, - 0x481ad127, - 0x09c08800, - 0xd12207c0, - 0x69604c12, - 0xd11e2800, - 0xf0004668, - 0x4668f88f, - 0x28017800, - 0x4668d117, - 0x28107840, - 0x2008d213, - 0x6a686160, - 0x01400940, - 0x4a0e6020, - 0x62d12100, - 0x21024a0d, - 0x21016011, - 0x60204308, - 0x43082103, - 0x60206268, - 0x4809bd38, - 0xbd384780, - 0x40044000, - 0x21000018, - 0x08930000, - 0x21000280, - 0x000068cf, - 0x21000068, - 0x40041100, - 0xe000e280, - 0x00003bc3, - 0x28004907, - 0x2004d000, - 0xb6724a06, - 0x07c97809, - 0x5810d001, - 0x2080e000, - 0xb240b662, - 0x00004770, - 0x2100026b, - 0x40046058, - 0x4c03b510, - 0xfedcf7ff, - 0x28006820, - 0xbd10d1fa, - 0x40041100, - 0x2041b510, - 0x00c0490e, - 0x490e4788, - 0x6b884602, - 0x24906b49, - 0x04c1014b, - 0x430b0ec9, - 0x4363490a, - 0x43597d49, - 0x689b4b09, - 0xfef9f7ff, - 0xb510bd10, - 0xfef0f7ff, - 0xd1010004, - 0xffe2f7ff, - 0xbd104620, - 0x00003c7d, - 0x40045080, - 0x21000280, - 0x40044000, - 0x8801b510, - 0x0f93050a, - 0xd1034a08, - 0x0d890589, - 0xd0012911, - 0xbd104790, - 0x46044790, - 0xd1032801, - 0xf7ffb672, - 0xb662ffc5, - 0xbd104620, - 0x00002645, - 0x4801b403, - 0xbd019001, - 0x00006fa5, - 0x00000000, - 0x00030001, - 0x001f000a, - 0x00eb0059, - 0x04ea0239, - 0x129709f9, - 0x32a11feb, - 0x660a4a78, - 0x9e8c82fa, - 0xc917b663, - 0xdeedd664, - 0xe5e0e3c1, - 0x000000ff, + { + 0x21000569, + 0x2100045d, + 0x21000491, + 0x21000495, + 0x210004bd, + 0x2100064d, + 0x210006fd, + 0x21000725, + 0x2100052b, + 0x210004f1, + 0x21000767, + 0x21000789, + 0x4710b5f8, + 0x460eb5f8, + 0x25012100, + 0x473004ad, + 0x7803480a, + 0xf80ff000, + 0xd00b079b, + 0x78204c12, + 0xd00728ff, + 0x702121ff, + 0x240f490e, + 0x43200224, + 0x82c83160, + 0xb5f8bdf8, + 0x47004801, + 0x2100026b, + 0x00004ce5, + 0xe0014809, + 0x0c004808, + 0x49054c06, + 0x2aff7822, + 0x7acad101, + 0x31607022, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210007f4, + 0x08080f07, + 0xf886f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4708b4f0, + 0x4801b510, + 0x00004700, + 0x00000989, + 0xf818f000, + 0x2950b2e1, + 0x2804d00b, + 0x2806d001, + 0x490dd107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490a2002, + 0x210c780a, + 0xd0024211, + 0x22804908, + 0xbdfe600a, + 0x4907b5fe, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000117, + 0xe000e200, + 0x0000ccf1, + 0x0000d103, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4603b570, + 0x29014615, + 0x2900d006, + 0x4a11d006, + 0xf7ff4628, + 0xbd70ff67, + 0xe000480f, + 0x2405480f, + 0xd8034283, + 0x1e640840, + 0xdcf92c00, + 0x200140e3, + 0x18180340, + 0x29010b82, + 0x4906d007, + 0x31802300, + 0xf7ff4628, + 0xb2e0ff51, + 0x4902bd70, + 0x316c4b04, + 0x0000e7f6, + 0x00005c83, + 0x2386bca0, + 0x230d8300, + 0x210007c4, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x4a22b510, + 0x61512100, + 0x68894921, + 0xd40900c9, + 0x4b204921, + 0x429805ca, + 0xd8016b4b, + 0xe0004313, + 0x634b4393, + 0xf7ff491d, + 0xbd10ff35, + 0x4d1ab538, + 0x28007f28, + 0x481ad127, + 0x09c08800, + 0xd12207c0, + 0x69604c12, + 0xd11e2800, + 0xf0004668, + 0x4668f88f, + 0x28017800, + 0x4668d117, + 0x28107840, + 0x2008d213, + 0x6a686160, + 0x01400940, + 0x4a0e6020, + 0x62d12100, + 0x21024a0d, + 0x21016011, + 0x60204308, + 0x43082103, + 0x60206268, + 0x4809bd38, + 0xbd384780, + 0x40044000, + 0x21000018, + 0x08930000, + 0x21000280, + 0x000068cf, + 0x21000068, + 0x40041100, + 0xe000e280, + 0x00003bc3, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x4c03b510, + 0xfedcf7ff, + 0x28006820, + 0xbd10d1fa, + 0x40041100, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfef9f7ff, + 0xb510bd10, + 0xfef0f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x8801b510, + 0x0f93050a, + 0xd1034a08, + 0x0d890589, + 0xd0012911, + 0xbd104790, + 0x46044790, + 0xd1032801, + 0xf7ffb672, + 0xb662ffc5, + 0xbd104620, + 0x00002645, + 0x4801b403, + 0xbd019001, + 0x00006fa5, + 0x00000000, + 0x00030001, + 0x001f000a, + 0x00eb0059, + 0x04ea0239, + 0x129709f9, + 0x32a11feb, + 0x660a4a78, + 0x9e8c82fa, + 0xc917b663, + 0xdeedd664, + 0xe5e0e3c1, + 0x000000ff, }; #define _NWORD_PATCHIMAGE_ANT_DIV 247 @@ -326,7 +324,6 @@ CPE_PATCH_TYPE patchImageAntDiv[] = #define _IRQ_PATCH_0 0x21000679 - #ifndef _ANT_DIV_SYSRAM_START #define _ANT_DIV_SYSRAM_START 0x20000000 #endif @@ -345,7 +342,7 @@ CPE_PATCH_TYPE patchImageAntDiv[] = PATCH_FUN_SPEC void enterAntDivCpePatch(void) { #if (_NWORD_PATCHIMAGE_ANT_DIV > 0) - uint32_t* pPatchVec = (uint32_t*) (_ANT_DIV_CPERAM_START + _ANT_DIV_PATCH_VEC_OFFSET); + uint32_t* pPatchVec = (uint32_t*)(_ANT_DIV_CPERAM_START + _ANT_DIV_PATCH_VEC_OFFSET); memcpy(pPatchVec, patchImageAntDiv, sizeof(patchImageAntDiv)); #endif @@ -357,10 +354,9 @@ PATCH_FUN_SPEC void enterAntDivSysPatch(void) PATCH_FUN_SPEC void configureAntDivPatch(void) { - uint8_t* pParserPatchTab = (uint8_t*) (_ANT_DIV_CPERAM_START + _ANT_DIV_PARSER_PATCH_TAB_OFFSET); - uint8_t* pPatchTab = (uint8_t*) (_ANT_DIV_CPERAM_START + _ANT_DIV_PATCH_TAB_OFFSET); - uint32_t* pIrqPatch = (uint32_t*) (_ANT_DIV_CPERAM_START + _ANT_DIV_IRQPATCH_OFFSET); - + uint8_t* pParserPatchTab = (uint8_t*)(_ANT_DIV_CPERAM_START + _ANT_DIV_PARSER_PATCH_TAB_OFFSET); + uint8_t* pPatchTab = (uint8_t*)(_ANT_DIV_CPERAM_START + _ANT_DIV_PATCH_TAB_OFFSET); + uint32_t* pIrqPatch = (uint32_t*)(_ANT_DIV_CPERAM_START + _ANT_DIV_IRQPATCH_OFFSET); pPatchTab[80] = 0; pPatchTab[57] = 1; @@ -408,4 +404,3 @@ PATCH_FUN_SPEC void rf_patch_cpe_ant_div(void) #endif #endif // _RF_PATCH_CPE_ANT_DIV_H - diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ble.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ble.h index ff23285..0e0f948 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ble.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ble.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_patch_cpe_ble.h -* Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ -* Revision: $Revision: 18438 $ -* -* Description: RF Core patch file for CC1350 Bluetooth Low Energy -* -* Copyright (c) 2015, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_cpe_ble.h + * Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ + * Revision: $Revision: 18438 $ + * + * Description: RF Core patch file for CC1350 Bluetooth Low Energy + * + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_CPE_BLE_H #define _RF_PATCH_CPE_BLE_H @@ -46,8 +46,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include @@ -69,124 +68,121 @@ extern "C" #define _APPLY_PATCH_TAB #endif - CPE_PATCH_TYPE patchImageBle[] = -{ - 0x21000439, - 0x2100044b, - 0x2100044b, - 0x21000471, - 0x21000551, - 0x21000495, - 0x210005a7, - 0x490b4c0c, - 0x28ff7820, - 0x7ac8d101, - 0x20077020, - 0x4c08e006, - 0x28ff7820, - 0x21ffd007, - 0x49047021, - 0x0224240f, - 0x31604320, - 0x467082c8, - 0x47001c80, - 0x40086200, - 0x210005c8, - 0xf82ef000, - 0x0a0a9905, - 0xd1092a6c, - 0x61782008, - 0x1c406920, - 0x310a6038, - 0x91056120, - 0x61782000, - 0x0000bdf8, - 0x4905b570, - 0xb6724a05, - 0x28017908, - 0x2001dc02, - 0x1d127088, - 0x4710b662, - 0x21000298, - 0x00004a81, - 0x4605b5ff, - 0x4c03b085, - 0xb5ff4720, - 0x01deb085, - 0x47204c01, - 0x00003ff7, - 0x000041cb, - 0x4e1ab5f8, - 0x6b714605, - 0x09cc4819, - 0x2d0001e4, - 0x4918d011, - 0x29027809, - 0x7b00d00f, - 0xb6724304, - 0x4f152001, - 0x47b80240, - 0x38204811, - 0x09c18800, - 0xd00407c9, - 0x7ac0e016, - 0x7b40e7f0, - 0x490fe7ee, - 0x61cc6374, - 0x07c00a40, - 0x2001d00c, - 0x6b310380, - 0xd0012d00, - 0xe0004301, - 0x46084381, - 0x49076331, - 0x63483940, - 0x47b82000, - 0xbdf8b662, - 0x21000280, - 0x21000088, - 0x2100029b, - 0x00003f7b, - 0x40044040, - 0x28004907, - 0x2004d000, - 0xb6724a06, - 0x07c97809, - 0x5810d001, - 0x2080e000, - 0xb240b662, - 0x00004770, - 0x2100026b, - 0x40046058, - 0x2041b510, - 0x00c0490e, - 0x490e4788, - 0x6b884602, - 0x24906b49, - 0x04c1014b, - 0x430b0ec9, - 0x4363490a, - 0x43597d49, - 0x689b4b09, - 0xff8df7ff, - 0xb510bd10, - 0xff84f7ff, - 0xd1010004, - 0xffe2f7ff, - 0xbd104620, - 0x00003c7d, - 0x40045080, - 0x21000280, - 0x40044000, - 0x000000ff, + { + 0x21000439, + 0x2100044b, + 0x2100044b, + 0x21000471, + 0x21000551, + 0x21000495, + 0x210005a7, + 0x490b4c0c, + 0x28ff7820, + 0x7ac8d101, + 0x20077020, + 0x4c08e006, + 0x28ff7820, + 0x21ffd007, + 0x49047021, + 0x0224240f, + 0x31604320, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210005c8, + 0xf82ef000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4905b570, + 0xb6724a05, + 0x28017908, + 0x2001dc02, + 0x1d127088, + 0x4710b662, + 0x21000298, + 0x00004a81, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xff8df7ff, + 0xb510bd10, + 0xff84f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x000000ff, }; #define _NWORD_PATCHIMAGE_BLE 108 #define _NWORD_PATCHSYS_BLE 0 - - #ifndef _BLE_SYSRAM_START #define _BLE_SYSRAM_START 0x20000000 #endif @@ -205,7 +201,7 @@ CPE_PATCH_TYPE patchImageBle[] = PATCH_FUN_SPEC void enterBleCpePatch(void) { #if (_NWORD_PATCHIMAGE_BLE > 0) - uint32_t* pPatchVec = (uint32_t*) (_BLE_CPERAM_START + _BLE_PATCH_VEC_OFFSET); + uint32_t* pPatchVec = (uint32_t*)(_BLE_CPERAM_START + _BLE_PATCH_VEC_OFFSET); memcpy(pPatchVec, patchImageBle, sizeof(patchImageBle)); #endif @@ -217,8 +213,7 @@ PATCH_FUN_SPEC void enterBleSysPatch(void) PATCH_FUN_SPEC void configureBlePatch(void) { - uint8_t* pPatchTab = (uint8_t*) (_BLE_CPERAM_START + _BLE_PATCH_TAB_OFFSET); - + uint8_t* pPatchTab = (uint8_t*)(_BLE_CPERAM_START + _BLE_PATCH_TAB_OFFSET); pPatchTab[112] = 0; pPatchTab[104] = 1; @@ -247,7 +242,6 @@ PATCH_FUN_SPEC void rf_patch_cpe_ble(void) applyBlePatch(); } - //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. @@ -258,4 +252,3 @@ PATCH_FUN_SPEC void rf_patch_cpe_ble(void) #endif #endif // _RF_PATCH_CPE_BLE_H - diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ble_priv_1_2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ble_priv_1_2.h index 8d10955..eae1bf0 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ble_priv_1_2.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ble_priv_1_2.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_patch_cpe_ble_priv_1_2.h -* Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ -* Revision: $Revision: 18438 $ -* -* Description: RF Core patch file for CC1350 Bluetooth Low Energy with privacy 1.2 support -* -* Copyright (c) 2015, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_cpe_ble_priv_1_2.h + * Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ + * Revision: $Revision: 18438 $ + * + * Description: RF Core patch file for CC1350 Bluetooth Low Energy with privacy 1.2 support + * + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_CPE_BLE_PRIV_1_2_H #define _RF_PATCH_CPE_BLE_PRIV_1_2_H @@ -46,8 +46,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include @@ -69,218 +68,215 @@ extern "C" #define _APPLY_PATCH_TAB #endif - CPE_PATCH_TYPE patchImageBlePriv12[] = -{ - 0x210005fd, - 0x2100043d, - 0x2100044f, - 0x2100044f, - 0x21000475, - 0x210006c9, - 0x21000499, - 0x2100071f, - 0x490b4c0c, - 0x28ff7820, - 0x7ac8d101, - 0x20077020, - 0x4c08e006, - 0x28ff7820, - 0x21ffd007, - 0x49047021, - 0x0224240f, - 0x31604320, - 0x467082c8, - 0x47001c80, - 0x40086200, - 0x21000740, - 0xf8e8f000, - 0x0a0a9905, - 0xd1092a6c, - 0x61782008, - 0x1c406920, - 0x310a6038, - 0x91056120, - 0x61782000, - 0x0000bdf8, - 0x4905b570, - 0xb6724a05, - 0x28017908, - 0x2001dc02, - 0x1d127088, - 0x4710b662, - 0x21000298, - 0x00004a81, - 0x4605b5ff, - 0x4c03b085, - 0xb5ff4720, - 0x01deb085, - 0x47204c01, - 0x00003ff7, - 0x000041cb, - 0x4d53b5fe, - 0x462c4628, - 0x90003040, - 0x7e014627, - 0x78383760, - 0xd0022900, - 0xd10707c0, - 0x09c1e050, - 0x07c0d04e, - 0x7d20d14c, - 0xd5490640, - 0x31724629, - 0x20064a48, - 0x98004790, - 0x28007e00, - 0x7d20d007, - 0xd5010640, - 0xe0002003, - 0x26132001, - 0x6f68e008, - 0x28010f80, - 0x2006d002, - 0xe0014606, - 0x26072003, - 0x02312201, - 0x1a890412, - 0x02008a7a, - 0x43020412, - 0x35806f6b, - 0x68a89501, - 0x47a84d37, - 0x2e062201, - 0x2e07d002, - 0xe007d002, - 0xe00543c0, - 0x70797839, - 0x70394311, - 0x61089901, - 0xda012800, - 0x55022039, - 0x7e809800, - 0xd0022800, - 0x201e2106, - 0x6a61e002, - 0x201f1f89, - 0x6ca162a1, - 0x64e04788, - 0xbdfe2000, - 0x47804826, - 0x4822bdfe, - 0x78413060, - 0xd0022900, - 0x21007001, - 0x48217041, - 0x470038b0, - 0x4e1cb5f8, - 0x4635481f, - 0x7fec3540, - 0x09e14637, - 0x6db1d01a, - 0xd0172901, - 0x29007f69, - 0x07a1d002, - 0xe011d502, - 0xd10f07e1, - 0x06497d39, - 0x2103d50c, - 0x77e94321, - 0x6f314780, - 0x29010f89, - 0x2100d002, - 0x76793720, - 0xbdf877ec, - 0xbdf84780, - 0x31404909, - 0x28157508, - 0x281bd008, - 0x281dd008, - 0x490ad008, - 0x18400080, - 0x47706980, - 0x47704808, - 0x47704808, - 0x47704808, - 0x21000144, - 0x000100af, - 0x0000e801, - 0x00010603, - 0x0001018d, - 0x000114c0, - 0x210005b1, - 0x2100059b, - 0x210004d5, - 0x4e1ab5f8, - 0x6b714605, - 0x09cc4819, - 0x2d0001e4, - 0x4918d011, - 0x29027809, - 0x7b00d00f, - 0xb6724304, - 0x4f152001, - 0x47b80240, - 0x38204811, - 0x09c18800, - 0xd00407c9, - 0x7ac0e016, - 0x7b40e7f0, - 0x490fe7ee, - 0x61cc6374, - 0x07c00a40, - 0x2001d00c, - 0x6b310380, - 0xd0012d00, - 0xe0004301, - 0x46084381, - 0x49076331, - 0x63483940, - 0x47b82000, - 0xbdf8b662, - 0x21000280, - 0x21000088, - 0x2100029b, - 0x00003f7b, - 0x40044040, - 0x28004907, - 0x2004d000, - 0xb6724a06, - 0x07c97809, - 0x5810d001, - 0x2080e000, - 0xb240b662, - 0x00004770, - 0x2100026b, - 0x40046058, - 0x2041b510, - 0x00c0490e, - 0x490e4788, - 0x6b884602, - 0x24906b49, - 0x04c1014b, - 0x430b0ec9, - 0x4363490a, - 0x43597d49, - 0x689b4b09, - 0xfed3f7ff, - 0xb510bd10, - 0xfecaf7ff, - 0xd1010004, - 0xffe2f7ff, - 0xbd104620, - 0x00003c7d, - 0x40045080, - 0x21000280, - 0x40044000, - 0x000000ff, + { + 0x210005fd, + 0x2100043d, + 0x2100044f, + 0x2100044f, + 0x21000475, + 0x210006c9, + 0x21000499, + 0x2100071f, + 0x490b4c0c, + 0x28ff7820, + 0x7ac8d101, + 0x20077020, + 0x4c08e006, + 0x28ff7820, + 0x21ffd007, + 0x49047021, + 0x0224240f, + 0x31604320, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x21000740, + 0xf8e8f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4905b570, + 0xb6724a05, + 0x28017908, + 0x2001dc02, + 0x1d127088, + 0x4710b662, + 0x21000298, + 0x00004a81, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4d53b5fe, + 0x462c4628, + 0x90003040, + 0x7e014627, + 0x78383760, + 0xd0022900, + 0xd10707c0, + 0x09c1e050, + 0x07c0d04e, + 0x7d20d14c, + 0xd5490640, + 0x31724629, + 0x20064a48, + 0x98004790, + 0x28007e00, + 0x7d20d007, + 0xd5010640, + 0xe0002003, + 0x26132001, + 0x6f68e008, + 0x28010f80, + 0x2006d002, + 0xe0014606, + 0x26072003, + 0x02312201, + 0x1a890412, + 0x02008a7a, + 0x43020412, + 0x35806f6b, + 0x68a89501, + 0x47a84d37, + 0x2e062201, + 0x2e07d002, + 0xe007d002, + 0xe00543c0, + 0x70797839, + 0x70394311, + 0x61089901, + 0xda012800, + 0x55022039, + 0x7e809800, + 0xd0022800, + 0x201e2106, + 0x6a61e002, + 0x201f1f89, + 0x6ca162a1, + 0x64e04788, + 0xbdfe2000, + 0x47804826, + 0x4822bdfe, + 0x78413060, + 0xd0022900, + 0x21007001, + 0x48217041, + 0x470038b0, + 0x4e1cb5f8, + 0x4635481f, + 0x7fec3540, + 0x09e14637, + 0x6db1d01a, + 0xd0172901, + 0x29007f69, + 0x07a1d002, + 0xe011d502, + 0xd10f07e1, + 0x06497d39, + 0x2103d50c, + 0x77e94321, + 0x6f314780, + 0x29010f89, + 0x2100d002, + 0x76793720, + 0xbdf877ec, + 0xbdf84780, + 0x31404909, + 0x28157508, + 0x281bd008, + 0x281dd008, + 0x490ad008, + 0x18400080, + 0x47706980, + 0x47704808, + 0x47704808, + 0x47704808, + 0x21000144, + 0x000100af, + 0x0000e801, + 0x00010603, + 0x0001018d, + 0x000114c0, + 0x210005b1, + 0x2100059b, + 0x210004d5, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfed3f7ff, + 0xb510bd10, + 0xfecaf7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x000000ff, }; #define _NWORD_PATCHIMAGE_BLE_PRIV_1_2 202 #define _NWORD_PATCHSYS_BLE_PRIV_1_2 0 - - #ifndef _BLE_PRIV_1_2_SYSRAM_START #define _BLE_PRIV_1_2_SYSRAM_START 0x20000000 #endif @@ -299,7 +295,7 @@ CPE_PATCH_TYPE patchImageBlePriv12[] = PATCH_FUN_SPEC void enterBlePriv12CpePatch(void) { #if (_NWORD_PATCHIMAGE_BLE_PRIV_1_2 > 0) - uint32_t* pPatchVec = (uint32_t*) (_BLE_PRIV_1_2_CPERAM_START + _BLE_PRIV_1_2_PATCH_VEC_OFFSET); + uint32_t* pPatchVec = (uint32_t*)(_BLE_PRIV_1_2_CPERAM_START + _BLE_PRIV_1_2_PATCH_VEC_OFFSET); memcpy(pPatchVec, patchImageBlePriv12, sizeof(patchImageBlePriv12)); #endif @@ -311,8 +307,7 @@ PATCH_FUN_SPEC void enterBlePriv12SysPatch(void) PATCH_FUN_SPEC void configureBlePriv12Patch(void) { - uint8_t* pPatchTab = (uint8_t*) (_BLE_PRIV_1_2_CPERAM_START + _BLE_PRIV_1_2_PATCH_TAB_OFFSET); - + uint8_t* pPatchTab = (uint8_t*)(_BLE_PRIV_1_2_CPERAM_START + _BLE_PRIV_1_2_PATCH_TAB_OFFSET); pPatchTab[1] = 0; pPatchTab[112] = 1; @@ -342,7 +337,6 @@ PATCH_FUN_SPEC void rf_patch_cpe_ble_priv_1_2(void) applyBlePriv12Patch(); } - //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. @@ -353,4 +347,3 @@ PATCH_FUN_SPEC void rf_patch_cpe_ble_priv_1_2(void) #endif #endif // _RF_PATCH_CPE_BLE_PRIV_1_2_H - diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_brepeat.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_brepeat.h index 46f42c1..f3ed512 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_brepeat.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_brepeat.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_patch_cpe_brepeat.h -* Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ -* Revision: $Revision: 18756 $ -* -* Description: RF core patch for CC13x0 for 1.2kbps and 2.4kbps Generic FSK -* -* Copyright (c) 2015, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_cpe_brepeat.h + * Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ + * Revision: $Revision: 18756 $ + * + * Description: RF core patch for CC13x0 for 1.2kbps and 2.4kbps Generic FSK + * + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_CPE_BREPEAT_H #define _RF_PATCH_CPE_BREPEAT_H @@ -46,8 +46,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include @@ -69,256 +68,255 @@ extern "C" #define _APPLY_PATCH_TAB #endif - CPE_PATCH_TYPE patchImageBrepeat[] = -{ - 0x21000569, - 0x2100045d, - 0x21000491, - 0x21000495, - 0x210004bd, - 0x2100064d, - 0x210006fd, - 0x21000725, - 0x2100052b, - 0x210004f1, - 0x21000767, - 0x21000789, - 0x4710b5f8, - 0x460eb5f8, - 0x25012100, - 0x473004ad, - 0x7803480a, - 0xf80ff000, - 0xd00b079b, - 0x78204c12, - 0xd00728ff, - 0x702121ff, - 0x240f490e, - 0x43200224, - 0x82c83160, - 0xb5f8bdf8, - 0x47004801, - 0x2100026b, - 0x00004ce5, - 0xe0014809, - 0x0c004808, - 0x49054c06, - 0x2aff7822, - 0x7acad101, - 0x31607022, - 0x467082c8, - 0x47001c80, - 0x40086200, - 0x210007f4, - 0x08080f07, - 0xf886f000, - 0x0a0a9905, - 0xd1092a6c, - 0x61782008, - 0x1c406920, - 0x310a6038, - 0x91056120, - 0x61782000, - 0x0000bdf8, - 0x4708b4f0, - 0x4801b510, - 0x00004700, - 0x00000989, - 0xf818f000, - 0x2950b2e1, - 0x2804d00b, - 0x2806d001, - 0x490dd107, - 0x07c97809, - 0x7821d103, - 0xd4000709, - 0x490a2002, - 0x210c780a, - 0xd0024211, - 0x22804908, - 0xbdfe600a, - 0x4907b5fe, - 0x48044708, - 0x22407801, - 0x70014391, - 0x47004804, - 0x210000c8, - 0x21000117, - 0xe000e200, - 0x0000ccf1, - 0x0000d103, - 0x4605b5ff, - 0x4c03b085, - 0xb5ff4720, - 0x01deb085, - 0x47204c01, - 0x00003ff7, - 0x000041cb, - 0x4603b570, - 0x29014615, - 0x2900d006, - 0x4a11d006, - 0xf7ff4628, - 0xbd70ff67, - 0xe000480f, - 0x2405480f, - 0xd8034283, - 0x1e640840, - 0xdcf92c00, - 0x200140e3, - 0x18180340, - 0x29010b82, - 0x4906d007, - 0x31802300, - 0xf7ff4628, - 0xb2e0ff51, - 0x4902bd70, - 0x316c4b04, - 0x0000e7f6, - 0x00005c83, - 0x2386bca0, - 0x230d8300, - 0x210007c4, - 0x4e1ab5f8, - 0x6b714605, - 0x09cc4819, - 0x2d0001e4, - 0x4918d011, - 0x29027809, - 0x7b00d00f, - 0xb6724304, - 0x4f152001, - 0x47b80240, - 0x38204811, - 0x09c18800, - 0xd00407c9, - 0x7ac0e016, - 0x7b40e7f0, - 0x490fe7ee, - 0x61cc6374, - 0x07c00a40, - 0x2001d00c, - 0x6b310380, - 0xd0012d00, - 0xe0004301, - 0x46084381, - 0x49076331, - 0x63483940, - 0x47b82000, - 0xbdf8b662, - 0x21000280, - 0x21000088, - 0x2100029b, - 0x00003f7b, - 0x40044040, - 0x4a22b510, - 0x61512100, - 0x68894921, - 0xd40900c9, - 0x4b204921, - 0x429805ca, - 0xd8016b4b, - 0xe0004313, - 0x634b4393, - 0xf7ff491d, - 0xbd10ff35, - 0x4d1ab538, - 0x28007f28, - 0x481ad127, - 0x09c08800, - 0xd12207c0, - 0x69604c12, - 0xd11e2800, - 0xf0004668, - 0x4668f88f, - 0x28017800, - 0x4668d117, - 0x28107840, - 0x2008d213, - 0x6a686160, - 0x01400940, - 0x4a0e6020, - 0x62d12100, - 0x21024a0d, - 0x21016011, - 0x60204308, - 0x43082103, - 0x60206268, - 0x4809bd38, - 0xbd384780, - 0x40044000, - 0x21000018, - 0x08930000, - 0x21000280, - 0x000068cf, - 0x21000068, - 0x40041100, - 0xe000e280, - 0x00003bc3, - 0x28004907, - 0x2004d000, - 0xb6724a06, - 0x07c97809, - 0x5810d001, - 0x2080e000, - 0xb240b662, - 0x00004770, - 0x2100026b, - 0x40046058, - 0x4c03b510, - 0xfedcf7ff, - 0x28006820, - 0xbd10d1fa, - 0x40041100, - 0x2041b510, - 0x00c0490e, - 0x490e4788, - 0x6b884602, - 0x24906b49, - 0x04c1014b, - 0x430b0ec9, - 0x4363490a, - 0x43597d49, - 0x689b4b09, - 0xfef9f7ff, - 0xb510bd10, - 0xfef0f7ff, - 0xd1010004, - 0xffe2f7ff, - 0xbd104620, - 0x00003c7d, - 0x40045080, - 0x21000280, - 0x40044000, - 0x8801b510, - 0x0f93050a, - 0xd1034a08, - 0x0d890589, - 0xd0012911, - 0xbd104790, - 0x46044790, - 0xd1032801, - 0xf7ffb672, - 0xb662ffc5, - 0xbd104620, - 0x00002645, - 0x4801b403, - 0xbd019001, - 0x00006fa5, - 0x00000000, - 0x00030001, - 0x001f000a, - 0x00eb0059, - 0x04ea0239, - 0x129709f9, - 0x32a11feb, - 0x660a4a78, - 0x9e8c82fa, - 0xc917b663, - 0xdeedd664, - 0xe5e0e3c1, - 0x000000ff, + { + 0x21000569, + 0x2100045d, + 0x21000491, + 0x21000495, + 0x210004bd, + 0x2100064d, + 0x210006fd, + 0x21000725, + 0x2100052b, + 0x210004f1, + 0x21000767, + 0x21000789, + 0x4710b5f8, + 0x460eb5f8, + 0x25012100, + 0x473004ad, + 0x7803480a, + 0xf80ff000, + 0xd00b079b, + 0x78204c12, + 0xd00728ff, + 0x702121ff, + 0x240f490e, + 0x43200224, + 0x82c83160, + 0xb5f8bdf8, + 0x47004801, + 0x2100026b, + 0x00004ce5, + 0xe0014809, + 0x0c004808, + 0x49054c06, + 0x2aff7822, + 0x7acad101, + 0x31607022, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210007f4, + 0x08080f07, + 0xf886f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4708b4f0, + 0x4801b510, + 0x00004700, + 0x00000989, + 0xf818f000, + 0x2950b2e1, + 0x2804d00b, + 0x2806d001, + 0x490dd107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490a2002, + 0x210c780a, + 0xd0024211, + 0x22804908, + 0xbdfe600a, + 0x4907b5fe, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000117, + 0xe000e200, + 0x0000ccf1, + 0x0000d103, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4603b570, + 0x29014615, + 0x2900d006, + 0x4a11d006, + 0xf7ff4628, + 0xbd70ff67, + 0xe000480f, + 0x2405480f, + 0xd8034283, + 0x1e640840, + 0xdcf92c00, + 0x200140e3, + 0x18180340, + 0x29010b82, + 0x4906d007, + 0x31802300, + 0xf7ff4628, + 0xb2e0ff51, + 0x4902bd70, + 0x316c4b04, + 0x0000e7f6, + 0x00005c83, + 0x2386bca0, + 0x230d8300, + 0x210007c4, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x4a22b510, + 0x61512100, + 0x68894921, + 0xd40900c9, + 0x4b204921, + 0x429805ca, + 0xd8016b4b, + 0xe0004313, + 0x634b4393, + 0xf7ff491d, + 0xbd10ff35, + 0x4d1ab538, + 0x28007f28, + 0x481ad127, + 0x09c08800, + 0xd12207c0, + 0x69604c12, + 0xd11e2800, + 0xf0004668, + 0x4668f88f, + 0x28017800, + 0x4668d117, + 0x28107840, + 0x2008d213, + 0x6a686160, + 0x01400940, + 0x4a0e6020, + 0x62d12100, + 0x21024a0d, + 0x21016011, + 0x60204308, + 0x43082103, + 0x60206268, + 0x4809bd38, + 0xbd384780, + 0x40044000, + 0x21000018, + 0x08930000, + 0x21000280, + 0x000068cf, + 0x21000068, + 0x40041100, + 0xe000e280, + 0x00003bc3, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x4c03b510, + 0xfedcf7ff, + 0x28006820, + 0xbd10d1fa, + 0x40041100, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfef9f7ff, + 0xb510bd10, + 0xfef0f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x8801b510, + 0x0f93050a, + 0xd1034a08, + 0x0d890589, + 0xd0012911, + 0xbd104790, + 0x46044790, + 0xd1032801, + 0xf7ffb672, + 0xb662ffc5, + 0xbd104620, + 0x00002645, + 0x4801b403, + 0xbd019001, + 0x00006fa5, + 0x00000000, + 0x00030001, + 0x001f000a, + 0x00eb0059, + 0x04ea0239, + 0x129709f9, + 0x32a11feb, + 0x660a4a78, + 0x9e8c82fa, + 0xc917b663, + 0xdeedd664, + 0xe5e0e3c1, + 0x000000ff, }; #define _NWORD_PATCHIMAGE_BREPEAT 247 @@ -326,7 +324,6 @@ CPE_PATCH_TYPE patchImageBrepeat[] = #define _IRQ_PATCH_0 0x21000679 - #ifndef _BREPEAT_SYSRAM_START #define _BREPEAT_SYSRAM_START 0x20000000 #endif @@ -345,7 +342,7 @@ CPE_PATCH_TYPE patchImageBrepeat[] = PATCH_FUN_SPEC void enterBrepeatCpePatch(void) { #if (_NWORD_PATCHIMAGE_BREPEAT > 0) - uint32_t* pPatchVec = (uint32_t*) (_BREPEAT_CPERAM_START + _BREPEAT_PATCH_VEC_OFFSET); + uint32_t* pPatchVec = (uint32_t*)(_BREPEAT_CPERAM_START + _BREPEAT_PATCH_VEC_OFFSET); memcpy(pPatchVec, patchImageBrepeat, sizeof(patchImageBrepeat)); #endif @@ -357,10 +354,9 @@ PATCH_FUN_SPEC void enterBrepeatSysPatch(void) PATCH_FUN_SPEC void configureBrepeatPatch(void) { - uint8_t* pParserPatchTab = (uint8_t*) (_BREPEAT_CPERAM_START + _BREPEAT_PARSER_PATCH_TAB_OFFSET); - uint8_t* pPatchTab = (uint8_t*) (_BREPEAT_CPERAM_START + _BREPEAT_PATCH_TAB_OFFSET); - uint32_t* pIrqPatch = (uint32_t*) (_BREPEAT_CPERAM_START + _BREPEAT_IRQPATCH_OFFSET); - + uint8_t* pParserPatchTab = (uint8_t*)(_BREPEAT_CPERAM_START + _BREPEAT_PARSER_PATCH_TAB_OFFSET); + uint8_t* pPatchTab = (uint8_t*)(_BREPEAT_CPERAM_START + _BREPEAT_PATCH_TAB_OFFSET); + uint32_t* pIrqPatch = (uint32_t*)(_BREPEAT_CPERAM_START + _BREPEAT_IRQPATCH_OFFSET); pPatchTab[80] = 0; pPatchTab[57] = 1; @@ -408,4 +404,3 @@ PATCH_FUN_SPEC void rf_patch_cpe_brepeat(void) #endif #endif // _RF_PATCH_CPE_BREPEAT_H - diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_genfsk.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_genfsk.h index cc7f716..dee23d7 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_genfsk.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_genfsk.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_patch_cpe_genfsk.h -* Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ -* Revision: $Revision: 18756 $ -* -* Description: RF Core patch file for CC13x0 generic FSK -* -* Copyright (c) 2015, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_cpe_genfsk.h + * Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ + * Revision: $Revision: 18756 $ + * + * Description: RF Core patch file for CC13x0 generic FSK + * + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_CPE_GENFSK_H #define _RF_PATCH_CPE_GENFSK_H @@ -46,8 +46,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include @@ -69,256 +68,255 @@ extern "C" #define _APPLY_PATCH_TAB #endif - CPE_PATCH_TYPE patchImageGenfsk[] = -{ - 0x21000569, - 0x2100045d, - 0x21000491, - 0x21000495, - 0x210004bd, - 0x2100064d, - 0x210006fd, - 0x21000725, - 0x2100052b, - 0x210004f1, - 0x21000767, - 0x21000789, - 0x4710b5f8, - 0x460eb5f8, - 0x25012100, - 0x473004ad, - 0x7803480a, - 0xf80ff000, - 0xd00b079b, - 0x78204c12, - 0xd00728ff, - 0x702121ff, - 0x240f490e, - 0x43200224, - 0x82c83160, - 0xb5f8bdf8, - 0x47004801, - 0x2100026b, - 0x00004ce5, - 0xe0014809, - 0x0c004808, - 0x49054c06, - 0x2aff7822, - 0x7acad101, - 0x31607022, - 0x467082c8, - 0x47001c80, - 0x40086200, - 0x210007f4, - 0x08080f07, - 0xf886f000, - 0x0a0a9905, - 0xd1092a6c, - 0x61782008, - 0x1c406920, - 0x310a6038, - 0x91056120, - 0x61782000, - 0x0000bdf8, - 0x4708b4f0, - 0x4801b510, - 0x00004700, - 0x00000989, - 0xf818f000, - 0x2950b2e1, - 0x2804d00b, - 0x2806d001, - 0x490dd107, - 0x07c97809, - 0x7821d103, - 0xd4000709, - 0x490a2002, - 0x210c780a, - 0xd0024211, - 0x22804908, - 0xbdfe600a, - 0x4907b5fe, - 0x48044708, - 0x22407801, - 0x70014391, - 0x47004804, - 0x210000c8, - 0x21000117, - 0xe000e200, - 0x0000ccf1, - 0x0000d103, - 0x4605b5ff, - 0x4c03b085, - 0xb5ff4720, - 0x01deb085, - 0x47204c01, - 0x00003ff7, - 0x000041cb, - 0x4603b570, - 0x29014615, - 0x2900d006, - 0x4a11d006, - 0xf7ff4628, - 0xbd70ff67, - 0xe000480f, - 0x2405480f, - 0xd8034283, - 0x1e640840, - 0xdcf92c00, - 0x200140e3, - 0x18180340, - 0x29010b82, - 0x4906d007, - 0x31802300, - 0xf7ff4628, - 0xb2e0ff51, - 0x4902bd70, - 0x316c4b04, - 0x0000e7f6, - 0x00005c83, - 0x2386bca0, - 0x230d8300, - 0x210007c4, - 0x4e1ab5f8, - 0x6b714605, - 0x09cc4819, - 0x2d0001e4, - 0x4918d011, - 0x29027809, - 0x7b00d00f, - 0xb6724304, - 0x4f152001, - 0x47b80240, - 0x38204811, - 0x09c18800, - 0xd00407c9, - 0x7ac0e016, - 0x7b40e7f0, - 0x490fe7ee, - 0x61cc6374, - 0x07c00a40, - 0x2001d00c, - 0x6b310380, - 0xd0012d00, - 0xe0004301, - 0x46084381, - 0x49076331, - 0x63483940, - 0x47b82000, - 0xbdf8b662, - 0x21000280, - 0x21000088, - 0x2100029b, - 0x00003f7b, - 0x40044040, - 0x4a22b510, - 0x61512100, - 0x68894921, - 0xd40900c9, - 0x4b204921, - 0x429805ca, - 0xd8016b4b, - 0xe0004313, - 0x634b4393, - 0xf7ff491d, - 0xbd10ff35, - 0x4d1ab538, - 0x28007f28, - 0x481ad127, - 0x09c08800, - 0xd12207c0, - 0x69604c12, - 0xd11e2800, - 0xf0004668, - 0x4668f88f, - 0x28017800, - 0x4668d117, - 0x28107840, - 0x2008d213, - 0x6a686160, - 0x01400940, - 0x4a0e6020, - 0x62d12100, - 0x21024a0d, - 0x21016011, - 0x60204308, - 0x43082103, - 0x60206268, - 0x4809bd38, - 0xbd384780, - 0x40044000, - 0x21000018, - 0x08930000, - 0x21000280, - 0x000068cf, - 0x21000068, - 0x40041100, - 0xe000e280, - 0x00003bc3, - 0x28004907, - 0x2004d000, - 0xb6724a06, - 0x07c97809, - 0x5810d001, - 0x2080e000, - 0xb240b662, - 0x00004770, - 0x2100026b, - 0x40046058, - 0x4c03b510, - 0xfedcf7ff, - 0x28006820, - 0xbd10d1fa, - 0x40041100, - 0x2041b510, - 0x00c0490e, - 0x490e4788, - 0x6b884602, - 0x24906b49, - 0x04c1014b, - 0x430b0ec9, - 0x4363490a, - 0x43597d49, - 0x689b4b09, - 0xfef9f7ff, - 0xb510bd10, - 0xfef0f7ff, - 0xd1010004, - 0xffe2f7ff, - 0xbd104620, - 0x00003c7d, - 0x40045080, - 0x21000280, - 0x40044000, - 0x8801b510, - 0x0f93050a, - 0xd1034a08, - 0x0d890589, - 0xd0012911, - 0xbd104790, - 0x46044790, - 0xd1032801, - 0xf7ffb672, - 0xb662ffc5, - 0xbd104620, - 0x00002645, - 0x4801b403, - 0xbd019001, - 0x00006fa5, - 0x00000000, - 0x00030001, - 0x001f000a, - 0x00eb0059, - 0x04ea0239, - 0x129709f9, - 0x32a11feb, - 0x660a4a78, - 0x9e8c82fa, - 0xc917b663, - 0xdeedd664, - 0xe5e0e3c1, - 0x000000ff, + { + 0x21000569, + 0x2100045d, + 0x21000491, + 0x21000495, + 0x210004bd, + 0x2100064d, + 0x210006fd, + 0x21000725, + 0x2100052b, + 0x210004f1, + 0x21000767, + 0x21000789, + 0x4710b5f8, + 0x460eb5f8, + 0x25012100, + 0x473004ad, + 0x7803480a, + 0xf80ff000, + 0xd00b079b, + 0x78204c12, + 0xd00728ff, + 0x702121ff, + 0x240f490e, + 0x43200224, + 0x82c83160, + 0xb5f8bdf8, + 0x47004801, + 0x2100026b, + 0x00004ce5, + 0xe0014809, + 0x0c004808, + 0x49054c06, + 0x2aff7822, + 0x7acad101, + 0x31607022, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210007f4, + 0x08080f07, + 0xf886f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4708b4f0, + 0x4801b510, + 0x00004700, + 0x00000989, + 0xf818f000, + 0x2950b2e1, + 0x2804d00b, + 0x2806d001, + 0x490dd107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490a2002, + 0x210c780a, + 0xd0024211, + 0x22804908, + 0xbdfe600a, + 0x4907b5fe, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000117, + 0xe000e200, + 0x0000ccf1, + 0x0000d103, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4603b570, + 0x29014615, + 0x2900d006, + 0x4a11d006, + 0xf7ff4628, + 0xbd70ff67, + 0xe000480f, + 0x2405480f, + 0xd8034283, + 0x1e640840, + 0xdcf92c00, + 0x200140e3, + 0x18180340, + 0x29010b82, + 0x4906d007, + 0x31802300, + 0xf7ff4628, + 0xb2e0ff51, + 0x4902bd70, + 0x316c4b04, + 0x0000e7f6, + 0x00005c83, + 0x2386bca0, + 0x230d8300, + 0x210007c4, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x4a22b510, + 0x61512100, + 0x68894921, + 0xd40900c9, + 0x4b204921, + 0x429805ca, + 0xd8016b4b, + 0xe0004313, + 0x634b4393, + 0xf7ff491d, + 0xbd10ff35, + 0x4d1ab538, + 0x28007f28, + 0x481ad127, + 0x09c08800, + 0xd12207c0, + 0x69604c12, + 0xd11e2800, + 0xf0004668, + 0x4668f88f, + 0x28017800, + 0x4668d117, + 0x28107840, + 0x2008d213, + 0x6a686160, + 0x01400940, + 0x4a0e6020, + 0x62d12100, + 0x21024a0d, + 0x21016011, + 0x60204308, + 0x43082103, + 0x60206268, + 0x4809bd38, + 0xbd384780, + 0x40044000, + 0x21000018, + 0x08930000, + 0x21000280, + 0x000068cf, + 0x21000068, + 0x40041100, + 0xe000e280, + 0x00003bc3, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x4c03b510, + 0xfedcf7ff, + 0x28006820, + 0xbd10d1fa, + 0x40041100, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfef9f7ff, + 0xb510bd10, + 0xfef0f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x8801b510, + 0x0f93050a, + 0xd1034a08, + 0x0d890589, + 0xd0012911, + 0xbd104790, + 0x46044790, + 0xd1032801, + 0xf7ffb672, + 0xb662ffc5, + 0xbd104620, + 0x00002645, + 0x4801b403, + 0xbd019001, + 0x00006fa5, + 0x00000000, + 0x00030001, + 0x001f000a, + 0x00eb0059, + 0x04ea0239, + 0x129709f9, + 0x32a11feb, + 0x660a4a78, + 0x9e8c82fa, + 0xc917b663, + 0xdeedd664, + 0xe5e0e3c1, + 0x000000ff, }; #define _NWORD_PATCHIMAGE_GENFSK 247 @@ -326,7 +324,6 @@ CPE_PATCH_TYPE patchImageGenfsk[] = #define _IRQ_PATCH_0 0x21000679 - #ifndef _GENFSK_SYSRAM_START #define _GENFSK_SYSRAM_START 0x20000000 #endif @@ -345,7 +342,7 @@ CPE_PATCH_TYPE patchImageGenfsk[] = PATCH_FUN_SPEC void enterGenfskCpePatch(void) { #if (_NWORD_PATCHIMAGE_GENFSK > 0) - uint32_t* pPatchVec = (uint32_t*) (_GENFSK_CPERAM_START + _GENFSK_PATCH_VEC_OFFSET); + uint32_t* pPatchVec = (uint32_t*)(_GENFSK_CPERAM_START + _GENFSK_PATCH_VEC_OFFSET); memcpy(pPatchVec, patchImageGenfsk, sizeof(patchImageGenfsk)); #endif @@ -357,10 +354,9 @@ PATCH_FUN_SPEC void enterGenfskSysPatch(void) PATCH_FUN_SPEC void configureGenfskPatch(void) { - uint8_t* pParserPatchTab = (uint8_t*) (_GENFSK_CPERAM_START + _GENFSK_PARSER_PATCH_TAB_OFFSET); - uint8_t* pPatchTab = (uint8_t*) (_GENFSK_CPERAM_START + _GENFSK_PATCH_TAB_OFFSET); - uint32_t* pIrqPatch = (uint32_t*) (_GENFSK_CPERAM_START + _GENFSK_IRQPATCH_OFFSET); - + uint8_t* pParserPatchTab = (uint8_t*)(_GENFSK_CPERAM_START + _GENFSK_PARSER_PATCH_TAB_OFFSET); + uint8_t* pPatchTab = (uint8_t*)(_GENFSK_CPERAM_START + _GENFSK_PATCH_TAB_OFFSET); + uint32_t* pIrqPatch = (uint32_t*)(_GENFSK_CPERAM_START + _GENFSK_IRQPATCH_OFFSET); pPatchTab[80] = 0; pPatchTab[57] = 1; @@ -408,4 +404,3 @@ PATCH_FUN_SPEC void rf_patch_cpe_genfsk(void) #endif #endif // _RF_PATCH_CPE_GENFSK_H - diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_genook.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_genook.h index 4b86f7c..64a16d5 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_genook.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_genook.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_patch_cpe_genook.h -* Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ -* Revision: $Revision: 18756 $ -* -* Description: RF core patch for CC13x0 Generic OOK -* -* Copyright (c) 2015, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_cpe_genook.h + * Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ + * Revision: $Revision: 18756 $ + * + * Description: RF core patch for CC13x0 Generic OOK + * + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_CPE_GENOOK_H #define _RF_PATCH_CPE_GENOOK_H @@ -46,8 +46,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include @@ -69,256 +68,255 @@ extern "C" #define _APPLY_PATCH_TAB #endif - CPE_PATCH_TYPE patchImageGenook[] = -{ - 0x21000569, - 0x2100045d, - 0x21000491, - 0x21000495, - 0x210004bd, - 0x2100064d, - 0x210006fd, - 0x21000725, - 0x2100052b, - 0x210004f1, - 0x21000767, - 0x21000789, - 0x4710b5f8, - 0x460eb5f8, - 0x25012100, - 0x473004ad, - 0x7803480a, - 0xf80ff000, - 0xd00b079b, - 0x78204c12, - 0xd00728ff, - 0x702121ff, - 0x240f490e, - 0x43200224, - 0x82c83160, - 0xb5f8bdf8, - 0x47004801, - 0x2100026b, - 0x00004ce5, - 0xe0014809, - 0x0c004808, - 0x49054c06, - 0x2aff7822, - 0x7acad101, - 0x31607022, - 0x467082c8, - 0x47001c80, - 0x40086200, - 0x210007f4, - 0x08080f07, - 0xf886f000, - 0x0a0a9905, - 0xd1092a6c, - 0x61782008, - 0x1c406920, - 0x310a6038, - 0x91056120, - 0x61782000, - 0x0000bdf8, - 0x4708b4f0, - 0x4801b510, - 0x00004700, - 0x00000989, - 0xf818f000, - 0x2950b2e1, - 0x2804d00b, - 0x2806d001, - 0x490dd107, - 0x07c97809, - 0x7821d103, - 0xd4000709, - 0x490a2002, - 0x210c780a, - 0xd0024211, - 0x22804908, - 0xbdfe600a, - 0x4907b5fe, - 0x48044708, - 0x22407801, - 0x70014391, - 0x47004804, - 0x210000c8, - 0x21000117, - 0xe000e200, - 0x0000ccf1, - 0x0000d103, - 0x4605b5ff, - 0x4c03b085, - 0xb5ff4720, - 0x01deb085, - 0x47204c01, - 0x00003ff7, - 0x000041cb, - 0x4603b570, - 0x29014615, - 0x2900d006, - 0x4a11d006, - 0xf7ff4628, - 0xbd70ff67, - 0xe000480f, - 0x2405480f, - 0xd8034283, - 0x1e640840, - 0xdcf92c00, - 0x200140e3, - 0x18180340, - 0x29010b82, - 0x4906d007, - 0x31802300, - 0xf7ff4628, - 0xb2e0ff51, - 0x4902bd70, - 0x316c4b04, - 0x0000e7f6, - 0x00005c83, - 0x2386bca0, - 0x230d8300, - 0x210007c4, - 0x4e1ab5f8, - 0x6b714605, - 0x09cc4819, - 0x2d0001e4, - 0x4918d011, - 0x29027809, - 0x7b00d00f, - 0xb6724304, - 0x4f152001, - 0x47b80240, - 0x38204811, - 0x09c18800, - 0xd00407c9, - 0x7ac0e016, - 0x7b40e7f0, - 0x490fe7ee, - 0x61cc6374, - 0x07c00a40, - 0x2001d00c, - 0x6b310380, - 0xd0012d00, - 0xe0004301, - 0x46084381, - 0x49076331, - 0x63483940, - 0x47b82000, - 0xbdf8b662, - 0x21000280, - 0x21000088, - 0x2100029b, - 0x00003f7b, - 0x40044040, - 0x4a22b510, - 0x61512100, - 0x68894921, - 0xd40900c9, - 0x4b204921, - 0x429805ca, - 0xd8016b4b, - 0xe0004313, - 0x634b4393, - 0xf7ff491d, - 0xbd10ff35, - 0x4d1ab538, - 0x28007f28, - 0x481ad127, - 0x09c08800, - 0xd12207c0, - 0x69604c12, - 0xd11e2800, - 0xf0004668, - 0x4668f88f, - 0x28017800, - 0x4668d117, - 0x28107840, - 0x2008d213, - 0x6a686160, - 0x01400940, - 0x4a0e6020, - 0x62d12100, - 0x21024a0d, - 0x21016011, - 0x60204308, - 0x43082103, - 0x60206268, - 0x4809bd38, - 0xbd384780, - 0x40044000, - 0x21000018, - 0x08930000, - 0x21000280, - 0x000068cf, - 0x21000068, - 0x40041100, - 0xe000e280, - 0x00003bc3, - 0x28004907, - 0x2004d000, - 0xb6724a06, - 0x07c97809, - 0x5810d001, - 0x2080e000, - 0xb240b662, - 0x00004770, - 0x2100026b, - 0x40046058, - 0x4c03b510, - 0xfedcf7ff, - 0x28006820, - 0xbd10d1fa, - 0x40041100, - 0x2041b510, - 0x00c0490e, - 0x490e4788, - 0x6b884602, - 0x24906b49, - 0x04c1014b, - 0x430b0ec9, - 0x4363490a, - 0x43597d49, - 0x689b4b09, - 0xfef9f7ff, - 0xb510bd10, - 0xfef0f7ff, - 0xd1010004, - 0xffe2f7ff, - 0xbd104620, - 0x00003c7d, - 0x40045080, - 0x21000280, - 0x40044000, - 0x8801b510, - 0x0f93050a, - 0xd1034a08, - 0x0d890589, - 0xd0012911, - 0xbd104790, - 0x46044790, - 0xd1032801, - 0xf7ffb672, - 0xb662ffc5, - 0xbd104620, - 0x00002645, - 0x4801b403, - 0xbd019001, - 0x00006fa5, - 0x00000000, - 0x00030001, - 0x001f000a, - 0x00eb0059, - 0x04ea0239, - 0x129709f9, - 0x32a11feb, - 0x660a4a78, - 0x9e8c82fa, - 0xc917b663, - 0xdeedd664, - 0xe5e0e3c1, - 0x000000ff, + { + 0x21000569, + 0x2100045d, + 0x21000491, + 0x21000495, + 0x210004bd, + 0x2100064d, + 0x210006fd, + 0x21000725, + 0x2100052b, + 0x210004f1, + 0x21000767, + 0x21000789, + 0x4710b5f8, + 0x460eb5f8, + 0x25012100, + 0x473004ad, + 0x7803480a, + 0xf80ff000, + 0xd00b079b, + 0x78204c12, + 0xd00728ff, + 0x702121ff, + 0x240f490e, + 0x43200224, + 0x82c83160, + 0xb5f8bdf8, + 0x47004801, + 0x2100026b, + 0x00004ce5, + 0xe0014809, + 0x0c004808, + 0x49054c06, + 0x2aff7822, + 0x7acad101, + 0x31607022, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210007f4, + 0x08080f07, + 0xf886f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4708b4f0, + 0x4801b510, + 0x00004700, + 0x00000989, + 0xf818f000, + 0x2950b2e1, + 0x2804d00b, + 0x2806d001, + 0x490dd107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490a2002, + 0x210c780a, + 0xd0024211, + 0x22804908, + 0xbdfe600a, + 0x4907b5fe, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000117, + 0xe000e200, + 0x0000ccf1, + 0x0000d103, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4603b570, + 0x29014615, + 0x2900d006, + 0x4a11d006, + 0xf7ff4628, + 0xbd70ff67, + 0xe000480f, + 0x2405480f, + 0xd8034283, + 0x1e640840, + 0xdcf92c00, + 0x200140e3, + 0x18180340, + 0x29010b82, + 0x4906d007, + 0x31802300, + 0xf7ff4628, + 0xb2e0ff51, + 0x4902bd70, + 0x316c4b04, + 0x0000e7f6, + 0x00005c83, + 0x2386bca0, + 0x230d8300, + 0x210007c4, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x4a22b510, + 0x61512100, + 0x68894921, + 0xd40900c9, + 0x4b204921, + 0x429805ca, + 0xd8016b4b, + 0xe0004313, + 0x634b4393, + 0xf7ff491d, + 0xbd10ff35, + 0x4d1ab538, + 0x28007f28, + 0x481ad127, + 0x09c08800, + 0xd12207c0, + 0x69604c12, + 0xd11e2800, + 0xf0004668, + 0x4668f88f, + 0x28017800, + 0x4668d117, + 0x28107840, + 0x2008d213, + 0x6a686160, + 0x01400940, + 0x4a0e6020, + 0x62d12100, + 0x21024a0d, + 0x21016011, + 0x60204308, + 0x43082103, + 0x60206268, + 0x4809bd38, + 0xbd384780, + 0x40044000, + 0x21000018, + 0x08930000, + 0x21000280, + 0x000068cf, + 0x21000068, + 0x40041100, + 0xe000e280, + 0x00003bc3, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x4c03b510, + 0xfedcf7ff, + 0x28006820, + 0xbd10d1fa, + 0x40041100, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfef9f7ff, + 0xb510bd10, + 0xfef0f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x8801b510, + 0x0f93050a, + 0xd1034a08, + 0x0d890589, + 0xd0012911, + 0xbd104790, + 0x46044790, + 0xd1032801, + 0xf7ffb672, + 0xb662ffc5, + 0xbd104620, + 0x00002645, + 0x4801b403, + 0xbd019001, + 0x00006fa5, + 0x00000000, + 0x00030001, + 0x001f000a, + 0x00eb0059, + 0x04ea0239, + 0x129709f9, + 0x32a11feb, + 0x660a4a78, + 0x9e8c82fa, + 0xc917b663, + 0xdeedd664, + 0xe5e0e3c1, + 0x000000ff, }; #define _NWORD_PATCHIMAGE_GENOOK 247 @@ -326,7 +324,6 @@ CPE_PATCH_TYPE patchImageGenook[] = #define _IRQ_PATCH_0 0x21000679 - #ifndef _GENOOK_SYSRAM_START #define _GENOOK_SYSRAM_START 0x20000000 #endif @@ -345,7 +342,7 @@ CPE_PATCH_TYPE patchImageGenook[] = PATCH_FUN_SPEC void enterGenookCpePatch(void) { #if (_NWORD_PATCHIMAGE_GENOOK > 0) - uint32_t* pPatchVec = (uint32_t*) (_GENOOK_CPERAM_START + _GENOOK_PATCH_VEC_OFFSET); + uint32_t* pPatchVec = (uint32_t*)(_GENOOK_CPERAM_START + _GENOOK_PATCH_VEC_OFFSET); memcpy(pPatchVec, patchImageGenook, sizeof(patchImageGenook)); #endif @@ -357,10 +354,9 @@ PATCH_FUN_SPEC void enterGenookSysPatch(void) PATCH_FUN_SPEC void configureGenookPatch(void) { - uint8_t* pParserPatchTab = (uint8_t*) (_GENOOK_CPERAM_START + _GENOOK_PARSER_PATCH_TAB_OFFSET); - uint8_t* pPatchTab = (uint8_t*) (_GENOOK_CPERAM_START + _GENOOK_PATCH_TAB_OFFSET); - uint32_t* pIrqPatch = (uint32_t*) (_GENOOK_CPERAM_START + _GENOOK_IRQPATCH_OFFSET); - + uint8_t* pParserPatchTab = (uint8_t*)(_GENOOK_CPERAM_START + _GENOOK_PARSER_PATCH_TAB_OFFSET); + uint8_t* pPatchTab = (uint8_t*)(_GENOOK_CPERAM_START + _GENOOK_PATCH_TAB_OFFSET); + uint32_t* pIrqPatch = (uint32_t*)(_GENOOK_CPERAM_START + _GENOOK_IRQPATCH_OFFSET); pPatchTab[80] = 0; pPatchTab[57] = 1; @@ -408,4 +404,3 @@ PATCH_FUN_SPEC void rf_patch_cpe_genook(void) #endif #endif // _RF_PATCH_CPE_GENOOK_H - diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ghs.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ghs.h index 7afd497..a42a84a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ghs.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_ghs.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_patch_cpe_ghs.h -* Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ -* Revision: $Revision: 18756 $ -* -* Description: RF core patch for CC13x0 Generic 4FSK up to 1.5Mbps -* -* Copyright (c) 2015, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_cpe_ghs.h + * Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ + * Revision: $Revision: 18756 $ + * + * Description: RF core patch for CC13x0 Generic 4FSK up to 1.5Mbps + * + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_CPE_GHS_H #define _RF_PATCH_CPE_GHS_H @@ -46,8 +46,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include @@ -69,256 +68,255 @@ extern "C" #define _APPLY_PATCH_TAB #endif - CPE_PATCH_TYPE patchImageGhs[] = -{ - 0x21000569, - 0x2100045d, - 0x21000491, - 0x21000495, - 0x210004bd, - 0x2100064d, - 0x210006fd, - 0x21000725, - 0x2100052b, - 0x210004f1, - 0x21000767, - 0x21000789, - 0x4710b5f8, - 0x460eb5f8, - 0x25012100, - 0x473004ad, - 0x7803480a, - 0xf80ff000, - 0xd00b079b, - 0x78204c12, - 0xd00728ff, - 0x702121ff, - 0x240f490e, - 0x43200224, - 0x82c83160, - 0xb5f8bdf8, - 0x47004801, - 0x2100026b, - 0x00004ce5, - 0xe0014809, - 0x0c004808, - 0x49054c06, - 0x2aff7822, - 0x7acad101, - 0x31607022, - 0x467082c8, - 0x47001c80, - 0x40086200, - 0x210007f4, - 0x08080f07, - 0xf886f000, - 0x0a0a9905, - 0xd1092a6c, - 0x61782008, - 0x1c406920, - 0x310a6038, - 0x91056120, - 0x61782000, - 0x0000bdf8, - 0x4708b4f0, - 0x4801b510, - 0x00004700, - 0x00000989, - 0xf818f000, - 0x2950b2e1, - 0x2804d00b, - 0x2806d001, - 0x490dd107, - 0x07c97809, - 0x7821d103, - 0xd4000709, - 0x490a2002, - 0x210c780a, - 0xd0024211, - 0x22804908, - 0xbdfe600a, - 0x4907b5fe, - 0x48044708, - 0x22407801, - 0x70014391, - 0x47004804, - 0x210000c8, - 0x21000117, - 0xe000e200, - 0x0000ccf1, - 0x0000d103, - 0x4605b5ff, - 0x4c03b085, - 0xb5ff4720, - 0x01deb085, - 0x47204c01, - 0x00003ff7, - 0x000041cb, - 0x4603b570, - 0x29014615, - 0x2900d006, - 0x4a11d006, - 0xf7ff4628, - 0xbd70ff67, - 0xe000480f, - 0x2405480f, - 0xd8034283, - 0x1e640840, - 0xdcf92c00, - 0x200140e3, - 0x18180340, - 0x29010b82, - 0x4906d007, - 0x31802300, - 0xf7ff4628, - 0xb2e0ff51, - 0x4902bd70, - 0x316c4b04, - 0x0000e7f6, - 0x00005c83, - 0x2386bca0, - 0x230d8300, - 0x210007c4, - 0x4e1ab5f8, - 0x6b714605, - 0x09cc4819, - 0x2d0001e4, - 0x4918d011, - 0x29027809, - 0x7b00d00f, - 0xb6724304, - 0x4f152001, - 0x47b80240, - 0x38204811, - 0x09c18800, - 0xd00407c9, - 0x7ac0e016, - 0x7b40e7f0, - 0x490fe7ee, - 0x61cc6374, - 0x07c00a40, - 0x2001d00c, - 0x6b310380, - 0xd0012d00, - 0xe0004301, - 0x46084381, - 0x49076331, - 0x63483940, - 0x47b82000, - 0xbdf8b662, - 0x21000280, - 0x21000088, - 0x2100029b, - 0x00003f7b, - 0x40044040, - 0x4a22b510, - 0x61512100, - 0x68894921, - 0xd40900c9, - 0x4b204921, - 0x429805ca, - 0xd8016b4b, - 0xe0004313, - 0x634b4393, - 0xf7ff491d, - 0xbd10ff35, - 0x4d1ab538, - 0x28007f28, - 0x481ad127, - 0x09c08800, - 0xd12207c0, - 0x69604c12, - 0xd11e2800, - 0xf0004668, - 0x4668f88f, - 0x28017800, - 0x4668d117, - 0x28107840, - 0x2008d213, - 0x6a686160, - 0x01400940, - 0x4a0e6020, - 0x62d12100, - 0x21024a0d, - 0x21016011, - 0x60204308, - 0x43082103, - 0x60206268, - 0x4809bd38, - 0xbd384780, - 0x40044000, - 0x21000018, - 0x08930000, - 0x21000280, - 0x000068cf, - 0x21000068, - 0x40041100, - 0xe000e280, - 0x00003bc3, - 0x28004907, - 0x2004d000, - 0xb6724a06, - 0x07c97809, - 0x5810d001, - 0x2080e000, - 0xb240b662, - 0x00004770, - 0x2100026b, - 0x40046058, - 0x4c03b510, - 0xfedcf7ff, - 0x28006820, - 0xbd10d1fa, - 0x40041100, - 0x2041b510, - 0x00c0490e, - 0x490e4788, - 0x6b884602, - 0x24906b49, - 0x04c1014b, - 0x430b0ec9, - 0x4363490a, - 0x43597d49, - 0x689b4b09, - 0xfef9f7ff, - 0xb510bd10, - 0xfef0f7ff, - 0xd1010004, - 0xffe2f7ff, - 0xbd104620, - 0x00003c7d, - 0x40045080, - 0x21000280, - 0x40044000, - 0x8801b510, - 0x0f93050a, - 0xd1034a08, - 0x0d890589, - 0xd0012911, - 0xbd104790, - 0x46044790, - 0xd1032801, - 0xf7ffb672, - 0xb662ffc5, - 0xbd104620, - 0x00002645, - 0x4801b403, - 0xbd019001, - 0x00006fa5, - 0x00000000, - 0x00030001, - 0x001f000a, - 0x00eb0059, - 0x04ea0239, - 0x129709f9, - 0x32a11feb, - 0x660a4a78, - 0x9e8c82fa, - 0xc917b663, - 0xdeedd664, - 0xe5e0e3c1, - 0x000000ff, + { + 0x21000569, + 0x2100045d, + 0x21000491, + 0x21000495, + 0x210004bd, + 0x2100064d, + 0x210006fd, + 0x21000725, + 0x2100052b, + 0x210004f1, + 0x21000767, + 0x21000789, + 0x4710b5f8, + 0x460eb5f8, + 0x25012100, + 0x473004ad, + 0x7803480a, + 0xf80ff000, + 0xd00b079b, + 0x78204c12, + 0xd00728ff, + 0x702121ff, + 0x240f490e, + 0x43200224, + 0x82c83160, + 0xb5f8bdf8, + 0x47004801, + 0x2100026b, + 0x00004ce5, + 0xe0014809, + 0x0c004808, + 0x49054c06, + 0x2aff7822, + 0x7acad101, + 0x31607022, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210007f4, + 0x08080f07, + 0xf886f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4708b4f0, + 0x4801b510, + 0x00004700, + 0x00000989, + 0xf818f000, + 0x2950b2e1, + 0x2804d00b, + 0x2806d001, + 0x490dd107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490a2002, + 0x210c780a, + 0xd0024211, + 0x22804908, + 0xbdfe600a, + 0x4907b5fe, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000117, + 0xe000e200, + 0x0000ccf1, + 0x0000d103, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4603b570, + 0x29014615, + 0x2900d006, + 0x4a11d006, + 0xf7ff4628, + 0xbd70ff67, + 0xe000480f, + 0x2405480f, + 0xd8034283, + 0x1e640840, + 0xdcf92c00, + 0x200140e3, + 0x18180340, + 0x29010b82, + 0x4906d007, + 0x31802300, + 0xf7ff4628, + 0xb2e0ff51, + 0x4902bd70, + 0x316c4b04, + 0x0000e7f6, + 0x00005c83, + 0x2386bca0, + 0x230d8300, + 0x210007c4, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x4a22b510, + 0x61512100, + 0x68894921, + 0xd40900c9, + 0x4b204921, + 0x429805ca, + 0xd8016b4b, + 0xe0004313, + 0x634b4393, + 0xf7ff491d, + 0xbd10ff35, + 0x4d1ab538, + 0x28007f28, + 0x481ad127, + 0x09c08800, + 0xd12207c0, + 0x69604c12, + 0xd11e2800, + 0xf0004668, + 0x4668f88f, + 0x28017800, + 0x4668d117, + 0x28107840, + 0x2008d213, + 0x6a686160, + 0x01400940, + 0x4a0e6020, + 0x62d12100, + 0x21024a0d, + 0x21016011, + 0x60204308, + 0x43082103, + 0x60206268, + 0x4809bd38, + 0xbd384780, + 0x40044000, + 0x21000018, + 0x08930000, + 0x21000280, + 0x000068cf, + 0x21000068, + 0x40041100, + 0xe000e280, + 0x00003bc3, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x4c03b510, + 0xfedcf7ff, + 0x28006820, + 0xbd10d1fa, + 0x40041100, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfef9f7ff, + 0xb510bd10, + 0xfef0f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x8801b510, + 0x0f93050a, + 0xd1034a08, + 0x0d890589, + 0xd0012911, + 0xbd104790, + 0x46044790, + 0xd1032801, + 0xf7ffb672, + 0xb662ffc5, + 0xbd104620, + 0x00002645, + 0x4801b403, + 0xbd019001, + 0x00006fa5, + 0x00000000, + 0x00030001, + 0x001f000a, + 0x00eb0059, + 0x04ea0239, + 0x129709f9, + 0x32a11feb, + 0x660a4a78, + 0x9e8c82fa, + 0xc917b663, + 0xdeedd664, + 0xe5e0e3c1, + 0x000000ff, }; #define _NWORD_PATCHIMAGE_GHS 247 @@ -326,7 +324,6 @@ CPE_PATCH_TYPE patchImageGhs[] = #define _IRQ_PATCH_0 0x21000679 - #ifndef _GHS_SYSRAM_START #define _GHS_SYSRAM_START 0x20000000 #endif @@ -345,7 +342,7 @@ CPE_PATCH_TYPE patchImageGhs[] = PATCH_FUN_SPEC void enterGhsCpePatch(void) { #if (_NWORD_PATCHIMAGE_GHS > 0) - uint32_t* pPatchVec = (uint32_t*) (_GHS_CPERAM_START + _GHS_PATCH_VEC_OFFSET); + uint32_t* pPatchVec = (uint32_t*)(_GHS_CPERAM_START + _GHS_PATCH_VEC_OFFSET); memcpy(pPatchVec, patchImageGhs, sizeof(patchImageGhs)); #endif @@ -357,10 +354,9 @@ PATCH_FUN_SPEC void enterGhsSysPatch(void) PATCH_FUN_SPEC void configureGhsPatch(void) { - uint8_t* pParserPatchTab = (uint8_t*) (_GHS_CPERAM_START + _GHS_PARSER_PATCH_TAB_OFFSET); - uint8_t* pPatchTab = (uint8_t*) (_GHS_CPERAM_START + _GHS_PATCH_TAB_OFFSET); - uint32_t* pIrqPatch = (uint32_t*) (_GHS_CPERAM_START + _GHS_IRQPATCH_OFFSET); - + uint8_t* pParserPatchTab = (uint8_t*)(_GHS_CPERAM_START + _GHS_PARSER_PATCH_TAB_OFFSET); + uint8_t* pPatchTab = (uint8_t*)(_GHS_CPERAM_START + _GHS_PATCH_TAB_OFFSET); + uint32_t* pIrqPatch = (uint32_t*)(_GHS_CPERAM_START + _GHS_IRQPATCH_OFFSET); pPatchTab[80] = 0; pPatchTab[57] = 1; @@ -408,4 +404,3 @@ PATCH_FUN_SPEC void rf_patch_cpe_ghs(void) #endif #endif // _RF_PATCH_CPE_GHS_H - diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_lrm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_lrm.h index 480e235..785c4f9 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_lrm.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_lrm.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_patch_cpe_lrm.h -* Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ -* Revision: $Revision: 18756 $ -* -* Description: RF core patch for CC13x0 Legacy Long Range Mode -* -* Copyright (c) 2015, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_cpe_lrm.h + * Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ + * Revision: $Revision: 18756 $ + * + * Description: RF core patch for CC13x0 Legacy Long Range Mode + * + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_CPE_LRM_H #define _RF_PATCH_CPE_LRM_H @@ -46,8 +46,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include @@ -69,256 +68,255 @@ extern "C" #define _APPLY_PATCH_TAB #endif - CPE_PATCH_TYPE patchImageLrm[] = -{ - 0x21000569, - 0x2100045d, - 0x21000491, - 0x21000495, - 0x210004bd, - 0x2100064d, - 0x210006fd, - 0x21000725, - 0x2100052b, - 0x210004f1, - 0x21000767, - 0x21000789, - 0x4710b5f8, - 0x460eb5f8, - 0x25012100, - 0x473004ad, - 0x7803480a, - 0xf80ff000, - 0xd00b079b, - 0x78204c12, - 0xd00728ff, - 0x702121ff, - 0x240f490e, - 0x43200224, - 0x82c83160, - 0xb5f8bdf8, - 0x47004801, - 0x2100026b, - 0x00004ce5, - 0xe0014809, - 0x0c004808, - 0x49054c06, - 0x2aff7822, - 0x7acad101, - 0x31607022, - 0x467082c8, - 0x47001c80, - 0x40086200, - 0x210007f4, - 0x08080f07, - 0xf886f000, - 0x0a0a9905, - 0xd1092a6c, - 0x61782008, - 0x1c406920, - 0x310a6038, - 0x91056120, - 0x61782000, - 0x0000bdf8, - 0x4708b4f0, - 0x4801b510, - 0x00004700, - 0x00000989, - 0xf818f000, - 0x2950b2e1, - 0x2804d00b, - 0x2806d001, - 0x490dd107, - 0x07c97809, - 0x7821d103, - 0xd4000709, - 0x490a2002, - 0x210c780a, - 0xd0024211, - 0x22804908, - 0xbdfe600a, - 0x4907b5fe, - 0x48044708, - 0x22407801, - 0x70014391, - 0x47004804, - 0x210000c8, - 0x21000117, - 0xe000e200, - 0x0000ccf1, - 0x0000d103, - 0x4605b5ff, - 0x4c03b085, - 0xb5ff4720, - 0x01deb085, - 0x47204c01, - 0x00003ff7, - 0x000041cb, - 0x4603b570, - 0x29014615, - 0x2900d006, - 0x4a11d006, - 0xf7ff4628, - 0xbd70ff67, - 0xe000480f, - 0x2405480f, - 0xd8034283, - 0x1e640840, - 0xdcf92c00, - 0x200140e3, - 0x18180340, - 0x29010b82, - 0x4906d007, - 0x31802300, - 0xf7ff4628, - 0xb2e0ff51, - 0x4902bd70, - 0x316c4b04, - 0x0000e7f6, - 0x00005c83, - 0x2386bca0, - 0x230d8300, - 0x210007c4, - 0x4e1ab5f8, - 0x6b714605, - 0x09cc4819, - 0x2d0001e4, - 0x4918d011, - 0x29027809, - 0x7b00d00f, - 0xb6724304, - 0x4f152001, - 0x47b80240, - 0x38204811, - 0x09c18800, - 0xd00407c9, - 0x7ac0e016, - 0x7b40e7f0, - 0x490fe7ee, - 0x61cc6374, - 0x07c00a40, - 0x2001d00c, - 0x6b310380, - 0xd0012d00, - 0xe0004301, - 0x46084381, - 0x49076331, - 0x63483940, - 0x47b82000, - 0xbdf8b662, - 0x21000280, - 0x21000088, - 0x2100029b, - 0x00003f7b, - 0x40044040, - 0x4a22b510, - 0x61512100, - 0x68894921, - 0xd40900c9, - 0x4b204921, - 0x429805ca, - 0xd8016b4b, - 0xe0004313, - 0x634b4393, - 0xf7ff491d, - 0xbd10ff35, - 0x4d1ab538, - 0x28007f28, - 0x481ad127, - 0x09c08800, - 0xd12207c0, - 0x69604c12, - 0xd11e2800, - 0xf0004668, - 0x4668f88f, - 0x28017800, - 0x4668d117, - 0x28107840, - 0x2008d213, - 0x6a686160, - 0x01400940, - 0x4a0e6020, - 0x62d12100, - 0x21024a0d, - 0x21016011, - 0x60204308, - 0x43082103, - 0x60206268, - 0x4809bd38, - 0xbd384780, - 0x40044000, - 0x21000018, - 0x08930000, - 0x21000280, - 0x000068cf, - 0x21000068, - 0x40041100, - 0xe000e280, - 0x00003bc3, - 0x28004907, - 0x2004d000, - 0xb6724a06, - 0x07c97809, - 0x5810d001, - 0x2080e000, - 0xb240b662, - 0x00004770, - 0x2100026b, - 0x40046058, - 0x4c03b510, - 0xfedcf7ff, - 0x28006820, - 0xbd10d1fa, - 0x40041100, - 0x2041b510, - 0x00c0490e, - 0x490e4788, - 0x6b884602, - 0x24906b49, - 0x04c1014b, - 0x430b0ec9, - 0x4363490a, - 0x43597d49, - 0x689b4b09, - 0xfef9f7ff, - 0xb510bd10, - 0xfef0f7ff, - 0xd1010004, - 0xffe2f7ff, - 0xbd104620, - 0x00003c7d, - 0x40045080, - 0x21000280, - 0x40044000, - 0x8801b510, - 0x0f93050a, - 0xd1034a08, - 0x0d890589, - 0xd0012911, - 0xbd104790, - 0x46044790, - 0xd1032801, - 0xf7ffb672, - 0xb662ffc5, - 0xbd104620, - 0x00002645, - 0x4801b403, - 0xbd019001, - 0x00006fa5, - 0x00000000, - 0x00030001, - 0x001f000a, - 0x00eb0059, - 0x04ea0239, - 0x129709f9, - 0x32a11feb, - 0x660a4a78, - 0x9e8c82fa, - 0xc917b663, - 0xdeedd664, - 0xe5e0e3c1, - 0x000000ff, + { + 0x21000569, + 0x2100045d, + 0x21000491, + 0x21000495, + 0x210004bd, + 0x2100064d, + 0x210006fd, + 0x21000725, + 0x2100052b, + 0x210004f1, + 0x21000767, + 0x21000789, + 0x4710b5f8, + 0x460eb5f8, + 0x25012100, + 0x473004ad, + 0x7803480a, + 0xf80ff000, + 0xd00b079b, + 0x78204c12, + 0xd00728ff, + 0x702121ff, + 0x240f490e, + 0x43200224, + 0x82c83160, + 0xb5f8bdf8, + 0x47004801, + 0x2100026b, + 0x00004ce5, + 0xe0014809, + 0x0c004808, + 0x49054c06, + 0x2aff7822, + 0x7acad101, + 0x31607022, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210007f4, + 0x08080f07, + 0xf886f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4708b4f0, + 0x4801b510, + 0x00004700, + 0x00000989, + 0xf818f000, + 0x2950b2e1, + 0x2804d00b, + 0x2806d001, + 0x490dd107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490a2002, + 0x210c780a, + 0xd0024211, + 0x22804908, + 0xbdfe600a, + 0x4907b5fe, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000117, + 0xe000e200, + 0x0000ccf1, + 0x0000d103, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4603b570, + 0x29014615, + 0x2900d006, + 0x4a11d006, + 0xf7ff4628, + 0xbd70ff67, + 0xe000480f, + 0x2405480f, + 0xd8034283, + 0x1e640840, + 0xdcf92c00, + 0x200140e3, + 0x18180340, + 0x29010b82, + 0x4906d007, + 0x31802300, + 0xf7ff4628, + 0xb2e0ff51, + 0x4902bd70, + 0x316c4b04, + 0x0000e7f6, + 0x00005c83, + 0x2386bca0, + 0x230d8300, + 0x210007c4, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x4a22b510, + 0x61512100, + 0x68894921, + 0xd40900c9, + 0x4b204921, + 0x429805ca, + 0xd8016b4b, + 0xe0004313, + 0x634b4393, + 0xf7ff491d, + 0xbd10ff35, + 0x4d1ab538, + 0x28007f28, + 0x481ad127, + 0x09c08800, + 0xd12207c0, + 0x69604c12, + 0xd11e2800, + 0xf0004668, + 0x4668f88f, + 0x28017800, + 0x4668d117, + 0x28107840, + 0x2008d213, + 0x6a686160, + 0x01400940, + 0x4a0e6020, + 0x62d12100, + 0x21024a0d, + 0x21016011, + 0x60204308, + 0x43082103, + 0x60206268, + 0x4809bd38, + 0xbd384780, + 0x40044000, + 0x21000018, + 0x08930000, + 0x21000280, + 0x000068cf, + 0x21000068, + 0x40041100, + 0xe000e280, + 0x00003bc3, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x4c03b510, + 0xfedcf7ff, + 0x28006820, + 0xbd10d1fa, + 0x40041100, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfef9f7ff, + 0xb510bd10, + 0xfef0f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x8801b510, + 0x0f93050a, + 0xd1034a08, + 0x0d890589, + 0xd0012911, + 0xbd104790, + 0x46044790, + 0xd1032801, + 0xf7ffb672, + 0xb662ffc5, + 0xbd104620, + 0x00002645, + 0x4801b403, + 0xbd019001, + 0x00006fa5, + 0x00000000, + 0x00030001, + 0x001f000a, + 0x00eb0059, + 0x04ea0239, + 0x129709f9, + 0x32a11feb, + 0x660a4a78, + 0x9e8c82fa, + 0xc917b663, + 0xdeedd664, + 0xe5e0e3c1, + 0x000000ff, }; #define _NWORD_PATCHIMAGE_LRM 247 @@ -326,7 +324,6 @@ CPE_PATCH_TYPE patchImageLrm[] = #define _IRQ_PATCH_0 0x21000679 - #ifndef _LRM_SYSRAM_START #define _LRM_SYSRAM_START 0x20000000 #endif @@ -345,7 +342,7 @@ CPE_PATCH_TYPE patchImageLrm[] = PATCH_FUN_SPEC void enterLrmCpePatch(void) { #if (_NWORD_PATCHIMAGE_LRM > 0) - uint32_t* pPatchVec = (uint32_t*) (_LRM_CPERAM_START + _LRM_PATCH_VEC_OFFSET); + uint32_t* pPatchVec = (uint32_t*)(_LRM_CPERAM_START + _LRM_PATCH_VEC_OFFSET); memcpy(pPatchVec, patchImageLrm, sizeof(patchImageLrm)); #endif @@ -357,10 +354,9 @@ PATCH_FUN_SPEC void enterLrmSysPatch(void) PATCH_FUN_SPEC void configureLrmPatch(void) { - uint8_t* pParserPatchTab = (uint8_t*) (_LRM_CPERAM_START + _LRM_PARSER_PATCH_TAB_OFFSET); - uint8_t* pPatchTab = (uint8_t*) (_LRM_CPERAM_START + _LRM_PATCH_TAB_OFFSET); - uint32_t* pIrqPatch = (uint32_t*) (_LRM_CPERAM_START + _LRM_IRQPATCH_OFFSET); - + uint8_t* pParserPatchTab = (uint8_t*)(_LRM_CPERAM_START + _LRM_PARSER_PATCH_TAB_OFFSET); + uint8_t* pPatchTab = (uint8_t*)(_LRM_CPERAM_START + _LRM_PATCH_TAB_OFFSET); + uint32_t* pIrqPatch = (uint32_t*)(_LRM_CPERAM_START + _LRM_IRQPATCH_OFFSET); pPatchTab[80] = 0; pPatchTab[57] = 1; @@ -408,4 +404,3 @@ PATCH_FUN_SPEC void rf_patch_cpe_lrm(void) #endif #endif // _RF_PATCH_CPE_LRM_H - diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_sl_longrange.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_sl_longrange.h index 6c3d350..a0fe30e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_sl_longrange.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_sl_longrange.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_patch_cpe_sl_longrange.h -* Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ -* Revision: $Revision: 18756 $ -* -* Description: RF core patch for CC13x0 SimpleLink Long Range -* -* Copyright (c) 2015, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_cpe_sl_longrange.h + * Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ + * Revision: $Revision: 18756 $ + * + * Description: RF core patch for CC13x0 SimpleLink Long Range + * + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_CPE_SL_LONGRANGE_H #define _RF_PATCH_CPE_SL_LONGRANGE_H @@ -46,8 +46,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include @@ -69,256 +68,255 @@ extern "C" #define _APPLY_PATCH_TAB #endif - CPE_PATCH_TYPE patchImageSlLongrange[] = -{ - 0x21000569, - 0x2100045d, - 0x21000491, - 0x21000495, - 0x210004bd, - 0x2100064d, - 0x210006fd, - 0x21000725, - 0x2100052b, - 0x210004f1, - 0x21000767, - 0x21000789, - 0x4710b5f8, - 0x460eb5f8, - 0x25012100, - 0x473004ad, - 0x7803480a, - 0xf80ff000, - 0xd00b079b, - 0x78204c12, - 0xd00728ff, - 0x702121ff, - 0x240f490e, - 0x43200224, - 0x82c83160, - 0xb5f8bdf8, - 0x47004801, - 0x2100026b, - 0x00004ce5, - 0xe0014809, - 0x0c004808, - 0x49054c06, - 0x2aff7822, - 0x7acad101, - 0x31607022, - 0x467082c8, - 0x47001c80, - 0x40086200, - 0x210007f4, - 0x08080f07, - 0xf886f000, - 0x0a0a9905, - 0xd1092a6c, - 0x61782008, - 0x1c406920, - 0x310a6038, - 0x91056120, - 0x61782000, - 0x0000bdf8, - 0x4708b4f0, - 0x4801b510, - 0x00004700, - 0x00000989, - 0xf818f000, - 0x2950b2e1, - 0x2804d00b, - 0x2806d001, - 0x490dd107, - 0x07c97809, - 0x7821d103, - 0xd4000709, - 0x490a2002, - 0x210c780a, - 0xd0024211, - 0x22804908, - 0xbdfe600a, - 0x4907b5fe, - 0x48044708, - 0x22407801, - 0x70014391, - 0x47004804, - 0x210000c8, - 0x21000117, - 0xe000e200, - 0x0000ccf1, - 0x0000d103, - 0x4605b5ff, - 0x4c03b085, - 0xb5ff4720, - 0x01deb085, - 0x47204c01, - 0x00003ff7, - 0x000041cb, - 0x4603b570, - 0x29014615, - 0x2900d006, - 0x4a11d006, - 0xf7ff4628, - 0xbd70ff67, - 0xe000480f, - 0x2405480f, - 0xd8034283, - 0x1e640840, - 0xdcf92c00, - 0x200140e3, - 0x18180340, - 0x29010b82, - 0x4906d007, - 0x31802300, - 0xf7ff4628, - 0xb2e0ff51, - 0x4902bd70, - 0x316c4b04, - 0x0000e7f6, - 0x00005c83, - 0x2386bca0, - 0x230d8300, - 0x210007c4, - 0x4e1ab5f8, - 0x6b714605, - 0x09cc4819, - 0x2d0001e4, - 0x4918d011, - 0x29027809, - 0x7b00d00f, - 0xb6724304, - 0x4f152001, - 0x47b80240, - 0x38204811, - 0x09c18800, - 0xd00407c9, - 0x7ac0e016, - 0x7b40e7f0, - 0x490fe7ee, - 0x61cc6374, - 0x07c00a40, - 0x2001d00c, - 0x6b310380, - 0xd0012d00, - 0xe0004301, - 0x46084381, - 0x49076331, - 0x63483940, - 0x47b82000, - 0xbdf8b662, - 0x21000280, - 0x21000088, - 0x2100029b, - 0x00003f7b, - 0x40044040, - 0x4a22b510, - 0x61512100, - 0x68894921, - 0xd40900c9, - 0x4b204921, - 0x429805ca, - 0xd8016b4b, - 0xe0004313, - 0x634b4393, - 0xf7ff491d, - 0xbd10ff35, - 0x4d1ab538, - 0x28007f28, - 0x481ad127, - 0x09c08800, - 0xd12207c0, - 0x69604c12, - 0xd11e2800, - 0xf0004668, - 0x4668f88f, - 0x28017800, - 0x4668d117, - 0x28107840, - 0x2008d213, - 0x6a686160, - 0x01400940, - 0x4a0e6020, - 0x62d12100, - 0x21024a0d, - 0x21016011, - 0x60204308, - 0x43082103, - 0x60206268, - 0x4809bd38, - 0xbd384780, - 0x40044000, - 0x21000018, - 0x08930000, - 0x21000280, - 0x000068cf, - 0x21000068, - 0x40041100, - 0xe000e280, - 0x00003bc3, - 0x28004907, - 0x2004d000, - 0xb6724a06, - 0x07c97809, - 0x5810d001, - 0x2080e000, - 0xb240b662, - 0x00004770, - 0x2100026b, - 0x40046058, - 0x4c03b510, - 0xfedcf7ff, - 0x28006820, - 0xbd10d1fa, - 0x40041100, - 0x2041b510, - 0x00c0490e, - 0x490e4788, - 0x6b884602, - 0x24906b49, - 0x04c1014b, - 0x430b0ec9, - 0x4363490a, - 0x43597d49, - 0x689b4b09, - 0xfef9f7ff, - 0xb510bd10, - 0xfef0f7ff, - 0xd1010004, - 0xffe2f7ff, - 0xbd104620, - 0x00003c7d, - 0x40045080, - 0x21000280, - 0x40044000, - 0x8801b510, - 0x0f93050a, - 0xd1034a08, - 0x0d890589, - 0xd0012911, - 0xbd104790, - 0x46044790, - 0xd1032801, - 0xf7ffb672, - 0xb662ffc5, - 0xbd104620, - 0x00002645, - 0x4801b403, - 0xbd019001, - 0x00006fa5, - 0x00000000, - 0x00030001, - 0x001f000a, - 0x00eb0059, - 0x04ea0239, - 0x129709f9, - 0x32a11feb, - 0x660a4a78, - 0x9e8c82fa, - 0xc917b663, - 0xdeedd664, - 0xe5e0e3c1, - 0x000000ff, + { + 0x21000569, + 0x2100045d, + 0x21000491, + 0x21000495, + 0x210004bd, + 0x2100064d, + 0x210006fd, + 0x21000725, + 0x2100052b, + 0x210004f1, + 0x21000767, + 0x21000789, + 0x4710b5f8, + 0x460eb5f8, + 0x25012100, + 0x473004ad, + 0x7803480a, + 0xf80ff000, + 0xd00b079b, + 0x78204c12, + 0xd00728ff, + 0x702121ff, + 0x240f490e, + 0x43200224, + 0x82c83160, + 0xb5f8bdf8, + 0x47004801, + 0x2100026b, + 0x00004ce5, + 0xe0014809, + 0x0c004808, + 0x49054c06, + 0x2aff7822, + 0x7acad101, + 0x31607022, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210007f4, + 0x08080f07, + 0xf886f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4708b4f0, + 0x4801b510, + 0x00004700, + 0x00000989, + 0xf818f000, + 0x2950b2e1, + 0x2804d00b, + 0x2806d001, + 0x490dd107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490a2002, + 0x210c780a, + 0xd0024211, + 0x22804908, + 0xbdfe600a, + 0x4907b5fe, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000117, + 0xe000e200, + 0x0000ccf1, + 0x0000d103, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4603b570, + 0x29014615, + 0x2900d006, + 0x4a11d006, + 0xf7ff4628, + 0xbd70ff67, + 0xe000480f, + 0x2405480f, + 0xd8034283, + 0x1e640840, + 0xdcf92c00, + 0x200140e3, + 0x18180340, + 0x29010b82, + 0x4906d007, + 0x31802300, + 0xf7ff4628, + 0xb2e0ff51, + 0x4902bd70, + 0x316c4b04, + 0x0000e7f6, + 0x00005c83, + 0x2386bca0, + 0x230d8300, + 0x210007c4, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x4a22b510, + 0x61512100, + 0x68894921, + 0xd40900c9, + 0x4b204921, + 0x429805ca, + 0xd8016b4b, + 0xe0004313, + 0x634b4393, + 0xf7ff491d, + 0xbd10ff35, + 0x4d1ab538, + 0x28007f28, + 0x481ad127, + 0x09c08800, + 0xd12207c0, + 0x69604c12, + 0xd11e2800, + 0xf0004668, + 0x4668f88f, + 0x28017800, + 0x4668d117, + 0x28107840, + 0x2008d213, + 0x6a686160, + 0x01400940, + 0x4a0e6020, + 0x62d12100, + 0x21024a0d, + 0x21016011, + 0x60204308, + 0x43082103, + 0x60206268, + 0x4809bd38, + 0xbd384780, + 0x40044000, + 0x21000018, + 0x08930000, + 0x21000280, + 0x000068cf, + 0x21000068, + 0x40041100, + 0xe000e280, + 0x00003bc3, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x4c03b510, + 0xfedcf7ff, + 0x28006820, + 0xbd10d1fa, + 0x40041100, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfef9f7ff, + 0xb510bd10, + 0xfef0f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x8801b510, + 0x0f93050a, + 0xd1034a08, + 0x0d890589, + 0xd0012911, + 0xbd104790, + 0x46044790, + 0xd1032801, + 0xf7ffb672, + 0xb662ffc5, + 0xbd104620, + 0x00002645, + 0x4801b403, + 0xbd019001, + 0x00006fa5, + 0x00000000, + 0x00030001, + 0x001f000a, + 0x00eb0059, + 0x04ea0239, + 0x129709f9, + 0x32a11feb, + 0x660a4a78, + 0x9e8c82fa, + 0xc917b663, + 0xdeedd664, + 0xe5e0e3c1, + 0x000000ff, }; #define _NWORD_PATCHIMAGE_SL_LONGRANGE 247 @@ -326,7 +324,6 @@ CPE_PATCH_TYPE patchImageSlLongrange[] = #define _IRQ_PATCH_0 0x21000679 - #ifndef _SL_LONGRANGE_SYSRAM_START #define _SL_LONGRANGE_SYSRAM_START 0x20000000 #endif @@ -345,7 +342,7 @@ CPE_PATCH_TYPE patchImageSlLongrange[] = PATCH_FUN_SPEC void enterSlLongrangeCpePatch(void) { #if (_NWORD_PATCHIMAGE_SL_LONGRANGE > 0) - uint32_t* pPatchVec = (uint32_t*) (_SL_LONGRANGE_CPERAM_START + _SL_LONGRANGE_PATCH_VEC_OFFSET); + uint32_t* pPatchVec = (uint32_t*)(_SL_LONGRANGE_CPERAM_START + _SL_LONGRANGE_PATCH_VEC_OFFSET); memcpy(pPatchVec, patchImageSlLongrange, sizeof(patchImageSlLongrange)); #endif @@ -357,10 +354,9 @@ PATCH_FUN_SPEC void enterSlLongrangeSysPatch(void) PATCH_FUN_SPEC void configureSlLongrangePatch(void) { - uint8_t* pParserPatchTab = (uint8_t*) (_SL_LONGRANGE_CPERAM_START + _SL_LONGRANGE_PARSER_PATCH_TAB_OFFSET); - uint8_t* pPatchTab = (uint8_t*) (_SL_LONGRANGE_CPERAM_START + _SL_LONGRANGE_PATCH_TAB_OFFSET); - uint32_t* pIrqPatch = (uint32_t*) (_SL_LONGRANGE_CPERAM_START + _SL_LONGRANGE_IRQPATCH_OFFSET); - + uint8_t* pParserPatchTab = (uint8_t*)(_SL_LONGRANGE_CPERAM_START + _SL_LONGRANGE_PARSER_PATCH_TAB_OFFSET); + uint8_t* pPatchTab = (uint8_t*)(_SL_LONGRANGE_CPERAM_START + _SL_LONGRANGE_PATCH_TAB_OFFSET); + uint32_t* pIrqPatch = (uint32_t*)(_SL_LONGRANGE_CPERAM_START + _SL_LONGRANGE_IRQPATCH_OFFSET); pPatchTab[80] = 0; pPatchTab[57] = 1; @@ -408,4 +404,3 @@ PATCH_FUN_SPEC void rf_patch_cpe_sl_longrange(void) #endif #endif // _RF_PATCH_CPE_SL_LONGRANGE_H - diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_wb_dsss.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_wb_dsss.h index 5c89185..5e4249e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_wb_dsss.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_wb_dsss.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_patch_cpe_wb_dsss.h -* Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ -* Revision: $Revision: 18756 $ -* -* Description: RF core patch for CC13x0 Wideband DSSS -* -* Copyright (c) 2015, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_cpe_wb_dsss.h + * Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ + * Revision: $Revision: 18756 $ + * + * Description: RF core patch for CC13x0 Wideband DSSS + * + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_CPE_WB_DSSS_H #define _RF_PATCH_CPE_WB_DSSS_H @@ -46,8 +46,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include @@ -69,256 +68,255 @@ extern "C" #define _APPLY_PATCH_TAB #endif - CPE_PATCH_TYPE patchImageWbDsss[] = -{ - 0x21000569, - 0x2100045d, - 0x21000491, - 0x21000495, - 0x210004bd, - 0x2100064d, - 0x210006fd, - 0x21000725, - 0x2100052b, - 0x210004f1, - 0x21000767, - 0x21000789, - 0x4710b5f8, - 0x460eb5f8, - 0x25012100, - 0x473004ad, - 0x7803480a, - 0xf80ff000, - 0xd00b079b, - 0x78204c12, - 0xd00728ff, - 0x702121ff, - 0x240f490e, - 0x43200224, - 0x82c83160, - 0xb5f8bdf8, - 0x47004801, - 0x2100026b, - 0x00004ce5, - 0xe0014809, - 0x0c004808, - 0x49054c06, - 0x2aff7822, - 0x7acad101, - 0x31607022, - 0x467082c8, - 0x47001c80, - 0x40086200, - 0x210007f4, - 0x08080f07, - 0xf886f000, - 0x0a0a9905, - 0xd1092a6c, - 0x61782008, - 0x1c406920, - 0x310a6038, - 0x91056120, - 0x61782000, - 0x0000bdf8, - 0x4708b4f0, - 0x4801b510, - 0x00004700, - 0x00000989, - 0xf818f000, - 0x2950b2e1, - 0x2804d00b, - 0x2806d001, - 0x490dd107, - 0x07c97809, - 0x7821d103, - 0xd4000709, - 0x490a2002, - 0x210c780a, - 0xd0024211, - 0x22804908, - 0xbdfe600a, - 0x4907b5fe, - 0x48044708, - 0x22407801, - 0x70014391, - 0x47004804, - 0x210000c8, - 0x21000117, - 0xe000e200, - 0x0000ccf1, - 0x0000d103, - 0x4605b5ff, - 0x4c03b085, - 0xb5ff4720, - 0x01deb085, - 0x47204c01, - 0x00003ff7, - 0x000041cb, - 0x4603b570, - 0x29014615, - 0x2900d006, - 0x4a11d006, - 0xf7ff4628, - 0xbd70ff67, - 0xe000480f, - 0x2405480f, - 0xd8034283, - 0x1e640840, - 0xdcf92c00, - 0x200140e3, - 0x18180340, - 0x29010b82, - 0x4906d007, - 0x31802300, - 0xf7ff4628, - 0xb2e0ff51, - 0x4902bd70, - 0x316c4b04, - 0x0000e7f6, - 0x00005c83, - 0x2386bca0, - 0x230d8300, - 0x210007c4, - 0x4e1ab5f8, - 0x6b714605, - 0x09cc4819, - 0x2d0001e4, - 0x4918d011, - 0x29027809, - 0x7b00d00f, - 0xb6724304, - 0x4f152001, - 0x47b80240, - 0x38204811, - 0x09c18800, - 0xd00407c9, - 0x7ac0e016, - 0x7b40e7f0, - 0x490fe7ee, - 0x61cc6374, - 0x07c00a40, - 0x2001d00c, - 0x6b310380, - 0xd0012d00, - 0xe0004301, - 0x46084381, - 0x49076331, - 0x63483940, - 0x47b82000, - 0xbdf8b662, - 0x21000280, - 0x21000088, - 0x2100029b, - 0x00003f7b, - 0x40044040, - 0x4a22b510, - 0x61512100, - 0x68894921, - 0xd40900c9, - 0x4b204921, - 0x429805ca, - 0xd8016b4b, - 0xe0004313, - 0x634b4393, - 0xf7ff491d, - 0xbd10ff35, - 0x4d1ab538, - 0x28007f28, - 0x481ad127, - 0x09c08800, - 0xd12207c0, - 0x69604c12, - 0xd11e2800, - 0xf0004668, - 0x4668f88f, - 0x28017800, - 0x4668d117, - 0x28107840, - 0x2008d213, - 0x6a686160, - 0x01400940, - 0x4a0e6020, - 0x62d12100, - 0x21024a0d, - 0x21016011, - 0x60204308, - 0x43082103, - 0x60206268, - 0x4809bd38, - 0xbd384780, - 0x40044000, - 0x21000018, - 0x08930000, - 0x21000280, - 0x000068cf, - 0x21000068, - 0x40041100, - 0xe000e280, - 0x00003bc3, - 0x28004907, - 0x2004d000, - 0xb6724a06, - 0x07c97809, - 0x5810d001, - 0x2080e000, - 0xb240b662, - 0x00004770, - 0x2100026b, - 0x40046058, - 0x4c03b510, - 0xfedcf7ff, - 0x28006820, - 0xbd10d1fa, - 0x40041100, - 0x2041b510, - 0x00c0490e, - 0x490e4788, - 0x6b884602, - 0x24906b49, - 0x04c1014b, - 0x430b0ec9, - 0x4363490a, - 0x43597d49, - 0x689b4b09, - 0xfef9f7ff, - 0xb510bd10, - 0xfef0f7ff, - 0xd1010004, - 0xffe2f7ff, - 0xbd104620, - 0x00003c7d, - 0x40045080, - 0x21000280, - 0x40044000, - 0x8801b510, - 0x0f93050a, - 0xd1034a08, - 0x0d890589, - 0xd0012911, - 0xbd104790, - 0x46044790, - 0xd1032801, - 0xf7ffb672, - 0xb662ffc5, - 0xbd104620, - 0x00002645, - 0x4801b403, - 0xbd019001, - 0x00006fa5, - 0x00000000, - 0x00030001, - 0x001f000a, - 0x00eb0059, - 0x04ea0239, - 0x129709f9, - 0x32a11feb, - 0x660a4a78, - 0x9e8c82fa, - 0xc917b663, - 0xdeedd664, - 0xe5e0e3c1, - 0x000000ff, + { + 0x21000569, + 0x2100045d, + 0x21000491, + 0x21000495, + 0x210004bd, + 0x2100064d, + 0x210006fd, + 0x21000725, + 0x2100052b, + 0x210004f1, + 0x21000767, + 0x21000789, + 0x4710b5f8, + 0x460eb5f8, + 0x25012100, + 0x473004ad, + 0x7803480a, + 0xf80ff000, + 0xd00b079b, + 0x78204c12, + 0xd00728ff, + 0x702121ff, + 0x240f490e, + 0x43200224, + 0x82c83160, + 0xb5f8bdf8, + 0x47004801, + 0x2100026b, + 0x00004ce5, + 0xe0014809, + 0x0c004808, + 0x49054c06, + 0x2aff7822, + 0x7acad101, + 0x31607022, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210007f4, + 0x08080f07, + 0xf886f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4708b4f0, + 0x4801b510, + 0x00004700, + 0x00000989, + 0xf818f000, + 0x2950b2e1, + 0x2804d00b, + 0x2806d001, + 0x490dd107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490a2002, + 0x210c780a, + 0xd0024211, + 0x22804908, + 0xbdfe600a, + 0x4907b5fe, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000117, + 0xe000e200, + 0x0000ccf1, + 0x0000d103, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4603b570, + 0x29014615, + 0x2900d006, + 0x4a11d006, + 0xf7ff4628, + 0xbd70ff67, + 0xe000480f, + 0x2405480f, + 0xd8034283, + 0x1e640840, + 0xdcf92c00, + 0x200140e3, + 0x18180340, + 0x29010b82, + 0x4906d007, + 0x31802300, + 0xf7ff4628, + 0xb2e0ff51, + 0x4902bd70, + 0x316c4b04, + 0x0000e7f6, + 0x00005c83, + 0x2386bca0, + 0x230d8300, + 0x210007c4, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x4a22b510, + 0x61512100, + 0x68894921, + 0xd40900c9, + 0x4b204921, + 0x429805ca, + 0xd8016b4b, + 0xe0004313, + 0x634b4393, + 0xf7ff491d, + 0xbd10ff35, + 0x4d1ab538, + 0x28007f28, + 0x481ad127, + 0x09c08800, + 0xd12207c0, + 0x69604c12, + 0xd11e2800, + 0xf0004668, + 0x4668f88f, + 0x28017800, + 0x4668d117, + 0x28107840, + 0x2008d213, + 0x6a686160, + 0x01400940, + 0x4a0e6020, + 0x62d12100, + 0x21024a0d, + 0x21016011, + 0x60204308, + 0x43082103, + 0x60206268, + 0x4809bd38, + 0xbd384780, + 0x40044000, + 0x21000018, + 0x08930000, + 0x21000280, + 0x000068cf, + 0x21000068, + 0x40041100, + 0xe000e280, + 0x00003bc3, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x4c03b510, + 0xfedcf7ff, + 0x28006820, + 0xbd10d1fa, + 0x40041100, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfef9f7ff, + 0xb510bd10, + 0xfef0f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x8801b510, + 0x0f93050a, + 0xd1034a08, + 0x0d890589, + 0xd0012911, + 0xbd104790, + 0x46044790, + 0xd1032801, + 0xf7ffb672, + 0xb662ffc5, + 0xbd104620, + 0x00002645, + 0x4801b403, + 0xbd019001, + 0x00006fa5, + 0x00000000, + 0x00030001, + 0x001f000a, + 0x00eb0059, + 0x04ea0239, + 0x129709f9, + 0x32a11feb, + 0x660a4a78, + 0x9e8c82fa, + 0xc917b663, + 0xdeedd664, + 0xe5e0e3c1, + 0x000000ff, }; #define _NWORD_PATCHIMAGE_WB_DSSS 247 @@ -326,7 +324,6 @@ CPE_PATCH_TYPE patchImageWbDsss[] = #define _IRQ_PATCH_0 0x21000679 - #ifndef _WB_DSSS_SYSRAM_START #define _WB_DSSS_SYSRAM_START 0x20000000 #endif @@ -345,7 +342,7 @@ CPE_PATCH_TYPE patchImageWbDsss[] = PATCH_FUN_SPEC void enterWbDsssCpePatch(void) { #if (_NWORD_PATCHIMAGE_WB_DSSS > 0) - uint32_t* pPatchVec = (uint32_t*) (_WB_DSSS_CPERAM_START + _WB_DSSS_PATCH_VEC_OFFSET); + uint32_t* pPatchVec = (uint32_t*)(_WB_DSSS_CPERAM_START + _WB_DSSS_PATCH_VEC_OFFSET); memcpy(pPatchVec, patchImageWbDsss, sizeof(patchImageWbDsss)); #endif @@ -357,10 +354,9 @@ PATCH_FUN_SPEC void enterWbDsssSysPatch(void) PATCH_FUN_SPEC void configureWbDsssPatch(void) { - uint8_t* pParserPatchTab = (uint8_t*) (_WB_DSSS_CPERAM_START + _WB_DSSS_PARSER_PATCH_TAB_OFFSET); - uint8_t* pPatchTab = (uint8_t*) (_WB_DSSS_CPERAM_START + _WB_DSSS_PATCH_TAB_OFFSET); - uint32_t* pIrqPatch = (uint32_t*) (_WB_DSSS_CPERAM_START + _WB_DSSS_IRQPATCH_OFFSET); - + uint8_t* pParserPatchTab = (uint8_t*)(_WB_DSSS_CPERAM_START + _WB_DSSS_PARSER_PATCH_TAB_OFFSET); + uint8_t* pPatchTab = (uint8_t*)(_WB_DSSS_CPERAM_START + _WB_DSSS_PATCH_TAB_OFFSET); + uint32_t* pIrqPatch = (uint32_t*)(_WB_DSSS_CPERAM_START + _WB_DSSS_IRQPATCH_OFFSET); pPatchTab[80] = 0; pPatchTab[57] = 1; @@ -408,4 +404,3 @@ PATCH_FUN_SPEC void rf_patch_cpe_wb_dsss(void) #endif #endif // _RF_PATCH_CPE_WB_DSSS_H - diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_wmbus_ctmode.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_wmbus_ctmode.h index cd0682b..97e24f7 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_wmbus_ctmode.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_wmbus_ctmode.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_patch_cpe_wmbus_ctmode.h -* Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ -* Revision: $Revision: 18756 $ -* -* Description: RF core patch for CC13x0 WMBUS C- and T-Mode -* -* Copyright (c) 2015, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_cpe_wmbus_ctmode.h + * Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ + * Revision: $Revision: 18756 $ + * + * Description: RF core patch for CC13x0 WMBUS C- and T-Mode + * + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_CPE_WMBUS_CTMODE_H #define _RF_PATCH_CPE_WMBUS_CTMODE_H @@ -46,8 +46,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include @@ -69,256 +68,255 @@ extern "C" #define _APPLY_PATCH_TAB #endif - CPE_PATCH_TYPE patchImageWmbusCtmode[] = -{ - 0x21000569, - 0x2100045d, - 0x21000491, - 0x21000495, - 0x210004bd, - 0x2100064d, - 0x210006fd, - 0x21000725, - 0x2100052b, - 0x210004f1, - 0x21000767, - 0x21000789, - 0x4710b5f8, - 0x460eb5f8, - 0x25012100, - 0x473004ad, - 0x7803480a, - 0xf80ff000, - 0xd00b079b, - 0x78204c12, - 0xd00728ff, - 0x702121ff, - 0x240f490e, - 0x43200224, - 0x82c83160, - 0xb5f8bdf8, - 0x47004801, - 0x2100026b, - 0x00004ce5, - 0xe0014809, - 0x0c004808, - 0x49054c06, - 0x2aff7822, - 0x7acad101, - 0x31607022, - 0x467082c8, - 0x47001c80, - 0x40086200, - 0x210007f4, - 0x08080f07, - 0xf886f000, - 0x0a0a9905, - 0xd1092a6c, - 0x61782008, - 0x1c406920, - 0x310a6038, - 0x91056120, - 0x61782000, - 0x0000bdf8, - 0x4708b4f0, - 0x4801b510, - 0x00004700, - 0x00000989, - 0xf818f000, - 0x2950b2e1, - 0x2804d00b, - 0x2806d001, - 0x490dd107, - 0x07c97809, - 0x7821d103, - 0xd4000709, - 0x490a2002, - 0x210c780a, - 0xd0024211, - 0x22804908, - 0xbdfe600a, - 0x4907b5fe, - 0x48044708, - 0x22407801, - 0x70014391, - 0x47004804, - 0x210000c8, - 0x21000117, - 0xe000e200, - 0x0000ccf1, - 0x0000d103, - 0x4605b5ff, - 0x4c03b085, - 0xb5ff4720, - 0x01deb085, - 0x47204c01, - 0x00003ff7, - 0x000041cb, - 0x4603b570, - 0x29014615, - 0x2900d006, - 0x4a11d006, - 0xf7ff4628, - 0xbd70ff67, - 0xe000480f, - 0x2405480f, - 0xd8034283, - 0x1e640840, - 0xdcf92c00, - 0x200140e3, - 0x18180340, - 0x29010b82, - 0x4906d007, - 0x31802300, - 0xf7ff4628, - 0xb2e0ff51, - 0x4902bd70, - 0x316c4b04, - 0x0000e7f6, - 0x00005c83, - 0x2386bca0, - 0x230d8300, - 0x210007c4, - 0x4e1ab5f8, - 0x6b714605, - 0x09cc4819, - 0x2d0001e4, - 0x4918d011, - 0x29027809, - 0x7b00d00f, - 0xb6724304, - 0x4f152001, - 0x47b80240, - 0x38204811, - 0x09c18800, - 0xd00407c9, - 0x7ac0e016, - 0x7b40e7f0, - 0x490fe7ee, - 0x61cc6374, - 0x07c00a40, - 0x2001d00c, - 0x6b310380, - 0xd0012d00, - 0xe0004301, - 0x46084381, - 0x49076331, - 0x63483940, - 0x47b82000, - 0xbdf8b662, - 0x21000280, - 0x21000088, - 0x2100029b, - 0x00003f7b, - 0x40044040, - 0x4a22b510, - 0x61512100, - 0x68894921, - 0xd40900c9, - 0x4b204921, - 0x429805ca, - 0xd8016b4b, - 0xe0004313, - 0x634b4393, - 0xf7ff491d, - 0xbd10ff35, - 0x4d1ab538, - 0x28007f28, - 0x481ad127, - 0x09c08800, - 0xd12207c0, - 0x69604c12, - 0xd11e2800, - 0xf0004668, - 0x4668f88f, - 0x28017800, - 0x4668d117, - 0x28107840, - 0x2008d213, - 0x6a686160, - 0x01400940, - 0x4a0e6020, - 0x62d12100, - 0x21024a0d, - 0x21016011, - 0x60204308, - 0x43082103, - 0x60206268, - 0x4809bd38, - 0xbd384780, - 0x40044000, - 0x21000018, - 0x08930000, - 0x21000280, - 0x000068cf, - 0x21000068, - 0x40041100, - 0xe000e280, - 0x00003bc3, - 0x28004907, - 0x2004d000, - 0xb6724a06, - 0x07c97809, - 0x5810d001, - 0x2080e000, - 0xb240b662, - 0x00004770, - 0x2100026b, - 0x40046058, - 0x4c03b510, - 0xfedcf7ff, - 0x28006820, - 0xbd10d1fa, - 0x40041100, - 0x2041b510, - 0x00c0490e, - 0x490e4788, - 0x6b884602, - 0x24906b49, - 0x04c1014b, - 0x430b0ec9, - 0x4363490a, - 0x43597d49, - 0x689b4b09, - 0xfef9f7ff, - 0xb510bd10, - 0xfef0f7ff, - 0xd1010004, - 0xffe2f7ff, - 0xbd104620, - 0x00003c7d, - 0x40045080, - 0x21000280, - 0x40044000, - 0x8801b510, - 0x0f93050a, - 0xd1034a08, - 0x0d890589, - 0xd0012911, - 0xbd104790, - 0x46044790, - 0xd1032801, - 0xf7ffb672, - 0xb662ffc5, - 0xbd104620, - 0x00002645, - 0x4801b403, - 0xbd019001, - 0x00006fa5, - 0x00000000, - 0x00030001, - 0x001f000a, - 0x00eb0059, - 0x04ea0239, - 0x129709f9, - 0x32a11feb, - 0x660a4a78, - 0x9e8c82fa, - 0xc917b663, - 0xdeedd664, - 0xe5e0e3c1, - 0x000000ff, + { + 0x21000569, + 0x2100045d, + 0x21000491, + 0x21000495, + 0x210004bd, + 0x2100064d, + 0x210006fd, + 0x21000725, + 0x2100052b, + 0x210004f1, + 0x21000767, + 0x21000789, + 0x4710b5f8, + 0x460eb5f8, + 0x25012100, + 0x473004ad, + 0x7803480a, + 0xf80ff000, + 0xd00b079b, + 0x78204c12, + 0xd00728ff, + 0x702121ff, + 0x240f490e, + 0x43200224, + 0x82c83160, + 0xb5f8bdf8, + 0x47004801, + 0x2100026b, + 0x00004ce5, + 0xe0014809, + 0x0c004808, + 0x49054c06, + 0x2aff7822, + 0x7acad101, + 0x31607022, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210007f4, + 0x08080f07, + 0xf886f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4708b4f0, + 0x4801b510, + 0x00004700, + 0x00000989, + 0xf818f000, + 0x2950b2e1, + 0x2804d00b, + 0x2806d001, + 0x490dd107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490a2002, + 0x210c780a, + 0xd0024211, + 0x22804908, + 0xbdfe600a, + 0x4907b5fe, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000117, + 0xe000e200, + 0x0000ccf1, + 0x0000d103, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4603b570, + 0x29014615, + 0x2900d006, + 0x4a11d006, + 0xf7ff4628, + 0xbd70ff67, + 0xe000480f, + 0x2405480f, + 0xd8034283, + 0x1e640840, + 0xdcf92c00, + 0x200140e3, + 0x18180340, + 0x29010b82, + 0x4906d007, + 0x31802300, + 0xf7ff4628, + 0xb2e0ff51, + 0x4902bd70, + 0x316c4b04, + 0x0000e7f6, + 0x00005c83, + 0x2386bca0, + 0x230d8300, + 0x210007c4, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x4a22b510, + 0x61512100, + 0x68894921, + 0xd40900c9, + 0x4b204921, + 0x429805ca, + 0xd8016b4b, + 0xe0004313, + 0x634b4393, + 0xf7ff491d, + 0xbd10ff35, + 0x4d1ab538, + 0x28007f28, + 0x481ad127, + 0x09c08800, + 0xd12207c0, + 0x69604c12, + 0xd11e2800, + 0xf0004668, + 0x4668f88f, + 0x28017800, + 0x4668d117, + 0x28107840, + 0x2008d213, + 0x6a686160, + 0x01400940, + 0x4a0e6020, + 0x62d12100, + 0x21024a0d, + 0x21016011, + 0x60204308, + 0x43082103, + 0x60206268, + 0x4809bd38, + 0xbd384780, + 0x40044000, + 0x21000018, + 0x08930000, + 0x21000280, + 0x000068cf, + 0x21000068, + 0x40041100, + 0xe000e280, + 0x00003bc3, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x4c03b510, + 0xfedcf7ff, + 0x28006820, + 0xbd10d1fa, + 0x40041100, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfef9f7ff, + 0xb510bd10, + 0xfef0f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x8801b510, + 0x0f93050a, + 0xd1034a08, + 0x0d890589, + 0xd0012911, + 0xbd104790, + 0x46044790, + 0xd1032801, + 0xf7ffb672, + 0xb662ffc5, + 0xbd104620, + 0x00002645, + 0x4801b403, + 0xbd019001, + 0x00006fa5, + 0x00000000, + 0x00030001, + 0x001f000a, + 0x00eb0059, + 0x04ea0239, + 0x129709f9, + 0x32a11feb, + 0x660a4a78, + 0x9e8c82fa, + 0xc917b663, + 0xdeedd664, + 0xe5e0e3c1, + 0x000000ff, }; #define _NWORD_PATCHIMAGE_WMBUS_CTMODE 247 @@ -326,7 +324,6 @@ CPE_PATCH_TYPE patchImageWmbusCtmode[] = #define _IRQ_PATCH_0 0x21000679 - #ifndef _WMBUS_CTMODE_SYSRAM_START #define _WMBUS_CTMODE_SYSRAM_START 0x20000000 #endif @@ -345,7 +342,7 @@ CPE_PATCH_TYPE patchImageWmbusCtmode[] = PATCH_FUN_SPEC void enterWmbusCtmodeCpePatch(void) { #if (_NWORD_PATCHIMAGE_WMBUS_CTMODE > 0) - uint32_t* pPatchVec = (uint32_t*) (_WMBUS_CTMODE_CPERAM_START + _WMBUS_CTMODE_PATCH_VEC_OFFSET); + uint32_t* pPatchVec = (uint32_t*)(_WMBUS_CTMODE_CPERAM_START + _WMBUS_CTMODE_PATCH_VEC_OFFSET); memcpy(pPatchVec, patchImageWmbusCtmode, sizeof(patchImageWmbusCtmode)); #endif @@ -357,10 +354,9 @@ PATCH_FUN_SPEC void enterWmbusCtmodeSysPatch(void) PATCH_FUN_SPEC void configureWmbusCtmodePatch(void) { - uint8_t* pParserPatchTab = (uint8_t*) (_WMBUS_CTMODE_CPERAM_START + _WMBUS_CTMODE_PARSER_PATCH_TAB_OFFSET); - uint8_t* pPatchTab = (uint8_t*) (_WMBUS_CTMODE_CPERAM_START + _WMBUS_CTMODE_PATCH_TAB_OFFSET); - uint32_t* pIrqPatch = (uint32_t*) (_WMBUS_CTMODE_CPERAM_START + _WMBUS_CTMODE_IRQPATCH_OFFSET); - + uint8_t* pParserPatchTab = (uint8_t*)(_WMBUS_CTMODE_CPERAM_START + _WMBUS_CTMODE_PARSER_PATCH_TAB_OFFSET); + uint8_t* pPatchTab = (uint8_t*)(_WMBUS_CTMODE_CPERAM_START + _WMBUS_CTMODE_PATCH_TAB_OFFSET); + uint32_t* pIrqPatch = (uint32_t*)(_WMBUS_CTMODE_CPERAM_START + _WMBUS_CTMODE_IRQPATCH_OFFSET); pPatchTab[80] = 0; pPatchTab[57] = 1; @@ -408,4 +404,3 @@ PATCH_FUN_SPEC void rf_patch_cpe_wmbus_ctmode(void) #endif #endif // _RF_PATCH_CPE_WMBUS_CTMODE_H - diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_wmbus_smode.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_wmbus_smode.h index 7a32627..e06accd 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_wmbus_smode.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_cpe_wmbus_smode.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_patch_cpe_wmbus_smode.h -* Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ -* Revision: $Revision: 18756 $ -* -* Description: RF core patch for CC13x0 WMBUS S-Mode -* -* Copyright (c) 2015, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_cpe_wmbus_smode.h + * Revised: $Date: 2018-11-02 11:52:02 +0100 (fr, 02 nov 2018) $ + * Revision: $Revision: 18756 $ + * + * Description: RF core patch for CC13x0 WMBUS S-Mode + * + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_CPE_WMBUS_SMODE_H #define _RF_PATCH_CPE_WMBUS_SMODE_H @@ -46,8 +46,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include @@ -69,256 +68,255 @@ extern "C" #define _APPLY_PATCH_TAB #endif - CPE_PATCH_TYPE patchImageWmbusSmode[] = -{ - 0x21000569, - 0x2100045d, - 0x21000491, - 0x21000495, - 0x210004bd, - 0x2100064d, - 0x210006fd, - 0x21000725, - 0x2100052b, - 0x210004f1, - 0x21000767, - 0x21000789, - 0x4710b5f8, - 0x460eb5f8, - 0x25012100, - 0x473004ad, - 0x7803480a, - 0xf80ff000, - 0xd00b079b, - 0x78204c12, - 0xd00728ff, - 0x702121ff, - 0x240f490e, - 0x43200224, - 0x82c83160, - 0xb5f8bdf8, - 0x47004801, - 0x2100026b, - 0x00004ce5, - 0xe0014809, - 0x0c004808, - 0x49054c06, - 0x2aff7822, - 0x7acad101, - 0x31607022, - 0x467082c8, - 0x47001c80, - 0x40086200, - 0x210007f4, - 0x08080f07, - 0xf886f000, - 0x0a0a9905, - 0xd1092a6c, - 0x61782008, - 0x1c406920, - 0x310a6038, - 0x91056120, - 0x61782000, - 0x0000bdf8, - 0x4708b4f0, - 0x4801b510, - 0x00004700, - 0x00000989, - 0xf818f000, - 0x2950b2e1, - 0x2804d00b, - 0x2806d001, - 0x490dd107, - 0x07c97809, - 0x7821d103, - 0xd4000709, - 0x490a2002, - 0x210c780a, - 0xd0024211, - 0x22804908, - 0xbdfe600a, - 0x4907b5fe, - 0x48044708, - 0x22407801, - 0x70014391, - 0x47004804, - 0x210000c8, - 0x21000117, - 0xe000e200, - 0x0000ccf1, - 0x0000d103, - 0x4605b5ff, - 0x4c03b085, - 0xb5ff4720, - 0x01deb085, - 0x47204c01, - 0x00003ff7, - 0x000041cb, - 0x4603b570, - 0x29014615, - 0x2900d006, - 0x4a11d006, - 0xf7ff4628, - 0xbd70ff67, - 0xe000480f, - 0x2405480f, - 0xd8034283, - 0x1e640840, - 0xdcf92c00, - 0x200140e3, - 0x18180340, - 0x29010b82, - 0x4906d007, - 0x31802300, - 0xf7ff4628, - 0xb2e0ff51, - 0x4902bd70, - 0x316c4b04, - 0x0000e7f6, - 0x00005c83, - 0x2386bca0, - 0x230d8300, - 0x210007c4, - 0x4e1ab5f8, - 0x6b714605, - 0x09cc4819, - 0x2d0001e4, - 0x4918d011, - 0x29027809, - 0x7b00d00f, - 0xb6724304, - 0x4f152001, - 0x47b80240, - 0x38204811, - 0x09c18800, - 0xd00407c9, - 0x7ac0e016, - 0x7b40e7f0, - 0x490fe7ee, - 0x61cc6374, - 0x07c00a40, - 0x2001d00c, - 0x6b310380, - 0xd0012d00, - 0xe0004301, - 0x46084381, - 0x49076331, - 0x63483940, - 0x47b82000, - 0xbdf8b662, - 0x21000280, - 0x21000088, - 0x2100029b, - 0x00003f7b, - 0x40044040, - 0x4a22b510, - 0x61512100, - 0x68894921, - 0xd40900c9, - 0x4b204921, - 0x429805ca, - 0xd8016b4b, - 0xe0004313, - 0x634b4393, - 0xf7ff491d, - 0xbd10ff35, - 0x4d1ab538, - 0x28007f28, - 0x481ad127, - 0x09c08800, - 0xd12207c0, - 0x69604c12, - 0xd11e2800, - 0xf0004668, - 0x4668f88f, - 0x28017800, - 0x4668d117, - 0x28107840, - 0x2008d213, - 0x6a686160, - 0x01400940, - 0x4a0e6020, - 0x62d12100, - 0x21024a0d, - 0x21016011, - 0x60204308, - 0x43082103, - 0x60206268, - 0x4809bd38, - 0xbd384780, - 0x40044000, - 0x21000018, - 0x08930000, - 0x21000280, - 0x000068cf, - 0x21000068, - 0x40041100, - 0xe000e280, - 0x00003bc3, - 0x28004907, - 0x2004d000, - 0xb6724a06, - 0x07c97809, - 0x5810d001, - 0x2080e000, - 0xb240b662, - 0x00004770, - 0x2100026b, - 0x40046058, - 0x4c03b510, - 0xfedcf7ff, - 0x28006820, - 0xbd10d1fa, - 0x40041100, - 0x2041b510, - 0x00c0490e, - 0x490e4788, - 0x6b884602, - 0x24906b49, - 0x04c1014b, - 0x430b0ec9, - 0x4363490a, - 0x43597d49, - 0x689b4b09, - 0xfef9f7ff, - 0xb510bd10, - 0xfef0f7ff, - 0xd1010004, - 0xffe2f7ff, - 0xbd104620, - 0x00003c7d, - 0x40045080, - 0x21000280, - 0x40044000, - 0x8801b510, - 0x0f93050a, - 0xd1034a08, - 0x0d890589, - 0xd0012911, - 0xbd104790, - 0x46044790, - 0xd1032801, - 0xf7ffb672, - 0xb662ffc5, - 0xbd104620, - 0x00002645, - 0x4801b403, - 0xbd019001, - 0x00006fa5, - 0x00000000, - 0x00030001, - 0x001f000a, - 0x00eb0059, - 0x04ea0239, - 0x129709f9, - 0x32a11feb, - 0x660a4a78, - 0x9e8c82fa, - 0xc917b663, - 0xdeedd664, - 0xe5e0e3c1, - 0x000000ff, + { + 0x21000569, + 0x2100045d, + 0x21000491, + 0x21000495, + 0x210004bd, + 0x2100064d, + 0x210006fd, + 0x21000725, + 0x2100052b, + 0x210004f1, + 0x21000767, + 0x21000789, + 0x4710b5f8, + 0x460eb5f8, + 0x25012100, + 0x473004ad, + 0x7803480a, + 0xf80ff000, + 0xd00b079b, + 0x78204c12, + 0xd00728ff, + 0x702121ff, + 0x240f490e, + 0x43200224, + 0x82c83160, + 0xb5f8bdf8, + 0x47004801, + 0x2100026b, + 0x00004ce5, + 0xe0014809, + 0x0c004808, + 0x49054c06, + 0x2aff7822, + 0x7acad101, + 0x31607022, + 0x467082c8, + 0x47001c80, + 0x40086200, + 0x210007f4, + 0x08080f07, + 0xf886f000, + 0x0a0a9905, + 0xd1092a6c, + 0x61782008, + 0x1c406920, + 0x310a6038, + 0x91056120, + 0x61782000, + 0x0000bdf8, + 0x4708b4f0, + 0x4801b510, + 0x00004700, + 0x00000989, + 0xf818f000, + 0x2950b2e1, + 0x2804d00b, + 0x2806d001, + 0x490dd107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490a2002, + 0x210c780a, + 0xd0024211, + 0x22804908, + 0xbdfe600a, + 0x4907b5fe, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000117, + 0xe000e200, + 0x0000ccf1, + 0x0000d103, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01deb085, + 0x47204c01, + 0x00003ff7, + 0x000041cb, + 0x4603b570, + 0x29014615, + 0x2900d006, + 0x4a11d006, + 0xf7ff4628, + 0xbd70ff67, + 0xe000480f, + 0x2405480f, + 0xd8034283, + 0x1e640840, + 0xdcf92c00, + 0x200140e3, + 0x18180340, + 0x29010b82, + 0x4906d007, + 0x31802300, + 0xf7ff4628, + 0xb2e0ff51, + 0x4902bd70, + 0x316c4b04, + 0x0000e7f6, + 0x00005c83, + 0x2386bca0, + 0x230d8300, + 0x210007c4, + 0x4e1ab5f8, + 0x6b714605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6374, + 0x07c00a40, + 0x2001d00c, + 0x6b310380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x49076331, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x2100029b, + 0x00003f7b, + 0x40044040, + 0x4a22b510, + 0x61512100, + 0x68894921, + 0xd40900c9, + 0x4b204921, + 0x429805ca, + 0xd8016b4b, + 0xe0004313, + 0x634b4393, + 0xf7ff491d, + 0xbd10ff35, + 0x4d1ab538, + 0x28007f28, + 0x481ad127, + 0x09c08800, + 0xd12207c0, + 0x69604c12, + 0xd11e2800, + 0xf0004668, + 0x4668f88f, + 0x28017800, + 0x4668d117, + 0x28107840, + 0x2008d213, + 0x6a686160, + 0x01400940, + 0x4a0e6020, + 0x62d12100, + 0x21024a0d, + 0x21016011, + 0x60204308, + 0x43082103, + 0x60206268, + 0x4809bd38, + 0xbd384780, + 0x40044000, + 0x21000018, + 0x08930000, + 0x21000280, + 0x000068cf, + 0x21000068, + 0x40041100, + 0xe000e280, + 0x00003bc3, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x4c03b510, + 0xfedcf7ff, + 0x28006820, + 0xbd10d1fa, + 0x40041100, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597d49, + 0x689b4b09, + 0xfef9f7ff, + 0xb510bd10, + 0xfef0f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003c7d, + 0x40045080, + 0x21000280, + 0x40044000, + 0x8801b510, + 0x0f93050a, + 0xd1034a08, + 0x0d890589, + 0xd0012911, + 0xbd104790, + 0x46044790, + 0xd1032801, + 0xf7ffb672, + 0xb662ffc5, + 0xbd104620, + 0x00002645, + 0x4801b403, + 0xbd019001, + 0x00006fa5, + 0x00000000, + 0x00030001, + 0x001f000a, + 0x00eb0059, + 0x04ea0239, + 0x129709f9, + 0x32a11feb, + 0x660a4a78, + 0x9e8c82fa, + 0xc917b663, + 0xdeedd664, + 0xe5e0e3c1, + 0x000000ff, }; #define _NWORD_PATCHIMAGE_WMBUS_SMODE 247 @@ -326,7 +324,6 @@ CPE_PATCH_TYPE patchImageWmbusSmode[] = #define _IRQ_PATCH_0 0x21000679 - #ifndef _WMBUS_SMODE_SYSRAM_START #define _WMBUS_SMODE_SYSRAM_START 0x20000000 #endif @@ -345,7 +342,7 @@ CPE_PATCH_TYPE patchImageWmbusSmode[] = PATCH_FUN_SPEC void enterWmbusSmodeCpePatch(void) { #if (_NWORD_PATCHIMAGE_WMBUS_SMODE > 0) - uint32_t* pPatchVec = (uint32_t*) (_WMBUS_SMODE_CPERAM_START + _WMBUS_SMODE_PATCH_VEC_OFFSET); + uint32_t* pPatchVec = (uint32_t*)(_WMBUS_SMODE_CPERAM_START + _WMBUS_SMODE_PATCH_VEC_OFFSET); memcpy(pPatchVec, patchImageWmbusSmode, sizeof(patchImageWmbusSmode)); #endif @@ -357,10 +354,9 @@ PATCH_FUN_SPEC void enterWmbusSmodeSysPatch(void) PATCH_FUN_SPEC void configureWmbusSmodePatch(void) { - uint8_t* pParserPatchTab = (uint8_t*) (_WMBUS_SMODE_CPERAM_START + _WMBUS_SMODE_PARSER_PATCH_TAB_OFFSET); - uint8_t* pPatchTab = (uint8_t*) (_WMBUS_SMODE_CPERAM_START + _WMBUS_SMODE_PATCH_TAB_OFFSET); - uint32_t* pIrqPatch = (uint32_t*) (_WMBUS_SMODE_CPERAM_START + _WMBUS_SMODE_IRQPATCH_OFFSET); - + uint8_t* pParserPatchTab = (uint8_t*)(_WMBUS_SMODE_CPERAM_START + _WMBUS_SMODE_PARSER_PATCH_TAB_OFFSET); + uint8_t* pPatchTab = (uint8_t*)(_WMBUS_SMODE_CPERAM_START + _WMBUS_SMODE_PATCH_TAB_OFFSET); + uint32_t* pIrqPatch = (uint32_t*)(_WMBUS_SMODE_CPERAM_START + _WMBUS_SMODE_IRQPATCH_OFFSET); pPatchTab[80] = 0; pPatchTab[57] = 1; @@ -408,4 +404,3 @@ PATCH_FUN_SPEC void rf_patch_cpe_wmbus_smode(void) #endif #endif // _RF_PATCH_CPE_WMBUS_SMODE_H - diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_brepeat.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_brepeat.h index b1fdb58..293935c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_brepeat.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_brepeat.h @@ -1,368 +1,367 @@ /****************************************************************************** -* Filename: rf_patch_mce_brepeat.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 for 1.2kbps and 2.4kbps Generic FSK -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_mce_brepeat.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 for 1.2kbps and 2.4kbps Generic FSK + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_MCE_BREPEAT_H #define _RF_PATCH_MCE_BREPEAT_H -#include #include "../inc/hw_types.h" +#include #ifndef MCE_PATCH_TYPE - #define MCE_PATCH_TYPE static const uint32_t +#define MCE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_MCERAM_BASE - #define RFC_MCERAM_BASE 0x21008000 +#define RFC_MCERAM_BASE 0x21008000 #endif #ifndef MCE_PATCH_MODE - #define MCE_PATCH_MODE 0 +#define MCE_PATCH_MODE 0 #endif MCE_PATCH_TYPE patchBrepeatMce[302] = -{ - 0x2fcf604e, - 0x030c3f9d, - 0x070c680a, - 0x00068080, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xf80007c0, - 0x1f0000f8, - 0xe007003f, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00070003, - 0x00003d1f, - 0x04000000, - 0x0000000f, - 0x000b0387, - 0x004348f4, - 0x80078000, - 0x00000670, - 0x0510091e, - 0x00070054, - 0x1f080100, - 0x00000031, - 0x3030002f, - 0x0000027f, - 0x00000000, - 0x0000aa00, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x72487220, - 0x7303a32d, - 0x72037305, - 0x73067304, - 0x73767204, - 0xc7c07276, - 0x00018001, - 0x90109001, - 0x90010801, - 0x720d720c, - 0xb0c0720e, - 0xb0f07100, - 0x7218a0c0, - 0x10208132, - 0x06703952, - 0x16300020, - 0x14011101, - 0x60836c01, - 0x60a06084, - 0x60836178, - 0x60836083, - 0x12106083, - 0x730f7220, - 0x73117310, - 0x00108181, - 0xb0709180, - 0x60796063, - 0x6656c030, - 0xc282c1e1, - 0x1820c470, - 0x6e236f13, - 0x16121611, - 0x7830688a, - 0x78409ab0, - 0x78509ac0, - 0xc4829ad0, - 0x1820c5a0, - 0x1203409d, - 0x16126e23, - 0x7870689a, - 0x607997e0, - 0xb1087276, - 0xb0f3b100, - 0xb0d8b0f1, - 0xb1087100, - 0xb200a0d8, - 0x87e0b760, - 0xb0f19780, - 0x7100b0c1, - 0xb0f17276, - 0xb012a0c1, - 0xb013b002, - 0xb484b003, - 0xb101b0d1, - 0x7100722c, - 0x8140b101, - 0x06f03940, - 0x06f38143, - 0x65b18161, - 0x1a133911, - 0x68c04cc3, - 0x22f08140, - 0x814044bd, - 0x16103980, - 0x85e11203, - 0x1a111403, - 0x44d01e01, - 0x1c13c211, - 0xc31148fa, - 0x48eb1c13, - 0x10301813, - 0x1ef08451, - 0xc10040e5, - 0x1a101830, - 0x68e23911, - 0x65b11030, - 0x68e53911, - 0x12f08461, - 0xc21160f7, - 0x10301813, - 0x1ef08461, - 0xc10040f7, - 0x1a101830, - 0x68f43911, - 0x65b11030, - 0x68f73911, - 0x12f08431, - 0x391165b1, - 0x844168fc, - 0x65b112f0, - 0x69013911, - 0x81a1721c, - 0x81e065a4, - 0x41052220, - 0xc040a0d1, - 0xc0309780, - 0xb0c19760, - 0x7100b0f1, - 0xa0c1b0f1, - 0x72487276, - 0xa002a003, - 0x73057248, - 0x73767306, - 0xa2007276, - 0x9010c7c0, - 0xb0066079, - 0xb004b016, - 0xb002b014, - 0x7810b012, - 0x90509030, - 0x90407820, - 0xb2059060, - 0x83038ae2, - 0x65ba9302, - 0xb064857f, - 0xc00bc00c, - 0xb072b011, - 0xa0c0a0c1, - 0xb0e6b116, - 0x22d18ab1, - 0xb0f24141, - 0x7100b0c2, - 0xa760b073, - 0xb7607378, - 0x226080b0, - 0x661c454b, - 0xb88f6141, - 0x18f08960, - 0x100f9550, - 0xa0c2720e, - 0xb0d7b201, - 0x7100b107, - 0x8ad0b041, - 0x415d22e0, - 0x22208210, - 0xb04d4536, - 0xc300b06d, - 0xb2019070, - 0x6656c040, - 0x7000a044, - 0x8180b88c, - 0x392489a4, - 0x00043184, - 0xc0509184, - 0x73766656, - 0x72487276, - 0x72027206, - 0x73057204, - 0x60797306, - 0xb32d721b, - 0x6656c060, - 0x6521b0f8, - 0xb107b0d7, - 0xb1077100, - 0xb1077100, - 0xb1077100, - 0xb1077100, - 0x8090120a, - 0x44632200, - 0x161a6605, - 0x1e0b815b, - 0x85524189, - 0x9862d070, - 0x1cba6656, - 0x18ab4da2, - 0x499e1efb, - 0x1af010b0, - 0x699c6605, - 0xc0f0a205, - 0x69a06605, - 0x6166a0d7, - 0x45a82201, - 0x61a913f2, - 0x92c21212, - 0x710085e2, - 0x1a12b101, - 0x45ab1e02, - 0x22017000, - 0x13f245b5, - 0x121261b6, - 0x710092c2, - 0x7000b101, - 0x39838143, - 0x94732a73, - 0x1a1085e0, - 0x120f1613, - 0x69c2143f, - 0xc200120b, - 0x41c91c0f, - 0x791b61cb, - 0xc40b61cf, - 0x318b18fb, - 0x8400313b, - 0x04107941, - 0x940000b0, - 0xa405b404, - 0x1e4185e1, - 0x1e3141e9, - 0x841041e1, - 0x31103180, - 0x94203980, - 0x841061ee, - 0x39803180, - 0x31101001, - 0x94201410, - 0x841061ee, - 0x39803180, - 0x94203120, - 0x84301201, - 0x87d097c0, - 0x84401401, - 0x87d097c0, - 0xc1001401, - 0x31111801, - 0x70009571, - 0x22011202, - 0x3a324201, - 0x38326202, - 0x69fd3911, - 0x85e37000, - 0x71001202, - 0xb107b88d, - 0x31818b11, - 0x14123d81, - 0x31818b21, - 0x14123d81, - 0x1e031a13, - 0x22f24607, - 0x12124619, - 0x1202621a, - 0x70009192, - 0x22b08ab0, - 0x1e3b4622, - 0x62244654, - 0x46541e7b, - 0xb889c00b, - 0x31808940, - 0x16103d80, - 0x140c3d30, - 0x226080b0, - 0x70004230, - 0x39838ab3, - 0x8ab106f3, - 0x0401cff0, - 0x1c1c3031, - 0x12004e4c, - 0x1c0c1810, - 0x80b04a4e, - 0x42412260, - 0x10c27000, - 0x3c321612, - 0x83208ae1, - 0x42502210, - 0x93016252, - 0x7000b0f2, - 0x623d101c, - 0x623d100c, - 0x62491821, - 0x62491421, - 0x624a161b, - 0x88409850, - 0x46572200, - 0x7000b830 -}; + { + 0x2fcf604e, + 0x030c3f9d, + 0x070c680a, + 0x00068080, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xf80007c0, + 0x1f0000f8, + 0xe007003f, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00070003, + 0x00003d1f, + 0x04000000, + 0x0000000f, + 0x000b0387, + 0x004348f4, + 0x80078000, + 0x00000670, + 0x0510091e, + 0x00070054, + 0x1f080100, + 0x00000031, + 0x3030002f, + 0x0000027f, + 0x00000000, + 0x0000aa00, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x72487220, + 0x7303a32d, + 0x72037305, + 0x73067304, + 0x73767204, + 0xc7c07276, + 0x00018001, + 0x90109001, + 0x90010801, + 0x720d720c, + 0xb0c0720e, + 0xb0f07100, + 0x7218a0c0, + 0x10208132, + 0x06703952, + 0x16300020, + 0x14011101, + 0x60836c01, + 0x60a06084, + 0x60836178, + 0x60836083, + 0x12106083, + 0x730f7220, + 0x73117310, + 0x00108181, + 0xb0709180, + 0x60796063, + 0x6656c030, + 0xc282c1e1, + 0x1820c470, + 0x6e236f13, + 0x16121611, + 0x7830688a, + 0x78409ab0, + 0x78509ac0, + 0xc4829ad0, + 0x1820c5a0, + 0x1203409d, + 0x16126e23, + 0x7870689a, + 0x607997e0, + 0xb1087276, + 0xb0f3b100, + 0xb0d8b0f1, + 0xb1087100, + 0xb200a0d8, + 0x87e0b760, + 0xb0f19780, + 0x7100b0c1, + 0xb0f17276, + 0xb012a0c1, + 0xb013b002, + 0xb484b003, + 0xb101b0d1, + 0x7100722c, + 0x8140b101, + 0x06f03940, + 0x06f38143, + 0x65b18161, + 0x1a133911, + 0x68c04cc3, + 0x22f08140, + 0x814044bd, + 0x16103980, + 0x85e11203, + 0x1a111403, + 0x44d01e01, + 0x1c13c211, + 0xc31148fa, + 0x48eb1c13, + 0x10301813, + 0x1ef08451, + 0xc10040e5, + 0x1a101830, + 0x68e23911, + 0x65b11030, + 0x68e53911, + 0x12f08461, + 0xc21160f7, + 0x10301813, + 0x1ef08461, + 0xc10040f7, + 0x1a101830, + 0x68f43911, + 0x65b11030, + 0x68f73911, + 0x12f08431, + 0x391165b1, + 0x844168fc, + 0x65b112f0, + 0x69013911, + 0x81a1721c, + 0x81e065a4, + 0x41052220, + 0xc040a0d1, + 0xc0309780, + 0xb0c19760, + 0x7100b0f1, + 0xa0c1b0f1, + 0x72487276, + 0xa002a003, + 0x73057248, + 0x73767306, + 0xa2007276, + 0x9010c7c0, + 0xb0066079, + 0xb004b016, + 0xb002b014, + 0x7810b012, + 0x90509030, + 0x90407820, + 0xb2059060, + 0x83038ae2, + 0x65ba9302, + 0xb064857f, + 0xc00bc00c, + 0xb072b011, + 0xa0c0a0c1, + 0xb0e6b116, + 0x22d18ab1, + 0xb0f24141, + 0x7100b0c2, + 0xa760b073, + 0xb7607378, + 0x226080b0, + 0x661c454b, + 0xb88f6141, + 0x18f08960, + 0x100f9550, + 0xa0c2720e, + 0xb0d7b201, + 0x7100b107, + 0x8ad0b041, + 0x415d22e0, + 0x22208210, + 0xb04d4536, + 0xc300b06d, + 0xb2019070, + 0x6656c040, + 0x7000a044, + 0x8180b88c, + 0x392489a4, + 0x00043184, + 0xc0509184, + 0x73766656, + 0x72487276, + 0x72027206, + 0x73057204, + 0x60797306, + 0xb32d721b, + 0x6656c060, + 0x6521b0f8, + 0xb107b0d7, + 0xb1077100, + 0xb1077100, + 0xb1077100, + 0xb1077100, + 0x8090120a, + 0x44632200, + 0x161a6605, + 0x1e0b815b, + 0x85524189, + 0x9862d070, + 0x1cba6656, + 0x18ab4da2, + 0x499e1efb, + 0x1af010b0, + 0x699c6605, + 0xc0f0a205, + 0x69a06605, + 0x6166a0d7, + 0x45a82201, + 0x61a913f2, + 0x92c21212, + 0x710085e2, + 0x1a12b101, + 0x45ab1e02, + 0x22017000, + 0x13f245b5, + 0x121261b6, + 0x710092c2, + 0x7000b101, + 0x39838143, + 0x94732a73, + 0x1a1085e0, + 0x120f1613, + 0x69c2143f, + 0xc200120b, + 0x41c91c0f, + 0x791b61cb, + 0xc40b61cf, + 0x318b18fb, + 0x8400313b, + 0x04107941, + 0x940000b0, + 0xa405b404, + 0x1e4185e1, + 0x1e3141e9, + 0x841041e1, + 0x31103180, + 0x94203980, + 0x841061ee, + 0x39803180, + 0x31101001, + 0x94201410, + 0x841061ee, + 0x39803180, + 0x94203120, + 0x84301201, + 0x87d097c0, + 0x84401401, + 0x87d097c0, + 0xc1001401, + 0x31111801, + 0x70009571, + 0x22011202, + 0x3a324201, + 0x38326202, + 0x69fd3911, + 0x85e37000, + 0x71001202, + 0xb107b88d, + 0x31818b11, + 0x14123d81, + 0x31818b21, + 0x14123d81, + 0x1e031a13, + 0x22f24607, + 0x12124619, + 0x1202621a, + 0x70009192, + 0x22b08ab0, + 0x1e3b4622, + 0x62244654, + 0x46541e7b, + 0xb889c00b, + 0x31808940, + 0x16103d80, + 0x140c3d30, + 0x226080b0, + 0x70004230, + 0x39838ab3, + 0x8ab106f3, + 0x0401cff0, + 0x1c1c3031, + 0x12004e4c, + 0x1c0c1810, + 0x80b04a4e, + 0x42412260, + 0x10c27000, + 0x3c321612, + 0x83208ae1, + 0x42502210, + 0x93016252, + 0x7000b0f2, + 0x623d101c, + 0x623d100c, + 0x62491821, + 0x62491421, + 0x624a161b, + 0x88409850, + 0x46572200, + 0x7000b830}; PATCH_FUN_SPEC void rf_patch_mce_brepeat(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genfsk.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genfsk.h index c8378c5..5a2c9e2 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genfsk.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genfsk.h @@ -1,526 +1,525 @@ /****************************************************************************** -* Filename: rf_patch_mce_genfsk.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 Generic FSK -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_mce_genfsk.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 Generic FSK + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_MCE_GENFSK_H #define _RF_PATCH_MCE_GENFSK_H -#include #include "../inc/hw_types.h" +#include #ifndef MCE_PATCH_TYPE - #define MCE_PATCH_TYPE static const uint32_t +#define MCE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_MCERAM_BASE - #define RFC_MCERAM_BASE 0x21008000 +#define RFC_MCERAM_BASE 0x21008000 #endif #ifndef MCE_PATCH_MODE - #define MCE_PATCH_MODE 0 +#define MCE_PATCH_MODE 0 #endif MCE_PATCH_TYPE patchGenfskMce[460] = -{ - 0x2fcf602b, - 0x030c3f9d, - 0x070c680a, - 0xfff0003f, - 0xff0000ff, - 0x00030006, - 0x3d1f0007, - 0x00000000, - 0x000f0400, - 0x03870000, - 0x40f4000b, - 0x80000043, - 0x06708082, - 0x091e0000, - 0x00540510, - 0x02000005, - 0x00613e10, - 0x002f0000, - 0x027f3030, - 0x00000000, - 0xaa000000, - 0x72200000, - 0xa32d7248, - 0x73057303, - 0x73047203, - 0x72047306, - 0x72767376, - 0x8001c7c0, - 0x90010001, - 0x08019010, - 0x720c9001, - 0x720e720d, - 0x7100b0c0, - 0xa0c0b0f0, - 0x81327218, - 0x39521020, - 0x00200670, - 0x11011630, - 0x6c011401, - 0x60696068, - 0x635360e5, - 0x60686068, - 0x60686068, - 0x60696068, - 0x635360e5, - 0x60686068, - 0x60686068, - 0x72201210, - 0x7310730f, - 0x81817311, - 0x91800010, - 0x6040b070, - 0xc030605e, - 0xc0b16792, - 0xc470c282, - 0x6f131820, - 0x16116e23, - 0x686f1612, - 0x9ab07830, - 0x9ac07840, - 0x9ad07850, - 0xc5a0c482, - 0x40821820, - 0x6e231203, - 0x687f1612, - 0x97e078a0, - 0x7276605e, - 0x94908160, - 0x39808140, - 0x10012a70, - 0x84321611, - 0xc0f38444, - 0xc200c0f5, - 0x40aa1c01, - 0x1c10c100, - 0x4ca240a0, - 0x18031013, - 0x1a131830, - 0x39121a10, - 0x60aa689d, - 0x60aa13f3, - 0x101513f3, - 0x1850c100, - 0x1a101a15, - 0x68a83914, - 0x7100b0d8, - 0xa0d8b108, - 0xb760b200, - 0x978087e0, - 0xb0c1b0f1, - 0xb0027100, - 0xb0f1b012, - 0x7276a0c1, - 0xb003b480, - 0x7229b013, - 0x7100b0d0, - 0x8140b100, - 0x71009290, - 0x8140b100, - 0x44c322f0, - 0x1c0313f0, - 0x929340cf, - 0x71009492, - 0x9295b100, - 0x71009494, - 0xb0d0b100, - 0x7000a480, - 0xc030a0d1, - 0xc0409760, - 0xb0f19780, - 0x7100b0c1, - 0xa0c1b0f1, - 0xa0037276, - 0xa200a002, - 0x730f7000, - 0xc0407310, - 0xc1006792, - 0x648591c0, - 0xb0f3b483, - 0x7100b0c3, - 0x64d6a0c3, - 0xb006605e, - 0xb004b016, - 0xb002b014, - 0x8400b012, - 0x04207862, - 0x39838143, - 0x94732a73, - 0x1832c1f2, - 0x10213162, - 0x00123151, - 0x94000020, - 0x16101030, - 0x31211001, - 0x22103930, - 0x12204110, - 0x10033150, - 0x00103180, - 0x93501630, - 0x12041202, - 0x41232273, - 0x97c08430, - 0x1a8287d2, - 0x97c08450, - 0x1a8487d4, - 0x22636125, - 0x84404130, - 0x87d097c0, - 0x14021a80, - 0x97c08460, - 0x1a8087d0, - 0x613c1404, - 0x78918440, - 0x97c00410, - 0x1a4287d2, - 0x78918460, - 0x97c00410, - 0x1a4487d4, - 0x31543152, - 0x06333963, - 0x38321613, - 0x31823834, - 0x31843982, - 0x95720042, - 0x90307810, - 0x78209050, - 0x90609040, - 0x8ae2b205, - 0x93028303, - 0xc00bc00c, - 0x31808140, - 0x39403980, - 0xc0f38141, - 0xc0140431, - 0xc0021441, - 0x695e1412, - 0x847d3122, - 0x140dc010, - 0x142d312d, - 0x318e8ace, - 0x397e311e, - 0x31498ac9, - 0x39493979, - 0x109a3129, - 0x720d720c, - 0xb101720e, - 0x7100b0d1, - 0xa0d1b072, - 0xb06ea04e, - 0xb06cb011, - 0x978ab089, - 0xb7647276, - 0xc662a764, - 0xc04f9762, - 0x8ab166d4, - 0x458c22f1, - 0x22f18ad1, - 0x6232458c, - 0xb0737100, - 0x80b7b760, - 0x45c32207, - 0x8ab1a760, - 0x419d22f1, - 0x419d2237, - 0x80b0b113, - 0x45982230, - 0x22e161ab, - 0x809041b0, - 0x41b02250, - 0x8210b0f5, - 0x418c2220, - 0xb7649789, - 0xb0f6a764, - 0x978d618c, - 0xa764b764, - 0x618cb0f6, - 0x22f08ad0, - 0x223741bc, - 0xb07541bc, - 0x80b0b113, - 0x45b62230, - 0x618cb087, - 0x431722d1, - 0x22208090, - 0x669a4317, - 0x978f618c, - 0x8410c7f3, - 0x39803180, - 0x00303183, - 0xb0879410, - 0xb0f2a0e3, - 0xb0f5a0c2, - 0xb0f1a0c5, - 0xa0c6b0c1, - 0xb113b110, - 0x220080b0, - 0x223045d4, - 0x710045d4, - 0x97801260, - 0xb88fb0f1, - 0x85708961, - 0x95511801, - 0x8a718a60, - 0xa487a488, - 0x1801c022, - 0x4df41c21, - 0x49f21412, - 0x1c0161f5, - 0x4df441f5, - 0x61f5b487, - 0xb041b488, - 0x8ad0b061, - 0x41fd22e0, - 0x22208210, - 0x71004570, - 0xb06eb04e, - 0x220180b1, - 0x2231468c, - 0x7276468c, - 0x8471b0f6, - 0xc2603121, - 0x97801410, - 0x9760c7e0, - 0x9760c6f0, - 0xb0c6b0f6, - 0xb7b0a0c1, - 0x8a748a63, - 0x8a948a83, - 0x80b17100, - 0x468c2201, - 0x468c2231, - 0x22c08ab0, - 0x89914624, - 0x41702201, - 0xc00081c1, - 0x847091c0, - 0x6a2881a2, - 0xc30091c1, - 0xb2019070, - 0xa0e3a0e0, - 0x7000a044, - 0xb0737100, - 0x80b7b760, - 0x46512207, - 0x466f2237, - 0x8ab1a760, - 0x424a22e1, - 0x22508090, - 0xb0f5424a, - 0x22208210, - 0x978d4232, - 0xa764b764, - 0x6232b0f6, - 0x431722d1, - 0x22208090, - 0x669a4317, - 0x978f6232, - 0xa0c2b0f2, - 0xa0c5b0f5, - 0xb0c1b0f1, - 0xb110a0c6, - 0x80b0b113, - 0x46592200, - 0x46592230, - 0x12607100, - 0xb0f19780, - 0x8961b88f, - 0x31808570, - 0x18013d80, - 0x8a609551, - 0xa1828a71, - 0x978f61e6, - 0xa0c2b0f2, - 0xa0c5b0f5, - 0xb0c1b0f1, - 0xb110a0c6, - 0x80b0b113, - 0x46772200, - 0x46772230, - 0x12607100, - 0xb0f19780, - 0x8961b88f, - 0x3d808570, - 0x95511801, - 0x8a918a80, - 0x61e6b182, - 0xa760b073, - 0xa7b0b760, - 0xa04eb072, - 0xb011b06e, - 0x22f08ab0, - 0x220145c3, - 0x626f4651, - 0x22b08ab0, - 0x1e3b46a0, - 0x62a246d2, - 0x46d21e7b, - 0xb889c00b, - 0x31808940, - 0x16103d80, - 0x140c3d30, - 0x220080b0, - 0x700042ae, - 0x39838ab3, - 0x8ab106f3, - 0x0401cff0, - 0x1c1c3031, - 0x12004eca, - 0x1c0c1810, - 0x80b04acc, - 0x42bf2200, - 0x10c27000, - 0x3c321612, - 0x83208ae1, - 0x42ce2210, - 0x930162d0, - 0x7000b0f2, - 0x62bb101c, - 0x62bb100c, - 0x62c71821, - 0x62c71421, - 0x62c8161b, - 0xb0f1b0f6, - 0xb113b110, - 0xb0f2b0f5, - 0x720d720c, - 0xb0e0720e, - 0x8ab2b0e3, - 0x42e522f2, - 0xb763b0c6, - 0x8ad062e8, - 0x430822f0, - 0xa404b405, - 0xa429b428, - 0x3180caa0, - 0x0001caa1, - 0x94619451, - 0x31838ad3, - 0x84103983, - 0x39803180, - 0x00303183, - 0x84009410, - 0x39503150, - 0x39838ad3, - 0xc1f406f3, - 0x31841834, - 0x00403134, - 0xb0899400, - 0x431222e2, - 0x394a8aca, - 0x312a398a, - 0xb0c5978a, - 0xb763b0c6, - 0x22d28ab2, - 0xb0c24316, - 0xb20f7000, - 0xa0e3a0e0, - 0xb764978e, - 0xb0f6a764, - 0xb113b110, - 0x22f08210, - 0xb0f54320, - 0xa0048002, - 0xa001a006, - 0x72047203, - 0x6792c050, - 0xb7647100, - 0xb0c5b0f6, - 0x7100a20f, - 0xa0c5b0f5, - 0x90307810, - 0x78209002, - 0x90609040, - 0xa20fb072, - 0x978a66d4, - 0xb0f6a764, - 0xb88c6185, - 0x89a48180, - 0x31843924, - 0x91840004, - 0x6792c060, - 0x72767376, - 0x72067248, - 0x72047202, - 0x73067305, - 0x1300605e, - 0xb32d91b0, - 0x6792c070, - 0x64f3b0f8, - 0x1a101200, - 0xc3809780, - 0xc2809760, - 0xa0c19760, - 0x8090b0c6, - 0x44402200, - 0x1e048154, - 0x97844363, - 0x8552b0f6, - 0x9862d080, - 0x89916792, - 0x43792211, - 0x8a938a82, - 0x9862e090, - 0x67929873, - 0x8a62637f, - 0xe0a08a73, - 0x98739862, - 0x87906792, - 0x1c018781, - 0x18014b8f, - 0x4b8d1ef1, - 0x1af18781, - 0x71009781, - 0x16f1b0f6, - 0xa2059781, - 0xb0f67100, - 0x6341a0c6, - 0x88409850, - 0x47932200, - 0x7000b830 -}; + { + 0x2fcf602b, + 0x030c3f9d, + 0x070c680a, + 0xfff0003f, + 0xff0000ff, + 0x00030006, + 0x3d1f0007, + 0x00000000, + 0x000f0400, + 0x03870000, + 0x40f4000b, + 0x80000043, + 0x06708082, + 0x091e0000, + 0x00540510, + 0x02000005, + 0x00613e10, + 0x002f0000, + 0x027f3030, + 0x00000000, + 0xaa000000, + 0x72200000, + 0xa32d7248, + 0x73057303, + 0x73047203, + 0x72047306, + 0x72767376, + 0x8001c7c0, + 0x90010001, + 0x08019010, + 0x720c9001, + 0x720e720d, + 0x7100b0c0, + 0xa0c0b0f0, + 0x81327218, + 0x39521020, + 0x00200670, + 0x11011630, + 0x6c011401, + 0x60696068, + 0x635360e5, + 0x60686068, + 0x60686068, + 0x60696068, + 0x635360e5, + 0x60686068, + 0x60686068, + 0x72201210, + 0x7310730f, + 0x81817311, + 0x91800010, + 0x6040b070, + 0xc030605e, + 0xc0b16792, + 0xc470c282, + 0x6f131820, + 0x16116e23, + 0x686f1612, + 0x9ab07830, + 0x9ac07840, + 0x9ad07850, + 0xc5a0c482, + 0x40821820, + 0x6e231203, + 0x687f1612, + 0x97e078a0, + 0x7276605e, + 0x94908160, + 0x39808140, + 0x10012a70, + 0x84321611, + 0xc0f38444, + 0xc200c0f5, + 0x40aa1c01, + 0x1c10c100, + 0x4ca240a0, + 0x18031013, + 0x1a131830, + 0x39121a10, + 0x60aa689d, + 0x60aa13f3, + 0x101513f3, + 0x1850c100, + 0x1a101a15, + 0x68a83914, + 0x7100b0d8, + 0xa0d8b108, + 0xb760b200, + 0x978087e0, + 0xb0c1b0f1, + 0xb0027100, + 0xb0f1b012, + 0x7276a0c1, + 0xb003b480, + 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0x78209050, + 0x90609040, + 0x8ae2b205, + 0x93028303, + 0xc00bc00c, + 0x31808140, + 0x39403980, + 0xc0f38141, + 0xc0140431, + 0xc0021441, + 0x695e1412, + 0x847d3122, + 0x140dc010, + 0x142d312d, + 0x318e8ace, + 0x397e311e, + 0x31498ac9, + 0x39493979, + 0x109a3129, + 0x720d720c, + 0xb101720e, + 0x7100b0d1, + 0xa0d1b072, + 0xb06ea04e, + 0xb06cb011, + 0x978ab089, + 0xb7647276, + 0xc662a764, + 0xc04f9762, + 0x8ab166d4, + 0x458c22f1, + 0x22f18ad1, + 0x6232458c, + 0xb0737100, + 0x80b7b760, + 0x45c32207, + 0x8ab1a760, + 0x419d22f1, + 0x419d2237, + 0x80b0b113, + 0x45982230, + 0x22e161ab, + 0x809041b0, + 0x41b02250, + 0x8210b0f5, + 0x418c2220, + 0xb7649789, + 0xb0f6a764, + 0x978d618c, + 0xa764b764, + 0x618cb0f6, + 0x22f08ad0, + 0x223741bc, + 0xb07541bc, + 0x80b0b113, + 0x45b62230, + 0x618cb087, + 0x431722d1, + 0x22208090, + 0x669a4317, + 0x978f618c, + 0x8410c7f3, + 0x39803180, + 0x00303183, + 0xb0879410, + 0xb0f2a0e3, + 0xb0f5a0c2, + 0xb0f1a0c5, + 0xa0c6b0c1, + 0xb113b110, + 0x220080b0, + 0x223045d4, + 0x710045d4, + 0x97801260, + 0xb88fb0f1, + 0x85708961, + 0x95511801, + 0x8a718a60, + 0xa487a488, + 0x1801c022, + 0x4df41c21, + 0x49f21412, + 0x1c0161f5, + 0x4df441f5, + 0x61f5b487, + 0xb041b488, + 0x8ad0b061, + 0x41fd22e0, + 0x22208210, + 0x71004570, + 0xb06eb04e, + 0x220180b1, + 0x2231468c, + 0x7276468c, + 0x8471b0f6, + 0xc2603121, + 0x97801410, + 0x9760c7e0, + 0x9760c6f0, + 0xb0c6b0f6, + 0xb7b0a0c1, + 0x8a748a63, + 0x8a948a83, + 0x80b17100, + 0x468c2201, + 0x468c2231, + 0x22c08ab0, + 0x89914624, + 0x41702201, + 0xc00081c1, + 0x847091c0, + 0x6a2881a2, + 0xc30091c1, + 0xb2019070, + 0xa0e3a0e0, + 0x7000a044, + 0xb0737100, + 0x80b7b760, + 0x46512207, + 0x466f2237, + 0x8ab1a760, + 0x424a22e1, + 0x22508090, + 0xb0f5424a, + 0x22208210, + 0x978d4232, + 0xa764b764, + 0x6232b0f6, + 0x431722d1, + 0x22208090, + 0x669a4317, + 0x978f6232, + 0xa0c2b0f2, + 0xa0c5b0f5, + 0xb0c1b0f1, + 0xb110a0c6, + 0x80b0b113, + 0x46592200, + 0x46592230, + 0x12607100, + 0xb0f19780, + 0x8961b88f, + 0x31808570, + 0x18013d80, + 0x8a609551, + 0xa1828a71, + 0x978f61e6, + 0xa0c2b0f2, + 0xa0c5b0f5, + 0xb0c1b0f1, + 0xb110a0c6, + 0x80b0b113, + 0x46772200, + 0x46772230, + 0x12607100, + 0xb0f19780, + 0x8961b88f, + 0x3d808570, + 0x95511801, + 0x8a918a80, + 0x61e6b182, + 0xa760b073, + 0xa7b0b760, + 0xa04eb072, + 0xb011b06e, + 0x22f08ab0, + 0x220145c3, + 0x626f4651, + 0x22b08ab0, + 0x1e3b46a0, + 0x62a246d2, + 0x46d21e7b, + 0xb889c00b, + 0x31808940, + 0x16103d80, + 0x140c3d30, + 0x220080b0, + 0x700042ae, + 0x39838ab3, + 0x8ab106f3, + 0x0401cff0, + 0x1c1c3031, + 0x12004eca, + 0x1c0c1810, + 0x80b04acc, + 0x42bf2200, + 0x10c27000, + 0x3c321612, + 0x83208ae1, + 0x42ce2210, + 0x930162d0, + 0x7000b0f2, + 0x62bb101c, + 0x62bb100c, + 0x62c71821, + 0x62c71421, + 0x62c8161b, + 0xb0f1b0f6, + 0xb113b110, + 0xb0f2b0f5, + 0x720d720c, + 0xb0e0720e, + 0x8ab2b0e3, + 0x42e522f2, + 0xb763b0c6, + 0x8ad062e8, + 0x430822f0, + 0xa404b405, + 0xa429b428, + 0x3180caa0, + 0x0001caa1, + 0x94619451, + 0x31838ad3, + 0x84103983, + 0x39803180, + 0x00303183, + 0x84009410, + 0x39503150, + 0x39838ad3, + 0xc1f406f3, + 0x31841834, + 0x00403134, + 0xb0899400, + 0x431222e2, + 0x394a8aca, + 0x312a398a, + 0xb0c5978a, + 0xb763b0c6, + 0x22d28ab2, + 0xb0c24316, + 0xb20f7000, + 0xa0e3a0e0, + 0xb764978e, + 0xb0f6a764, + 0xb113b110, + 0x22f08210, + 0xb0f54320, + 0xa0048002, + 0xa001a006, + 0x72047203, + 0x6792c050, + 0xb7647100, + 0xb0c5b0f6, + 0x7100a20f, + 0xa0c5b0f5, + 0x90307810, + 0x78209002, + 0x90609040, + 0xa20fb072, + 0x978a66d4, + 0xb0f6a764, + 0xb88c6185, + 0x89a48180, + 0x31843924, + 0x91840004, + 0x6792c060, + 0x72767376, + 0x72067248, + 0x72047202, + 0x73067305, + 0x1300605e, + 0xb32d91b0, + 0x6792c070, + 0x64f3b0f8, + 0x1a101200, + 0xc3809780, + 0xc2809760, + 0xa0c19760, + 0x8090b0c6, + 0x44402200, + 0x1e048154, + 0x97844363, + 0x8552b0f6, + 0x9862d080, + 0x89916792, + 0x43792211, + 0x8a938a82, + 0x9862e090, + 0x67929873, + 0x8a62637f, + 0xe0a08a73, + 0x98739862, + 0x87906792, + 0x1c018781, + 0x18014b8f, + 0x4b8d1ef1, + 0x1af18781, + 0x71009781, + 0x16f1b0f6, + 0xa2059781, + 0xb0f67100, + 0x6341a0c6, + 0x88409850, + 0x47932200, + 0x7000b830}; PATCH_FUN_SPEC void rf_patch_mce_genfsk(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genfsk_ant_div_pqt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genfsk_ant_div_pqt.h index e6d86ca..0a434fd 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genfsk_ant_div_pqt.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genfsk_ant_div_pqt.h @@ -1,481 +1,480 @@ /****************************************************************************** -* Filename: rf_patch_mce_genfsk_ant_div_pqt.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 Generic FSK PQT based antenna diversity -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_mce_genfsk_ant_div_pqt.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 Generic FSK PQT based antenna diversity + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_MCE_GENFSK_ANT_DIV_PQT_H #define _RF_PATCH_MCE_GENFSK_ANT_DIV_PQT_H -#include #include "../inc/hw_types.h" +#include #ifndef MCE_PATCH_TYPE - #define MCE_PATCH_TYPE static const uint32_t +#define MCE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_MCERAM_BASE - #define RFC_MCERAM_BASE 0x21008000 +#define RFC_MCERAM_BASE 0x21008000 #endif #ifndef MCE_PATCH_MODE - #define MCE_PATCH_MODE 0 +#define MCE_PATCH_MODE 0 #endif MCE_PATCH_TYPE patchGenfskAntDivPqtMce[415] = -{ - 0x2fcf602d, - 0x00003f9d, - 0x470a031a, - 0x000f0387, - 0xff00ffcf, - 0x80000006, - 0x00070003, - 0x00003d1f, - 0x04000000, - 0x0000000f, - 0x000b0387, - 0x004340f4, - 0x80828000, - 0x00000670, - 0x0510091e, - 0x00050054, - 0x3e100200, - 0x00000061, - 0x0c30002f, - 0x0000017f, - 0xaaaa0000, - 0x0000aaaa, - 0x72200000, - 0xa32d7248, - 0x73057303, - 0x73047203, - 0x72047306, - 0x72767376, - 0x8001c7c0, - 0x90010001, - 0x08019010, - 0x720c9001, - 0x720e720d, - 0x7100b0c0, - 0xa0c0b0f0, - 0x81327218, - 0x39521020, - 0x00200670, - 0x11011630, - 0x6c011401, - 0x606c606a, - 0x62cf60e4, - 0x606a606a, - 0x606b606a, - 0x606c606a, - 0x62cf60e4, - 0x606a606a, - 0x606b606a, - 0x72201210, - 0x7310730f, - 0x81817311, - 0x91800010, - 0x6042b070, - 0x60606060, - 0x6738c030, - 0xc282c0c1, - 0x1820c470, - 0x6e236f13, - 0x16121611, - 0x78306872, - 0x78409ab0, - 0x78509ac0, - 0x78609ad0, - 0xc4829ae0, - 0x1820c5a0, - 0x12034087, - 0x16126e23, - 0x60606884, - 0x94908160, - 0x39808140, - 0x10012a70, - 0x84321611, - 0xc0f38444, - 0xc200c0f5, - 0x40ac1c01, - 0x1c10c100, - 0x4ca440a2, - 0x18031013, - 0x1a131830, - 0x39121a10, - 0x60ac689f, - 0x60ac13f3, - 0x101513f3, - 0x1850c100, - 0x1a101a15, - 0x68aa3914, - 0x7100b0d8, - 0xa0d8b108, - 0x85e0b005, - 0x44b51e00, - 0xb24060b7, - 0xb200a005, - 0xb003b480, - 0xb002b013, - 0x7229b012, - 0x7100b0d0, - 0x8140b100, - 0x71009290, - 0x8140b100, - 0x44c322f0, - 0x1c0313f0, - 0x929340cf, - 0x71009492, - 0x9295b100, - 0x71009494, - 0xb0d0b100, - 0x7000a480, - 0xc030a0d1, - 0xc0409760, - 0xb0f19780, - 0x7100b0c1, - 0xa0c1b0f1, - 0xa0037276, - 0x7000a002, - 0x7310730f, - 0xd04085e1, - 0x67389861, - 0x91c0c100, - 0xb4836488, - 0xb0c3b0f3, - 0xa0c37100, - 0x606064d6, - 0xb016b006, - 0xb014b004, - 0xb012b002, - 0x78728400, - 0x81430420, - 0x2a733983, - 0xc1f29473, - 0x31621832, - 0x31511021, - 0x00200012, - 0x3142c022, - 0x94000020, - 0x16101030, - 0x31211001, - 0x22103930, - 0x12204114, - 0x10033150, - 0x00103180, - 0x93501630, - 0x12041202, - 0x41272273, - 0x97c08430, - 0x1a8287d2, - 0x97c08450, - 0x1a8487d4, - 0x22636129, - 0x84404134, - 0x87d097c0, - 0x14021a80, - 0x97c08460, - 0x1a8087d0, - 0x61401404, - 0x78918440, - 0x97c00410, - 0x1a4287d2, - 0x78918460, - 0x97c00410, - 0x1a4487d4, - 0x31543152, - 0x06333963, - 0x38321613, - 0x31823834, - 0x31843982, - 0x95720042, - 0x90307810, - 0x78209050, - 0x90609040, - 0x31808200, - 0x78b13980, - 0x92001410, - 0x8ae2b205, - 0x93028303, - 0x31808140, - 0x39403980, - 0xc0f38141, - 0xc0140431, - 0xc0021441, - 0x69661412, - 0x847d3122, - 0x8ac0161d, - 0x39803180, - 0x312d140d, - 0xc200142d, - 0x180d3120, - 0xa04eb072, - 0xb011b06e, - 0x7276b06c, - 0xa764b764, - 0x9762c662, - 0x7255c04f, - 0xb0f1b0f6, - 0xb113b110, - 0x720d720c, - 0xa0e0720e, - 0xb405b0e3, - 0x8ad3a404, - 0x39833183, - 0x31808410, - 0x31833980, - 0x94100030, - 0x31508400, - 0x8ad33950, - 0x06f33983, - 0x1834c1f4, - 0x31343184, - 0x94000040, - 0xa0e0b089, - 0xb0c1a0e3, - 0xb228b005, - 0x84017880, - 0xc0200401, - 0x00013140, - 0x72769401, - 0x9760c030, - 0x821a6702, - 0x1a1078a0, - 0xa7609780, - 0xb113b760, - 0x672cb0f1, - 0x8ac07100, - 0x97803980, - 0xb760a760, - 0x80b0b0f1, - 0x45cd2230, - 0x10a0b064, - 0x06103920, - 0x45cb1e00, - 0x7100b069, - 0x8ad061a6, - 0x41dc22e0, - 0x392010a0, - 0x1e000610, - 0x10a345dc, - 0x3d833143, - 0x16118611, - 0x61cb9611, - 0x314310a3, - 0xd0503d83, - 0x67389863, - 0x8ac0b064, - 0x78a13980, - 0x97801410, - 0xb760a760, - 0xb0f1b113, - 0x7100672c, - 0x223080b0, - 0x61fd45f2, - 0x31428212, - 0xd0603d82, - 0x67389862, - 0x1c23671b, - 0x67024a16, - 0x67026211, - 0x31428212, - 0xd0703d82, - 0x67389862, - 0x78a0671b, - 0x97801a10, - 0xb760a760, - 0x7100b0f1, - 0xc012b069, - 0x31823172, - 0x10203d82, - 0x10031032, - 0x6217670a, - 0x7276670a, - 0x9760c660, - 0x7880978d, - 0x04018401, - 0xc0509401, - 0xa76393b0, - 0xb0e0b763, - 0xb110a0e3, - 0xb0f6b113, - 0xa0c1b0c6, - 0xb064b0f1, - 0xb0737100, - 0xb0c1879c, - 0xa760a0c6, - 0x80b0b760, - 0x463d2200, - 0x16118601, - 0xd0809601, - 0x67389861, - 0x978f6174, - 0xb0f1a0e3, - 0xa0c6b0c1, - 0x80b0b110, - 0x46422200, - 0x12607100, - 0xb0f19780, - 0x8961b88f, - 0x18018570, - 0x8a609551, - 0xa4888a71, - 0xc022a487, - 0x1c211801, - 0x14124e5f, - 0x62604a5d, - 0x42601c01, - 0xb4874e5f, - 0xb4886260, - 0xb061b041, - 0xb04e7100, - 0x80b1b06e, - 0x46912201, - 0xb0f67276, - 0x31218471, - 0x1410c260, - 0xc7e09780, - 0xc6f09760, - 0xb0f69760, - 0xa0c1b0c6, - 0x8a63b7b0, - 0x71008a74, - 0x220180b1, - 0x8ab04691, - 0x468422c0, - 0x22018991, - 0x62914684, - 0xc00081c1, - 0x847091c0, - 0x6a8881a2, - 0xc30091c1, - 0xb2019070, - 0xa044a0e0, - 0x87907000, - 0xc360140c, - 0x1cdc180c, - 0x86014a9e, - 0x96011611, - 0x9861d090, - 0x61746738, - 0xa760b073, - 0xa7b0b760, - 0xa04eb072, - 0xb011b06e, - 0xb88c623d, - 0x89a48180, - 0x31843924, - 0x91840004, - 0x860385e4, - 0x9864e0a0, - 0x67389873, - 0x46ba1e04, - 0x16108720, - 0x62bd9720, - 0x16108730, - 0x85f29730, - 0x3d821023, - 0x3d833183, - 0x986ce0b0, - 0x6738987d, - 0x72767376, - 0x72067248, - 0x72047202, - 0x73067305, - 0x13006060, - 0xb32d91b0, - 0x6738c0c0, - 0x93b0c030, - 0x64f4b0f8, - 0x1a101200, - 0xc3809780, - 0xc2809760, - 0xa0c19760, - 0x8090b0c6, - 0x44422200, - 0x1e048154, - 0x978442e1, - 0x8552b0f6, - 0x9862d0d0, - 0x8a626738, - 0x87908a73, - 0x1c018781, - 0x18014aff, - 0x4afd1ef1, - 0x1af18781, - 0x71009781, - 0x16f1b0f6, - 0xa2059781, - 0xb0f67100, - 0x62a7a0c6, - 0x22508000, - 0xb0054707, - 0xb2406309, - 0x7000a005, - 0x39833183, - 0x00233182, - 0xa5e095f3, - 0x22548004, - 0xb5e0471a, - 0x102385f2, - 0x31833982, - 0x95f20032, - 0x82007000, - 0x39803180, - 0x4f221c23, - 0x63231021, - 0x31811031, - 0x92001410, - 0x8210a205, - 0x47272210, - 0x7000b205, - 0x8210a205, - 0x472d2210, - 0x31808200, - 0x78b13980, - 0x92001410, - 0x7000b205, - 0x88409850, - 0x47392200, - 0x7000b830 -}; + { + 0x2fcf602d, + 0x00003f9d, + 0x470a031a, + 0x000f0387, + 0xff00ffcf, + 0x80000006, + 0x00070003, + 0x00003d1f, + 0x04000000, + 0x0000000f, + 0x000b0387, + 0x004340f4, + 0x80828000, + 0x00000670, + 0x0510091e, + 0x00050054, + 0x3e100200, + 0x00000061, + 0x0c30002f, + 0x0000017f, + 0xaaaa0000, + 0x0000aaaa, + 0x72200000, + 0xa32d7248, + 0x73057303, + 0x73047203, + 0x72047306, + 0x72767376, + 0x8001c7c0, + 0x90010001, + 0x08019010, + 0x720c9001, + 0x720e720d, + 0x7100b0c0, + 0xa0c0b0f0, + 0x81327218, + 0x39521020, + 0x00200670, + 0x11011630, + 0x6c011401, + 0x606c606a, + 0x62cf60e4, + 0x606a606a, + 0x606b606a, + 0x606c606a, + 0x62cf60e4, + 0x606a606a, + 0x606b606a, + 0x72201210, + 0x7310730f, + 0x81817311, + 0x91800010, + 0x6042b070, + 0x60606060, + 0x6738c030, + 0xc282c0c1, + 0x1820c470, + 0x6e236f13, + 0x16121611, + 0x78306872, + 0x78409ab0, + 0x78509ac0, + 0x78609ad0, + 0xc4829ae0, + 0x1820c5a0, + 0x12034087, + 0x16126e23, + 0x60606884, + 0x94908160, + 0x39808140, + 0x10012a70, + 0x84321611, + 0xc0f38444, + 0xc200c0f5, + 0x40ac1c01, + 0x1c10c100, + 0x4ca440a2, + 0x18031013, + 0x1a131830, + 0x39121a10, + 0x60ac689f, + 0x60ac13f3, + 0x101513f3, + 0x1850c100, + 0x1a101a15, + 0x68aa3914, + 0x7100b0d8, + 0xa0d8b108, + 0x85e0b005, + 0x44b51e00, + 0xb24060b7, + 0xb200a005, + 0xb003b480, + 0xb002b013, + 0x7229b012, + 0x7100b0d0, + 0x8140b100, + 0x71009290, + 0x8140b100, + 0x44c322f0, + 0x1c0313f0, + 0x929340cf, + 0x71009492, + 0x9295b100, + 0x71009494, + 0xb0d0b100, + 0x7000a480, + 0xc030a0d1, + 0xc0409760, + 0xb0f19780, + 0x7100b0c1, + 0xa0c1b0f1, + 0xa0037276, + 0x7000a002, + 0x7310730f, + 0xd04085e1, + 0x67389861, + 0x91c0c100, + 0xb4836488, + 0xb0c3b0f3, + 0xa0c37100, + 0x606064d6, + 0xb016b006, + 0xb014b004, + 0xb012b002, + 0x78728400, + 0x81430420, + 0x2a733983, + 0xc1f29473, + 0x31621832, + 0x31511021, + 0x00200012, + 0x3142c022, + 0x94000020, + 0x16101030, + 0x31211001, + 0x22103930, + 0x12204114, + 0x10033150, + 0x00103180, + 0x93501630, + 0x12041202, + 0x41272273, + 0x97c08430, + 0x1a8287d2, + 0x97c08450, + 0x1a8487d4, + 0x22636129, + 0x84404134, + 0x87d097c0, + 0x14021a80, + 0x97c08460, + 0x1a8087d0, + 0x61401404, + 0x78918440, + 0x97c00410, + 0x1a4287d2, + 0x78918460, + 0x97c00410, + 0x1a4487d4, + 0x31543152, + 0x06333963, + 0x38321613, + 0x31823834, + 0x31843982, + 0x95720042, + 0x90307810, + 0x78209050, + 0x90609040, + 0x31808200, + 0x78b13980, + 0x92001410, + 0x8ae2b205, + 0x93028303, + 0x31808140, + 0x39403980, + 0xc0f38141, + 0xc0140431, + 0xc0021441, + 0x69661412, + 0x847d3122, + 0x8ac0161d, + 0x39803180, + 0x312d140d, + 0xc200142d, + 0x180d3120, + 0xa04eb072, + 0xb011b06e, + 0x7276b06c, + 0xa764b764, + 0x9762c662, + 0x7255c04f, + 0xb0f1b0f6, + 0xb113b110, + 0x720d720c, + 0xa0e0720e, + 0xb405b0e3, + 0x8ad3a404, + 0x39833183, + 0x31808410, + 0x31833980, + 0x94100030, + 0x31508400, + 0x8ad33950, + 0x06f33983, + 0x1834c1f4, + 0x31343184, + 0x94000040, + 0xa0e0b089, + 0xb0c1a0e3, + 0xb228b005, + 0x84017880, + 0xc0200401, + 0x00013140, + 0x72769401, + 0x9760c030, + 0x821a6702, + 0x1a1078a0, + 0xa7609780, + 0xb113b760, + 0x672cb0f1, + 0x8ac07100, + 0x97803980, + 0xb760a760, + 0x80b0b0f1, + 0x45cd2230, + 0x10a0b064, + 0x06103920, + 0x45cb1e00, + 0x7100b069, + 0x8ad061a6, + 0x41dc22e0, + 0x392010a0, + 0x1e000610, + 0x10a345dc, + 0x3d833143, + 0x16118611, + 0x61cb9611, + 0x314310a3, + 0xd0503d83, + 0x67389863, + 0x8ac0b064, + 0x78a13980, + 0x97801410, + 0xb760a760, + 0xb0f1b113, + 0x7100672c, + 0x223080b0, + 0x61fd45f2, + 0x31428212, + 0xd0603d82, + 0x67389862, + 0x1c23671b, + 0x67024a16, + 0x67026211, + 0x31428212, + 0xd0703d82, + 0x67389862, + 0x78a0671b, + 0x97801a10, + 0xb760a760, + 0x7100b0f1, + 0xc012b069, + 0x31823172, + 0x10203d82, + 0x10031032, + 0x6217670a, + 0x7276670a, + 0x9760c660, + 0x7880978d, + 0x04018401, + 0xc0509401, + 0xa76393b0, + 0xb0e0b763, + 0xb110a0e3, + 0xb0f6b113, + 0xa0c1b0c6, + 0xb064b0f1, + 0xb0737100, + 0xb0c1879c, + 0xa760a0c6, + 0x80b0b760, + 0x463d2200, + 0x16118601, + 0xd0809601, + 0x67389861, + 0x978f6174, + 0xb0f1a0e3, + 0xa0c6b0c1, + 0x80b0b110, + 0x46422200, + 0x12607100, + 0xb0f19780, + 0x8961b88f, + 0x18018570, + 0x8a609551, + 0xa4888a71, + 0xc022a487, + 0x1c211801, + 0x14124e5f, + 0x62604a5d, + 0x42601c01, + 0xb4874e5f, + 0xb4886260, + 0xb061b041, + 0xb04e7100, + 0x80b1b06e, + 0x46912201, + 0xb0f67276, + 0x31218471, + 0x1410c260, + 0xc7e09780, + 0xc6f09760, + 0xb0f69760, + 0xa0c1b0c6, + 0x8a63b7b0, + 0x71008a74, + 0x220180b1, + 0x8ab04691, + 0x468422c0, + 0x22018991, + 0x62914684, + 0xc00081c1, + 0x847091c0, + 0x6a8881a2, + 0xc30091c1, + 0xb2019070, + 0xa044a0e0, + 0x87907000, + 0xc360140c, + 0x1cdc180c, + 0x86014a9e, + 0x96011611, + 0x9861d090, + 0x61746738, + 0xa760b073, + 0xa7b0b760, + 0xa04eb072, + 0xb011b06e, + 0xb88c623d, + 0x89a48180, + 0x31843924, + 0x91840004, + 0x860385e4, + 0x9864e0a0, + 0x67389873, + 0x46ba1e04, + 0x16108720, + 0x62bd9720, + 0x16108730, + 0x85f29730, + 0x3d821023, + 0x3d833183, + 0x986ce0b0, + 0x6738987d, + 0x72767376, + 0x72067248, + 0x72047202, + 0x73067305, + 0x13006060, + 0xb32d91b0, + 0x6738c0c0, + 0x93b0c030, + 0x64f4b0f8, + 0x1a101200, + 0xc3809780, + 0xc2809760, + 0xa0c19760, + 0x8090b0c6, + 0x44422200, + 0x1e048154, + 0x978442e1, + 0x8552b0f6, + 0x9862d0d0, + 0x8a626738, + 0x87908a73, + 0x1c018781, + 0x18014aff, + 0x4afd1ef1, + 0x1af18781, + 0x71009781, + 0x16f1b0f6, + 0xa2059781, + 0xb0f67100, + 0x62a7a0c6, + 0x22508000, + 0xb0054707, + 0xb2406309, + 0x7000a005, + 0x39833183, + 0x00233182, + 0xa5e095f3, + 0x22548004, + 0xb5e0471a, + 0x102385f2, + 0x31833982, + 0x95f20032, + 0x82007000, + 0x39803180, + 0x4f221c23, + 0x63231021, + 0x31811031, + 0x92001410, + 0x8210a205, + 0x47272210, + 0x7000b205, + 0x8210a205, + 0x472d2210, + 0x31808200, + 0x78b13980, + 0x92001410, + 0x7000b205, + 0x88409850, + 0x47392200, + 0x7000b830}; PATCH_FUN_SPEC void rf_patch_mce_genfsk_ant_div_pqt(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genfsk_fec_cc1101.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genfsk_fec_cc1101.h index d7a8fb0..d92bec6 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genfsk_fec_cc1101.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genfsk_fec_cc1101.h @@ -1,537 +1,536 @@ /****************************************************************************** -* Filename: rf_patch_mce_genfsk_fec_cc1101.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 Generic FSK (with CC1101-compatible FEC and interleaver) -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_mce_genfsk_fec_cc1101.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 Generic FSK (with CC1101-compatible FEC and interleaver) + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_MCE_GENFSK_FEC_CC1101_H #define _RF_PATCH_MCE_GENFSK_FEC_CC1101_H -#include #include "../inc/hw_types.h" +#include #ifndef MCE_PATCH_TYPE - #define MCE_PATCH_TYPE static const uint32_t +#define MCE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_MCERAM_BASE - #define RFC_MCERAM_BASE 0x21008000 +#define RFC_MCERAM_BASE 0x21008000 #endif #ifndef MCE_PATCH_MODE - #define MCE_PATCH_MODE 0 +#define MCE_PATCH_MODE 0 #endif MCE_PATCH_TYPE patchGenfskFecMce[471] = -{ - 0x2fcf6054, - 0x030c0f9d, - 0x070c680a, - 0xff00003f, - 0x07c0d0d0, - 0x130007e0, - 0x50433221, - 0x10037162, - 0x53403122, - 0x00017261, - 0x01000010, - 0x00021000, - 0x02000020, - 0x00042000, - 0x04000040, - 0x00084000, - 0x08000080, - 0x00018000, - 0x00200018, - 0x00200003, - 0x00290011, - 0x0029000a, - 0x00320003, - 0x00320018, - 0x003b000a, - 0x003b0011, - 0x00070003, - 0x00003d1f, - 0x04000000, - 0x0000000f, - 0x000b0387, - 0x004340f4, - 0x80828000, - 0x00000670, - 0x0510091e, - 0x00050054, - 0x3e100200, - 0x00000061, - 0x3030002f, - 0x0000027f, - 0x00000000, - 0x0000aa00, - 0x72487220, - 0x7303a32d, - 0x72037305, - 0x73067304, - 0x73767204, - 0xc7c07276, - 0x00018001, - 0x90109001, - 0x90010801, - 0x720d720c, - 0xb0c0720e, - 0xb0f07100, - 0x7218a0c0, - 0x10208132, - 0x06703952, - 0x16300020, - 0x14011101, - 0x60896c01, - 0x60f0608c, - 0x6089631d, - 0x60896089, - 0x1210608a, - 0x730f7220, - 0x73117310, - 0x00108181, - 0xb0709180, - 0x607f6069, - 0x607f6400, - 0x67a8c030, - 0xc282c341, - 0x1820c470, - 0x6e236f13, - 0x16121611, - 0x78306892, - 0x78409ab0, - 0x78509ac0, - 0x83009ad0, - 0xc4829ae0, - 0x1820c5a0, - 0x120340a7, - 0x16126e23, - 0x607f68a4, - 0x94908160, - 0x39808140, - 0x10012a70, - 0x84321611, - 0xc0f38444, - 0xc200c0f5, - 0x40cc1c01, - 0x1c10c100, - 0x4cc440c2, - 0x18031013, - 0x1a131830, - 0x39121a10, - 0x60cc68bf, - 0x60cc13f3, - 0x101513f3, - 0x1850c100, - 0x1a101a15, - 0x68ca3914, - 0x7100b0d8, - 0xa0d8b108, - 0xb480b200, - 0xb013b003, - 0xb012b002, - 0xb0d07229, - 0xb1007100, - 0x92908140, - 0xb1007100, - 0x22f08140, - 0x13f044dc, - 0x40e81c03, - 0x94929293, - 0xb1007100, - 0x94949295, - 0x71006536, - 0xb0d0b100, - 0x7000a480, - 0x7310730f, - 0x67a8c040, - 0x91c0c000, - 0xc0b7c136, - 0xc009c008, - 0xc00bc00a, - 0xc00dc00c, - 0xc10e788f, - 0x9760c030, - 0x9780c000, - 0xb48464a8, - 0x10acc009, - 0x10f010bd, - 0x1e003980, - 0x81e0411c, - 0x41122210, - 0x611581a0, - 0x061010f0, - 0x6523391f, - 0x654c653c, - 0x1ce91619, - 0x6106450d, - 0x654c653c, - 0x1ce91619, - 0x6556451c, - 0x1081607f, - 0x6f121471, - 0x41292200, - 0x10233982, - 0x311a0613, - 0x1023003a, - 0x06133913, - 0x003b311b, - 0x39481028, - 0x700006f8, - 0x652381a0, - 0x1ce91619, - 0x70004536, - 0x14921062, - 0x10c16f23, - 0x41440431, - 0x61451210, - 0x10d113f0, - 0x414a0431, - 0x614b1211, - 0x700013f1, - 0xb10192c1, - 0x7100b0d1, - 0x92c0b101, - 0xb1017100, - 0x7000a0d1, - 0xc030a0d1, - 0xc0409760, - 0xb0f19780, - 0x7100b0c1, - 0xa0c1b0f1, - 0xa0037276, - 0x7000a002, - 0xb016b006, - 0xb014b004, - 0xb012b002, - 0x78628400, - 0x81430420, - 0x2a733983, - 0xc1f29473, - 0x31621832, - 0x31511021, - 0x00200012, - 0x10309400, - 0x39301610, - 0x417f2210, - 0x31501220, - 0x31801003, - 0x93501670, - 0x12041202, - 0x41912273, - 0x97c08430, - 0x1a8287d2, - 0x97c08450, - 0x1a8487d4, - 0x22636193, - 0x8440419e, - 0x87d097c0, - 0x14021a80, - 0x97c08460, - 0x1a8087d0, - 0x61aa1404, - 0x78718440, - 0x97c00410, - 0x1a4287d2, - 0x78718460, - 0x97c00410, - 0x1a4487d4, - 0x31543152, - 0x06333963, - 0x38321613, - 0x31823834, - 0x31843982, - 0x95720042, - 0x90307810, - 0x78209050, - 0x90609040, - 0x8ae2b205, - 0x93028303, - 0xc00bc00c, - 0x31808140, - 0x39403980, - 0xc0f38141, - 0xc0140431, - 0xc0021441, - 0x69cc1412, - 0x847d3122, - 0x140dc010, - 0x142d312d, - 0x318e8ace, - 0x397e311e, - 0x31498ac9, - 0x39493979, - 0x109a3129, - 0x720d720c, - 0xb101720e, - 0x7100b0d1, - 0xa0d1b072, - 0xb06ea04e, - 0xb06cb011, - 0x7276978a, - 0xa764b764, - 0x9762c662, - 0xc088c04f, - 0x8ab166b0, - 0x45fa22f1, - 0x22f18ad1, - 0x626445fa, - 0xb0737100, - 0x80b7b760, - 0x46312207, - 0x8ab1a760, - 0x420b22f1, - 0x420b2237, - 0x80b0b113, - 0x46062230, - 0x22e16219, - 0x8090421e, - 0x421e2250, - 0x8210b0f5, - 0x41fa2220, - 0xb7649789, - 0xb0f6a764, - 0x978d61fa, - 0xa764b764, - 0x61fab0f6, - 0x22f08ad0, - 0x2237422a, - 0xb075422a, - 0x80b0b113, - 0x46242230, - 0x61fab087, - 0x42f322d1, - 0x22208090, - 0x66ae42f3, - 0x978f61fa, - 0xa0e3a0e0, - 0xa0c5a0c2, - 0xb0c1b0f1, - 0x7100a0c6, - 0xb0f19788, - 0x8961b88f, - 0x18018570, - 0x8a609551, - 0xa4888a71, - 0xc062a487, - 0x1c211801, - 0x14124e51, - 0x62524a4f, - 0x42521c01, - 0xb4874e51, - 0xb4886252, - 0xb041b061, - 0x22e08ad0, - 0x8210425a, - 0x45de2220, - 0xb04d7100, - 0xb04fb06d, - 0xb074b06f, - 0x8a73b201, - 0x70008552, - 0xb0737100, - 0x80b7b760, - 0x46832207, - 0x46992237, - 0x8ab1a760, - 0x427c22e1, - 0x22508090, - 0xb0f5427c, - 0x22208210, - 0x978d4264, - 0xa764b764, - 0x6264b0f6, - 0x42f322d1, - 0x22208090, - 0x66ae42f3, - 0x978f6264, - 0xa0e3a0e0, - 0xa0c5a0c2, - 0xb0c1b0f1, - 0x7100a0c6, - 0xb0f19788, - 0x8961b88f, - 0x31808570, - 0x18013d80, - 0x8a609551, - 0xa1828a71, - 0x978f6243, - 0xa0e3a0e0, - 0xa0c5a0c2, - 0xb0c1b0f1, - 0x7100a0c6, - 0xb0f19788, - 0x8961b88f, - 0x3d808570, - 0x95511801, - 0x8a918a80, - 0x6243b182, - 0x7000b0f2, - 0xb0f1b0f6, - 0xb113b110, - 0xb0f2b0f5, - 0x720d720c, - 0xb0e0720e, - 0x8ab2b0e3, - 0x42c122f2, - 0xb763b0c6, - 0x8ad062c4, - 0x42e422f0, - 0xa404b405, - 0xa429b428, - 0x3180caa0, - 0x0001caa1, - 0x94619451, - 0x31838ad3, - 0x84103983, - 0x39803180, - 0x00303183, - 0x84009410, - 0x39503150, - 0x39838ad3, - 0xc1f406f3, - 0x31841834, - 0x00403134, - 0xb0899400, - 0x42ee22e2, - 0x394a8aca, - 0x312a398a, - 0xb0c5978a, - 0xb763b0c6, - 0x22d28ab2, - 0xb0c242f2, - 0xb20f7000, - 0xa0e3a0e0, - 0xb764978e, - 0xb0f6a764, - 0xb113b110, - 0x22f08210, - 0xb0f542fc, - 0xa0048002, - 0xa001a006, - 0x72047203, - 0x67a8c050, - 0xb7647100, - 0xb0c5b0f6, - 0x7100a20f, - 0xa0c5b0f5, - 0x90307810, - 0x78209002, - 0x90609040, - 0xa20fb072, - 0x978a66b0, - 0xb0f6a764, - 0x120061f3, - 0xc06091b0, - 0x7a3067a8, - 0xc10095a0, - 0xc622c241, - 0x6e236f13, - 0x16121611, - 0xb0f86b26, - 0xa0c16564, - 0xb0d7b107, - 0x9760c070, - 0x9780c070, - 0x7100b107, - 0x7100b107, - 0xb107a0d7, - 0xc1071206, - 0xc00d78a8, - 0x31131063, - 0x677e1483, - 0x1c671616, - 0xc02f473e, - 0x78a97898, - 0xb04f120e, - 0x1206b06f, - 0x67a01060, - 0x31131013, - 0x67891493, - 0x31131063, - 0x677e1483, - 0x1c671616, - 0x0a1e474c, - 0x435f1e1e, - 0x78a97898, - 0x78a86361, - 0x162f7899, - 0x1e008150, - 0x3930434b, - 0x1cf01620, - 0x4f4b436a, - 0x10601206, - 0x101367a0, - 0x14933113, - 0x16166789, - 0x476b1c67, - 0x72036798, - 0x73057204, - 0xa0047306, - 0xc7c0a002, - 0x607f9010, - 0xb0c1b0f1, - 0xb0f17100, - 0x87f1a0c1, - 0x6e318802, - 0x6e321613, - 0x6d317000, - 0x95e16d31, - 0x6d311613, - 0x95f16d31, - 0x1efdb5b0, - 0x85d04b96, - 0x91900610, - 0x7000161d, - 0xb5b0c0f0, - 0x85d10a11, - 0x91910611, - 0x70006b99, - 0x06311001, - 0x39203121, - 0x12f10010, - 0x70001801, - 0x88409850, - 0x47a92200, - 0x7000b830 -}; + { + 0x2fcf6054, + 0x030c0f9d, + 0x070c680a, + 0xff00003f, + 0x07c0d0d0, + 0x130007e0, + 0x50433221, + 0x10037162, + 0x53403122, + 0x00017261, + 0x01000010, + 0x00021000, + 0x02000020, + 0x00042000, + 0x04000040, + 0x00084000, + 0x08000080, + 0x00018000, + 0x00200018, + 0x00200003, + 0x00290011, + 0x0029000a, + 0x00320003, + 0x00320018, + 0x003b000a, + 0x003b0011, + 0x00070003, + 0x00003d1f, + 0x04000000, + 0x0000000f, + 0x000b0387, + 0x004340f4, + 0x80828000, + 0x00000670, + 0x0510091e, + 0x00050054, + 0x3e100200, + 0x00000061, + 0x3030002f, + 0x0000027f, + 0x00000000, + 0x0000aa00, + 0x72487220, + 0x7303a32d, + 0x72037305, + 0x73067304, + 0x73767204, + 0xc7c07276, + 0x00018001, + 0x90109001, + 0x90010801, + 0x720d720c, + 0xb0c0720e, + 0xb0f07100, + 0x7218a0c0, + 0x10208132, + 0x06703952, + 0x16300020, + 0x14011101, + 0x60896c01, + 0x60f0608c, + 0x6089631d, + 0x60896089, + 0x1210608a, + 0x730f7220, + 0x73117310, + 0x00108181, + 0xb0709180, + 0x607f6069, + 0x607f6400, + 0x67a8c030, + 0xc282c341, + 0x1820c470, + 0x6e236f13, + 0x16121611, + 0x78306892, + 0x78409ab0, + 0x78509ac0, + 0x83009ad0, + 0xc4829ae0, + 0x1820c5a0, + 0x120340a7, + 0x16126e23, + 0x607f68a4, + 0x94908160, + 0x39808140, + 0x10012a70, + 0x84321611, + 0xc0f38444, + 0xc200c0f5, + 0x40cc1c01, + 0x1c10c100, + 0x4cc440c2, + 0x18031013, + 0x1a131830, + 0x39121a10, + 0x60cc68bf, + 0x60cc13f3, + 0x101513f3, + 0x1850c100, + 0x1a101a15, + 0x68ca3914, + 0x7100b0d8, + 0xa0d8b108, + 0xb480b200, + 0xb013b003, + 0xb012b002, + 0xb0d07229, + 0xb1007100, + 0x92908140, + 0xb1007100, + 0x22f08140, + 0x13f044dc, + 0x40e81c03, + 0x94929293, + 0xb1007100, + 0x94949295, + 0x71006536, + 0xb0d0b100, + 0x7000a480, + 0x7310730f, + 0x67a8c040, + 0x91c0c000, + 0xc0b7c136, + 0xc009c008, + 0xc00bc00a, + 0xc00dc00c, + 0xc10e788f, + 0x9760c030, + 0x9780c000, + 0xb48464a8, + 0x10acc009, + 0x10f010bd, + 0x1e003980, + 0x81e0411c, + 0x41122210, + 0x611581a0, + 0x061010f0, + 0x6523391f, + 0x654c653c, + 0x1ce91619, + 0x6106450d, + 0x654c653c, + 0x1ce91619, + 0x6556451c, + 0x1081607f, + 0x6f121471, + 0x41292200, + 0x10233982, + 0x311a0613, + 0x1023003a, + 0x06133913, + 0x003b311b, + 0x39481028, + 0x700006f8, + 0x652381a0, + 0x1ce91619, + 0x70004536, + 0x14921062, + 0x10c16f23, + 0x41440431, + 0x61451210, + 0x10d113f0, + 0x414a0431, + 0x614b1211, + 0x700013f1, + 0xb10192c1, + 0x7100b0d1, + 0x92c0b101, + 0xb1017100, + 0x7000a0d1, + 0xc030a0d1, + 0xc0409760, + 0xb0f19780, + 0x7100b0c1, + 0xa0c1b0f1, + 0xa0037276, + 0x7000a002, + 0xb016b006, + 0xb014b004, + 0xb012b002, + 0x78628400, + 0x81430420, + 0x2a733983, + 0xc1f29473, + 0x31621832, + 0x31511021, + 0x00200012, + 0x10309400, + 0x39301610, + 0x417f2210, + 0x31501220, + 0x31801003, + 0x93501670, + 0x12041202, + 0x41912273, + 0x97c08430, + 0x1a8287d2, + 0x97c08450, + 0x1a8487d4, + 0x22636193, + 0x8440419e, + 0x87d097c0, + 0x14021a80, + 0x97c08460, + 0x1a8087d0, + 0x61aa1404, + 0x78718440, + 0x97c00410, + 0x1a4287d2, + 0x78718460, + 0x97c00410, + 0x1a4487d4, + 0x31543152, + 0x06333963, + 0x38321613, + 0x31823834, + 0x31843982, + 0x95720042, + 0x90307810, + 0x78209050, + 0x90609040, + 0x8ae2b205, + 0x93028303, + 0xc00bc00c, + 0x31808140, + 0x39403980, + 0xc0f38141, + 0xc0140431, + 0xc0021441, + 0x69cc1412, + 0x847d3122, + 0x140dc010, + 0x142d312d, + 0x318e8ace, + 0x397e311e, + 0x31498ac9, + 0x39493979, + 0x109a3129, + 0x720d720c, + 0xb101720e, + 0x7100b0d1, + 0xa0d1b072, + 0xb06ea04e, + 0xb06cb011, + 0x7276978a, + 0xa764b764, + 0x9762c662, + 0xc088c04f, + 0x8ab166b0, + 0x45fa22f1, + 0x22f18ad1, + 0x626445fa, + 0xb0737100, + 0x80b7b760, + 0x46312207, + 0x8ab1a760, + 0x420b22f1, + 0x420b2237, + 0x80b0b113, + 0x46062230, + 0x22e16219, + 0x8090421e, + 0x421e2250, + 0x8210b0f5, + 0x41fa2220, + 0xb7649789, + 0xb0f6a764, + 0x978d61fa, + 0xa764b764, + 0x61fab0f6, + 0x22f08ad0, + 0x2237422a, + 0xb075422a, + 0x80b0b113, + 0x46242230, + 0x61fab087, + 0x42f322d1, + 0x22208090, + 0x66ae42f3, + 0x978f61fa, + 0xa0e3a0e0, + 0xa0c5a0c2, + 0xb0c1b0f1, + 0x7100a0c6, + 0xb0f19788, + 0x8961b88f, + 0x18018570, + 0x8a609551, + 0xa4888a71, + 0xc062a487, + 0x1c211801, + 0x14124e51, + 0x62524a4f, + 0x42521c01, + 0xb4874e51, + 0xb4886252, + 0xb041b061, + 0x22e08ad0, + 0x8210425a, + 0x45de2220, + 0xb04d7100, + 0xb04fb06d, + 0xb074b06f, + 0x8a73b201, + 0x70008552, + 0xb0737100, + 0x80b7b760, + 0x46832207, + 0x46992237, + 0x8ab1a760, + 0x427c22e1, + 0x22508090, + 0xb0f5427c, + 0x22208210, + 0x978d4264, + 0xa764b764, + 0x6264b0f6, + 0x42f322d1, + 0x22208090, + 0x66ae42f3, + 0x978f6264, + 0xa0e3a0e0, + 0xa0c5a0c2, + 0xb0c1b0f1, + 0x7100a0c6, + 0xb0f19788, + 0x8961b88f, + 0x31808570, + 0x18013d80, + 0x8a609551, + 0xa1828a71, + 0x978f6243, + 0xa0e3a0e0, + 0xa0c5a0c2, + 0xb0c1b0f1, + 0x7100a0c6, + 0xb0f19788, + 0x8961b88f, + 0x3d808570, + 0x95511801, + 0x8a918a80, + 0x6243b182, + 0x7000b0f2, + 0xb0f1b0f6, + 0xb113b110, + 0xb0f2b0f5, + 0x720d720c, + 0xb0e0720e, + 0x8ab2b0e3, + 0x42c122f2, + 0xb763b0c6, + 0x8ad062c4, + 0x42e422f0, + 0xa404b405, + 0xa429b428, + 0x3180caa0, + 0x0001caa1, + 0x94619451, + 0x31838ad3, + 0x84103983, + 0x39803180, + 0x00303183, + 0x84009410, + 0x39503150, + 0x39838ad3, + 0xc1f406f3, + 0x31841834, + 0x00403134, + 0xb0899400, + 0x42ee22e2, + 0x394a8aca, + 0x312a398a, + 0xb0c5978a, + 0xb763b0c6, + 0x22d28ab2, + 0xb0c242f2, + 0xb20f7000, + 0xa0e3a0e0, + 0xb764978e, + 0xb0f6a764, + 0xb113b110, + 0x22f08210, + 0xb0f542fc, + 0xa0048002, + 0xa001a006, + 0x72047203, + 0x67a8c050, + 0xb7647100, + 0xb0c5b0f6, + 0x7100a20f, + 0xa0c5b0f5, + 0x90307810, + 0x78209002, + 0x90609040, + 0xa20fb072, + 0x978a66b0, + 0xb0f6a764, + 0x120061f3, + 0xc06091b0, + 0x7a3067a8, + 0xc10095a0, + 0xc622c241, + 0x6e236f13, + 0x16121611, + 0xb0f86b26, + 0xa0c16564, + 0xb0d7b107, + 0x9760c070, + 0x9780c070, + 0x7100b107, + 0x7100b107, + 0xb107a0d7, + 0xc1071206, + 0xc00d78a8, + 0x31131063, + 0x677e1483, + 0x1c671616, + 0xc02f473e, + 0x78a97898, + 0xb04f120e, + 0x1206b06f, + 0x67a01060, + 0x31131013, + 0x67891493, + 0x31131063, + 0x677e1483, + 0x1c671616, + 0x0a1e474c, + 0x435f1e1e, + 0x78a97898, + 0x78a86361, + 0x162f7899, + 0x1e008150, + 0x3930434b, + 0x1cf01620, + 0x4f4b436a, + 0x10601206, + 0x101367a0, + 0x14933113, + 0x16166789, + 0x476b1c67, + 0x72036798, + 0x73057204, + 0xa0047306, + 0xc7c0a002, + 0x607f9010, + 0xb0c1b0f1, + 0xb0f17100, + 0x87f1a0c1, + 0x6e318802, + 0x6e321613, + 0x6d317000, + 0x95e16d31, + 0x6d311613, + 0x95f16d31, + 0x1efdb5b0, + 0x85d04b96, + 0x91900610, + 0x7000161d, + 0xb5b0c0f0, + 0x85d10a11, + 0x91910611, + 0x70006b99, + 0x06311001, + 0x39203121, + 0x12f10010, + 0x70001801, + 0x88409850, + 0x47a92200, + 0x7000b830}; PATCH_FUN_SPEC void rf_patch_mce_genfsk_fec_cc1101(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genook.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genook.h index 2921b2a..9c8c42d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genook.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_genook.h @@ -1,529 +1,528 @@ /****************************************************************************** -* Filename: rf_patch_mce_genook.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 Generic OOK -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_mce_genook.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 Generic OOK + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_MCE_GENOOK_H #define _RF_PATCH_MCE_GENOOK_H -#include #include "../inc/hw_types.h" +#include #ifndef MCE_PATCH_TYPE - #define MCE_PATCH_TYPE static const uint32_t +#define MCE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_MCERAM_BASE - #define RFC_MCERAM_BASE 0x21008000 +#define RFC_MCERAM_BASE 0x21008000 #endif #ifndef MCE_PATCH_MODE - #define MCE_PATCH_MODE 0 +#define MCE_PATCH_MODE 0 #endif MCE_PATCH_TYPE patchGenookMce[463] = -{ - 0x00006030, - 0x01952fcf, - 0x7fff0001, - 0x030c003f, - 0x070c680a, - 0x00010000, - 0xaaaa000f, - 0x00fc00aa, - 0x00170003, - 0x0000001f, - 0x04000000, - 0x0000000f, - 0x00020387, - 0x00434074, - 0x20028000, - 0x000006f0, - 0x0500091e, - 0x00000054, - 0x50140000, - 0x00000050, - 0x7f30000f, - 0x0000007f, - 0x00000000, - 0x00000000, - 0x72487220, - 0x73057303, - 0x73047203, - 0x72047306, - 0x72767376, - 0x8001c7c0, - 0x90010001, - 0x08019010, - 0x720c9001, - 0x720e720d, - 0x7100b0c0, - 0xa0c0b0f0, - 0x81327218, - 0x9862d030, - 0x10206798, - 0x1e000670, - 0x1e104074, - 0x1e204075, - 0x3982405f, - 0x163206f2, - 0x14211101, - 0x61826c01, - 0x63186182, - 0x3982632e, - 0x16323942, - 0x14211101, - 0x60e36c01, - 0x610d60e3, - 0x606b1220, - 0x72201210, - 0x7310730f, - 0x81817311, - 0x91800010, - 0x6044b070, - 0xc101606a, - 0xc470c282, - 0x6f131820, - 0x16116e23, - 0x68791612, - 0x9ab07870, - 0x9ac07880, - 0x9ad07890, - 0x981078b0, - 0xc5a0c482, - 0x408e1820, - 0x6e231203, - 0x688b1612, - 0x9ae078a0, - 0x8160606a, - 0x81409490, - 0x2a703980, - 0x16111001, - 0x84448432, - 0xc0f5c0f3, - 0x1c01c200, - 0xc10040b5, - 0x40ab1c10, - 0x10134cad, - 0x18301803, - 0x1a101a13, - 0x68a83912, - 0x13f360b5, - 0x13f360b5, - 0xc1001015, - 0x1a151850, - 0x39141a10, - 0xb0d868b3, - 0xb1087100, - 0xb200a0d8, - 0xb012b002, - 0x22168216, - 0x814640bc, - 0x06f63d46, - 0x81408165, - 0x105106f0, - 0x65570611, - 0x68c53d15, - 0x22f08140, - 0x1a1644bf, - 0x8ae14cc2, - 0x9861d040, - 0x13f06798, - 0x40dc1c03, - 0x1021c0f0, - 0x65570611, - 0x68d73d12, - 0x1041c0f0, - 0x65570611, - 0x68dd3d14, - 0x72207000, - 0x7310730f, - 0x91c0c000, - 0xb0c1b0f1, - 0x9760c050, - 0x9780c010, - 0x6491c008, - 0x39838ad3, - 0x06133953, - 0x221081e0, - 0x81a14104, - 0x10170831, - 0x81306557, - 0x39403980, - 0x45031e10, - 0x0a111071, - 0x60f46557, - 0x65571201, - 0xa0c1b204, - 0xa0c3b0f1, - 0x6798c050, - 0x7220606a, - 0x7310730f, - 0x91c0c000, - 0xb0c1b0f1, - 0x9760c050, - 0x9780c010, - 0x8216b200, - 0x41192216, - 0xb012b002, - 0xc030c008, - 0x10a178ca, - 0x65570611, - 0x6921391a, - 0x78dac0f0, - 0x061110a1, - 0x391a6557, - 0xc0706928, - 0x10a178ea, - 0x65570611, - 0x692f391a, - 0x78fac090, - 0x061110a1, - 0x391a6557, - 0x8ad36936, - 0x39533983, - 0x81e00613, - 0x414c2210, - 0x0831c011, - 0x81a16557, - 0x65576793, - 0x0831c001, - 0x613f6557, - 0x6557c011, - 0x6557c001, - 0xa0c1b204, - 0xa0c3b0f1, - 0x6798c060, - 0xc029606a, - 0x455d2208, - 0x41732201, - 0x2201616c, - 0x8aef4573, - 0x416c22ff, - 0x31116578, - 0x39119201, - 0x80fe1018, - 0x456bc019, - 0x6173c029, - 0x7100b0f1, - 0x92013111, - 0x10183911, - 0xb0f1c019, - 0x1a197100, - 0x70004573, - 0x785f10f9, - 0x100004f9, - 0x10001000, - 0x1a191000, - 0x7000457b, - 0xc0706750, - 0x847d6798, - 0x140dc010, - 0x142d312d, - 0x318e8ace, - 0x397e311e, - 0x31498ac9, - 0x39493979, - 0x10903129, - 0x72769780, - 0xa764b764, - 0x9762c662, - 0xb012b002, - 0x986be080, - 0x6798987f, - 0x6699b485, - 0x8ab1a182, - 0x45aa22f1, - 0x22f18ad1, - 0x61df45aa, - 0x80b77100, - 0x45fd2207, - 0x22b08090, - 0x105441b6, - 0x662d858c, - 0x61aa668e, - 0x22f18ab1, - 0x223741c0, - 0xb11341c0, - 0x223080b0, - 0x61ce45bb, - 0x41d322e1, - 0x22508090, - 0xb0f541d3, - 0x22108210, - 0x978941aa, - 0xa764b764, - 0x61aab0f6, - 0xb764978d, - 0xb0f6a764, - 0x8ad061aa, - 0x42da22f0, - 0x42da2237, - 0xb113b075, - 0x223080b0, - 0xb08745d9, - 0x710061aa, - 0x220780b7, - 0x223745fd, - 0x809045fc, - 0x41ee22b0, - 0x858c1054, - 0x668e662d, - 0x8ab161df, - 0x41df22e1, - 0x22508090, - 0xb0f541df, - 0x22108210, - 0x978d41df, - 0xa764b764, - 0x61dfb0f6, - 0xb110b182, - 0xb113a0e0, - 0xb074a0e3, - 0xa044b201, - 0x986ad090, - 0x10806798, - 0x1c0a1610, - 0x1cfa4a0e, - 0x66704e0e, - 0xc00ec00f, - 0x80907100, - 0x44442200, - 0x1054858c, - 0x668e662d, - 0x39808130, - 0x1e1006f0, - 0x667a461f, - 0x66646220, - 0x1e008150, - 0x1a104210, - 0x4e101cf0, - 0x62106228, - 0xb0f6a0c6, - 0xb0fba0cb, - 0xb8846306, - 0x881188c2, - 0x1e010631, - 0x1e21424a, - 0x1e31423c, - 0x10564243, - 0x39161426, - 0x624b1065, - 0x31261056, - 0x14261856, - 0x10653926, - 0x1056624b, - 0x18563136, - 0x39361426, - 0x624b1065, - 0x82121026, - 0x1c263922, - 0x18624e59, - 0x1c12c101, - 0x12014e57, - 0x31211821, - 0xcc016261, - 0x18266261, - 0x1c16c101, - 0x10614e60, - 0x62613121, - 0x9581c401, - 0x7000b0fb, - 0x466f1c8a, - 0x39208210, - 0x4e6c1c04, - 0x626dc001, - 0x9191c011, - 0x7000161f, - 0x39208210, - 0x4e761c04, - 0x6277c001, - 0x9191c011, - 0x7000c01f, - 0x468d1c8a, - 0x31808580, - 0x10013d80, - 0x10171870, - 0x468c1e1e, - 0x39703980, - 0x39818ad1, - 0x08103951, - 0x161f9190, - 0x70000a1e, - 0x10c08581, - 0x22700810, - 0x120a4295, - 0x1cba6298, - 0x161a4293, - 0xb0fb7000, - 0xb0f1b0f6, - 0xb113b110, - 0xb0f2b0f5, - 0x720d720c, - 0xb0cb720e, - 0xb0e3b0e0, - 0x22f28ab2, - 0xb0c642ac, - 0x62afb763, - 0x22f08ad0, - 0xb40542cf, - 0xa428a404, - 0xcaa0a429, - 0xcaa13180, - 0x94510001, - 0x8ad39461, - 0x39833183, - 0x31808410, - 0x31833980, - 0x94100030, - 0x31508400, - 0x8ad33950, - 0x06f33983, - 0x1834c1f4, - 0x31343184, - 0x94000040, - 0x22e2b089, - 0x8aca42d9, - 0x398a394a, - 0x978a312a, - 0xb0c6b0c5, - 0x7000b763, - 0xa0e0b20f, - 0xa0cba0e3, - 0xb764978e, - 0xb0f6a764, - 0xb113b110, - 0x8210b0fb, - 0x42e52200, - 0x8002b0f5, - 0xa006a004, - 0x7203a001, - 0xc0a07204, - 0x71006798, - 0xb0f6b764, - 0xa20fb0c5, - 0xb0f57100, - 0x7820a0c5, - 0x90029030, - 0x90407830, - 0xb0729060, - 0x6699a20f, - 0xa764978a, - 0x61a3b0f6, - 0x8180b88c, - 0x392489a4, - 0x00043184, - 0xc0b09184, - 0x73766798, - 0x72487276, - 0x72027206, - 0x73057204, - 0x606a7306, - 0xc0c06750, - 0xb0f86798, - 0xb0fbb0cb, - 0xb228b005, - 0xb0fb7100, - 0x22e08ad0, - 0x82104328, - 0x43202210, - 0x8580662d, - 0x0a103970, - 0x63206789, - 0xc0d06750, - 0xb0cb6798, - 0x120cb074, - 0x398e881e, - 0x433e1e0e, - 0x30e01210, - 0x71001a20, - 0x6b3b662d, - 0x8ad07100, - 0x434522e0, - 0x22108210, - 0x662d4336, - 0x0a113971, - 0x81549191, - 0x43361e04, - 0x1cc4161c, - 0x63364306, - 0x91b01200, - 0xb006b0f8, - 0xb004b016, - 0xb002b014, - 0x8400b012, - 0x04207862, - 0x39838143, - 0x94732a73, - 0x1832c1f2, - 0x10213162, - 0x00123151, - 0x94000020, - 0x90307820, - 0x78309050, - 0x90609040, - 0x8330c04b, - 0x06303930, - 0x43751e00, - 0x10b8300b, - 0x39181a1b, - 0x108fc00a, - 0xa203a204, - 0x22408330, - 0x165f4382, - 0x6386b204, - 0x43862230, - 0xb203163f, - 0xb072b205, - 0x22007000, - 0xb005478d, - 0x80006392, - 0x43922250, - 0xa005b240, - 0x82a27000, - 0x06123972, - 0x70000821, - 0x88409850, - 0x47992200, - 0x7000b830 -}; + { + 0x00006030, + 0x01952fcf, + 0x7fff0001, + 0x030c003f, + 0x070c680a, + 0x00010000, + 0xaaaa000f, + 0x00fc00aa, + 0x00170003, + 0x0000001f, + 0x04000000, + 0x0000000f, + 0x00020387, + 0x00434074, + 0x20028000, + 0x000006f0, + 0x0500091e, + 0x00000054, + 0x50140000, + 0x00000050, + 0x7f30000f, + 0x0000007f, + 0x00000000, + 0x00000000, + 0x72487220, + 0x73057303, + 0x73047203, + 0x72047306, + 0x72767376, + 0x8001c7c0, + 0x90010001, + 0x08019010, + 0x720c9001, + 0x720e720d, + 0x7100b0c0, + 0xa0c0b0f0, + 0x81327218, + 0x9862d030, + 0x10206798, + 0x1e000670, + 0x1e104074, + 0x1e204075, + 0x3982405f, + 0x163206f2, + 0x14211101, + 0x61826c01, + 0x63186182, + 0x3982632e, + 0x16323942, + 0x14211101, + 0x60e36c01, + 0x610d60e3, + 0x606b1220, + 0x72201210, + 0x7310730f, + 0x81817311, + 0x91800010, + 0x6044b070, + 0xc101606a, + 0xc470c282, + 0x6f131820, + 0x16116e23, + 0x68791612, + 0x9ab07870, + 0x9ac07880, + 0x9ad07890, + 0x981078b0, + 0xc5a0c482, + 0x408e1820, + 0x6e231203, + 0x688b1612, + 0x9ae078a0, + 0x8160606a, + 0x81409490, + 0x2a703980, + 0x16111001, + 0x84448432, + 0xc0f5c0f3, + 0x1c01c200, + 0xc10040b5, + 0x40ab1c10, + 0x10134cad, + 0x18301803, + 0x1a101a13, + 0x68a83912, + 0x13f360b5, + 0x13f360b5, + 0xc1001015, + 0x1a151850, + 0x39141a10, + 0xb0d868b3, + 0xb1087100, + 0xb200a0d8, + 0xb012b002, + 0x22168216, + 0x814640bc, + 0x06f63d46, + 0x81408165, + 0x105106f0, + 0x65570611, + 0x68c53d15, + 0x22f08140, + 0x1a1644bf, + 0x8ae14cc2, + 0x9861d040, + 0x13f06798, + 0x40dc1c03, + 0x1021c0f0, + 0x65570611, + 0x68d73d12, + 0x1041c0f0, + 0x65570611, + 0x68dd3d14, + 0x72207000, + 0x7310730f, + 0x91c0c000, + 0xb0c1b0f1, + 0x9760c050, + 0x9780c010, + 0x6491c008, + 0x39838ad3, + 0x06133953, + 0x221081e0, + 0x81a14104, + 0x10170831, + 0x81306557, + 0x39403980, + 0x45031e10, + 0x0a111071, + 0x60f46557, + 0x65571201, + 0xa0c1b204, + 0xa0c3b0f1, + 0x6798c050, + 0x7220606a, + 0x7310730f, + 0x91c0c000, + 0xb0c1b0f1, + 0x9760c050, + 0x9780c010, + 0x8216b200, + 0x41192216, + 0xb012b002, + 0xc030c008, + 0x10a178ca, + 0x65570611, + 0x6921391a, + 0x78dac0f0, + 0x061110a1, + 0x391a6557, + 0xc0706928, + 0x10a178ea, + 0x65570611, + 0x692f391a, + 0x78fac090, + 0x061110a1, + 0x391a6557, + 0x8ad36936, + 0x39533983, + 0x81e00613, + 0x414c2210, + 0x0831c011, + 0x81a16557, + 0x65576793, + 0x0831c001, + 0x613f6557, + 0x6557c011, + 0x6557c001, + 0xa0c1b204, + 0xa0c3b0f1, + 0x6798c060, + 0xc029606a, + 0x455d2208, + 0x41732201, + 0x2201616c, + 0x8aef4573, + 0x416c22ff, + 0x31116578, + 0x39119201, + 0x80fe1018, + 0x456bc019, + 0x6173c029, + 0x7100b0f1, + 0x92013111, + 0x10183911, + 0xb0f1c019, + 0x1a197100, + 0x70004573, + 0x785f10f9, + 0x100004f9, + 0x10001000, + 0x1a191000, + 0x7000457b, + 0xc0706750, + 0x847d6798, + 0x140dc010, + 0x142d312d, + 0x318e8ace, + 0x397e311e, + 0x31498ac9, + 0x39493979, + 0x10903129, + 0x72769780, + 0xa764b764, + 0x9762c662, + 0xb012b002, + 0x986be080, + 0x6798987f, + 0x6699b485, + 0x8ab1a182, + 0x45aa22f1, + 0x22f18ad1, + 0x61df45aa, + 0x80b77100, + 0x45fd2207, + 0x22b08090, + 0x105441b6, + 0x662d858c, + 0x61aa668e, + 0x22f18ab1, + 0x223741c0, + 0xb11341c0, + 0x223080b0, + 0x61ce45bb, + 0x41d322e1, + 0x22508090, + 0xb0f541d3, + 0x22108210, + 0x978941aa, + 0xa764b764, + 0x61aab0f6, + 0xb764978d, + 0xb0f6a764, + 0x8ad061aa, + 0x42da22f0, + 0x42da2237, + 0xb113b075, + 0x223080b0, + 0xb08745d9, + 0x710061aa, + 0x220780b7, + 0x223745fd, + 0x809045fc, + 0x41ee22b0, + 0x858c1054, + 0x668e662d, + 0x8ab161df, + 0x41df22e1, + 0x22508090, + 0xb0f541df, + 0x22108210, + 0x978d41df, + 0xa764b764, + 0x61dfb0f6, + 0xb110b182, + 0xb113a0e0, + 0xb074a0e3, + 0xa044b201, + 0x986ad090, + 0x10806798, + 0x1c0a1610, + 0x1cfa4a0e, + 0x66704e0e, + 0xc00ec00f, + 0x80907100, + 0x44442200, + 0x1054858c, + 0x668e662d, + 0x39808130, + 0x1e1006f0, + 0x667a461f, + 0x66646220, + 0x1e008150, + 0x1a104210, + 0x4e101cf0, + 0x62106228, + 0xb0f6a0c6, + 0xb0fba0cb, + 0xb8846306, + 0x881188c2, + 0x1e010631, + 0x1e21424a, + 0x1e31423c, + 0x10564243, + 0x39161426, + 0x624b1065, + 0x31261056, + 0x14261856, + 0x10653926, + 0x1056624b, + 0x18563136, + 0x39361426, + 0x624b1065, + 0x82121026, + 0x1c263922, + 0x18624e59, + 0x1c12c101, + 0x12014e57, + 0x31211821, + 0xcc016261, + 0x18266261, + 0x1c16c101, + 0x10614e60, + 0x62613121, + 0x9581c401, + 0x7000b0fb, + 0x466f1c8a, + 0x39208210, + 0x4e6c1c04, + 0x626dc001, + 0x9191c011, + 0x7000161f, + 0x39208210, + 0x4e761c04, + 0x6277c001, + 0x9191c011, + 0x7000c01f, + 0x468d1c8a, + 0x31808580, + 0x10013d80, + 0x10171870, + 0x468c1e1e, + 0x39703980, + 0x39818ad1, + 0x08103951, + 0x161f9190, + 0x70000a1e, + 0x10c08581, + 0x22700810, + 0x120a4295, + 0x1cba6298, + 0x161a4293, + 0xb0fb7000, + 0xb0f1b0f6, + 0xb113b110, + 0xb0f2b0f5, + 0x720d720c, + 0xb0cb720e, + 0xb0e3b0e0, + 0x22f28ab2, + 0xb0c642ac, + 0x62afb763, + 0x22f08ad0, + 0xb40542cf, + 0xa428a404, + 0xcaa0a429, + 0xcaa13180, + 0x94510001, + 0x8ad39461, + 0x39833183, + 0x31808410, + 0x31833980, + 0x94100030, + 0x31508400, + 0x8ad33950, + 0x06f33983, + 0x1834c1f4, + 0x31343184, + 0x94000040, + 0x22e2b089, + 0x8aca42d9, + 0x398a394a, + 0x978a312a, + 0xb0c6b0c5, + 0x7000b763, + 0xa0e0b20f, + 0xa0cba0e3, + 0xb764978e, + 0xb0f6a764, + 0xb113b110, + 0x8210b0fb, + 0x42e52200, + 0x8002b0f5, + 0xa006a004, + 0x7203a001, + 0xc0a07204, + 0x71006798, + 0xb0f6b764, + 0xa20fb0c5, + 0xb0f57100, + 0x7820a0c5, + 0x90029030, + 0x90407830, + 0xb0729060, + 0x6699a20f, + 0xa764978a, + 0x61a3b0f6, + 0x8180b88c, + 0x392489a4, + 0x00043184, + 0xc0b09184, + 0x73766798, + 0x72487276, + 0x72027206, + 0x73057204, + 0x606a7306, + 0xc0c06750, + 0xb0f86798, + 0xb0fbb0cb, + 0xb228b005, + 0xb0fb7100, + 0x22e08ad0, + 0x82104328, + 0x43202210, + 0x8580662d, + 0x0a103970, + 0x63206789, + 0xc0d06750, + 0xb0cb6798, + 0x120cb074, + 0x398e881e, + 0x433e1e0e, + 0x30e01210, + 0x71001a20, + 0x6b3b662d, + 0x8ad07100, + 0x434522e0, + 0x22108210, + 0x662d4336, + 0x0a113971, + 0x81549191, + 0x43361e04, + 0x1cc4161c, + 0x63364306, + 0x91b01200, + 0xb006b0f8, + 0xb004b016, + 0xb002b014, + 0x8400b012, + 0x04207862, + 0x39838143, + 0x94732a73, + 0x1832c1f2, + 0x10213162, + 0x00123151, + 0x94000020, + 0x90307820, + 0x78309050, + 0x90609040, + 0x8330c04b, + 0x06303930, + 0x43751e00, + 0x10b8300b, + 0x39181a1b, + 0x108fc00a, + 0xa203a204, + 0x22408330, + 0x165f4382, + 0x6386b204, + 0x43862230, + 0xb203163f, + 0xb072b205, + 0x22007000, + 0xb005478d, + 0x80006392, + 0x43922250, + 0xa005b240, + 0x82a27000, + 0x06123972, + 0x70000821, + 0x88409850, + 0x47992200, + 0x7000b830}; PATCH_FUN_SPEC void rf_patch_mce_genook(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_ghs.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_ghs.h index 81d2000..e702fc1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_ghs.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_ghs.h @@ -1,367 +1,366 @@ /****************************************************************************** -* Filename: rf_patch_mce_ghs.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 Generic 4FSK up to 1.5Mbps -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_mce_ghs.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 Generic 4FSK up to 1.5Mbps + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_MCE_GHS_H #define _RF_PATCH_MCE_GHS_H -#include #include "../inc/hw_types.h" +#include #ifndef MCE_PATCH_TYPE - #define MCE_PATCH_TYPE static const uint32_t +#define MCE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_MCERAM_BASE - #define RFC_MCERAM_BASE 0x21008000 +#define RFC_MCERAM_BASE 0x21008000 #endif #ifndef MCE_PATCH_MODE - #define MCE_PATCH_MODE 0 +#define MCE_PATCH_MODE 0 #endif MCE_PATCH_TYPE patchGhsMce[301] = -{ - 0x2fcf603c, - 0x00f03f9d, - 0x0f30003d, - 0x003f0ff0, - 0x0000ff00, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00070003, - 0x31fd31fd, - 0x04000000, - 0x001d000f, - 0x000b0387, - 0x004340f4, - 0x80828000, - 0x00000f90, - 0x0510091e, - 0x00050054, - 0x11010000, - 0x0000003c, - 0x3030002f, - 0x0000027f, - 0xd3910000, - 0x0000193d, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x72487220, - 0x7303a32d, - 0x72037305, - 0x73067304, - 0x73767204, - 0xc7c07276, - 0x00018001, - 0x90109001, - 0x90010801, - 0x720d720c, - 0xb0c0720e, - 0xb0f07100, - 0x7218a0c0, - 0x10208132, - 0x06703952, - 0x16300020, - 0x14011101, - 0x60796c01, - 0x60f4607c, - 0x607961da, - 0x60796079, - 0x6079607a, - 0x60f4607c, - 0x607961da, - 0x60796079, - 0x1210607a, - 0x730f7220, - 0x73117310, - 0x00108181, - 0xb0709180, - 0x606f6051, - 0x606f6646, - 0x663cc030, - 0xc282c141, - 0x1820c470, - 0x6e236f13, - 0x16121611, - 0x78306882, - 0x78409ac0, - 0xc4829ad0, - 0x1820c5a0, - 0x12034093, - 0x16126e23, - 0x83606890, - 0x606f97e0, - 0x94908160, - 0x39808140, - 0x10012a70, - 0x84321611, - 0xc0f38444, - 0xc200c0f5, - 0x40ba1c01, - 0x1c10c100, - 0x4cb240b0, - 0x18031013, - 0x1a131830, - 0x39121a10, - 0x60ba68ad, - 0x60ba13f3, - 0x101513f3, - 0x1850c100, - 0x1a101a15, - 0x68b83914, - 0x7100b0d8, - 0xa0d8b108, - 0xb760b200, - 0x97808ac0, - 0xb0c1b0f1, - 0xb0f17100, - 0x7276a0c1, - 0xb003b480, - 0xb002b013, - 0x7229b012, - 0x7100b0d0, - 0x8140b100, - 0x71009290, - 0x8140b100, - 0x44d322f0, - 0x1c0313f0, - 0x929340df, - 0x71009492, - 0x9295b100, - 0x71009494, - 0xb0d0b100, - 0x7000a480, - 0xc030a0d1, - 0xc0409760, - 0xb0f19780, - 0x7100b0c1, - 0xa0c1b0f1, - 0xa0037276, - 0x7000a002, - 0x7310730f, - 0x663cc040, - 0x92f0c000, - 0x92a08ad0, - 0x91c0c110, - 0xb2f06496, - 0x92a082b0, - 0xb0f3b483, - 0x7100b0c3, - 0x64e6a0c3, - 0xb006606f, - 0xb004b016, - 0xb002b014, - 0x8400b012, - 0x04207872, - 0x39838143, - 0x94732a73, - 0x1832c1f2, - 0x10213162, - 0x00123151, - 0x94000020, - 0x16101030, - 0x22103930, - 0x12204124, - 0x10033150, - 0x16a03180, - 0x12029350, - 0x22731204, - 0x84304136, - 0x87d297c0, - 0x84501a82, - 0x87d497c0, - 0x61381a84, - 0x41432263, - 0x97c08440, - 0x1a8087d0, - 0x84601402, - 0x87d097c0, - 0x14041a80, - 0x8440614f, - 0x04107881, - 0x87d297c0, - 0x84601a42, - 0x04107881, - 0x87d497c0, - 0x31521a44, - 0x39633154, - 0x16130633, - 0x38343832, - 0x39823182, - 0x00423184, - 0x78509572, - 0x78109360, - 0x90509030, - 0x90407820, - 0xb2059060, - 0x6965cb40, - 0x936087e0, - 0xa0c5b0f5, - 0x83038ae2, - 0xc00c9302, - 0x8140c00b, - 0x39803180, - 0x81413940, - 0x0431c0f3, - 0x1441c014, - 0x1412c002, - 0x31226979, - 0xb0d1b101, - 0xb0727100, - 0xa04ea0d1, - 0xb011b06e, - 0xa041b06c, - 0xa487a488, - 0x720d720c, - 0x7276720e, - 0xa764b764, - 0x9760c440, - 0xc020c062, - 0xc07e9780, - 0xb0e0c07f, - 0xb0c1b0f1, - 0xb0f5b0c5, - 0xb7607100, - 0xa0c5a0e0, - 0x220080b0, - 0x621345a2, - 0x7100b88f, - 0x978eb073, - 0xb201b074, - 0x85708961, - 0x95511801, - 0x8a718a60, - 0x1c211801, - 0x14124db9, - 0x61ba49b7, - 0x41ba1c01, - 0xb4874db9, - 0xb48861ba, - 0xb0f1b061, - 0xb0417100, - 0xb0f1978f, - 0xb04e7100, - 0x8a73b06e, - 0x70008552, - 0x8180b88c, - 0x392489a4, - 0x00043184, - 0xc0509184, - 0x7850663c, - 0x73769360, - 0x72487276, - 0x72027206, - 0x73057204, - 0x606f7306, - 0x91b01300, - 0xc060b32d, - 0xb0f8663c, - 0x78606509, - 0x12009360, - 0x97801a10, - 0x9760c380, - 0x9760c280, - 0xb0c6a0c1, - 0x22008090, - 0x81544451, - 0x41ec1e04, - 0x16943914, - 0xb0f69784, - 0xd0708552, - 0x663c9862, - 0x8a738a62, - 0x9862e080, - 0x663c9873, - 0x87818790, - 0x4a101c01, - 0x1ef11801, - 0x87814a0e, - 0x97811af1, - 0xb0f67100, - 0x978116f1, - 0x7100a205, - 0xa0c6b0f6, - 0x821d61c6, - 0x418b1e0d, - 0x9880c030, - 0x88a48893, - 0x31343133, - 0x422522fd, - 0x3d343d33, - 0x30d32afd, - 0x821230d4, - 0x163d622b, - 0x3cd43cd3, - 0x82121a3d, - 0x94e3622b, - 0xb05394f4, - 0xc030618b, - 0x88929880, - 0x3d323132, - 0x313388a3, - 0xe0903d33, - 0x98739862, - 0x7000663c, - 0x88409850, - 0x463d2200, - 0x7000b830, - 0x22f08150, - 0xb0704259, - 0x3162c102, - 0x8150c001, - 0x42521e00, - 0x425322f0, - 0x3160e5a0, - 0x62533960, - 0x1a101020, - 0x6e236f13, - 0x16121611, - 0x70006a54 -}; + { + 0x2fcf603c, + 0x00f03f9d, + 0x0f30003d, + 0x003f0ff0, + 0x0000ff00, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00070003, + 0x31fd31fd, + 0x04000000, + 0x001d000f, + 0x000b0387, + 0x004340f4, + 0x80828000, + 0x00000f90, + 0x0510091e, + 0x00050054, + 0x11010000, + 0x0000003c, + 0x3030002f, + 0x0000027f, + 0xd3910000, + 0x0000193d, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x72487220, + 0x7303a32d, + 0x72037305, + 0x73067304, + 0x73767204, + 0xc7c07276, + 0x00018001, + 0x90109001, + 0x90010801, + 0x720d720c, + 0xb0c0720e, + 0xb0f07100, + 0x7218a0c0, + 0x10208132, + 0x06703952, + 0x16300020, + 0x14011101, + 0x60796c01, + 0x60f4607c, + 0x607961da, + 0x60796079, + 0x6079607a, + 0x60f4607c, + 0x607961da, + 0x60796079, + 0x1210607a, + 0x730f7220, + 0x73117310, + 0x00108181, + 0xb0709180, + 0x606f6051, + 0x606f6646, + 0x663cc030, + 0xc282c141, + 0x1820c470, + 0x6e236f13, + 0x16121611, + 0x78306882, + 0x78409ac0, + 0xc4829ad0, + 0x1820c5a0, + 0x12034093, + 0x16126e23, + 0x83606890, + 0x606f97e0, + 0x94908160, + 0x39808140, + 0x10012a70, + 0x84321611, + 0xc0f38444, + 0xc200c0f5, + 0x40ba1c01, + 0x1c10c100, + 0x4cb240b0, + 0x18031013, + 0x1a131830, + 0x39121a10, + 0x60ba68ad, + 0x60ba13f3, + 0x101513f3, + 0x1850c100, + 0x1a101a15, + 0x68b83914, + 0x7100b0d8, + 0xa0d8b108, + 0xb760b200, + 0x97808ac0, + 0xb0c1b0f1, + 0xb0f17100, + 0x7276a0c1, + 0xb003b480, + 0xb002b013, + 0x7229b012, + 0x7100b0d0, + 0x8140b100, + 0x71009290, + 0x8140b100, + 0x44d322f0, + 0x1c0313f0, + 0x929340df, + 0x71009492, + 0x9295b100, + 0x71009494, + 0xb0d0b100, + 0x7000a480, + 0xc030a0d1, + 0xc0409760, + 0xb0f19780, + 0x7100b0c1, + 0xa0c1b0f1, + 0xa0037276, + 0x7000a002, + 0x7310730f, + 0x663cc040, + 0x92f0c000, + 0x92a08ad0, + 0x91c0c110, + 0xb2f06496, + 0x92a082b0, + 0xb0f3b483, + 0x7100b0c3, + 0x64e6a0c3, + 0xb006606f, + 0xb004b016, + 0xb002b014, + 0x8400b012, + 0x04207872, + 0x39838143, + 0x94732a73, + 0x1832c1f2, + 0x10213162, + 0x00123151, + 0x94000020, + 0x16101030, + 0x22103930, + 0x12204124, + 0x10033150, + 0x16a03180, + 0x12029350, + 0x22731204, + 0x84304136, + 0x87d297c0, + 0x84501a82, + 0x87d497c0, + 0x61381a84, + 0x41432263, + 0x97c08440, + 0x1a8087d0, + 0x84601402, + 0x87d097c0, + 0x14041a80, + 0x8440614f, + 0x04107881, + 0x87d297c0, + 0x84601a42, + 0x04107881, + 0x87d497c0, + 0x31521a44, + 0x39633154, + 0x16130633, + 0x38343832, + 0x39823182, + 0x00423184, + 0x78509572, + 0x78109360, + 0x90509030, + 0x90407820, + 0xb2059060, + 0x6965cb40, + 0x936087e0, + 0xa0c5b0f5, + 0x83038ae2, + 0xc00c9302, + 0x8140c00b, + 0x39803180, + 0x81413940, + 0x0431c0f3, + 0x1441c014, + 0x1412c002, + 0x31226979, + 0xb0d1b101, + 0xb0727100, + 0xa04ea0d1, + 0xb011b06e, + 0xa041b06c, + 0xa487a488, + 0x720d720c, + 0x7276720e, + 0xa764b764, + 0x9760c440, + 0xc020c062, + 0xc07e9780, + 0xb0e0c07f, + 0xb0c1b0f1, + 0xb0f5b0c5, + 0xb7607100, + 0xa0c5a0e0, + 0x220080b0, + 0x621345a2, + 0x7100b88f, + 0x978eb073, + 0xb201b074, + 0x85708961, + 0x95511801, + 0x8a718a60, + 0x1c211801, + 0x14124db9, + 0x61ba49b7, + 0x41ba1c01, + 0xb4874db9, + 0xb48861ba, + 0xb0f1b061, + 0xb0417100, + 0xb0f1978f, + 0xb04e7100, + 0x8a73b06e, + 0x70008552, + 0x8180b88c, + 0x392489a4, + 0x00043184, + 0xc0509184, + 0x7850663c, + 0x73769360, + 0x72487276, + 0x72027206, + 0x73057204, + 0x606f7306, + 0x91b01300, + 0xc060b32d, + 0xb0f8663c, + 0x78606509, + 0x12009360, + 0x97801a10, + 0x9760c380, + 0x9760c280, + 0xb0c6a0c1, + 0x22008090, + 0x81544451, + 0x41ec1e04, + 0x16943914, + 0xb0f69784, + 0xd0708552, + 0x663c9862, + 0x8a738a62, + 0x9862e080, + 0x663c9873, + 0x87818790, + 0x4a101c01, + 0x1ef11801, + 0x87814a0e, + 0x97811af1, + 0xb0f67100, + 0x978116f1, + 0x7100a205, + 0xa0c6b0f6, + 0x821d61c6, + 0x418b1e0d, + 0x9880c030, + 0x88a48893, + 0x31343133, + 0x422522fd, + 0x3d343d33, + 0x30d32afd, + 0x821230d4, + 0x163d622b, + 0x3cd43cd3, + 0x82121a3d, + 0x94e3622b, + 0xb05394f4, + 0xc030618b, + 0x88929880, + 0x3d323132, + 0x313388a3, + 0xe0903d33, + 0x98739862, + 0x7000663c, + 0x88409850, + 0x463d2200, + 0x7000b830, + 0x22f08150, + 0xb0704259, + 0x3162c102, + 0x8150c001, + 0x42521e00, + 0x425322f0, + 0x3160e5a0, + 0x62533960, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006a54}; PATCH_FUN_SPEC void rf_patch_mce_ghs(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_hsp_4mbps.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_hsp_4mbps.h index e8612f6..76addf6 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_hsp_4mbps.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_hsp_4mbps.h @@ -1,318 +1,317 @@ /****************************************************************************** -* Filename: rf_patch_mce_hsp_4mbps.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 4Mbps High speed mode -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_mce_hsp_4mbps.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 4Mbps High speed mode + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_MCE_HSP_4MBPS_H #define _RF_PATCH_MCE_HSP_4MBPS_H -#include #include "../inc/hw_types.h" +#include #ifndef MCE_PATCH_TYPE - #define MCE_PATCH_TYPE static const uint32_t +#define MCE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_MCERAM_BASE - #define RFC_MCERAM_BASE 0x21008000 +#define RFC_MCERAM_BASE 0x21008000 #endif #ifndef MCE_PATCH_MODE - #define MCE_PATCH_MODE 0 +#define MCE_PATCH_MODE 0 #endif MCE_PATCH_TYPE patchHsp4mbpsMce[252] = -{ - 0x00036075, - 0x0079000f, - 0x00000000, - 0x000c8000, - 0x0000000a, - 0x00780002, - 0x80000000, - 0x06700808, - 0x0b000000, - 0x00500104, - 0x00000000, - 0x01ff0000, - 0x04030000, - 0x017f7f26, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x05952fc8, - 0x00ff2f8f, - 0x00ff00ff, - 0x00ff00ff, - 0x00ff00ff, - 0x00faf320, - 0xaaaa0000, - 0xaaaaaaaa, - 0xaaaaaaaa, - 0x2000faf3, - 0x00580200, - 0x0f700288, - 0x00010fd0, - 0x0a400000, - 0x0d100002, - 0x0f590b08, - 0x04340f9a, - 0x067d0b08, - 0x09820f9a, - 0x0bcb0b08, - 0x00a60f9a, - 0x02ef0b08, - 0x00000f9a, - 0x00000000, - 0x00000000, - 0xc1020000, - 0xc0013162, - 0x1e008150, - 0x1a10406d, - 0x1020606f, - 0x6f131a10, - 0x16116e23, - 0x686f1612, - 0x72207000, - 0x7310730f, - 0x720c7311, - 0x720e720d, - 0x73057248, - 0x73767306, - 0xc7c07276, - 0xb0c09010, - 0xb0f07100, - 0x7218a0c0, - 0x10208132, - 0x06703952, - 0x16300020, - 0x14011101, - 0x60b16c01, - 0x60de60c3, - 0x60b1611b, - 0x60b160b1, - 0x60b160b2, - 0x60de60c3, - 0x60b1611b, - 0x60b160b1, - 0x60b160b2, - 0x60de60c3, - 0x60b1611b, - 0x60b160b1, - 0x60b160b2, - 0x60de60c3, - 0x60b1611b, - 0x60b160b1, - 0x60b660b2, - 0x60b66465, - 0x60b71220, - 0x72201210, - 0x00108181, - 0xb0709180, - 0x00006083, - 0x00000000, - 0x00000000, - 0xc0110000, - 0xc560c282, - 0x6f131820, - 0x16116e23, - 0x68c71612, - 0x95a07ce0, - 0xc4f1c100, - 0x6f13c622, - 0x16116e23, - 0x68d11612, - 0x000060b6, - 0x00000000, - 0x00000000, - 0x00000000, - 0xc3517220, - 0x9290c0f0, - 0x94926f12, - 0xb1081611, - 0x7100b0d8, - 0xa0d8b108, - 0xb480b200, - 0x91c0c140, - 0xb012b002, - 0xb013b003, - 0xb100c0c0, - 0x7100b0d0, - 0x6f12b100, - 0x94921611, - 0xa0d068f5, - 0xb483a480, - 0xb0c3b0f3, - 0x1220b0f1, - 0xc0c09760, - 0x71009780, - 0xb482a0c3, - 0xb0c1b760, - 0xb0f17100, - 0xa483a0c1, - 0xa003a760, - 0xc7c0a002, - 0x60b69010, - 0x00000000, - 0x00000000, - 0x00000000, - 0x72200000, - 0x91b0c140, - 0x94327c52, - 0x94427c42, - 0x94027c62, - 0x93227c72, - 0x7cd07cc6, - 0xc00093b0, - 0xc3f09370, - 0xc3f13180, - 0x95f10001, - 0x96119601, - 0x7ce095e0, - 0xb00695a0, - 0xb004b016, - 0xb002b014, - 0xb107b012, - 0x7100b0d7, - 0xb072a0d7, - 0x90307b20, - 0x7b309050, - 0x90609040, - 0x72767b44, - 0x9762c022, - 0x9780c0e0, - 0x1e108210, - 0xc030454c, - 0xcb4065f2, - 0x65d36952, - 0xa0c5b0f5, - 0xb0f8b201, - 0xb0e0b110, - 0xb0737100, - 0xb072b760, - 0xb0619044, - 0xa0e0b110, - 0xb202a0c5, - 0x7ca2b074, - 0xb0c19362, - 0x7100b0f1, - 0x9780c080, - 0x88907388, - 0x88a194e0, - 0x936694f1, - 0x7100b0f1, - 0x9780c310, - 0xb0f1b3b5, - 0xc0307100, - 0x7c809780, - 0xb0f19320, - 0xc0207100, - 0xb0459780, - 0xb0f1b065, - 0xb04f7100, - 0xb0f1b06f, - 0x7276a0c1, - 0x97701240, - 0x9780fff0, - 0x9760c380, - 0xb0c8a764, - 0x7100b889, - 0xa0c8b0f8, - 0xd0408152, - 0x65f29862, - 0x97823112, - 0xb0c6b0f6, - 0xb0f67100, - 0xb107a0c6, - 0x7100b0d7, - 0x7100b107, - 0x7276b107, - 0x7100c0f0, - 0x7100b107, - 0xb5b0b107, - 0xa0d769a9, - 0x8a738a62, - 0x9862e050, - 0x65f29873, - 0xa202a201, - 0x31828942, - 0x84e73d82, - 0x313784f8, - 0x31383d37, - 0xe0603d38, - 0x98789867, - 0xc00065f2, - 0x93609370, - 0x94f094e0, - 0x73067305, - 0x72047203, - 0xa002a004, - 0x9010c7c0, - 0x7cb260b6, - 0x12f09362, - 0x738869d6, - 0x94e08890, - 0x94f188a1, - 0x7c929366, - 0xb0539362, - 0x31371007, - 0x10183d37, - 0x3d383138, - 0x9867e070, - 0x65f29878, - 0x00007000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x88409850, - 0x45f32200, - 0x7000b830 -}; + { + 0x00036075, + 0x0079000f, + 0x00000000, + 0x000c8000, + 0x0000000a, + 0x00780002, + 0x80000000, + 0x06700808, + 0x0b000000, + 0x00500104, + 0x00000000, + 0x01ff0000, + 0x04030000, + 0x017f7f26, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x05952fc8, + 0x00ff2f8f, + 0x00ff00ff, + 0x00ff00ff, + 0x00ff00ff, + 0x00faf320, + 0xaaaa0000, + 0xaaaaaaaa, + 0xaaaaaaaa, + 0x2000faf3, + 0x00580200, + 0x0f700288, + 0x00010fd0, + 0x0a400000, + 0x0d100002, + 0x0f590b08, + 0x04340f9a, + 0x067d0b08, + 0x09820f9a, + 0x0bcb0b08, + 0x00a60f9a, + 0x02ef0b08, + 0x00000f9a, + 0x00000000, + 0x00000000, + 0xc1020000, + 0xc0013162, + 0x1e008150, + 0x1a10406d, + 0x1020606f, + 0x6f131a10, + 0x16116e23, + 0x686f1612, + 0x72207000, + 0x7310730f, + 0x720c7311, + 0x720e720d, + 0x73057248, + 0x73767306, + 0xc7c07276, + 0xb0c09010, + 0xb0f07100, + 0x7218a0c0, + 0x10208132, + 0x06703952, + 0x16300020, + 0x14011101, + 0x60b16c01, + 0x60de60c3, + 0x60b1611b, + 0x60b160b1, + 0x60b160b2, + 0x60de60c3, + 0x60b1611b, + 0x60b160b1, + 0x60b160b2, + 0x60de60c3, + 0x60b1611b, + 0x60b160b1, + 0x60b160b2, + 0x60de60c3, + 0x60b1611b, + 0x60b160b1, + 0x60b660b2, + 0x60b66465, + 0x60b71220, + 0x72201210, + 0x00108181, + 0xb0709180, + 0x00006083, + 0x00000000, + 0x00000000, + 0xc0110000, + 0xc560c282, + 0x6f131820, + 0x16116e23, + 0x68c71612, + 0x95a07ce0, + 0xc4f1c100, + 0x6f13c622, + 0x16116e23, + 0x68d11612, + 0x000060b6, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc3517220, + 0x9290c0f0, + 0x94926f12, + 0xb1081611, + 0x7100b0d8, + 0xa0d8b108, + 0xb480b200, + 0x91c0c140, + 0xb012b002, + 0xb013b003, + 0xb100c0c0, + 0x7100b0d0, + 0x6f12b100, + 0x94921611, + 0xa0d068f5, + 0xb483a480, + 0xb0c3b0f3, + 0x1220b0f1, + 0xc0c09760, + 0x71009780, + 0xb482a0c3, + 0xb0c1b760, + 0xb0f17100, + 0xa483a0c1, + 0xa003a760, + 0xc7c0a002, + 0x60b69010, + 0x00000000, + 0x00000000, + 0x00000000, + 0x72200000, + 0x91b0c140, + 0x94327c52, + 0x94427c42, + 0x94027c62, + 0x93227c72, + 0x7cd07cc6, + 0xc00093b0, + 0xc3f09370, + 0xc3f13180, + 0x95f10001, + 0x96119601, + 0x7ce095e0, + 0xb00695a0, + 0xb004b016, + 0xb002b014, + 0xb107b012, + 0x7100b0d7, + 0xb072a0d7, + 0x90307b20, + 0x7b309050, + 0x90609040, + 0x72767b44, + 0x9762c022, + 0x9780c0e0, + 0x1e108210, + 0xc030454c, + 0xcb4065f2, + 0x65d36952, + 0xa0c5b0f5, + 0xb0f8b201, + 0xb0e0b110, + 0xb0737100, + 0xb072b760, + 0xb0619044, + 0xa0e0b110, + 0xb202a0c5, + 0x7ca2b074, + 0xb0c19362, + 0x7100b0f1, + 0x9780c080, + 0x88907388, + 0x88a194e0, + 0x936694f1, + 0x7100b0f1, + 0x9780c310, + 0xb0f1b3b5, + 0xc0307100, + 0x7c809780, + 0xb0f19320, + 0xc0207100, + 0xb0459780, + 0xb0f1b065, + 0xb04f7100, + 0xb0f1b06f, + 0x7276a0c1, + 0x97701240, + 0x9780fff0, + 0x9760c380, + 0xb0c8a764, + 0x7100b889, + 0xa0c8b0f8, + 0xd0408152, + 0x65f29862, + 0x97823112, + 0xb0c6b0f6, + 0xb0f67100, + 0xb107a0c6, + 0x7100b0d7, + 0x7100b107, + 0x7276b107, + 0x7100c0f0, + 0x7100b107, + 0xb5b0b107, + 0xa0d769a9, + 0x8a738a62, + 0x9862e050, + 0x65f29873, + 0xa202a201, + 0x31828942, + 0x84e73d82, + 0x313784f8, + 0x31383d37, + 0xe0603d38, + 0x98789867, + 0xc00065f2, + 0x93609370, + 0x94f094e0, + 0x73067305, + 0x72047203, + 0xa002a004, + 0x9010c7c0, + 0x7cb260b6, + 0x12f09362, + 0x738869d6, + 0x94e08890, + 0x94f188a1, + 0x7c929366, + 0xb0539362, + 0x31371007, + 0x10183d37, + 0x3d383138, + 0x9867e070, + 0x65f29878, + 0x00007000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x88409850, + 0x45f32200, + 0x7000b830}; PATCH_FUN_SPEC void rf_patch_mce_hsp_4mbps(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_iqdump.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_iqdump.h index 6babc9e..87a2fa0 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_iqdump.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_iqdump.h @@ -1,399 +1,398 @@ /****************************************************************************** -* Filename: rf_patch_mce_iqdump.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 IQ data -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_mce_iqdump.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 IQ data + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_MCE_IQDUMP_H #define _RF_PATCH_MCE_IQDUMP_H -#include #include "../inc/hw_types.h" +#include #ifndef MCE_PATCH_TYPE - #define MCE_PATCH_TYPE static const uint32_t +#define MCE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_MCERAM_BASE - #define RFC_MCERAM_BASE 0x21008000 +#define RFC_MCERAM_BASE 0x21008000 #endif #ifndef MCE_PATCH_MODE - #define MCE_PATCH_MODE 0 +#define MCE_PATCH_MODE 0 #endif MCE_PATCH_TYPE patchIqdumpMce[333] = -{ - 0x0000602d, - 0x3f9d2fcf, - 0x003f0001, - 0x0fffff00, - 0xf80007ff, - 0x00000300, - 0x00170003, - 0x00003d1f, - 0x08000000, - 0x0000000f, - 0x00000387, - 0x00434074, - 0x80828000, - 0x000006f0, - 0x0510091e, - 0x00070054, - 0x50140000, - 0x00000050, - 0x0c30c02f, - 0x0000017f, - 0x00000000, - 0x0000aa00, - 0x72200000, - 0xa32d7248, - 0x73057303, - 0x73047203, - 0x72047306, - 0x72767376, - 0x8001c7c0, - 0x90010001, - 0x08019010, - 0x720c9001, - 0x720e720d, - 0x7100b0c0, - 0xa0c0b0f0, - 0x81327218, - 0x39521020, - 0x00200670, - 0x11011630, - 0x6c011401, - 0x6081607e, - 0x60fa60ec, - 0x607e607e, - 0x607e607e, - 0x6081607e, - 0x619e60ec, - 0x607e607e, - 0x607e607e, - 0x6081607e, - 0x610a60ec, - 0x607e607e, - 0x607e607e, - 0x6081607e, - 0x61ba60ec, - 0x607e607e, - 0x607e607e, - 0x6081607e, - 0x614260ec, - 0x72201210, - 0x7310730f, - 0x81817311, - 0x91800010, - 0x6042b070, - 0x66896074, - 0xc0306074, - 0xc0c16674, - 0xc470c282, - 0x6f131820, - 0x16116e23, - 0x68871612, - 0x98107840, - 0xc5a0c482, - 0x40961820, - 0x6e231203, - 0x68931612, - 0x81606074, - 0x81409490, - 0x2a703980, - 0x16111001, - 0x84448432, - 0xc0f5c0f3, - 0x1c01c200, - 0xc10040bb, - 0x40b11c10, - 0x10134cb3, - 0x18301803, - 0x1a101a13, - 0x68ae3912, - 0x13f360bb, - 0x13f360bb, - 0xc1001015, - 0x1a151850, - 0x39141a10, - 0xb0d868b9, - 0xb1087100, - 0xb200a0d8, - 0xb003b480, - 0xb002b013, - 0x7229b012, - 0x7100b0d0, - 0x8140b100, - 0x71009290, - 0x8140b100, - 0x44cb22f0, - 0x1c0313f0, - 0x929340d7, - 0x71009492, - 0x9295b100, - 0x71009494, - 0xb0d0b100, - 0x7000a480, - 0xc030a0d1, - 0xc0409760, - 0xb0f19780, - 0x7100b0c1, - 0xa0c1b0f1, - 0xa0037276, - 0x7000a002, - 0x7310730f, - 0x6674c040, - 0x91c0c100, - 0xb4836497, - 0xb0c3b0f3, - 0xa0c37100, - 0x607464de, - 0xa0e0a0c2, - 0x730fa0e3, - 0x65fe7310, - 0x6674c050, - 0xc035b0c2, - 0x99c57100, - 0xb074b888, - 0x6104b0f2, - 0xa0e0a0c2, - 0x730fa0e3, - 0x65fe7310, - 0xc000c18b, - 0x120c91b0, - 0x787a1218, - 0x789e788d, - 0xb07410a9, - 0xc020b0c2, - 0x7100b0f2, - 0xc060691c, - 0xc0356674, - 0x7100b0f2, - 0x8a3099c5, - 0x8ad16593, - 0x412f2201, - 0x1ca81080, - 0x1208452e, - 0x658a1618, - 0x65938a40, - 0x22018ad1, - 0x1090413a, - 0x1e091a19, - 0x10a9453a, - 0x8154658a, - 0x41221e04, - 0x1c4c14bc, - 0x61224e5d, - 0xa0e0a0c2, - 0x730fa0e3, - 0x65fe7310, - 0x120c721b, - 0xb0741205, - 0xc020b0c2, - 0x7100b0f2, - 0xc070694e, - 0x78ad6674, - 0xb0f2881e, - 0x8ac07100, - 0x415e2200, - 0x22108200, - 0xb201455e, - 0x8902988d, - 0x3d823182, - 0x31808940, - 0x18023d80, - 0x1e0e063e, - 0x1e2e4180, - 0x1e3e4172, - 0x10564179, - 0x3d161426, - 0x61811065, - 0x31261056, - 0x14261856, - 0x10653d26, - 0x10566181, - 0x18563136, - 0x3d361426, - 0x61811065, - 0x39761026, - 0x81549196, - 0x41551e04, - 0x1c4c161c, - 0x61554e5d, - 0xc0b01001, - 0x39119191, - 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0x39633154, + 0x16130633, + 0x38343832, + 0x39823182, + 0x00423184, + 0x78209572, + 0x90509030, + 0x90407830, + 0xb2059060, + 0x9140cd90, + 0xa2057000, + 0x7100b0f2, + 0xb0f2a0c2, + 0x8180b88c, + 0x392489a4, + 0x00043184, + 0xc0d09184, + 0x73766674, + 0x72487276, + 0x72027206, + 0x73057204, + 0x60747306, + 0x88409850, + 0x46752200, + 0x7000b830, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc1020000, + 0xc0013162, + 0x1e008150, + 0x1a104291, + 0x10206293, + 0x6f131a10, + 0x16116e23, + 0x6a931612, + 0x00007000}; PATCH_FUN_SPEC void rf_patch_mce_iqdump(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_sl_longrange.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_sl_longrange.h index 4807acc..ee291e4 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_sl_longrange.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_sl_longrange.h @@ -1,322 +1,321 @@ /****************************************************************************** -* Filename: rf_patch_mce_sl_longrange.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 Simplelink Long range -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_mce_sl_longrange.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 Simplelink Long range + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_MCE_SL_LONGRANGE_H #define _RF_PATCH_MCE_SL_LONGRANGE_H -#include #include "../inc/hw_types.h" +#include #ifndef MCE_PATCH_TYPE - #define MCE_PATCH_TYPE static const uint32_t +#define MCE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_MCERAM_BASE - #define RFC_MCERAM_BASE 0x21008000 +#define RFC_MCERAM_BASE 0x21008000 #endif #ifndef MCE_PATCH_MODE - #define MCE_PATCH_MODE 0 +#define MCE_PATCH_MODE 0 #endif MCE_PATCH_TYPE patchSl_longrangeMce[256] = -{ - 0x146f603e, - 0x333c3c33, - 0x3cc3cccc, - 0x2fcf0005, - 0xdb3e0f9d, - 0x00007f7f, - 0x00020001, - 0x00000003, - 0x000c0003, - 0x00cc000f, - 0x003c00c3, - 0xcccc0033, - 0x33cccc33, - 0x0f003333, - 0x00000f0f, - 0x00070003, - 0x0000001f, - 0x04000000, - 0x0000000f, - 0x00010387, - 0x004348c0, - 0x80048000, - 0x000006f0, - 0x0524091e, - 0x00050054, - 0x48200800, - 0x00000048, - 0x7f7f001f, - 0x3c33014c, - 0xcccc333c, - 0x00003cc3, - 0x72487220, - 0x73057303, - 0x73047203, - 0x72047306, - 0x72767376, - 0x8001c7c0, - 0x90010001, - 0x08019010, - 0x720c9001, - 0x720e720d, - 0x7100b0c0, - 0xa0c0b0f0, - 0x81327218, - 0x39521020, - 0x00200670, - 0x11011630, - 0x6c011401, - 0x60766074, - 0x610e608a, - 0x60746074, - 0x60756074, - 0x606b1220, - 0x72201210, - 0x7310730f, - 0x81817311, - 0x91800010, - 0x6052b070, - 0x606a606a, - 0xc282c1e1, - 0x1820c470, - 0x6e236f13, - 0x16121611, - 0xc482687a, - 0x1820c810, - 0x12034087, - 0x16126e23, - 0xd0006884, - 0x606a9170, - 0x7310730f, - 0x91c0c000, - 0x8170c009, - 0x06703980, - 0x1e101610, - 0xc0b74499, - 0xc01ec008, - 0x1e2060aa, - 0xc0f7449f, - 0xc03ec018, - 0x1e4060aa, - 0xc13744a5, - 0xc07ec038, - 0x1e8060aa, - 0xc1774468, - 0xc0fec078, - 0x65f9c030, - 0x7100b0d8, - 0xa0d8b108, - 0xb480b200, - 0xb013b003, - 0xb012b002, - 0x39468146, - 0x0446c0f4, - 0xb0d01616, - 0xc13cc004, - 0x9290c070, - 0xc0707811, - 0x06321012, - 0x6f2314c2, - 0x71009493, - 0x3921b100, - 0x161468c2, - 0x44c01c64, - 0x0bf17811, - 0x1012c070, - 0x14c20632, - 0x94936f23, - 0xb1007100, - 0x68d13921, - 0xc6d5c4f4, - 0x81afc066, - 0x81e064f7, - 0x40e32210, - 0xc07060dd, - 0xc00f1610, - 0x68e564f7, - 0xc030a0d1, - 0xc0409760, - 0xb0f19780, - 0x7100b0c1, - 0xa0c1b0f1, - 0xa0037276, - 0x7220a002, - 0x061f606a, - 0x00f9316f, - 0x04411091, - 0x87da97c1, - 0x1091061a, - 0x97c10451, - 0x061b87db, - 0x14ba311b, - 0x147a3919, - 0x94936fa3, - 0x7100929e, - 0x7000b100, - 0x8ae4b0f8, - 0x93044112, - 0x9400c1f0, - 0x941078a0, - 0x8177721b, - 0x39871076, - 0x97c70677, - 0x161887d8, - 0x9867d040, - 0x782065f9, - 0x78309430, - 0x78409440, - 0x78509450, - 0x655a9460, - 0x98107890, - 0xb007656d, - 0xb104b017, - 0xc205b0d4, - 0x65e1c004, - 0x1c5465f2, - 0x91904938, - 0x81511614, - 0x41331e01, - 0x1c411671, - 0xa0d74d33, - 0x79cf79be, - 0x95ff95ee, - 0x65f21204, - 0x1c541614, - 0x9190414b, - 0xa2056145, - 0x65f9c050, - 0xa0d4a0d7, - 0x72027206, - 0x72037204, - 0x73057204, - 0x73767306, - 0x606a7276, - 0x3181c061, - 0xcff3c002, - 0x16116e12, - 0x16116e12, - 0x6e13c7e0, - 0x6e121611, - 0x69631611, - 0x6e12cff0, - 0x69691611, - 0xb0067000, - 0xb004b016, - 0xb002b014, - 0x7870b012, - 0x90509030, - 0x90407880, - 0xb2059060, - 0xc090b072, - 0xb11793b0, - 0xb116b0e7, - 0x7100b0e6, - 0xb107b073, - 0xa0e7a0e7, - 0x227080b0, - 0xa0e645a2, - 0xb0d7a0e7, - 0x7100b88e, - 0xb107b116, - 0xb061b041, - 0x93b0c0f0, - 0x8964b88f, - 0x95543114, - 0x7100a044, - 0xb04db107, - 0xb074b06d, - 0x7100b201, - 0x7000b107, - 0xb889b0d7, - 0x31848944, - 0x97243d84, - 0x97307860, - 0x69abc050, - 0xc2018740, - 0x3d601410, - 0x31648304, - 0x18043d64, - 0x3520cff0, - 0x93040404, - 0x93b0c0b0, - 0xd060b069, - 0x65f99864, - 0xb1077100, - 0x617da0d7, - 0x120a1209, - 0x140965d7, - 0x1e17141a, - 0x65d741d4, - 0x140a1419, - 0x41d41e37, - 0x140965d7, - 0x65d7141a, - 0x140a1419, - 0x3c8a3c89, - 0x71007000, - 0x7100b107, - 0x87f0b107, - 0x39803180, - 0x39818801, - 0x65c27000, - 0x10ac109b, - 0x10bd65c2, - 0x14db318d, - 0x318d10cd, - 0x318a14dc, - 0x149b14a9, - 0x95eb149c, - 0x700095fc, - 0xb079a0d7, - 0xb1047100, - 0x8820b0d7, - 0x98507000, - 0x22008840, - 0xb83045fa, - 0x00007000 -}; + { + 0x146f603e, + 0x333c3c33, + 0x3cc3cccc, + 0x2fcf0005, + 0xdb3e0f9d, + 0x00007f7f, + 0x00020001, + 0x00000003, + 0x000c0003, + 0x00cc000f, + 0x003c00c3, + 0xcccc0033, + 0x33cccc33, + 0x0f003333, + 0x00000f0f, + 0x00070003, + 0x0000001f, + 0x04000000, + 0x0000000f, + 0x00010387, + 0x004348c0, + 0x80048000, + 0x000006f0, + 0x0524091e, + 0x00050054, + 0x48200800, + 0x00000048, + 0x7f7f001f, + 0x3c33014c, + 0xcccc333c, + 0x00003cc3, + 0x72487220, + 0x73057303, + 0x73047203, + 0x72047306, + 0x72767376, + 0x8001c7c0, + 0x90010001, + 0x08019010, + 0x720c9001, + 0x720e720d, + 0x7100b0c0, + 0xa0c0b0f0, + 0x81327218, + 0x39521020, + 0x00200670, + 0x11011630, + 0x6c011401, + 0x60766074, + 0x610e608a, + 0x60746074, + 0x60756074, + 0x606b1220, + 0x72201210, + 0x7310730f, + 0x81817311, + 0x91800010, + 0x6052b070, + 0x606a606a, + 0xc282c1e1, + 0x1820c470, + 0x6e236f13, + 0x16121611, + 0xc482687a, + 0x1820c810, + 0x12034087, + 0x16126e23, + 0xd0006884, + 0x606a9170, + 0x7310730f, + 0x91c0c000, + 0x8170c009, + 0x06703980, + 0x1e101610, + 0xc0b74499, + 0xc01ec008, + 0x1e2060aa, + 0xc0f7449f, + 0xc03ec018, + 0x1e4060aa, + 0xc13744a5, + 0xc07ec038, + 0x1e8060aa, + 0xc1774468, + 0xc0fec078, + 0x65f9c030, + 0x7100b0d8, + 0xa0d8b108, + 0xb480b200, + 0xb013b003, + 0xb012b002, + 0x39468146, + 0x0446c0f4, + 0xb0d01616, + 0xc13cc004, + 0x9290c070, + 0xc0707811, + 0x06321012, + 0x6f2314c2, + 0x71009493, + 0x3921b100, + 0x161468c2, + 0x44c01c64, + 0x0bf17811, + 0x1012c070, + 0x14c20632, + 0x94936f23, + 0xb1007100, + 0x68d13921, + 0xc6d5c4f4, + 0x81afc066, + 0x81e064f7, + 0x40e32210, + 0xc07060dd, + 0xc00f1610, + 0x68e564f7, + 0xc030a0d1, + 0xc0409760, + 0xb0f19780, + 0x7100b0c1, + 0xa0c1b0f1, + 0xa0037276, + 0x7220a002, + 0x061f606a, + 0x00f9316f, + 0x04411091, + 0x87da97c1, + 0x1091061a, + 0x97c10451, + 0x061b87db, + 0x14ba311b, + 0x147a3919, + 0x94936fa3, + 0x7100929e, + 0x7000b100, + 0x8ae4b0f8, + 0x93044112, + 0x9400c1f0, + 0x941078a0, + 0x8177721b, + 0x39871076, + 0x97c70677, + 0x161887d8, + 0x9867d040, + 0x782065f9, + 0x78309430, + 0x78409440, + 0x78509450, + 0x655a9460, + 0x98107890, + 0xb007656d, + 0xb104b017, + 0xc205b0d4, + 0x65e1c004, + 0x1c5465f2, + 0x91904938, + 0x81511614, + 0x41331e01, + 0x1c411671, + 0xa0d74d33, + 0x79cf79be, + 0x95ff95ee, + 0x65f21204, + 0x1c541614, + 0x9190414b, + 0xa2056145, + 0x65f9c050, + 0xa0d4a0d7, + 0x72027206, + 0x72037204, + 0x73057204, + 0x73767306, + 0x606a7276, + 0x3181c061, + 0xcff3c002, + 0x16116e12, + 0x16116e12, + 0x6e13c7e0, + 0x6e121611, + 0x69631611, + 0x6e12cff0, + 0x69691611, + 0xb0067000, + 0xb004b016, + 0xb002b014, + 0x7870b012, + 0x90509030, + 0x90407880, + 0xb2059060, + 0xc090b072, + 0xb11793b0, + 0xb116b0e7, + 0x7100b0e6, + 0xb107b073, + 0xa0e7a0e7, + 0x227080b0, + 0xa0e645a2, + 0xb0d7a0e7, + 0x7100b88e, + 0xb107b116, + 0xb061b041, + 0x93b0c0f0, + 0x8964b88f, + 0x95543114, + 0x7100a044, + 0xb04db107, + 0xb074b06d, + 0x7100b201, + 0x7000b107, + 0xb889b0d7, + 0x31848944, + 0x97243d84, + 0x97307860, + 0x69abc050, + 0xc2018740, + 0x3d601410, + 0x31648304, + 0x18043d64, + 0x3520cff0, + 0x93040404, + 0x93b0c0b0, + 0xd060b069, + 0x65f99864, + 0xb1077100, + 0x617da0d7, + 0x120a1209, + 0x140965d7, + 0x1e17141a, + 0x65d741d4, + 0x140a1419, + 0x41d41e37, + 0x140965d7, + 0x65d7141a, + 0x140a1419, + 0x3c8a3c89, + 0x71007000, + 0x7100b107, + 0x87f0b107, + 0x39803180, + 0x39818801, + 0x65c27000, + 0x10ac109b, + 0x10bd65c2, + 0x14db318d, + 0x318d10cd, + 0x318a14dc, + 0x149b14a9, + 0x95eb149c, + 0x700095fc, + 0xb079a0d7, + 0xb1047100, + 0x8820b0d7, + 0x98507000, + 0x22008840, + 0xb83045fa, + 0x00007000}; PATCH_FUN_SPEC void rf_patch_mce_sl_longrange(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_wb_dsss.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_wb_dsss.h index aa4b009..c752de0 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_wb_dsss.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_wb_dsss.h @@ -1,345 +1,344 @@ /****************************************************************************** -* Filename: rf_patch_mce_wb_dsss.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 Wideband DSSS -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_mce_wb_dsss.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 Wideband DSSS + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_MCE_WB_DSSS_H #define _RF_PATCH_MCE_WB_DSSS_H -#include #include "../inc/hw_types.h" +#include #ifndef MCE_PATCH_TYPE - #define MCE_PATCH_TYPE static const uint32_t +#define MCE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_MCERAM_BASE - #define RFC_MCERAM_BASE 0x21008000 +#define RFC_MCERAM_BASE 0x21008000 #endif #ifndef MCE_PATCH_MODE - #define MCE_PATCH_MODE 0 +#define MCE_PATCH_MODE 0 #endif MCE_PATCH_TYPE patchWbDsssMce[279] = -{ - 0x2fcf6068, - 0xdb3e0f9d, - 0x7f7f0303, - 0x00010000, - 0x00030002, - 0x00030000, - 0x000f000c, - 0x00c300cc, - 0x0033003c, - 0xcc33cccc, - 0x333333cc, - 0x0f0f0f00, - 0x03050404, - 0x01070206, - 0x00090008, - 0x000b000a, - 0x0b000c00, - 0x09000a00, - 0x07010800, - 0x05030602, - 0x03030404, - 0x01010202, - 0x00000000, - 0x00000000, - 0x0b0b0c0c, - 0x09090a0a, - 0x07070808, - 0x05050606, - 0x05050404, - 0x07070606, - 0x09090808, - 0x0b0b0a0a, - 0x00000000, - 0x00000000, - 0x01010000, - 0x03030202, - 0x00070003, - 0x0000001f, - 0x04000000, - 0x0000000f, - 0x00010387, - 0x004348c9, - 0x80048000, - 0x000006f0, - 0x0524091e, - 0x00070054, - 0x280a0000, - 0x00000028, - 0x7f7f001f, - 0x3c33013e, - 0xcccc333c, - 0x00003cc3, - 0x72487220, - 0x73057303, - 0x73047203, - 0x72047306, - 0x72767376, - 0x8001c7c0, - 0x90010001, - 0x08019010, - 0x720c9001, - 0x720e720d, - 0x7100b0c0, - 0xa0c0b0f0, - 0x81327218, - 0x39521020, - 0x00200670, - 0x11011630, - 0x6c011401, - 0x60a0609e, - 0x613260b4, - 0x609e609e, - 0x609f609e, - 0x60951220, - 0x72201210, - 0x7310730f, - 0x81817311, - 0x91800010, - 0x607cb070, - 0x60946094, - 0xc282c481, - 0x1820c470, - 0x6e236f13, - 0x16121611, - 0xc48268a4, - 0x1820c810, - 0x120340b1, - 0x16126e23, - 0x784068ae, - 0x60949ab0, - 0x7310730f, - 0x91c0c000, - 0x8ab0c009, - 0x06703980, - 0xc0f41610, - 0xc036c0b5, - 0x44c61e10, - 0xc008c067, - 0x60d7c01e, - 0x44cc1e20, - 0xc018c0a7, - 0x60d7c03e, - 0x44d21e40, - 0xc038c0e7, - 0x60d7c07e, - 0x44921e80, - 0xc078c127, - 0x1062c0fe, - 0xe0301612, - 0x98789862, - 0x8160657c, - 0x81409490, - 0xb0d89290, - 0xb1087100, - 0xb200a0d8, - 0xb003b480, - 0xb002b013, - 0xb0d0b012, - 0xb1007100, - 0x22f08140, - 0xc0f044eb, - 0x84509290, - 0x71009490, - 0x8460b100, - 0x71009490, - 0x8430b100, - 0x71009490, - 0x8440b100, - 0x81af9490, - 0x81e0651b, - 0x41072210, - 0x10606101, - 0xc00f1620, - 0x6909651b, - 0xc030a0d1, - 0xc0409760, - 0xb0f19780, - 0x7100b0c1, - 0xa0c1b0f1, - 0xa0037276, - 0x7220a002, - 0x061f6094, - 0x00f9306f, - 0x04411091, - 0x87da97c1, - 0x1091061a, - 0x97c10451, - 0x061b87db, - 0x14ba311b, - 0x147a3919, - 0x71006fa3, - 0x9493b100, - 0x7000929e, - 0xc1f0b0f8, - 0x78509400, - 0x721b9410, - 0x10768ab7, - 0x06773987, - 0x87d897c7, - 0x1e071618, - 0xc0064543, - 0x1e17614e, - 0xc0064547, - 0x1e37614e, - 0xc036454b, - 0x1e77614e, - 0xc3364492, - 0xb0066182, - 0xb004b016, - 0xb002b014, - 0x7810b012, - 0x90509030, - 0x90407820, - 0xb2059060, - 0xc0b0b072, - 0xb11693b0, - 0x7100b0e6, - 0xb107b073, - 0xa0e6b116, - 0xb88eb0d7, - 0xb1077100, - 0xb061b041, - 0x93b0c0f0, - 0x8964b88f, - 0x95543114, - 0x7100a044, - 0xb04db107, - 0xb074b06d, - 0x7100b201, - 0x7000b107, - 0x88409850, - 0x457d2200, - 0x7000b830, - 0x9867d040, - 0xe1d1657c, - 0x95a06f10, - 0xe1e1c100, - 0x6f13c622, - 0x16116e23, - 0x698b1612, - 0x41e41e07, - 0xb04f654f, - 0xc0f5b06f, - 0x65d4c004, - 0x85d0b5b0, - 0x1c543920, - 0x9190499e, - 0x81511614, - 0x41971e01, - 0x1c411621, - 0xa0d74d97, - 0x797f796e, - 0x95ff95ee, - 0xb5b01204, - 0x392085d0, - 0x1c541614, - 0x919041b3, - 0xa20561ab, - 0x657cc050, - 0xa0d4a0d7, - 0x72027206, - 0x72037204, - 0x73057204, - 0x73767306, - 0x60947276, - 0x12091070, - 0xb1077100, - 0x89b3b88d, - 0x3d833183, - 0x41cd2006, - 0x14390bf3, - 0x3c8969c4, - 0x3d391649, - 0x700006f9, - 0xc28a65c2, - 0x6fab149a, - 0x149ac38a, - 0xc18a6fac, - 0x149a65c2, - 0x14db6fad, - 0x95ec14dc, - 0x700095fb, - 0x657cc060, - 0xb04f654f, - 0xc0f5b06f, - 0x7100c004, - 0x7100b107, - 0x87fcb107, - 0x95ec880b, - 0xb5b095fb, - 0x392085d0, - 0x49f91c54, - 0x16149190, - 0x1e018151, - 0x162141eb, - 0x4deb1c41, - 0x796ea0d7, - 0x95ee797f, - 0x120495ff, - 0x85d0b5b0, - 0x16143920, - 0x420e1c54, - 0x62069190, - 0xc070a205, - 0xa0d7657c, - 0x7206a0d4, - 0x72047202, - 0x72047203, - 0x73067305, - 0x72767376, - 0x00016094, - 0x00080018, - 0x001a0003, - 0x002c000a, - 0x003e0011, - 0x00080003, - 0x001a0018, - 0x002c0011, - 0x003e000a -}; + { + 0x2fcf6068, + 0xdb3e0f9d, + 0x7f7f0303, + 0x00010000, + 0x00030002, + 0x00030000, + 0x000f000c, + 0x00c300cc, + 0x0033003c, + 0xcc33cccc, + 0x333333cc, + 0x0f0f0f00, + 0x03050404, + 0x01070206, + 0x00090008, + 0x000b000a, + 0x0b000c00, + 0x09000a00, + 0x07010800, + 0x05030602, + 0x03030404, + 0x01010202, + 0x00000000, + 0x00000000, + 0x0b0b0c0c, + 0x09090a0a, + 0x07070808, + 0x05050606, + 0x05050404, + 0x07070606, + 0x09090808, + 0x0b0b0a0a, + 0x00000000, + 0x00000000, + 0x01010000, + 0x03030202, + 0x00070003, + 0x0000001f, + 0x04000000, + 0x0000000f, + 0x00010387, + 0x004348c9, + 0x80048000, + 0x000006f0, + 0x0524091e, + 0x00070054, + 0x280a0000, + 0x00000028, + 0x7f7f001f, + 0x3c33013e, + 0xcccc333c, + 0x00003cc3, + 0x72487220, + 0x73057303, + 0x73047203, + 0x72047306, + 0x72767376, + 0x8001c7c0, + 0x90010001, + 0x08019010, + 0x720c9001, + 0x720e720d, + 0x7100b0c0, + 0xa0c0b0f0, + 0x81327218, + 0x39521020, + 0x00200670, + 0x11011630, + 0x6c011401, + 0x60a0609e, + 0x613260b4, + 0x609e609e, + 0x609f609e, + 0x60951220, + 0x72201210, + 0x7310730f, + 0x81817311, + 0x91800010, + 0x607cb070, + 0x60946094, + 0xc282c481, + 0x1820c470, + 0x6e236f13, + 0x16121611, + 0xc48268a4, + 0x1820c810, + 0x120340b1, + 0x16126e23, + 0x784068ae, + 0x60949ab0, + 0x7310730f, + 0x91c0c000, + 0x8ab0c009, + 0x06703980, + 0xc0f41610, + 0xc036c0b5, + 0x44c61e10, + 0xc008c067, + 0x60d7c01e, + 0x44cc1e20, + 0xc018c0a7, + 0x60d7c03e, + 0x44d21e40, + 0xc038c0e7, + 0x60d7c07e, + 0x44921e80, + 0xc078c127, + 0x1062c0fe, + 0xe0301612, + 0x98789862, + 0x8160657c, + 0x81409490, + 0xb0d89290, + 0xb1087100, + 0xb200a0d8, + 0xb003b480, + 0xb002b013, + 0xb0d0b012, + 0xb1007100, + 0x22f08140, + 0xc0f044eb, + 0x84509290, + 0x71009490, + 0x8460b100, + 0x71009490, + 0x8430b100, + 0x71009490, + 0x8440b100, + 0x81af9490, + 0x81e0651b, + 0x41072210, + 0x10606101, + 0xc00f1620, + 0x6909651b, + 0xc030a0d1, + 0xc0409760, + 0xb0f19780, + 0x7100b0c1, + 0xa0c1b0f1, + 0xa0037276, + 0x7220a002, + 0x061f6094, + 0x00f9306f, + 0x04411091, + 0x87da97c1, + 0x1091061a, + 0x97c10451, + 0x061b87db, + 0x14ba311b, + 0x147a3919, + 0x71006fa3, + 0x9493b100, + 0x7000929e, + 0xc1f0b0f8, + 0x78509400, + 0x721b9410, + 0x10768ab7, + 0x06773987, + 0x87d897c7, + 0x1e071618, + 0xc0064543, + 0x1e17614e, + 0xc0064547, + 0x1e37614e, + 0xc036454b, + 0x1e77614e, + 0xc3364492, + 0xb0066182, + 0xb004b016, + 0xb002b014, + 0x7810b012, + 0x90509030, + 0x90407820, + 0xb2059060, + 0xc0b0b072, + 0xb11693b0, + 0x7100b0e6, + 0xb107b073, + 0xa0e6b116, + 0xb88eb0d7, + 0xb1077100, + 0xb061b041, + 0x93b0c0f0, + 0x8964b88f, + 0x95543114, + 0x7100a044, + 0xb04db107, + 0xb074b06d, + 0x7100b201, + 0x7000b107, + 0x88409850, + 0x457d2200, + 0x7000b830, + 0x9867d040, + 0xe1d1657c, + 0x95a06f10, + 0xe1e1c100, + 0x6f13c622, + 0x16116e23, + 0x698b1612, + 0x41e41e07, + 0xb04f654f, + 0xc0f5b06f, + 0x65d4c004, + 0x85d0b5b0, + 0x1c543920, + 0x9190499e, + 0x81511614, + 0x41971e01, + 0x1c411621, + 0xa0d74d97, + 0x797f796e, + 0x95ff95ee, + 0xb5b01204, + 0x392085d0, + 0x1c541614, + 0x919041b3, + 0xa20561ab, + 0x657cc050, + 0xa0d4a0d7, + 0x72027206, + 0x72037204, + 0x73057204, + 0x73767306, + 0x60947276, + 0x12091070, + 0xb1077100, + 0x89b3b88d, + 0x3d833183, + 0x41cd2006, + 0x14390bf3, + 0x3c8969c4, + 0x3d391649, + 0x700006f9, + 0xc28a65c2, + 0x6fab149a, + 0x149ac38a, + 0xc18a6fac, + 0x149a65c2, + 0x14db6fad, + 0x95ec14dc, + 0x700095fb, + 0x657cc060, + 0xb04f654f, + 0xc0f5b06f, + 0x7100c004, + 0x7100b107, + 0x87fcb107, + 0x95ec880b, + 0xb5b095fb, + 0x392085d0, + 0x49f91c54, + 0x16149190, + 0x1e018151, + 0x162141eb, + 0x4deb1c41, + 0x796ea0d7, + 0x95ee797f, + 0x120495ff, + 0x85d0b5b0, + 0x16143920, + 0x420e1c54, + 0x62069190, + 0xc070a205, + 0xa0d7657c, + 0x7206a0d4, + 0x72047202, + 0x72047203, + 0x73067305, + 0x72767376, + 0x00016094, + 0x00080018, + 0x001a0003, + 0x002c000a, + 0x003e0011, + 0x00080003, + 0x001a0018, + 0x002c0011, + 0x003e000a}; PATCH_FUN_SPEC void rf_patch_mce_wb_dsss(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_wmbus_ctmode.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_wmbus_ctmode.h index 9e442d1..e39de59 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_wmbus_ctmode.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_wmbus_ctmode.h @@ -1,578 +1,577 @@ /****************************************************************************** -* Filename: rf_patch_mce_wmbus_ctmode.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 WMBUS C- and T-Mode -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_mce_wmbus_ctmode.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 WMBUS C- and T-Mode + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_MCE_WMBUS_CTMODE_H #define _RF_PATCH_MCE_WMBUS_CTMODE_H -#include #include "../inc/hw_types.h" +#include #ifndef MCE_PATCH_TYPE - #define MCE_PATCH_TYPE static const uint32_t +#define MCE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_MCERAM_BASE - #define RFC_MCERAM_BASE 0x21008000 +#define RFC_MCERAM_BASE 0x21008000 #endif #ifndef MCE_PATCH_MODE - #define MCE_PATCH_MODE 0 +#define MCE_PATCH_MODE 0 #endif MCE_PATCH_TYPE patchWmbusTmodeMce[512] = -{ - 0x2fcf60b3, - 0xff803f9d, - 0x02b30666, - 0x0fff00ff, - 0x5555003f, - 0x05140510, - 0x0004002a, - 0x00310018, - 0x00610047, - 0x0092007a, - 0x00ba00a8, - 0x00d000c7, - 0x00d600d4, - 0x001f0045, - 0x00e800f8, - 0x00c000d0, - 0x008800a8, - 0x00600078, - 0x00440057, - 0x00180031, - 0x00250004, - 0x05b205a2, - 0x05d305c3, - 0x05f405e3, - 0x06140604, - 0x06350625, - 0x06560646, - 0x06770666, - 0x06980687, - 0x06b806a8, - 0x06c906b8, - 0x06e906d9, - 0x070a06fa, - 0x0016071b, - 0x001c002c, - 0x000e0034, - 0x001a0026, - 0x000d0032, - 0x00190025, - 0x000b0031, - 0x00130023, - 0x00060029, - 0x0006000e, - 0x0002000e, - 0x00040008, - 0x0006000e, - 0x0006000a, - 0x0002000c, - 0x00040008, - 0x0006000c, - 0x0006000e, - 0x0002000e, - 0x0000000e, - 0x0006000e, - 0x0006000a, - 0x0002000e, - 0x0006000a, - 0x0007000e, - 0x0007000f, - 0x0003000d, - 0x00050009, - 0x0001000d, - 0x0007000f, - 0x0001000f, - 0x0005000f, - 0x0007000f, - 0x0007000b, - 0x0003000b, - 0x0007000b, - 0x0007000b, - 0x0007000f, - 0x0003000f, - 0x0007000f, - 0x0003000f, - 0x3d1f0007, - 0x00000000, - 0x000f0400, - 0x03840000, - 0x00f4000b, - 0x80000043, - 0x06702801, - 0x091e0000, - 0x00040514, - 0x02000000, - 0x00613e10, - 0x842f0000, - 0x007f177f, - 0xaaaaaaaa, - 0x2abcaaaa, - 0x72200000, - 0xa32d7248, - 0x73057303, - 0x73047203, - 0x72047306, - 0x72767376, - 0x8001c7c0, - 0x90010001, - 0x08019010, - 0x720c9001, - 0x720e720d, - 0x7100b0c0, - 0xa0c0b0f0, - 0x81327218, - 0x39521020, - 0x00200670, - 0x11011630, - 0x6c011401, - 0x60ea60e8, - 0x61a66152, - 0x60e860e8, - 0x60e960e8, - 0x72201210, - 0x7310730f, - 0x81817311, - 0x91800010, - 0x60c8b070, - 0x60de60de, - 0xc282c931, - 0x1820c470, - 0x6e236f13, - 0x16121611, - 0x72ad68ee, - 0xc5a0c482, - 0x40fc1820, - 0x6e231203, - 0x68f91612, - 0x816060de, - 0x81409490, - 0x2a703980, - 0x16111001, - 0x84448432, - 0xc0f5c0f3, - 0x1c01c200, - 0xc1004121, - 0x41171c10, - 0x10134d19, - 0x18301803, - 0x1a101a13, - 0x69143912, - 0x13f36121, - 0x13f36121, - 0xc1001015, - 0x1a151850, - 0x39141a10, - 0xb0d8691f, - 0xb1087100, - 0xb200a0d8, - 0xb003b480, - 0xb002b013, - 0x7229b012, - 0x7100b0d0, - 0x8140b100, - 0x71009290, - 0x8140b100, - 0x453122f0, - 0x1c0313f0, - 0x9293413d, - 0x71009492, - 0x9295b100, - 0x71009494, - 0xb0d0b100, - 0x7000a480, - 0xc030a0d1, - 0xc0409760, - 0xb0f19780, - 0x7100b0c1, - 0xa0c1b0f1, - 0xa0037276, - 0x7000a002, - 0x7310730f, - 0x39818ad1, - 0x06113961, - 0x9861d030, - 0xc10067f9, - 0x64fd91c0, - 0x22e08ad0, - 0xb4834587, - 0xb0c3b0f3, - 0xc030b484, - 0xb10191c0, - 0x8ad5b0d1, - 0x416d22d5, - 0x809012f5, - 0x45822230, - 0x085081a0, - 0x1401c431, - 0xc0636f12, - 0x417a2252, - 0x617b1211, - 0x92c113f1, - 0x7100b101, - 0x1a133112, - 0x616d4576, - 0xb101a0d1, - 0x6544a0c3, - 0xb0d060de, - 0xc070b480, - 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0x91b01300, + 0xb0f1b760, + 0x72767100, + 0xb0c6b0f6, + 0xa0c1b0f1, + 0x1a101200, + 0xc3809780, + 0xc2809760, + 0x80909760, + 0x44c82200, + 0x1e048154, + 0x978443b5, + 0x8790b0f6, + 0x1c018781, + 0x18014bcd, + 0x4bcb1ef1, + 0x1af18781, + 0x71009781, + 0x16f1b0f6, + 0xa2059781, + 0xb0f67100, + 0x6199a0c6, + 0xc2a1961d, + 0x141d16c1, + 0x101d6fd1, + 0x82e03151, + 0x14013980, + 0x83329721, + 0x06711021, + 0x06323952, + 0x16111421, + 0x43e5c1b0, + 0x97303010, + 0x6be71270, + 0x874092dd, + 0x875094a0, + 0x700094b0, + 0x1e0087e0, + 0x84a047f3, + 0x94a097e0, + 0x92d07840, + 0x94b07850, + 0x98507000, + 0x22008840, + 0xb83047fa, + 0x00007000}; PATCH_FUN_SPEC void rf_patch_mce_wmbus_ctmode(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_wmbus_smode.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_wmbus_smode.h index cd50c0c..24373b5 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_wmbus_smode.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_mce_wmbus_smode.h @@ -1,578 +1,577 @@ /****************************************************************************** -* Filename: rf_patch_mce_wmbus_smode.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 WMBUS S-Mode -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_mce_wmbus_smode.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 WMBUS S-Mode + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_MCE_WMBUS_SMODE_H #define _RF_PATCH_MCE_WMBUS_SMODE_H -#include #include "../inc/hw_types.h" +#include #ifndef MCE_PATCH_TYPE - #define MCE_PATCH_TYPE static const uint32_t +#define MCE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_MCERAM_BASE - #define RFC_MCERAM_BASE 0x21008000 +#define RFC_MCERAM_BASE 0x21008000 #endif #ifndef MCE_PATCH_MODE - #define MCE_PATCH_MODE 0 +#define MCE_PATCH_MODE 0 #endif MCE_PATCH_TYPE patchWmbusSmodeMce[512] = -{ - 0x2fcf602e, - 0x030c3f9d, - 0x070c680a, - 0xff00003f, - 0x00000014, - 0x00000000, - 0x00000000, - 0x00070003, - 0x00003d1f, - 0x04000000, - 0x0000000f, - 0x000b0387, - 0x004340f4, - 0x80828000, - 0x00000670, - 0x0510091e, - 0x00050004, - 0x3e100200, - 0x00000061, - 0x3030002f, - 0x0000027f, - 0x00000000, - 0x0000aa00, - 0x72487220, - 0x7303a32d, - 0x72037305, - 0x73067304, - 0x73767204, - 0xc7c07276, - 0x00018001, - 0x90109001, - 0x90010801, - 0x720d720c, - 0xb0c0720e, - 0xb0f07100, - 0x7218a0c0, - 0x10208132, - 0x06703952, - 0x16300020, - 0x14011101, - 0x60636c01, - 0x60d76066, - 0x606362f6, - 0x60636063, - 0x12106064, - 0x730f7220, - 0x73117310, - 0x00108181, - 0xb0709180, - 0x60596043, - 0x605967ef, - 0x6791c030, - 0xc282c0e1, - 0x1820c470, - 0x6e236f13, - 0x16121611, - 0x7830686c, - 0x78409ab0, - 0x78509ac0, - 0x83009ad0, - 0xc4829ae0, - 0x1820c5a0, - 0x12034081, - 0x16126e23, - 0x6059687e, - 0x94908160, - 0x39808140, - 0x10012a70, - 0x84321611, - 0xc0f38444, - 0xc200c0f5, - 0x40a61c01, - 0x1c10c100, - 0x4c9e409c, - 0x18031013, - 0x1a131830, - 0x39121a10, - 0x60a66899, - 0x60a613f3, - 0x101513f3, - 0x1850c100, - 0x1a101a15, - 0x68a43914, - 0x7100b0d8, - 0xa0d8b108, - 0xb480b200, - 0xb013b003, - 0xb012b002, - 0xb0d07229, - 0xb1007100, - 0x92908140, - 0xb1007100, - 0x22f08140, - 0x13f044b6, - 0x40c21c03, - 0x94929293, - 0xb1007100, - 0x94949295, - 0xb1007100, - 0xa480b0d0, - 0xa0d17000, - 0x9760c030, - 0x9780c040, - 0xb0c1b0f1, - 0xb0f17100, - 0x7276a0c1, - 0xa002a003, - 0x730f7000, - 0xc0407310, - 0xc1006791, - 0x648291c0, - 0xb0f3b483, - 0xb484b0c3, - 0x91c0c000, - 0xb0d1b101, - 0x39858ad5, - 0x06153955, - 0x22308090, - 0x81a044ff, - 0x06100850, - 0x13f040f4, - 0x60f61211, - 0x13f11210, - 0x101b100a, - 0xb10192c0, - 0x92c17100, - 0x7100b101, - 0xa0d160ea, - 0xa0c3b101, - 0x605964c9, - 0xb016b006, - 0xb014b004, - 0xb012b002, - 0x78628400, - 0x81430420, - 0x2a733983, - 0xc1f29473, - 0x31621832, - 0x31511021, - 0x00200012, - 0x10309400, - 0x39301610, - 0x411f2210, - 0x31501220, - 0x31801003, - 0x93501630, - 0x12041202, - 0x41312273, - 0x97c08430, - 0x1a8287d2, - 0x97c08450, - 0x1a8487d4, - 0x22636133, - 0x8440413e, - 0x87d097c0, - 0x14021a80, - 0x97c08460, - 0x1a8087d0, - 0x614a1404, - 0x78718440, - 0x97c00410, - 0x1a4287d2, - 0x78718460, - 0x97c00410, - 0x1a4487d4, - 0x31543152, - 0x06333963, - 0x38321613, - 0x31823834, - 0x31843982, - 0x95720042, - 0x90307810, - 0x78209050, - 0x90609040, - 0x8ae2b205, - 0x93028303, - 0x9862e050, - 0x67919873, - 0xc00bc00c, - 0x31808140, - 0x39403980, - 0xc0f38141, - 0xc0140431, - 0xc0021441, - 0x69701412, - 0x847d3122, - 0x140dc010, - 0x142d312d, - 0x318e8ace, - 0x397e311e, - 0x31498ac9, - 0x39493979, - 0x109a3129, - 0xa04eb072, - 0xb011b06e, - 0x978ab06c, - 0xb7647276, - 0xc662a764, - 0xc04f9762, - 0x6677c028, - 0x22f18ab1, - 0x8ad14597, - 0x459722f1, - 0x710061f0, - 0xb760b073, - 0x220780b7, - 0xa76045ce, - 0x22f18ab1, - 0x223741a8, - 0xb11341a8, - 0x223080b0, - 0x61b645a3, - 0x41bb22e1, - 0x22508090, - 0xb0f541bb, - 0x22208210, - 0x97894197, - 0xa764b764, - 0x6197b0f6, - 0xb764978d, - 0xb0f6a764, - 0x8ad06197, - 0x41c722f0, - 0x41c72237, - 0xb113b075, - 0x223080b0, - 0xb08745c1, - 0x22d16197, - 0x809042ba, - 0x42ba2220, - 0x6197663a, - 0xa0e0978f, - 0xa0c2a0e3, - 0xb0f1a0c5, - 0xa0c6b0c1, - 0x97887100, - 0xb88fb0f1, - 0x85708961, - 0x95511801, - 0x8a718a60, - 0xa487a488, - 0x22e08ad0, - 0x821041e8, - 0x45822220, - 0xb04e7100, - 0xb074b06e, - 0x8a73b201, - 0x70008552, - 0xb0737100, - 0x80b7b760, - 0x460f2207, - 0x46252237, - 0x8ab1a760, - 0x420822e1, - 0x22508090, - 0xb0f54208, - 0x22208210, - 0x978d41f0, - 0xa764b764, - 0x61f0b0f6, - 0x42ba22d1, - 0x22208090, - 0x663a42ba, - 0x978f61f0, - 0xa0e3a0e0, - 0xa0c5a0c2, - 0xb0c1b0f1, - 0x7100a0c6, - 0xb0f19788, - 0x8961b88f, - 0x31808570, - 0x18013d80, - 0x8a609551, - 0xa1828a71, - 0x978f61e0, - 0xa0e3a0e0, - 0xa0c5a0c2, - 0xb0c1b0f1, - 0x7100a0c6, - 0xb0f19788, - 0x8961b88f, - 0x3d808570, - 0x95511801, - 0x8a918a80, - 0x61e0b182, - 0x22b08ab0, - 0x1e3b4640, - 0x62424675, - 0x46751e7b, - 0xb889c00b, - 0x31808940, - 0x16403d80, - 0x140c3d30, - 0x220080b0, - 0x7000424e, - 0x39838ab3, - 0x8ab106f3, - 0x0401cff0, - 0x1c1c3031, - 0x12004e6d, - 0x1c0c1810, - 0x80b04a6f, - 0x425f2200, - 0x10c27000, - 0x3c321612, - 0x83208ae1, - 0x42712210, - 0x93016273, - 0x9861d060, - 0xb0f26791, - 0x101c7000, - 0x100c625b, - 0x1821625b, - 0x14216267, - 0x161b6267, - 0xb0f6626b, - 0xb110b0f1, - 0xb0f5b113, - 0x720cb0f2, - 0x720e720d, - 0xb0e3b0e0, - 0x22f28ab2, - 0xb0c64288, - 0x628bb763, - 0x22f08ad0, - 0xb40542ab, - 0xb428a404, - 0xcaa0a429, - 0xcaa13180, - 0x94510001, - 0x8ad39461, - 0x39833183, - 0x31808410, - 0x31833980, - 0x94100030, - 0x31508400, - 0x8ad33950, - 0x06f33983, - 0x1834c1f4, - 0x31343184, - 0x94000040, - 0x22e2b089, - 0x8aca42b5, - 0x398a394a, - 0x978a312a, - 0xb0c6b0c5, - 0x8ab2b763, - 0x42b922d2, - 0x7000b0c2, - 0xa0e0b20f, - 0x978ea0e3, - 0xa764b764, - 0xb110b0f6, - 0x8210b113, - 0x42c322f0, - 0x8002b0f5, - 0xa006a004, - 0x7203a001, - 0xc0707204, - 0x71006791, - 0xb0f6b764, - 0xa20fb0c5, - 0xb0f57100, - 0x7810a0c5, - 0x90029030, - 0x90407820, - 0xb0729060, - 0x6677a20f, - 0xa764978a, - 0x6190b0f6, - 0x8180b88c, - 0x392489a4, - 0x00043184, - 0xc0809184, - 0x73766791, - 0x72487276, - 0x72027206, - 0x73057204, - 0x60597306, - 0x91b01200, - 0xc090b32d, - 0xb0f86791, - 0xb0f16504, - 0xb88eb0c1, - 0xe0a08a73, - 0x98729863, - 0x71006791, - 0xb0f1a0c1, - 0xb0c2b0f2, - 0x120ac00f, - 0x1a1f120f, - 0x12031204, - 0x39888ad8, - 0x06183958, - 0xb0f27100, - 0x8b10b88d, - 0x3d803180, - 0x6320100b, - 0x121a120b, - 0x16131a14, - 0xb0f27100, - 0x8b10b88d, - 0x3d803180, - 0x7100140b, - 0xb88db0f2, - 0x31808b10, - 0x140b3d80, - 0x7100100d, - 0xb88db0f2, - 0x31808b10, - 0x140b3d80, - 0x100c140d, - 0x4f3d22fd, - 0x120d10d0, - 0x7100180d, - 0xb88db0f2, - 0x31808b10, - 0x180b3d80, - 0x100e140c, - 0x4f4b22fc, - 0x120c10c0, - 0x7100180c, - 0xb88db0f2, - 0x31808b10, - 0x180b3d80, - 0x22fe140e, - 0x10e04f58, - 0x180e120e, - 0xb0f27100, - 0x8b10b88d, - 0x3d803180, - 0x7100180b, - 0xb88db0f2, - 0x31808b10, - 0x180b3d80, - 0x398b10b6, - 0x088b397b, - 0x161f919b, - 0x1e008150, - 0x1a104373, - 0x4f731cf0, - 0x6785637e, - 0x437d1e1a, - 0x431c1e4a, - 0xb0f27100, - 0x1614121a, - 0x63141613, - 0x9863e0b0, - 0x67919874, - 0xb0f2a0c2, - 0xc01a62e4, - 0x140d7880, - 0x1cec140e, - 0xc03a4b8d, - 0x1cdc10ec, - 0xc04a4b90, - 0x98507000, - 0x22008840, - 0xb8304792, - 0x00007000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xc1020000, - 0xc0013162, - 0x1e008150, - 0x1a1043f7, - 0x102063f9, - 0x6f131a10, - 0x16116e23, - 0x6bf91612, - 0x00007000 -}; + { + 0x2fcf602e, + 0x030c3f9d, + 0x070c680a, + 0xff00003f, + 0x00000014, + 0x00000000, + 0x00000000, + 0x00070003, + 0x00003d1f, + 0x04000000, + 0x0000000f, + 0x000b0387, + 0x004340f4, + 0x80828000, + 0x00000670, + 0x0510091e, + 0x00050004, + 0x3e100200, + 0x00000061, + 0x3030002f, + 0x0000027f, + 0x00000000, + 0x0000aa00, + 0x72487220, + 0x7303a32d, + 0x72037305, + 0x73067304, + 0x73767204, + 0xc7c07276, + 0x00018001, + 0x90109001, + 0x90010801, + 0x720d720c, + 0xb0c0720e, + 0xb0f07100, + 0x7218a0c0, + 0x10208132, + 0x06703952, + 0x16300020, + 0x14011101, + 0x60636c01, + 0x60d76066, + 0x606362f6, + 0x60636063, + 0x12106064, + 0x730f7220, + 0x73117310, + 0x00108181, + 0xb0709180, + 0x60596043, + 0x605967ef, + 0x6791c030, + 0xc282c0e1, + 0x1820c470, + 0x6e236f13, + 0x16121611, + 0x7830686c, + 0x78409ab0, + 0x78509ac0, + 0x83009ad0, + 0xc4829ae0, + 0x1820c5a0, + 0x12034081, + 0x16126e23, + 0x6059687e, + 0x94908160, + 0x39808140, + 0x10012a70, + 0x84321611, + 0xc0f38444, + 0xc200c0f5, + 0x40a61c01, + 0x1c10c100, + 0x4c9e409c, + 0x18031013, + 0x1a131830, + 0x39121a10, + 0x60a66899, + 0x60a613f3, + 0x101513f3, + 0x1850c100, + 0x1a101a15, + 0x68a43914, + 0x7100b0d8, + 0xa0d8b108, + 0xb480b200, + 0xb013b003, + 0xb012b002, + 0xb0d07229, + 0xb1007100, + 0x92908140, + 0xb1007100, + 0x22f08140, + 0x13f044b6, + 0x40c21c03, + 0x94929293, + 0xb1007100, + 0x94949295, + 0xb1007100, + 0xa480b0d0, + 0xa0d17000, + 0x9760c030, + 0x9780c040, + 0xb0c1b0f1, + 0xb0f17100, + 0x7276a0c1, + 0xa002a003, + 0x730f7000, + 0xc0407310, + 0xc1006791, + 0x648291c0, + 0xb0f3b483, + 0xb484b0c3, + 0x91c0c000, + 0xb0d1b101, + 0x39858ad5, + 0x06153955, + 0x22308090, + 0x81a044ff, + 0x06100850, + 0x13f040f4, + 0x60f61211, + 0x13f11210, + 0x101b100a, + 0xb10192c0, + 0x92c17100, + 0x7100b101, + 0xa0d160ea, + 0xa0c3b101, + 0x605964c9, + 0xb016b006, + 0xb014b004, + 0xb012b002, + 0x78628400, + 0x81430420, + 0x2a733983, + 0xc1f29473, + 0x31621832, + 0x31511021, + 0x00200012, + 0x10309400, + 0x39301610, + 0x411f2210, + 0x31501220, + 0x31801003, + 0x93501630, + 0x12041202, + 0x41312273, + 0x97c08430, + 0x1a8287d2, + 0x97c08450, + 0x1a8487d4, + 0x22636133, + 0x8440413e, + 0x87d097c0, + 0x14021a80, + 0x97c08460, + 0x1a8087d0, + 0x614a1404, + 0x78718440, + 0x97c00410, + 0x1a4287d2, + 0x78718460, + 0x97c00410, + 0x1a4487d4, + 0x31543152, + 0x06333963, + 0x38321613, + 0x31823834, + 0x31843982, + 0x95720042, + 0x90307810, + 0x78209050, + 0x90609040, + 0x8ae2b205, + 0x93028303, + 0x9862e050, + 0x67919873, + 0xc00bc00c, + 0x31808140, + 0x39403980, + 0xc0f38141, + 0xc0140431, + 0xc0021441, + 0x69701412, + 0x847d3122, + 0x140dc010, + 0x142d312d, + 0x318e8ace, + 0x397e311e, + 0x31498ac9, + 0x39493979, + 0x109a3129, + 0xa04eb072, + 0xb011b06e, + 0x978ab06c, + 0xb7647276, + 0xc662a764, + 0xc04f9762, + 0x6677c028, + 0x22f18ab1, + 0x8ad14597, + 0x459722f1, + 0x710061f0, + 0xb760b073, + 0x220780b7, + 0xa76045ce, + 0x22f18ab1, + 0x223741a8, + 0xb11341a8, + 0x223080b0, + 0x61b645a3, + 0x41bb22e1, + 0x22508090, + 0xb0f541bb, + 0x22208210, + 0x97894197, + 0xa764b764, + 0x6197b0f6, + 0xb764978d, + 0xb0f6a764, + 0x8ad06197, + 0x41c722f0, + 0x41c72237, + 0xb113b075, + 0x223080b0, + 0xb08745c1, + 0x22d16197, + 0x809042ba, + 0x42ba2220, + 0x6197663a, + 0xa0e0978f, + 0xa0c2a0e3, + 0xb0f1a0c5, + 0xa0c6b0c1, + 0x97887100, + 0xb88fb0f1, + 0x85708961, + 0x95511801, + 0x8a718a60, + 0xa487a488, + 0x22e08ad0, + 0x821041e8, + 0x45822220, + 0xb04e7100, + 0xb074b06e, + 0x8a73b201, + 0x70008552, + 0xb0737100, + 0x80b7b760, + 0x460f2207, + 0x46252237, + 0x8ab1a760, + 0x420822e1, + 0x22508090, + 0xb0f54208, + 0x22208210, + 0x978d41f0, + 0xa764b764, + 0x61f0b0f6, + 0x42ba22d1, + 0x22208090, + 0x663a42ba, + 0x978f61f0, + 0xa0e3a0e0, + 0xa0c5a0c2, + 0xb0c1b0f1, + 0x7100a0c6, + 0xb0f19788, + 0x8961b88f, + 0x31808570, + 0x18013d80, + 0x8a609551, + 0xa1828a71, + 0x978f61e0, + 0xa0e3a0e0, + 0xa0c5a0c2, + 0xb0c1b0f1, + 0x7100a0c6, + 0xb0f19788, + 0x8961b88f, + 0x3d808570, + 0x95511801, + 0x8a918a80, + 0x61e0b182, + 0x22b08ab0, + 0x1e3b4640, + 0x62424675, + 0x46751e7b, + 0xb889c00b, + 0x31808940, + 0x16403d80, + 0x140c3d30, + 0x220080b0, + 0x7000424e, + 0x39838ab3, + 0x8ab106f3, + 0x0401cff0, + 0x1c1c3031, + 0x12004e6d, + 0x1c0c1810, + 0x80b04a6f, + 0x425f2200, + 0x10c27000, + 0x3c321612, + 0x83208ae1, + 0x42712210, + 0x93016273, + 0x9861d060, + 0xb0f26791, + 0x101c7000, + 0x100c625b, + 0x1821625b, + 0x14216267, + 0x161b6267, + 0xb0f6626b, + 0xb110b0f1, + 0xb0f5b113, + 0x720cb0f2, + 0x720e720d, + 0xb0e3b0e0, + 0x22f28ab2, + 0xb0c64288, + 0x628bb763, + 0x22f08ad0, + 0xb40542ab, + 0xb428a404, + 0xcaa0a429, + 0xcaa13180, + 0x94510001, + 0x8ad39461, + 0x39833183, + 0x31808410, + 0x31833980, + 0x94100030, + 0x31508400, + 0x8ad33950, + 0x06f33983, + 0x1834c1f4, + 0x31343184, + 0x94000040, + 0x22e2b089, + 0x8aca42b5, + 0x398a394a, + 0x978a312a, + 0xb0c6b0c5, + 0x8ab2b763, + 0x42b922d2, + 0x7000b0c2, + 0xa0e0b20f, + 0x978ea0e3, + 0xa764b764, + 0xb110b0f6, + 0x8210b113, + 0x42c322f0, + 0x8002b0f5, + 0xa006a004, + 0x7203a001, + 0xc0707204, + 0x71006791, + 0xb0f6b764, + 0xa20fb0c5, + 0xb0f57100, + 0x7810a0c5, + 0x90029030, + 0x90407820, + 0xb0729060, + 0x6677a20f, + 0xa764978a, + 0x6190b0f6, + 0x8180b88c, + 0x392489a4, + 0x00043184, + 0xc0809184, + 0x73766791, + 0x72487276, + 0x72027206, + 0x73057204, + 0x60597306, + 0x91b01200, + 0xc090b32d, + 0xb0f86791, + 0xb0f16504, + 0xb88eb0c1, + 0xe0a08a73, + 0x98729863, + 0x71006791, + 0xb0f1a0c1, + 0xb0c2b0f2, + 0x120ac00f, + 0x1a1f120f, + 0x12031204, + 0x39888ad8, + 0x06183958, + 0xb0f27100, + 0x8b10b88d, + 0x3d803180, + 0x6320100b, + 0x121a120b, + 0x16131a14, + 0xb0f27100, + 0x8b10b88d, + 0x3d803180, + 0x7100140b, + 0xb88db0f2, + 0x31808b10, + 0x140b3d80, + 0x7100100d, + 0xb88db0f2, + 0x31808b10, + 0x140b3d80, + 0x100c140d, + 0x4f3d22fd, + 0x120d10d0, + 0x7100180d, + 0xb88db0f2, + 0x31808b10, + 0x180b3d80, + 0x100e140c, + 0x4f4b22fc, + 0x120c10c0, + 0x7100180c, + 0xb88db0f2, + 0x31808b10, + 0x180b3d80, + 0x22fe140e, + 0x10e04f58, + 0x180e120e, + 0xb0f27100, + 0x8b10b88d, + 0x3d803180, + 0x7100180b, + 0xb88db0f2, + 0x31808b10, + 0x180b3d80, + 0x398b10b6, + 0x088b397b, + 0x161f919b, + 0x1e008150, + 0x1a104373, + 0x4f731cf0, + 0x6785637e, + 0x437d1e1a, + 0x431c1e4a, + 0xb0f27100, + 0x1614121a, + 0x63141613, + 0x9863e0b0, + 0x67919874, + 0xb0f2a0c2, + 0xc01a62e4, + 0x140d7880, + 0x1cec140e, + 0xc03a4b8d, + 0x1cdc10ec, + 0xc04a4b90, + 0x98507000, + 0x22008840, + 0xb8304792, + 0x00007000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc1020000, + 0xc0013162, + 0x1e008150, + 0x1a1043f7, + 0x102063f9, + 0x6f131a10, + 0x16116e23, + 0x6bf91612, + 0x00007000}; PATCH_FUN_SPEC void rf_patch_mce_wmbus_smode(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_ble.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_ble.h index 6b51169..f551c5b 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_ble.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_ble.h @@ -1,378 +1,376 @@ /****************************************************************************** -* Filename: rf_patch_rfe_ble.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC1350 Bluetooth Low Energy -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - + * Filename: rf_patch_rfe_ble.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC1350 Bluetooth Low Energy + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_RFE_BLE_H #define _RF_PATCH_RFE_BLE_H -#include #include "../inc/hw_types.h" +#include #ifndef RFE_PATCH_TYPE - #define RFE_PATCH_TYPE static const uint32_t +#define RFE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_RFERAM_BASE - #define RFC_RFERAM_BASE 0x2100C000 +#define RFC_RFERAM_BASE 0x2100C000 #endif #ifndef RFE_PATCH_MODE - #define RFE_PATCH_MODE 0 +#define RFE_PATCH_MODE 0 #endif RFE_PATCH_TYPE patchBleRfe[311] = -{ - 0x0000612c, - 0x0002147f, - 0x00050006, - 0x0008000f, - 0x00520048, - 0x003fff80, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x43cf41cf, - 0x4fcf47cf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x00000000, - 0x00000000, - 0x000f0000, - 0x00000008, - 0x0000003f, - 0x003f0040, - 0x00040000, - 0x000e0068, - 0x000600dc, - 0x001a0043, - 0x00000005, - 0x00020000, - 0x003f0000, - 0x00000000, - 0x00c00004, - 0x00040000, - 0x000000c0, - 0x00000007, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x9100c050, - 0xc0707000, - 0x70009100, - 0x00213182, - 0xb1109131, - 0x81017000, - 0xa100b101, - 0x91323182, - 0x9101b110, - 0x81411011, - 0x40632241, - 0x700006f1, - 0x9101c051, - 0x39101830, - 0xd0083183, - 0x6f413118, - 0x91310031, - 0x1483b110, - 0x686f1614, - 0x10257000, - 0x9100c050, - 0xc140c3f4, - 0x6f031420, - 0x04411031, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0x04411031, - 0x3182c082, - 0x91310021, - 0x3963b110, - 0xc0a21031, - 0x00213182, - 0xb1109131, - 0x31151050, - 0x92051405, - 0x64537000, - 0x1031c052, - 0x31610631, - 0x645602c1, - 0x1031c112, - 0x06713921, - 0x02e13151, - 0x70006456, - 0x9101c051, - 0xc0e2cc01, - 0x64536456, - 0xc0c2c111, - 0xb0546456, - 0xa0547100, - 0x80f0b064, - 0x40b12200, - 0x90b01240, - 0xc2f0b032, - 0xc11168bc, - 0x6456c122, - 0x68c1c0b0, - 0x9101c051, - 0x3182c0e2, - 0x00028260, - 0xb1109132, - 0x68cbc230, - 0x00000000, - 0x12800000, - 0xb03290b0, - 0x64537000, - 0xc122c101, - 0xc1016456, - 0x6456c0c2, - 0x64998253, - 0x90b012c0, - 0x7000b032, - 0xc2726453, - 0x6456c081, - 0xc111c122, - 0xc0026456, - 0x6456c111, - 0xc331c062, - 0xc3626456, - 0x6456c111, - 0xc111c302, - 0x82536456, - 0x64993953, - 0x645bc3e2, - 0x40f62211, - 0xc881c242, - 0xc2526456, - 0x6456c111, - 0xcee1c272, - 0xc2026456, - 0x6456c881, - 0xc801c202, - 0xc0b06456, - 0x7000690a, - 0xc2426453, - 0x6456c801, - 0xc011c252, - 0xc2726456, - 0x6456c0e1, - 0xc101c002, - 0xc0626456, - 0x6456c301, - 0xc101c122, - 0xc3626456, - 0x6456c101, - 0xc101c302, - 0x82536456, - 0x70006499, - 0x00000000, - 0x00000000, - 0x72057306, - 0x720e720b, - 0x7100b050, - 0xb0608081, - 0x8092a050, - 0x92f1eff0, - 0x664f9302, - 0x45502241, - 0xc1f18080, - 0x16300410, - 0x14011101, - 0x61636c01, - 0x61656164, - 0x61676166, - 0x61696168, - 0x616d616b, - 0x6171616f, - 0x624c6249, - 0xc0f28091, - 0x31210421, - 0x2a428082, - 0x16321412, - 0x14211101, - 0x617e6c01, - 0x618461a0, - 0x617e624c, - 0x618461a0, - 0x6173624c, - 0x61736173, - 0x61736173, - 0x64a86173, - 0x64d36173, - 0x64e06173, - 0x650c6173, - 0x66596173, - 0x80826173, - 0x92f2dfe0, - 0xb0b0664f, - 0xb0b1617a, - 0x72057306, - 0x6130b030, - 0x664fcfd0, - 0xc003c284, - 0x6468c3c0, - 0x91507890, - 0x31107860, - 0x14107861, - 0x78509200, - 0x78613140, - 0x31400010, - 0x00107871, - 0x78b09210, - 0x78819260, - 0x78309221, - 0x78413140, - 0x92300010, - 0x91f0c010, - 0x61736655, - 0x80f0a054, - 0x45a82250, - 0x22008040, - 0x61a0463f, - 0x9160c800, - 0xb0508159, - 0x22418091, - 0xcfc04607, - 0x8212664f, - 0x39823182, - 0x10283942, - 0x82126477, - 0x041212f1, - 0x311f102f, - 0xc140142f, - 0x6f0d1420, - 0x10de396d, - 0x044ec3f4, - 0x3182c082, - 0x396d002e, - 0x3182c0a2, - 0x821a002d, - 0x8220398a, - 0x39803180, - 0x180bc00b, - 0x823078ac, - 0x10023940, - 0x3001c011, - 0x1801c010, - 0x31821802, - 0x26c10021, - 0xb0039191, - 0xb063b013, - 0x8203b053, - 0x80411439, - 0x463f2201, - 0x91c481b4, - 0x189581d5, - 0x4df51cb5, - 0x4a2d1cc5, - 0x80f09165, - 0x41e52210, - 0x913d6205, - 0x913eb110, - 0x9165b110, - 0x8159920f, - 0x18ab14f9, - 0x80f010bc, - 0x41a02250, - 0x46052210, - 0xcfb061e5, - 0xb063664f, - 0x10008230, - 0x0420c0f2, - 0xc0111002, - 0xc0103001, - 0x18021801, - 0x00213182, - 0x919126c1, - 0xb0139191, - 0xb063b003, - 0xb064b053, - 0x7100b054, - 0x22018041, - 0xb063463f, - 0x80f0b064, - 0x41a02250, - 0x91c181b1, - 0x189181d1, - 0xb0319161, - 0x8212621d, - 0x39823182, - 0x10283942, - 0x81596477, - 0x14598205, - 0xc00b8220, - 0x78ac180b, - 0x7100c080, - 0x6a3bb063, - 0x820161e5, - 0x31828162, - 0xefa03d82, - 0x930292f1, - 0xa003664f, - 0x80a26173, - 0x61736477, - 0x7100b050, - 0x92e06173, - 0x220082d0, - 0xb2c04650, - 0x80a07000, - 0x426c22f0, - 0xc102b030, - 0xc0013162, - 0x1e0080a0, - 0x22f04265, - 0xe6d04266, - 0x39603160, - 0x10206266, - 0x6f131a10, - 0x16116e23, - 0x6a671612, - 0x00007000 -}; + { + 0x0000612c, + 0x0002147f, + 0x00050006, + 0x0008000f, + 0x00520048, + 0x003fff80, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x00000000, + 0x000f0000, + 0x00000008, + 0x0000003f, + 0x003f0040, + 0x00040000, + 0x000e0068, + 0x000600dc, + 0x001a0043, + 0x00000005, + 0x00020000, + 0x003f0000, + 0x00000000, + 0x00c00004, + 0x00040000, + 0x000000c0, + 0x00000007, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x40632241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x686f1614, + 0x10257000, + 0x9100c050, + 0xc140c3f4, + 0x6f031420, + 0x04411031, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x64537000, + 0x1031c052, + 0x31610631, + 0x645602c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006456, + 0x9101c051, + 0xc0e2cc01, + 0x64536456, + 0xc0c2c111, + 0xb0546456, + 0xa0547100, + 0x80f0b064, + 0x40b12200, + 0x90b01240, + 0xc2f0b032, + 0xc11168bc, + 0x6456c122, + 0x68c1c0b0, + 0x9101c051, + 0x3182c0e2, + 0x00028260, + 0xb1109132, + 0x68cbc230, + 0x00000000, + 0x12800000, + 0xb03290b0, + 0x64537000, + 0xc122c101, + 0xc1016456, + 0x6456c0c2, + 0x64998253, + 0x90b012c0, + 0x7000b032, + 0xc2726453, + 0x6456c081, + 0xc111c122, + 0xc0026456, + 0x6456c111, + 0xc331c062, + 0xc3626456, + 0x6456c111, + 0xc111c302, + 0x82536456, + 0x64993953, + 0x645bc3e2, + 0x40f62211, + 0xc881c242, + 0xc2526456, + 0x6456c111, + 0xcee1c272, + 0xc2026456, + 0x6456c881, + 0xc801c202, + 0xc0b06456, + 0x7000690a, + 0xc2426453, + 0x6456c801, + 0xc011c252, + 0xc2726456, + 0x6456c0e1, + 0xc101c002, + 0xc0626456, + 0x6456c301, + 0xc101c122, + 0xc3626456, + 0x6456c101, + 0xc101c302, + 0x82536456, + 0x70006499, + 0x00000000, + 0x00000000, + 0x72057306, + 0x720e720b, + 0x7100b050, + 0xb0608081, + 0x8092a050, + 0x92f1eff0, + 0x664f9302, + 0x45502241, + 0xc1f18080, + 0x16300410, + 0x14011101, + 0x61636c01, + 0x61656164, + 0x61676166, + 0x61696168, + 0x616d616b, + 0x6171616f, + 0x624c6249, + 0xc0f28091, + 0x31210421, + 0x2a428082, + 0x16321412, + 0x14211101, + 0x617e6c01, + 0x618461a0, + 0x617e624c, + 0x618461a0, + 0x6173624c, + 0x61736173, + 0x61736173, + 0x64a86173, + 0x64d36173, + 0x64e06173, + 0x650c6173, + 0x66596173, + 0x80826173, + 0x92f2dfe0, + 0xb0b0664f, + 0xb0b1617a, + 0x72057306, + 0x6130b030, + 0x664fcfd0, + 0xc003c284, + 0x6468c3c0, + 0x91507890, + 0x31107860, + 0x14107861, + 0x78509200, + 0x78613140, + 0x31400010, + 0x00107871, + 0x78b09210, + 0x78819260, + 0x78309221, + 0x78413140, + 0x92300010, + 0x91f0c010, + 0x61736655, + 0x80f0a054, + 0x45a82250, + 0x22008040, + 0x61a0463f, + 0x9160c800, + 0xb0508159, + 0x22418091, + 0xcfc04607, + 0x8212664f, + 0x39823182, + 0x10283942, + 0x82126477, + 0x041212f1, + 0x311f102f, + 0xc140142f, + 0x6f0d1420, + 0x10de396d, + 0x044ec3f4, + 0x3182c082, + 0x396d002e, + 0x3182c0a2, + 0x821a002d, + 0x8220398a, + 0x39803180, + 0x180bc00b, + 0x823078ac, + 0x10023940, + 0x3001c011, + 0x1801c010, + 0x31821802, + 0x26c10021, + 0xb0039191, + 0xb063b013, + 0x8203b053, + 0x80411439, + 0x463f2201, + 0x91c481b4, + 0x189581d5, + 0x4df51cb5, + 0x4a2d1cc5, + 0x80f09165, + 0x41e52210, + 0x913d6205, + 0x913eb110, + 0x9165b110, + 0x8159920f, + 0x18ab14f9, + 0x80f010bc, + 0x41a02250, + 0x46052210, + 0xcfb061e5, + 0xb063664f, + 0x10008230, + 0x0420c0f2, + 0xc0111002, + 0xc0103001, + 0x18021801, + 0x00213182, + 0x919126c1, + 0xb0139191, + 0xb063b003, + 0xb064b053, + 0x7100b054, + 0x22018041, + 0xb063463f, + 0x80f0b064, + 0x41a02250, + 0x91c181b1, + 0x189181d1, + 0xb0319161, + 0x8212621d, + 0x39823182, + 0x10283942, + 0x81596477, + 0x14598205, + 0xc00b8220, + 0x78ac180b, + 0x7100c080, + 0x6a3bb063, + 0x820161e5, + 0x31828162, + 0xefa03d82, + 0x930292f1, + 0xa003664f, + 0x80a26173, + 0x61736477, + 0x7100b050, + 0x92e06173, + 0x220082d0, + 0xb2c04650, + 0x80a07000, + 0x426c22f0, + 0xc102b030, + 0xc0013162, + 0x1e0080a0, + 0x22f04265, + 0xe6d04266, + 0x39603160, + 0x10206266, + 0x6f131a10, + 0x16116e23, + 0x6a671612, + 0x00007000}; PATCH_FUN_SPEC void rf_patch_rfe_ble(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_brepeat.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_brepeat.h index e42627a..c89ede1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_brepeat.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_brepeat.h @@ -1,496 +1,494 @@ /****************************************************************************** -* Filename: rf_patch_rfe_brepeat.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 for 1.2kbps and 2.4kbps Generic FSK -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - + * Filename: rf_patch_rfe_brepeat.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 for 1.2kbps and 2.4kbps Generic FSK + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_RFE_BREPEAT_H #define _RF_PATCH_RFE_BREPEAT_H -#include #include "../inc/hw_types.h" +#include #ifndef RFE_PATCH_TYPE - #define RFE_PATCH_TYPE static const uint32_t +#define RFE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_RFERAM_BASE - #define RFC_RFERAM_BASE 0x2100C000 +#define RFC_RFERAM_BASE 0x2100C000 #endif #ifndef RFE_PATCH_MODE - #define RFE_PATCH_MODE 0 +#define RFE_PATCH_MODE 0 #endif RFE_PATCH_TYPE patchBrepeatRfe[429] = -{ - 0x000061a3, - 0x1307147f, - 0x24f1004d, - 0x3f131f2e, - 0x003f0ab0, - 0x0000ff07, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x43cf41cf, - 0x4fcf47cf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x00000000, - 0x0008000f, - 0x003f0000, - 0x00400000, - 0x0000003f, - 0x00680004, - 0x00dc000e, - 0x00430006, - 0x0005001a, - 0x00000000, - 0x00000002, - 0x0000003f, - 0x00040000, - 0x000000c0, - 0x00c00004, - 0x00070000, - 0x9100c050, - 0xc0707000, - 0x70009100, - 0x00213182, - 0xb1109131, - 0x81017000, - 0xa100b101, - 0x91323182, - 0x9101b110, - 0x81411011, - 0x404f2241, - 0x700006f1, - 0x9101c051, - 0x39101830, - 0xd0083183, - 0x6f413118, - 0x91310031, - 0x1483b110, - 0x685b1614, - 0x10257000, - 0x9100c050, - 0xc0c0c3f4, - 0x6f031420, - 0x04411031, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0x04411031, - 0x3182c082, - 0x91310021, - 0x3963b110, - 0xc0a21031, - 0x00213182, - 0xb1109131, - 0x31151050, - 0x92051405, - 0x643f7000, - 0x1031c052, - 0x31610631, - 0x644202c1, - 0x1031c112, - 0x06713921, - 0x02e13151, - 0x70006442, - 0x6599658a, - 0x8220c088, - 0x39803950, - 0x409f1e00, - 0x3001c041, - 0x1a181418, - 0x8230c089, - 0x39803960, - 0x40a91e00, - 0x3001c041, - 0x1a191419, - 0x9136643c, - 0x9134b110, - 0xb054b110, - 0xa0547100, - 0x80f0b064, - 0x40af2200, - 0x90b01240, - 0x8253b032, - 0x39533953, - 0x643f6485, - 0xc122c111, - 0xc1706442, - 0xc11168c2, - 0x6442c0c2, - 0x68c7c170, - 0x9100c050, - 0x92987227, - 0x16141615, - 0x10531042, - 0x8221c1f0, - 0x39313131, - 0x31313981, - 0xb270b051, - 0x72276572, - 0xb2709299, - 0x10731062, - 0x8231c3f0, - 0x39213121, - 0x101b3981, - 0xc0e26572, - 0x82603182, - 0x39803180, - 0xb0610002, - 0x91327100, - 0xa051b110, - 0x7227b061, - 0x68f3c230, - 0x12800000, - 0xb03290b0, - 0xc0507000, - 0x72279100, - 0x10629299, - 0xc3f01073, - 0x31218231, - 0x39813921, - 0xb270b051, - 0x7227657e, - 0xb2709298, - 0x10531042, - 0x8221c1f0, - 0x39313131, - 0x31313981, - 0x657e101a, - 0xb061a051, - 0xc0b07227, - 0x643f6918, - 0xc122c101, - 0xc1016442, - 0x6442c0c2, - 0x643c1a15, - 0xb1109135, - 0x64858253, - 0x90b012c0, - 0x7000b032, - 0xc272643f, - 0x6442c081, - 0xc111c122, - 0xc0026442, - 0x6442c111, - 0xc331c062, - 0xc3626442, - 0x6442c111, - 0xc111c302, - 0x82536442, - 0x64853953, - 0x6447c3e2, - 0x41402211, - 0xc881c242, - 0xc2526442, - 0x6442c111, - 0xcee1c272, - 0xc2026442, - 0x6442c881, - 0xc801c202, - 0xc0b06442, - 0x70006954, - 0xc242643f, - 0x6442c801, - 0xc011c252, - 0xc2726442, - 0x6442c0e1, - 0xc101c002, - 0xc0626442, - 0x6442c301, - 0xc101c122, - 0xc3626442, - 0x6442c101, - 0xc101c302, - 0x82536442, - 0x70006485, - 0x7100b061, - 0x1c231412, - 0x91334d7a, - 0x7000b110, - 0xb1109132, - 0x70006972, - 0x7100b061, - 0x1c321813, - 0x91324986, - 0x7000b110, - 0xb1109133, - 0x7000697e, - 0x6447c0c2, - 0xc0c21015, - 0x64471612, - 0x14153141, - 0x3180c0c0, - 0x10541405, - 0x040478a0, - 0xc0e67000, - 0xcc013186, - 0x10671416, - 0xc3f08261, - 0x14170401, - 0x73067000, - 0x720b7205, - 0xb050720e, - 0x80817100, - 0xa050b060, - 0x22418092, - 0x808045c3, - 0x0410c1f1, - 0x11011630, - 0x6c011401, - 0x61d761d6, - 0x61d961d8, - 0x61db61da, - 0x61de61dc, - 0x61e261e0, - 0x633661e4, - 0x80916339, - 0x0421c0f2, - 0x80823121, - 0x14122a42, - 0x11011632, - 0x6c011421, - 0x620b61ee, - 0x633961f4, - 0x620b61ee, - 0x633961f4, - 0x61e661e6, - 0x61e661e6, - 0x61e661e6, - 0x61e66494, - 0x61e664f9, - 0x61e6652a, - 0x61e66556, - 0x61e66746, - 0x90b01210, - 0x7306720e, - 0x12107205, - 0x61a79030, - 0x673ccff0, - 0xc003c1d4, - 0x6454c3c0, - 0x91507840, - 0x92107850, - 0x92207860, - 0x92307870, - 0x92407880, - 0x92607890, - 0x91907830, - 0x39408210, - 0x100106f0, - 0x14103110, - 0x67429200, - 0xa0bc61e6, - 0xa054a0e2, - 0x225080f0, - 0x80404615, - 0x472b2200, - 0xa040620d, - 0x318d822d, - 0x8210398d, - 0x0410c0f1, - 0x821a1009, - 0x041a394a, - 0x39808210, - 0x100e0410, - 0x10bc10ab, - 0x646310c2, - 0xcfe07229, - 0xb013673c, - 0x66c8b003, - 0xb050b053, - 0xb064b054, - 0x66a5b013, - 0x22e08210, - 0x66ae4638, - 0x80417100, - 0x472b2201, - 0x221080f0, - 0x22f0464b, - 0xb0644718, - 0x42382231, - 0x66ceb063, - 0x22e08210, - 0x66704638, - 0xb0646238, - 0x318f816f, - 0xdfd03d8f, - 0x673c92ff, - 0x80417100, - 0x472b2201, - 0x80f0b064, - 0x42652250, - 0x8211b063, - 0x466022c1, - 0x670566ce, - 0x22d18211, - 0x66704652, - 0x81616252, - 0x31818172, - 0x31823d81, - 0xefc03d82, - 0x930292f1, - 0x620b673c, - 0x91c081b0, - 0x829781d3, - 0x18d3a290, - 0x0bf34e7f, - 0x1ce31613, - 0x91c34aa4, - 0x143b81e3, - 0x1cba6290, - 0x1e23468b, - 0x1ce34a8b, - 0xb2904e8b, - 0x428b2207, - 0x1a1ba290, - 0x1ce36296, - 0x91c34aa4, - 0x183b81e3, - 0x4ea01cab, - 0x4aa21c9b, - 0x42a41cbc, - 0x821010b2, - 0x429d22d0, - 0x221080f0, - 0x646346a4, - 0x62a466a5, - 0x629410ab, - 0x6294109b, - 0x82307000, - 0x0410c0f1, - 0x7100b063, - 0x10bc6aa8, - 0x7000b0e0, - 0x91c281b2, - 0x820181d2, - 0x81511812, - 0x82411812, - 0x3d813181, - 0x4abf1c12, - 0xb032b0e2, - 0x92f2dfb0, - 0xc7f1673c, - 0x4ec31421, - 0x9162c812, - 0xb0319172, - 0x7000b0e1, - 0xc006c008, - 0x9160c800, - 0x70009170, - 0x81b08201, - 0x81d091c0, - 0x81511810, - 0x14061810, - 0x824280e1, - 0x3d823182, - 0x4ae41c20, - 0x2221b0e2, - 0xb03246e8, - 0xdfa01005, - 0x673c92f5, - 0x42e82221, - 0xb032a0e2, - 0x39418231, - 0x0401c0f0, - 0x42f61e01, - 0xc0101618, - 0x1c083010, - 0x10604704, - 0x10063c10, - 0x1461c7f1, - 0xc8164efa, - 0x81719166, - 0x3d813181, - 0x4b011c16, - 0xb0319176, - 0xc008c006, - 0x81617000, - 0x3d813181, - 0x39808240, - 0x1cf11801, - 0x14014b17, - 0x22c080b0, - 0xb0bc4717, - 0xef90b033, - 0x930f92f1, - 0x7000673c, - 0xb063a003, - 0xb0efb064, - 0x71006556, - 0x22008040, - 0xb064472b, - 0xa0ef652a, - 0x80407100, - 0x472b2200, - 0xb003b064, - 0x82016238, - 0x31828162, - 0xef803d82, - 0x930292f1, - 0xa003673c, - 0x61e66556, - 0x646380a2, - 0xb05061e6, - 0x61e67100, - 0x82d092e0, - 0x473d2200, - 0x7000b2c0, - 0x22f080a0, - 0xb0304359, - 0x3162c102, - 0x80a0c001, - 0x43521e00, - 0x435322f0, - 0x3160f5a0, - 0x63533960, - 0x1a101020, - 0x6e236f13, - 0x16121611, - 0x70006b54 -}; + { + 0x000061a3, + 0x1307147f, + 0x24f1004d, + 0x3f131f2e, + 0x003f0ab0, + 0x0000ff07, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x0008000f, + 0x003f0000, + 0x00400000, + 0x0000003f, + 0x00680004, + 0x00dc000e, + 0x00430006, + 0x0005001a, + 0x00000000, + 0x00000002, + 0x0000003f, + 0x00040000, + 0x000000c0, + 0x00c00004, + 0x00070000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x404f2241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x685b1614, + 0x10257000, + 0x9100c050, + 0xc0c0c3f4, + 0x6f031420, + 0x04411031, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x643f7000, + 0x1031c052, + 0x31610631, + 0x644202c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006442, + 0x6599658a, + 0x8220c088, + 0x39803950, + 0x409f1e00, + 0x3001c041, + 0x1a181418, + 0x8230c089, + 0x39803960, + 0x40a91e00, + 0x3001c041, + 0x1a191419, + 0x9136643c, + 0x9134b110, + 0xb054b110, + 0xa0547100, + 0x80f0b064, + 0x40af2200, + 0x90b01240, + 0x8253b032, + 0x39533953, + 0x643f6485, + 0xc122c111, + 0xc1706442, + 0xc11168c2, + 0x6442c0c2, + 0x68c7c170, + 0x9100c050, + 0x92987227, + 0x16141615, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0xb270b051, + 0x72276572, + 0xb2709299, + 0x10731062, + 0x8231c3f0, + 0x39213121, + 0x101b3981, + 0xc0e26572, + 0x82603182, + 0x39803180, + 0xb0610002, + 0x91327100, + 0xa051b110, + 0x7227b061, + 0x68f3c230, + 0x12800000, + 0xb03290b0, + 0xc0507000, + 0x72279100, + 0x10629299, + 0xc3f01073, + 0x31218231, + 0x39813921, + 0xb270b051, + 0x7227657e, + 0xb2709298, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0x657e101a, + 0xb061a051, + 0xc0b07227, + 0x643f6918, + 0xc122c101, + 0xc1016442, + 0x6442c0c2, + 0x643c1a15, + 0xb1109135, + 0x64858253, + 0x90b012c0, + 0x7000b032, + 0xc272643f, + 0x6442c081, + 0xc111c122, + 0xc0026442, + 0x6442c111, + 0xc331c062, + 0xc3626442, + 0x6442c111, + 0xc111c302, + 0x82536442, + 0x64853953, + 0x6447c3e2, + 0x41402211, + 0xc881c242, + 0xc2526442, + 0x6442c111, + 0xcee1c272, + 0xc2026442, + 0x6442c881, + 0xc801c202, + 0xc0b06442, + 0x70006954, + 0xc242643f, + 0x6442c801, + 0xc011c252, + 0xc2726442, + 0x6442c0e1, + 0xc101c002, + 0xc0626442, + 0x6442c301, + 0xc101c122, + 0xc3626442, + 0x6442c101, + 0xc101c302, + 0x82536442, + 0x70006485, + 0x7100b061, + 0x1c231412, + 0x91334d7a, + 0x7000b110, + 0xb1109132, + 0x70006972, + 0x7100b061, + 0x1c321813, + 0x91324986, + 0x7000b110, + 0xb1109133, + 0x7000697e, + 0x6447c0c2, + 0xc0c21015, + 0x64471612, + 0x14153141, + 0x3180c0c0, + 0x10541405, + 0x040478a0, + 0xc0e67000, + 0xcc013186, + 0x10671416, + 0xc3f08261, + 0x14170401, + 0x73067000, + 0x720b7205, + 0xb050720e, + 0x80817100, + 0xa050b060, + 0x22418092, + 0x808045c3, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x61d761d6, + 0x61d961d8, + 0x61db61da, + 0x61de61dc, + 0x61e261e0, + 0x633661e4, + 0x80916339, + 0x0421c0f2, + 0x80823121, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x620b61ee, + 0x633961f4, + 0x620b61ee, + 0x633961f4, + 0x61e661e6, + 0x61e661e6, + 0x61e661e6, + 0x61e66494, + 0x61e664f9, + 0x61e6652a, + 0x61e66556, + 0x61e66746, + 0x90b01210, + 0x7306720e, + 0x12107205, + 0x61a79030, + 0x673ccff0, + 0xc003c1d4, + 0x6454c3c0, + 0x91507840, + 0x92107850, + 0x92207860, + 0x92307870, + 0x92407880, + 0x92607890, + 0x91907830, + 0x39408210, + 0x100106f0, + 0x14103110, + 0x67429200, + 0xa0bc61e6, + 0xa054a0e2, + 0x225080f0, + 0x80404615, + 0x472b2200, + 0xa040620d, + 0x318d822d, + 0x8210398d, + 0x0410c0f1, + 0x821a1009, + 0x041a394a, + 0x39808210, + 0x100e0410, + 0x10bc10ab, + 0x646310c2, + 0xcfe07229, + 0xb013673c, + 0x66c8b003, + 0xb050b053, + 0xb064b054, + 0x66a5b013, + 0x22e08210, + 0x66ae4638, + 0x80417100, + 0x472b2201, + 0x221080f0, + 0x22f0464b, + 0xb0644718, + 0x42382231, + 0x66ceb063, + 0x22e08210, + 0x66704638, + 0xb0646238, + 0x318f816f, + 0xdfd03d8f, + 0x673c92ff, + 0x80417100, + 0x472b2201, + 0x80f0b064, + 0x42652250, + 0x8211b063, + 0x466022c1, + 0x670566ce, + 0x22d18211, + 0x66704652, + 0x81616252, + 0x31818172, + 0x31823d81, + 0xefc03d82, + 0x930292f1, + 0x620b673c, + 0x91c081b0, + 0x829781d3, + 0x18d3a290, + 0x0bf34e7f, + 0x1ce31613, + 0x91c34aa4, + 0x143b81e3, + 0x1cba6290, + 0x1e23468b, + 0x1ce34a8b, + 0xb2904e8b, + 0x428b2207, + 0x1a1ba290, + 0x1ce36296, + 0x91c34aa4, + 0x183b81e3, + 0x4ea01cab, + 0x4aa21c9b, + 0x42a41cbc, + 0x821010b2, + 0x429d22d0, + 0x221080f0, + 0x646346a4, + 0x62a466a5, + 0x629410ab, + 0x6294109b, + 0x82307000, + 0x0410c0f1, + 0x7100b063, + 0x10bc6aa8, + 0x7000b0e0, + 0x91c281b2, + 0x820181d2, + 0x81511812, + 0x82411812, + 0x3d813181, + 0x4abf1c12, + 0xb032b0e2, + 0x92f2dfb0, + 0xc7f1673c, + 0x4ec31421, + 0x9162c812, + 0xb0319172, + 0x7000b0e1, + 0xc006c008, + 0x9160c800, + 0x70009170, + 0x81b08201, + 0x81d091c0, + 0x81511810, + 0x14061810, + 0x824280e1, + 0x3d823182, + 0x4ae41c20, + 0x2221b0e2, + 0xb03246e8, + 0xdfa01005, + 0x673c92f5, + 0x42e82221, + 0xb032a0e2, + 0x39418231, + 0x0401c0f0, + 0x42f61e01, + 0xc0101618, + 0x1c083010, + 0x10604704, + 0x10063c10, + 0x1461c7f1, + 0xc8164efa, + 0x81719166, + 0x3d813181, + 0x4b011c16, + 0xb0319176, + 0xc008c006, + 0x81617000, + 0x3d813181, + 0x39808240, + 0x1cf11801, + 0x14014b17, + 0x22c080b0, + 0xb0bc4717, + 0xef90b033, + 0x930f92f1, + 0x7000673c, + 0xb063a003, + 0xb0efb064, + 0x71006556, + 0x22008040, + 0xb064472b, + 0xa0ef652a, + 0x80407100, + 0x472b2200, + 0xb003b064, + 0x82016238, + 0x31828162, + 0xef803d82, + 0x930292f1, + 0xa003673c, + 0x61e66556, + 0x646380a2, + 0xb05061e6, + 0x61e67100, + 0x82d092e0, + 0x473d2200, + 0x7000b2c0, + 0x22f080a0, + 0xb0304359, + 0x3162c102, + 0x80a0c001, + 0x43521e00, + 0x435322f0, + 0x3160f5a0, + 0x63533960, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006b54}; PATCH_FUN_SPEC void rf_patch_rfe_brepeat(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_genfsk.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_genfsk.h index db7b4c8..d2a7c70 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_genfsk.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_genfsk.h @@ -1,496 +1,494 @@ /****************************************************************************** -* Filename: rf_patch_rfe_genfsk.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 Generic FSK -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - + * Filename: rf_patch_rfe_genfsk.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 Generic FSK + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_RFE_GENFSK_H #define _RF_PATCH_RFE_GENFSK_H -#include #include "../inc/hw_types.h" +#include #ifndef RFE_PATCH_TYPE - #define RFE_PATCH_TYPE static const uint32_t +#define RFE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_RFERAM_BASE - #define RFC_RFERAM_BASE 0x2100C000 +#define RFC_RFERAM_BASE 0x2100C000 #endif #ifndef RFE_PATCH_MODE - #define RFE_PATCH_MODE 0 +#define RFE_PATCH_MODE 0 #endif RFE_PATCH_TYPE patchGenfskRfe[429] = -{ - 0x000061a3, - 0x1307147f, - 0x24f1004d, - 0x3f131f2e, - 0x003f0ab0, - 0x0000ff07, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x43cf41cf, - 0x4fcf47cf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x00000000, - 0x0008000f, - 0x003f0000, - 0x00400000, - 0x0000003f, - 0x00680004, - 0x00dc000e, - 0x00430006, - 0x0005001a, - 0x00000000, - 0x00000002, - 0x0000003f, - 0x00040000, - 0x000000c0, - 0x00c00004, - 0x00070000, - 0x9100c050, - 0xc0707000, - 0x70009100, - 0x00213182, - 0xb1109131, - 0x81017000, - 0xa100b101, - 0x91323182, - 0x9101b110, - 0x81411011, - 0x404f2241, - 0x700006f1, - 0x9101c051, - 0x39101830, - 0xd0083183, - 0x6f413118, - 0x91310031, - 0x1483b110, - 0x685b1614, - 0x10257000, - 0x9100c050, - 0xc0c0c3f4, - 0x6f031420, - 0x04411031, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0x04411031, - 0x3182c082, - 0x91310021, - 0x3963b110, - 0xc0a21031, - 0x00213182, - 0xb1109131, - 0x31151050, - 0x92051405, - 0x643f7000, - 0x1031c052, - 0x31610631, - 0x644202c1, - 0x1031c112, - 0x06713921, - 0x02e13151, - 0x70006442, - 0x6599658a, - 0x8220c088, - 0x39803950, - 0x409f1e00, - 0x3001c041, - 0x1a181418, - 0x8230c089, - 0x39803960, - 0x40a91e00, - 0x3001c041, - 0x1a191419, - 0x9136643c, - 0x9134b110, - 0xb054b110, - 0xa0547100, - 0x80f0b064, - 0x40af2200, - 0x90b01240, - 0x8253b032, - 0x39533953, - 0x643f6485, - 0xc122c111, - 0xc1706442, - 0xc11168c2, - 0x6442c0c2, - 0x68c7c170, - 0x9100c050, - 0x92987227, - 0x16141615, - 0x10531042, - 0x8221c1f0, - 0x39313131, - 0x31313981, - 0xb270b051, - 0x72276572, - 0xb2709299, - 0x10731062, - 0x8231c3f0, - 0x39213121, - 0x101b3981, - 0xc0e26572, - 0x82603182, - 0x39803180, - 0xb0610002, - 0x91327100, - 0xa051b110, - 0x7227b061, - 0x68f3c230, - 0x12800000, - 0xb03290b0, - 0xc0507000, - 0x72279100, - 0x10629299, - 0xc3f01073, - 0x31218231, - 0x39813921, - 0xb270b051, - 0x7227657e, - 0xb2709298, - 0x10531042, - 0x8221c1f0, - 0x39313131, - 0x31313981, - 0x657e101a, - 0xb061a051, - 0xc0b07227, - 0x643f6918, - 0xc122c101, - 0xc1016442, - 0x6442c0c2, - 0x643c1a15, - 0xb1109135, - 0x64858253, - 0x90b012c0, - 0x7000b032, - 0xc272643f, - 0x6442c081, - 0xc111c122, - 0xc0026442, - 0x6442c111, - 0xc331c062, - 0xc3626442, - 0x6442c111, - 0xc111c302, - 0x82536442, - 0x64853953, - 0x6447c3e2, - 0x41402211, - 0xc881c242, - 0xc2526442, - 0x6442c111, - 0xcee1c272, - 0xc2026442, - 0x6442c881, - 0xc801c202, - 0xc0b06442, - 0x70006954, - 0xc242643f, - 0x6442c801, - 0xc011c252, - 0xc2726442, - 0x6442c0e1, - 0xc101c002, - 0xc0626442, - 0x6442c301, - 0xc101c122, - 0xc3626442, - 0x6442c101, - 0xc101c302, - 0x82536442, - 0x70006485, - 0x7100b061, - 0x1c231412, - 0x91334d7a, - 0x7000b110, - 0xb1109132, - 0x70006972, - 0x7100b061, - 0x1c321813, - 0x91324986, - 0x7000b110, - 0xb1109133, - 0x7000697e, - 0x6447c0c2, - 0xc0c21015, - 0x64471612, - 0x14153141, - 0x3180c0c0, - 0x10541405, - 0x040478a0, - 0xc0e67000, - 0xcc013186, - 0x10671416, - 0xc3f08261, - 0x14170401, - 0x73067000, - 0x720b7205, - 0xb050720e, - 0x80817100, - 0xa050b060, - 0x22418092, - 0x808045c3, - 0x0410c1f1, - 0x11011630, - 0x6c011401, - 0x61d761d6, - 0x61d961d8, - 0x61db61da, - 0x61de61dc, - 0x61e261e0, - 0x633661e4, - 0x80916339, - 0x0421c0f2, - 0x80823121, - 0x14122a42, - 0x11011632, - 0x6c011421, - 0x620b61ee, - 0x633961f4, - 0x620b61ee, - 0x633961f4, - 0x61e661e6, - 0x61e661e6, - 0x61e661e6, - 0x61e66494, - 0x61e664f9, - 0x61e6652a, - 0x61e66556, - 0x61e66746, - 0x90b01210, - 0x7306720e, - 0x12107205, - 0x61a79030, - 0x673ccff0, - 0xc003c1d4, - 0x6454c3c0, - 0x91507840, - 0x92107850, - 0x92207860, - 0x92307870, - 0x92407880, - 0x92607890, - 0x91907830, - 0x39408210, - 0x100106f0, - 0x14103110, - 0x67429200, - 0xa0bc61e6, - 0xa054a0e2, - 0x225080f0, - 0x80404615, - 0x472b2200, - 0xa040620d, - 0x318d822d, - 0x8210398d, - 0x0410c0f1, - 0x821a1009, - 0x041a394a, - 0x39808210, - 0x100e0410, - 0x10bc10ab, - 0x646310c2, - 0xcfe07229, - 0xb013673c, - 0x66c8b003, - 0xb050b053, - 0xb064b054, - 0x66a5b013, - 0x22e08210, - 0x66ae4638, - 0x80417100, - 0x472b2201, - 0x221080f0, - 0x22f0464b, - 0xb0644718, - 0x42382231, - 0x66ceb063, - 0x22e08210, - 0x66704638, - 0xb0646238, - 0x318f816f, - 0xdfd03d8f, - 0x673c92ff, - 0x80417100, - 0x472b2201, - 0x80f0b064, - 0x42652250, - 0x8211b063, - 0x466022c1, - 0x670566ce, - 0x22d18211, - 0x66704652, - 0x81616252, - 0x31818172, - 0x31823d81, - 0xefc03d82, - 0x930292f1, - 0x620b673c, - 0x91c081b0, - 0x829781d3, - 0x18d3a290, - 0x0bf34e7f, - 0x1ce31613, - 0x91c34aa4, - 0x143b81e3, - 0x1cba6290, - 0x1e23468b, - 0x1ce34a8b, - 0xb2904e8b, - 0x428b2207, - 0x1a1ba290, - 0x1ce36296, - 0x91c34aa4, - 0x183b81e3, - 0x4ea01cab, - 0x4aa21c9b, - 0x42a41cbc, - 0x821010b2, - 0x429d22d0, - 0x221080f0, - 0x646346a4, - 0x62a466a5, - 0x629410ab, - 0x6294109b, - 0x82307000, - 0x0410c0f1, - 0x7100b063, - 0x10bc6aa8, - 0x7000b0e0, - 0x91c281b2, - 0x820181d2, - 0x81511812, - 0x82411812, - 0x3d813181, - 0x4abf1c12, - 0xb032b0e2, - 0x92f2dfb0, - 0xc7f1673c, - 0x4ec31421, - 0x9162c812, - 0xb0319172, - 0x7000b0e1, - 0xc006c008, - 0x9160c800, - 0x70009170, - 0x81b08201, - 0x81d091c0, - 0x81511810, - 0x14061810, - 0x824280e1, - 0x3d823182, - 0x4ae41c20, - 0x2221b0e2, - 0xb03246e8, - 0xdfa01005, - 0x673c92f5, - 0x42e82221, - 0xb032a0e2, - 0x39418231, - 0x0401c0f0, - 0x42f61e01, - 0xc0101618, - 0x1c083010, - 0x10604704, - 0x10063c10, - 0x1461c7f1, - 0xc8164efa, - 0x81719166, - 0x3d813181, - 0x4b011c16, - 0xb0319176, - 0xc008c006, - 0x81617000, - 0x3d813181, - 0x39808240, - 0x1cf11801, - 0x14014b17, - 0x22c080b0, - 0xb0bc4717, - 0xef90b033, - 0x930f92f1, - 0x7000673c, - 0xb063a003, - 0xb0efb064, - 0x71006556, - 0x22008040, - 0xb064472b, - 0xa0ef652a, - 0x80407100, - 0x472b2200, - 0xb003b064, - 0x82016238, - 0x31828162, - 0xef803d82, - 0x930292f1, - 0xa003673c, - 0x61e66556, - 0x646380a2, - 0xb05061e6, - 0x61e67100, - 0x82d092e0, - 0x473d2200, - 0x7000b2c0, - 0x22f080a0, - 0xb0304359, - 0x3162c102, - 0x80a0c001, - 0x43521e00, - 0x435322f0, - 0x3160f5a0, - 0x63533960, - 0x1a101020, - 0x6e236f13, - 0x16121611, - 0x70006b54 -}; + { + 0x000061a3, + 0x1307147f, + 0x24f1004d, + 0x3f131f2e, + 0x003f0ab0, + 0x0000ff07, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x0008000f, + 0x003f0000, + 0x00400000, + 0x0000003f, + 0x00680004, + 0x00dc000e, + 0x00430006, + 0x0005001a, + 0x00000000, + 0x00000002, + 0x0000003f, + 0x00040000, + 0x000000c0, + 0x00c00004, + 0x00070000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x404f2241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x685b1614, + 0x10257000, + 0x9100c050, + 0xc0c0c3f4, + 0x6f031420, + 0x04411031, + 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0x72279100, + 0x10629299, + 0xc3f01073, + 0x31218231, + 0x39813921, + 0xb270b051, + 0x7227657e, + 0xb2709298, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0x657e101a, + 0xb061a051, + 0xc0b07227, + 0x643f6918, + 0xc122c101, + 0xc1016442, + 0x6442c0c2, + 0x643c1a15, + 0xb1109135, + 0x64858253, + 0x90b012c0, + 0x7000b032, + 0xc272643f, + 0x6442c081, + 0xc111c122, + 0xc0026442, + 0x6442c111, + 0xc331c062, + 0xc3626442, + 0x6442c111, + 0xc111c302, + 0x82536442, + 0x64853953, + 0x6447c3e2, + 0x41402211, + 0xc881c242, + 0xc2526442, + 0x6442c111, + 0xcee1c272, + 0xc2026442, + 0x6442c881, + 0xc801c202, + 0xc0b06442, + 0x70006954, + 0xc242643f, + 0x6442c801, + 0xc011c252, + 0xc2726442, + 0x6442c0e1, + 0xc101c002, + 0xc0626442, + 0x6442c301, + 0xc101c122, + 0xc3626442, + 0x6442c101, + 0xc101c302, + 0x82536442, + 0x70006485, + 0x7100b061, + 0x1c231412, + 0x91334d7a, + 0x7000b110, + 0xb1109132, + 0x70006972, + 0x7100b061, + 0x1c321813, + 0x91324986, + 0x7000b110, + 0xb1109133, + 0x7000697e, + 0x6447c0c2, + 0xc0c21015, + 0x64471612, + 0x14153141, + 0x3180c0c0, + 0x10541405, + 0x040478a0, + 0xc0e67000, + 0xcc013186, + 0x10671416, + 0xc3f08261, + 0x14170401, + 0x73067000, + 0x720b7205, + 0xb050720e, + 0x80817100, + 0xa050b060, + 0x22418092, + 0x808045c3, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x61d761d6, + 0x61d961d8, + 0x61db61da, + 0x61de61dc, + 0x61e261e0, + 0x633661e4, + 0x80916339, + 0x0421c0f2, + 0x80823121, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x620b61ee, + 0x633961f4, + 0x620b61ee, + 0x633961f4, + 0x61e661e6, + 0x61e661e6, + 0x61e661e6, + 0x61e66494, + 0x61e664f9, + 0x61e6652a, + 0x61e66556, + 0x61e66746, + 0x90b01210, + 0x7306720e, + 0x12107205, + 0x61a79030, + 0x673ccff0, + 0xc003c1d4, + 0x6454c3c0, + 0x91507840, + 0x92107850, + 0x92207860, + 0x92307870, + 0x92407880, + 0x92607890, + 0x91907830, + 0x39408210, + 0x100106f0, + 0x14103110, + 0x67429200, + 0xa0bc61e6, + 0xa054a0e2, + 0x225080f0, + 0x80404615, + 0x472b2200, + 0xa040620d, + 0x318d822d, + 0x8210398d, + 0x0410c0f1, + 0x821a1009, + 0x041a394a, + 0x39808210, + 0x100e0410, + 0x10bc10ab, + 0x646310c2, + 0xcfe07229, + 0xb013673c, + 0x66c8b003, + 0xb050b053, + 0xb064b054, + 0x66a5b013, + 0x22e08210, + 0x66ae4638, + 0x80417100, + 0x472b2201, + 0x221080f0, + 0x22f0464b, + 0xb0644718, + 0x42382231, + 0x66ceb063, + 0x22e08210, + 0x66704638, + 0xb0646238, + 0x318f816f, + 0xdfd03d8f, + 0x673c92ff, + 0x80417100, + 0x472b2201, + 0x80f0b064, + 0x42652250, + 0x8211b063, + 0x466022c1, + 0x670566ce, + 0x22d18211, + 0x66704652, + 0x81616252, + 0x31818172, + 0x31823d81, + 0xefc03d82, + 0x930292f1, + 0x620b673c, + 0x91c081b0, + 0x829781d3, + 0x18d3a290, + 0x0bf34e7f, + 0x1ce31613, + 0x91c34aa4, + 0x143b81e3, + 0x1cba6290, + 0x1e23468b, + 0x1ce34a8b, + 0xb2904e8b, + 0x428b2207, + 0x1a1ba290, + 0x1ce36296, + 0x91c34aa4, + 0x183b81e3, + 0x4ea01cab, + 0x4aa21c9b, + 0x42a41cbc, + 0x821010b2, + 0x429d22d0, + 0x221080f0, + 0x646346a4, + 0x62a466a5, + 0x629410ab, + 0x6294109b, + 0x82307000, + 0x0410c0f1, + 0x7100b063, + 0x10bc6aa8, + 0x7000b0e0, + 0x91c281b2, + 0x820181d2, + 0x81511812, + 0x82411812, + 0x3d813181, + 0x4abf1c12, + 0xb032b0e2, + 0x92f2dfb0, + 0xc7f1673c, + 0x4ec31421, + 0x9162c812, + 0xb0319172, + 0x7000b0e1, + 0xc006c008, + 0x9160c800, + 0x70009170, + 0x81b08201, + 0x81d091c0, + 0x81511810, + 0x14061810, + 0x824280e1, + 0x3d823182, + 0x4ae41c20, + 0x2221b0e2, + 0xb03246e8, + 0xdfa01005, + 0x673c92f5, + 0x42e82221, + 0xb032a0e2, + 0x39418231, + 0x0401c0f0, + 0x42f61e01, + 0xc0101618, + 0x1c083010, + 0x10604704, + 0x10063c10, + 0x1461c7f1, + 0xc8164efa, + 0x81719166, + 0x3d813181, + 0x4b011c16, + 0xb0319176, + 0xc008c006, + 0x81617000, + 0x3d813181, + 0x39808240, + 0x1cf11801, + 0x14014b17, + 0x22c080b0, + 0xb0bc4717, + 0xef90b033, + 0x930f92f1, + 0x7000673c, + 0xb063a003, + 0xb0efb064, + 0x71006556, + 0x22008040, + 0xb064472b, + 0xa0ef652a, + 0x80407100, + 0x472b2200, + 0xb003b064, + 0x82016238, + 0x31828162, + 0xef803d82, + 0x930292f1, + 0xa003673c, + 0x61e66556, + 0x646380a2, + 0xb05061e6, + 0x61e67100, + 0x82d092e0, + 0x473d2200, + 0x7000b2c0, + 0x22f080a0, + 0xb0304359, + 0x3162c102, + 0x80a0c001, + 0x43521e00, + 0x435322f0, + 0x3160f5a0, + 0x63533960, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006b54}; PATCH_FUN_SPEC void rf_patch_rfe_genfsk(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_genfsk_ant_div.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_genfsk_ant_div.h index 674f414..153f48f 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_genfsk_ant_div.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_genfsk_ant_div.h @@ -1,432 +1,430 @@ /****************************************************************************** -* Filename: rf_patch_rfe_genfsk_ant_div.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 Generic FSK antenna diversity -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - + * Filename: rf_patch_rfe_genfsk_ant_div.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 Generic FSK antenna diversity + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_RFE_GENFSK_ANT_DIV_H #define _RF_PATCH_RFE_GENFSK_ANT_DIV_H -#include #include "../inc/hw_types.h" +#include #ifndef RFE_PATCH_TYPE - #define RFE_PATCH_TYPE static const uint32_t +#define RFE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_RFERAM_BASE - #define RFC_RFERAM_BASE 0x2100C000 +#define RFC_RFERAM_BASE 0x2100C000 #endif #ifndef RFE_PATCH_MODE - #define RFE_PATCH_MODE 0 +#define RFE_PATCH_MODE 0 #endif RFE_PATCH_TYPE patchGenfskAntDivRfe[365] = -{ - 0x0000613b, - 0x1307147f, - 0x35f1004d, - 0x0003ffa6, - 0x003f0a91, - 0xf00ff000, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x43cf41cf, - 0x4fcf47cf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x000f0000, - 0x00000008, - 0x0000003f, - 0x003f0040, - 0x00040000, - 0x000e0068, - 0x000600dc, - 0x001a0043, - 0x00000005, - 0x00020000, - 0x003f0000, - 0x00000000, - 0x00c00004, - 0x00040000, - 0x000000c0, - 0xc0500007, - 0x70009100, - 0x9100c070, - 0x31827000, - 0x91310021, - 0x7000b110, - 0xb1018101, - 0x3182a100, - 0xb1109132, - 0x10119101, - 0x22418141, - 0x06f1404e, - 0xc0517000, - 0x18309101, - 0x31833910, - 0x3118d008, - 0x00316f41, - 0xb1109131, - 0x16141483, - 0x7000685a, - 0xc0501025, - 0xc3f49100, - 0x1420c0c0, - 0x10316f03, - 0xc0220441, - 0x00213182, - 0xb1109131, - 0x10313963, - 0xc0820441, - 0x00213182, - 0xb1109131, - 0x10313963, - 0x3182c0a2, - 0x91310021, - 0x1050b110, - 0x14053115, - 0x70009205, - 0xc052643e, - 0x06311031, - 0x02c13161, - 0xc1126441, - 0x39211031, - 0x31510671, - 0x644102e1, - 0xc0517000, - 0xcc019101, - 0x6441c0e2, - 0xc111643e, - 0x6441c0c2, - 0x7100b054, - 0xb064a054, - 0x220080f0, - 0xc111409c, - 0x6441c122, - 0x9101c051, - 0x3182c0e2, - 0x00028260, - 0xb1109132, - 0x68afc300, - 0x1240643e, - 0xb03290b0, - 0x39538253, - 0x64843953, - 0x68b9c360, - 0x90b01280, - 0x7000b032, - 0xc101643e, - 0x6441c122, - 0xc0c2c101, - 0x82536441, - 0x12c06484, - 0xb03290b0, - 0x643e7000, - 0xc081c272, - 0xc1226441, - 0x6441c111, - 0xc111c002, - 0xc0626441, - 0x6441c331, - 0xc111c362, - 0xc3026441, - 0x6441c111, - 0x39538253, - 0xc3e26484, - 0x22116446, - 0xc24240e1, - 0x6441c881, - 0xc111c252, - 0xc2726441, - 0x6441cee1, - 0xc881c202, - 0xc2026441, - 0x6441c801, - 0x68f5c0b0, - 0x643e7000, - 0xc801c242, - 0xc2526441, - 0x6441c011, - 0xc0e1c272, - 0xc0026441, - 0x6441c101, - 0xc301c062, - 0xc1226441, - 0x6441c101, - 0xc101c362, - 0xc3026441, - 0x6441c101, - 0x64848253, - 0x00007000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x73060000, - 0x720b7205, - 0xb050720e, - 0x80817100, - 0xa050b060, - 0x22418092, - 0x8080455b, - 0x0410c1f1, - 0x11011630, - 0x6c011401, - 0x616f616e, - 0x61716170, - 0x61736172, - 0x61766174, - 0x617a6178, - 0x62b6617c, - 0x809162b9, - 0x0421c0f2, - 0x80823121, - 0x14122a42, - 0x11011632, - 0x6c011421, - 0x61a36186, - 0x62b9618c, - 0x61a36186, - 0x62b9618c, - 0x617e617e, - 0x617e617e, - 0x617e617e, - 0x617e6493, - 0x617e64be, - 0x617e64cb, - 0x617e64f7, - 0x617e66c6, - 0x90b01210, - 0x7306720e, - 0x12107205, - 0x613f9030, - 0x66bccff0, - 0xc003c1c4, - 0x6453c3c0, - 0x91507840, - 0x92107850, - 0x92207860, - 0x92307870, - 0x92407880, - 0x92607890, - 0x91907830, - 0x39408210, - 0x100106f0, - 0x14103110, - 0x66c29200, - 0x8210617e, - 0x0410c0f1, - 0x821a1009, - 0x041a394a, - 0x39808210, - 0x100e0410, - 0xa0bca040, - 0x78a080e1, - 0x90e10401, - 0x80f0a054, - 0x45bc2250, - 0x22008040, - 0x61b446ab, - 0x10ab822d, - 0x10c210bc, - 0xb0136462, - 0x6649b003, - 0xb050b053, - 0xb064b054, - 0x65fcb013, - 0x82106621, - 0x45cf22e0, - 0x7100662a, - 0x22018041, - 0x80f046ab, - 0x41af2250, - 0x221080f0, - 0xb06445df, - 0x41cf2231, - 0x664fb063, - 0xb06461cf, - 0x318f816f, - 0xdfe03d8f, - 0x66bc92ff, - 0x80417100, - 0x46ab2201, - 0x80f0b064, - 0x41f52250, - 0x8211b063, - 0x45f422c1, - 0x6698664f, - 0x816161e6, - 0x31818172, - 0x31823d81, - 0x61af3d82, - 0x3d8380f3, - 0x4e0818d3, - 0x16130bf3, - 0x4a201ce3, - 0x81e391c3, - 0x620d143b, - 0x4a201ce3, - 0x81e391c3, - 0x1cab183b, - 0x1c9b4e1c, - 0x1cbc4a1e, - 0x10b24220, - 0x22d08210, - 0x80f0421a, - 0x46202210, - 0x62206462, - 0x621110ab, - 0x6211109b, - 0x82307000, - 0x0410c0f1, - 0x7100b063, - 0x10bc6a24, - 0x7000b0e0, - 0x91c281b2, - 0x820181d2, - 0x81511812, - 0x82411812, - 0x3d813181, - 0x4a3b1c12, - 0xb032b0e2, - 0x92f2dfd0, - 0xc7f166bc, - 0x4e3f1421, - 0x9162c812, - 0x31829172, - 0x16223942, - 0x002080e0, - 0xb03190e0, - 0x12087000, - 0xc800c006, - 0x91709160, - 0x82017000, - 0x91c081b0, - 0x181081d0, - 0x18108151, - 0x80e11406, - 0x31828242, - 0x1c203d82, - 0x22214a67, - 0xb0e24673, - 0x1002b032, - 0x92f2dfc0, - 0x102066bc, - 0x22216273, - 0x1a324273, - 0x4e731c20, - 0xb032a0e2, - 0xdfb01002, - 0x66bc92f2, - 0x82311020, - 0xc0f03941, - 0x1e010401, - 0x16184281, - 0x3010c010, - 0x46971c08, - 0x3c101060, - 0xc7f11006, - 0x4e851461, - 0x9166c816, - 0x31818171, - 0x1c163d81, - 0x91764a8c, - 0x39463186, - 0x80e01686, - 0x048078b8, - 0x90e00060, - 0xc006b031, - 0x70001208, - 0x31818161, - 0x82403d81, - 0x18013980, - 0x4aaa1cf1, - 0x80b01401, - 0x46aa22c0, - 0xb033b0bc, - 0x92f1efa0, - 0x66bc930f, - 0x82017000, - 0x31828162, - 0xef903d82, - 0x930292f1, - 0xa00366bc, - 0x617e64f7, - 0x646280a2, - 0xb050617e, - 0x617e7100, - 0x82d092e0, - 0x46bd2200, - 0x7000b2c0, - 0x22f080a0, - 0xb03042d9, - 0x3162c102, - 0x80a0c001, - 0x42d21e00, - 0x42d322f0, - 0x3160eda0, - 0x62d33960, - 0x1a101020, - 0x6e236f13, - 0x16121611, - 0x70006ad4 -}; + { + 0x0000613b, + 0x1307147f, + 0x35f1004d, + 0x0003ffa6, + 0x003f0a91, + 0xf00ff000, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x000f0000, + 0x00000008, + 0x0000003f, + 0x003f0040, + 0x00040000, + 0x000e0068, + 0x000600dc, + 0x001a0043, + 0x00000005, + 0x00020000, + 0x003f0000, + 0x00000000, + 0x00c00004, + 0x00040000, + 0x000000c0, + 0xc0500007, + 0x70009100, + 0x9100c070, + 0x31827000, + 0x91310021, + 0x7000b110, + 0xb1018101, + 0x3182a100, + 0xb1109132, + 0x10119101, + 0x22418141, + 0x06f1404e, + 0xc0517000, + 0x18309101, + 0x31833910, + 0x3118d008, + 0x00316f41, + 0xb1109131, + 0x16141483, + 0x7000685a, + 0xc0501025, + 0xc3f49100, + 0x1420c0c0, + 0x10316f03, + 0xc0220441, + 0x00213182, + 0xb1109131, + 0x10313963, + 0xc0820441, + 0x00213182, + 0xb1109131, + 0x10313963, + 0x3182c0a2, + 0x91310021, + 0x1050b110, + 0x14053115, + 0x70009205, + 0xc052643e, + 0x06311031, + 0x02c13161, + 0xc1126441, + 0x39211031, + 0x31510671, + 0x644102e1, + 0xc0517000, + 0xcc019101, + 0x6441c0e2, + 0xc111643e, + 0x6441c0c2, + 0x7100b054, + 0xb064a054, + 0x220080f0, + 0xc111409c, + 0x6441c122, + 0x9101c051, + 0x3182c0e2, + 0x00028260, + 0xb1109132, + 0x68afc300, + 0x1240643e, + 0xb03290b0, + 0x39538253, + 0x64843953, + 0x68b9c360, + 0x90b01280, + 0x7000b032, + 0xc101643e, + 0x6441c122, + 0xc0c2c101, + 0x82536441, + 0x12c06484, + 0xb03290b0, + 0x643e7000, + 0xc081c272, + 0xc1226441, + 0x6441c111, + 0xc111c002, + 0xc0626441, + 0x6441c331, + 0xc111c362, + 0xc3026441, + 0x6441c111, + 0x39538253, + 0xc3e26484, + 0x22116446, + 0xc24240e1, + 0x6441c881, + 0xc111c252, + 0xc2726441, + 0x6441cee1, + 0xc881c202, + 0xc2026441, + 0x6441c801, + 0x68f5c0b0, + 0x643e7000, + 0xc801c242, + 0xc2526441, + 0x6441c011, + 0xc0e1c272, + 0xc0026441, + 0x6441c101, + 0xc301c062, + 0xc1226441, + 0x6441c101, + 0xc101c362, + 0xc3026441, + 0x6441c101, + 0x64848253, + 0x00007000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x73060000, + 0x720b7205, + 0xb050720e, + 0x80817100, + 0xa050b060, + 0x22418092, + 0x8080455b, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x616f616e, + 0x61716170, + 0x61736172, + 0x61766174, + 0x617a6178, + 0x62b6617c, + 0x809162b9, + 0x0421c0f2, + 0x80823121, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x61a36186, + 0x62b9618c, + 0x61a36186, + 0x62b9618c, + 0x617e617e, + 0x617e617e, + 0x617e617e, + 0x617e6493, + 0x617e64be, + 0x617e64cb, + 0x617e64f7, + 0x617e66c6, + 0x90b01210, + 0x7306720e, + 0x12107205, + 0x613f9030, + 0x66bccff0, + 0xc003c1c4, + 0x6453c3c0, + 0x91507840, + 0x92107850, + 0x92207860, + 0x92307870, + 0x92407880, + 0x92607890, + 0x91907830, + 0x39408210, + 0x100106f0, + 0x14103110, + 0x66c29200, + 0x8210617e, + 0x0410c0f1, + 0x821a1009, + 0x041a394a, + 0x39808210, + 0x100e0410, + 0xa0bca040, + 0x78a080e1, + 0x90e10401, + 0x80f0a054, + 0x45bc2250, + 0x22008040, + 0x61b446ab, + 0x10ab822d, + 0x10c210bc, + 0xb0136462, + 0x6649b003, + 0xb050b053, + 0xb064b054, + 0x65fcb013, + 0x82106621, + 0x45cf22e0, + 0x7100662a, + 0x22018041, + 0x80f046ab, + 0x41af2250, + 0x221080f0, + 0xb06445df, + 0x41cf2231, + 0x664fb063, + 0xb06461cf, + 0x318f816f, + 0xdfe03d8f, + 0x66bc92ff, + 0x80417100, + 0x46ab2201, + 0x80f0b064, + 0x41f52250, + 0x8211b063, + 0x45f422c1, + 0x6698664f, + 0x816161e6, + 0x31818172, + 0x31823d81, + 0x61af3d82, + 0x3d8380f3, + 0x4e0818d3, + 0x16130bf3, + 0x4a201ce3, + 0x81e391c3, + 0x620d143b, + 0x4a201ce3, + 0x81e391c3, + 0x1cab183b, + 0x1c9b4e1c, + 0x1cbc4a1e, + 0x10b24220, + 0x22d08210, + 0x80f0421a, + 0x46202210, + 0x62206462, + 0x621110ab, + 0x6211109b, + 0x82307000, + 0x0410c0f1, + 0x7100b063, + 0x10bc6a24, + 0x7000b0e0, + 0x91c281b2, + 0x820181d2, + 0x81511812, + 0x82411812, + 0x3d813181, + 0x4a3b1c12, + 0xb032b0e2, + 0x92f2dfd0, + 0xc7f166bc, + 0x4e3f1421, + 0x9162c812, + 0x31829172, + 0x16223942, + 0x002080e0, + 0xb03190e0, + 0x12087000, + 0xc800c006, + 0x91709160, + 0x82017000, + 0x91c081b0, + 0x181081d0, + 0x18108151, + 0x80e11406, + 0x31828242, + 0x1c203d82, + 0x22214a67, + 0xb0e24673, + 0x1002b032, + 0x92f2dfc0, + 0x102066bc, + 0x22216273, + 0x1a324273, + 0x4e731c20, + 0xb032a0e2, + 0xdfb01002, + 0x66bc92f2, + 0x82311020, + 0xc0f03941, + 0x1e010401, + 0x16184281, + 0x3010c010, + 0x46971c08, + 0x3c101060, + 0xc7f11006, + 0x4e851461, + 0x9166c816, + 0x31818171, + 0x1c163d81, + 0x91764a8c, + 0x39463186, + 0x80e01686, + 0x048078b8, + 0x90e00060, + 0xc006b031, + 0x70001208, + 0x31818161, + 0x82403d81, + 0x18013980, + 0x4aaa1cf1, + 0x80b01401, + 0x46aa22c0, + 0xb033b0bc, + 0x92f1efa0, + 0x66bc930f, + 0x82017000, + 0x31828162, + 0xef903d82, + 0x930292f1, + 0xa00366bc, + 0x617e64f7, + 0x646280a2, + 0xb050617e, + 0x617e7100, + 0x82d092e0, + 0x46bd2200, + 0x7000b2c0, + 0x22f080a0, + 0xb03042d9, + 0x3162c102, + 0x80a0c001, + 0x42d21e00, + 0x42d322f0, + 0x3160eda0, + 0x62d33960, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006ad4}; PATCH_FUN_SPEC void rf_patch_rfe_genfsk_ant_div(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_genook.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_genook.h index 9451426..728b85d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_genook.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_genook.h @@ -1,492 +1,490 @@ /****************************************************************************** -* Filename: rf_patch_rfe_genook.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 Generic OOK -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - + * Filename: rf_patch_rfe_genook.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 Generic OOK + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_RFE_GENOOK_H #define _RF_PATCH_RFE_GENOOK_H -#include #include "../inc/hw_types.h" +#include #ifndef RFE_PATCH_TYPE - #define RFE_PATCH_TYPE static const uint32_t +#define RFE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_RFERAM_BASE - #define RFC_RFERAM_BASE 0x2100C000 +#define RFC_RFERAM_BASE 0x2100C000 #endif #ifndef RFE_PATCH_MODE - #define RFE_PATCH_MODE 0 +#define RFE_PATCH_MODE 0 #endif RFE_PATCH_TYPE patchGenookRfe[425] = -{ - 0x00006122, - 0x0ec20ec1, - 0x0ec40ec3, - 0x0ec90ec6, - 0x0edf0ecf, - 0x0e3f0eef, - 0x0e3f0e3f, - 0x0e3f0e3f, - 0x0e3f0e3f, - 0x0d0f0e3f, - 0x0d3f0d1f, - 0x0d7f0d5f, - 0x0dbf0d9f, - 0x0dff0ddf, - 0x10000008, - 0x12031101, - 0x24f1004d, - 0x0018002e, - 0x72000a94, - 0x003ffffe, - 0x00ff007f, - 0x403003ff, - 0x40014000, - 0x40074003, - 0x404f400f, - 0x41cf40cf, - 0x47cf43cf, - 0x3fcf4fcf, - 0x1fcf2fcf, - 0x00000fcf, - 0x0008000f, - 0x003f0000, - 0x00000000, - 0x000000c0, - 0x00680004, - 0x00dc000e, - 0x00430006, - 0x0005001a, - 0x00000000, - 0x00000002, - 0x0000003f, - 0x00040000, - 0x000000c0, - 0x00c00004, - 0x00070000, - 0x9100c050, - 0xc0707000, - 0x70009100, - 0x00213182, - 0xb1109131, - 0x81017000, - 0xa100b101, - 0x91323182, - 0x9101b110, - 0x81411011, - 0x406d2241, - 0x700006f1, - 0x9101c051, - 0x39101830, - 0xd0083183, - 0x6f413118, - 0x91310031, - 0x1483b110, - 0x68791614, - 0x10257000, - 0x9100c050, - 0xc2b0c3f4, - 0x6f031420, - 0x04411031, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0x04411031, - 0x3182c082, - 0x91310021, - 0x3963b110, - 0xc0a21031, - 0x00213182, - 0xb1109131, - 0x31151050, - 0x92051405, - 0x645d7000, - 0x1031c052, - 0x31610631, - 0x646002c1, - 0x1031c112, - 0x06713921, - 0x02e13151, - 0x70006460, - 0xb054645d, - 0xa0547100, - 0x80f0b064, - 0x40b32200, - 0xc122c111, - 0xc3006460, - 0x645d68be, - 0x90b01240, - 0x8253b032, - 0x39533953, - 0xc36064a3, - 0x128068c8, - 0xb03290b0, - 0x645d7000, - 0xc122c101, - 0xc1016460, - 0x6460c0c2, - 0x64a38253, - 0x90b012c0, - 0x7000b032, - 0xc272645d, - 0x6460c081, - 0xc111c122, - 0xc0026460, - 0x6460c111, - 0xc331c062, - 0xc3626460, - 0x6460c111, - 0xc111c302, - 0x82536460, - 0x64a33953, - 0x6465c3e2, - 0x40f02211, - 0xc881c242, - 0xc2526460, - 0x6460c111, - 0xcee1c272, - 0xc2026460, - 0x6460c881, - 0xc801c202, - 0xc0b06460, - 0x70006904, - 0xc242645d, - 0x6460c801, - 0xc011c252, - 0xc2726460, - 0x6460c0e1, - 0xc101c002, - 0xc0626460, - 0x6460c301, - 0xc101c122, - 0xc3626460, - 0x6460c101, - 0xc101c302, - 0x82536460, - 0x700064a3, - 0x72057306, - 0x720e720b, - 0x7100b050, - 0xb0608081, - 0x8092a050, - 0x224180a2, - 0x80804543, - 0x0410c1f1, - 0x11011630, - 0x6c011401, - 0x61556154, - 0x61576156, - 0x61596158, - 0x615c615a, - 0x6160615e, - 0x62dd6162, - 0x809162e0, - 0x80823111, - 0x14122a42, - 0x11011632, - 0x6c011421, - 0x61836170, - 0x62e06176, - 0x61836170, - 0x62e06176, - 0x61636163, - 0x61636163, - 0x61636163, - 0x616364b2, - 0x616364cd, - 0x616364da, - 0x61636506, - 0x12106163, - 0x616890b0, - 0x90b01220, - 0x9050c010, - 0x90607a60, - 0x1210720e, - 0x61269030, - 0x674bcff0, - 0xc003c3b4, - 0x6472c3c0, - 0x91507a00, - 0x92107a10, - 0x92207a20, - 0x92307a30, - 0x92407a40, - 0x92607a50, - 0xa0bc6163, - 0xb060a0e1, - 0x80f0a054, - 0x458e2250, - 0x22008040, - 0x618546aa, - 0x674bcfe0, - 0x393080f0, - 0x22100630, - 0x79f14197, - 0x2200619c, - 0x79e1419b, - 0x79d1619c, - 0x822d9191, - 0x39408230, - 0x0410c0f1, - 0xc0121007, - 0x82193072, - 0x0419c0f1, - 0xc0f1821a, - 0x041a394a, - 0xc0f1821e, - 0x041e398e, - 0x10bc10ab, - 0x648110c2, - 0x7aa7c00f, - 0xb003b013, - 0xb053664e, - 0xb013b050, - 0xc0826624, - 0x6635668a, - 0xb0637100, - 0x22018041, - 0x80f046aa, - 0x41c02250, - 0x45c02210, - 0x46c822f0, - 0x668ac082, - 0x392010f0, - 0x81d391c0, - 0x10306654, - 0x4dde18d3, - 0x16130bf3, - 0x49f21ce3, - 0x81e391c3, - 0x61e3143b, - 0x49f21ce3, - 0x81e391c3, - 0x1cab183b, - 0x1c9b4e31, - 0x1cbc4a33, - 0x10b241f2, - 0x22d08210, - 0x80f041f0, - 0x45f22210, - 0x65f36481, - 0x10c061c0, - 0x4a0518b0, - 0x39101003, - 0x41fc1e00, - 0x3807380f, - 0x42152203, - 0x392010f0, - 0x1070180f, - 0x18073920, - 0x10036215, - 0x1801c001, - 0x1e013911, - 0x301f420d, - 0x22033017, - 0x10f04215, - 0x140f3920, - 0x39201070, - 0x66a11407, - 0x06f08230, - 0x80f13110, - 0x06313931, - 0x421f1e01, - 0xb0633810, - 0x6a1f7100, - 0x700010bc, - 0x06f08230, - 0x80f13110, - 0x06313931, - 0x422d1e01, - 0xb0633810, - 0x6a2d7100, - 0x10ab7000, - 0x109b61e7, - 0x10f261e7, - 0x91c23922, - 0x820181d2, - 0x81511812, - 0x82411812, - 0x3d813181, - 0x4a461c12, - 0xb032b0e1, - 0x674bcfd0, - 0x1421c7f1, - 0xc8124e4a, - 0x91729162, - 0x7000b031, - 0xc0061208, - 0x9160c800, - 0x70009170, - 0x10308201, - 0x81511810, - 0x14061810, - 0x824280e1, - 0x3d823182, - 0x4a661c20, - 0x46702211, - 0xb032b0e1, - 0x674bcfc0, - 0x42702211, - 0x1c201a32, - 0xa0e14e70, - 0xdfb0b032, - 0x674b92f2, - 0x39418231, - 0x1e0106f1, - 0x1618427b, - 0x3010c010, - 0x46891c08, - 0xc7f13c16, - 0x4e7f1461, - 0x9166c816, - 0x31818171, - 0x1c163d81, - 0x91764a86, - 0xc006b031, - 0x70001208, - 0x312381b3, - 0x187110f1, - 0x10153c21, - 0x4e931c37, - 0x10376295, - 0x14176296, - 0x4a991c3f, - 0x103f629b, - 0x1e0162a1, - 0x1211469e, - 0x42a11e0f, - 0x10f1181f, - 0x39311471, - 0x063080e0, - 0x14103121, - 0x700090e0, - 0x81628201, - 0x3d823182, - 0x92f1efa0, - 0x674b9302, - 0x6506a003, - 0x81616163, - 0x3d813181, - 0x39808240, - 0x1cf11801, - 0x14014ac7, - 0x22c080b0, - 0xb0bc46c7, - 0xef90b033, - 0x930f92f1, - 0x7000674b, - 0xb063a003, - 0xb054b064, - 0x6506b0e0, - 0x80407100, - 0x46aa2200, - 0x64dab064, - 0x7100a0e0, - 0x22008040, - 0xb06446aa, - 0xb003a054, - 0x80a261c0, - 0x61636481, - 0x39808260, - 0x10083950, - 0x82693128, - 0xc1f13989, - 0xc01b0419, - 0x1c9a79ca, - 0x109a4af0, - 0x62f31209, - 0x1a1918a9, - 0xb0e1c00b, - 0xb064b054, - 0x80f07100, - 0x47382240, - 0x42fd2210, - 0x645a631a, - 0x1e1b1090, - 0xc0214308, - 0x10001401, - 0x673a1000, - 0x67426b01, - 0xc131b101, - 0x6f1214a1, - 0xb1109132, - 0x1a1010a0, - 0x1401c131, - 0x10001000, - 0x6b10673a, - 0xc0c2c101, - 0x62f56460, - 0x645d6742, - 0xc0c2c111, - 0x10a06460, - 0x10a2c131, - 0x14211802, - 0x6b20673a, - 0x43371e1b, - 0xc021a101, - 0x91326f12, - 0x1090b110, - 0x43371e00, - 0xc0211a10, - 0x18021092, - 0x673a1421, - 0x62f56b31, - 0x6163a054, - 0x10801004, - 0x10406b3c, - 0x91326f12, - 0x7000b110, - 0x9101c051, - 0x3182c0e2, - 0x0002cc00, - 0xb1109132, - 0x92e07000, - 0x220082d0, - 0xb2c0474c, - 0x00007000 -}; + { + 0x00006122, + 0x0ec20ec1, + 0x0ec40ec3, + 0x0ec90ec6, + 0x0edf0ecf, + 0x0e3f0eef, + 0x0e3f0e3f, + 0x0e3f0e3f, + 0x0e3f0e3f, + 0x0d0f0e3f, + 0x0d3f0d1f, + 0x0d7f0d5f, + 0x0dbf0d9f, + 0x0dff0ddf, + 0x10000008, + 0x12031101, + 0x24f1004d, + 0x0018002e, + 0x72000a94, + 0x003ffffe, + 0x00ff007f, + 0x403003ff, + 0x40014000, + 0x40074003, + 0x404f400f, + 0x41cf40cf, + 0x47cf43cf, + 0x3fcf4fcf, + 0x1fcf2fcf, + 0x00000fcf, + 0x0008000f, + 0x003f0000, + 0x00000000, + 0x000000c0, + 0x00680004, + 0x00dc000e, + 0x00430006, + 0x0005001a, + 0x00000000, + 0x00000002, + 0x0000003f, + 0x00040000, + 0x000000c0, + 0x00c00004, + 0x00070000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x406d2241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x68791614, + 0x10257000, + 0x9100c050, + 0xc2b0c3f4, + 0x6f031420, + 0x04411031, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x645d7000, + 0x1031c052, + 0x31610631, + 0x646002c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006460, + 0xb054645d, + 0xa0547100, + 0x80f0b064, + 0x40b32200, + 0xc122c111, + 0xc3006460, + 0x645d68be, + 0x90b01240, + 0x8253b032, + 0x39533953, + 0xc36064a3, + 0x128068c8, + 0xb03290b0, + 0x645d7000, + 0xc122c101, + 0xc1016460, + 0x6460c0c2, + 0x64a38253, + 0x90b012c0, + 0x7000b032, + 0xc272645d, + 0x6460c081, + 0xc111c122, + 0xc0026460, + 0x6460c111, + 0xc331c062, + 0xc3626460, + 0x6460c111, + 0xc111c302, + 0x82536460, + 0x64a33953, + 0x6465c3e2, + 0x40f02211, + 0xc881c242, + 0xc2526460, + 0x6460c111, + 0xcee1c272, + 0xc2026460, + 0x6460c881, + 0xc801c202, + 0xc0b06460, + 0x70006904, + 0xc242645d, + 0x6460c801, + 0xc011c252, + 0xc2726460, + 0x6460c0e1, + 0xc101c002, + 0xc0626460, + 0x6460c301, + 0xc101c122, + 0xc3626460, + 0x6460c101, + 0xc101c302, + 0x82536460, + 0x700064a3, + 0x72057306, + 0x720e720b, + 0x7100b050, + 0xb0608081, + 0x8092a050, + 0x224180a2, + 0x80804543, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x61556154, + 0x61576156, + 0x61596158, + 0x615c615a, + 0x6160615e, + 0x62dd6162, + 0x809162e0, + 0x80823111, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x61836170, + 0x62e06176, + 0x61836170, + 0x62e06176, + 0x61636163, + 0x61636163, + 0x61636163, + 0x616364b2, + 0x616364cd, + 0x616364da, + 0x61636506, + 0x12106163, + 0x616890b0, + 0x90b01220, + 0x9050c010, + 0x90607a60, + 0x1210720e, + 0x61269030, + 0x674bcff0, + 0xc003c3b4, + 0x6472c3c0, + 0x91507a00, + 0x92107a10, + 0x92207a20, + 0x92307a30, + 0x92407a40, + 0x92607a50, + 0xa0bc6163, + 0xb060a0e1, + 0x80f0a054, + 0x458e2250, + 0x22008040, + 0x618546aa, + 0x674bcfe0, + 0x393080f0, + 0x22100630, + 0x79f14197, + 0x2200619c, + 0x79e1419b, + 0x79d1619c, + 0x822d9191, + 0x39408230, + 0x0410c0f1, + 0xc0121007, + 0x82193072, + 0x0419c0f1, + 0xc0f1821a, + 0x041a394a, + 0xc0f1821e, + 0x041e398e, + 0x10bc10ab, + 0x648110c2, + 0x7aa7c00f, + 0xb003b013, + 0xb053664e, + 0xb013b050, + 0xc0826624, + 0x6635668a, + 0xb0637100, + 0x22018041, + 0x80f046aa, + 0x41c02250, + 0x45c02210, + 0x46c822f0, + 0x668ac082, + 0x392010f0, + 0x81d391c0, + 0x10306654, + 0x4dde18d3, + 0x16130bf3, + 0x49f21ce3, + 0x81e391c3, + 0x61e3143b, + 0x49f21ce3, + 0x81e391c3, + 0x1cab183b, + 0x1c9b4e31, + 0x1cbc4a33, + 0x10b241f2, + 0x22d08210, + 0x80f041f0, + 0x45f22210, + 0x65f36481, + 0x10c061c0, + 0x4a0518b0, + 0x39101003, + 0x41fc1e00, + 0x3807380f, + 0x42152203, + 0x392010f0, + 0x1070180f, + 0x18073920, + 0x10036215, + 0x1801c001, + 0x1e013911, + 0x301f420d, + 0x22033017, + 0x10f04215, + 0x140f3920, + 0x39201070, + 0x66a11407, + 0x06f08230, + 0x80f13110, + 0x06313931, + 0x421f1e01, + 0xb0633810, + 0x6a1f7100, + 0x700010bc, + 0x06f08230, + 0x80f13110, + 0x06313931, + 0x422d1e01, + 0xb0633810, + 0x6a2d7100, + 0x10ab7000, + 0x109b61e7, + 0x10f261e7, + 0x91c23922, + 0x820181d2, + 0x81511812, + 0x82411812, + 0x3d813181, + 0x4a461c12, + 0xb032b0e1, + 0x674bcfd0, + 0x1421c7f1, + 0xc8124e4a, + 0x91729162, + 0x7000b031, + 0xc0061208, + 0x9160c800, + 0x70009170, + 0x10308201, + 0x81511810, + 0x14061810, + 0x824280e1, + 0x3d823182, + 0x4a661c20, + 0x46702211, + 0xb032b0e1, + 0x674bcfc0, + 0x42702211, + 0x1c201a32, + 0xa0e14e70, + 0xdfb0b032, + 0x674b92f2, + 0x39418231, + 0x1e0106f1, + 0x1618427b, + 0x3010c010, + 0x46891c08, + 0xc7f13c16, + 0x4e7f1461, + 0x9166c816, + 0x31818171, + 0x1c163d81, + 0x91764a86, + 0xc006b031, + 0x70001208, + 0x312381b3, + 0x187110f1, + 0x10153c21, + 0x4e931c37, + 0x10376295, + 0x14176296, + 0x4a991c3f, + 0x103f629b, + 0x1e0162a1, + 0x1211469e, + 0x42a11e0f, + 0x10f1181f, + 0x39311471, + 0x063080e0, + 0x14103121, + 0x700090e0, + 0x81628201, + 0x3d823182, + 0x92f1efa0, + 0x674b9302, + 0x6506a003, + 0x81616163, + 0x3d813181, + 0x39808240, + 0x1cf11801, + 0x14014ac7, + 0x22c080b0, + 0xb0bc46c7, + 0xef90b033, + 0x930f92f1, + 0x7000674b, + 0xb063a003, + 0xb054b064, + 0x6506b0e0, + 0x80407100, + 0x46aa2200, + 0x64dab064, + 0x7100a0e0, + 0x22008040, + 0xb06446aa, + 0xb003a054, + 0x80a261c0, + 0x61636481, + 0x39808260, + 0x10083950, + 0x82693128, + 0xc1f13989, + 0xc01b0419, + 0x1c9a79ca, + 0x109a4af0, + 0x62f31209, + 0x1a1918a9, + 0xb0e1c00b, + 0xb064b054, + 0x80f07100, + 0x47382240, + 0x42fd2210, + 0x645a631a, + 0x1e1b1090, + 0xc0214308, + 0x10001401, + 0x673a1000, + 0x67426b01, + 0xc131b101, + 0x6f1214a1, + 0xb1109132, + 0x1a1010a0, + 0x1401c131, + 0x10001000, + 0x6b10673a, + 0xc0c2c101, + 0x62f56460, + 0x645d6742, + 0xc0c2c111, + 0x10a06460, + 0x10a2c131, + 0x14211802, + 0x6b20673a, + 0x43371e1b, + 0xc021a101, + 0x91326f12, + 0x1090b110, + 0x43371e00, + 0xc0211a10, + 0x18021092, + 0x673a1421, + 0x62f56b31, + 0x6163a054, + 0x10801004, + 0x10406b3c, + 0x91326f12, + 0x7000b110, + 0x9101c051, + 0x3182c0e2, + 0x0002cc00, + 0xb1109132, + 0x92e07000, + 0x220082d0, + 0xb2c0474c, + 0x00007000}; PATCH_FUN_SPEC void rf_patch_rfe_genook(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_ghs.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_ghs.h index 7834560..b8fdf24 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_ghs.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_ghs.h @@ -1,565 +1,563 @@ /****************************************************************************** -* Filename: rf_patch_rfe_ghs.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 Generic 4FSK up to 1.5Mbps -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - + * Filename: rf_patch_rfe_ghs.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 Generic 4FSK up to 1.5Mbps + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_RFE_GHS_H #define _RF_PATCH_RFE_GHS_H -#include #include "../inc/hw_types.h" +#include #ifndef RFE_PATCH_TYPE - #define RFE_PATCH_TYPE static const uint32_t +#define RFE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_RFERAM_BASE - #define RFC_RFERAM_BASE 0x2100C000 +#define RFC_RFERAM_BASE 0x2100C000 #endif #ifndef RFE_PATCH_MODE - #define RFE_PATCH_MODE 0 +#define RFE_PATCH_MODE 0 #endif RFE_PATCH_TYPE patchGhsRfe[498] = -{ - 0x00006256, - 0x1307147f, - 0x24f1004d, - 0x3f131f2e, - 0x0100003f, - 0xff071f00, - 0x4030f00f, - 0x40014000, - 0x40074003, - 0x404f400f, - 0x41cf40cf, - 0x47cf43cf, - 0x3fcf4fcf, - 0x1fcf2fcf, - 0x00000fcf, - 0x00000000, - 0x00000000, - 0x00000000, - 0x000000a5, - 0x00000000, - 0x000000a5, - 0x00000000, - 0x000000a5, - 0x00000000, - 0x000000a5, - 0x00000000, - 0x000000a5, - 0x00000000, - 0x000000a5, - 0x00000000, - 0x000000a5, - 0x00000000, - 0x000000a5, - 0x00000000, - 0x000000a5, - 0x00000000, - 0x000000a5, - 0x00000000, - 0x005500a5, - 0x00550055, - 0x00550050, - 0x00550055, - 0x00aa0050, - 0x00aa00aa, - 0x00aa0005, - 0x00aa00aa, - 0x00000005, - 0x00000000, - 0x00000000, - 0x00000000, - 0x000f0000, - 0x00000008, - 0x0000003f, - 0x003f0040, - 0x00040000, - 0x000e0068, - 0x000600dc, - 0x001a0043, - 0x00000005, - 0x00020000, - 0x003f0000, - 0x00000000, - 0x00c00004, - 0x00040000, - 0x000000c0, - 0x00000007, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xc0500000, - 0x70009100, - 0x9100c070, - 0x31827000, - 0x91310021, - 0x7000b110, - 0xb1018101, - 0x3182a100, - 0xb1109132, - 0x10119101, - 0x22418141, - 0x06f140a0, - 0xc0517000, - 0x18309101, - 0x31833910, - 0x3118d008, - 0x00316f41, - 0xb1109131, - 0x16141483, - 0x700068ac, - 0xc0501025, - 0xc3f49100, - 0x1420c0d0, - 0x10316f03, - 0xc0220441, - 0x00213182, - 0xb1109131, - 0x10313963, - 0xc0820441, - 0x00213182, - 0xb1109131, - 0x10313963, - 0x3182c0a2, - 0x91310021, - 0x1052b110, - 0x31151050, - 0x92051405, - 0x39448244, - 0x31431023, - 0x92431443, - 0x10308243, - 0xc1d13920, - 0x6f151401, - 0x31130633, - 0x40e71e03, - 0x06353835, - 0x1c2440ef, - 0x26f54cee, - 0x60ef90e5, - 0x700090e5, - 0xc0526490, - 0x06311031, - 0x02c13161, - 0xc1126493, - 0x39211031, - 0x31510671, - 0x649302e1, - 0x82207000, - 0x041078a1, - 0x663d4168, - 0xc088664c, - 0x39508220, - 0x1e003980, - 0xc041410e, - 0x14183001, - 0xc0891a18, - 0x39608230, - 0x1e003980, - 0xc0414118, - 0x14193001, - 0x648d1a19, - 0xb1109136, - 0xb1109134, - 0x7100b054, - 0xb064a054, - 0x220080f0, - 0x1240411e, - 0xb03290b0, - 0xc1116490, - 0x6493c122, - 0x692dc170, - 0xc0c2c111, - 0xc1706493, - 0xc0506932, - 0x72279100, - 0x16159298, - 0x10421614, - 0xc1f01053, - 0x31318221, - 0x39813931, - 0xb0513131, - 0x6625b270, - 0x92997227, - 0x1062b270, - 0xc3f01073, - 0x31218231, - 0x39813921, - 0x6625101b, - 0x3182c0e2, - 0x31808260, - 0x00023980, - 0x7100b061, - 0xb1109132, - 0xb061a051, - 0x82537227, - 0x39533953, - 0xc23064f0, - 0x00006962, - 0x90b01280, - 0x7000b032, - 0x9101c051, - 0xc0e2cc01, - 0x64906493, - 0xc0c2c111, - 0xb0546493, - 0xa0547100, - 0x80f0b064, - 0x41712200, - 0x90b01240, - 0xc2f0b032, - 0xc111697c, - 0x6493c122, - 0x6981c0b0, - 0x9101c051, - 0x3182c0e2, - 0x00028260, - 0xb1109132, - 0x39538253, - 0x64f03953, - 0x698fc050, - 0x12800000, - 0xb03290b0, - 0x82537000, - 0x821064f0, - 0x419d22f0, - 0x0000c960, - 0x8220699b, - 0x041078a1, - 0xc05041d0, - 0x72279100, - 0x10629299, - 0xc3f01073, - 0x31218231, - 0x39813921, - 0xb270b051, - 0x72276631, - 0xb2709298, - 0x10531042, - 0x8221c1f0, - 0x39313131, - 0x31313981, - 0x6631101a, - 0xb061a051, - 0xc0b07227, - 0x649069c0, - 0xc122c101, - 0xc1016493, - 0x6493c0c2, - 0x648d1a15, - 0xb1109135, - 0x90b012c0, - 0x7000b032, - 0xc1016490, - 0x6493c122, - 0xc0c2c101, - 0x82536493, - 0x12c064f0, - 0xb03290b0, - 0x64907000, - 0xc081c272, - 0xc1226493, - 0x6493c111, - 0xc111c002, - 0xc0626493, - 0x6493c331, - 0xc111c362, - 0xc3026493, - 0x6493c111, - 0x39538253, - 0xc3e264f0, - 0x22116498, - 0xc24241f3, - 0x6493c881, - 0xc111c252, - 0xc2726493, - 0x6493cee1, - 0xc881c202, - 0xc2026493, - 0x6493c801, - 0x6a07c0b0, - 0x64907000, - 0xc801c242, - 0xc2526493, - 0x6493c011, - 0xc0e1c272, - 0xc0026493, - 0x6493c101, - 0xc301c062, - 0xc1226493, - 0x6493c101, - 0xc101c362, - 0xc3026493, - 0x6493c101, - 0x64f08253, - 0xb0617000, - 0x14127100, - 0x4e2d1c23, - 0xb1109133, - 0x91327000, - 0x6a25b110, - 0xb0617000, - 0x18137100, - 0x4a391c32, - 0xb1109132, - 0x91337000, - 0x6a31b110, - 0xc0c27000, - 0x10156498, - 0x1612c0c2, - 0x31416498, - 0xc0c01415, - 0x14053180, - 0x78b01054, - 0x70000404, - 0x3186c0e6, - 0x1416cc01, - 0x82611067, - 0x0401c3f0, - 0x70001417, - 0x72057306, - 0x720e720b, - 0x7100b050, - 0xb0608081, - 0x8092a050, - 0x46762241, - 0xc1f18080, - 0x16300410, - 0x14011101, - 0x62896c01, - 0x628b628a, - 0x628d628c, - 0x628f628e, - 0x62936291, - 0x62896295, - 0x63db63d8, - 0xc0f28091, - 0x31210421, - 0x2a428082, - 0x16321412, - 0x14211101, - 0x629f6c01, - 0x62a562bb, - 0x629f63db, - 0x62a562bb, - 0x629763db, - 0x62976297, - 0x62976297, - 0x64ff6297, - 0x65956297, - 0x65dd6297, - 0x66096297, - 0x12106297, - 0x720e90b0, - 0x72057306, - 0x90301210, - 0xcff0625a, - 0xc64467de, - 0xc3c0c003, - 0x784064a5, - 0x78509150, - 0x78609210, - 0x78709220, - 0x78809230, - 0x78909260, - 0x78309290, - 0x82109190, - 0x06f03940, - 0x31101001, - 0x92001410, - 0xa0e06297, - 0x80f0a054, - 0x46c42250, - 0x22008040, - 0x62bc47cd, - 0x822da040, - 0x398d318d, - 0xc0f18210, - 0x10090410, - 0x394a821a, - 0x8210041a, - 0x04103980, - 0x10ab100e, - 0x10c010bc, - 0x14c03140, - 0x10c29240, - 0xcfe064b4, - 0xb01367de, - 0x67a3b003, - 0xb050b053, - 0xb064b054, - 0x675bb013, - 0x22e08210, - 0x679446ee, - 0x91c081b0, - 0xb06381d5, - 0x80417100, - 0x47cd2201, - 0x221080f0, - 0xb064472a, - 0x42ee2231, - 0x81b0b063, - 0x81d391c0, - 0x4f0118d3, - 0x67a981d5, - 0x710062ee, - 0x22018041, - 0x80f047cd, - 0x472a2210, - 0x2231b064, - 0xb0634301, - 0x91c081b0, - 0x105081d3, - 0x18301035, - 0x4eee16a0, - 0x4aee18d3, - 0x1cbc6750, - 0x10b242ee, - 0x10bc64b4, - 0xcfd0675b, - 0x637267de, - 0x221080f0, - 0x10a2472a, - 0x675b64b4, - 0x675b675b, - 0x62c4675b, - 0x816fb064, - 0x3d8f318f, - 0x92ffdfc0, - 0x710067de, - 0x22018041, - 0xb06447cd, - 0x225080f0, - 0xb0634345, - 0x22c18211, - 0x67a9473f, - 0x82116331, - 0x473122d1, - 0x221080f0, - 0x8161472a, - 0x31818172, - 0x31823d81, - 0xefb03d82, - 0x930292f1, - 0x62bb67de, - 0x81e391c3, - 0x1cab183b, - 0x10ab4b57, - 0x1c9b7000, - 0x109b4f5a, - 0x82307000, - 0x823106f0, - 0x06f13941, - 0x3012c012, - 0x7100b063, - 0x436d1e01, - 0x81611618, - 0x3d813181, - 0x1c281416, - 0xb0314770, - 0xc006c008, - 0x70006b62, - 0xb0638290, - 0x80417100, - 0x47cd2201, - 0x221180f1, - 0x10074793, - 0x91c081b0, - 0x18d381d3, - 0x4b8e18e3, - 0x675014e3, - 0x438e1cbc, - 0x64b410b2, - 0x820310bc, - 0x92f3dfa0, - 0x675b67de, - 0x107067a9, - 0xcf906b73, - 0x632067de, - 0x91c281b2, - 0x820181d2, - 0x81511812, - 0xc7f11812, - 0x4f9f1421, - 0x9162c812, - 0xb0319172, - 0xc0087000, - 0xc800c006, - 0x91709160, - 0x82017000, - 0x91c081b0, - 0x181081d0, - 0x18108151, - 0x82311406, - 0x06f13941, - 0x43be1e01, - 0xc0101618, - 0x1c083010, - 0x106047cc, - 0x10063c10, - 0x1461c7f1, - 0xc8164fc2, - 0x81719166, - 0x3d813181, - 0x4bc91c16, - 0xb0319176, - 0xc008c006, - 0x82017000, - 0x31828162, - 0xef803d82, - 0x930292f1, - 0xa00367de, - 0x62976609, - 0x64b480a2, - 0xb0506297, - 0x62977100, - 0x82d092e0, - 0x47df2200, - 0x7000b2c0 -}; + { + 0x00006256, + 0x1307147f, + 0x24f1004d, + 0x3f131f2e, + 0x0100003f, + 0xff071f00, + 0x4030f00f, + 0x40014000, + 0x40074003, + 0x404f400f, + 0x41cf40cf, + 0x47cf43cf, + 0x3fcf4fcf, + 0x1fcf2fcf, + 0x00000fcf, + 0x00000000, + 0x00000000, + 0x00000000, + 0x000000a5, + 0x00000000, + 0x000000a5, + 0x00000000, + 0x000000a5, + 0x00000000, + 0x000000a5, + 0x00000000, + 0x000000a5, + 0x00000000, + 0x000000a5, + 0x00000000, + 0x000000a5, + 0x00000000, + 0x000000a5, + 0x00000000, + 0x000000a5, + 0x00000000, + 0x000000a5, + 0x00000000, + 0x005500a5, + 0x00550055, + 0x00550050, + 0x00550055, + 0x00aa0050, + 0x00aa00aa, + 0x00aa0005, + 0x00aa00aa, + 0x00000005, + 0x00000000, + 0x00000000, + 0x00000000, + 0x000f0000, + 0x00000008, + 0x0000003f, + 0x003f0040, + 0x00040000, + 0x000e0068, + 0x000600dc, + 0x001a0043, + 0x00000005, + 0x00020000, + 0x003f0000, + 0x00000000, + 0x00c00004, + 0x00040000, + 0x000000c0, + 0x00000007, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0500000, + 0x70009100, + 0x9100c070, + 0x31827000, + 0x91310021, + 0x7000b110, + 0xb1018101, + 0x3182a100, + 0xb1109132, + 0x10119101, + 0x22418141, + 0x06f140a0, + 0xc0517000, + 0x18309101, + 0x31833910, + 0x3118d008, + 0x00316f41, + 0xb1109131, + 0x16141483, + 0x700068ac, + 0xc0501025, + 0xc3f49100, + 0x1420c0d0, + 0x10316f03, + 0xc0220441, + 0x00213182, + 0xb1109131, + 0x10313963, + 0xc0820441, + 0x00213182, + 0xb1109131, + 0x10313963, + 0x3182c0a2, + 0x91310021, + 0x1052b110, + 0x31151050, + 0x92051405, + 0x39448244, + 0x31431023, + 0x92431443, + 0x10308243, + 0xc1d13920, + 0x6f151401, + 0x31130633, + 0x40e71e03, + 0x06353835, + 0x1c2440ef, + 0x26f54cee, + 0x60ef90e5, + 0x700090e5, + 0xc0526490, + 0x06311031, + 0x02c13161, + 0xc1126493, + 0x39211031, + 0x31510671, + 0x649302e1, + 0x82207000, + 0x041078a1, + 0x663d4168, + 0xc088664c, + 0x39508220, + 0x1e003980, + 0xc041410e, + 0x14183001, + 0xc0891a18, + 0x39608230, + 0x1e003980, + 0xc0414118, + 0x14193001, + 0x648d1a19, + 0xb1109136, + 0xb1109134, + 0x7100b054, + 0xb064a054, + 0x220080f0, + 0x1240411e, + 0xb03290b0, + 0xc1116490, + 0x6493c122, + 0x692dc170, + 0xc0c2c111, + 0xc1706493, + 0xc0506932, + 0x72279100, + 0x16159298, + 0x10421614, + 0xc1f01053, + 0x31318221, + 0x39813931, + 0xb0513131, + 0x6625b270, + 0x92997227, + 0x1062b270, + 0xc3f01073, + 0x31218231, + 0x39813921, + 0x6625101b, + 0x3182c0e2, + 0x31808260, + 0x00023980, + 0x7100b061, + 0xb1109132, + 0xb061a051, + 0x82537227, + 0x39533953, + 0xc23064f0, + 0x00006962, + 0x90b01280, + 0x7000b032, + 0x9101c051, + 0xc0e2cc01, + 0x64906493, + 0xc0c2c111, + 0xb0546493, + 0xa0547100, + 0x80f0b064, + 0x41712200, + 0x90b01240, + 0xc2f0b032, + 0xc111697c, + 0x6493c122, + 0x6981c0b0, + 0x9101c051, + 0x3182c0e2, + 0x00028260, + 0xb1109132, + 0x39538253, + 0x64f03953, + 0x698fc050, + 0x12800000, + 0xb03290b0, + 0x82537000, + 0x821064f0, + 0x419d22f0, + 0x0000c960, + 0x8220699b, + 0x041078a1, + 0xc05041d0, + 0x72279100, + 0x10629299, + 0xc3f01073, + 0x31218231, + 0x39813921, + 0xb270b051, + 0x72276631, + 0xb2709298, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0x6631101a, + 0xb061a051, + 0xc0b07227, + 0x649069c0, + 0xc122c101, + 0xc1016493, + 0x6493c0c2, + 0x648d1a15, + 0xb1109135, + 0x90b012c0, + 0x7000b032, + 0xc1016490, + 0x6493c122, + 0xc0c2c101, + 0x82536493, + 0x12c064f0, + 0xb03290b0, + 0x64907000, + 0xc081c272, + 0xc1226493, + 0x6493c111, + 0xc111c002, + 0xc0626493, + 0x6493c331, + 0xc111c362, + 0xc3026493, + 0x6493c111, + 0x39538253, + 0xc3e264f0, + 0x22116498, + 0xc24241f3, + 0x6493c881, + 0xc111c252, + 0xc2726493, + 0x6493cee1, + 0xc881c202, + 0xc2026493, + 0x6493c801, + 0x6a07c0b0, + 0x64907000, + 0xc801c242, + 0xc2526493, + 0x6493c011, + 0xc0e1c272, + 0xc0026493, + 0x6493c101, + 0xc301c062, + 0xc1226493, + 0x6493c101, + 0xc101c362, + 0xc3026493, + 0x6493c101, + 0x64f08253, + 0xb0617000, + 0x14127100, + 0x4e2d1c23, + 0xb1109133, + 0x91327000, + 0x6a25b110, + 0xb0617000, + 0x18137100, + 0x4a391c32, + 0xb1109132, + 0x91337000, + 0x6a31b110, + 0xc0c27000, + 0x10156498, + 0x1612c0c2, + 0x31416498, + 0xc0c01415, + 0x14053180, + 0x78b01054, + 0x70000404, + 0x3186c0e6, + 0x1416cc01, + 0x82611067, + 0x0401c3f0, + 0x70001417, + 0x72057306, + 0x720e720b, + 0x7100b050, + 0xb0608081, + 0x8092a050, + 0x46762241, + 0xc1f18080, + 0x16300410, + 0x14011101, + 0x62896c01, + 0x628b628a, + 0x628d628c, + 0x628f628e, + 0x62936291, + 0x62896295, + 0x63db63d8, + 0xc0f28091, + 0x31210421, + 0x2a428082, + 0x16321412, + 0x14211101, + 0x629f6c01, + 0x62a562bb, + 0x629f63db, + 0x62a562bb, + 0x629763db, + 0x62976297, + 0x62976297, + 0x64ff6297, + 0x65956297, + 0x65dd6297, + 0x66096297, + 0x12106297, + 0x720e90b0, + 0x72057306, + 0x90301210, + 0xcff0625a, + 0xc64467de, + 0xc3c0c003, + 0x784064a5, + 0x78509150, + 0x78609210, + 0x78709220, + 0x78809230, + 0x78909260, + 0x78309290, + 0x82109190, + 0x06f03940, + 0x31101001, + 0x92001410, + 0xa0e06297, + 0x80f0a054, + 0x46c42250, + 0x22008040, + 0x62bc47cd, + 0x822da040, + 0x398d318d, + 0xc0f18210, + 0x10090410, + 0x394a821a, + 0x8210041a, + 0x04103980, + 0x10ab100e, + 0x10c010bc, + 0x14c03140, + 0x10c29240, + 0xcfe064b4, + 0xb01367de, + 0x67a3b003, + 0xb050b053, + 0xb064b054, + 0x675bb013, + 0x22e08210, + 0x679446ee, + 0x91c081b0, + 0xb06381d5, + 0x80417100, + 0x47cd2201, + 0x221080f0, + 0xb064472a, + 0x42ee2231, + 0x81b0b063, + 0x81d391c0, + 0x4f0118d3, + 0x67a981d5, + 0x710062ee, + 0x22018041, + 0x80f047cd, + 0x472a2210, + 0x2231b064, + 0xb0634301, + 0x91c081b0, + 0x105081d3, + 0x18301035, + 0x4eee16a0, + 0x4aee18d3, + 0x1cbc6750, + 0x10b242ee, + 0x10bc64b4, + 0xcfd0675b, + 0x637267de, + 0x221080f0, + 0x10a2472a, + 0x675b64b4, + 0x675b675b, + 0x62c4675b, + 0x816fb064, + 0x3d8f318f, + 0x92ffdfc0, + 0x710067de, + 0x22018041, + 0xb06447cd, + 0x225080f0, + 0xb0634345, + 0x22c18211, + 0x67a9473f, + 0x82116331, + 0x473122d1, + 0x221080f0, + 0x8161472a, + 0x31818172, + 0x31823d81, + 0xefb03d82, + 0x930292f1, + 0x62bb67de, + 0x81e391c3, + 0x1cab183b, + 0x10ab4b57, + 0x1c9b7000, + 0x109b4f5a, + 0x82307000, + 0x823106f0, + 0x06f13941, + 0x3012c012, + 0x7100b063, + 0x436d1e01, + 0x81611618, + 0x3d813181, + 0x1c281416, + 0xb0314770, + 0xc006c008, + 0x70006b62, + 0xb0638290, + 0x80417100, + 0x47cd2201, + 0x221180f1, + 0x10074793, + 0x91c081b0, + 0x18d381d3, + 0x4b8e18e3, + 0x675014e3, + 0x438e1cbc, + 0x64b410b2, + 0x820310bc, + 0x92f3dfa0, + 0x675b67de, + 0x107067a9, + 0xcf906b73, + 0x632067de, + 0x91c281b2, + 0x820181d2, + 0x81511812, + 0xc7f11812, + 0x4f9f1421, + 0x9162c812, + 0xb0319172, + 0xc0087000, + 0xc800c006, + 0x91709160, + 0x82017000, + 0x91c081b0, + 0x181081d0, + 0x18108151, + 0x82311406, + 0x06f13941, + 0x43be1e01, + 0xc0101618, + 0x1c083010, + 0x106047cc, + 0x10063c10, + 0x1461c7f1, + 0xc8164fc2, + 0x81719166, + 0x3d813181, + 0x4bc91c16, + 0xb0319176, + 0xc008c006, + 0x82017000, + 0x31828162, + 0xef803d82, + 0x930292f1, + 0xa00367de, + 0x62976609, + 0x64b480a2, + 0xb0506297, + 0x62977100, + 0x82d092e0, + 0x47df2200, + 0x7000b2c0}; PATCH_FUN_SPEC void rf_patch_rfe_ghs(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_hsp_4mbps.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_hsp_4mbps.h index be35b00..2d5cfc1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_hsp_4mbps.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_hsp_4mbps.h @@ -1,388 +1,386 @@ /****************************************************************************** -* Filename: rf_patch_rfe_hsp_4mbps.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 4Mbps High speed mode -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - + * Filename: rf_patch_rfe_hsp_4mbps.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 4Mbps High speed mode + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_RFE_HSP_4MBPS_H #define _RF_PATCH_RFE_HSP_4MBPS_H -#include #include "../inc/hw_types.h" +#include #ifndef RFE_PATCH_TYPE - #define RFE_PATCH_TYPE static const uint32_t +#define RFE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_RFERAM_BASE - #define RFC_RFERAM_BASE 0x2100C000 +#define RFC_RFERAM_BASE 0x2100C000 #endif #ifndef RFE_PATCH_MODE - #define RFE_PATCH_MODE 0 +#define RFE_PATCH_MODE 0 #endif RFE_PATCH_TYPE patchHsp4mbpsRfe[321] = -{ - 0x0000611f, - 0x000f0000, - 0x00000008, - 0x0000003f, - 0x003f0040, - 0x00040000, - 0x000e0068, - 0x000600dc, - 0x001a0043, - 0x00000005, - 0x00020000, - 0x00000000, - 0x00000000, - 0x00c00004, - 0x00040000, - 0x000000c0, - 0x40300007, - 0x40014000, - 0x40074003, - 0x404f400f, - 0x41cf40cf, - 0x47cf43cf, - 0x3fcf4fcf, - 0x1fcf2fcf, - 0x02070fcf, - 0x4040067f, - 0x40404040, - 0x20403040, - 0x00401040, - 0x01c000c0, - 0x07c003c0, - 0x0fc10fc0, - 0x0fc70fc3, - 0xc0500fcf, - 0x70009100, - 0x9100c070, - 0x31827000, - 0x91310021, - 0x7000b110, - 0xb1018101, - 0x3182a100, - 0xb1109132, - 0x10119101, - 0x22418141, - 0x06f14056, - 0xc0517000, - 0x18309101, - 0x31833910, - 0x3118d008, - 0x00316f41, - 0xb1109131, - 0x16141483, - 0x70006862, - 0xc0501025, - 0xc3f49100, - 0x1420c210, - 0x10316f03, - 0xc0220441, - 0x00213182, - 0xb1109131, - 0x10313963, - 0xc0820441, - 0x00213182, - 0xb1109131, - 0x10313963, - 0x3182c0a2, - 0x91310021, - 0x1050b110, - 0x14053115, - 0x70009205, - 0xc0526446, - 0x06311031, - 0x02c13161, - 0xc1126449, - 0x39211031, - 0x31510671, - 0x644902e1, - 0xc0517000, - 0xcc019101, - 0x6449c0e2, - 0xc1116446, - 0x6449c0c2, - 0x7100b054, - 0xb064a054, - 0x220080f0, - 0xc11140a4, - 0x6449c122, - 0x9101c051, - 0x3182c0e2, - 0x00028260, - 0xb1109132, - 0x68b7c300, - 0x12406446, - 0xb03290b0, - 0x39538253, - 0x648c3953, - 0x68c1c360, - 0x90b01280, - 0x7000b032, - 0xc1016446, - 0x6449c122, - 0xc0c2c101, - 0x82536449, - 0x12c0648c, - 0xb03290b0, - 0x64467000, - 0xc081c272, - 0xc1226449, - 0x6449c111, - 0xc111c002, - 0xc0626449, - 0x6449c331, - 0xc111c362, - 0xc3026449, - 0x6449c111, - 0x39538253, - 0xc3e2648c, - 0x2211644e, - 0xc24240e9, - 0x6449c881, - 0xc111c252, - 0xc2726449, - 0x6449cee1, - 0xc881c202, - 0xc2026449, - 0x6449c801, - 0x68fdc0b0, - 0x64467000, - 0xc801c242, - 0xc2526449, - 0x6449c011, - 0xc0e1c272, - 0xc0026449, - 0x6449c101, - 0xc301c062, - 0xc1226449, - 0x6449c101, - 0xc101c362, - 0xc3026449, - 0x6449c101, - 0x648c8253, - 0x00007000, - 0x00000000, - 0x73060000, - 0x720b7205, - 0xb050720e, - 0xb0607100, - 0x8081a050, - 0x22418092, - 0x8080453e, - 0x0410c1f1, - 0x11011630, - 0x6c011401, - 0x61526151, - 0x61546153, - 0x61566155, - 0x61596157, - 0x615d615b, - 0x6151615f, - 0xc0f28091, - 0x31210421, - 0x2a428082, - 0x16321412, - 0x14211101, - 0x61706c01, - 0x6174618b, - 0x61706151, - 0x6174618b, - 0x61616151, - 0x61616161, - 0x61616161, - 0x649b6161, - 0x64c66161, - 0x64d36161, - 0x64ff6161, - 0x666e6161, - 0x12106161, - 0x616690b0, - 0x90b01220, - 0x7306720e, - 0x12107205, - 0x61239030, - 0x00000000, - 0x00000000, - 0xc003c024, - 0x645bc3c0, - 0x9159c4b9, - 0x9160c800, - 0x9200c2d0, - 0x9260c3f0, - 0x3140c060, - 0x0010c0f1, - 0xc0213140, - 0x92100010, - 0x9221c371, - 0x00006161, - 0x00000000, - 0x73060000, - 0x82188159, - 0x108f108e, - 0x041ec0f1, - 0x041f394f, - 0x664110f2, - 0x10f010f7, - 0x14f03110, - 0x822b1008, - 0x39808210, - 0x180a10ba, - 0x140c10bc, - 0x1210c04d, - 0x722490e0, - 0x8040a054, - 0x461c2200, - 0x221080f0, - 0x61a545ae, - 0x72248244, - 0x222180f1, - 0x7b104604, - 0x662c9190, - 0x1ca581d5, - 0x1cc549e1, - 0x1cb54dd4, - 0x18b549c7, - 0x4a001cd5, - 0x42001ce7, - 0x2204b240, - 0x1a174200, - 0x105061ee, - 0x180510b5, - 0x4a001cd5, - 0x42001cf7, - 0x2204b240, - 0x16174200, - 0x620061ee, - 0x42001ce7, - 0x91c518b5, - 0x107081e5, - 0x1ce01850, - 0x100749df, - 0x10e761ee, - 0x1cf761ee, - 0x10b14200, - 0x91c11851, - 0x107081e1, - 0x1cf01410, - 0x10074ded, - 0x10f761ee, - 0xa240b241, - 0x80f11072, - 0x46042221, - 0x82086641, - 0x9290c0c0, - 0xb051b061, - 0x92701250, - 0xb0617100, - 0x7227a051, - 0x22008040, - 0x621141ae, - 0x91907b20, - 0x8203662c, - 0x31858165, - 0xb0313d85, - 0x92f3eff0, - 0x66649305, - 0xb054a003, - 0x7100b050, - 0x22018041, - 0xb064461c, - 0x222080f0, - 0x6211418b, - 0xa050b060, - 0x31828162, - 0x82033d82, - 0x92f3efe0, - 0x66649302, - 0x6161720e, - 0x00000000, - 0x00000000, - 0xb013b003, - 0xb0531201, - 0x7100b050, - 0x22018041, - 0xb063461c, - 0x91c381b3, - 0x188581d5, - 0x91651895, - 0x00007000, - 0x00000000, - 0x10250000, - 0x9100c050, - 0x1420c330, - 0x10316f03, - 0x0401c3f0, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0xc3f01031, - 0xc0820401, - 0x00213182, - 0xb1109131, - 0x10313963, - 0x3182c0a2, - 0x91310021, - 0x1050b110, - 0x14053115, - 0x70009205, - 0x82d092e0, - 0x46652200, - 0x7000b2c0, - 0x22f080a0, - 0xb0304281, - 0x3162c102, - 0x80a0c001, - 0x427a1e00, - 0x427b22f0, - 0x3160e820, - 0x627b3960, - 0x1a101020, - 0x6e236f13, - 0x16121611, - 0x70006a7c -}; + { + 0x0000611f, + 0x000f0000, + 0x00000008, + 0x0000003f, + 0x003f0040, + 0x00040000, + 0x000e0068, + 0x000600dc, + 0x001a0043, + 0x00000005, + 0x00020000, + 0x00000000, + 0x00000000, + 0x00c00004, + 0x00040000, + 0x000000c0, + 0x40300007, + 0x40014000, + 0x40074003, + 0x404f400f, + 0x41cf40cf, + 0x47cf43cf, + 0x3fcf4fcf, + 0x1fcf2fcf, + 0x02070fcf, + 0x4040067f, + 0x40404040, + 0x20403040, + 0x00401040, + 0x01c000c0, + 0x07c003c0, + 0x0fc10fc0, + 0x0fc70fc3, + 0xc0500fcf, + 0x70009100, + 0x9100c070, + 0x31827000, + 0x91310021, + 0x7000b110, + 0xb1018101, + 0x3182a100, + 0xb1109132, + 0x10119101, + 0x22418141, + 0x06f14056, + 0xc0517000, + 0x18309101, + 0x31833910, + 0x3118d008, + 0x00316f41, + 0xb1109131, + 0x16141483, + 0x70006862, + 0xc0501025, + 0xc3f49100, + 0x1420c210, + 0x10316f03, + 0xc0220441, + 0x00213182, + 0xb1109131, + 0x10313963, + 0xc0820441, + 0x00213182, + 0xb1109131, + 0x10313963, + 0x3182c0a2, + 0x91310021, + 0x1050b110, + 0x14053115, + 0x70009205, + 0xc0526446, + 0x06311031, + 0x02c13161, + 0xc1126449, + 0x39211031, + 0x31510671, + 0x644902e1, + 0xc0517000, + 0xcc019101, + 0x6449c0e2, + 0xc1116446, + 0x6449c0c2, + 0x7100b054, + 0xb064a054, + 0x220080f0, + 0xc11140a4, + 0x6449c122, + 0x9101c051, + 0x3182c0e2, + 0x00028260, + 0xb1109132, + 0x68b7c300, + 0x12406446, + 0xb03290b0, + 0x39538253, + 0x648c3953, + 0x68c1c360, + 0x90b01280, + 0x7000b032, + 0xc1016446, + 0x6449c122, + 0xc0c2c101, + 0x82536449, + 0x12c0648c, + 0xb03290b0, + 0x64467000, + 0xc081c272, + 0xc1226449, + 0x6449c111, + 0xc111c002, + 0xc0626449, + 0x6449c331, + 0xc111c362, + 0xc3026449, + 0x6449c111, + 0x39538253, + 0xc3e2648c, + 0x2211644e, + 0xc24240e9, + 0x6449c881, + 0xc111c252, + 0xc2726449, + 0x6449cee1, + 0xc881c202, + 0xc2026449, + 0x6449c801, + 0x68fdc0b0, + 0x64467000, + 0xc801c242, + 0xc2526449, + 0x6449c011, + 0xc0e1c272, + 0xc0026449, + 0x6449c101, + 0xc301c062, + 0xc1226449, + 0x6449c101, + 0xc101c362, + 0xc3026449, + 0x6449c101, + 0x648c8253, + 0x00007000, + 0x00000000, + 0x73060000, + 0x720b7205, + 0xb050720e, + 0xb0607100, + 0x8081a050, + 0x22418092, + 0x8080453e, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x61526151, + 0x61546153, + 0x61566155, + 0x61596157, + 0x615d615b, + 0x6151615f, + 0xc0f28091, + 0x31210421, + 0x2a428082, + 0x16321412, + 0x14211101, + 0x61706c01, + 0x6174618b, + 0x61706151, + 0x6174618b, + 0x61616151, + 0x61616161, + 0x61616161, + 0x649b6161, + 0x64c66161, + 0x64d36161, + 0x64ff6161, + 0x666e6161, + 0x12106161, + 0x616690b0, + 0x90b01220, + 0x7306720e, + 0x12107205, + 0x61239030, + 0x00000000, + 0x00000000, + 0xc003c024, + 0x645bc3c0, + 0x9159c4b9, + 0x9160c800, + 0x9200c2d0, + 0x9260c3f0, + 0x3140c060, + 0x0010c0f1, + 0xc0213140, + 0x92100010, + 0x9221c371, + 0x00006161, + 0x00000000, + 0x73060000, + 0x82188159, + 0x108f108e, + 0x041ec0f1, + 0x041f394f, + 0x664110f2, + 0x10f010f7, + 0x14f03110, + 0x822b1008, + 0x39808210, + 0x180a10ba, + 0x140c10bc, + 0x1210c04d, + 0x722490e0, + 0x8040a054, + 0x461c2200, + 0x221080f0, + 0x61a545ae, + 0x72248244, + 0x222180f1, + 0x7b104604, + 0x662c9190, + 0x1ca581d5, + 0x1cc549e1, + 0x1cb54dd4, + 0x18b549c7, + 0x4a001cd5, + 0x42001ce7, + 0x2204b240, + 0x1a174200, + 0x105061ee, + 0x180510b5, + 0x4a001cd5, + 0x42001cf7, + 0x2204b240, + 0x16174200, + 0x620061ee, + 0x42001ce7, + 0x91c518b5, + 0x107081e5, + 0x1ce01850, + 0x100749df, + 0x10e761ee, + 0x1cf761ee, + 0x10b14200, + 0x91c11851, + 0x107081e1, + 0x1cf01410, + 0x10074ded, + 0x10f761ee, + 0xa240b241, + 0x80f11072, + 0x46042221, + 0x82086641, + 0x9290c0c0, + 0xb051b061, + 0x92701250, + 0xb0617100, + 0x7227a051, + 0x22008040, + 0x621141ae, + 0x91907b20, + 0x8203662c, + 0x31858165, + 0xb0313d85, + 0x92f3eff0, + 0x66649305, + 0xb054a003, + 0x7100b050, + 0x22018041, + 0xb064461c, + 0x222080f0, + 0x6211418b, + 0xa050b060, + 0x31828162, + 0x82033d82, + 0x92f3efe0, + 0x66649302, + 0x6161720e, + 0x00000000, + 0x00000000, + 0xb013b003, + 0xb0531201, + 0x7100b050, + 0x22018041, + 0xb063461c, + 0x91c381b3, + 0x188581d5, + 0x91651895, + 0x00007000, + 0x00000000, + 0x10250000, + 0x9100c050, + 0x1420c330, + 0x10316f03, + 0x0401c3f0, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0xc3f01031, + 0xc0820401, + 0x00213182, + 0xb1109131, + 0x10313963, + 0x3182c0a2, + 0x91310021, + 0x1050b110, + 0x14053115, + 0x70009205, + 0x82d092e0, + 0x46652200, + 0x7000b2c0, + 0x22f080a0, + 0xb0304281, + 0x3162c102, + 0x80a0c001, + 0x427a1e00, + 0x427b22f0, + 0x3160e820, + 0x627b3960, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006a7c}; PATCH_FUN_SPEC void rf_patch_rfe_hsp_4mbps(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_lrm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_lrm.h index dd659ed..61fb931 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_lrm.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_lrm.h @@ -1,496 +1,494 @@ /****************************************************************************** -* Filename: rf_patch_rfe_lrm.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 Legacy Long Range Mode -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - + * Filename: rf_patch_rfe_lrm.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 Legacy Long Range Mode + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_RFE_LRM_H #define _RF_PATCH_RFE_LRM_H -#include #include "../inc/hw_types.h" +#include #ifndef RFE_PATCH_TYPE - #define RFE_PATCH_TYPE static const uint32_t +#define RFE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_RFERAM_BASE - #define RFC_RFERAM_BASE 0x2100C000 +#define RFC_RFERAM_BASE 0x2100C000 #endif #ifndef RFE_PATCH_MODE - #define RFE_PATCH_MODE 0 +#define RFE_PATCH_MODE 0 #endif RFE_PATCH_TYPE patchLrmRfe[429] = -{ - 0x000061a3, - 0x1307147f, - 0x24f1004d, - 0x3f131f2e, - 0x003f0ab0, - 0x0000ff07, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x43cf41cf, - 0x4fcf47cf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x00000000, - 0x0008000f, - 0x003f0000, - 0x00400000, - 0x0000003f, - 0x00680004, - 0x00dc000e, - 0x00430006, - 0x0005001a, - 0x00000000, - 0x00000002, - 0x0000003f, - 0x00040000, - 0x000000c0, - 0x00c00004, - 0x00070000, - 0x9100c050, - 0xc0707000, - 0x70009100, - 0x00213182, - 0xb1109131, - 0x81017000, - 0xa100b101, - 0x91323182, - 0x9101b110, - 0x81411011, - 0x404f2241, - 0x700006f1, - 0x9101c051, - 0x39101830, - 0xd0083183, - 0x6f413118, - 0x91310031, - 0x1483b110, - 0x685b1614, - 0x10257000, - 0x9100c050, - 0xc0c0c3f4, - 0x6f031420, - 0x04411031, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0x04411031, - 0x3182c082, - 0x91310021, - 0x3963b110, - 0xc0a21031, - 0x00213182, - 0xb1109131, - 0x31151050, - 0x92051405, - 0x643f7000, - 0x1031c052, - 0x31610631, - 0x644202c1, - 0x1031c112, - 0x06713921, - 0x02e13151, - 0x70006442, - 0x6599658a, - 0x8220c088, - 0x39803950, - 0x409f1e00, - 0x3001c041, - 0x1a181418, - 0x8230c089, - 0x39803960, - 0x40a91e00, - 0x3001c041, - 0x1a191419, - 0x9136643c, - 0x9134b110, - 0xb054b110, - 0xa0547100, - 0x80f0b064, - 0x40af2200, - 0x90b01240, - 0x8253b032, - 0x39533953, - 0x643f6485, - 0xc122c111, - 0xc1706442, - 0xc11168c2, - 0x6442c0c2, - 0x68c7c170, - 0x9100c050, - 0x92987227, - 0x16141615, - 0x10531042, - 0x8221c1f0, - 0x39313131, - 0x31313981, - 0xb270b051, - 0x72276572, - 0xb2709299, - 0x10731062, - 0x8231c3f0, - 0x39213121, - 0x101b3981, - 0xc0e26572, - 0x82603182, - 0x39803180, - 0xb0610002, - 0x91327100, - 0xa051b110, - 0x7227b061, - 0x68f3c230, - 0x12800000, - 0xb03290b0, - 0xc0507000, - 0x72279100, - 0x10629299, - 0xc3f01073, - 0x31218231, - 0x39813921, - 0xb270b051, - 0x7227657e, - 0xb2709298, - 0x10531042, - 0x8221c1f0, - 0x39313131, - 0x31313981, - 0x657e101a, - 0xb061a051, - 0xc0b07227, - 0x643f6918, - 0xc122c101, - 0xc1016442, - 0x6442c0c2, - 0x643c1a15, - 0xb1109135, - 0x64858253, - 0x90b012c0, - 0x7000b032, - 0xc272643f, - 0x6442c081, - 0xc111c122, - 0xc0026442, - 0x6442c111, - 0xc331c062, - 0xc3626442, - 0x6442c111, - 0xc111c302, - 0x82536442, - 0x64853953, - 0x6447c3e2, - 0x41402211, - 0xc881c242, - 0xc2526442, - 0x6442c111, - 0xcee1c272, - 0xc2026442, - 0x6442c881, - 0xc801c202, - 0xc0b06442, - 0x70006954, - 0xc242643f, - 0x6442c801, - 0xc011c252, - 0xc2726442, - 0x6442c0e1, - 0xc101c002, - 0xc0626442, - 0x6442c301, - 0xc101c122, - 0xc3626442, - 0x6442c101, - 0xc101c302, - 0x82536442, - 0x70006485, - 0x7100b061, - 0x1c231412, - 0x91334d7a, - 0x7000b110, - 0xb1109132, - 0x70006972, - 0x7100b061, - 0x1c321813, - 0x91324986, - 0x7000b110, - 0xb1109133, - 0x7000697e, - 0x6447c0c2, - 0xc0c21015, - 0x64471612, - 0x14153141, - 0x3180c0c0, - 0x10541405, - 0x040478a0, - 0xc0e67000, - 0xcc013186, - 0x10671416, - 0xc3f08261, - 0x14170401, - 0x73067000, - 0x720b7205, - 0xb050720e, - 0x80817100, - 0xa050b060, - 0x22418092, - 0x808045c3, - 0x0410c1f1, - 0x11011630, - 0x6c011401, - 0x61d761d6, - 0x61d961d8, - 0x61db61da, - 0x61de61dc, - 0x61e261e0, - 0x633661e4, - 0x80916339, - 0x0421c0f2, - 0x80823121, - 0x14122a42, - 0x11011632, - 0x6c011421, - 0x620b61ee, - 0x633961f4, - 0x620b61ee, - 0x633961f4, - 0x61e661e6, - 0x61e661e6, - 0x61e661e6, - 0x61e66494, - 0x61e664f9, - 0x61e6652a, - 0x61e66556, - 0x61e66746, - 0x90b01210, - 0x7306720e, - 0x12107205, - 0x61a79030, - 0x673ccff0, - 0xc003c1d4, - 0x6454c3c0, - 0x91507840, - 0x92107850, - 0x92207860, - 0x92307870, - 0x92407880, - 0x92607890, - 0x91907830, - 0x39408210, - 0x100106f0, - 0x14103110, - 0x67429200, - 0xa0bc61e6, - 0xa054a0e2, - 0x225080f0, - 0x80404615, - 0x472b2200, - 0xa040620d, - 0x318d822d, - 0x8210398d, - 0x0410c0f1, - 0x821a1009, - 0x041a394a, - 0x39808210, - 0x100e0410, - 0x10bc10ab, - 0x646310c2, - 0xcfe07229, - 0xb013673c, - 0x66c8b003, - 0xb050b053, - 0xb064b054, - 0x66a5b013, - 0x22e08210, - 0x66ae4638, - 0x80417100, - 0x472b2201, - 0x221080f0, - 0x22f0464b, - 0xb0644718, - 0x42382231, - 0x66ceb063, - 0x22e08210, - 0x66704638, - 0xb0646238, - 0x318f816f, - 0xdfd03d8f, - 0x673c92ff, - 0x80417100, - 0x472b2201, - 0x80f0b064, - 0x42652250, - 0x8211b063, - 0x466022c1, - 0x670566ce, - 0x22d18211, - 0x66704652, - 0x81616252, - 0x31818172, - 0x31823d81, - 0xefc03d82, - 0x930292f1, - 0x620b673c, - 0x91c081b0, - 0x829781d3, - 0x18d3a290, - 0x0bf34e7f, - 0x1ce31613, - 0x91c34aa4, - 0x143b81e3, - 0x1cba6290, - 0x1e23468b, - 0x1ce34a8b, - 0xb2904e8b, - 0x428b2207, - 0x1a1ba290, - 0x1ce36296, - 0x91c34aa4, - 0x183b81e3, - 0x4ea01cab, - 0x4aa21c9b, - 0x42a41cbc, - 0x821010b2, - 0x429d22d0, - 0x221080f0, - 0x646346a4, - 0x62a466a5, - 0x629410ab, - 0x6294109b, - 0x82307000, - 0x0410c0f1, - 0x7100b063, - 0x10bc6aa8, - 0x7000b0e0, - 0x91c281b2, - 0x820181d2, - 0x81511812, - 0x82411812, - 0x3d813181, - 0x4abf1c12, - 0xb032b0e2, - 0x92f2dfb0, - 0xc7f1673c, - 0x4ec31421, - 0x9162c812, - 0xb0319172, - 0x7000b0e1, - 0xc006c008, - 0x9160c800, - 0x70009170, - 0x81b08201, - 0x81d091c0, - 0x81511810, - 0x14061810, - 0x824280e1, - 0x3d823182, - 0x4ae41c20, - 0x2221b0e2, - 0xb03246e8, - 0xdfa01005, - 0x673c92f5, - 0x42e82221, - 0xb032a0e2, - 0x39418231, - 0x0401c0f0, - 0x42f61e01, - 0xc0101618, - 0x1c083010, - 0x10604704, - 0x10063c10, - 0x1461c7f1, - 0xc8164efa, - 0x81719166, - 0x3d813181, - 0x4b011c16, - 0xb0319176, - 0xc008c006, - 0x81617000, - 0x3d813181, - 0x39808240, - 0x1cf11801, - 0x14014b17, - 0x22c080b0, - 0xb0bc4717, - 0xef90b033, - 0x930f92f1, - 0x7000673c, - 0xb063a003, - 0xb0efb064, - 0x71006556, - 0x22008040, - 0xb064472b, - 0xa0ef652a, - 0x80407100, - 0x472b2200, - 0xb003b064, - 0x82016238, - 0x31828162, - 0xef803d82, - 0x930292f1, - 0xa003673c, - 0x61e66556, - 0x646380a2, - 0xb05061e6, - 0x61e67100, - 0x82d092e0, - 0x473d2200, - 0x7000b2c0, - 0x22f080a0, - 0xb0304359, - 0x3162c102, - 0x80a0c001, - 0x43521e00, - 0x435322f0, - 0x3160f5a0, - 0x63533960, - 0x1a101020, - 0x6e236f13, - 0x16121611, - 0x70006b54 -}; + { + 0x000061a3, + 0x1307147f, + 0x24f1004d, + 0x3f131f2e, + 0x003f0ab0, + 0x0000ff07, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x0008000f, + 0x003f0000, + 0x00400000, + 0x0000003f, + 0x00680004, + 0x00dc000e, + 0x00430006, + 0x0005001a, + 0x00000000, + 0x00000002, + 0x0000003f, + 0x00040000, + 0x000000c0, + 0x00c00004, + 0x00070000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x404f2241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x685b1614, + 0x10257000, + 0x9100c050, + 0xc0c0c3f4, + 0x6f031420, + 0x04411031, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x643f7000, + 0x1031c052, + 0x31610631, + 0x644202c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006442, + 0x6599658a, + 0x8220c088, + 0x39803950, + 0x409f1e00, + 0x3001c041, + 0x1a181418, + 0x8230c089, + 0x39803960, + 0x40a91e00, + 0x3001c041, + 0x1a191419, + 0x9136643c, + 0x9134b110, + 0xb054b110, + 0xa0547100, + 0x80f0b064, + 0x40af2200, + 0x90b01240, + 0x8253b032, + 0x39533953, + 0x643f6485, + 0xc122c111, + 0xc1706442, + 0xc11168c2, + 0x6442c0c2, + 0x68c7c170, + 0x9100c050, + 0x92987227, + 0x16141615, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0xb270b051, + 0x72276572, + 0xb2709299, + 0x10731062, + 0x8231c3f0, + 0x39213121, + 0x101b3981, + 0xc0e26572, + 0x82603182, + 0x39803180, + 0xb0610002, + 0x91327100, + 0xa051b110, + 0x7227b061, + 0x68f3c230, + 0x12800000, + 0xb03290b0, + 0xc0507000, + 0x72279100, + 0x10629299, + 0xc3f01073, + 0x31218231, + 0x39813921, + 0xb270b051, + 0x7227657e, + 0xb2709298, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0x657e101a, + 0xb061a051, + 0xc0b07227, + 0x643f6918, + 0xc122c101, + 0xc1016442, + 0x6442c0c2, + 0x643c1a15, + 0xb1109135, + 0x64858253, + 0x90b012c0, + 0x7000b032, + 0xc272643f, + 0x6442c081, + 0xc111c122, + 0xc0026442, + 0x6442c111, + 0xc331c062, + 0xc3626442, + 0x6442c111, + 0xc111c302, + 0x82536442, + 0x64853953, + 0x6447c3e2, + 0x41402211, + 0xc881c242, + 0xc2526442, + 0x6442c111, + 0xcee1c272, + 0xc2026442, + 0x6442c881, + 0xc801c202, + 0xc0b06442, + 0x70006954, + 0xc242643f, + 0x6442c801, + 0xc011c252, + 0xc2726442, + 0x6442c0e1, + 0xc101c002, + 0xc0626442, + 0x6442c301, + 0xc101c122, + 0xc3626442, + 0x6442c101, + 0xc101c302, + 0x82536442, + 0x70006485, + 0x7100b061, + 0x1c231412, + 0x91334d7a, + 0x7000b110, + 0xb1109132, + 0x70006972, + 0x7100b061, + 0x1c321813, + 0x91324986, + 0x7000b110, + 0xb1109133, + 0x7000697e, + 0x6447c0c2, + 0xc0c21015, + 0x64471612, + 0x14153141, + 0x3180c0c0, + 0x10541405, + 0x040478a0, + 0xc0e67000, + 0xcc013186, + 0x10671416, + 0xc3f08261, + 0x14170401, + 0x73067000, + 0x720b7205, + 0xb050720e, + 0x80817100, + 0xa050b060, + 0x22418092, + 0x808045c3, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x61d761d6, + 0x61d961d8, + 0x61db61da, + 0x61de61dc, + 0x61e261e0, + 0x633661e4, + 0x80916339, + 0x0421c0f2, + 0x80823121, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x620b61ee, + 0x633961f4, + 0x620b61ee, + 0x633961f4, + 0x61e661e6, + 0x61e661e6, + 0x61e661e6, + 0x61e66494, + 0x61e664f9, + 0x61e6652a, + 0x61e66556, + 0x61e66746, + 0x90b01210, + 0x7306720e, + 0x12107205, + 0x61a79030, + 0x673ccff0, + 0xc003c1d4, + 0x6454c3c0, + 0x91507840, + 0x92107850, + 0x92207860, + 0x92307870, + 0x92407880, + 0x92607890, + 0x91907830, + 0x39408210, + 0x100106f0, + 0x14103110, + 0x67429200, + 0xa0bc61e6, + 0xa054a0e2, + 0x225080f0, + 0x80404615, + 0x472b2200, + 0xa040620d, + 0x318d822d, + 0x8210398d, + 0x0410c0f1, + 0x821a1009, + 0x041a394a, + 0x39808210, + 0x100e0410, + 0x10bc10ab, + 0x646310c2, + 0xcfe07229, + 0xb013673c, + 0x66c8b003, + 0xb050b053, + 0xb064b054, + 0x66a5b013, + 0x22e08210, + 0x66ae4638, + 0x80417100, + 0x472b2201, + 0x221080f0, + 0x22f0464b, + 0xb0644718, + 0x42382231, + 0x66ceb063, + 0x22e08210, + 0x66704638, + 0xb0646238, + 0x318f816f, + 0xdfd03d8f, + 0x673c92ff, + 0x80417100, + 0x472b2201, + 0x80f0b064, + 0x42652250, + 0x8211b063, + 0x466022c1, + 0x670566ce, + 0x22d18211, + 0x66704652, + 0x81616252, + 0x31818172, + 0x31823d81, + 0xefc03d82, + 0x930292f1, + 0x620b673c, + 0x91c081b0, + 0x829781d3, + 0x18d3a290, + 0x0bf34e7f, + 0x1ce31613, + 0x91c34aa4, + 0x143b81e3, + 0x1cba6290, + 0x1e23468b, + 0x1ce34a8b, + 0xb2904e8b, + 0x428b2207, + 0x1a1ba290, + 0x1ce36296, + 0x91c34aa4, + 0x183b81e3, + 0x4ea01cab, + 0x4aa21c9b, + 0x42a41cbc, + 0x821010b2, + 0x429d22d0, + 0x221080f0, + 0x646346a4, + 0x62a466a5, + 0x629410ab, + 0x6294109b, + 0x82307000, + 0x0410c0f1, + 0x7100b063, + 0x10bc6aa8, + 0x7000b0e0, + 0x91c281b2, + 0x820181d2, + 0x81511812, + 0x82411812, + 0x3d813181, + 0x4abf1c12, + 0xb032b0e2, + 0x92f2dfb0, + 0xc7f1673c, + 0x4ec31421, + 0x9162c812, + 0xb0319172, + 0x7000b0e1, + 0xc006c008, + 0x9160c800, + 0x70009170, + 0x81b08201, + 0x81d091c0, + 0x81511810, + 0x14061810, + 0x824280e1, + 0x3d823182, + 0x4ae41c20, + 0x2221b0e2, + 0xb03246e8, + 0xdfa01005, + 0x673c92f5, + 0x42e82221, + 0xb032a0e2, + 0x39418231, + 0x0401c0f0, + 0x42f61e01, + 0xc0101618, + 0x1c083010, + 0x10604704, + 0x10063c10, + 0x1461c7f1, + 0xc8164efa, + 0x81719166, + 0x3d813181, + 0x4b011c16, + 0xb0319176, + 0xc008c006, + 0x81617000, + 0x3d813181, + 0x39808240, + 0x1cf11801, + 0x14014b17, + 0x22c080b0, + 0xb0bc4717, + 0xef90b033, + 0x930f92f1, + 0x7000673c, + 0xb063a003, + 0xb0efb064, + 0x71006556, + 0x22008040, + 0xb064472b, + 0xa0ef652a, + 0x80407100, + 0x472b2200, + 0xb003b064, + 0x82016238, + 0x31828162, + 0xef803d82, + 0x930292f1, + 0xa003673c, + 0x61e66556, + 0x646380a2, + 0xb05061e6, + 0x61e67100, + 0x82d092e0, + 0x473d2200, + 0x7000b2c0, + 0x22f080a0, + 0xb0304359, + 0x3162c102, + 0x80a0c001, + 0x43521e00, + 0x435322f0, + 0x3160f5a0, + 0x63533960, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006b54}; PATCH_FUN_SPEC void rf_patch_rfe_lrm(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_sl_longrange.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_sl_longrange.h index 5b0a71d..02453ac 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_sl_longrange.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_sl_longrange.h @@ -1,496 +1,494 @@ /****************************************************************************** -* Filename: rf_patch_rfe_sl_longrange.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 Simplelink Long range -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - + * Filename: rf_patch_rfe_sl_longrange.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 Simplelink Long range + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_RFE_SL_LONGRANGE_H #define _RF_PATCH_RFE_SL_LONGRANGE_H -#include #include "../inc/hw_types.h" +#include #ifndef RFE_PATCH_TYPE - #define RFE_PATCH_TYPE static const uint32_t +#define RFE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_RFERAM_BASE - #define RFC_RFERAM_BASE 0x2100C000 +#define RFC_RFERAM_BASE 0x2100C000 #endif #ifndef RFE_PATCH_MODE - #define RFE_PATCH_MODE 0 +#define RFE_PATCH_MODE 0 #endif RFE_PATCH_TYPE patchSl_longrangeRfe[429] = -{ - 0x000061a3, - 0x1307147f, - 0x24f1004d, - 0x3f131f2e, - 0x003f0ab0, - 0x0000ff07, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x43cf41cf, - 0x4fcf47cf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x00000000, - 0x0008000f, - 0x003f0000, - 0x00400000, - 0x0000003f, - 0x00680004, - 0x00dc000e, - 0x00430006, - 0x0005001a, - 0x00000000, - 0x00000002, - 0x0000003f, - 0x00040000, - 0x000000c0, - 0x00c00004, - 0x00070000, - 0x9100c050, - 0xc0707000, - 0x70009100, - 0x00213182, - 0xb1109131, - 0x81017000, - 0xa100b101, - 0x91323182, - 0x9101b110, - 0x81411011, - 0x404f2241, - 0x700006f1, - 0x9101c051, - 0x39101830, - 0xd0083183, - 0x6f413118, - 0x91310031, - 0x1483b110, - 0x685b1614, - 0x10257000, - 0x9100c050, - 0xc0c0c3f4, - 0x6f031420, - 0x04411031, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0x04411031, - 0x3182c082, - 0x91310021, - 0x3963b110, - 0xc0a21031, - 0x00213182, - 0xb1109131, - 0x31151050, - 0x92051405, - 0x643f7000, - 0x1031c052, - 0x31610631, - 0x644202c1, - 0x1031c112, - 0x06713921, - 0x02e13151, - 0x70006442, - 0x6599658a, - 0x8220c088, - 0x39803950, - 0x409f1e00, - 0x3001c041, - 0x1a181418, - 0x8230c089, - 0x39803960, - 0x40a91e00, - 0x3001c041, - 0x1a191419, - 0x9136643c, - 0x9134b110, - 0xb054b110, - 0xa0547100, - 0x80f0b064, - 0x40af2200, - 0x90b01240, - 0x8253b032, - 0x39533953, - 0x643f6485, - 0xc122c111, - 0xc1706442, - 0xc11168c2, - 0x6442c0c2, - 0x68c7c170, - 0x9100c050, - 0x92987227, - 0x16141615, - 0x10531042, - 0x8221c1f0, - 0x39313131, - 0x31313981, - 0xb270b051, - 0x72276572, - 0xb2709299, - 0x10731062, - 0x8231c3f0, - 0x39213121, - 0x101b3981, - 0xc0e26572, - 0x82603182, - 0x39803180, - 0xb0610002, - 0x91327100, - 0xa051b110, - 0x7227b061, - 0x68f3c230, - 0x12800000, - 0xb03290b0, - 0xc0507000, - 0x72279100, - 0x10629299, - 0xc3f01073, - 0x31218231, - 0x39813921, - 0xb270b051, - 0x7227657e, - 0xb2709298, - 0x10531042, - 0x8221c1f0, - 0x39313131, - 0x31313981, - 0x657e101a, - 0xb061a051, - 0xc0b07227, - 0x643f6918, - 0xc122c101, - 0xc1016442, - 0x6442c0c2, - 0x643c1a15, - 0xb1109135, - 0x64858253, - 0x90b012c0, - 0x7000b032, - 0xc272643f, - 0x6442c081, - 0xc111c122, - 0xc0026442, - 0x6442c111, - 0xc331c062, - 0xc3626442, - 0x6442c111, - 0xc111c302, - 0x82536442, - 0x64853953, - 0x6447c3e2, - 0x41402211, - 0xc881c242, - 0xc2526442, - 0x6442c111, - 0xcee1c272, - 0xc2026442, - 0x6442c881, - 0xc801c202, - 0xc0b06442, - 0x70006954, - 0xc242643f, - 0x6442c801, - 0xc011c252, - 0xc2726442, - 0x6442c0e1, - 0xc101c002, - 0xc0626442, - 0x6442c301, - 0xc101c122, - 0xc3626442, - 0x6442c101, - 0xc101c302, - 0x82536442, - 0x70006485, - 0x7100b061, - 0x1c231412, - 0x91334d7a, - 0x7000b110, - 0xb1109132, - 0x70006972, - 0x7100b061, - 0x1c321813, - 0x91324986, - 0x7000b110, - 0xb1109133, - 0x7000697e, - 0x6447c0c2, - 0xc0c21015, - 0x64471612, - 0x14153141, - 0x3180c0c0, - 0x10541405, - 0x040478a0, - 0xc0e67000, - 0xcc013186, - 0x10671416, - 0xc3f08261, - 0x14170401, - 0x73067000, - 0x720b7205, - 0xb050720e, - 0x80817100, - 0xa050b060, - 0x22418092, - 0x808045c3, - 0x0410c1f1, - 0x11011630, - 0x6c011401, - 0x61d761d6, - 0x61d961d8, - 0x61db61da, - 0x61de61dc, - 0x61e261e0, - 0x633661e4, - 0x80916339, - 0x0421c0f2, - 0x80823121, - 0x14122a42, - 0x11011632, - 0x6c011421, - 0x620b61ee, - 0x633961f4, - 0x620b61ee, - 0x633961f4, - 0x61e661e6, - 0x61e661e6, - 0x61e661e6, - 0x61e66494, - 0x61e664f9, - 0x61e6652a, - 0x61e66556, - 0x61e66746, - 0x90b01210, - 0x7306720e, - 0x12107205, - 0x61a79030, - 0x673ccff0, - 0xc003c1d4, - 0x6454c3c0, - 0x91507840, - 0x92107850, - 0x92207860, - 0x92307870, - 0x92407880, - 0x92607890, - 0x91907830, - 0x39408210, - 0x100106f0, - 0x14103110, - 0x67429200, - 0xa0bc61e6, - 0xa054a0e2, - 0x225080f0, - 0x80404615, - 0x472b2200, - 0xa040620d, - 0x318d822d, - 0x8210398d, - 0x0410c0f1, - 0x821a1009, - 0x041a394a, - 0x39808210, - 0x100e0410, - 0x10bc10ab, - 0x646310c2, - 0xcfe07229, - 0xb013673c, - 0x66c8b003, - 0xb050b053, - 0xb064b054, - 0x66a5b013, - 0x22e08210, - 0x66ae4638, - 0x80417100, - 0x472b2201, - 0x221080f0, - 0x22f0464b, - 0xb0644718, - 0x42382231, - 0x66ceb063, - 0x22e08210, - 0x66704638, - 0xb0646238, - 0x318f816f, - 0xdfd03d8f, - 0x673c92ff, - 0x80417100, - 0x472b2201, - 0x80f0b064, - 0x42652250, - 0x8211b063, - 0x466022c1, - 0x670566ce, - 0x22d18211, - 0x66704652, - 0x81616252, - 0x31818172, - 0x31823d81, - 0xefc03d82, - 0x930292f1, - 0x620b673c, - 0x91c081b0, - 0x829781d3, - 0x18d3a290, - 0x0bf34e7f, - 0x1ce31613, - 0x91c34aa4, - 0x143b81e3, - 0x1cba6290, - 0x1e23468b, - 0x1ce34a8b, - 0xb2904e8b, - 0x428b2207, - 0x1a1ba290, - 0x1ce36296, - 0x91c34aa4, - 0x183b81e3, - 0x4ea01cab, - 0x4aa21c9b, - 0x42a41cbc, - 0x821010b2, - 0x429d22d0, - 0x221080f0, - 0x646346a4, - 0x62a466a5, - 0x629410ab, - 0x6294109b, - 0x82307000, - 0x0410c0f1, - 0x7100b063, - 0x10bc6aa8, - 0x7000b0e0, - 0x91c281b2, - 0x820181d2, - 0x81511812, - 0x82411812, - 0x3d813181, - 0x4abf1c12, - 0xb032b0e2, - 0x92f2dfb0, - 0xc7f1673c, - 0x4ec31421, - 0x9162c812, - 0xb0319172, - 0x7000b0e1, - 0xc006c008, - 0x9160c800, - 0x70009170, - 0x81b08201, - 0x81d091c0, - 0x81511810, - 0x14061810, - 0x824280e1, - 0x3d823182, - 0x4ae41c20, - 0x2221b0e2, - 0xb03246e8, - 0xdfa01005, - 0x673c92f5, - 0x42e82221, - 0xb032a0e2, - 0x39418231, - 0x0401c0f0, - 0x42f61e01, - 0xc0101618, - 0x1c083010, - 0x10604704, - 0x10063c10, - 0x1461c7f1, - 0xc8164efa, - 0x81719166, - 0x3d813181, - 0x4b011c16, - 0xb0319176, - 0xc008c006, - 0x81617000, - 0x3d813181, - 0x39808240, - 0x1cf11801, - 0x14014b17, - 0x22c080b0, - 0xb0bc4717, - 0xef90b033, - 0x930f92f1, - 0x7000673c, - 0xb063a003, - 0xb0efb064, - 0x71006556, - 0x22008040, - 0xb064472b, - 0xa0ef652a, - 0x80407100, - 0x472b2200, - 0xb003b064, - 0x82016238, - 0x31828162, - 0xef803d82, - 0x930292f1, - 0xa003673c, - 0x61e66556, - 0x646380a2, - 0xb05061e6, - 0x61e67100, - 0x82d092e0, - 0x473d2200, - 0x7000b2c0, - 0x22f080a0, - 0xb0304359, - 0x3162c102, - 0x80a0c001, - 0x43521e00, - 0x435322f0, - 0x3160f5a0, - 0x63533960, - 0x1a101020, - 0x6e236f13, - 0x16121611, - 0x70006b54 -}; + { + 0x000061a3, + 0x1307147f, + 0x24f1004d, + 0x3f131f2e, + 0x003f0ab0, + 0x0000ff07, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x0008000f, + 0x003f0000, + 0x00400000, + 0x0000003f, + 0x00680004, + 0x00dc000e, + 0x00430006, + 0x0005001a, + 0x00000000, + 0x00000002, + 0x0000003f, + 0x00040000, + 0x000000c0, + 0x00c00004, + 0x00070000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x404f2241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x685b1614, + 0x10257000, + 0x9100c050, + 0xc0c0c3f4, + 0x6f031420, + 0x04411031, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x643f7000, + 0x1031c052, + 0x31610631, + 0x644202c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006442, + 0x6599658a, + 0x8220c088, + 0x39803950, + 0x409f1e00, + 0x3001c041, + 0x1a181418, + 0x8230c089, + 0x39803960, + 0x40a91e00, + 0x3001c041, + 0x1a191419, + 0x9136643c, + 0x9134b110, + 0xb054b110, + 0xa0547100, + 0x80f0b064, + 0x40af2200, + 0x90b01240, + 0x8253b032, + 0x39533953, + 0x643f6485, + 0xc122c111, + 0xc1706442, + 0xc11168c2, + 0x6442c0c2, + 0x68c7c170, + 0x9100c050, + 0x92987227, + 0x16141615, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0xb270b051, + 0x72276572, + 0xb2709299, + 0x10731062, + 0x8231c3f0, + 0x39213121, + 0x101b3981, + 0xc0e26572, + 0x82603182, + 0x39803180, + 0xb0610002, + 0x91327100, + 0xa051b110, + 0x7227b061, + 0x68f3c230, + 0x12800000, + 0xb03290b0, + 0xc0507000, + 0x72279100, + 0x10629299, + 0xc3f01073, + 0x31218231, + 0x39813921, + 0xb270b051, + 0x7227657e, + 0xb2709298, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0x657e101a, + 0xb061a051, + 0xc0b07227, + 0x643f6918, + 0xc122c101, + 0xc1016442, + 0x6442c0c2, + 0x643c1a15, + 0xb1109135, + 0x64858253, + 0x90b012c0, + 0x7000b032, + 0xc272643f, + 0x6442c081, + 0xc111c122, + 0xc0026442, + 0x6442c111, + 0xc331c062, + 0xc3626442, + 0x6442c111, + 0xc111c302, + 0x82536442, + 0x64853953, + 0x6447c3e2, + 0x41402211, + 0xc881c242, + 0xc2526442, + 0x6442c111, + 0xcee1c272, + 0xc2026442, + 0x6442c881, + 0xc801c202, + 0xc0b06442, + 0x70006954, + 0xc242643f, + 0x6442c801, + 0xc011c252, + 0xc2726442, + 0x6442c0e1, + 0xc101c002, + 0xc0626442, + 0x6442c301, + 0xc101c122, + 0xc3626442, + 0x6442c101, + 0xc101c302, + 0x82536442, + 0x70006485, + 0x7100b061, + 0x1c231412, + 0x91334d7a, + 0x7000b110, + 0xb1109132, + 0x70006972, + 0x7100b061, + 0x1c321813, + 0x91324986, + 0x7000b110, + 0xb1109133, + 0x7000697e, + 0x6447c0c2, + 0xc0c21015, + 0x64471612, + 0x14153141, + 0x3180c0c0, + 0x10541405, + 0x040478a0, + 0xc0e67000, + 0xcc013186, + 0x10671416, + 0xc3f08261, + 0x14170401, + 0x73067000, + 0x720b7205, + 0xb050720e, + 0x80817100, + 0xa050b060, + 0x22418092, + 0x808045c3, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x61d761d6, + 0x61d961d8, + 0x61db61da, + 0x61de61dc, + 0x61e261e0, + 0x633661e4, + 0x80916339, + 0x0421c0f2, + 0x80823121, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x620b61ee, + 0x633961f4, + 0x620b61ee, + 0x633961f4, + 0x61e661e6, + 0x61e661e6, + 0x61e661e6, + 0x61e66494, + 0x61e664f9, + 0x61e6652a, + 0x61e66556, + 0x61e66746, + 0x90b01210, + 0x7306720e, + 0x12107205, + 0x61a79030, + 0x673ccff0, + 0xc003c1d4, + 0x6454c3c0, + 0x91507840, + 0x92107850, + 0x92207860, + 0x92307870, + 0x92407880, + 0x92607890, + 0x91907830, + 0x39408210, + 0x100106f0, + 0x14103110, + 0x67429200, + 0xa0bc61e6, + 0xa054a0e2, + 0x225080f0, + 0x80404615, + 0x472b2200, + 0xa040620d, + 0x318d822d, + 0x8210398d, + 0x0410c0f1, + 0x821a1009, + 0x041a394a, + 0x39808210, + 0x100e0410, + 0x10bc10ab, + 0x646310c2, + 0xcfe07229, + 0xb013673c, + 0x66c8b003, + 0xb050b053, + 0xb064b054, + 0x66a5b013, + 0x22e08210, + 0x66ae4638, + 0x80417100, + 0x472b2201, + 0x221080f0, + 0x22f0464b, + 0xb0644718, + 0x42382231, + 0x66ceb063, + 0x22e08210, + 0x66704638, + 0xb0646238, + 0x318f816f, + 0xdfd03d8f, + 0x673c92ff, + 0x80417100, + 0x472b2201, + 0x80f0b064, + 0x42652250, + 0x8211b063, + 0x466022c1, + 0x670566ce, + 0x22d18211, + 0x66704652, + 0x81616252, + 0x31818172, + 0x31823d81, + 0xefc03d82, + 0x930292f1, + 0x620b673c, + 0x91c081b0, + 0x829781d3, + 0x18d3a290, + 0x0bf34e7f, + 0x1ce31613, + 0x91c34aa4, + 0x143b81e3, + 0x1cba6290, + 0x1e23468b, + 0x1ce34a8b, + 0xb2904e8b, + 0x428b2207, + 0x1a1ba290, + 0x1ce36296, + 0x91c34aa4, + 0x183b81e3, + 0x4ea01cab, + 0x4aa21c9b, + 0x42a41cbc, + 0x821010b2, + 0x429d22d0, + 0x221080f0, + 0x646346a4, + 0x62a466a5, + 0x629410ab, + 0x6294109b, + 0x82307000, + 0x0410c0f1, + 0x7100b063, + 0x10bc6aa8, + 0x7000b0e0, + 0x91c281b2, + 0x820181d2, + 0x81511812, + 0x82411812, + 0x3d813181, + 0x4abf1c12, + 0xb032b0e2, + 0x92f2dfb0, + 0xc7f1673c, + 0x4ec31421, + 0x9162c812, + 0xb0319172, + 0x7000b0e1, + 0xc006c008, + 0x9160c800, + 0x70009170, + 0x81b08201, + 0x81d091c0, + 0x81511810, + 0x14061810, + 0x824280e1, + 0x3d823182, + 0x4ae41c20, + 0x2221b0e2, + 0xb03246e8, + 0xdfa01005, + 0x673c92f5, + 0x42e82221, + 0xb032a0e2, + 0x39418231, + 0x0401c0f0, + 0x42f61e01, + 0xc0101618, + 0x1c083010, + 0x10604704, + 0x10063c10, + 0x1461c7f1, + 0xc8164efa, + 0x81719166, + 0x3d813181, + 0x4b011c16, + 0xb0319176, + 0xc008c006, + 0x81617000, + 0x3d813181, + 0x39808240, + 0x1cf11801, + 0x14014b17, + 0x22c080b0, + 0xb0bc4717, + 0xef90b033, + 0x930f92f1, + 0x7000673c, + 0xb063a003, + 0xb0efb064, + 0x71006556, + 0x22008040, + 0xb064472b, + 0xa0ef652a, + 0x80407100, + 0x472b2200, + 0xb003b064, + 0x82016238, + 0x31828162, + 0xef803d82, + 0x930292f1, + 0xa003673c, + 0x61e66556, + 0x646380a2, + 0xb05061e6, + 0x61e67100, + 0x82d092e0, + 0x473d2200, + 0x7000b2c0, + 0x22f080a0, + 0xb0304359, + 0x3162c102, + 0x80a0c001, + 0x43521e00, + 0x435322f0, + 0x3160f5a0, + 0x63533960, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006b54}; PATCH_FUN_SPEC void rf_patch_rfe_sl_longrange(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_wb_dsss.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_wb_dsss.h index ccfdadc..f48aa14 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_wb_dsss.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_wb_dsss.h @@ -1,496 +1,494 @@ /****************************************************************************** -* Filename: rf_patch_rfe_wb_dsss.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 Wideband DSSS -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - + * Filename: rf_patch_rfe_wb_dsss.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 Wideband DSSS + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_RFE_WB_DSSS_H #define _RF_PATCH_RFE_WB_DSSS_H -#include #include "../inc/hw_types.h" +#include #ifndef RFE_PATCH_TYPE - #define RFE_PATCH_TYPE static const uint32_t +#define RFE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_RFERAM_BASE - #define RFC_RFERAM_BASE 0x2100C000 +#define RFC_RFERAM_BASE 0x2100C000 #endif #ifndef RFE_PATCH_MODE - #define RFE_PATCH_MODE 0 +#define RFE_PATCH_MODE 0 #endif RFE_PATCH_TYPE patchWb_dsssRfe[429] = -{ - 0x000061a3, - 0x1307147f, - 0x24f1004d, - 0x3f131f2e, - 0x003f0ab0, - 0x0000ff07, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x43cf41cf, - 0x4fcf47cf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x00000000, - 0x0008000f, - 0x003f0000, - 0x00400000, - 0x0000003f, - 0x00680004, - 0x00dc000e, - 0x00430006, - 0x0005001a, - 0x00000000, - 0x00000002, - 0x0000003f, - 0x00040000, - 0x000000c0, - 0x00c00004, - 0x00070000, - 0x9100c050, - 0xc0707000, - 0x70009100, - 0x00213182, - 0xb1109131, - 0x81017000, - 0xa100b101, - 0x91323182, - 0x9101b110, - 0x81411011, - 0x404f2241, - 0x700006f1, - 0x9101c051, - 0x39101830, - 0xd0083183, - 0x6f413118, - 0x91310031, - 0x1483b110, - 0x685b1614, - 0x10257000, - 0x9100c050, - 0xc0c0c3f4, - 0x6f031420, - 0x04411031, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0x04411031, - 0x3182c082, - 0x91310021, - 0x3963b110, - 0xc0a21031, - 0x00213182, - 0xb1109131, - 0x31151050, - 0x92051405, - 0x643f7000, - 0x1031c052, - 0x31610631, - 0x644202c1, - 0x1031c112, - 0x06713921, - 0x02e13151, - 0x70006442, - 0x6599658a, - 0x8220c088, - 0x39803950, - 0x409f1e00, - 0x3001c041, - 0x1a181418, - 0x8230c089, - 0x39803960, - 0x40a91e00, - 0x3001c041, - 0x1a191419, - 0x9136643c, - 0x9134b110, - 0xb054b110, - 0xa0547100, - 0x80f0b064, - 0x40af2200, - 0x90b01240, - 0x8253b032, - 0x39533953, - 0x643f6485, - 0xc122c111, - 0xc1706442, - 0xc11168c2, - 0x6442c0c2, - 0x68c7c170, - 0x9100c050, - 0x92987227, - 0x16141615, - 0x10531042, - 0x8221c1f0, - 0x39313131, - 0x31313981, - 0xb270b051, - 0x72276572, - 0xb2709299, - 0x10731062, - 0x8231c3f0, - 0x39213121, - 0x101b3981, - 0xc0e26572, - 0x82603182, - 0x39803180, - 0xb0610002, - 0x91327100, - 0xa051b110, - 0x7227b061, - 0x68f3c230, - 0x12800000, - 0xb03290b0, - 0xc0507000, - 0x72279100, - 0x10629299, - 0xc3f01073, - 0x31218231, - 0x39813921, - 0xb270b051, - 0x7227657e, - 0xb2709298, - 0x10531042, - 0x8221c1f0, - 0x39313131, - 0x31313981, - 0x657e101a, - 0xb061a051, - 0xc0b07227, - 0x643f6918, - 0xc122c101, - 0xc1016442, - 0x6442c0c2, - 0x643c1a15, - 0xb1109135, - 0x64858253, - 0x90b012c0, - 0x7000b032, - 0xc272643f, - 0x6442c081, - 0xc111c122, - 0xc0026442, - 0x6442c111, - 0xc331c062, - 0xc3626442, - 0x6442c111, - 0xc111c302, - 0x82536442, - 0x64853953, - 0x6447c3e2, - 0x41402211, - 0xc881c242, - 0xc2526442, - 0x6442c111, - 0xcee1c272, - 0xc2026442, - 0x6442c881, - 0xc801c202, - 0xc0b06442, - 0x70006954, - 0xc242643f, - 0x6442c801, - 0xc011c252, - 0xc2726442, - 0x6442c0e1, - 0xc101c002, - 0xc0626442, - 0x6442c301, - 0xc101c122, - 0xc3626442, - 0x6442c101, - 0xc101c302, - 0x82536442, - 0x70006485, - 0x7100b061, - 0x1c231412, - 0x91334d7a, - 0x7000b110, - 0xb1109132, - 0x70006972, - 0x7100b061, - 0x1c321813, - 0x91324986, - 0x7000b110, - 0xb1109133, - 0x7000697e, - 0x6447c0c2, - 0xc0c21015, - 0x64471612, - 0x14153141, - 0x3180c0c0, - 0x10541405, - 0x040478a0, - 0xc0e67000, - 0xcc013186, - 0x10671416, - 0xc3f08261, - 0x14170401, - 0x73067000, - 0x720b7205, - 0xb050720e, - 0x80817100, - 0xa050b060, - 0x22418092, - 0x808045c3, - 0x0410c1f1, - 0x11011630, - 0x6c011401, - 0x61d761d6, - 0x61d961d8, - 0x61db61da, - 0x61de61dc, - 0x61e261e0, - 0x633661e4, - 0x80916339, - 0x0421c0f2, - 0x80823121, - 0x14122a42, - 0x11011632, - 0x6c011421, - 0x620b61ee, - 0x633961f4, - 0x620b61ee, - 0x633961f4, - 0x61e661e6, - 0x61e661e6, - 0x61e661e6, - 0x61e66494, - 0x61e664f9, - 0x61e6652a, - 0x61e66556, - 0x61e66746, - 0x90b01210, - 0x7306720e, - 0x12107205, - 0x61a79030, - 0x673ccff0, - 0xc003c1d4, - 0x6454c3c0, - 0x91507840, - 0x92107850, - 0x92207860, - 0x92307870, - 0x92407880, - 0x92607890, - 0x91907830, - 0x39408210, - 0x100106f0, - 0x14103110, - 0x67429200, - 0xa0bc61e6, - 0xa054a0e2, - 0x225080f0, - 0x80404615, - 0x472b2200, - 0xa040620d, - 0x318d822d, - 0x8210398d, - 0x0410c0f1, - 0x821a1009, - 0x041a394a, - 0x39808210, - 0x100e0410, - 0x10bc10ab, - 0x646310c2, - 0xcfe07229, - 0xb013673c, - 0x66c8b003, - 0xb050b053, - 0xb064b054, - 0x66a5b013, - 0x22e08210, - 0x66ae4638, - 0x80417100, - 0x472b2201, - 0x221080f0, - 0x22f0464b, - 0xb0644718, - 0x42382231, - 0x66ceb063, - 0x22e08210, - 0x66704638, - 0xb0646238, - 0x318f816f, - 0xdfd03d8f, - 0x673c92ff, - 0x80417100, - 0x472b2201, - 0x80f0b064, - 0x42652250, - 0x8211b063, - 0x466022c1, - 0x670566ce, - 0x22d18211, - 0x66704652, - 0x81616252, - 0x31818172, - 0x31823d81, - 0xefc03d82, - 0x930292f1, - 0x620b673c, - 0x91c081b0, - 0x829781d3, - 0x18d3a290, - 0x0bf34e7f, - 0x1ce31613, - 0x91c34aa4, - 0x143b81e3, - 0x1cba6290, - 0x1e23468b, - 0x1ce34a8b, - 0xb2904e8b, - 0x428b2207, - 0x1a1ba290, - 0x1ce36296, - 0x91c34aa4, - 0x183b81e3, - 0x4ea01cab, - 0x4aa21c9b, - 0x42a41cbc, - 0x821010b2, - 0x429d22d0, - 0x221080f0, - 0x646346a4, - 0x62a466a5, - 0x629410ab, - 0x6294109b, - 0x82307000, - 0x0410c0f1, - 0x7100b063, - 0x10bc6aa8, - 0x7000b0e0, - 0x91c281b2, - 0x820181d2, - 0x81511812, - 0x82411812, - 0x3d813181, - 0x4abf1c12, - 0xb032b0e2, - 0x92f2dfb0, - 0xc7f1673c, - 0x4ec31421, - 0x9162c812, - 0xb0319172, - 0x7000b0e1, - 0xc006c008, - 0x9160c800, - 0x70009170, - 0x81b08201, - 0x81d091c0, - 0x81511810, - 0x14061810, - 0x824280e1, - 0x3d823182, - 0x4ae41c20, - 0x2221b0e2, - 0xb03246e8, - 0xdfa01005, - 0x673c92f5, - 0x42e82221, - 0xb032a0e2, - 0x39418231, - 0x0401c0f0, - 0x42f61e01, - 0xc0101618, - 0x1c083010, - 0x10604704, - 0x10063c10, - 0x1461c7f1, - 0xc8164efa, - 0x81719166, - 0x3d813181, - 0x4b011c16, - 0xb0319176, - 0xc008c006, - 0x81617000, - 0x3d813181, - 0x39808240, - 0x1cf11801, - 0x14014b17, - 0x22c080b0, - 0xb0bc4717, - 0xef90b033, - 0x930f92f1, - 0x7000673c, - 0xb063a003, - 0xb0efb064, - 0x71006556, - 0x22008040, - 0xb064472b, - 0xa0ef652a, - 0x80407100, - 0x472b2200, - 0xb003b064, - 0x82016238, - 0x31828162, - 0xef803d82, - 0x930292f1, - 0xa003673c, - 0x61e66556, - 0x646380a2, - 0xb05061e6, - 0x61e67100, - 0x82d092e0, - 0x473d2200, - 0x7000b2c0, - 0x22f080a0, - 0xb0304359, - 0x3162c102, - 0x80a0c001, - 0x43521e00, - 0x435322f0, - 0x3160f5a0, - 0x63533960, - 0x1a101020, - 0x6e236f13, - 0x16121611, - 0x70006b54 -}; + { + 0x000061a3, + 0x1307147f, + 0x24f1004d, + 0x3f131f2e, + 0x003f0ab0, + 0x0000ff07, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x0008000f, + 0x003f0000, + 0x00400000, + 0x0000003f, + 0x00680004, + 0x00dc000e, + 0x00430006, + 0x0005001a, + 0x00000000, + 0x00000002, + 0x0000003f, + 0x00040000, + 0x000000c0, + 0x00c00004, + 0x00070000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x404f2241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x685b1614, + 0x10257000, + 0x9100c050, + 0xc0c0c3f4, + 0x6f031420, + 0x04411031, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x643f7000, + 0x1031c052, + 0x31610631, + 0x644202c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006442, + 0x6599658a, + 0x8220c088, + 0x39803950, + 0x409f1e00, + 0x3001c041, + 0x1a181418, + 0x8230c089, + 0x39803960, + 0x40a91e00, + 0x3001c041, + 0x1a191419, + 0x9136643c, + 0x9134b110, + 0xb054b110, + 0xa0547100, + 0x80f0b064, + 0x40af2200, + 0x90b01240, + 0x8253b032, + 0x39533953, + 0x643f6485, + 0xc122c111, + 0xc1706442, + 0xc11168c2, + 0x6442c0c2, + 0x68c7c170, + 0x9100c050, + 0x92987227, + 0x16141615, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0xb270b051, + 0x72276572, + 0xb2709299, + 0x10731062, + 0x8231c3f0, + 0x39213121, + 0x101b3981, + 0xc0e26572, + 0x82603182, + 0x39803180, + 0xb0610002, + 0x91327100, + 0xa051b110, + 0x7227b061, + 0x68f3c230, + 0x12800000, + 0xb03290b0, + 0xc0507000, + 0x72279100, + 0x10629299, + 0xc3f01073, + 0x31218231, + 0x39813921, + 0xb270b051, + 0x7227657e, + 0xb2709298, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0x657e101a, + 0xb061a051, + 0xc0b07227, + 0x643f6918, + 0xc122c101, + 0xc1016442, + 0x6442c0c2, + 0x643c1a15, + 0xb1109135, + 0x64858253, + 0x90b012c0, + 0x7000b032, + 0xc272643f, + 0x6442c081, + 0xc111c122, + 0xc0026442, + 0x6442c111, + 0xc331c062, + 0xc3626442, + 0x6442c111, + 0xc111c302, + 0x82536442, + 0x64853953, + 0x6447c3e2, + 0x41402211, + 0xc881c242, + 0xc2526442, + 0x6442c111, + 0xcee1c272, + 0xc2026442, + 0x6442c881, + 0xc801c202, + 0xc0b06442, + 0x70006954, + 0xc242643f, + 0x6442c801, + 0xc011c252, + 0xc2726442, + 0x6442c0e1, + 0xc101c002, + 0xc0626442, + 0x6442c301, + 0xc101c122, + 0xc3626442, + 0x6442c101, + 0xc101c302, + 0x82536442, + 0x70006485, + 0x7100b061, + 0x1c231412, + 0x91334d7a, + 0x7000b110, + 0xb1109132, + 0x70006972, + 0x7100b061, + 0x1c321813, + 0x91324986, + 0x7000b110, + 0xb1109133, + 0x7000697e, + 0x6447c0c2, + 0xc0c21015, + 0x64471612, + 0x14153141, + 0x3180c0c0, + 0x10541405, + 0x040478a0, + 0xc0e67000, + 0xcc013186, + 0x10671416, + 0xc3f08261, + 0x14170401, + 0x73067000, + 0x720b7205, + 0xb050720e, + 0x80817100, + 0xa050b060, + 0x22418092, + 0x808045c3, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x61d761d6, + 0x61d961d8, + 0x61db61da, + 0x61de61dc, + 0x61e261e0, + 0x633661e4, + 0x80916339, + 0x0421c0f2, + 0x80823121, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x620b61ee, + 0x633961f4, + 0x620b61ee, + 0x633961f4, + 0x61e661e6, + 0x61e661e6, + 0x61e661e6, + 0x61e66494, + 0x61e664f9, + 0x61e6652a, + 0x61e66556, + 0x61e66746, + 0x90b01210, + 0x7306720e, + 0x12107205, + 0x61a79030, + 0x673ccff0, + 0xc003c1d4, + 0x6454c3c0, + 0x91507840, + 0x92107850, + 0x92207860, + 0x92307870, + 0x92407880, + 0x92607890, + 0x91907830, + 0x39408210, + 0x100106f0, + 0x14103110, + 0x67429200, + 0xa0bc61e6, + 0xa054a0e2, + 0x225080f0, + 0x80404615, + 0x472b2200, + 0xa040620d, + 0x318d822d, + 0x8210398d, + 0x0410c0f1, + 0x821a1009, + 0x041a394a, + 0x39808210, + 0x100e0410, + 0x10bc10ab, + 0x646310c2, + 0xcfe07229, + 0xb013673c, + 0x66c8b003, + 0xb050b053, + 0xb064b054, + 0x66a5b013, + 0x22e08210, + 0x66ae4638, + 0x80417100, + 0x472b2201, + 0x221080f0, + 0x22f0464b, + 0xb0644718, + 0x42382231, + 0x66ceb063, + 0x22e08210, + 0x66704638, + 0xb0646238, + 0x318f816f, + 0xdfd03d8f, + 0x673c92ff, + 0x80417100, + 0x472b2201, + 0x80f0b064, + 0x42652250, + 0x8211b063, + 0x466022c1, + 0x670566ce, + 0x22d18211, + 0x66704652, + 0x81616252, + 0x31818172, + 0x31823d81, + 0xefc03d82, + 0x930292f1, + 0x620b673c, + 0x91c081b0, + 0x829781d3, + 0x18d3a290, + 0x0bf34e7f, + 0x1ce31613, + 0x91c34aa4, + 0x143b81e3, + 0x1cba6290, + 0x1e23468b, + 0x1ce34a8b, + 0xb2904e8b, + 0x428b2207, + 0x1a1ba290, + 0x1ce36296, + 0x91c34aa4, + 0x183b81e3, + 0x4ea01cab, + 0x4aa21c9b, + 0x42a41cbc, + 0x821010b2, + 0x429d22d0, + 0x221080f0, + 0x646346a4, + 0x62a466a5, + 0x629410ab, + 0x6294109b, + 0x82307000, + 0x0410c0f1, + 0x7100b063, + 0x10bc6aa8, + 0x7000b0e0, + 0x91c281b2, + 0x820181d2, + 0x81511812, + 0x82411812, + 0x3d813181, + 0x4abf1c12, + 0xb032b0e2, + 0x92f2dfb0, + 0xc7f1673c, + 0x4ec31421, + 0x9162c812, + 0xb0319172, + 0x7000b0e1, + 0xc006c008, + 0x9160c800, + 0x70009170, + 0x81b08201, + 0x81d091c0, + 0x81511810, + 0x14061810, + 0x824280e1, + 0x3d823182, + 0x4ae41c20, + 0x2221b0e2, + 0xb03246e8, + 0xdfa01005, + 0x673c92f5, + 0x42e82221, + 0xb032a0e2, + 0x39418231, + 0x0401c0f0, + 0x42f61e01, + 0xc0101618, + 0x1c083010, + 0x10604704, + 0x10063c10, + 0x1461c7f1, + 0xc8164efa, + 0x81719166, + 0x3d813181, + 0x4b011c16, + 0xb0319176, + 0xc008c006, + 0x81617000, + 0x3d813181, + 0x39808240, + 0x1cf11801, + 0x14014b17, + 0x22c080b0, + 0xb0bc4717, + 0xef90b033, + 0x930f92f1, + 0x7000673c, + 0xb063a003, + 0xb0efb064, + 0x71006556, + 0x22008040, + 0xb064472b, + 0xa0ef652a, + 0x80407100, + 0x472b2200, + 0xb003b064, + 0x82016238, + 0x31828162, + 0xef803d82, + 0x930292f1, + 0xa003673c, + 0x61e66556, + 0x646380a2, + 0xb05061e6, + 0x61e67100, + 0x82d092e0, + 0x473d2200, + 0x7000b2c0, + 0x22f080a0, + 0xb0304359, + 0x3162c102, + 0x80a0c001, + 0x43521e00, + 0x435322f0, + 0x3160f5a0, + 0x63533960, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006b54}; PATCH_FUN_SPEC void rf_patch_rfe_wb_dsss(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_wmbus_ctmode.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_wmbus_ctmode.h index a43f284..c029002 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_wmbus_ctmode.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_wmbus_ctmode.h @@ -1,496 +1,494 @@ /****************************************************************************** -* Filename: rf_patch_rfe_wmbus_ctmode.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 WMBUS C- and T-Mode -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - + * Filename: rf_patch_rfe_wmbus_ctmode.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 WMBUS C- and T-Mode + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_RFE_WMBUS_CTMODE_H #define _RF_PATCH_RFE_WMBUS_CTMODE_H -#include #include "../inc/hw_types.h" +#include #ifndef RFE_PATCH_TYPE - #define RFE_PATCH_TYPE static const uint32_t +#define RFE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_RFERAM_BASE - #define RFC_RFERAM_BASE 0x2100C000 +#define RFC_RFERAM_BASE 0x2100C000 #endif #ifndef RFE_PATCH_MODE - #define RFE_PATCH_MODE 0 +#define RFE_PATCH_MODE 0 #endif RFE_PATCH_TYPE patchWmbus_ctmodeRfe[429] = -{ - 0x000061a3, - 0x1307147f, - 0x24f1004d, - 0x3f131f2e, - 0x003f0ab0, - 0x0000ff07, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x43cf41cf, - 0x4fcf47cf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x00000000, - 0x0008000f, - 0x003f0000, - 0x00400000, - 0x0000003f, - 0x00680004, - 0x00dc000e, - 0x00430006, - 0x0005001a, - 0x00000000, - 0x00000002, - 0x0000003f, - 0x00040000, - 0x000000c0, - 0x00c00004, - 0x00070000, - 0x9100c050, - 0xc0707000, - 0x70009100, - 0x00213182, - 0xb1109131, - 0x81017000, - 0xa100b101, - 0x91323182, - 0x9101b110, - 0x81411011, - 0x404f2241, - 0x700006f1, - 0x9101c051, - 0x39101830, - 0xd0083183, - 0x6f413118, - 0x91310031, - 0x1483b110, - 0x685b1614, - 0x10257000, - 0x9100c050, - 0xc0c0c3f4, - 0x6f031420, - 0x04411031, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0x04411031, - 0x3182c082, - 0x91310021, - 0x3963b110, - 0xc0a21031, - 0x00213182, - 0xb1109131, - 0x31151050, - 0x92051405, - 0x643f7000, - 0x1031c052, - 0x31610631, - 0x644202c1, - 0x1031c112, - 0x06713921, - 0x02e13151, - 0x70006442, - 0x6599658a, - 0x8220c088, - 0x39803950, - 0x409f1e00, - 0x3001c041, - 0x1a181418, - 0x8230c089, - 0x39803960, - 0x40a91e00, - 0x3001c041, - 0x1a191419, - 0x9136643c, - 0x9134b110, - 0xb054b110, - 0xa0547100, - 0x80f0b064, - 0x40af2200, - 0x90b01240, - 0x8253b032, - 0x39533953, - 0x643f6485, - 0xc122c111, - 0xc1706442, - 0xc11168c2, - 0x6442c0c2, - 0x68c7c170, - 0x9100c050, - 0x92987227, - 0x16141615, - 0x10531042, - 0x8221c1f0, - 0x39313131, - 0x31313981, - 0xb270b051, - 0x72276572, - 0xb2709299, - 0x10731062, - 0x8231c3f0, - 0x39213121, - 0x101b3981, - 0xc0e26572, - 0x82603182, - 0x39803180, - 0xb0610002, - 0x91327100, - 0xa051b110, - 0x7227b061, - 0x68f3c230, - 0x12800000, - 0xb03290b0, - 0xc0507000, - 0x72279100, - 0x10629299, - 0xc3f01073, - 0x31218231, - 0x39813921, - 0xb270b051, - 0x7227657e, - 0xb2709298, - 0x10531042, - 0x8221c1f0, - 0x39313131, - 0x31313981, - 0x657e101a, - 0xb061a051, - 0xc0b07227, - 0x643f6918, - 0xc122c101, - 0xc1016442, - 0x6442c0c2, - 0x643c1a15, - 0xb1109135, - 0x64858253, - 0x90b012c0, - 0x7000b032, - 0xc272643f, - 0x6442c081, - 0xc111c122, - 0xc0026442, - 0x6442c111, - 0xc331c062, - 0xc3626442, - 0x6442c111, - 0xc111c302, - 0x82536442, - 0x64853953, - 0x6447c3e2, - 0x41402211, - 0xc881c242, - 0xc2526442, - 0x6442c111, - 0xcee1c272, - 0xc2026442, - 0x6442c881, - 0xc801c202, - 0xc0b06442, - 0x70006954, - 0xc242643f, - 0x6442c801, - 0xc011c252, - 0xc2726442, - 0x6442c0e1, - 0xc101c002, - 0xc0626442, - 0x6442c301, - 0xc101c122, - 0xc3626442, - 0x6442c101, - 0xc101c302, - 0x82536442, - 0x70006485, - 0x7100b061, - 0x1c231412, - 0x91334d7a, - 0x7000b110, - 0xb1109132, - 0x70006972, - 0x7100b061, - 0x1c321813, - 0x91324986, - 0x7000b110, - 0xb1109133, - 0x7000697e, - 0x6447c0c2, - 0xc0c21015, - 0x64471612, - 0x14153141, - 0x3180c0c0, - 0x10541405, - 0x040478a0, - 0xc0e67000, - 0xcc013186, - 0x10671416, - 0xc3f08261, - 0x14170401, - 0x73067000, - 0x720b7205, - 0xb050720e, - 0x80817100, - 0xa050b060, - 0x22418092, - 0x808045c3, - 0x0410c1f1, - 0x11011630, - 0x6c011401, - 0x61d761d6, - 0x61d961d8, - 0x61db61da, - 0x61de61dc, - 0x61e261e0, - 0x633661e4, - 0x80916339, - 0x0421c0f2, - 0x80823121, - 0x14122a42, - 0x11011632, - 0x6c011421, - 0x620b61ee, - 0x633961f4, - 0x620b61ee, - 0x633961f4, - 0x61e661e6, - 0x61e661e6, - 0x61e661e6, - 0x61e66494, - 0x61e664f9, - 0x61e6652a, - 0x61e66556, - 0x61e66746, - 0x90b01210, - 0x7306720e, - 0x12107205, - 0x61a79030, - 0x673ccff0, - 0xc003c1d4, - 0x6454c3c0, - 0x91507840, - 0x92107850, - 0x92207860, - 0x92307870, - 0x92407880, - 0x92607890, - 0x91907830, - 0x39408210, - 0x100106f0, - 0x14103110, - 0x67429200, - 0xa0bc61e6, - 0xa054a0e2, - 0x225080f0, - 0x80404615, - 0x472b2200, - 0xa040620d, - 0x318d822d, - 0x8210398d, - 0x0410c0f1, - 0x821a1009, - 0x041a394a, - 0x39808210, - 0x100e0410, - 0x10bc10ab, - 0x646310c2, - 0xcfe07229, - 0xb013673c, - 0x66c8b003, - 0xb050b053, - 0xb064b054, - 0x66a5b013, - 0x22e08210, - 0x66ae4638, - 0x80417100, - 0x472b2201, - 0x221080f0, - 0x22f0464b, - 0xb0644718, - 0x42382231, - 0x66ceb063, - 0x22e08210, - 0x66704638, - 0xb0646238, - 0x318f816f, - 0xdfd03d8f, - 0x673c92ff, - 0x80417100, - 0x472b2201, - 0x80f0b064, - 0x42652250, - 0x8211b063, - 0x466022c1, - 0x670566ce, - 0x22d18211, - 0x66704652, - 0x81616252, - 0x31818172, - 0x31823d81, - 0xefc03d82, - 0x930292f1, - 0x620b673c, - 0x91c081b0, - 0x829781d3, - 0x18d3a290, - 0x0bf34e7f, - 0x1ce31613, - 0x91c34aa4, - 0x143b81e3, - 0x1cba6290, - 0x1e23468b, - 0x1ce34a8b, - 0xb2904e8b, - 0x428b2207, - 0x1a1ba290, - 0x1ce36296, - 0x91c34aa4, - 0x183b81e3, - 0x4ea01cab, - 0x4aa21c9b, - 0x42a41cbc, - 0x821010b2, - 0x429d22d0, - 0x221080f0, - 0x646346a4, - 0x62a466a5, - 0x629410ab, - 0x6294109b, - 0x82307000, - 0x0410c0f1, - 0x7100b063, - 0x10bc6aa8, - 0x7000b0e0, - 0x91c281b2, - 0x820181d2, - 0x81511812, - 0x82411812, - 0x3d813181, - 0x4abf1c12, - 0xb032b0e2, - 0x92f2dfb0, - 0xc7f1673c, - 0x4ec31421, - 0x9162c812, - 0xb0319172, - 0x7000b0e1, - 0xc006c008, - 0x9160c800, - 0x70009170, - 0x81b08201, - 0x81d091c0, - 0x81511810, - 0x14061810, - 0x824280e1, - 0x3d823182, - 0x4ae41c20, - 0x2221b0e2, - 0xb03246e8, - 0xdfa01005, - 0x673c92f5, - 0x42e82221, - 0xb032a0e2, - 0x39418231, - 0x0401c0f0, - 0x42f61e01, - 0xc0101618, - 0x1c083010, - 0x10604704, - 0x10063c10, - 0x1461c7f1, - 0xc8164efa, - 0x81719166, - 0x3d813181, - 0x4b011c16, - 0xb0319176, - 0xc008c006, - 0x81617000, - 0x3d813181, - 0x39808240, - 0x1cf11801, - 0x14014b17, - 0x22c080b0, - 0xb0bc4717, - 0xef90b033, - 0x930f92f1, - 0x7000673c, - 0xb063a003, - 0xb0efb064, - 0x71006556, - 0x22008040, - 0xb064472b, - 0xa0ef652a, - 0x80407100, - 0x472b2200, - 0xb003b064, - 0x82016238, - 0x31828162, - 0xef803d82, - 0x930292f1, - 0xa003673c, - 0x61e66556, - 0x646380a2, - 0xb05061e6, - 0x61e67100, - 0x82d092e0, - 0x473d2200, - 0x7000b2c0, - 0x22f080a0, - 0xb0304359, - 0x3162c102, - 0x80a0c001, - 0x43521e00, - 0x435322f0, - 0x3160f5a0, - 0x63533960, - 0x1a101020, - 0x6e236f13, - 0x16121611, - 0x70006b54 -}; + { + 0x000061a3, + 0x1307147f, + 0x24f1004d, + 0x3f131f2e, + 0x003f0ab0, + 0x0000ff07, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x0008000f, + 0x003f0000, + 0x00400000, + 0x0000003f, + 0x00680004, + 0x00dc000e, + 0x00430006, + 0x0005001a, + 0x00000000, + 0x00000002, + 0x0000003f, + 0x00040000, + 0x000000c0, + 0x00c00004, + 0x00070000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x404f2241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x685b1614, + 0x10257000, + 0x9100c050, + 0xc0c0c3f4, + 0x6f031420, + 0x04411031, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x643f7000, + 0x1031c052, + 0x31610631, + 0x644202c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006442, + 0x6599658a, + 0x8220c088, + 0x39803950, + 0x409f1e00, + 0x3001c041, + 0x1a181418, + 0x8230c089, + 0x39803960, + 0x40a91e00, + 0x3001c041, + 0x1a191419, + 0x9136643c, + 0x9134b110, + 0xb054b110, + 0xa0547100, + 0x80f0b064, + 0x40af2200, + 0x90b01240, + 0x8253b032, + 0x39533953, + 0x643f6485, + 0xc122c111, + 0xc1706442, + 0xc11168c2, + 0x6442c0c2, + 0x68c7c170, + 0x9100c050, + 0x92987227, + 0x16141615, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0xb270b051, + 0x72276572, + 0xb2709299, + 0x10731062, + 0x8231c3f0, + 0x39213121, + 0x101b3981, + 0xc0e26572, + 0x82603182, + 0x39803180, + 0xb0610002, + 0x91327100, + 0xa051b110, + 0x7227b061, + 0x68f3c230, + 0x12800000, + 0xb03290b0, + 0xc0507000, + 0x72279100, + 0x10629299, + 0xc3f01073, + 0x31218231, + 0x39813921, + 0xb270b051, + 0x7227657e, + 0xb2709298, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0x657e101a, + 0xb061a051, + 0xc0b07227, + 0x643f6918, + 0xc122c101, + 0xc1016442, + 0x6442c0c2, + 0x643c1a15, + 0xb1109135, + 0x64858253, + 0x90b012c0, + 0x7000b032, + 0xc272643f, + 0x6442c081, + 0xc111c122, + 0xc0026442, + 0x6442c111, + 0xc331c062, + 0xc3626442, + 0x6442c111, + 0xc111c302, + 0x82536442, + 0x64853953, + 0x6447c3e2, + 0x41402211, + 0xc881c242, + 0xc2526442, + 0x6442c111, + 0xcee1c272, + 0xc2026442, + 0x6442c881, + 0xc801c202, + 0xc0b06442, + 0x70006954, + 0xc242643f, + 0x6442c801, + 0xc011c252, + 0xc2726442, + 0x6442c0e1, + 0xc101c002, + 0xc0626442, + 0x6442c301, + 0xc101c122, + 0xc3626442, + 0x6442c101, + 0xc101c302, + 0x82536442, + 0x70006485, + 0x7100b061, + 0x1c231412, + 0x91334d7a, + 0x7000b110, + 0xb1109132, + 0x70006972, + 0x7100b061, + 0x1c321813, + 0x91324986, + 0x7000b110, + 0xb1109133, + 0x7000697e, + 0x6447c0c2, + 0xc0c21015, + 0x64471612, + 0x14153141, + 0x3180c0c0, + 0x10541405, + 0x040478a0, + 0xc0e67000, + 0xcc013186, + 0x10671416, + 0xc3f08261, + 0x14170401, + 0x73067000, + 0x720b7205, + 0xb050720e, + 0x80817100, + 0xa050b060, + 0x22418092, + 0x808045c3, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x61d761d6, + 0x61d961d8, + 0x61db61da, + 0x61de61dc, + 0x61e261e0, + 0x633661e4, + 0x80916339, + 0x0421c0f2, + 0x80823121, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x620b61ee, + 0x633961f4, + 0x620b61ee, + 0x633961f4, + 0x61e661e6, + 0x61e661e6, + 0x61e661e6, + 0x61e66494, + 0x61e664f9, + 0x61e6652a, + 0x61e66556, + 0x61e66746, + 0x90b01210, + 0x7306720e, + 0x12107205, + 0x61a79030, + 0x673ccff0, + 0xc003c1d4, + 0x6454c3c0, + 0x91507840, + 0x92107850, + 0x92207860, + 0x92307870, + 0x92407880, + 0x92607890, + 0x91907830, + 0x39408210, + 0x100106f0, + 0x14103110, + 0x67429200, + 0xa0bc61e6, + 0xa054a0e2, + 0x225080f0, + 0x80404615, + 0x472b2200, + 0xa040620d, + 0x318d822d, + 0x8210398d, + 0x0410c0f1, + 0x821a1009, + 0x041a394a, + 0x39808210, + 0x100e0410, + 0x10bc10ab, + 0x646310c2, + 0xcfe07229, + 0xb013673c, + 0x66c8b003, + 0xb050b053, + 0xb064b054, + 0x66a5b013, + 0x22e08210, + 0x66ae4638, + 0x80417100, + 0x472b2201, + 0x221080f0, + 0x22f0464b, + 0xb0644718, + 0x42382231, + 0x66ceb063, + 0x22e08210, + 0x66704638, + 0xb0646238, + 0x318f816f, + 0xdfd03d8f, + 0x673c92ff, + 0x80417100, + 0x472b2201, + 0x80f0b064, + 0x42652250, + 0x8211b063, + 0x466022c1, + 0x670566ce, + 0x22d18211, + 0x66704652, + 0x81616252, + 0x31818172, + 0x31823d81, + 0xefc03d82, + 0x930292f1, + 0x620b673c, + 0x91c081b0, + 0x829781d3, + 0x18d3a290, + 0x0bf34e7f, + 0x1ce31613, + 0x91c34aa4, + 0x143b81e3, + 0x1cba6290, + 0x1e23468b, + 0x1ce34a8b, + 0xb2904e8b, + 0x428b2207, + 0x1a1ba290, + 0x1ce36296, + 0x91c34aa4, + 0x183b81e3, + 0x4ea01cab, + 0x4aa21c9b, + 0x42a41cbc, + 0x821010b2, + 0x429d22d0, + 0x221080f0, + 0x646346a4, + 0x62a466a5, + 0x629410ab, + 0x6294109b, + 0x82307000, + 0x0410c0f1, + 0x7100b063, + 0x10bc6aa8, + 0x7000b0e0, + 0x91c281b2, + 0x820181d2, + 0x81511812, + 0x82411812, + 0x3d813181, + 0x4abf1c12, + 0xb032b0e2, + 0x92f2dfb0, + 0xc7f1673c, + 0x4ec31421, + 0x9162c812, + 0xb0319172, + 0x7000b0e1, + 0xc006c008, + 0x9160c800, + 0x70009170, + 0x81b08201, + 0x81d091c0, + 0x81511810, + 0x14061810, + 0x824280e1, + 0x3d823182, + 0x4ae41c20, + 0x2221b0e2, + 0xb03246e8, + 0xdfa01005, + 0x673c92f5, + 0x42e82221, + 0xb032a0e2, + 0x39418231, + 0x0401c0f0, + 0x42f61e01, + 0xc0101618, + 0x1c083010, + 0x10604704, + 0x10063c10, + 0x1461c7f1, + 0xc8164efa, + 0x81719166, + 0x3d813181, + 0x4b011c16, + 0xb0319176, + 0xc008c006, + 0x81617000, + 0x3d813181, + 0x39808240, + 0x1cf11801, + 0x14014b17, + 0x22c080b0, + 0xb0bc4717, + 0xef90b033, + 0x930f92f1, + 0x7000673c, + 0xb063a003, + 0xb0efb064, + 0x71006556, + 0x22008040, + 0xb064472b, + 0xa0ef652a, + 0x80407100, + 0x472b2200, + 0xb003b064, + 0x82016238, + 0x31828162, + 0xef803d82, + 0x930292f1, + 0xa003673c, + 0x61e66556, + 0x646380a2, + 0xb05061e6, + 0x61e67100, + 0x82d092e0, + 0x473d2200, + 0x7000b2c0, + 0x22f080a0, + 0xb0304359, + 0x3162c102, + 0x80a0c001, + 0x43521e00, + 0x435322f0, + 0x3160f5a0, + 0x63533960, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006b54}; PATCH_FUN_SPEC void rf_patch_rfe_wmbus_ctmode(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_wmbus_smode.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_wmbus_smode.h index 85c9fcc..379455a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_wmbus_smode.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x0/rf_patches/rf_patch_rfe_wmbus_smode.h @@ -1,496 +1,494 @@ /****************************************************************************** -* Filename: rf_patch_rfe_wmbus_smode.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC13x0 WMBUS S-Mode -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - + * Filename: rf_patch_rfe_wmbus_smode.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC13x0 WMBUS S-Mode + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_RFE_WMBUS_SMODE_H #define _RF_PATCH_RFE_WMBUS_SMODE_H -#include #include "../inc/hw_types.h" +#include #ifndef RFE_PATCH_TYPE - #define RFE_PATCH_TYPE static const uint32_t +#define RFE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_RFERAM_BASE - #define RFC_RFERAM_BASE 0x2100C000 +#define RFC_RFERAM_BASE 0x2100C000 #endif #ifndef RFE_PATCH_MODE - #define RFE_PATCH_MODE 0 +#define RFE_PATCH_MODE 0 #endif RFE_PATCH_TYPE patchWmbus_smodeRfe[429] = -{ - 0x000061a3, - 0x1307147f, - 0x24f1004d, - 0x3f131f2e, - 0x003f0ab0, - 0x0000ff07, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x43cf41cf, - 0x4fcf47cf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x00000000, - 0x0008000f, - 0x003f0000, - 0x00400000, - 0x0000003f, - 0x00680004, - 0x00dc000e, - 0x00430006, - 0x0005001a, - 0x00000000, - 0x00000002, - 0x0000003f, - 0x00040000, - 0x000000c0, - 0x00c00004, - 0x00070000, - 0x9100c050, - 0xc0707000, - 0x70009100, - 0x00213182, - 0xb1109131, - 0x81017000, - 0xa100b101, - 0x91323182, - 0x9101b110, - 0x81411011, - 0x404f2241, - 0x700006f1, - 0x9101c051, - 0x39101830, - 0xd0083183, - 0x6f413118, - 0x91310031, - 0x1483b110, - 0x685b1614, - 0x10257000, - 0x9100c050, - 0xc0c0c3f4, - 0x6f031420, - 0x04411031, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0x04411031, - 0x3182c082, - 0x91310021, - 0x3963b110, - 0xc0a21031, - 0x00213182, - 0xb1109131, - 0x31151050, - 0x92051405, - 0x643f7000, - 0x1031c052, - 0x31610631, - 0x644202c1, - 0x1031c112, - 0x06713921, - 0x02e13151, - 0x70006442, - 0x6599658a, - 0x8220c088, - 0x39803950, - 0x409f1e00, - 0x3001c041, - 0x1a181418, - 0x8230c089, - 0x39803960, - 0x40a91e00, - 0x3001c041, - 0x1a191419, - 0x9136643c, - 0x9134b110, - 0xb054b110, - 0xa0547100, - 0x80f0b064, - 0x40af2200, - 0x90b01240, - 0x8253b032, - 0x39533953, - 0x643f6485, - 0xc122c111, - 0xc1706442, - 0xc11168c2, - 0x6442c0c2, - 0x68c7c170, - 0x9100c050, - 0x92987227, - 0x16141615, - 0x10531042, - 0x8221c1f0, - 0x39313131, - 0x31313981, - 0xb270b051, - 0x72276572, - 0xb2709299, - 0x10731062, - 0x8231c3f0, - 0x39213121, - 0x101b3981, - 0xc0e26572, - 0x82603182, - 0x39803180, - 0xb0610002, - 0x91327100, - 0xa051b110, - 0x7227b061, - 0x68f3c230, - 0x12800000, - 0xb03290b0, - 0xc0507000, - 0x72279100, - 0x10629299, - 0xc3f01073, - 0x31218231, - 0x39813921, - 0xb270b051, - 0x7227657e, - 0xb2709298, - 0x10531042, - 0x8221c1f0, - 0x39313131, - 0x31313981, - 0x657e101a, - 0xb061a051, - 0xc0b07227, - 0x643f6918, - 0xc122c101, - 0xc1016442, - 0x6442c0c2, - 0x643c1a15, - 0xb1109135, - 0x64858253, - 0x90b012c0, - 0x7000b032, - 0xc272643f, - 0x6442c081, - 0xc111c122, - 0xc0026442, - 0x6442c111, - 0xc331c062, - 0xc3626442, - 0x6442c111, - 0xc111c302, - 0x82536442, - 0x64853953, - 0x6447c3e2, - 0x41402211, - 0xc881c242, - 0xc2526442, - 0x6442c111, - 0xcee1c272, - 0xc2026442, - 0x6442c881, - 0xc801c202, - 0xc0b06442, - 0x70006954, - 0xc242643f, - 0x6442c801, - 0xc011c252, - 0xc2726442, - 0x6442c0e1, - 0xc101c002, - 0xc0626442, - 0x6442c301, - 0xc101c122, - 0xc3626442, - 0x6442c101, - 0xc101c302, - 0x82536442, - 0x70006485, - 0x7100b061, - 0x1c231412, - 0x91334d7a, - 0x7000b110, - 0xb1109132, - 0x70006972, - 0x7100b061, - 0x1c321813, - 0x91324986, - 0x7000b110, - 0xb1109133, - 0x7000697e, - 0x6447c0c2, - 0xc0c21015, - 0x64471612, - 0x14153141, - 0x3180c0c0, - 0x10541405, - 0x040478a0, - 0xc0e67000, - 0xcc013186, - 0x10671416, - 0xc3f08261, - 0x14170401, - 0x73067000, - 0x720b7205, - 0xb050720e, - 0x80817100, - 0xa050b060, - 0x22418092, - 0x808045c3, - 0x0410c1f1, - 0x11011630, - 0x6c011401, - 0x61d761d6, - 0x61d961d8, - 0x61db61da, - 0x61de61dc, - 0x61e261e0, - 0x633661e4, - 0x80916339, - 0x0421c0f2, - 0x80823121, - 0x14122a42, - 0x11011632, - 0x6c011421, - 0x620b61ee, - 0x633961f4, - 0x620b61ee, - 0x633961f4, - 0x61e661e6, - 0x61e661e6, - 0x61e661e6, - 0x61e66494, - 0x61e664f9, - 0x61e6652a, - 0x61e66556, - 0x61e66746, - 0x90b01210, - 0x7306720e, - 0x12107205, - 0x61a79030, - 0x673ccff0, - 0xc003c1d4, - 0x6454c3c0, - 0x91507840, - 0x92107850, - 0x92207860, - 0x92307870, - 0x92407880, - 0x92607890, - 0x91907830, - 0x39408210, - 0x100106f0, - 0x14103110, - 0x67429200, - 0xa0bc61e6, - 0xa054a0e2, - 0x225080f0, - 0x80404615, - 0x472b2200, - 0xa040620d, - 0x318d822d, - 0x8210398d, - 0x0410c0f1, - 0x821a1009, - 0x041a394a, - 0x39808210, - 0x100e0410, - 0x10bc10ab, - 0x646310c2, - 0xcfe07229, - 0xb013673c, - 0x66c8b003, - 0xb050b053, - 0xb064b054, - 0x66a5b013, - 0x22e08210, - 0x66ae4638, - 0x80417100, - 0x472b2201, - 0x221080f0, - 0x22f0464b, - 0xb0644718, - 0x42382231, - 0x66ceb063, - 0x22e08210, - 0x66704638, - 0xb0646238, - 0x318f816f, - 0xdfd03d8f, - 0x673c92ff, - 0x80417100, - 0x472b2201, - 0x80f0b064, - 0x42652250, - 0x8211b063, - 0x466022c1, - 0x670566ce, - 0x22d18211, - 0x66704652, - 0x81616252, - 0x31818172, - 0x31823d81, - 0xefc03d82, - 0x930292f1, - 0x620b673c, - 0x91c081b0, - 0x829781d3, - 0x18d3a290, - 0x0bf34e7f, - 0x1ce31613, - 0x91c34aa4, - 0x143b81e3, - 0x1cba6290, - 0x1e23468b, - 0x1ce34a8b, - 0xb2904e8b, - 0x428b2207, - 0x1a1ba290, - 0x1ce36296, - 0x91c34aa4, - 0x183b81e3, - 0x4ea01cab, - 0x4aa21c9b, - 0x42a41cbc, - 0x821010b2, - 0x429d22d0, - 0x221080f0, - 0x646346a4, - 0x62a466a5, - 0x629410ab, - 0x6294109b, - 0x82307000, - 0x0410c0f1, - 0x7100b063, - 0x10bc6aa8, - 0x7000b0e0, - 0x91c281b2, - 0x820181d2, - 0x81511812, - 0x82411812, - 0x3d813181, - 0x4abf1c12, - 0xb032b0e2, - 0x92f2dfb0, - 0xc7f1673c, - 0x4ec31421, - 0x9162c812, - 0xb0319172, - 0x7000b0e1, - 0xc006c008, - 0x9160c800, - 0x70009170, - 0x81b08201, - 0x81d091c0, - 0x81511810, - 0x14061810, - 0x824280e1, - 0x3d823182, - 0x4ae41c20, - 0x2221b0e2, - 0xb03246e8, - 0xdfa01005, - 0x673c92f5, - 0x42e82221, - 0xb032a0e2, - 0x39418231, - 0x0401c0f0, - 0x42f61e01, - 0xc0101618, - 0x1c083010, - 0x10604704, - 0x10063c10, - 0x1461c7f1, - 0xc8164efa, - 0x81719166, - 0x3d813181, - 0x4b011c16, - 0xb0319176, - 0xc008c006, - 0x81617000, - 0x3d813181, - 0x39808240, - 0x1cf11801, - 0x14014b17, - 0x22c080b0, - 0xb0bc4717, - 0xef90b033, - 0x930f92f1, - 0x7000673c, - 0xb063a003, - 0xb0efb064, - 0x71006556, - 0x22008040, - 0xb064472b, - 0xa0ef652a, - 0x80407100, - 0x472b2200, - 0xb003b064, - 0x82016238, - 0x31828162, - 0xef803d82, - 0x930292f1, - 0xa003673c, - 0x61e66556, - 0x646380a2, - 0xb05061e6, - 0x61e67100, - 0x82d092e0, - 0x473d2200, - 0x7000b2c0, - 0x22f080a0, - 0xb0304359, - 0x3162c102, - 0x80a0c001, - 0x43521e00, - 0x435322f0, - 0x3160f5a0, - 0x63533960, - 0x1a101020, - 0x6e236f13, - 0x16121611, - 0x70006b54 -}; + { + 0x000061a3, + 0x1307147f, + 0x24f1004d, + 0x3f131f2e, + 0x003f0ab0, + 0x0000ff07, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x0008000f, + 0x003f0000, + 0x00400000, + 0x0000003f, + 0x00680004, + 0x00dc000e, + 0x00430006, + 0x0005001a, + 0x00000000, + 0x00000002, + 0x0000003f, + 0x00040000, + 0x000000c0, + 0x00c00004, + 0x00070000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x404f2241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x685b1614, + 0x10257000, + 0x9100c050, + 0xc0c0c3f4, + 0x6f031420, + 0x04411031, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x643f7000, + 0x1031c052, + 0x31610631, + 0x644202c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006442, + 0x6599658a, + 0x8220c088, + 0x39803950, + 0x409f1e00, + 0x3001c041, + 0x1a181418, + 0x8230c089, + 0x39803960, + 0x40a91e00, + 0x3001c041, + 0x1a191419, + 0x9136643c, + 0x9134b110, + 0xb054b110, + 0xa0547100, + 0x80f0b064, + 0x40af2200, + 0x90b01240, + 0x8253b032, + 0x39533953, + 0x643f6485, + 0xc122c111, + 0xc1706442, + 0xc11168c2, + 0x6442c0c2, + 0x68c7c170, + 0x9100c050, + 0x92987227, + 0x16141615, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0xb270b051, + 0x72276572, + 0xb2709299, + 0x10731062, + 0x8231c3f0, + 0x39213121, + 0x101b3981, + 0xc0e26572, + 0x82603182, + 0x39803180, + 0xb0610002, + 0x91327100, + 0xa051b110, + 0x7227b061, + 0x68f3c230, + 0x12800000, + 0xb03290b0, + 0xc0507000, + 0x72279100, + 0x10629299, + 0xc3f01073, + 0x31218231, + 0x39813921, + 0xb270b051, + 0x7227657e, + 0xb2709298, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0x657e101a, + 0xb061a051, + 0xc0b07227, + 0x643f6918, + 0xc122c101, + 0xc1016442, + 0x6442c0c2, + 0x643c1a15, + 0xb1109135, + 0x64858253, + 0x90b012c0, + 0x7000b032, + 0xc272643f, + 0x6442c081, + 0xc111c122, + 0xc0026442, + 0x6442c111, + 0xc331c062, + 0xc3626442, + 0x6442c111, + 0xc111c302, + 0x82536442, + 0x64853953, + 0x6447c3e2, + 0x41402211, + 0xc881c242, + 0xc2526442, + 0x6442c111, + 0xcee1c272, + 0xc2026442, + 0x6442c881, + 0xc801c202, + 0xc0b06442, + 0x70006954, + 0xc242643f, + 0x6442c801, + 0xc011c252, + 0xc2726442, + 0x6442c0e1, + 0xc101c002, + 0xc0626442, + 0x6442c301, + 0xc101c122, + 0xc3626442, + 0x6442c101, + 0xc101c302, + 0x82536442, + 0x70006485, + 0x7100b061, + 0x1c231412, + 0x91334d7a, + 0x7000b110, + 0xb1109132, + 0x70006972, + 0x7100b061, + 0x1c321813, + 0x91324986, + 0x7000b110, + 0xb1109133, + 0x7000697e, + 0x6447c0c2, + 0xc0c21015, + 0x64471612, + 0x14153141, + 0x3180c0c0, + 0x10541405, + 0x040478a0, + 0xc0e67000, + 0xcc013186, + 0x10671416, + 0xc3f08261, + 0x14170401, + 0x73067000, + 0x720b7205, + 0xb050720e, + 0x80817100, + 0xa050b060, + 0x22418092, + 0x808045c3, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x61d761d6, + 0x61d961d8, + 0x61db61da, + 0x61de61dc, + 0x61e261e0, + 0x633661e4, + 0x80916339, + 0x0421c0f2, + 0x80823121, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x620b61ee, + 0x633961f4, + 0x620b61ee, + 0x633961f4, + 0x61e661e6, + 0x61e661e6, + 0x61e661e6, + 0x61e66494, + 0x61e664f9, + 0x61e6652a, + 0x61e66556, + 0x61e66746, + 0x90b01210, + 0x7306720e, + 0x12107205, + 0x61a79030, + 0x673ccff0, + 0xc003c1d4, + 0x6454c3c0, + 0x91507840, + 0x92107850, + 0x92207860, + 0x92307870, + 0x92407880, + 0x92607890, + 0x91907830, + 0x39408210, + 0x100106f0, + 0x14103110, + 0x67429200, + 0xa0bc61e6, + 0xa054a0e2, + 0x225080f0, + 0x80404615, + 0x472b2200, + 0xa040620d, + 0x318d822d, + 0x8210398d, + 0x0410c0f1, + 0x821a1009, + 0x041a394a, + 0x39808210, + 0x100e0410, + 0x10bc10ab, + 0x646310c2, + 0xcfe07229, + 0xb013673c, + 0x66c8b003, + 0xb050b053, + 0xb064b054, + 0x66a5b013, + 0x22e08210, + 0x66ae4638, + 0x80417100, + 0x472b2201, + 0x221080f0, + 0x22f0464b, + 0xb0644718, + 0x42382231, + 0x66ceb063, + 0x22e08210, + 0x66704638, + 0xb0646238, + 0x318f816f, + 0xdfd03d8f, + 0x673c92ff, + 0x80417100, + 0x472b2201, + 0x80f0b064, + 0x42652250, + 0x8211b063, + 0x466022c1, + 0x670566ce, + 0x22d18211, + 0x66704652, + 0x81616252, + 0x31818172, + 0x31823d81, + 0xefc03d82, + 0x930292f1, + 0x620b673c, + 0x91c081b0, + 0x829781d3, + 0x18d3a290, + 0x0bf34e7f, + 0x1ce31613, + 0x91c34aa4, + 0x143b81e3, + 0x1cba6290, + 0x1e23468b, + 0x1ce34a8b, + 0xb2904e8b, + 0x428b2207, + 0x1a1ba290, + 0x1ce36296, + 0x91c34aa4, + 0x183b81e3, + 0x4ea01cab, + 0x4aa21c9b, + 0x42a41cbc, + 0x821010b2, + 0x429d22d0, + 0x221080f0, + 0x646346a4, + 0x62a466a5, + 0x629410ab, + 0x6294109b, + 0x82307000, + 0x0410c0f1, + 0x7100b063, + 0x10bc6aa8, + 0x7000b0e0, + 0x91c281b2, + 0x820181d2, + 0x81511812, + 0x82411812, + 0x3d813181, + 0x4abf1c12, + 0xb032b0e2, + 0x92f2dfb0, + 0xc7f1673c, + 0x4ec31421, + 0x9162c812, + 0xb0319172, + 0x7000b0e1, + 0xc006c008, + 0x9160c800, + 0x70009170, + 0x81b08201, + 0x81d091c0, + 0x81511810, + 0x14061810, + 0x824280e1, + 0x3d823182, + 0x4ae41c20, + 0x2221b0e2, + 0xb03246e8, + 0xdfa01005, + 0x673c92f5, + 0x42e82221, + 0xb032a0e2, + 0x39418231, + 0x0401c0f0, + 0x42f61e01, + 0xc0101618, + 0x1c083010, + 0x10604704, + 0x10063c10, + 0x1461c7f1, + 0xc8164efa, + 0x81719166, + 0x3d813181, + 0x4b011c16, + 0xb0319176, + 0xc008c006, + 0x81617000, + 0x3d813181, + 0x39808240, + 0x1cf11801, + 0x14014b17, + 0x22c080b0, + 0xb0bc4717, + 0xef90b033, + 0x930f92f1, + 0x7000673c, + 0xb063a003, + 0xb0efb064, + 0x71006556, + 0x22008040, + 0xb064472b, + 0xa0ef652a, + 0x80407100, + 0x472b2200, + 0xb003b064, + 0x82016238, + 0x31828162, + 0xef803d82, + 0x930292f1, + 0xa003673c, + 0x61e66556, + 0x646380a2, + 0xb05061e6, + 0x61e67100, + 0x82d092e0, + 0x473d2200, + 0x7000b2c0, + 0x22f080a0, + 0xb0304359, + 0x3162c102, + 0x80a0c001, + 0x43521e00, + 0x435322f0, + 0x3160f5a0, + 0x63533960, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006b54}; PATCH_FUN_SPEC void rf_patch_rfe_wmbus_smode(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/adi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/adi.h index 969c8de..1e26beb 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/adi.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/adi.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: adi.h -* Revised: 2016-11-17 16:39:28 +0100 (Thu, 17 Nov 2016) -* Revision: 47706 -* -* Description: Defines and prototypes for the ADI master interface. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: adi.h + * Revised: 2016-11-17 16:39:28 +0100 (Thu, 17 Nov 2016) + * Revision: 47706 + * + * Description: Defines and prototypes for the ADI master interface. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,36 +55,34 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include +#include "../inc/hw_adi.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" #include "../inc/hw_types.h" #include "../inc/hw_uart.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_adi.h" -#include "debug.h" #include "ddi.h" +#include "debug.h" +#include +#include //***************************************************************************** // // Number of registers in the ADI slave // //***************************************************************************** -#define ADI_SLAVE_REGS 16 - +#define ADI_SLAVE_REGS 16 //***************************************************************************** // // Defines that is used to control the ADI slave and master // //***************************************************************************** -#define ADI_PROTECT 0x00000080 -#define ADI_ACK 0x00000001 -#define ADI_SYNC 0x00000000 +#define ADI_PROTECT 0x00000080 +#define ADI_ACK 0x00000001 +#define ADI_SYNC 0x00000000 //***************************************************************************** // @@ -114,10 +112,6 @@ ADIBaseValid(uint32_t ui32Base) } #endif - - - - //***************************************************************************** // //! \brief Write an 8 bit value to a register in an ADI slave. diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/adi_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/adi_doc.h index 5543464..cb66827 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/adi_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/adi_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: adi_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: adi_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup adi_api //! @{ //! \section sec_adi Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aes.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aes.h index 2f21964..59b5085 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aes.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aes.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aes.h -* Revised: 2019-01-25 14:45:16 +0100 (Fri, 25 Jan 2019) -* Revision: 54287 -* -* Description: AES header file. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aes.h + * Revised: 2019-01-25 14:45:16 +0100 (Fri, 25 Jan 2019) + * Revision: 54287 + * + * Description: AES header file. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,20 +55,19 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_crypto.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" #include #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_crypto.h" -#include "debug.h" -#include "interrupt.h" -#include "cpu.h" //***************************************************************************** // @@ -84,18 +83,17 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AESStartDMAOperation NOROM_AESStartDMAOperation -#define AESSetInitializationVector NOROM_AESSetInitializationVector +#define AESStartDMAOperation NOROM_AESStartDMAOperation +#define AESSetInitializationVector NOROM_AESSetInitializationVector #define AESWriteCCMInitializationVector NOROM_AESWriteCCMInitializationVector -#define AESReadTag NOROM_AESReadTag -#define AESVerifyTag NOROM_AESVerifyTag -#define AESWriteToKeyStore NOROM_AESWriteToKeyStore -#define AESReadFromKeyStore NOROM_AESReadFromKeyStore -#define AESWaitForIRQFlags NOROM_AESWaitForIRQFlags -#define AESConfigureCCMCtrl NOROM_AESConfigureCCMCtrl +#define AESReadTag NOROM_AESReadTag +#define AESVerifyTag NOROM_AESVerifyTag +#define AESWriteToKeyStore NOROM_AESWriteToKeyStore +#define AESReadFromKeyStore NOROM_AESReadFromKeyStore +#define AESWaitForIRQFlags NOROM_AESWaitForIRQFlags +#define AESConfigureCCMCtrl NOROM_AESConfigureCCMCtrl #endif - //***************************************************************************** // // Values that can be passed to AESIntEnable, AESIntDisable, and AESIntClear @@ -104,12 +102,11 @@ extern "C" // function to see if it supports other interrupt status flags. // //***************************************************************************** -#define AES_DMA_IN_DONE CRYPTO_IRQEN_DMA_IN_DONE_M -#define AES_RESULT_RDY CRYPTO_IRQEN_RESULT_AVAIL_M -#define AES_DMA_BUS_ERR CRYPTO_IRQCLR_DMA_BUS_ERR_M -#define AES_KEY_ST_WR_ERR CRYPTO_IRQCLR_KEY_ST_WR_ERR_M -#define AES_KEY_ST_RD_ERR CRYPTO_IRQCLR_KEY_ST_RD_ERR_M - +#define AES_DMA_IN_DONE CRYPTO_IRQEN_DMA_IN_DONE_M +#define AES_RESULT_RDY CRYPTO_IRQEN_RESULT_AVAIL_M +#define AES_DMA_BUS_ERR CRYPTO_IRQCLR_DMA_BUS_ERR_M +#define AES_KEY_ST_WR_ERR CRYPTO_IRQCLR_KEY_ST_WR_ERR_M +#define AES_KEY_ST_RD_ERR CRYPTO_IRQCLR_KEY_ST_RD_ERR_M //***************************************************************************** // @@ -118,33 +115,32 @@ extern "C" //***************************************************************************** // AES module return codes -#define AES_SUCCESS 0 -#define AES_KEYSTORE_ERROR 1 -#define AES_KEYSTORE_AREA_INVALID 2 -#define AES_DMA_BUSY 3 -#define AES_DMA_ERROR 4 -#define AES_TAG_NOT_READY 5 -#define AES_TAG_VERIFICATION_FAILED 6 +#define AES_SUCCESS 0 +#define AES_KEYSTORE_ERROR 1 +#define AES_KEYSTORE_AREA_INVALID 2 +#define AES_DMA_BUSY 3 +#define AES_DMA_ERROR 4 +#define AES_TAG_NOT_READY 5 +#define AES_TAG_VERIFICATION_FAILED 6 // Key store module defines -#define AES_IV_LENGTH_BYTES 16 -#define AES_TAG_LENGTH_BYTES 16 -#define AES_128_KEY_LENGTH_BYTES (128 / 8) -#define AES_192_KEY_LENGTH_BYTES (192 / 8) -#define AES_256_KEY_LENGTH_BYTES (256 / 8) +#define AES_IV_LENGTH_BYTES 16 +#define AES_TAG_LENGTH_BYTES 16 +#define AES_128_KEY_LENGTH_BYTES (128 / 8) +#define AES_192_KEY_LENGTH_BYTES (192 / 8) +#define AES_256_KEY_LENGTH_BYTES (256 / 8) -#define AES_BLOCK_SIZE 16 +#define AES_BLOCK_SIZE 16 // DMA status codes -#define AES_DMA_CHANNEL0_ACTIVE CRYPTO_DMASTAT_CH0_ACT_M -#define AES_DMA_CHANNEL1_ACTIVE CRYPTO_DMASTAT_CH1_ACT_M -#define AES_DMA_PORT_ERROR CRYPTO_DMASTAT_PORT_ERR_M +#define AES_DMA_CHANNEL0_ACTIVE CRYPTO_DMASTAT_CH0_ACT_M +#define AES_DMA_CHANNEL1_ACTIVE CRYPTO_DMASTAT_CH1_ACT_M +#define AES_DMA_PORT_ERROR CRYPTO_DMASTAT_PORT_ERR_M // Crypto module operation types -#define AES_ALGSEL_AES CRYPTO_ALGSEL_AES_M -#define AES_ALGSEL_KEY_STORE CRYPTO_ALGSEL_KEY_STORE_M -#define AES_ALGSEL_TAG CRYPTO_ALGSEL_TAG_M - +#define AES_ALGSEL_AES CRYPTO_ALGSEL_AES_M +#define AES_ALGSEL_KEY_STORE CRYPTO_ALGSEL_KEY_STORE_M +#define AES_ALGSEL_TAG CRYPTO_ALGSEL_TAG_M //***************************************************************************** // @@ -153,24 +149,24 @@ extern "C" // may be odd. Do not attempt to write a 256-bit key to AES_KEY_AREA_7. // //***************************************************************************** -#define AES_KEY_AREA_0 0 -#define AES_KEY_AREA_1 1 -#define AES_KEY_AREA_2 2 -#define AES_KEY_AREA_3 3 -#define AES_KEY_AREA_4 4 -#define AES_KEY_AREA_5 5 -#define AES_KEY_AREA_6 6 -#define AES_KEY_AREA_7 7 +#define AES_KEY_AREA_0 0 +#define AES_KEY_AREA_1 1 +#define AES_KEY_AREA_2 2 +#define AES_KEY_AREA_3 3 +#define AES_KEY_AREA_4 4 +#define AES_KEY_AREA_5 5 +#define AES_KEY_AREA_6 6 +#define AES_KEY_AREA_7 7 //***************************************************************************** // // Defines for the AES-CTR mode counter width // //***************************************************************************** -#define AES_CTR_WIDTH_32 0x0 -#define AES_CTR_WIDTH_64 0x1 -#define AES_CTR_WIDTH_96 0x2 -#define AES_CTR_WIDTH_128 0x3 +#define AES_CTR_WIDTH_32 0x0 +#define AES_CTR_WIDTH_64 0x1 +#define AES_CTR_WIDTH_96 0x2 +#define AES_CTR_WIDTH_128 0x3 //***************************************************************************** // @@ -213,7 +209,7 @@ extern "C" //! \return None // //***************************************************************************** -extern void AESStartDMAOperation(const uint8_t* channel0Addr, uint32_t channel0Length, uint8_t* channel1Addr, uint32_t channel1Length); +extern void AESStartDMAOperation(const uint8_t* channel0Addr, uint32_t channel0Length, uint8_t* channel1Addr, uint32_t channel1Length); //***************************************************************************** // @@ -406,7 +402,6 @@ extern uint32_t AESWriteToKeyStore(const uint8_t* aesKey, uint32_t aesKeyLength, //***************************************************************************** extern uint32_t AESReadFromKeyStore(uint32_t keyStoreArea); - //***************************************************************************** // //! \brief Poll the interrupt status register and clear when done. @@ -786,40 +781,40 @@ __STATIC_INLINE void AESIntUnregister(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AESStartDMAOperation -#undef AESStartDMAOperation -#define AESStartDMAOperation ROM_AESStartDMAOperation +#undef AESStartDMAOperation +#define AESStartDMAOperation ROM_AESStartDMAOperation #endif #ifdef ROM_AESSetInitializationVector -#undef AESSetInitializationVector -#define AESSetInitializationVector ROM_AESSetInitializationVector +#undef AESSetInitializationVector +#define AESSetInitializationVector ROM_AESSetInitializationVector #endif #ifdef ROM_AESWriteCCMInitializationVector -#undef AESWriteCCMInitializationVector +#undef AESWriteCCMInitializationVector #define AESWriteCCMInitializationVector ROM_AESWriteCCMInitializationVector #endif #ifdef ROM_AESReadTag -#undef AESReadTag -#define AESReadTag ROM_AESReadTag +#undef AESReadTag +#define AESReadTag ROM_AESReadTag #endif #ifdef ROM_AESVerifyTag -#undef AESVerifyTag -#define AESVerifyTag ROM_AESVerifyTag +#undef AESVerifyTag +#define AESVerifyTag ROM_AESVerifyTag #endif #ifdef ROM_AESWriteToKeyStore -#undef AESWriteToKeyStore -#define AESWriteToKeyStore ROM_AESWriteToKeyStore +#undef AESWriteToKeyStore +#define AESWriteToKeyStore ROM_AESWriteToKeyStore #endif #ifdef ROM_AESReadFromKeyStore -#undef AESReadFromKeyStore -#define AESReadFromKeyStore ROM_AESReadFromKeyStore +#undef AESReadFromKeyStore +#define AESReadFromKeyStore ROM_AESReadFromKeyStore #endif #ifdef ROM_AESWaitForIRQFlags -#undef AESWaitForIRQFlags -#define AESWaitForIRQFlags ROM_AESWaitForIRQFlags +#undef AESWaitForIRQFlags +#define AESWaitForIRQFlags ROM_AESWaitForIRQFlags #endif #ifdef ROM_AESConfigureCCMCtrl -#undef AESConfigureCCMCtrl -#define AESConfigureCCMCtrl ROM_AESConfigureCCMCtrl +#undef AESConfigureCCMCtrl +#define AESConfigureCCMCtrl ROM_AESConfigureCCMCtrl #endif #endif @@ -832,7 +827,7 @@ __STATIC_INLINE void AESIntUnregister(void) } #endif -#endif // __AES_H__ +#endif // __AES_H__ //***************************************************************************** // diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aes_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aes_doc.h index 5d94afa..baa550f 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aes_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aes_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: aes_doc.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aes_doc.h + * Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) + * Revision: 49096 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup aes_api //! @{ //! \section sec_aes Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.h index 0a186b6..dc8e0a4 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.h @@ -1,41 +1,41 @@ /****************************************************************************** -* Filename: aon_batmon.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the AON Battery and Temperature -* Monitor -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_batmon.h + * Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) + * Revision: 47343 + * + * Description: Defines and prototypes for the AON Battery and Temperature + * Monitor + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -56,16 +56,15 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aon_batmon.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aon_batmon.h" -#include "debug.h" //***************************************************************************** // @@ -81,10 +80,9 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC +#define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC #endif - //***************************************************************************** // // API Functions and prototypes @@ -145,7 +143,6 @@ AONBatMonDisable(void) HWREG(AON_BATMON_BASE + AON_BATMON_O_CTL) = 0; } - //***************************************************************************** // //! \brief Get the current temperature measurement as a signed value in Deg Celsius. @@ -163,7 +160,7 @@ AONBatMonDisable(void) //! \sa AONBatMonNewTempMeasureReady() // //***************************************************************************** -extern int32_t AONBatMonTemperatureGetDegC( void ); +extern int32_t AONBatMonTemperatureGetDegC(void); //***************************************************************************** // @@ -221,7 +218,9 @@ AONBatMonNewBatteryMeasureReady(void) // Check the status bit. bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_BATUPD) & - AON_BATMON_BATUPD_STAT ? true : false; + AON_BATMON_BATUPD_STAT + ? true + : false; // Clear status bit if set. if (bStatus) @@ -260,7 +259,9 @@ AONBatMonNewTempMeasureReady(void) // Check the status bit. bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_TEMPUPD) & - AON_BATMON_TEMPUPD_STAT ? true : false; + AON_BATMON_TEMPUPD_STAT + ? true + : false; // Clear status bit if set. if (bStatus) @@ -281,8 +282,8 @@ AONBatMonNewTempMeasureReady(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AONBatMonTemperatureGetDegC -#undef AONBatMonTemperatureGetDegC -#define AONBatMonTemperatureGetDegC ROM_AONBatMonTemperatureGetDegC +#undef AONBatMonTemperatureGetDegC +#define AONBatMonTemperatureGetDegC ROM_AONBatMonTemperatureGetDegC #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.h index 54f50e6..ea40698 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aon_event.h -* Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017) -* Revision: 49506 -* -* Description: Defines and prototypes for the AON Event fabric. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_event.h + * Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017) + * Revision: 49506 + * + * Description: Defines and prototypes for the AON Event fabric. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,16 +55,15 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aon_event.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aon_event.h" -#include "debug.h" //***************************************************************************** // @@ -80,10 +79,10 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet -#define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet -#define AONEventMcuSet NOROM_AONEventMcuSet -#define AONEventMcuGet NOROM_AONEventMcuGet +#define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet +#define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet +#define AONEventMcuSet NOROM_AONEventMcuSet +#define AONEventMcuGet NOROM_AONEventMcuGet #endif //***************************************************************************** @@ -92,46 +91,46 @@ extern "C" // Note: Events are level-triggered active high // //***************************************************************************** -#define AON_EVENT_IOEV_MCU_WU 0 // Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU -#define AON_EVENT_AUX_TIMER2_EV0 1 // Event 0 from AUX Timer2 -#define AON_EVENT_AUX_TIMER2_EV1 2 // Event 1 from AUX Timer2 -#define AON_EVENT_AUX_TIMER2_EV2 3 // Event 2 from AUX Timer2 -#define AON_EVENT_AUX_TIMER2_EV3 4 // Event 3 from AUX Timer2 -#define AON_EVENT_BATMON_BATT_UL 5 // BATMON event: Battery level above upper limit -#define AON_EVENT_BATMON_BATT_LL 6 // BATMON event: Battery level below lower limit -#define AON_EVENT_BATMON_TEMP_UL 7 // BATMON event: Temperature level above upper limit -#define AON_EVENT_BATMON_TEMP_LL 8 // BATMON event: Temperature level below lower limit -#define AON_EVENT_BATMON_COMBINED 9 // Combined event from BATMON -#define AON_EVENT_IO 32 // Edge detect on any DIO. Edge detect is enabled and configured in IOC. +#define AON_EVENT_IOEV_MCU_WU 0 // Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU +#define AON_EVENT_AUX_TIMER2_EV0 1 // Event 0 from AUX Timer2 +#define AON_EVENT_AUX_TIMER2_EV1 2 // Event 1 from AUX Timer2 +#define AON_EVENT_AUX_TIMER2_EV2 3 // Event 2 from AUX Timer2 +#define AON_EVENT_AUX_TIMER2_EV3 4 // Event 3 from AUX Timer2 +#define AON_EVENT_BATMON_BATT_UL 5 // BATMON event: Battery level above upper limit +#define AON_EVENT_BATMON_BATT_LL 6 // BATMON event: Battery level below lower limit +#define AON_EVENT_BATMON_TEMP_UL 7 // BATMON event: Temperature level above upper limit +#define AON_EVENT_BATMON_TEMP_LL 8 // BATMON event: Temperature level below lower limit +#define AON_EVENT_BATMON_COMBINED 9 // Combined event from BATMON +#define AON_EVENT_IO 32 // Edge detect on any DIO. Edge detect is enabled and configured in IOC. // Event ID 33 is reserved for future use // Event ID 34 is reserved for future use -#define AON_EVENT_RTC_CH0 35 // RTC channel 0 -#define AON_EVENT_RTC_CH1 36 // RTC channel 1 -#define AON_EVENT_RTC_CH2 37 // RTC channel 2 -#define AON_EVENT_RTC_CH0_DLY 38 // RTC channel 0 - delayed event -#define AON_EVENT_RTC_CH1_DLY 39 // RTC channel 1 - delayed event -#define AON_EVENT_RTC_CH2_DLY 40 // RTC channel 2 - delayed event -#define AON_EVENT_RTC_COMB_DLY 41 // RTC combined delayed event -#define AON_EVENT_RTC_UPD 42 // RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) -#define AON_EVENT_JTAG 43 // JTAG generated event -#define AON_EVENT_AUX_SWEV0 44 // AUX Software triggered event #0 -#define AON_EVENT_AUX_SWEV1 45 // AUX Software triggered event #1 -#define AON_EVENT_AUX_SWEV2 46 // AUX Software triggered event #2 -#define AON_EVENT_AUX_COMPA 47 // Comparator A triggered (synchronized in AUX) -#define AON_EVENT_AUX_COMPB 48 // Comparator B triggered (synchronized in AUX) -#define AON_EVENT_AUX_ADC_DONE 49 // ADC conversion completed -#define AON_EVENT_AUX_TDC_DONE 50 // TDC completed or timed out -#define AON_EVENT_AUX_TIMER0_EV 51 // Timer 0 event -#define AON_EVENT_AUX_TIMER1_EV 52 // Timer 1 event -#define AON_EVENT_BATMON_TEMP 53 // BATMON temperature update event -#define AON_EVENT_BATMON_VOLT 54 // BATMON voltage update event -#define AON_EVENT_AUX_COMPB_ASYNC 55 // Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +#define AON_EVENT_RTC_CH0 35 // RTC channel 0 +#define AON_EVENT_RTC_CH1 36 // RTC channel 1 +#define AON_EVENT_RTC_CH2 37 // RTC channel 2 +#define AON_EVENT_RTC_CH0_DLY 38 // RTC channel 0 - delayed event +#define AON_EVENT_RTC_CH1_DLY 39 // RTC channel 1 - delayed event +#define AON_EVENT_RTC_CH2_DLY 40 // RTC channel 2 - delayed event +#define AON_EVENT_RTC_COMB_DLY 41 // RTC combined delayed event +#define AON_EVENT_RTC_UPD 42 // RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +#define AON_EVENT_JTAG 43 // JTAG generated event +#define AON_EVENT_AUX_SWEV0 44 // AUX Software triggered event #0 +#define AON_EVENT_AUX_SWEV1 45 // AUX Software triggered event #1 +#define AON_EVENT_AUX_SWEV2 46 // AUX Software triggered event #2 +#define AON_EVENT_AUX_COMPA 47 // Comparator A triggered (synchronized in AUX) +#define AON_EVENT_AUX_COMPB 48 // Comparator B triggered (synchronized in AUX) +#define AON_EVENT_AUX_ADC_DONE 49 // ADC conversion completed +#define AON_EVENT_AUX_TDC_DONE 50 // TDC completed or timed out +#define AON_EVENT_AUX_TIMER0_EV 51 // Timer 0 event +#define AON_EVENT_AUX_TIMER1_EV 52 // Timer 1 event +#define AON_EVENT_BATMON_TEMP 53 // BATMON temperature update event +#define AON_EVENT_BATMON_VOLT 54 // BATMON voltage update event +#define AON_EVENT_AUX_COMPB_ASYNC 55 // Comparator B triggered. Asynchronous signal directly from the AUX Comparator B #define AON_EVENT_AUX_COMPB_ASYNC_N 56 // Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B // Event ID 57-62 is reserved for future use -#define AON_EVENT_NONE 63 // No event, always low +#define AON_EVENT_NONE 63 // No event, always low // Keeping backward compatibility until major revision number is incremented -#define AON_EVENT_RTC0 ( AON_EVENT_RTC_CH0 ) +#define AON_EVENT_RTC0 (AON_EVENT_RTC_CH0) //***************************************************************************** // @@ -139,23 +138,23 @@ extern "C" // by AONEventMCUWakeUpGet(). // //***************************************************************************** -#define AON_EVENT_MCU_WU0 0 // Programmable MCU wake-up event 0 -#define AON_EVENT_MCU_WU1 1 // Programmable MCU wake-up event 1 -#define AON_EVENT_MCU_WU2 2 // Programmable MCU wake-up event 2 -#define AON_EVENT_MCU_WU3 3 // Programmable MCU wake-up event 3 -#define AON_EVENT_MCU_WU4 4 // Programmable MCU wake-up event 4 -#define AON_EVENT_MCU_WU5 5 // Programmable MCU wake-up event 5 -#define AON_EVENT_MCU_WU6 6 // Programmable MCU wake-up event 6 -#define AON_EVENT_MCU_WU7 7 // Programmable MCU wake-up event 7 +#define AON_EVENT_MCU_WU0 0 // Programmable MCU wake-up event 0 +#define AON_EVENT_MCU_WU1 1 // Programmable MCU wake-up event 1 +#define AON_EVENT_MCU_WU2 2 // Programmable MCU wake-up event 2 +#define AON_EVENT_MCU_WU3 3 // Programmable MCU wake-up event 3 +#define AON_EVENT_MCU_WU4 4 // Programmable MCU wake-up event 4 +#define AON_EVENT_MCU_WU5 5 // Programmable MCU wake-up event 5 +#define AON_EVENT_MCU_WU6 6 // Programmable MCU wake-up event 6 +#define AON_EVENT_MCU_WU7 7 // Programmable MCU wake-up event 7 //***************************************************************************** // // Values that can be passed to AONEventMcuSet() and AONEventMcuGet() // //***************************************************************************** -#define AON_EVENT_MCU_EVENT0 0 // Programmable event source fed to MCU event fabric (first of 3) -#define AON_EVENT_MCU_EVENT1 1 // Programmable event source fed to MCU event fabric (second of 3) -#define AON_EVENT_MCU_EVENT2 2 // Programmable event source fed to MCU event fabric (third of 3) +#define AON_EVENT_MCU_EVENT0 0 // Programmable event source fed to MCU event fabric (first of 3) +#define AON_EVENT_MCU_EVENT1 1 // Programmable event source fed to MCU event fabric (second of 3) +#define AON_EVENT_MCU_EVENT2 2 // Programmable event source fed to MCU event fabric (third of 3) //***************************************************************************** // @@ -527,20 +526,20 @@ AONEventRtcGet(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AONEventMcuWakeUpSet -#undef AONEventMcuWakeUpSet -#define AONEventMcuWakeUpSet ROM_AONEventMcuWakeUpSet +#undef AONEventMcuWakeUpSet +#define AONEventMcuWakeUpSet ROM_AONEventMcuWakeUpSet #endif #ifdef ROM_AONEventMcuWakeUpGet -#undef AONEventMcuWakeUpGet -#define AONEventMcuWakeUpGet ROM_AONEventMcuWakeUpGet +#undef AONEventMcuWakeUpGet +#define AONEventMcuWakeUpGet ROM_AONEventMcuWakeUpGet #endif #ifdef ROM_AONEventMcuSet -#undef AONEventMcuSet -#define AONEventMcuSet ROM_AONEventMcuSet +#undef AONEventMcuSet +#define AONEventMcuSet ROM_AONEventMcuSet #endif #ifdef ROM_AONEventMcuGet -#undef AONEventMcuGet -#define AONEventMcuGet ROM_AONEventMcuGet +#undef AONEventMcuGet +#define AONEventMcuGet ROM_AONEventMcuGet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event_doc.h index 75a8b0a..e2425bd 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: aon_event_doc.h -* Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017) -* Revision: 49506 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_event_doc.h + * Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017) + * Revision: 49506 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup aonevent_api //! @{ //! \section sec_aonevent Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.h index f60cb03..baffd83 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aon_ioc.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the AON IO Controller -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_ioc.h + * Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) + * Revision: 47343 + * + * Description: Defines and prototypes for the AON IO Controller + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,34 +55,33 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aon_ioc.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aon_ioc.h" -#include "debug.h" //***************************************************************************** // // Defines for the drive strength // //***************************************************************************** -#define AONIOC_DRV_STR_1 0x00000000 // Lowest drive strength -#define AONIOC_DRV_STR_2 0x00000001 -#define AONIOC_DRV_STR_3 0x00000003 -#define AONIOC_DRV_STR_4 0x00000002 -#define AONIOC_DRV_STR_5 0x00000006 -#define AONIOC_DRV_STR_6 0x00000007 -#define AONIOC_DRV_STR_7 0x00000005 -#define AONIOC_DRV_STR_8 0x00000004 // Highest drive strength +#define AONIOC_DRV_STR_1 0x00000000 // Lowest drive strength +#define AONIOC_DRV_STR_2 0x00000001 +#define AONIOC_DRV_STR_3 0x00000003 +#define AONIOC_DRV_STR_4 0x00000002 +#define AONIOC_DRV_STR_5 0x00000006 +#define AONIOC_DRV_STR_6 0x00000007 +#define AONIOC_DRV_STR_7 0x00000005 +#define AONIOC_DRV_STR_8 0x00000004 // Highest drive strength -#define AONIOC_DRV_LVL_MIN (AON_IOC_O_IOSTRMIN) -#define AONIOC_DRV_LVL_MED (AON_IOC_O_IOSTRMED) -#define AONIOC_DRV_LVL_MAX (AON_IOC_O_IOSTRMAX) +#define AONIOC_DRV_LVL_MIN (AON_IOC_O_IOSTRMIN) +#define AONIOC_DRV_LVL_MED (AON_IOC_O_IOSTRMED) +#define AONIOC_DRV_LVL_MAX (AON_IOC_O_IOSTRMAX) //***************************************************************************** // @@ -186,7 +185,7 @@ AONIOCDriveStrengthGet(uint32_t ui32DriveLevel) (ui32DriveLevel == AONIOC_DRV_LVL_MAX)); // Return the drive strength value. - return ( HWREG(AON_IOC_BASE + ui32DriveLevel) ); + return (HWREG(AON_IOC_BASE + ui32DriveLevel)); } //***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc_doc.h index 7fe0e93..e90c20c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: aon_ioc_doc.h -* Revised: 2016-03-30 11:01:30 +0200 (Wed, 30 Mar 2016) -* Revision: 45969 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_ioc_doc.h + * Revised: 2016-03-30 11:01:30 +0200 (Wed, 30 Mar 2016) + * Revision: 45969 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup aonioc_api //! @{ //! \section sec_aonioc Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.h index fef39d6..d429575 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aon_pmctl.h -* Revised: 2017-11-02 14:16:14 +0100 (Thu, 02 Nov 2017) -* Revision: 50156 -* -* Description: Defines and prototypes for the AON Power-Management Controller -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_pmctl.h + * Revised: 2017-11-02 14:16:14 +0100 (Thu, 02 Nov 2017) + * Revision: 50156 + * + * Description: Defines and prototypes for the AON Power-Management Controller + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,16 +55,15 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aon_pmctl.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aon_pmctl.h" -#include "debug.h" //***************************************************************************** // @@ -73,11 +72,11 @@ extern "C" // AONPMCTLMcuSRamConfig) . // //***************************************************************************** -#define MCU_RAM_RET_NONE AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_NONE -#define MCU_RAM_RET_LVL1 AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL1 -#define MCU_RAM_RET_LVL2 AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL2 -#define MCU_RAM_RET_LVL3 AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL3 -#define MCU_RAM_RET_FULL AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_FULL +#define MCU_RAM_RET_NONE AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_NONE +#define MCU_RAM_RET_LVL1 AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL1 +#define MCU_RAM_RET_LVL2 AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL2 +#define MCU_RAM_RET_LVL3 AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL3 +#define MCU_RAM_RET_FULL AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_FULL //***************************************************************************** // @@ -85,7 +84,7 @@ extern "C" // AONPMCTLPowerStatusGet() . // //***************************************************************************** -#define AONPMCTL_JTAG_POWER_ON AON_PMCTL_PWRSTAT_JTAG_PD_ON +#define AONPMCTL_JTAG_POWER_ON AON_PMCTL_PWRSTAT_JTAG_PD_ON //***************************************************************************** // @@ -157,7 +156,6 @@ AONPMCTLPowerStatusGet(void) return (HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRSTAT)); } - //***************************************************************************** // //! \brief Request power off of the JTAG domain. @@ -180,7 +178,6 @@ AONPMCTLJtagPowerOff(void) HWREG(AON_PMCTL_BASE + AON_PMCTL_O_JTAGCFG) = 0; } - //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl_doc.h index 60dec60..2346be2 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: aon_pmctl_doc.h -* Revised: 2017-11-02 15:41:14 +0100 (Thu, 02 Nov 2017) -* Revision: 50165 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_pmctl_doc.h + * Revised: 2017-11-02 15:41:14 +0100 (Thu, 02 Nov 2017) + * Revision: 50165 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup aonpmctl_api //! @{ //! \section sec_aonpmctl Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.h index 58cd097..246e59e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aon_rtc.h -* Revised: 2017-08-16 15:13:43 +0200 (Wed, 16 Aug 2017) -* Revision: 49593 -* -* Description: Defines and prototypes for the AON RTC -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_rtc.h + * Revised: 2017-08-16 15:13:43 +0200 (Wed, 16 Aug 2017) + * Revision: 49593 + * + * Description: Defines and prototypes for the AON RTC + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,16 +55,15 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aon_rtc.h" -#include "debug.h" //***************************************************************************** // @@ -80,7 +79,7 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet +#define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet #endif //***************************************************************************** @@ -89,11 +88,11 @@ extern "C" // parameter. // //***************************************************************************** -#define AON_RTC_CH_NONE 0x0 // RTC No channel -#define AON_RTC_CH0 0x1 // RTC Channel 0 -#define AON_RTC_CH1 0x2 // RTC Channel 1 -#define AON_RTC_CH2 0x4 // RTC Channel 2 -#define AON_RTC_ACTIVE 0x8 // RTC Active +#define AON_RTC_CH_NONE 0x0 // RTC No channel +#define AON_RTC_CH0 0x1 // RTC Channel 0 +#define AON_RTC_CH1 0x2 // RTC Channel 1 +#define AON_RTC_CH2 0x4 // RTC Channel 2 +#define AON_RTC_ACTIVE 0x8 // RTC Active //***************************************************************************** // @@ -101,19 +100,19 @@ extern "C" // //***************************************************************************** #define AON_RTC_CONFIG_DELAY_NODELAY 0 // NO DELAY -#define AON_RTC_CONFIG_DELAY_1 1 // Delay of 1 clk cycle -#define AON_RTC_CONFIG_DELAY_2 2 // Delay of 2 clk cycles -#define AON_RTC_CONFIG_DELAY_4 3 // Delay of 4 clk cycles -#define AON_RTC_CONFIG_DELAY_8 4 // Delay of 8 clk cycles -#define AON_RTC_CONFIG_DELAY_16 5 // Delay of 16 clk cycles -#define AON_RTC_CONFIG_DELAY_32 6 // Delay of 32 clk cycles -#define AON_RTC_CONFIG_DELAY_48 7 // Delay of 48 clk cycles -#define AON_RTC_CONFIG_DELAY_64 8 // Delay of 64 clk cycles -#define AON_RTC_CONFIG_DELAY_80 9 // Delay of 80 clk cycles -#define AON_RTC_CONFIG_DELAY_96 10 // Delay of 96 clk cycles -#define AON_RTC_CONFIG_DELAY_112 11 // Delay of 112 clk cycles -#define AON_RTC_CONFIG_DELAY_128 12 // Delay of 128 clk cycles -#define AON_RTC_CONFIG_DELAY_144 13 // Delay of 144 clk cycles +#define AON_RTC_CONFIG_DELAY_1 1 // Delay of 1 clk cycle +#define AON_RTC_CONFIG_DELAY_2 2 // Delay of 2 clk cycles +#define AON_RTC_CONFIG_DELAY_4 3 // Delay of 4 clk cycles +#define AON_RTC_CONFIG_DELAY_8 4 // Delay of 8 clk cycles +#define AON_RTC_CONFIG_DELAY_16 5 // Delay of 16 clk cycles +#define AON_RTC_CONFIG_DELAY_32 6 // Delay of 32 clk cycles +#define AON_RTC_CONFIG_DELAY_48 7 // Delay of 48 clk cycles +#define AON_RTC_CONFIG_DELAY_64 8 // Delay of 64 clk cycles +#define AON_RTC_CONFIG_DELAY_80 9 // Delay of 80 clk cycles +#define AON_RTC_CONFIG_DELAY_96 10 // Delay of 96 clk cycles +#define AON_RTC_CONFIG_DELAY_112 11 // Delay of 112 clk cycles +#define AON_RTC_CONFIG_DELAY_128 12 // Delay of 128 clk cycles +#define AON_RTC_CONFIG_DELAY_144 13 // Delay of 144 clk cycles //***************************************************************************** // @@ -121,8 +120,8 @@ extern "C" // parameter. // //***************************************************************************** -#define AON_RTC_MODE_CH1_CAPTURE 1 // Capture mode -#define AON_RTC_MODE_CH1_COMPARE 0 // Compare Mode +#define AON_RTC_MODE_CH1_CAPTURE 1 // Capture mode +#define AON_RTC_MODE_CH1_COMPARE 0 // Compare Mode //***************************************************************************** // @@ -130,7 +129,7 @@ extern "C" // parameter. // //***************************************************************************** -#define AON_RTC_MODE_CH2_CONTINUOUS 1 // Continuous mode +#define AON_RTC_MODE_CH2_CONTINUOUS 1 // Continuous mode #define AON_RTC_MODE_CH2_NORMALCOMPARE 0 // Normal compare mode //***************************************************************************** @@ -147,7 +146,7 @@ extern "C" // ( 4 * FACTOR_SEC_TO_COMP_VAL_FORMAT ) // //***************************************************************************** -#define FACTOR_SEC_TO_COMP_VAL_FORMAT 0x00010000 +#define FACTOR_SEC_TO_COMP_VAL_FORMAT 0x00010000 //***************************************************************************** // @@ -305,8 +304,7 @@ AONRTCDelayConfig(uint32_t ui32Delay) // Check the arguments. ASSERT(ui32Delay <= AON_RTC_CONFIG_DELAY_144); - - ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); + ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); ui32Cfg &= ~(AON_RTC_CTL_EV_DELAY_M); ui32Cfg |= (ui32Delay << AON_RTC_CTL_EV_DELAY_S); @@ -338,10 +336,10 @@ AONRTCCombinedEventConfig(uint32_t ui32Channels) uint32_t ui32Cfg; // Check the arguments. - ASSERT( (ui32Channels & (AON_RTC_CH0 | AON_RTC_CH1 | AON_RTC_CH2)) || - (ui32Channels == AON_RTC_CH_NONE) ); + ASSERT((ui32Channels & (AON_RTC_CH0 | AON_RTC_CH1 | AON_RTC_CH2)) || + (ui32Channels == AON_RTC_CH_NONE)); - ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); + ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); ui32Cfg &= ~(AON_RTC_CTL_COMB_EV_MASK_M); ui32Cfg |= (ui32Channels << AON_RTC_CTL_COMB_EV_MASK_S); @@ -816,9 +814,9 @@ AONRTCCompareValueGet(uint32_t ui32Channel) // //***************************************************************************** __STATIC_INLINE uint32_t -AONRTCCurrentCompareValueGet( void ) +AONRTCCurrentCompareValueGet(void) { - return ( HWREG( AON_RTC_BASE + AON_RTC_O_TIME )); + return (HWREG(AON_RTC_BASE + AON_RTC_O_TIME)); } //***************************************************************************** @@ -906,8 +904,8 @@ AONRTCCaptureValueCh1Get(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AONRTCCurrent64BitValueGet -#undef AONRTCCurrent64BitValueGet -#define AONRTCCurrent64BitValueGet ROM_AONRTCCurrent64BitValueGet +#undef AONRTCCurrent64BitValueGet +#define AONRTCCurrent64BitValueGet ROM_AONRTCCurrent64BitValueGet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc_doc.h index b3c142b..35dd310 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: aon_rtc_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_rtc_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup aonrtc_api //! @{ //! \section sec_aonrtc Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.h index 378db15..152c466 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.h @@ -1,41 +1,41 @@ /****************************************************************************** -* Filename: aux_adc.h -* Revised: 2018-02-07 09:45:39 +0100 (Wed, 07 Feb 2018) -* Revision: 51437 -* -* Description: Defines and prototypes for the AUX Analog-to-Digital -* Converter -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aux_adc.h + * Revised: 2018-02-07 09:45:39 +0100 (Wed, 07 Feb 2018) + * Revision: 51437 + * + * Description: Defines and prototypes for the AUX Analog-to-Digital + * Converter + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -56,19 +56,18 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_event.h" #include "../inc/hw_adi.h" #include "../inc/hw_adi_4_aux.h" #include "../inc/hw_aux_anaif.h" +#include "../inc/hw_event.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "rom.h" +#include +#include //***************************************************************************** // @@ -84,17 +83,17 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AUXADCDisable NOROM_AUXADCDisable -#define AUXADCEnableAsync NOROM_AUXADCEnableAsync -#define AUXADCEnableSync NOROM_AUXADCEnableSync -#define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling -#define AUXADCFlushFifo NOROM_AUXADCFlushFifo -#define AUXADCReadFifo NOROM_AUXADCReadFifo -#define AUXADCPopFifo NOROM_AUXADCPopFifo -#define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain -#define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset -#define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts -#define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue +#define AUXADCDisable NOROM_AUXADCDisable +#define AUXADCEnableAsync NOROM_AUXADCEnableAsync +#define AUXADCEnableSync NOROM_AUXADCEnableSync +#define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling +#define AUXADCFlushFifo NOROM_AUXADCFlushFifo +#define AUXADCReadFifo NOROM_AUXADCReadFifo +#define AUXADCPopFifo NOROM_AUXADCPopFifo +#define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain +#define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset +#define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts +#define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue #define AUXADCAdjustValueForGainAndOffset NOROM_AUXADCAdjustValueForGainAndOffset #define AUXADCUnadjustValueForGainAndOffset NOROM_AUXADCUnadjustValueForGainAndOffset #endif @@ -104,71 +103,70 @@ extern "C" // Defines for ADC reference sources. // //***************************************************************************** -#define AUXADC_REF_FIXED (0 << ADI_4_AUX_ADCREF0_SRC_S) -#define AUXADC_REF_VDDS_REL (1 << ADI_4_AUX_ADCREF0_SRC_S) +#define AUXADC_REF_FIXED (0 << ADI_4_AUX_ADCREF0_SRC_S) +#define AUXADC_REF_VDDS_REL (1 << ADI_4_AUX_ADCREF0_SRC_S) //***************************************************************************** // // Defines for the ADC FIFO status bits. // //***************************************************************************** -#define AUXADC_FIFO_EMPTY_M (AUX_ANAIF_ADCFIFOSTAT_EMPTY_M) -#define AUXADC_FIFO_ALMOST_FULL_M (AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M) -#define AUXADC_FIFO_FULL_M (AUX_ANAIF_ADCFIFOSTAT_FULL_M) -#define AUXADC_FIFO_UNDERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M) -#define AUXADC_FIFO_OVERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M) +#define AUXADC_FIFO_EMPTY_M (AUX_ANAIF_ADCFIFOSTAT_EMPTY_M) +#define AUXADC_FIFO_ALMOST_FULL_M (AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M) +#define AUXADC_FIFO_FULL_M (AUX_ANAIF_ADCFIFOSTAT_FULL_M) +#define AUXADC_FIFO_UNDERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M) +#define AUXADC_FIFO_OVERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M) //***************************************************************************** // // Defines for supported ADC triggers. // //***************************************************************************** -#define AUXADC_TRIGGER_MANUAL (EVENT_AUXSEL0_EV_NONE) -#define AUXADC_TRIGGER_GPT0A (EVENT_AUXSEL0_EV_GPT0A) -#define AUXADC_TRIGGER_GPT0B (EVENT_AUXSEL0_EV_GPT0B) -#define AUXADC_TRIGGER_GPT1A (EVENT_AUXSEL0_EV_GPT1A) -#define AUXADC_TRIGGER_GPT1B (EVENT_AUXSEL0_EV_GPT1B) -#define AUXADC_TRIGGER_GPT2A (EVENT_AUXSEL0_EV_GPT2A) -#define AUXADC_TRIGGER_GPT2B (EVENT_AUXSEL0_EV_GPT2B) -#define AUXADC_TRIGGER_GPT3A (EVENT_AUXSEL0_EV_GPT3A) -#define AUXADC_TRIGGER_GPT3B (EVENT_AUXSEL0_EV_GPT3B) +#define AUXADC_TRIGGER_MANUAL (EVENT_AUXSEL0_EV_NONE) +#define AUXADC_TRIGGER_GPT0A (EVENT_AUXSEL0_EV_GPT0A) +#define AUXADC_TRIGGER_GPT0B (EVENT_AUXSEL0_EV_GPT0B) +#define AUXADC_TRIGGER_GPT1A (EVENT_AUXSEL0_EV_GPT1A) +#define AUXADC_TRIGGER_GPT1B (EVENT_AUXSEL0_EV_GPT1B) +#define AUXADC_TRIGGER_GPT2A (EVENT_AUXSEL0_EV_GPT2A) +#define AUXADC_TRIGGER_GPT2B (EVENT_AUXSEL0_EV_GPT2B) +#define AUXADC_TRIGGER_GPT3A (EVENT_AUXSEL0_EV_GPT3A) +#define AUXADC_TRIGGER_GPT3B (EVENT_AUXSEL0_EV_GPT3B) // Additional triggers specific for cc26x2 and cc13x2 devices -#define AUXADC_TRIGGER_GPT0A_CMP (EVENT_AUXSEL0_EV_GPT0A_CMP) -#define AUXADC_TRIGGER_GPT0B_CMP (EVENT_AUXSEL0_EV_GPT0B_CMP) -#define AUXADC_TRIGGER_GPT1A_CMP (EVENT_AUXSEL0_EV_GPT1A_CMP) -#define AUXADC_TRIGGER_GPT1B_CMP (EVENT_AUXSEL0_EV_GPT1B_CMP) -#define AUXADC_TRIGGER_GPT2A_CMP (EVENT_AUXSEL0_EV_GPT2A_CMP) -#define AUXADC_TRIGGER_GPT2B_CMP (EVENT_AUXSEL0_EV_GPT2B_CMP) -#define AUXADC_TRIGGER_GPT3A_CMP (EVENT_AUXSEL0_EV_GPT3A_CMP) -#define AUXADC_TRIGGER_GPT3B_CMP (EVENT_AUXSEL0_EV_GPT3B_CMP) +#define AUXADC_TRIGGER_GPT0A_CMP (EVENT_AUXSEL0_EV_GPT0A_CMP) +#define AUXADC_TRIGGER_GPT0B_CMP (EVENT_AUXSEL0_EV_GPT0B_CMP) +#define AUXADC_TRIGGER_GPT1A_CMP (EVENT_AUXSEL0_EV_GPT1A_CMP) +#define AUXADC_TRIGGER_GPT1B_CMP (EVENT_AUXSEL0_EV_GPT1B_CMP) +#define AUXADC_TRIGGER_GPT2A_CMP (EVENT_AUXSEL0_EV_GPT2A_CMP) +#define AUXADC_TRIGGER_GPT2B_CMP (EVENT_AUXSEL0_EV_GPT2B_CMP) +#define AUXADC_TRIGGER_GPT3A_CMP (EVENT_AUXSEL0_EV_GPT3A_CMP) +#define AUXADC_TRIGGER_GPT3B_CMP (EVENT_AUXSEL0_EV_GPT3B_CMP) //***************************************************************************** // // Defines for ADC sampling type for synchronous operation. // //***************************************************************************** -#define AUXADC_SAMPLE_TIME_2P7_US 3 -#define AUXADC_SAMPLE_TIME_5P3_US 4 -#define AUXADC_SAMPLE_TIME_10P6_US 5 -#define AUXADC_SAMPLE_TIME_21P3_US 6 -#define AUXADC_SAMPLE_TIME_42P6_US 7 -#define AUXADC_SAMPLE_TIME_85P3_US 8 -#define AUXADC_SAMPLE_TIME_170_US 9 -#define AUXADC_SAMPLE_TIME_341_US 10 -#define AUXADC_SAMPLE_TIME_682_US 11 -#define AUXADC_SAMPLE_TIME_1P37_MS 12 -#define AUXADC_SAMPLE_TIME_2P73_MS 13 -#define AUXADC_SAMPLE_TIME_5P46_MS 14 -#define AUXADC_SAMPLE_TIME_10P9_MS 15 +#define AUXADC_SAMPLE_TIME_2P7_US 3 +#define AUXADC_SAMPLE_TIME_5P3_US 4 +#define AUXADC_SAMPLE_TIME_10P6_US 5 +#define AUXADC_SAMPLE_TIME_21P3_US 6 +#define AUXADC_SAMPLE_TIME_42P6_US 7 +#define AUXADC_SAMPLE_TIME_85P3_US 8 +#define AUXADC_SAMPLE_TIME_170_US 9 +#define AUXADC_SAMPLE_TIME_341_US 10 +#define AUXADC_SAMPLE_TIME_682_US 11 +#define AUXADC_SAMPLE_TIME_1P37_MS 12 +#define AUXADC_SAMPLE_TIME_2P73_MS 13 +#define AUXADC_SAMPLE_TIME_5P46_MS 14 +#define AUXADC_SAMPLE_TIME_10P9_MS 15 //***************************************************************************** // // Equivalent voltages for fixed ADC reference, in microvolts. // //***************************************************************************** -#define AUXADC_FIXED_REF_VOLTAGE_NORMAL 4300000 -#define AUXADC_FIXED_REF_VOLTAGE_UNSCALED 1478500 - +#define AUXADC_FIXED_REF_VOLTAGE_NORMAL 4300000 +#define AUXADC_FIXED_REF_VOLTAGE_UNSCALED 1478500 //***************************************************************************** // @@ -176,7 +174,6 @@ extern "C" // //***************************************************************************** - //***************************************************************************** // //! \brief Disables the ADC. @@ -526,55 +523,55 @@ extern int32_t AUXADCUnadjustValueForGainAndOffset(int32_t adcValue, int32_t gai #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AUXADCDisable -#undef AUXADCDisable -#define AUXADCDisable ROM_AUXADCDisable +#undef AUXADCDisable +#define AUXADCDisable ROM_AUXADCDisable #endif #ifdef ROM_AUXADCEnableAsync -#undef AUXADCEnableAsync -#define AUXADCEnableAsync ROM_AUXADCEnableAsync +#undef AUXADCEnableAsync +#define AUXADCEnableAsync ROM_AUXADCEnableAsync #endif #ifdef ROM_AUXADCEnableSync -#undef AUXADCEnableSync -#define AUXADCEnableSync ROM_AUXADCEnableSync +#undef AUXADCEnableSync +#define AUXADCEnableSync ROM_AUXADCEnableSync #endif #ifdef ROM_AUXADCDisableInputScaling -#undef AUXADCDisableInputScaling -#define AUXADCDisableInputScaling ROM_AUXADCDisableInputScaling +#undef AUXADCDisableInputScaling +#define AUXADCDisableInputScaling ROM_AUXADCDisableInputScaling #endif #ifdef ROM_AUXADCFlushFifo -#undef AUXADCFlushFifo -#define AUXADCFlushFifo ROM_AUXADCFlushFifo +#undef AUXADCFlushFifo +#define AUXADCFlushFifo ROM_AUXADCFlushFifo #endif #ifdef ROM_AUXADCReadFifo -#undef AUXADCReadFifo -#define AUXADCReadFifo ROM_AUXADCReadFifo +#undef AUXADCReadFifo +#define AUXADCReadFifo ROM_AUXADCReadFifo #endif #ifdef ROM_AUXADCPopFifo -#undef AUXADCPopFifo -#define AUXADCPopFifo ROM_AUXADCPopFifo +#undef AUXADCPopFifo +#define AUXADCPopFifo ROM_AUXADCPopFifo #endif #ifdef ROM_AUXADCGetAdjustmentGain -#undef AUXADCGetAdjustmentGain -#define AUXADCGetAdjustmentGain ROM_AUXADCGetAdjustmentGain +#undef AUXADCGetAdjustmentGain +#define AUXADCGetAdjustmentGain ROM_AUXADCGetAdjustmentGain #endif #ifdef ROM_AUXADCGetAdjustmentOffset -#undef AUXADCGetAdjustmentOffset -#define AUXADCGetAdjustmentOffset ROM_AUXADCGetAdjustmentOffset +#undef AUXADCGetAdjustmentOffset +#define AUXADCGetAdjustmentOffset ROM_AUXADCGetAdjustmentOffset #endif #ifdef ROM_AUXADCValueToMicrovolts -#undef AUXADCValueToMicrovolts -#define AUXADCValueToMicrovolts ROM_AUXADCValueToMicrovolts +#undef AUXADCValueToMicrovolts +#define AUXADCValueToMicrovolts ROM_AUXADCValueToMicrovolts #endif #ifdef ROM_AUXADCMicrovoltsToValue -#undef AUXADCMicrovoltsToValue -#define AUXADCMicrovoltsToValue ROM_AUXADCMicrovoltsToValue +#undef AUXADCMicrovoltsToValue +#define AUXADCMicrovoltsToValue ROM_AUXADCMicrovoltsToValue #endif #ifdef ROM_AUXADCAdjustValueForGainAndOffset -#undef AUXADCAdjustValueForGainAndOffset +#undef AUXADCAdjustValueForGainAndOffset #define AUXADCAdjustValueForGainAndOffset ROM_AUXADCAdjustValueForGainAndOffset #endif #ifdef ROM_AUXADCUnadjustValueForGainAndOffset -#undef AUXADCUnadjustValueForGainAndOffset +#undef AUXADCUnadjustValueForGainAndOffset #define AUXADCUnadjustValueForGainAndOffset ROM_AUXADCUnadjustValueForGainAndOffset #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.h index a83b619..d2c25b4 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aux_smph.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the AUX Semaphore -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aux_smph.h + * Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) + * Revision: 47343 + * + * Description: Defines and prototypes for the AUX Semaphore + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,24 +55,23 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" #include "../inc/hw_aux_smph.h" #include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "debug.h" +#include +#include //***************************************************************************** // // General constants and defines // //***************************************************************************** -#define AUX_SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed -#define AUX_SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed +#define AUX_SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed +#define AUX_SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed //***************************************************************************** // @@ -80,14 +79,14 @@ extern "C" // as the ui32Semaphore parameter. // //***************************************************************************** -#define AUX_SMPH_0 0 // AUX Semaphore 0 -#define AUX_SMPH_1 1 // AUX Semaphore 1 -#define AUX_SMPH_2 2 // AUX Semaphore 2 -#define AUX_SMPH_3 3 // AUX Semaphore 3 -#define AUX_SMPH_4 4 // AUX Semaphore 4 -#define AUX_SMPH_5 5 // AUX Semaphore 5 -#define AUX_SMPH_6 6 // AUX Semaphore 6 -#define AUX_SMPH_7 7 // AUX Semaphore 7 +#define AUX_SMPH_0 0 // AUX Semaphore 0 +#define AUX_SMPH_1 1 // AUX Semaphore 1 +#define AUX_SMPH_2 2 // AUX Semaphore 2 +#define AUX_SMPH_3 3 // AUX Semaphore 3 +#define AUX_SMPH_4 4 // AUX Semaphore 4 +#define AUX_SMPH_5 5 // AUX Semaphore 5 +#define AUX_SMPH_6 6 // AUX Semaphore 6 +#define AUX_SMPH_7 7 // AUX Semaphore 7 //***************************************************************************** // @@ -138,7 +137,7 @@ AUXSMPHAcquire(uint32_t ui32Semaphore) // Semaphore register reads 1 when lock was acquired otherwise 0 // (i.e. AUX_SMPH_CLAIMED). while (HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore) == - AUX_SMPH_CLAIMED) + AUX_SMPH_CLAIMED) { } } diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.h index d2b62d4..3720f1a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aux_sysif.h -* Revised: 2017-06-27 08:41:49 +0200 (Tue, 27 Jun 2017) -* Revision: 49245 -* -* Description: Defines and prototypes for the AUX System Interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aux_sysif.h + * Revised: 2017-06-27 08:41:49 +0200 (Tue, 27 Jun 2017) + * Revision: 49245 + * + * Description: Defines and prototypes for the AUX System Interface + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,16 +55,15 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aux_sysif.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aux_sysif.h" -#include "debug.h" //***************************************************************************** // @@ -80,10 +79,9 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AUXSYSIFOpModeChange NOROM_AUXSYSIFOpModeChange +#define AUXSYSIFOpModeChange NOROM_AUXSYSIFOpModeChange #endif - //***************************************************************************** // // API Functions and prototypes @@ -96,9 +94,9 @@ extern "C" // //***************************************************************************** #define AUX_SYSIF_OPMODE_TARGET_PDLP (AUX_SYSIF_OPMODEREQ_REQ_PDLP) -#define AUX_SYSIF_OPMODE_TARGET_PDA (AUX_SYSIF_OPMODEREQ_REQ_PDA) -#define AUX_SYSIF_OPMODE_TARGET_LP (AUX_SYSIF_OPMODEREQ_REQ_LP) -#define AUX_SYSIF_OPMODE_TARGET_A (AUX_SYSIF_OPMODEREQ_REQ_A) +#define AUX_SYSIF_OPMODE_TARGET_PDA (AUX_SYSIF_OPMODEREQ_REQ_PDA) +#define AUX_SYSIF_OPMODE_TARGET_LP (AUX_SYSIF_OPMODEREQ_REQ_LP) +#define AUX_SYSIF_OPMODE_TARGET_A (AUX_SYSIF_OPMODEREQ_REQ_A) //***************************************************************************** // @@ -129,8 +127,8 @@ extern void AUXSYSIFOpModeChange(uint32_t targetOpMode); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AUXSYSIFOpModeChange -#undef AUXSYSIFOpModeChange -#define AUXSYSIFOpModeChange ROM_AUXSYSIFOpModeChange +#undef AUXSYSIFOpModeChange +#define AUXSYSIFOpModeChange ROM_AUXSYSIFOpModeChange #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.h index 630b071..1ab7541 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aux_tdc.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Defines and prototypes for the AUX Time-to-Digital Converter -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aux_tdc.h + * Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) + * Revision: 49096 + * + * Description: Defines and prototypes for the AUX Time-to-Digital Converter + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,17 +55,16 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aux_tdc.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_aux_tdc.h" -#include "debug.h" //***************************************************************************** // @@ -81,8 +80,8 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AUXTDCConfigSet NOROM_AUXTDCConfigSet -#define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone +#define AUXTDCConfigSet NOROM_AUXTDCConfigSet +#define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone #endif //***************************************************************************** @@ -90,196 +89,196 @@ extern "C" // Defines for the status of a AUX TDC measurement. // //***************************************************************************** -#define AUX_TDC_BUSY 0x00000001 -#define AUX_TDC_TIMEOUT 0x00000002 -#define AUX_TDC_DONE 0x00000004 +#define AUX_TDC_BUSY 0x00000001 +#define AUX_TDC_TIMEOUT 0x00000002 +#define AUX_TDC_DONE 0x00000004 //***************************************************************************** // // Defines for the control of a AUX TDC. // //***************************************************************************** -#define AUX_TDC_RUNSYNC 0x00000001 -#define AUX_TDC_RUN 0x00000002 -#define AUX_TDC_ABORT 0x00000003 +#define AUX_TDC_RUNSYNC 0x00000001 +#define AUX_TDC_RUN 0x00000002 +#define AUX_TDC_ABORT 0x00000003 //***************************************************************************** // // Defines for possible states of the TDC internal state machine. // //***************************************************************************** -#define AUXTDC_WAIT_START (AUX_TDC_STAT_STATE_WAIT_START) -#define AUXTDC_WAIT_START_CNTEN (AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN) -#define AUXTDC_IDLE (AUX_TDC_STAT_STATE_IDLE) -#define AUXTDC_CLRCNT (AUX_TDC_STAT_STATE_CLR_CNT) -#define AUXTDC_WAIT_STOP (AUX_TDC_STAT_STATE_WAIT_STOP) -#define AUXTDC_WAIT_STOP_CNTDOWN (AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN) -#define AUXTDC_GETRESULTS (AUX_TDC_STAT_STATE_GET_RESULT) -#define AUXTDC_POR (AUX_TDC_STAT_STATE_POR) -#define AUXTDC_WAIT_CLRCNT_DONE (AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE) -#define AUXTDC_START_FALL (AUX_TDC_STAT_STATE_START_FALL) -#define AUXTDC_FORCE_STOP (AUX_TDC_STAT_STATE_FORCE_STOP) +#define AUXTDC_WAIT_START (AUX_TDC_STAT_STATE_WAIT_START) +#define AUXTDC_WAIT_START_CNTEN (AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN) +#define AUXTDC_IDLE (AUX_TDC_STAT_STATE_IDLE) +#define AUXTDC_CLRCNT (AUX_TDC_STAT_STATE_CLR_CNT) +#define AUXTDC_WAIT_STOP (AUX_TDC_STAT_STATE_WAIT_STOP) +#define AUXTDC_WAIT_STOP_CNTDOWN (AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN) +#define AUXTDC_GETRESULTS (AUX_TDC_STAT_STATE_GET_RESULT) +#define AUXTDC_POR (AUX_TDC_STAT_STATE_POR) +#define AUXTDC_WAIT_CLRCNT_DONE (AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE) +#define AUXTDC_START_FALL (AUX_TDC_STAT_STATE_START_FALL) +#define AUXTDC_FORCE_STOP (AUX_TDC_STAT_STATE_FORCE_STOP) //***************************************************************************** // // Defines for controlling the AUX TDC. Values can be passed to AUXTDCConfigSet(). // //***************************************************************************** -#define AUXTDC_STOPPOL_RIS (AUX_TDC_TRIGSRC_STOP_POL_HIGH) // Rising edge polarity for stop event -#define AUXTDC_STOPPOL_FALL (AUX_TDC_TRIGSRC_STOP_POL_LOW) // Falling edge polarity for stop event +#define AUXTDC_STOPPOL_RIS (AUX_TDC_TRIGSRC_STOP_POL_HIGH) // Rising edge polarity for stop event +#define AUXTDC_STOPPOL_FALL (AUX_TDC_TRIGSRC_STOP_POL_LOW) // Falling edge polarity for stop event -#define AUXTDC_STOP_AUXIO0 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0) -#define AUXTDC_STOP_AUXIO1 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1) -#define AUXTDC_STOP_AUXIO2 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2) -#define AUXTDC_STOP_AUXIO3 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3) -#define AUXTDC_STOP_AUXIO4 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4) -#define AUXTDC_STOP_AUXIO5 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5) -#define AUXTDC_STOP_AUXIO6 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6) -#define AUXTDC_STOP_AUXIO7 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7) -#define AUXTDC_STOP_AUXIO8 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8) -#define AUXTDC_STOP_AUXIO9 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9) -#define AUXTDC_STOP_AUXIO10 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10) -#define AUXTDC_STOP_AUXIO11 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11) -#define AUXTDC_STOP_AUXIO12 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12) -#define AUXTDC_STOP_AUXIO13 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13) -#define AUXTDC_STOP_AUXIO14 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14) -#define AUXTDC_STOP_AUXIO15 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15) -#define AUXTDC_STOP_AUXIO16 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO16) -#define AUXTDC_STOP_AUXIO17 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO17) -#define AUXTDC_STOP_AUXIO18 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO18) -#define AUXTDC_STOP_AUXIO19 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO19) -#define AUXTDC_STOP_AUXIO20 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO20) -#define AUXTDC_STOP_AUXIO21 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO21) -#define AUXTDC_STOP_AUXIO22 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO22) -#define AUXTDC_STOP_AUXIO23 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO23) -#define AUXTDC_STOP_AUXIO24 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO24) -#define AUXTDC_STOP_AUXIO25 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO25) -#define AUXTDC_STOP_AUXIO26 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO26) -#define AUXTDC_STOP_AUXIO27 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO27) -#define AUXTDC_STOP_AUXIO28 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO28) -#define AUXTDC_STOP_AUXIO29 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO29) -#define AUXTDC_STOP_AUXIO30 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO30) -#define AUXTDC_STOP_AUXIO31 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO31) -#define AUXTDC_STOP_MANUAL_EV (AUX_TDC_TRIGSRC_STOP_SRC_MANUAL_EV) -#define AUXTDC_STOP_AON_RTC_CH2_DLY (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2_DLY) -#define AUXTDC_STOP_AON_RTC_4KHZ (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_4KHZ) -#define AUXTDC_STOP_AON_BATMON_BAT_UPD (AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_BAT_UPD) -#define AUXTDC_STOP_AON_BATMON_TEMP_UPD (AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_TEMP_UPD) -#define AUXTDC_STOP_SCLK_LF (AUX_TDC_TRIGSRC_STOP_SRC_SCLK_LF) -#define AUXTDC_STOP_PWR_DWN (AUX_TDC_TRIGSRC_STOP_SRC_PWR_DWN) -#define AUXTDC_STOP_MCU_ACTIVE (AUX_TDC_TRIGSRC_STOP_SRC_MCU_ACTIVE) -#define AUXTDC_STOP_VDDR_RECHARGE (AUX_TDC_TRIGSRC_STOP_SRC_VDDR_RECHARGE) -#define AUXTDC_STOP_TIMER2_EV0 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV0) -#define AUXTDC_STOP_TIMER2_EV1 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV1) -#define AUXTDC_STOP_TIMER2_EV2 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV2) -#define AUXTDC_STOP_TIMER2_EV3 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV3) -#define AUXTDC_STOP_TIMER2_PULSE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_PULSE) -#define AUXTDC_STOP_TDC_DONE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_DONE) -#define AUXTDC_STOP_ADC_IRQ (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_IRQ) -#define AUXTDC_STOP_ADC_FIFO_NOT_EMPTY (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_NOT_EMPTY) -#define AUXTDC_STOP_NO_EVENT (AUX_TDC_TRIGSRC_STOP_SRC_NO_EVENT) -#define AUXTDC_STOP_ADC_DONE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_DONE) -#define AUXTDC_STOP_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_ALMOST_FULL) -#define AUXTDC_STOP_ISRC_RESET (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ISRC_RESET_N) -#define AUXTDC_STOP_OBSMUX0 (AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX0) -#define AUXTDC_STOP_OBSMUX1 (AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX1) -#define AUXTDC_STOP_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_SMPH_AUTOTAKE_DONE) -#define AUXTDC_STOP_TDC_PRE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_PRE) -#define AUXTDC_STOP_TIMER0_EV (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER0_EV) -#define AUXTDC_STOP_TIMER1_EV (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER1_EV) -#define AUXTDC_STOP_AON_RTC_CH2 (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2) -#define AUXTDC_STOP_AUX_COMPA (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA) -#define AUXTDC_STOP_AUX_COMPB (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB) -#define AUXTDC_STOP_ACLK_REF (AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF) -#define AUXTDC_STOP_MCU_EV (AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV) +#define AUXTDC_STOP_AUXIO0 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0) +#define AUXTDC_STOP_AUXIO1 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1) +#define AUXTDC_STOP_AUXIO2 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2) +#define AUXTDC_STOP_AUXIO3 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3) +#define AUXTDC_STOP_AUXIO4 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4) +#define AUXTDC_STOP_AUXIO5 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5) +#define AUXTDC_STOP_AUXIO6 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6) +#define AUXTDC_STOP_AUXIO7 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7) +#define AUXTDC_STOP_AUXIO8 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8) +#define AUXTDC_STOP_AUXIO9 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9) +#define AUXTDC_STOP_AUXIO10 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10) +#define AUXTDC_STOP_AUXIO11 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11) +#define AUXTDC_STOP_AUXIO12 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12) +#define AUXTDC_STOP_AUXIO13 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13) +#define AUXTDC_STOP_AUXIO14 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14) +#define AUXTDC_STOP_AUXIO15 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15) +#define AUXTDC_STOP_AUXIO16 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO16) +#define AUXTDC_STOP_AUXIO17 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO17) +#define AUXTDC_STOP_AUXIO18 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO18) +#define AUXTDC_STOP_AUXIO19 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO19) +#define AUXTDC_STOP_AUXIO20 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO20) +#define AUXTDC_STOP_AUXIO21 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO21) +#define AUXTDC_STOP_AUXIO22 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO22) +#define AUXTDC_STOP_AUXIO23 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO23) +#define AUXTDC_STOP_AUXIO24 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO24) +#define AUXTDC_STOP_AUXIO25 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO25) +#define AUXTDC_STOP_AUXIO26 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO26) +#define AUXTDC_STOP_AUXIO27 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO27) +#define AUXTDC_STOP_AUXIO28 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO28) +#define AUXTDC_STOP_AUXIO29 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO29) +#define AUXTDC_STOP_AUXIO30 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO30) +#define AUXTDC_STOP_AUXIO31 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO31) +#define AUXTDC_STOP_MANUAL_EV (AUX_TDC_TRIGSRC_STOP_SRC_MANUAL_EV) +#define AUXTDC_STOP_AON_RTC_CH2_DLY (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2_DLY) +#define AUXTDC_STOP_AON_RTC_4KHZ (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_4KHZ) +#define AUXTDC_STOP_AON_BATMON_BAT_UPD (AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_BAT_UPD) +#define AUXTDC_STOP_AON_BATMON_TEMP_UPD (AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_TEMP_UPD) +#define AUXTDC_STOP_SCLK_LF (AUX_TDC_TRIGSRC_STOP_SRC_SCLK_LF) +#define AUXTDC_STOP_PWR_DWN (AUX_TDC_TRIGSRC_STOP_SRC_PWR_DWN) +#define AUXTDC_STOP_MCU_ACTIVE (AUX_TDC_TRIGSRC_STOP_SRC_MCU_ACTIVE) +#define AUXTDC_STOP_VDDR_RECHARGE (AUX_TDC_TRIGSRC_STOP_SRC_VDDR_RECHARGE) +#define AUXTDC_STOP_TIMER2_EV0 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV0) +#define AUXTDC_STOP_TIMER2_EV1 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV1) +#define AUXTDC_STOP_TIMER2_EV2 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV2) +#define AUXTDC_STOP_TIMER2_EV3 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV3) +#define AUXTDC_STOP_TIMER2_PULSE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_PULSE) +#define AUXTDC_STOP_TDC_DONE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_DONE) +#define AUXTDC_STOP_ADC_IRQ (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_IRQ) +#define AUXTDC_STOP_ADC_FIFO_NOT_EMPTY (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_NOT_EMPTY) +#define AUXTDC_STOP_NO_EVENT (AUX_TDC_TRIGSRC_STOP_SRC_NO_EVENT) +#define AUXTDC_STOP_ADC_DONE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_DONE) +#define AUXTDC_STOP_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_ALMOST_FULL) +#define AUXTDC_STOP_ISRC_RESET (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ISRC_RESET_N) +#define AUXTDC_STOP_OBSMUX0 (AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX0) +#define AUXTDC_STOP_OBSMUX1 (AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX1) +#define AUXTDC_STOP_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_SMPH_AUTOTAKE_DONE) +#define AUXTDC_STOP_TDC_PRE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_PRE) +#define AUXTDC_STOP_TIMER0_EV (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER0_EV) +#define AUXTDC_STOP_TIMER1_EV (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER1_EV) +#define AUXTDC_STOP_AON_RTC_CH2 (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2) +#define AUXTDC_STOP_AUX_COMPA (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA) +#define AUXTDC_STOP_AUX_COMPB (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB) +#define AUXTDC_STOP_ACLK_REF (AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF) +#define AUXTDC_STOP_MCU_EV (AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV) -#define AUXTDC_STARTPOL_RIS (AUX_TDC_TRIGSRC_START_POL_HIGH) // Rising edge polarity for start event -#define AUXTDC_STARTPOL_FALL (AUX_TDC_TRIGSRC_START_POL_LOW) // Falling edge polarity for start event +#define AUXTDC_STARTPOL_RIS (AUX_TDC_TRIGSRC_START_POL_HIGH) // Rising edge polarity for start event +#define AUXTDC_STARTPOL_FALL (AUX_TDC_TRIGSRC_START_POL_LOW) // Falling edge polarity for start event -#define AUXTDC_START_AUXIO0 (AUX_TDC_TRIGSRC_START_SRC_AUXIO0) -#define AUXTDC_START_AUXIO1 (AUX_TDC_TRIGSRC_START_SRC_AUXIO1) -#define AUXTDC_START_AUXIO2 (AUX_TDC_TRIGSRC_START_SRC_AUXIO2) -#define AUXTDC_START_AUXIO3 (AUX_TDC_TRIGSRC_START_SRC_AUXIO3) -#define AUXTDC_START_AUXIO4 (AUX_TDC_TRIGSRC_START_SRC_AUXIO4) -#define AUXTDC_START_AUXIO5 (AUX_TDC_TRIGSRC_START_SRC_AUXIO5) -#define AUXTDC_START_AUXIO6 (AUX_TDC_TRIGSRC_START_SRC_AUXIO6) -#define AUXTDC_START_AUXIO7 (AUX_TDC_TRIGSRC_START_SRC_AUXIO7) -#define AUXTDC_START_AUXIO8 (AUX_TDC_TRIGSRC_START_SRC_AUXIO8) -#define AUXTDC_START_AUXIO9 (AUX_TDC_TRIGSRC_START_SRC_AUXIO9) -#define AUXTDC_START_AUXIO10 (AUX_TDC_TRIGSRC_START_SRC_AUXIO10) -#define AUXTDC_START_AUXIO11 (AUX_TDC_TRIGSRC_START_SRC_AUXIO11) -#define AUXTDC_START_AUXIO12 (AUX_TDC_TRIGSRC_START_SRC_AUXIO12) -#define AUXTDC_START_AUXIO13 (AUX_TDC_TRIGSRC_START_SRC_AUXIO13) -#define AUXTDC_START_AUXIO14 (AUX_TDC_TRIGSRC_START_SRC_AUXIO14) -#define AUXTDC_START_AUXIO15 (AUX_TDC_TRIGSRC_START_SRC_AUXIO15) -#define AUXTDC_START_AUXIO16 (AUX_TDC_TRIGSRC_START_SRC_AUXIO16) -#define AUXTDC_START_AUXIO17 (AUX_TDC_TRIGSRC_START_SRC_AUXIO17) -#define AUXTDC_START_AUXIO18 (AUX_TDC_TRIGSRC_START_SRC_AUXIO18) -#define AUXTDC_START_AUXIO19 (AUX_TDC_TRIGSRC_START_SRC_AUXIO19) -#define AUXTDC_START_AUXIO20 (AUX_TDC_TRIGSRC_START_SRC_AUXIO20) -#define AUXTDC_START_AUXIO21 (AUX_TDC_TRIGSRC_START_SRC_AUXIO21) -#define AUXTDC_START_AUXIO22 (AUX_TDC_TRIGSRC_START_SRC_AUXIO22) -#define AUXTDC_START_AUXIO23 (AUX_TDC_TRIGSRC_START_SRC_AUXIO23) -#define AUXTDC_START_AUXIO24 (AUX_TDC_TRIGSRC_START_SRC_AUXIO24) -#define AUXTDC_START_AUXIO25 (AUX_TDC_TRIGSRC_START_SRC_AUXIO25) -#define AUXTDC_START_AUXIO26 (AUX_TDC_TRIGSRC_START_SRC_AUXIO26) -#define AUXTDC_START_AUXIO27 (AUX_TDC_TRIGSRC_START_SRC_AUXIO27) -#define AUXTDC_START_AUXIO28 (AUX_TDC_TRIGSRC_START_SRC_AUXIO28) -#define AUXTDC_START_AUXIO29 (AUX_TDC_TRIGSRC_START_SRC_AUXIO29) -#define AUXTDC_START_AUXIO30 (AUX_TDC_TRIGSRC_START_SRC_AUXIO30) -#define AUXTDC_START_AUXIO31 (AUX_TDC_TRIGSRC_START_SRC_AUXIO31) -#define AUXTDC_START_MANUAL_EV (AUX_TDC_TRIGSRC_START_SRC_MANUAL_EV) -#define AUXTDC_START_AON_RTC_CH2_DLY (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2_DLY) -#define AUXTDC_START_AON_RTC_4KHZ (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_4KHZ) -#define AUXTDC_START_AON_BATMON_BAT_UPD (AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_BAT_UPD) -#define AUXTDC_START_AON_BATMON_TEMP_UPD (AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_TEMP_UPD) -#define AUXTDC_START_SCLK_LF (AUX_TDC_TRIGSRC_START_SRC_SCLK_LF) -#define AUXTDC_START_PWR_DWN (AUX_TDC_TRIGSRC_START_SRC_PWR_DWN) -#define AUXTDC_START_MCU_ACTIVE (AUX_TDC_TRIGSRC_START_SRC_MCU_ACTIVE) -#define AUXTDC_START_VDDR_RECHARGE (AUX_TDC_TRIGSRC_START_SRC_VDDR_RECHARGE) -#define AUXTDC_START_TIMER2_EV0 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV0) -#define AUXTDC_START_TIMER2_EV1 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV1) -#define AUXTDC_START_TIMER2_EV2 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV2) -#define AUXTDC_START_TIMER2_EV3 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV3) -#define AUXTDC_START_TIMER2_PULSE (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_PULSE) -#define AUXTDC_START_TDC_DONE (AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_DONE) -#define AUXTDC_START_ADC_IRQ (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_IRQ) -#define AUXTDC_START_ADC_FIFO_NOT_EMPTY (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_NOT_EMPTY) -#define AUXTDC_START_NO_EVENT (AUX_TDC_TRIGSRC_START_SRC_NO_EVENT) -#define AUXTDC_START_ADC_DONE (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_DONE) +#define AUXTDC_START_AUXIO0 (AUX_TDC_TRIGSRC_START_SRC_AUXIO0) +#define AUXTDC_START_AUXIO1 (AUX_TDC_TRIGSRC_START_SRC_AUXIO1) +#define AUXTDC_START_AUXIO2 (AUX_TDC_TRIGSRC_START_SRC_AUXIO2) +#define AUXTDC_START_AUXIO3 (AUX_TDC_TRIGSRC_START_SRC_AUXIO3) +#define AUXTDC_START_AUXIO4 (AUX_TDC_TRIGSRC_START_SRC_AUXIO4) +#define AUXTDC_START_AUXIO5 (AUX_TDC_TRIGSRC_START_SRC_AUXIO5) +#define AUXTDC_START_AUXIO6 (AUX_TDC_TRIGSRC_START_SRC_AUXIO6) +#define AUXTDC_START_AUXIO7 (AUX_TDC_TRIGSRC_START_SRC_AUXIO7) +#define AUXTDC_START_AUXIO8 (AUX_TDC_TRIGSRC_START_SRC_AUXIO8) +#define AUXTDC_START_AUXIO9 (AUX_TDC_TRIGSRC_START_SRC_AUXIO9) +#define AUXTDC_START_AUXIO10 (AUX_TDC_TRIGSRC_START_SRC_AUXIO10) +#define AUXTDC_START_AUXIO11 (AUX_TDC_TRIGSRC_START_SRC_AUXIO11) +#define AUXTDC_START_AUXIO12 (AUX_TDC_TRIGSRC_START_SRC_AUXIO12) +#define AUXTDC_START_AUXIO13 (AUX_TDC_TRIGSRC_START_SRC_AUXIO13) +#define AUXTDC_START_AUXIO14 (AUX_TDC_TRIGSRC_START_SRC_AUXIO14) +#define AUXTDC_START_AUXIO15 (AUX_TDC_TRIGSRC_START_SRC_AUXIO15) +#define AUXTDC_START_AUXIO16 (AUX_TDC_TRIGSRC_START_SRC_AUXIO16) +#define AUXTDC_START_AUXIO17 (AUX_TDC_TRIGSRC_START_SRC_AUXIO17) +#define AUXTDC_START_AUXIO18 (AUX_TDC_TRIGSRC_START_SRC_AUXIO18) +#define AUXTDC_START_AUXIO19 (AUX_TDC_TRIGSRC_START_SRC_AUXIO19) +#define AUXTDC_START_AUXIO20 (AUX_TDC_TRIGSRC_START_SRC_AUXIO20) +#define AUXTDC_START_AUXIO21 (AUX_TDC_TRIGSRC_START_SRC_AUXIO21) +#define AUXTDC_START_AUXIO22 (AUX_TDC_TRIGSRC_START_SRC_AUXIO22) +#define AUXTDC_START_AUXIO23 (AUX_TDC_TRIGSRC_START_SRC_AUXIO23) +#define AUXTDC_START_AUXIO24 (AUX_TDC_TRIGSRC_START_SRC_AUXIO24) +#define AUXTDC_START_AUXIO25 (AUX_TDC_TRIGSRC_START_SRC_AUXIO25) +#define AUXTDC_START_AUXIO26 (AUX_TDC_TRIGSRC_START_SRC_AUXIO26) +#define AUXTDC_START_AUXIO27 (AUX_TDC_TRIGSRC_START_SRC_AUXIO27) +#define AUXTDC_START_AUXIO28 (AUX_TDC_TRIGSRC_START_SRC_AUXIO28) +#define AUXTDC_START_AUXIO29 (AUX_TDC_TRIGSRC_START_SRC_AUXIO29) +#define AUXTDC_START_AUXIO30 (AUX_TDC_TRIGSRC_START_SRC_AUXIO30) +#define AUXTDC_START_AUXIO31 (AUX_TDC_TRIGSRC_START_SRC_AUXIO31) +#define AUXTDC_START_MANUAL_EV (AUX_TDC_TRIGSRC_START_SRC_MANUAL_EV) +#define AUXTDC_START_AON_RTC_CH2_DLY (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2_DLY) +#define AUXTDC_START_AON_RTC_4KHZ (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_4KHZ) +#define AUXTDC_START_AON_BATMON_BAT_UPD (AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_BAT_UPD) +#define AUXTDC_START_AON_BATMON_TEMP_UPD (AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_TEMP_UPD) +#define AUXTDC_START_SCLK_LF (AUX_TDC_TRIGSRC_START_SRC_SCLK_LF) +#define AUXTDC_START_PWR_DWN (AUX_TDC_TRIGSRC_START_SRC_PWR_DWN) +#define AUXTDC_START_MCU_ACTIVE (AUX_TDC_TRIGSRC_START_SRC_MCU_ACTIVE) +#define AUXTDC_START_VDDR_RECHARGE (AUX_TDC_TRIGSRC_START_SRC_VDDR_RECHARGE) +#define AUXTDC_START_TIMER2_EV0 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV0) +#define AUXTDC_START_TIMER2_EV1 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV1) +#define AUXTDC_START_TIMER2_EV2 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV2) +#define AUXTDC_START_TIMER2_EV3 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV3) +#define AUXTDC_START_TIMER2_PULSE (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_PULSE) +#define AUXTDC_START_TDC_DONE (AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_DONE) +#define AUXTDC_START_ADC_IRQ (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_IRQ) +#define AUXTDC_START_ADC_FIFO_NOT_EMPTY (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_NOT_EMPTY) +#define AUXTDC_START_NO_EVENT (AUX_TDC_TRIGSRC_START_SRC_NO_EVENT) +#define AUXTDC_START_ADC_DONE (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_DONE) #define AUXTDC_START_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_ALMOST_FULL) -#define AUXTDC_START_ISRC_RESET (AUX_TDC_TRIGSRC_START_SRC_AUX_ISRC_RESET_N) -#define AUXTDC_START_OBSMUX0 (AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX0) -#define AUXTDC_START_OBSMUX1 (AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX1) -#define AUXTDC_START_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_START_SRC_AUX_SMPH_AUTOTAKE_DONE) -#define AUXTDC_START_TDC_PRE (AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_PRE) -#define AUXTDC_START_TIMER0_EV (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER0_EV) -#define AUXTDC_START_TIMER1_EV (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER1_EV) -#define AUXTDC_START_AON_RTC_CH2 (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2) -#define AUXTDC_START_AUX_COMPA (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA) -#define AUXTDC_START_AUX_COMPB (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB) -#define AUXTDC_START_ACLK_REF (AUX_TDC_TRIGSRC_START_SRC_ACLK_REF) -#define AUXTDC_START_MCU_EV (AUX_TDC_TRIGSRC_START_SRC_MCU_EV) +#define AUXTDC_START_ISRC_RESET (AUX_TDC_TRIGSRC_START_SRC_AUX_ISRC_RESET_N) +#define AUXTDC_START_OBSMUX0 (AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX0) +#define AUXTDC_START_OBSMUX1 (AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX1) +#define AUXTDC_START_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_START_SRC_AUX_SMPH_AUTOTAKE_DONE) +#define AUXTDC_START_TDC_PRE (AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_PRE) +#define AUXTDC_START_TIMER0_EV (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER0_EV) +#define AUXTDC_START_TIMER1_EV (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER1_EV) +#define AUXTDC_START_AON_RTC_CH2 (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2) +#define AUXTDC_START_AUX_COMPA (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA) +#define AUXTDC_START_AUX_COMPB (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB) +#define AUXTDC_START_ACLK_REF (AUX_TDC_TRIGSRC_START_SRC_ACLK_REF) +#define AUXTDC_START_MCU_EV (AUX_TDC_TRIGSRC_START_SRC_MCU_EV) //***************************************************************************** // // Defines for the possible saturation values set using AUXTDCLimitSet(). // //***************************************************************************** -#define AUXTDC_SAT_4096 (AUX_TDC_SATCFG_LIMIT_R12) -#define AUXTDC_SAT_8192 (AUX_TDC_SATCFG_LIMIT_R13) -#define AUXTDC_SAT_16384 (AUX_TDC_SATCFG_LIMIT_R14) -#define AUXTDC_SAT_32768 (AUX_TDC_SATCFG_LIMIT_R15) -#define AUXTDC_SAT_65536 (AUX_TDC_SATCFG_LIMIT_R16) -#define AUXTDC_SAT_131072 (AUX_TDC_SATCFG_LIMIT_R17) -#define AUXTDC_SAT_262144 (AUX_TDC_SATCFG_LIMIT_R18) -#define AUXTDC_SAT_524288 (AUX_TDC_SATCFG_LIMIT_R19) -#define AUXTDC_SAT_1048576 (AUX_TDC_SATCFG_LIMIT_R20) -#define AUXTDC_SAT_2097152 (AUX_TDC_SATCFG_LIMIT_R21) -#define AUXTDC_SAT_4194304 (AUX_TDC_SATCFG_LIMIT_R22) -#define AUXTDC_SAT_8388608 (AUX_TDC_SATCFG_LIMIT_R23) -#define AUXTDC_SAT_16777216 (AUX_TDC_SATCFG_LIMIT_R24) -#define AUXTDC_NUM_SAT_VALS 16 +#define AUXTDC_SAT_4096 (AUX_TDC_SATCFG_LIMIT_R12) +#define AUXTDC_SAT_8192 (AUX_TDC_SATCFG_LIMIT_R13) +#define AUXTDC_SAT_16384 (AUX_TDC_SATCFG_LIMIT_R14) +#define AUXTDC_SAT_32768 (AUX_TDC_SATCFG_LIMIT_R15) +#define AUXTDC_SAT_65536 (AUX_TDC_SATCFG_LIMIT_R16) +#define AUXTDC_SAT_131072 (AUX_TDC_SATCFG_LIMIT_R17) +#define AUXTDC_SAT_262144 (AUX_TDC_SATCFG_LIMIT_R18) +#define AUXTDC_SAT_524288 (AUX_TDC_SATCFG_LIMIT_R19) +#define AUXTDC_SAT_1048576 (AUX_TDC_SATCFG_LIMIT_R20) +#define AUXTDC_SAT_2097152 (AUX_TDC_SATCFG_LIMIT_R21) +#define AUXTDC_SAT_4194304 (AUX_TDC_SATCFG_LIMIT_R22) +#define AUXTDC_SAT_8388608 (AUX_TDC_SATCFG_LIMIT_R23) +#define AUXTDC_SAT_16777216 (AUX_TDC_SATCFG_LIMIT_R24) +#define AUXTDC_NUM_SAT_VALS 16 //***************************************************************************** // @@ -527,7 +526,9 @@ AUXTDCIdle(uint32_t ui32Base) // Check if the AUX TDC is in the Idle state. return (((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE) ? true : false); + AUX_TDC_STAT_STATE_IDLE) + ? true + : false); } //***************************************************************************** @@ -749,7 +750,7 @@ AUXTDCCounterEnable(uint32_t ui32Base) // Check if the AUX TDC is in idle mode. If not in Idle mode, the counter // will not be enabled. if (!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE)) + AUX_TDC_STAT_STATE_IDLE)) { return false; } @@ -785,7 +786,7 @@ AUXTDCCounterDisable(uint32_t ui32Base) // Check if the AUX TDC is in Idle mode. If not in Idle mode, the counter // will not be disabled. if (!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE)) + AUX_TDC_STAT_STATE_IDLE)) { return false; } @@ -826,7 +827,7 @@ AUXTDCCounterSet(uint32_t ui32Base, uint32_t ui32Events) // Check if the AUX TDC is in idle mode. If not in idle mode, the counter // will not be disabled. if (!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE)) + AUX_TDC_STAT_STATE_IDLE)) { return false; } @@ -875,12 +876,12 @@ AUXTDCCounterGet(uint32_t ui32Base) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AUXTDCConfigSet -#undef AUXTDCConfigSet -#define AUXTDCConfigSet ROM_AUXTDCConfigSet +#undef AUXTDCConfigSet +#define AUXTDCConfigSet ROM_AUXTDCConfigSet #endif #ifdef ROM_AUXTDCMeasurementDone -#undef AUXTDCMeasurementDone -#define AUXTDCMeasurementDone ROM_AUXTDCMeasurementDone +#undef AUXTDCMeasurementDone +#define AUXTDCMeasurementDone ROM_AUXTDCMeasurementDone #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.h index 3dec1eb..291eb62 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: ccfgread.h -* Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) -* Revision: 47152 -* -* Description: API for reading CCFG. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: ccfgread.h + * Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) + * Revision: 47152 + * + * Description: API for reading CCFG. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,15 +55,14 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_ccfg.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ccfg.h" //***************************************************************************** // @@ -71,7 +70,6 @@ extern "C" // //***************************************************************************** - //***************************************************************************** // // API Functions and prototypes @@ -86,11 +84,11 @@ extern "C" // //***************************************************************************** __STATIC_INLINE bool -CCFGRead_DIS_GPRAM( void ) +CCFGRead_DIS_GPRAM(void) { - return (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & - CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) >> - CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S ) ; + return ((HWREG(CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS) & + CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M) >> + CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S); } //***************************************************************************** @@ -101,11 +99,11 @@ CCFGRead_DIS_GPRAM( void ) // //***************************************************************************** __STATIC_INLINE bool -CCFGRead_EXT_LF_CLK_DIO( void ) +CCFGRead_EXT_LF_CLK_DIO(void) { - return (( HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK ) & - CCFG_EXT_LF_CLK_DIO_M ) >> - CCFG_EXT_LF_CLK_DIO_S ) ; + return ((HWREG(CCFG_BASE + CCFG_O_EXT_LF_CLK) & + CCFG_EXT_LF_CLK_DIO_M) >> + CCFG_EXT_LF_CLK_DIO_S); } //***************************************************************************** @@ -113,10 +111,10 @@ CCFGRead_EXT_LF_CLK_DIO( void ) // Defines the possible values returned from CCFGRead_SCLK_LF_OPTION() // //***************************************************************************** -#define CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF ( CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) -#define CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) -#define CCFGREAD_SCLK_LF_OPTION_XOSC_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) -#define CCFGREAD_SCLK_LF_OPTION_RCOSC_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) +#define CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF (CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S) +#define CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF (CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S) +#define CCFGREAD_SCLK_LF_OPTION_XOSC_LF (CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S) +#define CCFGREAD_SCLK_LF_OPTION_RCOSC_LF (CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S) //***************************************************************************** // @@ -131,11 +129,11 @@ CCFGRead_EXT_LF_CLK_DIO( void ) // //***************************************************************************** __STATIC_INLINE uint32_t -CCFGRead_SCLK_LF_OPTION( void ) +CCFGRead_SCLK_LF_OPTION(void) { - return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF ) & - CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> - CCFG_MODE_CONF_SCLK_LF_OPTION_S ) ; + return ((HWREG(CCFG_BASE + CCFG_O_MODE_CONF) & + CCFG_MODE_CONF_SCLK_LF_OPTION_M) >> + CCFG_MODE_CONF_SCLK_LF_OPTION_S); } //***************************************************************************** @@ -143,9 +141,9 @@ CCFGRead_SCLK_LF_OPTION( void ) // Defines the possible values returned from CCFGRead_XOSC_FREQ() // //***************************************************************************** -#define CCFGREAD_XOSC_FREQ_24M ( CCFG_MODE_CONF_XOSC_FREQ_24M >> CCFG_MODE_CONF_XOSC_FREQ_S ) -#define CCFGREAD_XOSC_FREQ_48M ( CCFG_MODE_CONF_XOSC_FREQ_48M >> CCFG_MODE_CONF_XOSC_FREQ_S ) -#define CCFGREAD_XOSC_FREQ_HPOSC ( CCFG_MODE_CONF_XOSC_FREQ_HPOSC >> CCFG_MODE_CONF_XOSC_FREQ_S ) +#define CCFGREAD_XOSC_FREQ_24M (CCFG_MODE_CONF_XOSC_FREQ_24M >> CCFG_MODE_CONF_XOSC_FREQ_S) +#define CCFGREAD_XOSC_FREQ_48M (CCFG_MODE_CONF_XOSC_FREQ_48M >> CCFG_MODE_CONF_XOSC_FREQ_S) +#define CCFGREAD_XOSC_FREQ_HPOSC (CCFG_MODE_CONF_XOSC_FREQ_HPOSC >> CCFG_MODE_CONF_XOSC_FREQ_S) //***************************************************************************** // @@ -160,11 +158,11 @@ CCFGRead_SCLK_LF_OPTION( void ) // //***************************************************************************** __STATIC_INLINE uint32_t -CCFGRead_XOSC_FREQ( void ) +CCFGRead_XOSC_FREQ(void) { - return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF ) & - CCFG_MODE_CONF_XOSC_FREQ_M ) >> - CCFG_MODE_CONF_XOSC_FREQ_S ) ; + return ((HWREG(CCFG_BASE + CCFG_O_MODE_CONF) & + CCFG_MODE_CONF_XOSC_FREQ_M) >> + CCFG_MODE_CONF_XOSC_FREQ_S); } //***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread_doc.h index f3175fb..f8e9b82 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: ccfgread_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: ccfgread_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup ccfgread_api //! @{ //! \section sec_ccfgread Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.h index 255db9b..3892e80 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: chipinfo.h -* Revised: 2018-06-18 10:26:12 +0200 (Mon, 18 Jun 2018) -* Revision: 52189 -* -* Description: Collection of functions returning chip information. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: chipinfo.h + * Revised: 2018-06-18 10:26:12 +0200 (Mon, 18 Jun 2018) + * Revision: 52189 + * + * Description: Collection of functions returning chip information. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,15 +55,14 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" #include "../inc/hw_fcfg1.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include +#include //***************************************************************************** // @@ -80,10 +79,10 @@ extern "C" //***************************************************************************** #if !defined(DOXYGEN) #define ChipInfo_GetSupportedProtocol_BV NOROM_ChipInfo_GetSupportedProtocol_BV -#define ChipInfo_GetPackageType NOROM_ChipInfo_GetPackageType -#define ChipInfo_GetChipType NOROM_ChipInfo_GetChipType -#define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily -#define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision +#define ChipInfo_GetPackageType NOROM_ChipInfo_GetPackageType +#define ChipInfo_GetChipType NOROM_ChipInfo_GetChipType +#define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily +#define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision #define ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated NOROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated #endif @@ -98,10 +97,10 @@ extern "C" //***************************************************************************** typedef enum { - PROTOCOL_Unknown = 0, //!< None of the known protocols are supported. - PROTOCOLBIT_BLE = 0x02, //!< Bit[1] set, indicates that Bluetooth Low Energy is supported. + PROTOCOL_Unknown = 0, //!< None of the known protocols are supported. + PROTOCOLBIT_BLE = 0x02, //!< Bit[1] set, indicates that Bluetooth Low Energy is supported. PROTOCOLBIT_IEEE_802_15_4 = 0x04, //!< Bit[2] set, indicates that IEEE 802.15.4 is supported. - PROTOCOLBIT_Proprietary = 0x08 //!< Bit[3] set, indicates that proprietary protocols are supported. + PROTOCOLBIT_Proprietary = 0x08 //!< Bit[3] set, indicates that proprietary protocols are supported. } ProtocolBitVector_t; //***************************************************************************** @@ -112,7 +111,7 @@ typedef enum //! Returns \ref ProtocolBitVector_t which is a bit vector indicating supported protocols. // //***************************************************************************** -extern ProtocolBitVector_t ChipInfo_GetSupportedProtocol_BV( void ); +extern ProtocolBitVector_t ChipInfo_GetSupportedProtocol_BV(void); //***************************************************************************** // @@ -123,9 +122,9 @@ extern ProtocolBitVector_t ChipInfo_GetSupportedProtocol_BV( void ); // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_SupportsBLE( void ) +ChipInfo_SupportsBLE(void) { - return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_BLE ) != 0 ); + return ((ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_BLE) != 0); } //***************************************************************************** @@ -137,9 +136,9 @@ ChipInfo_SupportsBLE( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_SupportsIEEE_802_15_4( void ) +ChipInfo_SupportsIEEE_802_15_4(void) { - return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_IEEE_802_15_4 ) != 0 ); + return ((ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_IEEE_802_15_4) != 0); } //***************************************************************************** @@ -151,9 +150,9 @@ ChipInfo_SupportsIEEE_802_15_4( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_SupportsPROPRIETARY( void ) +ChipInfo_SupportsPROPRIETARY(void) { - return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_Proprietary ) != 0 ); + return ((ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_Proprietary) != 0); } //***************************************************************************** @@ -166,13 +165,13 @@ ChipInfo_SupportsPROPRIETARY( void ) //***************************************************************************** typedef enum { - PACKAGE_Unknown = -1, //!< -1 means that current package type is unknown. - PACKAGE_4x4 = 0, //!< 0 means that this is a 4x4 mm QFN (RHB) package. - PACKAGE_5x5 = 1, //!< 1 means that this is a 5x5 mm QFN (RSM) package. - PACKAGE_7x7 = 2, //!< 2 means that this is a 7x7 mm QFN (RGZ) package. - PACKAGE_WAFER = 3, //!< 3 means that this is a wafer sale package (naked die). - PACKAGE_WCSP = 4, //!< 4 means that this is a 2.7x2.7 mm WCSP (YFV). - PACKAGE_7x7_Q1 = 5 //!< 5 means that this is a 7x7 mm QFN package with Wettable Flanks. + PACKAGE_Unknown = -1, //!< -1 means that current package type is unknown. + PACKAGE_4x4 = 0, //!< 0 means that this is a 4x4 mm QFN (RHB) package. + PACKAGE_5x5 = 1, //!< 1 means that this is a 5x5 mm QFN (RSM) package. + PACKAGE_7x7 = 2, //!< 2 means that this is a 7x7 mm QFN (RGZ) package. + PACKAGE_WAFER = 3, //!< 3 means that this is a wafer sale package (naked die). + PACKAGE_WCSP = 4, //!< 4 means that this is a 2.7x2.7 mm WCSP (YFV). + PACKAGE_7x7_Q1 = 5 //!< 5 means that this is a 7x7 mm QFN package with Wettable Flanks. } PackageType_t; //***************************************************************************** @@ -183,7 +182,7 @@ typedef enum //! Returns \ref PackageType_t // //***************************************************************************** -extern PackageType_t ChipInfo_GetPackageType( void ); +extern PackageType_t ChipInfo_GetPackageType(void); //***************************************************************************** // @@ -194,9 +193,9 @@ extern PackageType_t ChipInfo_GetPackageType( void ); // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_PackageTypeIs4x4( void ) +ChipInfo_PackageTypeIs4x4(void) { - return ( ChipInfo_GetPackageType() == PACKAGE_4x4 ); + return (ChipInfo_GetPackageType() == PACKAGE_4x4); } //***************************************************************************** @@ -208,9 +207,9 @@ ChipInfo_PackageTypeIs4x4( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_PackageTypeIs5x5( void ) +ChipInfo_PackageTypeIs5x5(void) { - return ( ChipInfo_GetPackageType() == PACKAGE_5x5 ); + return (ChipInfo_GetPackageType() == PACKAGE_5x5); } //***************************************************************************** @@ -222,9 +221,9 @@ ChipInfo_PackageTypeIs5x5( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_PackageTypeIs7x7( void ) +ChipInfo_PackageTypeIs7x7(void) { - return ( ChipInfo_GetPackageType() == PACKAGE_7x7 ); + return (ChipInfo_GetPackageType() == PACKAGE_7x7); } //***************************************************************************** @@ -236,9 +235,9 @@ ChipInfo_PackageTypeIs7x7( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_PackageTypeIsWAFER( void ) +ChipInfo_PackageTypeIsWAFER(void) { - return ( ChipInfo_GetPackageType() == PACKAGE_WAFER ); + return (ChipInfo_GetPackageType() == PACKAGE_WAFER); } //***************************************************************************** @@ -250,9 +249,9 @@ ChipInfo_PackageTypeIsWAFER( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_PackageTypeIsWCSP( void ) +ChipInfo_PackageTypeIsWCSP(void) { - return ( ChipInfo_GetPackageType() == PACKAGE_WCSP ); + return (ChipInfo_GetPackageType() == PACKAGE_WCSP); } //***************************************************************************** @@ -264,9 +263,9 @@ ChipInfo_PackageTypeIsWCSP( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_PackageTypeIs7x7Q1( void ) +ChipInfo_PackageTypeIs7x7Q1(void) { - return ( ChipInfo_GetPackageType() == PACKAGE_7x7_Q1 ); + return (ChipInfo_GetPackageType() == PACKAGE_7x7_Q1); } //***************************************************************************** @@ -277,10 +276,10 @@ ChipInfo_PackageTypeIs7x7Q1( void ) //! Returns the internal chip HW revision code (in range 0-15) //***************************************************************************** __STATIC_INLINE uint32_t -ChipInfo_GetDeviceIdHwRevCode( void ) +ChipInfo_GetDeviceIdHwRevCode(void) { // Returns HwRevCode = FCFG1_O_ICEPICK_DEVICE_ID[31:28] - return ( HWREG( FCFG1_BASE + FCFG1_O_ICEPICK_DEVICE_ID ) >> 28 ); + return (HWREG(FCFG1_BASE + FCFG1_O_ICEPICK_DEVICE_ID) >> 28); } //***************************************************************************** @@ -295,18 +294,18 @@ ChipInfo_GetDeviceIdHwRevCode( void ) // //***************************************************************************** __STATIC_INLINE uint32_t -ChipInfo_GetMinorHwRev( void ) +ChipInfo_GetMinorHwRev(void) { - uint32_t minorRev = (( HWREG( FCFG1_BASE + FCFG1_O_MISC_CONF_1 ) & - FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M ) >> - FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S ) ; + uint32_t minorRev = ((HWREG(FCFG1_BASE + FCFG1_O_MISC_CONF_1) & + FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M) >> + FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S); - if ( minorRev >= 0x80 ) + if (minorRev >= 0x80) { minorRev = 0; } - return ( minorRev ); + return (minorRev); } //***************************************************************************** @@ -320,9 +319,9 @@ ChipInfo_GetMinorHwRev( void ) // //***************************************************************************** __STATIC_INLINE uint32_t -ChipInfo_GetUserId( void ) +ChipInfo_GetUserId(void) { - return ( HWREG( FCFG1_BASE + FCFG1_O_USER_ID )); + return (HWREG(FCFG1_BASE + FCFG1_O_USER_ID)); } //***************************************************************************** @@ -332,22 +331,22 @@ ChipInfo_GetUserId( void ) //***************************************************************************** typedef enum { - CHIP_TYPE_Unknown = -1, //!< -1 means that the chip type is unknown. - CHIP_TYPE_CC1310 = 0, //!< 0 means that this is a CC1310 chip. - CHIP_TYPE_CC1350 = 1, //!< 1 means that this is a CC1350 chip. - CHIP_TYPE_CC2620 = 2, //!< 2 means that this is a CC2620 chip. - CHIP_TYPE_CC2630 = 3, //!< 3 means that this is a CC2630 chip. - CHIP_TYPE_CC2640 = 4, //!< 4 means that this is a CC2640 chip. - CHIP_TYPE_CC2650 = 5, //!< 5 means that this is a CC2650 chip. - CHIP_TYPE_CUSTOM_0 = 6, //!< 6 means that this is a CUSTOM_0 chip. - CHIP_TYPE_CUSTOM_1 = 7, //!< 7 means that this is a CUSTOM_1 chip. - CHIP_TYPE_CC2640R2 = 8, //!< 8 means that this is a CC2640R2 chip. - CHIP_TYPE_CC2642 = 9, //!< 9 means that this is a CC2642 chip. - CHIP_TYPE_unused = 10,//!< 10 unused value - CHIP_TYPE_CC2652 = 11,//!< 11 means that this is a CC2652 chip. - CHIP_TYPE_CC1312 = 12,//!< 12 means that this is a CC1312 chip. - CHIP_TYPE_CC1352 = 13,//!< 13 means that this is a CC1352 chip. - CHIP_TYPE_CC1352P = 14 //!< 14 means that this is a CC1352P chip. + CHIP_TYPE_Unknown = -1, //!< -1 means that the chip type is unknown. + CHIP_TYPE_CC1310 = 0, //!< 0 means that this is a CC1310 chip. + CHIP_TYPE_CC1350 = 1, //!< 1 means that this is a CC1350 chip. + CHIP_TYPE_CC2620 = 2, //!< 2 means that this is a CC2620 chip. + CHIP_TYPE_CC2630 = 3, //!< 3 means that this is a CC2630 chip. + CHIP_TYPE_CC2640 = 4, //!< 4 means that this is a CC2640 chip. + CHIP_TYPE_CC2650 = 5, //!< 5 means that this is a CC2650 chip. + CHIP_TYPE_CUSTOM_0 = 6, //!< 6 means that this is a CUSTOM_0 chip. + CHIP_TYPE_CUSTOM_1 = 7, //!< 7 means that this is a CUSTOM_1 chip. + CHIP_TYPE_CC2640R2 = 8, //!< 8 means that this is a CC2640R2 chip. + CHIP_TYPE_CC2642 = 9, //!< 9 means that this is a CC2642 chip. + CHIP_TYPE_unused = 10, //!< 10 unused value + CHIP_TYPE_CC2652 = 11, //!< 11 means that this is a CC2652 chip. + CHIP_TYPE_CC1312 = 12, //!< 12 means that this is a CC1312 chip. + CHIP_TYPE_CC1352 = 13, //!< 13 means that this is a CC1352 chip. + CHIP_TYPE_CC1352P = 14 //!< 14 means that this is a CC1352P chip. } ChipType_t; //***************************************************************************** @@ -358,7 +357,7 @@ typedef enum //! Returns \ref ChipType_t // //***************************************************************************** -extern ChipType_t ChipInfo_GetChipType( void ); +extern ChipType_t ChipInfo_GetChipType(void); //***************************************************************************** // @@ -367,12 +366,12 @@ extern ChipType_t ChipInfo_GetChipType( void ); //***************************************************************************** typedef enum { - FAMILY_Unknown = -1, //!< -1 means that the chip's family member is unknown. - FAMILY_CC26x0 = 0, //!< 0 means that the chip is a CC26x0 family member. - FAMILY_CC13x0 = 1, //!< 1 means that the chip is a CC13x0 family member. - FAMILY_CC26x1 = 2, //!< 2 means that the chip is a CC26x1 family member. - FAMILY_CC26x0R2 = 3, //!< 3 means that the chip is a CC26x0R2 family (new ROM contents). - FAMILY_CC13x2_CC26x2 = 4 //!< 4 means that the chip is a CC13x2, CC26x2 family member. + FAMILY_Unknown = -1, //!< -1 means that the chip's family member is unknown. + FAMILY_CC26x0 = 0, //!< 0 means that the chip is a CC26x0 family member. + FAMILY_CC13x0 = 1, //!< 1 means that the chip is a CC13x0 family member. + FAMILY_CC26x1 = 2, //!< 2 means that the chip is a CC26x1 family member. + FAMILY_CC26x0R2 = 3, //!< 3 means that the chip is a CC26x0R2 family (new ROM contents). + FAMILY_CC13x2_CC26x2 = 4 //!< 4 means that the chip is a CC13x2, CC26x2 family member. } ChipFamily_t; //***************************************************************************** @@ -383,17 +382,17 @@ typedef enum //! Returns \ref ChipFamily_t // //***************************************************************************** -extern ChipFamily_t ChipInfo_GetChipFamily( void ); +extern ChipFamily_t ChipInfo_GetChipFamily(void); //***************************************************************************** // // Options for the define THIS_DRIVERLIB_BUILD // //***************************************************************************** -#define DRIVERLIB_BUILD_CC26X0 0 //!< 0 is the driverlib build ID for the cc26x0 driverlib. -#define DRIVERLIB_BUILD_CC13X0 1 //!< 1 is the driverlib build ID for the cc13x0 driverlib. -#define DRIVERLIB_BUILD_CC26X1 2 //!< 2 is the driverlib build ID for the cc26x1 driverlib. -#define DRIVERLIB_BUILD_CC26X0R2 3 //!< 3 is the driverlib build ID for the cc26x0r2 driverlib. +#define DRIVERLIB_BUILD_CC26X0 0 //!< 0 is the driverlib build ID for the cc26x0 driverlib. +#define DRIVERLIB_BUILD_CC13X0 1 //!< 1 is the driverlib build ID for the cc13x0 driverlib. +#define DRIVERLIB_BUILD_CC26X1 2 //!< 2 is the driverlib build ID for the cc26x1 driverlib. +#define DRIVERLIB_BUILD_CC26X0R2 3 //!< 3 is the driverlib build ID for the cc26x0r2 driverlib. #define DRIVERLIB_BUILD_CC13X2_CC26X2 4 //!< 4 is the driverlib build ID for the cc13x2_cc26x2 driverlib. //***************************************************************************** @@ -403,7 +402,7 @@ extern ChipFamily_t ChipInfo_GetChipFamily( void ); //! This driverlib build identifier can be useful for compile time checking/optimization (supporting C preprocessor expressions). // //***************************************************************************** -#define THIS_DRIVERLIB_BUILD DRIVERLIB_BUILD_CC13X2_CC26X2 +#define THIS_DRIVERLIB_BUILD DRIVERLIB_BUILD_CC13X2_CC26X2 //***************************************************************************** // @@ -414,9 +413,9 @@ extern ChipFamily_t ChipInfo_GetChipFamily( void ); // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_ChipFamilyIs_CC13x0( void ) +ChipInfo_ChipFamilyIs_CC13x0(void) { - return ( ChipInfo_GetChipFamily() == FAMILY_CC13x0 ); + return (ChipInfo_GetChipFamily() == FAMILY_CC13x0); } //***************************************************************************** @@ -428,9 +427,9 @@ ChipInfo_ChipFamilyIs_CC13x0( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_ChipFamilyIs_CC26x0( void ) +ChipInfo_ChipFamilyIs_CC26x0(void) { - return ( ChipInfo_GetChipFamily() == FAMILY_CC26x0 ); + return (ChipInfo_GetChipFamily() == FAMILY_CC26x0); } //***************************************************************************** @@ -442,9 +441,9 @@ ChipInfo_ChipFamilyIs_CC26x0( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_ChipFamilyIs_CC26x0R2( void ) +ChipInfo_ChipFamilyIs_CC26x0R2(void) { - return ( ChipInfo_GetChipFamily() == FAMILY_CC26x0R2 ); + return (ChipInfo_GetChipFamily() == FAMILY_CC26x0R2); } //***************************************************************************** @@ -456,9 +455,9 @@ ChipInfo_ChipFamilyIs_CC26x0R2( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_ChipFamilyIs_CC26x1( void ) +ChipInfo_ChipFamilyIs_CC26x1(void) { - return ( ChipInfo_GetChipFamily() == FAMILY_CC26x1 ); + return (ChipInfo_GetChipFamily() == FAMILY_CC26x1); } //***************************************************************************** @@ -470,9 +469,9 @@ ChipInfo_ChipFamilyIs_CC26x1( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_ChipFamilyIs_CC13x2_CC26x2( void ) +ChipInfo_ChipFamilyIs_CC13x2_CC26x2(void) { - return ( ChipInfo_GetChipFamily() == FAMILY_CC13x2_CC26x2 ); + return (ChipInfo_GetChipFamily() == FAMILY_CC13x2_CC26x2); } //***************************************************************************** @@ -482,14 +481,14 @@ ChipInfo_ChipFamilyIs_CC13x2_CC26x2( void ) //***************************************************************************** typedef enum { - HWREV_Unknown = -1, //!< -1 means that the chip's HW revision is unknown. - HWREV_1_0 = 10, //!< 10 means that the chip's HW revision is 1.0 - HWREV_1_1 = 11, //!< 11 means that the chip's HW revision is 1.1 - HWREV_2_0 = 20, //!< 20 means that the chip's HW revision is 2.0 - HWREV_2_1 = 21, //!< 21 means that the chip's HW revision is 2.1 - HWREV_2_2 = 22, //!< 22 means that the chip's HW revision is 2.2 - HWREV_2_3 = 23, //!< 23 means that the chip's HW revision is 2.3 - HWREV_2_4 = 24 //!< 24 means that the chip's HW revision is 2.4 + HWREV_Unknown = -1, //!< -1 means that the chip's HW revision is unknown. + HWREV_1_0 = 10, //!< 10 means that the chip's HW revision is 1.0 + HWREV_1_1 = 11, //!< 11 means that the chip's HW revision is 1.1 + HWREV_2_0 = 20, //!< 20 means that the chip's HW revision is 2.0 + HWREV_2_1 = 21, //!< 21 means that the chip's HW revision is 2.1 + HWREV_2_2 = 22, //!< 22 means that the chip's HW revision is 2.2 + HWREV_2_3 = 23, //!< 23 means that the chip's HW revision is 2.3 + HWREV_2_4 = 24 //!< 24 means that the chip's HW revision is 2.4 } HwRevision_t; //***************************************************************************** @@ -500,7 +499,7 @@ typedef enum //! Returns \ref HwRevision_t // //***************************************************************************** -extern HwRevision_t ChipInfo_GetHwRevision( void ); +extern HwRevision_t ChipInfo_GetHwRevision(void); //***************************************************************************** // @@ -511,9 +510,9 @@ extern HwRevision_t ChipInfo_GetHwRevision( void ); // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_1_0( void ) +ChipInfo_HwRevisionIs_1_0(void) { - return ( ChipInfo_GetHwRevision() == HWREV_1_0 ); + return (ChipInfo_GetHwRevision() == HWREV_1_0); } //***************************************************************************** @@ -525,9 +524,9 @@ ChipInfo_HwRevisionIs_1_0( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_2_0( void ) +ChipInfo_HwRevisionIs_2_0(void) { - return ( ChipInfo_GetHwRevision() == HWREV_2_0 ); + return (ChipInfo_GetHwRevision() == HWREV_2_0); } //***************************************************************************** @@ -539,9 +538,9 @@ ChipInfo_HwRevisionIs_2_0( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_GTEQ_2_0( void ) +ChipInfo_HwRevisionIs_GTEQ_2_0(void) { - return ( ChipInfo_GetHwRevision() >= HWREV_2_0 ); + return (ChipInfo_GetHwRevision() >= HWREV_2_0); } //***************************************************************************** @@ -553,9 +552,9 @@ ChipInfo_HwRevisionIs_GTEQ_2_0( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_2_1( void ) +ChipInfo_HwRevisionIs_2_1(void) { - return ( ChipInfo_GetHwRevision() == HWREV_2_1 ); + return (ChipInfo_GetHwRevision() == HWREV_2_1); } //***************************************************************************** @@ -567,9 +566,9 @@ ChipInfo_HwRevisionIs_2_1( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_GTEQ_2_1( void ) +ChipInfo_HwRevisionIs_GTEQ_2_1(void) { - return ( ChipInfo_GetHwRevision() >= HWREV_2_1 ); + return (ChipInfo_GetHwRevision() >= HWREV_2_1); } //***************************************************************************** @@ -581,9 +580,9 @@ ChipInfo_HwRevisionIs_GTEQ_2_1( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_2_2( void ) +ChipInfo_HwRevisionIs_2_2(void) { - return ( ChipInfo_GetHwRevision() == HWREV_2_2 ); + return (ChipInfo_GetHwRevision() == HWREV_2_2); } //***************************************************************************** @@ -595,9 +594,9 @@ ChipInfo_HwRevisionIs_2_2( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_GTEQ_2_2( void ) +ChipInfo_HwRevisionIs_GTEQ_2_2(void) { - return ( ChipInfo_GetHwRevision() >= HWREV_2_2 ); + return (ChipInfo_GetHwRevision() >= HWREV_2_2); } //***************************************************************************** @@ -609,9 +608,9 @@ ChipInfo_HwRevisionIs_GTEQ_2_2( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_GTEQ_2_3( void ) +ChipInfo_HwRevisionIs_GTEQ_2_3(void) { - return ( ChipInfo_GetHwRevision() >= HWREV_2_3 ); + return (ChipInfo_GetHwRevision() >= HWREV_2_3); } //***************************************************************************** @@ -623,9 +622,9 @@ ChipInfo_HwRevisionIs_GTEQ_2_3( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_GTEQ_2_4( void ) +ChipInfo_HwRevisionIs_GTEQ_2_4(void) { - return ( ChipInfo_GetHwRevision() >= HWREV_2_4 ); + return (ChipInfo_GetHwRevision() >= HWREV_2_4); } //***************************************************************************** @@ -635,7 +634,7 @@ ChipInfo_HwRevisionIs_GTEQ_2_4( void ) //! \return None // //***************************************************************************** -extern void ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated( void ); +extern void ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated(void); //***************************************************************************** // @@ -646,27 +645,27 @@ extern void ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated( void #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_ChipInfo_GetSupportedProtocol_BV -#undef ChipInfo_GetSupportedProtocol_BV +#undef ChipInfo_GetSupportedProtocol_BV #define ChipInfo_GetSupportedProtocol_BV ROM_ChipInfo_GetSupportedProtocol_BV #endif #ifdef ROM_ChipInfo_GetPackageType -#undef ChipInfo_GetPackageType -#define ChipInfo_GetPackageType ROM_ChipInfo_GetPackageType +#undef ChipInfo_GetPackageType +#define ChipInfo_GetPackageType ROM_ChipInfo_GetPackageType #endif #ifdef ROM_ChipInfo_GetChipType -#undef ChipInfo_GetChipType -#define ChipInfo_GetChipType ROM_ChipInfo_GetChipType +#undef ChipInfo_GetChipType +#define ChipInfo_GetChipType ROM_ChipInfo_GetChipType #endif #ifdef ROM_ChipInfo_GetChipFamily -#undef ChipInfo_GetChipFamily -#define ChipInfo_GetChipFamily ROM_ChipInfo_GetChipFamily +#undef ChipInfo_GetChipFamily +#define ChipInfo_GetChipFamily ROM_ChipInfo_GetChipFamily #endif #ifdef ROM_ChipInfo_GetHwRevision -#undef ChipInfo_GetHwRevision -#define ChipInfo_GetHwRevision ROM_ChipInfo_GetHwRevision +#undef ChipInfo_GetHwRevision +#define ChipInfo_GetHwRevision ROM_ChipInfo_GetHwRevision #endif #ifdef ROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated -#undef ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated +#undef ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated #define ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated ROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.h index 947687f..c039cf7 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.h @@ -1,41 +1,41 @@ /****************************************************************************** -* Filename: cpu.h -* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) -* Revision: 52111 -* -* Description: Defines and prototypes for the CPU instruction wrapper -* functions. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: cpu.h + * Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) + * Revision: 52111 + * + * Description: Defines and prototypes for the CPU instruction wrapper + * functions. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -56,15 +56,14 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_cpu_scs.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_cpu_scs.h" //***************************************************************************** // @@ -80,11 +79,11 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define CPUcpsid NOROM_CPUcpsid -#define CPUprimask NOROM_CPUprimask -#define CPUcpsie NOROM_CPUcpsie -#define CPUbasepriGet NOROM_CPUbasepriGet -#define CPUdelay NOROM_CPUdelay +#define CPUcpsid NOROM_CPUcpsid +#define CPUprimask NOROM_CPUprimask +#define CPUcpsie NOROM_CPUcpsie +#define CPUbasepriGet NOROM_CPUbasepriGet +#define CPUdelay NOROM_CPUdelay #endif //***************************************************************************** @@ -207,7 +206,7 @@ CPUwfi(void) { // Wait for the next interrupt. wfi; - bx lr + bx lr } #elif defined(__TI_COMPILER_VERSION__) __STATIC_INLINE void @@ -221,7 +220,7 @@ __STATIC_INLINE void __attribute__((always_inline)) CPUwfi(void) { // Wait for the next interrupt. - __asm volatile (" wfi\n"); + __asm volatile(" wfi\n"); } #endif @@ -254,7 +253,7 @@ CPUwfe(void) { // Wait for the next event. wfe; - bx lr + bx lr } #elif defined(__TI_COMPILER_VERSION__) __STATIC_INLINE void @@ -268,7 +267,7 @@ __STATIC_INLINE void __attribute__((always_inline)) CPUwfe(void) { // Wait for the next event. - __asm volatile (" wfe\n"); + __asm volatile(" wfe\n"); } #endif @@ -301,7 +300,7 @@ CPUsev(void) { // Send event. sev; - bx lr + bx lr } #elif defined(__TI_COMPILER_VERSION__) __STATIC_INLINE void @@ -315,11 +314,10 @@ __STATIC_INLINE void __attribute__((always_inline)) CPUsev(void) { // Send event. - __asm volatile (" sev\n"); + __asm volatile(" sev\n"); } #endif - //***************************************************************************** // //! \brief Update the interrupt priority disable level. @@ -350,8 +348,8 @@ __asm __STATIC_INLINE void CPUbasepriSet(uint32_t ui32NewBasepri) { // Set the BASEPRI register. - msr BASEPRI, r0; - bx lr + msr BASEPRI, r0; + bx lr } #elif defined(__TI_COMPILER_VERSION__) __STATIC_INLINE void @@ -363,15 +361,14 @@ CPUbasepriSet(uint32_t ui32NewBasepri) #else #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wattributes" -__STATIC_INLINE void __attribute__ ((naked)) +__STATIC_INLINE void __attribute__((naked)) CPUbasepriSet(uint32_t ui32NewBasepri) { // Set the BASEPRI register. - __asm volatile (" msr BASEPRI, %0\n" - " bx lr\n" - : /* No output */ - : "r" (ui32NewBasepri) - ); + __asm volatile(" msr BASEPRI, %0\n" + " bx lr\n" + : /* No output */ + : "r"(ui32NewBasepri)); } #pragma GCC diagnostic pop #endif @@ -393,9 +390,9 @@ CPUbasepriSet(uint32_t ui32NewBasepri) // //***************************************************************************** __STATIC_INLINE void -CPU_WriteBufferDisable( void ) +CPU_WriteBufferDisable(void) { - HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 1; + HWREGBITW(CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN) = 1; } //***************************************************************************** @@ -411,9 +408,9 @@ CPU_WriteBufferDisable( void ) // //***************************************************************************** __STATIC_INLINE void -CPU_WriteBufferEnable( void ) +CPU_WriteBufferEnable(void) { - HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 0; + HWREGBITW(CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN) = 0; } //***************************************************************************** @@ -425,24 +422,24 @@ CPU_WriteBufferEnable( void ) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_CPUcpsid -#undef CPUcpsid -#define CPUcpsid ROM_CPUcpsid +#undef CPUcpsid +#define CPUcpsid ROM_CPUcpsid #endif #ifdef ROM_CPUprimask -#undef CPUprimask -#define CPUprimask ROM_CPUprimask +#undef CPUprimask +#define CPUprimask ROM_CPUprimask #endif #ifdef ROM_CPUcpsie -#undef CPUcpsie -#define CPUcpsie ROM_CPUcpsie +#undef CPUcpsie +#define CPUcpsie ROM_CPUcpsie #endif #ifdef ROM_CPUbasepriGet -#undef CPUbasepriGet -#define CPUbasepriGet ROM_CPUbasepriGet +#undef CPUbasepriGet +#define CPUbasepriGet ROM_CPUbasepriGet #endif #ifdef ROM_CPUdelay -#undef CPUdelay -#define CPUdelay ROM_CPUdelay +#undef CPUdelay +#define CPUdelay ROM_CPUdelay #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/cpu_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/cpu_doc.h index 7f17aa3..4295c5e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/cpu_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/cpu_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: cpu_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: cpu_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup cpu_api //! @{ //! \section sec_cpu Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.h index 11760a6..4c64649 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: crypto.h -* Revised: 2018-01-12 18:46:31 +0100 (Fri, 12 Jan 2018) -* Revision: 51161 -* -* Description: AES header file. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: crypto.h + * Revised: 2018-01-12 18:46:31 +0100 (Fri, 12 Jan 2018) + * Revision: 51161 + * + * Description: AES header file. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,19 +55,18 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" #include "../inc/hw_crypto.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "cpu.h" #include "debug.h" #include "interrupt.h" -#include "cpu.h" +#include +#include //***************************************************************************** // @@ -83,19 +82,19 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define CRYPTOAesLoadKey NOROM_CRYPTOAesLoadKey -#define CRYPTOAesCbc NOROM_CRYPTOAesCbc -#define CRYPTOAesCbcStatus NOROM_CRYPTOAesCbcStatus -#define CRYPTOAesEcb NOROM_CRYPTOAesEcb -#define CRYPTOAesEcbStatus NOROM_CRYPTOAesEcbStatus -#define CRYPTOCcmAuthEncrypt NOROM_CRYPTOCcmAuthEncrypt -#define CRYPTOCcmAuthEncryptStatus NOROM_CRYPTOCcmAuthEncryptStatus -#define CRYPTOCcmAuthEncryptResultGet NOROM_CRYPTOCcmAuthEncryptResultGet -#define CRYPTOCcmInvAuthDecrypt NOROM_CRYPTOCcmInvAuthDecrypt -#define CRYPTOCcmInvAuthDecryptStatus NOROM_CRYPTOCcmInvAuthDecryptStatus +#define CRYPTOAesLoadKey NOROM_CRYPTOAesLoadKey +#define CRYPTOAesCbc NOROM_CRYPTOAesCbc +#define CRYPTOAesCbcStatus NOROM_CRYPTOAesCbcStatus +#define CRYPTOAesEcb NOROM_CRYPTOAesEcb +#define CRYPTOAesEcbStatus NOROM_CRYPTOAesEcbStatus +#define CRYPTOCcmAuthEncrypt NOROM_CRYPTOCcmAuthEncrypt +#define CRYPTOCcmAuthEncryptStatus NOROM_CRYPTOCcmAuthEncryptStatus +#define CRYPTOCcmAuthEncryptResultGet NOROM_CRYPTOCcmAuthEncryptResultGet +#define CRYPTOCcmInvAuthDecrypt NOROM_CRYPTOCcmInvAuthDecrypt +#define CRYPTOCcmInvAuthDecryptStatus NOROM_CRYPTOCcmInvAuthDecryptStatus #define CRYPTOCcmInvAuthDecryptResultGet NOROM_CRYPTOCcmInvAuthDecryptResultGet -#define CRYPTODmaEnable NOROM_CRYPTODmaEnable -#define CRYPTODmaDisable NOROM_CRYPTODmaDisable +#define CRYPTODmaEnable NOROM_CRYPTODmaEnable +#define CRYPTODmaDisable NOROM_CRYPTODmaDisable #endif //***************************************************************************** @@ -103,7 +102,7 @@ extern "C" // Length of AES Electronic Code Book (ECB) block in bytes // //***************************************************************************** -#define AES_ECB_LENGTH 16 +#define AES_ECB_LENGTH 16 //***************************************************************************** // @@ -111,24 +110,24 @@ extern "C" // as the ui32IntFlags parameter, and returned from CryptoIntStatus. // //***************************************************************************** -#define CRYPTO_DMA_IN_DONE 0x00000002 // DMA done interrupt mask -#define CRYPTO_RESULT_RDY 0x00000001 // Result ready interrupt mask -#define CRYPTO_DMA_BUS_ERR 0x80000000 // DMA Bus error -#define CRYPTO_KEY_ST_WR_ERR 0x40000000 // Key Store Write failed -#define CRYPTO_KEY_ST_RD_ERR 0x20000000 // Key Store Read failed +#define CRYPTO_DMA_IN_DONE 0x00000002 // DMA done interrupt mask +#define CRYPTO_RESULT_RDY 0x00000001 // Result ready interrupt mask +#define CRYPTO_DMA_BUS_ERR 0x80000000 // DMA Bus error +#define CRYPTO_KEY_ST_WR_ERR 0x40000000 // Key Store Write failed +#define CRYPTO_KEY_ST_RD_ERR 0x20000000 // Key Store Read failed -#define CRYPTO_IRQTYPE_LEVEL 0x00000001 // Crypto Level interrupt enabled -#define CRYPTO_IRQTYPE_PULSE 0x00000000 // Crypto pulse interrupt enabled +#define CRYPTO_IRQTYPE_LEVEL 0x00000001 // Crypto Level interrupt enabled +#define CRYPTO_IRQTYPE_PULSE 0x00000000 // Crypto pulse interrupt enabled -#define CRYPTO_DMA_CHAN0 0x00000001 // Crypto DMA Channel 0 -#define CRYPTO_DMA_CHAN1 0x00000002 // Crypto DMA Channel 1 +#define CRYPTO_DMA_CHAN0 0x00000001 // Crypto DMA Channel 0 +#define CRYPTO_DMA_CHAN1 0x00000002 // Crypto DMA Channel 1 -#define CRYPTO_AES128_ENCRYPT 0x0000000C // -#define CRYPTO_AES128_DECRYPT 0x00000008 // +#define CRYPTO_AES128_ENCRYPT 0x0000000C // +#define CRYPTO_AES128_DECRYPT 0x00000008 // -#define CRYPTO_DMA_READY 0x00000000 // DMA ready -#define CRYPTO_DMA_BSY 0x00000003 // DMA busy -#define CRYPTO_DMA_BUS_ERROR 0x00020000 // DMA encountered bus error +#define CRYPTO_DMA_READY 0x00000000 // DMA ready +#define CRYPTO_DMA_BSY 0x00000003 // DMA busy +#define CRYPTO_DMA_BUS_ERROR 0x00020000 // DMA encountered bus error //***************************************************************************** // @@ -137,25 +136,25 @@ extern "C" //***************************************************************************** // AES module return codes -#define AES_SUCCESS 0 -#define AES_KEYSTORE_READ_ERROR 1 -#define AES_KEYSTORE_WRITE_ERROR 2 -#define AES_DMA_BUS_ERROR 3 -#define CCM_AUTHENTICATION_FAILED 4 -#define AES_ECB_TEST_ERROR 8 -#define AES_NULL_ERROR 9 -#define AES_CCM_TEST_ERROR 10 -#define AES_DMA_BSY 11 +#define AES_SUCCESS 0 +#define AES_KEYSTORE_READ_ERROR 1 +#define AES_KEYSTORE_WRITE_ERROR 2 +#define AES_DMA_BUS_ERROR 3 +#define CCM_AUTHENTICATION_FAILED 4 +#define AES_ECB_TEST_ERROR 8 +#define AES_NULL_ERROR 9 +#define AES_CCM_TEST_ERROR 10 +#define AES_DMA_BSY 11 // Key store module defines -#define STATE_BLENGTH 16 // Number of bytes in State -#define KEY_BLENGTH 16 // Number of bytes in Key -#define KEY_EXP_LENGTH 176 // Nb * (Nr+1) * 4 +#define STATE_BLENGTH 16 // Number of bytes in State +#define KEY_BLENGTH 16 // Number of bytes in Key +#define KEY_EXP_LENGTH 176 // Nb * (Nr+1) * 4 -#define KEY_STORE_SIZE_128 0x00000001 -#define KEY_STORE_SIZE_192 0x00000002 -#define KEY_STORE_SIZE_256 0x00000003 -#define KEY_STORE_SIZE_BITS 0x00000003 +#define KEY_STORE_SIZE_128 0x00000001 +#define KEY_STORE_SIZE_192 0x00000002 +#define KEY_STORE_SIZE_256 0x00000003 +#define KEY_STORE_SIZE_BITS 0x00000003 //***************************************************************************** // @@ -164,36 +163,36 @@ extern "C" // are valid. // //***************************************************************************** -#define CRYPTO_KEY_AREA_0 0 -#define CRYPTO_KEY_AREA_1 1 -#define CRYPTO_KEY_AREA_2 2 -#define CRYPTO_KEY_AREA_3 3 -#define CRYPTO_KEY_AREA_4 4 -#define CRYPTO_KEY_AREA_5 5 -#define CRYPTO_KEY_AREA_6 6 -#define CRYPTO_KEY_AREA_7 7 +#define CRYPTO_KEY_AREA_0 0 +#define CRYPTO_KEY_AREA_1 1 +#define CRYPTO_KEY_AREA_2 2 +#define CRYPTO_KEY_AREA_3 3 +#define CRYPTO_KEY_AREA_4 4 +#define CRYPTO_KEY_AREA_5 5 +#define CRYPTO_KEY_AREA_6 6 +#define CRYPTO_KEY_AREA_7 7 //***************************************************************************** // // Defines for the current AES operation // //***************************************************************************** -#define CRYPTO_AES_NONE 0 -#define CRYPTO_AES_KEYL0AD 1 -#define CRYPTO_AES_ECB 2 -#define CRYPTO_AES_CCM 3 -#define CRYPTO_AES_RNG 4 -#define CRYPTO_AES_CBC 5 +#define CRYPTO_AES_NONE 0 +#define CRYPTO_AES_KEYL0AD 1 +#define CRYPTO_AES_ECB 2 +#define CRYPTO_AES_CCM 3 +#define CRYPTO_AES_RNG 4 +#define CRYPTO_AES_CBC 5 //***************************************************************************** // // Defines for the AES-CTR mode counter width // //***************************************************************************** -#define CRYPTO_AES_CTR_32 0x0 -#define CRYPTO_AES_CTR_64 0x1 -#define CRYPTO_AES_CTR_96 0x2 -#define CRYPTO_AES_CTR_128 0x3 +#define CRYPTO_AES_CTR_32 0x0 +#define CRYPTO_AES_CTR_64 0x1 +#define CRYPTO_AES_CTR_96 0x2 +#define CRYPTO_AES_CTR_128 0x3 //***************************************************************************** // @@ -457,7 +456,7 @@ extern uint32_t CRYPTOCcmAuthEncryptStatus(void); // //***************************************************************************** extern uint32_t CRYPTOCcmAuthEncryptResultGet(uint32_t ui32TagLength, - uint32_t* pui32CcmTag); + uint32_t* pui32CcmTag); //***************************************************************************** // @@ -530,9 +529,9 @@ extern uint32_t CRYPTOCcmInvAuthDecryptStatus(void); // //***************************************************************************** extern uint32_t CRYPTOCcmInvAuthDecryptResultGet(uint32_t ui32AuthLength, - uint32_t* pui32CipherText, - uint32_t ui32CipherTextLength, - uint32_t* pui32CcmTag); + uint32_t* pui32CipherText, + uint32_t ui32CipherTextLength, + uint32_t* pui32CcmTag); //***************************************************************************** // @@ -783,56 +782,56 @@ CRYPTOIntUnregister(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_CRYPTOAesLoadKey -#undef CRYPTOAesLoadKey -#define CRYPTOAesLoadKey ROM_CRYPTOAesLoadKey +#undef CRYPTOAesLoadKey +#define CRYPTOAesLoadKey ROM_CRYPTOAesLoadKey #endif #ifdef ROM_CRYPTOAesCbc -#undef CRYPTOAesCbc -#define CRYPTOAesCbc ROM_CRYPTOAesCbc +#undef CRYPTOAesCbc +#define CRYPTOAesCbc ROM_CRYPTOAesCbc #endif #ifdef ROM_CRYPTOAesCbcStatus -#undef CRYPTOAesCbcStatus -#define CRYPTOAesCbcStatus ROM_CRYPTOAesCbcStatus +#undef CRYPTOAesCbcStatus +#define CRYPTOAesCbcStatus ROM_CRYPTOAesCbcStatus #endif #ifdef ROM_CRYPTOAesEcb -#undef CRYPTOAesEcb -#define CRYPTOAesEcb ROM_CRYPTOAesEcb +#undef CRYPTOAesEcb +#define CRYPTOAesEcb ROM_CRYPTOAesEcb #endif #ifdef ROM_CRYPTOAesEcbStatus -#undef CRYPTOAesEcbStatus -#define CRYPTOAesEcbStatus ROM_CRYPTOAesEcbStatus +#undef CRYPTOAesEcbStatus +#define CRYPTOAesEcbStatus ROM_CRYPTOAesEcbStatus #endif #ifdef ROM_CRYPTOCcmAuthEncrypt -#undef CRYPTOCcmAuthEncrypt -#define CRYPTOCcmAuthEncrypt ROM_CRYPTOCcmAuthEncrypt +#undef CRYPTOCcmAuthEncrypt +#define CRYPTOCcmAuthEncrypt ROM_CRYPTOCcmAuthEncrypt #endif #ifdef ROM_CRYPTOCcmAuthEncryptStatus -#undef CRYPTOCcmAuthEncryptStatus -#define CRYPTOCcmAuthEncryptStatus ROM_CRYPTOCcmAuthEncryptStatus +#undef CRYPTOCcmAuthEncryptStatus +#define CRYPTOCcmAuthEncryptStatus ROM_CRYPTOCcmAuthEncryptStatus #endif #ifdef ROM_CRYPTOCcmAuthEncryptResultGet -#undef CRYPTOCcmAuthEncryptResultGet -#define CRYPTOCcmAuthEncryptResultGet ROM_CRYPTOCcmAuthEncryptResultGet +#undef CRYPTOCcmAuthEncryptResultGet +#define CRYPTOCcmAuthEncryptResultGet ROM_CRYPTOCcmAuthEncryptResultGet #endif #ifdef ROM_CRYPTOCcmInvAuthDecrypt -#undef CRYPTOCcmInvAuthDecrypt -#define CRYPTOCcmInvAuthDecrypt ROM_CRYPTOCcmInvAuthDecrypt +#undef CRYPTOCcmInvAuthDecrypt +#define CRYPTOCcmInvAuthDecrypt ROM_CRYPTOCcmInvAuthDecrypt #endif #ifdef ROM_CRYPTOCcmInvAuthDecryptStatus -#undef CRYPTOCcmInvAuthDecryptStatus -#define CRYPTOCcmInvAuthDecryptStatus ROM_CRYPTOCcmInvAuthDecryptStatus +#undef CRYPTOCcmInvAuthDecryptStatus +#define CRYPTOCcmInvAuthDecryptStatus ROM_CRYPTOCcmInvAuthDecryptStatus #endif #ifdef ROM_CRYPTOCcmInvAuthDecryptResultGet -#undef CRYPTOCcmInvAuthDecryptResultGet +#undef CRYPTOCcmInvAuthDecryptResultGet #define CRYPTOCcmInvAuthDecryptResultGet ROM_CRYPTOCcmInvAuthDecryptResultGet #endif #ifdef ROM_CRYPTODmaEnable -#undef CRYPTODmaEnable -#define CRYPTODmaEnable ROM_CRYPTODmaEnable +#undef CRYPTODmaEnable +#define CRYPTODmaEnable ROM_CRYPTODmaEnable #endif #ifdef ROM_CRYPTODmaDisable -#undef CRYPTODmaDisable -#define CRYPTODmaDisable ROM_CRYPTODmaDisable +#undef CRYPTODmaDisable +#define CRYPTODmaDisable ROM_CRYPTODmaDisable #endif #endif @@ -845,7 +844,7 @@ CRYPTOIntUnregister(void) } #endif -#endif // __CRYPTO_H__ +#endif // __CRYPTO_H__ //***************************************************************************** // diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.h index 6c45a78..b7d877e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: ddi.h -* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) -* Revision: 52111 -* -* Description: Defines and prototypes for the DDI master interface. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: ddi.h + * Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) + * Revision: 52111 + * + * Description: Defines and prototypes for the DDI master interface. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,18 +55,17 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aux_smph.h" +#include "../inc/hw_ddi.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "cpu.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ddi.h" -#include "../inc/hw_aux_smph.h" -#include "debug.h" -#include "cpu.h" //***************************************************************************** // @@ -82,11 +81,11 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define DDI32RegWrite NOROM_DDI32RegWrite -#define DDI16BitWrite NOROM_DDI16BitWrite -#define DDI16BitfieldWrite NOROM_DDI16BitfieldWrite -#define DDI16BitRead NOROM_DDI16BitRead -#define DDI16BitfieldRead NOROM_DDI16BitfieldRead +#define DDI32RegWrite NOROM_DDI32RegWrite +#define DDI16BitWrite NOROM_DDI16BitWrite +#define DDI16BitfieldWrite NOROM_DDI16BitfieldWrite +#define DDI16BitRead NOROM_DDI16BitRead +#define DDI16BitfieldRead NOROM_DDI16BitfieldRead #endif //***************************************************************************** @@ -94,17 +93,16 @@ extern "C" // Number of register in the DDI slave // //***************************************************************************** -#define DDI_SLAVE_REGS 64 - +#define DDI_SLAVE_REGS 64 //***************************************************************************** // // Defines that is used to control the ADI slave and master // //***************************************************************************** -#define DDI_PROTECT 0x00000080 -#define DDI_ACK 0x00000001 -#define DDI_SYNC 0x00000000 +#define DDI_PROTECT 0x00000080 +#define DDI_ACK 0x00000001 +#define DDI_SYNC 0x00000000 //***************************************************************************** // @@ -112,7 +110,6 @@ extern "C" // //***************************************************************************** - //***************************************************************************** // // Helper functions @@ -143,7 +140,6 @@ DDIBaseValid(uint32_t ui32Base) } #endif - //***************************************************************************** // //! \brief Read the value in a 32 bit register. @@ -361,7 +357,6 @@ extern void DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) extern void DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32WrData); - //***************************************************************************** // //! \brief Write a bit field via the DDI using 16-bit maskable write. @@ -421,24 +416,24 @@ extern uint16_t DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg, #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_DDI32RegWrite -#undef DDI32RegWrite -#define DDI32RegWrite ROM_DDI32RegWrite +#undef DDI32RegWrite +#define DDI32RegWrite ROM_DDI32RegWrite #endif #ifdef ROM_DDI16BitWrite -#undef DDI16BitWrite -#define DDI16BitWrite ROM_DDI16BitWrite +#undef DDI16BitWrite +#define DDI16BitWrite ROM_DDI16BitWrite #endif #ifdef ROM_DDI16BitfieldWrite -#undef DDI16BitfieldWrite -#define DDI16BitfieldWrite ROM_DDI16BitfieldWrite +#undef DDI16BitfieldWrite +#define DDI16BitfieldWrite ROM_DDI16BitfieldWrite #endif #ifdef ROM_DDI16BitRead -#undef DDI16BitRead -#define DDI16BitRead ROM_DDI16BitRead +#undef DDI16BitRead +#define DDI16BitRead ROM_DDI16BitRead #endif #ifdef ROM_DDI16BitfieldRead -#undef DDI16BitfieldRead -#define DDI16BitfieldRead ROM_DDI16BitfieldRead +#undef DDI16BitfieldRead +#define DDI16BitfieldRead ROM_DDI16BitfieldRead #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ddi_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ddi_doc.h index 86d5c15..7fd4780 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ddi_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ddi_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: ddi_doc.h -* Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016) -* Revision: 47080 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: ddi_doc.h + * Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016) + * Revision: 47080 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup ddi_api //! @{ //! \section sec_ddi Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/debug.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/debug.h index cbd4527..0f5bbcb 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/debug.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/debug.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: debug.h -* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) -* Revision: 48852 -* -* Description: Macros for assisting debug of the driver library. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: debug.h + * Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) + * Revision: 48852 + * + * Description: Macros for assisting debug of the driver library. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -62,8 +62,9 @@ extern void __error__(char* pcFilename, uint32_t ui32Line); // //***************************************************************************** #ifdef DRIVERLIB_DEBUG -#define ASSERT(expr) { \ - if(!(expr)) \ +#define ASSERT(expr) \ + { \ + if (!(expr)) \ { \ __error__(__FILE__, __LINE__); \ } \ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.h index b7a0434..2518c30 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.h @@ -1,41 +1,41 @@ /****************************************************************************** -* Filename: driverlib_release.h -* Revised: $Date: 2015-07-16 12:12:04 +0200 (Thu, 16 Jul 2015) $ -* Revision: $Revision: 44151 $ -* -* Description: Provides macros for ensuring that a specfic release of -* DriverLib is used. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: driverlib_release.h + * Revised: $Date: 2015-07-16 12:12:04 +0200 (Thu, 16 Jul 2015) $ + * Revision: $Revision: 44151 $ + * + * Description: Provides macros for ensuring that a specfic release of + * DriverLib is used. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -49,24 +49,16 @@ #ifndef __DRIVERLIB_RELEASE_H__ #define __DRIVERLIB_RELEASE_H__ - #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include - - - /// DriverLib release group number -#define DRIVERLIB_RELEASE_GROUP 0 +#define DRIVERLIB_RELEASE_GROUP 0 /// DriverLib release build number -#define DRIVERLIB_RELEASE_BUILD 54539 - - - +#define DRIVERLIB_RELEASE_BUILD 54539 //***************************************************************************** // @@ -85,9 +77,6 @@ extern "C" /// External declaration of the DriverLib release locking object extern DRIVERLIB_DECLARE_RELEASE(0, 54539); - - - //***************************************************************************** // //! This macro shall be called once from within a function of a precompiled @@ -112,9 +101,6 @@ extern DRIVERLIB_DECLARE_RELEASE(0, 54539); #define DRIVERLIB_ASSERT_RELEASE(group, build) \ (driverlib_release_##group##_##build) - - - //***************************************************************************** // //! This macro shall be called once from within a function of a precompiled @@ -137,16 +123,12 @@ extern DRIVERLIB_DECLARE_RELEASE(0, 54539); #define DRIVERLIB_ASSERT_CURR_RELEASE() \ DRIVERLIB_ASSERT_RELEASE(0, 54539) - - - #ifdef __cplusplus } #endif #endif // __DRIVERLIB_RELEASE_H__ - //***************************************************************************** // //! Close the Doxygen group. diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/event.h index f8f0c21..2df0cfa 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/event.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/event.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: event.h -* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) -* Revision: 47179 -* -* Description: Defines and prototypes for the Event Handler. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: event.h + * Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) + * Revision: 47179 + * + * Description: Defines and prototypes for the Event Handler. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,17 +55,15 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_event.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_event.h" -#include "debug.h" - //***************************************************************************** // @@ -142,28 +140,28 @@ __STATIC_INLINE void EventRegister(uint32_t ui32EventSubscriber, uint32_t ui32EventSource) { // Check the arguments. - ASSERT(( ui32EventSubscriber == EVENT_O_CPUIRQSEL30 ) || - ( ui32EventSubscriber == EVENT_O_RFCSEL9 ) || - ( ui32EventSubscriber == EVENT_O_GPT0ACAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT0BCAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT1ACAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT1BCAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT2ACAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT2BCAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT3ACAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT3BCAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH9SSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH9BSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH10SSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH10BSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH11SSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH11BSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH12SSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH12BSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH14BSEL ) || - ( ui32EventSubscriber == EVENT_O_AUXSEL0 ) || - ( ui32EventSubscriber == EVENT_O_I2SSTMPSEL0 ) || - ( ui32EventSubscriber == EVENT_O_FRZSEL0 ) ); + ASSERT((ui32EventSubscriber == EVENT_O_CPUIRQSEL30) || + (ui32EventSubscriber == EVENT_O_RFCSEL9) || + (ui32EventSubscriber == EVENT_O_GPT0ACAPTSEL) || + (ui32EventSubscriber == EVENT_O_GPT0BCAPTSEL) || + (ui32EventSubscriber == EVENT_O_GPT1ACAPTSEL) || + (ui32EventSubscriber == EVENT_O_GPT1BCAPTSEL) || + (ui32EventSubscriber == EVENT_O_GPT2ACAPTSEL) || + (ui32EventSubscriber == EVENT_O_GPT2BCAPTSEL) || + (ui32EventSubscriber == EVENT_O_GPT3ACAPTSEL) || + (ui32EventSubscriber == EVENT_O_GPT3BCAPTSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH9SSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH9BSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH10SSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH10BSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH11SSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH11BSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH12SSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH12BSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH14BSEL) || + (ui32EventSubscriber == EVENT_O_AUXSEL0) || + (ui32EventSubscriber == EVENT_O_I2SSTMPSEL0) || + (ui32EventSubscriber == EVENT_O_FRZSEL0)); // Map the event source to the event subscriber HWREG(EVENT_BASE + ui32EventSubscriber) = ui32EventSource; @@ -193,7 +191,7 @@ __STATIC_INLINE void EventSwEventSet(uint32_t ui32SwEvent) { // Check the arguments. - ASSERT( ui32SwEvent <= 3 ); + ASSERT(ui32SwEvent <= 3); // Each software event is byte accessible HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent) = 1; @@ -216,7 +214,7 @@ __STATIC_INLINE void EventSwEventClear(uint32_t ui32SwEvent) { // Check the arguments. - ASSERT( ui32SwEvent <= 3 ); + ASSERT(ui32SwEvent <= 3); // Each software event is byte accessible HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent) = 0; @@ -241,10 +239,10 @@ __STATIC_INLINE uint32_t EventSwEventGet(uint32_t ui32SwEvent) { // Check the arguments. - ASSERT( ui32SwEvent <= 3 ); + ASSERT(ui32SwEvent <= 3); // Each software event is byte accessible - return ( HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent)); + return (HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent)); } //***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/event_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/event_doc.h index a17b238..a410558 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/event_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/event_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: event_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: event_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup event_api //! @{ //! \section sec_event Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/flash.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/flash.h index 8086c17..dca2330 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/flash.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/flash.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: flash.h -* Revised: 2017-11-02 16:09:32 +0100 (Thu, 02 Nov 2017) -* Revision: 50166 -* -* Description: Defines and prototypes for the Flash driver. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: flash.h + * Revised: 2017-11-02 16:09:32 +0100 (Thu, 02 Nov 2017) + * Revision: 50166 + * + * Description: Defines and prototypes for the Flash driver. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,20 +55,19 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_flash.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" #include "../inc/hw_aon_pmctl.h" #include "../inc/hw_fcfg1.h" -#include "interrupt.h" +#include "../inc/hw_flash.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "debug.h" +#include "interrupt.h" +#include +#include //***************************************************************************** // @@ -84,15 +83,15 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define FlashPowerModeSet NOROM_FlashPowerModeSet -#define FlashPowerModeGet NOROM_FlashPowerModeGet -#define FlashProtectionSet NOROM_FlashProtectionSet -#define FlashProtectionGet NOROM_FlashProtectionGet -#define FlashProtectionSave NOROM_FlashProtectionSave -#define FlashSectorErase NOROM_FlashSectorErase -#define FlashProgram NOROM_FlashProgram -#define FlashEfuseReadRow NOROM_FlashEfuseReadRow -#define FlashDisableSectorsForWrite NOROM_FlashDisableSectorsForWrite +#define FlashPowerModeSet NOROM_FlashPowerModeSet +#define FlashPowerModeGet NOROM_FlashPowerModeGet +#define FlashProtectionSet NOROM_FlashProtectionSet +#define FlashProtectionGet NOROM_FlashProtectionGet +#define FlashProtectionSave NOROM_FlashProtectionSave +#define FlashSectorErase NOROM_FlashSectorErase +#define FlashProgram NOROM_FlashProgram +#define FlashEfuseReadRow NOROM_FlashEfuseReadRow +#define FlashDisableSectorsForWrite NOROM_FlashDisableSectorsForWrite #endif //***************************************************************************** @@ -100,12 +99,12 @@ extern "C" // Values that can be returned from the API functions // //***************************************************************************** -#define FAPI_STATUS_SUCCESS 0x00000000 // Function completed successfully -#define FAPI_STATUS_FSM_BUSY 0x00000001 // FSM is Busy -#define FAPI_STATUS_FSM_READY 0x00000002 // FSM is Ready +#define FAPI_STATUS_SUCCESS 0x00000000 // Function completed successfully +#define FAPI_STATUS_FSM_BUSY 0x00000001 // FSM is Busy +#define FAPI_STATUS_FSM_READY 0x00000002 // FSM is Ready #define FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH \ - 0x00000003 // Incorrect parameter value -#define FAPI_STATUS_FSM_ERROR 0x00000004 // Operation failed + 0x00000003 // Incorrect parameter value +#define FAPI_STATUS_FSM_ERROR 0x00000004 // Operation failed //***************************************************************************** // @@ -113,16 +112,16 @@ extern "C" // returned from FlashIntStatus(). // //***************************************************************************** -#define FLASH_INT_FSM_DONE 0x00400000 // FSM Done Interrupt Mask -#define FLASH_INT_RV 0x00010000 // Read Verify error Interrupt Mask +#define FLASH_INT_FSM_DONE 0x00400000 // FSM Done Interrupt Mask +#define FLASH_INT_RV 0x00010000 // Read Verify error Interrupt Mask //***************************************************************************** // // Values passed to FlashSetPowerMode() and returned from FlashGetPowerMode(). // //***************************************************************************** -#define FLASH_PWR_ACTIVE_MODE 0x00000000 -#define FLASH_PWR_OFF_MODE 0x00000001 +#define FLASH_PWR_ACTIVE_MODE 0x00000000 +#define FLASH_PWR_OFF_MODE 0x00000001 #define FLASH_PWR_DEEP_STDBY_MODE \ 0x00000002 @@ -131,8 +130,8 @@ extern "C" // Values passed to FlashSetProtection() and returned from FlashGetProtection(). // //***************************************************************************** -#define FLASH_NO_PROTECT 0x00000000 // Sector not protected -#define FLASH_WRITE_PROTECT 0x00000001 // Sector erase and program +#define FLASH_NO_PROTECT 0x00000000 // Sector not protected +#define FLASH_WRITE_PROTECT 0x00000001 // Sector erase and program // protected //***************************************************************************** @@ -140,21 +139,21 @@ extern "C" // Define used by the flash programming and erase functions // //***************************************************************************** -#define ADDR_OFFSET (0x1F800000 - FLASHMEM_BASE) +#define ADDR_OFFSET (0x1F800000 - FLASHMEM_BASE) //***************************************************************************** // // Define used for access to factory configuration area. // //***************************************************************************** -#define FCFG1_OFFSET 0x1000 +#define FCFG1_OFFSET 0x1000 //***************************************************************************** // // Define for the clock frequency input to the flash module in number of MHz // //***************************************************************************** -#define FLASH_MODULE_CLK_FREQ 48 +#define FLASH_MODULE_CLK_FREQ 48 //***************************************************************************** // @@ -163,16 +162,16 @@ extern "C" //***************************************************************************** typedef enum { - FAPI_PROGRAM_DATA = 0x0002, //!< Program data. - FAPI_ERASE_SECTOR = 0x0006, //!< Erase sector. - FAPI_ERASE_BANK = 0x0008, //!< Erase bank. + FAPI_PROGRAM_DATA = 0x0002, //!< Program data. + FAPI_ERASE_SECTOR = 0x0006, //!< Erase sector. + FAPI_ERASE_BANK = 0x0008, //!< Erase bank. FAPI_VALIDATE_SECTOR = 0x000E, //!< Validate sector. - FAPI_CLEAR_STATUS = 0x0010, //!< Clear status. - FAPI_PROGRAM_RESUME = 0x0014, //!< Program resume. - FAPI_ERASE_RESUME = 0x0016, //!< Erase resume. - FAPI_CLEAR_MORE = 0x0018, //!< Clear more. - FAPI_PROGRAM_SECTOR = 0x0020, //!< Program sector. - FAPI_ERASE_OTP = 0x0030 //!< Erase OTP. + FAPI_CLEAR_STATUS = 0x0010, //!< Clear status. + FAPI_PROGRAM_RESUME = 0x0014, //!< Program resume. + FAPI_ERASE_RESUME = 0x0016, //!< Erase resume. + FAPI_CLEAR_MORE = 0x0018, //!< Clear more. + FAPI_PROGRAM_SECTOR = 0x0020, //!< Program sector. + FAPI_ERASE_OTP = 0x0030 //!< Erase OTP. } tFlashStateCommandsType; //***************************************************************************** @@ -180,39 +179,39 @@ typedef enum // Defines for values written to the FLASH_O_FSM_WR_ENA register // //***************************************************************************** -#define FSM_REG_WRT_ENABLE 5 -#define FSM_REG_WRT_DISABLE 2 +#define FSM_REG_WRT_ENABLE 5 +#define FSM_REG_WRT_DISABLE 2 //***************************************************************************** // // Defines for the bank power mode field the FLASH_O_FBFALLBACK register // //***************************************************************************** -#define FBFALLBACK_SLEEP 0 -#define FBFALLBACK_DEEP_STDBY 1 -#define FBFALLBACK_ACTIVE 3 +#define FBFALLBACK_SLEEP 0 +#define FBFALLBACK_DEEP_STDBY 1 +#define FBFALLBACK_ACTIVE 3 //***************************************************************************** // // Defines for the bank grace period and pump grace period // //***************************************************************************** -#define FLASH_BAGP 0x14 -#define FLASH_PAGP 0x14 +#define FLASH_BAGP 0x14 +#define FLASH_PAGP 0x14 //***************************************************************************** // // Defines used by the FlashProgramPattern() function // //***************************************************************************** -#define PATTERN_BITS 0x20 // No of bits in data pattern to program +#define PATTERN_BITS 0x20 // No of bits in data pattern to program //***************************************************************************** // // Defines for the FW flag bits in the FLASH_O_FWFLAG register // //***************************************************************************** -#define FW_WRT_TRIMMED 0x00000001 +#define FW_WRT_TRIMMED 0x00000001 //***************************************************************************** // @@ -220,21 +219,21 @@ typedef enum // //***************************************************************************** typedef volatile uint8_t tFwpWriteByte; -#define FWPWRITE_BYTE_ADDRESS ((tFwpWriteByte *)((FLASH_BASE + FLASH_O_FWPWRITE0))) +#define FWPWRITE_BYTE_ADDRESS ((tFwpWriteByte*)((FLASH_BASE + FLASH_O_FWPWRITE0))) //***************************************************************************** // // Define for efuse instruction // //***************************************************************************** -#define DUMPWORD_INSTR 0x04 +#define DUMPWORD_INSTR 0x04 //***************************************************************************** // // Define for FSM command execution // //***************************************************************************** -#define FLASH_CMD_EXEC 0x15 +#define FLASH_CMD_EXEC 0x15 //***************************************************************************** // @@ -671,7 +670,6 @@ FlashIntClear(uint32_t ui32IntFlags) //***************************************************************************** extern uint32_t FlashSectorErase(uint32_t ui32SectorAddress); - //***************************************************************************** // //! \brief Programs unprotected flash sectors in the main bank. @@ -750,7 +748,6 @@ extern bool FlashEfuseReadRow(uint32_t* pui32EfuseData, //***************************************************************************** extern void FlashDisableSectorsForWrite(void); - //***************************************************************************** // // Support for DriverLib in ROM: @@ -760,40 +757,40 @@ extern void FlashDisableSectorsForWrite(void); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_FlashPowerModeSet -#undef FlashPowerModeSet -#define FlashPowerModeSet ROM_FlashPowerModeSet +#undef FlashPowerModeSet +#define FlashPowerModeSet ROM_FlashPowerModeSet #endif #ifdef ROM_FlashPowerModeGet -#undef FlashPowerModeGet -#define FlashPowerModeGet ROM_FlashPowerModeGet +#undef FlashPowerModeGet +#define FlashPowerModeGet ROM_FlashPowerModeGet #endif #ifdef ROM_FlashProtectionSet -#undef FlashProtectionSet -#define FlashProtectionSet ROM_FlashProtectionSet +#undef FlashProtectionSet +#define FlashProtectionSet ROM_FlashProtectionSet #endif #ifdef ROM_FlashProtectionGet -#undef FlashProtectionGet -#define FlashProtectionGet ROM_FlashProtectionGet +#undef FlashProtectionGet +#define FlashProtectionGet ROM_FlashProtectionGet #endif #ifdef ROM_FlashProtectionSave -#undef FlashProtectionSave -#define FlashProtectionSave ROM_FlashProtectionSave +#undef FlashProtectionSave +#define FlashProtectionSave ROM_FlashProtectionSave #endif #ifdef ROM_FlashSectorErase -#undef FlashSectorErase -#define FlashSectorErase ROM_FlashSectorErase +#undef FlashSectorErase +#define FlashSectorErase ROM_FlashSectorErase #endif #ifdef ROM_FlashProgram -#undef FlashProgram -#define FlashProgram ROM_FlashProgram +#undef FlashProgram +#define FlashProgram ROM_FlashProgram #endif #ifdef ROM_FlashEfuseReadRow -#undef FlashEfuseReadRow -#define FlashEfuseReadRow ROM_FlashEfuseReadRow +#undef FlashEfuseReadRow +#define FlashEfuseReadRow ROM_FlashEfuseReadRow #endif #ifdef ROM_FlashDisableSectorsForWrite -#undef FlashDisableSectorsForWrite -#define FlashDisableSectorsForWrite ROM_FlashDisableSectorsForWrite +#undef FlashDisableSectorsForWrite +#define FlashDisableSectorsForWrite ROM_FlashDisableSectorsForWrite #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.h index ffc16ef..f36f851 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: gpio.h -* Revised: 2018-05-02 11:11:40 +0200 (Wed, 02 May 2018) -* Revision: 51951 -* -* Description: Defines and prototypes for the GPIO. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: gpio.h + * Revised: 2018-05-02 11:11:40 +0200 (Wed, 02 May 2018) + * Revision: 51951 + * + * Description: Defines and prototypes for the GPIO. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,15 +55,14 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" #include "../inc/hw_gpio.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "debug.h" +#include //***************************************************************************** // @@ -75,29 +74,28 @@ extern "C" #include "chipinfo.h" static bool -dioNumberLegal( uint32_t dioNumber ) +dioNumberLegal(uint32_t dioNumber) { uint32_t ioCount = - (( HWREG( FCFG1_BASE + FCFG1_O_IOCONF ) & - FCFG1_IOCONF_GPIO_CNT_M ) >> - FCFG1_IOCONF_GPIO_CNT_S ) ; + ((HWREG(FCFG1_BASE + FCFG1_O_IOCONF) & + FCFG1_IOCONF_GPIO_CNT_M) >> + FCFG1_IOCONF_GPIO_CNT_S); // CC13x2 + CC26x2 - if ( ChipInfo_ChipFamilyIs_CC13x2_CC26x2() ) + if (ChipInfo_ChipFamilyIs_CC13x2_CC26x2()) { - return ( (dioNumber >= (31 - ioCount)) && (dioNumber < 31) ) + return ((dioNumber >= (31 - ioCount)) && (dioNumber < 31)) } // Special handling of CC13x0 7x7, where IO_CNT = 30 and legal range is 1..30 // for all other chips legal range is 0..(dioNumber-1) - else if (( ioCount == 30 ) && ChipInfo_ChipFamilyIs_CC13x0() ) + else if ((ioCount == 30) && ChipInfo_ChipFamilyIs_CC13x0()) { - return (( dioNumber > 0 ) && ( dioNumber <= ioCount )); + return ((dioNumber > 0) && (dioNumber <= ioCount)); } else { - return ( dioNumber < ioCount ); + return (dioNumber < ioCount); } - } #endif @@ -106,39 +104,39 @@ dioNumberLegal( uint32_t dioNumber ) // The following values define the bit field for the GPIO DIOs. // //***************************************************************************** -#define GPIO_DIO_0_MASK 0x00000001 // GPIO DIO 0 mask -#define GPIO_DIO_1_MASK 0x00000002 // GPIO DIO 1 mask -#define GPIO_DIO_2_MASK 0x00000004 // GPIO DIO 2 mask -#define GPIO_DIO_3_MASK 0x00000008 // GPIO DIO 3 mask -#define GPIO_DIO_4_MASK 0x00000010 // GPIO DIO 4 mask -#define GPIO_DIO_5_MASK 0x00000020 // GPIO DIO 5 mask -#define GPIO_DIO_6_MASK 0x00000040 // GPIO DIO 6 mask -#define GPIO_DIO_7_MASK 0x00000080 // GPIO DIO 7 mask -#define GPIO_DIO_8_MASK 0x00000100 // GPIO DIO 8 mask -#define GPIO_DIO_9_MASK 0x00000200 // GPIO DIO 9 mask -#define GPIO_DIO_10_MASK 0x00000400 // GPIO DIO 10 mask -#define GPIO_DIO_11_MASK 0x00000800 // GPIO DIO 11 mask -#define GPIO_DIO_12_MASK 0x00001000 // GPIO DIO 12 mask -#define GPIO_DIO_13_MASK 0x00002000 // GPIO DIO 13 mask -#define GPIO_DIO_14_MASK 0x00004000 // GPIO DIO 14 mask -#define GPIO_DIO_15_MASK 0x00008000 // GPIO DIO 15 mask -#define GPIO_DIO_16_MASK 0x00010000 // GPIO DIO 16 mask -#define GPIO_DIO_17_MASK 0x00020000 // GPIO DIO 17 mask -#define GPIO_DIO_18_MASK 0x00040000 // GPIO DIO 18 mask -#define GPIO_DIO_19_MASK 0x00080000 // GPIO DIO 19 mask -#define GPIO_DIO_20_MASK 0x00100000 // GPIO DIO 20 mask -#define GPIO_DIO_21_MASK 0x00200000 // GPIO DIO 21 mask -#define GPIO_DIO_22_MASK 0x00400000 // GPIO DIO 22 mask -#define GPIO_DIO_23_MASK 0x00800000 // GPIO DIO 23 mask -#define GPIO_DIO_24_MASK 0x01000000 // GPIO DIO 24 mask -#define GPIO_DIO_25_MASK 0x02000000 // GPIO DIO 25 mask -#define GPIO_DIO_26_MASK 0x04000000 // GPIO DIO 26 mask -#define GPIO_DIO_27_MASK 0x08000000 // GPIO DIO 27 mask -#define GPIO_DIO_28_MASK 0x10000000 // GPIO DIO 28 mask -#define GPIO_DIO_29_MASK 0x20000000 // GPIO DIO 29 mask -#define GPIO_DIO_30_MASK 0x40000000 // GPIO DIO 30 mask -#define GPIO_DIO_31_MASK 0x80000000 // GPIO DIO 31 mask -#define GPIO_DIO_ALL_MASK 0xFFFFFFFF // GPIO all DIOs mask +#define GPIO_DIO_0_MASK 0x00000001 // GPIO DIO 0 mask +#define GPIO_DIO_1_MASK 0x00000002 // GPIO DIO 1 mask +#define GPIO_DIO_2_MASK 0x00000004 // GPIO DIO 2 mask +#define GPIO_DIO_3_MASK 0x00000008 // GPIO DIO 3 mask +#define GPIO_DIO_4_MASK 0x00000010 // GPIO DIO 4 mask +#define GPIO_DIO_5_MASK 0x00000020 // GPIO DIO 5 mask +#define GPIO_DIO_6_MASK 0x00000040 // GPIO DIO 6 mask +#define GPIO_DIO_7_MASK 0x00000080 // GPIO DIO 7 mask +#define GPIO_DIO_8_MASK 0x00000100 // GPIO DIO 8 mask +#define GPIO_DIO_9_MASK 0x00000200 // GPIO DIO 9 mask +#define GPIO_DIO_10_MASK 0x00000400 // GPIO DIO 10 mask +#define GPIO_DIO_11_MASK 0x00000800 // GPIO DIO 11 mask +#define GPIO_DIO_12_MASK 0x00001000 // GPIO DIO 12 mask +#define GPIO_DIO_13_MASK 0x00002000 // GPIO DIO 13 mask +#define GPIO_DIO_14_MASK 0x00004000 // GPIO DIO 14 mask +#define GPIO_DIO_15_MASK 0x00008000 // GPIO DIO 15 mask +#define GPIO_DIO_16_MASK 0x00010000 // GPIO DIO 16 mask +#define GPIO_DIO_17_MASK 0x00020000 // GPIO DIO 17 mask +#define GPIO_DIO_18_MASK 0x00040000 // GPIO DIO 18 mask +#define GPIO_DIO_19_MASK 0x00080000 // GPIO DIO 19 mask +#define GPIO_DIO_20_MASK 0x00100000 // GPIO DIO 20 mask +#define GPIO_DIO_21_MASK 0x00200000 // GPIO DIO 21 mask +#define GPIO_DIO_22_MASK 0x00400000 // GPIO DIO 22 mask +#define GPIO_DIO_23_MASK 0x00800000 // GPIO DIO 23 mask +#define GPIO_DIO_24_MASK 0x01000000 // GPIO DIO 24 mask +#define GPIO_DIO_25_MASK 0x02000000 // GPIO DIO 25 mask +#define GPIO_DIO_26_MASK 0x04000000 // GPIO DIO 26 mask +#define GPIO_DIO_27_MASK 0x08000000 // GPIO DIO 27 mask +#define GPIO_DIO_28_MASK 0x10000000 // GPIO DIO 28 mask +#define GPIO_DIO_29_MASK 0x20000000 // GPIO DIO 29 mask +#define GPIO_DIO_30_MASK 0x40000000 // GPIO DIO 30 mask +#define GPIO_DIO_31_MASK 0x80000000 // GPIO DIO 31 mask +#define GPIO_DIO_ALL_MASK 0xFFFFFFFF // GPIO all DIOs mask //***************************************************************************** // @@ -147,8 +145,8 @@ dioNumberLegal( uint32_t dioNumber ) // GPIO_getOutputEnableDio(). // //***************************************************************************** -#define GPIO_OUTPUT_DISABLE 0x00000000 // DIO output is disabled -#define GPIO_OUTPUT_ENABLE 0x00000001 // DIO output is enabled +#define GPIO_OUTPUT_DISABLE 0x00000000 // DIO output is disabled +#define GPIO_OUTPUT_ENABLE 0x00000001 // DIO output is enabled //***************************************************************************** // @@ -168,13 +166,13 @@ dioNumberLegal( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE uint32_t -GPIO_readDio( uint32_t dioNumber ) +GPIO_readDio(uint32_t dioNumber) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); + ASSERT(dioNumberLegal(dioNumber)); // Return the input value from the specified DIO. - return (( HWREG( GPIO_BASE + GPIO_O_DIN31_0 ) >> dioNumber ) & 1 ); + return ((HWREG(GPIO_BASE + GPIO_O_DIN31_0) >> dioNumber) & 1); } //***************************************************************************** @@ -198,13 +196,13 @@ GPIO_readDio( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE uint32_t -GPIO_readMultiDio( uint32_t dioMask ) +GPIO_readMultiDio(uint32_t dioMask) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); // Return the input value from the specified DIOs. - return ( HWREG( GPIO_BASE + GPIO_O_DIN31_0 ) & dioMask ); + return (HWREG(GPIO_BASE + GPIO_O_DIN31_0) & dioMask); } //***************************************************************************** @@ -222,14 +220,14 @@ GPIO_readMultiDio( uint32_t dioMask ) // //***************************************************************************** __STATIC_INLINE void -GPIO_writeDio( uint32_t dioNumber, uint32_t value ) +GPIO_writeDio(uint32_t dioNumber, uint32_t value) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); - ASSERT(( value == 0 ) || ( value == 1 )); + ASSERT(dioNumberLegal(dioNumber)); + ASSERT((value == 0) || (value == 1)); // Write 0 or 1 to the byte indexed DOUT map - HWREGB( GPIO_BASE + dioNumber ) = value; + HWREGB(GPIO_BASE + dioNumber) = value; } //***************************************************************************** @@ -254,14 +252,14 @@ GPIO_writeDio( uint32_t dioNumber, uint32_t value ) // //***************************************************************************** __STATIC_INLINE void -GPIO_writeMultiDio( uint32_t dioMask, uint32_t bitVectoredValue ) +GPIO_writeMultiDio(uint32_t dioMask, uint32_t bitVectoredValue) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); - HWREG( GPIO_BASE + GPIO_O_DOUT31_0 ) = - ( HWREG( GPIO_BASE + GPIO_O_DOUT31_0 ) & ~dioMask ) | - ( bitVectoredValue & dioMask ); + HWREG(GPIO_BASE + GPIO_O_DOUT31_0) = + (HWREG(GPIO_BASE + GPIO_O_DOUT31_0) & ~dioMask) | + (bitVectoredValue & dioMask); } //***************************************************************************** @@ -276,13 +274,13 @@ GPIO_writeMultiDio( uint32_t dioMask, uint32_t bitVectoredValue ) // //***************************************************************************** __STATIC_INLINE void -GPIO_setDio( uint32_t dioNumber ) +GPIO_setDio(uint32_t dioNumber) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); + ASSERT(dioNumberLegal(dioNumber)); // Set the specified DIO. - HWREG( GPIO_BASE + GPIO_O_DOUTSET31_0 ) = ( 1 << dioNumber ); + HWREG(GPIO_BASE + GPIO_O_DOUTSET31_0) = (1 << dioNumber); } //***************************************************************************** @@ -301,13 +299,13 @@ GPIO_setDio( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE void -GPIO_setMultiDio( uint32_t dioMask ) +GPIO_setMultiDio(uint32_t dioMask) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); // Set the DIOs. - HWREG( GPIO_BASE + GPIO_O_DOUTSET31_0 ) = dioMask; + HWREG(GPIO_BASE + GPIO_O_DOUTSET31_0) = dioMask; } //***************************************************************************** @@ -322,13 +320,13 @@ GPIO_setMultiDio( uint32_t dioMask ) // //***************************************************************************** __STATIC_INLINE void -GPIO_clearDio( uint32_t dioNumber ) +GPIO_clearDio(uint32_t dioNumber) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); + ASSERT(dioNumberLegal(dioNumber)); // Clear the specified DIO. - HWREG( GPIO_BASE + GPIO_O_DOUTCLR31_0 ) = ( 1 << dioNumber ); + HWREG(GPIO_BASE + GPIO_O_DOUTCLR31_0) = (1 << dioNumber); } //***************************************************************************** @@ -347,13 +345,13 @@ GPIO_clearDio( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE void -GPIO_clearMultiDio( uint32_t dioMask ) +GPIO_clearMultiDio(uint32_t dioMask) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); // Clear the DIOs. - HWREG( GPIO_BASE + GPIO_O_DOUTCLR31_0 ) = dioMask; + HWREG(GPIO_BASE + GPIO_O_DOUTCLR31_0) = dioMask; } //***************************************************************************** @@ -368,13 +366,13 @@ GPIO_clearMultiDio( uint32_t dioMask ) // //***************************************************************************** __STATIC_INLINE void -GPIO_toggleDio( uint32_t dioNumber ) +GPIO_toggleDio(uint32_t dioNumber) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); + ASSERT(dioNumberLegal(dioNumber)); // Toggle the specified DIO. - HWREG( GPIO_BASE + GPIO_O_DOUTTGL31_0 ) = ( 1 << dioNumber ); + HWREG(GPIO_BASE + GPIO_O_DOUTTGL31_0) = (1 << dioNumber); } //***************************************************************************** @@ -393,13 +391,13 @@ GPIO_toggleDio( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE void -GPIO_toggleMultiDio( uint32_t dioMask ) +GPIO_toggleMultiDio(uint32_t dioMask) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); // Toggle the DIOs. - HWREG( GPIO_BASE + GPIO_O_DOUTTGL31_0 ) = dioMask; + HWREG(GPIO_BASE + GPIO_O_DOUTTGL31_0) = dioMask; } //***************************************************************************** @@ -419,13 +417,13 @@ GPIO_toggleMultiDio( uint32_t dioMask ) // //***************************************************************************** __STATIC_INLINE uint32_t -GPIO_getOutputEnableDio( uint32_t dioNumber ) +GPIO_getOutputEnableDio(uint32_t dioNumber) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); + ASSERT(dioNumberLegal(dioNumber)); // Return the output enable status for the specified DIO. - return (( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) >> dioNumber ) & 1 ); + return ((HWREG(GPIO_BASE + GPIO_O_DOE31_0) >> dioNumber) & 1); } //***************************************************************************** @@ -449,13 +447,13 @@ GPIO_getOutputEnableDio( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE uint32_t -GPIO_getOutputEnableMultiDio( uint32_t dioMask ) +GPIO_getOutputEnableMultiDio(uint32_t dioMask) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); // Return the output enable value for the specified DIOs. - return ( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) & dioMask ); + return (HWREG(GPIO_BASE + GPIO_O_DOE31_0) & dioMask); } //***************************************************************************** @@ -476,15 +474,15 @@ GPIO_getOutputEnableMultiDio( uint32_t dioMask ) // //***************************************************************************** __STATIC_INLINE void -GPIO_setOutputEnableDio( uint32_t dioNumber, uint32_t outputEnableValue ) +GPIO_setOutputEnableDio(uint32_t dioNumber, uint32_t outputEnableValue) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); - ASSERT(( outputEnableValue == GPIO_OUTPUT_DISABLE ) || - ( outputEnableValue == GPIO_OUTPUT_ENABLE ) ); + ASSERT(dioNumberLegal(dioNumber)); + ASSERT((outputEnableValue == GPIO_OUTPUT_DISABLE) || + (outputEnableValue == GPIO_OUTPUT_ENABLE)); // Update the output enable bit for the specified DIO. - HWREGBITW( GPIO_BASE + GPIO_O_DOE31_0, dioNumber ) = outputEnableValue; + HWREGBITW(GPIO_BASE + GPIO_O_DOE31_0, dioNumber) = outputEnableValue; } //***************************************************************************** @@ -512,14 +510,14 @@ GPIO_setOutputEnableDio( uint32_t dioNumber, uint32_t outputEnableValue ) // //***************************************************************************** __STATIC_INLINE void -GPIO_setOutputEnableMultiDio( uint32_t dioMask, uint32_t bitVectoredOutputEnable ) +GPIO_setOutputEnableMultiDio(uint32_t dioMask, uint32_t bitVectoredOutputEnable) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); - HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) = - ( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) & ~dioMask ) | - ( bitVectoredOutputEnable & dioMask ); + HWREG(GPIO_BASE + GPIO_O_DOE31_0) = + (HWREG(GPIO_BASE + GPIO_O_DOE31_0) & ~dioMask) | + (bitVectoredOutputEnable & dioMask); } //***************************************************************************** @@ -536,13 +534,13 @@ GPIO_setOutputEnableMultiDio( uint32_t dioMask, uint32_t bitVectoredOutputEnable // //***************************************************************************** __STATIC_INLINE uint32_t -GPIO_getEventDio( uint32_t dioNumber ) +GPIO_getEventDio(uint32_t dioNumber) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); + ASSERT(dioNumberLegal(dioNumber)); // Return the event status for the specified DIO. - return (( HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) >> dioNumber ) & 1 ); + return ((HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0) >> dioNumber) & 1); } //***************************************************************************** @@ -567,13 +565,13 @@ GPIO_getEventDio( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE uint32_t -GPIO_getEventMultiDio( uint32_t dioMask ) +GPIO_getEventMultiDio(uint32_t dioMask) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); // Return the event status for the specified DIO. - return ( HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) & dioMask ); + return (HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0) & dioMask); } //***************************************************************************** @@ -588,13 +586,13 @@ GPIO_getEventMultiDio( uint32_t dioMask ) // //***************************************************************************** __STATIC_INLINE void -GPIO_clearEventDio( uint32_t dioNumber ) +GPIO_clearEventDio(uint32_t dioNumber) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); + ASSERT(dioNumberLegal(dioNumber)); // Clear the event status for the specified DIO. - HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) = ( 1 << dioNumber ); + HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0) = (1 << dioNumber); } //***************************************************************************** @@ -614,13 +612,13 @@ GPIO_clearEventDio( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE void -GPIO_clearEventMultiDio( uint32_t dioMask ) +GPIO_clearEventMultiDio(uint32_t dioMask) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); // Clear the event status for the specified DIOs. - HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) = dioMask; + HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0) = dioMask; } //***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/gpio_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/gpio_doc.h index b4548af..0fe98bb 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/gpio_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/gpio_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: gpio_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: gpio_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup gpio_api //! @{ //! \section sec_gpio Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/group_analog_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/group_analog_doc.h index 21b8b55..a35d791 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/group_analog_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/group_analog_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: group_analog_doc.h -* Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016) -* Revision: 47080 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: group_analog_doc.h + * Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016) + * Revision: 47080 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup analog_group //! @{ //! \section sec_analog Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/group_aon_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/group_aon_doc.h index c5056d9..ee6b114 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/group_aon_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/group_aon_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: group_aon_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: group_aon_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup aon_group //! @{ //! \section sec_aon Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/group_aux_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/group_aux_doc.h index 63ddcfd..b3c5402 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/group_aux_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/group_aux_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: group_aux_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: group_aux_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup aux_group //! @{ //! \section sec_aux Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.h index c4ece78..5361dbf 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: i2c.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and prototypes for the I2C. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: i2c.h + * Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) + * Revision: 49048 + * + * Description: Defines and prototypes for the I2C. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,20 +55,19 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" +#include "../inc/hw_i2c.h" #include "../inc/hw_ints.h" #include "../inc/hw_memmap.h" -#include "../inc/hw_i2c.h" #include "../inc/hw_sysctl.h" +#include "../inc/hw_types.h" +#include "cpu.h" #include "debug.h" #include "interrupt.h" -#include "cpu.h" +#include +#include //***************************************************************************** // @@ -84,10 +83,10 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define I2CMasterInitExpClk NOROM_I2CMasterInitExpClk -#define I2CMasterErr NOROM_I2CMasterErr -#define I2CIntRegister NOROM_I2CIntRegister -#define I2CIntUnregister NOROM_I2CIntUnregister +#define I2CMasterInitExpClk NOROM_I2CMasterInitExpClk +#define I2CMasterErr NOROM_I2CMasterErr +#define I2CIntRegister NOROM_I2CIntRegister +#define I2CIntUnregister NOROM_I2CIntUnregister #endif //***************************************************************************** @@ -95,25 +94,25 @@ extern "C" // I2C Master commands // //***************************************************************************** -#define I2C_MASTER_CMD_SINGLE_SEND \ +#define I2C_MASTER_CMD_SINGLE_SEND \ 0x00000007 -#define I2C_MASTER_CMD_SINGLE_RECEIVE \ +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ 0x00000007 -#define I2C_MASTER_CMD_BURST_SEND_START \ +#define I2C_MASTER_CMD_BURST_SEND_START \ 0x00000003 -#define I2C_MASTER_CMD_BURST_SEND_CONT \ +#define I2C_MASTER_CMD_BURST_SEND_CONT \ 0x00000001 -#define I2C_MASTER_CMD_BURST_SEND_FINISH \ +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ 0x00000005 -#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ 0x00000004 -#define I2C_MASTER_CMD_BURST_RECEIVE_START \ +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ 0x0000000b -#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ 0x00000009 -#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ 0x00000005 -#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ 0x00000004 //***************************************************************************** @@ -121,7 +120,7 @@ extern "C" // I2C Master error status // //***************************************************************************** -#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_NONE 0 #define I2C_MASTER_ERR_ADDR_ACK 0x00000004 #define I2C_MASTER_ERR_DATA_ACK 0x00000008 #define I2C_MASTER_ERR_ARB_LOST 0x00000010 @@ -131,19 +130,19 @@ extern "C" // I2C Slave action requests // //***************************************************************************** -#define I2C_SLAVE_ACT_NONE 0 -#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data -#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data -#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data +#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte //***************************************************************************** // // I2C Slave interrupts // //***************************************************************************** -#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt. -#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt. -#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt. +#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt. +#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt. +#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt. //***************************************************************************** // @@ -937,20 +936,20 @@ extern void I2CIntUnregister(uint32_t ui32Base); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_I2CMasterInitExpClk -#undef I2CMasterInitExpClk -#define I2CMasterInitExpClk ROM_I2CMasterInitExpClk +#undef I2CMasterInitExpClk +#define I2CMasterInitExpClk ROM_I2CMasterInitExpClk #endif #ifdef ROM_I2CMasterErr -#undef I2CMasterErr -#define I2CMasterErr ROM_I2CMasterErr +#undef I2CMasterErr +#define I2CMasterErr ROM_I2CMasterErr #endif #ifdef ROM_I2CIntRegister -#undef I2CIntRegister -#define I2CIntRegister ROM_I2CIntRegister +#undef I2CIntRegister +#define I2CIntRegister ROM_I2CIntRegister #endif #ifdef ROM_I2CIntUnregister -#undef I2CIntUnregister -#define I2CIntUnregister ROM_I2CIntUnregister +#undef I2CIntUnregister +#define I2CIntUnregister ROM_I2CIntUnregister #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2c_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2c_doc.h index c339318..c2206dd 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2c_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2c_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: i2c_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: i2c_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup i2c_api //! @{ //! \section sec_i2c Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.h index 116b252..c158837 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: i2s.h -* Revised: 2018-11-16 11:16:53 +0100 (Fri, 16 Nov 2018) -* Revision: 53356 -* -* Description: Defines and prototypes for the I2S. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: i2s.h + * Revised: 2018-11-16 11:16:53 +0100 (Fri, 16 Nov 2018) + * Revision: 53356 + * + * Description: Defines and prototypes for the I2S. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //**************************************************************************** // @@ -55,18 +55,17 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" #include "../inc/hw_i2s.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "debug.h" #include "interrupt.h" +#include +#include //***************************************************************************** // @@ -82,14 +81,14 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define I2SEnable NOROM_I2SEnable -#define I2SAudioFormatConfigure NOROM_I2SAudioFormatConfigure -#define I2SChannelConfigure NOROM_I2SChannelConfigure -#define I2SBufferConfig NOROM_I2SBufferConfig -#define I2SPointerUpdate NOROM_I2SPointerUpdate -#define I2SPointerSet NOROM_I2SPointerSet -#define I2SSampleStampConfigure NOROM_I2SSampleStampConfigure -#define I2SSampleStampGet NOROM_I2SSampleStampGet +#define I2SEnable NOROM_I2SEnable +#define I2SAudioFormatConfigure NOROM_I2SAudioFormatConfigure +#define I2SChannelConfigure NOROM_I2SChannelConfigure +#define I2SBufferConfig NOROM_I2SBufferConfig +#define I2SPointerUpdate NOROM_I2SPointerUpdate +#define I2SPointerSet NOROM_I2SPointerSet +#define I2SSampleStampConfigure NOROM_I2SSampleStampConfigure +#define I2SSampleStampGet NOROM_I2SSampleStampGet #endif //***************************************************************************** @@ -118,15 +117,15 @@ extern "C" #ifndef DEPRECATED typedef struct { - uint16_t ui16DMABufSize; //!< Size of DMA buffer in number of samples. - uint16_t ui16ChBufSize; //!< Size of Channel buffer. - uint8_t ui8InChan; //!< Input Channel. - uint8_t ui8OutChan; //!< Output Channel. - uint16_t ui16MemLen; //!< Length of the audio words stored in memory. - uint32_t ui32InBase; //!< Base address of the input buffer. - uint32_t ui32InOffset; //!< Value of the current input pointer offset. - uint32_t ui32OutBase; //!< Base address of the output buffer. - uint32_t ui32OutOffset; //!< Value of the current output pointer offset. + uint16_t ui16DMABufSize; //!< Size of DMA buffer in number of samples. + uint16_t ui16ChBufSize; //!< Size of Channel buffer. + uint8_t ui8InChan; //!< Input Channel. + uint8_t ui8OutChan; //!< Output Channel. + uint16_t ui16MemLen; //!< Length of the audio words stored in memory. + uint32_t ui32InBase; //!< Base address of the input buffer. + uint32_t ui32InOffset; //!< Value of the current input pointer offset. + uint32_t ui32OutBase; //!< Base address of the output buffer. + uint32_t ui32OutOffset; //!< Value of the current output pointer offset. } I2SControlTable; #endif @@ -151,9 +150,9 @@ extern I2SControlTable* g_pControlTable; // //***************************************************************************** #ifndef DEPRECATED -#define I2S_DMA_BUF_SIZE_64 0x00000040 -#define I2S_DMA_BUF_SIZE_128 0x00000080 -#define I2S_DMA_BUF_SIZE_256 0x00000100 +#define I2S_DMA_BUF_SIZE_64 0x00000040 +#define I2S_DMA_BUF_SIZE_128 0x00000080 +#define I2S_DMA_BUF_SIZE_256 0x00000100 #endif //***************************************************************************** @@ -162,10 +161,10 @@ extern I2SControlTable* g_pControlTable; // //***************************************************************************** #ifndef DEPRECATED -#define I2S_EXT_WCLK 0x00000001 -#define I2S_INT_WCLK 0x00000002 -#define I2S_INVERT_WCLK 0x00000004 -#define I2S_NORMAL_WCLK 0x00000000 +#define I2S_EXT_WCLK 0x00000001 +#define I2S_INT_WCLK 0x00000002 +#define I2S_INVERT_WCLK 0x00000004 +#define I2S_NORMAL_WCLK 0x00000000 #endif //***************************************************************************** @@ -174,10 +173,10 @@ extern I2SControlTable* g_pControlTable; // //***************************************************************************** #ifndef DEPRECATED -#define I2S_LINE_UNUSED 0x00000000 -#define I2S_LINE_INPUT 0x00000001 -#define I2S_LINE_OUTPUT 0x00000002 -#define I2S_LINE_MASK 0x00000003 +#define I2S_LINE_UNUSED 0x00000000 +#define I2S_LINE_INPUT 0x00000001 +#define I2S_LINE_OUTPUT 0x00000002 +#define I2S_LINE_MASK 0x00000003 #endif //***************************************************************************** @@ -186,42 +185,42 @@ extern I2SControlTable* g_pControlTable; // //***************************************************************************** #ifndef DEPRECATED -#define I2S_CHAN0_ACT 0x00000100 -#define I2S_CHAN1_ACT 0x00000200 -#define I2S_CHAN2_ACT 0x00000400 -#define I2S_CHAN3_ACT 0x00000800 -#define I2S_CHAN4_ACT 0x00001000 -#define I2S_CHAN5_ACT 0x00002000 -#define I2S_CHAN6_ACT 0x00004000 -#define I2S_CHAN7_ACT 0x00008000 -#define I2S_MONO_MODE 0x00000100 -#define I2S_STEREO_MODE 0x00000300 -#define I2S_CHAN_CFG_MASK 0x0000FF00 +#define I2S_CHAN0_ACT 0x00000100 +#define I2S_CHAN1_ACT 0x00000200 +#define I2S_CHAN2_ACT 0x00000400 +#define I2S_CHAN3_ACT 0x00000800 +#define I2S_CHAN4_ACT 0x00001000 +#define I2S_CHAN5_ACT 0x00002000 +#define I2S_CHAN6_ACT 0x00004000 +#define I2S_CHAN7_ACT 0x00008000 +#define I2S_MONO_MODE 0x00000100 +#define I2S_STEREO_MODE 0x00000300 +#define I2S_CHAN_CFG_MASK 0x0000FF00 #endif -#define I2S_CHAN0_MASK 0x00000001 -#define I2S_CHAN1_MASK 0x00000002 -#define I2S_CHAN2_MASK 0x00000004 -#define I2S_CHAN3_MASK 0x00000008 -#define I2S_CHAN4_MASK 0x00000010 -#define I2S_CHAN5_MASK 0x00000020 -#define I2S_CHAN6_MASK 0x00000040 -#define I2S_CHAN7_MASK 0x00000080 +#define I2S_CHAN0_MASK 0x00000001 +#define I2S_CHAN1_MASK 0x00000002 +#define I2S_CHAN2_MASK 0x00000004 +#define I2S_CHAN3_MASK 0x00000008 +#define I2S_CHAN4_MASK 0x00000010 +#define I2S_CHAN5_MASK 0x00000020 +#define I2S_CHAN6_MASK 0x00000040 +#define I2S_CHAN7_MASK 0x00000080 //***************************************************************************** // // Defines for the audio format configuration // //***************************************************************************** -#define I2S_MEM_LENGTH_16 0x00000000 // 16 bit size of word in memory -#define I2S_MEM_LENGTH_24 0x00000080 // 24 bit size of word in memory -#define I2S_POS_EDGE 0x00000040 // Sample on positive edge -#define I2S_NEG_EDGE 0x00000000 // Sample on negative edge -#define I2S_DUAL_PHASE_FMT 0x00000020 // Dual Phased audio format -#define I2S_SINGLE_PHASE_FMT 0x00000000 // Single Phased audio format -#define I2S_WORD_LENGTH_8 0x00000008 // Word length is 8 bits -#define I2S_WORD_LENGTH_16 0x00000010 // Word length is 16 bits -#define I2S_WORD_LENGTH_24 0x00000018 // Word length is 24 bits +#define I2S_MEM_LENGTH_16 0x00000000 // 16 bit size of word in memory +#define I2S_MEM_LENGTH_24 0x00000080 // 24 bit size of word in memory +#define I2S_POS_EDGE 0x00000040 // Sample on positive edge +#define I2S_NEG_EDGE 0x00000000 // Sample on negative edge +#define I2S_DUAL_PHASE_FMT 0x00000020 // Dual Phased audio format +#define I2S_SINGLE_PHASE_FMT 0x00000000 // Single Phased audio format +#define I2S_WORD_LENGTH_8 0x00000008 // Word length is 8 bits +#define I2S_WORD_LENGTH_16 0x00000010 // Word length is 16 bits +#define I2S_WORD_LENGTH_24 0x00000018 // Word length is 24 bits //***************************************************************************** // @@ -229,10 +228,10 @@ extern I2SControlTable* g_pControlTable; // //***************************************************************************** #ifndef DEPRECATED -#define I2S_STMP0 0x00000001 // Sample stamp counter channel 0 -#define I2S_STMP1 0x00000002 // Sample stamp counter channel 1 +#define I2S_STMP0 0x00000001 // Sample stamp counter channel 0 +#define I2S_STMP1 0x00000002 // Sample stamp counter channel 1 #endif -#define I2S_STMP_SATURATION 0x0000FFFF // The saturation value used when +#define I2S_STMP_SATURATION 0x0000FFFF // The saturation value used when // calculating the sample stamp //***************************************************************************** @@ -240,13 +239,13 @@ extern I2SControlTable* g_pControlTable; // Defines for the interrupt // //***************************************************************************** -#define I2S_INT_DMA_IN 0x00000020 // DMA output buffer full interrupt -#define I2S_INT_DMA_OUT 0x00000010 // DMA input buffer empty interrupt -#define I2S_INT_TIMEOUT 0x00000008 // Word Clock Timeout -#define I2S_INT_BUS_ERR 0x00000004 // DMA Bus error -#define I2S_INT_WCLK_ERR 0x00000002 // Word Clock error -#define I2S_INT_PTR_ERR 0x00000001 // Data pointer error (DMA data was not updated in time). -#define I2S_INT_ALL 0x0000003F // All interrupts +#define I2S_INT_DMA_IN 0x00000020 // DMA output buffer full interrupt +#define I2S_INT_DMA_OUT 0x00000010 // DMA input buffer empty interrupt +#define I2S_INT_TIMEOUT 0x00000008 // Word Clock Timeout +#define I2S_INT_BUS_ERR 0x00000004 // DMA Bus error +#define I2S_INT_WCLK_ERR 0x00000002 // Word Clock error +#define I2S_INT_PTR_ERR 0x00000001 // Data pointer error (DMA data was not updated in time). +#define I2S_INT_ALL 0x0000003F // All interrupts //***************************************************************************** // @@ -842,7 +841,6 @@ I2SSampleStampDisable(uint32_t ui32Base) // Clear the enable bit. HWREG(I2S0_BASE + I2S_O_STMPCTL) = 0; - } //***************************************************************************** @@ -955,11 +953,11 @@ __STATIC_INLINE void I2SStop(uint32_t ui32Base) //***************************************************************************** __STATIC_INLINE void I2SFormatConfigure(uint32_t ui32Base, - uint8_t ui8iDataDelay, - uint8_t ui8iMemory24Bits, - uint8_t ui8iSamplingEdge, - bool boolDualPhase, - uint8_t ui8BitsPerSample, + uint8_t ui8iDataDelay, + uint8_t ui8iMemory24Bits, + uint8_t ui8iSamplingEdge, + bool boolDualPhase, + uint8_t ui8BitsPerSample, uint16_t ui16transmissionDelay) { // Check the arguments. @@ -969,11 +967,11 @@ I2SFormatConfigure(uint32_t ui32Base, // Setup register AIFFMTCFG Source. HWREGH(I2S0_BASE + I2S_O_AIFFMTCFG) = - (ui8iDataDelay << I2S_AIFFMTCFG_DATA_DELAY_S) | - (ui8iMemory24Bits << I2S_AIFFMTCFG_MEM_LEN_24_S) | - (ui8iSamplingEdge << I2S_AIFFMTCFG_SMPL_EDGE_S ) | - (boolDualPhase << I2S_AIFFMTCFG_DUAL_PHASE_S) | - (ui8BitsPerSample << I2S_AIFFMTCFG_WORD_LEN_S ); + (ui8iDataDelay << I2S_AIFFMTCFG_DATA_DELAY_S) | + (ui8iMemory24Bits << I2S_AIFFMTCFG_MEM_LEN_24_S) | + (ui8iSamplingEdge << I2S_AIFFMTCFG_SMPL_EDGE_S) | + (boolDualPhase << I2S_AIFFMTCFG_DUAL_PHASE_S) | + (ui8BitsPerSample << I2S_AIFFMTCFG_WORD_LEN_S); // Number of WCLK periods before the first read / write HWREGH(I2S0_BASE + I2S_O_STMPWPER) = ui16transmissionDelay; @@ -1022,8 +1020,8 @@ I2SFormatConfigure(uint32_t ui32Base, //**************************************************************************** __STATIC_INLINE void I2SFrameConfigure(uint32_t ui32Base, - uint8_t ui8StatusAD0, uint8_t ui8ChanAD0, - uint8_t ui8StatusAD1, uint8_t ui8ChanAD1) + uint8_t ui8StatusAD0, uint8_t ui8ChanAD0, + uint8_t ui8StatusAD1, uint8_t ui8ChanAD1) { // Check the arguments. ASSERT(I2SBaseValid(ui32Base)); @@ -1058,8 +1056,8 @@ I2SFrameConfigure(uint32_t ui32Base, //**************************************************************************** __STATIC_INLINE void I2SWclkConfigure(uint32_t ui32Base, - bool boolMaster, - bool boolWCLKInvert) + bool boolMaster, + bool boolWCLKInvert) { // Check the arguments. ASSERT(I2SBaseValid(ui32Base)); @@ -1071,8 +1069,8 @@ I2SWclkConfigure(uint32_t ui32Base, // Setup register WCLK Source. HWREGB(I2S0_BASE + I2S_O_AIFWCLKSRC) = - ((ui8ClkSource << I2S_AIFWCLKSRC_WCLK_SRC_S) | - (boolWCLKInvert << I2S_AIFWCLKSRC_WCLK_INV_S )); + ((ui8ClkSource << I2S_AIFWCLKSRC_WCLK_SRC_S) | + (boolWCLKInvert << I2S_AIFWCLKSRC_WCLK_INV_S)); } //**************************************************************************** @@ -1151,7 +1149,6 @@ I2SInPointerNextGet(uint32_t ui32Base) return (HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT)); } - //**************************************************************************** // //! \brief Get value stored in PTR NEXT OUT register @@ -1306,36 +1303,36 @@ I2SWclkCounterReset(uint32_t ui32Base) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_I2SEnable -#undef I2SEnable -#define I2SEnable ROM_I2SEnable +#undef I2SEnable +#define I2SEnable ROM_I2SEnable #endif #ifdef ROM_I2SAudioFormatConfigure -#undef I2SAudioFormatConfigure -#define I2SAudioFormatConfigure ROM_I2SAudioFormatConfigure +#undef I2SAudioFormatConfigure +#define I2SAudioFormatConfigure ROM_I2SAudioFormatConfigure #endif #ifdef ROM_I2SChannelConfigure -#undef I2SChannelConfigure -#define I2SChannelConfigure ROM_I2SChannelConfigure +#undef I2SChannelConfigure +#define I2SChannelConfigure ROM_I2SChannelConfigure #endif #ifdef ROM_I2SBufferConfig -#undef I2SBufferConfig -#define I2SBufferConfig ROM_I2SBufferConfig +#undef I2SBufferConfig +#define I2SBufferConfig ROM_I2SBufferConfig #endif #ifdef ROM_I2SPointerUpdate -#undef I2SPointerUpdate -#define I2SPointerUpdate ROM_I2SPointerUpdate +#undef I2SPointerUpdate +#define I2SPointerUpdate ROM_I2SPointerUpdate #endif #ifdef ROM_I2SPointerSet -#undef I2SPointerSet -#define I2SPointerSet ROM_I2SPointerSet +#undef I2SPointerSet +#define I2SPointerSet ROM_I2SPointerSet #endif #ifdef ROM_I2SSampleStampConfigure -#undef I2SSampleStampConfigure -#define I2SSampleStampConfigure ROM_I2SSampleStampConfigure +#undef I2SSampleStampConfigure +#define I2SSampleStampConfigure ROM_I2SSampleStampConfigure #endif #ifdef ROM_I2SSampleStampGet -#undef I2SSampleStampGet -#define I2SSampleStampGet ROM_I2SSampleStampGet +#undef I2SSampleStampGet +#define I2SSampleStampGet ROM_I2SSampleStampGet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2s_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2s_doc.h index 27ddceb..d72ccd4 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2s_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/i2s_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: i2s_doc.h -* Revised: $$ -* Revision: $$ -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: i2s_doc.h + * Revised: $$ + * Revision: $$ + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup i2s_api //! @{ //! \section sec_i2s Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.h index 6909338..dec9162 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: interrupt.h -* Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017) -* Revision: 50272 -* -* Description: Defines and prototypes for the NVIC Interrupt Controller -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: interrupt.h + * Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017) + * Revision: 50272 + * + * Description: Defines and prototypes for the NVIC Interrupt Controller + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,17 +55,16 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_ints.h" +#include "../inc/hw_nvic.h" +#include "../inc/hw_types.h" +#include "cpu.h" +#include "debug.h" #include #include -#include "../inc/hw_ints.h" -#include "../inc/hw_types.h" -#include "../inc/hw_nvic.h" -#include "debug.h" -#include "cpu.h" //***************************************************************************** // @@ -81,17 +80,17 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define IntRegister NOROM_IntRegister -#define IntUnregister NOROM_IntUnregister -#define IntPriorityGroupingSet NOROM_IntPriorityGroupingSet -#define IntPriorityGroupingGet NOROM_IntPriorityGroupingGet -#define IntPrioritySet NOROM_IntPrioritySet -#define IntPriorityGet NOROM_IntPriorityGet -#define IntEnable NOROM_IntEnable -#define IntDisable NOROM_IntDisable -#define IntPendSet NOROM_IntPendSet -#define IntPendGet NOROM_IntPendGet -#define IntPendClear NOROM_IntPendClear +#define IntRegister NOROM_IntRegister +#define IntUnregister NOROM_IntUnregister +#define IntPriorityGroupingSet NOROM_IntPriorityGroupingSet +#define IntPriorityGroupingGet NOROM_IntPriorityGroupingGet +#define IntPrioritySet NOROM_IntPrioritySet +#define IntPriorityGet NOROM_IntPriorityGet +#define IntEnable NOROM_IntEnable +#define IntDisable NOROM_IntDisable +#define IntPendSet NOROM_IntPendSet +#define IntPendGet NOROM_IntPendGet +#define IntPendClear NOROM_IntPendClear #endif //***************************************************************************** @@ -104,15 +103,15 @@ extern "C" // INT_PRIORITY_MASK = ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) // //***************************************************************************** -#define INT_PRIORITY_MASK 0x000000E0 -#define INT_PRI_LEVEL0 0x00000000 -#define INT_PRI_LEVEL1 0x00000020 -#define INT_PRI_LEVEL2 0x00000040 -#define INT_PRI_LEVEL3 0x00000060 -#define INT_PRI_LEVEL4 0x00000080 -#define INT_PRI_LEVEL5 0x000000A0 -#define INT_PRI_LEVEL6 0x000000C0 -#define INT_PRI_LEVEL7 0x000000E0 +#define INT_PRIORITY_MASK 0x000000E0 +#define INT_PRI_LEVEL0 0x00000000 +#define INT_PRI_LEVEL1 0x00000020 +#define INT_PRI_LEVEL2 0x00000040 +#define INT_PRI_LEVEL3 0x00000060 +#define INT_PRI_LEVEL4 0x00000080 +#define INT_PRI_LEVEL5 0x000000A0 +#define INT_PRI_LEVEL6 0x000000C0 +#define INT_PRI_LEVEL7 0x000000E0 //***************************************************************************** // @@ -653,48 +652,48 @@ IntPriorityMaskGet(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_IntRegister -#undef IntRegister -#define IntRegister ROM_IntRegister +#undef IntRegister +#define IntRegister ROM_IntRegister #endif #ifdef ROM_IntUnregister -#undef IntUnregister -#define IntUnregister ROM_IntUnregister +#undef IntUnregister +#define IntUnregister ROM_IntUnregister #endif #ifdef ROM_IntPriorityGroupingSet -#undef IntPriorityGroupingSet -#define IntPriorityGroupingSet ROM_IntPriorityGroupingSet +#undef IntPriorityGroupingSet +#define IntPriorityGroupingSet ROM_IntPriorityGroupingSet #endif #ifdef ROM_IntPriorityGroupingGet -#undef IntPriorityGroupingGet -#define IntPriorityGroupingGet ROM_IntPriorityGroupingGet +#undef IntPriorityGroupingGet +#define IntPriorityGroupingGet ROM_IntPriorityGroupingGet #endif #ifdef ROM_IntPrioritySet -#undef IntPrioritySet -#define IntPrioritySet ROM_IntPrioritySet +#undef IntPrioritySet +#define IntPrioritySet ROM_IntPrioritySet #endif #ifdef ROM_IntPriorityGet -#undef IntPriorityGet -#define IntPriorityGet ROM_IntPriorityGet +#undef IntPriorityGet +#define IntPriorityGet ROM_IntPriorityGet #endif #ifdef ROM_IntEnable -#undef IntEnable -#define IntEnable ROM_IntEnable +#undef IntEnable +#define IntEnable ROM_IntEnable #endif #ifdef ROM_IntDisable -#undef IntDisable -#define IntDisable ROM_IntDisable +#undef IntDisable +#define IntDisable ROM_IntDisable #endif #ifdef ROM_IntPendSet -#undef IntPendSet -#define IntPendSet ROM_IntPendSet +#undef IntPendSet +#define IntPendSet ROM_IntPendSet #endif #ifdef ROM_IntPendGet -#undef IntPendGet -#define IntPendGet ROM_IntPendGet +#undef IntPendGet +#define IntPendGet ROM_IntPendGet #endif #ifdef ROM_IntPendClear -#undef IntPendClear -#define IntPendClear ROM_IntPendClear +#undef IntPendClear +#define IntPendClear ROM_IntPendClear #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt_doc.h index ff02174..903851c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: interrupt_doc.h -* Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017) -* Revision: 50272 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: interrupt_doc.h + * Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017) + * Revision: 50272 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup interrupt_api //! @{ //! \section sec_interrupt Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.h index 1d4a81b..2ad379c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: ioc.h -* Revised: 2017-11-02 14:16:14 +0100 (Thu, 02 Nov 2017) -* Revision: 50156 -* -* Description: Defines and prototypes for the IO Controller. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: ioc.h + * Revised: 2017-11-02 14:16:14 +0100 (Thu, 02 Nov 2017) + * Revision: 50156 + * + * Description: Defines and prototypes for the IO Controller. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,19 +55,18 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ioc.h" #include "../inc/hw_ints.h" -#include "interrupt.h" +#include "../inc/hw_ioc.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "debug.h" #include "gpio.h" +#include "interrupt.h" +#include +#include //***************************************************************************** // @@ -83,27 +82,27 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define IOCPortConfigureSet NOROM_IOCPortConfigureSet -#define IOCPortConfigureGet NOROM_IOCPortConfigureGet -#define IOCIOShutdownSet NOROM_IOCIOShutdownSet -#define IOCIOModeSet NOROM_IOCIOModeSet -#define IOCIOIntSet NOROM_IOCIOIntSet -#define IOCIOEvtSet NOROM_IOCIOEvtSet -#define IOCIOPortPullSet NOROM_IOCIOPortPullSet -#define IOCIOHystSet NOROM_IOCIOHystSet -#define IOCIOInputSet NOROM_IOCIOInputSet -#define IOCIOSlewCtrlSet NOROM_IOCIOSlewCtrlSet -#define IOCIODrvStrengthSet NOROM_IOCIODrvStrengthSet -#define IOCIOPortIdSet NOROM_IOCIOPortIdSet -#define IOCIntEnable NOROM_IOCIntEnable -#define IOCIntDisable NOROM_IOCIntDisable -#define IOCPinTypeGpioInput NOROM_IOCPinTypeGpioInput -#define IOCPinTypeGpioOutput NOROM_IOCPinTypeGpioOutput -#define IOCPinTypeUart NOROM_IOCPinTypeUart -#define IOCPinTypeSsiMaster NOROM_IOCPinTypeSsiMaster -#define IOCPinTypeSsiSlave NOROM_IOCPinTypeSsiSlave -#define IOCPinTypeI2c NOROM_IOCPinTypeI2c -#define IOCPinTypeAux NOROM_IOCPinTypeAux +#define IOCPortConfigureSet NOROM_IOCPortConfigureSet +#define IOCPortConfigureGet NOROM_IOCPortConfigureGet +#define IOCIOShutdownSet NOROM_IOCIOShutdownSet +#define IOCIOModeSet NOROM_IOCIOModeSet +#define IOCIOIntSet NOROM_IOCIOIntSet +#define IOCIOEvtSet NOROM_IOCIOEvtSet +#define IOCIOPortPullSet NOROM_IOCIOPortPullSet +#define IOCIOHystSet NOROM_IOCIOHystSet +#define IOCIOInputSet NOROM_IOCIOInputSet +#define IOCIOSlewCtrlSet NOROM_IOCIOSlewCtrlSet +#define IOCIODrvStrengthSet NOROM_IOCIODrvStrengthSet +#define IOCIOPortIdSet NOROM_IOCIOPortIdSet +#define IOCIntEnable NOROM_IOCIntEnable +#define IOCIntDisable NOROM_IOCIntDisable +#define IOCPinTypeGpioInput NOROM_IOCPinTypeGpioInput +#define IOCPinTypeGpioOutput NOROM_IOCPinTypeGpioOutput +#define IOCPinTypeUart NOROM_IOCPinTypeUart +#define IOCPinTypeSsiMaster NOROM_IOCPinTypeSsiMaster +#define IOCPinTypeSsiSlave NOROM_IOCPinTypeSsiSlave +#define IOCPinTypeI2c NOROM_IOCPinTypeI2c +#define IOCPinTypeAux NOROM_IOCPinTypeAux #endif //***************************************************************************** @@ -118,41 +117,41 @@ extern "C" // The following fields are IO Id for the IOC module // //***************************************************************************** -#define IOID_0 0x00000000 // IO Id 0 -#define IOID_1 0x00000001 // IO Id 1 -#define IOID_2 0x00000002 // IO Id 2 -#define IOID_3 0x00000003 // IO Id 3 -#define IOID_4 0x00000004 // IO Id 4 -#define IOID_5 0x00000005 // IO Id 5 -#define IOID_6 0x00000006 // IO Id 6 -#define IOID_7 0x00000007 // IO Id 7 -#define IOID_8 0x00000008 // IO Id 8 -#define IOID_9 0x00000009 // IO Id 9 -#define IOID_10 0x0000000A // IO Id 10 -#define IOID_11 0x0000000B // IO Id 11 -#define IOID_12 0x0000000C // IO Id 12 -#define IOID_13 0x0000000D // IO Id 13 -#define IOID_14 0x0000000E // IO Id 14 -#define IOID_15 0x0000000F // IO Id 15 -#define IOID_16 0x00000010 // IO Id 16 -#define IOID_17 0x00000011 // IO Id 17 -#define IOID_18 0x00000012 // IO Id 18 -#define IOID_19 0x00000013 // IO Id 19 -#define IOID_20 0x00000014 // IO Id 20 -#define IOID_21 0x00000015 // IO Id 21 -#define IOID_22 0x00000016 // IO Id 22 -#define IOID_23 0x00000017 // IO Id 23 -#define IOID_24 0x00000018 // IO Id 24 -#define IOID_25 0x00000019 // IO Id 25 -#define IOID_26 0x0000001A // IO Id 26 -#define IOID_27 0x0000001B // IO Id 27 -#define IOID_28 0x0000001C // IO Id 28 -#define IOID_29 0x0000001D // IO Id 29 -#define IOID_30 0x0000001E // IO Id 30 -#define IOID_31 0x0000001F // IO Id 31 -#define IOID_UNUSED 0xFFFFFFFF // Unused IO Id +#define IOID_0 0x00000000 // IO Id 0 +#define IOID_1 0x00000001 // IO Id 1 +#define IOID_2 0x00000002 // IO Id 2 +#define IOID_3 0x00000003 // IO Id 3 +#define IOID_4 0x00000004 // IO Id 4 +#define IOID_5 0x00000005 // IO Id 5 +#define IOID_6 0x00000006 // IO Id 6 +#define IOID_7 0x00000007 // IO Id 7 +#define IOID_8 0x00000008 // IO Id 8 +#define IOID_9 0x00000009 // IO Id 9 +#define IOID_10 0x0000000A // IO Id 10 +#define IOID_11 0x0000000B // IO Id 11 +#define IOID_12 0x0000000C // IO Id 12 +#define IOID_13 0x0000000D // IO Id 13 +#define IOID_14 0x0000000E // IO Id 14 +#define IOID_15 0x0000000F // IO Id 15 +#define IOID_16 0x00000010 // IO Id 16 +#define IOID_17 0x00000011 // IO Id 17 +#define IOID_18 0x00000012 // IO Id 18 +#define IOID_19 0x00000013 // IO Id 19 +#define IOID_20 0x00000014 // IO Id 20 +#define IOID_21 0x00000015 // IO Id 21 +#define IOID_22 0x00000016 // IO Id 22 +#define IOID_23 0x00000017 // IO Id 23 +#define IOID_24 0x00000018 // IO Id 24 +#define IOID_25 0x00000019 // IO Id 25 +#define IOID_26 0x0000001A // IO Id 26 +#define IOID_27 0x0000001B // IO Id 27 +#define IOID_28 0x0000001C // IO Id 28 +#define IOID_29 0x0000001D // IO Id 29 +#define IOID_30 0x0000001E // IO Id 30 +#define IOID_31 0x0000001F // IO Id 31 +#define IOID_UNUSED 0xFFFFFFFF // Unused IO Id -#define IOC_IOID_MASK 0x000000FF // IOC IO Id bit mask +#define IOC_IOID_MASK 0x000000FF // IOC IO Id bit mask //***************************************************************************** // @@ -166,90 +165,90 @@ extern "C" // IOC Peripheral Port Mapping // //***************************************************************************** -#define IOC_PORT_GPIO 0x00000000 // Default general purpose IO usage -#define IOC_PORT_AON_CLK32K 0x00000007 // AON External 32kHz clock -#define IOC_PORT_AUX_IO 0x00000008 // AUX IO Pin -#define IOC_PORT_MCU_SSI0_RX 0x00000009 // MCU SSI0 Receive Pin -#define IOC_PORT_MCU_SSI0_TX 0x0000000A // MCU SSI0 Transmit Pin -#define IOC_PORT_MCU_SSI0_FSS 0x0000000B // MCU SSI0 FSS Pin -#define IOC_PORT_MCU_SSI0_CLK 0x0000000C // MCU SSI0 Clock Pin -#define IOC_PORT_MCU_I2C_MSSDA 0x0000000D // MCU I2C Data Pin -#define IOC_PORT_MCU_I2C_MSSCL 0x0000000E // MCU I2C Clock Pin -#define IOC_PORT_MCU_UART0_RX 0x0000000F // MCU UART0 Receive Pin -#define IOC_PORT_MCU_UART0_TX 0x00000010 // MCU UART0 Transmit Pin -#define IOC_PORT_MCU_UART0_CTS 0x00000011 // MCU UART0 Clear To Send Pin -#define IOC_PORT_MCU_UART0_RTS 0x00000012 // MCU UART0 Request To Send Pin -#define IOC_PORT_MCU_UART1_RX 0x00000013 // MCU UART1 Receive Pin -#define IOC_PORT_MCU_UART1_TX 0x00000014 // MCU UART1 Transmit Pin -#define IOC_PORT_MCU_UART1_CTS 0x00000015 // MCU UART1 Clear To Send Pin -#define IOC_PORT_MCU_UART1_RTS 0x00000016 // MCU UART1 Request To Send Pin -#define IOC_PORT_MCU_PORT_EVENT0 0x00000017 // MCU PORT EVENT 0 -#define IOC_PORT_MCU_PORT_EVENT1 0x00000018 // MCU PORT EVENT 1 -#define IOC_PORT_MCU_PORT_EVENT2 0x00000019 // MCU PORT EVENT 2 -#define IOC_PORT_MCU_PORT_EVENT3 0x0000001A // MCU PORT EVENT 3 -#define IOC_PORT_MCU_PORT_EVENT4 0x0000001B // MCU PORT EVENT 4 -#define IOC_PORT_MCU_PORT_EVENT5 0x0000001C // MCU PORT EVENT 5 -#define IOC_PORT_MCU_PORT_EVENT6 0x0000001D // MCU PORT EVENT 6 -#define IOC_PORT_MCU_PORT_EVENT7 0x0000001E // MCU PORT EVENT 7 -#define IOC_PORT_MCU_SWV 0x00000020 // Serial Wire Viewer -#define IOC_PORT_MCU_SSI1_RX 0x00000021 // MCU SSI1 Receive Pin -#define IOC_PORT_MCU_SSI1_TX 0x00000022 // MCU SSI1 Transmit Pin -#define IOC_PORT_MCU_SSI1_FSS 0x00000023 // MCU SSI1 FSS Pin -#define IOC_PORT_MCU_SSI1_CLK 0x00000024 // MCU SSI1 Clock Pin -#define IOC_PORT_MCU_I2S_AD0 0x00000025 // MCU I2S Data Pin 0 -#define IOC_PORT_MCU_I2S_AD1 0x00000026 // MCU I2S Data Pin 1 -#define IOC_PORT_MCU_I2S_WCLK 0x00000027 // MCU I2S Frame/Word Clock -#define IOC_PORT_MCU_I2S_BCLK 0x00000028 // MCU I2S Bit Clock -#define IOC_PORT_MCU_I2S_MCLK 0x00000029 // MCU I2S Master clock 2 -#define IOC_PORT_RFC_TRC 0x0000002E // RF Core Tracer -#define IOC_PORT_RFC_GPO0 0x0000002F // RC Core Data Out Pin 0 -#define IOC_PORT_RFC_GPO1 0x00000030 // RC Core Data Out Pin 1 -#define IOC_PORT_RFC_GPO2 0x00000031 // RC Core Data Out Pin 2 -#define IOC_PORT_RFC_GPO3 0x00000032 // RC Core Data Out Pin 3 -#define IOC_PORT_RFC_GPI0 0x00000033 // RC Core Data In Pin 0 -#define IOC_PORT_RFC_GPI1 0x00000034 // RC Core Data In Pin 1 -#define IOC_PORT_RFC_SMI_DL_OUT 0x00000035 // RF Core SMI Data Link Out -#define IOC_PORT_RFC_SMI_DL_IN 0x00000036 // RF Core SMI Data Link in -#define IOC_PORT_RFC_SMI_CL_OUT 0x00000037 // RF Core SMI Command Link Out -#define IOC_PORT_RFC_SMI_CL_IN 0x00000038 // RF Core SMI Command Link In +#define IOC_PORT_GPIO 0x00000000 // Default general purpose IO usage +#define IOC_PORT_AON_CLK32K 0x00000007 // AON External 32kHz clock +#define IOC_PORT_AUX_IO 0x00000008 // AUX IO Pin +#define IOC_PORT_MCU_SSI0_RX 0x00000009 // MCU SSI0 Receive Pin +#define IOC_PORT_MCU_SSI0_TX 0x0000000A // MCU SSI0 Transmit Pin +#define IOC_PORT_MCU_SSI0_FSS 0x0000000B // MCU SSI0 FSS Pin +#define IOC_PORT_MCU_SSI0_CLK 0x0000000C // MCU SSI0 Clock Pin +#define IOC_PORT_MCU_I2C_MSSDA 0x0000000D // MCU I2C Data Pin +#define IOC_PORT_MCU_I2C_MSSCL 0x0000000E // MCU I2C Clock Pin +#define IOC_PORT_MCU_UART0_RX 0x0000000F // MCU UART0 Receive Pin +#define IOC_PORT_MCU_UART0_TX 0x00000010 // MCU UART0 Transmit Pin +#define IOC_PORT_MCU_UART0_CTS 0x00000011 // MCU UART0 Clear To Send Pin +#define IOC_PORT_MCU_UART0_RTS 0x00000012 // MCU UART0 Request To Send Pin +#define IOC_PORT_MCU_UART1_RX 0x00000013 // MCU UART1 Receive Pin +#define IOC_PORT_MCU_UART1_TX 0x00000014 // MCU UART1 Transmit Pin +#define IOC_PORT_MCU_UART1_CTS 0x00000015 // MCU UART1 Clear To Send Pin +#define IOC_PORT_MCU_UART1_RTS 0x00000016 // MCU UART1 Request To Send Pin +#define IOC_PORT_MCU_PORT_EVENT0 0x00000017 // MCU PORT EVENT 0 +#define IOC_PORT_MCU_PORT_EVENT1 0x00000018 // MCU PORT EVENT 1 +#define IOC_PORT_MCU_PORT_EVENT2 0x00000019 // MCU PORT EVENT 2 +#define IOC_PORT_MCU_PORT_EVENT3 0x0000001A // MCU PORT EVENT 3 +#define IOC_PORT_MCU_PORT_EVENT4 0x0000001B // MCU PORT EVENT 4 +#define IOC_PORT_MCU_PORT_EVENT5 0x0000001C // MCU PORT EVENT 5 +#define IOC_PORT_MCU_PORT_EVENT6 0x0000001D // MCU PORT EVENT 6 +#define IOC_PORT_MCU_PORT_EVENT7 0x0000001E // MCU PORT EVENT 7 +#define IOC_PORT_MCU_SWV 0x00000020 // Serial Wire Viewer +#define IOC_PORT_MCU_SSI1_RX 0x00000021 // MCU SSI1 Receive Pin +#define IOC_PORT_MCU_SSI1_TX 0x00000022 // MCU SSI1 Transmit Pin +#define IOC_PORT_MCU_SSI1_FSS 0x00000023 // MCU SSI1 FSS Pin +#define IOC_PORT_MCU_SSI1_CLK 0x00000024 // MCU SSI1 Clock Pin +#define IOC_PORT_MCU_I2S_AD0 0x00000025 // MCU I2S Data Pin 0 +#define IOC_PORT_MCU_I2S_AD1 0x00000026 // MCU I2S Data Pin 1 +#define IOC_PORT_MCU_I2S_WCLK 0x00000027 // MCU I2S Frame/Word Clock +#define IOC_PORT_MCU_I2S_BCLK 0x00000028 // MCU I2S Bit Clock +#define IOC_PORT_MCU_I2S_MCLK 0x00000029 // MCU I2S Master clock 2 +#define IOC_PORT_RFC_TRC 0x0000002E // RF Core Tracer +#define IOC_PORT_RFC_GPO0 0x0000002F // RC Core Data Out Pin 0 +#define IOC_PORT_RFC_GPO1 0x00000030 // RC Core Data Out Pin 1 +#define IOC_PORT_RFC_GPO2 0x00000031 // RC Core Data Out Pin 2 +#define IOC_PORT_RFC_GPO3 0x00000032 // RC Core Data Out Pin 3 +#define IOC_PORT_RFC_GPI0 0x00000033 // RC Core Data In Pin 0 +#define IOC_PORT_RFC_GPI1 0x00000034 // RC Core Data In Pin 1 +#define IOC_PORT_RFC_SMI_DL_OUT 0x00000035 // RF Core SMI Data Link Out +#define IOC_PORT_RFC_SMI_DL_IN 0x00000036 // RF Core SMI Data Link in +#define IOC_PORT_RFC_SMI_CL_OUT 0x00000037 // RF Core SMI Command Link Out +#define IOC_PORT_RFC_SMI_CL_IN 0x00000038 // RF Core SMI Command Link In //***************************************************************************** // // Defines for enabling/disabling an IO // //***************************************************************************** -#define IOC_SLEW_ENABLE 0x00001000 -#define IOC_SLEW_DISABLE 0x00000000 -#define IOC_INPUT_ENABLE 0x20000000 -#define IOC_INPUT_DISABLE 0x00000000 -#define IOC_HYST_ENABLE 0x40000000 -#define IOC_HYST_DISABLE 0x00000000 +#define IOC_SLEW_ENABLE 0x00001000 +#define IOC_SLEW_DISABLE 0x00000000 +#define IOC_INPUT_ENABLE 0x20000000 +#define IOC_INPUT_DISABLE 0x00000000 +#define IOC_HYST_ENABLE 0x40000000 +#define IOC_HYST_DISABLE 0x00000000 //***************************************************************************** // // Defines that can be used to set the shutdown mode of an IO // //***************************************************************************** -#define IOC_NO_WAKE_UP 0x00000000 -#define IOC_WAKE_ON_LOW 0x10000000 -#define IOC_WAKE_ON_HIGH 0x18000000 +#define IOC_NO_WAKE_UP 0x00000000 +#define IOC_WAKE_ON_LOW 0x10000000 +#define IOC_WAKE_ON_HIGH 0x18000000 //***************************************************************************** // // Defines that can be used to set the IO Mode of an IO // //***************************************************************************** -#define IOC_IOMODE_NORMAL 0x00000000 // Normal Input/Output -#define IOC_IOMODE_INV 0x01000000 // Inverted Input/Output +#define IOC_IOMODE_NORMAL 0x00000000 // Normal Input/Output +#define IOC_IOMODE_INV 0x01000000 // Inverted Input/Output #define IOC_IOMODE_OPEN_DRAIN_NORMAL \ - 0x04000000 // Open Drain, Normal Input/Output + 0x04000000 // Open Drain, Normal Input/Output #define IOC_IOMODE_OPEN_DRAIN_INV \ - 0x05000000 // Open Drain, Inverted + 0x05000000 // Open Drain, Inverted // Input/Output #define IOC_IOMODE_OPEN_SRC_NORMAL \ - 0x06000000 // Open Source, Normal Input/Output + 0x06000000 // Open Source, Normal Input/Output #define IOC_IOMODE_OPEN_SRC_INV \ - 0x07000000 // Open Source, Inverted + 0x07000000 // Open Source, Inverted // Input/Output //***************************************************************************** @@ -257,41 +256,41 @@ extern "C" // Defines that can be used to set the edge detection on an IO // //***************************************************************************** -#define IOC_NO_EDGE 0x00000000 // No edge detection -#define IOC_FALLING_EDGE 0x00010000 // Edge detection on falling edge -#define IOC_RISING_EDGE 0x00020000 // Edge detection on rising edge -#define IOC_BOTH_EDGES 0x00030000 // Edge detection on both edges -#define IOC_INT_ENABLE 0x00040000 // Enable interrupt on edge detect -#define IOC_INT_DISABLE 0x00000000 // Disable interrupt on edge detect -#define IOC_INT_M 0x00070000 // Int config mask +#define IOC_NO_EDGE 0x00000000 // No edge detection +#define IOC_FALLING_EDGE 0x00010000 // Edge detection on falling edge +#define IOC_RISING_EDGE 0x00020000 // Edge detection on rising edge +#define IOC_BOTH_EDGES 0x00030000 // Edge detection on both edges +#define IOC_INT_ENABLE 0x00040000 // Enable interrupt on edge detect +#define IOC_INT_DISABLE 0x00000000 // Disable interrupt on edge detect +#define IOC_INT_M 0x00070000 // Int config mask //***************************************************************************** // // Defines that be used to set pull on an IO // //***************************************************************************** -#define IOC_NO_IOPULL 0x00006000 // No IO pull -#define IOC_IOPULL_UP 0x00004000 // Pull up -#define IOC_IOPULL_DOWN 0x00002000 // Pull down -#define IOC_IOPULL_M 0x00006000 // Pull config mask -#define IOC_IOPULL_M 0x00006000 +#define IOC_NO_IOPULL 0x00006000 // No IO pull +#define IOC_IOPULL_UP 0x00004000 // Pull up +#define IOC_IOPULL_DOWN 0x00002000 // Pull down +#define IOC_IOPULL_M 0x00006000 // Pull config mask +#define IOC_IOPULL_M 0x00006000 //***************************************************************************** // // Defines that can be used to select the drive strength of an IO // //***************************************************************************** -#define IOC_CURRENT_2MA 0x00000000 // 2mA drive strength -#define IOC_CURRENT_4MA 0x00000400 // 4mA drive strength -#define IOC_CURRENT_8MA 0x00000800 // 4 or 8mA drive strength +#define IOC_CURRENT_2MA 0x00000000 // 2mA drive strength +#define IOC_CURRENT_4MA 0x00000400 // 4mA drive strength +#define IOC_CURRENT_8MA 0x00000800 // 4 or 8mA drive strength -#define IOC_STRENGTH_AUTO 0x00000000 // Automatic Drive Strength +#define IOC_STRENGTH_AUTO 0x00000000 // Automatic Drive Strength // (2/4/8 mA @ VVDS) -#define IOC_STRENGTH_MAX 0x00000300 // Maximum Drive Strength +#define IOC_STRENGTH_MAX 0x00000300 // Maximum Drive Strength // (2/4/8 mA @ 1.8V) -#define IOC_STRENGTH_MED 0x00000200 // Medium Drive Strength +#define IOC_STRENGTH_MED 0x00000200 // Medium Drive Strength // (2/4/8 mA @ 2.5V) -#define IOC_STRENGTH_MIN 0x00000100 // Minimum Drive Strength +#define IOC_STRENGTH_MIN 0x00000100 // Minimum Drive Strength // (2/4/8 mA @ 3.3V) //***************************************************************************** @@ -299,32 +298,32 @@ extern "C" // Defines that can be used to enable event generation on edge detect // //***************************************************************************** -#define IOC_EVT_AON_PROG2_DISABLE 0x00000000 -#define IOC_EVT_AON_PROG2_ENABLE 0x00800000 -#define IOC_EVT_AON_PROG1_DISABLE 0x00000000 -#define IOC_EVT_AON_PROG1_ENABLE 0x00400000 -#define IOC_EVT_AON_PROG0_DISABLE 0x00000000 -#define IOC_EVT_AON_PROG0_ENABLE 0x00200000 -#define IOC_EVT_RTC_DISABLE 0x00000000 -#define IOC_EVT_RTC_ENABLE 0x00000080 -#define IOC_EVT_MCU_WU_DISABLE 0x00000000 -#define IOC_EVT_MCU_WU_ENABLE 0x00000040 +#define IOC_EVT_AON_PROG2_DISABLE 0x00000000 +#define IOC_EVT_AON_PROG2_ENABLE 0x00800000 +#define IOC_EVT_AON_PROG1_DISABLE 0x00000000 +#define IOC_EVT_AON_PROG1_ENABLE 0x00400000 +#define IOC_EVT_AON_PROG0_DISABLE 0x00000000 +#define IOC_EVT_AON_PROG0_ENABLE 0x00200000 +#define IOC_EVT_RTC_DISABLE 0x00000000 +#define IOC_EVT_RTC_ENABLE 0x00000080 +#define IOC_EVT_MCU_WU_DISABLE 0x00000000 +#define IOC_EVT_MCU_WU_ENABLE 0x00000040 //***************************************************************************** // // Defines for standard IO setup // //***************************************************************************** -#define IOC_STD_INPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ - IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ - IOC_HYST_DISABLE | IOC_NO_EDGE | \ - IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ - IOC_NO_WAKE_UP | IOC_INPUT_ENABLE ) -#define IOC_STD_OUTPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ - IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ - IOC_HYST_DISABLE | IOC_NO_EDGE | \ - IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ - IOC_NO_WAKE_UP | IOC_INPUT_DISABLE ) +#define IOC_STD_INPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ + IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ + IOC_HYST_DISABLE | IOC_NO_EDGE | \ + IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ + IOC_NO_WAKE_UP | IOC_INPUT_ENABLE) +#define IOC_STD_OUTPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ + IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ + IOC_HYST_DISABLE | IOC_NO_EDGE | \ + IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ + IOC_NO_WAKE_UP | IOC_INPUT_DISABLE) //***************************************************************************** // @@ -506,7 +505,6 @@ extern uint32_t IOCPortConfigureGet(uint32_t ui32IOId); //***************************************************************************** extern void IOCIOShutdownSet(uint32_t ui32IOId, uint32_t ui32IOShutdown); - //***************************************************************************** // //! \brief Set the IO Mode of an IO Port. @@ -904,7 +902,6 @@ IOCIntStatus(uint32_t ui32IOId) return (GPIO_getEventDio(ui32IOId)); } - //***************************************************************************** // //! \brief Setup an IO for standard GPIO input. @@ -1088,7 +1085,6 @@ extern void IOCPinTypeSsiSlave(uint32_t ui32Base, uint32_t ui32Rx, extern void IOCPinTypeI2c(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk); - //***************************************************************************** // //! \brief Configure an IO for AUX control. @@ -1120,88 +1116,88 @@ extern void IOCPinTypeAux(uint32_t ui32IOId); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_IOCPortConfigureSet -#undef IOCPortConfigureSet -#define IOCPortConfigureSet ROM_IOCPortConfigureSet +#undef IOCPortConfigureSet +#define IOCPortConfigureSet ROM_IOCPortConfigureSet #endif #ifdef ROM_IOCPortConfigureGet -#undef IOCPortConfigureGet -#define IOCPortConfigureGet ROM_IOCPortConfigureGet +#undef IOCPortConfigureGet +#define IOCPortConfigureGet ROM_IOCPortConfigureGet #endif #ifdef ROM_IOCIOShutdownSet -#undef IOCIOShutdownSet -#define IOCIOShutdownSet ROM_IOCIOShutdownSet +#undef IOCIOShutdownSet +#define IOCIOShutdownSet ROM_IOCIOShutdownSet #endif #ifdef ROM_IOCIOModeSet -#undef IOCIOModeSet -#define IOCIOModeSet ROM_IOCIOModeSet +#undef IOCIOModeSet +#define IOCIOModeSet ROM_IOCIOModeSet #endif #ifdef ROM_IOCIOIntSet -#undef IOCIOIntSet -#define IOCIOIntSet ROM_IOCIOIntSet +#undef IOCIOIntSet +#define IOCIOIntSet ROM_IOCIOIntSet #endif #ifdef ROM_IOCIOEvtSet -#undef IOCIOEvtSet -#define IOCIOEvtSet ROM_IOCIOEvtSet +#undef IOCIOEvtSet +#define IOCIOEvtSet ROM_IOCIOEvtSet #endif #ifdef ROM_IOCIOPortPullSet -#undef IOCIOPortPullSet -#define IOCIOPortPullSet ROM_IOCIOPortPullSet +#undef IOCIOPortPullSet +#define IOCIOPortPullSet ROM_IOCIOPortPullSet #endif #ifdef ROM_IOCIOHystSet -#undef IOCIOHystSet -#define IOCIOHystSet ROM_IOCIOHystSet +#undef IOCIOHystSet +#define IOCIOHystSet ROM_IOCIOHystSet #endif #ifdef ROM_IOCIOInputSet -#undef IOCIOInputSet -#define IOCIOInputSet ROM_IOCIOInputSet +#undef IOCIOInputSet +#define IOCIOInputSet ROM_IOCIOInputSet #endif #ifdef ROM_IOCIOSlewCtrlSet -#undef IOCIOSlewCtrlSet -#define IOCIOSlewCtrlSet ROM_IOCIOSlewCtrlSet +#undef IOCIOSlewCtrlSet +#define IOCIOSlewCtrlSet ROM_IOCIOSlewCtrlSet #endif #ifdef ROM_IOCIODrvStrengthSet -#undef IOCIODrvStrengthSet -#define IOCIODrvStrengthSet ROM_IOCIODrvStrengthSet +#undef IOCIODrvStrengthSet +#define IOCIODrvStrengthSet ROM_IOCIODrvStrengthSet #endif #ifdef ROM_IOCIOPortIdSet -#undef IOCIOPortIdSet -#define IOCIOPortIdSet ROM_IOCIOPortIdSet +#undef IOCIOPortIdSet +#define IOCIOPortIdSet ROM_IOCIOPortIdSet #endif #ifdef ROM_IOCIntEnable -#undef IOCIntEnable -#define IOCIntEnable ROM_IOCIntEnable +#undef IOCIntEnable +#define IOCIntEnable ROM_IOCIntEnable #endif #ifdef ROM_IOCIntDisable -#undef IOCIntDisable -#define IOCIntDisable ROM_IOCIntDisable +#undef IOCIntDisable +#define IOCIntDisable ROM_IOCIntDisable #endif #ifdef ROM_IOCPinTypeGpioInput -#undef IOCPinTypeGpioInput -#define IOCPinTypeGpioInput ROM_IOCPinTypeGpioInput +#undef IOCPinTypeGpioInput +#define IOCPinTypeGpioInput ROM_IOCPinTypeGpioInput #endif #ifdef ROM_IOCPinTypeGpioOutput -#undef IOCPinTypeGpioOutput -#define IOCPinTypeGpioOutput ROM_IOCPinTypeGpioOutput +#undef IOCPinTypeGpioOutput +#define IOCPinTypeGpioOutput ROM_IOCPinTypeGpioOutput #endif #ifdef ROM_IOCPinTypeUart -#undef IOCPinTypeUart -#define IOCPinTypeUart ROM_IOCPinTypeUart +#undef IOCPinTypeUart +#define IOCPinTypeUart ROM_IOCPinTypeUart #endif #ifdef ROM_IOCPinTypeSsiMaster -#undef IOCPinTypeSsiMaster -#define IOCPinTypeSsiMaster ROM_IOCPinTypeSsiMaster +#undef IOCPinTypeSsiMaster +#define IOCPinTypeSsiMaster ROM_IOCPinTypeSsiMaster #endif #ifdef ROM_IOCPinTypeSsiSlave -#undef IOCPinTypeSsiSlave -#define IOCPinTypeSsiSlave ROM_IOCPinTypeSsiSlave +#undef IOCPinTypeSsiSlave +#define IOCPinTypeSsiSlave ROM_IOCPinTypeSsiSlave #endif #ifdef ROM_IOCPinTypeI2c -#undef IOCPinTypeI2c -#define IOCPinTypeI2c ROM_IOCPinTypeI2c +#undef IOCPinTypeI2c +#define IOCPinTypeI2c ROM_IOCPinTypeI2c #endif #ifdef ROM_IOCPinTypeAux -#undef IOCPinTypeAux -#define IOCPinTypeAux ROM_IOCPinTypeAux +#undef IOCPinTypeAux +#define IOCPinTypeAux ROM_IOCPinTypeAux #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ioc_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ioc_doc.h index cd35eff..1e1a32e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ioc_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ioc_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: ioc_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: ioc_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup ioc_api //! @{ //! \section sec_ioc Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/osc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/osc.h index b504a3a..8254dd0 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/osc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/osc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: osc.h -* Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019) -* Revision: 54539 -* -* Description: Defines and prototypes for the system oscillator control. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: osc.h + * Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019) + * Revision: 54539 + * + * Description: Defines and prototypes for the system oscillator control. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,22 +55,21 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include #include "../inc/hw_aon_pmctl.h" #include "../inc/hw_ccfg.h" -#include "../inc/hw_fcfg1.h" -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" #include "../inc/hw_ddi.h" #include "../inc/hw_ddi_0_osc.h" -#include "rom.h" +#include "../inc/hw_fcfg1.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "ddi.h" #include "debug.h" +#include "rom.h" +#include +#include //***************************************************************************** // @@ -86,20 +85,20 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define OSCClockSourceSet NOROM_OSCClockSourceSet -#define OSCClockSourceGet NOROM_OSCClockSourceGet -#define OSCHF_GetStartupTime NOROM_OSCHF_GetStartupTime -#define OSCHF_TurnOnXosc NOROM_OSCHF_TurnOnXosc -#define OSCHF_AttemptToSwitchToXosc NOROM_OSCHF_AttemptToSwitchToXosc -#define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc -#define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude +#define OSCClockSourceSet NOROM_OSCClockSourceSet +#define OSCClockSourceGet NOROM_OSCClockSourceGet +#define OSCHF_GetStartupTime NOROM_OSCHF_GetStartupTime +#define OSCHF_TurnOnXosc NOROM_OSCHF_TurnOnXosc +#define OSCHF_AttemptToSwitchToXosc NOROM_OSCHF_AttemptToSwitchToXosc +#define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc +#define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude #define OSCHF_DebugGetExpectedAverageCrystalAmplitude NOROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude #define OSC_HPOSC_Debug_InitFreqOffsetParams NOROM_OSC_HPOSC_Debug_InitFreqOffsetParams #define OSC_HPOSCInitializeFrequencyOffsetParameters NOROM_OSC_HPOSCInitializeFrequencyOffsetParameters #define OSC_HPOSCRelativeFrequencyOffsetGet NOROM_OSC_HPOSCRelativeFrequencyOffsetGet -#define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray +#define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert NOROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert -#define OSC_HPOSCRtcCompensate NOROM_OSC_HPOSCRtcCompensate +#define OSC_HPOSCRtcCompensate NOROM_OSC_HPOSCRtcCompensate #endif //***************************************************************************** @@ -107,29 +106,29 @@ extern "C" // Defines for the High Frequency XTAL Power mode // //***************************************************************************** -#define LOW_POWER_XOSC 1 -#define HIGH_POWER_XOSC 0 +#define LOW_POWER_XOSC 1 +#define HIGH_POWER_XOSC 0 //***************************************************************************** // // Defines for the High Frequency XTAL Power mode // //***************************************************************************** -#define OSC_SRC_CLK_HF 0x00000001 -#define OSC_SRC_CLK_LF 0x00000004 +#define OSC_SRC_CLK_HF 0x00000001 +#define OSC_SRC_CLK_LF 0x00000004 -#define OSC_RCOSC_HF 0x00000000 -#define OSC_XOSC_HF 0x00000001 -#define OSC_RCOSC_LF 0x00000002 -#define OSC_XOSC_LF 0x00000003 +#define OSC_RCOSC_HF 0x00000000 +#define OSC_XOSC_HF 0x00000001 +#define OSC_RCOSC_LF 0x00000002 +#define OSC_XOSC_LF 0x00000003 -#define SCLK_HF_RCOSC_HF 0 -#define SCLK_HF_XOSC_HF 1 +#define SCLK_HF_RCOSC_HF 0 +#define SCLK_HF_XOSC_HF 1 -#define SCLK_LF_FROM_RCOSC_HF 0 -#define SCLK_LF_FROM_XOSC_HF 1 -#define SCLK_LF_FROM_RCOSC_LF 2 -#define SCLK_LF_FROM_XOSC_LF 3 +#define SCLK_LF_FROM_RCOSC_HF 0 +#define SCLK_LF_FROM_XOSC_HF 1 +#define SCLK_LF_FROM_RCOSC_LF 2 +#define SCLK_LF_FROM_XOSC_LF 3 //***************************************************************************** // @@ -176,11 +175,11 @@ OSCXHfPowerModeSet(uint32_t ui32Mode) // //***************************************************************************** __STATIC_INLINE void -OSCClockLossEventEnable( void ) +OSCClockLossEventEnable(void) { - DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, - DDI_0_OSC_CTL0_CLK_LOSS_EN_M, - DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 1 ); + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_CLK_LOSS_EN_M, + DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 1); } //***************************************************************************** @@ -199,11 +198,11 @@ OSCClockLossEventEnable( void ) // //***************************************************************************** __STATIC_INLINE void -OSCClockLossEventDisable( void ) +OSCClockLossEventDisable(void) { - DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, - DDI_0_OSC_CTL0_CLK_LOSS_EN_M, - DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 0 ); + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_CLK_LOSS_EN_M, + DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 0); } //***************************************************************************** @@ -287,8 +286,9 @@ OSCHfSourceReady(void) // Return the readiness of the HF clock source return (DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M, - DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S)) ? - true : false; + DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S)) + ? true + : false; } //***************************************************************************** @@ -352,8 +352,8 @@ OSC_IsHPOSCEnabled(void) { bool enabled = false; - if ((( HWREG(CCFG_BASE + CCFG_O_MODE_CONF) & CCFG_MODE_CONF_XOSC_FREQ_M) == CCFG_MODE_CONF_XOSC_FREQ_HPOSC) && - (( HWREG(FCFG1_BASE + FCFG1_O_OSC_CONF) & FCFG1_OSC_CONF_HPOSC_OPTION) == 0)) + if (((HWREG(CCFG_BASE + CCFG_O_MODE_CONF) & CCFG_MODE_CONF_XOSC_FREQ_M) == CCFG_MODE_CONF_XOSC_FREQ_HPOSC) && + ((HWREG(FCFG1_BASE + FCFG1_O_OSC_CONF) & FCFG1_OSC_CONF_HPOSC_OPTION) == 0)) { enabled = true; } @@ -382,8 +382,8 @@ OSC_IsHPOSCEnabledWithHfDerivedLfClock(void) // Check configuration by reading lower half of the 32-bit CTL0 register uint16_t regVal = HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0); - if ( ( ( regVal & DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M ) == DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF ) && - ( ( regVal & DDI_0_OSC_CTL0_HPOSC_MODE_EN_M ) == DDI_0_OSC_CTL0_HPOSC_MODE_EN ) ) + if (((regVal & DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M) == DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF) && + ((regVal & DDI_0_OSC_CTL0_HPOSC_MODE_EN_M) == DDI_0_OSC_CTL0_HPOSC_MODE_EN)) { enabled = true; } @@ -404,7 +404,7 @@ OSC_IsHPOSCEnabledWithHfDerivedLfClock(void) //! \return Time margin to use in microseconds. // //***************************************************************************** -extern uint32_t OSCHF_GetStartupTime( uint32_t timeUntilWakeupInMs ); +extern uint32_t OSCHF_GetStartupTime(uint32_t timeUntilWakeupInMs); //***************************************************************************** // @@ -416,7 +416,7 @@ extern uint32_t OSCHF_GetStartupTime( uint32_t timeUntilWakeupInMs ); //! \return None // //***************************************************************************** -extern void OSCHF_TurnOnXosc( void ); +extern void OSCHF_TurnOnXosc(void); //***************************************************************************** // @@ -431,7 +431,7 @@ extern void OSCHF_TurnOnXosc( void ); //! - \c false : Switching has not occurred. // //***************************************************************************** -extern bool OSCHF_AttemptToSwitchToXosc( void ); +extern bool OSCHF_AttemptToSwitchToXosc(void); //***************************************************************************** // @@ -443,7 +443,7 @@ extern bool OSCHF_AttemptToSwitchToXosc( void ); //! \return None // //***************************************************************************** -extern void OSCHF_SwitchToRcOscTurnOffXosc( void ); +extern void OSCHF_SwitchToRcOscTurnOffXosc(void); //***************************************************************************** // @@ -463,7 +463,7 @@ extern void OSCHF_SwitchToRcOscTurnOffXosc( void ); //! \sa OSCHF_DebugGetExpectedAverageCrystalAmplitude() // //***************************************************************************** -extern uint32_t OSCHF_DebugGetCrystalAmplitude( void ); +extern uint32_t OSCHF_DebugGetCrystalAmplitude(void); //***************************************************************************** // @@ -480,7 +480,7 @@ extern uint32_t OSCHF_DebugGetCrystalAmplitude( void ); //! \sa OSCHF_DebugGetCrystalAmplitude() // //***************************************************************************** -extern uint32_t OSCHF_DebugGetExpectedAverageCrystalAmplitude( void ); +extern uint32_t OSCHF_DebugGetExpectedAverageCrystalAmplitude(void); //***************************************************************************** // @@ -494,13 +494,13 @@ extern uint32_t OSCHF_DebugGetExpectedAverageCrystalAmplitude( void ); //***************************************************************************** typedef struct { - uint32_t meas_1 ; //!< Measurement set 1 (typically at room temp) - uint32_t meas_2 ; //!< Measurement set 2 (typically at high temp) - uint32_t meas_3 ; //!< Measurement set 3 (typically at low temp) - int32_t offsetD1 ; //!< Offset to measurement set 1 - int32_t offsetD2 ; //!< Offset to measurement set 2 - int32_t offsetD3 ; //!< Offset to measurement set 3 - int32_t polyP3 ; //!< The P3 polynomial + uint32_t meas_1; //!< Measurement set 1 (typically at room temp) + uint32_t meas_2; //!< Measurement set 2 (typically at high temp) + uint32_t meas_3; //!< Measurement set 3 (typically at low temp) + int32_t offsetD1; //!< Offset to measurement set 1 + int32_t offsetD2; //!< Offset to measurement set 2 + int32_t offsetD3; //!< Offset to measurement set 3 + int32_t polyP3; //!< The P3 polynomial } HposcDebugData_t; //***************************************************************************** @@ -514,7 +514,7 @@ typedef struct //! \sa OSC_HPOSCInitializeFrequencyOffsetParameters() // //***************************************************************************** -extern void OSC_HPOSC_Debug_InitFreqOffsetParams( HposcDebugData_t* pDebugData ); +extern void OSC_HPOSC_Debug_InitFreqOffsetParams(HposcDebugData_t* pDebugData); //***************************************************************************** // @@ -528,7 +528,7 @@ extern void OSC_HPOSC_Debug_InitFreqOffsetParams( HposcDebugData_t* pDebugData ) //! \sa OSC_HPOSC_Debug_InitFreqOffsetParams() // //***************************************************************************** -extern void OSC_HPOSCInitializeFrequencyOffsetParameters( void ); +extern void OSC_HPOSCInitializeFrequencyOffsetParameters(void); //***************************************************************************** // @@ -559,7 +559,7 @@ extern void OSC_HPOSCInitializeFrequencyOffsetParameters( void ); //! \sa OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert(), AONBatMonTemperatureGetDegC() // //***************************************************************************** -extern int32_t OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC ); +extern int32_t OSC_HPOSCRelativeFrequencyOffsetGet(int32_t tempDegC); //***************************************************************************** // @@ -577,7 +577,7 @@ extern int32_t OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC ); //! \return None // //***************************************************************************** -extern void OSC_AdjustXoscHfCapArray( int32_t capArrDelta ); +extern void OSC_AdjustXoscHfCapArray(int32_t capArrDelta); //***************************************************************************** // @@ -607,7 +607,7 @@ extern void OSC_AdjustXoscHfCapArray( int32_t capArrDelta ); //! \sa OSC_HPOSCRelativeFrequencyOffsetGet() // //***************************************************************************** -extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffset ); +extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert(int32_t HPOSC_RelFreqOffset); //***************************************************************************** // @@ -644,7 +644,7 @@ extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HP //! // //***************************************************************************** -extern void OSC_HPOSCRtcCompensate( int32_t relFreqOffset ); +extern void OSC_HPOSCRtcCompensate(int32_t relFreqOffset); //***************************************************************************** // @@ -655,60 +655,60 @@ extern void OSC_HPOSCRtcCompensate( int32_t relFreqOffset ); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_OSCClockSourceSet -#undef OSCClockSourceSet -#define OSCClockSourceSet ROM_OSCClockSourceSet +#undef OSCClockSourceSet +#define OSCClockSourceSet ROM_OSCClockSourceSet #endif #ifdef ROM_OSCClockSourceGet -#undef OSCClockSourceGet -#define OSCClockSourceGet ROM_OSCClockSourceGet +#undef OSCClockSourceGet +#define OSCClockSourceGet ROM_OSCClockSourceGet #endif #ifdef ROM_OSCHF_GetStartupTime -#undef OSCHF_GetStartupTime -#define OSCHF_GetStartupTime ROM_OSCHF_GetStartupTime +#undef OSCHF_GetStartupTime +#define OSCHF_GetStartupTime ROM_OSCHF_GetStartupTime #endif #ifdef ROM_OSCHF_TurnOnXosc -#undef OSCHF_TurnOnXosc -#define OSCHF_TurnOnXosc ROM_OSCHF_TurnOnXosc +#undef OSCHF_TurnOnXosc +#define OSCHF_TurnOnXosc ROM_OSCHF_TurnOnXosc #endif #ifdef ROM_OSCHF_AttemptToSwitchToXosc -#undef OSCHF_AttemptToSwitchToXosc -#define OSCHF_AttemptToSwitchToXosc ROM_OSCHF_AttemptToSwitchToXosc +#undef OSCHF_AttemptToSwitchToXosc +#define OSCHF_AttemptToSwitchToXosc ROM_OSCHF_AttemptToSwitchToXosc #endif #ifdef ROM_OSCHF_SwitchToRcOscTurnOffXosc -#undef OSCHF_SwitchToRcOscTurnOffXosc -#define OSCHF_SwitchToRcOscTurnOffXosc ROM_OSCHF_SwitchToRcOscTurnOffXosc +#undef OSCHF_SwitchToRcOscTurnOffXosc +#define OSCHF_SwitchToRcOscTurnOffXosc ROM_OSCHF_SwitchToRcOscTurnOffXosc #endif #ifdef ROM_OSCHF_DebugGetCrystalAmplitude -#undef OSCHF_DebugGetCrystalAmplitude -#define OSCHF_DebugGetCrystalAmplitude ROM_OSCHF_DebugGetCrystalAmplitude +#undef OSCHF_DebugGetCrystalAmplitude +#define OSCHF_DebugGetCrystalAmplitude ROM_OSCHF_DebugGetCrystalAmplitude #endif #ifdef ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude -#undef OSCHF_DebugGetExpectedAverageCrystalAmplitude +#undef OSCHF_DebugGetExpectedAverageCrystalAmplitude #define OSCHF_DebugGetExpectedAverageCrystalAmplitude ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude #endif #ifdef ROM_OSC_HPOSC_Debug_InitFreqOffsetParams -#undef OSC_HPOSC_Debug_InitFreqOffsetParams +#undef OSC_HPOSC_Debug_InitFreqOffsetParams #define OSC_HPOSC_Debug_InitFreqOffsetParams ROM_OSC_HPOSC_Debug_InitFreqOffsetParams #endif #ifdef ROM_OSC_HPOSCInitializeFrequencyOffsetParameters -#undef OSC_HPOSCInitializeFrequencyOffsetParameters +#undef OSC_HPOSCInitializeFrequencyOffsetParameters #define OSC_HPOSCInitializeFrequencyOffsetParameters ROM_OSC_HPOSCInitializeFrequencyOffsetParameters #endif #ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetGet -#undef OSC_HPOSCRelativeFrequencyOffsetGet +#undef OSC_HPOSCRelativeFrequencyOffsetGet #define OSC_HPOSCRelativeFrequencyOffsetGet ROM_OSC_HPOSCRelativeFrequencyOffsetGet #endif #ifdef ROM_OSC_AdjustXoscHfCapArray -#undef OSC_AdjustXoscHfCapArray -#define OSC_AdjustXoscHfCapArray ROM_OSC_AdjustXoscHfCapArray +#undef OSC_AdjustXoscHfCapArray +#define OSC_AdjustXoscHfCapArray ROM_OSC_AdjustXoscHfCapArray #endif #ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert -#undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert +#undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert #endif #ifdef ROM_OSC_HPOSCRtcCompensate -#undef OSC_HPOSCRtcCompensate -#define OSC_HPOSCRtcCompensate ROM_OSC_HPOSCRtcCompensate +#undef OSC_HPOSCRtcCompensate +#define OSC_HPOSCRtcCompensate ROM_OSC_HPOSCRtcCompensate #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pka.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pka.h index d81fef3..d02c13b 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pka.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pka.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: pka.h -* Revised: 2018-07-19 15:07:05 +0200 (Thu, 19 Jul 2018) -* Revision: 52294 -* -* Description: PKA header file. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: pka.h + * Revised: 2018-07-19 15:07:05 +0200 (Thu, 19 Jul 2018) + * Revision: 52294 + * + * Description: PKA header file. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,18 +55,17 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" #include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" #include "../inc/hw_pka.h" #include "../inc/hw_pka_ram.h" +#include "../inc/hw_types.h" +#include "debug.h" #include "interrupt.h" #include "sys_ctrl.h" -#include "debug.h" #include //***************************************************************************** @@ -83,60 +82,56 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define PKAClearPkaRam NOROM_PKAClearPkaRam -#define PKAGetOpsStatus NOROM_PKAGetOpsStatus -#define PKAArrayAllZeros NOROM_PKAArrayAllZeros -#define PKAZeroOutArray NOROM_PKAZeroOutArray -#define PKABigNumModStart NOROM_PKABigNumModStart -#define PKABigNumModGetResult NOROM_PKABigNumModGetResult -#define PKABigNumDivideStart NOROM_PKABigNumDivideStart -#define PKABigNumDivideGetQuotient NOROM_PKABigNumDivideGetQuotient -#define PKABigNumDivideGetRemainder NOROM_PKABigNumDivideGetRemainder -#define PKABigNumCmpStart NOROM_PKABigNumCmpStart -#define PKABigNumCmpGetResult NOROM_PKABigNumCmpGetResult -#define PKABigNumInvModStart NOROM_PKABigNumInvModStart -#define PKABigNumInvModGetResult NOROM_PKABigNumInvModGetResult -#define PKABigNumMultiplyStart NOROM_PKABigNumMultiplyStart -#define PKABigNumMultGetResult NOROM_PKABigNumMultGetResult -#define PKABigNumAddStart NOROM_PKABigNumAddStart -#define PKABigNumAddGetResult NOROM_PKABigNumAddGetResult -#define PKABigNumSubStart NOROM_PKABigNumSubStart -#define PKABigNumSubGetResult NOROM_PKABigNumSubGetResult -#define PKAEccMultiplyStart NOROM_PKAEccMultiplyStart -#define PKAEccMontgomeryMultiplyStart NOROM_PKAEccMontgomeryMultiplyStart -#define PKAEccMultiplyGetResult NOROM_PKAEccMultiplyGetResult -#define PKAEccAddStart NOROM_PKAEccAddStart -#define PKAEccAddGetResult NOROM_PKAEccAddGetResult +#define PKAClearPkaRam NOROM_PKAClearPkaRam +#define PKAGetOpsStatus NOROM_PKAGetOpsStatus +#define PKAArrayAllZeros NOROM_PKAArrayAllZeros +#define PKAZeroOutArray NOROM_PKAZeroOutArray +#define PKABigNumModStart NOROM_PKABigNumModStart +#define PKABigNumModGetResult NOROM_PKABigNumModGetResult +#define PKABigNumDivideStart NOROM_PKABigNumDivideStart +#define PKABigNumDivideGetQuotient NOROM_PKABigNumDivideGetQuotient +#define PKABigNumDivideGetRemainder NOROM_PKABigNumDivideGetRemainder +#define PKABigNumCmpStart NOROM_PKABigNumCmpStart +#define PKABigNumCmpGetResult NOROM_PKABigNumCmpGetResult +#define PKABigNumInvModStart NOROM_PKABigNumInvModStart +#define PKABigNumInvModGetResult NOROM_PKABigNumInvModGetResult +#define PKABigNumMultiplyStart NOROM_PKABigNumMultiplyStart +#define PKABigNumMultGetResult NOROM_PKABigNumMultGetResult +#define PKABigNumAddStart NOROM_PKABigNumAddStart +#define PKABigNumAddGetResult NOROM_PKABigNumAddGetResult +#define PKABigNumSubStart NOROM_PKABigNumSubStart +#define PKABigNumSubGetResult NOROM_PKABigNumSubGetResult +#define PKAEccMultiplyStart NOROM_PKAEccMultiplyStart +#define PKAEccMontgomeryMultiplyStart NOROM_PKAEccMontgomeryMultiplyStart +#define PKAEccMultiplyGetResult NOROM_PKAEccMultiplyGetResult +#define PKAEccAddStart NOROM_PKAEccAddStart +#define PKAEccAddGetResult NOROM_PKAEccAddGetResult #define PKAEccVerifyPublicKeyWeierstrassStart NOROM_PKAEccVerifyPublicKeyWeierstrassStart #endif - - - //***************************************************************************** // // Function return values // //***************************************************************************** -#define PKA_STATUS_SUCCESS 0 //!< Success -#define PKA_STATUS_FAILURE 1 //!< Failure -#define PKA_STATUS_INVALID_PARAM 2 //!< Invalid parameter -#define PKA_STATUS_BUF_UNDERFLOW 3 //!< Buffer underflow -#define PKA_STATUS_RESULT_0 4 //!< Result is all zeros -#define PKA_STATUS_A_GREATER_THAN_B 5 //!< Big number compare return status if the first big number is greater than the second. -#define PKA_STATUS_A_LESS_THAN_B 6 //!< Big number compare return status if the first big number is less than the second. -#define PKA_STATUS_EQUAL 7 //!< Big number compare return status if the first big number is equal to the second. -#define PKA_STATUS_OPERATION_BUSY 8 //!< PKA operation is in progress. -#define PKA_STATUS_OPERATION_RDY 9 //!< No PKA operation is in progress. -#define PKA_STATUS_LOCATION_IN_USE 10 //!< Location in PKA RAM is not available -#define PKA_STATUS_X_ZERO 11 //!< X coordinate of public key is 0 -#define PKA_STATUS_Y_ZERO 12 //!< Y coordinate of public key is 0 -#define PKA_STATUS_X_LARGER_THAN_PRIME 13 //!< X coordinate of public key is larger than the curve prime -#define PKA_STATUS_Y_LARGER_THAN_PRIME 14 //!< Y coordinate of public key is larger than the curve prime -#define PKA_STATUS_POINT_NOT_ON_CURVE 15 //!< The public key is not on the specified elliptic curve -#define PKA_STATUS_RESULT_ADDRESS_INCORRECT 16 //!< The address of the result passed into one of the PKA*GetResult functions is incorrect -#define PKA_STATUS_POINT_AT_INFINITY 17 //!< The ECC operation resulted in the point at infinity - +#define PKA_STATUS_SUCCESS 0 //!< Success +#define PKA_STATUS_FAILURE 1 //!< Failure +#define PKA_STATUS_INVALID_PARAM 2 //!< Invalid parameter +#define PKA_STATUS_BUF_UNDERFLOW 3 //!< Buffer underflow +#define PKA_STATUS_RESULT_0 4 //!< Result is all zeros +#define PKA_STATUS_A_GREATER_THAN_B 5 //!< Big number compare return status if the first big number is greater than the second. +#define PKA_STATUS_A_LESS_THAN_B 6 //!< Big number compare return status if the first big number is less than the second. +#define PKA_STATUS_EQUAL 7 //!< Big number compare return status if the first big number is equal to the second. +#define PKA_STATUS_OPERATION_BUSY 8 //!< PKA operation is in progress. +#define PKA_STATUS_OPERATION_RDY 9 //!< No PKA operation is in progress. +#define PKA_STATUS_LOCATION_IN_USE 10 //!< Location in PKA RAM is not available +#define PKA_STATUS_X_ZERO 11 //!< X coordinate of public key is 0 +#define PKA_STATUS_Y_ZERO 12 //!< Y coordinate of public key is 0 +#define PKA_STATUS_X_LARGER_THAN_PRIME 13 //!< X coordinate of public key is larger than the curve prime +#define PKA_STATUS_Y_LARGER_THAN_PRIME 14 //!< Y coordinate of public key is larger than the curve prime +#define PKA_STATUS_POINT_NOT_ON_CURVE 15 //!< The public key is not on the specified elliptic curve +#define PKA_STATUS_RESULT_ADDRESS_INCORRECT 16 //!< The address of the result passed into one of the PKA*GetResult functions is incorrect +#define PKA_STATUS_POINT_AT_INFINITY 17 //!< The ECC operation resulted in the point at infinity //***************************************************************************** // @@ -201,32 +196,32 @@ extern "C" //***************************************************************************** typedef union { - uint8_t byte[28]; - uint32_t word[28 / sizeof(uint32_t)]; + uint8_t byte[28]; + uint32_t word[28 / sizeof(uint32_t)]; } PKA_EccParam224; typedef union { - uint8_t byte[32]; - uint32_t word[32 / sizeof(uint32_t)]; + uint8_t byte[32]; + uint32_t word[32 / sizeof(uint32_t)]; } PKA_EccParam256; typedef union { - uint8_t byte[48]; - uint32_t word[48 / sizeof(uint32_t)]; + uint8_t byte[48]; + uint32_t word[48 / sizeof(uint32_t)]; } PKA_EccParam384; typedef union { - uint8_t byte[64]; - uint32_t word[64 / sizeof(uint32_t)]; + uint8_t byte[64]; + uint32_t word[64 / sizeof(uint32_t)]; } PKA_EccParam512; typedef union { - uint8_t byte[68]; - uint32_t word[68 / sizeof(uint32_t)]; + uint8_t byte[68]; + uint32_t word[68 / sizeof(uint32_t)]; } PKA_EccParam521; //***************************************************************************** @@ -236,38 +231,36 @@ typedef union // //***************************************************************************** - typedef struct PKA_EccPoint224_ { - PKA_EccParam224 x; - PKA_EccParam224 y; + PKA_EccParam224 x; + PKA_EccParam224 y; } PKA_EccPoint224; typedef struct PKA_EccPoint256_ { - PKA_EccParam256 x; - PKA_EccParam256 y; + PKA_EccParam256 x; + PKA_EccParam256 y; } PKA_EccPoint256; typedef struct PKA_EccPoint384_ { - PKA_EccParam384 x; - PKA_EccParam384 y; + PKA_EccParam384 x; + PKA_EccParam384 y; } PKA_EccPoint384; typedef struct PKA_EccPoint512_ { - PKA_EccParam512 x; - PKA_EccParam512 y; + PKA_EccParam512 x; + PKA_EccParam512 y; } PKA_EccPoint512; typedef struct PKA_EccPoint521_ { - PKA_EccParam521 x; - PKA_EccParam521 y; + PKA_EccParam521 x; + PKA_EccParam521 y; } PKA_EccPoint521; - //***************************************************************************** // //! \brief X coordinate of the generator point of the NISTP224 curve. @@ -282,7 +275,6 @@ extern const PKA_EccPoint224 NISTP224_generator; //***************************************************************************** extern const PKA_EccParam224 NISTP224_prime; - //***************************************************************************** // //! \brief a constant of the NISTP224 curve when expressed in short @@ -291,7 +283,6 @@ extern const PKA_EccParam224 NISTP224_prime; //***************************************************************************** extern const PKA_EccParam224 NISTP224_a; - //***************************************************************************** // //! \brief b constant of the NISTP224 curve when expressed in short @@ -300,7 +291,6 @@ extern const PKA_EccParam224 NISTP224_a; //***************************************************************************** extern const PKA_EccParam224 NISTP224_b; - //***************************************************************************** // //! \brief Order of the NISTP224 curve. @@ -308,9 +298,6 @@ extern const PKA_EccParam224 NISTP224_b; //***************************************************************************** extern const PKA_EccParam224 NISTP224_order; - - - //***************************************************************************** // //! \brief X coordinate of the generator point of the NISTP256 curve. @@ -325,7 +312,6 @@ extern const PKA_EccPoint256 NISTP256_generator; //***************************************************************************** extern const PKA_EccParam256 NISTP256_prime; - //***************************************************************************** // //! \brief a constant of the NISTP256 curve when expressed in short @@ -334,7 +320,6 @@ extern const PKA_EccParam256 NISTP256_prime; //***************************************************************************** extern const PKA_EccParam256 NISTP256_a; - //***************************************************************************** // //! \brief b constant of the NISTP256 curve when expressed in short @@ -343,7 +328,6 @@ extern const PKA_EccParam256 NISTP256_a; //***************************************************************************** extern const PKA_EccParam256 NISTP256_b; - //***************************************************************************** // //! \brief Order of the NISTP256 curve. @@ -351,10 +335,6 @@ extern const PKA_EccParam256 NISTP256_b; //***************************************************************************** extern const PKA_EccParam256 NISTP256_order; - - - - //***************************************************************************** // //! \brief X coordinate of the generator point of the NISTP384 curve. @@ -369,7 +349,6 @@ extern const PKA_EccPoint384 NISTP384_generator; //***************************************************************************** extern const PKA_EccParam384 NISTP384_prime; - //***************************************************************************** // //! \brief a constant of the NISTP384 curve when expressed in short @@ -378,7 +357,6 @@ extern const PKA_EccParam384 NISTP384_prime; //***************************************************************************** extern const PKA_EccParam384 NISTP384_a; - //***************************************************************************** // //! \brief b constant of the NISTP384 curve when expressed in short @@ -387,7 +365,6 @@ extern const PKA_EccParam384 NISTP384_a; //***************************************************************************** extern const PKA_EccParam384 NISTP384_b; - //***************************************************************************** // //! \brief Order of the NISTP384 curve. @@ -395,9 +372,6 @@ extern const PKA_EccParam384 NISTP384_b; //***************************************************************************** extern const PKA_EccParam384 NISTP384_order; - - - //***************************************************************************** // //! \brief X coordinate of the generator point of the NISTP521 curve. @@ -412,7 +386,6 @@ extern const PKA_EccPoint521 NISTP521_generator; //***************************************************************************** extern const PKA_EccParam521 NISTP521_prime; - //***************************************************************************** // //! \brief a constant of the NISTP521 curve when expressed in short @@ -421,7 +394,6 @@ extern const PKA_EccParam521 NISTP521_prime; //***************************************************************************** extern const PKA_EccParam521 NISTP521_a; - //***************************************************************************** // //! \brief b constant of the NISTP521 curve when expressed in short @@ -430,7 +402,6 @@ extern const PKA_EccParam521 NISTP521_a; //***************************************************************************** extern const PKA_EccParam521 NISTP521_b; - //***************************************************************************** // //! \brief Order of the NISTP521 curve. @@ -438,9 +409,6 @@ extern const PKA_EccParam521 NISTP521_b; //***************************************************************************** extern const PKA_EccParam521 NISTP521_order; - - - //***************************************************************************** // //! \brief X coordinate of the generator point of the BrainpoolP256R1 curve. @@ -455,7 +423,6 @@ extern const PKA_EccPoint256 BrainpoolP256R1_generator; //***************************************************************************** extern const PKA_EccParam256 BrainpoolP256R1_prime; - //***************************************************************************** // //! \brief a constant of the BrainpoolP256R1 curve when expressed in short @@ -464,7 +431,6 @@ extern const PKA_EccParam256 BrainpoolP256R1_prime; //***************************************************************************** extern const PKA_EccParam256 BrainpoolP256R1_a; - //***************************************************************************** // //! \brief b constant of the BrainpoolP256R1 curve when expressed in short @@ -473,7 +439,6 @@ extern const PKA_EccParam256 BrainpoolP256R1_a; //***************************************************************************** extern const PKA_EccParam256 BrainpoolP256R1_b; - //***************************************************************************** // //! \brief Order of the BrainpoolP256R1 curve. @@ -481,9 +446,6 @@ extern const PKA_EccParam256 BrainpoolP256R1_b; //***************************************************************************** extern const PKA_EccParam256 BrainpoolP256R1_order; - - - //***************************************************************************** // //! \brief X coordinate of the generator point of the BrainpoolP384R1 curve. @@ -498,7 +460,6 @@ extern const PKA_EccPoint384 BrainpoolP384R1_generator; //***************************************************************************** extern const PKA_EccParam384 BrainpoolP384R1_prime; - //***************************************************************************** // //! \brief a constant of the BrainpoolP384R1 curve when expressed in short @@ -507,7 +468,6 @@ extern const PKA_EccParam384 BrainpoolP384R1_prime; //***************************************************************************** extern const PKA_EccParam384 BrainpoolP384R1_a; - //***************************************************************************** // //! \brief b constant of the BrainpoolP384R1 curve when expressed in short @@ -516,7 +476,6 @@ extern const PKA_EccParam384 BrainpoolP384R1_a; //***************************************************************************** extern const PKA_EccParam384 BrainpoolP384R1_b; - //***************************************************************************** // //! \brief Order of the BrainpoolP384R1 curve. @@ -524,8 +483,6 @@ extern const PKA_EccParam384 BrainpoolP384R1_b; //***************************************************************************** extern const PKA_EccParam384 BrainpoolP384R1_order; - - //***************************************************************************** // //! \brief X coordinate of the generator point of the BrainpoolP512R1 curve. @@ -540,7 +497,6 @@ extern const PKA_EccPoint512 BrainpoolP512R1_generator; //***************************************************************************** extern const PKA_EccParam512 BrainpoolP512R1_prime; - //***************************************************************************** // //! \brief a constant of the BrainpoolP512R1 curve when expressed in short @@ -549,7 +505,6 @@ extern const PKA_EccParam512 BrainpoolP512R1_prime; //***************************************************************************** extern const PKA_EccParam512 BrainpoolP512R1_a; - //***************************************************************************** // //! \brief b constant of the BrainpoolP512R1 curve when expressed in short @@ -558,7 +513,6 @@ extern const PKA_EccParam512 BrainpoolP512R1_a; //***************************************************************************** extern const PKA_EccParam512 BrainpoolP512R1_b; - //***************************************************************************** // //! \brief Order of the BrainpoolP512R1 curve. @@ -566,8 +520,6 @@ extern const PKA_EccParam512 BrainpoolP512R1_b; //***************************************************************************** extern const PKA_EccParam512 BrainpoolP512R1_order; - - //***************************************************************************** // //! \brief X coordinate of the generator point of the Curve25519 curve. @@ -582,7 +534,6 @@ extern const PKA_EccPoint256 Curve25519_generator; //***************************************************************************** extern const PKA_EccParam256 Curve25519_prime; - //***************************************************************************** // //! \brief a constant of the Curve25519 curve when expressed in Montgomery @@ -591,7 +542,6 @@ extern const PKA_EccParam256 Curve25519_prime; //***************************************************************************** extern const PKA_EccParam256 Curve25519_a; - //***************************************************************************** // //! \brief b constant of the Curve25519 curve when expressed in Montgomery @@ -600,7 +550,6 @@ extern const PKA_EccParam256 Curve25519_a; //***************************************************************************** extern const PKA_EccParam256 Curve25519_b; - //***************************************************************************** // //! \brief Order of the Curve25519 curve. @@ -636,7 +585,7 @@ extern void PKAClearPkaRam(void); //! - \ref PKA_STATUS_OPERATION_RDY if the PKA operation is not in progress. // //***************************************************************************** -extern uint32_t PKAGetOpsStatus(void); +extern uint32_t PKAGetOpsStatus(void); //***************************************************************************** // @@ -691,7 +640,7 @@ extern void PKAZeroOutArray(const uint8_t* array, uint32_t arrayLength); //! \sa PKABigNumModGetResult() // //***************************************************************************** -extern uint32_t PKABigNumModStart(const uint8_t* bigNum, uint32_t bigNumLength, const uint8_t* modulus, uint32_t modulusLength, uint32_t* resultPKAMemAddr); +extern uint32_t PKABigNumModStart(const uint8_t* bigNum, uint32_t bigNumLength, const uint8_t* modulus, uint32_t modulusLength, uint32_t* resultPKAMemAddr); //***************************************************************************** // @@ -721,7 +670,7 @@ extern uint32_t PKABigNumModStart(const uint8_t* bigNum, uint32_t bigNumLength, //! \sa PKABigNumModStart() // //***************************************************************************** -extern uint32_t PKABigNumModGetResult(uint8_t* resultBuf, uint32_t length, uint32_t resultPKAMemAddr); +extern uint32_t PKABigNumModGetResult(uint8_t* resultBuf, uint32_t length, uint32_t resultPKAMemAddr); //***************************************************************************** // @@ -839,7 +788,7 @@ extern uint32_t PKABigNumDivideGetRemainder(uint8_t* resultBuf, uint32_t* length //! \sa PKABigNumCmpGetResult() // //***************************************************************************** -extern uint32_t PKABigNumCmpStart(const uint8_t* bigNum1, const uint8_t* bigNum2, uint32_t length); +extern uint32_t PKABigNumCmpStart(const uint8_t* bigNum1, const uint8_t* bigNum2, uint32_t length); //***************************************************************************** // @@ -857,7 +806,7 @@ extern uint32_t PKABigNumCmpStart(const uint8_t* bigNum1, const uint8_t* bigNum //! \sa PKABigNumCmpStart() // //***************************************************************************** -extern uint32_t PKABigNumCmpGetResult(void); +extern uint32_t PKABigNumCmpGetResult(void); //***************************************************************************** // @@ -887,8 +836,7 @@ extern uint32_t PKABigNumCmpGetResult(void); //! \sa PKABigNumInvModGetResult() // //***************************************************************************** -extern uint32_t PKABigNumInvModStart(const uint8_t* bigNum, uint32_t bigNumLength, const uint8_t* modulus, uint32_t modulusLength, uint32_t* resultPKAMemAddr); - +extern uint32_t PKABigNumInvModStart(const uint8_t* bigNum, uint32_t bigNumLength, const uint8_t* modulus, uint32_t modulusLength, uint32_t* resultPKAMemAddr); //***************************************************************************** // @@ -918,8 +866,7 @@ extern uint32_t PKABigNumInvModStart(const uint8_t* bigNum, uint32_t bigNumLeng //! \sa PKABigNumInvModStart() // //***************************************************************************** -extern uint32_t PKABigNumInvModGetResult(uint8_t* resultBuf, uint32_t length, uint32_t resultPKAMemAddr); - +extern uint32_t PKABigNumInvModGetResult(uint8_t* resultBuf, uint32_t length, uint32_t resultPKAMemAddr); //***************************************************************************** // @@ -946,8 +893,7 @@ extern uint32_t PKABigNumInvModGetResult(uint8_t* resultBuf, uint32_t length, u //! \sa PKABigNumMultGetResult() // //***************************************************************************** -extern uint32_t PKABigNumMultiplyStart(const uint8_t* multiplicand, uint32_t multiplicandLength, const uint8_t* multiplier, uint32_t multiplierLength, uint32_t* resultPKAMemAddr); - +extern uint32_t PKABigNumMultiplyStart(const uint8_t* multiplicand, uint32_t multiplicandLength, const uint8_t* multiplier, uint32_t multiplierLength, uint32_t* resultPKAMemAddr); //***************************************************************************** // @@ -978,7 +924,7 @@ extern uint32_t PKABigNumMultiplyStart(const uint8_t* multiplicand, uint32_t mu //! \sa PKABigNumMultiplyStart() // //***************************************************************************** -extern uint32_t PKABigNumMultGetResult(uint8_t* resultBuf, uint32_t* resultLength, uint32_t resultPKAMemAddr); +extern uint32_t PKABigNumMultGetResult(uint8_t* resultBuf, uint32_t* resultLength, uint32_t resultPKAMemAddr); //***************************************************************************** // @@ -1005,7 +951,7 @@ extern uint32_t PKABigNumMultGetResult(uint8_t* resultBuf, uint32_t* resultLeng //! \sa PKABigNumAddGetResult() // //***************************************************************************** -extern uint32_t PKABigNumAddStart(const uint8_t* bigNum1, uint32_t bigNum1Length, const uint8_t* bigNum2, uint32_t bigNum2Length, uint32_t* resultPKAMemAddr); +extern uint32_t PKABigNumAddStart(const uint8_t* bigNum1, uint32_t bigNum1Length, const uint8_t* bigNum2, uint32_t bigNum2Length, uint32_t* resultPKAMemAddr); //***************************************************************************** // @@ -1034,7 +980,7 @@ extern uint32_t PKABigNumAddStart(const uint8_t* bigNum1, uint32_t bigNum1Lengt //! \sa PKABigNumAddStart() // //***************************************************************************** -extern uint32_t PKABigNumAddGetResult(uint8_t* resultBuf, uint32_t* resultLength, uint32_t resultPKAMemAddr); +extern uint32_t PKABigNumAddGetResult(uint8_t* resultBuf, uint32_t* resultLength, uint32_t resultPKAMemAddr); //***************************************************************************** // @@ -1128,14 +1074,14 @@ extern uint32_t PKABigNumSubGetResult(uint8_t* resultBuf, uint32_t* resultLength //! \sa PKAEccMultiplyGetResult() // //***************************************************************************** -extern uint32_t PKAEccMultiplyStart(const uint8_t* scalar, - const uint8_t* curvePointX, - const uint8_t* curvePointY, - const uint8_t* prime, - const uint8_t* a, - const uint8_t* b, - uint32_t length, - uint32_t* resultPKAMemAddr); +extern uint32_t PKAEccMultiplyStart(const uint8_t* scalar, + const uint8_t* curvePointX, + const uint8_t* curvePointY, + const uint8_t* prime, + const uint8_t* a, + const uint8_t* b, + uint32_t length, + uint32_t* resultPKAMemAddr); //***************************************************************************** // @@ -1167,11 +1113,11 @@ extern uint32_t PKAEccMultiplyStart(const uint8_t* scalar, // //***************************************************************************** extern uint32_t PKAEccMontgomeryMultiplyStart(const uint8_t* scalar, - const uint8_t* curvePointX, - const uint8_t* prime, - const uint8_t* a, - uint32_t length, - uint32_t* resultPKAMemAddr); + const uint8_t* curvePointX, + const uint8_t* prime, + const uint8_t* a, + uint32_t length, + uint32_t* resultPKAMemAddr); //***************************************************************************** // @@ -1202,7 +1148,7 @@ extern uint32_t PKAEccMontgomeryMultiplyStart(const uint8_t* scalar, //! \sa PKAEccMultiplyStart() // //***************************************************************************** -extern uint32_t PKAEccMultiplyGetResult(uint8_t* curvePointX, uint8_t* curvePointY, uint32_t resultPKAMemAddr, uint32_t length); +extern uint32_t PKAEccMultiplyGetResult(uint8_t* curvePointX, uint8_t* curvePointY, uint32_t resultPKAMemAddr, uint32_t length); //***************************************************************************** // @@ -1242,14 +1188,14 @@ extern uint32_t PKAEccMultiplyGetResult(uint8_t* curvePointX, uint8_t* curvePoi //! \sa PKAEccAddGetResult() // //***************************************************************************** -extern uint32_t PKAEccAddStart(const uint8_t* curvePoint1X, - const uint8_t* curvePoint1Y, - const uint8_t* curvePoint2X, - const uint8_t* curvePoint2Y, - const uint8_t* prime, - const uint8_t* a, - uint32_t length, - uint32_t* resultPKAMemAddr); +extern uint32_t PKAEccAddStart(const uint8_t* curvePoint1X, + const uint8_t* curvePoint1Y, + const uint8_t* curvePoint2X, + const uint8_t* curvePoint2Y, + const uint8_t* prime, + const uint8_t* a, + uint32_t length, + uint32_t* resultPKAMemAddr); //***************************************************************************** // @@ -1279,8 +1225,7 @@ extern uint32_t PKAEccAddStart(const uint8_t* curvePoint1X, //! \sa PKAEccAddStart() // //***************************************************************************** -extern uint32_t PKAEccAddGetResult(uint8_t* curvePointX, uint8_t* curvePointY, uint32_t resultPKAMemAddr, uint32_t length); - +extern uint32_t PKAEccAddGetResult(uint8_t* curvePointX, uint8_t* curvePointY, uint32_t resultPKAMemAddr, uint32_t length); //***************************************************************************** // @@ -1328,12 +1273,12 @@ extern uint32_t PKAEccAddGetResult(uint8_t* curvePointX, uint8_t* curvePointY, // //***************************************************************************** extern uint32_t PKAEccVerifyPublicKeyWeierstrassStart(const uint8_t* curvePointX, - const uint8_t* curvePointY, - const uint8_t* prime, - const uint8_t* a, - const uint8_t* b, - const uint8_t* order, - uint32_t length); + const uint8_t* curvePointY, + const uint8_t* prime, + const uint8_t* a, + const uint8_t* b, + const uint8_t* order, + uint32_t length); //***************************************************************************** // @@ -1344,103 +1289,103 @@ extern uint32_t PKAEccVerifyPublicKeyWeierstrassStart(const uint8_t* curvePointX #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_PKAClearPkaRam -#undef PKAClearPkaRam -#define PKAClearPkaRam ROM_PKAClearPkaRam +#undef PKAClearPkaRam +#define PKAClearPkaRam ROM_PKAClearPkaRam #endif #ifdef ROM_PKAGetOpsStatus -#undef PKAGetOpsStatus -#define PKAGetOpsStatus ROM_PKAGetOpsStatus +#undef PKAGetOpsStatus +#define PKAGetOpsStatus ROM_PKAGetOpsStatus #endif #ifdef ROM_PKAArrayAllZeros -#undef PKAArrayAllZeros -#define PKAArrayAllZeros ROM_PKAArrayAllZeros +#undef PKAArrayAllZeros +#define PKAArrayAllZeros ROM_PKAArrayAllZeros #endif #ifdef ROM_PKAZeroOutArray -#undef PKAZeroOutArray -#define PKAZeroOutArray ROM_PKAZeroOutArray +#undef PKAZeroOutArray +#define PKAZeroOutArray ROM_PKAZeroOutArray #endif #ifdef ROM_PKABigNumModStart -#undef PKABigNumModStart -#define PKABigNumModStart ROM_PKABigNumModStart +#undef PKABigNumModStart +#define PKABigNumModStart ROM_PKABigNumModStart #endif #ifdef ROM_PKABigNumModGetResult -#undef PKABigNumModGetResult -#define PKABigNumModGetResult ROM_PKABigNumModGetResult +#undef PKABigNumModGetResult +#define PKABigNumModGetResult ROM_PKABigNumModGetResult #endif #ifdef ROM_PKABigNumDivideStart -#undef PKABigNumDivideStart -#define PKABigNumDivideStart ROM_PKABigNumDivideStart +#undef PKABigNumDivideStart +#define PKABigNumDivideStart ROM_PKABigNumDivideStart #endif #ifdef ROM_PKABigNumDivideGetQuotient -#undef PKABigNumDivideGetQuotient -#define PKABigNumDivideGetQuotient ROM_PKABigNumDivideGetQuotient +#undef PKABigNumDivideGetQuotient +#define PKABigNumDivideGetQuotient ROM_PKABigNumDivideGetQuotient #endif #ifdef ROM_PKABigNumDivideGetRemainder -#undef PKABigNumDivideGetRemainder -#define PKABigNumDivideGetRemainder ROM_PKABigNumDivideGetRemainder +#undef PKABigNumDivideGetRemainder +#define PKABigNumDivideGetRemainder ROM_PKABigNumDivideGetRemainder #endif #ifdef ROM_PKABigNumCmpStart -#undef PKABigNumCmpStart -#define PKABigNumCmpStart ROM_PKABigNumCmpStart +#undef PKABigNumCmpStart +#define PKABigNumCmpStart ROM_PKABigNumCmpStart #endif #ifdef ROM_PKABigNumCmpGetResult -#undef PKABigNumCmpGetResult -#define PKABigNumCmpGetResult ROM_PKABigNumCmpGetResult +#undef PKABigNumCmpGetResult +#define PKABigNumCmpGetResult ROM_PKABigNumCmpGetResult #endif #ifdef ROM_PKABigNumInvModStart -#undef PKABigNumInvModStart -#define PKABigNumInvModStart ROM_PKABigNumInvModStart +#undef PKABigNumInvModStart +#define PKABigNumInvModStart ROM_PKABigNumInvModStart #endif #ifdef ROM_PKABigNumInvModGetResult -#undef PKABigNumInvModGetResult -#define PKABigNumInvModGetResult ROM_PKABigNumInvModGetResult +#undef PKABigNumInvModGetResult +#define PKABigNumInvModGetResult ROM_PKABigNumInvModGetResult #endif #ifdef ROM_PKABigNumMultiplyStart -#undef PKABigNumMultiplyStart -#define PKABigNumMultiplyStart ROM_PKABigNumMultiplyStart +#undef PKABigNumMultiplyStart +#define PKABigNumMultiplyStart ROM_PKABigNumMultiplyStart #endif #ifdef ROM_PKABigNumMultGetResult -#undef PKABigNumMultGetResult -#define PKABigNumMultGetResult ROM_PKABigNumMultGetResult +#undef PKABigNumMultGetResult +#define PKABigNumMultGetResult ROM_PKABigNumMultGetResult #endif #ifdef ROM_PKABigNumAddStart -#undef PKABigNumAddStart -#define PKABigNumAddStart ROM_PKABigNumAddStart +#undef PKABigNumAddStart +#define PKABigNumAddStart ROM_PKABigNumAddStart #endif #ifdef ROM_PKABigNumAddGetResult -#undef PKABigNumAddGetResult -#define PKABigNumAddGetResult ROM_PKABigNumAddGetResult +#undef PKABigNumAddGetResult +#define PKABigNumAddGetResult ROM_PKABigNumAddGetResult #endif #ifdef ROM_PKABigNumSubStart -#undef PKABigNumSubStart -#define PKABigNumSubStart ROM_PKABigNumSubStart +#undef PKABigNumSubStart +#define PKABigNumSubStart ROM_PKABigNumSubStart #endif #ifdef ROM_PKABigNumSubGetResult -#undef PKABigNumSubGetResult -#define PKABigNumSubGetResult ROM_PKABigNumSubGetResult +#undef PKABigNumSubGetResult +#define PKABigNumSubGetResult ROM_PKABigNumSubGetResult #endif #ifdef ROM_PKAEccMultiplyStart -#undef PKAEccMultiplyStart -#define PKAEccMultiplyStart ROM_PKAEccMultiplyStart +#undef PKAEccMultiplyStart +#define PKAEccMultiplyStart ROM_PKAEccMultiplyStart #endif #ifdef ROM_PKAEccMontgomeryMultiplyStart -#undef PKAEccMontgomeryMultiplyStart -#define PKAEccMontgomeryMultiplyStart ROM_PKAEccMontgomeryMultiplyStart +#undef PKAEccMontgomeryMultiplyStart +#define PKAEccMontgomeryMultiplyStart ROM_PKAEccMontgomeryMultiplyStart #endif #ifdef ROM_PKAEccMultiplyGetResult -#undef PKAEccMultiplyGetResult -#define PKAEccMultiplyGetResult ROM_PKAEccMultiplyGetResult +#undef PKAEccMultiplyGetResult +#define PKAEccMultiplyGetResult ROM_PKAEccMultiplyGetResult #endif #ifdef ROM_PKAEccAddStart -#undef PKAEccAddStart -#define PKAEccAddStart ROM_PKAEccAddStart +#undef PKAEccAddStart +#define PKAEccAddStart ROM_PKAEccAddStart #endif #ifdef ROM_PKAEccAddGetResult -#undef PKAEccAddGetResult -#define PKAEccAddGetResult ROM_PKAEccAddGetResult +#undef PKAEccAddGetResult +#define PKAEccAddGetResult ROM_PKAEccAddGetResult #endif #ifdef ROM_PKAEccVerifyPublicKeyWeierstrassStart -#undef PKAEccVerifyPublicKeyWeierstrassStart +#undef PKAEccVerifyPublicKeyWeierstrassStart #define PKAEccVerifyPublicKeyWeierstrassStart ROM_PKAEccVerifyPublicKeyWeierstrassStart #endif #endif @@ -1454,7 +1399,7 @@ extern uint32_t PKAEccVerifyPublicKeyWeierstrassStart(const uint8_t* curvePointX } #endif -#endif // __PKA_H__ +#endif // __PKA_H__ //***************************************************************************** // diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pka_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pka_doc.h index 82d34c1..8b80ed8 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pka_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pka_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: pka_doc.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: pka_doc.h + * Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) + * Revision: 49096 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup pka_api //! @{ //! \section sec_pka Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.h index b97d38a..02b9b13 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: prcm.h -* Revised: 2018-10-23 10:19:14 +0200 (Tue, 23 Oct 2018) -* Revision: 52979 -* -* Description: Defines and prototypes for the PRCM -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: prcm.h + * Revised: 2018-10-23 10:19:14 +0200 (Tue, 23 Oct 2018) + * Revision: 52979 + * + * Description: Defines and prototypes for the PRCM + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,22 +55,20 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_nvic.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_prcm.h" -#include "../inc/hw_nvic.h" -#include "../inc/hw_aon_rtc.h" -#include "interrupt.h" -#include "debug.h" -#include "cpu.h" - //***************************************************************************** // @@ -86,22 +84,22 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet -#define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet -#define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet +#define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet +#define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet +#define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet #define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride -#define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource -#define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource -#define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn -#define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff -#define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable -#define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable -#define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable -#define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable -#define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable -#define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable -#define PRCMPowerDomainStatus NOROM_PRCMPowerDomainStatus -#define PRCMDeepSleep NOROM_PRCMDeepSleep +#define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource +#define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource +#define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn +#define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff +#define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable +#define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable +#define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable +#define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable +#define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable +#define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable +#define PRCMPowerDomainStatus NOROM_PRCMPowerDomainStatus +#define PRCMDeepSleep NOROM_PRCMDeepSleep #endif //***************************************************************************** @@ -109,24 +107,24 @@ extern "C" // Defines for the different System CPU power modes. // //***************************************************************************** -#define PRCM_RUN_MODE 0x00000001 -#define PRCM_SLEEP_MODE 0x00000002 -#define PRCM_DEEP_SLEEP_MODE 0x00000004 +#define PRCM_RUN_MODE 0x00000001 +#define PRCM_SLEEP_MODE 0x00000002 +#define PRCM_DEEP_SLEEP_MODE 0x00000004 //***************************************************************************** // // Defines used for setting the clock division factors // //***************************************************************************** -#define PRCM_CLOCK_DIV_1 PRCM_GPTCLKDIV_RATIO_DIV1 -#define PRCM_CLOCK_DIV_2 PRCM_GPTCLKDIV_RATIO_DIV2 -#define PRCM_CLOCK_DIV_4 PRCM_GPTCLKDIV_RATIO_DIV4 -#define PRCM_CLOCK_DIV_8 PRCM_GPTCLKDIV_RATIO_DIV8 -#define PRCM_CLOCK_DIV_16 PRCM_GPTCLKDIV_RATIO_DIV16 -#define PRCM_CLOCK_DIV_32 PRCM_GPTCLKDIV_RATIO_DIV32 -#define PRCM_CLOCK_DIV_64 PRCM_GPTCLKDIV_RATIO_DIV64 -#define PRCM_CLOCK_DIV_128 PRCM_GPTCLKDIV_RATIO_DIV128 -#define PRCM_CLOCK_DIV_256 PRCM_GPTCLKDIV_RATIO_DIV256 +#define PRCM_CLOCK_DIV_1 PRCM_GPTCLKDIV_RATIO_DIV1 +#define PRCM_CLOCK_DIV_2 PRCM_GPTCLKDIV_RATIO_DIV2 +#define PRCM_CLOCK_DIV_4 PRCM_GPTCLKDIV_RATIO_DIV4 +#define PRCM_CLOCK_DIV_8 PRCM_GPTCLKDIV_RATIO_DIV8 +#define PRCM_CLOCK_DIV_16 PRCM_GPTCLKDIV_RATIO_DIV16 +#define PRCM_CLOCK_DIV_32 PRCM_GPTCLKDIV_RATIO_DIV32 +#define PRCM_CLOCK_DIV_64 PRCM_GPTCLKDIV_RATIO_DIV64 +#define PRCM_CLOCK_DIV_128 PRCM_GPTCLKDIV_RATIO_DIV128 +#define PRCM_CLOCK_DIV_256 PRCM_GPTCLKDIV_RATIO_DIV256 //***************************************************************************** // @@ -134,32 +132,32 @@ extern "C" // domain // //***************************************************************************** -#define PRCM_DOMAIN_RFCORE 0x00000001 // RF Core domain ID for +#define PRCM_DOMAIN_RFCORE 0x00000001 // RF Core domain ID for // clock/power control. -#define PRCM_DOMAIN_SERIAL 0x00000002 // Serial domain ID for +#define PRCM_DOMAIN_SERIAL 0x00000002 // Serial domain ID for // clock/power control. -#define PRCM_DOMAIN_PERIPH 0x00000004 // Peripheral domain ID for +#define PRCM_DOMAIN_PERIPH 0x00000004 // Peripheral domain ID for // clock/power control. -#define PRCM_DOMAIN_SYSBUS 0x00000008 // Bus domain ID for clock/power +#define PRCM_DOMAIN_SYSBUS 0x00000008 // Bus domain ID for clock/power // control. -#define PRCM_DOMAIN_VIMS 0x00000010 // VIMS domain ID for clock/power +#define PRCM_DOMAIN_VIMS 0x00000010 // VIMS domain ID for clock/power // control. -#define PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP \ - 0x00020010 // For function PRCMPowerDomainOff() it is an option to +#define PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP \ + 0x00020010 // For function PRCMPowerDomainOff() it is an option to // select that VIMS power domain shall not power up // during the next wake up from uLDO (VIMS_MODE=0b10). -#define PRCM_DOMAIN_CPU 0x00000020 // CPU domain ID for clock/power +#define PRCM_DOMAIN_CPU 0x00000020 // CPU domain ID for clock/power // control. -#define PRCM_DOMAIN_TIMER 0x00000040 // GPT domain ID for clock +#define PRCM_DOMAIN_TIMER 0x00000040 // GPT domain ID for clock // control. -#define PRCM_DOMAIN_CLKCTRL 0x00000080 // Clock Control domain ID for +#define PRCM_DOMAIN_CLKCTRL 0x00000080 // Clock Control domain ID for // clock/power control. -#define PRCM_DOMAIN_MCU 0x00000100 // Reset control for entire MCU +#define PRCM_DOMAIN_MCU 0x00000100 // Reset control for entire MCU // domain. -#define PRCM_DOMAIN_POWER_OFF 0x00000002 // The domain is powered off -#define PRCM_DOMAIN_POWER_ON 0x00000001 // The domain is powered on -#define PRCM_DOMAIN_POWER_DOWN_READY \ - 0x00000000 // The domain is ready to be +#define PRCM_DOMAIN_POWER_OFF 0x00000002 // The domain is powered off +#define PRCM_DOMAIN_POWER_ON 0x00000001 // The domain is powered on +#define PRCM_DOMAIN_POWER_DOWN_READY \ + 0x00000000 // The domain is ready to be // powered down. //***************************************************************************** @@ -167,21 +165,21 @@ extern "C" // Defines for setting up the audio interface in the I2S module. // //***************************************************************************** -#define PRCM_WCLK_NEG_EDGE 0x00000008 -#define PRCM_WCLK_POS_EDGE 0x00000000 -#define PRCM_WCLK_SINGLE_PHASE 0x00000000 -#define PRCM_WCLK_DUAL_PHASE 0x00000002 -#define PRCM_WCLK_USER_DEF 0x00000004 -#define PRCM_I2S_WCLK_NEG_EDGE 0 -#define PRCM_I2S_WCLK_POS_EDGE 1 -#define PRCM_I2S_WCLK_SINGLE_PHASE 0 -#define PRCM_I2S_WCLK_DUAL_PHASE 1 -#define PRCM_I2S_WCLK_USER_DEF 2 +#define PRCM_WCLK_NEG_EDGE 0x00000008 +#define PRCM_WCLK_POS_EDGE 0x00000000 +#define PRCM_WCLK_SINGLE_PHASE 0x00000000 +#define PRCM_WCLK_DUAL_PHASE 0x00000002 +#define PRCM_WCLK_USER_DEF 0x00000004 +#define PRCM_I2S_WCLK_NEG_EDGE 0 +#define PRCM_I2S_WCLK_POS_EDGE 1 +#define PRCM_I2S_WCLK_SINGLE_PHASE 0 +#define PRCM_I2S_WCLK_DUAL_PHASE 1 +#define PRCM_I2S_WCLK_USER_DEF 2 -#define I2S_SAMPLE_RATE_16K 0x00000001 -#define I2S_SAMPLE_RATE_24K 0x00000002 -#define I2S_SAMPLE_RATE_32K 0x00000004 -#define I2S_SAMPLE_RATE_48K 0x00000008 +#define I2S_SAMPLE_RATE_16K 0x00000001 +#define I2S_SAMPLE_RATE_24K 0x00000002 +#define I2S_SAMPLE_RATE_32K 0x00000004 +#define I2S_SAMPLE_RATE_48K 0x00000008 //***************************************************************************** // @@ -191,21 +189,21 @@ extern "C" // bits[4:0] Defines the bit position within the register pointet on in [11:8] // //***************************************************************************** -#define PRCM_PERIPH_TIMER0 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S )) // Peripheral ID for GPT module 0 -#define PRCM_PERIPH_TIMER1 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 1 )) // Peripheral ID for GPT module 1 -#define PRCM_PERIPH_TIMER2 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 2 )) // Peripheral ID for GPT module 2 -#define PRCM_PERIPH_TIMER3 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 3 )) // Peripheral ID for GPT module 3 -#define PRCM_PERIPH_SSI0 ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S )) // Peripheral ID for SSI module 0 -#define PRCM_PERIPH_SSI1 ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S + 1 )) // Peripheral ID for SSI module 1 -#define PRCM_PERIPH_UART0 ( 0x00000200 | ( PRCM_UARTCLKGR_CLK_EN_S )) // Peripheral ID for UART module 0 -#define PRCM_PERIPH_UART1 ( 0x00000200 | ( PRCM_UARTCLKGR_CLK_EN_S + 1 )) // Peripheral ID for UART module 1 -#define PRCM_PERIPH_I2C0 ( 0x00000300 | ( PRCM_I2CCLKGR_CLK_EN_S )) // Peripheral ID for I2C module 0 -#define PRCM_PERIPH_CRYPTO ( 0x00000400 | ( PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S )) // Peripheral ID for CRYPTO module -#define PRCM_PERIPH_TRNG ( 0x00000400 | ( PRCM_SECDMACLKGR_TRNG_CLK_EN_S )) // Peripheral ID for TRNG module -#define PRCM_PERIPH_PKA ( 0x00000400 | ( PRCM_SECDMACLKGR_PKA_CLK_EN_S )) // Peripheral ID for PKA module -#define PRCM_PERIPH_UDMA ( 0x00000400 | ( PRCM_SECDMACLKGR_DMA_CLK_EN_S )) // Peripheral ID for UDMA module -#define PRCM_PERIPH_GPIO ( 0x00000500 | ( PRCM_GPIOCLKGR_CLK_EN_S )) // Peripheral ID for GPIO module -#define PRCM_PERIPH_I2S ( 0x00000600 | ( PRCM_I2SCLKGR_CLK_EN_S )) // Peripheral ID for I2S module +#define PRCM_PERIPH_TIMER0 (0x00000000 | (PRCM_GPTCLKGR_CLK_EN_S)) // Peripheral ID for GPT module 0 +#define PRCM_PERIPH_TIMER1 (0x00000000 | (PRCM_GPTCLKGR_CLK_EN_S + 1)) // Peripheral ID for GPT module 1 +#define PRCM_PERIPH_TIMER2 (0x00000000 | (PRCM_GPTCLKGR_CLK_EN_S + 2)) // Peripheral ID for GPT module 2 +#define PRCM_PERIPH_TIMER3 (0x00000000 | (PRCM_GPTCLKGR_CLK_EN_S + 3)) // Peripheral ID for GPT module 3 +#define PRCM_PERIPH_SSI0 (0x00000100 | (PRCM_SSICLKGR_CLK_EN_S)) // Peripheral ID for SSI module 0 +#define PRCM_PERIPH_SSI1 (0x00000100 | (PRCM_SSICLKGR_CLK_EN_S + 1)) // Peripheral ID for SSI module 1 +#define PRCM_PERIPH_UART0 (0x00000200 | (PRCM_UARTCLKGR_CLK_EN_S)) // Peripheral ID for UART module 0 +#define PRCM_PERIPH_UART1 (0x00000200 | (PRCM_UARTCLKGR_CLK_EN_S + 1)) // Peripheral ID for UART module 1 +#define PRCM_PERIPH_I2C0 (0x00000300 | (PRCM_I2CCLKGR_CLK_EN_S)) // Peripheral ID for I2C module 0 +#define PRCM_PERIPH_CRYPTO (0x00000400 | (PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S)) // Peripheral ID for CRYPTO module +#define PRCM_PERIPH_TRNG (0x00000400 | (PRCM_SECDMACLKGR_TRNG_CLK_EN_S)) // Peripheral ID for TRNG module +#define PRCM_PERIPH_PKA (0x00000400 | (PRCM_SECDMACLKGR_PKA_CLK_EN_S)) // Peripheral ID for PKA module +#define PRCM_PERIPH_UDMA (0x00000400 | (PRCM_SECDMACLKGR_DMA_CLK_EN_S)) // Peripheral ID for UDMA module +#define PRCM_PERIPH_GPIO (0x00000500 | (PRCM_GPIOCLKGR_CLK_EN_S)) // Peripheral ID for GPIO module +#define PRCM_PERIPH_I2S (0x00000600 | (PRCM_I2SCLKGR_CLK_EN_S)) // Peripheral ID for I2S module //***************************************************************************** // @@ -230,20 +228,20 @@ extern "C" static bool PRCMPeripheralValid(uint32_t ui32Peripheral) { - return ((ui32Peripheral == PRCM_PERIPH_TIMER0) || - (ui32Peripheral == PRCM_PERIPH_TIMER1) || - (ui32Peripheral == PRCM_PERIPH_TIMER2) || - (ui32Peripheral == PRCM_PERIPH_TIMER3) || - (ui32Peripheral == PRCM_PERIPH_SSI0) || - (ui32Peripheral == PRCM_PERIPH_SSI1) || - (ui32Peripheral == PRCM_PERIPH_UART0) || - (ui32Peripheral == PRCM_PERIPH_UART1) || - (ui32Peripheral == PRCM_PERIPH_I2C0) || - (ui32Peripheral == PRCM_PERIPH_CRYPTO) || - (ui32Peripheral == PRCM_PERIPH_TRNG) || - (ui32Peripheral == PRCM_PERIPH_PKA) || - (ui32Peripheral == PRCM_PERIPH_UDMA) || - (ui32Peripheral == PRCM_PERIPH_GPIO) || + return ((ui32Peripheral == PRCM_PERIPH_TIMER0) || + (ui32Peripheral == PRCM_PERIPH_TIMER1) || + (ui32Peripheral == PRCM_PERIPH_TIMER2) || + (ui32Peripheral == PRCM_PERIPH_TIMER3) || + (ui32Peripheral == PRCM_PERIPH_SSI0) || + (ui32Peripheral == PRCM_PERIPH_SSI1) || + (ui32Peripheral == PRCM_PERIPH_UART0) || + (ui32Peripheral == PRCM_PERIPH_UART1) || + (ui32Peripheral == PRCM_PERIPH_I2C0) || + (ui32Peripheral == PRCM_PERIPH_CRYPTO) || + (ui32Peripheral == PRCM_PERIPH_TRNG) || + (ui32Peripheral == PRCM_PERIPH_PKA) || + (ui32Peripheral == PRCM_PERIPH_UDMA) || + (ui32Peripheral == PRCM_PERIPH_GPIO) || (ui32Peripheral == PRCM_PERIPH_I2S)); } #endif @@ -366,11 +364,11 @@ PRCMMcuUldoConfigure(uint32_t ui32Enable) // //***************************************************************************** __STATIC_INLINE void -PRCMGPTimerClockDivisionSet( uint32_t clkDiv ) +PRCMGPTimerClockDivisionSet(uint32_t clkDiv) { - ASSERT( clkDiv <= PRCM_GPTCLKDIV_RATIO_DIV256 ); + ASSERT(clkDiv <= PRCM_GPTCLKDIV_RATIO_DIV256); - HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV ) = clkDiv; + HWREG(PRCM_BASE + PRCM_O_GPTCLKDIV) = clkDiv; } //***************************************************************************** @@ -394,12 +392,11 @@ PRCMGPTimerClockDivisionSet( uint32_t clkDiv ) // //***************************************************************************** __STATIC_INLINE uint32_t -PRCMGPTimerClockDivisionGet( void ) +PRCMGPTimerClockDivisionGet(void) { - return ( HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV )); + return (HWREG(PRCM_BASE + PRCM_O_GPTCLKDIV)); } - //***************************************************************************** // //! \brief Enable the audio clock generation. @@ -499,7 +496,7 @@ extern void PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, //***************************************************************************** #ifndef DEPRECATED extern void PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, - uint32_t ui32BitDiv, uint32_t ui32WordDiv); + uint32_t ui32BitDiv, uint32_t ui32WordDiv); #endif //***************************************************************************** @@ -523,12 +520,11 @@ extern void PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui3 //! \return None //! //***************************************************************************** -extern void PRCMAudioClockConfigOverride -(uint8_t ui8SamplingEdge, - uint8_t ui8WCLKPhase, - uint32_t ui32MstDiv, - uint32_t ui32BitDiv, - uint32_t ui32WordDiv); +extern void PRCMAudioClockConfigOverride(uint8_t ui8SamplingEdge, + uint8_t ui8WCLKPhase, + uint32_t ui32MstDiv, + uint32_t ui32BitDiv, + uint32_t ui32WordDiv); //***************************************************************************** // @@ -605,8 +601,7 @@ __STATIC_INLINE bool PRCMLoadGet(void) { // Return the load status. - return ((HWREG(PRCM_BASE + PRCM_O_CLKLOADCTL) & PRCM_CLKLOADCTL_LOAD_DONE) ? - true : false); + return ((HWREG(PRCM_BASE + PRCM_O_CLKLOADCTL) & PRCM_CLKLOADCTL_LOAD_DONE) ? true : false); } //***************************************************************************** @@ -1070,10 +1065,11 @@ PRCMRfReady(void) { // Return the ready status of the RF Core. return ((HWREG(PRCM_BASE + PRCM_O_PDSTAT1RFC) & - PRCM_PDSTAT1RFC_ON) ? true : false); + PRCM_PDSTAT1RFC_ON) + ? true + : false); } - //***************************************************************************** // //! \brief Put the processor into sleep mode. @@ -1121,9 +1117,9 @@ extern void PRCMDeepSleep(void); // //***************************************************************************** __STATIC_INLINE void -PRCMCacheRetentionEnable( void ) +PRCMCacheRetentionEnable(void) { - HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) |= PRCM_RAMRETEN_VIMS_M; + HWREG(PRCM_BASE + PRCM_O_RAMRETEN) |= PRCM_RAMRETEN_VIMS_M; } //***************************************************************************** @@ -1136,12 +1132,11 @@ PRCMCacheRetentionEnable( void ) // //***************************************************************************** __STATIC_INLINE void -PRCMCacheRetentionDisable( void ) +PRCMCacheRetentionDisable(void) { - HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) &= ~PRCM_RAMRETEN_VIMS_M; + HWREG(PRCM_BASE + PRCM_O_RAMRETEN) &= ~PRCM_RAMRETEN_VIMS_M; } - //***************************************************************************** // // Support for DriverLib in ROM: @@ -1151,68 +1146,68 @@ PRCMCacheRetentionDisable( void ) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_PRCMInfClockConfigureSet -#undef PRCMInfClockConfigureSet -#define PRCMInfClockConfigureSet ROM_PRCMInfClockConfigureSet +#undef PRCMInfClockConfigureSet +#define PRCMInfClockConfigureSet ROM_PRCMInfClockConfigureSet #endif #ifdef ROM_PRCMInfClockConfigureGet -#undef PRCMInfClockConfigureGet -#define PRCMInfClockConfigureGet ROM_PRCMInfClockConfigureGet +#undef PRCMInfClockConfigureGet +#define PRCMInfClockConfigureGet ROM_PRCMInfClockConfigureGet #endif #ifdef ROM_PRCMAudioClockConfigSet -#undef PRCMAudioClockConfigSet -#define PRCMAudioClockConfigSet ROM_PRCMAudioClockConfigSet +#undef PRCMAudioClockConfigSet +#define PRCMAudioClockConfigSet ROM_PRCMAudioClockConfigSet #endif #ifdef ROM_PRCMAudioClockConfigSetOverride -#undef PRCMAudioClockConfigSetOverride +#undef PRCMAudioClockConfigSetOverride #define PRCMAudioClockConfigSetOverride ROM_PRCMAudioClockConfigSetOverride #endif #ifdef ROM_PRCMAudioClockInternalSource -#undef PRCMAudioClockInternalSource -#define PRCMAudioClockInternalSource ROM_PRCMAudioClockInternalSource +#undef PRCMAudioClockInternalSource +#define PRCMAudioClockInternalSource ROM_PRCMAudioClockInternalSource #endif #ifdef ROM_PRCMAudioClockExternalSource -#undef PRCMAudioClockExternalSource -#define PRCMAudioClockExternalSource ROM_PRCMAudioClockExternalSource +#undef PRCMAudioClockExternalSource +#define PRCMAudioClockExternalSource ROM_PRCMAudioClockExternalSource #endif #ifdef ROM_PRCMPowerDomainOn -#undef PRCMPowerDomainOn -#define PRCMPowerDomainOn ROM_PRCMPowerDomainOn +#undef PRCMPowerDomainOn +#define PRCMPowerDomainOn ROM_PRCMPowerDomainOn #endif #ifdef ROM_PRCMPowerDomainOff -#undef PRCMPowerDomainOff -#define PRCMPowerDomainOff ROM_PRCMPowerDomainOff +#undef PRCMPowerDomainOff +#define PRCMPowerDomainOff ROM_PRCMPowerDomainOff #endif #ifdef ROM_PRCMPeripheralRunEnable -#undef PRCMPeripheralRunEnable -#define PRCMPeripheralRunEnable ROM_PRCMPeripheralRunEnable +#undef PRCMPeripheralRunEnable +#define PRCMPeripheralRunEnable ROM_PRCMPeripheralRunEnable #endif #ifdef ROM_PRCMPeripheralRunDisable -#undef PRCMPeripheralRunDisable -#define PRCMPeripheralRunDisable ROM_PRCMPeripheralRunDisable +#undef PRCMPeripheralRunDisable +#define PRCMPeripheralRunDisable ROM_PRCMPeripheralRunDisable #endif #ifdef ROM_PRCMPeripheralSleepEnable -#undef PRCMPeripheralSleepEnable -#define PRCMPeripheralSleepEnable ROM_PRCMPeripheralSleepEnable +#undef PRCMPeripheralSleepEnable +#define PRCMPeripheralSleepEnable ROM_PRCMPeripheralSleepEnable #endif #ifdef ROM_PRCMPeripheralSleepDisable -#undef PRCMPeripheralSleepDisable -#define PRCMPeripheralSleepDisable ROM_PRCMPeripheralSleepDisable +#undef PRCMPeripheralSleepDisable +#define PRCMPeripheralSleepDisable ROM_PRCMPeripheralSleepDisable #endif #ifdef ROM_PRCMPeripheralDeepSleepEnable -#undef PRCMPeripheralDeepSleepEnable -#define PRCMPeripheralDeepSleepEnable ROM_PRCMPeripheralDeepSleepEnable +#undef PRCMPeripheralDeepSleepEnable +#define PRCMPeripheralDeepSleepEnable ROM_PRCMPeripheralDeepSleepEnable #endif #ifdef ROM_PRCMPeripheralDeepSleepDisable -#undef PRCMPeripheralDeepSleepDisable -#define PRCMPeripheralDeepSleepDisable ROM_PRCMPeripheralDeepSleepDisable +#undef PRCMPeripheralDeepSleepDisable +#define PRCMPeripheralDeepSleepDisable ROM_PRCMPeripheralDeepSleepDisable #endif #ifdef ROM_PRCMPowerDomainStatus -#undef PRCMPowerDomainStatus -#define PRCMPowerDomainStatus ROM_PRCMPowerDomainStatus +#undef PRCMPowerDomainStatus +#define PRCMPowerDomainStatus ROM_PRCMPowerDomainStatus #endif #ifdef ROM_PRCMDeepSleep -#undef PRCMDeepSleep -#define PRCMDeepSleep ROM_PRCMDeepSleep +#undef PRCMDeepSleep +#define PRCMDeepSleep ROM_PRCMDeepSleep #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.h index 734bba7..861bd51 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: pwr_ctrl.h -* Revised: 2017-11-02 15:41:14 +0100 (Thu, 02 Nov 2017) -* Revision: 50165 -* -* Description: Defines and prototypes for the System Power Control. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: pwr_ctrl.h + * Revised: 2017-11-02 15:41:14 +0100 (Thu, 02 Nov 2017) + * Revision: 50165 + * + * Description: Defines and prototypes for the System Power Control. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,25 +55,24 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" +#include "../inc/hw_adi_2_refsys.h" #include "../inc/hw_aon_pmctl.h" #include "../inc/hw_aon_rtc.h" -#include "../inc/hw_adi_2_refsys.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "adi.h" +#include "aon_ioc.h" +#include "cpu.h" #include "debug.h" #include "interrupt.h" #include "osc.h" -#include "cpu.h" #include "prcm.h" -#include "aon_ioc.h" -#include "adi.h" +#include +#include //***************************************************************************** // @@ -89,7 +88,7 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define PowerCtrlSourceSet NOROM_PowerCtrlSourceSet +#define PowerCtrlSourceSet NOROM_PowerCtrlSourceSet #endif //***************************************************************************** @@ -97,37 +96,37 @@ extern "C" // Defines for the system power states // //***************************************************************************** -#define PWRCTRL_ACTIVE 0x00000001 -#define PWRCTRL_STANDBY 0x00000002 -#define PWRCTRL_POWER_DOWN 0x00000004 -#define PWRCTRL_SHUTDOWN 0x00000008 +#define PWRCTRL_ACTIVE 0x00000001 +#define PWRCTRL_STANDBY 0x00000002 +#define PWRCTRL_POWER_DOWN 0x00000004 +#define PWRCTRL_SHUTDOWN 0x00000008 //***************************************************************************** // // Defines for the power configuration in the AON System Control 1.2 V // //***************************************************************************** -#define PWRCTRL_IOSEG3_ENABLE 0x00000800 -#define PWRCTRL_IOSEG2_ENABLE 0x00000400 -#define PWRCTRL_IOSEG3_DISABLE 0x00000200 -#define PWRCTRL_IOSEG2_DISABLE 0x00000100 -#define PWRCTRL_PWRSRC_DCDC 0x00000001 -#define PWRCTRL_PWRSRC_GLDO 0x00000000 -#define PWRCTRL_PWRSRC_ULDO 0x00000002 +#define PWRCTRL_IOSEG3_ENABLE 0x00000800 +#define PWRCTRL_IOSEG2_ENABLE 0x00000400 +#define PWRCTRL_IOSEG3_DISABLE 0x00000200 +#define PWRCTRL_IOSEG2_DISABLE 0x00000100 +#define PWRCTRL_PWRSRC_DCDC 0x00000001 +#define PWRCTRL_PWRSRC_GLDO 0x00000000 +#define PWRCTRL_PWRSRC_ULDO 0x00000002 //***************************************************************************** // // The following are defines for the various reset source for the device. // //***************************************************************************** -#define PWRCTRL_RST_POWER_ON 0x00000000 // Reset by power on -#define PWRCTRL_RST_PIN 0x00000001 // Pin reset -#define PWRCTRL_RST_VDDS_BOD 0x00000002 // VDDS Brown Out Detect -#define PWRCTRL_RST_VDD_BOD 0x00000003 // VDD Brown Out Detect -#define PWRCTRL_RST_VDDR_BOD 0x00000004 // VDDR Brown Out Detect -#define PWRCTRL_RST_CLK_LOSS 0x00000005 // Clock loss Reset -#define PWRCTRL_RST_SW_PIN 0x00000006 // SYSRESET or pin reset -#define PWRCTRL_RST_WARM 0x00000007 // Reset via PRCM warm reset request +#define PWRCTRL_RST_POWER_ON 0x00000000 // Reset by power on +#define PWRCTRL_RST_PIN 0x00000001 // Pin reset +#define PWRCTRL_RST_VDDS_BOD 0x00000002 // VDDS Brown Out Detect +#define PWRCTRL_RST_VDD_BOD 0x00000003 // VDD Brown Out Detect +#define PWRCTRL_RST_VDDR_BOD 0x00000004 // VDDR Brown Out Detect +#define PWRCTRL_RST_CLK_LOSS 0x00000005 // Clock loss Reset +#define PWRCTRL_RST_SW_PIN 0x00000006 // SYSRESET or pin reset +#define PWRCTRL_RST_WARM 0x00000007 // Reset via PRCM warm reset request //***************************************************************************** // @@ -222,9 +221,9 @@ __STATIC_INLINE uint32_t PowerCtrlResetSourceGet(void) { // Get the reset source. - return (( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & - AON_PMCTL_RESETCTL_RESET_SRC_M ) >> - AON_PMCTL_RESETCTL_RESET_SRC_S ) ; + return ((HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL) & + AON_PMCTL_RESETCTL_RESET_SRC_M) >> + AON_PMCTL_RESETCTL_RESET_SRC_S); } //***************************************************************************** @@ -277,8 +276,8 @@ PowerCtrlPadSleepDisable(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_PowerCtrlSourceSet -#undef PowerCtrlSourceSet -#define PowerCtrlSourceSet ROM_PowerCtrlSourceSet +#undef PowerCtrlSourceSet +#define PowerCtrlSourceSet ROM_PowerCtrlSourceSet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_cmd.h index f0c53ea..a3d9961 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_cmd.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_cmd.h @@ -1,56 +1,56 @@ /****************************************************************************** -* Filename: rf_ble_cmd.h -* Revised: 2018-07-31 20:13:42 +0200 (Tue, 31 Jul 2018) -* Revision: 18572 -* -* Description: CC13x2/CC26x2 API for Bluetooth Low Energy commands -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_ble_cmd.h + * Revised: 2018-07-31 20:13:42 +0200 (Tue, 31 Jul 2018) + * Revision: 18572 + * + * Description: CC13x2/CC26x2 API for Bluetooth Low Energy commands + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __BLE_CMD_H #define __BLE_CMD_H #ifndef __RFC_STRUCT - #define __RFC_STRUCT +#define __RFC_STRUCT #endif #ifndef __RFC_STRUCT_ATTR - #if defined(__GNUC__) - #define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) - #elif defined(__TI_ARM__) - #define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) - #else - #define __RFC_STRUCT_ATTR - #endif +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__((aligned(4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__((__packed__, aligned(4))) +#else +#define __RFC_STRUCT_ATTR +#endif #endif //! \addtogroup rfc @@ -59,9 +59,9 @@ //! \addtogroup ble_cmd //! @{ -#include -#include "rf_mailbox.h" #include "rf_common_cmd.h" +#include "rf_mailbox.h" +#include typedef struct __RFC_STRUCT rfc_bleRadioOp_s rfc_bleRadioOp_t; typedef struct __RFC_STRUCT rfc_ble5RadioOp_s rfc_ble5RadioOp_t; @@ -123,41 +123,41 @@ typedef struct __RFC_STRUCT rfc_ble5RxStatus_s rfc_ble5RxStatus_t; //! @{ struct __RFC_STRUCT rfc_bleRadioOp_s { - uint16_t commandNo; //!< The command ID number - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - uint8_t* pParams; //!< Pointer to command specific parameter structure - uint8_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + uint8_t* pParams; //!< Pointer to command specific parameter structure + uint8_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} @@ -166,56 +166,56 @@ struct __RFC_STRUCT rfc_bleRadioOp_s //! @{ struct __RFC_STRUCT rfc_ble5RadioOp_s { - uint16_t commandNo; //!< The command ID number - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct - { - uint8_t mainMode: 2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding: 6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - uint8_t* pParams; //!< Pointer to command specific parameter structure - uint8_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct + { + uint8_t mainMode : 2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding : 6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + uint8_t* pParams; //!< Pointer to command specific parameter structure + uint8_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} @@ -225,1404 +225,1404 @@ struct __RFC_STRUCT rfc_ble5RadioOp_s //! Command structure for Bluetooth commands which includes the optional field for 20-dBm PA TX power struct __RFC_STRUCT rfc_ble5Tx20RadioOp_s { - uint16_t commandNo; //!< The command ID number - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct - { - uint8_t mainMode: 2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding: 6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - uint8_t* pParams; //!< Pointer to command specific parameter structure - uint8_t* pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct + { + uint8_t mainMode : 2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding : 6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + uint8_t* pParams; //!< Pointer to command specific parameter structure + uint8_t* pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_SLAVE //! @{ -#define CMD_BLE_SLAVE 0x1801 +#define CMD_BLE_SLAVE 0x1801 //! BLE Slave Command struct __RFC_STRUCT rfc_CMD_BLE_SLAVE_s { - uint16_t commandNo; //!< The command ID number 0x1801 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleSlavePar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleMasterSlaveOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleSlavePar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleMasterSlaveOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_MASTER //! @{ -#define CMD_BLE_MASTER 0x1802 +#define CMD_BLE_MASTER 0x1802 //! BLE Master Command struct __RFC_STRUCT rfc_CMD_BLE_MASTER_s { - uint16_t commandNo; //!< The command ID number 0x1802 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleMasterPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleMasterSlaveOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleMasterPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleMasterSlaveOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_ADV //! @{ -#define CMD_BLE_ADV 0x1803 +#define CMD_BLE_ADV 0x1803 //! BLE Connectable Undirected Advertiser Command struct __RFC_STRUCT rfc_CMD_BLE_ADV_s { - uint16_t commandNo; //!< The command ID number 0x1803 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1803 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_ADV_DIR //! @{ -#define CMD_BLE_ADV_DIR 0x1804 +#define CMD_BLE_ADV_DIR 0x1804 //! BLE Connectable Directed Advertiser Command struct __RFC_STRUCT rfc_CMD_BLE_ADV_DIR_s { - uint16_t commandNo; //!< The command ID number 0x1804 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1804 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_ADV_NC //! @{ -#define CMD_BLE_ADV_NC 0x1805 +#define CMD_BLE_ADV_NC 0x1805 //! BLE Non-Connectable Advertiser Command struct __RFC_STRUCT rfc_CMD_BLE_ADV_NC_s { - uint16_t commandNo; //!< The command ID number 0x1805 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1805 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_ADV_SCAN //! @{ -#define CMD_BLE_ADV_SCAN 0x1806 +#define CMD_BLE_ADV_SCAN 0x1806 //! BLE Scannable Undirected Advertiser Command struct __RFC_STRUCT rfc_CMD_BLE_ADV_SCAN_s { - uint16_t commandNo; //!< The command ID number 0x1806 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1806 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_SCANNER //! @{ -#define CMD_BLE_SCANNER 0x1807 +#define CMD_BLE_SCANNER 0x1807 //! BLE Scanner Command struct __RFC_STRUCT rfc_CMD_BLE_SCANNER_s { - uint16_t commandNo; //!< The command ID number 0x1807 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleScannerPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleScannerOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1807 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleScannerPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleScannerOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_INITIATOR //! @{ -#define CMD_BLE_INITIATOR 0x1808 +#define CMD_BLE_INITIATOR 0x1808 //! BLE Initiator Command struct __RFC_STRUCT rfc_CMD_BLE_INITIATOR_s { - uint16_t commandNo; //!< The command ID number 0x1808 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleInitiatorPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleInitiatorOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1808 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleInitiatorPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleInitiatorOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_GENERIC_RX //! @{ -#define CMD_BLE_GENERIC_RX 0x1809 +#define CMD_BLE_GENERIC_RX 0x1809 //! BLE Generic Receiver Command struct __RFC_STRUCT rfc_CMD_BLE_GENERIC_RX_s { - uint16_t commandNo; //!< The command ID number 0x1809 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleGenericRxPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleGenericRxOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1809 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleGenericRxPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleGenericRxOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_TX_TEST //! @{ -#define CMD_BLE_TX_TEST 0x180A +#define CMD_BLE_TX_TEST 0x180A //! BLE PHY Test Transmitter Command struct __RFC_STRUCT rfc_CMD_BLE_TX_TEST_s { - uint16_t commandNo; //!< The command ID number 0x180A - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleTxTestPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleTxTestOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x180A + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleTxTestPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleTxTestOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_ADV_PAYLOAD //! @{ -#define CMD_BLE_ADV_PAYLOAD 0x1001 +#define CMD_BLE_ADV_PAYLOAD 0x1001 //! BLE Update Advertising Payload Command struct __RFC_STRUCT rfc_CMD_BLE_ADV_PAYLOAD_s { - uint16_t commandNo; //!< The command ID number 0x1001 - uint8_t payloadType; //!< \brief 0: Advertising data
- //!< 1: Scan response data - uint8_t newLen; //!< Length of the new payload - uint8_t* pNewData; //!< Pointer to the buffer containing the new data - rfc_bleAdvPar_t* pParams; //!< Pointer to the parameter structure to update + uint16_t commandNo; //!< The command ID number 0x1001 + uint8_t payloadType; //!< \brief 0: Advertising data
+ //!< 1: Scan response data + uint8_t newLen; //!< Length of the new payload + uint8_t* pNewData; //!< Pointer to the buffer containing the new data + rfc_bleAdvPar_t* pParams; //!< Pointer to the parameter structure to update } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE5_RADIO_SETUP //! @{ -#define CMD_BLE5_RADIO_SETUP 0x1820 +#define CMD_BLE5_RADIO_SETUP 0x1820 //! Bluetooth 5 Radio Setup Command for all PHYs struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_s { - uint16_t commandNo; //!< The command ID number 0x1820 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t mainMode: 2; //!< \brief PHY to use for non-BLE commands:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding: 1; //!< \brief Coding to use for TX if coded PHY is selected for non-BLE commands
- //!< 0: S = 8 (125 kbps)
- //!< 1: S = 2 (500 kbps) - } defaultPhy; - uint8_t loDivider; //!< LO divider setting to use. Supported values: 0 or 2. - struct - { - uint16_t frontEndMode: 3; //!< \brief 0x00: Differential mode
- //!< 0x01: Single-ended mode RFP
- //!< 0x02: Single-ended mode RFN
- //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
- //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
- //!< Others: Reserved - uint16_t biasMode: 1; //!< \brief 0: Internal bias
- //!< 1: External bias - uint16_t analogCfgMode: 6; //!< \brief 0x00: Write analog configuration.
- //!< Required first time after boot and when changing frequency band - //!< or front-end configuration
- //!< 0x2D: Keep analog configuration.
- //!< May be used after standby or when changing mode with the same frequency - //!< band and front-end configuration
- //!< Others: Reserved - uint16_t bNoFsPowerUp: 1; //!< \brief 0: Power up frequency synth
- //!< 1: Do not power up frequency synth - } config; //!< Configuration options - uint16_t txPower; //!< Default transmit power - uint32_t* pRegOverrideCommon; //!< \brief Pointer to a list of hardware and configuration registers to override during common - //!< initialization. If NULL, no override is used. - uint32_t* pRegOverride1Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting - //!< 1 Mbps PHY mode. If NULL, no override is used. - uint32_t* pRegOverride2Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting - //!< 2 Mbps PHY mode. If NULL, no override is used. - uint32_t* pRegOverrideCoded; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting - //!< coded PHY mode. If NULL, no override is used. + uint16_t commandNo; //!< The command ID number 0x1820 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t mainMode : 2; //!< \brief PHY to use for non-BLE commands:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding : 1; //!< \brief Coding to use for TX if coded PHY is selected for non-BLE commands
+ //!< 0: S = 8 (125 kbps)
+ //!< 1: S = 2 (500 kbps) + } defaultPhy; + uint8_t loDivider; //!< LO divider setting to use. Supported values: 0 or 2. + struct + { + uint16_t frontEndMode : 3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode : 1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode : 6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp : 1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Default transmit power + uint32_t* pRegOverrideCommon; //!< \brief Pointer to a list of hardware and configuration registers to override during common + //!< initialization. If NULL, no override is used. + uint32_t* pRegOverride1Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting + //!< 1 Mbps PHY mode. If NULL, no override is used. + uint32_t* pRegOverride2Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting + //!< 2 Mbps PHY mode. If NULL, no override is used. + uint32_t* pRegOverrideCoded; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting + //!< coded PHY mode. If NULL, no override is used. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE5_SLAVE //! @{ -#define CMD_BLE5_SLAVE 0x1821 +#define CMD_BLE5_SLAVE 0x1821 //! Bluetooth 5 Slave Command struct __RFC_STRUCT rfc_CMD_BLE5_SLAVE_s { - uint16_t commandNo; //!< The command ID number 0x1821 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct - { - uint8_t mainMode: 2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding: 6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_ble5SlavePar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleMasterSlaveOutput_t* pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. + uint16_t commandNo; //!< The command ID number 0x1821 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct + { + uint8_t mainMode : 2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding : 6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_ble5SlavePar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleMasterSlaveOutput_t* pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE5_MASTER //! @{ -#define CMD_BLE5_MASTER 0x1822 +#define CMD_BLE5_MASTER 0x1822 //! Bluetooth 5 Master Command struct __RFC_STRUCT rfc_CMD_BLE5_MASTER_s { - uint16_t commandNo; //!< The command ID number 0x1822 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct - { - uint8_t mainMode: 2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding: 6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_ble5MasterPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleMasterSlaveOutput_t* pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. + uint16_t commandNo; //!< The command ID number 0x1822 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct + { + uint8_t mainMode : 2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding : 6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_ble5MasterPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleMasterSlaveOutput_t* pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE5_ADV_EXT //! @{ -#define CMD_BLE5_ADV_EXT 0x1823 +#define CMD_BLE5_ADV_EXT 0x1823 //! Bluetooth 5 Extended Advertiser Command struct __RFC_STRUCT rfc_CMD_BLE5_ADV_EXT_s { - uint16_t commandNo; //!< The command ID number 0x1823 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct - { - uint8_t mainMode: 2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding: 6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_ble5AdvExtPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. + uint16_t commandNo; //!< The command ID number 0x1823 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct + { + uint8_t mainMode : 2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding : 6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_ble5AdvExtPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE5_ADV_AUX //! @{ -#define CMD_BLE5_ADV_AUX 0x1824 +#define CMD_BLE5_ADV_AUX 0x1824 //! Bluetooth 5 Secondary Channel Advertiser Command struct __RFC_STRUCT rfc_CMD_BLE5_ADV_AUX_s { - uint16_t commandNo; //!< The command ID number 0x1824 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct - { - uint8_t mainMode: 2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding: 6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_ble5AdvAuxPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. + uint16_t commandNo; //!< The command ID number 0x1824 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct + { + uint8_t mainMode : 2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding : 6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_ble5AdvAuxPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE5_SCANNER //! @{ -#define CMD_BLE5_SCANNER 0x1827 +#define CMD_BLE5_SCANNER 0x1827 //! Bluetooth 5 Scanner Command struct __RFC_STRUCT rfc_CMD_BLE5_SCANNER_s { - uint16_t commandNo; //!< The command ID number 0x1827 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct - { - uint8_t mainMode: 2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding: 6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_ble5ScannerPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_ble5ScanInitOutput_t* pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. + uint16_t commandNo; //!< The command ID number 0x1827 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct + { + uint8_t mainMode : 2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding : 6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_ble5ScannerPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_ble5ScanInitOutput_t* pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE5_INITIATOR //! @{ -#define CMD_BLE5_INITIATOR 0x1828 +#define CMD_BLE5_INITIATOR 0x1828 //! Bluetooth 5 Initiator Command struct __RFC_STRUCT rfc_CMD_BLE5_INITIATOR_s { - uint16_t commandNo; //!< The command ID number 0x1828 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct - { - uint8_t mainMode: 2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding: 6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_ble5InitiatorPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_ble5ScanInitOutput_t* pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. + uint16_t commandNo; //!< The command ID number 0x1828 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct + { + uint8_t mainMode : 2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding : 6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_ble5InitiatorPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_ble5ScanInitOutput_t* pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE5_GENERIC_RX //! @{ -#define CMD_BLE5_GENERIC_RX 0x1829 +#define CMD_BLE5_GENERIC_RX 0x1829 //! Bluetooth 5 Generic Receiver Command struct __RFC_STRUCT rfc_CMD_BLE5_GENERIC_RX_s { - uint16_t commandNo; //!< The command ID number 0x1829 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct - { - uint8_t mainMode: 2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding: 6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_bleGenericRxPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleGenericRxOutput_t* pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. + uint16_t commandNo; //!< The command ID number 0x1829 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct + { + uint8_t mainMode : 2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding : 6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_bleGenericRxPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleGenericRxOutput_t* pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE5_TX_TEST //! @{ -#define CMD_BLE5_TX_TEST 0x182A +#define CMD_BLE5_TX_TEST 0x182A //! Bluetooth 5 PHY Test Transmitter Command struct __RFC_STRUCT rfc_CMD_BLE5_TX_TEST_s { - uint16_t commandNo; //!< The command ID number 0x182A - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct - { - uint8_t mainMode: 2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding: 6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_bleTxTestPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleTxTestOutput_t* pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. + uint16_t commandNo; //!< The command ID number 0x182A + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct + { + uint8_t mainMode : 2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding : 6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_bleTxTestPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleTxTestOutput_t* pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE5_ADV //! @{ -#define CMD_BLE5_ADV 0x182B +#define CMD_BLE5_ADV 0x182B //! Bluetooth 5 Connectable Undirected Advertiser Command struct __RFC_STRUCT rfc_CMD_BLE5_ADV_s { - uint16_t commandNo; //!< The command ID number 0x182B - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct - { - uint8_t mainMode: 2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding: 6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. + uint16_t commandNo; //!< The command ID number 0x182B + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct + { + uint8_t mainMode : 2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding : 6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE5_ADV_DIR //! @{ -#define CMD_BLE5_ADV_DIR 0x182C +#define CMD_BLE5_ADV_DIR 0x182C //! Bluetooth 5 Connectable Directed Advertiser Command struct __RFC_STRUCT rfc_CMD_BLE5_ADV_DIR_s { - uint16_t commandNo; //!< The command ID number 0x182C - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct - { - uint8_t mainMode: 2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding: 6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. + uint16_t commandNo; //!< The command ID number 0x182C + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct + { + uint8_t mainMode : 2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding : 6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE5_ADV_NC //! @{ -#define CMD_BLE5_ADV_NC 0x182D +#define CMD_BLE5_ADV_NC 0x182D //! Bluetooth 5 Non-Connectable Advertiser Command struct __RFC_STRUCT rfc_CMD_BLE5_ADV_NC_s { - uint16_t commandNo; //!< The command ID number 0x182D - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct - { - uint8_t mainMode: 2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding: 6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. + uint16_t commandNo; //!< The command ID number 0x182D + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct + { + uint8_t mainMode : 2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding : 6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE5_ADV_SCAN //! @{ -#define CMD_BLE5_ADV_SCAN 0x182E +#define CMD_BLE5_ADV_SCAN 0x182E //! Bluetooth 5 Scannable Undirected Advertiser Command struct __RFC_STRUCT rfc_CMD_BLE5_ADV_SCAN_s { - uint16_t commandNo; //!< The command ID number 0x182E - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct - { - uint8_t mainMode: 2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding: 6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. + uint16_t commandNo; //!< The command ID number 0x182E + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel index
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + struct + { + uint8_t mainMode : 2; //!< \brief PHY to use:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding : 6; //!< \brief Coding to use for TX if coded PHY is selected. + //!< See the Technical Reference Manual for details. + } phyMode; + uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS + uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
+ //!< 0x0000: Use default TX power
+ //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command + //!< structure that includes tx20Power must be used) + rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure + uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
+ //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; + //!< overrides the one given in radio setup for the duration of the command.
+ //!< If tx20Power >= 0x10000000: Pointer to PA change override structure + //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
+ //!< For other values of txPower, this field is not accessed by the radio + //!< CPU and may be omitted from the structure. } __RFC_STRUCT_ATTR; //! @} @@ -1632,71 +1632,71 @@ struct __RFC_STRUCT rfc_CMD_BLE5_ADV_SCAN_s //! Bluetooth 5 Radio Setup Command for all PHYs with PA Switching Fields struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_PA_s { - uint16_t commandNo; //!< The command ID number - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t mainMode: 2; //!< \brief PHY to use for non-BLE commands:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding: 1; //!< \brief Coding to use for TX if coded PHY is selected for non-BLE commands
- //!< 0: S = 8 (125 kbps)
- //!< 1: S = 2 (500 kbps) - } defaultPhy; - uint8_t loDivider; //!< LO divider setting to use. Supported values: 0 or 2. - struct - { - uint16_t frontEndMode: 3; //!< \brief 0x00: Differential mode
- //!< 0x01: Single-ended mode RFP
- //!< 0x02: Single-ended mode RFN
- //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
- //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
- //!< Others: Reserved - uint16_t biasMode: 1; //!< \brief 0: Internal bias
- //!< 1: External bias - uint16_t analogCfgMode: 6; //!< \brief 0x00: Write analog configuration.
- //!< Required first time after boot and when changing frequency band - //!< or front-end configuration
- //!< 0x2D: Keep analog configuration.
- //!< May be used after standby or when changing mode with the same frequency - //!< band and front-end configuration
- //!< Others: Reserved - uint16_t bNoFsPowerUp: 1; //!< \brief 0: Power up frequency synth
- //!< 1: Do not power up frequency synth - } config; //!< Configuration options - uint16_t txPower; //!< Default transmit power - uint32_t* pRegOverrideCommon; //!< \brief Pointer to a list of hardware and configuration registers to override during common - //!< initialization. If NULL, no override is used. - uint32_t* pRegOverride1Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting - //!< 1 Mbps PHY mode. If NULL, no override is used. - uint32_t* pRegOverride2Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting - //!< 2 Mbps PHY mode. If NULL, no override is used. - uint32_t* pRegOverrideCoded; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting - //!< coded PHY mode. If NULL, no override is used. - uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to - //!< standard PA. Used by RF driver only, not radio CPU. - uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to - //!< 20-dBm PA. Used by RF driver only, not radio CPU. + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t mainMode : 2; //!< \brief PHY to use for non-BLE commands:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< 3: Reserved + uint8_t coding : 1; //!< \brief Coding to use for TX if coded PHY is selected for non-BLE commands
+ //!< 0: S = 8 (125 kbps)
+ //!< 1: S = 2 (500 kbps) + } defaultPhy; + uint8_t loDivider; //!< LO divider setting to use. Supported values: 0 or 2. + struct + { + uint16_t frontEndMode : 3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode : 1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode : 6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp : 1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Default transmit power + uint32_t* pRegOverrideCommon; //!< \brief Pointer to a list of hardware and configuration registers to override during common + //!< initialization. If NULL, no override is used. + uint32_t* pRegOverride1Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting + //!< 1 Mbps PHY mode. If NULL, no override is used. + uint32_t* pRegOverride2Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting + //!< 2 Mbps PHY mode. If NULL, no override is used. + uint32_t* pRegOverrideCoded; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting + //!< coded PHY mode. If NULL, no override is used. + uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< standard PA. Used by RF driver only, not radio CPU. + uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< 20-dBm PA. Used by RF driver only, not radio CPU. } __RFC_STRUCT_ATTR; //! @} @@ -1705,36 +1705,36 @@ struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_PA_s //! @{ struct __RFC_STRUCT rfc_bleMasterSlavePar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - dataQueue_t* pTxQ; //!< Pointer to transmit queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t lastRxSn: 1; //!< The SN bit of the header of the last packet received with CRC OK - uint8_t lastTxSn: 1; //!< The SN bit of the header of the last transmitted packet - uint8_t nextTxSn: 1; //!< The SN bit of the header of the next packet to transmit - uint8_t bFirstPkt: 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise - uint8_t bAutoEmpty: 1; //!< 1 if the last transmitted packet was an auto-empty packet - uint8_t bLlCtrlTx: 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) - uint8_t bLlCtrlAckRx: 1; //!< 1 if the last received packet was the ACK of an LL control packet - uint8_t bLlCtrlAckPending: 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed - } seqStat; //!< Sequence number status - uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit - uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit - uint32_t accessAddress; //!< Access address used on the connection - uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte - uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte - uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t lastRxSn : 1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn : 1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn : 1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt : 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty : 1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx : 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx : 1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending : 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; //!< Sequence number status + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte } __RFC_STRUCT_ATTR; //! @} @@ -1745,60 +1745,60 @@ struct __RFC_STRUCT rfc_bleMasterSlavePar_s struct __RFC_STRUCT rfc_bleSlavePar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - dataQueue_t* pTxQ; //!< Pointer to transmit queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t lastRxSn: 1; //!< The SN bit of the header of the last packet received with CRC OK - uint8_t lastTxSn: 1; //!< The SN bit of the header of the last transmitted packet - uint8_t nextTxSn: 1; //!< The SN bit of the header of the next packet to transmit - uint8_t bFirstPkt: 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise - uint8_t bAutoEmpty: 1; //!< 1 if the last transmitted packet was an auto-empty packet - uint8_t bLlCtrlTx: 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) - uint8_t bLlCtrlAckRx: 1; //!< 1 if the last received packet was the ACK of an LL control packet - uint8_t bLlCtrlAckPending: 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed - } seqStat; //!< Sequence number status - uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit - uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit - uint32_t accessAddress; //!< Access address used on the connection - uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte - uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte - uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } timeoutTrigger; //!< Trigger that defines timeout of the first receive operation - ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that defines timeout of the first - //!< receive operation - uint16_t __dummy0; - uint8_t __dummy1; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< connection event as soon as allowed + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t lastRxSn : 1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn : 1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn : 1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt : 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty : 1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx : 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx : 1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending : 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; //!< Sequence number status + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that defines timeout of the first receive operation + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that defines timeout of the first + //!< receive operation + uint16_t __dummy0; + uint8_t __dummy1; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< connection event as soon as allowed } __RFC_STRUCT_ATTR; //! @} @@ -1809,47 +1809,47 @@ struct __RFC_STRUCT rfc_bleSlavePar_s struct __RFC_STRUCT rfc_bleMasterPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - dataQueue_t* pTxQ; //!< Pointer to transmit queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t lastRxSn: 1; //!< The SN bit of the header of the last packet received with CRC OK - uint8_t lastTxSn: 1; //!< The SN bit of the header of the last transmitted packet - uint8_t nextTxSn: 1; //!< The SN bit of the header of the next packet to transmit - uint8_t bFirstPkt: 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise - uint8_t bAutoEmpty: 1; //!< 1 if the last transmitted packet was an auto-empty packet - uint8_t bLlCtrlTx: 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) - uint8_t bLlCtrlAckRx: 1; //!< 1 if the last received packet was the ACK of an LL control packet - uint8_t bLlCtrlAckPending: 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed - } seqStat; //!< Sequence number status - uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit - uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit - uint32_t accessAddress; //!< Access address used on the connection - uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte - uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte - uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< connection event as soon as allowed + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t lastRxSn : 1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn : 1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn : 1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt : 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty : 1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx : 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx : 1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending : 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; //!< Sequence number status + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< connection event as soon as allowed } __RFC_STRUCT_ATTR; //! @} @@ -1860,68 +1860,68 @@ struct __RFC_STRUCT rfc_bleMasterPar_s struct __RFC_STRUCT rfc_bleAdvPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t advFilterPolicy: 2; //!< \brief Advertiser filter policy
- //!< 0: Process scan and connect requests from all devices
- //!< 1: Process connect requests from all devices and only scan requests from - //!< devices that are in the white list
- //!< 2: Process scan requests from all devices and only connect requests from - //!< devices that are in the white list
- //!< 3: Process scan and connect requests only from devices in the white list - uint8_t deviceAddrType: 1; //!< The type of the device address -- public (0) or random (1) - uint8_t peerAddrType: 1; //!< Directed advertiser: The type of the peer address -- public (0) or random (1) - uint8_t bStrictLenFilter: 1; //!< \brief 0: Accept any packet with a valid advertising packet length
- //!< 1: Discard messages with illegal length for the given packet type - uint8_t chSel: 1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2
- //!< 1: Report support of Channel Selection Algorithm #2 - uint8_t privIgnMode: 1; //!< \brief 0: Filter on bPrivIgn only when white list is used - //!< 1: Filter on bPrivIgn always - uint8_t rpaMode: 1; //!< \brief Resolvable private address mode
- //!< 0: Normal operation
- //!< 1: Use white list for a received RPA regardless of filter policy - } advConfig; - uint8_t advLen; //!< Size of advertiser data - uint8_t scanRspLen; //!< Size of scan response data - uint8_t* pAdvData; //!< Pointer to buffer containing ADV*_IND data - uint8_t* pScanRspData; //!< Pointer to buffer containing SCAN_RSP data - uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. - //!< If least significant bit is 1, the address type given by - //!< advConfig.deviceAddrType is inverted. - rfc_bleWhiteListEntry_t* pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address (directed - //!< advertiser). If least significant bit is 1, the address type given by - //!< advConfig.peerAddrType is inverted. - struct - { - uint8_t scanRspEndType: 1; //!< \brief Command status at end if SCAN_RSP was sent:
- //!< 0: End with BLE_DONE_OK and result True
- //!< 1: End with BLE_DONE_SCAN_RSP and result False - } behConfig; - uint8_t __dummy0; - uint8_t __dummy1; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the advertiser event as soon as allowed - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< advertiser event as soon as allowed + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t advFilterPolicy : 2; //!< \brief Advertiser filter policy
+ //!< 0: Process scan and connect requests from all devices
+ //!< 1: Process connect requests from all devices and only scan requests from + //!< devices that are in the white list
+ //!< 2: Process scan requests from all devices and only connect requests from + //!< devices that are in the white list
+ //!< 3: Process scan and connect requests only from devices in the white list + uint8_t deviceAddrType : 1; //!< The type of the device address -- public (0) or random (1) + uint8_t peerAddrType : 1; //!< Directed advertiser: The type of the peer address -- public (0) or random (1) + uint8_t bStrictLenFilter : 1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t chSel : 1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2
+ //!< 1: Report support of Channel Selection Algorithm #2 + uint8_t privIgnMode : 1; //!< \brief 0: Filter on bPrivIgn only when white list is used + //!< 1: Filter on bPrivIgn always + uint8_t rpaMode : 1; //!< \brief Resolvable private address mode
+ //!< 0: Normal operation
+ //!< 1: Use white list for a received RPA regardless of filter policy + } advConfig; + uint8_t advLen; //!< Size of advertiser data + uint8_t scanRspLen; //!< Size of scan response data + uint8_t* pAdvData; //!< Pointer to buffer containing ADV*_IND data + uint8_t* pScanRspData; //!< Pointer to buffer containing SCAN_RSP data + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< advConfig.deviceAddrType is inverted. + rfc_bleWhiteListEntry_t* pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address (directed + //!< advertiser). If least significant bit is 1, the address type given by + //!< advConfig.peerAddrType is inverted. + struct + { + uint8_t scanRspEndType : 1; //!< \brief Command status at end if SCAN_RSP was sent:
+ //!< 0: End with BLE_DONE_OK and result True
+ //!< 1: End with BLE_DONE_SCAN_RSP and result False + } behConfig; + uint8_t __dummy0; + uint8_t __dummy1; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the advertiser event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< advertiser event as soon as allowed } __RFC_STRUCT_ATTR; //! @} @@ -1932,79 +1932,79 @@ struct __RFC_STRUCT rfc_bleAdvPar_s struct __RFC_STRUCT rfc_bleScannerPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t scanFilterPolicy: 1; //!< \brief Scanning filter policy regarding advertiser address
- //!< 0: Accept all advertisement packets
- //!< 1: Accept only advertisement packets from devices where the advertiser's address - //!< is in the white list - uint8_t bActiveScan: 1; //!< \brief 0: Passive scan
- //!< 1: Active scan - uint8_t deviceAddrType: 1; //!< The type of the device address -- public (0) or random (1) - uint8_t rpaFilterPolicy: 1; //!< \brief Filter policy for initA for ADV_DIRECT_IND messages
- //!< 0: Accept only initA that matches own address
- //!< 1: Also accept all resolvable private addresses - uint8_t bStrictLenFilter: 1; //!< \brief 0: Accept any packet with a valid advertising packet length
- //!< 1: Discard messages with illegal length for the given packet type - uint8_t bAutoWlIgnore: 1; //!< \brief 0: Do not set ignore bit in white list from radio CPU
- //!< 1: Automatically set ignore bit in white list - uint8_t bEndOnRpt: 1; //!< \brief 0: Continue scanner operation after each reporting ADV*_IND or sending SCAN_RSP
- //!< 1: End scanner operation after each reported ADV*_IND and potentially SCAN_RSP - uint8_t rpaMode: 1; //!< \brief Resolvable private address mode
- //!< 0: Normal operation
- //!< 1: Use white list for a received RPA regardless of filter policy - } scanConfig; - uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure - uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth spec - struct - { - uint8_t logUpperLimit: 4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure - uint8_t bLastSucceeded: 1; //!< \brief 1 if the last SCAN_RSP was successfully received and upperLimit - //!< not changed - uint8_t bLastFailed: 1; //!< \brief 1 if reception of the last SCAN_RSP failed and upperLimit was not - //!< changed - } backoffPar; - uint8_t scanReqLen; //!< Size of scan request data - uint8_t* pScanReqData; //!< Pointer to buffer containing SCAN_REQ data - uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. - //!< If least significant bit is 1, the address type given by - //!< scanConfig.deviceAddrType is inverted. - rfc_bleWhiteListEntry_t* pWhiteList; //!< Pointer to white list - uint16_t __dummy0; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_ENDED + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t scanFilterPolicy : 1; //!< \brief Scanning filter policy regarding advertiser address
+ //!< 0: Accept all advertisement packets
+ //!< 1: Accept only advertisement packets from devices where the advertiser's address + //!< is in the white list + uint8_t bActiveScan : 1; //!< \brief 0: Passive scan
+ //!< 1: Active scan + uint8_t deviceAddrType : 1; //!< The type of the device address -- public (0) or random (1) + uint8_t rpaFilterPolicy : 1; //!< \brief Filter policy for initA for ADV_DIRECT_IND messages
+ //!< 0: Accept only initA that matches own address
+ //!< 1: Also accept all resolvable private addresses + uint8_t bStrictLenFilter : 1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t bAutoWlIgnore : 1; //!< \brief 0: Do not set ignore bit in white list from radio CPU
+ //!< 1: Automatically set ignore bit in white list + uint8_t bEndOnRpt : 1; //!< \brief 0: Continue scanner operation after each reporting ADV*_IND or sending SCAN_RSP
+ //!< 1: End scanner operation after each reported ADV*_IND and potentially SCAN_RSP + uint8_t rpaMode : 1; //!< \brief Resolvable private address mode
+ //!< 0: Normal operation
+ //!< 1: Use white list for a received RPA regardless of filter policy + } scanConfig; + uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure + uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth spec + struct + { + uint8_t logUpperLimit : 4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure + uint8_t bLastSucceeded : 1; //!< \brief 1 if the last SCAN_RSP was successfully received and upperLimit + //!< not changed + uint8_t bLastFailed : 1; //!< \brief 1 if reception of the last SCAN_RSP failed and upperLimit was not + //!< changed + } backoffPar; + uint8_t scanReqLen; //!< Size of scan request data + uint8_t* pScanReqData; //!< Pointer to buffer containing SCAN_REQ data + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< scanConfig.deviceAddrType is inverted. + rfc_bleWhiteListEntry_t* pWhiteList; //!< Pointer to white list + uint16_t __dummy0; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_ENDED } __RFC_STRUCT_ATTR; //! @} @@ -2015,67 +2015,67 @@ struct __RFC_STRUCT rfc_bleScannerPar_s struct __RFC_STRUCT rfc_bleInitiatorPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t bUseWhiteList: 1; //!< \brief Initiator filter policy
- //!< 0: Use specific peer address
- //!< 1: Use white list - uint8_t bDynamicWinOffset: 1; //!< \brief 0: No dynamic WinOffset insertion
- //!< 1: Use dynamic WinOffset insertion - uint8_t deviceAddrType: 1; //!< The type of the device address -- public (0) or random (1) - uint8_t peerAddrType: 1; //!< The type of the peer address -- public (0) or random (1) - uint8_t bStrictLenFilter: 1; //!< \brief 0: Accept any packet with a valid advertising packet length
- //!< 1: Discard messages with illegal length for the given packet type - uint8_t chSel: 1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2
- //!< 1: Report support of Channel Selection Algorithm #2 - } initConfig; - uint8_t __dummy0; - uint8_t connectReqLen; //!< Size of connect request data - uint8_t* pConnectReqData; //!< Pointer to buffer containing LLData to go in the CONNECT_IND (CONNECT_REQ) - uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. - //!< If least significant bit is 1, the address type given by - //!< initConfig.deviceAddrType is inverted. - rfc_bleWhiteListEntry_t* pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address. If least - //!< significant bit is 1, the address type given by initConfig.peerAddrType - //!< is inverted. - ratmr_t connectTime; //!< \brief Indication of timer value of the first possible start time of the first connection event. - //!< Set to the calculated value if a connection is made and to the next possible connection - //!< time if not. - uint16_t __dummy1; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_ENDED + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t bUseWhiteList : 1; //!< \brief Initiator filter policy
+ //!< 0: Use specific peer address
+ //!< 1: Use white list + uint8_t bDynamicWinOffset : 1; //!< \brief 0: No dynamic WinOffset insertion
+ //!< 1: Use dynamic WinOffset insertion + uint8_t deviceAddrType : 1; //!< The type of the device address -- public (0) or random (1) + uint8_t peerAddrType : 1; //!< The type of the peer address -- public (0) or random (1) + uint8_t bStrictLenFilter : 1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t chSel : 1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2
+ //!< 1: Report support of Channel Selection Algorithm #2 + } initConfig; + uint8_t __dummy0; + uint8_t connectReqLen; //!< Size of connect request data + uint8_t* pConnectReqData; //!< Pointer to buffer containing LLData to go in the CONNECT_IND (CONNECT_REQ) + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< initConfig.deviceAddrType is inverted. + rfc_bleWhiteListEntry_t* pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address. If least + //!< significant bit is 1, the address type given by initConfig.peerAddrType + //!< is inverted. + ratmr_t connectTime; //!< \brief Indication of timer value of the first possible start time of the first connection event. + //!< Set to the calculated value if a connection is made and to the next possible connection + //!< time if not. + uint16_t __dummy1; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_ENDED } __RFC_STRUCT_ATTR; //! @} @@ -2086,36 +2086,36 @@ struct __RFC_STRUCT rfc_bleInitiatorPar_s struct __RFC_STRUCT rfc_bleGenericRxPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue. May be NULL; if so, received packets are not stored - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - uint8_t bRepeat; //!< \brief 0: End operation after receiving a packet
- //!< 1: Restart receiver after receiving a packet - uint16_t __dummy0; - uint32_t accessAddress; //!< Access address used on the connection - uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte - uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte - uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the Rx operation - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< Rx operation + dataQueue_t* pRxQ; //!< Pointer to receive queue. May be NULL; if so, received packets are not stored + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + uint8_t bRepeat; //!< \brief 0: End operation after receiving a packet
+ //!< 1: Restart receiver after receiving a packet + uint16_t __dummy0; + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Rx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< Rx operation } __RFC_STRUCT_ATTR; //! @} @@ -2126,36 +2126,36 @@ struct __RFC_STRUCT rfc_bleGenericRxPar_s struct __RFC_STRUCT rfc_bleTxTestPar_s { - uint16_t numPackets; //!< \brief Number of packets to transmit
- //!< 0: Transmit unlimited number of packets - uint8_t payloadLength; //!< The number of payload bytes in each packet. - uint8_t packetType; //!< \brief The packet type to be used, encoded according to the Bluetooth 5.0 spec, Volume 6, Part F, - //!< Section 4.1.4 - ratmr_t period; //!< Number of radio timer cycles between the start of each packet - struct - { - uint8_t bOverrideDefault: 1; //!< \brief 0: Use default packet encoding
- //!< 1: Override packet contents - uint8_t bUsePrbs9: 1; //!< \brief If bOverride is 1:
- //!< 0: No PRBS9 encoding of packet
- //!< 1: Use PRBS9 encoding of packet - uint8_t bUsePrbs15: 1; //!< \brief If bOverride is 1:
- //!< 0: No PRBS15 encoding of packet
- //!< 1: Use PRBS15 encoding of packet - } config; - uint8_t byteVal; //!< If config.bOverride is 1, value of each byte to be sent - uint8_t __dummy0; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the Test Tx operation - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< Test Tx operation + uint16_t numPackets; //!< \brief Number of packets to transmit
+ //!< 0: Transmit unlimited number of packets + uint8_t payloadLength; //!< The number of payload bytes in each packet. + uint8_t packetType; //!< \brief The packet type to be used, encoded according to the Bluetooth 5.0 spec, Volume 6, Part F, + //!< Section 4.1.4 + ratmr_t period; //!< Number of radio timer cycles between the start of each packet + struct + { + uint8_t bOverrideDefault : 1; //!< \brief 0: Use default packet encoding
+ //!< 1: Override packet contents + uint8_t bUsePrbs9 : 1; //!< \brief If bOverride is 1:
+ //!< 0: No PRBS9 encoding of packet
+ //!< 1: Use PRBS9 encoding of packet + uint8_t bUsePrbs15 : 1; //!< \brief If bOverride is 1:
+ //!< 0: No PRBS15 encoding of packet
+ //!< 1: Use PRBS15 encoding of packet + } config; + uint8_t byteVal; //!< If config.bOverride is 1, value of each byte to be sent + uint8_t __dummy0; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Test Tx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< Test Tx operation } __RFC_STRUCT_ATTR; //! @} @@ -2166,61 +2166,61 @@ struct __RFC_STRUCT rfc_bleTxTestPar_s struct __RFC_STRUCT rfc_ble5SlavePar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - dataQueue_t* pTxQ; //!< Pointer to transmit queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t lastRxSn: 1; //!< The SN bit of the header of the last packet received with CRC OK - uint8_t lastTxSn: 1; //!< The SN bit of the header of the last transmitted packet - uint8_t nextTxSn: 1; //!< The SN bit of the header of the next packet to transmit - uint8_t bFirstPkt: 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise - uint8_t bAutoEmpty: 1; //!< 1 if the last transmitted packet was an auto-empty packet - uint8_t bLlCtrlTx: 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) - uint8_t bLlCtrlAckRx: 1; //!< 1 if the last received packet was the ACK of an LL control packet - uint8_t bLlCtrlAckPending: 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed - } seqStat; //!< Sequence number status - uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit - uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit - uint32_t accessAddress; //!< Access address used on the connection - uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte - uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte - uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } timeoutTrigger; //!< Trigger that defines timeout of the first receive operation - ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that defines timeout of the first - //!< receive operation - uint8_t maxRxPktLen; //!< Maximum packet length currently allowed for received packets on the connection - uint8_t maxLenLowRate; //!< Maximum packet length for which using S = 8 (125 kbps) is allowed when transmitting. 0: no limit. - uint8_t __dummy0; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< connection event as soon as allowed + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t lastRxSn : 1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn : 1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn : 1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt : 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty : 1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx : 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx : 1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending : 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; //!< Sequence number status + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that defines timeout of the first receive operation + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that defines timeout of the first + //!< receive operation + uint8_t maxRxPktLen; //!< Maximum packet length currently allowed for received packets on the connection + uint8_t maxLenLowRate; //!< Maximum packet length for which using S = 8 (125 kbps) is allowed when transmitting. 0: no limit. + uint8_t __dummy0; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< connection event as soon as allowed } __RFC_STRUCT_ATTR; //! @} @@ -2231,49 +2231,49 @@ struct __RFC_STRUCT rfc_ble5SlavePar_s struct __RFC_STRUCT rfc_ble5MasterPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - dataQueue_t* pTxQ; //!< Pointer to transmit queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t lastRxSn: 1; //!< The SN bit of the header of the last packet received with CRC OK - uint8_t lastTxSn: 1; //!< The SN bit of the header of the last transmitted packet - uint8_t nextTxSn: 1; //!< The SN bit of the header of the next packet to transmit - uint8_t bFirstPkt: 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise - uint8_t bAutoEmpty: 1; //!< 1 if the last transmitted packet was an auto-empty packet - uint8_t bLlCtrlTx: 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) - uint8_t bLlCtrlAckRx: 1; //!< 1 if the last received packet was the ACK of an LL control packet - uint8_t bLlCtrlAckPending: 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed - } seqStat; //!< Sequence number status - uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit - uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit - uint32_t accessAddress; //!< Access address used on the connection - uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte - uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte - uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< connection event as soon as allowed - uint8_t maxRxPktLen; //!< Maximum packet length currently allowed for received packets on the connection - uint8_t maxLenLowRate; //!< Maximum packet length for which using S = 8 (125 kbps) is allowed when transmitting. 0: no limit. + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t lastRxSn : 1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn : 1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn : 1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt : 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty : 1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx : 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx : 1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending : 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; //!< Sequence number status + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< connection event as soon as allowed + uint8_t maxRxPktLen; //!< Maximum packet length currently allowed for received packets on the connection + uint8_t maxLenLowRate; //!< Maximum packet length for which using S = 8 (125 kbps) is allowed when transmitting. 0: no limit. } __RFC_STRUCT_ATTR; //! @} @@ -2284,20 +2284,20 @@ struct __RFC_STRUCT rfc_ble5MasterPar_s struct __RFC_STRUCT rfc_ble5AdvExtPar_s { - struct - { - uint8_t : 2; - uint8_t deviceAddrType: 1; //!< The type of the device address -- public (0) or random (1) - } advConfig; - uint8_t __dummy0; - uint8_t __dummy1; - uint8_t auxPtrTargetType; //!< \brief Number indicating reference for auxPtrTargetTime. Takes same values as trigger types, - //!< but only TRIG_ABSTIME and TRIG_REL_* are allowed - ratmr_t auxPtrTargetTime; //!< Time of start of packet to which auxPtr points - uint8_t* pAdvPkt; //!< Pointer to extended advertising packet for the ADV_EXT_IND packet - uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. - //!< If least significant bit is 1, the address type given by - //!< advConfig.deviceAddrType is inverted. + struct + { + uint8_t : 2; + uint8_t deviceAddrType : 1; //!< The type of the device address -- public (0) or random (1) + } advConfig; + uint8_t __dummy0; + uint8_t __dummy1; + uint8_t auxPtrTargetType; //!< \brief Number indicating reference for auxPtrTargetTime. Takes same values as trigger types, + //!< but only TRIG_ABSTIME and TRIG_REL_* are allowed + ratmr_t auxPtrTargetTime; //!< Time of start of packet to which auxPtr points + uint8_t* pAdvPkt; //!< Pointer to extended advertising packet for the ADV_EXT_IND packet + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< advConfig.deviceAddrType is inverted. } __RFC_STRUCT_ATTR; //! @} @@ -2308,57 +2308,57 @@ struct __RFC_STRUCT rfc_ble5AdvExtPar_s struct __RFC_STRUCT rfc_ble5AdvAuxPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t advFilterPolicy: 2; //!< \brief Advertiser filter policy
- //!< 0: Process scan and connect requests from all devices
- //!< 1: Process connect requests from all devices and only scan requests from - //!< devices that are in the white list
- //!< 2: Process scan requests from all devices and only connect requests from - //!< devices that are in the white list
- //!< 3: Process scan and connect requests only from devices in the white list - uint8_t deviceAddrType: 1; //!< The type of the device address -- public (0) or random (1) - uint8_t targetAddrType: 1; //!< Directed secondary advertiser: The type of the target address -- public (0) or random (1) - uint8_t bStrictLenFilter: 1; //!< \brief 0: Accept any packet with a valid advertising packet length
- //!< 1: Discard messages with illegal length for the given packet type - uint8_t bDirected: 1; //!< \brief 0: Advertiser is undirected: pWhiteList points to a white list - //!< 1: Advertiser is directed: pWhiteList points to a single device address - uint8_t privIgnMode: 1; //!< \brief 0: Filter on bPrivIgn only when white list is used - //!< 1: Filter on bPrivIgn always - uint8_t rpaMode: 1; //!< \brief Resolvable private address mode
- //!< 0: Normal operation
- //!< 1: Use white list for a received RPA regardless of filter policy - } advConfig; - struct - { - uint8_t scanRspEndType: 1; //!< \brief Command status at end if AUX_SCAN_RSP was sent:
- //!< 0: End with BLE_DONE_OK and result True
- //!< 1: End with BLE_DONE_SCAN_RSP and result False - } behConfig; - uint8_t auxPtrTargetType; //!< \brief Number indicating reference for auxPtrTargetTime. Takes same values as trigger types, - //!< but only TRIG_ABSTIME and TRIG_REL_* are allowed - ratmr_t auxPtrTargetTime; //!< Time of start of packet to which auxPtr points - uint8_t* pAdvPkt; //!< Pointer to extended advertising packet for the ADV_AUX_IND packet - uint8_t* pRspPkt; //!< \brief Pointer to extended advertising packet for the AUX_SCAN_RSP or AUX_CONNECT_RSP packet - //!< (may be NULL if not applicable) - uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. - //!< If least significant bit is 1, the address type given by - //!< advConfig.deviceAddrType is inverted. - rfc_bleWhiteListEntry_t* pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address (directed - //!< advertiser). If least significant bit is 1, the address type given by - //!< advConfig.peerAddrType is inverted. + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t advFilterPolicy : 2; //!< \brief Advertiser filter policy
+ //!< 0: Process scan and connect requests from all devices
+ //!< 1: Process connect requests from all devices and only scan requests from + //!< devices that are in the white list
+ //!< 2: Process scan requests from all devices and only connect requests from + //!< devices that are in the white list
+ //!< 3: Process scan and connect requests only from devices in the white list + uint8_t deviceAddrType : 1; //!< The type of the device address -- public (0) or random (1) + uint8_t targetAddrType : 1; //!< Directed secondary advertiser: The type of the target address -- public (0) or random (1) + uint8_t bStrictLenFilter : 1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t bDirected : 1; //!< \brief 0: Advertiser is undirected: pWhiteList points to a white list + //!< 1: Advertiser is directed: pWhiteList points to a single device address + uint8_t privIgnMode : 1; //!< \brief 0: Filter on bPrivIgn only when white list is used + //!< 1: Filter on bPrivIgn always + uint8_t rpaMode : 1; //!< \brief Resolvable private address mode
+ //!< 0: Normal operation
+ //!< 1: Use white list for a received RPA regardless of filter policy + } advConfig; + struct + { + uint8_t scanRspEndType : 1; //!< \brief Command status at end if AUX_SCAN_RSP was sent:
+ //!< 0: End with BLE_DONE_OK and result True
+ //!< 1: End with BLE_DONE_SCAN_RSP and result False + } behConfig; + uint8_t auxPtrTargetType; //!< \brief Number indicating reference for auxPtrTargetTime. Takes same values as trigger types, + //!< but only TRIG_ABSTIME and TRIG_REL_* are allowed + ratmr_t auxPtrTargetTime; //!< Time of start of packet to which auxPtr points + uint8_t* pAdvPkt; //!< Pointer to extended advertising packet for the ADV_AUX_IND packet + uint8_t* pRspPkt; //!< \brief Pointer to extended advertising packet for the AUX_SCAN_RSP or AUX_CONNECT_RSP packet + //!< (may be NULL if not applicable) + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< advConfig.deviceAddrType is inverted. + rfc_bleWhiteListEntry_t* pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address (directed + //!< advertiser). If least significant bit is 1, the address type given by + //!< advConfig.peerAddrType is inverted. } __RFC_STRUCT_ATTR; //! @} @@ -2367,14 +2367,14 @@ struct __RFC_STRUCT rfc_ble5AdvAuxPar_s //! @{ struct __RFC_STRUCT rfc_ble5AuxChRes_s { - ratmr_t rxStartTime; //!< The time needed to start RX in order to receive the packet - uint16_t rxListenTime; //!< The time needed to listen in order to receive the packet. 0: No AUX packet - uint8_t channelNo; //!< The channel index used for secondary advertising - uint8_t phyMode; //!< \brief PHY to use on secondary channel:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< Others: Reserved + ratmr_t rxStartTime; //!< The time needed to start RX in order to receive the packet + uint16_t rxListenTime; //!< The time needed to listen in order to receive the packet. 0: No AUX packet + uint8_t channelNo; //!< The channel index used for secondary advertising + uint8_t phyMode; //!< \brief PHY to use on secondary channel:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< Others: Reserved } __RFC_STRUCT_ATTR; //! @} @@ -2385,128 +2385,128 @@ struct __RFC_STRUCT rfc_ble5AuxChRes_s struct __RFC_STRUCT rfc_ble5ScannerPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t scanFilterPolicy: 1; //!< \brief Scanning filter policy regarding advertiser address
- //!< 0: Accept all advertisement packets
- //!< 1: Accept only advertisement packets from devices where the advertiser's address - //!< is in the White list. - uint8_t bActiveScan: 1; //!< \brief 0: Passive scan
- //!< 1: Active scan - uint8_t deviceAddrType: 1; //!< The type of the device address -- public (0) or random (1) - uint8_t rpaFilterPolicy: 1; //!< \brief Filter policy for initA of ADV_DIRECT_IND messages
- //!< 0: Accept only initA that matches own address
- //!< 1: Also accept all resolvable private addresses - uint8_t bStrictLenFilter: 1; //!< \brief 0: Accept any packet with a valid advertising packet length
- //!< 1: Discard messages with illegal length for the given packet type - uint8_t bAutoWlIgnore: 1; //!< \brief 0: Do not set ignore bit in white list from radio CPU for legacy packets
- //!< 1: Automatically set ignore bit in white list for legacy packets - uint8_t bEndOnRpt: 1; //!< \brief 0: Continue scanner operation after each reporting ADV*_IND or sending SCAN_RSP
- //!< 1: End scanner operation after each reported ADV*_IND and potentially SCAN_RSP - uint8_t rpaMode: 1; //!< \brief Resolvable private address mode
- //!< 0: Normal operation
- //!< 1: Use white list for a received RPA regardless of filter policy - } scanConfig; - uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure - uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth spec - struct - { - uint8_t logUpperLimit: 4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure - uint8_t bLastSucceeded: 1; //!< \brief 1 if the last SCAN_RSP was successfully received and upperLimit - //!< not changed - uint8_t bLastFailed: 1; //!< \brief 1 if reception of the last SCAN_RSP failed and upperLimit was not - //!< changed - } backoffPar; - struct - { - uint8_t bCheckAdi: 1; //!< \brief 0: Do not perform ADI filtering
- //!< 1: Perform ADI filtering on packets where ADI is present - uint8_t bAutoAdiUpdate: 1; //!< \brief 0: Do not update ADI entries in radio CPU using legacy mode (recommended)
- //!< 1: Legacy mode: Automatically update ADI entry for received packets with - //!< AdvDataInfo after first occurrence - uint8_t bApplyDuplicateFiltering: 1; //!< \brief 0: Do not apply duplicate filtering based on device address for extended - //!< advertiser packets (recommended)
- //!< 1: Apply duplicate filtering based on device address for extended advertiser - //!< packets with no ADI field - uint8_t bAutoWlIgnore: 1; //!< \brief 0: Do not set ignore bit in white list from radio CPU for extended advertising packets
- //!< 1: Automatically set ignore bit in white list for extended advertising packets - uint8_t bAutoAdiProcess: 1; //!< \brief 0: Do not use automatic ADI processing
- //!< 1: Automatically update ADI entry for received packets so that only the same - //!< ADI is accepted for the rest of the chain and the SID/DID combination is - //!< ignored after the entire chain is received. - uint8_t bExclusiveSid: 1; //!< \brief 0: Set adiStatus.state to 0 when command starts so that all - //!< valid SIDs are accepted
- //!< 1: Do not modify adiStatus.state when command starts
- } extFilterConfig; - struct - { - uint8_t lastAcceptedSid: 4; //!< Indication of SID of last successfully received packet that was not ignored - uint8_t state: 3; //!< \brief 0: No extended packet received, or last extended packet didn't have an ADI; - //!< lastAcceptedSid field is not valid
- //!< 1: A message with ADI has been received, but no chain is under reception; - //!< ADI filtering to be performed normally
- //!< 2: A message with SID as given in lastAcceptedSid has been - //!< received, and chained messages are still pending. Messages without this - //!< SID will be ignored
- //!< 3: An AUX_SCAN_RSP message has been received after receiving messages with SID - //!< as given in lastAcceptedSid, and chained messages are - //!< pending. Messages with an ADI field will be ignored.
- //!< 4: A message with no ADI has been received, and chained messages are still - //!< pending. Messages with an ADI field will be ignored.
+ dataQueue_t* pRxQ; //!< Pointer to receive queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t scanFilterPolicy : 1; //!< \brief Scanning filter policy regarding advertiser address
+ //!< 0: Accept all advertisement packets
+ //!< 1: Accept only advertisement packets from devices where the advertiser's address + //!< is in the White list. + uint8_t bActiveScan : 1; //!< \brief 0: Passive scan
+ //!< 1: Active scan + uint8_t deviceAddrType : 1; //!< The type of the device address -- public (0) or random (1) + uint8_t rpaFilterPolicy : 1; //!< \brief Filter policy for initA of ADV_DIRECT_IND messages
+ //!< 0: Accept only initA that matches own address
+ //!< 1: Also accept all resolvable private addresses + uint8_t bStrictLenFilter : 1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t bAutoWlIgnore : 1; //!< \brief 0: Do not set ignore bit in white list from radio CPU for legacy packets
+ //!< 1: Automatically set ignore bit in white list for legacy packets + uint8_t bEndOnRpt : 1; //!< \brief 0: Continue scanner operation after each reporting ADV*_IND or sending SCAN_RSP
+ //!< 1: End scanner operation after each reported ADV*_IND and potentially SCAN_RSP + uint8_t rpaMode : 1; //!< \brief Resolvable private address mode
+ //!< 0: Normal operation
+ //!< 1: Use white list for a received RPA regardless of filter policy + } scanConfig; + uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure + uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth spec + struct + { + uint8_t logUpperLimit : 4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure + uint8_t bLastSucceeded : 1; //!< \brief 1 if the last SCAN_RSP was successfully received and upperLimit + //!< not changed + uint8_t bLastFailed : 1; //!< \brief 1 if reception of the last SCAN_RSP failed and upperLimit was not + //!< changed + } backoffPar; + struct + { + uint8_t bCheckAdi : 1; //!< \brief 0: Do not perform ADI filtering
+ //!< 1: Perform ADI filtering on packets where ADI is present + uint8_t bAutoAdiUpdate : 1; //!< \brief 0: Do not update ADI entries in radio CPU using legacy mode (recommended)
+ //!< 1: Legacy mode: Automatically update ADI entry for received packets with + //!< AdvDataInfo after first occurrence + uint8_t bApplyDuplicateFiltering : 1; //!< \brief 0: Do not apply duplicate filtering based on device address for extended + //!< advertiser packets (recommended)
+ //!< 1: Apply duplicate filtering based on device address for extended advertiser + //!< packets with no ADI field + uint8_t bAutoWlIgnore : 1; //!< \brief 0: Do not set ignore bit in white list from radio CPU for extended advertising packets
+ //!< 1: Automatically set ignore bit in white list for extended advertising packets + uint8_t bAutoAdiProcess : 1; //!< \brief 0: Do not use automatic ADI processing
+ //!< 1: Automatically update ADI entry for received packets so that only the same + //!< ADI is accepted for the rest of the chain and the SID/DID combination is + //!< ignored after the entire chain is received. + uint8_t bExclusiveSid : 1; //!< \brief 0: Set adiStatus.state to 0 when command starts so that all + //!< valid SIDs are accepted
+ //!< 1: Do not modify adiStatus.state when command starts
+ } extFilterConfig; + struct + { + uint8_t lastAcceptedSid : 4; //!< Indication of SID of last successfully received packet that was not ignored + uint8_t state : 3; //!< \brief 0: No extended packet received, or last extended packet didn't have an ADI; + //!< lastAcceptedSid field is not valid
+ //!< 1: A message with ADI has been received, but no chain is under reception; + //!< ADI filtering to be performed normally
+ //!< 2: A message with SID as given in lastAcceptedSid has been + //!< received, and chained messages are still pending. Messages without this + //!< SID will be ignored
+ //!< 3: An AUX_SCAN_RSP message has been received after receiving messages with SID + //!< as given in lastAcceptedSid, and chained messages are + //!< pending. Messages with an ADI field will be ignored.
+ //!< 4: A message with no ADI has been received, and chained messages are still + //!< pending. Messages with an ADI field will be ignored.
+ //!< Others: Reserved + } adiStatus; + uint8_t __dummy0; + uint16_t __dummy1; + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< scanConfig.deviceAddrType is inverted. + rfc_bleWhiteListEntry_t* pWhiteList; //!< Pointer to white list + rfc_ble5AdiEntry_t* pAdiList; //!< Pointer to advDataInfo list + uint16_t maxWaitTimeForAuxCh; //!< \brief Maximum wait time for switching to secondary scanning withing the command. If the time + //!< to the start of the event is greater than this, the command will end with BLE_DONE_AUX. + //!< If it is smaller, the radio will automatically switch to the correct channel and PHY. + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_ENDED + ratmr_t rxStartTime; //!< The time needed to start RX in order to receive the packet + uint16_t rxListenTime; //!< The time needed to listen in order to receive the packet. 0: No AUX packet + uint8_t channelNo; //!< The channel index used for secondary advertising + uint8_t phyMode; //!< \brief PHY to use on secondary channel:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
//!< Others: Reserved - } adiStatus; - uint8_t __dummy0; - uint16_t __dummy1; - uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. - //!< If least significant bit is 1, the address type given by - //!< scanConfig.deviceAddrType is inverted. - rfc_bleWhiteListEntry_t* pWhiteList; //!< Pointer to white list - rfc_ble5AdiEntry_t* pAdiList; //!< Pointer to advDataInfo list - uint16_t maxWaitTimeForAuxCh; //!< \brief Maximum wait time for switching to secondary scanning withing the command. If the time - //!< to the start of the event is greater than this, the command will end with BLE_DONE_AUX. - //!< If it is smaller, the radio will automatically switch to the correct channel and PHY. - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_ENDED - ratmr_t rxStartTime; //!< The time needed to start RX in order to receive the packet - uint16_t rxListenTime; //!< The time needed to listen in order to receive the packet. 0: No AUX packet - uint8_t channelNo; //!< The channel index used for secondary advertising - uint8_t phyMode; //!< \brief PHY to use on secondary channel:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< Others: Reserved } __RFC_STRUCT_ATTR; //! @} @@ -2517,85 +2517,85 @@ struct __RFC_STRUCT rfc_ble5ScannerPar_s struct __RFC_STRUCT rfc_ble5InitiatorPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t bUseWhiteList: 1; //!< \brief Initiator filter policy
- //!< 0: Use specific peer address
- //!< 1: Use white list - uint8_t bDynamicWinOffset: 1; //!< 1: Use dynamic WinOffset insertion - uint8_t deviceAddrType: 1; //!< The type of the device address -- public (0) or random (1) - uint8_t peerAddrType: 1; //!< The type of the peer address -- public (0) or random (1) - uint8_t bStrictLenFilter: 1; //!< \brief 0: Accept any packet with a valid advertising packet length
- //!< 1: Discard messages with illegal length for the given packet type - uint8_t chSel: 1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2 in CONNECT_IND
- //!< 1: Report support of Channel Selection Algorithm #2 in CONNECT_IND - } initConfig; - uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure - uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth spec - struct - { - uint8_t logUpperLimit: 4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure - uint8_t bLastSucceeded: 1; //!< \brief 1 if the last SCAN_RSP was successfully received and upperLimit - //!< not changed - uint8_t bLastFailed: 1; //!< \brief 1 if reception of the last SCAN_RSP failed and upperLimit was not - //!< changed - } backoffPar; - uint8_t connectReqLen; //!< Size of connect request data - uint8_t* pConnectReqData; //!< Pointer to buffer containing LLData to go in the CONNECT_IND or AUX_CONNECT_REQ packet - uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. - //!< If least significant bit is 1, the address type given by - //!< initConfig.deviceAddrType is inverted. - rfc_bleWhiteListEntry_t* pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address. If least - //!< significant bit is 1, the address type given by initConfig.peerAddrType - //!< is inverted. - ratmr_t connectTime; //!< \brief Indication of timer value of the first possible start time of the first connection event. - //!< Set to the calculated value if a connection is made and to the next possible connection - //!< time if not. - uint16_t maxWaitTimeForAuxCh; //!< \brief Maximum wait time for switching to secondary scanning withing the command. If the time - //!< to the start of the event is greater than this, the command will end with BLE_DONE_AUX. - //!< If it is smaller, the radio will automatically switch to the correct channel and PHY. - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_ENDED - ratmr_t rxStartTime; //!< The time needed to start RX in order to receive the packet - uint16_t rxListenTime; //!< The time needed to listen in order to receive the packet. 0: No AUX packet - uint8_t channelNo; //!< The channel index used for secondary advertising - uint8_t phyMode; //!< \brief PHY to use on secondary channel:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< Others: Reserved + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t bUseWhiteList : 1; //!< \brief Initiator filter policy
+ //!< 0: Use specific peer address
+ //!< 1: Use white list + uint8_t bDynamicWinOffset : 1; //!< 1: Use dynamic WinOffset insertion + uint8_t deviceAddrType : 1; //!< The type of the device address -- public (0) or random (1) + uint8_t peerAddrType : 1; //!< The type of the peer address -- public (0) or random (1) + uint8_t bStrictLenFilter : 1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t chSel : 1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2 in CONNECT_IND
+ //!< 1: Report support of Channel Selection Algorithm #2 in CONNECT_IND + } initConfig; + uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure + uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth spec + struct + { + uint8_t logUpperLimit : 4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure + uint8_t bLastSucceeded : 1; //!< \brief 1 if the last SCAN_RSP was successfully received and upperLimit + //!< not changed + uint8_t bLastFailed : 1; //!< \brief 1 if reception of the last SCAN_RSP failed and upperLimit was not + //!< changed + } backoffPar; + uint8_t connectReqLen; //!< Size of connect request data + uint8_t* pConnectReqData; //!< Pointer to buffer containing LLData to go in the CONNECT_IND or AUX_CONNECT_REQ packet + uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. + //!< If least significant bit is 1, the address type given by + //!< initConfig.deviceAddrType is inverted. + rfc_bleWhiteListEntry_t* pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address. If least + //!< significant bit is 1, the address type given by initConfig.peerAddrType + //!< is inverted. + ratmr_t connectTime; //!< \brief Indication of timer value of the first possible start time of the first connection event. + //!< Set to the calculated value if a connection is made and to the next possible connection + //!< time if not. + uint16_t maxWaitTimeForAuxCh; //!< \brief Maximum wait time for switching to secondary scanning withing the command. If the time + //!< to the start of the event is greater than this, the command will end with BLE_DONE_AUX. + //!< If it is smaller, the radio will automatically switch to the correct channel and PHY. + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_ENDED + ratmr_t rxStartTime; //!< The time needed to start RX in order to receive the packet + uint16_t rxListenTime; //!< The time needed to listen in order to receive the packet. 0: No AUX packet + uint8_t channelNo; //!< The channel index used for secondary advertising + uint8_t phyMode; //!< \brief PHY to use on secondary channel:
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded
+ //!< Others: Reserved } __RFC_STRUCT_ATTR; //! @} @@ -2606,37 +2606,37 @@ struct __RFC_STRUCT rfc_ble5InitiatorPar_s struct __RFC_STRUCT rfc_bleMasterSlaveOutput_s { - uint8_t nTx; //!< \brief Total number of packets (including auto-empty and retransmissions) that have been - //!< transmitted - uint8_t nTxAck; //!< Total number of transmitted packets (including auto-empty) that have been ACK'ed - uint8_t nTxCtrl; //!< Number of unique LL control packets from the Tx queue that have been transmitted - uint8_t nTxCtrlAck; //!< Number of LL control packets from the Tx queue that have been finished (ACK'ed) - uint8_t nTxCtrlAckAck; //!< \brief Number of LL control packets that have been ACK'ed and where an ACK has been sent in - //!< response - uint8_t nTxRetrans; //!< Number of retransmissions that has been done - uint8_t nTxEntryDone; //!< Number of packets from the Tx queue that have been finished (ACK'ed) - uint8_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored - uint8_t nRxCtrl; //!< Number of LL control packets that have been received with CRC OK and not ignored - uint8_t nRxCtrlAck; //!< \brief Number of LL control packets that have been received with CRC OK and not ignored, and - //!< then ACK'ed - uint8_t nRxNok; //!< Number of packets that have been received with CRC error - uint8_t nRxIgnored; //!< \brief Number of packets that have been received with CRC OK and ignored due to repeated - //!< sequence number - uint8_t nRxEmpty; //!< Number of packets that have been received with CRC OK and no payload - uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space - int8_t lastRssi; //!< RSSI of last received packet (signed) - struct - { - uint8_t bTimeStampValid: 1; //!< 1 if a valid time stamp has been written to timeStamp; 0 otherwise - uint8_t bLastCrcErr: 1; //!< 1 if the last received packet had CRC error; 0 otherwise - uint8_t bLastIgnored: 1; //!< 1 if the last received packet with CRC OK was ignored; 0 otherwise - uint8_t bLastEmpty: 1; //!< 1 if the last received packet with CRC OK was empty; 0 otherwise - uint8_t bLastCtrl: 1; //!< 1 if the last received packet with CRC OK was an LL control packet; 0 otherwise - uint8_t bLastMd: 1; //!< 1 if the last received packet with CRC OK had MD = 1; 0 otherwise - uint8_t bLastAck: 1; //!< \brief 1 if the last received packet with CRC OK was an ACK of a transmitted packet; - //!< 0 otherwise - } pktStatus; //!< Status of received packets - ratmr_t timeStamp; //!< Slave operation: Time stamp of first received packet + uint8_t nTx; //!< \brief Total number of packets (including auto-empty and retransmissions) that have been + //!< transmitted + uint8_t nTxAck; //!< Total number of transmitted packets (including auto-empty) that have been ACK'ed + uint8_t nTxCtrl; //!< Number of unique LL control packets from the Tx queue that have been transmitted + uint8_t nTxCtrlAck; //!< Number of LL control packets from the Tx queue that have been finished (ACK'ed) + uint8_t nTxCtrlAckAck; //!< \brief Number of LL control packets that have been ACK'ed and where an ACK has been sent in + //!< response + uint8_t nTxRetrans; //!< Number of retransmissions that has been done + uint8_t nTxEntryDone; //!< Number of packets from the Tx queue that have been finished (ACK'ed) + uint8_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored + uint8_t nRxCtrl; //!< Number of LL control packets that have been received with CRC OK and not ignored + uint8_t nRxCtrlAck; //!< \brief Number of LL control packets that have been received with CRC OK and not ignored, and + //!< then ACK'ed + uint8_t nRxNok; //!< Number of packets that have been received with CRC error + uint8_t nRxIgnored; //!< \brief Number of packets that have been received with CRC OK and ignored due to repeated + //!< sequence number + uint8_t nRxEmpty; //!< Number of packets that have been received with CRC OK and no payload + uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< RSSI of last received packet (signed) + struct + { + uint8_t bTimeStampValid : 1; //!< 1 if a valid time stamp has been written to timeStamp; 0 otherwise + uint8_t bLastCrcErr : 1; //!< 1 if the last received packet had CRC error; 0 otherwise + uint8_t bLastIgnored : 1; //!< 1 if the last received packet with CRC OK was ignored; 0 otherwise + uint8_t bLastEmpty : 1; //!< 1 if the last received packet with CRC OK was empty; 0 otherwise + uint8_t bLastCtrl : 1; //!< 1 if the last received packet with CRC OK was an LL control packet; 0 otherwise + uint8_t bLastMd : 1; //!< 1 if the last received packet with CRC OK had MD = 1; 0 otherwise + uint8_t bLastAck : 1; //!< \brief 1 if the last received packet with CRC OK was an ACK of a transmitted packet; + //!< 0 otherwise + } pktStatus; //!< Status of received packets + ratmr_t timeStamp; //!< Slave operation: Time stamp of first received packet } __RFC_STRUCT_ATTR; //! @} @@ -2647,16 +2647,16 @@ struct __RFC_STRUCT rfc_bleMasterSlaveOutput_s struct __RFC_STRUCT rfc_bleAdvOutput_s { - uint16_t nTxAdvInd; //!< Number of ADV*_IND packets completely transmitted - uint8_t nTxScanRsp; //!< Number of AUX_SCAN_RSP or SCAN_RSP packets transmitted - uint8_t nRxScanReq; //!< Number of AUX_SCAN_REQ or SCAN_REQ packets received OK and not ignored - uint8_t nRxConnectReq; //!< Number of AUX_CONNECT_REQ or CONNECT_IND (CONNECT_REQ) packets received OK and not ignored - uint8_t nTxConnectRsp; //!< Number of AUX_CONNECT_RSP packets transmitted - uint16_t nRxNok; //!< Number of packets received with CRC error - uint16_t nRxIgnored; //!< Number of packets received with CRC OK, but ignored - uint8_t nRxBufFull; //!< Number of packets received that did not fit in Rx queue - int8_t lastRssi; //!< The RSSI of the last received packet (signed) - ratmr_t timeStamp; //!< Time stamp of the last received packet + uint16_t nTxAdvInd; //!< Number of ADV*_IND packets completely transmitted + uint8_t nTxScanRsp; //!< Number of AUX_SCAN_RSP or SCAN_RSP packets transmitted + uint8_t nRxScanReq; //!< Number of AUX_SCAN_REQ or SCAN_REQ packets received OK and not ignored + uint8_t nRxConnectReq; //!< Number of AUX_CONNECT_REQ or CONNECT_IND (CONNECT_REQ) packets received OK and not ignored + uint8_t nTxConnectRsp; //!< Number of AUX_CONNECT_RSP packets transmitted + uint16_t nRxNok; //!< Number of packets received with CRC error + uint16_t nRxIgnored; //!< Number of packets received with CRC OK, but ignored + uint8_t nRxBufFull; //!< Number of packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet (signed) + ratmr_t timeStamp; //!< Time stamp of the last received packet } __RFC_STRUCT_ATTR; //! @} @@ -2667,19 +2667,19 @@ struct __RFC_STRUCT rfc_bleAdvOutput_s struct __RFC_STRUCT rfc_bleScannerOutput_s { - uint16_t nTxScanReq; //!< Number of transmitted SCAN_REQ packets - uint16_t nBackedOffScanReq; //!< Number of SCAN_REQ packets not sent due to backoff procedure - uint16_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored - uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored - uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error - uint16_t nRxScanRspOk; //!< Number of SCAN_RSP packets received with CRC OK and not ignored - uint16_t nRxScanRspIgnored; //!< Number of SCAN_RSP packets received with CRC OK, but ignored - uint16_t nRxScanRspNok; //!< Number of SCAN_RSP packets received with CRC error - uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue - uint8_t nRxScanRspBufFull; //!< Number of SCAN_RSP packets received that did not fit in Rx queue - int8_t lastRssi; //!< The RSSI of the last received packet (signed) - uint8_t __dummy0; - ratmr_t timeStamp; //!< Time stamp of the last successfully received ADV*_IND packet that was not ignored + uint16_t nTxScanReq; //!< Number of transmitted SCAN_REQ packets + uint16_t nBackedOffScanReq; //!< Number of SCAN_REQ packets not sent due to backoff procedure + uint16_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored + uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored + uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error + uint16_t nRxScanRspOk; //!< Number of SCAN_RSP packets received with CRC OK and not ignored + uint16_t nRxScanRspIgnored; //!< Number of SCAN_RSP packets received with CRC OK, but ignored + uint16_t nRxScanRspNok; //!< Number of SCAN_RSP packets received with CRC error + uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue + uint8_t nRxScanRspBufFull; //!< Number of SCAN_RSP packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet (signed) + uint8_t __dummy0; + ratmr_t timeStamp; //!< Time stamp of the last successfully received ADV*_IND packet that was not ignored } __RFC_STRUCT_ATTR; //! @} @@ -2690,13 +2690,13 @@ struct __RFC_STRUCT rfc_bleScannerOutput_s struct __RFC_STRUCT rfc_bleInitiatorOutput_s { - uint8_t nTxConnectReq; //!< Number of transmitted CONNECT_IND (CONNECT_REQ) packets - uint8_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored - uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored - uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error - uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue - int8_t lastRssi; //!< The RSSI of the last received packet (signed) - ratmr_t timeStamp; //!< Time stamp of the received ADV*_IND packet that caused transmission of CONNECT_IND (CONNECT_REQ) + uint8_t nTxConnectReq; //!< Number of transmitted CONNECT_IND (CONNECT_REQ) packets + uint8_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored + uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored + uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error + uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet (signed) + ratmr_t timeStamp; //!< Time stamp of the received ADV*_IND packet that caused transmission of CONNECT_IND (CONNECT_REQ) } __RFC_STRUCT_ATTR; //! @} @@ -2707,19 +2707,19 @@ struct __RFC_STRUCT rfc_bleInitiatorOutput_s struct __RFC_STRUCT rfc_ble5ScanInitOutput_s { - uint16_t nTxReq; //!< Number of transmitted AUX_SCAN_REQ, SCAN_REQ, AUX_CONNECT_REQ, or CONNECT_IND packets - uint16_t nBackedOffReq; //!< Number of AUX_SCAN_REQ, SCAN_REQ, or AUX_CONNECT_REQ packets not sent due to backoff procedure - uint16_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored - uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored - uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error - uint16_t nRxRspOk; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received with CRC OK and not ignored - uint16_t nRxRspIgnored; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received with CRC OK, but ignored - uint16_t nRxRspNok; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received with CRC error - uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue - uint8_t nRxRspBufFull; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received that did not fit in Rx queue - int8_t lastRssi; //!< The RSSI of the last received packet (signed) - uint8_t __dummy0; - ratmr_t timeStamp; //!< Time stamp of the last successfully received *ADV*_IND packet that was not ignored + uint16_t nTxReq; //!< Number of transmitted AUX_SCAN_REQ, SCAN_REQ, AUX_CONNECT_REQ, or CONNECT_IND packets + uint16_t nBackedOffReq; //!< Number of AUX_SCAN_REQ, SCAN_REQ, or AUX_CONNECT_REQ packets not sent due to backoff procedure + uint16_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored + uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored + uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error + uint16_t nRxRspOk; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received with CRC OK and not ignored + uint16_t nRxRspIgnored; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received with CRC OK, but ignored + uint16_t nRxRspNok; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received with CRC error + uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue + uint8_t nRxRspBufFull; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet (signed) + uint8_t __dummy0; + ratmr_t timeStamp; //!< Time stamp of the last successfully received *ADV*_IND packet that was not ignored } __RFC_STRUCT_ATTR; //! @} @@ -2730,12 +2730,12 @@ struct __RFC_STRUCT rfc_ble5ScanInitOutput_s struct __RFC_STRUCT rfc_bleGenericRxOutput_s { - uint16_t nRxOk; //!< Number of packets received with CRC OK - uint16_t nRxNok; //!< Number of packets received with CRC error - uint16_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space - int8_t lastRssi; //!< The RSSI of the last received packet (signed) - uint8_t __dummy0; - ratmr_t timeStamp; //!< Time stamp of the last received packet + uint16_t nRxOk; //!< Number of packets received with CRC OK + uint16_t nRxNok; //!< Number of packets received with CRC error + uint16_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< The RSSI of the last received packet (signed) + uint8_t __dummy0; + ratmr_t timeStamp; //!< Time stamp of the last received packet } __RFC_STRUCT_ATTR; //! @} @@ -2746,7 +2746,7 @@ struct __RFC_STRUCT rfc_bleGenericRxOutput_s struct __RFC_STRUCT rfc_bleTxTestOutput_s { - uint16_t nTx; //!< Number of packets transmitted + uint16_t nTx; //!< Number of packets transmitted } __RFC_STRUCT_ATTR; //! @} @@ -2757,39 +2757,39 @@ struct __RFC_STRUCT rfc_bleTxTestOutput_s struct __RFC_STRUCT rfc_ble5ExtAdvEntry_s { - struct - { - uint8_t length: 6; //!< Extended header length - uint8_t advMode: 2; //!< \brief Advertiser mode as defined in BLE:
- //!< 0: Non-connectable, non-scannable
- //!< 1: Connectable, non-scannable
- //!< 2: Non-connectable, scannable
- //!< 3: Reserved - } extHdrInfo; - uint8_t extHdrFlags; //!< Extended header flags as defined in BLE - struct - { - uint8_t bSkipAdvA: 1; //!< \brief 0: AdvA is present in extended payload if configured in - //!< extHdrFlags
- //!< 1: AdvA is inserted automatically from command structure if configured in - //!< extHdrFlags and is omitted from extended header - uint8_t bSkipTargetA: 1; //!< \brief 0: TargetA is present in extended payload if configured in - //!< extHdrFlags. For response messages, the value is replaced - //!< by the received address when sending
- //!< 1: TargetA is inserted automatically from command structure or received - //!< address if configured in extHdrFlags and is omitted from - //!< extended header. Not supported with CMD_BLE5_ADV_EXT. - uint8_t deviceAddrType: 1; //!< \brief If bSkipAdvA = 0: The type of the device address in extended - //!< header buffer -- public (0) or random (1) - uint8_t targetAddrType: 1; //!< \brief If bSkipAdvA = 0: The type of the target address in extended - //!< header buffer -- public (0) or random (1) - } extHdrConfig; - uint8_t advDataLen; //!< Size of payload buffer - uint8_t* pExtHeader; //!< \brief Pointer to buffer containing extended header. If no fields except extended - //!< header flags, automatic advertiser address, or automatic target address are - //!< present, pointer may be NULL. - uint8_t* pAdvData; //!< \brief Pointer to buffer containing advData. If advDataLen = 0, - //!< pointer may be NULL. + struct + { + uint8_t length : 6; //!< Extended header length + uint8_t advMode : 2; //!< \brief Advertiser mode as defined in BLE:
+ //!< 0: Non-connectable, non-scannable
+ //!< 1: Connectable, non-scannable
+ //!< 2: Non-connectable, scannable
+ //!< 3: Reserved + } extHdrInfo; + uint8_t extHdrFlags; //!< Extended header flags as defined in BLE + struct + { + uint8_t bSkipAdvA : 1; //!< \brief 0: AdvA is present in extended payload if configured in + //!< extHdrFlags
+ //!< 1: AdvA is inserted automatically from command structure if configured in + //!< extHdrFlags and is omitted from extended header + uint8_t bSkipTargetA : 1; //!< \brief 0: TargetA is present in extended payload if configured in + //!< extHdrFlags. For response messages, the value is replaced + //!< by the received address when sending
+ //!< 1: TargetA is inserted automatically from command structure or received + //!< address if configured in extHdrFlags and is omitted from + //!< extended header. Not supported with CMD_BLE5_ADV_EXT. + uint8_t deviceAddrType : 1; //!< \brief If bSkipAdvA = 0: The type of the device address in extended + //!< header buffer -- public (0) or random (1) + uint8_t targetAddrType : 1; //!< \brief If bSkipAdvA = 0: The type of the target address in extended + //!< header buffer -- public (0) or random (1) + } extHdrConfig; + uint8_t advDataLen; //!< Size of payload buffer + uint8_t* pExtHeader; //!< \brief Pointer to buffer containing extended header. If no fields except extended + //!< header flags, automatic advertiser address, or automatic target address are + //!< present, pointer may be NULL. + uint8_t* pAdvData; //!< \brief Pointer to buffer containing advData. If advDataLen = 0, + //!< pointer may be NULL. } __RFC_STRUCT_ATTR; //! @} @@ -2800,20 +2800,20 @@ struct __RFC_STRUCT rfc_ble5ExtAdvEntry_s struct __RFC_STRUCT rfc_bleWhiteListEntry_s { - uint8_t size; //!< Number of while list entries. Used in the first entry of the list only - struct - { - uint8_t bEnable: 1; //!< 1 if the entry is in use, 0 if the entry is not in use - uint8_t addrType: 1; //!< The type address in the entry -- public (0) or random (1) - uint8_t bWlIgn: 1; //!< \brief 1 if the entry is to be ignored by a scanner if the AdvDataInfo - //!< field is not present, 0 otherwise. Used to mask out entries that - //!< have already been scanned and reported. - uint8_t : 1; - uint8_t bPrivIgn: 1; //!< \brief 1 if the entry is to be ignored as part of a privacy algorithm, - //!< 0 otherwise - } conf; - uint16_t address; //!< Least significant 16 bits of the address contained in the entry - uint32_t addressHi; //!< Most significant 32 bits of the address contained in the entry + uint8_t size; //!< Number of while list entries. Used in the first entry of the list only + struct + { + uint8_t bEnable : 1; //!< 1 if the entry is in use, 0 if the entry is not in use + uint8_t addrType : 1; //!< The type address in the entry -- public (0) or random (1) + uint8_t bWlIgn : 1; //!< \brief 1 if the entry is to be ignored by a scanner if the AdvDataInfo + //!< field is not present, 0 otherwise. Used to mask out entries that + //!< have already been scanned and reported. + uint8_t : 1; + uint8_t bPrivIgn : 1; //!< \brief 1 if the entry is to be ignored as part of a privacy algorithm, + //!< 0 otherwise + } conf; + uint16_t address; //!< Least significant 16 bits of the address contained in the entry + uint32_t addressHi; //!< Most significant 32 bits of the address contained in the entry } __RFC_STRUCT_ATTR; //! @} @@ -2824,16 +2824,16 @@ struct __RFC_STRUCT rfc_bleWhiteListEntry_s struct __RFC_STRUCT rfc_ble5AdiEntry_s { - struct - { - uint16_t advDataId: 12; //!< \brief If bValid = 1: Last Advertising Data ID (DID) for the - //!< Advertising Set ID (SID) corresponding to the entry number in the array - uint16_t mode: 2; //!< \brief 0: Entry is invalid (always receive packet with the given SID)
- //!< 1: Entry is valid (ignore packets with the given SID where DID equals - //!< advDataId)
- //!< 2: Entry is blocked (always ignore packet with the given SID)
- //!< 3: Reserved - } advDataInfo; + struct + { + uint16_t advDataId : 12; //!< \brief If bValid = 1: Last Advertising Data ID (DID) for the + //!< Advertising Set ID (SID) corresponding to the entry number in the array + uint16_t mode : 2; //!< \brief 0: Entry is invalid (always receive packet with the given SID)
+ //!< 1: Entry is valid (ignore packets with the given SID where DID equals + //!< advDataId)
+ //!< 2: Entry is blocked (always ignore packet with the given SID)
+ //!< 3: Reserved + } advDataInfo; } __RFC_STRUCT_ATTR; //! @} @@ -2844,13 +2844,13 @@ struct __RFC_STRUCT rfc_ble5AdiEntry_s struct __RFC_STRUCT rfc_bleRxStatus_s { - struct - { - uint8_t channel: 6; //!< \brief The channel on which the packet was received, provided channel is in the range - //!< 0--39; otherwise 0x3F - uint8_t bIgnore: 1; //!< 1 if the packet is marked as ignored, 0 otherwise - uint8_t bCrcErr: 1; //!< 1 if the packet was received with CRC error, 0 otherwise - } status; + struct + { + uint8_t channel : 6; //!< \brief The channel on which the packet was received, provided channel is in the range + //!< 0--39; otherwise 0x3F + uint8_t bIgnore : 1; //!< 1 if the packet is marked as ignored, 0 otherwise + uint8_t bCrcErr : 1; //!< 1 if the packet was received with CRC error, 0 otherwise + } status; } __RFC_STRUCT_ATTR; //! @} @@ -2861,18 +2861,18 @@ struct __RFC_STRUCT rfc_bleRxStatus_s struct __RFC_STRUCT rfc_ble5RxStatus_s { - struct - { - uint16_t channel: 6; //!< \brief The channel on which the packet was received, provided channel is in the range - //!< 0--39; otherwise 0x3F - uint16_t bIgnore: 1; //!< 1 if the packet is marked as ignored, 0 otherwise - uint16_t bCrcErr: 1; //!< 1 if the packet was received with CRC error, 0 otherwise - uint16_t phyMode: 2; //!< \brief The PHY on which the packet was received
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded, S = 8 (125 kbps)
- //!< 3: Coded, S = 2 (500 kbps) - } status; + struct + { + uint16_t channel : 6; //!< \brief The channel on which the packet was received, provided channel is in the range + //!< 0--39; otherwise 0x3F + uint16_t bIgnore : 1; //!< 1 if the packet is marked as ignored, 0 otherwise + uint16_t bCrcErr : 1; //!< 1 if the packet was received with CRC error, 0 otherwise + uint16_t phyMode : 2; //!< \brief The PHY on which the packet was received
+ //!< 0: 1 Mbps
+ //!< 1: 2 Mbps
+ //!< 2: Coded, S = 8 (125 kbps)
+ //!< 3: Coded, S = 2 (500 kbps) + } status; } __RFC_STRUCT_ATTR; //! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_mailbox.h index abc14d3..68646fa 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_mailbox.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_mailbox.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_ble_mailbox.h -* Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018) -* Revision: 18171 -* -* Description: Definitions for BLE interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_ble_mailbox.h + * Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018) + * Revision: 18171 + * + * Description: Definitions for BLE interface + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _BLE_MAILBOX_H #define _BLE_MAILBOX_H @@ -43,34 +43,33 @@ ///@{ /// \name Operation finished normally ///@{ -#define BLE_DONE_OK 0x1400 ///< Operation ended normally -#define BLE_DONE_RXTIMEOUT 0x1401 ///< Timeout of first Rx of slave operation or end of scan window -#define BLE_DONE_NOSYNC 0x1402 ///< Timeout of subsequent Rx -#define BLE_DONE_RXERR 0x1403 ///< Operation ended because of receive error (CRC or other) -#define BLE_DONE_CONNECT 0x1404 ///< CONNECT_IND or AUX_CONNECT_RSP received or transmitted -#define BLE_DONE_MAXNACK 0x1405 ///< Maximum number of retransmissions exceeded -#define BLE_DONE_ENDED 0x1406 ///< Operation stopped after end trigger -#define BLE_DONE_ABORT 0x1407 ///< Operation aborted by command -#define BLE_DONE_STOPPED 0x1408 ///< Operation stopped after stop command -#define BLE_DONE_AUX 0x1409 ///< Operation ended after following aux pointer pointing far ahead -#define BLE_DONE_CONNECT_CHSEL0 0x140A ///< CONNECT_IND received or transmitted; peer does not support channel selection algorithm #2 -#define BLE_DONE_SCAN_RSP 0x140B ///< SCAN_RSP or AUX_SCAN_RSP transmitted +#define BLE_DONE_OK 0x1400 ///< Operation ended normally +#define BLE_DONE_RXTIMEOUT 0x1401 ///< Timeout of first Rx of slave operation or end of scan window +#define BLE_DONE_NOSYNC 0x1402 ///< Timeout of subsequent Rx +#define BLE_DONE_RXERR 0x1403 ///< Operation ended because of receive error (CRC or other) +#define BLE_DONE_CONNECT 0x1404 ///< CONNECT_IND or AUX_CONNECT_RSP received or transmitted +#define BLE_DONE_MAXNACK 0x1405 ///< Maximum number of retransmissions exceeded +#define BLE_DONE_ENDED 0x1406 ///< Operation stopped after end trigger +#define BLE_DONE_ABORT 0x1407 ///< Operation aborted by command +#define BLE_DONE_STOPPED 0x1408 ///< Operation stopped after stop command +#define BLE_DONE_AUX 0x1409 ///< Operation ended after following aux pointer pointing far ahead +#define BLE_DONE_CONNECT_CHSEL0 0x140A ///< CONNECT_IND received or transmitted; peer does not support channel selection algorithm #2 +#define BLE_DONE_SCAN_RSP 0x140B ///< SCAN_RSP or AUX_SCAN_RSP transmitted ///@} /// \name Operation finished with error ///@{ -#define BLE_ERROR_PAR 0x1800 ///< Illegal parameter -#define BLE_ERROR_RXBUF 0x1801 ///< No available Rx buffer (Advertiser, Scanner, Initiator) -#define BLE_ERROR_NO_SETUP 0x1802 ///< Operation using Rx or Tx attempted when not in BLE mode -#define BLE_ERROR_NO_FS 0x1803 ///< Operation using Rx or Tx attempted without frequency synth configured -#define BLE_ERROR_SYNTH_PROG 0x1804 ///< Synthesizer programming failed to complete on time -#define BLE_ERROR_RXOVF 0x1805 ///< Receiver overflowed during operation -#define BLE_ERROR_TXUNF 0x1806 ///< Transmitter underflowed during operation -#define BLE_ERROR_AUX 0x1807 ///< Calculated AUX pointer was too far into the future or in the past +#define BLE_ERROR_PAR 0x1800 ///< Illegal parameter +#define BLE_ERROR_RXBUF 0x1801 ///< No available Rx buffer (Advertiser, Scanner, Initiator) +#define BLE_ERROR_NO_SETUP 0x1802 ///< Operation using Rx or Tx attempted when not in BLE mode +#define BLE_ERROR_NO_FS 0x1803 ///< Operation using Rx or Tx attempted without frequency synth configured +#define BLE_ERROR_SYNTH_PROG 0x1804 ///< Synthesizer programming failed to complete on time +#define BLE_ERROR_RXOVF 0x1805 ///< Receiver overflowed during operation +#define BLE_ERROR_TXUNF 0x1806 ///< Transmitter underflowed during operation +#define BLE_ERROR_AUX 0x1807 ///< Calculated AUX pointer was too far into the future or in the past ///@} ///@} - /// Special trigger for BLE slave command -#define BLE_TRIG_REL_SYNC 15 +#define BLE_TRIG_REL_SYNC 15 #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_common_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_common_cmd.h index ccf4867..b701beb 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_common_cmd.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_common_cmd.h @@ -1,56 +1,56 @@ /****************************************************************************** -* Filename: rf_common_cmd.h -* Revised: 2018-11-02 11:52:02 +0100 (Fri, 02 Nov 2018) -* Revision: 18756 -* -* Description: CC13x2/CC26x2 API for common/generic commands -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_common_cmd.h + * Revised: 2018-11-02 11:52:02 +0100 (Fri, 02 Nov 2018) + * Revision: 18756 + * + * Description: CC13x2/CC26x2 API for common/generic commands + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __COMMON_CMD_H #define __COMMON_CMD_H #ifndef __RFC_STRUCT - #define __RFC_STRUCT +#define __RFC_STRUCT #endif #ifndef __RFC_STRUCT_ATTR - #if defined(__GNUC__) - #define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) - #elif defined(__TI_ARM__) - #define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) - #else - #define __RFC_STRUCT_ATTR - #endif +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__((aligned(4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__((__packed__, aligned(4))) +#else +#define __RFC_STRUCT_ATTR +#endif #endif //! \addtogroup rfc @@ -59,8 +59,8 @@ //! \addtogroup common_cmd //! @{ -#include #include "rf_mailbox.h" +#include typedef struct __RFC_STRUCT rfc_command_s rfc_command_t; typedef struct __RFC_STRUCT rfc_radioOp_s rfc_radioOp_t; @@ -113,7 +113,7 @@ typedef struct __RFC_STRUCT rfc_CMD_SET_CMD_START_IRQ_s rfc_CMD_SET_CMD_START_IR //! @{ struct __RFC_STRUCT rfc_command_s { - uint16_t commandNo; //!< The command ID number + uint16_t commandNo; //!< The command ID number } __RFC_STRUCT_ATTR; //! @} @@ -124,606 +124,606 @@ struct __RFC_STRUCT rfc_command_s struct __RFC_STRUCT rfc_radioOp_s { - uint16_t commandNo; //!< The command ID number - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_NOP //! @{ -#define CMD_NOP 0x0801 +#define CMD_NOP 0x0801 //! No Operation Command struct __RFC_STRUCT rfc_CMD_NOP_s { - uint16_t commandNo; //!< The command ID number 0x0801 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; + uint16_t commandNo; //!< The command ID number 0x0801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_RADIO_SETUP //! @{ -#define CMD_RADIO_SETUP 0x0802 +#define CMD_RADIO_SETUP 0x0802 //! Radio Setup Command for Pre-Defined Schemes struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_s { - uint16_t commandNo; //!< The command ID number 0x0802 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t mode; //!< \brief The main mode to use
- //!< 0x00: BLE
- //!< 0x01: IEEE 802.15.4
- //!< 0x02: 2 Mbps GFSK
- //!< 0x05: 5 Mbps coded 8-FSK
- //!< 0xFF: Keep existing mode; update overrides only
- //!< Others: Reserved - uint8_t loDivider; //!< \brief LO divider setting to use. Supported values: 0, 2, 4, - //!< 5, 6, 10, 12, 15, and 30. - struct - { - uint16_t frontEndMode: 3; //!< \brief 0x00: Differential mode
- //!< 0x01: Single-ended mode RFP
- //!< 0x02: Single-ended mode RFN
- //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
- //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ uint16_t commandNo; //!< The command ID number 0x0802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t mode; //!< \brief The main mode to use
+ //!< 0x00: BLE
+ //!< 0x01: IEEE 802.15.4
+ //!< 0x02: 2 Mbps GFSK
+ //!< 0x05: 5 Mbps coded 8-FSK
+ //!< 0xFF: Keep existing mode; update overrides only
//!< Others: Reserved - uint16_t biasMode: 1; //!< \brief 0: Internal bias
- //!< 1: External bias - uint16_t analogCfgMode: 6; //!< \brief 0x00: Write analog configuration.
- //!< Required first time after boot and when changing frequency band - //!< or front-end configuration
- //!< 0x2D: Keep analog configuration.
- //!< May be used after standby or when changing mode with the same frequency - //!< band and front-end configuration
- //!< Others: Reserved - uint16_t bNoFsPowerUp: 1; //!< \brief 0: Power up frequency synth
- //!< 1: Do not power up frequency synth - } config; //!< Configuration options - uint16_t txPower; //!< Transmit power - uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no - //!< override is used. + uint8_t loDivider; //!< \brief LO divider setting to use. Supported values: 0, 2, 4, + //!< 5, 6, 10, 12, 15, and 30. + struct + { + uint16_t frontEndMode : 3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode : 1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode : 6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp : 1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_FS //! @{ -#define CMD_FS 0x0803 +#define CMD_FS 0x0803 //! Frequency Synthesizer Programming Command struct __RFC_STRUCT rfc_CMD_FS_s { - uint16_t commandNo; //!< The command ID number 0x0803 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t frequency; //!< The frequency in MHz to tune to - uint16_t fractFreq; //!< Fractional part of the frequency to tune to - struct - { - uint8_t bTxMode: 1; //!< \brief 0: Start synth in RX mode
- //!< 1: Start synth in TX mode - uint8_t refFreq: 6; //!< \brief 0: Use default reference frequency
- //!< Others: Use reference frequency 48 MHz/refFreq - } synthConf; - uint8_t __dummy0; //!< Reserved, always write 0 - uint8_t __dummy1; //!< Reserved - uint8_t __dummy2; //!< Reserved - uint16_t __dummy3; //!< Reserved + uint16_t commandNo; //!< The command ID number 0x0803 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t frequency; //!< The frequency in MHz to tune to + uint16_t fractFreq; //!< Fractional part of the frequency to tune to + struct + { + uint8_t bTxMode : 1; //!< \brief 0: Start synth in RX mode
+ //!< 1: Start synth in TX mode + uint8_t refFreq : 6; //!< \brief 0: Use default reference frequency
+ //!< Others: Use reference frequency 48 MHz/refFreq + } synthConf; + uint8_t __dummy0; //!< Reserved, always write 0 + uint8_t __dummy1; //!< Reserved + uint8_t __dummy2; //!< Reserved + uint16_t __dummy3; //!< Reserved } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_FS_OFF //! @{ -#define CMD_FS_OFF 0x0804 +#define CMD_FS_OFF 0x0804 //! Command for Turning off Frequency Synthesizer struct __RFC_STRUCT rfc_CMD_FS_OFF_s { - uint16_t commandNo; //!< The command ID number 0x0804 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; + uint16_t commandNo; //!< The command ID number 0x0804 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_RX_TEST //! @{ -#define CMD_RX_TEST 0x0807 +#define CMD_RX_TEST 0x0807 //! Receiver Test Command struct __RFC_STRUCT rfc_CMD_RX_TEST_s { - uint16_t commandNo; //!< The command ID number 0x0807 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bEnaFifo: 1; //!< \brief 0: Do not enable FIFO in modem, so that received data is not available
- //!< 1: Enable FIFO in modem -- the data must be read out by the application - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bNoSync: 1; //!< \brief 0: Run sync search as normal for the configured mode
- //!< 1: Write correlation thresholds to the maximum value to avoid getting sync - } config; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - uint32_t syncWord; //!< Sync word to use for receiver - ratmr_t endTime; //!< Time to end the operation + uint16_t commandNo; //!< The command ID number 0x0807 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bEnaFifo : 1; //!< \brief 0: Do not enable FIFO in modem, so that received data is not available
+ //!< 1: Enable FIFO in modem -- the data must be read out by the application + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bNoSync : 1; //!< \brief 0: Run sync search as normal for the configured mode
+ //!< 1: Write correlation thresholds to the maximum value to avoid getting sync + } config; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + uint32_t syncWord; //!< Sync word to use for receiver + ratmr_t endTime; //!< Time to end the operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_TX_TEST //! @{ -#define CMD_TX_TEST 0x0808 +#define CMD_TX_TEST 0x0808 //! Transmitter Test Command struct __RFC_STRUCT rfc_CMD_TX_TEST_s { - uint16_t commandNo; //!< The command ID number 0x0808 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bUseCw: 1; //!< \brief 0: Send modulated signal
- //!< 1: Send continuous wave - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t whitenMode: 2; //!< \brief 0: No whitening
- //!< 1: Default whitening
- //!< 2: PRBS-15
- //!< 3: PRBS-32 - } config; - uint8_t __dummy0; - uint16_t txWord; //!< Value to send to the modem before whitening - uint8_t __dummy1; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - uint32_t syncWord; //!< Sync word to use for transmitter - ratmr_t endTime; //!< Time to end the operation + uint16_t commandNo; //!< The command ID number 0x0808 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bUseCw : 1; //!< \brief 0: Send modulated signal
+ //!< 1: Send continuous wave + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t whitenMode : 2; //!< \brief 0: No whitening
+ //!< 1: Default whitening
+ //!< 2: PRBS-15
+ //!< 3: PRBS-32 + } config; + uint8_t __dummy0; + uint16_t txWord; //!< Value to send to the modem before whitening + uint8_t __dummy1; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + uint32_t syncWord; //!< Sync word to use for transmitter + ratmr_t endTime; //!< Time to end the operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SYNC_STOP_RAT //! @{ -#define CMD_SYNC_STOP_RAT 0x0809 +#define CMD_SYNC_STOP_RAT 0x0809 //! Synchronize and Stop Radio Timer Command struct __RFC_STRUCT rfc_CMD_SYNC_STOP_RAT_s { - uint16_t commandNo; //!< The command ID number 0x0809 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t __dummy0; - ratmr_t rat0; //!< \brief The returned RAT timer value corresponding to the value the RAT would have had when the - //!< RTC was zero + uint16_t commandNo; //!< The command ID number 0x0809 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + ratmr_t rat0; //!< \brief The returned RAT timer value corresponding to the value the RAT would have had when the + //!< RTC was zero } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SYNC_START_RAT //! @{ -#define CMD_SYNC_START_RAT 0x080A +#define CMD_SYNC_START_RAT 0x080A //! Synchrously Start Radio Timer Command struct __RFC_STRUCT rfc_CMD_SYNC_START_RAT_s { - uint16_t commandNo; //!< The command ID number 0x080A - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t __dummy0; - ratmr_t rat0; //!< \brief The desired RAT timer value corresponding to the value the RAT would have had when the - //!< RTC was zero. This parameter is returned by CMD_SYNC_STOP_RAT + uint16_t commandNo; //!< The command ID number 0x080A + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + ratmr_t rat0; //!< \brief The desired RAT timer value corresponding to the value the RAT would have had when the + //!< RTC was zero. This parameter is returned by CMD_SYNC_STOP_RAT } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_RESYNC_RAT //! @{ -#define CMD_RESYNC_RAT 0x0816 +#define CMD_RESYNC_RAT 0x0816 //! Re-calculate rat0 value while RAT is running struct __RFC_STRUCT rfc_CMD_RESYNC_RAT_s { - uint16_t commandNo; //!< The command ID number 0x0816 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t __dummy0; - ratmr_t rat0; //!< \brief The desired RAT timer value corresponding to the value the RAT would have had when the - //!< RTC was zero + uint16_t commandNo; //!< The command ID number 0x0816 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + ratmr_t rat0; //!< \brief The desired RAT timer value corresponding to the value the RAT would have had when the + //!< RTC was zero } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_COUNT //! @{ -#define CMD_COUNT 0x080B +#define CMD_COUNT 0x080B //! Counter Command struct __RFC_STRUCT rfc_CMD_COUNT_s { - uint16_t commandNo; //!< The command ID number 0x080B - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation - //!< differs if the result is zero + uint16_t commandNo; //!< The command ID number 0x080B + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation + //!< differs if the result is zero } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_FS_POWERUP //! @{ -#define CMD_FS_POWERUP 0x080C +#define CMD_FS_POWERUP 0x080C //! Power up Frequency Syntheszier Command struct __RFC_STRUCT rfc_CMD_FS_POWERUP_s { - uint16_t commandNo; //!< The command ID number 0x080C - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t __dummy0; - uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override. If NULL, no override is used. + uint16_t commandNo; //!< The command ID number 0x080C + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override. If NULL, no override is used. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_FS_POWERDOWN //! @{ -#define CMD_FS_POWERDOWN 0x080D +#define CMD_FS_POWERDOWN 0x080D //! Power down Frequency Syntheszier Command struct __RFC_STRUCT rfc_CMD_FS_POWERDOWN_s { - uint16_t commandNo; //!< The command ID number 0x080D - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; + uint16_t commandNo; //!< The command ID number 0x080D + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SCH_IMM //! @{ -#define CMD_SCH_IMM 0x0810 +#define CMD_SCH_IMM 0x0810 //! Run Immidiate Command as Radio Operation Command struct __RFC_STRUCT rfc_CMD_SCH_IMM_s { - uint16_t commandNo; //!< The command ID number 0x0810 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t __dummy0; - uint32_t cmdrVal; //!< Value as would be written to CMDR - uint32_t cmdstaVal; //!< Value as would be returned in CMDSTA + uint16_t commandNo; //!< The command ID number 0x0810 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + uint32_t cmdrVal; //!< Value as would be written to CMDR + uint32_t cmdstaVal; //!< Value as would be returned in CMDSTA } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_COUNT_BRANCH //! @{ -#define CMD_COUNT_BRANCH 0x0812 +#define CMD_COUNT_BRANCH 0x0812 //! Counter Command with Branch of Command Chain struct __RFC_STRUCT rfc_CMD_COUNT_BRANCH_s { - uint16_t commandNo; //!< The command ID number 0x0812 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation - //!< differs if the result is zero - rfc_radioOp_t* pNextOpIfOk; //!< Pointer to next operation if counter did not expire + uint16_t commandNo; //!< The command ID number 0x0812 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation + //!< differs if the result is zero + rfc_radioOp_t* pNextOpIfOk; //!< Pointer to next operation if counter did not expire } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PATTERN_CHECK //! @{ -#define CMD_PATTERN_CHECK 0x0813 +#define CMD_PATTERN_CHECK 0x0813 //! Command for Checking a Value in Memory aginst a Pattern struct __RFC_STRUCT rfc_CMD_PATTERN_CHECK_s { - uint16_t commandNo; //!< The command ID number 0x0813 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint16_t operation: 2; //!< \brief Operation to perform
- //!< 0: True if value == compareVal
- //!< 1: True if value < compareVal
- //!< 2: True if value > compareVal
- //!< 3: Reserved - uint16_t bByteRev: 1; //!< \brief If 1, interchange the four bytes of the value, so that they are read - //!< most-significant-byte-first. - uint16_t bBitRev: 1; //!< If 1, perform bit reversal of the value - uint16_t signExtend: 5; //!< \brief 0: Treat value and compareVal as unsigned
- //!< 1--31: Treat value and compareVal as signed, where the value - //!< gives the number of the most significant bit in the signed number. - uint16_t bRxVal: 1; //!< \brief 0: Use pValue as a pointer
- //!< 1: Use pValue as a signed offset to the start of the last - //!< committed RX entry element - } patternOpt; //!< Options for comparison - rfc_radioOp_t* pNextOpIfOk; //!< Pointer to next operation if comparison result was true - uint8_t* pValue; //!< Pointer to read from, or offset from last RX entry if patternOpt.bRxVal == 1 - uint32_t mask; //!< Bit mask to apply before comparison - uint32_t compareVal; //!< Value to compare to + uint16_t commandNo; //!< The command ID number 0x0813 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint16_t operation : 2; //!< \brief Operation to perform
+ //!< 0: True if value == compareVal
+ //!< 1: True if value < compareVal
+ //!< 2: True if value > compareVal
+ //!< 3: Reserved + uint16_t bByteRev : 1; //!< \brief If 1, interchange the four bytes of the value, so that they are read + //!< most-significant-byte-first. + uint16_t bBitRev : 1; //!< If 1, perform bit reversal of the value + uint16_t signExtend : 5; //!< \brief 0: Treat value and compareVal as unsigned
+ //!< 1--31: Treat value and compareVal as signed, where the value + //!< gives the number of the most significant bit in the signed number. + uint16_t bRxVal : 1; //!< \brief 0: Use pValue as a pointer
+ //!< 1: Use pValue as a signed offset to the start of the last + //!< committed RX entry element + } patternOpt; //!< Options for comparison + rfc_radioOp_t* pNextOpIfOk; //!< Pointer to next operation if comparison result was true + uint8_t* pValue; //!< Pointer to read from, or offset from last RX entry if patternOpt.bRxVal == 1 + uint32_t mask; //!< Bit mask to apply before comparison + uint32_t compareVal; //!< Value to compare to } __RFC_STRUCT_ATTR; //! @} @@ -733,443 +733,443 @@ struct __RFC_STRUCT rfc_CMD_PATTERN_CHECK_s //! Radio Setup Command for Pre-Defined Schemes with PA Switching Fields struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_PA_s { - uint16_t commandNo; //!< The command ID number - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t mode; //!< \brief The main mode to use
- //!< 0x00: BLE
- //!< 0x01: IEEE 802.15.4
- //!< 0x02: 2 Mbps GFSK
- //!< 0x05: 5 Mbps coded 8-FSK
- //!< 0xFF: Keep existing mode; update overrides only
- //!< Others: Reserved - uint8_t loDivider; //!< \brief LO divider setting to use. Supported values: 0, 2, 4, - //!< 5, 6, 10, 12, 15, and 30. - struct - { - uint16_t frontEndMode: 3; //!< \brief 0x00: Differential mode
- //!< 0x01: Single-ended mode RFP
- //!< 0x02: Single-ended mode RFN
- //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
- //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t mode; //!< \brief The main mode to use
+ //!< 0x00: BLE
+ //!< 0x01: IEEE 802.15.4
+ //!< 0x02: 2 Mbps GFSK
+ //!< 0x05: 5 Mbps coded 8-FSK
+ //!< 0xFF: Keep existing mode; update overrides only
//!< Others: Reserved - uint16_t biasMode: 1; //!< \brief 0: Internal bias
- //!< 1: External bias - uint16_t analogCfgMode: 6; //!< \brief 0x00: Write analog configuration.
- //!< Required first time after boot and when changing frequency band - //!< or front-end configuration
- //!< 0x2D: Keep analog configuration.
- //!< May be used after standby or when changing mode with the same frequency - //!< band and front-end configuration
- //!< Others: Reserved - uint16_t bNoFsPowerUp: 1; //!< \brief 0: Power up frequency synth
- //!< 1: Do not power up frequency synth - } config; //!< Configuration options - uint16_t txPower; //!< Transmit power - uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no - //!< override is used. - uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to - //!< standard PA. Used by RF driver only, not radio CPU. - uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to - //!< 20-dBm PA. Used by RF driver only, not radio CPU. + uint8_t loDivider; //!< \brief LO divider setting to use. Supported values: 0, 2, 4, + //!< 5, 6, 10, 12, 15, and 30. + struct + { + uint16_t frontEndMode : 3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode : 1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode : 6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp : 1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. + uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< standard PA. Used by RF driver only, not radio CPU. + uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< 20-dBm PA. Used by RF driver only, not radio CPU. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_ABORT //! @{ -#define CMD_ABORT 0x0401 +#define CMD_ABORT 0x0401 //! Abort Running Radio Operation Command struct __RFC_STRUCT rfc_CMD_ABORT_s { - uint16_t commandNo; //!< The command ID number 0x0401 + uint16_t commandNo; //!< The command ID number 0x0401 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_STOP //! @{ -#define CMD_STOP 0x0402 +#define CMD_STOP 0x0402 //! Stop Running Radio Operation Command Gracefully struct __RFC_STRUCT rfc_CMD_STOP_s { - uint16_t commandNo; //!< The command ID number 0x0402 + uint16_t commandNo; //!< The command ID number 0x0402 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_GET_RSSI //! @{ -#define CMD_GET_RSSI 0x0403 +#define CMD_GET_RSSI 0x0403 //! Read RSSI Command struct __RFC_STRUCT rfc_CMD_GET_RSSI_s { - uint16_t commandNo; //!< The command ID number 0x0403 + uint16_t commandNo; //!< The command ID number 0x0403 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_UPDATE_RADIO_SETUP //! @{ -#define CMD_UPDATE_RADIO_SETUP 0x0001 +#define CMD_UPDATE_RADIO_SETUP 0x0001 //! Update Radio Settings Command struct __RFC_STRUCT rfc_CMD_UPDATE_RADIO_SETUP_s { - uint16_t commandNo; //!< The command ID number 0x0001 - uint16_t __dummy0; - uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override + uint16_t commandNo; //!< The command ID number 0x0001 + uint16_t __dummy0; + uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_TRIGGER //! @{ -#define CMD_TRIGGER 0x0404 +#define CMD_TRIGGER 0x0404 //! Generate Command Trigger struct __RFC_STRUCT rfc_CMD_TRIGGER_s { - uint16_t commandNo; //!< The command ID number 0x0404 - uint8_t triggerNo; //!< Command trigger number + uint16_t commandNo; //!< The command ID number 0x0404 + uint8_t triggerNo; //!< Command trigger number } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_GET_FW_INFO //! @{ -#define CMD_GET_FW_INFO 0x0002 +#define CMD_GET_FW_INFO 0x0002 //! Request Information on the RF Core ROM Firmware struct __RFC_STRUCT rfc_CMD_GET_FW_INFO_s { - uint16_t commandNo; //!< The command ID number 0x0002 - uint16_t versionNo; //!< Firmware version number - uint16_t startOffset; //!< The start of free RAM - uint16_t freeRamSz; //!< The size of free RAM - uint16_t availRatCh; //!< Bitmap of available RAT channels + uint16_t commandNo; //!< The command ID number 0x0002 + uint16_t versionNo; //!< Firmware version number + uint16_t startOffset; //!< The start of free RAM + uint16_t freeRamSz; //!< The size of free RAM + uint16_t availRatCh; //!< Bitmap of available RAT channels } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_START_RAT //! @{ -#define CMD_START_RAT 0x0405 +#define CMD_START_RAT 0x0405 //! Asynchronously Start Radio Timer Command struct __RFC_STRUCT rfc_CMD_START_RAT_s { - uint16_t commandNo; //!< The command ID number 0x0405 + uint16_t commandNo; //!< The command ID number 0x0405 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PING //! @{ -#define CMD_PING 0x0406 +#define CMD_PING 0x0406 //! Respond with Command ACK Only struct __RFC_STRUCT rfc_CMD_PING_s { - uint16_t commandNo; //!< The command ID number 0x0406 + uint16_t commandNo; //!< The command ID number 0x0406 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_READ_RFREG //! @{ -#define CMD_READ_RFREG 0x0601 +#define CMD_READ_RFREG 0x0601 //! Read RF Core Hardware Register struct __RFC_STRUCT rfc_CMD_READ_RFREG_s { - uint16_t commandNo; //!< The command ID number 0x0601 - uint16_t address; //!< The offset from the start of the RF core HW register bank (0x40040000) - uint32_t value; //!< Returned value of the register + uint16_t commandNo; //!< The command ID number 0x0601 + uint16_t address; //!< The offset from the start of the RF core HW register bank (0x40040000) + uint32_t value; //!< Returned value of the register } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_ADD_DATA_ENTRY //! @{ -#define CMD_ADD_DATA_ENTRY 0x0005 +#define CMD_ADD_DATA_ENTRY 0x0005 //! Add Data Entry to Queue struct __RFC_STRUCT rfc_CMD_ADD_DATA_ENTRY_s { - uint16_t commandNo; //!< The command ID number 0x0005 - uint16_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to the queue structure to which the entry will be added - uint8_t* pEntry; //!< Pointer to the entry + uint16_t commandNo; //!< The command ID number 0x0005 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to which the entry will be added + uint8_t* pEntry; //!< Pointer to the entry } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_REMOVE_DATA_ENTRY //! @{ -#define CMD_REMOVE_DATA_ENTRY 0x0006 +#define CMD_REMOVE_DATA_ENTRY 0x0006 //! Remove First Data Entry from Queue struct __RFC_STRUCT rfc_CMD_REMOVE_DATA_ENTRY_s { - uint16_t commandNo; //!< The command ID number 0x0006 - uint16_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to the queue structure from which the entry will be removed - uint8_t* pEntry; //!< Pointer to the entry that was removed + uint16_t commandNo; //!< The command ID number 0x0006 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure from which the entry will be removed + uint8_t* pEntry; //!< Pointer to the entry that was removed } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_FLUSH_QUEUE //! @{ -#define CMD_FLUSH_QUEUE 0x0007 +#define CMD_FLUSH_QUEUE 0x0007 //! Flush Data Queue struct __RFC_STRUCT rfc_CMD_FLUSH_QUEUE_s { - uint16_t commandNo; //!< The command ID number 0x0007 - uint16_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed - uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed + uint16_t commandNo; //!< The command ID number 0x0007 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed + uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_CLEAR_RX //! @{ -#define CMD_CLEAR_RX 0x0008 +#define CMD_CLEAR_RX 0x0008 //! Clear all RX Queue Entries struct __RFC_STRUCT rfc_CMD_CLEAR_RX_s { - uint16_t commandNo; //!< The command ID number 0x0008 - uint16_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to the queue structure to be cleared + uint16_t commandNo; //!< The command ID number 0x0008 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to be cleared } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_REMOVE_PENDING_ENTRIES //! @{ -#define CMD_REMOVE_PENDING_ENTRIES 0x0009 +#define CMD_REMOVE_PENDING_ENTRIES 0x0009 //! Remove Pending Entries from Queue struct __RFC_STRUCT rfc_CMD_REMOVE_PENDING_ENTRIES_s { - uint16_t commandNo; //!< The command ID number 0x0009 - uint16_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed - uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed + uint16_t commandNo; //!< The command ID number 0x0009 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed + uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SET_RAT_CMP //! @{ -#define CMD_SET_RAT_CMP 0x000A +#define CMD_SET_RAT_CMP 0x000A //! Set Radio Timer Channel in Compare Mode struct __RFC_STRUCT rfc_CMD_SET_RAT_CMP_s { - uint16_t commandNo; //!< The command ID number 0x000A - uint8_t ratCh; //!< The radio timer channel number - uint8_t __dummy0; - ratmr_t compareTime; //!< The time at which the compare occurs + uint16_t commandNo; //!< The command ID number 0x000A + uint8_t ratCh; //!< The radio timer channel number + uint8_t __dummy0; + ratmr_t compareTime; //!< The time at which the compare occurs } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SET_RAT_CPT //! @{ -#define CMD_SET_RAT_CPT 0x0603 +#define CMD_SET_RAT_CPT 0x0603 //! Set Radio Timer Channel in Capture Mode struct __RFC_STRUCT rfc_CMD_SET_RAT_CPT_s { - uint16_t commandNo; //!< The command ID number 0x0603 - struct - { - uint16_t : 3; - uint16_t inputSrc: 5; //!< Input source indicator - uint16_t ratCh: 4; //!< The radio timer channel number - uint16_t bRepeated: 1; //!< \brief 0: Single capture mode
- //!< 1: Repeated capture mode - uint16_t inputMode: 2; //!< \brief Input mode:
- //!< 0: Capture on rising edge
- //!< 1: Capture on falling edge
- //!< 2: Capture on both edges
- //!< 3: Reserved - } config; + uint16_t commandNo; //!< The command ID number 0x0603 + struct + { + uint16_t : 3; + uint16_t inputSrc : 5; //!< Input source indicator + uint16_t ratCh : 4; //!< The radio timer channel number + uint16_t bRepeated : 1; //!< \brief 0: Single capture mode
+ //!< 1: Repeated capture mode + uint16_t inputMode : 2; //!< \brief Input mode:
+ //!< 0: Capture on rising edge
+ //!< 1: Capture on falling edge
+ //!< 2: Capture on both edges
+ //!< 3: Reserved + } config; } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_DISABLE_RAT_CH //! @{ -#define CMD_DISABLE_RAT_CH 0x0408 +#define CMD_DISABLE_RAT_CH 0x0408 //! Disable Radio Timer Channel struct __RFC_STRUCT rfc_CMD_DISABLE_RAT_CH_s { - uint16_t commandNo; //!< The command ID number 0x0408 - uint8_t ratCh; //!< The radio timer channel number + uint16_t commandNo; //!< The command ID number 0x0408 + uint8_t ratCh; //!< The radio timer channel number } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SET_RAT_OUTPUT //! @{ -#define CMD_SET_RAT_OUTPUT 0x0604 +#define CMD_SET_RAT_OUTPUT 0x0604 //! Set Radio Timer Output to a Specified Mode struct __RFC_STRUCT rfc_CMD_SET_RAT_OUTPUT_s { - uint16_t commandNo; //!< The command ID number 0x0604 - struct - { - uint16_t : 2; - uint16_t outputSel: 3; //!< Output event indicator - uint16_t outputMode: 3; //!< \brief 0: Set output line low as default; and pulse on event. Duration of pulse is one RF Core clock period (ca. 41.67 ns).
- //!< 1: Set output line high on event
- //!< 2: Set output line low on event
- //!< 3: Toggle (invert) output line state on event
- //!< 4: Immediately set output line to low (does not change upon event)
- //!< 5: Immediately set output line to high (does not change upon event)
- //!< Others: Reserved - uint16_t ratCh: 4; //!< The radio timer channel number - } config; + uint16_t commandNo; //!< The command ID number 0x0604 + struct + { + uint16_t : 2; + uint16_t outputSel : 3; //!< Output event indicator + uint16_t outputMode : 3; //!< \brief 0: Set output line low as default; and pulse on event. Duration of pulse is one RF Core clock period (ca. 41.67 ns).
+ //!< 1: Set output line high on event
+ //!< 2: Set output line low on event
+ //!< 3: Toggle (invert) output line state on event
+ //!< 4: Immediately set output line to low (does not change upon event)
+ //!< 5: Immediately set output line to high (does not change upon event)
+ //!< Others: Reserved + uint16_t ratCh : 4; //!< The radio timer channel number + } config; } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_ARM_RAT_CH //! @{ -#define CMD_ARM_RAT_CH 0x0409 +#define CMD_ARM_RAT_CH 0x0409 //! Arm Radio Timer Channel struct __RFC_STRUCT rfc_CMD_ARM_RAT_CH_s { - uint16_t commandNo; //!< The command ID number 0x0409 - uint8_t ratCh; //!< The radio timer channel number + uint16_t commandNo; //!< The command ID number 0x0409 + uint8_t ratCh; //!< The radio timer channel number } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_DISARM_RAT_CH //! @{ -#define CMD_DISARM_RAT_CH 0x040A +#define CMD_DISARM_RAT_CH 0x040A //! Disarm Radio Timer Channel struct __RFC_STRUCT rfc_CMD_DISARM_RAT_CH_s { - uint16_t commandNo; //!< The command ID number 0x040A - uint8_t ratCh; //!< The radio timer channel number + uint16_t commandNo; //!< The command ID number 0x040A + uint8_t ratCh; //!< The radio timer channel number } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SET_TX_POWER //! @{ -#define CMD_SET_TX_POWER 0x0010 +#define CMD_SET_TX_POWER 0x0010 //! Set Transmit Power struct __RFC_STRUCT rfc_CMD_SET_TX_POWER_s { - uint16_t commandNo; //!< The command ID number 0x0010 - uint16_t txPower; //!< New TX power setting + uint16_t commandNo; //!< The command ID number 0x0010 + uint16_t txPower; //!< New TX power setting } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SET_TX20_POWER //! @{ -#define CMD_SET_TX20_POWER 0x0014 +#define CMD_SET_TX20_POWER 0x0014 //! Set Transmit Power for 20-dBm PA struct __RFC_STRUCT rfc_CMD_SET_TX20_POWER_s { - uint16_t commandNo; //!< The command ID number 0x0014 - uint16_t __dummy0; - uint32_t tx20Power; //!< New TX power setting + uint16_t commandNo; //!< The command ID number 0x0014 + uint16_t __dummy0; + uint32_t tx20Power; //!< New TX power setting } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_CHANGE_PA //! @{ -#define CMD_CHANGE_PA 0x0015 +#define CMD_CHANGE_PA 0x0015 //! Set TX power with possibility to switch between PAs struct __RFC_STRUCT rfc_CMD_CHANGE_PA_s { - uint16_t commandNo; //!< The command ID number 0x0015 - uint16_t __dummy0; - uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override as part of the - //!< change, including new TX power + uint16_t commandNo; //!< The command ID number 0x0015 + uint16_t __dummy0; + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override as part of the + //!< change, including new TX power } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_UPDATE_HPOSC_FREQ //! @{ -#define CMD_UPDATE_HPOSC_FREQ 0x0608 +#define CMD_UPDATE_HPOSC_FREQ 0x0608 //! Set New Frequency Offset for HPOSC struct __RFC_STRUCT rfc_CMD_UPDATE_HPOSC_FREQ_s { - uint16_t commandNo; //!< The command ID number 0x0608 - int16_t freqOffset; //!< Relative frequency offset, signed, scaled by 2-22 + uint16_t commandNo; //!< The command ID number 0x0608 + int16_t freqOffset; //!< Relative frequency offset, signed, scaled by 2-22 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_UPDATE_FS //! @{ -#define CMD_UPDATE_FS 0x0011 +#define CMD_UPDATE_FS 0x0011 //! Set New Synthesizer Frequency without Recalibration (Deprecated; use CMD_MODIFY_FS) struct __RFC_STRUCT rfc_CMD_UPDATE_FS_s { - uint16_t commandNo; //!< The command ID number 0x0011 - uint16_t __dummy0; - uint32_t __dummy1; - uint32_t __dummy2; - uint16_t __dummy3; - uint16_t frequency; //!< The frequency in MHz to tune to - uint16_t fractFreq; //!< Fractional part of the frequency to tune to + uint16_t commandNo; //!< The command ID number 0x0011 + uint16_t __dummy0; + uint32_t __dummy1; + uint32_t __dummy2; + uint16_t __dummy3; + uint16_t frequency; //!< The frequency in MHz to tune to + uint16_t fractFreq; //!< Fractional part of the frequency to tune to } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_MODIFY_FS //! @{ -#define CMD_MODIFY_FS 0x0013 +#define CMD_MODIFY_FS 0x0013 //! Set New Synthesizer Frequency without Recalibration struct __RFC_STRUCT rfc_CMD_MODIFY_FS_s { - uint16_t commandNo; //!< The command ID number 0x0013 - uint16_t frequency; //!< The frequency in MHz to tune to - uint16_t fractFreq; //!< Fractional part of the frequency to tune to + uint16_t commandNo; //!< The command ID number 0x0013 + uint16_t frequency; //!< The frequency in MHz to tune to + uint16_t fractFreq; //!< Fractional part of the frequency to tune to } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BUS_REQUEST //! @{ -#define CMD_BUS_REQUEST 0x040E +#define CMD_BUS_REQUEST 0x040E //! Request System Bus to be Availbale struct __RFC_STRUCT rfc_CMD_BUS_REQUEST_s { - uint16_t commandNo; //!< The command ID number 0x040E - uint8_t bSysBusNeeded; //!< \brief 0: System bus may sleep
- //!< 1: System bus access needed + uint16_t commandNo; //!< The command ID number 0x040E + uint8_t bSysBusNeeded; //!< \brief 0: System bus may sleep
+ //!< 1: System bus access needed } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SET_CMD_START_IRQ //! @{ -#define CMD_SET_CMD_START_IRQ 0x0411 +#define CMD_SET_CMD_START_IRQ 0x0411 //! Enable or disable generation of IRQ when a radio operation command starts struct __RFC_STRUCT rfc_CMD_SET_CMD_START_IRQ_s { - uint16_t commandNo; //!< The command ID number 0x0411 - uint8_t bEna; //!< 1 to enable interrupt generation; 0 to disable it + uint16_t commandNo; //!< The command ID number 0x0411 + uint8_t bEna; //!< 1 to enable interrupt generation; 0 to disable it } __RFC_STRUCT_ATTR; //! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_data_entry.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_data_entry.h index f555437..ab2338e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_data_entry.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_data_entry.h @@ -1,56 +1,56 @@ /****************************************************************************** -* Filename: rf_data_entry.h -* Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018) -* Revision: 18170 -* -* Description: Definition of API for data exchange -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_data_entry.h + * Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018) + * Revision: 18170 + * + * Description: Definition of API for data exchange + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __DATA_ENTRY_H #define __DATA_ENTRY_H #ifndef __RFC_STRUCT - #define __RFC_STRUCT +#define __RFC_STRUCT #endif #ifndef __RFC_STRUCT_ATTR - #if defined(__GNUC__) - #define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) - #elif defined(__TI_ARM__) - #define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) - #else - #define __RFC_STRUCT_ATTR - #endif +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__((aligned(4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__((__packed__, aligned(4))) +#else +#define __RFC_STRUCT_ATTR +#endif #endif //! \addtogroup rfc @@ -59,8 +59,8 @@ //! \addtogroup data_entry //! @{ -#include #include "rf_mailbox.h" +#include typedef struct __RFC_STRUCT rfc_dataEntry_s rfc_dataEntry_t; typedef struct __RFC_STRUCT rfc_dataEntryGeneral_s rfc_dataEntryGeneral_t; @@ -72,25 +72,25 @@ typedef struct __RFC_STRUCT rfc_dataEntryPartial_s rfc_dataEntryPartial_t; //! @{ struct __RFC_STRUCT rfc_dataEntry_s { - uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry - uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to - struct - { - uint8_t type: 2; //!< \brief Type of data entry structure
- //!< 0: General data entry
- //!< 1: Multi-element Rx entry
- //!< 2: Pointer entry
- //!< 3: Partial read Rx entry - uint8_t lenSz: 2; //!< \brief Size of length word in start of each Rx entry element
- //!< 0: No length indicator
- //!< 1: One byte length indicator
- //!< 2: Two bytes length indicator
- //!< 3: Reserved - uint8_t irqIntv: 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated - //!< by the radio CPU (0: 16 bytes) - } config; - uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
- //!< For other entries: Number of bytes following this length field + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct + { + uint8_t type : 2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz : 2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv : 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field } __RFC_STRUCT_ATTR; //! @} @@ -101,26 +101,26 @@ struct __RFC_STRUCT rfc_dataEntry_s struct __RFC_STRUCT rfc_dataEntryGeneral_s { - uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry - uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to - struct - { - uint8_t type: 2; //!< \brief Type of data entry structure
- //!< 0: General data entry
- //!< 1: Multi-element Rx entry
- //!< 2: Pointer entry
- //!< 3: Partial read Rx entry - uint8_t lenSz: 2; //!< \brief Size of length word in start of each Rx entry element
- //!< 0: No length indicator
- //!< 1: One byte length indicator
- //!< 2: Two bytes length indicator
- //!< 3: Reserved - uint8_t irqIntv: 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated - //!< by the radio CPU (0: 16 bytes) - } config; - uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
- //!< For other entries: Number of bytes following this length field - uint8_t data; //!< First byte of the data array to be received or transmitted + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct + { + uint8_t type : 2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz : 2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv : 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + uint8_t data; //!< First byte of the data array to be received or transmitted } __RFC_STRUCT_ATTR; //! @} @@ -131,28 +131,28 @@ struct __RFC_STRUCT rfc_dataEntryGeneral_s struct __RFC_STRUCT rfc_dataEntryMulti_s { - uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry - uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to - struct - { - uint8_t type: 2; //!< \brief Type of data entry structure
- //!< 0: General data entry
- //!< 1: Multi-element Rx entry
- //!< 2: Pointer entry
- //!< 3: Partial read Rx entry - uint8_t lenSz: 2; //!< \brief Size of length word in start of each Rx entry element
- //!< 0: No length indicator
- //!< 1: One byte length indicator
- //!< 2: Two bytes length indicator
- //!< 3: Reserved - uint8_t irqIntv: 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated - //!< by the radio CPU (0: 16 bytes) - } config; - uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
- //!< For other entries: Number of bytes following this length field - uint16_t numElements; //!< Number of entry elements committed in the entry - uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU - uint8_t rxData; //!< First byte of the data array of received data entry elements + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct + { + uint8_t type : 2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz : 2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv : 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + uint16_t numElements; //!< Number of entry elements committed in the entry + uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU + uint8_t rxData; //!< First byte of the data array of received data entry elements } __RFC_STRUCT_ATTR; //! @} @@ -163,26 +163,26 @@ struct __RFC_STRUCT rfc_dataEntryMulti_s struct __RFC_STRUCT rfc_dataEntryPointer_s { - uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry - uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to - struct - { - uint8_t type: 2; //!< \brief Type of data entry structure
- //!< 0: General data entry
- //!< 1: Multi-element Rx entry
- //!< 2: Pointer entry
- //!< 3: Partial read Rx entry - uint8_t lenSz: 2; //!< \brief Size of length word in start of each Rx entry element
- //!< 0: No length indicator
- //!< 1: One byte length indicator
- //!< 2: Two bytes length indicator
- //!< 3: Reserved - uint8_t irqIntv: 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated - //!< by the radio CPU (0: 16 bytes) - } config; - uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
- //!< For other entries: Number of bytes following this length field - uint8_t* pData; //!< Pointer to data buffer of data to be received ro transmitted + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct + { + uint8_t type : 2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz : 2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv : 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + uint8_t* pData; //!< Pointer to data buffer of data to be received ro transmitted } __RFC_STRUCT_ATTR; //! @} @@ -193,34 +193,34 @@ struct __RFC_STRUCT rfc_dataEntryPointer_s struct __RFC_STRUCT rfc_dataEntryPartial_s { - uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry - uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to - struct - { - uint8_t type: 2; //!< \brief Type of data entry structure
- //!< 0: General data entry
- //!< 1: Multi-element Rx entry
- //!< 2: Pointer entry
- //!< 3: Partial read Rx entry - uint8_t lenSz: 2; //!< \brief Size of length word in start of each Rx entry element
- //!< 0: No length indicator
- //!< 1: One byte length indicator
- //!< 2: Two bytes length indicator
- //!< 3: Reserved - uint8_t irqIntv: 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated - //!< by the radio CPU (0: 16 bytes) - } config; - uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
- //!< For other entries: Number of bytes following this length field - struct - { - uint16_t numElements: 13; //!< Number of entry elements committed in the entry - uint16_t bEntryOpen: 1; //!< 1 if the entry contains an element that is still open for appending data - uint16_t bFirstCont: 1; //!< 1 if the first element is a continuation of the last packet from the previous entry - uint16_t bLastCont: 1; //!< 1 if the packet in the last element continues in the next entry - } pktStatus; - uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU - uint8_t rxData; //!< First byte of the data array of received data entry elements + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct + { + uint8_t type : 2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz : 2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv : 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + struct + { + uint16_t numElements : 13; //!< Number of entry elements committed in the entry + uint16_t bEntryOpen : 1; //!< 1 if the entry contains an element that is still open for appending data + uint16_t bFirstCont : 1; //!< 1 if the first element is a continuation of the last packet from the previous entry + uint16_t bLastCont : 1; //!< 1 if the packet in the last element continues in the next entry + } pktStatus; + uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU + uint8_t rxData; //!< First byte of the data array of received data entry elements } __RFC_STRUCT_ATTR; //! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_cmd.h index 066e0af..de98f89 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_cmd.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_cmd.h @@ -1,56 +1,56 @@ /****************************************************************************** -* Filename: rf_hs_cmd.h -* Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018) -* Revision: 18170 -* -* Description: CC13x2/CC26x2 API for high-speed mode commands -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_hs_cmd.h + * Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018) + * Revision: 18170 + * + * Description: CC13x2/CC26x2 API for high-speed mode commands + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HS_CMD_H #define __HS_CMD_H #ifndef __RFC_STRUCT - #define __RFC_STRUCT +#define __RFC_STRUCT #endif #ifndef __RFC_STRUCT_ATTR - #if defined(__GNUC__) - #define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) - #elif defined(__TI_ARM__) - #define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) - #else - #define __RFC_STRUCT_ATTR - #endif +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__((aligned(4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__((__packed__, aligned(4))) +#else +#define __RFC_STRUCT_ATTR +#endif #endif //! \addtogroup rfc @@ -59,9 +59,9 @@ //! \addtogroup hs_cmd //! @{ -#include -#include "rf_mailbox.h" #include "rf_common_cmd.h" +#include "rf_mailbox.h" +#include typedef struct __RFC_STRUCT rfc_CMD_HS_TX_s rfc_CMD_HS_TX_t; typedef struct __RFC_STRUCT rfc_CMD_HS_RX_s rfc_CMD_HS_RX_t; @@ -70,114 +70,114 @@ typedef struct __RFC_STRUCT rfc_hsRxStatus_s rfc_hsRxStatus_t; //! \addtogroup CMD_HS_TX //! @{ -#define CMD_HS_TX 0x3841 +#define CMD_HS_TX 0x3841 //! High-Speed Transmit Command struct __RFC_STRUCT rfc_CMD_HS_TX_s { - uint16_t commandNo; //!< The command ID number 0x3841 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bUseCrc: 1; //!< \brief 0: Do not append CRC
- //!< 1: Append CRC - uint8_t bVarLen: 1; //!< \brief 0: Fixed length
- //!< 1: Transmit length as first half-word - uint8_t bCheckQAtEnd: 1; //!< \brief 0: Always end with HS_DONE_OK when packet has been transmitted
- //!< 1: Check if Tx queue is empty when packet has been transmitted - } pktConf; - uint8_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to Tx queue + uint16_t commandNo; //!< The command ID number 0x3841 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bUseCrc : 1; //!< \brief 0: Do not append CRC
+ //!< 1: Append CRC + uint8_t bVarLen : 1; //!< \brief 0: Fixed length
+ //!< 1: Transmit length as first half-word + uint8_t bCheckQAtEnd : 1; //!< \brief 0: Always end with HS_DONE_OK when packet has been transmitted
+ //!< 1: Check if Tx queue is empty when packet has been transmitted + } pktConf; + uint8_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to Tx queue } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_HS_RX //! @{ -#define CMD_HS_RX 0x3842 +#define CMD_HS_RX 0x3842 //! High-Speed Receive Command struct __RFC_STRUCT rfc_CMD_HS_RX_s { - uint16_t commandNo; //!< The command ID number 0x3842 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bUseCrc: 1; //!< \brief 0: Do not receive or check CRC
- //!< 1: Receive and check CRC - uint8_t bVarLen: 1; //!< \brief 0: Fixed length
- //!< 1: Receive length as first byte - uint8_t bRepeatOk: 1; //!< \brief 0: End operation after receiving a packet correctly
- //!< 1: Go back to sync search after receiving a packet correctly - uint8_t bRepeatNok: 1; //!< \brief 0: End operation after receiving a packet with CRC error
- //!< 1: Go back to sync search after receiving a packet with CRC error - uint8_t addressMode: 2; //!< \brief 0: No address check
- //!< 1: Accept address0 and address1
- //!< 2: Accept address0, address1, and 0x0000
- //!< 3: Accept address0, address1, 0x0000, and 0xFFFF - } pktConf; - struct - { - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bIncludeLen: 1; //!< If 1, include the received length field in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise 3scard it - uint8_t bAppendStatus: 1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConf; - uint16_t maxPktLen; //!< Packet length for fixed length; maximum packet length for variable length - uint16_t address0; //!< Address - uint16_t address1; //!< Address (set equal to address0 to accept only one address) - uint8_t __dummy0; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - ratmr_t endTime; //!< Time used together with endTrigger for ending the operation - dataQueue_t* pQueue; //!< Pointer to receive queue - rfc_hsRxOutput_t* pOutput; //!< Pointer to output structure + uint16_t commandNo; //!< The command ID number 0x3842 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bUseCrc : 1; //!< \brief 0: Do not receive or check CRC
+ //!< 1: Receive and check CRC + uint8_t bVarLen : 1; //!< \brief 0: Fixed length
+ //!< 1: Receive length as first byte + uint8_t bRepeatOk : 1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok : 1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t addressMode : 2; //!< \brief 0: No address check
+ //!< 1: Accept address0 and address1
+ //!< 2: Accept address0, address1, and 0x0000
+ //!< 3: Accept address0, address1, 0x0000, and 0xFFFF + } pktConf; + struct + { + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bIncludeLen : 1; //!< If 1, include the received length field in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise 3scard it + uint8_t bAppendStatus : 1; //!< If 1, append a status word to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConf; + uint16_t maxPktLen; //!< Packet length for fixed length; maximum packet length for variable length + uint16_t address0; //!< Address + uint16_t address1; //!< Address (set equal to address0 to accept only one address) + uint8_t __dummy0; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + dataQueue_t* pQueue; //!< Pointer to receive queue + rfc_hsRxOutput_t* pOutput; //!< Pointer to output structure } __RFC_STRUCT_ATTR; //! @} @@ -188,12 +188,12 @@ struct __RFC_STRUCT rfc_CMD_HS_RX_s struct __RFC_STRUCT rfc_hsRxOutput_s { - uint16_t nRxOk; //!< Number of packets that have been received with CRC OK - uint16_t nRxNok; //!< Number of packets that have been received with CRC error - uint16_t nRxAborted; //!< Number of packets not received due to illegal length or address mismatch - uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space - int8_t lastRssi; //!< RSSI of last received packet - ratmr_t timeStamp; //!< Time stamp of last received packet + uint16_t nRxOk; //!< Number of packets that have been received with CRC OK + uint16_t nRxNok; //!< Number of packets that have been received with CRC error + uint16_t nRxAborted; //!< Number of packets not received due to illegal length or address mismatch + uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< RSSI of last received packet + ratmr_t timeStamp; //!< Time stamp of last received packet } __RFC_STRUCT_ATTR; //! @} @@ -204,16 +204,16 @@ struct __RFC_STRUCT rfc_hsRxOutput_s struct __RFC_STRUCT rfc_hsRxStatus_s { - struct - { - uint16_t rssi: 8; //!< RSSI of the received packet in dBm (signed) - uint16_t bCrcErr: 1; //!< \brief 0: Packet received OK
- //!< 1: Packet received with CRC error - uint16_t addressInd: 2; //!< \brief 0: Received address0 (or no address check)
- //!< 1: Received address1
- //!< 2: Received address 0x0000
- //!< 3: Received address 0xFFFF - } status; + struct + { + uint16_t rssi : 8; //!< RSSI of the received packet in dBm (signed) + uint16_t bCrcErr : 1; //!< \brief 0: Packet received OK
+ //!< 1: Packet received with CRC error + uint16_t addressInd : 2; //!< \brief 0: Received address0 (or no address check)
+ //!< 1: Received address1
+ //!< 2: Received address 0x0000
+ //!< 3: Received address 0xFFFF + } status; } __RFC_STRUCT_ATTR; //! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_mailbox.h index 9031f8e..cce9165 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_mailbox.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_mailbox.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_hs_mailbox.h -* Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018) -* Revision: 18171 -* -* Description: Definitions for high-speed mode radio interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_hs_mailbox.h + * Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018) + * Revision: 18171 + * + * Description: Definitions for high-speed mode radio interface + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _HS_MAILBOX_H #define _HS_MAILBOX_H @@ -43,22 +43,22 @@ ///@{ /// \name Operation finished normally ///@{ -#define HS_DONE_OK 0x3440 ///< Operation ended normally -#define HS_DONE_RXTIMEOUT 0x3441 ///< Operation stopped after end trigger while waiting for sync -#define HS_DONE_RXERR 0x3442 ///< Operation ended after CRC error -#define HS_DONE_TXBUF 0x3443 ///< Tx queue was empty at start of operation -#define HS_DONE_ENDED 0x3444 ///< Operation stopped after end trigger during reception -#define HS_DONE_STOPPED 0x3445 ///< Operation stopped after stop command -#define HS_DONE_ABORT 0x3446 ///< Operation aborted by abort command +#define HS_DONE_OK 0x3440 ///< Operation ended normally +#define HS_DONE_RXTIMEOUT 0x3441 ///< Operation stopped after end trigger while waiting for sync +#define HS_DONE_RXERR 0x3442 ///< Operation ended after CRC error +#define HS_DONE_TXBUF 0x3443 ///< Tx queue was empty at start of operation +#define HS_DONE_ENDED 0x3444 ///< Operation stopped after end trigger during reception +#define HS_DONE_STOPPED 0x3445 ///< Operation stopped after stop command +#define HS_DONE_ABORT 0x3446 ///< Operation aborted by abort command ///@} /// \name Operation finished with error ///@{ -#define HS_ERROR_PAR 0x3840 ///< Illegal parameter -#define HS_ERROR_RXBUF 0x3841 ///< No available Rx buffer at the start of a packet -#define HS_ERROR_NO_SETUP 0x3842 ///< Radio was not set up in a compatible mode -#define HS_ERROR_NO_FS 0x3843 ///< Synth was not programmed when running Rx or Tx -#define HS_ERROR_RXOVF 0x3844 ///< Rx overflow observed during operation -#define HS_ERROR_TXUNF 0x3845 ///< Tx underflow observed during operation +#define HS_ERROR_PAR 0x3840 ///< Illegal parameter +#define HS_ERROR_RXBUF 0x3841 ///< No available Rx buffer at the start of a packet +#define HS_ERROR_NO_SETUP 0x3842 ///< Radio was not set up in a compatible mode +#define HS_ERROR_NO_FS 0x3843 ///< Synth was not programmed when running Rx or Tx +#define HS_ERROR_RXOVF 0x3844 ///< Rx overflow observed during operation +#define HS_ERROR_TXUNF 0x3845 ///< Tx underflow observed during operation ///@} ///@} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_cmd.h index 6357eff..e0c8886 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_cmd.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_cmd.h @@ -1,56 +1,56 @@ /****************************************************************************** -* Filename: rf_ieee_cmd.h -* Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018) -* Revision: 18170 -* -* Description: CC13x2/CC26x2 API for IEEE 802.15.4 commands -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_ieee_cmd.h + * Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018) + * Revision: 18170 + * + * Description: CC13x2/CC26x2 API for IEEE 802.15.4 commands + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __IEEE_CMD_H #define __IEEE_CMD_H #ifndef __RFC_STRUCT - #define __RFC_STRUCT +#define __RFC_STRUCT #endif #ifndef __RFC_STRUCT_ATTR - #if defined(__GNUC__) - #define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) - #elif defined(__TI_ARM__) - #define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) - #else - #define __RFC_STRUCT_ATTR - #endif +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__((aligned(4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__((__packed__, aligned(4))) +#else +#define __RFC_STRUCT_ATTR +#endif #endif //! \addtogroup rfc @@ -59,9 +59,9 @@ //! \addtogroup ieee_cmd //! @{ -#include -#include "rf_mailbox.h" #include "rf_common_cmd.h" +#include "rf_mailbox.h" +#include typedef struct __RFC_STRUCT rfc_CMD_IEEE_RX_s rfc_CMD_IEEE_RX_t; typedef struct __RFC_STRUCT rfc_CMD_IEEE_ED_SCAN_s rfc_CMD_IEEE_ED_SCAN_t; @@ -81,537 +81,537 @@ typedef struct __RFC_STRUCT rfc_ieeeRxCorrCrc_s rfc_ieeeRxCorrCrc_t; //! \addtogroup CMD_IEEE_RX //! @{ -#define CMD_IEEE_RX 0x2801 +#define CMD_IEEE_RX 0x2801 //! IEEE 802.15.4 Receive Command struct __RFC_STRUCT rfc_CMD_IEEE_RX_s { - uint16_t commandNo; //!< The command ID number 0x2801 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to tune to in the start of the operation
- //!< 0: Use existing channel
- //!< 11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 × (channel - 11)) MHz
- //!< 60--207: Frequency is (2300 + channel) MHz
- //!< Others: Reserved - struct - { - uint8_t bAutoFlushCrc: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushIgn: 1; //!< If 1, automatically remove packets that can be ignored according to frame filtering from Rx queue - uint8_t bIncludePhyHdr: 1; //!< If 1, include the received PHY header field in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendCorrCrc: 1; //!< If 1, append a correlation value and CRC result byte to the packet in the Rx queue - uint8_t bAppendSrcInd: 1; //!< If 1, append an index from the source matching algorithm - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; - dataQueue_t* pRxQ; //!< Pointer to receive queue - rfc_ieeeRxOutput_t* pOutput; //!< Pointer to output structure (NULL: Do not store results) - struct - { - uint16_t frameFiltEn: 1; //!< \brief 0: Disable frame filtering
- //!< 1: Enable frame filtering - uint16_t frameFiltStop: 1; //!< \brief 0: Receive all packets to the end
- //!< 1: Stop receiving frame once frame filtering has caused the frame to be rejected. - uint16_t autoAckEn: 1; //!< \brief 0: Disable auto ACK
- //!< 1: Enable auto ACK. - uint16_t slottedAckEn: 1; //!< \brief 0: Non-slotted ACK
- //!< 1: Slotted ACK. - uint16_t autoPendEn: 1; //!< \brief 0: Auto-pend disabled
- //!< 1: Auto-pend enabled - uint16_t defaultPend: 1; //!< The value of the pending data bit in auto ACK packets that are not subject to auto-pend - uint16_t bPendDataReqOnly: 1; //!< \brief 0: Use auto-pend for any packet
- //!< 1: Use auto-pend for data request packets only - uint16_t bPanCoord: 1; //!< \brief 0: Device is not PAN coordinator
- //!< 1: Device is PAN coordinator - uint16_t maxFrameVersion: 2; //!< Reject frames where the frame version field in the FCF is greater than this value - uint16_t fcfReservedMask: 3; //!< Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero - uint16_t modifyFtFilter: 2; //!< \brief Treatment of MSB of frame type field before frame-type filtering:
- //!< 0: No modification
- //!< 1: Invert MSB
- //!< 2: Set MSB to 0
- //!< 3: Set MSB to 1 - uint16_t bStrictLenFilter: 1; //!< \brief 0: Accept acknowledgement frames of any length >= 5
- //!< 1: Accept only acknowledgement frames of length 5 - } frameFiltOpt; //!< Frame filtering options - struct - { - uint8_t bAcceptFt0Beacon: 1; //!< \brief Treatment of frames with frame type 000 (beacon):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt1Data: 1; //!< \brief Treatment of frames with frame type 001 (data):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt2Ack: 1; //!< \brief Treatment of frames with frame type 010 (ACK):
- //!< 0: Reject, unless running ACK receive command
- //!< 1: Always accept - uint8_t bAcceptFt3MacCmd: 1; //!< \brief Treatment of frames with frame type 011 (MAC command):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt4Reserved: 1; //!< \brief Treatment of frames with frame type 100 (reserved):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt5Reserved: 1; //!< \brief Treatment of frames with frame type 101 (reserved):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt6Reserved: 1; //!< \brief Treatment of frames with frame type 110 (reserved):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt7Reserved: 1; //!< \brief Treatment of frames with frame type 111 (reserved):
- //!< 0: Reject
- //!< 1: Accept - } frameTypes; //!< Frame types to receive in frame filtering - struct - { - uint8_t ccaEnEnergy: 1; //!< Enable energy scan as CCA source - uint8_t ccaEnCorr: 1; //!< Enable correlator based carrier sense as CCA source - uint8_t ccaEnSync: 1; //!< Enable sync found based carrier sense as CCA source - uint8_t ccaCorrOp: 1; //!< \brief Operator to use between energy based and correlator based CCA
- //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
- //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy - uint8_t ccaSyncOp: 1; //!< \brief Operator to use between sync found based CCA and the others
- //!< 0: Always report busy channel if ccaSync is busy
- //!< 1: Always report idle channel if ccaSync is idle - uint8_t ccaCorrThr: 2; //!< Threshold for number of correlation peaks in correlator based carrier sense - } ccaOpt; //!< CCA options - int8_t ccaRssiThr; //!< RSSI threshold for CCA - uint8_t __dummy0; - uint8_t numExtEntries; //!< Number of extended address entries - uint8_t numShortEntries; //!< Number of short address entries - uint32_t* pExtEntryList; //!< Pointer to list of extended address entries - uint32_t* pShortEntryList; //!< Pointer to list of short address entries - uint64_t localExtAddr; //!< The extended address of the local device - uint16_t localShortAddr; //!< The short address of the local device - uint16_t localPanID; //!< The PAN ID of the local device - uint16_t __dummy1; - uint8_t __dummy2; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the Rx operation - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the Rx - //!< operation + uint16_t commandNo; //!< The command ID number 0x2801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to tune to in the start of the operation
+ //!< 0: Use existing channel
+ //!< 11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 × (channel - 11)) MHz
+ //!< 60--207: Frequency is (2300 + channel) MHz
+ //!< Others: Reserved + struct + { + uint8_t bAutoFlushCrc : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushIgn : 1; //!< If 1, automatically remove packets that can be ignored according to frame filtering from Rx queue + uint8_t bIncludePhyHdr : 1; //!< If 1, include the received PHY header field in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendCorrCrc : 1; //!< If 1, append a correlation value and CRC result byte to the packet in the Rx queue + uint8_t bAppendSrcInd : 1; //!< If 1, append an index from the source matching algorithm + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; + dataQueue_t* pRxQ; //!< Pointer to receive queue + rfc_ieeeRxOutput_t* pOutput; //!< Pointer to output structure (NULL: Do not store results) + struct + { + uint16_t frameFiltEn : 1; //!< \brief 0: Disable frame filtering
+ //!< 1: Enable frame filtering + uint16_t frameFiltStop : 1; //!< \brief 0: Receive all packets to the end
+ //!< 1: Stop receiving frame once frame filtering has caused the frame to be rejected. + uint16_t autoAckEn : 1; //!< \brief 0: Disable auto ACK
+ //!< 1: Enable auto ACK. + uint16_t slottedAckEn : 1; //!< \brief 0: Non-slotted ACK
+ //!< 1: Slotted ACK. + uint16_t autoPendEn : 1; //!< \brief 0: Auto-pend disabled
+ //!< 1: Auto-pend enabled + uint16_t defaultPend : 1; //!< The value of the pending data bit in auto ACK packets that are not subject to auto-pend + uint16_t bPendDataReqOnly : 1; //!< \brief 0: Use auto-pend for any packet
+ //!< 1: Use auto-pend for data request packets only + uint16_t bPanCoord : 1; //!< \brief 0: Device is not PAN coordinator
+ //!< 1: Device is PAN coordinator + uint16_t maxFrameVersion : 2; //!< Reject frames where the frame version field in the FCF is greater than this value + uint16_t fcfReservedMask : 3; //!< Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero + uint16_t modifyFtFilter : 2; //!< \brief Treatment of MSB of frame type field before frame-type filtering:
+ //!< 0: No modification
+ //!< 1: Invert MSB
+ //!< 2: Set MSB to 0
+ //!< 3: Set MSB to 1 + uint16_t bStrictLenFilter : 1; //!< \brief 0: Accept acknowledgement frames of any length >= 5
+ //!< 1: Accept only acknowledgement frames of length 5 + } frameFiltOpt; //!< Frame filtering options + struct + { + uint8_t bAcceptFt0Beacon : 1; //!< \brief Treatment of frames with frame type 000 (beacon):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt1Data : 1; //!< \brief Treatment of frames with frame type 001 (data):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt2Ack : 1; //!< \brief Treatment of frames with frame type 010 (ACK):
+ //!< 0: Reject, unless running ACK receive command
+ //!< 1: Always accept + uint8_t bAcceptFt3MacCmd : 1; //!< \brief Treatment of frames with frame type 011 (MAC command):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt4Reserved : 1; //!< \brief Treatment of frames with frame type 100 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt5Reserved : 1; //!< \brief Treatment of frames with frame type 101 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt6Reserved : 1; //!< \brief Treatment of frames with frame type 110 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt7Reserved : 1; //!< \brief Treatment of frames with frame type 111 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + } frameTypes; //!< Frame types to receive in frame filtering + struct + { + uint8_t ccaEnEnergy : 1; //!< Enable energy scan as CCA source + uint8_t ccaEnCorr : 1; //!< Enable correlator based carrier sense as CCA source + uint8_t ccaEnSync : 1; //!< Enable sync found based carrier sense as CCA source + uint8_t ccaCorrOp : 1; //!< \brief Operator to use between energy based and correlator based CCA
+ //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
+ //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy + uint8_t ccaSyncOp : 1; //!< \brief Operator to use between sync found based CCA and the others
+ //!< 0: Always report busy channel if ccaSync is busy
+ //!< 1: Always report idle channel if ccaSync is idle + uint8_t ccaCorrThr : 2; //!< Threshold for number of correlation peaks in correlator based carrier sense + } ccaOpt; //!< CCA options + int8_t ccaRssiThr; //!< RSSI threshold for CCA + uint8_t __dummy0; + uint8_t numExtEntries; //!< Number of extended address entries + uint8_t numShortEntries; //!< Number of short address entries + uint32_t* pExtEntryList; //!< Pointer to list of extended address entries + uint32_t* pShortEntryList; //!< Pointer to list of short address entries + uint64_t localExtAddr; //!< The extended address of the local device + uint16_t localShortAddr; //!< The short address of the local device + uint16_t localPanID; //!< The PAN ID of the local device + uint16_t __dummy1; + uint8_t __dummy2; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Rx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the Rx + //!< operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_ED_SCAN //! @{ -#define CMD_IEEE_ED_SCAN 0x2802 +#define CMD_IEEE_ED_SCAN 0x2802 //! IEEE 802.15.4 Energy Detect Scan Command struct __RFC_STRUCT rfc_CMD_IEEE_ED_SCAN_s { - uint16_t commandNo; //!< The command ID number 0x2802 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to tune to in the start of the operation
- //!< 0: Use existing channel
- //!< 11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 × (channel - 11)) MHz
- //!< 60--207: Frequency is (2300 + channel) MHz
- //!< Others: Reserved - struct - { - uint8_t ccaEnEnergy: 1; //!< Enable energy scan as CCA source - uint8_t ccaEnCorr: 1; //!< Enable correlator based carrier sense as CCA source - uint8_t ccaEnSync: 1; //!< Enable sync found based carrier sense as CCA source - uint8_t ccaCorrOp: 1; //!< \brief Operator to use between energy based and correlator based CCA
- //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
- //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy - uint8_t ccaSyncOp: 1; //!< \brief Operator to use between sync found based CCA and the others
- //!< 0: Always report busy channel if ccaSync is busy
- //!< 1: Always report idle channel if ccaSync is idle - uint8_t ccaCorrThr: 2; //!< Threshold for number of correlation peaks in correlator based carrier sense - } ccaOpt; //!< CCA options - int8_t ccaRssiThr; //!< RSSI threshold for CCA - uint8_t __dummy0; - int8_t maxRssi; //!< The maximum RSSI recorded during the ED scan - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the Rx operation - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the Rx - //!< operation + uint16_t commandNo; //!< The command ID number 0x2802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to tune to in the start of the operation
+ //!< 0: Use existing channel
+ //!< 11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 × (channel - 11)) MHz
+ //!< 60--207: Frequency is (2300 + channel) MHz
+ //!< Others: Reserved + struct + { + uint8_t ccaEnEnergy : 1; //!< Enable energy scan as CCA source + uint8_t ccaEnCorr : 1; //!< Enable correlator based carrier sense as CCA source + uint8_t ccaEnSync : 1; //!< Enable sync found based carrier sense as CCA source + uint8_t ccaCorrOp : 1; //!< \brief Operator to use between energy based and correlator based CCA
+ //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
+ //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy + uint8_t ccaSyncOp : 1; //!< \brief Operator to use between sync found based CCA and the others
+ //!< 0: Always report busy channel if ccaSync is busy
+ //!< 1: Always report idle channel if ccaSync is idle + uint8_t ccaCorrThr : 2; //!< Threshold for number of correlation peaks in correlator based carrier sense + } ccaOpt; //!< CCA options + int8_t ccaRssiThr; //!< RSSI threshold for CCA + uint8_t __dummy0; + int8_t maxRssi; //!< The maximum RSSI recorded during the ED scan + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Rx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the Rx + //!< operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_TX //! @{ -#define CMD_IEEE_TX 0x2C01 +#define CMD_IEEE_TX 0x2C01 //! IEEE 802.15.4 Transmit Command struct __RFC_STRUCT rfc_CMD_IEEE_TX_s { - uint16_t commandNo; //!< The command ID number 0x2C01 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bIncludePhyHdr: 1; //!< \brief 0: Find PHY header automatically
- //!< 1: Insert PHY header from the buffer - uint8_t bIncludeCrc: 1; //!< \brief 0: Append automatically calculated CRC
- //!< 1: Insert FCS (CRC) from the buffer - uint8_t : 1; - uint8_t payloadLenMsb: 5; //!< \brief Most significant bits of payload length. Should only be non-zero to create long - //!< non-standard packets for test purposes - } txOpt; - uint8_t payloadLen; //!< Number of bytes in the payload - uint8_t* pPayload; //!< Pointer to payload buffer of size payloadLen - ratmr_t timeStamp; //!< Time stamp of transmitted frame + uint16_t commandNo; //!< The command ID number 0x2C01 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bIncludePhyHdr : 1; //!< \brief 0: Find PHY header automatically
+ //!< 1: Insert PHY header from the buffer + uint8_t bIncludeCrc : 1; //!< \brief 0: Append automatically calculated CRC
+ //!< 1: Insert FCS (CRC) from the buffer + uint8_t : 1; + uint8_t payloadLenMsb : 5; //!< \brief Most significant bits of payload length. Should only be non-zero to create long + //!< non-standard packets for test purposes + } txOpt; + uint8_t payloadLen; //!< Number of bytes in the payload + uint8_t* pPayload; //!< Pointer to payload buffer of size payloadLen + ratmr_t timeStamp; //!< Time stamp of transmitted frame } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_CSMA //! @{ -#define CMD_IEEE_CSMA 0x2C02 +#define CMD_IEEE_CSMA 0x2C02 //! IEEE 802.15.4 CSMA-CA Command struct __RFC_STRUCT rfc_CMD_IEEE_CSMA_s { - uint16_t commandNo; //!< The command ID number 0x2C02 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t randomState; //!< The state of the pseudo-random generator - uint8_t macMaxBE; //!< The IEEE 802.15.4 MAC parameter macMaxBE - uint8_t macMaxCSMABackoffs; //!< The IEEE 802.15.4 MAC parameter macMaxCSMABackoffs - struct - { - uint8_t initCW: 5; //!< The initialization value for the CW parameter - uint8_t bSlotted: 1; //!< \brief 0: non-slotted CSMA
- //!< 1: slotted CSMA - uint8_t rxOffMode: 2; //!< \brief 0: RX stays on during CSMA backoffs
- //!< 1: The CSMA-CA algorithm will suspend the receiver if no frame is being received
- //!< 2: The CSMA-CA algorithm will suspend the receiver if no frame is being received, - //!< or after finishing it (including auto ACK) otherwise
- //!< 3: The CSMA-CA algorithm will suspend the receiver immediately during back-offs - } csmaConfig; - uint8_t NB; //!< The NB parameter from the IEEE 802.15.4 CSMA-CA algorithm - uint8_t BE; //!< The BE parameter from the IEEE 802.15.4 CSMA-CA algorithm - uint8_t remainingPeriods; //!< The number of remaining periods from a paused backoff countdown - int8_t lastRssi; //!< RSSI measured at the last CCA operation - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the CSMA-CA operation - ratmr_t lastTimeStamp; //!< Time of the last CCA operation - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< CSMA-CA operation + uint16_t commandNo; //!< The command ID number 0x2C02 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t randomState; //!< The state of the pseudo-random generator + uint8_t macMaxBE; //!< The IEEE 802.15.4 MAC parameter macMaxBE + uint8_t macMaxCSMABackoffs; //!< The IEEE 802.15.4 MAC parameter macMaxCSMABackoffs + struct + { + uint8_t initCW : 5; //!< The initialization value for the CW parameter + uint8_t bSlotted : 1; //!< \brief 0: non-slotted CSMA
+ //!< 1: slotted CSMA + uint8_t rxOffMode : 2; //!< \brief 0: RX stays on during CSMA backoffs
+ //!< 1: The CSMA-CA algorithm will suspend the receiver if no frame is being received
+ //!< 2: The CSMA-CA algorithm will suspend the receiver if no frame is being received, + //!< or after finishing it (including auto ACK) otherwise
+ //!< 3: The CSMA-CA algorithm will suspend the receiver immediately during back-offs + } csmaConfig; + uint8_t NB; //!< The NB parameter from the IEEE 802.15.4 CSMA-CA algorithm + uint8_t BE; //!< The BE parameter from the IEEE 802.15.4 CSMA-CA algorithm + uint8_t remainingPeriods; //!< The number of remaining periods from a paused backoff countdown + int8_t lastRssi; //!< RSSI measured at the last CCA operation + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the CSMA-CA operation + ratmr_t lastTimeStamp; //!< Time of the last CCA operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< CSMA-CA operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_RX_ACK //! @{ -#define CMD_IEEE_RX_ACK 0x2C03 +#define CMD_IEEE_RX_ACK 0x2C03 //! IEEE 802.15.4 Receive Acknowledgement Command struct __RFC_STRUCT rfc_CMD_IEEE_RX_ACK_s { - uint16_t commandNo; //!< The command ID number 0x2C03 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t seqNo; //!< Sequence number to expect - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to give up acknowledgement reception - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to give up - //!< acknowledgement reception + uint16_t commandNo; //!< The command ID number 0x2C03 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t seqNo; //!< Sequence number to expect + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to give up acknowledgement reception + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to give up + //!< acknowledgement reception } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_ABORT_BG //! @{ -#define CMD_IEEE_ABORT_BG 0x2C04 +#define CMD_IEEE_ABORT_BG 0x2C04 //! IEEE 802.15.4 Abort Background Level Command struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_BG_s { - uint16_t commandNo; //!< The command ID number 0x2C04 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; + uint16_t commandNo; //!< The command ID number 0x2C04 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_MOD_CCA //! @{ -#define CMD_IEEE_MOD_CCA 0x2001 +#define CMD_IEEE_MOD_CCA 0x2001 //! IEEE 802.15.4 Modify CCA Parameter Command struct __RFC_STRUCT rfc_CMD_IEEE_MOD_CCA_s { - uint16_t commandNo; //!< The command ID number 0x2001 - struct - { - uint8_t ccaEnEnergy: 1; //!< Enable energy scan as CCA source - uint8_t ccaEnCorr: 1; //!< Enable correlator based carrier sense as CCA source - uint8_t ccaEnSync: 1; //!< Enable sync found based carrier sense as CCA source - uint8_t ccaCorrOp: 1; //!< \brief Operator to use between energy based and correlator based CCA
- //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
- //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy - uint8_t ccaSyncOp: 1; //!< \brief Operator to use between sync found based CCA and the others
- //!< 0: Always report busy channel if ccaSync is busy
- //!< 1: Always report idle channel if ccaSync is idle - uint8_t ccaCorrThr: 2; //!< Threshold for number of correlation peaks in correlator based carrier sense - } newCcaOpt; //!< New value of ccaOpt for the running background level operation - int8_t newCcaRssiThr; //!< New value of ccaRssiThr for the running background level operation + uint16_t commandNo; //!< The command ID number 0x2001 + struct + { + uint8_t ccaEnEnergy : 1; //!< Enable energy scan as CCA source + uint8_t ccaEnCorr : 1; //!< Enable correlator based carrier sense as CCA source + uint8_t ccaEnSync : 1; //!< Enable sync found based carrier sense as CCA source + uint8_t ccaCorrOp : 1; //!< \brief Operator to use between energy based and correlator based CCA
+ //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
+ //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy + uint8_t ccaSyncOp : 1; //!< \brief Operator to use between sync found based CCA and the others
+ //!< 0: Always report busy channel if ccaSync is busy
+ //!< 1: Always report idle channel if ccaSync is idle + uint8_t ccaCorrThr : 2; //!< Threshold for number of correlation peaks in correlator based carrier sense + } newCcaOpt; //!< New value of ccaOpt for the running background level operation + int8_t newCcaRssiThr; //!< New value of ccaRssiThr for the running background level operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_MOD_FILT //! @{ -#define CMD_IEEE_MOD_FILT 0x2002 +#define CMD_IEEE_MOD_FILT 0x2002 //! IEEE 802.15.4 Modify Frame Filtering Parameter Command struct __RFC_STRUCT rfc_CMD_IEEE_MOD_FILT_s { - uint16_t commandNo; //!< The command ID number 0x2002 - struct - { - uint16_t frameFiltEn: 1; //!< \brief 0: Disable frame filtering
- //!< 1: Enable frame filtering - uint16_t frameFiltStop: 1; //!< \brief 0: Receive all packets to the end
- //!< 1: Stop receiving frame once frame filtering has caused the frame to be rejected. - uint16_t autoAckEn: 1; //!< \brief 0: Disable auto ACK
- //!< 1: Enable auto ACK. - uint16_t slottedAckEn: 1; //!< \brief 0: Non-slotted ACK
- //!< 1: Slotted ACK. - uint16_t autoPendEn: 1; //!< \brief 0: Auto-pend disabled
- //!< 1: Auto-pend enabled - uint16_t defaultPend: 1; //!< The value of the pending data bit in auto ACK packets that are not subject to auto-pend - uint16_t bPendDataReqOnly: 1; //!< \brief 0: Use auto-pend for any packet
- //!< 1: Use auto-pend for data request packets only - uint16_t bPanCoord: 1; //!< \brief 0: Device is not PAN coordinator
- //!< 1: Device is PAN coordinator - uint16_t maxFrameVersion: 2; //!< Reject frames where the frame version field in the FCF is greater than this value - uint16_t fcfReservedMask: 3; //!< Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero - uint16_t modifyFtFilter: 2; //!< \brief Treatment of MSB of frame type field before frame-type filtering:
- //!< 0: No modification
- //!< 1: Invert MSB
- //!< 2: Set MSB to 0
- //!< 3: Set MSB to 1 - uint16_t bStrictLenFilter: 1; //!< \brief 0: Accept acknowledgement frames of any length >= 5
- //!< 1: Accept only acknowledgement frames of length 5 - } newFrameFiltOpt; //!< New value of frameFiltOpt for the running background level operation - struct - { - uint8_t bAcceptFt0Beacon: 1; //!< \brief Treatment of frames with frame type 000 (beacon):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt1Data: 1; //!< \brief Treatment of frames with frame type 001 (data):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt2Ack: 1; //!< \brief Treatment of frames with frame type 010 (ACK):
- //!< 0: Reject, unless running ACK receive command
- //!< 1: Always accept - uint8_t bAcceptFt3MacCmd: 1; //!< \brief Treatment of frames with frame type 011 (MAC command):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt4Reserved: 1; //!< \brief Treatment of frames with frame type 100 (reserved):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt5Reserved: 1; //!< \brief Treatment of frames with frame type 101 (reserved):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt6Reserved: 1; //!< \brief Treatment of frames with frame type 110 (reserved):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt7Reserved: 1; //!< \brief Treatment of frames with frame type 111 (reserved):
- //!< 0: Reject
- //!< 1: Accept - } newFrameTypes; //!< New value of frameTypes for the running background level operation + uint16_t commandNo; //!< The command ID number 0x2002 + struct + { + uint16_t frameFiltEn : 1; //!< \brief 0: Disable frame filtering
+ //!< 1: Enable frame filtering + uint16_t frameFiltStop : 1; //!< \brief 0: Receive all packets to the end
+ //!< 1: Stop receiving frame once frame filtering has caused the frame to be rejected. + uint16_t autoAckEn : 1; //!< \brief 0: Disable auto ACK
+ //!< 1: Enable auto ACK. + uint16_t slottedAckEn : 1; //!< \brief 0: Non-slotted ACK
+ //!< 1: Slotted ACK. + uint16_t autoPendEn : 1; //!< \brief 0: Auto-pend disabled
+ //!< 1: Auto-pend enabled + uint16_t defaultPend : 1; //!< The value of the pending data bit in auto ACK packets that are not subject to auto-pend + uint16_t bPendDataReqOnly : 1; //!< \brief 0: Use auto-pend for any packet
+ //!< 1: Use auto-pend for data request packets only + uint16_t bPanCoord : 1; //!< \brief 0: Device is not PAN coordinator
+ //!< 1: Device is PAN coordinator + uint16_t maxFrameVersion : 2; //!< Reject frames where the frame version field in the FCF is greater than this value + uint16_t fcfReservedMask : 3; //!< Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero + uint16_t modifyFtFilter : 2; //!< \brief Treatment of MSB of frame type field before frame-type filtering:
+ //!< 0: No modification
+ //!< 1: Invert MSB
+ //!< 2: Set MSB to 0
+ //!< 3: Set MSB to 1 + uint16_t bStrictLenFilter : 1; //!< \brief 0: Accept acknowledgement frames of any length >= 5
+ //!< 1: Accept only acknowledgement frames of length 5 + } newFrameFiltOpt; //!< New value of frameFiltOpt for the running background level operation + struct + { + uint8_t bAcceptFt0Beacon : 1; //!< \brief Treatment of frames with frame type 000 (beacon):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt1Data : 1; //!< \brief Treatment of frames with frame type 001 (data):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt2Ack : 1; //!< \brief Treatment of frames with frame type 010 (ACK):
+ //!< 0: Reject, unless running ACK receive command
+ //!< 1: Always accept + uint8_t bAcceptFt3MacCmd : 1; //!< \brief Treatment of frames with frame type 011 (MAC command):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt4Reserved : 1; //!< \brief Treatment of frames with frame type 100 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt5Reserved : 1; //!< \brief Treatment of frames with frame type 101 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt6Reserved : 1; //!< \brief Treatment of frames with frame type 110 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt7Reserved : 1; //!< \brief Treatment of frames with frame type 111 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + } newFrameTypes; //!< New value of frameTypes for the running background level operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_MOD_SRC_MATCH //! @{ -#define CMD_IEEE_MOD_SRC_MATCH 0x2003 +#define CMD_IEEE_MOD_SRC_MATCH 0x2003 //! IEEE 802.15.4 Enable/Disable Source Matching Entry Command struct __RFC_STRUCT rfc_CMD_IEEE_MOD_SRC_MATCH_s { - uint16_t commandNo; //!< The command ID number 0x2003 - struct - { - uint8_t bEnable: 1; //!< \brief 0: Disable entry
- //!< 1: Enable entry - uint8_t srcPend: 1; //!< New value of the pending bit for the entry - uint8_t entryType: 1; //!< \brief 0: Short address
- //!< 1: Extended address - } options; - uint8_t entryNo; //!< Index of entry to enable or disable + uint16_t commandNo; //!< The command ID number 0x2003 + struct + { + uint8_t bEnable : 1; //!< \brief 0: Disable entry
+ //!< 1: Enable entry + uint8_t srcPend : 1; //!< New value of the pending bit for the entry + uint8_t entryType : 1; //!< \brief 0: Short address
+ //!< 1: Extended address + } options; + uint8_t entryNo; //!< Index of entry to enable or disable } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_ABORT_FG //! @{ -#define CMD_IEEE_ABORT_FG 0x2401 +#define CMD_IEEE_ABORT_FG 0x2401 //! IEEE 802.15.4 Abort Foreground Level Command struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_FG_s { - uint16_t commandNo; //!< The command ID number 0x2401 + uint16_t commandNo; //!< The command ID number 0x2401 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_STOP_FG //! @{ -#define CMD_IEEE_STOP_FG 0x2402 +#define CMD_IEEE_STOP_FG 0x2402 //! IEEE 802.15.4 Gracefully Stop Foreground Level Command struct __RFC_STRUCT rfc_CMD_IEEE_STOP_FG_s { - uint16_t commandNo; //!< The command ID number 0x2402 + uint16_t commandNo; //!< The command ID number 0x2402 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_CCA_REQ //! @{ -#define CMD_IEEE_CCA_REQ 0x2403 +#define CMD_IEEE_CCA_REQ 0x2403 //! IEEE 802.15.4 CCA and RSSI Information Request Command struct __RFC_STRUCT rfc_CMD_IEEE_CCA_REQ_s { - uint16_t commandNo; //!< The command ID number 0x2403 - int8_t currentRssi; //!< The RSSI currently observed on the channel - int8_t maxRssi; //!< The maximum RSSI observed on the channel since Rx was started - struct - { - uint8_t ccaState: 2; //!< \brief Value of the current CCA state
- //!< 0: Idle
- //!< 1: Busy
- //!< 2: Invalid - uint8_t ccaEnergy: 2; //!< \brief Value of the current energy detect CCA state
- //!< 0: Idle
- //!< 1: Busy
- //!< 2: Invalid - uint8_t ccaCorr: 2; //!< \brief Value of the current correlator based carrier sense CCA state
- //!< 0: Idle
- //!< 1: Busy
- //!< 2: Invalid - uint8_t ccaSync: 1; //!< \brief Value of the current sync found based carrier sense CCA state
- //!< 0: Idle
- //!< 1: Busy - } ccaInfo; + uint16_t commandNo; //!< The command ID number 0x2403 + int8_t currentRssi; //!< The RSSI currently observed on the channel + int8_t maxRssi; //!< The maximum RSSI observed on the channel since Rx was started + struct + { + uint8_t ccaState : 2; //!< \brief Value of the current CCA state
+ //!< 0: Idle
+ //!< 1: Busy
+ //!< 2: Invalid + uint8_t ccaEnergy : 2; //!< \brief Value of the current energy detect CCA state
+ //!< 0: Idle
+ //!< 1: Busy
+ //!< 2: Invalid + uint8_t ccaCorr : 2; //!< \brief Value of the current correlator based carrier sense CCA state
+ //!< 0: Idle
+ //!< 1: Busy
+ //!< 2: Invalid + uint8_t ccaSync : 1; //!< \brief Value of the current sync found based carrier sense CCA state
+ //!< 0: Idle
+ //!< 1: Busy + } ccaInfo; } __RFC_STRUCT_ATTR; //! @} @@ -622,19 +622,19 @@ struct __RFC_STRUCT rfc_CMD_IEEE_CCA_REQ_s struct __RFC_STRUCT rfc_ieeeRxOutput_s { - uint8_t nTxAck; //!< Total number of transmitted ACK frames - uint8_t nRxBeacon; //!< Number of received beacon frames - uint8_t nRxData; //!< Number of received data frames - uint8_t nRxAck; //!< Number of received acknowledgement frames - uint8_t nRxMacCmd; //!< Number of received MAC command frames - uint8_t nRxReserved; //!< Number of received frames with reserved frame type - uint8_t nRxNok; //!< Number of received frames with CRC error - uint8_t nRxIgnored; //!< Number of frames received that are to be ignored - uint8_t nRxBufFull; //!< Number of received frames discarded because the Rx buffer was full - int8_t lastRssi; //!< RSSI of last received frame - int8_t maxRssi; //!< Highest RSSI observed in the operation - uint8_t __dummy0; - ratmr_t beaconTimeStamp; //!< Time stamp of last received beacon frame + uint8_t nTxAck; //!< Total number of transmitted ACK frames + uint8_t nRxBeacon; //!< Number of received beacon frames + uint8_t nRxData; //!< Number of received data frames + uint8_t nRxAck; //!< Number of received acknowledgement frames + uint8_t nRxMacCmd; //!< Number of received MAC command frames + uint8_t nRxReserved; //!< Number of received frames with reserved frame type + uint8_t nRxNok; //!< Number of received frames with CRC error + uint8_t nRxIgnored; //!< Number of frames received that are to be ignored + uint8_t nRxBufFull; //!< Number of received frames discarded because the Rx buffer was full + int8_t lastRssi; //!< RSSI of last received frame + int8_t maxRssi; //!< Highest RSSI observed in the operation + uint8_t __dummy0; + ratmr_t beaconTimeStamp; //!< Time stamp of last received beacon frame } __RFC_STRUCT_ATTR; //! @} @@ -645,8 +645,8 @@ struct __RFC_STRUCT rfc_ieeeRxOutput_s struct __RFC_STRUCT rfc_shortAddrEntry_s { - uint16_t shortAddr; //!< Short address - uint16_t panId; //!< PAN ID + uint16_t shortAddr; //!< Short address + uint16_t panId; //!< PAN ID } __RFC_STRUCT_ATTR; //! @} @@ -657,12 +657,12 @@ struct __RFC_STRUCT rfc_shortAddrEntry_s struct __RFC_STRUCT rfc_ieeeRxCorrCrc_s { - struct - { - uint8_t corr: 6; //!< The correlation value - uint8_t bIgnore: 1; //!< 1 if the packet should be rejected by frame filtering, 0 otherwise - uint8_t bCrcErr: 1; //!< 1 if the packet was received with CRC error, 0 otherwise - } status; + struct + { + uint8_t corr : 6; //!< The correlation value + uint8_t bIgnore : 1; //!< 1 if the packet should be rejected by frame filtering, 0 otherwise + uint8_t bCrcErr : 1; //!< 1 if the packet was received with CRC error, 0 otherwise + } status; } __RFC_STRUCT_ATTR; //! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_mailbox.h index e76cf28..55ad71a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_mailbox.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_mailbox.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_ieee_mailbox.h -* Revised: 2018-01-23 19:51:42 +0100 (Tue, 23 Jan 2018) -* Revision: 18189 -* -* Description: Definitions for IEEE 802.15.4 interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_ieee_mailbox.h + * Revised: 2018-01-23 19:51:42 +0100 (Tue, 23 Jan 2018) + * Revision: 18189 + * + * Description: Definitions for IEEE 802.15.4 interface + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _IEEE_MAILBOX_H #define _IEEE_MAILBOX_H @@ -45,28 +45,28 @@ ///@{ /// \name Operation not finished ///@{ -#define IEEE_SUSPENDED 0x2001 ///< Operation suspended +#define IEEE_SUSPENDED 0x2001 ///< Operation suspended ///@} /// \name Operation finished normally ///@{ -#define IEEE_DONE_OK 0x2400 ///< Operation ended normally -#define IEEE_DONE_BUSY 0x2401 ///< CSMA-CA operation ended with failure -#define IEEE_DONE_STOPPED 0x2402 ///< Operation stopped after stop command -#define IEEE_DONE_ACK 0x2403 ///< ACK packet received with pending data bit cleared -#define IEEE_DONE_ACKPEND 0x2404 ///< ACK packet received with pending data bit set -#define IEEE_DONE_TIMEOUT 0x2405 ///< Operation ended due to timeout -#define IEEE_DONE_BGEND 0x2406 ///< FG operation ended because necessary background level +#define IEEE_DONE_OK 0x2400 ///< Operation ended normally +#define IEEE_DONE_BUSY 0x2401 ///< CSMA-CA operation ended with failure +#define IEEE_DONE_STOPPED 0x2402 ///< Operation stopped after stop command +#define IEEE_DONE_ACK 0x2403 ///< ACK packet received with pending data bit cleared +#define IEEE_DONE_ACKPEND 0x2404 ///< ACK packet received with pending data bit set +#define IEEE_DONE_TIMEOUT 0x2405 ///< Operation ended due to timeout +#define IEEE_DONE_BGEND 0x2406 ///< FG operation ended because necessary background level ///< operation ended -#define IEEE_DONE_ABORT 0x2407 ///< Operation aborted by command +#define IEEE_DONE_ABORT 0x2407 ///< Operation aborted by command ///@} /// \name Operation finished with error ///@{ -#define IEEE_ERROR_PAR 0x2800 ///< Illegal parameter -#define IEEE_ERROR_NO_SETUP 0x2801 ///< Operation using Rx or Tx attempted when not in 15.4 mode -#define IEEE_ERROR_NO_FS 0x2802 ///< Operation using Rx or Tx attempted without frequency synth configured -#define IEEE_ERROR_SYNTH_PROG 0x2803 ///< Synthesizer programming failed to complete on time -#define IEEE_ERROR_RXOVF 0x2804 ///< Receiver overflowed during operation -#define IEEE_ERROR_TXUNF 0x2805 ///< Transmitter underflowed during operation +#define IEEE_ERROR_PAR 0x2800 ///< Illegal parameter +#define IEEE_ERROR_NO_SETUP 0x2801 ///< Operation using Rx or Tx attempted when not in 15.4 mode +#define IEEE_ERROR_NO_FS 0x2802 ///< Operation using Rx or Tx attempted without frequency synth configured +#define IEEE_ERROR_SYNTH_PROG 0x2803 ///< Synthesizer programming failed to complete on time +#define IEEE_ERROR_RXOVF 0x2804 ///< Receiver overflowed during operation +#define IEEE_ERROR_TXUNF 0x2805 ///< Transmitter underflowed during operation ///@} ///@} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_mailbox.h index 6262fad..138028a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_mailbox.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_mailbox.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_mailbox.h -* Revised: 2018-11-02 11:52:02 +0100 (Fri, 02 Nov 2018) -* Revision: 18756 -* -* Description: Definitions for interface between system and radio CPU -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_mailbox.h + * Revised: 2018-11-02 11:52:02 +0100 (Fri, 02 Nov 2018) + * Revision: 18756 + * + * Description: Definitions for interface between system and radio CPU + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _MAILBOX_H #define _MAILBOX_H @@ -42,132 +42,122 @@ #include #include - /// \name RF mode values /// Defines used to indicate mode of operation to radio core. ///@{ -#define RF_MODE_AUTO 0x00 -#define RF_MODE_BLE 0x00 -#define RF_MODE_IEEE_15_4 0x00 -#define RF_MODE_PROPRIETARY_2_4 0x00 -#define RF_MODE_PROPRIETARY RF_MODE_PROPRIETARY_2_4 -#define RF_MODE_MULTIPLE 0x00 +#define RF_MODE_AUTO 0x00 +#define RF_MODE_BLE 0x00 +#define RF_MODE_IEEE_15_4 0x00 +#define RF_MODE_PROPRIETARY_2_4 0x00 +#define RF_MODE_PROPRIETARY RF_MODE_PROPRIETARY_2_4 +#define RF_MODE_MULTIPLE 0x00 ///@} - /// Type definition for RAT typedef uint32_t ratmr_t; - - /// Type definition for a data queue typedef struct { - uint8_t* pCurrEntry; ///< Pointer to the data queue entry to be used, NULL for an empty queue - uint8_t* pLastEntry; ///< Pointer to the last entry in the queue, NULL for a circular queue + uint8_t* pCurrEntry; ///< Pointer to the data queue entry to be used, NULL for an empty queue + uint8_t* pLastEntry; ///< Pointer to the last entry in the queue, NULL for a circular queue } dataQueue_t; - - /// \name CPE interrupt definitions /// Interrupt masks for the CPE interrupt in RDBELL. ///@{ -#define IRQN_COMMAND_DONE 0 ///< Radio operation command finished -#define IRQN_LAST_COMMAND_DONE 1 ///< Last radio operation command in a chain finished -#define IRQN_FG_COMMAND_DONE 2 ///< FG level Radio operation command finished -#define IRQN_LAST_FG_COMMAND_DONE 3 ///< Last FG level radio operation command in a chain finished -#define IRQN_TX_DONE 4 ///< Packet transmitted -#define IRQN_TX_ACK 5 ///< ACK packet transmitted -#define IRQN_TX_CTRL 6 ///< Control packet transmitted -#define IRQN_TX_CTRL_ACK 7 ///< Acknowledgement received on a transmitted control packet -#define IRQN_TX_CTRL_ACK_ACK 8 ///< Acknowledgement received on a transmitted control packet, and acknowledgement transmitted for that packet -#define IRQN_TX_RETRANS 9 ///< Packet retransmitted -#define IRQN_TX_ENTRY_DONE 10 ///< Tx queue data entry state changed to Finished -#define IRQN_TX_BUFFER_CHANGED 11 ///< A buffer change is complete -#define IRQN_COMMAND_STARTED 12 ///< A radio operation command has gone into active state -#define IRQN_FG_COMMAND_STARTED 13 ///< FG level radio operation command has gone into active state -#define IRQN_PA_CHANGED 14 ///< PA is changed -#define IRQN_RX_OK 16 ///< Packet received with CRC OK, payload, and not to be ignored -#define IRQN_RX_NOK 17 ///< Packet received with CRC error -#define IRQN_RX_IGNORED 18 ///< Packet received with CRC OK, but to be ignored -#define IRQN_RX_EMPTY 19 ///< Packet received with CRC OK, not to be ignored, no payload -#define IRQN_RX_CTRL 20 ///< Control packet received with CRC OK, not to be ignored -#define IRQN_RX_CTRL_ACK 21 ///< Control packet received with CRC OK, not to be ignored, then ACK sent -#define IRQN_RX_BUF_FULL 22 ///< Packet received that did not fit in the Rx queue -#define IRQN_RX_ENTRY_DONE 23 ///< Rx queue data entry changing state to Finished -#define IRQN_RX_DATA_WRITTEN 24 ///< Data written to partial read Rx buffer -#define IRQN_RX_N_DATA_WRITTEN 25 ///< Specified number of bytes written to partial read Rx buffer -#define IRQN_RX_ABORTED 26 ///< Packet reception stopped before packet was done -#define IRQN_RX_COLLISION_DETECTED 27 ///< A collision was indicated during packet reception -#define IRQN_SYNTH_NO_LOCK 28 ///< The synth has gone out of lock after calibration -#define IRQN_MODULES_UNLOCKED 29 ///< As part of the boot process, the CM0 has opened access to RF core modules and memories -#define IRQN_BOOT_DONE 30 ///< The RF core CPU boot is finished +#define IRQN_COMMAND_DONE 0 ///< Radio operation command finished +#define IRQN_LAST_COMMAND_DONE 1 ///< Last radio operation command in a chain finished +#define IRQN_FG_COMMAND_DONE 2 ///< FG level Radio operation command finished +#define IRQN_LAST_FG_COMMAND_DONE 3 ///< Last FG level radio operation command in a chain finished +#define IRQN_TX_DONE 4 ///< Packet transmitted +#define IRQN_TX_ACK 5 ///< ACK packet transmitted +#define IRQN_TX_CTRL 6 ///< Control packet transmitted +#define IRQN_TX_CTRL_ACK 7 ///< Acknowledgement received on a transmitted control packet +#define IRQN_TX_CTRL_ACK_ACK 8 ///< Acknowledgement received on a transmitted control packet, and acknowledgement transmitted for that packet +#define IRQN_TX_RETRANS 9 ///< Packet retransmitted +#define IRQN_TX_ENTRY_DONE 10 ///< Tx queue data entry state changed to Finished +#define IRQN_TX_BUFFER_CHANGED 11 ///< A buffer change is complete +#define IRQN_COMMAND_STARTED 12 ///< A radio operation command has gone into active state +#define IRQN_FG_COMMAND_STARTED 13 ///< FG level radio operation command has gone into active state +#define IRQN_PA_CHANGED 14 ///< PA is changed +#define IRQN_RX_OK 16 ///< Packet received with CRC OK, payload, and not to be ignored +#define IRQN_RX_NOK 17 ///< Packet received with CRC error +#define IRQN_RX_IGNORED 18 ///< Packet received with CRC OK, but to be ignored +#define IRQN_RX_EMPTY 19 ///< Packet received with CRC OK, not to be ignored, no payload +#define IRQN_RX_CTRL 20 ///< Control packet received with CRC OK, not to be ignored +#define IRQN_RX_CTRL_ACK 21 ///< Control packet received with CRC OK, not to be ignored, then ACK sent +#define IRQN_RX_BUF_FULL 22 ///< Packet received that did not fit in the Rx queue +#define IRQN_RX_ENTRY_DONE 23 ///< Rx queue data entry changing state to Finished +#define IRQN_RX_DATA_WRITTEN 24 ///< Data written to partial read Rx buffer +#define IRQN_RX_N_DATA_WRITTEN 25 ///< Specified number of bytes written to partial read Rx buffer +#define IRQN_RX_ABORTED 26 ///< Packet reception stopped before packet was done +#define IRQN_RX_COLLISION_DETECTED 27 ///< A collision was indicated during packet reception +#define IRQN_SYNTH_NO_LOCK 28 ///< The synth has gone out of lock after calibration +#define IRQN_MODULES_UNLOCKED 29 ///< As part of the boot process, the CM0 has opened access to RF core modules and memories +#define IRQN_BOOT_DONE 30 ///< The RF core CPU boot is finished -#define IRQN_INTERNAL_ERROR 31 ///< Internal error observed +#define IRQN_INTERNAL_ERROR 31 ///< Internal error observed -#define IRQ_COMMAND_DONE (1U << IRQN_COMMAND_DONE) -#define IRQ_LAST_COMMAND_DONE (1U << IRQN_LAST_COMMAND_DONE) -#define IRQ_FG_COMMAND_DONE (1U << IRQN_FG_COMMAND_DONE) -#define IRQ_LAST_FG_COMMAND_DONE (1U << IRQN_LAST_FG_COMMAND_DONE) +#define IRQ_COMMAND_DONE (1U << IRQN_COMMAND_DONE) +#define IRQ_LAST_COMMAND_DONE (1U << IRQN_LAST_COMMAND_DONE) +#define IRQ_FG_COMMAND_DONE (1U << IRQN_FG_COMMAND_DONE) +#define IRQ_LAST_FG_COMMAND_DONE (1U << IRQN_LAST_FG_COMMAND_DONE) -#define IRQ_TX_DONE (1U << IRQN_TX_DONE) -#define IRQ_TX_ACK (1U << IRQN_TX_ACK) -#define IRQ_TX_CTRL (1U << IRQN_TX_CTRL) -#define IRQ_TX_CTRL_ACK (1U << IRQN_TX_CTRL_ACK) -#define IRQ_TX_CTRL_ACK_ACK (1U << IRQN_TX_CTRL_ACK_ACK) -#define IRQ_TX_RETRANS (1U << IRQN_TX_RETRANS) +#define IRQ_TX_DONE (1U << IRQN_TX_DONE) +#define IRQ_TX_ACK (1U << IRQN_TX_ACK) +#define IRQ_TX_CTRL (1U << IRQN_TX_CTRL) +#define IRQ_TX_CTRL_ACK (1U << IRQN_TX_CTRL_ACK) +#define IRQ_TX_CTRL_ACK_ACK (1U << IRQN_TX_CTRL_ACK_ACK) +#define IRQ_TX_RETRANS (1U << IRQN_TX_RETRANS) -#define IRQ_TX_ENTRY_DONE (1U << IRQN_TX_ENTRY_DONE) -#define IRQ_TX_BUFFER_CHANGED (1U << IRQN_TX_BUFFER_CHANGED) +#define IRQ_TX_ENTRY_DONE (1U << IRQN_TX_ENTRY_DONE) +#define IRQ_TX_BUFFER_CHANGED (1U << IRQN_TX_BUFFER_CHANGED) -#define IRQ_COMMAND_STARTED (1U << IRQN_COMMAND_STARTED) -#define IRQ_FG_COMMAND_STARTED (1U << IRQN_FG_COMMAND_STARTED) -#define IRQ_PA_CHANGED (1U << IRQN_PA_CHANGED) +#define IRQ_COMMAND_STARTED (1U << IRQN_COMMAND_STARTED) +#define IRQ_FG_COMMAND_STARTED (1U << IRQN_FG_COMMAND_STARTED) +#define IRQ_PA_CHANGED (1U << IRQN_PA_CHANGED) -#define IRQ_RX_OK (1U << IRQN_RX_OK) -#define IRQ_RX_NOK (1U << IRQN_RX_NOK) -#define IRQ_RX_IGNORED (1U << IRQN_RX_IGNORED) -#define IRQ_RX_EMPTY (1U << IRQN_RX_EMPTY) -#define IRQ_RX_CTRL (1U << IRQN_RX_CTRL) -#define IRQ_RX_CTRL_ACK (1U << IRQN_RX_CTRL_ACK) -#define IRQ_RX_BUF_FULL (1U << IRQN_RX_BUF_FULL) -#define IRQ_RX_ENTRY_DONE (1U << IRQN_RX_ENTRY_DONE) -#define IRQ_RX_DATA_WRITTEN (1U << IRQN_RX_DATA_WRITTEN) -#define IRQ_RX_N_DATA_WRITTEN (1U << IRQN_RX_N_DATA_WRITTEN) -#define IRQ_RX_ABORTED (1U << IRQN_RX_ABORTED) -#define IRQ_RX_COLLISION_DETECTED (1U << IRQN_RX_COLLISION_DETECTED) -#define IRQ_SYNTH_NO_LOCK (1U << IRQN_SYNTH_NO_LOCK) -#define IRQ_MODULES_UNLOCKED (1U << IRQN_MODULES_UNLOCKED) -#define IRQ_BOOT_DONE (1U << IRQN_BOOT_DONE) -#define IRQ_INTERNAL_ERROR (1U << IRQN_INTERNAL_ERROR) +#define IRQ_RX_OK (1U << IRQN_RX_OK) +#define IRQ_RX_NOK (1U << IRQN_RX_NOK) +#define IRQ_RX_IGNORED (1U << IRQN_RX_IGNORED) +#define IRQ_RX_EMPTY (1U << IRQN_RX_EMPTY) +#define IRQ_RX_CTRL (1U << IRQN_RX_CTRL) +#define IRQ_RX_CTRL_ACK (1U << IRQN_RX_CTRL_ACK) +#define IRQ_RX_BUF_FULL (1U << IRQN_RX_BUF_FULL) +#define IRQ_RX_ENTRY_DONE (1U << IRQN_RX_ENTRY_DONE) +#define IRQ_RX_DATA_WRITTEN (1U << IRQN_RX_DATA_WRITTEN) +#define IRQ_RX_N_DATA_WRITTEN (1U << IRQN_RX_N_DATA_WRITTEN) +#define IRQ_RX_ABORTED (1U << IRQN_RX_ABORTED) +#define IRQ_RX_COLLISION_DETECTED (1U << IRQN_RX_COLLISION_DETECTED) +#define IRQ_SYNTH_NO_LOCK (1U << IRQN_SYNTH_NO_LOCK) +#define IRQ_MODULES_UNLOCKED (1U << IRQN_MODULES_UNLOCKED) +#define IRQ_BOOT_DONE (1U << IRQN_BOOT_DONE) +#define IRQ_INTERNAL_ERROR (1U << IRQN_INTERNAL_ERROR) ///@} - - /// \name CMDSTA values /// Values returned in result byte of CMDSTA ///@{ -#define CMDSTA_Pending 0x00 ///< The command has not yet been parsed -#define CMDSTA_Done 0x01 ///< Command successfully parsed +#define CMDSTA_Pending 0x00 ///< The command has not yet been parsed +#define CMDSTA_Done 0x01 ///< Command successfully parsed -#define CMDSTA_IllegalPointer 0x81 ///< The pointer signaled in CMDR is not valid -#define CMDSTA_UnknownCommand 0x82 ///< The command number in the command structure is unknown -#define CMDSTA_UnknownDirCommand 0x83 ///< The command number for a direct command is unknown, or the +#define CMDSTA_IllegalPointer 0x81 ///< The pointer signaled in CMDR is not valid +#define CMDSTA_UnknownCommand 0x82 ///< The command number in the command structure is unknown +#define CMDSTA_UnknownDirCommand 0x83 ///< The command number for a direct command is unknown, or the ///< command is not a direct command -#define CMDSTA_ContextError 0x85 ///< An immediate or direct command was issued in a context +#define CMDSTA_ContextError 0x85 ///< An immediate or direct command was issued in a context ///< where it is not supported -#define CMDSTA_SchedulingError 0x86 ///< A radio operation command was attempted to be scheduled +#define CMDSTA_SchedulingError 0x86 ///< A radio operation command was attempted to be scheduled ///< while another operation was already running in the RF core -#define CMDSTA_ParError 0x87 ///< There were errors in the command parameters that are parsed +#define CMDSTA_ParError 0x87 ///< There were errors in the command parameters that are parsed ///< on submission. -#define CMDSTA_QueueError 0x88 ///< An operation on a data entry queue was attempted that was +#define CMDSTA_QueueError 0x88 ///< An operation on a data entry queue was attempted that was ///< not supported by the queue in its current state -#define CMDSTA_QueueBusy 0x89 ///< An operation on a data entry was attempted while that entry +#define CMDSTA_QueueBusy 0x89 ///< An operation on a data entry was attempted while that entry ///< was busy ///@} - - /// \name Macros for sending direct commands ///@{ /// Direct command with no parameter @@ -181,8 +171,6 @@ typedef struct ///@} - - /// \name Definitions for trigger types ///@{ #define TRIG_NOW 0 ///< Triggers immediately @@ -200,63 +188,59 @@ typedef struct ///< trigger happened in the past ///@} - /// \name Definitions for conditional execution ///@{ -#define COND_ALWAYS 0 ///< Always run next command (except in case of Abort) -#define COND_NEVER 1 ///< Never run next command -#define COND_STOP_ON_FALSE 2 ///< Run next command if this command returned True, stop if it returned +#define COND_ALWAYS 0 ///< Always run next command (except in case of Abort) +#define COND_NEVER 1 ///< Never run next command +#define COND_STOP_ON_FALSE 2 ///< Run next command if this command returned True, stop if it returned ///< False -#define COND_STOP_ON_TRUE 3 ///< Stop if this command returned True, run next command if it returned +#define COND_STOP_ON_TRUE 3 ///< Stop if this command returned True, run next command if it returned ///< False -#define COND_SKIP_ON_FALSE 4 ///< Run next command if this command returned True, skip a number of +#define COND_SKIP_ON_FALSE 4 ///< Run next command if this command returned True, skip a number of ///< commands if it returned False -#define COND_SKIP_ON_TRUE 5 ///< Skip a number of commands if this command returned True, run next +#define COND_SKIP_ON_TRUE 5 ///< Skip a number of commands if this command returned True, run next ///< command if it returned False ///@} - - /// \name Radio operation status ///@{ /// \name Operation not finished ///@{ -#define IDLE 0x0000 ///< Operation not started -#define PENDING 0x0001 ///< Start of command is pending -#define ACTIVE 0x0002 ///< Running -#define SKIPPED 0x0003 ///< Operation skipped due to condition in another command +#define IDLE 0x0000 ///< Operation not started +#define PENDING 0x0001 ///< Start of command is pending +#define ACTIVE 0x0002 ///< Running +#define SKIPPED 0x0003 ///< Operation skipped due to condition in another command ///@} /// \name Operation finished normally ///@{ -#define DONE_OK 0x0400 ///< Operation ended normally -#define DONE_COUNTDOWN 0x0401 ///< Counter reached zero -#define DONE_RXERR 0x0402 ///< Operation ended with CRC error -#define DONE_TIMEOUT 0x0403 ///< Operation ended with timeout -#define DONE_STOPPED 0x0404 ///< Operation stopped after CMD_STOP command -#define DONE_ABORT 0x0405 ///< Operation aborted by CMD_ABORT command -#define DONE_FAILED 0x0406 ///< Scheduled immediate command failed +#define DONE_OK 0x0400 ///< Operation ended normally +#define DONE_COUNTDOWN 0x0401 ///< Counter reached zero +#define DONE_RXERR 0x0402 ///< Operation ended with CRC error +#define DONE_TIMEOUT 0x0403 ///< Operation ended with timeout +#define DONE_STOPPED 0x0404 ///< Operation stopped after CMD_STOP command +#define DONE_ABORT 0x0405 ///< Operation aborted by CMD_ABORT command +#define DONE_FAILED 0x0406 ///< Scheduled immediate command failed ///@} /// \name Operation finished with error ///@{ -#define ERROR_PAST_START 0x0800 ///< The start trigger occurred in the past -#define ERROR_START_TRIG 0x0801 ///< Illegal start trigger parameter -#define ERROR_CONDITION 0x0802 ///< Illegal condition for next operation -#define ERROR_PAR 0x0803 ///< Error in a command specific parameter -#define ERROR_POINTER 0x0804 ///< Invalid pointer to next operation -#define ERROR_CMDID 0x0805 ///< Next operation has a command ID that is undefined or not a radio +#define ERROR_PAST_START 0x0800 ///< The start trigger occurred in the past +#define ERROR_START_TRIG 0x0801 ///< Illegal start trigger parameter +#define ERROR_CONDITION 0x0802 ///< Illegal condition for next operation +#define ERROR_PAR 0x0803 ///< Error in a command specific parameter +#define ERROR_POINTER 0x0804 ///< Invalid pointer to next operation +#define ERROR_CMDID 0x0805 ///< Next operation has a command ID that is undefined or not a radio ///< operation command -#define ERROR_WRONG_BG 0x0806 ///< FG level command not compatible with running BG level command -#define ERROR_NO_SETUP 0x0807 ///< Operation using Rx or Tx attempted without CMD_RADIO_SETUP -#define ERROR_NO_FS 0x0808 ///< Operation using Rx or Tx attempted without frequency synth configured -#define ERROR_SYNTH_PROG 0x0809 ///< Synthesizer calibration failed -#define ERROR_TXUNF 0x080A ///< Tx underflow observed -#define ERROR_RXOVF 0x080B ///< Rx overflow observed -#define ERROR_NO_RX 0x080C ///< Attempted to access data from Rx when no such data was yet received -#define ERROR_PENDING 0x080D ///< Command submitted in the future with another command at different level pending +#define ERROR_WRONG_BG 0x0806 ///< FG level command not compatible with running BG level command +#define ERROR_NO_SETUP 0x0807 ///< Operation using Rx or Tx attempted without CMD_RADIO_SETUP +#define ERROR_NO_FS 0x0808 ///< Operation using Rx or Tx attempted without frequency synth configured +#define ERROR_SYNTH_PROG 0x0809 ///< Synthesizer calibration failed +#define ERROR_TXUNF 0x080A ///< Tx underflow observed +#define ERROR_RXOVF 0x080B ///< Rx overflow observed +#define ERROR_NO_RX 0x080C ///< Attempted to access data from Rx when no such data was yet received +#define ERROR_PENDING 0x080D ///< Command submitted in the future with another command at different level pending ///@} ///@} - /// \name Data entry types ///@{ #define DATA_ENTRY_TYPE_GEN 0 ///< General type: Tx entry or single element Rx entry @@ -265,37 +249,34 @@ typedef struct #define DATA_ENTRY_TYPE_PARTIAL 3 ///< Partial read entry type ///@ - /// \name Data entry statuses ///@{ -#define DATA_ENTRY_PENDING 0 ///< Entry not yet used -#define DATA_ENTRY_ACTIVE 1 ///< Entry in use by radio CPU -#define DATA_ENTRY_BUSY 2 ///< Entry being updated -#define DATA_ENTRY_FINISHED 3 ///< Radio CPU is finished accessing the entry -#define DATA_ENTRY_UNFINISHED 4 ///< Radio CPU is finished accessing the entry, but packet could not be finished +#define DATA_ENTRY_PENDING 0 ///< Entry not yet used +#define DATA_ENTRY_ACTIVE 1 ///< Entry in use by radio CPU +#define DATA_ENTRY_BUSY 2 ///< Entry being updated +#define DATA_ENTRY_FINISHED 3 ///< Radio CPU is finished accessing the entry +#define DATA_ENTRY_UNFINISHED 4 ///< Radio CPU is finished accessing the entry, but packet could not be finished ///@} - /// \name Macros for RF register override ///@{ /// Macro for ADI half-size value-mask combination #define ADI_VAL_MASK(addr, mask, value) \ - (((addr) & 1) ? (((mask) & 0x0F) | (((value) & 0x0F) << 4)) : \ - ((((mask) & 0x0F) << 4) | ((value) & 0x0F))) + (((addr) & 1) ? (((mask) & 0x0F) | (((value) & 0x0F) << 4)) : ((((mask) & 0x0F) << 4) | ((value) & 0x0F))) /// 32-bit write of 16-bit value -#define HW_REG_OVERRIDE(addr, val) ((((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(val) << 16)) +#define HW_REG_OVERRIDE(addr, val) ((((uintptr_t)(addr)) & 0xFFFC) | ((uint32_t)(val) << 16)) /// ADI register, full-size write #define ADI_REG_OVERRIDE(adiNo, addr, val) (2 | ((uint32_t)(val) << 16) | \ - (((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31)) + (((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31)) /// 2 ADI registers, full-size write -#define ADI_2REG_OVERRIDE(adiNo, addr, val, addr2, val2) \ +#define ADI_2REG_OVERRIDE(adiNo, addr, val, addr2, val2) \ (2 | ((uint32_t)(val2) << 2) | (((addr2) & 0x3F) << 10) | ((uint32_t)(val) << 16) | \ (((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31)) /// ADI register, half-size read-modify-write #define ADI_HALFREG_OVERRIDE(adiNo, addr, mask, val) (2 | (ADI_VAL_MASK(addr, mask, val) << 16) | \ - (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31)) + (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31)) /// 2 ADI registers, half-size read-modify-write -#define ADI_2HALFREG_OVERRIDE(adiNo, addr, mask, val, addr2, mask2, val2) \ +#define ADI_2HALFREG_OVERRIDE(adiNo, addr, mask, val, addr2, mask2, val2) \ (2 | (ADI_VAL_MASK(addr2, mask2, val2) << 2) | (((addr2) & 0x3F) << 10) | \ (ADI_VAL_MASK(addr, mask, val) << 16) | (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31)) @@ -303,54 +284,53 @@ typedef struct #define SW_REG_OVERRIDE(cmd, field, val) (3 | ((_POSITION_##cmd##_##field) << 4) | ((uint32_t)(val) << 16)) /// SW register as defined in radio_par_def.txt with added index (for use with registers > 16 bits). #define SW_REG_IND_OVERRIDE(cmd, field, offset, val) (3 | \ - (((_POSITION_##cmd##_##field) + ((offset) << 1)) << 4) | ((uint32_t)(val) << 16)) + (((_POSITION_##cmd##_##field) + ((offset) << 1)) << 4) | ((uint32_t)(val) << 16)) /// 8-bit SW register as defined in radio_par_def.txt #define SW_REG_BYTE_OVERRIDE(cmd, field, val) (0x8003 | ((_POSITION_##cmd##_##field) << 4) | \ - (((uint32_t)(val) & 0xFF) << 16)) + (((uint32_t)(val) & 0xFF) << 16)) /// Two 8-bit SW registers as defined in radio_par_def.txt; the one given by field and the next byte. #define SW_REG_2BYTE_OVERRIDE(cmd, field, val0, val1) (3 | (((_POSITION_##cmd##_##field) & 0xFFFE) << 4) | \ - (((uint32_t)(val0) << 16) & 0x00FF0000) | ((uint32_t)(val1) << 24)) + (((uint32_t)(val0) << 16) & 0x00FF0000) | ((uint32_t)(val1) << 24)) #define SW_REG_MASK_OVERRIDE(cmd, field, offset, mask, val) (0x8003 | \ - ((_POSITION_##cmd##_##field + (offset)) << 4) | (((uint32_t)(val) & 0xFF) << 16) | (((uint32_t)(mask) & 0xFF) << 24)) + ((_POSITION_##cmd##_##field + (offset)) << 4) | (((uint32_t)(val) & 0xFF) << 16) | (((uint32_t)(mask) & 0xFF) << 24)) -#define HW16_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) -#define HW32_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | \ - ((uint32_t)(length) << 16) | (1U << 30)) -#define HW16_MASK_ARRAY_OVERRIDE(addr, length) (0x20000001 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) -#define HW32_MASK_ARRAY_OVERRIDE(addr, length) (0x60000001 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) +#define HW16_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t)(addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) +#define HW32_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t)(addr)) & 0xFFFC) | \ + ((uint32_t)(length) << 16) | (1U << 30)) +#define HW16_MASK_ARRAY_OVERRIDE(addr, length) (0x20000001 | (((uintptr_t)(addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) +#define HW32_MASK_ARRAY_OVERRIDE(addr, length) (0x60000001 | (((uintptr_t)(addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) #define HW16_MASK_VAL(mask, val) ((mask) << 16 | (val)) #define ADI_ARRAY_OVERRIDE(adiNo, addr, bHalfSize, length) (1 | ((((addr) & 0x3F) << 2)) | \ - ((!!(bHalfSize)) << 8) | ((!!(adiNo)) << 9) | ((uint32_t)(length) << 16) | (2U << 30)) + ((!!(bHalfSize)) << 8) | ((!!(adiNo)) << 9) | ((uint32_t)(length) << 16) | (2U << 30)) #define SW_ARRAY_OVERRIDE(cmd, firstfield, length) (1 | (((_POSITION_##cmd##_##firstfield)) << 2) | \ - ((uint32_t)(length) << 16) | (3U << 30)) + ((uint32_t)(length) << 16) | (3U << 30)) #define MCE_RFE_OVERRIDE(mceCfg, mceRomBank, mceMode, rfeCfg, rfeRomBank, rfeMode) \ - (7 | ((mceCfg & 2) << 3) | ((rfeCfg & 2) << 4) |\ - ((mceCfg & 1) << 6) | (((mceRomBank) & 0x0F) << 7) | \ - ((rfeCfg & 1) << 11) | (((rfeRomBank) & 0x0F) << 12) | \ + (7 | ((mceCfg & 2) << 3) | ((rfeCfg & 2) << 4) | \ + ((mceCfg & 1) << 6) | (((mceRomBank) & 0x0F) << 7) | \ + ((rfeCfg & 1) << 11) | (((rfeRomBank) & 0x0F) << 12) | \ (((mceMode) & 0x00FF) << 16) | (((rfeMode) & 0x00FF) << 24)) #define HPOSC_OVERRIDE(freqOffset) (0x000B | ((freqOffset) << 16)) -#define TX20_POWER_OVERRIDE(tx20Power) (0x002B | (((uint32_t) tx20Power) << 10)) -#define TX_STD_POWER_OVERRIDE(txPower) (0x022B | (((uint32_t) txPower) << 10)) +#define TX20_POWER_OVERRIDE(tx20Power) (0x002B | (((uint32_t)tx20Power) << 10)) +#define TX_STD_POWER_OVERRIDE(txPower) (0x022B | (((uint32_t)txPower) << 10)) #define MCE_RFE_SPLIT_OVERRIDE(mceRxCfg, mceTxCfg, rfeRxCfg, rfeTxCfg) \ (0x003B | ((mceRxCfg) << 12) | ((mceTxCfg) << 17) | ((rfeRxCfg) << 22) | ((rfeTxCfg) << 27)) #define CENTER_FREQ_OVERRIDE(centerFreq, flags) (0x004B | ((flags & 0x03) << 18) | \ - ((centerFreq) << 20)) + ((centerFreq) << 20)) #define MOD_TYPE_OVERRIDE(modType, deviation, stepSz, flags) (0x005B | ((flags & 0x01) << 15) | \ - ((modType) << 16) | ((deviation) << 19) |((stepSz) << 30) ) -#define NEW_OVERRIDE_SEGMENT(address) (((((uintptr_t)(address)) & 0x03FFFFFC) << 6) | 0x000F | \ - (((((uintptr_t)(address) >> 24) == 0x20) ? 0x01 : \ - (((uintptr_t)(address) >> 24) == 0x21) ? 0x02 : \ - (((uintptr_t)(address) >> 24) == 0xA0) ? 0x03 : \ - (((uintptr_t)(address) >> 24) == 0x00) ? 0x04 : \ - (((uintptr_t)(address) >> 24) == 0x10) ? 0x05 : \ - (((uintptr_t)(address) >> 24) == 0x11) ? 0x06 : \ - (((uintptr_t)(address) >> 24) == 0x40) ? 0x07 : \ - (((uintptr_t)(address) >> 24) == 0x50) ? 0x08 : \ - 0x09) << 4)) // Use illegal value for illegal address range + ((modType) << 16) | ((deviation) << 19) | ((stepSz) << 30)) +#define NEW_OVERRIDE_SEGMENT(address) (((((uintptr_t)(address)) & 0x03FFFFFC) << 6) | 0x000F | \ + (((((uintptr_t)(address) >> 24) == 0x20) ? 0x01 : (((uintptr_t)(address) >> 24) == 0x21) ? 0x02 \ + : (((uintptr_t)(address) >> 24) == 0xA0) ? 0x03 \ + : (((uintptr_t)(address) >> 24) == 0x00) ? 0x04 \ + : (((uintptr_t)(address) >> 24) == 0x10) ? 0x05 \ + : (((uintptr_t)(address) >> 24) == 0x11) ? 0x06 \ + : (((uintptr_t)(address) >> 24) == 0x40) ? 0x07 \ + : (((uintptr_t)(address) >> 24) == 0x50) ? 0x08 \ + : 0x09) \ + << 4)) // Use illegal value for illegal address range /// End of string for override register #define END_OVERRIDE 0xFFFFFFFF - /// ADI address-value pair #define ADI_ADDR_VAL(addr, value) ((((addr) & 0x7F) << 8) | ((value) & 0xFF)) #define ADI_ADDR_VAL_MASK(addr, mask, value) ((((addr) & 0x7F) << 8) | ADI_VAL_MASK(addr, mask, value)) @@ -361,5 +341,4 @@ typedef struct #define HIWORD(value) ((value) >> 16) ///@} - #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_cmd.h index f22ac81..69230d8 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_cmd.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_cmd.h @@ -1,56 +1,56 @@ /****************************************************************************** -* Filename: rf_prop_cmd.h -* Revised: 2018-07-31 20:13:42 +0200 (Tue, 31 Jul 2018) -* Revision: 18572 -* -* Description: CC13x2/CC26x2 API for Proprietary mode commands -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_prop_cmd.h + * Revised: 2018-07-31 20:13:42 +0200 (Tue, 31 Jul 2018) + * Revision: 18572 + * + * Description: CC13x2/CC26x2 API for Proprietary mode commands + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __PROP_CMD_H #define __PROP_CMD_H #ifndef __RFC_STRUCT - #define __RFC_STRUCT +#define __RFC_STRUCT #endif #ifndef __RFC_STRUCT_ATTR - #if defined(__GNUC__) - #define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) - #elif defined(__TI_ARM__) - #define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) - #else - #define __RFC_STRUCT_ATTR - #endif +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__((aligned(4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__((__packed__, aligned(4))) +#else +#define __RFC_STRUCT_ATTR +#endif #endif //! \addtogroup rfc @@ -59,9 +59,9 @@ //! \addtogroup prop_cmd //! @{ -#include -#include "rf_mailbox.h" #include "rf_common_cmd.h" +#include "rf_mailbox.h" +#include typedef struct __RFC_STRUCT rfc_carrierSense_s rfc_carrierSense_t; typedef struct __RFC_STRUCT rfc_CMD_PROP_TX_s rfc_CMD_PROP_TX_t; @@ -84,879 +84,879 @@ typedef struct __RFC_STRUCT rfc_propRxStatus_s rfc_propRxStatus_t; //! @{ struct __RFC_STRUCT rfc_carrierSense_s { - struct - { - uint8_t bEnaRssi: 1; //!< If 1, enable RSSI as a criterion - uint8_t bEnaCorr: 1; //!< If 1, enable correlation as a criterion - uint8_t operation: 1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
- //!< 1: Busy if both RSSI and correlation indicates Busy - uint8_t busyOp: 1; //!< \brief 0: Continue carrier sense on channel Busy
- //!< 1: End carrier sense on channel Busy
- //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle - uint8_t idleOp: 1; //!< \brief 0: Continue on channel Idle
- //!< 1: End on channel Idle - uint8_t timeoutRes: 1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
- //!< 1: Timeout with channel state Invalid treated as Idle - } csConf; - int8_t rssiThr; //!< RSSI threshold - uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is - //!< declared Idle - uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is - //!< declared Busy - uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods - struct - { - uint8_t numCorrInv: 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Idle to Invalid - uint8_t numCorrBusy: 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Invalid to Busy - } corrConfig; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } csEndTrigger; //!< Trigger classifier for ending the carrier sense - ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation + struct + { + uint8_t bEnaRssi : 1; //!< If 1, enable RSSI as a criterion + uint8_t bEnaCorr : 1; //!< If 1, enable correlation as a criterion + uint8_t operation : 1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
+ //!< 1: Busy if both RSSI and correlation indicates Busy + uint8_t busyOp : 1; //!< \brief 0: Continue carrier sense on channel Busy
+ //!< 1: End carrier sense on channel Busy
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle + uint8_t idleOp : 1; //!< \brief 0: Continue on channel Idle
+ //!< 1: End on channel Idle + uint8_t timeoutRes : 1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
+ //!< 1: Timeout with channel state Invalid treated as Idle + } csConf; + int8_t rssiThr; //!< RSSI threshold + uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is + //!< declared Idle + uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is + //!< declared Busy + uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods + struct + { + uint8_t numCorrInv : 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Idle to Invalid + uint8_t numCorrBusy : 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Invalid to Busy + } corrConfig; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } csEndTrigger; //!< Trigger classifier for ending the carrier sense + ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_TX //! @{ -#define CMD_PROP_TX 0x3801 +#define CMD_PROP_TX 0x3801 //! Proprietary Mode Transmit Command struct __RFC_STRUCT rfc_CMD_PROP_TX_s { - uint16_t commandNo; //!< The command ID number 0x3801 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t : 2; - uint8_t bUseCrc: 1; //!< \brief 0: Do not append CRC
- //!< 1: Append CRC - uint8_t bVarLen: 1; //!< \brief 0: Fixed length
- //!< 1: Transmit length as first byte - } pktConf; - uint8_t pktLen; //!< Packet length - uint32_t syncWord; //!< Sync word to transmit - uint8_t* pPkt; //!< Pointer to packet + uint16_t commandNo; //!< The command ID number 0x3801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t : 2; + uint8_t bUseCrc : 1; //!< \brief 0: Do not append CRC
+ //!< 1: Append CRC + uint8_t bVarLen : 1; //!< \brief 0: Fixed length
+ //!< 1: Transmit length as first byte + } pktConf; + uint8_t pktLen; //!< Packet length + uint32_t syncWord; //!< Sync word to transmit + uint8_t* pPkt; //!< Pointer to packet } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_RX //! @{ -#define CMD_PROP_RX 0x3802 +#define CMD_PROP_RX 0x3802 //! Proprietary Mode Receive Command struct __RFC_STRUCT rfc_CMD_PROP_RX_s { - uint16_t commandNo; //!< The command ID number 0x3802 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bRepeatOk: 1; //!< \brief 0: End operation after receiving a packet correctly
- //!< 1: Go back to sync search after receiving a packet correctly - uint8_t bRepeatNok: 1; //!< \brief 0: End operation after receiving a packet with CRC error
- //!< 1: Go back to sync search after receiving a packet with CRC error - uint8_t bUseCrc: 1; //!< \brief 0: Do not check CRC
- //!< 1: Check CRC - uint8_t bVarLen: 1; //!< \brief 0: Fixed length
- //!< 1: Receive length as first byte - uint8_t bChkAddress: 1; //!< \brief 0: No address check
- //!< 1: Check address - uint8_t endType: 1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
- //!< 1: Packet reception is stopped if end trigger happens - uint8_t filterOp: 1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
- //!< 1: Receive packet and mark it as ignored on address mismatch - } pktConf; - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically discard ignored packets from RX queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically discard packets with CRC error from RX queue - uint8_t : 1; - uint8_t bIncludeHdr: 1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the RX queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the RX queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the RX queue - } rxConf; //!< RX configuration - uint32_t syncWord; //!< Sync word to listen for - uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
- //!< 0: Unlimited or unknown length - uint8_t address0; //!< Address - uint8_t address1; //!< \brief Address (set equal to address0 to accept only one address. If 0xFF, accept - //!< 0x00 as well) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - ratmr_t endTime; //!< Time used together with endTrigger for ending the operation - dataQueue_t* pQueue; //!< Pointer to receive queue - uint8_t* pOutput; //!< Pointer to output structure + uint16_t commandNo; //!< The command ID number 0x3802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk : 1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok : 1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc : 1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bVarLen : 1; //!< \brief 0: Fixed length
+ //!< 1: Receive length as first byte + uint8_t bChkAddress : 1; //!< \brief 0: No address check
+ //!< 1: Check address + uint8_t endType : 1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp : 1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t : 1; + uint8_t bIncludeHdr : 1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord; //!< Sync word to listen for + uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + uint8_t address0; //!< Address + uint8_t address1; //!< \brief Address (set equal to address0 to accept only one address. If 0xFF, accept + //!< 0x00 as well) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_TX_ADV //! @{ -#define CMD_PROP_TX_ADV 0x3803 +#define CMD_PROP_TX_ADV 0x3803 //! Proprietary Mode Advanced Transmit Command struct __RFC_STRUCT rfc_CMD_PROP_TX_ADV_s { - uint16_t commandNo; //!< The command ID number 0x3803 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t : 2; - uint8_t bUseCrc: 1; //!< \brief 0: Do not append CRC
- //!< 1: Append CRC - uint8_t bCrcIncSw: 1; //!< \brief 0:Do not include sync word in CRC calculation
- //!< 1: Include sync word in CRC calculation - uint8_t bCrcIncHdr: 1; //!< \brief 0: Do not include header in CRC calculation
- //!< 1: Include header in CRC calculation - } pktConf; - uint8_t numHdrBits; //!< Number of bits in header (0--32) - uint16_t pktLen; //!< Packet length. 0: Unlimited - struct - { - uint8_t bExtTxTrig: 1; //!< \brief 0: Start packet on a fixed time from the command start trigger
- //!< 1: Start packet on an external trigger (input event to RAT) - uint8_t inputMode: 2; //!< \brief Input mode if external trigger is used for TX start
- //!< 0: Rising edge
- //!< 1: Falling edge
- //!< 2: Both edges
- //!< 3: Reserved - uint8_t source: 5; //!< RAT input event number used for capture if external trigger is used for TX start - } startConf; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } preTrigger; //!< Trigger for transition from preamble to sync word - ratmr_t preTime; //!< \brief Time used together with preTrigger for transition from preamble to sync - //!< word. If preTrigger.triggerType is set to "now", one preamble as - //!< configured in the setup will be sent. Otherwise, the preamble will be repeated until - //!< this trigger is observed. - uint32_t syncWord; //!< Sync word to transmit - uint8_t* pPkt; //!< Pointer to packet, or TX queue for unlimited length + uint16_t commandNo; //!< The command ID number 0x3803 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t : 2; + uint8_t bUseCrc : 1; //!< \brief 0: Do not append CRC
+ //!< 1: Append CRC + uint8_t bCrcIncSw : 1; //!< \brief 0:Do not include sync word in CRC calculation
+ //!< 1: Include sync word in CRC calculation + uint8_t bCrcIncHdr : 1; //!< \brief 0: Do not include header in CRC calculation
+ //!< 1: Include header in CRC calculation + } pktConf; + uint8_t numHdrBits; //!< Number of bits in header (0--32) + uint16_t pktLen; //!< Packet length. 0: Unlimited + struct + { + uint8_t bExtTxTrig : 1; //!< \brief 0: Start packet on a fixed time from the command start trigger
+ //!< 1: Start packet on an external trigger (input event to RAT) + uint8_t inputMode : 2; //!< \brief Input mode if external trigger is used for TX start
+ //!< 0: Rising edge
+ //!< 1: Falling edge
+ //!< 2: Both edges
+ //!< 3: Reserved + uint8_t source : 5; //!< RAT input event number used for capture if external trigger is used for TX start + } startConf; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } preTrigger; //!< Trigger for transition from preamble to sync word + ratmr_t preTime; //!< \brief Time used together with preTrigger for transition from preamble to sync + //!< word. If preTrigger.triggerType is set to "now", one preamble as + //!< configured in the setup will be sent. Otherwise, the preamble will be repeated until + //!< this trigger is observed. + uint32_t syncWord; //!< Sync word to transmit + uint8_t* pPkt; //!< Pointer to packet, or TX queue for unlimited length } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_RX_ADV //! @{ -#define CMD_PROP_RX_ADV 0x3804 +#define CMD_PROP_RX_ADV 0x3804 //! Proprietary Mode Advanced Receive Command struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_s { - uint16_t commandNo; //!< The command ID number 0x3804 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bRepeatOk: 1; //!< \brief 0: End operation after receiving a packet correctly
- //!< 1: Go back to sync search after receiving a packet correctly - uint8_t bRepeatNok: 1; //!< \brief 0: End operation after receiving a packet with CRC error
- //!< 1: Go back to sync search after receiving a packet with CRC error - uint8_t bUseCrc: 1; //!< \brief 0: Do not check CRC
- //!< 1: Check CRC - uint8_t bCrcIncSw: 1; //!< \brief 0: Do not include sync word in CRC calculation
- //!< 1: Include sync word in CRC calculation - uint8_t bCrcIncHdr: 1; //!< \brief 0: Do not include header in CRC calculation
- //!< 1: Include header in CRC calculation - uint8_t endType: 1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
- //!< 1: Packet reception is stopped if end trigger happens - uint8_t filterOp: 1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
- //!< 1: Receive packet and mark it as ignored on address mismatch - } pktConf; - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically discard ignored packets from RX queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically discard packets with CRC error from RX queue - uint8_t : 1; - uint8_t bIncludeHdr: 1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the RX queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the RX queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the RX queue - } rxConf; //!< RX configuration - uint32_t syncWord0; //!< Sync word to listen for - uint32_t syncWord1; //!< Alternative sync word if non-zero - uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
- //!< 0: Unlimited or unknown length - struct - { - uint16_t numHdrBits: 6; //!< Number of bits in header (0--32) - uint16_t lenPos: 5; //!< Position of length field in header (0--31) - uint16_t numLenBits: 5; //!< Number of bits in length field (0--16) - } hdrConf; - struct - { - uint16_t addrType: 1; //!< \brief 0: Address after header
- //!< 1: Address in header - uint16_t addrSize: 5; //!< \brief If addrType = 0: Address size in bytes
- //!< If addrType = 1: Address size in bits - uint16_t addrPos: 5; //!< \brief If addrType = 1: Bit position of address in header
- //!< If addrType = 0: Non-zero to extend address with sync word identifier - uint16_t numAddr: 5; //!< Number of addresses in address list - } addrConf; - int8_t lenOffset; //!< Signed value to add to length field - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - ratmr_t endTime; //!< Time used together with endTrigger for ending the operation - uint8_t* pAddr; //!< Pointer to address list - dataQueue_t* pQueue; //!< Pointer to receive queue - uint8_t* pOutput; //!< Pointer to output structure + uint16_t commandNo; //!< The command ID number 0x3804 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk : 1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok : 1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc : 1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bCrcIncSw : 1; //!< \brief 0: Do not include sync word in CRC calculation
+ //!< 1: Include sync word in CRC calculation + uint8_t bCrcIncHdr : 1; //!< \brief 0: Do not include header in CRC calculation
+ //!< 1: Include header in CRC calculation + uint8_t endType : 1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp : 1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t : 1; + uint8_t bIncludeHdr : 1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord0; //!< Sync word to listen for + uint32_t syncWord1; //!< Alternative sync word if non-zero + uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + struct + { + uint16_t numHdrBits : 6; //!< Number of bits in header (0--32) + uint16_t lenPos : 5; //!< Position of length field in header (0--31) + uint16_t numLenBits : 5; //!< Number of bits in length field (0--16) + } hdrConf; + struct + { + uint16_t addrType : 1; //!< \brief 0: Address after header
+ //!< 1: Address in header + uint16_t addrSize : 5; //!< \brief If addrType = 0: Address size in bytes
+ //!< If addrType = 1: Address size in bits + uint16_t addrPos : 5; //!< \brief If addrType = 1: Bit position of address in header
+ //!< If addrType = 0: Non-zero to extend address with sync word identifier + uint16_t numAddr : 5; //!< Number of addresses in address list + } addrConf; + int8_t lenOffset; //!< Signed value to add to length field + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + uint8_t* pAddr; //!< Pointer to address list + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_CS //! @{ -#define CMD_PROP_CS 0x3805 +#define CMD_PROP_CS 0x3805 //! Carrier Sense Command struct __RFC_STRUCT rfc_CMD_PROP_CS_s { - uint16_t commandNo; //!< The command ID number 0x3805 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOffIdle: 1; //!< \brief 0: Keep synth running if command ends with channel Idle
- //!< 1: Turn off synth if command ends with channel Idle - uint8_t bFsOffBusy: 1; //!< \brief 0: Keep synth running if command ends with channel Busy
- //!< 1: Turn off synth if command ends with channel Busy - } csFsConf; - uint8_t __dummy0; - struct - { - uint8_t bEnaRssi: 1; //!< If 1, enable RSSI as a criterion - uint8_t bEnaCorr: 1; //!< If 1, enable correlation as a criterion - uint8_t operation: 1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
- //!< 1: Busy if both RSSI and correlation indicates Busy - uint8_t busyOp: 1; //!< \brief 0: Continue carrier sense on channel Busy
- //!< 1: End carrier sense on channel Busy
- //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle - uint8_t idleOp: 1; //!< \brief 0: Continue on channel Idle
- //!< 1: End on channel Idle - uint8_t timeoutRes: 1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
- //!< 1: Timeout with channel state Invalid treated as Idle - } csConf; - int8_t rssiThr; //!< RSSI threshold - uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is - //!< declared Idle - uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is - //!< declared Busy - uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods - struct - { - uint8_t numCorrInv: 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Idle to Invalid - uint8_t numCorrBusy: 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Invalid to Busy - } corrConfig; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } csEndTrigger; //!< Trigger classifier for ending the carrier sense - ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation + uint16_t commandNo; //!< The command ID number 0x3805 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOffIdle : 1; //!< \brief 0: Keep synth running if command ends with channel Idle
+ //!< 1: Turn off synth if command ends with channel Idle + uint8_t bFsOffBusy : 1; //!< \brief 0: Keep synth running if command ends with channel Busy
+ //!< 1: Turn off synth if command ends with channel Busy + } csFsConf; + uint8_t __dummy0; + struct + { + uint8_t bEnaRssi : 1; //!< If 1, enable RSSI as a criterion + uint8_t bEnaCorr : 1; //!< If 1, enable correlation as a criterion + uint8_t operation : 1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
+ //!< 1: Busy if both RSSI and correlation indicates Busy + uint8_t busyOp : 1; //!< \brief 0: Continue carrier sense on channel Busy
+ //!< 1: End carrier sense on channel Busy
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle + uint8_t idleOp : 1; //!< \brief 0: Continue on channel Idle
+ //!< 1: End on channel Idle + uint8_t timeoutRes : 1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
+ //!< 1: Timeout with channel state Invalid treated as Idle + } csConf; + int8_t rssiThr; //!< RSSI threshold + uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is + //!< declared Idle + uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is + //!< declared Busy + uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods + struct + { + uint8_t numCorrInv : 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Idle to Invalid + uint8_t numCorrBusy : 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Invalid to Busy + } corrConfig; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } csEndTrigger; //!< Trigger classifier for ending the carrier sense + ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_RADIO_SETUP //! @{ -#define CMD_PROP_RADIO_SETUP 0x3806 +#define CMD_PROP_RADIO_SETUP 0x3806 //! Proprietary Mode Radio Setup Command for 2.4 GHz struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_s { - uint16_t commandNo; //!< The command ID number 0x3806 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint16_t modType: 3; //!< \brief 0: FSK
- //!< 1: GFSK
- //!< 2: OOK
- //!< Others: Reserved - uint16_t deviation: 11; //!< Deviation (specified in number of steps, with step size given by deviationStepSz) - uint16_t deviationStepSz: 2; //!< \brief Deviation step size
- //!< 0: 250 Hz
- //!< 1: 1000 Hz
- //!< 2: 15.625 Hz
- //!< 3: 62.5 Hz - } modulation; - struct - { - uint32_t preScale: 8; //!< Prescaler value - uint32_t rateWord: 21; //!< Rate word - uint32_t decimMode: 3; //!< \brief 0: Use automatic PDIF decimation
- //!< 1: Force PDIF decimation to 0
- //!< 3: Force PDIF decimation to 1
- //!< 5: Force PDIF decimation to 2
- //!< Others: Reserved - } symbolRate; //!< Symbol rate setting - uint8_t rxBw; //!< Receiver bandwidth - struct - { - uint8_t nPreamBytes: 6; //!< \brief 0: 1 preamble bit
- //!< 1--16: Number of preamble bytes
- //!< 18, 20, ..., 30: Number of preamble bytes
- //!< 31: 4 preamble bits
- //!< 32: 32 preamble bytes
- //!< Others: Reserved - uint8_t preamMode: 2; //!< \brief 0: Send 0 as the first preamble bit
- //!< 1: Send 1 as the first preamble bit
- //!< 2: Send same first bit in preamble and sync word
- //!< 3: Send different first bit in preamble and sync word - } preamConf; - struct - { - uint16_t nSwBits: 6; //!< Number of sync word bits (8--32) - uint16_t bBitReversal: 1; //!< \brief 0: Use positive deviation for 1
- //!< 1: Use positive deviation for 0 - uint16_t bMsbFirst: 1; //!< \brief 0: Least significant bit transmitted first
- //!< 1: Most significant bit transmitted first - uint16_t fecMode: 4; //!< \brief Select coding
- //!< 0: Uncoded binary modulation
- //!< 10: Manchester coded binary modulation
- //!< Others: Reserved - uint16_t : 1; - uint16_t whitenMode: 3; //!< \brief 0: No whitening
- //!< 1: CC1101/CC2500 compatible whitening
- //!< 2: PN9 whitening without byte reversal
- //!< 3: Reserved
- //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
- //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
- //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
- //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC - } formatConf; - struct - { - uint16_t frontEndMode: 3; //!< \brief 0x00: Differential mode
- //!< 0x01: Single-ended mode RFP
- //!< 0x02: Single-ended mode RFN
- //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
- //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
- //!< Others: Reserved - uint16_t biasMode: 1; //!< \brief 0: Internal bias
- //!< 1: External bias - uint16_t analogCfgMode: 6; //!< \brief 0x00: Write analog configuration.
- //!< Required first time after boot and when changing frequency band - //!< or front-end configuration
- //!< 0x2D: Keep analog configuration.
- //!< May be used after standby or when changing mode with the same frequency - //!< band and front-end configuration
- //!< Others: Reserved - uint16_t bNoFsPowerUp: 1; //!< \brief 0: Power up frequency synth
- //!< 1: Do not power up frequency synth - } config; //!< Configuration options - uint16_t txPower; //!< Transmit power - uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no - //!< override is used. + uint16_t commandNo; //!< The command ID number 0x3806 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint16_t modType : 3; //!< \brief 0: FSK
+ //!< 1: GFSK
+ //!< 2: OOK
+ //!< Others: Reserved + uint16_t deviation : 11; //!< Deviation (specified in number of steps, with step size given by deviationStepSz) + uint16_t deviationStepSz : 2; //!< \brief Deviation step size
+ //!< 0: 250 Hz
+ //!< 1: 1000 Hz
+ //!< 2: 15.625 Hz
+ //!< 3: 62.5 Hz + } modulation; + struct + { + uint32_t preScale : 8; //!< Prescaler value + uint32_t rateWord : 21; //!< Rate word + uint32_t decimMode : 3; //!< \brief 0: Use automatic PDIF decimation
+ //!< 1: Force PDIF decimation to 0
+ //!< 3: Force PDIF decimation to 1
+ //!< 5: Force PDIF decimation to 2
+ //!< Others: Reserved + } symbolRate; //!< Symbol rate setting + uint8_t rxBw; //!< Receiver bandwidth + struct + { + uint8_t nPreamBytes : 6; //!< \brief 0: 1 preamble bit
+ //!< 1--16: Number of preamble bytes
+ //!< 18, 20, ..., 30: Number of preamble bytes
+ //!< 31: 4 preamble bits
+ //!< 32: 32 preamble bytes
+ //!< Others: Reserved + uint8_t preamMode : 2; //!< \brief 0: Send 0 as the first preamble bit
+ //!< 1: Send 1 as the first preamble bit
+ //!< 2: Send same first bit in preamble and sync word
+ //!< 3: Send different first bit in preamble and sync word + } preamConf; + struct + { + uint16_t nSwBits : 6; //!< Number of sync word bits (8--32) + uint16_t bBitReversal : 1; //!< \brief 0: Use positive deviation for 1
+ //!< 1: Use positive deviation for 0 + uint16_t bMsbFirst : 1; //!< \brief 0: Least significant bit transmitted first
+ //!< 1: Most significant bit transmitted first + uint16_t fecMode : 4; //!< \brief Select coding
+ //!< 0: Uncoded binary modulation
+ //!< 10: Manchester coded binary modulation
+ //!< Others: Reserved + uint16_t : 1; + uint16_t whitenMode : 3; //!< \brief 0: No whitening
+ //!< 1: CC1101/CC2500 compatible whitening
+ //!< 2: PN9 whitening without byte reversal
+ //!< 3: Reserved
+ //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
+ //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
+ //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
+ //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC + } formatConf; + struct + { + uint16_t frontEndMode : 3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode : 1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode : 6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp : 1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_RADIO_DIV_SETUP //! @{ -#define CMD_PROP_RADIO_DIV_SETUP 0x3807 +#define CMD_PROP_RADIO_DIV_SETUP 0x3807 //! Proprietary Mode Radio Setup Command for All Frequency Bands struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_s { - uint16_t commandNo; //!< The command ID number 0x3807 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint16_t modType: 3; //!< \brief 0: FSK
- //!< 1: GFSK
- //!< 2: OOK
- //!< Others: Reserved - uint16_t deviation: 11; //!< Deviation (specified in number of steps, with step size given by deviationStepSz) - uint16_t deviationStepSz: 2; //!< \brief Deviation step size
- //!< 0: 250 Hz
- //!< 1: 1000 Hz
- //!< 2: 15.625 Hz
- //!< 3: 62.5 Hz - } modulation; - struct - { - uint32_t preScale: 8; //!< Prescaler value - uint32_t rateWord: 21; //!< Rate word - uint32_t decimMode: 3; //!< \brief 0: Use automatic PDIF decimation
- //!< 1: Force PDIF decimation to 0
- //!< 3: Force PDIF decimation to 1
- //!< 5: Force PDIF decimation to 2
- //!< Others: Reserved - } symbolRate; //!< Symbol rate setting - uint8_t rxBw; //!< Receiver bandwidth - struct - { - uint8_t nPreamBytes: 6; //!< \brief 0: 1 preamble bit
- //!< 1--16: Number of preamble bytes
- //!< 18, 20, ..., 30: Number of preamble bytes
- //!< 31: 4 preamble bits
- //!< 32: 32 preamble bytes
- //!< Others: Reserved - uint8_t preamMode: 2; //!< \brief 0: Send 0 as the first preamble bit
- //!< 1: Send 1 as the first preamble bit
- //!< 2: Send same first bit in preamble and sync word
- //!< 3: Send different first bit in preamble and sync word - } preamConf; - struct - { - uint16_t nSwBits: 6; //!< Number of sync word bits (8--32) - uint16_t bBitReversal: 1; //!< \brief 0: Use positive deviation for 1
- //!< 1: Use positive deviation for 0 - uint16_t bMsbFirst: 1; //!< \brief 0: Least significant bit transmitted first
- //!< 1: Most significant bit transmitted first - uint16_t fecMode: 4; //!< \brief Select coding
- //!< 0: Uncoded binary modulation
- //!< 10: Manchester coded binary modulation
- //!< Others: Reserved - uint16_t : 1; - uint16_t whitenMode: 3; //!< \brief 0: No whitening
- //!< 1: CC1101/CC2500 compatible whitening
- //!< 2: PN9 whitening without byte reversal
- //!< 3: Reserved
- //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
- //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
- //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
- //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC - } formatConf; - struct - { - uint16_t frontEndMode: 3; //!< \brief 0x00: Differential mode
- //!< 0x01: Single-ended mode RFP
- //!< 0x02: Single-ended mode RFN
- //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
- //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
- //!< Others: Reserved - uint16_t biasMode: 1; //!< \brief 0: Internal bias
- //!< 1: External bias - uint16_t analogCfgMode: 6; //!< \brief 0x00: Write analog configuration.
- //!< Required first time after boot and when changing frequency band - //!< or front-end configuration
- //!< 0x2D: Keep analog configuration.
- //!< May be used after standby or when changing mode with the same frequency - //!< band and front-end configuration
- //!< Others: Reserved - uint16_t bNoFsPowerUp: 1; //!< \brief 0: Power up frequency synth
- //!< 1: Do not power up frequency synth - } config; //!< Configuration options - uint16_t txPower; //!< Transmit power - uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no - //!< override is used. - uint16_t centerFreq; //!< \brief Center frequency of the frequency band used, in MHz; used for calculating some internal TX and RX parameters. - //!< For a single channel RF system, this should be set equal to the RF frequency used. - //!< For a multi channel RF system (e.g. frequency hopping spread spectrum), this should be set equal - //!< to the center frequency of the frequency band used. - int16_t intFreq; //!< \brief Intermediate frequency to use for RX, in MHz on 4.12 signed format. TX will use same - //!< intermediate frequency if supported, otherwise 0.
- //!< 0x8000: Use default. - uint8_t loDivider; //!< LO frequency divider setting to use. Supported values: 0, 2, 4, 5, 6, 10, 12, 15, and 30 + uint16_t commandNo; //!< The command ID number 0x3807 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint16_t modType : 3; //!< \brief 0: FSK
+ //!< 1: GFSK
+ //!< 2: OOK
+ //!< Others: Reserved + uint16_t deviation : 11; //!< Deviation (specified in number of steps, with step size given by deviationStepSz) + uint16_t deviationStepSz : 2; //!< \brief Deviation step size
+ //!< 0: 250 Hz
+ //!< 1: 1000 Hz
+ //!< 2: 15.625 Hz
+ //!< 3: 62.5 Hz + } modulation; + struct + { + uint32_t preScale : 8; //!< Prescaler value + uint32_t rateWord : 21; //!< Rate word + uint32_t decimMode : 3; //!< \brief 0: Use automatic PDIF decimation
+ //!< 1: Force PDIF decimation to 0
+ //!< 3: Force PDIF decimation to 1
+ //!< 5: Force PDIF decimation to 2
+ //!< Others: Reserved + } symbolRate; //!< Symbol rate setting + uint8_t rxBw; //!< Receiver bandwidth + struct + { + uint8_t nPreamBytes : 6; //!< \brief 0: 1 preamble bit
+ //!< 1--16: Number of preamble bytes
+ //!< 18, 20, ..., 30: Number of preamble bytes
+ //!< 31: 4 preamble bits
+ //!< 32: 32 preamble bytes
+ //!< Others: Reserved + uint8_t preamMode : 2; //!< \brief 0: Send 0 as the first preamble bit
+ //!< 1: Send 1 as the first preamble bit
+ //!< 2: Send same first bit in preamble and sync word
+ //!< 3: Send different first bit in preamble and sync word + } preamConf; + struct + { + uint16_t nSwBits : 6; //!< Number of sync word bits (8--32) + uint16_t bBitReversal : 1; //!< \brief 0: Use positive deviation for 1
+ //!< 1: Use positive deviation for 0 + uint16_t bMsbFirst : 1; //!< \brief 0: Least significant bit transmitted first
+ //!< 1: Most significant bit transmitted first + uint16_t fecMode : 4; //!< \brief Select coding
+ //!< 0: Uncoded binary modulation
+ //!< 10: Manchester coded binary modulation
+ //!< Others: Reserved + uint16_t : 1; + uint16_t whitenMode : 3; //!< \brief 0: No whitening
+ //!< 1: CC1101/CC2500 compatible whitening
+ //!< 2: PN9 whitening without byte reversal
+ //!< 3: Reserved
+ //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
+ //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
+ //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
+ //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC + } formatConf; + struct + { + uint16_t frontEndMode : 3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode : 1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode : 6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp : 1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. + uint16_t centerFreq; //!< \brief Center frequency of the frequency band used, in MHz; used for calculating some internal TX and RX parameters. + //!< For a single channel RF system, this should be set equal to the RF frequency used. + //!< For a multi channel RF system (e.g. frequency hopping spread spectrum), this should be set equal + //!< to the center frequency of the frequency band used. + int16_t intFreq; //!< \brief Intermediate frequency to use for RX, in MHz on 4.12 signed format. TX will use same + //!< intermediate frequency if supported, otherwise 0.
+ //!< 0x8000: Use default. + uint8_t loDivider; //!< LO frequency divider setting to use. Supported values: 0, 2, 4, 5, 6, 10, 12, 15, and 30 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_RX_SNIFF //! @{ -#define CMD_PROP_RX_SNIFF 0x3808 +#define CMD_PROP_RX_SNIFF 0x3808 //! Proprietary Mode Receive Command with Sniff Mode struct __RFC_STRUCT rfc_CMD_PROP_RX_SNIFF_s { - uint16_t commandNo; //!< The command ID number 0x3808 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bRepeatOk: 1; //!< \brief 0: End operation after receiving a packet correctly
- //!< 1: Go back to sync search after receiving a packet correctly - uint8_t bRepeatNok: 1; //!< \brief 0: End operation after receiving a packet with CRC error
- //!< 1: Go back to sync search after receiving a packet with CRC error - uint8_t bUseCrc: 1; //!< \brief 0: Do not check CRC
- //!< 1: Check CRC - uint8_t bVarLen: 1; //!< \brief 0: Fixed length
- //!< 1: Receive length as first byte - uint8_t bChkAddress: 1; //!< \brief 0: No address check
- //!< 1: Check address - uint8_t endType: 1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
- //!< 1: Packet reception is stopped if end trigger happens - uint8_t filterOp: 1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
- //!< 1: Receive packet and mark it as ignored on address mismatch - } pktConf; - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically discard ignored packets from RX queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically discard packets with CRC error from RX queue - uint8_t : 1; - uint8_t bIncludeHdr: 1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the RX queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the RX queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the RX queue - } rxConf; //!< RX configuration - uint32_t syncWord; //!< Sync word to listen for - uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
- //!< 0: Unlimited or unknown length - uint8_t address0; //!< Address - uint8_t address1; //!< \brief Address (set equal to address0 to accept only one address. If 0xFF, accept - //!< 0x00 as well) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - ratmr_t endTime; //!< Time used together with endTrigger for ending the operation - dataQueue_t* pQueue; //!< Pointer to receive queue - uint8_t* pOutput; //!< Pointer to output structure - struct - { - uint8_t bEnaRssi: 1; //!< If 1, enable RSSI as a criterion - uint8_t bEnaCorr: 1; //!< If 1, enable correlation as a criterion - uint8_t operation: 1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
- //!< 1: Busy if both RSSI and correlation indicates Busy - uint8_t busyOp: 1; //!< \brief 0: Continue carrier sense on channel Busy
- //!< 1: End carrier sense on channel Busy
- //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle - uint8_t idleOp: 1; //!< \brief 0: Continue on channel Idle
- //!< 1: End on channel Idle - uint8_t timeoutRes: 1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
- //!< 1: Timeout with channel state Invalid treated as Idle - } csConf; - int8_t rssiThr; //!< RSSI threshold - uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is - //!< declared Idle - uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is - //!< declared Busy - uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods - struct - { - uint8_t numCorrInv: 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Idle to Invalid - uint8_t numCorrBusy: 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Invalid to Busy - } corrConfig; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } csEndTrigger; //!< Trigger classifier for ending the carrier sense - ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation + uint16_t commandNo; //!< The command ID number 0x3808 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk : 1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok : 1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc : 1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bVarLen : 1; //!< \brief 0: Fixed length
+ //!< 1: Receive length as first byte + uint8_t bChkAddress : 1; //!< \brief 0: No address check
+ //!< 1: Check address + uint8_t endType : 1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp : 1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t : 1; + uint8_t bIncludeHdr : 1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord; //!< Sync word to listen for + uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + uint8_t address0; //!< Address + uint8_t address1; //!< \brief Address (set equal to address0 to accept only one address. If 0xFF, accept + //!< 0x00 as well) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure + struct + { + uint8_t bEnaRssi : 1; //!< If 1, enable RSSI as a criterion + uint8_t bEnaCorr : 1; //!< If 1, enable correlation as a criterion + uint8_t operation : 1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
+ //!< 1: Busy if both RSSI and correlation indicates Busy + uint8_t busyOp : 1; //!< \brief 0: Continue carrier sense on channel Busy
+ //!< 1: End carrier sense on channel Busy
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle + uint8_t idleOp : 1; //!< \brief 0: Continue on channel Idle
+ //!< 1: End on channel Idle + uint8_t timeoutRes : 1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
+ //!< 1: Timeout with channel state Invalid treated as Idle + } csConf; + int8_t rssiThr; //!< RSSI threshold + uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is + //!< declared Idle + uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is + //!< declared Busy + uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods + struct + { + uint8_t numCorrInv : 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Idle to Invalid + uint8_t numCorrBusy : 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Invalid to Busy + } corrConfig; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } csEndTrigger; //!< Trigger classifier for ending the carrier sense + ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_RX_ADV_SNIFF //! @{ -#define CMD_PROP_RX_ADV_SNIFF 0x3809 +#define CMD_PROP_RX_ADV_SNIFF 0x3809 //! Proprietary Mode Advanced Receive Command with Sniff Mode struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_SNIFF_s { - uint16_t commandNo; //!< The command ID number 0x3809 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bRepeatOk: 1; //!< \brief 0: End operation after receiving a packet correctly
- //!< 1: Go back to sync search after receiving a packet correctly - uint8_t bRepeatNok: 1; //!< \brief 0: End operation after receiving a packet with CRC error
- //!< 1: Go back to sync search after receiving a packet with CRC error - uint8_t bUseCrc: 1; //!< \brief 0: Do not check CRC
- //!< 1: Check CRC - uint8_t bCrcIncSw: 1; //!< \brief 0: Do not include sync word in CRC calculation
- //!< 1: Include sync word in CRC calculation - uint8_t bCrcIncHdr: 1; //!< \brief 0: Do not include header in CRC calculation
- //!< 1: Include header in CRC calculation - uint8_t endType: 1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
- //!< 1: Packet reception is stopped if end trigger happens - uint8_t filterOp: 1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
- //!< 1: Receive packet and mark it as ignored on address mismatch - } pktConf; - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically discard ignored packets from RX queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically discard packets with CRC error from RX queue - uint8_t : 1; - uint8_t bIncludeHdr: 1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the RX queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the RX queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the RX queue - } rxConf; //!< RX configuration - uint32_t syncWord0; //!< Sync word to listen for - uint32_t syncWord1; //!< Alternative sync word if non-zero - uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
- //!< 0: Unlimited or unknown length - struct - { - uint16_t numHdrBits: 6; //!< Number of bits in header (0--32) - uint16_t lenPos: 5; //!< Position of length field in header (0--31) - uint16_t numLenBits: 5; //!< Number of bits in length field (0--16) - } hdrConf; - struct - { - uint16_t addrType: 1; //!< \brief 0: Address after header
- //!< 1: Address in header - uint16_t addrSize: 5; //!< \brief If addrType = 0: Address size in bytes
- //!< If addrType = 1: Address size in bits - uint16_t addrPos: 5; //!< \brief If addrType = 1: Bit position of address in header
- //!< If addrType = 0: Non-zero to extend address with sync word identifier - uint16_t numAddr: 5; //!< Number of addresses in address list - } addrConf; - int8_t lenOffset; //!< Signed value to add to length field - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - ratmr_t endTime; //!< Time used together with endTrigger for ending the operation - uint8_t* pAddr; //!< Pointer to address list - dataQueue_t* pQueue; //!< Pointer to receive queue - uint8_t* pOutput; //!< Pointer to output structure - struct - { - uint8_t bEnaRssi: 1; //!< If 1, enable RSSI as a criterion - uint8_t bEnaCorr: 1; //!< If 1, enable correlation as a criterion - uint8_t operation: 1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
- //!< 1: Busy if both RSSI and correlation indicates Busy - uint8_t busyOp: 1; //!< \brief 0: Continue carrier sense on channel Busy
- //!< 1: End carrier sense on channel Busy
- //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle - uint8_t idleOp: 1; //!< \brief 0: Continue on channel Idle
- //!< 1: End on channel Idle - uint8_t timeoutRes: 1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
- //!< 1: Timeout with channel state Invalid treated as Idle - } csConf; - int8_t rssiThr; //!< RSSI threshold - uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is - //!< declared Idle - uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is - //!< declared Busy - uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods - struct - { - uint8_t numCorrInv: 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Idle to Invalid - uint8_t numCorrBusy: 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Invalid to Busy - } corrConfig; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } csEndTrigger; //!< Trigger classifier for ending the carrier sense - ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation + uint16_t commandNo; //!< The command ID number 0x3809 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk : 1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok : 1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc : 1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bCrcIncSw : 1; //!< \brief 0: Do not include sync word in CRC calculation
+ //!< 1: Include sync word in CRC calculation + uint8_t bCrcIncHdr : 1; //!< \brief 0: Do not include header in CRC calculation
+ //!< 1: Include header in CRC calculation + uint8_t endType : 1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp : 1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t : 1; + uint8_t bIncludeHdr : 1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord0; //!< Sync word to listen for + uint32_t syncWord1; //!< Alternative sync word if non-zero + uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + struct + { + uint16_t numHdrBits : 6; //!< Number of bits in header (0--32) + uint16_t lenPos : 5; //!< Position of length field in header (0--31) + uint16_t numLenBits : 5; //!< Number of bits in length field (0--16) + } hdrConf; + struct + { + uint16_t addrType : 1; //!< \brief 0: Address after header
+ //!< 1: Address in header + uint16_t addrSize : 5; //!< \brief If addrType = 0: Address size in bytes
+ //!< If addrType = 1: Address size in bits + uint16_t addrPos : 5; //!< \brief If addrType = 1: Bit position of address in header
+ //!< If addrType = 0: Non-zero to extend address with sync word identifier + uint16_t numAddr : 5; //!< Number of addresses in address list + } addrConf; + int8_t lenOffset; //!< Signed value to add to length field + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + uint8_t* pAddr; //!< Pointer to address list + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure + struct + { + uint8_t bEnaRssi : 1; //!< If 1, enable RSSI as a criterion + uint8_t bEnaCorr : 1; //!< If 1, enable correlation as a criterion + uint8_t operation : 1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
+ //!< 1: Busy if both RSSI and correlation indicates Busy + uint8_t busyOp : 1; //!< \brief 0: Continue carrier sense on channel Busy
+ //!< 1: End carrier sense on channel Busy
+ //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle + uint8_t idleOp : 1; //!< \brief 0: Continue on channel Idle
+ //!< 1: End on channel Idle + uint8_t timeoutRes : 1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
+ //!< 1: Timeout with channel state Invalid treated as Idle + } csConf; + int8_t rssiThr; //!< RSSI threshold + uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is + //!< declared Idle + uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is + //!< declared Busy + uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods + struct + { + uint8_t numCorrInv : 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Idle to Invalid + uint8_t numCorrBusy : 4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT + //!< ticks between them needed to go from Invalid to Busy + } corrConfig; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } csEndTrigger; //!< Trigger classifier for ending the carrier sense + ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation } __RFC_STRUCT_ATTR; //! @} @@ -966,111 +966,111 @@ struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_SNIFF_s //! Proprietary Mode Radio Setup Command for 2.4 GHz with PA Switching Fields struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_PA_s { - uint16_t commandNo; //!< The command ID number - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint16_t modType: 3; //!< \brief 0: FSK
- //!< 1: GFSK
- //!< 2: OOK
- //!< Others: Reserved - uint16_t deviation: 11; //!< Deviation (specified in number of steps, with step size given by deviationStepSz) - uint16_t deviationStepSz: 2; //!< \brief Deviation step size
- //!< 0: 250 Hz
- //!< 1: 1000 Hz
- //!< 2: 15.625 Hz
- //!< 3: 62.5 Hz - } modulation; - struct - { - uint32_t preScale: 8; //!< Prescaler value - uint32_t rateWord: 21; //!< Rate word - uint32_t decimMode: 3; //!< \brief 0: Use automatic PDIF decimation
- //!< 1: Force PDIF decimation to 0
- //!< 3: Force PDIF decimation to 1
- //!< 5: Force PDIF decimation to 2
- //!< Others: Reserved - } symbolRate; //!< Symbol rate setting - uint8_t rxBw; //!< Receiver bandwidth - struct - { - uint8_t nPreamBytes: 6; //!< \brief 0: 1 preamble bit
- //!< 1--16: Number of preamble bytes
- //!< 18, 20, ..., 30: Number of preamble bytes
- //!< 31: 4 preamble bits
- //!< 32: 32 preamble bytes
- //!< Others: Reserved - uint8_t preamMode: 2; //!< \brief 0: Send 0 as the first preamble bit
- //!< 1: Send 1 as the first preamble bit
- //!< 2: Send same first bit in preamble and sync word
- //!< 3: Send different first bit in preamble and sync word - } preamConf; - struct - { - uint16_t nSwBits: 6; //!< Number of sync word bits (8--32) - uint16_t bBitReversal: 1; //!< \brief 0: Use positive deviation for 1
- //!< 1: Use positive deviation for 0 - uint16_t bMsbFirst: 1; //!< \brief 0: Least significant bit transmitted first
- //!< 1: Most significant bit transmitted first - uint16_t fecMode: 4; //!< \brief Select coding
- //!< 0: Uncoded binary modulation
- //!< 10: Manchester coded binary modulation
- //!< Others: Reserved - uint16_t : 1; - uint16_t whitenMode: 3; //!< \brief 0: No whitening
- //!< 1: CC1101/CC2500 compatible whitening
- //!< 2: PN9 whitening without byte reversal
- //!< 3: Reserved
- //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
- //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
- //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
- //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC - } formatConf; - struct - { - uint16_t frontEndMode: 3; //!< \brief 0x00: Differential mode
- //!< 0x01: Single-ended mode RFP
- //!< 0x02: Single-ended mode RFN
- //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
- //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
- //!< Others: Reserved - uint16_t biasMode: 1; //!< \brief 0: Internal bias
- //!< 1: External bias - uint16_t analogCfgMode: 6; //!< \brief 0x00: Write analog configuration.
- //!< Required first time after boot and when changing frequency band - //!< or front-end configuration
- //!< 0x2D: Keep analog configuration.
- //!< May be used after standby or when changing mode with the same frequency - //!< band and front-end configuration
- //!< Others: Reserved - uint16_t bNoFsPowerUp: 1; //!< \brief 0: Power up frequency synth
- //!< 1: Do not power up frequency synth - } config; //!< Configuration options - uint16_t txPower; //!< Transmit power - uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no - //!< override is used. - uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to - //!< standard PA. Used by RF driver only, not radio CPU. - uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to - //!< 20-dBm PA. Used by RF driver only, not radio CPU. + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint16_t modType : 3; //!< \brief 0: FSK
+ //!< 1: GFSK
+ //!< 2: OOK
+ //!< Others: Reserved + uint16_t deviation : 11; //!< Deviation (specified in number of steps, with step size given by deviationStepSz) + uint16_t deviationStepSz : 2; //!< \brief Deviation step size
+ //!< 0: 250 Hz
+ //!< 1: 1000 Hz
+ //!< 2: 15.625 Hz
+ //!< 3: 62.5 Hz + } modulation; + struct + { + uint32_t preScale : 8; //!< Prescaler value + uint32_t rateWord : 21; //!< Rate word + uint32_t decimMode : 3; //!< \brief 0: Use automatic PDIF decimation
+ //!< 1: Force PDIF decimation to 0
+ //!< 3: Force PDIF decimation to 1
+ //!< 5: Force PDIF decimation to 2
+ //!< Others: Reserved + } symbolRate; //!< Symbol rate setting + uint8_t rxBw; //!< Receiver bandwidth + struct + { + uint8_t nPreamBytes : 6; //!< \brief 0: 1 preamble bit
+ //!< 1--16: Number of preamble bytes
+ //!< 18, 20, ..., 30: Number of preamble bytes
+ //!< 31: 4 preamble bits
+ //!< 32: 32 preamble bytes
+ //!< Others: Reserved + uint8_t preamMode : 2; //!< \brief 0: Send 0 as the first preamble bit
+ //!< 1: Send 1 as the first preamble bit
+ //!< 2: Send same first bit in preamble and sync word
+ //!< 3: Send different first bit in preamble and sync word + } preamConf; + struct + { + uint16_t nSwBits : 6; //!< Number of sync word bits (8--32) + uint16_t bBitReversal : 1; //!< \brief 0: Use positive deviation for 1
+ //!< 1: Use positive deviation for 0 + uint16_t bMsbFirst : 1; //!< \brief 0: Least significant bit transmitted first
+ //!< 1: Most significant bit transmitted first + uint16_t fecMode : 4; //!< \brief Select coding
+ //!< 0: Uncoded binary modulation
+ //!< 10: Manchester coded binary modulation
+ //!< Others: Reserved + uint16_t : 1; + uint16_t whitenMode : 3; //!< \brief 0: No whitening
+ //!< 1: CC1101/CC2500 compatible whitening
+ //!< 2: PN9 whitening without byte reversal
+ //!< 3: Reserved
+ //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
+ //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
+ //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
+ //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC + } formatConf; + struct + { + uint16_t frontEndMode : 3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode : 1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode : 6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp : 1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. + uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< standard PA. Used by RF driver only, not radio CPU. + uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< 20-dBm PA. Used by RF driver only, not radio CPU. } __RFC_STRUCT_ATTR; //! @} @@ -1080,144 +1080,144 @@ struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_PA_s //! Proprietary Mode Radio Setup Command for All Frequency Bands with PA Switching Fields struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_PA_s { - uint16_t commandNo; //!< The command ID number - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint16_t modType: 3; //!< \brief 0: FSK
- //!< 1: GFSK
- //!< 2: OOK
- //!< Others: Reserved - uint16_t deviation: 11; //!< Deviation (specified in number of steps, with step size given by deviationStepSz) - uint16_t deviationStepSz: 2; //!< \brief Deviation step size
- //!< 0: 250 Hz
- //!< 1: 1000 Hz
- //!< 2: 15.625 Hz
- //!< 3: 62.5 Hz - } modulation; - struct - { - uint32_t preScale: 8; //!< Prescaler value - uint32_t rateWord: 21; //!< Rate word - uint32_t decimMode: 3; //!< \brief 0: Use automatic PDIF decimation
- //!< 1: Force PDIF decimation to 0
- //!< 3: Force PDIF decimation to 1
- //!< 5: Force PDIF decimation to 2
- //!< Others: Reserved - } symbolRate; //!< Symbol rate setting - uint8_t rxBw; //!< Receiver bandwidth - struct - { - uint8_t nPreamBytes: 6; //!< \brief 0: 1 preamble bit
- //!< 1--16: Number of preamble bytes
- //!< 18, 20, ..., 30: Number of preamble bytes
- //!< 31: 4 preamble bits
- //!< 32: 32 preamble bytes
- //!< Others: Reserved - uint8_t preamMode: 2; //!< \brief 0: Send 0 as the first preamble bit
- //!< 1: Send 1 as the first preamble bit
- //!< 2: Send same first bit in preamble and sync word
- //!< 3: Send different first bit in preamble and sync word - } preamConf; - struct - { - uint16_t nSwBits: 6; //!< Number of sync word bits (8--32) - uint16_t bBitReversal: 1; //!< \brief 0: Use positive deviation for 1
- //!< 1: Use positive deviation for 0 - uint16_t bMsbFirst: 1; //!< \brief 0: Least significant bit transmitted first
- //!< 1: Most significant bit transmitted first - uint16_t fecMode: 4; //!< \brief Select coding
- //!< 0: Uncoded binary modulation
- //!< 10: Manchester coded binary modulation
- //!< Others: Reserved - uint16_t : 1; - uint16_t whitenMode: 3; //!< \brief 0: No whitening
- //!< 1: CC1101/CC2500 compatible whitening
- //!< 2: PN9 whitening without byte reversal
- //!< 3: Reserved
- //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
- //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
- //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
- //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC - } formatConf; - struct - { - uint16_t frontEndMode: 3; //!< \brief 0x00: Differential mode
- //!< 0x01: Single-ended mode RFP
- //!< 0x02: Single-ended mode RFN
- //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
- //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
- //!< Others: Reserved - uint16_t biasMode: 1; //!< \brief 0: Internal bias
- //!< 1: External bias - uint16_t analogCfgMode: 6; //!< \brief 0x00: Write analog configuration.
- //!< Required first time after boot and when changing frequency band - //!< or front-end configuration
- //!< 0x2D: Keep analog configuration.
- //!< May be used after standby or when changing mode with the same frequency - //!< band and front-end configuration
- //!< Others: Reserved - uint16_t bNoFsPowerUp: 1; //!< \brief 0: Power up frequency synth
- //!< 1: Do not power up frequency synth - } config; //!< Configuration options - uint16_t txPower; //!< Transmit power - uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no - //!< override is used. - uint16_t centerFreq; //!< \brief Center frequency of the frequency band used, in MHz; used for calculating some internal TX and RX parameters. - //!< For a single channel RF system, this should be set equal to the RF frequency used. - //!< For a multi channel RF system (e.g. frequency hopping spread spectrum), this should be set equal - //!< to the center frequency of the frequency band used. - int16_t intFreq; //!< \brief Intermediate frequency to use for RX, in MHz on 4.12 signed format. TX will use same - //!< intermediate frequency if supported, otherwise 0.
- //!< 0x8000: Use default. - uint8_t loDivider; //!< LO frequency divider setting to use. Supported values: 0, 2, 4, 5, 6, 10, 12, 15, and 30 - uint8_t __dummy0; - uint16_t __dummy1; - uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to - //!< standard PA. Used by RF driver only, not radio CPU. - uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to - //!< 20-dBm PA. Used by RF driver only, not radio CPU. + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint16_t modType : 3; //!< \brief 0: FSK
+ //!< 1: GFSK
+ //!< 2: OOK
+ //!< Others: Reserved + uint16_t deviation : 11; //!< Deviation (specified in number of steps, with step size given by deviationStepSz) + uint16_t deviationStepSz : 2; //!< \brief Deviation step size
+ //!< 0: 250 Hz
+ //!< 1: 1000 Hz
+ //!< 2: 15.625 Hz
+ //!< 3: 62.5 Hz + } modulation; + struct + { + uint32_t preScale : 8; //!< Prescaler value + uint32_t rateWord : 21; //!< Rate word + uint32_t decimMode : 3; //!< \brief 0: Use automatic PDIF decimation
+ //!< 1: Force PDIF decimation to 0
+ //!< 3: Force PDIF decimation to 1
+ //!< 5: Force PDIF decimation to 2
+ //!< Others: Reserved + } symbolRate; //!< Symbol rate setting + uint8_t rxBw; //!< Receiver bandwidth + struct + { + uint8_t nPreamBytes : 6; //!< \brief 0: 1 preamble bit
+ //!< 1--16: Number of preamble bytes
+ //!< 18, 20, ..., 30: Number of preamble bytes
+ //!< 31: 4 preamble bits
+ //!< 32: 32 preamble bytes
+ //!< Others: Reserved + uint8_t preamMode : 2; //!< \brief 0: Send 0 as the first preamble bit
+ //!< 1: Send 1 as the first preamble bit
+ //!< 2: Send same first bit in preamble and sync word
+ //!< 3: Send different first bit in preamble and sync word + } preamConf; + struct + { + uint16_t nSwBits : 6; //!< Number of sync word bits (8--32) + uint16_t bBitReversal : 1; //!< \brief 0: Use positive deviation for 1
+ //!< 1: Use positive deviation for 0 + uint16_t bMsbFirst : 1; //!< \brief 0: Least significant bit transmitted first
+ //!< 1: Most significant bit transmitted first + uint16_t fecMode : 4; //!< \brief Select coding
+ //!< 0: Uncoded binary modulation
+ //!< 10: Manchester coded binary modulation
+ //!< Others: Reserved + uint16_t : 1; + uint16_t whitenMode : 3; //!< \brief 0: No whitening
+ //!< 1: CC1101/CC2500 compatible whitening
+ //!< 2: PN9 whitening without byte reversal
+ //!< 3: Reserved
+ //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
+ //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
+ //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
+ //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC + } formatConf; + struct + { + uint16_t frontEndMode : 3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode : 1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode : 6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp : 1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< Transmit power + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. + uint16_t centerFreq; //!< \brief Center frequency of the frequency band used, in MHz; used for calculating some internal TX and RX parameters. + //!< For a single channel RF system, this should be set equal to the RF frequency used. + //!< For a multi channel RF system (e.g. frequency hopping spread spectrum), this should be set equal + //!< to the center frequency of the frequency band used. + int16_t intFreq; //!< \brief Intermediate frequency to use for RX, in MHz on 4.12 signed format. TX will use same + //!< intermediate frequency if supported, otherwise 0.
+ //!< 0x8000: Use default. + uint8_t loDivider; //!< LO frequency divider setting to use. Supported values: 0, 2, 4, 5, 6, 10, 12, 15, and 30 + uint8_t __dummy0; + uint16_t __dummy1; + uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< standard PA. Used by RF driver only, not radio CPU. + uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to + //!< 20-dBm PA. Used by RF driver only, not radio CPU. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_SET_LEN //! @{ -#define CMD_PROP_SET_LEN 0x3401 +#define CMD_PROP_SET_LEN 0x3401 //! Set Packet Length Command struct __RFC_STRUCT rfc_CMD_PROP_SET_LEN_s { - uint16_t commandNo; //!< The command ID number 0x3401 - uint16_t rxLen; //!< Payload length to use + uint16_t commandNo; //!< The command ID number 0x3401 + uint16_t rxLen; //!< Payload length to use } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_RESTART_RX //! @{ -#define CMD_PROP_RESTART_RX 0x3402 +#define CMD_PROP_RESTART_RX 0x3402 //! Restart Packet Command struct __RFC_STRUCT rfc_CMD_PROP_RESTART_RX_s { - uint16_t commandNo; //!< The command ID number 0x3402 + uint16_t commandNo; //!< The command ID number 0x3402 } __RFC_STRUCT_ATTR; //! @} @@ -1228,13 +1228,13 @@ struct __RFC_STRUCT rfc_CMD_PROP_RESTART_RX_s struct __RFC_STRUCT rfc_propRxOutput_s { - uint16_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored - uint16_t nRxNok; //!< Number of packets that have been received with CRC error - uint8_t nRxIgnored; //!< Number of packets that have been received with CRC OK and ignored due to address mismatch - uint8_t nRxStopped; //!< Number of packets not received due to illegal length or address mismatch with pktConf.filterOp = 1 - uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space - int8_t lastRssi; //!< RSSI of last received packet - ratmr_t timeStamp; //!< Time stamp of last received packet + uint16_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored + uint16_t nRxNok; //!< Number of packets that have been received with CRC error + uint8_t nRxIgnored; //!< Number of packets that have been received with CRC OK and ignored due to address mismatch + uint8_t nRxStopped; //!< Number of packets not received due to illegal length or address mismatch with pktConf.filterOp = 1 + uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< RSSI of last received packet + ratmr_t timeStamp; //!< Time stamp of last received packet } __RFC_STRUCT_ATTR; //! @} @@ -1245,15 +1245,15 @@ struct __RFC_STRUCT rfc_propRxOutput_s struct __RFC_STRUCT rfc_propRxStatus_s { - struct - { - uint8_t addressInd: 5; //!< Index of address found (0 if not applicable) - uint8_t syncWordId: 1; //!< 0 for primary sync word, 1 for alternate sync word - uint8_t result: 2; //!< \brief 0: Packet received correctly, not ignored
- //!< 1: Packet received with CRC error
- //!< 2: Packet received correctly, but can be ignored
- //!< 3: Packet reception was aborted - } status; + struct + { + uint8_t addressInd : 5; //!< Index of address found (0 if not applicable) + uint8_t syncWordId : 1; //!< 0 for primary sync word, 1 for alternate sync word + uint8_t result : 2; //!< \brief 0: Packet received correctly, not ignored
+ //!< 1: Packet received with CRC error
+ //!< 2: Packet received correctly, but can be ignored
+ //!< 3: Packet reception was aborted + } status; } __RFC_STRUCT_ATTR; //! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_mailbox.h index c6ac409..ef2ff75 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_mailbox.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_mailbox.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_prop_mailbox.h -* Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018) -* Revision: 18171 -* -* Description: Definitions for proprietary mode radio interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_prop_mailbox.h + * Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018) + * Revision: 18171 + * + * Description: Definitions for proprietary mode radio interface + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _PROP_MAILBOX_H #define _PROP_MAILBOX_H @@ -43,28 +43,28 @@ ///@{ /// \name Operation finished normally ///@{ -#define PROP_DONE_OK 0x3400 ///< Operation ended normally -#define PROP_DONE_RXTIMEOUT 0x3401 ///< Operation stopped after end trigger while waiting for sync -#define PROP_DONE_BREAK 0x3402 ///< Rx stopped due to timeout in the middle of a packet -#define PROP_DONE_ENDED 0x3403 ///< Operation stopped after end trigger during reception -#define PROP_DONE_STOPPED 0x3404 ///< Operation stopped after stop command -#define PROP_DONE_ABORT 0x3405 ///< Operation aborted by abort command -#define PROP_DONE_RXERR 0x3406 ///< Operation ended after receiving packet with CRC error -#define PROP_DONE_IDLE 0x3407 ///< Carrier sense operation ended because of idle channel -#define PROP_DONE_BUSY 0x3408 ///< Carrier sense operation ended because of busy channel -#define PROP_DONE_IDLETIMEOUT 0x3409 ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 1 -#define PROP_DONE_BUSYTIMEOUT 0x340A ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 0 +#define PROP_DONE_OK 0x3400 ///< Operation ended normally +#define PROP_DONE_RXTIMEOUT 0x3401 ///< Operation stopped after end trigger while waiting for sync +#define PROP_DONE_BREAK 0x3402 ///< Rx stopped due to timeout in the middle of a packet +#define PROP_DONE_ENDED 0x3403 ///< Operation stopped after end trigger during reception +#define PROP_DONE_STOPPED 0x3404 ///< Operation stopped after stop command +#define PROP_DONE_ABORT 0x3405 ///< Operation aborted by abort command +#define PROP_DONE_RXERR 0x3406 ///< Operation ended after receiving packet with CRC error +#define PROP_DONE_IDLE 0x3407 ///< Carrier sense operation ended because of idle channel +#define PROP_DONE_BUSY 0x3408 ///< Carrier sense operation ended because of busy channel +#define PROP_DONE_IDLETIMEOUT 0x3409 ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 1 +#define PROP_DONE_BUSYTIMEOUT 0x340A ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 0 ///@} /// \name Operation finished with error ///@{ -#define PROP_ERROR_PAR 0x3800 ///< Illegal parameter -#define PROP_ERROR_RXBUF 0x3801 ///< No available Rx buffer at the start of a packet -#define PROP_ERROR_RXFULL 0x3802 ///< Out of Rx buffer during reception in a partial read buffer -#define PROP_ERROR_NO_SETUP 0x3803 ///< Radio was not set up in proprietary mode -#define PROP_ERROR_NO_FS 0x3804 ///< Synth was not programmed when running Rx or Tx -#define PROP_ERROR_RXOVF 0x3805 ///< Rx overflow observed during operation -#define PROP_ERROR_TXUNF 0x3806 ///< Tx underflow observed during operation +#define PROP_ERROR_PAR 0x3800 ///< Illegal parameter +#define PROP_ERROR_RXBUF 0x3801 ///< No available Rx buffer at the start of a packet +#define PROP_ERROR_RXFULL 0x3802 ///< Out of Rx buffer during reception in a partial read buffer +#define PROP_ERROR_NO_SETUP 0x3803 ///< Radio was not set up in proprietary mode +#define PROP_ERROR_NO_FS 0x3804 ///< Synth was not programmed when running Rx or Tx +#define PROP_ERROR_RXOVF 0x3805 ///< Rx overflow observed during operation +#define PROP_ERROR_TXUNF 0x3806 ///< Tx underflow observed during operation ///@} ///@} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.h index 66f21ab..5fd3747 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rfc.h -* Revised: 2018-08-08 14:03:25 +0200 (Wed, 08 Aug 2018) -* Revision: 52338 -* -* Description: Defines and prototypes for the RF Core. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rfc.h + * Revised: 2018-08-08 14:03:25 +0200 (Wed, 08 Aug 2018) + * Revision: 52338 + * + * Description: Defines and prototypes for the RF Core. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -53,41 +53,40 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_rfc_pwr.h" -#include "../inc/hw_rfc_dbell.h" -#include "../inc/hw_fcfg1.h" -#include "../inc/hw_adi_3_refsys.h" #include "../inc/hw_adi.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_fcfg1.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_rfc_dbell.h" +#include "../inc/hw_rfc_pwr.h" +#include "../inc/hw_types.h" +#include "rf_ble_cmd.h" #include "rf_common_cmd.h" #include "rf_prop_cmd.h" -#include "rf_ble_cmd.h" +#include +#include // Definition of RFTRIM container typedef struct { - uint32_t configIfAdc; - uint32_t configRfFrontend; - uint32_t configSynth; - uint32_t configMiscAdc; + uint32_t configIfAdc; + uint32_t configRfFrontend; + uint32_t configSynth; + uint32_t configMiscAdc; } rfTrim_t; // Definition of maximum search depth used by the RFCOverrideUpdate function -#define RFC_MAX_SEARCH_DEPTH 5 -#define RFC_PA_TYPE_ADDRESS 0x21000345 -#define RFC_PA_TYPE_MASK 0x04 -#define RFC_PA_GAIN_ADDRESS 0x2100034C -#define RFC_PA_GAIN_MASK 0x003FFFFF +#define RFC_MAX_SEARCH_DEPTH 5 +#define RFC_PA_TYPE_ADDRESS 0x21000345 +#define RFC_PA_TYPE_MASK 0x04 +#define RFC_PA_GAIN_ADDRESS 0x2100034C +#define RFC_PA_GAIN_MASK 0x003FFFFF #define RFC_FE_MODE_ESCAPE_VALUE 0xFF -#define RFC_FE_OVERRIDE_ADDRESS 0x0703 -#define RFC_FE_OVERRIDE_MASK 0x0000FFFF +#define RFC_FE_OVERRIDE_ADDRESS 0x0703 +#define RFC_FE_OVERRIDE_MASK 0x0000FFFF //***************************************************************************** // @@ -103,14 +102,14 @@ typedef struct // //***************************************************************************** #if !defined(DOXYGEN) -#define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear -#define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo -#define RFCSynthPowerDown NOROM_RFCSynthPowerDown -#define RFCCpePatchReset NOROM_RFCCpePatchReset -#define RFCOverrideSearch NOROM_RFCOverrideSearch -#define RFCOverrideUpdate NOROM_RFCOverrideUpdate -#define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear -#define RFCAnaDivTxOverride NOROM_RFCAnaDivTxOverride +#define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear +#define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo +#define RFCSynthPowerDown NOROM_RFCSynthPowerDown +#define RFCCpePatchReset NOROM_RFCCpePatchReset +#define RFCOverrideSearch NOROM_RFCOverrideSearch +#define RFCOverrideUpdate NOROM_RFCOverrideUpdate +#define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear +#define RFCAnaDivTxOverride NOROM_RFCAnaDivTxOverride #endif //***************************************************************************** @@ -134,12 +133,9 @@ __STATIC_INLINE void RFCClockEnable(void) { // Enable basic clocks to get the CPE run - HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = RFC_PWR_PWMCLKEN_CPERAM - | RFC_PWR_PWMCLKEN_CPE - | RFC_PWR_PWMCLKEN_RFC; + HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = RFC_PWR_PWMCLKEN_CPERAM | RFC_PWR_PWMCLKEN_CPE | RFC_PWR_PWMCLKEN_RFC; } - //***************************************************************************** // //! \brief Disable the RF core clocks. @@ -162,7 +158,6 @@ RFCClockDisable(void) HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = 0x0; } - //***************************************************************************** // //! Clear HW interrupt flags @@ -175,7 +170,6 @@ RFCCpeIntClear(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) = ~ui32Mask; } - //***************************************************************************** // //! Clear CPE interrupt flags. @@ -188,7 +182,6 @@ RFCHwIntClear(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) = ~ui32Mask; } - //***************************************************************************** // //! Select interrupt sources to CPE0 (assign to INT_RFC_CPE_0 interrupt vector). @@ -201,7 +194,6 @@ RFCCpe0IntSelect(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) &= ~ui32Mask; } - //***************************************************************************** // //! Select interrupt sources to CPE1 (assign to INT_RFC_CPE_1 interrupt vector). @@ -214,7 +206,6 @@ RFCCpe1IntSelect(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) |= ui32Mask; } - //***************************************************************************** // //! Enable CPEx interrupt sources. @@ -227,7 +218,6 @@ RFCCpeIntEnable(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) |= ui32Mask; } - //***************************************************************************** // //! Select, clear, and enable interrupt sources to CPE0. @@ -246,7 +236,6 @@ RFCCpe0IntSelectClearEnable(uint32_t ui32Mask) RFCCpeIntEnable(ui32Mask); } - //***************************************************************************** // //! Select, clear, and enable interrupt sources to CPE1. @@ -265,7 +254,6 @@ RFCCpe1IntSelectClearEnable(uint32_t ui32Mask) RFCCpeIntEnable(ui32Mask); } - //***************************************************************************** // //! Enable HW interrupt sources. @@ -278,7 +266,6 @@ RFCHwIntEnable(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) |= ui32Mask; } - //***************************************************************************** // //! Disable CPE interrupt sources. @@ -291,7 +278,6 @@ RFCCpeIntDisable(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) &= ~ui32Mask; } - //***************************************************************************** // //! Disable HW interrupt sources. @@ -304,7 +290,6 @@ RFCHwIntDisable(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) &= ~ui32Mask; } - //***************************************************************************** // //! Get and clear CPE interrupt flags. @@ -312,7 +297,6 @@ RFCHwIntDisable(uint32_t ui32Mask) //***************************************************************************** extern uint32_t RFCCpeIntGetAndClear(uint32_t ui32Mask); - //***************************************************************************** // //! Clear ACK interrupt flag. @@ -325,7 +309,6 @@ RFCAckIntClear(void) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG) = 0x0; } - //***************************************************************************** // //! Send a radio operation to the doorbell and wait for an acknowledgment. @@ -333,7 +316,6 @@ RFCAckIntClear(void) //***************************************************************************** extern uint32_t RFCDoorbellSendTo(uint32_t pOp); - //***************************************************************************** // //! This function implements a fast way to turn off the synthesizer. @@ -341,7 +323,6 @@ extern uint32_t RFCDoorbellSendTo(uint32_t pOp); //***************************************************************************** extern void RFCSynthPowerDown(void); - //***************************************************************************** // //! Reset previously patched CPE RAM to a state where it can be patched again. @@ -349,7 +330,6 @@ extern void RFCSynthPowerDown(void); //***************************************************************************** extern void RFCCpePatchReset(void); - //***************************************************************************** // // Function to search an override list for the provided pattern within the search depth. @@ -357,7 +337,6 @@ extern void RFCCpePatchReset(void); //***************************************************************************** extern uint8_t RFCOverrideSearch(const uint32_t* pOverride, const uint32_t pattern, const uint32_t mask, const uint8_t searchDepth); - //***************************************************************************** // //! Function to update override list @@ -365,7 +344,6 @@ extern uint8_t RFCOverrideSearch(const uint32_t* pOverride, const uint32_t patte //***************************************************************************** extern uint8_t RFCOverrideUpdate(rfc_radioOp_t* pOpSetup, uint32_t* pParams); - //***************************************************************************** // //! Get and clear HW interrupt flags. @@ -373,7 +351,6 @@ extern uint8_t RFCOverrideUpdate(rfc_radioOp_t* pOpSetup, uint32_t* pParams); //***************************************************************************** extern uint32_t RFCHwIntGetAndClear(uint32_t ui32Mask); - //***************************************************************************** // //! Get the type of currently selected PA. @@ -396,7 +373,6 @@ RFCGetPaGain(void) return (HWREG(RFC_PA_GAIN_ADDRESS) & RFC_PA_GAIN_MASK); } - //***************************************************************************** // //! Function to calculate the proper override run-time for the High Gain PA. @@ -404,7 +380,6 @@ RFCGetPaGain(void) //***************************************************************************** extern uint32_t RFCAnaDivTxOverride(uint8_t loDivider, uint8_t frontEndMode); - //***************************************************************************** // // Support for DriverLib in ROM: @@ -414,36 +389,36 @@ extern uint32_t RFCAnaDivTxOverride(uint8_t loDivider, uint8_t frontEndMode); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_RFCCpeIntGetAndClear -#undef RFCCpeIntGetAndClear -#define RFCCpeIntGetAndClear ROM_RFCCpeIntGetAndClear +#undef RFCCpeIntGetAndClear +#define RFCCpeIntGetAndClear ROM_RFCCpeIntGetAndClear #endif #ifdef ROM_RFCDoorbellSendTo -#undef RFCDoorbellSendTo -#define RFCDoorbellSendTo ROM_RFCDoorbellSendTo +#undef RFCDoorbellSendTo +#define RFCDoorbellSendTo ROM_RFCDoorbellSendTo #endif #ifdef ROM_RFCSynthPowerDown -#undef RFCSynthPowerDown -#define RFCSynthPowerDown ROM_RFCSynthPowerDown +#undef RFCSynthPowerDown +#define RFCSynthPowerDown ROM_RFCSynthPowerDown #endif #ifdef ROM_RFCCpePatchReset -#undef RFCCpePatchReset -#define RFCCpePatchReset ROM_RFCCpePatchReset +#undef RFCCpePatchReset +#define RFCCpePatchReset ROM_RFCCpePatchReset #endif #ifdef ROM_RFCOverrideSearch -#undef RFCOverrideSearch -#define RFCOverrideSearch ROM_RFCOverrideSearch +#undef RFCOverrideSearch +#define RFCOverrideSearch ROM_RFCOverrideSearch #endif #ifdef ROM_RFCOverrideUpdate -#undef RFCOverrideUpdate -#define RFCOverrideUpdate ROM_RFCOverrideUpdate +#undef RFCOverrideUpdate +#define RFCOverrideUpdate ROM_RFCOverrideUpdate #endif #ifdef ROM_RFCHwIntGetAndClear -#undef RFCHwIntGetAndClear -#define RFCHwIntGetAndClear ROM_RFCHwIntGetAndClear +#undef RFCHwIntGetAndClear +#define RFCHwIntGetAndClear ROM_RFCHwIntGetAndClear #endif #ifdef ROM_RFCAnaDivTxOverride -#undef RFCAnaDivTxOverride -#define RFCAnaDivTxOverride ROM_RFCAnaDivTxOverride +#undef RFCAnaDivTxOverride +#define RFCAnaDivTxOverride ROM_RFCAnaDivTxOverride #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rom.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rom.h index cd15c47..e06760c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rom.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rom.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rom.h -* Revised: 2018-11-02 13:54:49 +0100 (Fri, 02 Nov 2018) -* Revision: 53196 -* -* Description: Prototypes for the ROM utility functions. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rom.h + * Revised: 2018-11-02 13:54:49 +0100 (Fri, 02 Nov 2018) + * Revision: 53196 + * + * Description: Prototypes for the ROM utility functions. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __ROM_H__ #define __ROM_H__ @@ -46,8 +46,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include "../inc/hw_types.h" @@ -59,179 +58,179 @@ extern "C" #define ROM_HAPI_TABLE_ADDR 0x10000048 // ROM Hard-API function interface types -typedef uint32_t (* FPTR_CRC32_T) ( uint8_t* /* pui8Data */, \ - uint32_t /* ui32ByteCount */, \ - uint32_t /* ui32RepeatCount */); +typedef uint32_t (*FPTR_CRC32_T)(uint8_t * /* pui8Data */, + uint32_t /* ui32ByteCount */, + uint32_t /* ui32RepeatCount */); -typedef uint32_t (* FPTR_GETFLSIZE_T) ( void ); +typedef uint32_t (*FPTR_GETFLSIZE_T)(void); -typedef uint32_t (* FPTR_GETCHIPID_T) ( void ); +typedef uint32_t (*FPTR_GETCHIPID_T)(void); -typedef uint32_t (* FPTR_RESERVED1_T) ( uint32_t ); +typedef uint32_t (*FPTR_RESERVED1_T)(uint32_t); -typedef uint32_t (* FPTR_RESERVED2_T) ( void ); +typedef uint32_t (*FPTR_RESERVED2_T)(void); -typedef uint32_t (* FPTR_RESERVED3_T) ( uint8_t*, \ - uint32_t, \ - uint32_t ); -typedef void (* FPTR_RESETDEV_T) ( void ); +typedef uint32_t (*FPTR_RESERVED3_T)(uint8_t *, + uint32_t, + uint32_t); +typedef void (*FPTR_RESETDEV_T)(void); -typedef uint32_t (* FPTR_FLETCHER32_T) ( uint16_t* /* pui16Data */, \ - uint16_t /* ui16WordCount */, \ - uint16_t /* ui16RepeatCount */); +typedef uint32_t (*FPTR_FLETCHER32_T)(uint16_t * /* pui16Data */, + uint16_t /* ui16WordCount */, + uint16_t /* ui16RepeatCount */); -typedef uint32_t (* FPTR_MINVAL_T) ( uint32_t* /* ulpDataBuffer */, \ - uint32_t /* ui32DataCount */); +typedef uint32_t (*FPTR_MINVAL_T)(uint32_t * /* ulpDataBuffer */, + uint32_t /* ui32DataCount */); -typedef uint32_t (* FPTR_MAXVAL_T) ( uint32_t* /* pui32DataBuffer */, \ - uint32_t /* ui32DataCount */); +typedef uint32_t (*FPTR_MAXVAL_T)(uint32_t * /* pui32DataBuffer */, + uint32_t /* ui32DataCount */); -typedef uint32_t (* FPTR_MEANVAL_T) ( uint32_t* /* pui32DataBuffer */, \ - uint32_t /* ui32DataCount */); +typedef uint32_t (*FPTR_MEANVAL_T)(uint32_t * /* pui32DataBuffer */, + uint32_t /* ui32DataCount */); -typedef uint32_t (* FPTR_STDDVAL_T) ( uint32_t* /* pui32DataBuffer */, \ - uint32_t /* ui32DataCount */); +typedef uint32_t (*FPTR_STDDVAL_T)(uint32_t * /* pui32DataBuffer */, + uint32_t /* ui32DataCount */); -typedef void (* FPTR_HFSOURCESAFESWITCH_T) ( void ); +typedef void (*FPTR_HFSOURCESAFESWITCH_T)(void); -typedef void (* FPTR_RESERVED4_T) ( uint32_t ); +typedef void (*FPTR_RESERVED4_T)(uint32_t); -typedef void (* FPTR_RESERVED5_T) ( uint32_t ); +typedef void (*FPTR_RESERVED5_T)(uint32_t); -typedef void (* FPTR_COMPAIN_T) ( uint8_t /* ut8Signal */); +typedef void (*FPTR_COMPAIN_T)(uint8_t /* ut8Signal */); -typedef void (* FPTR_COMPAREF_T) ( uint8_t /* ut8Signal */); +typedef void (*FPTR_COMPAREF_T)(uint8_t /* ut8Signal */); -typedef void (* FPTR_ADCCOMPBIN_T) ( uint8_t /* ut8Signal */); +typedef void (*FPTR_ADCCOMPBIN_T)(uint8_t /* ut8Signal */); -typedef void (* FPTR_DACVREF_T) ( uint8_t /* ut8Signal */); +typedef void (*FPTR_DACVREF_T)(uint8_t /* ut8Signal */); -extern uint32_t MemBusWrkAroundHapiProgramFlash(uint8_t* pui8DataBuffer, - uint32_t ui32Address, - uint32_t ui32Count); +extern uint32_t MemBusWrkAroundHapiProgramFlash(uint8_t *pui8DataBuffer, + uint32_t ui32Address, + uint32_t ui32Count); extern uint32_t MemBusWrkAroundHapiEraseSector(uint32_t ui32Address); // ROM Hard-API access table type typedef struct { - FPTR_CRC32_T Crc32; - FPTR_GETFLSIZE_T FlashGetSize; - FPTR_GETCHIPID_T GetChipId; - FPTR_RESERVED1_T ReservedLocation1; - FPTR_RESERVED2_T ReservedLocation2; - FPTR_RESERVED3_T ReservedLocation3; - FPTR_RESETDEV_T ResetDevice; - FPTR_FLETCHER32_T Fletcher32; - FPTR_MINVAL_T MinValue; - FPTR_MAXVAL_T MaxValue; - FPTR_MEANVAL_T MeanValue; - FPTR_STDDVAL_T StandDeviationValue; - FPTR_RESERVED4_T ReservedLocation4; - FPTR_RESERVED5_T ReservedLocation5; - FPTR_HFSOURCESAFESWITCH_T HFSourceSafeSwitch; - FPTR_COMPAIN_T SelectCompAInput; - FPTR_COMPAREF_T SelectCompARef; - FPTR_ADCCOMPBIN_T SelectADCCompBInput; - FPTR_DACVREF_T SelectDACVref; + FPTR_CRC32_T Crc32; + FPTR_GETFLSIZE_T FlashGetSize; + FPTR_GETCHIPID_T GetChipId; + FPTR_RESERVED1_T ReservedLocation1; + FPTR_RESERVED2_T ReservedLocation2; + FPTR_RESERVED3_T ReservedLocation3; + FPTR_RESETDEV_T ResetDevice; + FPTR_FLETCHER32_T Fletcher32; + FPTR_MINVAL_T MinValue; + FPTR_MAXVAL_T MaxValue; + FPTR_MEANVAL_T MeanValue; + FPTR_STDDVAL_T StandDeviationValue; + FPTR_RESERVED4_T ReservedLocation4; + FPTR_RESERVED5_T ReservedLocation5; + FPTR_HFSOURCESAFESWITCH_T HFSourceSafeSwitch; + FPTR_COMPAIN_T SelectCompAInput; + FPTR_COMPAREF_T SelectCompARef; + FPTR_ADCCOMPBIN_T SelectADCCompBInput; + FPTR_DACVREF_T SelectDACVref; } HARD_API_T; // Pointer to the ROM HAPI table -#define P_HARD_API ((HARD_API_T*) ROM_HAPI_TABLE_ADDR) +#define P_HARD_API ((HARD_API_T *)ROM_HAPI_TABLE_ADDR) -#define HapiCrc32(a,b,c) P_HARD_API->Crc32(a,b,c) -#define HapiGetFlashSize() P_HARD_API->FlashGetSize() -#define HapiGetChipId() P_HARD_API->GetChipId() -#define HapiSectorErase(a) MemBusWrkAroundHapiEraseSector(a) -#define HapiProgramFlash(a,b,c) MemBusWrkAroundHapiProgramFlash(a,b,c) -#define HapiResetDevice() P_HARD_API->ResetDevice() -#define HapiFletcher32(a,b,c) P_HARD_API->Fletcher32(a,b,c) -#define HapiMinValue(a,b) P_HARD_API->MinValue(a,b) -#define HapiMaxValue(a,b) P_HARD_API->MaxValue(a,b) -#define HapiMeanValue(a,b) P_HARD_API->MeanValue(a,b) -#define HapiStandDeviationValue(a,b) P_HARD_API->StandDeviationValue(a,b) -#define HapiHFSourceSafeSwitch() P_HARD_API->HFSourceSafeSwitch() -#define HapiSelectCompAInput(a) P_HARD_API->SelectCompAInput(a) -#define HapiSelectCompARef(a) P_HARD_API->SelectCompARef(a) -#define HapiSelectADCCompBInput(a) P_HARD_API->SelectADCCompBInput(a) -#define HapiSelectDACVref(a) P_HARD_API->SelectDACVref(a) +#define HapiCrc32(a, b, c) P_HARD_API->Crc32(a, b, c) +#define HapiGetFlashSize() P_HARD_API->FlashGetSize() +#define HapiGetChipId() P_HARD_API->GetChipId() +#define HapiSectorErase(a) MemBusWrkAroundHapiEraseSector(a) +#define HapiProgramFlash(a, b, c) MemBusWrkAroundHapiProgramFlash(a, b, c) +#define HapiResetDevice() P_HARD_API->ResetDevice() +#define HapiFletcher32(a, b, c) P_HARD_API->Fletcher32(a, b, c) +#define HapiMinValue(a, b) P_HARD_API->MinValue(a, b) +#define HapiMaxValue(a, b) P_HARD_API->MaxValue(a, b) +#define HapiMeanValue(a, b) P_HARD_API->MeanValue(a, b) +#define HapiStandDeviationValue(a, b) P_HARD_API->StandDeviationValue(a, b) +#define HapiHFSourceSafeSwitch() P_HARD_API->HFSourceSafeSwitch() +#define HapiSelectCompAInput(a) P_HARD_API->SelectCompAInput(a) +#define HapiSelectCompARef(a) P_HARD_API->SelectCompARef(a) +#define HapiSelectADCCompBInput(a) P_HARD_API->SelectADCCompBInput(a) +#define HapiSelectDACVref(a) P_HARD_API->SelectDACVref(a) // Defines for input parameter to the HapiSelectCompAInput function. -#define COMPA_IN_NC 0x00 +#define COMPA_IN_NC 0x00 // Defines used in CC13x0/CC26x0 devices -#define COMPA_IN_AUXIO7 0x09 -#define COMPA_IN_AUXIO6 0x0A -#define COMPA_IN_AUXIO5 0x0B -#define COMPA_IN_AUXIO4 0x0C -#define COMPA_IN_AUXIO3 0x0D -#define COMPA_IN_AUXIO2 0x0E -#define COMPA_IN_AUXIO1 0x0F -#define COMPA_IN_AUXIO0 0x10 +#define COMPA_IN_AUXIO7 0x09 +#define COMPA_IN_AUXIO6 0x0A +#define COMPA_IN_AUXIO5 0x0B +#define COMPA_IN_AUXIO4 0x0C +#define COMPA_IN_AUXIO3 0x0D +#define COMPA_IN_AUXIO2 0x0E +#define COMPA_IN_AUXIO1 0x0F +#define COMPA_IN_AUXIO0 0x10 // Defines used in CC13x2/CC26x2 devices -#define COMPA_IN_AUXIO26 COMPA_IN_AUXIO7 -#define COMPA_IN_AUXIO25 COMPA_IN_AUXIO6 -#define COMPA_IN_AUXIO24 COMPA_IN_AUXIO5 -#define COMPA_IN_AUXIO23 COMPA_IN_AUXIO4 -#define COMPA_IN_AUXIO22 COMPA_IN_AUXIO3 -#define COMPA_IN_AUXIO21 COMPA_IN_AUXIO2 -#define COMPA_IN_AUXIO20 COMPA_IN_AUXIO1 -#define COMPA_IN_AUXIO19 COMPA_IN_AUXIO0 +#define COMPA_IN_AUXIO26 COMPA_IN_AUXIO7 +#define COMPA_IN_AUXIO25 COMPA_IN_AUXIO6 +#define COMPA_IN_AUXIO24 COMPA_IN_AUXIO5 +#define COMPA_IN_AUXIO23 COMPA_IN_AUXIO4 +#define COMPA_IN_AUXIO22 COMPA_IN_AUXIO3 +#define COMPA_IN_AUXIO21 COMPA_IN_AUXIO2 +#define COMPA_IN_AUXIO20 COMPA_IN_AUXIO1 +#define COMPA_IN_AUXIO19 COMPA_IN_AUXIO0 // Defines for input parameter to the HapiSelectCompARef function. -#define COMPA_REF_NC 0x00 -#define COMPA_REF_DCOUPL 0x01 -#define COMPA_REF_VSS 0x02 -#define COMPA_REF_VDDS 0x03 -#define COMPA_REF_ADCVREFP 0x04 +#define COMPA_REF_NC 0x00 +#define COMPA_REF_DCOUPL 0x01 +#define COMPA_REF_VSS 0x02 +#define COMPA_REF_VDDS 0x03 +#define COMPA_REF_ADCVREFP 0x04 // Defines used in CC13x0/CC26x0 devices -#define COMPA_REF_AUXIO7 0x09 -#define COMPA_REF_AUXIO6 0x0A -#define COMPA_REF_AUXIO5 0x0B -#define COMPA_REF_AUXIO4 0x0C -#define COMPA_REF_AUXIO3 0x0D -#define COMPA_REF_AUXIO2 0x0E -#define COMPA_REF_AUXIO1 0x0F -#define COMPA_REF_AUXIO0 0x10 +#define COMPA_REF_AUXIO7 0x09 +#define COMPA_REF_AUXIO6 0x0A +#define COMPA_REF_AUXIO5 0x0B +#define COMPA_REF_AUXIO4 0x0C +#define COMPA_REF_AUXIO3 0x0D +#define COMPA_REF_AUXIO2 0x0E +#define COMPA_REF_AUXIO1 0x0F +#define COMPA_REF_AUXIO0 0x10 // Defines used in CC13x2/CC26x2 devices -#define COMPA_REF_AUXIO26 COMPA_REF_AUXIO7 -#define COMPA_REF_AUXIO25 COMPA_REF_AUXIO6 -#define COMPA_REF_AUXIO24 COMPA_REF_AUXIO5 -#define COMPA_REF_AUXIO23 COMPA_REF_AUXIO4 -#define COMPA_REF_AUXIO22 COMPA_REF_AUXIO3 -#define COMPA_REF_AUXIO21 COMPA_REF_AUXIO2 -#define COMPA_REF_AUXIO20 COMPA_REF_AUXIO1 -#define COMPA_REF_AUXIO19 COMPA_REF_AUXIO0 +#define COMPA_REF_AUXIO26 COMPA_REF_AUXIO7 +#define COMPA_REF_AUXIO25 COMPA_REF_AUXIO6 +#define COMPA_REF_AUXIO24 COMPA_REF_AUXIO5 +#define COMPA_REF_AUXIO23 COMPA_REF_AUXIO4 +#define COMPA_REF_AUXIO22 COMPA_REF_AUXIO3 +#define COMPA_REF_AUXIO21 COMPA_REF_AUXIO2 +#define COMPA_REF_AUXIO20 COMPA_REF_AUXIO1 +#define COMPA_REF_AUXIO19 COMPA_REF_AUXIO0 // Defines for input parameter to the HapiSelectADCCompBInput function. -#define ADC_COMPB_IN_NC 0x00 -#define ADC_COMPB_IN_DCOUPL 0x03 -#define ADC_COMPB_IN_VSS 0x04 -#define ADC_COMPB_IN_VDDS 0x05 +#define ADC_COMPB_IN_NC 0x00 +#define ADC_COMPB_IN_DCOUPL 0x03 +#define ADC_COMPB_IN_VSS 0x04 +#define ADC_COMPB_IN_VDDS 0x05 // Defines used in CC13x0/CC26x0 devices -#define ADC_COMPB_IN_AUXIO7 0x09 -#define ADC_COMPB_IN_AUXIO6 0x0A -#define ADC_COMPB_IN_AUXIO5 0x0B -#define ADC_COMPB_IN_AUXIO4 0x0C -#define ADC_COMPB_IN_AUXIO3 0x0D -#define ADC_COMPB_IN_AUXIO2 0x0E -#define ADC_COMPB_IN_AUXIO1 0x0F -#define ADC_COMPB_IN_AUXIO0 0x10 +#define ADC_COMPB_IN_AUXIO7 0x09 +#define ADC_COMPB_IN_AUXIO6 0x0A +#define ADC_COMPB_IN_AUXIO5 0x0B +#define ADC_COMPB_IN_AUXIO4 0x0C +#define ADC_COMPB_IN_AUXIO3 0x0D +#define ADC_COMPB_IN_AUXIO2 0x0E +#define ADC_COMPB_IN_AUXIO1 0x0F +#define ADC_COMPB_IN_AUXIO0 0x10 // Defines used in CC13x2/CC26x2 devices -#define ADC_COMPB_IN_AUXIO26 ADC_COMPB_IN_AUXIO7 -#define ADC_COMPB_IN_AUXIO25 ADC_COMPB_IN_AUXIO6 -#define ADC_COMPB_IN_AUXIO24 ADC_COMPB_IN_AUXIO5 -#define ADC_COMPB_IN_AUXIO23 ADC_COMPB_IN_AUXIO4 -#define ADC_COMPB_IN_AUXIO22 ADC_COMPB_IN_AUXIO3 -#define ADC_COMPB_IN_AUXIO21 ADC_COMPB_IN_AUXIO2 -#define ADC_COMPB_IN_AUXIO20 ADC_COMPB_IN_AUXIO1 -#define ADC_COMPB_IN_AUXIO19 ADC_COMPB_IN_AUXIO0 +#define ADC_COMPB_IN_AUXIO26 ADC_COMPB_IN_AUXIO7 +#define ADC_COMPB_IN_AUXIO25 ADC_COMPB_IN_AUXIO6 +#define ADC_COMPB_IN_AUXIO24 ADC_COMPB_IN_AUXIO5 +#define ADC_COMPB_IN_AUXIO23 ADC_COMPB_IN_AUXIO4 +#define ADC_COMPB_IN_AUXIO22 ADC_COMPB_IN_AUXIO3 +#define ADC_COMPB_IN_AUXIO21 ADC_COMPB_IN_AUXIO2 +#define ADC_COMPB_IN_AUXIO20 ADC_COMPB_IN_AUXIO1 +#define ADC_COMPB_IN_AUXIO19 ADC_COMPB_IN_AUXIO0 // Defines for input parameter to the HapiSelectDACVref function. // The define values can not be changed! -#define DAC_REF_NC 0x00 -#define DAC_REF_DCOUPL 0x01 -#define DAC_REF_VSS 0x02 -#define DAC_REF_VDDS 0x03 +#define DAC_REF_NC 0x00 +#define DAC_REF_DCOUPL 0x01 +#define DAC_REF_VSS 0x02 +#define DAC_REF_VDDS 0x03 #endif // __HAPI_H__ @@ -240,808 +239,780 @@ typedef struct // Pointers to the main API tables. // //***************************************************************************** -#define ROM_API_TABLE ((uint32_t *) 0x10000180) -#define ROM_VERSION (ROM_API_TABLE[0]) +#define ROM_API_TABLE ((uint32_t *)0x10000180) +#define ROM_VERSION (ROM_API_TABLE[0]) - -#define ROM_API_AON_EVENT_TABLE ((uint32_t*) (ROM_API_TABLE[1])) -#define ROM_API_AON_IOC_TABLE ((uint32_t*) (ROM_API_TABLE[2])) -#define ROM_API_AON_RTC_TABLE ((uint32_t*) (ROM_API_TABLE[3])) -#define ROM_API_AUX_CTRL_TABLE ((uint32_t*) (ROM_API_TABLE[5])) -#define ROM_API_AUX_TDC_TABLE ((uint32_t*) (ROM_API_TABLE[6])) -#define ROM_API_DDI_TABLE ((uint32_t*) (ROM_API_TABLE[9])) -#define ROM_API_FLASH_TABLE ((uint32_t*) (ROM_API_TABLE[10])) -#define ROM_API_I2C_TABLE ((uint32_t*) (ROM_API_TABLE[11])) -#define ROM_API_INTERRUPT_TABLE ((uint32_t*) (ROM_API_TABLE[12])) -#define ROM_API_IOC_TABLE ((uint32_t*) (ROM_API_TABLE[13])) -#define ROM_API_PRCM_TABLE ((uint32_t*) (ROM_API_TABLE[14])) -#define ROM_API_SMPH_TABLE ((uint32_t*) (ROM_API_TABLE[15])) -#define ROM_API_SSI_TABLE ((uint32_t*) (ROM_API_TABLE[17])) -#define ROM_API_TIMER_TABLE ((uint32_t*) (ROM_API_TABLE[18])) -#define ROM_API_TRNG_TABLE ((uint32_t*) (ROM_API_TABLE[19])) -#define ROM_API_UART_TABLE ((uint32_t*) (ROM_API_TABLE[20])) -#define ROM_API_UDMA_TABLE ((uint32_t*) (ROM_API_TABLE[21])) -#define ROM_API_VIMS_TABLE ((uint32_t*) (ROM_API_TABLE[22])) -#define ROM_API_CRYPTO_TABLE ((uint32_t*) (ROM_API_TABLE[23])) -#define ROM_API_OSC_TABLE ((uint32_t*) (ROM_API_TABLE[24])) -#define ROM_API_AUX_ADC_TABLE ((uint32_t*) (ROM_API_TABLE[25])) -#define ROM_API_SYS_CTRL_TABLE ((uint32_t*) (ROM_API_TABLE[26])) -#define ROM_API_AON_BATMON_TABLE ((uint32_t*) (ROM_API_TABLE[27])) -#define ROM_API_SETUP_ROM_TABLE ((uint32_t*) (ROM_API_TABLE[28])) -#define ROM_API_I2S_TABLE ((uint32_t*) (ROM_API_TABLE[29])) -#define ROM_API_PWR_CTRL_TABLE ((uint32_t*) (ROM_API_TABLE[30])) -#define ROM_API_AES_TABLE ((uint32_t*) (ROM_API_TABLE[31])) -#define ROM_API_PKA_TABLE ((uint32_t*) (ROM_API_TABLE[32])) -#define ROM_API_SHA2_TABLE ((uint32_t*) (ROM_API_TABLE[33])) +#define ROM_API_AON_EVENT_TABLE ((uint32_t *)(ROM_API_TABLE[1])) +#define ROM_API_AON_IOC_TABLE ((uint32_t *)(ROM_API_TABLE[2])) +#define ROM_API_AON_RTC_TABLE ((uint32_t *)(ROM_API_TABLE[3])) +#define ROM_API_AUX_CTRL_TABLE ((uint32_t *)(ROM_API_TABLE[5])) +#define ROM_API_AUX_TDC_TABLE ((uint32_t *)(ROM_API_TABLE[6])) +#define ROM_API_DDI_TABLE ((uint32_t *)(ROM_API_TABLE[9])) +#define ROM_API_FLASH_TABLE ((uint32_t *)(ROM_API_TABLE[10])) +#define ROM_API_I2C_TABLE ((uint32_t *)(ROM_API_TABLE[11])) +#define ROM_API_INTERRUPT_TABLE ((uint32_t *)(ROM_API_TABLE[12])) +#define ROM_API_IOC_TABLE ((uint32_t *)(ROM_API_TABLE[13])) +#define ROM_API_PRCM_TABLE ((uint32_t *)(ROM_API_TABLE[14])) +#define ROM_API_SMPH_TABLE ((uint32_t *)(ROM_API_TABLE[15])) +#define ROM_API_SSI_TABLE ((uint32_t *)(ROM_API_TABLE[17])) +#define ROM_API_TIMER_TABLE ((uint32_t *)(ROM_API_TABLE[18])) +#define ROM_API_TRNG_TABLE ((uint32_t *)(ROM_API_TABLE[19])) +#define ROM_API_UART_TABLE ((uint32_t *)(ROM_API_TABLE[20])) +#define ROM_API_UDMA_TABLE ((uint32_t *)(ROM_API_TABLE[21])) +#define ROM_API_VIMS_TABLE ((uint32_t *)(ROM_API_TABLE[22])) +#define ROM_API_CRYPTO_TABLE ((uint32_t *)(ROM_API_TABLE[23])) +#define ROM_API_OSC_TABLE ((uint32_t *)(ROM_API_TABLE[24])) +#define ROM_API_AUX_ADC_TABLE ((uint32_t *)(ROM_API_TABLE[25])) +#define ROM_API_SYS_CTRL_TABLE ((uint32_t *)(ROM_API_TABLE[26])) +#define ROM_API_AON_BATMON_TABLE ((uint32_t *)(ROM_API_TABLE[27])) +#define ROM_API_SETUP_ROM_TABLE ((uint32_t *)(ROM_API_TABLE[28])) +#define ROM_API_I2S_TABLE ((uint32_t *)(ROM_API_TABLE[29])) +#define ROM_API_PWR_CTRL_TABLE ((uint32_t *)(ROM_API_TABLE[30])) +#define ROM_API_AES_TABLE ((uint32_t *)(ROM_API_TABLE[31])) +#define ROM_API_PKA_TABLE ((uint32_t *)(ROM_API_TABLE[32])) +#define ROM_API_SHA2_TABLE ((uint32_t *)(ROM_API_TABLE[33])) // AON_EVENT FUNCTIONS -#define ROM_AONEventMcuWakeUpSet \ +#define ROM_AONEventMcuWakeUpSet \ ((void (*)(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc)) \ - ROM_API_AON_EVENT_TABLE[0]) + ROM_API_AON_EVENT_TABLE[0]) -#define ROM_AONEventMcuWakeUpGet \ - ((uint32_t (*)(uint32_t ui32MCUWUEvent)) \ - ROM_API_AON_EVENT_TABLE[1]) +#define ROM_AONEventMcuWakeUpGet \ + ((uint32_t(*)(uint32_t ui32MCUWUEvent)) \ + ROM_API_AON_EVENT_TABLE[1]) -#define ROM_AONEventMcuSet \ +#define ROM_AONEventMcuSet \ ((void (*)(uint32_t ui32MCUEvent, uint32_t ui32EventSrc)) \ - ROM_API_AON_EVENT_TABLE[4]) - -#define ROM_AONEventMcuGet \ - ((uint32_t (*)(uint32_t ui32MCUEvent)) \ - ROM_API_AON_EVENT_TABLE[5]) + ROM_API_AON_EVENT_TABLE[4]) +#define ROM_AONEventMcuGet \ + ((uint32_t(*)(uint32_t ui32MCUEvent)) \ + ROM_API_AON_EVENT_TABLE[5]) // AON_RTC FUNCTIONS #define ROM_AONRTCCurrent64BitValueGet \ - ((uint64_t (*)(void)) \ - ROM_API_AON_RTC_TABLE[12]) - + ((uint64_t(*)(void)) \ + ROM_API_AON_RTC_TABLE[12]) // AUX_TDC FUNCTIONS -#define ROM_AUXTDCConfigSet \ +#define ROM_AUXTDCConfigSet \ ((void (*)(uint32_t ui32Base, uint32_t ui32StartCondition, uint32_t ui32StopCondition)) \ - ROM_API_AUX_TDC_TABLE[0]) - -#define ROM_AUXTDCMeasurementDone \ - ((uint32_t (*)(uint32_t ui32Base)) \ - ROM_API_AUX_TDC_TABLE[1]) + ROM_API_AUX_TDC_TABLE[0]) +#define ROM_AUXTDCMeasurementDone \ + ((uint32_t(*)(uint32_t ui32Base)) \ + ROM_API_AUX_TDC_TABLE[1]) // DDI FUNCTIONS -#define ROM_DDI16BitWrite \ +#define ROM_DDI16BitWrite \ ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32WrData)) \ - ROM_API_DDI_TABLE[0]) + ROM_API_DDI_TABLE[0]) -#define ROM_DDI16BitfieldWrite \ +#define ROM_DDI16BitfieldWrite \ ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift, uint16_t ui32Data)) \ - ROM_API_DDI_TABLE[1]) + ROM_API_DDI_TABLE[1]) -#define ROM_DDI16BitRead \ - ((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask)) \ - ROM_API_DDI_TABLE[2]) +#define ROM_DDI16BitRead \ + ((uint16_t(*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask)) \ + ROM_API_DDI_TABLE[2]) -#define ROM_DDI16BitfieldRead \ - ((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift)) \ - ROM_API_DDI_TABLE[3]) +#define ROM_DDI16BitfieldRead \ + ((uint16_t(*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift)) \ + ROM_API_DDI_TABLE[3]) -#define ROM_DDI32RegWrite \ +#define ROM_DDI32RegWrite \ ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)) \ - ROM_API_DDI_TABLE[4]) - + ROM_API_DDI_TABLE[4]) // FLASH FUNCTIONS -#define ROM_FlashPowerModeSet \ +#define ROM_FlashPowerModeSet \ ((void (*)(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriod, uint32_t ui32PumpGracePeriod)) \ - ROM_API_FLASH_TABLE[0]) + ROM_API_FLASH_TABLE[0]) #define ROM_FlashPowerModeGet \ - ((uint32_t (*)(void)) \ - ROM_API_FLASH_TABLE[1]) + ((uint32_t(*)(void)) \ + ROM_API_FLASH_TABLE[1]) -#define ROM_FlashProtectionSet \ +#define ROM_FlashProtectionSet \ ((void (*)(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode)) \ - ROM_API_FLASH_TABLE[2]) + ROM_API_FLASH_TABLE[2]) -#define ROM_FlashProtectionGet \ - ((uint32_t (*)(uint32_t ui32SectorAddress)) \ - ROM_API_FLASH_TABLE[3]) +#define ROM_FlashProtectionGet \ + ((uint32_t(*)(uint32_t ui32SectorAddress)) \ + ROM_API_FLASH_TABLE[3]) -#define ROM_FlashProtectionSave \ - ((uint32_t (*)(uint32_t ui32SectorAddress)) \ - ROM_API_FLASH_TABLE[4]) +#define ROM_FlashProtectionSave \ + ((uint32_t(*)(uint32_t ui32SectorAddress)) \ + ROM_API_FLASH_TABLE[4]) -#define ROM_FlashEfuseReadRow \ - ((bool (*)(uint32_t *pui32EfuseData, uint32_t ui32RowAddress)) \ - ROM_API_FLASH_TABLE[8]) +#define ROM_FlashEfuseReadRow \ + ((bool (*)(uint32_t * pui32EfuseData, uint32_t ui32RowAddress)) \ + ROM_API_FLASH_TABLE[8]) #define ROM_FlashDisableSectorsForWrite \ - ((void (*)(void)) \ - ROM_API_FLASH_TABLE[9]) - + ((void (*)(void)) \ + ROM_API_FLASH_TABLE[9]) // I2C FUNCTIONS -#define ROM_I2CMasterInitExpClk \ +#define ROM_I2CMasterInitExpClk \ ((void (*)(uint32_t ui32Base, uint32_t ui32I2CClk, bool bFast)) \ - ROM_API_I2C_TABLE[0]) - -#define ROM_I2CMasterErr \ - ((uint32_t (*)(uint32_t ui32Base)) \ - ROM_API_I2C_TABLE[1]) + ROM_API_I2C_TABLE[0]) +#define ROM_I2CMasterErr \ + ((uint32_t(*)(uint32_t ui32Base)) \ + ROM_API_I2C_TABLE[1]) // INTERRUPT FUNCTIONS #define ROM_IntPriorityGroupingSet \ ((void (*)(uint32_t ui32Bits)) \ - ROM_API_INTERRUPT_TABLE[0]) + ROM_API_INTERRUPT_TABLE[0]) #define ROM_IntPriorityGroupingGet \ - ((uint32_t (*)(void)) \ - ROM_API_INTERRUPT_TABLE[1]) + ((uint32_t(*)(void)) \ + ROM_API_INTERRUPT_TABLE[1]) -#define ROM_IntPrioritySet \ +#define ROM_IntPrioritySet \ ((void (*)(uint32_t ui32Interrupt, uint8_t ui8Priority)) \ - ROM_API_INTERRUPT_TABLE[2]) + ROM_API_INTERRUPT_TABLE[2]) -#define ROM_IntPriorityGet \ - ((int32_t (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[3]) +#define ROM_IntPriorityGet \ + ((int32_t(*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[3]) -#define ROM_IntEnable \ +#define ROM_IntEnable \ ((void (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[4]) + ROM_API_INTERRUPT_TABLE[4]) -#define ROM_IntDisable \ +#define ROM_IntDisable \ ((void (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[5]) + ROM_API_INTERRUPT_TABLE[5]) -#define ROM_IntPendSet \ +#define ROM_IntPendSet \ ((void (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[6]) + ROM_API_INTERRUPT_TABLE[6]) -#define ROM_IntPendGet \ +#define ROM_IntPendGet \ ((bool (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[7]) + ROM_API_INTERRUPT_TABLE[7]) -#define ROM_IntPendClear \ +#define ROM_IntPendClear \ ((void (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[8]) - + ROM_API_INTERRUPT_TABLE[8]) // IOC FUNCTIONS -#define ROM_IOCPortConfigureSet \ +#define ROM_IOCPortConfigureSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId, uint32_t ui32IOConfig)) \ - ROM_API_IOC_TABLE[0]) + ROM_API_IOC_TABLE[0]) -#define ROM_IOCPortConfigureGet \ - ((uint32_t (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[1]) +#define ROM_IOCPortConfigureGet \ + ((uint32_t(*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[1]) -#define ROM_IOCIOShutdownSet \ +#define ROM_IOCIOShutdownSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32IOShutdown)) \ - ROM_API_IOC_TABLE[2]) + ROM_API_IOC_TABLE[2]) -#define ROM_IOCIOModeSet \ +#define ROM_IOCIOModeSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32IOMode)) \ - ROM_API_IOC_TABLE[4]) + ROM_API_IOC_TABLE[4]) -#define ROM_IOCIOIntSet \ +#define ROM_IOCIOIntSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet)) \ - ROM_API_IOC_TABLE[5]) + ROM_API_IOC_TABLE[5]) -#define ROM_IOCIOPortPullSet \ +#define ROM_IOCIOPortPullSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32Pull)) \ - ROM_API_IOC_TABLE[6]) + ROM_API_IOC_TABLE[6]) -#define ROM_IOCIOHystSet \ +#define ROM_IOCIOHystSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32Hysteresis)) \ - ROM_API_IOC_TABLE[7]) + ROM_API_IOC_TABLE[7]) -#define ROM_IOCIOInputSet \ +#define ROM_IOCIOInputSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32Input)) \ - ROM_API_IOC_TABLE[8]) + ROM_API_IOC_TABLE[8]) -#define ROM_IOCIOSlewCtrlSet \ +#define ROM_IOCIOSlewCtrlSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32SlewEnable)) \ - ROM_API_IOC_TABLE[9]) + ROM_API_IOC_TABLE[9]) -#define ROM_IOCIODrvStrengthSet \ +#define ROM_IOCIODrvStrengthSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32IOCurrent, uint32_t ui32DrvStrength)) \ - ROM_API_IOC_TABLE[10]) + ROM_API_IOC_TABLE[10]) -#define ROM_IOCIOPortIdSet \ +#define ROM_IOCIOPortIdSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId)) \ - ROM_API_IOC_TABLE[11]) + ROM_API_IOC_TABLE[11]) -#define ROM_IOCIntEnable \ +#define ROM_IOCIntEnable \ ((void (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[12]) + ROM_API_IOC_TABLE[12]) -#define ROM_IOCIntDisable \ +#define ROM_IOCIntDisable \ ((void (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[13]) + ROM_API_IOC_TABLE[13]) -#define ROM_IOCPinTypeGpioInput \ +#define ROM_IOCPinTypeGpioInput \ ((void (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[14]) + ROM_API_IOC_TABLE[14]) -#define ROM_IOCPinTypeGpioOutput \ +#define ROM_IOCPinTypeGpioOutput \ ((void (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[15]) + ROM_API_IOC_TABLE[15]) -#define ROM_IOCPinTypeUart \ +#define ROM_IOCPinTypeUart \ ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Cts, uint32_t ui32Rts)) \ - ROM_API_IOC_TABLE[16]) + ROM_API_IOC_TABLE[16]) -#define ROM_IOCPinTypeSsiMaster \ +#define ROM_IOCPinTypeSsiMaster \ ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ - ROM_API_IOC_TABLE[17]) + ROM_API_IOC_TABLE[17]) -#define ROM_IOCPinTypeSsiSlave \ +#define ROM_IOCPinTypeSsiSlave \ ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ - ROM_API_IOC_TABLE[18]) + ROM_API_IOC_TABLE[18]) -#define ROM_IOCPinTypeI2c \ +#define ROM_IOCPinTypeI2c \ ((void (*)(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk)) \ - ROM_API_IOC_TABLE[19]) + ROM_API_IOC_TABLE[19]) -#define ROM_IOCPinTypeAux \ +#define ROM_IOCPinTypeAux \ ((void (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[21]) - + ROM_API_IOC_TABLE[21]) // PRCM FUNCTIONS -#define ROM_PRCMInfClockConfigureSet \ +#define ROM_PRCMInfClockConfigureSet \ ((void (*)(uint32_t ui32ClkDiv, uint32_t ui32PowerMode)) \ - ROM_API_PRCM_TABLE[0]) + ROM_API_PRCM_TABLE[0]) -#define ROM_PRCMInfClockConfigureGet \ - ((uint32_t (*)(uint32_t ui32PowerMode)) \ - ROM_API_PRCM_TABLE[1]) +#define ROM_PRCMInfClockConfigureGet \ + ((uint32_t(*)(uint32_t ui32PowerMode)) \ + ROM_API_PRCM_TABLE[1]) -#define ROM_PRCMAudioClockConfigSet \ +#define ROM_PRCMAudioClockConfigSet \ ((void (*)(uint32_t ui32ClkConfig, uint32_t ui32SampleRate)) \ - ROM_API_PRCM_TABLE[4]) + ROM_API_PRCM_TABLE[4]) -#define ROM_PRCMPowerDomainOn \ +#define ROM_PRCMPowerDomainOn \ ((void (*)(uint32_t ui32Domains)) \ - ROM_API_PRCM_TABLE[5]) + ROM_API_PRCM_TABLE[5]) -#define ROM_PRCMPowerDomainOff \ +#define ROM_PRCMPowerDomainOff \ ((void (*)(uint32_t ui32Domains)) \ - ROM_API_PRCM_TABLE[6]) + ROM_API_PRCM_TABLE[6]) -#define ROM_PRCMPeripheralRunEnable \ +#define ROM_PRCMPeripheralRunEnable \ ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[7]) + ROM_API_PRCM_TABLE[7]) -#define ROM_PRCMPeripheralRunDisable \ +#define ROM_PRCMPeripheralRunDisable \ ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[8]) + ROM_API_PRCM_TABLE[8]) -#define ROM_PRCMPeripheralSleepEnable \ +#define ROM_PRCMPeripheralSleepEnable \ ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[9]) + ROM_API_PRCM_TABLE[9]) -#define ROM_PRCMPeripheralSleepDisable \ +#define ROM_PRCMPeripheralSleepDisable \ ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[10]) + ROM_API_PRCM_TABLE[10]) #define ROM_PRCMPeripheralDeepSleepEnable \ - ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[11]) + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[11]) #define ROM_PRCMPeripheralDeepSleepDisable \ - ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[12]) + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[12]) -#define ROM_PRCMPowerDomainStatus \ - ((uint32_t (*)(uint32_t ui32Domains)) \ - ROM_API_PRCM_TABLE[13]) +#define ROM_PRCMPowerDomainStatus \ + ((uint32_t(*)(uint32_t ui32Domains)) \ + ROM_API_PRCM_TABLE[13]) #define ROM_PRCMDeepSleep \ - ((void (*)(void)) \ - ROM_API_PRCM_TABLE[14]) + ((void (*)(void)) \ + ROM_API_PRCM_TABLE[14]) -#define ROM_PRCMAudioClockConfigSetOverride \ +#define ROM_PRCMAudioClockConfigSetOverride \ ((void (*)(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, uint32_t ui32BitDiv, uint32_t ui32WordDiv)) \ - ROM_API_PRCM_TABLE[17]) - + ROM_API_PRCM_TABLE[17]) // SMPH FUNCTIONS -#define ROM_SMPHAcquire \ +#define ROM_SMPHAcquire \ ((void (*)(uint32_t ui32Semaphore)) \ - ROM_API_SMPH_TABLE[0]) - + ROM_API_SMPH_TABLE[0]) // SSI FUNCTIONS -#define ROM_SSIConfigSetExpClk \ +#define ROM_SSIConfigSetExpClk \ ((void (*)(uint32_t ui32Base, uint32_t ui32SSIClk, uint32_t ui32Protocol, uint32_t ui32Mode, uint32_t ui32BitRate, uint32_t ui32DataWidth)) \ - ROM_API_SSI_TABLE[0]) + ROM_API_SSI_TABLE[0]) -#define ROM_SSIDataPut \ +#define ROM_SSIDataPut \ ((void (*)(uint32_t ui32Base, uint32_t ui32Data)) \ - ROM_API_SSI_TABLE[1]) + ROM_API_SSI_TABLE[1]) -#define ROM_SSIDataPutNonBlocking \ - ((int32_t (*)(uint32_t ui32Base, uint32_t ui32Data)) \ - ROM_API_SSI_TABLE[2]) +#define ROM_SSIDataPutNonBlocking \ + ((int32_t(*)(uint32_t ui32Base, uint32_t ui32Data)) \ + ROM_API_SSI_TABLE[2]) -#define ROM_SSIDataGet \ - ((void (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ - ROM_API_SSI_TABLE[3]) - -#define ROM_SSIDataGetNonBlocking \ - ((int32_t (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ - ROM_API_SSI_TABLE[4]) +#define ROM_SSIDataGet \ + ((void (*)(uint32_t ui32Base, uint32_t * pui32Data)) \ + ROM_API_SSI_TABLE[3]) +#define ROM_SSIDataGetNonBlocking \ + ((int32_t(*)(uint32_t ui32Base, uint32_t * pui32Data)) \ + ROM_API_SSI_TABLE[4]) // TIMER FUNCTIONS -#define ROM_TimerConfigure \ +#define ROM_TimerConfigure \ ((void (*)(uint32_t ui32Base, uint32_t ui32Config)) \ - ROM_API_TIMER_TABLE[0]) + ROM_API_TIMER_TABLE[0]) -#define ROM_TimerLevelControl \ +#define ROM_TimerLevelControl \ ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert)) \ - ROM_API_TIMER_TABLE[1]) + ROM_API_TIMER_TABLE[1]) -#define ROM_TimerStallControl \ +#define ROM_TimerStallControl \ ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bStall)) \ - ROM_API_TIMER_TABLE[3]) + ROM_API_TIMER_TABLE[3]) -#define ROM_TimerWaitOnTriggerControl \ +#define ROM_TimerWaitOnTriggerControl \ ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bWait)) \ - ROM_API_TIMER_TABLE[4]) + ROM_API_TIMER_TABLE[4]) -#define ROM_TimerIntervalLoadMode \ +#define ROM_TimerIntervalLoadMode \ ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode)) \ - ROM_API_TIMER_TABLE[5]) + ROM_API_TIMER_TABLE[5]) -#define ROM_TimerMatchUpdateMode \ +#define ROM_TimerMatchUpdateMode \ ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode)) \ - ROM_API_TIMER_TABLE[6]) - + ROM_API_TIMER_TABLE[6]) // TRNG FUNCTIONS -#define ROM_TRNGConfigure \ +#define ROM_TRNGConfigure \ ((void (*)(uint32_t ui32MinSamplesPerCycle, uint32_t ui32MaxSamplesPerCycle, uint32_t ui32ClocksPerSample)) \ - ROM_API_TRNG_TABLE[0]) - -#define ROM_TRNGNumberGet \ - ((uint32_t (*)(uint32_t ui32Word)) \ - ROM_API_TRNG_TABLE[1]) + ROM_API_TRNG_TABLE[0]) +#define ROM_TRNGNumberGet \ + ((uint32_t(*)(uint32_t ui32Word)) \ + ROM_API_TRNG_TABLE[1]) // UART FUNCTIONS -#define ROM_UARTFIFOLevelGet \ - ((void (*)(uint32_t ui32Base, uint32_t *pui32TxLevel, uint32_t *pui32RxLevel)) \ - ROM_API_UART_TABLE[0]) +#define ROM_UARTFIFOLevelGet \ + ((void (*)(uint32_t ui32Base, uint32_t * pui32TxLevel, uint32_t * pui32RxLevel)) \ + ROM_API_UART_TABLE[0]) -#define ROM_UARTConfigSetExpClk \ +#define ROM_UARTConfigSetExpClk \ ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t ui32Baud, uint32_t ui32Config)) \ - ROM_API_UART_TABLE[1]) + ROM_API_UART_TABLE[1]) -#define ROM_UARTConfigGetExpClk \ - ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t *pui32Baud, uint32_t *pui32Config)) \ - ROM_API_UART_TABLE[2]) +#define ROM_UARTConfigGetExpClk \ + ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t * pui32Baud, uint32_t * pui32Config)) \ + ROM_API_UART_TABLE[2]) -#define ROM_UARTDisable \ +#define ROM_UARTDisable \ ((void (*)(uint32_t ui32Base)) \ - ROM_API_UART_TABLE[3]) + ROM_API_UART_TABLE[3]) -#define ROM_UARTCharGetNonBlocking \ - ((int32_t (*)(uint32_t ui32Base)) \ - ROM_API_UART_TABLE[4]) +#define ROM_UARTCharGetNonBlocking \ + ((int32_t(*)(uint32_t ui32Base)) \ + ROM_API_UART_TABLE[4]) -#define ROM_UARTCharGet \ - ((int32_t (*)(uint32_t ui32Base)) \ - ROM_API_UART_TABLE[5]) +#define ROM_UARTCharGet \ + ((int32_t(*)(uint32_t ui32Base)) \ + ROM_API_UART_TABLE[5]) -#define ROM_UARTCharPutNonBlocking \ +#define ROM_UARTCharPutNonBlocking \ ((bool (*)(uint32_t ui32Base, uint8_t ui8Data)) \ - ROM_API_UART_TABLE[6]) + ROM_API_UART_TABLE[6]) -#define ROM_UARTCharPut \ +#define ROM_UARTCharPut \ ((void (*)(uint32_t ui32Base, uint8_t ui8Data)) \ - ROM_API_UART_TABLE[7]) - + ROM_API_UART_TABLE[7]) // UDMA FUNCTIONS -#define ROM_uDMAChannelAttributeEnable \ +#define ROM_uDMAChannelAttributeEnable \ ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ - ROM_API_UDMA_TABLE[0]) + ROM_API_UDMA_TABLE[0]) -#define ROM_uDMAChannelAttributeDisable \ +#define ROM_uDMAChannelAttributeDisable \ ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ - ROM_API_UDMA_TABLE[1]) + ROM_API_UDMA_TABLE[1]) -#define ROM_uDMAChannelAttributeGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelNum)) \ - ROM_API_UDMA_TABLE[2]) +#define ROM_uDMAChannelAttributeGet \ + ((uint32_t(*)(uint32_t ui32Base, uint32_t ui32ChannelNum)) \ + ROM_API_UDMA_TABLE[2]) -#define ROM_uDMAChannelControlSet \ +#define ROM_uDMAChannelControlSet \ ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Control)) \ - ROM_API_UDMA_TABLE[3]) + ROM_API_UDMA_TABLE[3]) -#define ROM_uDMAChannelTransferSet \ +#define ROM_uDMAChannelTransferSet \ ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, uint32_t ui32TransferSize)) \ - ROM_API_UDMA_TABLE[4]) + ROM_API_UDMA_TABLE[4]) -#define ROM_uDMAChannelScatterGatherSet \ +#define ROM_uDMAChannelScatterGatherSet \ ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void *pvTaskList, uint32_t ui32IsPeriphSG)) \ - ROM_API_UDMA_TABLE[5]) + ROM_API_UDMA_TABLE[5]) -#define ROM_uDMAChannelSizeGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ - ROM_API_UDMA_TABLE[6]) - -#define ROM_uDMAChannelModeGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ - ROM_API_UDMA_TABLE[7]) +#define ROM_uDMAChannelSizeGet \ + ((uint32_t(*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ + ROM_API_UDMA_TABLE[6]) +#define ROM_uDMAChannelModeGet \ + ((uint32_t(*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ + ROM_API_UDMA_TABLE[7]) // VIMS FUNCTIONS -#define ROM_VIMSConfigure \ +#define ROM_VIMSConfigure \ ((void (*)(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch)) \ - ROM_API_VIMS_TABLE[0]) + ROM_API_VIMS_TABLE[0]) -#define ROM_VIMSModeSet \ +#define ROM_VIMSModeSet \ ((void (*)(uint32_t ui32Base, uint32_t ui32Mode)) \ - ROM_API_VIMS_TABLE[1]) + ROM_API_VIMS_TABLE[1]) -#define ROM_VIMSModeGet \ - ((uint32_t (*)(uint32_t ui32Base)) \ - ROM_API_VIMS_TABLE[2]) - -#define ROM_VIMSModeSafeSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32NewMode, bool blocking)) \ - ROM_API_VIMS_TABLE[3]) +#define ROM_VIMSModeGet \ + ((uint32_t(*)(uint32_t ui32Base)) \ + ROM_API_VIMS_TABLE[2]) +#define ROM_VIMSModeSafeSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32NewMode, bool blocking)) \ + ROM_API_VIMS_TABLE[3]) // OSC FUNCTIONS -#define ROM_OSCClockSourceGet \ - ((uint32_t (*)(uint32_t ui32SrcClk)) \ - ROM_API_OSC_TABLE[0]) +#define ROM_OSCClockSourceGet \ + ((uint32_t(*)(uint32_t ui32SrcClk)) \ + ROM_API_OSC_TABLE[0]) -#define ROM_OSCClockSourceSet \ +#define ROM_OSCClockSourceSet \ ((void (*)(uint32_t ui32SrcClk, uint32_t ui32Osc)) \ - ROM_API_OSC_TABLE[1]) + ROM_API_OSC_TABLE[1]) #define ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert \ - ((int16_t (*)(int32_t HPOSC_RelFreqOffset)) \ - ROM_API_OSC_TABLE[3]) - + ((int16_t(*)(int32_t HPOSC_RelFreqOffset)) \ + ROM_API_OSC_TABLE[3]) // AUX_ADC FUNCTIONS -#define ROM_AUXADCAdjustValueForGainAndOffset \ - ((int32_t (*)(int32_t adcValue, int32_t gain, int32_t offset)) \ - ROM_API_AUX_ADC_TABLE[0]) +#define ROM_AUXADCAdjustValueForGainAndOffset \ + ((int32_t(*)(int32_t adcValue, int32_t gain, int32_t offset)) \ + ROM_API_AUX_ADC_TABLE[0]) #define ROM_AUXADCDisable \ - ((void (*)(void)) \ - ROM_API_AUX_ADC_TABLE[1]) + ((void (*)(void)) \ + ROM_API_AUX_ADC_TABLE[1]) #define ROM_AUXADCDisableInputScaling \ - ((void (*)(void)) \ - ROM_API_AUX_ADC_TABLE[2]) + ((void (*)(void)) \ + ROM_API_AUX_ADC_TABLE[2]) -#define ROM_AUXADCEnableAsync \ +#define ROM_AUXADCEnableAsync \ ((void (*)(uint32_t refSource, uint32_t trigger)) \ - ROM_API_AUX_ADC_TABLE[3]) + ROM_API_AUX_ADC_TABLE[3]) -#define ROM_AUXADCEnableSync \ +#define ROM_AUXADCEnableSync \ ((void (*)(uint32_t refSource, uint32_t sampleTime, uint32_t trigger)) \ - ROM_API_AUX_ADC_TABLE[4]) + ROM_API_AUX_ADC_TABLE[4]) #define ROM_AUXADCFlushFifo \ - ((void (*)(void)) \ - ROM_API_AUX_ADC_TABLE[5]) + ((void (*)(void)) \ + ROM_API_AUX_ADC_TABLE[5]) -#define ROM_AUXADCGetAdjustmentGain \ - ((int32_t (*)(uint32_t refSource)) \ - ROM_API_AUX_ADC_TABLE[6]) +#define ROM_AUXADCGetAdjustmentGain \ + ((int32_t(*)(uint32_t refSource)) \ + ROM_API_AUX_ADC_TABLE[6]) #define ROM_AUXADCGetAdjustmentOffset \ - ((int32_t (*)(uint32_t refSource)) \ - ROM_API_AUX_ADC_TABLE[7]) + ((int32_t(*)(uint32_t refSource)) \ + ROM_API_AUX_ADC_TABLE[7]) -#define ROM_AUXADCMicrovoltsToValue \ - ((int32_t (*)(int32_t fixedRefVoltage, int32_t microvolts)) \ - ROM_API_AUX_ADC_TABLE[8]) +#define ROM_AUXADCMicrovoltsToValue \ + ((int32_t(*)(int32_t fixedRefVoltage, int32_t microvolts)) \ + ROM_API_AUX_ADC_TABLE[8]) #define ROM_AUXADCPopFifo \ - ((uint32_t (*)(void)) \ - ROM_API_AUX_ADC_TABLE[9]) + ((uint32_t(*)(void)) \ + ROM_API_AUX_ADC_TABLE[9]) #define ROM_AUXADCReadFifo \ - ((uint32_t (*)(void)) \ - ROM_API_AUX_ADC_TABLE[10]) + ((uint32_t(*)(void)) \ + ROM_API_AUX_ADC_TABLE[10]) -#define ROM_AUXADCUnadjustValueForGainAndOffset \ - ((int32_t (*)(int32_t adcValue, int32_t gain, int32_t offset)) \ - ROM_API_AUX_ADC_TABLE[11]) - -#define ROM_AUXADCValueToMicrovolts \ - ((int32_t (*)(int32_t fixedRefVoltage, int32_t adcValue)) \ - ROM_API_AUX_ADC_TABLE[12]) +#define ROM_AUXADCUnadjustValueForGainAndOffset \ + ((int32_t(*)(int32_t adcValue, int32_t gain, int32_t offset)) \ + ROM_API_AUX_ADC_TABLE[11]) +#define ROM_AUXADCValueToMicrovolts \ + ((int32_t(*)(int32_t fixedRefVoltage, int32_t adcValue)) \ + ROM_API_AUX_ADC_TABLE[12]) // SYS_CTRL FUNCTIONS #define ROM_SysCtrlResetSourceGet \ - ((uint32_t (*)(void)) \ - ROM_API_SYS_CTRL_TABLE[0]) + ((uint32_t(*)(void)) \ + ROM_API_SYS_CTRL_TABLE[0]) #define ROM_SysCtrl_DCDC_VoltageConditionalControl \ - ((void (*)(void)) \ - ROM_API_SYS_CTRL_TABLE[1]) - + ((void (*)(void)) \ + ROM_API_SYS_CTRL_TABLE[1]) // AON_BATMON FUNCTIONS #define ROM_AONBatMonTemperatureGetDegC \ - ((int32_t (*)(void)) \ - ROM_API_AON_BATMON_TABLE[0]) - + ((int32_t(*)(void)) \ + ROM_API_AON_BATMON_TABLE[0]) // SETUP_ROM FUNCTIONS #define ROM_SetupAfterColdResetWakeupFromShutDownCfg1 \ - ((void (*)(uint32_t ccfg_ModeConfReg)) \ - ROM_API_SETUP_ROM_TABLE[0]) + ((void (*)(uint32_t ccfg_ModeConfReg)) \ + ROM_API_SETUP_ROM_TABLE[0]) -#define ROM_SetupAfterColdResetWakeupFromShutDownCfg2 \ +#define ROM_SetupAfterColdResetWakeupFromShutDownCfg2 \ ((void (*)(uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg)) \ - ROM_API_SETUP_ROM_TABLE[1]) + ROM_API_SETUP_ROM_TABLE[1]) #define ROM_SetupAfterColdResetWakeupFromShutDownCfg3 \ - ((void (*)(uint32_t ccfg_ModeConfReg)) \ - ROM_API_SETUP_ROM_TABLE[2]) + ((void (*)(uint32_t ccfg_ModeConfReg)) \ + ROM_API_SETUP_ROM_TABLE[2]) -#define ROM_SetupGetTrimForAdcShModeEn \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ - ROM_API_SETUP_ROM_TABLE[3]) +#define ROM_SetupGetTrimForAdcShModeEn \ + ((uint32_t(*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[3]) -#define ROM_SetupGetTrimForAdcShVbufEn \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ - ROM_API_SETUP_ROM_TABLE[4]) +#define ROM_SetupGetTrimForAdcShVbufEn \ + ((uint32_t(*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[4]) -#define ROM_SetupGetTrimForAmpcompCtrl \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ - ROM_API_SETUP_ROM_TABLE[5]) +#define ROM_SetupGetTrimForAmpcompCtrl \ + ((uint32_t(*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[5]) #define ROM_SetupGetTrimForAmpcompTh1 \ - ((uint32_t (*)(void)) \ - ROM_API_SETUP_ROM_TABLE[6]) + ((uint32_t(*)(void)) \ + ROM_API_SETUP_ROM_TABLE[6]) #define ROM_SetupGetTrimForAmpcompTh2 \ - ((uint32_t (*)(void)) \ - ROM_API_SETUP_ROM_TABLE[7]) + ((uint32_t(*)(void)) \ + ROM_API_SETUP_ROM_TABLE[7]) -#define ROM_SetupGetTrimForAnabypassValue1 \ - ((uint32_t (*)(uint32_t ccfg_ModeConfReg)) \ - ROM_API_SETUP_ROM_TABLE[8]) +#define ROM_SetupGetTrimForAnabypassValue1 \ + ((uint32_t(*)(uint32_t ccfg_ModeConfReg)) \ + ROM_API_SETUP_ROM_TABLE[8]) #define ROM_SetupGetTrimForDblrLoopFilterResetVoltage \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ - ROM_API_SETUP_ROM_TABLE[9]) + ((uint32_t(*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[9]) -#define ROM_SetupGetTrimForRadcExtCfg \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ - ROM_API_SETUP_ROM_TABLE[10]) +#define ROM_SetupGetTrimForRadcExtCfg \ + ((uint32_t(*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[10]) -#define ROM_SetupGetTrimForRcOscLfIBiasTrim \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ - ROM_API_SETUP_ROM_TABLE[11]) +#define ROM_SetupGetTrimForRcOscLfIBiasTrim \ + ((uint32_t(*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[11]) #define ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim \ - ((uint32_t (*)(void)) \ - ROM_API_SETUP_ROM_TABLE[12]) + ((uint32_t(*)(void)) \ + ROM_API_SETUP_ROM_TABLE[12]) -#define ROM_SetupGetTrimForXoscHfCtl \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ - ROM_API_SETUP_ROM_TABLE[13]) +#define ROM_SetupGetTrimForXoscHfCtl \ + ((uint32_t(*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[13]) #define ROM_SetupGetTrimForXoscHfFastStart \ - ((uint32_t (*)(void)) \ - ROM_API_SETUP_ROM_TABLE[14]) + ((uint32_t(*)(void)) \ + ROM_API_SETUP_ROM_TABLE[14]) #define ROM_SetupGetTrimForXoscHfIbiastherm \ - ((uint32_t (*)(void)) \ - ROM_API_SETUP_ROM_TABLE[15]) + ((uint32_t(*)(void)) \ + ROM_API_SETUP_ROM_TABLE[15]) #define ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ - ROM_API_SETUP_ROM_TABLE[16]) + ((uint32_t(*)(uint32_t ui32Fcfg1Revision)) \ + ROM_API_SETUP_ROM_TABLE[16]) #define ROM_SetupSetAonRtcSubSecInc \ ((void (*)(uint32_t subSecInc)) \ - ROM_API_SETUP_ROM_TABLE[17]) + ROM_API_SETUP_ROM_TABLE[17]) #define ROM_SetupSetCacheModeAccordingToCcfgSetting \ - ((void (*)(void)) \ - ROM_API_SETUP_ROM_TABLE[18]) + ((void (*)(void)) \ + ROM_API_SETUP_ROM_TABLE[18]) -#define ROM_SetupStepVddrTrimTo \ +#define ROM_SetupStepVddrTrimTo \ ((void (*)(uint32_t toCode)) \ - ROM_API_SETUP_ROM_TABLE[19]) - + ROM_API_SETUP_ROM_TABLE[19]) // I2S FUNCTIONS -#define ROM_I2SPointerSet \ - ((void (*)(uint32_t ui32Base, bool bInput, void * pNextPointer)) \ - ROM_API_I2S_TABLE[0]) - -#define ROM_I2SSampleStampGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32Channel)) \ - ROM_API_I2S_TABLE[1]) +#define ROM_I2SPointerSet \ + ((void (*)(uint32_t ui32Base, bool bInput, void *pNextPointer)) \ + ROM_API_I2S_TABLE[0]) +#define ROM_I2SSampleStampGet \ + ((uint32_t(*)(uint32_t ui32Base, uint32_t ui32Channel)) \ + ROM_API_I2S_TABLE[1]) // PWR_CTRL FUNCTIONS -#define ROM_PowerCtrlSourceSet \ +#define ROM_PowerCtrlSourceSet \ ((void (*)(uint32_t ui32PowerConfig)) \ - ROM_API_PWR_CTRL_TABLE[0]) - + ROM_API_PWR_CTRL_TABLE[0]) // AES FUNCTIONS -#define ROM_AESConfigureCCMCtrl \ +#define ROM_AESConfigureCCMCtrl \ ((void (*)(uint32_t nonceLength, uint32_t macLength, bool encrypt)) \ - ROM_API_AES_TABLE[0]) + ROM_API_AES_TABLE[0]) -#define ROM_AESReadFromKeyStore \ - ((uint32_t (*)(uint32_t keyStoreArea)) \ - ROM_API_AES_TABLE[1]) +#define ROM_AESReadFromKeyStore \ + ((uint32_t(*)(uint32_t keyStoreArea)) \ + ROM_API_AES_TABLE[1]) -#define ROM_AESReadTag \ - ((uint32_t (*)(uint8_t *tag, uint32_t tagLength)) \ - ROM_API_AES_TABLE[2]) +#define ROM_AESReadTag \ + ((uint32_t(*)(uint8_t * tag, uint32_t tagLength)) \ + ROM_API_AES_TABLE[2]) -#define ROM_AESSetInitializationVector \ +#define ROM_AESSetInitializationVector \ ((void (*)(const uint32_t *initializationVector)) \ - ROM_API_AES_TABLE[3]) + ROM_API_AES_TABLE[3]) -#define ROM_AESStartDMAOperation \ +#define ROM_AESStartDMAOperation \ ((void (*)(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length)) \ - ROM_API_AES_TABLE[4]) + ROM_API_AES_TABLE[4]) -#define ROM_AESVerifyTag \ - ((uint32_t (*)(const uint8_t *tag, uint32_t tagLength)) \ - ROM_API_AES_TABLE[5]) +#define ROM_AESVerifyTag \ + ((uint32_t(*)(const uint8_t *tag, uint32_t tagLength)) \ + ROM_API_AES_TABLE[5]) -#define ROM_AESWaitForIRQFlags \ - ((uint32_t (*)(uint32_t irqFlags)) \ - ROM_API_AES_TABLE[6]) +#define ROM_AESWaitForIRQFlags \ + ((uint32_t(*)(uint32_t irqFlags)) \ + ROM_API_AES_TABLE[6]) -#define ROM_AESWriteCCMInitializationVector \ +#define ROM_AESWriteCCMInitializationVector \ ((void (*)(const uint8_t *nonce, uint32_t nonceLength)) \ - ROM_API_AES_TABLE[7]) - -#define ROM_AESWriteToKeyStore \ - ((uint32_t (*)(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea)) \ - ROM_API_AES_TABLE[8]) + ROM_API_AES_TABLE[7]) +#define ROM_AESWriteToKeyStore \ + ((uint32_t(*)(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea)) \ + ROM_API_AES_TABLE[8]) // PKA FUNCTIONS -#define ROM_PKABigNumAddGetResult \ - ((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[0]) +#define ROM_PKABigNumAddGetResult \ + ((uint32_t(*)(uint8_t * resultBuf, uint32_t * resultLength, uint32_t resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[0]) #define ROM_PKABigNumCmpGetResult \ - ((uint32_t (*)(void)) \ - ROM_API_PKA_TABLE[1]) + ((uint32_t(*)(void)) \ + ROM_API_PKA_TABLE[1]) -#define ROM_PKABigNumInvModGetResult \ - ((uint32_t (*)(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[2]) +#define ROM_PKABigNumInvModGetResult \ + ((uint32_t(*)(uint8_t * resultBuf, uint32_t length, uint32_t resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[2]) -#define ROM_PKABigNumModGetResult \ - ((uint32_t (*)(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[3]) +#define ROM_PKABigNumModGetResult \ + ((uint32_t(*)(uint8_t * resultBuf, uint32_t length, uint32_t resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[3]) -#define ROM_PKABigNumMultGetResult \ - ((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[4]) +#define ROM_PKABigNumMultGetResult \ + ((uint32_t(*)(uint8_t * resultBuf, uint32_t * resultLength, uint32_t resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[4]) -#define ROM_PKAEccAddGetResult \ - ((uint32_t (*)(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length)) \ - ROM_API_PKA_TABLE[5]) +#define ROM_PKAEccAddGetResult \ + ((uint32_t(*)(uint8_t * curvePointX, uint8_t * curvePointY, uint32_t resultPKAMemAddr, uint32_t length)) \ + ROM_API_PKA_TABLE[5]) -#define ROM_PKAEccAddStart \ - ((uint32_t (*)(const uint8_t *curvePoint1X, const uint8_t *curvePoint1Y, const uint8_t *curvePoint2X, const uint8_t *curvePoint2Y, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[6]) +#define ROM_PKAEccAddStart \ + ((uint32_t(*)(const uint8_t *curvePoint1X, const uint8_t *curvePoint1Y, const uint8_t *curvePoint2X, const uint8_t *curvePoint2Y, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[6]) -#define ROM_PKAEccMultiplyGetResult \ - ((uint32_t (*)(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length)) \ - ROM_API_PKA_TABLE[7]) +#define ROM_PKAEccMultiplyGetResult \ + ((uint32_t(*)(uint8_t * curvePointX, uint8_t * curvePointY, uint32_t resultPKAMemAddr, uint32_t length)) \ + ROM_API_PKA_TABLE[7]) -#define ROM_PKAEccMultiplyStart \ - ((uint32_t (*)(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, uint32_t length, uint32_t *resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[8]) +#define ROM_PKAEccMultiplyStart \ + ((uint32_t(*)(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, uint32_t length, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[8]) #define ROM_PKAGetOpsStatus \ - ((uint32_t (*)(void)) \ - ROM_API_PKA_TABLE[9]) + ((uint32_t(*)(void)) \ + ROM_API_PKA_TABLE[9]) -#define ROM_PKABigNumAddStart \ - ((uint32_t (*)(const uint8_t *bigNum1, uint32_t bigNum1Length, const uint8_t *bigNum2, uint32_t bigNum2Length, uint32_t *resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[10]) +#define ROM_PKABigNumAddStart \ + ((uint32_t(*)(const uint8_t *bigNum1, uint32_t bigNum1Length, const uint8_t *bigNum2, uint32_t bigNum2Length, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[10]) -#define ROM_PKABigNumCmpStart \ - ((uint32_t (*)(const uint8_t *bigNum1, const uint8_t *bigNum2, uint32_t length)) \ - ROM_API_PKA_TABLE[11]) +#define ROM_PKABigNumCmpStart \ + ((uint32_t(*)(const uint8_t *bigNum1, const uint8_t *bigNum2, uint32_t length)) \ + ROM_API_PKA_TABLE[11]) -#define ROM_PKABigNumInvModStart \ - ((uint32_t (*)(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[12]) +#define ROM_PKABigNumInvModStart \ + ((uint32_t(*)(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[12]) -#define ROM_PKABigNumModStart \ - ((uint32_t (*)(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[13]) +#define ROM_PKABigNumModStart \ + ((uint32_t(*)(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[13]) -#define ROM_PKABigNumMultiplyStart \ - ((uint32_t (*)(const uint8_t *multiplicand, uint32_t multiplicandLength, const uint8_t *multiplier, uint32_t multiplierLength, uint32_t *resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[14]) +#define ROM_PKABigNumMultiplyStart \ + ((uint32_t(*)(const uint8_t *multiplicand, uint32_t multiplicandLength, const uint8_t *multiplier, uint32_t multiplierLength, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[14]) -#define ROM_PKABigNumSubGetResult \ - ((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[15]) +#define ROM_PKABigNumSubGetResult \ + ((uint32_t(*)(uint8_t * resultBuf, uint32_t * resultLength, uint32_t resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[15]) -#define ROM_PKABigNumSubStart \ - ((uint32_t (*)(const uint8_t *minuend, uint32_t minuendLength, const uint8_t *subtrahend, uint32_t subtrahendLength, uint32_t *resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[16]) +#define ROM_PKABigNumSubStart \ + ((uint32_t(*)(const uint8_t *minuend, uint32_t minuendLength, const uint8_t *subtrahend, uint32_t subtrahendLength, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[16]) -#define ROM_PKAArrayAllZeros \ +#define ROM_PKAArrayAllZeros \ ((bool (*)(const uint8_t *array, uint32_t arrayLength)) \ - ROM_API_PKA_TABLE[17]) + ROM_API_PKA_TABLE[17]) -#define ROM_PKABigNumDivideGetQuotient \ - ((uint32_t (*)(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr)) \ - ROM_API_PKA_TABLE[18]) +#define ROM_PKABigNumDivideGetQuotient \ + ((uint32_t(*)(uint8_t * resultBuf, uint32_t * length, uint32_t resultQuotientMemAddr)) \ + ROM_API_PKA_TABLE[18]) -#define ROM_PKABigNumDivideGetRemainder \ - ((uint32_t (*)(uint8_t *resultBuf, uint32_t *length, uint32_t resultRemainderMemAddr)) \ - ROM_API_PKA_TABLE[19]) +#define ROM_PKABigNumDivideGetRemainder \ + ((uint32_t(*)(uint8_t * resultBuf, uint32_t * length, uint32_t resultRemainderMemAddr)) \ + ROM_API_PKA_TABLE[19]) -#define ROM_PKABigNumDivideStart \ - ((uint32_t (*)(const uint8_t *dividend, uint32_t dividendLength, const uint8_t *divisor, uint32_t divisorLength, uint32_t *resultQuotientMemAddr, uint32_t *resultRemainderMemAddr)) \ - ROM_API_PKA_TABLE[20]) +#define ROM_PKABigNumDivideStart \ + ((uint32_t(*)(const uint8_t *dividend, uint32_t dividendLength, const uint8_t *divisor, uint32_t divisorLength, uint32_t *resultQuotientMemAddr, uint32_t *resultRemainderMemAddr)) \ + ROM_API_PKA_TABLE[20]) -#define ROM_PKAEccVerifyPublicKeyWeierstrassStart \ - ((uint32_t (*)(const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, const uint8_t *order, uint32_t length)) \ - ROM_API_PKA_TABLE[21]) +#define ROM_PKAEccVerifyPublicKeyWeierstrassStart \ + ((uint32_t(*)(const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, const uint8_t *order, uint32_t length)) \ + ROM_API_PKA_TABLE[21]) -#define ROM_PKAZeroOutArray \ +#define ROM_PKAZeroOutArray \ ((void (*)(const uint8_t *array, uint32_t arrayLength)) \ - ROM_API_PKA_TABLE[22]) - -#define ROM_PKAEccMontgomeryMultiplyStart \ - ((uint32_t (*)(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[23]) + ROM_API_PKA_TABLE[22]) +#define ROM_PKAEccMontgomeryMultiplyStart \ + ((uint32_t(*)(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr)) \ + ROM_API_PKA_TABLE[23]) // SHA2 FUNCTIONS -#define ROM_SHA2ComputeFinalHash \ - ((uint32_t (*)(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm)) \ - ROM_API_SHA2_TABLE[0]) +#define ROM_SHA2ComputeFinalHash \ + ((uint32_t(*)(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm)) \ + ROM_API_SHA2_TABLE[0]) -#define ROM_SHA2ComputeHash \ - ((uint32_t (*)(const uint8_t *message, uint8_t *resultDigest, uint32_t totalMsgLength, uint32_t hashAlgorithm)) \ - ROM_API_SHA2_TABLE[1]) +#define ROM_SHA2ComputeHash \ + ((uint32_t(*)(const uint8_t *message, uint8_t *resultDigest, uint32_t totalMsgLength, uint32_t hashAlgorithm)) \ + ROM_API_SHA2_TABLE[1]) -#define ROM_SHA2ComputeInitialHash \ - ((uint32_t (*)(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t initialMessageLength)) \ - ROM_API_SHA2_TABLE[2]) +#define ROM_SHA2ComputeInitialHash \ + ((uint32_t(*)(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t initialMessageLength)) \ + ROM_API_SHA2_TABLE[2]) -#define ROM_SHA2ComputeIntermediateHash \ - ((uint32_t (*)(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t intermediateMessageLength)) \ - ROM_API_SHA2_TABLE[3]) - -#define ROM_SHA2StartDMAOperation \ - ((void (*)(uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length)) \ - ROM_API_SHA2_TABLE[4]) - -#define ROM_SHA2WaitForIRQFlags \ - ((uint32_t (*)(uint32_t irqFlags)) \ - ROM_API_SHA2_TABLE[5]) +#define ROM_SHA2ComputeIntermediateHash \ + ((uint32_t(*)(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t intermediateMessageLength)) \ + ROM_API_SHA2_TABLE[3]) +#define ROM_SHA2StartDMAOperation \ + ((void (*)(uint8_t * channel0Addr, uint32_t channel0Length, uint8_t * channel1Addr, uint32_t channel1Length)) \ + ROM_API_SHA2_TABLE[4]) +#define ROM_SHA2WaitForIRQFlags \ + ((uint32_t(*)(uint32_t irqFlags)) \ + ROM_API_SHA2_TABLE[5]) //***************************************************************************** // diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.h index 391db99..74da8cf 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.h @@ -1,41 +1,41 @@ /****************************************************************************** -* Filename: rom_crypto.h -* Revised: 2018-09-17 09:24:56 +0200 (Mon, 17 Sep 2018) -* Revision: 52624 -* -* Description: This header file is the API to the crypto functions -* built into ROM on the CC13xx/CC26xx. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -*******************************************************************************/ + * Filename: rom_crypto.h + * Revised: 2018-09-17 09:24:56 +0200 (Mon, 17 Sep 2018) + * Revision: 52624 + * + * Description: This header file is the API to the crypto functions + * built into ROM on the CC13xx/CC26xx. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ //***************************************************************************** // @@ -50,8 +50,7 @@ #define ROM_CRYPTO_H #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif ////////////////////////////////////* ECC *///////////////////////////////////// @@ -75,42 +74,42 @@ extern "C" * ECC Return Status Flags. */ // Scalar multiplication status -#define ECC_MODULUS_EVEN 0xDC -#define ECC_MODULUS_LARGER_THAN_255_WORDS 0xD2 -#define ECC_MODULUS_LENGTH_ZERO 0x08 -#define ECC_MODULUS_MSW_IS_ZERO 0x30 -#define ECC_SCALAR_TOO_LONG 0x35 -#define ECC_SCALAR_LENGTH_ZERO 0x53 -#define ECC_ORDER_TOO_LONG 0xC6 -#define ECC_ORDER_LENGTH_ZERO 0x6C -#define ECC_X_COORD_TOO_LONG 0x3C -#define ECC_X_COORD_LENGTH_ZERO 0xC3 -#define ECC_Y_COORD_TOO_LONG 0x65 -#define ECC_Y_COORD_LENGTH_ZERO 0x56 -#define ECC_A_COEF_TOO_LONG 0x5C -#define ECC_A_COEF_LENGTH_ZERO 0xC5 -#define ECC_BAD_WINDOW_SIZE 0x66 -#define ECC_SCALAR_MUL_OK 0x99 +#define ECC_MODULUS_EVEN 0xDC +#define ECC_MODULUS_LARGER_THAN_255_WORDS 0xD2 +#define ECC_MODULUS_LENGTH_ZERO 0x08 +#define ECC_MODULUS_MSW_IS_ZERO 0x30 +#define ECC_SCALAR_TOO_LONG 0x35 +#define ECC_SCALAR_LENGTH_ZERO 0x53 +#define ECC_ORDER_TOO_LONG 0xC6 +#define ECC_ORDER_LENGTH_ZERO 0x6C +#define ECC_X_COORD_TOO_LONG 0x3C +#define ECC_X_COORD_LENGTH_ZERO 0xC3 +#define ECC_Y_COORD_TOO_LONG 0x65 +#define ECC_Y_COORD_LENGTH_ZERO 0x56 +#define ECC_A_COEF_TOO_LONG 0x5C +#define ECC_A_COEF_LENGTH_ZERO 0xC5 +#define ECC_BAD_WINDOW_SIZE 0x66 +#define ECC_SCALAR_MUL_OK 0x99 // ECDSA and ECDH status -#define ECC_ORDER_LARGER_THAN_255_WORDS 0x28 -#define ECC_ORDER_EVEN 0x82 -#define ECC_ORDER_MSW_IS_ZERO 0x23 -#define ECC_ECC_KEY_TOO_LONG 0x25 -#define ECC_ECC_KEY_LENGTH_ZERO 0x52 -#define ECC_DIGEST_TOO_LONG 0x27 -#define ECC_DIGEST_LENGTH_ZERO 0x72 -#define ECC_ECDSA_SIGN_OK 0x32 -#define ECC_ECDSA_INVALID_SIGNATURE 0x5A -#define ECC_ECDSA_VALID_SIGNATURE 0xA5 -#define ECC_SIG_P1_TOO_LONG 0x11 -#define ECC_SIG_P1_LENGTH_ZERO 0x12 -#define ECC_SIG_P2_TOO_LONG 0x22 -#define ECC_SIG_P2_LENGTH_ZERO 0x21 +#define ECC_ORDER_LARGER_THAN_255_WORDS 0x28 +#define ECC_ORDER_EVEN 0x82 +#define ECC_ORDER_MSW_IS_ZERO 0x23 +#define ECC_ECC_KEY_TOO_LONG 0x25 +#define ECC_ECC_KEY_LENGTH_ZERO 0x52 +#define ECC_DIGEST_TOO_LONG 0x27 +#define ECC_DIGEST_LENGTH_ZERO 0x72 +#define ECC_ECDSA_SIGN_OK 0x32 +#define ECC_ECDSA_INVALID_SIGNATURE 0x5A +#define ECC_ECDSA_VALID_SIGNATURE 0xA5 +#define ECC_SIG_P1_TOO_LONG 0x11 +#define ECC_SIG_P1_LENGTH_ZERO 0x12 +#define ECC_SIG_P2_TOO_LONG 0x22 +#define ECC_SIG_P2_LENGTH_ZERO 0x21 -#define ECC_ECDSA_KEYGEN_OK ECC_SCALAR_MUL_OK -#define ECC_ECDH_KEYGEN_OK ECC_SCALAR_MUL_OK -#define ECC_ECDH_COMMON_KEY_OK ECC_SCALAR_MUL_OK +#define ECC_ECDSA_KEYGEN_OK ECC_SCALAR_MUL_OK +#define ECC_ECDH_KEYGEN_OK ECC_SCALAR_MUL_OK +#define ECC_ECDH_COMMON_KEY_OK ECC_SCALAR_MUL_OK //***************************************************************************** /*! @@ -130,17 +129,17 @@ extern void ECC_initialize(uint32_t* pWorkzone); //***************************************************************************** /*! -* \brief Generate a key. -* -* This is used for both ECDH and ECDSA. -* -* \param randString Pointer to random string, input. -* \param privateKey Pointer to the private key, output. -* \param publicKey_x Pointer to public key X-coordinate, output. -* \param publicKey_y Pointer to public key Y-coordinate, output. -* -* \return Status -*/ + * \brief Generate a key. + * + * This is used for both ECDH and ECDSA. + * + * \param randString Pointer to random string, input. + * \param privateKey Pointer to the private key, output. + * \param publicKey_x Pointer to public key X-coordinate, output. + * \param publicKey_y Pointer to public key Y-coordinate, output. + * + * \return Status + */ //***************************************************************************** extern uint8_t ECC_generateKey(uint32_t* randString, uint32_t* privateKey, uint32_t* publicKey_x, uint32_t* publicKey_y); @@ -191,11 +190,10 @@ extern uint8_t ECC_ECDSA_verify(uint32_t* publicKey_x, uint32_t* publicKey_y, */ //***************************************************************************** extern uint8_t ECC_ECDH_computeSharedSecret(uint32_t* privateKey, - uint32_t* publicKey_x, - uint32_t* publicKey_y, - uint32_t* sharedSecret_x, - uint32_t* sharedSecret_y); - + uint32_t* publicKey_x, + uint32_t* publicKey_y, + uint32_t* sharedSecret_x, + uint32_t* sharedSecret_y); #ifdef __cplusplus } diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup.h index 923bc71..db72a66 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: setup.h -* Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) -* Revision: 52993 -* -* Description: Prototypes and defines for the setup API. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: setup.h + * Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) + * Revision: 52993 + * + * Description: Prototypes and defines for the setup API. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,8 +55,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif // Hardware headers @@ -78,7 +77,7 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define SetupTrimDevice NOROM_SetupTrimDevice +#define SetupTrimDevice NOROM_SetupTrimDevice #endif //***************************************************************************** @@ -105,7 +104,7 @@ extern "C" //! \return None // //***************************************************************************** -extern void SetupTrimDevice( void ); +extern void SetupTrimDevice(void); //***************************************************************************** // @@ -116,8 +115,8 @@ extern void SetupTrimDevice( void ); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_SetupTrimDevice -#undef SetupTrimDevice -#define SetupTrimDevice ROM_SetupTrimDevice +#undef SetupTrimDevice +#define SetupTrimDevice ROM_SetupTrimDevice #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_doc.h index 07ab97e..1b46e56 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: setup_doc.h -* Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017) -* Revision: 49096 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: setup_doc.h + * Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017) + * Revision: 49096 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup setup_api //! @{ //! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.h index cea180c..067c62f 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: setup_rom.h -* Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) -* Revision: 52993 -* -* Description: Prototypes and defines for the setup API. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: setup_rom.h + * Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) + * Revision: 52993 + * + * Description: Prototypes and defines for the setup API. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,8 +55,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif // Hardware headers @@ -81,23 +80,23 @@ extern "C" #define SetupAfterColdResetWakeupFromShutDownCfg1 NOROM_SetupAfterColdResetWakeupFromShutDownCfg1 #define SetupAfterColdResetWakeupFromShutDownCfg2 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2 #define SetupAfterColdResetWakeupFromShutDownCfg3 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3 -#define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn -#define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn -#define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl -#define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1 -#define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2 -#define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1 +#define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn +#define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn +#define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl +#define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1 +#define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2 +#define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1 #define SetupGetTrimForDblrLoopFilterResetVoltage NOROM_SetupGetTrimForDblrLoopFilterResetVoltage -#define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg +#define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg #define SetupGetTrimForRcOscLfIBiasTrim NOROM_SetupGetTrimForRcOscLfIBiasTrim #define SetupGetTrimForRcOscLfRtuneCtuneTrim NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim -#define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl -#define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart +#define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl +#define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart #define SetupGetTrimForXoscHfIbiastherm NOROM_SetupGetTrimForXoscHfIbiastherm #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio #define SetupSetCacheModeAccordingToCcfgSetting NOROM_SetupSetCacheModeAccordingToCcfgSetting -#define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc -#define SetupStepVddrTrimTo NOROM_SetupStepVddrTrimTo +#define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc +#define SetupStepVddrTrimTo NOROM_SetupStepVddrTrimTo #endif //***************************************************************************** @@ -119,7 +118,7 @@ extern "C" //! \return None // //***************************************************************************** -extern void SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg ); +extern void SetupAfterColdResetWakeupFromShutDownCfg1(uint32_t ccfg_ModeConfReg); //***************************************************************************** // @@ -135,7 +134,7 @@ extern void SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg //! \return None // //***************************************************************************** -extern void SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg ); +extern void SetupAfterColdResetWakeupFromShutDownCfg2(uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg); //***************************************************************************** // @@ -155,7 +154,7 @@ extern void SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revisio //! \return None // //***************************************************************************** -extern void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ); +extern void SetupAfterColdResetWakeupFromShutDownCfg3(uint32_t ccfg_ModeConfReg); //***************************************************************************** // @@ -166,7 +165,7 @@ extern void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg //! \return Returns the trim value from FCFG1. // //***************************************************************************** -extern uint32_t SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForAdcShModeEn(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -177,7 +176,7 @@ extern uint32_t SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision ); //! \return Returns the trim value from FCFG1. // //***************************************************************************** -extern uint32_t SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForAdcShVbufEn(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -188,7 +187,7 @@ extern uint32_t SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForAmpcompCtrl(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -197,7 +196,7 @@ extern uint32_t SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForAmpcompTh1( void ); +extern uint32_t SetupGetTrimForAmpcompTh1(void); //***************************************************************************** // @@ -206,7 +205,7 @@ extern uint32_t SetupGetTrimForAmpcompTh1( void ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForAmpcompTh2( void ); +extern uint32_t SetupGetTrimForAmpcompTh2(void); //***************************************************************************** // @@ -217,7 +216,7 @@ extern uint32_t SetupGetTrimForAmpcompTh2( void ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ); +extern uint32_t SetupGetTrimForAnabypassValue1(uint32_t ccfg_ModeConfReg); //***************************************************************************** // @@ -228,7 +227,7 @@ extern uint32_t SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ); //! \return Returns the trim value from FCFG1. // //***************************************************************************** -extern uint32_t SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForDblrLoopFilterResetVoltage(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -239,7 +238,7 @@ extern uint32_t SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Rev //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForRadcExtCfg(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -250,7 +249,7 @@ extern uint32_t SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision ); //! \return Returns the trim value from FCFG1. // //***************************************************************************** -extern uint32_t SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForRcOscLfIBiasTrim(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -260,7 +259,7 @@ extern uint32_t SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim( void ); +extern uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim(void); //***************************************************************************** // @@ -271,7 +270,7 @@ extern uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim( void ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForXoscHfCtl(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -280,7 +279,7 @@ extern uint32_t SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForXoscHfFastStart( void ); +extern uint32_t SetupGetTrimForXoscHfFastStart(void); //***************************************************************************** // @@ -290,7 +289,7 @@ extern uint32_t SetupGetTrimForXoscHfFastStart( void ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForXoscHfIbiastherm( void ); +extern uint32_t SetupGetTrimForXoscHfIbiastherm(void); //***************************************************************************** // @@ -302,7 +301,7 @@ extern uint32_t SetupGetTrimForXoscHfIbiastherm( void ); //! \return Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet. // //***************************************************************************** -extern uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -314,18 +313,18 @@ extern uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg // //***************************************************************************** __STATIC_INLINE int32_t -SetupSignExtendVddrTrimValue( uint32_t ui32VddrTrimVal ) +SetupSignExtendVddrTrimValue(uint32_t ui32VddrTrimVal) { // The VDDR trim value is 5 bits representing the range from -10 to +21 // (where -10=0x16, -1=0x1F, 0=0x00, 1=0x01 and +21=0x15) int32_t i32SignedVddrVal = ui32VddrTrimVal; - if ( i32SignedVddrVal > 0x15 ) + if (i32SignedVddrVal > 0x15) { i32SignedVddrVal -= 0x20; } - return ( i32SignedVddrVal ); + return (i32SignedVddrVal); } //***************************************************************************** @@ -335,7 +334,7 @@ SetupSignExtendVddrTrimValue( uint32_t ui32VddrTrimVal ) //! \return None // //***************************************************************************** -extern void SetupSetCacheModeAccordingToCcfgSetting( void ); +extern void SetupSetCacheModeAccordingToCcfgSetting(void); //***************************************************************************** // @@ -346,7 +345,7 @@ extern void SetupSetCacheModeAccordingToCcfgSetting( void ); //! \return None // //***************************************************************************** -extern void SetupSetAonRtcSubSecInc( uint32_t subSecInc ); +extern void SetupSetAonRtcSubSecInc(uint32_t subSecInc); //***************************************************************************** // @@ -360,7 +359,7 @@ extern void SetupSetAonRtcSubSecInc( uint32_t subSecInc ); //! \return None // //***************************************************************************** -extern void SetupStepVddrTrimTo( uint32_t toCode ); +extern void SetupStepVddrTrimTo(uint32_t toCode); //***************************************************************************** // @@ -371,84 +370,84 @@ extern void SetupStepVddrTrimTo( uint32_t toCode ); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg1 -#undef SetupAfterColdResetWakeupFromShutDownCfg1 +#undef SetupAfterColdResetWakeupFromShutDownCfg1 #define SetupAfterColdResetWakeupFromShutDownCfg1 ROM_SetupAfterColdResetWakeupFromShutDownCfg1 #endif #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg2 -#undef SetupAfterColdResetWakeupFromShutDownCfg2 +#undef SetupAfterColdResetWakeupFromShutDownCfg2 #define SetupAfterColdResetWakeupFromShutDownCfg2 ROM_SetupAfterColdResetWakeupFromShutDownCfg2 #endif #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg3 -#undef SetupAfterColdResetWakeupFromShutDownCfg3 +#undef SetupAfterColdResetWakeupFromShutDownCfg3 #define SetupAfterColdResetWakeupFromShutDownCfg3 ROM_SetupAfterColdResetWakeupFromShutDownCfg3 #endif #ifdef ROM_SetupGetTrimForAdcShModeEn -#undef SetupGetTrimForAdcShModeEn -#define SetupGetTrimForAdcShModeEn ROM_SetupGetTrimForAdcShModeEn +#undef SetupGetTrimForAdcShModeEn +#define SetupGetTrimForAdcShModeEn ROM_SetupGetTrimForAdcShModeEn #endif #ifdef ROM_SetupGetTrimForAdcShVbufEn -#undef SetupGetTrimForAdcShVbufEn -#define SetupGetTrimForAdcShVbufEn ROM_SetupGetTrimForAdcShVbufEn +#undef SetupGetTrimForAdcShVbufEn +#define SetupGetTrimForAdcShVbufEn ROM_SetupGetTrimForAdcShVbufEn #endif #ifdef ROM_SetupGetTrimForAmpcompCtrl -#undef SetupGetTrimForAmpcompCtrl -#define SetupGetTrimForAmpcompCtrl ROM_SetupGetTrimForAmpcompCtrl +#undef SetupGetTrimForAmpcompCtrl +#define SetupGetTrimForAmpcompCtrl ROM_SetupGetTrimForAmpcompCtrl #endif #ifdef ROM_SetupGetTrimForAmpcompTh1 -#undef SetupGetTrimForAmpcompTh1 -#define SetupGetTrimForAmpcompTh1 ROM_SetupGetTrimForAmpcompTh1 +#undef SetupGetTrimForAmpcompTh1 +#define SetupGetTrimForAmpcompTh1 ROM_SetupGetTrimForAmpcompTh1 #endif #ifdef ROM_SetupGetTrimForAmpcompTh2 -#undef SetupGetTrimForAmpcompTh2 -#define SetupGetTrimForAmpcompTh2 ROM_SetupGetTrimForAmpcompTh2 +#undef SetupGetTrimForAmpcompTh2 +#define SetupGetTrimForAmpcompTh2 ROM_SetupGetTrimForAmpcompTh2 #endif #ifdef ROM_SetupGetTrimForAnabypassValue1 -#undef SetupGetTrimForAnabypassValue1 -#define SetupGetTrimForAnabypassValue1 ROM_SetupGetTrimForAnabypassValue1 +#undef SetupGetTrimForAnabypassValue1 +#define SetupGetTrimForAnabypassValue1 ROM_SetupGetTrimForAnabypassValue1 #endif #ifdef ROM_SetupGetTrimForDblrLoopFilterResetVoltage -#undef SetupGetTrimForDblrLoopFilterResetVoltage +#undef SetupGetTrimForDblrLoopFilterResetVoltage #define SetupGetTrimForDblrLoopFilterResetVoltage ROM_SetupGetTrimForDblrLoopFilterResetVoltage #endif #ifdef ROM_SetupGetTrimForRadcExtCfg -#undef SetupGetTrimForRadcExtCfg -#define SetupGetTrimForRadcExtCfg ROM_SetupGetTrimForRadcExtCfg +#undef SetupGetTrimForRadcExtCfg +#define SetupGetTrimForRadcExtCfg ROM_SetupGetTrimForRadcExtCfg #endif #ifdef ROM_SetupGetTrimForRcOscLfIBiasTrim -#undef SetupGetTrimForRcOscLfIBiasTrim +#undef SetupGetTrimForRcOscLfIBiasTrim #define SetupGetTrimForRcOscLfIBiasTrim ROM_SetupGetTrimForRcOscLfIBiasTrim #endif #ifdef ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim -#undef SetupGetTrimForRcOscLfRtuneCtuneTrim +#undef SetupGetTrimForRcOscLfRtuneCtuneTrim #define SetupGetTrimForRcOscLfRtuneCtuneTrim ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim #endif #ifdef ROM_SetupGetTrimForXoscHfCtl -#undef SetupGetTrimForXoscHfCtl -#define SetupGetTrimForXoscHfCtl ROM_SetupGetTrimForXoscHfCtl +#undef SetupGetTrimForXoscHfCtl +#define SetupGetTrimForXoscHfCtl ROM_SetupGetTrimForXoscHfCtl #endif #ifdef ROM_SetupGetTrimForXoscHfFastStart -#undef SetupGetTrimForXoscHfFastStart -#define SetupGetTrimForXoscHfFastStart ROM_SetupGetTrimForXoscHfFastStart +#undef SetupGetTrimForXoscHfFastStart +#define SetupGetTrimForXoscHfFastStart ROM_SetupGetTrimForXoscHfFastStart #endif #ifdef ROM_SetupGetTrimForXoscHfIbiastherm -#undef SetupGetTrimForXoscHfIbiastherm +#undef SetupGetTrimForXoscHfIbiastherm #define SetupGetTrimForXoscHfIbiastherm ROM_SetupGetTrimForXoscHfIbiastherm #endif #ifdef ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio -#undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio +#undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio #endif #ifdef ROM_SetupSetCacheModeAccordingToCcfgSetting -#undef SetupSetCacheModeAccordingToCcfgSetting +#undef SetupSetCacheModeAccordingToCcfgSetting #define SetupSetCacheModeAccordingToCcfgSetting ROM_SetupSetCacheModeAccordingToCcfgSetting #endif #ifdef ROM_SetupSetAonRtcSubSecInc -#undef SetupSetAonRtcSubSecInc -#define SetupSetAonRtcSubSecInc ROM_SetupSetAonRtcSubSecInc +#undef SetupSetAonRtcSubSecInc +#define SetupSetAonRtcSubSecInc ROM_SetupSetAonRtcSubSecInc #endif #ifdef ROM_SetupStepVddrTrimTo -#undef SetupStepVddrTrimTo -#define SetupStepVddrTrimTo ROM_SetupStepVddrTrimTo +#undef SetupStepVddrTrimTo +#define SetupStepVddrTrimTo ROM_SetupStepVddrTrimTo #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom_doc.h index bafcf07..c8df48a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: setup_rom_doc.h -* Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017) -* Revision: 49096 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: setup_rom_doc.h + * Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017) + * Revision: 49096 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup setup_rom_api //! @{ //! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.h index 885c08e..316df78 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: sha2.h -* Revised: 2018-04-17 16:04:03 +0200 (Tue, 17 Apr 2018) -* Revision: 51893 -* -* Description: SHA-2 header file. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: sha2.h + * Revised: 2018-04-17 16:04:03 +0200 (Tue, 17 Apr 2018) + * Revision: 51893 + * + * Description: SHA-2 header file. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,21 +55,20 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_crypto.h" #include "../inc/hw_ccfg.h" +#include "../inc/hw_crypto.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "cpu.h" #include "debug.h" #include "interrupt.h" -#include "cpu.h" +#include +#include +#include //***************************************************************************** // @@ -85,12 +84,12 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define SHA2StartDMAOperation NOROM_SHA2StartDMAOperation -#define SHA2WaitForIRQFlags NOROM_SHA2WaitForIRQFlags -#define SHA2ComputeInitialHash NOROM_SHA2ComputeInitialHash -#define SHA2ComputeIntermediateHash NOROM_SHA2ComputeIntermediateHash -#define SHA2ComputeFinalHash NOROM_SHA2ComputeFinalHash -#define SHA2ComputeHash NOROM_SHA2ComputeHash +#define SHA2StartDMAOperation NOROM_SHA2StartDMAOperation +#define SHA2WaitForIRQFlags NOROM_SHA2WaitForIRQFlags +#define SHA2ComputeInitialHash NOROM_SHA2ComputeInitialHash +#define SHA2ComputeIntermediateHash NOROM_SHA2ComputeIntermediateHash +#define SHA2ComputeFinalHash NOROM_SHA2ComputeFinalHash +#define SHA2ComputeHash NOROM_SHA2ComputeHash #endif //***************************************************************************** @@ -101,10 +100,9 @@ extern "C" // function to see if it supports other interrupt status flags. // //***************************************************************************** -#define SHA2_DMA_IN_DONE (CRYPTO_IRQEN_DMA_IN_DONE_M) -#define SHA2_RESULT_RDY (CRYPTO_IRQEN_RESULT_AVAIL_M) -#define SHA2_DMA_BUS_ERR (CRYPTO_IRQCLR_DMA_BUS_ERR_M) - +#define SHA2_DMA_IN_DONE (CRYPTO_IRQEN_DMA_IN_DONE_M) +#define SHA2_RESULT_RDY (CRYPTO_IRQEN_RESULT_AVAIL_M) +#define SHA2_DMA_BUS_ERR (CRYPTO_IRQCLR_DMA_BUS_ERR_M) //***************************************************************************** // @@ -113,45 +111,43 @@ extern "C" //***************************************************************************** // SHA-2 module return codes -#define SHA2_SUCCESS 0 -#define SHA2_INVALID_ALGORITHM 1 -#define SHA2_DMA_BUSY 3 -#define SHA2_DMA_ERROR 4 -#define SHA2_DIGEST_NOT_READY 5 -#define SHA2_OLD_DIGEST_NOT_READ 6 +#define SHA2_SUCCESS 0 +#define SHA2_INVALID_ALGORITHM 1 +#define SHA2_DMA_BUSY 3 +#define SHA2_DMA_ERROR 4 +#define SHA2_DIGEST_NOT_READY 5 +#define SHA2_OLD_DIGEST_NOT_READ 6 // SHA-2 output digest lengths in bytes. -#define SHA2_SHA224_DIGEST_LENGTH_BYTES (224 / 8) -#define SHA2_SHA256_DIGEST_LENGTH_BYTES (256 / 8) -#define SHA2_SHA384_DIGEST_LENGTH_BYTES (384 / 8) -#define SHA2_SHA512_DIGEST_LENGTH_BYTES (512 / 8) +#define SHA2_SHA224_DIGEST_LENGTH_BYTES (224 / 8) +#define SHA2_SHA256_DIGEST_LENGTH_BYTES (256 / 8) +#define SHA2_SHA384_DIGEST_LENGTH_BYTES (384 / 8) +#define SHA2_SHA512_DIGEST_LENGTH_BYTES (512 / 8) -//Selectable SHA-2 modes. They determine the algorithm used and if initial -//values will be set to the default constants or not -#define SHA2_MODE_SELECT_SHA224 (CRYPTO_HASHMODE_SHA224_MODE_M) -#define SHA2_MODE_SELECT_SHA256 (CRYPTO_HASHMODE_SHA256_MODE_M) -#define SHA2_MODE_SELECT_SHA384 (CRYPTO_HASHMODE_SHA384_MODE_M) -#define SHA2_MODE_SELECT_SHA512 (CRYPTO_HASHMODE_SHA512_MODE_M) -#define SHA2_MODE_SELECT_NEW_HASH (CRYPTO_HASHMODE_NEW_HASH_M) +// Selectable SHA-2 modes. They determine the algorithm used and if initial +// values will be set to the default constants or not +#define SHA2_MODE_SELECT_SHA224 (CRYPTO_HASHMODE_SHA224_MODE_M) +#define SHA2_MODE_SELECT_SHA256 (CRYPTO_HASHMODE_SHA256_MODE_M) +#define SHA2_MODE_SELECT_SHA384 (CRYPTO_HASHMODE_SHA384_MODE_M) +#define SHA2_MODE_SELECT_SHA512 (CRYPTO_HASHMODE_SHA512_MODE_M) +#define SHA2_MODE_SELECT_NEW_HASH (CRYPTO_HASHMODE_NEW_HASH_M) // SHA-2 block lengths. When hashing block-wise, they define the size of each // block provided to the new and intermediate hash functions. -#define SHA2_SHA224_BLOCK_SIZE_BYTES (512 / 8) -#define SHA2_SHA256_BLOCK_SIZE_BYTES (512 / 8) -#define SHA2_SHA384_BLOCK_SIZE_BYTES (1024 / 8) -#define SHA2_SHA512_BLOCK_SIZE_BYTES (1024 / 8) +#define SHA2_SHA224_BLOCK_SIZE_BYTES (512 / 8) +#define SHA2_SHA256_BLOCK_SIZE_BYTES (512 / 8) +#define SHA2_SHA384_BLOCK_SIZE_BYTES (1024 / 8) +#define SHA2_SHA512_BLOCK_SIZE_BYTES (1024 / 8) // DMA status codes -#define SHA2_DMA_CHANNEL0_ACTIVE (CRYPTO_DMASTAT_CH0_ACT_M) -#define SHA2_DMA_CHANNEL1_ACTIVE (CRYPTO_DMASTAT_CH1_ACT_M) -#define SHA2_DMA_PORT_ERROR (CRYPTO_DMASTAT_PORT_ERR_M) +#define SHA2_DMA_CHANNEL0_ACTIVE (CRYPTO_DMASTAT_CH0_ACT_M) +#define SHA2_DMA_CHANNEL1_ACTIVE (CRYPTO_DMASTAT_CH1_ACT_M) +#define SHA2_DMA_PORT_ERROR (CRYPTO_DMASTAT_PORT_ERR_M) // Crypto module DMA operation types -#define SHA2_ALGSEL_SHA256 0x04 -#define SHA2_ALGSEL_SHA512 0x08 -#define SHA2_ALGSEL_TAG (CRYPTO_ALGSEL_TAG_M) - - +#define SHA2_ALGSEL_SHA256 0x04 +#define SHA2_ALGSEL_SHA512 0x08 +#define SHA2_ALGSEL_TAG (CRYPTO_ALGSEL_TAG_M) //***************************************************************************** // @@ -186,7 +182,7 @@ extern "C" //! \return None // //***************************************************************************** -extern void SHA2StartDMAOperation(uint8_t* channel0Addr, uint32_t channel0Length, uint8_t* channel1Addr, uint32_t channel1Length); +extern void SHA2StartDMAOperation(uint8_t* channel0Addr, uint32_t channel0Length, uint8_t* channel1Addr, uint32_t channel1Length); //***************************************************************************** // @@ -462,8 +458,6 @@ __STATIC_INLINE void SHA2SelectAlgorithm(uint32_t algorithm) HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = algorithm; } - - //***************************************************************************** // //! \brief Specify the total length of the message. @@ -519,7 +513,6 @@ __STATIC_INLINE void SHA2SetDigest(uint32_t* digest, uint8_t digestLength) { HWREG(CRYPTO_BASE + CRYPTO_O_HASHDIGESTA + (i * sizeof(uint32_t))) = digest[i]; } - } //***************************************************************************** @@ -764,28 +757,28 @@ __STATIC_INLINE void SHA2IntUnregister(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_SHA2StartDMAOperation -#undef SHA2StartDMAOperation -#define SHA2StartDMAOperation ROM_SHA2StartDMAOperation +#undef SHA2StartDMAOperation +#define SHA2StartDMAOperation ROM_SHA2StartDMAOperation #endif #ifdef ROM_SHA2WaitForIRQFlags -#undef SHA2WaitForIRQFlags -#define SHA2WaitForIRQFlags ROM_SHA2WaitForIRQFlags +#undef SHA2WaitForIRQFlags +#define SHA2WaitForIRQFlags ROM_SHA2WaitForIRQFlags #endif #ifdef ROM_SHA2ComputeInitialHash -#undef SHA2ComputeInitialHash -#define SHA2ComputeInitialHash ROM_SHA2ComputeInitialHash +#undef SHA2ComputeInitialHash +#define SHA2ComputeInitialHash ROM_SHA2ComputeInitialHash #endif #ifdef ROM_SHA2ComputeIntermediateHash -#undef SHA2ComputeIntermediateHash -#define SHA2ComputeIntermediateHash ROM_SHA2ComputeIntermediateHash +#undef SHA2ComputeIntermediateHash +#define SHA2ComputeIntermediateHash ROM_SHA2ComputeIntermediateHash #endif #ifdef ROM_SHA2ComputeFinalHash -#undef SHA2ComputeFinalHash -#define SHA2ComputeFinalHash ROM_SHA2ComputeFinalHash +#undef SHA2ComputeFinalHash +#define SHA2ComputeFinalHash ROM_SHA2ComputeFinalHash #endif #ifdef ROM_SHA2ComputeHash -#undef SHA2ComputeHash -#define SHA2ComputeHash ROM_SHA2ComputeHash +#undef SHA2ComputeHash +#define SHA2ComputeHash ROM_SHA2ComputeHash #endif #endif @@ -798,7 +791,7 @@ __STATIC_INLINE void SHA2IntUnregister(void) } #endif -#endif // __SHA2_H__ +#endif // __SHA2_H__ //***************************************************************************** // diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sha2_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sha2_doc.h index 4207b4b..3ea7eab 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sha2_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sha2_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: sha2_doc.h -* Revised: 2017-11-01 10:33:37 +0100 (Wed, 01 Nov 2017) -* Revision: 50125 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: sha2_doc.h + * Revised: 2017-11-01 10:33:37 +0100 (Wed, 01 Nov 2017) + * Revision: 50125 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup sha2_api //! @{ //! \section sec_sha2 Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/smph.h index e1bfc44..5e8ebb1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/smph.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/smph.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: smph.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the MCU Semaphore. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: smph.h + * Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) + * Revision: 47343 + * + * Description: Defines and prototypes for the MCU Semaphore. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,16 +55,15 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_memmap.h" +#include "../inc/hw_smph.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_smph.h" -#include "../inc/hw_memmap.h" -#include "debug.h" //***************************************************************************** // @@ -80,7 +79,7 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define SMPHAcquire NOROM_SMPHAcquire +#define SMPHAcquire NOROM_SMPHAcquire #endif //***************************************************************************** @@ -88,8 +87,8 @@ extern "C" // General constants and defines // //***************************************************************************** -#define SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed -#define SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed +#define SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed +#define SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed //***************************************************************************** // @@ -97,38 +96,38 @@ extern "C" // as the ui32Semaphore parameter. // //***************************************************************************** -#define SMPH_0 0 // MCU Semaphore 0 -#define SMPH_1 1 // MCU Semaphore 1 -#define SMPH_2 2 // MCU Semaphore 2 -#define SMPH_3 3 // MCU Semaphore 3 -#define SMPH_4 4 // MCU Semaphore 4 -#define SMPH_5 5 // MCU Semaphore 5 -#define SMPH_6 6 // MCU Semaphore 6 -#define SMPH_7 7 // MCU Semaphore 7 -#define SMPH_8 8 // MCU Semaphore 8 -#define SMPH_9 9 // MCU Semaphore 9 -#define SMPH_10 10 // MCU Semaphore 10 -#define SMPH_11 11 // MCU Semaphore 11 -#define SMPH_12 12 // MCU Semaphore 12 -#define SMPH_13 13 // MCU Semaphore 13 -#define SMPH_14 14 // MCU Semaphore 14 -#define SMPH_15 15 // MCU Semaphore 15 -#define SMPH_16 16 // MCU Semaphore 16 -#define SMPH_17 17 // MCU Semaphore 17 -#define SMPH_18 18 // MCU Semaphore 18 -#define SMPH_19 19 // MCU Semaphore 19 -#define SMPH_20 20 // MCU Semaphore 20 -#define SMPH_21 21 // MCU Semaphore 21 -#define SMPH_22 22 // MCU Semaphore 22 -#define SMPH_23 23 // MCU Semaphore 23 -#define SMPH_24 24 // MCU Semaphore 24 -#define SMPH_25 25 // MCU Semaphore 25 -#define SMPH_26 26 // MCU Semaphore 26 -#define SMPH_27 27 // MCU Semaphore 27 -#define SMPH_28 28 // MCU Semaphore 28 -#define SMPH_29 29 // MCU Semaphore 29 -#define SMPH_30 30 // MCU Semaphore 30 -#define SMPH_31 31 // MCU Semaphore 31 +#define SMPH_0 0 // MCU Semaphore 0 +#define SMPH_1 1 // MCU Semaphore 1 +#define SMPH_2 2 // MCU Semaphore 2 +#define SMPH_3 3 // MCU Semaphore 3 +#define SMPH_4 4 // MCU Semaphore 4 +#define SMPH_5 5 // MCU Semaphore 5 +#define SMPH_6 6 // MCU Semaphore 6 +#define SMPH_7 7 // MCU Semaphore 7 +#define SMPH_8 8 // MCU Semaphore 8 +#define SMPH_9 9 // MCU Semaphore 9 +#define SMPH_10 10 // MCU Semaphore 10 +#define SMPH_11 11 // MCU Semaphore 11 +#define SMPH_12 12 // MCU Semaphore 12 +#define SMPH_13 13 // MCU Semaphore 13 +#define SMPH_14 14 // MCU Semaphore 14 +#define SMPH_15 15 // MCU Semaphore 15 +#define SMPH_16 16 // MCU Semaphore 16 +#define SMPH_17 17 // MCU Semaphore 17 +#define SMPH_18 18 // MCU Semaphore 18 +#define SMPH_19 19 // MCU Semaphore 19 +#define SMPH_20 20 // MCU Semaphore 20 +#define SMPH_21 21 // MCU Semaphore 21 +#define SMPH_22 22 // MCU Semaphore 22 +#define SMPH_23 23 // MCU Semaphore 23 +#define SMPH_24 24 // MCU Semaphore 24 +#define SMPH_25 25 // MCU Semaphore 25 +#define SMPH_26 26 // MCU Semaphore 26 +#define SMPH_27 27 // MCU Semaphore 27 +#define SMPH_28 28 // MCU Semaphore 28 +#define SMPH_29 29 // MCU Semaphore 29 +#define SMPH_30 30 // MCU Semaphore 30 +#define SMPH_31 31 // MCU Semaphore 31 //***************************************************************************** // @@ -287,8 +286,8 @@ SMPHRelease(uint32_t ui32Semaphore) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_SMPHAcquire -#undef SMPHAcquire -#define SMPHAcquire ROM_SMPHAcquire +#undef SMPHAcquire +#define SMPHAcquire ROM_SMPHAcquire #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/smph_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/smph_doc.h index c66ef84..086359e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/smph_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/smph_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: smph_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: smph_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup mcusemaphore_api //! @{ //! \section sec_mcusemaphore Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.h index 74eaa08..c09fc82 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: ssi.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and macros for the SSI. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: ssi.h + * Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) + * Revision: 49048 + * + * Description: Defines and macros for the SSI. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,18 +55,17 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include #include "../inc/hw_ints.h" #include "../inc/hw_memmap.h" -#include "../inc/hw_types.h" #include "../inc/hw_ssi.h" +#include "../inc/hw_types.h" #include "debug.h" #include "interrupt.h" +#include +#include //***************************************************************************** // @@ -82,13 +81,13 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define SSIConfigSetExpClk NOROM_SSIConfigSetExpClk -#define SSIDataPut NOROM_SSIDataPut -#define SSIDataPutNonBlocking NOROM_SSIDataPutNonBlocking -#define SSIDataGet NOROM_SSIDataGet -#define SSIDataGetNonBlocking NOROM_SSIDataGetNonBlocking -#define SSIIntRegister NOROM_SSIIntRegister -#define SSIIntUnregister NOROM_SSIIntUnregister +#define SSIConfigSetExpClk NOROM_SSIConfigSetExpClk +#define SSIDataPut NOROM_SSIDataPut +#define SSIDataPutNonBlocking NOROM_SSIDataPutNonBlocking +#define SSIDataGet NOROM_SSIDataGet +#define SSIDataGetNonBlocking NOROM_SSIDataGetNonBlocking +#define SSIIntRegister NOROM_SSIIntRegister +#define SSIIntUnregister NOROM_SSIIntUnregister #endif //***************************************************************************** @@ -97,45 +96,45 @@ extern "C" // as the ui32IntFlags parameter, and returned by SSIIntStatus. // //***************************************************************************** -#define SSI_TXFF 0x00000008 // TX FIFO half full or less -#define SSI_RXFF 0x00000004 // RX FIFO half full or more -#define SSI_RXTO 0x00000002 // RX timeout -#define SSI_RXOR 0x00000001 // RX overrun +#define SSI_TXFF 0x00000008 // TX FIFO half full or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or more +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun //***************************************************************************** // // Values that are returned from SSIStatus // //***************************************************************************** -#define SSI_RX_FULL 0x00000008 // Receive FIFO full -#define SSI_RX_NOT_EMPTY 0x00000004 // Receive FIFO not empty -#define SSI_TX_NOT_FULL 0x00000002 // Transmit FIFO not full -#define SSI_TX_EMPTY 0x00000001 // Transmit FIFO empty -#define SSI_STATUS_MASK 0x0000000F +#define SSI_RX_FULL 0x00000008 // Receive FIFO full +#define SSI_RX_NOT_EMPTY 0x00000004 // Receive FIFO not empty +#define SSI_TX_NOT_FULL 0x00000002 // Transmit FIFO not full +#define SSI_TX_EMPTY 0x00000001 // Transmit FIFO empty +#define SSI_STATUS_MASK 0x0000000F //***************************************************************************** // // Values that can be passed to SSIConfigSetExpClk. // //***************************************************************************** -#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 -#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 -#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 -#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 -#define SSI_FRF_TI 0x00000010 // TI frame format -#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format -#define SSI_MODE_MASTER 0x00000000 // SSI master -#define SSI_MODE_SLAVE 0x00000001 // SSI slave -#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled //***************************************************************************** // // Values that can be passed to SSIDMAEnable() and SSIDMADisable(). // //***************************************************************************** -#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit -#define SSI_DMA_RX 0x00000001 // Enable DMA for receive +#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit +#define SSI_DMA_RX 0x00000001 // Enable DMA for receive //***************************************************************************** // @@ -651,32 +650,32 @@ SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_SSIConfigSetExpClk -#undef SSIConfigSetExpClk -#define SSIConfigSetExpClk ROM_SSIConfigSetExpClk +#undef SSIConfigSetExpClk +#define SSIConfigSetExpClk ROM_SSIConfigSetExpClk #endif #ifdef ROM_SSIDataPut -#undef SSIDataPut -#define SSIDataPut ROM_SSIDataPut +#undef SSIDataPut +#define SSIDataPut ROM_SSIDataPut #endif #ifdef ROM_SSIDataPutNonBlocking -#undef SSIDataPutNonBlocking -#define SSIDataPutNonBlocking ROM_SSIDataPutNonBlocking +#undef SSIDataPutNonBlocking +#define SSIDataPutNonBlocking ROM_SSIDataPutNonBlocking #endif #ifdef ROM_SSIDataGet -#undef SSIDataGet -#define SSIDataGet ROM_SSIDataGet +#undef SSIDataGet +#define SSIDataGet ROM_SSIDataGet #endif #ifdef ROM_SSIDataGetNonBlocking -#undef SSIDataGetNonBlocking -#define SSIDataGetNonBlocking ROM_SSIDataGetNonBlocking +#undef SSIDataGetNonBlocking +#define SSIDataGetNonBlocking ROM_SSIDataGetNonBlocking #endif #ifdef ROM_SSIIntRegister -#undef SSIIntRegister -#define SSIIntRegister ROM_SSIIntRegister +#undef SSIIntRegister +#define SSIIntRegister ROM_SSIIntRegister #endif #ifdef ROM_SSIIntUnregister -#undef SSIIntUnregister -#define SSIIntUnregister ROM_SSIIntUnregister +#undef SSIIntUnregister +#define SSIIntUnregister ROM_SSIIntUnregister #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-config.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-config.h index 2b338bd..93e071f 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-config.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-config.h @@ -1,8 +1,8 @@ /****************************************************************************** -* Filename: sw_ecrypt-config.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ + * Filename: sw_ecrypt-config.h + * Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) + * Revision: 47308 + ******************************************************************************/ /* ecrypt-config.h */ /* *** Normally, it should not be necessary to edit this file. *** */ @@ -17,46 +17,46 @@ /* * The LITTLE endian machines: */ -#if ( ! defined(ECRYPT_LITTLE_ENDIAN)) - #if defined(__ultrix) /* Older MIPS */ - #define ECRYPT_LITTLE_ENDIAN - #elif defined(__alpha) /* Alpha */ - #define ECRYPT_LITTLE_ENDIAN - #elif defined(i386) /* x86 (gcc) */ - #define ECRYPT_LITTLE_ENDIAN - #elif defined(__i386) /* x86 (gcc) */ - #define ECRYPT_LITTLE_ENDIAN - #elif defined(_M_IX86) /* x86 (MSC, Borland) */ - #define ECRYPT_LITTLE_ENDIAN - #elif defined(_MSC_VER) /* x86 (surely MSC) */ - #define ECRYPT_LITTLE_ENDIAN - #elif defined(__INTEL_COMPILER) /* x86 (surely Intel compiler icl.exe) */ - #define ECRYPT_LITTLE_ENDIAN +#if (!defined(ECRYPT_LITTLE_ENDIAN)) +#if defined(__ultrix) /* Older MIPS */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(__alpha) /* Alpha */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(i386) /* x86 (gcc) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(__i386) /* x86 (gcc) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(_M_IX86) /* x86 (MSC, Borland) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(_MSC_VER) /* x86 (surely MSC) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(__INTEL_COMPILER) /* x86 (surely Intel compiler icl.exe) */ +#define ECRYPT_LITTLE_ENDIAN - /* - * The BIG endian machines: - */ - #elif defined(sun) /* Newer Sparc's */ - #define ECRYPT_BIG_ENDIAN - #elif defined(__ppc__) /* PowerPC */ - #define ECRYPT_BIG_ENDIAN +/* + * The BIG endian machines: + */ +#elif defined(sun) /* Newer Sparc's */ +#define ECRYPT_BIG_ENDIAN +#elif defined(__ppc__) /* PowerPC */ +#define ECRYPT_BIG_ENDIAN - /* - * Finally machines with UNKNOWN endianness: - */ - #elif defined (_AIX) /* RS6000 */ - #define ECRYPT_UNKNOWN - #elif defined(__hpux) /* HP-PA */ - #define ECRYPT_UNKNOWN - #elif defined(__aux) /* 68K */ - #define ECRYPT_UNKNOWN - #elif defined(__dgux) /* 88K (but P6 in latest boxes) */ - #define ECRYPT_UNKNOWN - #elif defined(__sgi) /* Newer MIPS */ - #define ECRYPT_UNKNOWN - #else /* Any other processor */ - #define ECRYPT_UNKNOWN - #endif +/* + * Finally machines with UNKNOWN endianness: + */ +#elif defined(_AIX) /* RS6000 */ +#define ECRYPT_UNKNOWN +#elif defined(__hpux) /* HP-PA */ +#define ECRYPT_UNKNOWN +#elif defined(__aux) /* 68K */ +#define ECRYPT_UNKNOWN +#elif defined(__dgux) /* 88K (but P6 in latest boxes) */ +#define ECRYPT_UNKNOWN +#elif defined(__sgi) /* Newer MIPS */ +#define ECRYPT_UNKNOWN +#else /* Any other processor */ +#define ECRYPT_UNKNOWN +#endif #endif /* ------------------------------------------------------------------------- */ @@ -75,188 +75,188 @@ /* --- check char --- */ #if (UCHAR_MAX / 0xFU > 0xFU) - #ifndef I8T - #define I8T char - #define U8C(v) (v##U) +#ifndef I8T +#define I8T char +#define U8C(v) (v##U) - #if (UCHAR_MAX == 0xFFU) - #define ECRYPT_I8T_IS_BYTE - #endif +#if (UCHAR_MAX == 0xFFU) +#define ECRYPT_I8T_IS_BYTE +#endif - #endif +#endif - #if (UCHAR_MAX / 0xFFU > 0xFFU) - #ifndef I16T - #define I16T char - #define U16C(v) (v##U) - #endif +#if (UCHAR_MAX / 0xFFU > 0xFFU) +#ifndef I16T +#define I16T char +#define U16C(v) (v##U) +#endif - #if (UCHAR_MAX / 0xFFFFU > 0xFFFFU) - #ifndef I32T - #define I32T char - #define U32C(v) (v##U) - #endif +#if (UCHAR_MAX / 0xFFFFU > 0xFFFFU) +#ifndef I32T +#define I32T char +#define U32C(v) (v##U) +#endif - #if (UCHAR_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) - #ifndef I64T - #define I64T char - #define U64C(v) (v##U) - #define ECRYPT_NATIVE64 - #endif +#if (UCHAR_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) +#ifndef I64T +#define I64T char +#define U64C(v) (v##U) +#define ECRYPT_NATIVE64 +#endif - #endif - #endif - #endif +#endif +#endif +#endif #endif /* --- check short --- */ #if (USHRT_MAX / 0xFU > 0xFU) - #ifndef I8T - #define I8T short - #define U8C(v) (v##U) +#ifndef I8T +#define I8T short +#define U8C(v) (v##U) - #if (USHRT_MAX == 0xFFU) - #define ECRYPT_I8T_IS_BYTE - #endif +#if (USHRT_MAX == 0xFFU) +#define ECRYPT_I8T_IS_BYTE +#endif - #endif +#endif - #if (USHRT_MAX / 0xFFU > 0xFFU) - #ifndef I16T - #define I16T short - #define U16C(v) (v##U) - #endif +#if (USHRT_MAX / 0xFFU > 0xFFU) +#ifndef I16T +#define I16T short +#define U16C(v) (v##U) +#endif - #if (USHRT_MAX / 0xFFFFU > 0xFFFFU) - #ifndef I32T - #define I32T short - #define U32C(v) (v##U) - #endif +#if (USHRT_MAX / 0xFFFFU > 0xFFFFU) +#ifndef I32T +#define I32T short +#define U32C(v) (v##U) +#endif - #if (USHRT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) - #ifndef I64T - #define I64T short - #define U64C(v) (v##U) - #define ECRYPT_NATIVE64 - #endif +#if (USHRT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) +#ifndef I64T +#define I64T short +#define U64C(v) (v##U) +#define ECRYPT_NATIVE64 +#endif - #endif - #endif - #endif +#endif +#endif +#endif #endif /* --- check int --- */ #if (UINT_MAX / 0xFU > 0xFU) - #ifndef I8T - #define I8T int - #define U8C(v) (v##U) +#ifndef I8T +#define I8T int +#define U8C(v) (v##U) - #if (ULONG_MAX == 0xFFU) - #define ECRYPT_I8T_IS_BYTE - #endif +#if (ULONG_MAX == 0xFFU) +#define ECRYPT_I8T_IS_BYTE +#endif - #endif +#endif - #if (UINT_MAX / 0xFFU > 0xFFU) - #ifndef I16T - #define I16T int - #define U16C(v) (v##U) - #endif +#if (UINT_MAX / 0xFFU > 0xFFU) +#ifndef I16T +#define I16T int +#define U16C(v) (v##U) +#endif - #if (UINT_MAX / 0xFFFFU > 0xFFFFU) - #ifndef I32T - #define I32T int - #define U32C(v) (v##U) - #endif +#if (UINT_MAX / 0xFFFFU > 0xFFFFU) +#ifndef I32T +#define I32T int +#define U32C(v) (v##U) +#endif - #if (UINT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) - #ifndef I64T - #define I64T int - #define U64C(v) (v##U) - #define ECRYPT_NATIVE64 - #endif +#if (UINT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) +#ifndef I64T +#define I64T int +#define U64C(v) (v##U) +#define ECRYPT_NATIVE64 +#endif - #endif - #endif - #endif +#endif +#endif +#endif #endif /* --- check long --- */ #if (ULONG_MAX / 0xFUL > 0xFUL) - #ifndef I8T - #define I8T long - #define U8C(v) (v##UL) +#ifndef I8T +#define I8T long +#define U8C(v) (v##UL) - #if (ULONG_MAX == 0xFFUL) - #define ECRYPT_I8T_IS_BYTE - #endif +#if (ULONG_MAX == 0xFFUL) +#define ECRYPT_I8T_IS_BYTE +#endif - #endif +#endif - #if (ULONG_MAX / 0xFFUL > 0xFFUL) - #ifndef I16T - #define I16T long - #define U16C(v) (v##UL) - #endif +#if (ULONG_MAX / 0xFFUL > 0xFFUL) +#ifndef I16T +#define I16T long +#define U16C(v) (v##UL) +#endif - #if (ULONG_MAX / 0xFFFFUL > 0xFFFFUL) - #ifndef I32T - #define I32T long - #define U32C(v) (v##UL) - #endif +#if (ULONG_MAX / 0xFFFFUL > 0xFFFFUL) +#ifndef I32T +#define I32T long +#define U32C(v) (v##UL) +#endif - #if (ULONG_MAX / 0xFFFFFFFFUL > 0xFFFFFFFFUL) - #ifndef I64T - #define I64T long - #define U64C(v) (v##UL) - #define ECRYPT_NATIVE64 - #endif +#if (ULONG_MAX / 0xFFFFFFFFUL > 0xFFFFFFFFUL) +#ifndef I64T +#define I64T long +#define U64C(v) (v##UL) +#define ECRYPT_NATIVE64 +#endif - #endif - #endif - #endif +#endif +#endif +#endif #endif /* --- check long long --- */ #ifdef ULLONG_MAX - #if (ULLONG_MAX / 0xFULL > 0xFULL) - #ifndef I8T - #define I8T long long - #define U8C(v) (v##ULL) +#if (ULLONG_MAX / 0xFULL > 0xFULL) +#ifndef I8T +#define I8T long long +#define U8C(v) (v##ULL) - #if (ULLONG_MAX == 0xFFULL) - #define ECRYPT_I8T_IS_BYTE - #endif +#if (ULLONG_MAX == 0xFFULL) +#define ECRYPT_I8T_IS_BYTE +#endif - #endif +#endif - #if (ULLONG_MAX / 0xFFULL > 0xFFULL) - #ifndef I16T - #define I16T long long - #define U16C(v) (v##ULL) - #endif +#if (ULLONG_MAX / 0xFFULL > 0xFFULL) +#ifndef I16T +#define I16T long long +#define U16C(v) (v##ULL) +#endif - #if (ULLONG_MAX / 0xFFFFULL > 0xFFFFULL) - #ifndef I32T - #define I32T long long - #define U32C(v) (v##ULL) - #endif +#if (ULLONG_MAX / 0xFFFFULL > 0xFFFFULL) +#ifndef I32T +#define I32T long long +#define U32C(v) (v##ULL) +#endif - #if (ULLONG_MAX / 0xFFFFFFFFULL > 0xFFFFFFFFULL) - #ifndef I64T - #define I64T long long - #define U64C(v) (v##ULL) - #endif +#if (ULLONG_MAX / 0xFFFFFFFFULL > 0xFFFFFFFFULL) +#ifndef I64T +#define I64T long long +#define U64C(v) (v##ULL) +#endif - #endif - #endif - #endif - #endif +#endif +#endif +#endif +#endif #endif @@ -264,13 +264,13 @@ #ifdef _UI64_MAX - #if (_UI64_MAX / 0xFFFFFFFFui64 > 0xFFFFFFFFui64) - #ifndef I64T - #define I64T __int64 - #define U64C(v) (v##ui64) - #endif +#if (_UI64_MAX / 0xFFFFFFFFui64 > 0xFFFFFFFFui64) +#ifndef I64T +#define I64T __int64 +#define U64C(v) (v##ui64) +#endif - #endif +#endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-machine.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-machine.h index a3eba88..48788a8 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-machine.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-machine.h @@ -1,8 +1,8 @@ /****************************************************************************** -* Filename: sw_ecrypt-machine.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ + * Filename: sw_ecrypt-machine.h + * Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) + * Revision: 47308 + ******************************************************************************/ /* ecrypt-machine.h */ /* @@ -16,23 +16,23 @@ #if (defined(ECRYPT_DEFAULT_ROT) && !defined(ECRYPT_MACHINE_ROT)) - #define ECRYPT_MACHINE_ROT +#define ECRYPT_MACHINE_ROT - #if (defined(WIN32) && defined(_MSC_VER)) +#if (defined(WIN32) && defined(_MSC_VER)) - #undef ROTL32 - #undef ROTR32 - #undef ROTL64 - #undef ROTR64 +#undef ROTL32 +#undef ROTR32 +#undef ROTL64 +#undef ROTR64 - #include +#include - #define ROTL32(v, n) _lrotl(v, n) - #define ROTR32(v, n) _lrotr(v, n) - #define ROTL64(v, n) _rotl64(v, n) - #define ROTR64(v, n) _rotr64(v, n) +#define ROTL32(v, n) _lrotl(v, n) +#define ROTR32(v, n) _lrotr(v, n) +#define ROTL64(v, n) _rotl64(v, n) +#define ROTR64(v, n) _rotr64(v, n) - #endif +#endif #endif @@ -40,11 +40,11 @@ #if (defined(ECRYPT_DEFAULT_SWAP) && !defined(ECRYPT_MACHINE_SWAP)) - #define ECRYPT_MACHINE_SWAP +#define ECRYPT_MACHINE_SWAP - /* - * If you want to overwrite the default swap macros, put it here. And so on. - */ +/* + * If you want to overwrite the default swap macros, put it here. And so on. + */ #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-portable.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-portable.h index 600c718..067451a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-portable.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-portable.h @@ -1,8 +1,8 @@ /****************************************************************************** -* Filename: sw_ecrypt-portable.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ + * Filename: sw_ecrypt-portable.h + * Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) + * Revision: 47308 + ******************************************************************************/ /* ecrypt-portable.h */ /* @@ -46,23 +46,23 @@ */ #ifdef I8T - typedef signed I8T s8; - typedef unsigned I8T u8; +typedef signed I8T s8; +typedef unsigned I8T u8; #endif #ifdef I16T - typedef signed I16T s16; - typedef unsigned I16T u16; +typedef signed I16T s16; +typedef unsigned I16T u16; #endif #ifdef I32T - typedef signed I32T s32; - typedef unsigned I32T u32; +typedef signed I32T s32; +typedef unsigned I32T u32; #endif #ifdef I64T - typedef signed I64T s64; - typedef unsigned I64T u64; +typedef signed I64T s64; +typedef unsigned I64T u64; #endif /* @@ -113,13 +113,13 @@ #define SWAP16(v) \ ROTL16(v, 8) -#define SWAP32(v) \ - ((ROTL32(v, 8) & U32C(0x00FF00FF)) | \ +#define SWAP32(v) \ + ((ROTL32(v, 8) & U32C(0x00FF00FF)) | \ (ROTL32(v, 24) & U32C(0xFF00FF00))) #ifdef ECRYPT_NATIVE64 -#define SWAP64(v) \ - ((ROTL64(v, 8) & U64C(0x000000FF000000FF)) | \ +#define SWAP64(v) \ + ((ROTL64(v, 8) & U64C(0x000000FF000000FF)) | \ (ROTL64(v, 24) & U64C(0x0000FF000000FF00)) | \ (ROTL64(v, 40) & U64C(0x00FF000000FF0000)) | \ (ROTL64(v, 56) & U64C(0xFF000000FF000000))) @@ -133,23 +133,23 @@ #define ECRYPT_DEFAULT_WTOW #ifdef ECRYPT_LITTLE_ENDIAN - #define U16TO16_LITTLE(v) (v) - #define U32TO32_LITTLE(v) (v) - #define U64TO64_LITTLE(v) (v) +#define U16TO16_LITTLE(v) (v) +#define U32TO32_LITTLE(v) (v) +#define U64TO64_LITTLE(v) (v) - #define U16TO16_BIG(v) SWAP16(v) - #define U32TO32_BIG(v) SWAP32(v) - #define U64TO64_BIG(v) SWAP64(v) +#define U16TO16_BIG(v) SWAP16(v) +#define U32TO32_BIG(v) SWAP32(v) +#define U64TO64_BIG(v) SWAP64(v) #endif #ifdef ECRYPT_BIG_ENDIAN - #define U16TO16_LITTLE(v) SWAP16(v) - #define U32TO32_LITTLE(v) SWAP32(v) - #define U64TO64_LITTLE(v) SWAP64(v) +#define U16TO16_LITTLE(v) SWAP16(v) +#define U32TO32_LITTLE(v) SWAP32(v) +#define U64TO64_LITTLE(v) SWAP64(v) - #define U16TO16_BIG(v) (v) - #define U32TO32_BIG(v) (v) - #define U64TO64_BIG(v) (v) +#define U16TO16_BIG(v) (v) +#define U32TO32_BIG(v) (v) +#define U64TO64_BIG(v) (v) #endif #include "sw_ecrypt-machine.h" @@ -163,38 +163,38 @@ #if (!defined(ECRYPT_UNKNOWN) && defined(ECRYPT_I8T_IS_BYTE)) -#define U8TO16_LITTLE(p) U16TO16_LITTLE(((u16*)(p))[0]) -#define U8TO32_LITTLE(p) U32TO32_LITTLE(((u32*)(p))[0]) -#define U8TO64_LITTLE(p) U64TO64_LITTLE(((u64*)(p))[0]) +#define U8TO16_LITTLE(p) U16TO16_LITTLE(((u16 *)(p))[0]) +#define U8TO32_LITTLE(p) U32TO32_LITTLE(((u32 *)(p))[0]) +#define U8TO64_LITTLE(p) U64TO64_LITTLE(((u64 *)(p))[0]) -#define U8TO16_BIG(p) U16TO16_BIG(((u16*)(p))[0]) -#define U8TO32_BIG(p) U32TO32_BIG(((u32*)(p))[0]) -#define U8TO64_BIG(p) U64TO64_BIG(((u64*)(p))[0]) +#define U8TO16_BIG(p) U16TO16_BIG(((u16 *)(p))[0]) +#define U8TO32_BIG(p) U32TO32_BIG(((u32 *)(p))[0]) +#define U8TO64_BIG(p) U64TO64_BIG(((u64 *)(p))[0]) -#define U16TO8_LITTLE(p, v) (((u16*)(p))[0] = U16TO16_LITTLE(v)) -#define U32TO8_LITTLE(p, v) (((u32*)(p))[0] = U32TO32_LITTLE(v)) -#define U64TO8_LITTLE(p, v) (((u64*)(p))[0] = U64TO64_LITTLE(v)) +#define U16TO8_LITTLE(p, v) (((u16 *)(p))[0] = U16TO16_LITTLE(v)) +#define U32TO8_LITTLE(p, v) (((u32 *)(p))[0] = U32TO32_LITTLE(v)) +#define U64TO8_LITTLE(p, v) (((u64 *)(p))[0] = U64TO64_LITTLE(v)) -#define U16TO8_BIG(p, v) (((u16*)(p))[0] = U16TO16_BIG(v)) -#define U32TO8_BIG(p, v) (((u32*)(p))[0] = U32TO32_BIG(v)) -#define U64TO8_BIG(p, v) (((u64*)(p))[0] = U64TO64_BIG(v)) +#define U16TO8_BIG(p, v) (((u16 *)(p))[0] = U16TO16_BIG(v)) +#define U32TO8_BIG(p, v) (((u32 *)(p))[0] = U32TO32_BIG(v)) +#define U64TO8_BIG(p, v) (((u64 *)(p))[0] = U64TO64_BIG(v)) #else #define U8TO16_LITTLE(p) \ - (((u16)((p)[0]) ) | \ - ((u16)((p)[1]) << 8)) + (((u16)((p)[0])) | \ + ((u16)((p)[1]) << 8)) -#define U8TO32_LITTLE(p) \ - (((u32)((p)[0]) ) | \ - ((u32)((p)[1]) << 8) | \ +#define U8TO32_LITTLE(p) \ + (((u32)((p)[0])) | \ + ((u32)((p)[1]) << 8) | \ ((u32)((p)[2]) << 16) | \ ((u32)((p)[3]) << 24)) #ifdef ECRYPT_NATIVE64 -#define U8TO64_LITTLE(p) \ - (((u64)((p)[0]) ) | \ - ((u64)((p)[1]) << 8) | \ +#define U8TO64_LITTLE(p) \ + (((u64)((p)[0])) | \ + ((u64)((p)[1]) << 8) | \ ((u64)((p)[2]) << 16) | \ ((u64)((p)[3]) << 24) | \ ((u64)((p)[4]) << 32) | \ @@ -206,50 +206,53 @@ ((u64)U8TO32_LITTLE(p) | ((u64)U8TO32_LITTLE((p) + 4) << 32)) #endif -#define U8TO16_BIG(p) \ - (((u16)((p)[0]) << 8) | \ - ((u16)((p)[1]) )) +#define U8TO16_BIG(p) \ + (((u16)((p)[0]) << 8) | \ + ((u16)((p)[1]))) -#define U8TO32_BIG(p) \ +#define U8TO32_BIG(p) \ (((u32)((p)[0]) << 24) | \ ((u32)((p)[1]) << 16) | \ - ((u32)((p)[2]) << 8) | \ - ((u32)((p)[3]) )) + ((u32)((p)[2]) << 8) | \ + ((u32)((p)[3]))) #ifdef ECRYPT_NATIVE64 -#define U8TO64_BIG(p) \ +#define U8TO64_BIG(p) \ (((u64)((p)[0]) << 56) | \ ((u64)((p)[1]) << 48) | \ ((u64)((p)[2]) << 40) | \ ((u64)((p)[3]) << 32) | \ ((u64)((p)[4]) << 24) | \ ((u64)((p)[5]) << 16) | \ - ((u64)((p)[6]) << 8) | \ - ((u64)((p)[7]) )) + ((u64)((p)[6]) << 8) | \ + ((u64)((p)[7]))) #else #define U8TO64_BIG(p) \ (((u64)U8TO32_BIG(p) << 32) | (u64)U8TO32_BIG((p) + 4)) #endif -#define U16TO8_LITTLE(p, v) \ - do { \ - (p)[0] = U8V((v) ); \ - (p)[1] = U8V((v) >> 8); \ +#define U16TO8_LITTLE(p, v) \ + do \ + { \ + (p)[0] = U8V((v)); \ + (p)[1] = U8V((v) >> 8); \ } while (0) -#define U32TO8_LITTLE(p, v) \ - do { \ - (p)[0] = U8V((v) ); \ - (p)[1] = U8V((v) >> 8); \ +#define U32TO8_LITTLE(p, v) \ + do \ + { \ + (p)[0] = U8V((v)); \ + (p)[1] = U8V((v) >> 8); \ (p)[2] = U8V((v) >> 16); \ (p)[3] = U8V((v) >> 24); \ } while (0) #ifdef ECRYPT_NATIVE64 -#define U64TO8_LITTLE(p, v) \ - do { \ - (p)[0] = U8V((v) ); \ - (p)[1] = U8V((v) >> 8); \ +#define U64TO8_LITTLE(p, v) \ + do \ + { \ + (p)[0] = U8V((v)); \ + (p)[1] = U8V((v) >> 8); \ (p)[2] = U8V((v) >> 16); \ (p)[3] = U8V((v) >> 24); \ (p)[4] = U8V((v) >> 32); \ @@ -258,44 +261,49 @@ (p)[7] = U8V((v) >> 56); \ } while (0) #else -#define U64TO8_LITTLE(p, v) \ - do { \ - U32TO8_LITTLE((p), U32V((v) )); \ +#define U64TO8_LITTLE(p, v) \ + do \ + { \ + U32TO8_LITTLE((p), U32V((v))); \ U32TO8_LITTLE((p) + 4, U32V((v) >> 32)); \ } while (0) #endif -#define U16TO8_BIG(p, v) \ - do { \ - (p)[0] = U8V((v) ); \ - (p)[1] = U8V((v) >> 8); \ +#define U16TO8_BIG(p, v) \ + do \ + { \ + (p)[0] = U8V((v)); \ + (p)[1] = U8V((v) >> 8); \ } while (0) -#define U32TO8_BIG(p, v) \ - do { \ +#define U32TO8_BIG(p, v) \ + do \ + { \ (p)[0] = U8V((v) >> 24); \ (p)[1] = U8V((v) >> 16); \ - (p)[2] = U8V((v) >> 8); \ - (p)[3] = U8V((v) ); \ + (p)[2] = U8V((v) >> 8); \ + (p)[3] = U8V((v)); \ } while (0) #ifdef ECRYPT_NATIVE64 -#define U64TO8_BIG(p, v) \ - do { \ +#define U64TO8_BIG(p, v) \ + do \ + { \ (p)[0] = U8V((v) >> 56); \ (p)[1] = U8V((v) >> 48); \ (p)[2] = U8V((v) >> 40); \ (p)[3] = U8V((v) >> 32); \ (p)[4] = U8V((v) >> 24); \ (p)[5] = U8V((v) >> 16); \ - (p)[6] = U8V((v) >> 8); \ - (p)[7] = U8V((v) ); \ + (p)[6] = U8V((v) >> 8); \ + (p)[7] = U8V((v)); \ } while (0) #else -#define U64TO8_BIG(p, v) \ - do { \ - U32TO8_BIG((p), U32V((v) >> 32)); \ - U32TO8_BIG((p) + 4, U32V((v) )); \ +#define U64TO8_BIG(p, v) \ + do \ + { \ + U32TO8_BIG((p), U32V((v) >> 32)); \ + U32TO8_BIG((p) + 4, U32V((v))); \ } while (0) #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-sync.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-sync.h index 7d9a344..e3ac4d2 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-sync.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-sync.h @@ -1,8 +1,8 @@ /****************************************************************************** -* Filename: sw_ecrypt-sync.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ + * Filename: sw_ecrypt-sync.h + * Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) + * Revision: 47308 + ******************************************************************************/ /* ecrypt-sync.h */ /* @@ -42,11 +42,11 @@ * All sizes are in bits. */ -#define ECRYPT_MAXKEYSIZE 256 /* [edit] */ -#define ECRYPT_KEYSIZE(i) (128 + (i)*128) /* [edit] */ +#define ECRYPT_MAXKEYSIZE 256 /* [edit] */ +#define ECRYPT_KEYSIZE(i) (128 + (i) * 128) /* [edit] */ -#define ECRYPT_MAXIVSIZE 64 /* [edit] */ -#define ECRYPT_IVSIZE(i) (64 + (i)*64) /* [edit] */ +#define ECRYPT_MAXIVSIZE 64 /* [edit] */ +#define ECRYPT_IVSIZE(i) (64 + (i) * 64) /* [edit] */ /* ------------------------------------------------------------------------- */ @@ -59,12 +59,12 @@ typedef struct { - u32 input[16]; /* could be compressed */ - /* - * [edit] - * - * Put here all state variable needed during the encryption process. - */ + u32 input[16]; /* could be compressed */ + /* + * [edit] + * + * Put here all state variable needed during the encryption process. + */ } ECRYPT_ctx; /* ------------------------------------------------------------------------- */ @@ -86,8 +86,8 @@ void ECRYPT_init(void); void ECRYPT_keysetup( ECRYPT_ctx* ctx, const u8* key, - u32 keysize, /* Key size in bits. */ - u32 ivsize); /* IV size in bits. */ + u32 keysize, /* Key size in bits. */ + u32 ivsize); /* IV size in bits. */ /* * IV setup. After having called ECRYPT_keysetup(), the user is @@ -141,13 +141,13 @@ void ECRYPT_encrypt_bytes( ECRYPT_ctx* ctx, const u8* plaintext, u8* ciphertext, - u32 msglen); /* Message length in bytes. */ + u32 msglen); /* Message length in bytes. */ void ECRYPT_decrypt_bytes( ECRYPT_ctx* ctx, const u8* ciphertext, u8* plaintext, - u32 msglen); /* Message length in bytes. */ + u32 msglen); /* Message length in bytes. */ /* ------------------------------------------------------------------------- */ @@ -167,7 +167,7 @@ void ECRYPT_decrypt_bytes( void ECRYPT_keystream_bytes( ECRYPT_ctx* ctx, u8* keystream, - u32 length); /* Length of keystream in bytes. */ + u32 length); /* Length of keystream in bytes. */ #endif @@ -188,7 +188,7 @@ void ECRYPT_keystream_bytes( * "ecrypt-sync.c". If you want to implement them differently, please * undef the ECRYPT_USES_DEFAULT_ALL_IN_ONE flag. */ -#define ECRYPT_USES_DEFAULT_ALL_IN_ONE /* [edit] */ +#define ECRYPT_USES_DEFAULT_ALL_IN_ONE /* [edit] */ void ECRYPT_encrypt_packet( ECRYPT_ctx* ctx, @@ -213,23 +213,23 @@ void ECRYPT_decrypt_packet( * declared below. */ -#define ECRYPT_BLOCKLENGTH 64 /* [edit] */ +#define ECRYPT_BLOCKLENGTH 64 /* [edit] */ -#define ECRYPT_USES_DEFAULT_BLOCK_MACROS /* [edit] */ +#define ECRYPT_USES_DEFAULT_BLOCK_MACROS /* [edit] */ #ifdef ECRYPT_USES_DEFAULT_BLOCK_MACROS -#define ECRYPT_encrypt_blocks(ctx, plaintext, ciphertext, blocks) \ - ECRYPT_encrypt_bytes(ctx, plaintext, ciphertext, \ +#define ECRYPT_encrypt_blocks(ctx, plaintext, ciphertext, blocks) \ + ECRYPT_encrypt_bytes(ctx, plaintext, ciphertext, \ (blocks) * ECRYPT_BLOCKLENGTH) -#define ECRYPT_decrypt_blocks(ctx, ciphertext, plaintext, blocks) \ - ECRYPT_decrypt_bytes(ctx, ciphertext, plaintext, \ +#define ECRYPT_decrypt_blocks(ctx, ciphertext, plaintext, blocks) \ + ECRYPT_decrypt_bytes(ctx, ciphertext, plaintext, \ (blocks) * ECRYPT_BLOCKLENGTH) #ifdef ECRYPT_GENERATES_KEYSTREAM -#define ECRYPT_keystream_blocks(ctx, keystream, blocks) \ - ECRYPT_keystream_bytes(ctx, keystream, \ +#define ECRYPT_keystream_blocks(ctx, keystream, blocks) \ + ECRYPT_keystream_bytes(ctx, keystream, \ (blocks) * ECRYPT_BLOCKLENGTH) #endif @@ -240,20 +240,20 @@ void ECRYPT_encrypt_blocks( ECRYPT_ctx* ctx, const u8* plaintext, u8* ciphertext, - u32 blocks); /* Message length in blocks. */ + u32 blocks); /* Message length in blocks. */ void ECRYPT_decrypt_blocks( ECRYPT_ctx* ctx, const u8* ciphertext, u8* plaintext, - u32 blocks); /* Message length in blocks. */ + u32 blocks); /* Message length in blocks. */ #ifdef ECRYPT_GENERATES_KEYSTREAM void ECRYPT_keystream_blocks( ECRYPT_ctx* ctx, const u8* keystream, - u32 blocks); /* Keystream length in blocks. */ + u32 blocks); /* Keystream length in blocks. */ #endif @@ -269,14 +269,14 @@ void ECRYPT_keystream_blocks( * 10). Note also that all variants should have exactly the same * external interface (i.e., the same ECRYPT_BLOCKLENGTH, etc.). */ -#define ECRYPT_MAXVARIANT 1 /* [edit] */ +#define ECRYPT_MAXVARIANT 1 /* [edit] */ #ifndef ECRYPT_VARIANT - #define ECRYPT_VARIANT 1 +#define ECRYPT_VARIANT 1 #endif #if (ECRYPT_VARIANT > ECRYPT_MAXVARIANT) - #error this variant does not exist +#error this variant does not exist #endif /* ------------------------------------------------------------------------- */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna-32.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna-32.h index 3e4eb10..73b809a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna-32.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna-32.h @@ -1,18 +1,18 @@ /****************************************************************************** -* Filename: sw_poly1305-donna-32.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ + * Filename: sw_poly1305-donna-32.h + * Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) + * Revision: 47308 + ******************************************************************************/ /* poly1305 implementation using 32 bit * 32 bit = 64 bit multiplication and 64 bit addition */ #if defined(_MSC_VER) - #define POLY1305_NOINLINE __declspec(noinline) +#define POLY1305_NOINLINE __declspec(noinline) #elif defined(__GNUC__) - #define POLY1305_NOINLINE __attribute__((noinline)) +#define POLY1305_NOINLINE __attribute__((noinline)) #else - #define POLY1305_NOINLINE +#define POLY1305_NOINLINE #endif #define poly1305_block_size 16 @@ -20,29 +20,28 @@ /* 17 + sizeof(size_t) + 14*sizeof(unsigned long) */ typedef struct { - unsigned long r[5]; - unsigned long h[5]; - unsigned long pad[4]; - size_t leftover; - unsigned char buffer[poly1305_block_size]; - unsigned char final; + unsigned long r[5]; + unsigned long h[5]; + unsigned long pad[4]; + size_t leftover; + unsigned char buffer[poly1305_block_size]; + unsigned char final; } poly1305_state_internal_t; /* interpret four 8 bit unsigned integers as a 32 bit unsigned integer in little endian */ static unsigned long U8TO32(const unsigned char* p) { - return - (((unsigned long)(p[0] & 0xff) ) | - ((unsigned long)(p[1] & 0xff) << 8) | - ((unsigned long)(p[2] & 0xff) << 16) | - ((unsigned long)(p[3] & 0xff) << 24)); + return (((unsigned long)(p[0] & 0xff)) | + ((unsigned long)(p[1] & 0xff) << 8) | + ((unsigned long)(p[2] & 0xff) << 16) | + ((unsigned long)(p[3] & 0xff) << 24)); } /* store a 32 bit unsigned integer as four 8 bit unsigned integers in little endian */ static void U32TO8(unsigned char* p, unsigned long v) { - p[0] = (v ) & 0xff; - p[1] = (v >> 8) & 0xff; + p[0] = (v) & 0xff; + p[1] = (v >> 8) & 0xff; p[2] = (v >> 16) & 0xff; p[3] = (v >> 24) & 0xff; } @@ -52,10 +51,10 @@ void poly1305_init(poly1305_context* ctx, const unsigned char key[32]) poly1305_state_internal_t* st = (poly1305_state_internal_t*)ctx; /* r &= 0xffffffc0ffffffc0ffffffc0fffffff */ - st->r[0] = (U8TO32(&key[ 0]) ) & 0x3ffffff; - st->r[1] = (U8TO32(&key[ 3]) >> 2) & 0x3ffff03; - st->r[2] = (U8TO32(&key[ 6]) >> 4) & 0x3ffc0ff; - st->r[3] = (U8TO32(&key[ 9]) >> 6) & 0x3f03fff; + st->r[0] = (U8TO32(&key[0])) & 0x3ffffff; + st->r[1] = (U8TO32(&key[3]) >> 2) & 0x3ffff03; + st->r[2] = (U8TO32(&key[6]) >> 4) & 0x3ffc0ff; + st->r[3] = (U8TO32(&key[9]) >> 6) & 0x3f03fff; st->r[4] = (U8TO32(&key[12]) >> 8) & 0x00fffff; /* h = 0 */ @@ -104,7 +103,7 @@ static void poly1305_blocks(poly1305_state_internal_t* st, const unsigned char* while (bytes >= poly1305_block_size) { /* h += m[i] */ - h0 += (U8TO32(m + 0) ) & 0x3ffffff; + h0 += (U8TO32(m + 0)) & 0x3ffffff; h1 += (U8TO32(m + 3) >> 2) & 0x3ffffff; h2 += (U8TO32(m + 6) >> 4) & 0x3ffffff; h3 += (U8TO32(m + 9) >> 6) & 0x3ffffff; @@ -133,8 +132,8 @@ static void poly1305_blocks(poly1305_state_internal_t* st, const unsigned char* c = (unsigned long)(d4 >> 26); h4 = (unsigned long)d4 & 0x3ffffff; h0 += c * 5; - c = (h0 >> 26); - h0 = h0 & 0x3ffffff; + c = (h0 >> 26); + h0 = h0 & 0x3ffffff; h1 += c; m += poly1305_block_size; @@ -178,19 +177,19 @@ POLY1305_NOINLINE void poly1305_finish(poly1305_context* ctx, unsigned char mac[ c = h1 >> 26; h1 = h1 & 0x3ffffff; - h2 += c; + h2 += c; c = h2 >> 26; h2 = h2 & 0x3ffffff; - h3 += c; + h3 += c; c = h3 >> 26; h3 = h3 & 0x3ffffff; - h4 += c; + h4 += c; c = h4 >> 26; h4 = h4 & 0x3ffffff; h0 += c * 5; c = h0 >> 26; h0 = h0 & 0x3ffffff; - h1 += c; + h1 += c; /* compute h + -p */ g0 = h0 + 5; @@ -222,13 +221,13 @@ POLY1305_NOINLINE void poly1305_finish(poly1305_context* ctx, unsigned char mac[ h4 = (h4 & mask) | g4; /* h = h % (2^128) */ - h0 = ((h0 ) | (h1 << 26)) & 0xffffffff; - h1 = ((h1 >> 6) | (h2 << 20)) & 0xffffffff; + h0 = ((h0) | (h1 << 26)) & 0xffffffff; + h1 = ((h1 >> 6) | (h2 << 20)) & 0xffffffff; h2 = ((h2 >> 12) | (h3 << 14)) & 0xffffffff; - h3 = ((h3 >> 18) | (h4 << 8)) & 0xffffffff; + h3 = ((h3 >> 18) | (h4 << 8)) & 0xffffffff; /* mac = (h + pad) % (2^128) */ - f = (unsigned long long)h0 + st->pad[0] ; + f = (unsigned long long)h0 + st->pad[0]; h0 = (unsigned long)f; f = (unsigned long long)h1 + st->pad[1] + (f >> 32); h1 = (unsigned long)f; @@ -237,9 +236,9 @@ POLY1305_NOINLINE void poly1305_finish(poly1305_context* ctx, unsigned char mac[ f = (unsigned long long)h3 + st->pad[3] + (f >> 32); h3 = (unsigned long)f; - U32TO8(mac + 0, h0); - U32TO8(mac + 4, h1); - U32TO8(mac + 8, h2); + U32TO8(mac + 0, h0); + U32TO8(mac + 4, h1); + U32TO8(mac + 8, h2); U32TO8(mac + 12, h3); /* zero out the state */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.h index a544927..3230064 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.h @@ -1,8 +1,8 @@ /****************************************************************************** -* Filename: sw_poly1305-donna.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ + * Filename: sw_poly1305-donna.h + * Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) + * Revision: 47308 + ******************************************************************************/ #ifndef POLY1305_DONNA_H #define POLY1305_DONNA_H @@ -11,8 +11,8 @@ typedef struct { - size_t aligner; - unsigned char opaque[136]; + size_t aligner; + unsigned char opaque[136]; } poly1305_context; void poly1305_init(poly1305_context* ctx, const unsigned char key[32]); diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.h index c3082e8..3dd34db 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: sys_ctrl.h -* Revised: 2018-09-17 14:58:51 +0200 (Mon, 17 Sep 2018) -* Revision: 52634 -* -* Description: Defines and prototypes for the System Controller. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: sys_ctrl.h + * Revised: 2018-09-17 14:58:51 +0200 (Mon, 17 Sep 2018) + * Revision: 52634 + * + * Description: Defines and prototypes for the System Controller. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,35 +55,33 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_sysctl.h" -#include "../inc/hw_prcm.h" -#include "../inc/hw_nvic.h" -#include "../inc/hw_aon_ioc.h" -#include "../inc/hw_ddi_0_osc.h" -#include "../inc/hw_rfc_pwr.h" -#include "../inc/hw_prcm.h" #include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_aon_ioc.h" #include "../inc/hw_aon_pmctl.h" #include "../inc/hw_aon_rtc.h" +#include "../inc/hw_ddi_0_osc.h" #include "../inc/hw_fcfg1.h" -#include "interrupt.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_nvic.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_rfc_pwr.h" +#include "../inc/hw_sysctl.h" +#include "../inc/hw_types.h" +#include "adi.h" +#include "cpu.h" +#include "ddi.h" #include "debug.h" -#include "pwr_ctrl.h" +#include "interrupt.h" #include "osc.h" #include "prcm.h" -#include "adi.h" -#include "ddi.h" -#include "cpu.h" +#include "pwr_ctrl.h" #include "vims.h" +#include +#include //***************************************************************************** // @@ -99,14 +97,14 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define SysCtrlIdle NOROM_SysCtrlIdle -#define SysCtrlShutdownWithAbort NOROM_SysCtrlShutdownWithAbort -#define SysCtrlShutdown NOROM_SysCtrlShutdown -#define SysCtrlStandby NOROM_SysCtrlStandby +#define SysCtrlIdle NOROM_SysCtrlIdle +#define SysCtrlShutdownWithAbort NOROM_SysCtrlShutdownWithAbort +#define SysCtrlShutdown NOROM_SysCtrlShutdown +#define SysCtrlStandby NOROM_SysCtrlStandby #define SysCtrlSetRechargeBeforePowerDown NOROM_SysCtrlSetRechargeBeforePowerDown #define SysCtrlAdjustRechargeAfterPowerDown NOROM_SysCtrlAdjustRechargeAfterPowerDown #define SysCtrl_DCDC_VoltageConditionalControl NOROM_SysCtrl_DCDC_VoltageConditionalControl -#define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet +#define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet #endif //***************************************************************************** @@ -114,17 +112,17 @@ extern "C" // Defines for the settings of the main XOSC // //***************************************************************************** -#define SYSCTRL_SYSBUS_ON 0x00000001 -#define SYSCTRL_SYSBUS_OFF 0x00000000 +#define SYSCTRL_SYSBUS_ON 0x00000001 +#define SYSCTRL_SYSBUS_OFF 0x00000000 //***************************************************************************** // // Defines for the different power modes of the System CPU // //***************************************************************************** -#define CPU_RUN 0x00000000 -#define CPU_SLEEP 0x00000001 -#define CPU_DEEP_SLEEP 0x00000002 +#define CPU_RUN 0x00000000 +#define CPU_SLEEP 0x00000001 +#define CPU_DEEP_SLEEP 0x00000002 //***************************************************************************** // @@ -132,23 +130,23 @@ extern "C" // //***************************************************************************** #define XOSC_IN_HIGH_POWER_MODE 0 // When xosc_hf is in HIGH_POWER_XOSC -#define XOSC_IN_LOW_POWER_MODE 1 // When xosc_hf is in LOW_POWER_XOSC +#define XOSC_IN_LOW_POWER_MODE 1 // When xosc_hf is in LOW_POWER_XOSC //***************************************************************************** // // Defines for the vimsPdMode parameter of SysCtrlIdle and SysCtrlStandby // //***************************************************************************** -#define VIMS_ON_CPU_ON_MODE 0 // VIMS power domain is only powered when CPU power domain is powered -#define VIMS_ON_BUS_ON_MODE 1 // VIMS power domain is powered whenever the BUS power domain is powered -#define VIMS_NO_PWR_UP_MODE 2 // VIMS power domain is not powered up at next wakeup. +#define VIMS_ON_CPU_ON_MODE 0 // VIMS power domain is only powered when CPU power domain is powered +#define VIMS_ON_BUS_ON_MODE 1 // VIMS power domain is powered whenever the BUS power domain is powered +#define VIMS_NO_PWR_UP_MODE 2 // VIMS power domain is not powered up at next wakeup. //***************************************************************************** // // Defines for the rechargeMode parameter of SysCtrlStandby // //***************************************************************************** -#define SYSCTRL_PREFERRED_RECHARGE_MODE \ +#define SYSCTRL_PREFERRED_RECHARGE_MODE \ 0xFFFFFFFF // Preferred recharge mode //***************************************************************************** @@ -313,10 +311,10 @@ extern void SysCtrlStandby(bool retainCache, uint32_t vimsPdMode, uint32_t recha // //***************************************************************************** __STATIC_INLINE uint32_t -SysCtrlClockGet( void ) +SysCtrlClockGet(void) { // Return fixed clock speed - return ( GET_MCU_CLOCK ); + return (GET_MCU_CLOCK); } //***************************************************************************** @@ -384,7 +382,7 @@ SysCtrlAonUpdate(void) //! \return None // //***************************************************************************** -extern void SysCtrlSetRechargeBeforePowerDown( uint32_t xoscPowerMode ); +extern void SysCtrlSetRechargeBeforePowerDown(uint32_t xoscPowerMode); //***************************************************************************** // @@ -395,7 +393,7 @@ extern void SysCtrlSetRechargeBeforePowerDown( uint32_t xoscPowerMode ); //! \return None // //***************************************************************************** -extern void SysCtrlAdjustRechargeAfterPowerDown( uint32_t vddrRechargeMargin ); +extern void SysCtrlAdjustRechargeAfterPowerDown(uint32_t vddrRechargeMargin); //***************************************************************************** // @@ -412,21 +410,21 @@ extern void SysCtrlAdjustRechargeAfterPowerDown( uint32_t vddrRechargeMargin ); //! \return None // //***************************************************************************** -extern void SysCtrl_DCDC_VoltageConditionalControl( void ); +extern void SysCtrl_DCDC_VoltageConditionalControl(void); //***************************************************************************** // \name Return values from calling SysCtrlResetSourceGet() //@{ //***************************************************************************** -#define RSTSRC_PWR_ON (( AON_PMCTL_RESETCTL_RESET_SRC_PWR_ON ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_PIN_RESET (( AON_PMCTL_RESETCTL_RESET_SRC_PIN_RESET ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_VDDS_LOSS (( AON_PMCTL_RESETCTL_RESET_SRC_VDDS_LOSS ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_VDDR_LOSS (( AON_PMCTL_RESETCTL_RESET_SRC_VDDR_LOSS ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_CLK_LOSS (( AON_PMCTL_RESETCTL_RESET_SRC_CLK_LOSS ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_SYSRESET (( AON_PMCTL_RESETCTL_RESET_SRC_SYSRESET ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_WARMRESET (( AON_PMCTL_RESETCTL_RESET_SRC_WARMRESET ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_WAKEUP_FROM_SHUTDOWN ((( AON_PMCTL_RESETCTL_RESET_SRC_M ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) + 1 ) -#define RSTSRC_WAKEUP_FROM_TCK_NOISE ((( AON_PMCTL_RESETCTL_RESET_SRC_M ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) + 2 ) +#define RSTSRC_PWR_ON ((AON_PMCTL_RESETCTL_RESET_SRC_PWR_ON) >> (AON_PMCTL_RESETCTL_RESET_SRC_S)) +#define RSTSRC_PIN_RESET ((AON_PMCTL_RESETCTL_RESET_SRC_PIN_RESET) >> (AON_PMCTL_RESETCTL_RESET_SRC_S)) +#define RSTSRC_VDDS_LOSS ((AON_PMCTL_RESETCTL_RESET_SRC_VDDS_LOSS) >> (AON_PMCTL_RESETCTL_RESET_SRC_S)) +#define RSTSRC_VDDR_LOSS ((AON_PMCTL_RESETCTL_RESET_SRC_VDDR_LOSS) >> (AON_PMCTL_RESETCTL_RESET_SRC_S)) +#define RSTSRC_CLK_LOSS ((AON_PMCTL_RESETCTL_RESET_SRC_CLK_LOSS) >> (AON_PMCTL_RESETCTL_RESET_SRC_S)) +#define RSTSRC_SYSRESET ((AON_PMCTL_RESETCTL_RESET_SRC_SYSRESET) >> (AON_PMCTL_RESETCTL_RESET_SRC_S)) +#define RSTSRC_WARMRESET ((AON_PMCTL_RESETCTL_RESET_SRC_WARMRESET) >> (AON_PMCTL_RESETCTL_RESET_SRC_S)) +#define RSTSRC_WAKEUP_FROM_SHUTDOWN (((AON_PMCTL_RESETCTL_RESET_SRC_M) >> (AON_PMCTL_RESETCTL_RESET_SRC_S)) + 1) +#define RSTSRC_WAKEUP_FROM_TCK_NOISE (((AON_PMCTL_RESETCTL_RESET_SRC_M) >> (AON_PMCTL_RESETCTL_RESET_SRC_S)) + 2) //@} //***************************************************************************** @@ -449,7 +447,7 @@ extern void SysCtrl_DCDC_VoltageConditionalControl( void ); //! - \ref RSTSRC_WAKEUP_FROM_TCK_NOISE // //***************************************************************************** -extern uint32_t SysCtrlResetSourceGet( void ); +extern uint32_t SysCtrlResetSourceGet(void); //***************************************************************************** // @@ -459,15 +457,15 @@ extern uint32_t SysCtrlResetSourceGet( void ); // //***************************************************************************** __STATIC_INLINE void -SysCtrlSystemReset( void ) +SysCtrlSystemReset(void) { // Disable CPU interrupts CPUcpsid(); // Write reset register - HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_SYSRESET_BITN ) = 1; + HWREGBITW(AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_SYSRESET_BITN) = 1; // Finally, wait until the above write propagates - while ( 1 ) + while (1) { // Do nothing, just wait for the reset (and never return from here) } @@ -526,36 +524,36 @@ SysCtrlClockLossResetDisable(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_SysCtrlIdle -#undef SysCtrlIdle -#define SysCtrlIdle ROM_SysCtrlIdle +#undef SysCtrlIdle +#define SysCtrlIdle ROM_SysCtrlIdle #endif #ifdef ROM_SysCtrlShutdownWithAbort -#undef SysCtrlShutdownWithAbort -#define SysCtrlShutdownWithAbort ROM_SysCtrlShutdownWithAbort +#undef SysCtrlShutdownWithAbort +#define SysCtrlShutdownWithAbort ROM_SysCtrlShutdownWithAbort #endif #ifdef ROM_SysCtrlShutdown -#undef SysCtrlShutdown -#define SysCtrlShutdown ROM_SysCtrlShutdown +#undef SysCtrlShutdown +#define SysCtrlShutdown ROM_SysCtrlShutdown #endif #ifdef ROM_SysCtrlStandby -#undef SysCtrlStandby -#define SysCtrlStandby ROM_SysCtrlStandby +#undef SysCtrlStandby +#define SysCtrlStandby ROM_SysCtrlStandby #endif #ifdef ROM_SysCtrlSetRechargeBeforePowerDown -#undef SysCtrlSetRechargeBeforePowerDown +#undef SysCtrlSetRechargeBeforePowerDown #define SysCtrlSetRechargeBeforePowerDown ROM_SysCtrlSetRechargeBeforePowerDown #endif #ifdef ROM_SysCtrlAdjustRechargeAfterPowerDown -#undef SysCtrlAdjustRechargeAfterPowerDown +#undef SysCtrlAdjustRechargeAfterPowerDown #define SysCtrlAdjustRechargeAfterPowerDown ROM_SysCtrlAdjustRechargeAfterPowerDown #endif #ifdef ROM_SysCtrl_DCDC_VoltageConditionalControl -#undef SysCtrl_DCDC_VoltageConditionalControl +#undef SysCtrl_DCDC_VoltageConditionalControl #define SysCtrl_DCDC_VoltageConditionalControl ROM_SysCtrl_DCDC_VoltageConditionalControl #endif #ifdef ROM_SysCtrlResetSourceGet -#undef SysCtrlResetSourceGet -#define SysCtrlResetSourceGet ROM_SysCtrlResetSourceGet +#undef SysCtrlResetSourceGet +#define SysCtrlResetSourceGet ROM_SysCtrlResetSourceGet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/systick.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/systick.h index d065440..c471218 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/systick.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/systick.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: systick.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Prototypes for the SysTick driver. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: systick.h + * Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) + * Revision: 49048 + * + * Description: Prototypes for the SysTick driver. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,17 +55,16 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include #include "../inc/hw_ints.h" #include "../inc/hw_nvic.h" #include "../inc/hw_types.h" #include "debug.h" #include "interrupt.h" +#include +#include //***************************************************************************** // diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/systick_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/systick_doc.h index 70848fc..0eaecd3 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/systick_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/systick_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: systick_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: systick_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup systick_api //! @{ //! \section sec_systick Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/timer.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/timer.h index b010b3b..4110801 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/timer.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/timer.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: timer.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: timer.h + * Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) + * Revision: 49048 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //**************************************************************************** // @@ -53,18 +53,17 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_gpt.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" +#include "interrupt.h" #include #include -#include "../inc/hw_ints.h" -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_gpt.h" -#include "interrupt.h" -#include "debug.h" //***************************************************************************** // @@ -80,14 +79,14 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define TimerConfigure NOROM_TimerConfigure -#define TimerLevelControl NOROM_TimerLevelControl -#define TimerStallControl NOROM_TimerStallControl -#define TimerWaitOnTriggerControl NOROM_TimerWaitOnTriggerControl -#define TimerIntRegister NOROM_TimerIntRegister -#define TimerIntUnregister NOROM_TimerIntUnregister -#define TimerMatchUpdateMode NOROM_TimerMatchUpdateMode -#define TimerIntervalLoadMode NOROM_TimerIntervalLoadMode +#define TimerConfigure NOROM_TimerConfigure +#define TimerLevelControl NOROM_TimerLevelControl +#define TimerStallControl NOROM_TimerStallControl +#define TimerWaitOnTriggerControl NOROM_TimerWaitOnTriggerControl +#define TimerIntRegister NOROM_TimerIntRegister +#define TimerIntUnregister NOROM_TimerIntUnregister +#define TimerMatchUpdateMode NOROM_TimerMatchUpdateMode +#define TimerIntervalLoadMode NOROM_TimerIntervalLoadMode #endif //***************************************************************************** @@ -95,29 +94,29 @@ extern "C" // Values that can be passed to TimerConfigure as the ui32Config parameter. // //***************************************************************************** -#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer -#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count timer -#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer -#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count timer -#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers -#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer -#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer -#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer -#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer -#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer -#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer -#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output +#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer +#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count timer +#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer +#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count timer +#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers +#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer +#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer +#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer +#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer +#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer +#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer +#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output //***************************************************************************** // @@ -126,25 +125,25 @@ extern "C" // TimerIntStatus. // //***************************************************************************** -#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt -#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt -#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt +#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt +#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt +#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt //***************************************************************************** // // Values that can be passed to TimerControlEvent as the ui32Event parameter. // //***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges //***************************************************************************** // @@ -152,39 +151,39 @@ extern "C" // parameter. // //***************************************************************************** -#define TIMER_A 0x000000FF // Timer A -#define TIMER_B 0x0000FF00 // Timer B -#define TIMER_BOTH 0x0000FFFF // Timer Both +#define TIMER_A 0x000000FF // Timer A +#define TIMER_B 0x0000FF00 // Timer B +#define TIMER_BOTH 0x0000FFFF // Timer Both //***************************************************************************** // // Values that can be passed to GPTSynchronize as the ui32Timers parameter // //***************************************************************************** -#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A -#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B -#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A -#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B -#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A -#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B -#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A -#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B +#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A +#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B +#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A +#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B +#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A +#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B +#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A +#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B //***************************************************************************** // // Values that can be passed to TimerMatchUpdateMode // //***************************************************************************** -#define TIMER_MATCHUPDATE_NEXTCYCLE 0x00000000 // Apply match register on next cycle -#define TIMER_MATCHUPDATE_TIMEOUT 0x00000001 // Apply match register on next timeout +#define TIMER_MATCHUPDATE_NEXTCYCLE 0x00000000 // Apply match register on next cycle +#define TIMER_MATCHUPDATE_TIMEOUT 0x00000001 // Apply match register on next timeout //***************************************************************************** // // Values that can be passed to TimerIntervalLoad // //***************************************************************************** -#define TIMER_INTERVALLOAD_NEXTCYCLE 0x00000000 // Load TxR register with the value in the TxILR register on the next clock cycle -#define TIMER_INTERVALLOAD_TIMEOUT 0x00000001 // Load TxR register with the value in the TxILR register on next timeout +#define TIMER_INTERVALLOAD_NEXTCYCLE 0x00000000 // Load TxR register with the value in the TxILR register on the next clock cycle +#define TIMER_INTERVALLOAD_TIMEOUT 0x00000001 // Load TxR register with the value in the TxILR register on next timeout //***************************************************************************** // @@ -522,8 +521,7 @@ TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer) (ui32Timer == TIMER_BOTH)); // Return the appropriate prescale value. - return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPR) : - HWREG(ui32Base + GPT_O_TBPR)); + return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPR) : HWREG(ui32Base + GPT_O_TBPR)); } //***************************************************************************** @@ -597,8 +595,7 @@ TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer) ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); // Return the appropriate prescale match value. - return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPMR) : - HWREG(ui32Base + GPT_O_TBPMR)); + return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPMR) : HWREG(ui32Base + GPT_O_TBPMR)); } //***************************************************************************** @@ -674,8 +671,7 @@ TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer) ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); // Return the appropriate load value. - return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAILR) : - HWREG(ui32Base + GPT_O_TBILR)); + return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAILR) : HWREG(ui32Base + GPT_O_TBILR)); } //***************************************************************************** @@ -706,8 +702,7 @@ TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer) ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); // Return the appropriate timer value. - return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAR) : - HWREG(ui32Base + GPT_O_TBR)); + return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAR) : HWREG(ui32Base + GPT_O_TBR)); } //***************************************************************************** @@ -786,8 +781,7 @@ TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer) ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); // Return the appropriate match value. - return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAMATCHR) : - HWREG(ui32Base + GPT_O_TBMATCHR)); + return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAMATCHR) : HWREG(ui32Base + GPT_O_TBMATCHR)); } //***************************************************************************** @@ -936,8 +930,7 @@ TimerIntStatus(uint32_t ui32Base, bool bMasked) // Return either the interrupt status or the raw interrupt status as // requested. - return (bMasked ? HWREG(ui32Base + GPT_O_MIS) : - HWREG(ui32Base + GPT_O_RIS)); + return (bMasked ? HWREG(ui32Base + GPT_O_MIS) : HWREG(ui32Base + GPT_O_RIS)); } //***************************************************************************** @@ -1123,36 +1116,36 @@ extern void TimerIntervalLoadMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_ #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_TimerConfigure -#undef TimerConfigure -#define TimerConfigure ROM_TimerConfigure +#undef TimerConfigure +#define TimerConfigure ROM_TimerConfigure #endif #ifdef ROM_TimerLevelControl -#undef TimerLevelControl -#define TimerLevelControl ROM_TimerLevelControl +#undef TimerLevelControl +#define TimerLevelControl ROM_TimerLevelControl #endif #ifdef ROM_TimerStallControl -#undef TimerStallControl -#define TimerStallControl ROM_TimerStallControl +#undef TimerStallControl +#define TimerStallControl ROM_TimerStallControl #endif #ifdef ROM_TimerWaitOnTriggerControl -#undef TimerWaitOnTriggerControl -#define TimerWaitOnTriggerControl ROM_TimerWaitOnTriggerControl +#undef TimerWaitOnTriggerControl +#define TimerWaitOnTriggerControl ROM_TimerWaitOnTriggerControl #endif #ifdef ROM_TimerIntRegister -#undef TimerIntRegister -#define TimerIntRegister ROM_TimerIntRegister +#undef TimerIntRegister +#define TimerIntRegister ROM_TimerIntRegister #endif #ifdef ROM_TimerIntUnregister -#undef TimerIntUnregister -#define TimerIntUnregister ROM_TimerIntUnregister +#undef TimerIntUnregister +#define TimerIntUnregister ROM_TimerIntUnregister #endif #ifdef ROM_TimerMatchUpdateMode -#undef TimerMatchUpdateMode -#define TimerMatchUpdateMode ROM_TimerMatchUpdateMode +#undef TimerMatchUpdateMode +#define TimerMatchUpdateMode ROM_TimerMatchUpdateMode #endif #ifdef ROM_TimerIntervalLoadMode -#undef TimerIntervalLoadMode -#define TimerIntervalLoadMode ROM_TimerIntervalLoadMode +#undef TimerIntervalLoadMode +#define TimerIntervalLoadMode ROM_TimerIntervalLoadMode #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/timer_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/timer_doc.h index d15c086..b9e9b91 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/timer_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/timer_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: timer_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: timer_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup timer_api //! @{ //! \section sec_timer Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/trng.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/trng.h index e3cfd1e..1723dc7 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/trng.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/trng.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: trng.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and prototypes for the true random number gen. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: trng.h + * Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) + * Revision: 49048 + * + * Description: Defines and prototypes for the true random number gen. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,19 +55,18 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_trng.h" -#include "../inc/hw_memmap.h" #include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_trng.h" +#include "../inc/hw_types.h" +#include "cpu.h" #include "debug.h" #include "interrupt.h" -#include "cpu.h" +#include +#include //***************************************************************************** // @@ -83,8 +82,8 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define TRNGConfigure NOROM_TRNGConfigure -#define TRNGNumberGet NOROM_TRNGNumberGet +#define TRNGConfigure NOROM_TRNGConfigure +#define TRNGNumberGet NOROM_TRNGNumberGet #endif //***************************************************************************** @@ -92,12 +91,12 @@ extern "C" // // //***************************************************************************** -#define TRNG_NUMBER_READY 0x00000001 // -#define TRNG_FRO_SHUTDOWN 0x00000002 // -#define TRNG_NEED_CLOCK 0x80000000 // +#define TRNG_NUMBER_READY 0x00000001 // +#define TRNG_FRO_SHUTDOWN 0x00000002 // +#define TRNG_NEED_CLOCK 0x80000000 // -#define TRNG_HI_WORD 0x00000001 -#define TRNG_LOW_WORD 0x00000002 +#define TRNG_HI_WORD 0x00000001 +#define TRNG_LOW_WORD 0x00000002 //***************************************************************************** // @@ -422,12 +421,12 @@ TRNGIntUnregister(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_TRNGConfigure -#undef TRNGConfigure -#define TRNGConfigure ROM_TRNGConfigure +#undef TRNGConfigure +#define TRNGConfigure ROM_TRNGConfigure #endif #ifdef ROM_TRNGNumberGet -#undef TRNGNumberGet -#define TRNGNumberGet ROM_TRNGNumberGet +#undef TRNGNumberGet +#define TRNGNumberGet ROM_TRNGNumberGet #endif #endif @@ -440,7 +439,7 @@ TRNGIntUnregister(void) } #endif -#endif // __TRNG_H__ +#endif // __TRNG_H__ //***************************************************************************** // diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/uart.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/uart.h index 69afb60..42a2572 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/uart.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/uart.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: uart.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Defines and prototypes for the UART. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: uart.h + * Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) + * Revision: 49096 + * + * Description: Defines and prototypes for the UART. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,18 +55,17 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" #include "../inc/hw_types.h" #include "../inc/hw_uart.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "interrupt.h" #include "debug.h" +#include "interrupt.h" +#include +#include //***************************************************************************** // @@ -82,16 +81,16 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define UARTFIFOLevelGet NOROM_UARTFIFOLevelGet -#define UARTConfigSetExpClk NOROM_UARTConfigSetExpClk -#define UARTConfigGetExpClk NOROM_UARTConfigGetExpClk -#define UARTDisable NOROM_UARTDisable -#define UARTCharGetNonBlocking NOROM_UARTCharGetNonBlocking -#define UARTCharGet NOROM_UARTCharGet -#define UARTCharPutNonBlocking NOROM_UARTCharPutNonBlocking -#define UARTCharPut NOROM_UARTCharPut -#define UARTIntRegister NOROM_UARTIntRegister -#define UARTIntUnregister NOROM_UARTIntUnregister +#define UARTFIFOLevelGet NOROM_UARTFIFOLevelGet +#define UARTConfigSetExpClk NOROM_UARTConfigSetExpClk +#define UARTConfigGetExpClk NOROM_UARTConfigGetExpClk +#define UARTDisable NOROM_UARTDisable +#define UARTCharGetNonBlocking NOROM_UARTCharGetNonBlocking +#define UARTCharGet NOROM_UARTCharGet +#define UARTCharPutNonBlocking NOROM_UARTCharPutNonBlocking +#define UARTCharPut NOROM_UARTCharPut +#define UARTIntRegister NOROM_UARTIntRegister +#define UARTIntUnregister NOROM_UARTIntUnregister #endif //***************************************************************************** @@ -100,15 +99,15 @@ extern "C" // as the ui32IntFlags parameter, and returned from UARTIntStatus. // //***************************************************************************** -#define UART_INT_EOT ( UART_IMSC_EOTIM ) // End Of Transmission Interrupt Mask -#define UART_INT_OE ( UART_IMSC_OEIM ) // Overrun Error Interrupt Mask -#define UART_INT_BE ( UART_IMSC_BEIM ) // Break Error Interrupt Mask -#define UART_INT_PE ( UART_IMSC_PEIM ) // Parity Error Interrupt Mask -#define UART_INT_FE ( UART_IMSC_FEIM ) // Framing Error Interrupt Mask -#define UART_INT_RT ( UART_IMSC_RTIM ) // Receive Timeout Interrupt Mask -#define UART_INT_TX ( UART_IMSC_TXIM ) // Transmit Interrupt Mask -#define UART_INT_RX ( UART_IMSC_RXIM ) // Receive Interrupt Mask -#define UART_INT_CTS ( UART_IMSC_CTSMIM ) // CTS Modem Interrupt Mask +#define UART_INT_EOT (UART_IMSC_EOTIM) // End Of Transmission Interrupt Mask +#define UART_INT_OE (UART_IMSC_OEIM) // Overrun Error Interrupt Mask +#define UART_INT_BE (UART_IMSC_BEIM) // Break Error Interrupt Mask +#define UART_INT_PE (UART_IMSC_PEIM) // Parity Error Interrupt Mask +#define UART_INT_FE (UART_IMSC_FEIM) // Framing Error Interrupt Mask +#define UART_INT_RT (UART_IMSC_RTIM) // Receive Timeout Interrupt Mask +#define UART_INT_TX (UART_IMSC_TXIM) // Transmit Interrupt Mask +#define UART_INT_RX (UART_IMSC_RXIM) // Receive Interrupt Mask +#define UART_INT_CTS (UART_IMSC_CTSMIM) // CTS Modem Interrupt Mask //***************************************************************************** // @@ -119,20 +118,20 @@ extern "C" // UARTParityModeGet. // //***************************************************************************** -#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length -#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data -#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data -#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data -#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data -#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits -#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit -#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits -#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity -#define UART_CONFIG_PAR_NONE 0x00000000 // No parity -#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity -#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity -#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one -#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero +#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero //***************************************************************************** // @@ -140,11 +139,11 @@ extern "C" // and returned by UARTFIFOLevelGet in the pui32TxLevel. // //***************************************************************************** -#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full -#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full -#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full -#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full -#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full +#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full +#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full +#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full +#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full +#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full //***************************************************************************** // @@ -152,38 +151,38 @@ extern "C" // and returned by UARTFIFOLevelGet in the pui32RxLevel. // //***************************************************************************** -#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full -#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full -#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full -#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full -#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full +#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full +#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full +#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full +#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full +#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full //***************************************************************************** // // Values that can be passed to UARTDMAEnable() and UARTDMADisable(). // //***************************************************************************** -#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error -#define UART_DMA_TX 0x00000002 // Enable DMA for transmit -#define UART_DMA_RX 0x00000001 // Enable DMA for receive +#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error +#define UART_DMA_TX 0x00000002 // Enable DMA for transmit +#define UART_DMA_RX 0x00000001 // Enable DMA for receive //***************************************************************************** // // Values returned from UARTRxErrorGet(). // //***************************************************************************** -#define UART_RXERROR_OVERRUN 0x00000008 -#define UART_RXERROR_BREAK 0x00000004 -#define UART_RXERROR_PARITY 0x00000002 -#define UART_RXERROR_FRAMING 0x00000001 +#define UART_RXERROR_OVERRUN 0x00000008 +#define UART_RXERROR_BREAK 0x00000004 +#define UART_RXERROR_PARITY 0x00000002 +#define UART_RXERROR_FRAMING 0x00000001 //***************************************************************************** // // Values returned from the UARTBusy(). // //***************************************************************************** -#define UART_BUSY 0x00000001 -#define UART_IDLE 0x00000000 +#define UART_BUSY 0x00000001 +#define UART_IDLE 0x00000000 //***************************************************************************** // @@ -209,8 +208,8 @@ extern "C" static bool UARTBaseValid(uint32_t ui32Base) { - return (( ui32Base == UART0_BASE ) || ( ui32Base == UART0_NONBUF_BASE ) || - ( ui32Base == UART1_BASE ) || ( ui32Base == UART1_NONBUF_BASE ) ); + return ((ui32Base == UART0_BASE) || (ui32Base == UART0_NONBUF_BASE) || + (ui32Base == UART1_BASE) || (ui32Base == UART1_NONBUF_BASE)); } #endif @@ -248,7 +247,8 @@ UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity) // Set the parity mode. HWREG(ui32Base + UART_O_LCRH) = ((HWREG(ui32Base + UART_O_LCRH) & ~(UART_LCRH_SPS | UART_LCRH_EPS | - UART_LCRH_PEN)) | ui32Parity); + UART_LCRH_PEN)) | + ui32Parity); } //***************************************************************************** @@ -641,8 +641,7 @@ UARTBusy(uint32_t ui32Base) ASSERT(UARTBaseValid(ui32Base)); // Determine if the UART is busy. - return ((HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) ? - UART_BUSY : UART_IDLE); + return ((HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) ? UART_BUSY : UART_IDLE); } //***************************************************************************** @@ -668,9 +667,7 @@ UARTBreakCtl(uint32_t ui32Base, bool bBreakState) // Set the break condition as requested. HWREG(ui32Base + UART_O_LCRH) = - (bBreakState ? - (HWREG(ui32Base + UART_O_LCRH) | UART_LCRH_BRK) : - (HWREG(ui32Base + UART_O_LCRH) & ~(UART_LCRH_BRK))); + (bBreakState ? (HWREG(ui32Base + UART_O_LCRH) | UART_LCRH_BRK) : (HWREG(ui32Base + UART_O_LCRH) & ~(UART_LCRH_BRK))); } //***************************************************************************** @@ -998,12 +995,12 @@ UARTRxErrorClear(uint32_t ui32Base) // //***************************************************************************** __STATIC_INLINE void -UARTHwFlowControlEnable( uint32_t ui32Base ) +UARTHwFlowControlEnable(uint32_t ui32Base) { // Check the arguments. - ASSERT( UARTBaseValid( ui32Base )); + ASSERT(UARTBaseValid(ui32Base)); - HWREG( ui32Base + UART_O_CTL ) |= ( UART_CTL_CTSEN | UART_CTL_RTSEN ); + HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_CTSEN | UART_CTL_RTSEN); } //***************************************************************************** @@ -1018,15 +1015,14 @@ UARTHwFlowControlEnable( uint32_t ui32Base ) // //***************************************************************************** __STATIC_INLINE void -UARTHwFlowControlDisable( uint32_t ui32Base ) +UARTHwFlowControlDisable(uint32_t ui32Base) { // Check the arguments. - ASSERT( UARTBaseValid( ui32Base )); + ASSERT(UARTBaseValid(ui32Base)); - HWREG( ui32Base + UART_O_CTL ) &= ~( UART_CTL_CTSEN | UART_CTL_RTSEN ); + HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_CTSEN | UART_CTL_RTSEN); } - //***************************************************************************** // // Support for DriverLib in ROM: @@ -1036,44 +1032,44 @@ UARTHwFlowControlDisable( uint32_t ui32Base ) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_UARTFIFOLevelGet -#undef UARTFIFOLevelGet -#define UARTFIFOLevelGet ROM_UARTFIFOLevelGet +#undef UARTFIFOLevelGet +#define UARTFIFOLevelGet ROM_UARTFIFOLevelGet #endif #ifdef ROM_UARTConfigSetExpClk -#undef UARTConfigSetExpClk -#define UARTConfigSetExpClk ROM_UARTConfigSetExpClk +#undef UARTConfigSetExpClk +#define UARTConfigSetExpClk ROM_UARTConfigSetExpClk #endif #ifdef ROM_UARTConfigGetExpClk -#undef UARTConfigGetExpClk -#define UARTConfigGetExpClk ROM_UARTConfigGetExpClk +#undef UARTConfigGetExpClk +#define UARTConfigGetExpClk ROM_UARTConfigGetExpClk #endif #ifdef ROM_UARTDisable -#undef UARTDisable -#define UARTDisable ROM_UARTDisable +#undef UARTDisable +#define UARTDisable ROM_UARTDisable #endif #ifdef ROM_UARTCharGetNonBlocking -#undef UARTCharGetNonBlocking -#define UARTCharGetNonBlocking ROM_UARTCharGetNonBlocking +#undef UARTCharGetNonBlocking +#define UARTCharGetNonBlocking ROM_UARTCharGetNonBlocking #endif #ifdef ROM_UARTCharGet -#undef UARTCharGet -#define UARTCharGet ROM_UARTCharGet +#undef UARTCharGet +#define UARTCharGet ROM_UARTCharGet #endif #ifdef ROM_UARTCharPutNonBlocking -#undef UARTCharPutNonBlocking -#define UARTCharPutNonBlocking ROM_UARTCharPutNonBlocking +#undef UARTCharPutNonBlocking +#define UARTCharPutNonBlocking ROM_UARTCharPutNonBlocking #endif #ifdef ROM_UARTCharPut -#undef UARTCharPut -#define UARTCharPut ROM_UARTCharPut +#undef UARTCharPut +#define UARTCharPut ROM_UARTCharPut #endif #ifdef ROM_UARTIntRegister -#undef UARTIntRegister -#define UARTIntRegister ROM_UARTIntRegister +#undef UARTIntRegister +#define UARTIntRegister ROM_UARTIntRegister #endif #ifdef ROM_UARTIntUnregister -#undef UARTIntUnregister -#define UARTIntUnregister ROM_UARTIntUnregister +#undef UARTIntUnregister +#define UARTIntUnregister ROM_UARTIntUnregister #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/uart_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/uart_doc.h index ba77f94..21d1bf9 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/uart_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/uart_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: uart_doc.h -* Revised: 2018-02-09 15:45:36 +0100 (fr, 09 feb 2018) -* Revision: 51470 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: uart_doc.h + * Revised: 2018-02-09 15:45:36 +0100 (fr, 09 feb 2018) + * Revision: 51470 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ /*! \addtogroup uart_api @{ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/udma.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/udma.h index 0ac722a..be36838 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/udma.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/udma.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: udma.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and prototypes for the uDMA controller. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: udma.h + * Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) + * Revision: 49048 + * + * Description: Defines and prototypes for the uDMA controller. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,18 +55,17 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" #include "../inc/hw_ints.h" #include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "../inc/hw_udma.h" #include "debug.h" #include "interrupt.h" +#include +#include //***************************************************************************** // @@ -82,14 +81,14 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable -#define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable -#define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet -#define uDMAChannelControlSet NOROM_uDMAChannelControlSet -#define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet -#define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet -#define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet -#define uDMAChannelModeGet NOROM_uDMAChannelModeGet +#define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable +#define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable +#define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet +#define uDMAChannelControlSet NOROM_uDMAChannelControlSet +#define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet +#define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet +#define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet +#define uDMAChannelModeGet NOROM_uDMAChannelModeGet #endif //***************************************************************************** @@ -102,12 +101,11 @@ extern "C" //***************************************************************************** typedef struct { - volatile void* pvSrcEndAddr; //!< The ending source address of the data transfer. - volatile void* pvDstEndAddr; //!< The ending destination address of the data transfer. - volatile uint32_t ui32Control; //!< The channel control mode. - volatile uint32_t ui32Spare; //!< An unused location. -} -tDMAControlTable; + volatile void* pvSrcEndAddr; //!< The ending source address of the data transfer. + volatile void* pvDstEndAddr; //!< The ending destination address of the data transfer. + volatile uint32_t ui32Control; //!< The channel control mode. + volatile uint32_t ui32Spare; //!< An unused location. +} tDMAControlTable; //***************************************************************************** // @@ -177,42 +175,40 @@ tDMAControlTable; //! \return None (this is not a function) // //***************************************************************************** -#define uDMATaskStructEntry(ui32TransferCount, \ - ui32ItemSize, \ - ui32SrcIncrement, \ - pvSrcAddr, \ - ui32DstIncrement, \ - pvDstAddr, \ - ui32ArbSize, \ - ui32Mode) \ -{ \ - (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (pvSrcAddr) : \ - ((void *)(&((uint8_t *)(pvSrcAddr))[((ui32TransferCount) << \ - ((ui32SrcIncrement) >> 26)) - 1]))), \ - (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (pvDstAddr) : \ - ((void *)(&((uint8_t *)(pvDstAddr))[((ui32TransferCount) << \ - ((ui32DstIncrement) >> 30)) - 1]))), \ - (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \ - (ui32ArbSize) | (((ui32TransferCount) - 1) << 4) | \ - ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ - ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ - (ui32Mode) | UDMA_MODE_ALT_SELECT : (ui32Mode)), 0 \ -} +#define uDMATaskStructEntry(ui32TransferCount, \ + ui32ItemSize, \ + ui32SrcIncrement, \ + pvSrcAddr, \ + ui32DstIncrement, \ + pvDstAddr, \ + ui32ArbSize, \ + ui32Mode) \ + { \ + (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (pvSrcAddr) : ((void*)(&((uint8_t*)(pvSrcAddr))[((ui32TransferCount) << ((ui32SrcIncrement) >> 26)) - 1]))), \ + (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (pvDstAddr) : ((void*)(&((uint8_t*)(pvDstAddr))[((ui32TransferCount) << ((ui32DstIncrement) >> 30)) - 1]))), \ + (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \ + (ui32ArbSize) | (((ui32TransferCount) - 1) << 4) | \ + ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ + ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) \ + ? (ui32Mode) | UDMA_MODE_ALT_SELECT \ + : (ui32Mode)), \ + 0 \ + } //***************************************************************************** // // The hardware configured number of uDMA channels. // //***************************************************************************** -#define UDMA_NUM_CHANNELS 21 +#define UDMA_NUM_CHANNELS 21 //***************************************************************************** // // The level of priority for the uDMA channels // //***************************************************************************** -#define UDMA_PRIORITY_LOW 0x00000000 -#define UDMA_PRIORITY_HIGH 0x00000001 +#define UDMA_PRIORITY_LOW 0x00000000 +#define UDMA_PRIORITY_HIGH 0x00000001 //***************************************************************************** // @@ -220,11 +216,11 @@ tDMAControlTable; // uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). // //***************************************************************************** -#define UDMA_ATTR_USEBURST 0x00000001 -#define UDMA_ATTR_ALTSELECT 0x00000002 +#define UDMA_ATTR_USEBURST 0x00000001 +#define UDMA_ATTR_ALTSELECT 0x00000002 #define UDMA_ATTR_HIGH_PRIORITY 0x00000004 -#define UDMA_ATTR_REQMASK 0x00000008 -#define UDMA_ATTR_ALL 0x0000000F +#define UDMA_ATTR_REQMASK 0x00000008 +#define UDMA_ATTR_ALL 0x0000000F //***************************************************************************** // @@ -232,56 +228,56 @@ tDMAControlTable; // uDMAChannelModeGet(). // //***************************************************************************** -#define UDMA_MODE_STOP 0x00000000 -#define UDMA_MODE_BASIC 0x00000001 -#define UDMA_MODE_AUTO 0x00000002 -#define UDMA_MODE_PINGPONG 0x00000003 -#define UDMA_MODE_MEM_SCATTER_GATHER \ +#define UDMA_MODE_STOP 0x00000000 +#define UDMA_MODE_BASIC 0x00000001 +#define UDMA_MODE_AUTO 0x00000002 +#define UDMA_MODE_PINGPONG 0x00000003 +#define UDMA_MODE_MEM_SCATTER_GATHER \ 0x00000004 -#define UDMA_MODE_PER_SCATTER_GATHER \ +#define UDMA_MODE_PER_SCATTER_GATHER \ 0x00000006 -#define UDMA_MODE_M 0x00000007 // uDMA Transfer Mode -#define UDMA_MODE_ALT_SELECT 0x00000001 +#define UDMA_MODE_M 0x00000007 // uDMA Transfer Mode +#define UDMA_MODE_ALT_SELECT 0x00000001 //***************************************************************************** // // Channel configuration values that can be passed to uDMAControlSet(). // //***************************************************************************** -#define UDMA_DST_INC_8 0x00000000 -#define UDMA_DST_INC_16 0x40000000 -#define UDMA_DST_INC_32 0x80000000 -#define UDMA_DST_INC_NONE 0xC0000000 -#define UDMA_DST_INC_M 0xC0000000 // Destination Address Increment -#define UDMA_DST_INC_S 30 -#define UDMA_SRC_INC_8 0x00000000 -#define UDMA_SRC_INC_16 0x04000000 -#define UDMA_SRC_INC_32 0x08000000 -#define UDMA_SRC_INC_NONE 0x0c000000 -#define UDMA_SRC_INC_M 0x0C000000 // Source Address Increment -#define UDMA_SRC_INC_S 26 -#define UDMA_SIZE_8 0x00000000 -#define UDMA_SIZE_16 0x11000000 -#define UDMA_SIZE_32 0x22000000 -#define UDMA_SIZE_M 0x33000000 // Data Size -#define UDMA_SIZE_S 24 -#define UDMA_ARB_1 0x00000000 -#define UDMA_ARB_2 0x00004000 -#define UDMA_ARB_4 0x00008000 -#define UDMA_ARB_8 0x0000c000 -#define UDMA_ARB_16 0x00010000 -#define UDMA_ARB_32 0x00014000 -#define UDMA_ARB_64 0x00018000 -#define UDMA_ARB_128 0x0001c000 -#define UDMA_ARB_256 0x00020000 -#define UDMA_ARB_512 0x00024000 -#define UDMA_ARB_1024 0x00028000 -#define UDMA_ARB_M 0x0003C000 // Arbitration Size -#define UDMA_ARB_S 14 -#define UDMA_NEXT_USEBURST 0x00000008 -#define UDMA_XFER_SIZE_MAX 1024 -#define UDMA_XFER_SIZE_M 0x00003FF0 // Transfer size -#define UDMA_XFER_SIZE_S 4 +#define UDMA_DST_INC_8 0x00000000 +#define UDMA_DST_INC_16 0x40000000 +#define UDMA_DST_INC_32 0x80000000 +#define UDMA_DST_INC_NONE 0xC0000000 +#define UDMA_DST_INC_M 0xC0000000 // Destination Address Increment +#define UDMA_DST_INC_S 30 +#define UDMA_SRC_INC_8 0x00000000 +#define UDMA_SRC_INC_16 0x04000000 +#define UDMA_SRC_INC_32 0x08000000 +#define UDMA_SRC_INC_NONE 0x0c000000 +#define UDMA_SRC_INC_M 0x0C000000 // Source Address Increment +#define UDMA_SRC_INC_S 26 +#define UDMA_SIZE_8 0x00000000 +#define UDMA_SIZE_16 0x11000000 +#define UDMA_SIZE_32 0x22000000 +#define UDMA_SIZE_M 0x33000000 // Data Size +#define UDMA_SIZE_S 24 +#define UDMA_ARB_1 0x00000000 +#define UDMA_ARB_2 0x00004000 +#define UDMA_ARB_4 0x00008000 +#define UDMA_ARB_8 0x0000c000 +#define UDMA_ARB_16 0x00010000 +#define UDMA_ARB_32 0x00014000 +#define UDMA_ARB_64 0x00018000 +#define UDMA_ARB_128 0x0001c000 +#define UDMA_ARB_256 0x00020000 +#define UDMA_ARB_512 0x00024000 +#define UDMA_ARB_1024 0x00028000 +#define UDMA_ARB_M 0x0003C000 // Arbitration Size +#define UDMA_ARB_S 14 +#define UDMA_NEXT_USEBURST 0x00000008 +#define UDMA_XFER_SIZE_MAX 1024 +#define UDMA_XFER_SIZE_M 0x00003FF0 // Transfer size +#define UDMA_XFER_SIZE_S 4 //***************************************************************************** // @@ -289,25 +285,25 @@ tDMAControlTable; // ID. // //***************************************************************************** -#define UDMA_CHAN_SW_EVT0 0 // Software Event Channel 0 -#define UDMA_CHAN_UART0_RX 1 // UART0 RX Data -#define UDMA_CHAN_UART0_TX 2 // UART0 RX Data -#define UDMA_CHAN_SSI0_RX 3 // SSI0 RX Data -#define UDMA_CHAN_SSI0_TX 4 // SSI0 RX Data -#define UDMA_CHAN_AUX_ADC 7 // AUX ADC event -#define UDMA_CHAN_AUX_SW 8 // AUX Software event -#define UDMA_CHAN_TIMER0_A 9 // Timer0 A event -#define UDMA_CHAN_TIMER0_B 10 // Timer0 B event -#define UDMA_CHAN_TIMER1_A 11 -#define UDMA_CHAN_TIMER1_B 12 -#define UDMA_CHAN_AON_PROG2 13 -#define UDMA_CHAN_DMA_PROG 14 -#define UDMA_CHAN_AON_RTC 15 -#define UDMA_CHAN_SSI1_RX 16 -#define UDMA_CHAN_SSI1_TX 17 -#define UDMA_CHAN_SW_EVT1 18 -#define UDMA_CHAN_SW_EVT2 19 -#define UDMA_CHAN_SW_EVT3 20 +#define UDMA_CHAN_SW_EVT0 0 // Software Event Channel 0 +#define UDMA_CHAN_UART0_RX 1 // UART0 RX Data +#define UDMA_CHAN_UART0_TX 2 // UART0 RX Data +#define UDMA_CHAN_SSI0_RX 3 // SSI0 RX Data +#define UDMA_CHAN_SSI0_TX 4 // SSI0 RX Data +#define UDMA_CHAN_AUX_ADC 7 // AUX ADC event +#define UDMA_CHAN_AUX_SW 8 // AUX Software event +#define UDMA_CHAN_TIMER0_A 9 // Timer0 A event +#define UDMA_CHAN_TIMER0_B 10 // Timer0 B event +#define UDMA_CHAN_TIMER1_A 11 +#define UDMA_CHAN_TIMER1_B 12 +#define UDMA_CHAN_AON_PROG2 13 +#define UDMA_CHAN_DMA_PROG 14 +#define UDMA_CHAN_AON_RTC 15 +#define UDMA_CHAN_SSI1_RX 16 +#define UDMA_CHAN_SSI1_TX 17 +#define UDMA_CHAN_SW_EVT1 18 +#define UDMA_CHAN_SW_EVT2 19 +#define UDMA_CHAN_SW_EVT3 20 //***************************************************************************** // @@ -315,8 +311,8 @@ tDMAControlTable; // control structure should be used. // //***************************************************************************** -#define UDMA_PRI_SELECT 0x00000000 -#define UDMA_ALT_SELECT 0x00000020 +#define UDMA_PRI_SELECT 0x00000000 +#define UDMA_ALT_SELECT 0x00000020 //***************************************************************************** // @@ -514,8 +510,7 @@ uDMAChannelIsEnabled(uint32_t ui32Base, uint32_t ui32ChannelNum) // AND the specified channel bit with the enable register, and return the // result. - return ((HWREG(ui32Base + UDMA_O_SETCHANNELEN) & (1 << ui32ChannelNum)) ? - true : false); + return ((HWREG(ui32Base + UDMA_O_SETCHANNELEN) & (1 << ui32ChannelNum)) ? true : false); } //***************************************************************************** @@ -1150,8 +1145,7 @@ uDMAChannelPriorityGet(uint32_t ui32Base, uint32_t ui32ChannelNum) ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); // Return the channel priority. - return (HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum) ? - UDMA_PRIORITY_HIGH : UDMA_PRIORITY_LOW); + return (HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum) ? UDMA_PRIORITY_HIGH : UDMA_PRIORITY_LOW); } //***************************************************************************** @@ -1187,36 +1181,36 @@ uDMAChannelPriorityClear(uint32_t ui32Base, uint32_t ui32ChannelNum) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_uDMAChannelAttributeEnable -#undef uDMAChannelAttributeEnable -#define uDMAChannelAttributeEnable ROM_uDMAChannelAttributeEnable +#undef uDMAChannelAttributeEnable +#define uDMAChannelAttributeEnable ROM_uDMAChannelAttributeEnable #endif #ifdef ROM_uDMAChannelAttributeDisable -#undef uDMAChannelAttributeDisable -#define uDMAChannelAttributeDisable ROM_uDMAChannelAttributeDisable +#undef uDMAChannelAttributeDisable +#define uDMAChannelAttributeDisable ROM_uDMAChannelAttributeDisable #endif #ifdef ROM_uDMAChannelAttributeGet -#undef uDMAChannelAttributeGet -#define uDMAChannelAttributeGet ROM_uDMAChannelAttributeGet +#undef uDMAChannelAttributeGet +#define uDMAChannelAttributeGet ROM_uDMAChannelAttributeGet #endif #ifdef ROM_uDMAChannelControlSet -#undef uDMAChannelControlSet -#define uDMAChannelControlSet ROM_uDMAChannelControlSet +#undef uDMAChannelControlSet +#define uDMAChannelControlSet ROM_uDMAChannelControlSet #endif #ifdef ROM_uDMAChannelTransferSet -#undef uDMAChannelTransferSet -#define uDMAChannelTransferSet ROM_uDMAChannelTransferSet +#undef uDMAChannelTransferSet +#define uDMAChannelTransferSet ROM_uDMAChannelTransferSet #endif #ifdef ROM_uDMAChannelScatterGatherSet -#undef uDMAChannelScatterGatherSet -#define uDMAChannelScatterGatherSet ROM_uDMAChannelScatterGatherSet +#undef uDMAChannelScatterGatherSet +#define uDMAChannelScatterGatherSet ROM_uDMAChannelScatterGatherSet #endif #ifdef ROM_uDMAChannelSizeGet -#undef uDMAChannelSizeGet -#define uDMAChannelSizeGet ROM_uDMAChannelSizeGet +#undef uDMAChannelSizeGet +#define uDMAChannelSizeGet ROM_uDMAChannelSizeGet #endif #ifdef ROM_uDMAChannelModeGet -#undef uDMAChannelModeGet -#define uDMAChannelModeGet ROM_uDMAChannelModeGet +#undef uDMAChannelModeGet +#define uDMAChannelModeGet ROM_uDMAChannelModeGet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/vims.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/vims.h index ac48eaf..58a72ff 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/vims.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/vims.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: vims.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the VIMS. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: vims.h + * Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) + * Revision: 47343 + * + * Description: Defines and prototypes for the VIMS. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,16 +55,15 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" #include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "../inc/hw_vims.h" #include "debug.h" +#include +#include //***************************************************************************** // @@ -80,10 +79,10 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define VIMSConfigure NOROM_VIMSConfigure -#define VIMSModeSet NOROM_VIMSModeSet -#define VIMSModeGet NOROM_VIMSModeGet -#define VIMSModeSafeSet NOROM_VIMSModeSafeSet +#define VIMSConfigure NOROM_VIMSConfigure +#define VIMSModeSet NOROM_VIMSModeSet +#define VIMSModeGet NOROM_VIMSModeGet +#define VIMSModeSafeSet NOROM_VIMSModeSafeSet #endif //***************************************************************************** @@ -92,11 +91,11 @@ extern "C" // and returned from VIMSModeGet(). // //***************************************************************************** -#define VIMS_MODE_CHANGING 0x4 // VIMS mode is changing now and VIMS_MODE +#define VIMS_MODE_CHANGING 0x4 // VIMS mode is changing now and VIMS_MODE // can not be changed at moment. #define VIMS_MODE_DISABLED (VIMS_CTL_MODE_GPRAM) // Disabled mode (GPRAM enabled). -#define VIMS_MODE_ENABLED (VIMS_CTL_MODE_CACHE) // Enabled mode, only USERCODE is cached. -#define VIMS_MODE_OFF (VIMS_CTL_MODE_OFF) // VIMS Cache RAM is off +#define VIMS_MODE_ENABLED (VIMS_CTL_MODE_CACHE) // Enabled mode, only USERCODE is cached. +#define VIMS_MODE_OFF (VIMS_CTL_MODE_OFF) // VIMS Cache RAM is off //***************************************************************************** // @@ -277,9 +276,9 @@ extern uint32_t VIMSModeGet(uint32_t ui32Base); //! \sa \ref VIMSModeSet() and \ref VIMSModeGet() // //***************************************************************************** -extern void VIMSModeSafeSet( uint32_t ui32Base, - uint32_t ui32NewMode, - bool blocking ); +extern void VIMSModeSafeSet(uint32_t ui32Base, + uint32_t ui32NewMode, + bool blocking); //***************************************************************************** // @@ -334,20 +333,20 @@ VIMSLineBufEnable(uint32_t ui32Base) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_VIMSConfigure -#undef VIMSConfigure -#define VIMSConfigure ROM_VIMSConfigure +#undef VIMSConfigure +#define VIMSConfigure ROM_VIMSConfigure #endif #ifdef ROM_VIMSModeSet -#undef VIMSModeSet -#define VIMSModeSet ROM_VIMSModeSet +#undef VIMSModeSet +#define VIMSModeSet ROM_VIMSModeSet #endif #ifdef ROM_VIMSModeGet -#undef VIMSModeGet -#define VIMSModeGet ROM_VIMSModeGet +#undef VIMSModeGet +#define VIMSModeGet ROM_VIMSModeGet #endif #ifdef ROM_VIMSModeSafeSet -#undef VIMSModeSafeSet -#define VIMSModeSafeSet ROM_VIMSModeSafeSet +#undef VIMSModeSafeSet +#define VIMSModeSafeSet ROM_VIMSModeSafeSet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.h index a964eb3..3db6a6c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: wdt.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and prototypes for the Watchdog Timer. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: wdt.h + * Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) + * Revision: 49048 + * + * Description: Defines and prototypes for the Watchdog Timer. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,27 +55,26 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" #include "../inc/hw_ints.h" #include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "../inc/hw_wdt.h" #include "debug.h" #include "interrupt.h" +#include +#include //***************************************************************************** // // The following are defines for the bit fields in the WDT_O_LOCK register. // //***************************************************************************** -#define WATCHDOG_LOCK_UNLOCKED 0x00000000 // Unlocked -#define WATCHDOG_LOCK_LOCKED 0x00000001 // Locked -#define WATCHDOG_LOCK_UNLOCK 0x1ACCE551 // Unlocks the Watchdog Timer +#define WATCHDOG_LOCK_UNLOCKED 0x00000000 // Unlocked +#define WATCHDOG_LOCK_LOCKED 0x00000001 // Locked +#define WATCHDOG_LOCK_UNLOCK 0x1ACCE551 // Unlocks the Watchdog Timer //***************************************************************************** // @@ -83,15 +82,15 @@ extern "C" // WDT_MIS registers. // //***************************************************************************** -#define WATCHDOG_INT_TIMEOUT 0x00000001 // Watchdog timer expired +#define WATCHDOG_INT_TIMEOUT 0x00000001 // Watchdog timer expired //***************************************************************************** // // The type of interrupt that can be generated by the watchdog. // //***************************************************************************** -#define WATCHDOG_INT_TYPE_INT 0x00000000 -#define WATCHDOG_INT_TYPE_NMI 0x00000004 +#define WATCHDOG_INT_TYPE_INT 0x00000000 +#define WATCHDOG_INT_TYPE_NMI 0x00000004 //***************************************************************************** // @@ -231,8 +230,7 @@ __STATIC_INLINE bool WatchdogLockState(void) { // Get the lock state. - return ((HWREG(WDT_BASE + WDT_O_LOCK) == WATCHDOG_LOCK_LOCKED) ? - true : false); + return ((HWREG(WDT_BASE + WDT_O_LOCK) == WATCHDOG_LOCK_LOCKED) ? true : false); } //***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog_doc.h index 877bab7..552cd74 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: watchdog_doc.h -* Revised: 2018-02-09 15:45:36 +0100 (Fri, 09 Feb 2018) -* Revision: 51470 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: watchdog_doc.h + * Revised: 2018-02-09 15:45:36 +0100 (Fri, 09 Feb 2018) + * Revision: 51470 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup wdt_api //! @{ //! \section sec_wdt Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/asmdefs.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/asmdefs.h index ddb5315..1d02ca8 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/asmdefs.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/asmdefs.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: asmdefs.h -* Revised: 2015-06-05 14:39:10 +0200 (Fri, 05 Jun 2015) -* Revision: 43803 -* -* Description: Macros to allow assembly code be portable among tool chains. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: asmdefs.h + * Revised: 2015-06-05 14:39:10 +0200 (Fri, 05 Jun 2015) + * Revision: 43803 + * + * Description: Macros to allow assembly code be portable among tool chains. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __ASMDEFS_H__ #define __ASMDEFS_H__ @@ -46,27 +46,27 @@ //***************************************************************************** #ifdef __IAR_SYSTEMS_ICC__ - // - // Section headers. - // - #define __LIBRARY__ module - #define __TEXT__ rseg CODE:CODE(2) - #define __DATA__ rseg DATA:DATA(2) - #define __BSS__ rseg DATA:DATA(2) - #define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) +// +// Section headers. +// +#define __LIBRARY__ module +#define __TEXT__ rseg CODE : CODE(2) +#define __DATA__ rseg DATA : DATA(2) +#define __BSS__ rseg DATA : DATA(2) +#define __TEXT_NOROOT__ rseg CODE : CODE : NOROOT(2) - // - // Assembler mnemonics. - // - #define __ALIGN__ alignrom 2 - #define __END__ end - #define __EXPORT__ export - #define __IMPORT__ import - #define __LABEL__ - #define __STR__ dcb - #define __THUMB_LABEL__ thumb - #define __WORD__ dcd - #define __INLINE_DATA__ data +// +// Assembler mnemonics. +// +#define __ALIGN__ alignrom 2 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ thumb +#define __WORD__ dcd +#define __INLINE_DATA__ data #endif // __IAR_SYSTEMS_ICC__ @@ -77,34 +77,34 @@ //***************************************************************************** #if defined(__GNUC__) - // - // The assembly code preamble required to put the assembler into the correct - // configuration. - // - .syntax unified +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// +.syntax unified .thumb - // - // Section headers. - // - #define __LIBRARY__ @ - #define __TEXT__ .text - #define __DATA__ .data - #define __BSS__ .bss - #define __TEXT_NOROOT__ .text +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text - // - // Assembler mnemonics. - // - #define __ALIGN__ .balign 4 - #define __END__ .end - #define __EXPORT__ .globl - #define __IMPORT__ .extern - #define __LABEL__ : - #define __STR__ .ascii - #define __THUMB_LABEL__ .thumb_func - #define __WORD__ .word - #define __INLINE_DATA__ +// +// Assembler mnemonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ #endif // __GNUC__ @@ -115,37 +115,35 @@ //***************************************************************************** #if defined(__CC_ARM) - // - // The assembly code preamble required to put the assembler into the correct - // configuration. - // - thumb - require8 - preserve8 + // + // The assembly code preamble required to put the assembler into the correct + // configuration. + // + thumb + require8 preserve8 - // - // Section headers. - // - #define __LIBRARY__ ; - #define __TEXT__ area ||.text||, code, readonly, align=2 - #define __DATA__ area ||.data||, data, align=2 - #define __BSS__ area ||.bss||, noinit, align=2 - #define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 +// +// Section headers. +// +#define __LIBRARY__ ; +#define __TEXT__ area ||.text ||, code, readonly, align = 2 +#define __DATA__ area ||.data ||, data, align = 2 +#define __BSS__ area ||.bss ||, noinit, align = 2 +#define __TEXT_NOROOT__ area ||.text ||, code, readonly, align = 2 - // - // Assembler mnemonics. - // - #define __ALIGN__ align 4 - #define __END__ end - #define __EXPORT__ export - #define __IMPORT__ import - #define __LABEL__ - #define __STR__ dcb - #define __THUMB_LABEL__ - #define __WORD__ dcd - #define __INLINE_DATA__ +// +// Assembler mnemonics. +// +#define __ALIGN__ align 4 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ +#define __WORD__ dcd +#define __INLINE_DATA__ #endif // __CC_ARM - #endif // __ASMDEF_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi.h index 7e7b603..692d892 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_adi.h -* Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) -* Revision: 42365 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_adi.h + * Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) + * Revision: 42365 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_ADI_H__ #define __HW_ADI_H__ @@ -154,21 +154,21 @@ // The following are defines for the ADI master instruction offsets. // //***************************************************************************** -#define ADI_O_DIR 0x00000000 // Offset for the direct access +#define ADI_O_DIR 0x00000000 // Offset for the direct access // instruction -#define ADI_O_SET 0x00000010 // Offset for 'Set' instruction. -#define ADI_O_CLR 0x00000020 // Offset for 'Clear' instruction. -#define ADI_O_MASK4B 0x00000040 // Offset for 4-bit masked access. +#define ADI_O_SET 0x00000010 // Offset for 'Set' instruction. +#define ADI_O_CLR 0x00000020 // Offset for 'Clear' instruction. +#define ADI_O_MASK4B 0x00000040 // Offset for 4-bit masked access. // Data bit[n] is written if mask // bit[n] is set ('1'). // Bits 7:4 are mask. Bits 3:0 are data. // Requires 'byte' write. -#define ADI_O_MASK8B 0x00000060 // Offset for 8-bit masked access. +#define ADI_O_MASK8B 0x00000060 // Offset for 8-bit masked access. // Data bit[n] is written if mask // bit[n] is set ('1'). Bits 15:8 are // mask. Bits 7:0 are data. Requires // 'short' write. -#define ADI_O_MASK16B 0x00000080 // Offset for 16-bit masked access. +#define ADI_O_MASK16B 0x00000080 // Offset for 16-bit masked access. // Data bit[n] is written if mask // bit[n] is set ('1'). Bits 31:16 // are mask. Bits 15:0 are data. @@ -179,8 +179,8 @@ // The following are defines for the ADI register offsets. // //***************************************************************************** -#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register -#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration +#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register +#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration //***************************************************************************** // @@ -188,26 +188,26 @@ // ADI_O_SLAVESTAT register. // //***************************************************************************** -#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ +#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ // signal. Writing 0 to this bit // forces a sync with slave, // ensuring that req will be 0. It // is recommended to write 0 to // this register before power down // of the master. -#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 -#define ADI_SLAVESTAT_DI_REQ_S 1 -#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK +#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 +#define ADI_SLAVESTAT_DI_REQ_S 1 +#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK // signal -#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 -#define ADI_SLAVESTAT_DI_ACK_S 0 +#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 +#define ADI_SLAVESTAT_DI_ACK_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_SLAVECONF register. // //***************************************************************************** -#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer +#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer // accessible when this bit is set. // (unless sticky_bit_overwrite is // asserted on top module) @@ -215,7 +215,7 @@ 0x00000080 #define ADI_SLAVECONF_CONFLOCK_S 7 #define ADI_SLAVECONF_WAITFORACK \ - 0x00000004 // A transaction on the ADI + 0x00000004 // A transaction on the ADI // interface does not end until ack // has been received from the slave // when this bit is set. @@ -224,7 +224,7 @@ 0x00000004 #define ADI_SLAVECONF_WAITFORACK_S 2 #define ADI_SLAVECONF_ADICLKSPEED_M \ - 0x00000003 // Sets the period of an ADI + 0x00000003 // Sets the period of an ADI // transactions. All transactions // takes an even number of clock // cycles,- ADI clock rising edge @@ -250,103 +250,103 @@ // to not use these. // //***************************************************************************** -#define ADI_O_DIR03 0x00000000 // Direct access for adi byte +#define ADI_O_DIR03 0x00000000 // Direct access for adi byte // offsets 0 to 3 -#define ADI_O_DIR47 0x00000004 // Direct access for adi byte +#define ADI_O_DIR47 0x00000004 // Direct access for adi byte // offsets 4 to 7 -#define ADI_O_DIR811 0x00000008 // Direct access for adi byte +#define ADI_O_DIR811 0x00000008 // Direct access for adi byte // offsets 8 to 11 -#define ADI_O_DIR1215 0x0000000C // Direct access for adi byte +#define ADI_O_DIR1215 0x0000000C // Direct access for adi byte // offsets 12 to 15 -#define ADI_O_SET03 0x00000010 // Set register for ADI byte +#define ADI_O_SET03 0x00000010 // Set register for ADI byte // offsets 0 to 3 -#define ADI_O_SET47 0x00000014 // Set register for ADI byte +#define ADI_O_SET47 0x00000014 // Set register for ADI byte // offsets 4 to 7 -#define ADI_O_SET811 0x00000018 // Set register for ADI byte +#define ADI_O_SET811 0x00000018 // Set register for ADI byte // offsets 8 to 11 -#define ADI_O_SET1215 0x0000001C // Set register for ADI byte +#define ADI_O_SET1215 0x0000001C // Set register for ADI byte // offsets 12 to 15 -#define ADI_O_CLR03 0x00000020 // Clear register for ADI byte +#define ADI_O_CLR03 0x00000020 // Clear register for ADI byte // offsets 0 to 3 -#define ADI_O_CLR47 0x00000024 // Clear register for ADI byte +#define ADI_O_CLR47 0x00000024 // Clear register for ADI byte // offsets 4 to 7 -#define ADI_O_CLR811 0x00000028 // Clear register for ADI byte +#define ADI_O_CLR811 0x00000028 // Clear register for ADI byte // offsets 8 to 11 -#define ADI_O_CLR1215 0x0000002C // Clear register for ADI byte +#define ADI_O_CLR1215 0x0000002C // Clear register for ADI byte // offsets 12 to 15 -#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register -#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration +#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register +#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration // register -#define ADI_O_MASK4B01 0x00000040 // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B01 0x00000040 // Masked access (4m/4d) for ADI // Registers at byte offsets 0 and // 1 -#define ADI_O_MASK4B23 0x00000044 // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B23 0x00000044 // Masked access (4m/4d) for ADI // Registers at byte offsets 2 and // 3 -#define ADI_O_MASK4B45 0x00000048 // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B45 0x00000048 // Masked access (4m/4d) for ADI // Registers at byte offsets 4 and // 5 -#define ADI_O_MASK4B67 0x0000004C // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B67 0x0000004C // Masked access (4m/4d) for ADI // Registers at byte offsets 6 and // 7 -#define ADI_O_MASK4B89 0x00000050 // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B89 0x00000050 // Masked access (4m/4d) for ADI // Registers at byte offsets 8 and // 9 -#define ADI_O_MASK4B1011 0x00000054 // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B1011 0x00000054 // Masked access (4m/4d) for ADI // Registers at byte offsets 10 and // 11 -#define ADI_O_MASK4B1213 0x00000058 // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B1213 0x00000058 // Masked access (4m/4d) for ADI // Registers at byte offsets 12 and // 13 -#define ADI_O_MASK4B1415 0x0000005C // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B1415 0x0000005C // Masked access (4m/4d) for ADI // Registers at byte offsets 14 and // 15 -#define ADI_O_MASK8B01 0x00000060 // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B01 0x00000060 // Masked access (8m/8d) for ADI // Registers at byte offsets 0 and // 1 -#define ADI_O_MASK8B23 0x00000064 // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B23 0x00000064 // Masked access (8m/8d) for ADI // Registers at byte offsets 2 and // 3 -#define ADI_O_MASK8B45 0x00000068 // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B45 0x00000068 // Masked access (8m/8d) for ADI // Registers at byte offsets 4 and // 5 -#define ADI_O_MASK8B67 0x0000006C // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B67 0x0000006C // Masked access (8m/8d) for ADI // Registers at byte offsets 6 and // 7 -#define ADI_O_MASK8B89 0x00000070 // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B89 0x00000070 // Masked access (8m/8d) for ADI // Registers at byte offsets 8 and // 9 -#define ADI_O_MASK8B1011 0x00000074 // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B1011 0x00000074 // Masked access (8m/8d) for ADI // Registers at byte offsets 10 and // 11 -#define ADI_O_MASK8B1213 0x00000078 // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B1213 0x00000078 // Masked access (8m/8d) for ADI // Registers at byte offsets 12 and // 13 -#define ADI_O_MASK8B1415 0x0000007C // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B1415 0x0000007C // Masked access (8m/8d) for ADI // Registers at byte offsets 14 and // 15 -#define ADI_O_MASK16B01 0x00000080 // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B01 0x00000080 // Masked access (16m/16d) for ADI // Registers at byte offsets 0 and // 1 -#define ADI_O_MASK16B23 0x00000084 // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B23 0x00000084 // Masked access (16m/16d) for ADI // Registers at byte offsets 2 and // 3 -#define ADI_O_MASK16B45 0x00000088 // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B45 0x00000088 // Masked access (16m/16d) for ADI // Registers at byte offsets 4 and // 5 -#define ADI_O_MASK16B67 0x0000008C // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B67 0x0000008C // Masked access (16m/16d) for ADI // Registers at byte offsets 6 and // 7 -#define ADI_O_MASK16B89 0x00000090 // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B89 0x00000090 // Masked access (16m/16d) for ADI // Registers at byte offsets 8 and // 9 -#define ADI_O_MASK16B1011 0x00000094 // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B1011 0x00000094 // Masked access (16m/16d) for ADI // Registers at byte offsets 10 and // 11 -#define ADI_O_MASK16B1213 0x00000098 // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B1213 0x00000098 // Masked access (16m/16d) for ADI // Registers at byte offsets 12 and // 13 -#define ADI_O_MASK16B1415 0x0000009C // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B1415 0x0000009C // Masked access (16m/16d) for ADI // Registers at byte offsets 14 and // 15 @@ -355,253 +355,253 @@ // The following are defines for the bit fields in the ADI_O_DIR03 register. // //***************************************************************************** -#define ADI_DIR03_B3_M 0xFF000000 // Direct access to ADI register 3 -#define ADI_DIR03_B3_S 24 -#define ADI_DIR03_B2_M 0x00FF0000 // Direct access to ADI register 2 -#define ADI_DIR03_B2_S 16 -#define ADI_DIR03_B1_M 0x0000FF00 // Direct access to ADI register 1 -#define ADI_DIR03_B1_S 8 -#define ADI_DIR03_B0_M 0x000000FF // Direct access to ADI register 0 -#define ADI_DIR03_B0_S 0 +#define ADI_DIR03_B3_M 0xFF000000 // Direct access to ADI register 3 +#define ADI_DIR03_B3_S 24 +#define ADI_DIR03_B2_M 0x00FF0000 // Direct access to ADI register 2 +#define ADI_DIR03_B2_S 16 +#define ADI_DIR03_B1_M 0x0000FF00 // Direct access to ADI register 1 +#define ADI_DIR03_B1_S 8 +#define ADI_DIR03_B0_M 0x000000FF // Direct access to ADI register 0 +#define ADI_DIR03_B0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_DIR47 register. // //***************************************************************************** -#define ADI_DIR47_B3_M 0xFF000000 // Direct access to ADI register 7 -#define ADI_DIR47_B3_S 24 -#define ADI_DIR47_B2_M 0x00FF0000 // Direct access to ADI register 6 -#define ADI_DIR47_B2_S 16 -#define ADI_DIR47_B1_M 0x0000FF00 // Direct access to ADI register 5 -#define ADI_DIR47_B1_S 8 -#define ADI_DIR47_B0_M 0x000000FF // Direct access to ADI register 4 -#define ADI_DIR47_B0_S 0 +#define ADI_DIR47_B3_M 0xFF000000 // Direct access to ADI register 7 +#define ADI_DIR47_B3_S 24 +#define ADI_DIR47_B2_M 0x00FF0000 // Direct access to ADI register 6 +#define ADI_DIR47_B2_S 16 +#define ADI_DIR47_B1_M 0x0000FF00 // Direct access to ADI register 5 +#define ADI_DIR47_B1_S 8 +#define ADI_DIR47_B0_M 0x000000FF // Direct access to ADI register 4 +#define ADI_DIR47_B0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_DIR811 register. // //***************************************************************************** -#define ADI_DIR811_B3_M 0xFF000000 // Direct access to ADI register +#define ADI_DIR811_B3_M 0xFF000000 // Direct access to ADI register // 11 -#define ADI_DIR811_B3_S 24 -#define ADI_DIR811_B2_M 0x00FF0000 // Direct access to ADI register +#define ADI_DIR811_B3_S 24 +#define ADI_DIR811_B2_M 0x00FF0000 // Direct access to ADI register // 10 -#define ADI_DIR811_B2_S 16 -#define ADI_DIR811_B1_M 0x0000FF00 // Direct access to ADI register 9 -#define ADI_DIR811_B1_S 8 -#define ADI_DIR811_B0_M 0x000000FF // Direct access to ADI register 8 -#define ADI_DIR811_B0_S 0 +#define ADI_DIR811_B2_S 16 +#define ADI_DIR811_B1_M 0x0000FF00 // Direct access to ADI register 9 +#define ADI_DIR811_B1_S 8 +#define ADI_DIR811_B0_M 0x000000FF // Direct access to ADI register 8 +#define ADI_DIR811_B0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_DIR1215 register. // //***************************************************************************** -#define ADI_DIR1215_B3_M 0xFF000000 // Direct access to ADI register +#define ADI_DIR1215_B3_M 0xFF000000 // Direct access to ADI register // 15 -#define ADI_DIR1215_B3_S 24 -#define ADI_DIR1215_B2_M 0x00FF0000 // Direct access to ADI register +#define ADI_DIR1215_B3_S 24 +#define ADI_DIR1215_B2_M 0x00FF0000 // Direct access to ADI register // 14 -#define ADI_DIR1215_B2_S 16 -#define ADI_DIR1215_B1_M 0x0000FF00 // Direct access to ADI register +#define ADI_DIR1215_B2_S 16 +#define ADI_DIR1215_B1_M 0x0000FF00 // Direct access to ADI register // 13 -#define ADI_DIR1215_B1_S 8 -#define ADI_DIR1215_B0_M 0x000000FF // Direct access to ADI register +#define ADI_DIR1215_B1_S 8 +#define ADI_DIR1215_B0_M 0x000000FF // Direct access to ADI register // 12 -#define ADI_DIR1215_B0_S 0 +#define ADI_DIR1215_B0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_SET03 register. // //***************************************************************************** -#define ADI_SET03_S3_M 0xFF000000 // A high bit value will set the +#define ADI_SET03_S3_M 0xFF000000 // A high bit value will set the // corresponding bit in ADI // register 3. Read returns 0. -#define ADI_SET03_S3_S 24 -#define ADI_SET03_S2_M 0x00FF0000 // A high bit value will set the +#define ADI_SET03_S3_S 24 +#define ADI_SET03_S2_M 0x00FF0000 // A high bit value will set the // corresponding bit in ADI // register 2. Read returns 0. -#define ADI_SET03_S2_S 16 -#define ADI_SET03_S1_M 0x0000FF00 // A high bit value will set the +#define ADI_SET03_S2_S 16 +#define ADI_SET03_S1_M 0x0000FF00 // A high bit value will set the // corresponding bit in ADI // register 1. Read returns 0. -#define ADI_SET03_S1_S 8 -#define ADI_SET03_S0_M 0x000000FF // A high bit value will set the +#define ADI_SET03_S1_S 8 +#define ADI_SET03_S0_M 0x000000FF // A high bit value will set the // corresponding bit in ADI // register 0. Read returns 0. -#define ADI_SET03_S0_S 0 +#define ADI_SET03_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_SET47 register. // //***************************************************************************** -#define ADI_SET47_S3_M 0xFF000000 // A high bit value will set the +#define ADI_SET47_S3_M 0xFF000000 // A high bit value will set the // corresponding bit in ADI // register 7. Read returns 0. -#define ADI_SET47_S3_S 24 -#define ADI_SET47_S2_M 0x00FF0000 // A high bit value will set the +#define ADI_SET47_S3_S 24 +#define ADI_SET47_S2_M 0x00FF0000 // A high bit value will set the // corresponding bit in ADI // register 6. Read returns 0. -#define ADI_SET47_S2_S 16 -#define ADI_SET47_S1_M 0x0000FF00 // A high bit value will set the +#define ADI_SET47_S2_S 16 +#define ADI_SET47_S1_M 0x0000FF00 // A high bit value will set the // corresponding bit in ADI // register 5. Read returns 0. -#define ADI_SET47_S1_S 8 -#define ADI_SET47_S0_M 0x000000FF // A high bit value will set the +#define ADI_SET47_S1_S 8 +#define ADI_SET47_S0_M 0x000000FF // A high bit value will set the // corresponding bit in ADI // register 4. Read returns 0. -#define ADI_SET47_S0_S 0 +#define ADI_SET47_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_SET811 register. // //***************************************************************************** -#define ADI_SET811_S3_M 0xFF000000 // A high bit value will set the +#define ADI_SET811_S3_M 0xFF000000 // A high bit value will set the // corresponding bit in ADI // register 11. Read returns 0. -#define ADI_SET811_S3_S 24 -#define ADI_SET811_S2_M 0x00FF0000 // A high bit value will set the +#define ADI_SET811_S3_S 24 +#define ADI_SET811_S2_M 0x00FF0000 // A high bit value will set the // corresponding bit in ADI // register 10. Read returns 0. -#define ADI_SET811_S2_S 16 -#define ADI_SET811_S1_M 0x0000FF00 // A high bit value will set the +#define ADI_SET811_S2_S 16 +#define ADI_SET811_S1_M 0x0000FF00 // A high bit value will set the // corresponding bit in ADI // register 9. Read returns 0. -#define ADI_SET811_S1_S 8 -#define ADI_SET811_S0_M 0x000000FF // A high bit value will set the +#define ADI_SET811_S1_S 8 +#define ADI_SET811_S0_M 0x000000FF // A high bit value will set the // corresponding bit in ADI // register 8. Read returns 0. -#define ADI_SET811_S0_S 0 +#define ADI_SET811_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_SET1215 register. // //***************************************************************************** -#define ADI_SET1215_S3_M 0xFF000000 // A high bit value will set the +#define ADI_SET1215_S3_M 0xFF000000 // A high bit value will set the // corresponding bit in ADI // register 15. Read returns 0. -#define ADI_SET1215_S3_S 24 -#define ADI_SET1215_S2_M 0x00FF0000 // A high bit value will set the +#define ADI_SET1215_S3_S 24 +#define ADI_SET1215_S2_M 0x00FF0000 // A high bit value will set the // corresponding bit in ADI // register 14. Read returns 0. -#define ADI_SET1215_S2_S 16 -#define ADI_SET1215_S1_M 0x0000FF00 // A high bit value will set the +#define ADI_SET1215_S2_S 16 +#define ADI_SET1215_S1_M 0x0000FF00 // A high bit value will set the // corresponding bit in ADI // register 13. Read returns 0. -#define ADI_SET1215_S1_S 8 -#define ADI_SET1215_S0_M 0x000000FF // A high bit value will set the +#define ADI_SET1215_S1_S 8 +#define ADI_SET1215_S0_M 0x000000FF // A high bit value will set the // corresponding bit in ADI // register 12. Read returns 0. -#define ADI_SET1215_S0_S 0 +#define ADI_SET1215_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_CLR03 register. // //***************************************************************************** -#define ADI_CLR03_S3_M 0xFF000000 // A high bit value will clear the +#define ADI_CLR03_S3_M 0xFF000000 // A high bit value will clear the // corresponding bit in ADI // register 3 -#define ADI_CLR03_S3_S 24 -#define ADI_CLR03_S2_M 0x00FF0000 // A high bit value will clear the +#define ADI_CLR03_S3_S 24 +#define ADI_CLR03_S2_M 0x00FF0000 // A high bit value will clear the // corresponding bit in ADI // register 2 -#define ADI_CLR03_S2_S 16 -#define ADI_CLR03_S1_M 0x0000FF00 // A high bit value will clear the +#define ADI_CLR03_S2_S 16 +#define ADI_CLR03_S1_M 0x0000FF00 // A high bit value will clear the // corresponding bit in ADI // register 1 -#define ADI_CLR03_S1_S 8 -#define ADI_CLR03_S0_M 0x000000FF // A high bit value will clear the +#define ADI_CLR03_S1_S 8 +#define ADI_CLR03_S0_M 0x000000FF // A high bit value will clear the // corresponding bit in ADI // register 0 -#define ADI_CLR03_S0_S 0 +#define ADI_CLR03_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_CLR47 register. // //***************************************************************************** -#define ADI_CLR47_S3_M 0xFF000000 // A high bit value will clear the +#define ADI_CLR47_S3_M 0xFF000000 // A high bit value will clear the // corresponding bit in ADI // register 7 -#define ADI_CLR47_S3_S 24 -#define ADI_CLR47_S2_M 0x00FF0000 // A high bit value will clear the +#define ADI_CLR47_S3_S 24 +#define ADI_CLR47_S2_M 0x00FF0000 // A high bit value will clear the // corresponding bit in ADI // register 6 -#define ADI_CLR47_S2_S 16 -#define ADI_CLR47_S1_M 0x0000FF00 // A high bit value will clear the +#define ADI_CLR47_S2_S 16 +#define ADI_CLR47_S1_M 0x0000FF00 // A high bit value will clear the // corresponding bit in ADI // register 5 -#define ADI_CLR47_S1_S 8 -#define ADI_CLR47_S0_M 0x000000FF // A high bit value will clear the +#define ADI_CLR47_S1_S 8 +#define ADI_CLR47_S0_M 0x000000FF // A high bit value will clear the // corresponding bit in ADI // register 4 -#define ADI_CLR47_S0_S 0 +#define ADI_CLR47_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_CLR811 register. // //***************************************************************************** -#define ADI_CLR811_S3_M 0xFF000000 // A high bit value will clear the +#define ADI_CLR811_S3_M 0xFF000000 // A high bit value will clear the // corresponding bit in ADI // register 11 -#define ADI_CLR811_S3_S 24 -#define ADI_CLR811_S2_M 0x00FF0000 // A high bit value will clear the +#define ADI_CLR811_S3_S 24 +#define ADI_CLR811_S2_M 0x00FF0000 // A high bit value will clear the // corresponding bit in ADI // register 10 -#define ADI_CLR811_S2_S 16 -#define ADI_CLR811_S1_M 0x0000FF00 // A high bit value will clear the +#define ADI_CLR811_S2_S 16 +#define ADI_CLR811_S1_M 0x0000FF00 // A high bit value will clear the // corresponding bit in ADI // register 9 -#define ADI_CLR811_S1_S 8 -#define ADI_CLR811_S0_M 0x000000FF // A high bit value will clear the +#define ADI_CLR811_S1_S 8 +#define ADI_CLR811_S0_M 0x000000FF // A high bit value will clear the // corresponding bit in ADI // register 8 -#define ADI_CLR811_S0_S 0 +#define ADI_CLR811_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_CLR1215 register. // //***************************************************************************** -#define ADI_CLR1215_S3_M 0xFF000000 // A high bit value will clear the +#define ADI_CLR1215_S3_M 0xFF000000 // A high bit value will clear the // corresponding bit in ADI // register 15 -#define ADI_CLR1215_S3_S 24 -#define ADI_CLR1215_S2_M 0x00FF0000 // A high bit value will clear the +#define ADI_CLR1215_S3_S 24 +#define ADI_CLR1215_S2_M 0x00FF0000 // A high bit value will clear the // corresponding bit in ADI // register 14 -#define ADI_CLR1215_S2_S 16 -#define ADI_CLR1215_S1_M 0x0000FF00 // A high bit value will clear the +#define ADI_CLR1215_S2_S 16 +#define ADI_CLR1215_S1_M 0x0000FF00 // A high bit value will clear the // corresponding bit in ADI // register 13 -#define ADI_CLR1215_S1_S 8 -#define ADI_CLR1215_S0_M 0x000000FF // A high bit value will clear the +#define ADI_CLR1215_S1_S 8 +#define ADI_CLR1215_S0_M 0x000000FF // A high bit value will clear the // corresponding bit in ADI // register 12 -#define ADI_CLR1215_S0_S 0 +#define ADI_CLR1215_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_SLAVESTAT register. // //***************************************************************************** -#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ +#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ // signal. Writing 0 to this bit // forces a sync with slave, // ensuring that req will be 0. It // is recommended to write 0 to // this register before power down // of the master. -#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 -#define ADI_SLAVESTAT_DI_REQ_S 1 -#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK +#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 +#define ADI_SLAVESTAT_DI_REQ_S 1 +#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK // signal -#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 -#define ADI_SLAVESTAT_DI_ACK_S 0 +#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 +#define ADI_SLAVESTAT_DI_ACK_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_SLAVECONF register. // //***************************************************************************** -#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer +#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer // accessible when this bit is set. // (unless sticky_bit_overwrite is // asserted on top module) @@ -609,7 +609,7 @@ 0x00000080 #define ADI_SLAVECONF_CONFLOCK_S 7 #define ADI_SLAVECONF_WAITFORACK \ - 0x00000004 // A transaction on the ADI + 0x00000004 // A transaction on the ADI // interface does not end until ack // has been received from the slave // when this bit is set. @@ -618,7 +618,7 @@ 0x00000004 #define ADI_SLAVECONF_WAITFORACK_S 2 #define ADI_SLAVECONF_ADICLKSPEED_M \ - 0x00000003 // Sets the period of an ADI + 0x00000003 // Sets the period of an ADI // transactions. All transactions // takes an even number of clock // cycles,- ADI clock rising edge @@ -641,542 +641,542 @@ // The following are defines for the bit fields in the ADI_O_MASK4B01 register. // //***************************************************************************** -#define ADI_MASK4B01_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B01_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 1 -#define ADI_MASK4B01_M1H_S 28 -#define ADI_MASK4B01_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B01_M1H_S 28 +#define ADI_MASK4B01_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 1, - only bits selected // by mask M1H will be affected by // access -#define ADI_MASK4B01_D1H_S 24 -#define ADI_MASK4B01_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B01_D1H_S 24 +#define ADI_MASK4B01_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 1 -#define ADI_MASK4B01_M1L_S 20 -#define ADI_MASK4B01_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B01_M1L_S 20 +#define ADI_MASK4B01_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 1, - only bits selected // by mask M1L will be affected by // access -#define ADI_MASK4B01_D1L_S 16 -#define ADI_MASK4B01_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B01_D1L_S 16 +#define ADI_MASK4B01_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 0 -#define ADI_MASK4B01_M0H_S 12 -#define ADI_MASK4B01_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B01_M0H_S 12 +#define ADI_MASK4B01_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 0, - only bits selected // by mask M0H will be affected by // access -#define ADI_MASK4B01_D0H_S 8 -#define ADI_MASK4B01_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B01_D0H_S 8 +#define ADI_MASK4B01_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 0 -#define ADI_MASK4B01_M0L_S 4 -#define ADI_MASK4B01_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B01_M0L_S 4 +#define ADI_MASK4B01_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 0, - only bits selected // by mask M0L will be affected by // access -#define ADI_MASK4B01_D0L_S 0 +#define ADI_MASK4B01_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK4B23 register. // //***************************************************************************** -#define ADI_MASK4B23_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B23_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 3 -#define ADI_MASK4B23_M1H_S 28 -#define ADI_MASK4B23_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B23_M1H_S 28 +#define ADI_MASK4B23_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 3, - only bits selected // by mask M1H will be affected by // access -#define ADI_MASK4B23_D1H_S 24 -#define ADI_MASK4B23_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B23_D1H_S 24 +#define ADI_MASK4B23_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 3 -#define ADI_MASK4B23_M1L_S 20 -#define ADI_MASK4B23_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B23_M1L_S 20 +#define ADI_MASK4B23_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 3, - only bits selected // by mask M1L will be affected by // access -#define ADI_MASK4B23_D1L_S 16 -#define ADI_MASK4B23_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B23_D1L_S 16 +#define ADI_MASK4B23_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 2 -#define ADI_MASK4B23_M0H_S 12 -#define ADI_MASK4B23_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B23_M0H_S 12 +#define ADI_MASK4B23_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 2, - only bits selected // by mask M0H will be affected by // access -#define ADI_MASK4B23_D0H_S 8 -#define ADI_MASK4B23_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B23_D0H_S 8 +#define ADI_MASK4B23_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 2 -#define ADI_MASK4B23_M0L_S 4 -#define ADI_MASK4B23_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B23_M0L_S 4 +#define ADI_MASK4B23_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 2, - only bits selected // by mask M0L will be affected by // access -#define ADI_MASK4B23_D0L_S 0 +#define ADI_MASK4B23_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK4B45 register. // //***************************************************************************** -#define ADI_MASK4B45_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B45_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 5 -#define ADI_MASK4B45_M1H_S 28 -#define ADI_MASK4B45_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B45_M1H_S 28 +#define ADI_MASK4B45_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 5, - only bits selected // by mask M1H will be affected by // access -#define ADI_MASK4B45_D1H_S 24 -#define ADI_MASK4B45_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B45_D1H_S 24 +#define ADI_MASK4B45_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 5 -#define ADI_MASK4B45_M1L_S 20 -#define ADI_MASK4B45_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B45_M1L_S 20 +#define ADI_MASK4B45_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 5, - only bits selected // by mask M1L will be affected by // access -#define ADI_MASK4B45_D1L_S 16 -#define ADI_MASK4B45_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B45_D1L_S 16 +#define ADI_MASK4B45_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 4 -#define ADI_MASK4B45_M0H_S 12 -#define ADI_MASK4B45_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B45_M0H_S 12 +#define ADI_MASK4B45_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 4, - only bits selected // by mask M0H will be affected by // access -#define ADI_MASK4B45_D0H_S 8 -#define ADI_MASK4B45_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B45_D0H_S 8 +#define ADI_MASK4B45_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 4 -#define ADI_MASK4B45_M0L_S 4 -#define ADI_MASK4B45_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B45_M0L_S 4 +#define ADI_MASK4B45_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 4, - only bits selected // by mask M0L will be affected by // access -#define ADI_MASK4B45_D0L_S 0 +#define ADI_MASK4B45_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK4B67 register. // //***************************************************************************** -#define ADI_MASK4B67_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B67_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 7 -#define ADI_MASK4B67_M1H_S 28 -#define ADI_MASK4B67_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B67_M1H_S 28 +#define ADI_MASK4B67_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 7, - only bits selected // by mask M1H will be affected by // access -#define ADI_MASK4B67_D1H_S 24 -#define ADI_MASK4B67_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B67_D1H_S 24 +#define ADI_MASK4B67_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 7 -#define ADI_MASK4B67_M1L_S 20 -#define ADI_MASK4B67_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B67_M1L_S 20 +#define ADI_MASK4B67_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 7, - only bits selected // by mask M1L will be affected by // access -#define ADI_MASK4B67_D1L_S 16 -#define ADI_MASK4B67_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B67_D1L_S 16 +#define ADI_MASK4B67_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 6 -#define ADI_MASK4B67_M0H_S 12 -#define ADI_MASK4B67_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B67_M0H_S 12 +#define ADI_MASK4B67_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 6, - only bits selected // by mask M0H will be affected by // access -#define ADI_MASK4B67_D0H_S 8 -#define ADI_MASK4B67_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B67_D0H_S 8 +#define ADI_MASK4B67_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 6 -#define ADI_MASK4B67_M0L_S 4 -#define ADI_MASK4B67_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B67_M0L_S 4 +#define ADI_MASK4B67_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 6, - only bits selected // by mask M0L will be affected by // access -#define ADI_MASK4B67_D0L_S 0 +#define ADI_MASK4B67_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK4B89 register. // //***************************************************************************** -#define ADI_MASK4B89_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B89_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 9 -#define ADI_MASK4B89_M1H_S 28 -#define ADI_MASK4B89_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B89_M1H_S 28 +#define ADI_MASK4B89_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 9, - only bits selected // by mask M1H will be affected by // access -#define ADI_MASK4B89_D1H_S 24 -#define ADI_MASK4B89_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B89_D1H_S 24 +#define ADI_MASK4B89_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 9 -#define ADI_MASK4B89_M1L_S 20 -#define ADI_MASK4B89_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B89_M1L_S 20 +#define ADI_MASK4B89_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 9, - only bits selected // by mask M1L will be affected by // access -#define ADI_MASK4B89_D1L_S 16 -#define ADI_MASK4B89_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B89_D1L_S 16 +#define ADI_MASK4B89_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 8 -#define ADI_MASK4B89_M0H_S 12 -#define ADI_MASK4B89_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B89_M0H_S 12 +#define ADI_MASK4B89_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 8, - only bits selected // by mask M0H will be affected by // access -#define ADI_MASK4B89_D0H_S 8 -#define ADI_MASK4B89_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B89_D0H_S 8 +#define ADI_MASK4B89_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 8 -#define ADI_MASK4B89_M0L_S 4 -#define ADI_MASK4B89_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B89_M0L_S 4 +#define ADI_MASK4B89_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 8, - only bits selected // by mask M0L will be affected by // access -#define ADI_MASK4B89_D0L_S 0 +#define ADI_MASK4B89_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK4B1011 register. // //***************************************************************************** -#define ADI_MASK4B1011_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B1011_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 11 -#define ADI_MASK4B1011_M1H_S 28 -#define ADI_MASK4B1011_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B1011_M1H_S 28 +#define ADI_MASK4B1011_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 11, - only bits // selected by mask M1H will be // affected by access -#define ADI_MASK4B1011_D1H_S 24 -#define ADI_MASK4B1011_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B1011_D1H_S 24 +#define ADI_MASK4B1011_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 11 -#define ADI_MASK4B1011_M1L_S 20 -#define ADI_MASK4B1011_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B1011_M1L_S 20 +#define ADI_MASK4B1011_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 11, - only bits // selected by mask M1L will be // affected by access -#define ADI_MASK4B1011_D1L_S 16 -#define ADI_MASK4B1011_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B1011_D1L_S 16 +#define ADI_MASK4B1011_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 10 -#define ADI_MASK4B1011_M0H_S 12 -#define ADI_MASK4B1011_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B1011_M0H_S 12 +#define ADI_MASK4B1011_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 10, - only bits // selected by mask M0H will be // affected by access -#define ADI_MASK4B1011_D0H_S 8 -#define ADI_MASK4B1011_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B1011_D0H_S 8 +#define ADI_MASK4B1011_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 10 -#define ADI_MASK4B1011_M0L_S 4 -#define ADI_MASK4B1011_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B1011_M0L_S 4 +#define ADI_MASK4B1011_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 10, - only bits // selected by mask M0L will be // affected by access -#define ADI_MASK4B1011_D0L_S 0 +#define ADI_MASK4B1011_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK4B1213 register. // //***************************************************************************** -#define ADI_MASK4B1213_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B1213_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 13 -#define ADI_MASK4B1213_M1H_S 28 -#define ADI_MASK4B1213_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B1213_M1H_S 28 +#define ADI_MASK4B1213_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 13, - only bits // selected by mask M1H will be // affected by access -#define ADI_MASK4B1213_D1H_S 24 -#define ADI_MASK4B1213_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B1213_D1H_S 24 +#define ADI_MASK4B1213_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 13 -#define ADI_MASK4B1213_M1L_S 20 -#define ADI_MASK4B1213_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B1213_M1L_S 20 +#define ADI_MASK4B1213_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 13, - only bits // selected by mask M1L will be // affected by access -#define ADI_MASK4B1213_D1L_S 16 -#define ADI_MASK4B1213_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B1213_D1L_S 16 +#define ADI_MASK4B1213_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 12 -#define ADI_MASK4B1213_M0H_S 12 -#define ADI_MASK4B1213_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B1213_M0H_S 12 +#define ADI_MASK4B1213_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 12, - only bits // selected by mask M0H will be // affected by access -#define ADI_MASK4B1213_D0H_S 8 -#define ADI_MASK4B1213_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B1213_D0H_S 8 +#define ADI_MASK4B1213_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 12 -#define ADI_MASK4B1213_M0L_S 4 -#define ADI_MASK4B1213_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B1213_M0L_S 4 +#define ADI_MASK4B1213_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 12, - only bits // selected by mask M0L will be // affected by access -#define ADI_MASK4B1213_D0L_S 0 +#define ADI_MASK4B1213_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK4B1415 register. // //***************************************************************************** -#define ADI_MASK4B1415_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B1415_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 15 -#define ADI_MASK4B1415_M1H_S 28 -#define ADI_MASK4B1415_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B1415_M1H_S 28 +#define ADI_MASK4B1415_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 15, - only bits // selected by mask M1H will be // affected by access -#define ADI_MASK4B1415_D1H_S 24 -#define ADI_MASK4B1415_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B1415_D1H_S 24 +#define ADI_MASK4B1415_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 15 -#define ADI_MASK4B1415_M1L_S 20 -#define ADI_MASK4B1415_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B1415_M1L_S 20 +#define ADI_MASK4B1415_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 15, - only bits // selected by mask M1L will be // affected by access -#define ADI_MASK4B1415_D1L_S 16 -#define ADI_MASK4B1415_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B1415_D1L_S 16 +#define ADI_MASK4B1415_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 14 -#define ADI_MASK4B1415_M0H_S 12 -#define ADI_MASK4B1415_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B1415_M0H_S 12 +#define ADI_MASK4B1415_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 14, - only bits // selected by mask M0H will be // affected by access -#define ADI_MASK4B1415_D0H_S 8 -#define ADI_MASK4B1415_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B1415_D0H_S 8 +#define ADI_MASK4B1415_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 14 -#define ADI_MASK4B1415_M0L_S 4 -#define ADI_MASK4B1415_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B1415_M0L_S 4 +#define ADI_MASK4B1415_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 14, - only bits // selected by mask M0L will be // affected by access -#define ADI_MASK4B1415_D0L_S 0 +#define ADI_MASK4B1415_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK8B01 register. // //***************************************************************************** -#define ADI_MASK8B01_M1_M 0xFF000000 // Mask for ADI register 1 -#define ADI_MASK8B01_M1_S 24 -#define ADI_MASK8B01_D1_M 0x00FF0000 // Data for ADI register 1, - only +#define ADI_MASK8B01_M1_M 0xFF000000 // Mask for ADI register 1 +#define ADI_MASK8B01_M1_S 24 +#define ADI_MASK8B01_D1_M 0x00FF0000 // Data for ADI register 1, - only // bits selected by mask M1 will be // affected by access -#define ADI_MASK8B01_D1_S 16 -#define ADI_MASK8B01_M0_M 0x0000FF00 // Mask for ADI register 0 -#define ADI_MASK8B01_M0_S 8 -#define ADI_MASK8B01_D0_M 0x000000FF // Data for ADI register 0, - only +#define ADI_MASK8B01_D1_S 16 +#define ADI_MASK8B01_M0_M 0x0000FF00 // Mask for ADI register 0 +#define ADI_MASK8B01_M0_S 8 +#define ADI_MASK8B01_D0_M 0x000000FF // Data for ADI register 0, - only // bits selected by mask M0 will be // affected by access -#define ADI_MASK8B01_D0_S 0 +#define ADI_MASK8B01_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK8B23 register. // //***************************************************************************** -#define ADI_MASK8B23_M1_M 0xFF000000 // Mask for ADI register 3 -#define ADI_MASK8B23_M1_S 24 -#define ADI_MASK8B23_D1_M 0x00FF0000 // Data for ADI register 3, - only +#define ADI_MASK8B23_M1_M 0xFF000000 // Mask for ADI register 3 +#define ADI_MASK8B23_M1_S 24 +#define ADI_MASK8B23_D1_M 0x00FF0000 // Data for ADI register 3, - only // bits selected by mask M1 will be // affected by access -#define ADI_MASK8B23_D1_S 16 -#define ADI_MASK8B23_M0_M 0x0000FF00 // Mask for ADI register 2 -#define ADI_MASK8B23_M0_S 8 -#define ADI_MASK8B23_D0_M 0x000000FF // Data for ADI register 2, - only +#define ADI_MASK8B23_D1_S 16 +#define ADI_MASK8B23_M0_M 0x0000FF00 // Mask for ADI register 2 +#define ADI_MASK8B23_M0_S 8 +#define ADI_MASK8B23_D0_M 0x000000FF // Data for ADI register 2, - only // bits selected by mask M0 will be // affected by access -#define ADI_MASK8B23_D0_S 0 +#define ADI_MASK8B23_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK8B45 register. // //***************************************************************************** -#define ADI_MASK8B45_M1_M 0xFF000000 // Mask for ADI register 5 -#define ADI_MASK8B45_M1_S 24 -#define ADI_MASK8B45_D1_M 0x00FF0000 // Data for ADI register 5, - only +#define ADI_MASK8B45_M1_M 0xFF000000 // Mask for ADI register 5 +#define ADI_MASK8B45_M1_S 24 +#define ADI_MASK8B45_D1_M 0x00FF0000 // Data for ADI register 5, - only // bits selected by mask M1 will be // affected by access -#define ADI_MASK8B45_D1_S 16 -#define ADI_MASK8B45_M0_M 0x0000FF00 // Mask for ADI register 4 -#define ADI_MASK8B45_M0_S 8 -#define ADI_MASK8B45_D0_M 0x000000FF // Data for ADI register 4, - only +#define ADI_MASK8B45_D1_S 16 +#define ADI_MASK8B45_M0_M 0x0000FF00 // Mask for ADI register 4 +#define ADI_MASK8B45_M0_S 8 +#define ADI_MASK8B45_D0_M 0x000000FF // Data for ADI register 4, - only // bits selected by mask M0 will be // affected by access -#define ADI_MASK8B45_D0_S 0 +#define ADI_MASK8B45_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK8B67 register. // //***************************************************************************** -#define ADI_MASK8B67_M1_M 0xFF000000 // Mask for ADI register 7 -#define ADI_MASK8B67_M1_S 24 -#define ADI_MASK8B67_D1_M 0x00FF0000 // Data for ADI register 7, - only +#define ADI_MASK8B67_M1_M 0xFF000000 // Mask for ADI register 7 +#define ADI_MASK8B67_M1_S 24 +#define ADI_MASK8B67_D1_M 0x00FF0000 // Data for ADI register 7, - only // bits selected by mask M1 will be // affected by access -#define ADI_MASK8B67_D1_S 16 -#define ADI_MASK8B67_M0_M 0x0000FF00 // Mask for ADI register 6 -#define ADI_MASK8B67_M0_S 8 -#define ADI_MASK8B67_D0_M 0x000000FF // Data for ADI register 6, - only +#define ADI_MASK8B67_D1_S 16 +#define ADI_MASK8B67_M0_M 0x0000FF00 // Mask for ADI register 6 +#define ADI_MASK8B67_M0_S 8 +#define ADI_MASK8B67_D0_M 0x000000FF // Data for ADI register 6, - only // bits selected by mask M0 will be // affected by access -#define ADI_MASK8B67_D0_S 0 +#define ADI_MASK8B67_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK8B89 register. // //***************************************************************************** -#define ADI_MASK8B89_M1_M 0xFF000000 // Mask for ADI register 9 -#define ADI_MASK8B89_M1_S 24 -#define ADI_MASK8B89_D1_M 0x00FF0000 // Data for ADI register 9, - only +#define ADI_MASK8B89_M1_M 0xFF000000 // Mask for ADI register 9 +#define ADI_MASK8B89_M1_S 24 +#define ADI_MASK8B89_D1_M 0x00FF0000 // Data for ADI register 9, - only // bits selected by mask M1 will be // affected by access -#define ADI_MASK8B89_D1_S 16 -#define ADI_MASK8B89_M0_M 0x0000FF00 // Mask for ADI register 8 -#define ADI_MASK8B89_M0_S 8 -#define ADI_MASK8B89_D0_M 0x000000FF // Data for ADI register 8, - only +#define ADI_MASK8B89_D1_S 16 +#define ADI_MASK8B89_M0_M 0x0000FF00 // Mask for ADI register 8 +#define ADI_MASK8B89_M0_S 8 +#define ADI_MASK8B89_D0_M 0x000000FF // Data for ADI register 8, - only // bits selected by mask M0 will be // affected by access -#define ADI_MASK8B89_D0_S 0 +#define ADI_MASK8B89_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK8B1011 register. // //***************************************************************************** -#define ADI_MASK8B1011_M1_M 0xFF000000 // Mask for ADI register 11 -#define ADI_MASK8B1011_M1_S 24 -#define ADI_MASK8B1011_D1_M 0x00FF0000 // Data for ADI register 11, - +#define ADI_MASK8B1011_M1_M 0xFF000000 // Mask for ADI register 11 +#define ADI_MASK8B1011_M1_S 24 +#define ADI_MASK8B1011_D1_M 0x00FF0000 // Data for ADI register 11, - // only bits selected by mask M1 // will be affected by access -#define ADI_MASK8B1011_D1_S 16 -#define ADI_MASK8B1011_M0_M 0x0000FF00 // Mask for ADI register 10 -#define ADI_MASK8B1011_M0_S 8 -#define ADI_MASK8B1011_D0_M 0x000000FF // Data for ADI register 10, - +#define ADI_MASK8B1011_D1_S 16 +#define ADI_MASK8B1011_M0_M 0x0000FF00 // Mask for ADI register 10 +#define ADI_MASK8B1011_M0_S 8 +#define ADI_MASK8B1011_D0_M 0x000000FF // Data for ADI register 10, - // only bits selected by mask M0 // will be affected by access -#define ADI_MASK8B1011_D0_S 0 +#define ADI_MASK8B1011_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK8B1213 register. // //***************************************************************************** -#define ADI_MASK8B1213_M1_M 0xFF000000 // Mask for ADI register 13 -#define ADI_MASK8B1213_M1_S 24 -#define ADI_MASK8B1213_D1_M 0x00FF0000 // Data for ADI register 13, - +#define ADI_MASK8B1213_M1_M 0xFF000000 // Mask for ADI register 13 +#define ADI_MASK8B1213_M1_S 24 +#define ADI_MASK8B1213_D1_M 0x00FF0000 // Data for ADI register 13, - // only bits selected by mask M1 // will be affected by access -#define ADI_MASK8B1213_D1_S 16 -#define ADI_MASK8B1213_M0_M 0x0000FF00 // Mask for ADI register 12 -#define ADI_MASK8B1213_M0_S 8 -#define ADI_MASK8B1213_D0_M 0x000000FF // Data for ADI register 12, - +#define ADI_MASK8B1213_D1_S 16 +#define ADI_MASK8B1213_M0_M 0x0000FF00 // Mask for ADI register 12 +#define ADI_MASK8B1213_M0_S 8 +#define ADI_MASK8B1213_D0_M 0x000000FF // Data for ADI register 12, - // only bits selected by mask M0 // will be affected by access -#define ADI_MASK8B1213_D0_S 0 +#define ADI_MASK8B1213_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK8B1415 register. // //***************************************************************************** -#define ADI_MASK8B1415_M1_M 0xFF000000 // Mask for ADI register 15 -#define ADI_MASK8B1415_M1_S 24 -#define ADI_MASK8B1415_D1_M 0x00FF0000 // Data for ADI register 15, - +#define ADI_MASK8B1415_M1_M 0xFF000000 // Mask for ADI register 15 +#define ADI_MASK8B1415_M1_S 24 +#define ADI_MASK8B1415_D1_M 0x00FF0000 // Data for ADI register 15, - // only bits selected by mask M1 // will be affected by access -#define ADI_MASK8B1415_D1_S 16 -#define ADI_MASK8B1415_M0_M 0x0000FF00 // Mask for ADI register 14 -#define ADI_MASK8B1415_M0_S 8 -#define ADI_MASK8B1415_D0_M 0x000000FF // Data for ADI register 14, - +#define ADI_MASK8B1415_D1_S 16 +#define ADI_MASK8B1415_M0_M 0x0000FF00 // Mask for ADI register 14 +#define ADI_MASK8B1415_M0_S 8 +#define ADI_MASK8B1415_D0_M 0x000000FF // Data for ADI register 14, - // only bits selected by mask M0 // will be affected by access -#define ADI_MASK8B1415_D0_S 0 +#define ADI_MASK8B1415_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B01 register. // //***************************************************************************** -#define ADI_MASK16B01_M_M 0xFFFF0000 // Mask for ADI register 0 and 1 -#define ADI_MASK16B01_M_S 16 -#define ADI_MASK16B01_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B01_M_M 0xFFFF0000 // Mask for ADI register 0 and 1 +#define ADI_MASK16B01_M_S 16 +#define ADI_MASK16B01_D_M 0x0000FFFF // Data for ADI register at // offsets 0 and 1, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B01_D_S 0 +#define ADI_MASK16B01_D_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B23 register. // //***************************************************************************** -#define ADI_MASK16B23_M_M 0xFFFF0000 // Mask for ADI register 2 and 3 -#define ADI_MASK16B23_M_S 16 -#define ADI_MASK16B23_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B23_M_M 0xFFFF0000 // Mask for ADI register 2 and 3 +#define ADI_MASK16B23_M_S 16 +#define ADI_MASK16B23_D_M 0x0000FFFF // Data for ADI register at // offsets 2 and 3, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B23_D_S 0 +#define ADI_MASK16B23_D_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B45 register. // //***************************************************************************** -#define ADI_MASK16B45_M_M 0xFFFF0000 // Mask for ADI register 4 and 5 -#define ADI_MASK16B45_M_S 16 -#define ADI_MASK16B45_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B45_M_M 0xFFFF0000 // Mask for ADI register 4 and 5 +#define ADI_MASK16B45_M_S 16 +#define ADI_MASK16B45_D_M 0x0000FFFF // Data for ADI register at // offsets 4 and 5, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B45_D_S 0 +#define ADI_MASK16B45_D_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B67 register. // //***************************************************************************** -#define ADI_MASK16B67_M_M 0xFFFF0000 // Mask for ADI register 6 and 7 -#define ADI_MASK16B67_M_S 16 -#define ADI_MASK16B67_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B67_M_M 0xFFFF0000 // Mask for ADI register 6 and 7 +#define ADI_MASK16B67_M_S 16 +#define ADI_MASK16B67_D_M 0x0000FFFF // Data for ADI register at // offsets 6 and 7, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B67_D_S 0 +#define ADI_MASK16B67_D_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B89 register. // //***************************************************************************** -#define ADI_MASK16B89_M_M 0xFFFF0000 // Mask for ADI register 8 and 9 -#define ADI_MASK16B89_M_S 16 -#define ADI_MASK16B89_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B89_M_M 0xFFFF0000 // Mask for ADI register 8 and 9 +#define ADI_MASK16B89_M_S 16 +#define ADI_MASK16B89_D_M 0x0000FFFF // Data for ADI register at // offsets 8 and 9, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B89_D_S 0 +#define ADI_MASK16B89_D_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B1011 register. // //***************************************************************************** -#define ADI_MASK16B1011_M_M 0xFFFF0000 // Mask for ADI register 10 and 11 -#define ADI_MASK16B1011_M_S 16 -#define ADI_MASK16B1011_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B1011_M_M 0xFFFF0000 // Mask for ADI register 10 and 11 +#define ADI_MASK16B1011_M_S 16 +#define ADI_MASK16B1011_D_M 0x0000FFFF // Data for ADI register at // offsets 10 and 11, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B1011_D_S 0 +#define ADI_MASK16B1011_D_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B1213 register. // //***************************************************************************** -#define ADI_MASK16B1213_M_M 0xFFFF0000 // Mask for ADI register 12 and 13 -#define ADI_MASK16B1213_M_S 16 -#define ADI_MASK16B1213_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B1213_M_M 0xFFFF0000 // Mask for ADI register 12 and 13 +#define ADI_MASK16B1213_M_S 16 +#define ADI_MASK16B1213_D_M 0x0000FFFF // Data for ADI register at // offsets 12 and 13, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B1213_D_S 0 +#define ADI_MASK16B1213_D_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B1415 register. // //***************************************************************************** -#define ADI_MASK16B1415_M_M 0xFFFF0000 // Mask for ADI register 14 and 15 -#define ADI_MASK16B1415_M_S 16 -#define ADI_MASK16B1415_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B1415_M_M 0xFFFF0000 // Mask for ADI register 14 and 15 +#define ADI_MASK16B1415_M_S 16 +#define ADI_MASK16B1415_D_M 0x0000FFFF // Data for ADI register at // offsets 14 and 15, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B1415_D_S 0 +#define ADI_MASK16B1415_D_S 0 #endif // __HW_ADI_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_2_refsys.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_2_refsys.h index 069c3d5..41add34 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_2_refsys.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_2_refsys.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_adi_2_refsys_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_adi_2_refsys_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_ADI_2_REFSYS_H__ #define __HW_ADI_2_REFSYS_H__ @@ -44,34 +44,34 @@ // //***************************************************************************** // Internal -#define ADI_2_REFSYS_O_REFSYSCTL0 0x00000000 +#define ADI_2_REFSYS_O_REFSYSCTL0 0x00000000 // Internal -#define ADI_2_REFSYS_O_SOCLDOCTL0 0x00000002 +#define ADI_2_REFSYS_O_SOCLDOCTL0 0x00000002 // Internal -#define ADI_2_REFSYS_O_SOCLDOCTL1 0x00000003 +#define ADI_2_REFSYS_O_SOCLDOCTL1 0x00000003 // Internal -#define ADI_2_REFSYS_O_SOCLDOCTL2 0x00000004 +#define ADI_2_REFSYS_O_SOCLDOCTL2 0x00000004 // Internal -#define ADI_2_REFSYS_O_SOCLDOCTL3 0x00000005 +#define ADI_2_REFSYS_O_SOCLDOCTL3 0x00000005 // Internal -#define ADI_2_REFSYS_O_SOCLDOCTL4 0x00000006 +#define ADI_2_REFSYS_O_SOCLDOCTL4 0x00000006 // Internal -#define ADI_2_REFSYS_O_SOCLDOCTL5 0x00000007 +#define ADI_2_REFSYS_O_SOCLDOCTL5 0x00000007 // Internal -#define ADI_2_REFSYS_O_HPOSCCTL0 0x0000000A +#define ADI_2_REFSYS_O_HPOSCCTL0 0x0000000A // Internal -#define ADI_2_REFSYS_O_HPOSCCTL1 0x0000000B +#define ADI_2_REFSYS_O_HPOSCCTL1 0x0000000B // Internal -#define ADI_2_REFSYS_O_HPOSCCTL2 0x0000000C +#define ADI_2_REFSYS_O_HPOSCCTL2 0x0000000C //***************************************************************************** // @@ -81,9 +81,9 @@ // Field: [4:0] TRIM_IREF // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_W 5 -#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_M 0x0000001F -#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_S 0 +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_W 5 +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_M 0x0000001F +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_S 0 //***************************************************************************** // @@ -93,16 +93,16 @@ // Field: [7:4] VTRIM_UDIG // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_W 4 -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_M 0x000000F0 -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_S 4 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_W 4 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_M 0x000000F0 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_S 4 // Field: [3:0] VTRIM_BOD // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_W 4 -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_M 0x0000000F -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_S 0 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_W 4 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_M 0x0000000F +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_S 0 //***************************************************************************** // @@ -112,16 +112,16 @@ // Field: [7:4] VTRIM_COARSE // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_W 4 -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_M 0x000000F0 -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_S 4 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_W 4 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_M 0x000000F0 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_S 4 // Field: [3:0] VTRIM_DIG // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_W 4 -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_M 0x0000000F -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_S 0 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_W 4 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_M 0x0000000F +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_S 0 //***************************************************************************** // @@ -131,9 +131,9 @@ // Field: [2:0] VTRIM_DELTA // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_W 3 -#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_M 0x00000007 -#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_S 0 +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_W 3 +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_S 0 //***************************************************************************** // @@ -143,9 +143,9 @@ // Field: [7:6] ITRIM_DIGLDO_LOAD // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_W 2 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_M 0x000000C0 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_S 6 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_W 2 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_M 0x000000C0 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_S 6 // Field: [5:3] ITRIM_DIGLDO // @@ -155,20 +155,20 @@ // BIAS_100P Internal. Only to be used through TI provided API. // BIAS_80P Internal. Only to be used through TI provided API. // BIAS_60P Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_W 3 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_M 0x00000038 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_S 3 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_120P 0x00000038 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_100P 0x00000028 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_80P 0x00000018 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_60P 0x00000000 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_W 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_M 0x00000038 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_S 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_120P 0x00000038 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_100P 0x00000028 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_80P 0x00000018 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_60P 0x00000000 // Field: [2:0] ITRIM_UDIGLDO // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_W 3 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_M 0x00000007 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_S 0 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_W 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_S 0 //***************************************************************************** // @@ -178,23 +178,23 @@ // Field: [6:5] UDIG_ITEST_EN // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_W 2 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_M 0x00000060 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_S 5 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_W 2 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_M 0x00000060 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_S 5 // Field: [4:2] DIG_ITEST_EN // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_W 3 -#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_M 0x0000001C -#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_S 2 +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_W 3 +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_M 0x0000001C +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_S 2 // Field: [1] BIAS_DIS // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS 0x00000002 -#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_M 0x00000002 -#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_S 1 +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_M 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_S 1 // Field: [0] UDIG_LDO_EN // @@ -202,11 +202,11 @@ // ENUMs: // EN Internal. Only to be used through TI provided API. // DIS Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN 0x00000001 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_M 0x00000001 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_S 0 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_EN 0x00000001 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_DIS 0x00000000 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_M 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_S 0 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_EN 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_DIS 0x00000000 //***************************************************************************** // @@ -216,9 +216,9 @@ // Field: [3] IMON_ITEST_EN // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN 0x00000008 -#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_M 0x00000008 -#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_S 3 +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN 0x00000008 +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_M 0x00000008 +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_S 3 // Field: [2:0] TESTSEL // @@ -228,13 +228,13 @@ // VREF_AMP Internal. Only to be used through TI provided API. // ITEST Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_W 3 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_M 0x00000007 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_S 0 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VDD_AON 0x00000004 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VREF_AMP 0x00000002 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_ITEST 0x00000001 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_NC 0x00000000 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_W 3 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_S 0 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VDD_AON 0x00000004 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VREF_AMP 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_ITEST 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_NC 0x00000000 //***************************************************************************** // @@ -244,9 +244,9 @@ // Field: [7] FILTER_EN // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN 0x00000080 -#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M 0x00000080 -#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S 7 +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S 7 // Field: [6:5] BIAS_RECHARGE_DLY // @@ -256,13 +256,13 @@ // MIN_DLY_X4 Internal. Only to be used through TI provided API. // MIN_DLY_X2 Internal. Only to be used through TI provided API. // MIN_DLY_X1 Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_W 2 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M 0x00000060 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S 5 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X8 0x00000060 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X4 0x00000040 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X2 0x00000020 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X1 0x00000000 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M 0x00000060 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S 5 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X8 0x00000060 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X4 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X2 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X1 0x00000000 // Field: [4:3] TUNE_CAP // @@ -272,20 +272,20 @@ // SHIFT_M70 Internal. Only to be used through TI provided API. // SHIFT_M35 Internal. Only to be used through TI provided API. // SHIFT_0 Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_W 2 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_M 0x00000018 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_S 3 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M108 0x00000018 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M70 0x00000010 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M35 0x00000008 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_0 0x00000000 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_M 0x00000018 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_S 3 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M108 0x00000018 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M70 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M35 0x00000008 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_0 0x00000000 // Field: [2:1] SERIES_CAP // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_W 2 -#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M 0x00000006 -#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S 1 +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M 0x00000006 +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S 1 // Field: [0] DIV3_BYPASS // @@ -293,11 +293,11 @@ // ENUMs: // HPOSC_2520MHZ Internal. Only to be used through TI provided API. // HPOSC_840MHZ Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS 0x00000001 -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M 0x00000001 -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S 0 -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_2520MHZ 0x00000001 -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_840MHZ 0x00000000 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S 0 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_2520MHZ 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_840MHZ 0x00000000 //***************************************************************************** // @@ -307,23 +307,23 @@ // Field: [5] BIAS_DIS // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS 0x00000020 -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_M 0x00000020 -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_S 5 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_M 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_S 5 // Field: [4] PWRDET_EN // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN 0x00000010 -#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_M 0x00000010 -#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_S 4 +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_M 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_S 4 // Field: [3:0] BIAS_RES_SET // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_W 4 -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M 0x0000000F -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S 0 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_W 4 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M 0x0000000F +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S 0 //***************************************************************************** // @@ -333,30 +333,29 @@ // Field: [7] BIAS_HOLD_MODE_EN // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN 0x00000080 -#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M 0x00000080 -#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S 7 +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S 7 // Field: [6] TESTMUX_EN // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN 0x00000040 -#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_M 0x00000040 -#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_S 6 +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_M 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_S 6 // Field: [5:4] ATEST_SEL // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_W 2 -#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_M 0x00000030 -#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_S 4 +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_W 2 +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_M 0x00000030 +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_S 4 // Field: [3:0] CURRMIRR_RATIO // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_W 4 -#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M 0x0000000F -#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S 0 - +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_W 4 +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M 0x0000000F +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S 0 #endif // __ADI_2_REFSYS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_3_refsys.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_3_refsys.h index b42dac8..4b9d23b 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_3_refsys.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_3_refsys.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_adi_3_refsys_h -* Revised: 2018-09-27 10:33:21 +0200 (Thu, 27 Sep 2018) -* Revision: 52772 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_adi_3_refsys_h + * Revised: 2018-09-27 10:33:21 +0200 (Thu, 27 Sep 2018) + * Revision: 52772 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_ADI_3_REFSYS_H__ #define __HW_ADI_3_REFSYS_H__ @@ -44,46 +44,46 @@ // //***************************************************************************** // Internal -#define ADI_3_REFSYS_O_ATESTCTL1 0x00000001 +#define ADI_3_REFSYS_O_ATESTCTL1 0x00000001 // Internal -#define ADI_3_REFSYS_O_REFSYSCTL0 0x00000002 +#define ADI_3_REFSYS_O_REFSYSCTL0 0x00000002 // Internal -#define ADI_3_REFSYS_O_REFSYSCTL1 0x00000003 +#define ADI_3_REFSYS_O_REFSYSCTL1 0x00000003 // Internal -#define ADI_3_REFSYS_O_REFSYSCTL2 0x00000004 +#define ADI_3_REFSYS_O_REFSYSCTL2 0x00000004 // Internal -#define ADI_3_REFSYS_O_REFSYSCTL3 0x00000005 +#define ADI_3_REFSYS_O_REFSYSCTL3 0x00000005 // DCDC Control 0 -#define ADI_3_REFSYS_O_DCDCCTL0 0x00000006 +#define ADI_3_REFSYS_O_DCDCCTL0 0x00000006 // DCDC Control 1 -#define ADI_3_REFSYS_O_DCDCCTL1 0x00000007 +#define ADI_3_REFSYS_O_DCDCCTL1 0x00000007 // DCDC Control 2 -#define ADI_3_REFSYS_O_DCDCCTL2 0x00000008 +#define ADI_3_REFSYS_O_DCDCCTL2 0x00000008 // Internal -#define ADI_3_REFSYS_O_DCDCCTL3 0x00000009 +#define ADI_3_REFSYS_O_DCDCCTL3 0x00000009 // Internal -#define ADI_3_REFSYS_O_DCDCCTL4 0x0000000A +#define ADI_3_REFSYS_O_DCDCCTL4 0x0000000A // Internal -#define ADI_3_REFSYS_O_DCDCCTL5 0x0000000B +#define ADI_3_REFSYS_O_DCDCCTL5 0x0000000B // RECHARGE_CONTROL_1 -#define ADI_3_REFSYS_O_AUX_DEBUG 0x0000000C +#define ADI_3_REFSYS_O_AUX_DEBUG 0x0000000C // Recharge Comparator Control Byte 0 -#define ADI_3_REFSYS_O_CTL_RECHARGE_CMP0 0x0000000D +#define ADI_3_REFSYS_O_CTL_RECHARGE_CMP0 0x0000000D // Recharge Comparator Control Byte 1 -#define ADI_3_REFSYS_O_CTL_RECHARGE_CMP1 0x0000000E +#define ADI_3_REFSYS_O_CTL_RECHARGE_CMP1 0x0000000E //***************************************************************************** // @@ -97,12 +97,12 @@ // ICELL_A0 Internal. Only to be used through TI provided API. // IREF_A0 Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_W 2 -#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_M 0x00000018 -#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_S 3 -#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_ICELL_A0 0x00000010 -#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_IREF_A0 0x00000008 -#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_NC 0x00000000 +#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_W 2 +#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_M 0x00000018 +#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_S 3 +#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_ICELL_A0 0x00000010 +#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_IREF_A0 0x00000008 +#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_NC 0x00000000 // Field: [2:0] ATEST1_CTL // @@ -112,13 +112,13 @@ // VPP_DIV5_A1 Internal. Only to be used through TI provided API. // VREAD_DIV2_A1 Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_W 3 -#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_M 0x00000007 -#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_S 0 -#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_VREFM_A1 0x00000004 -#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_VPP_DIV5_A1 0x00000002 -#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_VREAD_DIV2_A1 0x00000001 -#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_NC 0x00000000 +#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_W 3 +#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_M 0x00000007 +#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_S 0 +#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_VREFM_A1 0x00000004 +#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_VPP_DIV5_A1 0x00000002 +#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_VREAD_DIV2_A1 0x00000001 +#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_NC 0x00000000 //***************************************************************************** // @@ -138,18 +138,18 @@ // IVREF4U Internal. Only to be used through TI provided API. // IPTAT2U Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_W 8 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_M 0x000000FF -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_S 0 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_BMCOMPOUT 0x00000080 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VTEMP 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VREF0P8V 0x00000020 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBGUNBUFF 0x00000010 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBG 0x00000008 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IREF4U 0x00000004 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IVREF4U 0x00000002 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IPTAT2U 0x00000001 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_NC 0x00000000 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_W 8 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_M 0x000000FF +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_S 0 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_BMCOMPOUT 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VTEMP 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VREF0P8V 0x00000020 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBGUNBUFF 0x00000010 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBG 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IREF4U 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IVREF4U 0x00000002 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IPTAT2U 0x00000001 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_NC 0x00000000 //***************************************************************************** // @@ -192,41 +192,41 @@ // POS_6 Internal. Only to be used through TI provided API. // POS_5 Internal. Only to be used through TI provided API. // POS_4 Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_W 5 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M 0x000000F8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S 3 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_27 0x000000F8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_26 0x000000F0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_25 0x000000E8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_24 0x000000E0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 0x000000D8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_30 0x000000D0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_29 0x000000C8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_28 0x000000C0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_19 0x000000B8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_18 0x000000B0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_17 0x000000A8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_16 0x000000A0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_23 0x00000098 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_22 0x00000090 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_21 0x00000088 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_20 0x00000080 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_11 0x00000078 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_10 0x00000070 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_9 0x00000068 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_8 0x00000060 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_15 0x00000058 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_14 0x00000050 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_13 0x00000048 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_12 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_3 0x00000038 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_2 0x00000030 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_1 0x00000028 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_0 0x00000020 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_7 0x00000018 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_6 0x00000010 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_5 0x00000008 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_4 0x00000000 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_W 5 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M 0x000000F8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S 3 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_27 0x000000F8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_26 0x000000F0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_25 0x000000E8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_24 0x000000E0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 0x000000D8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_30 0x000000D0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_29 0x000000C8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_28 0x000000C0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_19 0x000000B8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_18 0x000000B0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_17 0x000000A8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_16 0x000000A0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_23 0x00000098 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_22 0x00000090 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_21 0x00000088 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_20 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_11 0x00000078 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_10 0x00000070 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_9 0x00000068 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_8 0x00000060 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_15 0x00000058 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_14 0x00000050 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_13 0x00000048 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_12 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_3 0x00000038 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_2 0x00000030 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_1 0x00000028 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_0 0x00000020 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_7 0x00000018 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_6 0x00000010 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_5 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_4 0x00000000 // Field: [2] BATMON_COMP_TEST_EN // @@ -234,11 +234,11 @@ // ENUMs: // EN Internal. Only to be used through TI provided API. // DIS Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN 0x00000004 -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_M 0x00000004 -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_S 2 -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_EN 0x00000004 -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_DIS 0x00000000 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_M 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_S 2 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_EN 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_DIS 0x00000000 // Field: [1:0] TESTCTL // @@ -247,12 +247,12 @@ // IPTAT1U Internal. Only to be used through TI provided API. // BMCOMPIN Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_W 2 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_M 0x00000003 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_S 0 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_IPTAT1U 0x00000002 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_BMCOMPIN 0x00000001 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_NC 0x00000000 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_W 2 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_M 0x00000003 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_S 0 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_IPTAT1U 0x00000002 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_BMCOMPIN 0x00000001 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_NC 0x00000000 //***************************************************************************** // @@ -262,23 +262,23 @@ // Field: [7:4] TRIM_VREF // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_W 4 -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_M 0x000000F0 -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_S 4 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_W 4 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_M 0x000000F0 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_S 4 // Field: [3] BOD_EXTERNAL_REG_MODE // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL2_BOD_EXTERNAL_REG_MODE 0x00000008 -#define ADI_3_REFSYS_REFSYSCTL2_BOD_EXTERNAL_REG_MODE_M 0x00000008 -#define ADI_3_REFSYS_REFSYSCTL2_BOD_EXTERNAL_REG_MODE_S 3 +#define ADI_3_REFSYS_REFSYSCTL2_BOD_EXTERNAL_REG_MODE 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL2_BOD_EXTERNAL_REG_MODE_M 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL2_BOD_EXTERNAL_REG_MODE_S 3 // Field: [1:0] TRIM_TSENSE // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_W 2 -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_M 0x00000003 -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_S 0 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_W 2 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_M 0x00000003 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_S 0 //***************************************************************************** // @@ -288,9 +288,9 @@ // Field: [7] BOD_BG_TRIM_EN // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN 0x00000080 -#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_M 0x00000080 -#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_S 7 +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_M 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_S 7 // Field: [6] VTEMP_EN // @@ -298,18 +298,18 @@ // ENUMs: // EN Internal. Only to be used through TI provided API. // DIS Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_M 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_S 6 -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_EN 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_DIS 0x00000000 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_M 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_S 6 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_EN 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_DIS 0x00000000 // Field: [5:0] TRIM_VBG // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W 6 -#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M 0x0000003F -#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S 0 +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W 6 +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M 0x0000003F +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S 0 //***************************************************************************** // @@ -324,9 +324,9 @@ // 0x0: Default 11mA. // 0x3: Max 15mA. // 0x4: Max 5mA -#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_W 3 -#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_M 0x000000E0 -#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_S 5 +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_W 3 +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_M 0x000000E0 +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_S 5 // Field: [4:0] VDDR_TRIM // @@ -341,9 +341,9 @@ // 0x05: Typical voltage after trim voltage 1.71V. // 0x15: Max voltage 1.96V. // 0x16: Min voltage 1.47V. -#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_W 5 -#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M 0x0000001F -#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S 0 +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_W 5 +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M 0x0000001F +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S 0 //***************************************************************************** // @@ -359,9 +359,9 @@ // 0x1: Increase GLDO bias by 1.3x. // 0x2: Increase GLDO bias by 1.6x. // 0x3: Decrease GLDO bias by 0.7x. -#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_W 2 -#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_M 0x000000C0 -#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_S 6 +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_W 2 +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_M 0x000000C0 +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_S 6 // Field: [5] VDDR_OK_HYST // @@ -369,9 +369,9 @@ // // 0: Hysteresis = 60mV // 1: Hysteresis = 70mV -#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST 0x00000020 -#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_M 0x00000020 -#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_S 5 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST 0x00000020 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_S 5 // Field: [4:0] VDDR_TRIM_SLEEP // @@ -386,9 +386,9 @@ // 0x19: Typical voltage after trim voltage 1.52V. // 0x15: Max voltage 1.96V. // 0x16: Min voltage 1.47V. -#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_W 5 -#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M 0x0000001F -#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S 0 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_W 5 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M 0x0000001F +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S 0 //***************************************************************************** // @@ -401,9 +401,9 @@ // // 0: Erroramp Off (Default) // 1: Erroramp On. Turns on GLDO error amp switch. -#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW 0x00000040 -#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_M 0x00000040 -#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_S 6 +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW 0x00000040 +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_M 0x00000040 +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_S 6 // Field: [5] TEST_VDDR // @@ -413,9 +413,9 @@ // 1: Connected // // Set TESTSEL = 0x0 first before setting this bit. -#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR 0x00000020 -#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_M 0x00000020 -#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_S 5 +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR 0x00000020 +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_S 5 // Field: [4] BIAS_DIS // @@ -423,9 +423,9 @@ // // 0: Dummy bias current on (Default) // 1: Dummy bias current off -#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS 0x00000010 -#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_M 0x00000010 -#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_S 4 +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS 0x00000010 +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_M 0x00000010 +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_S 4 // Field: [3:0] TESTSEL // @@ -437,14 +437,14 @@ // bus. // ERRAMP_OUT Error amp output voltage connected to test bus. // NC No signal connected to test bus. -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_W 4 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_M 0x0000000F -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_S 0 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_VDDROK 0x00000008 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_IB1U 0x00000004 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_PASSGATE 0x00000002 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_ERRAMP_OUT 0x00000001 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_NC 0x00000000 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_W 4 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_M 0x0000000F +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_S 0 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_VDDROK 0x00000008 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_IB1U 0x00000004 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_PASSGATE 0x00000002 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_ERRAMP_OUT 0x00000001 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_NC 0x00000000 //***************************************************************************** // @@ -459,13 +459,13 @@ // BOOST Internal. Only to be used through TI provided API. // BOOST_N1 Internal. Only to be used through TI provided API. // DEFAULT Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_W 2 -#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_M 0x00000003 -#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_S 0 -#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST_P1 0x00000003 -#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST 0x00000002 -#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST_N1 0x00000001 -#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_DEFAULT 0x00000000 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_W 2 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_M 0x00000003 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_S 0 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST_P1 0x00000003 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST 0x00000002 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST_N1 0x00000001 +#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_DEFAULT 0x00000000 //***************************************************************************** // @@ -475,23 +475,23 @@ // Field: [7:6] DEADTIME_TRIM // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_W 2 -#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_M 0x000000C0 -#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_S 6 +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_W 2 +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_M 0x000000C0 +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_S 6 // Field: [5:3] LOW_EN_SEL // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_W 3 -#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_M 0x00000038 -#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_S 3 +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_W 3 +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_M 0x00000038 +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_S 3 // Field: [2:0] HIGH_EN_SEL // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_W 3 -#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_M 0x00000007 -#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_S 0 +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_W 3 +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_M 0x00000007 +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_S 0 //***************************************************************************** // @@ -501,16 +501,16 @@ // Field: [5] TESTN // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL5_TESTN 0x00000020 -#define ADI_3_REFSYS_DCDCCTL5_TESTN_M 0x00000020 -#define ADI_3_REFSYS_DCDCCTL5_TESTN_S 5 +#define ADI_3_REFSYS_DCDCCTL5_TESTN 0x00000020 +#define ADI_3_REFSYS_DCDCCTL5_TESTN_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL5_TESTN_S 5 // Field: [4] TESTP // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL5_TESTP 0x00000010 -#define ADI_3_REFSYS_DCDCCTL5_TESTP_M 0x00000010 -#define ADI_3_REFSYS_DCDCCTL5_TESTP_S 4 +#define ADI_3_REFSYS_DCDCCTL5_TESTP 0x00000010 +#define ADI_3_REFSYS_DCDCCTL5_TESTP_M 0x00000010 +#define ADI_3_REFSYS_DCDCCTL5_TESTP_S 4 // Field: [3] DITHER_EN // @@ -518,18 +518,18 @@ // ENUMs: // EN Internal. Only to be used through TI provided API. // DIS Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN 0x00000008 -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_M 0x00000008 -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_S 3 -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_EN 0x00000008 -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_DIS 0x00000000 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_M 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_S 3 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_EN 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_DIS 0x00000000 // Field: [2:0] IPEAK // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL5_IPEAK_W 3 -#define ADI_3_REFSYS_DCDCCTL5_IPEAK_M 0x00000007 -#define ADI_3_REFSYS_DCDCCTL5_IPEAK_S 0 +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_W 3 +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_M 0x00000007 +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_S 0 //***************************************************************************** // @@ -539,51 +539,51 @@ // Field: [6] LPM_BIAS_BACKUP_EN // // Activate the backup circuit in case the main circuit does not work -#define ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN 0x00000040 -#define ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN_M 0x00000040 -#define ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN_S 6 +#define ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN 0x00000040 +#define ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN_M 0x00000040 +#define ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN_S 6 // Field: [5] DAC_DBG_OFFSET_COMP // // Offset compensation signal (Debug Mode) -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_OFFSET_COMP 0x00000020 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_OFFSET_COMP_M 0x00000020 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_OFFSET_COMP_S 5 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_OFFSET_COMP 0x00000020 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_OFFSET_COMP_M 0x00000020 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_OFFSET_COMP_S 5 // Field: [4] DAC_DBG_HOLD // // S-H Cap hold signal (Debug Mode) -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_HOLD 0x00000010 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_HOLD_M 0x00000010 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_HOLD_S 4 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_HOLD 0x00000010 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_HOLD_M 0x00000010 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_HOLD_S 4 // Field: [3] DAC_DBG_PRECHARGE // // PRE-CHARGE signal (Debug Mode) -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_PRECHARGE 0x00000008 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_PRECHARGE_M 0x00000008 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_PRECHARGE_S 3 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_PRECHARGE 0x00000008 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_PRECHARGE_M 0x00000008 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_PRECHARGE_S 3 // Field: [2] DAC_DBG_CAP_SAMPLE // // Cap-array sample signal (Debug Mode) -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_CAP_SAMPLE 0x00000004 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_CAP_SAMPLE_M 0x00000004 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_CAP_SAMPLE_S 2 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_CAP_SAMPLE 0x00000004 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_CAP_SAMPLE_M 0x00000004 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_CAP_SAMPLE_S 2 // Field: [1] DAC_DBG_SAMPLE // // S-H Cap sample signal (Debug Mode) -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_SAMPLE 0x00000002 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_SAMPLE_M 0x00000002 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_SAMPLE_S 1 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_SAMPLE 0x00000002 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_SAMPLE_M 0x00000002 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_SAMPLE_S 1 // Field: [0] DAC_DBG_EN // // Enable Debug Mode -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_EN 0x00000001 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_EN_M 0x00000001 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_EN_S 0 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_EN 0x00000001 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_EN_M 0x00000001 +#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_EN_S 0 //***************************************************************************** // @@ -596,11 +596,11 @@ // ENUMs: // DIS Disable the clock // EN Enable the clock -#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE 0x00000010 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_M 0x00000010 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_S 4 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_DIS 0x00000010 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_EN 0x00000000 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE 0x00000010 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_M 0x00000010 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_S 4 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_DIS 0x00000010 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_EN 0x00000000 // Field: [3:0] TRIM_RECHARGE_COMP_REFLEVEL // @@ -629,14 +629,14 @@ // ENUMs: // EN Enable. VDDR input is connected to ATEST network // DIS Disable. VDDR input is connected to VDDR itself -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN 0x00000080 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_M \ +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN 0x00000080 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_M \ 0x00000080 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_S \ +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_S \ 7 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_EN \ +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_EN \ 0x00000080 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_DIS \ +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_DIS \ 0x00000000 // Field: [6] RECHARGE_BLOCK_ATEST_EN @@ -645,14 +645,14 @@ // ENUMs: // EN Enable // DIS Disable -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN 0x00000040 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_M \ +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN 0x00000040 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_M \ 0x00000040 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_S \ +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_S \ 6 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_EN \ +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_EN \ 0x00000040 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_DIS \ +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_DIS \ 0x00000000 // Field: [5] FORCE_SAMPLE_VDDR @@ -661,11 +661,11 @@ // ENUMs: // EN Enable // DIS Disable -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR 0x00000020 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_M 0x00000020 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_S 5 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_EN 0x00000020 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_DIS 0x00000000 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR 0x00000020 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_M 0x00000020 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_S 5 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_EN 0x00000020 +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_DIS 0x00000000 // Field: [4:0] TRIM_RECHARGE_COMP_OFFSET // @@ -674,12 +674,11 @@ // 0x00: Maximum degeneration on input side (VDDR side). // 0x1F: Maximum degeneration on reference side from cap divider. // 0x10: Nominal code. -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_W \ +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_W \ 5 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_M \ +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_M \ 0x0000001F -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_S \ +#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_S \ 0 - #endif // __ADI_3_REFSYS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_4_aux.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_4_aux.h index f17daf6..6b038ef 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_4_aux.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_4_aux.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_adi_4_aux_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_adi_4_aux_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_ADI_4_AUX_H__ #define __HW_ADI_4_AUX_H__ @@ -44,40 +44,40 @@ // //***************************************************************************** // Internal -#define ADI_4_AUX_O_MUX0 0x00000000 +#define ADI_4_AUX_O_MUX0 0x00000000 // Internal -#define ADI_4_AUX_O_MUX1 0x00000001 +#define ADI_4_AUX_O_MUX1 0x00000001 // Internal -#define ADI_4_AUX_O_MUX2 0x00000002 +#define ADI_4_AUX_O_MUX2 0x00000002 // Internal -#define ADI_4_AUX_O_MUX3 0x00000003 +#define ADI_4_AUX_O_MUX3 0x00000003 // Current Source -#define ADI_4_AUX_O_ISRC 0x00000004 +#define ADI_4_AUX_O_ISRC 0x00000004 // Comparator -#define ADI_4_AUX_O_COMP 0x00000005 +#define ADI_4_AUX_O_COMP 0x00000005 // Internal -#define ADI_4_AUX_O_MUX4 0x00000007 +#define ADI_4_AUX_O_MUX4 0x00000007 // ADC Control 0 -#define ADI_4_AUX_O_ADC0 0x00000008 +#define ADI_4_AUX_O_ADC0 0x00000008 // ADC Control 1 -#define ADI_4_AUX_O_ADC1 0x00000009 +#define ADI_4_AUX_O_ADC1 0x00000009 // ADC Reference 0 -#define ADI_4_AUX_O_ADCREF0 0x0000000A +#define ADI_4_AUX_O_ADCREF0 0x0000000A // ADC Reference 1 -#define ADI_4_AUX_O_ADCREF1 0x0000000B +#define ADI_4_AUX_O_ADCREF1 0x0000000B // Internal -#define ADI_4_AUX_O_LPMBIAS 0x0000000E +#define ADI_4_AUX_O_LPMBIAS 0x0000000E //***************************************************************************** // @@ -90,11 +90,11 @@ // ENUMs: // VDDR_1P8V Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX0_ADCCOMPB_IN 0x00000040 -#define ADI_4_AUX_MUX0_ADCCOMPB_IN_M 0x00000040 -#define ADI_4_AUX_MUX0_ADCCOMPB_IN_S 6 -#define ADI_4_AUX_MUX0_ADCCOMPB_IN_VDDR_1P8V 0x00000040 -#define ADI_4_AUX_MUX0_ADCCOMPB_IN_NC 0x00000000 +#define ADI_4_AUX_MUX0_ADCCOMPB_IN 0x00000040 +#define ADI_4_AUX_MUX0_ADCCOMPB_IN_M 0x00000040 +#define ADI_4_AUX_MUX0_ADCCOMPB_IN_S 6 +#define ADI_4_AUX_MUX0_ADCCOMPB_IN_VDDR_1P8V 0x00000040 +#define ADI_4_AUX_MUX0_ADCCOMPB_IN_NC 0x00000000 // Field: [3:0] COMPA_REF // @@ -105,14 +105,14 @@ // VSS Internal. Only to be used through TI provided API. // DCOUPL Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX0_COMPA_REF_W 4 -#define ADI_4_AUX_MUX0_COMPA_REF_M 0x0000000F -#define ADI_4_AUX_MUX0_COMPA_REF_S 0 -#define ADI_4_AUX_MUX0_COMPA_REF_ADCVREFP 0x00000008 -#define ADI_4_AUX_MUX0_COMPA_REF_VDDS 0x00000004 -#define ADI_4_AUX_MUX0_COMPA_REF_VSS 0x00000002 -#define ADI_4_AUX_MUX0_COMPA_REF_DCOUPL 0x00000001 -#define ADI_4_AUX_MUX0_COMPA_REF_NC 0x00000000 +#define ADI_4_AUX_MUX0_COMPA_REF_W 4 +#define ADI_4_AUX_MUX0_COMPA_REF_M 0x0000000F +#define ADI_4_AUX_MUX0_COMPA_REF_S 0 +#define ADI_4_AUX_MUX0_COMPA_REF_ADCVREFP 0x00000008 +#define ADI_4_AUX_MUX0_COMPA_REF_VDDS 0x00000004 +#define ADI_4_AUX_MUX0_COMPA_REF_VSS 0x00000002 +#define ADI_4_AUX_MUX0_COMPA_REF_DCOUPL 0x00000001 +#define ADI_4_AUX_MUX0_COMPA_REF_NC 0x00000000 //***************************************************************************** // @@ -132,18 +132,18 @@ // AUXIO25 Internal. Only to be used through TI provided API. // AUXIO26 Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX1_COMPA_IN_W 8 -#define ADI_4_AUX_MUX1_COMPA_IN_M 0x000000FF -#define ADI_4_AUX_MUX1_COMPA_IN_S 0 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO19 0x00000080 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO20 0x00000040 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO21 0x00000020 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO22 0x00000010 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO23 0x00000008 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO24 0x00000004 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO25 0x00000002 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO26 0x00000001 -#define ADI_4_AUX_MUX1_COMPA_IN_NC 0x00000000 +#define ADI_4_AUX_MUX1_COMPA_IN_W 8 +#define ADI_4_AUX_MUX1_COMPA_IN_M 0x000000FF +#define ADI_4_AUX_MUX1_COMPA_IN_S 0 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO19 0x00000080 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO20 0x00000040 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO21 0x00000020 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO22 0x00000010 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO23 0x00000008 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO24 0x00000004 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO25 0x00000002 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO26 0x00000001 +#define ADI_4_AUX_MUX1_COMPA_IN_NC 0x00000000 //***************************************************************************** // @@ -160,15 +160,15 @@ // ATEST1 Internal. Only to be used through TI provided API. // ATEST0 Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_W 5 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_M 0x000000F8 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_S 3 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VDDS 0x00000080 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VSS 0x00000040 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_DCOUPL 0x00000020 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST1 0x00000010 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST0 0x00000008 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_NC 0x00000000 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_W 5 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_M 0x000000F8 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_S 3 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VDDS 0x00000080 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VSS 0x00000040 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_DCOUPL 0x00000020 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST1 0x00000010 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST0 0x00000008 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_NC 0x00000000 // Field: [2:0] DAC_VREF_SEL // @@ -178,13 +178,13 @@ // ADCREF Internal. Only to be used through TI provided API. // DCOUPL Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX2_DAC_VREF_SEL_W 3 -#define ADI_4_AUX_MUX2_DAC_VREF_SEL_M 0x00000007 -#define ADI_4_AUX_MUX2_DAC_VREF_SEL_S 0 -#define ADI_4_AUX_MUX2_DAC_VREF_SEL_VDDS 0x00000004 -#define ADI_4_AUX_MUX2_DAC_VREF_SEL_ADCREF 0x00000002 -#define ADI_4_AUX_MUX2_DAC_VREF_SEL_DCOUPL 0x00000001 -#define ADI_4_AUX_MUX2_DAC_VREF_SEL_NC 0x00000000 +#define ADI_4_AUX_MUX2_DAC_VREF_SEL_W 3 +#define ADI_4_AUX_MUX2_DAC_VREF_SEL_M 0x00000007 +#define ADI_4_AUX_MUX2_DAC_VREF_SEL_S 0 +#define ADI_4_AUX_MUX2_DAC_VREF_SEL_VDDS 0x00000004 +#define ADI_4_AUX_MUX2_DAC_VREF_SEL_ADCREF 0x00000002 +#define ADI_4_AUX_MUX2_DAC_VREF_SEL_DCOUPL 0x00000001 +#define ADI_4_AUX_MUX2_DAC_VREF_SEL_NC 0x00000000 //***************************************************************************** // @@ -204,18 +204,18 @@ // AUXIO25 Internal. Only to be used through TI provided API. // AUXIO26 Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_W 8 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_M 0x000000FF -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_S 0 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO19 0x00000080 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO20 0x00000040 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO21 0x00000020 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO22 0x00000010 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO23 0x00000008 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO24 0x00000004 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO25 0x00000002 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO26 0x00000001 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_NC 0x00000000 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_W 8 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_M 0x000000FF +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_S 0 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO19 0x00000080 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO20 0x00000040 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO21 0x00000020 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO22 0x00000010 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO23 0x00000008 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO24 0x00000004 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO25 0x00000002 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO26 0x00000001 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_NC 0x00000000 //***************************************************************************** // @@ -235,23 +235,23 @@ // 0P5U 0.5 uA // 0P25U 0.25 uA // NC No current connected -#define ADI_4_AUX_ISRC_TRIM_W 6 -#define ADI_4_AUX_ISRC_TRIM_M 0x000000FC -#define ADI_4_AUX_ISRC_TRIM_S 2 -#define ADI_4_AUX_ISRC_TRIM_11P75U 0x00000080 -#define ADI_4_AUX_ISRC_TRIM_4P5U 0x00000040 -#define ADI_4_AUX_ISRC_TRIM_2P0U 0x00000020 -#define ADI_4_AUX_ISRC_TRIM_1P0U 0x00000010 -#define ADI_4_AUX_ISRC_TRIM_0P5U 0x00000008 -#define ADI_4_AUX_ISRC_TRIM_0P25U 0x00000004 -#define ADI_4_AUX_ISRC_TRIM_NC 0x00000000 +#define ADI_4_AUX_ISRC_TRIM_W 6 +#define ADI_4_AUX_ISRC_TRIM_M 0x000000FC +#define ADI_4_AUX_ISRC_TRIM_S 2 +#define ADI_4_AUX_ISRC_TRIM_11P75U 0x00000080 +#define ADI_4_AUX_ISRC_TRIM_4P5U 0x00000040 +#define ADI_4_AUX_ISRC_TRIM_2P0U 0x00000020 +#define ADI_4_AUX_ISRC_TRIM_1P0U 0x00000010 +#define ADI_4_AUX_ISRC_TRIM_0P5U 0x00000008 +#define ADI_4_AUX_ISRC_TRIM_0P25U 0x00000004 +#define ADI_4_AUX_ISRC_TRIM_NC 0x00000000 // Field: [0] EN // // Current source enable -#define ADI_4_AUX_ISRC_EN 0x00000001 -#define ADI_4_AUX_ISRC_EN_M 0x00000001 -#define ADI_4_AUX_ISRC_EN_S 0 +#define ADI_4_AUX_ISRC_EN 0x00000001 +#define ADI_4_AUX_ISRC_EN_M 0x00000001 +#define ADI_4_AUX_ISRC_EN_S 0 //***************************************************************************** // @@ -262,39 +262,39 @@ // // Enables 400kohm resistance from COMPA reference node to ground. Used with // COMPA_REF_CURR_EN to generate voltage reference for cap-sense. -#define ADI_4_AUX_COMP_COMPA_REF_RES_EN 0x00000080 -#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_M 0x00000080 -#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_S 7 +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN 0x00000080 +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_M 0x00000080 +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_S 7 // Field: [6] COMPA_REF_CURR_EN // // Enables 2uA IPTAT current from ISRC to COMPA reference node. Requires // ISRC.EN = 1. Used with COMPA_REF_RES_EN to generate voltage reference for // cap-sense. -#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN 0x00000040 -#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_M 0x00000040 -#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_S 6 +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN 0x00000040 +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_M 0x00000040 +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_S 6 // Field: [5:3] LPM_BIAS_WIDTH_TRIM // // Internal. Only to be used through TI provided API. -#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_W 3 -#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M 0x00000038 -#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S 3 +#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_W 3 +#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M 0x00000038 +#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S 3 // Field: [2] COMPB_EN // // COMPB enable -#define ADI_4_AUX_COMP_COMPB_EN 0x00000004 -#define ADI_4_AUX_COMP_COMPB_EN_M 0x00000004 -#define ADI_4_AUX_COMP_COMPB_EN_S 2 +#define ADI_4_AUX_COMP_COMPB_EN 0x00000004 +#define ADI_4_AUX_COMP_COMPB_EN_M 0x00000004 +#define ADI_4_AUX_COMP_COMPB_EN_S 2 // Field: [0] COMPA_EN // // COMPA enable -#define ADI_4_AUX_COMP_COMPA_EN 0x00000001 -#define ADI_4_AUX_COMP_COMPA_EN_M 0x00000001 -#define ADI_4_AUX_COMP_COMPA_EN_S 0 +#define ADI_4_AUX_COMP_COMPA_EN 0x00000001 +#define ADI_4_AUX_COMP_COMPA_EN_M 0x00000001 +#define ADI_4_AUX_COMP_COMPA_EN_S 0 //***************************************************************************** // @@ -314,18 +314,18 @@ // AUXIO25 Internal. Only to be used through TI provided API. // AUXIO26 Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX4_COMPA_REF_W 8 -#define ADI_4_AUX_MUX4_COMPA_REF_M 0x000000FF -#define ADI_4_AUX_MUX4_COMPA_REF_S 0 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO19 0x00000080 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO20 0x00000040 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO21 0x00000020 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO22 0x00000010 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO23 0x00000008 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO24 0x00000004 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO25 0x00000002 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO26 0x00000001 -#define ADI_4_AUX_MUX4_COMPA_REF_NC 0x00000000 +#define ADI_4_AUX_MUX4_COMPA_REF_W 8 +#define ADI_4_AUX_MUX4_COMPA_REF_M 0x000000FF +#define ADI_4_AUX_MUX4_COMPA_REF_S 0 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO19 0x00000080 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO20 0x00000040 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO21 0x00000020 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO22 0x00000010 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO23 0x00000008 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO24 0x00000004 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO25 0x00000002 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO26 0x00000001 +#define ADI_4_AUX_MUX4_COMPA_REF_NC 0x00000000 //***************************************************************************** // @@ -351,9 +351,9 @@ // signal. Sampling restarts when the conversion has finished. // Asynchronous mode is useful when it is important to avoid jitter in the // sampling instant of an externally driven signal -#define ADI_4_AUX_ADC0_SMPL_MODE 0x00000080 -#define ADI_4_AUX_ADC0_SMPL_MODE_M 0x00000080 -#define ADI_4_AUX_ADC0_SMPL_MODE_S 7 +#define ADI_4_AUX_ADC0_SMPL_MODE 0x00000080 +#define ADI_4_AUX_ADC0_SMPL_MODE_M 0x00000080 +#define ADI_4_AUX_ADC0_SMPL_MODE_S 7 // Field: [6:3] SMPL_CYCLE_EXP // @@ -374,22 +374,22 @@ // 10P6_US 64x 6 MHz clock periods = 10.6us // 5P3_US 32x 6 MHz clock periods = 5.3us // 2P7_US 16x 6 MHz clock periods = 2.7us -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_W 4 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M 0x00000078 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S 3 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P9_MS 0x00000078 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P46_MS 0x00000070 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P73_MS 0x00000068 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_1P37_MS 0x00000060 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_682_US 0x00000058 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_341_US 0x00000050 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_170_US 0x00000048 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_85P3_US 0x00000040 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_42P6_US 0x00000038 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_21P3_US 0x00000030 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P6_US 0x00000028 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P3_US 0x00000020 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P7_US 0x00000018 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_W 4 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M 0x00000078 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S 3 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P9_MS 0x00000078 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P46_MS 0x00000070 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P73_MS 0x00000068 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_1P37_MS 0x00000060 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_682_US 0x00000058 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_341_US 0x00000050 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_170_US 0x00000048 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_85P3_US 0x00000040 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_42P6_US 0x00000038 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_21P3_US 0x00000030 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P6_US 0x00000028 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P3_US 0x00000020 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P7_US 0x00000018 // Field: [1] RESET_N // @@ -398,9 +398,9 @@ // // 0: Reset // 1: Normal operation -#define ADI_4_AUX_ADC0_RESET_N 0x00000002 -#define ADI_4_AUX_ADC0_RESET_N_M 0x00000002 -#define ADI_4_AUX_ADC0_RESET_N_S 1 +#define ADI_4_AUX_ADC0_RESET_N 0x00000002 +#define ADI_4_AUX_ADC0_RESET_N_M 0x00000002 +#define ADI_4_AUX_ADC0_RESET_N_S 1 // Field: [0] EN // @@ -408,9 +408,9 @@ // // 0: Disable // 1: Enable -#define ADI_4_AUX_ADC0_EN 0x00000001 -#define ADI_4_AUX_ADC0_EN_M 0x00000001 -#define ADI_4_AUX_ADC0_EN_S 0 +#define ADI_4_AUX_ADC0_EN 0x00000001 +#define ADI_4_AUX_ADC0_EN_M 0x00000001 +#define ADI_4_AUX_ADC0_EN_S 0 //***************************************************************************** // @@ -420,9 +420,9 @@ // Field: [0] SCALE_DIS // // Internal. Only to be used through TI provided API. -#define ADI_4_AUX_ADC1_SCALE_DIS 0x00000001 -#define ADI_4_AUX_ADC1_SCALE_DIS_M 0x00000001 -#define ADI_4_AUX_ADC1_SCALE_DIS_S 0 +#define ADI_4_AUX_ADC1_SCALE_DIS 0x00000001 +#define ADI_4_AUX_ADC1_SCALE_DIS_M 0x00000001 +#define ADI_4_AUX_ADC1_SCALE_DIS_S 0 //***************************************************************************** // @@ -439,23 +439,23 @@ // Keep ADCREF enabled when ADC0.SMPL_MODE = 0. // Recommendation: Enable ADCREF always when ADC0.SMPL_CYCLE_EXP is less than // 0x6 (21.3us sampling time). -#define ADI_4_AUX_ADCREF0_REF_ON_IDLE 0x00000040 -#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_M 0x00000040 -#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_S 6 +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE 0x00000040 +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_M 0x00000040 +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_S 6 // Field: [5] IOMUX // // Internal. Only to be used through TI provided API. -#define ADI_4_AUX_ADCREF0_IOMUX 0x00000020 -#define ADI_4_AUX_ADCREF0_IOMUX_M 0x00000020 -#define ADI_4_AUX_ADCREF0_IOMUX_S 5 +#define ADI_4_AUX_ADCREF0_IOMUX 0x00000020 +#define ADI_4_AUX_ADCREF0_IOMUX_M 0x00000020 +#define ADI_4_AUX_ADCREF0_IOMUX_S 5 // Field: [4] EXT // // Internal. Only to be used through TI provided API. -#define ADI_4_AUX_ADCREF0_EXT 0x00000010 -#define ADI_4_AUX_ADCREF0_EXT_M 0x00000010 -#define ADI_4_AUX_ADCREF0_EXT_S 4 +#define ADI_4_AUX_ADCREF0_EXT 0x00000010 +#define ADI_4_AUX_ADCREF0_EXT_M 0x00000010 +#define ADI_4_AUX_ADCREF0_EXT_S 4 // Field: [3] SRC // @@ -463,9 +463,9 @@ // // 0: Fixed reference = 4.3V // 1: Relative reference = VDDS -#define ADI_4_AUX_ADCREF0_SRC 0x00000008 -#define ADI_4_AUX_ADCREF0_SRC_M 0x00000008 -#define ADI_4_AUX_ADCREF0_SRC_S 3 +#define ADI_4_AUX_ADCREF0_SRC 0x00000008 +#define ADI_4_AUX_ADCREF0_SRC_M 0x00000008 +#define ADI_4_AUX_ADCREF0_SRC_S 3 // Field: [0] EN // @@ -473,9 +473,9 @@ // // 0: ADC reference module powered down // 1: ADC reference module enabled -#define ADI_4_AUX_ADCREF0_EN 0x00000001 -#define ADI_4_AUX_ADCREF0_EN_M 0x00000001 -#define ADI_4_AUX_ADCREF0_EN_S 0 +#define ADI_4_AUX_ADCREF0_EN 0x00000001 +#define ADI_4_AUX_ADCREF0_EN_M 0x00000001 +#define ADI_4_AUX_ADCREF0_EN_S 0 //***************************************************************************** // @@ -493,9 +493,9 @@ // 0x3F - nominal - 0.4% 1.425V // 0x1F - maximum voltage 1.6V // 0x20 - minimum voltage 1.3V -#define ADI_4_AUX_ADCREF1_VTRIM_W 6 -#define ADI_4_AUX_ADCREF1_VTRIM_M 0x0000003F -#define ADI_4_AUX_ADCREF1_VTRIM_S 0 +#define ADI_4_AUX_ADCREF1_VTRIM_W 6 +#define ADI_4_AUX_ADCREF1_VTRIM_M 0x0000003F +#define ADI_4_AUX_ADCREF1_VTRIM_S 0 //***************************************************************************** // @@ -505,9 +505,8 @@ // Field: [5:0] LPM_TRIM_IOUT // // Internal. Only to be used through TI provided API. -#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_W 6 -#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M 0x0000003F -#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S 0 - +#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_W 6 +#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M 0x0000003F +#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S 0 #endif // __ADI_4_AUX__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_batmon.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_batmon.h index 257c8a6..22b65f2 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_batmon.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_batmon.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aon_batmon_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aon_batmon_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AON_BATMON_H__ #define __HW_AON_BATMON_H__ @@ -44,61 +44,61 @@ // //***************************************************************************** // Internal -#define AON_BATMON_O_CTL 0x00000000 +#define AON_BATMON_O_CTL 0x00000000 // Internal -#define AON_BATMON_O_MEASCFG 0x00000004 +#define AON_BATMON_O_MEASCFG 0x00000004 // Internal -#define AON_BATMON_O_TEMPP0 0x0000000C +#define AON_BATMON_O_TEMPP0 0x0000000C // Internal -#define AON_BATMON_O_TEMPP1 0x00000010 +#define AON_BATMON_O_TEMPP1 0x00000010 // Internal -#define AON_BATMON_O_TEMPP2 0x00000014 +#define AON_BATMON_O_TEMPP2 0x00000014 // Internal -#define AON_BATMON_O_BATMONP0 0x00000018 +#define AON_BATMON_O_BATMONP0 0x00000018 // Internal -#define AON_BATMON_O_BATMONP1 0x0000001C +#define AON_BATMON_O_BATMONP1 0x0000001C // Internal -#define AON_BATMON_O_IOSTRP0 0x00000020 +#define AON_BATMON_O_IOSTRP0 0x00000020 // Internal -#define AON_BATMON_O_FLASHPUMPP0 0x00000024 +#define AON_BATMON_O_FLASHPUMPP0 0x00000024 // Last Measured Battery Voltage -#define AON_BATMON_O_BAT 0x00000028 +#define AON_BATMON_O_BAT 0x00000028 // Battery Update -#define AON_BATMON_O_BATUPD 0x0000002C +#define AON_BATMON_O_BATUPD 0x0000002C // Temperature -#define AON_BATMON_O_TEMP 0x00000030 +#define AON_BATMON_O_TEMP 0x00000030 // Temperature Update -#define AON_BATMON_O_TEMPUPD 0x00000034 +#define AON_BATMON_O_TEMPUPD 0x00000034 // Event Mask -#define AON_BATMON_O_EVENTMASK 0x00000048 +#define AON_BATMON_O_EVENTMASK 0x00000048 // Event -#define AON_BATMON_O_EVENT 0x0000004C +#define AON_BATMON_O_EVENT 0x0000004C // Battery Upper Limit -#define AON_BATMON_O_BATTUL 0x00000050 +#define AON_BATMON_O_BATTUL 0x00000050 // Battery Lower Limit -#define AON_BATMON_O_BATTLL 0x00000054 +#define AON_BATMON_O_BATTLL 0x00000054 // Temperature Upper Limit -#define AON_BATMON_O_TEMPUL 0x00000058 +#define AON_BATMON_O_TEMPUL 0x00000058 // Temperature Lower Limit -#define AON_BATMON_O_TEMPLL 0x0000005C +#define AON_BATMON_O_TEMPLL 0x0000005C //***************************************************************************** // @@ -108,18 +108,18 @@ // Field: [1] CALC_EN // // Internal. Only to be used through TI provided API. -#define AON_BATMON_CTL_CALC_EN 0x00000002 -#define AON_BATMON_CTL_CALC_EN_BITN 1 -#define AON_BATMON_CTL_CALC_EN_M 0x00000002 -#define AON_BATMON_CTL_CALC_EN_S 1 +#define AON_BATMON_CTL_CALC_EN 0x00000002 +#define AON_BATMON_CTL_CALC_EN_BITN 1 +#define AON_BATMON_CTL_CALC_EN_M 0x00000002 +#define AON_BATMON_CTL_CALC_EN_S 1 // Field: [0] MEAS_EN // // Internal. Only to be used through TI provided API. -#define AON_BATMON_CTL_MEAS_EN 0x00000001 -#define AON_BATMON_CTL_MEAS_EN_BITN 0 -#define AON_BATMON_CTL_MEAS_EN_M 0x00000001 -#define AON_BATMON_CTL_MEAS_EN_S 0 +#define AON_BATMON_CTL_MEAS_EN 0x00000001 +#define AON_BATMON_CTL_MEAS_EN_BITN 0 +#define AON_BATMON_CTL_MEAS_EN_M 0x00000001 +#define AON_BATMON_CTL_MEAS_EN_S 0 //***************************************************************************** // @@ -134,13 +134,13 @@ // 16CYC Internal. Only to be used through TI provided API. // 8CYC Internal. Only to be used through TI provided API. // CONT Internal. Only to be used through TI provided API. -#define AON_BATMON_MEASCFG_PER_W 2 -#define AON_BATMON_MEASCFG_PER_M 0x00000003 -#define AON_BATMON_MEASCFG_PER_S 0 -#define AON_BATMON_MEASCFG_PER_32CYC 0x00000003 -#define AON_BATMON_MEASCFG_PER_16CYC 0x00000002 -#define AON_BATMON_MEASCFG_PER_8CYC 0x00000001 -#define AON_BATMON_MEASCFG_PER_CONT 0x00000000 +#define AON_BATMON_MEASCFG_PER_W 2 +#define AON_BATMON_MEASCFG_PER_M 0x00000003 +#define AON_BATMON_MEASCFG_PER_S 0 +#define AON_BATMON_MEASCFG_PER_32CYC 0x00000003 +#define AON_BATMON_MEASCFG_PER_16CYC 0x00000002 +#define AON_BATMON_MEASCFG_PER_8CYC 0x00000001 +#define AON_BATMON_MEASCFG_PER_CONT 0x00000000 //***************************************************************************** // @@ -150,9 +150,9 @@ // Field: [7:0] CFG // // Internal. Only to be used through TI provided API. -#define AON_BATMON_TEMPP0_CFG_W 8 -#define AON_BATMON_TEMPP0_CFG_M 0x000000FF -#define AON_BATMON_TEMPP0_CFG_S 0 +#define AON_BATMON_TEMPP0_CFG_W 8 +#define AON_BATMON_TEMPP0_CFG_M 0x000000FF +#define AON_BATMON_TEMPP0_CFG_S 0 //***************************************************************************** // @@ -162,9 +162,9 @@ // Field: [5:0] CFG // // Internal. Only to be used through TI provided API. -#define AON_BATMON_TEMPP1_CFG_W 6 -#define AON_BATMON_TEMPP1_CFG_M 0x0000003F -#define AON_BATMON_TEMPP1_CFG_S 0 +#define AON_BATMON_TEMPP1_CFG_W 6 +#define AON_BATMON_TEMPP1_CFG_M 0x0000003F +#define AON_BATMON_TEMPP1_CFG_S 0 //***************************************************************************** // @@ -174,9 +174,9 @@ // Field: [4:0] CFG // // Internal. Only to be used through TI provided API. -#define AON_BATMON_TEMPP2_CFG_W 5 -#define AON_BATMON_TEMPP2_CFG_M 0x0000001F -#define AON_BATMON_TEMPP2_CFG_S 0 +#define AON_BATMON_TEMPP2_CFG_W 5 +#define AON_BATMON_TEMPP2_CFG_M 0x0000001F +#define AON_BATMON_TEMPP2_CFG_S 0 //***************************************************************************** // @@ -186,9 +186,9 @@ // Field: [6:0] CFG // // Internal. Only to be used through TI provided API. -#define AON_BATMON_BATMONP0_CFG_W 7 -#define AON_BATMON_BATMONP0_CFG_M 0x0000007F -#define AON_BATMON_BATMONP0_CFG_S 0 +#define AON_BATMON_BATMONP0_CFG_W 7 +#define AON_BATMON_BATMONP0_CFG_M 0x0000007F +#define AON_BATMON_BATMONP0_CFG_S 0 //***************************************************************************** // @@ -198,9 +198,9 @@ // Field: [5:0] CFG // // Internal. Only to be used through TI provided API. -#define AON_BATMON_BATMONP1_CFG_W 6 -#define AON_BATMON_BATMONP1_CFG_M 0x0000003F -#define AON_BATMON_BATMONP1_CFG_S 0 +#define AON_BATMON_BATMONP1_CFG_W 6 +#define AON_BATMON_BATMONP1_CFG_M 0x0000003F +#define AON_BATMON_BATMONP1_CFG_S 0 //***************************************************************************** // @@ -210,16 +210,16 @@ // Field: [5:4] CFG2 // // Internal. Only to be used through TI provided API. -#define AON_BATMON_IOSTRP0_CFG2_W 2 -#define AON_BATMON_IOSTRP0_CFG2_M 0x00000030 -#define AON_BATMON_IOSTRP0_CFG2_S 4 +#define AON_BATMON_IOSTRP0_CFG2_W 2 +#define AON_BATMON_IOSTRP0_CFG2_M 0x00000030 +#define AON_BATMON_IOSTRP0_CFG2_S 4 // Field: [3:0] CFG1 // // Internal. Only to be used through TI provided API. -#define AON_BATMON_IOSTRP0_CFG1_W 4 -#define AON_BATMON_IOSTRP0_CFG1_M 0x0000000F -#define AON_BATMON_IOSTRP0_CFG1_S 0 +#define AON_BATMON_IOSTRP0_CFG1_W 4 +#define AON_BATMON_IOSTRP0_CFG1_M 0x0000000F +#define AON_BATMON_IOSTRP0_CFG1_S 0 //***************************************************************************** // @@ -229,48 +229,48 @@ // Field: [9] DIS_NOISE_FILTER // // Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER 0x00000200 -#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER_BITN 9 -#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER_M 0x00000200 -#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER_S 9 +#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER 0x00000200 +#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER_BITN 9 +#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER_M 0x00000200 +#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER_S 9 // Field: [8] FALLB // // Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_FALLB 0x00000100 -#define AON_BATMON_FLASHPUMPP0_FALLB_BITN 8 -#define AON_BATMON_FLASHPUMPP0_FALLB_M 0x00000100 -#define AON_BATMON_FLASHPUMPP0_FALLB_S 8 +#define AON_BATMON_FLASHPUMPP0_FALLB 0x00000100 +#define AON_BATMON_FLASHPUMPP0_FALLB_BITN 8 +#define AON_BATMON_FLASHPUMPP0_FALLB_M 0x00000100 +#define AON_BATMON_FLASHPUMPP0_FALLB_S 8 // Field: [7:6] HIGHLIM // // Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_HIGHLIM_W 2 -#define AON_BATMON_FLASHPUMPP0_HIGHLIM_M 0x000000C0 -#define AON_BATMON_FLASHPUMPP0_HIGHLIM_S 6 +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_W 2 +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_M 0x000000C0 +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_S 6 // Field: [5] LOWLIM // // Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_LOWLIM 0x00000020 -#define AON_BATMON_FLASHPUMPP0_LOWLIM_BITN 5 -#define AON_BATMON_FLASHPUMPP0_LOWLIM_M 0x00000020 -#define AON_BATMON_FLASHPUMPP0_LOWLIM_S 5 +#define AON_BATMON_FLASHPUMPP0_LOWLIM 0x00000020 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_BITN 5 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_M 0x00000020 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_S 5 // Field: [4] OVR // // Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_OVR 0x00000010 -#define AON_BATMON_FLASHPUMPP0_OVR_BITN 4 -#define AON_BATMON_FLASHPUMPP0_OVR_M 0x00000010 -#define AON_BATMON_FLASHPUMPP0_OVR_S 4 +#define AON_BATMON_FLASHPUMPP0_OVR 0x00000010 +#define AON_BATMON_FLASHPUMPP0_OVR_BITN 4 +#define AON_BATMON_FLASHPUMPP0_OVR_M 0x00000010 +#define AON_BATMON_FLASHPUMPP0_OVR_S 4 // Field: [3:0] CFG // // Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_CFG_W 4 -#define AON_BATMON_FLASHPUMPP0_CFG_M 0x0000000F -#define AON_BATMON_FLASHPUMPP0_CFG_S 0 +#define AON_BATMON_FLASHPUMPP0_CFG_W 4 +#define AON_BATMON_FLASHPUMPP0_CFG_M 0x0000000F +#define AON_BATMON_FLASHPUMPP0_CFG_S 0 //***************************************************************************** // @@ -285,9 +285,9 @@ // ... // 0x3: 3V + fractional part // 0x4: 4V + fractional part -#define AON_BATMON_BAT_INT_W 3 -#define AON_BATMON_BAT_INT_M 0x00000700 -#define AON_BATMON_BAT_INT_S 8 +#define AON_BATMON_BAT_INT_W 3 +#define AON_BATMON_BAT_INT_M 0x00000700 +#define AON_BATMON_BAT_INT_S 8 // Field: [7:0] FRAC // @@ -302,9 +302,9 @@ // 0xA0: 1/2 + 1/8 = .625V // ... // 0xFF: Max -#define AON_BATMON_BAT_FRAC_W 8 -#define AON_BATMON_BAT_FRAC_M 0x000000FF -#define AON_BATMON_BAT_FRAC_S 0 +#define AON_BATMON_BAT_FRAC_W 8 +#define AON_BATMON_BAT_FRAC_M 0x000000FF +#define AON_BATMON_BAT_FRAC_S 0 //***************************************************************************** // @@ -318,10 +318,10 @@ // 1: New battery voltage is present. // // Write 1 to clear the status. -#define AON_BATMON_BATUPD_STAT 0x00000001 -#define AON_BATMON_BATUPD_STAT_BITN 0 -#define AON_BATMON_BATUPD_STAT_M 0x00000001 -#define AON_BATMON_BATUPD_STAT_S 0 +#define AON_BATMON_BATUPD_STAT 0x00000001 +#define AON_BATMON_BATUPD_STAT_BITN 0 +#define AON_BATMON_BATUPD_STAT_M 0x00000001 +#define AON_BATMON_BATUPD_STAT_S 0 //***************************************************************************** // @@ -341,9 +341,9 @@ // 0x1B: 27C // 0x55: 85C // 0xFF: Max value -#define AON_BATMON_TEMP_INT_W 9 -#define AON_BATMON_TEMP_INT_M 0x0001FF00 -#define AON_BATMON_TEMP_INT_S 8 +#define AON_BATMON_TEMP_INT_W 9 +#define AON_BATMON_TEMP_INT_M 0x0001FF00 +#define AON_BATMON_TEMP_INT_S 8 //***************************************************************************** // @@ -357,10 +357,10 @@ // 1: New temperature is present. // // Write 1 to clear the status. -#define AON_BATMON_TEMPUPD_STAT 0x00000001 -#define AON_BATMON_TEMPUPD_STAT_BITN 0 -#define AON_BATMON_TEMPUPD_STAT_M 0x00000001 -#define AON_BATMON_TEMPUPD_STAT_S 0 +#define AON_BATMON_TEMPUPD_STAT 0x00000001 +#define AON_BATMON_TEMPUPD_STAT_BITN 0 +#define AON_BATMON_TEMPUPD_STAT_M 0x00000001 +#define AON_BATMON_TEMPUPD_STAT_S 0 //***************************************************************************** // @@ -371,55 +371,55 @@ // // 1: EVENT.TEMP_UPDATE contributes to combined event from BATMON // 0: EVENT.TEMP_UPDATE does not contribute to combined event from BATMON -#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK 0x00000020 -#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK_BITN 5 -#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK_M 0x00000020 -#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK_S 5 +#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK 0x00000020 +#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK_BITN 5 +#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK_M 0x00000020 +#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK_S 5 // Field: [4] BATT_UPDATE_MASK // // 1: EVENT.BATT_UPDATE contributes to combined event from BATMON // 0: EVENT.BATT_UPDATE does not contribute to combined event from BATMON -#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK 0x00000010 -#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK_BITN 4 -#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK_M 0x00000010 -#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK_S 4 +#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK 0x00000010 +#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK_BITN 4 +#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK_M 0x00000010 +#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK_S 4 // Field: [3] TEMP_BELOW_LL_MASK // // 1: EVENT.TEMP_BELOW_LL contributes to combined event from BATMON // 0: EVENT.TEMP_BELOW_LL does not contribute to combined event from BATMON -#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK 0x00000008 -#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK_BITN 3 -#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK_M 0x00000008 -#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK_S 3 +#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK 0x00000008 +#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK_BITN 3 +#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK_M 0x00000008 +#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK_S 3 // Field: [2] TEMP_OVER_UL_MASK // // 1: EVENT.TEMP_OVER_UL contributes to combined event from BATMON // 0: EVENT.TEMP_OVER_UL does not contribute to combined event from BATMON -#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK 0x00000004 -#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK_BITN 2 -#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK_M 0x00000004 -#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK_S 2 +#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK 0x00000004 +#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK_BITN 2 +#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK_M 0x00000004 +#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK_S 2 // Field: [1] BATT_BELOW_LL_MASK // // 1: EVENT.BATT_BELOW_LL contributes to combined event from BATMON // 0: EVENT.BATT_BELOW_LL does not contribute to combined event from BATMON -#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK 0x00000002 -#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK_BITN 1 -#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK_M 0x00000002 -#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK_S 1 +#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK 0x00000002 +#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK_BITN 1 +#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK_M 0x00000002 +#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK_S 1 // Field: [0] BATT_OVER_UL_MASK // // 1: EVENT.BATT_OVER_UL contributes to combined event from BATMON // 0: EVENT.BATT_OVER_UL does not contribute to combined event from BATMON -#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK 0x00000001 -#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK_BITN 0 -#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK_M 0x00000001 -#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK_S 0 +#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK 0x00000001 +#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK_BITN 0 +#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK_M 0x00000001 +#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK_S 0 //***************************************************************************** // @@ -429,18 +429,18 @@ // Field: [5] TEMP_UPDATE // // Alias to TEMPUPD.STAT -#define AON_BATMON_EVENT_TEMP_UPDATE 0x00000020 -#define AON_BATMON_EVENT_TEMP_UPDATE_BITN 5 -#define AON_BATMON_EVENT_TEMP_UPDATE_M 0x00000020 -#define AON_BATMON_EVENT_TEMP_UPDATE_S 5 +#define AON_BATMON_EVENT_TEMP_UPDATE 0x00000020 +#define AON_BATMON_EVENT_TEMP_UPDATE_BITN 5 +#define AON_BATMON_EVENT_TEMP_UPDATE_M 0x00000020 +#define AON_BATMON_EVENT_TEMP_UPDATE_S 5 // Field: [4] BATT_UPDATE // // Alias to BATUPD.STAT -#define AON_BATMON_EVENT_BATT_UPDATE 0x00000010 -#define AON_BATMON_EVENT_BATT_UPDATE_BITN 4 -#define AON_BATMON_EVENT_BATT_UPDATE_M 0x00000010 -#define AON_BATMON_EVENT_BATT_UPDATE_S 4 +#define AON_BATMON_EVENT_BATT_UPDATE 0x00000010 +#define AON_BATMON_EVENT_BATT_UPDATE_BITN 4 +#define AON_BATMON_EVENT_BATT_UPDATE_M 0x00000010 +#define AON_BATMON_EVENT_BATT_UPDATE_S 4 // Field: [3] TEMP_BELOW_LL // @@ -450,10 +450,10 @@ // Write: // 1: Clears the flag // 0: No change in the flag -#define AON_BATMON_EVENT_TEMP_BELOW_LL 0x00000008 -#define AON_BATMON_EVENT_TEMP_BELOW_LL_BITN 3 -#define AON_BATMON_EVENT_TEMP_BELOW_LL_M 0x00000008 -#define AON_BATMON_EVENT_TEMP_BELOW_LL_S 3 +#define AON_BATMON_EVENT_TEMP_BELOW_LL 0x00000008 +#define AON_BATMON_EVENT_TEMP_BELOW_LL_BITN 3 +#define AON_BATMON_EVENT_TEMP_BELOW_LL_M 0x00000008 +#define AON_BATMON_EVENT_TEMP_BELOW_LL_S 3 // Field: [2] TEMP_OVER_UL // @@ -463,10 +463,10 @@ // Write: // 1: Clears the flag // 0: No change in the flag -#define AON_BATMON_EVENT_TEMP_OVER_UL 0x00000004 -#define AON_BATMON_EVENT_TEMP_OVER_UL_BITN 2 -#define AON_BATMON_EVENT_TEMP_OVER_UL_M 0x00000004 -#define AON_BATMON_EVENT_TEMP_OVER_UL_S 2 +#define AON_BATMON_EVENT_TEMP_OVER_UL 0x00000004 +#define AON_BATMON_EVENT_TEMP_OVER_UL_BITN 2 +#define AON_BATMON_EVENT_TEMP_OVER_UL_M 0x00000004 +#define AON_BATMON_EVENT_TEMP_OVER_UL_S 2 // Field: [1] BATT_BELOW_LL // @@ -476,10 +476,10 @@ // Write: // 1: Clears the flag // 0: No change in the flag -#define AON_BATMON_EVENT_BATT_BELOW_LL 0x00000002 -#define AON_BATMON_EVENT_BATT_BELOW_LL_BITN 1 -#define AON_BATMON_EVENT_BATT_BELOW_LL_M 0x00000002 -#define AON_BATMON_EVENT_BATT_BELOW_LL_S 1 +#define AON_BATMON_EVENT_BATT_BELOW_LL 0x00000002 +#define AON_BATMON_EVENT_BATT_BELOW_LL_BITN 1 +#define AON_BATMON_EVENT_BATT_BELOW_LL_M 0x00000002 +#define AON_BATMON_EVENT_BATT_BELOW_LL_S 1 // Field: [0] BATT_OVER_UL // @@ -489,10 +489,10 @@ // Write: // 1: Clears the flag // 0: No change in the flag -#define AON_BATMON_EVENT_BATT_OVER_UL 0x00000001 -#define AON_BATMON_EVENT_BATT_OVER_UL_BITN 0 -#define AON_BATMON_EVENT_BATT_OVER_UL_M 0x00000001 -#define AON_BATMON_EVENT_BATT_OVER_UL_S 0 +#define AON_BATMON_EVENT_BATT_OVER_UL 0x00000001 +#define AON_BATMON_EVENT_BATT_OVER_UL_BITN 0 +#define AON_BATMON_EVENT_BATT_OVER_UL_M 0x00000001 +#define AON_BATMON_EVENT_BATT_OVER_UL_S 0 //***************************************************************************** // @@ -507,9 +507,9 @@ // ... // 0x3: 3V + fractional part // 0x4: 4V + fractional part -#define AON_BATMON_BATTUL_INT_W 3 -#define AON_BATMON_BATTUL_INT_M 0x00000700 -#define AON_BATMON_BATTUL_INT_S 8 +#define AON_BATMON_BATTUL_INT_W 3 +#define AON_BATMON_BATTUL_INT_M 0x00000700 +#define AON_BATMON_BATTUL_INT_S 8 // Field: [7:0] FRAC // @@ -524,9 +524,9 @@ // 0xA0: 1/2 + 1/8 = .625V // ... // 0xFF: Max -#define AON_BATMON_BATTUL_FRAC_W 8 -#define AON_BATMON_BATTUL_FRAC_M 0x000000FF -#define AON_BATMON_BATTUL_FRAC_S 0 +#define AON_BATMON_BATTUL_FRAC_W 8 +#define AON_BATMON_BATTUL_FRAC_M 0x000000FF +#define AON_BATMON_BATTUL_FRAC_S 0 //***************************************************************************** // @@ -541,9 +541,9 @@ // ... // 0x3: 3V + fractional part // 0x4: 4V + fractional part -#define AON_BATMON_BATTLL_INT_W 3 -#define AON_BATMON_BATTLL_INT_M 0x00000700 -#define AON_BATMON_BATTLL_INT_S 8 +#define AON_BATMON_BATTLL_INT_W 3 +#define AON_BATMON_BATTLL_INT_M 0x00000700 +#define AON_BATMON_BATTLL_INT_S 8 // Field: [7:0] FRAC // @@ -558,9 +558,9 @@ // 0xA0: 1/2 + 1/8 = .625V // ... // 0xFF: Max -#define AON_BATMON_BATTLL_FRAC_W 8 -#define AON_BATMON_BATTLL_FRAC_M 0x000000FF -#define AON_BATMON_BATTLL_FRAC_S 0 +#define AON_BATMON_BATTLL_FRAC_W 8 +#define AON_BATMON_BATTLL_FRAC_M 0x000000FF +#define AON_BATMON_BATTLL_FRAC_S 0 //***************************************************************************** // @@ -580,9 +580,9 @@ // 0x1B: 27C // 0x55: 85C // 0xFF: Max value -#define AON_BATMON_TEMPUL_INT_W 9 -#define AON_BATMON_TEMPUL_INT_M 0x0001FF00 -#define AON_BATMON_TEMPUL_INT_S 8 +#define AON_BATMON_TEMPUL_INT_W 9 +#define AON_BATMON_TEMPUL_INT_M 0x0001FF00 +#define AON_BATMON_TEMPUL_INT_S 8 // Field: [7:6] FRAC // @@ -606,9 +606,9 @@ // 111111111,01 = (-1+0,25) = -0,75 // 111111111,00 = (-1+0,00) = -1,00 // 111111110,11 = (-2+0,75) = -1,25 -#define AON_BATMON_TEMPUL_FRAC_W 2 -#define AON_BATMON_TEMPUL_FRAC_M 0x000000C0 -#define AON_BATMON_TEMPUL_FRAC_S 6 +#define AON_BATMON_TEMPUL_FRAC_W 2 +#define AON_BATMON_TEMPUL_FRAC_M 0x000000C0 +#define AON_BATMON_TEMPUL_FRAC_S 6 //***************************************************************************** // @@ -628,9 +628,9 @@ // 0x1B: 27C // 0x55: 85C // 0xFF: Max value -#define AON_BATMON_TEMPLL_INT_W 9 -#define AON_BATMON_TEMPLL_INT_M 0x0001FF00 -#define AON_BATMON_TEMPLL_INT_S 8 +#define AON_BATMON_TEMPLL_INT_W 9 +#define AON_BATMON_TEMPLL_INT_M 0x0001FF00 +#define AON_BATMON_TEMPLL_INT_S 8 // Field: [7:6] FRAC // @@ -654,9 +654,8 @@ // 111111111,01 = (-1+0,25) = -0,75 // 111111111,00 = (-1+0,00) = -1,00 // 111111110,11 = (-2+0,75) = -1,25 -#define AON_BATMON_TEMPLL_FRAC_W 2 -#define AON_BATMON_TEMPLL_FRAC_M 0x000000C0 -#define AON_BATMON_TEMPLL_FRAC_S 6 - +#define AON_BATMON_TEMPLL_FRAC_W 2 +#define AON_BATMON_TEMPLL_FRAC_M 0x000000C0 +#define AON_BATMON_TEMPLL_FRAC_S 6 #endif // __AON_BATMON__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_event.h index 1f070c8..4abfbe9 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_event.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_event.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aon_event_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aon_event_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AON_EVENT_H__ #define __HW_AON_EVENT_H__ @@ -44,16 +44,16 @@ // //***************************************************************************** // Wake-up Selector For MCU -#define AON_EVENT_O_MCUWUSEL 0x00000000 +#define AON_EVENT_O_MCUWUSEL 0x00000000 // Wake-up Selector For MCU -#define AON_EVENT_O_MCUWUSEL1 0x00000004 +#define AON_EVENT_O_MCUWUSEL1 0x00000004 // Event Selector For MCU Event Fabric -#define AON_EVENT_O_EVTOMCUSEL 0x00000008 +#define AON_EVENT_O_EVTOMCUSEL 0x00000008 // RTC Capture Event Selector For AON_RTC -#define AON_EVENT_O_RTCSEL 0x0000000C +#define AON_EVENT_O_RTCSEL 0x0000000C //***************************************************************************** // @@ -113,43 +113,43 @@ // IOEV_MCU_WU Edge detect IO event from the DIO(s) which have // enabled contribution to IOEV_MCU_WU in // [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] -#define AON_EVENT_MCUWUSEL_WU3_EV_W 6 -#define AON_EVENT_MCUWUSEL_WU3_EV_M 0x3F000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_S 24 -#define AON_EVENT_MCUWUSEL_WU3_EV_NONE 0x3F000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC_N 0x38000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC 0x37000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_VOLT 0x36000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP 0x35000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER1_EV 0x34000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER0_EV 0x33000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TDC_DONE 0x32000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_ADC_DONE 0x31000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB 0x30000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPA 0x2F000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV2 0x2E000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV1 0x2D000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV0 0x2C000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_JTAG 0x2B000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_UPD 0x2A000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_COMB_DLY 0x29000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2_DLY 0x28000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1_DLY 0x27000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0_DLY 0x26000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2 0x25000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1 0x24000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0 0x23000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD 0x20000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_COMBINED 0x09000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP_LL 0x08000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP_UL 0x07000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_BATT_LL 0x06000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_BATT_UL 0x05000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV3 0x04000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV2 0x03000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV1 0x02000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV0 0x01000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_IOEV_MCU_WU 0x00000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU3_EV_M 0x3F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_S 24 +#define AON_EVENT_MCUWUSEL_WU3_EV_NONE 0x3F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC_N 0x38000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC 0x37000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_VOLT 0x36000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP 0x35000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER1_EV 0x34000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER0_EV 0x33000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TDC_DONE 0x32000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_ADC_DONE 0x31000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB 0x30000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPA 0x2F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV2 0x2E000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV1 0x2D000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV0 0x2C000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_JTAG 0x2B000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_UPD 0x2A000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_COMB_DLY 0x29000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2_DLY 0x28000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1_DLY 0x27000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0_DLY 0x26000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2 0x25000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1 0x24000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0 0x23000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD 0x20000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_COMBINED 0x09000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP_LL 0x08000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP_UL 0x07000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_BATT_LL 0x06000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_BATT_UL 0x05000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV3 0x04000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV2 0x03000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV1 0x02000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV0 0x01000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_IOEV_MCU_WU 0x00000000 // Field: [21:16] WU2_EV // @@ -204,43 +204,43 @@ // IOEV_MCU_WU Edge detect IO event from the DIO(s) which have // enabled contribution to IOEV_MCU_WU in // [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] -#define AON_EVENT_MCUWUSEL_WU2_EV_W 6 -#define AON_EVENT_MCUWUSEL_WU2_EV_M 0x003F0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_S 16 -#define AON_EVENT_MCUWUSEL_WU2_EV_NONE 0x003F0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000 -#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_VOLT 0x00360000 -#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP 0x00350000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB 0x00300000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPA 0x002F0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV2 0x002E0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV1 0x002D0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV0 0x002C0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_JTAG 0x002B0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_UPD 0x002A0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2 0x00250000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1 0x00240000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0 0x00230000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD 0x00200000 -#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_COMBINED 0x00090000 -#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP_LL 0x00080000 -#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP_UL 0x00070000 -#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_BATT_LL 0x00060000 -#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_BATT_UL 0x00050000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV3 0x00040000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV2 0x00030000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV1 0x00020000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV0 0x00010000 -#define AON_EVENT_MCUWUSEL_WU2_EV_IOEV_MCU_WU 0x00000000 +#define AON_EVENT_MCUWUSEL_WU2_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU2_EV_M 0x003F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_S 16 +#define AON_EVENT_MCUWUSEL_WU2_EV_NONE 0x003F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_JTAG 0x002B0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2 0x00250000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1 0x00240000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0 0x00230000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD 0x00200000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_COMBINED 0x00090000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP_LL 0x00080000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP_UL 0x00070000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_BATT_LL 0x00060000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_BATT_UL 0x00050000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV3 0x00040000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV2 0x00030000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV1 0x00020000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV0 0x00010000 +#define AON_EVENT_MCUWUSEL_WU2_EV_IOEV_MCU_WU 0x00000000 // Field: [13:8] WU1_EV // @@ -295,43 +295,43 @@ // IOEV_MCU_WU Edge detect IO event from the DIO(s) which have // enabled contribution to IOEV_MCU_WU in // [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] -#define AON_EVENT_MCUWUSEL_WU1_EV_W 6 -#define AON_EVENT_MCUWUSEL_WU1_EV_M 0x00003F00 -#define AON_EVENT_MCUWUSEL_WU1_EV_S 8 -#define AON_EVENT_MCUWUSEL_WU1_EV_NONE 0x00003F00 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700 -#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_VOLT 0x00003600 -#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP 0x00003500 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB 0x00003000 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPA 0x00002F00 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV2 0x00002E00 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV1 0x00002D00 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV0 0x00002C00 -#define AON_EVENT_MCUWUSEL_WU1_EV_JTAG 0x00002B00 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_UPD 0x00002A00 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2 0x00002500 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1 0x00002400 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0 0x00002300 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD 0x00002000 -#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_COMBINED 0x00000900 -#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP_LL 0x00000800 -#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP_UL 0x00000700 -#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_BATT_LL 0x00000600 -#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_BATT_UL 0x00000500 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV3 0x00000400 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV2 0x00000300 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV1 0x00000200 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV0 0x00000100 -#define AON_EVENT_MCUWUSEL_WU1_EV_IOEV_MCU_WU 0x00000000 +#define AON_EVENT_MCUWUSEL_WU1_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU1_EV_M 0x00003F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_S 8 +#define AON_EVENT_MCUWUSEL_WU1_EV_NONE 0x00003F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_MCUWUSEL_WU1_EV_JTAG 0x00002B00 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2 0x00002500 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1 0x00002400 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0 0x00002300 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD 0x00002000 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_COMBINED 0x00000900 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP_LL 0x00000800 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP_UL 0x00000700 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_BATT_LL 0x00000600 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_BATT_UL 0x00000500 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV3 0x00000400 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV2 0x00000300 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV1 0x00000200 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV0 0x00000100 +#define AON_EVENT_MCUWUSEL_WU1_EV_IOEV_MCU_WU 0x00000000 // Field: [5:0] WU0_EV // @@ -386,43 +386,43 @@ // IOEV_MCU_WU Edge detect IO event from the DIO(s) which have // enabled contribution to IOEV_MCU_WU in // [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] -#define AON_EVENT_MCUWUSEL_WU0_EV_W 6 -#define AON_EVENT_MCUWUSEL_WU0_EV_M 0x0000003F -#define AON_EVENT_MCUWUSEL_WU0_EV_S 0 -#define AON_EVENT_MCUWUSEL_WU0_EV_NONE 0x0000003F -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037 -#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_VOLT 0x00000036 -#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP 0x00000035 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB 0x00000030 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPA 0x0000002F -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV2 0x0000002E -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV1 0x0000002D -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV0 0x0000002C -#define AON_EVENT_MCUWUSEL_WU0_EV_JTAG 0x0000002B -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_UPD 0x0000002A -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2 0x00000025 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1 0x00000024 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0 0x00000023 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD 0x00000020 -#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_COMBINED 0x00000009 -#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP_LL 0x00000008 -#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP_UL 0x00000007 -#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_BATT_LL 0x00000006 -#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_BATT_UL 0x00000005 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV3 0x00000004 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV2 0x00000003 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV1 0x00000002 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV0 0x00000001 -#define AON_EVENT_MCUWUSEL_WU0_EV_IOEV_MCU_WU 0x00000000 +#define AON_EVENT_MCUWUSEL_WU0_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU0_EV_M 0x0000003F +#define AON_EVENT_MCUWUSEL_WU0_EV_S 0 +#define AON_EVENT_MCUWUSEL_WU0_EV_NONE 0x0000003F +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_MCUWUSEL_WU0_EV_JTAG 0x0000002B +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_UPD 0x0000002A +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2 0x00000025 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1 0x00000024 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0 0x00000023 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD 0x00000020 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_COMBINED 0x00000009 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP_LL 0x00000008 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP_UL 0x00000007 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_BATT_LL 0x00000006 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_BATT_UL 0x00000005 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV3 0x00000004 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV2 0x00000003 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV1 0x00000002 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV0 0x00000001 +#define AON_EVENT_MCUWUSEL_WU0_EV_IOEV_MCU_WU 0x00000000 //***************************************************************************** // @@ -482,43 +482,43 @@ // IOEV_MCU_WU Edge detect IO event from the DIO(s) which have // enabled contribution to IOEV_MCU_WU in // [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] -#define AON_EVENT_MCUWUSEL1_WU7_EV_W 6 -#define AON_EVENT_MCUWUSEL1_WU7_EV_M 0x3F000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_S 24 -#define AON_EVENT_MCUWUSEL1_WU7_EV_NONE 0x3F000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPB_ASYNC_N 0x38000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPB_ASYNC 0x37000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_VOLT 0x36000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_TEMP 0x35000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER1_EV 0x34000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER0_EV 0x33000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TDC_DONE 0x32000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_ADC_DONE 0x31000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPB 0x30000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPA 0x2F000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_SWEV2 0x2E000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_SWEV1 0x2D000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_SWEV0 0x2C000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_JTAG 0x2B000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_UPD 0x2A000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_COMB_DLY 0x29000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH2_DLY 0x28000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH1_DLY 0x27000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH0_DLY 0x26000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH2 0x25000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH1 0x24000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH0 0x23000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_PAD 0x20000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_COMBINED 0x09000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_TEMP_LL 0x08000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_TEMP_UL 0x07000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_BATT_LL 0x06000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_BATT_UL 0x05000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV3 0x04000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV2 0x03000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV1 0x02000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV0 0x01000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_IOEV_MCU_WU 0x00000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_W 6 +#define AON_EVENT_MCUWUSEL1_WU7_EV_M 0x3F000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_S 24 +#define AON_EVENT_MCUWUSEL1_WU7_EV_NONE 0x3F000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPB_ASYNC_N 0x38000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPB_ASYNC 0x37000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_VOLT 0x36000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_TEMP 0x35000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER1_EV 0x34000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER0_EV 0x33000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TDC_DONE 0x32000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_ADC_DONE 0x31000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPB 0x30000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPA 0x2F000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_SWEV2 0x2E000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_SWEV1 0x2D000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_SWEV0 0x2C000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_JTAG 0x2B000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_UPD 0x2A000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_COMB_DLY 0x29000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH2_DLY 0x28000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH1_DLY 0x27000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH0_DLY 0x26000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH2 0x25000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH1 0x24000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH0 0x23000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_PAD 0x20000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_COMBINED 0x09000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_TEMP_LL 0x08000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_TEMP_UL 0x07000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_BATT_LL 0x06000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_BATT_UL 0x05000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV3 0x04000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV2 0x03000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV1 0x02000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV0 0x01000000 +#define AON_EVENT_MCUWUSEL1_WU7_EV_IOEV_MCU_WU 0x00000000 // Field: [21:16] WU6_EV // @@ -573,43 +573,43 @@ // IOEV_MCU_WU Edge detect IO event from the DIO(s) which have // enabled contribution to IOEV_MCU_WU in // [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] -#define AON_EVENT_MCUWUSEL1_WU6_EV_W 6 -#define AON_EVENT_MCUWUSEL1_WU6_EV_M 0x003F0000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_S 16 -#define AON_EVENT_MCUWUSEL1_WU6_EV_NONE 0x003F0000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPB_ASYNC_N 0x00380000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPB_ASYNC 0x00370000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_VOLT 0x00360000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_TEMP 0x00350000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER1_EV 0x00340000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER0_EV 0x00330000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TDC_DONE 0x00320000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_ADC_DONE 0x00310000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPB 0x00300000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPA 0x002F0000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_SWEV2 0x002E0000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_SWEV1 0x002D0000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_SWEV0 0x002C0000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_JTAG 0x002B0000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_UPD 0x002A0000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_COMB_DLY 0x00290000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH2_DLY 0x00280000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH1_DLY 0x00270000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH0_DLY 0x00260000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH2 0x00250000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH1 0x00240000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH0 0x00230000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_PAD 0x00200000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_COMBINED 0x00090000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_TEMP_LL 0x00080000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_TEMP_UL 0x00070000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_BATT_LL 0x00060000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_BATT_UL 0x00050000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV3 0x00040000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV2 0x00030000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV1 0x00020000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV0 0x00010000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_IOEV_MCU_WU 0x00000000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_W 6 +#define AON_EVENT_MCUWUSEL1_WU6_EV_M 0x003F0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_S 16 +#define AON_EVENT_MCUWUSEL1_WU6_EV_NONE 0x003F0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_JTAG 0x002B0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH2 0x00250000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH1 0x00240000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH0 0x00230000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_PAD 0x00200000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_COMBINED 0x00090000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_TEMP_LL 0x00080000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_TEMP_UL 0x00070000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_BATT_LL 0x00060000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_BATT_UL 0x00050000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV3 0x00040000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV2 0x00030000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV1 0x00020000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV0 0x00010000 +#define AON_EVENT_MCUWUSEL1_WU6_EV_IOEV_MCU_WU 0x00000000 // Field: [13:8] WU5_EV // @@ -664,43 +664,43 @@ // IOEV_MCU_WU Edge detect IO event from the DIO(s) which have // enabled contribution to IOEV_MCU_WU in // [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] -#define AON_EVENT_MCUWUSEL1_WU5_EV_W 6 -#define AON_EVENT_MCUWUSEL1_WU5_EV_M 0x00003F00 -#define AON_EVENT_MCUWUSEL1_WU5_EV_S 8 -#define AON_EVENT_MCUWUSEL1_WU5_EV_NONE 0x00003F00 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPB_ASYNC_N 0x00003800 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPB_ASYNC 0x00003700 -#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_VOLT 0x00003600 -#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_TEMP 0x00003500 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER1_EV 0x00003400 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER0_EV 0x00003300 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TDC_DONE 0x00003200 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_ADC_DONE 0x00003100 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPB 0x00003000 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPA 0x00002F00 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_SWEV2 0x00002E00 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_SWEV1 0x00002D00 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_SWEV0 0x00002C00 -#define AON_EVENT_MCUWUSEL1_WU5_EV_JTAG 0x00002B00 -#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_UPD 0x00002A00 -#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_COMB_DLY 0x00002900 -#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH2_DLY 0x00002800 -#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH1_DLY 0x00002700 -#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH0_DLY 0x00002600 -#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH2 0x00002500 -#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH1 0x00002400 -#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH0 0x00002300 -#define AON_EVENT_MCUWUSEL1_WU5_EV_PAD 0x00002000 -#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_COMBINED 0x00000900 -#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_TEMP_LL 0x00000800 -#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_TEMP_UL 0x00000700 -#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_BATT_LL 0x00000600 -#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_BATT_UL 0x00000500 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV3 0x00000400 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV2 0x00000300 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV1 0x00000200 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV0 0x00000100 -#define AON_EVENT_MCUWUSEL1_WU5_EV_IOEV_MCU_WU 0x00000000 +#define AON_EVENT_MCUWUSEL1_WU5_EV_W 6 +#define AON_EVENT_MCUWUSEL1_WU5_EV_M 0x00003F00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_S 8 +#define AON_EVENT_MCUWUSEL1_WU5_EV_NONE 0x00003F00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_JTAG 0x00002B00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH2 0x00002500 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH1 0x00002400 +#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH0 0x00002300 +#define AON_EVENT_MCUWUSEL1_WU5_EV_PAD 0x00002000 +#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_COMBINED 0x00000900 +#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_TEMP_LL 0x00000800 +#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_TEMP_UL 0x00000700 +#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_BATT_LL 0x00000600 +#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_BATT_UL 0x00000500 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV3 0x00000400 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV2 0x00000300 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV1 0x00000200 +#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV0 0x00000100 +#define AON_EVENT_MCUWUSEL1_WU5_EV_IOEV_MCU_WU 0x00000000 // Field: [5:0] WU4_EV // @@ -755,43 +755,43 @@ // IOEV_MCU_WU Edge detect IO event from the DIO(s) which have // enabled contribution to IOEV_MCU_WU in // [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] -#define AON_EVENT_MCUWUSEL1_WU4_EV_W 6 -#define AON_EVENT_MCUWUSEL1_WU4_EV_M 0x0000003F -#define AON_EVENT_MCUWUSEL1_WU4_EV_S 0 -#define AON_EVENT_MCUWUSEL1_WU4_EV_NONE 0x0000003F -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPB_ASYNC_N 0x00000038 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPB_ASYNC 0x00000037 -#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_VOLT 0x00000036 -#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_TEMP 0x00000035 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER1_EV 0x00000034 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER0_EV 0x00000033 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TDC_DONE 0x00000032 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_ADC_DONE 0x00000031 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPB 0x00000030 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPA 0x0000002F -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_SWEV2 0x0000002E -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_SWEV1 0x0000002D -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_SWEV0 0x0000002C -#define AON_EVENT_MCUWUSEL1_WU4_EV_JTAG 0x0000002B -#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_UPD 0x0000002A -#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_COMB_DLY 0x00000029 -#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH2_DLY 0x00000028 -#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH1_DLY 0x00000027 -#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH0_DLY 0x00000026 -#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH2 0x00000025 -#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH1 0x00000024 -#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH0 0x00000023 -#define AON_EVENT_MCUWUSEL1_WU4_EV_PAD 0x00000020 -#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_COMBINED 0x00000009 -#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_TEMP_LL 0x00000008 -#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_TEMP_UL 0x00000007 -#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_BATT_LL 0x00000006 -#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_BATT_UL 0x00000005 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV3 0x00000004 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV2 0x00000003 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV1 0x00000002 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV0 0x00000001 -#define AON_EVENT_MCUWUSEL1_WU4_EV_IOEV_MCU_WU 0x00000000 +#define AON_EVENT_MCUWUSEL1_WU4_EV_W 6 +#define AON_EVENT_MCUWUSEL1_WU4_EV_M 0x0000003F +#define AON_EVENT_MCUWUSEL1_WU4_EV_S 0 +#define AON_EVENT_MCUWUSEL1_WU4_EV_NONE 0x0000003F +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_MCUWUSEL1_WU4_EV_JTAG 0x0000002B +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_UPD 0x0000002A +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH2 0x00000025 +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH1 0x00000024 +#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH0 0x00000023 +#define AON_EVENT_MCUWUSEL1_WU4_EV_PAD 0x00000020 +#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_COMBINED 0x00000009 +#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_TEMP_LL 0x00000008 +#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_TEMP_UL 0x00000007 +#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_BATT_LL 0x00000006 +#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_BATT_UL 0x00000005 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV3 0x00000004 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV2 0x00000003 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV1 0x00000002 +#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV0 0x00000001 +#define AON_EVENT_MCUWUSEL1_WU4_EV_IOEV_MCU_WU 0x00000000 //***************************************************************************** // @@ -849,43 +849,43 @@ // IOEV_AON_PROG2 Edge detect IO event from the DIO(s) which have // enabled contribution to IOEV_AON_PROG2 in // [MCU_IOC:IOCFGx.IOEV_AON_PROG2_EN] -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_W 6 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M 0x003F0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S 16 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_NONE 0x003F0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC_N 0x00380000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC 0x00370000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_VOLT 0x00360000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP 0x00350000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER1_EV 0x00340000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER0_EV 0x00330000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TDC_DONE 0x00320000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_ADC_DONE 0x00310000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB 0x00300000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPA 0x002F0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV2 0x002E0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV1 0x002D0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV0 0x002C0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_JTAG 0x002B0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_UPD 0x002A0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_COMB_DLY 0x00290000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2_DLY 0x00280000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1_DLY 0x00270000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0_DLY 0x00260000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2 0x00250000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1 0x00240000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0 0x00230000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD 0x00200000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_COMBINED 0x00090000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP_LL 0x00080000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP_UL 0x00070000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_BATT_LL 0x00060000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_BATT_UL 0x00050000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV3 0x00040000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV2 0x00030000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV1 0x00020000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV0 0x00010000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_IOEV_AON_PROG2 0x00000000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M 0x003F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S 16 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_NONE 0x003F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_JTAG 0x002B0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2 0x00250000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1 0x00240000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0 0x00230000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD 0x00200000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_COMBINED 0x00090000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP_LL 0x00080000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP_UL 0x00070000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_BATT_LL 0x00060000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_BATT_UL 0x00050000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV3 0x00040000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV2 0x00030000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV1 0x00020000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV0 0x00010000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_IOEV_AON_PROG2 0x00000000 // Field: [13:8] AON_PROG1_EV // @@ -929,43 +929,43 @@ // IOEV_AON_PROG1 Edge detect IO event from the DIO(s) which have // enabled contribution to IOEV_AON_PROG1 in // [MCU_IOC:IOCFGx.IOEV_AON_PROG1_EN] -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_W 6 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M 0x00003F00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S 8 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_NONE 0x00003F00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC_N 0x00003800 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC 0x00003700 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_VOLT 0x00003600 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP 0x00003500 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER1_EV 0x00003400 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER0_EV 0x00003300 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TDC_DONE 0x00003200 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_ADC_DONE 0x00003100 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB 0x00003000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPA 0x00002F00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV2 0x00002E00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV1 0x00002D00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV0 0x00002C00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_JTAG 0x00002B00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_UPD 0x00002A00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_COMB_DLY 0x00002900 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2_DLY 0x00002800 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1_DLY 0x00002700 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0_DLY 0x00002600 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2 0x00002500 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1 0x00002400 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0 0x00002300 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD 0x00002000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_COMBINED 0x00000900 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP_LL 0x00000800 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP_UL 0x00000700 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_BATT_LL 0x00000600 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_BATT_UL 0x00000500 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV3 0x00000400 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV2 0x00000300 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV1 0x00000200 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV0 0x00000100 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_IOEV_AON_PROG1 0x00000000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M 0x00003F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S 8 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_NONE 0x00003F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_JTAG 0x00002B00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2 0x00002500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1 0x00002400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0 0x00002300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD 0x00002000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_COMBINED 0x00000900 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP_LL 0x00000800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP_UL 0x00000700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_BATT_LL 0x00000600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_BATT_UL 0x00000500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV3 0x00000400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV2 0x00000300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV1 0x00000200 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV0 0x00000100 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_IOEV_AON_PROG1 0x00000000 // Field: [5:0] AON_PROG0_EV // @@ -1009,43 +1009,43 @@ // IOEV_AON_PROG0 Edge detect IO event from the DIO(s) which have // enabled contribution to IOEV_AON_PROG0 in // [MCU_IOC:IOCFGx.IOEV_AON_PROG0_EN] -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_W 6 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M 0x0000003F -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S 0 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_NONE 0x0000003F -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC_N 0x00000038 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC 0x00000037 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_VOLT 0x00000036 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP 0x00000035 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER1_EV 0x00000034 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER0_EV 0x00000033 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TDC_DONE 0x00000032 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_ADC_DONE 0x00000031 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB 0x00000030 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPA 0x0000002F -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV2 0x0000002E -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV1 0x0000002D -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV0 0x0000002C -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_JTAG 0x0000002B -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_UPD 0x0000002A -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_COMB_DLY 0x00000029 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2_DLY 0x00000028 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1_DLY 0x00000027 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0_DLY 0x00000026 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2 0x00000025 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1 0x00000024 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0 0x00000023 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD 0x00000020 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_COMBINED 0x00000009 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP_LL 0x00000008 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP_UL 0x00000007 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_BATT_LL 0x00000006 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_BATT_UL 0x00000005 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV3 0x00000004 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV2 0x00000003 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV1 0x00000002 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV0 0x00000001 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_IOEV_AON_PROG0 0x00000000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M 0x0000003F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S 0 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_NONE 0x0000003F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_JTAG 0x0000002B +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_UPD 0x0000002A +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2 0x00000025 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1 0x00000024 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0 0x00000023 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD 0x00000020 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_COMBINED 0x00000009 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP_LL 0x00000008 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP_UL 0x00000007 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_BATT_LL 0x00000006 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_BATT_UL 0x00000005 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV3 0x00000004 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV2 0x00000003 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV1 0x00000002 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV0 0x00000001 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_IOEV_AON_PROG0 0x00000000 //***************************************************************************** // @@ -1093,43 +1093,42 @@ // IOEV_RTC Edge detect IO event from the DIO(s) which have // enabled contribution to IOEV_RTC in // [MCU_IOC:IOCFGx.IOEV_RTC_EN] -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_W 6 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M 0x0000003F -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S 0 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_NONE 0x0000003F -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC_N 0x00000038 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC 0x00000037 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_VOLT 0x00000036 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP 0x00000035 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER1_EV 0x00000034 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER0_EV 0x00000033 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TDC_DONE 0x00000032 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_ADC_DONE 0x00000031 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB 0x00000030 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPA 0x0000002F -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV2 0x0000002E -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV1 0x0000002D -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV0 0x0000002C -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_JTAG 0x0000002B -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_UPD 0x0000002A -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_COMB_DLY 0x00000029 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2_DLY 0x00000028 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1_DLY 0x00000027 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0_DLY 0x00000026 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2 0x00000025 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1 0x00000024 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0 0x00000023 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD 0x00000020 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_COMBINED 0x00000009 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP_LL 0x00000008 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP_UL 0x00000007 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_BATT_LL 0x00000006 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_BATT_UL 0x00000005 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV3 0x00000004 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV2 0x00000003 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV1 0x00000002 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV0 0x00000001 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_IOEV_RTC 0x00000000 - +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_W 6 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M 0x0000003F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S 0 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_NONE 0x0000003F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_JTAG 0x0000002B +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_UPD 0x0000002A +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2 0x00000025 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1 0x00000024 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0 0x00000023 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD 0x00000020 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_COMBINED 0x00000009 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP_LL 0x00000008 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP_UL 0x00000007 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_BATT_LL 0x00000006 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_BATT_UL 0x00000005 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV3 0x00000004 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV2 0x00000003 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV1 0x00000002 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV0 0x00000001 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_IOEV_RTC 0x00000000 #endif // __AON_EVENT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_ioc.h index b40b8fa..ff6d712 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_ioc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_ioc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aon_ioc_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aon_ioc_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AON_IOC_H__ #define __HW_AON_IOC_H__ @@ -44,22 +44,22 @@ // //***************************************************************************** // Internal -#define AON_IOC_O_IOSTRMIN 0x00000000 +#define AON_IOC_O_IOSTRMIN 0x00000000 // Internal -#define AON_IOC_O_IOSTRMED 0x00000004 +#define AON_IOC_O_IOSTRMED 0x00000004 // Internal -#define AON_IOC_O_IOSTRMAX 0x00000008 +#define AON_IOC_O_IOSTRMAX 0x00000008 // IO Latch Control -#define AON_IOC_O_IOCLATCH 0x0000000C +#define AON_IOC_O_IOCLATCH 0x0000000C // SCLK_LF External Output Control -#define AON_IOC_O_CLK32KCTL 0x00000010 +#define AON_IOC_O_CLK32KCTL 0x00000010 // TCK IO Pin Control -#define AON_IOC_O_TCKCTL 0x00000014 +#define AON_IOC_O_TCKCTL 0x00000014 //***************************************************************************** // @@ -69,9 +69,9 @@ // Field: [2:0] GRAY_CODE // // Internal. Only to be used through TI provided API. -#define AON_IOC_IOSTRMIN_GRAY_CODE_W 3 -#define AON_IOC_IOSTRMIN_GRAY_CODE_M 0x00000007 -#define AON_IOC_IOSTRMIN_GRAY_CODE_S 0 +#define AON_IOC_IOSTRMIN_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMIN_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMIN_GRAY_CODE_S 0 //***************************************************************************** // @@ -81,9 +81,9 @@ // Field: [2:0] GRAY_CODE // // Internal. Only to be used through TI provided API. -#define AON_IOC_IOSTRMED_GRAY_CODE_W 3 -#define AON_IOC_IOSTRMED_GRAY_CODE_M 0x00000007 -#define AON_IOC_IOSTRMED_GRAY_CODE_S 0 +#define AON_IOC_IOSTRMED_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMED_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMED_GRAY_CODE_S 0 //***************************************************************************** // @@ -93,9 +93,9 @@ // Field: [2:0] GRAY_CODE // // Internal. Only to be used through TI provided API. -#define AON_IOC_IOSTRMAX_GRAY_CODE_W 3 -#define AON_IOC_IOSTRMAX_GRAY_CODE_M 0x00000007 -#define AON_IOC_IOSTRMAX_GRAY_CODE_S 0 +#define AON_IOC_IOSTRMAX_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMAX_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMAX_GRAY_CODE_S 0 //***************************************************************************** // @@ -118,12 +118,12 @@ // the IO pin is frozen by latches and kept even // if GPIO module or a peripheral module is turned // off -#define AON_IOC_IOCLATCH_EN 0x00000001 -#define AON_IOC_IOCLATCH_EN_BITN 0 -#define AON_IOC_IOCLATCH_EN_M 0x00000001 -#define AON_IOC_IOCLATCH_EN_S 0 -#define AON_IOC_IOCLATCH_EN_TRANSP 0x00000001 -#define AON_IOC_IOCLATCH_EN_STATIC 0x00000000 +#define AON_IOC_IOCLATCH_EN 0x00000001 +#define AON_IOC_IOCLATCH_EN_BITN 0 +#define AON_IOC_IOCLATCH_EN_M 0x00000001 +#define AON_IOC_IOCLATCH_EN_S 0 +#define AON_IOC_IOCLATCH_EN_TRANSP 0x00000001 +#define AON_IOC_IOCLATCH_EN_STATIC 0x00000000 //***************************************************************************** // @@ -135,10 +135,10 @@ // 0: Output enable active. SCLK_LF output on IO pin that has PORT_ID (for // example IOC:IOCFG0.PORT_ID) set to AON_CLK32K. // 1: Output enable not active -#define AON_IOC_CLK32KCTL_OE_N 0x00000001 -#define AON_IOC_CLK32KCTL_OE_N_BITN 0 -#define AON_IOC_CLK32KCTL_OE_N_M 0x00000001 -#define AON_IOC_CLK32KCTL_OE_N_S 0 +#define AON_IOC_CLK32KCTL_OE_N 0x00000001 +#define AON_IOC_CLK32KCTL_OE_N_BITN 0 +#define AON_IOC_CLK32KCTL_OE_N_M 0x00000001 +#define AON_IOC_CLK32KCTL_OE_N_S 0 //***************************************************************************** // @@ -149,10 +149,9 @@ // // 0: Input driver for TCK disabled. // 1: Input driver for TCK enabled. -#define AON_IOC_TCKCTL_EN 0x00000001 -#define AON_IOC_TCKCTL_EN_BITN 0 -#define AON_IOC_TCKCTL_EN_M 0x00000001 -#define AON_IOC_TCKCTL_EN_S 0 - +#define AON_IOC_TCKCTL_EN 0x00000001 +#define AON_IOC_TCKCTL_EN_BITN 0 +#define AON_IOC_TCKCTL_EN_M 0x00000001 +#define AON_IOC_TCKCTL_EN_S 0 #endif // __AON_IOC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_pmctl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_pmctl.h index 33192cf..d62f539 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_pmctl.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_pmctl.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aon_pmctl_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aon_pmctl_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AON_PMCTL_H__ #define __HW_AON_PMCTL_H__ @@ -44,40 +44,40 @@ // //***************************************************************************** // AUX SCE Clock Management -#define AON_PMCTL_O_AUXSCECLK 0x00000004 +#define AON_PMCTL_O_AUXSCECLK 0x00000004 // RAM Configuration -#define AON_PMCTL_O_RAMCFG 0x00000008 +#define AON_PMCTL_O_RAMCFG 0x00000008 // Power Management Control -#define AON_PMCTL_O_PWRCTL 0x00000010 +#define AON_PMCTL_O_PWRCTL 0x00000010 // AON Power and Reset Status -#define AON_PMCTL_O_PWRSTAT 0x00000014 +#define AON_PMCTL_O_PWRSTAT 0x00000014 // Shutdown Control -#define AON_PMCTL_O_SHUTDOWN 0x00000018 +#define AON_PMCTL_O_SHUTDOWN 0x00000018 // Recharge Controller Configuration -#define AON_PMCTL_O_RECHARGECFG 0x0000001C +#define AON_PMCTL_O_RECHARGECFG 0x0000001C // Recharge Controller Status -#define AON_PMCTL_O_RECHARGESTAT 0x00000020 +#define AON_PMCTL_O_RECHARGESTAT 0x00000020 // Oscillator Configuration -#define AON_PMCTL_O_OSCCFG 0x00000024 +#define AON_PMCTL_O_OSCCFG 0x00000024 // Reset Management -#define AON_PMCTL_O_RESETCTL 0x00000028 +#define AON_PMCTL_O_RESETCTL 0x00000028 // Sleep Control -#define AON_PMCTL_O_SLEEPCTL 0x0000002C +#define AON_PMCTL_O_SLEEPCTL 0x0000002C // JTAG Configuration -#define AON_PMCTL_O_JTAGCFG 0x00000034 +#define AON_PMCTL_O_JTAGCFG 0x00000034 // JTAG USERCODE -#define AON_PMCTL_O_JTAGUSERCODE 0x0000003C +#define AON_PMCTL_O_JTAGUSERCODE 0x0000003C //***************************************************************************** // @@ -91,12 +91,12 @@ // ENUMs: // SCLK_LF LF clock (SCLK_LF ) // NO_CLOCK No clock -#define AON_PMCTL_AUXSCECLK_PD_SRC 0x00000100 -#define AON_PMCTL_AUXSCECLK_PD_SRC_BITN 8 -#define AON_PMCTL_AUXSCECLK_PD_SRC_M 0x00000100 -#define AON_PMCTL_AUXSCECLK_PD_SRC_S 8 -#define AON_PMCTL_AUXSCECLK_PD_SRC_SCLK_LF 0x00000100 -#define AON_PMCTL_AUXSCECLK_PD_SRC_NO_CLOCK 0x00000000 +#define AON_PMCTL_AUXSCECLK_PD_SRC 0x00000100 +#define AON_PMCTL_AUXSCECLK_PD_SRC_BITN 8 +#define AON_PMCTL_AUXSCECLK_PD_SRC_M 0x00000100 +#define AON_PMCTL_AUXSCECLK_PD_SRC_S 8 +#define AON_PMCTL_AUXSCECLK_PD_SRC_SCLK_LF 0x00000100 +#define AON_PMCTL_AUXSCECLK_PD_SRC_NO_CLOCK 0x00000000 // Field: [0] SRC // @@ -105,12 +105,12 @@ // ENUMs: // SCLK_MF MF Clock (SCLK_MF) // SCLK_HFDIV2 HF Clock divided by 2 (SCLK_HFDIV2) -#define AON_PMCTL_AUXSCECLK_SRC 0x00000001 -#define AON_PMCTL_AUXSCECLK_SRC_BITN 0 -#define AON_PMCTL_AUXSCECLK_SRC_M 0x00000001 -#define AON_PMCTL_AUXSCECLK_SRC_S 0 -#define AON_PMCTL_AUXSCECLK_SRC_SCLK_MF 0x00000001 -#define AON_PMCTL_AUXSCECLK_SRC_SCLK_HFDIV2 0x00000000 +#define AON_PMCTL_AUXSCECLK_SRC 0x00000001 +#define AON_PMCTL_AUXSCECLK_SRC_BITN 0 +#define AON_PMCTL_AUXSCECLK_SRC_M 0x00000001 +#define AON_PMCTL_AUXSCECLK_SRC_S 0 +#define AON_PMCTL_AUXSCECLK_SRC_SCLK_MF 0x00000001 +#define AON_PMCTL_AUXSCECLK_SRC_SCLK_HFDIV2 0x00000000 //***************************************************************************** // @@ -120,18 +120,18 @@ // Field: [17] AUX_SRAM_PWR_OFF // // Internal. Only to be used through TI provided API. -#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF 0x00020000 -#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_BITN 17 -#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_M 0x00020000 -#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_S 17 +#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF 0x00020000 +#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_BITN 17 +#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_M 0x00020000 +#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_S 17 // Field: [16] AUX_SRAM_RET_EN // // Internal. Only to be used through TI provided API. -#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN 0x00010000 -#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_BITN 16 -#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_M 0x00010000 -#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_S 16 +#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN 0x00010000 +#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_BITN 16 +#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_M 0x00010000 +#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_S 16 // Field: [3:0] BUS_SRAM_RET_EN // @@ -146,14 +146,14 @@ // SRAM:BANK2 // RET_LEVEL1 Retention on for SRAM:BANK0 and SRAM:BANK1 // RET_NONE Retention is disabled -#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_W 4 -#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_M 0x0000000F -#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_S 0 -#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_FULL 0x0000000F -#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL3 0x00000007 -#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL2 0x00000003 -#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL1 0x00000001 -#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_NONE 0x00000000 +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_W 4 +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_M 0x0000000F +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_S 0 +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_FULL 0x0000000F +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL3 0x00000007 +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL2 0x00000003 +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL1 0x00000001 +#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_NONE 0x00000000 //***************************************************************************** // @@ -169,10 +169,10 @@ // // DCDC_EN must also be set for DCDC to be used as regulator for VDDR in active // mode -#define AON_PMCTL_PWRCTL_DCDC_ACTIVE 0x00000004 -#define AON_PMCTL_PWRCTL_DCDC_ACTIVE_BITN 2 -#define AON_PMCTL_PWRCTL_DCDC_ACTIVE_M 0x00000004 -#define AON_PMCTL_PWRCTL_DCDC_ACTIVE_S 2 +#define AON_PMCTL_PWRCTL_DCDC_ACTIVE 0x00000004 +#define AON_PMCTL_PWRCTL_DCDC_ACTIVE_BITN 2 +#define AON_PMCTL_PWRCTL_DCDC_ACTIVE_M 0x00000004 +#define AON_PMCTL_PWRCTL_DCDC_ACTIVE_S 2 // Field: [1] EXT_REG_MODE // @@ -180,10 +180,10 @@ // // 0: DCDC or GLDO are generating VDDR // 1: DCDC and GLDO are bypassed and an external regulator supplies VDDR -#define AON_PMCTL_PWRCTL_EXT_REG_MODE 0x00000002 -#define AON_PMCTL_PWRCTL_EXT_REG_MODE_BITN 1 -#define AON_PMCTL_PWRCTL_EXT_REG_MODE_M 0x00000002 -#define AON_PMCTL_PWRCTL_EXT_REG_MODE_S 1 +#define AON_PMCTL_PWRCTL_EXT_REG_MODE 0x00000002 +#define AON_PMCTL_PWRCTL_EXT_REG_MODE_BITN 1 +#define AON_PMCTL_PWRCTL_EXT_REG_MODE_M 0x00000002 +#define AON_PMCTL_PWRCTL_EXT_REG_MODE_S 1 // Field: [0] DCDC_EN // @@ -193,10 +193,10 @@ // 1: Use DCDC for recharge of VDDR // // Note: This bitfield should be set to the same as DCDC_ACTIVE -#define AON_PMCTL_PWRCTL_DCDC_EN 0x00000001 -#define AON_PMCTL_PWRCTL_DCDC_EN_BITN 0 -#define AON_PMCTL_PWRCTL_DCDC_EN_M 0x00000001 -#define AON_PMCTL_PWRCTL_DCDC_EN_S 0 +#define AON_PMCTL_PWRCTL_DCDC_EN 0x00000001 +#define AON_PMCTL_PWRCTL_DCDC_EN_BITN 0 +#define AON_PMCTL_PWRCTL_DCDC_EN_M 0x00000001 +#define AON_PMCTL_PWRCTL_DCDC_EN_S 0 //***************************************************************************** // @@ -209,10 +209,10 @@ // // 0: JTAG is powered off // 1: JTAG is powered on -#define AON_PMCTL_PWRSTAT_JTAG_PD_ON 0x00000004 -#define AON_PMCTL_PWRSTAT_JTAG_PD_ON_BITN 2 -#define AON_PMCTL_PWRSTAT_JTAG_PD_ON_M 0x00000004 -#define AON_PMCTL_PWRSTAT_JTAG_PD_ON_S 2 +#define AON_PMCTL_PWRSTAT_JTAG_PD_ON 0x00000004 +#define AON_PMCTL_PWRSTAT_JTAG_PD_ON_BITN 2 +#define AON_PMCTL_PWRSTAT_JTAG_PD_ON_M 0x00000004 +#define AON_PMCTL_PWRSTAT_JTAG_PD_ON_S 2 // Field: [1] AUX_BUS_RESET_DONE // @@ -220,10 +220,10 @@ // // 0: AUX Bus is being reset // 1: AUX Bus reset is released -#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE 0x00000002 -#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_BITN 1 -#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_M 0x00000002 -#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_S 1 +#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE 0x00000002 +#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_BITN 1 +#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_M 0x00000002 +#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_S 1 // Field: [0] AUX_RESET_DONE // @@ -231,10 +231,10 @@ // // 0: AUX is being reset // 1: AUX reset is released -#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE 0x00000001 -#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_BITN 0 -#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_M 0x00000001 -#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_S 0 +#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE 0x00000001 +#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_BITN 0 +#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_M 0x00000001 +#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_S 0 //***************************************************************************** // @@ -247,10 +247,10 @@ // // 0: Do not write 0 to this bit. // 1: Immediately start the process to enter shutdown mode -#define AON_PMCTL_SHUTDOWN_EN 0x00000001 -#define AON_PMCTL_SHUTDOWN_EN_BITN 0 -#define AON_PMCTL_SHUTDOWN_EN_M 0x00000001 -#define AON_PMCTL_SHUTDOWN_EN_S 0 +#define AON_PMCTL_SHUTDOWN_EN 0x00000001 +#define AON_PMCTL_SHUTDOWN_EN_BITN 0 +#define AON_PMCTL_SHUTDOWN_EN_M 0x00000001 +#define AON_PMCTL_SHUTDOWN_EN_S 0 //***************************************************************************** // @@ -270,55 +270,55 @@ // ADAPTIVE Adaptive timer // STATIC Static timer // OFF Recharge disabled -#define AON_PMCTL_RECHARGECFG_MODE_W 2 -#define AON_PMCTL_RECHARGECFG_MODE_M 0xC0000000 -#define AON_PMCTL_RECHARGECFG_MODE_S 30 -#define AON_PMCTL_RECHARGECFG_MODE_COMPARATOR 0xC0000000 -#define AON_PMCTL_RECHARGECFG_MODE_ADAPTIVE 0x80000000 -#define AON_PMCTL_RECHARGECFG_MODE_STATIC 0x40000000 -#define AON_PMCTL_RECHARGECFG_MODE_OFF 0x00000000 +#define AON_PMCTL_RECHARGECFG_MODE_W 2 +#define AON_PMCTL_RECHARGECFG_MODE_M 0xC0000000 +#define AON_PMCTL_RECHARGECFG_MODE_S 30 +#define AON_PMCTL_RECHARGECFG_MODE_COMPARATOR 0xC0000000 +#define AON_PMCTL_RECHARGECFG_MODE_ADAPTIVE 0x80000000 +#define AON_PMCTL_RECHARGECFG_MODE_STATIC 0x40000000 +#define AON_PMCTL_RECHARGECFG_MODE_OFF 0x00000000 // Field: [23:20] C2 // // Internal. Only to be used through TI provided API. -#define AON_PMCTL_RECHARGECFG_C2_W 4 -#define AON_PMCTL_RECHARGECFG_C2_M 0x00F00000 -#define AON_PMCTL_RECHARGECFG_C2_S 20 +#define AON_PMCTL_RECHARGECFG_C2_W 4 +#define AON_PMCTL_RECHARGECFG_C2_M 0x00F00000 +#define AON_PMCTL_RECHARGECFG_C2_S 20 // Field: [19:16] C1 // // Internal. Only to be used through TI provided API. -#define AON_PMCTL_RECHARGECFG_C1_W 4 -#define AON_PMCTL_RECHARGECFG_C1_M 0x000F0000 -#define AON_PMCTL_RECHARGECFG_C1_S 16 +#define AON_PMCTL_RECHARGECFG_C1_W 4 +#define AON_PMCTL_RECHARGECFG_C1_M 0x000F0000 +#define AON_PMCTL_RECHARGECFG_C1_S 16 // Field: [15:11] MAX_PER_M // // Internal. Only to be used through TI provided API. -#define AON_PMCTL_RECHARGECFG_MAX_PER_M_W 5 -#define AON_PMCTL_RECHARGECFG_MAX_PER_M_M 0x0000F800 -#define AON_PMCTL_RECHARGECFG_MAX_PER_M_S 11 +#define AON_PMCTL_RECHARGECFG_MAX_PER_M_W 5 +#define AON_PMCTL_RECHARGECFG_MAX_PER_M_M 0x0000F800 +#define AON_PMCTL_RECHARGECFG_MAX_PER_M_S 11 // Field: [10:8] MAX_PER_E // // Internal. Only to be used through TI provided API. -#define AON_PMCTL_RECHARGECFG_MAX_PER_E_W 3 -#define AON_PMCTL_RECHARGECFG_MAX_PER_E_M 0x00000700 -#define AON_PMCTL_RECHARGECFG_MAX_PER_E_S 8 +#define AON_PMCTL_RECHARGECFG_MAX_PER_E_W 3 +#define AON_PMCTL_RECHARGECFG_MAX_PER_E_M 0x00000700 +#define AON_PMCTL_RECHARGECFG_MAX_PER_E_S 8 // Field: [7:3] PER_M // // Internal. Only to be used through TI provided API. -#define AON_PMCTL_RECHARGECFG_PER_M_W 5 -#define AON_PMCTL_RECHARGECFG_PER_M_M 0x000000F8 -#define AON_PMCTL_RECHARGECFG_PER_M_S 3 +#define AON_PMCTL_RECHARGECFG_PER_M_W 5 +#define AON_PMCTL_RECHARGECFG_PER_M_M 0x000000F8 +#define AON_PMCTL_RECHARGECFG_PER_M_S 3 // Field: [2:0] PER_E // // Internal. Only to be used through TI provided API. -#define AON_PMCTL_RECHARGECFG_PER_E_W 3 -#define AON_PMCTL_RECHARGECFG_PER_E_M 0x00000007 -#define AON_PMCTL_RECHARGECFG_PER_E_S 0 +#define AON_PMCTL_RECHARGECFG_PER_E_W 3 +#define AON_PMCTL_RECHARGECFG_PER_E_M 0x00000007 +#define AON_PMCTL_RECHARGECFG_PER_E_S 0 //***************************************************************************** // @@ -335,9 +335,9 @@ // // The register is updated prior to every recharge period with a shift left, // and bit 0 is updated with the last VDDR sample. -#define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_W 4 -#define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_M 0x000F0000 -#define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_S 16 +#define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_W 4 +#define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_M 0x000F0000 +#define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_S 16 // Field: [15:0] MAX_USED_PER // @@ -347,9 +347,9 @@ // during standby. // // This bitfield is cleared to 0 when writing this register. -#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_W 16 -#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_M 0x0000FFFF -#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_S 0 +#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_W 16 +#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_M 0x0000FFFF +#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_S 0 //***************************************************************************** // @@ -359,16 +359,16 @@ // Field: [7:3] PER_M // // Internal. Only to be used through TI provided API. -#define AON_PMCTL_OSCCFG_PER_M_W 5 -#define AON_PMCTL_OSCCFG_PER_M_M 0x000000F8 -#define AON_PMCTL_OSCCFG_PER_M_S 3 +#define AON_PMCTL_OSCCFG_PER_M_W 5 +#define AON_PMCTL_OSCCFG_PER_M_M 0x000000F8 +#define AON_PMCTL_OSCCFG_PER_M_S 3 // Field: [2:0] PER_E // // Internal. Only to be used through TI provided API. -#define AON_PMCTL_OSCCFG_PER_E_W 3 -#define AON_PMCTL_OSCCFG_PER_E_M 0x00000007 -#define AON_PMCTL_OSCCFG_PER_E_S 0 +#define AON_PMCTL_OSCCFG_PER_E_W 3 +#define AON_PMCTL_OSCCFG_PER_E_M 0x00000007 +#define AON_PMCTL_OSCCFG_PER_E_S 0 //***************************************************************************** // @@ -382,42 +382,42 @@ // // 0: No effect // 1: Generate system reset. Appears as SYSRESET in RESET_SRC -#define AON_PMCTL_RESETCTL_SYSRESET 0x80000000 -#define AON_PMCTL_RESETCTL_SYSRESET_BITN 31 -#define AON_PMCTL_RESETCTL_SYSRESET_M 0x80000000 -#define AON_PMCTL_RESETCTL_SYSRESET_S 31 +#define AON_PMCTL_RESETCTL_SYSRESET 0x80000000 +#define AON_PMCTL_RESETCTL_SYSRESET_BITN 31 +#define AON_PMCTL_RESETCTL_SYSRESET_M 0x80000000 +#define AON_PMCTL_RESETCTL_SYSRESET_S 31 // Field: [25] BOOT_DET_1_CLR // // Internal. Only to be used through TI provided API. -#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR 0x02000000 -#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_BITN 25 -#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_M 0x02000000 -#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_S 25 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR 0x02000000 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_BITN 25 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_M 0x02000000 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_S 25 // Field: [24] BOOT_DET_0_CLR // // Internal. Only to be used through TI provided API. -#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR 0x01000000 -#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_BITN 24 -#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_M 0x01000000 -#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_S 24 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR 0x01000000 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_BITN 24 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_M 0x01000000 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_S 24 // Field: [17] BOOT_DET_1_SET // // Internal. Only to be used through TI provided API. -#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET 0x00020000 -#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_BITN 17 -#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M 0x00020000 -#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_S 17 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET 0x00020000 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_BITN 17 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M 0x00020000 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_S 17 // Field: [16] BOOT_DET_0_SET // // Internal. Only to be used through TI provided API. -#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET 0x00010000 -#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_BITN 16 -#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_M 0x00010000 -#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_S 16 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET 0x00010000 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_BITN 16 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_M 0x00010000 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_S 16 // Field: [15] WU_FROM_SD // @@ -432,10 +432,10 @@ // 1: A wakeup has occurred from SHUTDOWN // // Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted. -#define AON_PMCTL_RESETCTL_WU_FROM_SD 0x00008000 -#define AON_PMCTL_RESETCTL_WU_FROM_SD_BITN 15 -#define AON_PMCTL_RESETCTL_WU_FROM_SD_M 0x00008000 -#define AON_PMCTL_RESETCTL_WU_FROM_SD_S 15 +#define AON_PMCTL_RESETCTL_WU_FROM_SD 0x00008000 +#define AON_PMCTL_RESETCTL_WU_FROM_SD_BITN 15 +#define AON_PMCTL_RESETCTL_WU_FROM_SD_M 0x00008000 +#define AON_PMCTL_RESETCTL_WU_FROM_SD_S 15 // Field: [14] GPIO_WU_FROM_SD // @@ -452,26 +452,26 @@ // from SHUTDOWN procedure until this bitfield is asserted as well. // // Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted. -#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD 0x00004000 -#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_BITN 14 -#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_M 0x00004000 -#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_S 14 +#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD 0x00004000 +#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_BITN 14 +#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_M 0x00004000 +#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_S 14 // Field: [13] BOOT_DET_1 // // Internal. Only to be used through TI provided API. -#define AON_PMCTL_RESETCTL_BOOT_DET_1 0x00002000 -#define AON_PMCTL_RESETCTL_BOOT_DET_1_BITN 13 -#define AON_PMCTL_RESETCTL_BOOT_DET_1_M 0x00002000 -#define AON_PMCTL_RESETCTL_BOOT_DET_1_S 13 +#define AON_PMCTL_RESETCTL_BOOT_DET_1 0x00002000 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_BITN 13 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_M 0x00002000 +#define AON_PMCTL_RESETCTL_BOOT_DET_1_S 13 // Field: [12] BOOT_DET_0 // // Internal. Only to be used through TI provided API. -#define AON_PMCTL_RESETCTL_BOOT_DET_0 0x00001000 -#define AON_PMCTL_RESETCTL_BOOT_DET_0_BITN 12 -#define AON_PMCTL_RESETCTL_BOOT_DET_0_M 0x00001000 -#define AON_PMCTL_RESETCTL_BOOT_DET_0_S 12 +#define AON_PMCTL_RESETCTL_BOOT_DET_0 0x00001000 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_BITN 12 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_M 0x00001000 +#define AON_PMCTL_RESETCTL_BOOT_DET_0_S 12 // Field: [8] VDDS_LOSS_EN // @@ -479,10 +479,10 @@ // // 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1 // 1: Brown out detect of VDDS generates system reset -#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN 0x00000100 -#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_BITN 8 -#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_M 0x00000100 -#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_S 8 +#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN 0x00000100 +#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_BITN 8 +#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_M 0x00000100 +#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_S 8 // Field: [7] VDDR_LOSS_EN // @@ -490,10 +490,10 @@ // // 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1 // 1: Brown out detect of VDDR generates system reset -#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN 0x00000080 -#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_BITN 7 -#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M 0x00000080 -#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_S 7 +#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN 0x00000080 +#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_BITN 7 +#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M 0x00000080 +#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_S 7 // Field: [6] VDD_LOSS_EN // @@ -501,10 +501,10 @@ // // 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1 // 1: Brown out detect of VDD generates system reset -#define AON_PMCTL_RESETCTL_VDD_LOSS_EN 0x00000040 -#define AON_PMCTL_RESETCTL_VDD_LOSS_EN_BITN 6 -#define AON_PMCTL_RESETCTL_VDD_LOSS_EN_M 0x00000040 -#define AON_PMCTL_RESETCTL_VDD_LOSS_EN_S 6 +#define AON_PMCTL_RESETCTL_VDD_LOSS_EN 0x00000040 +#define AON_PMCTL_RESETCTL_VDD_LOSS_EN_BITN 6 +#define AON_PMCTL_RESETCTL_VDD_LOSS_EN_M 0x00000040 +#define AON_PMCTL_RESETCTL_VDD_LOSS_EN_S 6 // Field: [5] CLK_LOSS_EN // @@ -518,18 +518,18 @@ // source for SCLK_LF. Failure to do so may result in a spurious system // reset. Clock loss reset generation is controlled by // [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN] -#define AON_PMCTL_RESETCTL_CLK_LOSS_EN 0x00000020 -#define AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN 5 -#define AON_PMCTL_RESETCTL_CLK_LOSS_EN_M 0x00000020 -#define AON_PMCTL_RESETCTL_CLK_LOSS_EN_S 5 +#define AON_PMCTL_RESETCTL_CLK_LOSS_EN 0x00000020 +#define AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN 5 +#define AON_PMCTL_RESETCTL_CLK_LOSS_EN_M 0x00000020 +#define AON_PMCTL_RESETCTL_CLK_LOSS_EN_S 5 // Field: [4] MCU_WARM_RESET // // Internal. Only to be used through TI provided API. -#define AON_PMCTL_RESETCTL_MCU_WARM_RESET 0x00000010 -#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_BITN 4 -#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_M 0x00000010 -#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_S 4 +#define AON_PMCTL_RESETCTL_MCU_WARM_RESET 0x00000010 +#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_BITN 4 +#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_M 0x00000010 +#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_S 4 // Field: [3:1] RESET_SRC // @@ -554,16 +554,16 @@ // VDDS_LOSS Brown out detect on VDDS // PIN_RESET Reset pin // PWR_ON Power on reset -#define AON_PMCTL_RESETCTL_RESET_SRC_W 3 -#define AON_PMCTL_RESETCTL_RESET_SRC_M 0x0000000E -#define AON_PMCTL_RESETCTL_RESET_SRC_S 1 -#define AON_PMCTL_RESETCTL_RESET_SRC_WARMRESET 0x0000000E -#define AON_PMCTL_RESETCTL_RESET_SRC_SYSRESET 0x0000000C -#define AON_PMCTL_RESETCTL_RESET_SRC_CLK_LOSS 0x0000000A -#define AON_PMCTL_RESETCTL_RESET_SRC_VDDR_LOSS 0x00000008 -#define AON_PMCTL_RESETCTL_RESET_SRC_VDDS_LOSS 0x00000004 -#define AON_PMCTL_RESETCTL_RESET_SRC_PIN_RESET 0x00000002 -#define AON_PMCTL_RESETCTL_RESET_SRC_PWR_ON 0x00000000 +#define AON_PMCTL_RESETCTL_RESET_SRC_W 3 +#define AON_PMCTL_RESETCTL_RESET_SRC_M 0x0000000E +#define AON_PMCTL_RESETCTL_RESET_SRC_S 1 +#define AON_PMCTL_RESETCTL_RESET_SRC_WARMRESET 0x0000000E +#define AON_PMCTL_RESETCTL_RESET_SRC_SYSRESET 0x0000000C +#define AON_PMCTL_RESETCTL_RESET_SRC_CLK_LOSS 0x0000000A +#define AON_PMCTL_RESETCTL_RESET_SRC_VDDR_LOSS 0x00000008 +#define AON_PMCTL_RESETCTL_RESET_SRC_VDDS_LOSS 0x00000004 +#define AON_PMCTL_RESETCTL_RESET_SRC_PIN_RESET 0x00000002 +#define AON_PMCTL_RESETCTL_RESET_SRC_PWR_ON 0x00000000 //***************************************************************************** // @@ -583,10 +583,10 @@ // // Application software must reconfigure the state for all IO's before setting // this bitfield upon waking up from a SHUTDOWN to avoid glitches on pins. -#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS 0x00000001 -#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN 0 -#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_M 0x00000001 -#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_S 0 +#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS 0x00000001 +#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN 0 +#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_M 0x00000001 +#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_S 0 //***************************************************************************** // @@ -603,10 +603,10 @@ // // Note: The reset value causes JTAG Power domain to be powered on by default. // Software must clear this bit to turn off the JTAG Power domain -#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON 0x00000100 -#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_BITN 8 -#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_M 0x00000100 -#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_S 8 +#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON 0x00000100 +#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_BITN 8 +#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_M 0x00000100 +#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_S 8 //***************************************************************************** // @@ -617,9 +617,8 @@ // // 32-bit JTAG USERCODE register feeding main JTAG TAP // Note: This field can be locked by LOCKCFG.LOCK -#define AON_PMCTL_JTAGUSERCODE_USER_CODE_W 32 -#define AON_PMCTL_JTAGUSERCODE_USER_CODE_M 0xFFFFFFFF -#define AON_PMCTL_JTAGUSERCODE_USER_CODE_S 0 - +#define AON_PMCTL_JTAGUSERCODE_USER_CODE_W 32 +#define AON_PMCTL_JTAGUSERCODE_USER_CODE_M 0xFFFFFFFF +#define AON_PMCTL_JTAGUSERCODE_USER_CODE_S 0 #endif // __AON_PMCTL__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_rtc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_rtc.h index 6644cf4..0ae6397 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_rtc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_rtc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aon_rtc_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aon_rtc_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AON_RTC_H__ #define __HW_AON_RTC_H__ @@ -44,46 +44,46 @@ // //***************************************************************************** // Control -#define AON_RTC_O_CTL 0x00000000 +#define AON_RTC_O_CTL 0x00000000 // Event Flags, RTC Status -#define AON_RTC_O_EVFLAGS 0x00000004 +#define AON_RTC_O_EVFLAGS 0x00000004 // Second Counter Value, Integer Part -#define AON_RTC_O_SEC 0x00000008 +#define AON_RTC_O_SEC 0x00000008 // Second Counter Value, Fractional Part -#define AON_RTC_O_SUBSEC 0x0000000C +#define AON_RTC_O_SUBSEC 0x0000000C // Subseconds Increment -#define AON_RTC_O_SUBSECINC 0x00000010 +#define AON_RTC_O_SUBSECINC 0x00000010 // Channel Configuration -#define AON_RTC_O_CHCTL 0x00000014 +#define AON_RTC_O_CHCTL 0x00000014 // Channel 0 Compare Value -#define AON_RTC_O_CH0CMP 0x00000018 +#define AON_RTC_O_CH0CMP 0x00000018 // Channel 1 Compare Value -#define AON_RTC_O_CH1CMP 0x0000001C +#define AON_RTC_O_CH1CMP 0x0000001C // Channel 2 Compare Value -#define AON_RTC_O_CH2CMP 0x00000020 +#define AON_RTC_O_CH2CMP 0x00000020 // Channel 2 Compare Value Auto-increment -#define AON_RTC_O_CH2CMPINC 0x00000024 +#define AON_RTC_O_CH2CMPINC 0x00000024 // Channel 1 Capture Value -#define AON_RTC_O_CH1CAPT 0x00000028 +#define AON_RTC_O_CH1CAPT 0x00000028 // AON Synchronization -#define AON_RTC_O_SYNC 0x0000002C +#define AON_RTC_O_SYNC 0x0000002C // Current Counter Value -#define AON_RTC_O_TIME 0x00000030 +#define AON_RTC_O_TIME 0x00000030 // Synchronization to SCLK_LF -#define AON_RTC_O_SYNCLF 0x00000034 +#define AON_RTC_O_SYNCLF 0x00000034 //***************************************************************************** // @@ -98,13 +98,13 @@ // CH1 Use Channel 1 delayed event in combined event // CH0 Use Channel 0 delayed event in combined event // NONE No event is selected for combined event. -#define AON_RTC_CTL_COMB_EV_MASK_W 3 -#define AON_RTC_CTL_COMB_EV_MASK_M 0x00070000 -#define AON_RTC_CTL_COMB_EV_MASK_S 16 -#define AON_RTC_CTL_COMB_EV_MASK_CH2 0x00040000 -#define AON_RTC_CTL_COMB_EV_MASK_CH1 0x00020000 -#define AON_RTC_CTL_COMB_EV_MASK_CH0 0x00010000 -#define AON_RTC_CTL_COMB_EV_MASK_NONE 0x00000000 +#define AON_RTC_CTL_COMB_EV_MASK_W 3 +#define AON_RTC_CTL_COMB_EV_MASK_M 0x00070000 +#define AON_RTC_CTL_COMB_EV_MASK_S 16 +#define AON_RTC_CTL_COMB_EV_MASK_CH2 0x00040000 +#define AON_RTC_CTL_COMB_EV_MASK_CH1 0x00020000 +#define AON_RTC_CTL_COMB_EV_MASK_CH0 0x00010000 +#define AON_RTC_CTL_COMB_EV_MASK_NONE 0x00000000 // Field: [11:8] EV_DELAY // @@ -125,23 +125,23 @@ // D2 Delay by 2 clock cycles // D1 Delay by 1 clock cycles // D0 No delay on delayed event -#define AON_RTC_CTL_EV_DELAY_W 4 -#define AON_RTC_CTL_EV_DELAY_M 0x00000F00 -#define AON_RTC_CTL_EV_DELAY_S 8 -#define AON_RTC_CTL_EV_DELAY_D144 0x00000D00 -#define AON_RTC_CTL_EV_DELAY_D128 0x00000C00 -#define AON_RTC_CTL_EV_DELAY_D112 0x00000B00 -#define AON_RTC_CTL_EV_DELAY_D96 0x00000A00 -#define AON_RTC_CTL_EV_DELAY_D80 0x00000900 -#define AON_RTC_CTL_EV_DELAY_D64 0x00000800 -#define AON_RTC_CTL_EV_DELAY_D48 0x00000700 -#define AON_RTC_CTL_EV_DELAY_D32 0x00000600 -#define AON_RTC_CTL_EV_DELAY_D16 0x00000500 -#define AON_RTC_CTL_EV_DELAY_D8 0x00000400 -#define AON_RTC_CTL_EV_DELAY_D4 0x00000300 -#define AON_RTC_CTL_EV_DELAY_D2 0x00000200 -#define AON_RTC_CTL_EV_DELAY_D1 0x00000100 -#define AON_RTC_CTL_EV_DELAY_D0 0x00000000 +#define AON_RTC_CTL_EV_DELAY_W 4 +#define AON_RTC_CTL_EV_DELAY_M 0x00000F00 +#define AON_RTC_CTL_EV_DELAY_S 8 +#define AON_RTC_CTL_EV_DELAY_D144 0x00000D00 +#define AON_RTC_CTL_EV_DELAY_D128 0x00000C00 +#define AON_RTC_CTL_EV_DELAY_D112 0x00000B00 +#define AON_RTC_CTL_EV_DELAY_D96 0x00000A00 +#define AON_RTC_CTL_EV_DELAY_D80 0x00000900 +#define AON_RTC_CTL_EV_DELAY_D64 0x00000800 +#define AON_RTC_CTL_EV_DELAY_D48 0x00000700 +#define AON_RTC_CTL_EV_DELAY_D32 0x00000600 +#define AON_RTC_CTL_EV_DELAY_D16 0x00000500 +#define AON_RTC_CTL_EV_DELAY_D8 0x00000400 +#define AON_RTC_CTL_EV_DELAY_D4 0x00000300 +#define AON_RTC_CTL_EV_DELAY_D2 0x00000200 +#define AON_RTC_CTL_EV_DELAY_D1 0x00000100 +#define AON_RTC_CTL_EV_DELAY_D0 0x00000000 // Field: [7] RESET // @@ -150,10 +150,10 @@ // Writing 1 to this bit will reset the RTC counter. // // This bit is cleared when reset takes effect -#define AON_RTC_CTL_RESET 0x00000080 -#define AON_RTC_CTL_RESET_BITN 7 -#define AON_RTC_CTL_RESET_M 0x00000080 -#define AON_RTC_CTL_RESET_S 7 +#define AON_RTC_CTL_RESET 0x00000080 +#define AON_RTC_CTL_RESET_BITN 7 +#define AON_RTC_CTL_RESET_M 0x00000080 +#define AON_RTC_CTL_RESET_S 7 // Field: [2] RTC_4KHZ_EN // @@ -162,10 +162,10 @@ // // 0: RTC_4KHZ signal is forced to 0 // 1: RTC_4KHZ is enabled ( provied that RTC is enabled EN) -#define AON_RTC_CTL_RTC_4KHZ_EN 0x00000004 -#define AON_RTC_CTL_RTC_4KHZ_EN_BITN 2 -#define AON_RTC_CTL_RTC_4KHZ_EN_M 0x00000004 -#define AON_RTC_CTL_RTC_4KHZ_EN_S 2 +#define AON_RTC_CTL_RTC_4KHZ_EN 0x00000004 +#define AON_RTC_CTL_RTC_4KHZ_EN_BITN 2 +#define AON_RTC_CTL_RTC_4KHZ_EN_M 0x00000004 +#define AON_RTC_CTL_RTC_4KHZ_EN_S 2 // Field: [1] RTC_UPD_EN // @@ -174,10 +174,10 @@ // // 0: RTC_UPD signal is forced to 0 // 1: RTC_UPD signal is toggling @16 kHz -#define AON_RTC_CTL_RTC_UPD_EN 0x00000002 -#define AON_RTC_CTL_RTC_UPD_EN_BITN 1 -#define AON_RTC_CTL_RTC_UPD_EN_M 0x00000002 -#define AON_RTC_CTL_RTC_UPD_EN_S 1 +#define AON_RTC_CTL_RTC_UPD_EN 0x00000002 +#define AON_RTC_CTL_RTC_UPD_EN_BITN 1 +#define AON_RTC_CTL_RTC_UPD_EN_M 0x00000002 +#define AON_RTC_CTL_RTC_UPD_EN_S 1 // Field: [0] EN // @@ -185,10 +185,10 @@ // // 0: Halted (frozen) // 1: Running -#define AON_RTC_CTL_EN 0x00000001 -#define AON_RTC_CTL_EN_BITN 0 -#define AON_RTC_CTL_EN_M 0x00000001 -#define AON_RTC_CTL_EN_S 0 +#define AON_RTC_CTL_EN 0x00000001 +#define AON_RTC_CTL_EN_BITN 0 +#define AON_RTC_CTL_EN_M 0x00000001 +#define AON_RTC_CTL_EN_S 0 //***************************************************************************** // @@ -208,10 +208,10 @@ // // AUX_SCE can read the flag through AUX_EVCTL:EVSTAT2.AON_RTC_CH2 and clear it // using AUX_SYSIF:RTCEVCLR.RTC_CH2_EV_CLR. -#define AON_RTC_EVFLAGS_CH2 0x00010000 -#define AON_RTC_EVFLAGS_CH2_BITN 16 -#define AON_RTC_EVFLAGS_CH2_M 0x00010000 -#define AON_RTC_EVFLAGS_CH2_S 16 +#define AON_RTC_EVFLAGS_CH2 0x00010000 +#define AON_RTC_EVFLAGS_CH2_BITN 16 +#define AON_RTC_EVFLAGS_CH2_M 0x00010000 +#define AON_RTC_EVFLAGS_CH2_S 16 // Field: [8] CH1 // @@ -225,10 +225,10 @@ // value matches any time between next RTC value and 1 second in the past. // // Writing 1 clears this flag. -#define AON_RTC_EVFLAGS_CH1 0x00000100 -#define AON_RTC_EVFLAGS_CH1_BITN 8 -#define AON_RTC_EVFLAGS_CH1_M 0x00000100 -#define AON_RTC_EVFLAGS_CH1_S 8 +#define AON_RTC_EVFLAGS_CH1 0x00000100 +#define AON_RTC_EVFLAGS_CH1_BITN 8 +#define AON_RTC_EVFLAGS_CH1_M 0x00000100 +#define AON_RTC_EVFLAGS_CH1_S 8 // Field: [0] CH0 // @@ -240,10 +240,10 @@ // time between next RTC value and 1 second in the past. // // Writing 1 clears this flag. -#define AON_RTC_EVFLAGS_CH0 0x00000001 -#define AON_RTC_EVFLAGS_CH0_BITN 0 -#define AON_RTC_EVFLAGS_CH0_M 0x00000001 -#define AON_RTC_EVFLAGS_CH0_S 0 +#define AON_RTC_EVFLAGS_CH0 0x00000001 +#define AON_RTC_EVFLAGS_CH0_BITN 0 +#define AON_RTC_EVFLAGS_CH0_M 0x00000001 +#define AON_RTC_EVFLAGS_CH0_S 0 //***************************************************************************** // @@ -257,9 +257,9 @@ // When reading this register the content of SUBSEC.VALUE is simultaneously // latched. A consistent reading of the combined Real Time Clock can be // obtained by first reading this register, then reading SUBSEC register. -#define AON_RTC_SEC_VALUE_W 32 -#define AON_RTC_SEC_VALUE_M 0xFFFFFFFF -#define AON_RTC_SEC_VALUE_S 0 +#define AON_RTC_SEC_VALUE_W 32 +#define AON_RTC_SEC_VALUE_M 0xFFFFFFFF +#define AON_RTC_SEC_VALUE_S 0 //***************************************************************************** // @@ -276,9 +276,9 @@ // - 0x4000_0000 = 0.25 sec // - 0x8000_0000 = 0.5 sec // - 0xC000_0000 = 0.75 sec -#define AON_RTC_SUBSEC_VALUE_W 32 -#define AON_RTC_SUBSEC_VALUE_M 0xFFFFFFFF -#define AON_RTC_SUBSEC_VALUE_S 0 +#define AON_RTC_SUBSEC_VALUE_W 32 +#define AON_RTC_SUBSEC_VALUE_M 0xFFFFFFFF +#define AON_RTC_SUBSEC_VALUE_S 0 //***************************************************************************** // @@ -304,9 +304,9 @@ // NOTE: This register is read only. Modification of the register value must be // done using registers AUX_SYSIF:RTCSUBSECINC0 , AUX_SYSIF:RTCSUBSECINC1 and // AUX_SYSIF:RTCSUBSECINCCTL -#define AON_RTC_SUBSECINC_VALUEINC_W 24 -#define AON_RTC_SUBSECINC_VALUEINC_M 0x00FFFFFF -#define AON_RTC_SUBSECINC_VALUEINC_S 0 +#define AON_RTC_SUBSECINC_VALUEINC_W 24 +#define AON_RTC_SUBSECINC_VALUEINC_M 0x00FFFFFF +#define AON_RTC_SUBSECINC_VALUEINC_S 0 //***************************************************************************** // @@ -316,10 +316,10 @@ // Field: [18] CH2_CONT_EN // // Set to enable continuous operation of Channel 2 -#define AON_RTC_CHCTL_CH2_CONT_EN 0x00040000 -#define AON_RTC_CHCTL_CH2_CONT_EN_BITN 18 -#define AON_RTC_CHCTL_CH2_CONT_EN_M 0x00040000 -#define AON_RTC_CHCTL_CH2_CONT_EN_S 18 +#define AON_RTC_CHCTL_CH2_CONT_EN 0x00040000 +#define AON_RTC_CHCTL_CH2_CONT_EN_BITN 18 +#define AON_RTC_CHCTL_CH2_CONT_EN_M 0x00040000 +#define AON_RTC_CHCTL_CH2_CONT_EN_S 18 // Field: [16] CH2_EN // @@ -327,10 +327,10 @@ // // 0: Disable RTC Channel 2 // 1: Enable RTC Channel 2 -#define AON_RTC_CHCTL_CH2_EN 0x00010000 -#define AON_RTC_CHCTL_CH2_EN_BITN 16 -#define AON_RTC_CHCTL_CH2_EN_M 0x00010000 -#define AON_RTC_CHCTL_CH2_EN_S 16 +#define AON_RTC_CHCTL_CH2_EN 0x00010000 +#define AON_RTC_CHCTL_CH2_EN_BITN 16 +#define AON_RTC_CHCTL_CH2_EN_M 0x00010000 +#define AON_RTC_CHCTL_CH2_EN_S 16 // Field: [9] CH1_CAPT_EN // @@ -338,10 +338,10 @@ // // 0: Compare mode (default) // 1: Capture mode -#define AON_RTC_CHCTL_CH1_CAPT_EN 0x00000200 -#define AON_RTC_CHCTL_CH1_CAPT_EN_BITN 9 -#define AON_RTC_CHCTL_CH1_CAPT_EN_M 0x00000200 -#define AON_RTC_CHCTL_CH1_CAPT_EN_S 9 +#define AON_RTC_CHCTL_CH1_CAPT_EN 0x00000200 +#define AON_RTC_CHCTL_CH1_CAPT_EN_BITN 9 +#define AON_RTC_CHCTL_CH1_CAPT_EN_M 0x00000200 +#define AON_RTC_CHCTL_CH1_CAPT_EN_S 9 // Field: [8] CH1_EN // @@ -349,10 +349,10 @@ // // 0: Disable RTC Channel 1 // 1: Enable RTC Channel 1 -#define AON_RTC_CHCTL_CH1_EN 0x00000100 -#define AON_RTC_CHCTL_CH1_EN_BITN 8 -#define AON_RTC_CHCTL_CH1_EN_M 0x00000100 -#define AON_RTC_CHCTL_CH1_EN_S 8 +#define AON_RTC_CHCTL_CH1_EN 0x00000100 +#define AON_RTC_CHCTL_CH1_EN_BITN 8 +#define AON_RTC_CHCTL_CH1_EN_M 0x00000100 +#define AON_RTC_CHCTL_CH1_EN_S 8 // Field: [0] CH0_EN // @@ -360,10 +360,10 @@ // // 0: Disable RTC Channel 0 // 1: Enable RTC Channel 0 -#define AON_RTC_CHCTL_CH0_EN 0x00000001 -#define AON_RTC_CHCTL_CH0_EN_BITN 0 -#define AON_RTC_CHCTL_CH0_EN_M 0x00000001 -#define AON_RTC_CHCTL_CH0_EN_S 0 +#define AON_RTC_CHCTL_CH0_EN 0x00000001 +#define AON_RTC_CHCTL_CH0_EN_BITN 0 +#define AON_RTC_CHCTL_CH0_EN_M 0x00000001 +#define AON_RTC_CHCTL_CH0_EN_S 0 //***************************************************************************** // @@ -391,9 +391,9 @@ // // *) It can take up to one SCLK_LF clock cycles before event occurs due to // synchronization. -#define AON_RTC_CH0CMP_VALUE_W 32 -#define AON_RTC_CH0CMP_VALUE_M 0xFFFFFFFF -#define AON_RTC_CH0CMP_VALUE_S 0 +#define AON_RTC_CH0CMP_VALUE_W 32 +#define AON_RTC_CH0CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH0CMP_VALUE_S 0 //***************************************************************************** // @@ -421,9 +421,9 @@ // // *) It can take up to one SCLK_LF clock cycles before event occurs due to // synchronization. -#define AON_RTC_CH1CMP_VALUE_W 32 -#define AON_RTC_CH1CMP_VALUE_M 0xFFFFFFFF -#define AON_RTC_CH1CMP_VALUE_S 0 +#define AON_RTC_CH1CMP_VALUE_W 32 +#define AON_RTC_CH1CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH1CMP_VALUE_S 0 //***************************************************************************** // @@ -451,9 +451,9 @@ // // *) It can take up to one SCLK_LF clock cycles before event occurs due to // synchronization. -#define AON_RTC_CH2CMP_VALUE_W 32 -#define AON_RTC_CH2CMP_VALUE_M 0xFFFFFFFF -#define AON_RTC_CH2CMP_VALUE_S 0 +#define AON_RTC_CH2CMP_VALUE_W 32 +#define AON_RTC_CH2CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH2CMP_VALUE_S 0 //***************************************************************************** // @@ -464,9 +464,9 @@ // // If CHCTL.CH2_CONT_EN is set, this value is added to CH2CMP.VALUE on every // channel 2 compare event. -#define AON_RTC_CH2CMPINC_VALUE_W 32 -#define AON_RTC_CH2CMPINC_VALUE_M 0xFFFFFFFF -#define AON_RTC_CH2CMPINC_VALUE_S 0 +#define AON_RTC_CH2CMPINC_VALUE_W 32 +#define AON_RTC_CH2CMPINC_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH2CMPINC_VALUE_S 0 //***************************************************************************** // @@ -476,16 +476,16 @@ // Field: [31:16] SEC // // Value of SEC.VALUE bits 15:0 at capture time. -#define AON_RTC_CH1CAPT_SEC_W 16 -#define AON_RTC_CH1CAPT_SEC_M 0xFFFF0000 -#define AON_RTC_CH1CAPT_SEC_S 16 +#define AON_RTC_CH1CAPT_SEC_W 16 +#define AON_RTC_CH1CAPT_SEC_M 0xFFFF0000 +#define AON_RTC_CH1CAPT_SEC_S 16 // Field: [15:0] SUBSEC // // Value of SUBSEC.VALUE bits 31:16 at capture time. -#define AON_RTC_CH1CAPT_SUBSEC_W 16 -#define AON_RTC_CH1CAPT_SUBSEC_M 0x0000FFFF -#define AON_RTC_CH1CAPT_SUBSEC_S 0 +#define AON_RTC_CH1CAPT_SUBSEC_W 16 +#define AON_RTC_CH1CAPT_SUBSEC_M 0x0000FFFF +#define AON_RTC_CH1CAPT_SUBSEC_S 0 //***************************************************************************** // @@ -502,10 +502,10 @@ // waking up from sleep // Failure to do so may result in reading AON values from prior to going to // sleep -#define AON_RTC_SYNC_WBUSY 0x00000001 -#define AON_RTC_SYNC_WBUSY_BITN 0 -#define AON_RTC_SYNC_WBUSY_M 0x00000001 -#define AON_RTC_SYNC_WBUSY_S 0 +#define AON_RTC_SYNC_WBUSY 0x00000001 +#define AON_RTC_SYNC_WBUSY_BITN 0 +#define AON_RTC_SYNC_WBUSY_M 0x00000001 +#define AON_RTC_SYNC_WBUSY_S 0 //***************************************************************************** // @@ -515,16 +515,16 @@ // Field: [31:16] SEC_L // // Returns the lower halfword of SEC register. -#define AON_RTC_TIME_SEC_L_W 16 -#define AON_RTC_TIME_SEC_L_M 0xFFFF0000 -#define AON_RTC_TIME_SEC_L_S 16 +#define AON_RTC_TIME_SEC_L_W 16 +#define AON_RTC_TIME_SEC_L_M 0xFFFF0000 +#define AON_RTC_TIME_SEC_L_S 16 // Field: [15:0] SUBSEC_H // // Returns the upper halfword of SUBSEC register. -#define AON_RTC_TIME_SUBSEC_H_W 16 -#define AON_RTC_TIME_SUBSEC_H_M 0x0000FFFF -#define AON_RTC_TIME_SUBSEC_H_S 0 +#define AON_RTC_TIME_SUBSEC_H_W 16 +#define AON_RTC_TIME_SUBSEC_H_M 0x0000FFFF +#define AON_RTC_TIME_SUBSEC_H_S 0 //***************************************************************************** // @@ -537,10 +537,9 @@ // a positive or negative edge of SCLK_LF is seen. // 0: Falling edge of SCLK_LF // 1: Rising edge of SCLK_LF -#define AON_RTC_SYNCLF_PHASE 0x00000001 -#define AON_RTC_SYNCLF_PHASE_BITN 0 -#define AON_RTC_SYNCLF_PHASE_M 0x00000001 -#define AON_RTC_SYNCLF_PHASE_S 0 - +#define AON_RTC_SYNCLF_PHASE 0x00000001 +#define AON_RTC_SYNCLF_PHASE_BITN 0 +#define AON_RTC_SYNCLF_PHASE_M 0x00000001 +#define AON_RTC_SYNCLF_PHASE_S 0 #endif // __AON_RTC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_aiodio.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_aiodio.h index 29d8cf9..d7000ab 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_aiodio.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_aiodio.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_aiodio_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_aiodio_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_AIODIO_H__ #define __HW_AUX_AIODIO_H__ @@ -44,58 +44,58 @@ // //***************************************************************************** // Input Output Mode -#define AUX_AIODIO_O_IOMODE 0x00000000 +#define AUX_AIODIO_O_IOMODE 0x00000000 // General Purpose Input Output Digital Input Enable -#define AUX_AIODIO_O_GPIODIE 0x00000004 +#define AUX_AIODIO_O_GPIODIE 0x00000004 // Input Output Peripheral Output Enable -#define AUX_AIODIO_O_IOPOE 0x00000008 +#define AUX_AIODIO_O_IOPOE 0x00000008 // General Purpose Input Output Data Out -#define AUX_AIODIO_O_GPIODOUT 0x0000000C +#define AUX_AIODIO_O_GPIODOUT 0x0000000C // General Purpose Input Output Data In -#define AUX_AIODIO_O_GPIODIN 0x00000010 +#define AUX_AIODIO_O_GPIODIN 0x00000010 // General Purpose Input Output Data Out Set -#define AUX_AIODIO_O_GPIODOUTSET 0x00000014 +#define AUX_AIODIO_O_GPIODOUTSET 0x00000014 // General Purpose Input Output Data Out Clear -#define AUX_AIODIO_O_GPIODOUTCLR 0x00000018 +#define AUX_AIODIO_O_GPIODOUTCLR 0x00000018 // General Purpose Input Output Data Out Toggle -#define AUX_AIODIO_O_GPIODOUTTGL 0x0000001C +#define AUX_AIODIO_O_GPIODOUTTGL 0x0000001C // Input Output 0 Peripheral Select -#define AUX_AIODIO_O_IO0PSEL 0x00000020 +#define AUX_AIODIO_O_IO0PSEL 0x00000020 // Input Output 1 Peripheral Select -#define AUX_AIODIO_O_IO1PSEL 0x00000024 +#define AUX_AIODIO_O_IO1PSEL 0x00000024 // Input Output 2 Peripheral Select -#define AUX_AIODIO_O_IO2PSEL 0x00000028 +#define AUX_AIODIO_O_IO2PSEL 0x00000028 // Input Output 3 Peripheral Select -#define AUX_AIODIO_O_IO3PSEL 0x0000002C +#define AUX_AIODIO_O_IO3PSEL 0x0000002C // Input Output 4 Peripheral Select -#define AUX_AIODIO_O_IO4PSEL 0x00000030 +#define AUX_AIODIO_O_IO4PSEL 0x00000030 // Input Output 5 Peripheral Select -#define AUX_AIODIO_O_IO5PSEL 0x00000034 +#define AUX_AIODIO_O_IO5PSEL 0x00000034 // Input Output 6 Peripheral Select -#define AUX_AIODIO_O_IO6PSEL 0x00000038 +#define AUX_AIODIO_O_IO6PSEL 0x00000038 // Input Output 7 Peripheral Select -#define AUX_AIODIO_O_IO7PSEL 0x0000003C +#define AUX_AIODIO_O_IO7PSEL 0x0000003C // Input Output Mode Low -#define AUX_AIODIO_O_IOMODEL 0x00000040 +#define AUX_AIODIO_O_IOMODEL 0x00000040 // Input Output Mode High -#define AUX_AIODIO_O_IOMODEH 0x00000044 +#define AUX_AIODIO_O_IOMODEH 0x00000044 //***************************************************************************** // @@ -152,13 +152,13 @@ // When IOPOE bit 7 is 1: // The signal selected by IO7PSEL.SRC drives // AUXIO[8i+7]. -#define AUX_AIODIO_IOMODE_IO7_W 2 -#define AUX_AIODIO_IOMODE_IO7_M 0x0000C000 -#define AUX_AIODIO_IOMODE_IO7_S 14 -#define AUX_AIODIO_IOMODE_IO7_OPEN_SOURCE 0x0000C000 -#define AUX_AIODIO_IOMODE_IO7_OPEN_DRAIN 0x00008000 -#define AUX_AIODIO_IOMODE_IO7_IN 0x00004000 -#define AUX_AIODIO_IOMODE_IO7_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO7_W 2 +#define AUX_AIODIO_IOMODE_IO7_M 0x0000C000 +#define AUX_AIODIO_IOMODE_IO7_S 14 +#define AUX_AIODIO_IOMODE_IO7_OPEN_SOURCE 0x0000C000 +#define AUX_AIODIO_IOMODE_IO7_OPEN_DRAIN 0x00008000 +#define AUX_AIODIO_IOMODE_IO7_IN 0x00004000 +#define AUX_AIODIO_IOMODE_IO7_OUT 0x00000000 // Field: [13:12] IO6 // @@ -210,13 +210,13 @@ // When IOPOE bit 6 is 1: // The signal selected by IO6PSEL.SRC drives // AUXIO[8i+6]. -#define AUX_AIODIO_IOMODE_IO6_W 2 -#define AUX_AIODIO_IOMODE_IO6_M 0x00003000 -#define AUX_AIODIO_IOMODE_IO6_S 12 -#define AUX_AIODIO_IOMODE_IO6_OPEN_SOURCE 0x00003000 -#define AUX_AIODIO_IOMODE_IO6_OPEN_DRAIN 0x00002000 -#define AUX_AIODIO_IOMODE_IO6_IN 0x00001000 -#define AUX_AIODIO_IOMODE_IO6_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO6_W 2 +#define AUX_AIODIO_IOMODE_IO6_M 0x00003000 +#define AUX_AIODIO_IOMODE_IO6_S 12 +#define AUX_AIODIO_IOMODE_IO6_OPEN_SOURCE 0x00003000 +#define AUX_AIODIO_IOMODE_IO6_OPEN_DRAIN 0x00002000 +#define AUX_AIODIO_IOMODE_IO6_IN 0x00001000 +#define AUX_AIODIO_IOMODE_IO6_OUT 0x00000000 // Field: [11:10] IO5 // @@ -268,13 +268,13 @@ // When IOPOE bit 5 is 1: // The signal selected by IO5PSEL.SRC drives // AUXIO[8i+5]. -#define AUX_AIODIO_IOMODE_IO5_W 2 -#define AUX_AIODIO_IOMODE_IO5_M 0x00000C00 -#define AUX_AIODIO_IOMODE_IO5_S 10 -#define AUX_AIODIO_IOMODE_IO5_OPEN_SOURCE 0x00000C00 -#define AUX_AIODIO_IOMODE_IO5_OPEN_DRAIN 0x00000800 -#define AUX_AIODIO_IOMODE_IO5_IN 0x00000400 -#define AUX_AIODIO_IOMODE_IO5_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO5_W 2 +#define AUX_AIODIO_IOMODE_IO5_M 0x00000C00 +#define AUX_AIODIO_IOMODE_IO5_S 10 +#define AUX_AIODIO_IOMODE_IO5_OPEN_SOURCE 0x00000C00 +#define AUX_AIODIO_IOMODE_IO5_OPEN_DRAIN 0x00000800 +#define AUX_AIODIO_IOMODE_IO5_IN 0x00000400 +#define AUX_AIODIO_IOMODE_IO5_OUT 0x00000000 // Field: [9:8] IO4 // @@ -326,13 +326,13 @@ // When IOPOE bit 4 is 1: // The signal selected by IO4PSEL.SRC drives // AUXIO[8i+4]. -#define AUX_AIODIO_IOMODE_IO4_W 2 -#define AUX_AIODIO_IOMODE_IO4_M 0x00000300 -#define AUX_AIODIO_IOMODE_IO4_S 8 -#define AUX_AIODIO_IOMODE_IO4_OPEN_SOURCE 0x00000300 -#define AUX_AIODIO_IOMODE_IO4_OPEN_DRAIN 0x00000200 -#define AUX_AIODIO_IOMODE_IO4_IN 0x00000100 -#define AUX_AIODIO_IOMODE_IO4_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO4_W 2 +#define AUX_AIODIO_IOMODE_IO4_M 0x00000300 +#define AUX_AIODIO_IOMODE_IO4_S 8 +#define AUX_AIODIO_IOMODE_IO4_OPEN_SOURCE 0x00000300 +#define AUX_AIODIO_IOMODE_IO4_OPEN_DRAIN 0x00000200 +#define AUX_AIODIO_IOMODE_IO4_IN 0x00000100 +#define AUX_AIODIO_IOMODE_IO4_OUT 0x00000000 // Field: [7:6] IO3 // @@ -384,13 +384,13 @@ // When IOPOE bit 3 is 1: // The signal selected by IO3PSEL.SRC drives // AUXIO[8i+3]. -#define AUX_AIODIO_IOMODE_IO3_W 2 -#define AUX_AIODIO_IOMODE_IO3_M 0x000000C0 -#define AUX_AIODIO_IOMODE_IO3_S 6 -#define AUX_AIODIO_IOMODE_IO3_OPEN_SOURCE 0x000000C0 -#define AUX_AIODIO_IOMODE_IO3_OPEN_DRAIN 0x00000080 -#define AUX_AIODIO_IOMODE_IO3_IN 0x00000040 -#define AUX_AIODIO_IOMODE_IO3_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO3_W 2 +#define AUX_AIODIO_IOMODE_IO3_M 0x000000C0 +#define AUX_AIODIO_IOMODE_IO3_S 6 +#define AUX_AIODIO_IOMODE_IO3_OPEN_SOURCE 0x000000C0 +#define AUX_AIODIO_IOMODE_IO3_OPEN_DRAIN 0x00000080 +#define AUX_AIODIO_IOMODE_IO3_IN 0x00000040 +#define AUX_AIODIO_IOMODE_IO3_OUT 0x00000000 // Field: [5:4] IO2 // @@ -442,13 +442,13 @@ // When IOPOE bit 2 is 1: // The signal selected by IO2PSEL.SRC drives // AUXIO[8i+2]. -#define AUX_AIODIO_IOMODE_IO2_W 2 -#define AUX_AIODIO_IOMODE_IO2_M 0x00000030 -#define AUX_AIODIO_IOMODE_IO2_S 4 -#define AUX_AIODIO_IOMODE_IO2_OPEN_SOURCE 0x00000030 -#define AUX_AIODIO_IOMODE_IO2_OPEN_DRAIN 0x00000020 -#define AUX_AIODIO_IOMODE_IO2_IN 0x00000010 -#define AUX_AIODIO_IOMODE_IO2_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO2_W 2 +#define AUX_AIODIO_IOMODE_IO2_M 0x00000030 +#define AUX_AIODIO_IOMODE_IO2_S 4 +#define AUX_AIODIO_IOMODE_IO2_OPEN_SOURCE 0x00000030 +#define AUX_AIODIO_IOMODE_IO2_OPEN_DRAIN 0x00000020 +#define AUX_AIODIO_IOMODE_IO2_IN 0x00000010 +#define AUX_AIODIO_IOMODE_IO2_OUT 0x00000000 // Field: [3:2] IO1 // @@ -500,13 +500,13 @@ // When IOPOE bit 1 is 1: // The signal selected by IO1PSEL.SRC drives // AUXIO[8i+1]. -#define AUX_AIODIO_IOMODE_IO1_W 2 -#define AUX_AIODIO_IOMODE_IO1_M 0x0000000C -#define AUX_AIODIO_IOMODE_IO1_S 2 -#define AUX_AIODIO_IOMODE_IO1_OPEN_SOURCE 0x0000000C -#define AUX_AIODIO_IOMODE_IO1_OPEN_DRAIN 0x00000008 -#define AUX_AIODIO_IOMODE_IO1_IN 0x00000004 -#define AUX_AIODIO_IOMODE_IO1_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO1_W 2 +#define AUX_AIODIO_IOMODE_IO1_M 0x0000000C +#define AUX_AIODIO_IOMODE_IO1_S 2 +#define AUX_AIODIO_IOMODE_IO1_OPEN_SOURCE 0x0000000C +#define AUX_AIODIO_IOMODE_IO1_OPEN_DRAIN 0x00000008 +#define AUX_AIODIO_IOMODE_IO1_IN 0x00000004 +#define AUX_AIODIO_IOMODE_IO1_OUT 0x00000000 // Field: [1:0] IO0 // @@ -558,13 +558,13 @@ // When IOPOE bit 0 is 1: // The signal selected by IO0PSEL.SRC drives // AUXIO[8i+0]. -#define AUX_AIODIO_IOMODE_IO0_W 2 -#define AUX_AIODIO_IOMODE_IO0_M 0x00000003 -#define AUX_AIODIO_IOMODE_IO0_S 0 -#define AUX_AIODIO_IOMODE_IO0_OPEN_SOURCE 0x00000003 -#define AUX_AIODIO_IOMODE_IO0_OPEN_DRAIN 0x00000002 -#define AUX_AIODIO_IOMODE_IO0_IN 0x00000001 -#define AUX_AIODIO_IOMODE_IO0_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO0_W 2 +#define AUX_AIODIO_IOMODE_IO0_M 0x00000003 +#define AUX_AIODIO_IOMODE_IO0_S 0 +#define AUX_AIODIO_IOMODE_IO0_OPEN_SOURCE 0x00000003 +#define AUX_AIODIO_IOMODE_IO0_OPEN_DRAIN 0x00000002 +#define AUX_AIODIO_IOMODE_IO0_IN 0x00000001 +#define AUX_AIODIO_IOMODE_IO0_OUT 0x00000000 //***************************************************************************** // @@ -582,9 +582,9 @@ // value in GPIODIN. // You must disable the digital input buffer for analog input or pins that // float to avoid current leakage. -#define AUX_AIODIO_GPIODIE_IO7_0_W 8 -#define AUX_AIODIO_GPIODIE_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODIE_IO7_0_S 0 +#define AUX_AIODIO_GPIODIE_IO7_0_W 8 +#define AUX_AIODIO_GPIODIE_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODIE_IO7_0_S 0 //***************************************************************************** // @@ -597,9 +597,9 @@ // driven from source given in [IOnPSEL.*]. // Write 0 to bit index n in this bit vector to configure AUXIO[8i+n] to be // driven from bit n in GPIODOUT. -#define AUX_AIODIO_IOPOE_IO7_0_W 8 -#define AUX_AIODIO_IOPOE_IO7_0_M 0x000000FF -#define AUX_AIODIO_IOPOE_IO7_0_S 0 +#define AUX_AIODIO_IOPOE_IO7_0_W 8 +#define AUX_AIODIO_IOPOE_IO7_0_M 0x000000FF +#define AUX_AIODIO_IOPOE_IO7_0_S 0 //***************************************************************************** // @@ -613,9 +613,9 @@ // // You must clear bit n in IOPOE to connect bit n in this bit vector to // AUXIO[8i+n]. -#define AUX_AIODIO_GPIODOUT_IO7_0_W 8 -#define AUX_AIODIO_GPIODOUT_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODOUT_IO7_0_S 0 +#define AUX_AIODIO_GPIODOUT_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUT_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUT_IO7_0_S 0 //***************************************************************************** // @@ -626,9 +626,9 @@ // // Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit // n is set. Otherwise, bit n is read as 0. -#define AUX_AIODIO_GPIODIN_IO7_0_W 8 -#define AUX_AIODIO_GPIODIN_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODIN_IO7_0_S 0 +#define AUX_AIODIO_GPIODIN_IO7_0_W 8 +#define AUX_AIODIO_GPIODIN_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODIN_IO7_0_S 0 //***************************************************************************** // @@ -640,9 +640,9 @@ // Write 1 to bit index n in this bit vector to set GPIODOUT bit n. // // Read value is 0. -#define AUX_AIODIO_GPIODOUTSET_IO7_0_W 8 -#define AUX_AIODIO_GPIODOUTSET_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODOUTSET_IO7_0_S 0 +#define AUX_AIODIO_GPIODOUTSET_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTSET_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTSET_IO7_0_S 0 //***************************************************************************** // @@ -654,9 +654,9 @@ // Write 1 to bit index n in this bit vector to clear GPIODOUT bit n. // // Read value is 0. -#define AUX_AIODIO_GPIODOUTCLR_IO7_0_W 8 -#define AUX_AIODIO_GPIODOUTCLR_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODOUTCLR_IO7_0_S 0 +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_S 0 //***************************************************************************** // @@ -668,9 +668,9 @@ // Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n. // // Read value is 0. -#define AUX_AIODIO_GPIODOUTTGL_IO7_0_W 8 -#define AUX_AIODIO_GPIODOUTTGL_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODOUTTGL_IO7_0_S 0 +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_S 0 //***************************************************************************** // @@ -696,17 +696,17 @@ // AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. // AUX_EV_OBS Peripheral output mux selects event selected by // AUX_EVCTL:EVOBSCFG -#define AUX_AIODIO_IO0PSEL_SRC_W 3 -#define AUX_AIODIO_IO0PSEL_SRC_M 0x00000007 -#define AUX_AIODIO_IO0PSEL_SRC_S 0 -#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 -#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV3 0x00000006 -#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV2 0x00000005 -#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV1 0x00000004 -#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV0 0x00000003 -#define AUX_AIODIO_IO0PSEL_SRC_AUX_SPIM_MOSI 0x00000002 -#define AUX_AIODIO_IO0PSEL_SRC_AUX_SPIM_SCLK 0x00000001 -#define AUX_AIODIO_IO0PSEL_SRC_AUX_EV_OBS 0x00000000 +#define AUX_AIODIO_IO0PSEL_SRC_W 3 +#define AUX_AIODIO_IO0PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO0PSEL_SRC_S 0 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO0PSEL_SRC_AUX_EV_OBS 0x00000000 //***************************************************************************** // @@ -732,17 +732,17 @@ // AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. // AUX_EV_OBS Peripheral output mux selects event selected by // AUX_EVCTL:EVOBSCFG -#define AUX_AIODIO_IO1PSEL_SRC_W 3 -#define AUX_AIODIO_IO1PSEL_SRC_M 0x00000007 -#define AUX_AIODIO_IO1PSEL_SRC_S 0 -#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 -#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV3 0x00000006 -#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV2 0x00000005 -#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV1 0x00000004 -#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV0 0x00000003 -#define AUX_AIODIO_IO1PSEL_SRC_AUX_SPIM_MOSI 0x00000002 -#define AUX_AIODIO_IO1PSEL_SRC_AUX_SPIM_SCLK 0x00000001 -#define AUX_AIODIO_IO1PSEL_SRC_AUX_EV_OBS 0x00000000 +#define AUX_AIODIO_IO1PSEL_SRC_W 3 +#define AUX_AIODIO_IO1PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO1PSEL_SRC_S 0 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO1PSEL_SRC_AUX_EV_OBS 0x00000000 //***************************************************************************** // @@ -768,17 +768,17 @@ // AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. // AUX_EV_OBS Peripheral output mux selects event selected by // AUX_EVCTL:EVOBSCFG -#define AUX_AIODIO_IO2PSEL_SRC_W 3 -#define AUX_AIODIO_IO2PSEL_SRC_M 0x00000007 -#define AUX_AIODIO_IO2PSEL_SRC_S 0 -#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 -#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV3 0x00000006 -#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV2 0x00000005 -#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV1 0x00000004 -#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV0 0x00000003 -#define AUX_AIODIO_IO2PSEL_SRC_AUX_SPIM_MOSI 0x00000002 -#define AUX_AIODIO_IO2PSEL_SRC_AUX_SPIM_SCLK 0x00000001 -#define AUX_AIODIO_IO2PSEL_SRC_AUX_EV_OBS 0x00000000 +#define AUX_AIODIO_IO2PSEL_SRC_W 3 +#define AUX_AIODIO_IO2PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO2PSEL_SRC_S 0 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO2PSEL_SRC_AUX_EV_OBS 0x00000000 //***************************************************************************** // @@ -804,17 +804,17 @@ // AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. // AUX_EV_OBS Peripheral output mux selects event selected by // AUX_EVCTL:EVOBSCFG -#define AUX_AIODIO_IO3PSEL_SRC_W 3 -#define AUX_AIODIO_IO3PSEL_SRC_M 0x00000007 -#define AUX_AIODIO_IO3PSEL_SRC_S 0 -#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 -#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV3 0x00000006 -#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV2 0x00000005 -#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV1 0x00000004 -#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV0 0x00000003 -#define AUX_AIODIO_IO3PSEL_SRC_AUX_SPIM_MOSI 0x00000002 -#define AUX_AIODIO_IO3PSEL_SRC_AUX_SPIM_SCLK 0x00000001 -#define AUX_AIODIO_IO3PSEL_SRC_AUX_EV_OBS 0x00000000 +#define AUX_AIODIO_IO3PSEL_SRC_W 3 +#define AUX_AIODIO_IO3PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO3PSEL_SRC_S 0 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO3PSEL_SRC_AUX_EV_OBS 0x00000000 //***************************************************************************** // @@ -840,17 +840,17 @@ // AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. // AUX_EV_OBS Peripheral output mux selects event selected by // AUX_EVCTL:EVOBSCFG -#define AUX_AIODIO_IO4PSEL_SRC_W 3 -#define AUX_AIODIO_IO4PSEL_SRC_M 0x00000007 -#define AUX_AIODIO_IO4PSEL_SRC_S 0 -#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 -#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV3 0x00000006 -#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV2 0x00000005 -#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV1 0x00000004 -#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV0 0x00000003 -#define AUX_AIODIO_IO4PSEL_SRC_AUX_SPIM_MOSI 0x00000002 -#define AUX_AIODIO_IO4PSEL_SRC_AUX_SPIM_SCLK 0x00000001 -#define AUX_AIODIO_IO4PSEL_SRC_AUX_EV_OBS 0x00000000 +#define AUX_AIODIO_IO4PSEL_SRC_W 3 +#define AUX_AIODIO_IO4PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO4PSEL_SRC_S 0 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO4PSEL_SRC_AUX_EV_OBS 0x00000000 //***************************************************************************** // @@ -876,17 +876,17 @@ // AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. // AUX_EV_OBS Peripheral output mux selects event selected by // AUX_EVCTL:EVOBSCFG -#define AUX_AIODIO_IO5PSEL_SRC_W 3 -#define AUX_AIODIO_IO5PSEL_SRC_M 0x00000007 -#define AUX_AIODIO_IO5PSEL_SRC_S 0 -#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 -#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV3 0x00000006 -#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV2 0x00000005 -#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV1 0x00000004 -#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV0 0x00000003 -#define AUX_AIODIO_IO5PSEL_SRC_AUX_SPIM_MOSI 0x00000002 -#define AUX_AIODIO_IO5PSEL_SRC_AUX_SPIM_SCLK 0x00000001 -#define AUX_AIODIO_IO5PSEL_SRC_AUX_EV_OBS 0x00000000 +#define AUX_AIODIO_IO5PSEL_SRC_W 3 +#define AUX_AIODIO_IO5PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO5PSEL_SRC_S 0 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO5PSEL_SRC_AUX_EV_OBS 0x00000000 //***************************************************************************** // @@ -912,17 +912,17 @@ // AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. // AUX_EV_OBS Peripheral output mux selects event selected by // AUX_EVCTL:EVOBSCFG -#define AUX_AIODIO_IO6PSEL_SRC_W 3 -#define AUX_AIODIO_IO6PSEL_SRC_M 0x00000007 -#define AUX_AIODIO_IO6PSEL_SRC_S 0 -#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 -#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV3 0x00000006 -#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV2 0x00000005 -#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV1 0x00000004 -#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV0 0x00000003 -#define AUX_AIODIO_IO6PSEL_SRC_AUX_SPIM_MOSI 0x00000002 -#define AUX_AIODIO_IO6PSEL_SRC_AUX_SPIM_SCLK 0x00000001 -#define AUX_AIODIO_IO6PSEL_SRC_AUX_EV_OBS 0x00000000 +#define AUX_AIODIO_IO6PSEL_SRC_W 3 +#define AUX_AIODIO_IO6PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO6PSEL_SRC_S 0 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO6PSEL_SRC_AUX_EV_OBS 0x00000000 //***************************************************************************** // @@ -948,17 +948,17 @@ // AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. // AUX_EV_OBS Peripheral output mux selects event selected by // AUX_EVCTL:EVOBSCFG -#define AUX_AIODIO_IO7PSEL_SRC_W 3 -#define AUX_AIODIO_IO7PSEL_SRC_M 0x00000007 -#define AUX_AIODIO_IO7PSEL_SRC_S 0 -#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 -#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV3 0x00000006 -#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV2 0x00000005 -#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV1 0x00000004 -#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV0 0x00000003 -#define AUX_AIODIO_IO7PSEL_SRC_AUX_SPIM_MOSI 0x00000002 -#define AUX_AIODIO_IO7PSEL_SRC_AUX_SPIM_SCLK 0x00000001 -#define AUX_AIODIO_IO7PSEL_SRC_AUX_EV_OBS 0x00000000 +#define AUX_AIODIO_IO7PSEL_SRC_W 3 +#define AUX_AIODIO_IO7PSEL_SRC_M 0x00000007 +#define AUX_AIODIO_IO7PSEL_SRC_S 0 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV3 0x00000006 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV2 0x00000005 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV1 0x00000004 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV0 0x00000003 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_SPIM_MOSI 0x00000002 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_SPIM_SCLK 0x00000001 +#define AUX_AIODIO_IO7PSEL_SRC_AUX_EV_OBS 0x00000000 //***************************************************************************** // @@ -968,30 +968,30 @@ // Field: [7:6] IO3 // // See IOMODE.IO3. -#define AUX_AIODIO_IOMODEL_IO3_W 2 -#define AUX_AIODIO_IOMODEL_IO3_M 0x000000C0 -#define AUX_AIODIO_IOMODEL_IO3_S 6 +#define AUX_AIODIO_IOMODEL_IO3_W 2 +#define AUX_AIODIO_IOMODEL_IO3_M 0x000000C0 +#define AUX_AIODIO_IOMODEL_IO3_S 6 // Field: [5:4] IO2 // // See IOMODE.IO2. -#define AUX_AIODIO_IOMODEL_IO2_W 2 -#define AUX_AIODIO_IOMODEL_IO2_M 0x00000030 -#define AUX_AIODIO_IOMODEL_IO2_S 4 +#define AUX_AIODIO_IOMODEL_IO2_W 2 +#define AUX_AIODIO_IOMODEL_IO2_M 0x00000030 +#define AUX_AIODIO_IOMODEL_IO2_S 4 // Field: [3:2] IO1 // // See IOMODE.IO1. -#define AUX_AIODIO_IOMODEL_IO1_W 2 -#define AUX_AIODIO_IOMODEL_IO1_M 0x0000000C -#define AUX_AIODIO_IOMODEL_IO1_S 2 +#define AUX_AIODIO_IOMODEL_IO1_W 2 +#define AUX_AIODIO_IOMODEL_IO1_M 0x0000000C +#define AUX_AIODIO_IOMODEL_IO1_S 2 // Field: [1:0] IO0 // // See IOMODE.IO0. -#define AUX_AIODIO_IOMODEL_IO0_W 2 -#define AUX_AIODIO_IOMODEL_IO0_M 0x00000003 -#define AUX_AIODIO_IOMODEL_IO0_S 0 +#define AUX_AIODIO_IOMODEL_IO0_W 2 +#define AUX_AIODIO_IOMODEL_IO0_M 0x00000003 +#define AUX_AIODIO_IOMODEL_IO0_S 0 //***************************************************************************** // @@ -1001,30 +1001,29 @@ // Field: [7:6] IO7 // // See IOMODE.IO7. -#define AUX_AIODIO_IOMODEH_IO7_W 2 -#define AUX_AIODIO_IOMODEH_IO7_M 0x000000C0 -#define AUX_AIODIO_IOMODEH_IO7_S 6 +#define AUX_AIODIO_IOMODEH_IO7_W 2 +#define AUX_AIODIO_IOMODEH_IO7_M 0x000000C0 +#define AUX_AIODIO_IOMODEH_IO7_S 6 // Field: [5:4] IO6 // // See IOMODE.IO6. -#define AUX_AIODIO_IOMODEH_IO6_W 2 -#define AUX_AIODIO_IOMODEH_IO6_M 0x00000030 -#define AUX_AIODIO_IOMODEH_IO6_S 4 +#define AUX_AIODIO_IOMODEH_IO6_W 2 +#define AUX_AIODIO_IOMODEH_IO6_M 0x00000030 +#define AUX_AIODIO_IOMODEH_IO6_S 4 // Field: [3:2] IO5 // // See IOMODE.IO5. -#define AUX_AIODIO_IOMODEH_IO5_W 2 -#define AUX_AIODIO_IOMODEH_IO5_M 0x0000000C -#define AUX_AIODIO_IOMODEH_IO5_S 2 +#define AUX_AIODIO_IOMODEH_IO5_W 2 +#define AUX_AIODIO_IOMODEH_IO5_M 0x0000000C +#define AUX_AIODIO_IOMODEH_IO5_S 2 // Field: [1:0] IO4 // // See IOMODE.IO4. -#define AUX_AIODIO_IOMODEH_IO4_W 2 -#define AUX_AIODIO_IOMODEH_IO4_M 0x00000003 -#define AUX_AIODIO_IOMODEH_IO4_S 0 - +#define AUX_AIODIO_IOMODEH_IO4_W 2 +#define AUX_AIODIO_IOMODEH_IO4_M 0x00000003 +#define AUX_AIODIO_IOMODEH_IO4_S 0 #endif // __AUX_AIODIO__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_anaif.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_anaif.h index f9777f8..4ecea34 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_anaif.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_anaif.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_anaif_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_anaif_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_ANAIF_H__ #define __HW_AUX_ANAIF_H__ @@ -44,40 +44,40 @@ // //***************************************************************************** // ADC Control -#define AUX_ANAIF_O_ADCCTL 0x00000010 +#define AUX_ANAIF_O_ADCCTL 0x00000010 // ADC FIFO Status -#define AUX_ANAIF_O_ADCFIFOSTAT 0x00000014 +#define AUX_ANAIF_O_ADCFIFOSTAT 0x00000014 // ADC FIFO -#define AUX_ANAIF_O_ADCFIFO 0x00000018 +#define AUX_ANAIF_O_ADCFIFO 0x00000018 // ADC Trigger -#define AUX_ANAIF_O_ADCTRIG 0x0000001C +#define AUX_ANAIF_O_ADCTRIG 0x0000001C // Current Source Control -#define AUX_ANAIF_O_ISRCCTL 0x00000020 +#define AUX_ANAIF_O_ISRCCTL 0x00000020 // DAC Control -#define AUX_ANAIF_O_DACCTL 0x00000030 +#define AUX_ANAIF_O_DACCTL 0x00000030 // Low Power Mode Bias Control -#define AUX_ANAIF_O_LPMBIASCTL 0x00000034 +#define AUX_ANAIF_O_LPMBIASCTL 0x00000034 // DAC Sample Control -#define AUX_ANAIF_O_DACSMPLCTL 0x00000038 +#define AUX_ANAIF_O_DACSMPLCTL 0x00000038 // DAC Sample Configuration 0 -#define AUX_ANAIF_O_DACSMPLCFG0 0x0000003C +#define AUX_ANAIF_O_DACSMPLCFG0 0x0000003C // DAC Sample Configuration 1 -#define AUX_ANAIF_O_DACSMPLCFG1 0x00000040 +#define AUX_ANAIF_O_DACSMPLCFG1 0x00000040 // DAC Value -#define AUX_ANAIF_O_DACVALUE 0x00000044 +#define AUX_ANAIF_O_DACVALUE 0x00000044 // DAC Status -#define AUX_ANAIF_O_DACSTAT 0x00000048 +#define AUX_ANAIF_O_DACSTAT 0x00000048 //***************************************************************************** // @@ -90,12 +90,12 @@ // ENUMs: // FALL Set ADC trigger on falling edge of event source. // RISE Set ADC trigger on rising edge of event source. -#define AUX_ANAIF_ADCCTL_START_POL 0x00004000 -#define AUX_ANAIF_ADCCTL_START_POL_BITN 14 -#define AUX_ANAIF_ADCCTL_START_POL_M 0x00004000 -#define AUX_ANAIF_ADCCTL_START_POL_S 14 -#define AUX_ANAIF_ADCCTL_START_POL_FALL 0x00004000 -#define AUX_ANAIF_ADCCTL_START_POL_RISE 0x00000000 +#define AUX_ANAIF_ADCCTL_START_POL 0x00004000 +#define AUX_ANAIF_ADCCTL_START_POL_BITN 14 +#define AUX_ANAIF_ADCCTL_START_POL_M 0x00004000 +#define AUX_ANAIF_ADCCTL_START_POL_S 14 +#define AUX_ANAIF_ADCCTL_START_POL_FALL 0x00004000 +#define AUX_ANAIF_ADCCTL_START_POL_RISE 0x00000000 // Field: [13:8] START_SRC // @@ -164,66 +164,66 @@ // AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 // AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 // AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_ANAIF_ADCCTL_START_SRC_W 6 -#define AUX_ANAIF_ADCCTL_START_SRC_M 0x00003F00 -#define AUX_ANAIF_ADCCTL_START_SRC_S 8 -#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT 0x00003F00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_ISRC_RESET_N 0x00003800 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TDC_DONE 0x00003700 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER0_EV 0x00003600 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER1_EV 0x00003500 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_PULSE 0x00003400 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV3 0x00003300 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV2 0x00003200 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV1 0x00003100 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV0 0x00003000 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPB 0x00002F00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPA 0x00002E00 -#define AUX_ANAIF_ADCCTL_START_SRC_MCU_EV 0x00002B00 -#define AUX_ANAIF_ADCCTL_START_SRC_ACLK_REF 0x00002A00 -#define AUX_ANAIF_ADCCTL_START_SRC_VDDR_RECHARGE 0x00002900 -#define AUX_ANAIF_ADCCTL_START_SRC_MCU_ACTIVE 0x00002800 -#define AUX_ANAIF_ADCCTL_START_SRC_PWR_DWN 0x00002700 -#define AUX_ANAIF_ADCCTL_START_SRC_SCLK_LF 0x00002600 -#define AUX_ANAIF_ADCCTL_START_SRC_AON_BATMON_TEMP_UPD 0x00002500 -#define AUX_ANAIF_ADCCTL_START_SRC_AON_BATMON_BAT_UPD 0x00002400 -#define AUX_ANAIF_ADCCTL_START_SRC_AON_RTC_4KHZ 0x00002300 -#define AUX_ANAIF_ADCCTL_START_SRC_AON_RTC_CH2_DLY 0x00002200 -#define AUX_ANAIF_ADCCTL_START_SRC_AON_RTC_CH2 0x00002100 -#define AUX_ANAIF_ADCCTL_START_SRC_MANUAL_EV 0x00002000 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO31 0x00001F00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO30 0x00001E00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO29 0x00001D00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO28 0x00001C00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO27 0x00001B00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO26 0x00001A00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO25 0x00001900 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO24 0x00001800 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO23 0x00001700 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO22 0x00001600 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO21 0x00001500 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO20 0x00001400 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO19 0x00001300 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO18 0x00001200 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO17 0x00001100 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO16 0x00001000 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO15 0x00000F00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO14 0x00000E00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO13 0x00000D00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO12 0x00000C00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO11 0x00000B00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO10 0x00000A00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO9 0x00000900 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO8 0x00000800 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO7 0x00000700 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO6 0x00000600 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO5 0x00000500 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO4 0x00000400 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO3 0x00000300 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO2 0x00000200 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO1 0x00000100 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO0 0x00000000 +#define AUX_ANAIF_ADCCTL_START_SRC_W 6 +#define AUX_ANAIF_ADCCTL_START_SRC_M 0x00003F00 +#define AUX_ANAIF_ADCCTL_START_SRC_S 8 +#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT 0x00003F00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_ISRC_RESET_N 0x00003800 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TDC_DONE 0x00003700 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER0_EV 0x00003600 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER1_EV 0x00003500 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_PULSE 0x00003400 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV3 0x00003300 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV2 0x00003200 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV1 0x00003100 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV0 0x00003000 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPB 0x00002F00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPA 0x00002E00 +#define AUX_ANAIF_ADCCTL_START_SRC_MCU_EV 0x00002B00 +#define AUX_ANAIF_ADCCTL_START_SRC_ACLK_REF 0x00002A00 +#define AUX_ANAIF_ADCCTL_START_SRC_VDDR_RECHARGE 0x00002900 +#define AUX_ANAIF_ADCCTL_START_SRC_MCU_ACTIVE 0x00002800 +#define AUX_ANAIF_ADCCTL_START_SRC_PWR_DWN 0x00002700 +#define AUX_ANAIF_ADCCTL_START_SRC_SCLK_LF 0x00002600 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_BATMON_TEMP_UPD 0x00002500 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_BATMON_BAT_UPD 0x00002400 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_RTC_4KHZ 0x00002300 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_RTC_CH2_DLY 0x00002200 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_RTC_CH2 0x00002100 +#define AUX_ANAIF_ADCCTL_START_SRC_MANUAL_EV 0x00002000 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO31 0x00001F00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO30 0x00001E00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO29 0x00001D00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO28 0x00001C00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO27 0x00001B00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO26 0x00001A00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO25 0x00001900 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO24 0x00001800 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO23 0x00001700 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO22 0x00001600 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO21 0x00001500 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO20 0x00001400 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO19 0x00001300 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO18 0x00001200 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO17 0x00001100 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO16 0x00001000 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO15 0x00000F00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO14 0x00000E00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO13 0x00000D00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO12 0x00000C00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO11 0x00000B00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO10 0x00000A00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO9 0x00000900 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO8 0x00000800 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO7 0x00000700 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO6 0x00000600 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO5 0x00000500 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO4 0x00000400 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO3 0x00000300 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO2 0x00000200 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO1 0x00000100 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO0 0x00000000 // Field: [1:0] CMD // @@ -241,12 +241,12 @@ // clock cycles before it sets CMD to EN or DIS. // EN Enable ADC interface. // DIS Disable ADC interface. -#define AUX_ANAIF_ADCCTL_CMD_W 2 -#define AUX_ANAIF_ADCCTL_CMD_M 0x00000003 -#define AUX_ANAIF_ADCCTL_CMD_S 0 -#define AUX_ANAIF_ADCCTL_CMD_FLUSH 0x00000003 -#define AUX_ANAIF_ADCCTL_CMD_EN 0x00000001 -#define AUX_ANAIF_ADCCTL_CMD_DIS 0x00000000 +#define AUX_ANAIF_ADCCTL_CMD_W 2 +#define AUX_ANAIF_ADCCTL_CMD_M 0x00000003 +#define AUX_ANAIF_ADCCTL_CMD_S 0 +#define AUX_ANAIF_ADCCTL_CMD_FLUSH 0x00000003 +#define AUX_ANAIF_ADCCTL_CMD_EN 0x00000001 +#define AUX_ANAIF_ADCCTL_CMD_DIS 0x00000000 //***************************************************************************** // @@ -262,10 +262,10 @@ // // When the flag is set, the ADC FIFO write pointer is static. It is not // possible to add more samples to the ADC FIFO. Flush FIFO to clear the flag. -#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW 0x00000010 -#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_BITN 4 -#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M 0x00000010 -#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_S 4 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW 0x00000010 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_BITN 4 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M 0x00000010 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_S 4 // Field: [3] UNDERFLOW // @@ -276,10 +276,10 @@ // // When the flag is set, the ADC FIFO read pointer is static. Read returns the // previous sample that was read. Flush FIFO to clear the flag. -#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW 0x00000008 -#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_BITN 3 -#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M 0x00000008 -#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_S 3 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW 0x00000008 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_BITN 3 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M 0x00000008 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_S 3 // Field: [2] FULL // @@ -290,10 +290,10 @@ // // When the flag is set, it is not possible to add more samples to the ADC // FIFO. An attempt to add samples sets the OVERFLOW flag. -#define AUX_ANAIF_ADCFIFOSTAT_FULL 0x00000004 -#define AUX_ANAIF_ADCFIFOSTAT_FULL_BITN 2 -#define AUX_ANAIF_ADCFIFOSTAT_FULL_M 0x00000004 -#define AUX_ANAIF_ADCFIFOSTAT_FULL_S 2 +#define AUX_ANAIF_ADCFIFOSTAT_FULL 0x00000004 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_BITN 2 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_M 0x00000004 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_S 2 // Field: [1] ALMOST_FULL // @@ -302,10 +302,10 @@ // 0: There are less than 3 samples in the FIFO, or the FIFO is full. The FULL // flag is also asserted in the latter case. // 1: There are 3 samples in the FIFO, there is room for one more sample. -#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL 0x00000002 -#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_BITN 1 -#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M 0x00000002 -#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_S 1 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL 0x00000002 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_BITN 1 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M 0x00000002 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_S 1 // Field: [0] EMPTY // @@ -316,10 +316,10 @@ // // When the flag is set, read returns the previous sample that was read and // sets the UNDERFLOW flag. -#define AUX_ANAIF_ADCFIFOSTAT_EMPTY 0x00000001 -#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_BITN 0 -#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_M 0x00000001 -#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_S 0 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY 0x00000001 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_BITN 0 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_M 0x00000001 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_S 0 //***************************************************************************** // @@ -336,9 +336,9 @@ // Write: // Write dummy sample to FIFO. This is useful for code development when you do // not have real ADC samples. -#define AUX_ANAIF_ADCFIFO_DATA_W 12 -#define AUX_ANAIF_ADCFIFO_DATA_M 0x00000FFF -#define AUX_ANAIF_ADCFIFO_DATA_S 0 +#define AUX_ANAIF_ADCFIFO_DATA_W 12 +#define AUX_ANAIF_ADCFIFO_DATA_M 0x00000FFF +#define AUX_ANAIF_ADCFIFO_DATA_S 0 //***************************************************************************** // @@ -354,10 +354,10 @@ // // To manually trigger the ADC, you must set ADCCTL.START_SRC to NO_EVENT to // avoid conflict with event-driven ADC trigger. -#define AUX_ANAIF_ADCTRIG_START 0x00000001 -#define AUX_ANAIF_ADCTRIG_START_BITN 0 -#define AUX_ANAIF_ADCTRIG_START_M 0x00000001 -#define AUX_ANAIF_ADCTRIG_START_S 0 +#define AUX_ANAIF_ADCTRIG_START 0x00000001 +#define AUX_ANAIF_ADCTRIG_START_BITN 0 +#define AUX_ANAIF_ADCTRIG_START_M 0x00000001 +#define AUX_ANAIF_ADCTRIG_START_S 0 //***************************************************************************** // @@ -370,10 +370,10 @@ // // 0: ISRC drives 0 uA. // 1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN. -#define AUX_ANAIF_ISRCCTL_RESET_N 0x00000001 -#define AUX_ANAIF_ISRCCTL_RESET_N_BITN 0 -#define AUX_ANAIF_ISRCCTL_RESET_N_M 0x00000001 -#define AUX_ANAIF_ISRCCTL_RESET_N_S 0 +#define AUX_ANAIF_ISRCCTL_RESET_N 0x00000001 +#define AUX_ANAIF_ISRCCTL_RESET_N_BITN 0 +#define AUX_ANAIF_ISRCCTL_RESET_N_M 0x00000001 +#define AUX_ANAIF_ISRCCTL_RESET_N_S 0 //***************************************************************************** // @@ -394,10 +394,10 @@ // in Standby TI-RTOS power mode. The System CPU must set // AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to BUS_RATE to use the DAC in Active // and Idle TI-RTOS power modes. -#define AUX_ANAIF_DACCTL_DAC_EN 0x00000020 -#define AUX_ANAIF_DACCTL_DAC_EN_BITN 5 -#define AUX_ANAIF_DACCTL_DAC_EN_M 0x00000020 -#define AUX_ANAIF_DACCTL_DAC_EN_S 5 +#define AUX_ANAIF_DACCTL_DAC_EN 0x00000020 +#define AUX_ANAIF_DACCTL_DAC_EN_BITN 5 +#define AUX_ANAIF_DACCTL_DAC_EN_M 0x00000020 +#define AUX_ANAIF_DACCTL_DAC_EN_S 5 // Field: [4] DAC_BUFFER_EN // @@ -412,10 +412,10 @@ // Enable buffer when DAC_VOUT_SEL equals COMPA_IN. // // Do not enable the buffer when AUX_SYSIF:OPMODEREQ.REQ equals PDA or PDLP. -#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN 0x00000010 -#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN_BITN 4 -#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN_M 0x00000010 -#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN_S 4 +#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN 0x00000010 +#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN_BITN 4 +#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN_M 0x00000010 +#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN_S 4 // Field: [3] DAC_PRECHARGE_EN // @@ -432,10 +432,10 @@ // Otherwise, see ADI_4_AUX:MUX2.DAC_VREF_SEL for DAC output voltage range. // // Enable precharge 1 us before you enable the DAC and the buffer. -#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN 0x00000008 -#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_BITN 3 -#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_M 0x00000008 -#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_S 3 +#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN 0x00000008 +#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_BITN 3 +#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_M 0x00000008 +#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_S 3 // Field: [2:0] DAC_VOUT_SEL // @@ -463,13 +463,13 @@ // It is recommended to use // NC as intermediate step when you change // DAC_VOUT_SEL. -#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_W 3 -#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_M 0x00000007 -#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_S 0 -#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPA_IN 0x00000004 -#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPA_REF 0x00000002 -#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPB_REF 0x00000001 -#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_NC 0x00000000 +#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_W 3 +#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_M 0x00000007 +#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_S 0 +#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPA_IN 0x00000004 +#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPA_REF 0x00000002 +#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPB_REF 0x00000001 +#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_NC 0x00000000 //***************************************************************************** // @@ -484,10 +484,10 @@ // 1: Enable low power mode bias module. // // Set EN to 1 15 us before you enable the DAC or Comparator A. -#define AUX_ANAIF_LPMBIASCTL_EN 0x00000001 -#define AUX_ANAIF_LPMBIASCTL_EN_BITN 0 -#define AUX_ANAIF_LPMBIASCTL_EN_M 0x00000001 -#define AUX_ANAIF_LPMBIASCTL_EN_S 0 +#define AUX_ANAIF_LPMBIASCTL_EN 0x00000001 +#define AUX_ANAIF_LPMBIASCTL_EN_BITN 0 +#define AUX_ANAIF_LPMBIASCTL_EN_M 0x00000001 +#define AUX_ANAIF_LPMBIASCTL_EN_S 0 //***************************************************************************** // @@ -502,10 +502,10 @@ // when the current sample clock period completes. // 1: Enable DAC sample clock. DACSTAT must be 0 before you enable sample // clock. -#define AUX_ANAIF_DACSMPLCTL_EN 0x00000001 -#define AUX_ANAIF_DACSMPLCTL_EN_BITN 0 -#define AUX_ANAIF_DACSMPLCTL_EN_M 0x00000001 -#define AUX_ANAIF_DACSMPLCTL_EN_S 0 +#define AUX_ANAIF_DACSMPLCTL_EN 0x00000001 +#define AUX_ANAIF_DACSMPLCTL_EN_BITN 0 +#define AUX_ANAIF_DACSMPLCTL_EN_M 0x00000001 +#define AUX_ANAIF_DACSMPLCTL_EN_S 0 //***************************************************************************** // @@ -523,9 +523,9 @@ // 1: Divide by 2. // ... // 63: Divide by 64. -#define AUX_ANAIF_DACSMPLCFG0_CLKDIV_W 6 -#define AUX_ANAIF_DACSMPLCFG0_CLKDIV_M 0x0000003F -#define AUX_ANAIF_DACSMPLCFG0_CLKDIV_S 0 +#define AUX_ANAIF_DACSMPLCFG0_CLKDIV_W 6 +#define AUX_ANAIF_DACSMPLCFG0_CLKDIV_M 0x0000003F +#define AUX_ANAIF_DACSMPLCFG0_CLKDIV_S 0 //***************************************************************************** // @@ -540,10 +540,10 @@ // // 0: 2 periods // 1: 4 periods -#define AUX_ANAIF_DACSMPLCFG1_H_PER 0x00004000 -#define AUX_ANAIF_DACSMPLCFG1_H_PER_BITN 14 -#define AUX_ANAIF_DACSMPLCFG1_H_PER_M 0x00004000 -#define AUX_ANAIF_DACSMPLCFG1_H_PER_S 14 +#define AUX_ANAIF_DACSMPLCFG1_H_PER 0x00004000 +#define AUX_ANAIF_DACSMPLCFG1_H_PER_BITN 14 +#define AUX_ANAIF_DACSMPLCFG1_H_PER_M 0x00004000 +#define AUX_ANAIF_DACSMPLCFG1_H_PER_S 14 // Field: [13:12] L_PER // @@ -555,9 +555,9 @@ // 1: 2 periods // 2: 3 periods // 3: 4 periods -#define AUX_ANAIF_DACSMPLCFG1_L_PER_W 2 -#define AUX_ANAIF_DACSMPLCFG1_L_PER_M 0x00003000 -#define AUX_ANAIF_DACSMPLCFG1_L_PER_S 12 +#define AUX_ANAIF_DACSMPLCFG1_L_PER_W 2 +#define AUX_ANAIF_DACSMPLCFG1_L_PER_M 0x00003000 +#define AUX_ANAIF_DACSMPLCFG1_L_PER_S 12 // Field: [11:8] SETUP_CNT // @@ -569,9 +569,9 @@ // 1: 2 sample clock periods // ... // 15 : 16 sample clock periods -#define AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_W 4 -#define AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_M 0x00000F00 -#define AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_S 8 +#define AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_W 4 +#define AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_M 0x00000F00 +#define AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_S 8 // Field: [7:0] HOLD_INTERVAL // @@ -581,9 +581,9 @@ // period during hold phase. The sample clock is low when inactive. // // The range is 0 to 255. -#define AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_W 8 -#define AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_M 0x000000FF -#define AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_S 0 +#define AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_W 8 +#define AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_M 0x000000FF +#define AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_S 0 //***************************************************************************** // @@ -598,9 +598,9 @@ // // Only change VALUE when DACCTL.DAC_EN is 0. Then wait 1 us before you enable // the DAC. -#define AUX_ANAIF_DACVALUE_VALUE_W 8 -#define AUX_ANAIF_DACVALUE_VALUE_M 0x000000FF -#define AUX_ANAIF_DACVALUE_VALUE_S 0 +#define AUX_ANAIF_DACVALUE_VALUE_W 8 +#define AUX_ANAIF_DACVALUE_VALUE_M 0x000000FF +#define AUX_ANAIF_DACVALUE_VALUE_S 0 //***************************************************************************** // @@ -613,10 +613,10 @@ // // 0: Sample clock is disabled or setup phase is complete. // 1: Setup phase in progress. -#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE 0x00000002 -#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE_BITN 1 -#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE_M 0x00000002 -#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE_S 1 +#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE 0x00000002 +#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE_BITN 1 +#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE_M 0x00000002 +#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE_S 1 // Field: [0] HOLD_ACTIVE // @@ -624,10 +624,9 @@ // // 0: Sample clock is disabled or DAC is not in hold phase. // 1: Hold phase in progress. -#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE 0x00000001 -#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE_BITN 0 -#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE_M 0x00000001 -#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE_S 0 - +#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE 0x00000001 +#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE_BITN 0 +#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE_M 0x00000001 +#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE_S 0 #endif // __AUX_ANAIF__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_evctl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_evctl.h index 3bf1344..a3daea1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_evctl.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_evctl.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_evctl_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_evctl_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_EVCTL_H__ #define __HW_AUX_EVCTL_H__ @@ -44,82 +44,82 @@ // //***************************************************************************** // Event Status 0 -#define AUX_EVCTL_O_EVSTAT0 0x00000000 +#define AUX_EVCTL_O_EVSTAT0 0x00000000 // Event Status 1 -#define AUX_EVCTL_O_EVSTAT1 0x00000004 +#define AUX_EVCTL_O_EVSTAT1 0x00000004 // Event Status 2 -#define AUX_EVCTL_O_EVSTAT2 0x00000008 +#define AUX_EVCTL_O_EVSTAT2 0x00000008 // Event Status 3 -#define AUX_EVCTL_O_EVSTAT3 0x0000000C +#define AUX_EVCTL_O_EVSTAT3 0x0000000C // Sensor Controller Engine Wait Event Configuration 0 -#define AUX_EVCTL_O_SCEWEVCFG0 0x00000010 +#define AUX_EVCTL_O_SCEWEVCFG0 0x00000010 // Sensor Controller Engine Wait Event Configuration 1 -#define AUX_EVCTL_O_SCEWEVCFG1 0x00000014 +#define AUX_EVCTL_O_SCEWEVCFG1 0x00000014 // Direct Memory Access Control -#define AUX_EVCTL_O_DMACTL 0x00000018 +#define AUX_EVCTL_O_DMACTL 0x00000018 // Software Event Set -#define AUX_EVCTL_O_SWEVSET 0x00000020 +#define AUX_EVCTL_O_SWEVSET 0x00000020 // Events To AON Flags -#define AUX_EVCTL_O_EVTOAONFLAGS 0x00000024 +#define AUX_EVCTL_O_EVTOAONFLAGS 0x00000024 // Events To AON Polarity -#define AUX_EVCTL_O_EVTOAONPOL 0x00000028 +#define AUX_EVCTL_O_EVTOAONPOL 0x00000028 // Events To AON Clear -#define AUX_EVCTL_O_EVTOAONFLAGSCLR 0x0000002C +#define AUX_EVCTL_O_EVTOAONFLAGSCLR 0x0000002C // Events to MCU Flags -#define AUX_EVCTL_O_EVTOMCUFLAGS 0x00000030 +#define AUX_EVCTL_O_EVTOMCUFLAGS 0x00000030 // Event To MCU Polarity -#define AUX_EVCTL_O_EVTOMCUPOL 0x00000034 +#define AUX_EVCTL_O_EVTOMCUPOL 0x00000034 // Events To MCU Flags Clear -#define AUX_EVCTL_O_EVTOMCUFLAGSCLR 0x00000038 +#define AUX_EVCTL_O_EVTOMCUFLAGSCLR 0x00000038 // Combined Event To MCU Mask -#define AUX_EVCTL_O_COMBEVTOMCUMASK 0x0000003C +#define AUX_EVCTL_O_COMBEVTOMCUMASK 0x0000003C // Event Observation Configuration -#define AUX_EVCTL_O_EVOBSCFG 0x00000040 +#define AUX_EVCTL_O_EVOBSCFG 0x00000040 // Programmable Delay -#define AUX_EVCTL_O_PROGDLY 0x00000044 +#define AUX_EVCTL_O_PROGDLY 0x00000044 // Manual -#define AUX_EVCTL_O_MANUAL 0x00000048 +#define AUX_EVCTL_O_MANUAL 0x00000048 // Event Status 0 Low -#define AUX_EVCTL_O_EVSTAT0L 0x0000004C +#define AUX_EVCTL_O_EVSTAT0L 0x0000004C // Event Status 0 High -#define AUX_EVCTL_O_EVSTAT0H 0x00000050 +#define AUX_EVCTL_O_EVSTAT0H 0x00000050 // Event Status 1 Low -#define AUX_EVCTL_O_EVSTAT1L 0x00000054 +#define AUX_EVCTL_O_EVSTAT1L 0x00000054 // Event Status 1 High -#define AUX_EVCTL_O_EVSTAT1H 0x00000058 +#define AUX_EVCTL_O_EVSTAT1H 0x00000058 // Event Status 2 Low -#define AUX_EVCTL_O_EVSTAT2L 0x0000005C +#define AUX_EVCTL_O_EVSTAT2L 0x0000005C // Event Status 2 High -#define AUX_EVCTL_O_EVSTAT2H 0x00000060 +#define AUX_EVCTL_O_EVSTAT2H 0x00000060 // Event Status 3 Low -#define AUX_EVCTL_O_EVSTAT3L 0x00000064 +#define AUX_EVCTL_O_EVSTAT3L 0x00000064 // Event Status 3 High -#define AUX_EVCTL_O_EVSTAT3H 0x00000068 +#define AUX_EVCTL_O_EVSTAT3H 0x00000068 //***************************************************************************** // @@ -129,130 +129,130 @@ // Field: [15] AUXIO15 // // AUXIO15 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 7. -#define AUX_EVCTL_EVSTAT0_AUXIO15 0x00008000 -#define AUX_EVCTL_EVSTAT0_AUXIO15_BITN 15 -#define AUX_EVCTL_EVSTAT0_AUXIO15_M 0x00008000 -#define AUX_EVCTL_EVSTAT0_AUXIO15_S 15 +#define AUX_EVCTL_EVSTAT0_AUXIO15 0x00008000 +#define AUX_EVCTL_EVSTAT0_AUXIO15_BITN 15 +#define AUX_EVCTL_EVSTAT0_AUXIO15_M 0x00008000 +#define AUX_EVCTL_EVSTAT0_AUXIO15_S 15 // Field: [14] AUXIO14 // // AUXIO14 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 6. -#define AUX_EVCTL_EVSTAT0_AUXIO14 0x00004000 -#define AUX_EVCTL_EVSTAT0_AUXIO14_BITN 14 -#define AUX_EVCTL_EVSTAT0_AUXIO14_M 0x00004000 -#define AUX_EVCTL_EVSTAT0_AUXIO14_S 14 +#define AUX_EVCTL_EVSTAT0_AUXIO14 0x00004000 +#define AUX_EVCTL_EVSTAT0_AUXIO14_BITN 14 +#define AUX_EVCTL_EVSTAT0_AUXIO14_M 0x00004000 +#define AUX_EVCTL_EVSTAT0_AUXIO14_S 14 // Field: [13] AUXIO13 // // AUXIO13 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 5. -#define AUX_EVCTL_EVSTAT0_AUXIO13 0x00002000 -#define AUX_EVCTL_EVSTAT0_AUXIO13_BITN 13 -#define AUX_EVCTL_EVSTAT0_AUXIO13_M 0x00002000 -#define AUX_EVCTL_EVSTAT0_AUXIO13_S 13 +#define AUX_EVCTL_EVSTAT0_AUXIO13 0x00002000 +#define AUX_EVCTL_EVSTAT0_AUXIO13_BITN 13 +#define AUX_EVCTL_EVSTAT0_AUXIO13_M 0x00002000 +#define AUX_EVCTL_EVSTAT0_AUXIO13_S 13 // Field: [12] AUXIO12 // // AUXIO12 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 4. -#define AUX_EVCTL_EVSTAT0_AUXIO12 0x00001000 -#define AUX_EVCTL_EVSTAT0_AUXIO12_BITN 12 -#define AUX_EVCTL_EVSTAT0_AUXIO12_M 0x00001000 -#define AUX_EVCTL_EVSTAT0_AUXIO12_S 12 +#define AUX_EVCTL_EVSTAT0_AUXIO12 0x00001000 +#define AUX_EVCTL_EVSTAT0_AUXIO12_BITN 12 +#define AUX_EVCTL_EVSTAT0_AUXIO12_M 0x00001000 +#define AUX_EVCTL_EVSTAT0_AUXIO12_S 12 // Field: [11] AUXIO11 // // AUXIO11 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 3. -#define AUX_EVCTL_EVSTAT0_AUXIO11 0x00000800 -#define AUX_EVCTL_EVSTAT0_AUXIO11_BITN 11 -#define AUX_EVCTL_EVSTAT0_AUXIO11_M 0x00000800 -#define AUX_EVCTL_EVSTAT0_AUXIO11_S 11 +#define AUX_EVCTL_EVSTAT0_AUXIO11 0x00000800 +#define AUX_EVCTL_EVSTAT0_AUXIO11_BITN 11 +#define AUX_EVCTL_EVSTAT0_AUXIO11_M 0x00000800 +#define AUX_EVCTL_EVSTAT0_AUXIO11_S 11 // Field: [10] AUXIO10 // // AUXIO10 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 2. -#define AUX_EVCTL_EVSTAT0_AUXIO10 0x00000400 -#define AUX_EVCTL_EVSTAT0_AUXIO10_BITN 10 -#define AUX_EVCTL_EVSTAT0_AUXIO10_M 0x00000400 -#define AUX_EVCTL_EVSTAT0_AUXIO10_S 10 +#define AUX_EVCTL_EVSTAT0_AUXIO10 0x00000400 +#define AUX_EVCTL_EVSTAT0_AUXIO10_BITN 10 +#define AUX_EVCTL_EVSTAT0_AUXIO10_M 0x00000400 +#define AUX_EVCTL_EVSTAT0_AUXIO10_S 10 // Field: [9] AUXIO9 // // AUXIO9 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 1. -#define AUX_EVCTL_EVSTAT0_AUXIO9 0x00000200 -#define AUX_EVCTL_EVSTAT0_AUXIO9_BITN 9 -#define AUX_EVCTL_EVSTAT0_AUXIO9_M 0x00000200 -#define AUX_EVCTL_EVSTAT0_AUXIO9_S 9 +#define AUX_EVCTL_EVSTAT0_AUXIO9 0x00000200 +#define AUX_EVCTL_EVSTAT0_AUXIO9_BITN 9 +#define AUX_EVCTL_EVSTAT0_AUXIO9_M 0x00000200 +#define AUX_EVCTL_EVSTAT0_AUXIO9_S 9 // Field: [8] AUXIO8 // // AUXIO8 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 0. -#define AUX_EVCTL_EVSTAT0_AUXIO8 0x00000100 -#define AUX_EVCTL_EVSTAT0_AUXIO8_BITN 8 -#define AUX_EVCTL_EVSTAT0_AUXIO8_M 0x00000100 -#define AUX_EVCTL_EVSTAT0_AUXIO8_S 8 +#define AUX_EVCTL_EVSTAT0_AUXIO8 0x00000100 +#define AUX_EVCTL_EVSTAT0_AUXIO8_BITN 8 +#define AUX_EVCTL_EVSTAT0_AUXIO8_M 0x00000100 +#define AUX_EVCTL_EVSTAT0_AUXIO8_S 8 // Field: [7] AUXIO7 // // AUXIO7 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 7. -#define AUX_EVCTL_EVSTAT0_AUXIO7 0x00000080 -#define AUX_EVCTL_EVSTAT0_AUXIO7_BITN 7 -#define AUX_EVCTL_EVSTAT0_AUXIO7_M 0x00000080 -#define AUX_EVCTL_EVSTAT0_AUXIO7_S 7 +#define AUX_EVCTL_EVSTAT0_AUXIO7 0x00000080 +#define AUX_EVCTL_EVSTAT0_AUXIO7_BITN 7 +#define AUX_EVCTL_EVSTAT0_AUXIO7_M 0x00000080 +#define AUX_EVCTL_EVSTAT0_AUXIO7_S 7 // Field: [6] AUXIO6 // // AUXIO6 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 6. -#define AUX_EVCTL_EVSTAT0_AUXIO6 0x00000040 -#define AUX_EVCTL_EVSTAT0_AUXIO6_BITN 6 -#define AUX_EVCTL_EVSTAT0_AUXIO6_M 0x00000040 -#define AUX_EVCTL_EVSTAT0_AUXIO6_S 6 +#define AUX_EVCTL_EVSTAT0_AUXIO6 0x00000040 +#define AUX_EVCTL_EVSTAT0_AUXIO6_BITN 6 +#define AUX_EVCTL_EVSTAT0_AUXIO6_M 0x00000040 +#define AUX_EVCTL_EVSTAT0_AUXIO6_S 6 // Field: [5] AUXIO5 // // AUXIO5 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 5. -#define AUX_EVCTL_EVSTAT0_AUXIO5 0x00000020 -#define AUX_EVCTL_EVSTAT0_AUXIO5_BITN 5 -#define AUX_EVCTL_EVSTAT0_AUXIO5_M 0x00000020 -#define AUX_EVCTL_EVSTAT0_AUXIO5_S 5 +#define AUX_EVCTL_EVSTAT0_AUXIO5 0x00000020 +#define AUX_EVCTL_EVSTAT0_AUXIO5_BITN 5 +#define AUX_EVCTL_EVSTAT0_AUXIO5_M 0x00000020 +#define AUX_EVCTL_EVSTAT0_AUXIO5_S 5 // Field: [4] AUXIO4 // // AUXIO4 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 4. -#define AUX_EVCTL_EVSTAT0_AUXIO4 0x00000010 -#define AUX_EVCTL_EVSTAT0_AUXIO4_BITN 4 -#define AUX_EVCTL_EVSTAT0_AUXIO4_M 0x00000010 -#define AUX_EVCTL_EVSTAT0_AUXIO4_S 4 +#define AUX_EVCTL_EVSTAT0_AUXIO4 0x00000010 +#define AUX_EVCTL_EVSTAT0_AUXIO4_BITN 4 +#define AUX_EVCTL_EVSTAT0_AUXIO4_M 0x00000010 +#define AUX_EVCTL_EVSTAT0_AUXIO4_S 4 // Field: [3] AUXIO3 // // AUXIO3 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 3. -#define AUX_EVCTL_EVSTAT0_AUXIO3 0x00000008 -#define AUX_EVCTL_EVSTAT0_AUXIO3_BITN 3 -#define AUX_EVCTL_EVSTAT0_AUXIO3_M 0x00000008 -#define AUX_EVCTL_EVSTAT0_AUXIO3_S 3 +#define AUX_EVCTL_EVSTAT0_AUXIO3 0x00000008 +#define AUX_EVCTL_EVSTAT0_AUXIO3_BITN 3 +#define AUX_EVCTL_EVSTAT0_AUXIO3_M 0x00000008 +#define AUX_EVCTL_EVSTAT0_AUXIO3_S 3 // Field: [2] AUXIO2 // // AUXIO2 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 2. -#define AUX_EVCTL_EVSTAT0_AUXIO2 0x00000004 -#define AUX_EVCTL_EVSTAT0_AUXIO2_BITN 2 -#define AUX_EVCTL_EVSTAT0_AUXIO2_M 0x00000004 -#define AUX_EVCTL_EVSTAT0_AUXIO2_S 2 +#define AUX_EVCTL_EVSTAT0_AUXIO2 0x00000004 +#define AUX_EVCTL_EVSTAT0_AUXIO2_BITN 2 +#define AUX_EVCTL_EVSTAT0_AUXIO2_M 0x00000004 +#define AUX_EVCTL_EVSTAT0_AUXIO2_S 2 // Field: [1] AUXIO1 // // AUXIO1 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 1. -#define AUX_EVCTL_EVSTAT0_AUXIO1 0x00000002 -#define AUX_EVCTL_EVSTAT0_AUXIO1_BITN 1 -#define AUX_EVCTL_EVSTAT0_AUXIO1_M 0x00000002 -#define AUX_EVCTL_EVSTAT0_AUXIO1_S 1 +#define AUX_EVCTL_EVSTAT0_AUXIO1 0x00000002 +#define AUX_EVCTL_EVSTAT0_AUXIO1_BITN 1 +#define AUX_EVCTL_EVSTAT0_AUXIO1_M 0x00000002 +#define AUX_EVCTL_EVSTAT0_AUXIO1_S 1 // Field: [0] AUXIO0 // // AUXIO0 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 0. -#define AUX_EVCTL_EVSTAT0_AUXIO0 0x00000001 -#define AUX_EVCTL_EVSTAT0_AUXIO0_BITN 0 -#define AUX_EVCTL_EVSTAT0_AUXIO0_M 0x00000001 -#define AUX_EVCTL_EVSTAT0_AUXIO0_S 0 +#define AUX_EVCTL_EVSTAT0_AUXIO0 0x00000001 +#define AUX_EVCTL_EVSTAT0_AUXIO0_BITN 0 +#define AUX_EVCTL_EVSTAT0_AUXIO0_M 0x00000001 +#define AUX_EVCTL_EVSTAT0_AUXIO0_S 0 //***************************************************************************** // @@ -262,130 +262,130 @@ // Field: [15] AUXIO31 // // AUXIO31 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 7. -#define AUX_EVCTL_EVSTAT1_AUXIO31 0x00008000 -#define AUX_EVCTL_EVSTAT1_AUXIO31_BITN 15 -#define AUX_EVCTL_EVSTAT1_AUXIO31_M 0x00008000 -#define AUX_EVCTL_EVSTAT1_AUXIO31_S 15 +#define AUX_EVCTL_EVSTAT1_AUXIO31 0x00008000 +#define AUX_EVCTL_EVSTAT1_AUXIO31_BITN 15 +#define AUX_EVCTL_EVSTAT1_AUXIO31_M 0x00008000 +#define AUX_EVCTL_EVSTAT1_AUXIO31_S 15 // Field: [14] AUXIO30 // // AUXIO30 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 6. -#define AUX_EVCTL_EVSTAT1_AUXIO30 0x00004000 -#define AUX_EVCTL_EVSTAT1_AUXIO30_BITN 14 -#define AUX_EVCTL_EVSTAT1_AUXIO30_M 0x00004000 -#define AUX_EVCTL_EVSTAT1_AUXIO30_S 14 +#define AUX_EVCTL_EVSTAT1_AUXIO30 0x00004000 +#define AUX_EVCTL_EVSTAT1_AUXIO30_BITN 14 +#define AUX_EVCTL_EVSTAT1_AUXIO30_M 0x00004000 +#define AUX_EVCTL_EVSTAT1_AUXIO30_S 14 // Field: [13] AUXIO29 // // AUXIO29 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 5. -#define AUX_EVCTL_EVSTAT1_AUXIO29 0x00002000 -#define AUX_EVCTL_EVSTAT1_AUXIO29_BITN 13 -#define AUX_EVCTL_EVSTAT1_AUXIO29_M 0x00002000 -#define AUX_EVCTL_EVSTAT1_AUXIO29_S 13 +#define AUX_EVCTL_EVSTAT1_AUXIO29 0x00002000 +#define AUX_EVCTL_EVSTAT1_AUXIO29_BITN 13 +#define AUX_EVCTL_EVSTAT1_AUXIO29_M 0x00002000 +#define AUX_EVCTL_EVSTAT1_AUXIO29_S 13 // Field: [12] AUXIO28 // // AUXIO28 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 4. -#define AUX_EVCTL_EVSTAT1_AUXIO28 0x00001000 -#define AUX_EVCTL_EVSTAT1_AUXIO28_BITN 12 -#define AUX_EVCTL_EVSTAT1_AUXIO28_M 0x00001000 -#define AUX_EVCTL_EVSTAT1_AUXIO28_S 12 +#define AUX_EVCTL_EVSTAT1_AUXIO28 0x00001000 +#define AUX_EVCTL_EVSTAT1_AUXIO28_BITN 12 +#define AUX_EVCTL_EVSTAT1_AUXIO28_M 0x00001000 +#define AUX_EVCTL_EVSTAT1_AUXIO28_S 12 // Field: [11] AUXIO27 // // AUXIO27 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 3. -#define AUX_EVCTL_EVSTAT1_AUXIO27 0x00000800 -#define AUX_EVCTL_EVSTAT1_AUXIO27_BITN 11 -#define AUX_EVCTL_EVSTAT1_AUXIO27_M 0x00000800 -#define AUX_EVCTL_EVSTAT1_AUXIO27_S 11 +#define AUX_EVCTL_EVSTAT1_AUXIO27 0x00000800 +#define AUX_EVCTL_EVSTAT1_AUXIO27_BITN 11 +#define AUX_EVCTL_EVSTAT1_AUXIO27_M 0x00000800 +#define AUX_EVCTL_EVSTAT1_AUXIO27_S 11 // Field: [10] AUXIO26 // // AUXIO26 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 2. -#define AUX_EVCTL_EVSTAT1_AUXIO26 0x00000400 -#define AUX_EVCTL_EVSTAT1_AUXIO26_BITN 10 -#define AUX_EVCTL_EVSTAT1_AUXIO26_M 0x00000400 -#define AUX_EVCTL_EVSTAT1_AUXIO26_S 10 +#define AUX_EVCTL_EVSTAT1_AUXIO26 0x00000400 +#define AUX_EVCTL_EVSTAT1_AUXIO26_BITN 10 +#define AUX_EVCTL_EVSTAT1_AUXIO26_M 0x00000400 +#define AUX_EVCTL_EVSTAT1_AUXIO26_S 10 // Field: [9] AUXIO25 // // AUXIO25 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 1. -#define AUX_EVCTL_EVSTAT1_AUXIO25 0x00000200 -#define AUX_EVCTL_EVSTAT1_AUXIO25_BITN 9 -#define AUX_EVCTL_EVSTAT1_AUXIO25_M 0x00000200 -#define AUX_EVCTL_EVSTAT1_AUXIO25_S 9 +#define AUX_EVCTL_EVSTAT1_AUXIO25 0x00000200 +#define AUX_EVCTL_EVSTAT1_AUXIO25_BITN 9 +#define AUX_EVCTL_EVSTAT1_AUXIO25_M 0x00000200 +#define AUX_EVCTL_EVSTAT1_AUXIO25_S 9 // Field: [8] AUXIO24 // // AUXIO24 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 0. -#define AUX_EVCTL_EVSTAT1_AUXIO24 0x00000100 -#define AUX_EVCTL_EVSTAT1_AUXIO24_BITN 8 -#define AUX_EVCTL_EVSTAT1_AUXIO24_M 0x00000100 -#define AUX_EVCTL_EVSTAT1_AUXIO24_S 8 +#define AUX_EVCTL_EVSTAT1_AUXIO24 0x00000100 +#define AUX_EVCTL_EVSTAT1_AUXIO24_BITN 8 +#define AUX_EVCTL_EVSTAT1_AUXIO24_M 0x00000100 +#define AUX_EVCTL_EVSTAT1_AUXIO24_S 8 // Field: [7] AUXIO23 // // AUXIO23 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 7. -#define AUX_EVCTL_EVSTAT1_AUXIO23 0x00000080 -#define AUX_EVCTL_EVSTAT1_AUXIO23_BITN 7 -#define AUX_EVCTL_EVSTAT1_AUXIO23_M 0x00000080 -#define AUX_EVCTL_EVSTAT1_AUXIO23_S 7 +#define AUX_EVCTL_EVSTAT1_AUXIO23 0x00000080 +#define AUX_EVCTL_EVSTAT1_AUXIO23_BITN 7 +#define AUX_EVCTL_EVSTAT1_AUXIO23_M 0x00000080 +#define AUX_EVCTL_EVSTAT1_AUXIO23_S 7 // Field: [6] AUXIO22 // // AUXIO22 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 6. -#define AUX_EVCTL_EVSTAT1_AUXIO22 0x00000040 -#define AUX_EVCTL_EVSTAT1_AUXIO22_BITN 6 -#define AUX_EVCTL_EVSTAT1_AUXIO22_M 0x00000040 -#define AUX_EVCTL_EVSTAT1_AUXIO22_S 6 +#define AUX_EVCTL_EVSTAT1_AUXIO22 0x00000040 +#define AUX_EVCTL_EVSTAT1_AUXIO22_BITN 6 +#define AUX_EVCTL_EVSTAT1_AUXIO22_M 0x00000040 +#define AUX_EVCTL_EVSTAT1_AUXIO22_S 6 // Field: [5] AUXIO21 // // AUXIO21 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 5. -#define AUX_EVCTL_EVSTAT1_AUXIO21 0x00000020 -#define AUX_EVCTL_EVSTAT1_AUXIO21_BITN 5 -#define AUX_EVCTL_EVSTAT1_AUXIO21_M 0x00000020 -#define AUX_EVCTL_EVSTAT1_AUXIO21_S 5 +#define AUX_EVCTL_EVSTAT1_AUXIO21 0x00000020 +#define AUX_EVCTL_EVSTAT1_AUXIO21_BITN 5 +#define AUX_EVCTL_EVSTAT1_AUXIO21_M 0x00000020 +#define AUX_EVCTL_EVSTAT1_AUXIO21_S 5 // Field: [4] AUXIO20 // // AUXIO20 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 4. -#define AUX_EVCTL_EVSTAT1_AUXIO20 0x00000010 -#define AUX_EVCTL_EVSTAT1_AUXIO20_BITN 4 -#define AUX_EVCTL_EVSTAT1_AUXIO20_M 0x00000010 -#define AUX_EVCTL_EVSTAT1_AUXIO20_S 4 +#define AUX_EVCTL_EVSTAT1_AUXIO20 0x00000010 +#define AUX_EVCTL_EVSTAT1_AUXIO20_BITN 4 +#define AUX_EVCTL_EVSTAT1_AUXIO20_M 0x00000010 +#define AUX_EVCTL_EVSTAT1_AUXIO20_S 4 // Field: [3] AUXIO19 // // AUXIO19 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 3. -#define AUX_EVCTL_EVSTAT1_AUXIO19 0x00000008 -#define AUX_EVCTL_EVSTAT1_AUXIO19_BITN 3 -#define AUX_EVCTL_EVSTAT1_AUXIO19_M 0x00000008 -#define AUX_EVCTL_EVSTAT1_AUXIO19_S 3 +#define AUX_EVCTL_EVSTAT1_AUXIO19 0x00000008 +#define AUX_EVCTL_EVSTAT1_AUXIO19_BITN 3 +#define AUX_EVCTL_EVSTAT1_AUXIO19_M 0x00000008 +#define AUX_EVCTL_EVSTAT1_AUXIO19_S 3 // Field: [2] AUXIO18 // // AUXIO18 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 2. -#define AUX_EVCTL_EVSTAT1_AUXIO18 0x00000004 -#define AUX_EVCTL_EVSTAT1_AUXIO18_BITN 2 -#define AUX_EVCTL_EVSTAT1_AUXIO18_M 0x00000004 -#define AUX_EVCTL_EVSTAT1_AUXIO18_S 2 +#define AUX_EVCTL_EVSTAT1_AUXIO18 0x00000004 +#define AUX_EVCTL_EVSTAT1_AUXIO18_BITN 2 +#define AUX_EVCTL_EVSTAT1_AUXIO18_M 0x00000004 +#define AUX_EVCTL_EVSTAT1_AUXIO18_S 2 // Field: [1] AUXIO17 // // AUXIO17 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 1. -#define AUX_EVCTL_EVSTAT1_AUXIO17 0x00000002 -#define AUX_EVCTL_EVSTAT1_AUXIO17_BITN 1 -#define AUX_EVCTL_EVSTAT1_AUXIO17_M 0x00000002 -#define AUX_EVCTL_EVSTAT1_AUXIO17_S 1 +#define AUX_EVCTL_EVSTAT1_AUXIO17 0x00000002 +#define AUX_EVCTL_EVSTAT1_AUXIO17_BITN 1 +#define AUX_EVCTL_EVSTAT1_AUXIO17_M 0x00000002 +#define AUX_EVCTL_EVSTAT1_AUXIO17_S 1 // Field: [0] AUXIO16 // // AUXIO16 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 0. -#define AUX_EVCTL_EVSTAT1_AUXIO16 0x00000001 -#define AUX_EVCTL_EVSTAT1_AUXIO16_BITN 0 -#define AUX_EVCTL_EVSTAT1_AUXIO16_M 0x00000001 -#define AUX_EVCTL_EVSTAT1_AUXIO16_S 0 +#define AUX_EVCTL_EVSTAT1_AUXIO16 0x00000001 +#define AUX_EVCTL_EVSTAT1_AUXIO16_BITN 0 +#define AUX_EVCTL_EVSTAT1_AUXIO16_M 0x00000001 +#define AUX_EVCTL_EVSTAT1_AUXIO16_S 0 //***************************************************************************** // @@ -397,143 +397,143 @@ // Comparator B output. // Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPB_SYNC_RATE sets the // synchronization rate for this event. -#define AUX_EVCTL_EVSTAT2_AUX_COMPB 0x00008000 -#define AUX_EVCTL_EVSTAT2_AUX_COMPB_BITN 15 -#define AUX_EVCTL_EVSTAT2_AUX_COMPB_M 0x00008000 -#define AUX_EVCTL_EVSTAT2_AUX_COMPB_S 15 +#define AUX_EVCTL_EVSTAT2_AUX_COMPB 0x00008000 +#define AUX_EVCTL_EVSTAT2_AUX_COMPB_BITN 15 +#define AUX_EVCTL_EVSTAT2_AUX_COMPB_M 0x00008000 +#define AUX_EVCTL_EVSTAT2_AUX_COMPB_S 15 // Field: [14] AUX_COMPA // // Comparator A output. // Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPA_SYNC_RATE sets the // synchronization rate for this event. -#define AUX_EVCTL_EVSTAT2_AUX_COMPA 0x00004000 -#define AUX_EVCTL_EVSTAT2_AUX_COMPA_BITN 14 -#define AUX_EVCTL_EVSTAT2_AUX_COMPA_M 0x00004000 -#define AUX_EVCTL_EVSTAT2_AUX_COMPA_S 14 +#define AUX_EVCTL_EVSTAT2_AUX_COMPA 0x00004000 +#define AUX_EVCTL_EVSTAT2_AUX_COMPA_BITN 14 +#define AUX_EVCTL_EVSTAT2_AUX_COMPA_M 0x00004000 +#define AUX_EVCTL_EVSTAT2_AUX_COMPA_S 14 // Field: [13] MCU_OBSMUX1 // // Observation input 1 from IOC. // This event is configured by IOC:OBSAUXOUTPUT.SEL1. -#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1 0x00002000 -#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1_BITN 13 -#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1_M 0x00002000 -#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1_S 13 +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1 0x00002000 +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1_BITN 13 +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1_M 0x00002000 +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1_S 13 // Field: [12] MCU_OBSMUX0 // // Observation input 0 from IOC. // This event is configured by IOC:OBSAUXOUTPUT.SEL0 and can be overridden by // IOC:OBSAUXOUTPUT.SEL_MISC. -#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0 0x00001000 -#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0_BITN 12 -#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0_M 0x00001000 -#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0_S 12 +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0 0x00001000 +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0_BITN 12 +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0_M 0x00001000 +#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0_S 12 // Field: [11] MCU_EV // // Event from EVENT configured by EVENT:AUXSEL0. -#define AUX_EVCTL_EVSTAT2_MCU_EV 0x00000800 -#define AUX_EVCTL_EVSTAT2_MCU_EV_BITN 11 -#define AUX_EVCTL_EVSTAT2_MCU_EV_M 0x00000800 -#define AUX_EVCTL_EVSTAT2_MCU_EV_S 11 +#define AUX_EVCTL_EVSTAT2_MCU_EV 0x00000800 +#define AUX_EVCTL_EVSTAT2_MCU_EV_BITN 11 +#define AUX_EVCTL_EVSTAT2_MCU_EV_M 0x00000800 +#define AUX_EVCTL_EVSTAT2_MCU_EV_S 11 // Field: [10] ACLK_REF // // TDC reference clock. // It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by // AUX_SYSIF:TDCREFCLKCTL.REQ. -#define AUX_EVCTL_EVSTAT2_ACLK_REF 0x00000400 -#define AUX_EVCTL_EVSTAT2_ACLK_REF_BITN 10 -#define AUX_EVCTL_EVSTAT2_ACLK_REF_M 0x00000400 -#define AUX_EVCTL_EVSTAT2_ACLK_REF_S 10 +#define AUX_EVCTL_EVSTAT2_ACLK_REF 0x00000400 +#define AUX_EVCTL_EVSTAT2_ACLK_REF_BITN 10 +#define AUX_EVCTL_EVSTAT2_ACLK_REF_M 0x00000400 +#define AUX_EVCTL_EVSTAT2_ACLK_REF_S 10 // Field: [9] VDDR_RECHARGE // // Event is high during VDDR recharge. -#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE 0x00000200 -#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE_BITN 9 -#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE_M 0x00000200 -#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE_S 9 +#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE 0x00000200 +#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE_BITN 9 +#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE_M 0x00000200 +#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE_S 9 // Field: [8] MCU_ACTIVE // // Event is high while system(MCU, AUX, or JTAG domains) is active or // transitions to active (GLDO or DCDC power supply state). Event is not high // during VDDR recharge. -#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE 0x00000100 -#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE_BITN 8 -#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE_M 0x00000100 -#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE_S 8 +#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE 0x00000100 +#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE_BITN 8 +#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE_M 0x00000100 +#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE_S 8 // Field: [7] PWR_DWN // // Event is high while system(MCU, AUX, or JTAG domains) is in powerdown (uLDO // power supply). -#define AUX_EVCTL_EVSTAT2_PWR_DWN 0x00000080 -#define AUX_EVCTL_EVSTAT2_PWR_DWN_BITN 7 -#define AUX_EVCTL_EVSTAT2_PWR_DWN_M 0x00000080 -#define AUX_EVCTL_EVSTAT2_PWR_DWN_S 7 +#define AUX_EVCTL_EVSTAT2_PWR_DWN 0x00000080 +#define AUX_EVCTL_EVSTAT2_PWR_DWN_BITN 7 +#define AUX_EVCTL_EVSTAT2_PWR_DWN_M 0x00000080 +#define AUX_EVCTL_EVSTAT2_PWR_DWN_S 7 // Field: [6] SCLK_LF // // SCLK_LF clock -#define AUX_EVCTL_EVSTAT2_SCLK_LF 0x00000040 -#define AUX_EVCTL_EVSTAT2_SCLK_LF_BITN 6 -#define AUX_EVCTL_EVSTAT2_SCLK_LF_M 0x00000040 -#define AUX_EVCTL_EVSTAT2_SCLK_LF_S 6 +#define AUX_EVCTL_EVSTAT2_SCLK_LF 0x00000040 +#define AUX_EVCTL_EVSTAT2_SCLK_LF_BITN 6 +#define AUX_EVCTL_EVSTAT2_SCLK_LF_M 0x00000040 +#define AUX_EVCTL_EVSTAT2_SCLK_LF_S 6 // Field: [5] AON_BATMON_TEMP_UPD // // Event is high for two SCLK_MF clock periods when there is an update of // AON_BATMON:TEMP. -#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD 0x00000020 -#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD_BITN 5 -#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD_M 0x00000020 -#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD_S 5 +#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD 0x00000020 +#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD_BITN 5 +#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD_M 0x00000020 +#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD_S 5 // Field: [4] AON_BATMON_BAT_UPD // // Event is high for two SCLK_MF clock periods when there is an update of // AON_BATMON:BAT. -#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD 0x00000010 -#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD_BITN 4 -#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD_M 0x00000010 -#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD_S 4 +#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD 0x00000010 +#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD_BITN 4 +#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD_M 0x00000010 +#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD_S 4 // Field: [3] AON_RTC_4KHZ // // AON_RTC:SUBSEC.VALUE bit 19. // AON_RTC:CTL.RTC_4KHZ_EN enables this event. -#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ 0x00000008 -#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ_BITN 3 -#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ_M 0x00000008 -#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ_S 3 +#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ 0x00000008 +#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ_BITN 3 +#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ_M 0x00000008 +#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ_S 3 // Field: [2] AON_RTC_CH2_DLY // // AON_RTC:EVFLAGS.CH2 delayed by AON_RTC:CTL.EV_DELAY configuration. -#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY 0x00000004 -#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY_BITN 2 -#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY_M 0x00000004 -#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY_S 2 +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY 0x00000004 +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY_BITN 2 +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY_M 0x00000004 +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY_S 2 // Field: [1] AON_RTC_CH2 // // AON_RTC:EVFLAGS.CH2. -#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2 0x00000002 -#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_BITN 1 -#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_M 0x00000002 -#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_S 1 +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2 0x00000002 +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_BITN 1 +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_M 0x00000002 +#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_S 1 // Field: [0] MANUAL_EV // // Programmable event. See MANUAL for description. -#define AUX_EVCTL_EVSTAT2_MANUAL_EV 0x00000001 -#define AUX_EVCTL_EVSTAT2_MANUAL_EV_BITN 0 -#define AUX_EVCTL_EVSTAT2_MANUAL_EV_M 0x00000001 -#define AUX_EVCTL_EVSTAT2_MANUAL_EV_S 0 +#define AUX_EVCTL_EVSTAT2_MANUAL_EV 0x00000001 +#define AUX_EVCTL_EVSTAT2_MANUAL_EV_BITN 0 +#define AUX_EVCTL_EVSTAT2_MANUAL_EV_M 0x00000001 +#define AUX_EVCTL_EVSTAT2_MANUAL_EV_S 0 //***************************************************************************** // @@ -543,42 +543,42 @@ // Field: [15] AUX_TIMER2_CLKSWITCH_RDY // // AUX_SYSIF:TIMER2CLKSWITCH.RDY -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY 0x00008000 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY_BITN 15 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY_M 0x00008000 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY_S 15 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY 0x00008000 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY_BITN 15 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY_M 0x00008000 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY_S 15 // Field: [14] AUX_DAC_HOLD_ACTIVE // // AUX_ANAIF:DACSTAT.HOLD_ACTIVE -#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE 0x00004000 -#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE_BITN 14 -#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE_M 0x00004000 -#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE_S 14 +#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE 0x00004000 +#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE_BITN 14 +#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE_M 0x00004000 +#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE_S 14 // Field: [13] AUX_SMPH_AUTOTAKE_DONE // // See AUX_SMPH:AUTOTAKE.SMPH_ID for description. -#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE 0x00002000 -#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE_BITN 13 -#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE_M 0x00002000 -#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE_S 13 +#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE 0x00002000 +#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE_BITN 13 +#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE_M 0x00002000 +#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE_S 13 // Field: [12] AUX_ADC_FIFO_NOT_EMPTY // // AUX_ANAIF:ADCFIFOSTAT.EMPTY negated -#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY 0x00001000 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY_BITN 12 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY_M 0x00001000 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY_S 12 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY 0x00001000 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY_BITN 12 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY_M 0x00001000 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY_S 12 // Field: [11] AUX_ADC_FIFO_ALMOST_FULL // // AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL -#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL 0x00000800 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL_BITN 11 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000800 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL_S 11 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL 0x00000800 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL_BITN 11 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000800 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL_S 11 // Field: [10] AUX_ADC_IRQ // @@ -593,101 +593,101 @@ // AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW // // Bit 7 in UDMA0:DONEMASK must be 0. -#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ 0x00000400 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ_BITN 10 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ_S 10 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ_S 10 // Field: [9] AUX_ADC_DONE // // AUX_ANAIF ADC conversion done event. // Event is synchronized at AUX bus rate. -#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE 0x00000200 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE_BITN 9 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE_M 0x00000200 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE_S 9 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE 0x00000200 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE_BITN 9 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE_M 0x00000200 +#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE_S 9 // Field: [8] AUX_ISRC_RESET_N // // AUX_ANAIF:ISRCCTL.RESET_N -#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N 0x00000100 -#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N_BITN 8 -#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N_M 0x00000100 -#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N_S 8 +#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N 0x00000100 +#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N_BITN 8 +#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N_M 0x00000100 +#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N_S 8 // Field: [7] AUX_TDC_DONE // // AUX_TDC:STAT.DONE -#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE 0x00000080 -#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE_BITN 7 -#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE_M 0x00000080 -#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE_S 7 +#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE 0x00000080 +#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE_BITN 7 +#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE_M 0x00000080 +#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE_S 7 // Field: [6] AUX_TIMER0_EV // // AUX_TIMER0_EV event, see AUX_TIMER01:T0TARGET for description. -#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV 0x00000040 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV_BITN 6 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV_M 0x00000040 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV_S 6 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV 0x00000040 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV_BITN 6 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV_M 0x00000040 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV_S 6 // Field: [5] AUX_TIMER1_EV // // AUX_TIMER1_EV event, see AUX_TIMER01:T1TARGET for description. -#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV 0x00000020 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV_BITN 5 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV_S 5 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV_S 5 // Field: [4] AUX_TIMER2_PULSE // // AUX_TIMER2 pulse event. // Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the // synchronization rate for this event. -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE 0x00000010 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE_BITN 4 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE_M 0x00000010 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE_S 4 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE 0x00000010 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE_BITN 4 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE_M 0x00000010 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE_S 4 // Field: [3] AUX_TIMER2_EV3 // // AUX_TIMER2 event output 3. // Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the // synchronization rate for this event. -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3 0x00000008 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3_BITN 3 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3_M 0x00000008 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3_S 3 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3 0x00000008 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3_BITN 3 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3_M 0x00000008 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3_S 3 // Field: [2] AUX_TIMER2_EV2 // // AUX_TIMER2 event output 2. // Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the // synchronization rate for this event. -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2 0x00000004 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2_BITN 2 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2_M 0x00000004 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2_S 2 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2 0x00000004 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2_BITN 2 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2_M 0x00000004 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2_S 2 // Field: [1] AUX_TIMER2_EV1 // // AUX_TIMER2 event output 1. // Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the // synchronization rate for this event. -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1 0x00000002 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1_BITN 1 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1_M 0x00000002 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1_S 1 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1 0x00000002 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1_BITN 1 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1_M 0x00000002 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1_S 1 // Field: [0] AUX_TIMER2_EV0 // // AUX_TIMER2 event output 0. // Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the // synchronization rate for this event. -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0 0x00000001 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0_BITN 0 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0_M 0x00000001 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0_S 0 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0 0x00000001 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0_BITN 0 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0_M 0x00000001 +#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0_S 0 //***************************************************************************** // @@ -700,10 +700,10 @@ // // 0: Disable event combination. // 1: Enable event combination. -#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN 0x00000040 -#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN_BITN 6 -#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN_M 0x00000040 -#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN_S 6 +#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN 0x00000040 +#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN_BITN 6 +#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN_M 0x00000040 +#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN_S 6 // Field: [5:0] EV0_SEL // @@ -774,73 +774,73 @@ // AUXIO2 EVSTAT0.AUXIO2 // AUXIO1 EVSTAT0.AUXIO1 // AUXIO0 EVSTAT0.AUXIO0 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_W 6 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_M 0x0000003F -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_S 0 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_CLKSWITCH_RDY 0x0000003F -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_DAC_HOLD_ACTIVE 0x0000003E -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_SMPH_AUTOTAKE_DONE 0x0000003D -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_IRQ 0x0000003A -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_DONE 0x00000039 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ISRC_RESET_N 0x00000038 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TDC_DONE 0x00000037 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER0_EV 0x00000036 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER1_EV 0x00000035 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_PULSE 0x00000034 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV3 0x00000033 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV2 0x00000032 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV1 0x00000031 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV0 0x00000030 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_COMPB 0x0000002F -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_COMPA 0x0000002E -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_OBSMUX1 0x0000002D -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_OBSMUX0 0x0000002C -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_EV 0x0000002B -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_ACLK_REF 0x0000002A -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_VDDR_RECHARGE 0x00000029 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_ACTIVE 0x00000028 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_PWR_DWN 0x00000027 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_SCLK_LF 0x00000026 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_BATMON_TEMP_UPD 0x00000025 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_BATMON_BAT_UPD 0x00000024 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_RTC_4KHZ 0x00000023 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_RTC_CH2_DLY 0x00000022 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_RTC_CH2 0x00000021 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_PROG_DLY_IDLE 0x00000020 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO31 0x0000001F -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO30 0x0000001E -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO29 0x0000001D -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO28 0x0000001C -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO27 0x0000001B -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO26 0x0000001A -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO25 0x00000019 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO24 0x00000018 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO23 0x00000017 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO22 0x00000016 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO21 0x00000015 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO20 0x00000014 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO19 0x00000013 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO18 0x00000012 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO17 0x00000011 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO16 0x00000010 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO15 0x0000000F -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO14 0x0000000E -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO13 0x0000000D -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO12 0x0000000C -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO11 0x0000000B -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO10 0x0000000A -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO9 0x00000009 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO8 0x00000008 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO7 0x00000007 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO6 0x00000006 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO5 0x00000005 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO4 0x00000004 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO3 0x00000003 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO2 0x00000002 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO1 0x00000001 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO0 0x00000000 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_W 6 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_M 0x0000003F +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_S 0 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_CLKSWITCH_RDY 0x0000003F +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_DAC_HOLD_ACTIVE 0x0000003E +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_IRQ 0x0000003A +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_DONE 0x00000039 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ISRC_RESET_N 0x00000038 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TDC_DONE 0x00000037 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER0_EV 0x00000036 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER1_EV 0x00000035 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_PULSE 0x00000034 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV3 0x00000033 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV2 0x00000032 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV1 0x00000031 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV0 0x00000030 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_COMPB 0x0000002F +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_COMPA 0x0000002E +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_OBSMUX1 0x0000002D +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_OBSMUX0 0x0000002C +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_EV 0x0000002B +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_ACLK_REF 0x0000002A +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_VDDR_RECHARGE 0x00000029 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_ACTIVE 0x00000028 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_PWR_DWN 0x00000027 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_SCLK_LF 0x00000026 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_RTC_4KHZ 0x00000023 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_RTC_CH2_DLY 0x00000022 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_RTC_CH2 0x00000021 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_PROG_DLY_IDLE 0x00000020 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO31 0x0000001F +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO30 0x0000001E +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO29 0x0000001D +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO28 0x0000001C +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO27 0x0000001B +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO26 0x0000001A +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO25 0x00000019 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO24 0x00000018 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO23 0x00000017 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO22 0x00000016 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO21 0x00000015 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO20 0x00000014 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO19 0x00000013 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO18 0x00000012 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO17 0x00000011 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO16 0x00000010 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO15 0x0000000F +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO14 0x0000000E +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO13 0x0000000D +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO12 0x0000000C +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO11 0x0000000B +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO10 0x0000000A +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO9 0x00000009 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO8 0x00000008 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO7 0x00000007 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO6 0x00000006 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO5 0x00000005 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO4 0x00000004 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO3 0x00000003 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO2 0x00000002 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO1 0x00000001 +#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO0 0x00000000 //***************************************************************************** // @@ -860,10 +860,10 @@ // // 0: Non-inverted. // 1: Inverted. -#define AUX_EVCTL_SCEWEVCFG1_EV0_POL 0x00000080 -#define AUX_EVCTL_SCEWEVCFG1_EV0_POL_BITN 7 -#define AUX_EVCTL_SCEWEVCFG1_EV0_POL_M 0x00000080 -#define AUX_EVCTL_SCEWEVCFG1_EV0_POL_S 7 +#define AUX_EVCTL_SCEWEVCFG1_EV0_POL 0x00000080 +#define AUX_EVCTL_SCEWEVCFG1_EV0_POL_BITN 7 +#define AUX_EVCTL_SCEWEVCFG1_EV0_POL_M 0x00000080 +#define AUX_EVCTL_SCEWEVCFG1_EV0_POL_S 7 // Field: [6] EV1_POL // @@ -878,10 +878,10 @@ // // 0: Non-inverted. // 1: Inverted. -#define AUX_EVCTL_SCEWEVCFG1_EV1_POL 0x00000040 -#define AUX_EVCTL_SCEWEVCFG1_EV1_POL_BITN 6 -#define AUX_EVCTL_SCEWEVCFG1_EV1_POL_M 0x00000040 -#define AUX_EVCTL_SCEWEVCFG1_EV1_POL_S 6 +#define AUX_EVCTL_SCEWEVCFG1_EV1_POL 0x00000040 +#define AUX_EVCTL_SCEWEVCFG1_EV1_POL_BITN 6 +#define AUX_EVCTL_SCEWEVCFG1_EV1_POL_M 0x00000040 +#define AUX_EVCTL_SCEWEVCFG1_EV1_POL_S 6 // Field: [5:0] EV1_SEL // @@ -952,73 +952,73 @@ // AUXIO2 EVSTAT0.AUXIO2 // AUXIO1 EVSTAT0.AUXIO1 // AUXIO0 EVSTAT0.AUXIO0 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_W 6 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_M 0x0000003F -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_S 0 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_CLKSWITCH_RDY 0x0000003F -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_DAC_HOLD_ACTIVE 0x0000003E -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_SMPH_AUTOTAKE_DONE 0x0000003D -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_IRQ 0x0000003A -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_DONE 0x00000039 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ISRC_RESET_N 0x00000038 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TDC_DONE 0x00000037 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER0_EV 0x00000036 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER1_EV 0x00000035 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_PULSE 0x00000034 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV3 0x00000033 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV2 0x00000032 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV1 0x00000031 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV0 0x00000030 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_COMPB 0x0000002F -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_COMPA 0x0000002E -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_OBSMUX1 0x0000002D -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_OBSMUX0 0x0000002C -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_EV 0x0000002B -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_ACLK_REF 0x0000002A -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_VDDR_RECHARGE 0x00000029 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_ACTIVE 0x00000028 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_PWR_DWN 0x00000027 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_SCLK_LF 0x00000026 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_BATMON_TEMP_UPD 0x00000025 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_BATMON_BAT_UPD 0x00000024 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_RTC_4KHZ 0x00000023 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_RTC_CH2_DLY 0x00000022 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_RTC_CH2 0x00000021 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_PROG_DLY_IDLE 0x00000020 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO31 0x0000001F -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO30 0x0000001E -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO29 0x0000001D -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO28 0x0000001C -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO27 0x0000001B -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO26 0x0000001A -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO25 0x00000019 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO24 0x00000018 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO23 0x00000017 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO22 0x00000016 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO21 0x00000015 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO20 0x00000014 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO19 0x00000013 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO18 0x00000012 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO17 0x00000011 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO16 0x00000010 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO15 0x0000000F -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO14 0x0000000E -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO13 0x0000000D -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO12 0x0000000C -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO11 0x0000000B -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO10 0x0000000A -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO9 0x00000009 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO8 0x00000008 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO7 0x00000007 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO6 0x00000006 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO5 0x00000005 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO4 0x00000004 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO3 0x00000003 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO2 0x00000002 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO1 0x00000001 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO0 0x00000000 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_W 6 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_M 0x0000003F +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_S 0 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_CLKSWITCH_RDY 0x0000003F +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_DAC_HOLD_ACTIVE 0x0000003E +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_IRQ 0x0000003A +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_DONE 0x00000039 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ISRC_RESET_N 0x00000038 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TDC_DONE 0x00000037 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER0_EV 0x00000036 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER1_EV 0x00000035 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_PULSE 0x00000034 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV3 0x00000033 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV2 0x00000032 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV1 0x00000031 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV0 0x00000030 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_COMPB 0x0000002F +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_COMPA 0x0000002E +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_OBSMUX1 0x0000002D +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_OBSMUX0 0x0000002C +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_EV 0x0000002B +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_ACLK_REF 0x0000002A +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_VDDR_RECHARGE 0x00000029 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_ACTIVE 0x00000028 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_PWR_DWN 0x00000027 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_SCLK_LF 0x00000026 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_RTC_4KHZ 0x00000023 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_RTC_CH2_DLY 0x00000022 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_RTC_CH2 0x00000021 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_PROG_DLY_IDLE 0x00000020 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO31 0x0000001F +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO30 0x0000001E +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO29 0x0000001D +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO28 0x0000001C +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO27 0x0000001B +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO26 0x0000001A +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO25 0x00000019 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO24 0x00000018 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO23 0x00000017 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO22 0x00000016 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO21 0x00000015 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO20 0x00000014 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO19 0x00000013 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO18 0x00000012 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO17 0x00000011 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO16 0x00000010 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO15 0x0000000F +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO14 0x0000000E +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO13 0x0000000D +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO12 0x0000000C +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO11 0x0000000B +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO10 0x0000000A +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO9 0x00000009 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO8 0x00000008 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO7 0x00000007 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO6 0x00000006 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO5 0x00000005 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO4 0x00000004 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO3 0x00000003 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO2 0x00000002 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO1 0x00000001 +#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO0 0x00000000 //***************************************************************************** // @@ -1033,12 +1033,12 @@ // when the condition configured in SEL is met. // BURST Burst requests are generated on UDMA0 channel 7 // when the condition configured in SEL is met. -#define AUX_EVCTL_DMACTL_REQ_MODE 0x00000004 -#define AUX_EVCTL_DMACTL_REQ_MODE_BITN 2 -#define AUX_EVCTL_DMACTL_REQ_MODE_M 0x00000004 -#define AUX_EVCTL_DMACTL_REQ_MODE_S 2 -#define AUX_EVCTL_DMACTL_REQ_MODE_SINGLE 0x00000004 -#define AUX_EVCTL_DMACTL_REQ_MODE_BURST 0x00000000 +#define AUX_EVCTL_DMACTL_REQ_MODE 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_BITN 2 +#define AUX_EVCTL_DMACTL_REQ_MODE_M 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_S 2 +#define AUX_EVCTL_DMACTL_REQ_MODE_SINGLE 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_BURST 0x00000000 // Field: [1] EN // @@ -1046,10 +1046,10 @@ // // 0: Disable UDMA0 interface to ADC. // 1: Enable UDMA0 interface to ADC. -#define AUX_EVCTL_DMACTL_EN 0x00000002 -#define AUX_EVCTL_DMACTL_EN_BITN 1 -#define AUX_EVCTL_DMACTL_EN_M 0x00000002 -#define AUX_EVCTL_DMACTL_EN_S 1 +#define AUX_EVCTL_DMACTL_EN 0x00000002 +#define AUX_EVCTL_DMACTL_EN_BITN 1 +#define AUX_EVCTL_DMACTL_EN_M 0x00000002 +#define AUX_EVCTL_DMACTL_EN_S 1 // Field: [0] SEL // @@ -1060,12 +1060,12 @@ // FIFO is almost full (3/4 full). // AUX_ADC_FIFO_NOT_EMPTY UDMA0 trigger event will be generated when there // are samples in the ADC FIFO. -#define AUX_EVCTL_DMACTL_SEL 0x00000001 -#define AUX_EVCTL_DMACTL_SEL_BITN 0 -#define AUX_EVCTL_DMACTL_SEL_M 0x00000001 -#define AUX_EVCTL_DMACTL_SEL_S 0 -#define AUX_EVCTL_DMACTL_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x00000001 -#define AUX_EVCTL_DMACTL_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x00000000 +#define AUX_EVCTL_DMACTL_SEL 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_BITN 0 +#define AUX_EVCTL_DMACTL_SEL_M 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_S 0 +#define AUX_EVCTL_DMACTL_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x00000000 //***************************************************************************** // @@ -1078,10 +1078,10 @@ // // 0: No effect. // 1: Set software event flag 2. -#define AUX_EVCTL_SWEVSET_SWEV2 0x00000004 -#define AUX_EVCTL_SWEVSET_SWEV2_BITN 2 -#define AUX_EVCTL_SWEVSET_SWEV2_M 0x00000004 -#define AUX_EVCTL_SWEVSET_SWEV2_S 2 +#define AUX_EVCTL_SWEVSET_SWEV2 0x00000004 +#define AUX_EVCTL_SWEVSET_SWEV2_BITN 2 +#define AUX_EVCTL_SWEVSET_SWEV2_M 0x00000004 +#define AUX_EVCTL_SWEVSET_SWEV2_S 2 // Field: [1] SWEV1 // @@ -1089,10 +1089,10 @@ // // 0: No effect. // 1: Set software event flag 1. -#define AUX_EVCTL_SWEVSET_SWEV1 0x00000002 -#define AUX_EVCTL_SWEVSET_SWEV1_BITN 1 -#define AUX_EVCTL_SWEVSET_SWEV1_M 0x00000002 -#define AUX_EVCTL_SWEVSET_SWEV1_S 1 +#define AUX_EVCTL_SWEVSET_SWEV1 0x00000002 +#define AUX_EVCTL_SWEVSET_SWEV1_BITN 1 +#define AUX_EVCTL_SWEVSET_SWEV1_M 0x00000002 +#define AUX_EVCTL_SWEVSET_SWEV1_S 1 // Field: [0] SWEV0 // @@ -1100,10 +1100,10 @@ // // 0: No effect. // 1: Set software event flag 0. -#define AUX_EVCTL_SWEVSET_SWEV0 0x00000001 -#define AUX_EVCTL_SWEVSET_SWEV0_BITN 0 -#define AUX_EVCTL_SWEVSET_SWEV0_M 0x00000001 -#define AUX_EVCTL_SWEVSET_SWEV0_S 0 +#define AUX_EVCTL_SWEVSET_SWEV0 0x00000001 +#define AUX_EVCTL_SWEVSET_SWEV0_BITN 0 +#define AUX_EVCTL_SWEVSET_SWEV0_M 0x00000001 +#define AUX_EVCTL_SWEVSET_SWEV0_S 0 //***************************************************************************** // @@ -1114,79 +1114,79 @@ // // This event flag is set when level selected by EVTOAONPOL.AUX_TIMER1_EV // occurs on EVSTAT3.AUX_TIMER1_EV. -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV 0x00000100 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV_BITN 8 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV_M 0x00000100 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV_S 8 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV_S 8 // Field: [7] AUX_TIMER0_EV // // This event flag is set when level selected by EVTOAONPOL.AUX_TIMER0_EV // occurs on EVSTAT3.AUX_TIMER0_EV. -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV 0x00000080 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV_BITN 7 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV_M 0x00000080 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV_S 7 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV_S 7 // Field: [6] AUX_TDC_DONE // // This event flag is set when level selected by EVTOAONPOL.AUX_TDC_DONE occurs // on EVSTAT3.AUX_TDC_DONE. -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE 0x00000040 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE_BITN 6 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE_S 6 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE_S 6 // Field: [5] AUX_ADC_DONE // // This event flag is set when level selected by EVTOAONPOL.AUX_ADC_DONE occurs // on EVSTAT3.AUX_ADC_DONE. -#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE 0x00000020 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE_BITN 5 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE_M 0x00000020 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE_S 5 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE_S 5 // Field: [4] AUX_COMPB // // This event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on // EVSTAT2.AUX_COMPB. -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB 0x00000010 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_BITN 4 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_M 0x00000010 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_S 4 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_S 4 // Field: [3] AUX_COMPA // // This event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on // EVSTAT2.AUX_COMPA. -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA 0x00000008 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_BITN 3 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_M 0x00000008 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_S 3 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_S 3 // Field: [2] SWEV2 // // This event flag is set when software writes a 1 to SWEVSET.SWEV2. -#define AUX_EVCTL_EVTOAONFLAGS_SWEV2 0x00000004 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_BITN 2 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_M 0x00000004 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_S 2 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_BITN 2 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_M 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_S 2 // Field: [1] SWEV1 // // This event flag is set when software writes a 1 to SWEVSET.SWEV1. -#define AUX_EVCTL_EVTOAONFLAGS_SWEV1 0x00000002 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_BITN 1 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_M 0x00000002 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_S 1 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_BITN 1 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_M 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_S 1 // Field: [0] SWEV0 // // This event flag is set when software writes a 1 to SWEVSET.SWEV0. -#define AUX_EVCTL_EVTOAONFLAGS_SWEV0 0x00000001 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_BITN 0 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_M 0x00000001 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_S 0 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_BITN 0 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_M 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_S 0 //***************************************************************************** // @@ -1200,12 +1200,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV 0x00000100 -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_BITN 8 -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_M 0x00000100 -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_S 8 -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_LOW 0x00000100 -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_HIGH 0x00000000 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_S 8 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_LOW 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_HIGH 0x00000000 // Field: [7] AUX_TIMER0_EV // @@ -1214,12 +1214,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV 0x00000080 -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_BITN 7 -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_M 0x00000080 -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_S 7 -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_LOW 0x00000080 -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_HIGH 0x00000000 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_S 7 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_LOW 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_HIGH 0x00000000 // Field: [6] AUX_TDC_DONE // @@ -1227,12 +1227,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE 0x00000040 -#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_BITN 6 -#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_S 6 -#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_LOW 0x00000040 -#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_HIGH 0x00000000 +#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_S 6 +#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_LOW 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_HIGH 0x00000000 // Field: [5] AUX_ADC_DONE // @@ -1241,12 +1241,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE 0x00000020 -#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_BITN 5 -#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_M 0x00000020 -#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_S 5 -#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_LOW 0x00000020 -#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_HIGH 0x00000000 +#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_S 5 +#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_LOW 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_HIGH 0x00000000 // Field: [4] AUX_COMPB // @@ -1254,12 +1254,12 @@ // ENUMs: // FALL Falling edge // RISE Rising edge -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB 0x00000010 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_BITN 4 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_M 0x00000010 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_S 4 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_FALL 0x00000010 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_RISE 0x00000000 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_S 4 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_FALL 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_RISE 0x00000000 // Field: [3] AUX_COMPA // @@ -1267,12 +1267,12 @@ // ENUMs: // FALL Falling edge // RISE Rising edge -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA 0x00000008 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_BITN 3 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_M 0x00000008 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_S 3 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_FALL 0x00000008 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_RISE 0x00000000 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_S 3 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_FALL 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_RISE 0x00000000 //***************************************************************************** // @@ -1284,90 +1284,90 @@ // Write 1 to clear EVTOAONFLAGS.AUX_TIMER1_EV. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV 0x00000100 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV_BITN 8 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV_M 0x00000100 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV_S 8 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV_S 8 // Field: [7] AUX_TIMER0_EV // // Write 1 to clear EVTOAONFLAGS.AUX_TIMER0_EV. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV 0x00000080 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV_BITN 7 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV_M 0x00000080 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV_S 7 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV_S 7 // Field: [6] AUX_TDC_DONE // // Write 1 to clear EVTOAONFLAGS.AUX_TDC_DONE. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE 0x00000040 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE_BITN 6 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE_S 6 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE_S 6 // Field: [5] AUX_ADC_DONE // // Write 1 to clear EVTOAONFLAGS.AUX_ADC_DONE. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE 0x00000020 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE_BITN 5 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE_M 0x00000020 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE_S 5 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE_S 5 // Field: [4] AUX_COMPB // // Write 1 to clear EVTOAONFLAGS.AUX_COMPB. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB 0x00000010 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_BITN 4 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_M 0x00000010 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_S 4 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_S 4 // Field: [3] AUX_COMPA // // Write 1 to clear EVTOAONFLAGS.AUX_COMPA. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA 0x00000008 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_BITN 3 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_M 0x00000008 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_S 3 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_S 3 // Field: [2] SWEV2 // // Write 1 to clear EVTOAONFLAGS.SWEV2. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2 0x00000004 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_BITN 2 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_M 0x00000004 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_S 2 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_BITN 2 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_M 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_S 2 // Field: [1] SWEV1 // // Write 1 to clear EVTOAONFLAGS.SWEV1. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1 0x00000002 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_BITN 1 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_M 0x00000002 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_S 1 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_BITN 1 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_M 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_S 1 // Field: [0] SWEV0 // // Write 1 to clear EVTOAONFLAGS.SWEV0. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0 0x00000001 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_BITN 0 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_M 0x00000001 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_S 0 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_BITN 0 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_M 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_S 0 //***************************************************************************** // @@ -1378,146 +1378,146 @@ // // This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_PULSE // occurs on EVSTAT3.AUX_TIMER2_PULSE. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE 0x00008000 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE_BITN 15 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE_M 0x00008000 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE_S 15 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE 0x00008000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE_BITN 15 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE_M 0x00008000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE_S 15 // Field: [14] AUX_TIMER2_EV3 // // This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV3 // occurs on EVSTAT3.AUX_TIMER2_EV3. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3 0x00004000 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3_BITN 14 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3_M 0x00004000 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3_S 14 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3 0x00004000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3_BITN 14 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3_M 0x00004000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3_S 14 // Field: [13] AUX_TIMER2_EV2 // // This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV2 // occurs on EVSTAT3.AUX_TIMER2_EV2. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2 0x00002000 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2_BITN 13 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2_M 0x00002000 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2_S 13 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2 0x00002000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2_BITN 13 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2_M 0x00002000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2_S 13 // Field: [12] AUX_TIMER2_EV1 // // This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV1 // occurs on EVSTAT3.AUX_TIMER2_EV1. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1 0x00001000 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1_BITN 12 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1_M 0x00001000 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1_S 12 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1 0x00001000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1_BITN 12 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1_M 0x00001000 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1_S 12 // Field: [11] AUX_TIMER2_EV0 // // This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV0 // occurs on EVSTAT3.AUX_TIMER2_EV0. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0 0x00000800 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0_BITN 11 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0_M 0x00000800 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0_S 11 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0 0x00000800 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0_BITN 11 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0_M 0x00000800 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0_S 11 // Field: [10] AUX_ADC_IRQ // // This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_IRQ occurs // on EVSTAT3.AUX_ADC_IRQ. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ 0x00000400 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ_BITN 10 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ_S 10 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ_S 10 // Field: [9] MCU_OBSMUX0 // // This event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs // on EVSTAT2.MCU_OBSMUX0. -#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0 0x00000200 -#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0_BITN 9 -#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0_S 9 +#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0_S 9 // Field: [8] AUX_ADC_FIFO_ALMOST_FULL // // This event flag is set when level selected by // EVTOMCUPOL.AUX_ADC_FIFO_ALMOST_FULL occurs on // EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL_S 8 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL_S 8 // Field: [7] AUX_ADC_DONE // // This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_DONE occurs // on EVSTAT3.AUX_ADC_DONE. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE 0x00000080 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE_BITN 7 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE_S 7 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE_S 7 // Field: [6] AUX_SMPH_AUTOTAKE_DONE // // This event flag is set when level selected by // EVTOMCUPOL.AUX_SMPH_AUTOTAKE_DONE occurs on EVSTAT3.AUX_SMPH_AUTOTAKE_DONE. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE_S 6 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE_S 6 // Field: [5] AUX_TIMER1_EV // // This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER1_EV // occurs on EVSTAT3.AUX_TIMER1_EV. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV 0x00000020 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV_BITN 5 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV_S 5 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV_S 5 // Field: [4] AUX_TIMER0_EV // // This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER0_EV // occurs on EVSTAT3.AUX_TIMER0_EV. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV 0x00000010 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV_BITN 4 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV_S 4 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV_S 4 // Field: [3] AUX_TDC_DONE // // This event flag is set when level selected by EVTOMCUPOL.AUX_TDC_DONE occurs // on EVSTAT3.AUX_TDC_DONE. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE 0x00000008 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE_BITN 3 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE_S 3 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE_S 3 // Field: [2] AUX_COMPB // // This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on // EVSTAT2.AUX_COMPB. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB 0x00000004 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_BITN 2 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_S 2 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_S 2 // Field: [1] AUX_COMPA // // This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on // EVSTAT2.AUX_COMPA. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA 0x00000002 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_BITN 1 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_S 1 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_S 1 // Field: [0] AUX_WU_EV // // This event flag is set when level selected by EVTOMCUPOL.AUX_WU_EV occurs on // reduction-OR of the AUX_SYSIF:WUFLAGS register. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV 0x00000001 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV_BITN 0 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV_M 0x00000001 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV_S 0 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV_S 0 //***************************************************************************** // @@ -1530,12 +1530,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE 0x00008000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_BITN 15 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_M 0x00008000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_S 15 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_LOW 0x00008000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE 0x00008000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_BITN 15 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_M 0x00008000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_S 15 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_LOW 0x00008000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_HIGH 0x00000000 // Field: [14] AUX_TIMER2_EV3 // @@ -1543,12 +1543,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3 0x00004000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_BITN 14 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_M 0x00004000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_S 14 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_LOW 0x00004000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3 0x00004000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_BITN 14 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_M 0x00004000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_S 14 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_LOW 0x00004000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_HIGH 0x00000000 // Field: [13] AUX_TIMER2_EV2 // @@ -1556,12 +1556,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2 0x00002000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_BITN 13 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_M 0x00002000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_S 13 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_LOW 0x00002000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2 0x00002000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_BITN 13 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_M 0x00002000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_S 13 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_LOW 0x00002000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_HIGH 0x00000000 // Field: [12] AUX_TIMER2_EV1 // @@ -1569,12 +1569,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1 0x00001000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_BITN 12 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_M 0x00001000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_S 12 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_LOW 0x00001000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1 0x00001000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_BITN 12 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_M 0x00001000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_S 12 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_LOW 0x00001000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_HIGH 0x00000000 // Field: [11] AUX_TIMER2_EV0 // @@ -1582,12 +1582,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0 0x00000800 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_BITN 11 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_M 0x00000800 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_S 11 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_LOW 0x00000800 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0 0x00000800 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_BITN 11 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_M 0x00000800 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_S 11 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_LOW 0x00000800 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_HIGH 0x00000000 // Field: [10] AUX_ADC_IRQ // @@ -1595,12 +1595,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ 0x00000400 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_BITN 10 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_S 10 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_LOW 0x00000400 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_S 10 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_LOW 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_HIGH 0x00000000 // Field: [9] MCU_OBSMUX0 // @@ -1608,12 +1608,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0 0x00000200 -#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_BITN 9 -#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_S 9 -#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_LOW 0x00000200 -#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_S 9 +#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_LOW 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_HIGH 0x00000000 // Field: [8] AUX_ADC_FIFO_ALMOST_FULL // @@ -1622,12 +1622,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_S 8 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_LOW 0x00000100 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_S 8 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_LOW 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_HIGH 0x00000000 // Field: [7] AUX_ADC_DONE // @@ -1635,12 +1635,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE 0x00000080 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_BITN 7 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_S 7 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_LOW 0x00000080 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_S 7 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_LOW 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_HIGH 0x00000000 // Field: [6] AUX_SMPH_AUTOTAKE_DONE // @@ -1648,12 +1648,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_S 6 -#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_LOW 0x00000040 -#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_S 6 +#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_LOW 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_HIGH 0x00000000 // Field: [5] AUX_TIMER1_EV // @@ -1661,12 +1661,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV 0x00000020 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_BITN 5 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_S 5 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_LOW 0x00000020 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_S 5 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_LOW 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_HIGH 0x00000000 // Field: [4] AUX_TIMER0_EV // @@ -1674,12 +1674,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV 0x00000010 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_BITN 4 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_S 4 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_LOW 0x00000010 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_S 4 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_LOW 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_HIGH 0x00000000 // Field: [3] AUX_TDC_DONE // @@ -1687,12 +1687,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE 0x00000008 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_BITN 3 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_S 3 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_LOW 0x00000008 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_S 3 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_LOW 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_HIGH 0x00000000 // Field: [2] AUX_COMPB // @@ -1700,12 +1700,12 @@ // ENUMs: // FALL Falling edge // RISE Rising edge -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB 0x00000004 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_BITN 2 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_S 2 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_FALL 0x00000004 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_RISE 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_S 2 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_FALL 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_RISE 0x00000000 // Field: [1] AUX_COMPA // @@ -1713,12 +1713,12 @@ // ENUMs: // FALL Falling edge // RISE Rising edge -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA 0x00000002 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_BITN 1 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_S 1 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_FALL 0x00000002 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_RISE 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_S 1 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_FALL 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_RISE 0x00000000 // Field: [0] AUX_WU_EV // @@ -1726,12 +1726,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV 0x00000001 -#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_BITN 0 -#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_M 0x00000001 -#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_S 0 -#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_LOW 0x00000001 -#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_S 0 +#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_LOW 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_HIGH 0x00000000 //***************************************************************************** // @@ -1743,160 +1743,160 @@ // Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_PULSE. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE 0x00008000 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE_BITN 15 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE_M 0x00008000 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE_S 15 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE 0x00008000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE_BITN 15 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE_M 0x00008000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE_S 15 // Field: [14] AUX_TIMER2_EV3 // // Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV3. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3 0x00004000 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3_BITN 14 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3_M 0x00004000 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3_S 14 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3 0x00004000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3_BITN 14 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3_M 0x00004000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3_S 14 // Field: [13] AUX_TIMER2_EV2 // // Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV2. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2 0x00002000 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2_BITN 13 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2_M 0x00002000 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2_S 13 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2 0x00002000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2_BITN 13 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2_M 0x00002000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2_S 13 // Field: [12] AUX_TIMER2_EV1 // // Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV1. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1 0x00001000 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1_BITN 12 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1_M 0x00001000 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1_S 12 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1 0x00001000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1_BITN 12 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1_M 0x00001000 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1_S 12 // Field: [11] AUX_TIMER2_EV0 // // Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV0. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0 0x00000800 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0_BITN 11 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0_M 0x00000800 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0_S 11 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0 0x00000800 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0_BITN 11 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0_M 0x00000800 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0_S 11 // Field: [10] AUX_ADC_IRQ // // Write 1 to clear EVTOMCUFLAGS.AUX_ADC_IRQ. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ 0x00000400 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ_BITN 10 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ_S 10 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ_S 10 // Field: [9] MCU_OBSMUX0 // // Write 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0 0x00000200 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0_BITN 9 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0_S 9 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0_S 9 // Field: [8] AUX_ADC_FIFO_ALMOST_FULL // // Write 1 to clear EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL_S 8 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL_S 8 // Field: [7] AUX_ADC_DONE // // Write 1 to clear EVTOMCUFLAGS.AUX_ADC_DONE. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE 0x00000080 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE_BITN 7 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE_S 7 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE_S 7 // Field: [6] AUX_SMPH_AUTOTAKE_DONE // // Write 1 to clear EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE_S 6 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE_S 6 // Field: [5] AUX_TIMER1_EV // // Write 1 to clear EVTOMCUFLAGS.AUX_TIMER1_EV. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV 0x00000020 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV_BITN 5 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV_S 5 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV_S 5 // Field: [4] AUX_TIMER0_EV // // Write 1 to clear EVTOMCUFLAGS.AUX_TIMER0_EV. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV 0x00000010 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV_BITN 4 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV_S 4 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV_S 4 // Field: [3] AUX_TDC_DONE // // Write 1 to clear EVTOMCUFLAGS.AUX_TDC_DONE. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE 0x00000008 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE_BITN 3 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE_S 3 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE_S 3 // Field: [2] AUX_COMPB // // Write 1 to clear EVTOMCUFLAGS.AUX_COMPB. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB 0x00000004 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_BITN 2 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_S 2 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_S 2 // Field: [1] AUX_COMPA // // Write 1 to clear EVTOMCUFLAGS.AUX_COMPA. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA 0x00000002 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_BITN 1 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_S 1 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_S 1 // Field: [0] AUX_WU_EV // // Write 1 to clear EVTOMCUFLAGS.AUX_WU_EV. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV 0x00000001 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV_BITN 0 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV_M 0x00000001 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV_S 0 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV_S 0 //***************************************************************************** // @@ -1909,10 +1909,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE 0x00008000 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE_BITN 15 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE_M 0x00008000 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE_S 15 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE 0x00008000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE_BITN 15 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE_M 0x00008000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE_S 15 // Field: [14] AUX_TIMER2_EV3 // @@ -1920,10 +1920,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3 0x00004000 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3_BITN 14 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3_M 0x00004000 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3_S 14 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3 0x00004000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3_BITN 14 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3_M 0x00004000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3_S 14 // Field: [13] AUX_TIMER2_EV2 // @@ -1931,10 +1931,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2 0x00002000 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2_BITN 13 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2_M 0x00002000 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2_S 13 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2 0x00002000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2_BITN 13 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2_M 0x00002000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2_S 13 // Field: [12] AUX_TIMER2_EV1 // @@ -1942,10 +1942,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1 0x00001000 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1_BITN 12 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1_M 0x00001000 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1_S 12 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1 0x00001000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1_BITN 12 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1_M 0x00001000 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1_S 12 // Field: [11] AUX_TIMER2_EV0 // @@ -1953,10 +1953,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0 0x00000800 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0_BITN 11 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0_M 0x00000800 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0_S 11 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0 0x00000800 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0_BITN 11 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0_M 0x00000800 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0_S 11 // Field: [10] AUX_ADC_IRQ // @@ -1964,10 +1964,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ 0x00000400 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ_BITN 10 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ_S 10 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ 0x00000400 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ_BITN 10 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ_S 10 // Field: [9] MCU_OBSMUX0 // @@ -1975,10 +1975,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0 0x00000200 -#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0_BITN 9 -#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0_S 9 +#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0 0x00000200 +#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0_BITN 9 +#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0_S 9 // Field: [8] AUX_ADC_FIFO_ALMOST_FULL // @@ -1986,10 +1986,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL_S 8 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL_S 8 // Field: [7] AUX_ADC_DONE // @@ -1997,10 +1997,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE 0x00000080 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE_BITN 7 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE_S 7 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE 0x00000080 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE_BITN 7 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE_S 7 // Field: [6] AUX_SMPH_AUTOTAKE_DONE // @@ -2008,10 +2008,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE_S 6 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE_S 6 // Field: [5] AUX_TIMER1_EV // @@ -2019,10 +2019,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV 0x00000020 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV_BITN 5 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV_S 5 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV 0x00000020 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV_BITN 5 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV_S 5 // Field: [4] AUX_TIMER0_EV // @@ -2030,10 +2030,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV 0x00000010 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV_BITN 4 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV_S 4 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV 0x00000010 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV_BITN 4 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV_S 4 // Field: [3] AUX_TDC_DONE // @@ -2041,10 +2041,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE 0x00000008 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE_BITN 3 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE_S 3 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE 0x00000008 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE_BITN 3 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE_S 3 // Field: [2] AUX_COMPB // @@ -2052,10 +2052,10 @@ // // 0: Exclude // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB 0x00000004 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_BITN 2 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_S 2 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB 0x00000004 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_BITN 2 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_S 2 // Field: [1] AUX_COMPA // @@ -2063,10 +2063,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA 0x00000002 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_BITN 1 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_S 1 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA 0x00000002 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_BITN 1 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_S 1 // Field: [0] AUX_WU_EV // @@ -2074,10 +2074,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV 0x00000001 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV_BITN 0 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV_M 0x00000001 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV_S 0 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV 0x00000001 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV_BITN 0 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV_M 0x00000001 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV_S 0 //***************************************************************************** // @@ -2153,73 +2153,73 @@ // AUXIO2 EVSTAT0.AUXIO2 // AUXIO1 EVSTAT0.AUXIO1 // AUXIO0 EVSTAT0.AUXIO0 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_W 6 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_M 0x0000003F -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_S 0 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_CLKSW_RDY 0x0000003F -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_DAC_HOLD_ACTIVE 0x0000003E -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_SMPH_AUTOTAKE_DONE 0x0000003D -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_IRQ 0x0000003A -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_DONE 0x00000039 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ISRC_RESET_N 0x00000038 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TDC_DONE 0x00000037 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER0_EV 0x00000036 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER1_EV 0x00000035 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_PULSE 0x00000034 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV3 0x00000033 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV2 0x00000032 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV1 0x00000031 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV0 0x00000030 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_COMPB 0x0000002F -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_COMPA 0x0000002E -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_OBSMUX1 0x0000002D -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_OBSMUX0 0x0000002C -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_EV 0x0000002B -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_ACLK_REF 0x0000002A -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_VDDR_RECHARGE 0x00000029 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_ACTIVE 0x00000028 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_PWR_DWN 0x00000027 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_SCLK_LF 0x00000026 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_BATMON_TEMP_UPD 0x00000025 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_BATMON_BAT_UPD 0x00000024 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_RTC_4KHZ 0x00000023 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_RTC_CH2_DLY 0x00000022 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_RTC_CH2 0x00000021 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MANUAL_EV 0x00000020 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO31 0x0000001F -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO30 0x0000001E -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO29 0x0000001D -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO28 0x0000001C -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO27 0x0000001B -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO26 0x0000001A -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO25 0x00000019 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO24 0x00000018 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO23 0x00000017 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO22 0x00000016 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO21 0x00000015 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO20 0x00000014 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO19 0x00000013 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO18 0x00000012 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO17 0x00000011 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO16 0x00000010 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO15 0x0000000F -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO14 0x0000000E -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO13 0x0000000D -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO12 0x0000000C -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO11 0x0000000B -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO10 0x0000000A -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO9 0x00000009 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO8 0x00000008 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO7 0x00000007 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO6 0x00000006 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO5 0x00000005 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO4 0x00000004 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO3 0x00000003 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO2 0x00000002 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO1 0x00000001 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO0 0x00000000 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_W 6 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_M 0x0000003F +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_S 0 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_CLKSW_RDY 0x0000003F +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_DAC_HOLD_ACTIVE 0x0000003E +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_IRQ 0x0000003A +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_DONE 0x00000039 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ISRC_RESET_N 0x00000038 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TDC_DONE 0x00000037 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER0_EV 0x00000036 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER1_EV 0x00000035 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_PULSE 0x00000034 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV3 0x00000033 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV2 0x00000032 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV1 0x00000031 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV0 0x00000030 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_COMPB 0x0000002F +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_COMPA 0x0000002E +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_OBSMUX1 0x0000002D +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_OBSMUX0 0x0000002C +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_EV 0x0000002B +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_ACLK_REF 0x0000002A +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_VDDR_RECHARGE 0x00000029 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_ACTIVE 0x00000028 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_PWR_DWN 0x00000027 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_SCLK_LF 0x00000026 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_RTC_4KHZ 0x00000023 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_RTC_CH2_DLY 0x00000022 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_RTC_CH2 0x00000021 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MANUAL_EV 0x00000020 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO31 0x0000001F +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO30 0x0000001E +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO29 0x0000001D +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO28 0x0000001C +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO27 0x0000001B +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO26 0x0000001A +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO25 0x00000019 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO24 0x00000018 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO23 0x00000017 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO22 0x00000016 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO21 0x00000015 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO20 0x00000014 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO19 0x00000013 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO18 0x00000012 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO17 0x00000011 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO16 0x00000010 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO15 0x0000000F +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO14 0x0000000E +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO13 0x0000000D +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO12 0x0000000C +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO11 0x0000000B +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO10 0x0000000A +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO9 0x00000009 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO8 0x00000008 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO7 0x00000007 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO6 0x00000006 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO5 0x00000005 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO4 0x00000004 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO3 0x00000003 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO2 0x00000002 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO1 0x00000001 +#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO0 0x00000000 //***************************************************************************** // @@ -2238,9 +2238,9 @@ // Decrementation of VALUE halts when either is true: // - AUX_SCE:CTL.DBG_FREEZE_EN is set and system CPU is halted in debug mode. // - AUX_SYSIF:TIMERHALT.PROGDLY is set. -#define AUX_EVCTL_PROGDLY_VALUE_W 16 -#define AUX_EVCTL_PROGDLY_VALUE_M 0x0000FFFF -#define AUX_EVCTL_PROGDLY_VALUE_S 0 +#define AUX_EVCTL_PROGDLY_VALUE_W 16 +#define AUX_EVCTL_PROGDLY_VALUE_M 0x0000FFFF +#define AUX_EVCTL_PROGDLY_VALUE_S 0 //***************************************************************************** // @@ -2250,10 +2250,10 @@ // Field: [0] EV // // This bit field sets the value of EVSTAT2.MANUAL_EV. -#define AUX_EVCTL_MANUAL_EV 0x00000001 -#define AUX_EVCTL_MANUAL_EV_BITN 0 -#define AUX_EVCTL_MANUAL_EV_M 0x00000001 -#define AUX_EVCTL_MANUAL_EV_S 0 +#define AUX_EVCTL_MANUAL_EV 0x00000001 +#define AUX_EVCTL_MANUAL_EV_BITN 0 +#define AUX_EVCTL_MANUAL_EV_M 0x00000001 +#define AUX_EVCTL_MANUAL_EV_S 0 //***************************************************************************** // @@ -2263,9 +2263,9 @@ // Field: [7:0] ALIAS_EV // // Alias of EVSTAT0 event 7 down to 0. -#define AUX_EVCTL_EVSTAT0L_ALIAS_EV_W 8 -#define AUX_EVCTL_EVSTAT0L_ALIAS_EV_M 0x000000FF -#define AUX_EVCTL_EVSTAT0L_ALIAS_EV_S 0 +#define AUX_EVCTL_EVSTAT0L_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT0L_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT0L_ALIAS_EV_S 0 //***************************************************************************** // @@ -2275,9 +2275,9 @@ // Field: [7:0] ALIAS_EV // // Alias of EVSTAT0 event 15 down to 8. -#define AUX_EVCTL_EVSTAT0H_ALIAS_EV_W 8 -#define AUX_EVCTL_EVSTAT0H_ALIAS_EV_M 0x000000FF -#define AUX_EVCTL_EVSTAT0H_ALIAS_EV_S 0 +#define AUX_EVCTL_EVSTAT0H_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT0H_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT0H_ALIAS_EV_S 0 //***************************************************************************** // @@ -2287,9 +2287,9 @@ // Field: [7:0] ALIAS_EV // // Alias of EVSTAT1 event 7 down to 0. -#define AUX_EVCTL_EVSTAT1L_ALIAS_EV_W 8 -#define AUX_EVCTL_EVSTAT1L_ALIAS_EV_M 0x000000FF -#define AUX_EVCTL_EVSTAT1L_ALIAS_EV_S 0 +#define AUX_EVCTL_EVSTAT1L_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT1L_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT1L_ALIAS_EV_S 0 //***************************************************************************** // @@ -2299,9 +2299,9 @@ // Field: [7:0] ALIAS_EV // // Alias of EVSTAT1 event 15 down to 8. -#define AUX_EVCTL_EVSTAT1H_ALIAS_EV_W 8 -#define AUX_EVCTL_EVSTAT1H_ALIAS_EV_M 0x000000FF -#define AUX_EVCTL_EVSTAT1H_ALIAS_EV_S 0 +#define AUX_EVCTL_EVSTAT1H_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT1H_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT1H_ALIAS_EV_S 0 //***************************************************************************** // @@ -2311,9 +2311,9 @@ // Field: [7:0] ALIAS_EV // // Alias of EVSTAT2 event 7 down to 0. -#define AUX_EVCTL_EVSTAT2L_ALIAS_EV_W 8 -#define AUX_EVCTL_EVSTAT2L_ALIAS_EV_M 0x000000FF -#define AUX_EVCTL_EVSTAT2L_ALIAS_EV_S 0 +#define AUX_EVCTL_EVSTAT2L_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT2L_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT2L_ALIAS_EV_S 0 //***************************************************************************** // @@ -2323,9 +2323,9 @@ // Field: [7:0] ALIAS_EV // // Alias of EVSTAT2 event 15 down to 8. -#define AUX_EVCTL_EVSTAT2H_ALIAS_EV_W 8 -#define AUX_EVCTL_EVSTAT2H_ALIAS_EV_M 0x000000FF -#define AUX_EVCTL_EVSTAT2H_ALIAS_EV_S 0 +#define AUX_EVCTL_EVSTAT2H_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT2H_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT2H_ALIAS_EV_S 0 //***************************************************************************** // @@ -2335,9 +2335,9 @@ // Field: [7:0] ALIAS_EV // // Alias of EVSTAT3 event 7 down to 0. -#define AUX_EVCTL_EVSTAT3L_ALIAS_EV_W 8 -#define AUX_EVCTL_EVSTAT3L_ALIAS_EV_M 0x000000FF -#define AUX_EVCTL_EVSTAT3L_ALIAS_EV_S 0 +#define AUX_EVCTL_EVSTAT3L_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT3L_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT3L_ALIAS_EV_S 0 //***************************************************************************** // @@ -2347,9 +2347,8 @@ // Field: [7:0] ALIAS_EV // // Alias of EVSTAT3 event 15 down to 8. -#define AUX_EVCTL_EVSTAT3H_ALIAS_EV_W 8 -#define AUX_EVCTL_EVSTAT3H_ALIAS_EV_M 0x000000FF -#define AUX_EVCTL_EVSTAT3H_ALIAS_EV_S 0 - +#define AUX_EVCTL_EVSTAT3H_ALIAS_EV_W 8 +#define AUX_EVCTL_EVSTAT3H_ALIAS_EV_M 0x000000FF +#define AUX_EVCTL_EVSTAT3H_ALIAS_EV_S 0 #endif // __AUX_EVCTL__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_mac.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_mac.h index fb426ef..7a6fac3 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_mac.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_mac.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_mac_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_mac_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_MAC_H__ #define __HW_AUX_MAC_H__ @@ -44,124 +44,124 @@ // //***************************************************************************** // Signed Operand 0 -#define AUX_MAC_O_OP0S 0x00000000 +#define AUX_MAC_O_OP0S 0x00000000 // Unsigned Operand 0 -#define AUX_MAC_O_OP0U 0x00000004 +#define AUX_MAC_O_OP0U 0x00000004 // Signed Operand 1 and Multiply -#define AUX_MAC_O_OP1SMUL 0x00000008 +#define AUX_MAC_O_OP1SMUL 0x00000008 // Unsigned Operand 1 and Multiply -#define AUX_MAC_O_OP1UMUL 0x0000000C +#define AUX_MAC_O_OP1UMUL 0x0000000C // Signed Operand 1 and Multiply-Accumulate -#define AUX_MAC_O_OP1SMAC 0x00000010 +#define AUX_MAC_O_OP1SMAC 0x00000010 // Unsigned Operand 1 and Multiply-Accumulate -#define AUX_MAC_O_OP1UMAC 0x00000014 +#define AUX_MAC_O_OP1UMAC 0x00000014 // Signed Operand 1 and 16-bit Addition -#define AUX_MAC_O_OP1SADD16 0x00000018 +#define AUX_MAC_O_OP1SADD16 0x00000018 // Unsigned Operand 1 and 16-bit Addition -#define AUX_MAC_O_OP1UADD16 0x0000001C +#define AUX_MAC_O_OP1UADD16 0x0000001C // Signed Operand 1 and 32-bit Addition -#define AUX_MAC_O_OP1SADD32 0x00000020 +#define AUX_MAC_O_OP1SADD32 0x00000020 // Unsigned Operand 1 and 32-bit Addition -#define AUX_MAC_O_OP1UADD32 0x00000024 +#define AUX_MAC_O_OP1UADD32 0x00000024 // Count Leading Zero -#define AUX_MAC_O_CLZ 0x00000028 +#define AUX_MAC_O_CLZ 0x00000028 // Count Leading Sign -#define AUX_MAC_O_CLS 0x0000002C +#define AUX_MAC_O_CLS 0x0000002C // Accumulator Shift -#define AUX_MAC_O_ACCSHIFT 0x00000030 +#define AUX_MAC_O_ACCSHIFT 0x00000030 // Accumulator Reset -#define AUX_MAC_O_ACCRESET 0x00000034 +#define AUX_MAC_O_ACCRESET 0x00000034 // Accumulator Bits 15:0 -#define AUX_MAC_O_ACC15_0 0x00000038 +#define AUX_MAC_O_ACC15_0 0x00000038 // Accumulator Bits 16:1 -#define AUX_MAC_O_ACC16_1 0x0000003C +#define AUX_MAC_O_ACC16_1 0x0000003C // Accumulator Bits 17:2 -#define AUX_MAC_O_ACC17_2 0x00000040 +#define AUX_MAC_O_ACC17_2 0x00000040 // Accumulator Bits 18:3 -#define AUX_MAC_O_ACC18_3 0x00000044 +#define AUX_MAC_O_ACC18_3 0x00000044 // Accumulator Bits 19:4 -#define AUX_MAC_O_ACC19_4 0x00000048 +#define AUX_MAC_O_ACC19_4 0x00000048 // Accumulator Bits 20:5 -#define AUX_MAC_O_ACC20_5 0x0000004C +#define AUX_MAC_O_ACC20_5 0x0000004C // Accumulator Bits 21:6 -#define AUX_MAC_O_ACC21_6 0x00000050 +#define AUX_MAC_O_ACC21_6 0x00000050 // Accumulator Bits 22:7 -#define AUX_MAC_O_ACC22_7 0x00000054 +#define AUX_MAC_O_ACC22_7 0x00000054 // Accumulator Bits 23:8 -#define AUX_MAC_O_ACC23_8 0x00000058 +#define AUX_MAC_O_ACC23_8 0x00000058 // Accumulator Bits 24:9 -#define AUX_MAC_O_ACC24_9 0x0000005C +#define AUX_MAC_O_ACC24_9 0x0000005C // Accumulator Bits 25:10 -#define AUX_MAC_O_ACC25_10 0x00000060 +#define AUX_MAC_O_ACC25_10 0x00000060 // Accumulator Bits 26:11 -#define AUX_MAC_O_ACC26_11 0x00000064 +#define AUX_MAC_O_ACC26_11 0x00000064 // Accumulator Bits 27:12 -#define AUX_MAC_O_ACC27_12 0x00000068 +#define AUX_MAC_O_ACC27_12 0x00000068 // Accumulator Bits 28:13 -#define AUX_MAC_O_ACC28_13 0x0000006C +#define AUX_MAC_O_ACC28_13 0x0000006C // Accumulator Bits 29:14 -#define AUX_MAC_O_ACC29_14 0x00000070 +#define AUX_MAC_O_ACC29_14 0x00000070 // Accumulator Bits 30:15 -#define AUX_MAC_O_ACC30_15 0x00000074 +#define AUX_MAC_O_ACC30_15 0x00000074 // Accumulator Bits 31:16 -#define AUX_MAC_O_ACC31_16 0x00000078 +#define AUX_MAC_O_ACC31_16 0x00000078 // Accumulator Bits 32:17 -#define AUX_MAC_O_ACC32_17 0x0000007C +#define AUX_MAC_O_ACC32_17 0x0000007C // Accumulator Bits 33:18 -#define AUX_MAC_O_ACC33_18 0x00000080 +#define AUX_MAC_O_ACC33_18 0x00000080 // Accumulator Bits 34:19 -#define AUX_MAC_O_ACC34_19 0x00000084 +#define AUX_MAC_O_ACC34_19 0x00000084 // Accumulator Bits 35:20 -#define AUX_MAC_O_ACC35_20 0x00000088 +#define AUX_MAC_O_ACC35_20 0x00000088 // Accumulator Bits 36:21 -#define AUX_MAC_O_ACC36_21 0x0000008C +#define AUX_MAC_O_ACC36_21 0x0000008C // Accumulator Bits 37:22 -#define AUX_MAC_O_ACC37_22 0x00000090 +#define AUX_MAC_O_ACC37_22 0x00000090 // Accumulator Bits 38:23 -#define AUX_MAC_O_ACC38_23 0x00000094 +#define AUX_MAC_O_ACC38_23 0x00000094 // Accumulator Bits 39:24 -#define AUX_MAC_O_ACC39_24 0x00000098 +#define AUX_MAC_O_ACC39_24 0x00000098 // Accumulator Bits 39:32 -#define AUX_MAC_O_ACC39_32 0x0000009C +#define AUX_MAC_O_ACC39_32 0x0000009C //***************************************************************************** // @@ -173,9 +173,9 @@ // Signed operand 0. // // Operand for multiply, multiply-and-accumulate, or 32-bit add operations. -#define AUX_MAC_OP0S_OP0_VALUE_W 16 -#define AUX_MAC_OP0S_OP0_VALUE_M 0x0000FFFF -#define AUX_MAC_OP0S_OP0_VALUE_S 0 +#define AUX_MAC_OP0S_OP0_VALUE_W 16 +#define AUX_MAC_OP0S_OP0_VALUE_M 0x0000FFFF +#define AUX_MAC_OP0S_OP0_VALUE_S 0 //***************************************************************************** // @@ -187,9 +187,9 @@ // Unsigned operand 0. // // Operand for multiply, multiply-and-accumulate, or 32-bit add operations. -#define AUX_MAC_OP0U_OP0_VALUE_W 16 -#define AUX_MAC_OP0U_OP0_VALUE_M 0x0000FFFF -#define AUX_MAC_OP0U_OP0_VALUE_S 0 +#define AUX_MAC_OP0U_OP0_VALUE_W 16 +#define AUX_MAC_OP0U_OP0_VALUE_M 0x0000FFFF +#define AUX_MAC_OP0U_OP0_VALUE_S 0 //***************************************************************************** // @@ -206,9 +206,9 @@ // OP0S.OP0_VALUE. // When operand 0 was written to OP0U.OP0_VALUE: ACC = OP1_VALUE * // OP0U.OP0_VALUE. -#define AUX_MAC_OP1SMUL_OP1_VALUE_W 16 -#define AUX_MAC_OP1SMUL_OP1_VALUE_M 0x0000FFFF -#define AUX_MAC_OP1SMUL_OP1_VALUE_S 0 +#define AUX_MAC_OP1SMUL_OP1_VALUE_W 16 +#define AUX_MAC_OP1SMUL_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1SMUL_OP1_VALUE_S 0 //***************************************************************************** // @@ -226,9 +226,9 @@ // OP0S.OP0_VALUE. // When operand 0 was written to OP0U.OP0_VALUE: ACC = OP1_VALUE * // OP0U.OP0_VALUE. -#define AUX_MAC_OP1UMUL_OP1_VALUE_W 16 -#define AUX_MAC_OP1UMUL_OP1_VALUE_M 0x0000FFFF -#define AUX_MAC_OP1UMUL_OP1_VALUE_S 0 +#define AUX_MAC_OP1UMUL_OP1_VALUE_W 16 +#define AUX_MAC_OP1UMUL_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1UMUL_OP1_VALUE_S 0 //***************************************************************************** // @@ -245,9 +245,9 @@ // OP0S.OP0_VALUE ). // When operand 0 was written to OP0U.OP0_VALUE: ACC = ACC + ( OP1_VALUE * // OP0U.OP0_VALUE ). -#define AUX_MAC_OP1SMAC_OP1_VALUE_W 16 -#define AUX_MAC_OP1SMAC_OP1_VALUE_M 0x0000FFFF -#define AUX_MAC_OP1SMAC_OP1_VALUE_S 0 +#define AUX_MAC_OP1SMAC_OP1_VALUE_W 16 +#define AUX_MAC_OP1SMAC_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1SMAC_OP1_VALUE_S 0 //***************************************************************************** // @@ -265,9 +265,9 @@ // OP0S.OP0_VALUE ). // When operand 0 was written to OP0U.OP0_VALUE: ACC = ACC + ( OP1_VALUE * // OP0U.OP0_VALUE ). -#define AUX_MAC_OP1UMAC_OP1_VALUE_W 16 -#define AUX_MAC_OP1UMAC_OP1_VALUE_M 0x0000FFFF -#define AUX_MAC_OP1UMAC_OP1_VALUE_S 0 +#define AUX_MAC_OP1UMAC_OP1_VALUE_W 16 +#define AUX_MAC_OP1UMAC_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1UMAC_OP1_VALUE_S 0 //***************************************************************************** // @@ -281,9 +281,9 @@ // Write OP1_VALUE to set signed operand 1 and trigger the following operation: // // ACC = ACC + OP1_VALUE. -#define AUX_MAC_OP1SADD16_OP1_VALUE_W 16 -#define AUX_MAC_OP1SADD16_OP1_VALUE_M 0x0000FFFF -#define AUX_MAC_OP1SADD16_OP1_VALUE_S 0 +#define AUX_MAC_OP1SADD16_OP1_VALUE_W 16 +#define AUX_MAC_OP1SADD16_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1SADD16_OP1_VALUE_S 0 //***************************************************************************** // @@ -298,9 +298,9 @@ // operation: // // ACC = ACC + OP1_VALUE. -#define AUX_MAC_OP1UADD16_OP1_VALUE_W 16 -#define AUX_MAC_OP1UADD16_OP1_VALUE_M 0x0000FFFF -#define AUX_MAC_OP1UADD16_OP1_VALUE_S 0 +#define AUX_MAC_OP1UADD16_OP1_VALUE_W 16 +#define AUX_MAC_OP1UADD16_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1UADD16_OP1_VALUE_S 0 //***************************************************************************** // @@ -318,9 +318,9 @@ // (( OP1_VALUE << 16) | OP0S.OP0_VALUE ). // When lower half of 32-bit operand was written to OP0U.OP0_VALUE: ACC = ACC + // (( OP1_VALUE << 16) | OP0U.OP0_VALUE ). -#define AUX_MAC_OP1SADD32_OP1_VALUE_W 16 -#define AUX_MAC_OP1SADD32_OP1_VALUE_M 0x0000FFFF -#define AUX_MAC_OP1SADD32_OP1_VALUE_S 0 +#define AUX_MAC_OP1SADD32_OP1_VALUE_W 16 +#define AUX_MAC_OP1SADD32_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1SADD32_OP1_VALUE_S 0 //***************************************************************************** // @@ -338,9 +338,9 @@ // (( OP1_VALUE << 16) | OP0S.OP0_VALUE ). // When lower half of 32-bit operand was written to OP0U.OP0_VALUE: ACC = ACC + // (( OP1_VALUE << 16) | OP0U.OP0_VALUE ). -#define AUX_MAC_OP1UADD32_OP1_VALUE_W 16 -#define AUX_MAC_OP1UADD32_OP1_VALUE_M 0x0000FFFF -#define AUX_MAC_OP1UADD32_OP1_VALUE_S 0 +#define AUX_MAC_OP1UADD32_OP1_VALUE_W 16 +#define AUX_MAC_OP1UADD32_OP1_VALUE_M 0x0000FFFF +#define AUX_MAC_OP1UADD32_OP1_VALUE_S 0 //***************************************************************************** // @@ -355,9 +355,9 @@ // 0x01: 1 leading zero. // ... // 0x28: 40 leading zeros (accumulator value is 0). -#define AUX_MAC_CLZ_VALUE_W 6 -#define AUX_MAC_CLZ_VALUE_M 0x0000003F -#define AUX_MAC_CLZ_VALUE_S 0 +#define AUX_MAC_CLZ_VALUE_W 6 +#define AUX_MAC_CLZ_VALUE_M 0x0000003F +#define AUX_MAC_CLZ_VALUE_S 0 //***************************************************************************** // @@ -373,9 +373,9 @@ // When MSB of accumulator is 1, VALUE is number of leading ones, MSB included. // // VALUE range is 1 thru 40. -#define AUX_MAC_CLS_VALUE_W 6 -#define AUX_MAC_CLS_VALUE_M 0x0000003F -#define AUX_MAC_CLS_VALUE_S 0 +#define AUX_MAC_CLS_VALUE_W 6 +#define AUX_MAC_CLS_VALUE_M 0x0000003F +#define AUX_MAC_CLS_VALUE_S 0 //***************************************************************************** // @@ -387,20 +387,20 @@ // Logic shift left by 1 bit. // // Write 1 to shift the accumulator one bit to the left, 0 inserted at bit 0. -#define AUX_MAC_ACCSHIFT_LSL1 0x00000004 -#define AUX_MAC_ACCSHIFT_LSL1_BITN 2 -#define AUX_MAC_ACCSHIFT_LSL1_M 0x00000004 -#define AUX_MAC_ACCSHIFT_LSL1_S 2 +#define AUX_MAC_ACCSHIFT_LSL1 0x00000004 +#define AUX_MAC_ACCSHIFT_LSL1_BITN 2 +#define AUX_MAC_ACCSHIFT_LSL1_M 0x00000004 +#define AUX_MAC_ACCSHIFT_LSL1_S 2 // Field: [1] LSR1 // // Logic shift right by 1 bit. // // Write 1 to shift the accumulator one bit to the right, 0 inserted at bit 39. -#define AUX_MAC_ACCSHIFT_LSR1 0x00000002 -#define AUX_MAC_ACCSHIFT_LSR1_BITN 1 -#define AUX_MAC_ACCSHIFT_LSR1_M 0x00000002 -#define AUX_MAC_ACCSHIFT_LSR1_S 1 +#define AUX_MAC_ACCSHIFT_LSR1 0x00000002 +#define AUX_MAC_ACCSHIFT_LSR1_BITN 1 +#define AUX_MAC_ACCSHIFT_LSR1_M 0x00000002 +#define AUX_MAC_ACCSHIFT_LSR1_S 1 // Field: [0] ASR1 // @@ -408,10 +408,10 @@ // // Write 1 to shift the accumulator one bit to the right, previous sign bit // inserted at bit 39. -#define AUX_MAC_ACCSHIFT_ASR1 0x00000001 -#define AUX_MAC_ACCSHIFT_ASR1_BITN 0 -#define AUX_MAC_ACCSHIFT_ASR1_M 0x00000001 -#define AUX_MAC_ACCSHIFT_ASR1_S 0 +#define AUX_MAC_ACCSHIFT_ASR1 0x00000001 +#define AUX_MAC_ACCSHIFT_ASR1_BITN 0 +#define AUX_MAC_ACCSHIFT_ASR1_M 0x00000001 +#define AUX_MAC_ACCSHIFT_ASR1_S 0 //***************************************************************************** // @@ -422,9 +422,9 @@ // // Write any value to this register to trigger a reset of all bits in the // accumulator. -#define AUX_MAC_ACCRESET_TRG_W 16 -#define AUX_MAC_ACCRESET_TRG_M 0x0000FFFF -#define AUX_MAC_ACCRESET_TRG_S 0 +#define AUX_MAC_ACCRESET_TRG_W 16 +#define AUX_MAC_ACCRESET_TRG_M 0x0000FFFF +#define AUX_MAC_ACCRESET_TRG_S 0 //***************************************************************************** // @@ -436,9 +436,9 @@ // Value of the accumulator, bits 15:0. // // Write VALUE to initialize bits 15:0 of accumulator. -#define AUX_MAC_ACC15_0_VALUE_W 16 -#define AUX_MAC_ACC15_0_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC15_0_VALUE_S 0 +#define AUX_MAC_ACC15_0_VALUE_W 16 +#define AUX_MAC_ACC15_0_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC15_0_VALUE_S 0 //***************************************************************************** // @@ -448,9 +448,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 16:1. -#define AUX_MAC_ACC16_1_VALUE_W 16 -#define AUX_MAC_ACC16_1_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC16_1_VALUE_S 0 +#define AUX_MAC_ACC16_1_VALUE_W 16 +#define AUX_MAC_ACC16_1_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC16_1_VALUE_S 0 //***************************************************************************** // @@ -460,9 +460,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 17:2. -#define AUX_MAC_ACC17_2_VALUE_W 16 -#define AUX_MAC_ACC17_2_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC17_2_VALUE_S 0 +#define AUX_MAC_ACC17_2_VALUE_W 16 +#define AUX_MAC_ACC17_2_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC17_2_VALUE_S 0 //***************************************************************************** // @@ -472,9 +472,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 18:3. -#define AUX_MAC_ACC18_3_VALUE_W 16 -#define AUX_MAC_ACC18_3_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC18_3_VALUE_S 0 +#define AUX_MAC_ACC18_3_VALUE_W 16 +#define AUX_MAC_ACC18_3_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC18_3_VALUE_S 0 //***************************************************************************** // @@ -484,9 +484,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 19:4. -#define AUX_MAC_ACC19_4_VALUE_W 16 -#define AUX_MAC_ACC19_4_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC19_4_VALUE_S 0 +#define AUX_MAC_ACC19_4_VALUE_W 16 +#define AUX_MAC_ACC19_4_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC19_4_VALUE_S 0 //***************************************************************************** // @@ -496,9 +496,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 20:5. -#define AUX_MAC_ACC20_5_VALUE_W 16 -#define AUX_MAC_ACC20_5_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC20_5_VALUE_S 0 +#define AUX_MAC_ACC20_5_VALUE_W 16 +#define AUX_MAC_ACC20_5_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC20_5_VALUE_S 0 //***************************************************************************** // @@ -508,9 +508,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 21:6. -#define AUX_MAC_ACC21_6_VALUE_W 16 -#define AUX_MAC_ACC21_6_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC21_6_VALUE_S 0 +#define AUX_MAC_ACC21_6_VALUE_W 16 +#define AUX_MAC_ACC21_6_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC21_6_VALUE_S 0 //***************************************************************************** // @@ -520,9 +520,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 22:7. -#define AUX_MAC_ACC22_7_VALUE_W 16 -#define AUX_MAC_ACC22_7_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC22_7_VALUE_S 0 +#define AUX_MAC_ACC22_7_VALUE_W 16 +#define AUX_MAC_ACC22_7_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC22_7_VALUE_S 0 //***************************************************************************** // @@ -532,9 +532,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 23:8. -#define AUX_MAC_ACC23_8_VALUE_W 16 -#define AUX_MAC_ACC23_8_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC23_8_VALUE_S 0 +#define AUX_MAC_ACC23_8_VALUE_W 16 +#define AUX_MAC_ACC23_8_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC23_8_VALUE_S 0 //***************************************************************************** // @@ -544,9 +544,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 24:9. -#define AUX_MAC_ACC24_9_VALUE_W 16 -#define AUX_MAC_ACC24_9_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC24_9_VALUE_S 0 +#define AUX_MAC_ACC24_9_VALUE_W 16 +#define AUX_MAC_ACC24_9_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC24_9_VALUE_S 0 //***************************************************************************** // @@ -556,9 +556,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 25:10. -#define AUX_MAC_ACC25_10_VALUE_W 16 -#define AUX_MAC_ACC25_10_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC25_10_VALUE_S 0 +#define AUX_MAC_ACC25_10_VALUE_W 16 +#define AUX_MAC_ACC25_10_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC25_10_VALUE_S 0 //***************************************************************************** // @@ -568,9 +568,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 26:11. -#define AUX_MAC_ACC26_11_VALUE_W 16 -#define AUX_MAC_ACC26_11_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC26_11_VALUE_S 0 +#define AUX_MAC_ACC26_11_VALUE_W 16 +#define AUX_MAC_ACC26_11_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC26_11_VALUE_S 0 //***************************************************************************** // @@ -580,9 +580,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 27:12. -#define AUX_MAC_ACC27_12_VALUE_W 16 -#define AUX_MAC_ACC27_12_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC27_12_VALUE_S 0 +#define AUX_MAC_ACC27_12_VALUE_W 16 +#define AUX_MAC_ACC27_12_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC27_12_VALUE_S 0 //***************************************************************************** // @@ -592,9 +592,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 28:13. -#define AUX_MAC_ACC28_13_VALUE_W 16 -#define AUX_MAC_ACC28_13_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC28_13_VALUE_S 0 +#define AUX_MAC_ACC28_13_VALUE_W 16 +#define AUX_MAC_ACC28_13_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC28_13_VALUE_S 0 //***************************************************************************** // @@ -604,9 +604,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 29:14. -#define AUX_MAC_ACC29_14_VALUE_W 16 -#define AUX_MAC_ACC29_14_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC29_14_VALUE_S 0 +#define AUX_MAC_ACC29_14_VALUE_W 16 +#define AUX_MAC_ACC29_14_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC29_14_VALUE_S 0 //***************************************************************************** // @@ -616,9 +616,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 30:15. -#define AUX_MAC_ACC30_15_VALUE_W 16 -#define AUX_MAC_ACC30_15_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC30_15_VALUE_S 0 +#define AUX_MAC_ACC30_15_VALUE_W 16 +#define AUX_MAC_ACC30_15_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC30_15_VALUE_S 0 //***************************************************************************** // @@ -630,9 +630,9 @@ // Value of the accumulator, bits 31:16. // // Write VALUE to initialize bits 31:16 of accumulator. -#define AUX_MAC_ACC31_16_VALUE_W 16 -#define AUX_MAC_ACC31_16_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC31_16_VALUE_S 0 +#define AUX_MAC_ACC31_16_VALUE_W 16 +#define AUX_MAC_ACC31_16_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC31_16_VALUE_S 0 //***************************************************************************** // @@ -642,9 +642,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 32:17. -#define AUX_MAC_ACC32_17_VALUE_W 16 -#define AUX_MAC_ACC32_17_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC32_17_VALUE_S 0 +#define AUX_MAC_ACC32_17_VALUE_W 16 +#define AUX_MAC_ACC32_17_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC32_17_VALUE_S 0 //***************************************************************************** // @@ -654,9 +654,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 33:18. -#define AUX_MAC_ACC33_18_VALUE_W 16 -#define AUX_MAC_ACC33_18_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC33_18_VALUE_S 0 +#define AUX_MAC_ACC33_18_VALUE_W 16 +#define AUX_MAC_ACC33_18_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC33_18_VALUE_S 0 //***************************************************************************** // @@ -666,9 +666,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 34:19. -#define AUX_MAC_ACC34_19_VALUE_W 16 -#define AUX_MAC_ACC34_19_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC34_19_VALUE_S 0 +#define AUX_MAC_ACC34_19_VALUE_W 16 +#define AUX_MAC_ACC34_19_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC34_19_VALUE_S 0 //***************************************************************************** // @@ -678,9 +678,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 35:20. -#define AUX_MAC_ACC35_20_VALUE_W 16 -#define AUX_MAC_ACC35_20_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC35_20_VALUE_S 0 +#define AUX_MAC_ACC35_20_VALUE_W 16 +#define AUX_MAC_ACC35_20_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC35_20_VALUE_S 0 //***************************************************************************** // @@ -690,9 +690,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 36:21. -#define AUX_MAC_ACC36_21_VALUE_W 16 -#define AUX_MAC_ACC36_21_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC36_21_VALUE_S 0 +#define AUX_MAC_ACC36_21_VALUE_W 16 +#define AUX_MAC_ACC36_21_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC36_21_VALUE_S 0 //***************************************************************************** // @@ -702,9 +702,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 37:22. -#define AUX_MAC_ACC37_22_VALUE_W 16 -#define AUX_MAC_ACC37_22_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC37_22_VALUE_S 0 +#define AUX_MAC_ACC37_22_VALUE_W 16 +#define AUX_MAC_ACC37_22_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC37_22_VALUE_S 0 //***************************************************************************** // @@ -714,9 +714,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 38:23. -#define AUX_MAC_ACC38_23_VALUE_W 16 -#define AUX_MAC_ACC38_23_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC38_23_VALUE_S 0 +#define AUX_MAC_ACC38_23_VALUE_W 16 +#define AUX_MAC_ACC38_23_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC38_23_VALUE_S 0 //***************************************************************************** // @@ -726,9 +726,9 @@ // Field: [15:0] VALUE // // Value of the accumulator, bits 39:24. -#define AUX_MAC_ACC39_24_VALUE_W 16 -#define AUX_MAC_ACC39_24_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC39_24_VALUE_S 0 +#define AUX_MAC_ACC39_24_VALUE_W 16 +#define AUX_MAC_ACC39_24_VALUE_M 0x0000FFFF +#define AUX_MAC_ACC39_24_VALUE_S 0 //***************************************************************************** // @@ -740,9 +740,8 @@ // Value of the accumulator, bits 39:32. // // Write VALUE to initialize bits 39:32 of accumulator. -#define AUX_MAC_ACC39_32_VALUE_W 8 -#define AUX_MAC_ACC39_32_VALUE_M 0x000000FF -#define AUX_MAC_ACC39_32_VALUE_S 0 - +#define AUX_MAC_ACC39_32_VALUE_W 8 +#define AUX_MAC_ACC39_32_VALUE_M 0x000000FF +#define AUX_MAC_ACC39_32_VALUE_S 0 #endif // __AUX_MAC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_ram.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_ram.h index 427948a..73a1016 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_ram.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_ram.h @@ -1,48 +1,45 @@ /****************************************************************************** -* Filename: hw_aux_ram_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_ram_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_RAM_H__ #define __HW_AUX_RAM_H__ +#define AUX_RAM_O_BANK0 0x00000000 +#define AUX_RAM_BANK0_BYTE_SIZE 4096 -#define AUX_RAM_O_BANK0 0x00000000 -#define AUX_RAM_BANK0_BYTE_SIZE 4096 - -#define AUX_RAM_TOT_BYTE_SIZE 4096 - - +#define AUX_RAM_TOT_BYTE_SIZE 4096 #endif // __HW_AUX_RAM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sce.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sce.h index 5be902d..056d66a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sce.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sce.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_sce_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_sce_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_SCE_H__ #define __HW_AUX_SCE_H__ @@ -44,34 +44,34 @@ // //***************************************************************************** // Internal -#define AUX_SCE_O_CTL 0x00000000 +#define AUX_SCE_O_CTL 0x00000000 // Internal -#define AUX_SCE_O_FETCHSTAT 0x00000004 +#define AUX_SCE_O_FETCHSTAT 0x00000004 // Internal -#define AUX_SCE_O_CPUSTAT 0x00000008 +#define AUX_SCE_O_CPUSTAT 0x00000008 // Internal -#define AUX_SCE_O_WUSTAT 0x0000000C +#define AUX_SCE_O_WUSTAT 0x0000000C // Internal -#define AUX_SCE_O_REG1_0 0x00000010 +#define AUX_SCE_O_REG1_0 0x00000010 // Internal -#define AUX_SCE_O_REG3_2 0x00000014 +#define AUX_SCE_O_REG3_2 0x00000014 // Internal -#define AUX_SCE_O_REG5_4 0x00000018 +#define AUX_SCE_O_REG5_4 0x00000018 // Internal -#define AUX_SCE_O_REG7_6 0x0000001C +#define AUX_SCE_O_REG7_6 0x0000001C // Internal -#define AUX_SCE_O_LOOPADDR 0x00000020 +#define AUX_SCE_O_LOOPADDR 0x00000020 // Internal -#define AUX_SCE_O_LOOPCNT 0x00000024 +#define AUX_SCE_O_LOOPCNT 0x00000024 //***************************************************************************** // @@ -81,79 +81,79 @@ // Field: [31:24] FORCE_EV_LOW // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_FORCE_EV_LOW_W 8 -#define AUX_SCE_CTL_FORCE_EV_LOW_M 0xFF000000 -#define AUX_SCE_CTL_FORCE_EV_LOW_S 24 +#define AUX_SCE_CTL_FORCE_EV_LOW_W 8 +#define AUX_SCE_CTL_FORCE_EV_LOW_M 0xFF000000 +#define AUX_SCE_CTL_FORCE_EV_LOW_S 24 // Field: [23:16] FORCE_EV_HIGH // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_FORCE_EV_HIGH_W 8 -#define AUX_SCE_CTL_FORCE_EV_HIGH_M 0x00FF0000 -#define AUX_SCE_CTL_FORCE_EV_HIGH_S 16 +#define AUX_SCE_CTL_FORCE_EV_HIGH_W 8 +#define AUX_SCE_CTL_FORCE_EV_HIGH_M 0x00FF0000 +#define AUX_SCE_CTL_FORCE_EV_HIGH_S 16 // Field: [15:8] RESET_VECTOR // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_RESET_VECTOR_W 8 -#define AUX_SCE_CTL_RESET_VECTOR_M 0x0000FF00 -#define AUX_SCE_CTL_RESET_VECTOR_S 8 +#define AUX_SCE_CTL_RESET_VECTOR_W 8 +#define AUX_SCE_CTL_RESET_VECTOR_M 0x0000FF00 +#define AUX_SCE_CTL_RESET_VECTOR_S 8 // Field: [6] DBG_FREEZE_EN // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_DBG_FREEZE_EN 0x00000040 -#define AUX_SCE_CTL_DBG_FREEZE_EN_BITN 6 -#define AUX_SCE_CTL_DBG_FREEZE_EN_M 0x00000040 -#define AUX_SCE_CTL_DBG_FREEZE_EN_S 6 +#define AUX_SCE_CTL_DBG_FREEZE_EN 0x00000040 +#define AUX_SCE_CTL_DBG_FREEZE_EN_BITN 6 +#define AUX_SCE_CTL_DBG_FREEZE_EN_M 0x00000040 +#define AUX_SCE_CTL_DBG_FREEZE_EN_S 6 // Field: [5] FORCE_WU_LOW // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_FORCE_WU_LOW 0x00000020 -#define AUX_SCE_CTL_FORCE_WU_LOW_BITN 5 -#define AUX_SCE_CTL_FORCE_WU_LOW_M 0x00000020 -#define AUX_SCE_CTL_FORCE_WU_LOW_S 5 +#define AUX_SCE_CTL_FORCE_WU_LOW 0x00000020 +#define AUX_SCE_CTL_FORCE_WU_LOW_BITN 5 +#define AUX_SCE_CTL_FORCE_WU_LOW_M 0x00000020 +#define AUX_SCE_CTL_FORCE_WU_LOW_S 5 // Field: [4] FORCE_WU_HIGH // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_FORCE_WU_HIGH 0x00000010 -#define AUX_SCE_CTL_FORCE_WU_HIGH_BITN 4 -#define AUX_SCE_CTL_FORCE_WU_HIGH_M 0x00000010 -#define AUX_SCE_CTL_FORCE_WU_HIGH_S 4 +#define AUX_SCE_CTL_FORCE_WU_HIGH 0x00000010 +#define AUX_SCE_CTL_FORCE_WU_HIGH_BITN 4 +#define AUX_SCE_CTL_FORCE_WU_HIGH_M 0x00000010 +#define AUX_SCE_CTL_FORCE_WU_HIGH_S 4 // Field: [3] RESTART // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_RESTART 0x00000008 -#define AUX_SCE_CTL_RESTART_BITN 3 -#define AUX_SCE_CTL_RESTART_M 0x00000008 -#define AUX_SCE_CTL_RESTART_S 3 +#define AUX_SCE_CTL_RESTART 0x00000008 +#define AUX_SCE_CTL_RESTART_BITN 3 +#define AUX_SCE_CTL_RESTART_M 0x00000008 +#define AUX_SCE_CTL_RESTART_S 3 // Field: [2] SINGLE_STEP // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_SINGLE_STEP 0x00000004 -#define AUX_SCE_CTL_SINGLE_STEP_BITN 2 -#define AUX_SCE_CTL_SINGLE_STEP_M 0x00000004 -#define AUX_SCE_CTL_SINGLE_STEP_S 2 +#define AUX_SCE_CTL_SINGLE_STEP 0x00000004 +#define AUX_SCE_CTL_SINGLE_STEP_BITN 2 +#define AUX_SCE_CTL_SINGLE_STEP_M 0x00000004 +#define AUX_SCE_CTL_SINGLE_STEP_S 2 // Field: [1] SUSPEND // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_SUSPEND 0x00000002 -#define AUX_SCE_CTL_SUSPEND_BITN 1 -#define AUX_SCE_CTL_SUSPEND_M 0x00000002 -#define AUX_SCE_CTL_SUSPEND_S 1 +#define AUX_SCE_CTL_SUSPEND 0x00000002 +#define AUX_SCE_CTL_SUSPEND_BITN 1 +#define AUX_SCE_CTL_SUSPEND_M 0x00000002 +#define AUX_SCE_CTL_SUSPEND_S 1 // Field: [0] CLK_EN // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_CLK_EN 0x00000001 -#define AUX_SCE_CTL_CLK_EN_BITN 0 -#define AUX_SCE_CTL_CLK_EN_M 0x00000001 -#define AUX_SCE_CTL_CLK_EN_S 0 +#define AUX_SCE_CTL_CLK_EN 0x00000001 +#define AUX_SCE_CTL_CLK_EN_BITN 0 +#define AUX_SCE_CTL_CLK_EN_M 0x00000001 +#define AUX_SCE_CTL_CLK_EN_S 0 //***************************************************************************** // @@ -163,16 +163,16 @@ // Field: [31:16] OPCODE // // Internal. Only to be used through TI provided API. -#define AUX_SCE_FETCHSTAT_OPCODE_W 16 -#define AUX_SCE_FETCHSTAT_OPCODE_M 0xFFFF0000 -#define AUX_SCE_FETCHSTAT_OPCODE_S 16 +#define AUX_SCE_FETCHSTAT_OPCODE_W 16 +#define AUX_SCE_FETCHSTAT_OPCODE_M 0xFFFF0000 +#define AUX_SCE_FETCHSTAT_OPCODE_S 16 // Field: [15:0] PC // // Internal. Only to be used through TI provided API. -#define AUX_SCE_FETCHSTAT_PC_W 16 -#define AUX_SCE_FETCHSTAT_PC_M 0x0000FFFF -#define AUX_SCE_FETCHSTAT_PC_S 0 +#define AUX_SCE_FETCHSTAT_PC_W 16 +#define AUX_SCE_FETCHSTAT_PC_M 0x0000FFFF +#define AUX_SCE_FETCHSTAT_PC_S 0 //***************************************************************************** // @@ -182,66 +182,66 @@ // Field: [11] BUS_ERROR // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_BUS_ERROR 0x00000800 -#define AUX_SCE_CPUSTAT_BUS_ERROR_BITN 11 -#define AUX_SCE_CPUSTAT_BUS_ERROR_M 0x00000800 -#define AUX_SCE_CPUSTAT_BUS_ERROR_S 11 +#define AUX_SCE_CPUSTAT_BUS_ERROR 0x00000800 +#define AUX_SCE_CPUSTAT_BUS_ERROR_BITN 11 +#define AUX_SCE_CPUSTAT_BUS_ERROR_M 0x00000800 +#define AUX_SCE_CPUSTAT_BUS_ERROR_S 11 // Field: [10] SLEEP // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_SLEEP 0x00000400 -#define AUX_SCE_CPUSTAT_SLEEP_BITN 10 -#define AUX_SCE_CPUSTAT_SLEEP_M 0x00000400 -#define AUX_SCE_CPUSTAT_SLEEP_S 10 +#define AUX_SCE_CPUSTAT_SLEEP 0x00000400 +#define AUX_SCE_CPUSTAT_SLEEP_BITN 10 +#define AUX_SCE_CPUSTAT_SLEEP_M 0x00000400 +#define AUX_SCE_CPUSTAT_SLEEP_S 10 // Field: [9] WEV // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_WEV 0x00000200 -#define AUX_SCE_CPUSTAT_WEV_BITN 9 -#define AUX_SCE_CPUSTAT_WEV_M 0x00000200 -#define AUX_SCE_CPUSTAT_WEV_S 9 +#define AUX_SCE_CPUSTAT_WEV 0x00000200 +#define AUX_SCE_CPUSTAT_WEV_BITN 9 +#define AUX_SCE_CPUSTAT_WEV_M 0x00000200 +#define AUX_SCE_CPUSTAT_WEV_S 9 // Field: [8] HALTED // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_HALTED 0x00000100 -#define AUX_SCE_CPUSTAT_HALTED_BITN 8 -#define AUX_SCE_CPUSTAT_HALTED_M 0x00000100 -#define AUX_SCE_CPUSTAT_HALTED_S 8 +#define AUX_SCE_CPUSTAT_HALTED 0x00000100 +#define AUX_SCE_CPUSTAT_HALTED_BITN 8 +#define AUX_SCE_CPUSTAT_HALTED_M 0x00000100 +#define AUX_SCE_CPUSTAT_HALTED_S 8 // Field: [3] V_FLAG // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_V_FLAG 0x00000008 -#define AUX_SCE_CPUSTAT_V_FLAG_BITN 3 -#define AUX_SCE_CPUSTAT_V_FLAG_M 0x00000008 -#define AUX_SCE_CPUSTAT_V_FLAG_S 3 +#define AUX_SCE_CPUSTAT_V_FLAG 0x00000008 +#define AUX_SCE_CPUSTAT_V_FLAG_BITN 3 +#define AUX_SCE_CPUSTAT_V_FLAG_M 0x00000008 +#define AUX_SCE_CPUSTAT_V_FLAG_S 3 // Field: [2] C_FLAG // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_C_FLAG 0x00000004 -#define AUX_SCE_CPUSTAT_C_FLAG_BITN 2 -#define AUX_SCE_CPUSTAT_C_FLAG_M 0x00000004 -#define AUX_SCE_CPUSTAT_C_FLAG_S 2 +#define AUX_SCE_CPUSTAT_C_FLAG 0x00000004 +#define AUX_SCE_CPUSTAT_C_FLAG_BITN 2 +#define AUX_SCE_CPUSTAT_C_FLAG_M 0x00000004 +#define AUX_SCE_CPUSTAT_C_FLAG_S 2 // Field: [1] N_FLAG // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_N_FLAG 0x00000002 -#define AUX_SCE_CPUSTAT_N_FLAG_BITN 1 -#define AUX_SCE_CPUSTAT_N_FLAG_M 0x00000002 -#define AUX_SCE_CPUSTAT_N_FLAG_S 1 +#define AUX_SCE_CPUSTAT_N_FLAG 0x00000002 +#define AUX_SCE_CPUSTAT_N_FLAG_BITN 1 +#define AUX_SCE_CPUSTAT_N_FLAG_M 0x00000002 +#define AUX_SCE_CPUSTAT_N_FLAG_S 1 // Field: [0] Z_FLAG // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_Z_FLAG 0x00000001 -#define AUX_SCE_CPUSTAT_Z_FLAG_BITN 0 -#define AUX_SCE_CPUSTAT_Z_FLAG_M 0x00000001 -#define AUX_SCE_CPUSTAT_Z_FLAG_S 0 +#define AUX_SCE_CPUSTAT_Z_FLAG 0x00000001 +#define AUX_SCE_CPUSTAT_Z_FLAG_BITN 0 +#define AUX_SCE_CPUSTAT_Z_FLAG_M 0x00000001 +#define AUX_SCE_CPUSTAT_Z_FLAG_S 0 //***************************************************************************** // @@ -251,17 +251,17 @@ // Field: [18:16] EXC_VECTOR // // Internal. Only to be used through TI provided API. -#define AUX_SCE_WUSTAT_EXC_VECTOR_W 3 -#define AUX_SCE_WUSTAT_EXC_VECTOR_M 0x00070000 -#define AUX_SCE_WUSTAT_EXC_VECTOR_S 16 +#define AUX_SCE_WUSTAT_EXC_VECTOR_W 3 +#define AUX_SCE_WUSTAT_EXC_VECTOR_M 0x00070000 +#define AUX_SCE_WUSTAT_EXC_VECTOR_S 16 // Field: [8] WU_SIGNAL // // Internal. Only to be used through TI provided API. -#define AUX_SCE_WUSTAT_WU_SIGNAL 0x00000100 -#define AUX_SCE_WUSTAT_WU_SIGNAL_BITN 8 -#define AUX_SCE_WUSTAT_WU_SIGNAL_M 0x00000100 -#define AUX_SCE_WUSTAT_WU_SIGNAL_S 8 +#define AUX_SCE_WUSTAT_WU_SIGNAL 0x00000100 +#define AUX_SCE_WUSTAT_WU_SIGNAL_BITN 8 +#define AUX_SCE_WUSTAT_WU_SIGNAL_M 0x00000100 +#define AUX_SCE_WUSTAT_WU_SIGNAL_S 8 // Field: [7:0] EV_SIGNALS // @@ -275,17 +275,17 @@ // AUX_COMPB Internal. Only to be used through TI provided API. // AUX_COMPA Internal. Only to be used through TI provided API. // AUX_PROG_DLY_IDLE Internal. Only to be used through TI provided API. -#define AUX_SCE_WUSTAT_EV_SIGNALS_W 8 -#define AUX_SCE_WUSTAT_EV_SIGNALS_M 0x000000FF -#define AUX_SCE_WUSTAT_EV_SIGNALS_S 0 -#define AUX_SCE_WUSTAT_EV_SIGNALS_SCEWEV_PROG 0x00000080 -#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_ADC_FIFO_NOT_EMPTY 0x00000040 -#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_TIMER1_EV_OR_IDLE 0x00000020 -#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_TIMER0_EV_OR_IDLE 0x00000010 -#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_TDC_DONE 0x00000008 -#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_COMPB 0x00000004 -#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_COMPA 0x00000002 -#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_PROG_DLY_IDLE 0x00000001 +#define AUX_SCE_WUSTAT_EV_SIGNALS_W 8 +#define AUX_SCE_WUSTAT_EV_SIGNALS_M 0x000000FF +#define AUX_SCE_WUSTAT_EV_SIGNALS_S 0 +#define AUX_SCE_WUSTAT_EV_SIGNALS_SCEWEV_PROG 0x00000080 +#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_ADC_FIFO_NOT_EMPTY 0x00000040 +#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_TIMER1_EV_OR_IDLE 0x00000020 +#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_TIMER0_EV_OR_IDLE 0x00000010 +#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_TDC_DONE 0x00000008 +#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_COMPB 0x00000004 +#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_COMPA 0x00000002 +#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_PROG_DLY_IDLE 0x00000001 //***************************************************************************** // @@ -295,16 +295,16 @@ // Field: [31:16] REG1 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG1_0_REG1_W 16 -#define AUX_SCE_REG1_0_REG1_M 0xFFFF0000 -#define AUX_SCE_REG1_0_REG1_S 16 +#define AUX_SCE_REG1_0_REG1_W 16 +#define AUX_SCE_REG1_0_REG1_M 0xFFFF0000 +#define AUX_SCE_REG1_0_REG1_S 16 // Field: [15:0] REG0 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG1_0_REG0_W 16 -#define AUX_SCE_REG1_0_REG0_M 0x0000FFFF -#define AUX_SCE_REG1_0_REG0_S 0 +#define AUX_SCE_REG1_0_REG0_W 16 +#define AUX_SCE_REG1_0_REG0_M 0x0000FFFF +#define AUX_SCE_REG1_0_REG0_S 0 //***************************************************************************** // @@ -314,16 +314,16 @@ // Field: [31:16] REG3 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG3_2_REG3_W 16 -#define AUX_SCE_REG3_2_REG3_M 0xFFFF0000 -#define AUX_SCE_REG3_2_REG3_S 16 +#define AUX_SCE_REG3_2_REG3_W 16 +#define AUX_SCE_REG3_2_REG3_M 0xFFFF0000 +#define AUX_SCE_REG3_2_REG3_S 16 // Field: [15:0] REG2 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG3_2_REG2_W 16 -#define AUX_SCE_REG3_2_REG2_M 0x0000FFFF -#define AUX_SCE_REG3_2_REG2_S 0 +#define AUX_SCE_REG3_2_REG2_W 16 +#define AUX_SCE_REG3_2_REG2_M 0x0000FFFF +#define AUX_SCE_REG3_2_REG2_S 0 //***************************************************************************** // @@ -333,16 +333,16 @@ // Field: [31:16] REG5 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG5_4_REG5_W 16 -#define AUX_SCE_REG5_4_REG5_M 0xFFFF0000 -#define AUX_SCE_REG5_4_REG5_S 16 +#define AUX_SCE_REG5_4_REG5_W 16 +#define AUX_SCE_REG5_4_REG5_M 0xFFFF0000 +#define AUX_SCE_REG5_4_REG5_S 16 // Field: [15:0] REG4 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG5_4_REG4_W 16 -#define AUX_SCE_REG5_4_REG4_M 0x0000FFFF -#define AUX_SCE_REG5_4_REG4_S 0 +#define AUX_SCE_REG5_4_REG4_W 16 +#define AUX_SCE_REG5_4_REG4_M 0x0000FFFF +#define AUX_SCE_REG5_4_REG4_S 0 //***************************************************************************** // @@ -352,16 +352,16 @@ // Field: [31:16] REG7 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG7_6_REG7_W 16 -#define AUX_SCE_REG7_6_REG7_M 0xFFFF0000 -#define AUX_SCE_REG7_6_REG7_S 16 +#define AUX_SCE_REG7_6_REG7_W 16 +#define AUX_SCE_REG7_6_REG7_M 0xFFFF0000 +#define AUX_SCE_REG7_6_REG7_S 16 // Field: [15:0] REG6 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG7_6_REG6_W 16 -#define AUX_SCE_REG7_6_REG6_M 0x0000FFFF -#define AUX_SCE_REG7_6_REG6_S 0 +#define AUX_SCE_REG7_6_REG6_W 16 +#define AUX_SCE_REG7_6_REG6_M 0x0000FFFF +#define AUX_SCE_REG7_6_REG6_S 0 //***************************************************************************** // @@ -371,16 +371,16 @@ // Field: [31:16] STOP // // Internal. Only to be used through TI provided API. -#define AUX_SCE_LOOPADDR_STOP_W 16 -#define AUX_SCE_LOOPADDR_STOP_M 0xFFFF0000 -#define AUX_SCE_LOOPADDR_STOP_S 16 +#define AUX_SCE_LOOPADDR_STOP_W 16 +#define AUX_SCE_LOOPADDR_STOP_M 0xFFFF0000 +#define AUX_SCE_LOOPADDR_STOP_S 16 // Field: [15:0] START // // Internal. Only to be used through TI provided API. -#define AUX_SCE_LOOPADDR_START_W 16 -#define AUX_SCE_LOOPADDR_START_M 0x0000FFFF -#define AUX_SCE_LOOPADDR_START_S 0 +#define AUX_SCE_LOOPADDR_START_W 16 +#define AUX_SCE_LOOPADDR_START_M 0x0000FFFF +#define AUX_SCE_LOOPADDR_START_S 0 //***************************************************************************** // @@ -390,9 +390,8 @@ // Field: [7:0] ITER_LEFT // // Internal. Only to be used through TI provided API. -#define AUX_SCE_LOOPCNT_ITER_LEFT_W 8 -#define AUX_SCE_LOOPCNT_ITER_LEFT_M 0x000000FF -#define AUX_SCE_LOOPCNT_ITER_LEFT_S 0 - +#define AUX_SCE_LOOPCNT_ITER_LEFT_W 8 +#define AUX_SCE_LOOPCNT_ITER_LEFT_M 0x000000FF +#define AUX_SCE_LOOPCNT_ITER_LEFT_S 0 #endif // __AUX_SCE__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_smph.h index 3f6555e..66f8f3a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_smph.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_smph.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_smph_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_smph_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_SMPH_H__ #define __HW_AUX_SMPH_H__ @@ -44,31 +44,31 @@ // //***************************************************************************** // Semaphore 0 -#define AUX_SMPH_O_SMPH0 0x00000000 +#define AUX_SMPH_O_SMPH0 0x00000000 // Semaphore 1 -#define AUX_SMPH_O_SMPH1 0x00000004 +#define AUX_SMPH_O_SMPH1 0x00000004 // Semaphore 2 -#define AUX_SMPH_O_SMPH2 0x00000008 +#define AUX_SMPH_O_SMPH2 0x00000008 // Semaphore 3 -#define AUX_SMPH_O_SMPH3 0x0000000C +#define AUX_SMPH_O_SMPH3 0x0000000C // Semaphore 4 -#define AUX_SMPH_O_SMPH4 0x00000010 +#define AUX_SMPH_O_SMPH4 0x00000010 // Semaphore 5 -#define AUX_SMPH_O_SMPH5 0x00000014 +#define AUX_SMPH_O_SMPH5 0x00000014 // Semaphore 6 -#define AUX_SMPH_O_SMPH6 0x00000018 +#define AUX_SMPH_O_SMPH6 0x00000018 // Semaphore 7 -#define AUX_SMPH_O_SMPH7 0x0000001C +#define AUX_SMPH_O_SMPH7 0x0000001C // Auto Take -#define AUX_SMPH_O_AUTOTAKE 0x00000020 +#define AUX_SMPH_O_AUTOTAKE 0x00000020 //***************************************************************************** // @@ -88,10 +88,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH0_STAT 0x00000001 -#define AUX_SMPH_SMPH0_STAT_BITN 0 -#define AUX_SMPH_SMPH0_STAT_M 0x00000001 -#define AUX_SMPH_SMPH0_STAT_S 0 +#define AUX_SMPH_SMPH0_STAT 0x00000001 +#define AUX_SMPH_SMPH0_STAT_BITN 0 +#define AUX_SMPH_SMPH0_STAT_M 0x00000001 +#define AUX_SMPH_SMPH0_STAT_S 0 //***************************************************************************** // @@ -111,10 +111,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH1_STAT 0x00000001 -#define AUX_SMPH_SMPH1_STAT_BITN 0 -#define AUX_SMPH_SMPH1_STAT_M 0x00000001 -#define AUX_SMPH_SMPH1_STAT_S 0 +#define AUX_SMPH_SMPH1_STAT 0x00000001 +#define AUX_SMPH_SMPH1_STAT_BITN 0 +#define AUX_SMPH_SMPH1_STAT_M 0x00000001 +#define AUX_SMPH_SMPH1_STAT_S 0 //***************************************************************************** // @@ -134,10 +134,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH2_STAT 0x00000001 -#define AUX_SMPH_SMPH2_STAT_BITN 0 -#define AUX_SMPH_SMPH2_STAT_M 0x00000001 -#define AUX_SMPH_SMPH2_STAT_S 0 +#define AUX_SMPH_SMPH2_STAT 0x00000001 +#define AUX_SMPH_SMPH2_STAT_BITN 0 +#define AUX_SMPH_SMPH2_STAT_M 0x00000001 +#define AUX_SMPH_SMPH2_STAT_S 0 //***************************************************************************** // @@ -157,10 +157,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH3_STAT 0x00000001 -#define AUX_SMPH_SMPH3_STAT_BITN 0 -#define AUX_SMPH_SMPH3_STAT_M 0x00000001 -#define AUX_SMPH_SMPH3_STAT_S 0 +#define AUX_SMPH_SMPH3_STAT 0x00000001 +#define AUX_SMPH_SMPH3_STAT_BITN 0 +#define AUX_SMPH_SMPH3_STAT_M 0x00000001 +#define AUX_SMPH_SMPH3_STAT_S 0 //***************************************************************************** // @@ -180,10 +180,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH4_STAT 0x00000001 -#define AUX_SMPH_SMPH4_STAT_BITN 0 -#define AUX_SMPH_SMPH4_STAT_M 0x00000001 -#define AUX_SMPH_SMPH4_STAT_S 0 +#define AUX_SMPH_SMPH4_STAT 0x00000001 +#define AUX_SMPH_SMPH4_STAT_BITN 0 +#define AUX_SMPH_SMPH4_STAT_M 0x00000001 +#define AUX_SMPH_SMPH4_STAT_S 0 //***************************************************************************** // @@ -203,10 +203,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH5_STAT 0x00000001 -#define AUX_SMPH_SMPH5_STAT_BITN 0 -#define AUX_SMPH_SMPH5_STAT_M 0x00000001 -#define AUX_SMPH_SMPH5_STAT_S 0 +#define AUX_SMPH_SMPH5_STAT 0x00000001 +#define AUX_SMPH_SMPH5_STAT_BITN 0 +#define AUX_SMPH_SMPH5_STAT_M 0x00000001 +#define AUX_SMPH_SMPH5_STAT_S 0 //***************************************************************************** // @@ -226,10 +226,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH6_STAT 0x00000001 -#define AUX_SMPH_SMPH6_STAT_BITN 0 -#define AUX_SMPH_SMPH6_STAT_M 0x00000001 -#define AUX_SMPH_SMPH6_STAT_S 0 +#define AUX_SMPH_SMPH6_STAT 0x00000001 +#define AUX_SMPH_SMPH6_STAT_BITN 0 +#define AUX_SMPH_SMPH6_STAT_M 0x00000001 +#define AUX_SMPH_SMPH6_STAT_S 0 //***************************************************************************** // @@ -249,10 +249,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH7_STAT 0x00000001 -#define AUX_SMPH_SMPH7_STAT_BITN 0 -#define AUX_SMPH_SMPH7_STAT_M 0x00000001 -#define AUX_SMPH_SMPH7_STAT_S 0 +#define AUX_SMPH_SMPH7_STAT 0x00000001 +#define AUX_SMPH_SMPH7_STAT_BITN 0 +#define AUX_SMPH_SMPH7_STAT_M 0x00000001 +#define AUX_SMPH_SMPH7_STAT_S 0 //***************************************************************************** // @@ -274,9 +274,8 @@ // - Usage of this functionality must be restricted to one CPU core. // - Software must wait until AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE is 1 // before it writes a new value to SMPH_ID. -#define AUX_SMPH_AUTOTAKE_SMPH_ID_W 3 -#define AUX_SMPH_AUTOTAKE_SMPH_ID_M 0x00000007 -#define AUX_SMPH_AUTOTAKE_SMPH_ID_S 0 - +#define AUX_SMPH_AUTOTAKE_SMPH_ID_W 3 +#define AUX_SMPH_AUTOTAKE_SMPH_ID_M 0x00000007 +#define AUX_SMPH_AUTOTAKE_SMPH_ID_S 0 #endif // __AUX_SMPH__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_spim.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_spim.h index baf3482..72bb912 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_spim.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_spim.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_spim_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_spim_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_SPIM_H__ #define __HW_AUX_SPIM_H__ @@ -44,31 +44,31 @@ // //***************************************************************************** // SPI Master Configuration -#define AUX_SPIM_O_SPIMCFG 0x00000000 +#define AUX_SPIM_O_SPIMCFG 0x00000000 // MISO Configuration -#define AUX_SPIM_O_MISOCFG 0x00000004 +#define AUX_SPIM_O_MISOCFG 0x00000004 // MOSI Control -#define AUX_SPIM_O_MOSICTL 0x00000008 +#define AUX_SPIM_O_MOSICTL 0x00000008 // Transmit 8 Bit -#define AUX_SPIM_O_TX8 0x0000000C +#define AUX_SPIM_O_TX8 0x0000000C // Transmit 16 Bit -#define AUX_SPIM_O_TX16 0x00000010 +#define AUX_SPIM_O_TX16 0x00000010 // Receive 8 Bit -#define AUX_SPIM_O_RX8 0x00000014 +#define AUX_SPIM_O_RX8 0x00000014 // Receive 16 Bit -#define AUX_SPIM_O_RX16 0x00000018 +#define AUX_SPIM_O_RX16 0x00000018 // SCLK Idle -#define AUX_SPIM_O_SCLKIDLE 0x0000001C +#define AUX_SPIM_O_SCLKIDLE 0x0000001C // Data Idle -#define AUX_SPIM_O_DATAIDLE 0x00000020 +#define AUX_SPIM_O_DATAIDLE 0x00000020 //***************************************************************************** // @@ -87,9 +87,9 @@ // 0x02: Divide by 6. // ... // 0x3F: Divide by 128. -#define AUX_SPIM_SPIMCFG_DIV_W 6 -#define AUX_SPIM_SPIMCFG_DIV_M 0x000000FC -#define AUX_SPIM_SPIMCFG_DIV_S 2 +#define AUX_SPIM_SPIMCFG_DIV_W 6 +#define AUX_SPIM_SPIMCFG_DIV_M 0x000000FC +#define AUX_SPIM_SPIMCFG_DIV_S 2 // Field: [1] PHA // @@ -99,10 +99,10 @@ // edges of SCLK. // 1: Sample MISO at trailing (even) edges and shift MOSI at leading (odd) // edges of SCLK. -#define AUX_SPIM_SPIMCFG_PHA 0x00000002 -#define AUX_SPIM_SPIMCFG_PHA_BITN 1 -#define AUX_SPIM_SPIMCFG_PHA_M 0x00000002 -#define AUX_SPIM_SPIMCFG_PHA_S 1 +#define AUX_SPIM_SPIMCFG_PHA 0x00000002 +#define AUX_SPIM_SPIMCFG_PHA_BITN 1 +#define AUX_SPIM_SPIMCFG_PHA_M 0x00000002 +#define AUX_SPIM_SPIMCFG_PHA_S 1 // Field: [0] POL // @@ -110,10 +110,10 @@ // // 0: SCLK is low when idle, first clock edge rises. // 1: SCLK is high when idle, first clock edge falls. -#define AUX_SPIM_SPIMCFG_POL 0x00000001 -#define AUX_SPIM_SPIMCFG_POL_BITN 0 -#define AUX_SPIM_SPIMCFG_POL_M 0x00000001 -#define AUX_SPIM_SPIMCFG_POL_S 0 +#define AUX_SPIM_SPIMCFG_POL 0x00000001 +#define AUX_SPIM_SPIMCFG_POL_BITN 0 +#define AUX_SPIM_SPIMCFG_POL_M 0x00000001 +#define AUX_SPIM_SPIMCFG_POL_S 0 //***************************************************************************** // @@ -125,9 +125,9 @@ // AUXIO to MISO mux. // // Select the AUXIO pin that connects to MISO. -#define AUX_SPIM_MISOCFG_AUXIO_W 5 -#define AUX_SPIM_MISOCFG_AUXIO_M 0x0000001F -#define AUX_SPIM_MISOCFG_AUXIO_S 0 +#define AUX_SPIM_MISOCFG_AUXIO_W 5 +#define AUX_SPIM_MISOCFG_AUXIO_M 0x0000001F +#define AUX_SPIM_MISOCFG_AUXIO_S 0 //***************************************************************************** // @@ -140,10 +140,10 @@ // // 0: Set MOSI low. // 1: Set MOSI high. -#define AUX_SPIM_MOSICTL_VALUE 0x00000001 -#define AUX_SPIM_MOSICTL_VALUE_BITN 0 -#define AUX_SPIM_MOSICTL_VALUE_M 0x00000001 -#define AUX_SPIM_MOSICTL_VALUE_S 0 +#define AUX_SPIM_MOSICTL_VALUE 0x00000001 +#define AUX_SPIM_MOSICTL_VALUE_BITN 0 +#define AUX_SPIM_MOSICTL_VALUE_M 0x00000001 +#define AUX_SPIM_MOSICTL_VALUE_S 0 //***************************************************************************** // @@ -156,9 +156,9 @@ // // Write DATA to start transfer, MSB first. When transfer completes, MOSI stays // at the value of LSB. -#define AUX_SPIM_TX8_DATA_W 8 -#define AUX_SPIM_TX8_DATA_M 0x000000FF -#define AUX_SPIM_TX8_DATA_S 0 +#define AUX_SPIM_TX8_DATA_W 8 +#define AUX_SPIM_TX8_DATA_M 0x000000FF +#define AUX_SPIM_TX8_DATA_S 0 //***************************************************************************** // @@ -171,9 +171,9 @@ // // Write DATA to start transfer, MSB first. When transfer completes, MOSI stays // at the value of LSB. -#define AUX_SPIM_TX16_DATA_W 16 -#define AUX_SPIM_TX16_DATA_M 0x0000FFFF -#define AUX_SPIM_TX16_DATA_S 0 +#define AUX_SPIM_TX16_DATA_W 16 +#define AUX_SPIM_TX16_DATA_M 0x0000FFFF +#define AUX_SPIM_TX16_DATA_S 0 //***************************************************************************** // @@ -183,9 +183,9 @@ // Field: [7:0] DATA // // Latest 8 bits received on MISO. -#define AUX_SPIM_RX8_DATA_W 8 -#define AUX_SPIM_RX8_DATA_M 0x000000FF -#define AUX_SPIM_RX8_DATA_S 0 +#define AUX_SPIM_RX8_DATA_W 8 +#define AUX_SPIM_RX8_DATA_M 0x000000FF +#define AUX_SPIM_RX8_DATA_S 0 //***************************************************************************** // @@ -195,9 +195,9 @@ // Field: [15:0] DATA // // Latest 16 bits received on MISO. -#define AUX_SPIM_RX16_DATA_W 16 -#define AUX_SPIM_RX16_DATA_M 0x0000FFFF -#define AUX_SPIM_RX16_DATA_S 0 +#define AUX_SPIM_RX16_DATA_W 16 +#define AUX_SPIM_RX16_DATA_M 0x0000FFFF +#define AUX_SPIM_RX16_DATA_S 0 //***************************************************************************** // @@ -212,10 +212,10 @@ // then returns 1. // // AUX_SCE can use this to control CS deassertion. -#define AUX_SPIM_SCLKIDLE_STAT 0x00000001 -#define AUX_SPIM_SCLKIDLE_STAT_BITN 0 -#define AUX_SPIM_SCLKIDLE_STAT_M 0x00000001 -#define AUX_SPIM_SCLKIDLE_STAT_S 0 +#define AUX_SPIM_SCLKIDLE_STAT 0x00000001 +#define AUX_SPIM_SCLKIDLE_STAT_BITN 0 +#define AUX_SPIM_SCLKIDLE_STAT_M 0x00000001 +#define AUX_SPIM_SCLKIDLE_STAT_S 0 //***************************************************************************** // @@ -230,10 +230,9 @@ // completes. Read then returns 1. // // AUX_SCE can use this to control CS deassertion. -#define AUX_SPIM_DATAIDLE_STAT 0x00000001 -#define AUX_SPIM_DATAIDLE_STAT_BITN 0 -#define AUX_SPIM_DATAIDLE_STAT_M 0x00000001 -#define AUX_SPIM_DATAIDLE_STAT_S 0 - +#define AUX_SPIM_DATAIDLE_STAT 0x00000001 +#define AUX_SPIM_DATAIDLE_STAT_BITN 0 +#define AUX_SPIM_DATAIDLE_STAT_M 0x00000001 +#define AUX_SPIM_DATAIDLE_STAT_S 0 #endif // __AUX_SPIM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sysif.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sysif.h index 8b7ab84..fe7ecbc 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sysif.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sysif.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_sysif_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_sysif_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_SYSIF_H__ #define __HW_AUX_SYSIF_H__ @@ -44,127 +44,127 @@ // //***************************************************************************** // Operational Mode Request -#define AUX_SYSIF_O_OPMODEREQ 0x00000000 +#define AUX_SYSIF_O_OPMODEREQ 0x00000000 // Operational Mode Acknowledgement -#define AUX_SYSIF_O_OPMODEACK 0x00000004 +#define AUX_SYSIF_O_OPMODEACK 0x00000004 // Programmable Wakeup 0 Configuration -#define AUX_SYSIF_O_PROGWU0CFG 0x00000008 +#define AUX_SYSIF_O_PROGWU0CFG 0x00000008 // Programmable Wakeup 1 Configuration -#define AUX_SYSIF_O_PROGWU1CFG 0x0000000C +#define AUX_SYSIF_O_PROGWU1CFG 0x0000000C // Programmable Wakeup 2 Configuration -#define AUX_SYSIF_O_PROGWU2CFG 0x00000010 +#define AUX_SYSIF_O_PROGWU2CFG 0x00000010 // Programmable Wakeup 3 Configuration -#define AUX_SYSIF_O_PROGWU3CFG 0x00000014 +#define AUX_SYSIF_O_PROGWU3CFG 0x00000014 // Software Wakeup Triggers -#define AUX_SYSIF_O_SWWUTRIG 0x00000018 +#define AUX_SYSIF_O_SWWUTRIG 0x00000018 // Wakeup Flags -#define AUX_SYSIF_O_WUFLAGS 0x0000001C +#define AUX_SYSIF_O_WUFLAGS 0x0000001C // Wakeup Flags Clear -#define AUX_SYSIF_O_WUFLAGSCLR 0x00000020 +#define AUX_SYSIF_O_WUFLAGSCLR 0x00000020 // Wakeup Gate -#define AUX_SYSIF_O_WUGATE 0x00000024 +#define AUX_SYSIF_O_WUGATE 0x00000024 // Vector Configuration 0 -#define AUX_SYSIF_O_VECCFG0 0x00000028 +#define AUX_SYSIF_O_VECCFG0 0x00000028 // Vector Configuration 1 -#define AUX_SYSIF_O_VECCFG1 0x0000002C +#define AUX_SYSIF_O_VECCFG1 0x0000002C // Vector Configuration 2 -#define AUX_SYSIF_O_VECCFG2 0x00000030 +#define AUX_SYSIF_O_VECCFG2 0x00000030 // Vector Configuration 3 -#define AUX_SYSIF_O_VECCFG3 0x00000034 +#define AUX_SYSIF_O_VECCFG3 0x00000034 // Vector Configuration 4 -#define AUX_SYSIF_O_VECCFG4 0x00000038 +#define AUX_SYSIF_O_VECCFG4 0x00000038 // Vector Configuration 5 -#define AUX_SYSIF_O_VECCFG5 0x0000003C +#define AUX_SYSIF_O_VECCFG5 0x0000003C // Vector Configuration 6 -#define AUX_SYSIF_O_VECCFG6 0x00000040 +#define AUX_SYSIF_O_VECCFG6 0x00000040 // Vector Configuration 7 -#define AUX_SYSIF_O_VECCFG7 0x00000044 +#define AUX_SYSIF_O_VECCFG7 0x00000044 // Event Synchronization Rate -#define AUX_SYSIF_O_EVSYNCRATE 0x00000048 +#define AUX_SYSIF_O_EVSYNCRATE 0x00000048 // Peripheral Operational Rate -#define AUX_SYSIF_O_PEROPRATE 0x0000004C +#define AUX_SYSIF_O_PEROPRATE 0x0000004C // ADC Clock Control -#define AUX_SYSIF_O_ADCCLKCTL 0x00000050 +#define AUX_SYSIF_O_ADCCLKCTL 0x00000050 // TDC Counter Clock Control -#define AUX_SYSIF_O_TDCCLKCTL 0x00000054 +#define AUX_SYSIF_O_TDCCLKCTL 0x00000054 // TDC Reference Clock Control -#define AUX_SYSIF_O_TDCREFCLKCTL 0x00000058 +#define AUX_SYSIF_O_TDCREFCLKCTL 0x00000058 // AUX_TIMER2 Clock Control -#define AUX_SYSIF_O_TIMER2CLKCTL 0x0000005C +#define AUX_SYSIF_O_TIMER2CLKCTL 0x0000005C // AUX_TIMER2 Clock Status -#define AUX_SYSIF_O_TIMER2CLKSTAT 0x00000060 +#define AUX_SYSIF_O_TIMER2CLKSTAT 0x00000060 // AUX_TIMER2 Clock Switch -#define AUX_SYSIF_O_TIMER2CLKSWITCH 0x00000064 +#define AUX_SYSIF_O_TIMER2CLKSWITCH 0x00000064 // AUX_TIMER2 Debug Control -#define AUX_SYSIF_O_TIMER2DBGCTL 0x00000068 +#define AUX_SYSIF_O_TIMER2DBGCTL 0x00000068 // Clock Shift Detection -#define AUX_SYSIF_O_CLKSHIFTDET 0x00000070 +#define AUX_SYSIF_O_CLKSHIFTDET 0x00000070 // VDDR Recharge Trigger -#define AUX_SYSIF_O_RECHARGETRIG 0x00000074 +#define AUX_SYSIF_O_RECHARGETRIG 0x00000074 // VDDR Recharge Detection -#define AUX_SYSIF_O_RECHARGEDET 0x00000078 +#define AUX_SYSIF_O_RECHARGEDET 0x00000078 // Real Time Counter Sub Second Increment 0 -#define AUX_SYSIF_O_RTCSUBSECINC0 0x0000007C +#define AUX_SYSIF_O_RTCSUBSECINC0 0x0000007C // Real Time Counter Sub Second Increment 1 -#define AUX_SYSIF_O_RTCSUBSECINC1 0x00000080 +#define AUX_SYSIF_O_RTCSUBSECINC1 0x00000080 // Real Time Counter Sub Second Increment Control -#define AUX_SYSIF_O_RTCSUBSECINCCTL 0x00000084 +#define AUX_SYSIF_O_RTCSUBSECINCCTL 0x00000084 // Real Time Counter Second -#define AUX_SYSIF_O_RTCSEC 0x00000088 +#define AUX_SYSIF_O_RTCSEC 0x00000088 // Real Time Counter Sub-Second -#define AUX_SYSIF_O_RTCSUBSEC 0x0000008C +#define AUX_SYSIF_O_RTCSUBSEC 0x0000008C // AON_RTC Event Clear -#define AUX_SYSIF_O_RTCEVCLR 0x00000090 +#define AUX_SYSIF_O_RTCEVCLR 0x00000090 // AON_BATMON Battery Voltage Value -#define AUX_SYSIF_O_BATMONBAT 0x00000094 +#define AUX_SYSIF_O_BATMONBAT 0x00000094 // AON_BATMON Temperature Value -#define AUX_SYSIF_O_BATMONTEMP 0x0000009C +#define AUX_SYSIF_O_BATMONTEMP 0x0000009C // Timer Halt -#define AUX_SYSIF_O_TIMERHALT 0x000000A0 +#define AUX_SYSIF_O_TIMERHALT 0x000000A0 // AUX_TIMER2 Bridge -#define AUX_SYSIF_O_TIMER2BRIDGE 0x000000B0 +#define AUX_SYSIF_O_TIMER2BRIDGE 0x000000B0 // Software Power Profiler -#define AUX_SYSIF_O_SWPWRPROF 0x000000B4 +#define AUX_SYSIF_O_SWPWRPROF 0x000000B4 //***************************************************************************** // @@ -209,13 +209,13 @@ // sets the SCE clock frequency (SCE_RATE). // - An active wakeup flag // does not change operational mode. -#define AUX_SYSIF_OPMODEREQ_REQ_W 2 -#define AUX_SYSIF_OPMODEREQ_REQ_M 0x00000003 -#define AUX_SYSIF_OPMODEREQ_REQ_S 0 -#define AUX_SYSIF_OPMODEREQ_REQ_PDLP 0x00000003 -#define AUX_SYSIF_OPMODEREQ_REQ_PDA 0x00000002 -#define AUX_SYSIF_OPMODEREQ_REQ_LP 0x00000001 -#define AUX_SYSIF_OPMODEREQ_REQ_A 0x00000000 +#define AUX_SYSIF_OPMODEREQ_REQ_W 2 +#define AUX_SYSIF_OPMODEREQ_REQ_M 0x00000003 +#define AUX_SYSIF_OPMODEREQ_REQ_S 0 +#define AUX_SYSIF_OPMODEREQ_REQ_PDLP 0x00000003 +#define AUX_SYSIF_OPMODEREQ_REQ_PDA 0x00000002 +#define AUX_SYSIF_OPMODEREQ_REQ_LP 0x00000001 +#define AUX_SYSIF_OPMODEREQ_REQ_A 0x00000000 //***************************************************************************** // @@ -232,13 +232,13 @@ // mode is acknowledged. // LP Lowpower operational mode is acknowledged. // A Active operational mode is acknowledged. -#define AUX_SYSIF_OPMODEACK_ACK_W 2 -#define AUX_SYSIF_OPMODEACK_ACK_M 0x00000003 -#define AUX_SYSIF_OPMODEACK_ACK_S 0 -#define AUX_SYSIF_OPMODEACK_ACK_PDLP 0x00000003 -#define AUX_SYSIF_OPMODEACK_ACK_PDA 0x00000002 -#define AUX_SYSIF_OPMODEACK_ACK_LP 0x00000001 -#define AUX_SYSIF_OPMODEACK_ACK_A 0x00000000 +#define AUX_SYSIF_OPMODEACK_ACK_W 2 +#define AUX_SYSIF_OPMODEACK_ACK_M 0x00000003 +#define AUX_SYSIF_OPMODEACK_ACK_S 0 +#define AUX_SYSIF_OPMODEACK_ACK_PDLP 0x00000003 +#define AUX_SYSIF_OPMODEACK_ACK_PDA 0x00000002 +#define AUX_SYSIF_OPMODEACK_ACK_LP 0x00000001 +#define AUX_SYSIF_OPMODEACK_ACK_A 0x00000000 //***************************************************************************** // @@ -256,12 +256,12 @@ // low. // HIGH The wakeup flag is set when WU_SRC is high or goes // high. -#define AUX_SYSIF_PROGWU0CFG_POL 0x00000080 -#define AUX_SYSIF_PROGWU0CFG_POL_BITN 7 -#define AUX_SYSIF_PROGWU0CFG_POL_M 0x00000080 -#define AUX_SYSIF_PROGWU0CFG_POL_S 7 -#define AUX_SYSIF_PROGWU0CFG_POL_LOW 0x00000080 -#define AUX_SYSIF_PROGWU0CFG_POL_HIGH 0x00000000 +#define AUX_SYSIF_PROGWU0CFG_POL 0x00000080 +#define AUX_SYSIF_PROGWU0CFG_POL_BITN 7 +#define AUX_SYSIF_PROGWU0CFG_POL_M 0x00000080 +#define AUX_SYSIF_PROGWU0CFG_POL_S 7 +#define AUX_SYSIF_PROGWU0CFG_POL_LOW 0x00000080 +#define AUX_SYSIF_PROGWU0CFG_POL_HIGH 0x00000000 // Field: [6] EN // @@ -269,10 +269,10 @@ // // 0: Disable wakeup flag. // 1: Enable wakeup flag. -#define AUX_SYSIF_PROGWU0CFG_EN 0x00000040 -#define AUX_SYSIF_PROGWU0CFG_EN_BITN 6 -#define AUX_SYSIF_PROGWU0CFG_EN_M 0x00000040 -#define AUX_SYSIF_PROGWU0CFG_EN_S 6 +#define AUX_SYSIF_PROGWU0CFG_EN 0x00000040 +#define AUX_SYSIF_PROGWU0CFG_EN_BITN 6 +#define AUX_SYSIF_PROGWU0CFG_EN_M 0x00000040 +#define AUX_SYSIF_PROGWU0CFG_EN_S 6 // Field: [5:0] WU_SRC // @@ -346,72 +346,72 @@ // AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 // AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 // AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_W 6 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_M 0x0000003F -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_S 0 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_NO_EVENT 0x0000003F -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_DONE 0x00000039 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TDC_DONE 0x00000037 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER0_EV 0x00000036 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER1_EV 0x00000035 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_COMPB 0x0000002F -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_COMPA 0x0000002E -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_OBSMUX1 0x0000002D -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_OBSMUX0 0x0000002C -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_EV 0x0000002B -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_ACLK_REF 0x0000002A -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_VDDR_RECHARGE 0x00000029 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_ACTIVE 0x00000028 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_PWR_DWN 0x00000027 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_SCLK_LF 0x00000026 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_RTC_4KHZ 0x00000023 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_RTC_CH2 0x00000021 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MANUAL_EV 0x00000020 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO31 0x0000001F -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO30 0x0000001E -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO29 0x0000001D -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO28 0x0000001C -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO27 0x0000001B -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO26 0x0000001A -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO25 0x00000019 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO24 0x00000018 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO23 0x00000017 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO22 0x00000016 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO21 0x00000015 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO20 0x00000014 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO19 0x00000013 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO18 0x00000012 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO17 0x00000011 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO16 0x00000010 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO15 0x0000000F -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO14 0x0000000E -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO13 0x0000000D -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO12 0x0000000C -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO11 0x0000000B -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO10 0x0000000A -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO9 0x00000009 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO8 0x00000008 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO7 0x00000007 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO6 0x00000006 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO5 0x00000005 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO4 0x00000004 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO3 0x00000003 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO2 0x00000002 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO1 0x00000001 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO0 0x00000000 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_W 6 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_M 0x0000003F +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_S 0 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_NO_EVENT 0x0000003F +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_DONE 0x00000039 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TDC_DONE 0x00000037 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER0_EV 0x00000036 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER1_EV 0x00000035 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_COMPB 0x0000002F +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_COMPA 0x0000002E +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_OBSMUX1 0x0000002D +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_OBSMUX0 0x0000002C +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_EV 0x0000002B +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_ACLK_REF 0x0000002A +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_VDDR_RECHARGE 0x00000029 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_ACTIVE 0x00000028 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_PWR_DWN 0x00000027 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_SCLK_LF 0x00000026 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_RTC_4KHZ 0x00000023 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_RTC_CH2 0x00000021 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MANUAL_EV 0x00000020 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO31 0x0000001F +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO30 0x0000001E +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO29 0x0000001D +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO28 0x0000001C +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO27 0x0000001B +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO26 0x0000001A +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO25 0x00000019 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO24 0x00000018 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO23 0x00000017 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO22 0x00000016 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO21 0x00000015 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO20 0x00000014 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO19 0x00000013 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO18 0x00000012 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO17 0x00000011 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO16 0x00000010 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO15 0x0000000F +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO14 0x0000000E +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO13 0x0000000D +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO12 0x0000000C +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO11 0x0000000B +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO10 0x0000000A +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO9 0x00000009 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO8 0x00000008 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO7 0x00000007 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO6 0x00000006 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO5 0x00000005 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO4 0x00000004 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO3 0x00000003 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO2 0x00000002 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO1 0x00000001 +#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO0 0x00000000 //***************************************************************************** // @@ -429,12 +429,12 @@ // low. // HIGH The wakeup flag is set when WU_SRC is high or goes // high. -#define AUX_SYSIF_PROGWU1CFG_POL 0x00000080 -#define AUX_SYSIF_PROGWU1CFG_POL_BITN 7 -#define AUX_SYSIF_PROGWU1CFG_POL_M 0x00000080 -#define AUX_SYSIF_PROGWU1CFG_POL_S 7 -#define AUX_SYSIF_PROGWU1CFG_POL_LOW 0x00000080 -#define AUX_SYSIF_PROGWU1CFG_POL_HIGH 0x00000000 +#define AUX_SYSIF_PROGWU1CFG_POL 0x00000080 +#define AUX_SYSIF_PROGWU1CFG_POL_BITN 7 +#define AUX_SYSIF_PROGWU1CFG_POL_M 0x00000080 +#define AUX_SYSIF_PROGWU1CFG_POL_S 7 +#define AUX_SYSIF_PROGWU1CFG_POL_LOW 0x00000080 +#define AUX_SYSIF_PROGWU1CFG_POL_HIGH 0x00000000 // Field: [6] EN // @@ -442,10 +442,10 @@ // // 0: Disable wakeup flag. // 1: Enable wakeup flag. -#define AUX_SYSIF_PROGWU1CFG_EN 0x00000040 -#define AUX_SYSIF_PROGWU1CFG_EN_BITN 6 -#define AUX_SYSIF_PROGWU1CFG_EN_M 0x00000040 -#define AUX_SYSIF_PROGWU1CFG_EN_S 6 +#define AUX_SYSIF_PROGWU1CFG_EN 0x00000040 +#define AUX_SYSIF_PROGWU1CFG_EN_BITN 6 +#define AUX_SYSIF_PROGWU1CFG_EN_M 0x00000040 +#define AUX_SYSIF_PROGWU1CFG_EN_S 6 // Field: [5:0] WU_SRC // @@ -519,72 +519,72 @@ // AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 // AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 // AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_W 6 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_M 0x0000003F -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_S 0 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_NO_EVENT 0x0000003F -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_DONE 0x00000039 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TDC_DONE 0x00000037 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER0_EV 0x00000036 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER1_EV 0x00000035 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_COMPB 0x0000002F -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_COMPA 0x0000002E -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_OBSMUX1 0x0000002D -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_OBSMUX0 0x0000002C -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_EV 0x0000002B -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_ACLK_REF 0x0000002A -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_VDDR_RECHARGE 0x00000029 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_ACTIVE 0x00000028 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_PWR_DWN 0x00000027 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_SCLK_LF 0x00000026 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_RTC_4KHZ 0x00000023 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_RTC_CH2 0x00000021 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MANUAL_EV 0x00000020 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO31 0x0000001F -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO30 0x0000001E -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO29 0x0000001D -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO28 0x0000001C -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO27 0x0000001B -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO26 0x0000001A -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO25 0x00000019 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO24 0x00000018 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO23 0x00000017 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO22 0x00000016 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO21 0x00000015 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO20 0x00000014 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO19 0x00000013 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO18 0x00000012 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO17 0x00000011 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO16 0x00000010 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO15 0x0000000F -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO14 0x0000000E -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO13 0x0000000D -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO12 0x0000000C -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO11 0x0000000B -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO10 0x0000000A -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO9 0x00000009 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO8 0x00000008 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO7 0x00000007 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO6 0x00000006 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO5 0x00000005 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO4 0x00000004 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO3 0x00000003 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO2 0x00000002 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO1 0x00000001 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO0 0x00000000 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_W 6 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_M 0x0000003F +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_S 0 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_NO_EVENT 0x0000003F +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_DONE 0x00000039 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TDC_DONE 0x00000037 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER0_EV 0x00000036 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER1_EV 0x00000035 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_COMPB 0x0000002F +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_COMPA 0x0000002E +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_OBSMUX1 0x0000002D +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_OBSMUX0 0x0000002C +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_EV 0x0000002B +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_ACLK_REF 0x0000002A +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_VDDR_RECHARGE 0x00000029 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_ACTIVE 0x00000028 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_PWR_DWN 0x00000027 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_SCLK_LF 0x00000026 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_RTC_4KHZ 0x00000023 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_RTC_CH2 0x00000021 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MANUAL_EV 0x00000020 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO31 0x0000001F +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO30 0x0000001E +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO29 0x0000001D +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO28 0x0000001C +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO27 0x0000001B +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO26 0x0000001A +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO25 0x00000019 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO24 0x00000018 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO23 0x00000017 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO22 0x00000016 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO21 0x00000015 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO20 0x00000014 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO19 0x00000013 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO18 0x00000012 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO17 0x00000011 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO16 0x00000010 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO15 0x0000000F +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO14 0x0000000E +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO13 0x0000000D +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO12 0x0000000C +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO11 0x0000000B +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO10 0x0000000A +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO9 0x00000009 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO8 0x00000008 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO7 0x00000007 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO6 0x00000006 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO5 0x00000005 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO4 0x00000004 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO3 0x00000003 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO2 0x00000002 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO1 0x00000001 +#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO0 0x00000000 //***************************************************************************** // @@ -602,12 +602,12 @@ // low. // HIGH The wakeup flag is set when WU_SRC is high or goes // high. -#define AUX_SYSIF_PROGWU2CFG_POL 0x00000080 -#define AUX_SYSIF_PROGWU2CFG_POL_BITN 7 -#define AUX_SYSIF_PROGWU2CFG_POL_M 0x00000080 -#define AUX_SYSIF_PROGWU2CFG_POL_S 7 -#define AUX_SYSIF_PROGWU2CFG_POL_LOW 0x00000080 -#define AUX_SYSIF_PROGWU2CFG_POL_HIGH 0x00000000 +#define AUX_SYSIF_PROGWU2CFG_POL 0x00000080 +#define AUX_SYSIF_PROGWU2CFG_POL_BITN 7 +#define AUX_SYSIF_PROGWU2CFG_POL_M 0x00000080 +#define AUX_SYSIF_PROGWU2CFG_POL_S 7 +#define AUX_SYSIF_PROGWU2CFG_POL_LOW 0x00000080 +#define AUX_SYSIF_PROGWU2CFG_POL_HIGH 0x00000000 // Field: [6] EN // @@ -615,10 +615,10 @@ // // 0: Disable wakeup flag. // 1: Enable wakeup flag. -#define AUX_SYSIF_PROGWU2CFG_EN 0x00000040 -#define AUX_SYSIF_PROGWU2CFG_EN_BITN 6 -#define AUX_SYSIF_PROGWU2CFG_EN_M 0x00000040 -#define AUX_SYSIF_PROGWU2CFG_EN_S 6 +#define AUX_SYSIF_PROGWU2CFG_EN 0x00000040 +#define AUX_SYSIF_PROGWU2CFG_EN_BITN 6 +#define AUX_SYSIF_PROGWU2CFG_EN_M 0x00000040 +#define AUX_SYSIF_PROGWU2CFG_EN_S 6 // Field: [5:0] WU_SRC // @@ -692,72 +692,72 @@ // AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 // AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 // AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_W 6 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_M 0x0000003F -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_S 0 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_NO_EVENT 0x0000003F -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_DONE 0x00000039 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TDC_DONE 0x00000037 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER0_EV 0x00000036 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER1_EV 0x00000035 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_COMPB 0x0000002F -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_COMPA 0x0000002E -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_OBSMUX1 0x0000002D -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_OBSMUX0 0x0000002C -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_EV 0x0000002B -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_ACLK_REF 0x0000002A -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_VDDR_RECHARGE 0x00000029 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_ACTIVE 0x00000028 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_PWR_DWN 0x00000027 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_SCLK_LF 0x00000026 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_RTC_4KHZ 0x00000023 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_RTC_CH2 0x00000021 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MANUAL_EV 0x00000020 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO31 0x0000001F -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO30 0x0000001E -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO29 0x0000001D -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO28 0x0000001C -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO27 0x0000001B -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO26 0x0000001A -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO25 0x00000019 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO24 0x00000018 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO23 0x00000017 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO22 0x00000016 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO21 0x00000015 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO20 0x00000014 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO19 0x00000013 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO18 0x00000012 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO17 0x00000011 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO16 0x00000010 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO15 0x0000000F -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO14 0x0000000E -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO13 0x0000000D -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO12 0x0000000C -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO11 0x0000000B -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO10 0x0000000A -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO9 0x00000009 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO8 0x00000008 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO7 0x00000007 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO6 0x00000006 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO5 0x00000005 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO4 0x00000004 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO3 0x00000003 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO2 0x00000002 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO1 0x00000001 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO0 0x00000000 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_W 6 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_M 0x0000003F +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_S 0 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_NO_EVENT 0x0000003F +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_DONE 0x00000039 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TDC_DONE 0x00000037 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER0_EV 0x00000036 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER1_EV 0x00000035 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_COMPB 0x0000002F +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_COMPA 0x0000002E +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_OBSMUX1 0x0000002D +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_OBSMUX0 0x0000002C +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_EV 0x0000002B +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_ACLK_REF 0x0000002A +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_VDDR_RECHARGE 0x00000029 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_ACTIVE 0x00000028 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_PWR_DWN 0x00000027 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_SCLK_LF 0x00000026 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_RTC_4KHZ 0x00000023 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_RTC_CH2 0x00000021 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MANUAL_EV 0x00000020 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO31 0x0000001F +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO30 0x0000001E +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO29 0x0000001D +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO28 0x0000001C +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO27 0x0000001B +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO26 0x0000001A +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO25 0x00000019 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO24 0x00000018 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO23 0x00000017 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO22 0x00000016 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO21 0x00000015 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO20 0x00000014 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO19 0x00000013 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO18 0x00000012 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO17 0x00000011 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO16 0x00000010 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO15 0x0000000F +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO14 0x0000000E +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO13 0x0000000D +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO12 0x0000000C +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO11 0x0000000B +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO10 0x0000000A +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO9 0x00000009 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO8 0x00000008 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO7 0x00000007 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO6 0x00000006 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO5 0x00000005 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO4 0x00000004 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO3 0x00000003 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO2 0x00000002 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO1 0x00000001 +#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO0 0x00000000 //***************************************************************************** // @@ -775,12 +775,12 @@ // low. // HIGH The wakeup flag is set when WU_SRC is high or goes // high. -#define AUX_SYSIF_PROGWU3CFG_POL 0x00000080 -#define AUX_SYSIF_PROGWU3CFG_POL_BITN 7 -#define AUX_SYSIF_PROGWU3CFG_POL_M 0x00000080 -#define AUX_SYSIF_PROGWU3CFG_POL_S 7 -#define AUX_SYSIF_PROGWU3CFG_POL_LOW 0x00000080 -#define AUX_SYSIF_PROGWU3CFG_POL_HIGH 0x00000000 +#define AUX_SYSIF_PROGWU3CFG_POL 0x00000080 +#define AUX_SYSIF_PROGWU3CFG_POL_BITN 7 +#define AUX_SYSIF_PROGWU3CFG_POL_M 0x00000080 +#define AUX_SYSIF_PROGWU3CFG_POL_S 7 +#define AUX_SYSIF_PROGWU3CFG_POL_LOW 0x00000080 +#define AUX_SYSIF_PROGWU3CFG_POL_HIGH 0x00000000 // Field: [6] EN // @@ -788,10 +788,10 @@ // // 0: Disable wakeup flag. // 1: Enable wakeup flag. -#define AUX_SYSIF_PROGWU3CFG_EN 0x00000040 -#define AUX_SYSIF_PROGWU3CFG_EN_BITN 6 -#define AUX_SYSIF_PROGWU3CFG_EN_M 0x00000040 -#define AUX_SYSIF_PROGWU3CFG_EN_S 6 +#define AUX_SYSIF_PROGWU3CFG_EN 0x00000040 +#define AUX_SYSIF_PROGWU3CFG_EN_BITN 6 +#define AUX_SYSIF_PROGWU3CFG_EN_M 0x00000040 +#define AUX_SYSIF_PROGWU3CFG_EN_S 6 // Field: [5:0] WU_SRC // @@ -865,72 +865,72 @@ // AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 // AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 // AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_W 6 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_M 0x0000003F -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_S 0 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_NO_EVENT 0x0000003F -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_DONE 0x00000039 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TDC_DONE 0x00000037 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER0_EV 0x00000036 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER1_EV 0x00000035 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_COMPB 0x0000002F -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_COMPA 0x0000002E -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_OBSMUX1 0x0000002D -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_OBSMUX0 0x0000002C -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_EV 0x0000002B -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_ACLK_REF 0x0000002A -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_VDDR_RECHARGE 0x00000029 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_ACTIVE 0x00000028 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_PWR_DWN 0x00000027 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_SCLK_LF 0x00000026 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_RTC_4KHZ 0x00000023 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_RTC_CH2 0x00000021 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MANUAL_EV 0x00000020 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO31 0x0000001F -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO30 0x0000001E -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO29 0x0000001D -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO28 0x0000001C -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO27 0x0000001B -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO26 0x0000001A -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO25 0x00000019 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO24 0x00000018 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO23 0x00000017 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO22 0x00000016 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO21 0x00000015 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO20 0x00000014 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO19 0x00000013 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO18 0x00000012 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO17 0x00000011 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO16 0x00000010 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO15 0x0000000F -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO14 0x0000000E -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO13 0x0000000D -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO12 0x0000000C -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO11 0x0000000B -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO10 0x0000000A -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO9 0x00000009 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO8 0x00000008 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO7 0x00000007 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO6 0x00000006 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO5 0x00000005 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO4 0x00000004 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO3 0x00000003 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO2 0x00000002 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO1 0x00000001 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO0 0x00000000 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_W 6 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_M 0x0000003F +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_S 0 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_NO_EVENT 0x0000003F +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_DONE 0x00000039 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TDC_DONE 0x00000037 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER0_EV 0x00000036 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER1_EV 0x00000035 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_COMPB 0x0000002F +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_COMPA 0x0000002E +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_OBSMUX1 0x0000002D +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_OBSMUX0 0x0000002C +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_EV 0x0000002B +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_ACLK_REF 0x0000002A +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_VDDR_RECHARGE 0x00000029 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_ACTIVE 0x00000028 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_PWR_DWN 0x00000027 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_SCLK_LF 0x00000026 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_RTC_4KHZ 0x00000023 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_RTC_CH2 0x00000021 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MANUAL_EV 0x00000020 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO31 0x0000001F +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO30 0x0000001E +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO29 0x0000001D +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO28 0x0000001C +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO27 0x0000001B +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO26 0x0000001A +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO25 0x00000019 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO24 0x00000018 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO23 0x00000017 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO22 0x00000016 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO21 0x00000015 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO20 0x00000014 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO19 0x00000013 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO18 0x00000012 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO17 0x00000011 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO16 0x00000010 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO15 0x0000000F +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO14 0x0000000E +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO13 0x0000000D +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO12 0x0000000C +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO11 0x0000000B +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO10 0x0000000A +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO9 0x00000009 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO8 0x00000008 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO7 0x00000007 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO6 0x00000006 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO5 0x00000005 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO4 0x00000004 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO3 0x00000003 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO2 0x00000002 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO1 0x00000001 +#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO0 0x00000000 //***************************************************************************** // @@ -943,10 +943,10 @@ // // 0: No effect. // 1: Set WUFLAGS.SW_WU3 and trigger AUX wakeup. -#define AUX_SYSIF_SWWUTRIG_SW_WU3 0x00000008 -#define AUX_SYSIF_SWWUTRIG_SW_WU3_BITN 3 -#define AUX_SYSIF_SWWUTRIG_SW_WU3_M 0x00000008 -#define AUX_SYSIF_SWWUTRIG_SW_WU3_S 3 +#define AUX_SYSIF_SWWUTRIG_SW_WU3 0x00000008 +#define AUX_SYSIF_SWWUTRIG_SW_WU3_BITN 3 +#define AUX_SYSIF_SWWUTRIG_SW_WU3_M 0x00000008 +#define AUX_SYSIF_SWWUTRIG_SW_WU3_S 3 // Field: [2] SW_WU2 // @@ -954,10 +954,10 @@ // // 0: No effect. // 1: Set WUFLAGS.SW_WU2 and trigger AUX wakeup. -#define AUX_SYSIF_SWWUTRIG_SW_WU2 0x00000004 -#define AUX_SYSIF_SWWUTRIG_SW_WU2_BITN 2 -#define AUX_SYSIF_SWWUTRIG_SW_WU2_M 0x00000004 -#define AUX_SYSIF_SWWUTRIG_SW_WU2_S 2 +#define AUX_SYSIF_SWWUTRIG_SW_WU2 0x00000004 +#define AUX_SYSIF_SWWUTRIG_SW_WU2_BITN 2 +#define AUX_SYSIF_SWWUTRIG_SW_WU2_M 0x00000004 +#define AUX_SYSIF_SWWUTRIG_SW_WU2_S 2 // Field: [1] SW_WU1 // @@ -965,10 +965,10 @@ // // 0: No effect. // 1: Set WUFLAGS.SW_WU1 and trigger AUX wakeup. -#define AUX_SYSIF_SWWUTRIG_SW_WU1 0x00000002 -#define AUX_SYSIF_SWWUTRIG_SW_WU1_BITN 1 -#define AUX_SYSIF_SWWUTRIG_SW_WU1_M 0x00000002 -#define AUX_SYSIF_SWWUTRIG_SW_WU1_S 1 +#define AUX_SYSIF_SWWUTRIG_SW_WU1 0x00000002 +#define AUX_SYSIF_SWWUTRIG_SW_WU1_BITN 1 +#define AUX_SYSIF_SWWUTRIG_SW_WU1_M 0x00000002 +#define AUX_SYSIF_SWWUTRIG_SW_WU1_S 1 // Field: [0] SW_WU0 // @@ -976,10 +976,10 @@ // // 0: No effect. // 1: Set WUFLAGS.SW_WU0 and trigger AUX wakeup. -#define AUX_SYSIF_SWWUTRIG_SW_WU0 0x00000001 -#define AUX_SYSIF_SWWUTRIG_SW_WU0_BITN 0 -#define AUX_SYSIF_SWWUTRIG_SW_WU0_M 0x00000001 -#define AUX_SYSIF_SWWUTRIG_SW_WU0_S 0 +#define AUX_SYSIF_SWWUTRIG_SW_WU0 0x00000001 +#define AUX_SYSIF_SWWUTRIG_SW_WU0_BITN 0 +#define AUX_SYSIF_SWWUTRIG_SW_WU0_M 0x00000001 +#define AUX_SYSIF_SWWUTRIG_SW_WU0_S 0 //***************************************************************************** // @@ -992,10 +992,10 @@ // // 0: Software wakeup 3 not triggered. // 1: Software wakeup 3 triggered. -#define AUX_SYSIF_WUFLAGS_SW_WU3 0x00000080 -#define AUX_SYSIF_WUFLAGS_SW_WU3_BITN 7 -#define AUX_SYSIF_WUFLAGS_SW_WU3_M 0x00000080 -#define AUX_SYSIF_WUFLAGS_SW_WU3_S 7 +#define AUX_SYSIF_WUFLAGS_SW_WU3 0x00000080 +#define AUX_SYSIF_WUFLAGS_SW_WU3_BITN 7 +#define AUX_SYSIF_WUFLAGS_SW_WU3_M 0x00000080 +#define AUX_SYSIF_WUFLAGS_SW_WU3_S 7 // Field: [6] SW_WU2 // @@ -1003,10 +1003,10 @@ // // 0: Software wakeup 2 not triggered. // 1: Software wakeup 2 triggered. -#define AUX_SYSIF_WUFLAGS_SW_WU2 0x00000040 -#define AUX_SYSIF_WUFLAGS_SW_WU2_BITN 6 -#define AUX_SYSIF_WUFLAGS_SW_WU2_M 0x00000040 -#define AUX_SYSIF_WUFLAGS_SW_WU2_S 6 +#define AUX_SYSIF_WUFLAGS_SW_WU2 0x00000040 +#define AUX_SYSIF_WUFLAGS_SW_WU2_BITN 6 +#define AUX_SYSIF_WUFLAGS_SW_WU2_M 0x00000040 +#define AUX_SYSIF_WUFLAGS_SW_WU2_S 6 // Field: [5] SW_WU1 // @@ -1014,10 +1014,10 @@ // // 0: Software wakeup 1 not triggered. // 1: Software wakeup 1 triggered. -#define AUX_SYSIF_WUFLAGS_SW_WU1 0x00000020 -#define AUX_SYSIF_WUFLAGS_SW_WU1_BITN 5 -#define AUX_SYSIF_WUFLAGS_SW_WU1_M 0x00000020 -#define AUX_SYSIF_WUFLAGS_SW_WU1_S 5 +#define AUX_SYSIF_WUFLAGS_SW_WU1 0x00000020 +#define AUX_SYSIF_WUFLAGS_SW_WU1_BITN 5 +#define AUX_SYSIF_WUFLAGS_SW_WU1_M 0x00000020 +#define AUX_SYSIF_WUFLAGS_SW_WU1_S 5 // Field: [4] SW_WU0 // @@ -1025,10 +1025,10 @@ // // 0: Software wakeup 0 not triggered. // 1: Software wakeup 0 triggered. -#define AUX_SYSIF_WUFLAGS_SW_WU0 0x00000010 -#define AUX_SYSIF_WUFLAGS_SW_WU0_BITN 4 -#define AUX_SYSIF_WUFLAGS_SW_WU0_M 0x00000010 -#define AUX_SYSIF_WUFLAGS_SW_WU0_S 4 +#define AUX_SYSIF_WUFLAGS_SW_WU0 0x00000010 +#define AUX_SYSIF_WUFLAGS_SW_WU0_BITN 4 +#define AUX_SYSIF_WUFLAGS_SW_WU0_M 0x00000010 +#define AUX_SYSIF_WUFLAGS_SW_WU0_S 4 // Field: [3] PROG_WU3 // @@ -1036,10 +1036,10 @@ // // 0: Programmable wakeup 3 not triggered. // 1: Programmable wakeup 3 triggered. -#define AUX_SYSIF_WUFLAGS_PROG_WU3 0x00000008 -#define AUX_SYSIF_WUFLAGS_PROG_WU3_BITN 3 -#define AUX_SYSIF_WUFLAGS_PROG_WU3_M 0x00000008 -#define AUX_SYSIF_WUFLAGS_PROG_WU3_S 3 +#define AUX_SYSIF_WUFLAGS_PROG_WU3 0x00000008 +#define AUX_SYSIF_WUFLAGS_PROG_WU3_BITN 3 +#define AUX_SYSIF_WUFLAGS_PROG_WU3_M 0x00000008 +#define AUX_SYSIF_WUFLAGS_PROG_WU3_S 3 // Field: [2] PROG_WU2 // @@ -1047,10 +1047,10 @@ // // 0: Programmable wakeup 2 not triggered. // 1: Programmable wakeup 2 triggered. -#define AUX_SYSIF_WUFLAGS_PROG_WU2 0x00000004 -#define AUX_SYSIF_WUFLAGS_PROG_WU2_BITN 2 -#define AUX_SYSIF_WUFLAGS_PROG_WU2_M 0x00000004 -#define AUX_SYSIF_WUFLAGS_PROG_WU2_S 2 +#define AUX_SYSIF_WUFLAGS_PROG_WU2 0x00000004 +#define AUX_SYSIF_WUFLAGS_PROG_WU2_BITN 2 +#define AUX_SYSIF_WUFLAGS_PROG_WU2_M 0x00000004 +#define AUX_SYSIF_WUFLAGS_PROG_WU2_S 2 // Field: [1] PROG_WU1 // @@ -1058,10 +1058,10 @@ // // 0: Programmable wakeup 1 not triggered. // 1: Programmable wakeup 1 triggered. -#define AUX_SYSIF_WUFLAGS_PROG_WU1 0x00000002 -#define AUX_SYSIF_WUFLAGS_PROG_WU1_BITN 1 -#define AUX_SYSIF_WUFLAGS_PROG_WU1_M 0x00000002 -#define AUX_SYSIF_WUFLAGS_PROG_WU1_S 1 +#define AUX_SYSIF_WUFLAGS_PROG_WU1 0x00000002 +#define AUX_SYSIF_WUFLAGS_PROG_WU1_BITN 1 +#define AUX_SYSIF_WUFLAGS_PROG_WU1_M 0x00000002 +#define AUX_SYSIF_WUFLAGS_PROG_WU1_S 1 // Field: [0] PROG_WU0 // @@ -1069,10 +1069,10 @@ // // 0: Programmable wakeup 0 not triggered. // 1: Programmable wakeup 0 triggered. -#define AUX_SYSIF_WUFLAGS_PROG_WU0 0x00000001 -#define AUX_SYSIF_WUFLAGS_PROG_WU0_BITN 0 -#define AUX_SYSIF_WUFLAGS_PROG_WU0_M 0x00000001 -#define AUX_SYSIF_WUFLAGS_PROG_WU0_S 0 +#define AUX_SYSIF_WUFLAGS_PROG_WU0 0x00000001 +#define AUX_SYSIF_WUFLAGS_PROG_WU0_BITN 0 +#define AUX_SYSIF_WUFLAGS_PROG_WU0_M 0x00000001 +#define AUX_SYSIF_WUFLAGS_PROG_WU0_S 0 //***************************************************************************** // @@ -1085,10 +1085,10 @@ // // 0: No effect. // 1: Clear WUFLAGS.SW_WU3. Keep high until WUFLAGS.SW_WU3 is 0. -#define AUX_SYSIF_WUFLAGSCLR_SW_WU3 0x00000080 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU3_BITN 7 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU3_M 0x00000080 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU3_S 7 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU3 0x00000080 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU3_BITN 7 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU3_M 0x00000080 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU3_S 7 // Field: [6] SW_WU2 // @@ -1096,10 +1096,10 @@ // // 0: No effect. // 1: Clear WUFLAGS.SW_WU2. Keep high until WUFLAGS.SW_WU2 is 0. -#define AUX_SYSIF_WUFLAGSCLR_SW_WU2 0x00000040 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU2_BITN 6 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU2_M 0x00000040 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU2_S 6 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU2 0x00000040 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU2_BITN 6 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU2_M 0x00000040 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU2_S 6 // Field: [5] SW_WU1 // @@ -1107,10 +1107,10 @@ // // 0: No effect. // 1: Clear WUFLAGS.SW_WU1. Keep high until WUFLAGS.SW_WU1 is 0. -#define AUX_SYSIF_WUFLAGSCLR_SW_WU1 0x00000020 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU1_BITN 5 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU1_M 0x00000020 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU1_S 5 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU1 0x00000020 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU1_BITN 5 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU1_M 0x00000020 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU1_S 5 // Field: [4] SW_WU0 // @@ -1118,10 +1118,10 @@ // // 0: No effect. // 1: Clear WUFLAGS.SW_WU0. Keep high until WUFLAGS.SW_WU0 is 0. -#define AUX_SYSIF_WUFLAGSCLR_SW_WU0 0x00000010 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU0_BITN 4 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU0_M 0x00000010 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU0_S 4 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU0 0x00000010 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU0_BITN 4 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU0_M 0x00000010 +#define AUX_SYSIF_WUFLAGSCLR_SW_WU0_S 4 // Field: [3] PROG_WU3 // @@ -1134,10 +1134,10 @@ // PROGWU3CFG.EN is 1. // The wakeup flag becomes level sensitive if you write PROG_WU3 to 0 when // PROGWU3CFG.EN is 0, then set PROGWU3CFG.EN. -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3 0x00000008 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3_BITN 3 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3_M 0x00000008 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3_S 3 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3 0x00000008 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3_BITN 3 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3_M 0x00000008 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3_S 3 // Field: [2] PROG_WU2 // @@ -1150,10 +1150,10 @@ // PROGWU2CFG.EN is 1. // The wakeup flag becomes level sensitive if you write PROG_WU2 to 0 when // PROGWU2CFG.EN is 0, then set PROGWU2CFG.EN. -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2 0x00000004 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2_BITN 2 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2_M 0x00000004 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2_S 2 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2 0x00000004 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2_BITN 2 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2_M 0x00000004 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2_S 2 // Field: [1] PROG_WU1 // @@ -1166,10 +1166,10 @@ // PROGWU1CFG.EN is 1. // The wakeup flag becomes level sensitive if you write PROG_WU1 to 0 when // PROGWU1CFG.EN is 0, then set PROGWU1CFG.EN. -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1 0x00000002 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1_BITN 1 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1_M 0x00000002 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1_S 1 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1 0x00000002 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1_BITN 1 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1_M 0x00000002 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1_S 1 // Field: [0] PROG_WU0 // @@ -1182,10 +1182,10 @@ // PROGWU0CFG.EN is 1. // The wakeup flag becomes level sensitive if you write PROG_WU0 to 0 when // PROGWU0CFG.EN is 0, then set PROGWU0CFG.EN. -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0 0x00000001 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0_BITN 0 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0_M 0x00000001 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0_S 0 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0 0x00000001 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0_BITN 0 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0_M 0x00000001 +#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0_S 0 //***************************************************************************** // @@ -1198,10 +1198,10 @@ // // 0: Disable AUX wakeup output. // 1: Enable AUX wakeup output. -#define AUX_SYSIF_WUGATE_EN 0x00000001 -#define AUX_SYSIF_WUGATE_EN_BITN 0 -#define AUX_SYSIF_WUGATE_EN_M 0x00000001 -#define AUX_SYSIF_WUGATE_EN_S 0 +#define AUX_SYSIF_WUGATE_EN 0x00000001 +#define AUX_SYSIF_WUGATE_EN_BITN 0 +#define AUX_SYSIF_WUGATE_EN_M 0x00000001 +#define AUX_SYSIF_WUGATE_EN_S 0 //***************************************************************************** // @@ -1224,19 +1224,19 @@ // PROG_WU1 WUFLAGS.PROG_WU1 // PROG_WU0 WUFLAGS.PROG_WU0 // NONE Vector is disabled. -#define AUX_SYSIF_VECCFG0_VEC_EV_W 4 -#define AUX_SYSIF_VECCFG0_VEC_EV_M 0x0000000F -#define AUX_SYSIF_VECCFG0_VEC_EV_S 0 -#define AUX_SYSIF_VECCFG0_VEC_EV_AON_RTC_CH2_DLY 0x00000009 -#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU3 0x00000008 -#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU2 0x00000007 -#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU1 0x00000006 -#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU0 0x00000005 -#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU3 0x00000004 -#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU2 0x00000003 -#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU1 0x00000002 -#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU0 0x00000001 -#define AUX_SYSIF_VECCFG0_VEC_EV_NONE 0x00000000 +#define AUX_SYSIF_VECCFG0_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG0_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG0_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG0_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG0_VEC_EV_NONE 0x00000000 //***************************************************************************** // @@ -1259,19 +1259,19 @@ // PROG_WU1 WUFLAGS.PROG_WU1 // PROG_WU0 WUFLAGS.PROG_WU0 // NONE Vector is disabled. -#define AUX_SYSIF_VECCFG1_VEC_EV_W 4 -#define AUX_SYSIF_VECCFG1_VEC_EV_M 0x0000000F -#define AUX_SYSIF_VECCFG1_VEC_EV_S 0 -#define AUX_SYSIF_VECCFG1_VEC_EV_AON_RTC_CH2_DLY 0x00000009 -#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU3 0x00000008 -#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU2 0x00000007 -#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU1 0x00000006 -#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU0 0x00000005 -#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU3 0x00000004 -#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU2 0x00000003 -#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU1 0x00000002 -#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU0 0x00000001 -#define AUX_SYSIF_VECCFG1_VEC_EV_NONE 0x00000000 +#define AUX_SYSIF_VECCFG1_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG1_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG1_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG1_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG1_VEC_EV_NONE 0x00000000 //***************************************************************************** // @@ -1294,19 +1294,19 @@ // PROG_WU1 WUFLAGS.PROG_WU1 // PROG_WU0 WUFLAGS.PROG_WU0 // NONE Vector is disabled. -#define AUX_SYSIF_VECCFG2_VEC_EV_W 4 -#define AUX_SYSIF_VECCFG2_VEC_EV_M 0x0000000F -#define AUX_SYSIF_VECCFG2_VEC_EV_S 0 -#define AUX_SYSIF_VECCFG2_VEC_EV_AON_RTC_CH2_DLY 0x00000009 -#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU3 0x00000008 -#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU2 0x00000007 -#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU1 0x00000006 -#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU0 0x00000005 -#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU3 0x00000004 -#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU2 0x00000003 -#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU1 0x00000002 -#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU0 0x00000001 -#define AUX_SYSIF_VECCFG2_VEC_EV_NONE 0x00000000 +#define AUX_SYSIF_VECCFG2_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG2_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG2_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG2_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG2_VEC_EV_NONE 0x00000000 //***************************************************************************** // @@ -1329,19 +1329,19 @@ // PROG_WU1 WUFLAGS.PROG_WU1 // PROG_WU0 WUFLAGS.PROG_WU0 // NONE Vector is disabled. -#define AUX_SYSIF_VECCFG3_VEC_EV_W 4 -#define AUX_SYSIF_VECCFG3_VEC_EV_M 0x0000000F -#define AUX_SYSIF_VECCFG3_VEC_EV_S 0 -#define AUX_SYSIF_VECCFG3_VEC_EV_AON_RTC_CH2_DLY 0x00000009 -#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU3 0x00000008 -#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU2 0x00000007 -#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU1 0x00000006 -#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU0 0x00000005 -#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU3 0x00000004 -#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU2 0x00000003 -#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU1 0x00000002 -#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU0 0x00000001 -#define AUX_SYSIF_VECCFG3_VEC_EV_NONE 0x00000000 +#define AUX_SYSIF_VECCFG3_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG3_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG3_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG3_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG3_VEC_EV_NONE 0x00000000 //***************************************************************************** // @@ -1364,19 +1364,19 @@ // PROG_WU1 WUFLAGS.PROG_WU1 // PROG_WU0 WUFLAGS.PROG_WU0 // NONE Vector is disabled. -#define AUX_SYSIF_VECCFG4_VEC_EV_W 4 -#define AUX_SYSIF_VECCFG4_VEC_EV_M 0x0000000F -#define AUX_SYSIF_VECCFG4_VEC_EV_S 0 -#define AUX_SYSIF_VECCFG4_VEC_EV_AON_RTC_CH2_DLY 0x00000009 -#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU3 0x00000008 -#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU2 0x00000007 -#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU1 0x00000006 -#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU0 0x00000005 -#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU3 0x00000004 -#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU2 0x00000003 -#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU1 0x00000002 -#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU0 0x00000001 -#define AUX_SYSIF_VECCFG4_VEC_EV_NONE 0x00000000 +#define AUX_SYSIF_VECCFG4_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG4_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG4_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG4_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG4_VEC_EV_NONE 0x00000000 //***************************************************************************** // @@ -1399,19 +1399,19 @@ // PROG_WU1 WUFLAGS.PROG_WU1 // PROG_WU0 WUFLAGS.PROG_WU0 // NONE Vector is disabled. -#define AUX_SYSIF_VECCFG5_VEC_EV_W 4 -#define AUX_SYSIF_VECCFG5_VEC_EV_M 0x0000000F -#define AUX_SYSIF_VECCFG5_VEC_EV_S 0 -#define AUX_SYSIF_VECCFG5_VEC_EV_AON_RTC_CH2_DLY 0x00000009 -#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU3 0x00000008 -#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU2 0x00000007 -#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU1 0x00000006 -#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU0 0x00000005 -#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU3 0x00000004 -#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU2 0x00000003 -#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU1 0x00000002 -#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU0 0x00000001 -#define AUX_SYSIF_VECCFG5_VEC_EV_NONE 0x00000000 +#define AUX_SYSIF_VECCFG5_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG5_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG5_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG5_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG5_VEC_EV_NONE 0x00000000 //***************************************************************************** // @@ -1434,19 +1434,19 @@ // PROG_WU1 WUFLAGS.PROG_WU1 // PROG_WU0 WUFLAGS.PROG_WU0 // NONE Vector is disabled. -#define AUX_SYSIF_VECCFG6_VEC_EV_W 4 -#define AUX_SYSIF_VECCFG6_VEC_EV_M 0x0000000F -#define AUX_SYSIF_VECCFG6_VEC_EV_S 0 -#define AUX_SYSIF_VECCFG6_VEC_EV_AON_RTC_CH2_DLY 0x00000009 -#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU3 0x00000008 -#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU2 0x00000007 -#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU1 0x00000006 -#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU0 0x00000005 -#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU3 0x00000004 -#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU2 0x00000003 -#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU1 0x00000002 -#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU0 0x00000001 -#define AUX_SYSIF_VECCFG6_VEC_EV_NONE 0x00000000 +#define AUX_SYSIF_VECCFG6_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG6_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG6_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG6_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG6_VEC_EV_NONE 0x00000000 //***************************************************************************** // @@ -1469,19 +1469,19 @@ // PROG_WU1 WUFLAGS.PROG_WU1 // PROG_WU0 WUFLAGS.PROG_WU0 // NONE Vector is disabled. -#define AUX_SYSIF_VECCFG7_VEC_EV_W 4 -#define AUX_SYSIF_VECCFG7_VEC_EV_M 0x0000000F -#define AUX_SYSIF_VECCFG7_VEC_EV_S 0 -#define AUX_SYSIF_VECCFG7_VEC_EV_AON_RTC_CH2_DLY 0x00000009 -#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU3 0x00000008 -#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU2 0x00000007 -#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU1 0x00000006 -#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU0 0x00000005 -#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU3 0x00000004 -#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU2 0x00000003 -#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU1 0x00000002 -#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU0 0x00000001 -#define AUX_SYSIF_VECCFG7_VEC_EV_NONE 0x00000000 +#define AUX_SYSIF_VECCFG7_VEC_EV_W 4 +#define AUX_SYSIF_VECCFG7_VEC_EV_M 0x0000000F +#define AUX_SYSIF_VECCFG7_VEC_EV_S 0 +#define AUX_SYSIF_VECCFG7_VEC_EV_AON_RTC_CH2_DLY 0x00000009 +#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU3 0x00000008 +#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU2 0x00000007 +#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU1 0x00000006 +#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU0 0x00000005 +#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU3 0x00000004 +#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU2 0x00000003 +#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU1 0x00000002 +#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU0 0x00000001 +#define AUX_SYSIF_VECCFG7_VEC_EV_NONE 0x00000000 //***************************************************************************** // @@ -1494,12 +1494,12 @@ // ENUMs: // BUS_RATE AUX bus rate // SCE_RATE SCE rate -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE 0x00000004 -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_BITN 2 -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_M 0x00000004 -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_S 2 -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_BUS_RATE 0x00000004 -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_SCE_RATE 0x00000000 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE 0x00000004 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_BITN 2 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_M 0x00000004 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_S 2 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_BUS_RATE 0x00000004 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_SCE_RATE 0x00000000 // Field: [1] AUX_COMPB_SYNC_RATE // @@ -1507,12 +1507,12 @@ // ENUMs: // BUS_RATE AUX bus rate // SCE_RATE SCE rate -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE 0x00000002 -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_BITN 1 -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_M 0x00000002 -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_S 1 -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_BUS_RATE 0x00000002 -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_SCE_RATE 0x00000000 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE 0x00000002 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_BITN 1 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_M 0x00000002 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_S 1 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_BUS_RATE 0x00000002 +#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_SCE_RATE 0x00000000 // Field: [0] AUX_TIMER2_SYNC_RATE // @@ -1525,12 +1525,12 @@ // ENUMs: // BUS_RATE AUX bus rate // SCE_RATE SCE rate -#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE 0x00000001 -#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_BITN 0 -#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_M 0x00000001 -#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_S 0 -#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_BUS_RATE 0x00000001 -#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_SCE_RATE 0x00000000 +#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE 0x00000001 +#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_BITN 0 +#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_M 0x00000001 +#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_S 0 +#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_BUS_RATE 0x00000001 +#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_SCE_RATE 0x00000000 //***************************************************************************** // @@ -1543,12 +1543,12 @@ // ENUMs: // BUS_RATE AUX bus rate // SCE_RATE SCE rate -#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE 0x00000008 -#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_BITN 3 -#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_M 0x00000008 -#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_S 3 -#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_BUS_RATE 0x00000008 -#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_SCE_RATE 0x00000000 +#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE 0x00000008 +#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_BITN 3 +#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_M 0x00000008 +#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_S 3 +#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_BUS_RATE 0x00000008 +#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_SCE_RATE 0x00000000 // Field: [2] TIMER01_OP_RATE // @@ -1556,12 +1556,12 @@ // ENUMs: // BUS_RATE AUX bus rate // SCE_RATE SCE rate -#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE 0x00000004 -#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_BITN 2 -#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_M 0x00000004 -#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_S 2 -#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_BUS_RATE 0x00000004 -#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_SCE_RATE 0x00000000 +#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE 0x00000004 +#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_BITN 2 +#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_M 0x00000004 +#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_S 2 +#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_BUS_RATE 0x00000004 +#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_SCE_RATE 0x00000000 // Field: [1] SPIM_OP_RATE // @@ -1569,12 +1569,12 @@ // ENUMs: // BUS_RATE AUX bus rate // SCE_RATE SCE rate -#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE 0x00000002 -#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_BITN 1 -#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_M 0x00000002 -#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_S 1 -#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_BUS_RATE 0x00000002 -#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_SCE_RATE 0x00000000 +#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE 0x00000002 +#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_BITN 1 +#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_M 0x00000002 +#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_S 1 +#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_BUS_RATE 0x00000002 +#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_SCE_RATE 0x00000000 // Field: [0] MAC_OP_RATE // @@ -1582,12 +1582,12 @@ // ENUMs: // BUS_RATE AUX bus rate // SCE_RATE SCE rate -#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE 0x00000001 -#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_BITN 0 -#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_M 0x00000001 -#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_S 0 -#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_BUS_RATE 0x00000001 -#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_SCE_RATE 0x00000000 +#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE 0x00000001 +#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_BITN 0 +#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_M 0x00000001 +#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_S 0 +#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_BUS_RATE 0x00000001 +#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_SCE_RATE 0x00000000 //***************************************************************************** // @@ -1600,10 +1600,10 @@ // // 0: ADC clock is disabled. // 1: ADC clock is enabled. -#define AUX_SYSIF_ADCCLKCTL_ACK 0x00000002 -#define AUX_SYSIF_ADCCLKCTL_ACK_BITN 1 -#define AUX_SYSIF_ADCCLKCTL_ACK_M 0x00000002 -#define AUX_SYSIF_ADCCLKCTL_ACK_S 1 +#define AUX_SYSIF_ADCCLKCTL_ACK 0x00000002 +#define AUX_SYSIF_ADCCLKCTL_ACK_BITN 1 +#define AUX_SYSIF_ADCCLKCTL_ACK_M 0x00000002 +#define AUX_SYSIF_ADCCLKCTL_ACK_S 1 // Field: [0] REQ // @@ -1613,10 +1613,10 @@ // 1: Enable ADC clock. // // Only modify REQ when equal to ACK. -#define AUX_SYSIF_ADCCLKCTL_REQ 0x00000001 -#define AUX_SYSIF_ADCCLKCTL_REQ_BITN 0 -#define AUX_SYSIF_ADCCLKCTL_REQ_M 0x00000001 -#define AUX_SYSIF_ADCCLKCTL_REQ_S 0 +#define AUX_SYSIF_ADCCLKCTL_REQ 0x00000001 +#define AUX_SYSIF_ADCCLKCTL_REQ_BITN 0 +#define AUX_SYSIF_ADCCLKCTL_REQ_M 0x00000001 +#define AUX_SYSIF_ADCCLKCTL_REQ_S 0 //***************************************************************************** // @@ -1629,10 +1629,10 @@ // // 0: TDC counter clock is disabled. // 1: TDC counter clock is enabled. -#define AUX_SYSIF_TDCCLKCTL_ACK 0x00000002 -#define AUX_SYSIF_TDCCLKCTL_ACK_BITN 1 -#define AUX_SYSIF_TDCCLKCTL_ACK_M 0x00000002 -#define AUX_SYSIF_TDCCLKCTL_ACK_S 1 +#define AUX_SYSIF_TDCCLKCTL_ACK 0x00000002 +#define AUX_SYSIF_TDCCLKCTL_ACK_BITN 1 +#define AUX_SYSIF_TDCCLKCTL_ACK_M 0x00000002 +#define AUX_SYSIF_TDCCLKCTL_ACK_S 1 // Field: [0] REQ // @@ -1642,10 +1642,10 @@ // 1: Enable TDC counter clock. // // Only modify REQ when equal to ACK. -#define AUX_SYSIF_TDCCLKCTL_REQ 0x00000001 -#define AUX_SYSIF_TDCCLKCTL_REQ_BITN 0 -#define AUX_SYSIF_TDCCLKCTL_REQ_M 0x00000001 -#define AUX_SYSIF_TDCCLKCTL_REQ_S 0 +#define AUX_SYSIF_TDCCLKCTL_REQ 0x00000001 +#define AUX_SYSIF_TDCCLKCTL_REQ_BITN 0 +#define AUX_SYSIF_TDCCLKCTL_REQ_M 0x00000001 +#define AUX_SYSIF_TDCCLKCTL_REQ_S 0 //***************************************************************************** // @@ -1658,10 +1658,10 @@ // // 0: TDC reference clock is disabled. // 1: TDC reference clock is enabled. -#define AUX_SYSIF_TDCREFCLKCTL_ACK 0x00000002 -#define AUX_SYSIF_TDCREFCLKCTL_ACK_BITN 1 -#define AUX_SYSIF_TDCREFCLKCTL_ACK_M 0x00000002 -#define AUX_SYSIF_TDCREFCLKCTL_ACK_S 1 +#define AUX_SYSIF_TDCREFCLKCTL_ACK 0x00000002 +#define AUX_SYSIF_TDCREFCLKCTL_ACK_BITN 1 +#define AUX_SYSIF_TDCREFCLKCTL_ACK_M 0x00000002 +#define AUX_SYSIF_TDCREFCLKCTL_ACK_S 1 // Field: [0] REQ // @@ -1671,10 +1671,10 @@ // 1: Enable TDC reference clock. // // Only modify REQ when equal to ACK. -#define AUX_SYSIF_TDCREFCLKCTL_REQ 0x00000001 -#define AUX_SYSIF_TDCREFCLKCTL_REQ_BITN 0 -#define AUX_SYSIF_TDCREFCLKCTL_REQ_M 0x00000001 -#define AUX_SYSIF_TDCREFCLKCTL_REQ_S 0 +#define AUX_SYSIF_TDCREFCLKCTL_REQ 0x00000001 +#define AUX_SYSIF_TDCREFCLKCTL_REQ_BITN 0 +#define AUX_SYSIF_TDCREFCLKCTL_REQ_M 0x00000001 +#define AUX_SYSIF_TDCREFCLKCTL_REQ_S 0 //***************************************************************************** // @@ -1696,13 +1696,13 @@ // SCLK_MF SCLK_MF // SCLK_LF SCLK_LF // NONE no clock -#define AUX_SYSIF_TIMER2CLKCTL_SRC_W 3 -#define AUX_SYSIF_TIMER2CLKCTL_SRC_M 0x00000007 -#define AUX_SYSIF_TIMER2CLKCTL_SRC_S 0 -#define AUX_SYSIF_TIMER2CLKCTL_SRC_SCLK_HFDIV2 0x00000004 -#define AUX_SYSIF_TIMER2CLKCTL_SRC_SCLK_MF 0x00000002 -#define AUX_SYSIF_TIMER2CLKCTL_SRC_SCLK_LF 0x00000001 -#define AUX_SYSIF_TIMER2CLKCTL_SRC_NONE 0x00000000 +#define AUX_SYSIF_TIMER2CLKCTL_SRC_W 3 +#define AUX_SYSIF_TIMER2CLKCTL_SRC_M 0x00000007 +#define AUX_SYSIF_TIMER2CLKCTL_SRC_S 0 +#define AUX_SYSIF_TIMER2CLKCTL_SRC_SCLK_HFDIV2 0x00000004 +#define AUX_SYSIF_TIMER2CLKCTL_SRC_SCLK_MF 0x00000002 +#define AUX_SYSIF_TIMER2CLKCTL_SRC_SCLK_LF 0x00000001 +#define AUX_SYSIF_TIMER2CLKCTL_SRC_NONE 0x00000000 //***************************************************************************** // @@ -1717,13 +1717,13 @@ // SCLK_MF SCLK_MF // SCLK_LF SCLK_LF // NONE No clock -#define AUX_SYSIF_TIMER2CLKSTAT_STAT_W 3 -#define AUX_SYSIF_TIMER2CLKSTAT_STAT_M 0x00000007 -#define AUX_SYSIF_TIMER2CLKSTAT_STAT_S 0 -#define AUX_SYSIF_TIMER2CLKSTAT_STAT_SCLK_HFDIV2 0x00000004 -#define AUX_SYSIF_TIMER2CLKSTAT_STAT_SCLK_MF 0x00000002 -#define AUX_SYSIF_TIMER2CLKSTAT_STAT_SCLK_LF 0x00000001 -#define AUX_SYSIF_TIMER2CLKSTAT_STAT_NONE 0x00000000 +#define AUX_SYSIF_TIMER2CLKSTAT_STAT_W 3 +#define AUX_SYSIF_TIMER2CLKSTAT_STAT_M 0x00000007 +#define AUX_SYSIF_TIMER2CLKSTAT_STAT_S 0 +#define AUX_SYSIF_TIMER2CLKSTAT_STAT_SCLK_HFDIV2 0x00000004 +#define AUX_SYSIF_TIMER2CLKSTAT_STAT_SCLK_MF 0x00000002 +#define AUX_SYSIF_TIMER2CLKSTAT_STAT_SCLK_LF 0x00000001 +#define AUX_SYSIF_TIMER2CLKSTAT_STAT_NONE 0x00000000 //***************************************************************************** // @@ -1738,10 +1738,10 @@ // 1: TIMER2CLKCTL.SRC equals TIMER2CLKSTAT.STAT. // // RDY connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY. -#define AUX_SYSIF_TIMER2CLKSWITCH_RDY 0x00000001 -#define AUX_SYSIF_TIMER2CLKSWITCH_RDY_BITN 0 -#define AUX_SYSIF_TIMER2CLKSWITCH_RDY_M 0x00000001 -#define AUX_SYSIF_TIMER2CLKSWITCH_RDY_S 0 +#define AUX_SYSIF_TIMER2CLKSWITCH_RDY 0x00000001 +#define AUX_SYSIF_TIMER2CLKSWITCH_RDY_BITN 0 +#define AUX_SYSIF_TIMER2CLKSWITCH_RDY_M 0x00000001 +#define AUX_SYSIF_TIMER2CLKSWITCH_RDY_S 0 //***************************************************************************** // @@ -1754,10 +1754,10 @@ // // 0: AUX_TIMER2 does not halt when the system CPU halts in debug mode. // 1: Halt AUX_TIMER2 when the system CPU halts in debug mode. -#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN 0x00000001 -#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN_BITN 0 -#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN_M 0x00000001 -#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN_S 0 +#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN 0x00000001 +#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN_BITN 0 +#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN_M 0x00000001 +#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN_S 0 //***************************************************************************** // @@ -1777,10 +1777,10 @@ // // 0: MCU domain did not enter or exit active state since you wrote 0 to STAT. // 1: MCU domain entered or exited active state since you wrote 0 to STAT. -#define AUX_SYSIF_CLKSHIFTDET_STAT 0x00000001 -#define AUX_SYSIF_CLKSHIFTDET_STAT_BITN 0 -#define AUX_SYSIF_CLKSHIFTDET_STAT_M 0x00000001 -#define AUX_SYSIF_CLKSHIFTDET_STAT_S 0 +#define AUX_SYSIF_CLKSHIFTDET_STAT 0x00000001 +#define AUX_SYSIF_CLKSHIFTDET_STAT_BITN 0 +#define AUX_SYSIF_CLKSHIFTDET_STAT_M 0x00000001 +#define AUX_SYSIF_CLKSHIFTDET_STAT_S 0 //***************************************************************************** // @@ -1805,10 +1805,10 @@ // Follow this sequence when OPMODEREQ.REQ is PDA or PDLP: // - Set TRIG. // - Clear TRIG. -#define AUX_SYSIF_RECHARGETRIG_TRIG 0x00000001 -#define AUX_SYSIF_RECHARGETRIG_TRIG_BITN 0 -#define AUX_SYSIF_RECHARGETRIG_TRIG_M 0x00000001 -#define AUX_SYSIF_RECHARGETRIG_TRIG_S 0 +#define AUX_SYSIF_RECHARGETRIG_TRIG 0x00000001 +#define AUX_SYSIF_RECHARGETRIG_TRIG_BITN 0 +#define AUX_SYSIF_RECHARGETRIG_TRIG_M 0x00000001 +#define AUX_SYSIF_RECHARGETRIG_TRIG_S 0 //***************************************************************************** // @@ -1821,10 +1821,10 @@ // // 0: No recharge of VDDR has occurred since EN was set. // 1: Recharge of VDDR has occurred since EN was set. -#define AUX_SYSIF_RECHARGEDET_STAT 0x00000002 -#define AUX_SYSIF_RECHARGEDET_STAT_BITN 1 -#define AUX_SYSIF_RECHARGEDET_STAT_M 0x00000002 -#define AUX_SYSIF_RECHARGEDET_STAT_S 1 +#define AUX_SYSIF_RECHARGEDET_STAT 0x00000002 +#define AUX_SYSIF_RECHARGEDET_STAT_BITN 1 +#define AUX_SYSIF_RECHARGEDET_STAT_M 0x00000002 +#define AUX_SYSIF_RECHARGEDET_STAT_S 1 // Field: [0] EN // @@ -1832,10 +1832,10 @@ // // 0: Disable recharge detection. STAT becomes zero. // 1: Enable recharge detection. -#define AUX_SYSIF_RECHARGEDET_EN 0x00000001 -#define AUX_SYSIF_RECHARGEDET_EN_BITN 0 -#define AUX_SYSIF_RECHARGEDET_EN_M 0x00000001 -#define AUX_SYSIF_RECHARGEDET_EN_S 0 +#define AUX_SYSIF_RECHARGEDET_EN 0x00000001 +#define AUX_SYSIF_RECHARGEDET_EN_BITN 0 +#define AUX_SYSIF_RECHARGEDET_EN_M 0x00000001 +#define AUX_SYSIF_RECHARGEDET_EN_S 0 //***************************************************************************** // @@ -1845,9 +1845,9 @@ // Field: [15:0] INC15_0 // // New value for bits 15:0 in AON_RTC:SUBSECINC. -#define AUX_SYSIF_RTCSUBSECINC0_INC15_0_W 16 -#define AUX_SYSIF_RTCSUBSECINC0_INC15_0_M 0x0000FFFF -#define AUX_SYSIF_RTCSUBSECINC0_INC15_0_S 0 +#define AUX_SYSIF_RTCSUBSECINC0_INC15_0_W 16 +#define AUX_SYSIF_RTCSUBSECINC0_INC15_0_M 0x0000FFFF +#define AUX_SYSIF_RTCSUBSECINC0_INC15_0_S 0 //***************************************************************************** // @@ -1857,9 +1857,9 @@ // Field: [7:0] INC23_16 // // New value for bits 23:16 in AON_RTC:SUBSECINC. -#define AUX_SYSIF_RTCSUBSECINC1_INC23_16_W 8 -#define AUX_SYSIF_RTCSUBSECINC1_INC23_16_M 0x000000FF -#define AUX_SYSIF_RTCSUBSECINC1_INC23_16_S 0 +#define AUX_SYSIF_RTCSUBSECINC1_INC23_16_W 8 +#define AUX_SYSIF_RTCSUBSECINC1_INC23_16_M 0x000000FF +#define AUX_SYSIF_RTCSUBSECINC1_INC23_16_S 0 //***************************************************************************** // @@ -1872,10 +1872,10 @@ // // 0: AON_RTC has not acknowledged UPD_REQ. // 1: AON_RTC has acknowledged UPD_REQ. -#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK 0x00000002 -#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_BITN 1 -#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_M 0x00000002 -#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_S 1 +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK 0x00000002 +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_BITN 1 +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_M 0x00000002 +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_S 1 // Field: [0] UPD_REQ // @@ -1886,10 +1886,10 @@ // // Only change UPD_REQ when it equals UPD_ACK. Clear UPD_REQ after UPD_ACK is // 1. -#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ 0x00000001 -#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ_BITN 0 -#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ_M 0x00000001 -#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ_S 0 +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ 0x00000001 +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ_BITN 0 +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ_M 0x00000001 +#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ_S 0 //***************************************************************************** // @@ -1903,9 +1903,9 @@ // Follow this procedure to get the correct value: // - Do two dummy reads of SEC. // - Then read SEC until two consecutive reads are equal. -#define AUX_SYSIF_RTCSEC_SEC_W 16 -#define AUX_SYSIF_RTCSEC_SEC_M 0x0000FFFF -#define AUX_SYSIF_RTCSEC_SEC_S 0 +#define AUX_SYSIF_RTCSEC_SEC_W 16 +#define AUX_SYSIF_RTCSEC_SEC_M 0x0000FFFF +#define AUX_SYSIF_RTCSEC_SEC_S 0 //***************************************************************************** // @@ -1919,9 +1919,9 @@ // Follow this procedure to get the correct value: // - Do two dummy reads SUBSEC. // - Then read SUBSEC until two consecutive reads are equal. -#define AUX_SYSIF_RTCSUBSEC_SUBSEC_W 16 -#define AUX_SYSIF_RTCSUBSEC_SUBSEC_M 0x0000FFFF -#define AUX_SYSIF_RTCSUBSEC_SUBSEC_S 0 +#define AUX_SYSIF_RTCSUBSEC_SUBSEC_W 16 +#define AUX_SYSIF_RTCSUBSEC_SUBSEC_M 0x0000FFFF +#define AUX_SYSIF_RTCSUBSEC_SUBSEC_S 0 //***************************************************************************** // @@ -1937,10 +1937,10 @@ // // Keep RTC_CH2_EV_CLR high until AUX_EVCTL:EVSTAT2.AON_RTC_CH2 and // AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY are 0. -#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR 0x00000001 -#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR_BITN 0 -#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR_M 0x00000001 -#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR_S 0 +#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR 0x00000001 +#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR_BITN 0 +#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR_M 0x00000001 +#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR_S 0 //***************************************************************************** // @@ -1954,9 +1954,9 @@ // Follow this procedure to get the correct value: // - Do two dummy reads of INT. // - Then read INT until two consecutive reads are equal. -#define AUX_SYSIF_BATMONBAT_INT_W 3 -#define AUX_SYSIF_BATMONBAT_INT_M 0x00000700 -#define AUX_SYSIF_BATMONBAT_INT_S 8 +#define AUX_SYSIF_BATMONBAT_INT_W 3 +#define AUX_SYSIF_BATMONBAT_INT_M 0x00000700 +#define AUX_SYSIF_BATMONBAT_INT_S 8 // Field: [7:0] FRAC // @@ -1965,9 +1965,9 @@ // Follow this procedure to get the correct value: // - Do two dummy reads of FRAC. // - Then read FRAC until two consecutive reads are equal. -#define AUX_SYSIF_BATMONBAT_FRAC_W 8 -#define AUX_SYSIF_BATMONBAT_FRAC_M 0x000000FF -#define AUX_SYSIF_BATMONBAT_FRAC_S 0 +#define AUX_SYSIF_BATMONBAT_FRAC_W 8 +#define AUX_SYSIF_BATMONBAT_FRAC_M 0x000000FF +#define AUX_SYSIF_BATMONBAT_FRAC_S 0 //***************************************************************************** // @@ -1981,9 +1981,9 @@ // Follow this procedure to get the correct value: // - Do two dummy reads of SIGN. // - Then read SIGN until two consecutive reads are equal. -#define AUX_SYSIF_BATMONTEMP_SIGN_W 5 -#define AUX_SYSIF_BATMONTEMP_SIGN_M 0x0000F800 -#define AUX_SYSIF_BATMONTEMP_SIGN_S 11 +#define AUX_SYSIF_BATMONTEMP_SIGN_W 5 +#define AUX_SYSIF_BATMONTEMP_SIGN_M 0x0000F800 +#define AUX_SYSIF_BATMONTEMP_SIGN_S 11 // Field: [10:2] INT // @@ -1992,9 +1992,9 @@ // Follow this procedure to get the correct value: // - Do two dummy reads of INT. // - Then read INT until two consecutive reads are equal. -#define AUX_SYSIF_BATMONTEMP_INT_W 9 -#define AUX_SYSIF_BATMONTEMP_INT_M 0x000007FC -#define AUX_SYSIF_BATMONTEMP_INT_S 2 +#define AUX_SYSIF_BATMONTEMP_INT_W 9 +#define AUX_SYSIF_BATMONTEMP_INT_M 0x000007FC +#define AUX_SYSIF_BATMONTEMP_INT_S 2 // Field: [1:0] FRAC // @@ -2003,9 +2003,9 @@ // Follow this procedure to get the correct value: // - Do two dummy reads of FRAC. // - Then read FRAC until two consecutive reads are equal. -#define AUX_SYSIF_BATMONTEMP_FRAC_W 2 -#define AUX_SYSIF_BATMONTEMP_FRAC_M 0x00000003 -#define AUX_SYSIF_BATMONTEMP_FRAC_S 0 +#define AUX_SYSIF_BATMONTEMP_FRAC_W 2 +#define AUX_SYSIF_BATMONTEMP_FRAC_M 0x00000003 +#define AUX_SYSIF_BATMONTEMP_FRAC_S 0 //***************************************************************************** // @@ -2018,10 +2018,10 @@ // // 0: AUX_EVCTL:PROGDLY.VALUE decrements as normal. // 1: Halt AUX_EVCTL:PROGDLY.VALUE decrementation. -#define AUX_SYSIF_TIMERHALT_PROGDLY 0x00000008 -#define AUX_SYSIF_TIMERHALT_PROGDLY_BITN 3 -#define AUX_SYSIF_TIMERHALT_PROGDLY_M 0x00000008 -#define AUX_SYSIF_TIMERHALT_PROGDLY_S 3 +#define AUX_SYSIF_TIMERHALT_PROGDLY 0x00000008 +#define AUX_SYSIF_TIMERHALT_PROGDLY_BITN 3 +#define AUX_SYSIF_TIMERHALT_PROGDLY_M 0x00000008 +#define AUX_SYSIF_TIMERHALT_PROGDLY_S 3 // Field: [2] AUX_TIMER2 // @@ -2029,10 +2029,10 @@ // // 0: AUX_TIMER2 operates as normal. // 1: Halt AUX_TIMER2 operation. -#define AUX_SYSIF_TIMERHALT_AUX_TIMER2 0x00000004 -#define AUX_SYSIF_TIMERHALT_AUX_TIMER2_BITN 2 -#define AUX_SYSIF_TIMERHALT_AUX_TIMER2_M 0x00000004 -#define AUX_SYSIF_TIMERHALT_AUX_TIMER2_S 2 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER2 0x00000004 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER2_BITN 2 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER2_M 0x00000004 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER2_S 2 // Field: [1] AUX_TIMER1 // @@ -2040,10 +2040,10 @@ // // 0: AUX_TIMER01 Timer 1 operates as normal. // 1: Halt AUX_TIMER01 Timer 1 operation. -#define AUX_SYSIF_TIMERHALT_AUX_TIMER1 0x00000002 -#define AUX_SYSIF_TIMERHALT_AUX_TIMER1_BITN 1 -#define AUX_SYSIF_TIMERHALT_AUX_TIMER1_M 0x00000002 -#define AUX_SYSIF_TIMERHALT_AUX_TIMER1_S 1 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER1 0x00000002 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER1_BITN 1 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER1_M 0x00000002 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER1_S 1 // Field: [0] AUX_TIMER0 // @@ -2051,10 +2051,10 @@ // // 0: AUX_TIMER01 Timer 0 operates as normal. // 1: Halt AUX_TIMER01 Timer 0 operation. -#define AUX_SYSIF_TIMERHALT_AUX_TIMER0 0x00000001 -#define AUX_SYSIF_TIMERHALT_AUX_TIMER0_BITN 0 -#define AUX_SYSIF_TIMERHALT_AUX_TIMER0_M 0x00000001 -#define AUX_SYSIF_TIMERHALT_AUX_TIMER0_S 0 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER0 0x00000001 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER0_BITN 0 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER0_M 0x00000001 +#define AUX_SYSIF_TIMERHALT_AUX_TIMER0_S 0 //***************************************************************************** // @@ -2067,10 +2067,10 @@ // // 0: No unfinished bus transactions. // 1: A bus transaction is ongoing. -#define AUX_SYSIF_TIMER2BRIDGE_BUSY 0x00000001 -#define AUX_SYSIF_TIMER2BRIDGE_BUSY_BITN 0 -#define AUX_SYSIF_TIMER2BRIDGE_BUSY_M 0x00000001 -#define AUX_SYSIF_TIMER2BRIDGE_BUSY_S 0 +#define AUX_SYSIF_TIMER2BRIDGE_BUSY 0x00000001 +#define AUX_SYSIF_TIMER2BRIDGE_BUSY_BITN 0 +#define AUX_SYSIF_TIMER2BRIDGE_BUSY_M 0x00000001 +#define AUX_SYSIF_TIMER2BRIDGE_BUSY_S 0 //***************************************************************************** // @@ -2080,9 +2080,8 @@ // Field: [2:0] STAT // // Software status bits that can be read by the power profiler. -#define AUX_SYSIF_SWPWRPROF_STAT_W 3 -#define AUX_SYSIF_SWPWRPROF_STAT_M 0x00000007 -#define AUX_SYSIF_SWPWRPROF_STAT_S 0 - +#define AUX_SYSIF_SWPWRPROF_STAT_W 3 +#define AUX_SYSIF_SWPWRPROF_STAT_M 0x00000007 +#define AUX_SYSIF_SWPWRPROF_STAT_S 0 #endif // __AUX_SYSIF__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_tdc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_tdc.h index eee6d69..ae41300 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_tdc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_tdc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_tdc_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_tdc_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_TDC_H__ #define __HW_AUX_TDC_H__ @@ -44,34 +44,34 @@ // //***************************************************************************** // Control -#define AUX_TDC_O_CTL 0x00000000 +#define AUX_TDC_O_CTL 0x00000000 // Status -#define AUX_TDC_O_STAT 0x00000004 +#define AUX_TDC_O_STAT 0x00000004 // Result -#define AUX_TDC_O_RESULT 0x00000008 +#define AUX_TDC_O_RESULT 0x00000008 // Saturation Configuration -#define AUX_TDC_O_SATCFG 0x0000000C +#define AUX_TDC_O_SATCFG 0x0000000C // Trigger Source -#define AUX_TDC_O_TRIGSRC 0x00000010 +#define AUX_TDC_O_TRIGSRC 0x00000010 // Trigger Counter -#define AUX_TDC_O_TRIGCNT 0x00000014 +#define AUX_TDC_O_TRIGCNT 0x00000014 // Trigger Counter Load -#define AUX_TDC_O_TRIGCNTLOAD 0x00000018 +#define AUX_TDC_O_TRIGCNTLOAD 0x00000018 // Trigger Counter Configuration -#define AUX_TDC_O_TRIGCNTCFG 0x0000001C +#define AUX_TDC_O_TRIGCNTCFG 0x0000001C // Prescaler Control -#define AUX_TDC_O_PRECTL 0x00000020 +#define AUX_TDC_O_PRECTL 0x00000020 // Prescaler Counter -#define AUX_TDC_O_PRECNTR 0x00000024 +#define AUX_TDC_O_PRECNTR 0x00000024 //***************************************************************************** // @@ -107,13 +107,13 @@ // This is not needed as // prerequisite for a measurement. Reliable clear // is only guaranteed from IDLE state. -#define AUX_TDC_CTL_CMD_W 2 -#define AUX_TDC_CTL_CMD_M 0x00000003 -#define AUX_TDC_CTL_CMD_S 0 -#define AUX_TDC_CTL_CMD_ABORT 0x00000003 -#define AUX_TDC_CTL_CMD_RUN 0x00000002 -#define AUX_TDC_CTL_CMD_RUN_SYNC_START 0x00000001 -#define AUX_TDC_CTL_CMD_CLR_RESULT 0x00000000 +#define AUX_TDC_CTL_CMD_W 2 +#define AUX_TDC_CTL_CMD_M 0x00000003 +#define AUX_TDC_CTL_CMD_S 0 +#define AUX_TDC_CTL_CMD_ABORT 0x00000003 +#define AUX_TDC_CTL_CMD_RUN 0x00000002 +#define AUX_TDC_CTL_CMD_RUN_SYNC_START 0x00000001 +#define AUX_TDC_CTL_CMD_CLR_RESULT 0x00000000 //***************************************************************************** // @@ -129,10 +129,10 @@ // // This field is cleared when a new measurement is started or when CLR_RESULT // is written to CTL.CMD. -#define AUX_TDC_STAT_SAT 0x00000080 -#define AUX_TDC_STAT_SAT_BITN 7 -#define AUX_TDC_STAT_SAT_M 0x00000080 -#define AUX_TDC_STAT_SAT_S 7 +#define AUX_TDC_STAT_SAT 0x00000080 +#define AUX_TDC_STAT_SAT_BITN 7 +#define AUX_TDC_STAT_SAT_M 0x00000080 +#define AUX_TDC_STAT_SAT_S 7 // Field: [6] DONE // @@ -143,10 +143,10 @@ // // This field clears when a new TDC measurement starts or when you write // CLR_RESULT to CTL.CMD. -#define AUX_TDC_STAT_DONE 0x00000040 -#define AUX_TDC_STAT_DONE_BITN 6 -#define AUX_TDC_STAT_DONE_M 0x00000040 -#define AUX_TDC_STAT_DONE_S 6 +#define AUX_TDC_STAT_DONE 0x00000040 +#define AUX_TDC_STAT_DONE_BITN 6 +#define AUX_TDC_STAT_DONE_M 0x00000040 +#define AUX_TDC_STAT_DONE_S 6 // Field: [5:0] STATE // @@ -192,20 +192,20 @@ // looks for the start condition. The state // machine waits for the fast-counter to // increment. -#define AUX_TDC_STAT_STATE_W 6 -#define AUX_TDC_STAT_STATE_M 0x0000003F -#define AUX_TDC_STAT_STATE_S 0 -#define AUX_TDC_STAT_STATE_FORCE_STOP 0x0000002E -#define AUX_TDC_STAT_STATE_START_FALL 0x0000001E -#define AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE 0x00000016 -#define AUX_TDC_STAT_STATE_POR 0x0000000F -#define AUX_TDC_STAT_STATE_GET_RESULT 0x0000000E -#define AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN 0x0000000C -#define AUX_TDC_STAT_STATE_WAIT_STOP 0x00000008 -#define AUX_TDC_STAT_STATE_CLR_CNT 0x00000007 -#define AUX_TDC_STAT_STATE_IDLE 0x00000006 -#define AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN 0x00000004 -#define AUX_TDC_STAT_STATE_WAIT_START 0x00000000 +#define AUX_TDC_STAT_STATE_W 6 +#define AUX_TDC_STAT_STATE_M 0x0000003F +#define AUX_TDC_STAT_STATE_S 0 +#define AUX_TDC_STAT_STATE_FORCE_STOP 0x0000002E +#define AUX_TDC_STAT_STATE_START_FALL 0x0000001E +#define AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE 0x00000016 +#define AUX_TDC_STAT_STATE_POR 0x0000000F +#define AUX_TDC_STAT_STATE_GET_RESULT 0x0000000E +#define AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN 0x0000000C +#define AUX_TDC_STAT_STATE_WAIT_STOP 0x00000008 +#define AUX_TDC_STAT_STATE_CLR_CNT 0x00000007 +#define AUX_TDC_STAT_STATE_IDLE 0x00000006 +#define AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN 0x00000004 +#define AUX_TDC_STAT_STATE_WAIT_START 0x00000000 //***************************************************************************** // @@ -224,9 +224,9 @@ // takes a non-zero time to stop the measurement. Hence, the maximum value of // this field becomes slightly higher than 2^24 if you configure SATCFG.LIMIT // to R24. -#define AUX_TDC_RESULT_VALUE_W 25 -#define AUX_TDC_RESULT_VALUE_M 0x01FFFFFF -#define AUX_TDC_RESULT_VALUE_S 0 +#define AUX_TDC_RESULT_VALUE_W 25 +#define AUX_TDC_RESULT_VALUE_M 0x01FFFFFF +#define AUX_TDC_RESULT_VALUE_S 0 //***************************************************************************** // @@ -267,22 +267,22 @@ // when RESULT.VALUE[13] is set. // R12 Result bit 12: TDC conversion saturates and stops // when RESULT.VALUE[12] is set. -#define AUX_TDC_SATCFG_LIMIT_W 4 -#define AUX_TDC_SATCFG_LIMIT_M 0x0000000F -#define AUX_TDC_SATCFG_LIMIT_S 0 -#define AUX_TDC_SATCFG_LIMIT_R24 0x0000000F -#define AUX_TDC_SATCFG_LIMIT_R23 0x0000000E -#define AUX_TDC_SATCFG_LIMIT_R22 0x0000000D -#define AUX_TDC_SATCFG_LIMIT_R21 0x0000000C -#define AUX_TDC_SATCFG_LIMIT_R20 0x0000000B -#define AUX_TDC_SATCFG_LIMIT_R19 0x0000000A -#define AUX_TDC_SATCFG_LIMIT_R18 0x00000009 -#define AUX_TDC_SATCFG_LIMIT_R17 0x00000008 -#define AUX_TDC_SATCFG_LIMIT_R16 0x00000007 -#define AUX_TDC_SATCFG_LIMIT_R15 0x00000006 -#define AUX_TDC_SATCFG_LIMIT_R14 0x00000005 -#define AUX_TDC_SATCFG_LIMIT_R13 0x00000004 -#define AUX_TDC_SATCFG_LIMIT_R12 0x00000003 +#define AUX_TDC_SATCFG_LIMIT_W 4 +#define AUX_TDC_SATCFG_LIMIT_M 0x0000000F +#define AUX_TDC_SATCFG_LIMIT_S 0 +#define AUX_TDC_SATCFG_LIMIT_R24 0x0000000F +#define AUX_TDC_SATCFG_LIMIT_R23 0x0000000E +#define AUX_TDC_SATCFG_LIMIT_R22 0x0000000D +#define AUX_TDC_SATCFG_LIMIT_R21 0x0000000C +#define AUX_TDC_SATCFG_LIMIT_R20 0x0000000B +#define AUX_TDC_SATCFG_LIMIT_R19 0x0000000A +#define AUX_TDC_SATCFG_LIMIT_R18 0x00000009 +#define AUX_TDC_SATCFG_LIMIT_R17 0x00000008 +#define AUX_TDC_SATCFG_LIMIT_R16 0x00000007 +#define AUX_TDC_SATCFG_LIMIT_R15 0x00000006 +#define AUX_TDC_SATCFG_LIMIT_R14 0x00000005 +#define AUX_TDC_SATCFG_LIMIT_R13 0x00000004 +#define AUX_TDC_SATCFG_LIMIT_R12 0x00000003 //***************************************************************************** // @@ -297,12 +297,12 @@ // ENUMs: // LOW TDC conversion stops when low level is detected. // HIGH TDC conversion stops when high level is detected. -#define AUX_TDC_TRIGSRC_STOP_POL 0x00004000 -#define AUX_TDC_TRIGSRC_STOP_POL_BITN 14 -#define AUX_TDC_TRIGSRC_STOP_POL_M 0x00004000 -#define AUX_TDC_TRIGSRC_STOP_POL_S 14 -#define AUX_TDC_TRIGSRC_STOP_POL_LOW 0x00004000 -#define AUX_TDC_TRIGSRC_STOP_POL_HIGH 0x00000000 +#define AUX_TDC_TRIGSRC_STOP_POL 0x00004000 +#define AUX_TDC_TRIGSRC_STOP_POL_BITN 14 +#define AUX_TDC_TRIGSRC_STOP_POL_M 0x00004000 +#define AUX_TDC_TRIGSRC_STOP_POL_S 14 +#define AUX_TDC_TRIGSRC_STOP_POL_LOW 0x00004000 +#define AUX_TDC_TRIGSRC_STOP_POL_HIGH 0x00000000 // Field: [13:8] STOP_SRC // @@ -375,73 +375,73 @@ // AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 // AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 // AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_TDC_TRIGSRC_STOP_SRC_W 6 -#define AUX_TDC_TRIGSRC_STOP_SRC_M 0x00003F00 -#define AUX_TDC_TRIGSRC_STOP_SRC_S 8 -#define AUX_TDC_TRIGSRC_STOP_SRC_NO_EVENT 0x00003F00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_PRE 0x00003E00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00003C00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00003B00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_IRQ 0x00003A00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_DONE 0x00003900 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ISRC_RESET_N 0x00003800 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_DONE 0x00003700 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER0_EV 0x00003600 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER1_EV 0x00003500 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_PULSE 0x00003400 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV3 0x00003300 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV2 0x00003200 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV1 0x00003100 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV0 0x00003000 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB 0x00002F00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA 0x00002E00 -#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX1 0x00002D00 -#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX0 0x00002C00 -#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV 0x00002B00 -#define AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF 0x00002A00 -#define AUX_TDC_TRIGSRC_STOP_SRC_VDDR_RECHARGE 0x00002900 -#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_ACTIVE 0x00002800 -#define AUX_TDC_TRIGSRC_STOP_SRC_PWR_DWN 0x00002700 -#define AUX_TDC_TRIGSRC_STOP_SRC_SCLK_LF 0x00002600 -#define AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_TEMP_UPD 0x00002500 -#define AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_BAT_UPD 0x00002400 -#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_4KHZ 0x00002300 -#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2_DLY 0x00002200 -#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2 0x00002100 -#define AUX_TDC_TRIGSRC_STOP_SRC_MANUAL_EV 0x00002000 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO31 0x00001F00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO30 0x00001E00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO29 0x00001D00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO28 0x00001C00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO27 0x00001B00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO26 0x00001A00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO25 0x00001900 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO24 0x00001800 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO23 0x00001700 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO22 0x00001600 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO21 0x00001500 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO20 0x00001400 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO19 0x00001300 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO18 0x00001200 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO17 0x00001100 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO16 0x00001000 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15 0x00000F00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14 0x00000E00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13 0x00000D00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12 0x00000C00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11 0x00000B00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10 0x00000A00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9 0x00000900 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8 0x00000800 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7 0x00000700 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6 0x00000600 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5 0x00000500 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4 0x00000400 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3 0x00000300 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2 0x00000200 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1 0x00000100 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0 0x00000000 +#define AUX_TDC_TRIGSRC_STOP_SRC_W 6 +#define AUX_TDC_TRIGSRC_STOP_SRC_M 0x00003F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_S 8 +#define AUX_TDC_TRIGSRC_STOP_SRC_NO_EVENT 0x00003F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_PRE 0x00003E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00003C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00003B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_IRQ 0x00003A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_DONE 0x00003900 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ISRC_RESET_N 0x00003800 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_DONE 0x00003700 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER0_EV 0x00003600 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER1_EV 0x00003500 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_PULSE 0x00003400 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV3 0x00003300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV2 0x00003200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV1 0x00003100 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV0 0x00003000 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB 0x00002F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA 0x00002E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX1 0x00002D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX0 0x00002C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV 0x00002B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF 0x00002A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_VDDR_RECHARGE 0x00002900 +#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_ACTIVE 0x00002800 +#define AUX_TDC_TRIGSRC_STOP_SRC_PWR_DWN 0x00002700 +#define AUX_TDC_TRIGSRC_STOP_SRC_SCLK_LF 0x00002600 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_TEMP_UPD 0x00002500 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_BAT_UPD 0x00002400 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_4KHZ 0x00002300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2_DLY 0x00002200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2 0x00002100 +#define AUX_TDC_TRIGSRC_STOP_SRC_MANUAL_EV 0x00002000 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO31 0x00001F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO30 0x00001E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO29 0x00001D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO28 0x00001C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO27 0x00001B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO26 0x00001A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO25 0x00001900 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO24 0x00001800 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO23 0x00001700 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO22 0x00001600 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO21 0x00001500 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO20 0x00001400 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO19 0x00001300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO18 0x00001200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO17 0x00001100 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO16 0x00001000 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15 0x00000F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14 0x00000E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13 0x00000D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12 0x00000C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11 0x00000B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10 0x00000A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9 0x00000900 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8 0x00000800 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7 0x00000700 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6 0x00000600 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5 0x00000500 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4 0x00000400 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3 0x00000300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2 0x00000200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1 0x00000100 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0 0x00000000 // Field: [6] START_POL // @@ -451,12 +451,12 @@ // ENUMs: // LOW TDC conversion starts when low level is detected. // HIGH TDC conversion starts when high level is detected. -#define AUX_TDC_TRIGSRC_START_POL 0x00000040 -#define AUX_TDC_TRIGSRC_START_POL_BITN 6 -#define AUX_TDC_TRIGSRC_START_POL_M 0x00000040 -#define AUX_TDC_TRIGSRC_START_POL_S 6 -#define AUX_TDC_TRIGSRC_START_POL_LOW 0x00000040 -#define AUX_TDC_TRIGSRC_START_POL_HIGH 0x00000000 +#define AUX_TDC_TRIGSRC_START_POL 0x00000040 +#define AUX_TDC_TRIGSRC_START_POL_BITN 6 +#define AUX_TDC_TRIGSRC_START_POL_M 0x00000040 +#define AUX_TDC_TRIGSRC_START_POL_S 6 +#define AUX_TDC_TRIGSRC_START_POL_LOW 0x00000040 +#define AUX_TDC_TRIGSRC_START_POL_HIGH 0x00000000 // Field: [5:0] START_SRC // @@ -529,73 +529,73 @@ // AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 // AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 // AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_TDC_TRIGSRC_START_SRC_W 6 -#define AUX_TDC_TRIGSRC_START_SRC_M 0x0000003F -#define AUX_TDC_TRIGSRC_START_SRC_S 0 -#define AUX_TDC_TRIGSRC_START_SRC_NO_EVENT 0x0000003F -#define AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_PRE 0x0000003E -#define AUX_TDC_TRIGSRC_START_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D -#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C -#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B -#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_IRQ 0x0000003A -#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_DONE 0x00000039 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_ISRC_RESET_N 0x00000038 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_DONE 0x00000037 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER0_EV 0x00000036 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER1_EV 0x00000035 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_PULSE 0x00000034 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV3 0x00000033 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV2 0x00000032 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV1 0x00000031 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV0 0x00000030 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB 0x0000002F -#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA 0x0000002E -#define AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX1 0x0000002D -#define AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX0 0x0000002C -#define AUX_TDC_TRIGSRC_START_SRC_MCU_EV 0x0000002B -#define AUX_TDC_TRIGSRC_START_SRC_ACLK_REF 0x0000002A -#define AUX_TDC_TRIGSRC_START_SRC_VDDR_RECHARGE 0x00000029 -#define AUX_TDC_TRIGSRC_START_SRC_MCU_ACTIVE 0x00000028 -#define AUX_TDC_TRIGSRC_START_SRC_PWR_DWN 0x00000027 -#define AUX_TDC_TRIGSRC_START_SRC_SCLK_LF 0x00000026 -#define AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_TEMP_UPD 0x00000025 -#define AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_BAT_UPD 0x00000024 -#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_4KHZ 0x00000023 -#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2_DLY 0x00000022 -#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2 0x00000021 -#define AUX_TDC_TRIGSRC_START_SRC_MANUAL_EV 0x00000020 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO31 0x0000001F -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO30 0x0000001E -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO29 0x0000001D -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO28 0x0000001C -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO27 0x0000001B -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO26 0x0000001A -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO25 0x00000019 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO24 0x00000018 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO23 0x00000017 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO22 0x00000016 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO21 0x00000015 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO20 0x00000014 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO19 0x00000013 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO18 0x00000012 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO17 0x00000011 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO16 0x00000010 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO15 0x0000000F -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO14 0x0000000E -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO13 0x0000000D -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO12 0x0000000C -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO11 0x0000000B -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO10 0x0000000A -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO9 0x00000009 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO8 0x00000008 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO7 0x00000007 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO6 0x00000006 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO5 0x00000005 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO4 0x00000004 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO3 0x00000003 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO2 0x00000002 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO1 0x00000001 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO0 0x00000000 +#define AUX_TDC_TRIGSRC_START_SRC_W 6 +#define AUX_TDC_TRIGSRC_START_SRC_M 0x0000003F +#define AUX_TDC_TRIGSRC_START_SRC_S 0 +#define AUX_TDC_TRIGSRC_START_SRC_NO_EVENT 0x0000003F +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_PRE 0x0000003E +#define AUX_TDC_TRIGSRC_START_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_IRQ 0x0000003A +#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_DONE 0x00000039 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_ISRC_RESET_N 0x00000038 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_DONE 0x00000037 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER0_EV 0x00000036 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER1_EV 0x00000035 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_PULSE 0x00000034 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV3 0x00000033 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV2 0x00000032 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV1 0x00000031 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV0 0x00000030 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB 0x0000002F +#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA 0x0000002E +#define AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX1 0x0000002D +#define AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX0 0x0000002C +#define AUX_TDC_TRIGSRC_START_SRC_MCU_EV 0x0000002B +#define AUX_TDC_TRIGSRC_START_SRC_ACLK_REF 0x0000002A +#define AUX_TDC_TRIGSRC_START_SRC_VDDR_RECHARGE 0x00000029 +#define AUX_TDC_TRIGSRC_START_SRC_MCU_ACTIVE 0x00000028 +#define AUX_TDC_TRIGSRC_START_SRC_PWR_DWN 0x00000027 +#define AUX_TDC_TRIGSRC_START_SRC_SCLK_LF 0x00000026 +#define AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_4KHZ 0x00000023 +#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2_DLY 0x00000022 +#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2 0x00000021 +#define AUX_TDC_TRIGSRC_START_SRC_MANUAL_EV 0x00000020 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO31 0x0000001F +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO30 0x0000001E +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO29 0x0000001D +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO28 0x0000001C +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO27 0x0000001B +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO26 0x0000001A +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO25 0x00000019 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO24 0x00000018 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO23 0x00000017 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO22 0x00000016 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO21 0x00000015 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO20 0x00000014 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO19 0x00000013 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO18 0x00000012 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO17 0x00000011 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO16 0x00000010 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO15 0x0000000F +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO14 0x0000000E +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO13 0x0000000D +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO12 0x0000000C +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO11 0x0000000B +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO10 0x0000000A +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO9 0x00000009 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO8 0x00000008 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO7 0x00000007 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO6 0x00000006 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO5 0x00000005 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO4 0x00000004 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO3 0x00000003 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO2 0x00000002 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO1 0x00000001 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO0 0x00000000 //***************************************************************************** // @@ -615,9 +615,9 @@ // // When AUX_TDC:TRIGCNTCFG.EN is 1, TRIGCNTLOAD.CNT is loaded into CNT at the // start of the measurement. -#define AUX_TDC_TRIGCNT_CNT_W 16 -#define AUX_TDC_TRIGCNT_CNT_M 0x0000FFFF -#define AUX_TDC_TRIGCNT_CNT_S 0 +#define AUX_TDC_TRIGCNT_CNT_W 16 +#define AUX_TDC_TRIGCNT_CNT_M 0x0000FFFF +#define AUX_TDC_TRIGCNT_CNT_S 0 //***************************************************************************** // @@ -646,9 +646,9 @@ // // When AUX_TDC:TRIGCNTCFG.EN is 1, CNT is loaded into TRIGCNT.CNT at the start // of the measurement. -#define AUX_TDC_TRIGCNTLOAD_CNT_W 16 -#define AUX_TDC_TRIGCNTLOAD_CNT_M 0x0000FFFF -#define AUX_TDC_TRIGCNTLOAD_CNT_S 0 +#define AUX_TDC_TRIGCNTLOAD_CNT_W 16 +#define AUX_TDC_TRIGCNTLOAD_CNT_M 0x0000FFFF +#define AUX_TDC_TRIGCNTLOAD_CNT_S 0 //***************************************************************************** // @@ -663,10 +663,10 @@ // 1: Enable stop-counter. // // Change only while STAT.STATE is IDLE. -#define AUX_TDC_TRIGCNTCFG_EN 0x00000001 -#define AUX_TDC_TRIGCNTCFG_EN_BITN 0 -#define AUX_TDC_TRIGCNTCFG_EN_M 0x00000001 -#define AUX_TDC_TRIGCNTCFG_EN_S 0 +#define AUX_TDC_TRIGCNTCFG_EN 0x00000001 +#define AUX_TDC_TRIGCNTCFG_EN_BITN 0 +#define AUX_TDC_TRIGCNTCFG_EN_M 0x00000001 +#define AUX_TDC_TRIGCNTCFG_EN_S 0 //***************************************************************************** // @@ -681,10 +681,10 @@ // 1: Release reset of prescaler. // // AUX_TDC_PRE event becomes 0 when you reset the prescaler. -#define AUX_TDC_PRECTL_RESET_N 0x00000080 -#define AUX_TDC_PRECTL_RESET_N_BITN 7 -#define AUX_TDC_PRECTL_RESET_N_M 0x00000080 -#define AUX_TDC_PRECTL_RESET_N_S 7 +#define AUX_TDC_PRECTL_RESET_N 0x00000080 +#define AUX_TDC_PRECTL_RESET_N_BITN 7 +#define AUX_TDC_PRECTL_RESET_N_M 0x00000080 +#define AUX_TDC_PRECTL_RESET_N_S 7 // Field: [6] RATIO // @@ -704,12 +704,12 @@ // rising edge for every 16 rising edges of the // input. AUX_TDC_PRE event toggles on every 8th // rising edge of the input. -#define AUX_TDC_PRECTL_RATIO 0x00000040 -#define AUX_TDC_PRECTL_RATIO_BITN 6 -#define AUX_TDC_PRECTL_RATIO_M 0x00000040 -#define AUX_TDC_PRECTL_RATIO_S 6 -#define AUX_TDC_PRECTL_RATIO_DIV64 0x00000040 -#define AUX_TDC_PRECTL_RATIO_DIV16 0x00000000 +#define AUX_TDC_PRECTL_RATIO 0x00000040 +#define AUX_TDC_PRECTL_RATIO_BITN 6 +#define AUX_TDC_PRECTL_RATIO_M 0x00000040 +#define AUX_TDC_PRECTL_RATIO_S 6 +#define AUX_TDC_PRECTL_RATIO_DIV64 0x00000040 +#define AUX_TDC_PRECTL_RATIO_DIV16 0x00000000 // Field: [5:0] SRC // @@ -783,72 +783,72 @@ // AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 // AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 // AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_TDC_PRECTL_SRC_W 6 -#define AUX_TDC_PRECTL_SRC_M 0x0000003F -#define AUX_TDC_PRECTL_SRC_S 0 -#define AUX_TDC_PRECTL_SRC_NO_EVENT 0x0000003F -#define AUX_TDC_PRECTL_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D -#define AUX_TDC_PRECTL_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C -#define AUX_TDC_PRECTL_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B -#define AUX_TDC_PRECTL_SRC_AUX_ADC_IRQ 0x0000003A -#define AUX_TDC_PRECTL_SRC_AUX_ADC_DONE 0x00000039 -#define AUX_TDC_PRECTL_SRC_AUX_ISRC_RESET_N 0x00000038 -#define AUX_TDC_PRECTL_SRC_AUX_TDC_DONE 0x00000037 -#define AUX_TDC_PRECTL_SRC_AUX_TIMER0_EV 0x00000036 -#define AUX_TDC_PRECTL_SRC_AUX_TIMER1_EV 0x00000035 -#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_PULSE 0x00000034 -#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV3 0x00000033 -#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV2 0x00000032 -#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV1 0x00000031 -#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV0 0x00000030 -#define AUX_TDC_PRECTL_SRC_AUX_COMPB 0x0000002F -#define AUX_TDC_PRECTL_SRC_AUX_COMPA 0x0000002E -#define AUX_TDC_PRECTL_SRC_MCU_OBSMUX1 0x0000002D -#define AUX_TDC_PRECTL_SRC_MCU_OBSMUX0 0x0000002C -#define AUX_TDC_PRECTL_SRC_MCU_EV 0x0000002B -#define AUX_TDC_PRECTL_SRC_ACLK_REF 0x0000002A -#define AUX_TDC_PRECTL_SRC_VDDR_RECHARGE 0x00000029 -#define AUX_TDC_PRECTL_SRC_MCU_ACTIVE 0x00000028 -#define AUX_TDC_PRECTL_SRC_PWR_DWN 0x00000027 -#define AUX_TDC_PRECTL_SRC_SCLK_LF 0x00000026 -#define AUX_TDC_PRECTL_SRC_AON_BATMON_TEMP_UPD 0x00000025 -#define AUX_TDC_PRECTL_SRC_AON_BATMON_BAT_UPD 0x00000024 -#define AUX_TDC_PRECTL_SRC_AON_RTC_4KHZ 0x00000023 -#define AUX_TDC_PRECTL_SRC_AON_RTC_CH2_DLY 0x00000022 -#define AUX_TDC_PRECTL_SRC_AON_RTC_CH2 0x00000021 -#define AUX_TDC_PRECTL_SRC_MANUAL_EV 0x00000020 -#define AUX_TDC_PRECTL_SRC_AUXIO31 0x0000001F -#define AUX_TDC_PRECTL_SRC_AUXIO30 0x0000001E -#define AUX_TDC_PRECTL_SRC_AUXIO29 0x0000001D -#define AUX_TDC_PRECTL_SRC_AUXIO28 0x0000001C -#define AUX_TDC_PRECTL_SRC_AUXIO27 0x0000001B -#define AUX_TDC_PRECTL_SRC_AUXIO26 0x0000001A -#define AUX_TDC_PRECTL_SRC_AUXIO25 0x00000019 -#define AUX_TDC_PRECTL_SRC_AUXIO24 0x00000018 -#define AUX_TDC_PRECTL_SRC_AUXIO23 0x00000017 -#define AUX_TDC_PRECTL_SRC_AUXIO22 0x00000016 -#define AUX_TDC_PRECTL_SRC_AUXIO21 0x00000015 -#define AUX_TDC_PRECTL_SRC_AUXIO20 0x00000014 -#define AUX_TDC_PRECTL_SRC_AUXIO19 0x00000013 -#define AUX_TDC_PRECTL_SRC_AUXIO18 0x00000012 -#define AUX_TDC_PRECTL_SRC_AUXIO17 0x00000011 -#define AUX_TDC_PRECTL_SRC_AUXIO16 0x00000010 -#define AUX_TDC_PRECTL_SRC_AUXIO15 0x0000000F -#define AUX_TDC_PRECTL_SRC_AUXIO14 0x0000000E -#define AUX_TDC_PRECTL_SRC_AUXIO13 0x0000000D -#define AUX_TDC_PRECTL_SRC_AUXIO12 0x0000000C -#define AUX_TDC_PRECTL_SRC_AUXIO11 0x0000000B -#define AUX_TDC_PRECTL_SRC_AUXIO10 0x0000000A -#define AUX_TDC_PRECTL_SRC_AUXIO9 0x00000009 -#define AUX_TDC_PRECTL_SRC_AUXIO8 0x00000008 -#define AUX_TDC_PRECTL_SRC_AUXIO7 0x00000007 -#define AUX_TDC_PRECTL_SRC_AUXIO6 0x00000006 -#define AUX_TDC_PRECTL_SRC_AUXIO5 0x00000005 -#define AUX_TDC_PRECTL_SRC_AUXIO4 0x00000004 -#define AUX_TDC_PRECTL_SRC_AUXIO3 0x00000003 -#define AUX_TDC_PRECTL_SRC_AUXIO2 0x00000002 -#define AUX_TDC_PRECTL_SRC_AUXIO1 0x00000001 -#define AUX_TDC_PRECTL_SRC_AUXIO0 0x00000000 +#define AUX_TDC_PRECTL_SRC_W 6 +#define AUX_TDC_PRECTL_SRC_M 0x0000003F +#define AUX_TDC_PRECTL_SRC_S 0 +#define AUX_TDC_PRECTL_SRC_NO_EVENT 0x0000003F +#define AUX_TDC_PRECTL_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D +#define AUX_TDC_PRECTL_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C +#define AUX_TDC_PRECTL_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B +#define AUX_TDC_PRECTL_SRC_AUX_ADC_IRQ 0x0000003A +#define AUX_TDC_PRECTL_SRC_AUX_ADC_DONE 0x00000039 +#define AUX_TDC_PRECTL_SRC_AUX_ISRC_RESET_N 0x00000038 +#define AUX_TDC_PRECTL_SRC_AUX_TDC_DONE 0x00000037 +#define AUX_TDC_PRECTL_SRC_AUX_TIMER0_EV 0x00000036 +#define AUX_TDC_PRECTL_SRC_AUX_TIMER1_EV 0x00000035 +#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_PULSE 0x00000034 +#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV3 0x00000033 +#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV2 0x00000032 +#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV1 0x00000031 +#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV0 0x00000030 +#define AUX_TDC_PRECTL_SRC_AUX_COMPB 0x0000002F +#define AUX_TDC_PRECTL_SRC_AUX_COMPA 0x0000002E +#define AUX_TDC_PRECTL_SRC_MCU_OBSMUX1 0x0000002D +#define AUX_TDC_PRECTL_SRC_MCU_OBSMUX0 0x0000002C +#define AUX_TDC_PRECTL_SRC_MCU_EV 0x0000002B +#define AUX_TDC_PRECTL_SRC_ACLK_REF 0x0000002A +#define AUX_TDC_PRECTL_SRC_VDDR_RECHARGE 0x00000029 +#define AUX_TDC_PRECTL_SRC_MCU_ACTIVE 0x00000028 +#define AUX_TDC_PRECTL_SRC_PWR_DWN 0x00000027 +#define AUX_TDC_PRECTL_SRC_SCLK_LF 0x00000026 +#define AUX_TDC_PRECTL_SRC_AON_BATMON_TEMP_UPD 0x00000025 +#define AUX_TDC_PRECTL_SRC_AON_BATMON_BAT_UPD 0x00000024 +#define AUX_TDC_PRECTL_SRC_AON_RTC_4KHZ 0x00000023 +#define AUX_TDC_PRECTL_SRC_AON_RTC_CH2_DLY 0x00000022 +#define AUX_TDC_PRECTL_SRC_AON_RTC_CH2 0x00000021 +#define AUX_TDC_PRECTL_SRC_MANUAL_EV 0x00000020 +#define AUX_TDC_PRECTL_SRC_AUXIO31 0x0000001F +#define AUX_TDC_PRECTL_SRC_AUXIO30 0x0000001E +#define AUX_TDC_PRECTL_SRC_AUXIO29 0x0000001D +#define AUX_TDC_PRECTL_SRC_AUXIO28 0x0000001C +#define AUX_TDC_PRECTL_SRC_AUXIO27 0x0000001B +#define AUX_TDC_PRECTL_SRC_AUXIO26 0x0000001A +#define AUX_TDC_PRECTL_SRC_AUXIO25 0x00000019 +#define AUX_TDC_PRECTL_SRC_AUXIO24 0x00000018 +#define AUX_TDC_PRECTL_SRC_AUXIO23 0x00000017 +#define AUX_TDC_PRECTL_SRC_AUXIO22 0x00000016 +#define AUX_TDC_PRECTL_SRC_AUXIO21 0x00000015 +#define AUX_TDC_PRECTL_SRC_AUXIO20 0x00000014 +#define AUX_TDC_PRECTL_SRC_AUXIO19 0x00000013 +#define AUX_TDC_PRECTL_SRC_AUXIO18 0x00000012 +#define AUX_TDC_PRECTL_SRC_AUXIO17 0x00000011 +#define AUX_TDC_PRECTL_SRC_AUXIO16 0x00000010 +#define AUX_TDC_PRECTL_SRC_AUXIO15 0x0000000F +#define AUX_TDC_PRECTL_SRC_AUXIO14 0x0000000E +#define AUX_TDC_PRECTL_SRC_AUXIO13 0x0000000D +#define AUX_TDC_PRECTL_SRC_AUXIO12 0x0000000C +#define AUX_TDC_PRECTL_SRC_AUXIO11 0x0000000B +#define AUX_TDC_PRECTL_SRC_AUXIO10 0x0000000A +#define AUX_TDC_PRECTL_SRC_AUXIO9 0x00000009 +#define AUX_TDC_PRECTL_SRC_AUXIO8 0x00000008 +#define AUX_TDC_PRECTL_SRC_AUXIO7 0x00000007 +#define AUX_TDC_PRECTL_SRC_AUXIO6 0x00000006 +#define AUX_TDC_PRECTL_SRC_AUXIO5 0x00000005 +#define AUX_TDC_PRECTL_SRC_AUXIO4 0x00000004 +#define AUX_TDC_PRECTL_SRC_AUXIO3 0x00000003 +#define AUX_TDC_PRECTL_SRC_AUXIO2 0x00000002 +#define AUX_TDC_PRECTL_SRC_AUXIO1 0x00000001 +#define AUX_TDC_PRECTL_SRC_AUXIO0 0x00000000 //***************************************************************************** // @@ -871,9 +871,8 @@ // - The prescaler counter is reset to 2 by PRECTL.RESET_N. // - The captured value is 2 when the number of rising edges on prescaler input // is less than 3. Otherwise, captured value equals number of event pulses - 1. -#define AUX_TDC_PRECNTR_CNT_W 16 -#define AUX_TDC_PRECNTR_CNT_M 0x0000FFFF -#define AUX_TDC_PRECNTR_CNT_S 0 - +#define AUX_TDC_PRECNTR_CNT_W 16 +#define AUX_TDC_PRECNTR_CNT_M 0x0000FFFF +#define AUX_TDC_PRECNTR_CNT_S 0 #endif // __AUX_TDC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer01.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer01.h index 6c6a2fa..6d9efc1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer01.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer01.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_timer01_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_timer01_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_TIMER01_H__ #define __HW_AUX_TIMER01_H__ @@ -44,28 +44,28 @@ // //***************************************************************************** // Timer 0 Configuration -#define AUX_TIMER01_O_T0CFG 0x00000000 +#define AUX_TIMER01_O_T0CFG 0x00000000 // Timer 0 Control -#define AUX_TIMER01_O_T0CTL 0x00000004 +#define AUX_TIMER01_O_T0CTL 0x00000004 // Timer 0 Target -#define AUX_TIMER01_O_T0TARGET 0x00000008 +#define AUX_TIMER01_O_T0TARGET 0x00000008 // Timer 0 Counter -#define AUX_TIMER01_O_T0CNTR 0x0000000C +#define AUX_TIMER01_O_T0CNTR 0x0000000C // Timer 1 Configuration -#define AUX_TIMER01_O_T1CFG 0x00000010 +#define AUX_TIMER01_O_T1CFG 0x00000010 // Timer 1 Control -#define AUX_TIMER01_O_T1CTL 0x00000014 +#define AUX_TIMER01_O_T1CTL 0x00000014 // Timer 1 Target -#define AUX_TIMER01_O_T1TARGET 0x00000018 +#define AUX_TIMER01_O_T1TARGET 0x00000018 // Timer 1 Counter -#define AUX_TIMER01_O_T1CNTR 0x0000001C +#define AUX_TIMER01_O_T1CNTR 0x0000001C //***************************************************************************** // @@ -78,12 +78,12 @@ // ENUMs: // FALL Count on falling edges of TICK_SRC. // RISE Count on rising edges of TICK_SRC. -#define AUX_TIMER01_T0CFG_TICK_SRC_POL 0x00004000 -#define AUX_TIMER01_T0CFG_TICK_SRC_POL_BITN 14 -#define AUX_TIMER01_T0CFG_TICK_SRC_POL_M 0x00004000 -#define AUX_TIMER01_T0CFG_TICK_SRC_POL_S 14 -#define AUX_TIMER01_T0CFG_TICK_SRC_POL_FALL 0x00004000 -#define AUX_TIMER01_T0CFG_TICK_SRC_POL_RISE 0x00000000 +#define AUX_TIMER01_T0CFG_TICK_SRC_POL 0x00004000 +#define AUX_TIMER01_T0CFG_TICK_SRC_POL_BITN 14 +#define AUX_TIMER01_T0CFG_TICK_SRC_POL_M 0x00004000 +#define AUX_TIMER01_T0CFG_TICK_SRC_POL_S 14 +#define AUX_TIMER01_T0CFG_TICK_SRC_POL_FALL 0x00004000 +#define AUX_TIMER01_T0CFG_TICK_SRC_POL_RISE 0x00000000 // Field: [13:8] TICK_SRC // @@ -153,73 +153,73 @@ // AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 // AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 // AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_TIMER01_T0CFG_TICK_SRC_W 6 -#define AUX_TIMER01_T0CFG_TICK_SRC_M 0x00003F00 -#define AUX_TIMER01_T0CFG_TICK_SRC_S 8 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_CLKSW_RDY 0x00003F00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_DAC_HOLD_ACTIVE 0x00003E00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00003C00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00003B00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_IRQ 0x00003A00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_DONE 0x00003900 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ISRC_RESET_N 0x00003800 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TDC_DONE 0x00003700 -#define AUX_TIMER01_T0CFG_TICK_SRC_NO_EVENT 0x00003600 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER1_EV 0x00003500 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_PULSE 0x00003400 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV3 0x00003300 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV2 0x00003200 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV1 0x00003100 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV0 0x00003000 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_COMPB 0x00002F00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_COMPA 0x00002E00 -#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_OBSMUX1 0x00002D00 -#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_OBSMUX0 0x00002C00 -#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_EV 0x00002B00 -#define AUX_TIMER01_T0CFG_TICK_SRC_ACLK_REF 0x00002A00 -#define AUX_TIMER01_T0CFG_TICK_SRC_VDDR_RECHARGE 0x00002900 -#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_ACTIVE 0x00002800 -#define AUX_TIMER01_T0CFG_TICK_SRC_PWR_DWN 0x00002700 -#define AUX_TIMER01_T0CFG_TICK_SRC_SCLK_LF 0x00002600 -#define AUX_TIMER01_T0CFG_TICK_SRC_AON_BATMON_TEMP_UPD 0x00002500 -#define AUX_TIMER01_T0CFG_TICK_SRC_AON_BATMON_BAT_UPD 0x00002400 -#define AUX_TIMER01_T0CFG_TICK_SRC_AON_RTC_4KHZ 0x00002300 -#define AUX_TIMER01_T0CFG_TICK_SRC_AON_RTC_CH2_DLY 0x00002200 -#define AUX_TIMER01_T0CFG_TICK_SRC_AON_RTC_CH2 0x00002100 -#define AUX_TIMER01_T0CFG_TICK_SRC_MANUAL_EV 0x00002000 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO31 0x00001F00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO30 0x00001E00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO29 0x00001D00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO28 0x00001C00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO27 0x00001B00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO26 0x00001A00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO25 0x00001900 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO24 0x00001800 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO23 0x00001700 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO22 0x00001600 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO21 0x00001500 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO20 0x00001400 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO19 0x00001300 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO18 0x00001200 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO17 0x00001100 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO16 0x00001000 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO15 0x00000F00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO14 0x00000E00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO13 0x00000D00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO12 0x00000C00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO11 0x00000B00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO10 0x00000A00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO9 0x00000900 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO8 0x00000800 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO7 0x00000700 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO6 0x00000600 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO5 0x00000500 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO4 0x00000400 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO3 0x00000300 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO2 0x00000200 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO1 0x00000100 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO0 0x00000000 +#define AUX_TIMER01_T0CFG_TICK_SRC_W 6 +#define AUX_TIMER01_T0CFG_TICK_SRC_M 0x00003F00 +#define AUX_TIMER01_T0CFG_TICK_SRC_S 8 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_CLKSW_RDY 0x00003F00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_DAC_HOLD_ACTIVE 0x00003E00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00003C00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00003B00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_IRQ 0x00003A00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_DONE 0x00003900 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ISRC_RESET_N 0x00003800 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TDC_DONE 0x00003700 +#define AUX_TIMER01_T0CFG_TICK_SRC_NO_EVENT 0x00003600 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER1_EV 0x00003500 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_PULSE 0x00003400 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV3 0x00003300 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV2 0x00003200 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV1 0x00003100 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV0 0x00003000 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_COMPB 0x00002F00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_COMPA 0x00002E00 +#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_OBSMUX1 0x00002D00 +#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_OBSMUX0 0x00002C00 +#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_EV 0x00002B00 +#define AUX_TIMER01_T0CFG_TICK_SRC_ACLK_REF 0x00002A00 +#define AUX_TIMER01_T0CFG_TICK_SRC_VDDR_RECHARGE 0x00002900 +#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_ACTIVE 0x00002800 +#define AUX_TIMER01_T0CFG_TICK_SRC_PWR_DWN 0x00002700 +#define AUX_TIMER01_T0CFG_TICK_SRC_SCLK_LF 0x00002600 +#define AUX_TIMER01_T0CFG_TICK_SRC_AON_BATMON_TEMP_UPD 0x00002500 +#define AUX_TIMER01_T0CFG_TICK_SRC_AON_BATMON_BAT_UPD 0x00002400 +#define AUX_TIMER01_T0CFG_TICK_SRC_AON_RTC_4KHZ 0x00002300 +#define AUX_TIMER01_T0CFG_TICK_SRC_AON_RTC_CH2_DLY 0x00002200 +#define AUX_TIMER01_T0CFG_TICK_SRC_AON_RTC_CH2 0x00002100 +#define AUX_TIMER01_T0CFG_TICK_SRC_MANUAL_EV 0x00002000 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO31 0x00001F00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO30 0x00001E00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO29 0x00001D00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO28 0x00001C00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO27 0x00001B00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO26 0x00001A00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO25 0x00001900 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO24 0x00001800 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO23 0x00001700 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO22 0x00001600 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO21 0x00001500 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO20 0x00001400 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO19 0x00001300 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO18 0x00001200 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO17 0x00001100 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO16 0x00001000 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO15 0x00000F00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO14 0x00000E00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO13 0x00000D00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO12 0x00000C00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO11 0x00000B00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO10 0x00000A00 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO9 0x00000900 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO8 0x00000800 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO7 0x00000700 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO6 0x00000600 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO5 0x00000500 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO4 0x00000400 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO3 0x00000300 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO2 0x00000200 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO1 0x00000100 +#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO0 0x00000000 // Field: [7:4] PRE // @@ -230,9 +230,9 @@ // 0x2: Divide by 4. // ... // 0xF: Divide by 32,768. -#define AUX_TIMER01_T0CFG_PRE_W 4 -#define AUX_TIMER01_T0CFG_PRE_M 0x000000F0 -#define AUX_TIMER01_T0CFG_PRE_S 4 +#define AUX_TIMER01_T0CFG_PRE_W 4 +#define AUX_TIMER01_T0CFG_PRE_M 0x000000F0 +#define AUX_TIMER01_T0CFG_PRE_S 4 // Field: [1] MODE // @@ -244,12 +244,12 @@ // CLK Use clock as source for prescaler. Note that // AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the // clock frequency. -#define AUX_TIMER01_T0CFG_MODE 0x00000002 -#define AUX_TIMER01_T0CFG_MODE_BITN 1 -#define AUX_TIMER01_T0CFG_MODE_M 0x00000002 -#define AUX_TIMER01_T0CFG_MODE_S 1 -#define AUX_TIMER01_T0CFG_MODE_TICK 0x00000002 -#define AUX_TIMER01_T0CFG_MODE_CLK 0x00000000 +#define AUX_TIMER01_T0CFG_MODE 0x00000002 +#define AUX_TIMER01_T0CFG_MODE_BITN 1 +#define AUX_TIMER01_T0CFG_MODE_M 0x00000002 +#define AUX_TIMER01_T0CFG_MODE_S 1 +#define AUX_TIMER01_T0CFG_MODE_TICK 0x00000002 +#define AUX_TIMER01_T0CFG_MODE_CLK 0x00000000 // Field: [0] RELOAD // @@ -266,12 +266,12 @@ // T0CTL.EN becomes 0 when the counter value // becomes equal to or greater than // T0TARGET.VALUE. -#define AUX_TIMER01_T0CFG_RELOAD 0x00000001 -#define AUX_TIMER01_T0CFG_RELOAD_BITN 0 -#define AUX_TIMER01_T0CFG_RELOAD_M 0x00000001 -#define AUX_TIMER01_T0CFG_RELOAD_S 0 -#define AUX_TIMER01_T0CFG_RELOAD_CONT 0x00000001 -#define AUX_TIMER01_T0CFG_RELOAD_MAN 0x00000000 +#define AUX_TIMER01_T0CFG_RELOAD 0x00000001 +#define AUX_TIMER01_T0CFG_RELOAD_BITN 0 +#define AUX_TIMER01_T0CFG_RELOAD_M 0x00000001 +#define AUX_TIMER01_T0CFG_RELOAD_S 0 +#define AUX_TIMER01_T0CFG_RELOAD_CONT 0x00000001 +#define AUX_TIMER01_T0CFG_RELOAD_MAN 0x00000000 //***************************************************************************** // @@ -286,10 +286,10 @@ // 1: Enable Timer 0. // // The counter restarts from 0 when you enable Timer 0. -#define AUX_TIMER01_T0CTL_EN 0x00000001 -#define AUX_TIMER01_T0CTL_EN_BITN 0 -#define AUX_TIMER01_T0CTL_EN_M 0x00000001 -#define AUX_TIMER01_T0CTL_EN_S 0 +#define AUX_TIMER01_T0CTL_EN 0x00000001 +#define AUX_TIMER01_T0CTL_EN_BITN 0 +#define AUX_TIMER01_T0CTL_EN_M 0x00000001 +#define AUX_TIMER01_T0CTL_EN_S 0 //***************************************************************************** // @@ -321,9 +321,9 @@ // // // It is allowed to update the VALUE while the timer runs. -#define AUX_TIMER01_T0TARGET_VALUE_W 16 -#define AUX_TIMER01_T0TARGET_VALUE_M 0x0000FFFF -#define AUX_TIMER01_T0TARGET_VALUE_S 0 +#define AUX_TIMER01_T0TARGET_VALUE_W 16 +#define AUX_TIMER01_T0TARGET_VALUE_M 0x0000FFFF +#define AUX_TIMER01_T0TARGET_VALUE_S 0 //***************************************************************************** // @@ -333,9 +333,9 @@ // Field: [15:0] VALUE // // Timer 0 counter value. -#define AUX_TIMER01_T0CNTR_VALUE_W 16 -#define AUX_TIMER01_T0CNTR_VALUE_M 0x0000FFFF -#define AUX_TIMER01_T0CNTR_VALUE_S 0 +#define AUX_TIMER01_T0CNTR_VALUE_W 16 +#define AUX_TIMER01_T0CNTR_VALUE_M 0x0000FFFF +#define AUX_TIMER01_T0CNTR_VALUE_S 0 //***************************************************************************** // @@ -348,12 +348,12 @@ // ENUMs: // FALL Count on falling edges of TICK_SRC. // RISE Count on rising edges of TICK_SRC. -#define AUX_TIMER01_T1CFG_TICK_SRC_POL 0x00004000 -#define AUX_TIMER01_T1CFG_TICK_SRC_POL_BITN 14 -#define AUX_TIMER01_T1CFG_TICK_SRC_POL_M 0x00004000 -#define AUX_TIMER01_T1CFG_TICK_SRC_POL_S 14 -#define AUX_TIMER01_T1CFG_TICK_SRC_POL_FALL 0x00004000 -#define AUX_TIMER01_T1CFG_TICK_SRC_POL_RISE 0x00000000 +#define AUX_TIMER01_T1CFG_TICK_SRC_POL 0x00004000 +#define AUX_TIMER01_T1CFG_TICK_SRC_POL_BITN 14 +#define AUX_TIMER01_T1CFG_TICK_SRC_POL_M 0x00004000 +#define AUX_TIMER01_T1CFG_TICK_SRC_POL_S 14 +#define AUX_TIMER01_T1CFG_TICK_SRC_POL_FALL 0x00004000 +#define AUX_TIMER01_T1CFG_TICK_SRC_POL_RISE 0x00000000 // Field: [13:8] TICK_SRC // @@ -423,73 +423,73 @@ // AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 // AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 // AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_TIMER01_T1CFG_TICK_SRC_W 6 -#define AUX_TIMER01_T1CFG_TICK_SRC_M 0x00003F00 -#define AUX_TIMER01_T1CFG_TICK_SRC_S 8 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_CLKSW_RDY 0x00003F00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_DAC_HOLD_ACTIVE 0x00003E00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00003C00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00003B00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_IRQ 0x00003A00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_DONE 0x00003900 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ISRC_RESET_N 0x00003800 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TDC_DONE 0x00003700 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER0_EV 0x00003600 -#define AUX_TIMER01_T1CFG_TICK_SRC_NO_EVENT 0x00003500 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_PULSE 0x00003400 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV3 0x00003300 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV2 0x00003200 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV1 0x00003100 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV0 0x00003000 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_COMPB 0x00002F00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_COMPA 0x00002E00 -#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_OBSMUX1 0x00002D00 -#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_OBSMUX0 0x00002C00 -#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_EV 0x00002B00 -#define AUX_TIMER01_T1CFG_TICK_SRC_ACLK_REF 0x00002A00 -#define AUX_TIMER01_T1CFG_TICK_SRC_VDDR_RECHARGE 0x00002900 -#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_ACTIVE 0x00002800 -#define AUX_TIMER01_T1CFG_TICK_SRC_PWR_DWN 0x00002700 -#define AUX_TIMER01_T1CFG_TICK_SRC_SCLK_LF 0x00002600 -#define AUX_TIMER01_T1CFG_TICK_SRC_AON_BATMON_TEMP_UPD 0x00002500 -#define AUX_TIMER01_T1CFG_TICK_SRC_AON_BATMON_BAT_UPD 0x00002400 -#define AUX_TIMER01_T1CFG_TICK_SRC_AON_RTC_4KHZ 0x00002300 -#define AUX_TIMER01_T1CFG_TICK_SRC_AON_RTC_CH2_DLY 0x00002200 -#define AUX_TIMER01_T1CFG_TICK_SRC_AON_RTC_CH2 0x00002100 -#define AUX_TIMER01_T1CFG_TICK_SRC_MANUAL_EV 0x00002000 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO31 0x00001F00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO30 0x00001E00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO29 0x00001D00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO28 0x00001C00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO27 0x00001B00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO26 0x00001A00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO25 0x00001900 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO24 0x00001800 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO23 0x00001700 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO22 0x00001600 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO21 0x00001500 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO20 0x00001400 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO19 0x00001300 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO18 0x00001200 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO17 0x00001100 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO16 0x00001000 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO15 0x00000F00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO14 0x00000E00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO13 0x00000D00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO12 0x00000C00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO11 0x00000B00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO10 0x00000A00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO9 0x00000900 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO8 0x00000800 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO7 0x00000700 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO6 0x00000600 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO5 0x00000500 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO4 0x00000400 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO3 0x00000300 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO2 0x00000200 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO1 0x00000100 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO0 0x00000000 +#define AUX_TIMER01_T1CFG_TICK_SRC_W 6 +#define AUX_TIMER01_T1CFG_TICK_SRC_M 0x00003F00 +#define AUX_TIMER01_T1CFG_TICK_SRC_S 8 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_CLKSW_RDY 0x00003F00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_DAC_HOLD_ACTIVE 0x00003E00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00003C00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00003B00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_IRQ 0x00003A00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_DONE 0x00003900 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ISRC_RESET_N 0x00003800 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TDC_DONE 0x00003700 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER0_EV 0x00003600 +#define AUX_TIMER01_T1CFG_TICK_SRC_NO_EVENT 0x00003500 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_PULSE 0x00003400 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV3 0x00003300 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV2 0x00003200 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV1 0x00003100 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV0 0x00003000 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_COMPB 0x00002F00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_COMPA 0x00002E00 +#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_OBSMUX1 0x00002D00 +#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_OBSMUX0 0x00002C00 +#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_EV 0x00002B00 +#define AUX_TIMER01_T1CFG_TICK_SRC_ACLK_REF 0x00002A00 +#define AUX_TIMER01_T1CFG_TICK_SRC_VDDR_RECHARGE 0x00002900 +#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_ACTIVE 0x00002800 +#define AUX_TIMER01_T1CFG_TICK_SRC_PWR_DWN 0x00002700 +#define AUX_TIMER01_T1CFG_TICK_SRC_SCLK_LF 0x00002600 +#define AUX_TIMER01_T1CFG_TICK_SRC_AON_BATMON_TEMP_UPD 0x00002500 +#define AUX_TIMER01_T1CFG_TICK_SRC_AON_BATMON_BAT_UPD 0x00002400 +#define AUX_TIMER01_T1CFG_TICK_SRC_AON_RTC_4KHZ 0x00002300 +#define AUX_TIMER01_T1CFG_TICK_SRC_AON_RTC_CH2_DLY 0x00002200 +#define AUX_TIMER01_T1CFG_TICK_SRC_AON_RTC_CH2 0x00002100 +#define AUX_TIMER01_T1CFG_TICK_SRC_MANUAL_EV 0x00002000 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO31 0x00001F00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO30 0x00001E00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO29 0x00001D00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO28 0x00001C00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO27 0x00001B00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO26 0x00001A00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO25 0x00001900 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO24 0x00001800 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO23 0x00001700 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO22 0x00001600 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO21 0x00001500 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO20 0x00001400 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO19 0x00001300 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO18 0x00001200 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO17 0x00001100 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO16 0x00001000 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO15 0x00000F00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO14 0x00000E00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO13 0x00000D00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO12 0x00000C00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO11 0x00000B00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO10 0x00000A00 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO9 0x00000900 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO8 0x00000800 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO7 0x00000700 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO6 0x00000600 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO5 0x00000500 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO4 0x00000400 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO3 0x00000300 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO2 0x00000200 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO1 0x00000100 +#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO0 0x00000000 // Field: [7:4] PRE // @@ -500,9 +500,9 @@ // 0x2: Divide by 4. // ... // 0xF: Divide by 32,768. -#define AUX_TIMER01_T1CFG_PRE_W 4 -#define AUX_TIMER01_T1CFG_PRE_M 0x000000F0 -#define AUX_TIMER01_T1CFG_PRE_S 4 +#define AUX_TIMER01_T1CFG_PRE_W 4 +#define AUX_TIMER01_T1CFG_PRE_M 0x000000F0 +#define AUX_TIMER01_T1CFG_PRE_S 4 // Field: [1] MODE // @@ -514,12 +514,12 @@ // CLK Use clock as source for prescaler. Note that // AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the // clock frequency. -#define AUX_TIMER01_T1CFG_MODE 0x00000002 -#define AUX_TIMER01_T1CFG_MODE_BITN 1 -#define AUX_TIMER01_T1CFG_MODE_M 0x00000002 -#define AUX_TIMER01_T1CFG_MODE_S 1 -#define AUX_TIMER01_T1CFG_MODE_TICK 0x00000002 -#define AUX_TIMER01_T1CFG_MODE_CLK 0x00000000 +#define AUX_TIMER01_T1CFG_MODE 0x00000002 +#define AUX_TIMER01_T1CFG_MODE_BITN 1 +#define AUX_TIMER01_T1CFG_MODE_M 0x00000002 +#define AUX_TIMER01_T1CFG_MODE_S 1 +#define AUX_TIMER01_T1CFG_MODE_TICK 0x00000002 +#define AUX_TIMER01_T1CFG_MODE_CLK 0x00000000 // Field: [0] RELOAD // @@ -536,12 +536,12 @@ // T1CTL.EN becomes 0 when the counter value // becomes equal to or greater than // T1TARGET.VALUE. -#define AUX_TIMER01_T1CFG_RELOAD 0x00000001 -#define AUX_TIMER01_T1CFG_RELOAD_BITN 0 -#define AUX_TIMER01_T1CFG_RELOAD_M 0x00000001 -#define AUX_TIMER01_T1CFG_RELOAD_S 0 -#define AUX_TIMER01_T1CFG_RELOAD_CONT 0x00000001 -#define AUX_TIMER01_T1CFG_RELOAD_MAN 0x00000000 +#define AUX_TIMER01_T1CFG_RELOAD 0x00000001 +#define AUX_TIMER01_T1CFG_RELOAD_BITN 0 +#define AUX_TIMER01_T1CFG_RELOAD_M 0x00000001 +#define AUX_TIMER01_T1CFG_RELOAD_S 0 +#define AUX_TIMER01_T1CFG_RELOAD_CONT 0x00000001 +#define AUX_TIMER01_T1CFG_RELOAD_MAN 0x00000000 //***************************************************************************** // @@ -556,10 +556,10 @@ // 1: Enable Timer 1. // // The counter restarts from 0 when you enable Timer 1. -#define AUX_TIMER01_T1CTL_EN 0x00000001 -#define AUX_TIMER01_T1CTL_EN_BITN 0 -#define AUX_TIMER01_T1CTL_EN_M 0x00000001 -#define AUX_TIMER01_T1CTL_EN_S 0 +#define AUX_TIMER01_T1CTL_EN 0x00000001 +#define AUX_TIMER01_T1CTL_EN_BITN 0 +#define AUX_TIMER01_T1CTL_EN_M 0x00000001 +#define AUX_TIMER01_T1CTL_EN_S 0 //***************************************************************************** // @@ -591,9 +591,9 @@ // // // It is allowed to update the VALUE while the timer runs. -#define AUX_TIMER01_T1TARGET_VALUE_W 16 -#define AUX_TIMER01_T1TARGET_VALUE_M 0x0000FFFF -#define AUX_TIMER01_T1TARGET_VALUE_S 0 +#define AUX_TIMER01_T1TARGET_VALUE_W 16 +#define AUX_TIMER01_T1TARGET_VALUE_M 0x0000FFFF +#define AUX_TIMER01_T1TARGET_VALUE_S 0 //***************************************************************************** // @@ -603,9 +603,8 @@ // Field: [15:0] VALUE // // Timer 1 counter value. -#define AUX_TIMER01_T1CNTR_VALUE_W 16 -#define AUX_TIMER01_T1CNTR_VALUE_M 0x0000FFFF -#define AUX_TIMER01_T1CNTR_VALUE_S 0 - +#define AUX_TIMER01_T1CNTR_VALUE_W 16 +#define AUX_TIMER01_T1CNTR_VALUE_M 0x0000FFFF +#define AUX_TIMER01_T1CNTR_VALUE_S 0 #endif // __AUX_TIMER01__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer2.h index 48cb3cc..5bd1511 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer2.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer2.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_timer2_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_timer2_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_TIMER2_H__ #define __HW_AUX_TIMER2_H__ @@ -44,73 +44,73 @@ // //***************************************************************************** // Timer Control -#define AUX_TIMER2_O_CTL 0x00000000 +#define AUX_TIMER2_O_CTL 0x00000000 // Target -#define AUX_TIMER2_O_TARGET 0x00000004 +#define AUX_TIMER2_O_TARGET 0x00000004 // Shadow Target -#define AUX_TIMER2_O_SHDWTARGET 0x00000008 +#define AUX_TIMER2_O_SHDWTARGET 0x00000008 // Counter -#define AUX_TIMER2_O_CNTR 0x0000000C +#define AUX_TIMER2_O_CNTR 0x0000000C // Clock Prescaler Configuration -#define AUX_TIMER2_O_PRECFG 0x00000010 +#define AUX_TIMER2_O_PRECFG 0x00000010 // Event Control -#define AUX_TIMER2_O_EVCTL 0x00000014 +#define AUX_TIMER2_O_EVCTL 0x00000014 // Pulse Trigger -#define AUX_TIMER2_O_PULSETRIG 0x00000018 +#define AUX_TIMER2_O_PULSETRIG 0x00000018 // Channel 0 Event Configuration -#define AUX_TIMER2_O_CH0EVCFG 0x00000080 +#define AUX_TIMER2_O_CH0EVCFG 0x00000080 // Channel 0 Capture Configuration -#define AUX_TIMER2_O_CH0CCFG 0x00000084 +#define AUX_TIMER2_O_CH0CCFG 0x00000084 // Channel 0 Pipeline Capture Compare -#define AUX_TIMER2_O_CH0PCC 0x00000088 +#define AUX_TIMER2_O_CH0PCC 0x00000088 // Channel 0 Capture Compare -#define AUX_TIMER2_O_CH0CC 0x0000008C +#define AUX_TIMER2_O_CH0CC 0x0000008C // Channel 1 Event Configuration -#define AUX_TIMER2_O_CH1EVCFG 0x00000090 +#define AUX_TIMER2_O_CH1EVCFG 0x00000090 // Channel 1 Capture Configuration -#define AUX_TIMER2_O_CH1CCFG 0x00000094 +#define AUX_TIMER2_O_CH1CCFG 0x00000094 // Channel 1 Pipeline Capture Compare -#define AUX_TIMER2_O_CH1PCC 0x00000098 +#define AUX_TIMER2_O_CH1PCC 0x00000098 // Channel 1 Capture Compare -#define AUX_TIMER2_O_CH1CC 0x0000009C +#define AUX_TIMER2_O_CH1CC 0x0000009C // Channel 2 Event Configuration -#define AUX_TIMER2_O_CH2EVCFG 0x000000A0 +#define AUX_TIMER2_O_CH2EVCFG 0x000000A0 // Channel 2 Capture Configuration -#define AUX_TIMER2_O_CH2CCFG 0x000000A4 +#define AUX_TIMER2_O_CH2CCFG 0x000000A4 // Channel 2 Pipeline Capture Compare -#define AUX_TIMER2_O_CH2PCC 0x000000A8 +#define AUX_TIMER2_O_CH2PCC 0x000000A8 // Channel 2 Capture Compare -#define AUX_TIMER2_O_CH2CC 0x000000AC +#define AUX_TIMER2_O_CH2CC 0x000000AC // Channel 3 Event Configuration -#define AUX_TIMER2_O_CH3EVCFG 0x000000B0 +#define AUX_TIMER2_O_CH3EVCFG 0x000000B0 // Channel 3 Capture Configuration -#define AUX_TIMER2_O_CH3CCFG 0x000000B4 +#define AUX_TIMER2_O_CH3CCFG 0x000000B4 // Channel 3 Pipeline Capture Compare -#define AUX_TIMER2_O_CH3PCC 0x000000B8 +#define AUX_TIMER2_O_CH3PCC 0x000000B8 // Channel 3 Capture Compare -#define AUX_TIMER2_O_CH3CC 0x000000BC +#define AUX_TIMER2_O_CH3CC 0x000000BC //***************************************************************************** // @@ -125,10 +125,10 @@ // 1: Reset CH3CC, CH3PCC, CH3EVCFG, and CH3CCFG. // // Read returns 0. -#define AUX_TIMER2_CTL_CH3_RESET 0x00000040 -#define AUX_TIMER2_CTL_CH3_RESET_BITN 6 -#define AUX_TIMER2_CTL_CH3_RESET_M 0x00000040 -#define AUX_TIMER2_CTL_CH3_RESET_S 6 +#define AUX_TIMER2_CTL_CH3_RESET 0x00000040 +#define AUX_TIMER2_CTL_CH3_RESET_BITN 6 +#define AUX_TIMER2_CTL_CH3_RESET_M 0x00000040 +#define AUX_TIMER2_CTL_CH3_RESET_S 6 // Field: [5] CH2_RESET // @@ -138,10 +138,10 @@ // 1: Reset CH2CC, CH2PCC, CH2EVCFG, and CH2CCFG. // // Read returns 0. -#define AUX_TIMER2_CTL_CH2_RESET 0x00000020 -#define AUX_TIMER2_CTL_CH2_RESET_BITN 5 -#define AUX_TIMER2_CTL_CH2_RESET_M 0x00000020 -#define AUX_TIMER2_CTL_CH2_RESET_S 5 +#define AUX_TIMER2_CTL_CH2_RESET 0x00000020 +#define AUX_TIMER2_CTL_CH2_RESET_BITN 5 +#define AUX_TIMER2_CTL_CH2_RESET_M 0x00000020 +#define AUX_TIMER2_CTL_CH2_RESET_S 5 // Field: [4] CH1_RESET // @@ -151,10 +151,10 @@ // 1: Reset CH1CC, CH1PCC, CH1EVCFG, and CH1CCFG. // // Read returns 0. -#define AUX_TIMER2_CTL_CH1_RESET 0x00000010 -#define AUX_TIMER2_CTL_CH1_RESET_BITN 4 -#define AUX_TIMER2_CTL_CH1_RESET_M 0x00000010 -#define AUX_TIMER2_CTL_CH1_RESET_S 4 +#define AUX_TIMER2_CTL_CH1_RESET 0x00000010 +#define AUX_TIMER2_CTL_CH1_RESET_BITN 4 +#define AUX_TIMER2_CTL_CH1_RESET_M 0x00000010 +#define AUX_TIMER2_CTL_CH1_RESET_S 4 // Field: [3] CH0_RESET // @@ -164,10 +164,10 @@ // 1: Reset CH0CC, CH0PCC, CH0EVCFG, and CH0CCFG. // // Read returns 0. -#define AUX_TIMER2_CTL_CH0_RESET 0x00000008 -#define AUX_TIMER2_CTL_CH0_RESET_BITN 3 -#define AUX_TIMER2_CTL_CH0_RESET_M 0x00000008 -#define AUX_TIMER2_CTL_CH0_RESET_S 3 +#define AUX_TIMER2_CTL_CH0_RESET 0x00000008 +#define AUX_TIMER2_CTL_CH0_RESET_BITN 3 +#define AUX_TIMER2_CTL_CH0_RESET_M 0x00000008 +#define AUX_TIMER2_CTL_CH0_RESET_S 3 // Field: [2] TARGET_EN // @@ -177,12 +177,12 @@ // ENUMs: // TARGET TARGET.VALUE // CNTR_MAX 65535 -#define AUX_TIMER2_CTL_TARGET_EN 0x00000004 -#define AUX_TIMER2_CTL_TARGET_EN_BITN 2 -#define AUX_TIMER2_CTL_TARGET_EN_M 0x00000004 -#define AUX_TIMER2_CTL_TARGET_EN_S 2 -#define AUX_TIMER2_CTL_TARGET_EN_TARGET 0x00000004 -#define AUX_TIMER2_CTL_TARGET_EN_CNTR_MAX 0x00000000 +#define AUX_TIMER2_CTL_TARGET_EN 0x00000004 +#define AUX_TIMER2_CTL_TARGET_EN_BITN 2 +#define AUX_TIMER2_CTL_TARGET_EN_M 0x00000004 +#define AUX_TIMER2_CTL_TARGET_EN_S 2 +#define AUX_TIMER2_CTL_TARGET_EN_TARGET 0x00000004 +#define AUX_TIMER2_CTL_TARGET_EN_CNTR_MAX 0x00000000 // Field: [1:0] MODE // @@ -209,13 +209,13 @@ // target value, then stops and sets MODE to DIS. // DIS Disable timer. Updates to counter, channels, and // events stop. -#define AUX_TIMER2_CTL_MODE_W 2 -#define AUX_TIMER2_CTL_MODE_M 0x00000003 -#define AUX_TIMER2_CTL_MODE_S 0 -#define AUX_TIMER2_CTL_MODE_UPDWN_PER 0x00000003 -#define AUX_TIMER2_CTL_MODE_UP_PER 0x00000002 -#define AUX_TIMER2_CTL_MODE_UP_ONCE 0x00000001 -#define AUX_TIMER2_CTL_MODE_DIS 0x00000000 +#define AUX_TIMER2_CTL_MODE_W 2 +#define AUX_TIMER2_CTL_MODE_M 0x00000003 +#define AUX_TIMER2_CTL_MODE_S 0 +#define AUX_TIMER2_CTL_MODE_UPDWN_PER 0x00000003 +#define AUX_TIMER2_CTL_MODE_UP_PER 0x00000002 +#define AUX_TIMER2_CTL_MODE_UP_ONCE 0x00000001 +#define AUX_TIMER2_CTL_MODE_DIS 0x00000000 //***************************************************************************** // @@ -226,9 +226,9 @@ // // 16 bit user defined counter target value, which is used when selected by // CTL.TARGET_EN. -#define AUX_TIMER2_TARGET_VALUE_W 16 -#define AUX_TIMER2_TARGET_VALUE_M 0x0000FFFF -#define AUX_TIMER2_TARGET_VALUE_S 0 +#define AUX_TIMER2_TARGET_VALUE_W 16 +#define AUX_TIMER2_TARGET_VALUE_M 0x0000FFFF +#define AUX_TIMER2_TARGET_VALUE_S 0 //***************************************************************************** // @@ -244,9 +244,9 @@ // // This is useful to avoid period jitter in PWM applications with time-varying // period, sometimes referenced as phase corrected PWM. -#define AUX_TIMER2_SHDWTARGET_VALUE_W 16 -#define AUX_TIMER2_SHDWTARGET_VALUE_M 0x0000FFFF -#define AUX_TIMER2_SHDWTARGET_VALUE_S 0 +#define AUX_TIMER2_SHDWTARGET_VALUE_W 16 +#define AUX_TIMER2_SHDWTARGET_VALUE_M 0x0000FFFF +#define AUX_TIMER2_SHDWTARGET_VALUE_S 0 //***************************************************************************** // @@ -256,9 +256,9 @@ // Field: [15:0] VALUE // // 16 bit current counter value. -#define AUX_TIMER2_CNTR_VALUE_W 16 -#define AUX_TIMER2_CNTR_VALUE_M 0x0000FFFF -#define AUX_TIMER2_CNTR_VALUE_S 0 +#define AUX_TIMER2_CNTR_VALUE_W 16 +#define AUX_TIMER2_CNTR_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CNTR_VALUE_S 0 //***************************************************************************** // @@ -278,9 +278,9 @@ // 0x01: Divide by 2. // ... // 0xFF: Divide by 256. -#define AUX_TIMER2_PRECFG_CLKDIV_W 8 -#define AUX_TIMER2_PRECFG_CLKDIV_M 0x000000FF -#define AUX_TIMER2_PRECFG_CLKDIV_S 0 +#define AUX_TIMER2_PRECFG_CLKDIV_W 8 +#define AUX_TIMER2_PRECFG_CLKDIV_M 0x000000FF +#define AUX_TIMER2_PRECFG_CLKDIV_S 0 //***************************************************************************** // @@ -292,80 +292,80 @@ // Set event 3. // // Write 1 to set event 3. -#define AUX_TIMER2_EVCTL_EV3_SET 0x00000080 -#define AUX_TIMER2_EVCTL_EV3_SET_BITN 7 -#define AUX_TIMER2_EVCTL_EV3_SET_M 0x00000080 -#define AUX_TIMER2_EVCTL_EV3_SET_S 7 +#define AUX_TIMER2_EVCTL_EV3_SET 0x00000080 +#define AUX_TIMER2_EVCTL_EV3_SET_BITN 7 +#define AUX_TIMER2_EVCTL_EV3_SET_M 0x00000080 +#define AUX_TIMER2_EVCTL_EV3_SET_S 7 // Field: [6] EV3_CLR // // Clear event 3. // // Write 1 to clear event 3. -#define AUX_TIMER2_EVCTL_EV3_CLR 0x00000040 -#define AUX_TIMER2_EVCTL_EV3_CLR_BITN 6 -#define AUX_TIMER2_EVCTL_EV3_CLR_M 0x00000040 -#define AUX_TIMER2_EVCTL_EV3_CLR_S 6 +#define AUX_TIMER2_EVCTL_EV3_CLR 0x00000040 +#define AUX_TIMER2_EVCTL_EV3_CLR_BITN 6 +#define AUX_TIMER2_EVCTL_EV3_CLR_M 0x00000040 +#define AUX_TIMER2_EVCTL_EV3_CLR_S 6 // Field: [5] EV2_SET // // Set event 2. // // Write 1 to set event 2. -#define AUX_TIMER2_EVCTL_EV2_SET 0x00000020 -#define AUX_TIMER2_EVCTL_EV2_SET_BITN 5 -#define AUX_TIMER2_EVCTL_EV2_SET_M 0x00000020 -#define AUX_TIMER2_EVCTL_EV2_SET_S 5 +#define AUX_TIMER2_EVCTL_EV2_SET 0x00000020 +#define AUX_TIMER2_EVCTL_EV2_SET_BITN 5 +#define AUX_TIMER2_EVCTL_EV2_SET_M 0x00000020 +#define AUX_TIMER2_EVCTL_EV2_SET_S 5 // Field: [4] EV2_CLR // // Clear event 2. // // Write 1 to clear event 2. -#define AUX_TIMER2_EVCTL_EV2_CLR 0x00000010 -#define AUX_TIMER2_EVCTL_EV2_CLR_BITN 4 -#define AUX_TIMER2_EVCTL_EV2_CLR_M 0x00000010 -#define AUX_TIMER2_EVCTL_EV2_CLR_S 4 +#define AUX_TIMER2_EVCTL_EV2_CLR 0x00000010 +#define AUX_TIMER2_EVCTL_EV2_CLR_BITN 4 +#define AUX_TIMER2_EVCTL_EV2_CLR_M 0x00000010 +#define AUX_TIMER2_EVCTL_EV2_CLR_S 4 // Field: [3] EV1_SET // // Set event 1. // // Write 1 to set event 1. -#define AUX_TIMER2_EVCTL_EV1_SET 0x00000008 -#define AUX_TIMER2_EVCTL_EV1_SET_BITN 3 -#define AUX_TIMER2_EVCTL_EV1_SET_M 0x00000008 -#define AUX_TIMER2_EVCTL_EV1_SET_S 3 +#define AUX_TIMER2_EVCTL_EV1_SET 0x00000008 +#define AUX_TIMER2_EVCTL_EV1_SET_BITN 3 +#define AUX_TIMER2_EVCTL_EV1_SET_M 0x00000008 +#define AUX_TIMER2_EVCTL_EV1_SET_S 3 // Field: [2] EV1_CLR // // Clear event 1. // // Write 1 to clear event 1. -#define AUX_TIMER2_EVCTL_EV1_CLR 0x00000004 -#define AUX_TIMER2_EVCTL_EV1_CLR_BITN 2 -#define AUX_TIMER2_EVCTL_EV1_CLR_M 0x00000004 -#define AUX_TIMER2_EVCTL_EV1_CLR_S 2 +#define AUX_TIMER2_EVCTL_EV1_CLR 0x00000004 +#define AUX_TIMER2_EVCTL_EV1_CLR_BITN 2 +#define AUX_TIMER2_EVCTL_EV1_CLR_M 0x00000004 +#define AUX_TIMER2_EVCTL_EV1_CLR_S 2 // Field: [1] EV0_SET // // Set event 0. // // Write 1 to set event 0. -#define AUX_TIMER2_EVCTL_EV0_SET 0x00000002 -#define AUX_TIMER2_EVCTL_EV0_SET_BITN 1 -#define AUX_TIMER2_EVCTL_EV0_SET_M 0x00000002 -#define AUX_TIMER2_EVCTL_EV0_SET_S 1 +#define AUX_TIMER2_EVCTL_EV0_SET 0x00000002 +#define AUX_TIMER2_EVCTL_EV0_SET_BITN 1 +#define AUX_TIMER2_EVCTL_EV0_SET_M 0x00000002 +#define AUX_TIMER2_EVCTL_EV0_SET_S 1 // Field: [0] EV0_CLR // // Clear event 0. // // Write 1 to clear event 0. -#define AUX_TIMER2_EVCTL_EV0_CLR 0x00000001 -#define AUX_TIMER2_EVCTL_EV0_CLR_BITN 0 -#define AUX_TIMER2_EVCTL_EV0_CLR_M 0x00000001 -#define AUX_TIMER2_EVCTL_EV0_CLR_S 0 +#define AUX_TIMER2_EVCTL_EV0_CLR 0x00000001 +#define AUX_TIMER2_EVCTL_EV0_CLR_BITN 0 +#define AUX_TIMER2_EVCTL_EV0_CLR_M 0x00000001 +#define AUX_TIMER2_EVCTL_EV0_CLR_S 0 //***************************************************************************** // @@ -378,10 +378,10 @@ // // Write 1 to generate a pulse to AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. Pulse // width equals the duty cycle of AUX_SYSIF:TIMER2CLKCTL.SRC. -#define AUX_TIMER2_PULSETRIG_TRIG 0x00000001 -#define AUX_TIMER2_PULSETRIG_TRIG_BITN 0 -#define AUX_TIMER2_PULSETRIG_TRIG_M 0x00000001 -#define AUX_TIMER2_PULSETRIG_TRIG_S 0 +#define AUX_TIMER2_PULSETRIG_TRIG 0x00000001 +#define AUX_TIMER2_PULSETRIG_TRIG_BITN 0 +#define AUX_TIMER2_PULSETRIG_TRIG_M 0x00000001 +#define AUX_TIMER2_PULSETRIG_TRIG_S 0 //***************************************************************************** // @@ -396,10 +396,10 @@ // 1: Channel 0 controls event 3. // // When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH0EVCFG_EV3_GEN 0x00000080 -#define AUX_TIMER2_CH0EVCFG_EV3_GEN_BITN 7 -#define AUX_TIMER2_CH0EVCFG_EV3_GEN_M 0x00000080 -#define AUX_TIMER2_CH0EVCFG_EV3_GEN_S 7 +#define AUX_TIMER2_CH0EVCFG_EV3_GEN 0x00000080 +#define AUX_TIMER2_CH0EVCFG_EV3_GEN_BITN 7 +#define AUX_TIMER2_CH0EVCFG_EV3_GEN_M 0x00000080 +#define AUX_TIMER2_CH0EVCFG_EV3_GEN_S 7 // Field: [6] EV2_GEN // @@ -409,10 +409,10 @@ // 1: Channel 0 controls event 2. // // When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH0EVCFG_EV2_GEN 0x00000040 -#define AUX_TIMER2_CH0EVCFG_EV2_GEN_BITN 6 -#define AUX_TIMER2_CH0EVCFG_EV2_GEN_M 0x00000040 -#define AUX_TIMER2_CH0EVCFG_EV2_GEN_S 6 +#define AUX_TIMER2_CH0EVCFG_EV2_GEN 0x00000040 +#define AUX_TIMER2_CH0EVCFG_EV2_GEN_BITN 6 +#define AUX_TIMER2_CH0EVCFG_EV2_GEN_M 0x00000040 +#define AUX_TIMER2_CH0EVCFG_EV2_GEN_S 6 // Field: [5] EV1_GEN // @@ -422,10 +422,10 @@ // 1: Channel 0 controls event 1. // // When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH0EVCFG_EV1_GEN 0x00000020 -#define AUX_TIMER2_CH0EVCFG_EV1_GEN_BITN 5 -#define AUX_TIMER2_CH0EVCFG_EV1_GEN_M 0x00000020 -#define AUX_TIMER2_CH0EVCFG_EV1_GEN_S 5 +#define AUX_TIMER2_CH0EVCFG_EV1_GEN 0x00000020 +#define AUX_TIMER2_CH0EVCFG_EV1_GEN_BITN 5 +#define AUX_TIMER2_CH0EVCFG_EV1_GEN_M 0x00000020 +#define AUX_TIMER2_CH0EVCFG_EV1_GEN_S 5 // Field: [4] EV0_GEN // @@ -435,10 +435,10 @@ // 1: Channel 0 controls event 0. // // When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH0EVCFG_EV0_GEN 0x00000010 -#define AUX_TIMER2_CH0EVCFG_EV0_GEN_BITN 4 -#define AUX_TIMER2_CH0EVCFG_EV0_GEN_M 0x00000010 -#define AUX_TIMER2_CH0EVCFG_EV0_GEN_S 4 +#define AUX_TIMER2_CH0EVCFG_EV0_GEN 0x00000010 +#define AUX_TIMER2_CH0EVCFG_EV0_GEN_BITN 4 +#define AUX_TIMER2_CH0EVCFG_EV0_GEN_M 0x00000010 +#define AUX_TIMER2_CH0EVCFG_EV0_GEN_S 4 // Field: [3:0] CCACT // @@ -674,25 +674,25 @@ // capture events caused by expired signal values // in edge-detection circuit. // DIS Disable channel. -#define AUX_TIMER2_CH0EVCFG_CCACT_W 4 -#define AUX_TIMER2_CH0EVCFG_CCACT_M 0x0000000F -#define AUX_TIMER2_CH0EVCFG_CCACT_S 0 -#define AUX_TIMER2_CH0EVCFG_CCACT_PULSE_ON_CMP 0x0000000F -#define AUX_TIMER2_CH0EVCFG_CCACT_TGL_ON_CMP 0x0000000E -#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CMP 0x0000000D -#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_CMP 0x0000000C -#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B -#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A -#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CAPT 0x00000009 -#define AUX_TIMER2_CH0EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 -#define AUX_TIMER2_CH0EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 -#define AUX_TIMER2_CH0EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 -#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 -#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 -#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 -#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 -#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 -#define AUX_TIMER2_CH0EVCFG_CCACT_DIS 0x00000000 +#define AUX_TIMER2_CH0EVCFG_CCACT_W 4 +#define AUX_TIMER2_CH0EVCFG_CCACT_M 0x0000000F +#define AUX_TIMER2_CH0EVCFG_CCACT_S 0 +#define AUX_TIMER2_CH0EVCFG_CCACT_PULSE_ON_CMP 0x0000000F +#define AUX_TIMER2_CH0EVCFG_CCACT_TGL_ON_CMP 0x0000000E +#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CMP 0x0000000D +#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_CMP 0x0000000C +#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B +#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A +#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CAPT 0x00000009 +#define AUX_TIMER2_CH0EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 +#define AUX_TIMER2_CH0EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 +#define AUX_TIMER2_CH0EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 +#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 +#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 +#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 +#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 +#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 +#define AUX_TIMER2_CH0EVCFG_CCACT_DIS 0x00000000 //***************************************************************************** // @@ -780,71 +780,71 @@ // AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 // AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 // AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_W 6 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_M 0x0000007E -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_S 1 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_NO_EVENT 0x0000007E -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_COMPB 0x0000005E -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_COMPA 0x0000005C -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_EV 0x00000056 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_ACLK_REF 0x00000054 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_PWR_DWN 0x0000004E -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_SCLK_LF 0x0000004C -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MANUAL_EV 0x00000040 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO31 0x0000003E -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO30 0x0000003C -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO29 0x0000003A -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO28 0x00000038 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO27 0x00000036 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO26 0x00000034 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO25 0x00000032 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO24 0x00000030 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO23 0x0000002E -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO22 0x0000002C -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO21 0x0000002A -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO20 0x00000028 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO19 0x00000026 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO18 0x00000024 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO17 0x00000022 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO16 0x00000020 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO15 0x0000001E -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO14 0x0000001C -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO13 0x0000001A -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO12 0x00000018 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO11 0x00000016 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO10 0x00000014 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO9 0x00000012 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO8 0x00000010 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO7 0x0000000E -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO6 0x0000000C -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO5 0x0000000A -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO4 0x00000008 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO3 0x00000006 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO2 0x00000004 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO1 0x00000002 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO0 0x00000000 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_W 6 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_M 0x0000007E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_S 1 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_NO_EVENT 0x0000007E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_COMPB 0x0000005E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_COMPA 0x0000005C +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_EV 0x00000056 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_ACLK_REF 0x00000054 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_PWR_DWN 0x0000004E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_SCLK_LF 0x0000004C +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MANUAL_EV 0x00000040 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO31 0x0000003E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO30 0x0000003C +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO29 0x0000003A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO28 0x00000038 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO27 0x00000036 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO26 0x00000034 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO25 0x00000032 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO24 0x00000030 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO23 0x0000002E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO22 0x0000002C +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO21 0x0000002A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO20 0x00000028 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO19 0x00000026 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO18 0x00000024 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO17 0x00000022 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO16 0x00000020 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO15 0x0000001E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO14 0x0000001C +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO13 0x0000001A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO12 0x00000018 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO11 0x00000016 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO10 0x00000014 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO9 0x00000012 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO8 0x00000010 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO7 0x0000000E +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO6 0x0000000C +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO5 0x0000000A +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO4 0x00000008 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO3 0x00000006 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO2 0x00000004 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO1 0x00000002 +#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO0 0x00000000 // Field: [0] EDGE // @@ -855,12 +855,12 @@ // ENUMs: // RISING Capture CNTR.VALUE at rising edge of CAPT_SRC. // FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC. -#define AUX_TIMER2_CH0CCFG_EDGE 0x00000001 -#define AUX_TIMER2_CH0CCFG_EDGE_BITN 0 -#define AUX_TIMER2_CH0CCFG_EDGE_M 0x00000001 -#define AUX_TIMER2_CH0CCFG_EDGE_S 0 -#define AUX_TIMER2_CH0CCFG_EDGE_RISING 0x00000001 -#define AUX_TIMER2_CH0CCFG_EDGE_FALLING 0x00000000 +#define AUX_TIMER2_CH0CCFG_EDGE 0x00000001 +#define AUX_TIMER2_CH0CCFG_EDGE_BITN 0 +#define AUX_TIMER2_CH0CCFG_EDGE_M 0x00000001 +#define AUX_TIMER2_CH0CCFG_EDGE_S 0 +#define AUX_TIMER2_CH0CCFG_EDGE_RISING 0x00000001 +#define AUX_TIMER2_CH0CCFG_EDGE_FALLING 0x00000000 //***************************************************************************** // @@ -882,9 +882,9 @@ // When CH0EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the // width of the low or high phase of the selected signal. This is specified by // CH0CCFG.EDGE and CH0CCFG.CAPT_SRC. -#define AUX_TIMER2_CH0PCC_VALUE_W 16 -#define AUX_TIMER2_CH0PCC_VALUE_M 0x0000FFFF -#define AUX_TIMER2_CH0PCC_VALUE_S 0 +#define AUX_TIMER2_CH0PCC_VALUE_W 16 +#define AUX_TIMER2_CH0PCC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH0PCC_VALUE_S 0 //***************************************************************************** // @@ -905,9 +905,9 @@ // The current counter value is stored in VALUE when a capture event occurs. // CH0EVCFG.CCACT determines if VALUE is a signal period or a regular capture // value. -#define AUX_TIMER2_CH0CC_VALUE_W 16 -#define AUX_TIMER2_CH0CC_VALUE_M 0x0000FFFF -#define AUX_TIMER2_CH0CC_VALUE_S 0 +#define AUX_TIMER2_CH0CC_VALUE_W 16 +#define AUX_TIMER2_CH0CC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH0CC_VALUE_S 0 //***************************************************************************** // @@ -922,10 +922,10 @@ // 1: Channel 1 controls event 3. // // When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH1EVCFG_EV3_GEN 0x00000080 -#define AUX_TIMER2_CH1EVCFG_EV3_GEN_BITN 7 -#define AUX_TIMER2_CH1EVCFG_EV3_GEN_M 0x00000080 -#define AUX_TIMER2_CH1EVCFG_EV3_GEN_S 7 +#define AUX_TIMER2_CH1EVCFG_EV3_GEN 0x00000080 +#define AUX_TIMER2_CH1EVCFG_EV3_GEN_BITN 7 +#define AUX_TIMER2_CH1EVCFG_EV3_GEN_M 0x00000080 +#define AUX_TIMER2_CH1EVCFG_EV3_GEN_S 7 // Field: [6] EV2_GEN // @@ -935,10 +935,10 @@ // 1: Channel 1 controls event 2. // // When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH1EVCFG_EV2_GEN 0x00000040 -#define AUX_TIMER2_CH1EVCFG_EV2_GEN_BITN 6 -#define AUX_TIMER2_CH1EVCFG_EV2_GEN_M 0x00000040 -#define AUX_TIMER2_CH1EVCFG_EV2_GEN_S 6 +#define AUX_TIMER2_CH1EVCFG_EV2_GEN 0x00000040 +#define AUX_TIMER2_CH1EVCFG_EV2_GEN_BITN 6 +#define AUX_TIMER2_CH1EVCFG_EV2_GEN_M 0x00000040 +#define AUX_TIMER2_CH1EVCFG_EV2_GEN_S 6 // Field: [5] EV1_GEN // @@ -948,10 +948,10 @@ // 1: Channel 1 controls event 1. // // When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH1EVCFG_EV1_GEN 0x00000020 -#define AUX_TIMER2_CH1EVCFG_EV1_GEN_BITN 5 -#define AUX_TIMER2_CH1EVCFG_EV1_GEN_M 0x00000020 -#define AUX_TIMER2_CH1EVCFG_EV1_GEN_S 5 +#define AUX_TIMER2_CH1EVCFG_EV1_GEN 0x00000020 +#define AUX_TIMER2_CH1EVCFG_EV1_GEN_BITN 5 +#define AUX_TIMER2_CH1EVCFG_EV1_GEN_M 0x00000020 +#define AUX_TIMER2_CH1EVCFG_EV1_GEN_S 5 // Field: [4] EV0_GEN // @@ -961,10 +961,10 @@ // 1: Channel 1 controls event 0. // // When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH1EVCFG_EV0_GEN 0x00000010 -#define AUX_TIMER2_CH1EVCFG_EV0_GEN_BITN 4 -#define AUX_TIMER2_CH1EVCFG_EV0_GEN_M 0x00000010 -#define AUX_TIMER2_CH1EVCFG_EV0_GEN_S 4 +#define AUX_TIMER2_CH1EVCFG_EV0_GEN 0x00000010 +#define AUX_TIMER2_CH1EVCFG_EV0_GEN_BITN 4 +#define AUX_TIMER2_CH1EVCFG_EV0_GEN_M 0x00000010 +#define AUX_TIMER2_CH1EVCFG_EV0_GEN_S 4 // Field: [3:0] CCACT // @@ -1200,25 +1200,25 @@ // capture events caused by expired signal values // in edge-detection circuit. // DIS Disable channel. -#define AUX_TIMER2_CH1EVCFG_CCACT_W 4 -#define AUX_TIMER2_CH1EVCFG_CCACT_M 0x0000000F -#define AUX_TIMER2_CH1EVCFG_CCACT_S 0 -#define AUX_TIMER2_CH1EVCFG_CCACT_PULSE_ON_CMP 0x0000000F -#define AUX_TIMER2_CH1EVCFG_CCACT_TGL_ON_CMP 0x0000000E -#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CMP 0x0000000D -#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_CMP 0x0000000C -#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B -#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A -#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CAPT 0x00000009 -#define AUX_TIMER2_CH1EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 -#define AUX_TIMER2_CH1EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 -#define AUX_TIMER2_CH1EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 -#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 -#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 -#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 -#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 -#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 -#define AUX_TIMER2_CH1EVCFG_CCACT_DIS 0x00000000 +#define AUX_TIMER2_CH1EVCFG_CCACT_W 4 +#define AUX_TIMER2_CH1EVCFG_CCACT_M 0x0000000F +#define AUX_TIMER2_CH1EVCFG_CCACT_S 0 +#define AUX_TIMER2_CH1EVCFG_CCACT_PULSE_ON_CMP 0x0000000F +#define AUX_TIMER2_CH1EVCFG_CCACT_TGL_ON_CMP 0x0000000E +#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CMP 0x0000000D +#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_CMP 0x0000000C +#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B +#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A +#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CAPT 0x00000009 +#define AUX_TIMER2_CH1EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 +#define AUX_TIMER2_CH1EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 +#define AUX_TIMER2_CH1EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 +#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 +#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 +#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 +#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 +#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 +#define AUX_TIMER2_CH1EVCFG_CCACT_DIS 0x00000000 //***************************************************************************** // @@ -1306,71 +1306,71 @@ // AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 // AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 // AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_W 6 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_M 0x0000007E -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_S 1 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_NO_EVENT 0x0000007E -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_COMPB 0x0000005E -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_COMPA 0x0000005C -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_EV 0x00000056 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_ACLK_REF 0x00000054 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_PWR_DWN 0x0000004E -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_SCLK_LF 0x0000004C -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MANUAL_EV 0x00000040 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO31 0x0000003E -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO30 0x0000003C -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO29 0x0000003A -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO28 0x00000038 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO27 0x00000036 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO26 0x00000034 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO25 0x00000032 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO24 0x00000030 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO23 0x0000002E -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO22 0x0000002C -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO21 0x0000002A -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO20 0x00000028 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO19 0x00000026 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO18 0x00000024 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO17 0x00000022 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO16 0x00000020 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO15 0x0000001E -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO14 0x0000001C -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO13 0x0000001A -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO12 0x00000018 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO11 0x00000016 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO10 0x00000014 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO9 0x00000012 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO8 0x00000010 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO7 0x0000000E -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO6 0x0000000C -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO5 0x0000000A -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO4 0x00000008 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO3 0x00000006 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO2 0x00000004 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO1 0x00000002 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO0 0x00000000 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_W 6 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_M 0x0000007E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_S 1 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_NO_EVENT 0x0000007E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_COMPB 0x0000005E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_COMPA 0x0000005C +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_EV 0x00000056 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_ACLK_REF 0x00000054 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_PWR_DWN 0x0000004E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_SCLK_LF 0x0000004C +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MANUAL_EV 0x00000040 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO31 0x0000003E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO30 0x0000003C +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO29 0x0000003A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO28 0x00000038 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO27 0x00000036 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO26 0x00000034 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO25 0x00000032 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO24 0x00000030 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO23 0x0000002E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO22 0x0000002C +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO21 0x0000002A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO20 0x00000028 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO19 0x00000026 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO18 0x00000024 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO17 0x00000022 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO16 0x00000020 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO15 0x0000001E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO14 0x0000001C +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO13 0x0000001A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO12 0x00000018 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO11 0x00000016 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO10 0x00000014 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO9 0x00000012 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO8 0x00000010 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO7 0x0000000E +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO6 0x0000000C +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO5 0x0000000A +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO4 0x00000008 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO3 0x00000006 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO2 0x00000004 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO1 0x00000002 +#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO0 0x00000000 // Field: [0] EDGE // @@ -1381,12 +1381,12 @@ // ENUMs: // RISING Capture CNTR.VALUE at rising edge of CAPT_SRC. // FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC. -#define AUX_TIMER2_CH1CCFG_EDGE 0x00000001 -#define AUX_TIMER2_CH1CCFG_EDGE_BITN 0 -#define AUX_TIMER2_CH1CCFG_EDGE_M 0x00000001 -#define AUX_TIMER2_CH1CCFG_EDGE_S 0 -#define AUX_TIMER2_CH1CCFG_EDGE_RISING 0x00000001 -#define AUX_TIMER2_CH1CCFG_EDGE_FALLING 0x00000000 +#define AUX_TIMER2_CH1CCFG_EDGE 0x00000001 +#define AUX_TIMER2_CH1CCFG_EDGE_BITN 0 +#define AUX_TIMER2_CH1CCFG_EDGE_M 0x00000001 +#define AUX_TIMER2_CH1CCFG_EDGE_S 0 +#define AUX_TIMER2_CH1CCFG_EDGE_RISING 0x00000001 +#define AUX_TIMER2_CH1CCFG_EDGE_FALLING 0x00000000 //***************************************************************************** // @@ -1408,9 +1408,9 @@ // When CH1EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the // width of the low or high phase of the selected signal. This is specified by // CH1CCFG.EDGE and CH1CCFG.CAPT_SRC. -#define AUX_TIMER2_CH1PCC_VALUE_W 16 -#define AUX_TIMER2_CH1PCC_VALUE_M 0x0000FFFF -#define AUX_TIMER2_CH1PCC_VALUE_S 0 +#define AUX_TIMER2_CH1PCC_VALUE_W 16 +#define AUX_TIMER2_CH1PCC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH1PCC_VALUE_S 0 //***************************************************************************** // @@ -1431,9 +1431,9 @@ // The current counter value is stored in VALUE when a capture event occurs. // CH1EVCFG.CCACT determines if VALUE is a signal period or a regular capture // value. -#define AUX_TIMER2_CH1CC_VALUE_W 16 -#define AUX_TIMER2_CH1CC_VALUE_M 0x0000FFFF -#define AUX_TIMER2_CH1CC_VALUE_S 0 +#define AUX_TIMER2_CH1CC_VALUE_W 16 +#define AUX_TIMER2_CH1CC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH1CC_VALUE_S 0 //***************************************************************************** // @@ -1448,10 +1448,10 @@ // 1: Channel 2 controls event 3. // // When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH2EVCFG_EV3_GEN 0x00000080 -#define AUX_TIMER2_CH2EVCFG_EV3_GEN_BITN 7 -#define AUX_TIMER2_CH2EVCFG_EV3_GEN_M 0x00000080 -#define AUX_TIMER2_CH2EVCFG_EV3_GEN_S 7 +#define AUX_TIMER2_CH2EVCFG_EV3_GEN 0x00000080 +#define AUX_TIMER2_CH2EVCFG_EV3_GEN_BITN 7 +#define AUX_TIMER2_CH2EVCFG_EV3_GEN_M 0x00000080 +#define AUX_TIMER2_CH2EVCFG_EV3_GEN_S 7 // Field: [6] EV2_GEN // @@ -1461,10 +1461,10 @@ // 1: Channel 2 controls event 2. // // When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH2EVCFG_EV2_GEN 0x00000040 -#define AUX_TIMER2_CH2EVCFG_EV2_GEN_BITN 6 -#define AUX_TIMER2_CH2EVCFG_EV2_GEN_M 0x00000040 -#define AUX_TIMER2_CH2EVCFG_EV2_GEN_S 6 +#define AUX_TIMER2_CH2EVCFG_EV2_GEN 0x00000040 +#define AUX_TIMER2_CH2EVCFG_EV2_GEN_BITN 6 +#define AUX_TIMER2_CH2EVCFG_EV2_GEN_M 0x00000040 +#define AUX_TIMER2_CH2EVCFG_EV2_GEN_S 6 // Field: [5] EV1_GEN // @@ -1474,10 +1474,10 @@ // 1: Channel 2 controls event 1. // // When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH2EVCFG_EV1_GEN 0x00000020 -#define AUX_TIMER2_CH2EVCFG_EV1_GEN_BITN 5 -#define AUX_TIMER2_CH2EVCFG_EV1_GEN_M 0x00000020 -#define AUX_TIMER2_CH2EVCFG_EV1_GEN_S 5 +#define AUX_TIMER2_CH2EVCFG_EV1_GEN 0x00000020 +#define AUX_TIMER2_CH2EVCFG_EV1_GEN_BITN 5 +#define AUX_TIMER2_CH2EVCFG_EV1_GEN_M 0x00000020 +#define AUX_TIMER2_CH2EVCFG_EV1_GEN_S 5 // Field: [4] EV0_GEN // @@ -1487,10 +1487,10 @@ // 1: Channel 2 controls event 0. // // When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH2EVCFG_EV0_GEN 0x00000010 -#define AUX_TIMER2_CH2EVCFG_EV0_GEN_BITN 4 -#define AUX_TIMER2_CH2EVCFG_EV0_GEN_M 0x00000010 -#define AUX_TIMER2_CH2EVCFG_EV0_GEN_S 4 +#define AUX_TIMER2_CH2EVCFG_EV0_GEN 0x00000010 +#define AUX_TIMER2_CH2EVCFG_EV0_GEN_BITN 4 +#define AUX_TIMER2_CH2EVCFG_EV0_GEN_M 0x00000010 +#define AUX_TIMER2_CH2EVCFG_EV0_GEN_S 4 // Field: [3:0] CCACT // @@ -1726,25 +1726,25 @@ // capture events caused by expired signal values // in edge-detection circuit. // DIS Disable channel. -#define AUX_TIMER2_CH2EVCFG_CCACT_W 4 -#define AUX_TIMER2_CH2EVCFG_CCACT_M 0x0000000F -#define AUX_TIMER2_CH2EVCFG_CCACT_S 0 -#define AUX_TIMER2_CH2EVCFG_CCACT_PULSE_ON_CMP 0x0000000F -#define AUX_TIMER2_CH2EVCFG_CCACT_TGL_ON_CMP 0x0000000E -#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CMP 0x0000000D -#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_CMP 0x0000000C -#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B -#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A -#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CAPT 0x00000009 -#define AUX_TIMER2_CH2EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 -#define AUX_TIMER2_CH2EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 -#define AUX_TIMER2_CH2EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 -#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 -#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 -#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 -#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 -#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 -#define AUX_TIMER2_CH2EVCFG_CCACT_DIS 0x00000000 +#define AUX_TIMER2_CH2EVCFG_CCACT_W 4 +#define AUX_TIMER2_CH2EVCFG_CCACT_M 0x0000000F +#define AUX_TIMER2_CH2EVCFG_CCACT_S 0 +#define AUX_TIMER2_CH2EVCFG_CCACT_PULSE_ON_CMP 0x0000000F +#define AUX_TIMER2_CH2EVCFG_CCACT_TGL_ON_CMP 0x0000000E +#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CMP 0x0000000D +#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_CMP 0x0000000C +#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B +#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A +#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CAPT 0x00000009 +#define AUX_TIMER2_CH2EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 +#define AUX_TIMER2_CH2EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 +#define AUX_TIMER2_CH2EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 +#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 +#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 +#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 +#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 +#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 +#define AUX_TIMER2_CH2EVCFG_CCACT_DIS 0x00000000 //***************************************************************************** // @@ -1832,71 +1832,71 @@ // AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 // AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 // AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_W 6 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_M 0x0000007E -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_S 1 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_NO_EVENT 0x0000007E -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_COMPB 0x0000005E -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_COMPA 0x0000005C -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_EV 0x00000056 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_ACLK_REF 0x00000054 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_PWR_DWN 0x0000004E -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_SCLK_LF 0x0000004C -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MANUAL_EV 0x00000040 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO31 0x0000003E -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO30 0x0000003C -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO29 0x0000003A -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO28 0x00000038 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO27 0x00000036 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO26 0x00000034 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO25 0x00000032 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO24 0x00000030 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO23 0x0000002E -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO22 0x0000002C -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO21 0x0000002A -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO20 0x00000028 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO19 0x00000026 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO18 0x00000024 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO17 0x00000022 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO16 0x00000020 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO15 0x0000001E -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO14 0x0000001C -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO13 0x0000001A -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO12 0x00000018 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO11 0x00000016 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO10 0x00000014 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO9 0x00000012 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO8 0x00000010 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO7 0x0000000E -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO6 0x0000000C -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO5 0x0000000A -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO4 0x00000008 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO3 0x00000006 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO2 0x00000004 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO1 0x00000002 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO0 0x00000000 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_W 6 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_M 0x0000007E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_S 1 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_NO_EVENT 0x0000007E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_COMPB 0x0000005E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_COMPA 0x0000005C +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_EV 0x00000056 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_ACLK_REF 0x00000054 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_PWR_DWN 0x0000004E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_SCLK_LF 0x0000004C +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MANUAL_EV 0x00000040 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO31 0x0000003E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO30 0x0000003C +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO29 0x0000003A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO28 0x00000038 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO27 0x00000036 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO26 0x00000034 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO25 0x00000032 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO24 0x00000030 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO23 0x0000002E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO22 0x0000002C +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO21 0x0000002A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO20 0x00000028 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO19 0x00000026 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO18 0x00000024 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO17 0x00000022 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO16 0x00000020 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO15 0x0000001E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO14 0x0000001C +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO13 0x0000001A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO12 0x00000018 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO11 0x00000016 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO10 0x00000014 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO9 0x00000012 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO8 0x00000010 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO7 0x0000000E +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO6 0x0000000C +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO5 0x0000000A +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO4 0x00000008 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO3 0x00000006 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO2 0x00000004 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO1 0x00000002 +#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO0 0x00000000 // Field: [0] EDGE // @@ -1907,12 +1907,12 @@ // ENUMs: // RISING Capture CNTR.VALUE at rising edge of CAPT_SRC. // FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC. -#define AUX_TIMER2_CH2CCFG_EDGE 0x00000001 -#define AUX_TIMER2_CH2CCFG_EDGE_BITN 0 -#define AUX_TIMER2_CH2CCFG_EDGE_M 0x00000001 -#define AUX_TIMER2_CH2CCFG_EDGE_S 0 -#define AUX_TIMER2_CH2CCFG_EDGE_RISING 0x00000001 -#define AUX_TIMER2_CH2CCFG_EDGE_FALLING 0x00000000 +#define AUX_TIMER2_CH2CCFG_EDGE 0x00000001 +#define AUX_TIMER2_CH2CCFG_EDGE_BITN 0 +#define AUX_TIMER2_CH2CCFG_EDGE_M 0x00000001 +#define AUX_TIMER2_CH2CCFG_EDGE_S 0 +#define AUX_TIMER2_CH2CCFG_EDGE_RISING 0x00000001 +#define AUX_TIMER2_CH2CCFG_EDGE_FALLING 0x00000000 //***************************************************************************** // @@ -1934,9 +1934,9 @@ // When CH2EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the // width of the low or high phase of the selected signal. This is specified by // CH2CCFG.EDGE and CH2CCFG.CAPT_SRC. -#define AUX_TIMER2_CH2PCC_VALUE_W 16 -#define AUX_TIMER2_CH2PCC_VALUE_M 0x0000FFFF -#define AUX_TIMER2_CH2PCC_VALUE_S 0 +#define AUX_TIMER2_CH2PCC_VALUE_W 16 +#define AUX_TIMER2_CH2PCC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH2PCC_VALUE_S 0 //***************************************************************************** // @@ -1957,9 +1957,9 @@ // The current counter value is stored in VALUE when a capture event occurs. // CH2EVCFG.CCACT determines if VALUE is a signal period or a regular capture // value. -#define AUX_TIMER2_CH2CC_VALUE_W 16 -#define AUX_TIMER2_CH2CC_VALUE_M 0x0000FFFF -#define AUX_TIMER2_CH2CC_VALUE_S 0 +#define AUX_TIMER2_CH2CC_VALUE_W 16 +#define AUX_TIMER2_CH2CC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH2CC_VALUE_S 0 //***************************************************************************** // @@ -1974,10 +1974,10 @@ // 1: Channel 3 controls event 3. // // When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH3EVCFG_EV3_GEN 0x00000080 -#define AUX_TIMER2_CH3EVCFG_EV3_GEN_BITN 7 -#define AUX_TIMER2_CH3EVCFG_EV3_GEN_M 0x00000080 -#define AUX_TIMER2_CH3EVCFG_EV3_GEN_S 7 +#define AUX_TIMER2_CH3EVCFG_EV3_GEN 0x00000080 +#define AUX_TIMER2_CH3EVCFG_EV3_GEN_BITN 7 +#define AUX_TIMER2_CH3EVCFG_EV3_GEN_M 0x00000080 +#define AUX_TIMER2_CH3EVCFG_EV3_GEN_S 7 // Field: [6] EV2_GEN // @@ -1987,10 +1987,10 @@ // 1: Channel 3 controls event 2. // // When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH3EVCFG_EV2_GEN 0x00000040 -#define AUX_TIMER2_CH3EVCFG_EV2_GEN_BITN 6 -#define AUX_TIMER2_CH3EVCFG_EV2_GEN_M 0x00000040 -#define AUX_TIMER2_CH3EVCFG_EV2_GEN_S 6 +#define AUX_TIMER2_CH3EVCFG_EV2_GEN 0x00000040 +#define AUX_TIMER2_CH3EVCFG_EV2_GEN_BITN 6 +#define AUX_TIMER2_CH3EVCFG_EV2_GEN_M 0x00000040 +#define AUX_TIMER2_CH3EVCFG_EV2_GEN_S 6 // Field: [5] EV1_GEN // @@ -2000,10 +2000,10 @@ // 1: Channel 3 controls event 1. // // When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH3EVCFG_EV1_GEN 0x00000020 -#define AUX_TIMER2_CH3EVCFG_EV1_GEN_BITN 5 -#define AUX_TIMER2_CH3EVCFG_EV1_GEN_M 0x00000020 -#define AUX_TIMER2_CH3EVCFG_EV1_GEN_S 5 +#define AUX_TIMER2_CH3EVCFG_EV1_GEN 0x00000020 +#define AUX_TIMER2_CH3EVCFG_EV1_GEN_BITN 5 +#define AUX_TIMER2_CH3EVCFG_EV1_GEN_M 0x00000020 +#define AUX_TIMER2_CH3EVCFG_EV1_GEN_S 5 // Field: [4] EV0_GEN // @@ -2013,10 +2013,10 @@ // 1: Channel 3 controls event 0. // // When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH3EVCFG_EV0_GEN 0x00000010 -#define AUX_TIMER2_CH3EVCFG_EV0_GEN_BITN 4 -#define AUX_TIMER2_CH3EVCFG_EV0_GEN_M 0x00000010 -#define AUX_TIMER2_CH3EVCFG_EV0_GEN_S 4 +#define AUX_TIMER2_CH3EVCFG_EV0_GEN 0x00000010 +#define AUX_TIMER2_CH3EVCFG_EV0_GEN_BITN 4 +#define AUX_TIMER2_CH3EVCFG_EV0_GEN_M 0x00000010 +#define AUX_TIMER2_CH3EVCFG_EV0_GEN_S 4 // Field: [3:0] CCACT // @@ -2252,25 +2252,25 @@ // capture events caused by expired signal values // in edge-detection circuit. // DIS Disable channel. -#define AUX_TIMER2_CH3EVCFG_CCACT_W 4 -#define AUX_TIMER2_CH3EVCFG_CCACT_M 0x0000000F -#define AUX_TIMER2_CH3EVCFG_CCACT_S 0 -#define AUX_TIMER2_CH3EVCFG_CCACT_PULSE_ON_CMP 0x0000000F -#define AUX_TIMER2_CH3EVCFG_CCACT_TGL_ON_CMP 0x0000000E -#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CMP 0x0000000D -#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_CMP 0x0000000C -#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B -#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A -#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CAPT 0x00000009 -#define AUX_TIMER2_CH3EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 -#define AUX_TIMER2_CH3EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 -#define AUX_TIMER2_CH3EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 -#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 -#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 -#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 -#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 -#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 -#define AUX_TIMER2_CH3EVCFG_CCACT_DIS 0x00000000 +#define AUX_TIMER2_CH3EVCFG_CCACT_W 4 +#define AUX_TIMER2_CH3EVCFG_CCACT_M 0x0000000F +#define AUX_TIMER2_CH3EVCFG_CCACT_S 0 +#define AUX_TIMER2_CH3EVCFG_CCACT_PULSE_ON_CMP 0x0000000F +#define AUX_TIMER2_CH3EVCFG_CCACT_TGL_ON_CMP 0x0000000E +#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CMP 0x0000000D +#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_CMP 0x0000000C +#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B +#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A +#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CAPT 0x00000009 +#define AUX_TIMER2_CH3EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 +#define AUX_TIMER2_CH3EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 +#define AUX_TIMER2_CH3EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 +#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 +#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 +#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 +#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 +#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 +#define AUX_TIMER2_CH3EVCFG_CCACT_DIS 0x00000000 //***************************************************************************** // @@ -2358,71 +2358,71 @@ // AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 // AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 // AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_W 6 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_M 0x0000007E -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_S 1 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_NO_EVENT 0x0000007E -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_COMPB 0x0000005E -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_COMPA 0x0000005C -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_EV 0x00000056 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_ACLK_REF 0x00000054 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_PWR_DWN 0x0000004E -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_SCLK_LF 0x0000004C -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MANUAL_EV 0x00000040 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO31 0x0000003E -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO30 0x0000003C -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO29 0x0000003A -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO28 0x00000038 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO27 0x00000036 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO26 0x00000034 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO25 0x00000032 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO24 0x00000030 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO23 0x0000002E -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO22 0x0000002C -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO21 0x0000002A -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO20 0x00000028 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO19 0x00000026 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO18 0x00000024 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO17 0x00000022 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO16 0x00000020 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO15 0x0000001E -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO14 0x0000001C -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO13 0x0000001A -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO12 0x00000018 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO11 0x00000016 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO10 0x00000014 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO9 0x00000012 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO8 0x00000010 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO7 0x0000000E -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO6 0x0000000C -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO5 0x0000000A -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO4 0x00000008 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO3 0x00000006 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO2 0x00000004 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO1 0x00000002 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO0 0x00000000 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_W 6 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_M 0x0000007E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_S 1 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_NO_EVENT 0x0000007E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_COMPB 0x0000005E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_COMPA 0x0000005C +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_EV 0x00000056 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_ACLK_REF 0x00000054 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_PWR_DWN 0x0000004E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_SCLK_LF 0x0000004C +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MANUAL_EV 0x00000040 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO31 0x0000003E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO30 0x0000003C +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO29 0x0000003A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO28 0x00000038 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO27 0x00000036 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO26 0x00000034 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO25 0x00000032 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO24 0x00000030 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO23 0x0000002E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO22 0x0000002C +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO21 0x0000002A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO20 0x00000028 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO19 0x00000026 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO18 0x00000024 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO17 0x00000022 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO16 0x00000020 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO15 0x0000001E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO14 0x0000001C +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO13 0x0000001A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO12 0x00000018 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO11 0x00000016 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO10 0x00000014 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO9 0x00000012 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO8 0x00000010 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO7 0x0000000E +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO6 0x0000000C +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO5 0x0000000A +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO4 0x00000008 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO3 0x00000006 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO2 0x00000004 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO1 0x00000002 +#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO0 0x00000000 // Field: [0] EDGE // @@ -2433,12 +2433,12 @@ // ENUMs: // RISING Capture CNTR.VALUE at rising edge of CAPT_SRC. // FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC. -#define AUX_TIMER2_CH3CCFG_EDGE 0x00000001 -#define AUX_TIMER2_CH3CCFG_EDGE_BITN 0 -#define AUX_TIMER2_CH3CCFG_EDGE_M 0x00000001 -#define AUX_TIMER2_CH3CCFG_EDGE_S 0 -#define AUX_TIMER2_CH3CCFG_EDGE_RISING 0x00000001 -#define AUX_TIMER2_CH3CCFG_EDGE_FALLING 0x00000000 +#define AUX_TIMER2_CH3CCFG_EDGE 0x00000001 +#define AUX_TIMER2_CH3CCFG_EDGE_BITN 0 +#define AUX_TIMER2_CH3CCFG_EDGE_M 0x00000001 +#define AUX_TIMER2_CH3CCFG_EDGE_S 0 +#define AUX_TIMER2_CH3CCFG_EDGE_RISING 0x00000001 +#define AUX_TIMER2_CH3CCFG_EDGE_FALLING 0x00000000 //***************************************************************************** // @@ -2460,9 +2460,9 @@ // When CH3EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the // width of the low or high phase of the selected signal. This is specified by // CH3CCFG.EDGE and CH3CCFG.CAPT_SRC. -#define AUX_TIMER2_CH3PCC_VALUE_W 16 -#define AUX_TIMER2_CH3PCC_VALUE_M 0x0000FFFF -#define AUX_TIMER2_CH3PCC_VALUE_S 0 +#define AUX_TIMER2_CH3PCC_VALUE_W 16 +#define AUX_TIMER2_CH3PCC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH3PCC_VALUE_S 0 //***************************************************************************** // @@ -2483,9 +2483,8 @@ // The current counter value is stored in VALUE when a capture event occurs. // CH3EVCFG.CCACT determines if VALUE is a signal period or a regular capture // value. -#define AUX_TIMER2_CH3CC_VALUE_W 16 -#define AUX_TIMER2_CH3CC_VALUE_M 0x0000FFFF -#define AUX_TIMER2_CH3CC_VALUE_S 0 - +#define AUX_TIMER2_CH3CC_VALUE_W 16 +#define AUX_TIMER2_CH3CC_VALUE_M 0x0000FFFF +#define AUX_TIMER2_CH3CC_VALUE_S 0 #endif // __AUX_TIMER2__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg.h index fc5a834..da5e527 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_ccfg_h -* Revised: 2018-10-19 08:48:09 +0200 (Fri, 19 Oct 2018) -* Revision: 52957 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_ccfg_h + * Revised: 2018-10-19 08:48:09 +0200 (Fri, 19 Oct 2018) + * Revision: 52957 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CCFG_H__ #define __HW_CCFG_H__ @@ -44,70 +44,70 @@ // //***************************************************************************** // Extern LF clock configuration -#define CCFG_O_EXT_LF_CLK 0x00001FA8 +#define CCFG_O_EXT_LF_CLK 0x00001FA8 // Mode Configuration 1 -#define CCFG_O_MODE_CONF_1 0x00001FAC +#define CCFG_O_MODE_CONF_1 0x00001FAC // CCFG Size and Disable Flags -#define CCFG_O_SIZE_AND_DIS_FLAGS 0x00001FB0 +#define CCFG_O_SIZE_AND_DIS_FLAGS 0x00001FB0 // Mode Configuration 0 -#define CCFG_O_MODE_CONF 0x00001FB4 +#define CCFG_O_MODE_CONF 0x00001FB4 // Voltage Load 0 -#define CCFG_O_VOLT_LOAD_0 0x00001FB8 +#define CCFG_O_VOLT_LOAD_0 0x00001FB8 // Voltage Load 1 -#define CCFG_O_VOLT_LOAD_1 0x00001FBC +#define CCFG_O_VOLT_LOAD_1 0x00001FBC // Real Time Clock Offset -#define CCFG_O_RTC_OFFSET 0x00001FC0 +#define CCFG_O_RTC_OFFSET 0x00001FC0 // Frequency Offset -#define CCFG_O_FREQ_OFFSET 0x00001FC4 +#define CCFG_O_FREQ_OFFSET 0x00001FC4 // IEEE MAC Address 0 -#define CCFG_O_IEEE_MAC_0 0x00001FC8 +#define CCFG_O_IEEE_MAC_0 0x00001FC8 // IEEE MAC Address 1 -#define CCFG_O_IEEE_MAC_1 0x00001FCC +#define CCFG_O_IEEE_MAC_1 0x00001FCC // IEEE BLE Address 0 -#define CCFG_O_IEEE_BLE_0 0x00001FD0 +#define CCFG_O_IEEE_BLE_0 0x00001FD0 // IEEE BLE Address 1 -#define CCFG_O_IEEE_BLE_1 0x00001FD4 +#define CCFG_O_IEEE_BLE_1 0x00001FD4 // Bootloader Configuration -#define CCFG_O_BL_CONFIG 0x00001FD8 +#define CCFG_O_BL_CONFIG 0x00001FD8 // Erase Configuration -#define CCFG_O_ERASE_CONF 0x00001FDC +#define CCFG_O_ERASE_CONF 0x00001FDC // TI Options -#define CCFG_O_CCFG_TI_OPTIONS 0x00001FE0 +#define CCFG_O_CCFG_TI_OPTIONS 0x00001FE0 // Test Access Points Enable 0 -#define CCFG_O_CCFG_TAP_DAP_0 0x00001FE4 +#define CCFG_O_CCFG_TAP_DAP_0 0x00001FE4 // Test Access Points Enable 1 -#define CCFG_O_CCFG_TAP_DAP_1 0x00001FE8 +#define CCFG_O_CCFG_TAP_DAP_1 0x00001FE8 // Image Valid -#define CCFG_O_IMAGE_VALID_CONF 0x00001FEC +#define CCFG_O_IMAGE_VALID_CONF 0x00001FEC // Protect Sectors 0-31 -#define CCFG_O_CCFG_PROT_31_0 0x00001FF0 +#define CCFG_O_CCFG_PROT_31_0 0x00001FF0 // Protect Sectors 32-63 -#define CCFG_O_CCFG_PROT_63_32 0x00001FF4 +#define CCFG_O_CCFG_PROT_63_32 0x00001FF4 // Protect Sectors 64-95 -#define CCFG_O_CCFG_PROT_95_64 0x00001FF8 +#define CCFG_O_CCFG_PROT_95_64 0x00001FF8 // Protect Sectors 96-127 -#define CCFG_O_CCFG_PROT_127_96 0x00001FFC +#define CCFG_O_CCFG_PROT_127_96 0x00001FFC //***************************************************************************** // @@ -120,9 +120,9 @@ // SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL. The selected DIO // will be marked as reserved by the pin driver (TI-RTOS environment) and hence // not selectable for other usage. -#define CCFG_EXT_LF_CLK_DIO_W 8 -#define CCFG_EXT_LF_CLK_DIO_M 0xFF000000 -#define CCFG_EXT_LF_CLK_DIO_S 24 +#define CCFG_EXT_LF_CLK_DIO_W 8 +#define CCFG_EXT_LF_CLK_DIO_M 0xFF000000 +#define CCFG_EXT_LF_CLK_DIO_S 24 // Field: [23:0] RTC_INCREMENT // @@ -130,9 +130,9 @@ // written to AON_RTC:SUBSECINC.VALUEINC. Defined as follows: // EXT_LF_CLK.RTC_INCREMENT = 2^38/InputClockFrequency in Hertz (e.g.: // RTC_INCREMENT=0x800000 for InputClockFrequency=32768 Hz) -#define CCFG_EXT_LF_CLK_RTC_INCREMENT_W 24 -#define CCFG_EXT_LF_CLK_RTC_INCREMENT_M 0x00FFFFFF -#define CCFG_EXT_LF_CLK_RTC_INCREMENT_S 0 +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_W 24 +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_M 0x00FFFFFF +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_S 0 //***************************************************************************** // @@ -153,9 +153,9 @@ // NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must // be called regularly to apply this field (handled automatically if using TI // RTOS!). -#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_W 4 -#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M 0x00F00000 -#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S 20 +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_W 4 +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M 0x00F00000 +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S 20 // Field: [19] ALT_DCDC_DITHER_EN // @@ -163,10 +163,10 @@ // (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). // 0: Dither disable // 1: Dither enable -#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x00080000 -#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_BITN 19 -#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M 0x00080000 -#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S 19 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x00080000 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_BITN 19 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M 0x00080000 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S 19 // Field: [18:16] ALT_DCDC_IPEAK // @@ -179,35 +179,35 @@ // 4: 47mA // ... // 7: 59mA (max) -#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_W 3 -#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M 0x00070000 -#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S 16 +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_W 3 +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M 0x00070000 +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S 16 // Field: [15:12] DELTA_IBIAS_INIT // // Signed delta value for IBIAS_INIT. Delta value only applies if // SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. // See FCFG1:AMPCOMP_CTRL1.IBIAS_INIT -#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W 4 -#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M 0x0000F000 -#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S 12 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W 4 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M 0x0000F000 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S 12 // Field: [11:8] DELTA_IBIAS_OFFSET // // Signed delta value for IBIAS_OFFSET. Delta value only applies if // SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. // See FCFG1:AMPCOMP_CTRL1.IBIAS_OFFSET -#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W 4 -#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M 0x00000F00 -#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S 8 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W 4 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M 0x00000F00 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S 8 // Field: [7:0] XOSC_MAX_START // // Unsigned value of maximum XOSC startup time (worst case) in units of 100us. // Value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. -#define CCFG_MODE_CONF_1_XOSC_MAX_START_W 8 -#define CCFG_MODE_CONF_1_XOSC_MAX_START_M 0x000000FF -#define CCFG_MODE_CONF_1_XOSC_MAX_START_S 0 +#define CCFG_MODE_CONF_1_XOSC_MAX_START_W 8 +#define CCFG_MODE_CONF_1_XOSC_MAX_START_M 0x000000FF +#define CCFG_MODE_CONF_1_XOSC_MAX_START_S 0 //***************************************************************************** // @@ -217,18 +217,18 @@ // Field: [31:16] SIZE_OF_CCFG // // Total size of CCFG in bytes. -#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_W 16 -#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M 0xFFFF0000 -#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S 16 +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_W 16 +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M 0xFFFF0000 +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S 16 // Field: [15:4] DISABLE_FLAGS // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_W 12 -#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M 0x0000FFF0 -#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S 4 +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_W 12 +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M 0x0000FFF0 +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S 4 // Field: [3] DIS_TCXO // @@ -237,10 +237,10 @@ // 1: TCXO functionality disabled. // Note: // An external TCXO is required if DIS_TCXO = 0. -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x00000008 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_BITN 3 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M 0x00000008 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S 3 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x00000008 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_BITN 3 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M 0x00000008 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S 3 // Field: [2] DIS_GPRAM // @@ -253,10 +253,10 @@ // enabled. // See: // VIMS:CTL.MODE -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x00000004 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_BITN 2 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M 0x00000004 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S 2 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x00000004 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_BITN 2 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M 0x00000004 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S 2 // Field: [1] DIS_ALT_DCDC_SETTING // @@ -271,10 +271,10 @@ // NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must // be called regularly to apply this field (handled automatically if using TI // RTOS!). -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x00000002 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_BITN 1 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M 0x00000002 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S 1 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x00000002 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_BITN 1 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M 0x00000002 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S 1 // Field: [0] DIS_XOSC_OVR // @@ -285,10 +285,10 @@ // MODE_CONF_1.DELTA_IBIAS_INIT // MODE_CONF_1.DELTA_IBIAS_OFFSET // MODE_CONF_1.XOSC_MAX_START -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x00000001 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_BITN 0 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M 0x00000001 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S 0 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x00000001 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_BITN 0 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M 0x00000001 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S 0 //***************************************************************************** // @@ -305,9 +305,9 @@ // 0x0 (0) : Delta = +1 // ... // 0x7 (7) : Delta = +8 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W 4 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M 0xF0000000 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S 28 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W 4 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M 0xF0000000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S 28 // Field: [27] DCDC_RECHARGE // @@ -318,10 +318,10 @@ // NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must // be called regularly to apply this field (handled automatically if using TI // RTOS!). -#define CCFG_MODE_CONF_DCDC_RECHARGE 0x08000000 -#define CCFG_MODE_CONF_DCDC_RECHARGE_BITN 27 -#define CCFG_MODE_CONF_DCDC_RECHARGE_M 0x08000000 -#define CCFG_MODE_CONF_DCDC_RECHARGE_S 27 +#define CCFG_MODE_CONF_DCDC_RECHARGE 0x08000000 +#define CCFG_MODE_CONF_DCDC_RECHARGE_BITN 27 +#define CCFG_MODE_CONF_DCDC_RECHARGE_M 0x08000000 +#define CCFG_MODE_CONF_DCDC_RECHARGE_S 27 // Field: [26] DCDC_ACTIVE // @@ -332,20 +332,20 @@ // NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must // be called regularly to apply this field (handled automatically if using TI // RTOS!). -#define CCFG_MODE_CONF_DCDC_ACTIVE 0x04000000 -#define CCFG_MODE_CONF_DCDC_ACTIVE_BITN 26 -#define CCFG_MODE_CONF_DCDC_ACTIVE_M 0x04000000 -#define CCFG_MODE_CONF_DCDC_ACTIVE_S 26 +#define CCFG_MODE_CONF_DCDC_ACTIVE 0x04000000 +#define CCFG_MODE_CONF_DCDC_ACTIVE_BITN 26 +#define CCFG_MODE_CONF_DCDC_ACTIVE_M 0x04000000 +#define CCFG_MODE_CONF_DCDC_ACTIVE_S 26 // Field: [25] VDDR_EXT_LOAD // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_MODE_CONF_VDDR_EXT_LOAD 0x02000000 -#define CCFG_MODE_CONF_VDDR_EXT_LOAD_BITN 25 -#define CCFG_MODE_CONF_VDDR_EXT_LOAD_M 0x02000000 -#define CCFG_MODE_CONF_VDDR_EXT_LOAD_S 25 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD 0x02000000 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_BITN 25 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_M 0x02000000 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_S 25 // Field: [24] VDDS_BOD_LEVEL // @@ -353,10 +353,10 @@ // 0: VDDS BOD level is 2.0V (necessary for external load mode, or for maximum // PA output power on CC13xx). // 1: VDDS BOD level is 1.8V (or 1.65V for external regulator mode) (default). -#define CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x01000000 -#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_BITN 24 -#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_M 0x01000000 -#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_S 24 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x01000000 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_BITN 24 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_M 0x01000000 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_S 24 // Field: [23:22] SCLK_LF_OPTION // @@ -378,13 +378,13 @@ // trimDevice() xxWare boot function). Standby // power mode is not supported when using this // clock source. -#define CCFG_MODE_CONF_SCLK_LF_OPTION_W 2 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_M 0x00C00000 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_S 22 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF 0x00C00000 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF 0x00800000 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF 0x00400000 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF 0x00000000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_W 2 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_M 0x00C00000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_S 22 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF 0x00C00000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF 0x00800000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF 0x00400000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF 0x00000000 // Field: [21] VDDR_TRIM_SLEEP_TC // @@ -398,20 +398,20 @@ // Delta = max (delta, min(8, floor(62-temp)/8)) // Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is the current // temperature in degrees C. -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x00200000 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_BITN 21 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M 0x00200000 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S 21 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x00200000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_BITN 21 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M 0x00200000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S 21 // Field: [20] RTC_COMP // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_MODE_CONF_RTC_COMP 0x00100000 -#define CCFG_MODE_CONF_RTC_COMP_BITN 20 -#define CCFG_MODE_CONF_RTC_COMP_M 0x00100000 -#define CCFG_MODE_CONF_RTC_COMP_S 20 +#define CCFG_MODE_CONF_RTC_COMP 0x00100000 +#define CCFG_MODE_CONF_RTC_COMP_BITN 20 +#define CCFG_MODE_CONF_RTC_COMP_M 0x00100000 +#define CCFG_MODE_CONF_RTC_COMP_S 20 // Field: [19:18] XOSC_FREQ // @@ -420,12 +420,12 @@ // 24M 24 MHz XOSC_HF // 48M 48 MHz XOSC_HF // HPOSC HPOSC -#define CCFG_MODE_CONF_XOSC_FREQ_W 2 -#define CCFG_MODE_CONF_XOSC_FREQ_M 0x000C0000 -#define CCFG_MODE_CONF_XOSC_FREQ_S 18 -#define CCFG_MODE_CONF_XOSC_FREQ_24M 0x000C0000 -#define CCFG_MODE_CONF_XOSC_FREQ_48M 0x00080000 -#define CCFG_MODE_CONF_XOSC_FREQ_HPOSC 0x00040000 +#define CCFG_MODE_CONF_XOSC_FREQ_W 2 +#define CCFG_MODE_CONF_XOSC_FREQ_M 0x000C0000 +#define CCFG_MODE_CONF_XOSC_FREQ_S 18 +#define CCFG_MODE_CONF_XOSC_FREQ_24M 0x000C0000 +#define CCFG_MODE_CONF_XOSC_FREQ_48M 0x00080000 +#define CCFG_MODE_CONF_XOSC_FREQ_HPOSC 0x00040000 // Field: [17] XOSC_CAP_MOD // @@ -433,28 +433,28 @@ // XOSC_CAPARRAY_DELTA. // 0: Apply cap-array delta // 1: Do not apply cap-array delta (default) -#define CCFG_MODE_CONF_XOSC_CAP_MOD 0x00020000 -#define CCFG_MODE_CONF_XOSC_CAP_MOD_BITN 17 -#define CCFG_MODE_CONF_XOSC_CAP_MOD_M 0x00020000 -#define CCFG_MODE_CONF_XOSC_CAP_MOD_S 17 +#define CCFG_MODE_CONF_XOSC_CAP_MOD 0x00020000 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_BITN 17 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_M 0x00020000 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_S 17 // Field: [16] HF_COMP // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_MODE_CONF_HF_COMP 0x00010000 -#define CCFG_MODE_CONF_HF_COMP_BITN 16 -#define CCFG_MODE_CONF_HF_COMP_M 0x00010000 -#define CCFG_MODE_CONF_HF_COMP_S 16 +#define CCFG_MODE_CONF_HF_COMP 0x00010000 +#define CCFG_MODE_CONF_HF_COMP_BITN 16 +#define CCFG_MODE_CONF_HF_COMP_M 0x00010000 +#define CCFG_MODE_CONF_HF_COMP_S 16 // Field: [15:8] XOSC_CAPARRAY_DELTA // // Signed 8-bit value, directly modifying trimmed XOSC cap-array step value. // Enabled by XOSC_CAP_MOD. -#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W 8 -#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M 0x0000FF00 -#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S 8 +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W 8 +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M 0x0000FF00 +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S 8 // Field: [7:0] VDDR_CAP // @@ -467,9 +467,9 @@ // NOTE! If using the following functions this field must be configured (used // by TI RTOS): // SysCtrlSetRechargeBeforePowerDown() SysCtrlAdjustRechargeAfterPowerDown() -#define CCFG_MODE_CONF_VDDR_CAP_W 8 -#define CCFG_MODE_CONF_VDDR_CAP_M 0x000000FF -#define CCFG_MODE_CONF_VDDR_CAP_S 0 +#define CCFG_MODE_CONF_VDDR_CAP_W 8 +#define CCFG_MODE_CONF_VDDR_CAP_M 0x000000FF +#define CCFG_MODE_CONF_VDDR_CAP_S 0 //***************************************************************************** // @@ -481,36 +481,36 @@ // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_W 8 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M 0xFF000000 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S 24 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M 0xFF000000 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S 24 // Field: [23:16] VDDR_EXT_TP25 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_W 8 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M 0x00FF0000 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S 16 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M 0x00FF0000 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S 16 // Field: [15:8] VDDR_EXT_TP5 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_W 8 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M 0x0000FF00 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M 0x0000FF00 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S 8 // Field: [7:0] VDDR_EXT_TM15 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_W 8 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M 0x000000FF -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S 0 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M 0x000000FF +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S 0 //***************************************************************************** // @@ -522,36 +522,36 @@ // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_W 8 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M 0xFF000000 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S 24 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M 0xFF000000 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S 24 // Field: [23:16] VDDR_EXT_TP105 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_W 8 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M 0x00FF0000 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S 16 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M 0x00FF0000 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S 16 // Field: [15:8] VDDR_EXT_TP85 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_W 8 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M 0x0000FF00 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M 0x0000FF00 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S 8 // Field: [7:0] VDDR_EXT_TP65 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_W 8 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M 0x000000FF -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S 0 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M 0x000000FF +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S 0 //***************************************************************************** // @@ -563,27 +563,27 @@ // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_RTC_OFFSET_RTC_COMP_P0_W 16 -#define CCFG_RTC_OFFSET_RTC_COMP_P0_M 0xFFFF0000 -#define CCFG_RTC_OFFSET_RTC_COMP_P0_S 16 +#define CCFG_RTC_OFFSET_RTC_COMP_P0_W 16 +#define CCFG_RTC_OFFSET_RTC_COMP_P0_M 0xFFFF0000 +#define CCFG_RTC_OFFSET_RTC_COMP_P0_S 16 // Field: [15:8] RTC_COMP_P1 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_RTC_OFFSET_RTC_COMP_P1_W 8 -#define CCFG_RTC_OFFSET_RTC_COMP_P1_M 0x0000FF00 -#define CCFG_RTC_OFFSET_RTC_COMP_P1_S 8 +#define CCFG_RTC_OFFSET_RTC_COMP_P1_W 8 +#define CCFG_RTC_OFFSET_RTC_COMP_P1_M 0x0000FF00 +#define CCFG_RTC_OFFSET_RTC_COMP_P1_S 8 // Field: [7:0] RTC_COMP_P2 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_RTC_OFFSET_RTC_COMP_P2_W 8 -#define CCFG_RTC_OFFSET_RTC_COMP_P2_M 0x000000FF -#define CCFG_RTC_OFFSET_RTC_COMP_P2_S 0 +#define CCFG_RTC_OFFSET_RTC_COMP_P2_W 8 +#define CCFG_RTC_OFFSET_RTC_COMP_P2_M 0x000000FF +#define CCFG_RTC_OFFSET_RTC_COMP_P2_S 0 //***************************************************************************** // @@ -595,27 +595,27 @@ // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_FREQ_OFFSET_HF_COMP_P0_W 16 -#define CCFG_FREQ_OFFSET_HF_COMP_P0_M 0xFFFF0000 -#define CCFG_FREQ_OFFSET_HF_COMP_P0_S 16 +#define CCFG_FREQ_OFFSET_HF_COMP_P0_W 16 +#define CCFG_FREQ_OFFSET_HF_COMP_P0_M 0xFFFF0000 +#define CCFG_FREQ_OFFSET_HF_COMP_P0_S 16 // Field: [15:8] HF_COMP_P1 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_FREQ_OFFSET_HF_COMP_P1_W 8 -#define CCFG_FREQ_OFFSET_HF_COMP_P1_M 0x0000FF00 -#define CCFG_FREQ_OFFSET_HF_COMP_P1_S 8 +#define CCFG_FREQ_OFFSET_HF_COMP_P1_W 8 +#define CCFG_FREQ_OFFSET_HF_COMP_P1_M 0x0000FF00 +#define CCFG_FREQ_OFFSET_HF_COMP_P1_S 8 // Field: [7:0] HF_COMP_P2 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_FREQ_OFFSET_HF_COMP_P2_W 8 -#define CCFG_FREQ_OFFSET_HF_COMP_P2_M 0x000000FF -#define CCFG_FREQ_OFFSET_HF_COMP_P2_S 0 +#define CCFG_FREQ_OFFSET_HF_COMP_P2_W 8 +#define CCFG_FREQ_OFFSET_HF_COMP_P2_M 0x000000FF +#define CCFG_FREQ_OFFSET_HF_COMP_P2_S 0 //***************************************************************************** // @@ -627,9 +627,9 @@ // Bits[31:0] of the 64-bits custom IEEE MAC address. // If different from 0xFFFFFFFF then the value of this field is applied; // otherwise use value from FCFG. -#define CCFG_IEEE_MAC_0_ADDR_W 32 -#define CCFG_IEEE_MAC_0_ADDR_M 0xFFFFFFFF -#define CCFG_IEEE_MAC_0_ADDR_S 0 +#define CCFG_IEEE_MAC_0_ADDR_W 32 +#define CCFG_IEEE_MAC_0_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_MAC_0_ADDR_S 0 //***************************************************************************** // @@ -641,9 +641,9 @@ // Bits[63:32] of the 64-bits custom IEEE MAC address. // If different from 0xFFFFFFFF then the value of this field is applied; // otherwise use value from FCFG. -#define CCFG_IEEE_MAC_1_ADDR_W 32 -#define CCFG_IEEE_MAC_1_ADDR_M 0xFFFFFFFF -#define CCFG_IEEE_MAC_1_ADDR_S 0 +#define CCFG_IEEE_MAC_1_ADDR_W 32 +#define CCFG_IEEE_MAC_1_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_MAC_1_ADDR_S 0 //***************************************************************************** // @@ -655,9 +655,9 @@ // Bits[31:0] of the 64-bits custom IEEE BLE address. // If different from 0xFFFFFFFF then the value of this field is applied; // otherwise use value from FCFG. -#define CCFG_IEEE_BLE_0_ADDR_W 32 -#define CCFG_IEEE_BLE_0_ADDR_M 0xFFFFFFFF -#define CCFG_IEEE_BLE_0_ADDR_S 0 +#define CCFG_IEEE_BLE_0_ADDR_W 32 +#define CCFG_IEEE_BLE_0_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_BLE_0_ADDR_S 0 //***************************************************************************** // @@ -669,9 +669,9 @@ // Bits[63:32] of the 64-bits custom IEEE BLE address. // If different from 0xFFFFFFFF then the value of this field is applied; // otherwise use value from FCFG. -#define CCFG_IEEE_BLE_1_ADDR_W 32 -#define CCFG_IEEE_BLE_1_ADDR_M 0xFFFFFFFF -#define CCFG_IEEE_BLE_1_ADDR_S 0 +#define CCFG_IEEE_BLE_1_ADDR_W 32 +#define CCFG_IEEE_BLE_1_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_BLE_1_ADDR_S 0 //***************************************************************************** // @@ -685,9 +685,9 @@ // conditions for boot loader backdoor are met). // 0xC5: Boot loader is enabled. // Any other value: Boot loader is disabled. -#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_W 8 -#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M 0xFF000000 -#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S 24 +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_W 8 +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M 0xFF000000 +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S 24 // Field: [16] BL_LEVEL // @@ -695,18 +695,18 @@ // loader backdoor is enabled by the BL_ENABLE field. // 0: Active low. // 1: Active high. -#define CCFG_BL_CONFIG_BL_LEVEL 0x00010000 -#define CCFG_BL_CONFIG_BL_LEVEL_BITN 16 -#define CCFG_BL_CONFIG_BL_LEVEL_M 0x00010000 -#define CCFG_BL_CONFIG_BL_LEVEL_S 16 +#define CCFG_BL_CONFIG_BL_LEVEL 0x00010000 +#define CCFG_BL_CONFIG_BL_LEVEL_BITN 16 +#define CCFG_BL_CONFIG_BL_LEVEL_M 0x00010000 +#define CCFG_BL_CONFIG_BL_LEVEL_S 16 // Field: [15:8] BL_PIN_NUMBER // // DIO number that is level checked if the boot loader backdoor is enabled by // the BL_ENABLE field. -#define CCFG_BL_CONFIG_BL_PIN_NUMBER_W 8 -#define CCFG_BL_CONFIG_BL_PIN_NUMBER_M 0x0000FF00 -#define CCFG_BL_CONFIG_BL_PIN_NUMBER_S 8 +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_W 8 +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_M 0x0000FF00 +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_S 8 // Field: [7:0] BL_ENABLE // @@ -716,9 +716,9 @@ // // NOTE! Boot loader must be enabled (see BOOTLOADER_ENABLE) if boot loader // backdoor is enabled. -#define CCFG_BL_CONFIG_BL_ENABLE_W 8 -#define CCFG_BL_CONFIG_BL_ENABLE_M 0x000000FF -#define CCFG_BL_CONFIG_BL_ENABLE_S 0 +#define CCFG_BL_CONFIG_BL_ENABLE_W 8 +#define CCFG_BL_CONFIG_BL_ENABLE_M 0x000000FF +#define CCFG_BL_CONFIG_BL_ENABLE_S 0 //***************************************************************************** // @@ -735,10 +735,10 @@ // 0: Disable. Any chip erase request detected during boot will be ignored. // 1: Enable. Any chip erase request detected during boot will be performed by // the boot FW. -#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x00000100 -#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_BITN 8 -#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M 0x00000100 -#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S 8 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x00000100 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_BITN 8 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M 0x00000100 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S 8 // Field: [0] BANK_ERASE_DIS_N // @@ -749,10 +749,10 @@ // protected by write protect configuration bits in CCFG. // 0: Disable the boot loader bank erase function. // 1: Enable the boot loader bank erase function. -#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x00000001 -#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_BITN 0 -#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M 0x00000001 -#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S 0 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x00000001 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_BITN 0 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M 0x00000001 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S 0 //***************************************************************************** // @@ -766,9 +766,9 @@ // option with the unlock code. // All other values: Disable the functionality of unlocking the TI FA option // with the unlock code. -#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_W 8 -#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M 0x000000FF -#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S 0 +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_W 8 +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M 0x000000FF +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S 0 //***************************************************************************** // @@ -782,9 +782,9 @@ // boot FW. // Any other value: Main CPU DAP access will remain disabled out of // power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M 0x00FF0000 -#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S 16 +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M 0x00FF0000 +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S 16 // Field: [15:8] PWRPROF_TAP_ENABLE // @@ -793,9 +793,9 @@ // FW if enabled by corresponding configuration value in FCFG1 defined by TI. // Any other value: PWRPROF TAP access will remain disabled out of // power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_M 0x0000FF00 -#define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_S 8 +#define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_M 0x0000FF00 +#define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_S 8 // Field: [7:0] TEST_TAP_ENABLE // @@ -804,9 +804,9 @@ // if enabled by corresponding configuration value in FCFG1 defined by TI. // Any other value: TEST TAP access will remain disabled out of // power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M 0x000000FF -#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S 0 +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M 0x000000FF +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S 0 //***************************************************************************** // @@ -820,9 +820,9 @@ // FW if enabled by corresponding configuration value in FCFG1 defined by TI. // Any other value: PBIST2 TAP access will remain disabled out of // power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M 0x00FF0000 -#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S 16 +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M 0x00FF0000 +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S 16 // Field: [15:8] PBIST1_TAP_ENABLE // @@ -831,9 +831,9 @@ // FW if enabled by corresponding configuration value in FCFG1 defined by TI. // Any other value: PBIST1 TAP access will remain disabled out of // power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M 0x0000FF00 -#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S 8 +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M 0x0000FF00 +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S 8 // Field: [7:0] AON_TAP_ENABLE // @@ -842,9 +842,9 @@ // if enabled by corresponding configuration value in FCFG1 defined by TI. // Any other value: AON TAP access will remain disabled out of // power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_M 0x000000FF -#define CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_S 0 +#define CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_M 0x000000FF +#define CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_S 0 //***************************************************************************** // @@ -858,9 +858,9 @@ // image. // Any illegal vector table start address value will force the boot FW in ROM // to transfer control to the serial boot loader in ROM. -#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_W 32 -#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_M 0xFFFFFFFF -#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_S 0 +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_W 32 +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_M 0xFFFFFFFF +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_S 0 //***************************************************************************** // @@ -870,258 +870,258 @@ // Field: [31] WRT_PROT_SEC_31 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31 0x80000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_BITN 31 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_M 0x80000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_S 31 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31 0x80000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_BITN 31 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_M 0x80000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_S 31 // Field: [30] WRT_PROT_SEC_30 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30 0x40000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_BITN 30 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_M 0x40000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_S 30 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30 0x40000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_BITN 30 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_M 0x40000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_S 30 // Field: [29] WRT_PROT_SEC_29 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29 0x20000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_BITN 29 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_M 0x20000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_S 29 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29 0x20000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_BITN 29 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_M 0x20000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_S 29 // Field: [28] WRT_PROT_SEC_28 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28 0x10000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_BITN 28 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_M 0x10000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_S 28 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28 0x10000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_BITN 28 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_M 0x10000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_S 28 // Field: [27] WRT_PROT_SEC_27 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27 0x08000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_BITN 27 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_M 0x08000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_S 27 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27 0x08000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_BITN 27 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_M 0x08000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_S 27 // Field: [26] WRT_PROT_SEC_26 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26 0x04000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_BITN 26 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_M 0x04000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_S 26 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26 0x04000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_BITN 26 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_M 0x04000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_S 26 // Field: [25] WRT_PROT_SEC_25 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25 0x02000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_BITN 25 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_M 0x02000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_S 25 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25 0x02000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_BITN 25 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_M 0x02000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_S 25 // Field: [24] WRT_PROT_SEC_24 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24 0x01000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_BITN 24 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_M 0x01000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_S 24 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24 0x01000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_BITN 24 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_M 0x01000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_S 24 // Field: [23] WRT_PROT_SEC_23 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23 0x00800000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_BITN 23 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_M 0x00800000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_S 23 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23 0x00800000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_BITN 23 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_M 0x00800000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_S 23 // Field: [22] WRT_PROT_SEC_22 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22 0x00400000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_BITN 22 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_M 0x00400000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_S 22 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22 0x00400000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_BITN 22 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_M 0x00400000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_S 22 // Field: [21] WRT_PROT_SEC_21 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21 0x00200000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_BITN 21 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_M 0x00200000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_S 21 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21 0x00200000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_BITN 21 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_M 0x00200000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_S 21 // Field: [20] WRT_PROT_SEC_20 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20 0x00100000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_BITN 20 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_M 0x00100000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_S 20 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20 0x00100000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_BITN 20 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_M 0x00100000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_S 20 // Field: [19] WRT_PROT_SEC_19 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19 0x00080000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_BITN 19 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_M 0x00080000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_S 19 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19 0x00080000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_BITN 19 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_M 0x00080000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_S 19 // Field: [18] WRT_PROT_SEC_18 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18 0x00040000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_BITN 18 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_M 0x00040000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_S 18 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18 0x00040000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_BITN 18 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_M 0x00040000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_S 18 // Field: [17] WRT_PROT_SEC_17 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17 0x00020000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_BITN 17 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_M 0x00020000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_S 17 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17 0x00020000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_BITN 17 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_M 0x00020000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_S 17 // Field: [16] WRT_PROT_SEC_16 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16 0x00010000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_BITN 16 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_M 0x00010000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_S 16 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16 0x00010000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_BITN 16 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_M 0x00010000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_S 16 // Field: [15] WRT_PROT_SEC_15 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15 0x00008000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_BITN 15 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_M 0x00008000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_S 15 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15 0x00008000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_BITN 15 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_M 0x00008000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_S 15 // Field: [14] WRT_PROT_SEC_14 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14 0x00004000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_BITN 14 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_M 0x00004000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_S 14 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14 0x00004000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_BITN 14 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_M 0x00004000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_S 14 // Field: [13] WRT_PROT_SEC_13 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13 0x00002000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_BITN 13 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_M 0x00002000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_S 13 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13 0x00002000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_BITN 13 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_M 0x00002000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_S 13 // Field: [12] WRT_PROT_SEC_12 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12 0x00001000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_BITN 12 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_M 0x00001000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_S 12 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12 0x00001000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_BITN 12 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_M 0x00001000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_S 12 // Field: [11] WRT_PROT_SEC_11 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11 0x00000800 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_BITN 11 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_M 0x00000800 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_S 11 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11 0x00000800 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_BITN 11 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_M 0x00000800 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_S 11 // Field: [10] WRT_PROT_SEC_10 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10 0x00000400 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_BITN 10 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_M 0x00000400 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_S 10 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10 0x00000400 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_BITN 10 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_M 0x00000400 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_S 10 // Field: [9] WRT_PROT_SEC_9 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9 0x00000200 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_BITN 9 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_M 0x00000200 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_S 9 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9 0x00000200 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_BITN 9 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_M 0x00000200 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_S 9 // Field: [8] WRT_PROT_SEC_8 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8 0x00000100 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_BITN 8 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_M 0x00000100 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_S 8 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8 0x00000100 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_BITN 8 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_M 0x00000100 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_S 8 // Field: [7] WRT_PROT_SEC_7 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7 0x00000080 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_BITN 7 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_M 0x00000080 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_S 7 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7 0x00000080 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_BITN 7 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_M 0x00000080 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_S 7 // Field: [6] WRT_PROT_SEC_6 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6 0x00000040 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_BITN 6 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_M 0x00000040 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_S 6 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6 0x00000040 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_BITN 6 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_M 0x00000040 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_S 6 // Field: [5] WRT_PROT_SEC_5 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5 0x00000020 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_BITN 5 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_M 0x00000020 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_S 5 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5 0x00000020 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_BITN 5 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_M 0x00000020 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_S 5 // Field: [4] WRT_PROT_SEC_4 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4 0x00000010 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_BITN 4 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_M 0x00000010 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_S 4 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4 0x00000010 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_BITN 4 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_M 0x00000010 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_S 4 // Field: [3] WRT_PROT_SEC_3 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3 0x00000008 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_BITN 3 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_M 0x00000008 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_S 3 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3 0x00000008 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_BITN 3 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_M 0x00000008 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_S 3 // Field: [2] WRT_PROT_SEC_2 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2 0x00000004 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_BITN 2 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_M 0x00000004 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_S 2 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2 0x00000004 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_BITN 2 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_M 0x00000004 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_S 2 // Field: [1] WRT_PROT_SEC_1 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1 0x00000002 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_BITN 1 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_M 0x00000002 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_S 1 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1 0x00000002 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_BITN 1 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_M 0x00000002 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_S 1 // Field: [0] WRT_PROT_SEC_0 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0 0x00000001 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_BITN 0 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_M 0x00000001 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_S 0 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0 0x00000001 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_BITN 0 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_M 0x00000001 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_S 0 //***************************************************************************** // @@ -1131,258 +1131,258 @@ // Field: [31] WRT_PROT_SEC_63 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63 0x80000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_BITN 31 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_M 0x80000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_S 31 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63 0x80000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_BITN 31 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_M 0x80000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_S 31 // Field: [30] WRT_PROT_SEC_62 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62 0x40000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_BITN 30 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_M 0x40000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_S 30 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62 0x40000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_BITN 30 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_M 0x40000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_S 30 // Field: [29] WRT_PROT_SEC_61 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61 0x20000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_BITN 29 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_M 0x20000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_S 29 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61 0x20000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_BITN 29 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_M 0x20000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_S 29 // Field: [28] WRT_PROT_SEC_60 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60 0x10000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_BITN 28 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_M 0x10000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_S 28 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60 0x10000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_BITN 28 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_M 0x10000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_S 28 // Field: [27] WRT_PROT_SEC_59 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59 0x08000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_BITN 27 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_M 0x08000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_S 27 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59 0x08000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_BITN 27 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_M 0x08000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_S 27 // Field: [26] WRT_PROT_SEC_58 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58 0x04000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_BITN 26 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_M 0x04000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_S 26 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58 0x04000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_BITN 26 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_M 0x04000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_S 26 // Field: [25] WRT_PROT_SEC_57 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57 0x02000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_BITN 25 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_M 0x02000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_S 25 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57 0x02000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_BITN 25 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_M 0x02000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_S 25 // Field: [24] WRT_PROT_SEC_56 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56 0x01000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_BITN 24 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_M 0x01000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_S 24 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56 0x01000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_BITN 24 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_M 0x01000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_S 24 // Field: [23] WRT_PROT_SEC_55 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55 0x00800000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_BITN 23 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_M 0x00800000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_S 23 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55 0x00800000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_BITN 23 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_M 0x00800000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_S 23 // Field: [22] WRT_PROT_SEC_54 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54 0x00400000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_BITN 22 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_M 0x00400000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_S 22 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54 0x00400000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_BITN 22 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_M 0x00400000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_S 22 // Field: [21] WRT_PROT_SEC_53 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53 0x00200000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_BITN 21 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_M 0x00200000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_S 21 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53 0x00200000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_BITN 21 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_M 0x00200000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_S 21 // Field: [20] WRT_PROT_SEC_52 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52 0x00100000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_BITN 20 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_M 0x00100000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_S 20 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52 0x00100000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_BITN 20 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_M 0x00100000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_S 20 // Field: [19] WRT_PROT_SEC_51 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51 0x00080000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_BITN 19 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_M 0x00080000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_S 19 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51 0x00080000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_BITN 19 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_M 0x00080000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_S 19 // Field: [18] WRT_PROT_SEC_50 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50 0x00040000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_BITN 18 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_M 0x00040000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_S 18 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50 0x00040000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_BITN 18 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_M 0x00040000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_S 18 // Field: [17] WRT_PROT_SEC_49 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49 0x00020000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_BITN 17 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_M 0x00020000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_S 17 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49 0x00020000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_BITN 17 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_M 0x00020000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_S 17 // Field: [16] WRT_PROT_SEC_48 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48 0x00010000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_BITN 16 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_M 0x00010000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_S 16 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48 0x00010000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_BITN 16 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_M 0x00010000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_S 16 // Field: [15] WRT_PROT_SEC_47 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47 0x00008000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_BITN 15 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_M 0x00008000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_S 15 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47 0x00008000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_BITN 15 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_M 0x00008000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_S 15 // Field: [14] WRT_PROT_SEC_46 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46 0x00004000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_BITN 14 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_M 0x00004000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_S 14 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46 0x00004000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_BITN 14 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_M 0x00004000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_S 14 // Field: [13] WRT_PROT_SEC_45 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45 0x00002000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_BITN 13 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_M 0x00002000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_S 13 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45 0x00002000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_BITN 13 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_M 0x00002000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_S 13 // Field: [12] WRT_PROT_SEC_44 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44 0x00001000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_BITN 12 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_M 0x00001000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_S 12 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44 0x00001000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_BITN 12 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_M 0x00001000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_S 12 // Field: [11] WRT_PROT_SEC_43 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43 0x00000800 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_BITN 11 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_M 0x00000800 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_S 11 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43 0x00000800 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_BITN 11 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_M 0x00000800 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_S 11 // Field: [10] WRT_PROT_SEC_42 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42 0x00000400 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_BITN 10 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_M 0x00000400 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_S 10 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42 0x00000400 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_BITN 10 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_M 0x00000400 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_S 10 // Field: [9] WRT_PROT_SEC_41 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41 0x00000200 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_BITN 9 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_M 0x00000200 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_S 9 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41 0x00000200 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_BITN 9 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_M 0x00000200 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_S 9 // Field: [8] WRT_PROT_SEC_40 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40 0x00000100 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_BITN 8 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_M 0x00000100 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_S 8 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40 0x00000100 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_BITN 8 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_M 0x00000100 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_S 8 // Field: [7] WRT_PROT_SEC_39 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39 0x00000080 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_BITN 7 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_M 0x00000080 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_S 7 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39 0x00000080 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_BITN 7 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_M 0x00000080 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_S 7 // Field: [6] WRT_PROT_SEC_38 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38 0x00000040 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_BITN 6 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_M 0x00000040 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_S 6 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38 0x00000040 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_BITN 6 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_M 0x00000040 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_S 6 // Field: [5] WRT_PROT_SEC_37 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37 0x00000020 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_BITN 5 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_M 0x00000020 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_S 5 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37 0x00000020 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_BITN 5 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_M 0x00000020 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_S 5 // Field: [4] WRT_PROT_SEC_36 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36 0x00000010 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_BITN 4 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_M 0x00000010 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_S 4 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36 0x00000010 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_BITN 4 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_M 0x00000010 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_S 4 // Field: [3] WRT_PROT_SEC_35 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35 0x00000008 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_BITN 3 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_M 0x00000008 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_S 3 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35 0x00000008 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_BITN 3 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_M 0x00000008 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_S 3 // Field: [2] WRT_PROT_SEC_34 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34 0x00000004 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_BITN 2 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_M 0x00000004 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_S 2 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34 0x00000004 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_BITN 2 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_M 0x00000004 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_S 2 // Field: [1] WRT_PROT_SEC_33 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33 0x00000002 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_BITN 1 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_M 0x00000002 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_S 1 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33 0x00000002 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_BITN 1 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_M 0x00000002 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_S 1 // Field: [0] WRT_PROT_SEC_32 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32 0x00000001 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_BITN 0 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_M 0x00000001 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_S 0 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32 0x00000001 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_BITN 0 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_M 0x00000001 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_S 0 //***************************************************************************** // @@ -1392,258 +1392,258 @@ // Field: [31] WRT_PROT_SEC_95 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95 0x80000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_BITN 31 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_M 0x80000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_S 31 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95 0x80000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_BITN 31 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_M 0x80000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_S 31 // Field: [30] WRT_PROT_SEC_94 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94 0x40000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_BITN 30 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_M 0x40000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_S 30 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94 0x40000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_BITN 30 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_M 0x40000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_S 30 // Field: [29] WRT_PROT_SEC_93 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93 0x20000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_BITN 29 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_M 0x20000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_S 29 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93 0x20000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_BITN 29 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_M 0x20000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_S 29 // Field: [28] WRT_PROT_SEC_92 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92 0x10000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_BITN 28 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_M 0x10000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_S 28 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92 0x10000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_BITN 28 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_M 0x10000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_S 28 // Field: [27] WRT_PROT_SEC_91 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91 0x08000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_BITN 27 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_M 0x08000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_S 27 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91 0x08000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_BITN 27 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_M 0x08000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_S 27 // Field: [26] WRT_PROT_SEC_90 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90 0x04000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_BITN 26 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_M 0x04000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_S 26 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90 0x04000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_BITN 26 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_M 0x04000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_S 26 // Field: [25] WRT_PROT_SEC_89 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89 0x02000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_BITN 25 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_M 0x02000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_S 25 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89 0x02000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_BITN 25 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_M 0x02000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_S 25 // Field: [24] WRT_PROT_SEC_88 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88 0x01000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_BITN 24 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_M 0x01000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_S 24 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88 0x01000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_BITN 24 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_M 0x01000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_S 24 // Field: [23] WRT_PROT_SEC_87 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87 0x00800000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_BITN 23 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_M 0x00800000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_S 23 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87 0x00800000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_BITN 23 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_M 0x00800000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_S 23 // Field: [22] WRT_PROT_SEC_86 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86 0x00400000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_BITN 22 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_M 0x00400000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_S 22 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86 0x00400000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_BITN 22 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_M 0x00400000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_S 22 // Field: [21] WRT_PROT_SEC_85 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85 0x00200000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_BITN 21 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_M 0x00200000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_S 21 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85 0x00200000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_BITN 21 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_M 0x00200000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_S 21 // Field: [20] WRT_PROT_SEC_84 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84 0x00100000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_BITN 20 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_M 0x00100000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_S 20 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84 0x00100000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_BITN 20 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_M 0x00100000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_S 20 // Field: [19] WRT_PROT_SEC_83 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83 0x00080000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_BITN 19 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_M 0x00080000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_S 19 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83 0x00080000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_BITN 19 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_M 0x00080000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_S 19 // Field: [18] WRT_PROT_SEC_82 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82 0x00040000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_BITN 18 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_M 0x00040000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_S 18 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82 0x00040000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_BITN 18 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_M 0x00040000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_S 18 // Field: [17] WRT_PROT_SEC_81 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81 0x00020000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_BITN 17 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_M 0x00020000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_S 17 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81 0x00020000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_BITN 17 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_M 0x00020000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_S 17 // Field: [16] WRT_PROT_SEC_80 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80 0x00010000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_BITN 16 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_M 0x00010000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_S 16 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80 0x00010000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_BITN 16 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_M 0x00010000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_S 16 // Field: [15] WRT_PROT_SEC_79 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79 0x00008000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_BITN 15 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_M 0x00008000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_S 15 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79 0x00008000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_BITN 15 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_M 0x00008000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_S 15 // Field: [14] WRT_PROT_SEC_78 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78 0x00004000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_BITN 14 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_M 0x00004000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_S 14 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78 0x00004000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_BITN 14 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_M 0x00004000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_S 14 // Field: [13] WRT_PROT_SEC_77 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77 0x00002000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_BITN 13 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_M 0x00002000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_S 13 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77 0x00002000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_BITN 13 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_M 0x00002000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_S 13 // Field: [12] WRT_PROT_SEC_76 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76 0x00001000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_BITN 12 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_M 0x00001000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_S 12 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76 0x00001000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_BITN 12 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_M 0x00001000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_S 12 // Field: [11] WRT_PROT_SEC_75 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75 0x00000800 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_BITN 11 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_M 0x00000800 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_S 11 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75 0x00000800 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_BITN 11 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_M 0x00000800 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_S 11 // Field: [10] WRT_PROT_SEC_74 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74 0x00000400 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_BITN 10 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_M 0x00000400 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_S 10 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74 0x00000400 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_BITN 10 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_M 0x00000400 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_S 10 // Field: [9] WRT_PROT_SEC_73 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73 0x00000200 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_BITN 9 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_M 0x00000200 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_S 9 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73 0x00000200 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_BITN 9 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_M 0x00000200 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_S 9 // Field: [8] WRT_PROT_SEC_72 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72 0x00000100 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_BITN 8 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_M 0x00000100 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_S 8 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72 0x00000100 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_BITN 8 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_M 0x00000100 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_S 8 // Field: [7] WRT_PROT_SEC_71 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71 0x00000080 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_BITN 7 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_M 0x00000080 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_S 7 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71 0x00000080 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_BITN 7 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_M 0x00000080 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_S 7 // Field: [6] WRT_PROT_SEC_70 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70 0x00000040 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_BITN 6 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_M 0x00000040 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_S 6 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70 0x00000040 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_BITN 6 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_M 0x00000040 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_S 6 // Field: [5] WRT_PROT_SEC_69 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69 0x00000020 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_BITN 5 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_M 0x00000020 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_S 5 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69 0x00000020 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_BITN 5 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_M 0x00000020 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_S 5 // Field: [4] WRT_PROT_SEC_68 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68 0x00000010 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_BITN 4 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_M 0x00000010 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_S 4 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68 0x00000010 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_BITN 4 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_M 0x00000010 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_S 4 // Field: [3] WRT_PROT_SEC_67 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67 0x00000008 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_BITN 3 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_M 0x00000008 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_S 3 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67 0x00000008 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_BITN 3 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_M 0x00000008 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_S 3 // Field: [2] WRT_PROT_SEC_66 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66 0x00000004 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_BITN 2 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_M 0x00000004 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_S 2 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66 0x00000004 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_BITN 2 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_M 0x00000004 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_S 2 // Field: [1] WRT_PROT_SEC_65 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65 0x00000002 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_BITN 1 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_M 0x00000002 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_S 1 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65 0x00000002 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_BITN 1 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_M 0x00000002 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_S 1 // Field: [0] WRT_PROT_SEC_64 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64 0x00000001 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_BITN 0 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_M 0x00000001 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_S 0 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64 0x00000001 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_BITN 0 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_M 0x00000001 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_S 0 //***************************************************************************** // @@ -1653,258 +1653,257 @@ // Field: [31] WRT_PROT_SEC_127 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127 0x80000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_BITN 31 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_M 0x80000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_S 31 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127 0x80000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_BITN 31 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_M 0x80000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_S 31 // Field: [30] WRT_PROT_SEC_126 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126 0x40000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_BITN 30 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_M 0x40000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_S 30 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126 0x40000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_BITN 30 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_M 0x40000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_S 30 // Field: [29] WRT_PROT_SEC_125 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125 0x20000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_BITN 29 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_M 0x20000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_S 29 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125 0x20000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_BITN 29 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_M 0x20000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_S 29 // Field: [28] WRT_PROT_SEC_124 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124 0x10000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_BITN 28 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_M 0x10000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_S 28 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124 0x10000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_BITN 28 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_M 0x10000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_S 28 // Field: [27] WRT_PROT_SEC_123 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123 0x08000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_BITN 27 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_M 0x08000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_S 27 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123 0x08000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_BITN 27 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_M 0x08000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_S 27 // Field: [26] WRT_PROT_SEC_122 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122 0x04000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_BITN 26 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_M 0x04000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_S 26 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122 0x04000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_BITN 26 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_M 0x04000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_S 26 // Field: [25] WRT_PROT_SEC_121 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121 0x02000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_BITN 25 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_M 0x02000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_S 25 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121 0x02000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_BITN 25 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_M 0x02000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_S 25 // Field: [24] WRT_PROT_SEC_120 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120 0x01000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_BITN 24 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_M 0x01000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_S 24 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120 0x01000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_BITN 24 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_M 0x01000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_S 24 // Field: [23] WRT_PROT_SEC_119 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119 0x00800000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_BITN 23 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_M 0x00800000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_S 23 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119 0x00800000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_BITN 23 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_M 0x00800000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_S 23 // Field: [22] WRT_PROT_SEC_118 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118 0x00400000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_BITN 22 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_M 0x00400000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_S 22 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118 0x00400000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_BITN 22 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_M 0x00400000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_S 22 // Field: [21] WRT_PROT_SEC_117 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117 0x00200000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_BITN 21 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_M 0x00200000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_S 21 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117 0x00200000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_BITN 21 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_M 0x00200000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_S 21 // Field: [20] WRT_PROT_SEC_116 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116 0x00100000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_BITN 20 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_M 0x00100000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_S 20 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116 0x00100000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_BITN 20 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_M 0x00100000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_S 20 // Field: [19] WRT_PROT_SEC_115 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115 0x00080000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_BITN 19 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_M 0x00080000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_S 19 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115 0x00080000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_BITN 19 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_M 0x00080000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_S 19 // Field: [18] WRT_PROT_SEC_114 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114 0x00040000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_BITN 18 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_M 0x00040000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_S 18 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114 0x00040000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_BITN 18 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_M 0x00040000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_S 18 // Field: [17] WRT_PROT_SEC_113 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113 0x00020000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_BITN 17 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_M 0x00020000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_S 17 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113 0x00020000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_BITN 17 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_M 0x00020000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_S 17 // Field: [16] WRT_PROT_SEC_112 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112 0x00010000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_BITN 16 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_M 0x00010000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_S 16 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112 0x00010000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_BITN 16 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_M 0x00010000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_S 16 // Field: [15] WRT_PROT_SEC_111 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111 0x00008000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_BITN 15 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_M 0x00008000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_S 15 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111 0x00008000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_BITN 15 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_M 0x00008000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_S 15 // Field: [14] WRT_PROT_SEC_110 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110 0x00004000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_BITN 14 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_M 0x00004000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_S 14 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110 0x00004000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_BITN 14 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_M 0x00004000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_S 14 // Field: [13] WRT_PROT_SEC_109 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109 0x00002000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_BITN 13 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_M 0x00002000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_S 13 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109 0x00002000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_BITN 13 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_M 0x00002000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_S 13 // Field: [12] WRT_PROT_SEC_108 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108 0x00001000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_BITN 12 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_M 0x00001000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_S 12 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108 0x00001000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_BITN 12 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_M 0x00001000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_S 12 // Field: [11] WRT_PROT_SEC_107 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107 0x00000800 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_BITN 11 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_M 0x00000800 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_S 11 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107 0x00000800 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_BITN 11 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_M 0x00000800 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_S 11 // Field: [10] WRT_PROT_SEC_106 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106 0x00000400 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_BITN 10 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_M 0x00000400 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_S 10 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106 0x00000400 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_BITN 10 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_M 0x00000400 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_S 10 // Field: [9] WRT_PROT_SEC_105 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105 0x00000200 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_BITN 9 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_M 0x00000200 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_S 9 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105 0x00000200 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_BITN 9 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_M 0x00000200 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_S 9 // Field: [8] WRT_PROT_SEC_104 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104 0x00000100 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_BITN 8 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_M 0x00000100 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_S 8 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104 0x00000100 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_BITN 8 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_M 0x00000100 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_S 8 // Field: [7] WRT_PROT_SEC_103 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103 0x00000080 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_BITN 7 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_M 0x00000080 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_S 7 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103 0x00000080 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_BITN 7 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_M 0x00000080 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_S 7 // Field: [6] WRT_PROT_SEC_102 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102 0x00000040 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_BITN 6 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_M 0x00000040 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_S 6 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102 0x00000040 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_BITN 6 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_M 0x00000040 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_S 6 // Field: [5] WRT_PROT_SEC_101 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101 0x00000020 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_BITN 5 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_M 0x00000020 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_S 5 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101 0x00000020 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_BITN 5 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_M 0x00000020 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_S 5 // Field: [4] WRT_PROT_SEC_100 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100 0x00000010 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_BITN 4 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_M 0x00000010 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_S 4 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100 0x00000010 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_BITN 4 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_M 0x00000010 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_S 4 // Field: [3] WRT_PROT_SEC_99 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99 0x00000008 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_BITN 3 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_M 0x00000008 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_S 3 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99 0x00000008 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_BITN 3 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_M 0x00000008 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_S 3 // Field: [2] WRT_PROT_SEC_98 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98 0x00000004 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_BITN 2 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_M 0x00000004 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_S 2 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98 0x00000004 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_BITN 2 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_M 0x00000004 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_S 2 // Field: [1] WRT_PROT_SEC_97 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97 0x00000002 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_BITN 1 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_M 0x00000002 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_S 1 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97 0x00000002 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_BITN 1 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_M 0x00000002 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_S 1 // Field: [0] WRT_PROT_SEC_96 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96 0x00000001 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_BITN 0 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_M 0x00000001 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_S 0 - +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96 0x00000001 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_BITN 0 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_M 0x00000001 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_S 0 #endif // __CCFG__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg_simple_struct.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg_simple_struct.h index b4034e8..c599787 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg_simple_struct.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg_simple_struct.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_ccfg_simple_struct_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_ccfg_simple_struct_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CCFG_SIMPLE_STRUCT_H__ #define __HW_CCFG_SIMPLE_STRUCT_H__ @@ -46,29 +46,29 @@ //***************************************************************************** typedef struct { - // Mapped to address - uint32_t CCFG_EXT_LF_CLK ; // 0x50004FA8 - uint32_t CCFG_MODE_CONF_1 ; // 0x50004FAC - uint32_t CCFG_SIZE_AND_DIS_FLAGS ; // 0x50004FB0 - uint32_t CCFG_MODE_CONF ; // 0x50004FB4 - uint32_t CCFG_VOLT_LOAD_0 ; // 0x50004FB8 - uint32_t CCFG_VOLT_LOAD_1 ; // 0x50004FBC - uint32_t CCFG_RTC_OFFSET ; // 0x50004FC0 - uint32_t CCFG_FREQ_OFFSET ; // 0x50004FC4 - uint32_t CCFG_IEEE_MAC_0 ; // 0x50004FC8 - uint32_t CCFG_IEEE_MAC_1 ; // 0x50004FCC - uint32_t CCFG_IEEE_BLE_0 ; // 0x50004FD0 - uint32_t CCFG_IEEE_BLE_1 ; // 0x50004FD4 - uint32_t CCFG_BL_CONFIG ; // 0x50004FD8 - uint32_t CCFG_ERASE_CONF ; // 0x50004FDC - uint32_t CCFG_CCFG_TI_OPTIONS ; // 0x50004FE0 - uint32_t CCFG_CCFG_TAP_DAP_0 ; // 0x50004FE4 - uint32_t CCFG_CCFG_TAP_DAP_1 ; // 0x50004FE8 - uint32_t CCFG_IMAGE_VALID_CONF ; // 0x50004FEC - uint32_t CCFG_CCFG_PROT_31_0 ; // 0x50004FF0 - uint32_t CCFG_CCFG_PROT_63_32 ; // 0x50004FF4 - uint32_t CCFG_CCFG_PROT_95_64 ; // 0x50004FF8 - uint32_t CCFG_CCFG_PROT_127_96 ; // 0x50004FFC + // Mapped to address + uint32_t CCFG_EXT_LF_CLK; // 0x50004FA8 + uint32_t CCFG_MODE_CONF_1; // 0x50004FAC + uint32_t CCFG_SIZE_AND_DIS_FLAGS; // 0x50004FB0 + uint32_t CCFG_MODE_CONF; // 0x50004FB4 + uint32_t CCFG_VOLT_LOAD_0; // 0x50004FB8 + uint32_t CCFG_VOLT_LOAD_1; // 0x50004FBC + uint32_t CCFG_RTC_OFFSET; // 0x50004FC0 + uint32_t CCFG_FREQ_OFFSET; // 0x50004FC4 + uint32_t CCFG_IEEE_MAC_0; // 0x50004FC8 + uint32_t CCFG_IEEE_MAC_1; // 0x50004FCC + uint32_t CCFG_IEEE_BLE_0; // 0x50004FD0 + uint32_t CCFG_IEEE_BLE_1; // 0x50004FD4 + uint32_t CCFG_BL_CONFIG; // 0x50004FD8 + uint32_t CCFG_ERASE_CONF; // 0x50004FDC + uint32_t CCFG_CCFG_TI_OPTIONS; // 0x50004FE0 + uint32_t CCFG_CCFG_TAP_DAP_0; // 0x50004FE4 + uint32_t CCFG_CCFG_TAP_DAP_1; // 0x50004FE8 + uint32_t CCFG_IMAGE_VALID_CONF; // 0x50004FEC + uint32_t CCFG_CCFG_PROT_31_0; // 0x50004FF0 + uint32_t CCFG_CCFG_PROT_63_32; // 0x50004FF4 + uint32_t CCFG_CCFG_PROT_95_64; // 0x50004FF8 + uint32_t CCFG_CCFG_PROT_127_96; // 0x50004FFC } ccfg_t; //***************************************************************************** @@ -78,5 +78,4 @@ typedef struct //***************************************************************************** extern const ccfg_t __ccfg; - #endif // __HW_CCFG_SIMPLE_STRUCT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_chip_def.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_chip_def.h index 94df2fc..7b06e08 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_chip_def.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_chip_def.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: hw_chip_def.h -* Revised: 2017-06-26 09:33:33 +0200 (Mon, 26 Jun 2017) -* Revision: 49227 -* -* Description: Defines for device properties. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_chip_def.h + * Revised: 2017-06-26 09:33:33 +0200 (Mon, 26 Jun 2017) + * Revision: 49227 + * + * Description: Defines for device properties. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -53,8 +53,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif //***************************************************************************** @@ -64,13 +63,13 @@ extern "C" // //***************************************************************************** /* CC2620F128 */ -#if defined(CC2620F128RGZ_R20) || defined(CC2620F128RGZ_R21) +#if defined(CC2620F128RGZ_R20) || defined(CC2620F128RGZ_R21) #define CC_CHIP_ID 0x26200720 #elif defined(CC2620F128RHB_R20) || defined(CC2620F128RHB_R21) #define CC_CHIP_ID 0x26200520 #elif defined(CC2620F128RSM_R20) || defined(CC2620F128RSM_R21) #define CC_CHIP_ID 0x26200420 -#elif defined(CC2620F128_R20) || defined(CC2620F128_R21) +#elif defined(CC2620F128_R20) || defined(CC2620F128_R21) #define CC_CHIP_ID 0x26200020 #elif defined(CC2620F128RGZ_R22) || defined(CC2620F128RGZ) #define CC_CHIP_ID 0x26200722 @@ -78,7 +77,7 @@ extern "C" #define CC_CHIP_ID 0x26200522 #elif defined(CC2620F128RSM_R22) || defined(CC2620F128RSM) #define CC_CHIP_ID 0x26200422 -#elif defined(CC2620F128_R22) || defined(CC2620F128) +#elif defined(CC2620F128_R22) || defined(CC2620F128) #define CC_CHIP_ID 0x26200022 /* CC2630F128 */ #elif defined(CC2630F128RGZ_R20) || defined(CC2630F128RGZ_R21) @@ -87,7 +86,7 @@ extern "C" #define CC_CHIP_ID 0x26300520 #elif defined(CC2630F128RSM_R20) || defined(CC2630F128RSM_R21) #define CC_CHIP_ID 0x26300420 -#elif defined(CC2630F128_R20) || defined(CC2630F128_R21) +#elif defined(CC2630F128_R20) || defined(CC2630F128_R21) #define CC_CHIP_ID 0x26300020 #elif defined(CC2630F128RGZ_R22) || defined(CC2630F128RGZ) #define CC_CHIP_ID 0x26300722 @@ -95,7 +94,7 @@ extern "C" #define CC_CHIP_ID 0x26300522 #elif defined(CC2630F128RSM_R22) || defined(CC2630F128RSM) #define CC_CHIP_ID 0x26300422 -#elif defined(CC2630F128_R22) || defined(CC2630F128) +#elif defined(CC2630F128_R22) || defined(CC2630F128) #define CC_CHIP_ID 0x26300022 /* CC2640F128 */ #elif defined(CC2640F128RGZ_R20) || defined(CC2640F128RGZ_R21) @@ -104,7 +103,7 @@ extern "C" #define CC_CHIP_ID 0x26400520 #elif defined(CC2640F128RSM_R20) || defined(CC2640F128RSM_R21) #define CC_CHIP_ID 0x26400420 -#elif defined(CC2640F128_R20) || defined(CC2640F128_R21) +#elif defined(CC2640F128_R20) || defined(CC2640F128_R21) #define CC_CHIP_ID 0x26400020 #elif defined(CC2640F128RGZ_R22) || defined(CC2640F128RGZ) #define CC_CHIP_ID 0x26400722 @@ -112,7 +111,7 @@ extern "C" #define CC_CHIP_ID 0x26400522 #elif defined(CC2640F128RSM_R22) || defined(CC2640F128RSM) #define CC_CHIP_ID 0x26400422 -#elif defined(CC2640F128_R22) || defined(CC2640F128) +#elif defined(CC2640F128_R22) || defined(CC2640F128) #define CC_CHIP_ID 0x26400022 /* CC2650F128 */ #elif defined(CC2650F128RGZ_R20) || defined(CC2650F128RGZ_R21) @@ -121,7 +120,7 @@ extern "C" #define CC_CHIP_ID 0x26500520 #elif defined(CC2650F128RSM_R20) || defined(CC2650F128RSM_R21) #define CC_CHIP_ID 0x26500420 -#elif defined(CC2650F128_R20) || defined(CC2650F128_R21) +#elif defined(CC2650F128_R20) || defined(CC2650F128_R21) #define CC_CHIP_ID 0x26500020 #elif defined(CC2650F128RGZ_R22) || defined(CC2650F128RGZ) #define CC_CHIP_ID 0x26500722 @@ -129,7 +128,7 @@ extern "C" #define CC_CHIP_ID 0x26500522 #elif defined(CC2650F128RSM_R22) || defined(CC2650F128RSM) #define CC_CHIP_ID 0x26500422 -#elif defined(CC2650F128_R22) || defined(CC2650F128) +#elif defined(CC2650F128_R22) || defined(CC2650F128) #define CC_CHIP_ID 0x26500022 /* CC2650L128 (OTP) */ #elif defined(CC2650L128) @@ -141,7 +140,7 @@ extern "C" #define CC_CHIP_ID 0x13100520 #elif defined(CC1310F128RSM_R20) || defined(CC1310F128RSM) #define CC_CHIP_ID 0x13100420 -#elif defined(CC1310F128_R20) || defined(CC1310F128) +#elif defined(CC1310F128_R20) || defined(CC1310F128) #define CC_CHIP_ID 0x13100020 /* CC1350F128 */ #elif defined(CC1350F128RGZ_R20) || defined(CC1350F128RGZ) @@ -150,7 +149,7 @@ extern "C" #define CC_CHIP_ID 0x13500520 #elif defined(CC1350F128RSM_R20) || defined(CC1350F128RSM) #define CC_CHIP_ID 0x13500420 -#elif defined(CC1350F128_R20) || defined(CC1350F128) +#elif defined(CC1350F128_R20) || defined(CC1350F128) #define CC_CHIP_ID 0x13500020 /* CC2640R2F */ #elif defined(CC2640R2FRGZ_R25) || defined(CC2640R2FRGZ) @@ -159,37 +158,37 @@ extern "C" #define CC_CHIP_ID 0x26401510 #elif defined(CC2640R2FRSM_R25) || defined(CC2640R2FRSM) #define CC_CHIP_ID 0x26401410 -#elif defined(CC2640R2F_R25) || defined(CC2640R2F) +#elif defined(CC2640R2F_R25) || defined(CC2640R2F) #define CC_CHIP_ID 0x26401010 /* CC2652R1F */ #elif defined(CC2652R1FRGZ_R10) || defined(CC2652R1FRGZ) #define CC_CHIP_ID 0x26523710 -#elif defined(CC2652R1F_R10) || defined(CC2652R1F) +#elif defined(CC2652R1F_R10) || defined(CC2652R1F) #define CC_CHIP_ID 0x26523010 /* CC2644R1F */ #elif defined(CC2644R1FRGZ_R10) || defined(CC2644R1FRGZ) #define CC_CHIP_ID 0x26443710 -#elif defined(CC2644R1F_R10) || defined(CC2644R1F) +#elif defined(CC2644R1F_R10) || defined(CC2644R1F) #define CC_CHIP_ID 0x26443010 /* CC2642R1F */ #elif defined(CC2642R1FRGZ_R10) || defined(CC2642R1FRGZ) #define CC_CHIP_ID 0x26423710 -#elif defined(CC2642R1F_R10) || defined(CC2642R1F) +#elif defined(CC2642R1F_R10) || defined(CC2642R1F) #define CC_CHIP_ID 0x26423010 /* CC1354R1F */ #elif defined(CC1354R1FRGZ_R10) || defined(CC1354R1FRGZ) #define CC_CHIP_ID 0x13543710 -#elif defined(CC1354R1F_R10) || defined(CC1354R1F) +#elif defined(CC1354R1F_R10) || defined(CC1354R1F) #define CC_CHIP_ID 0x13543010 /* CC1352R1F */ #elif defined(CC1352R1FRGZ_R10) || defined(CC1352R1FRGZ) #define CC_CHIP_ID 0x13523710 -#elif defined(CC1352R1F_R10) || defined(CC1352R1F) +#elif defined(CC1352R1F_R10) || defined(CC1352R1F) #define CC_CHIP_ID 0x13523010 /* CC1312R1F */ #elif defined(CC1312R1FRGZ_R10) || defined(CC1312R1FRGZ) #define CC_CHIP_ID 0x13123710 -#elif defined(CC1312R1F_R10) || defined(CC1312R1F) +#elif defined(CC1312R1F_R10) || defined(CC1312R1F) #define CC_CHIP_ID 0x13123010 #endif @@ -210,7 +209,7 @@ extern "C" #if (CC_GET_CHIP_OPTION != ((CC_CHIP_ID & 0x0000F000) >> 12)) #error "Specified chip option does not match DriverLib release" #endif -#if (CC_GET_CHIP_HWREV != ((CC_CHIP_ID & 0x000000FF) >> 0)) +#if (CC_GET_CHIP_HWREV != ((CC_CHIP_ID & 0x000000FF) >> 0)) #error "Specified chip hardware revision does not match DriverLib release" #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_dwt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_dwt.h index 5386ee9..99cb118 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_dwt.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_dwt.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_cpu_dwt_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_cpu_dwt_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CPU_DWT_H__ #define __HW_CPU_DWT_H__ @@ -44,64 +44,64 @@ // //***************************************************************************** // Control -#define CPU_DWT_O_CTRL 0x00000000 +#define CPU_DWT_O_CTRL 0x00000000 // Current PC Sampler Cycle Count -#define CPU_DWT_O_CYCCNT 0x00000004 +#define CPU_DWT_O_CYCCNT 0x00000004 // CPI Count -#define CPU_DWT_O_CPICNT 0x00000008 +#define CPU_DWT_O_CPICNT 0x00000008 // Exception Overhead Count -#define CPU_DWT_O_EXCCNT 0x0000000C +#define CPU_DWT_O_EXCCNT 0x0000000C // Sleep Count -#define CPU_DWT_O_SLEEPCNT 0x00000010 +#define CPU_DWT_O_SLEEPCNT 0x00000010 // LSU Count -#define CPU_DWT_O_LSUCNT 0x00000014 +#define CPU_DWT_O_LSUCNT 0x00000014 // Fold Count -#define CPU_DWT_O_FOLDCNT 0x00000018 +#define CPU_DWT_O_FOLDCNT 0x00000018 // Program Counter Sample -#define CPU_DWT_O_PCSR 0x0000001C +#define CPU_DWT_O_PCSR 0x0000001C // Comparator 0 -#define CPU_DWT_O_COMP0 0x00000020 +#define CPU_DWT_O_COMP0 0x00000020 // Mask 0 -#define CPU_DWT_O_MASK0 0x00000024 +#define CPU_DWT_O_MASK0 0x00000024 // Function 0 -#define CPU_DWT_O_FUNCTION0 0x00000028 +#define CPU_DWT_O_FUNCTION0 0x00000028 // Comparator 1 -#define CPU_DWT_O_COMP1 0x00000030 +#define CPU_DWT_O_COMP1 0x00000030 // Mask 1 -#define CPU_DWT_O_MASK1 0x00000034 +#define CPU_DWT_O_MASK1 0x00000034 // Function 1 -#define CPU_DWT_O_FUNCTION1 0x00000038 +#define CPU_DWT_O_FUNCTION1 0x00000038 // Comparator 2 -#define CPU_DWT_O_COMP2 0x00000040 +#define CPU_DWT_O_COMP2 0x00000040 // Mask 2 -#define CPU_DWT_O_MASK2 0x00000044 +#define CPU_DWT_O_MASK2 0x00000044 // Function 2 -#define CPU_DWT_O_FUNCTION2 0x00000048 +#define CPU_DWT_O_FUNCTION2 0x00000048 // Comparator 3 -#define CPU_DWT_O_COMP3 0x00000050 +#define CPU_DWT_O_COMP3 0x00000050 // Mask 3 -#define CPU_DWT_O_MASK3 0x00000054 +#define CPU_DWT_O_MASK3 0x00000054 // Function 3 -#define CPU_DWT_O_FUNCTION3 0x00000058 +#define CPU_DWT_O_FUNCTION3 0x00000058 //***************************************************************************** // @@ -111,18 +111,18 @@ // Field: [25] NOCYCCNT // // When set, CYCCNT is not supported. -#define CPU_DWT_CTRL_NOCYCCNT 0x02000000 -#define CPU_DWT_CTRL_NOCYCCNT_BITN 25 -#define CPU_DWT_CTRL_NOCYCCNT_M 0x02000000 -#define CPU_DWT_CTRL_NOCYCCNT_S 25 +#define CPU_DWT_CTRL_NOCYCCNT 0x02000000 +#define CPU_DWT_CTRL_NOCYCCNT_BITN 25 +#define CPU_DWT_CTRL_NOCYCCNT_M 0x02000000 +#define CPU_DWT_CTRL_NOCYCCNT_S 25 // Field: [24] NOPRFCNT // // When set, FOLDCNT, LSUCNT, SLEEPCNT, EXCCNT, and CPICNT are not supported. -#define CPU_DWT_CTRL_NOPRFCNT 0x01000000 -#define CPU_DWT_CTRL_NOPRFCNT_BITN 24 -#define CPU_DWT_CTRL_NOPRFCNT_M 0x01000000 -#define CPU_DWT_CTRL_NOPRFCNT_S 24 +#define CPU_DWT_CTRL_NOPRFCNT 0x01000000 +#define CPU_DWT_CTRL_NOPRFCNT_BITN 24 +#define CPU_DWT_CTRL_NOPRFCNT_M 0x01000000 +#define CPU_DWT_CTRL_NOPRFCNT_S 24 // Field: [22] CYCEVTENA // @@ -132,10 +132,10 @@ // // 0: Cycle count events disabled // 1: Cycle count events enabled -#define CPU_DWT_CTRL_CYCEVTENA 0x00400000 -#define CPU_DWT_CTRL_CYCEVTENA_BITN 22 -#define CPU_DWT_CTRL_CYCEVTENA_M 0x00400000 -#define CPU_DWT_CTRL_CYCEVTENA_S 22 +#define CPU_DWT_CTRL_CYCEVTENA 0x00400000 +#define CPU_DWT_CTRL_CYCEVTENA_BITN 22 +#define CPU_DWT_CTRL_CYCEVTENA_M 0x00400000 +#define CPU_DWT_CTRL_CYCEVTENA_S 22 // Field: [21] FOLDEVTENA // @@ -146,10 +146,10 @@ // // 0: Folded instruction count events disabled. // 1: Folded instruction count events enabled. -#define CPU_DWT_CTRL_FOLDEVTENA 0x00200000 -#define CPU_DWT_CTRL_FOLDEVTENA_BITN 21 -#define CPU_DWT_CTRL_FOLDEVTENA_M 0x00200000 -#define CPU_DWT_CTRL_FOLDEVTENA_S 21 +#define CPU_DWT_CTRL_FOLDEVTENA 0x00200000 +#define CPU_DWT_CTRL_FOLDEVTENA_BITN 21 +#define CPU_DWT_CTRL_FOLDEVTENA_M 0x00200000 +#define CPU_DWT_CTRL_FOLDEVTENA_S 21 // Field: [20] LSUEVTENA // @@ -159,10 +159,10 @@ // // 0: LSU count events disabled. // 1: LSU count events enabled. -#define CPU_DWT_CTRL_LSUEVTENA 0x00100000 -#define CPU_DWT_CTRL_LSUEVTENA_BITN 20 -#define CPU_DWT_CTRL_LSUEVTENA_M 0x00100000 -#define CPU_DWT_CTRL_LSUEVTENA_S 20 +#define CPU_DWT_CTRL_LSUEVTENA 0x00100000 +#define CPU_DWT_CTRL_LSUEVTENA_BITN 20 +#define CPU_DWT_CTRL_LSUEVTENA_M 0x00100000 +#define CPU_DWT_CTRL_LSUEVTENA_S 20 // Field: [19] SLEEPEVTENA // @@ -171,10 +171,10 @@ // // 0: Sleep count events disabled. // 1: Sleep count events enabled. -#define CPU_DWT_CTRL_SLEEPEVTENA 0x00080000 -#define CPU_DWT_CTRL_SLEEPEVTENA_BITN 19 -#define CPU_DWT_CTRL_SLEEPEVTENA_M 0x00080000 -#define CPU_DWT_CTRL_SLEEPEVTENA_S 19 +#define CPU_DWT_CTRL_SLEEPEVTENA 0x00080000 +#define CPU_DWT_CTRL_SLEEPEVTENA_BITN 19 +#define CPU_DWT_CTRL_SLEEPEVTENA_M 0x00080000 +#define CPU_DWT_CTRL_SLEEPEVTENA_S 19 // Field: [18] EXCEVTENA // @@ -183,10 +183,10 @@ // // 0x0: Interrupt overhead event disabled. // 0x1: Interrupt overhead event enabled. -#define CPU_DWT_CTRL_EXCEVTENA 0x00040000 -#define CPU_DWT_CTRL_EXCEVTENA_BITN 18 -#define CPU_DWT_CTRL_EXCEVTENA_M 0x00040000 -#define CPU_DWT_CTRL_EXCEVTENA_S 18 +#define CPU_DWT_CTRL_EXCEVTENA 0x00040000 +#define CPU_DWT_CTRL_EXCEVTENA_BITN 18 +#define CPU_DWT_CTRL_EXCEVTENA_M 0x00040000 +#define CPU_DWT_CTRL_EXCEVTENA_S 18 // Field: [17] CPIEVTENA // @@ -195,10 +195,10 @@ // // 0: CPI counter events disabled. // 1: CPI counter events enabled. -#define CPU_DWT_CTRL_CPIEVTENA 0x00020000 -#define CPU_DWT_CTRL_CPIEVTENA_BITN 17 -#define CPU_DWT_CTRL_CPIEVTENA_M 0x00020000 -#define CPU_DWT_CTRL_CPIEVTENA_S 17 +#define CPU_DWT_CTRL_CPIEVTENA 0x00020000 +#define CPU_DWT_CTRL_CPIEVTENA_BITN 17 +#define CPU_DWT_CTRL_CPIEVTENA_M 0x00020000 +#define CPU_DWT_CTRL_CPIEVTENA_S 17 // Field: [16] EXCTRCENA // @@ -206,10 +206,10 @@ // // 0: Interrupt event trace disabled. // 1: Interrupt event trace enabled. -#define CPU_DWT_CTRL_EXCTRCENA 0x00010000 -#define CPU_DWT_CTRL_EXCTRCENA_BITN 16 -#define CPU_DWT_CTRL_EXCTRCENA_M 0x00010000 -#define CPU_DWT_CTRL_EXCTRCENA_S 16 +#define CPU_DWT_CTRL_EXCTRCENA 0x00010000 +#define CPU_DWT_CTRL_EXCTRCENA_BITN 16 +#define CPU_DWT_CTRL_EXCTRCENA_M 0x00010000 +#define CPU_DWT_CTRL_EXCTRCENA_S 16 // Field: [12] PCSAMPLEENA // @@ -219,10 +219,10 @@ // // 0: PC Sampling event disabled. // 1: Sampling event enabled. -#define CPU_DWT_CTRL_PCSAMPLEENA 0x00001000 -#define CPU_DWT_CTRL_PCSAMPLEENA_BITN 12 -#define CPU_DWT_CTRL_PCSAMPLEENA_M 0x00001000 -#define CPU_DWT_CTRL_PCSAMPLEENA_S 12 +#define CPU_DWT_CTRL_PCSAMPLEENA 0x00001000 +#define CPU_DWT_CTRL_PCSAMPLEENA_BITN 12 +#define CPU_DWT_CTRL_PCSAMPLEENA_M 0x00001000 +#define CPU_DWT_CTRL_PCSAMPLEENA_S 12 // Field: [11:10] SYNCTAP // @@ -235,13 +235,13 @@ // BIT26 Tap at bit 26 of CYCCNT // BIT24 Tap at bit 24 of CYCCNT // DIS Disabled. No synchronization packets -#define CPU_DWT_CTRL_SYNCTAP_W 2 -#define CPU_DWT_CTRL_SYNCTAP_M 0x00000C00 -#define CPU_DWT_CTRL_SYNCTAP_S 10 -#define CPU_DWT_CTRL_SYNCTAP_BIT28 0x00000C00 -#define CPU_DWT_CTRL_SYNCTAP_BIT26 0x00000800 -#define CPU_DWT_CTRL_SYNCTAP_BIT24 0x00000400 -#define CPU_DWT_CTRL_SYNCTAP_DIS 0x00000000 +#define CPU_DWT_CTRL_SYNCTAP_W 2 +#define CPU_DWT_CTRL_SYNCTAP_M 0x00000C00 +#define CPU_DWT_CTRL_SYNCTAP_S 10 +#define CPU_DWT_CTRL_SYNCTAP_BIT28 0x00000C00 +#define CPU_DWT_CTRL_SYNCTAP_BIT26 0x00000800 +#define CPU_DWT_CTRL_SYNCTAP_BIT24 0x00000400 +#define CPU_DWT_CTRL_SYNCTAP_DIS 0x00000000 // Field: [9] CYCTAP // @@ -253,12 +253,12 @@ // ENUMs: // BIT10 Selects bit [10] to tap // BIT6 Selects bit [6] to tap -#define CPU_DWT_CTRL_CYCTAP 0x00000200 -#define CPU_DWT_CTRL_CYCTAP_BITN 9 -#define CPU_DWT_CTRL_CYCTAP_M 0x00000200 -#define CPU_DWT_CTRL_CYCTAP_S 9 -#define CPU_DWT_CTRL_CYCTAP_BIT10 0x00000200 -#define CPU_DWT_CTRL_CYCTAP_BIT6 0x00000000 +#define CPU_DWT_CTRL_CYCTAP 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_BITN 9 +#define CPU_DWT_CTRL_CYCTAP_M 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_S 9 +#define CPU_DWT_CTRL_CYCTAP_BIT10 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_BIT6 0x00000000 // Field: [8:5] POSTCNT // @@ -266,9 +266,9 @@ // to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it // triggers an event for PCSAMPLEENA or CYCEVTENA use. It also reloads with the // value from POSTPRESET. -#define CPU_DWT_CTRL_POSTCNT_W 4 -#define CPU_DWT_CTRL_POSTCNT_M 0x000001E0 -#define CPU_DWT_CTRL_POSTCNT_S 5 +#define CPU_DWT_CTRL_POSTCNT_W 4 +#define CPU_DWT_CTRL_POSTCNT_M 0x000001E0 +#define CPU_DWT_CTRL_POSTCNT_S 5 // Field: [4:1] POSTPRESET // @@ -277,18 +277,18 @@ // a count-down value, to be reloaded into POSTCNT each time it reaches 0. For // example, a value 1 in this register means an event is formed every other tap // change. -#define CPU_DWT_CTRL_POSTPRESET_W 4 -#define CPU_DWT_CTRL_POSTPRESET_M 0x0000001E -#define CPU_DWT_CTRL_POSTPRESET_S 1 +#define CPU_DWT_CTRL_POSTPRESET_W 4 +#define CPU_DWT_CTRL_POSTPRESET_M 0x0000001E +#define CPU_DWT_CTRL_POSTPRESET_S 1 // Field: [0] CYCCNTENA // // Enable CYCCNT, allowing it to increment and generate synchronization and // count events. If NOCYCCNT = 1, this bit reads zero and ignore writes. -#define CPU_DWT_CTRL_CYCCNTENA 0x00000001 -#define CPU_DWT_CTRL_CYCCNTENA_BITN 0 -#define CPU_DWT_CTRL_CYCCNTENA_M 0x00000001 -#define CPU_DWT_CTRL_CYCCNTENA_S 0 +#define CPU_DWT_CTRL_CYCCNTENA 0x00000001 +#define CPU_DWT_CTRL_CYCCNTENA_BITN 0 +#define CPU_DWT_CTRL_CYCCNTENA_M 0x00000001 +#define CPU_DWT_CTRL_CYCCNTENA_S 0 //***************************************************************************** // @@ -303,9 +303,9 @@ // advance in power modes where free-running clock to CPU stops). It wraps // around to 0 on overflow. The debugger must initialize this to 0 when first // enabling. -#define CPU_DWT_CYCCNT_CYCCNT_W 32 -#define CPU_DWT_CYCCNT_CYCCNT_M 0xFFFFFFFF -#define CPU_DWT_CYCCNT_CYCCNT_S 0 +#define CPU_DWT_CYCCNT_CYCCNT_W 32 +#define CPU_DWT_CYCCNT_CYCCNT_M 0xFFFFFFFF +#define CPU_DWT_CYCCNT_CYCCNT_S 0 //***************************************************************************** // @@ -320,9 +320,9 @@ // stalls. If CTRL.CPIEVTENA is set, an event is emitted when the counter // overflows. This counter initializes to 0 when it is enabled using // CTRL.CPIEVTENA. -#define CPU_DWT_CPICNT_CPICNT_W 8 -#define CPU_DWT_CPICNT_CPICNT_M 0x000000FF -#define CPU_DWT_CPICNT_CPICNT_S 0 +#define CPU_DWT_CPICNT_CPICNT_W 8 +#define CPU_DWT_CPICNT_CPICNT_M 0x000000FF +#define CPU_DWT_CPICNT_CPICNT_S 0 //***************************************************************************** // @@ -335,9 +335,9 @@ // interrupt processing (for example entry stacking, return unstacking, // pre-emption). An event is emitted on counter overflow (every 256 cycles). // This counter initializes to 0 when it is enabled using CTRL.EXCEVTENA. -#define CPU_DWT_EXCCNT_EXCCNT_W 8 -#define CPU_DWT_EXCCNT_EXCCNT_M 0x000000FF -#define CPU_DWT_EXCCNT_EXCCNT_S 0 +#define CPU_DWT_EXCCNT_EXCCNT_W 8 +#define CPU_DWT_EXCCNT_EXCCNT_M 0x000000FF +#define CPU_DWT_EXCCNT_EXCCNT_S 0 //***************************************************************************** // @@ -353,9 +353,9 @@ // power modes the free-running clock to CPU is gated to minimize power // consumption. This means that the sleep counter will be invalid in these // power modes. -#define CPU_DWT_SLEEPCNT_SLEEPCNT_W 8 -#define CPU_DWT_SLEEPCNT_SLEEPCNT_M 0x000000FF -#define CPU_DWT_SLEEPCNT_SLEEPCNT_S 0 +#define CPU_DWT_SLEEPCNT_SLEEPCNT_W 8 +#define CPU_DWT_SLEEPCNT_SLEEPCNT_M 0x000000FF +#define CPU_DWT_SLEEPCNT_SLEEPCNT_S 0 //***************************************************************************** // @@ -371,9 +371,9 @@ // cycles (i.e. takes four cycles to execute), increments this counter three // times. An event is emitted on counter overflow (every 256 cycles). This // counter initializes to 0 when it is enabled using CTRL.LSUEVTENA. -#define CPU_DWT_LSUCNT_LSUCNT_W 8 -#define CPU_DWT_LSUCNT_LSUCNT_M 0x000000FF -#define CPU_DWT_LSUCNT_LSUCNT_S 0 +#define CPU_DWT_LSUCNT_LSUCNT_W 8 +#define CPU_DWT_LSUCNT_LSUCNT_M 0x000000FF +#define CPU_DWT_LSUCNT_LSUCNT_S 0 //***************************************************************************** // @@ -384,9 +384,9 @@ // // This counts the total number folded instructions. This counter initializes // to 0 when it is enabled using CTRL.FOLDEVTENA. -#define CPU_DWT_FOLDCNT_FOLDCNT_W 8 -#define CPU_DWT_FOLDCNT_FOLDCNT_M 0x000000FF -#define CPU_DWT_FOLDCNT_FOLDCNT_S 0 +#define CPU_DWT_FOLDCNT_FOLDCNT_W 8 +#define CPU_DWT_FOLDCNT_FOLDCNT_M 0x000000FF +#define CPU_DWT_FOLDCNT_FOLDCNT_S 0 //***************************************************************************** // @@ -396,9 +396,9 @@ // Field: [31:0] EIASAMPLE // // Execution instruction address sample, or 0xFFFFFFFF if the core is halted. -#define CPU_DWT_PCSR_EIASAMPLE_W 32 -#define CPU_DWT_PCSR_EIASAMPLE_M 0xFFFFFFFF -#define CPU_DWT_PCSR_EIASAMPLE_S 0 +#define CPU_DWT_PCSR_EIASAMPLE_W 32 +#define CPU_DWT_PCSR_EIASAMPLE_M 0xFFFFFFFF +#define CPU_DWT_PCSR_EIASAMPLE_S 0 //***************************************************************************** // @@ -410,9 +410,9 @@ // Reference value to compare against PC or the data address as given by // FUNCTION0. Comparator 0 can also compare against the value of the PC Sampler // Counter (CYCCNT). -#define CPU_DWT_COMP0_COMP_W 32 -#define CPU_DWT_COMP0_COMP_M 0xFFFFFFFF -#define CPU_DWT_COMP0_COMP_S 0 +#define CPU_DWT_COMP0_COMP_W 32 +#define CPU_DWT_COMP0_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP0_COMP_S 0 //***************************************************************************** // @@ -427,9 +427,9 @@ // slightly more complex to enable matching an address wherever it appears on a // bus. So, if COMP0 is 3, this matches a word access of 0, because 3 would be // within the word. -#define CPU_DWT_MASK0_MASK_W 4 -#define CPU_DWT_MASK0_MASK_M 0x0000000F -#define CPU_DWT_MASK0_MASK_S 0 +#define CPU_DWT_MASK0_MASK_W 4 +#define CPU_DWT_MASK0_MASK_M 0x0000000F +#define CPU_DWT_MASK0_MASK_S 0 //***************************************************************************** // @@ -441,29 +441,29 @@ // This bit is set when the comparator matches, and indicates that the // operation defined by FUNCTION has occurred since this bit was last read. // This bit is cleared on read. -#define CPU_DWT_FUNCTION0_MATCHED 0x01000000 -#define CPU_DWT_FUNCTION0_MATCHED_BITN 24 -#define CPU_DWT_FUNCTION0_MATCHED_M 0x01000000 -#define CPU_DWT_FUNCTION0_MATCHED_S 24 +#define CPU_DWT_FUNCTION0_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION0_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION0_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION0_MATCHED_S 24 // Field: [7] CYCMATCH // // This bit is only available in comparator 0. When set, COMP0 will compare // against the cycle counter (CYCCNT). -#define CPU_DWT_FUNCTION0_CYCMATCH 0x00000080 -#define CPU_DWT_FUNCTION0_CYCMATCH_BITN 7 -#define CPU_DWT_FUNCTION0_CYCMATCH_M 0x00000080 -#define CPU_DWT_FUNCTION0_CYCMATCH_S 7 +#define CPU_DWT_FUNCTION0_CYCMATCH 0x00000080 +#define CPU_DWT_FUNCTION0_CYCMATCH_BITN 7 +#define CPU_DWT_FUNCTION0_CYCMATCH_M 0x00000080 +#define CPU_DWT_FUNCTION0_CYCMATCH_S 7 // Field: [5] EMITRANGE // // Emit range field. This bit permits emitting offset when range match occurs. // PC sampling is not supported when emit range is enabled. // This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. -#define CPU_DWT_FUNCTION0_EMITRANGE 0x00000020 -#define CPU_DWT_FUNCTION0_EMITRANGE_BITN 5 -#define CPU_DWT_FUNCTION0_EMITRANGE_M 0x00000020 -#define CPU_DWT_FUNCTION0_EMITRANGE_S 5 +#define CPU_DWT_FUNCTION0_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION0_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION0_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION0_EMITRANGE_S 5 // Field: [3:0] FUNCTION // @@ -500,9 +500,9 @@ // sampled for the first address of a burst. // Note 3: PC match is not recommended for watchpoints because it stops after // the instruction. It mainly guards and triggers the ETM. -#define CPU_DWT_FUNCTION0_FUNCTION_W 4 -#define CPU_DWT_FUNCTION0_FUNCTION_M 0x0000000F -#define CPU_DWT_FUNCTION0_FUNCTION_S 0 +#define CPU_DWT_FUNCTION0_FUNCTION_W 4 +#define CPU_DWT_FUNCTION0_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION0_FUNCTION_S 0 //***************************************************************************** // @@ -515,9 +515,9 @@ // FUNCTION1. // Comparator 1 can also compare data values. So this register can contain // reference values for data matching. -#define CPU_DWT_COMP1_COMP_W 32 -#define CPU_DWT_COMP1_COMP_M 0xFFFFFFFF -#define CPU_DWT_COMP1_COMP_S 0 +#define CPU_DWT_COMP1_COMP_W 32 +#define CPU_DWT_COMP1_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP1_COMP_S 0 //***************************************************************************** // @@ -532,9 +532,9 @@ // slightly more complex to enable matching an address wherever it appears on a // bus. So, if COMP1 is 3, this matches a word access of 0, because 3 would be // within the word. -#define CPU_DWT_MASK1_MASK_W 4 -#define CPU_DWT_MASK1_MASK_M 0x0000000F -#define CPU_DWT_MASK1_MASK_S 0 +#define CPU_DWT_MASK1_MASK_W 4 +#define CPU_DWT_MASK1_MASK_M 0x0000000F +#define CPU_DWT_MASK1_MASK_S 0 //***************************************************************************** // @@ -546,26 +546,26 @@ // This bit is set when the comparator matches, and indicates that the // operation defined by FUNCTION has occurred since this bit was last read. // This bit is cleared on read. -#define CPU_DWT_FUNCTION1_MATCHED 0x01000000 -#define CPU_DWT_FUNCTION1_MATCHED_BITN 24 -#define CPU_DWT_FUNCTION1_MATCHED_M 0x01000000 -#define CPU_DWT_FUNCTION1_MATCHED_S 24 +#define CPU_DWT_FUNCTION1_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION1_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION1_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION1_MATCHED_S 24 // Field: [19:16] DATAVADDR1 // // Identity of a second linked address comparator for data value matching when // DATAVMATCH == 1 and LNK1ENA == 1. -#define CPU_DWT_FUNCTION1_DATAVADDR1_W 4 -#define CPU_DWT_FUNCTION1_DATAVADDR1_M 0x000F0000 -#define CPU_DWT_FUNCTION1_DATAVADDR1_S 16 +#define CPU_DWT_FUNCTION1_DATAVADDR1_W 4 +#define CPU_DWT_FUNCTION1_DATAVADDR1_M 0x000F0000 +#define CPU_DWT_FUNCTION1_DATAVADDR1_S 16 // Field: [15:12] DATAVADDR0 // // Identity of a linked address comparator for data value matching when // DATAVMATCH == 1. -#define CPU_DWT_FUNCTION1_DATAVADDR0_W 4 -#define CPU_DWT_FUNCTION1_DATAVADDR0_M 0x0000F000 -#define CPU_DWT_FUNCTION1_DATAVADDR0_S 12 +#define CPU_DWT_FUNCTION1_DATAVADDR0_W 4 +#define CPU_DWT_FUNCTION1_DATAVADDR0_M 0x0000F000 +#define CPU_DWT_FUNCTION1_DATAVADDR0_S 12 // Field: [11:10] DATAVSIZE // @@ -575,9 +575,9 @@ // 0x1: Halfword // 0x2: Word // 0x3: Unpredictable. -#define CPU_DWT_FUNCTION1_DATAVSIZE_W 2 -#define CPU_DWT_FUNCTION1_DATAVSIZE_M 0x00000C00 -#define CPU_DWT_FUNCTION1_DATAVSIZE_S 10 +#define CPU_DWT_FUNCTION1_DATAVSIZE_W 2 +#define CPU_DWT_FUNCTION1_DATAVSIZE_M 0x00000C00 +#define CPU_DWT_FUNCTION1_DATAVSIZE_S 10 // Field: [9] LNK1ENA // @@ -585,10 +585,10 @@ // // 0: DATAVADDR1 not supported // 1: DATAVADDR1 supported (enabled) -#define CPU_DWT_FUNCTION1_LNK1ENA 0x00000200 -#define CPU_DWT_FUNCTION1_LNK1ENA_BITN 9 -#define CPU_DWT_FUNCTION1_LNK1ENA_M 0x00000200 -#define CPU_DWT_FUNCTION1_LNK1ENA_S 9 +#define CPU_DWT_FUNCTION1_LNK1ENA 0x00000200 +#define CPU_DWT_FUNCTION1_LNK1ENA_BITN 9 +#define CPU_DWT_FUNCTION1_LNK1ENA_M 0x00000200 +#define CPU_DWT_FUNCTION1_LNK1ENA_S 9 // Field: [8] DATAVMATCH // @@ -601,20 +601,20 @@ // those comparators only provide the address match for the data comparison. // // This bit is only available in comparator 1. -#define CPU_DWT_FUNCTION1_DATAVMATCH 0x00000100 -#define CPU_DWT_FUNCTION1_DATAVMATCH_BITN 8 -#define CPU_DWT_FUNCTION1_DATAVMATCH_M 0x00000100 -#define CPU_DWT_FUNCTION1_DATAVMATCH_S 8 +#define CPU_DWT_FUNCTION1_DATAVMATCH 0x00000100 +#define CPU_DWT_FUNCTION1_DATAVMATCH_BITN 8 +#define CPU_DWT_FUNCTION1_DATAVMATCH_M 0x00000100 +#define CPU_DWT_FUNCTION1_DATAVMATCH_S 8 // Field: [5] EMITRANGE // // Emit range field. This bit permits emitting offset when range match occurs. // PC sampling is not supported when emit range is enabled. // This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. -#define CPU_DWT_FUNCTION1_EMITRANGE 0x00000020 -#define CPU_DWT_FUNCTION1_EMITRANGE_BITN 5 -#define CPU_DWT_FUNCTION1_EMITRANGE_M 0x00000020 -#define CPU_DWT_FUNCTION1_EMITRANGE_S 5 +#define CPU_DWT_FUNCTION1_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION1_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION1_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION1_EMITRANGE_S 5 // Field: [3:0] FUNCTION // @@ -660,9 +660,9 @@ // reading DATAVMATCH. If it is not settable then data matching is unavailable. // Note 5: PC match is not recommended for watchpoints because it stops after // the instruction. It mainly guards and triggers the ETM. -#define CPU_DWT_FUNCTION1_FUNCTION_W 4 -#define CPU_DWT_FUNCTION1_FUNCTION_M 0x0000000F -#define CPU_DWT_FUNCTION1_FUNCTION_S 0 +#define CPU_DWT_FUNCTION1_FUNCTION_W 4 +#define CPU_DWT_FUNCTION1_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION1_FUNCTION_S 0 //***************************************************************************** // @@ -673,9 +673,9 @@ // // Reference value to compare against PC or the data address as given by // FUNCTION2. -#define CPU_DWT_COMP2_COMP_W 32 -#define CPU_DWT_COMP2_COMP_M 0xFFFFFFFF -#define CPU_DWT_COMP2_COMP_S 0 +#define CPU_DWT_COMP2_COMP_W 32 +#define CPU_DWT_COMP2_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP2_COMP_S 0 //***************************************************************************** // @@ -690,9 +690,9 @@ // slightly more complex to enable matching an address wherever it appears on a // bus. So, if COMP2 is 3, this matches a word access of 0, because 3 would be // within the word. -#define CPU_DWT_MASK2_MASK_W 4 -#define CPU_DWT_MASK2_MASK_M 0x0000000F -#define CPU_DWT_MASK2_MASK_S 0 +#define CPU_DWT_MASK2_MASK_W 4 +#define CPU_DWT_MASK2_MASK_M 0x0000000F +#define CPU_DWT_MASK2_MASK_S 0 //***************************************************************************** // @@ -704,20 +704,20 @@ // This bit is set when the comparator matches, and indicates that the // operation defined by FUNCTION has occurred since this bit was last read. // This bit is cleared on read. -#define CPU_DWT_FUNCTION2_MATCHED 0x01000000 -#define CPU_DWT_FUNCTION2_MATCHED_BITN 24 -#define CPU_DWT_FUNCTION2_MATCHED_M 0x01000000 -#define CPU_DWT_FUNCTION2_MATCHED_S 24 +#define CPU_DWT_FUNCTION2_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION2_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION2_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION2_MATCHED_S 24 // Field: [5] EMITRANGE // // Emit range field. This bit permits emitting offset when range match occurs. // PC sampling is not supported when emit range is enabled. // This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. -#define CPU_DWT_FUNCTION2_EMITRANGE 0x00000020 -#define CPU_DWT_FUNCTION2_EMITRANGE_BITN 5 -#define CPU_DWT_FUNCTION2_EMITRANGE_M 0x00000020 -#define CPU_DWT_FUNCTION2_EMITRANGE_S 5 +#define CPU_DWT_FUNCTION2_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION2_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION2_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION2_EMITRANGE_S 5 // Field: [3:0] FUNCTION // @@ -754,9 +754,9 @@ // sampled for the first address of a burst. // Note 3: PC match is not recommended for watchpoints because it stops after // the instruction. It mainly guards and triggers the ETM. -#define CPU_DWT_FUNCTION2_FUNCTION_W 4 -#define CPU_DWT_FUNCTION2_FUNCTION_M 0x0000000F -#define CPU_DWT_FUNCTION2_FUNCTION_S 0 +#define CPU_DWT_FUNCTION2_FUNCTION_W 4 +#define CPU_DWT_FUNCTION2_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION2_FUNCTION_S 0 //***************************************************************************** // @@ -767,9 +767,9 @@ // // Reference value to compare against PC or the data address as given by // FUNCTION3. -#define CPU_DWT_COMP3_COMP_W 32 -#define CPU_DWT_COMP3_COMP_M 0xFFFFFFFF -#define CPU_DWT_COMP3_COMP_S 0 +#define CPU_DWT_COMP3_COMP_W 32 +#define CPU_DWT_COMP3_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP3_COMP_S 0 //***************************************************************************** // @@ -784,9 +784,9 @@ // slightly more complex to enable matching an address wherever it appears on a // bus. So, if COMP3 is 3, this matches a word access of 0, because 3 would be // within the word. -#define CPU_DWT_MASK3_MASK_W 4 -#define CPU_DWT_MASK3_MASK_M 0x0000000F -#define CPU_DWT_MASK3_MASK_S 0 +#define CPU_DWT_MASK3_MASK_W 4 +#define CPU_DWT_MASK3_MASK_M 0x0000000F +#define CPU_DWT_MASK3_MASK_S 0 //***************************************************************************** // @@ -798,20 +798,20 @@ // This bit is set when the comparator matches, and indicates that the // operation defined by FUNCTION has occurred since this bit was last read. // This bit is cleared on read. -#define CPU_DWT_FUNCTION3_MATCHED 0x01000000 -#define CPU_DWT_FUNCTION3_MATCHED_BITN 24 -#define CPU_DWT_FUNCTION3_MATCHED_M 0x01000000 -#define CPU_DWT_FUNCTION3_MATCHED_S 24 +#define CPU_DWT_FUNCTION3_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION3_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION3_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION3_MATCHED_S 24 // Field: [5] EMITRANGE // // Emit range field. This bit permits emitting offset when range match occurs. // PC sampling is not supported when emit range is enabled. // This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. -#define CPU_DWT_FUNCTION3_EMITRANGE 0x00000020 -#define CPU_DWT_FUNCTION3_EMITRANGE_BITN 5 -#define CPU_DWT_FUNCTION3_EMITRANGE_M 0x00000020 -#define CPU_DWT_FUNCTION3_EMITRANGE_S 5 +#define CPU_DWT_FUNCTION3_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION3_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION3_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION3_EMITRANGE_S 5 // Field: [3:0] FUNCTION // @@ -848,9 +848,8 @@ // sampled for the first address of a burst. // Note 3: PC match is not recommended for watchpoints because it stops after // the instruction. It mainly guards and triggers the ETM. -#define CPU_DWT_FUNCTION3_FUNCTION_W 4 -#define CPU_DWT_FUNCTION3_FUNCTION_M 0x0000000F -#define CPU_DWT_FUNCTION3_FUNCTION_S 0 - +#define CPU_DWT_FUNCTION3_FUNCTION_W 4 +#define CPU_DWT_FUNCTION3_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION3_FUNCTION_S 0 #endif // __CPU_DWT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_fpb.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_fpb.h index c87fab0..305f194 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_fpb.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_fpb.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_cpu_fpb_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_cpu_fpb_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CPU_FPB_H__ #define __HW_CPU_FPB_H__ @@ -44,34 +44,34 @@ // //***************************************************************************** // Control -#define CPU_FPB_O_CTRL 0x00000000 +#define CPU_FPB_O_CTRL 0x00000000 // Remap -#define CPU_FPB_O_REMAP 0x00000004 +#define CPU_FPB_O_REMAP 0x00000004 // Comparator 0 -#define CPU_FPB_O_COMP0 0x00000008 +#define CPU_FPB_O_COMP0 0x00000008 // Comparator 1 -#define CPU_FPB_O_COMP1 0x0000000C +#define CPU_FPB_O_COMP1 0x0000000C // Comparator 2 -#define CPU_FPB_O_COMP2 0x00000010 +#define CPU_FPB_O_COMP2 0x00000010 // Comparator 3 -#define CPU_FPB_O_COMP3 0x00000014 +#define CPU_FPB_O_COMP3 0x00000014 // Comparator 4 -#define CPU_FPB_O_COMP4 0x00000018 +#define CPU_FPB_O_COMP4 0x00000018 // Comparator 5 -#define CPU_FPB_O_COMP5 0x0000001C +#define CPU_FPB_O_COMP5 0x0000001C // Comparator 6 -#define CPU_FPB_O_COMP6 0x00000020 +#define CPU_FPB_O_COMP6 0x00000020 // Comparator 7 -#define CPU_FPB_O_COMP7 0x00000024 +#define CPU_FPB_O_COMP7 0x00000024 //***************************************************************************** // @@ -84,9 +84,9 @@ // Where less than sixteen code comparators are provided, the bank count is // zero, and the number present indicated by NUM_CODE1. This read only field // contains 3'b000 to indicate 0 banks for Cortex-M processor. -#define CPU_FPB_CTRL_NUM_CODE2_W 2 -#define CPU_FPB_CTRL_NUM_CODE2_M 0x00003000 -#define CPU_FPB_CTRL_NUM_CODE2_S 12 +#define CPU_FPB_CTRL_NUM_CODE2_W 2 +#define CPU_FPB_CTRL_NUM_CODE2_M 0x00003000 +#define CPU_FPB_CTRL_NUM_CODE2_S 12 // Field: [11:8] NUM_LIT // @@ -94,9 +94,9 @@ // // 0x0: No literal slots // 0x2: Two literal slots -#define CPU_FPB_CTRL_NUM_LIT_W 4 -#define CPU_FPB_CTRL_NUM_LIT_M 0x00000F00 -#define CPU_FPB_CTRL_NUM_LIT_S 8 +#define CPU_FPB_CTRL_NUM_LIT_W 4 +#define CPU_FPB_CTRL_NUM_LIT_M 0x00000F00 +#define CPU_FPB_CTRL_NUM_LIT_S 8 // Field: [7:4] NUM_CODE1 // @@ -105,18 +105,18 @@ // 0x0: No code slots // 0x2: Two code slots // 0x6: Six code slots -#define CPU_FPB_CTRL_NUM_CODE1_W 4 -#define CPU_FPB_CTRL_NUM_CODE1_M 0x000000F0 -#define CPU_FPB_CTRL_NUM_CODE1_S 4 +#define CPU_FPB_CTRL_NUM_CODE1_W 4 +#define CPU_FPB_CTRL_NUM_CODE1_M 0x000000F0 +#define CPU_FPB_CTRL_NUM_CODE1_S 4 // Field: [1] KEY // // Key field. In order to write to this register, this bit-field must be // written to '1'. This bit always reads 0. -#define CPU_FPB_CTRL_KEY 0x00000002 -#define CPU_FPB_CTRL_KEY_BITN 1 -#define CPU_FPB_CTRL_KEY_M 0x00000002 -#define CPU_FPB_CTRL_KEY_S 1 +#define CPU_FPB_CTRL_KEY 0x00000002 +#define CPU_FPB_CTRL_KEY_BITN 1 +#define CPU_FPB_CTRL_KEY_M 0x00000002 +#define CPU_FPB_CTRL_KEY_S 1 // Field: [0] ENABLE // @@ -124,10 +124,10 @@ // // 0x0: Flash patch unit disabled // 0x1: Flash patch unit enabled -#define CPU_FPB_CTRL_ENABLE 0x00000001 -#define CPU_FPB_CTRL_ENABLE_BITN 0 -#define CPU_FPB_CTRL_ENABLE_M 0x00000001 -#define CPU_FPB_CTRL_ENABLE_S 0 +#define CPU_FPB_CTRL_ENABLE 0x00000001 +#define CPU_FPB_CTRL_ENABLE_BITN 0 +#define CPU_FPB_CTRL_ENABLE_M 0x00000001 +#define CPU_FPB_CTRL_ENABLE_S 0 //***************************************************************************** // @@ -137,9 +137,9 @@ // Field: [28:5] REMAP // // Remap base address field. -#define CPU_FPB_REMAP_REMAP_W 24 -#define CPU_FPB_REMAP_REMAP_M 0x1FFFFFE0 -#define CPU_FPB_REMAP_REMAP_S 5 +#define CPU_FPB_REMAP_REMAP_W 24 +#define CPU_FPB_REMAP_REMAP_M 0x1FFFFFE0 +#define CPU_FPB_REMAP_REMAP_S 5 //***************************************************************************** // @@ -155,16 +155,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP0_REPLACE_W 2 -#define CPU_FPB_COMP0_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP0_REPLACE_S 30 +#define CPU_FPB_COMP0_REPLACE_W 2 +#define CPU_FPB_COMP0_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP0_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP0_COMP_W 27 -#define CPU_FPB_COMP0_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP0_COMP_S 2 +#define CPU_FPB_COMP0_COMP_W 27 +#define CPU_FPB_COMP0_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP0_COMP_S 2 // Field: [0] ENABLE // @@ -173,10 +173,10 @@ // // 0x0: Compare and remap for comparator 0 disabled // 0x1: Compare and remap for comparator 0 enabled -#define CPU_FPB_COMP0_ENABLE 0x00000001 -#define CPU_FPB_COMP0_ENABLE_BITN 0 -#define CPU_FPB_COMP0_ENABLE_M 0x00000001 -#define CPU_FPB_COMP0_ENABLE_S 0 +#define CPU_FPB_COMP0_ENABLE 0x00000001 +#define CPU_FPB_COMP0_ENABLE_BITN 0 +#define CPU_FPB_COMP0_ENABLE_M 0x00000001 +#define CPU_FPB_COMP0_ENABLE_S 0 //***************************************************************************** // @@ -192,16 +192,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP1_REPLACE_W 2 -#define CPU_FPB_COMP1_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP1_REPLACE_S 30 +#define CPU_FPB_COMP1_REPLACE_W 2 +#define CPU_FPB_COMP1_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP1_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP1_COMP_W 27 -#define CPU_FPB_COMP1_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP1_COMP_S 2 +#define CPU_FPB_COMP1_COMP_W 27 +#define CPU_FPB_COMP1_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP1_COMP_S 2 // Field: [0] ENABLE // @@ -210,10 +210,10 @@ // // 0x0: Compare and remap for comparator 1 disabled // 0x1: Compare and remap for comparator 1 enabled -#define CPU_FPB_COMP1_ENABLE 0x00000001 -#define CPU_FPB_COMP1_ENABLE_BITN 0 -#define CPU_FPB_COMP1_ENABLE_M 0x00000001 -#define CPU_FPB_COMP1_ENABLE_S 0 +#define CPU_FPB_COMP1_ENABLE 0x00000001 +#define CPU_FPB_COMP1_ENABLE_BITN 0 +#define CPU_FPB_COMP1_ENABLE_M 0x00000001 +#define CPU_FPB_COMP1_ENABLE_S 0 //***************************************************************************** // @@ -229,16 +229,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP2_REPLACE_W 2 -#define CPU_FPB_COMP2_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP2_REPLACE_S 30 +#define CPU_FPB_COMP2_REPLACE_W 2 +#define CPU_FPB_COMP2_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP2_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP2_COMP_W 27 -#define CPU_FPB_COMP2_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP2_COMP_S 2 +#define CPU_FPB_COMP2_COMP_W 27 +#define CPU_FPB_COMP2_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP2_COMP_S 2 // Field: [0] ENABLE // @@ -247,10 +247,10 @@ // // 0x0: Compare and remap for comparator 2 disabled // 0x1: Compare and remap for comparator 2 enabled -#define CPU_FPB_COMP2_ENABLE 0x00000001 -#define CPU_FPB_COMP2_ENABLE_BITN 0 -#define CPU_FPB_COMP2_ENABLE_M 0x00000001 -#define CPU_FPB_COMP2_ENABLE_S 0 +#define CPU_FPB_COMP2_ENABLE 0x00000001 +#define CPU_FPB_COMP2_ENABLE_BITN 0 +#define CPU_FPB_COMP2_ENABLE_M 0x00000001 +#define CPU_FPB_COMP2_ENABLE_S 0 //***************************************************************************** // @@ -266,16 +266,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP3_REPLACE_W 2 -#define CPU_FPB_COMP3_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP3_REPLACE_S 30 +#define CPU_FPB_COMP3_REPLACE_W 2 +#define CPU_FPB_COMP3_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP3_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP3_COMP_W 27 -#define CPU_FPB_COMP3_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP3_COMP_S 2 +#define CPU_FPB_COMP3_COMP_W 27 +#define CPU_FPB_COMP3_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP3_COMP_S 2 // Field: [0] ENABLE // @@ -284,10 +284,10 @@ // // 0x0: Compare and remap for comparator 3 disabled // 0x1: Compare and remap for comparator 3 enabled -#define CPU_FPB_COMP3_ENABLE 0x00000001 -#define CPU_FPB_COMP3_ENABLE_BITN 0 -#define CPU_FPB_COMP3_ENABLE_M 0x00000001 -#define CPU_FPB_COMP3_ENABLE_S 0 +#define CPU_FPB_COMP3_ENABLE 0x00000001 +#define CPU_FPB_COMP3_ENABLE_BITN 0 +#define CPU_FPB_COMP3_ENABLE_M 0x00000001 +#define CPU_FPB_COMP3_ENABLE_S 0 //***************************************************************************** // @@ -303,16 +303,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP4_REPLACE_W 2 -#define CPU_FPB_COMP4_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP4_REPLACE_S 30 +#define CPU_FPB_COMP4_REPLACE_W 2 +#define CPU_FPB_COMP4_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP4_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP4_COMP_W 27 -#define CPU_FPB_COMP4_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP4_COMP_S 2 +#define CPU_FPB_COMP4_COMP_W 27 +#define CPU_FPB_COMP4_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP4_COMP_S 2 // Field: [0] ENABLE // @@ -321,10 +321,10 @@ // // 0x0: Compare and remap for comparator 4 disabled // 0x1: Compare and remap for comparator 4 enabled -#define CPU_FPB_COMP4_ENABLE 0x00000001 -#define CPU_FPB_COMP4_ENABLE_BITN 0 -#define CPU_FPB_COMP4_ENABLE_M 0x00000001 -#define CPU_FPB_COMP4_ENABLE_S 0 +#define CPU_FPB_COMP4_ENABLE 0x00000001 +#define CPU_FPB_COMP4_ENABLE_BITN 0 +#define CPU_FPB_COMP4_ENABLE_M 0x00000001 +#define CPU_FPB_COMP4_ENABLE_S 0 //***************************************************************************** // @@ -340,16 +340,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP5_REPLACE_W 2 -#define CPU_FPB_COMP5_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP5_REPLACE_S 30 +#define CPU_FPB_COMP5_REPLACE_W 2 +#define CPU_FPB_COMP5_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP5_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP5_COMP_W 27 -#define CPU_FPB_COMP5_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP5_COMP_S 2 +#define CPU_FPB_COMP5_COMP_W 27 +#define CPU_FPB_COMP5_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP5_COMP_S 2 // Field: [0] ENABLE // @@ -358,10 +358,10 @@ // // 0x0: Compare and remap for comparator 5 disabled // 0x1: Compare and remap for comparator 5 enabled -#define CPU_FPB_COMP5_ENABLE 0x00000001 -#define CPU_FPB_COMP5_ENABLE_BITN 0 -#define CPU_FPB_COMP5_ENABLE_M 0x00000001 -#define CPU_FPB_COMP5_ENABLE_S 0 +#define CPU_FPB_COMP5_ENABLE 0x00000001 +#define CPU_FPB_COMP5_ENABLE_BITN 0 +#define CPU_FPB_COMP5_ENABLE_M 0x00000001 +#define CPU_FPB_COMP5_ENABLE_S 0 //***************************************************************************** // @@ -378,16 +378,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP6_REPLACE_W 2 -#define CPU_FPB_COMP6_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP6_REPLACE_S 30 +#define CPU_FPB_COMP6_REPLACE_W 2 +#define CPU_FPB_COMP6_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP6_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP6_COMP_W 27 -#define CPU_FPB_COMP6_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP6_COMP_S 2 +#define CPU_FPB_COMP6_COMP_W 27 +#define CPU_FPB_COMP6_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP6_COMP_S 2 // Field: [0] ENABLE // @@ -396,10 +396,10 @@ // // 0x0: Compare and remap for comparator 6 disabled // 0x1: Compare and remap for comparator 6 enabled -#define CPU_FPB_COMP6_ENABLE 0x00000001 -#define CPU_FPB_COMP6_ENABLE_BITN 0 -#define CPU_FPB_COMP6_ENABLE_M 0x00000001 -#define CPU_FPB_COMP6_ENABLE_S 0 +#define CPU_FPB_COMP6_ENABLE 0x00000001 +#define CPU_FPB_COMP6_ENABLE_BITN 0 +#define CPU_FPB_COMP6_ENABLE_M 0x00000001 +#define CPU_FPB_COMP6_ENABLE_S 0 //***************************************************************************** // @@ -416,16 +416,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP7_REPLACE_W 2 -#define CPU_FPB_COMP7_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP7_REPLACE_S 30 +#define CPU_FPB_COMP7_REPLACE_W 2 +#define CPU_FPB_COMP7_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP7_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP7_COMP_W 27 -#define CPU_FPB_COMP7_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP7_COMP_S 2 +#define CPU_FPB_COMP7_COMP_W 27 +#define CPU_FPB_COMP7_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP7_COMP_S 2 // Field: [0] ENABLE // @@ -434,10 +434,9 @@ // // 0x0: Compare and remap for comparator 7 disabled // 0x1: Compare and remap for comparator 7 enabled -#define CPU_FPB_COMP7_ENABLE 0x00000001 -#define CPU_FPB_COMP7_ENABLE_BITN 0 -#define CPU_FPB_COMP7_ENABLE_M 0x00000001 -#define CPU_FPB_COMP7_ENABLE_S 0 - +#define CPU_FPB_COMP7_ENABLE 0x00000001 +#define CPU_FPB_COMP7_ENABLE_BITN 0 +#define CPU_FPB_COMP7_ENABLE_M 0x00000001 +#define CPU_FPB_COMP7_ENABLE_S 0 #endif // __CPU_FPB__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_itm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_itm.h index 528e1e8..b004984 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_itm.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_itm.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_cpu_itm_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_cpu_itm_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CPU_ITM_H__ #define __HW_CPU_ITM_H__ @@ -44,115 +44,115 @@ // //***************************************************************************** // Stimulus Port 0 -#define CPU_ITM_O_STIM0 0x00000000 +#define CPU_ITM_O_STIM0 0x00000000 // Stimulus Port 1 -#define CPU_ITM_O_STIM1 0x00000004 +#define CPU_ITM_O_STIM1 0x00000004 // Stimulus Port 2 -#define CPU_ITM_O_STIM2 0x00000008 +#define CPU_ITM_O_STIM2 0x00000008 // Stimulus Port 3 -#define CPU_ITM_O_STIM3 0x0000000C +#define CPU_ITM_O_STIM3 0x0000000C // Stimulus Port 4 -#define CPU_ITM_O_STIM4 0x00000010 +#define CPU_ITM_O_STIM4 0x00000010 // Stimulus Port 5 -#define CPU_ITM_O_STIM5 0x00000014 +#define CPU_ITM_O_STIM5 0x00000014 // Stimulus Port 6 -#define CPU_ITM_O_STIM6 0x00000018 +#define CPU_ITM_O_STIM6 0x00000018 // Stimulus Port 7 -#define CPU_ITM_O_STIM7 0x0000001C +#define CPU_ITM_O_STIM7 0x0000001C // Stimulus Port 8 -#define CPU_ITM_O_STIM8 0x00000020 +#define CPU_ITM_O_STIM8 0x00000020 // Stimulus Port 9 -#define CPU_ITM_O_STIM9 0x00000024 +#define CPU_ITM_O_STIM9 0x00000024 // Stimulus Port 10 -#define CPU_ITM_O_STIM10 0x00000028 +#define CPU_ITM_O_STIM10 0x00000028 // Stimulus Port 11 -#define CPU_ITM_O_STIM11 0x0000002C +#define CPU_ITM_O_STIM11 0x0000002C // Stimulus Port 12 -#define CPU_ITM_O_STIM12 0x00000030 +#define CPU_ITM_O_STIM12 0x00000030 // Stimulus Port 13 -#define CPU_ITM_O_STIM13 0x00000034 +#define CPU_ITM_O_STIM13 0x00000034 // Stimulus Port 14 -#define CPU_ITM_O_STIM14 0x00000038 +#define CPU_ITM_O_STIM14 0x00000038 // Stimulus Port 15 -#define CPU_ITM_O_STIM15 0x0000003C +#define CPU_ITM_O_STIM15 0x0000003C // Stimulus Port 16 -#define CPU_ITM_O_STIM16 0x00000040 +#define CPU_ITM_O_STIM16 0x00000040 // Stimulus Port 17 -#define CPU_ITM_O_STIM17 0x00000044 +#define CPU_ITM_O_STIM17 0x00000044 // Stimulus Port 18 -#define CPU_ITM_O_STIM18 0x00000048 +#define CPU_ITM_O_STIM18 0x00000048 // Stimulus Port 19 -#define CPU_ITM_O_STIM19 0x0000004C +#define CPU_ITM_O_STIM19 0x0000004C // Stimulus Port 20 -#define CPU_ITM_O_STIM20 0x00000050 +#define CPU_ITM_O_STIM20 0x00000050 // Stimulus Port 21 -#define CPU_ITM_O_STIM21 0x00000054 +#define CPU_ITM_O_STIM21 0x00000054 // Stimulus Port 22 -#define CPU_ITM_O_STIM22 0x00000058 +#define CPU_ITM_O_STIM22 0x00000058 // Stimulus Port 23 -#define CPU_ITM_O_STIM23 0x0000005C +#define CPU_ITM_O_STIM23 0x0000005C // Stimulus Port 24 -#define CPU_ITM_O_STIM24 0x00000060 +#define CPU_ITM_O_STIM24 0x00000060 // Stimulus Port 25 -#define CPU_ITM_O_STIM25 0x00000064 +#define CPU_ITM_O_STIM25 0x00000064 // Stimulus Port 26 -#define CPU_ITM_O_STIM26 0x00000068 +#define CPU_ITM_O_STIM26 0x00000068 // Stimulus Port 27 -#define CPU_ITM_O_STIM27 0x0000006C +#define CPU_ITM_O_STIM27 0x0000006C // Stimulus Port 28 -#define CPU_ITM_O_STIM28 0x00000070 +#define CPU_ITM_O_STIM28 0x00000070 // Stimulus Port 29 -#define CPU_ITM_O_STIM29 0x00000074 +#define CPU_ITM_O_STIM29 0x00000074 // Stimulus Port 30 -#define CPU_ITM_O_STIM30 0x00000078 +#define CPU_ITM_O_STIM30 0x00000078 // Stimulus Port 31 -#define CPU_ITM_O_STIM31 0x0000007C +#define CPU_ITM_O_STIM31 0x0000007C // Trace Enable -#define CPU_ITM_O_TER 0x00000E00 +#define CPU_ITM_O_TER 0x00000E00 // Trace Privilege -#define CPU_ITM_O_TPR 0x00000E40 +#define CPU_ITM_O_TPR 0x00000E40 // Trace Control -#define CPU_ITM_O_TCR 0x00000E80 +#define CPU_ITM_O_TCR 0x00000E80 // Lock Access -#define CPU_ITM_O_LAR 0x00000FB0 +#define CPU_ITM_O_LAR 0x00000FB0 // Lock Status -#define CPU_ITM_O_LSR 0x00000FB4 +#define CPU_ITM_O_LSR 0x00000FB4 //***************************************************************************** // @@ -167,9 +167,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM0_STIM0_W 32 -#define CPU_ITM_STIM0_STIM0_M 0xFFFFFFFF -#define CPU_ITM_STIM0_STIM0_S 0 +#define CPU_ITM_STIM0_STIM0_W 32 +#define CPU_ITM_STIM0_STIM0_M 0xFFFFFFFF +#define CPU_ITM_STIM0_STIM0_S 0 //***************************************************************************** // @@ -184,9 +184,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM1_STIM1_W 32 -#define CPU_ITM_STIM1_STIM1_M 0xFFFFFFFF -#define CPU_ITM_STIM1_STIM1_S 0 +#define CPU_ITM_STIM1_STIM1_W 32 +#define CPU_ITM_STIM1_STIM1_M 0xFFFFFFFF +#define CPU_ITM_STIM1_STIM1_S 0 //***************************************************************************** // @@ -201,9 +201,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM2_STIM2_W 32 -#define CPU_ITM_STIM2_STIM2_M 0xFFFFFFFF -#define CPU_ITM_STIM2_STIM2_S 0 +#define CPU_ITM_STIM2_STIM2_W 32 +#define CPU_ITM_STIM2_STIM2_M 0xFFFFFFFF +#define CPU_ITM_STIM2_STIM2_S 0 //***************************************************************************** // @@ -218,9 +218,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM3_STIM3_W 32 -#define CPU_ITM_STIM3_STIM3_M 0xFFFFFFFF -#define CPU_ITM_STIM3_STIM3_S 0 +#define CPU_ITM_STIM3_STIM3_W 32 +#define CPU_ITM_STIM3_STIM3_M 0xFFFFFFFF +#define CPU_ITM_STIM3_STIM3_S 0 //***************************************************************************** // @@ -235,9 +235,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM4_STIM4_W 32 -#define CPU_ITM_STIM4_STIM4_M 0xFFFFFFFF -#define CPU_ITM_STIM4_STIM4_S 0 +#define CPU_ITM_STIM4_STIM4_W 32 +#define CPU_ITM_STIM4_STIM4_M 0xFFFFFFFF +#define CPU_ITM_STIM4_STIM4_S 0 //***************************************************************************** // @@ -252,9 +252,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM5_STIM5_W 32 -#define CPU_ITM_STIM5_STIM5_M 0xFFFFFFFF -#define CPU_ITM_STIM5_STIM5_S 0 +#define CPU_ITM_STIM5_STIM5_W 32 +#define CPU_ITM_STIM5_STIM5_M 0xFFFFFFFF +#define CPU_ITM_STIM5_STIM5_S 0 //***************************************************************************** // @@ -269,9 +269,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM6_STIM6_W 32 -#define CPU_ITM_STIM6_STIM6_M 0xFFFFFFFF -#define CPU_ITM_STIM6_STIM6_S 0 +#define CPU_ITM_STIM6_STIM6_W 32 +#define CPU_ITM_STIM6_STIM6_M 0xFFFFFFFF +#define CPU_ITM_STIM6_STIM6_S 0 //***************************************************************************** // @@ -286,9 +286,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM7_STIM7_W 32 -#define CPU_ITM_STIM7_STIM7_M 0xFFFFFFFF -#define CPU_ITM_STIM7_STIM7_S 0 +#define CPU_ITM_STIM7_STIM7_W 32 +#define CPU_ITM_STIM7_STIM7_M 0xFFFFFFFF +#define CPU_ITM_STIM7_STIM7_S 0 //***************************************************************************** // @@ -303,9 +303,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM8_STIM8_W 32 -#define CPU_ITM_STIM8_STIM8_M 0xFFFFFFFF -#define CPU_ITM_STIM8_STIM8_S 0 +#define CPU_ITM_STIM8_STIM8_W 32 +#define CPU_ITM_STIM8_STIM8_M 0xFFFFFFFF +#define CPU_ITM_STIM8_STIM8_S 0 //***************************************************************************** // @@ -320,9 +320,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM9_STIM9_W 32 -#define CPU_ITM_STIM9_STIM9_M 0xFFFFFFFF -#define CPU_ITM_STIM9_STIM9_S 0 +#define CPU_ITM_STIM9_STIM9_W 32 +#define CPU_ITM_STIM9_STIM9_M 0xFFFFFFFF +#define CPU_ITM_STIM9_STIM9_S 0 //***************************************************************************** // @@ -337,9 +337,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM10_STIM10_W 32 -#define CPU_ITM_STIM10_STIM10_M 0xFFFFFFFF -#define CPU_ITM_STIM10_STIM10_S 0 +#define CPU_ITM_STIM10_STIM10_W 32 +#define CPU_ITM_STIM10_STIM10_M 0xFFFFFFFF +#define CPU_ITM_STIM10_STIM10_S 0 //***************************************************************************** // @@ -354,9 +354,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM11_STIM11_W 32 -#define CPU_ITM_STIM11_STIM11_M 0xFFFFFFFF -#define CPU_ITM_STIM11_STIM11_S 0 +#define CPU_ITM_STIM11_STIM11_W 32 +#define CPU_ITM_STIM11_STIM11_M 0xFFFFFFFF +#define CPU_ITM_STIM11_STIM11_S 0 //***************************************************************************** // @@ -371,9 +371,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM12_STIM12_W 32 -#define CPU_ITM_STIM12_STIM12_M 0xFFFFFFFF -#define CPU_ITM_STIM12_STIM12_S 0 +#define CPU_ITM_STIM12_STIM12_W 32 +#define CPU_ITM_STIM12_STIM12_M 0xFFFFFFFF +#define CPU_ITM_STIM12_STIM12_S 0 //***************************************************************************** // @@ -388,9 +388,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM13_STIM13_W 32 -#define CPU_ITM_STIM13_STIM13_M 0xFFFFFFFF -#define CPU_ITM_STIM13_STIM13_S 0 +#define CPU_ITM_STIM13_STIM13_W 32 +#define CPU_ITM_STIM13_STIM13_M 0xFFFFFFFF +#define CPU_ITM_STIM13_STIM13_S 0 //***************************************************************************** // @@ -405,9 +405,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM14_STIM14_W 32 -#define CPU_ITM_STIM14_STIM14_M 0xFFFFFFFF -#define CPU_ITM_STIM14_STIM14_S 0 +#define CPU_ITM_STIM14_STIM14_W 32 +#define CPU_ITM_STIM14_STIM14_M 0xFFFFFFFF +#define CPU_ITM_STIM14_STIM14_S 0 //***************************************************************************** // @@ -422,9 +422,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM15_STIM15_W 32 -#define CPU_ITM_STIM15_STIM15_M 0xFFFFFFFF -#define CPU_ITM_STIM15_STIM15_S 0 +#define CPU_ITM_STIM15_STIM15_W 32 +#define CPU_ITM_STIM15_STIM15_M 0xFFFFFFFF +#define CPU_ITM_STIM15_STIM15_S 0 //***************************************************************************** // @@ -439,9 +439,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM16_STIM16_W 32 -#define CPU_ITM_STIM16_STIM16_M 0xFFFFFFFF -#define CPU_ITM_STIM16_STIM16_S 0 +#define CPU_ITM_STIM16_STIM16_W 32 +#define CPU_ITM_STIM16_STIM16_M 0xFFFFFFFF +#define CPU_ITM_STIM16_STIM16_S 0 //***************************************************************************** // @@ -456,9 +456,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM17_STIM17_W 32 -#define CPU_ITM_STIM17_STIM17_M 0xFFFFFFFF -#define CPU_ITM_STIM17_STIM17_S 0 +#define CPU_ITM_STIM17_STIM17_W 32 +#define CPU_ITM_STIM17_STIM17_M 0xFFFFFFFF +#define CPU_ITM_STIM17_STIM17_S 0 //***************************************************************************** // @@ -473,9 +473,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM18_STIM18_W 32 -#define CPU_ITM_STIM18_STIM18_M 0xFFFFFFFF -#define CPU_ITM_STIM18_STIM18_S 0 +#define CPU_ITM_STIM18_STIM18_W 32 +#define CPU_ITM_STIM18_STIM18_M 0xFFFFFFFF +#define CPU_ITM_STIM18_STIM18_S 0 //***************************************************************************** // @@ -490,9 +490,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM19_STIM19_W 32 -#define CPU_ITM_STIM19_STIM19_M 0xFFFFFFFF -#define CPU_ITM_STIM19_STIM19_S 0 +#define CPU_ITM_STIM19_STIM19_W 32 +#define CPU_ITM_STIM19_STIM19_M 0xFFFFFFFF +#define CPU_ITM_STIM19_STIM19_S 0 //***************************************************************************** // @@ -507,9 +507,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM20_STIM20_W 32 -#define CPU_ITM_STIM20_STIM20_M 0xFFFFFFFF -#define CPU_ITM_STIM20_STIM20_S 0 +#define CPU_ITM_STIM20_STIM20_W 32 +#define CPU_ITM_STIM20_STIM20_M 0xFFFFFFFF +#define CPU_ITM_STIM20_STIM20_S 0 //***************************************************************************** // @@ -524,9 +524,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM21_STIM21_W 32 -#define CPU_ITM_STIM21_STIM21_M 0xFFFFFFFF -#define CPU_ITM_STIM21_STIM21_S 0 +#define CPU_ITM_STIM21_STIM21_W 32 +#define CPU_ITM_STIM21_STIM21_M 0xFFFFFFFF +#define CPU_ITM_STIM21_STIM21_S 0 //***************************************************************************** // @@ -541,9 +541,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM22_STIM22_W 32 -#define CPU_ITM_STIM22_STIM22_M 0xFFFFFFFF -#define CPU_ITM_STIM22_STIM22_S 0 +#define CPU_ITM_STIM22_STIM22_W 32 +#define CPU_ITM_STIM22_STIM22_M 0xFFFFFFFF +#define CPU_ITM_STIM22_STIM22_S 0 //***************************************************************************** // @@ -558,9 +558,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM23_STIM23_W 32 -#define CPU_ITM_STIM23_STIM23_M 0xFFFFFFFF -#define CPU_ITM_STIM23_STIM23_S 0 +#define CPU_ITM_STIM23_STIM23_W 32 +#define CPU_ITM_STIM23_STIM23_M 0xFFFFFFFF +#define CPU_ITM_STIM23_STIM23_S 0 //***************************************************************************** // @@ -575,9 +575,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM24_STIM24_W 32 -#define CPU_ITM_STIM24_STIM24_M 0xFFFFFFFF -#define CPU_ITM_STIM24_STIM24_S 0 +#define CPU_ITM_STIM24_STIM24_W 32 +#define CPU_ITM_STIM24_STIM24_M 0xFFFFFFFF +#define CPU_ITM_STIM24_STIM24_S 0 //***************************************************************************** // @@ -592,9 +592,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM25_STIM25_W 32 -#define CPU_ITM_STIM25_STIM25_M 0xFFFFFFFF -#define CPU_ITM_STIM25_STIM25_S 0 +#define CPU_ITM_STIM25_STIM25_W 32 +#define CPU_ITM_STIM25_STIM25_M 0xFFFFFFFF +#define CPU_ITM_STIM25_STIM25_S 0 //***************************************************************************** // @@ -609,9 +609,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM26_STIM26_W 32 -#define CPU_ITM_STIM26_STIM26_M 0xFFFFFFFF -#define CPU_ITM_STIM26_STIM26_S 0 +#define CPU_ITM_STIM26_STIM26_W 32 +#define CPU_ITM_STIM26_STIM26_M 0xFFFFFFFF +#define CPU_ITM_STIM26_STIM26_S 0 //***************************************************************************** // @@ -626,9 +626,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM27_STIM27_W 32 -#define CPU_ITM_STIM27_STIM27_M 0xFFFFFFFF -#define CPU_ITM_STIM27_STIM27_S 0 +#define CPU_ITM_STIM27_STIM27_W 32 +#define CPU_ITM_STIM27_STIM27_M 0xFFFFFFFF +#define CPU_ITM_STIM27_STIM27_S 0 //***************************************************************************** // @@ -643,9 +643,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM28_STIM28_W 32 -#define CPU_ITM_STIM28_STIM28_M 0xFFFFFFFF -#define CPU_ITM_STIM28_STIM28_S 0 +#define CPU_ITM_STIM28_STIM28_W 32 +#define CPU_ITM_STIM28_STIM28_M 0xFFFFFFFF +#define CPU_ITM_STIM28_STIM28_S 0 //***************************************************************************** // @@ -660,9 +660,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM29_STIM29_W 32 -#define CPU_ITM_STIM29_STIM29_M 0xFFFFFFFF -#define CPU_ITM_STIM29_STIM29_S 0 +#define CPU_ITM_STIM29_STIM29_W 32 +#define CPU_ITM_STIM29_STIM29_M 0xFFFFFFFF +#define CPU_ITM_STIM29_STIM29_S 0 //***************************************************************************** // @@ -677,9 +677,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM30_STIM30_W 32 -#define CPU_ITM_STIM30_STIM30_M 0xFFFFFFFF -#define CPU_ITM_STIM30_STIM30_S 0 +#define CPU_ITM_STIM30_STIM30_W 32 +#define CPU_ITM_STIM30_STIM30_M 0xFFFFFFFF +#define CPU_ITM_STIM30_STIM30_S 0 //***************************************************************************** // @@ -694,9 +694,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM31_STIM31_W 32 -#define CPU_ITM_STIM31_STIM31_M 0xFFFFFFFF -#define CPU_ITM_STIM31_STIM31_S 0 +#define CPU_ITM_STIM31_STIM31_W 32 +#define CPU_ITM_STIM31_STIM31_M 0xFFFFFFFF +#define CPU_ITM_STIM31_STIM31_S 0 //***************************************************************************** // @@ -706,258 +706,258 @@ // Field: [31] STIMENA31 // // Bit mask to enable tracing on ITM stimulus port 31. -#define CPU_ITM_TER_STIMENA31 0x80000000 -#define CPU_ITM_TER_STIMENA31_BITN 31 -#define CPU_ITM_TER_STIMENA31_M 0x80000000 -#define CPU_ITM_TER_STIMENA31_S 31 +#define CPU_ITM_TER_STIMENA31 0x80000000 +#define CPU_ITM_TER_STIMENA31_BITN 31 +#define CPU_ITM_TER_STIMENA31_M 0x80000000 +#define CPU_ITM_TER_STIMENA31_S 31 // Field: [30] STIMENA30 // // Bit mask to enable tracing on ITM stimulus port 30. -#define CPU_ITM_TER_STIMENA30 0x40000000 -#define CPU_ITM_TER_STIMENA30_BITN 30 -#define CPU_ITM_TER_STIMENA30_M 0x40000000 -#define CPU_ITM_TER_STIMENA30_S 30 +#define CPU_ITM_TER_STIMENA30 0x40000000 +#define CPU_ITM_TER_STIMENA30_BITN 30 +#define CPU_ITM_TER_STIMENA30_M 0x40000000 +#define CPU_ITM_TER_STIMENA30_S 30 // Field: [29] STIMENA29 // // Bit mask to enable tracing on ITM stimulus port 29. -#define CPU_ITM_TER_STIMENA29 0x20000000 -#define CPU_ITM_TER_STIMENA29_BITN 29 -#define CPU_ITM_TER_STIMENA29_M 0x20000000 -#define CPU_ITM_TER_STIMENA29_S 29 +#define CPU_ITM_TER_STIMENA29 0x20000000 +#define CPU_ITM_TER_STIMENA29_BITN 29 +#define CPU_ITM_TER_STIMENA29_M 0x20000000 +#define CPU_ITM_TER_STIMENA29_S 29 // Field: [28] STIMENA28 // // Bit mask to enable tracing on ITM stimulus port 28. -#define CPU_ITM_TER_STIMENA28 0x10000000 -#define CPU_ITM_TER_STIMENA28_BITN 28 -#define CPU_ITM_TER_STIMENA28_M 0x10000000 -#define CPU_ITM_TER_STIMENA28_S 28 +#define CPU_ITM_TER_STIMENA28 0x10000000 +#define CPU_ITM_TER_STIMENA28_BITN 28 +#define CPU_ITM_TER_STIMENA28_M 0x10000000 +#define CPU_ITM_TER_STIMENA28_S 28 // Field: [27] STIMENA27 // // Bit mask to enable tracing on ITM stimulus port 27. -#define CPU_ITM_TER_STIMENA27 0x08000000 -#define CPU_ITM_TER_STIMENA27_BITN 27 -#define CPU_ITM_TER_STIMENA27_M 0x08000000 -#define CPU_ITM_TER_STIMENA27_S 27 +#define CPU_ITM_TER_STIMENA27 0x08000000 +#define CPU_ITM_TER_STIMENA27_BITN 27 +#define CPU_ITM_TER_STIMENA27_M 0x08000000 +#define CPU_ITM_TER_STIMENA27_S 27 // Field: [26] STIMENA26 // // Bit mask to enable tracing on ITM stimulus port 26. -#define CPU_ITM_TER_STIMENA26 0x04000000 -#define CPU_ITM_TER_STIMENA26_BITN 26 -#define CPU_ITM_TER_STIMENA26_M 0x04000000 -#define CPU_ITM_TER_STIMENA26_S 26 +#define CPU_ITM_TER_STIMENA26 0x04000000 +#define CPU_ITM_TER_STIMENA26_BITN 26 +#define CPU_ITM_TER_STIMENA26_M 0x04000000 +#define CPU_ITM_TER_STIMENA26_S 26 // Field: [25] STIMENA25 // // Bit mask to enable tracing on ITM stimulus port 25. -#define CPU_ITM_TER_STIMENA25 0x02000000 -#define CPU_ITM_TER_STIMENA25_BITN 25 -#define CPU_ITM_TER_STIMENA25_M 0x02000000 -#define CPU_ITM_TER_STIMENA25_S 25 +#define CPU_ITM_TER_STIMENA25 0x02000000 +#define CPU_ITM_TER_STIMENA25_BITN 25 +#define CPU_ITM_TER_STIMENA25_M 0x02000000 +#define CPU_ITM_TER_STIMENA25_S 25 // Field: [24] STIMENA24 // // Bit mask to enable tracing on ITM stimulus port 24. -#define CPU_ITM_TER_STIMENA24 0x01000000 -#define CPU_ITM_TER_STIMENA24_BITN 24 -#define CPU_ITM_TER_STIMENA24_M 0x01000000 -#define CPU_ITM_TER_STIMENA24_S 24 +#define CPU_ITM_TER_STIMENA24 0x01000000 +#define CPU_ITM_TER_STIMENA24_BITN 24 +#define CPU_ITM_TER_STIMENA24_M 0x01000000 +#define CPU_ITM_TER_STIMENA24_S 24 // Field: [23] STIMENA23 // // Bit mask to enable tracing on ITM stimulus port 23. -#define CPU_ITM_TER_STIMENA23 0x00800000 -#define CPU_ITM_TER_STIMENA23_BITN 23 -#define CPU_ITM_TER_STIMENA23_M 0x00800000 -#define CPU_ITM_TER_STIMENA23_S 23 +#define CPU_ITM_TER_STIMENA23 0x00800000 +#define CPU_ITM_TER_STIMENA23_BITN 23 +#define CPU_ITM_TER_STIMENA23_M 0x00800000 +#define CPU_ITM_TER_STIMENA23_S 23 // Field: [22] STIMENA22 // // Bit mask to enable tracing on ITM stimulus port 22. -#define CPU_ITM_TER_STIMENA22 0x00400000 -#define CPU_ITM_TER_STIMENA22_BITN 22 -#define CPU_ITM_TER_STIMENA22_M 0x00400000 -#define CPU_ITM_TER_STIMENA22_S 22 +#define CPU_ITM_TER_STIMENA22 0x00400000 +#define CPU_ITM_TER_STIMENA22_BITN 22 +#define CPU_ITM_TER_STIMENA22_M 0x00400000 +#define CPU_ITM_TER_STIMENA22_S 22 // Field: [21] STIMENA21 // // Bit mask to enable tracing on ITM stimulus port 21. -#define CPU_ITM_TER_STIMENA21 0x00200000 -#define CPU_ITM_TER_STIMENA21_BITN 21 -#define CPU_ITM_TER_STIMENA21_M 0x00200000 -#define CPU_ITM_TER_STIMENA21_S 21 +#define CPU_ITM_TER_STIMENA21 0x00200000 +#define CPU_ITM_TER_STIMENA21_BITN 21 +#define CPU_ITM_TER_STIMENA21_M 0x00200000 +#define CPU_ITM_TER_STIMENA21_S 21 // Field: [20] STIMENA20 // // Bit mask to enable tracing on ITM stimulus port 20. -#define CPU_ITM_TER_STIMENA20 0x00100000 -#define CPU_ITM_TER_STIMENA20_BITN 20 -#define CPU_ITM_TER_STIMENA20_M 0x00100000 -#define CPU_ITM_TER_STIMENA20_S 20 +#define CPU_ITM_TER_STIMENA20 0x00100000 +#define CPU_ITM_TER_STIMENA20_BITN 20 +#define CPU_ITM_TER_STIMENA20_M 0x00100000 +#define CPU_ITM_TER_STIMENA20_S 20 // Field: [19] STIMENA19 // // Bit mask to enable tracing on ITM stimulus port 19. -#define CPU_ITM_TER_STIMENA19 0x00080000 -#define CPU_ITM_TER_STIMENA19_BITN 19 -#define CPU_ITM_TER_STIMENA19_M 0x00080000 -#define CPU_ITM_TER_STIMENA19_S 19 +#define CPU_ITM_TER_STIMENA19 0x00080000 +#define CPU_ITM_TER_STIMENA19_BITN 19 +#define CPU_ITM_TER_STIMENA19_M 0x00080000 +#define CPU_ITM_TER_STIMENA19_S 19 // Field: [18] STIMENA18 // // Bit mask to enable tracing on ITM stimulus port 18. -#define CPU_ITM_TER_STIMENA18 0x00040000 -#define CPU_ITM_TER_STIMENA18_BITN 18 -#define CPU_ITM_TER_STIMENA18_M 0x00040000 -#define CPU_ITM_TER_STIMENA18_S 18 +#define CPU_ITM_TER_STIMENA18 0x00040000 +#define CPU_ITM_TER_STIMENA18_BITN 18 +#define CPU_ITM_TER_STIMENA18_M 0x00040000 +#define CPU_ITM_TER_STIMENA18_S 18 // Field: [17] STIMENA17 // // Bit mask to enable tracing on ITM stimulus port 17. -#define CPU_ITM_TER_STIMENA17 0x00020000 -#define CPU_ITM_TER_STIMENA17_BITN 17 -#define CPU_ITM_TER_STIMENA17_M 0x00020000 -#define CPU_ITM_TER_STIMENA17_S 17 +#define CPU_ITM_TER_STIMENA17 0x00020000 +#define CPU_ITM_TER_STIMENA17_BITN 17 +#define CPU_ITM_TER_STIMENA17_M 0x00020000 +#define CPU_ITM_TER_STIMENA17_S 17 // Field: [16] STIMENA16 // // Bit mask to enable tracing on ITM stimulus port 16. -#define CPU_ITM_TER_STIMENA16 0x00010000 -#define CPU_ITM_TER_STIMENA16_BITN 16 -#define CPU_ITM_TER_STIMENA16_M 0x00010000 -#define CPU_ITM_TER_STIMENA16_S 16 +#define CPU_ITM_TER_STIMENA16 0x00010000 +#define CPU_ITM_TER_STIMENA16_BITN 16 +#define CPU_ITM_TER_STIMENA16_M 0x00010000 +#define CPU_ITM_TER_STIMENA16_S 16 // Field: [15] STIMENA15 // // Bit mask to enable tracing on ITM stimulus port 15. -#define CPU_ITM_TER_STIMENA15 0x00008000 -#define CPU_ITM_TER_STIMENA15_BITN 15 -#define CPU_ITM_TER_STIMENA15_M 0x00008000 -#define CPU_ITM_TER_STIMENA15_S 15 +#define CPU_ITM_TER_STIMENA15 0x00008000 +#define CPU_ITM_TER_STIMENA15_BITN 15 +#define CPU_ITM_TER_STIMENA15_M 0x00008000 +#define CPU_ITM_TER_STIMENA15_S 15 // Field: [14] STIMENA14 // // Bit mask to enable tracing on ITM stimulus port 14. -#define CPU_ITM_TER_STIMENA14 0x00004000 -#define CPU_ITM_TER_STIMENA14_BITN 14 -#define CPU_ITM_TER_STIMENA14_M 0x00004000 -#define CPU_ITM_TER_STIMENA14_S 14 +#define CPU_ITM_TER_STIMENA14 0x00004000 +#define CPU_ITM_TER_STIMENA14_BITN 14 +#define CPU_ITM_TER_STIMENA14_M 0x00004000 +#define CPU_ITM_TER_STIMENA14_S 14 // Field: [13] STIMENA13 // // Bit mask to enable tracing on ITM stimulus port 13. -#define CPU_ITM_TER_STIMENA13 0x00002000 -#define CPU_ITM_TER_STIMENA13_BITN 13 -#define CPU_ITM_TER_STIMENA13_M 0x00002000 -#define CPU_ITM_TER_STIMENA13_S 13 +#define CPU_ITM_TER_STIMENA13 0x00002000 +#define CPU_ITM_TER_STIMENA13_BITN 13 +#define CPU_ITM_TER_STIMENA13_M 0x00002000 +#define CPU_ITM_TER_STIMENA13_S 13 // Field: [12] STIMENA12 // // Bit mask to enable tracing on ITM stimulus port 12. -#define CPU_ITM_TER_STIMENA12 0x00001000 -#define CPU_ITM_TER_STIMENA12_BITN 12 -#define CPU_ITM_TER_STIMENA12_M 0x00001000 -#define CPU_ITM_TER_STIMENA12_S 12 +#define CPU_ITM_TER_STIMENA12 0x00001000 +#define CPU_ITM_TER_STIMENA12_BITN 12 +#define CPU_ITM_TER_STIMENA12_M 0x00001000 +#define CPU_ITM_TER_STIMENA12_S 12 // Field: [11] STIMENA11 // // Bit mask to enable tracing on ITM stimulus port 11. -#define CPU_ITM_TER_STIMENA11 0x00000800 -#define CPU_ITM_TER_STIMENA11_BITN 11 -#define CPU_ITM_TER_STIMENA11_M 0x00000800 -#define CPU_ITM_TER_STIMENA11_S 11 +#define CPU_ITM_TER_STIMENA11 0x00000800 +#define CPU_ITM_TER_STIMENA11_BITN 11 +#define CPU_ITM_TER_STIMENA11_M 0x00000800 +#define CPU_ITM_TER_STIMENA11_S 11 // Field: [10] STIMENA10 // // Bit mask to enable tracing on ITM stimulus port 10. -#define CPU_ITM_TER_STIMENA10 0x00000400 -#define CPU_ITM_TER_STIMENA10_BITN 10 -#define CPU_ITM_TER_STIMENA10_M 0x00000400 -#define CPU_ITM_TER_STIMENA10_S 10 +#define CPU_ITM_TER_STIMENA10 0x00000400 +#define CPU_ITM_TER_STIMENA10_BITN 10 +#define CPU_ITM_TER_STIMENA10_M 0x00000400 +#define CPU_ITM_TER_STIMENA10_S 10 // Field: [9] STIMENA9 // // Bit mask to enable tracing on ITM stimulus port 9. -#define CPU_ITM_TER_STIMENA9 0x00000200 -#define CPU_ITM_TER_STIMENA9_BITN 9 -#define CPU_ITM_TER_STIMENA9_M 0x00000200 -#define CPU_ITM_TER_STIMENA9_S 9 +#define CPU_ITM_TER_STIMENA9 0x00000200 +#define CPU_ITM_TER_STIMENA9_BITN 9 +#define CPU_ITM_TER_STIMENA9_M 0x00000200 +#define CPU_ITM_TER_STIMENA9_S 9 // Field: [8] STIMENA8 // // Bit mask to enable tracing on ITM stimulus port 8. -#define CPU_ITM_TER_STIMENA8 0x00000100 -#define CPU_ITM_TER_STIMENA8_BITN 8 -#define CPU_ITM_TER_STIMENA8_M 0x00000100 -#define CPU_ITM_TER_STIMENA8_S 8 +#define CPU_ITM_TER_STIMENA8 0x00000100 +#define CPU_ITM_TER_STIMENA8_BITN 8 +#define CPU_ITM_TER_STIMENA8_M 0x00000100 +#define CPU_ITM_TER_STIMENA8_S 8 // Field: [7] STIMENA7 // // Bit mask to enable tracing on ITM stimulus port 7. -#define CPU_ITM_TER_STIMENA7 0x00000080 -#define CPU_ITM_TER_STIMENA7_BITN 7 -#define CPU_ITM_TER_STIMENA7_M 0x00000080 -#define CPU_ITM_TER_STIMENA7_S 7 +#define CPU_ITM_TER_STIMENA7 0x00000080 +#define CPU_ITM_TER_STIMENA7_BITN 7 +#define CPU_ITM_TER_STIMENA7_M 0x00000080 +#define CPU_ITM_TER_STIMENA7_S 7 // Field: [6] STIMENA6 // // Bit mask to enable tracing on ITM stimulus port 6. -#define CPU_ITM_TER_STIMENA6 0x00000040 -#define CPU_ITM_TER_STIMENA6_BITN 6 -#define CPU_ITM_TER_STIMENA6_M 0x00000040 -#define CPU_ITM_TER_STIMENA6_S 6 +#define CPU_ITM_TER_STIMENA6 0x00000040 +#define CPU_ITM_TER_STIMENA6_BITN 6 +#define CPU_ITM_TER_STIMENA6_M 0x00000040 +#define CPU_ITM_TER_STIMENA6_S 6 // Field: [5] STIMENA5 // // Bit mask to enable tracing on ITM stimulus port 5. -#define CPU_ITM_TER_STIMENA5 0x00000020 -#define CPU_ITM_TER_STIMENA5_BITN 5 -#define CPU_ITM_TER_STIMENA5_M 0x00000020 -#define CPU_ITM_TER_STIMENA5_S 5 +#define CPU_ITM_TER_STIMENA5 0x00000020 +#define CPU_ITM_TER_STIMENA5_BITN 5 +#define CPU_ITM_TER_STIMENA5_M 0x00000020 +#define CPU_ITM_TER_STIMENA5_S 5 // Field: [4] STIMENA4 // // Bit mask to enable tracing on ITM stimulus port 4. -#define CPU_ITM_TER_STIMENA4 0x00000010 -#define CPU_ITM_TER_STIMENA4_BITN 4 -#define CPU_ITM_TER_STIMENA4_M 0x00000010 -#define CPU_ITM_TER_STIMENA4_S 4 +#define CPU_ITM_TER_STIMENA4 0x00000010 +#define CPU_ITM_TER_STIMENA4_BITN 4 +#define CPU_ITM_TER_STIMENA4_M 0x00000010 +#define CPU_ITM_TER_STIMENA4_S 4 // Field: [3] STIMENA3 // // Bit mask to enable tracing on ITM stimulus port 3. -#define CPU_ITM_TER_STIMENA3 0x00000008 -#define CPU_ITM_TER_STIMENA3_BITN 3 -#define CPU_ITM_TER_STIMENA3_M 0x00000008 -#define CPU_ITM_TER_STIMENA3_S 3 +#define CPU_ITM_TER_STIMENA3 0x00000008 +#define CPU_ITM_TER_STIMENA3_BITN 3 +#define CPU_ITM_TER_STIMENA3_M 0x00000008 +#define CPU_ITM_TER_STIMENA3_S 3 // Field: [2] STIMENA2 // // Bit mask to enable tracing on ITM stimulus port 2. -#define CPU_ITM_TER_STIMENA2 0x00000004 -#define CPU_ITM_TER_STIMENA2_BITN 2 -#define CPU_ITM_TER_STIMENA2_M 0x00000004 -#define CPU_ITM_TER_STIMENA2_S 2 +#define CPU_ITM_TER_STIMENA2 0x00000004 +#define CPU_ITM_TER_STIMENA2_BITN 2 +#define CPU_ITM_TER_STIMENA2_M 0x00000004 +#define CPU_ITM_TER_STIMENA2_S 2 // Field: [1] STIMENA1 // // Bit mask to enable tracing on ITM stimulus port 1. -#define CPU_ITM_TER_STIMENA1 0x00000002 -#define CPU_ITM_TER_STIMENA1_BITN 1 -#define CPU_ITM_TER_STIMENA1_M 0x00000002 -#define CPU_ITM_TER_STIMENA1_S 1 +#define CPU_ITM_TER_STIMENA1 0x00000002 +#define CPU_ITM_TER_STIMENA1_BITN 1 +#define CPU_ITM_TER_STIMENA1_M 0x00000002 +#define CPU_ITM_TER_STIMENA1_S 1 // Field: [0] STIMENA0 // // Bit mask to enable tracing on ITM stimulus port 0. -#define CPU_ITM_TER_STIMENA0 0x00000001 -#define CPU_ITM_TER_STIMENA0_BITN 0 -#define CPU_ITM_TER_STIMENA0_M 0x00000001 -#define CPU_ITM_TER_STIMENA0_S 0 +#define CPU_ITM_TER_STIMENA0 0x00000001 +#define CPU_ITM_TER_STIMENA0_BITN 0 +#define CPU_ITM_TER_STIMENA0_M 0x00000001 +#define CPU_ITM_TER_STIMENA0_S 0 //***************************************************************************** // @@ -975,9 +975,9 @@ // // 0: User access allowed to stimulus ports // 1: Privileged access only to stimulus ports -#define CPU_ITM_TPR_PRIVMASK_W 4 -#define CPU_ITM_TPR_PRIVMASK_M 0x0000000F -#define CPU_ITM_TPR_PRIVMASK_S 0 +#define CPU_ITM_TPR_PRIVMASK_W 4 +#define CPU_ITM_TPR_PRIVMASK_M 0x0000000F +#define CPU_ITM_TPR_PRIVMASK_S 0 //***************************************************************************** // @@ -987,19 +987,19 @@ // Field: [23] BUSY // // Set when ITM events present and being drained. -#define CPU_ITM_TCR_BUSY 0x00800000 -#define CPU_ITM_TCR_BUSY_BITN 23 -#define CPU_ITM_TCR_BUSY_M 0x00800000 -#define CPU_ITM_TCR_BUSY_S 23 +#define CPU_ITM_TCR_BUSY 0x00800000 +#define CPU_ITM_TCR_BUSY_BITN 23 +#define CPU_ITM_TCR_BUSY_M 0x00800000 +#define CPU_ITM_TCR_BUSY_S 23 // Field: [22:16] ATBID // // Trace Bus ID for CoreSight system. Optional identifier for multi-source // trace stream formatting. If multi-source trace is in use, this field must be // written with a non-zero value. -#define CPU_ITM_TCR_ATBID_W 7 -#define CPU_ITM_TCR_ATBID_M 0x007F0000 -#define CPU_ITM_TCR_ATBID_S 16 +#define CPU_ITM_TCR_ATBID_W 7 +#define CPU_ITM_TCR_ATBID_M 0x007F0000 +#define CPU_ITM_TCR_ATBID_S 16 // Field: [9:8] TSPRESCALE // @@ -1009,13 +1009,13 @@ // DIV16 Divide by 16 // DIV4 Divide by 4 // NOPRESCALING No prescaling -#define CPU_ITM_TCR_TSPRESCALE_W 2 -#define CPU_ITM_TCR_TSPRESCALE_M 0x00000300 -#define CPU_ITM_TCR_TSPRESCALE_S 8 -#define CPU_ITM_TCR_TSPRESCALE_DIV64 0x00000300 -#define CPU_ITM_TCR_TSPRESCALE_DIV16 0x00000200 -#define CPU_ITM_TCR_TSPRESCALE_DIV4 0x00000100 -#define CPU_ITM_TCR_TSPRESCALE_NOPRESCALING 0x00000000 +#define CPU_ITM_TCR_TSPRESCALE_W 2 +#define CPU_ITM_TCR_TSPRESCALE_M 0x00000300 +#define CPU_ITM_TCR_TSPRESCALE_S 8 +#define CPU_ITM_TCR_TSPRESCALE_DIV64 0x00000300 +#define CPU_ITM_TCR_TSPRESCALE_DIV16 0x00000200 +#define CPU_ITM_TCR_TSPRESCALE_DIV4 0x00000100 +#define CPU_ITM_TCR_TSPRESCALE_NOPRESCALING 0x00000000 // Field: [4] SWOENA // @@ -1028,29 +1028,29 @@ // 0x1: Timestamp counter uses lineout (data related) clock from TPIU // interface. The timestamp counter is held in reset while the output line is // idle. -#define CPU_ITM_TCR_SWOENA 0x00000010 -#define CPU_ITM_TCR_SWOENA_BITN 4 -#define CPU_ITM_TCR_SWOENA_M 0x00000010 -#define CPU_ITM_TCR_SWOENA_S 4 +#define CPU_ITM_TCR_SWOENA 0x00000010 +#define CPU_ITM_TCR_SWOENA_BITN 4 +#define CPU_ITM_TCR_SWOENA_M 0x00000010 +#define CPU_ITM_TCR_SWOENA_S 4 // Field: [3] DWTENA // // Enables the DWT stimulus (hardware event packet emission to the TPIU from // the DWT) -#define CPU_ITM_TCR_DWTENA 0x00000008 -#define CPU_ITM_TCR_DWTENA_BITN 3 -#define CPU_ITM_TCR_DWTENA_M 0x00000008 -#define CPU_ITM_TCR_DWTENA_S 3 +#define CPU_ITM_TCR_DWTENA 0x00000008 +#define CPU_ITM_TCR_DWTENA_BITN 3 +#define CPU_ITM_TCR_DWTENA_M 0x00000008 +#define CPU_ITM_TCR_DWTENA_S 3 // Field: [2] SYNCENA // // Enables synchronization packet transmission for a synchronous TPIU. // CPU_DWT:CTRL.SYNCTAP must be configured for the correct synchronization // speed. -#define CPU_ITM_TCR_SYNCENA 0x00000004 -#define CPU_ITM_TCR_SYNCENA_BITN 2 -#define CPU_ITM_TCR_SYNCENA_M 0x00000004 -#define CPU_ITM_TCR_SYNCENA_S 2 +#define CPU_ITM_TCR_SYNCENA 0x00000004 +#define CPU_ITM_TCR_SYNCENA_BITN 2 +#define CPU_ITM_TCR_SYNCENA_M 0x00000004 +#define CPU_ITM_TCR_SYNCENA_S 2 // Field: [1] TSENA // @@ -1061,19 +1061,19 @@ // for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps // are triggered by activity on the internal trace bus only. In this case there // is no regular timestamp output when the ITM is idle. -#define CPU_ITM_TCR_TSENA 0x00000002 -#define CPU_ITM_TCR_TSENA_BITN 1 -#define CPU_ITM_TCR_TSENA_M 0x00000002 -#define CPU_ITM_TCR_TSENA_S 1 +#define CPU_ITM_TCR_TSENA 0x00000002 +#define CPU_ITM_TCR_TSENA_BITN 1 +#define CPU_ITM_TCR_TSENA_M 0x00000002 +#define CPU_ITM_TCR_TSENA_S 1 // Field: [0] ITMENA // // Enables ITM. This is the master enable, and must be set before ITM Stimulus // and Trace Enable registers can be written. -#define CPU_ITM_TCR_ITMENA 0x00000001 -#define CPU_ITM_TCR_ITMENA_BITN 0 -#define CPU_ITM_TCR_ITMENA_M 0x00000001 -#define CPU_ITM_TCR_ITMENA_S 0 +#define CPU_ITM_TCR_ITMENA 0x00000001 +#define CPU_ITM_TCR_ITMENA_BITN 0 +#define CPU_ITM_TCR_ITMENA_M 0x00000001 +#define CPU_ITM_TCR_ITMENA_S 0 //***************************************************************************** // @@ -1084,9 +1084,9 @@ // // A privileged write of 0xC5ACCE55 enables more write access to Control // Registers TER, TPR and TCR. An invalid write removes write access. -#define CPU_ITM_LAR_LOCK_ACCESS_W 32 -#define CPU_ITM_LAR_LOCK_ACCESS_M 0xFFFFFFFF -#define CPU_ITM_LAR_LOCK_ACCESS_S 0 +#define CPU_ITM_LAR_LOCK_ACCESS_W 32 +#define CPU_ITM_LAR_LOCK_ACCESS_M 0xFFFFFFFF +#define CPU_ITM_LAR_LOCK_ACCESS_S 0 //***************************************************************************** // @@ -1096,27 +1096,26 @@ // Field: [2] BYTEACC // // Reads 0 which means 8-bit lock access is not be implemented. -#define CPU_ITM_LSR_BYTEACC 0x00000004 -#define CPU_ITM_LSR_BYTEACC_BITN 2 -#define CPU_ITM_LSR_BYTEACC_M 0x00000004 -#define CPU_ITM_LSR_BYTEACC_S 2 +#define CPU_ITM_LSR_BYTEACC 0x00000004 +#define CPU_ITM_LSR_BYTEACC_BITN 2 +#define CPU_ITM_LSR_BYTEACC_M 0x00000004 +#define CPU_ITM_LSR_BYTEACC_S 2 // Field: [1] ACCESS // // Write access to component is blocked. All writes are ignored, reads are // permitted. -#define CPU_ITM_LSR_ACCESS 0x00000002 -#define CPU_ITM_LSR_ACCESS_BITN 1 -#define CPU_ITM_LSR_ACCESS_M 0x00000002 -#define CPU_ITM_LSR_ACCESS_S 1 +#define CPU_ITM_LSR_ACCESS 0x00000002 +#define CPU_ITM_LSR_ACCESS_BITN 1 +#define CPU_ITM_LSR_ACCESS_M 0x00000002 +#define CPU_ITM_LSR_ACCESS_S 1 // Field: [0] PRESENT // // Indicates that a lock mechanism exists for this component. -#define CPU_ITM_LSR_PRESENT 0x00000001 -#define CPU_ITM_LSR_PRESENT_BITN 0 -#define CPU_ITM_LSR_PRESENT_M 0x00000001 -#define CPU_ITM_LSR_PRESENT_S 0 - +#define CPU_ITM_LSR_PRESENT 0x00000001 +#define CPU_ITM_LSR_PRESENT_BITN 0 +#define CPU_ITM_LSR_PRESENT_M 0x00000001 +#define CPU_ITM_LSR_PRESENT_S 0 #endif // __CPU_ITM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_rom_table.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_rom_table.h index 69bf441..cd5012b 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_rom_table.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_rom_table.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_cpu_rom_table_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_cpu_rom_table_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CPU_ROM_TABLE_H__ #define __HW_CPU_ROM_TABLE_H__ @@ -44,28 +44,28 @@ // //***************************************************************************** // System Control Space Component -#define CPU_ROM_TABLE_O_SCS 0x00000000 +#define CPU_ROM_TABLE_O_SCS 0x00000000 // Data Watchpoint and Trace Component -#define CPU_ROM_TABLE_O_DWT 0x00000004 +#define CPU_ROM_TABLE_O_DWT 0x00000004 // Flash Patch and Breakpoint Component -#define CPU_ROM_TABLE_O_FPB 0x00000008 +#define CPU_ROM_TABLE_O_FPB 0x00000008 // Instrumentation Trace Component -#define CPU_ROM_TABLE_O_ITM 0x0000000C +#define CPU_ROM_TABLE_O_ITM 0x0000000C // Trace Port Interface Component -#define CPU_ROM_TABLE_O_TPIU 0x00000010 +#define CPU_ROM_TABLE_O_TPIU 0x00000010 // Enhanced Trace Component -#define CPU_ROM_TABLE_O_ETM 0x00000014 +#define CPU_ROM_TABLE_O_ETM 0x00000014 // End Marker -#define CPU_ROM_TABLE_O_END 0x00000018 +#define CPU_ROM_TABLE_O_END 0x00000018 // System Memory Map Access for DAP -#define CPU_ROM_TABLE_O_SYSTEM_ACCESS 0x00000FCC +#define CPU_ROM_TABLE_O_SYSTEM_ACCESS 0x00000FCC //***************************************************************************** // @@ -76,9 +76,9 @@ // // Points to the SCS at 0xE000E000. // (SCS + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE000E000. -#define CPU_ROM_TABLE_SCS_SCS_W 32 -#define CPU_ROM_TABLE_SCS_SCS_M 0xFFFFFFFF -#define CPU_ROM_TABLE_SCS_SCS_S 0 +#define CPU_ROM_TABLE_SCS_SCS_W 32 +#define CPU_ROM_TABLE_SCS_SCS_M 0xFFFFFFFF +#define CPU_ROM_TABLE_SCS_SCS_S 0 //***************************************************************************** // @@ -89,18 +89,18 @@ // // Points to the Data Watchpoint and Trace block at 0xE0001000. // (2*DWT + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0001000. -#define CPU_ROM_TABLE_DWT_DWT_W 31 -#define CPU_ROM_TABLE_DWT_DWT_M 0xFFFFFFFE -#define CPU_ROM_TABLE_DWT_DWT_S 1 +#define CPU_ROM_TABLE_DWT_DWT_W 31 +#define CPU_ROM_TABLE_DWT_DWT_M 0xFFFFFFFE +#define CPU_ROM_TABLE_DWT_DWT_S 1 // Field: [0] DWT_PRESENT // // 0: DWT is not present // 1: DWT is present. -#define CPU_ROM_TABLE_DWT_DWT_PRESENT 0x00000001 -#define CPU_ROM_TABLE_DWT_DWT_PRESENT_BITN 0 -#define CPU_ROM_TABLE_DWT_DWT_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_DWT_DWT_PRESENT_S 0 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT 0x00000001 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_BITN 0 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_S 0 //***************************************************************************** // @@ -111,18 +111,18 @@ // // Points to the Flash Patch and Breakpoint block at 0xE0002000. // (2*FPB + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0002000. -#define CPU_ROM_TABLE_FPB_FPB_W 31 -#define CPU_ROM_TABLE_FPB_FPB_M 0xFFFFFFFE -#define CPU_ROM_TABLE_FPB_FPB_S 1 +#define CPU_ROM_TABLE_FPB_FPB_W 31 +#define CPU_ROM_TABLE_FPB_FPB_M 0xFFFFFFFE +#define CPU_ROM_TABLE_FPB_FPB_S 1 // Field: [0] FPB_PRESENT // // 0: FPB is not present // 1: FPB is present. -#define CPU_ROM_TABLE_FPB_FPB_PRESENT 0x00000001 -#define CPU_ROM_TABLE_FPB_FPB_PRESENT_BITN 0 -#define CPU_ROM_TABLE_FPB_FPB_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_FPB_FPB_PRESENT_S 0 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT 0x00000001 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_BITN 0 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_S 0 //***************************************************************************** // @@ -133,18 +133,18 @@ // // Points to the Instrumentation Trace block at 0xE0000000. // (2*ITM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0000000. -#define CPU_ROM_TABLE_ITM_ITM_W 31 -#define CPU_ROM_TABLE_ITM_ITM_M 0xFFFFFFFE -#define CPU_ROM_TABLE_ITM_ITM_S 1 +#define CPU_ROM_TABLE_ITM_ITM_W 31 +#define CPU_ROM_TABLE_ITM_ITM_M 0xFFFFFFFE +#define CPU_ROM_TABLE_ITM_ITM_S 1 // Field: [0] ITM_PRESENT // // 0: ITM is not present // 1: ITM is present. -#define CPU_ROM_TABLE_ITM_ITM_PRESENT 0x00000001 -#define CPU_ROM_TABLE_ITM_ITM_PRESENT_BITN 0 -#define CPU_ROM_TABLE_ITM_ITM_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_ITM_ITM_PRESENT_S 0 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT 0x00000001 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_BITN 0 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_S 0 //***************************************************************************** // @@ -155,18 +155,18 @@ // // Points to the TPIU. TPIU is at 0xE0040000. // (2*TPIU + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0040000. -#define CPU_ROM_TABLE_TPIU_TPIU_W 31 -#define CPU_ROM_TABLE_TPIU_TPIU_M 0xFFFFFFFE -#define CPU_ROM_TABLE_TPIU_TPIU_S 1 +#define CPU_ROM_TABLE_TPIU_TPIU_W 31 +#define CPU_ROM_TABLE_TPIU_TPIU_M 0xFFFFFFFE +#define CPU_ROM_TABLE_TPIU_TPIU_S 1 // Field: [0] TPIU_PRESENT // // 0: TPIU is not present // 1: TPIU is present. -#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT 0x00000001 -#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_BITN 0 -#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_S 0 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT 0x00000001 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_BITN 0 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_S 0 //***************************************************************************** // @@ -177,18 +177,18 @@ // // Points to the ETM. ETM is at 0xE0041000. // (2*ETM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0041000. -#define CPU_ROM_TABLE_ETM_ETM_W 31 -#define CPU_ROM_TABLE_ETM_ETM_M 0xFFFFFFFE -#define CPU_ROM_TABLE_ETM_ETM_S 1 +#define CPU_ROM_TABLE_ETM_ETM_W 31 +#define CPU_ROM_TABLE_ETM_ETM_M 0xFFFFFFFE +#define CPU_ROM_TABLE_ETM_ETM_S 1 // Field: [0] ETM_PRESENT // // 0: ETM is not present // 1: ETM is present. -#define CPU_ROM_TABLE_ETM_ETM_PRESENT 0x00000001 -#define CPU_ROM_TABLE_ETM_ETM_PRESENT_BITN 0 -#define CPU_ROM_TABLE_ETM_ETM_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_ETM_ETM_PRESENT_S 0 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT 0x00000001 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_BITN 0 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_S 0 //***************************************************************************** // @@ -198,9 +198,9 @@ // Field: [31:0] END // // End of the ROM table -#define CPU_ROM_TABLE_END_END_W 32 -#define CPU_ROM_TABLE_END_END_M 0xFFFFFFFF -#define CPU_ROM_TABLE_END_END_S 0 +#define CPU_ROM_TABLE_END_END_W 32 +#define CPU_ROM_TABLE_END_END_M 0xFFFFFFFF +#define CPU_ROM_TABLE_END_END_S 0 //***************************************************************************** // @@ -211,10 +211,9 @@ // // 1: The system memory map is accessible using the DAP // 0: Only debug resources are accessible using the DAP -#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS 0x00000001 -#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_BITN 0 -#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_M 0x00000001 -#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_S 0 - +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS 0x00000001 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_BITN 0 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_M 0x00000001 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_S 0 #endif // __CPU_ROM_TABLE__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_scs.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_scs.h index 33ccf0c..8e3849d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_scs.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_scs.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_cpu_scs_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_cpu_scs_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CPU_SCS_H__ #define __HW_CPU_SCS_H__ @@ -44,235 +44,235 @@ // //***************************************************************************** // Interrupt Control Type -#define CPU_SCS_O_ICTR 0x00000004 +#define CPU_SCS_O_ICTR 0x00000004 // Auxiliary Control -#define CPU_SCS_O_ACTLR 0x00000008 +#define CPU_SCS_O_ACTLR 0x00000008 // SysTick Control and Status -#define CPU_SCS_O_STCSR 0x00000010 +#define CPU_SCS_O_STCSR 0x00000010 // SysTick Reload Value -#define CPU_SCS_O_STRVR 0x00000014 +#define CPU_SCS_O_STRVR 0x00000014 // SysTick Current Value -#define CPU_SCS_O_STCVR 0x00000018 +#define CPU_SCS_O_STCVR 0x00000018 // SysTick Calibration Value -#define CPU_SCS_O_STCR 0x0000001C +#define CPU_SCS_O_STCR 0x0000001C // Irq 0 to 31 Set Enable -#define CPU_SCS_O_NVIC_ISER0 0x00000100 +#define CPU_SCS_O_NVIC_ISER0 0x00000100 // Irq 32 to 63 Set Enable -#define CPU_SCS_O_NVIC_ISER1 0x00000104 +#define CPU_SCS_O_NVIC_ISER1 0x00000104 // Irq 0 to 31 Clear Enable -#define CPU_SCS_O_NVIC_ICER0 0x00000180 +#define CPU_SCS_O_NVIC_ICER0 0x00000180 // Irq 32 to 63 Clear Enable -#define CPU_SCS_O_NVIC_ICER1 0x00000184 +#define CPU_SCS_O_NVIC_ICER1 0x00000184 // Irq 0 to 31 Set Pending -#define CPU_SCS_O_NVIC_ISPR0 0x00000200 +#define CPU_SCS_O_NVIC_ISPR0 0x00000200 // Irq 32 to 63 Set Pending -#define CPU_SCS_O_NVIC_ISPR1 0x00000204 +#define CPU_SCS_O_NVIC_ISPR1 0x00000204 // Irq 0 to 31 Clear Pending -#define CPU_SCS_O_NVIC_ICPR0 0x00000280 +#define CPU_SCS_O_NVIC_ICPR0 0x00000280 // Irq 32 to 63 Clear Pending -#define CPU_SCS_O_NVIC_ICPR1 0x00000284 +#define CPU_SCS_O_NVIC_ICPR1 0x00000284 // Irq 0 to 31 Active Bit -#define CPU_SCS_O_NVIC_IABR0 0x00000300 +#define CPU_SCS_O_NVIC_IABR0 0x00000300 // Irq 32 to 63 Active Bit -#define CPU_SCS_O_NVIC_IABR1 0x00000304 +#define CPU_SCS_O_NVIC_IABR1 0x00000304 // Irq 0 to 3 Priority -#define CPU_SCS_O_NVIC_IPR0 0x00000400 +#define CPU_SCS_O_NVIC_IPR0 0x00000400 // Irq 4 to 7 Priority -#define CPU_SCS_O_NVIC_IPR1 0x00000404 +#define CPU_SCS_O_NVIC_IPR1 0x00000404 // Irq 8 to 11 Priority -#define CPU_SCS_O_NVIC_IPR2 0x00000408 +#define CPU_SCS_O_NVIC_IPR2 0x00000408 // Irq 12 to 15 Priority -#define CPU_SCS_O_NVIC_IPR3 0x0000040C +#define CPU_SCS_O_NVIC_IPR3 0x0000040C // Irq 16 to 19 Priority -#define CPU_SCS_O_NVIC_IPR4 0x00000410 +#define CPU_SCS_O_NVIC_IPR4 0x00000410 // Irq 20 to 23 Priority -#define CPU_SCS_O_NVIC_IPR5 0x00000414 +#define CPU_SCS_O_NVIC_IPR5 0x00000414 // Irq 24 to 27 Priority -#define CPU_SCS_O_NVIC_IPR6 0x00000418 +#define CPU_SCS_O_NVIC_IPR6 0x00000418 // Irq 28 to 31 Priority -#define CPU_SCS_O_NVIC_IPR7 0x0000041C +#define CPU_SCS_O_NVIC_IPR7 0x0000041C // Irq 32 to 35 Priority -#define CPU_SCS_O_NVIC_IPR8 0x00000420 +#define CPU_SCS_O_NVIC_IPR8 0x00000420 // Irq 32 to 35 Priority -#define CPU_SCS_O_NVIC_IPR9 0x00000424 +#define CPU_SCS_O_NVIC_IPR9 0x00000424 // CPUID Base -#define CPU_SCS_O_CPUID 0x00000D00 +#define CPU_SCS_O_CPUID 0x00000D00 // Interrupt Control State -#define CPU_SCS_O_ICSR 0x00000D04 +#define CPU_SCS_O_ICSR 0x00000D04 // Vector Table Offset -#define CPU_SCS_O_VTOR 0x00000D08 +#define CPU_SCS_O_VTOR 0x00000D08 // Application Interrupt/Reset Control -#define CPU_SCS_O_AIRCR 0x00000D0C +#define CPU_SCS_O_AIRCR 0x00000D0C // System Control -#define CPU_SCS_O_SCR 0x00000D10 +#define CPU_SCS_O_SCR 0x00000D10 // Configuration Control -#define CPU_SCS_O_CCR 0x00000D14 +#define CPU_SCS_O_CCR 0x00000D14 // System Handlers 4-7 Priority -#define CPU_SCS_O_SHPR1 0x00000D18 +#define CPU_SCS_O_SHPR1 0x00000D18 // System Handlers 8-11 Priority -#define CPU_SCS_O_SHPR2 0x00000D1C +#define CPU_SCS_O_SHPR2 0x00000D1C // System Handlers 12-15 Priority -#define CPU_SCS_O_SHPR3 0x00000D20 +#define CPU_SCS_O_SHPR3 0x00000D20 // System Handler Control and State -#define CPU_SCS_O_SHCSR 0x00000D24 +#define CPU_SCS_O_SHCSR 0x00000D24 // Configurable Fault Status -#define CPU_SCS_O_CFSR 0x00000D28 +#define CPU_SCS_O_CFSR 0x00000D28 // Hard Fault Status -#define CPU_SCS_O_HFSR 0x00000D2C +#define CPU_SCS_O_HFSR 0x00000D2C // Debug Fault Status -#define CPU_SCS_O_DFSR 0x00000D30 +#define CPU_SCS_O_DFSR 0x00000D30 // Mem Manage Fault Address -#define CPU_SCS_O_MMFAR 0x00000D34 +#define CPU_SCS_O_MMFAR 0x00000D34 // Bus Fault Address -#define CPU_SCS_O_BFAR 0x00000D38 +#define CPU_SCS_O_BFAR 0x00000D38 // Auxiliary Fault Status -#define CPU_SCS_O_AFSR 0x00000D3C +#define CPU_SCS_O_AFSR 0x00000D3C // Processor Feature 0 -#define CPU_SCS_O_ID_PFR0 0x00000D40 +#define CPU_SCS_O_ID_PFR0 0x00000D40 // Processor Feature 1 -#define CPU_SCS_O_ID_PFR1 0x00000D44 +#define CPU_SCS_O_ID_PFR1 0x00000D44 // Debug Feature 0 -#define CPU_SCS_O_ID_DFR0 0x00000D48 +#define CPU_SCS_O_ID_DFR0 0x00000D48 // Auxiliary Feature 0 -#define CPU_SCS_O_ID_AFR0 0x00000D4C +#define CPU_SCS_O_ID_AFR0 0x00000D4C // Memory Model Feature 0 -#define CPU_SCS_O_ID_MMFR0 0x00000D50 +#define CPU_SCS_O_ID_MMFR0 0x00000D50 // Memory Model Feature 1 -#define CPU_SCS_O_ID_MMFR1 0x00000D54 +#define CPU_SCS_O_ID_MMFR1 0x00000D54 // Memory Model Feature 2 -#define CPU_SCS_O_ID_MMFR2 0x00000D58 +#define CPU_SCS_O_ID_MMFR2 0x00000D58 // Memory Model Feature 3 -#define CPU_SCS_O_ID_MMFR3 0x00000D5C +#define CPU_SCS_O_ID_MMFR3 0x00000D5C // ISA Feature 0 -#define CPU_SCS_O_ID_ISAR0 0x00000D60 +#define CPU_SCS_O_ID_ISAR0 0x00000D60 // ISA Feature 1 -#define CPU_SCS_O_ID_ISAR1 0x00000D64 +#define CPU_SCS_O_ID_ISAR1 0x00000D64 // ISA Feature 2 -#define CPU_SCS_O_ID_ISAR2 0x00000D68 +#define CPU_SCS_O_ID_ISAR2 0x00000D68 // ISA Feature 3 -#define CPU_SCS_O_ID_ISAR3 0x00000D6C +#define CPU_SCS_O_ID_ISAR3 0x00000D6C // ISA Feature 4 -#define CPU_SCS_O_ID_ISAR4 0x00000D70 +#define CPU_SCS_O_ID_ISAR4 0x00000D70 // Coprocessor Access Control -#define CPU_SCS_O_CPACR 0x00000D88 +#define CPU_SCS_O_CPACR 0x00000D88 // MPU Type -#define CPU_SCS_O_MPU_TYPE 0x00000D90 +#define CPU_SCS_O_MPU_TYPE 0x00000D90 // MPU Control -#define CPU_SCS_O_MPU_CTRL 0x00000D94 +#define CPU_SCS_O_MPU_CTRL 0x00000D94 // MPU Region Number -#define CPU_SCS_O_MPU_RNR 0x00000D98 +#define CPU_SCS_O_MPU_RNR 0x00000D98 // MPU Region Base Address -#define CPU_SCS_O_MPU_RBAR 0x00000D9C +#define CPU_SCS_O_MPU_RBAR 0x00000D9C // MPU Region Attribute and Size -#define CPU_SCS_O_MPU_RASR 0x00000DA0 +#define CPU_SCS_O_MPU_RASR 0x00000DA0 // MPU Alias 1 Region Base Address -#define CPU_SCS_O_MPU_RBAR_A1 0x00000DA4 +#define CPU_SCS_O_MPU_RBAR_A1 0x00000DA4 // MPU Alias 1 Region Attribute and Size -#define CPU_SCS_O_MPU_RASR_A1 0x00000DA8 +#define CPU_SCS_O_MPU_RASR_A1 0x00000DA8 // MPU Alias 2 Region Base Address -#define CPU_SCS_O_MPU_RBAR_A2 0x00000DAC +#define CPU_SCS_O_MPU_RBAR_A2 0x00000DAC // MPU Alias 2 Region Attribute and Size -#define CPU_SCS_O_MPU_RASR_A2 0x00000DB0 +#define CPU_SCS_O_MPU_RASR_A2 0x00000DB0 // MPU Alias 3 Region Base Address -#define CPU_SCS_O_MPU_RBAR_A3 0x00000DB4 +#define CPU_SCS_O_MPU_RBAR_A3 0x00000DB4 // MPU Alias 3 Region Attribute and Size -#define CPU_SCS_O_MPU_RASR_A3 0x00000DB8 +#define CPU_SCS_O_MPU_RASR_A3 0x00000DB8 // Debug Halting Control and Status -#define CPU_SCS_O_DHCSR 0x00000DF0 +#define CPU_SCS_O_DHCSR 0x00000DF0 // Deubg Core Register Selector -#define CPU_SCS_O_DCRSR 0x00000DF4 +#define CPU_SCS_O_DCRSR 0x00000DF4 // Debug Core Register Data -#define CPU_SCS_O_DCRDR 0x00000DF8 +#define CPU_SCS_O_DCRDR 0x00000DF8 // Debug Exception and Monitor Control -#define CPU_SCS_O_DEMCR 0x00000DFC +#define CPU_SCS_O_DEMCR 0x00000DFC // Software Trigger Interrupt -#define CPU_SCS_O_STIR 0x00000F00 +#define CPU_SCS_O_STIR 0x00000F00 // Floating Point Context Control -#define CPU_SCS_O_FPCCR 0x00000F34 +#define CPU_SCS_O_FPCCR 0x00000F34 // Floating-Point Context Address -#define CPU_SCS_O_FPCAR 0x00000F38 +#define CPU_SCS_O_FPCAR 0x00000F38 // Floating Point Default Status Control -#define CPU_SCS_O_FPDSCR 0x00000F3C +#define CPU_SCS_O_FPDSCR 0x00000F3C // Media and FP Feature 0 -#define CPU_SCS_O_MVFR0 0x00000F40 +#define CPU_SCS_O_MVFR0 0x00000F40 // Media and FP Feature 1 -#define CPU_SCS_O_MVFR1 0x00000F44 +#define CPU_SCS_O_MVFR1 0x00000F44 //***************************************************************************** // @@ -291,9 +291,9 @@ // 5: 161...192 // 6: 193...224 // 7: 225...256 -#define CPU_SCS_ICTR_INTLINESNUM_W 3 -#define CPU_SCS_ICTR_INTLINESNUM_M 0x00000007 -#define CPU_SCS_ICTR_INTLINESNUM_S 0 +#define CPU_SCS_ICTR_INTLINESNUM_W 3 +#define CPU_SCS_ICTR_INTLINESNUM_M 0x00000007 +#define CPU_SCS_ICTR_INTLINESNUM_S 0 //***************************************************************************** // @@ -304,26 +304,26 @@ // // Disables floating point instructions completing out of order with respect to // integer instructions. -#define CPU_SCS_ACTLR_DISOOFP 0x00000200 -#define CPU_SCS_ACTLR_DISOOFP_BITN 9 -#define CPU_SCS_ACTLR_DISOOFP_M 0x00000200 -#define CPU_SCS_ACTLR_DISOOFP_S 9 +#define CPU_SCS_ACTLR_DISOOFP 0x00000200 +#define CPU_SCS_ACTLR_DISOOFP_BITN 9 +#define CPU_SCS_ACTLR_DISOOFP_M 0x00000200 +#define CPU_SCS_ACTLR_DISOOFP_S 9 // Field: [8] DISFPCA // // Disable automatic update of CONTROL.FPCA -#define CPU_SCS_ACTLR_DISFPCA 0x00000100 -#define CPU_SCS_ACTLR_DISFPCA_BITN 8 -#define CPU_SCS_ACTLR_DISFPCA_M 0x00000100 -#define CPU_SCS_ACTLR_DISFPCA_S 8 +#define CPU_SCS_ACTLR_DISFPCA 0x00000100 +#define CPU_SCS_ACTLR_DISFPCA_BITN 8 +#define CPU_SCS_ACTLR_DISFPCA_M 0x00000100 +#define CPU_SCS_ACTLR_DISFPCA_S 8 // Field: [2] DISFOLD // // Disables folding of IT instruction. -#define CPU_SCS_ACTLR_DISFOLD 0x00000004 -#define CPU_SCS_ACTLR_DISFOLD_BITN 2 -#define CPU_SCS_ACTLR_DISFOLD_M 0x00000004 -#define CPU_SCS_ACTLR_DISFOLD_S 2 +#define CPU_SCS_ACTLR_DISFOLD 0x00000004 +#define CPU_SCS_ACTLR_DISFOLD_BITN 2 +#define CPU_SCS_ACTLR_DISFOLD_M 0x00000004 +#define CPU_SCS_ACTLR_DISFOLD_S 2 // Field: [1] DISDEFWBUF // @@ -331,20 +331,20 @@ // all bus faults to be precise bus faults but decreases the performance of the // processor because the stores to memory have to complete before the next // instruction can be executed. -#define CPU_SCS_ACTLR_DISDEFWBUF 0x00000002 -#define CPU_SCS_ACTLR_DISDEFWBUF_BITN 1 -#define CPU_SCS_ACTLR_DISDEFWBUF_M 0x00000002 -#define CPU_SCS_ACTLR_DISDEFWBUF_S 1 +#define CPU_SCS_ACTLR_DISDEFWBUF 0x00000002 +#define CPU_SCS_ACTLR_DISDEFWBUF_BITN 1 +#define CPU_SCS_ACTLR_DISDEFWBUF_M 0x00000002 +#define CPU_SCS_ACTLR_DISDEFWBUF_S 1 // Field: [0] DISMCYCINT // // Disables interruption of multi-cycle instructions. This increases the // interrupt latency of the processor becuase LDM/STM completes before // interrupt stacking occurs. -#define CPU_SCS_ACTLR_DISMCYCINT 0x00000001 -#define CPU_SCS_ACTLR_DISMCYCINT_BITN 0 -#define CPU_SCS_ACTLR_DISMCYCINT_M 0x00000001 -#define CPU_SCS_ACTLR_DISMCYCINT_S 0 +#define CPU_SCS_ACTLR_DISMCYCINT 0x00000001 +#define CPU_SCS_ACTLR_DISMCYCINT_BITN 0 +#define CPU_SCS_ACTLR_DISMCYCINT_M 0x00000001 +#define CPU_SCS_ACTLR_DISMCYCINT_S 0 //***************************************************************************** // @@ -358,10 +358,10 @@ // If read by the debugger using the DAP, this bit is cleared on read-only if // the MasterType bit in the **AHB-AP** Control Register is set to 0. // Otherwise, COUNTFLAG is not changed by the debugger read. -#define CPU_SCS_STCSR_COUNTFLAG 0x00010000 -#define CPU_SCS_STCSR_COUNTFLAG_BITN 16 -#define CPU_SCS_STCSR_COUNTFLAG_M 0x00010000 -#define CPU_SCS_STCSR_COUNTFLAG_S 16 +#define CPU_SCS_STCSR_COUNTFLAG 0x00010000 +#define CPU_SCS_STCSR_COUNTFLAG_BITN 16 +#define CPU_SCS_STCSR_COUNTFLAG_M 0x00010000 +#define CPU_SCS_STCSR_COUNTFLAG_S 16 // Field: [2] CLKSOURCE // @@ -372,20 +372,20 @@ // // External clock is not available in this device. Writes to this field will be // ignored. -#define CPU_SCS_STCSR_CLKSOURCE 0x00000004 -#define CPU_SCS_STCSR_CLKSOURCE_BITN 2 -#define CPU_SCS_STCSR_CLKSOURCE_M 0x00000004 -#define CPU_SCS_STCSR_CLKSOURCE_S 2 +#define CPU_SCS_STCSR_CLKSOURCE 0x00000004 +#define CPU_SCS_STCSR_CLKSOURCE_BITN 2 +#define CPU_SCS_STCSR_CLKSOURCE_M 0x00000004 +#define CPU_SCS_STCSR_CLKSOURCE_S 2 // Field: [1] TICKINT // // 0: Counting down to zero does not pend the SysTick handler. Software can use // COUNTFLAG to determine if the SysTick handler has ever counted to zero. // 1: Counting down to zero pends the SysTick handler. -#define CPU_SCS_STCSR_TICKINT 0x00000002 -#define CPU_SCS_STCSR_TICKINT_BITN 1 -#define CPU_SCS_STCSR_TICKINT_M 0x00000002 -#define CPU_SCS_STCSR_TICKINT_S 1 +#define CPU_SCS_STCSR_TICKINT 0x00000002 +#define CPU_SCS_STCSR_TICKINT_BITN 1 +#define CPU_SCS_STCSR_TICKINT_M 0x00000002 +#define CPU_SCS_STCSR_TICKINT_S 1 // Field: [0] ENABLE // @@ -396,10 +396,10 @@ // Reload value STRVR.RELOAD and then begins counting down. On reaching 0, it // sets COUNTFLAG to 1 and optionally pends the SysTick handler, based on // TICKINT. It then loads STRVR.RELOAD again, and begins counting. -#define CPU_SCS_STCSR_ENABLE 0x00000001 -#define CPU_SCS_STCSR_ENABLE_BITN 0 -#define CPU_SCS_STCSR_ENABLE_M 0x00000001 -#define CPU_SCS_STCSR_ENABLE_S 0 +#define CPU_SCS_STCSR_ENABLE 0x00000001 +#define CPU_SCS_STCSR_ENABLE_BITN 0 +#define CPU_SCS_STCSR_ENABLE_M 0x00000001 +#define CPU_SCS_STCSR_ENABLE_S 0 //***************************************************************************** // @@ -410,9 +410,9 @@ // // Value to load into the SysTick Current Value Register STCVR.CURRENT when the // counter reaches 0. -#define CPU_SCS_STRVR_RELOAD_W 24 -#define CPU_SCS_STRVR_RELOAD_M 0x00FFFFFF -#define CPU_SCS_STRVR_RELOAD_S 0 +#define CPU_SCS_STRVR_RELOAD_W 24 +#define CPU_SCS_STRVR_RELOAD_M 0x00FFFFFF +#define CPU_SCS_STRVR_RELOAD_S 0 //***************************************************************************** // @@ -425,9 +425,9 @@ // protection is provided, so change with care. Writing to it with any value // clears the register to 0. Clearing this register also clears // STCSR.COUNTFLAG. -#define CPU_SCS_STCVR_CURRENT_W 24 -#define CPU_SCS_STCVR_CURRENT_M 0x00FFFFFF -#define CPU_SCS_STCVR_CURRENT_S 0 +#define CPU_SCS_STCVR_CURRENT_W 24 +#define CPU_SCS_STCVR_CURRENT_M 0x00FFFFFF +#define CPU_SCS_STCVR_CURRENT_S 0 //***************************************************************************** // @@ -437,28 +437,28 @@ // Field: [31] NOREF // // Reads as one. Indicates that no separate reference clock is provided. -#define CPU_SCS_STCR_NOREF 0x80000000 -#define CPU_SCS_STCR_NOREF_BITN 31 -#define CPU_SCS_STCR_NOREF_M 0x80000000 -#define CPU_SCS_STCR_NOREF_S 31 +#define CPU_SCS_STCR_NOREF 0x80000000 +#define CPU_SCS_STCR_NOREF_BITN 31 +#define CPU_SCS_STCR_NOREF_M 0x80000000 +#define CPU_SCS_STCR_NOREF_S 31 // Field: [30] SKEW // // Reads as one. The calibration value is not exactly 10ms because of clock // frequency. This could affect its suitability as a software real time clock. -#define CPU_SCS_STCR_SKEW 0x40000000 -#define CPU_SCS_STCR_SKEW_BITN 30 -#define CPU_SCS_STCR_SKEW_M 0x40000000 -#define CPU_SCS_STCR_SKEW_S 30 +#define CPU_SCS_STCR_SKEW 0x40000000 +#define CPU_SCS_STCR_SKEW_BITN 30 +#define CPU_SCS_STCR_SKEW_M 0x40000000 +#define CPU_SCS_STCR_SKEW_S 30 // Field: [23:0] TENMS // // An optional Reload value to be used for 10ms (100Hz) timing, subject to // system clock skew errors. The value read is valid only when core clock is at // 48MHz. -#define CPU_SCS_STCR_TENMS_W 24 -#define CPU_SCS_STCR_TENMS_M 0x00FFFFFF -#define CPU_SCS_STCR_TENMS_S 0 +#define CPU_SCS_STCR_TENMS_W 24 +#define CPU_SCS_STCR_TENMS_M 0x00FFFFFF +#define CPU_SCS_STCR_TENMS_S 0 //***************************************************************************** // @@ -470,320 +470,320 @@ // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA31 0x80000000 -#define CPU_SCS_NVIC_ISER0_SETENA31_BITN 31 -#define CPU_SCS_NVIC_ISER0_SETENA31_M 0x80000000 -#define CPU_SCS_NVIC_ISER0_SETENA31_S 31 +#define CPU_SCS_NVIC_ISER0_SETENA31 0x80000000 +#define CPU_SCS_NVIC_ISER0_SETENA31_BITN 31 +#define CPU_SCS_NVIC_ISER0_SETENA31_M 0x80000000 +#define CPU_SCS_NVIC_ISER0_SETENA31_S 31 // Field: [30] SETENA30 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA30 0x40000000 -#define CPU_SCS_NVIC_ISER0_SETENA30_BITN 30 -#define CPU_SCS_NVIC_ISER0_SETENA30_M 0x40000000 -#define CPU_SCS_NVIC_ISER0_SETENA30_S 30 +#define CPU_SCS_NVIC_ISER0_SETENA30 0x40000000 +#define CPU_SCS_NVIC_ISER0_SETENA30_BITN 30 +#define CPU_SCS_NVIC_ISER0_SETENA30_M 0x40000000 +#define CPU_SCS_NVIC_ISER0_SETENA30_S 30 // Field: [29] SETENA29 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA29 0x20000000 -#define CPU_SCS_NVIC_ISER0_SETENA29_BITN 29 -#define CPU_SCS_NVIC_ISER0_SETENA29_M 0x20000000 -#define CPU_SCS_NVIC_ISER0_SETENA29_S 29 +#define CPU_SCS_NVIC_ISER0_SETENA29 0x20000000 +#define CPU_SCS_NVIC_ISER0_SETENA29_BITN 29 +#define CPU_SCS_NVIC_ISER0_SETENA29_M 0x20000000 +#define CPU_SCS_NVIC_ISER0_SETENA29_S 29 // Field: [28] SETENA28 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA28 0x10000000 -#define CPU_SCS_NVIC_ISER0_SETENA28_BITN 28 -#define CPU_SCS_NVIC_ISER0_SETENA28_M 0x10000000 -#define CPU_SCS_NVIC_ISER0_SETENA28_S 28 +#define CPU_SCS_NVIC_ISER0_SETENA28 0x10000000 +#define CPU_SCS_NVIC_ISER0_SETENA28_BITN 28 +#define CPU_SCS_NVIC_ISER0_SETENA28_M 0x10000000 +#define CPU_SCS_NVIC_ISER0_SETENA28_S 28 // Field: [27] SETENA27 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA27 0x08000000 -#define CPU_SCS_NVIC_ISER0_SETENA27_BITN 27 -#define CPU_SCS_NVIC_ISER0_SETENA27_M 0x08000000 -#define CPU_SCS_NVIC_ISER0_SETENA27_S 27 +#define CPU_SCS_NVIC_ISER0_SETENA27 0x08000000 +#define CPU_SCS_NVIC_ISER0_SETENA27_BITN 27 +#define CPU_SCS_NVIC_ISER0_SETENA27_M 0x08000000 +#define CPU_SCS_NVIC_ISER0_SETENA27_S 27 // Field: [26] SETENA26 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA26 0x04000000 -#define CPU_SCS_NVIC_ISER0_SETENA26_BITN 26 -#define CPU_SCS_NVIC_ISER0_SETENA26_M 0x04000000 -#define CPU_SCS_NVIC_ISER0_SETENA26_S 26 +#define CPU_SCS_NVIC_ISER0_SETENA26 0x04000000 +#define CPU_SCS_NVIC_ISER0_SETENA26_BITN 26 +#define CPU_SCS_NVIC_ISER0_SETENA26_M 0x04000000 +#define CPU_SCS_NVIC_ISER0_SETENA26_S 26 // Field: [25] SETENA25 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA25 0x02000000 -#define CPU_SCS_NVIC_ISER0_SETENA25_BITN 25 -#define CPU_SCS_NVIC_ISER0_SETENA25_M 0x02000000 -#define CPU_SCS_NVIC_ISER0_SETENA25_S 25 +#define CPU_SCS_NVIC_ISER0_SETENA25 0x02000000 +#define CPU_SCS_NVIC_ISER0_SETENA25_BITN 25 +#define CPU_SCS_NVIC_ISER0_SETENA25_M 0x02000000 +#define CPU_SCS_NVIC_ISER0_SETENA25_S 25 // Field: [24] SETENA24 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA24 0x01000000 -#define CPU_SCS_NVIC_ISER0_SETENA24_BITN 24 -#define CPU_SCS_NVIC_ISER0_SETENA24_M 0x01000000 -#define CPU_SCS_NVIC_ISER0_SETENA24_S 24 +#define CPU_SCS_NVIC_ISER0_SETENA24 0x01000000 +#define CPU_SCS_NVIC_ISER0_SETENA24_BITN 24 +#define CPU_SCS_NVIC_ISER0_SETENA24_M 0x01000000 +#define CPU_SCS_NVIC_ISER0_SETENA24_S 24 // Field: [23] SETENA23 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA23 0x00800000 -#define CPU_SCS_NVIC_ISER0_SETENA23_BITN 23 -#define CPU_SCS_NVIC_ISER0_SETENA23_M 0x00800000 -#define CPU_SCS_NVIC_ISER0_SETENA23_S 23 +#define CPU_SCS_NVIC_ISER0_SETENA23 0x00800000 +#define CPU_SCS_NVIC_ISER0_SETENA23_BITN 23 +#define CPU_SCS_NVIC_ISER0_SETENA23_M 0x00800000 +#define CPU_SCS_NVIC_ISER0_SETENA23_S 23 // Field: [22] SETENA22 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA22 0x00400000 -#define CPU_SCS_NVIC_ISER0_SETENA22_BITN 22 -#define CPU_SCS_NVIC_ISER0_SETENA22_M 0x00400000 -#define CPU_SCS_NVIC_ISER0_SETENA22_S 22 +#define CPU_SCS_NVIC_ISER0_SETENA22 0x00400000 +#define CPU_SCS_NVIC_ISER0_SETENA22_BITN 22 +#define CPU_SCS_NVIC_ISER0_SETENA22_M 0x00400000 +#define CPU_SCS_NVIC_ISER0_SETENA22_S 22 // Field: [21] SETENA21 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA21 0x00200000 -#define CPU_SCS_NVIC_ISER0_SETENA21_BITN 21 -#define CPU_SCS_NVIC_ISER0_SETENA21_M 0x00200000 -#define CPU_SCS_NVIC_ISER0_SETENA21_S 21 +#define CPU_SCS_NVIC_ISER0_SETENA21 0x00200000 +#define CPU_SCS_NVIC_ISER0_SETENA21_BITN 21 +#define CPU_SCS_NVIC_ISER0_SETENA21_M 0x00200000 +#define CPU_SCS_NVIC_ISER0_SETENA21_S 21 // Field: [20] SETENA20 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA20 0x00100000 -#define CPU_SCS_NVIC_ISER0_SETENA20_BITN 20 -#define CPU_SCS_NVIC_ISER0_SETENA20_M 0x00100000 -#define CPU_SCS_NVIC_ISER0_SETENA20_S 20 +#define CPU_SCS_NVIC_ISER0_SETENA20 0x00100000 +#define CPU_SCS_NVIC_ISER0_SETENA20_BITN 20 +#define CPU_SCS_NVIC_ISER0_SETENA20_M 0x00100000 +#define CPU_SCS_NVIC_ISER0_SETENA20_S 20 // Field: [19] SETENA19 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA19 0x00080000 -#define CPU_SCS_NVIC_ISER0_SETENA19_BITN 19 -#define CPU_SCS_NVIC_ISER0_SETENA19_M 0x00080000 -#define CPU_SCS_NVIC_ISER0_SETENA19_S 19 +#define CPU_SCS_NVIC_ISER0_SETENA19 0x00080000 +#define CPU_SCS_NVIC_ISER0_SETENA19_BITN 19 +#define CPU_SCS_NVIC_ISER0_SETENA19_M 0x00080000 +#define CPU_SCS_NVIC_ISER0_SETENA19_S 19 // Field: [18] SETENA18 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA18 0x00040000 -#define CPU_SCS_NVIC_ISER0_SETENA18_BITN 18 -#define CPU_SCS_NVIC_ISER0_SETENA18_M 0x00040000 -#define CPU_SCS_NVIC_ISER0_SETENA18_S 18 +#define CPU_SCS_NVIC_ISER0_SETENA18 0x00040000 +#define CPU_SCS_NVIC_ISER0_SETENA18_BITN 18 +#define CPU_SCS_NVIC_ISER0_SETENA18_M 0x00040000 +#define CPU_SCS_NVIC_ISER0_SETENA18_S 18 // Field: [17] SETENA17 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA17 0x00020000 -#define CPU_SCS_NVIC_ISER0_SETENA17_BITN 17 -#define CPU_SCS_NVIC_ISER0_SETENA17_M 0x00020000 -#define CPU_SCS_NVIC_ISER0_SETENA17_S 17 +#define CPU_SCS_NVIC_ISER0_SETENA17 0x00020000 +#define CPU_SCS_NVIC_ISER0_SETENA17_BITN 17 +#define CPU_SCS_NVIC_ISER0_SETENA17_M 0x00020000 +#define CPU_SCS_NVIC_ISER0_SETENA17_S 17 // Field: [16] SETENA16 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA16 0x00010000 -#define CPU_SCS_NVIC_ISER0_SETENA16_BITN 16 -#define CPU_SCS_NVIC_ISER0_SETENA16_M 0x00010000 -#define CPU_SCS_NVIC_ISER0_SETENA16_S 16 +#define CPU_SCS_NVIC_ISER0_SETENA16 0x00010000 +#define CPU_SCS_NVIC_ISER0_SETENA16_BITN 16 +#define CPU_SCS_NVIC_ISER0_SETENA16_M 0x00010000 +#define CPU_SCS_NVIC_ISER0_SETENA16_S 16 // Field: [15] SETENA15 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA15 0x00008000 -#define CPU_SCS_NVIC_ISER0_SETENA15_BITN 15 -#define CPU_SCS_NVIC_ISER0_SETENA15_M 0x00008000 -#define CPU_SCS_NVIC_ISER0_SETENA15_S 15 +#define CPU_SCS_NVIC_ISER0_SETENA15 0x00008000 +#define CPU_SCS_NVIC_ISER0_SETENA15_BITN 15 +#define CPU_SCS_NVIC_ISER0_SETENA15_M 0x00008000 +#define CPU_SCS_NVIC_ISER0_SETENA15_S 15 // Field: [14] SETENA14 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA14 0x00004000 -#define CPU_SCS_NVIC_ISER0_SETENA14_BITN 14 -#define CPU_SCS_NVIC_ISER0_SETENA14_M 0x00004000 -#define CPU_SCS_NVIC_ISER0_SETENA14_S 14 +#define CPU_SCS_NVIC_ISER0_SETENA14 0x00004000 +#define CPU_SCS_NVIC_ISER0_SETENA14_BITN 14 +#define CPU_SCS_NVIC_ISER0_SETENA14_M 0x00004000 +#define CPU_SCS_NVIC_ISER0_SETENA14_S 14 // Field: [13] SETENA13 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA13 0x00002000 -#define CPU_SCS_NVIC_ISER0_SETENA13_BITN 13 -#define CPU_SCS_NVIC_ISER0_SETENA13_M 0x00002000 -#define CPU_SCS_NVIC_ISER0_SETENA13_S 13 +#define CPU_SCS_NVIC_ISER0_SETENA13 0x00002000 +#define CPU_SCS_NVIC_ISER0_SETENA13_BITN 13 +#define CPU_SCS_NVIC_ISER0_SETENA13_M 0x00002000 +#define CPU_SCS_NVIC_ISER0_SETENA13_S 13 // Field: [12] SETENA12 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA12 0x00001000 -#define CPU_SCS_NVIC_ISER0_SETENA12_BITN 12 -#define CPU_SCS_NVIC_ISER0_SETENA12_M 0x00001000 -#define CPU_SCS_NVIC_ISER0_SETENA12_S 12 +#define CPU_SCS_NVIC_ISER0_SETENA12 0x00001000 +#define CPU_SCS_NVIC_ISER0_SETENA12_BITN 12 +#define CPU_SCS_NVIC_ISER0_SETENA12_M 0x00001000 +#define CPU_SCS_NVIC_ISER0_SETENA12_S 12 // Field: [11] SETENA11 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA11 0x00000800 -#define CPU_SCS_NVIC_ISER0_SETENA11_BITN 11 -#define CPU_SCS_NVIC_ISER0_SETENA11_M 0x00000800 -#define CPU_SCS_NVIC_ISER0_SETENA11_S 11 +#define CPU_SCS_NVIC_ISER0_SETENA11 0x00000800 +#define CPU_SCS_NVIC_ISER0_SETENA11_BITN 11 +#define CPU_SCS_NVIC_ISER0_SETENA11_M 0x00000800 +#define CPU_SCS_NVIC_ISER0_SETENA11_S 11 // Field: [10] SETENA10 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA10 0x00000400 -#define CPU_SCS_NVIC_ISER0_SETENA10_BITN 10 -#define CPU_SCS_NVIC_ISER0_SETENA10_M 0x00000400 -#define CPU_SCS_NVIC_ISER0_SETENA10_S 10 +#define CPU_SCS_NVIC_ISER0_SETENA10 0x00000400 +#define CPU_SCS_NVIC_ISER0_SETENA10_BITN 10 +#define CPU_SCS_NVIC_ISER0_SETENA10_M 0x00000400 +#define CPU_SCS_NVIC_ISER0_SETENA10_S 10 // Field: [9] SETENA9 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA9 0x00000200 -#define CPU_SCS_NVIC_ISER0_SETENA9_BITN 9 -#define CPU_SCS_NVIC_ISER0_SETENA9_M 0x00000200 -#define CPU_SCS_NVIC_ISER0_SETENA9_S 9 +#define CPU_SCS_NVIC_ISER0_SETENA9 0x00000200 +#define CPU_SCS_NVIC_ISER0_SETENA9_BITN 9 +#define CPU_SCS_NVIC_ISER0_SETENA9_M 0x00000200 +#define CPU_SCS_NVIC_ISER0_SETENA9_S 9 // Field: [8] SETENA8 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA8 0x00000100 -#define CPU_SCS_NVIC_ISER0_SETENA8_BITN 8 -#define CPU_SCS_NVIC_ISER0_SETENA8_M 0x00000100 -#define CPU_SCS_NVIC_ISER0_SETENA8_S 8 +#define CPU_SCS_NVIC_ISER0_SETENA8 0x00000100 +#define CPU_SCS_NVIC_ISER0_SETENA8_BITN 8 +#define CPU_SCS_NVIC_ISER0_SETENA8_M 0x00000100 +#define CPU_SCS_NVIC_ISER0_SETENA8_S 8 // Field: [7] SETENA7 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA7 0x00000080 -#define CPU_SCS_NVIC_ISER0_SETENA7_BITN 7 -#define CPU_SCS_NVIC_ISER0_SETENA7_M 0x00000080 -#define CPU_SCS_NVIC_ISER0_SETENA7_S 7 +#define CPU_SCS_NVIC_ISER0_SETENA7 0x00000080 +#define CPU_SCS_NVIC_ISER0_SETENA7_BITN 7 +#define CPU_SCS_NVIC_ISER0_SETENA7_M 0x00000080 +#define CPU_SCS_NVIC_ISER0_SETENA7_S 7 // Field: [6] SETENA6 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA6 0x00000040 -#define CPU_SCS_NVIC_ISER0_SETENA6_BITN 6 -#define CPU_SCS_NVIC_ISER0_SETENA6_M 0x00000040 -#define CPU_SCS_NVIC_ISER0_SETENA6_S 6 +#define CPU_SCS_NVIC_ISER0_SETENA6 0x00000040 +#define CPU_SCS_NVIC_ISER0_SETENA6_BITN 6 +#define CPU_SCS_NVIC_ISER0_SETENA6_M 0x00000040 +#define CPU_SCS_NVIC_ISER0_SETENA6_S 6 // Field: [5] SETENA5 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA5 0x00000020 -#define CPU_SCS_NVIC_ISER0_SETENA5_BITN 5 -#define CPU_SCS_NVIC_ISER0_SETENA5_M 0x00000020 -#define CPU_SCS_NVIC_ISER0_SETENA5_S 5 +#define CPU_SCS_NVIC_ISER0_SETENA5 0x00000020 +#define CPU_SCS_NVIC_ISER0_SETENA5_BITN 5 +#define CPU_SCS_NVIC_ISER0_SETENA5_M 0x00000020 +#define CPU_SCS_NVIC_ISER0_SETENA5_S 5 // Field: [4] SETENA4 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA4 0x00000010 -#define CPU_SCS_NVIC_ISER0_SETENA4_BITN 4 -#define CPU_SCS_NVIC_ISER0_SETENA4_M 0x00000010 -#define CPU_SCS_NVIC_ISER0_SETENA4_S 4 +#define CPU_SCS_NVIC_ISER0_SETENA4 0x00000010 +#define CPU_SCS_NVIC_ISER0_SETENA4_BITN 4 +#define CPU_SCS_NVIC_ISER0_SETENA4_M 0x00000010 +#define CPU_SCS_NVIC_ISER0_SETENA4_S 4 // Field: [3] SETENA3 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA3 0x00000008 -#define CPU_SCS_NVIC_ISER0_SETENA3_BITN 3 -#define CPU_SCS_NVIC_ISER0_SETENA3_M 0x00000008 -#define CPU_SCS_NVIC_ISER0_SETENA3_S 3 +#define CPU_SCS_NVIC_ISER0_SETENA3 0x00000008 +#define CPU_SCS_NVIC_ISER0_SETENA3_BITN 3 +#define CPU_SCS_NVIC_ISER0_SETENA3_M 0x00000008 +#define CPU_SCS_NVIC_ISER0_SETENA3_S 3 // Field: [2] SETENA2 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA2 0x00000004 -#define CPU_SCS_NVIC_ISER0_SETENA2_BITN 2 -#define CPU_SCS_NVIC_ISER0_SETENA2_M 0x00000004 -#define CPU_SCS_NVIC_ISER0_SETENA2_S 2 +#define CPU_SCS_NVIC_ISER0_SETENA2 0x00000004 +#define CPU_SCS_NVIC_ISER0_SETENA2_BITN 2 +#define CPU_SCS_NVIC_ISER0_SETENA2_M 0x00000004 +#define CPU_SCS_NVIC_ISER0_SETENA2_S 2 // Field: [1] SETENA1 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA1 0x00000002 -#define CPU_SCS_NVIC_ISER0_SETENA1_BITN 1 -#define CPU_SCS_NVIC_ISER0_SETENA1_M 0x00000002 -#define CPU_SCS_NVIC_ISER0_SETENA1_S 1 +#define CPU_SCS_NVIC_ISER0_SETENA1 0x00000002 +#define CPU_SCS_NVIC_ISER0_SETENA1_BITN 1 +#define CPU_SCS_NVIC_ISER0_SETENA1_M 0x00000002 +#define CPU_SCS_NVIC_ISER0_SETENA1_S 1 // Field: [0] SETENA0 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA0 0x00000001 -#define CPU_SCS_NVIC_ISER0_SETENA0_BITN 0 -#define CPU_SCS_NVIC_ISER0_SETENA0_M 0x00000001 -#define CPU_SCS_NVIC_ISER0_SETENA0_S 0 +#define CPU_SCS_NVIC_ISER0_SETENA0 0x00000001 +#define CPU_SCS_NVIC_ISER0_SETENA0_BITN 0 +#define CPU_SCS_NVIC_ISER0_SETENA0_M 0x00000001 +#define CPU_SCS_NVIC_ISER0_SETENA0_S 0 //***************************************************************************** // @@ -795,60 +795,60 @@ // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER1_SETENA37 0x00000020 -#define CPU_SCS_NVIC_ISER1_SETENA37_BITN 5 -#define CPU_SCS_NVIC_ISER1_SETENA37_M 0x00000020 -#define CPU_SCS_NVIC_ISER1_SETENA37_S 5 +#define CPU_SCS_NVIC_ISER1_SETENA37 0x00000020 +#define CPU_SCS_NVIC_ISER1_SETENA37_BITN 5 +#define CPU_SCS_NVIC_ISER1_SETENA37_M 0x00000020 +#define CPU_SCS_NVIC_ISER1_SETENA37_S 5 // Field: [4] SETENA36 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER1_SETENA36 0x00000010 -#define CPU_SCS_NVIC_ISER1_SETENA36_BITN 4 -#define CPU_SCS_NVIC_ISER1_SETENA36_M 0x00000010 -#define CPU_SCS_NVIC_ISER1_SETENA36_S 4 +#define CPU_SCS_NVIC_ISER1_SETENA36 0x00000010 +#define CPU_SCS_NVIC_ISER1_SETENA36_BITN 4 +#define CPU_SCS_NVIC_ISER1_SETENA36_M 0x00000010 +#define CPU_SCS_NVIC_ISER1_SETENA36_S 4 // Field: [3] SETENA35 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER1_SETENA35 0x00000008 -#define CPU_SCS_NVIC_ISER1_SETENA35_BITN 3 -#define CPU_SCS_NVIC_ISER1_SETENA35_M 0x00000008 -#define CPU_SCS_NVIC_ISER1_SETENA35_S 3 +#define CPU_SCS_NVIC_ISER1_SETENA35 0x00000008 +#define CPU_SCS_NVIC_ISER1_SETENA35_BITN 3 +#define CPU_SCS_NVIC_ISER1_SETENA35_M 0x00000008 +#define CPU_SCS_NVIC_ISER1_SETENA35_S 3 // Field: [2] SETENA34 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER1_SETENA34 0x00000004 -#define CPU_SCS_NVIC_ISER1_SETENA34_BITN 2 -#define CPU_SCS_NVIC_ISER1_SETENA34_M 0x00000004 -#define CPU_SCS_NVIC_ISER1_SETENA34_S 2 +#define CPU_SCS_NVIC_ISER1_SETENA34 0x00000004 +#define CPU_SCS_NVIC_ISER1_SETENA34_BITN 2 +#define CPU_SCS_NVIC_ISER1_SETENA34_M 0x00000004 +#define CPU_SCS_NVIC_ISER1_SETENA34_S 2 // Field: [1] SETENA33 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER1_SETENA33 0x00000002 -#define CPU_SCS_NVIC_ISER1_SETENA33_BITN 1 -#define CPU_SCS_NVIC_ISER1_SETENA33_M 0x00000002 -#define CPU_SCS_NVIC_ISER1_SETENA33_S 1 +#define CPU_SCS_NVIC_ISER1_SETENA33 0x00000002 +#define CPU_SCS_NVIC_ISER1_SETENA33_BITN 1 +#define CPU_SCS_NVIC_ISER1_SETENA33_M 0x00000002 +#define CPU_SCS_NVIC_ISER1_SETENA33_S 1 // Field: [0] SETENA32 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER1_SETENA32 0x00000001 -#define CPU_SCS_NVIC_ISER1_SETENA32_BITN 0 -#define CPU_SCS_NVIC_ISER1_SETENA32_M 0x00000001 -#define CPU_SCS_NVIC_ISER1_SETENA32_S 0 +#define CPU_SCS_NVIC_ISER1_SETENA32 0x00000001 +#define CPU_SCS_NVIC_ISER1_SETENA32_BITN 0 +#define CPU_SCS_NVIC_ISER1_SETENA32_M 0x00000001 +#define CPU_SCS_NVIC_ISER1_SETENA32_S 0 //***************************************************************************** // @@ -860,320 +860,320 @@ // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA31 0x80000000 -#define CPU_SCS_NVIC_ICER0_CLRENA31_BITN 31 -#define CPU_SCS_NVIC_ICER0_CLRENA31_M 0x80000000 -#define CPU_SCS_NVIC_ICER0_CLRENA31_S 31 +#define CPU_SCS_NVIC_ICER0_CLRENA31 0x80000000 +#define CPU_SCS_NVIC_ICER0_CLRENA31_BITN 31 +#define CPU_SCS_NVIC_ICER0_CLRENA31_M 0x80000000 +#define CPU_SCS_NVIC_ICER0_CLRENA31_S 31 // Field: [30] CLRENA30 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA30 0x40000000 -#define CPU_SCS_NVIC_ICER0_CLRENA30_BITN 30 -#define CPU_SCS_NVIC_ICER0_CLRENA30_M 0x40000000 -#define CPU_SCS_NVIC_ICER0_CLRENA30_S 30 +#define CPU_SCS_NVIC_ICER0_CLRENA30 0x40000000 +#define CPU_SCS_NVIC_ICER0_CLRENA30_BITN 30 +#define CPU_SCS_NVIC_ICER0_CLRENA30_M 0x40000000 +#define CPU_SCS_NVIC_ICER0_CLRENA30_S 30 // Field: [29] CLRENA29 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA29 0x20000000 -#define CPU_SCS_NVIC_ICER0_CLRENA29_BITN 29 -#define CPU_SCS_NVIC_ICER0_CLRENA29_M 0x20000000 -#define CPU_SCS_NVIC_ICER0_CLRENA29_S 29 +#define CPU_SCS_NVIC_ICER0_CLRENA29 0x20000000 +#define CPU_SCS_NVIC_ICER0_CLRENA29_BITN 29 +#define CPU_SCS_NVIC_ICER0_CLRENA29_M 0x20000000 +#define CPU_SCS_NVIC_ICER0_CLRENA29_S 29 // Field: [28] CLRENA28 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA28 0x10000000 -#define CPU_SCS_NVIC_ICER0_CLRENA28_BITN 28 -#define CPU_SCS_NVIC_ICER0_CLRENA28_M 0x10000000 -#define CPU_SCS_NVIC_ICER0_CLRENA28_S 28 +#define CPU_SCS_NVIC_ICER0_CLRENA28 0x10000000 +#define CPU_SCS_NVIC_ICER0_CLRENA28_BITN 28 +#define CPU_SCS_NVIC_ICER0_CLRENA28_M 0x10000000 +#define CPU_SCS_NVIC_ICER0_CLRENA28_S 28 // Field: [27] CLRENA27 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA27 0x08000000 -#define CPU_SCS_NVIC_ICER0_CLRENA27_BITN 27 -#define CPU_SCS_NVIC_ICER0_CLRENA27_M 0x08000000 -#define CPU_SCS_NVIC_ICER0_CLRENA27_S 27 +#define CPU_SCS_NVIC_ICER0_CLRENA27 0x08000000 +#define CPU_SCS_NVIC_ICER0_CLRENA27_BITN 27 +#define CPU_SCS_NVIC_ICER0_CLRENA27_M 0x08000000 +#define CPU_SCS_NVIC_ICER0_CLRENA27_S 27 // Field: [26] CLRENA26 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA26 0x04000000 -#define CPU_SCS_NVIC_ICER0_CLRENA26_BITN 26 -#define CPU_SCS_NVIC_ICER0_CLRENA26_M 0x04000000 -#define CPU_SCS_NVIC_ICER0_CLRENA26_S 26 +#define CPU_SCS_NVIC_ICER0_CLRENA26 0x04000000 +#define CPU_SCS_NVIC_ICER0_CLRENA26_BITN 26 +#define CPU_SCS_NVIC_ICER0_CLRENA26_M 0x04000000 +#define CPU_SCS_NVIC_ICER0_CLRENA26_S 26 // Field: [25] CLRENA25 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA25 0x02000000 -#define CPU_SCS_NVIC_ICER0_CLRENA25_BITN 25 -#define CPU_SCS_NVIC_ICER0_CLRENA25_M 0x02000000 -#define CPU_SCS_NVIC_ICER0_CLRENA25_S 25 +#define CPU_SCS_NVIC_ICER0_CLRENA25 0x02000000 +#define CPU_SCS_NVIC_ICER0_CLRENA25_BITN 25 +#define CPU_SCS_NVIC_ICER0_CLRENA25_M 0x02000000 +#define CPU_SCS_NVIC_ICER0_CLRENA25_S 25 // Field: [24] CLRENA24 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA24 0x01000000 -#define CPU_SCS_NVIC_ICER0_CLRENA24_BITN 24 -#define CPU_SCS_NVIC_ICER0_CLRENA24_M 0x01000000 -#define CPU_SCS_NVIC_ICER0_CLRENA24_S 24 +#define CPU_SCS_NVIC_ICER0_CLRENA24 0x01000000 +#define CPU_SCS_NVIC_ICER0_CLRENA24_BITN 24 +#define CPU_SCS_NVIC_ICER0_CLRENA24_M 0x01000000 +#define CPU_SCS_NVIC_ICER0_CLRENA24_S 24 // Field: [23] CLRENA23 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA23 0x00800000 -#define CPU_SCS_NVIC_ICER0_CLRENA23_BITN 23 -#define CPU_SCS_NVIC_ICER0_CLRENA23_M 0x00800000 -#define CPU_SCS_NVIC_ICER0_CLRENA23_S 23 +#define CPU_SCS_NVIC_ICER0_CLRENA23 0x00800000 +#define CPU_SCS_NVIC_ICER0_CLRENA23_BITN 23 +#define CPU_SCS_NVIC_ICER0_CLRENA23_M 0x00800000 +#define CPU_SCS_NVIC_ICER0_CLRENA23_S 23 // Field: [22] CLRENA22 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA22 0x00400000 -#define CPU_SCS_NVIC_ICER0_CLRENA22_BITN 22 -#define CPU_SCS_NVIC_ICER0_CLRENA22_M 0x00400000 -#define CPU_SCS_NVIC_ICER0_CLRENA22_S 22 +#define CPU_SCS_NVIC_ICER0_CLRENA22 0x00400000 +#define CPU_SCS_NVIC_ICER0_CLRENA22_BITN 22 +#define CPU_SCS_NVIC_ICER0_CLRENA22_M 0x00400000 +#define CPU_SCS_NVIC_ICER0_CLRENA22_S 22 // Field: [21] CLRENA21 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA21 0x00200000 -#define CPU_SCS_NVIC_ICER0_CLRENA21_BITN 21 -#define CPU_SCS_NVIC_ICER0_CLRENA21_M 0x00200000 -#define CPU_SCS_NVIC_ICER0_CLRENA21_S 21 +#define CPU_SCS_NVIC_ICER0_CLRENA21 0x00200000 +#define CPU_SCS_NVIC_ICER0_CLRENA21_BITN 21 +#define CPU_SCS_NVIC_ICER0_CLRENA21_M 0x00200000 +#define CPU_SCS_NVIC_ICER0_CLRENA21_S 21 // Field: [20] CLRENA20 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA20 0x00100000 -#define CPU_SCS_NVIC_ICER0_CLRENA20_BITN 20 -#define CPU_SCS_NVIC_ICER0_CLRENA20_M 0x00100000 -#define CPU_SCS_NVIC_ICER0_CLRENA20_S 20 +#define CPU_SCS_NVIC_ICER0_CLRENA20 0x00100000 +#define CPU_SCS_NVIC_ICER0_CLRENA20_BITN 20 +#define CPU_SCS_NVIC_ICER0_CLRENA20_M 0x00100000 +#define CPU_SCS_NVIC_ICER0_CLRENA20_S 20 // Field: [19] CLRENA19 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA19 0x00080000 -#define CPU_SCS_NVIC_ICER0_CLRENA19_BITN 19 -#define CPU_SCS_NVIC_ICER0_CLRENA19_M 0x00080000 -#define CPU_SCS_NVIC_ICER0_CLRENA19_S 19 +#define CPU_SCS_NVIC_ICER0_CLRENA19 0x00080000 +#define CPU_SCS_NVIC_ICER0_CLRENA19_BITN 19 +#define CPU_SCS_NVIC_ICER0_CLRENA19_M 0x00080000 +#define CPU_SCS_NVIC_ICER0_CLRENA19_S 19 // Field: [18] CLRENA18 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA18 0x00040000 -#define CPU_SCS_NVIC_ICER0_CLRENA18_BITN 18 -#define CPU_SCS_NVIC_ICER0_CLRENA18_M 0x00040000 -#define CPU_SCS_NVIC_ICER0_CLRENA18_S 18 +#define CPU_SCS_NVIC_ICER0_CLRENA18 0x00040000 +#define CPU_SCS_NVIC_ICER0_CLRENA18_BITN 18 +#define CPU_SCS_NVIC_ICER0_CLRENA18_M 0x00040000 +#define CPU_SCS_NVIC_ICER0_CLRENA18_S 18 // Field: [17] CLRENA17 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA17 0x00020000 -#define CPU_SCS_NVIC_ICER0_CLRENA17_BITN 17 -#define CPU_SCS_NVIC_ICER0_CLRENA17_M 0x00020000 -#define CPU_SCS_NVIC_ICER0_CLRENA17_S 17 +#define CPU_SCS_NVIC_ICER0_CLRENA17 0x00020000 +#define CPU_SCS_NVIC_ICER0_CLRENA17_BITN 17 +#define CPU_SCS_NVIC_ICER0_CLRENA17_M 0x00020000 +#define CPU_SCS_NVIC_ICER0_CLRENA17_S 17 // Field: [16] CLRENA16 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA16 0x00010000 -#define CPU_SCS_NVIC_ICER0_CLRENA16_BITN 16 -#define CPU_SCS_NVIC_ICER0_CLRENA16_M 0x00010000 -#define CPU_SCS_NVIC_ICER0_CLRENA16_S 16 +#define CPU_SCS_NVIC_ICER0_CLRENA16 0x00010000 +#define CPU_SCS_NVIC_ICER0_CLRENA16_BITN 16 +#define CPU_SCS_NVIC_ICER0_CLRENA16_M 0x00010000 +#define CPU_SCS_NVIC_ICER0_CLRENA16_S 16 // Field: [15] CLRENA15 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA15 0x00008000 -#define CPU_SCS_NVIC_ICER0_CLRENA15_BITN 15 -#define CPU_SCS_NVIC_ICER0_CLRENA15_M 0x00008000 -#define CPU_SCS_NVIC_ICER0_CLRENA15_S 15 +#define CPU_SCS_NVIC_ICER0_CLRENA15 0x00008000 +#define CPU_SCS_NVIC_ICER0_CLRENA15_BITN 15 +#define CPU_SCS_NVIC_ICER0_CLRENA15_M 0x00008000 +#define CPU_SCS_NVIC_ICER0_CLRENA15_S 15 // Field: [14] CLRENA14 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA14 0x00004000 -#define CPU_SCS_NVIC_ICER0_CLRENA14_BITN 14 -#define CPU_SCS_NVIC_ICER0_CLRENA14_M 0x00004000 -#define CPU_SCS_NVIC_ICER0_CLRENA14_S 14 +#define CPU_SCS_NVIC_ICER0_CLRENA14 0x00004000 +#define CPU_SCS_NVIC_ICER0_CLRENA14_BITN 14 +#define CPU_SCS_NVIC_ICER0_CLRENA14_M 0x00004000 +#define CPU_SCS_NVIC_ICER0_CLRENA14_S 14 // Field: [13] CLRENA13 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA13 0x00002000 -#define CPU_SCS_NVIC_ICER0_CLRENA13_BITN 13 -#define CPU_SCS_NVIC_ICER0_CLRENA13_M 0x00002000 -#define CPU_SCS_NVIC_ICER0_CLRENA13_S 13 +#define CPU_SCS_NVIC_ICER0_CLRENA13 0x00002000 +#define CPU_SCS_NVIC_ICER0_CLRENA13_BITN 13 +#define CPU_SCS_NVIC_ICER0_CLRENA13_M 0x00002000 +#define CPU_SCS_NVIC_ICER0_CLRENA13_S 13 // Field: [12] CLRENA12 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA12 0x00001000 -#define CPU_SCS_NVIC_ICER0_CLRENA12_BITN 12 -#define CPU_SCS_NVIC_ICER0_CLRENA12_M 0x00001000 -#define CPU_SCS_NVIC_ICER0_CLRENA12_S 12 +#define CPU_SCS_NVIC_ICER0_CLRENA12 0x00001000 +#define CPU_SCS_NVIC_ICER0_CLRENA12_BITN 12 +#define CPU_SCS_NVIC_ICER0_CLRENA12_M 0x00001000 +#define CPU_SCS_NVIC_ICER0_CLRENA12_S 12 // Field: [11] CLRENA11 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA11 0x00000800 -#define CPU_SCS_NVIC_ICER0_CLRENA11_BITN 11 -#define CPU_SCS_NVIC_ICER0_CLRENA11_M 0x00000800 -#define CPU_SCS_NVIC_ICER0_CLRENA11_S 11 +#define CPU_SCS_NVIC_ICER0_CLRENA11 0x00000800 +#define CPU_SCS_NVIC_ICER0_CLRENA11_BITN 11 +#define CPU_SCS_NVIC_ICER0_CLRENA11_M 0x00000800 +#define CPU_SCS_NVIC_ICER0_CLRENA11_S 11 // Field: [10] CLRENA10 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA10 0x00000400 -#define CPU_SCS_NVIC_ICER0_CLRENA10_BITN 10 -#define CPU_SCS_NVIC_ICER0_CLRENA10_M 0x00000400 -#define CPU_SCS_NVIC_ICER0_CLRENA10_S 10 +#define CPU_SCS_NVIC_ICER0_CLRENA10 0x00000400 +#define CPU_SCS_NVIC_ICER0_CLRENA10_BITN 10 +#define CPU_SCS_NVIC_ICER0_CLRENA10_M 0x00000400 +#define CPU_SCS_NVIC_ICER0_CLRENA10_S 10 // Field: [9] CLRENA9 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA9 0x00000200 -#define CPU_SCS_NVIC_ICER0_CLRENA9_BITN 9 -#define CPU_SCS_NVIC_ICER0_CLRENA9_M 0x00000200 -#define CPU_SCS_NVIC_ICER0_CLRENA9_S 9 +#define CPU_SCS_NVIC_ICER0_CLRENA9 0x00000200 +#define CPU_SCS_NVIC_ICER0_CLRENA9_BITN 9 +#define CPU_SCS_NVIC_ICER0_CLRENA9_M 0x00000200 +#define CPU_SCS_NVIC_ICER0_CLRENA9_S 9 // Field: [8] CLRENA8 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA8 0x00000100 -#define CPU_SCS_NVIC_ICER0_CLRENA8_BITN 8 -#define CPU_SCS_NVIC_ICER0_CLRENA8_M 0x00000100 -#define CPU_SCS_NVIC_ICER0_CLRENA8_S 8 +#define CPU_SCS_NVIC_ICER0_CLRENA8 0x00000100 +#define CPU_SCS_NVIC_ICER0_CLRENA8_BITN 8 +#define CPU_SCS_NVIC_ICER0_CLRENA8_M 0x00000100 +#define CPU_SCS_NVIC_ICER0_CLRENA8_S 8 // Field: [7] CLRENA7 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA7 0x00000080 -#define CPU_SCS_NVIC_ICER0_CLRENA7_BITN 7 -#define CPU_SCS_NVIC_ICER0_CLRENA7_M 0x00000080 -#define CPU_SCS_NVIC_ICER0_CLRENA7_S 7 +#define CPU_SCS_NVIC_ICER0_CLRENA7 0x00000080 +#define CPU_SCS_NVIC_ICER0_CLRENA7_BITN 7 +#define CPU_SCS_NVIC_ICER0_CLRENA7_M 0x00000080 +#define CPU_SCS_NVIC_ICER0_CLRENA7_S 7 // Field: [6] CLRENA6 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA6 0x00000040 -#define CPU_SCS_NVIC_ICER0_CLRENA6_BITN 6 -#define CPU_SCS_NVIC_ICER0_CLRENA6_M 0x00000040 -#define CPU_SCS_NVIC_ICER0_CLRENA6_S 6 +#define CPU_SCS_NVIC_ICER0_CLRENA6 0x00000040 +#define CPU_SCS_NVIC_ICER0_CLRENA6_BITN 6 +#define CPU_SCS_NVIC_ICER0_CLRENA6_M 0x00000040 +#define CPU_SCS_NVIC_ICER0_CLRENA6_S 6 // Field: [5] CLRENA5 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA5 0x00000020 -#define CPU_SCS_NVIC_ICER0_CLRENA5_BITN 5 -#define CPU_SCS_NVIC_ICER0_CLRENA5_M 0x00000020 -#define CPU_SCS_NVIC_ICER0_CLRENA5_S 5 +#define CPU_SCS_NVIC_ICER0_CLRENA5 0x00000020 +#define CPU_SCS_NVIC_ICER0_CLRENA5_BITN 5 +#define CPU_SCS_NVIC_ICER0_CLRENA5_M 0x00000020 +#define CPU_SCS_NVIC_ICER0_CLRENA5_S 5 // Field: [4] CLRENA4 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA4 0x00000010 -#define CPU_SCS_NVIC_ICER0_CLRENA4_BITN 4 -#define CPU_SCS_NVIC_ICER0_CLRENA4_M 0x00000010 -#define CPU_SCS_NVIC_ICER0_CLRENA4_S 4 +#define CPU_SCS_NVIC_ICER0_CLRENA4 0x00000010 +#define CPU_SCS_NVIC_ICER0_CLRENA4_BITN 4 +#define CPU_SCS_NVIC_ICER0_CLRENA4_M 0x00000010 +#define CPU_SCS_NVIC_ICER0_CLRENA4_S 4 // Field: [3] CLRENA3 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA3 0x00000008 -#define CPU_SCS_NVIC_ICER0_CLRENA3_BITN 3 -#define CPU_SCS_NVIC_ICER0_CLRENA3_M 0x00000008 -#define CPU_SCS_NVIC_ICER0_CLRENA3_S 3 +#define CPU_SCS_NVIC_ICER0_CLRENA3 0x00000008 +#define CPU_SCS_NVIC_ICER0_CLRENA3_BITN 3 +#define CPU_SCS_NVIC_ICER0_CLRENA3_M 0x00000008 +#define CPU_SCS_NVIC_ICER0_CLRENA3_S 3 // Field: [2] CLRENA2 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA2 0x00000004 -#define CPU_SCS_NVIC_ICER0_CLRENA2_BITN 2 -#define CPU_SCS_NVIC_ICER0_CLRENA2_M 0x00000004 -#define CPU_SCS_NVIC_ICER0_CLRENA2_S 2 +#define CPU_SCS_NVIC_ICER0_CLRENA2 0x00000004 +#define CPU_SCS_NVIC_ICER0_CLRENA2_BITN 2 +#define CPU_SCS_NVIC_ICER0_CLRENA2_M 0x00000004 +#define CPU_SCS_NVIC_ICER0_CLRENA2_S 2 // Field: [1] CLRENA1 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA1 0x00000002 -#define CPU_SCS_NVIC_ICER0_CLRENA1_BITN 1 -#define CPU_SCS_NVIC_ICER0_CLRENA1_M 0x00000002 -#define CPU_SCS_NVIC_ICER0_CLRENA1_S 1 +#define CPU_SCS_NVIC_ICER0_CLRENA1 0x00000002 +#define CPU_SCS_NVIC_ICER0_CLRENA1_BITN 1 +#define CPU_SCS_NVIC_ICER0_CLRENA1_M 0x00000002 +#define CPU_SCS_NVIC_ICER0_CLRENA1_S 1 // Field: [0] CLRENA0 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA0 0x00000001 -#define CPU_SCS_NVIC_ICER0_CLRENA0_BITN 0 -#define CPU_SCS_NVIC_ICER0_CLRENA0_M 0x00000001 -#define CPU_SCS_NVIC_ICER0_CLRENA0_S 0 +#define CPU_SCS_NVIC_ICER0_CLRENA0 0x00000001 +#define CPU_SCS_NVIC_ICER0_CLRENA0_BITN 0 +#define CPU_SCS_NVIC_ICER0_CLRENA0_M 0x00000001 +#define CPU_SCS_NVIC_ICER0_CLRENA0_S 0 //***************************************************************************** // @@ -1185,60 +1185,60 @@ // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER1_CLRENA37 0x00000020 -#define CPU_SCS_NVIC_ICER1_CLRENA37_BITN 5 -#define CPU_SCS_NVIC_ICER1_CLRENA37_M 0x00000020 -#define CPU_SCS_NVIC_ICER1_CLRENA37_S 5 +#define CPU_SCS_NVIC_ICER1_CLRENA37 0x00000020 +#define CPU_SCS_NVIC_ICER1_CLRENA37_BITN 5 +#define CPU_SCS_NVIC_ICER1_CLRENA37_M 0x00000020 +#define CPU_SCS_NVIC_ICER1_CLRENA37_S 5 // Field: [4] CLRENA36 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER1_CLRENA36 0x00000010 -#define CPU_SCS_NVIC_ICER1_CLRENA36_BITN 4 -#define CPU_SCS_NVIC_ICER1_CLRENA36_M 0x00000010 -#define CPU_SCS_NVIC_ICER1_CLRENA36_S 4 +#define CPU_SCS_NVIC_ICER1_CLRENA36 0x00000010 +#define CPU_SCS_NVIC_ICER1_CLRENA36_BITN 4 +#define CPU_SCS_NVIC_ICER1_CLRENA36_M 0x00000010 +#define CPU_SCS_NVIC_ICER1_CLRENA36_S 4 // Field: [3] CLRENA35 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER1_CLRENA35 0x00000008 -#define CPU_SCS_NVIC_ICER1_CLRENA35_BITN 3 -#define CPU_SCS_NVIC_ICER1_CLRENA35_M 0x00000008 -#define CPU_SCS_NVIC_ICER1_CLRENA35_S 3 +#define CPU_SCS_NVIC_ICER1_CLRENA35 0x00000008 +#define CPU_SCS_NVIC_ICER1_CLRENA35_BITN 3 +#define CPU_SCS_NVIC_ICER1_CLRENA35_M 0x00000008 +#define CPU_SCS_NVIC_ICER1_CLRENA35_S 3 // Field: [2] CLRENA34 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER1_CLRENA34 0x00000004 -#define CPU_SCS_NVIC_ICER1_CLRENA34_BITN 2 -#define CPU_SCS_NVIC_ICER1_CLRENA34_M 0x00000004 -#define CPU_SCS_NVIC_ICER1_CLRENA34_S 2 +#define CPU_SCS_NVIC_ICER1_CLRENA34 0x00000004 +#define CPU_SCS_NVIC_ICER1_CLRENA34_BITN 2 +#define CPU_SCS_NVIC_ICER1_CLRENA34_M 0x00000004 +#define CPU_SCS_NVIC_ICER1_CLRENA34_S 2 // Field: [1] CLRENA33 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER1_CLRENA33 0x00000002 -#define CPU_SCS_NVIC_ICER1_CLRENA33_BITN 1 -#define CPU_SCS_NVIC_ICER1_CLRENA33_M 0x00000002 -#define CPU_SCS_NVIC_ICER1_CLRENA33_S 1 +#define CPU_SCS_NVIC_ICER1_CLRENA33 0x00000002 +#define CPU_SCS_NVIC_ICER1_CLRENA33_BITN 1 +#define CPU_SCS_NVIC_ICER1_CLRENA33_M 0x00000002 +#define CPU_SCS_NVIC_ICER1_CLRENA33_S 1 // Field: [0] CLRENA32 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER1_CLRENA32 0x00000001 -#define CPU_SCS_NVIC_ICER1_CLRENA32_BITN 0 -#define CPU_SCS_NVIC_ICER1_CLRENA32_M 0x00000001 -#define CPU_SCS_NVIC_ICER1_CLRENA32_S 0 +#define CPU_SCS_NVIC_ICER1_CLRENA32 0x00000001 +#define CPU_SCS_NVIC_ICER1_CLRENA32_BITN 0 +#define CPU_SCS_NVIC_ICER1_CLRENA32_M 0x00000001 +#define CPU_SCS_NVIC_ICER1_CLRENA32_S 0 //***************************************************************************** // @@ -1250,320 +1250,320 @@ // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND31 0x80000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND31_BITN 31 -#define CPU_SCS_NVIC_ISPR0_SETPEND31_M 0x80000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND31_S 31 +#define CPU_SCS_NVIC_ISPR0_SETPEND31 0x80000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_BITN 31 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_M 0x80000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_S 31 // Field: [30] SETPEND30 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND30 0x40000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND30_BITN 30 -#define CPU_SCS_NVIC_ISPR0_SETPEND30_M 0x40000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND30_S 30 +#define CPU_SCS_NVIC_ISPR0_SETPEND30 0x40000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_BITN 30 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_M 0x40000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_S 30 // Field: [29] SETPEND29 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND29 0x20000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND29_BITN 29 -#define CPU_SCS_NVIC_ISPR0_SETPEND29_M 0x20000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND29_S 29 +#define CPU_SCS_NVIC_ISPR0_SETPEND29 0x20000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_BITN 29 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_M 0x20000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_S 29 // Field: [28] SETPEND28 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND28 0x10000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND28_BITN 28 -#define CPU_SCS_NVIC_ISPR0_SETPEND28_M 0x10000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND28_S 28 +#define CPU_SCS_NVIC_ISPR0_SETPEND28 0x10000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_BITN 28 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_M 0x10000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_S 28 // Field: [27] SETPEND27 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND27 0x08000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND27_BITN 27 -#define CPU_SCS_NVIC_ISPR0_SETPEND27_M 0x08000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND27_S 27 +#define CPU_SCS_NVIC_ISPR0_SETPEND27 0x08000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_BITN 27 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_M 0x08000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_S 27 // Field: [26] SETPEND26 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND26 0x04000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND26_BITN 26 -#define CPU_SCS_NVIC_ISPR0_SETPEND26_M 0x04000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND26_S 26 +#define CPU_SCS_NVIC_ISPR0_SETPEND26 0x04000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_BITN 26 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_M 0x04000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_S 26 // Field: [25] SETPEND25 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND25 0x02000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND25_BITN 25 -#define CPU_SCS_NVIC_ISPR0_SETPEND25_M 0x02000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND25_S 25 +#define CPU_SCS_NVIC_ISPR0_SETPEND25 0x02000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_BITN 25 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_M 0x02000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_S 25 // Field: [24] SETPEND24 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND24 0x01000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND24_BITN 24 -#define CPU_SCS_NVIC_ISPR0_SETPEND24_M 0x01000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND24_S 24 +#define CPU_SCS_NVIC_ISPR0_SETPEND24 0x01000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_BITN 24 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_M 0x01000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_S 24 // Field: [23] SETPEND23 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND23 0x00800000 -#define CPU_SCS_NVIC_ISPR0_SETPEND23_BITN 23 -#define CPU_SCS_NVIC_ISPR0_SETPEND23_M 0x00800000 -#define CPU_SCS_NVIC_ISPR0_SETPEND23_S 23 +#define CPU_SCS_NVIC_ISPR0_SETPEND23 0x00800000 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_BITN 23 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_M 0x00800000 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_S 23 // Field: [22] SETPEND22 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND22 0x00400000 -#define CPU_SCS_NVIC_ISPR0_SETPEND22_BITN 22 -#define CPU_SCS_NVIC_ISPR0_SETPEND22_M 0x00400000 -#define CPU_SCS_NVIC_ISPR0_SETPEND22_S 22 +#define CPU_SCS_NVIC_ISPR0_SETPEND22 0x00400000 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_BITN 22 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_M 0x00400000 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_S 22 // Field: [21] SETPEND21 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND21 0x00200000 -#define CPU_SCS_NVIC_ISPR0_SETPEND21_BITN 21 -#define CPU_SCS_NVIC_ISPR0_SETPEND21_M 0x00200000 -#define CPU_SCS_NVIC_ISPR0_SETPEND21_S 21 +#define CPU_SCS_NVIC_ISPR0_SETPEND21 0x00200000 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_BITN 21 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_M 0x00200000 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_S 21 // Field: [20] SETPEND20 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND20 0x00100000 -#define CPU_SCS_NVIC_ISPR0_SETPEND20_BITN 20 -#define CPU_SCS_NVIC_ISPR0_SETPEND20_M 0x00100000 -#define CPU_SCS_NVIC_ISPR0_SETPEND20_S 20 +#define CPU_SCS_NVIC_ISPR0_SETPEND20 0x00100000 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_BITN 20 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_M 0x00100000 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_S 20 // Field: [19] SETPEND19 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND19 0x00080000 -#define CPU_SCS_NVIC_ISPR0_SETPEND19_BITN 19 -#define CPU_SCS_NVIC_ISPR0_SETPEND19_M 0x00080000 -#define CPU_SCS_NVIC_ISPR0_SETPEND19_S 19 +#define CPU_SCS_NVIC_ISPR0_SETPEND19 0x00080000 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_BITN 19 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_M 0x00080000 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_S 19 // Field: [18] SETPEND18 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND18 0x00040000 -#define CPU_SCS_NVIC_ISPR0_SETPEND18_BITN 18 -#define CPU_SCS_NVIC_ISPR0_SETPEND18_M 0x00040000 -#define CPU_SCS_NVIC_ISPR0_SETPEND18_S 18 +#define CPU_SCS_NVIC_ISPR0_SETPEND18 0x00040000 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_BITN 18 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_M 0x00040000 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_S 18 // Field: [17] SETPEND17 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND17 0x00020000 -#define CPU_SCS_NVIC_ISPR0_SETPEND17_BITN 17 -#define CPU_SCS_NVIC_ISPR0_SETPEND17_M 0x00020000 -#define CPU_SCS_NVIC_ISPR0_SETPEND17_S 17 +#define CPU_SCS_NVIC_ISPR0_SETPEND17 0x00020000 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_BITN 17 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_M 0x00020000 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_S 17 // Field: [16] SETPEND16 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND16 0x00010000 -#define CPU_SCS_NVIC_ISPR0_SETPEND16_BITN 16 -#define CPU_SCS_NVIC_ISPR0_SETPEND16_M 0x00010000 -#define CPU_SCS_NVIC_ISPR0_SETPEND16_S 16 +#define CPU_SCS_NVIC_ISPR0_SETPEND16 0x00010000 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_BITN 16 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_M 0x00010000 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_S 16 // Field: [15] SETPEND15 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND15 0x00008000 -#define CPU_SCS_NVIC_ISPR0_SETPEND15_BITN 15 -#define CPU_SCS_NVIC_ISPR0_SETPEND15_M 0x00008000 -#define CPU_SCS_NVIC_ISPR0_SETPEND15_S 15 +#define CPU_SCS_NVIC_ISPR0_SETPEND15 0x00008000 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_BITN 15 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_M 0x00008000 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_S 15 // Field: [14] SETPEND14 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND14 0x00004000 -#define CPU_SCS_NVIC_ISPR0_SETPEND14_BITN 14 -#define CPU_SCS_NVIC_ISPR0_SETPEND14_M 0x00004000 -#define CPU_SCS_NVIC_ISPR0_SETPEND14_S 14 +#define CPU_SCS_NVIC_ISPR0_SETPEND14 0x00004000 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_BITN 14 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_M 0x00004000 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_S 14 // Field: [13] SETPEND13 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND13 0x00002000 -#define CPU_SCS_NVIC_ISPR0_SETPEND13_BITN 13 -#define CPU_SCS_NVIC_ISPR0_SETPEND13_M 0x00002000 -#define CPU_SCS_NVIC_ISPR0_SETPEND13_S 13 +#define CPU_SCS_NVIC_ISPR0_SETPEND13 0x00002000 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_BITN 13 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_M 0x00002000 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_S 13 // Field: [12] SETPEND12 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND12 0x00001000 -#define CPU_SCS_NVIC_ISPR0_SETPEND12_BITN 12 -#define CPU_SCS_NVIC_ISPR0_SETPEND12_M 0x00001000 -#define CPU_SCS_NVIC_ISPR0_SETPEND12_S 12 +#define CPU_SCS_NVIC_ISPR0_SETPEND12 0x00001000 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_BITN 12 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_M 0x00001000 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_S 12 // Field: [11] SETPEND11 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND11 0x00000800 -#define CPU_SCS_NVIC_ISPR0_SETPEND11_BITN 11 -#define CPU_SCS_NVIC_ISPR0_SETPEND11_M 0x00000800 -#define CPU_SCS_NVIC_ISPR0_SETPEND11_S 11 +#define CPU_SCS_NVIC_ISPR0_SETPEND11 0x00000800 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_BITN 11 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_M 0x00000800 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_S 11 // Field: [10] SETPEND10 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND10 0x00000400 -#define CPU_SCS_NVIC_ISPR0_SETPEND10_BITN 10 -#define CPU_SCS_NVIC_ISPR0_SETPEND10_M 0x00000400 -#define CPU_SCS_NVIC_ISPR0_SETPEND10_S 10 +#define CPU_SCS_NVIC_ISPR0_SETPEND10 0x00000400 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_BITN 10 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_M 0x00000400 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_S 10 // Field: [9] SETPEND9 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND9 0x00000200 -#define CPU_SCS_NVIC_ISPR0_SETPEND9_BITN 9 -#define CPU_SCS_NVIC_ISPR0_SETPEND9_M 0x00000200 -#define CPU_SCS_NVIC_ISPR0_SETPEND9_S 9 +#define CPU_SCS_NVIC_ISPR0_SETPEND9 0x00000200 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_BITN 9 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_M 0x00000200 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_S 9 // Field: [8] SETPEND8 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND8 0x00000100 -#define CPU_SCS_NVIC_ISPR0_SETPEND8_BITN 8 -#define CPU_SCS_NVIC_ISPR0_SETPEND8_M 0x00000100 -#define CPU_SCS_NVIC_ISPR0_SETPEND8_S 8 +#define CPU_SCS_NVIC_ISPR0_SETPEND8 0x00000100 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_BITN 8 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_M 0x00000100 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_S 8 // Field: [7] SETPEND7 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND7 0x00000080 -#define CPU_SCS_NVIC_ISPR0_SETPEND7_BITN 7 -#define CPU_SCS_NVIC_ISPR0_SETPEND7_M 0x00000080 -#define CPU_SCS_NVIC_ISPR0_SETPEND7_S 7 +#define CPU_SCS_NVIC_ISPR0_SETPEND7 0x00000080 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_BITN 7 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_M 0x00000080 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_S 7 // Field: [6] SETPEND6 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND6 0x00000040 -#define CPU_SCS_NVIC_ISPR0_SETPEND6_BITN 6 -#define CPU_SCS_NVIC_ISPR0_SETPEND6_M 0x00000040 -#define CPU_SCS_NVIC_ISPR0_SETPEND6_S 6 +#define CPU_SCS_NVIC_ISPR0_SETPEND6 0x00000040 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_BITN 6 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_M 0x00000040 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_S 6 // Field: [5] SETPEND5 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND5 0x00000020 -#define CPU_SCS_NVIC_ISPR0_SETPEND5_BITN 5 -#define CPU_SCS_NVIC_ISPR0_SETPEND5_M 0x00000020 -#define CPU_SCS_NVIC_ISPR0_SETPEND5_S 5 +#define CPU_SCS_NVIC_ISPR0_SETPEND5 0x00000020 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_BITN 5 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_M 0x00000020 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_S 5 // Field: [4] SETPEND4 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND4 0x00000010 -#define CPU_SCS_NVIC_ISPR0_SETPEND4_BITN 4 -#define CPU_SCS_NVIC_ISPR0_SETPEND4_M 0x00000010 -#define CPU_SCS_NVIC_ISPR0_SETPEND4_S 4 +#define CPU_SCS_NVIC_ISPR0_SETPEND4 0x00000010 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_BITN 4 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_M 0x00000010 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_S 4 // Field: [3] SETPEND3 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND3 0x00000008 -#define CPU_SCS_NVIC_ISPR0_SETPEND3_BITN 3 -#define CPU_SCS_NVIC_ISPR0_SETPEND3_M 0x00000008 -#define CPU_SCS_NVIC_ISPR0_SETPEND3_S 3 +#define CPU_SCS_NVIC_ISPR0_SETPEND3 0x00000008 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_BITN 3 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_M 0x00000008 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_S 3 // Field: [2] SETPEND2 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND2 0x00000004 -#define CPU_SCS_NVIC_ISPR0_SETPEND2_BITN 2 -#define CPU_SCS_NVIC_ISPR0_SETPEND2_M 0x00000004 -#define CPU_SCS_NVIC_ISPR0_SETPEND2_S 2 +#define CPU_SCS_NVIC_ISPR0_SETPEND2 0x00000004 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_BITN 2 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_M 0x00000004 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_S 2 // Field: [1] SETPEND1 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND1 0x00000002 -#define CPU_SCS_NVIC_ISPR0_SETPEND1_BITN 1 -#define CPU_SCS_NVIC_ISPR0_SETPEND1_M 0x00000002 -#define CPU_SCS_NVIC_ISPR0_SETPEND1_S 1 +#define CPU_SCS_NVIC_ISPR0_SETPEND1 0x00000002 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_BITN 1 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_M 0x00000002 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_S 1 // Field: [0] SETPEND0 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND0 0x00000001 -#define CPU_SCS_NVIC_ISPR0_SETPEND0_BITN 0 -#define CPU_SCS_NVIC_ISPR0_SETPEND0_M 0x00000001 -#define CPU_SCS_NVIC_ISPR0_SETPEND0_S 0 +#define CPU_SCS_NVIC_ISPR0_SETPEND0 0x00000001 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_BITN 0 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_M 0x00000001 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_S 0 //***************************************************************************** // @@ -1575,60 +1575,60 @@ // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR1_SETPEND37 0x00000020 -#define CPU_SCS_NVIC_ISPR1_SETPEND37_BITN 5 -#define CPU_SCS_NVIC_ISPR1_SETPEND37_M 0x00000020 -#define CPU_SCS_NVIC_ISPR1_SETPEND37_S 5 +#define CPU_SCS_NVIC_ISPR1_SETPEND37 0x00000020 +#define CPU_SCS_NVIC_ISPR1_SETPEND37_BITN 5 +#define CPU_SCS_NVIC_ISPR1_SETPEND37_M 0x00000020 +#define CPU_SCS_NVIC_ISPR1_SETPEND37_S 5 // Field: [4] SETPEND36 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR1_SETPEND36 0x00000010 -#define CPU_SCS_NVIC_ISPR1_SETPEND36_BITN 4 -#define CPU_SCS_NVIC_ISPR1_SETPEND36_M 0x00000010 -#define CPU_SCS_NVIC_ISPR1_SETPEND36_S 4 +#define CPU_SCS_NVIC_ISPR1_SETPEND36 0x00000010 +#define CPU_SCS_NVIC_ISPR1_SETPEND36_BITN 4 +#define CPU_SCS_NVIC_ISPR1_SETPEND36_M 0x00000010 +#define CPU_SCS_NVIC_ISPR1_SETPEND36_S 4 // Field: [3] SETPEND35 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR1_SETPEND35 0x00000008 -#define CPU_SCS_NVIC_ISPR1_SETPEND35_BITN 3 -#define CPU_SCS_NVIC_ISPR1_SETPEND35_M 0x00000008 -#define CPU_SCS_NVIC_ISPR1_SETPEND35_S 3 +#define CPU_SCS_NVIC_ISPR1_SETPEND35 0x00000008 +#define CPU_SCS_NVIC_ISPR1_SETPEND35_BITN 3 +#define CPU_SCS_NVIC_ISPR1_SETPEND35_M 0x00000008 +#define CPU_SCS_NVIC_ISPR1_SETPEND35_S 3 // Field: [2] SETPEND34 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR1_SETPEND34 0x00000004 -#define CPU_SCS_NVIC_ISPR1_SETPEND34_BITN 2 -#define CPU_SCS_NVIC_ISPR1_SETPEND34_M 0x00000004 -#define CPU_SCS_NVIC_ISPR1_SETPEND34_S 2 +#define CPU_SCS_NVIC_ISPR1_SETPEND34 0x00000004 +#define CPU_SCS_NVIC_ISPR1_SETPEND34_BITN 2 +#define CPU_SCS_NVIC_ISPR1_SETPEND34_M 0x00000004 +#define CPU_SCS_NVIC_ISPR1_SETPEND34_S 2 // Field: [1] SETPEND33 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR1_SETPEND33 0x00000002 -#define CPU_SCS_NVIC_ISPR1_SETPEND33_BITN 1 -#define CPU_SCS_NVIC_ISPR1_SETPEND33_M 0x00000002 -#define CPU_SCS_NVIC_ISPR1_SETPEND33_S 1 +#define CPU_SCS_NVIC_ISPR1_SETPEND33 0x00000002 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_BITN 1 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_M 0x00000002 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_S 1 // Field: [0] SETPEND32 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR1_SETPEND32 0x00000001 -#define CPU_SCS_NVIC_ISPR1_SETPEND32_BITN 0 -#define CPU_SCS_NVIC_ISPR1_SETPEND32_M 0x00000001 -#define CPU_SCS_NVIC_ISPR1_SETPEND32_S 0 +#define CPU_SCS_NVIC_ISPR1_SETPEND32 0x00000001 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_BITN 0 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_M 0x00000001 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_S 0 //***************************************************************************** // @@ -1640,320 +1640,320 @@ // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND31 0x80000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND31_BITN 31 -#define CPU_SCS_NVIC_ICPR0_CLRPEND31_M 0x80000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND31_S 31 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31 0x80000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_BITN 31 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_M 0x80000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_S 31 // Field: [30] CLRPEND30 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND30 0x40000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND30_BITN 30 -#define CPU_SCS_NVIC_ICPR0_CLRPEND30_M 0x40000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND30_S 30 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30 0x40000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_BITN 30 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_M 0x40000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_S 30 // Field: [29] CLRPEND29 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND29 0x20000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND29_BITN 29 -#define CPU_SCS_NVIC_ICPR0_CLRPEND29_M 0x20000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND29_S 29 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29 0x20000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_BITN 29 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_M 0x20000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_S 29 // Field: [28] CLRPEND28 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND28 0x10000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND28_BITN 28 -#define CPU_SCS_NVIC_ICPR0_CLRPEND28_M 0x10000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND28_S 28 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28 0x10000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_BITN 28 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_M 0x10000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_S 28 // Field: [27] CLRPEND27 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND27 0x08000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND27_BITN 27 -#define CPU_SCS_NVIC_ICPR0_CLRPEND27_M 0x08000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND27_S 27 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27 0x08000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_BITN 27 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_M 0x08000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_S 27 // Field: [26] CLRPEND26 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND26 0x04000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND26_BITN 26 -#define CPU_SCS_NVIC_ICPR0_CLRPEND26_M 0x04000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND26_S 26 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26 0x04000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_BITN 26 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_M 0x04000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_S 26 // Field: [25] CLRPEND25 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND25 0x02000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND25_BITN 25 -#define CPU_SCS_NVIC_ICPR0_CLRPEND25_M 0x02000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND25_S 25 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25 0x02000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_BITN 25 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_M 0x02000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_S 25 // Field: [24] CLRPEND24 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND24 0x01000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND24_BITN 24 -#define CPU_SCS_NVIC_ICPR0_CLRPEND24_M 0x01000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND24_S 24 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24 0x01000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_BITN 24 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_M 0x01000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_S 24 // Field: [23] CLRPEND23 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND23 0x00800000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND23_BITN 23 -#define CPU_SCS_NVIC_ICPR0_CLRPEND23_M 0x00800000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND23_S 23 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23 0x00800000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_BITN 23 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_M 0x00800000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_S 23 // Field: [22] CLRPEND22 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND22 0x00400000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND22_BITN 22 -#define CPU_SCS_NVIC_ICPR0_CLRPEND22_M 0x00400000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND22_S 22 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22 0x00400000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_BITN 22 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_M 0x00400000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_S 22 // Field: [21] CLRPEND21 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND21 0x00200000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND21_BITN 21 -#define CPU_SCS_NVIC_ICPR0_CLRPEND21_M 0x00200000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND21_S 21 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21 0x00200000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_BITN 21 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_M 0x00200000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_S 21 // Field: [20] CLRPEND20 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND20 0x00100000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND20_BITN 20 -#define CPU_SCS_NVIC_ICPR0_CLRPEND20_M 0x00100000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND20_S 20 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20 0x00100000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_BITN 20 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_M 0x00100000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_S 20 // Field: [19] CLRPEND19 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND19 0x00080000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND19_BITN 19 -#define CPU_SCS_NVIC_ICPR0_CLRPEND19_M 0x00080000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND19_S 19 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19 0x00080000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_BITN 19 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_M 0x00080000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_S 19 // Field: [18] CLRPEND18 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND18 0x00040000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND18_BITN 18 -#define CPU_SCS_NVIC_ICPR0_CLRPEND18_M 0x00040000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND18_S 18 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18 0x00040000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_BITN 18 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_M 0x00040000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_S 18 // Field: [17] CLRPEND17 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND17 0x00020000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND17_BITN 17 -#define CPU_SCS_NVIC_ICPR0_CLRPEND17_M 0x00020000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND17_S 17 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17 0x00020000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_BITN 17 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_M 0x00020000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_S 17 // Field: [16] CLRPEND16 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND16 0x00010000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND16_BITN 16 -#define CPU_SCS_NVIC_ICPR0_CLRPEND16_M 0x00010000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND16_S 16 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16 0x00010000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_BITN 16 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_M 0x00010000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_S 16 // Field: [15] CLRPEND15 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND15 0x00008000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND15_BITN 15 -#define CPU_SCS_NVIC_ICPR0_CLRPEND15_M 0x00008000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND15_S 15 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15 0x00008000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_BITN 15 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_M 0x00008000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_S 15 // Field: [14] CLRPEND14 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND14 0x00004000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND14_BITN 14 -#define CPU_SCS_NVIC_ICPR0_CLRPEND14_M 0x00004000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND14_S 14 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14 0x00004000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_BITN 14 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_M 0x00004000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_S 14 // Field: [13] CLRPEND13 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND13 0x00002000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND13_BITN 13 -#define CPU_SCS_NVIC_ICPR0_CLRPEND13_M 0x00002000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND13_S 13 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13 0x00002000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_BITN 13 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_M 0x00002000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_S 13 // Field: [12] CLRPEND12 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND12 0x00001000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND12_BITN 12 -#define CPU_SCS_NVIC_ICPR0_CLRPEND12_M 0x00001000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND12_S 12 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12 0x00001000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_BITN 12 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_M 0x00001000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_S 12 // Field: [11] CLRPEND11 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND11 0x00000800 -#define CPU_SCS_NVIC_ICPR0_CLRPEND11_BITN 11 -#define CPU_SCS_NVIC_ICPR0_CLRPEND11_M 0x00000800 -#define CPU_SCS_NVIC_ICPR0_CLRPEND11_S 11 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11 0x00000800 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_BITN 11 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_M 0x00000800 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_S 11 // Field: [10] CLRPEND10 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND10 0x00000400 -#define CPU_SCS_NVIC_ICPR0_CLRPEND10_BITN 10 -#define CPU_SCS_NVIC_ICPR0_CLRPEND10_M 0x00000400 -#define CPU_SCS_NVIC_ICPR0_CLRPEND10_S 10 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10 0x00000400 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_BITN 10 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_M 0x00000400 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_S 10 // Field: [9] CLRPEND9 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND9 0x00000200 -#define CPU_SCS_NVIC_ICPR0_CLRPEND9_BITN 9 -#define CPU_SCS_NVIC_ICPR0_CLRPEND9_M 0x00000200 -#define CPU_SCS_NVIC_ICPR0_CLRPEND9_S 9 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9 0x00000200 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_BITN 9 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_M 0x00000200 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_S 9 // Field: [8] CLRPEND8 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND8 0x00000100 -#define CPU_SCS_NVIC_ICPR0_CLRPEND8_BITN 8 -#define CPU_SCS_NVIC_ICPR0_CLRPEND8_M 0x00000100 -#define CPU_SCS_NVIC_ICPR0_CLRPEND8_S 8 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8 0x00000100 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_BITN 8 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_M 0x00000100 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_S 8 // Field: [7] CLRPEND7 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND7 0x00000080 -#define CPU_SCS_NVIC_ICPR0_CLRPEND7_BITN 7 -#define CPU_SCS_NVIC_ICPR0_CLRPEND7_M 0x00000080 -#define CPU_SCS_NVIC_ICPR0_CLRPEND7_S 7 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7 0x00000080 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_BITN 7 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_M 0x00000080 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_S 7 // Field: [6] CLRPEND6 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND6 0x00000040 -#define CPU_SCS_NVIC_ICPR0_CLRPEND6_BITN 6 -#define CPU_SCS_NVIC_ICPR0_CLRPEND6_M 0x00000040 -#define CPU_SCS_NVIC_ICPR0_CLRPEND6_S 6 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6 0x00000040 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_BITN 6 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_M 0x00000040 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_S 6 // Field: [5] CLRPEND5 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND5 0x00000020 -#define CPU_SCS_NVIC_ICPR0_CLRPEND5_BITN 5 -#define CPU_SCS_NVIC_ICPR0_CLRPEND5_M 0x00000020 -#define CPU_SCS_NVIC_ICPR0_CLRPEND5_S 5 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5 0x00000020 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_BITN 5 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_M 0x00000020 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_S 5 // Field: [4] CLRPEND4 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND4 0x00000010 -#define CPU_SCS_NVIC_ICPR0_CLRPEND4_BITN 4 -#define CPU_SCS_NVIC_ICPR0_CLRPEND4_M 0x00000010 -#define CPU_SCS_NVIC_ICPR0_CLRPEND4_S 4 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4 0x00000010 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_BITN 4 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_M 0x00000010 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_S 4 // Field: [3] CLRPEND3 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND3 0x00000008 -#define CPU_SCS_NVIC_ICPR0_CLRPEND3_BITN 3 -#define CPU_SCS_NVIC_ICPR0_CLRPEND3_M 0x00000008 -#define CPU_SCS_NVIC_ICPR0_CLRPEND3_S 3 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3 0x00000008 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_BITN 3 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_M 0x00000008 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_S 3 // Field: [2] CLRPEND2 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND2 0x00000004 -#define CPU_SCS_NVIC_ICPR0_CLRPEND2_BITN 2 -#define CPU_SCS_NVIC_ICPR0_CLRPEND2_M 0x00000004 -#define CPU_SCS_NVIC_ICPR0_CLRPEND2_S 2 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2 0x00000004 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_BITN 2 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_M 0x00000004 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_S 2 // Field: [1] CLRPEND1 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND1 0x00000002 -#define CPU_SCS_NVIC_ICPR0_CLRPEND1_BITN 1 -#define CPU_SCS_NVIC_ICPR0_CLRPEND1_M 0x00000002 -#define CPU_SCS_NVIC_ICPR0_CLRPEND1_S 1 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1 0x00000002 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_BITN 1 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_M 0x00000002 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_S 1 // Field: [0] CLRPEND0 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND0 0x00000001 -#define CPU_SCS_NVIC_ICPR0_CLRPEND0_BITN 0 -#define CPU_SCS_NVIC_ICPR0_CLRPEND0_M 0x00000001 -#define CPU_SCS_NVIC_ICPR0_CLRPEND0_S 0 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0 0x00000001 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_BITN 0 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_M 0x00000001 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_S 0 //***************************************************************************** // @@ -1965,60 +1965,60 @@ // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 37 (See EVENT:CPUIRQSEL37.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR1_CLRPEND37 0x00000020 -#define CPU_SCS_NVIC_ICPR1_CLRPEND37_BITN 5 -#define CPU_SCS_NVIC_ICPR1_CLRPEND37_M 0x00000020 -#define CPU_SCS_NVIC_ICPR1_CLRPEND37_S 5 +#define CPU_SCS_NVIC_ICPR1_CLRPEND37 0x00000020 +#define CPU_SCS_NVIC_ICPR1_CLRPEND37_BITN 5 +#define CPU_SCS_NVIC_ICPR1_CLRPEND37_M 0x00000020 +#define CPU_SCS_NVIC_ICPR1_CLRPEND37_S 5 // Field: [4] CLRPEND36 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 36 (See EVENT:CPUIRQSEL36.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR1_CLRPEND36 0x00000010 -#define CPU_SCS_NVIC_ICPR1_CLRPEND36_BITN 4 -#define CPU_SCS_NVIC_ICPR1_CLRPEND36_M 0x00000010 -#define CPU_SCS_NVIC_ICPR1_CLRPEND36_S 4 +#define CPU_SCS_NVIC_ICPR1_CLRPEND36 0x00000010 +#define CPU_SCS_NVIC_ICPR1_CLRPEND36_BITN 4 +#define CPU_SCS_NVIC_ICPR1_CLRPEND36_M 0x00000010 +#define CPU_SCS_NVIC_ICPR1_CLRPEND36_S 4 // Field: [3] CLRPEND35 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 35 (See EVENT:CPUIRQSEL35.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR1_CLRPEND35 0x00000008 -#define CPU_SCS_NVIC_ICPR1_CLRPEND35_BITN 3 -#define CPU_SCS_NVIC_ICPR1_CLRPEND35_M 0x00000008 -#define CPU_SCS_NVIC_ICPR1_CLRPEND35_S 3 +#define CPU_SCS_NVIC_ICPR1_CLRPEND35 0x00000008 +#define CPU_SCS_NVIC_ICPR1_CLRPEND35_BITN 3 +#define CPU_SCS_NVIC_ICPR1_CLRPEND35_M 0x00000008 +#define CPU_SCS_NVIC_ICPR1_CLRPEND35_S 3 // Field: [2] CLRPEND34 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 34 (See EVENT:CPUIRQSEL34.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR1_CLRPEND34 0x00000004 -#define CPU_SCS_NVIC_ICPR1_CLRPEND34_BITN 2 -#define CPU_SCS_NVIC_ICPR1_CLRPEND34_M 0x00000004 -#define CPU_SCS_NVIC_ICPR1_CLRPEND34_S 2 +#define CPU_SCS_NVIC_ICPR1_CLRPEND34 0x00000004 +#define CPU_SCS_NVIC_ICPR1_CLRPEND34_BITN 2 +#define CPU_SCS_NVIC_ICPR1_CLRPEND34_M 0x00000004 +#define CPU_SCS_NVIC_ICPR1_CLRPEND34_S 2 // Field: [1] CLRPEND33 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR1_CLRPEND33 0x00000002 -#define CPU_SCS_NVIC_ICPR1_CLRPEND33_BITN 1 -#define CPU_SCS_NVIC_ICPR1_CLRPEND33_M 0x00000002 -#define CPU_SCS_NVIC_ICPR1_CLRPEND33_S 1 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33 0x00000002 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_BITN 1 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_M 0x00000002 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_S 1 // Field: [0] CLRPEND32 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR1_CLRPEND32 0x00000001 -#define CPU_SCS_NVIC_ICPR1_CLRPEND32_BITN 0 -#define CPU_SCS_NVIC_ICPR1_CLRPEND32_M 0x00000001 -#define CPU_SCS_NVIC_ICPR1_CLRPEND32_S 0 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32 0x00000001 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_BITN 0 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_M 0x00000001 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_S 0 //***************************************************************************** // @@ -2030,320 +2030,320 @@ // Reading 0 from this bit implies that interrupt line 31 is not active. // Reading 1 from this bit implies that the interrupt line 31 is active (See // EVENT:CPUIRQSEL31.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE31 0x80000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE31_BITN 31 -#define CPU_SCS_NVIC_IABR0_ACTIVE31_M 0x80000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE31_S 31 +#define CPU_SCS_NVIC_IABR0_ACTIVE31 0x80000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_BITN 31 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_M 0x80000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_S 31 // Field: [30] ACTIVE30 // // Reading 0 from this bit implies that interrupt line 30 is not active. // Reading 1 from this bit implies that the interrupt line 30 is active (See // EVENT:CPUIRQSEL30.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE30 0x40000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE30_BITN 30 -#define CPU_SCS_NVIC_IABR0_ACTIVE30_M 0x40000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE30_S 30 +#define CPU_SCS_NVIC_IABR0_ACTIVE30 0x40000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_BITN 30 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_M 0x40000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_S 30 // Field: [29] ACTIVE29 // // Reading 0 from this bit implies that interrupt line 29 is not active. // Reading 1 from this bit implies that the interrupt line 29 is active (See // EVENT:CPUIRQSEL29.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE29 0x20000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE29_BITN 29 -#define CPU_SCS_NVIC_IABR0_ACTIVE29_M 0x20000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE29_S 29 +#define CPU_SCS_NVIC_IABR0_ACTIVE29 0x20000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_BITN 29 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_M 0x20000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_S 29 // Field: [28] ACTIVE28 // // Reading 0 from this bit implies that interrupt line 28 is not active. // Reading 1 from this bit implies that the interrupt line 28 is active (See // EVENT:CPUIRQSEL28.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE28 0x10000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE28_BITN 28 -#define CPU_SCS_NVIC_IABR0_ACTIVE28_M 0x10000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE28_S 28 +#define CPU_SCS_NVIC_IABR0_ACTIVE28 0x10000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_BITN 28 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_M 0x10000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_S 28 // Field: [27] ACTIVE27 // // Reading 0 from this bit implies that interrupt line 27 is not active. // Reading 1 from this bit implies that the interrupt line 27 is active (See // EVENT:CPUIRQSEL27.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE27 0x08000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE27_BITN 27 -#define CPU_SCS_NVIC_IABR0_ACTIVE27_M 0x08000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE27_S 27 +#define CPU_SCS_NVIC_IABR0_ACTIVE27 0x08000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_BITN 27 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_M 0x08000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_S 27 // Field: [26] ACTIVE26 // // Reading 0 from this bit implies that interrupt line 26 is not active. // Reading 1 from this bit implies that the interrupt line 26 is active (See // EVENT:CPUIRQSEL26.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE26 0x04000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE26_BITN 26 -#define CPU_SCS_NVIC_IABR0_ACTIVE26_M 0x04000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE26_S 26 +#define CPU_SCS_NVIC_IABR0_ACTIVE26 0x04000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_BITN 26 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_M 0x04000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_S 26 // Field: [25] ACTIVE25 // // Reading 0 from this bit implies that interrupt line 25 is not active. // Reading 1 from this bit implies that the interrupt line 25 is active (See // EVENT:CPUIRQSEL25.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE25 0x02000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE25_BITN 25 -#define CPU_SCS_NVIC_IABR0_ACTIVE25_M 0x02000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE25_S 25 +#define CPU_SCS_NVIC_IABR0_ACTIVE25 0x02000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_BITN 25 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_M 0x02000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_S 25 // Field: [24] ACTIVE24 // // Reading 0 from this bit implies that interrupt line 24 is not active. // Reading 1 from this bit implies that the interrupt line 24 is active (See // EVENT:CPUIRQSEL24.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE24 0x01000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE24_BITN 24 -#define CPU_SCS_NVIC_IABR0_ACTIVE24_M 0x01000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE24_S 24 +#define CPU_SCS_NVIC_IABR0_ACTIVE24 0x01000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_BITN 24 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_M 0x01000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_S 24 // Field: [23] ACTIVE23 // // Reading 0 from this bit implies that interrupt line 23 is not active. // Reading 1 from this bit implies that the interrupt line 23 is active (See // EVENT:CPUIRQSEL23.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE23 0x00800000 -#define CPU_SCS_NVIC_IABR0_ACTIVE23_BITN 23 -#define CPU_SCS_NVIC_IABR0_ACTIVE23_M 0x00800000 -#define CPU_SCS_NVIC_IABR0_ACTIVE23_S 23 +#define CPU_SCS_NVIC_IABR0_ACTIVE23 0x00800000 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_BITN 23 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_M 0x00800000 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_S 23 // Field: [22] ACTIVE22 // // Reading 0 from this bit implies that interrupt line 22 is not active. // Reading 1 from this bit implies that the interrupt line 22 is active (See // EVENT:CPUIRQSEL22.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE22 0x00400000 -#define CPU_SCS_NVIC_IABR0_ACTIVE22_BITN 22 -#define CPU_SCS_NVIC_IABR0_ACTIVE22_M 0x00400000 -#define CPU_SCS_NVIC_IABR0_ACTIVE22_S 22 +#define CPU_SCS_NVIC_IABR0_ACTIVE22 0x00400000 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_BITN 22 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_M 0x00400000 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_S 22 // Field: [21] ACTIVE21 // // Reading 0 from this bit implies that interrupt line 21 is not active. // Reading 1 from this bit implies that the interrupt line 21 is active (See // EVENT:CPUIRQSEL21.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE21 0x00200000 -#define CPU_SCS_NVIC_IABR0_ACTIVE21_BITN 21 -#define CPU_SCS_NVIC_IABR0_ACTIVE21_M 0x00200000 -#define CPU_SCS_NVIC_IABR0_ACTIVE21_S 21 +#define CPU_SCS_NVIC_IABR0_ACTIVE21 0x00200000 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_BITN 21 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_M 0x00200000 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_S 21 // Field: [20] ACTIVE20 // // Reading 0 from this bit implies that interrupt line 20 is not active. // Reading 1 from this bit implies that the interrupt line 20 is active (See // EVENT:CPUIRQSEL20.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE20 0x00100000 -#define CPU_SCS_NVIC_IABR0_ACTIVE20_BITN 20 -#define CPU_SCS_NVIC_IABR0_ACTIVE20_M 0x00100000 -#define CPU_SCS_NVIC_IABR0_ACTIVE20_S 20 +#define CPU_SCS_NVIC_IABR0_ACTIVE20 0x00100000 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_BITN 20 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_M 0x00100000 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_S 20 // Field: [19] ACTIVE19 // // Reading 0 from this bit implies that interrupt line 19 is not active. // Reading 1 from this bit implies that the interrupt line 19 is active (See // EVENT:CPUIRQSEL19.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE19 0x00080000 -#define CPU_SCS_NVIC_IABR0_ACTIVE19_BITN 19 -#define CPU_SCS_NVIC_IABR0_ACTIVE19_M 0x00080000 -#define CPU_SCS_NVIC_IABR0_ACTIVE19_S 19 +#define CPU_SCS_NVIC_IABR0_ACTIVE19 0x00080000 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_BITN 19 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_M 0x00080000 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_S 19 // Field: [18] ACTIVE18 // // Reading 0 from this bit implies that interrupt line 18 is not active. // Reading 1 from this bit implies that the interrupt line 18 is active (See // EVENT:CPUIRQSEL18.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE18 0x00040000 -#define CPU_SCS_NVIC_IABR0_ACTIVE18_BITN 18 -#define CPU_SCS_NVIC_IABR0_ACTIVE18_M 0x00040000 -#define CPU_SCS_NVIC_IABR0_ACTIVE18_S 18 +#define CPU_SCS_NVIC_IABR0_ACTIVE18 0x00040000 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_BITN 18 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_M 0x00040000 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_S 18 // Field: [17] ACTIVE17 // // Reading 0 from this bit implies that interrupt line 17 is not active. // Reading 1 from this bit implies that the interrupt line 17 is active (See // EVENT:CPUIRQSEL17.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE17 0x00020000 -#define CPU_SCS_NVIC_IABR0_ACTIVE17_BITN 17 -#define CPU_SCS_NVIC_IABR0_ACTIVE17_M 0x00020000 -#define CPU_SCS_NVIC_IABR0_ACTIVE17_S 17 +#define CPU_SCS_NVIC_IABR0_ACTIVE17 0x00020000 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_BITN 17 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_M 0x00020000 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_S 17 // Field: [16] ACTIVE16 // // Reading 0 from this bit implies that interrupt line 16 is not active. // Reading 1 from this bit implies that the interrupt line 16 is active (See // EVENT:CPUIRQSEL16.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE16 0x00010000 -#define CPU_SCS_NVIC_IABR0_ACTIVE16_BITN 16 -#define CPU_SCS_NVIC_IABR0_ACTIVE16_M 0x00010000 -#define CPU_SCS_NVIC_IABR0_ACTIVE16_S 16 +#define CPU_SCS_NVIC_IABR0_ACTIVE16 0x00010000 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_BITN 16 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_M 0x00010000 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_S 16 // Field: [15] ACTIVE15 // // Reading 0 from this bit implies that interrupt line 15 is not active. // Reading 1 from this bit implies that the interrupt line 15 is active (See // EVENT:CPUIRQSEL15.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE15 0x00008000 -#define CPU_SCS_NVIC_IABR0_ACTIVE15_BITN 15 -#define CPU_SCS_NVIC_IABR0_ACTIVE15_M 0x00008000 -#define CPU_SCS_NVIC_IABR0_ACTIVE15_S 15 +#define CPU_SCS_NVIC_IABR0_ACTIVE15 0x00008000 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_BITN 15 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_M 0x00008000 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_S 15 // Field: [14] ACTIVE14 // // Reading 0 from this bit implies that interrupt line 14 is not active. // Reading 1 from this bit implies that the interrupt line 14 is active (See // EVENT:CPUIRQSEL14.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE14 0x00004000 -#define CPU_SCS_NVIC_IABR0_ACTIVE14_BITN 14 -#define CPU_SCS_NVIC_IABR0_ACTIVE14_M 0x00004000 -#define CPU_SCS_NVIC_IABR0_ACTIVE14_S 14 +#define CPU_SCS_NVIC_IABR0_ACTIVE14 0x00004000 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_BITN 14 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_M 0x00004000 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_S 14 // Field: [13] ACTIVE13 // // Reading 0 from this bit implies that interrupt line 13 is not active. // Reading 1 from this bit implies that the interrupt line 13 is active (See // EVENT:CPUIRQSEL13.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE13 0x00002000 -#define CPU_SCS_NVIC_IABR0_ACTIVE13_BITN 13 -#define CPU_SCS_NVIC_IABR0_ACTIVE13_M 0x00002000 -#define CPU_SCS_NVIC_IABR0_ACTIVE13_S 13 +#define CPU_SCS_NVIC_IABR0_ACTIVE13 0x00002000 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_BITN 13 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_M 0x00002000 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_S 13 // Field: [12] ACTIVE12 // // Reading 0 from this bit implies that interrupt line 12 is not active. // Reading 1 from this bit implies that the interrupt line 12 is active (See // EVENT:CPUIRQSEL12.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE12 0x00001000 -#define CPU_SCS_NVIC_IABR0_ACTIVE12_BITN 12 -#define CPU_SCS_NVIC_IABR0_ACTIVE12_M 0x00001000 -#define CPU_SCS_NVIC_IABR0_ACTIVE12_S 12 +#define CPU_SCS_NVIC_IABR0_ACTIVE12 0x00001000 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_BITN 12 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_M 0x00001000 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_S 12 // Field: [11] ACTIVE11 // // Reading 0 from this bit implies that interrupt line 11 is not active. // Reading 1 from this bit implies that the interrupt line 11 is active (See // EVENT:CPUIRQSEL11.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE11 0x00000800 -#define CPU_SCS_NVIC_IABR0_ACTIVE11_BITN 11 -#define CPU_SCS_NVIC_IABR0_ACTIVE11_M 0x00000800 -#define CPU_SCS_NVIC_IABR0_ACTIVE11_S 11 +#define CPU_SCS_NVIC_IABR0_ACTIVE11 0x00000800 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_BITN 11 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_M 0x00000800 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_S 11 // Field: [10] ACTIVE10 // // Reading 0 from this bit implies that interrupt line 10 is not active. // Reading 1 from this bit implies that the interrupt line 10 is active (See // EVENT:CPUIRQSEL10.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE10 0x00000400 -#define CPU_SCS_NVIC_IABR0_ACTIVE10_BITN 10 -#define CPU_SCS_NVIC_IABR0_ACTIVE10_M 0x00000400 -#define CPU_SCS_NVIC_IABR0_ACTIVE10_S 10 +#define CPU_SCS_NVIC_IABR0_ACTIVE10 0x00000400 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_BITN 10 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_M 0x00000400 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_S 10 // Field: [9] ACTIVE9 // // Reading 0 from this bit implies that interrupt line 9 is not active. Reading // 1 from this bit implies that the interrupt line 9 is active (See // EVENT:CPUIRQSEL9.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE9 0x00000200 -#define CPU_SCS_NVIC_IABR0_ACTIVE9_BITN 9 -#define CPU_SCS_NVIC_IABR0_ACTIVE9_M 0x00000200 -#define CPU_SCS_NVIC_IABR0_ACTIVE9_S 9 +#define CPU_SCS_NVIC_IABR0_ACTIVE9 0x00000200 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_BITN 9 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_M 0x00000200 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_S 9 // Field: [8] ACTIVE8 // // Reading 0 from this bit implies that interrupt line 8 is not active. Reading // 1 from this bit implies that the interrupt line 8 is active (See // EVENT:CPUIRQSEL8.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE8 0x00000100 -#define CPU_SCS_NVIC_IABR0_ACTIVE8_BITN 8 -#define CPU_SCS_NVIC_IABR0_ACTIVE8_M 0x00000100 -#define CPU_SCS_NVIC_IABR0_ACTIVE8_S 8 +#define CPU_SCS_NVIC_IABR0_ACTIVE8 0x00000100 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_BITN 8 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_M 0x00000100 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_S 8 // Field: [7] ACTIVE7 // // Reading 0 from this bit implies that interrupt line 7 is not active. Reading // 1 from this bit implies that the interrupt line 7 is active (See // EVENT:CPUIRQSEL7.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE7 0x00000080 -#define CPU_SCS_NVIC_IABR0_ACTIVE7_BITN 7 -#define CPU_SCS_NVIC_IABR0_ACTIVE7_M 0x00000080 -#define CPU_SCS_NVIC_IABR0_ACTIVE7_S 7 +#define CPU_SCS_NVIC_IABR0_ACTIVE7 0x00000080 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_BITN 7 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_M 0x00000080 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_S 7 // Field: [6] ACTIVE6 // // Reading 0 from this bit implies that interrupt line 6 is not active. Reading // 1 from this bit implies that the interrupt line 6 is active (See // EVENT:CPUIRQSEL6.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE6 0x00000040 -#define CPU_SCS_NVIC_IABR0_ACTIVE6_BITN 6 -#define CPU_SCS_NVIC_IABR0_ACTIVE6_M 0x00000040 -#define CPU_SCS_NVIC_IABR0_ACTIVE6_S 6 +#define CPU_SCS_NVIC_IABR0_ACTIVE6 0x00000040 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_BITN 6 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_M 0x00000040 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_S 6 // Field: [5] ACTIVE5 // // Reading 0 from this bit implies that interrupt line 5 is not active. Reading // 1 from this bit implies that the interrupt line 5 is active (See // EVENT:CPUIRQSEL5.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE5 0x00000020 -#define CPU_SCS_NVIC_IABR0_ACTIVE5_BITN 5 -#define CPU_SCS_NVIC_IABR0_ACTIVE5_M 0x00000020 -#define CPU_SCS_NVIC_IABR0_ACTIVE5_S 5 +#define CPU_SCS_NVIC_IABR0_ACTIVE5 0x00000020 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_BITN 5 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_M 0x00000020 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_S 5 // Field: [4] ACTIVE4 // // Reading 0 from this bit implies that interrupt line 4 is not active. Reading // 1 from this bit implies that the interrupt line 4 is active (See // EVENT:CPUIRQSEL4.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE4 0x00000010 -#define CPU_SCS_NVIC_IABR0_ACTIVE4_BITN 4 -#define CPU_SCS_NVIC_IABR0_ACTIVE4_M 0x00000010 -#define CPU_SCS_NVIC_IABR0_ACTIVE4_S 4 +#define CPU_SCS_NVIC_IABR0_ACTIVE4 0x00000010 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_BITN 4 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_M 0x00000010 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_S 4 // Field: [3] ACTIVE3 // // Reading 0 from this bit implies that interrupt line 3 is not active. Reading // 1 from this bit implies that the interrupt line 3 is active (See // EVENT:CPUIRQSEL3.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE3 0x00000008 -#define CPU_SCS_NVIC_IABR0_ACTIVE3_BITN 3 -#define CPU_SCS_NVIC_IABR0_ACTIVE3_M 0x00000008 -#define CPU_SCS_NVIC_IABR0_ACTIVE3_S 3 +#define CPU_SCS_NVIC_IABR0_ACTIVE3 0x00000008 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_BITN 3 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_M 0x00000008 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_S 3 // Field: [2] ACTIVE2 // // Reading 0 from this bit implies that interrupt line 2 is not active. Reading // 1 from this bit implies that the interrupt line 2 is active (See // EVENT:CPUIRQSEL2.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE2 0x00000004 -#define CPU_SCS_NVIC_IABR0_ACTIVE2_BITN 2 -#define CPU_SCS_NVIC_IABR0_ACTIVE2_M 0x00000004 -#define CPU_SCS_NVIC_IABR0_ACTIVE2_S 2 +#define CPU_SCS_NVIC_IABR0_ACTIVE2 0x00000004 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_BITN 2 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_M 0x00000004 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_S 2 // Field: [1] ACTIVE1 // // Reading 0 from this bit implies that interrupt line 1 is not active. Reading // 1 from this bit implies that the interrupt line 1 is active (See // EVENT:CPUIRQSEL1.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE1 0x00000002 -#define CPU_SCS_NVIC_IABR0_ACTIVE1_BITN 1 -#define CPU_SCS_NVIC_IABR0_ACTIVE1_M 0x00000002 -#define CPU_SCS_NVIC_IABR0_ACTIVE1_S 1 +#define CPU_SCS_NVIC_IABR0_ACTIVE1 0x00000002 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_BITN 1 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_M 0x00000002 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_S 1 // Field: [0] ACTIVE0 // // Reading 0 from this bit implies that interrupt line 0 is not active. Reading // 1 from this bit implies that the interrupt line 0 is active (See // EVENT:CPUIRQSEL0.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE0 0x00000001 -#define CPU_SCS_NVIC_IABR0_ACTIVE0_BITN 0 -#define CPU_SCS_NVIC_IABR0_ACTIVE0_M 0x00000001 -#define CPU_SCS_NVIC_IABR0_ACTIVE0_S 0 +#define CPU_SCS_NVIC_IABR0_ACTIVE0 0x00000001 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_BITN 0 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_M 0x00000001 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_S 0 //***************************************************************************** // @@ -2355,60 +2355,60 @@ // Reading 0 from this bit implies that interrupt line 37 is not active. // Reading 1 from this bit implies that the interrupt line 37 is active (See // EVENT:CPUIRQSEL37.EV for details). -#define CPU_SCS_NVIC_IABR1_ACTIVE37 0x00000020 -#define CPU_SCS_NVIC_IABR1_ACTIVE37_BITN 5 -#define CPU_SCS_NVIC_IABR1_ACTIVE37_M 0x00000020 -#define CPU_SCS_NVIC_IABR1_ACTIVE37_S 5 +#define CPU_SCS_NVIC_IABR1_ACTIVE37 0x00000020 +#define CPU_SCS_NVIC_IABR1_ACTIVE37_BITN 5 +#define CPU_SCS_NVIC_IABR1_ACTIVE37_M 0x00000020 +#define CPU_SCS_NVIC_IABR1_ACTIVE37_S 5 // Field: [4] ACTIVE36 // // Reading 0 from this bit implies that interrupt line 36 is not active. // Reading 1 from this bit implies that the interrupt line 36 is active (See // EVENT:CPUIRQSEL36.EV for details). -#define CPU_SCS_NVIC_IABR1_ACTIVE36 0x00000010 -#define CPU_SCS_NVIC_IABR1_ACTIVE36_BITN 4 -#define CPU_SCS_NVIC_IABR1_ACTIVE36_M 0x00000010 -#define CPU_SCS_NVIC_IABR1_ACTIVE36_S 4 +#define CPU_SCS_NVIC_IABR1_ACTIVE36 0x00000010 +#define CPU_SCS_NVIC_IABR1_ACTIVE36_BITN 4 +#define CPU_SCS_NVIC_IABR1_ACTIVE36_M 0x00000010 +#define CPU_SCS_NVIC_IABR1_ACTIVE36_S 4 // Field: [3] ACTIVE35 // // Reading 0 from this bit implies that interrupt line 35 is not active. // Reading 1 from this bit implies that the interrupt line 35 is active (See // EVENT:CPUIRQSEL35.EV for details). -#define CPU_SCS_NVIC_IABR1_ACTIVE35 0x00000008 -#define CPU_SCS_NVIC_IABR1_ACTIVE35_BITN 3 -#define CPU_SCS_NVIC_IABR1_ACTIVE35_M 0x00000008 -#define CPU_SCS_NVIC_IABR1_ACTIVE35_S 3 +#define CPU_SCS_NVIC_IABR1_ACTIVE35 0x00000008 +#define CPU_SCS_NVIC_IABR1_ACTIVE35_BITN 3 +#define CPU_SCS_NVIC_IABR1_ACTIVE35_M 0x00000008 +#define CPU_SCS_NVIC_IABR1_ACTIVE35_S 3 // Field: [2] ACTIVE34 // // Reading 0 from this bit implies that interrupt line 34 is not active. // Reading 1 from this bit implies that the interrupt line 34 is active (See // EVENT:CPUIRQSEL34.EV for details). -#define CPU_SCS_NVIC_IABR1_ACTIVE34 0x00000004 -#define CPU_SCS_NVIC_IABR1_ACTIVE34_BITN 2 -#define CPU_SCS_NVIC_IABR1_ACTIVE34_M 0x00000004 -#define CPU_SCS_NVIC_IABR1_ACTIVE34_S 2 +#define CPU_SCS_NVIC_IABR1_ACTIVE34 0x00000004 +#define CPU_SCS_NVIC_IABR1_ACTIVE34_BITN 2 +#define CPU_SCS_NVIC_IABR1_ACTIVE34_M 0x00000004 +#define CPU_SCS_NVIC_IABR1_ACTIVE34_S 2 // Field: [1] ACTIVE33 // // Reading 0 from this bit implies that interrupt line 33 is not active. // Reading 1 from this bit implies that the interrupt line 33 is active (See // EVENT:CPUIRQSEL33.EV for details). -#define CPU_SCS_NVIC_IABR1_ACTIVE33 0x00000002 -#define CPU_SCS_NVIC_IABR1_ACTIVE33_BITN 1 -#define CPU_SCS_NVIC_IABR1_ACTIVE33_M 0x00000002 -#define CPU_SCS_NVIC_IABR1_ACTIVE33_S 1 +#define CPU_SCS_NVIC_IABR1_ACTIVE33 0x00000002 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_BITN 1 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_M 0x00000002 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_S 1 // Field: [0] ACTIVE32 // // Reading 0 from this bit implies that interrupt line 32 is not active. // Reading 1 from this bit implies that the interrupt line 32 is active (See // EVENT:CPUIRQSEL32.EV for details). -#define CPU_SCS_NVIC_IABR1_ACTIVE32 0x00000001 -#define CPU_SCS_NVIC_IABR1_ACTIVE32_BITN 0 -#define CPU_SCS_NVIC_IABR1_ACTIVE32_M 0x00000001 -#define CPU_SCS_NVIC_IABR1_ACTIVE32_S 0 +#define CPU_SCS_NVIC_IABR1_ACTIVE32 0x00000001 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_BITN 0 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_M 0x00000001 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_S 0 //***************************************************************************** // @@ -2418,30 +2418,30 @@ // Field: [31:24] PRI_3 // // Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). -#define CPU_SCS_NVIC_IPR0_PRI_3_W 8 -#define CPU_SCS_NVIC_IPR0_PRI_3_M 0xFF000000 -#define CPU_SCS_NVIC_IPR0_PRI_3_S 24 +#define CPU_SCS_NVIC_IPR0_PRI_3_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_3_M 0xFF000000 +#define CPU_SCS_NVIC_IPR0_PRI_3_S 24 // Field: [23:16] PRI_2 // // Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). -#define CPU_SCS_NVIC_IPR0_PRI_2_W 8 -#define CPU_SCS_NVIC_IPR0_PRI_2_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR0_PRI_2_S 16 +#define CPU_SCS_NVIC_IPR0_PRI_2_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_2_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR0_PRI_2_S 16 // Field: [15:8] PRI_1 // // Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). -#define CPU_SCS_NVIC_IPR0_PRI_1_W 8 -#define CPU_SCS_NVIC_IPR0_PRI_1_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR0_PRI_1_S 8 +#define CPU_SCS_NVIC_IPR0_PRI_1_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_1_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR0_PRI_1_S 8 // Field: [7:0] PRI_0 // // Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). -#define CPU_SCS_NVIC_IPR0_PRI_0_W 8 -#define CPU_SCS_NVIC_IPR0_PRI_0_M 0x000000FF -#define CPU_SCS_NVIC_IPR0_PRI_0_S 0 +#define CPU_SCS_NVIC_IPR0_PRI_0_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_0_M 0x000000FF +#define CPU_SCS_NVIC_IPR0_PRI_0_S 0 //***************************************************************************** // @@ -2451,30 +2451,30 @@ // Field: [31:24] PRI_7 // // Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). -#define CPU_SCS_NVIC_IPR1_PRI_7_W 8 -#define CPU_SCS_NVIC_IPR1_PRI_7_M 0xFF000000 -#define CPU_SCS_NVIC_IPR1_PRI_7_S 24 +#define CPU_SCS_NVIC_IPR1_PRI_7_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_7_M 0xFF000000 +#define CPU_SCS_NVIC_IPR1_PRI_7_S 24 // Field: [23:16] PRI_6 // // Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). -#define CPU_SCS_NVIC_IPR1_PRI_6_W 8 -#define CPU_SCS_NVIC_IPR1_PRI_6_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR1_PRI_6_S 16 +#define CPU_SCS_NVIC_IPR1_PRI_6_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_6_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR1_PRI_6_S 16 // Field: [15:8] PRI_5 // // Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). -#define CPU_SCS_NVIC_IPR1_PRI_5_W 8 -#define CPU_SCS_NVIC_IPR1_PRI_5_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR1_PRI_5_S 8 +#define CPU_SCS_NVIC_IPR1_PRI_5_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_5_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR1_PRI_5_S 8 // Field: [7:0] PRI_4 // // Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). -#define CPU_SCS_NVIC_IPR1_PRI_4_W 8 -#define CPU_SCS_NVIC_IPR1_PRI_4_M 0x000000FF -#define CPU_SCS_NVIC_IPR1_PRI_4_S 0 +#define CPU_SCS_NVIC_IPR1_PRI_4_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_4_M 0x000000FF +#define CPU_SCS_NVIC_IPR1_PRI_4_S 0 //***************************************************************************** // @@ -2484,30 +2484,30 @@ // Field: [31:24] PRI_11 // // Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). -#define CPU_SCS_NVIC_IPR2_PRI_11_W 8 -#define CPU_SCS_NVIC_IPR2_PRI_11_M 0xFF000000 -#define CPU_SCS_NVIC_IPR2_PRI_11_S 24 +#define CPU_SCS_NVIC_IPR2_PRI_11_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_11_M 0xFF000000 +#define CPU_SCS_NVIC_IPR2_PRI_11_S 24 // Field: [23:16] PRI_10 // // Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). -#define CPU_SCS_NVIC_IPR2_PRI_10_W 8 -#define CPU_SCS_NVIC_IPR2_PRI_10_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR2_PRI_10_S 16 +#define CPU_SCS_NVIC_IPR2_PRI_10_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_10_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR2_PRI_10_S 16 // Field: [15:8] PRI_9 // // Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). -#define CPU_SCS_NVIC_IPR2_PRI_9_W 8 -#define CPU_SCS_NVIC_IPR2_PRI_9_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR2_PRI_9_S 8 +#define CPU_SCS_NVIC_IPR2_PRI_9_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_9_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR2_PRI_9_S 8 // Field: [7:0] PRI_8 // // Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). -#define CPU_SCS_NVIC_IPR2_PRI_8_W 8 -#define CPU_SCS_NVIC_IPR2_PRI_8_M 0x000000FF -#define CPU_SCS_NVIC_IPR2_PRI_8_S 0 +#define CPU_SCS_NVIC_IPR2_PRI_8_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_8_M 0x000000FF +#define CPU_SCS_NVIC_IPR2_PRI_8_S 0 //***************************************************************************** // @@ -2517,30 +2517,30 @@ // Field: [31:24] PRI_15 // // Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). -#define CPU_SCS_NVIC_IPR3_PRI_15_W 8 -#define CPU_SCS_NVIC_IPR3_PRI_15_M 0xFF000000 -#define CPU_SCS_NVIC_IPR3_PRI_15_S 24 +#define CPU_SCS_NVIC_IPR3_PRI_15_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_15_M 0xFF000000 +#define CPU_SCS_NVIC_IPR3_PRI_15_S 24 // Field: [23:16] PRI_14 // // Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). -#define CPU_SCS_NVIC_IPR3_PRI_14_W 8 -#define CPU_SCS_NVIC_IPR3_PRI_14_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR3_PRI_14_S 16 +#define CPU_SCS_NVIC_IPR3_PRI_14_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_14_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR3_PRI_14_S 16 // Field: [15:8] PRI_13 // // Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). -#define CPU_SCS_NVIC_IPR3_PRI_13_W 8 -#define CPU_SCS_NVIC_IPR3_PRI_13_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR3_PRI_13_S 8 +#define CPU_SCS_NVIC_IPR3_PRI_13_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_13_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR3_PRI_13_S 8 // Field: [7:0] PRI_12 // // Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). -#define CPU_SCS_NVIC_IPR3_PRI_12_W 8 -#define CPU_SCS_NVIC_IPR3_PRI_12_M 0x000000FF -#define CPU_SCS_NVIC_IPR3_PRI_12_S 0 +#define CPU_SCS_NVIC_IPR3_PRI_12_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_12_M 0x000000FF +#define CPU_SCS_NVIC_IPR3_PRI_12_S 0 //***************************************************************************** // @@ -2550,30 +2550,30 @@ // Field: [31:24] PRI_19 // // Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). -#define CPU_SCS_NVIC_IPR4_PRI_19_W 8 -#define CPU_SCS_NVIC_IPR4_PRI_19_M 0xFF000000 -#define CPU_SCS_NVIC_IPR4_PRI_19_S 24 +#define CPU_SCS_NVIC_IPR4_PRI_19_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_19_M 0xFF000000 +#define CPU_SCS_NVIC_IPR4_PRI_19_S 24 // Field: [23:16] PRI_18 // // Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). -#define CPU_SCS_NVIC_IPR4_PRI_18_W 8 -#define CPU_SCS_NVIC_IPR4_PRI_18_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR4_PRI_18_S 16 +#define CPU_SCS_NVIC_IPR4_PRI_18_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_18_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR4_PRI_18_S 16 // Field: [15:8] PRI_17 // // Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). -#define CPU_SCS_NVIC_IPR4_PRI_17_W 8 -#define CPU_SCS_NVIC_IPR4_PRI_17_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR4_PRI_17_S 8 +#define CPU_SCS_NVIC_IPR4_PRI_17_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_17_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR4_PRI_17_S 8 // Field: [7:0] PRI_16 // // Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). -#define CPU_SCS_NVIC_IPR4_PRI_16_W 8 -#define CPU_SCS_NVIC_IPR4_PRI_16_M 0x000000FF -#define CPU_SCS_NVIC_IPR4_PRI_16_S 0 +#define CPU_SCS_NVIC_IPR4_PRI_16_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_16_M 0x000000FF +#define CPU_SCS_NVIC_IPR4_PRI_16_S 0 //***************************************************************************** // @@ -2583,30 +2583,30 @@ // Field: [31:24] PRI_23 // // Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). -#define CPU_SCS_NVIC_IPR5_PRI_23_W 8 -#define CPU_SCS_NVIC_IPR5_PRI_23_M 0xFF000000 -#define CPU_SCS_NVIC_IPR5_PRI_23_S 24 +#define CPU_SCS_NVIC_IPR5_PRI_23_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_23_M 0xFF000000 +#define CPU_SCS_NVIC_IPR5_PRI_23_S 24 // Field: [23:16] PRI_22 // // Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). -#define CPU_SCS_NVIC_IPR5_PRI_22_W 8 -#define CPU_SCS_NVIC_IPR5_PRI_22_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR5_PRI_22_S 16 +#define CPU_SCS_NVIC_IPR5_PRI_22_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_22_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR5_PRI_22_S 16 // Field: [15:8] PRI_21 // // Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). -#define CPU_SCS_NVIC_IPR5_PRI_21_W 8 -#define CPU_SCS_NVIC_IPR5_PRI_21_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR5_PRI_21_S 8 +#define CPU_SCS_NVIC_IPR5_PRI_21_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_21_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR5_PRI_21_S 8 // Field: [7:0] PRI_20 // // Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). -#define CPU_SCS_NVIC_IPR5_PRI_20_W 8 -#define CPU_SCS_NVIC_IPR5_PRI_20_M 0x000000FF -#define CPU_SCS_NVIC_IPR5_PRI_20_S 0 +#define CPU_SCS_NVIC_IPR5_PRI_20_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_20_M 0x000000FF +#define CPU_SCS_NVIC_IPR5_PRI_20_S 0 //***************************************************************************** // @@ -2616,30 +2616,30 @@ // Field: [31:24] PRI_27 // // Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). -#define CPU_SCS_NVIC_IPR6_PRI_27_W 8 -#define CPU_SCS_NVIC_IPR6_PRI_27_M 0xFF000000 -#define CPU_SCS_NVIC_IPR6_PRI_27_S 24 +#define CPU_SCS_NVIC_IPR6_PRI_27_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_27_M 0xFF000000 +#define CPU_SCS_NVIC_IPR6_PRI_27_S 24 // Field: [23:16] PRI_26 // // Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). -#define CPU_SCS_NVIC_IPR6_PRI_26_W 8 -#define CPU_SCS_NVIC_IPR6_PRI_26_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR6_PRI_26_S 16 +#define CPU_SCS_NVIC_IPR6_PRI_26_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_26_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR6_PRI_26_S 16 // Field: [15:8] PRI_25 // // Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). -#define CPU_SCS_NVIC_IPR6_PRI_25_W 8 -#define CPU_SCS_NVIC_IPR6_PRI_25_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR6_PRI_25_S 8 +#define CPU_SCS_NVIC_IPR6_PRI_25_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_25_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR6_PRI_25_S 8 // Field: [7:0] PRI_24 // // Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). -#define CPU_SCS_NVIC_IPR6_PRI_24_W 8 -#define CPU_SCS_NVIC_IPR6_PRI_24_M 0x000000FF -#define CPU_SCS_NVIC_IPR6_PRI_24_S 0 +#define CPU_SCS_NVIC_IPR6_PRI_24_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_24_M 0x000000FF +#define CPU_SCS_NVIC_IPR6_PRI_24_S 0 //***************************************************************************** // @@ -2649,30 +2649,30 @@ // Field: [31:24] PRI_31 // // Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). -#define CPU_SCS_NVIC_IPR7_PRI_31_W 8 -#define CPU_SCS_NVIC_IPR7_PRI_31_M 0xFF000000 -#define CPU_SCS_NVIC_IPR7_PRI_31_S 24 +#define CPU_SCS_NVIC_IPR7_PRI_31_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_31_M 0xFF000000 +#define CPU_SCS_NVIC_IPR7_PRI_31_S 24 // Field: [23:16] PRI_30 // // Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). -#define CPU_SCS_NVIC_IPR7_PRI_30_W 8 -#define CPU_SCS_NVIC_IPR7_PRI_30_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR7_PRI_30_S 16 +#define CPU_SCS_NVIC_IPR7_PRI_30_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_30_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR7_PRI_30_S 16 // Field: [15:8] PRI_29 // // Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). -#define CPU_SCS_NVIC_IPR7_PRI_29_W 8 -#define CPU_SCS_NVIC_IPR7_PRI_29_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR7_PRI_29_S 8 +#define CPU_SCS_NVIC_IPR7_PRI_29_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_29_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR7_PRI_29_S 8 // Field: [7:0] PRI_28 // // Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). -#define CPU_SCS_NVIC_IPR7_PRI_28_W 8 -#define CPU_SCS_NVIC_IPR7_PRI_28_M 0x000000FF -#define CPU_SCS_NVIC_IPR7_PRI_28_S 0 +#define CPU_SCS_NVIC_IPR7_PRI_28_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_28_M 0x000000FF +#define CPU_SCS_NVIC_IPR7_PRI_28_S 0 //***************************************************************************** // @@ -2682,30 +2682,30 @@ // Field: [31:24] PRI_35 // // Priority of interrupt 35 (See EVENT:CPUIRQSEL35.EV for details). -#define CPU_SCS_NVIC_IPR8_PRI_35_W 8 -#define CPU_SCS_NVIC_IPR8_PRI_35_M 0xFF000000 -#define CPU_SCS_NVIC_IPR8_PRI_35_S 24 +#define CPU_SCS_NVIC_IPR8_PRI_35_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_35_M 0xFF000000 +#define CPU_SCS_NVIC_IPR8_PRI_35_S 24 // Field: [23:16] PRI_34 // // Priority of interrupt 34 (See EVENT:CPUIRQSEL34.EV for details). -#define CPU_SCS_NVIC_IPR8_PRI_34_W 8 -#define CPU_SCS_NVIC_IPR8_PRI_34_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR8_PRI_34_S 16 +#define CPU_SCS_NVIC_IPR8_PRI_34_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_34_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR8_PRI_34_S 16 // Field: [15:8] PRI_33 // // Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). -#define CPU_SCS_NVIC_IPR8_PRI_33_W 8 -#define CPU_SCS_NVIC_IPR8_PRI_33_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR8_PRI_33_S 8 +#define CPU_SCS_NVIC_IPR8_PRI_33_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_33_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR8_PRI_33_S 8 // Field: [7:0] PRI_32 // // Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). -#define CPU_SCS_NVIC_IPR8_PRI_32_W 8 -#define CPU_SCS_NVIC_IPR8_PRI_32_M 0x000000FF -#define CPU_SCS_NVIC_IPR8_PRI_32_S 0 +#define CPU_SCS_NVIC_IPR8_PRI_32_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_32_M 0x000000FF +#define CPU_SCS_NVIC_IPR8_PRI_32_S 0 //***************************************************************************** // @@ -2715,16 +2715,16 @@ // Field: [15:8] PRI_37 // // Priority of interrupt 37 (See EVENT:CPUIRQSEL37.EV for details). -#define CPU_SCS_NVIC_IPR9_PRI_37_W 8 -#define CPU_SCS_NVIC_IPR9_PRI_37_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR9_PRI_37_S 8 +#define CPU_SCS_NVIC_IPR9_PRI_37_W 8 +#define CPU_SCS_NVIC_IPR9_PRI_37_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR9_PRI_37_S 8 // Field: [7:0] PRI_36 // // Priority of interrupt 36 (See EVENT:CPUIRQSEL36.EV for details). -#define CPU_SCS_NVIC_IPR9_PRI_36_W 8 -#define CPU_SCS_NVIC_IPR9_PRI_36_M 0x000000FF -#define CPU_SCS_NVIC_IPR9_PRI_36_S 0 +#define CPU_SCS_NVIC_IPR9_PRI_36_W 8 +#define CPU_SCS_NVIC_IPR9_PRI_36_M 0x000000FF +#define CPU_SCS_NVIC_IPR9_PRI_36_S 0 //***************************************************************************** // @@ -2734,37 +2734,37 @@ // Field: [31:24] IMPLEMENTER // // Implementor code. -#define CPU_SCS_CPUID_IMPLEMENTER_W 8 -#define CPU_SCS_CPUID_IMPLEMENTER_M 0xFF000000 -#define CPU_SCS_CPUID_IMPLEMENTER_S 24 +#define CPU_SCS_CPUID_IMPLEMENTER_W 8 +#define CPU_SCS_CPUID_IMPLEMENTER_M 0xFF000000 +#define CPU_SCS_CPUID_IMPLEMENTER_S 24 // Field: [23:20] VARIANT // // Implementation defined variant number. -#define CPU_SCS_CPUID_VARIANT_W 4 -#define CPU_SCS_CPUID_VARIANT_M 0x00F00000 -#define CPU_SCS_CPUID_VARIANT_S 20 +#define CPU_SCS_CPUID_VARIANT_W 4 +#define CPU_SCS_CPUID_VARIANT_M 0x00F00000 +#define CPU_SCS_CPUID_VARIANT_S 20 // Field: [19:16] CONSTANT // // Reads as 0xF -#define CPU_SCS_CPUID_CONSTANT_W 4 -#define CPU_SCS_CPUID_CONSTANT_M 0x000F0000 -#define CPU_SCS_CPUID_CONSTANT_S 16 +#define CPU_SCS_CPUID_CONSTANT_W 4 +#define CPU_SCS_CPUID_CONSTANT_M 0x000F0000 +#define CPU_SCS_CPUID_CONSTANT_S 16 // Field: [15:4] PARTNO // // Number of processor within family. -#define CPU_SCS_CPUID_PARTNO_W 12 -#define CPU_SCS_CPUID_PARTNO_M 0x0000FFF0 -#define CPU_SCS_CPUID_PARTNO_S 4 +#define CPU_SCS_CPUID_PARTNO_W 12 +#define CPU_SCS_CPUID_PARTNO_M 0x0000FFF0 +#define CPU_SCS_CPUID_PARTNO_S 4 // Field: [3:0] REVISION // // Implementation defined revision number. -#define CPU_SCS_CPUID_REVISION_W 4 -#define CPU_SCS_CPUID_REVISION_M 0x0000000F -#define CPU_SCS_CPUID_REVISION_S 0 +#define CPU_SCS_CPUID_REVISION_W 4 +#define CPU_SCS_CPUID_REVISION_M 0x0000000F +#define CPU_SCS_CPUID_REVISION_S 0 //***************************************************************************** // @@ -2779,10 +2779,10 @@ // // 0: No action // 1: Set pending NMI -#define CPU_SCS_ICSR_NMIPENDSET 0x80000000 -#define CPU_SCS_ICSR_NMIPENDSET_BITN 31 -#define CPU_SCS_ICSR_NMIPENDSET_M 0x80000000 -#define CPU_SCS_ICSR_NMIPENDSET_S 31 +#define CPU_SCS_ICSR_NMIPENDSET 0x80000000 +#define CPU_SCS_ICSR_NMIPENDSET_BITN 31 +#define CPU_SCS_ICSR_NMIPENDSET_M 0x80000000 +#define CPU_SCS_ICSR_NMIPENDSET_S 31 // Field: [28] PENDSVSET // @@ -2790,10 +2790,10 @@ // // 0: No action // 1: Set pending PendSV -#define CPU_SCS_ICSR_PENDSVSET 0x10000000 -#define CPU_SCS_ICSR_PENDSVSET_BITN 28 -#define CPU_SCS_ICSR_PENDSVSET_M 0x10000000 -#define CPU_SCS_ICSR_PENDSVSET_S 28 +#define CPU_SCS_ICSR_PENDSVSET 0x10000000 +#define CPU_SCS_ICSR_PENDSVSET_BITN 28 +#define CPU_SCS_ICSR_PENDSVSET_M 0x10000000 +#define CPU_SCS_ICSR_PENDSVSET_S 28 // Field: [27] PENDSVCLR // @@ -2801,10 +2801,10 @@ // // 0: No action // 1: Clear pending pendSV -#define CPU_SCS_ICSR_PENDSVCLR 0x08000000 -#define CPU_SCS_ICSR_PENDSVCLR_BITN 27 -#define CPU_SCS_ICSR_PENDSVCLR_M 0x08000000 -#define CPU_SCS_ICSR_PENDSVCLR_S 27 +#define CPU_SCS_ICSR_PENDSVCLR 0x08000000 +#define CPU_SCS_ICSR_PENDSVCLR_BITN 27 +#define CPU_SCS_ICSR_PENDSVCLR_M 0x08000000 +#define CPU_SCS_ICSR_PENDSVCLR_S 27 // Field: [26] PENDSTSET // @@ -2812,10 +2812,10 @@ // // 0: No action // 1: Set pending SysTick -#define CPU_SCS_ICSR_PENDSTSET 0x04000000 -#define CPU_SCS_ICSR_PENDSTSET_BITN 26 -#define CPU_SCS_ICSR_PENDSTSET_M 0x04000000 -#define CPU_SCS_ICSR_PENDSTSET_S 26 +#define CPU_SCS_ICSR_PENDSTSET 0x04000000 +#define CPU_SCS_ICSR_PENDSTSET_BITN 26 +#define CPU_SCS_ICSR_PENDSTSET_M 0x04000000 +#define CPU_SCS_ICSR_PENDSTSET_S 26 // Field: [25] PENDSTCLR // @@ -2823,10 +2823,10 @@ // // 0: No action // 1: Clear pending SysTick -#define CPU_SCS_ICSR_PENDSTCLR 0x02000000 -#define CPU_SCS_ICSR_PENDSTCLR_BITN 25 -#define CPU_SCS_ICSR_PENDSTCLR_M 0x02000000 -#define CPU_SCS_ICSR_PENDSTCLR_S 25 +#define CPU_SCS_ICSR_PENDSTCLR 0x02000000 +#define CPU_SCS_ICSR_PENDSTCLR_BITN 25 +#define CPU_SCS_ICSR_PENDSTCLR_M 0x02000000 +#define CPU_SCS_ICSR_PENDSTCLR_S 25 // Field: [23] ISRPREEMPT // @@ -2836,10 +2836,10 @@ // // 0: A pending exception is not serviced. // 1: A pending exception is serviced on exit from the debug halt state -#define CPU_SCS_ICSR_ISRPREEMPT 0x00800000 -#define CPU_SCS_ICSR_ISRPREEMPT_BITN 23 -#define CPU_SCS_ICSR_ISRPREEMPT_M 0x00800000 -#define CPU_SCS_ICSR_ISRPREEMPT_S 23 +#define CPU_SCS_ICSR_ISRPREEMPT 0x00800000 +#define CPU_SCS_ICSR_ISRPREEMPT_BITN 23 +#define CPU_SCS_ICSR_ISRPREEMPT_M 0x00800000 +#define CPU_SCS_ICSR_ISRPREEMPT_S 23 // Field: [22] ISRPENDING // @@ -2847,18 +2847,18 @@ // // 0x0: Interrupt not pending // 0x1: Interrupt pending -#define CPU_SCS_ICSR_ISRPENDING 0x00400000 -#define CPU_SCS_ICSR_ISRPENDING_BITN 22 -#define CPU_SCS_ICSR_ISRPENDING_M 0x00400000 -#define CPU_SCS_ICSR_ISRPENDING_S 22 +#define CPU_SCS_ICSR_ISRPENDING 0x00400000 +#define CPU_SCS_ICSR_ISRPENDING_BITN 22 +#define CPU_SCS_ICSR_ISRPENDING_M 0x00400000 +#define CPU_SCS_ICSR_ISRPENDING_S 22 // Field: [17:12] VECTPENDING // // Pending ISR number field. This field contains the interrupt number of the // highest priority pending ISR. -#define CPU_SCS_ICSR_VECTPENDING_W 6 -#define CPU_SCS_ICSR_VECTPENDING_M 0x0003F000 -#define CPU_SCS_ICSR_VECTPENDING_S 12 +#define CPU_SCS_ICSR_VECTPENDING_W 6 +#define CPU_SCS_ICSR_VECTPENDING_M 0x0003F000 +#define CPU_SCS_ICSR_VECTPENDING_S 12 // Field: [11] RETTOBASE // @@ -2867,17 +2867,17 @@ // 0: There are preempted active exceptions to execute // 1: There are no active exceptions, or the currently-executing exception is // the only active exception. -#define CPU_SCS_ICSR_RETTOBASE 0x00000800 -#define CPU_SCS_ICSR_RETTOBASE_BITN 11 -#define CPU_SCS_ICSR_RETTOBASE_M 0x00000800 -#define CPU_SCS_ICSR_RETTOBASE_S 11 +#define CPU_SCS_ICSR_RETTOBASE 0x00000800 +#define CPU_SCS_ICSR_RETTOBASE_BITN 11 +#define CPU_SCS_ICSR_RETTOBASE_M 0x00000800 +#define CPU_SCS_ICSR_RETTOBASE_S 11 // Field: [8:0] VECTACTIVE // // Active ISR number field. Reset clears this field. -#define CPU_SCS_ICSR_VECTACTIVE_W 9 -#define CPU_SCS_ICSR_VECTACTIVE_M 0x000001FF -#define CPU_SCS_ICSR_VECTACTIVE_S 0 +#define CPU_SCS_ICSR_VECTACTIVE_W 9 +#define CPU_SCS_ICSR_VECTACTIVE_M 0x000001FF +#define CPU_SCS_ICSR_VECTACTIVE_S 0 //***************************************************************************** // @@ -2887,9 +2887,9 @@ // Field: [29:7] TBLOFF // // Bits 29 down to 7 of the vector table base offset. -#define CPU_SCS_VTOR_TBLOFF_W 23 -#define CPU_SCS_VTOR_TBLOFF_M 0x3FFFFF80 -#define CPU_SCS_VTOR_TBLOFF_S 7 +#define CPU_SCS_VTOR_TBLOFF_W 23 +#define CPU_SCS_VTOR_TBLOFF_M 0x3FFFFF80 +#define CPU_SCS_VTOR_TBLOFF_S 7 //***************************************************************************** // @@ -2900,9 +2900,9 @@ // // Register key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. // Otherwise the write value is ignored. Read always returns 0xFA05. -#define CPU_SCS_AIRCR_VECTKEY_W 16 -#define CPU_SCS_AIRCR_VECTKEY_M 0xFFFF0000 -#define CPU_SCS_AIRCR_VECTKEY_S 16 +#define CPU_SCS_AIRCR_VECTKEY_W 16 +#define CPU_SCS_AIRCR_VECTKEY_M 0xFFFF0000 +#define CPU_SCS_AIRCR_VECTKEY_S 16 // Field: [15] ENDIANESS // @@ -2910,12 +2910,12 @@ // ENUMs: // BIG Big endian // LITTLE Little endian -#define CPU_SCS_AIRCR_ENDIANESS 0x00008000 -#define CPU_SCS_AIRCR_ENDIANESS_BITN 15 -#define CPU_SCS_AIRCR_ENDIANESS_M 0x00008000 -#define CPU_SCS_AIRCR_ENDIANESS_S 15 -#define CPU_SCS_AIRCR_ENDIANESS_BIG 0x00008000 -#define CPU_SCS_AIRCR_ENDIANESS_LITTLE 0x00000000 +#define CPU_SCS_AIRCR_ENDIANESS 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_BITN 15 +#define CPU_SCS_AIRCR_ENDIANESS_M 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_S 15 +#define CPU_SCS_AIRCR_ENDIANESS_BIG 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_LITTLE 0x00000000 // Field: [10:8] PRIGROUP // @@ -2927,18 +2927,18 @@ // means that the PRIGROUP value represents a point starting at the left of the // Least Significant Bit (LSB). The lowest value might not be 0 depending on // the number of bits allocated for priorities, and implementation choices. -#define CPU_SCS_AIRCR_PRIGROUP_W 3 -#define CPU_SCS_AIRCR_PRIGROUP_M 0x00000700 -#define CPU_SCS_AIRCR_PRIGROUP_S 8 +#define CPU_SCS_AIRCR_PRIGROUP_W 3 +#define CPU_SCS_AIRCR_PRIGROUP_M 0x00000700 +#define CPU_SCS_AIRCR_PRIGROUP_S 8 // Field: [2] SYSRESETREQ // // Requests a warm reset. Setting this bit does not prevent Halting Debug from // running. -#define CPU_SCS_AIRCR_SYSRESETREQ 0x00000004 -#define CPU_SCS_AIRCR_SYSRESETREQ_BITN 2 -#define CPU_SCS_AIRCR_SYSRESETREQ_M 0x00000004 -#define CPU_SCS_AIRCR_SYSRESETREQ_S 2 +#define CPU_SCS_AIRCR_SYSRESETREQ 0x00000004 +#define CPU_SCS_AIRCR_SYSRESETREQ_BITN 2 +#define CPU_SCS_AIRCR_SYSRESETREQ_M 0x00000004 +#define CPU_SCS_AIRCR_SYSRESETREQ_S 2 // Field: [1] VECTCLRACTIVE // @@ -2948,10 +2948,10 @@ // IPSR is not cleared by this operation. So, if used by an application, it // must only be used at the base level of activation, or within a system // handler whose active bit can be set. -#define CPU_SCS_AIRCR_VECTCLRACTIVE 0x00000002 -#define CPU_SCS_AIRCR_VECTCLRACTIVE_BITN 1 -#define CPU_SCS_AIRCR_VECTCLRACTIVE_M 0x00000002 -#define CPU_SCS_AIRCR_VECTCLRACTIVE_S 1 +#define CPU_SCS_AIRCR_VECTCLRACTIVE 0x00000002 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_BITN 1 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_M 0x00000002 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_S 1 // Field: [0] VECTRESET // @@ -2959,10 +2959,10 @@ // This bit is reserved for debug use and can be written to 1 only when the // core is halted. The bit self-clears. Writing this bit to 1 while core is not // halted may result in unpredictable behavior. -#define CPU_SCS_AIRCR_VECTRESET 0x00000001 -#define CPU_SCS_AIRCR_VECTRESET_BITN 0 -#define CPU_SCS_AIRCR_VECTRESET_M 0x00000001 -#define CPU_SCS_AIRCR_VECTRESET_S 0 +#define CPU_SCS_AIRCR_VECTRESET 0x00000001 +#define CPU_SCS_AIRCR_VECTRESET_BITN 0 +#define CPU_SCS_AIRCR_VECTRESET_M 0x00000001 +#define CPU_SCS_AIRCR_VECTRESET_S 0 //***************************************************************************** // @@ -2983,10 +2983,10 @@ // the processor is not waiting for an event, the event is registered and // affects the next WFE. // The processor also wakes up on execution of an SEV instruction. -#define CPU_SCS_SCR_SEVONPEND 0x00000010 -#define CPU_SCS_SCR_SEVONPEND_BITN 4 -#define CPU_SCS_SCR_SEVONPEND_M 0x00000010 -#define CPU_SCS_SCR_SEVONPEND_S 4 +#define CPU_SCS_SCR_SEVONPEND 0x00000010 +#define CPU_SCS_SCR_SEVONPEND_BITN 4 +#define CPU_SCS_SCR_SEVONPEND_M 0x00000010 +#define CPU_SCS_SCR_SEVONPEND_S 4 // Field: [2] SLEEPDEEP // @@ -2995,12 +2995,12 @@ // ENUMs: // DEEPSLEEP Deep sleep // SLEEP Sleep -#define CPU_SCS_SCR_SLEEPDEEP 0x00000004 -#define CPU_SCS_SCR_SLEEPDEEP_BITN 2 -#define CPU_SCS_SCR_SLEEPDEEP_M 0x00000004 -#define CPU_SCS_SCR_SLEEPDEEP_S 2 -#define CPU_SCS_SCR_SLEEPDEEP_DEEPSLEEP 0x00000004 -#define CPU_SCS_SCR_SLEEPDEEP_SLEEP 0x00000000 +#define CPU_SCS_SCR_SLEEPDEEP 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_BITN 2 +#define CPU_SCS_SCR_SLEEPDEEP_M 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_S 2 +#define CPU_SCS_SCR_SLEEPDEEP_DEEPSLEEP 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_SLEEP 0x00000000 // Field: [1] SLEEPONEXIT // @@ -3009,10 +3009,10 @@ // // 0: Do not sleep when returning to thread mode // 1: Sleep on ISR exit -#define CPU_SCS_SCR_SLEEPONEXIT 0x00000002 -#define CPU_SCS_SCR_SLEEPONEXIT_BITN 1 -#define CPU_SCS_SCR_SLEEPONEXIT_M 0x00000002 -#define CPU_SCS_SCR_SLEEPONEXIT_S 1 +#define CPU_SCS_SCR_SLEEPONEXIT 0x00000002 +#define CPU_SCS_SCR_SLEEPONEXIT_BITN 1 +#define CPU_SCS_SCR_SLEEPONEXIT_M 0x00000002 +#define CPU_SCS_SCR_SLEEPONEXIT_S 1 //***************************************************************************** // @@ -3028,10 +3028,10 @@ // 1: On exception entry, the SP used prior to the exception is adjusted to be // 8-byte aligned and the context to restore it is saved. The SP is restored on // the associated exception return. -#define CPU_SCS_CCR_STKALIGN 0x00000200 -#define CPU_SCS_CCR_STKALIGN_BITN 9 -#define CPU_SCS_CCR_STKALIGN_M 0x00000200 -#define CPU_SCS_CCR_STKALIGN_S 9 +#define CPU_SCS_CCR_STKALIGN 0x00000200 +#define CPU_SCS_CCR_STKALIGN_BITN 9 +#define CPU_SCS_CCR_STKALIGN_M 0x00000200 +#define CPU_SCS_CCR_STKALIGN_S 9 // Field: [8] BFHFNMIGN // @@ -3045,10 +3045,10 @@ // Set this bit to 1 only when the handler and its data are in absolutely safe // memory. The normal use // of this bit is to probe system devices and bridges to detect problems. -#define CPU_SCS_CCR_BFHFNMIGN 0x00000100 -#define CPU_SCS_CCR_BFHFNMIGN_BITN 8 -#define CPU_SCS_CCR_BFHFNMIGN_M 0x00000100 -#define CPU_SCS_CCR_BFHFNMIGN_S 8 +#define CPU_SCS_CCR_BFHFNMIGN 0x00000100 +#define CPU_SCS_CCR_BFHFNMIGN_BITN 8 +#define CPU_SCS_CCR_BFHFNMIGN_M 0x00000100 +#define CPU_SCS_CCR_BFHFNMIGN_S 8 // Field: [4] DIV_0_TRP // @@ -3059,10 +3059,10 @@ // quotient of 0. // 1: Trap divide by 0. The relevant Usage Fault Status Register bit is // CFSR.DIVBYZERO. -#define CPU_SCS_CCR_DIV_0_TRP 0x00000010 -#define CPU_SCS_CCR_DIV_0_TRP_BITN 4 -#define CPU_SCS_CCR_DIV_0_TRP_M 0x00000010 -#define CPU_SCS_CCR_DIV_0_TRP_S 4 +#define CPU_SCS_CCR_DIV_0_TRP 0x00000010 +#define CPU_SCS_CCR_DIV_0_TRP_BITN 4 +#define CPU_SCS_CCR_DIV_0_TRP_M 0x00000010 +#define CPU_SCS_CCR_DIV_0_TRP_S 4 // Field: [3] UNALIGN_TRP // @@ -3075,10 +3075,10 @@ // If this bit is set to 1, an unaligned access generates a UsageFault. // Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of // the value in UNALIGN_TRP. -#define CPU_SCS_CCR_UNALIGN_TRP 0x00000008 -#define CPU_SCS_CCR_UNALIGN_TRP_BITN 3 -#define CPU_SCS_CCR_UNALIGN_TRP_M 0x00000008 -#define CPU_SCS_CCR_UNALIGN_TRP_S 3 +#define CPU_SCS_CCR_UNALIGN_TRP 0x00000008 +#define CPU_SCS_CCR_UNALIGN_TRP_BITN 3 +#define CPU_SCS_CCR_UNALIGN_TRP_M 0x00000008 +#define CPU_SCS_CCR_UNALIGN_TRP_S 3 // Field: [1] USERSETMPEND // @@ -3089,10 +3089,10 @@ // 1: User code can write the Software Trigger Interrupt register (STIR) to // trigger (pend) a Main exception, which is associated with the Main stack // pointer. -#define CPU_SCS_CCR_USERSETMPEND 0x00000002 -#define CPU_SCS_CCR_USERSETMPEND_BITN 1 -#define CPU_SCS_CCR_USERSETMPEND_M 0x00000002 -#define CPU_SCS_CCR_USERSETMPEND_S 1 +#define CPU_SCS_CCR_USERSETMPEND 0x00000002 +#define CPU_SCS_CCR_USERSETMPEND_BITN 1 +#define CPU_SCS_CCR_USERSETMPEND_M 0x00000002 +#define CPU_SCS_CCR_USERSETMPEND_S 1 // Field: [0] NONBASETHREDENA // @@ -3109,10 +3109,10 @@ // - BX with any register. // The value written to the PC is intercepted and is referred to as the // EXC_RETURN value. -#define CPU_SCS_CCR_NONBASETHREDENA 0x00000001 -#define CPU_SCS_CCR_NONBASETHREDENA_BITN 0 -#define CPU_SCS_CCR_NONBASETHREDENA_M 0x00000001 -#define CPU_SCS_CCR_NONBASETHREDENA_S 0 +#define CPU_SCS_CCR_NONBASETHREDENA 0x00000001 +#define CPU_SCS_CCR_NONBASETHREDENA_BITN 0 +#define CPU_SCS_CCR_NONBASETHREDENA_M 0x00000001 +#define CPU_SCS_CCR_NONBASETHREDENA_S 0 //***************************************************************************** // @@ -3122,23 +3122,23 @@ // Field: [23:16] PRI_6 // // Priority of system handler 6. UsageFault -#define CPU_SCS_SHPR1_PRI_6_W 8 -#define CPU_SCS_SHPR1_PRI_6_M 0x00FF0000 -#define CPU_SCS_SHPR1_PRI_6_S 16 +#define CPU_SCS_SHPR1_PRI_6_W 8 +#define CPU_SCS_SHPR1_PRI_6_M 0x00FF0000 +#define CPU_SCS_SHPR1_PRI_6_S 16 // Field: [15:8] PRI_5 // // Priority of system handler 5: BusFault -#define CPU_SCS_SHPR1_PRI_5_W 8 -#define CPU_SCS_SHPR1_PRI_5_M 0x0000FF00 -#define CPU_SCS_SHPR1_PRI_5_S 8 +#define CPU_SCS_SHPR1_PRI_5_W 8 +#define CPU_SCS_SHPR1_PRI_5_M 0x0000FF00 +#define CPU_SCS_SHPR1_PRI_5_S 8 // Field: [7:0] PRI_4 // // Priority of system handler 4: MemManage -#define CPU_SCS_SHPR1_PRI_4_W 8 -#define CPU_SCS_SHPR1_PRI_4_M 0x000000FF -#define CPU_SCS_SHPR1_PRI_4_S 0 +#define CPU_SCS_SHPR1_PRI_4_W 8 +#define CPU_SCS_SHPR1_PRI_4_M 0x000000FF +#define CPU_SCS_SHPR1_PRI_4_S 0 //***************************************************************************** // @@ -3148,9 +3148,9 @@ // Field: [31:24] PRI_11 // // Priority of system handler 11. SVCall -#define CPU_SCS_SHPR2_PRI_11_W 8 -#define CPU_SCS_SHPR2_PRI_11_M 0xFF000000 -#define CPU_SCS_SHPR2_PRI_11_S 24 +#define CPU_SCS_SHPR2_PRI_11_W 8 +#define CPU_SCS_SHPR2_PRI_11_M 0xFF000000 +#define CPU_SCS_SHPR2_PRI_11_S 24 //***************************************************************************** // @@ -3160,23 +3160,23 @@ // Field: [31:24] PRI_15 // // Priority of system handler 15. SysTick exception -#define CPU_SCS_SHPR3_PRI_15_W 8 -#define CPU_SCS_SHPR3_PRI_15_M 0xFF000000 -#define CPU_SCS_SHPR3_PRI_15_S 24 +#define CPU_SCS_SHPR3_PRI_15_W 8 +#define CPU_SCS_SHPR3_PRI_15_M 0xFF000000 +#define CPU_SCS_SHPR3_PRI_15_S 24 // Field: [23:16] PRI_14 // // Priority of system handler 14. Pend SV -#define CPU_SCS_SHPR3_PRI_14_W 8 -#define CPU_SCS_SHPR3_PRI_14_M 0x00FF0000 -#define CPU_SCS_SHPR3_PRI_14_S 16 +#define CPU_SCS_SHPR3_PRI_14_W 8 +#define CPU_SCS_SHPR3_PRI_14_M 0x00FF0000 +#define CPU_SCS_SHPR3_PRI_14_S 16 // Field: [7:0] PRI_12 // // Priority of system handler 12. Debug Monitor -#define CPU_SCS_SHPR3_PRI_12_W 8 -#define CPU_SCS_SHPR3_PRI_12_M 0x000000FF -#define CPU_SCS_SHPR3_PRI_12_S 0 +#define CPU_SCS_SHPR3_PRI_12_W 8 +#define CPU_SCS_SHPR3_PRI_12_M 0x000000FF +#define CPU_SCS_SHPR3_PRI_12_S 0 //***************************************************************************** // @@ -3189,12 +3189,12 @@ // ENUMs: // EN Exception enabled // DIS Exception disabled -#define CPU_SCS_SHCSR_USGFAULTENA 0x00040000 -#define CPU_SCS_SHCSR_USGFAULTENA_BITN 18 -#define CPU_SCS_SHCSR_USGFAULTENA_M 0x00040000 -#define CPU_SCS_SHCSR_USGFAULTENA_S 18 -#define CPU_SCS_SHCSR_USGFAULTENA_EN 0x00040000 -#define CPU_SCS_SHCSR_USGFAULTENA_DIS 0x00000000 +#define CPU_SCS_SHCSR_USGFAULTENA 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_BITN 18 +#define CPU_SCS_SHCSR_USGFAULTENA_M 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_S 18 +#define CPU_SCS_SHCSR_USGFAULTENA_EN 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_DIS 0x00000000 // Field: [17] BUSFAULTENA // @@ -3202,12 +3202,12 @@ // ENUMs: // EN Exception enabled // DIS Exception disabled -#define CPU_SCS_SHCSR_BUSFAULTENA 0x00020000 -#define CPU_SCS_SHCSR_BUSFAULTENA_BITN 17 -#define CPU_SCS_SHCSR_BUSFAULTENA_M 0x00020000 -#define CPU_SCS_SHCSR_BUSFAULTENA_S 17 -#define CPU_SCS_SHCSR_BUSFAULTENA_EN 0x00020000 -#define CPU_SCS_SHCSR_BUSFAULTENA_DIS 0x00000000 +#define CPU_SCS_SHCSR_BUSFAULTENA 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_BITN 17 +#define CPU_SCS_SHCSR_BUSFAULTENA_M 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_S 17 +#define CPU_SCS_SHCSR_BUSFAULTENA_EN 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_DIS 0x00000000 // Field: [16] MEMFAULTENA // @@ -3215,12 +3215,12 @@ // ENUMs: // EN Exception enabled // DIS Exception disabled -#define CPU_SCS_SHCSR_MEMFAULTENA 0x00010000 -#define CPU_SCS_SHCSR_MEMFAULTENA_BITN 16 -#define CPU_SCS_SHCSR_MEMFAULTENA_M 0x00010000 -#define CPU_SCS_SHCSR_MEMFAULTENA_S 16 -#define CPU_SCS_SHCSR_MEMFAULTENA_EN 0x00010000 -#define CPU_SCS_SHCSR_MEMFAULTENA_DIS 0x00000000 +#define CPU_SCS_SHCSR_MEMFAULTENA 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_BITN 16 +#define CPU_SCS_SHCSR_MEMFAULTENA_M 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_S 16 +#define CPU_SCS_SHCSR_MEMFAULTENA_EN 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_DIS 0x00000000 // Field: [15] SVCALLPENDED // @@ -3228,12 +3228,12 @@ // ENUMs: // PENDING Exception is pending. // NOTPENDING Exception is not active -#define CPU_SCS_SHCSR_SVCALLPENDED 0x00008000 -#define CPU_SCS_SHCSR_SVCALLPENDED_BITN 15 -#define CPU_SCS_SHCSR_SVCALLPENDED_M 0x00008000 -#define CPU_SCS_SHCSR_SVCALLPENDED_S 15 -#define CPU_SCS_SHCSR_SVCALLPENDED_PENDING 0x00008000 -#define CPU_SCS_SHCSR_SVCALLPENDED_NOTPENDING 0x00000000 +#define CPU_SCS_SHCSR_SVCALLPENDED 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_BITN 15 +#define CPU_SCS_SHCSR_SVCALLPENDED_M 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_S 15 +#define CPU_SCS_SHCSR_SVCALLPENDED_PENDING 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_NOTPENDING 0x00000000 // Field: [14] BUSFAULTPENDED // @@ -3241,12 +3241,12 @@ // ENUMs: // PENDING Exception is pending. // NOTPENDING Exception is not active -#define CPU_SCS_SHCSR_BUSFAULTPENDED 0x00004000 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_BITN 14 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_M 0x00004000 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_S 14 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_PENDING 0x00004000 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_NOTPENDING 0x00000000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_BITN 14 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_M 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_S 14 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_PENDING 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_NOTPENDING 0x00000000 // Field: [13] MEMFAULTPENDED // @@ -3254,12 +3254,12 @@ // ENUMs: // PENDING Exception is pending. // NOTPENDING Exception is not active -#define CPU_SCS_SHCSR_MEMFAULTPENDED 0x00002000 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_BITN 13 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_M 0x00002000 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_S 13 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_PENDING 0x00002000 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_NOTPENDING 0x00000000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_BITN 13 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_M 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_S 13 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_PENDING 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_NOTPENDING 0x00000000 // Field: [12] USGFAULTPENDED // @@ -3267,12 +3267,12 @@ // ENUMs: // PENDING Exception is pending. // NOTPENDING Exception is not active -#define CPU_SCS_SHCSR_USGFAULTPENDED 0x00001000 -#define CPU_SCS_SHCSR_USGFAULTPENDED_BITN 12 -#define CPU_SCS_SHCSR_USGFAULTPENDED_M 0x00001000 -#define CPU_SCS_SHCSR_USGFAULTPENDED_S 12 -#define CPU_SCS_SHCSR_USGFAULTPENDED_PENDING 0x00001000 -#define CPU_SCS_SHCSR_USGFAULTPENDED_NOTPENDING 0x00000000 +#define CPU_SCS_SHCSR_USGFAULTPENDED 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_BITN 12 +#define CPU_SCS_SHCSR_USGFAULTPENDED_M 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_S 12 +#define CPU_SCS_SHCSR_USGFAULTPENDED_PENDING 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_NOTPENDING 0x00000000 // Field: [11] SYSTICKACT // @@ -3283,12 +3283,12 @@ // ENUMs: // ACTIVE Exception is active // NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_SYSTICKACT 0x00000800 -#define CPU_SCS_SHCSR_SYSTICKACT_BITN 11 -#define CPU_SCS_SHCSR_SYSTICKACT_M 0x00000800 -#define CPU_SCS_SHCSR_SYSTICKACT_S 11 -#define CPU_SCS_SHCSR_SYSTICKACT_ACTIVE 0x00000800 -#define CPU_SCS_SHCSR_SYSTICKACT_NOTACTIVE 0x00000000 +#define CPU_SCS_SHCSR_SYSTICKACT 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_BITN 11 +#define CPU_SCS_SHCSR_SYSTICKACT_M 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_S 11 +#define CPU_SCS_SHCSR_SYSTICKACT_ACTIVE 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_NOTACTIVE 0x00000000 // Field: [10] PENDSVACT // @@ -3296,10 +3296,10 @@ // // 0x0: Not active // 0x1: Active -#define CPU_SCS_SHCSR_PENDSVACT 0x00000400 -#define CPU_SCS_SHCSR_PENDSVACT_BITN 10 -#define CPU_SCS_SHCSR_PENDSVACT_M 0x00000400 -#define CPU_SCS_SHCSR_PENDSVACT_S 10 +#define CPU_SCS_SHCSR_PENDSVACT 0x00000400 +#define CPU_SCS_SHCSR_PENDSVACT_BITN 10 +#define CPU_SCS_SHCSR_PENDSVACT_M 0x00000400 +#define CPU_SCS_SHCSR_PENDSVACT_S 10 // Field: [8] MONITORACT // @@ -3307,12 +3307,12 @@ // ENUMs: // ACTIVE Exception is active // NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_MONITORACT 0x00000100 -#define CPU_SCS_SHCSR_MONITORACT_BITN 8 -#define CPU_SCS_SHCSR_MONITORACT_M 0x00000100 -#define CPU_SCS_SHCSR_MONITORACT_S 8 -#define CPU_SCS_SHCSR_MONITORACT_ACTIVE 0x00000100 -#define CPU_SCS_SHCSR_MONITORACT_NOTACTIVE 0x00000000 +#define CPU_SCS_SHCSR_MONITORACT 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_BITN 8 +#define CPU_SCS_SHCSR_MONITORACT_M 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_S 8 +#define CPU_SCS_SHCSR_MONITORACT_ACTIVE 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_NOTACTIVE 0x00000000 // Field: [7] SVCALLACT // @@ -3320,12 +3320,12 @@ // ENUMs: // ACTIVE Exception is active // NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_SVCALLACT 0x00000080 -#define CPU_SCS_SHCSR_SVCALLACT_BITN 7 -#define CPU_SCS_SHCSR_SVCALLACT_M 0x00000080 -#define CPU_SCS_SHCSR_SVCALLACT_S 7 -#define CPU_SCS_SHCSR_SVCALLACT_ACTIVE 0x00000080 -#define CPU_SCS_SHCSR_SVCALLACT_NOTACTIVE 0x00000000 +#define CPU_SCS_SHCSR_SVCALLACT 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_BITN 7 +#define CPU_SCS_SHCSR_SVCALLACT_M 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_S 7 +#define CPU_SCS_SHCSR_SVCALLACT_ACTIVE 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_NOTACTIVE 0x00000000 // Field: [3] USGFAULTACT // @@ -3333,12 +3333,12 @@ // ENUMs: // ACTIVE Exception is active // NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_USGFAULTACT 0x00000008 -#define CPU_SCS_SHCSR_USGFAULTACT_BITN 3 -#define CPU_SCS_SHCSR_USGFAULTACT_M 0x00000008 -#define CPU_SCS_SHCSR_USGFAULTACT_S 3 -#define CPU_SCS_SHCSR_USGFAULTACT_ACTIVE 0x00000008 -#define CPU_SCS_SHCSR_USGFAULTACT_NOTACTIVE 0x00000000 +#define CPU_SCS_SHCSR_USGFAULTACT 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_BITN 3 +#define CPU_SCS_SHCSR_USGFAULTACT_M 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_S 3 +#define CPU_SCS_SHCSR_USGFAULTACT_ACTIVE 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_NOTACTIVE 0x00000000 // Field: [1] BUSFAULTACT // @@ -3346,12 +3346,12 @@ // ENUMs: // ACTIVE Exception is active // NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_BUSFAULTACT 0x00000002 -#define CPU_SCS_SHCSR_BUSFAULTACT_BITN 1 -#define CPU_SCS_SHCSR_BUSFAULTACT_M 0x00000002 -#define CPU_SCS_SHCSR_BUSFAULTACT_S 1 -#define CPU_SCS_SHCSR_BUSFAULTACT_ACTIVE 0x00000002 -#define CPU_SCS_SHCSR_BUSFAULTACT_NOTACTIVE 0x00000000 +#define CPU_SCS_SHCSR_BUSFAULTACT 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_BITN 1 +#define CPU_SCS_SHCSR_BUSFAULTACT_M 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_S 1 +#define CPU_SCS_SHCSR_BUSFAULTACT_ACTIVE 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_NOTACTIVE 0x00000000 // Field: [0] MEMFAULTACT // @@ -3359,12 +3359,12 @@ // ENUMs: // ACTIVE Exception is active // NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_MEMFAULTACT 0x00000001 -#define CPU_SCS_SHCSR_MEMFAULTACT_BITN 0 -#define CPU_SCS_SHCSR_MEMFAULTACT_M 0x00000001 -#define CPU_SCS_SHCSR_MEMFAULTACT_S 0 -#define CPU_SCS_SHCSR_MEMFAULTACT_ACTIVE 0x00000001 -#define CPU_SCS_SHCSR_MEMFAULTACT_NOTACTIVE 0x00000000 +#define CPU_SCS_SHCSR_MEMFAULTACT 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_BITN 0 +#define CPU_SCS_SHCSR_MEMFAULTACT_M 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_S 0 +#define CPU_SCS_SHCSR_MEMFAULTACT_ACTIVE 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_NOTACTIVE 0x00000000 //***************************************************************************** // @@ -3377,39 +3377,39 @@ // enabled and an SDIV or UDIV instruction is used with a divisor of 0, this // fault occurs The instruction is executed and the return PC points to it. If // CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0. -#define CPU_SCS_CFSR_DIVBYZERO 0x02000000 -#define CPU_SCS_CFSR_DIVBYZERO_BITN 25 -#define CPU_SCS_CFSR_DIVBYZERO_M 0x02000000 -#define CPU_SCS_CFSR_DIVBYZERO_S 25 +#define CPU_SCS_CFSR_DIVBYZERO 0x02000000 +#define CPU_SCS_CFSR_DIVBYZERO_BITN 25 +#define CPU_SCS_CFSR_DIVBYZERO_M 0x02000000 +#define CPU_SCS_CFSR_DIVBYZERO_S 25 // Field: [24] UNALIGNED // // When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an // unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD // instructions always fault irrespective of the setting of CCR.UNALIGN_TRP. -#define CPU_SCS_CFSR_UNALIGNED 0x01000000 -#define CPU_SCS_CFSR_UNALIGNED_BITN 24 -#define CPU_SCS_CFSR_UNALIGNED_M 0x01000000 -#define CPU_SCS_CFSR_UNALIGNED_S 24 +#define CPU_SCS_CFSR_UNALIGNED 0x01000000 +#define CPU_SCS_CFSR_UNALIGNED_BITN 24 +#define CPU_SCS_CFSR_UNALIGNED_M 0x01000000 +#define CPU_SCS_CFSR_UNALIGNED_S 24 // Field: [19] NOCP // // Attempt to use a coprocessor instruction. The processor does not support // coprocessor instructions. -#define CPU_SCS_CFSR_NOCP 0x00080000 -#define CPU_SCS_CFSR_NOCP_BITN 19 -#define CPU_SCS_CFSR_NOCP_M 0x00080000 -#define CPU_SCS_CFSR_NOCP_S 19 +#define CPU_SCS_CFSR_NOCP 0x00080000 +#define CPU_SCS_CFSR_NOCP_BITN 19 +#define CPU_SCS_CFSR_NOCP_M 0x00080000 +#define CPU_SCS_CFSR_NOCP_S 19 // Field: [18] INVPC // // Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid // context, invalid value. The return PC points to the instruction that tried // to set the PC. -#define CPU_SCS_CFSR_INVPC 0x00040000 -#define CPU_SCS_CFSR_INVPC_BITN 18 -#define CPU_SCS_CFSR_INVPC_M 0x00040000 -#define CPU_SCS_CFSR_INVPC_S 18 +#define CPU_SCS_CFSR_INVPC 0x00040000 +#define CPU_SCS_CFSR_INVPC_BITN 18 +#define CPU_SCS_CFSR_INVPC_M 0x00040000 +#define CPU_SCS_CFSR_INVPC_S 18 // Field: [17] INVSTATE // @@ -3417,20 +3417,20 @@ // type instruction has changed state). This includes state change after entry // to or return from exception, as well as from inter-working instructions. // Return PC points to faulting instruction, with the invalid state. -#define CPU_SCS_CFSR_INVSTATE 0x00020000 -#define CPU_SCS_CFSR_INVSTATE_BITN 17 -#define CPU_SCS_CFSR_INVSTATE_M 0x00020000 -#define CPU_SCS_CFSR_INVSTATE_S 17 +#define CPU_SCS_CFSR_INVSTATE 0x00020000 +#define CPU_SCS_CFSR_INVSTATE_BITN 17 +#define CPU_SCS_CFSR_INVSTATE_M 0x00020000 +#define CPU_SCS_CFSR_INVSTATE_S 17 // Field: [16] UNDEFINSTR // // This bit is set when the processor attempts to execute an undefined // instruction. This is an instruction that the processor cannot decode. The // return PC points to the undefined instruction. -#define CPU_SCS_CFSR_UNDEFINSTR 0x00010000 -#define CPU_SCS_CFSR_UNDEFINSTR_BITN 16 -#define CPU_SCS_CFSR_UNDEFINSTR_M 0x00010000 -#define CPU_SCS_CFSR_UNDEFINSTR_S 16 +#define CPU_SCS_CFSR_UNDEFINSTR 0x00010000 +#define CPU_SCS_CFSR_UNDEFINSTR_BITN 16 +#define CPU_SCS_CFSR_UNDEFINSTR_M 0x00010000 +#define CPU_SCS_CFSR_UNDEFINSTR_S 16 // Field: [15] BFARVALID // @@ -3440,20 +3440,20 @@ // Bus fault occurs that is escalated to a Hard Fault because of priority, the // Hard Fault handler must clear this bit. This prevents problems if returning // to a stacked active Bus fault handler whose BFAR value has been overwritten. -#define CPU_SCS_CFSR_BFARVALID 0x00008000 -#define CPU_SCS_CFSR_BFARVALID_BITN 15 -#define CPU_SCS_CFSR_BFARVALID_M 0x00008000 -#define CPU_SCS_CFSR_BFARVALID_S 15 +#define CPU_SCS_CFSR_BFARVALID 0x00008000 +#define CPU_SCS_CFSR_BFARVALID_BITN 15 +#define CPU_SCS_CFSR_BFARVALID_M 0x00008000 +#define CPU_SCS_CFSR_BFARVALID_S 15 // Field: [12] STKERR // // Stacking from exception has caused one or more bus faults. The SP is still // adjusted and the values in the context area on the stack might be incorrect. // BFAR is not written. -#define CPU_SCS_CFSR_STKERR 0x00001000 -#define CPU_SCS_CFSR_STKERR_BITN 12 -#define CPU_SCS_CFSR_STKERR_M 0x00001000 -#define CPU_SCS_CFSR_STKERR_S 12 +#define CPU_SCS_CFSR_STKERR 0x00001000 +#define CPU_SCS_CFSR_STKERR_BITN 12 +#define CPU_SCS_CFSR_STKERR_M 0x00001000 +#define CPU_SCS_CFSR_STKERR_S 12 // Field: [11] UNSTKERR // @@ -3461,10 +3461,10 @@ // chained to the handler, so that the original return stack is still present. // SP is not adjusted from failing return and new save is not performed. BFAR // is not written. -#define CPU_SCS_CFSR_UNSTKERR 0x00000800 -#define CPU_SCS_CFSR_UNSTKERR_BITN 11 -#define CPU_SCS_CFSR_UNSTKERR_M 0x00000800 -#define CPU_SCS_CFSR_UNSTKERR_S 11 +#define CPU_SCS_CFSR_UNSTKERR 0x00000800 +#define CPU_SCS_CFSR_UNSTKERR_BITN 11 +#define CPU_SCS_CFSR_UNSTKERR_M 0x00000800 +#define CPU_SCS_CFSR_UNSTKERR_S 11 // Field: [10] IMPRECISERR // @@ -3475,28 +3475,28 @@ // activation. If a precise fault occurs before returning to a lower priority // exception, the handler detects both IMPRECISERR set and one of the precise // fault status bits set at the same time. BFAR is not written. -#define CPU_SCS_CFSR_IMPRECISERR 0x00000400 -#define CPU_SCS_CFSR_IMPRECISERR_BITN 10 -#define CPU_SCS_CFSR_IMPRECISERR_M 0x00000400 -#define CPU_SCS_CFSR_IMPRECISERR_S 10 +#define CPU_SCS_CFSR_IMPRECISERR 0x00000400 +#define CPU_SCS_CFSR_IMPRECISERR_BITN 10 +#define CPU_SCS_CFSR_IMPRECISERR_M 0x00000400 +#define CPU_SCS_CFSR_IMPRECISERR_S 10 // Field: [9] PRECISERR // // Precise data bus error return. -#define CPU_SCS_CFSR_PRECISERR 0x00000200 -#define CPU_SCS_CFSR_PRECISERR_BITN 9 -#define CPU_SCS_CFSR_PRECISERR_M 0x00000200 -#define CPU_SCS_CFSR_PRECISERR_S 9 +#define CPU_SCS_CFSR_PRECISERR 0x00000200 +#define CPU_SCS_CFSR_PRECISERR_BITN 9 +#define CPU_SCS_CFSR_PRECISERR_M 0x00000200 +#define CPU_SCS_CFSR_PRECISERR_S 9 // Field: [8] IBUSERR // // Instruction bus error flag. This flag is set by a prefetch error. The fault // stops on the instruction, so if the error occurs under a branch shadow, no // fault occurs. BFAR is not written. -#define CPU_SCS_CFSR_IBUSERR 0x00000100 -#define CPU_SCS_CFSR_IBUSERR_BITN 8 -#define CPU_SCS_CFSR_IBUSERR_M 0x00000100 -#define CPU_SCS_CFSR_IBUSERR_S 8 +#define CPU_SCS_CFSR_IBUSERR 0x00000100 +#define CPU_SCS_CFSR_IBUSERR_BITN 8 +#define CPU_SCS_CFSR_IBUSERR_M 0x00000100 +#define CPU_SCS_CFSR_IBUSERR_S 8 // Field: [7] MMARVALID // @@ -3505,20 +3505,20 @@ // fault occurs that is escalated to a Hard Fault because of priority, the Hard // Fault handler must clear this bit. This prevents problems on return to a // stacked active MemManage handler whose MMFAR value has been overwritten. -#define CPU_SCS_CFSR_MMARVALID 0x00000080 -#define CPU_SCS_CFSR_MMARVALID_BITN 7 -#define CPU_SCS_CFSR_MMARVALID_M 0x00000080 -#define CPU_SCS_CFSR_MMARVALID_S 7 +#define CPU_SCS_CFSR_MMARVALID 0x00000080 +#define CPU_SCS_CFSR_MMARVALID_BITN 7 +#define CPU_SCS_CFSR_MMARVALID_M 0x00000080 +#define CPU_SCS_CFSR_MMARVALID_S 7 // Field: [4] MSTKERR // // Stacking from exception has caused one or more access violations. The SP is // still adjusted and the values in the context area on the stack might be // incorrect. MMFAR is not written. -#define CPU_SCS_CFSR_MSTKERR 0x00000010 -#define CPU_SCS_CFSR_MSTKERR_BITN 4 -#define CPU_SCS_CFSR_MSTKERR_M 0x00000010 -#define CPU_SCS_CFSR_MSTKERR_S 4 +#define CPU_SCS_CFSR_MSTKERR 0x00000010 +#define CPU_SCS_CFSR_MSTKERR_BITN 4 +#define CPU_SCS_CFSR_MSTKERR_M 0x00000010 +#define CPU_SCS_CFSR_MSTKERR_S 4 // Field: [3] MUNSTKERR // @@ -3526,10 +3526,10 @@ // is chained to the handler, so that the original return stack is still // present. SP is not adjusted from failing return and new save is not // performed. MMFAR is not written. -#define CPU_SCS_CFSR_MUNSTKERR 0x00000008 -#define CPU_SCS_CFSR_MUNSTKERR_BITN 3 -#define CPU_SCS_CFSR_MUNSTKERR_M 0x00000008 -#define CPU_SCS_CFSR_MUNSTKERR_S 3 +#define CPU_SCS_CFSR_MUNSTKERR 0x00000008 +#define CPU_SCS_CFSR_MUNSTKERR_BITN 3 +#define CPU_SCS_CFSR_MUNSTKERR_M 0x00000008 +#define CPU_SCS_CFSR_MUNSTKERR_S 3 // Field: [1] DACCVIOL // @@ -3537,10 +3537,10 @@ // does not permit the operation sets this flag. The return PC points to the // faulting instruction. This error loads MMFAR with the address of the // attempted access. -#define CPU_SCS_CFSR_DACCVIOL 0x00000002 -#define CPU_SCS_CFSR_DACCVIOL_BITN 1 -#define CPU_SCS_CFSR_DACCVIOL_M 0x00000002 -#define CPU_SCS_CFSR_DACCVIOL_S 1 +#define CPU_SCS_CFSR_DACCVIOL 0x00000002 +#define CPU_SCS_CFSR_DACCVIOL_BITN 1 +#define CPU_SCS_CFSR_DACCVIOL_M 0x00000002 +#define CPU_SCS_CFSR_DACCVIOL_S 1 // Field: [0] IACCVIOL // @@ -3548,10 +3548,10 @@ // location that does not permit execution sets this flag. This occurs on any // access to an XN region, even when the MPU is disabled or not present. The // return PC points to the faulting instruction. MMFAR is not written. -#define CPU_SCS_CFSR_IACCVIOL 0x00000001 -#define CPU_SCS_CFSR_IACCVIOL_BITN 0 -#define CPU_SCS_CFSR_IACCVIOL_M 0x00000001 -#define CPU_SCS_CFSR_IACCVIOL_S 0 +#define CPU_SCS_CFSR_IACCVIOL 0x00000001 +#define CPU_SCS_CFSR_IACCVIOL_BITN 0 +#define CPU_SCS_CFSR_IACCVIOL_M 0x00000001 +#define CPU_SCS_CFSR_IACCVIOL_S 0 //***************************************************************************** // @@ -3566,10 +3566,10 @@ // both halting and monitor debug are disabled, it only happens for debug // events that are not ignored (minimally, BKPT). The Debug Fault Status // Register is updated. -#define CPU_SCS_HFSR_DEBUGEVT 0x80000000 -#define CPU_SCS_HFSR_DEBUGEVT_BITN 31 -#define CPU_SCS_HFSR_DEBUGEVT_M 0x80000000 -#define CPU_SCS_HFSR_DEBUGEVT_S 31 +#define CPU_SCS_HFSR_DEBUGEVT 0x80000000 +#define CPU_SCS_HFSR_DEBUGEVT_BITN 31 +#define CPU_SCS_HFSR_DEBUGEVT_M 0x80000000 +#define CPU_SCS_HFSR_DEBUGEVT_S 31 // Field: [30] FORCED // @@ -3577,20 +3577,20 @@ // activate because of priority or because the Configurable Fault is disabled. // The Hard Fault handler then has to read the other fault status registers to // determine cause. -#define CPU_SCS_HFSR_FORCED 0x40000000 -#define CPU_SCS_HFSR_FORCED_BITN 30 -#define CPU_SCS_HFSR_FORCED_M 0x40000000 -#define CPU_SCS_HFSR_FORCED_S 30 +#define CPU_SCS_HFSR_FORCED 0x40000000 +#define CPU_SCS_HFSR_FORCED_BITN 30 +#define CPU_SCS_HFSR_FORCED_M 0x40000000 +#define CPU_SCS_HFSR_FORCED_S 30 // Field: [1] VECTTBL // // This bit is set if there is a fault because of vector table read on // exception processing (Bus Fault). This case is always a Hard Fault. The // return PC points to the pre-empted instruction. -#define CPU_SCS_HFSR_VECTTBL 0x00000002 -#define CPU_SCS_HFSR_VECTTBL_BITN 1 -#define CPU_SCS_HFSR_VECTTBL_M 0x00000002 -#define CPU_SCS_HFSR_VECTTBL_S 1 +#define CPU_SCS_HFSR_VECTTBL 0x00000002 +#define CPU_SCS_HFSR_VECTTBL_BITN 1 +#define CPU_SCS_HFSR_VECTTBL_M 0x00000002 +#define CPU_SCS_HFSR_VECTTBL_S 1 //***************************************************************************** // @@ -3604,10 +3604,10 @@ // // 0x0: External debug request signal not asserted // 0x1: External debug request signal asserted -#define CPU_SCS_DFSR_EXTERNAL 0x00000010 -#define CPU_SCS_DFSR_EXTERNAL_BITN 4 -#define CPU_SCS_DFSR_EXTERNAL_M 0x00000010 -#define CPU_SCS_DFSR_EXTERNAL_S 4 +#define CPU_SCS_DFSR_EXTERNAL 0x00000010 +#define CPU_SCS_DFSR_EXTERNAL_BITN 4 +#define CPU_SCS_DFSR_EXTERNAL_M 0x00000010 +#define CPU_SCS_DFSR_EXTERNAL_S 4 // Field: [3] VCATCH // @@ -3616,10 +3616,10 @@ // // 0x0: No vector catch occurred // 0x1: Vector catch occurred -#define CPU_SCS_DFSR_VCATCH 0x00000008 -#define CPU_SCS_DFSR_VCATCH_BITN 3 -#define CPU_SCS_DFSR_VCATCH_M 0x00000008 -#define CPU_SCS_DFSR_VCATCH_S 3 +#define CPU_SCS_DFSR_VCATCH 0x00000008 +#define CPU_SCS_DFSR_VCATCH_BITN 3 +#define CPU_SCS_DFSR_VCATCH_M 0x00000008 +#define CPU_SCS_DFSR_VCATCH_S 3 // Field: [2] DWTTRAP // @@ -3628,10 +3628,10 @@ // // 0x0: No DWT match // 0x1: DWT match -#define CPU_SCS_DFSR_DWTTRAP 0x00000004 -#define CPU_SCS_DFSR_DWTTRAP_BITN 2 -#define CPU_SCS_DFSR_DWTTRAP_M 0x00000004 -#define CPU_SCS_DFSR_DWTTRAP_S 2 +#define CPU_SCS_DFSR_DWTTRAP 0x00000004 +#define CPU_SCS_DFSR_DWTTRAP_BITN 2 +#define CPU_SCS_DFSR_DWTTRAP_M 0x00000004 +#define CPU_SCS_DFSR_DWTTRAP_S 2 // Field: [1] BKPT // @@ -3641,10 +3641,10 @@ // // 0x0: No BKPT instruction execution // 0x1: BKPT instruction execution -#define CPU_SCS_DFSR_BKPT 0x00000002 -#define CPU_SCS_DFSR_BKPT_BITN 1 -#define CPU_SCS_DFSR_BKPT_M 0x00000002 -#define CPU_SCS_DFSR_BKPT_S 1 +#define CPU_SCS_DFSR_BKPT 0x00000002 +#define CPU_SCS_DFSR_BKPT_BITN 1 +#define CPU_SCS_DFSR_BKPT_M 0x00000002 +#define CPU_SCS_DFSR_BKPT_S 1 // Field: [0] HALTED // @@ -3652,10 +3652,10 @@ // // 0x0: No halt request // 0x1: Halt requested by NVIC, including step -#define CPU_SCS_DFSR_HALTED 0x00000001 -#define CPU_SCS_DFSR_HALTED_BITN 0 -#define CPU_SCS_DFSR_HALTED_M 0x00000001 -#define CPU_SCS_DFSR_HALTED_S 0 +#define CPU_SCS_DFSR_HALTED 0x00000001 +#define CPU_SCS_DFSR_HALTED_BITN 0 +#define CPU_SCS_DFSR_HALTED_M 0x00000001 +#define CPU_SCS_DFSR_HALTED_S 0 //***************************************************************************** // @@ -3671,9 +3671,9 @@ // address can be any offset in the range of the requested size. Flags // CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination // with CFSR.MMARVALIDindicate the cause of the fault. -#define CPU_SCS_MMFAR_ADDRESS_W 32 -#define CPU_SCS_MMFAR_ADDRESS_M 0xFFFFFFFF -#define CPU_SCS_MMFAR_ADDRESS_S 0 +#define CPU_SCS_MMFAR_ADDRESS_W 32 +#define CPU_SCS_MMFAR_ADDRESS_M 0xFFFFFFFF +#define CPU_SCS_MMFAR_ADDRESS_S 0 //***************************************************************************** // @@ -3688,9 +3688,9 @@ // Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and // CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the // fault. -#define CPU_SCS_BFAR_ADDRESS_W 32 -#define CPU_SCS_BFAR_ADDRESS_M 0xFFFFFFFF -#define CPU_SCS_BFAR_ADDRESS_S 0 +#define CPU_SCS_BFAR_ADDRESS_W 32 +#define CPU_SCS_BFAR_ADDRESS_M 0xFFFFFFFF +#define CPU_SCS_BFAR_ADDRESS_S 0 //***************************************************************************** // @@ -3701,9 +3701,9 @@ // // Implementation defined. The bits map directly onto the signal assignment to // the auxiliary fault inputs. Tied to 0 -#define CPU_SCS_AFSR_IMPDEF_W 32 -#define CPU_SCS_AFSR_IMPDEF_M 0xFFFFFFFF -#define CPU_SCS_AFSR_IMPDEF_S 0 +#define CPU_SCS_AFSR_IMPDEF_W 32 +#define CPU_SCS_AFSR_IMPDEF_M 0xFFFFFFFF +#define CPU_SCS_AFSR_IMPDEF_S 0 //***************************************************************************** // @@ -3721,9 +3721,9 @@ // instructions can be added using the appropriate instruction attribute, but // other 32-bit basic instructions cannot.) // 0x3: Thumb-2 encoding with all Thumb-2 basic instructions -#define CPU_SCS_ID_PFR0_STATE1_W 4 -#define CPU_SCS_ID_PFR0_STATE1_M 0x000000F0 -#define CPU_SCS_ID_PFR0_STATE1_S 4 +#define CPU_SCS_ID_PFR0_STATE1_W 4 +#define CPU_SCS_ID_PFR0_STATE1_M 0x000000F0 +#define CPU_SCS_ID_PFR0_STATE1_S 4 // Field: [3:0] STATE0 // @@ -3731,9 +3731,9 @@ // // 0x0: No ARM encoding // 0x1: N/A -#define CPU_SCS_ID_PFR0_STATE0_W 4 -#define CPU_SCS_ID_PFR0_STATE0_M 0x0000000F -#define CPU_SCS_ID_PFR0_STATE0_S 0 +#define CPU_SCS_ID_PFR0_STATE0_W 4 +#define CPU_SCS_ID_PFR0_STATE0_M 0x0000000F +#define CPU_SCS_ID_PFR0_STATE0_S 0 //***************************************************************************** // @@ -3746,9 +3746,9 @@ // // 0x0: Not supported // 0x2: Two-stack support -#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_W 4 -#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M 0x00000F00 -#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_S 8 +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_W 4 +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M 0x00000F00 +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_S 8 //***************************************************************************** // @@ -3761,9 +3761,9 @@ // // 0x0: Not supported // 0x1: Microcontroller debug v1 (ITMv1 and DWTv1) -#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_W 4 -#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_M 0x00F00000 -#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_S 20 +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_W 4 +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_M 0x00F00000 +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_S 20 //***************************************************************************** // @@ -3791,10 +3791,10 @@ // // 0x0: Not supported // 0x1: Wait for interrupt supported -#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING 0x01000000 -#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_BITN 24 -#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M 0x01000000 -#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_S 24 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING 0x01000000 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_BITN 24 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M 0x01000000 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_S 24 //***************************************************************************** // @@ -3839,25 +3839,25 @@ // Field: [23:16] IREGION // // The processor core uses only a unified MPU, this field always reads 0x0. -#define CPU_SCS_MPU_TYPE_IREGION_W 8 -#define CPU_SCS_MPU_TYPE_IREGION_M 0x00FF0000 -#define CPU_SCS_MPU_TYPE_IREGION_S 16 +#define CPU_SCS_MPU_TYPE_IREGION_W 8 +#define CPU_SCS_MPU_TYPE_IREGION_M 0x00FF0000 +#define CPU_SCS_MPU_TYPE_IREGION_S 16 // Field: [15:8] DREGION // // Number of supported MPU regions field. This field reads 0x08 indicating // eight MPU regions. -#define CPU_SCS_MPU_TYPE_DREGION_W 8 -#define CPU_SCS_MPU_TYPE_DREGION_M 0x0000FF00 -#define CPU_SCS_MPU_TYPE_DREGION_S 8 +#define CPU_SCS_MPU_TYPE_DREGION_W 8 +#define CPU_SCS_MPU_TYPE_DREGION_M 0x0000FF00 +#define CPU_SCS_MPU_TYPE_DREGION_S 8 // Field: [0] SEPARATE // // The processor core uses only a unified MPU, thus this field is always 0. -#define CPU_SCS_MPU_TYPE_SEPARATE 0x00000001 -#define CPU_SCS_MPU_TYPE_SEPARATE_BITN 0 -#define CPU_SCS_MPU_TYPE_SEPARATE_M 0x00000001 -#define CPU_SCS_MPU_TYPE_SEPARATE_S 0 +#define CPU_SCS_MPU_TYPE_SEPARATE 0x00000001 +#define CPU_SCS_MPU_TYPE_SEPARATE_BITN 0 +#define CPU_SCS_MPU_TYPE_SEPARATE_M 0x00000001 +#define CPU_SCS_MPU_TYPE_SEPARATE_S 0 //***************************************************************************** // @@ -3877,10 +3877,10 @@ // the MPU is disabled, the default map acts on both privileged and user mode // code. XN and SO rules always apply to the system partition whether this // enable is set or not. If the MPU is disabled, this bit is ignored. -#define CPU_SCS_MPU_CTRL_PRIVDEFENA 0x00000004 -#define CPU_SCS_MPU_CTRL_PRIVDEFENA_BITN 2 -#define CPU_SCS_MPU_CTRL_PRIVDEFENA_M 0x00000004 -#define CPU_SCS_MPU_CTRL_PRIVDEFENA_S 2 +#define CPU_SCS_MPU_CTRL_PRIVDEFENA 0x00000004 +#define CPU_SCS_MPU_CTRL_PRIVDEFENA_BITN 2 +#define CPU_SCS_MPU_CTRL_PRIVDEFENA_M 0x00000004 +#define CPU_SCS_MPU_CTRL_PRIVDEFENA_S 2 // Field: [1] HFNMIENA // @@ -3889,10 +3889,10 @@ // handlers. If this bit is not set, the MPU is disabled when in these // handlers, regardless of the value of ENABLE bit. If this bit is set and // ENABLE is not set, behavior is unpredictable. -#define CPU_SCS_MPU_CTRL_HFNMIENA 0x00000002 -#define CPU_SCS_MPU_CTRL_HFNMIENA_BITN 1 -#define CPU_SCS_MPU_CTRL_HFNMIENA_M 0x00000002 -#define CPU_SCS_MPU_CTRL_HFNMIENA_S 1 +#define CPU_SCS_MPU_CTRL_HFNMIENA 0x00000002 +#define CPU_SCS_MPU_CTRL_HFNMIENA_BITN 1 +#define CPU_SCS_MPU_CTRL_HFNMIENA_M 0x00000002 +#define CPU_SCS_MPU_CTRL_HFNMIENA_S 1 // Field: [0] ENABLE // @@ -3900,10 +3900,10 @@ // // 0: MPU disabled // 1: MPU enabled -#define CPU_SCS_MPU_CTRL_ENABLE 0x00000001 -#define CPU_SCS_MPU_CTRL_ENABLE_BITN 0 -#define CPU_SCS_MPU_CTRL_ENABLE_M 0x00000001 -#define CPU_SCS_MPU_CTRL_ENABLE_S 0 +#define CPU_SCS_MPU_CTRL_ENABLE 0x00000001 +#define CPU_SCS_MPU_CTRL_ENABLE_BITN 0 +#define CPU_SCS_MPU_CTRL_ENABLE_M 0x00000001 +#define CPU_SCS_MPU_CTRL_ENABLE_S 0 //***************************************************************************** // @@ -3916,9 +3916,9 @@ // This field selects the region to operate on when using the MPU_RASR and // MPU_RBAR. It must be written first except when the address MPU_RBAR.VALID // and MPU_RBAR.REGION fields are written, which overwrites this. -#define CPU_SCS_MPU_RNR_REGION_W 8 -#define CPU_SCS_MPU_RNR_REGION_M 0x000000FF -#define CPU_SCS_MPU_RNR_REGION_S 0 +#define CPU_SCS_MPU_RNR_REGION_W 8 +#define CPU_SCS_MPU_RNR_REGION_M 0x000000FF +#define CPU_SCS_MPU_RNR_REGION_S 0 //***************************************************************************** // @@ -3932,26 +3932,26 @@ // is aligned according to an even multiple of size. The power of 2 size // specified by the SZENABLE field of the MPU Region Attribute and Size // Register defines how many bits of base address are used. -#define CPU_SCS_MPU_RBAR_ADDR_W 27 -#define CPU_SCS_MPU_RBAR_ADDR_M 0xFFFFFFE0 -#define CPU_SCS_MPU_RBAR_ADDR_S 5 +#define CPU_SCS_MPU_RBAR_ADDR_W 27 +#define CPU_SCS_MPU_RBAR_ADDR_M 0xFFFFFFE0 +#define CPU_SCS_MPU_RBAR_ADDR_S 5 // Field: [4] VALID // // MPU region number valid: // 0: MPU_RNR remains unchanged and is interpreted. // 1: MPU_RNR is overwritten by REGION. -#define CPU_SCS_MPU_RBAR_VALID 0x00000010 -#define CPU_SCS_MPU_RBAR_VALID_BITN 4 -#define CPU_SCS_MPU_RBAR_VALID_M 0x00000010 -#define CPU_SCS_MPU_RBAR_VALID_S 4 +#define CPU_SCS_MPU_RBAR_VALID 0x00000010 +#define CPU_SCS_MPU_RBAR_VALID_BITN 4 +#define CPU_SCS_MPU_RBAR_VALID_M 0x00000010 +#define CPU_SCS_MPU_RBAR_VALID_S 4 // Field: [3:0] REGION // // MPU region override field -#define CPU_SCS_MPU_RBAR_REGION_W 4 -#define CPU_SCS_MPU_RBAR_REGION_M 0x0000000F -#define CPU_SCS_MPU_RBAR_REGION_S 0 +#define CPU_SCS_MPU_RBAR_REGION_W 4 +#define CPU_SCS_MPU_RBAR_REGION_M 0x0000000F +#define CPU_SCS_MPU_RBAR_REGION_S 0 //***************************************************************************** // @@ -3963,10 +3963,10 @@ // Instruction access disable: // 0: Enable instruction fetches // 1: Disable instruction fetches -#define CPU_SCS_MPU_RASR_XN 0x10000000 -#define CPU_SCS_MPU_RASR_XN_BITN 28 -#define CPU_SCS_MPU_RASR_XN_M 0x10000000 -#define CPU_SCS_MPU_RASR_XN_S 28 +#define CPU_SCS_MPU_RASR_XN 0x10000000 +#define CPU_SCS_MPU_RASR_XN_BITN 28 +#define CPU_SCS_MPU_RASR_XN_M 0x10000000 +#define CPU_SCS_MPU_RASR_XN_S 28 // Field: [26:24] AP // @@ -3979,46 +3979,46 @@ // 0x5: Priviliged permissions: Read-only. User permissions: No access. // 0x6: Priviliged permissions: Read-only. User permissions: Read-only. // 0x7: Priviliged permissions: Read-only. User permissions: Read-only. -#define CPU_SCS_MPU_RASR_AP_W 3 -#define CPU_SCS_MPU_RASR_AP_M 0x07000000 -#define CPU_SCS_MPU_RASR_AP_S 24 +#define CPU_SCS_MPU_RASR_AP_W 3 +#define CPU_SCS_MPU_RASR_AP_M 0x07000000 +#define CPU_SCS_MPU_RASR_AP_S 24 // Field: [21:19] TEX // // Type extension -#define CPU_SCS_MPU_RASR_TEX_W 3 -#define CPU_SCS_MPU_RASR_TEX_M 0x00380000 -#define CPU_SCS_MPU_RASR_TEX_S 19 +#define CPU_SCS_MPU_RASR_TEX_W 3 +#define CPU_SCS_MPU_RASR_TEX_M 0x00380000 +#define CPU_SCS_MPU_RASR_TEX_S 19 // Field: [18] S // // Shareable bit: // 0: Not shareable // 1: Shareable -#define CPU_SCS_MPU_RASR_S 0x00040000 -#define CPU_SCS_MPU_RASR_S_BITN 18 -#define CPU_SCS_MPU_RASR_S_M 0x00040000 -#define CPU_SCS_MPU_RASR_S_S 18 +#define CPU_SCS_MPU_RASR_S 0x00040000 +#define CPU_SCS_MPU_RASR_S_BITN 18 +#define CPU_SCS_MPU_RASR_S_M 0x00040000 +#define CPU_SCS_MPU_RASR_S_S 18 // Field: [17] C // // Cacheable bit: // 0: Not cacheable // 1: Cacheable -#define CPU_SCS_MPU_RASR_C 0x00020000 -#define CPU_SCS_MPU_RASR_C_BITN 17 -#define CPU_SCS_MPU_RASR_C_M 0x00020000 -#define CPU_SCS_MPU_RASR_C_S 17 +#define CPU_SCS_MPU_RASR_C 0x00020000 +#define CPU_SCS_MPU_RASR_C_BITN 17 +#define CPU_SCS_MPU_RASR_C_M 0x00020000 +#define CPU_SCS_MPU_RASR_C_S 17 // Field: [16] B // // Bufferable bit: // 0: Not bufferable // 1: Bufferable -#define CPU_SCS_MPU_RASR_B 0x00010000 -#define CPU_SCS_MPU_RASR_B_BITN 16 -#define CPU_SCS_MPU_RASR_B_M 0x00010000 -#define CPU_SCS_MPU_RASR_B_S 16 +#define CPU_SCS_MPU_RASR_B 0x00010000 +#define CPU_SCS_MPU_RASR_B_BITN 16 +#define CPU_SCS_MPU_RASR_B_M 0x00010000 +#define CPU_SCS_MPU_RASR_B_S 16 // Field: [15:8] SRD // @@ -4026,9 +4026,9 @@ // Setting a bit in this field disables the corresponding sub-region. Regions // are split into eight equal-sized sub-regions. Sub-regions are not supported // for region sizes of 128 bytes and less. -#define CPU_SCS_MPU_RASR_SRD_W 8 -#define CPU_SCS_MPU_RASR_SRD_M 0x0000FF00 -#define CPU_SCS_MPU_RASR_SRD_S 8 +#define CPU_SCS_MPU_RASR_SRD_W 8 +#define CPU_SCS_MPU_RASR_SRD_M 0x0000FF00 +#define CPU_SCS_MPU_RASR_SRD_S 8 // Field: [5:1] SIZE // @@ -4061,19 +4061,19 @@ // 0x1D: 1GB // 0x1E: 2GB // 0x1F: 4GB -#define CPU_SCS_MPU_RASR_SIZE_W 5 -#define CPU_SCS_MPU_RASR_SIZE_M 0x0000003E -#define CPU_SCS_MPU_RASR_SIZE_S 1 +#define CPU_SCS_MPU_RASR_SIZE_W 5 +#define CPU_SCS_MPU_RASR_SIZE_M 0x0000003E +#define CPU_SCS_MPU_RASR_SIZE_S 1 // Field: [0] ENABLE // // Region enable bit: // 0: Disable region // 1: Enable region -#define CPU_SCS_MPU_RASR_ENABLE 0x00000001 -#define CPU_SCS_MPU_RASR_ENABLE_BITN 0 -#define CPU_SCS_MPU_RASR_ENABLE_M 0x00000001 -#define CPU_SCS_MPU_RASR_ENABLE_S 0 +#define CPU_SCS_MPU_RASR_ENABLE 0x00000001 +#define CPU_SCS_MPU_RASR_ENABLE_BITN 0 +#define CPU_SCS_MPU_RASR_ENABLE_M 0x00000001 +#define CPU_SCS_MPU_RASR_ENABLE_S 0 //***************************************************************************** // @@ -4083,9 +4083,9 @@ // Field: [31:0] MPU_RBAR_A1 // // Alias for MPU_RBAR -#define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_W 32 -#define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_M 0xFFFFFFFF -#define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_S 0 +#define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_W 32 +#define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_M 0xFFFFFFFF +#define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_S 0 //***************************************************************************** // @@ -4095,9 +4095,9 @@ // Field: [31:0] MPU_RASR_A1 // // Alias for MPU_RASR -#define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_W 32 -#define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_M 0xFFFFFFFF -#define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_S 0 +#define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_W 32 +#define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_M 0xFFFFFFFF +#define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_S 0 //***************************************************************************** // @@ -4107,9 +4107,9 @@ // Field: [31:0] MPU_RBAR_A2 // // Alias for MPU_RBAR -#define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_W 32 -#define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_M 0xFFFFFFFF -#define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_S 0 +#define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_W 32 +#define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_M 0xFFFFFFFF +#define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_S 0 //***************************************************************************** // @@ -4119,9 +4119,9 @@ // Field: [31:0] MPU_RASR_A2 // // Alias for MPU_RASR -#define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_W 32 -#define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_M 0xFFFFFFFF -#define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_S 0 +#define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_W 32 +#define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_M 0xFFFFFFFF +#define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_S 0 //***************************************************************************** // @@ -4131,9 +4131,9 @@ // Field: [31:0] MPU_RBAR_A3 // // Alias for MPU_RBAR -#define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_W 32 -#define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_M 0xFFFFFFFF -#define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_S 0 +#define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_W 32 +#define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_M 0xFFFFFFFF +#define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_S 0 //***************************************************************************** // @@ -4143,9 +4143,9 @@ // Field: [31:0] MPU_RASR_A3 // // Alias for MPU_RASR -#define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_W 32 -#define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_M 0xFFFFFFFF -#define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_S 0 +#define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_W 32 +#define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_M 0xFFFFFFFF +#define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_S 0 //***************************************************************************** // @@ -4161,10 +4161,10 @@ // reset still). // When writing to this register, 0 must be written this bit-field, otherwise // the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_RESET_ST 0x02000000 -#define CPU_SCS_DHCSR_S_RESET_ST_BITN 25 -#define CPU_SCS_DHCSR_S_RESET_ST_M 0x02000000 -#define CPU_SCS_DHCSR_S_RESET_ST_S 25 +#define CPU_SCS_DHCSR_S_RESET_ST 0x02000000 +#define CPU_SCS_DHCSR_S_RESET_ST_BITN 25 +#define CPU_SCS_DHCSR_S_RESET_ST_M 0x02000000 +#define CPU_SCS_DHCSR_S_RESET_ST_S 25 // Field: [24] S_RETIRE_ST // @@ -4173,10 +4173,10 @@ // load/store or fetch. // When writing to this register, 0 must be written this bit-field, otherwise // the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_RETIRE_ST 0x01000000 -#define CPU_SCS_DHCSR_S_RETIRE_ST_BITN 24 -#define CPU_SCS_DHCSR_S_RETIRE_ST_M 0x01000000 -#define CPU_SCS_DHCSR_S_RETIRE_ST_S 24 +#define CPU_SCS_DHCSR_S_RETIRE_ST 0x01000000 +#define CPU_SCS_DHCSR_S_RETIRE_ST_BITN 24 +#define CPU_SCS_DHCSR_S_RETIRE_ST_M 0x01000000 +#define CPU_SCS_DHCSR_S_RETIRE_ST_S 24 // Field: [19] S_LOCKUP // @@ -4184,10 +4184,10 @@ // present. // When writing to this register, 1 must be written this bit-field, otherwise // the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_LOCKUP 0x00080000 -#define CPU_SCS_DHCSR_S_LOCKUP_BITN 19 -#define CPU_SCS_DHCSR_S_LOCKUP_M 0x00080000 -#define CPU_SCS_DHCSR_S_LOCKUP_S 19 +#define CPU_SCS_DHCSR_S_LOCKUP 0x00080000 +#define CPU_SCS_DHCSR_S_LOCKUP_BITN 19 +#define CPU_SCS_DHCSR_S_LOCKUP_M 0x00080000 +#define CPU_SCS_DHCSR_S_LOCKUP_S 19 // Field: [18] S_SLEEP // @@ -4195,20 +4195,20 @@ // use C_HALT to gain control or wait for interrupt to wake-up. // When writing to this register, 1 must be written this bit-field, otherwise // the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_SLEEP 0x00040000 -#define CPU_SCS_DHCSR_S_SLEEP_BITN 18 -#define CPU_SCS_DHCSR_S_SLEEP_M 0x00040000 -#define CPU_SCS_DHCSR_S_SLEEP_S 18 +#define CPU_SCS_DHCSR_S_SLEEP 0x00040000 +#define CPU_SCS_DHCSR_S_SLEEP_BITN 18 +#define CPU_SCS_DHCSR_S_SLEEP_M 0x00040000 +#define CPU_SCS_DHCSR_S_SLEEP_S 18 // Field: [17] S_HALT // // The core is in debug state when this bit is set. // When writing to this register, 1 must be written this bit-field, otherwise // the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_HALT 0x00020000 -#define CPU_SCS_DHCSR_S_HALT_BITN 17 -#define CPU_SCS_DHCSR_S_HALT_M 0x00020000 -#define CPU_SCS_DHCSR_S_HALT_S 17 +#define CPU_SCS_DHCSR_S_HALT 0x00020000 +#define CPU_SCS_DHCSR_S_HALT_BITN 17 +#define CPU_SCS_DHCSR_S_HALT_M 0x00020000 +#define CPU_SCS_DHCSR_S_HALT_S 17 // Field: [16] S_REGRDY // @@ -4216,10 +4216,10 @@ // available. Last transfer is complete. // When writing to this register, 1 must be written this bit-field, otherwise // the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_REGRDY 0x00010000 -#define CPU_SCS_DHCSR_S_REGRDY_BITN 16 -#define CPU_SCS_DHCSR_S_REGRDY_M 0x00010000 -#define CPU_SCS_DHCSR_S_REGRDY_S 16 +#define CPU_SCS_DHCSR_S_REGRDY 0x00010000 +#define CPU_SCS_DHCSR_S_REGRDY_BITN 16 +#define CPU_SCS_DHCSR_S_REGRDY_M 0x00010000 +#define CPU_SCS_DHCSR_S_REGRDY_S 16 // Field: [5] C_SNAPSTALL // @@ -4229,10 +4229,10 @@ // The core reads S_RETIRE_ST as 0. This indicates that no instruction has // advanced. This prevents misuse. The bus state is Unpredictable when this is // used. S_RETIRE_ST can detect core stalls on load/store operations. -#define CPU_SCS_DHCSR_C_SNAPSTALL 0x00000020 -#define CPU_SCS_DHCSR_C_SNAPSTALL_BITN 5 -#define CPU_SCS_DHCSR_C_SNAPSTALL_M 0x00000020 -#define CPU_SCS_DHCSR_C_SNAPSTALL_S 5 +#define CPU_SCS_DHCSR_C_SNAPSTALL 0x00000020 +#define CPU_SCS_DHCSR_C_SNAPSTALL_BITN 5 +#define CPU_SCS_DHCSR_C_SNAPSTALL_M 0x00000020 +#define CPU_SCS_DHCSR_C_SNAPSTALL_S 5 // Field: [3] C_MASKINTS // @@ -4244,10 +4244,10 @@ // be separate). Modifying C_MASKINTS while the system is running with halting // debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable // behavior. -#define CPU_SCS_DHCSR_C_MASKINTS 0x00000008 -#define CPU_SCS_DHCSR_C_MASKINTS_BITN 3 -#define CPU_SCS_DHCSR_C_MASKINTS_M 0x00000008 -#define CPU_SCS_DHCSR_C_MASKINTS_S 3 +#define CPU_SCS_DHCSR_C_MASKINTS 0x00000008 +#define CPU_SCS_DHCSR_C_MASKINTS_BITN 3 +#define CPU_SCS_DHCSR_C_MASKINTS_M 0x00000008 +#define CPU_SCS_DHCSR_C_MASKINTS_S 3 // Field: [2] C_STEP // @@ -4255,19 +4255,19 @@ // Must only be modified when the processor is halted (S_HALT == 1). // Modifying C_STEP while the system is running with halting debug support // enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior. -#define CPU_SCS_DHCSR_C_STEP 0x00000004 -#define CPU_SCS_DHCSR_C_STEP_BITN 2 -#define CPU_SCS_DHCSR_C_STEP_M 0x00000004 -#define CPU_SCS_DHCSR_C_STEP_S 2 +#define CPU_SCS_DHCSR_C_STEP 0x00000004 +#define CPU_SCS_DHCSR_C_STEP_BITN 2 +#define CPU_SCS_DHCSR_C_STEP_M 0x00000004 +#define CPU_SCS_DHCSR_C_STEP_S 2 // Field: [1] C_HALT // // Halts the core. This bit is set automatically when the core Halts. For // example Breakpoint. This bit clears on core reset. -#define CPU_SCS_DHCSR_C_HALT 0x00000002 -#define CPU_SCS_DHCSR_C_HALT_BITN 1 -#define CPU_SCS_DHCSR_C_HALT_M 0x00000002 -#define CPU_SCS_DHCSR_C_HALT_S 1 +#define CPU_SCS_DHCSR_C_HALT 0x00000002 +#define CPU_SCS_DHCSR_C_HALT_BITN 1 +#define CPU_SCS_DHCSR_C_HALT_M 0x00000002 +#define CPU_SCS_DHCSR_C_HALT_S 1 // Field: [0] C_DEBUGEN // @@ -4277,10 +4277,10 @@ // The values of C_HALT, C_STEP and C_MASKINTS are ignored by hardware when // C_DEBUGEN = 0. The read values for C_HALT, C_STEP and C_MASKINTS fields will // be unknown to software when C_DEBUGEN = 0. -#define CPU_SCS_DHCSR_C_DEBUGEN 0x00000001 -#define CPU_SCS_DHCSR_C_DEBUGEN_BITN 0 -#define CPU_SCS_DHCSR_C_DEBUGEN_M 0x00000001 -#define CPU_SCS_DHCSR_C_DEBUGEN_S 0 +#define CPU_SCS_DHCSR_C_DEBUGEN 0x00000001 +#define CPU_SCS_DHCSR_C_DEBUGEN_BITN 0 +#define CPU_SCS_DHCSR_C_DEBUGEN_M 0x00000001 +#define CPU_SCS_DHCSR_C_DEBUGEN_S 0 //***************************************************************************** // @@ -4291,10 +4291,10 @@ // // 1: Write // 0: Read -#define CPU_SCS_DCRSR_REGWNR 0x00010000 -#define CPU_SCS_DCRSR_REGWNR_BITN 16 -#define CPU_SCS_DCRSR_REGWNR_M 0x00010000 -#define CPU_SCS_DCRSR_REGWNR_S 16 +#define CPU_SCS_DCRSR_REGWNR 0x00010000 +#define CPU_SCS_DCRSR_REGWNR_BITN 16 +#define CPU_SCS_DCRSR_REGWNR_M 0x00010000 +#define CPU_SCS_DCRSR_REGWNR_S 16 // Field: [4:0] REGSEL // @@ -4320,9 +4320,9 @@ // 0x11: MSP (Main SP) // 0x12: PSP (Process SP) // 0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 | PRIMASK -#define CPU_SCS_DCRSR_REGSEL_W 5 -#define CPU_SCS_DCRSR_REGSEL_M 0x0000001F -#define CPU_SCS_DCRSR_REGSEL_S 0 +#define CPU_SCS_DCRSR_REGSEL_W 5 +#define CPU_SCS_DCRSR_REGSEL_M 0x0000001F +#define CPU_SCS_DCRSR_REGSEL_S 0 //***************************************************************************** // @@ -4339,9 +4339,9 @@ // can use this register for communication in non-halting debug. This enables // flags and bits to acknowledge state and indicate if commands have been // accepted to, replied to, or accepted and replied to. -#define CPU_SCS_DCRDR_DCRDR_W 32 -#define CPU_SCS_DCRDR_DCRDR_M 0xFFFFFFFF -#define CPU_SCS_DCRDR_DCRDR_S 0 +#define CPU_SCS_DCRDR_DCRDR_W 32 +#define CPU_SCS_DCRDR_DCRDR_M 0xFFFFFFFF +#define CPU_SCS_DCRDR_DCRDR_S 0 //***************************************************************************** // @@ -4354,10 +4354,10 @@ // ITM, ETM and TPIU. This enables control of power usage unless tracing is // required. The application can enable this, for ITM use, or use by a // debugger. -#define CPU_SCS_DEMCR_TRCENA 0x01000000 -#define CPU_SCS_DEMCR_TRCENA_BITN 24 -#define CPU_SCS_DEMCR_TRCENA_M 0x01000000 -#define CPU_SCS_DEMCR_TRCENA_S 24 +#define CPU_SCS_DEMCR_TRCENA 0x01000000 +#define CPU_SCS_DEMCR_TRCENA_BITN 24 +#define CPU_SCS_DEMCR_TRCENA_M 0x01000000 +#define CPU_SCS_DEMCR_TRCENA_S 24 // Field: [19] MON_REQ // @@ -4366,10 +4366,10 @@ // // 0x0: Woken up by debug exception. // 0x1: Woken up by MON_PEND -#define CPU_SCS_DEMCR_MON_REQ 0x00080000 -#define CPU_SCS_DEMCR_MON_REQ_BITN 19 -#define CPU_SCS_DEMCR_MON_REQ_M 0x00080000 -#define CPU_SCS_DEMCR_MON_REQ_S 19 +#define CPU_SCS_DEMCR_MON_REQ 0x00080000 +#define CPU_SCS_DEMCR_MON_REQ_BITN 19 +#define CPU_SCS_DEMCR_MON_REQ_M 0x00080000 +#define CPU_SCS_DEMCR_MON_REQ_S 19 // Field: [18] MON_STEP // @@ -4377,10 +4377,10 @@ // This is the equivalent to DHCSR.C_STEP. Interrupts are only stepped // according to the priority of the monitor and settings of PRIMASK, FAULTMASK, // or BASEPRI. -#define CPU_SCS_DEMCR_MON_STEP 0x00040000 -#define CPU_SCS_DEMCR_MON_STEP_BITN 18 -#define CPU_SCS_DEMCR_MON_STEP_M 0x00040000 -#define CPU_SCS_DEMCR_MON_STEP_S 18 +#define CPU_SCS_DEMCR_MON_STEP 0x00040000 +#define CPU_SCS_DEMCR_MON_STEP_BITN 18 +#define CPU_SCS_DEMCR_MON_STEP_M 0x00040000 +#define CPU_SCS_DEMCR_MON_STEP_S 18 // Field: [17] MON_PEND // @@ -4389,10 +4389,10 @@ // Monitor debug. This register does not reset on a system reset. It is only // reset by a power-on reset. Software in the reset handler or later, or by the // DAP must enable the debug monitor. -#define CPU_SCS_DEMCR_MON_PEND 0x00020000 -#define CPU_SCS_DEMCR_MON_PEND_BITN 17 -#define CPU_SCS_DEMCR_MON_PEND_M 0x00020000 -#define CPU_SCS_DEMCR_MON_PEND_S 17 +#define CPU_SCS_DEMCR_MON_PEND 0x00020000 +#define CPU_SCS_DEMCR_MON_PEND_BITN 17 +#define CPU_SCS_DEMCR_MON_PEND_M 0x00020000 +#define CPU_SCS_DEMCR_MON_PEND_S 17 // Field: [16] MON_EN // @@ -4409,80 +4409,80 @@ // push. 2. If a late arriving interrupt comes in during vectoring, it is not // taken. That is, an implementation that supports the late arrival // optimization must suppress it in this case. -#define CPU_SCS_DEMCR_MON_EN 0x00010000 -#define CPU_SCS_DEMCR_MON_EN_BITN 16 -#define CPU_SCS_DEMCR_MON_EN_M 0x00010000 -#define CPU_SCS_DEMCR_MON_EN_S 16 +#define CPU_SCS_DEMCR_MON_EN 0x00010000 +#define CPU_SCS_DEMCR_MON_EN_BITN 16 +#define CPU_SCS_DEMCR_MON_EN_M 0x00010000 +#define CPU_SCS_DEMCR_MON_EN_S 16 // Field: [10] VC_HARDERR // // Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_HARDERR 0x00000400 -#define CPU_SCS_DEMCR_VC_HARDERR_BITN 10 -#define CPU_SCS_DEMCR_VC_HARDERR_M 0x00000400 -#define CPU_SCS_DEMCR_VC_HARDERR_S 10 +#define CPU_SCS_DEMCR_VC_HARDERR 0x00000400 +#define CPU_SCS_DEMCR_VC_HARDERR_BITN 10 +#define CPU_SCS_DEMCR_VC_HARDERR_M 0x00000400 +#define CPU_SCS_DEMCR_VC_HARDERR_S 10 // Field: [9] VC_INTERR // // Debug trap on a fault occurring during an exception entry or return // sequence. Ignored when DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_INTERR 0x00000200 -#define CPU_SCS_DEMCR_VC_INTERR_BITN 9 -#define CPU_SCS_DEMCR_VC_INTERR_M 0x00000200 -#define CPU_SCS_DEMCR_VC_INTERR_S 9 +#define CPU_SCS_DEMCR_VC_INTERR 0x00000200 +#define CPU_SCS_DEMCR_VC_INTERR_BITN 9 +#define CPU_SCS_DEMCR_VC_INTERR_M 0x00000200 +#define CPU_SCS_DEMCR_VC_INTERR_S 9 // Field: [8] VC_BUSERR // // Debug Trap on normal Bus error. Ignored when DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_BUSERR 0x00000100 -#define CPU_SCS_DEMCR_VC_BUSERR_BITN 8 -#define CPU_SCS_DEMCR_VC_BUSERR_M 0x00000100 -#define CPU_SCS_DEMCR_VC_BUSERR_S 8 +#define CPU_SCS_DEMCR_VC_BUSERR 0x00000100 +#define CPU_SCS_DEMCR_VC_BUSERR_BITN 8 +#define CPU_SCS_DEMCR_VC_BUSERR_M 0x00000100 +#define CPU_SCS_DEMCR_VC_BUSERR_S 8 // Field: [7] VC_STATERR // // Debug trap on Usage Fault state errors. Ignored when DHCSR.C_DEBUGEN is // cleared. -#define CPU_SCS_DEMCR_VC_STATERR 0x00000080 -#define CPU_SCS_DEMCR_VC_STATERR_BITN 7 -#define CPU_SCS_DEMCR_VC_STATERR_M 0x00000080 -#define CPU_SCS_DEMCR_VC_STATERR_S 7 +#define CPU_SCS_DEMCR_VC_STATERR 0x00000080 +#define CPU_SCS_DEMCR_VC_STATERR_BITN 7 +#define CPU_SCS_DEMCR_VC_STATERR_M 0x00000080 +#define CPU_SCS_DEMCR_VC_STATERR_S 7 // Field: [6] VC_CHKERR // // Debug trap on Usage Fault enabled checking errors. Ignored when // DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_CHKERR 0x00000040 -#define CPU_SCS_DEMCR_VC_CHKERR_BITN 6 -#define CPU_SCS_DEMCR_VC_CHKERR_M 0x00000040 -#define CPU_SCS_DEMCR_VC_CHKERR_S 6 +#define CPU_SCS_DEMCR_VC_CHKERR 0x00000040 +#define CPU_SCS_DEMCR_VC_CHKERR_BITN 6 +#define CPU_SCS_DEMCR_VC_CHKERR_M 0x00000040 +#define CPU_SCS_DEMCR_VC_CHKERR_S 6 // Field: [5] VC_NOCPERR // // Debug trap on a UsageFault access to a Coprocessor. Ignored when // DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_NOCPERR 0x00000020 -#define CPU_SCS_DEMCR_VC_NOCPERR_BITN 5 -#define CPU_SCS_DEMCR_VC_NOCPERR_M 0x00000020 -#define CPU_SCS_DEMCR_VC_NOCPERR_S 5 +#define CPU_SCS_DEMCR_VC_NOCPERR 0x00000020 +#define CPU_SCS_DEMCR_VC_NOCPERR_BITN 5 +#define CPU_SCS_DEMCR_VC_NOCPERR_M 0x00000020 +#define CPU_SCS_DEMCR_VC_NOCPERR_S 5 // Field: [4] VC_MMERR // // Debug trap on Memory Management faults. Ignored when DHCSR.C_DEBUGEN is // cleared. -#define CPU_SCS_DEMCR_VC_MMERR 0x00000010 -#define CPU_SCS_DEMCR_VC_MMERR_BITN 4 -#define CPU_SCS_DEMCR_VC_MMERR_M 0x00000010 -#define CPU_SCS_DEMCR_VC_MMERR_S 4 +#define CPU_SCS_DEMCR_VC_MMERR 0x00000010 +#define CPU_SCS_DEMCR_VC_MMERR_BITN 4 +#define CPU_SCS_DEMCR_VC_MMERR_M 0x00000010 +#define CPU_SCS_DEMCR_VC_MMERR_S 4 // Field: [0] VC_CORERESET // // Reset Vector Catch. Halt running system if Core reset occurs. Ignored when // DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_CORERESET 0x00000001 -#define CPU_SCS_DEMCR_VC_CORERESET_BITN 0 -#define CPU_SCS_DEMCR_VC_CORERESET_M 0x00000001 -#define CPU_SCS_DEMCR_VC_CORERESET_S 0 +#define CPU_SCS_DEMCR_VC_CORERESET 0x00000001 +#define CPU_SCS_DEMCR_VC_CORERESET_BITN 0 +#define CPU_SCS_DEMCR_VC_CORERESET_M 0x00000001 +#define CPU_SCS_DEMCR_VC_CORERESET_S 0 //***************************************************************************** // @@ -4494,9 +4494,9 @@ // Interrupt ID field. Writing a value to this bit-field is the same as // manually pending an interrupt by setting the corresponding interrupt bit in // an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1. -#define CPU_SCS_STIR_INTID_W 9 -#define CPU_SCS_STIR_INTID_M 0x000001FF -#define CPU_SCS_STIR_INTID_S 0 +#define CPU_SCS_STIR_INTID_W 9 +#define CPU_SCS_STIR_INTID_M 0x000001FF +#define CPU_SCS_STIR_INTID_S 0 //***************************************************************************** // @@ -4510,10 +4510,10 @@ // to be set (FPCA) on execution of a floating point instruction which results // in the floating point state automatically being preserved on exception // entry. -#define CPU_SCS_FPCCR_ASPEN 0x80000000 -#define CPU_SCS_FPCCR_ASPEN_BITN 31 -#define CPU_SCS_FPCCR_ASPEN_M 0x80000000 -#define CPU_SCS_FPCCR_ASPEN_S 31 +#define CPU_SCS_FPCCR_ASPEN 0x80000000 +#define CPU_SCS_FPCCR_ASPEN_BITN 31 +#define CPU_SCS_FPCCR_ASPEN_M 0x80000000 +#define CPU_SCS_FPCCR_ASPEN_S 31 // Field: [30] LSPEN // @@ -4523,10 +4523,10 @@ // until the new context performs a floating point operation. // 0: Disable automatic lazy state preservation for floating-point context. // 1: Enable automatic lazy state preservation for floating-point context. -#define CPU_SCS_FPCCR_LSPEN 0x40000000 -#define CPU_SCS_FPCCR_LSPEN_BITN 30 -#define CPU_SCS_FPCCR_LSPEN_M 0x40000000 -#define CPU_SCS_FPCCR_LSPEN_S 30 +#define CPU_SCS_FPCCR_LSPEN 0x40000000 +#define CPU_SCS_FPCCR_LSPEN_BITN 30 +#define CPU_SCS_FPCCR_LSPEN_M 0x40000000 +#define CPU_SCS_FPCCR_LSPEN_S 30 // Field: [8] MONRDY // @@ -4536,10 +4536,10 @@ // DEMCR.MON_PEND when the floating-point stack frame was allocated. // 1: DebugMonitor is enabled and priority permits setting DEMCR.MON_PEND when // the floating-point stack frame was allocated. -#define CPU_SCS_FPCCR_MONRDY 0x00000100 -#define CPU_SCS_FPCCR_MONRDY_BITN 8 -#define CPU_SCS_FPCCR_MONRDY_M 0x00000100 -#define CPU_SCS_FPCCR_MONRDY_S 8 +#define CPU_SCS_FPCCR_MONRDY 0x00000100 +#define CPU_SCS_FPCCR_MONRDY_BITN 8 +#define CPU_SCS_FPCCR_MONRDY_M 0x00000100 +#define CPU_SCS_FPCCR_MONRDY_S 8 // Field: [6] BFRDY // @@ -4550,10 +4550,10 @@ // allocated. // 1: BusFault is enabled and priority permitted setting the BusFault handler // to the pending state when the floating-point stack frame was allocated. -#define CPU_SCS_FPCCR_BFRDY 0x00000040 -#define CPU_SCS_FPCCR_BFRDY_BITN 6 -#define CPU_SCS_FPCCR_BFRDY_M 0x00000040 -#define CPU_SCS_FPCCR_BFRDY_S 6 +#define CPU_SCS_FPCCR_BFRDY 0x00000040 +#define CPU_SCS_FPCCR_BFRDY_BITN 6 +#define CPU_SCS_FPCCR_BFRDY_M 0x00000040 +#define CPU_SCS_FPCCR_BFRDY_S 6 // Field: [5] MMRDY // @@ -4564,10 +4564,10 @@ // allocated. // 1: MemManage is enabled and priority permitted setting the MemManage handler // to the pending state when the floating-point stack frame was allocated. -#define CPU_SCS_FPCCR_MMRDY 0x00000020 -#define CPU_SCS_FPCCR_MMRDY_BITN 5 -#define CPU_SCS_FPCCR_MMRDY_M 0x00000020 -#define CPU_SCS_FPCCR_MMRDY_S 5 +#define CPU_SCS_FPCCR_MMRDY 0x00000020 +#define CPU_SCS_FPCCR_MMRDY_BITN 5 +#define CPU_SCS_FPCCR_MMRDY_M 0x00000020 +#define CPU_SCS_FPCCR_MMRDY_S 5 // Field: [4] HFRDY // @@ -4577,10 +4577,10 @@ // state when the floating-point stack frame was allocated. // 1: Priority permitted setting the HardFault handler to the pending state // when the floating-point stack frame was allocated. -#define CPU_SCS_FPCCR_HFRDY 0x00000010 -#define CPU_SCS_FPCCR_HFRDY_BITN 4 -#define CPU_SCS_FPCCR_HFRDY_M 0x00000010 -#define CPU_SCS_FPCCR_HFRDY_S 4 +#define CPU_SCS_FPCCR_HFRDY 0x00000010 +#define CPU_SCS_FPCCR_HFRDY_BITN 4 +#define CPU_SCS_FPCCR_HFRDY_M 0x00000010 +#define CPU_SCS_FPCCR_HFRDY_S 4 // Field: [3] THREAD // @@ -4589,10 +4589,10 @@ // 0: Mode was not Thread Mode when the floating-point stack frame was // allocated. // 1: Mode was Thread Mode when the floating-point stack frame was allocated. -#define CPU_SCS_FPCCR_THREAD 0x00000008 -#define CPU_SCS_FPCCR_THREAD_BITN 3 -#define CPU_SCS_FPCCR_THREAD_M 0x00000008 -#define CPU_SCS_FPCCR_THREAD_S 3 +#define CPU_SCS_FPCCR_THREAD 0x00000008 +#define CPU_SCS_FPCCR_THREAD_BITN 3 +#define CPU_SCS_FPCCR_THREAD_M 0x00000008 +#define CPU_SCS_FPCCR_THREAD_S 3 // Field: [1] USER // @@ -4602,10 +4602,10 @@ // allocated. // 1: Privilege level was user when the floating-point stack frame was // allocated. -#define CPU_SCS_FPCCR_USER 0x00000002 -#define CPU_SCS_FPCCR_USER_BITN 1 -#define CPU_SCS_FPCCR_USER_M 0x00000002 -#define CPU_SCS_FPCCR_USER_S 1 +#define CPU_SCS_FPCCR_USER 0x00000002 +#define CPU_SCS_FPCCR_USER_BITN 1 +#define CPU_SCS_FPCCR_USER_M 0x00000002 +#define CPU_SCS_FPCCR_USER_S 1 // Field: [0] LSPACT // @@ -4613,10 +4613,10 @@ // 0: Lazy state preservation is not active. // 1: Lazy state preservation is active. floating-point stack frame has been // allocated but saving state to it has been deferred. -#define CPU_SCS_FPCCR_LSPACT 0x00000001 -#define CPU_SCS_FPCCR_LSPACT_BITN 0 -#define CPU_SCS_FPCCR_LSPACT_M 0x00000001 -#define CPU_SCS_FPCCR_LSPACT_S 0 +#define CPU_SCS_FPCCR_LSPACT 0x00000001 +#define CPU_SCS_FPCCR_LSPACT_BITN 0 +#define CPU_SCS_FPCCR_LSPACT_M 0x00000001 +#define CPU_SCS_FPCCR_LSPACT_S 0 //***************************************************************************** // @@ -4627,9 +4627,9 @@ // // Holds the (double-word-aligned) location of the unpopulated floating-point // register space allocated on an exception stack frame. -#define CPU_SCS_FPCAR_ADDRESS_W 30 -#define CPU_SCS_FPCAR_ADDRESS_M 0xFFFFFFFC -#define CPU_SCS_FPCAR_ADDRESS_S 2 +#define CPU_SCS_FPCAR_ADDRESS_W 30 +#define CPU_SCS_FPCAR_ADDRESS_M 0xFFFFFFFC +#define CPU_SCS_FPCAR_ADDRESS_S 2 //***************************************************************************** // @@ -4640,28 +4640,28 @@ // // Default value for Alternative Half Precision bit. (If this bit is set to 1 // then Alternative half-precision format is selected). -#define CPU_SCS_FPDSCR_AHP 0x04000000 -#define CPU_SCS_FPDSCR_AHP_BITN 26 -#define CPU_SCS_FPDSCR_AHP_M 0x04000000 -#define CPU_SCS_FPDSCR_AHP_S 26 +#define CPU_SCS_FPDSCR_AHP 0x04000000 +#define CPU_SCS_FPDSCR_AHP_BITN 26 +#define CPU_SCS_FPDSCR_AHP_M 0x04000000 +#define CPU_SCS_FPDSCR_AHP_S 26 // Field: [25] DN // // Default value for Default NaN mode bit. (If this bit is set to 1 then any // operation involving one or more NaNs returns the Default NaN). -#define CPU_SCS_FPDSCR_DN 0x02000000 -#define CPU_SCS_FPDSCR_DN_BITN 25 -#define CPU_SCS_FPDSCR_DN_M 0x02000000 -#define CPU_SCS_FPDSCR_DN_S 25 +#define CPU_SCS_FPDSCR_DN 0x02000000 +#define CPU_SCS_FPDSCR_DN_BITN 25 +#define CPU_SCS_FPDSCR_DN_M 0x02000000 +#define CPU_SCS_FPDSCR_DN_S 25 // Field: [24] FZ // // Default value for Flush-to-Zero mode bit. (If this bit is set to 1 then // Flush-to-zero mode is enabled). -#define CPU_SCS_FPDSCR_FZ 0x01000000 -#define CPU_SCS_FPDSCR_FZ_BITN 24 -#define CPU_SCS_FPDSCR_FZ_M 0x01000000 -#define CPU_SCS_FPDSCR_FZ_S 24 +#define CPU_SCS_FPDSCR_FZ 0x01000000 +#define CPU_SCS_FPDSCR_FZ_BITN 24 +#define CPU_SCS_FPDSCR_FZ_M 0x01000000 +#define CPU_SCS_FPDSCR_FZ_S 24 // Field: [23:22] RMODE // @@ -4673,9 +4673,9 @@ // 0b11 Round towards Zero (RZ) mode. // The specified rounding mode is used by almost all floating-point // instructions). -#define CPU_SCS_FPDSCR_RMODE_W 2 -#define CPU_SCS_FPDSCR_RMODE_M 0x00C00000 -#define CPU_SCS_FPDSCR_RMODE_S 22 +#define CPU_SCS_FPDSCR_RMODE_W 2 +#define CPU_SCS_FPDSCR_RMODE_M 0x00C00000 +#define CPU_SCS_FPDSCR_RMODE_S 22 //***************************************************************************** // @@ -4686,65 +4686,65 @@ // // Indicates the rounding modes supported by the FP floating-point hardware. // The value of this field is: 0b0001 - all rounding modes supported. -#define CPU_SCS_MVFR0_FP_ROUNDING_MODES_W 4 -#define CPU_SCS_MVFR0_FP_ROUNDING_MODES_M 0xF0000000 -#define CPU_SCS_MVFR0_FP_ROUNDING_MODES_S 28 +#define CPU_SCS_MVFR0_FP_ROUNDING_MODES_W 4 +#define CPU_SCS_MVFR0_FP_ROUNDING_MODES_M 0xF0000000 +#define CPU_SCS_MVFR0_FP_ROUNDING_MODES_S 28 // Field: [27:24] SHORT_VECTORS // // Indicates the hardware support for FP short vectors. The value of this field // is: 0b0000 - not supported. -#define CPU_SCS_MVFR0_SHORT_VECTORS_W 4 -#define CPU_SCS_MVFR0_SHORT_VECTORS_M 0x0F000000 -#define CPU_SCS_MVFR0_SHORT_VECTORS_S 24 +#define CPU_SCS_MVFR0_SHORT_VECTORS_W 4 +#define CPU_SCS_MVFR0_SHORT_VECTORS_M 0x0F000000 +#define CPU_SCS_MVFR0_SHORT_VECTORS_S 24 // Field: [23:20] SQUARE_ROOT // // Indicates the hardware support for FP square root operations. The value of // this field is: 0b0001 - supported. -#define CPU_SCS_MVFR0_SQUARE_ROOT_W 4 -#define CPU_SCS_MVFR0_SQUARE_ROOT_M 0x00F00000 -#define CPU_SCS_MVFR0_SQUARE_ROOT_S 20 +#define CPU_SCS_MVFR0_SQUARE_ROOT_W 4 +#define CPU_SCS_MVFR0_SQUARE_ROOT_M 0x00F00000 +#define CPU_SCS_MVFR0_SQUARE_ROOT_S 20 // Field: [19:16] DIVIDE // // Indicates the hardware support for FP divide operations. The value of this // field is: 0b0001 - supported. -#define CPU_SCS_MVFR0_DIVIDE_W 4 -#define CPU_SCS_MVFR0_DIVIDE_M 0x000F0000 -#define CPU_SCS_MVFR0_DIVIDE_S 16 +#define CPU_SCS_MVFR0_DIVIDE_W 4 +#define CPU_SCS_MVFR0_DIVIDE_M 0x000F0000 +#define CPU_SCS_MVFR0_DIVIDE_S 16 // Field: [15:12] FP_EXCEPTION_TRAPPING // // Indicates whether the FP hardware implementation supports exception // trapping. The value of this field is: 0b0000 - not supported. -#define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_W 4 -#define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_M 0x0000F000 -#define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_S 12 +#define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_W 4 +#define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_M 0x0000F000 +#define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_S 12 // Field: [11:8] DOUBLE_PRECISION // // Indicates the hardware support for FP double-precision operations. The value // of this field is: 0b0000 - not supported. -#define CPU_SCS_MVFR0_DOUBLE_PRECISION_W 4 -#define CPU_SCS_MVFR0_DOUBLE_PRECISION_M 0x00000F00 -#define CPU_SCS_MVFR0_DOUBLE_PRECISION_S 8 +#define CPU_SCS_MVFR0_DOUBLE_PRECISION_W 4 +#define CPU_SCS_MVFR0_DOUBLE_PRECISION_M 0x00000F00 +#define CPU_SCS_MVFR0_DOUBLE_PRECISION_S 8 // Field: [7:4] SINGLE_PRECISION // // Indicates the hardware support for FP single-precision operations. The value // of this field is: 0b0010 - supported. -#define CPU_SCS_MVFR0_SINGLE_PRECISION_W 4 -#define CPU_SCS_MVFR0_SINGLE_PRECISION_M 0x000000F0 -#define CPU_SCS_MVFR0_SINGLE_PRECISION_S 4 +#define CPU_SCS_MVFR0_SINGLE_PRECISION_W 4 +#define CPU_SCS_MVFR0_SINGLE_PRECISION_M 0x000000F0 +#define CPU_SCS_MVFR0_SINGLE_PRECISION_S 4 // Field: [3:0] A_SIMD // // Indicates the size of the FP register bank. The value of this field is: // 0b0001 - supported, 16 x 64-bit registers. -#define CPU_SCS_MVFR0_A_SIMD_W 4 -#define CPU_SCS_MVFR0_A_SIMD_M 0x0000000F -#define CPU_SCS_MVFR0_A_SIMD_S 0 +#define CPU_SCS_MVFR0_A_SIMD_W 4 +#define CPU_SCS_MVFR0_A_SIMD_M 0x0000000F +#define CPU_SCS_MVFR0_A_SIMD_S 0 //***************************************************************************** // @@ -4755,35 +4755,34 @@ // // Indicates whether the FP supports fused multiply accumulate operations. The // value of this field is: 0b0001 - supported. -#define CPU_SCS_MVFR1_FP_FUSED_MAC_W 4 -#define CPU_SCS_MVFR1_FP_FUSED_MAC_M 0xF0000000 -#define CPU_SCS_MVFR1_FP_FUSED_MAC_S 28 +#define CPU_SCS_MVFR1_FP_FUSED_MAC_W 4 +#define CPU_SCS_MVFR1_FP_FUSED_MAC_M 0xF0000000 +#define CPU_SCS_MVFR1_FP_FUSED_MAC_S 28 // Field: [27:24] FP_HPFP // // Indicates whether the FP supports half-precision floating-point conversion // operations. The value of this field is: 0b0001 - supported. -#define CPU_SCS_MVFR1_FP_HPFP_W 4 -#define CPU_SCS_MVFR1_FP_HPFP_M 0x0F000000 -#define CPU_SCS_MVFR1_FP_HPFP_S 24 +#define CPU_SCS_MVFR1_FP_HPFP_W 4 +#define CPU_SCS_MVFR1_FP_HPFP_M 0x0F000000 +#define CPU_SCS_MVFR1_FP_HPFP_S 24 // Field: [7:4] D_NAN_MODE // // Indicates whether the FP hardware implementation supports only the Default // NaN mode. The value of this field is: 0b0001 - hardware supports propagation // of NaN values. -#define CPU_SCS_MVFR1_D_NAN_MODE_W 4 -#define CPU_SCS_MVFR1_D_NAN_MODE_M 0x000000F0 -#define CPU_SCS_MVFR1_D_NAN_MODE_S 4 +#define CPU_SCS_MVFR1_D_NAN_MODE_W 4 +#define CPU_SCS_MVFR1_D_NAN_MODE_M 0x000000F0 +#define CPU_SCS_MVFR1_D_NAN_MODE_S 4 // Field: [3:0] FTZ_MODE // // Indicates whether the FP hardware implementation supports only the // Flush-to-Zero mode of operation. The value of this field is: 0b0001 - // hardware supports full denormalized number arithmetic. -#define CPU_SCS_MVFR1_FTZ_MODE_W 4 -#define CPU_SCS_MVFR1_FTZ_MODE_M 0x0000000F -#define CPU_SCS_MVFR1_FTZ_MODE_S 0 - +#define CPU_SCS_MVFR1_FTZ_MODE_W 4 +#define CPU_SCS_MVFR1_FTZ_MODE_M 0x0000000F +#define CPU_SCS_MVFR1_FTZ_MODE_S 0 #endif // __CPU_SCS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tiprop.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tiprop.h index e4b89d1..161dd11 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tiprop.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tiprop.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_cpu_tiprop_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_cpu_tiprop_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CPU_TIPROP_H__ #define __HW_CPU_TIPROP_H__ @@ -44,7 +44,7 @@ // //***************************************************************************** // Internal -#define CPU_TIPROP_O_TRACECLKMUX 0x00000FF8 +#define CPU_TIPROP_O_TRACECLKMUX 0x00000FF8 //***************************************************************************** // @@ -57,12 +57,11 @@ // ENUMs: // TRACECLK Internal. Only to be used through TI provided API. // SWV Internal. Only to be used through TI provided API. -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV 0x00000001 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_BITN 0 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_M 0x00000001 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_S 0 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_TRACECLK 0x00000001 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_SWV 0x00000000 - +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_BITN 0 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_M 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_S 0 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_TRACECLK 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_SWV 0x00000000 #endif // __CPU_TIPROP__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tpiu.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tpiu.h index f95bb09..7c393a5 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tpiu.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tpiu.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_cpu_tpiu_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_cpu_tpiu_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CPU_TPIU_H__ #define __HW_CPU_TPIU_H__ @@ -44,40 +44,40 @@ // //***************************************************************************** // Supported Sync Port Sizes -#define CPU_TPIU_O_SSPSR 0x00000000 +#define CPU_TPIU_O_SSPSR 0x00000000 // Current Sync Port Size -#define CPU_TPIU_O_CSPSR 0x00000004 +#define CPU_TPIU_O_CSPSR 0x00000004 // Async Clock Prescaler -#define CPU_TPIU_O_ACPR 0x00000010 +#define CPU_TPIU_O_ACPR 0x00000010 // Selected Pin Protocol -#define CPU_TPIU_O_SPPR 0x000000F0 +#define CPU_TPIU_O_SPPR 0x000000F0 // Formatter and Flush Status -#define CPU_TPIU_O_FFSR 0x00000300 +#define CPU_TPIU_O_FFSR 0x00000300 // Formatter and Flush Control -#define CPU_TPIU_O_FFCR 0x00000304 +#define CPU_TPIU_O_FFCR 0x00000304 // Formatter Synchronization Counter -#define CPU_TPIU_O_FSCR 0x00000308 +#define CPU_TPIU_O_FSCR 0x00000308 // Claim Tag Mask -#define CPU_TPIU_O_CLAIMMASK 0x00000FA0 +#define CPU_TPIU_O_CLAIMMASK 0x00000FA0 // Claim Tag Set -#define CPU_TPIU_O_CLAIMSET 0x00000FA0 +#define CPU_TPIU_O_CLAIMSET 0x00000FA0 // Current Claim Tag -#define CPU_TPIU_O_CLAIMTAG 0x00000FA4 +#define CPU_TPIU_O_CLAIMTAG 0x00000FA4 // Claim Tag Clear -#define CPU_TPIU_O_CLAIMCLR 0x00000FA4 +#define CPU_TPIU_O_CLAIMCLR 0x00000FA4 // Device ID -#define CPU_TPIU_O_DEVID 0x00000FC8 +#define CPU_TPIU_O_DEVID 0x00000FC8 //***************************************************************************** // @@ -90,10 +90,10 @@ // // 0x0: Not supported // 0x1: Supported -#define CPU_TPIU_SSPSR_FOUR 0x00000008 -#define CPU_TPIU_SSPSR_FOUR_BITN 3 -#define CPU_TPIU_SSPSR_FOUR_M 0x00000008 -#define CPU_TPIU_SSPSR_FOUR_S 3 +#define CPU_TPIU_SSPSR_FOUR 0x00000008 +#define CPU_TPIU_SSPSR_FOUR_BITN 3 +#define CPU_TPIU_SSPSR_FOUR_M 0x00000008 +#define CPU_TPIU_SSPSR_FOUR_S 3 // Field: [2] THREE // @@ -101,10 +101,10 @@ // // 0x0: Not supported // 0x1: Supported -#define CPU_TPIU_SSPSR_THREE 0x00000004 -#define CPU_TPIU_SSPSR_THREE_BITN 2 -#define CPU_TPIU_SSPSR_THREE_M 0x00000004 -#define CPU_TPIU_SSPSR_THREE_S 2 +#define CPU_TPIU_SSPSR_THREE 0x00000004 +#define CPU_TPIU_SSPSR_THREE_BITN 2 +#define CPU_TPIU_SSPSR_THREE_M 0x00000004 +#define CPU_TPIU_SSPSR_THREE_S 2 // Field: [1] TWO // @@ -112,10 +112,10 @@ // // 0x0: Not supported // 0x1: Supported -#define CPU_TPIU_SSPSR_TWO 0x00000002 -#define CPU_TPIU_SSPSR_TWO_BITN 1 -#define CPU_TPIU_SSPSR_TWO_M 0x00000002 -#define CPU_TPIU_SSPSR_TWO_S 1 +#define CPU_TPIU_SSPSR_TWO 0x00000002 +#define CPU_TPIU_SSPSR_TWO_BITN 1 +#define CPU_TPIU_SSPSR_TWO_M 0x00000002 +#define CPU_TPIU_SSPSR_TWO_S 1 // Field: [0] ONE // @@ -123,10 +123,10 @@ // // 0x0: Not supported // 0x1: Supported -#define CPU_TPIU_SSPSR_ONE 0x00000001 -#define CPU_TPIU_SSPSR_ONE_BITN 0 -#define CPU_TPIU_SSPSR_ONE_M 0x00000001 -#define CPU_TPIU_SSPSR_ONE_S 0 +#define CPU_TPIU_SSPSR_ONE 0x00000001 +#define CPU_TPIU_SSPSR_ONE_BITN 0 +#define CPU_TPIU_SSPSR_ONE_M 0x00000001 +#define CPU_TPIU_SSPSR_ONE_S 0 //***************************************************************************** // @@ -138,40 +138,40 @@ // 4-bit port enable // Writing values with more than one bit set in CSPSR, or setting a bit that is // not indicated as supported in SSPSR can cause Unpredictable behavior. -#define CPU_TPIU_CSPSR_FOUR 0x00000008 -#define CPU_TPIU_CSPSR_FOUR_BITN 3 -#define CPU_TPIU_CSPSR_FOUR_M 0x00000008 -#define CPU_TPIU_CSPSR_FOUR_S 3 +#define CPU_TPIU_CSPSR_FOUR 0x00000008 +#define CPU_TPIU_CSPSR_FOUR_BITN 3 +#define CPU_TPIU_CSPSR_FOUR_M 0x00000008 +#define CPU_TPIU_CSPSR_FOUR_S 3 // Field: [2] THREE // // 3-bit port enable // Writing values with more than one bit set in CSPSR, or setting a bit that is // not indicated as supported in SSPSR can cause Unpredictable behavior. -#define CPU_TPIU_CSPSR_THREE 0x00000004 -#define CPU_TPIU_CSPSR_THREE_BITN 2 -#define CPU_TPIU_CSPSR_THREE_M 0x00000004 -#define CPU_TPIU_CSPSR_THREE_S 2 +#define CPU_TPIU_CSPSR_THREE 0x00000004 +#define CPU_TPIU_CSPSR_THREE_BITN 2 +#define CPU_TPIU_CSPSR_THREE_M 0x00000004 +#define CPU_TPIU_CSPSR_THREE_S 2 // Field: [1] TWO // // 2-bit port enable // Writing values with more than one bit set in CSPSR, or setting a bit that is // not indicated as supported in SSPSR can cause Unpredictable behavior. -#define CPU_TPIU_CSPSR_TWO 0x00000002 -#define CPU_TPIU_CSPSR_TWO_BITN 1 -#define CPU_TPIU_CSPSR_TWO_M 0x00000002 -#define CPU_TPIU_CSPSR_TWO_S 1 +#define CPU_TPIU_CSPSR_TWO 0x00000002 +#define CPU_TPIU_CSPSR_TWO_BITN 1 +#define CPU_TPIU_CSPSR_TWO_M 0x00000002 +#define CPU_TPIU_CSPSR_TWO_S 1 // Field: [0] ONE // // 1-bit port enable // Writing values with more than one bit set in CSPSR, or setting a bit that is // not indicated as supported in SSPSR can cause Unpredictable behavior. -#define CPU_TPIU_CSPSR_ONE 0x00000001 -#define CPU_TPIU_CSPSR_ONE_BITN 0 -#define CPU_TPIU_CSPSR_ONE_M 0x00000001 -#define CPU_TPIU_CSPSR_ONE_S 0 +#define CPU_TPIU_CSPSR_ONE 0x00000001 +#define CPU_TPIU_CSPSR_ONE_BITN 0 +#define CPU_TPIU_CSPSR_ONE_M 0x00000001 +#define CPU_TPIU_CSPSR_ONE_S 0 //***************************************************************************** // @@ -181,9 +181,9 @@ // Field: [12:0] PRESCALER // // Divisor for input trace clock is (PRESCALER + 1). -#define CPU_TPIU_ACPR_PRESCALER_W 13 -#define CPU_TPIU_ACPR_PRESCALER_M 0x00001FFF -#define CPU_TPIU_ACPR_PRESCALER_S 0 +#define CPU_TPIU_ACPR_PRESCALER_W 13 +#define CPU_TPIU_ACPR_PRESCALER_M 0x00001FFF +#define CPU_TPIU_ACPR_PRESCALER_S 0 //***************************************************************************** // @@ -198,12 +198,12 @@ // SWO_MANCHESTER SerialWire Output (Manchester). This is the reset // value. // TRACEPORT TracePort mode -#define CPU_TPIU_SPPR_PROTOCOL_W 2 -#define CPU_TPIU_SPPR_PROTOCOL_M 0x00000003 -#define CPU_TPIU_SPPR_PROTOCOL_S 0 -#define CPU_TPIU_SPPR_PROTOCOL_SWO_NRZ 0x00000002 -#define CPU_TPIU_SPPR_PROTOCOL_SWO_MANCHESTER 0x00000001 -#define CPU_TPIU_SPPR_PROTOCOL_TRACEPORT 0x00000000 +#define CPU_TPIU_SPPR_PROTOCOL_W 2 +#define CPU_TPIU_SPPR_PROTOCOL_M 0x00000003 +#define CPU_TPIU_SPPR_PROTOCOL_S 0 +#define CPU_TPIU_SPPR_PROTOCOL_SWO_NRZ 0x00000002 +#define CPU_TPIU_SPPR_PROTOCOL_SWO_MANCHESTER 0x00000001 +#define CPU_TPIU_SPPR_PROTOCOL_TRACEPORT 0x00000000 //***************************************************************************** // @@ -214,10 +214,10 @@ // // 0: Formatter can be stopped // 1: Formatter cannot be stopped -#define CPU_TPIU_FFSR_FTNONSTOP 0x00000008 -#define CPU_TPIU_FFSR_FTNONSTOP_BITN 3 -#define CPU_TPIU_FFSR_FTNONSTOP_M 0x00000008 -#define CPU_TPIU_FFSR_FTNONSTOP_S 3 +#define CPU_TPIU_FFSR_FTNONSTOP 0x00000008 +#define CPU_TPIU_FFSR_FTNONSTOP_BITN 3 +#define CPU_TPIU_FFSR_FTNONSTOP_M 0x00000008 +#define CPU_TPIU_FFSR_FTNONSTOP_S 3 //***************************************************************************** // @@ -227,10 +227,10 @@ // Field: [8] TRIGIN // // Indicates that triggers are inserted when a trigger pin is asserted. -#define CPU_TPIU_FFCR_TRIGIN 0x00000100 -#define CPU_TPIU_FFCR_TRIGIN_BITN 8 -#define CPU_TPIU_FFCR_TRIGIN_M 0x00000100 -#define CPU_TPIU_FFCR_TRIGIN_S 8 +#define CPU_TPIU_FFCR_TRIGIN 0x00000100 +#define CPU_TPIU_FFCR_TRIGIN_BITN 8 +#define CPU_TPIU_FFCR_TRIGIN_M 0x00000100 +#define CPU_TPIU_FFCR_TRIGIN_S 8 // Field: [1] ENFCONT // @@ -238,10 +238,10 @@ // // 0: Continuous formatting disabled // 1: Continuous formatting enabled -#define CPU_TPIU_FFCR_ENFCONT 0x00000002 -#define CPU_TPIU_FFCR_ENFCONT_BITN 1 -#define CPU_TPIU_FFCR_ENFCONT_M 0x00000002 -#define CPU_TPIU_FFCR_ENFCONT_S 1 +#define CPU_TPIU_FFCR_ENFCONT 0x00000002 +#define CPU_TPIU_FFCR_ENFCONT_BITN 1 +#define CPU_TPIU_FFCR_ENFCONT_M 0x00000002 +#define CPU_TPIU_FFCR_ENFCONT_S 1 //***************************************************************************** // @@ -253,9 +253,9 @@ // The global synchronization trigger is generated by the Program Counter (PC) // Sampler block. This means that there is no synchronization counter in the // TPIU. -#define CPU_TPIU_FSCR_FSCR_W 32 -#define CPU_TPIU_FSCR_FSCR_M 0xFFFFFFFF -#define CPU_TPIU_FSCR_FSCR_S 0 +#define CPU_TPIU_FSCR_FSCR_W 32 +#define CPU_TPIU_FSCR_FSCR_M 0xFFFFFFFF +#define CPU_TPIU_FSCR_FSCR_S 0 //***************************************************************************** // @@ -272,9 +272,9 @@ // 1: This claim tag bit is not implemented // // The behavior when writing to this register is described in CLAIMSET. -#define CPU_TPIU_CLAIMMASK_CLAIMMASK_W 32 -#define CPU_TPIU_CLAIMMASK_CLAIMMASK_M 0xFFFFFFFF -#define CPU_TPIU_CLAIMMASK_CLAIMMASK_S 0 +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_W 32 +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_S 0 //***************************************************************************** // @@ -291,9 +291,9 @@ // 1: Set this bit in the claim tag // // The behavior when reading from this location is described in CLAIMMASK. -#define CPU_TPIU_CLAIMSET_CLAIMSET_W 32 -#define CPU_TPIU_CLAIMSET_CLAIMSET_M 0xFFFFFFFF -#define CPU_TPIU_CLAIMSET_CLAIMSET_S 0 +#define CPU_TPIU_CLAIMSET_CLAIMSET_W 32 +#define CPU_TPIU_CLAIMSET_CLAIMSET_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMSET_CLAIMSET_S 0 //***************************************************************************** // @@ -307,9 +307,9 @@ // Reading CLAIMMASK determines how many bits from this register must be used. // // The behavior when writing to this register is described in CLAIMCLR. -#define CPU_TPIU_CLAIMTAG_CLAIMTAG_W 32 -#define CPU_TPIU_CLAIMTAG_CLAIMTAG_M 0xFFFFFFFF -#define CPU_TPIU_CLAIMTAG_CLAIMTAG_S 0 +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_W 32 +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_S 0 //***************************************************************************** // @@ -326,9 +326,9 @@ // 1: Clear this bit in the claim tag. // // The behavior when reading from this location is described in CLAIMTAG. -#define CPU_TPIU_CLAIMCLR_CLAIMCLR_W 32 -#define CPU_TPIU_CLAIMCLR_CLAIMCLR_M 0xFFFFFFFF -#define CPU_TPIU_CLAIMCLR_CLAIMCLR_S 0 +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_W 32 +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_S 0 //***************************************************************************** // @@ -339,9 +339,8 @@ // // This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there is no // ETM present. -#define CPU_TPIU_DEVID_DEVID_W 32 -#define CPU_TPIU_DEVID_DEVID_M 0xFFFFFFFF -#define CPU_TPIU_DEVID_DEVID_S 0 - +#define CPU_TPIU_DEVID_DEVID_W 32 +#define CPU_TPIU_DEVID_DEVID_M 0xFFFFFFFF +#define CPU_TPIU_DEVID_DEVID_S 0 #endif // __CPU_TPIU__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_crypto.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_crypto.h index e349b89..9c3649c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_crypto.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_crypto.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_crypto_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_crypto_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CRYPTO_H__ #define __HW_CRYPTO_H__ @@ -44,313 +44,313 @@ // //***************************************************************************** // Channel 0 Control -#define CRYPTO_O_DMACH0CTL 0x00000000 +#define CRYPTO_O_DMACH0CTL 0x00000000 // Channel 0 External Address -#define CRYPTO_O_DMACH0EXTADDR 0x00000004 +#define CRYPTO_O_DMACH0EXTADDR 0x00000004 // Channel 0 DMA Length -#define CRYPTO_O_DMACH0LEN 0x0000000C +#define CRYPTO_O_DMACH0LEN 0x0000000C // DMAC Status -#define CRYPTO_O_DMASTAT 0x00000018 +#define CRYPTO_O_DMASTAT 0x00000018 // DMAC Software Reset -#define CRYPTO_O_DMASWRESET 0x0000001C +#define CRYPTO_O_DMASWRESET 0x0000001C // Channel 1 Control -#define CRYPTO_O_DMACH1CTL 0x00000020 +#define CRYPTO_O_DMACH1CTL 0x00000020 // Channel 1 External Address -#define CRYPTO_O_DMACH1EXTADDR 0x00000024 +#define CRYPTO_O_DMACH1EXTADDR 0x00000024 // Channel 1 DMA Length -#define CRYPTO_O_DMACH1LEN 0x0000002C +#define CRYPTO_O_DMACH1LEN 0x0000002C // DMAC Master Run-time Parameters -#define CRYPTO_O_DMABUSCFG 0x00000078 +#define CRYPTO_O_DMABUSCFG 0x00000078 // DMAC Port Error Raw Status -#define CRYPTO_O_DMAPORTERR 0x0000007C +#define CRYPTO_O_DMAPORTERR 0x0000007C // DMAC Version -#define CRYPTO_O_DMAHWVER 0x000000FC +#define CRYPTO_O_DMAHWVER 0x000000FC // Key Store Write Area -#define CRYPTO_O_KEYWRITEAREA 0x00000400 +#define CRYPTO_O_KEYWRITEAREA 0x00000400 // Key Store Written Area -#define CRYPTO_O_KEYWRITTENAREA 0x00000404 +#define CRYPTO_O_KEYWRITTENAREA 0x00000404 // Key Store Size -#define CRYPTO_O_KEYSIZE 0x00000408 +#define CRYPTO_O_KEYSIZE 0x00000408 // Key Store Read Area -#define CRYPTO_O_KEYREADAREA 0x0000040C +#define CRYPTO_O_KEYREADAREA 0x0000040C // AES_KEY2_0 / AES_GHASH_H_IN_0 -#define CRYPTO_O_AESKEY20 0x00000500 +#define CRYPTO_O_AESKEY20 0x00000500 // AES_KEY2_0 / AES_GHASH_H_IN_0 -#define CRYPTO_O_AESKEY21 0x00000504 +#define CRYPTO_O_AESKEY21 0x00000504 // AES_KEY2_0 / AES_GHASH_H_IN_0 -#define CRYPTO_O_AESKEY22 0x00000508 +#define CRYPTO_O_AESKEY22 0x00000508 // AES_KEY2_0 / AES_GHASH_H_IN_0 -#define CRYPTO_O_AESKEY23 0x0000050C +#define CRYPTO_O_AESKEY23 0x0000050C // AES_KEY3_0 / AES_KEY2_4 -#define CRYPTO_O_AESKEY30 0x00000510 +#define CRYPTO_O_AESKEY30 0x00000510 // AES_KEY3_0 / AES_KEY2_4 -#define CRYPTO_O_AESKEY31 0x00000514 +#define CRYPTO_O_AESKEY31 0x00000514 // AES_KEY3_0 / AES_KEY2_4 -#define CRYPTO_O_AESKEY32 0x00000518 +#define CRYPTO_O_AESKEY32 0x00000518 // AES_KEY3_0 / AES_KEY2_4 -#define CRYPTO_O_AESKEY33 0x0000051C +#define CRYPTO_O_AESKEY33 0x0000051C // AES initialization vector registers -#define CRYPTO_O_AESIV0 0x00000540 +#define CRYPTO_O_AESIV0 0x00000540 // AES initialization vector registers -#define CRYPTO_O_AESIV1 0x00000544 +#define CRYPTO_O_AESIV1 0x00000544 // AES initialization vector registers -#define CRYPTO_O_AESIV2 0x00000548 +#define CRYPTO_O_AESIV2 0x00000548 // AES initialization vector registers -#define CRYPTO_O_AESIV3 0x0000054C +#define CRYPTO_O_AESIV3 0x0000054C // AES Control -#define CRYPTO_O_AESCTL 0x00000550 +#define CRYPTO_O_AESCTL 0x00000550 // AES Crypto Length 0 (LSW) -#define CRYPTO_O_AESDATALEN0 0x00000554 +#define CRYPTO_O_AESDATALEN0 0x00000554 // AES Crypto Length 1 (MSW) -#define CRYPTO_O_AESDATALEN1 0x00000558 +#define CRYPTO_O_AESDATALEN1 0x00000558 // AES Authentication Length -#define CRYPTO_O_AESAUTHLEN 0x0000055C +#define CRYPTO_O_AESAUTHLEN 0x0000055C // Data Input/Output -#define CRYPTO_O_AESDATAOUT0 0x00000560 +#define CRYPTO_O_AESDATAOUT0 0x00000560 // AES Data Input_Output 0 -#define CRYPTO_O_AESDATAIN0 0x00000560 +#define CRYPTO_O_AESDATAIN0 0x00000560 // Data Input/Output -#define CRYPTO_O_AESDATAOUT1 0x00000564 +#define CRYPTO_O_AESDATAOUT1 0x00000564 // AES Data Input_Output 0 -#define CRYPTO_O_AESDATAIN1 0x00000564 +#define CRYPTO_O_AESDATAIN1 0x00000564 // Data Input/Output -#define CRYPTO_O_AESDATAOUT2 0x00000568 +#define CRYPTO_O_AESDATAOUT2 0x00000568 // AES Data Input_Output 2 -#define CRYPTO_O_AESDATAIN2 0x00000568 +#define CRYPTO_O_AESDATAIN2 0x00000568 // Data Input/Output -#define CRYPTO_O_AESDATAOUT3 0x0000056C +#define CRYPTO_O_AESDATAOUT3 0x0000056C // AES Data Input_Output 3 -#define CRYPTO_O_AESDATAIN3 0x0000056C +#define CRYPTO_O_AESDATAIN3 0x0000056C // AES Tag Out 0 -#define CRYPTO_O_AESTAGOUT0 0x00000570 +#define CRYPTO_O_AESTAGOUT0 0x00000570 // AES Tag Out 0 -#define CRYPTO_O_AESTAGOUT1 0x00000574 +#define CRYPTO_O_AESTAGOUT1 0x00000574 // AES Tag Out 0 -#define CRYPTO_O_AESTAGOUT2 0x00000578 +#define CRYPTO_O_AESTAGOUT2 0x00000578 // AES Tag Out 0 -#define CRYPTO_O_AESTAGOUT3 0x0000057C +#define CRYPTO_O_AESTAGOUT3 0x0000057C // HASH Data Input 1 -#define CRYPTO_O_HASHDATAIN1 0x00000604 +#define CRYPTO_O_HASHDATAIN1 0x00000604 // HASH Data Input 2 -#define CRYPTO_O_HASHDATAIN2 0x00000608 +#define CRYPTO_O_HASHDATAIN2 0x00000608 // HASH Data Input 3 -#define CRYPTO_O_HASHDATAIN3 0x0000060C +#define CRYPTO_O_HASHDATAIN3 0x0000060C // HASH Data Input 4 -#define CRYPTO_O_HASHDATAIN4 0x00000610 +#define CRYPTO_O_HASHDATAIN4 0x00000610 // HASH Data Input 5 -#define CRYPTO_O_HASHDATAIN5 0x00000614 +#define CRYPTO_O_HASHDATAIN5 0x00000614 // HASH Data Input 6 -#define CRYPTO_O_HASHDATAIN6 0x00000618 +#define CRYPTO_O_HASHDATAIN6 0x00000618 // HASH Data Input 7 -#define CRYPTO_O_HASHDATAIN7 0x0000061C +#define CRYPTO_O_HASHDATAIN7 0x0000061C // HASH Data Input 8 -#define CRYPTO_O_HASHDATAIN8 0x00000620 +#define CRYPTO_O_HASHDATAIN8 0x00000620 // HASH Data Input 9 -#define CRYPTO_O_HASHDATAIN9 0x00000624 +#define CRYPTO_O_HASHDATAIN9 0x00000624 // HASH Data Input 10 -#define CRYPTO_O_HASHDATAIN10 0x00000628 +#define CRYPTO_O_HASHDATAIN10 0x00000628 // HASH Data Input 11 -#define CRYPTO_O_HASHDATAIN11 0x0000062C +#define CRYPTO_O_HASHDATAIN11 0x0000062C // HASH Data Input 12 -#define CRYPTO_O_HASHDATAIN12 0x00000630 +#define CRYPTO_O_HASHDATAIN12 0x00000630 // HASH Data Input 13 -#define CRYPTO_O_HASHDATAIN13 0x00000634 +#define CRYPTO_O_HASHDATAIN13 0x00000634 // HASH Data Input 14 -#define CRYPTO_O_HASHDATAIN14 0x00000638 +#define CRYPTO_O_HASHDATAIN14 0x00000638 // HASH Data Input 15 -#define CRYPTO_O_HASHDATAIN15 0x0000063C +#define CRYPTO_O_HASHDATAIN15 0x0000063C // HASH Data Input 16 -#define CRYPTO_O_HASHDATAIN16 0x00000640 +#define CRYPTO_O_HASHDATAIN16 0x00000640 // HASH Data Input 17 -#define CRYPTO_O_HASHDATAIN17 0x00000644 +#define CRYPTO_O_HASHDATAIN17 0x00000644 // HASH Data Input 18 -#define CRYPTO_O_HASHDATAIN18 0x00000648 +#define CRYPTO_O_HASHDATAIN18 0x00000648 // HASH Data Input 19 -#define CRYPTO_O_HASHDATAIN19 0x0000064C +#define CRYPTO_O_HASHDATAIN19 0x0000064C // HASH Data Input 20 -#define CRYPTO_O_HASHDATAIN20 0x00000650 +#define CRYPTO_O_HASHDATAIN20 0x00000650 // HASH Data Input 21 -#define CRYPTO_O_HASHDATAIN21 0x00000654 +#define CRYPTO_O_HASHDATAIN21 0x00000654 // HASH Data Input 22 -#define CRYPTO_O_HASHDATAIN22 0x00000658 +#define CRYPTO_O_HASHDATAIN22 0x00000658 // HASH Data Input 23 -#define CRYPTO_O_HASHDATAIN23 0x0000065C +#define CRYPTO_O_HASHDATAIN23 0x0000065C // HASH Data Input 24 -#define CRYPTO_O_HASHDATAIN24 0x00000660 +#define CRYPTO_O_HASHDATAIN24 0x00000660 // HASH Data Input 25 -#define CRYPTO_O_HASHDATAIN25 0x00000664 +#define CRYPTO_O_HASHDATAIN25 0x00000664 // HASH Data Input 26 -#define CRYPTO_O_HASHDATAIN26 0x00000668 +#define CRYPTO_O_HASHDATAIN26 0x00000668 // HASH Data Input 27 -#define CRYPTO_O_HASHDATAIN27 0x0000066C +#define CRYPTO_O_HASHDATAIN27 0x0000066C // HASH Data Input 28 -#define CRYPTO_O_HASHDATAIN28 0x00000670 +#define CRYPTO_O_HASHDATAIN28 0x00000670 // HASH Data Input 29 -#define CRYPTO_O_HASHDATAIN29 0x00000674 +#define CRYPTO_O_HASHDATAIN29 0x00000674 // HASH Data Input 30 -#define CRYPTO_O_HASHDATAIN30 0x00000678 +#define CRYPTO_O_HASHDATAIN30 0x00000678 // HASH Data Input 31 -#define CRYPTO_O_HASHDATAIN31 0x0000067C +#define CRYPTO_O_HASHDATAIN31 0x0000067C // HASH Input_Output Buffer Control -#define CRYPTO_O_HASHIOBUFCTRL 0x00000680 +#define CRYPTO_O_HASHIOBUFCTRL 0x00000680 // HASH Mode -#define CRYPTO_O_HASHMODE 0x00000684 +#define CRYPTO_O_HASHMODE 0x00000684 // HASH Input Length LSB -#define CRYPTO_O_HASHINLENL 0x00000688 +#define CRYPTO_O_HASHINLENL 0x00000688 // HASH Input Length MSB -#define CRYPTO_O_HASHINLENH 0x0000068C +#define CRYPTO_O_HASHINLENH 0x0000068C // HASH Digest A -#define CRYPTO_O_HASHDIGESTA 0x000006C0 +#define CRYPTO_O_HASHDIGESTA 0x000006C0 // HASH Digest B -#define CRYPTO_O_HASHDIGESTB 0x000006C4 +#define CRYPTO_O_HASHDIGESTB 0x000006C4 // HASH Digest C -#define CRYPTO_O_HASHDIGESTC 0x000006C8 +#define CRYPTO_O_HASHDIGESTC 0x000006C8 // HASH Digest D -#define CRYPTO_O_HASHDIGESTD 0x000006CC +#define CRYPTO_O_HASHDIGESTD 0x000006CC // HASH Digest E -#define CRYPTO_O_HASHDIGESTE 0x000006D0 +#define CRYPTO_O_HASHDIGESTE 0x000006D0 // HASH Digest F -#define CRYPTO_O_HASHDIGESTF 0x000006D4 +#define CRYPTO_O_HASHDIGESTF 0x000006D4 // HASH Digest G -#define CRYPTO_O_HASHDIGESTG 0x000006D8 +#define CRYPTO_O_HASHDIGESTG 0x000006D8 // HASH Digest H -#define CRYPTO_O_HASHDIGESTH 0x000006DC +#define CRYPTO_O_HASHDIGESTH 0x000006DC // HASH Digest I -#define CRYPTO_O_HASHDIGESTI 0x000006E0 +#define CRYPTO_O_HASHDIGESTI 0x000006E0 // HASH Digest J -#define CRYPTO_O_HASHDIGESTJ 0x000006E4 +#define CRYPTO_O_HASHDIGESTJ 0x000006E4 // HASH Digest K -#define CRYPTO_O_HASHDIGESTK 0x000006E8 +#define CRYPTO_O_HASHDIGESTK 0x000006E8 // HASH Digest L -#define CRYPTO_O_HASHDIGESTL 0x000006EC +#define CRYPTO_O_HASHDIGESTL 0x000006EC // HASH Digest M -#define CRYPTO_O_HASHDIGESTM 0x000006F0 +#define CRYPTO_O_HASHDIGESTM 0x000006F0 // HASH Digest N -#define CRYPTO_O_HASHDIGESTN 0x000006F4 +#define CRYPTO_O_HASHDIGESTN 0x000006F4 // HASH Digest 0 -#define CRYPTO_O_HASHDIGESTO 0x000006F8 +#define CRYPTO_O_HASHDIGESTO 0x000006F8 // HASH Digest P -#define CRYPTO_O_HASHDIGESTP 0x000006FC +#define CRYPTO_O_HASHDIGESTP 0x000006FC // Algorithm Select -#define CRYPTO_O_ALGSEL 0x00000700 +#define CRYPTO_O_ALGSEL 0x00000700 // DMA Protection Control -#define CRYPTO_O_DMAPROTCTL 0x00000704 +#define CRYPTO_O_DMAPROTCTL 0x00000704 // Software Reset -#define CRYPTO_O_SWRESET 0x00000740 +#define CRYPTO_O_SWRESET 0x00000740 // Control Interrupt Configuration -#define CRYPTO_O_IRQTYPE 0x00000780 +#define CRYPTO_O_IRQTYPE 0x00000780 // Control Interrupt Enable -#define CRYPTO_O_IRQEN 0x00000784 +#define CRYPTO_O_IRQEN 0x00000784 // Control Interrupt Clear -#define CRYPTO_O_IRQCLR 0x00000788 +#define CRYPTO_O_IRQCLR 0x00000788 // Control Interrupt Set -#define CRYPTO_O_IRQSET 0x0000078C +#define CRYPTO_O_IRQSET 0x0000078C // Control Interrupt Status -#define CRYPTO_O_IRQSTAT 0x00000790 +#define CRYPTO_O_IRQSTAT 0x00000790 // Hardware Version -#define CRYPTO_O_HWVER 0x000007FC +#define CRYPTO_O_HWVER 0x000007FC //***************************************************************************** // @@ -366,10 +366,10 @@ // external port is arbitrated using the round robin scheme. If one channel has // a high priority and another one low, the channel with the high priority is // served first, in case of simultaneous access requests. -#define CRYPTO_DMACH0CTL_PRIO 0x00000002 -#define CRYPTO_DMACH0CTL_PRIO_BITN 1 -#define CRYPTO_DMACH0CTL_PRIO_M 0x00000002 -#define CRYPTO_DMACH0CTL_PRIO_S 1 +#define CRYPTO_DMACH0CTL_PRIO 0x00000002 +#define CRYPTO_DMACH0CTL_PRIO_BITN 1 +#define CRYPTO_DMACH0CTL_PRIO_M 0x00000002 +#define CRYPTO_DMACH0CTL_PRIO_S 1 // Field: [0] EN // @@ -378,10 +378,10 @@ // 1: Enable // Note: Disabling an active channel interrupts the DMA operation. The ongoing // block transfer completes, but no new transfers are requested. -#define CRYPTO_DMACH0CTL_EN 0x00000001 -#define CRYPTO_DMACH0CTL_EN_BITN 0 -#define CRYPTO_DMACH0CTL_EN_M 0x00000001 -#define CRYPTO_DMACH0CTL_EN_S 0 +#define CRYPTO_DMACH0CTL_EN 0x00000001 +#define CRYPTO_DMACH0CTL_EN_BITN 0 +#define CRYPTO_DMACH0CTL_EN_M 0x00000001 +#define CRYPTO_DMACH0CTL_EN_S 0 //***************************************************************************** // @@ -395,9 +395,9 @@ // being sent to the master interface. Note: The crypto DMA copies out upto 3 // bytes until it hits a word boundary, thus the address need not be word // aligned. -#define CRYPTO_DMACH0EXTADDR_ADDR_W 32 -#define CRYPTO_DMACH0EXTADDR_ADDR_M 0xFFFFFFFF -#define CRYPTO_DMACH0EXTADDR_ADDR_S 0 +#define CRYPTO_DMACH0EXTADDR_ADDR_W 32 +#define CRYPTO_DMACH0EXTADDR_ADDR_M 0xFFFFFFFF +#define CRYPTO_DMACH0EXTADDR_ADDR_S 0 //***************************************************************************** // @@ -413,9 +413,9 @@ // Note: Setting this register to a nonzero value starts the transfer if the // channel is enabled. Therefore, this register must be written last when // setting up a DMA channel. -#define CRYPTO_DMACH0LEN_DMALEN_W 16 -#define CRYPTO_DMACH0LEN_DMALEN_M 0x0000FFFF -#define CRYPTO_DMACH0LEN_DMALEN_S 0 +#define CRYPTO_DMACH0LEN_DMALEN_W 16 +#define CRYPTO_DMACH0LEN_DMALEN_M 0x0000FFFF +#define CRYPTO_DMACH0LEN_DMALEN_S 0 //***************************************************************************** // @@ -425,26 +425,26 @@ // Field: [17] PORT_ERR // // Reflects possible transfer errors on the AHB port. -#define CRYPTO_DMASTAT_PORT_ERR 0x00020000 -#define CRYPTO_DMASTAT_PORT_ERR_BITN 17 -#define CRYPTO_DMASTAT_PORT_ERR_M 0x00020000 -#define CRYPTO_DMASTAT_PORT_ERR_S 17 +#define CRYPTO_DMASTAT_PORT_ERR 0x00020000 +#define CRYPTO_DMASTAT_PORT_ERR_BITN 17 +#define CRYPTO_DMASTAT_PORT_ERR_M 0x00020000 +#define CRYPTO_DMASTAT_PORT_ERR_S 17 // Field: [1] CH1_ACT // // A value of 1 indicates that channel 1 is active (DMA transfer on-going). -#define CRYPTO_DMASTAT_CH1_ACT 0x00000002 -#define CRYPTO_DMASTAT_CH1_ACT_BITN 1 -#define CRYPTO_DMASTAT_CH1_ACT_M 0x00000002 -#define CRYPTO_DMASTAT_CH1_ACT_S 1 +#define CRYPTO_DMASTAT_CH1_ACT 0x00000002 +#define CRYPTO_DMASTAT_CH1_ACT_BITN 1 +#define CRYPTO_DMASTAT_CH1_ACT_M 0x00000002 +#define CRYPTO_DMASTAT_CH1_ACT_S 1 // Field: [0] CH0_ACT // // A value of 1 indicates that channel 0 is active (DMA transfer on-going). -#define CRYPTO_DMASTAT_CH0_ACT 0x00000001 -#define CRYPTO_DMASTAT_CH0_ACT_BITN 0 -#define CRYPTO_DMASTAT_CH0_ACT_M 0x00000001 -#define CRYPTO_DMASTAT_CH0_ACT_S 0 +#define CRYPTO_DMASTAT_CH0_ACT 0x00000001 +#define CRYPTO_DMASTAT_CH0_ACT_BITN 0 +#define CRYPTO_DMASTAT_CH0_ACT_M 0x00000001 +#define CRYPTO_DMASTAT_CH0_ACT_S 0 //***************************************************************************** // @@ -457,10 +457,10 @@ // 0 : Disabled // 1 : Enabled (self-cleared to 0) // Completion of the software reset must be checked through the DMASTAT -#define CRYPTO_DMASWRESET_SWRES 0x00000001 -#define CRYPTO_DMASWRESET_SWRES_BITN 0 -#define CRYPTO_DMASWRESET_SWRES_M 0x00000001 -#define CRYPTO_DMASWRESET_SWRES_S 0 +#define CRYPTO_DMASWRESET_SWRES 0x00000001 +#define CRYPTO_DMASWRESET_SWRES_BITN 0 +#define CRYPTO_DMASWRESET_SWRES_M 0x00000001 +#define CRYPTO_DMASWRESET_SWRES_S 0 //***************************************************************************** // @@ -476,10 +476,10 @@ // external port is arbitrated using the round robin scheme. If one channel has // a high priority and another one low, the channel with the high priority is // served first, in case of simultaneous access requests. -#define CRYPTO_DMACH1CTL_PRIO 0x00000002 -#define CRYPTO_DMACH1CTL_PRIO_BITN 1 -#define CRYPTO_DMACH1CTL_PRIO_M 0x00000002 -#define CRYPTO_DMACH1CTL_PRIO_S 1 +#define CRYPTO_DMACH1CTL_PRIO 0x00000002 +#define CRYPTO_DMACH1CTL_PRIO_BITN 1 +#define CRYPTO_DMACH1CTL_PRIO_M 0x00000002 +#define CRYPTO_DMACH1CTL_PRIO_S 1 // Field: [0] EN // @@ -488,10 +488,10 @@ // 1: Enable // Note: Disabling an active channel interrupts the DMA operation. The ongoing // block transfer completes, but no new transfers are requested. -#define CRYPTO_DMACH1CTL_EN 0x00000001 -#define CRYPTO_DMACH1CTL_EN_BITN 0 -#define CRYPTO_DMACH1CTL_EN_M 0x00000001 -#define CRYPTO_DMACH1CTL_EN_S 0 +#define CRYPTO_DMACH1CTL_EN 0x00000001 +#define CRYPTO_DMACH1CTL_EN_BITN 0 +#define CRYPTO_DMACH1CTL_EN_M 0x00000001 +#define CRYPTO_DMACH1CTL_EN_S 0 //***************************************************************************** // @@ -505,9 +505,9 @@ // being sent to the master interface. Note: The crypto DMA copies out upto 3 // bytes until it hits a word boundary, thus the address need not be word // aligned. -#define CRYPTO_DMACH1EXTADDR_ADDR_W 32 -#define CRYPTO_DMACH1EXTADDR_ADDR_M 0xFFFFFFFF -#define CRYPTO_DMACH1EXTADDR_ADDR_S 0 +#define CRYPTO_DMACH1EXTADDR_ADDR_W 32 +#define CRYPTO_DMACH1EXTADDR_ADDR_M 0xFFFFFFFF +#define CRYPTO_DMACH1EXTADDR_ADDR_S 0 //***************************************************************************** // @@ -523,9 +523,9 @@ // Note: Setting this register to a nonzero value starts the transfer if the // channel is enabled. Therefore, this register must be written last when // setting up a DMA channel. -#define CRYPTO_DMACH1LEN_DMALEN_W 16 -#define CRYPTO_DMACH1LEN_DMALEN_M 0x0000FFFF -#define CRYPTO_DMACH1LEN_DMALEN_S 0 +#define CRYPTO_DMACH1LEN_DMALEN_W 16 +#define CRYPTO_DMACH1LEN_DMALEN_M 0x0000FFFF +#define CRYPTO_DMACH1LEN_DMALEN_S 0 //***************************************************************************** // @@ -541,14 +541,14 @@ // 16_BYTE 16 bytes // 8_BYTE 8 bytes // 4_BYTE 4 bytes -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_W 4 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_M 0x0000F000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_S 12 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_64_BYTE 0x00006000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_32_BYTE 0x00005000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_16_BYTE 0x00004000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_8_BYTE 0x00003000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_4_BYTE 0x00002000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_W 4 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_M 0x0000F000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_S 12 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_64_BYTE 0x00006000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_32_BYTE 0x00005000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_16_BYTE 0x00004000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_8_BYTE 0x00003000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_4_BYTE 0x00002000 // Field: [11] AHB_MST1_IDLE_EN // @@ -556,12 +556,12 @@ // ENUMs: // IDLE Idle transfer insertion enabled // NO_IDLE Do not insert idle transfers. -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN 0x00000800 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_BITN 11 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_M 0x00000800 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_S 11 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_IDLE 0x00000800 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_NO_IDLE 0x00000000 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_BITN 11 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_M 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_S 11 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_IDLE 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_NO_IDLE 0x00000000 // Field: [10] AHB_MST1_INCR_EN // @@ -569,12 +569,12 @@ // ENUMs: // SPECIFIED Fixed length bursts or single transfers // UNSPECIFIED Unspecified length burst transfers -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN 0x00000400 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_BITN 10 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_M 0x00000400 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_S 10 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_SPECIFIED 0x00000400 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_UNSPECIFIED 0x00000000 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_BITN 10 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_M 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_S 10 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_SPECIFIED 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_UNSPECIFIED 0x00000000 // Field: [9] AHB_MST1_LOCK_EN // @@ -582,12 +582,12 @@ // ENUMs: // LOCKED Transfers are locked // NOT_LOCKED Transfers are not locked -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN 0x00000200 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_BITN 9 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_M 0x00000200 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_S 9 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_LOCKED 0x00000200 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_NOT_LOCKED 0x00000000 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_BITN 9 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_M 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_S 9 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_LOCKED 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_NOT_LOCKED 0x00000000 // Field: [8] AHB_MST1_BIGEND // @@ -595,12 +595,12 @@ // ENUMs: // BIG_ENDIAN Big Endian // LITTLE_ENDIAN Little Endian -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND 0x00000100 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BITN 8 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_M 0x00000100 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_S 8 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BIG_ENDIAN 0x00000100 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_LITTLE_ENDIAN 0x00000000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BITN 8 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_M 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_S 8 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BIG_ENDIAN 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_LITTLE_ENDIAN 0x00000000 //***************************************************************************** // @@ -610,19 +610,19 @@ // Field: [12] PORT1_AHB_ERROR // // A value of 1 indicates that the EIP-101 has detected an AHB bus error -#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR 0x00001000 -#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR_BITN 12 -#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR_M 0x00001000 -#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR_S 12 +#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR 0x00001000 +#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR_BITN 12 +#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR_M 0x00001000 +#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR_S 12 // Field: [9] PORT1_CHANNEL // // Indicates which channel has serviced last (channel 0 or channel 1) by AHB // master port. -#define CRYPTO_DMAPORTERR_PORT1_CHANNEL 0x00000200 -#define CRYPTO_DMAPORTERR_PORT1_CHANNEL_BITN 9 -#define CRYPTO_DMAPORTERR_PORT1_CHANNEL_M 0x00000200 -#define CRYPTO_DMAPORTERR_PORT1_CHANNEL_S 9 +#define CRYPTO_DMAPORTERR_PORT1_CHANNEL 0x00000200 +#define CRYPTO_DMAPORTERR_PORT1_CHANNEL_BITN 9 +#define CRYPTO_DMAPORTERR_PORT1_CHANNEL_M 0x00000200 +#define CRYPTO_DMAPORTERR_PORT1_CHANNEL_S 9 //***************************************************************************** // @@ -632,38 +632,38 @@ // Field: [27:24] HW_MAJOR_VERSION // // Major version number -#define CRYPTO_DMAHWVER_HW_MAJOR_VERSION_W 4 -#define CRYPTO_DMAHWVER_HW_MAJOR_VERSION_M 0x0F000000 -#define CRYPTO_DMAHWVER_HW_MAJOR_VERSION_S 24 +#define CRYPTO_DMAHWVER_HW_MAJOR_VERSION_W 4 +#define CRYPTO_DMAHWVER_HW_MAJOR_VERSION_M 0x0F000000 +#define CRYPTO_DMAHWVER_HW_MAJOR_VERSION_S 24 // Field: [23:20] HW_MINOR_VERSION // // Minor version number -#define CRYPTO_DMAHWVER_HW_MINOR_VERSION_W 4 -#define CRYPTO_DMAHWVER_HW_MINOR_VERSION_M 0x00F00000 -#define CRYPTO_DMAHWVER_HW_MINOR_VERSION_S 20 +#define CRYPTO_DMAHWVER_HW_MINOR_VERSION_W 4 +#define CRYPTO_DMAHWVER_HW_MINOR_VERSION_M 0x00F00000 +#define CRYPTO_DMAHWVER_HW_MINOR_VERSION_S 20 // Field: [19:16] HW_PATCH_LEVEL // // Patch level // Starts at 0 at first delivery of this version -#define CRYPTO_DMAHWVER_HW_PATCH_LEVEL_W 4 -#define CRYPTO_DMAHWVER_HW_PATCH_LEVEL_M 0x000F0000 -#define CRYPTO_DMAHWVER_HW_PATCH_LEVEL_S 16 +#define CRYPTO_DMAHWVER_HW_PATCH_LEVEL_W 4 +#define CRYPTO_DMAHWVER_HW_PATCH_LEVEL_M 0x000F0000 +#define CRYPTO_DMAHWVER_HW_PATCH_LEVEL_S 16 // Field: [15:8] EIP_NUMBER_COMPL // // Bit-by-bit complement of the EIP_NUMBER field bits. -#define CRYPTO_DMAHWVER_EIP_NUMBER_COMPL_W 8 -#define CRYPTO_DMAHWVER_EIP_NUMBER_COMPL_M 0x0000FF00 -#define CRYPTO_DMAHWVER_EIP_NUMBER_COMPL_S 8 +#define CRYPTO_DMAHWVER_EIP_NUMBER_COMPL_W 8 +#define CRYPTO_DMAHWVER_EIP_NUMBER_COMPL_M 0x0000FF00 +#define CRYPTO_DMAHWVER_EIP_NUMBER_COMPL_S 8 // Field: [7:0] EIP_NUMBER // // Binary encoding of the EIP-number of this DMA controller (209) -#define CRYPTO_DMAHWVER_EIP_NUMBER_W 8 -#define CRYPTO_DMAHWVER_EIP_NUMBER_M 0x000000FF -#define CRYPTO_DMAHWVER_EIP_NUMBER_S 0 +#define CRYPTO_DMAHWVER_EIP_NUMBER_W 8 +#define CRYPTO_DMAHWVER_EIP_NUMBER_M 0x000000FF +#define CRYPTO_DMAHWVER_EIP_NUMBER_S 0 //***************************************************************************** // @@ -684,12 +684,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA7 0x00000080 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_BITN 7 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_M 0x00000080 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_S 7 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_SEL 0x00000080 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_BITN 7 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_M 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_S 7 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_SEL 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_NOT_SEL 0x00000000 // Field: [6] RAM_AREA6 // @@ -705,12 +705,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA6 0x00000040 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_BITN 6 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_M 0x00000040 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_S 6 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_SEL 0x00000040 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_BITN 6 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_M 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_S 6 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_SEL 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_NOT_SEL 0x00000000 // Field: [5] RAM_AREA5 // @@ -726,12 +726,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA5 0x00000020 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_BITN 5 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_M 0x00000020 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_S 5 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_SEL 0x00000020 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_BITN 5 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_M 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_S 5 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_SEL 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_NOT_SEL 0x00000000 // Field: [4] RAM_AREA4 // @@ -747,12 +747,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA4 0x00000010 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_BITN 4 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_M 0x00000010 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_S 4 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_SEL 0x00000010 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_BITN 4 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_M 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_S 4 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_SEL 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_NOT_SEL 0x00000000 // Field: [3] RAM_AREA3 // @@ -768,12 +768,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA3 0x00000008 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_BITN 3 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_M 0x00000008 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_S 3 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_SEL 0x00000008 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_BITN 3 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_M 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_S 3 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_SEL 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_NOT_SEL 0x00000000 // Field: [2] RAM_AREA2 // @@ -789,12 +789,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA2 0x00000004 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_BITN 2 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_M 0x00000004 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_S 2 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_SEL 0x00000004 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_BITN 2 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_M 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_S 2 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_SEL 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_NOT_SEL 0x00000000 // Field: [1] RAM_AREA1 // @@ -810,12 +810,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA1 0x00000002 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_BITN 1 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_M 0x00000002 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_S 1 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_SEL 0x00000002 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_BITN 1 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_M 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_S 1 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_SEL 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_NOT_SEL 0x00000000 // Field: [0] RAM_AREA0 // @@ -831,12 +831,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA0 0x00000001 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_BITN 0 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_M 0x00000001 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_S 0 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_SEL 0x00000001 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_BITN 0 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_M 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_S 0 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_SEL 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_NOT_SEL 0x00000000 //***************************************************************************** // @@ -857,12 +857,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7 0x00000080 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_BITN 7 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_M 0x00000080 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_S 7 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_WRITTEN 0x00000080 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_BITN 7 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_M 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_S 7 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_WRITTEN 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_NOT_WRITTEN 0x00000000 // Field: [6] RAM_AREA_WRITTEN6 // @@ -878,12 +878,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6 0x00000040 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_BITN 6 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_M 0x00000040 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_S 6 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_WRITTEN 0x00000040 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_BITN 6 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_M 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_S 6 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_WRITTEN 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_NOT_WRITTEN 0x00000000 // Field: [5] RAM_AREA_WRITTEN5 // @@ -899,12 +899,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5 0x00000020 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_BITN 5 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_M 0x00000020 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_S 5 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_WRITTEN 0x00000020 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_BITN 5 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_M 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_S 5 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_WRITTEN 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_NOT_WRITTEN 0x00000000 // Field: [4] RAM_AREA_WRITTEN4 // @@ -920,12 +920,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4 0x00000010 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_BITN 4 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_M 0x00000010 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_S 4 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_WRITTEN 0x00000010 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_BITN 4 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_M 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_S 4 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_WRITTEN 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_NOT_WRITTEN 0x00000000 // Field: [3] RAM_AREA_WRITTEN3 // @@ -941,12 +941,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3 0x00000008 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_BITN 3 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_M 0x00000008 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_S 3 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_WRITTEN 0x00000008 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_BITN 3 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_M 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_S 3 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_WRITTEN 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_NOT_WRITTEN 0x00000000 // Field: [2] RAM_AREA_WRITTEN2 // @@ -962,12 +962,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2 0x00000004 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_BITN 2 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_M 0x00000004 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_S 2 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_WRITTEN 0x00000004 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_BITN 2 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_M 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_S 2 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_WRITTEN 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_NOT_WRITTEN 0x00000000 // Field: [1] RAM_AREA_WRITTEN1 // @@ -983,12 +983,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1 0x00000002 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_BITN 1 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_M 0x00000002 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_S 1 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_WRITTEN 0x00000002 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_BITN 1 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_M 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_S 1 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_WRITTEN 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_NOT_WRITTEN 0x00000000 // Field: [0] RAM_AREA_WRITTEN0 // @@ -999,10 +999,10 @@ // Note: This register will be reset on a soft reset initiated by writing to // DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key // store memory. -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0 0x00000001 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_BITN 0 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_M 0x00000001 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_S 0 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0 0x00000001 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_BITN 0 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_M 0x00000001 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_S 0 //***************************************************************************** // @@ -1019,12 +1019,12 @@ // 256_BIT 256 bits // 192_BIT 192 bits // 128_BIT 128 bits -#define CRYPTO_KEYSIZE_SIZE_W 2 -#define CRYPTO_KEYSIZE_SIZE_M 0x00000003 -#define CRYPTO_KEYSIZE_SIZE_S 0 -#define CRYPTO_KEYSIZE_SIZE_256_BIT 0x00000003 -#define CRYPTO_KEYSIZE_SIZE_192_BIT 0x00000002 -#define CRYPTO_KEYSIZE_SIZE_128_BIT 0x00000001 +#define CRYPTO_KEYSIZE_SIZE_W 2 +#define CRYPTO_KEYSIZE_SIZE_M 0x00000003 +#define CRYPTO_KEYSIZE_SIZE_S 0 +#define CRYPTO_KEYSIZE_SIZE_256_BIT 0x00000003 +#define CRYPTO_KEYSIZE_SIZE_192_BIT 0x00000002 +#define CRYPTO_KEYSIZE_SIZE_128_BIT 0x00000001 //***************************************************************************** // @@ -1036,10 +1036,10 @@ // Key store operation busy status flag (read only): // 0: Operation is complete. // 1: Operation is not completed and the key store is busy. -#define CRYPTO_KEYREADAREA_BUSY 0x80000000 -#define CRYPTO_KEYREADAREA_BUSY_BITN 31 -#define CRYPTO_KEYREADAREA_BUSY_M 0x80000000 -#define CRYPTO_KEYREADAREA_BUSY_S 31 +#define CRYPTO_KEYREADAREA_BUSY 0x80000000 +#define CRYPTO_KEYREADAREA_BUSY_BITN 31 +#define CRYPTO_KEYREADAREA_BUSY_M 0x80000000 +#define CRYPTO_KEYREADAREA_BUSY_S 31 // Field: [3:0] RAM_AREA // @@ -1060,18 +1060,18 @@ // RAM_AREA2 RAM Area 2 // RAM_AREA1 RAM Area 1 // RAM_AREA0 RAM Area 0 -#define CRYPTO_KEYREADAREA_RAM_AREA_W 4 -#define CRYPTO_KEYREADAREA_RAM_AREA_M 0x0000000F -#define CRYPTO_KEYREADAREA_RAM_AREA_S 0 -#define CRYPTO_KEYREADAREA_RAM_AREA_NO_RAM 0x00000008 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA7 0x00000007 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA6 0x00000006 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA5 0x00000005 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA4 0x00000004 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA3 0x00000003 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA2 0x00000002 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA1 0x00000001 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA0 0x00000000 +#define CRYPTO_KEYREADAREA_RAM_AREA_W 4 +#define CRYPTO_KEYREADAREA_RAM_AREA_M 0x0000000F +#define CRYPTO_KEYREADAREA_RAM_AREA_S 0 +#define CRYPTO_KEYREADAREA_RAM_AREA_NO_RAM 0x00000008 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA7 0x00000007 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA6 0x00000006 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA5 0x00000005 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA4 0x00000004 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA3 0x00000003 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA2 0x00000002 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA1 0x00000001 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA0 0x00000000 //***************************************************************************** // @@ -1093,9 +1093,9 @@ // // For CBC-MAC: // -[255:0] - ZEROES - This register must remain 0. -#define CRYPTO_AESKEY20_AES_KEY2_W 32 -#define CRYPTO_AESKEY20_AES_KEY2_M 0xFFFFFFFF -#define CRYPTO_AESKEY20_AES_KEY2_S 0 +#define CRYPTO_AESKEY20_AES_KEY2_W 32 +#define CRYPTO_AESKEY20_AES_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY20_AES_KEY2_S 0 //***************************************************************************** // @@ -1117,9 +1117,9 @@ // // For CBC-MAC: // -[255:0] - ZEROES - This register must remain 0. -#define CRYPTO_AESKEY21_AES_KEY2_W 32 -#define CRYPTO_AESKEY21_AES_KEY2_M 0xFFFFFFFF -#define CRYPTO_AESKEY21_AES_KEY2_S 0 +#define CRYPTO_AESKEY21_AES_KEY2_W 32 +#define CRYPTO_AESKEY21_AES_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY21_AES_KEY2_S 0 //***************************************************************************** // @@ -1141,9 +1141,9 @@ // // For CBC-MAC: // -[255:0] - ZEROES - This register must remain 0. -#define CRYPTO_AESKEY22_AES_KEY2_W 32 -#define CRYPTO_AESKEY22_AES_KEY2_M 0xFFFFFFFF -#define CRYPTO_AESKEY22_AES_KEY2_S 0 +#define CRYPTO_AESKEY22_AES_KEY2_W 32 +#define CRYPTO_AESKEY22_AES_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY22_AES_KEY2_S 0 //***************************************************************************** // @@ -1165,9 +1165,9 @@ // // For CBC-MAC: // -[255:0] - ZEROES - This register must remain 0. -#define CRYPTO_AESKEY23_AES_KEY2_W 32 -#define CRYPTO_AESKEY23_AES_KEY2_M 0xFFFFFFFF -#define CRYPTO_AESKEY23_AES_KEY2_S 0 +#define CRYPTO_AESKEY23_AES_KEY2_W 32 +#define CRYPTO_AESKEY23_AES_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY23_AES_KEY2_S 0 //***************************************************************************** // @@ -1189,9 +1189,9 @@ // // For CBC-MAC: // -[255:0] - ZEROES - This register must remain 0. -#define CRYPTO_AESKEY30_AES_KEY3_W 32 -#define CRYPTO_AESKEY30_AES_KEY3_M 0xFFFFFFFF -#define CRYPTO_AESKEY30_AES_KEY3_S 0 +#define CRYPTO_AESKEY30_AES_KEY3_W 32 +#define CRYPTO_AESKEY30_AES_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY30_AES_KEY3_S 0 //***************************************************************************** // @@ -1213,9 +1213,9 @@ // // For CBC-MAC: // -[255:0] - ZEROES - This register must remain 0. -#define CRYPTO_AESKEY31_AES_KEY3_W 32 -#define CRYPTO_AESKEY31_AES_KEY3_M 0xFFFFFFFF -#define CRYPTO_AESKEY31_AES_KEY3_S 0 +#define CRYPTO_AESKEY31_AES_KEY3_W 32 +#define CRYPTO_AESKEY31_AES_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY31_AES_KEY3_S 0 //***************************************************************************** // @@ -1237,9 +1237,9 @@ // // For CBC-MAC: // -[255:0] - ZEROES - This register must remain 0. -#define CRYPTO_AESKEY32_AES_KEY3_W 32 -#define CRYPTO_AESKEY32_AES_KEY3_M 0xFFFFFFFF -#define CRYPTO_AESKEY32_AES_KEY3_S 0 +#define CRYPTO_AESKEY32_AES_KEY3_W 32 +#define CRYPTO_AESKEY32_AES_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY32_AES_KEY3_S 0 //***************************************************************************** // @@ -1261,9 +1261,9 @@ // // For CBC-MAC: // -[255:0] - ZEROES - This register must remain 0. -#define CRYPTO_AESKEY33_AES_KEY3_W 32 -#define CRYPTO_AESKEY33_AES_KEY3_M 0xFFFFFFFF -#define CRYPTO_AESKEY33_AES_KEY3_S 0 +#define CRYPTO_AESKEY33_AES_KEY3_W 32 +#define CRYPTO_AESKEY33_AES_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY33_AES_KEY3_S 0 //***************************************************************************** // @@ -1302,9 +1302,9 @@ // -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the // start of each operation. After an operation, these registers contain the // 128-bit TAG output, generated by the EIP-120t. -#define CRYPTO_AESIV0_AES_IV_W 32 -#define CRYPTO_AESIV0_AES_IV_M 0xFFFFFFFF -#define CRYPTO_AESIV0_AES_IV_S 0 +#define CRYPTO_AESIV0_AES_IV_W 32 +#define CRYPTO_AESIV0_AES_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV0_AES_IV_S 0 //***************************************************************************** // @@ -1343,9 +1343,9 @@ // -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the // start of each operation. After an operation, these registers contain the // 128-bit TAG output, generated by the EIP-120t. -#define CRYPTO_AESIV1_AES_IV_W 32 -#define CRYPTO_AESIV1_AES_IV_M 0xFFFFFFFF -#define CRYPTO_AESIV1_AES_IV_S 0 +#define CRYPTO_AESIV1_AES_IV_W 32 +#define CRYPTO_AESIV1_AES_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV1_AES_IV_S 0 //***************************************************************************** // @@ -1384,9 +1384,9 @@ // -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the // start of each operation. After an operation, these registers contain the // 128-bit TAG output, generated by the EIP-120t. -#define CRYPTO_AESIV2_AES_IV_W 32 -#define CRYPTO_AESIV2_AES_IV_M 0xFFFFFFFF -#define CRYPTO_AESIV2_AES_IV_S 0 +#define CRYPTO_AESIV2_AES_IV_W 32 +#define CRYPTO_AESIV2_AES_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV2_AES_IV_S 0 //***************************************************************************** // @@ -1425,9 +1425,9 @@ // -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the // start of each operation. After an operation, these registers contain the // 128-bit TAG output, generated by the EIP-120t. -#define CRYPTO_AESIV3_AES_IV_W 32 -#define CRYPTO_AESIV3_AES_IV_M 0xFFFFFFFF -#define CRYPTO_AESIV3_AES_IV_S 0 +#define CRYPTO_AESIV3_AES_IV_W 32 +#define CRYPTO_AESIV3_AES_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV3_AES_IV_S 0 //***************************************************************************** // @@ -1438,10 +1438,10 @@ // // If 1, this read-only status bit indicates that the context data registers // can be overwritten and the host is permitted to write the next context. -#define CRYPTO_AESCTL_CONTEXT_READY 0x80000000 -#define CRYPTO_AESCTL_CONTEXT_READY_BITN 31 -#define CRYPTO_AESCTL_CONTEXT_READY_M 0x80000000 -#define CRYPTO_AESCTL_CONTEXT_READY_S 31 +#define CRYPTO_AESCTL_CONTEXT_READY 0x80000000 +#define CRYPTO_AESCTL_CONTEXT_READY_BITN 31 +#define CRYPTO_AESCTL_CONTEXT_READY_M 0x80000000 +#define CRYPTO_AESCTL_CONTEXT_READY_S 31 // Field: [30] SAVED_CONTEXT_RDY // @@ -1456,10 +1456,10 @@ // with 1. // Note: This bit is controlled automatically by the EIP-120t for TAG read DMA // operations. -#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY 0x40000000 -#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_BITN 30 -#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M 0x40000000 -#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_S 30 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY 0x40000000 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_BITN 30 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M 0x40000000 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_S 30 // Field: [29] SAVE_CONTEXT // @@ -1471,10 +1471,10 @@ // If this bit is set, the engine retains its full context until the TAG and/or // IV registers are read. // The TAG or IV must be read before the AES engine can start a new operation. -#define CRYPTO_AESCTL_SAVE_CONTEXT 0x20000000 -#define CRYPTO_AESCTL_SAVE_CONTEXT_BITN 29 -#define CRYPTO_AESCTL_SAVE_CONTEXT_M 0x20000000 -#define CRYPTO_AESCTL_SAVE_CONTEXT_S 29 +#define CRYPTO_AESCTL_SAVE_CONTEXT 0x20000000 +#define CRYPTO_AESCTL_SAVE_CONTEXT_BITN 29 +#define CRYPTO_AESCTL_SAVE_CONTEXT_M 0x20000000 +#define CRYPTO_AESCTL_SAVE_CONTEXT_S 29 // Field: [24:22] CCM_M // @@ -1483,18 +1483,18 @@ // CCM-M plus one). // Note: The EIP-120t always returns a 128-bit authentication field, of which // the M least significant bytes are valid. All values are supported. -#define CRYPTO_AESCTL_CCM_M_W 3 -#define CRYPTO_AESCTL_CCM_M_M 0x01C00000 -#define CRYPTO_AESCTL_CCM_M_S 22 +#define CRYPTO_AESCTL_CCM_M_W 3 +#define CRYPTO_AESCTL_CCM_M_M 0x01C00000 +#define CRYPTO_AESCTL_CCM_M_S 22 // Field: [21:19] CCM_L // // Defines L, which indicates the width of the length field for CCM operations; // the length field in bytes equals the value of CMM-L plus one. All values are // supported. -#define CRYPTO_AESCTL_CCM_L_W 3 -#define CRYPTO_AESCTL_CCM_L_M 0x00380000 -#define CRYPTO_AESCTL_CCM_L_S 19 +#define CRYPTO_AESCTL_CCM_L_W 3 +#define CRYPTO_AESCTL_CCM_L_M 0x00380000 +#define CRYPTO_AESCTL_CCM_L_S 19 // Field: [18] CCM // @@ -1504,10 +1504,10 @@ // after all other registers. // Note: The CTR mode bit in this register must also be set to 1 to enable // AES-CTR; selecting other AES modes than CTR mode is invalid. -#define CRYPTO_AESCTL_CCM 0x00040000 -#define CRYPTO_AESCTL_CCM_BITN 18 -#define CRYPTO_AESCTL_CCM_M 0x00040000 -#define CRYPTO_AESCTL_CCM_S 18 +#define CRYPTO_AESCTL_CCM 0x00040000 +#define CRYPTO_AESCTL_CCM_BITN 18 +#define CRYPTO_AESCTL_CCM_M 0x00040000 +#define CRYPTO_AESCTL_CCM_S 18 // Field: [17:16] GCM // @@ -1523,9 +1523,9 @@ // 11 = Autonomous GHASH (both H- and Y0-encrypted calculated internally) // Note: The EIP-120t-1 configuration only supports mode 11 (autonomous GHASH), // other GCM modes are not allowed. -#define CRYPTO_AESCTL_GCM_W 2 -#define CRYPTO_AESCTL_GCM_M 0x00030000 -#define CRYPTO_AESCTL_GCM_S 16 +#define CRYPTO_AESCTL_GCM_W 2 +#define CRYPTO_AESCTL_GCM_M 0x00030000 +#define CRYPTO_AESCTL_GCM_S 16 // Field: [15] CBC_MAC // @@ -1533,10 +1533,10 @@ // The direction bit must be set to 1 for this mode. // Selecting this mode requires writing the length register after all other // registers. -#define CRYPTO_AESCTL_CBC_MAC 0x00008000 -#define CRYPTO_AESCTL_CBC_MAC_BITN 15 -#define CRYPTO_AESCTL_CBC_MAC_M 0x00008000 -#define CRYPTO_AESCTL_CBC_MAC_S 15 +#define CRYPTO_AESCTL_CBC_MAC 0x00008000 +#define CRYPTO_AESCTL_CBC_MAC_BITN 15 +#define CRYPTO_AESCTL_CBC_MAC_M 0x00008000 +#define CRYPTO_AESCTL_CBC_MAC_S 15 // Field: [8:7] CTR_WIDTH // @@ -1550,31 +1550,31 @@ // 96_BIT 96 bits // 64_BIT 64 bits // 32_BIT 32 bits -#define CRYPTO_AESCTL_CTR_WIDTH_W 2 -#define CRYPTO_AESCTL_CTR_WIDTH_M 0x00000180 -#define CRYPTO_AESCTL_CTR_WIDTH_S 7 -#define CRYPTO_AESCTL_CTR_WIDTH_128_BIT 0x00000180 -#define CRYPTO_AESCTL_CTR_WIDTH_96_BIT 0x00000100 -#define CRYPTO_AESCTL_CTR_WIDTH_64_BIT 0x00000080 -#define CRYPTO_AESCTL_CTR_WIDTH_32_BIT 0x00000000 +#define CRYPTO_AESCTL_CTR_WIDTH_W 2 +#define CRYPTO_AESCTL_CTR_WIDTH_M 0x00000180 +#define CRYPTO_AESCTL_CTR_WIDTH_S 7 +#define CRYPTO_AESCTL_CTR_WIDTH_128_BIT 0x00000180 +#define CRYPTO_AESCTL_CTR_WIDTH_96_BIT 0x00000100 +#define CRYPTO_AESCTL_CTR_WIDTH_64_BIT 0x00000080 +#define CRYPTO_AESCTL_CTR_WIDTH_32_BIT 0x00000000 // Field: [6] CTR // // If set to 1, AES counter mode (CTR) is selected. // Note: This bit must also be set for GCM and CCM, when encryption/decryption // is required. -#define CRYPTO_AESCTL_CTR 0x00000040 -#define CRYPTO_AESCTL_CTR_BITN 6 -#define CRYPTO_AESCTL_CTR_M 0x00000040 -#define CRYPTO_AESCTL_CTR_S 6 +#define CRYPTO_AESCTL_CTR 0x00000040 +#define CRYPTO_AESCTL_CTR_BITN 6 +#define CRYPTO_AESCTL_CTR_M 0x00000040 +#define CRYPTO_AESCTL_CTR_S 6 // Field: [5] CBC // // If set to 1, cipher-block-chaining (CBC) mode is selected. -#define CRYPTO_AESCTL_CBC 0x00000020 -#define CRYPTO_AESCTL_CBC_BITN 5 -#define CRYPTO_AESCTL_CBC_M 0x00000020 -#define CRYPTO_AESCTL_CBC_S 5 +#define CRYPTO_AESCTL_CBC 0x00000020 +#define CRYPTO_AESCTL_CBC_BITN 5 +#define CRYPTO_AESCTL_CBC_M 0x00000020 +#define CRYPTO_AESCTL_CBC_S 5 // Field: [4:3] KEY_SIZE // @@ -1585,19 +1585,19 @@ // 01 = 128-bit // 10 = 192-bit // 11 = 256-bit -#define CRYPTO_AESCTL_KEY_SIZE_W 2 -#define CRYPTO_AESCTL_KEY_SIZE_M 0x00000018 -#define CRYPTO_AESCTL_KEY_SIZE_S 3 +#define CRYPTO_AESCTL_KEY_SIZE_W 2 +#define CRYPTO_AESCTL_KEY_SIZE_M 0x00000018 +#define CRYPTO_AESCTL_KEY_SIZE_S 3 // Field: [2] DIR // // If set to 1 an encrypt operation is performed. // If set to 0 a decrypt operation is performed. // This bit must be written with a 1 when CBC-MAC is selected. -#define CRYPTO_AESCTL_DIR 0x00000004 -#define CRYPTO_AESCTL_DIR_BITN 2 -#define CRYPTO_AESCTL_DIR_M 0x00000004 -#define CRYPTO_AESCTL_DIR_S 2 +#define CRYPTO_AESCTL_DIR 0x00000004 +#define CRYPTO_AESCTL_DIR_BITN 2 +#define CRYPTO_AESCTL_DIR_M 0x00000004 +#define CRYPTO_AESCTL_DIR_S 2 // Field: [1] INPUT_READY // @@ -1609,10 +1609,10 @@ // Note: For DMA operations, this bit is automatically controlled by the // EIP-120t. // After reset, this bit is 0. After writing a context, this bit becomes 1. -#define CRYPTO_AESCTL_INPUT_READY 0x00000002 -#define CRYPTO_AESCTL_INPUT_READY_BITN 1 -#define CRYPTO_AESCTL_INPUT_READY_M 0x00000002 -#define CRYPTO_AESCTL_INPUT_READY_S 1 +#define CRYPTO_AESCTL_INPUT_READY 0x00000002 +#define CRYPTO_AESCTL_INPUT_READY_BITN 1 +#define CRYPTO_AESCTL_INPUT_READY_M 0x00000002 +#define CRYPTO_AESCTL_INPUT_READY_S 1 // Field: [0] OUTPUT_READY // @@ -1623,10 +1623,10 @@ // Writing 1 to this bit is ignored. // Note: For DMA operations, this bit is automatically controlled by the // EIP-120t. -#define CRYPTO_AESCTL_OUTPUT_READY 0x00000001 -#define CRYPTO_AESCTL_OUTPUT_READY_BITN 0 -#define CRYPTO_AESCTL_OUTPUT_READY_M 0x00000001 -#define CRYPTO_AESCTL_OUTPUT_READY_S 0 +#define CRYPTO_AESCTL_OUTPUT_READY 0x00000001 +#define CRYPTO_AESCTL_OUTPUT_READY_BITN 0 +#define CRYPTO_AESCTL_OUTPUT_READY_M 0x00000001 +#define CRYPTO_AESCTL_OUTPUT_READY_S 0 //***************************************************************************** // @@ -1657,9 +1657,9 @@ // data length must be programmed in multiples of the block cipher size, 16 // bytes. // For a host read operation, these registers return all-0s. -#define CRYPTO_AESDATALEN0_C_LENGTH_W 32 -#define CRYPTO_AESDATALEN0_C_LENGTH_M 0xFFFFFFFF -#define CRYPTO_AESDATALEN0_C_LENGTH_S 0 +#define CRYPTO_AESDATALEN0_C_LENGTH_W 32 +#define CRYPTO_AESDATALEN0_C_LENGTH_M 0xFFFFFFFF +#define CRYPTO_AESDATALEN0_C_LENGTH_S 0 //***************************************************************************** // @@ -1690,9 +1690,9 @@ // data length must be programmed in multiples of the block cipher size, 16 // bytes. // For a host read operation, these registers return all-0s. -#define CRYPTO_AESDATALEN1_C_LENGTH_W 29 -#define CRYPTO_AESDATALEN1_C_LENGTH_M 0x1FFFFFFF -#define CRYPTO_AESDATALEN1_C_LENGTH_S 0 +#define CRYPTO_AESDATALEN1_C_LENGTH_W 29 +#define CRYPTO_AESDATALEN1_C_LENGTH_M 0x1FFFFFFF +#define CRYPTO_AESDATALEN1_C_LENGTH_S 0 //***************************************************************************** // @@ -1709,9 +1709,9 @@ // A write to this register triggers the engine to start using this context for // GCM and CCM. // For a host read operation, these registers return all-0s. -#define CRYPTO_AESAUTHLEN_AUTH_LENGTH_W 32 -#define CRYPTO_AESAUTHLEN_AUTH_LENGTH_M 0xFFFFFFFF -#define CRYPTO_AESAUTHLEN_AUTH_LENGTH_S 0 +#define CRYPTO_AESAUTHLEN_AUTH_LENGTH_W 32 +#define CRYPTO_AESAUTHLEN_AUTH_LENGTH_M 0xFFFFFFFF +#define CRYPTO_AESAUTHLEN_AUTH_LENGTH_S 0 //***************************************************************************** // @@ -1738,9 +1738,9 @@ // // Note: The AAD / authentication only data is not copied to the output buffer // but only used for authentication. -#define CRYPTO_AESDATAOUT0_DATA_W 32 -#define CRYPTO_AESDATAOUT0_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAOUT0_DATA_S 0 +#define CRYPTO_AESDATAOUT0_DATA_W 32 +#define CRYPTO_AESDATAOUT0_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT0_DATA_S 0 //***************************************************************************** // @@ -1779,9 +1779,9 @@ // mode, the remaining data in an unaligned data block is ignored. // Note: The AAD / authentication only data is not copied to the output buffer // but only used for authentication. -#define CRYPTO_AESDATAIN0_AES_DATA_IN_OUT_W 32 -#define CRYPTO_AESDATAIN0_AES_DATA_IN_OUT_M 0xFFFFFFFF -#define CRYPTO_AESDATAIN0_AES_DATA_IN_OUT_S 0 +#define CRYPTO_AESDATAIN0_AES_DATA_IN_OUT_W 32 +#define CRYPTO_AESDATAIN0_AES_DATA_IN_OUT_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN0_AES_DATA_IN_OUT_S 0 //***************************************************************************** // @@ -1808,9 +1808,9 @@ // // Note: The AAD / authentication only data is not copied to the output buffer // but only used for authentication. -#define CRYPTO_AESDATAOUT1_DATA_W 32 -#define CRYPTO_AESDATAOUT1_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAOUT1_DATA_S 0 +#define CRYPTO_AESDATAOUT1_DATA_W 32 +#define CRYPTO_AESDATAOUT1_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT1_DATA_S 0 //***************************************************************************** // @@ -1849,9 +1849,9 @@ // mode, the remaining data in an unaligned data block is ignored. // Note: The AAD / authentication only data is not copied to the output buffer // but only used for authentication. -#define CRYPTO_AESDATAIN1_AES_DATA_IN_OUT_W 32 -#define CRYPTO_AESDATAIN1_AES_DATA_IN_OUT_M 0xFFFFFFFF -#define CRYPTO_AESDATAIN1_AES_DATA_IN_OUT_S 0 +#define CRYPTO_AESDATAIN1_AES_DATA_IN_OUT_W 32 +#define CRYPTO_AESDATAIN1_AES_DATA_IN_OUT_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN1_AES_DATA_IN_OUT_S 0 //***************************************************************************** // @@ -1878,9 +1878,9 @@ // // Note: The AAD / authentication only data is not copied to the output buffer // but only used for authentication. -#define CRYPTO_AESDATAOUT2_DATA_W 32 -#define CRYPTO_AESDATAOUT2_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAOUT2_DATA_S 0 +#define CRYPTO_AESDATAOUT2_DATA_W 32 +#define CRYPTO_AESDATAOUT2_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT2_DATA_S 0 //***************************************************************************** // @@ -1919,9 +1919,9 @@ // mode, the remaining data in an unaligned data block is ignored. // Note: The AAD / authentication only data is not copied to the output buffer // but only used for authentication. -#define CRYPTO_AESDATAIN2_AES_DATA_IN_OUT_W 32 -#define CRYPTO_AESDATAIN2_AES_DATA_IN_OUT_M 0xFFFFFFFF -#define CRYPTO_AESDATAIN2_AES_DATA_IN_OUT_S 0 +#define CRYPTO_AESDATAIN2_AES_DATA_IN_OUT_W 32 +#define CRYPTO_AESDATAIN2_AES_DATA_IN_OUT_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN2_AES_DATA_IN_OUT_S 0 //***************************************************************************** // @@ -1948,9 +1948,9 @@ // // Note: The AAD / authentication only data is not copied to the output buffer // but only used for authentication. -#define CRYPTO_AESDATAOUT3_DATA_W 32 -#define CRYPTO_AESDATAOUT3_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAOUT3_DATA_S 0 +#define CRYPTO_AESDATAOUT3_DATA_W 32 +#define CRYPTO_AESDATAOUT3_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT3_DATA_S 0 //***************************************************************************** // @@ -1989,9 +1989,9 @@ // mode, the remaining data in an unaligned data block is ignored. // Note: The AAD / authentication only data is not copied to the output buffer // but only used for authentication. -#define CRYPTO_AESDATAIN3_AES_DATA_IN_OUT_W 32 -#define CRYPTO_AESDATAIN3_AES_DATA_IN_OUT_M 0xFFFFFFFF -#define CRYPTO_AESDATAIN3_AES_DATA_IN_OUT_S 0 +#define CRYPTO_AESDATAIN3_AES_DATA_IN_OUT_W 32 +#define CRYPTO_AESDATAIN3_AES_DATA_IN_OUT_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN3_AES_DATA_IN_OUT_S 0 //***************************************************************************** // @@ -2010,9 +2010,9 @@ // the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for // operations/modes that do not return a TAG, reads from this register return // data from the IV register. -#define CRYPTO_AESTAGOUT0_AES_TAG_W 32 -#define CRYPTO_AESTAGOUT0_AES_TAG_M 0xFFFFFFFF -#define CRYPTO_AESTAGOUT0_AES_TAG_S 0 +#define CRYPTO_AESTAGOUT0_AES_TAG_W 32 +#define CRYPTO_AESTAGOUT0_AES_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT0_AES_TAG_S 0 //***************************************************************************** // @@ -2031,9 +2031,9 @@ // the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for // operations/modes that do not return a TAG, reads from this register return // data from the IV register. -#define CRYPTO_AESTAGOUT1_AES_TAG_W 32 -#define CRYPTO_AESTAGOUT1_AES_TAG_M 0xFFFFFFFF -#define CRYPTO_AESTAGOUT1_AES_TAG_S 0 +#define CRYPTO_AESTAGOUT1_AES_TAG_W 32 +#define CRYPTO_AESTAGOUT1_AES_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT1_AES_TAG_S 0 //***************************************************************************** // @@ -2052,9 +2052,9 @@ // the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for // operations/modes that do not return a TAG, reads from this register return // data from the IV register. -#define CRYPTO_AESTAGOUT2_AES_TAG_W 32 -#define CRYPTO_AESTAGOUT2_AES_TAG_M 0xFFFFFFFF -#define CRYPTO_AESTAGOUT2_AES_TAG_S 0 +#define CRYPTO_AESTAGOUT2_AES_TAG_W 32 +#define CRYPTO_AESTAGOUT2_AES_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT2_AES_TAG_S 0 //***************************************************************************** // @@ -2073,9 +2073,9 @@ // the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for // operations/modes that do not return a TAG, reads from this register return // data from the IV register. -#define CRYPTO_AESTAGOUT3_AES_TAG_W 32 -#define CRYPTO_AESTAGOUT3_AES_TAG_M 0xFFFFFFFF -#define CRYPTO_AESTAGOUT3_AES_TAG_S 0 +#define CRYPTO_AESTAGOUT3_AES_TAG_W 32 +#define CRYPTO_AESTAGOUT3_AES_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT3_AES_TAG_S 0 //***************************************************************************** // @@ -2100,9 +2100,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN1_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN1_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN1_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN1_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN1_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN1_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2127,9 +2127,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN2_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN2_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN2_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN2_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN2_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN2_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2154,9 +2154,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN3_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN3_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN3_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN3_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN3_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN3_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2181,9 +2181,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN4_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN4_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN4_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN4_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN4_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN4_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2208,9 +2208,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN5_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN5_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN5_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN5_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN5_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN5_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2235,9 +2235,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN6_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN6_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN6_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN6_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN6_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN6_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2262,9 +2262,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN7_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN7_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN7_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN7_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN7_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN7_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2289,9 +2289,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN8_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN8_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN8_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN8_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN8_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN8_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2316,9 +2316,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN9_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN9_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN9_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN9_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN9_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN9_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2343,9 +2343,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN10_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN10_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN10_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN10_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN10_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN10_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2370,9 +2370,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN11_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN11_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN11_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN11_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN11_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN11_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2397,9 +2397,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN12_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN12_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN12_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN12_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN12_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN12_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2424,9 +2424,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN13_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN13_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN13_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN13_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN13_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN13_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2451,9 +2451,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN14_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN14_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN14_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN14_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN14_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN14_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2478,9 +2478,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN15_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN15_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN15_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN15_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN15_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN15_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2505,9 +2505,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN16_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN16_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN16_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN16_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN16_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN16_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2532,9 +2532,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN17_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN17_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN17_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN17_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN17_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN17_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2559,9 +2559,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN18_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN18_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN18_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN18_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN18_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN18_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2586,9 +2586,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN19_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN19_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN19_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN19_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN19_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN19_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2613,9 +2613,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN20_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN20_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN20_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN20_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN20_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN20_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2640,9 +2640,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN21_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN21_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN21_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN21_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN21_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN21_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2667,9 +2667,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN22_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN22_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN22_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN22_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN22_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN22_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2694,9 +2694,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN23_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN23_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN23_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN23_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN23_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN23_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2721,9 +2721,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN24_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN24_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN24_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN24_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN24_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN24_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2748,9 +2748,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN25_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN25_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN25_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN25_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN25_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN25_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2775,9 +2775,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN26_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN26_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN26_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN26_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN26_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN26_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2802,9 +2802,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN27_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN27_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN27_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN27_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN27_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN27_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2829,9 +2829,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN28_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN28_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN28_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN28_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN28_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN28_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2856,9 +2856,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN29_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN29_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN29_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN29_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN29_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN29_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2883,9 +2883,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN30_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN30_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN30_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN30_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN30_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN30_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2910,9 +2910,9 @@ // significant bits of data must be written, but they must be padded with 0s to // the next 32-bit boundary. // Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN31_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN31_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN31_HASH_DATA_IN_S 0 +#define CRYPTO_HASHDATAIN31_HASH_DATA_IN_W 32 +#define CRYPTO_HASHDATAIN31_HASH_DATA_IN_M 0xFFFFFFFF +#define CRYPTO_HASHDATAIN31_HASH_DATA_IN_S 0 //***************************************************************************** // @@ -2931,10 +2931,10 @@ // aligned and calculates the intermediate digest. // This bit is automatically cleared when the last DMA data block is arrived in // the hash engine. -#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE 0x00000080 -#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_BITN 7 -#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_M 0x00000080 -#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_S 7 +#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE 0x00000080 +#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_BITN 7 +#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_M 0x00000080 +#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_S 7 // Field: [6] GET_DIGEST // @@ -2953,10 +2953,10 @@ // has processed the contents of the HASHDATAINn register. In the period // between this bit is set by the host and the actual HASHDATAINn processing, // this bit reads 1. -#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST 0x00000040 -#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST_BITN 6 -#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST_M 0x00000040 -#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST_S 6 +#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST 0x00000040 +#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST_BITN 6 +#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST_M 0x00000040 +#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST_S 6 // Field: [5] PAD_MESSAGE // @@ -2979,10 +2979,10 @@ // This bit is automatically cleared (i.e. reads 0) by the hash engine. This // bit reads 1 between the time it was set by the host and the hash engine // interpreted its value. -#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE 0x00000020 -#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE_BITN 5 -#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE_M 0x00000020 -#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE_S 5 +#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE 0x00000020 +#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE_BITN 5 +#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE_M 0x00000020 +#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE_S 5 // Field: [2] RFD_IN // @@ -2995,10 +2995,10 @@ // When 0, the input buffer of the hash engine is processing the data that is // currently in HASHDATAINn; writing new data to these registers is not // allowed. -#define CRYPTO_HASHIOBUFCTRL_RFD_IN 0x00000004 -#define CRYPTO_HASHIOBUFCTRL_RFD_IN_BITN 2 -#define CRYPTO_HASHIOBUFCTRL_RFD_IN_M 0x00000004 -#define CRYPTO_HASHIOBUFCTRL_RFD_IN_S 2 +#define CRYPTO_HASHIOBUFCTRL_RFD_IN 0x00000004 +#define CRYPTO_HASHIOBUFCTRL_RFD_IN_BITN 2 +#define CRYPTO_HASHIOBUFCTRL_RFD_IN_M 0x00000004 +#define CRYPTO_HASHIOBUFCTRL_RFD_IN_S 2 // Field: [1] DATA_IN_AV // @@ -3015,10 +3015,10 @@ // starts processing the HASHDATAINn contents. This bit reads 1 between the // time it was set by the host and the hash engine actually starts processing // the input data block. -#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV 0x00000002 -#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV_BITN 1 -#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV_M 0x00000002 -#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV_S 1 +#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV 0x00000002 +#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV_BITN 1 +#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV_M 0x00000002 +#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV_S 1 // Field: [0] OUTPUT_FULL // @@ -3037,10 +3037,10 @@ // Writing 0 to this bit has no effect. // Note: If this bit is asserted (1) no new operation should be started before // the digest is retrieved from the hash engine and this bit is cleared (0). -#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL 0x00000001 -#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_BITN 0 -#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_M 0x00000001 -#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_S 0 +#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL 0x00000001 +#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_BITN 0 +#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_M 0x00000001 +#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_S 0 //***************************************************************************** // @@ -3050,34 +3050,34 @@ // Field: [6] SHA384_MODE // // The host must write this bit with 1 prior to processing a SHA 384 session. -#define CRYPTO_HASHMODE_SHA384_MODE 0x00000040 -#define CRYPTO_HASHMODE_SHA384_MODE_BITN 6 -#define CRYPTO_HASHMODE_SHA384_MODE_M 0x00000040 -#define CRYPTO_HASHMODE_SHA384_MODE_S 6 +#define CRYPTO_HASHMODE_SHA384_MODE 0x00000040 +#define CRYPTO_HASHMODE_SHA384_MODE_BITN 6 +#define CRYPTO_HASHMODE_SHA384_MODE_M 0x00000040 +#define CRYPTO_HASHMODE_SHA384_MODE_S 6 // Field: [5] SHA512_MODE // // The host must write this bit with 1 prior to processing a SHA 512 session. -#define CRYPTO_HASHMODE_SHA512_MODE 0x00000020 -#define CRYPTO_HASHMODE_SHA512_MODE_BITN 5 -#define CRYPTO_HASHMODE_SHA512_MODE_M 0x00000020 -#define CRYPTO_HASHMODE_SHA512_MODE_S 5 +#define CRYPTO_HASHMODE_SHA512_MODE 0x00000020 +#define CRYPTO_HASHMODE_SHA512_MODE_BITN 5 +#define CRYPTO_HASHMODE_SHA512_MODE_M 0x00000020 +#define CRYPTO_HASHMODE_SHA512_MODE_S 5 // Field: [4] SHA224_MODE // // The host must write this bit with 1 prior to processing a SHA 224 session. -#define CRYPTO_HASHMODE_SHA224_MODE 0x00000010 -#define CRYPTO_HASHMODE_SHA224_MODE_BITN 4 -#define CRYPTO_HASHMODE_SHA224_MODE_M 0x00000010 -#define CRYPTO_HASHMODE_SHA224_MODE_S 4 +#define CRYPTO_HASHMODE_SHA224_MODE 0x00000010 +#define CRYPTO_HASHMODE_SHA224_MODE_BITN 4 +#define CRYPTO_HASHMODE_SHA224_MODE_M 0x00000010 +#define CRYPTO_HASHMODE_SHA224_MODE_S 4 // Field: [3] SHA256_MODE // // The host must write this bit with 1 prior to processing a SHA 256 session. -#define CRYPTO_HASHMODE_SHA256_MODE 0x00000008 -#define CRYPTO_HASHMODE_SHA256_MODE_BITN 3 -#define CRYPTO_HASHMODE_SHA256_MODE_M 0x00000008 -#define CRYPTO_HASHMODE_SHA256_MODE_S 3 +#define CRYPTO_HASHMODE_SHA256_MODE 0x00000008 +#define CRYPTO_HASHMODE_SHA256_MODE_BITN 3 +#define CRYPTO_HASHMODE_SHA256_MODE_M 0x00000008 +#define CRYPTO_HASHMODE_SHA256_MODE_S 3 // Field: [0] NEW_HASH // @@ -3089,10 +3089,10 @@ // engine will start processing with the digest that is currently in its // internal HASHDIGESTn registers. // This bit is automatically cleared when hash processing is started. -#define CRYPTO_HASHMODE_NEW_HASH 0x00000001 -#define CRYPTO_HASHMODE_NEW_HASH_BITN 0 -#define CRYPTO_HASHMODE_NEW_HASH_M 0x00000001 -#define CRYPTO_HASHMODE_NEW_HASH_S 0 +#define CRYPTO_HASHMODE_NEW_HASH 0x00000001 +#define CRYPTO_HASHMODE_NEW_HASH_BITN 0 +#define CRYPTO_HASHMODE_NEW_HASH_M 0x00000001 +#define CRYPTO_HASHMODE_NEW_HASH_S 0 //***************************************************************************** // @@ -3134,9 +3134,9 @@ // host read operations from these register locations will return 0s. // Note: When getting data from DMA, this register must be programmed before // DMA is programmed to start. -#define CRYPTO_HASHINLENL_LENGTH_IN_W 32 -#define CRYPTO_HASHINLENL_LENGTH_IN_M 0xFFFFFFFF -#define CRYPTO_HASHINLENL_LENGTH_IN_S 0 +#define CRYPTO_HASHINLENL_LENGTH_IN_W 32 +#define CRYPTO_HASHINLENL_LENGTH_IN_M 0xFFFFFFFF +#define CRYPTO_HASHINLENL_LENGTH_IN_S 0 //***************************************************************************** // @@ -3178,9 +3178,9 @@ // host read operations from these register locations will return 0s. // Note: When getting data from DMA, this register must be programmed before // DMA is programmed to start. -#define CRYPTO_HASHINLENH_LENGTH_IN_W 32 -#define CRYPTO_HASHINLENH_LENGTH_IN_M 0xFFFFFFFF -#define CRYPTO_HASHINLENH_LENGTH_IN_S 0 +#define CRYPTO_HASHINLENH_LENGTH_IN_W 32 +#define CRYPTO_HASHINLENH_LENGTH_IN_M 0xFFFFFFFF +#define CRYPTO_HASHINLENH_LENGTH_IN_S 0 //***************************************************************************** // @@ -3206,9 +3206,9 @@ // Reading from these registers provides the intermediate hash result // (non-final hash operation) or the final hash result (final hash operation) // after data processing. -#define CRYPTO_HASHDIGESTA_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTA_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTA_HASH_DIGEST_S 0 +#define CRYPTO_HASHDIGESTA_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTA_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTA_HASH_DIGEST_S 0 //***************************************************************************** // @@ -3234,9 +3234,9 @@ // Reading from these registers provides the intermediate hash result // (non-final hash operation) or the final hash result (final hash operation) // after data processing. -#define CRYPTO_HASHDIGESTB_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTB_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTB_HASH_DIGEST_S 0 +#define CRYPTO_HASHDIGESTB_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTB_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTB_HASH_DIGEST_S 0 //***************************************************************************** // @@ -3262,9 +3262,9 @@ // Reading from these registers provides the intermediate hash result // (non-final hash operation) or the final hash result (final hash operation) // after data processing. -#define CRYPTO_HASHDIGESTC_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTC_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTC_HASH_DIGEST_S 0 +#define CRYPTO_HASHDIGESTC_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTC_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTC_HASH_DIGEST_S 0 //***************************************************************************** // @@ -3290,9 +3290,9 @@ // Reading from these registers provides the intermediate hash result // (non-final hash operation) or the final hash result (final hash operation) // after data processing. -#define CRYPTO_HASHDIGESTD_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTD_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTD_HASH_DIGEST_S 0 +#define CRYPTO_HASHDIGESTD_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTD_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTD_HASH_DIGEST_S 0 //***************************************************************************** // @@ -3318,9 +3318,9 @@ // Reading from these registers provides the intermediate hash result // (non-final hash operation) or the final hash result (final hash operation) // after data processing. -#define CRYPTO_HASHDIGESTE_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTE_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTE_HASH_DIGEST_S 0 +#define CRYPTO_HASHDIGESTE_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTE_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTE_HASH_DIGEST_S 0 //***************************************************************************** // @@ -3346,9 +3346,9 @@ // Reading from these registers provides the intermediate hash result // (non-final hash operation) or the final hash result (final hash operation) // after data processing. -#define CRYPTO_HASHDIGESTF_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTF_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTF_HASH_DIGEST_S 0 +#define CRYPTO_HASHDIGESTF_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTF_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTF_HASH_DIGEST_S 0 //***************************************************************************** // @@ -3374,9 +3374,9 @@ // Reading from these registers provides the intermediate hash result // (non-final hash operation) or the final hash result (final hash operation) // after data processing. -#define CRYPTO_HASHDIGESTG_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTG_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTG_HASH_DIGEST_S 0 +#define CRYPTO_HASHDIGESTG_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTG_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTG_HASH_DIGEST_S 0 //***************************************************************************** // @@ -3402,9 +3402,9 @@ // Reading from these registers provides the intermediate hash result // (non-final hash operation) or the final hash result (final hash operation) // after data processing. -#define CRYPTO_HASHDIGESTH_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTH_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTH_HASH_DIGEST_S 0 +#define CRYPTO_HASHDIGESTH_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTH_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTH_HASH_DIGEST_S 0 //***************************************************************************** // @@ -3430,9 +3430,9 @@ // Reading from these registers provides the intermediate hash result // (non-final hash operation) or the final hash result (final hash operation) // after data processing. -#define CRYPTO_HASHDIGESTI_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTI_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTI_HASH_DIGEST_S 0 +#define CRYPTO_HASHDIGESTI_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTI_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTI_HASH_DIGEST_S 0 //***************************************************************************** // @@ -3458,9 +3458,9 @@ // Reading from these registers provides the intermediate hash result // (non-final hash operation) or the final hash result (final hash operation) // after data processing. -#define CRYPTO_HASHDIGESTJ_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTJ_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTJ_HASH_DIGEST_S 0 +#define CRYPTO_HASHDIGESTJ_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTJ_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTJ_HASH_DIGEST_S 0 //***************************************************************************** // @@ -3486,9 +3486,9 @@ // Reading from these registers provides the intermediate hash result // (non-final hash operation) or the final hash result (final hash operation) // after data processing. -#define CRYPTO_HASHDIGESTK_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTK_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTK_HASH_DIGEST_S 0 +#define CRYPTO_HASHDIGESTK_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTK_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTK_HASH_DIGEST_S 0 //***************************************************************************** // @@ -3514,9 +3514,9 @@ // Reading from these registers provides the intermediate hash result // (non-final hash operation) or the final hash result (final hash operation) // after data processing. -#define CRYPTO_HASHDIGESTL_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTL_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTL_HASH_DIGEST_S 0 +#define CRYPTO_HASHDIGESTL_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTL_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTL_HASH_DIGEST_S 0 //***************************************************************************** // @@ -3542,9 +3542,9 @@ // Reading from these registers provides the intermediate hash result // (non-final hash operation) or the final hash result (final hash operation) // after data processing. -#define CRYPTO_HASHDIGESTM_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTM_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTM_HASH_DIGEST_S 0 +#define CRYPTO_HASHDIGESTM_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTM_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTM_HASH_DIGEST_S 0 //***************************************************************************** // @@ -3570,9 +3570,9 @@ // Reading from these registers provides the intermediate hash result // (non-final hash operation) or the final hash result (final hash operation) // after data processing. -#define CRYPTO_HASHDIGESTN_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTN_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTN_HASH_DIGEST_S 0 +#define CRYPTO_HASHDIGESTN_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTN_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTN_HASH_DIGEST_S 0 //***************************************************************************** // @@ -3598,9 +3598,9 @@ // Reading from these registers provides the intermediate hash result // (non-final hash operation) or the final hash result (final hash operation) // after data processing. -#define CRYPTO_HASHDIGESTO_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTO_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTO_HASH_DIGEST_S 0 +#define CRYPTO_HASHDIGESTO_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTO_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTO_HASH_DIGEST_S 0 //***************************************************************************** // @@ -3626,9 +3626,9 @@ // Reading from these registers provides the intermediate hash result // (non-final hash operation) or the final hash result (final hash operation) // after data processing. -#define CRYPTO_HASHDIGESTP_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTP_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTP_HASH_DIGEST_S 0 +#define CRYPTO_HASHDIGESTP_HASH_DIGEST_W 32 +#define CRYPTO_HASHDIGESTP_HASH_DIGEST_M 0xFFFFFFFF +#define CRYPTO_HASHDIGESTP_HASH_DIGEST_S 0 //***************************************************************************** // @@ -3642,10 +3642,10 @@ // The maximum transfer size to DMA engine is set to 64 bytes for reading and // 32 bytes for writing (the latter is only applicable if the hash result is // written out through the DMA). -#define CRYPTO_ALGSEL_HASH_SHA_512 0x100000000 -#define CRYPTO_ALGSEL_HASH_SHA_512_BITN 32 -#define CRYPTO_ALGSEL_HASH_SHA_512_M 0x100000000 -#define CRYPTO_ALGSEL_HASH_SHA_512_S 32 +#define CRYPTO_ALGSEL_HASH_SHA_512 0x100000000 +#define CRYPTO_ALGSEL_HASH_SHA_512_BITN 32 +#define CRYPTO_ALGSEL_HASH_SHA_512_M 0x100000000 +#define CRYPTO_ALGSEL_HASH_SHA_512_S 32 // Field: [31] TAG // @@ -3656,10 +3656,10 @@ // any other selected module, setting this bit only allows a DMA that reads the // TAG. No data allowed to be transferred to or from the selected module via // the DMA. -#define CRYPTO_ALGSEL_TAG 0x80000000 -#define CRYPTO_ALGSEL_TAG_BITN 31 -#define CRYPTO_ALGSEL_TAG_M 0x80000000 -#define CRYPTO_ALGSEL_TAG_S 31 +#define CRYPTO_ALGSEL_TAG 0x80000000 +#define CRYPTO_ALGSEL_TAG_BITN 31 +#define CRYPTO_ALGSEL_TAG_M 0x80000000 +#define CRYPTO_ALGSEL_TAG_S 31 // Field: [2] HASH_SHA_256 // @@ -3668,30 +3668,30 @@ // The maximum transfer size to DMA engine is set to 64 bytes for reading and // 32 bytes for writing (the latter is only applicable if the hash result is // written out through the DMA). -#define CRYPTO_ALGSEL_HASH_SHA_256 0x00000004 -#define CRYPTO_ALGSEL_HASH_SHA_256_BITN 2 -#define CRYPTO_ALGSEL_HASH_SHA_256_M 0x00000004 -#define CRYPTO_ALGSEL_HASH_SHA_256_S 2 +#define CRYPTO_ALGSEL_HASH_SHA_256 0x00000004 +#define CRYPTO_ALGSEL_HASH_SHA_256_BITN 2 +#define CRYPTO_ALGSEL_HASH_SHA_256_M 0x00000004 +#define CRYPTO_ALGSEL_HASH_SHA_256_S 2 // Field: [1] AES // // If set to one, selects the AES engine as source/destination for the DMA // The read and write maximum transfer size to the DMA engine is set to 16 // bytes. -#define CRYPTO_ALGSEL_AES 0x00000002 -#define CRYPTO_ALGSEL_AES_BITN 1 -#define CRYPTO_ALGSEL_AES_M 0x00000002 -#define CRYPTO_ALGSEL_AES_S 1 +#define CRYPTO_ALGSEL_AES 0x00000002 +#define CRYPTO_ALGSEL_AES_BITN 1 +#define CRYPTO_ALGSEL_AES_M 0x00000002 +#define CRYPTO_ALGSEL_AES_S 1 // Field: [0] KEY_STORE // // If set to one, selects the Key Store as destination for the DMA // The maximum transfer size to DMA engine is set to 32 bytes (however // transfers of 16, 24 and 32 bytes are allowed) -#define CRYPTO_ALGSEL_KEY_STORE 0x00000001 -#define CRYPTO_ALGSEL_KEY_STORE_BITN 0 -#define CRYPTO_ALGSEL_KEY_STORE_M 0x00000001 -#define CRYPTO_ALGSEL_KEY_STORE_S 0 +#define CRYPTO_ALGSEL_KEY_STORE 0x00000001 +#define CRYPTO_ALGSEL_KEY_STORE_BITN 0 +#define CRYPTO_ALGSEL_KEY_STORE_M 0x00000001 +#define CRYPTO_ALGSEL_KEY_STORE_S 0 //***************************************************************************** // @@ -3704,10 +3704,10 @@ // area as destination. // 0 : transfers use 'USER' type access. // 1 : transfers use 'PRIVILEGED' type access. -#define CRYPTO_DMAPROTCTL_PROT_EN 0x00000001 -#define CRYPTO_DMAPROTCTL_PROT_EN_BITN 0 -#define CRYPTO_DMAPROTCTL_PROT_EN_M 0x00000001 -#define CRYPTO_DMAPROTCTL_PROT_EN_S 0 +#define CRYPTO_DMAPROTCTL_PROT_EN 0x00000001 +#define CRYPTO_DMAPROTCTL_PROT_EN_BITN 0 +#define CRYPTO_DMAPROTCTL_PROT_EN_M 0x00000001 +#define CRYPTO_DMAPROTCTL_PROT_EN_S 0 //***************************************************************************** // @@ -3723,10 +3723,10 @@ // flags; therefore, the keys must be reloaded to the key store module. // Writing 0 has no effect. // The bit is self cleared after executing the reset. -#define CRYPTO_SWRESET_SW_RESET 0x00000001 -#define CRYPTO_SWRESET_SW_RESET_BITN 0 -#define CRYPTO_SWRESET_SW_RESET_M 0x00000001 -#define CRYPTO_SWRESET_SW_RESET_S 0 +#define CRYPTO_SWRESET_SW_RESET 0x00000001 +#define CRYPTO_SWRESET_SW_RESET_BITN 0 +#define CRYPTO_SWRESET_SW_RESET_M 0x00000001 +#define CRYPTO_SWRESET_SW_RESET_S 0 //***************************************************************************** // @@ -3739,10 +3739,10 @@ // If this bit is set to 1, the interrupt is a level interrupt that must be // cleared by writing the interrupt clear register. // This bit is applicable for both interrupt output signals. -#define CRYPTO_IRQTYPE_LEVEL 0x00000001 -#define CRYPTO_IRQTYPE_LEVEL_BITN 0 -#define CRYPTO_IRQTYPE_LEVEL_M 0x00000001 -#define CRYPTO_IRQTYPE_LEVEL_S 0 +#define CRYPTO_IRQTYPE_LEVEL 0x00000001 +#define CRYPTO_IRQTYPE_LEVEL_BITN 0 +#define CRYPTO_IRQTYPE_LEVEL_M 0x00000001 +#define CRYPTO_IRQTYPE_LEVEL_S 0 //***************************************************************************** // @@ -3754,20 +3754,20 @@ // If this bit is set to 0, the DMA input done (irq_dma_in_done) interrupt // output is disabled and remains 0. // If this bit is set to 1, the DMA input done interrupt output is enabled. -#define CRYPTO_IRQEN_DMA_IN_DONE 0x00000002 -#define CRYPTO_IRQEN_DMA_IN_DONE_BITN 1 -#define CRYPTO_IRQEN_DMA_IN_DONE_M 0x00000002 -#define CRYPTO_IRQEN_DMA_IN_DONE_S 1 +#define CRYPTO_IRQEN_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQEN_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQEN_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQEN_DMA_IN_DONE_S 1 // Field: [0] RESULT_AVAIL // // If this bit is set to 0, the result available (irq_result_av) interrupt // output is disabled and remains 0. // If this bit is set to 1, the result available interrupt output is enabled. -#define CRYPTO_IRQEN_RESULT_AVAIL 0x00000001 -#define CRYPTO_IRQEN_RESULT_AVAIL_BITN 0 -#define CRYPTO_IRQEN_RESULT_AVAIL_M 0x00000001 -#define CRYPTO_IRQEN_RESULT_AVAIL_S 0 +#define CRYPTO_IRQEN_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQEN_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQEN_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQEN_RESULT_AVAIL_S 0 //***************************************************************************** // @@ -3778,28 +3778,28 @@ // // If 1 is written to this bit, the DMA bus error status is cleared. // Writing 0 has no effect. -#define CRYPTO_IRQCLR_DMA_BUS_ERR 0x80000000 -#define CRYPTO_IRQCLR_DMA_BUS_ERR_BITN 31 -#define CRYPTO_IRQCLR_DMA_BUS_ERR_M 0x80000000 -#define CRYPTO_IRQCLR_DMA_BUS_ERR_S 31 +#define CRYPTO_IRQCLR_DMA_BUS_ERR 0x80000000 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_BITN 31 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_M 0x80000000 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_S 31 // Field: [30] KEY_ST_WR_ERR // // If 1 is written to this bit, the key store write error status is cleared. // Writing 0 has no effect. -#define CRYPTO_IRQCLR_KEY_ST_WR_ERR 0x40000000 -#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_BITN 30 -#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_M 0x40000000 -#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_S 30 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR 0x40000000 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_BITN 30 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_M 0x40000000 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_S 30 // Field: [29] KEY_ST_RD_ERR // // If 1 is written to this bit, the key store read error status is cleared. // Writing 0 has no effect. -#define CRYPTO_IRQCLR_KEY_ST_RD_ERR 0x20000000 -#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_BITN 29 -#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_M 0x20000000 -#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_S 29 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR 0x20000000 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_BITN 29 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_M 0x20000000 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_S 29 // Field: [1] DMA_IN_DONE // @@ -3808,10 +3808,10 @@ // Writing 0 has no effect. // Note that clearing an interrupt makes sense only if the interrupt output is // programmed as level (refer to IRQTYPE). -#define CRYPTO_IRQCLR_DMA_IN_DONE 0x00000002 -#define CRYPTO_IRQCLR_DMA_IN_DONE_BITN 1 -#define CRYPTO_IRQCLR_DMA_IN_DONE_M 0x00000002 -#define CRYPTO_IRQCLR_DMA_IN_DONE_S 1 +#define CRYPTO_IRQCLR_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQCLR_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQCLR_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQCLR_DMA_IN_DONE_S 1 // Field: [0] RESULT_AVAIL // @@ -3820,10 +3820,10 @@ // Writing 0 has no effect. // Note that clearing an interrupt makes sense only if the interrupt output is // programmed as level (refer to IRQTYPE). -#define CRYPTO_IRQCLR_RESULT_AVAIL 0x00000001 -#define CRYPTO_IRQCLR_RESULT_AVAIL_BITN 0 -#define CRYPTO_IRQCLR_RESULT_AVAIL_M 0x00000001 -#define CRYPTO_IRQCLR_RESULT_AVAIL_S 0 +#define CRYPTO_IRQCLR_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQCLR_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQCLR_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQCLR_RESULT_AVAIL_S 0 //***************************************************************************** // @@ -3839,10 +3839,10 @@ // DMA data in done (irq_dma_in_done) interrupt is not needed. If it is // programmed to level, clearing the interrupt output should be done by writing // the interrupt clear register (IRQCLR.DMA_IN_DONE). -#define CRYPTO_IRQSET_DMA_IN_DONE 0x00000002 -#define CRYPTO_IRQSET_DMA_IN_DONE_BITN 1 -#define CRYPTO_IRQSET_DMA_IN_DONE_M 0x00000002 -#define CRYPTO_IRQSET_DMA_IN_DONE_S 1 +#define CRYPTO_IRQSET_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQSET_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQSET_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQSET_DMA_IN_DONE_S 1 // Field: [0] RESULT_AVAIL // @@ -3853,10 +3853,10 @@ // result available (irq_result_av) interrupt is not needed. If it is // programmed to level, clearing the interrupt output should be done by writing // the interrupt clear register (IRQCLR.RESULT_AVAIL). -#define CRYPTO_IRQSET_RESULT_AVAIL 0x00000001 -#define CRYPTO_IRQSET_RESULT_AVAIL_BITN 0 -#define CRYPTO_IRQSET_RESULT_AVAIL_M 0x00000001 -#define CRYPTO_IRQSET_RESULT_AVAIL_S 0 +#define CRYPTO_IRQSET_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQSET_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQSET_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQSET_RESULT_AVAIL_S 0 //***************************************************************************** // @@ -3870,10 +3870,10 @@ // IRQCLR.DMA_BUS_ERR // Note: This error is asserted if an error is detected on the AHB master // interface during a DMA operation. -#define CRYPTO_IRQSTAT_DMA_BUS_ERR 0x80000000 -#define CRYPTO_IRQSTAT_DMA_BUS_ERR_BITN 31 -#define CRYPTO_IRQSTAT_DMA_BUS_ERR_M 0x80000000 -#define CRYPTO_IRQSTAT_DMA_BUS_ERR_S 31 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR 0x80000000 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_BITN 31 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_M 0x80000000 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_S 31 // Field: [30] KEY_ST_WR_ERR // @@ -3882,10 +3882,10 @@ // it is cleared through the IRQCLR.KEY_ST_WR_ERR register. // Note: This error is asserted if a DMA operation does not cover a full key // area or more areas are written than expected. -#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR 0x40000000 -#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_BITN 30 -#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M 0x40000000 -#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_S 30 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR 0x40000000 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_BITN 30 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M 0x40000000 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_S 30 // Field: [29] KEY_ST_RD_ERR // @@ -3894,30 +3894,30 @@ // is held until it is cleared through the IRQCLR.KEY_ST_RD_ERR register. // Note: This error is asserted if a key location is selected in the key store // that is not available. -#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR 0x20000000 -#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_BITN 29 -#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M 0x20000000 -#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_S 29 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR 0x20000000 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_BITN 29 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M 0x20000000 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_S 29 // Field: [1] DMA_IN_DONE // // This read only bit returns the actual DMA data in done (irq_data_in_done) // interrupt status of the DMA data in done interrupt output pin // (irq_data_in_done). -#define CRYPTO_IRQSTAT_DMA_IN_DONE 0x00000002 -#define CRYPTO_IRQSTAT_DMA_IN_DONE_BITN 1 -#define CRYPTO_IRQSTAT_DMA_IN_DONE_M 0x00000002 -#define CRYPTO_IRQSTAT_DMA_IN_DONE_S 1 +#define CRYPTO_IRQSTAT_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_S 1 // Field: [0] RESULT_AVAIL // // This read only bit returns the actual result available (irq_result_av) // interrupt status of the result available interrupt output pin // (irq_result_av). -#define CRYPTO_IRQSTAT_RESULT_AVAIL 0x00000001 -#define CRYPTO_IRQSTAT_RESULT_AVAIL_BITN 0 -#define CRYPTO_IRQSTAT_RESULT_AVAIL_M 0x00000001 -#define CRYPTO_IRQSTAT_RESULT_AVAIL_S 0 +#define CRYPTO_IRQSTAT_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_S 0 //***************************************************************************** // @@ -3927,40 +3927,39 @@ // Field: [27:24] HW_MAJOR_VER // // Major version number -#define CRYPTO_HWVER_HW_MAJOR_VER_W 4 -#define CRYPTO_HWVER_HW_MAJOR_VER_M 0x0F000000 -#define CRYPTO_HWVER_HW_MAJOR_VER_S 24 +#define CRYPTO_HWVER_HW_MAJOR_VER_W 4 +#define CRYPTO_HWVER_HW_MAJOR_VER_M 0x0F000000 +#define CRYPTO_HWVER_HW_MAJOR_VER_S 24 // Field: [23:20] HW_MINOR_VER // // Minor version number -#define CRYPTO_HWVER_HW_MINOR_VER_W 4 -#define CRYPTO_HWVER_HW_MINOR_VER_M 0x00F00000 -#define CRYPTO_HWVER_HW_MINOR_VER_S 20 +#define CRYPTO_HWVER_HW_MINOR_VER_W 4 +#define CRYPTO_HWVER_HW_MINOR_VER_M 0x00F00000 +#define CRYPTO_HWVER_HW_MINOR_VER_S 20 // Field: [19:16] HW_PATCH_LVL // // Patch level // Starts at 0 at first delivery of this version -#define CRYPTO_HWVER_HW_PATCH_LVL_W 4 -#define CRYPTO_HWVER_HW_PATCH_LVL_M 0x000F0000 -#define CRYPTO_HWVER_HW_PATCH_LVL_S 16 +#define CRYPTO_HWVER_HW_PATCH_LVL_W 4 +#define CRYPTO_HWVER_HW_PATCH_LVL_M 0x000F0000 +#define CRYPTO_HWVER_HW_PATCH_LVL_S 16 // Field: [15:8] VER_NUM_COMPL // // These bits simply contain the complement of bits [7:0] (0x87), used by a // driver to ascertain that the EIP-120t register is indeed read. -#define CRYPTO_HWVER_VER_NUM_COMPL_W 8 -#define CRYPTO_HWVER_VER_NUM_COMPL_M 0x0000FF00 -#define CRYPTO_HWVER_VER_NUM_COMPL_S 8 +#define CRYPTO_HWVER_VER_NUM_COMPL_W 8 +#define CRYPTO_HWVER_VER_NUM_COMPL_M 0x0000FF00 +#define CRYPTO_HWVER_VER_NUM_COMPL_S 8 // Field: [7:0] VER_NUM // // These bits encode the EIP number for the EIP-120t, this field contains the // value 120 (decimal) or 0x78. -#define CRYPTO_HWVER_VER_NUM_W 8 -#define CRYPTO_HWVER_VER_NUM_M 0x000000FF -#define CRYPTO_HWVER_VER_NUM_S 0 - +#define CRYPTO_HWVER_VER_NUM_W 8 +#define CRYPTO_HWVER_VER_NUM_M 0x000000FF +#define CRYPTO_HWVER_VER_NUM_S 0 #endif // __CRYPTO__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi.h index 03edea6..bafb755 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_ddi.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_ddi.h + * Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) + * Revision: 49096 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_DDI_H__ #define __HW_DDI_H__ @@ -176,22 +176,20 @@ // The following are defines for the DDI master instruction offsets. // //***************************************************************************** -#define DDI_O_DIR 0x00000000 // Offset for the direct access instruction -#define DDI_O_SET 0x00000080 // Offset for 'Set' instruction. -#define DDI_O_CLR 0x00000100 // Offset for 'Clear' instruction. -#define DDI_O_MASK4B 0x00000200 // Offset for 4-bit masked access. +#define DDI_O_DIR 0x00000000 // Offset for the direct access instruction +#define DDI_O_SET 0x00000080 // Offset for 'Set' instruction. +#define DDI_O_CLR 0x00000100 // Offset for 'Clear' instruction. +#define DDI_O_MASK4B 0x00000200 // Offset for 4-bit masked access. // Data bit[n] is written if mask bit[n] is set ('1'). // Bits 7:4 are mask. Bits 3:0 are data. // Requires 'byte' write. -#define DDI_O_MASK8B 0x00000300 // Offset for 8-bit masked access. +#define DDI_O_MASK8B 0x00000300 // Offset for 8-bit masked access. // Data bit[n] is written if mask bit[n] is set ('1'). // Bits 15:8 are mask. Bits 7:0 are data. // Requires 'short' write. -#define DDI_O_MASK16B 0x00000400 // Offset for 16-bit masked access. +#define DDI_O_MASK16B 0x00000400 // Offset for 16-bit masked access. // Data bit[n] is written if mask bit[n] is set ('1'). // Bits 31:16 are mask. Bits 15:0 are data. // Requires 'long' write. - - #endif // __HW_DDI_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi_0_osc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi_0_osc.h index d74a01d..814c985 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi_0_osc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi_0_osc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_ddi_0_osc_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_ddi_0_osc_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_DDI_0_OSC_H__ #define __HW_DDI_0_OSC_H__ @@ -44,55 +44,55 @@ // //***************************************************************************** // Control 0 -#define DDI_0_OSC_O_CTL0 0x00000000 +#define DDI_0_OSC_O_CTL0 0x00000000 // Control 1 -#define DDI_0_OSC_O_CTL1 0x00000004 +#define DDI_0_OSC_O_CTL1 0x00000004 // RADC External Configuration -#define DDI_0_OSC_O_RADCEXTCFG 0x00000008 +#define DDI_0_OSC_O_RADCEXTCFG 0x00000008 // Amplitude Compensation Control -#define DDI_0_OSC_O_AMPCOMPCTL 0x0000000C +#define DDI_0_OSC_O_AMPCOMPCTL 0x0000000C // Amplitude Compensation Threshold 1 -#define DDI_0_OSC_O_AMPCOMPTH1 0x00000010 +#define DDI_0_OSC_O_AMPCOMPTH1 0x00000010 // Amplitude Compensation Threshold 2 -#define DDI_0_OSC_O_AMPCOMPTH2 0x00000014 +#define DDI_0_OSC_O_AMPCOMPTH2 0x00000014 // Analog Bypass Values 1 -#define DDI_0_OSC_O_ANABYPASSVAL1 0x00000018 +#define DDI_0_OSC_O_ANABYPASSVAL1 0x00000018 // Internal -#define DDI_0_OSC_O_ANABYPASSVAL2 0x0000001C +#define DDI_0_OSC_O_ANABYPASSVAL2 0x0000001C // Analog Test Control -#define DDI_0_OSC_O_ATESTCTL 0x00000020 +#define DDI_0_OSC_O_ATESTCTL 0x00000020 // ADC Doubler Nanoamp Control -#define DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL 0x00000024 +#define DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL 0x00000024 // XOSCHF Control -#define DDI_0_OSC_O_XOSCHFCTL 0x00000028 +#define DDI_0_OSC_O_XOSCHFCTL 0x00000028 // Low Frequency Oscillator Control -#define DDI_0_OSC_O_LFOSCCTL 0x0000002C +#define DDI_0_OSC_O_LFOSCCTL 0x0000002C // RCOSCHF Control -#define DDI_0_OSC_O_RCOSCHFCTL 0x00000030 +#define DDI_0_OSC_O_RCOSCHFCTL 0x00000030 // RCOSC_MF Control -#define DDI_0_OSC_O_RCOSCMFCTL 0x00000034 +#define DDI_0_OSC_O_RCOSCMFCTL 0x00000034 // Status 0 -#define DDI_0_OSC_O_STAT0 0x0000003C +#define DDI_0_OSC_O_STAT0 0x0000003C // Status 1 -#define DDI_0_OSC_O_STAT1 0x00000040 +#define DDI_0_OSC_O_STAT1 0x00000040 // Status 2 -#define DDI_0_OSC_O_STAT2 0x00000044 +#define DDI_0_OSC_O_STAT2 0x00000044 //***************************************************************************** // @@ -105,39 +105,39 @@ // ENUMs: // 24M Internal. Only to be used through TI provided API. // 48M Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000 -#define DDI_0_OSC_CTL0_XTAL_IS_24M_M 0x80000000 -#define DDI_0_OSC_CTL0_XTAL_IS_24M_S 31 -#define DDI_0_OSC_CTL0_XTAL_IS_24M_24M 0x80000000 -#define DDI_0_OSC_CTL0_XTAL_IS_24M_48M 0x00000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_S 31 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_24M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_48M 0x00000000 // Field: [29] BYPASS_XOSC_LF_CLK_QUAL // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000 -#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M 0x20000000 -#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_S 29 +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000 +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M 0x20000000 +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_S 29 // Field: [28] BYPASS_RCOSC_LF_CLK_QUAL // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000 -#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M 0x10000000 -#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S 28 +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000 +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M 0x10000000 +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S 28 // Field: [27:26] DOUBLER_START_DURATION // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_W 2 -#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_M 0x0C000000 -#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_S 26 +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_W 2 +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_M 0x0C000000 +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_S 26 // Field: [25] DOUBLER_RESET_DURATION // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x02000000 -#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_M 0x02000000 -#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_S 25 +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x02000000 +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_M 0x02000000 +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_S 25 // Field: [24] CLK_DCDC_SRC_SEL // @@ -145,30 +145,30 @@ // // 0: CLK_DCDC is 48 MHz clock from RCOSC or XOSC / HPOSC // 1: CLK_DCDC is always 48 MHz clock from RCOSC -#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL 0x01000000 -#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M 0x01000000 -#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_S 24 +#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL 0x01000000 +#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M 0x01000000 +#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_S 24 // Field: [14] HPOSC_MODE_EN // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_HPOSC_MODE_EN 0x00004000 -#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_M 0x00004000 -#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_S 14 +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN 0x00004000 +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_M 0x00004000 +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_S 14 // Field: [12] RCOSC_LF_TRIMMED // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x00001000 -#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_M 0x00001000 -#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_S 12 +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x00001000 +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_M 0x00001000 +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_S 12 // Field: [11] XOSC_HF_POWER_MODE // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x00000800 -#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_M 0x00000800 -#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_S 11 +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x00000800 +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_M 0x00000800 +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_S 11 // Field: [10] XOSC_LF_DIG_BYPASS // @@ -191,9 +191,9 @@ // It is recommended that either the rcosc_hf or xosc_hf (whichever is // currently active) be selected as the source in step 1 above. This provides a // faster clock change. -#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x00000400 -#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_M 0x00000400 -#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_S 10 +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x00000400 +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_M 0x00000400 +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_S 10 // Field: [9] CLK_LOSS_EN // @@ -206,9 +206,9 @@ // Clock loss detection must be disabled when changing the sclk_lf source. // STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf // source has completed. -#define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x00000200 -#define DDI_0_OSC_CTL0_CLK_LOSS_EN_M 0x00000200 -#define DDI_0_OSC_CTL0_CLK_LOSS_EN_S 9 +#define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x00000200 +#define DDI_0_OSC_CTL0_CLK_LOSS_EN_M 0x00000200 +#define DDI_0_OSC_CTL0_CLK_LOSS_EN_S 9 // Field: [8:7] ACLK_TDC_SRC_SEL // @@ -218,9 +218,9 @@ // 01: RCOSC_HF (24MHz) // 10: XOSC_HF (24MHz) // 11: Not used -#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_W 2 -#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M 0x00000180 -#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S 7 +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_W 2 +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M 0x00000180 +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S 7 // Field: [6:4] ACLK_REF_SRC_SEL // @@ -232,9 +232,9 @@ // 011: XOSC_LF (32.768kHz) // 100: RCOSC_MF (2MHz) // 101-111: Not used -#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_W 3 -#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M 0x00000070 -#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S 4 +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_W 3 +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M 0x00000070 +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S 4 // Field: [3:2] SCLK_LF_SRC_SEL // @@ -246,13 +246,13 @@ // XOSC // RCOSCHFDLF Low frequency clock derived from High Frequency // RCOSC -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_W 2 -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M 0x0000000C -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S 2 -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCLF 0x0000000C -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCLF 0x00000008 -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF 0x00000004 -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCHFDLF 0x00000000 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_W 2 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M 0x0000000C +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S 2 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCLF 0x0000000C +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCLF 0x00000008 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF 0x00000004 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCHFDLF 0x00000000 // Field: [0] SCLK_HF_SRC_SEL // @@ -260,11 +260,11 @@ // ENUMs: // XOSC High frequency XOSC clock // RCOSC High frequency RCOSC clock -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL 0x00000001 -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M 0x00000001 -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S 0 -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC 0x00000001 -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC 0x00000000 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S 0 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC 0x00000000 //***************************************************************************** // @@ -274,23 +274,23 @@ // Field: [22:18] RCOSCHFCTRIMFRACT // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_W 5 -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_M 0x007C0000 -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_S 18 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_W 5 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_M 0x007C0000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_S 18 // Field: [17] RCOSCHFCTRIMFRACT_EN // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN 0x00020000 -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_M 0x00020000 -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_S 17 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN 0x00020000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_M 0x00020000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_S 17 // Field: [1:0] XOSC_HF_FAST_START // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_W 2 -#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_M 0x00000003 -#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_S 0 +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_W 2 +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_M 0x00000003 +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_S 0 //***************************************************************************** // @@ -300,37 +300,37 @@ // Field: [31:22] HPM_IBIAS_WAIT_CNT // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_W 10 -#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_M 0xFFC00000 -#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S 22 +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_W 10 +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_M 0xFFC00000 +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S 22 // Field: [21:16] LPM_IBIAS_WAIT_CNT // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_W 6 -#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_M 0x003F0000 -#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S 16 +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_W 6 +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_M 0x003F0000 +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S 16 // Field: [15:12] IDAC_STEP // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_W 4 -#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_M 0x0000F000 -#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S 12 +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_W 4 +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_M 0x0000F000 +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S 12 // Field: [11:6] RADC_DAC_TH // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_W 6 -#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_M 0x00000FC0 -#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_S 6 +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_W 6 +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_M 0x00000FC0 +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_S 6 // Field: [5] RADC_MODE_IS_SAR // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR 0x00000020 -#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_M 0x00000020 -#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_S 5 +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR 0x00000020 +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_M 0x00000020 +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_S 5 //***************************************************************************** // @@ -340,9 +340,9 @@ // Field: [30] AMPCOMP_REQ_MODE // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE 0x40000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_M 0x40000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S 30 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE 0x40000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_M 0x40000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S 30 // Field: [29:28] AMPCOMP_FSM_UPDATE_RATE // @@ -352,62 +352,62 @@ // 500KHZ Internal. Only to be used through TI provided API. // 1MHZ Internal. Only to be used through TI provided API. // 2MHZ Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_W 2 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_M 0x30000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_S 28 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_250KHZ 0x30000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_500KHZ 0x20000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_1MHZ 0x10000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_2MHZ 0x00000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_W 2 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_M 0x30000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_S 28 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_250KHZ 0x30000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_500KHZ 0x20000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_1MHZ 0x10000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_2MHZ 0x00000000 // Field: [27] AMPCOMP_SW_CTRL // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL 0x08000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_M 0x08000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_S 27 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL 0x08000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_M 0x08000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_S 27 // Field: [26] AMPCOMP_SW_EN // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN 0x04000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_M 0x04000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_S 26 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN 0x04000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_M 0x04000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_S 26 // Field: [23:20] IBIAS_OFFSET // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_W 4 -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M 0x00F00000 -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S 20 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M 0x00F00000 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S 20 // Field: [19:16] IBIAS_INIT // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_W 4 -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M 0x000F0000 -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S 16 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M 0x000F0000 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S 16 // Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_W 8 -#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 -#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S 8 +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_W 8 +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S 8 // Field: [7:4] CAP_STEP // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_W 4 -#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_M 0x000000F0 -#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S 4 +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_W 4 +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_M 0x000000F0 +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S 4 // Field: [3:0] IBIASCAP_HPTOLP_OL_CNT // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_W 4 -#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F -#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S 0 +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S 0 //***************************************************************************** // @@ -417,30 +417,30 @@ // Field: [23:18] HPMRAMP3_LTH // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_W 6 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M 0x00FC0000 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S 18 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M 0x00FC0000 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S 18 // Field: [15:10] HPMRAMP3_HTH // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_W 6 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M 0x0000FC00 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S 10 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M 0x0000FC00 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S 10 // Field: [9:6] IBIASCAP_LPTOHP_OL_CNT // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_W 4 -#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 -#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S 6 +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_W 4 +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S 6 // Field: [5:0] HPMRAMP1_TH // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_W 6 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_M 0x0000003F -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S 0 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_M 0x0000003F +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S 0 //***************************************************************************** // @@ -450,30 +450,30 @@ // Field: [31:26] LPMUPDATE_LTH // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_W 6 -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_M 0xFC000000 -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S 26 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_W 6 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_M 0xFC000000 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S 26 // Field: [23:18] LPMUPDATE_HTH // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_W 6 -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_M 0x00FC0000 -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S 18 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_W 6 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_M 0x00FC0000 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S 18 // Field: [15:10] ADC_COMP_AMPTH_LPM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_W 6 -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S 10 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_W 6 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S 10 // Field: [7:2] ADC_COMP_AMPTH_HPM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_W 6 -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_M 0x000000FC -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S 2 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_W 6 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_M 0x000000FC +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S 2 //***************************************************************************** // @@ -483,16 +483,16 @@ // Field: [19:16] XOSC_HF_ROW_Q12 // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_W 4 -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_M 0x000F0000 -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S 16 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_W 4 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_M 0x000F0000 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S 16 // Field: [15:0] XOSC_HF_COLUMN_Q12 // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_W 16 -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_M 0x0000FFFF -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S 0 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_W 16 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_M 0x0000FFFF +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S 0 //***************************************************************************** // @@ -502,9 +502,9 @@ // Field: [13:0] XOSC_HF_IBIASTHERM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_W 14 -#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_M 0x00003FFF -#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S 0 +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_W 14 +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_M 0x00003FFF +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S 0 //***************************************************************************** // @@ -514,9 +514,9 @@ // Field: [31] SCLK_LF_AUX_EN // // Enable 32 kHz clock to AUX_COMPB. -#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN 0x80000000 -#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_M 0x80000000 -#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_S 31 +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN 0x80000000 +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_M 0x80000000 +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_S 31 // Field: [15:14] TEST_RCOSCMF // @@ -527,9 +527,9 @@ // 0x2: clock qualification disabled // 0x3: boosted bias current into self biased inverter + clock qualification // disabled -#define DDI_0_OSC_ATESTCTL_TEST_RCOSCMF_W 2 -#define DDI_0_OSC_ATESTCTL_TEST_RCOSCMF_M 0x0000C000 -#define DDI_0_OSC_ATESTCTL_TEST_RCOSCMF_S 14 +#define DDI_0_OSC_ATESTCTL_TEST_RCOSCMF_W 2 +#define DDI_0_OSC_ATESTCTL_TEST_RCOSCMF_M 0x0000C000 +#define DDI_0_OSC_ATESTCTL_TEST_RCOSCMF_S 14 // Field: [13:12] ATEST_RCOSCMF // @@ -541,9 +541,9 @@ // 0x2: ATEST disabled // 0x3: ATEST enabled, bias current connected, ATEST internal to **RCOSC_MF* // enabled to send out 2MHz clock. -#define DDI_0_OSC_ATESTCTL_ATEST_RCOSCMF_W 2 -#define DDI_0_OSC_ATESTCTL_ATEST_RCOSCMF_M 0x00003000 -#define DDI_0_OSC_ATESTCTL_ATEST_RCOSCMF_S 12 +#define DDI_0_OSC_ATESTCTL_ATEST_RCOSCMF_W 2 +#define DDI_0_OSC_ATESTCTL_ATEST_RCOSCMF_M 0x00003000 +#define DDI_0_OSC_ATESTCTL_ATEST_RCOSCMF_S 12 //***************************************************************************** // @@ -553,38 +553,38 @@ // Field: [24] NANOAMP_BIAS_ENABLE // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE 0x01000000 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_M 0x01000000 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_S 24 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE 0x01000000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_M 0x01000000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_S 24 // Field: [23] SPARE23 // // Software should not rely on the value of a reserved. Writing any other value // than the reset value may result in undefined behavior -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23 0x00800000 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_M 0x00800000 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_S 23 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23 0x00800000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_M 0x00800000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_S 23 // Field: [5] ADC_SH_MODE_EN // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN 0x00000020 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_M 0x00000020 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_S 5 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN 0x00000020 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_M 0x00000020 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_S 5 // Field: [4] ADC_SH_VBUF_EN // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN 0x00000010 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_M 0x00000010 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_S 4 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN 0x00000010 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_M 0x00000010 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_S 4 // Field: [1:0] ADC_IREF_CTRL // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_W 2 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_M 0x00000003 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_S 0 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_W 2 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_M 0x00000003 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_S 0 //***************************************************************************** // @@ -596,46 +596,46 @@ // If this register is 1 when TCXO_MODE is 1, then the XOSC_HF is enabled, // turning on the XOSC_HF bias current allowing a DC bias point to be provided // to the clipped-sine wave clock signal on external input. -#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN 0x00002000 -#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN_M 0x00002000 -#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN_S 13 +#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN 0x00002000 +#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN_M 0x00002000 +#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN_S 13 // Field: [12] TCXO_MODE // // If this register is 1 when BYPASS is 1, this will enable clock // qualification on the TCXO clock on external input. This register has no // effect when BYPASS is 0. -#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE 0x00001000 -#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_M 0x00001000 -#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_S 12 +#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE 0x00001000 +#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_M 0x00001000 +#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_S 12 // Field: [9:8] PEAK_DET_ITRIM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_W 2 -#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_M 0x00000300 -#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S 8 +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_W 2 +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_M 0x00000300 +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S 8 // Field: [6] BYPASS // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_XOSCHFCTL_BYPASS 0x00000040 -#define DDI_0_OSC_XOSCHFCTL_BYPASS_M 0x00000040 -#define DDI_0_OSC_XOSCHFCTL_BYPASS_S 6 +#define DDI_0_OSC_XOSCHFCTL_BYPASS 0x00000040 +#define DDI_0_OSC_XOSCHFCTL_BYPASS_M 0x00000040 +#define DDI_0_OSC_XOSCHFCTL_BYPASS_S 6 // Field: [4:2] HP_BUF_ITRIM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_W 3 -#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_M 0x0000001C -#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S 2 +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_W 3 +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_M 0x0000001C +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S 2 // Field: [1:0] LP_BUF_ITRIM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_W 2 -#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_M 0x00000003 -#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S 0 +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_W 2 +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_M 0x00000003 +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S 0 //***************************************************************************** // @@ -645,16 +645,16 @@ // Field: [23:22] XOSCLF_REGULATOR_TRIM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_W 2 -#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_M 0x00C00000 -#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_S 22 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_W 2 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_M 0x00C00000 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_S 22 // Field: [21:18] XOSCLF_CMIRRWR_RATIO // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_W 4 -#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_M 0x003C0000 -#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_S 18 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_W 4 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_M 0x003C0000 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_S 18 // Field: [9:8] RCOSCLF_RTUNE_TRIM // @@ -664,20 +664,20 @@ // 6P5MEG Internal. Only to be used through TI provided API. // 7P0MEG Internal. Only to be used through TI provided API. // 7P5MEG Internal. Only to be used through TI provided API. -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_W 2 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M 0x00000300 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S 8 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P0MEG 0x00000300 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P5MEG 0x00000200 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P0MEG 0x00000100 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P5MEG 0x00000000 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_W 2 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M 0x00000300 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S 8 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P0MEG 0x00000300 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P5MEG 0x00000200 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P0MEG 0x00000100 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P5MEG 0x00000000 // Field: [7:0] RCOSCLF_CTUNE_TRIM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_W 8 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M 0x000000FF -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S 0 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_W 8 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M 0x000000FF +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S 0 //***************************************************************************** // @@ -687,9 +687,9 @@ // Field: [15:8] RCOSCHF_CTRIM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_W 8 -#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M 0x0000FF00 -#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S 8 +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_W 8 +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M 0x0000FF00 +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S 8 //***************************************************************************** // @@ -703,9 +703,9 @@ // 0x0: nominal frequency, 0.625pF // 0x40: highest frequency, 0.125pF // 0x3F: lowest frequency, 1.125pF -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_W 7 -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_M 0x0000FE00 -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_S 9 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_W 7 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_M 0x0000FE00 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_S 9 // Field: [8] RCOSC_MF_REG_SEL // @@ -713,9 +713,9 @@ // // 0: default // 1: alternate -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL 0x00000100 -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL_M 0x00000100 -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL_S 8 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL 0x00000100 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL_M 0x00000100 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL_S 8 // Field: [7:6] RCOSC_MF_RES_COARSE // @@ -725,9 +725,9 @@ // 0x1: 300kohms, min // 0x2: 600kohms, max // 0x3: 500kohms -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_W 2 -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_M 0x000000C0 -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_S 6 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_W 2 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_M 0x000000C0 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_S 6 // Field: [5:4] RCOSC_MF_RES_FINE // @@ -737,9 +737,9 @@ // 0x1: 13kohms // 0x2: 16kohms // 0x3: 20kohms, max resistance, min freq -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_W 2 -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_M 0x00000030 -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_S 4 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_W 2 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_M 0x00000030 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_S 4 // Field: [3:0] RCOSC_MF_BIAS_ADJ // @@ -748,9 +748,9 @@ // 0x8 minimum current // 0x0 default current // 0x7 maximum current -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_W 4 -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_M 0x0000000F -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_S 0 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_W 4 +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_M 0x0000000F +#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_S 0 //***************************************************************************** // @@ -767,13 +767,13 @@ // XOSC // RCOSCHFDLF Low frequency clock derived from High Frequency // RCOSC -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_W 2 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_M 0x60000000 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_S 29 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCLF 0x60000000 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCLF 0x40000000 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCHFDLF 0x20000000 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCHFDLF 0x00000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_W 2 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_M 0x60000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_S 29 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCLF 0x60000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCLF 0x40000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCHFDLF 0x20000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCHFDLF 0x00000000 // Field: [28] SCLK_HF_SRC // @@ -781,67 +781,67 @@ // ENUMs: // XOSC High frequency XOSC // RCOSC High frequency RCOSC clock -#define DDI_0_OSC_STAT0_SCLK_HF_SRC 0x10000000 -#define DDI_0_OSC_STAT0_SCLK_HF_SRC_M 0x10000000 -#define DDI_0_OSC_STAT0_SCLK_HF_SRC_S 28 -#define DDI_0_OSC_STAT0_SCLK_HF_SRC_XOSC 0x10000000 -#define DDI_0_OSC_STAT0_SCLK_HF_SRC_RCOSC 0x00000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_M 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_S 28 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_XOSC 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_RCOSC 0x00000000 // Field: [22] RCOSC_HF_EN // // RCOSC_HF_EN -#define DDI_0_OSC_STAT0_RCOSC_HF_EN 0x00400000 -#define DDI_0_OSC_STAT0_RCOSC_HF_EN_M 0x00400000 -#define DDI_0_OSC_STAT0_RCOSC_HF_EN_S 22 +#define DDI_0_OSC_STAT0_RCOSC_HF_EN 0x00400000 +#define DDI_0_OSC_STAT0_RCOSC_HF_EN_M 0x00400000 +#define DDI_0_OSC_STAT0_RCOSC_HF_EN_S 22 // Field: [21] RCOSC_LF_EN // // RCOSC_LF_EN -#define DDI_0_OSC_STAT0_RCOSC_LF_EN 0x00200000 -#define DDI_0_OSC_STAT0_RCOSC_LF_EN_M 0x00200000 -#define DDI_0_OSC_STAT0_RCOSC_LF_EN_S 21 +#define DDI_0_OSC_STAT0_RCOSC_LF_EN 0x00200000 +#define DDI_0_OSC_STAT0_RCOSC_LF_EN_M 0x00200000 +#define DDI_0_OSC_STAT0_RCOSC_LF_EN_S 21 // Field: [20] XOSC_LF_EN // // XOSC_LF_EN -#define DDI_0_OSC_STAT0_XOSC_LF_EN 0x00100000 -#define DDI_0_OSC_STAT0_XOSC_LF_EN_M 0x00100000 -#define DDI_0_OSC_STAT0_XOSC_LF_EN_S 20 +#define DDI_0_OSC_STAT0_XOSC_LF_EN 0x00100000 +#define DDI_0_OSC_STAT0_XOSC_LF_EN_M 0x00100000 +#define DDI_0_OSC_STAT0_XOSC_LF_EN_S 20 // Field: [19] CLK_DCDC_RDY // // CLK_DCDC_RDY -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY 0x00080000 -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_M 0x00080000 -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_S 19 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY 0x00080000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_M 0x00080000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_S 19 // Field: [18] CLK_DCDC_RDY_ACK // // CLK_DCDC_RDY_ACK -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK 0x00040000 -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_M 0x00040000 -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_S 18 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK 0x00040000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_M 0x00040000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_S 18 // Field: [17] SCLK_HF_LOSS // // Indicates sclk_hf is lost -#define DDI_0_OSC_STAT0_SCLK_HF_LOSS 0x00020000 -#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_M 0x00020000 -#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_S 17 +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS 0x00020000 +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_M 0x00020000 +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_S 17 // Field: [16] SCLK_LF_LOSS // // Indicates sclk_lf is lost -#define DDI_0_OSC_STAT0_SCLK_LF_LOSS 0x00010000 -#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_M 0x00010000 -#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_S 16 +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS 0x00010000 +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_M 0x00010000 +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_S 16 // Field: [15] XOSC_HF_EN // // Indicates that XOSC_HF is enabled. -#define DDI_0_OSC_STAT0_XOSC_HF_EN 0x00008000 -#define DDI_0_OSC_STAT0_XOSC_HF_EN_M 0x00008000 -#define DDI_0_OSC_STAT0_XOSC_HF_EN_S 15 +#define DDI_0_OSC_STAT0_XOSC_HF_EN 0x00008000 +#define DDI_0_OSC_STAT0_XOSC_HF_EN_M 0x00008000 +#define DDI_0_OSC_STAT0_XOSC_HF_EN_S 15 // Field: [13] XB_48M_CLK_EN // @@ -849,51 +849,51 @@ // // It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler // bypass for the 48MHz crystal). -#define DDI_0_OSC_STAT0_XB_48M_CLK_EN 0x00002000 -#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_M 0x00002000 -#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_S 13 +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN 0x00002000 +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_M 0x00002000 +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_S 13 // Field: [11] XOSC_HF_LP_BUF_EN // // XOSC_HF_LP_BUF_EN -#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN 0x00000800 -#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_M 0x00000800 -#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_S 11 +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN 0x00000800 +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_M 0x00000800 +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_S 11 // Field: [10] XOSC_HF_HP_BUF_EN // // XOSC_HF_HP_BUF_EN -#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN 0x00000400 -#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_M 0x00000400 -#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_S 10 +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN 0x00000400 +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_M 0x00000400 +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_S 10 // Field: [8] ADC_THMET // // ADC_THMET -#define DDI_0_OSC_STAT0_ADC_THMET 0x00000100 -#define DDI_0_OSC_STAT0_ADC_THMET_M 0x00000100 -#define DDI_0_OSC_STAT0_ADC_THMET_S 8 +#define DDI_0_OSC_STAT0_ADC_THMET 0x00000100 +#define DDI_0_OSC_STAT0_ADC_THMET_M 0x00000100 +#define DDI_0_OSC_STAT0_ADC_THMET_S 8 // Field: [7] ADC_DATA_READY // // indicates when adc_data is ready. -#define DDI_0_OSC_STAT0_ADC_DATA_READY 0x00000080 -#define DDI_0_OSC_STAT0_ADC_DATA_READY_M 0x00000080 -#define DDI_0_OSC_STAT0_ADC_DATA_READY_S 7 +#define DDI_0_OSC_STAT0_ADC_DATA_READY 0x00000080 +#define DDI_0_OSC_STAT0_ADC_DATA_READY_M 0x00000080 +#define DDI_0_OSC_STAT0_ADC_DATA_READY_S 7 // Field: [6:1] ADC_DATA // // adc_data -#define DDI_0_OSC_STAT0_ADC_DATA_W 6 -#define DDI_0_OSC_STAT0_ADC_DATA_M 0x0000007E -#define DDI_0_OSC_STAT0_ADC_DATA_S 1 +#define DDI_0_OSC_STAT0_ADC_DATA_W 6 +#define DDI_0_OSC_STAT0_ADC_DATA_M 0x0000007E +#define DDI_0_OSC_STAT0_ADC_DATA_S 1 // Field: [0] PENDINGSCLKHFSWITCHING // // Indicates when SCLK_HF clock source is ready to be switched -#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING 0x00000001 -#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M 0x00000001 -#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S 0 +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING 0x00000001 +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M 0x00000001 +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S 0 //***************************************************************************** // @@ -919,24 +919,24 @@ // HPM_RAMP1 HPM_RAMP1 // INITIALIZATION INITIALIZATION // RESET RESET -#define DDI_0_OSC_STAT1_RAMPSTATE_W 4 -#define DDI_0_OSC_STAT1_RAMPSTATE_M 0xF0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_S 28 -#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START_SETTLE 0xE0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START 0xD0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_DUMMY_TO_INIT_1 0xC0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_DEC_W_MEASURE 0xB0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_INC 0xA0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_LPM_UPDATE 0x90000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_DEC_W_MEASURE 0x80000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_CAP_UPDATE 0x70000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_INCREMENT 0x60000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_UPDATE 0x50000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP3 0x40000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP2 0x30000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP1 0x20000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_INITIALIZATION 0x10000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_RESET 0x00000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_W 4 +#define DDI_0_OSC_STAT1_RAMPSTATE_M 0xF0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_S 28 +#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START_SETTLE 0xE0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START 0xD0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_DUMMY_TO_INIT_1 0xC0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_DEC_W_MEASURE 0xB0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_INC 0xA0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_LPM_UPDATE 0x90000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_DEC_W_MEASURE 0x80000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_CAP_UPDATE 0x70000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_INCREMENT 0x60000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_UPDATE 0x50000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP3 0x40000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP2 0x30000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP1 0x20000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_INITIALIZATION 0x10000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_RESET 0x00000000 // Field: [27:22] HPM_UPDATE_AMP // @@ -947,9 +947,9 @@ // would indicate that the amplitude of the crystal is approximately 480 mV. // To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero // value. -#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_W 6 -#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M 0x0FC00000 -#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S 22 +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_W 6 +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M 0x0FC00000 +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S 22 // Field: [21:16] LPM_UPDATE_AMP // @@ -960,121 +960,121 @@ // indicate that the amplitude of the crystal is approximately 480 mV. To // enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero // value. -#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_W 6 -#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_M 0x003F0000 -#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_S 16 +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_W 6 +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_M 0x003F0000 +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_S 16 // Field: [15] FORCE_RCOSC_HF // // force_rcosc_hf -#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF 0x00008000 -#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_M 0x00008000 -#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_S 15 +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF 0x00008000 +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_M 0x00008000 +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_S 15 // Field: [14] SCLK_HF_EN // // SCLK_HF_EN -#define DDI_0_OSC_STAT1_SCLK_HF_EN 0x00004000 -#define DDI_0_OSC_STAT1_SCLK_HF_EN_M 0x00004000 -#define DDI_0_OSC_STAT1_SCLK_HF_EN_S 14 +#define DDI_0_OSC_STAT1_SCLK_HF_EN 0x00004000 +#define DDI_0_OSC_STAT1_SCLK_HF_EN_M 0x00004000 +#define DDI_0_OSC_STAT1_SCLK_HF_EN_S 14 // Field: [13] SCLK_MF_EN // // SCLK_MF_EN -#define DDI_0_OSC_STAT1_SCLK_MF_EN 0x00002000 -#define DDI_0_OSC_STAT1_SCLK_MF_EN_M 0x00002000 -#define DDI_0_OSC_STAT1_SCLK_MF_EN_S 13 +#define DDI_0_OSC_STAT1_SCLK_MF_EN 0x00002000 +#define DDI_0_OSC_STAT1_SCLK_MF_EN_M 0x00002000 +#define DDI_0_OSC_STAT1_SCLK_MF_EN_S 13 // Field: [12] ACLK_ADC_EN // // ACLK_ADC_EN -#define DDI_0_OSC_STAT1_ACLK_ADC_EN 0x00001000 -#define DDI_0_OSC_STAT1_ACLK_ADC_EN_M 0x00001000 -#define DDI_0_OSC_STAT1_ACLK_ADC_EN_S 12 +#define DDI_0_OSC_STAT1_ACLK_ADC_EN 0x00001000 +#define DDI_0_OSC_STAT1_ACLK_ADC_EN_M 0x00001000 +#define DDI_0_OSC_STAT1_ACLK_ADC_EN_S 12 // Field: [11] ACLK_TDC_EN // // ACLK_TDC_EN -#define DDI_0_OSC_STAT1_ACLK_TDC_EN 0x00000800 -#define DDI_0_OSC_STAT1_ACLK_TDC_EN_M 0x00000800 -#define DDI_0_OSC_STAT1_ACLK_TDC_EN_S 11 +#define DDI_0_OSC_STAT1_ACLK_TDC_EN 0x00000800 +#define DDI_0_OSC_STAT1_ACLK_TDC_EN_M 0x00000800 +#define DDI_0_OSC_STAT1_ACLK_TDC_EN_S 11 // Field: [10] ACLK_REF_EN // // ACLK_REF_EN -#define DDI_0_OSC_STAT1_ACLK_REF_EN 0x00000400 -#define DDI_0_OSC_STAT1_ACLK_REF_EN_M 0x00000400 -#define DDI_0_OSC_STAT1_ACLK_REF_EN_S 10 +#define DDI_0_OSC_STAT1_ACLK_REF_EN 0x00000400 +#define DDI_0_OSC_STAT1_ACLK_REF_EN_M 0x00000400 +#define DDI_0_OSC_STAT1_ACLK_REF_EN_S 10 // Field: [9] CLK_CHP_EN // // CLK_CHP_EN -#define DDI_0_OSC_STAT1_CLK_CHP_EN 0x00000200 -#define DDI_0_OSC_STAT1_CLK_CHP_EN_M 0x00000200 -#define DDI_0_OSC_STAT1_CLK_CHP_EN_S 9 +#define DDI_0_OSC_STAT1_CLK_CHP_EN 0x00000200 +#define DDI_0_OSC_STAT1_CLK_CHP_EN_M 0x00000200 +#define DDI_0_OSC_STAT1_CLK_CHP_EN_S 9 // Field: [8] CLK_DCDC_EN // // CLK_DCDC_EN -#define DDI_0_OSC_STAT1_CLK_DCDC_EN 0x00000100 -#define DDI_0_OSC_STAT1_CLK_DCDC_EN_M 0x00000100 -#define DDI_0_OSC_STAT1_CLK_DCDC_EN_S 8 +#define DDI_0_OSC_STAT1_CLK_DCDC_EN 0x00000100 +#define DDI_0_OSC_STAT1_CLK_DCDC_EN_M 0x00000100 +#define DDI_0_OSC_STAT1_CLK_DCDC_EN_S 8 // Field: [7] SCLK_HF_GOOD // // SCLK_HF_GOOD -#define DDI_0_OSC_STAT1_SCLK_HF_GOOD 0x00000080 -#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_M 0x00000080 -#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_S 7 +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD 0x00000080 +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_M 0x00000080 +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_S 7 // Field: [6] SCLK_MF_GOOD // // SCLK_MF_GOOD -#define DDI_0_OSC_STAT1_SCLK_MF_GOOD 0x00000040 -#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_M 0x00000040 -#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_S 6 +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD 0x00000040 +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_M 0x00000040 +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_S 6 // Field: [5] SCLK_LF_GOOD // // SCLK_LF_GOOD -#define DDI_0_OSC_STAT1_SCLK_LF_GOOD 0x00000020 -#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_M 0x00000020 -#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_S 5 +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD 0x00000020 +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_M 0x00000020 +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_S 5 // Field: [4] ACLK_ADC_GOOD // // ACLK_ADC_GOOD -#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD 0x00000010 -#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_M 0x00000010 -#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_S 4 +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD 0x00000010 +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_M 0x00000010 +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_S 4 // Field: [3] ACLK_TDC_GOOD // // ACLK_TDC_GOOD -#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD 0x00000008 -#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_M 0x00000008 -#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_S 3 +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD 0x00000008 +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_M 0x00000008 +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_S 3 // Field: [2] ACLK_REF_GOOD // // ACLK_REF_GOOD. -#define DDI_0_OSC_STAT1_ACLK_REF_GOOD 0x00000004 -#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_M 0x00000004 -#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_S 2 +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD 0x00000004 +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_M 0x00000004 +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_S 2 // Field: [1] CLK_CHP_GOOD // // CLK_CHP_GOOD -#define DDI_0_OSC_STAT1_CLK_CHP_GOOD 0x00000002 -#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_M 0x00000002 -#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_S 1 +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD 0x00000002 +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_M 0x00000002 +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_S 1 // Field: [0] CLK_DCDC_GOOD // // CLK_DCDC_GOOD -#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD 0x00000001 -#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_M 0x00000001 -#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_S 0 +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD 0x00000001 +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_M 0x00000001 +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_S 0 //***************************************************************************** // @@ -1085,69 +1085,68 @@ // // DC Bias read by RADC during SAR mode // The value is an unsigned integer. It is used for debug only. -#define DDI_0_OSC_STAT2_ADC_DCBIAS_W 6 -#define DDI_0_OSC_STAT2_ADC_DCBIAS_M 0xFC000000 -#define DDI_0_OSC_STAT2_ADC_DCBIAS_S 26 +#define DDI_0_OSC_STAT2_ADC_DCBIAS_W 6 +#define DDI_0_OSC_STAT2_ADC_DCBIAS_M 0xFC000000 +#define DDI_0_OSC_STAT2_ADC_DCBIAS_S 26 // Field: [25] HPM_RAMP1_THMET // // Indication of threshold is met for hpm_ramp1 -#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET 0x02000000 -#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_M 0x02000000 -#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_S 25 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET 0x02000000 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_M 0x02000000 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_S 25 // Field: [24] HPM_RAMP2_THMET // // Indication of threshold is met for hpm_ramp2 -#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET 0x01000000 -#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_M 0x01000000 -#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_S 24 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET 0x01000000 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_M 0x01000000 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_S 24 // Field: [23] HPM_RAMP3_THMET // // Indication of threshold is met for hpm_ramp3 -#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET 0x00800000 -#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_M 0x00800000 -#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_S 23 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET 0x00800000 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_M 0x00800000 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_S 23 // Field: [15:12] RAMPSTATE // // xosc_hf amplitude compensation FSM // // This is identical to STAT1.RAMPSTATE. See that description for encoding. -#define DDI_0_OSC_STAT2_RAMPSTATE_W 4 -#define DDI_0_OSC_STAT2_RAMPSTATE_M 0x0000F000 -#define DDI_0_OSC_STAT2_RAMPSTATE_S 12 +#define DDI_0_OSC_STAT2_RAMPSTATE_W 4 +#define DDI_0_OSC_STAT2_RAMPSTATE_M 0x0000F000 +#define DDI_0_OSC_STAT2_RAMPSTATE_S 12 // Field: [3] AMPCOMP_REQ // // ampcomp_req -#define DDI_0_OSC_STAT2_AMPCOMP_REQ 0x00000008 -#define DDI_0_OSC_STAT2_AMPCOMP_REQ_M 0x00000008 -#define DDI_0_OSC_STAT2_AMPCOMP_REQ_S 3 +#define DDI_0_OSC_STAT2_AMPCOMP_REQ 0x00000008 +#define DDI_0_OSC_STAT2_AMPCOMP_REQ_M 0x00000008 +#define DDI_0_OSC_STAT2_AMPCOMP_REQ_S 3 // Field: [2] XOSC_HF_AMPGOOD // // amplitude of xosc_hf is within the required threshold (set by DDI). Not used // for anything just for debug/status -#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD 0x00000004 -#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_M 0x00000004 -#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_S 2 +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD 0x00000004 +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_M 0x00000004 +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_S 2 // Field: [1] XOSC_HF_FREQGOOD // // frequency of xosc_hf is good to use for the digital clocks -#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD 0x00000002 -#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_M 0x00000002 -#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_S 1 +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD 0x00000002 +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_M 0x00000002 +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_S 1 // Field: [0] XOSC_HF_RF_FREQGOOD // // frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio // operations. Used for SW to start synthesizer. -#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD 0x00000001 -#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_M 0x00000001 -#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_S 0 - +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD 0x00000001 +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_M 0x00000001 +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_S 0 #endif // __DDI_0_OSC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_event.h index c365d74..eafdf8f 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_event.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_event.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_event_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_event_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_EVENT_H__ #define __HW_EVENT_H__ @@ -44,304 +44,304 @@ // //***************************************************************************** // Output Selection for CPU Interrupt 0 -#define EVENT_O_CPUIRQSEL0 0x00000000 +#define EVENT_O_CPUIRQSEL0 0x00000000 // Output Selection for CPU Interrupt 1 -#define EVENT_O_CPUIRQSEL1 0x00000004 +#define EVENT_O_CPUIRQSEL1 0x00000004 // Output Selection for CPU Interrupt 2 -#define EVENT_O_CPUIRQSEL2 0x00000008 +#define EVENT_O_CPUIRQSEL2 0x00000008 // Output Selection for CPU Interrupt 3 -#define EVENT_O_CPUIRQSEL3 0x0000000C +#define EVENT_O_CPUIRQSEL3 0x0000000C // Output Selection for CPU Interrupt 4 -#define EVENT_O_CPUIRQSEL4 0x00000010 +#define EVENT_O_CPUIRQSEL4 0x00000010 // Output Selection for CPU Interrupt 5 -#define EVENT_O_CPUIRQSEL5 0x00000014 +#define EVENT_O_CPUIRQSEL5 0x00000014 // Output Selection for CPU Interrupt 6 -#define EVENT_O_CPUIRQSEL6 0x00000018 +#define EVENT_O_CPUIRQSEL6 0x00000018 // Output Selection for CPU Interrupt 7 -#define EVENT_O_CPUIRQSEL7 0x0000001C +#define EVENT_O_CPUIRQSEL7 0x0000001C // Output Selection for CPU Interrupt 8 -#define EVENT_O_CPUIRQSEL8 0x00000020 +#define EVENT_O_CPUIRQSEL8 0x00000020 // Output Selection for CPU Interrupt 9 -#define EVENT_O_CPUIRQSEL9 0x00000024 +#define EVENT_O_CPUIRQSEL9 0x00000024 // Output Selection for CPU Interrupt 10 -#define EVENT_O_CPUIRQSEL10 0x00000028 +#define EVENT_O_CPUIRQSEL10 0x00000028 // Output Selection for CPU Interrupt 11 -#define EVENT_O_CPUIRQSEL11 0x0000002C +#define EVENT_O_CPUIRQSEL11 0x0000002C // Output Selection for CPU Interrupt 12 -#define EVENT_O_CPUIRQSEL12 0x00000030 +#define EVENT_O_CPUIRQSEL12 0x00000030 // Output Selection for CPU Interrupt 13 -#define EVENT_O_CPUIRQSEL13 0x00000034 +#define EVENT_O_CPUIRQSEL13 0x00000034 // Output Selection for CPU Interrupt 14 -#define EVENT_O_CPUIRQSEL14 0x00000038 +#define EVENT_O_CPUIRQSEL14 0x00000038 // Output Selection for CPU Interrupt 15 -#define EVENT_O_CPUIRQSEL15 0x0000003C +#define EVENT_O_CPUIRQSEL15 0x0000003C // Output Selection for CPU Interrupt 16 -#define EVENT_O_CPUIRQSEL16 0x00000040 +#define EVENT_O_CPUIRQSEL16 0x00000040 // Output Selection for CPU Interrupt 17 -#define EVENT_O_CPUIRQSEL17 0x00000044 +#define EVENT_O_CPUIRQSEL17 0x00000044 // Output Selection for CPU Interrupt 18 -#define EVENT_O_CPUIRQSEL18 0x00000048 +#define EVENT_O_CPUIRQSEL18 0x00000048 // Output Selection for CPU Interrupt 19 -#define EVENT_O_CPUIRQSEL19 0x0000004C +#define EVENT_O_CPUIRQSEL19 0x0000004C // Output Selection for CPU Interrupt 20 -#define EVENT_O_CPUIRQSEL20 0x00000050 +#define EVENT_O_CPUIRQSEL20 0x00000050 // Output Selection for CPU Interrupt 21 -#define EVENT_O_CPUIRQSEL21 0x00000054 +#define EVENT_O_CPUIRQSEL21 0x00000054 // Output Selection for CPU Interrupt 22 -#define EVENT_O_CPUIRQSEL22 0x00000058 +#define EVENT_O_CPUIRQSEL22 0x00000058 // Output Selection for CPU Interrupt 23 -#define EVENT_O_CPUIRQSEL23 0x0000005C +#define EVENT_O_CPUIRQSEL23 0x0000005C // Output Selection for CPU Interrupt 24 -#define EVENT_O_CPUIRQSEL24 0x00000060 +#define EVENT_O_CPUIRQSEL24 0x00000060 // Output Selection for CPU Interrupt 25 -#define EVENT_O_CPUIRQSEL25 0x00000064 +#define EVENT_O_CPUIRQSEL25 0x00000064 // Output Selection for CPU Interrupt 26 -#define EVENT_O_CPUIRQSEL26 0x00000068 +#define EVENT_O_CPUIRQSEL26 0x00000068 // Output Selection for CPU Interrupt 27 -#define EVENT_O_CPUIRQSEL27 0x0000006C +#define EVENT_O_CPUIRQSEL27 0x0000006C // Output Selection for CPU Interrupt 28 -#define EVENT_O_CPUIRQSEL28 0x00000070 +#define EVENT_O_CPUIRQSEL28 0x00000070 // Output Selection for CPU Interrupt 29 -#define EVENT_O_CPUIRQSEL29 0x00000074 +#define EVENT_O_CPUIRQSEL29 0x00000074 // Output Selection for CPU Interrupt 30 -#define EVENT_O_CPUIRQSEL30 0x00000078 +#define EVENT_O_CPUIRQSEL30 0x00000078 // Output Selection for CPU Interrupt 31 -#define EVENT_O_CPUIRQSEL31 0x0000007C +#define EVENT_O_CPUIRQSEL31 0x0000007C // Output Selection for CPU Interrupt 32 -#define EVENT_O_CPUIRQSEL32 0x00000080 +#define EVENT_O_CPUIRQSEL32 0x00000080 // Output Selection for CPU Interrupt 33 -#define EVENT_O_CPUIRQSEL33 0x00000084 +#define EVENT_O_CPUIRQSEL33 0x00000084 // Output Selection for CPU Interrupt 34 -#define EVENT_O_CPUIRQSEL34 0x00000088 +#define EVENT_O_CPUIRQSEL34 0x00000088 // Output Selection for CPU Interrupt 35 -#define EVENT_O_CPUIRQSEL35 0x0000008C +#define EVENT_O_CPUIRQSEL35 0x0000008C // Output Selection for CPU Interrupt 36 -#define EVENT_O_CPUIRQSEL36 0x00000090 +#define EVENT_O_CPUIRQSEL36 0x00000090 // Output Selection for CPU Interrupt 37 -#define EVENT_O_CPUIRQSEL37 0x00000094 +#define EVENT_O_CPUIRQSEL37 0x00000094 // Output Selection for RFC Event 0 -#define EVENT_O_RFCSEL0 0x00000100 +#define EVENT_O_RFCSEL0 0x00000100 // Output Selection for RFC Event 1 -#define EVENT_O_RFCSEL1 0x00000104 +#define EVENT_O_RFCSEL1 0x00000104 // Output Selection for RFC Event 2 -#define EVENT_O_RFCSEL2 0x00000108 +#define EVENT_O_RFCSEL2 0x00000108 // Output Selection for RFC Event 3 -#define EVENT_O_RFCSEL3 0x0000010C +#define EVENT_O_RFCSEL3 0x0000010C // Output Selection for RFC Event 4 -#define EVENT_O_RFCSEL4 0x00000110 +#define EVENT_O_RFCSEL4 0x00000110 // Output Selection for RFC Event 5 -#define EVENT_O_RFCSEL5 0x00000114 +#define EVENT_O_RFCSEL5 0x00000114 // Output Selection for RFC Event 6 -#define EVENT_O_RFCSEL6 0x00000118 +#define EVENT_O_RFCSEL6 0x00000118 // Output Selection for RFC Event 7 -#define EVENT_O_RFCSEL7 0x0000011C +#define EVENT_O_RFCSEL7 0x0000011C // Output Selection for RFC Event 8 -#define EVENT_O_RFCSEL8 0x00000120 +#define EVENT_O_RFCSEL8 0x00000120 // Output Selection for RFC Event 9 -#define EVENT_O_RFCSEL9 0x00000124 +#define EVENT_O_RFCSEL9 0x00000124 // Output Selection for GPT0 0 -#define EVENT_O_GPT0ACAPTSEL 0x00000200 +#define EVENT_O_GPT0ACAPTSEL 0x00000200 // Output Selection for GPT0 1 -#define EVENT_O_GPT0BCAPTSEL 0x00000204 +#define EVENT_O_GPT0BCAPTSEL 0x00000204 // Output Selection for GPT1 0 -#define EVENT_O_GPT1ACAPTSEL 0x00000300 +#define EVENT_O_GPT1ACAPTSEL 0x00000300 // Output Selection for GPT1 1 -#define EVENT_O_GPT1BCAPTSEL 0x00000304 +#define EVENT_O_GPT1BCAPTSEL 0x00000304 // Output Selection for GPT2 0 -#define EVENT_O_GPT2ACAPTSEL 0x00000400 +#define EVENT_O_GPT2ACAPTSEL 0x00000400 // Output Selection for GPT2 1 -#define EVENT_O_GPT2BCAPTSEL 0x00000404 +#define EVENT_O_GPT2BCAPTSEL 0x00000404 // Output Selection for DMA Channel 1 SREQ -#define EVENT_O_UDMACH1SSEL 0x00000508 +#define EVENT_O_UDMACH1SSEL 0x00000508 // Output Selection for DMA Channel 1 REQ -#define EVENT_O_UDMACH1BSEL 0x0000050C +#define EVENT_O_UDMACH1BSEL 0x0000050C // Output Selection for DMA Channel 2 SREQ -#define EVENT_O_UDMACH2SSEL 0x00000510 +#define EVENT_O_UDMACH2SSEL 0x00000510 // Output Selection for DMA Channel 2 REQ -#define EVENT_O_UDMACH2BSEL 0x00000514 +#define EVENT_O_UDMACH2BSEL 0x00000514 // Output Selection for DMA Channel 3 SREQ -#define EVENT_O_UDMACH3SSEL 0x00000518 +#define EVENT_O_UDMACH3SSEL 0x00000518 // Output Selection for DMA Channel 3 REQ -#define EVENT_O_UDMACH3BSEL 0x0000051C +#define EVENT_O_UDMACH3BSEL 0x0000051C // Output Selection for DMA Channel 4 SREQ -#define EVENT_O_UDMACH4SSEL 0x00000520 +#define EVENT_O_UDMACH4SSEL 0x00000520 // Output Selection for DMA Channel 4 REQ -#define EVENT_O_UDMACH4BSEL 0x00000524 +#define EVENT_O_UDMACH4BSEL 0x00000524 // Output Selection for DMA Channel 5 SREQ -#define EVENT_O_UDMACH5SSEL 0x00000528 +#define EVENT_O_UDMACH5SSEL 0x00000528 // Output Selection for DMA Channel 5 REQ -#define EVENT_O_UDMACH5BSEL 0x0000052C +#define EVENT_O_UDMACH5BSEL 0x0000052C // Output Selection for DMA Channel 6 SREQ -#define EVENT_O_UDMACH6SSEL 0x00000530 +#define EVENT_O_UDMACH6SSEL 0x00000530 // Output Selection for DMA Channel 6 REQ -#define EVENT_O_UDMACH6BSEL 0x00000534 +#define EVENT_O_UDMACH6BSEL 0x00000534 // Output Selection for DMA Channel 7 SREQ -#define EVENT_O_UDMACH7SSEL 0x00000538 +#define EVENT_O_UDMACH7SSEL 0x00000538 // Output Selection for DMA Channel 7 REQ -#define EVENT_O_UDMACH7BSEL 0x0000053C +#define EVENT_O_UDMACH7BSEL 0x0000053C // Output Selection for DMA Channel 8 SREQ -#define EVENT_O_UDMACH8SSEL 0x00000540 +#define EVENT_O_UDMACH8SSEL 0x00000540 // Output Selection for DMA Channel 8 REQ -#define EVENT_O_UDMACH8BSEL 0x00000544 +#define EVENT_O_UDMACH8BSEL 0x00000544 // Output Selection for DMA Channel 9 SREQ -#define EVENT_O_UDMACH9SSEL 0x00000548 +#define EVENT_O_UDMACH9SSEL 0x00000548 // Output Selection for DMA Channel 9 REQ -#define EVENT_O_UDMACH9BSEL 0x0000054C +#define EVENT_O_UDMACH9BSEL 0x0000054C // Output Selection for DMA Channel 10 SREQ -#define EVENT_O_UDMACH10SSEL 0x00000550 +#define EVENT_O_UDMACH10SSEL 0x00000550 // Output Selection for DMA Channel 10 REQ -#define EVENT_O_UDMACH10BSEL 0x00000554 +#define EVENT_O_UDMACH10BSEL 0x00000554 // Output Selection for DMA Channel 11 SREQ -#define EVENT_O_UDMACH11SSEL 0x00000558 +#define EVENT_O_UDMACH11SSEL 0x00000558 // Output Selection for DMA Channel 11 REQ -#define EVENT_O_UDMACH11BSEL 0x0000055C +#define EVENT_O_UDMACH11BSEL 0x0000055C // Output Selection for DMA Channel 12 SREQ -#define EVENT_O_UDMACH12SSEL 0x00000560 +#define EVENT_O_UDMACH12SSEL 0x00000560 // Output Selection for DMA Channel 12 REQ -#define EVENT_O_UDMACH12BSEL 0x00000564 +#define EVENT_O_UDMACH12BSEL 0x00000564 // Output Selection for DMA Channel 13 REQ -#define EVENT_O_UDMACH13BSEL 0x0000056C +#define EVENT_O_UDMACH13BSEL 0x0000056C // Output Selection for DMA Channel 14 REQ -#define EVENT_O_UDMACH14BSEL 0x00000574 +#define EVENT_O_UDMACH14BSEL 0x00000574 // Output Selection for DMA Channel 15 REQ -#define EVENT_O_UDMACH15BSEL 0x0000057C +#define EVENT_O_UDMACH15BSEL 0x0000057C // Output Selection for DMA Channel 16 SREQ -#define EVENT_O_UDMACH16SSEL 0x00000580 +#define EVENT_O_UDMACH16SSEL 0x00000580 // Output Selection for DMA Channel 16 REQ -#define EVENT_O_UDMACH16BSEL 0x00000584 +#define EVENT_O_UDMACH16BSEL 0x00000584 // Output Selection for DMA Channel 17 SREQ -#define EVENT_O_UDMACH17SSEL 0x00000588 +#define EVENT_O_UDMACH17SSEL 0x00000588 // Output Selection for DMA Channel 17 REQ -#define EVENT_O_UDMACH17BSEL 0x0000058C +#define EVENT_O_UDMACH17BSEL 0x0000058C // Output Selection for DMA Channel 21 SREQ -#define EVENT_O_UDMACH21SSEL 0x000005A8 +#define EVENT_O_UDMACH21SSEL 0x000005A8 // Output Selection for DMA Channel 21 REQ -#define EVENT_O_UDMACH21BSEL 0x000005AC +#define EVENT_O_UDMACH21BSEL 0x000005AC // Output Selection for DMA Channel 22 SREQ -#define EVENT_O_UDMACH22SSEL 0x000005B0 +#define EVENT_O_UDMACH22SSEL 0x000005B0 // Output Selection for DMA Channel 22 REQ -#define EVENT_O_UDMACH22BSEL 0x000005B4 +#define EVENT_O_UDMACH22BSEL 0x000005B4 // Output Selection for DMA Channel 23 SREQ -#define EVENT_O_UDMACH23SSEL 0x000005B8 +#define EVENT_O_UDMACH23SSEL 0x000005B8 // Output Selection for DMA Channel 23 REQ -#define EVENT_O_UDMACH23BSEL 0x000005BC +#define EVENT_O_UDMACH23BSEL 0x000005BC // Output Selection for DMA Channel 24 SREQ -#define EVENT_O_UDMACH24SSEL 0x000005C0 +#define EVENT_O_UDMACH24SSEL 0x000005C0 // Output Selection for DMA Channel 24 REQ -#define EVENT_O_UDMACH24BSEL 0x000005C4 +#define EVENT_O_UDMACH24BSEL 0x000005C4 // Output Selection for GPT3 0 -#define EVENT_O_GPT3ACAPTSEL 0x00000600 +#define EVENT_O_GPT3ACAPTSEL 0x00000600 // Output Selection for GPT3 1 -#define EVENT_O_GPT3BCAPTSEL 0x00000604 +#define EVENT_O_GPT3BCAPTSEL 0x00000604 // Output Selection for AUX Subscriber 0 -#define EVENT_O_AUXSEL0 0x00000700 +#define EVENT_O_AUXSEL0 0x00000700 // Output Selection for NMI Subscriber 0 -#define EVENT_O_CM3NMISEL0 0x00000800 +#define EVENT_O_CM3NMISEL0 0x00000800 // Output Selection for I2S Subscriber 0 -#define EVENT_O_I2SSTMPSEL0 0x00000900 +#define EVENT_O_I2SSTMPSEL0 0x00000900 // Output Selection for FRZ Subscriber -#define EVENT_O_FRZSEL0 0x00000A00 +#define EVENT_O_FRZSEL0 0x00000A00 // Set or Clear Software Events -#define EVENT_O_SWEV 0x00000F00 +#define EVENT_O_SWEV 0x00000F00 //***************************************************************************** // @@ -355,10 +355,10 @@ // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings -#define EVENT_CPUIRQSEL0_EV_W 7 -#define EVENT_CPUIRQSEL0_EV_M 0x0000007F -#define EVENT_CPUIRQSEL0_EV_S 0 -#define EVENT_CPUIRQSEL0_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_CPUIRQSEL0_EV_W 7 +#define EVENT_CPUIRQSEL0_EV_M 0x0000007F +#define EVENT_CPUIRQSEL0_EV_S 0 +#define EVENT_CPUIRQSEL0_EV_AON_GPIO_EDGE 0x00000004 //***************************************************************************** // @@ -370,10 +370,10 @@ // Read only selection value // ENUMs: // I2C_IRQ Interrupt event from I2C -#define EVENT_CPUIRQSEL1_EV_W 7 -#define EVENT_CPUIRQSEL1_EV_M 0x0000007F -#define EVENT_CPUIRQSEL1_EV_S 0 -#define EVENT_CPUIRQSEL1_EV_I2C_IRQ 0x00000009 +#define EVENT_CPUIRQSEL1_EV_W 7 +#define EVENT_CPUIRQSEL1_EV_M 0x0000007F +#define EVENT_CPUIRQSEL1_EV_S 0 +#define EVENT_CPUIRQSEL1_EV_I2C_IRQ 0x00000009 //***************************************************************************** // @@ -389,10 +389,10 @@ // RFC_DBELL:RFCPEIFG. Only interrupts selected // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a // RFC_CPE_1 event -#define EVENT_CPUIRQSEL2_EV_W 7 -#define EVENT_CPUIRQSEL2_EV_M 0x0000007F -#define EVENT_CPUIRQSEL2_EV_S 0 -#define EVENT_CPUIRQSEL2_EV_RFC_CPE_1 0x0000001E +#define EVENT_CPUIRQSEL2_EV_W 7 +#define EVENT_CPUIRQSEL2_EV_M 0x0000007F +#define EVENT_CPUIRQSEL2_EV_S 0 +#define EVENT_CPUIRQSEL2_EV_RFC_CPE_1 0x0000001E //***************************************************************************** // @@ -404,10 +404,10 @@ // Read only selection value // ENUMs: // PKA_IRQ PKA Interrupt event -#define EVENT_CPUIRQSEL3_EV_W 7 -#define EVENT_CPUIRQSEL3_EV_M 0x0000007F -#define EVENT_CPUIRQSEL3_EV_S 0 -#define EVENT_CPUIRQSEL3_EV_PKA_IRQ 0x0000001F +#define EVENT_CPUIRQSEL3_EV_W 7 +#define EVENT_CPUIRQSEL3_EV_M 0x0000007F +#define EVENT_CPUIRQSEL3_EV_S 0 +#define EVENT_CPUIRQSEL3_EV_PKA_IRQ 0x0000001F //***************************************************************************** // @@ -420,10 +420,10 @@ // ENUMs: // AON_RTC_COMB Event from AON_RTC, controlled by the // AON_RTC:CTL.COMB_EV_MASK setting -#define EVENT_CPUIRQSEL4_EV_W 7 -#define EVENT_CPUIRQSEL4_EV_M 0x0000007F -#define EVENT_CPUIRQSEL4_EV_S 0 -#define EVENT_CPUIRQSEL4_EV_AON_RTC_COMB 0x00000007 +#define EVENT_CPUIRQSEL4_EV_W 7 +#define EVENT_CPUIRQSEL4_EV_M 0x0000007F +#define EVENT_CPUIRQSEL4_EV_S 0 +#define EVENT_CPUIRQSEL4_EV_AON_RTC_COMB 0x00000007 //***************************************************************************** // @@ -436,10 +436,10 @@ // ENUMs: // UART0_COMB UART0 combined interrupt, interrupt flags are // found here UART0:MIS -#define EVENT_CPUIRQSEL5_EV_W 7 -#define EVENT_CPUIRQSEL5_EV_M 0x0000007F -#define EVENT_CPUIRQSEL5_EV_S 0 -#define EVENT_CPUIRQSEL5_EV_UART0_COMB 0x00000024 +#define EVENT_CPUIRQSEL5_EV_W 7 +#define EVENT_CPUIRQSEL5_EV_M 0x0000007F +#define EVENT_CPUIRQSEL5_EV_S 0 +#define EVENT_CPUIRQSEL5_EV_UART0_COMB 0x00000024 //***************************************************************************** // @@ -455,10 +455,10 @@ // AUX_EVENT0 AON wake up event. // MCU domain wakeup control // AON_EVENT:MCUWUSEL -#define EVENT_CPUIRQSEL6_EV_W 7 -#define EVENT_CPUIRQSEL6_EV_M 0x0000007F -#define EVENT_CPUIRQSEL6_EV_S 0 -#define EVENT_CPUIRQSEL6_EV_AUX_SWEV0 0x0000001C +#define EVENT_CPUIRQSEL6_EV_W 7 +#define EVENT_CPUIRQSEL6_EV_M 0x0000007F +#define EVENT_CPUIRQSEL6_EV_S 0 +#define EVENT_CPUIRQSEL6_EV_AUX_SWEV0 0x0000001C //***************************************************************************** // @@ -471,10 +471,10 @@ // ENUMs: // SSI0_COMB SSI0 combined interrupt, interrupt flags are found // here SSI0:MIS -#define EVENT_CPUIRQSEL7_EV_W 7 -#define EVENT_CPUIRQSEL7_EV_M 0x0000007F -#define EVENT_CPUIRQSEL7_EV_S 0 -#define EVENT_CPUIRQSEL7_EV_SSI0_COMB 0x00000022 +#define EVENT_CPUIRQSEL7_EV_W 7 +#define EVENT_CPUIRQSEL7_EV_M 0x0000007F +#define EVENT_CPUIRQSEL7_EV_S 0 +#define EVENT_CPUIRQSEL7_EV_SSI0_COMB 0x00000022 //***************************************************************************** // @@ -487,10 +487,10 @@ // ENUMs: // SSI1_COMB SSI1 combined interrupt, interrupt flags are found // here SSI1:MIS -#define EVENT_CPUIRQSEL8_EV_W 7 -#define EVENT_CPUIRQSEL8_EV_M 0x0000007F -#define EVENT_CPUIRQSEL8_EV_S 0 -#define EVENT_CPUIRQSEL8_EV_SSI1_COMB 0x00000023 +#define EVENT_CPUIRQSEL8_EV_W 7 +#define EVENT_CPUIRQSEL8_EV_M 0x0000007F +#define EVENT_CPUIRQSEL8_EV_S 0 +#define EVENT_CPUIRQSEL8_EV_SSI1_COMB 0x00000023 //***************************************************************************** // @@ -506,10 +506,10 @@ // RFC_DBELL:RFCPEIFG. Only interrupts selected // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a // RFC_CPE_0 event -#define EVENT_CPUIRQSEL9_EV_W 7 -#define EVENT_CPUIRQSEL9_EV_M 0x0000007F -#define EVENT_CPUIRQSEL9_EV_S 0 -#define EVENT_CPUIRQSEL9_EV_RFC_CPE_0 0x0000001B +#define EVENT_CPUIRQSEL9_EV_W 7 +#define EVENT_CPUIRQSEL9_EV_M 0x0000007F +#define EVENT_CPUIRQSEL9_EV_S 0 +#define EVENT_CPUIRQSEL9_EV_RFC_CPE_0 0x0000001B //***************************************************************************** // @@ -522,10 +522,10 @@ // ENUMs: // RFC_HW_COMB Combined RFC hardware interrupt, corresponding // flag is here RFC_DBELL:RFHWIFG -#define EVENT_CPUIRQSEL10_EV_W 7 -#define EVENT_CPUIRQSEL10_EV_M 0x0000007F -#define EVENT_CPUIRQSEL10_EV_S 0 -#define EVENT_CPUIRQSEL10_EV_RFC_HW_COMB 0x0000001A +#define EVENT_CPUIRQSEL10_EV_W 7 +#define EVENT_CPUIRQSEL10_EV_M 0x0000007F +#define EVENT_CPUIRQSEL10_EV_S 0 +#define EVENT_CPUIRQSEL10_EV_RFC_HW_COMB 0x0000001A //***************************************************************************** // @@ -538,10 +538,10 @@ // ENUMs: // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -#define EVENT_CPUIRQSEL11_EV_W 7 -#define EVENT_CPUIRQSEL11_EV_M 0x0000007F -#define EVENT_CPUIRQSEL11_EV_S 0 -#define EVENT_CPUIRQSEL11_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_CPUIRQSEL11_EV_W 7 +#define EVENT_CPUIRQSEL11_EV_M 0x0000007F +#define EVENT_CPUIRQSEL11_EV_S 0 +#define EVENT_CPUIRQSEL11_EV_RFC_CMD_ACK 0x00000019 //***************************************************************************** // @@ -553,10 +553,10 @@ // Read only selection value // ENUMs: // I2S_IRQ Interrupt event from I2S -#define EVENT_CPUIRQSEL12_EV_W 7 -#define EVENT_CPUIRQSEL12_EV_M 0x0000007F -#define EVENT_CPUIRQSEL12_EV_S 0 -#define EVENT_CPUIRQSEL12_EV_I2S_IRQ 0x00000008 +#define EVENT_CPUIRQSEL12_EV_W 7 +#define EVENT_CPUIRQSEL12_EV_M 0x0000007F +#define EVENT_CPUIRQSEL12_EV_S 0 +#define EVENT_CPUIRQSEL12_EV_I2S_IRQ 0x00000008 //***************************************************************************** // @@ -572,10 +572,10 @@ // AUX_EVENT2 AON wake up event. // MCU domain wakeup control // AON_EVENT:MCUWUSEL -#define EVENT_CPUIRQSEL13_EV_W 7 -#define EVENT_CPUIRQSEL13_EV_M 0x0000007F -#define EVENT_CPUIRQSEL13_EV_S 0 -#define EVENT_CPUIRQSEL13_EV_AUX_SWEV1 0x0000001D +#define EVENT_CPUIRQSEL13_EV_W 7 +#define EVENT_CPUIRQSEL13_EV_M 0x0000007F +#define EVENT_CPUIRQSEL13_EV_S 0 +#define EVENT_CPUIRQSEL13_EV_AUX_SWEV1 0x0000001D //***************************************************************************** // @@ -588,10 +588,10 @@ // ENUMs: // WDT_IRQ Watchdog interrupt event, controlled by // WDT:CTL.INTEN -#define EVENT_CPUIRQSEL14_EV_W 7 -#define EVENT_CPUIRQSEL14_EV_M 0x0000007F -#define EVENT_CPUIRQSEL14_EV_S 0 -#define EVENT_CPUIRQSEL14_EV_WDT_IRQ 0x00000018 +#define EVENT_CPUIRQSEL14_EV_W 7 +#define EVENT_CPUIRQSEL14_EV_M 0x0000007F +#define EVENT_CPUIRQSEL14_EV_S 0 +#define EVENT_CPUIRQSEL14_EV_WDT_IRQ 0x00000018 //***************************************************************************** // @@ -603,10 +603,10 @@ // Read only selection value // ENUMs: // GPT0A GPT0A interrupt event, controlled by GPT0:TAMR -#define EVENT_CPUIRQSEL15_EV_W 7 -#define EVENT_CPUIRQSEL15_EV_M 0x0000007F -#define EVENT_CPUIRQSEL15_EV_S 0 -#define EVENT_CPUIRQSEL15_EV_GPT0A 0x00000010 +#define EVENT_CPUIRQSEL15_EV_W 7 +#define EVENT_CPUIRQSEL15_EV_M 0x0000007F +#define EVENT_CPUIRQSEL15_EV_S 0 +#define EVENT_CPUIRQSEL15_EV_GPT0A 0x00000010 //***************************************************************************** // @@ -618,10 +618,10 @@ // Read only selection value // ENUMs: // GPT0B GPT0B interrupt event, controlled by GPT0:TBMR -#define EVENT_CPUIRQSEL16_EV_W 7 -#define EVENT_CPUIRQSEL16_EV_M 0x0000007F -#define EVENT_CPUIRQSEL16_EV_S 0 -#define EVENT_CPUIRQSEL16_EV_GPT0B 0x00000011 +#define EVENT_CPUIRQSEL16_EV_W 7 +#define EVENT_CPUIRQSEL16_EV_M 0x0000007F +#define EVENT_CPUIRQSEL16_EV_S 0 +#define EVENT_CPUIRQSEL16_EV_GPT0B 0x00000011 //***************************************************************************** // @@ -633,10 +633,10 @@ // Read only selection value // ENUMs: // GPT1A GPT1A interrupt event, controlled by GPT1:TAMR -#define EVENT_CPUIRQSEL17_EV_W 7 -#define EVENT_CPUIRQSEL17_EV_M 0x0000007F -#define EVENT_CPUIRQSEL17_EV_S 0 -#define EVENT_CPUIRQSEL17_EV_GPT1A 0x00000012 +#define EVENT_CPUIRQSEL17_EV_W 7 +#define EVENT_CPUIRQSEL17_EV_M 0x0000007F +#define EVENT_CPUIRQSEL17_EV_S 0 +#define EVENT_CPUIRQSEL17_EV_GPT1A 0x00000012 //***************************************************************************** // @@ -648,10 +648,10 @@ // Read only selection value // ENUMs: // GPT1B GPT1B interrupt event, controlled by GPT1:TBMR -#define EVENT_CPUIRQSEL18_EV_W 7 -#define EVENT_CPUIRQSEL18_EV_M 0x0000007F -#define EVENT_CPUIRQSEL18_EV_S 0 -#define EVENT_CPUIRQSEL18_EV_GPT1B 0x00000013 +#define EVENT_CPUIRQSEL18_EV_W 7 +#define EVENT_CPUIRQSEL18_EV_M 0x0000007F +#define EVENT_CPUIRQSEL18_EV_S 0 +#define EVENT_CPUIRQSEL18_EV_GPT1B 0x00000013 //***************************************************************************** // @@ -663,10 +663,10 @@ // Read only selection value // ENUMs: // GPT2A GPT2A interrupt event, controlled by GPT2:TAMR -#define EVENT_CPUIRQSEL19_EV_W 7 -#define EVENT_CPUIRQSEL19_EV_M 0x0000007F -#define EVENT_CPUIRQSEL19_EV_S 0 -#define EVENT_CPUIRQSEL19_EV_GPT2A 0x0000000C +#define EVENT_CPUIRQSEL19_EV_W 7 +#define EVENT_CPUIRQSEL19_EV_M 0x0000007F +#define EVENT_CPUIRQSEL19_EV_S 0 +#define EVENT_CPUIRQSEL19_EV_GPT2A 0x0000000C //***************************************************************************** // @@ -678,10 +678,10 @@ // Read only selection value // ENUMs: // GPT2B GPT2B interrupt event, controlled by GPT2:TBMR -#define EVENT_CPUIRQSEL20_EV_W 7 -#define EVENT_CPUIRQSEL20_EV_M 0x0000007F -#define EVENT_CPUIRQSEL20_EV_S 0 -#define EVENT_CPUIRQSEL20_EV_GPT2B 0x0000000D +#define EVENT_CPUIRQSEL20_EV_W 7 +#define EVENT_CPUIRQSEL20_EV_M 0x0000007F +#define EVENT_CPUIRQSEL20_EV_S 0 +#define EVENT_CPUIRQSEL20_EV_GPT2B 0x0000000D //***************************************************************************** // @@ -693,10 +693,10 @@ // Read only selection value // ENUMs: // GPT3A GPT3A interrupt event, controlled by GPT3:TAMR -#define EVENT_CPUIRQSEL21_EV_W 7 -#define EVENT_CPUIRQSEL21_EV_M 0x0000007F -#define EVENT_CPUIRQSEL21_EV_S 0 -#define EVENT_CPUIRQSEL21_EV_GPT3A 0x0000000E +#define EVENT_CPUIRQSEL21_EV_W 7 +#define EVENT_CPUIRQSEL21_EV_M 0x0000007F +#define EVENT_CPUIRQSEL21_EV_S 0 +#define EVENT_CPUIRQSEL21_EV_GPT3A 0x0000000E //***************************************************************************** // @@ -708,10 +708,10 @@ // Read only selection value // ENUMs: // GPT3B GPT3B interrupt event, controlled by GPT3:TBMR -#define EVENT_CPUIRQSEL22_EV_W 7 -#define EVENT_CPUIRQSEL22_EV_M 0x0000007F -#define EVENT_CPUIRQSEL22_EV_S 0 -#define EVENT_CPUIRQSEL22_EV_GPT3B 0x0000000F +#define EVENT_CPUIRQSEL22_EV_W 7 +#define EVENT_CPUIRQSEL22_EV_M 0x0000007F +#define EVENT_CPUIRQSEL22_EV_S 0 +#define EVENT_CPUIRQSEL22_EV_GPT3B 0x0000000F //***************************************************************************** // @@ -726,10 +726,10 @@ // corresponding flag is found here // CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by // CRYPTO:IRQSTAT.RESULT_AVAIL -#define EVENT_CPUIRQSEL23_EV_W 7 -#define EVENT_CPUIRQSEL23_EV_M 0x0000007F -#define EVENT_CPUIRQSEL23_EV_S 0 -#define EVENT_CPUIRQSEL23_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D +#define EVENT_CPUIRQSEL23_EV_W 7 +#define EVENT_CPUIRQSEL23_EV_M 0x0000007F +#define EVENT_CPUIRQSEL23_EV_S 0 +#define EVENT_CPUIRQSEL23_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D //***************************************************************************** // @@ -742,10 +742,10 @@ // ENUMs: // DMA_DONE_COMB Combined DMA done, corresponding flags are here // UDMA0:REQDONE -#define EVENT_CPUIRQSEL24_EV_W 7 -#define EVENT_CPUIRQSEL24_EV_M 0x0000007F -#define EVENT_CPUIRQSEL24_EV_S 0 -#define EVENT_CPUIRQSEL24_EV_DMA_DONE_COMB 0x00000027 +#define EVENT_CPUIRQSEL24_EV_W 7 +#define EVENT_CPUIRQSEL24_EV_M 0x0000007F +#define EVENT_CPUIRQSEL24_EV_S 0 +#define EVENT_CPUIRQSEL24_EV_DMA_DONE_COMB 0x00000027 //***************************************************************************** // @@ -757,10 +757,10 @@ // Read only selection value // ENUMs: // DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS -#define EVENT_CPUIRQSEL25_EV_W 7 -#define EVENT_CPUIRQSEL25_EV_M 0x0000007F -#define EVENT_CPUIRQSEL25_EV_S 0 -#define EVENT_CPUIRQSEL25_EV_DMA_ERR 0x00000026 +#define EVENT_CPUIRQSEL25_EV_W 7 +#define EVENT_CPUIRQSEL25_EV_M 0x0000007F +#define EVENT_CPUIRQSEL25_EV_S 0 +#define EVENT_CPUIRQSEL25_EV_DMA_ERR 0x00000026 //***************************************************************************** // @@ -774,10 +774,10 @@ // FLASH FLASH controller error event, the status flags // are FLASH:FEDACSTAT.FSM_DONE and // FLASH:FEDACSTAT.RVF_INT -#define EVENT_CPUIRQSEL26_EV_W 7 -#define EVENT_CPUIRQSEL26_EV_M 0x0000007F -#define EVENT_CPUIRQSEL26_EV_S 0 -#define EVENT_CPUIRQSEL26_EV_FLASH 0x00000015 +#define EVENT_CPUIRQSEL26_EV_W 7 +#define EVENT_CPUIRQSEL26_EV_M 0x0000007F +#define EVENT_CPUIRQSEL26_EV_S 0 +#define EVENT_CPUIRQSEL26_EV_FLASH 0x00000015 //***************************************************************************** // @@ -789,10 +789,10 @@ // Read only selection value // ENUMs: // SWEV0 Software event 0, triggered by SWEV.SWEV0 -#define EVENT_CPUIRQSEL27_EV_W 7 -#define EVENT_CPUIRQSEL27_EV_M 0x0000007F -#define EVENT_CPUIRQSEL27_EV_S 0 -#define EVENT_CPUIRQSEL27_EV_SWEV0 0x00000064 +#define EVENT_CPUIRQSEL27_EV_W 7 +#define EVENT_CPUIRQSEL27_EV_M 0x0000007F +#define EVENT_CPUIRQSEL27_EV_S 0 +#define EVENT_CPUIRQSEL27_EV_SWEV0 0x00000064 //***************************************************************************** // @@ -805,10 +805,10 @@ // ENUMs: // AUX_COMB AUX combined event, the corresponding flag // register is here AUX_EVCTL:EVTOMCUFLAGS -#define EVENT_CPUIRQSEL28_EV_W 7 -#define EVENT_CPUIRQSEL28_EV_M 0x0000007F -#define EVENT_CPUIRQSEL28_EV_S 0 -#define EVENT_CPUIRQSEL28_EV_AUX_COMB 0x0000000B +#define EVENT_CPUIRQSEL28_EV_W 7 +#define EVENT_CPUIRQSEL28_EV_M 0x0000007F +#define EVENT_CPUIRQSEL28_EV_S 0 +#define EVENT_CPUIRQSEL28_EV_AUX_COMB 0x0000000B //***************************************************************************** // @@ -822,10 +822,10 @@ // AON_PROG0 AON programmable event 0. Event selected by // AON_EVENT MCU event selector, // AON_EVENT:EVTOMCUSEL.AON_PROG0_EV -#define EVENT_CPUIRQSEL29_EV_W 7 -#define EVENT_CPUIRQSEL29_EV_M 0x0000007F -#define EVENT_CPUIRQSEL29_EV_S 0 -#define EVENT_CPUIRQSEL29_EV_AON_PROG0 0x00000001 +#define EVENT_CPUIRQSEL29_EV_W 7 +#define EVENT_CPUIRQSEL29_EV_M 0x0000007F +#define EVENT_CPUIRQSEL29_EV_S 0 +#define EVENT_CPUIRQSEL29_EV_AON_PROG0 0x00000001 //***************************************************************************** // @@ -887,33 +887,33 @@ // AON_EVENT MCU event selector, // AON_EVENT:EVTOMCUSEL.AON_PROG1_EV // NONE Always inactive -#define EVENT_CPUIRQSEL30_EV_W 7 -#define EVENT_CPUIRQSEL30_EV_M 0x0000007F -#define EVENT_CPUIRQSEL30_EV_S 0 -#define EVENT_CPUIRQSEL30_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_CPUIRQSEL30_EV_AON_RTC_UPD 0x00000077 -#define EVENT_CPUIRQSEL30_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_CPUIRQSEL30_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_CPUIRQSEL30_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_CPUIRQSEL30_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_CPUIRQSEL30_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_CPUIRQSEL30_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_CPUIRQSEL30_EV_AUX_COMPB 0x0000006B -#define EVENT_CPUIRQSEL30_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_CPUIRQSEL30_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E -#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_CPUIRQSEL30_EV_DMA_CH18_DONE 0x00000016 -#define EVENT_CPUIRQSEL30_EV_DMA_CH0_DONE 0x00000014 -#define EVENT_CPUIRQSEL30_EV_AON_AUX_SWEV0 0x0000000A -#define EVENT_CPUIRQSEL30_EV_I2S_IRQ 0x00000008 -#define EVENT_CPUIRQSEL30_EV_AON_PROG2 0x00000003 -#define EVENT_CPUIRQSEL30_EV_AON_PROG1 0x00000002 -#define EVENT_CPUIRQSEL30_EV_NONE 0x00000000 +#define EVENT_CPUIRQSEL30_EV_W 7 +#define EVENT_CPUIRQSEL30_EV_M 0x0000007F +#define EVENT_CPUIRQSEL30_EV_S 0 +#define EVENT_CPUIRQSEL30_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_CPUIRQSEL30_EV_AON_RTC_UPD 0x00000077 +#define EVENT_CPUIRQSEL30_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_CPUIRQSEL30_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_CPUIRQSEL30_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_CPUIRQSEL30_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_CPUIRQSEL30_EV_AUX_COMPB 0x0000006B +#define EVENT_CPUIRQSEL30_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_CPUIRQSEL30_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_CPUIRQSEL30_EV_DMA_CH18_DONE 0x00000016 +#define EVENT_CPUIRQSEL30_EV_DMA_CH0_DONE 0x00000014 +#define EVENT_CPUIRQSEL30_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_CPUIRQSEL30_EV_I2S_IRQ 0x00000008 +#define EVENT_CPUIRQSEL30_EV_AON_PROG2 0x00000003 +#define EVENT_CPUIRQSEL30_EV_AON_PROG1 0x00000002 +#define EVENT_CPUIRQSEL30_EV_NONE 0x00000000 //***************************************************************************** // @@ -926,10 +926,10 @@ // ENUMs: // AUX_COMPA AUX Compare A event, corresponds to // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -#define EVENT_CPUIRQSEL31_EV_W 7 -#define EVENT_CPUIRQSEL31_EV_M 0x0000007F -#define EVENT_CPUIRQSEL31_EV_S 0 -#define EVENT_CPUIRQSEL31_EV_AUX_COMPA 0x0000006A +#define EVENT_CPUIRQSEL31_EV_W 7 +#define EVENT_CPUIRQSEL31_EV_M 0x0000007F +#define EVENT_CPUIRQSEL31_EV_S 0 +#define EVENT_CPUIRQSEL31_EV_AUX_COMPA 0x0000006A //***************************************************************************** // @@ -943,10 +943,10 @@ // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to // AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status // flags are found here AUX_EVCTL:EVTOMCUFLAGS -#define EVENT_CPUIRQSEL32_EV_W 7 -#define EVENT_CPUIRQSEL32_EV_M 0x0000007F -#define EVENT_CPUIRQSEL32_EV_S 0 -#define EVENT_CPUIRQSEL32_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_CPUIRQSEL32_EV_W 7 +#define EVENT_CPUIRQSEL32_EV_M 0x0000007F +#define EVENT_CPUIRQSEL32_EV_S 0 +#define EVENT_CPUIRQSEL32_EV_AUX_ADC_IRQ 0x00000073 //***************************************************************************** // @@ -958,10 +958,10 @@ // Read only selection value // ENUMs: // TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN -#define EVENT_CPUIRQSEL33_EV_W 7 -#define EVENT_CPUIRQSEL33_EV_M 0x0000007F -#define EVENT_CPUIRQSEL33_EV_S 0 -#define EVENT_CPUIRQSEL33_EV_TRNG_IRQ 0x00000068 +#define EVENT_CPUIRQSEL33_EV_W 7 +#define EVENT_CPUIRQSEL33_EV_M 0x0000007F +#define EVENT_CPUIRQSEL33_EV_S 0 +#define EVENT_CPUIRQSEL33_EV_TRNG_IRQ 0x00000068 //***************************************************************************** // @@ -973,10 +973,10 @@ // Read only selection value // ENUMs: // OSC_COMB Combined event from Oscillator control -#define EVENT_CPUIRQSEL34_EV_W 7 -#define EVENT_CPUIRQSEL34_EV_M 0x0000007F -#define EVENT_CPUIRQSEL34_EV_S 0 -#define EVENT_CPUIRQSEL34_EV_OSC_COMB 0x00000006 +#define EVENT_CPUIRQSEL34_EV_W 7 +#define EVENT_CPUIRQSEL34_EV_M 0x0000007F +#define EVENT_CPUIRQSEL34_EV_S 0 +#define EVENT_CPUIRQSEL34_EV_OSC_COMB 0x00000006 //***************************************************************************** // @@ -989,10 +989,10 @@ // ENUMs: // AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag // AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 -#define EVENT_CPUIRQSEL35_EV_W 7 -#define EVENT_CPUIRQSEL35_EV_M 0x0000007F -#define EVENT_CPUIRQSEL35_EV_S 0 -#define EVENT_CPUIRQSEL35_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_CPUIRQSEL35_EV_W 7 +#define EVENT_CPUIRQSEL35_EV_M 0x0000007F +#define EVENT_CPUIRQSEL35_EV_S 0 +#define EVENT_CPUIRQSEL35_EV_AUX_TIMER2_EV0 0x00000038 //***************************************************************************** // @@ -1005,10 +1005,10 @@ // ENUMs: // UART1_COMB UART1 combined interrupt, interrupt flags are // found here UART1:MIS -#define EVENT_CPUIRQSEL36_EV_W 7 -#define EVENT_CPUIRQSEL36_EV_M 0x0000007F -#define EVENT_CPUIRQSEL36_EV_S 0 -#define EVENT_CPUIRQSEL36_EV_UART1_COMB 0x00000025 +#define EVENT_CPUIRQSEL36_EV_W 7 +#define EVENT_CPUIRQSEL36_EV_M 0x0000007F +#define EVENT_CPUIRQSEL36_EV_S 0 +#define EVENT_CPUIRQSEL36_EV_UART1_COMB 0x00000025 //***************************************************************************** // @@ -1020,10 +1020,10 @@ // Read only selection value // ENUMs: // BATMON_COMB Combined event from battery monitor -#define EVENT_CPUIRQSEL37_EV_W 7 -#define EVENT_CPUIRQSEL37_EV_M 0x0000007F -#define EVENT_CPUIRQSEL37_EV_S 0 -#define EVENT_CPUIRQSEL37_EV_BATMON_COMB 0x00000005 +#define EVENT_CPUIRQSEL37_EV_W 7 +#define EVENT_CPUIRQSEL37_EV_M 0x0000007F +#define EVENT_CPUIRQSEL37_EV_S 0 +#define EVENT_CPUIRQSEL37_EV_BATMON_COMB 0x00000005 //***************************************************************************** // @@ -1035,10 +1035,10 @@ // Read only selection value // ENUMs: // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -#define EVENT_RFCSEL0_EV_W 7 -#define EVENT_RFCSEL0_EV_M 0x0000007F -#define EVENT_RFCSEL0_EV_S 0 -#define EVENT_RFCSEL0_EV_GPT0A_CMP 0x0000003D +#define EVENT_RFCSEL0_EV_W 7 +#define EVENT_RFCSEL0_EV_M 0x0000007F +#define EVENT_RFCSEL0_EV_S 0 +#define EVENT_RFCSEL0_EV_GPT0A_CMP 0x0000003D //***************************************************************************** // @@ -1050,10 +1050,10 @@ // Read only selection value // ENUMs: // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -#define EVENT_RFCSEL1_EV_W 7 -#define EVENT_RFCSEL1_EV_M 0x0000007F -#define EVENT_RFCSEL1_EV_S 0 -#define EVENT_RFCSEL1_EV_GPT0B_CMP 0x0000003E +#define EVENT_RFCSEL1_EV_W 7 +#define EVENT_RFCSEL1_EV_M 0x0000007F +#define EVENT_RFCSEL1_EV_S 0 +#define EVENT_RFCSEL1_EV_GPT0B_CMP 0x0000003E //***************************************************************************** // @@ -1065,10 +1065,10 @@ // Read only selection value // ENUMs: // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -#define EVENT_RFCSEL2_EV_W 7 -#define EVENT_RFCSEL2_EV_M 0x0000007F -#define EVENT_RFCSEL2_EV_S 0 -#define EVENT_RFCSEL2_EV_GPT1A_CMP 0x0000003F +#define EVENT_RFCSEL2_EV_W 7 +#define EVENT_RFCSEL2_EV_M 0x0000007F +#define EVENT_RFCSEL2_EV_S 0 +#define EVENT_RFCSEL2_EV_GPT1A_CMP 0x0000003F //***************************************************************************** // @@ -1080,10 +1080,10 @@ // Read only selection value // ENUMs: // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -#define EVENT_RFCSEL3_EV_W 7 -#define EVENT_RFCSEL3_EV_M 0x0000007F -#define EVENT_RFCSEL3_EV_S 0 -#define EVENT_RFCSEL3_EV_GPT1B_CMP 0x00000040 +#define EVENT_RFCSEL3_EV_W 7 +#define EVENT_RFCSEL3_EV_M 0x0000007F +#define EVENT_RFCSEL3_EV_S 0 +#define EVENT_RFCSEL3_EV_GPT1B_CMP 0x00000040 //***************************************************************************** // @@ -1095,10 +1095,10 @@ // Read only selection value // ENUMs: // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -#define EVENT_RFCSEL4_EV_W 7 -#define EVENT_RFCSEL4_EV_M 0x0000007F -#define EVENT_RFCSEL4_EV_S 0 -#define EVENT_RFCSEL4_EV_GPT2A_CMP 0x00000041 +#define EVENT_RFCSEL4_EV_W 7 +#define EVENT_RFCSEL4_EV_M 0x0000007F +#define EVENT_RFCSEL4_EV_S 0 +#define EVENT_RFCSEL4_EV_GPT2A_CMP 0x00000041 //***************************************************************************** // @@ -1110,10 +1110,10 @@ // Read only selection value // ENUMs: // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -#define EVENT_RFCSEL5_EV_W 7 -#define EVENT_RFCSEL5_EV_M 0x0000007F -#define EVENT_RFCSEL5_EV_S 0 -#define EVENT_RFCSEL5_EV_GPT2B_CMP 0x00000042 +#define EVENT_RFCSEL5_EV_W 7 +#define EVENT_RFCSEL5_EV_M 0x0000007F +#define EVENT_RFCSEL5_EV_S 0 +#define EVENT_RFCSEL5_EV_GPT2B_CMP 0x00000042 //***************************************************************************** // @@ -1125,10 +1125,10 @@ // Read only selection value // ENUMs: // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -#define EVENT_RFCSEL6_EV_W 7 -#define EVENT_RFCSEL6_EV_M 0x0000007F -#define EVENT_RFCSEL6_EV_S 0 -#define EVENT_RFCSEL6_EV_GPT3A_CMP 0x00000043 +#define EVENT_RFCSEL6_EV_W 7 +#define EVENT_RFCSEL6_EV_M 0x0000007F +#define EVENT_RFCSEL6_EV_S 0 +#define EVENT_RFCSEL6_EV_GPT3A_CMP 0x00000043 //***************************************************************************** // @@ -1140,10 +1140,10 @@ // Read only selection value // ENUMs: // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -#define EVENT_RFCSEL7_EV_W 7 -#define EVENT_RFCSEL7_EV_M 0x0000007F -#define EVENT_RFCSEL7_EV_S 0 -#define EVENT_RFCSEL7_EV_GPT3B_CMP 0x00000044 +#define EVENT_RFCSEL7_EV_W 7 +#define EVENT_RFCSEL7_EV_M 0x0000007F +#define EVENT_RFCSEL7_EV_S 0 +#define EVENT_RFCSEL7_EV_GPT3B_CMP 0x00000044 //***************************************************************************** // @@ -1156,10 +1156,10 @@ // ENUMs: // AON_RTC_UPD RTC periodic event controlled by // AON_RTC:CTL.RTC_UPD_EN -#define EVENT_RFCSEL8_EV_W 7 -#define EVENT_RFCSEL8_EV_M 0x0000007F -#define EVENT_RFCSEL8_EV_S 0 -#define EVENT_RFCSEL8_EV_AON_RTC_UPD 0x00000077 +#define EVENT_RFCSEL8_EV_W 7 +#define EVENT_RFCSEL8_EV_M 0x0000007F +#define EVENT_RFCSEL8_EV_S 0 +#define EVENT_RFCSEL8_EV_AON_RTC_UPD 0x00000077 //***************************************************************************** // @@ -1235,40 +1235,40 @@ // AON_EVENT MCU event selector, // AON_EVENT:EVTOMCUSEL.AON_PROG0_EV // NONE Always inactive -#define EVENT_RFCSEL9_EV_W 7 -#define EVENT_RFCSEL9_EV_M 0x0000007F -#define EVENT_RFCSEL9_EV_S 0 -#define EVENT_RFCSEL9_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_RFCSEL9_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_RFCSEL9_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_RFCSEL9_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_RFCSEL9_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_RFCSEL9_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_RFCSEL9_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_RFCSEL9_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_RFCSEL9_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_RFCSEL9_EV_AUX_COMPB 0x0000006B -#define EVENT_RFCSEL9_EV_AUX_COMPA 0x0000006A -#define EVENT_RFCSEL9_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_RFCSEL9_EV_SWEV1 0x00000065 -#define EVENT_RFCSEL9_EV_SWEV0 0x00000064 -#define EVENT_RFCSEL9_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D -#define EVENT_RFCSEL9_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_RFCSEL9_EV_DMA_DONE_COMB 0x00000027 -#define EVENT_RFCSEL9_EV_UART1_COMB 0x00000025 -#define EVENT_RFCSEL9_EV_UART0_COMB 0x00000024 -#define EVENT_RFCSEL9_EV_SSI1_COMB 0x00000023 -#define EVENT_RFCSEL9_EV_SSI0_COMB 0x00000022 -#define EVENT_RFCSEL9_EV_WDT_IRQ 0x00000018 -#define EVENT_RFCSEL9_EV_AON_AUX_SWEV0 0x0000000A -#define EVENT_RFCSEL9_EV_I2S_IRQ 0x00000008 -#define EVENT_RFCSEL9_EV_AON_PROG1 0x00000002 -#define EVENT_RFCSEL9_EV_AON_PROG0 0x00000001 -#define EVENT_RFCSEL9_EV_NONE 0x00000000 +#define EVENT_RFCSEL9_EV_W 7 +#define EVENT_RFCSEL9_EV_M 0x0000007F +#define EVENT_RFCSEL9_EV_S 0 +#define EVENT_RFCSEL9_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_RFCSEL9_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_RFCSEL9_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_RFCSEL9_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_RFCSEL9_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_RFCSEL9_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_RFCSEL9_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_RFCSEL9_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_RFCSEL9_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_RFCSEL9_EV_AUX_COMPB 0x0000006B +#define EVENT_RFCSEL9_EV_AUX_COMPA 0x0000006A +#define EVENT_RFCSEL9_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_RFCSEL9_EV_SWEV1 0x00000065 +#define EVENT_RFCSEL9_EV_SWEV0 0x00000064 +#define EVENT_RFCSEL9_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D +#define EVENT_RFCSEL9_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_RFCSEL9_EV_DMA_DONE_COMB 0x00000027 +#define EVENT_RFCSEL9_EV_UART1_COMB 0x00000025 +#define EVENT_RFCSEL9_EV_UART0_COMB 0x00000024 +#define EVENT_RFCSEL9_EV_SSI1_COMB 0x00000023 +#define EVENT_RFCSEL9_EV_SSI0_COMB 0x00000022 +#define EVENT_RFCSEL9_EV_WDT_IRQ 0x00000018 +#define EVENT_RFCSEL9_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_RFCSEL9_EV_I2S_IRQ 0x00000008 +#define EVENT_RFCSEL9_EV_AON_PROG1 0x00000002 +#define EVENT_RFCSEL9_EV_AON_PROG0 0x00000001 +#define EVENT_RFCSEL9_EV_NONE 0x00000000 //***************************************************************************** // @@ -1369,53 +1369,53 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT0ACAPTSEL_EV_W 7 -#define EVENT_GPT0ACAPTSEL_EV_M 0x0000007F -#define EVENT_GPT0ACAPTSEL_EV_S 0 -#define EVENT_GPT0ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT0ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT0ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT0ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT0ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT1 0x00000056 -#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT0 0x00000055 -#define EVENT_GPT0ACAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT0ACAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT0ACAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT0ACAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT0ACAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT0ACAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT0ACAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT0ACAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_GPT0ACAPTSEL_EV_UART1_COMB 0x00000025 -#define EVENT_GPT0ACAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT0ACAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT0ACAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT0ACAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT0ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT0ACAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT0ACAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT0ACAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT0ACAPTSEL_EV_OSC_COMB 0x00000006 -#define EVENT_GPT0ACAPTSEL_EV_BATMON_COMB 0x00000005 -#define EVENT_GPT0ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT0ACAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT0ACAPTSEL_EV_W 7 +#define EVENT_GPT0ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT0ACAPTSEL_EV_S 0 +#define EVENT_GPT0ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT0ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT0ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT0ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT0ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_GPT0ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT0ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT0ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT0ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT0ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT0ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT0ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT0ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT0ACAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT0ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT0ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT0ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT0ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT0ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT0ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT0ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT0ACAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT0ACAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT0ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT0ACAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -1516,53 +1516,53 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT0BCAPTSEL_EV_W 7 -#define EVENT_GPT0BCAPTSEL_EV_M 0x0000007F -#define EVENT_GPT0BCAPTSEL_EV_S 0 -#define EVENT_GPT0BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT0BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT0BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT0BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT0BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT1 0x00000056 -#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT0 0x00000055 -#define EVENT_GPT0BCAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT0BCAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT0BCAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT0BCAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT0BCAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT0BCAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT0BCAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT0BCAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_GPT0BCAPTSEL_EV_UART1_COMB 0x00000025 -#define EVENT_GPT0BCAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT0BCAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT0BCAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT0BCAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT0BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT0BCAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT0BCAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT0BCAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT0BCAPTSEL_EV_OSC_COMB 0x00000006 -#define EVENT_GPT0BCAPTSEL_EV_BATMON_COMB 0x00000005 -#define EVENT_GPT0BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT0BCAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT0BCAPTSEL_EV_W 7 +#define EVENT_GPT0BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT0BCAPTSEL_EV_S 0 +#define EVENT_GPT0BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT0BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT0BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT0BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT0BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_GPT0BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT0BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT0BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT0BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT0BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT0BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT0BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT0BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT0BCAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT0BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT0BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT0BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT0BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT0BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT0BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT0BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT0BCAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT0BCAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT0BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT0BCAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -1663,53 +1663,53 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT1ACAPTSEL_EV_W 7 -#define EVENT_GPT1ACAPTSEL_EV_M 0x0000007F -#define EVENT_GPT1ACAPTSEL_EV_S 0 -#define EVENT_GPT1ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT1ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT1ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT1ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT1ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT3 0x00000058 -#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT2 0x00000057 -#define EVENT_GPT1ACAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT1ACAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT1ACAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT1ACAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT1ACAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT1ACAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT1ACAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT1ACAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_GPT1ACAPTSEL_EV_UART1_COMB 0x00000025 -#define EVENT_GPT1ACAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT1ACAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT1ACAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT1ACAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT1ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT1ACAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT1ACAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT1ACAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT1ACAPTSEL_EV_OSC_COMB 0x00000006 -#define EVENT_GPT1ACAPTSEL_EV_BATMON_COMB 0x00000005 -#define EVENT_GPT1ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT1ACAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT1ACAPTSEL_EV_W 7 +#define EVENT_GPT1ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT1ACAPTSEL_EV_S 0 +#define EVENT_GPT1ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT1ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT1ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT1ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT1ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_GPT1ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT1ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT1ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT1ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT1ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT1ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT1ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT1ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT1ACAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT1ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT1ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT1ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT1ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT1ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT1ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT1ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT1ACAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT1ACAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT1ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT1ACAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -1810,53 +1810,53 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT1BCAPTSEL_EV_W 7 -#define EVENT_GPT1BCAPTSEL_EV_M 0x0000007F -#define EVENT_GPT1BCAPTSEL_EV_S 0 -#define EVENT_GPT1BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT1BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT1BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT1BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT1BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT3 0x00000058 -#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT2 0x00000057 -#define EVENT_GPT1BCAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT1BCAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT1BCAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT1BCAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT1BCAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT1BCAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT1BCAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT1BCAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_GPT1BCAPTSEL_EV_UART1_COMB 0x00000025 -#define EVENT_GPT1BCAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT1BCAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT1BCAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT1BCAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT1BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT1BCAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT1BCAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT1BCAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT1BCAPTSEL_EV_OSC_COMB 0x00000006 -#define EVENT_GPT1BCAPTSEL_EV_BATMON_COMB 0x00000005 -#define EVENT_GPT1BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT1BCAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT1BCAPTSEL_EV_W 7 +#define EVENT_GPT1BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT1BCAPTSEL_EV_S 0 +#define EVENT_GPT1BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT1BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT1BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT1BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT1BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_GPT1BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT1BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT1BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT1BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT1BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT1BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT1BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT1BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT1BCAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT1BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT1BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT1BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT1BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT1BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT1BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT1BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT1BCAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT1BCAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT1BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT1BCAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -1957,53 +1957,53 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT2ACAPTSEL_EV_W 7 -#define EVENT_GPT2ACAPTSEL_EV_M 0x0000007F -#define EVENT_GPT2ACAPTSEL_EV_S 0 -#define EVENT_GPT2ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT2ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT2ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT2ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT2ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT5 0x0000005A -#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT4 0x00000059 -#define EVENT_GPT2ACAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT2ACAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT2ACAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT2ACAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT2ACAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT2ACAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT2ACAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT2ACAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_GPT2ACAPTSEL_EV_UART1_COMB 0x00000025 -#define EVENT_GPT2ACAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT2ACAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT2ACAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT2ACAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT2ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT2ACAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT2ACAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT2ACAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT2ACAPTSEL_EV_OSC_COMB 0x00000006 -#define EVENT_GPT2ACAPTSEL_EV_BATMON_COMB 0x00000005 -#define EVENT_GPT2ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT2ACAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT2ACAPTSEL_EV_W 7 +#define EVENT_GPT2ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT2ACAPTSEL_EV_S 0 +#define EVENT_GPT2ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT2ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT2ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT2ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT2ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_GPT2ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT2ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT2ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT2ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT2ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT2ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT2ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT2ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT2ACAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT2ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT2ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT2ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT2ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT2ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT2ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT2ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT2ACAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT2ACAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT2ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT2ACAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2104,53 +2104,53 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT2BCAPTSEL_EV_W 7 -#define EVENT_GPT2BCAPTSEL_EV_M 0x0000007F -#define EVENT_GPT2BCAPTSEL_EV_S 0 -#define EVENT_GPT2BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT2BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT2BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT2BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT2BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT5 0x0000005A -#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT4 0x00000059 -#define EVENT_GPT2BCAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT2BCAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT2BCAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT2BCAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT2BCAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT2BCAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT2BCAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT2BCAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_GPT2BCAPTSEL_EV_UART1_COMB 0x00000025 -#define EVENT_GPT2BCAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT2BCAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT2BCAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT2BCAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT2BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT2BCAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT2BCAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT2BCAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT2BCAPTSEL_EV_OSC_COMB 0x00000006 -#define EVENT_GPT2BCAPTSEL_EV_BATMON_COMB 0x00000005 -#define EVENT_GPT2BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT2BCAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT2BCAPTSEL_EV_W 7 +#define EVENT_GPT2BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT2BCAPTSEL_EV_S 0 +#define EVENT_GPT2BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT2BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT2BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT2BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT2BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_GPT2BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT2BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT2BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT2BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT2BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT2BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT2BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT2BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT2BCAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT2BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT2BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT2BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT2BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT2BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT2BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT2BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT2BCAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT2BCAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT2BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT2BCAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2163,10 +2163,10 @@ // ENUMs: // UART0_RX_DMASREQ UART0 RX DMA single request, controlled by // UART0:DMACTL.RXDMAE -#define EVENT_UDMACH1SSEL_EV_W 7 -#define EVENT_UDMACH1SSEL_EV_M 0x0000007F -#define EVENT_UDMACH1SSEL_EV_S 0 -#define EVENT_UDMACH1SSEL_EV_UART0_RX_DMASREQ 0x00000031 +#define EVENT_UDMACH1SSEL_EV_W 7 +#define EVENT_UDMACH1SSEL_EV_M 0x0000007F +#define EVENT_UDMACH1SSEL_EV_S 0 +#define EVENT_UDMACH1SSEL_EV_UART0_RX_DMASREQ 0x00000031 //***************************************************************************** // @@ -2179,10 +2179,10 @@ // ENUMs: // UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by // UART0:DMACTL.RXDMAE -#define EVENT_UDMACH1BSEL_EV_W 7 -#define EVENT_UDMACH1BSEL_EV_M 0x0000007F -#define EVENT_UDMACH1BSEL_EV_S 0 -#define EVENT_UDMACH1BSEL_EV_UART0_RX_DMABREQ 0x00000030 +#define EVENT_UDMACH1BSEL_EV_W 7 +#define EVENT_UDMACH1BSEL_EV_M 0x0000007F +#define EVENT_UDMACH1BSEL_EV_S 0 +#define EVENT_UDMACH1BSEL_EV_UART0_RX_DMABREQ 0x00000030 //***************************************************************************** // @@ -2195,10 +2195,10 @@ // ENUMs: // UART0_TX_DMASREQ UART0 TX DMA single request, controlled by // UART0:DMACTL.TXDMAE -#define EVENT_UDMACH2SSEL_EV_W 7 -#define EVENT_UDMACH2SSEL_EV_M 0x0000007F -#define EVENT_UDMACH2SSEL_EV_S 0 -#define EVENT_UDMACH2SSEL_EV_UART0_TX_DMASREQ 0x00000033 +#define EVENT_UDMACH2SSEL_EV_W 7 +#define EVENT_UDMACH2SSEL_EV_M 0x0000007F +#define EVENT_UDMACH2SSEL_EV_S 0 +#define EVENT_UDMACH2SSEL_EV_UART0_TX_DMASREQ 0x00000033 //***************************************************************************** // @@ -2211,10 +2211,10 @@ // ENUMs: // UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by // UART0:DMACTL.TXDMAE -#define EVENT_UDMACH2BSEL_EV_W 7 -#define EVENT_UDMACH2BSEL_EV_M 0x0000007F -#define EVENT_UDMACH2BSEL_EV_S 0 -#define EVENT_UDMACH2BSEL_EV_UART0_TX_DMABREQ 0x00000032 +#define EVENT_UDMACH2BSEL_EV_W 7 +#define EVENT_UDMACH2BSEL_EV_M 0x0000007F +#define EVENT_UDMACH2BSEL_EV_S 0 +#define EVENT_UDMACH2BSEL_EV_UART0_TX_DMABREQ 0x00000032 //***************************************************************************** // @@ -2227,10 +2227,10 @@ // ENUMs: // SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by // SSI0:DMACR.RXDMAE -#define EVENT_UDMACH3SSEL_EV_W 7 -#define EVENT_UDMACH3SSEL_EV_M 0x0000007F -#define EVENT_UDMACH3SSEL_EV_S 0 -#define EVENT_UDMACH3SSEL_EV_SSI0_RX_DMASREQ 0x00000029 +#define EVENT_UDMACH3SSEL_EV_W 7 +#define EVENT_UDMACH3SSEL_EV_M 0x0000007F +#define EVENT_UDMACH3SSEL_EV_S 0 +#define EVENT_UDMACH3SSEL_EV_SSI0_RX_DMASREQ 0x00000029 //***************************************************************************** // @@ -2243,10 +2243,10 @@ // ENUMs: // SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by // SSI0:DMACR.RXDMAE -#define EVENT_UDMACH3BSEL_EV_W 7 -#define EVENT_UDMACH3BSEL_EV_M 0x0000007F -#define EVENT_UDMACH3BSEL_EV_S 0 -#define EVENT_UDMACH3BSEL_EV_SSI0_RX_DMABREQ 0x00000028 +#define EVENT_UDMACH3BSEL_EV_W 7 +#define EVENT_UDMACH3BSEL_EV_M 0x0000007F +#define EVENT_UDMACH3BSEL_EV_S 0 +#define EVENT_UDMACH3BSEL_EV_SSI0_RX_DMABREQ 0x00000028 //***************************************************************************** // @@ -2259,10 +2259,10 @@ // ENUMs: // SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by // SSI0:DMACR.TXDMAE -#define EVENT_UDMACH4SSEL_EV_W 7 -#define EVENT_UDMACH4SSEL_EV_M 0x0000007F -#define EVENT_UDMACH4SSEL_EV_S 0 -#define EVENT_UDMACH4SSEL_EV_SSI0_TX_DMASREQ 0x0000002B +#define EVENT_UDMACH4SSEL_EV_W 7 +#define EVENT_UDMACH4SSEL_EV_M 0x0000007F +#define EVENT_UDMACH4SSEL_EV_S 0 +#define EVENT_UDMACH4SSEL_EV_SSI0_TX_DMASREQ 0x0000002B //***************************************************************************** // @@ -2275,10 +2275,10 @@ // ENUMs: // SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by // SSI0:DMACR.TXDMAE -#define EVENT_UDMACH4BSEL_EV_W 7 -#define EVENT_UDMACH4BSEL_EV_M 0x0000007F -#define EVENT_UDMACH4BSEL_EV_S 0 -#define EVENT_UDMACH4BSEL_EV_SSI0_TX_DMABREQ 0x0000002A +#define EVENT_UDMACH4BSEL_EV_W 7 +#define EVENT_UDMACH4BSEL_EV_M 0x0000007F +#define EVENT_UDMACH4BSEL_EV_S 0 +#define EVENT_UDMACH4BSEL_EV_SSI0_TX_DMABREQ 0x0000002A //***************************************************************************** // @@ -2291,10 +2291,10 @@ // ENUMs: // UART1_RX_DMASREQ UART1 RX DMA single request, controlled by // UART1:DMACTL.RXDMAE -#define EVENT_UDMACH5SSEL_EV_W 7 -#define EVENT_UDMACH5SSEL_EV_M 0x0000007F -#define EVENT_UDMACH5SSEL_EV_S 0 -#define EVENT_UDMACH5SSEL_EV_UART1_RX_DMASREQ 0x00000035 +#define EVENT_UDMACH5SSEL_EV_W 7 +#define EVENT_UDMACH5SSEL_EV_M 0x0000007F +#define EVENT_UDMACH5SSEL_EV_S 0 +#define EVENT_UDMACH5SSEL_EV_UART1_RX_DMASREQ 0x00000035 //***************************************************************************** // @@ -2307,10 +2307,10 @@ // ENUMs: // UART1_RX_DMABREQ UART1 RX DMA burst request, controlled by // UART1:DMACTL.RXDMAE -#define EVENT_UDMACH5BSEL_EV_W 7 -#define EVENT_UDMACH5BSEL_EV_M 0x0000007F -#define EVENT_UDMACH5BSEL_EV_S 0 -#define EVENT_UDMACH5BSEL_EV_UART1_RX_DMABREQ 0x00000034 +#define EVENT_UDMACH5BSEL_EV_W 7 +#define EVENT_UDMACH5BSEL_EV_M 0x0000007F +#define EVENT_UDMACH5BSEL_EV_S 0 +#define EVENT_UDMACH5BSEL_EV_UART1_RX_DMABREQ 0x00000034 //***************************************************************************** // @@ -2323,10 +2323,10 @@ // ENUMs: // UART1_TX_DMASREQ UART1 TX DMA single request, controlled by // UART1:DMACTL.TXDMAE -#define EVENT_UDMACH6SSEL_EV_W 7 -#define EVENT_UDMACH6SSEL_EV_M 0x0000007F -#define EVENT_UDMACH6SSEL_EV_S 0 -#define EVENT_UDMACH6SSEL_EV_UART1_TX_DMASREQ 0x00000037 +#define EVENT_UDMACH6SSEL_EV_W 7 +#define EVENT_UDMACH6SSEL_EV_M 0x0000007F +#define EVENT_UDMACH6SSEL_EV_S 0 +#define EVENT_UDMACH6SSEL_EV_UART1_TX_DMASREQ 0x00000037 //***************************************************************************** // @@ -2339,10 +2339,10 @@ // ENUMs: // UART1_TX_DMABREQ UART1 TX DMA burst request, controlled by // UART1:DMACTL.TXDMAE -#define EVENT_UDMACH6BSEL_EV_W 7 -#define EVENT_UDMACH6BSEL_EV_M 0x0000007F -#define EVENT_UDMACH6BSEL_EV_S 0 -#define EVENT_UDMACH6BSEL_EV_UART1_TX_DMABREQ 0x00000036 +#define EVENT_UDMACH6BSEL_EV_W 7 +#define EVENT_UDMACH6BSEL_EV_M 0x0000007F +#define EVENT_UDMACH6BSEL_EV_S 0 +#define EVENT_UDMACH6BSEL_EV_UART1_TX_DMABREQ 0x00000036 //***************************************************************************** // @@ -2355,10 +2355,10 @@ // ENUMs: // AUX_DMASREQ DMA single request event from AUX, configured by // AUX_EVCTL:DMACTL -#define EVENT_UDMACH7SSEL_EV_W 7 -#define EVENT_UDMACH7SSEL_EV_M 0x0000007F -#define EVENT_UDMACH7SSEL_EV_S 0 -#define EVENT_UDMACH7SSEL_EV_AUX_DMASREQ 0x00000075 +#define EVENT_UDMACH7SSEL_EV_W 7 +#define EVENT_UDMACH7SSEL_EV_M 0x0000007F +#define EVENT_UDMACH7SSEL_EV_S 0 +#define EVENT_UDMACH7SSEL_EV_AUX_DMASREQ 0x00000075 //***************************************************************************** // @@ -2371,10 +2371,10 @@ // ENUMs: // AUX_DMABREQ DMA burst request event from AUX, configured by // AUX_EVCTL:DMACTL -#define EVENT_UDMACH7BSEL_EV_W 7 -#define EVENT_UDMACH7BSEL_EV_M 0x0000007F -#define EVENT_UDMACH7BSEL_EV_S 0 -#define EVENT_UDMACH7BSEL_EV_AUX_DMABREQ 0x00000076 +#define EVENT_UDMACH7BSEL_EV_W 7 +#define EVENT_UDMACH7BSEL_EV_M 0x0000007F +#define EVENT_UDMACH7BSEL_EV_S 0 +#define EVENT_UDMACH7BSEL_EV_AUX_DMABREQ 0x00000076 //***************************************************************************** // @@ -2387,10 +2387,10 @@ // ENUMs: // AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by // AUX_EVCTL:DMASWREQ.START -#define EVENT_UDMACH8SSEL_EV_W 7 -#define EVENT_UDMACH8SSEL_EV_M 0x0000007F -#define EVENT_UDMACH8SSEL_EV_S 0 -#define EVENT_UDMACH8SSEL_EV_AUX_SW_DMABREQ 0x00000074 +#define EVENT_UDMACH8SSEL_EV_W 7 +#define EVENT_UDMACH8SSEL_EV_M 0x0000007F +#define EVENT_UDMACH8SSEL_EV_S 0 +#define EVENT_UDMACH8SSEL_EV_AUX_SW_DMABREQ 0x00000074 //***************************************************************************** // @@ -2403,10 +2403,10 @@ // ENUMs: // AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by // AUX_EVCTL:DMASWREQ.START -#define EVENT_UDMACH8BSEL_EV_W 7 -#define EVENT_UDMACH8BSEL_EV_M 0x0000007F -#define EVENT_UDMACH8BSEL_EV_S 0 -#define EVENT_UDMACH8BSEL_EV_AUX_SW_DMABREQ 0x00000074 +#define EVENT_UDMACH8BSEL_EV_W 7 +#define EVENT_UDMACH8BSEL_EV_M 0x0000007F +#define EVENT_UDMACH8BSEL_EV_S 0 +#define EVENT_UDMACH8BSEL_EV_AUX_SW_DMABREQ 0x00000074 //***************************************************************************** // @@ -2431,20 +2431,20 @@ // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // TIE_LOW Not used tied to 0 // NONE Always inactive -#define EVENT_UDMACH9SSEL_EV_W 7 -#define EVENT_UDMACH9SSEL_EV_M 0x0000007F -#define EVENT_UDMACH9SSEL_EV_S 0 -#define EVENT_UDMACH9SSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH9SSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH9SSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH9SSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH9SSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH9SSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH9SSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH9SSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH9SSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH9SSEL_EV_TIE_LOW 0x00000045 -#define EVENT_UDMACH9SSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH9SSEL_EV_W 7 +#define EVENT_UDMACH9SSEL_EV_M 0x0000007F +#define EVENT_UDMACH9SSEL_EV_S 0 +#define EVENT_UDMACH9SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH9SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH9SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH9SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH9SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH9SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH9SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH9SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH9SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH9SSEL_EV_TIE_LOW 0x00000045 +#define EVENT_UDMACH9SSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2468,19 +2468,19 @@ // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // NONE Always inactive -#define EVENT_UDMACH9BSEL_EV_W 7 -#define EVENT_UDMACH9BSEL_EV_M 0x0000007F -#define EVENT_UDMACH9BSEL_EV_S 0 -#define EVENT_UDMACH9BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH9BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH9BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH9BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH9BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH9BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH9BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH9BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH9BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH9BSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH9BSEL_EV_W 7 +#define EVENT_UDMACH9BSEL_EV_M 0x0000007F +#define EVENT_UDMACH9BSEL_EV_S 0 +#define EVENT_UDMACH9BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH9BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH9BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH9BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH9BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH9BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH9BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH9BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH9BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH9BSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2505,20 +2505,20 @@ // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // TIE_LOW Not used tied to 0 // NONE Always inactive -#define EVENT_UDMACH10SSEL_EV_W 7 -#define EVENT_UDMACH10SSEL_EV_M 0x0000007F -#define EVENT_UDMACH10SSEL_EV_S 0 -#define EVENT_UDMACH10SSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH10SSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH10SSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH10SSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH10SSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH10SSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH10SSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH10SSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH10SSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH10SSEL_EV_TIE_LOW 0x00000046 -#define EVENT_UDMACH10SSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH10SSEL_EV_W 7 +#define EVENT_UDMACH10SSEL_EV_M 0x0000007F +#define EVENT_UDMACH10SSEL_EV_S 0 +#define EVENT_UDMACH10SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH10SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH10SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH10SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH10SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH10SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH10SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH10SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH10SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH10SSEL_EV_TIE_LOW 0x00000046 +#define EVENT_UDMACH10SSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2542,19 +2542,19 @@ // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // NONE Always inactive -#define EVENT_UDMACH10BSEL_EV_W 7 -#define EVENT_UDMACH10BSEL_EV_M 0x0000007F -#define EVENT_UDMACH10BSEL_EV_S 0 -#define EVENT_UDMACH10BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH10BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH10BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH10BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH10BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH10BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH10BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH10BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH10BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH10BSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH10BSEL_EV_W 7 +#define EVENT_UDMACH10BSEL_EV_M 0x0000007F +#define EVENT_UDMACH10BSEL_EV_S 0 +#define EVENT_UDMACH10BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH10BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH10BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH10BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH10BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH10BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH10BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH10BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH10BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH10BSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2579,20 +2579,20 @@ // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // TIE_LOW Not used tied to 0 // NONE Always inactive -#define EVENT_UDMACH11SSEL_EV_W 7 -#define EVENT_UDMACH11SSEL_EV_M 0x0000007F -#define EVENT_UDMACH11SSEL_EV_S 0 -#define EVENT_UDMACH11SSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH11SSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH11SSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH11SSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH11SSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH11SSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH11SSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH11SSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH11SSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH11SSEL_EV_TIE_LOW 0x00000047 -#define EVENT_UDMACH11SSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH11SSEL_EV_W 7 +#define EVENT_UDMACH11SSEL_EV_M 0x0000007F +#define EVENT_UDMACH11SSEL_EV_S 0 +#define EVENT_UDMACH11SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH11SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH11SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH11SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH11SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH11SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH11SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH11SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH11SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH11SSEL_EV_TIE_LOW 0x00000047 +#define EVENT_UDMACH11SSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2616,19 +2616,19 @@ // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // NONE Always inactive -#define EVENT_UDMACH11BSEL_EV_W 7 -#define EVENT_UDMACH11BSEL_EV_M 0x0000007F -#define EVENT_UDMACH11BSEL_EV_S 0 -#define EVENT_UDMACH11BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH11BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH11BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH11BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH11BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH11BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH11BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH11BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH11BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH11BSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH11BSEL_EV_W 7 +#define EVENT_UDMACH11BSEL_EV_M 0x0000007F +#define EVENT_UDMACH11BSEL_EV_S 0 +#define EVENT_UDMACH11BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH11BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH11BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH11BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH11BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH11BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH11BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH11BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH11BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH11BSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2653,20 +2653,20 @@ // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // TIE_LOW Not used tied to 0 // NONE Always inactive -#define EVENT_UDMACH12SSEL_EV_W 7 -#define EVENT_UDMACH12SSEL_EV_M 0x0000007F -#define EVENT_UDMACH12SSEL_EV_S 0 -#define EVENT_UDMACH12SSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH12SSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH12SSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH12SSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH12SSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH12SSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH12SSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH12SSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH12SSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH12SSEL_EV_TIE_LOW 0x00000048 -#define EVENT_UDMACH12SSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH12SSEL_EV_W 7 +#define EVENT_UDMACH12SSEL_EV_M 0x0000007F +#define EVENT_UDMACH12SSEL_EV_S 0 +#define EVENT_UDMACH12SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH12SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH12SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH12SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH12SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH12SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH12SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH12SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH12SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH12SSEL_EV_TIE_LOW 0x00000048 +#define EVENT_UDMACH12SSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2690,19 +2690,19 @@ // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // NONE Always inactive -#define EVENT_UDMACH12BSEL_EV_W 7 -#define EVENT_UDMACH12BSEL_EV_M 0x0000007F -#define EVENT_UDMACH12BSEL_EV_S 0 -#define EVENT_UDMACH12BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH12BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH12BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH12BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH12BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH12BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH12BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH12BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH12BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH12BSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH12BSEL_EV_W 7 +#define EVENT_UDMACH12BSEL_EV_M 0x0000007F +#define EVENT_UDMACH12BSEL_EV_S 0 +#define EVENT_UDMACH12BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH12BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH12BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH12BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH12BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH12BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH12BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH12BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH12BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH12BSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2716,10 +2716,10 @@ // AON_PROG2 AON programmable event 2. Event selected by // AON_EVENT MCU event selector, // AON_EVENT:EVTOMCUSEL.AON_PROG2_EV -#define EVENT_UDMACH13BSEL_EV_W 7 -#define EVENT_UDMACH13BSEL_EV_M 0x0000007F -#define EVENT_UDMACH13BSEL_EV_S 0 -#define EVENT_UDMACH13BSEL_EV_AON_PROG2 0x00000003 +#define EVENT_UDMACH13BSEL_EV_W 7 +#define EVENT_UDMACH13BSEL_EV_M 0x0000007F +#define EVENT_UDMACH13BSEL_EV_S 0 +#define EVENT_UDMACH13BSEL_EV_AON_PROG2 0x00000003 //***************************************************************************** // @@ -2933,115 +2933,115 @@ // AON_EVENT MCU event selector, // AON_EVENT:EVTOMCUSEL.AON_PROG0_EV // NONE Always inactive -#define EVENT_UDMACH14BSEL_EV_W 7 -#define EVENT_UDMACH14BSEL_EV_M 0x0000007F -#define EVENT_UDMACH14BSEL_EV_S 0 -#define EVENT_UDMACH14BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH14BSEL_EV_CPU_HALTED 0x00000078 -#define EVENT_UDMACH14BSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_UDMACH14BSEL_EV_AUX_DMABREQ 0x00000076 -#define EVENT_UDMACH14BSEL_EV_AUX_DMASREQ 0x00000075 -#define EVENT_UDMACH14BSEL_EV_AUX_SW_DMABREQ 0x00000074 -#define EVENT_UDMACH14BSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_UDMACH14BSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_UDMACH14BSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_UDMACH14BSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_UDMACH14BSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_UDMACH14BSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_UDMACH14BSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_UDMACH14BSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_UDMACH14BSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_UDMACH14BSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_UDMACH14BSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_UDMACH14BSEL_EV_TRNG_IRQ 0x00000068 -#define EVENT_UDMACH14BSEL_EV_SWEV3 0x00000067 -#define EVENT_UDMACH14BSEL_EV_SWEV2 0x00000066 -#define EVENT_UDMACH14BSEL_EV_SWEV1 0x00000065 -#define EVENT_UDMACH14BSEL_EV_SWEV0 0x00000064 -#define EVENT_UDMACH14BSEL_EV_WDT_NMI 0x00000063 -#define EVENT_UDMACH14BSEL_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E -#define EVENT_UDMACH14BSEL_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT7 0x0000005C -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT6 0x0000005B -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT5 0x0000005A -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT4 0x00000059 -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT3 0x00000058 -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT2 0x00000057 -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT1 0x00000056 -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT0 0x00000055 -#define EVENT_UDMACH14BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH14BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH14BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH14BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH14BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH14BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH14BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH14BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH14BSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_UDMACH14BSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_UDMACH14BSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_UDMACH14BSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_UDMACH14BSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_UDMACH14BSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_UDMACH14BSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_UDMACH14BSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_UDMACH14BSEL_EV_UART1_TX_DMASREQ 0x00000037 -#define EVENT_UDMACH14BSEL_EV_UART1_TX_DMABREQ 0x00000036 -#define EVENT_UDMACH14BSEL_EV_UART1_RX_DMASREQ 0x00000035 -#define EVENT_UDMACH14BSEL_EV_UART1_RX_DMABREQ 0x00000034 -#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMASREQ 0x00000033 -#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMABREQ 0x00000032 -#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMASREQ 0x00000031 -#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMABREQ 0x00000030 -#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMASREQ 0x0000002F -#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMABREQ 0x0000002E -#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMASREQ 0x0000002D -#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMABREQ 0x0000002C -#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMASREQ 0x0000002B -#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMABREQ 0x0000002A -#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMASREQ 0x00000029 -#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMABREQ 0x00000028 -#define EVENT_UDMACH14BSEL_EV_DMA_DONE_COMB 0x00000027 -#define EVENT_UDMACH14BSEL_EV_DMA_ERR 0x00000026 -#define EVENT_UDMACH14BSEL_EV_UART1_COMB 0x00000025 -#define EVENT_UDMACH14BSEL_EV_UART0_COMB 0x00000024 -#define EVENT_UDMACH14BSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_UDMACH14BSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_UDMACH14BSEL_EV_PKA_IRQ 0x0000001F -#define EVENT_UDMACH14BSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_UDMACH14BSEL_EV_AUX_SWEV1 0x0000001D -#define EVENT_UDMACH14BSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_UDMACH14BSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_UDMACH14BSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_UDMACH14BSEL_EV_WDT_IRQ 0x00000018 -#define EVENT_UDMACH14BSEL_EV_DMA_CH18_DONE 0x00000016 -#define EVENT_UDMACH14BSEL_EV_FLASH 0x00000015 -#define EVENT_UDMACH14BSEL_EV_DMA_CH0_DONE 0x00000014 -#define EVENT_UDMACH14BSEL_EV_GPT1B 0x00000013 -#define EVENT_UDMACH14BSEL_EV_GPT1A 0x00000012 -#define EVENT_UDMACH14BSEL_EV_GPT0B 0x00000011 -#define EVENT_UDMACH14BSEL_EV_GPT0A 0x00000010 -#define EVENT_UDMACH14BSEL_EV_GPT3B 0x0000000F -#define EVENT_UDMACH14BSEL_EV_GPT3A 0x0000000E -#define EVENT_UDMACH14BSEL_EV_GPT2B 0x0000000D -#define EVENT_UDMACH14BSEL_EV_GPT2A 0x0000000C -#define EVENT_UDMACH14BSEL_EV_AUX_COMB 0x0000000B -#define EVENT_UDMACH14BSEL_EV_AON_AUX_SWEV0 0x0000000A -#define EVENT_UDMACH14BSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_UDMACH14BSEL_EV_I2S_IRQ 0x00000008 -#define EVENT_UDMACH14BSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_UDMACH14BSEL_EV_OSC_COMB 0x00000006 -#define EVENT_UDMACH14BSEL_EV_BATMON_COMB 0x00000005 -#define EVENT_UDMACH14BSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_UDMACH14BSEL_EV_AON_PROG2 0x00000003 -#define EVENT_UDMACH14BSEL_EV_AON_PROG1 0x00000002 -#define EVENT_UDMACH14BSEL_EV_AON_PROG0 0x00000001 -#define EVENT_UDMACH14BSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH14BSEL_EV_W 7 +#define EVENT_UDMACH14BSEL_EV_M 0x0000007F +#define EVENT_UDMACH14BSEL_EV_S 0 +#define EVENT_UDMACH14BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH14BSEL_EV_CPU_HALTED 0x00000078 +#define EVENT_UDMACH14BSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_UDMACH14BSEL_EV_AUX_DMABREQ 0x00000076 +#define EVENT_UDMACH14BSEL_EV_AUX_DMASREQ 0x00000075 +#define EVENT_UDMACH14BSEL_EV_AUX_SW_DMABREQ 0x00000074 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_UDMACH14BSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_UDMACH14BSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_UDMACH14BSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_UDMACH14BSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_UDMACH14BSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_UDMACH14BSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_UDMACH14BSEL_EV_TRNG_IRQ 0x00000068 +#define EVENT_UDMACH14BSEL_EV_SWEV3 0x00000067 +#define EVENT_UDMACH14BSEL_EV_SWEV2 0x00000066 +#define EVENT_UDMACH14BSEL_EV_SWEV1 0x00000065 +#define EVENT_UDMACH14BSEL_EV_SWEV0 0x00000064 +#define EVENT_UDMACH14BSEL_EV_WDT_NMI 0x00000063 +#define EVENT_UDMACH14BSEL_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E +#define EVENT_UDMACH14BSEL_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_UDMACH14BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH14BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH14BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH14BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH14BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH14BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH14BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH14BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH14BSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_UDMACH14BSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_UDMACH14BSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_UDMACH14BSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_UDMACH14BSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_UDMACH14BSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_UDMACH14BSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_UDMACH14BSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_UDMACH14BSEL_EV_UART1_TX_DMASREQ 0x00000037 +#define EVENT_UDMACH14BSEL_EV_UART1_TX_DMABREQ 0x00000036 +#define EVENT_UDMACH14BSEL_EV_UART1_RX_DMASREQ 0x00000035 +#define EVENT_UDMACH14BSEL_EV_UART1_RX_DMABREQ 0x00000034 +#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMASREQ 0x00000033 +#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMABREQ 0x00000032 +#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMASREQ 0x00000031 +#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMABREQ 0x00000030 +#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMASREQ 0x0000002F +#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMABREQ 0x0000002E +#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMASREQ 0x0000002D +#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMABREQ 0x0000002C +#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMASREQ 0x0000002B +#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMABREQ 0x0000002A +#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMASREQ 0x00000029 +#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMABREQ 0x00000028 +#define EVENT_UDMACH14BSEL_EV_DMA_DONE_COMB 0x00000027 +#define EVENT_UDMACH14BSEL_EV_DMA_ERR 0x00000026 +#define EVENT_UDMACH14BSEL_EV_UART1_COMB 0x00000025 +#define EVENT_UDMACH14BSEL_EV_UART0_COMB 0x00000024 +#define EVENT_UDMACH14BSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_UDMACH14BSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_UDMACH14BSEL_EV_PKA_IRQ 0x0000001F +#define EVENT_UDMACH14BSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_UDMACH14BSEL_EV_AUX_SWEV1 0x0000001D +#define EVENT_UDMACH14BSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_UDMACH14BSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_UDMACH14BSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_UDMACH14BSEL_EV_WDT_IRQ 0x00000018 +#define EVENT_UDMACH14BSEL_EV_DMA_CH18_DONE 0x00000016 +#define EVENT_UDMACH14BSEL_EV_FLASH 0x00000015 +#define EVENT_UDMACH14BSEL_EV_DMA_CH0_DONE 0x00000014 +#define EVENT_UDMACH14BSEL_EV_GPT1B 0x00000013 +#define EVENT_UDMACH14BSEL_EV_GPT1A 0x00000012 +#define EVENT_UDMACH14BSEL_EV_GPT0B 0x00000011 +#define EVENT_UDMACH14BSEL_EV_GPT0A 0x00000010 +#define EVENT_UDMACH14BSEL_EV_GPT3B 0x0000000F +#define EVENT_UDMACH14BSEL_EV_GPT3A 0x0000000E +#define EVENT_UDMACH14BSEL_EV_GPT2B 0x0000000D +#define EVENT_UDMACH14BSEL_EV_GPT2A 0x0000000C +#define EVENT_UDMACH14BSEL_EV_AUX_COMB 0x0000000B +#define EVENT_UDMACH14BSEL_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_UDMACH14BSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_UDMACH14BSEL_EV_I2S_IRQ 0x00000008 +#define EVENT_UDMACH14BSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_UDMACH14BSEL_EV_OSC_COMB 0x00000006 +#define EVENT_UDMACH14BSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_UDMACH14BSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_UDMACH14BSEL_EV_AON_PROG2 0x00000003 +#define EVENT_UDMACH14BSEL_EV_AON_PROG1 0x00000002 +#define EVENT_UDMACH14BSEL_EV_AON_PROG0 0x00000001 +#define EVENT_UDMACH14BSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -3054,10 +3054,10 @@ // ENUMs: // AON_RTC_COMB Event from AON_RTC, controlled by the // AON_RTC:CTL.COMB_EV_MASK setting -#define EVENT_UDMACH15BSEL_EV_W 7 -#define EVENT_UDMACH15BSEL_EV_M 0x0000007F -#define EVENT_UDMACH15BSEL_EV_S 0 -#define EVENT_UDMACH15BSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_UDMACH15BSEL_EV_W 7 +#define EVENT_UDMACH15BSEL_EV_M 0x0000007F +#define EVENT_UDMACH15BSEL_EV_S 0 +#define EVENT_UDMACH15BSEL_EV_AON_RTC_COMB 0x00000007 //***************************************************************************** // @@ -3070,10 +3070,10 @@ // ENUMs: // SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by // SSI0:DMACR.RXDMAE -#define EVENT_UDMACH16SSEL_EV_W 7 -#define EVENT_UDMACH16SSEL_EV_M 0x0000007F -#define EVENT_UDMACH16SSEL_EV_S 0 -#define EVENT_UDMACH16SSEL_EV_SSI1_RX_DMASREQ 0x0000002D +#define EVENT_UDMACH16SSEL_EV_W 7 +#define EVENT_UDMACH16SSEL_EV_M 0x0000007F +#define EVENT_UDMACH16SSEL_EV_S 0 +#define EVENT_UDMACH16SSEL_EV_SSI1_RX_DMASREQ 0x0000002D //***************************************************************************** // @@ -3086,10 +3086,10 @@ // ENUMs: // SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by // SSI0:DMACR.RXDMAE -#define EVENT_UDMACH16BSEL_EV_W 7 -#define EVENT_UDMACH16BSEL_EV_M 0x0000007F -#define EVENT_UDMACH16BSEL_EV_S 0 -#define EVENT_UDMACH16BSEL_EV_SSI1_RX_DMABREQ 0x0000002C +#define EVENT_UDMACH16BSEL_EV_W 7 +#define EVENT_UDMACH16BSEL_EV_M 0x0000007F +#define EVENT_UDMACH16BSEL_EV_S 0 +#define EVENT_UDMACH16BSEL_EV_SSI1_RX_DMABREQ 0x0000002C //***************************************************************************** // @@ -3102,10 +3102,10 @@ // ENUMs: // SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by // SSI0:DMACR.TXDMAE -#define EVENT_UDMACH17SSEL_EV_W 7 -#define EVENT_UDMACH17SSEL_EV_M 0x0000007F -#define EVENT_UDMACH17SSEL_EV_S 0 -#define EVENT_UDMACH17SSEL_EV_SSI1_TX_DMASREQ 0x0000002F +#define EVENT_UDMACH17SSEL_EV_W 7 +#define EVENT_UDMACH17SSEL_EV_M 0x0000007F +#define EVENT_UDMACH17SSEL_EV_S 0 +#define EVENT_UDMACH17SSEL_EV_SSI1_TX_DMASREQ 0x0000002F //***************************************************************************** // @@ -3118,10 +3118,10 @@ // ENUMs: // SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by // SSI0:DMACR.TXDMAE -#define EVENT_UDMACH17BSEL_EV_W 7 -#define EVENT_UDMACH17BSEL_EV_M 0x0000007F -#define EVENT_UDMACH17BSEL_EV_S 0 -#define EVENT_UDMACH17BSEL_EV_SSI1_TX_DMABREQ 0x0000002E +#define EVENT_UDMACH17BSEL_EV_W 7 +#define EVENT_UDMACH17BSEL_EV_M 0x0000007F +#define EVENT_UDMACH17BSEL_EV_S 0 +#define EVENT_UDMACH17BSEL_EV_SSI1_TX_DMABREQ 0x0000002E //***************************************************************************** // @@ -3133,10 +3133,10 @@ // Read only selection value // ENUMs: // SWEV0 Software event 0, triggered by SWEV.SWEV0 -#define EVENT_UDMACH21SSEL_EV_W 7 -#define EVENT_UDMACH21SSEL_EV_M 0x0000007F -#define EVENT_UDMACH21SSEL_EV_S 0 -#define EVENT_UDMACH21SSEL_EV_SWEV0 0x00000064 +#define EVENT_UDMACH21SSEL_EV_W 7 +#define EVENT_UDMACH21SSEL_EV_M 0x0000007F +#define EVENT_UDMACH21SSEL_EV_S 0 +#define EVENT_UDMACH21SSEL_EV_SWEV0 0x00000064 //***************************************************************************** // @@ -3148,10 +3148,10 @@ // Read only selection value // ENUMs: // SWEV0 Software event 0, triggered by SWEV.SWEV0 -#define EVENT_UDMACH21BSEL_EV_W 7 -#define EVENT_UDMACH21BSEL_EV_M 0x0000007F -#define EVENT_UDMACH21BSEL_EV_S 0 -#define EVENT_UDMACH21BSEL_EV_SWEV0 0x00000064 +#define EVENT_UDMACH21BSEL_EV_W 7 +#define EVENT_UDMACH21BSEL_EV_M 0x0000007F +#define EVENT_UDMACH21BSEL_EV_S 0 +#define EVENT_UDMACH21BSEL_EV_SWEV0 0x00000064 //***************************************************************************** // @@ -3163,10 +3163,10 @@ // Read only selection value // ENUMs: // SWEV1 Software event 1, triggered by SWEV.SWEV1 -#define EVENT_UDMACH22SSEL_EV_W 7 -#define EVENT_UDMACH22SSEL_EV_M 0x0000007F -#define EVENT_UDMACH22SSEL_EV_S 0 -#define EVENT_UDMACH22SSEL_EV_SWEV1 0x00000065 +#define EVENT_UDMACH22SSEL_EV_W 7 +#define EVENT_UDMACH22SSEL_EV_M 0x0000007F +#define EVENT_UDMACH22SSEL_EV_S 0 +#define EVENT_UDMACH22SSEL_EV_SWEV1 0x00000065 //***************************************************************************** // @@ -3178,10 +3178,10 @@ // Read only selection value // ENUMs: // SWEV1 Software event 1, triggered by SWEV.SWEV1 -#define EVENT_UDMACH22BSEL_EV_W 7 -#define EVENT_UDMACH22BSEL_EV_M 0x0000007F -#define EVENT_UDMACH22BSEL_EV_S 0 -#define EVENT_UDMACH22BSEL_EV_SWEV1 0x00000065 +#define EVENT_UDMACH22BSEL_EV_W 7 +#define EVENT_UDMACH22BSEL_EV_M 0x0000007F +#define EVENT_UDMACH22BSEL_EV_S 0 +#define EVENT_UDMACH22BSEL_EV_SWEV1 0x00000065 //***************************************************************************** // @@ -3193,10 +3193,10 @@ // Read only selection value // ENUMs: // SWEV2 Software event 2, triggered by SWEV.SWEV2 -#define EVENT_UDMACH23SSEL_EV_W 7 -#define EVENT_UDMACH23SSEL_EV_M 0x0000007F -#define EVENT_UDMACH23SSEL_EV_S 0 -#define EVENT_UDMACH23SSEL_EV_SWEV2 0x00000066 +#define EVENT_UDMACH23SSEL_EV_W 7 +#define EVENT_UDMACH23SSEL_EV_M 0x0000007F +#define EVENT_UDMACH23SSEL_EV_S 0 +#define EVENT_UDMACH23SSEL_EV_SWEV2 0x00000066 //***************************************************************************** // @@ -3208,10 +3208,10 @@ // Read only selection value // ENUMs: // SWEV2 Software event 2, triggered by SWEV.SWEV2 -#define EVENT_UDMACH23BSEL_EV_W 7 -#define EVENT_UDMACH23BSEL_EV_M 0x0000007F -#define EVENT_UDMACH23BSEL_EV_S 0 -#define EVENT_UDMACH23BSEL_EV_SWEV2 0x00000066 +#define EVENT_UDMACH23BSEL_EV_W 7 +#define EVENT_UDMACH23BSEL_EV_M 0x0000007F +#define EVENT_UDMACH23BSEL_EV_S 0 +#define EVENT_UDMACH23BSEL_EV_SWEV2 0x00000066 //***************************************************************************** // @@ -3223,10 +3223,10 @@ // Read only selection value // ENUMs: // SWEV3 Software event 3, triggered by SWEV.SWEV3 -#define EVENT_UDMACH24SSEL_EV_W 7 -#define EVENT_UDMACH24SSEL_EV_M 0x0000007F -#define EVENT_UDMACH24SSEL_EV_S 0 -#define EVENT_UDMACH24SSEL_EV_SWEV3 0x00000067 +#define EVENT_UDMACH24SSEL_EV_W 7 +#define EVENT_UDMACH24SSEL_EV_M 0x0000007F +#define EVENT_UDMACH24SSEL_EV_S 0 +#define EVENT_UDMACH24SSEL_EV_SWEV3 0x00000067 //***************************************************************************** // @@ -3238,10 +3238,10 @@ // Read only selection value // ENUMs: // SWEV3 Software event 3, triggered by SWEV.SWEV3 -#define EVENT_UDMACH24BSEL_EV_W 7 -#define EVENT_UDMACH24BSEL_EV_M 0x0000007F -#define EVENT_UDMACH24BSEL_EV_S 0 -#define EVENT_UDMACH24BSEL_EV_SWEV3 0x00000067 +#define EVENT_UDMACH24BSEL_EV_W 7 +#define EVENT_UDMACH24BSEL_EV_M 0x0000007F +#define EVENT_UDMACH24BSEL_EV_S 0 +#define EVENT_UDMACH24BSEL_EV_SWEV3 0x00000067 //***************************************************************************** // @@ -3342,53 +3342,53 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT3ACAPTSEL_EV_W 7 -#define EVENT_GPT3ACAPTSEL_EV_M 0x0000007F -#define EVENT_GPT3ACAPTSEL_EV_S 0 -#define EVENT_GPT3ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT3ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT3ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT3ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT3ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT7 0x0000005C -#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT6 0x0000005B -#define EVENT_GPT3ACAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT3ACAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT3ACAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT3ACAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT3ACAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT3ACAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT3ACAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT3ACAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_GPT3ACAPTSEL_EV_UART1_COMB 0x00000025 -#define EVENT_GPT3ACAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT3ACAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT3ACAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT3ACAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT3ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT3ACAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT3ACAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT3ACAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT3ACAPTSEL_EV_OSC_COMB 0x00000006 -#define EVENT_GPT3ACAPTSEL_EV_BATMON_COMB 0x00000005 -#define EVENT_GPT3ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT3ACAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT3ACAPTSEL_EV_W 7 +#define EVENT_GPT3ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT3ACAPTSEL_EV_S 0 +#define EVENT_GPT3ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT3ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT3ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT3ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT3ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_GPT3ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT3ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT3ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT3ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT3ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT3ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT3ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT3ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT3ACAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT3ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT3ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT3ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT3ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT3ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT3ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT3ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT3ACAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT3ACAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT3ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT3ACAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -3489,53 +3489,53 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT3BCAPTSEL_EV_W 7 -#define EVENT_GPT3BCAPTSEL_EV_M 0x0000007F -#define EVENT_GPT3BCAPTSEL_EV_S 0 -#define EVENT_GPT3BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT3BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT3BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT3BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT3BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT7 0x0000005C -#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT6 0x0000005B -#define EVENT_GPT3BCAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT3BCAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT3BCAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT3BCAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT3BCAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT3BCAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT3BCAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT3BCAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_GPT3BCAPTSEL_EV_UART1_COMB 0x00000025 -#define EVENT_GPT3BCAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT3BCAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT3BCAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT3BCAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT3BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT3BCAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT3BCAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT3BCAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT3BCAPTSEL_EV_OSC_COMB 0x00000006 -#define EVENT_GPT3BCAPTSEL_EV_BATMON_COMB 0x00000005 -#define EVENT_GPT3BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT3BCAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT3BCAPTSEL_EV_W 7 +#define EVENT_GPT3BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT3BCAPTSEL_EV_S 0 +#define EVENT_GPT3BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT3BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT3BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT3BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT3BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_GPT3BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT3BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT3BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT3BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT3BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT3BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT3BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT3BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 +#define EVENT_GPT3BCAPTSEL_EV_UART1_COMB 0x00000025 +#define EVENT_GPT3BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT3BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT3BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT3BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT3BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT3BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT3BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT3BCAPTSEL_EV_OSC_COMB 0x00000006 +#define EVENT_GPT3BCAPTSEL_EV_BATMON_COMB 0x00000005 +#define EVENT_GPT3BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT3BCAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -3567,27 +3567,27 @@ // GPT2B GPT2B interrupt event, controlled by GPT2:TBMR // GPT2A GPT2A interrupt event, controlled by GPT2:TAMR // NONE Always inactive -#define EVENT_AUXSEL0_EV_W 7 -#define EVENT_AUXSEL0_EV_M 0x0000007F -#define EVENT_AUXSEL0_EV_S 0 -#define EVENT_AUXSEL0_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_AUXSEL0_EV_GPT3B_CMP 0x00000044 -#define EVENT_AUXSEL0_EV_GPT3A_CMP 0x00000043 -#define EVENT_AUXSEL0_EV_GPT2B_CMP 0x00000042 -#define EVENT_AUXSEL0_EV_GPT2A_CMP 0x00000041 -#define EVENT_AUXSEL0_EV_GPT1B_CMP 0x00000040 -#define EVENT_AUXSEL0_EV_GPT1A_CMP 0x0000003F -#define EVENT_AUXSEL0_EV_GPT0B_CMP 0x0000003E -#define EVENT_AUXSEL0_EV_GPT0A_CMP 0x0000003D -#define EVENT_AUXSEL0_EV_GPT1B 0x00000013 -#define EVENT_AUXSEL0_EV_GPT1A 0x00000012 -#define EVENT_AUXSEL0_EV_GPT0B 0x00000011 -#define EVENT_AUXSEL0_EV_GPT0A 0x00000010 -#define EVENT_AUXSEL0_EV_GPT3B 0x0000000F -#define EVENT_AUXSEL0_EV_GPT3A 0x0000000E -#define EVENT_AUXSEL0_EV_GPT2B 0x0000000D -#define EVENT_AUXSEL0_EV_GPT2A 0x0000000C -#define EVENT_AUXSEL0_EV_NONE 0x00000000 +#define EVENT_AUXSEL0_EV_W 7 +#define EVENT_AUXSEL0_EV_M 0x0000007F +#define EVENT_AUXSEL0_EV_S 0 +#define EVENT_AUXSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_AUXSEL0_EV_GPT3B_CMP 0x00000044 +#define EVENT_AUXSEL0_EV_GPT3A_CMP 0x00000043 +#define EVENT_AUXSEL0_EV_GPT2B_CMP 0x00000042 +#define EVENT_AUXSEL0_EV_GPT2A_CMP 0x00000041 +#define EVENT_AUXSEL0_EV_GPT1B_CMP 0x00000040 +#define EVENT_AUXSEL0_EV_GPT1A_CMP 0x0000003F +#define EVENT_AUXSEL0_EV_GPT0B_CMP 0x0000003E +#define EVENT_AUXSEL0_EV_GPT0A_CMP 0x0000003D +#define EVENT_AUXSEL0_EV_GPT1B 0x00000013 +#define EVENT_AUXSEL0_EV_GPT1A 0x00000012 +#define EVENT_AUXSEL0_EV_GPT0B 0x00000011 +#define EVENT_AUXSEL0_EV_GPT0A 0x00000010 +#define EVENT_AUXSEL0_EV_GPT3B 0x0000000F +#define EVENT_AUXSEL0_EV_GPT3A 0x0000000E +#define EVENT_AUXSEL0_EV_GPT2B 0x0000000D +#define EVENT_AUXSEL0_EV_GPT2A 0x0000000C +#define EVENT_AUXSEL0_EV_NONE 0x00000000 //***************************************************************************** // @@ -3600,10 +3600,10 @@ // ENUMs: // WDT_NMI Watchdog non maskable interrupt event, controlled // by WDT:CTL.INTTYPE -#define EVENT_CM3NMISEL0_EV_W 7 -#define EVENT_CM3NMISEL0_EV_M 0x0000007F -#define EVENT_CM3NMISEL0_EV_S 0 -#define EVENT_CM3NMISEL0_EV_WDT_NMI 0x00000063 +#define EVENT_CM3NMISEL0_EV_W 7 +#define EVENT_CM3NMISEL0_EV_M 0x0000007F +#define EVENT_CM3NMISEL0_EV_S 0 +#define EVENT_CM3NMISEL0_EV_WDT_NMI 0x00000063 //***************************************************************************** // @@ -3619,11 +3619,11 @@ // ENUMs: // ALWAYS_ACTIVE Always asserted // NONE Always inactive -#define EVENT_I2SSTMPSEL0_EV_W 7 -#define EVENT_I2SSTMPSEL0_EV_M 0x0000007F -#define EVENT_I2SSTMPSEL0_EV_S 0 -#define EVENT_I2SSTMPSEL0_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_I2SSTMPSEL0_EV_NONE 0x00000000 +#define EVENT_I2SSTMPSEL0_EV_W 7 +#define EVENT_I2SSTMPSEL0_EV_M 0x0000007F +#define EVENT_I2SSTMPSEL0_EV_S 0 +#define EVENT_I2SSTMPSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_I2SSTMPSEL0_EV_NONE 0x00000000 //***************************************************************************** // @@ -3640,12 +3640,12 @@ // ALWAYS_ACTIVE Always asserted // CPU_HALTED CPU halted // NONE Always inactive -#define EVENT_FRZSEL0_EV_W 7 -#define EVENT_FRZSEL0_EV_M 0x0000007F -#define EVENT_FRZSEL0_EV_S 0 -#define EVENT_FRZSEL0_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_FRZSEL0_EV_CPU_HALTED 0x00000078 -#define EVENT_FRZSEL0_EV_NONE 0x00000000 +#define EVENT_FRZSEL0_EV_W 7 +#define EVENT_FRZSEL0_EV_M 0x0000007F +#define EVENT_FRZSEL0_EV_S 0 +#define EVENT_FRZSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_FRZSEL0_EV_CPU_HALTED 0x00000078 +#define EVENT_FRZSEL0_EV_NONE 0x00000000 //***************************************************************************** // @@ -3655,34 +3655,33 @@ // Field: [24] SWEV3 // // Writing "1" to this bit when the value is "0" triggers the Software 3 event. -#define EVENT_SWEV_SWEV3 0x01000000 -#define EVENT_SWEV_SWEV3_BITN 24 -#define EVENT_SWEV_SWEV3_M 0x01000000 -#define EVENT_SWEV_SWEV3_S 24 +#define EVENT_SWEV_SWEV3 0x01000000 +#define EVENT_SWEV_SWEV3_BITN 24 +#define EVENT_SWEV_SWEV3_M 0x01000000 +#define EVENT_SWEV_SWEV3_S 24 // Field: [16] SWEV2 // // Writing "1" to this bit when the value is "0" triggers the Software 2 event. -#define EVENT_SWEV_SWEV2 0x00010000 -#define EVENT_SWEV_SWEV2_BITN 16 -#define EVENT_SWEV_SWEV2_M 0x00010000 -#define EVENT_SWEV_SWEV2_S 16 +#define EVENT_SWEV_SWEV2 0x00010000 +#define EVENT_SWEV_SWEV2_BITN 16 +#define EVENT_SWEV_SWEV2_M 0x00010000 +#define EVENT_SWEV_SWEV2_S 16 // Field: [8] SWEV1 // // Writing "1" to this bit when the value is "0" triggers the Software 1 event. -#define EVENT_SWEV_SWEV1 0x00000100 -#define EVENT_SWEV_SWEV1_BITN 8 -#define EVENT_SWEV_SWEV1_M 0x00000100 -#define EVENT_SWEV_SWEV1_S 8 +#define EVENT_SWEV_SWEV1 0x00000100 +#define EVENT_SWEV_SWEV1_BITN 8 +#define EVENT_SWEV_SWEV1_M 0x00000100 +#define EVENT_SWEV_SWEV1_S 8 // Field: [0] SWEV0 // // Writing "1" to this bit when the value is "0" triggers the Software 0 event. -#define EVENT_SWEV_SWEV0 0x00000001 -#define EVENT_SWEV_SWEV0_BITN 0 -#define EVENT_SWEV_SWEV0_M 0x00000001 -#define EVENT_SWEV_SWEV0_S 0 - +#define EVENT_SWEV_SWEV0 0x00000001 +#define EVENT_SWEV_SWEV0_BITN 0 +#define EVENT_SWEV_SWEV0_M 0x00000001 +#define EVENT_SWEV_SWEV0_S 0 #endif // __EVENT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_fcfg1.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_fcfg1.h index 9abcaa1..71b9320 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_fcfg1.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_fcfg1.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_fcfg1_h -* Revised: 2018-11-06 14:08:24 +0100 (Tue, 06 Nov 2018) -* Revision: 53237 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_fcfg1_h + * Revised: 2018-11-06 14:08:24 +0100 (Tue, 06 Nov 2018) + * Revision: 53237 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_FCFG1_H__ #define __HW_FCFG1_H__ @@ -44,241 +44,241 @@ // //***************************************************************************** // Misc configurations -#define FCFG1_O_MISC_CONF_1 0x000000A0 +#define FCFG1_O_MISC_CONF_1 0x000000A0 // Internal -#define FCFG1_O_MISC_CONF_2 0x000000A4 +#define FCFG1_O_MISC_CONF_2 0x000000A4 // Internal -#define FCFG1_O_HPOSC_MEAS_5 0x000000B0 +#define FCFG1_O_HPOSC_MEAS_5 0x000000B0 // Internal -#define FCFG1_O_HPOSC_MEAS_4 0x000000B4 +#define FCFG1_O_HPOSC_MEAS_4 0x000000B4 // Internal -#define FCFG1_O_HPOSC_MEAS_3 0x000000B8 +#define FCFG1_O_HPOSC_MEAS_3 0x000000B8 // Internal -#define FCFG1_O_HPOSC_MEAS_2 0x000000BC +#define FCFG1_O_HPOSC_MEAS_2 0x000000BC // Internal -#define FCFG1_O_HPOSC_MEAS_1 0x000000C0 +#define FCFG1_O_HPOSC_MEAS_1 0x000000C0 // Internal -#define FCFG1_O_CONFIG_CC26_FE 0x000000C4 +#define FCFG1_O_CONFIG_CC26_FE 0x000000C4 // Internal -#define FCFG1_O_CONFIG_CC13_FE 0x000000C8 +#define FCFG1_O_CONFIG_CC13_FE 0x000000C8 // Internal -#define FCFG1_O_CONFIG_RF_COMMON 0x000000CC +#define FCFG1_O_CONFIG_RF_COMMON 0x000000CC // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV2_CC26_2G4 0x000000D0 +#define FCFG1_O_CONFIG_SYNTH_DIV2_CC26_2G4 0x000000D0 // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV2_CC13_2G4 0x000000D4 +#define FCFG1_O_CONFIG_SYNTH_DIV2_CC13_2G4 0x000000D4 // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV2_CC26_1G 0x000000D8 +#define FCFG1_O_CONFIG_SYNTH_DIV2_CC26_1G 0x000000D8 // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV2_CC13_1G 0x000000DC +#define FCFG1_O_CONFIG_SYNTH_DIV2_CC13_1G 0x000000DC // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV4_CC26 0x000000E0 +#define FCFG1_O_CONFIG_SYNTH_DIV4_CC26 0x000000E0 // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV4_CC13 0x000000E4 +#define FCFG1_O_CONFIG_SYNTH_DIV4_CC13 0x000000E4 // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV5 0x000000E8 +#define FCFG1_O_CONFIG_SYNTH_DIV5 0x000000E8 // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV6_CC26 0x000000EC +#define FCFG1_O_CONFIG_SYNTH_DIV6_CC26 0x000000EC // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV6_CC13 0x000000F0 +#define FCFG1_O_CONFIG_SYNTH_DIV6_CC13 0x000000F0 // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV10 0x000000F4 +#define FCFG1_O_CONFIG_SYNTH_DIV10 0x000000F4 // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV12_CC26 0x000000F8 +#define FCFG1_O_CONFIG_SYNTH_DIV12_CC26 0x000000F8 // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV12_CC13 0x000000FC +#define FCFG1_O_CONFIG_SYNTH_DIV12_CC13 0x000000FC // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV15 0x00000100 +#define FCFG1_O_CONFIG_SYNTH_DIV15 0x00000100 // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV30 0x00000104 +#define FCFG1_O_CONFIG_SYNTH_DIV30 0x00000104 // Flash information -#define FCFG1_O_FLASH_NUMBER 0x00000164 +#define FCFG1_O_FLASH_NUMBER 0x00000164 // Flash information -#define FCFG1_O_FLASH_COORDINATE 0x0000016C +#define FCFG1_O_FLASH_COORDINATE 0x0000016C // Internal -#define FCFG1_O_FLASH_E_P 0x00000170 +#define FCFG1_O_FLASH_E_P 0x00000170 // Internal -#define FCFG1_O_FLASH_C_E_P_R 0x00000174 +#define FCFG1_O_FLASH_C_E_P_R 0x00000174 // Internal -#define FCFG1_O_FLASH_P_R_PV 0x00000178 +#define FCFG1_O_FLASH_P_R_PV 0x00000178 // Internal -#define FCFG1_O_FLASH_EH_SEQ 0x0000017C +#define FCFG1_O_FLASH_EH_SEQ 0x0000017C // Internal -#define FCFG1_O_FLASH_VHV_E 0x00000180 +#define FCFG1_O_FLASH_VHV_E 0x00000180 // Internal -#define FCFG1_O_FLASH_PP 0x00000184 +#define FCFG1_O_FLASH_PP 0x00000184 // Internal -#define FCFG1_O_FLASH_PROG_EP 0x00000188 +#define FCFG1_O_FLASH_PROG_EP 0x00000188 // Internal -#define FCFG1_O_FLASH_ERA_PW 0x0000018C +#define FCFG1_O_FLASH_ERA_PW 0x0000018C // Internal -#define FCFG1_O_FLASH_VHV 0x00000190 +#define FCFG1_O_FLASH_VHV 0x00000190 // Internal -#define FCFG1_O_FLASH_VHV_PV 0x00000194 +#define FCFG1_O_FLASH_VHV_PV 0x00000194 // Internal -#define FCFG1_O_FLASH_V 0x00000198 +#define FCFG1_O_FLASH_V 0x00000198 // User Identification. -#define FCFG1_O_USER_ID 0x00000294 +#define FCFG1_O_USER_ID 0x00000294 // Internal -#define FCFG1_O_FLASH_OTP_DATA3 0x000002B0 +#define FCFG1_O_FLASH_OTP_DATA3 0x000002B0 // Internal -#define FCFG1_O_ANA2_TRIM 0x000002B4 +#define FCFG1_O_ANA2_TRIM 0x000002B4 // Internal -#define FCFG1_O_LDO_TRIM 0x000002B8 +#define FCFG1_O_LDO_TRIM 0x000002B8 // MAC BLE Address 0 -#define FCFG1_O_MAC_BLE_0 0x000002E8 +#define FCFG1_O_MAC_BLE_0 0x000002E8 // MAC BLE Address 1 -#define FCFG1_O_MAC_BLE_1 0x000002EC +#define FCFG1_O_MAC_BLE_1 0x000002EC // MAC IEEE 802.15.4 Address 0 -#define FCFG1_O_MAC_15_4_0 0x000002F0 +#define FCFG1_O_MAC_15_4_0 0x000002F0 // MAC IEEE 802.15.4 Address 1 -#define FCFG1_O_MAC_15_4_1 0x000002F4 +#define FCFG1_O_MAC_15_4_1 0x000002F4 // Internal -#define FCFG1_O_FLASH_OTP_DATA4 0x00000308 +#define FCFG1_O_FLASH_OTP_DATA4 0x00000308 // Miscellaneous Trim Parameters -#define FCFG1_O_MISC_TRIM 0x0000030C +#define FCFG1_O_MISC_TRIM 0x0000030C // Internal -#define FCFG1_O_RCOSC_HF_TEMPCOMP 0x00000310 +#define FCFG1_O_RCOSC_HF_TEMPCOMP 0x00000310 // IcePick Device Identification -#define FCFG1_O_ICEPICK_DEVICE_ID 0x00000318 +#define FCFG1_O_ICEPICK_DEVICE_ID 0x00000318 // Factory Configuration (FCFG1) Revision -#define FCFG1_O_FCFG1_REVISION 0x0000031C +#define FCFG1_O_FCFG1_REVISION 0x0000031C // Misc OTP Data -#define FCFG1_O_MISC_OTP_DATA 0x00000320 +#define FCFG1_O_MISC_OTP_DATA 0x00000320 // IO Configuration -#define FCFG1_O_IOCONF 0x00000344 +#define FCFG1_O_IOCONF 0x00000344 // Internal -#define FCFG1_O_CONFIG_IF_ADC 0x0000034C +#define FCFG1_O_CONFIG_IF_ADC 0x0000034C // Internal -#define FCFG1_O_CONFIG_OSC_TOP 0x00000350 +#define FCFG1_O_CONFIG_OSC_TOP 0x00000350 // AUX_ADC Gain in Absolute Reference Mode -#define FCFG1_O_SOC_ADC_ABS_GAIN 0x0000035C +#define FCFG1_O_SOC_ADC_ABS_GAIN 0x0000035C // AUX_ADC Gain in Relative Reference Mode -#define FCFG1_O_SOC_ADC_REL_GAIN 0x00000360 +#define FCFG1_O_SOC_ADC_REL_GAIN 0x00000360 // AUX_ADC Temperature Offsets in Absolute Reference Mode -#define FCFG1_O_SOC_ADC_OFFSET_INT 0x00000368 +#define FCFG1_O_SOC_ADC_OFFSET_INT 0x00000368 // Internal -#define FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT 0x0000036C +#define FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT 0x0000036C // Internal -#define FCFG1_O_AMPCOMP_TH1 0x00000370 +#define FCFG1_O_AMPCOMP_TH1 0x00000370 // Internal -#define FCFG1_O_AMPCOMP_TH2 0x00000374 +#define FCFG1_O_AMPCOMP_TH2 0x00000374 // Internal -#define FCFG1_O_AMPCOMP_CTRL1 0x00000378 +#define FCFG1_O_AMPCOMP_CTRL1 0x00000378 // Internal -#define FCFG1_O_ANABYPASS_VALUE2 0x0000037C +#define FCFG1_O_ANABYPASS_VALUE2 0x0000037C // Internal -#define FCFG1_O_VOLT_TRIM 0x00000388 +#define FCFG1_O_VOLT_TRIM 0x00000388 // OSC Configuration -#define FCFG1_O_OSC_CONF 0x0000038C +#define FCFG1_O_OSC_CONF 0x0000038C // Internal -#define FCFG1_O_FREQ_OFFSET 0x00000390 +#define FCFG1_O_FREQ_OFFSET 0x00000390 // Internal -#define FCFG1_O_MISC_OTP_DATA_1 0x00000398 +#define FCFG1_O_MISC_OTP_DATA_1 0x00000398 // Shadow of EFUSE:DIE_ID_0 register -#define FCFG1_O_SHDW_DIE_ID_0 0x000003D0 +#define FCFG1_O_SHDW_DIE_ID_0 0x000003D0 // Shadow of EFUSE:DIE_ID_1 register -#define FCFG1_O_SHDW_DIE_ID_1 0x000003D4 +#define FCFG1_O_SHDW_DIE_ID_1 0x000003D4 // Shadow of EFUSE:DIE_ID_2 register -#define FCFG1_O_SHDW_DIE_ID_2 0x000003D8 +#define FCFG1_O_SHDW_DIE_ID_2 0x000003D8 // Shadow of EFUSE:DIE_ID_3 register -#define FCFG1_O_SHDW_DIE_ID_3 0x000003DC +#define FCFG1_O_SHDW_DIE_ID_3 0x000003DC // Internal -#define FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM 0x000003F8 +#define FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM 0x000003F8 // Internal -#define FCFG1_O_SHDW_ANA_TRIM 0x000003FC +#define FCFG1_O_SHDW_ANA_TRIM 0x000003FC // Internal -#define FCFG1_O_DAC_BIAS_CNF 0x0000040C +#define FCFG1_O_DAC_BIAS_CNF 0x0000040C // Internal -#define FCFG1_O_TFW_PROBE 0x00000418 +#define FCFG1_O_TFW_PROBE 0x00000418 // Internal -#define FCFG1_O_TFW_FT 0x0000041C +#define FCFG1_O_TFW_FT 0x0000041C // Internal -#define FCFG1_O_DAC_CAL0 0x00000420 +#define FCFG1_O_DAC_CAL0 0x00000420 // Internal -#define FCFG1_O_DAC_CAL1 0x00000424 +#define FCFG1_O_DAC_CAL1 0x00000424 // Internal -#define FCFG1_O_DAC_CAL2 0x00000428 +#define FCFG1_O_DAC_CAL2 0x00000428 // Internal -#define FCFG1_O_DAC_CAL3 0x0000042C +#define FCFG1_O_DAC_CAL3 0x0000042C //***************************************************************************** // @@ -291,9 +291,9 @@ // Any test of this field by SW should be implemented as a 'greater or equal' // comparison as signed integer. // Value may change without warning. -#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_W 8 -#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M 0x000000FF -#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S 0 +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_W 8 +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M 0x000000FF +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S 0 //***************************************************************************** // @@ -303,9 +303,9 @@ // Field: [7:0] HPOSC_COMP_P3 // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W 8 -#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_M 0x000000FF -#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S 0 +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W 8 +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_M 0x000000FF +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S 0 //***************************************************************************** // @@ -315,23 +315,23 @@ // Field: [31:16] HPOSC_D5 // // Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_W 16 -#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_M 0xFFFF0000 -#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_S 16 +#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_W 16 +#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_M 0xFFFF0000 +#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_S 16 // Field: [15:8] HPOSC_T5 // // Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_W 8 -#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_M 0x0000FF00 -#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_S 8 +#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_W 8 +#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_M 0x0000FF00 +#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_S 8 // Field: [7:0] HPOSC_DT5 // // Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_W 8 -#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_M 0x000000FF -#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_S 0 +#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_W 8 +#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_M 0x000000FF +#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_S 0 //***************************************************************************** // @@ -341,23 +341,23 @@ // Field: [31:16] HPOSC_D4 // // Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_W 16 -#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_M 0xFFFF0000 -#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_S 16 +#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_W 16 +#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_M 0xFFFF0000 +#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_S 16 // Field: [15:8] HPOSC_T4 // // Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_W 8 -#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_M 0x0000FF00 -#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_S 8 +#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_W 8 +#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_M 0x0000FF00 +#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_S 8 // Field: [7:0] HPOSC_DT4 // // Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_W 8 -#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_M 0x000000FF -#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_S 0 +#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_W 8 +#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_M 0x000000FF +#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_S 0 //***************************************************************************** // @@ -367,23 +367,23 @@ // Field: [31:16] HPOSC_D3 // // Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_W 16 -#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_M 0xFFFF0000 -#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_S 16 +#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_W 16 +#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_M 0xFFFF0000 +#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_S 16 // Field: [15:8] HPOSC_T3 // // Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_W 8 -#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_M 0x0000FF00 -#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_S 8 +#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_W 8 +#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_M 0x0000FF00 +#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_S 8 // Field: [7:0] HPOSC_DT3 // // Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_W 8 -#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_M 0x000000FF -#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_S 0 +#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_W 8 +#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_M 0x000000FF +#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_S 0 //***************************************************************************** // @@ -393,23 +393,23 @@ // Field: [31:16] HPOSC_D2 // // Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_W 16 -#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_M 0xFFFF0000 -#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_S 16 +#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_W 16 +#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_M 0xFFFF0000 +#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_S 16 // Field: [15:8] HPOSC_T2 // // Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_W 8 -#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_M 0x0000FF00 -#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_S 8 +#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_W 8 +#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_M 0x0000FF00 +#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_S 8 // Field: [7:0] HPOSC_DT2 // // Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_W 8 -#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_M 0x000000FF -#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_S 0 +#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_W 8 +#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_M 0x000000FF +#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_S 0 //***************************************************************************** // @@ -419,23 +419,23 @@ // Field: [31:16] HPOSC_D1 // // Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_W 16 -#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_M 0xFFFF0000 -#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_S 16 +#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_W 16 +#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_M 0xFFFF0000 +#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_S 16 // Field: [15:8] HPOSC_T1 // // Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_W 8 -#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_M 0x0000FF00 -#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_S 8 +#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_W 8 +#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_M 0x0000FF00 +#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_S 8 // Field: [7:0] HPOSC_DT1 // // Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_W 8 -#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_M 0x000000FF -#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_S 0 +#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_W 8 +#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_M 0x000000FF +#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_S 0 //***************************************************************************** // @@ -445,53 +445,53 @@ // Field: [31:28] IFAMP_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC26_FE_IFAMP_IB_W 4 -#define FCFG1_CONFIG_CC26_FE_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_CC26_FE_IFAMP_IB_S 28 +#define FCFG1_CONFIG_CC26_FE_IFAMP_IB_W 4 +#define FCFG1_CONFIG_CC26_FE_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_CC26_FE_IFAMP_IB_S 28 // Field: [27:24] LNA_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC26_FE_LNA_IB_W 4 -#define FCFG1_CONFIG_CC26_FE_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_CC26_FE_LNA_IB_S 24 +#define FCFG1_CONFIG_CC26_FE_LNA_IB_W 4 +#define FCFG1_CONFIG_CC26_FE_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_CC26_FE_LNA_IB_S 24 // Field: [23:19] IFAMP_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_S 19 +#define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_S 19 // Field: [18:14] CTL_PA0_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_S 14 +#define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_S 14 // Field: [13] PATRIMCOMPLETE_N // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N 0x00002000 -#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_BITN 13 -#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_M 0x00002000 -#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_S 13 +#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N 0x00002000 +#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_BITN 13 +#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_M 0x00002000 +#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_S 13 // Field: [12] RSSITRIMCOMPLETE_N // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N 0x00001000 -#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_BITN 12 -#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_M 0x00001000 -#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_S 12 +#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N 0x00001000 +#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_BITN 12 +#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_M 0x00001000 +#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_S 12 // Field: [7:0] RSSI_OFFSET // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_M 0x000000FF -#define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_S 0 +#define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_M 0x000000FF +#define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_S 0 //***************************************************************************** // @@ -501,53 +501,53 @@ // Field: [31:28] IFAMP_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC13_FE_IFAMP_IB_W 4 -#define FCFG1_CONFIG_CC13_FE_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_CC13_FE_IFAMP_IB_S 28 +#define FCFG1_CONFIG_CC13_FE_IFAMP_IB_W 4 +#define FCFG1_CONFIG_CC13_FE_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_CC13_FE_IFAMP_IB_S 28 // Field: [27:24] LNA_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC13_FE_LNA_IB_W 4 -#define FCFG1_CONFIG_CC13_FE_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_CC13_FE_LNA_IB_S 24 +#define FCFG1_CONFIG_CC13_FE_LNA_IB_W 4 +#define FCFG1_CONFIG_CC13_FE_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_CC13_FE_LNA_IB_S 24 // Field: [23:19] IFAMP_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_S 19 +#define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_S 19 // Field: [18:14] CTL_PA0_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_S 14 +#define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_S 14 // Field: [13] PATRIMCOMPLETE_N // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N 0x00002000 -#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_BITN 13 -#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_M 0x00002000 -#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_S 13 +#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N 0x00002000 +#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_BITN 13 +#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_M 0x00002000 +#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_S 13 // Field: [12] RSSITRIMCOMPLETE_N // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N 0x00001000 -#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_BITN 12 -#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_M 0x00001000 -#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_S 12 +#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N 0x00001000 +#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_BITN 12 +#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_M 0x00001000 +#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_S 12 // Field: [7:0] RSSI_OFFSET // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_M 0x000000FF -#define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_S 0 +#define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_M 0x000000FF +#define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_S 0 //***************************************************************************** // @@ -557,53 +557,53 @@ // Field: [31] DISABLE_CORNER_CAP // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP 0x80000000 -#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_BITN 31 -#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_M 0x80000000 -#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_S 31 +#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP 0x80000000 +#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_BITN 31 +#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_M 0x80000000 +#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_S 31 // Field: [30:25] SLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_M 0x7E000000 -#define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_S 25 +#define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_M 0x7E000000 +#define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_S 25 // Field: [21] PA20DBMTRIMCOMPLETE_N // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N 0x00200000 -#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_BITN 21 -#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_M 0x00200000 -#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_S 21 +#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N 0x00200000 +#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_BITN 21 +#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_M 0x00200000 +#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_S 21 // Field: [20:16] CTL_PA_20DBM_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_W 5 -#define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_M 0x001F0000 -#define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_S 16 +#define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_W 5 +#define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_M 0x001F0000 +#define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_S 16 // Field: [15:9] RFLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_M 0x0000FE00 -#define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_S 9 +#define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_M 0x0000FE00 +#define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_S 9 // Field: [8:6] QUANTCTLTHRES // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_S 6 +#define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_S 6 // Field: [5:0] DACTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_COMMON_DACTRIM_W 6 -#define FCFG1_CONFIG_RF_COMMON_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_RF_COMMON_DACTRIM_S 0 +#define FCFG1_CONFIG_RF_COMMON_DACTRIM_W 6 +#define FCFG1_CONFIG_RF_COMMON_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_RF_COMMON_DACTRIM_S 0 //***************************************************************************** // @@ -613,23 +613,23 @@ // Field: [31:28] MIN_ALLOWED_RTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_S 28 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_S 28 // Field: [27:12] RFC_MDM_DEMIQMC0 // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N // @@ -651,23 +651,23 @@ // Field: [31:28] MIN_ALLOWED_RTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_S 28 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_S 28 // Field: [27:12] RFC_MDM_DEMIQMC0 // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N // @@ -689,23 +689,23 @@ // Field: [31:28] MIN_ALLOWED_RTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_S 28 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_S 28 // Field: [27:12] RFC_MDM_DEMIQMC0 // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N // @@ -727,23 +727,23 @@ // Field: [31:28] MIN_ALLOWED_RTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_S 28 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_S 28 // Field: [27:12] RFC_MDM_DEMIQMC0 // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N // @@ -765,23 +765,23 @@ // Field: [31:28] MIN_ALLOWED_RTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_S 28 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_S 28 // Field: [27:12] RFC_MDM_DEMIQMC0 // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N // @@ -803,23 +803,23 @@ // Field: [31:28] MIN_ALLOWED_RTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_S 28 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_S 28 // Field: [27:12] RFC_MDM_DEMIQMC0 // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N // @@ -841,33 +841,33 @@ // Field: [31:28] MIN_ALLOWED_RTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_S 28 +#define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_S 28 // Field: [27:12] RFC_MDM_DEMIQMC0 // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 0x00000020 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 0x00000020 #define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 5 -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 5 //***************************************************************************** @@ -878,23 +878,23 @@ // Field: [31:28] MIN_ALLOWED_RTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_S 28 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_S 28 // Field: [27:12] RFC_MDM_DEMIQMC0 // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N // @@ -916,23 +916,23 @@ // Field: [31:28] MIN_ALLOWED_RTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_S 28 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_S 28 // Field: [27:12] RFC_MDM_DEMIQMC0 // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N // @@ -954,34 +954,34 @@ // Field: [31:28] MIN_ALLOWED_RTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_S 28 +#define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_S 28 // Field: [27:12] RFC_MDM_DEMIQMC0 // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 0x00000020 #define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 5 -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 5 //***************************************************************************** @@ -992,23 +992,23 @@ // Field: [31:28] MIN_ALLOWED_RTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_S 28 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_S 28 // Field: [27:12] RFC_MDM_DEMIQMC0 // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N // @@ -1030,23 +1030,23 @@ // Field: [31:28] MIN_ALLOWED_RTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_S 28 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_S 28 // Field: [27:12] RFC_MDM_DEMIQMC0 // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N // @@ -1068,34 +1068,34 @@ // Field: [31:28] MIN_ALLOWED_RTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_S 28 +#define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_S 28 // Field: [27:12] RFC_MDM_DEMIQMC0 // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 0x00000020 #define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 5 -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 5 //***************************************************************************** @@ -1106,34 +1106,34 @@ // Field: [31:28] MIN_ALLOWED_RTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_S 28 +#define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_W 4 +#define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_M 0xF0000000 +#define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_S 28 // Field: [27:12] RFC_MDM_DEMIQMC0 // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ 0x00000020 #define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ 5 -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ 5 //***************************************************************************** @@ -1144,9 +1144,9 @@ // Field: [31:0] LOT_NUMBER // // Number of the manufacturing lot that produced this unit. -#define FCFG1_FLASH_NUMBER_LOT_NUMBER_W 32 -#define FCFG1_FLASH_NUMBER_LOT_NUMBER_M 0xFFFFFFFF -#define FCFG1_FLASH_NUMBER_LOT_NUMBER_S 0 +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_W 32 +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_M 0xFFFFFFFF +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_S 0 //***************************************************************************** // @@ -1156,16 +1156,16 @@ // Field: [31:16] XCOORDINATE // // X coordinate of this unit on the wafer. -#define FCFG1_FLASH_COORDINATE_XCOORDINATE_W 16 -#define FCFG1_FLASH_COORDINATE_XCOORDINATE_M 0xFFFF0000 -#define FCFG1_FLASH_COORDINATE_XCOORDINATE_S 16 +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_W 16 +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_M 0xFFFF0000 +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_S 16 // Field: [15:0] YCOORDINATE // // Y coordinate of this unit on the wafer. -#define FCFG1_FLASH_COORDINATE_YCOORDINATE_W 16 -#define FCFG1_FLASH_COORDINATE_YCOORDINATE_M 0x0000FFFF -#define FCFG1_FLASH_COORDINATE_YCOORDINATE_S 0 +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_W 16 +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_M 0x0000FFFF +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_S 0 //***************************************************************************** // @@ -1175,30 +1175,30 @@ // Field: [31:24] PSU // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_E_P_PSU_W 8 -#define FCFG1_FLASH_E_P_PSU_M 0xFF000000 -#define FCFG1_FLASH_E_P_PSU_S 24 +#define FCFG1_FLASH_E_P_PSU_W 8 +#define FCFG1_FLASH_E_P_PSU_M 0xFF000000 +#define FCFG1_FLASH_E_P_PSU_S 24 // Field: [23:16] ESU // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_E_P_ESU_W 8 -#define FCFG1_FLASH_E_P_ESU_M 0x00FF0000 -#define FCFG1_FLASH_E_P_ESU_S 16 +#define FCFG1_FLASH_E_P_ESU_W 8 +#define FCFG1_FLASH_E_P_ESU_M 0x00FF0000 +#define FCFG1_FLASH_E_P_ESU_S 16 // Field: [15:8] PVSU // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_E_P_PVSU_W 8 -#define FCFG1_FLASH_E_P_PVSU_M 0x0000FF00 -#define FCFG1_FLASH_E_P_PVSU_S 8 +#define FCFG1_FLASH_E_P_PVSU_W 8 +#define FCFG1_FLASH_E_P_PVSU_M 0x0000FF00 +#define FCFG1_FLASH_E_P_PVSU_S 8 // Field: [7:0] EVSU // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_E_P_EVSU_W 8 -#define FCFG1_FLASH_E_P_EVSU_M 0x000000FF -#define FCFG1_FLASH_E_P_EVSU_S 0 +#define FCFG1_FLASH_E_P_EVSU_W 8 +#define FCFG1_FLASH_E_P_EVSU_M 0x000000FF +#define FCFG1_FLASH_E_P_EVSU_S 0 //***************************************************************************** // @@ -1208,30 +1208,30 @@ // Field: [31:24] RVSU // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_C_E_P_R_RVSU_W 8 -#define FCFG1_FLASH_C_E_P_R_RVSU_M 0xFF000000 -#define FCFG1_FLASH_C_E_P_R_RVSU_S 24 +#define FCFG1_FLASH_C_E_P_R_RVSU_W 8 +#define FCFG1_FLASH_C_E_P_R_RVSU_M 0xFF000000 +#define FCFG1_FLASH_C_E_P_R_RVSU_S 24 // Field: [23:16] PV_ACCESS // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_W 8 -#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_M 0x00FF0000 -#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_S 16 +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_W 8 +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_M 0x00FF0000 +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_S 16 // Field: [15:12] A_EXEZ_SETUP // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_W 4 -#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M 0x0000F000 -#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S 12 +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_W 4 +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M 0x0000F000 +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S 12 // Field: [11:0] CVSU // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_C_E_P_R_CVSU_W 12 -#define FCFG1_FLASH_C_E_P_R_CVSU_M 0x00000FFF -#define FCFG1_FLASH_C_E_P_R_CVSU_S 0 +#define FCFG1_FLASH_C_E_P_R_CVSU_W 12 +#define FCFG1_FLASH_C_E_P_R_CVSU_M 0x00000FFF +#define FCFG1_FLASH_C_E_P_R_CVSU_S 0 //***************************************************************************** // @@ -1241,30 +1241,30 @@ // Field: [31:24] PH // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_P_R_PV_PH_W 8 -#define FCFG1_FLASH_P_R_PV_PH_M 0xFF000000 -#define FCFG1_FLASH_P_R_PV_PH_S 24 +#define FCFG1_FLASH_P_R_PV_PH_W 8 +#define FCFG1_FLASH_P_R_PV_PH_M 0xFF000000 +#define FCFG1_FLASH_P_R_PV_PH_S 24 // Field: [23:16] RH // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_P_R_PV_RH_W 8 -#define FCFG1_FLASH_P_R_PV_RH_M 0x00FF0000 -#define FCFG1_FLASH_P_R_PV_RH_S 16 +#define FCFG1_FLASH_P_R_PV_RH_W 8 +#define FCFG1_FLASH_P_R_PV_RH_M 0x00FF0000 +#define FCFG1_FLASH_P_R_PV_RH_S 16 // Field: [15:8] PVH // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_P_R_PV_PVH_W 8 -#define FCFG1_FLASH_P_R_PV_PVH_M 0x0000FF00 -#define FCFG1_FLASH_P_R_PV_PVH_S 8 +#define FCFG1_FLASH_P_R_PV_PVH_W 8 +#define FCFG1_FLASH_P_R_PV_PVH_M 0x0000FF00 +#define FCFG1_FLASH_P_R_PV_PVH_S 8 // Field: [7:0] PVH2 // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_P_R_PV_PVH2_W 8 -#define FCFG1_FLASH_P_R_PV_PVH2_M 0x000000FF -#define FCFG1_FLASH_P_R_PV_PVH2_S 0 +#define FCFG1_FLASH_P_R_PV_PVH2_W 8 +#define FCFG1_FLASH_P_R_PV_PVH2_M 0x000000FF +#define FCFG1_FLASH_P_R_PV_PVH2_S 0 //***************************************************************************** // @@ -1274,30 +1274,30 @@ // Field: [31:24] EH // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_EH_SEQ_EH_W 8 -#define FCFG1_FLASH_EH_SEQ_EH_M 0xFF000000 -#define FCFG1_FLASH_EH_SEQ_EH_S 24 +#define FCFG1_FLASH_EH_SEQ_EH_W 8 +#define FCFG1_FLASH_EH_SEQ_EH_M 0xFF000000 +#define FCFG1_FLASH_EH_SEQ_EH_S 24 // Field: [23:16] SEQ // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_EH_SEQ_SEQ_W 8 -#define FCFG1_FLASH_EH_SEQ_SEQ_M 0x00FF0000 -#define FCFG1_FLASH_EH_SEQ_SEQ_S 16 +#define FCFG1_FLASH_EH_SEQ_SEQ_W 8 +#define FCFG1_FLASH_EH_SEQ_SEQ_M 0x00FF0000 +#define FCFG1_FLASH_EH_SEQ_SEQ_S 16 // Field: [15:12] VSTAT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_EH_SEQ_VSTAT_W 4 -#define FCFG1_FLASH_EH_SEQ_VSTAT_M 0x0000F000 -#define FCFG1_FLASH_EH_SEQ_VSTAT_S 12 +#define FCFG1_FLASH_EH_SEQ_VSTAT_W 4 +#define FCFG1_FLASH_EH_SEQ_VSTAT_M 0x0000F000 +#define FCFG1_FLASH_EH_SEQ_VSTAT_S 12 // Field: [11:0] SM_FREQUENCY // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_W 12 -#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_M 0x00000FFF -#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_S 0 +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_W 12 +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_M 0x00000FFF +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_S 0 //***************************************************************************** // @@ -1307,16 +1307,16 @@ // Field: [31:16] VHV_E_START // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_E_VHV_E_START_W 16 -#define FCFG1_FLASH_VHV_E_VHV_E_START_M 0xFFFF0000 -#define FCFG1_FLASH_VHV_E_VHV_E_START_S 16 +#define FCFG1_FLASH_VHV_E_VHV_E_START_W 16 +#define FCFG1_FLASH_VHV_E_VHV_E_START_M 0xFFFF0000 +#define FCFG1_FLASH_VHV_E_VHV_E_START_S 16 // Field: [15:0] VHV_E_STEP_HIGHT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_W 16 -#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M 0x0000FFFF -#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S 0 +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_W 16 +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M 0x0000FFFF +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S 0 //***************************************************************************** // @@ -1326,23 +1326,23 @@ // Field: [31:24] PUMP_SU // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PP_PUMP_SU_W 8 -#define FCFG1_FLASH_PP_PUMP_SU_M 0xFF000000 -#define FCFG1_FLASH_PP_PUMP_SU_S 24 +#define FCFG1_FLASH_PP_PUMP_SU_W 8 +#define FCFG1_FLASH_PP_PUMP_SU_M 0xFF000000 +#define FCFG1_FLASH_PP_PUMP_SU_S 24 // Field: [23:16] TRIM3P4 // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PP_TRIM3P4_W 8 -#define FCFG1_FLASH_PP_TRIM3P4_M 0x00FF0000 -#define FCFG1_FLASH_PP_TRIM3P4_S 16 +#define FCFG1_FLASH_PP_TRIM3P4_W 8 +#define FCFG1_FLASH_PP_TRIM3P4_M 0x00FF0000 +#define FCFG1_FLASH_PP_TRIM3P4_S 16 // Field: [15:0] MAX_PP // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PP_MAX_PP_W 16 -#define FCFG1_FLASH_PP_MAX_PP_M 0x0000FFFF -#define FCFG1_FLASH_PP_MAX_PP_S 0 +#define FCFG1_FLASH_PP_MAX_PP_W 16 +#define FCFG1_FLASH_PP_MAX_PP_M 0x0000FFFF +#define FCFG1_FLASH_PP_MAX_PP_S 0 //***************************************************************************** // @@ -1352,16 +1352,16 @@ // Field: [31:16] MAX_EP // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PROG_EP_MAX_EP_W 16 -#define FCFG1_FLASH_PROG_EP_MAX_EP_M 0xFFFF0000 -#define FCFG1_FLASH_PROG_EP_MAX_EP_S 16 +#define FCFG1_FLASH_PROG_EP_MAX_EP_W 16 +#define FCFG1_FLASH_PROG_EP_MAX_EP_M 0xFFFF0000 +#define FCFG1_FLASH_PROG_EP_MAX_EP_S 16 // Field: [15:0] PROGRAM_PW // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_W 16 -#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_M 0x0000FFFF -#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_S 0 +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_W 16 +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_M 0x0000FFFF +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_S 0 //***************************************************************************** // @@ -1371,9 +1371,9 @@ // Field: [31:0] ERASE_PW // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_ERA_PW_ERASE_PW_W 32 -#define FCFG1_FLASH_ERA_PW_ERASE_PW_M 0xFFFFFFFF -#define FCFG1_FLASH_ERA_PW_ERASE_PW_S 0 +#define FCFG1_FLASH_ERA_PW_ERASE_PW_W 32 +#define FCFG1_FLASH_ERA_PW_ERASE_PW_M 0xFFFFFFFF +#define FCFG1_FLASH_ERA_PW_ERASE_PW_S 0 //***************************************************************************** // @@ -1383,30 +1383,30 @@ // Field: [27:24] TRIM13_P // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_TRIM13_P_W 4 -#define FCFG1_FLASH_VHV_TRIM13_P_M 0x0F000000 -#define FCFG1_FLASH_VHV_TRIM13_P_S 24 +#define FCFG1_FLASH_VHV_TRIM13_P_W 4 +#define FCFG1_FLASH_VHV_TRIM13_P_M 0x0F000000 +#define FCFG1_FLASH_VHV_TRIM13_P_S 24 // Field: [19:16] VHV_P // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_VHV_P_W 4 -#define FCFG1_FLASH_VHV_VHV_P_M 0x000F0000 -#define FCFG1_FLASH_VHV_VHV_P_S 16 +#define FCFG1_FLASH_VHV_VHV_P_W 4 +#define FCFG1_FLASH_VHV_VHV_P_M 0x000F0000 +#define FCFG1_FLASH_VHV_VHV_P_S 16 // Field: [11:8] TRIM13_E // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_TRIM13_E_W 4 -#define FCFG1_FLASH_VHV_TRIM13_E_M 0x00000F00 -#define FCFG1_FLASH_VHV_TRIM13_E_S 8 +#define FCFG1_FLASH_VHV_TRIM13_E_W 4 +#define FCFG1_FLASH_VHV_TRIM13_E_M 0x00000F00 +#define FCFG1_FLASH_VHV_TRIM13_E_S 8 // Field: [3:0] VHV_E // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_VHV_E_W 4 -#define FCFG1_FLASH_VHV_VHV_E_M 0x0000000F -#define FCFG1_FLASH_VHV_VHV_E_S 0 +#define FCFG1_FLASH_VHV_VHV_E_W 4 +#define FCFG1_FLASH_VHV_VHV_E_M 0x0000000F +#define FCFG1_FLASH_VHV_VHV_E_S 0 //***************************************************************************** // @@ -1416,30 +1416,30 @@ // Field: [27:24] TRIM13_PV // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_PV_TRIM13_PV_W 4 -#define FCFG1_FLASH_VHV_PV_TRIM13_PV_M 0x0F000000 -#define FCFG1_FLASH_VHV_PV_TRIM13_PV_S 24 +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_W 4 +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_M 0x0F000000 +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_S 24 // Field: [19:16] VHV_PV // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_PV_VHV_PV_W 4 -#define FCFG1_FLASH_VHV_PV_VHV_PV_M 0x000F0000 -#define FCFG1_FLASH_VHV_PV_VHV_PV_S 16 +#define FCFG1_FLASH_VHV_PV_VHV_PV_W 4 +#define FCFG1_FLASH_VHV_PV_VHV_PV_M 0x000F0000 +#define FCFG1_FLASH_VHV_PV_VHV_PV_S 16 // Field: [15:8] VCG2P5 // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_PV_VCG2P5_W 8 -#define FCFG1_FLASH_VHV_PV_VCG2P5_M 0x0000FF00 -#define FCFG1_FLASH_VHV_PV_VCG2P5_S 8 +#define FCFG1_FLASH_VHV_PV_VCG2P5_W 8 +#define FCFG1_FLASH_VHV_PV_VCG2P5_M 0x0000FF00 +#define FCFG1_FLASH_VHV_PV_VCG2P5_S 8 // Field: [7:0] VINH // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_PV_VINH_W 8 -#define FCFG1_FLASH_VHV_PV_VINH_M 0x000000FF -#define FCFG1_FLASH_VHV_PV_VINH_S 0 +#define FCFG1_FLASH_VHV_PV_VINH_W 8 +#define FCFG1_FLASH_VHV_PV_VINH_M 0x000000FF +#define FCFG1_FLASH_VHV_PV_VINH_S 0 //***************************************************************************** // @@ -1449,30 +1449,30 @@ // Field: [31:24] VSL_P // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_V_VSL_P_W 8 -#define FCFG1_FLASH_V_VSL_P_M 0xFF000000 -#define FCFG1_FLASH_V_VSL_P_S 24 +#define FCFG1_FLASH_V_VSL_P_W 8 +#define FCFG1_FLASH_V_VSL_P_M 0xFF000000 +#define FCFG1_FLASH_V_VSL_P_S 24 // Field: [23:16] VWL_P // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_V_VWL_P_W 8 -#define FCFG1_FLASH_V_VWL_P_M 0x00FF0000 -#define FCFG1_FLASH_V_VWL_P_S 16 +#define FCFG1_FLASH_V_VWL_P_W 8 +#define FCFG1_FLASH_V_VWL_P_M 0x00FF0000 +#define FCFG1_FLASH_V_VWL_P_S 16 // Field: [15:8] V_READ // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_V_V_READ_W 8 -#define FCFG1_FLASH_V_V_READ_M 0x0000FF00 -#define FCFG1_FLASH_V_V_READ_S 8 +#define FCFG1_FLASH_V_V_READ_W 8 +#define FCFG1_FLASH_V_V_READ_M 0x0000FF00 +#define FCFG1_FLASH_V_V_READ_S 8 // Field: [7:0] TRIM0P8 // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_V_TRIM0P8_W 8 -#define FCFG1_FLASH_V_TRIM0P8_M 0x000000FF -#define FCFG1_FLASH_V_TRIM0P8_S 0 +#define FCFG1_FLASH_V_TRIM0P8_W 8 +#define FCFG1_FLASH_V_TRIM0P8_M 0x000000FF +#define FCFG1_FLASH_V_TRIM0P8_S 0 //***************************************************************************** // @@ -1482,9 +1482,9 @@ // Field: [31:28] PG_REV // // Field used to distinguish revisions of the device -#define FCFG1_USER_ID_PG_REV_W 4 -#define FCFG1_USER_ID_PG_REV_M 0xF0000000 -#define FCFG1_USER_ID_PG_REV_S 28 +#define FCFG1_USER_ID_PG_REV_W 4 +#define FCFG1_USER_ID_PG_REV_M 0xF0000000 +#define FCFG1_USER_ID_PG_REV_S 28 // Field: [27:26] VER // @@ -1493,27 +1493,27 @@ // 0x0: Bits [25:12] of this register has the stated meaning. // // Any other setting indicate a different encoding of these bits. -#define FCFG1_USER_ID_VER_W 2 -#define FCFG1_USER_ID_VER_M 0x0C000000 -#define FCFG1_USER_ID_VER_S 26 +#define FCFG1_USER_ID_VER_W 2 +#define FCFG1_USER_ID_VER_M 0x0C000000 +#define FCFG1_USER_ID_VER_S 26 // Field: [25] PA // // 0: Does not support 20dBm PA // 1: Supports 20dBM PA -#define FCFG1_USER_ID_PA 0x02000000 -#define FCFG1_USER_ID_PA_BITN 25 -#define FCFG1_USER_ID_PA_M 0x02000000 -#define FCFG1_USER_ID_PA_S 25 +#define FCFG1_USER_ID_PA 0x02000000 +#define FCFG1_USER_ID_PA_BITN 25 +#define FCFG1_USER_ID_PA_M 0x02000000 +#define FCFG1_USER_ID_PA_S 25 // Field: [23] CC13 // // 0: CC26xx device type // 1: CC13xx device type -#define FCFG1_USER_ID_CC13 0x00800000 -#define FCFG1_USER_ID_CC13_BITN 23 -#define FCFG1_USER_ID_CC13_M 0x00800000 -#define FCFG1_USER_ID_CC13_S 23 +#define FCFG1_USER_ID_CC13 0x00800000 +#define FCFG1_USER_ID_CC13_BITN 23 +#define FCFG1_USER_ID_CC13_M 0x00800000 +#define FCFG1_USER_ID_CC13_S 23 // Field: [22:19] SEQUENCE // @@ -1521,9 +1521,9 @@ // // Used to differentiate between marketing/orderable product where other fields // of this register are the same (temp range, flash size, voltage range etc) -#define FCFG1_USER_ID_SEQUENCE_W 4 -#define FCFG1_USER_ID_SEQUENCE_M 0x00780000 -#define FCFG1_USER_ID_SEQUENCE_S 19 +#define FCFG1_USER_ID_SEQUENCE_W 4 +#define FCFG1_USER_ID_SEQUENCE_M 0x00780000 +#define FCFG1_USER_ID_SEQUENCE_S 19 // Field: [18:16] PKG // @@ -1538,9 +1538,9 @@ // // Other values are reserved for future use. // Packages available for a specific device are shown in the device datasheet. -#define FCFG1_USER_ID_PKG_W 3 -#define FCFG1_USER_ID_PKG_M 0x00070000 -#define FCFG1_USER_ID_PKG_S 16 +#define FCFG1_USER_ID_PKG_W 3 +#define FCFG1_USER_ID_PKG_M 0x00070000 +#define FCFG1_USER_ID_PKG_S 16 // Field: [15:12] PROTOCOL // @@ -1553,9 +1553,9 @@ // // More than one protocol can be supported on same device - values above are // then combined. -#define FCFG1_USER_ID_PROTOCOL_W 4 -#define FCFG1_USER_ID_PROTOCOL_M 0x0000F000 -#define FCFG1_USER_ID_PROTOCOL_S 12 +#define FCFG1_USER_ID_PROTOCOL_W 4 +#define FCFG1_USER_ID_PROTOCOL_M 0x0000F000 +#define FCFG1_USER_ID_PROTOCOL_S 12 //***************************************************************************** // @@ -1565,45 +1565,45 @@ // Field: [31:23] EC_STEP_SIZE // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_W 9 -#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M 0xFF800000 -#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S 23 +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_W 9 +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M 0xFF800000 +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S 23 // Field: [22] DO_PRECOND // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND 0x00400000 -#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_BITN 22 -#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M 0x00400000 -#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S 22 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND 0x00400000 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_BITN 22 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M 0x00400000 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S 22 // Field: [21:18] MAX_EC_LEVEL // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_W 4 -#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M 0x003C0000 -#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S 18 +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_W 4 +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M 0x003C0000 +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S 18 // Field: [17:16] TRIM_1P7 // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_W 2 -#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M 0x00030000 -#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S 16 +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_W 2 +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M 0x00030000 +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S 16 // Field: [15:8] FLASH_SIZE // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_W 8 -#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_M 0x0000FF00 -#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_S 8 +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_W 8 +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_M 0x0000FF00 +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_S 8 // Field: [7:0] WAIT_SYSCODE // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_W 8 -#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_M 0x000000FF -#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_S 0 +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_W 8 +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_M 0x000000FF +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_S 0 //***************************************************************************** // @@ -1613,75 +1613,75 @@ // Field: [31] RCOSCHFCTRIMFRACT_EN // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN 0x80000000 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_BITN 31 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_M 0x80000000 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_S 31 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN 0x80000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_BITN 31 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_M 0x80000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_S 31 // Field: [30:26] RCOSCHFCTRIMFRACT // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_W 5 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_M 0x7C000000 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_S 26 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_W 5 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_M 0x7C000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_S 26 // Field: [24:23] SET_RCOSC_HF_FINE_RESISTOR // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_W 2 -#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_M 0x01800000 -#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_S 23 +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_W 2 +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_M 0x01800000 +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_S 23 // Field: [22] ATESTLF_UDIGLDO_IBIAS_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM 0x00400000 -#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_BITN 22 -#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_M 0x00400000 -#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_S 22 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM 0x00400000 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_BITN 22 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_M 0x00400000 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_S 22 // Field: [21:15] NANOAMP_RES_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_W 7 -#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_M 0x003F8000 -#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_S 15 +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_W 7 +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_M 0x003F8000 +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_S 15 // Field: [11] DITHER_EN // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DITHER_EN 0x00000800 -#define FCFG1_ANA2_TRIM_DITHER_EN_BITN 11 -#define FCFG1_ANA2_TRIM_DITHER_EN_M 0x00000800 -#define FCFG1_ANA2_TRIM_DITHER_EN_S 11 +#define FCFG1_ANA2_TRIM_DITHER_EN 0x00000800 +#define FCFG1_ANA2_TRIM_DITHER_EN_BITN 11 +#define FCFG1_ANA2_TRIM_DITHER_EN_M 0x00000800 +#define FCFG1_ANA2_TRIM_DITHER_EN_S 11 // Field: [10:8] DCDC_IPEAK // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DCDC_IPEAK_W 3 -#define FCFG1_ANA2_TRIM_DCDC_IPEAK_M 0x00000700 -#define FCFG1_ANA2_TRIM_DCDC_IPEAK_S 8 +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_W 3 +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_M 0x00000700 +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_S 8 // Field: [7:6] DEAD_TIME_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_W 2 -#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_M 0x000000C0 -#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_S 6 +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_W 2 +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_M 0x000000C0 +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_S 6 // Field: [5:3] DCDC_LOW_EN_SEL // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_W 3 -#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_M 0x00000038 -#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_S 3 +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_W 3 +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_M 0x00000038 +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_S 3 // Field: [2:0] DCDC_HIGH_EN_SEL // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_W 3 -#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_M 0x00000007 -#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_S 0 +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_W 3 +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_M 0x00000007 +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_S 0 //***************************************************************************** // @@ -1691,37 +1691,37 @@ // Field: [28:24] VDDR_TRIM_SLEEP // // Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_W 5 -#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M 0x1F000000 -#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S 24 +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_W 5 +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M 0x1F000000 +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S 24 // Field: [18:16] GLDO_CURSRC // // Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_GLDO_CURSRC_W 3 -#define FCFG1_LDO_TRIM_GLDO_CURSRC_M 0x00070000 -#define FCFG1_LDO_TRIM_GLDO_CURSRC_S 16 +#define FCFG1_LDO_TRIM_GLDO_CURSRC_W 3 +#define FCFG1_LDO_TRIM_GLDO_CURSRC_M 0x00070000 +#define FCFG1_LDO_TRIM_GLDO_CURSRC_S 16 // Field: [12:11] ITRIM_DIGLDO_LOAD // // Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_W 2 -#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_M 0x00001800 -#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_S 11 +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_W 2 +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_M 0x00001800 +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_S 11 // Field: [10:8] ITRIM_UDIGLDO // // Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_W 3 -#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_M 0x00000700 -#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_S 8 +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_W 3 +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_M 0x00000700 +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_S 8 // Field: [2:0] VTRIM_DELTA // // Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_VTRIM_DELTA_W 3 -#define FCFG1_LDO_TRIM_VTRIM_DELTA_M 0x00000007 -#define FCFG1_LDO_TRIM_VTRIM_DELTA_S 0 +#define FCFG1_LDO_TRIM_VTRIM_DELTA_W 3 +#define FCFG1_LDO_TRIM_VTRIM_DELTA_M 0x00000007 +#define FCFG1_LDO_TRIM_VTRIM_DELTA_S 0 //***************************************************************************** // @@ -1731,9 +1731,9 @@ // Field: [31:0] ADDR_0_31 // // The first 32-bits of the 64-bit MAC BLE address -#define FCFG1_MAC_BLE_0_ADDR_0_31_W 32 -#define FCFG1_MAC_BLE_0_ADDR_0_31_M 0xFFFFFFFF -#define FCFG1_MAC_BLE_0_ADDR_0_31_S 0 +#define FCFG1_MAC_BLE_0_ADDR_0_31_W 32 +#define FCFG1_MAC_BLE_0_ADDR_0_31_M 0xFFFFFFFF +#define FCFG1_MAC_BLE_0_ADDR_0_31_S 0 //***************************************************************************** // @@ -1743,9 +1743,9 @@ // Field: [31:0] ADDR_32_63 // // The last 32-bits of the 64-bit MAC BLE address -#define FCFG1_MAC_BLE_1_ADDR_32_63_W 32 -#define FCFG1_MAC_BLE_1_ADDR_32_63_M 0xFFFFFFFF -#define FCFG1_MAC_BLE_1_ADDR_32_63_S 0 +#define FCFG1_MAC_BLE_1_ADDR_32_63_W 32 +#define FCFG1_MAC_BLE_1_ADDR_32_63_M 0xFFFFFFFF +#define FCFG1_MAC_BLE_1_ADDR_32_63_S 0 //***************************************************************************** // @@ -1755,9 +1755,9 @@ // Field: [31:0] ADDR_0_31 // // The first 32-bits of the 64-bit MAC 15.4 address -#define FCFG1_MAC_15_4_0_ADDR_0_31_W 32 -#define FCFG1_MAC_15_4_0_ADDR_0_31_M 0xFFFFFFFF -#define FCFG1_MAC_15_4_0_ADDR_0_31_S 0 +#define FCFG1_MAC_15_4_0_ADDR_0_31_W 32 +#define FCFG1_MAC_15_4_0_ADDR_0_31_M 0xFFFFFFFF +#define FCFG1_MAC_15_4_0_ADDR_0_31_S 0 //***************************************************************************** // @@ -1767,9 +1767,9 @@ // Field: [31:0] ADDR_32_63 // // The last 32-bits of the 64-bit MAC 15.4 address -#define FCFG1_MAC_15_4_1_ADDR_32_63_W 32 -#define FCFG1_MAC_15_4_1_ADDR_32_63_M 0xFFFFFFFF -#define FCFG1_MAC_15_4_1_ADDR_32_63_S 0 +#define FCFG1_MAC_15_4_1_ADDR_32_63_W 32 +#define FCFG1_MAC_15_4_1_ADDR_32_63_M 0xFFFFFFFF +#define FCFG1_MAC_15_4_1_ADDR_32_63_S 0 //***************************************************************************** // @@ -1779,154 +1779,154 @@ // Field: [31] STANDBY_MODE_SEL_INT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT 0x80000000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_BITN 31 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M 0x80000000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S 31 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT 0x80000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_BITN 31 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M 0x80000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S 31 // Field: [30:29] STANDBY_PW_SEL_INT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_W 2 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M 0x60000000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S 29 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M 0x60000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S 29 // Field: [28] DIS_STANDBY_INT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT 0x10000000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_BITN 28 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M 0x10000000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_S 28 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT 0x10000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_BITN 28 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M 0x10000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_S 28 // Field: [27] DIS_IDLE_INT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT 0x08000000 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_BITN 27 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M 0x08000000 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S 27 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT 0x08000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_BITN 27 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M 0x08000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S 27 // Field: [26:24] VIN_AT_X_INT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_W 3 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M 0x07000000 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S 24 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M 0x07000000 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S 24 // Field: [23] STANDBY_MODE_SEL_EXT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT 0x00800000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_BITN 23 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M 0x00800000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S 23 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT 0x00800000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_BITN 23 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M 0x00800000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S 23 // Field: [22:21] STANDBY_PW_SEL_EXT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_W 2 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M 0x00600000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S 21 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M 0x00600000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S 21 // Field: [20] DIS_STANDBY_EXT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT 0x00100000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_BITN 20 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M 0x00100000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_S 20 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT 0x00100000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_BITN 20 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M 0x00100000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_S 20 // Field: [19] DIS_IDLE_EXT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT 0x00080000 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_BITN 19 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M 0x00080000 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S 19 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT 0x00080000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_BITN 19 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M 0x00080000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S 19 // Field: [18:16] VIN_AT_X_EXT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_W 3 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M 0x00070000 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S 16 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M 0x00070000 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S 16 // Field: [15] STANDBY_MODE_SEL_INT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD 0x00008000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_BITN 15 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M 0x00008000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S 15 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD 0x00008000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_BITN 15 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M 0x00008000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S 15 // Field: [14:13] STANDBY_PW_SEL_INT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_W 2 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M 0x00006000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S 13 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M 0x00006000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S 13 // Field: [12] DIS_STANDBY_INT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD 0x00001000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_BITN 12 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M 0x00001000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_S 12 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD 0x00001000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_BITN 12 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M 0x00001000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_S 12 // Field: [11] DIS_IDLE_INT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD 0x00000800 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_BITN 11 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M 0x00000800 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S 11 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD 0x00000800 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_BITN 11 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M 0x00000800 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S 11 // Field: [10:8] VIN_AT_X_INT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_W 3 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M 0x00000700 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S 8 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M 0x00000700 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S 8 // Field: [7] STANDBY_MODE_SEL_EXT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD 0x00000080 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_BITN 7 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M 0x00000080 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S 7 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD 0x00000080 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_BITN 7 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M 0x00000080 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S 7 // Field: [6:5] STANDBY_PW_SEL_EXT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_W 2 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M 0x00000060 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S 5 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M 0x00000060 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S 5 // Field: [4] DIS_STANDBY_EXT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD 0x00000010 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_BITN 4 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M 0x00000010 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_S 4 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD 0x00000010 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_BITN 4 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M 0x00000010 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_S 4 // Field: [3] DIS_IDLE_EXT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD 0x00000008 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_BITN 3 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M 0x00000008 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S 3 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD 0x00000008 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_BITN 3 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M 0x00000008 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S 3 // Field: [2:0] VIN_AT_X_EXT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_W 3 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M 0x00000007 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S 0 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M 0x00000007 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S 0 //***************************************************************************** // @@ -1936,24 +1936,24 @@ // Field: [16:12] TRIM_RECHARGE_COMP_OFFSET // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_W 5 -#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_M 0x0001F000 -#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_S 12 +#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_W 5 +#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_M 0x0001F000 +#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_S 12 // Field: [11:8] TRIM_RECHARGE_COMP_REFLEVEL // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_W 4 -#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_M 0x00000F00 -#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_S 8 +#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_W 4 +#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_M 0x00000F00 +#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_S 8 // Field: [7:0] TEMPVSLOPE // // Signed byte value representing the TEMP slope with battery voltage, in // degrees C / V, with four fractional bits. -#define FCFG1_MISC_TRIM_TEMPVSLOPE_W 8 -#define FCFG1_MISC_TRIM_TEMPVSLOPE_M 0x000000FF -#define FCFG1_MISC_TRIM_TEMPVSLOPE_S 0 +#define FCFG1_MISC_TRIM_TEMPVSLOPE_W 8 +#define FCFG1_MISC_TRIM_TEMPVSLOPE_M 0x000000FF +#define FCFG1_MISC_TRIM_TEMPVSLOPE_S 0 //***************************************************************************** // @@ -1963,30 +1963,30 @@ // Field: [31:24] FINE_RESISTOR // // Internal. Only to be used through TI provided API. -#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_W 8 -#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_M 0xFF000000 -#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_S 24 +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_M 0xFF000000 +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_S 24 // Field: [23:16] CTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_W 8 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_M 0x00FF0000 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_S 16 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_M 0x00FF0000 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_S 16 // Field: [15:8] CTRIMFRACT_QUAD // // Internal. Only to be used through TI provided API. -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_W 8 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_M 0x0000FF00 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_S 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_M 0x0000FF00 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_S 8 // Field: [7:0] CTRIMFRACT_SLOPE // // Internal. Only to be used through TI provided API. -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_W 8 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_M 0x000000FF -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_S 0 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_M 0x000000FF +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_S 0 //***************************************************************************** // @@ -1996,25 +1996,25 @@ // Field: [31:28] PG_REV // // Field used to distinguish revisions of the device. -#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_W 4 -#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_M 0xF0000000 -#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_S 28 +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_W 4 +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_M 0xF0000000 +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_S 28 // Field: [27:12] WAFER_ID // // Field used to identify silicon die. -#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_W 16 -#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M 0x0FFFF000 -#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S 12 +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_W 16 +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M 0x0FFFF000 +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S 12 // Field: [11:0] MANUFACTURER_ID // // Manufacturer code. // // 0x02F: Texas Instruments -#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_W 12 -#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_M 0x00000FFF -#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_S 0 +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_W 12 +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_M 0x00000FFF +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_S 0 //***************************************************************************** // @@ -2029,9 +2029,9 @@ // to be produced if the FCFG1 layout has changed since the previous production // of devices. // Value migth change without warning. -#define FCFG1_FCFG1_REVISION_REV_W 32 -#define FCFG1_FCFG1_REVISION_REV_M 0xFFFFFFFF -#define FCFG1_FCFG1_REVISION_REV_S 0 +#define FCFG1_FCFG1_REVISION_REV_W 32 +#define FCFG1_FCFG1_REVISION_REV_M 0xFFFFFFFF +#define FCFG1_FCFG1_REVISION_REV_S 0 //***************************************************************************** // @@ -2041,30 +2041,30 @@ // Field: [31:28] RCOSC_HF_ITUNE // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_W 4 -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_M 0xF0000000 -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_S 28 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_W 4 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_M 0xF0000000 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_S 28 // Field: [27:20] RCOSC_HF_CRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_W 8 -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_M 0x0FF00000 -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_S 20 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_W 8 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_M 0x0FF00000 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_S 20 // Field: [19:15] PER_M // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_PER_M_W 5 -#define FCFG1_MISC_OTP_DATA_PER_M_M 0x000F8000 -#define FCFG1_MISC_OTP_DATA_PER_M_S 15 +#define FCFG1_MISC_OTP_DATA_PER_M_W 5 +#define FCFG1_MISC_OTP_DATA_PER_M_M 0x000F8000 +#define FCFG1_MISC_OTP_DATA_PER_M_S 15 // Field: [14:12] PER_E // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_PER_E_W 3 -#define FCFG1_MISC_OTP_DATA_PER_E_M 0x00007000 -#define FCFG1_MISC_OTP_DATA_PER_E_S 12 +#define FCFG1_MISC_OTP_DATA_PER_E_W 3 +#define FCFG1_MISC_OTP_DATA_PER_E_M 0x00007000 +#define FCFG1_MISC_OTP_DATA_PER_E_S 12 //***************************************************************************** // @@ -2074,9 +2074,9 @@ // Field: [6:0] GPIO_CNT // // Number of available DIOs. -#define FCFG1_IOCONF_GPIO_CNT_W 7 -#define FCFG1_IOCONF_GPIO_CNT_M 0x0000007F -#define FCFG1_IOCONF_GPIO_CNT_S 0 +#define FCFG1_IOCONF_GPIO_CNT_W 7 +#define FCFG1_IOCONF_GPIO_CNT_M 0x0000007F +#define FCFG1_IOCONF_GPIO_CNT_S 0 //***************************************************************************** // @@ -2086,58 +2086,58 @@ // Field: [31:28] FF2ADJ // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_FF2ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_FF2ADJ_M 0xF0000000 -#define FCFG1_CONFIG_IF_ADC_FF2ADJ_S 28 +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_M 0xF0000000 +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_S 28 // Field: [27:24] FF3ADJ // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_FF3ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_FF3ADJ_M 0x0F000000 -#define FCFG1_CONFIG_IF_ADC_FF3ADJ_S 24 +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_M 0x0F000000 +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_S 24 // Field: [23:20] INT3ADJ // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_INT3ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_INT3ADJ_M 0x00F00000 -#define FCFG1_CONFIG_IF_ADC_INT3ADJ_S 20 +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_M 0x00F00000 +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_S 20 // Field: [19:16] FF1ADJ // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_FF1ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_FF1ADJ_M 0x000F0000 -#define FCFG1_CONFIG_IF_ADC_FF1ADJ_S 16 +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_M 0x000F0000 +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_S 16 // Field: [15:14] AAFCAP // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_AAFCAP_W 2 -#define FCFG1_CONFIG_IF_ADC_AAFCAP_M 0x0000C000 -#define FCFG1_CONFIG_IF_ADC_AAFCAP_S 14 +#define FCFG1_CONFIG_IF_ADC_AAFCAP_W 2 +#define FCFG1_CONFIG_IF_ADC_AAFCAP_M 0x0000C000 +#define FCFG1_CONFIG_IF_ADC_AAFCAP_S 14 // Field: [13:10] INT2ADJ // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_INT2ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_INT2ADJ_M 0x00003C00 -#define FCFG1_CONFIG_IF_ADC_INT2ADJ_S 10 +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_M 0x00003C00 +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_S 10 // Field: [9:5] IFDIGLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_W 5 -#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_M 0x000003E0 -#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_S 5 +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_W 5 +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_M 0x000003E0 +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_S 5 // Field: [4:0] IFANALDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_W 5 -#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_M 0x0000001F -#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_W 5 +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_M 0x0000001F +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -2147,30 +2147,30 @@ // Field: [29:26] XOSC_HF_ROW_Q12 // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_W 4 -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M 0x3C000000 -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S 26 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_W 4 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M 0x3C000000 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S 26 // Field: [25:10] XOSC_HF_COLUMN_Q12 // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_W 16 -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M 0x03FFFC00 -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S 10 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_W 16 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M 0x03FFFC00 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S 10 // Field: [9:2] RCOSCLF_CTUNE_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_W 8 -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M 0x000003FC -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S 2 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_W 8 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M 0x000003FC +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S 2 // Field: [1:0] RCOSCLF_RTUNE_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_W 2 -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M 0x00000003 -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S 0 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_W 2 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M 0x00000003 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S 0 //***************************************************************************** // @@ -2181,9 +2181,9 @@ // // SOC_ADC gain in absolute reference mode at temperature 1 (30C). Calculated // in production test.. -#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_W 16 -#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M 0x0000FFFF -#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S 0 +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_W 16 +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M 0x0000FFFF +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S 0 //***************************************************************************** // @@ -2194,9 +2194,9 @@ // // SOC_ADC gain in relative reference mode at temperature 1 (30C). Calculated // in production test.. -#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_W 16 -#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M 0x0000FFFF -#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S 0 +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_W 16 +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M 0x0000FFFF +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S 0 //***************************************************************************** // @@ -2207,17 +2207,17 @@ // // SOC_ADC offset in relative reference mode at temperature 1 (30C). Signed // 8-bit number. Calculated in production test.. -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_W 8 -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_M 0x00FF0000 -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S 16 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_W 8 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_M 0x00FF0000 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S 16 // Field: [7:0] SOC_ADC_ABS_OFFSET_TEMP1 // // SOC_ADC offset in absolute reference mode at temperature 1 (30C). Signed // 8-bit number. Calculated in production test.. -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_W 8 -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_M 0x000000FF -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S 0 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_W 8 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_M 0x000000FF +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S 0 //***************************************************************************** // @@ -2242,30 +2242,30 @@ // Field: [23:18] HPMRAMP3_LTH // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_W 6 -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M 0x00FC0000 -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S 18 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M 0x00FC0000 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S 18 // Field: [15:10] HPMRAMP3_HTH // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_W 6 -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M 0x0000FC00 -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S 10 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M 0x0000FC00 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S 10 // Field: [9:6] IBIASCAP_LPTOHP_OL_CNT // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_W 4 -#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 -#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S 6 +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_W 4 +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S 6 // Field: [5:0] HPMRAMP1_TH // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_W 6 -#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M 0x0000003F -#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S 0 +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M 0x0000003F +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S 0 //***************************************************************************** // @@ -2275,30 +2275,30 @@ // Field: [31:26] LPMUPDATE_LTH // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_W 6 -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M 0xFC000000 -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S 26 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_W 6 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M 0xFC000000 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S 26 // Field: [23:18] LPMUPDATE_HTM // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_W 6 -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M 0x00FC0000 -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S 18 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_W 6 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M 0x00FC0000 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S 18 // Field: [15:10] ADC_COMP_AMPTH_LPM // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_W 6 -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S 10 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_W 6 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S 10 // Field: [7:2] ADC_COMP_AMPTH_HPM // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_W 6 -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M 0x000000FC -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S 2 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_W 6 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M 0x000000FC +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S 2 //***************************************************************************** // @@ -2308,45 +2308,45 @@ // Field: [30] AMPCOMP_REQ_MODE // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE 0x40000000 -#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_BITN 30 -#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M 0x40000000 -#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S 30 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE 0x40000000 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_BITN 30 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M 0x40000000 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S 30 // Field: [23:20] IBIAS_OFFSET // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_W 4 -#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M 0x00F00000 -#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S 20 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M 0x00F00000 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S 20 // Field: [19:16] IBIAS_INIT // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_W 4 -#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M 0x000F0000 -#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S 16 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M 0x000F0000 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S 16 // Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_W 8 -#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 -#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S 8 +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_W 8 +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S 8 // Field: [7:4] CAP_STEP // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_W 4 -#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_M 0x000000F0 -#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_S 4 +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_W 4 +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_M 0x000000F0 +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_S 4 // Field: [3:0] IBIASCAP_HPTOLP_OL_CNT // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_W 4 -#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F -#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S 0 +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S 0 //***************************************************************************** // @@ -2356,9 +2356,9 @@ // Field: [13:0] XOSC_HF_IBIASTHERM // // Internal. Only to be used through TI provided API. -#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_W 14 -#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M 0x00003FFF -#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S 0 +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_W 14 +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M 0x00003FFF +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S 0 //***************************************************************************** // @@ -2368,30 +2368,30 @@ // Field: [28:24] VDDR_TRIM_HH // // Internal. Only to be used through TI provided API. -#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_W 5 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M 0x1F000000 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S 24 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M 0x1F000000 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S 24 // Field: [20:16] VDDR_TRIM_H // // Internal. Only to be used through TI provided API. -#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_W 5 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_M 0x001F0000 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_S 16 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_M 0x001F0000 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_S 16 // Field: [12:8] VDDR_TRIM_SLEEP_H // // Internal. Only to be used through TI provided API. -#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_W 5 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_M 0x00001F00 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_S 8 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_M 0x00001F00 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_S 8 // Field: [4:0] TRIMBOD_H // // Internal. Only to be used through TI provided API. -#define FCFG1_VOLT_TRIM_TRIMBOD_H_W 5 -#define FCFG1_VOLT_TRIM_TRIMBOD_H_M 0x0000001F -#define FCFG1_VOLT_TRIM_TRIMBOD_H_S 0 +#define FCFG1_VOLT_TRIM_TRIMBOD_H_W 5 +#define FCFG1_VOLT_TRIM_TRIMBOD_H_M 0x0000001F +#define FCFG1_VOLT_TRIM_TRIMBOD_H_S 0 //***************************************************************************** // @@ -2401,116 +2401,116 @@ // Field: [29] ADC_SH_VBUF_EN // // Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN. -#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN 0x20000000 -#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_BITN 29 -#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M 0x20000000 -#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S 29 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN 0x20000000 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_BITN 29 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M 0x20000000 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S 29 // Field: [28] ADC_SH_MODE_EN // // Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN. -#define FCFG1_OSC_CONF_ADC_SH_MODE_EN 0x10000000 -#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_BITN 28 -#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_M 0x10000000 -#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_S 28 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN 0x10000000 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_BITN 28 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_M 0x10000000 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_S 28 // Field: [27] ATESTLF_RCOSCLF_IBIAS_TRIM // // Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM. -#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM 0x08000000 -#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_BITN 27 -#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M 0x08000000 -#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S 27 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM 0x08000000 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_BITN 27 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M 0x08000000 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S 27 // Field: [26:25] XOSCLF_REGULATOR_TRIM // // Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM. -#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_W 2 -#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M 0x06000000 -#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_S 25 +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_W 2 +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M 0x06000000 +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_S 25 // Field: [24:21] XOSCLF_CMIRRWR_RATIO // // Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO. -#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_W 4 -#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M 0x01E00000 -#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S 21 +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_W 4 +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M 0x01E00000 +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S 21 // Field: [20:19] XOSC_HF_FAST_START // // Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START. -#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_W 2 -#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_M 0x00180000 -#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_S 19 +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_W 2 +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_M 0x00180000 +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_S 19 // Field: [18] XOSC_OPTION // // 0: XOSC_HF unavailable (may not be bonded out) // 1: XOSC_HF available (default) -#define FCFG1_OSC_CONF_XOSC_OPTION 0x00040000 -#define FCFG1_OSC_CONF_XOSC_OPTION_BITN 18 -#define FCFG1_OSC_CONF_XOSC_OPTION_M 0x00040000 -#define FCFG1_OSC_CONF_XOSC_OPTION_S 18 +#define FCFG1_OSC_CONF_XOSC_OPTION 0x00040000 +#define FCFG1_OSC_CONF_XOSC_OPTION_BITN 18 +#define FCFG1_OSC_CONF_XOSC_OPTION_M 0x00040000 +#define FCFG1_OSC_CONF_XOSC_OPTION_S 18 // Field: [17] HPOSC_OPTION // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_OPTION 0x00020000 -#define FCFG1_OSC_CONF_HPOSC_OPTION_BITN 17 -#define FCFG1_OSC_CONF_HPOSC_OPTION_M 0x00020000 -#define FCFG1_OSC_CONF_HPOSC_OPTION_S 17 +#define FCFG1_OSC_CONF_HPOSC_OPTION 0x00020000 +#define FCFG1_OSC_CONF_HPOSC_OPTION_BITN 17 +#define FCFG1_OSC_CONF_HPOSC_OPTION_M 0x00020000 +#define FCFG1_OSC_CONF_HPOSC_OPTION_S 17 // Field: [16] HPOSC_BIAS_HOLD_MODE_EN // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN 0x00010000 -#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_BITN 16 -#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M 0x00010000 -#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S 16 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN 0x00010000 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_BITN 16 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M 0x00010000 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S 16 // Field: [15:12] HPOSC_CURRMIRR_RATIO // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_W 4 -#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M 0x0000F000 -#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S 12 +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_W 4 +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M 0x0000F000 +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S 12 // Field: [11:8] HPOSC_BIAS_RES_SET // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_W 4 -#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M 0x00000F00 -#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S 8 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_W 4 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M 0x00000F00 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S 8 // Field: [7] HPOSC_FILTER_EN // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_FILTER_EN 0x00000080 -#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_BITN 7 -#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_M 0x00000080 -#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_S 7 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN 0x00000080 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_BITN 7 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_M 0x00000080 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_S 7 // Field: [6:5] HPOSC_BIAS_RECHARGE_DELAY // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_W 2 -#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M 0x00000060 -#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S 5 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_W 2 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M 0x00000060 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S 5 // Field: [2:1] HPOSC_SERIES_CAP // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_W 2 -#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M 0x00000006 -#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S 1 +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_W 2 +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M 0x00000006 +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S 1 // Field: [0] HPOSC_DIV3_BYPASS // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS 0x00000001 -#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_BITN 0 -#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M 0x00000001 -#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S 0 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS 0x00000001 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_BITN 0 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M 0x00000001 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S 0 //***************************************************************************** // @@ -2520,23 +2520,23 @@ // Field: [31:16] HPOSC_COMP_P0 // // Internal. Only to be used through TI provided API. -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W 16 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_M 0xFFFF0000 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S 16 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W 16 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_M 0xFFFF0000 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S 16 // Field: [15:8] HPOSC_COMP_P1 // // Internal. Only to be used through TI provided API. -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W 8 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_M 0x0000FF00 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S 8 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W 8 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_M 0x0000FF00 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S 8 // Field: [7:0] HPOSC_COMP_P2 // // Internal. Only to be used through TI provided API. -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W 8 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_M 0x000000FF -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S 0 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W 8 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_M 0x000000FF +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S 0 //***************************************************************************** // @@ -2546,51 +2546,51 @@ // Field: [28:27] PEAK_DET_ITRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_W 2 -#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M 0x18000000 -#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S 27 +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_W 2 +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M 0x18000000 +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S 27 // Field: [26:24] HP_BUF_ITRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_W 3 -#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M 0x07000000 -#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S 24 +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_W 3 +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M 0x07000000 +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S 24 // Field: [23:22] LP_BUF_ITRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_W 2 -#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M 0x00C00000 -#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S 22 +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_W 2 +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M 0x00C00000 +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S 22 // Field: [21:20] DBLR_LOOP_FILTER_RESET_VOLTAGE // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_W 2 -#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M 0x00300000 -#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S 20 +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_W 2 +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M 0x00300000 +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S 20 // Field: [19:10] HPM_IBIAS_WAIT_CNT // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_W 10 -#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M 0x000FFC00 -#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S 10 +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_W 10 +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M 0x000FFC00 +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S 10 // Field: [9:4] LPM_IBIAS_WAIT_CNT // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_W 6 -#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M 0x000003F0 -#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S 4 +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_W 6 +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M 0x000003F0 +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S 4 // Field: [3:0] IDAC_STEP // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_W 4 -#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M 0x0000000F -#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S 0 +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_W 4 +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M 0x0000000F +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S 0 //***************************************************************************** // @@ -2600,9 +2600,9 @@ // Field: [31:0] ID_31_0 // // Shadow of DIE_ID_0 register in eFuse row number 5 -#define FCFG1_SHDW_DIE_ID_0_ID_31_0_W 32 -#define FCFG1_SHDW_DIE_ID_0_ID_31_0_M 0xFFFFFFFF -#define FCFG1_SHDW_DIE_ID_0_ID_31_0_S 0 +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_W 32 +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_S 0 //***************************************************************************** // @@ -2612,9 +2612,9 @@ // Field: [31:0] ID_63_32 // // Shadow of DIE_ID_1 register in eFuse row number 6 -#define FCFG1_SHDW_DIE_ID_1_ID_63_32_W 32 -#define FCFG1_SHDW_DIE_ID_1_ID_63_32_M 0xFFFFFFFF -#define FCFG1_SHDW_DIE_ID_1_ID_63_32_S 0 +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_W 32 +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_S 0 //***************************************************************************** // @@ -2624,9 +2624,9 @@ // Field: [31:0] ID_95_64 // // Shadow of DIE_ID_2 register in eFuse row number 7 -#define FCFG1_SHDW_DIE_ID_2_ID_95_64_W 32 -#define FCFG1_SHDW_DIE_ID_2_ID_95_64_M 0xFFFFFFFF -#define FCFG1_SHDW_DIE_ID_2_ID_95_64_S 0 +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_W 32 +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_S 0 //***************************************************************************** // @@ -2636,9 +2636,9 @@ // Field: [31:0] ID_127_96 // // Shadow of DIE_ID_3 register in eFuse row number 8 -#define FCFG1_SHDW_DIE_ID_3_ID_127_96_W 32 -#define FCFG1_SHDW_DIE_ID_3_ID_127_96_M 0xFFFFFFFF -#define FCFG1_SHDW_DIE_ID_3_ID_127_96_S 0 +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_W 32 +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_S 0 //***************************************************************************** // @@ -2648,44 +2648,44 @@ // Field: [26:23] TRIMMAG // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_W 4 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_M 0x07800000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_S 23 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_M 0x07800000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_S 23 // Field: [22:18] TRIMIREF // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_W 5 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_M 0x007C0000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_S 18 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_W 5 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_M 0x007C0000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_S 18 // Field: [17:16] ITRIM_DIG_LDO // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_W 2 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_M 0x00030000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_S 16 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_W 2 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_M 0x00030000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_S 16 // Field: [15:12] VTRIM_DIG // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_W 4 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_M 0x0000F000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_S 12 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_M 0x0000F000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_S 12 // Field: [11:8] VTRIM_COARSE // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_W 4 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_M 0x00000F00 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_S 8 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_M 0x00000F00 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_S 8 // Field: [7:0] RCOSCHF_CTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_W 8 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M 0x000000FF -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S 0 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_W 8 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M 0x000000FF +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S 0 //***************************************************************************** // @@ -2695,83 +2695,83 @@ // Field: [30] ALT_VDDR_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM 0x40000000 -#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_BITN 30 -#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_M 0x40000000 -#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_S 30 +#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM 0x40000000 +#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_BITN 30 +#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_M 0x40000000 +#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_S 30 // Field: [29] DET_LOGIC_DIS // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS 0x20000000 -#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_BITN 29 -#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_M 0x20000000 -#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_S 29 +#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS 0x20000000 +#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_BITN 29 +#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_M 0x20000000 +#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_S 29 // Field: [28:27] BOD_BANDGAP_TRIM_CNF_EXT // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_W 2 -#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_M 0x18000000 -#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_S 27 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_W 2 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_M 0x18000000 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_S 27 // Field: [26:25] BOD_BANDGAP_TRIM_CNF // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_W 2 -#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_M 0x06000000 -#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_S 25 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_W 2 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_M 0x06000000 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_S 25 // Field: [24] VDDR_ENABLE_PG1 // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1 0x01000000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_BITN 24 -#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_M 0x01000000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_S 24 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1 0x01000000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_BITN 24 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_M 0x01000000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_S 24 // Field: [23] VDDR_OK_HYS // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS 0x00800000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_BITN 23 -#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_M 0x00800000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_S 23 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS 0x00800000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_BITN 23 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_M 0x00800000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_S 23 // Field: [22:21] IPTAT_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_W 2 -#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_M 0x00600000 -#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_S 21 +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_W 2 +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_M 0x00600000 +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_S 21 // Field: [20:16] VDDR_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_W 5 -#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M 0x001F0000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S 16 +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_W 5 +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M 0x001F0000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S 16 // Field: [15:11] TRIMBOD_INTMODE // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_W 5 -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_M 0x0000F800 -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_S 11 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_W 5 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_M 0x0000F800 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_S 11 // Field: [10:6] TRIMBOD_EXTMODE // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_W 5 -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_M 0x000007C0 -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_S 6 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_W 5 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_M 0x000007C0 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_S 6 // Field: [5:0] TRIMTEMP // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W 6 -#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_M 0x0000003F -#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_S 0 +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W 6 +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_M 0x0000003F +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_S 0 //***************************************************************************** // @@ -2781,24 +2781,24 @@ // Field: [17:12] LPM_TRIM_IOUT // // Internal. Only to be used through TI provided API. -#define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_W 6 -#define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_M 0x0003F000 -#define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_S 12 +#define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_W 6 +#define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_M 0x0003F000 +#define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_S 12 // Field: [11:9] LPM_BIAS_WIDTH_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_W 3 -#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_M 0x00000E00 -#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_S 9 +#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_W 3 +#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_M 0x00000E00 +#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_S 9 // Field: [8] LPM_BIAS_BACKUP_EN // // Internal. Only to be used through TI provided API. -#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN 0x00000100 -#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_BITN 8 -#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_M 0x00000100 -#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_S 8 +#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN 0x00000100 +#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_BITN 8 +#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_M 0x00000100 +#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_S 8 //***************************************************************************** // @@ -2808,9 +2808,9 @@ // Field: [31:0] REV // // Internal. Only to be used through TI provided API. -#define FCFG1_TFW_PROBE_REV_W 32 -#define FCFG1_TFW_PROBE_REV_M 0xFFFFFFFF -#define FCFG1_TFW_PROBE_REV_S 0 +#define FCFG1_TFW_PROBE_REV_W 32 +#define FCFG1_TFW_PROBE_REV_M 0xFFFFFFFF +#define FCFG1_TFW_PROBE_REV_S 0 //***************************************************************************** // @@ -2820,9 +2820,9 @@ // Field: [31:0] REV // // Internal. Only to be used through TI provided API. -#define FCFG1_TFW_FT_REV_W 32 -#define FCFG1_TFW_FT_REV_M 0xFFFFFFFF -#define FCFG1_TFW_FT_REV_S 0 +#define FCFG1_TFW_FT_REV_W 32 +#define FCFG1_TFW_FT_REV_M 0xFFFFFFFF +#define FCFG1_TFW_FT_REV_S 0 //***************************************************************************** // @@ -2832,16 +2832,16 @@ // Field: [31:16] SOC_DAC_VOUT_CAL_DECOUPLE_C2 // // Internal. Only to be used through TI provided API. -#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_W 16 -#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_M 0xFFFF0000 -#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_S 16 +#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_W 16 +#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_M 0xFFFF0000 +#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_S 16 // Field: [15:0] SOC_DAC_VOUT_CAL_DECOUPLE_C1 // // Internal. Only to be used through TI provided API. -#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_W 16 -#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_M 0x0000FFFF -#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_S 0 +#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_W 16 +#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_M 0x0000FFFF +#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_S 0 //***************************************************************************** // @@ -2851,16 +2851,16 @@ // Field: [31:16] SOC_DAC_VOUT_CAL_PRECH_C2 // // Internal. Only to be used through TI provided API. -#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_W 16 -#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_M 0xFFFF0000 -#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_S 16 +#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_W 16 +#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_M 0xFFFF0000 +#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_S 16 // Field: [15:0] SOC_DAC_VOUT_CAL_PRECH_C1 // // Internal. Only to be used through TI provided API. -#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_W 16 -#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_M 0x0000FFFF -#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_S 0 +#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_W 16 +#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_M 0x0000FFFF +#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_S 0 //***************************************************************************** // @@ -2870,16 +2870,16 @@ // Field: [31:16] SOC_DAC_VOUT_CAL_ADCREF_C2 // // Internal. Only to be used through TI provided API. -#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_W 16 -#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_M 0xFFFF0000 -#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_S 16 +#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_W 16 +#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_M 0xFFFF0000 +#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_S 16 // Field: [15:0] SOC_DAC_VOUT_CAL_ADCREF_C1 // // Internal. Only to be used through TI provided API. -#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_W 16 -#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_M 0x0000FFFF -#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_S 0 +#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_W 16 +#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_M 0x0000FFFF +#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_S 0 //***************************************************************************** // @@ -2889,16 +2889,15 @@ // Field: [31:16] SOC_DAC_VOUT_CAL_VDDS_C2 // // Internal. Only to be used through TI provided API. -#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_W 16 -#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_M 0xFFFF0000 -#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_S 16 +#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_W 16 +#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_M 0xFFFF0000 +#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_S 16 // Field: [15:0] SOC_DAC_VOUT_CAL_VDDS_C1 // // Internal. Only to be used through TI provided API. -#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_W 16 -#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_M 0x0000FFFF -#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_S 0 - +#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_W 16 +#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_M 0x0000FFFF +#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_S 0 #endif // __FCFG1__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_flash.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_flash.h index cfc45cb..e66929d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_flash.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_flash.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_flash_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_flash_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_FLASH_H__ #define __HW_FLASH_H__ @@ -44,376 +44,376 @@ // //***************************************************************************** // FMC and Efuse Status -#define FLASH_O_STAT 0x0000001C +#define FLASH_O_STAT 0x0000001C // Internal -#define FLASH_O_CFG 0x00000024 +#define FLASH_O_CFG 0x00000024 // Internal -#define FLASH_O_SYSCODE_START 0x00000028 +#define FLASH_O_SYSCODE_START 0x00000028 // Internal -#define FLASH_O_FLASH_SIZE 0x0000002C +#define FLASH_O_FLASH_SIZE 0x0000002C // Internal -#define FLASH_O_FWLOCK 0x0000003C +#define FLASH_O_FWLOCK 0x0000003C // Internal -#define FLASH_O_FWFLAG 0x00000040 +#define FLASH_O_FWFLAG 0x00000040 // Internal -#define FLASH_O_EFUSE 0x00001000 +#define FLASH_O_EFUSE 0x00001000 // Internal -#define FLASH_O_EFUSEADDR 0x00001004 +#define FLASH_O_EFUSEADDR 0x00001004 // Internal -#define FLASH_O_DATAUPPER 0x00001008 +#define FLASH_O_DATAUPPER 0x00001008 // Internal -#define FLASH_O_DATALOWER 0x0000100C +#define FLASH_O_DATALOWER 0x0000100C // Internal -#define FLASH_O_EFUSECFG 0x00001010 +#define FLASH_O_EFUSECFG 0x00001010 // Internal -#define FLASH_O_EFUSESTAT 0x00001014 +#define FLASH_O_EFUSESTAT 0x00001014 // Internal -#define FLASH_O_ACC 0x00001018 +#define FLASH_O_ACC 0x00001018 // Internal -#define FLASH_O_BOUNDARY 0x0000101C +#define FLASH_O_BOUNDARY 0x0000101C // Internal -#define FLASH_O_EFUSEFLAG 0x00001020 +#define FLASH_O_EFUSEFLAG 0x00001020 // Internal -#define FLASH_O_EFUSEKEY 0x00001024 +#define FLASH_O_EFUSEKEY 0x00001024 // Internal -#define FLASH_O_EFUSERELEASE 0x00001028 +#define FLASH_O_EFUSERELEASE 0x00001028 // Internal -#define FLASH_O_EFUSEPINS 0x0000102C +#define FLASH_O_EFUSEPINS 0x0000102C // Internal -#define FLASH_O_EFUSECRA 0x00001030 +#define FLASH_O_EFUSECRA 0x00001030 // Internal -#define FLASH_O_EFUSEREAD 0x00001034 +#define FLASH_O_EFUSEREAD 0x00001034 // Internal -#define FLASH_O_EFUSEPROGRAM 0x00001038 +#define FLASH_O_EFUSEPROGRAM 0x00001038 // Internal -#define FLASH_O_EFUSEERROR 0x0000103C +#define FLASH_O_EFUSEERROR 0x0000103C // Internal -#define FLASH_O_SINGLEBIT 0x00001040 +#define FLASH_O_SINGLEBIT 0x00001040 // Internal -#define FLASH_O_TWOBIT 0x00001044 +#define FLASH_O_TWOBIT 0x00001044 // Internal -#define FLASH_O_SELFTESTCYC 0x00001048 +#define FLASH_O_SELFTESTCYC 0x00001048 // Internal -#define FLASH_O_SELFTESTSIGN 0x0000104C +#define FLASH_O_SELFTESTSIGN 0x0000104C // Internal -#define FLASH_O_FRDCTL 0x00002000 +#define FLASH_O_FRDCTL 0x00002000 // Internal -#define FLASH_O_FSPRD 0x00002004 +#define FLASH_O_FSPRD 0x00002004 // Internal -#define FLASH_O_FEDACCTL1 0x00002008 +#define FLASH_O_FEDACCTL1 0x00002008 // Internal -#define FLASH_O_FEDACSTAT 0x0000201C +#define FLASH_O_FEDACSTAT 0x0000201C // Internal -#define FLASH_O_FBPROT 0x00002030 +#define FLASH_O_FBPROT 0x00002030 // Internal -#define FLASH_O_FBSE 0x00002034 +#define FLASH_O_FBSE 0x00002034 // Internal -#define FLASH_O_FBBUSY 0x00002038 +#define FLASH_O_FBBUSY 0x00002038 // Internal -#define FLASH_O_FBAC 0x0000203C +#define FLASH_O_FBAC 0x0000203C // Internal -#define FLASH_O_FBFALLBACK 0x00002040 +#define FLASH_O_FBFALLBACK 0x00002040 // Internal -#define FLASH_O_FBPRDY 0x00002044 +#define FLASH_O_FBPRDY 0x00002044 // Internal -#define FLASH_O_FPAC1 0x00002048 +#define FLASH_O_FPAC1 0x00002048 // Internal -#define FLASH_O_FPAC2 0x0000204C +#define FLASH_O_FPAC2 0x0000204C // Internal -#define FLASH_O_FMAC 0x00002050 +#define FLASH_O_FMAC 0x00002050 // Internal -#define FLASH_O_FMSTAT 0x00002054 +#define FLASH_O_FMSTAT 0x00002054 // Internal -#define FLASH_O_FLOCK 0x00002064 +#define FLASH_O_FLOCK 0x00002064 // Internal -#define FLASH_O_FVREADCT 0x00002080 +#define FLASH_O_FVREADCT 0x00002080 // Internal -#define FLASH_O_FVHVCT1 0x00002084 +#define FLASH_O_FVHVCT1 0x00002084 // Internal -#define FLASH_O_FVHVCT2 0x00002088 +#define FLASH_O_FVHVCT2 0x00002088 // Internal -#define FLASH_O_FVHVCT3 0x0000208C +#define FLASH_O_FVHVCT3 0x0000208C // Internal -#define FLASH_O_FVNVCT 0x00002090 +#define FLASH_O_FVNVCT 0x00002090 // Internal -#define FLASH_O_FVSLP 0x00002094 +#define FLASH_O_FVSLP 0x00002094 // Internal -#define FLASH_O_FVWLCT 0x00002098 +#define FLASH_O_FVWLCT 0x00002098 // Internal -#define FLASH_O_FEFUSECTL 0x0000209C +#define FLASH_O_FEFUSECTL 0x0000209C // Internal -#define FLASH_O_FEFUSESTAT 0x000020A0 +#define FLASH_O_FEFUSESTAT 0x000020A0 // Internal -#define FLASH_O_FEFUSEDATA 0x000020A4 +#define FLASH_O_FEFUSEDATA 0x000020A4 // Internal -#define FLASH_O_FSEQPMP 0x000020A8 +#define FLASH_O_FSEQPMP 0x000020A8 // Internal -#define FLASH_O_FBSTROBES 0x00002100 +#define FLASH_O_FBSTROBES 0x00002100 // Internal -#define FLASH_O_FPSTROBES 0x00002104 +#define FLASH_O_FPSTROBES 0x00002104 // Internal -#define FLASH_O_FBMODE 0x00002108 +#define FLASH_O_FBMODE 0x00002108 // Internal -#define FLASH_O_FTCR 0x0000210C +#define FLASH_O_FTCR 0x0000210C // Internal -#define FLASH_O_FADDR 0x00002110 +#define FLASH_O_FADDR 0x00002110 // Internal -#define FLASH_O_FTCTL 0x0000211C +#define FLASH_O_FTCTL 0x0000211C // Internal -#define FLASH_O_FWPWRITE0 0x00002120 +#define FLASH_O_FWPWRITE0 0x00002120 // Internal -#define FLASH_O_FWPWRITE1 0x00002124 +#define FLASH_O_FWPWRITE1 0x00002124 // Internal -#define FLASH_O_FWPWRITE2 0x00002128 +#define FLASH_O_FWPWRITE2 0x00002128 // Internal -#define FLASH_O_FWPWRITE3 0x0000212C +#define FLASH_O_FWPWRITE3 0x0000212C // Internal -#define FLASH_O_FWPWRITE4 0x00002130 +#define FLASH_O_FWPWRITE4 0x00002130 // Internal -#define FLASH_O_FWPWRITE5 0x00002134 +#define FLASH_O_FWPWRITE5 0x00002134 // Internal -#define FLASH_O_FWPWRITE6 0x00002138 +#define FLASH_O_FWPWRITE6 0x00002138 // Internal -#define FLASH_O_FWPWRITE7 0x0000213C +#define FLASH_O_FWPWRITE7 0x0000213C // Internal -#define FLASH_O_FWPWRITE_ECC 0x00002140 +#define FLASH_O_FWPWRITE_ECC 0x00002140 // Internal -#define FLASH_O_FSWSTAT 0x00002144 +#define FLASH_O_FSWSTAT 0x00002144 // Internal -#define FLASH_O_FSM_GLBCTL 0x00002200 +#define FLASH_O_FSM_GLBCTL 0x00002200 // Internal -#define FLASH_O_FSM_STATE 0x00002204 +#define FLASH_O_FSM_STATE 0x00002204 // Internal -#define FLASH_O_FSM_STAT 0x00002208 +#define FLASH_O_FSM_STAT 0x00002208 // Internal -#define FLASH_O_FSM_CMD 0x0000220C +#define FLASH_O_FSM_CMD 0x0000220C // Internal -#define FLASH_O_FSM_PE_OSU 0x00002210 +#define FLASH_O_FSM_PE_OSU 0x00002210 // Internal -#define FLASH_O_FSM_VSTAT 0x00002214 +#define FLASH_O_FSM_VSTAT 0x00002214 // Internal -#define FLASH_O_FSM_PE_VSU 0x00002218 +#define FLASH_O_FSM_PE_VSU 0x00002218 // Internal -#define FLASH_O_FSM_CMP_VSU 0x0000221C +#define FLASH_O_FSM_CMP_VSU 0x0000221C // Internal -#define FLASH_O_FSM_EX_VAL 0x00002220 +#define FLASH_O_FSM_EX_VAL 0x00002220 // Internal -#define FLASH_O_FSM_RD_H 0x00002224 +#define FLASH_O_FSM_RD_H 0x00002224 // Internal -#define FLASH_O_FSM_P_OH 0x00002228 +#define FLASH_O_FSM_P_OH 0x00002228 // Internal -#define FLASH_O_FSM_ERA_OH 0x0000222C +#define FLASH_O_FSM_ERA_OH 0x0000222C // Internal -#define FLASH_O_FSM_SAV_PPUL 0x00002230 +#define FLASH_O_FSM_SAV_PPUL 0x00002230 // Internal -#define FLASH_O_FSM_PE_VH 0x00002234 +#define FLASH_O_FSM_PE_VH 0x00002234 // Internal -#define FLASH_O_FSM_PRG_PW 0x00002240 +#define FLASH_O_FSM_PRG_PW 0x00002240 // Internal -#define FLASH_O_FSM_ERA_PW 0x00002244 +#define FLASH_O_FSM_ERA_PW 0x00002244 // Internal -#define FLASH_O_FSM_SAV_ERA_PUL 0x00002254 +#define FLASH_O_FSM_SAV_ERA_PUL 0x00002254 // Internal -#define FLASH_O_FSM_TIMER 0x00002258 +#define FLASH_O_FSM_TIMER 0x00002258 // Internal -#define FLASH_O_FSM_MODE 0x0000225C +#define FLASH_O_FSM_MODE 0x0000225C // Internal -#define FLASH_O_FSM_PGM 0x00002260 +#define FLASH_O_FSM_PGM 0x00002260 // Internal -#define FLASH_O_FSM_ERA 0x00002264 +#define FLASH_O_FSM_ERA 0x00002264 // Internal -#define FLASH_O_FSM_PRG_PUL 0x00002268 +#define FLASH_O_FSM_PRG_PUL 0x00002268 // Internal -#define FLASH_O_FSM_ERA_PUL 0x0000226C +#define FLASH_O_FSM_ERA_PUL 0x0000226C // Internal -#define FLASH_O_FSM_STEP_SIZE 0x00002270 +#define FLASH_O_FSM_STEP_SIZE 0x00002270 // Internal -#define FLASH_O_FSM_PUL_CNTR 0x00002274 +#define FLASH_O_FSM_PUL_CNTR 0x00002274 // Internal -#define FLASH_O_FSM_EC_STEP_HEIGHT 0x00002278 +#define FLASH_O_FSM_EC_STEP_HEIGHT 0x00002278 // Internal -#define FLASH_O_FSM_ST_MACHINE 0x0000227C +#define FLASH_O_FSM_ST_MACHINE 0x0000227C // Internal -#define FLASH_O_FSM_FLES 0x00002280 +#define FLASH_O_FSM_FLES 0x00002280 // Internal -#define FLASH_O_FSM_WR_ENA 0x00002288 +#define FLASH_O_FSM_WR_ENA 0x00002288 // Internal -#define FLASH_O_FSM_ACC_PP 0x0000228C +#define FLASH_O_FSM_ACC_PP 0x0000228C // Internal -#define FLASH_O_FSM_ACC_EP 0x00002290 +#define FLASH_O_FSM_ACC_EP 0x00002290 // Internal -#define FLASH_O_FSM_ADDR 0x000022A0 +#define FLASH_O_FSM_ADDR 0x000022A0 // Internal -#define FLASH_O_FSM_SECTOR 0x000022A4 +#define FLASH_O_FSM_SECTOR 0x000022A4 // Internal -#define FLASH_O_FMC_REV_ID 0x000022A8 +#define FLASH_O_FMC_REV_ID 0x000022A8 // Internal -#define FLASH_O_FSM_ERR_ADDR 0x000022AC +#define FLASH_O_FSM_ERR_ADDR 0x000022AC // Internal -#define FLASH_O_FSM_PGM_MAXPUL 0x000022B0 +#define FLASH_O_FSM_PGM_MAXPUL 0x000022B0 // Internal -#define FLASH_O_FSM_EXECUTE 0x000022B4 +#define FLASH_O_FSM_EXECUTE 0x000022B4 // Internal -#define FLASH_O_FSM_SECTOR1 0x000022C0 +#define FLASH_O_FSM_SECTOR1 0x000022C0 // Internal -#define FLASH_O_FSM_SECTOR2 0x000022C4 +#define FLASH_O_FSM_SECTOR2 0x000022C4 // Internal -#define FLASH_O_FSM_BSLE0 0x000022E0 +#define FLASH_O_FSM_BSLE0 0x000022E0 // Internal -#define FLASH_O_FSM_BSLE1 0x000022E4 +#define FLASH_O_FSM_BSLE1 0x000022E4 // Internal -#define FLASH_O_FSM_BSLP0 0x000022F0 +#define FLASH_O_FSM_BSLP0 0x000022F0 // Internal -#define FLASH_O_FSM_BSLP1 0x000022F4 +#define FLASH_O_FSM_BSLP1 0x000022F4 // FMC FSM Enable 128-bit Wide Programming -#define FLASH_O_FSM_PGM128 0x000022F8 +#define FLASH_O_FSM_PGM128 0x000022F8 // Internal -#define FLASH_O_FCFG_BANK 0x00002400 +#define FLASH_O_FCFG_BANK 0x00002400 // Internal -#define FLASH_O_FCFG_WRAPPER 0x00002404 +#define FLASH_O_FCFG_WRAPPER 0x00002404 // Internal -#define FLASH_O_FCFG_BNK_TYPE 0x00002408 +#define FLASH_O_FCFG_BNK_TYPE 0x00002408 // Internal -#define FLASH_O_FCFG_B0_START 0x00002410 +#define FLASH_O_FCFG_B0_START 0x00002410 // Internal -#define FLASH_O_FCFG_B1_START 0x00002414 +#define FLASH_O_FCFG_B1_START 0x00002414 // Internal -#define FLASH_O_FCFG_B2_START 0x00002418 +#define FLASH_O_FCFG_B2_START 0x00002418 // Internal -#define FLASH_O_FCFG_B3_START 0x0000241C +#define FLASH_O_FCFG_B3_START 0x0000241C // Internal -#define FLASH_O_FCFG_B4_START 0x00002420 +#define FLASH_O_FCFG_B4_START 0x00002420 // Internal -#define FLASH_O_FCFG_B5_START 0x00002424 +#define FLASH_O_FCFG_B5_START 0x00002424 // Internal -#define FLASH_O_FCFG_B6_START 0x00002428 +#define FLASH_O_FCFG_B6_START 0x00002428 // Internal -#define FLASH_O_FCFG_B7_START 0x0000242C +#define FLASH_O_FCFG_B7_START 0x0000242C // Internal -#define FLASH_O_FCFG_B0_SSIZE0 0x00002430 +#define FLASH_O_FCFG_B0_SSIZE0 0x00002430 //***************************************************************************** // @@ -425,37 +425,37 @@ // Efuse scanning detected if fuse ROM is blank: // 0 : Not blank // 1 : Blank -#define FLASH_STAT_EFUSE_BLANK 0x00008000 -#define FLASH_STAT_EFUSE_BLANK_BITN 15 -#define FLASH_STAT_EFUSE_BLANK_M 0x00008000 -#define FLASH_STAT_EFUSE_BLANK_S 15 +#define FLASH_STAT_EFUSE_BLANK 0x00008000 +#define FLASH_STAT_EFUSE_BLANK_BITN 15 +#define FLASH_STAT_EFUSE_BLANK_M 0x00008000 +#define FLASH_STAT_EFUSE_BLANK_S 15 // Field: [14] EFUSE_TIMEOUT // // Efuse scanning resulted in timeout error. // 0 : No Timeout error // 1 : Timeout Error -#define FLASH_STAT_EFUSE_TIMEOUT 0x00004000 -#define FLASH_STAT_EFUSE_TIMEOUT_BITN 14 -#define FLASH_STAT_EFUSE_TIMEOUT_M 0x00004000 -#define FLASH_STAT_EFUSE_TIMEOUT_S 14 +#define FLASH_STAT_EFUSE_TIMEOUT 0x00004000 +#define FLASH_STAT_EFUSE_TIMEOUT_BITN 14 +#define FLASH_STAT_EFUSE_TIMEOUT_M 0x00004000 +#define FLASH_STAT_EFUSE_TIMEOUT_S 14 // Field: [13] SPRS_BYTE_NOT_OK // // Efuse scanning resulted in scan chain Sparse byte error. // 0 : No Sparse error // 1 : Sparse Error -#define FLASH_STAT_SPRS_BYTE_NOT_OK 0x00002000 -#define FLASH_STAT_SPRS_BYTE_NOT_OK_BITN 13 -#define FLASH_STAT_SPRS_BYTE_NOT_OK_M 0x00002000 -#define FLASH_STAT_SPRS_BYTE_NOT_OK_S 13 +#define FLASH_STAT_SPRS_BYTE_NOT_OK 0x00002000 +#define FLASH_STAT_SPRS_BYTE_NOT_OK_BITN 13 +#define FLASH_STAT_SPRS_BYTE_NOT_OK_M 0x00002000 +#define FLASH_STAT_SPRS_BYTE_NOT_OK_S 13 // Field: [12:8] EFUSE_ERRCODE // // Same as EFUSEERROR.CODE -#define FLASH_STAT_EFUSE_ERRCODE_W 5 -#define FLASH_STAT_EFUSE_ERRCODE_M 0x00001F00 -#define FLASH_STAT_EFUSE_ERRCODE_S 8 +#define FLASH_STAT_EFUSE_ERRCODE_W 5 +#define FLASH_STAT_EFUSE_ERRCODE_M 0x00001F00 +#define FLASH_STAT_EFUSE_ERRCODE_S 8 // Field: [2] SAMHOLD_DIS // @@ -463,10 +463,10 @@ // to 1 some delay after CFG.DIS_IDLE is set to 1. // 0: Not disabled // 1: Sample and hold disabled and stable -#define FLASH_STAT_SAMHOLD_DIS 0x00000004 -#define FLASH_STAT_SAMHOLD_DIS_BITN 2 -#define FLASH_STAT_SAMHOLD_DIS_M 0x00000004 -#define FLASH_STAT_SAMHOLD_DIS_S 2 +#define FLASH_STAT_SAMHOLD_DIS 0x00000004 +#define FLASH_STAT_SAMHOLD_DIS_BITN 2 +#define FLASH_STAT_SAMHOLD_DIS_M 0x00000004 +#define FLASH_STAT_SAMHOLD_DIS_S 2 // Field: [1] BUSY // @@ -475,20 +475,20 @@ // is delayed some cycles) // 0 : Not busy // 1 : Busy -#define FLASH_STAT_BUSY 0x00000002 -#define FLASH_STAT_BUSY_BITN 1 -#define FLASH_STAT_BUSY_M 0x00000002 -#define FLASH_STAT_BUSY_S 1 +#define FLASH_STAT_BUSY 0x00000002 +#define FLASH_STAT_BUSY_BITN 1 +#define FLASH_STAT_BUSY_M 0x00000002 +#define FLASH_STAT_BUSY_S 1 // Field: [0] POWER_MODE // // Power state of the flash sub-system. // 0 : Active // 1 : Low power -#define FLASH_STAT_POWER_MODE 0x00000001 -#define FLASH_STAT_POWER_MODE_BITN 0 -#define FLASH_STAT_POWER_MODE_M 0x00000001 -#define FLASH_STAT_POWER_MODE_S 0 +#define FLASH_STAT_POWER_MODE 0x00000001 +#define FLASH_STAT_POWER_MODE_BITN 0 +#define FLASH_STAT_POWER_MODE_M 0x00000001 +#define FLASH_STAT_POWER_MODE_S 0 //***************************************************************************** // @@ -498,57 +498,57 @@ // Field: [8] STANDBY_MODE_SEL // // Internal. Only to be used through TI provided API. -#define FLASH_CFG_STANDBY_MODE_SEL 0x00000100 -#define FLASH_CFG_STANDBY_MODE_SEL_BITN 8 -#define FLASH_CFG_STANDBY_MODE_SEL_M 0x00000100 -#define FLASH_CFG_STANDBY_MODE_SEL_S 8 +#define FLASH_CFG_STANDBY_MODE_SEL 0x00000100 +#define FLASH_CFG_STANDBY_MODE_SEL_BITN 8 +#define FLASH_CFG_STANDBY_MODE_SEL_M 0x00000100 +#define FLASH_CFG_STANDBY_MODE_SEL_S 8 // Field: [7:6] STANDBY_PW_SEL // // Internal. Only to be used through TI provided API. -#define FLASH_CFG_STANDBY_PW_SEL_W 2 -#define FLASH_CFG_STANDBY_PW_SEL_M 0x000000C0 -#define FLASH_CFG_STANDBY_PW_SEL_S 6 +#define FLASH_CFG_STANDBY_PW_SEL_W 2 +#define FLASH_CFG_STANDBY_PW_SEL_M 0x000000C0 +#define FLASH_CFG_STANDBY_PW_SEL_S 6 // Field: [5] DIS_EFUSECLK // // Internal. Only to be used through TI provided API. -#define FLASH_CFG_DIS_EFUSECLK 0x00000020 -#define FLASH_CFG_DIS_EFUSECLK_BITN 5 -#define FLASH_CFG_DIS_EFUSECLK_M 0x00000020 -#define FLASH_CFG_DIS_EFUSECLK_S 5 +#define FLASH_CFG_DIS_EFUSECLK 0x00000020 +#define FLASH_CFG_DIS_EFUSECLK_BITN 5 +#define FLASH_CFG_DIS_EFUSECLK_M 0x00000020 +#define FLASH_CFG_DIS_EFUSECLK_S 5 // Field: [4] DIS_READACCESS // // Internal. Only to be used through TI provided API. -#define FLASH_CFG_DIS_READACCESS 0x00000010 -#define FLASH_CFG_DIS_READACCESS_BITN 4 -#define FLASH_CFG_DIS_READACCESS_M 0x00000010 -#define FLASH_CFG_DIS_READACCESS_S 4 +#define FLASH_CFG_DIS_READACCESS 0x00000010 +#define FLASH_CFG_DIS_READACCESS_BITN 4 +#define FLASH_CFG_DIS_READACCESS_M 0x00000010 +#define FLASH_CFG_DIS_READACCESS_S 4 // Field: [3] ENABLE_SWINTF // // Internal. Only to be used through TI provided API. -#define FLASH_CFG_ENABLE_SWINTF 0x00000008 -#define FLASH_CFG_ENABLE_SWINTF_BITN 3 -#define FLASH_CFG_ENABLE_SWINTF_M 0x00000008 -#define FLASH_CFG_ENABLE_SWINTF_S 3 +#define FLASH_CFG_ENABLE_SWINTF 0x00000008 +#define FLASH_CFG_ENABLE_SWINTF_BITN 3 +#define FLASH_CFG_ENABLE_SWINTF_M 0x00000008 +#define FLASH_CFG_ENABLE_SWINTF_S 3 // Field: [1] DIS_STANDBY // // Internal. Only to be used through TI provided API. -#define FLASH_CFG_DIS_STANDBY 0x00000002 -#define FLASH_CFG_DIS_STANDBY_BITN 1 -#define FLASH_CFG_DIS_STANDBY_M 0x00000002 -#define FLASH_CFG_DIS_STANDBY_S 1 +#define FLASH_CFG_DIS_STANDBY 0x00000002 +#define FLASH_CFG_DIS_STANDBY_BITN 1 +#define FLASH_CFG_DIS_STANDBY_M 0x00000002 +#define FLASH_CFG_DIS_STANDBY_S 1 // Field: [0] DIS_IDLE // // Internal. Only to be used through TI provided API. -#define FLASH_CFG_DIS_IDLE 0x00000001 -#define FLASH_CFG_DIS_IDLE_BITN 0 -#define FLASH_CFG_DIS_IDLE_M 0x00000001 -#define FLASH_CFG_DIS_IDLE_S 0 +#define FLASH_CFG_DIS_IDLE 0x00000001 +#define FLASH_CFG_DIS_IDLE_BITN 0 +#define FLASH_CFG_DIS_IDLE_M 0x00000001 +#define FLASH_CFG_DIS_IDLE_S 0 //***************************************************************************** // @@ -558,9 +558,9 @@ // Field: [5:0] SYSCODE_START // // Internal. Only to be used through TI provided API. -#define FLASH_SYSCODE_START_SYSCODE_START_W 6 -#define FLASH_SYSCODE_START_SYSCODE_START_M 0x0000003F -#define FLASH_SYSCODE_START_SYSCODE_START_S 0 +#define FLASH_SYSCODE_START_SYSCODE_START_W 6 +#define FLASH_SYSCODE_START_SYSCODE_START_M 0x0000003F +#define FLASH_SYSCODE_START_SYSCODE_START_S 0 //***************************************************************************** // @@ -570,9 +570,9 @@ // Field: [7:0] SECTORS // // Internal. Only to be used through TI provided API. -#define FLASH_FLASH_SIZE_SECTORS_W 8 -#define FLASH_FLASH_SIZE_SECTORS_M 0x000000FF -#define FLASH_FLASH_SIZE_SECTORS_S 0 +#define FLASH_FLASH_SIZE_SECTORS_W 8 +#define FLASH_FLASH_SIZE_SECTORS_M 0x000000FF +#define FLASH_FLASH_SIZE_SECTORS_S 0 //***************************************************************************** // @@ -582,9 +582,9 @@ // Field: [2:0] FWLOCK // // Internal. Only to be used through TI provided API. -#define FLASH_FWLOCK_FWLOCK_W 3 -#define FLASH_FWLOCK_FWLOCK_M 0x00000007 -#define FLASH_FWLOCK_FWLOCK_S 0 +#define FLASH_FWLOCK_FWLOCK_W 3 +#define FLASH_FWLOCK_FWLOCK_M 0x00000007 +#define FLASH_FWLOCK_FWLOCK_S 0 //***************************************************************************** // @@ -594,9 +594,9 @@ // Field: [2:0] FWFLAG // // Internal. Only to be used through TI provided API. -#define FLASH_FWFLAG_FWFLAG_W 3 -#define FLASH_FWFLAG_FWFLAG_M 0x00000007 -#define FLASH_FWFLAG_FWFLAG_S 0 +#define FLASH_FWFLAG_FWFLAG_W 3 +#define FLASH_FWFLAG_FWFLAG_M 0x00000007 +#define FLASH_FWFLAG_FWFLAG_S 0 //***************************************************************************** // @@ -606,16 +606,16 @@ // Field: [28:24] INSTRUCTION // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSE_INSTRUCTION_W 5 -#define FLASH_EFUSE_INSTRUCTION_M 0x1F000000 -#define FLASH_EFUSE_INSTRUCTION_S 24 +#define FLASH_EFUSE_INSTRUCTION_W 5 +#define FLASH_EFUSE_INSTRUCTION_M 0x1F000000 +#define FLASH_EFUSE_INSTRUCTION_S 24 // Field: [15:0] DUMPWORD // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSE_DUMPWORD_W 16 -#define FLASH_EFUSE_DUMPWORD_M 0x0000FFFF -#define FLASH_EFUSE_DUMPWORD_S 0 +#define FLASH_EFUSE_DUMPWORD_W 16 +#define FLASH_EFUSE_DUMPWORD_M 0x0000FFFF +#define FLASH_EFUSE_DUMPWORD_S 0 //***************************************************************************** // @@ -625,16 +625,16 @@ // Field: [15:11] BLOCK // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEADDR_BLOCK_W 5 -#define FLASH_EFUSEADDR_BLOCK_M 0x0000F800 -#define FLASH_EFUSEADDR_BLOCK_S 11 +#define FLASH_EFUSEADDR_BLOCK_W 5 +#define FLASH_EFUSEADDR_BLOCK_M 0x0000F800 +#define FLASH_EFUSEADDR_BLOCK_S 11 // Field: [10:0] ROW // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEADDR_ROW_W 11 -#define FLASH_EFUSEADDR_ROW_M 0x000007FF -#define FLASH_EFUSEADDR_ROW_S 0 +#define FLASH_EFUSEADDR_ROW_W 11 +#define FLASH_EFUSEADDR_ROW_M 0x000007FF +#define FLASH_EFUSEADDR_ROW_S 0 //***************************************************************************** // @@ -644,33 +644,33 @@ // Field: [7:3] SPARE // // Internal. Only to be used through TI provided API. -#define FLASH_DATAUPPER_SPARE_W 5 -#define FLASH_DATAUPPER_SPARE_M 0x000000F8 -#define FLASH_DATAUPPER_SPARE_S 3 +#define FLASH_DATAUPPER_SPARE_W 5 +#define FLASH_DATAUPPER_SPARE_M 0x000000F8 +#define FLASH_DATAUPPER_SPARE_S 3 // Field: [2] P // // Internal. Only to be used through TI provided API. -#define FLASH_DATAUPPER_P 0x00000004 -#define FLASH_DATAUPPER_P_BITN 2 -#define FLASH_DATAUPPER_P_M 0x00000004 -#define FLASH_DATAUPPER_P_S 2 +#define FLASH_DATAUPPER_P 0x00000004 +#define FLASH_DATAUPPER_P_BITN 2 +#define FLASH_DATAUPPER_P_M 0x00000004 +#define FLASH_DATAUPPER_P_S 2 // Field: [1] R // // Internal. Only to be used through TI provided API. -#define FLASH_DATAUPPER_R 0x00000002 -#define FLASH_DATAUPPER_R_BITN 1 -#define FLASH_DATAUPPER_R_M 0x00000002 -#define FLASH_DATAUPPER_R_S 1 +#define FLASH_DATAUPPER_R 0x00000002 +#define FLASH_DATAUPPER_R_BITN 1 +#define FLASH_DATAUPPER_R_M 0x00000002 +#define FLASH_DATAUPPER_R_S 1 // Field: [0] EEN // // Internal. Only to be used through TI provided API. -#define FLASH_DATAUPPER_EEN 0x00000001 -#define FLASH_DATAUPPER_EEN_BITN 0 -#define FLASH_DATAUPPER_EEN_M 0x00000001 -#define FLASH_DATAUPPER_EEN_S 0 +#define FLASH_DATAUPPER_EEN 0x00000001 +#define FLASH_DATAUPPER_EEN_BITN 0 +#define FLASH_DATAUPPER_EEN_M 0x00000001 +#define FLASH_DATAUPPER_EEN_S 0 //***************************************************************************** // @@ -680,9 +680,9 @@ // Field: [31:0] DATA // // Internal. Only to be used through TI provided API. -#define FLASH_DATALOWER_DATA_W 32 -#define FLASH_DATALOWER_DATA_M 0xFFFFFFFF -#define FLASH_DATALOWER_DATA_S 0 +#define FLASH_DATALOWER_DATA_W 32 +#define FLASH_DATALOWER_DATA_M 0xFFFFFFFF +#define FLASH_DATALOWER_DATA_S 0 //***************************************************************************** // @@ -692,25 +692,25 @@ // Field: [8] IDLEGATING // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSECFG_IDLEGATING 0x00000100 -#define FLASH_EFUSECFG_IDLEGATING_BITN 8 -#define FLASH_EFUSECFG_IDLEGATING_M 0x00000100 -#define FLASH_EFUSECFG_IDLEGATING_S 8 +#define FLASH_EFUSECFG_IDLEGATING 0x00000100 +#define FLASH_EFUSECFG_IDLEGATING_BITN 8 +#define FLASH_EFUSECFG_IDLEGATING_M 0x00000100 +#define FLASH_EFUSECFG_IDLEGATING_S 8 // Field: [4:3] SLAVEPOWER // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSECFG_SLAVEPOWER_W 2 -#define FLASH_EFUSECFG_SLAVEPOWER_M 0x00000018 -#define FLASH_EFUSECFG_SLAVEPOWER_S 3 +#define FLASH_EFUSECFG_SLAVEPOWER_W 2 +#define FLASH_EFUSECFG_SLAVEPOWER_M 0x00000018 +#define FLASH_EFUSECFG_SLAVEPOWER_S 3 // Field: [0] GATING // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSECFG_GATING 0x00000001 -#define FLASH_EFUSECFG_GATING_BITN 0 -#define FLASH_EFUSECFG_GATING_M 0x00000001 -#define FLASH_EFUSECFG_GATING_S 0 +#define FLASH_EFUSECFG_GATING 0x00000001 +#define FLASH_EFUSECFG_GATING_BITN 0 +#define FLASH_EFUSECFG_GATING_M 0x00000001 +#define FLASH_EFUSECFG_GATING_S 0 //***************************************************************************** // @@ -720,10 +720,10 @@ // Field: [0] RESETDONE // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSESTAT_RESETDONE 0x00000001 -#define FLASH_EFUSESTAT_RESETDONE_BITN 0 -#define FLASH_EFUSESTAT_RESETDONE_M 0x00000001 -#define FLASH_EFUSESTAT_RESETDONE_S 0 +#define FLASH_EFUSESTAT_RESETDONE 0x00000001 +#define FLASH_EFUSESTAT_RESETDONE_BITN 0 +#define FLASH_EFUSESTAT_RESETDONE_M 0x00000001 +#define FLASH_EFUSESTAT_RESETDONE_S 0 //***************************************************************************** // @@ -733,9 +733,9 @@ // Field: [23:0] ACCUMULATOR // // Internal. Only to be used through TI provided API. -#define FLASH_ACC_ACCUMULATOR_W 24 -#define FLASH_ACC_ACCUMULATOR_M 0x00FFFFFF -#define FLASH_ACC_ACCUMULATOR_S 0 +#define FLASH_ACC_ACCUMULATOR_W 24 +#define FLASH_ACC_ACCUMULATOR_M 0x00FFFFFF +#define FLASH_ACC_ACCUMULATOR_S 0 //***************************************************************************** // @@ -745,110 +745,110 @@ // Field: [23] DISROW0 // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_DISROW0 0x00800000 -#define FLASH_BOUNDARY_DISROW0_BITN 23 -#define FLASH_BOUNDARY_DISROW0_M 0x00800000 -#define FLASH_BOUNDARY_DISROW0_S 23 +#define FLASH_BOUNDARY_DISROW0 0x00800000 +#define FLASH_BOUNDARY_DISROW0_BITN 23 +#define FLASH_BOUNDARY_DISROW0_M 0x00800000 +#define FLASH_BOUNDARY_DISROW0_S 23 // Field: [22] SPARE // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SPARE 0x00400000 -#define FLASH_BOUNDARY_SPARE_BITN 22 -#define FLASH_BOUNDARY_SPARE_M 0x00400000 -#define FLASH_BOUNDARY_SPARE_S 22 +#define FLASH_BOUNDARY_SPARE 0x00400000 +#define FLASH_BOUNDARY_SPARE_BITN 22 +#define FLASH_BOUNDARY_SPARE_M 0x00400000 +#define FLASH_BOUNDARY_SPARE_S 22 // Field: [21] EFC_SELF_TEST_ERROR // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR 0x00200000 -#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_BITN 21 -#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_M 0x00200000 -#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_S 21 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR 0x00200000 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_BITN 21 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_M 0x00200000 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_S 21 // Field: [20] EFC_INSTRUCTION_INFO // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO 0x00100000 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_BITN 20 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_M 0x00100000 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_S 20 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO 0x00100000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_BITN 20 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_M 0x00100000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_S 20 // Field: [19] EFC_INSTRUCTION_ERROR // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR 0x00080000 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_BITN 19 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_M 0x00080000 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_S 19 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR 0x00080000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_BITN 19 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_M 0x00080000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_S 19 // Field: [18] EFC_AUTOLOAD_ERROR // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR 0x00040000 -#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_BITN 18 -#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_M 0x00040000 -#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_S 18 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR 0x00040000 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_BITN 18 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_M 0x00040000 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_S 18 // Field: [17:14] OUTPUTENABLE // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_OUTPUTENABLE_W 4 -#define FLASH_BOUNDARY_OUTPUTENABLE_M 0x0003C000 -#define FLASH_BOUNDARY_OUTPUTENABLE_S 14 +#define FLASH_BOUNDARY_OUTPUTENABLE_W 4 +#define FLASH_BOUNDARY_OUTPUTENABLE_M 0x0003C000 +#define FLASH_BOUNDARY_OUTPUTENABLE_S 14 // Field: [13] SYS_ECC_SELF_TEST_EN // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN 0x00002000 -#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_BITN 13 -#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_M 0x00002000 -#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_S 13 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN 0x00002000 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_BITN 13 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_M 0x00002000 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_S 13 // Field: [12] SYS_ECC_OVERRIDE_EN // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN 0x00001000 -#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_BITN 12 -#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_M 0x00001000 -#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_S 12 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN 0x00001000 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_BITN 12 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_M 0x00001000 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_S 12 // Field: [11] EFC_FDI // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_FDI 0x00000800 -#define FLASH_BOUNDARY_EFC_FDI_BITN 11 -#define FLASH_BOUNDARY_EFC_FDI_M 0x00000800 -#define FLASH_BOUNDARY_EFC_FDI_S 11 +#define FLASH_BOUNDARY_EFC_FDI 0x00000800 +#define FLASH_BOUNDARY_EFC_FDI_BITN 11 +#define FLASH_BOUNDARY_EFC_FDI_M 0x00000800 +#define FLASH_BOUNDARY_EFC_FDI_S 11 // Field: [10] SYS_DIEID_AUTOLOAD_EN // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN 0x00000400 -#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_BITN 10 -#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_M 0x00000400 -#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_S 10 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN 0x00000400 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_BITN 10 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_M 0x00000400 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_S 10 // Field: [9:8] SYS_REPAIR_EN // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_REPAIR_EN_W 2 -#define FLASH_BOUNDARY_SYS_REPAIR_EN_M 0x00000300 -#define FLASH_BOUNDARY_SYS_REPAIR_EN_S 8 +#define FLASH_BOUNDARY_SYS_REPAIR_EN_W 2 +#define FLASH_BOUNDARY_SYS_REPAIR_EN_M 0x00000300 +#define FLASH_BOUNDARY_SYS_REPAIR_EN_S 8 // Field: [7:4] SYS_WS_READ_STATES // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_WS_READ_STATES_W 4 -#define FLASH_BOUNDARY_SYS_WS_READ_STATES_M 0x000000F0 -#define FLASH_BOUNDARY_SYS_WS_READ_STATES_S 4 +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_W 4 +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_M 0x000000F0 +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_S 4 // Field: [3:0] INPUTENABLE // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_INPUTENABLE_W 4 -#define FLASH_BOUNDARY_INPUTENABLE_M 0x0000000F -#define FLASH_BOUNDARY_INPUTENABLE_S 0 +#define FLASH_BOUNDARY_INPUTENABLE_W 4 +#define FLASH_BOUNDARY_INPUTENABLE_M 0x0000000F +#define FLASH_BOUNDARY_INPUTENABLE_S 0 //***************************************************************************** // @@ -858,10 +858,10 @@ // Field: [0] KEY // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEFLAG_KEY 0x00000001 -#define FLASH_EFUSEFLAG_KEY_BITN 0 -#define FLASH_EFUSEFLAG_KEY_M 0x00000001 -#define FLASH_EFUSEFLAG_KEY_S 0 +#define FLASH_EFUSEFLAG_KEY 0x00000001 +#define FLASH_EFUSEFLAG_KEY_BITN 0 +#define FLASH_EFUSEFLAG_KEY_M 0x00000001 +#define FLASH_EFUSEFLAG_KEY_S 0 //***************************************************************************** // @@ -871,9 +871,9 @@ // Field: [31:0] CODE // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEKEY_CODE_W 32 -#define FLASH_EFUSEKEY_CODE_M 0xFFFFFFFF -#define FLASH_EFUSEKEY_CODE_S 0 +#define FLASH_EFUSEKEY_CODE_W 32 +#define FLASH_EFUSEKEY_CODE_M 0xFFFFFFFF +#define FLASH_EFUSEKEY_CODE_S 0 //***************************************************************************** // @@ -883,44 +883,44 @@ // Field: [31:25] ODPYEAR // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_ODPYEAR_W 7 -#define FLASH_EFUSERELEASE_ODPYEAR_M 0xFE000000 -#define FLASH_EFUSERELEASE_ODPYEAR_S 25 +#define FLASH_EFUSERELEASE_ODPYEAR_W 7 +#define FLASH_EFUSERELEASE_ODPYEAR_M 0xFE000000 +#define FLASH_EFUSERELEASE_ODPYEAR_S 25 // Field: [24:21] ODPMONTH // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_ODPMONTH_W 4 -#define FLASH_EFUSERELEASE_ODPMONTH_M 0x01E00000 -#define FLASH_EFUSERELEASE_ODPMONTH_S 21 +#define FLASH_EFUSERELEASE_ODPMONTH_W 4 +#define FLASH_EFUSERELEASE_ODPMONTH_M 0x01E00000 +#define FLASH_EFUSERELEASE_ODPMONTH_S 21 // Field: [20:16] ODPDAY // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_ODPDAY_W 5 -#define FLASH_EFUSERELEASE_ODPDAY_M 0x001F0000 -#define FLASH_EFUSERELEASE_ODPDAY_S 16 +#define FLASH_EFUSERELEASE_ODPDAY_W 5 +#define FLASH_EFUSERELEASE_ODPDAY_M 0x001F0000 +#define FLASH_EFUSERELEASE_ODPDAY_S 16 // Field: [15:9] EFUSEYEAR // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_EFUSEYEAR_W 7 -#define FLASH_EFUSERELEASE_EFUSEYEAR_M 0x0000FE00 -#define FLASH_EFUSERELEASE_EFUSEYEAR_S 9 +#define FLASH_EFUSERELEASE_EFUSEYEAR_W 7 +#define FLASH_EFUSERELEASE_EFUSEYEAR_M 0x0000FE00 +#define FLASH_EFUSERELEASE_EFUSEYEAR_S 9 // Field: [8:5] EFUSEMONTH // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_EFUSEMONTH_W 4 -#define FLASH_EFUSERELEASE_EFUSEMONTH_M 0x000001E0 -#define FLASH_EFUSERELEASE_EFUSEMONTH_S 5 +#define FLASH_EFUSERELEASE_EFUSEMONTH_W 4 +#define FLASH_EFUSERELEASE_EFUSEMONTH_M 0x000001E0 +#define FLASH_EFUSERELEASE_EFUSEMONTH_S 5 // Field: [4:0] EFUSEDAY // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_EFUSEDAY_W 5 -#define FLASH_EFUSERELEASE_EFUSEDAY_M 0x0000001F -#define FLASH_EFUSERELEASE_EFUSEDAY_S 0 +#define FLASH_EFUSERELEASE_EFUSEDAY_W 5 +#define FLASH_EFUSERELEASE_EFUSEDAY_M 0x0000001F +#define FLASH_EFUSERELEASE_EFUSEDAY_S 0 //***************************************************************************** // @@ -930,96 +930,96 @@ // Field: [15] EFC_SELF_TEST_DONE // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE 0x00008000 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_BITN 15 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_M 0x00008000 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_S 15 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE 0x00008000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_BITN 15 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_M 0x00008000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_S 15 // Field: [14] EFC_SELF_TEST_ERROR // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR 0x00004000 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_BITN 14 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_M 0x00004000 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_S 14 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR 0x00004000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_BITN 14 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_M 0x00004000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_S 14 // Field: [13] SYS_ECC_SELF_TEST_EN // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN 0x00002000 -#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_BITN 13 -#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_M 0x00002000 -#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_S 13 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN 0x00002000 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_BITN 13 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_M 0x00002000 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_S 13 // Field: [12] EFC_INSTRUCTION_INFO // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO 0x00001000 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_BITN 12 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_M 0x00001000 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_S 12 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO 0x00001000 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_BITN 12 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_M 0x00001000 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_S 12 // Field: [11] EFC_INSTRUCTION_ERROR // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR 0x00000800 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_BITN 11 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_M 0x00000800 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_S 11 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR 0x00000800 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_BITN 11 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_M 0x00000800 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_S 11 // Field: [10] EFC_AUTOLOAD_ERROR // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR 0x00000400 -#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_BITN 10 -#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_M 0x00000400 -#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_S 10 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR 0x00000400 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_BITN 10 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_M 0x00000400 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_S 10 // Field: [9] SYS_ECC_OVERRIDE_EN // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN 0x00000200 -#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_BITN 9 -#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_M 0x00000200 -#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_S 9 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN 0x00000200 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_BITN 9 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_M 0x00000200 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_S 9 // Field: [8] EFC_READY // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_READY 0x00000100 -#define FLASH_EFUSEPINS_EFC_READY_BITN 8 -#define FLASH_EFUSEPINS_EFC_READY_M 0x00000100 -#define FLASH_EFUSEPINS_EFC_READY_S 8 +#define FLASH_EFUSEPINS_EFC_READY 0x00000100 +#define FLASH_EFUSEPINS_EFC_READY_BITN 8 +#define FLASH_EFUSEPINS_EFC_READY_M 0x00000100 +#define FLASH_EFUSEPINS_EFC_READY_S 8 // Field: [7] EFC_FCLRZ // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_FCLRZ 0x00000080 -#define FLASH_EFUSEPINS_EFC_FCLRZ_BITN 7 -#define FLASH_EFUSEPINS_EFC_FCLRZ_M 0x00000080 -#define FLASH_EFUSEPINS_EFC_FCLRZ_S 7 +#define FLASH_EFUSEPINS_EFC_FCLRZ 0x00000080 +#define FLASH_EFUSEPINS_EFC_FCLRZ_BITN 7 +#define FLASH_EFUSEPINS_EFC_FCLRZ_M 0x00000080 +#define FLASH_EFUSEPINS_EFC_FCLRZ_S 7 // Field: [6] SYS_DIEID_AUTOLOAD_EN // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN 0x00000040 -#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_BITN 6 -#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_M 0x00000040 -#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_S 6 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN 0x00000040 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_BITN 6 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_M 0x00000040 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_S 6 // Field: [5:4] SYS_REPAIR_EN // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_REPAIR_EN_W 2 -#define FLASH_EFUSEPINS_SYS_REPAIR_EN_M 0x00000030 -#define FLASH_EFUSEPINS_SYS_REPAIR_EN_S 4 +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_W 2 +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_M 0x00000030 +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_S 4 // Field: [3:0] SYS_WS_READ_STATES // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_W 4 -#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_M 0x0000000F -#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_S 0 +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_W 4 +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_M 0x0000000F +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_S 0 //***************************************************************************** // @@ -1029,9 +1029,9 @@ // Field: [5:0] DATA // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSECRA_DATA_W 6 -#define FLASH_EFUSECRA_DATA_M 0x0000003F -#define FLASH_EFUSECRA_DATA_S 0 +#define FLASH_EFUSECRA_DATA_W 6 +#define FLASH_EFUSECRA_DATA_M 0x0000003F +#define FLASH_EFUSECRA_DATA_S 0 //***************************************************************************** // @@ -1041,39 +1041,39 @@ // Field: [9:8] DATABIT // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_DATABIT_W 2 -#define FLASH_EFUSEREAD_DATABIT_M 0x00000300 -#define FLASH_EFUSEREAD_DATABIT_S 8 +#define FLASH_EFUSEREAD_DATABIT_W 2 +#define FLASH_EFUSEREAD_DATABIT_M 0x00000300 +#define FLASH_EFUSEREAD_DATABIT_S 8 // Field: [7:4] READCLOCK // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_READCLOCK_W 4 -#define FLASH_EFUSEREAD_READCLOCK_M 0x000000F0 -#define FLASH_EFUSEREAD_READCLOCK_S 4 +#define FLASH_EFUSEREAD_READCLOCK_W 4 +#define FLASH_EFUSEREAD_READCLOCK_M 0x000000F0 +#define FLASH_EFUSEREAD_READCLOCK_S 4 // Field: [3] DEBUG // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_DEBUG 0x00000008 -#define FLASH_EFUSEREAD_DEBUG_BITN 3 -#define FLASH_EFUSEREAD_DEBUG_M 0x00000008 -#define FLASH_EFUSEREAD_DEBUG_S 3 +#define FLASH_EFUSEREAD_DEBUG 0x00000008 +#define FLASH_EFUSEREAD_DEBUG_BITN 3 +#define FLASH_EFUSEREAD_DEBUG_M 0x00000008 +#define FLASH_EFUSEREAD_DEBUG_S 3 // Field: [2] SPARE // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_SPARE 0x00000004 -#define FLASH_EFUSEREAD_SPARE_BITN 2 -#define FLASH_EFUSEREAD_SPARE_M 0x00000004 -#define FLASH_EFUSEREAD_SPARE_S 2 +#define FLASH_EFUSEREAD_SPARE 0x00000004 +#define FLASH_EFUSEREAD_SPARE_BITN 2 +#define FLASH_EFUSEREAD_SPARE_M 0x00000004 +#define FLASH_EFUSEREAD_SPARE_S 2 // Field: [1:0] MARGIN // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_MARGIN_W 2 -#define FLASH_EFUSEREAD_MARGIN_M 0x00000003 -#define FLASH_EFUSEREAD_MARGIN_S 0 +#define FLASH_EFUSEREAD_MARGIN_W 2 +#define FLASH_EFUSEREAD_MARGIN_M 0x00000003 +#define FLASH_EFUSEREAD_MARGIN_S 0 //***************************************************************************** // @@ -1083,39 +1083,39 @@ // Field: [30] COMPAREDISABLE // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_COMPAREDISABLE 0x40000000 -#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_BITN 30 -#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_M 0x40000000 -#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_S 30 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE 0x40000000 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_BITN 30 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_M 0x40000000 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_S 30 // Field: [29:14] CLOCKSTALL // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_CLOCKSTALL_W 16 -#define FLASH_EFUSEPROGRAM_CLOCKSTALL_M 0x3FFFC000 -#define FLASH_EFUSEPROGRAM_CLOCKSTALL_S 14 +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_W 16 +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_M 0x3FFFC000 +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_S 14 // Field: [13] VPPTOVDD // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_VPPTOVDD 0x00002000 -#define FLASH_EFUSEPROGRAM_VPPTOVDD_BITN 13 -#define FLASH_EFUSEPROGRAM_VPPTOVDD_M 0x00002000 -#define FLASH_EFUSEPROGRAM_VPPTOVDD_S 13 +#define FLASH_EFUSEPROGRAM_VPPTOVDD 0x00002000 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_BITN 13 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_M 0x00002000 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_S 13 // Field: [12:9] ITERATIONS // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_ITERATIONS_W 4 -#define FLASH_EFUSEPROGRAM_ITERATIONS_M 0x00001E00 -#define FLASH_EFUSEPROGRAM_ITERATIONS_S 9 +#define FLASH_EFUSEPROGRAM_ITERATIONS_W 4 +#define FLASH_EFUSEPROGRAM_ITERATIONS_M 0x00001E00 +#define FLASH_EFUSEPROGRAM_ITERATIONS_S 9 // Field: [8:0] WRITECLOCK // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_WRITECLOCK_W 9 -#define FLASH_EFUSEPROGRAM_WRITECLOCK_M 0x000001FF -#define FLASH_EFUSEPROGRAM_WRITECLOCK_S 0 +#define FLASH_EFUSEPROGRAM_WRITECLOCK_W 9 +#define FLASH_EFUSEPROGRAM_WRITECLOCK_M 0x000001FF +#define FLASH_EFUSEPROGRAM_WRITECLOCK_S 0 //***************************************************************************** // @@ -1125,17 +1125,17 @@ // Field: [5] DONE // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEERROR_DONE 0x00000020 -#define FLASH_EFUSEERROR_DONE_BITN 5 -#define FLASH_EFUSEERROR_DONE_M 0x00000020 -#define FLASH_EFUSEERROR_DONE_S 5 +#define FLASH_EFUSEERROR_DONE 0x00000020 +#define FLASH_EFUSEERROR_DONE_BITN 5 +#define FLASH_EFUSEERROR_DONE_M 0x00000020 +#define FLASH_EFUSEERROR_DONE_S 5 // Field: [4:0] CODE // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEERROR_CODE_W 5 -#define FLASH_EFUSEERROR_CODE_M 0x0000001F -#define FLASH_EFUSEERROR_CODE_S 0 +#define FLASH_EFUSEERROR_CODE_W 5 +#define FLASH_EFUSEERROR_CODE_M 0x0000001F +#define FLASH_EFUSEERROR_CODE_S 0 //***************************************************************************** // @@ -1145,17 +1145,17 @@ // Field: [31:1] FROMN // // Internal. Only to be used through TI provided API. -#define FLASH_SINGLEBIT_FROMN_W 31 -#define FLASH_SINGLEBIT_FROMN_M 0xFFFFFFFE -#define FLASH_SINGLEBIT_FROMN_S 1 +#define FLASH_SINGLEBIT_FROMN_W 31 +#define FLASH_SINGLEBIT_FROMN_M 0xFFFFFFFE +#define FLASH_SINGLEBIT_FROMN_S 1 // Field: [0] FROM0 // // Internal. Only to be used through TI provided API. -#define FLASH_SINGLEBIT_FROM0 0x00000001 -#define FLASH_SINGLEBIT_FROM0_BITN 0 -#define FLASH_SINGLEBIT_FROM0_M 0x00000001 -#define FLASH_SINGLEBIT_FROM0_S 0 +#define FLASH_SINGLEBIT_FROM0 0x00000001 +#define FLASH_SINGLEBIT_FROM0_BITN 0 +#define FLASH_SINGLEBIT_FROM0_M 0x00000001 +#define FLASH_SINGLEBIT_FROM0_S 0 //***************************************************************************** // @@ -1165,17 +1165,17 @@ // Field: [31:1] FROMN // // Internal. Only to be used through TI provided API. -#define FLASH_TWOBIT_FROMN_W 31 -#define FLASH_TWOBIT_FROMN_M 0xFFFFFFFE -#define FLASH_TWOBIT_FROMN_S 1 +#define FLASH_TWOBIT_FROMN_W 31 +#define FLASH_TWOBIT_FROMN_M 0xFFFFFFFE +#define FLASH_TWOBIT_FROMN_S 1 // Field: [0] FROM0 // // Internal. Only to be used through TI provided API. -#define FLASH_TWOBIT_FROM0 0x00000001 -#define FLASH_TWOBIT_FROM0_BITN 0 -#define FLASH_TWOBIT_FROM0_M 0x00000001 -#define FLASH_TWOBIT_FROM0_S 0 +#define FLASH_TWOBIT_FROM0 0x00000001 +#define FLASH_TWOBIT_FROM0_BITN 0 +#define FLASH_TWOBIT_FROM0_M 0x00000001 +#define FLASH_TWOBIT_FROM0_S 0 //***************************************************************************** // @@ -1185,9 +1185,9 @@ // Field: [31:0] CYCLES // // Internal. Only to be used through TI provided API. -#define FLASH_SELFTESTCYC_CYCLES_W 32 -#define FLASH_SELFTESTCYC_CYCLES_M 0xFFFFFFFF -#define FLASH_SELFTESTCYC_CYCLES_S 0 +#define FLASH_SELFTESTCYC_CYCLES_W 32 +#define FLASH_SELFTESTCYC_CYCLES_M 0xFFFFFFFF +#define FLASH_SELFTESTCYC_CYCLES_S 0 //***************************************************************************** // @@ -1197,9 +1197,9 @@ // Field: [31:0] SIGNATURE // // Internal. Only to be used through TI provided API. -#define FLASH_SELFTESTSIGN_SIGNATURE_W 32 -#define FLASH_SELFTESTSIGN_SIGNATURE_M 0xFFFFFFFF -#define FLASH_SELFTESTSIGN_SIGNATURE_S 0 +#define FLASH_SELFTESTSIGN_SIGNATURE_W 32 +#define FLASH_SELFTESTSIGN_SIGNATURE_M 0xFFFFFFFF +#define FLASH_SELFTESTSIGN_SIGNATURE_S 0 //***************************************************************************** // @@ -1209,9 +1209,9 @@ // Field: [11:8] RWAIT // // Internal. Only to be used through TI provided API. -#define FLASH_FRDCTL_RWAIT_W 4 -#define FLASH_FRDCTL_RWAIT_M 0x00000F00 -#define FLASH_FRDCTL_RWAIT_S 8 +#define FLASH_FRDCTL_RWAIT_W 4 +#define FLASH_FRDCTL_RWAIT_M 0x00000F00 +#define FLASH_FRDCTL_RWAIT_S 8 //***************************************************************************** // @@ -1221,25 +1221,25 @@ // Field: [15:8] RMBSEM // // Internal. Only to be used through TI provided API. -#define FLASH_FSPRD_RMBSEM_W 8 -#define FLASH_FSPRD_RMBSEM_M 0x0000FF00 -#define FLASH_FSPRD_RMBSEM_S 8 +#define FLASH_FSPRD_RMBSEM_W 8 +#define FLASH_FSPRD_RMBSEM_M 0x0000FF00 +#define FLASH_FSPRD_RMBSEM_S 8 // Field: [1] RM1 // // Internal. Only to be used through TI provided API. -#define FLASH_FSPRD_RM1 0x00000002 -#define FLASH_FSPRD_RM1_BITN 1 -#define FLASH_FSPRD_RM1_M 0x00000002 -#define FLASH_FSPRD_RM1_S 1 +#define FLASH_FSPRD_RM1 0x00000002 +#define FLASH_FSPRD_RM1_BITN 1 +#define FLASH_FSPRD_RM1_M 0x00000002 +#define FLASH_FSPRD_RM1_S 1 // Field: [0] RM0 // // Internal. Only to be used through TI provided API. -#define FLASH_FSPRD_RM0 0x00000001 -#define FLASH_FSPRD_RM0_BITN 0 -#define FLASH_FSPRD_RM0_M 0x00000001 -#define FLASH_FSPRD_RM0_S 0 +#define FLASH_FSPRD_RM0 0x00000001 +#define FLASH_FSPRD_RM0_BITN 0 +#define FLASH_FSPRD_RM0_M 0x00000001 +#define FLASH_FSPRD_RM0_S 0 //***************************************************************************** // @@ -1249,10 +1249,10 @@ // Field: [24] SUSP_IGNR // // Internal. Only to be used through TI provided API. -#define FLASH_FEDACCTL1_SUSP_IGNR 0x01000000 -#define FLASH_FEDACCTL1_SUSP_IGNR_BITN 24 -#define FLASH_FEDACCTL1_SUSP_IGNR_M 0x01000000 -#define FLASH_FEDACCTL1_SUSP_IGNR_S 24 +#define FLASH_FEDACCTL1_SUSP_IGNR 0x01000000 +#define FLASH_FEDACCTL1_SUSP_IGNR_BITN 24 +#define FLASH_FEDACCTL1_SUSP_IGNR_M 0x01000000 +#define FLASH_FEDACCTL1_SUSP_IGNR_S 24 //***************************************************************************** // @@ -1262,18 +1262,18 @@ // Field: [25] RVF_INT // // Internal. Only to be used through TI provided API. -#define FLASH_FEDACSTAT_RVF_INT 0x02000000 -#define FLASH_FEDACSTAT_RVF_INT_BITN 25 -#define FLASH_FEDACSTAT_RVF_INT_M 0x02000000 -#define FLASH_FEDACSTAT_RVF_INT_S 25 +#define FLASH_FEDACSTAT_RVF_INT 0x02000000 +#define FLASH_FEDACSTAT_RVF_INT_BITN 25 +#define FLASH_FEDACSTAT_RVF_INT_M 0x02000000 +#define FLASH_FEDACSTAT_RVF_INT_S 25 // Field: [24] FSM_DONE // // Internal. Only to be used through TI provided API. -#define FLASH_FEDACSTAT_FSM_DONE 0x01000000 -#define FLASH_FEDACSTAT_FSM_DONE_BITN 24 -#define FLASH_FEDACSTAT_FSM_DONE_M 0x01000000 -#define FLASH_FEDACSTAT_FSM_DONE_S 24 +#define FLASH_FEDACSTAT_FSM_DONE 0x01000000 +#define FLASH_FEDACSTAT_FSM_DONE_BITN 24 +#define FLASH_FEDACSTAT_FSM_DONE_M 0x01000000 +#define FLASH_FEDACSTAT_FSM_DONE_S 24 //***************************************************************************** // @@ -1283,10 +1283,10 @@ // Field: [0] PROTL1DIS // // Internal. Only to be used through TI provided API. -#define FLASH_FBPROT_PROTL1DIS 0x00000001 -#define FLASH_FBPROT_PROTL1DIS_BITN 0 -#define FLASH_FBPROT_PROTL1DIS_M 0x00000001 -#define FLASH_FBPROT_PROTL1DIS_S 0 +#define FLASH_FBPROT_PROTL1DIS 0x00000001 +#define FLASH_FBPROT_PROTL1DIS_BITN 0 +#define FLASH_FBPROT_PROTL1DIS_M 0x00000001 +#define FLASH_FBPROT_PROTL1DIS_S 0 //***************************************************************************** // @@ -1296,9 +1296,9 @@ // Field: [15:0] BSE // // Internal. Only to be used through TI provided API. -#define FLASH_FBSE_BSE_W 16 -#define FLASH_FBSE_BSE_M 0x0000FFFF -#define FLASH_FBSE_BSE_S 0 +#define FLASH_FBSE_BSE_W 16 +#define FLASH_FBSE_BSE_M 0x0000FFFF +#define FLASH_FBSE_BSE_S 0 //***************************************************************************** // @@ -1308,9 +1308,9 @@ // Field: [7:0] BUSY // // Internal. Only to be used through TI provided API. -#define FLASH_FBBUSY_BUSY_W 8 -#define FLASH_FBBUSY_BUSY_M 0x000000FF -#define FLASH_FBBUSY_BUSY_S 0 +#define FLASH_FBBUSY_BUSY_W 8 +#define FLASH_FBBUSY_BUSY_M 0x000000FF +#define FLASH_FBBUSY_BUSY_S 0 //***************************************************************************** // @@ -1320,24 +1320,24 @@ // Field: [16] OTPPROTDIS // // Internal. Only to be used through TI provided API. -#define FLASH_FBAC_OTPPROTDIS 0x00010000 -#define FLASH_FBAC_OTPPROTDIS_BITN 16 -#define FLASH_FBAC_OTPPROTDIS_M 0x00010000 -#define FLASH_FBAC_OTPPROTDIS_S 16 +#define FLASH_FBAC_OTPPROTDIS 0x00010000 +#define FLASH_FBAC_OTPPROTDIS_BITN 16 +#define FLASH_FBAC_OTPPROTDIS_M 0x00010000 +#define FLASH_FBAC_OTPPROTDIS_S 16 // Field: [15:8] BAGP // // Internal. Only to be used through TI provided API. -#define FLASH_FBAC_BAGP_W 8 -#define FLASH_FBAC_BAGP_M 0x0000FF00 -#define FLASH_FBAC_BAGP_S 8 +#define FLASH_FBAC_BAGP_W 8 +#define FLASH_FBAC_BAGP_M 0x0000FF00 +#define FLASH_FBAC_BAGP_S 8 // Field: [7:0] VREADS // // Internal. Only to be used through TI provided API. -#define FLASH_FBAC_VREADS_W 8 -#define FLASH_FBAC_VREADS_M 0x000000FF -#define FLASH_FBAC_VREADS_S 0 +#define FLASH_FBAC_VREADS_W 8 +#define FLASH_FBAC_VREADS_M 0x000000FF +#define FLASH_FBAC_VREADS_S 0 //***************************************************************************** // @@ -1347,72 +1347,72 @@ // Field: [27:24] FSM_PWRSAV // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_FSM_PWRSAV_W 4 -#define FLASH_FBFALLBACK_FSM_PWRSAV_M 0x0F000000 -#define FLASH_FBFALLBACK_FSM_PWRSAV_S 24 +#define FLASH_FBFALLBACK_FSM_PWRSAV_W 4 +#define FLASH_FBFALLBACK_FSM_PWRSAV_M 0x0F000000 +#define FLASH_FBFALLBACK_FSM_PWRSAV_S 24 // Field: [19:16] REG_PWRSAV // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_REG_PWRSAV_W 4 -#define FLASH_FBFALLBACK_REG_PWRSAV_M 0x000F0000 -#define FLASH_FBFALLBACK_REG_PWRSAV_S 16 +#define FLASH_FBFALLBACK_REG_PWRSAV_W 4 +#define FLASH_FBFALLBACK_REG_PWRSAV_M 0x000F0000 +#define FLASH_FBFALLBACK_REG_PWRSAV_S 16 // Field: [15:14] BANKPWR7 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR7_W 2 -#define FLASH_FBFALLBACK_BANKPWR7_M 0x0000C000 -#define FLASH_FBFALLBACK_BANKPWR7_S 14 +#define FLASH_FBFALLBACK_BANKPWR7_W 2 +#define FLASH_FBFALLBACK_BANKPWR7_M 0x0000C000 +#define FLASH_FBFALLBACK_BANKPWR7_S 14 // Field: [13:12] BANKPWR6 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR6_W 2 -#define FLASH_FBFALLBACK_BANKPWR6_M 0x00003000 -#define FLASH_FBFALLBACK_BANKPWR6_S 12 +#define FLASH_FBFALLBACK_BANKPWR6_W 2 +#define FLASH_FBFALLBACK_BANKPWR6_M 0x00003000 +#define FLASH_FBFALLBACK_BANKPWR6_S 12 // Field: [11:10] BANKPWR5 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR5_W 2 -#define FLASH_FBFALLBACK_BANKPWR5_M 0x00000C00 -#define FLASH_FBFALLBACK_BANKPWR5_S 10 +#define FLASH_FBFALLBACK_BANKPWR5_W 2 +#define FLASH_FBFALLBACK_BANKPWR5_M 0x00000C00 +#define FLASH_FBFALLBACK_BANKPWR5_S 10 // Field: [9:8] BANKPWR4 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR4_W 2 -#define FLASH_FBFALLBACK_BANKPWR4_M 0x00000300 -#define FLASH_FBFALLBACK_BANKPWR4_S 8 +#define FLASH_FBFALLBACK_BANKPWR4_W 2 +#define FLASH_FBFALLBACK_BANKPWR4_M 0x00000300 +#define FLASH_FBFALLBACK_BANKPWR4_S 8 // Field: [7:6] BANKPWR3 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR3_W 2 -#define FLASH_FBFALLBACK_BANKPWR3_M 0x000000C0 -#define FLASH_FBFALLBACK_BANKPWR3_S 6 +#define FLASH_FBFALLBACK_BANKPWR3_W 2 +#define FLASH_FBFALLBACK_BANKPWR3_M 0x000000C0 +#define FLASH_FBFALLBACK_BANKPWR3_S 6 // Field: [5:4] BANKPWR2 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR2_W 2 -#define FLASH_FBFALLBACK_BANKPWR2_M 0x00000030 -#define FLASH_FBFALLBACK_BANKPWR2_S 4 +#define FLASH_FBFALLBACK_BANKPWR2_W 2 +#define FLASH_FBFALLBACK_BANKPWR2_M 0x00000030 +#define FLASH_FBFALLBACK_BANKPWR2_S 4 // Field: [3:2] BANKPWR1 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR1_W 2 -#define FLASH_FBFALLBACK_BANKPWR1_M 0x0000000C -#define FLASH_FBFALLBACK_BANKPWR1_S 2 +#define FLASH_FBFALLBACK_BANKPWR1_W 2 +#define FLASH_FBFALLBACK_BANKPWR1_M 0x0000000C +#define FLASH_FBFALLBACK_BANKPWR1_S 2 // Field: [1:0] BANKPWR0 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR0_W 2 -#define FLASH_FBFALLBACK_BANKPWR0_M 0x00000003 -#define FLASH_FBFALLBACK_BANKPWR0_S 0 +#define FLASH_FBFALLBACK_BANKPWR0_W 2 +#define FLASH_FBFALLBACK_BANKPWR0_M 0x00000003 +#define FLASH_FBFALLBACK_BANKPWR0_S 0 //***************************************************************************** // @@ -1422,26 +1422,26 @@ // Field: [16] BANKBUSY // // Internal. Only to be used through TI provided API. -#define FLASH_FBPRDY_BANKBUSY 0x00010000 -#define FLASH_FBPRDY_BANKBUSY_BITN 16 -#define FLASH_FBPRDY_BANKBUSY_M 0x00010000 -#define FLASH_FBPRDY_BANKBUSY_S 16 +#define FLASH_FBPRDY_BANKBUSY 0x00010000 +#define FLASH_FBPRDY_BANKBUSY_BITN 16 +#define FLASH_FBPRDY_BANKBUSY_M 0x00010000 +#define FLASH_FBPRDY_BANKBUSY_S 16 // Field: [15] PUMPRDY // // Internal. Only to be used through TI provided API. -#define FLASH_FBPRDY_PUMPRDY 0x00008000 -#define FLASH_FBPRDY_PUMPRDY_BITN 15 -#define FLASH_FBPRDY_PUMPRDY_M 0x00008000 -#define FLASH_FBPRDY_PUMPRDY_S 15 +#define FLASH_FBPRDY_PUMPRDY 0x00008000 +#define FLASH_FBPRDY_PUMPRDY_BITN 15 +#define FLASH_FBPRDY_PUMPRDY_M 0x00008000 +#define FLASH_FBPRDY_PUMPRDY_S 15 // Field: [0] BANKRDY // // Internal. Only to be used through TI provided API. -#define FLASH_FBPRDY_BANKRDY 0x00000001 -#define FLASH_FBPRDY_BANKRDY_BITN 0 -#define FLASH_FBPRDY_BANKRDY_M 0x00000001 -#define FLASH_FBPRDY_BANKRDY_S 0 +#define FLASH_FBPRDY_BANKRDY 0x00000001 +#define FLASH_FBPRDY_BANKRDY_BITN 0 +#define FLASH_FBPRDY_BANKRDY_M 0x00000001 +#define FLASH_FBPRDY_BANKRDY_S 0 //***************************************************************************** // @@ -1451,23 +1451,23 @@ // Field: [27:16] PSLEEPTDIS // // Internal. Only to be used through TI provided API. -#define FLASH_FPAC1_PSLEEPTDIS_W 12 -#define FLASH_FPAC1_PSLEEPTDIS_M 0x0FFF0000 -#define FLASH_FPAC1_PSLEEPTDIS_S 16 +#define FLASH_FPAC1_PSLEEPTDIS_W 12 +#define FLASH_FPAC1_PSLEEPTDIS_M 0x0FFF0000 +#define FLASH_FPAC1_PSLEEPTDIS_S 16 // Field: [15:4] PUMPRESET_PW // // Internal. Only to be used through TI provided API. -#define FLASH_FPAC1_PUMPRESET_PW_W 12 -#define FLASH_FPAC1_PUMPRESET_PW_M 0x0000FFF0 -#define FLASH_FPAC1_PUMPRESET_PW_S 4 +#define FLASH_FPAC1_PUMPRESET_PW_W 12 +#define FLASH_FPAC1_PUMPRESET_PW_M 0x0000FFF0 +#define FLASH_FPAC1_PUMPRESET_PW_S 4 // Field: [1:0] PUMPPWR // // Internal. Only to be used through TI provided API. -#define FLASH_FPAC1_PUMPPWR_W 2 -#define FLASH_FPAC1_PUMPPWR_M 0x00000003 -#define FLASH_FPAC1_PUMPPWR_S 0 +#define FLASH_FPAC1_PUMPPWR_W 2 +#define FLASH_FPAC1_PUMPPWR_M 0x00000003 +#define FLASH_FPAC1_PUMPPWR_S 0 //***************************************************************************** // @@ -1477,9 +1477,9 @@ // Field: [15:0] PAGP // // Internal. Only to be used through TI provided API. -#define FLASH_FPAC2_PAGP_W 16 -#define FLASH_FPAC2_PAGP_M 0x0000FFFF -#define FLASH_FPAC2_PAGP_S 0 +#define FLASH_FPAC2_PAGP_W 16 +#define FLASH_FPAC2_PAGP_M 0x0000FFFF +#define FLASH_FPAC2_PAGP_S 0 //***************************************************************************** // @@ -1489,9 +1489,9 @@ // Field: [2:0] BANK // // Internal. Only to be used through TI provided API. -#define FLASH_FMAC_BANK_W 3 -#define FLASH_FMAC_BANK_M 0x00000007 -#define FLASH_FMAC_BANK_S 0 +#define FLASH_FMAC_BANK_W 3 +#define FLASH_FMAC_BANK_M 0x00000007 +#define FLASH_FMAC_BANK_S 0 //***************************************************************************** // @@ -1501,146 +1501,146 @@ // Field: [17] RVSUSP // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_RVSUSP 0x00020000 -#define FLASH_FMSTAT_RVSUSP_BITN 17 -#define FLASH_FMSTAT_RVSUSP_M 0x00020000 -#define FLASH_FMSTAT_RVSUSP_S 17 +#define FLASH_FMSTAT_RVSUSP 0x00020000 +#define FLASH_FMSTAT_RVSUSP_BITN 17 +#define FLASH_FMSTAT_RVSUSP_M 0x00020000 +#define FLASH_FMSTAT_RVSUSP_S 17 // Field: [16] RDVER // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_RDVER 0x00010000 -#define FLASH_FMSTAT_RDVER_BITN 16 -#define FLASH_FMSTAT_RDVER_M 0x00010000 -#define FLASH_FMSTAT_RDVER_S 16 +#define FLASH_FMSTAT_RDVER 0x00010000 +#define FLASH_FMSTAT_RDVER_BITN 16 +#define FLASH_FMSTAT_RDVER_M 0x00010000 +#define FLASH_FMSTAT_RDVER_S 16 // Field: [15] RVF // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_RVF 0x00008000 -#define FLASH_FMSTAT_RVF_BITN 15 -#define FLASH_FMSTAT_RVF_M 0x00008000 -#define FLASH_FMSTAT_RVF_S 15 +#define FLASH_FMSTAT_RVF 0x00008000 +#define FLASH_FMSTAT_RVF_BITN 15 +#define FLASH_FMSTAT_RVF_M 0x00008000 +#define FLASH_FMSTAT_RVF_S 15 // Field: [14] ILA // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_ILA 0x00004000 -#define FLASH_FMSTAT_ILA_BITN 14 -#define FLASH_FMSTAT_ILA_M 0x00004000 -#define FLASH_FMSTAT_ILA_S 14 +#define FLASH_FMSTAT_ILA 0x00004000 +#define FLASH_FMSTAT_ILA_BITN 14 +#define FLASH_FMSTAT_ILA_M 0x00004000 +#define FLASH_FMSTAT_ILA_S 14 // Field: [13] DBF // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_DBF 0x00002000 -#define FLASH_FMSTAT_DBF_BITN 13 -#define FLASH_FMSTAT_DBF_M 0x00002000 -#define FLASH_FMSTAT_DBF_S 13 +#define FLASH_FMSTAT_DBF 0x00002000 +#define FLASH_FMSTAT_DBF_BITN 13 +#define FLASH_FMSTAT_DBF_M 0x00002000 +#define FLASH_FMSTAT_DBF_S 13 // Field: [12] PGV // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_PGV 0x00001000 -#define FLASH_FMSTAT_PGV_BITN 12 -#define FLASH_FMSTAT_PGV_M 0x00001000 -#define FLASH_FMSTAT_PGV_S 12 +#define FLASH_FMSTAT_PGV 0x00001000 +#define FLASH_FMSTAT_PGV_BITN 12 +#define FLASH_FMSTAT_PGV_M 0x00001000 +#define FLASH_FMSTAT_PGV_S 12 // Field: [11] PCV // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_PCV 0x00000800 -#define FLASH_FMSTAT_PCV_BITN 11 -#define FLASH_FMSTAT_PCV_M 0x00000800 -#define FLASH_FMSTAT_PCV_S 11 +#define FLASH_FMSTAT_PCV 0x00000800 +#define FLASH_FMSTAT_PCV_BITN 11 +#define FLASH_FMSTAT_PCV_M 0x00000800 +#define FLASH_FMSTAT_PCV_S 11 // Field: [10] EV // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_EV 0x00000400 -#define FLASH_FMSTAT_EV_BITN 10 -#define FLASH_FMSTAT_EV_M 0x00000400 -#define FLASH_FMSTAT_EV_S 10 +#define FLASH_FMSTAT_EV 0x00000400 +#define FLASH_FMSTAT_EV_BITN 10 +#define FLASH_FMSTAT_EV_M 0x00000400 +#define FLASH_FMSTAT_EV_S 10 // Field: [9] CV // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_CV 0x00000200 -#define FLASH_FMSTAT_CV_BITN 9 -#define FLASH_FMSTAT_CV_M 0x00000200 -#define FLASH_FMSTAT_CV_S 9 +#define FLASH_FMSTAT_CV 0x00000200 +#define FLASH_FMSTAT_CV_BITN 9 +#define FLASH_FMSTAT_CV_M 0x00000200 +#define FLASH_FMSTAT_CV_S 9 // Field: [8] BUSY // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_BUSY 0x00000100 -#define FLASH_FMSTAT_BUSY_BITN 8 -#define FLASH_FMSTAT_BUSY_M 0x00000100 -#define FLASH_FMSTAT_BUSY_S 8 +#define FLASH_FMSTAT_BUSY 0x00000100 +#define FLASH_FMSTAT_BUSY_BITN 8 +#define FLASH_FMSTAT_BUSY_M 0x00000100 +#define FLASH_FMSTAT_BUSY_S 8 // Field: [7] ERS // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_ERS 0x00000080 -#define FLASH_FMSTAT_ERS_BITN 7 -#define FLASH_FMSTAT_ERS_M 0x00000080 -#define FLASH_FMSTAT_ERS_S 7 +#define FLASH_FMSTAT_ERS 0x00000080 +#define FLASH_FMSTAT_ERS_BITN 7 +#define FLASH_FMSTAT_ERS_M 0x00000080 +#define FLASH_FMSTAT_ERS_S 7 // Field: [6] PGM // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_PGM 0x00000040 -#define FLASH_FMSTAT_PGM_BITN 6 -#define FLASH_FMSTAT_PGM_M 0x00000040 -#define FLASH_FMSTAT_PGM_S 6 +#define FLASH_FMSTAT_PGM 0x00000040 +#define FLASH_FMSTAT_PGM_BITN 6 +#define FLASH_FMSTAT_PGM_M 0x00000040 +#define FLASH_FMSTAT_PGM_S 6 // Field: [5] INVDAT // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_INVDAT 0x00000020 -#define FLASH_FMSTAT_INVDAT_BITN 5 -#define FLASH_FMSTAT_INVDAT_M 0x00000020 -#define FLASH_FMSTAT_INVDAT_S 5 +#define FLASH_FMSTAT_INVDAT 0x00000020 +#define FLASH_FMSTAT_INVDAT_BITN 5 +#define FLASH_FMSTAT_INVDAT_M 0x00000020 +#define FLASH_FMSTAT_INVDAT_S 5 // Field: [4] CSTAT // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_CSTAT 0x00000010 -#define FLASH_FMSTAT_CSTAT_BITN 4 -#define FLASH_FMSTAT_CSTAT_M 0x00000010 -#define FLASH_FMSTAT_CSTAT_S 4 +#define FLASH_FMSTAT_CSTAT 0x00000010 +#define FLASH_FMSTAT_CSTAT_BITN 4 +#define FLASH_FMSTAT_CSTAT_M 0x00000010 +#define FLASH_FMSTAT_CSTAT_S 4 // Field: [3] VOLSTAT // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_VOLSTAT 0x00000008 -#define FLASH_FMSTAT_VOLSTAT_BITN 3 -#define FLASH_FMSTAT_VOLSTAT_M 0x00000008 -#define FLASH_FMSTAT_VOLSTAT_S 3 +#define FLASH_FMSTAT_VOLSTAT 0x00000008 +#define FLASH_FMSTAT_VOLSTAT_BITN 3 +#define FLASH_FMSTAT_VOLSTAT_M 0x00000008 +#define FLASH_FMSTAT_VOLSTAT_S 3 // Field: [2] ESUSP // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_ESUSP 0x00000004 -#define FLASH_FMSTAT_ESUSP_BITN 2 -#define FLASH_FMSTAT_ESUSP_M 0x00000004 -#define FLASH_FMSTAT_ESUSP_S 2 +#define FLASH_FMSTAT_ESUSP 0x00000004 +#define FLASH_FMSTAT_ESUSP_BITN 2 +#define FLASH_FMSTAT_ESUSP_M 0x00000004 +#define FLASH_FMSTAT_ESUSP_S 2 // Field: [1] PSUSP // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_PSUSP 0x00000002 -#define FLASH_FMSTAT_PSUSP_BITN 1 -#define FLASH_FMSTAT_PSUSP_M 0x00000002 -#define FLASH_FMSTAT_PSUSP_S 1 +#define FLASH_FMSTAT_PSUSP 0x00000002 +#define FLASH_FMSTAT_PSUSP_BITN 1 +#define FLASH_FMSTAT_PSUSP_M 0x00000002 +#define FLASH_FMSTAT_PSUSP_S 1 // Field: [0] SLOCK // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_SLOCK 0x00000001 -#define FLASH_FMSTAT_SLOCK_BITN 0 -#define FLASH_FMSTAT_SLOCK_M 0x00000001 -#define FLASH_FMSTAT_SLOCK_S 0 +#define FLASH_FMSTAT_SLOCK 0x00000001 +#define FLASH_FMSTAT_SLOCK_BITN 0 +#define FLASH_FMSTAT_SLOCK_M 0x00000001 +#define FLASH_FMSTAT_SLOCK_S 0 //***************************************************************************** // @@ -1650,9 +1650,9 @@ // Field: [15:0] ENCOM // // Internal. Only to be used through TI provided API. -#define FLASH_FLOCK_ENCOM_W 16 -#define FLASH_FLOCK_ENCOM_M 0x0000FFFF -#define FLASH_FLOCK_ENCOM_S 0 +#define FLASH_FLOCK_ENCOM_W 16 +#define FLASH_FLOCK_ENCOM_M 0x0000FFFF +#define FLASH_FLOCK_ENCOM_S 0 //***************************************************************************** // @@ -1662,9 +1662,9 @@ // Field: [3:0] VREADCT // // Internal. Only to be used through TI provided API. -#define FLASH_FVREADCT_VREADCT_W 4 -#define FLASH_FVREADCT_VREADCT_M 0x0000000F -#define FLASH_FVREADCT_VREADCT_S 0 +#define FLASH_FVREADCT_VREADCT_W 4 +#define FLASH_FVREADCT_VREADCT_M 0x0000000F +#define FLASH_FVREADCT_VREADCT_S 0 //***************************************************************************** // @@ -1674,30 +1674,30 @@ // Field: [23:20] TRIM13_E // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT1_TRIM13_E_W 4 -#define FLASH_FVHVCT1_TRIM13_E_M 0x00F00000 -#define FLASH_FVHVCT1_TRIM13_E_S 20 +#define FLASH_FVHVCT1_TRIM13_E_W 4 +#define FLASH_FVHVCT1_TRIM13_E_M 0x00F00000 +#define FLASH_FVHVCT1_TRIM13_E_S 20 // Field: [19:16] VHVCT_E // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT1_VHVCT_E_W 4 -#define FLASH_FVHVCT1_VHVCT_E_M 0x000F0000 -#define FLASH_FVHVCT1_VHVCT_E_S 16 +#define FLASH_FVHVCT1_VHVCT_E_W 4 +#define FLASH_FVHVCT1_VHVCT_E_M 0x000F0000 +#define FLASH_FVHVCT1_VHVCT_E_S 16 // Field: [7:4] TRIM13_PV // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT1_TRIM13_PV_W 4 -#define FLASH_FVHVCT1_TRIM13_PV_M 0x000000F0 -#define FLASH_FVHVCT1_TRIM13_PV_S 4 +#define FLASH_FVHVCT1_TRIM13_PV_W 4 +#define FLASH_FVHVCT1_TRIM13_PV_M 0x000000F0 +#define FLASH_FVHVCT1_TRIM13_PV_S 4 // Field: [3:0] VHVCT_PV // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT1_VHVCT_PV_W 4 -#define FLASH_FVHVCT1_VHVCT_PV_M 0x0000000F -#define FLASH_FVHVCT1_VHVCT_PV_S 0 +#define FLASH_FVHVCT1_VHVCT_PV_W 4 +#define FLASH_FVHVCT1_VHVCT_PV_M 0x0000000F +#define FLASH_FVHVCT1_VHVCT_PV_S 0 //***************************************************************************** // @@ -1707,16 +1707,16 @@ // Field: [23:20] TRIM13_P // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT2_TRIM13_P_W 4 -#define FLASH_FVHVCT2_TRIM13_P_M 0x00F00000 -#define FLASH_FVHVCT2_TRIM13_P_S 20 +#define FLASH_FVHVCT2_TRIM13_P_W 4 +#define FLASH_FVHVCT2_TRIM13_P_M 0x00F00000 +#define FLASH_FVHVCT2_TRIM13_P_S 20 // Field: [19:16] VHVCT_P // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT2_VHVCT_P_W 4 -#define FLASH_FVHVCT2_VHVCT_P_M 0x000F0000 -#define FLASH_FVHVCT2_VHVCT_P_S 16 +#define FLASH_FVHVCT2_VHVCT_P_W 4 +#define FLASH_FVHVCT2_VHVCT_P_M 0x000F0000 +#define FLASH_FVHVCT2_VHVCT_P_S 16 //***************************************************************************** // @@ -1726,16 +1726,16 @@ // Field: [19:16] WCT // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT3_WCT_W 4 -#define FLASH_FVHVCT3_WCT_M 0x000F0000 -#define FLASH_FVHVCT3_WCT_S 16 +#define FLASH_FVHVCT3_WCT_W 4 +#define FLASH_FVHVCT3_WCT_M 0x000F0000 +#define FLASH_FVHVCT3_WCT_S 16 // Field: [3:0] VHVCT_READ // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT3_VHVCT_READ_W 4 -#define FLASH_FVHVCT3_VHVCT_READ_M 0x0000000F -#define FLASH_FVHVCT3_VHVCT_READ_S 0 +#define FLASH_FVHVCT3_VHVCT_READ_W 4 +#define FLASH_FVHVCT3_VHVCT_READ_M 0x0000000F +#define FLASH_FVHVCT3_VHVCT_READ_S 0 //***************************************************************************** // @@ -1745,16 +1745,16 @@ // Field: [12:8] VCG2P5CT // // Internal. Only to be used through TI provided API. -#define FLASH_FVNVCT_VCG2P5CT_W 5 -#define FLASH_FVNVCT_VCG2P5CT_M 0x00001F00 -#define FLASH_FVNVCT_VCG2P5CT_S 8 +#define FLASH_FVNVCT_VCG2P5CT_W 5 +#define FLASH_FVNVCT_VCG2P5CT_M 0x00001F00 +#define FLASH_FVNVCT_VCG2P5CT_S 8 // Field: [4:0] VIN_CT // // Internal. Only to be used through TI provided API. -#define FLASH_FVNVCT_VIN_CT_W 5 -#define FLASH_FVNVCT_VIN_CT_M 0x0000001F -#define FLASH_FVNVCT_VIN_CT_S 0 +#define FLASH_FVNVCT_VIN_CT_W 5 +#define FLASH_FVNVCT_VIN_CT_M 0x0000001F +#define FLASH_FVNVCT_VIN_CT_S 0 //***************************************************************************** // @@ -1764,9 +1764,9 @@ // Field: [15:12] VSL_P // // Internal. Only to be used through TI provided API. -#define FLASH_FVSLP_VSL_P_W 4 -#define FLASH_FVSLP_VSL_P_M 0x0000F000 -#define FLASH_FVSLP_VSL_P_S 12 +#define FLASH_FVSLP_VSL_P_W 4 +#define FLASH_FVSLP_VSL_P_M 0x0000F000 +#define FLASH_FVSLP_VSL_P_S 12 //***************************************************************************** // @@ -1776,9 +1776,9 @@ // Field: [4:0] VWLCT_P // // Internal. Only to be used through TI provided API. -#define FLASH_FVWLCT_VWLCT_P_W 5 -#define FLASH_FVWLCT_VWLCT_P_M 0x0000001F -#define FLASH_FVWLCT_VWLCT_P_S 0 +#define FLASH_FVWLCT_VWLCT_P_W 5 +#define FLASH_FVWLCT_VWLCT_P_M 0x0000001F +#define FLASH_FVWLCT_VWLCT_P_S 0 //***************************************************************************** // @@ -1788,48 +1788,48 @@ // Field: [26:24] CHAIN_SEL // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_CHAIN_SEL_W 3 -#define FLASH_FEFUSECTL_CHAIN_SEL_M 0x07000000 -#define FLASH_FEFUSECTL_CHAIN_SEL_S 24 +#define FLASH_FEFUSECTL_CHAIN_SEL_W 3 +#define FLASH_FEFUSECTL_CHAIN_SEL_M 0x07000000 +#define FLASH_FEFUSECTL_CHAIN_SEL_S 24 // Field: [17] WRITE_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_WRITE_EN 0x00020000 -#define FLASH_FEFUSECTL_WRITE_EN_BITN 17 -#define FLASH_FEFUSECTL_WRITE_EN_M 0x00020000 -#define FLASH_FEFUSECTL_WRITE_EN_S 17 +#define FLASH_FEFUSECTL_WRITE_EN 0x00020000 +#define FLASH_FEFUSECTL_WRITE_EN_BITN 17 +#define FLASH_FEFUSECTL_WRITE_EN_M 0x00020000 +#define FLASH_FEFUSECTL_WRITE_EN_S 17 // Field: [16] BP_SEL // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_BP_SEL 0x00010000 -#define FLASH_FEFUSECTL_BP_SEL_BITN 16 -#define FLASH_FEFUSECTL_BP_SEL_M 0x00010000 -#define FLASH_FEFUSECTL_BP_SEL_S 16 +#define FLASH_FEFUSECTL_BP_SEL 0x00010000 +#define FLASH_FEFUSECTL_BP_SEL_BITN 16 +#define FLASH_FEFUSECTL_BP_SEL_M 0x00010000 +#define FLASH_FEFUSECTL_BP_SEL_S 16 // Field: [8] EF_CLRZ // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_EF_CLRZ 0x00000100 -#define FLASH_FEFUSECTL_EF_CLRZ_BITN 8 -#define FLASH_FEFUSECTL_EF_CLRZ_M 0x00000100 -#define FLASH_FEFUSECTL_EF_CLRZ_S 8 +#define FLASH_FEFUSECTL_EF_CLRZ 0x00000100 +#define FLASH_FEFUSECTL_EF_CLRZ_BITN 8 +#define FLASH_FEFUSECTL_EF_CLRZ_M 0x00000100 +#define FLASH_FEFUSECTL_EF_CLRZ_S 8 // Field: [4] EF_TEST // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_EF_TEST 0x00000010 -#define FLASH_FEFUSECTL_EF_TEST_BITN 4 -#define FLASH_FEFUSECTL_EF_TEST_M 0x00000010 -#define FLASH_FEFUSECTL_EF_TEST_S 4 +#define FLASH_FEFUSECTL_EF_TEST 0x00000010 +#define FLASH_FEFUSECTL_EF_TEST_BITN 4 +#define FLASH_FEFUSECTL_EF_TEST_M 0x00000010 +#define FLASH_FEFUSECTL_EF_TEST_S 4 // Field: [3:0] EFUSE_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_EFUSE_EN_W 4 -#define FLASH_FEFUSECTL_EFUSE_EN_M 0x0000000F -#define FLASH_FEFUSECTL_EFUSE_EN_S 0 +#define FLASH_FEFUSECTL_EFUSE_EN_W 4 +#define FLASH_FEFUSECTL_EFUSE_EN_M 0x0000000F +#define FLASH_FEFUSECTL_EFUSE_EN_S 0 //***************************************************************************** // @@ -1839,10 +1839,10 @@ // Field: [0] SHIFT_DONE // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSESTAT_SHIFT_DONE 0x00000001 -#define FLASH_FEFUSESTAT_SHIFT_DONE_BITN 0 -#define FLASH_FEFUSESTAT_SHIFT_DONE_M 0x00000001 -#define FLASH_FEFUSESTAT_SHIFT_DONE_S 0 +#define FLASH_FEFUSESTAT_SHIFT_DONE 0x00000001 +#define FLASH_FEFUSESTAT_SHIFT_DONE_BITN 0 +#define FLASH_FEFUSESTAT_SHIFT_DONE_M 0x00000001 +#define FLASH_FEFUSESTAT_SHIFT_DONE_S 0 //***************************************************************************** // @@ -1852,9 +1852,9 @@ // Field: [31:0] FEFUSEDATA // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSEDATA_FEFUSEDATA_W 32 -#define FLASH_FEFUSEDATA_FEFUSEDATA_M 0xFFFFFFFF -#define FLASH_FEFUSEDATA_FEFUSEDATA_S 0 +#define FLASH_FEFUSEDATA_FEFUSEDATA_W 32 +#define FLASH_FEFUSEDATA_FEFUSEDATA_M 0xFFFFFFFF +#define FLASH_FEFUSEDATA_FEFUSEDATA_S 0 //***************************************************************************** // @@ -1864,38 +1864,38 @@ // Field: [27:24] TRIM_3P4 // // Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_TRIM_3P4_W 4 -#define FLASH_FSEQPMP_TRIM_3P4_M 0x0F000000 -#define FLASH_FSEQPMP_TRIM_3P4_S 24 +#define FLASH_FSEQPMP_TRIM_3P4_W 4 +#define FLASH_FSEQPMP_TRIM_3P4_M 0x0F000000 +#define FLASH_FSEQPMP_TRIM_3P4_S 24 // Field: [21:20] TRIM_1P7 // // Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_TRIM_1P7_W 2 -#define FLASH_FSEQPMP_TRIM_1P7_M 0x00300000 -#define FLASH_FSEQPMP_TRIM_1P7_S 20 +#define FLASH_FSEQPMP_TRIM_1P7_W 2 +#define FLASH_FSEQPMP_TRIM_1P7_M 0x00300000 +#define FLASH_FSEQPMP_TRIM_1P7_S 20 // Field: [19:16] TRIM_0P8 // // Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_TRIM_0P8_W 4 -#define FLASH_FSEQPMP_TRIM_0P8_M 0x000F0000 -#define FLASH_FSEQPMP_TRIM_0P8_S 16 +#define FLASH_FSEQPMP_TRIM_0P8_W 4 +#define FLASH_FSEQPMP_TRIM_0P8_M 0x000F0000 +#define FLASH_FSEQPMP_TRIM_0P8_S 16 // Field: [14:12] VIN_AT_X // // Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_VIN_AT_X_W 3 -#define FLASH_FSEQPMP_VIN_AT_X_M 0x00007000 -#define FLASH_FSEQPMP_VIN_AT_X_S 12 +#define FLASH_FSEQPMP_VIN_AT_X_W 3 +#define FLASH_FSEQPMP_VIN_AT_X_M 0x00007000 +#define FLASH_FSEQPMP_VIN_AT_X_S 12 // Field: [8] VIN_BY_PASS // // Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_VIN_BY_PASS 0x00000100 -#define FLASH_FSEQPMP_VIN_BY_PASS_BITN 8 -#define FLASH_FSEQPMP_VIN_BY_PASS_M 0x00000100 -#define FLASH_FSEQPMP_VIN_BY_PASS_S 8 +#define FLASH_FSEQPMP_VIN_BY_PASS 0x00000100 +#define FLASH_FSEQPMP_VIN_BY_PASS_BITN 8 +#define FLASH_FSEQPMP_VIN_BY_PASS_M 0x00000100 +#define FLASH_FSEQPMP_VIN_BY_PASS_S 8 //***************************************************************************** // @@ -1905,82 +1905,82 @@ // Field: [24] ECBIT // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_ECBIT 0x01000000 -#define FLASH_FBSTROBES_ECBIT_BITN 24 -#define FLASH_FBSTROBES_ECBIT_M 0x01000000 -#define FLASH_FBSTROBES_ECBIT_S 24 +#define FLASH_FBSTROBES_ECBIT 0x01000000 +#define FLASH_FBSTROBES_ECBIT_BITN 24 +#define FLASH_FBSTROBES_ECBIT_M 0x01000000 +#define FLASH_FBSTROBES_ECBIT_S 24 // Field: [18] RWAIT2_FLCLK // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_RWAIT2_FLCLK 0x00040000 -#define FLASH_FBSTROBES_RWAIT2_FLCLK_BITN 18 -#define FLASH_FBSTROBES_RWAIT2_FLCLK_M 0x00040000 -#define FLASH_FBSTROBES_RWAIT2_FLCLK_S 18 +#define FLASH_FBSTROBES_RWAIT2_FLCLK 0x00040000 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_BITN 18 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_M 0x00040000 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_S 18 // Field: [17] RWAIT_FLCLK // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_RWAIT_FLCLK 0x00020000 -#define FLASH_FBSTROBES_RWAIT_FLCLK_BITN 17 -#define FLASH_FBSTROBES_RWAIT_FLCLK_M 0x00020000 -#define FLASH_FBSTROBES_RWAIT_FLCLK_S 17 +#define FLASH_FBSTROBES_RWAIT_FLCLK 0x00020000 +#define FLASH_FBSTROBES_RWAIT_FLCLK_BITN 17 +#define FLASH_FBSTROBES_RWAIT_FLCLK_M 0x00020000 +#define FLASH_FBSTROBES_RWAIT_FLCLK_S 17 // Field: [16] FLCLKEN // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_FLCLKEN 0x00010000 -#define FLASH_FBSTROBES_FLCLKEN_BITN 16 -#define FLASH_FBSTROBES_FLCLKEN_M 0x00010000 -#define FLASH_FBSTROBES_FLCLKEN_S 16 +#define FLASH_FBSTROBES_FLCLKEN 0x00010000 +#define FLASH_FBSTROBES_FLCLKEN_BITN 16 +#define FLASH_FBSTROBES_FLCLKEN_M 0x00010000 +#define FLASH_FBSTROBES_FLCLKEN_S 16 // Field: [8] CTRLENZ // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_CTRLENZ 0x00000100 -#define FLASH_FBSTROBES_CTRLENZ_BITN 8 -#define FLASH_FBSTROBES_CTRLENZ_M 0x00000100 -#define FLASH_FBSTROBES_CTRLENZ_S 8 +#define FLASH_FBSTROBES_CTRLENZ 0x00000100 +#define FLASH_FBSTROBES_CTRLENZ_BITN 8 +#define FLASH_FBSTROBES_CTRLENZ_M 0x00000100 +#define FLASH_FBSTROBES_CTRLENZ_S 8 // Field: [6] NOCOLRED // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_NOCOLRED 0x00000040 -#define FLASH_FBSTROBES_NOCOLRED_BITN 6 -#define FLASH_FBSTROBES_NOCOLRED_M 0x00000040 -#define FLASH_FBSTROBES_NOCOLRED_S 6 +#define FLASH_FBSTROBES_NOCOLRED 0x00000040 +#define FLASH_FBSTROBES_NOCOLRED_BITN 6 +#define FLASH_FBSTROBES_NOCOLRED_M 0x00000040 +#define FLASH_FBSTROBES_NOCOLRED_S 6 // Field: [5] PRECOL // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_PRECOL 0x00000020 -#define FLASH_FBSTROBES_PRECOL_BITN 5 -#define FLASH_FBSTROBES_PRECOL_M 0x00000020 -#define FLASH_FBSTROBES_PRECOL_S 5 +#define FLASH_FBSTROBES_PRECOL 0x00000020 +#define FLASH_FBSTROBES_PRECOL_BITN 5 +#define FLASH_FBSTROBES_PRECOL_M 0x00000020 +#define FLASH_FBSTROBES_PRECOL_S 5 // Field: [4] TI_OTP // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_TI_OTP 0x00000010 -#define FLASH_FBSTROBES_TI_OTP_BITN 4 -#define FLASH_FBSTROBES_TI_OTP_M 0x00000010 -#define FLASH_FBSTROBES_TI_OTP_S 4 +#define FLASH_FBSTROBES_TI_OTP 0x00000010 +#define FLASH_FBSTROBES_TI_OTP_BITN 4 +#define FLASH_FBSTROBES_TI_OTP_M 0x00000010 +#define FLASH_FBSTROBES_TI_OTP_S 4 // Field: [3] OTP // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_OTP 0x00000008 -#define FLASH_FBSTROBES_OTP_BITN 3 -#define FLASH_FBSTROBES_OTP_M 0x00000008 -#define FLASH_FBSTROBES_OTP_S 3 +#define FLASH_FBSTROBES_OTP 0x00000008 +#define FLASH_FBSTROBES_OTP_BITN 3 +#define FLASH_FBSTROBES_OTP_M 0x00000008 +#define FLASH_FBSTROBES_OTP_S 3 // Field: [2] TEZ // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_TEZ 0x00000004 -#define FLASH_FBSTROBES_TEZ_BITN 2 -#define FLASH_FBSTROBES_TEZ_M 0x00000004 -#define FLASH_FBSTROBES_TEZ_S 2 +#define FLASH_FBSTROBES_TEZ 0x00000004 +#define FLASH_FBSTROBES_TEZ_BITN 2 +#define FLASH_FBSTROBES_TEZ_M 0x00000004 +#define FLASH_FBSTROBES_TEZ_S 2 //***************************************************************************** // @@ -1990,26 +1990,26 @@ // Field: [8] EXECUTEZ // // Internal. Only to be used through TI provided API. -#define FLASH_FPSTROBES_EXECUTEZ 0x00000100 -#define FLASH_FPSTROBES_EXECUTEZ_BITN 8 -#define FLASH_FPSTROBES_EXECUTEZ_M 0x00000100 -#define FLASH_FPSTROBES_EXECUTEZ_S 8 +#define FLASH_FPSTROBES_EXECUTEZ 0x00000100 +#define FLASH_FPSTROBES_EXECUTEZ_BITN 8 +#define FLASH_FPSTROBES_EXECUTEZ_M 0x00000100 +#define FLASH_FPSTROBES_EXECUTEZ_S 8 // Field: [1] V3PWRDNZ // // Internal. Only to be used through TI provided API. -#define FLASH_FPSTROBES_V3PWRDNZ 0x00000002 -#define FLASH_FPSTROBES_V3PWRDNZ_BITN 1 -#define FLASH_FPSTROBES_V3PWRDNZ_M 0x00000002 -#define FLASH_FPSTROBES_V3PWRDNZ_S 1 +#define FLASH_FPSTROBES_V3PWRDNZ 0x00000002 +#define FLASH_FPSTROBES_V3PWRDNZ_BITN 1 +#define FLASH_FPSTROBES_V3PWRDNZ_M 0x00000002 +#define FLASH_FPSTROBES_V3PWRDNZ_S 1 // Field: [0] V5PWRDNZ // // Internal. Only to be used through TI provided API. -#define FLASH_FPSTROBES_V5PWRDNZ 0x00000001 -#define FLASH_FPSTROBES_V5PWRDNZ_BITN 0 -#define FLASH_FPSTROBES_V5PWRDNZ_M 0x00000001 -#define FLASH_FPSTROBES_V5PWRDNZ_S 0 +#define FLASH_FPSTROBES_V5PWRDNZ 0x00000001 +#define FLASH_FPSTROBES_V5PWRDNZ_BITN 0 +#define FLASH_FPSTROBES_V5PWRDNZ_M 0x00000001 +#define FLASH_FPSTROBES_V5PWRDNZ_S 0 //***************************************************************************** // @@ -2019,9 +2019,9 @@ // Field: [2:0] MODE // // Internal. Only to be used through TI provided API. -#define FLASH_FBMODE_MODE_W 3 -#define FLASH_FBMODE_MODE_M 0x00000007 -#define FLASH_FBMODE_MODE_S 0 +#define FLASH_FBMODE_MODE_W 3 +#define FLASH_FBMODE_MODE_M 0x00000007 +#define FLASH_FBMODE_MODE_S 0 //***************************************************************************** // @@ -2031,9 +2031,9 @@ // Field: [6:0] TCR // // Internal. Only to be used through TI provided API. -#define FLASH_FTCR_TCR_W 7 -#define FLASH_FTCR_TCR_M 0x0000007F -#define FLASH_FTCR_TCR_S 0 +#define FLASH_FTCR_TCR_W 7 +#define FLASH_FTCR_TCR_M 0x0000007F +#define FLASH_FTCR_TCR_S 0 //***************************************************************************** // @@ -2043,9 +2043,9 @@ // Field: [31:0] FADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FADDR_FADDR_W 32 -#define FLASH_FADDR_FADDR_M 0xFFFFFFFF -#define FLASH_FADDR_FADDR_S 0 +#define FLASH_FADDR_FADDR_W 32 +#define FLASH_FADDR_FADDR_M 0xFFFFFFFF +#define FLASH_FADDR_FADDR_S 0 //***************************************************************************** // @@ -2055,18 +2055,18 @@ // Field: [16] WDATA_BLK_CLR // // Internal. Only to be used through TI provided API. -#define FLASH_FTCTL_WDATA_BLK_CLR 0x00010000 -#define FLASH_FTCTL_WDATA_BLK_CLR_BITN 16 -#define FLASH_FTCTL_WDATA_BLK_CLR_M 0x00010000 -#define FLASH_FTCTL_WDATA_BLK_CLR_S 16 +#define FLASH_FTCTL_WDATA_BLK_CLR 0x00010000 +#define FLASH_FTCTL_WDATA_BLK_CLR_BITN 16 +#define FLASH_FTCTL_WDATA_BLK_CLR_M 0x00010000 +#define FLASH_FTCTL_WDATA_BLK_CLR_S 16 // Field: [1] TEST_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FTCTL_TEST_EN 0x00000002 -#define FLASH_FTCTL_TEST_EN_BITN 1 -#define FLASH_FTCTL_TEST_EN_M 0x00000002 -#define FLASH_FTCTL_TEST_EN_S 1 +#define FLASH_FTCTL_TEST_EN 0x00000002 +#define FLASH_FTCTL_TEST_EN_BITN 1 +#define FLASH_FTCTL_TEST_EN_M 0x00000002 +#define FLASH_FTCTL_TEST_EN_S 1 //***************************************************************************** // @@ -2076,9 +2076,9 @@ // Field: [31:0] FWPWRITE0 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE0_FWPWRITE0_W 32 -#define FLASH_FWPWRITE0_FWPWRITE0_M 0xFFFFFFFF -#define FLASH_FWPWRITE0_FWPWRITE0_S 0 +#define FLASH_FWPWRITE0_FWPWRITE0_W 32 +#define FLASH_FWPWRITE0_FWPWRITE0_M 0xFFFFFFFF +#define FLASH_FWPWRITE0_FWPWRITE0_S 0 //***************************************************************************** // @@ -2088,9 +2088,9 @@ // Field: [31:0] FWPWRITE1 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE1_FWPWRITE1_W 32 -#define FLASH_FWPWRITE1_FWPWRITE1_M 0xFFFFFFFF -#define FLASH_FWPWRITE1_FWPWRITE1_S 0 +#define FLASH_FWPWRITE1_FWPWRITE1_W 32 +#define FLASH_FWPWRITE1_FWPWRITE1_M 0xFFFFFFFF +#define FLASH_FWPWRITE1_FWPWRITE1_S 0 //***************************************************************************** // @@ -2100,9 +2100,9 @@ // Field: [31:0] FWPWRITE2 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE2_FWPWRITE2_W 32 -#define FLASH_FWPWRITE2_FWPWRITE2_M 0xFFFFFFFF -#define FLASH_FWPWRITE2_FWPWRITE2_S 0 +#define FLASH_FWPWRITE2_FWPWRITE2_W 32 +#define FLASH_FWPWRITE2_FWPWRITE2_M 0xFFFFFFFF +#define FLASH_FWPWRITE2_FWPWRITE2_S 0 //***************************************************************************** // @@ -2112,9 +2112,9 @@ // Field: [31:0] FWPWRITE3 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE3_FWPWRITE3_W 32 -#define FLASH_FWPWRITE3_FWPWRITE3_M 0xFFFFFFFF -#define FLASH_FWPWRITE3_FWPWRITE3_S 0 +#define FLASH_FWPWRITE3_FWPWRITE3_W 32 +#define FLASH_FWPWRITE3_FWPWRITE3_M 0xFFFFFFFF +#define FLASH_FWPWRITE3_FWPWRITE3_S 0 //***************************************************************************** // @@ -2124,9 +2124,9 @@ // Field: [31:0] FWPWRITE4 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE4_FWPWRITE4_W 32 -#define FLASH_FWPWRITE4_FWPWRITE4_M 0xFFFFFFFF -#define FLASH_FWPWRITE4_FWPWRITE4_S 0 +#define FLASH_FWPWRITE4_FWPWRITE4_W 32 +#define FLASH_FWPWRITE4_FWPWRITE4_M 0xFFFFFFFF +#define FLASH_FWPWRITE4_FWPWRITE4_S 0 //***************************************************************************** // @@ -2136,9 +2136,9 @@ // Field: [31:0] FWPWRITE5 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE5_FWPWRITE5_W 32 -#define FLASH_FWPWRITE5_FWPWRITE5_M 0xFFFFFFFF -#define FLASH_FWPWRITE5_FWPWRITE5_S 0 +#define FLASH_FWPWRITE5_FWPWRITE5_W 32 +#define FLASH_FWPWRITE5_FWPWRITE5_M 0xFFFFFFFF +#define FLASH_FWPWRITE5_FWPWRITE5_S 0 //***************************************************************************** // @@ -2148,9 +2148,9 @@ // Field: [31:0] FWPWRITE6 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE6_FWPWRITE6_W 32 -#define FLASH_FWPWRITE6_FWPWRITE6_M 0xFFFFFFFF -#define FLASH_FWPWRITE6_FWPWRITE6_S 0 +#define FLASH_FWPWRITE6_FWPWRITE6_W 32 +#define FLASH_FWPWRITE6_FWPWRITE6_M 0xFFFFFFFF +#define FLASH_FWPWRITE6_FWPWRITE6_S 0 //***************************************************************************** // @@ -2160,9 +2160,9 @@ // Field: [31:0] FWPWRITE7 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE7_FWPWRITE7_W 32 -#define FLASH_FWPWRITE7_FWPWRITE7_M 0xFFFFFFFF -#define FLASH_FWPWRITE7_FWPWRITE7_S 0 +#define FLASH_FWPWRITE7_FWPWRITE7_W 32 +#define FLASH_FWPWRITE7_FWPWRITE7_M 0xFFFFFFFF +#define FLASH_FWPWRITE7_FWPWRITE7_S 0 //***************************************************************************** // @@ -2172,30 +2172,30 @@ // Field: [31:24] ECCBYTES07_00 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_W 8 -#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_M 0xFF000000 -#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_S 24 +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_M 0xFF000000 +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_S 24 // Field: [23:16] ECCBYTES15_08 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_W 8 -#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_M 0x00FF0000 -#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_S 16 +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_M 0x00FF0000 +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_S 16 // Field: [15:8] ECCBYTES23_16 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_W 8 -#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_M 0x0000FF00 -#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_S 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_M 0x0000FF00 +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_S 8 // Field: [7:0] ECCBYTES31_24 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_W 8 -#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_M 0x000000FF -#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_S 0 +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_M 0x000000FF +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_S 0 //***************************************************************************** // @@ -2205,10 +2205,10 @@ // Field: [0] SAFELV // // Internal. Only to be used through TI provided API. -#define FLASH_FSWSTAT_SAFELV 0x00000001 -#define FLASH_FSWSTAT_SAFELV_BITN 0 -#define FLASH_FSWSTAT_SAFELV_M 0x00000001 -#define FLASH_FSWSTAT_SAFELV_S 0 +#define FLASH_FSWSTAT_SAFELV 0x00000001 +#define FLASH_FSWSTAT_SAFELV_BITN 0 +#define FLASH_FSWSTAT_SAFELV_M 0x00000001 +#define FLASH_FSWSTAT_SAFELV_S 0 //***************************************************************************** // @@ -2218,10 +2218,10 @@ // Field: [0] CLKSEL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_GLBCTL_CLKSEL 0x00000001 -#define FLASH_FSM_GLBCTL_CLKSEL_BITN 0 -#define FLASH_FSM_GLBCTL_CLKSEL_M 0x00000001 -#define FLASH_FSM_GLBCTL_CLKSEL_S 0 +#define FLASH_FSM_GLBCTL_CLKSEL 0x00000001 +#define FLASH_FSM_GLBCTL_CLKSEL_BITN 0 +#define FLASH_FSM_GLBCTL_CLKSEL_M 0x00000001 +#define FLASH_FSM_GLBCTL_CLKSEL_S 0 //***************************************************************************** // @@ -2231,42 +2231,42 @@ // Field: [11] CTRLENZ // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_CTRLENZ 0x00000800 -#define FLASH_FSM_STATE_CTRLENZ_BITN 11 -#define FLASH_FSM_STATE_CTRLENZ_M 0x00000800 -#define FLASH_FSM_STATE_CTRLENZ_S 11 +#define FLASH_FSM_STATE_CTRLENZ 0x00000800 +#define FLASH_FSM_STATE_CTRLENZ_BITN 11 +#define FLASH_FSM_STATE_CTRLENZ_M 0x00000800 +#define FLASH_FSM_STATE_CTRLENZ_S 11 // Field: [10] EXECUTEZ // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_EXECUTEZ 0x00000400 -#define FLASH_FSM_STATE_EXECUTEZ_BITN 10 -#define FLASH_FSM_STATE_EXECUTEZ_M 0x00000400 -#define FLASH_FSM_STATE_EXECUTEZ_S 10 +#define FLASH_FSM_STATE_EXECUTEZ 0x00000400 +#define FLASH_FSM_STATE_EXECUTEZ_BITN 10 +#define FLASH_FSM_STATE_EXECUTEZ_M 0x00000400 +#define FLASH_FSM_STATE_EXECUTEZ_S 10 // Field: [8] FSM_ACT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_FSM_ACT 0x00000100 -#define FLASH_FSM_STATE_FSM_ACT_BITN 8 -#define FLASH_FSM_STATE_FSM_ACT_M 0x00000100 -#define FLASH_FSM_STATE_FSM_ACT_S 8 +#define FLASH_FSM_STATE_FSM_ACT 0x00000100 +#define FLASH_FSM_STATE_FSM_ACT_BITN 8 +#define FLASH_FSM_STATE_FSM_ACT_M 0x00000100 +#define FLASH_FSM_STATE_FSM_ACT_S 8 // Field: [7] TIOTP_ACT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_TIOTP_ACT 0x00000080 -#define FLASH_FSM_STATE_TIOTP_ACT_BITN 7 -#define FLASH_FSM_STATE_TIOTP_ACT_M 0x00000080 -#define FLASH_FSM_STATE_TIOTP_ACT_S 7 +#define FLASH_FSM_STATE_TIOTP_ACT 0x00000080 +#define FLASH_FSM_STATE_TIOTP_ACT_BITN 7 +#define FLASH_FSM_STATE_TIOTP_ACT_M 0x00000080 +#define FLASH_FSM_STATE_TIOTP_ACT_S 7 // Field: [6] OTP_ACT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_OTP_ACT 0x00000040 -#define FLASH_FSM_STATE_OTP_ACT_BITN 6 -#define FLASH_FSM_STATE_OTP_ACT_M 0x00000040 -#define FLASH_FSM_STATE_OTP_ACT_S 6 +#define FLASH_FSM_STATE_OTP_ACT 0x00000040 +#define FLASH_FSM_STATE_OTP_ACT_BITN 6 +#define FLASH_FSM_STATE_OTP_ACT_M 0x00000040 +#define FLASH_FSM_STATE_OTP_ACT_S 6 //***************************************************************************** // @@ -2276,26 +2276,26 @@ // Field: [2] NON_OP // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STAT_NON_OP 0x00000004 -#define FLASH_FSM_STAT_NON_OP_BITN 2 -#define FLASH_FSM_STAT_NON_OP_M 0x00000004 -#define FLASH_FSM_STAT_NON_OP_S 2 +#define FLASH_FSM_STAT_NON_OP 0x00000004 +#define FLASH_FSM_STAT_NON_OP_BITN 2 +#define FLASH_FSM_STAT_NON_OP_M 0x00000004 +#define FLASH_FSM_STAT_NON_OP_S 2 // Field: [1] OVR_PUL_CNT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STAT_OVR_PUL_CNT 0x00000002 -#define FLASH_FSM_STAT_OVR_PUL_CNT_BITN 1 -#define FLASH_FSM_STAT_OVR_PUL_CNT_M 0x00000002 -#define FLASH_FSM_STAT_OVR_PUL_CNT_S 1 +#define FLASH_FSM_STAT_OVR_PUL_CNT 0x00000002 +#define FLASH_FSM_STAT_OVR_PUL_CNT_BITN 1 +#define FLASH_FSM_STAT_OVR_PUL_CNT_M 0x00000002 +#define FLASH_FSM_STAT_OVR_PUL_CNT_S 1 // Field: [0] INV_DAT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STAT_INV_DAT 0x00000001 -#define FLASH_FSM_STAT_INV_DAT_BITN 0 -#define FLASH_FSM_STAT_INV_DAT_M 0x00000001 -#define FLASH_FSM_STAT_INV_DAT_S 0 +#define FLASH_FSM_STAT_INV_DAT 0x00000001 +#define FLASH_FSM_STAT_INV_DAT_BITN 0 +#define FLASH_FSM_STAT_INV_DAT_M 0x00000001 +#define FLASH_FSM_STAT_INV_DAT_S 0 //***************************************************************************** // @@ -2305,9 +2305,9 @@ // Field: [5:0] FSMCMD // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_CMD_FSMCMD_W 6 -#define FLASH_FSM_CMD_FSMCMD_M 0x0000003F -#define FLASH_FSM_CMD_FSMCMD_S 0 +#define FLASH_FSM_CMD_FSMCMD_W 6 +#define FLASH_FSM_CMD_FSMCMD_M 0x0000003F +#define FLASH_FSM_CMD_FSMCMD_S 0 //***************************************************************************** // @@ -2317,16 +2317,16 @@ // Field: [15:8] PGM_OSU // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_OSU_PGM_OSU_W 8 -#define FLASH_FSM_PE_OSU_PGM_OSU_M 0x0000FF00 -#define FLASH_FSM_PE_OSU_PGM_OSU_S 8 +#define FLASH_FSM_PE_OSU_PGM_OSU_W 8 +#define FLASH_FSM_PE_OSU_PGM_OSU_M 0x0000FF00 +#define FLASH_FSM_PE_OSU_PGM_OSU_S 8 // Field: [7:0] ERA_OSU // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_OSU_ERA_OSU_W 8 -#define FLASH_FSM_PE_OSU_ERA_OSU_M 0x000000FF -#define FLASH_FSM_PE_OSU_ERA_OSU_S 0 +#define FLASH_FSM_PE_OSU_ERA_OSU_W 8 +#define FLASH_FSM_PE_OSU_ERA_OSU_M 0x000000FF +#define FLASH_FSM_PE_OSU_ERA_OSU_S 0 //***************************************************************************** // @@ -2336,9 +2336,9 @@ // Field: [15:12] VSTAT_CNT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_VSTAT_VSTAT_CNT_W 4 -#define FLASH_FSM_VSTAT_VSTAT_CNT_M 0x0000F000 -#define FLASH_FSM_VSTAT_VSTAT_CNT_S 12 +#define FLASH_FSM_VSTAT_VSTAT_CNT_W 4 +#define FLASH_FSM_VSTAT_VSTAT_CNT_M 0x0000F000 +#define FLASH_FSM_VSTAT_VSTAT_CNT_S 12 //***************************************************************************** // @@ -2348,16 +2348,16 @@ // Field: [15:8] PGM_VSU // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_VSU_PGM_VSU_W 8 -#define FLASH_FSM_PE_VSU_PGM_VSU_M 0x0000FF00 -#define FLASH_FSM_PE_VSU_PGM_VSU_S 8 +#define FLASH_FSM_PE_VSU_PGM_VSU_W 8 +#define FLASH_FSM_PE_VSU_PGM_VSU_M 0x0000FF00 +#define FLASH_FSM_PE_VSU_PGM_VSU_S 8 // Field: [7:0] ERA_VSU // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_VSU_ERA_VSU_W 8 -#define FLASH_FSM_PE_VSU_ERA_VSU_M 0x000000FF -#define FLASH_FSM_PE_VSU_ERA_VSU_S 0 +#define FLASH_FSM_PE_VSU_ERA_VSU_W 8 +#define FLASH_FSM_PE_VSU_ERA_VSU_M 0x000000FF +#define FLASH_FSM_PE_VSU_ERA_VSU_S 0 //***************************************************************************** // @@ -2367,9 +2367,9 @@ // Field: [15:12] ADD_EXZ // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_CMP_VSU_ADD_EXZ_W 4 -#define FLASH_FSM_CMP_VSU_ADD_EXZ_M 0x0000F000 -#define FLASH_FSM_CMP_VSU_ADD_EXZ_S 12 +#define FLASH_FSM_CMP_VSU_ADD_EXZ_W 4 +#define FLASH_FSM_CMP_VSU_ADD_EXZ_M 0x0000F000 +#define FLASH_FSM_CMP_VSU_ADD_EXZ_S 12 //***************************************************************************** // @@ -2379,16 +2379,16 @@ // Field: [15:8] REP_VSU // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_EX_VAL_REP_VSU_W 8 -#define FLASH_FSM_EX_VAL_REP_VSU_M 0x0000FF00 -#define FLASH_FSM_EX_VAL_REP_VSU_S 8 +#define FLASH_FSM_EX_VAL_REP_VSU_W 8 +#define FLASH_FSM_EX_VAL_REP_VSU_M 0x0000FF00 +#define FLASH_FSM_EX_VAL_REP_VSU_S 8 // Field: [7:0] EXE_VALD // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_EX_VAL_EXE_VALD_W 8 -#define FLASH_FSM_EX_VAL_EXE_VALD_M 0x000000FF -#define FLASH_FSM_EX_VAL_EXE_VALD_S 0 +#define FLASH_FSM_EX_VAL_EXE_VALD_W 8 +#define FLASH_FSM_EX_VAL_EXE_VALD_M 0x000000FF +#define FLASH_FSM_EX_VAL_EXE_VALD_S 0 //***************************************************************************** // @@ -2398,9 +2398,9 @@ // Field: [7:0] RD_H // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_RD_H_RD_H_W 8 -#define FLASH_FSM_RD_H_RD_H_M 0x000000FF -#define FLASH_FSM_RD_H_RD_H_S 0 +#define FLASH_FSM_RD_H_RD_H_W 8 +#define FLASH_FSM_RD_H_RD_H_M 0x000000FF +#define FLASH_FSM_RD_H_RD_H_S 0 //***************************************************************************** // @@ -2410,9 +2410,9 @@ // Field: [15:8] PGM_OH // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_P_OH_PGM_OH_W 8 -#define FLASH_FSM_P_OH_PGM_OH_M 0x0000FF00 -#define FLASH_FSM_P_OH_PGM_OH_S 8 +#define FLASH_FSM_P_OH_PGM_OH_W 8 +#define FLASH_FSM_P_OH_PGM_OH_M 0x0000FF00 +#define FLASH_FSM_P_OH_PGM_OH_S 8 //***************************************************************************** // @@ -2422,9 +2422,9 @@ // Field: [15:0] ERA_OH // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_OH_ERA_OH_W 16 -#define FLASH_FSM_ERA_OH_ERA_OH_M 0x0000FFFF -#define FLASH_FSM_ERA_OH_ERA_OH_S 0 +#define FLASH_FSM_ERA_OH_ERA_OH_W 16 +#define FLASH_FSM_ERA_OH_ERA_OH_M 0x0000FFFF +#define FLASH_FSM_ERA_OH_ERA_OH_S 0 //***************************************************************************** // @@ -2434,9 +2434,9 @@ // Field: [11:0] SAV_P_PUL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_W 12 -#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_M 0x00000FFF -#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_S 0 +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_W 12 +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_M 0x00000FFF +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_S 0 //***************************************************************************** // @@ -2446,9 +2446,9 @@ // Field: [15:8] PGM_VH // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_VH_PGM_VH_W 8 -#define FLASH_FSM_PE_VH_PGM_VH_M 0x0000FF00 -#define FLASH_FSM_PE_VH_PGM_VH_S 8 +#define FLASH_FSM_PE_VH_PGM_VH_W 8 +#define FLASH_FSM_PE_VH_PGM_VH_M 0x0000FF00 +#define FLASH_FSM_PE_VH_PGM_VH_S 8 //***************************************************************************** // @@ -2458,9 +2458,9 @@ // Field: [15:0] PROG_PUL_WIDTH // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_W 16 -#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M 0x0000FFFF -#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S 0 +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_W 16 +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M 0x0000FFFF +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S 0 //***************************************************************************** // @@ -2470,9 +2470,9 @@ // Field: [31:0] FSM_ERA_PW // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_PW_FSM_ERA_PW_W 32 -#define FLASH_FSM_ERA_PW_FSM_ERA_PW_M 0xFFFFFFFF -#define FLASH_FSM_ERA_PW_FSM_ERA_PW_S 0 +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_W 32 +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_M 0xFFFFFFFF +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_S 0 //***************************************************************************** // @@ -2482,9 +2482,9 @@ // Field: [11:0] SAV_ERA_PUL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_W 12 -#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_M 0x00000FFF -#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_S 0 +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_W 12 +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_M 0x00000FFF +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_S 0 //***************************************************************************** // @@ -2494,9 +2494,9 @@ // Field: [31:0] FSM_TIMER // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_TIMER_FSM_TIMER_W 32 -#define FLASH_FSM_TIMER_FSM_TIMER_M 0xFFFFFFFF -#define FLASH_FSM_TIMER_FSM_TIMER_S 0 +#define FLASH_FSM_TIMER_FSM_TIMER_W 32 +#define FLASH_FSM_TIMER_FSM_TIMER_M 0xFFFFFFFF +#define FLASH_FSM_TIMER_FSM_TIMER_S 0 //***************************************************************************** // @@ -2506,58 +2506,58 @@ // Field: [19:18] RDV_SUBMODE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_RDV_SUBMODE_W 2 -#define FLASH_FSM_MODE_RDV_SUBMODE_M 0x000C0000 -#define FLASH_FSM_MODE_RDV_SUBMODE_S 18 +#define FLASH_FSM_MODE_RDV_SUBMODE_W 2 +#define FLASH_FSM_MODE_RDV_SUBMODE_M 0x000C0000 +#define FLASH_FSM_MODE_RDV_SUBMODE_S 18 // Field: [17:16] PGM_SUBMODE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_PGM_SUBMODE_W 2 -#define FLASH_FSM_MODE_PGM_SUBMODE_M 0x00030000 -#define FLASH_FSM_MODE_PGM_SUBMODE_S 16 +#define FLASH_FSM_MODE_PGM_SUBMODE_W 2 +#define FLASH_FSM_MODE_PGM_SUBMODE_M 0x00030000 +#define FLASH_FSM_MODE_PGM_SUBMODE_S 16 // Field: [15:14] ERA_SUBMODE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_ERA_SUBMODE_W 2 -#define FLASH_FSM_MODE_ERA_SUBMODE_M 0x0000C000 -#define FLASH_FSM_MODE_ERA_SUBMODE_S 14 +#define FLASH_FSM_MODE_ERA_SUBMODE_W 2 +#define FLASH_FSM_MODE_ERA_SUBMODE_M 0x0000C000 +#define FLASH_FSM_MODE_ERA_SUBMODE_S 14 // Field: [13:12] SUBMODE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_SUBMODE_W 2 -#define FLASH_FSM_MODE_SUBMODE_M 0x00003000 -#define FLASH_FSM_MODE_SUBMODE_S 12 +#define FLASH_FSM_MODE_SUBMODE_W 2 +#define FLASH_FSM_MODE_SUBMODE_M 0x00003000 +#define FLASH_FSM_MODE_SUBMODE_S 12 // Field: [11:9] SAV_PGM_CMD // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_SAV_PGM_CMD_W 3 -#define FLASH_FSM_MODE_SAV_PGM_CMD_M 0x00000E00 -#define FLASH_FSM_MODE_SAV_PGM_CMD_S 9 +#define FLASH_FSM_MODE_SAV_PGM_CMD_W 3 +#define FLASH_FSM_MODE_SAV_PGM_CMD_M 0x00000E00 +#define FLASH_FSM_MODE_SAV_PGM_CMD_S 9 // Field: [8:6] SAV_ERA_MODE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_SAV_ERA_MODE_W 3 -#define FLASH_FSM_MODE_SAV_ERA_MODE_M 0x000001C0 -#define FLASH_FSM_MODE_SAV_ERA_MODE_S 6 +#define FLASH_FSM_MODE_SAV_ERA_MODE_W 3 +#define FLASH_FSM_MODE_SAV_ERA_MODE_M 0x000001C0 +#define FLASH_FSM_MODE_SAV_ERA_MODE_S 6 // Field: [5:3] MODE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_MODE_W 3 -#define FLASH_FSM_MODE_MODE_M 0x00000038 -#define FLASH_FSM_MODE_MODE_S 3 +#define FLASH_FSM_MODE_MODE_W 3 +#define FLASH_FSM_MODE_MODE_M 0x00000038 +#define FLASH_FSM_MODE_MODE_S 3 // Field: [2:0] CMD // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_CMD_W 3 -#define FLASH_FSM_MODE_CMD_M 0x00000007 -#define FLASH_FSM_MODE_CMD_S 0 +#define FLASH_FSM_MODE_CMD_W 3 +#define FLASH_FSM_MODE_CMD_M 0x00000007 +#define FLASH_FSM_MODE_CMD_S 0 //***************************************************************************** // @@ -2567,16 +2567,16 @@ // Field: [25:23] PGM_BANK // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PGM_PGM_BANK_W 3 -#define FLASH_FSM_PGM_PGM_BANK_M 0x03800000 -#define FLASH_FSM_PGM_PGM_BANK_S 23 +#define FLASH_FSM_PGM_PGM_BANK_W 3 +#define FLASH_FSM_PGM_PGM_BANK_M 0x03800000 +#define FLASH_FSM_PGM_PGM_BANK_S 23 // Field: [22:0] PGM_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PGM_PGM_ADDR_W 23 -#define FLASH_FSM_PGM_PGM_ADDR_M 0x007FFFFF -#define FLASH_FSM_PGM_PGM_ADDR_S 0 +#define FLASH_FSM_PGM_PGM_ADDR_W 23 +#define FLASH_FSM_PGM_PGM_ADDR_M 0x007FFFFF +#define FLASH_FSM_PGM_PGM_ADDR_S 0 //***************************************************************************** // @@ -2586,16 +2586,16 @@ // Field: [25:23] ERA_BANK // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_ERA_BANK_W 3 -#define FLASH_FSM_ERA_ERA_BANK_M 0x03800000 -#define FLASH_FSM_ERA_ERA_BANK_S 23 +#define FLASH_FSM_ERA_ERA_BANK_W 3 +#define FLASH_FSM_ERA_ERA_BANK_M 0x03800000 +#define FLASH_FSM_ERA_ERA_BANK_S 23 // Field: [22:0] ERA_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_ERA_ADDR_W 23 -#define FLASH_FSM_ERA_ERA_ADDR_M 0x007FFFFF -#define FLASH_FSM_ERA_ERA_ADDR_S 0 +#define FLASH_FSM_ERA_ERA_ADDR_W 23 +#define FLASH_FSM_ERA_ERA_ADDR_M 0x007FFFFF +#define FLASH_FSM_ERA_ERA_ADDR_S 0 //***************************************************************************** // @@ -2605,16 +2605,16 @@ // Field: [19:16] BEG_EC_LEVEL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_W 4 -#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M 0x000F0000 -#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S 16 +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_W 4 +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M 0x000F0000 +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S 16 // Field: [11:0] MAX_PRG_PUL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_W 12 -#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M 0x00000FFF -#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S 0 +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_W 12 +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M 0x00000FFF +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S 0 //***************************************************************************** // @@ -2624,16 +2624,16 @@ // Field: [19:16] MAX_EC_LEVEL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_W 4 -#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M 0x000F0000 -#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S 16 +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_W 4 +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M 0x000F0000 +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S 16 // Field: [11:0] MAX_ERA_PUL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_W 12 -#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M 0x00000FFF -#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S 0 +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_W 12 +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M 0x00000FFF +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S 0 //***************************************************************************** // @@ -2643,9 +2643,9 @@ // Field: [24:16] EC_STEP_SIZE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_W 9 -#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M 0x01FF0000 -#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S 16 +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_W 9 +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M 0x01FF0000 +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S 16 //***************************************************************************** // @@ -2655,16 +2655,16 @@ // Field: [24:16] CUR_EC_LEVEL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_W 9 -#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_M 0x01FF0000 -#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_S 16 +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_W 9 +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_M 0x01FF0000 +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_S 16 // Field: [11:0] PUL_CNTR // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PUL_CNTR_PUL_CNTR_W 12 -#define FLASH_FSM_PUL_CNTR_PUL_CNTR_M 0x00000FFF -#define FLASH_FSM_PUL_CNTR_PUL_CNTR_S 0 +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_W 12 +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_M 0x00000FFF +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_S 0 //***************************************************************************** // @@ -2674,9 +2674,9 @@ // Field: [3:0] EC_STEP_HEIGHT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_W 4 -#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M 0x0000000F -#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_S 0 +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_W 4 +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M 0x0000000F +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_S 0 //***************************************************************************** // @@ -2686,137 +2686,137 @@ // Field: [23] DO_PRECOND // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_DO_PRECOND 0x00800000 -#define FLASH_FSM_ST_MACHINE_DO_PRECOND_BITN 23 -#define FLASH_FSM_ST_MACHINE_DO_PRECOND_M 0x00800000 -#define FLASH_FSM_ST_MACHINE_DO_PRECOND_S 23 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND 0x00800000 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_BITN 23 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_M 0x00800000 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_S 23 // Field: [22] FSM_INT_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_FSM_INT_EN 0x00400000 -#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_BITN 22 -#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_M 0x00400000 -#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_S 22 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN 0x00400000 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_BITN 22 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_M 0x00400000 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_S 22 // Field: [21] ALL_BANKS // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_ALL_BANKS 0x00200000 -#define FLASH_FSM_ST_MACHINE_ALL_BANKS_BITN 21 -#define FLASH_FSM_ST_MACHINE_ALL_BANKS_M 0x00200000 -#define FLASH_FSM_ST_MACHINE_ALL_BANKS_S 21 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS 0x00200000 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_BITN 21 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_M 0x00200000 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_S 21 // Field: [20] CMPV_ALLOWED // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED 0x00100000 -#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_BITN 20 -#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_M 0x00100000 -#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_S 20 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED 0x00100000 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_BITN 20 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_M 0x00100000 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_S 20 // Field: [19] RANDOM // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_RANDOM 0x00080000 -#define FLASH_FSM_ST_MACHINE_RANDOM_BITN 19 -#define FLASH_FSM_ST_MACHINE_RANDOM_M 0x00080000 -#define FLASH_FSM_ST_MACHINE_RANDOM_S 19 +#define FLASH_FSM_ST_MACHINE_RANDOM 0x00080000 +#define FLASH_FSM_ST_MACHINE_RANDOM_BITN 19 +#define FLASH_FSM_ST_MACHINE_RANDOM_M 0x00080000 +#define FLASH_FSM_ST_MACHINE_RANDOM_S 19 // Field: [18] RV_SEC_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_RV_SEC_EN 0x00040000 -#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_BITN 18 -#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_M 0x00040000 -#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_S 18 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN 0x00040000 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_BITN 18 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_M 0x00040000 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_S 18 // Field: [17] RV_RES // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_RV_RES 0x00020000 -#define FLASH_FSM_ST_MACHINE_RV_RES_BITN 17 -#define FLASH_FSM_ST_MACHINE_RV_RES_M 0x00020000 -#define FLASH_FSM_ST_MACHINE_RV_RES_S 17 +#define FLASH_FSM_ST_MACHINE_RV_RES 0x00020000 +#define FLASH_FSM_ST_MACHINE_RV_RES_BITN 17 +#define FLASH_FSM_ST_MACHINE_RV_RES_M 0x00020000 +#define FLASH_FSM_ST_MACHINE_RV_RES_S 17 // Field: [16] RV_INT_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_RV_INT_EN 0x00010000 -#define FLASH_FSM_ST_MACHINE_RV_INT_EN_BITN 16 -#define FLASH_FSM_ST_MACHINE_RV_INT_EN_M 0x00010000 -#define FLASH_FSM_ST_MACHINE_RV_INT_EN_S 16 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN 0x00010000 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_BITN 16 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_M 0x00010000 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_S 16 // Field: [14] ONE_TIME_GOOD // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD 0x00004000 -#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_BITN 14 -#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_M 0x00004000 -#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_S 14 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD 0x00004000 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_BITN 14 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_M 0x00004000 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_S 14 // Field: [11] DO_REDU_COL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_DO_REDU_COL 0x00000800 -#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_BITN 11 -#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_M 0x00000800 -#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_S 11 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL 0x00000800 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_BITN 11 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_M 0x00000800 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_S 11 // Field: [10:7] DBG_SHORT_ROW // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_W 4 -#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_M 0x00000780 -#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_S 7 +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_W 4 +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_M 0x00000780 +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_S 7 // Field: [5] PGM_SEC_COF_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN 0x00000020 -#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_BITN 5 -#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_M 0x00000020 -#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_S 5 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN 0x00000020 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_BITN 5 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_M 0x00000020 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_S 5 // Field: [4] PREC_STOP_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN 0x00000010 -#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_BITN 4 -#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_M 0x00000010 -#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_S 4 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN 0x00000010 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_BITN 4 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_M 0x00000010 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_S 4 // Field: [3] DIS_TST_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_DIS_TST_EN 0x00000008 -#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_BITN 3 -#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_M 0x00000008 -#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_S 3 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN 0x00000008 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_BITN 3 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_M 0x00000008 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_S 3 // Field: [2] CMD_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_CMD_EN 0x00000004 -#define FLASH_FSM_ST_MACHINE_CMD_EN_BITN 2 -#define FLASH_FSM_ST_MACHINE_CMD_EN_M 0x00000004 -#define FLASH_FSM_ST_MACHINE_CMD_EN_S 2 +#define FLASH_FSM_ST_MACHINE_CMD_EN 0x00000004 +#define FLASH_FSM_ST_MACHINE_CMD_EN_BITN 2 +#define FLASH_FSM_ST_MACHINE_CMD_EN_M 0x00000004 +#define FLASH_FSM_ST_MACHINE_CMD_EN_S 2 // Field: [1] INV_DATA // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_INV_DATA 0x00000002 -#define FLASH_FSM_ST_MACHINE_INV_DATA_BITN 1 -#define FLASH_FSM_ST_MACHINE_INV_DATA_M 0x00000002 -#define FLASH_FSM_ST_MACHINE_INV_DATA_S 1 +#define FLASH_FSM_ST_MACHINE_INV_DATA 0x00000002 +#define FLASH_FSM_ST_MACHINE_INV_DATA_BITN 1 +#define FLASH_FSM_ST_MACHINE_INV_DATA_M 0x00000002 +#define FLASH_FSM_ST_MACHINE_INV_DATA_S 1 // Field: [0] OVERRIDE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_OVERRIDE 0x00000001 -#define FLASH_FSM_ST_MACHINE_OVERRIDE_BITN 0 -#define FLASH_FSM_ST_MACHINE_OVERRIDE_M 0x00000001 -#define FLASH_FSM_ST_MACHINE_OVERRIDE_S 0 +#define FLASH_FSM_ST_MACHINE_OVERRIDE 0x00000001 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_BITN 0 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_M 0x00000001 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_S 0 //***************************************************************************** // @@ -2826,16 +2826,16 @@ // Field: [11:8] BLK_TIOTP // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_FLES_BLK_TIOTP_W 4 -#define FLASH_FSM_FLES_BLK_TIOTP_M 0x00000F00 -#define FLASH_FSM_FLES_BLK_TIOTP_S 8 +#define FLASH_FSM_FLES_BLK_TIOTP_W 4 +#define FLASH_FSM_FLES_BLK_TIOTP_M 0x00000F00 +#define FLASH_FSM_FLES_BLK_TIOTP_S 8 // Field: [7:0] BLK_OTP // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_FLES_BLK_OTP_W 8 -#define FLASH_FSM_FLES_BLK_OTP_M 0x000000FF -#define FLASH_FSM_FLES_BLK_OTP_S 0 +#define FLASH_FSM_FLES_BLK_OTP_W 8 +#define FLASH_FSM_FLES_BLK_OTP_M 0x000000FF +#define FLASH_FSM_FLES_BLK_OTP_S 0 //***************************************************************************** // @@ -2845,9 +2845,9 @@ // Field: [2:0] WR_ENA // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_WR_ENA_WR_ENA_W 3 -#define FLASH_FSM_WR_ENA_WR_ENA_M 0x00000007 -#define FLASH_FSM_WR_ENA_WR_ENA_S 0 +#define FLASH_FSM_WR_ENA_WR_ENA_W 3 +#define FLASH_FSM_WR_ENA_WR_ENA_M 0x00000007 +#define FLASH_FSM_WR_ENA_WR_ENA_S 0 //***************************************************************************** // @@ -2857,9 +2857,9 @@ // Field: [31:0] FSM_ACC_PP // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ACC_PP_FSM_ACC_PP_W 32 -#define FLASH_FSM_ACC_PP_FSM_ACC_PP_M 0xFFFFFFFF -#define FLASH_FSM_ACC_PP_FSM_ACC_PP_S 0 +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_W 32 +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_M 0xFFFFFFFF +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_S 0 //***************************************************************************** // @@ -2869,9 +2869,9 @@ // Field: [15:0] ACC_EP // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ACC_EP_ACC_EP_W 16 -#define FLASH_FSM_ACC_EP_ACC_EP_M 0x0000FFFF -#define FLASH_FSM_ACC_EP_ACC_EP_S 0 +#define FLASH_FSM_ACC_EP_ACC_EP_W 16 +#define FLASH_FSM_ACC_EP_ACC_EP_M 0x0000FFFF +#define FLASH_FSM_ACC_EP_ACC_EP_S 0 //***************************************************************************** // @@ -2881,16 +2881,16 @@ // Field: [30:28] BANK // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ADDR_BANK_W 3 -#define FLASH_FSM_ADDR_BANK_M 0x70000000 -#define FLASH_FSM_ADDR_BANK_S 28 +#define FLASH_FSM_ADDR_BANK_W 3 +#define FLASH_FSM_ADDR_BANK_M 0x70000000 +#define FLASH_FSM_ADDR_BANK_S 28 // Field: [27:0] CUR_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ADDR_CUR_ADDR_W 28 -#define FLASH_FSM_ADDR_CUR_ADDR_M 0x0FFFFFFF -#define FLASH_FSM_ADDR_CUR_ADDR_S 0 +#define FLASH_FSM_ADDR_CUR_ADDR_W 28 +#define FLASH_FSM_ADDR_CUR_ADDR_M 0x0FFFFFFF +#define FLASH_FSM_ADDR_CUR_ADDR_S 0 //***************************************************************************** // @@ -2900,30 +2900,30 @@ // Field: [31:16] SECT_ERASED // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR_SECT_ERASED_W 16 -#define FLASH_FSM_SECTOR_SECT_ERASED_M 0xFFFF0000 -#define FLASH_FSM_SECTOR_SECT_ERASED_S 16 +#define FLASH_FSM_SECTOR_SECT_ERASED_W 16 +#define FLASH_FSM_SECTOR_SECT_ERASED_M 0xFFFF0000 +#define FLASH_FSM_SECTOR_SECT_ERASED_S 16 // Field: [15:8] FSM_SECTOR_EXTENSION // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_W 8 -#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_M 0x0000FF00 -#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_S 8 +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_W 8 +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_M 0x0000FF00 +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_S 8 // Field: [7:4] SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR_SECTOR_W 4 -#define FLASH_FSM_SECTOR_SECTOR_M 0x000000F0 -#define FLASH_FSM_SECTOR_SECTOR_S 4 +#define FLASH_FSM_SECTOR_SECTOR_W 4 +#define FLASH_FSM_SECTOR_SECTOR_M 0x000000F0 +#define FLASH_FSM_SECTOR_SECTOR_S 4 // Field: [3:0] SEC_OUT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR_SEC_OUT_W 4 -#define FLASH_FSM_SECTOR_SEC_OUT_M 0x0000000F -#define FLASH_FSM_SECTOR_SEC_OUT_S 0 +#define FLASH_FSM_SECTOR_SEC_OUT_W 4 +#define FLASH_FSM_SECTOR_SEC_OUT_M 0x0000000F +#define FLASH_FSM_SECTOR_SEC_OUT_S 0 //***************************************************************************** // @@ -2933,16 +2933,16 @@ // Field: [31:12] MOD_VERSION // // Internal. Only to be used through TI provided API. -#define FLASH_FMC_REV_ID_MOD_VERSION_W 20 -#define FLASH_FMC_REV_ID_MOD_VERSION_M 0xFFFFF000 -#define FLASH_FMC_REV_ID_MOD_VERSION_S 12 +#define FLASH_FMC_REV_ID_MOD_VERSION_W 20 +#define FLASH_FMC_REV_ID_MOD_VERSION_M 0xFFFFF000 +#define FLASH_FMC_REV_ID_MOD_VERSION_S 12 // Field: [11:0] CONFIG_CRC // // Internal. Only to be used through TI provided API. -#define FLASH_FMC_REV_ID_CONFIG_CRC_W 12 -#define FLASH_FMC_REV_ID_CONFIG_CRC_M 0x00000FFF -#define FLASH_FMC_REV_ID_CONFIG_CRC_S 0 +#define FLASH_FMC_REV_ID_CONFIG_CRC_W 12 +#define FLASH_FMC_REV_ID_CONFIG_CRC_M 0x00000FFF +#define FLASH_FMC_REV_ID_CONFIG_CRC_S 0 //***************************************************************************** // @@ -2952,16 +2952,16 @@ // Field: [31:8] FSM_ERR_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_W 24 -#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_M 0xFFFFFF00 -#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_S 8 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_W 24 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_M 0xFFFFFF00 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_S 8 // Field: [3:0] FSM_ERR_BANK // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_W 4 -#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_M 0x0000000F -#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_S 0 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_W 4 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_M 0x0000000F +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_S 0 //***************************************************************************** // @@ -2971,9 +2971,9 @@ // Field: [11:0] FSM_PGM_MAXPUL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_W 12 -#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_M 0x00000FFF -#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_S 0 +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_W 12 +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_M 0x00000FFF +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_S 0 //***************************************************************************** // @@ -2983,16 +2983,16 @@ // Field: [19:16] SUSPEND_NOW // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_EXECUTE_SUSPEND_NOW_W 4 -#define FLASH_FSM_EXECUTE_SUSPEND_NOW_M 0x000F0000 -#define FLASH_FSM_EXECUTE_SUSPEND_NOW_S 16 +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_W 4 +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_M 0x000F0000 +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_S 16 // Field: [4:0] FSMEXECUTE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_EXECUTE_FSMEXECUTE_W 5 -#define FLASH_FSM_EXECUTE_FSMEXECUTE_M 0x0000001F -#define FLASH_FSM_EXECUTE_FSMEXECUTE_S 0 +#define FLASH_FSM_EXECUTE_FSMEXECUTE_W 5 +#define FLASH_FSM_EXECUTE_FSMEXECUTE_M 0x0000001F +#define FLASH_FSM_EXECUTE_FSMEXECUTE_S 0 //***************************************************************************** // @@ -3002,9 +3002,9 @@ // Field: [31:0] FSM_SECTOR1 // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR1_FSM_SECTOR1_W 32 -#define FLASH_FSM_SECTOR1_FSM_SECTOR1_M 0xFFFFFFFF -#define FLASH_FSM_SECTOR1_FSM_SECTOR1_S 0 +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_W 32 +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_M 0xFFFFFFFF +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_S 0 //***************************************************************************** // @@ -3014,9 +3014,9 @@ // Field: [31:0] FSM_SECTOR2 // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR2_FSM_SECTOR2_W 32 -#define FLASH_FSM_SECTOR2_FSM_SECTOR2_M 0xFFFFFFFF -#define FLASH_FSM_SECTOR2_FSM_SECTOR2_S 0 +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_W 32 +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_M 0xFFFFFFFF +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_S 0 //***************************************************************************** // @@ -3026,9 +3026,9 @@ // Field: [31:0] FSM_BSLE0 // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_BSLE0_FSM_BSLE0_W 32 -#define FLASH_FSM_BSLE0_FSM_BSLE0_M 0xFFFFFFFF -#define FLASH_FSM_BSLE0_FSM_BSLE0_S 0 +#define FLASH_FSM_BSLE0_FSM_BSLE0_W 32 +#define FLASH_FSM_BSLE0_FSM_BSLE0_M 0xFFFFFFFF +#define FLASH_FSM_BSLE0_FSM_BSLE0_S 0 //***************************************************************************** // @@ -3038,9 +3038,9 @@ // Field: [31:0] FSM_BSL1 // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_BSLE1_FSM_BSL1_W 32 -#define FLASH_FSM_BSLE1_FSM_BSL1_M 0xFFFFFFFF -#define FLASH_FSM_BSLE1_FSM_BSL1_S 0 +#define FLASH_FSM_BSLE1_FSM_BSL1_W 32 +#define FLASH_FSM_BSLE1_FSM_BSL1_M 0xFFFFFFFF +#define FLASH_FSM_BSLE1_FSM_BSL1_S 0 //***************************************************************************** // @@ -3050,9 +3050,9 @@ // Field: [31:0] FSM_BSLP0 // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_BSLP0_FSM_BSLP0_W 32 -#define FLASH_FSM_BSLP0_FSM_BSLP0_M 0xFFFFFFFF -#define FLASH_FSM_BSLP0_FSM_BSLP0_S 0 +#define FLASH_FSM_BSLP0_FSM_BSLP0_W 32 +#define FLASH_FSM_BSLP0_FSM_BSLP0_M 0xFFFFFFFF +#define FLASH_FSM_BSLP0_FSM_BSLP0_S 0 //***************************************************************************** // @@ -3062,9 +3062,9 @@ // Field: [31:0] FSM_BSL1 // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_BSLP1_FSM_BSL1_W 32 -#define FLASH_FSM_BSLP1_FSM_BSL1_M 0xFFFFFFFF -#define FLASH_FSM_BSLP1_FSM_BSL1_S 0 +#define FLASH_FSM_BSLP1_FSM_BSL1_W 32 +#define FLASH_FSM_BSLP1_FSM_BSL1_M 0xFFFFFFFF +#define FLASH_FSM_BSLP1_FSM_BSL1_S 0 //***************************************************************************** // @@ -3081,10 +3081,10 @@ // word is divided into two 64-bit words for programming. [default] // // This register is write protected with the FSM_WR_ENA register. -#define FLASH_FSM_PGM128_EN_PGM128 0x00000001 -#define FLASH_FSM_PGM128_EN_PGM128_BITN 0 -#define FLASH_FSM_PGM128_EN_PGM128_M 0x00000001 -#define FLASH_FSM_PGM128_EN_PGM128_S 0 +#define FLASH_FSM_PGM128_EN_PGM128 0x00000001 +#define FLASH_FSM_PGM128_EN_PGM128_BITN 0 +#define FLASH_FSM_PGM128_EN_PGM128_M 0x00000001 +#define FLASH_FSM_PGM128_EN_PGM128_S 0 //***************************************************************************** // @@ -3094,30 +3094,30 @@ // Field: [31:20] EE_BANK_WIDTH // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BANK_EE_BANK_WIDTH_W 12 -#define FLASH_FCFG_BANK_EE_BANK_WIDTH_M 0xFFF00000 -#define FLASH_FCFG_BANK_EE_BANK_WIDTH_S 20 +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_W 12 +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_M 0xFFF00000 +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_S 20 // Field: [19:16] EE_NUM_BANK // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BANK_EE_NUM_BANK_W 4 -#define FLASH_FCFG_BANK_EE_NUM_BANK_M 0x000F0000 -#define FLASH_FCFG_BANK_EE_NUM_BANK_S 16 +#define FLASH_FCFG_BANK_EE_NUM_BANK_W 4 +#define FLASH_FCFG_BANK_EE_NUM_BANK_M 0x000F0000 +#define FLASH_FCFG_BANK_EE_NUM_BANK_S 16 // Field: [15:4] MAIN_BANK_WIDTH // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_W 12 -#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M 0x0000FFF0 -#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S 4 +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_W 12 +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M 0x0000FFF0 +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S 4 // Field: [3:0] MAIN_NUM_BANK // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BANK_MAIN_NUM_BANK_W 4 -#define FLASH_FCFG_BANK_MAIN_NUM_BANK_M 0x0000000F -#define FLASH_FCFG_BANK_MAIN_NUM_BANK_S 0 +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_W 4 +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_M 0x0000000F +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_S 0 //***************************************************************************** // @@ -3127,84 +3127,84 @@ // Field: [31:24] FAMILY_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_W 8 -#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_M 0xFF000000 -#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_S 24 +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_W 8 +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_M 0xFF000000 +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_S 24 // Field: [20] MEM_MAP // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_MEM_MAP 0x00100000 -#define FLASH_FCFG_WRAPPER_MEM_MAP_BITN 20 -#define FLASH_FCFG_WRAPPER_MEM_MAP_M 0x00100000 -#define FLASH_FCFG_WRAPPER_MEM_MAP_S 20 +#define FLASH_FCFG_WRAPPER_MEM_MAP 0x00100000 +#define FLASH_FCFG_WRAPPER_MEM_MAP_BITN 20 +#define FLASH_FCFG_WRAPPER_MEM_MAP_M 0x00100000 +#define FLASH_FCFG_WRAPPER_MEM_MAP_S 20 // Field: [19:16] CPU2 // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_CPU2_W 4 -#define FLASH_FCFG_WRAPPER_CPU2_M 0x000F0000 -#define FLASH_FCFG_WRAPPER_CPU2_S 16 +#define FLASH_FCFG_WRAPPER_CPU2_W 4 +#define FLASH_FCFG_WRAPPER_CPU2_M 0x000F0000 +#define FLASH_FCFG_WRAPPER_CPU2_S 16 // Field: [15:12] EE_IN_MAIN // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_W 4 -#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_M 0x0000F000 -#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_S 12 +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_W 4 +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_M 0x0000F000 +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_S 12 // Field: [11] ROM // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_ROM 0x00000800 -#define FLASH_FCFG_WRAPPER_ROM_BITN 11 -#define FLASH_FCFG_WRAPPER_ROM_M 0x00000800 -#define FLASH_FCFG_WRAPPER_ROM_S 11 +#define FLASH_FCFG_WRAPPER_ROM 0x00000800 +#define FLASH_FCFG_WRAPPER_ROM_BITN 11 +#define FLASH_FCFG_WRAPPER_ROM_M 0x00000800 +#define FLASH_FCFG_WRAPPER_ROM_S 11 // Field: [10] IFLUSH // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_IFLUSH 0x00000400 -#define FLASH_FCFG_WRAPPER_IFLUSH_BITN 10 -#define FLASH_FCFG_WRAPPER_IFLUSH_M 0x00000400 -#define FLASH_FCFG_WRAPPER_IFLUSH_S 10 +#define FLASH_FCFG_WRAPPER_IFLUSH 0x00000400 +#define FLASH_FCFG_WRAPPER_IFLUSH_BITN 10 +#define FLASH_FCFG_WRAPPER_IFLUSH_M 0x00000400 +#define FLASH_FCFG_WRAPPER_IFLUSH_S 10 // Field: [9] SIL3 // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_SIL3 0x00000200 -#define FLASH_FCFG_WRAPPER_SIL3_BITN 9 -#define FLASH_FCFG_WRAPPER_SIL3_M 0x00000200 -#define FLASH_FCFG_WRAPPER_SIL3_S 9 +#define FLASH_FCFG_WRAPPER_SIL3 0x00000200 +#define FLASH_FCFG_WRAPPER_SIL3_BITN 9 +#define FLASH_FCFG_WRAPPER_SIL3_M 0x00000200 +#define FLASH_FCFG_WRAPPER_SIL3_S 9 // Field: [8] ECCA // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_ECCA 0x00000100 -#define FLASH_FCFG_WRAPPER_ECCA_BITN 8 -#define FLASH_FCFG_WRAPPER_ECCA_M 0x00000100 -#define FLASH_FCFG_WRAPPER_ECCA_S 8 +#define FLASH_FCFG_WRAPPER_ECCA 0x00000100 +#define FLASH_FCFG_WRAPPER_ECCA_BITN 8 +#define FLASH_FCFG_WRAPPER_ECCA_M 0x00000100 +#define FLASH_FCFG_WRAPPER_ECCA_S 8 // Field: [7:6] AUTO_SUSP // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_AUTO_SUSP_W 2 -#define FLASH_FCFG_WRAPPER_AUTO_SUSP_M 0x000000C0 -#define FLASH_FCFG_WRAPPER_AUTO_SUSP_S 6 +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_W 2 +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_M 0x000000C0 +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_S 6 // Field: [5:4] UERR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_UERR_W 2 -#define FLASH_FCFG_WRAPPER_UERR_M 0x00000030 -#define FLASH_FCFG_WRAPPER_UERR_S 4 +#define FLASH_FCFG_WRAPPER_UERR_W 2 +#define FLASH_FCFG_WRAPPER_UERR_M 0x00000030 +#define FLASH_FCFG_WRAPPER_UERR_S 4 // Field: [3:0] CPU_TYPE1 // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_CPU_TYPE1_W 4 -#define FLASH_FCFG_WRAPPER_CPU_TYPE1_M 0x0000000F -#define FLASH_FCFG_WRAPPER_CPU_TYPE1_S 0 +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_W 4 +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_M 0x0000000F +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_S 0 //***************************************************************************** // @@ -3214,58 +3214,58 @@ // Field: [31:28] B7_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B7_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B7_TYPE_M 0xF0000000 -#define FLASH_FCFG_BNK_TYPE_B7_TYPE_S 28 +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_M 0xF0000000 +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_S 28 // Field: [27:24] B6_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B6_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B6_TYPE_M 0x0F000000 -#define FLASH_FCFG_BNK_TYPE_B6_TYPE_S 24 +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_M 0x0F000000 +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_S 24 // Field: [23:20] B5_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B5_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B5_TYPE_M 0x00F00000 -#define FLASH_FCFG_BNK_TYPE_B5_TYPE_S 20 +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_M 0x00F00000 +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_S 20 // Field: [19:16] B4_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B4_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B4_TYPE_M 0x000F0000 -#define FLASH_FCFG_BNK_TYPE_B4_TYPE_S 16 +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_M 0x000F0000 +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_S 16 // Field: [15:12] B3_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B3_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B3_TYPE_M 0x0000F000 -#define FLASH_FCFG_BNK_TYPE_B3_TYPE_S 12 +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_M 0x0000F000 +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_S 12 // Field: [11:8] B2_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B2_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B2_TYPE_M 0x00000F00 -#define FLASH_FCFG_BNK_TYPE_B2_TYPE_S 8 +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_M 0x00000F00 +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_S 8 // Field: [7:4] B1_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B1_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B1_TYPE_M 0x000000F0 -#define FLASH_FCFG_BNK_TYPE_B1_TYPE_S 4 +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_M 0x000000F0 +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_S 4 // Field: [3:0] B0_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B0_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B0_TYPE_M 0x0000000F -#define FLASH_FCFG_BNK_TYPE_B0_TYPE_S 0 +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_M 0x0000000F +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_S 0 //***************************************************************************** // @@ -3275,23 +3275,23 @@ // Field: [31:28] B0_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_W 4 -#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_S 28 +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_W 4 +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_S 28 // Field: [27:24] B0_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_W 4 -#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_S 24 +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_W 4 +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_S 24 // Field: [23:0] B0_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_START_B0_START_ADDR_W 24 -#define FLASH_FCFG_B0_START_B0_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B0_START_B0_START_ADDR_S 0 +#define FLASH_FCFG_B0_START_B0_START_ADDR_W 24 +#define FLASH_FCFG_B0_START_B0_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B0_START_B0_START_ADDR_S 0 //***************************************************************************** // @@ -3301,23 +3301,23 @@ // Field: [31:28] B1_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_W 4 -#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_S 28 +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_W 4 +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_S 28 // Field: [27:24] B1_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_W 4 -#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_S 24 +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_W 4 +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_S 24 // Field: [23:0] B1_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B1_START_B1_START_ADDR_W 24 -#define FLASH_FCFG_B1_START_B1_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B1_START_B1_START_ADDR_S 0 +#define FLASH_FCFG_B1_START_B1_START_ADDR_W 24 +#define FLASH_FCFG_B1_START_B1_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B1_START_B1_START_ADDR_S 0 //***************************************************************************** // @@ -3327,23 +3327,23 @@ // Field: [31:28] B2_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_W 4 -#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_S 28 +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_W 4 +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_S 28 // Field: [27:24] B2_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_W 4 -#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_S 24 +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_W 4 +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_S 24 // Field: [23:0] B2_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B2_START_B2_START_ADDR_W 24 -#define FLASH_FCFG_B2_START_B2_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B2_START_B2_START_ADDR_S 0 +#define FLASH_FCFG_B2_START_B2_START_ADDR_W 24 +#define FLASH_FCFG_B2_START_B2_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B2_START_B2_START_ADDR_S 0 //***************************************************************************** // @@ -3353,23 +3353,23 @@ // Field: [31:28] B3_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_W 4 -#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_S 28 +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_W 4 +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_S 28 // Field: [27:24] B3_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_W 4 -#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_S 24 +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_W 4 +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_S 24 // Field: [23:0] B3_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B3_START_B3_START_ADDR_W 24 -#define FLASH_FCFG_B3_START_B3_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B3_START_B3_START_ADDR_S 0 +#define FLASH_FCFG_B3_START_B3_START_ADDR_W 24 +#define FLASH_FCFG_B3_START_B3_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B3_START_B3_START_ADDR_S 0 //***************************************************************************** // @@ -3379,23 +3379,23 @@ // Field: [31:28] B4_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_W 4 -#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_S 28 +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_W 4 +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_S 28 // Field: [27:24] B4_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_W 4 -#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_S 24 +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_W 4 +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_S 24 // Field: [23:0] B4_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B4_START_B4_START_ADDR_W 24 -#define FLASH_FCFG_B4_START_B4_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B4_START_B4_START_ADDR_S 0 +#define FLASH_FCFG_B4_START_B4_START_ADDR_W 24 +#define FLASH_FCFG_B4_START_B4_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B4_START_B4_START_ADDR_S 0 //***************************************************************************** // @@ -3405,23 +3405,23 @@ // Field: [31:28] B5_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_W 4 -#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_S 28 +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_W 4 +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_S 28 // Field: [27:24] B5_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_W 4 -#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_S 24 +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_W 4 +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_S 24 // Field: [23:0] B5_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B5_START_B5_START_ADDR_W 24 -#define FLASH_FCFG_B5_START_B5_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B5_START_B5_START_ADDR_S 0 +#define FLASH_FCFG_B5_START_B5_START_ADDR_W 24 +#define FLASH_FCFG_B5_START_B5_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B5_START_B5_START_ADDR_S 0 //***************************************************************************** // @@ -3431,23 +3431,23 @@ // Field: [31:28] B6_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_W 4 -#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_S 28 +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_W 4 +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_S 28 // Field: [27:24] B6_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_W 4 -#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_S 24 +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_W 4 +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_S 24 // Field: [23:0] B6_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B6_START_B6_START_ADDR_W 24 -#define FLASH_FCFG_B6_START_B6_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B6_START_B6_START_ADDR_S 0 +#define FLASH_FCFG_B6_START_B6_START_ADDR_W 24 +#define FLASH_FCFG_B6_START_B6_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B6_START_B6_START_ADDR_S 0 //***************************************************************************** // @@ -3457,23 +3457,23 @@ // Field: [31:28] B7_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_W 4 -#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_S 28 +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_W 4 +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_S 28 // Field: [27:24] B7_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_W 4 -#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_S 24 +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_W 4 +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_S 24 // Field: [23:0] B7_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B7_START_B7_START_ADDR_W 24 -#define FLASH_FCFG_B7_START_B7_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B7_START_B7_START_ADDR_S 0 +#define FLASH_FCFG_B7_START_B7_START_ADDR_W 24 +#define FLASH_FCFG_B7_START_B7_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B7_START_B7_START_ADDR_S 0 //***************************************************************************** // @@ -3483,16 +3483,15 @@ // Field: [27:16] B0_NUM_SECTORS // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_W 12 -#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_M 0x0FFF0000 -#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_S 16 +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_W 12 +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_M 0x0FFF0000 +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_S 16 // Field: [3:0] B0_SECT_SIZE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_W 4 -#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M 0x0000000F -#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S 0 - +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_W 4 +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M 0x0000000F +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S 0 #endif // __FLASH__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_gpio.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_gpio.h index 1bf518b..19ddd42 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_gpio.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_gpio.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_gpio_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_gpio_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_GPIO_H__ #define __HW_GPIO_H__ @@ -44,49 +44,49 @@ // //***************************************************************************** // Data Out 0 to 3 -#define GPIO_O_DOUT3_0 0x00000000 +#define GPIO_O_DOUT3_0 0x00000000 // Data Out 4 to 7 -#define GPIO_O_DOUT7_4 0x00000004 +#define GPIO_O_DOUT7_4 0x00000004 // Data Out 8 to 11 -#define GPIO_O_DOUT11_8 0x00000008 +#define GPIO_O_DOUT11_8 0x00000008 // Data Out 12 to 15 -#define GPIO_O_DOUT15_12 0x0000000C +#define GPIO_O_DOUT15_12 0x0000000C // Data Out 16 to 19 -#define GPIO_O_DOUT19_16 0x00000010 +#define GPIO_O_DOUT19_16 0x00000010 // Data Out 20 to 23 -#define GPIO_O_DOUT23_20 0x00000014 +#define GPIO_O_DOUT23_20 0x00000014 // Data Out 24 to 27 -#define GPIO_O_DOUT27_24 0x00000018 +#define GPIO_O_DOUT27_24 0x00000018 // Data Out 28 to 31 -#define GPIO_O_DOUT31_28 0x0000001C +#define GPIO_O_DOUT31_28 0x0000001C // Data Output for DIO 0 to 31 -#define GPIO_O_DOUT31_0 0x00000080 +#define GPIO_O_DOUT31_0 0x00000080 // Data Out Set -#define GPIO_O_DOUTSET31_0 0x00000090 +#define GPIO_O_DOUTSET31_0 0x00000090 // Data Out Clear -#define GPIO_O_DOUTCLR31_0 0x000000A0 +#define GPIO_O_DOUTCLR31_0 0x000000A0 // Data Out Toggle -#define GPIO_O_DOUTTGL31_0 0x000000B0 +#define GPIO_O_DOUTTGL31_0 0x000000B0 // Data Input from DIO 0 to 31 -#define GPIO_O_DIN31_0 0x000000C0 +#define GPIO_O_DIN31_0 0x000000C0 // Data Output Enable for DIO 0 to 31 -#define GPIO_O_DOE31_0 0x000000D0 +#define GPIO_O_DOE31_0 0x000000D0 // Event Register for DIO 0 to 31 -#define GPIO_O_EVFLAGS31_0 0x000000E0 +#define GPIO_O_EVFLAGS31_0 0x000000E0 //***************************************************************************** // @@ -97,37 +97,37 @@ // // Sets the state of the pin that is configured as DIO#3, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT3_0_DIO3 0x01000000 -#define GPIO_DOUT3_0_DIO3_BITN 24 -#define GPIO_DOUT3_0_DIO3_M 0x01000000 -#define GPIO_DOUT3_0_DIO3_S 24 +#define GPIO_DOUT3_0_DIO3 0x01000000 +#define GPIO_DOUT3_0_DIO3_BITN 24 +#define GPIO_DOUT3_0_DIO3_M 0x01000000 +#define GPIO_DOUT3_0_DIO3_S 24 // Field: [16] DIO2 // // Sets the state of the pin that is configured as DIO#2, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT3_0_DIO2 0x00010000 -#define GPIO_DOUT3_0_DIO2_BITN 16 -#define GPIO_DOUT3_0_DIO2_M 0x00010000 -#define GPIO_DOUT3_0_DIO2_S 16 +#define GPIO_DOUT3_0_DIO2 0x00010000 +#define GPIO_DOUT3_0_DIO2_BITN 16 +#define GPIO_DOUT3_0_DIO2_M 0x00010000 +#define GPIO_DOUT3_0_DIO2_S 16 // Field: [8] DIO1 // // Sets the state of the pin that is configured as DIO#1, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT3_0_DIO1 0x00000100 -#define GPIO_DOUT3_0_DIO1_BITN 8 -#define GPIO_DOUT3_0_DIO1_M 0x00000100 -#define GPIO_DOUT3_0_DIO1_S 8 +#define GPIO_DOUT3_0_DIO1 0x00000100 +#define GPIO_DOUT3_0_DIO1_BITN 8 +#define GPIO_DOUT3_0_DIO1_M 0x00000100 +#define GPIO_DOUT3_0_DIO1_S 8 // Field: [0] DIO0 // // Sets the state of the pin that is configured as DIO#0, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT3_0_DIO0 0x00000001 -#define GPIO_DOUT3_0_DIO0_BITN 0 -#define GPIO_DOUT3_0_DIO0_M 0x00000001 -#define GPIO_DOUT3_0_DIO0_S 0 +#define GPIO_DOUT3_0_DIO0 0x00000001 +#define GPIO_DOUT3_0_DIO0_BITN 0 +#define GPIO_DOUT3_0_DIO0_M 0x00000001 +#define GPIO_DOUT3_0_DIO0_S 0 //***************************************************************************** // @@ -138,37 +138,37 @@ // // Sets the state of the pin that is configured as DIO#7, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT7_4_DIO7 0x01000000 -#define GPIO_DOUT7_4_DIO7_BITN 24 -#define GPIO_DOUT7_4_DIO7_M 0x01000000 -#define GPIO_DOUT7_4_DIO7_S 24 +#define GPIO_DOUT7_4_DIO7 0x01000000 +#define GPIO_DOUT7_4_DIO7_BITN 24 +#define GPIO_DOUT7_4_DIO7_M 0x01000000 +#define GPIO_DOUT7_4_DIO7_S 24 // Field: [16] DIO6 // // Sets the state of the pin that is configured as DIO#6, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT7_4_DIO6 0x00010000 -#define GPIO_DOUT7_4_DIO6_BITN 16 -#define GPIO_DOUT7_4_DIO6_M 0x00010000 -#define GPIO_DOUT7_4_DIO6_S 16 +#define GPIO_DOUT7_4_DIO6 0x00010000 +#define GPIO_DOUT7_4_DIO6_BITN 16 +#define GPIO_DOUT7_4_DIO6_M 0x00010000 +#define GPIO_DOUT7_4_DIO6_S 16 // Field: [8] DIO5 // // Sets the state of the pin that is configured as DIO#5, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT7_4_DIO5 0x00000100 -#define GPIO_DOUT7_4_DIO5_BITN 8 -#define GPIO_DOUT7_4_DIO5_M 0x00000100 -#define GPIO_DOUT7_4_DIO5_S 8 +#define GPIO_DOUT7_4_DIO5 0x00000100 +#define GPIO_DOUT7_4_DIO5_BITN 8 +#define GPIO_DOUT7_4_DIO5_M 0x00000100 +#define GPIO_DOUT7_4_DIO5_S 8 // Field: [0] DIO4 // // Sets the state of the pin that is configured as DIO#4, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT7_4_DIO4 0x00000001 -#define GPIO_DOUT7_4_DIO4_BITN 0 -#define GPIO_DOUT7_4_DIO4_M 0x00000001 -#define GPIO_DOUT7_4_DIO4_S 0 +#define GPIO_DOUT7_4_DIO4 0x00000001 +#define GPIO_DOUT7_4_DIO4_BITN 0 +#define GPIO_DOUT7_4_DIO4_M 0x00000001 +#define GPIO_DOUT7_4_DIO4_S 0 //***************************************************************************** // @@ -179,37 +179,37 @@ // // Sets the state of the pin that is configured as DIO#11, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT11_8_DIO11 0x01000000 -#define GPIO_DOUT11_8_DIO11_BITN 24 -#define GPIO_DOUT11_8_DIO11_M 0x01000000 -#define GPIO_DOUT11_8_DIO11_S 24 +#define GPIO_DOUT11_8_DIO11 0x01000000 +#define GPIO_DOUT11_8_DIO11_BITN 24 +#define GPIO_DOUT11_8_DIO11_M 0x01000000 +#define GPIO_DOUT11_8_DIO11_S 24 // Field: [16] DIO10 // // Sets the state of the pin that is configured as DIO#10, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT11_8_DIO10 0x00010000 -#define GPIO_DOUT11_8_DIO10_BITN 16 -#define GPIO_DOUT11_8_DIO10_M 0x00010000 -#define GPIO_DOUT11_8_DIO10_S 16 +#define GPIO_DOUT11_8_DIO10 0x00010000 +#define GPIO_DOUT11_8_DIO10_BITN 16 +#define GPIO_DOUT11_8_DIO10_M 0x00010000 +#define GPIO_DOUT11_8_DIO10_S 16 // Field: [8] DIO9 // // Sets the state of the pin that is configured as DIO#9, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT11_8_DIO9 0x00000100 -#define GPIO_DOUT11_8_DIO9_BITN 8 -#define GPIO_DOUT11_8_DIO9_M 0x00000100 -#define GPIO_DOUT11_8_DIO9_S 8 +#define GPIO_DOUT11_8_DIO9 0x00000100 +#define GPIO_DOUT11_8_DIO9_BITN 8 +#define GPIO_DOUT11_8_DIO9_M 0x00000100 +#define GPIO_DOUT11_8_DIO9_S 8 // Field: [0] DIO8 // // Sets the state of the pin that is configured as DIO#8, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT11_8_DIO8 0x00000001 -#define GPIO_DOUT11_8_DIO8_BITN 0 -#define GPIO_DOUT11_8_DIO8_M 0x00000001 -#define GPIO_DOUT11_8_DIO8_S 0 +#define GPIO_DOUT11_8_DIO8 0x00000001 +#define GPIO_DOUT11_8_DIO8_BITN 0 +#define GPIO_DOUT11_8_DIO8_M 0x00000001 +#define GPIO_DOUT11_8_DIO8_S 0 //***************************************************************************** // @@ -220,37 +220,37 @@ // // Sets the state of the pin that is configured as DIO#15, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT15_12_DIO15 0x01000000 -#define GPIO_DOUT15_12_DIO15_BITN 24 -#define GPIO_DOUT15_12_DIO15_M 0x01000000 -#define GPIO_DOUT15_12_DIO15_S 24 +#define GPIO_DOUT15_12_DIO15 0x01000000 +#define GPIO_DOUT15_12_DIO15_BITN 24 +#define GPIO_DOUT15_12_DIO15_M 0x01000000 +#define GPIO_DOUT15_12_DIO15_S 24 // Field: [16] DIO14 // // Sets the state of the pin that is configured as DIO#14, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT15_12_DIO14 0x00010000 -#define GPIO_DOUT15_12_DIO14_BITN 16 -#define GPIO_DOUT15_12_DIO14_M 0x00010000 -#define GPIO_DOUT15_12_DIO14_S 16 +#define GPIO_DOUT15_12_DIO14 0x00010000 +#define GPIO_DOUT15_12_DIO14_BITN 16 +#define GPIO_DOUT15_12_DIO14_M 0x00010000 +#define GPIO_DOUT15_12_DIO14_S 16 // Field: [8] DIO13 // // Sets the state of the pin that is configured as DIO#13, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT15_12_DIO13 0x00000100 -#define GPIO_DOUT15_12_DIO13_BITN 8 -#define GPIO_DOUT15_12_DIO13_M 0x00000100 -#define GPIO_DOUT15_12_DIO13_S 8 +#define GPIO_DOUT15_12_DIO13 0x00000100 +#define GPIO_DOUT15_12_DIO13_BITN 8 +#define GPIO_DOUT15_12_DIO13_M 0x00000100 +#define GPIO_DOUT15_12_DIO13_S 8 // Field: [0] DIO12 // // Sets the state of the pin that is configured as DIO#12, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT15_12_DIO12 0x00000001 -#define GPIO_DOUT15_12_DIO12_BITN 0 -#define GPIO_DOUT15_12_DIO12_M 0x00000001 -#define GPIO_DOUT15_12_DIO12_S 0 +#define GPIO_DOUT15_12_DIO12 0x00000001 +#define GPIO_DOUT15_12_DIO12_BITN 0 +#define GPIO_DOUT15_12_DIO12_M 0x00000001 +#define GPIO_DOUT15_12_DIO12_S 0 //***************************************************************************** // @@ -261,37 +261,37 @@ // // Sets the state of the pin that is configured as DIO#19, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT19_16_DIO19 0x01000000 -#define GPIO_DOUT19_16_DIO19_BITN 24 -#define GPIO_DOUT19_16_DIO19_M 0x01000000 -#define GPIO_DOUT19_16_DIO19_S 24 +#define GPIO_DOUT19_16_DIO19 0x01000000 +#define GPIO_DOUT19_16_DIO19_BITN 24 +#define GPIO_DOUT19_16_DIO19_M 0x01000000 +#define GPIO_DOUT19_16_DIO19_S 24 // Field: [16] DIO18 // // Sets the state of the pin that is configured as DIO#18, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT19_16_DIO18 0x00010000 -#define GPIO_DOUT19_16_DIO18_BITN 16 -#define GPIO_DOUT19_16_DIO18_M 0x00010000 -#define GPIO_DOUT19_16_DIO18_S 16 +#define GPIO_DOUT19_16_DIO18 0x00010000 +#define GPIO_DOUT19_16_DIO18_BITN 16 +#define GPIO_DOUT19_16_DIO18_M 0x00010000 +#define GPIO_DOUT19_16_DIO18_S 16 // Field: [8] DIO17 // // Sets the state of the pin that is configured as DIO#17, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT19_16_DIO17 0x00000100 -#define GPIO_DOUT19_16_DIO17_BITN 8 -#define GPIO_DOUT19_16_DIO17_M 0x00000100 -#define GPIO_DOUT19_16_DIO17_S 8 +#define GPIO_DOUT19_16_DIO17 0x00000100 +#define GPIO_DOUT19_16_DIO17_BITN 8 +#define GPIO_DOUT19_16_DIO17_M 0x00000100 +#define GPIO_DOUT19_16_DIO17_S 8 // Field: [0] DIO16 // // Sets the state of the pin that is configured as DIO#16, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT19_16_DIO16 0x00000001 -#define GPIO_DOUT19_16_DIO16_BITN 0 -#define GPIO_DOUT19_16_DIO16_M 0x00000001 -#define GPIO_DOUT19_16_DIO16_S 0 +#define GPIO_DOUT19_16_DIO16 0x00000001 +#define GPIO_DOUT19_16_DIO16_BITN 0 +#define GPIO_DOUT19_16_DIO16_M 0x00000001 +#define GPIO_DOUT19_16_DIO16_S 0 //***************************************************************************** // @@ -302,37 +302,37 @@ // // Sets the state of the pin that is configured as DIO#23, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT23_20_DIO23 0x01000000 -#define GPIO_DOUT23_20_DIO23_BITN 24 -#define GPIO_DOUT23_20_DIO23_M 0x01000000 -#define GPIO_DOUT23_20_DIO23_S 24 +#define GPIO_DOUT23_20_DIO23 0x01000000 +#define GPIO_DOUT23_20_DIO23_BITN 24 +#define GPIO_DOUT23_20_DIO23_M 0x01000000 +#define GPIO_DOUT23_20_DIO23_S 24 // Field: [16] DIO22 // // Sets the state of the pin that is configured as DIO#22, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT23_20_DIO22 0x00010000 -#define GPIO_DOUT23_20_DIO22_BITN 16 -#define GPIO_DOUT23_20_DIO22_M 0x00010000 -#define GPIO_DOUT23_20_DIO22_S 16 +#define GPIO_DOUT23_20_DIO22 0x00010000 +#define GPIO_DOUT23_20_DIO22_BITN 16 +#define GPIO_DOUT23_20_DIO22_M 0x00010000 +#define GPIO_DOUT23_20_DIO22_S 16 // Field: [8] DIO21 // // Sets the state of the pin that is configured as DIO#21, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT23_20_DIO21 0x00000100 -#define GPIO_DOUT23_20_DIO21_BITN 8 -#define GPIO_DOUT23_20_DIO21_M 0x00000100 -#define GPIO_DOUT23_20_DIO21_S 8 +#define GPIO_DOUT23_20_DIO21 0x00000100 +#define GPIO_DOUT23_20_DIO21_BITN 8 +#define GPIO_DOUT23_20_DIO21_M 0x00000100 +#define GPIO_DOUT23_20_DIO21_S 8 // Field: [0] DIO20 // // Sets the state of the pin that is configured as DIO#20, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT23_20_DIO20 0x00000001 -#define GPIO_DOUT23_20_DIO20_BITN 0 -#define GPIO_DOUT23_20_DIO20_M 0x00000001 -#define GPIO_DOUT23_20_DIO20_S 0 +#define GPIO_DOUT23_20_DIO20 0x00000001 +#define GPIO_DOUT23_20_DIO20_BITN 0 +#define GPIO_DOUT23_20_DIO20_M 0x00000001 +#define GPIO_DOUT23_20_DIO20_S 0 //***************************************************************************** // @@ -343,37 +343,37 @@ // // Sets the state of the pin that is configured as DIO#27, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT27_24_DIO27 0x01000000 -#define GPIO_DOUT27_24_DIO27_BITN 24 -#define GPIO_DOUT27_24_DIO27_M 0x01000000 -#define GPIO_DOUT27_24_DIO27_S 24 +#define GPIO_DOUT27_24_DIO27 0x01000000 +#define GPIO_DOUT27_24_DIO27_BITN 24 +#define GPIO_DOUT27_24_DIO27_M 0x01000000 +#define GPIO_DOUT27_24_DIO27_S 24 // Field: [16] DIO26 // // Sets the state of the pin that is configured as DIO#26, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT27_24_DIO26 0x00010000 -#define GPIO_DOUT27_24_DIO26_BITN 16 -#define GPIO_DOUT27_24_DIO26_M 0x00010000 -#define GPIO_DOUT27_24_DIO26_S 16 +#define GPIO_DOUT27_24_DIO26 0x00010000 +#define GPIO_DOUT27_24_DIO26_BITN 16 +#define GPIO_DOUT27_24_DIO26_M 0x00010000 +#define GPIO_DOUT27_24_DIO26_S 16 // Field: [8] DIO25 // // Sets the state of the pin that is configured as DIO#25, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT27_24_DIO25 0x00000100 -#define GPIO_DOUT27_24_DIO25_BITN 8 -#define GPIO_DOUT27_24_DIO25_M 0x00000100 -#define GPIO_DOUT27_24_DIO25_S 8 +#define GPIO_DOUT27_24_DIO25 0x00000100 +#define GPIO_DOUT27_24_DIO25_BITN 8 +#define GPIO_DOUT27_24_DIO25_M 0x00000100 +#define GPIO_DOUT27_24_DIO25_S 8 // Field: [0] DIO24 // // Sets the state of the pin that is configured as DIO#24, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT27_24_DIO24 0x00000001 -#define GPIO_DOUT27_24_DIO24_BITN 0 -#define GPIO_DOUT27_24_DIO24_M 0x00000001 -#define GPIO_DOUT27_24_DIO24_S 0 +#define GPIO_DOUT27_24_DIO24 0x00000001 +#define GPIO_DOUT27_24_DIO24_BITN 0 +#define GPIO_DOUT27_24_DIO24_M 0x00000001 +#define GPIO_DOUT27_24_DIO24_S 0 //***************************************************************************** // @@ -384,37 +384,37 @@ // // Sets the state of the pin that is configured as DIO#31, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT31_28_DIO31 0x01000000 -#define GPIO_DOUT31_28_DIO31_BITN 24 -#define GPIO_DOUT31_28_DIO31_M 0x01000000 -#define GPIO_DOUT31_28_DIO31_S 24 +#define GPIO_DOUT31_28_DIO31 0x01000000 +#define GPIO_DOUT31_28_DIO31_BITN 24 +#define GPIO_DOUT31_28_DIO31_M 0x01000000 +#define GPIO_DOUT31_28_DIO31_S 24 // Field: [16] DIO30 // // Sets the state of the pin that is configured as DIO#30, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT31_28_DIO30 0x00010000 -#define GPIO_DOUT31_28_DIO30_BITN 16 -#define GPIO_DOUT31_28_DIO30_M 0x00010000 -#define GPIO_DOUT31_28_DIO30_S 16 +#define GPIO_DOUT31_28_DIO30 0x00010000 +#define GPIO_DOUT31_28_DIO30_BITN 16 +#define GPIO_DOUT31_28_DIO30_M 0x00010000 +#define GPIO_DOUT31_28_DIO30_S 16 // Field: [8] DIO29 // // Sets the state of the pin that is configured as DIO#29, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT31_28_DIO29 0x00000100 -#define GPIO_DOUT31_28_DIO29_BITN 8 -#define GPIO_DOUT31_28_DIO29_M 0x00000100 -#define GPIO_DOUT31_28_DIO29_S 8 +#define GPIO_DOUT31_28_DIO29 0x00000100 +#define GPIO_DOUT31_28_DIO29_BITN 8 +#define GPIO_DOUT31_28_DIO29_M 0x00000100 +#define GPIO_DOUT31_28_DIO29_S 8 // Field: [0] DIO28 // // Sets the state of the pin that is configured as DIO#28, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT31_28_DIO28 0x00000001 -#define GPIO_DOUT31_28_DIO28_BITN 0 -#define GPIO_DOUT31_28_DIO28_M 0x00000001 -#define GPIO_DOUT31_28_DIO28_S 0 +#define GPIO_DOUT31_28_DIO28 0x00000001 +#define GPIO_DOUT31_28_DIO28_BITN 0 +#define GPIO_DOUT31_28_DIO28_M 0x00000001 +#define GPIO_DOUT31_28_DIO28_S 0 //***************************************************************************** // @@ -424,258 +424,258 @@ // Field: [31] DIO31 // // Data output for DIO 31 -#define GPIO_DOUT31_0_DIO31 0x80000000 -#define GPIO_DOUT31_0_DIO31_BITN 31 -#define GPIO_DOUT31_0_DIO31_M 0x80000000 -#define GPIO_DOUT31_0_DIO31_S 31 +#define GPIO_DOUT31_0_DIO31 0x80000000 +#define GPIO_DOUT31_0_DIO31_BITN 31 +#define GPIO_DOUT31_0_DIO31_M 0x80000000 +#define GPIO_DOUT31_0_DIO31_S 31 // Field: [30] DIO30 // // Data output for DIO 30 -#define GPIO_DOUT31_0_DIO30 0x40000000 -#define GPIO_DOUT31_0_DIO30_BITN 30 -#define GPIO_DOUT31_0_DIO30_M 0x40000000 -#define GPIO_DOUT31_0_DIO30_S 30 +#define GPIO_DOUT31_0_DIO30 0x40000000 +#define GPIO_DOUT31_0_DIO30_BITN 30 +#define GPIO_DOUT31_0_DIO30_M 0x40000000 +#define GPIO_DOUT31_0_DIO30_S 30 // Field: [29] DIO29 // // Data output for DIO 29 -#define GPIO_DOUT31_0_DIO29 0x20000000 -#define GPIO_DOUT31_0_DIO29_BITN 29 -#define GPIO_DOUT31_0_DIO29_M 0x20000000 -#define GPIO_DOUT31_0_DIO29_S 29 +#define GPIO_DOUT31_0_DIO29 0x20000000 +#define GPIO_DOUT31_0_DIO29_BITN 29 +#define GPIO_DOUT31_0_DIO29_M 0x20000000 +#define GPIO_DOUT31_0_DIO29_S 29 // Field: [28] DIO28 // // Data output for DIO 28 -#define GPIO_DOUT31_0_DIO28 0x10000000 -#define GPIO_DOUT31_0_DIO28_BITN 28 -#define GPIO_DOUT31_0_DIO28_M 0x10000000 -#define GPIO_DOUT31_0_DIO28_S 28 +#define GPIO_DOUT31_0_DIO28 0x10000000 +#define GPIO_DOUT31_0_DIO28_BITN 28 +#define GPIO_DOUT31_0_DIO28_M 0x10000000 +#define GPIO_DOUT31_0_DIO28_S 28 // Field: [27] DIO27 // // Data output for DIO 27 -#define GPIO_DOUT31_0_DIO27 0x08000000 -#define GPIO_DOUT31_0_DIO27_BITN 27 -#define GPIO_DOUT31_0_DIO27_M 0x08000000 -#define GPIO_DOUT31_0_DIO27_S 27 +#define GPIO_DOUT31_0_DIO27 0x08000000 +#define GPIO_DOUT31_0_DIO27_BITN 27 +#define GPIO_DOUT31_0_DIO27_M 0x08000000 +#define GPIO_DOUT31_0_DIO27_S 27 // Field: [26] DIO26 // // Data output for DIO 26 -#define GPIO_DOUT31_0_DIO26 0x04000000 -#define GPIO_DOUT31_0_DIO26_BITN 26 -#define GPIO_DOUT31_0_DIO26_M 0x04000000 -#define GPIO_DOUT31_0_DIO26_S 26 +#define GPIO_DOUT31_0_DIO26 0x04000000 +#define GPIO_DOUT31_0_DIO26_BITN 26 +#define GPIO_DOUT31_0_DIO26_M 0x04000000 +#define GPIO_DOUT31_0_DIO26_S 26 // Field: [25] DIO25 // // Data output for DIO 25 -#define GPIO_DOUT31_0_DIO25 0x02000000 -#define GPIO_DOUT31_0_DIO25_BITN 25 -#define GPIO_DOUT31_0_DIO25_M 0x02000000 -#define GPIO_DOUT31_0_DIO25_S 25 +#define GPIO_DOUT31_0_DIO25 0x02000000 +#define GPIO_DOUT31_0_DIO25_BITN 25 +#define GPIO_DOUT31_0_DIO25_M 0x02000000 +#define GPIO_DOUT31_0_DIO25_S 25 // Field: [24] DIO24 // // Data output for DIO 24 -#define GPIO_DOUT31_0_DIO24 0x01000000 -#define GPIO_DOUT31_0_DIO24_BITN 24 -#define GPIO_DOUT31_0_DIO24_M 0x01000000 -#define GPIO_DOUT31_0_DIO24_S 24 +#define GPIO_DOUT31_0_DIO24 0x01000000 +#define GPIO_DOUT31_0_DIO24_BITN 24 +#define GPIO_DOUT31_0_DIO24_M 0x01000000 +#define GPIO_DOUT31_0_DIO24_S 24 // Field: [23] DIO23 // // Data output for DIO 23 -#define GPIO_DOUT31_0_DIO23 0x00800000 -#define GPIO_DOUT31_0_DIO23_BITN 23 -#define GPIO_DOUT31_0_DIO23_M 0x00800000 -#define GPIO_DOUT31_0_DIO23_S 23 +#define GPIO_DOUT31_0_DIO23 0x00800000 +#define GPIO_DOUT31_0_DIO23_BITN 23 +#define GPIO_DOUT31_0_DIO23_M 0x00800000 +#define GPIO_DOUT31_0_DIO23_S 23 // Field: [22] DIO22 // // Data output for DIO 22 -#define GPIO_DOUT31_0_DIO22 0x00400000 -#define GPIO_DOUT31_0_DIO22_BITN 22 -#define GPIO_DOUT31_0_DIO22_M 0x00400000 -#define GPIO_DOUT31_0_DIO22_S 22 +#define GPIO_DOUT31_0_DIO22 0x00400000 +#define GPIO_DOUT31_0_DIO22_BITN 22 +#define GPIO_DOUT31_0_DIO22_M 0x00400000 +#define GPIO_DOUT31_0_DIO22_S 22 // Field: [21] DIO21 // // Data output for DIO 21 -#define GPIO_DOUT31_0_DIO21 0x00200000 -#define GPIO_DOUT31_0_DIO21_BITN 21 -#define GPIO_DOUT31_0_DIO21_M 0x00200000 -#define GPIO_DOUT31_0_DIO21_S 21 +#define GPIO_DOUT31_0_DIO21 0x00200000 +#define GPIO_DOUT31_0_DIO21_BITN 21 +#define GPIO_DOUT31_0_DIO21_M 0x00200000 +#define GPIO_DOUT31_0_DIO21_S 21 // Field: [20] DIO20 // // Data output for DIO 20 -#define GPIO_DOUT31_0_DIO20 0x00100000 -#define GPIO_DOUT31_0_DIO20_BITN 20 -#define GPIO_DOUT31_0_DIO20_M 0x00100000 -#define GPIO_DOUT31_0_DIO20_S 20 +#define GPIO_DOUT31_0_DIO20 0x00100000 +#define GPIO_DOUT31_0_DIO20_BITN 20 +#define GPIO_DOUT31_0_DIO20_M 0x00100000 +#define GPIO_DOUT31_0_DIO20_S 20 // Field: [19] DIO19 // // Data output for DIO 19 -#define GPIO_DOUT31_0_DIO19 0x00080000 -#define GPIO_DOUT31_0_DIO19_BITN 19 -#define GPIO_DOUT31_0_DIO19_M 0x00080000 -#define GPIO_DOUT31_0_DIO19_S 19 +#define GPIO_DOUT31_0_DIO19 0x00080000 +#define GPIO_DOUT31_0_DIO19_BITN 19 +#define GPIO_DOUT31_0_DIO19_M 0x00080000 +#define GPIO_DOUT31_0_DIO19_S 19 // Field: [18] DIO18 // // Data output for DIO 18 -#define GPIO_DOUT31_0_DIO18 0x00040000 -#define GPIO_DOUT31_0_DIO18_BITN 18 -#define GPIO_DOUT31_0_DIO18_M 0x00040000 -#define GPIO_DOUT31_0_DIO18_S 18 +#define GPIO_DOUT31_0_DIO18 0x00040000 +#define GPIO_DOUT31_0_DIO18_BITN 18 +#define GPIO_DOUT31_0_DIO18_M 0x00040000 +#define GPIO_DOUT31_0_DIO18_S 18 // Field: [17] DIO17 // // Data output for DIO 17 -#define GPIO_DOUT31_0_DIO17 0x00020000 -#define GPIO_DOUT31_0_DIO17_BITN 17 -#define GPIO_DOUT31_0_DIO17_M 0x00020000 -#define GPIO_DOUT31_0_DIO17_S 17 +#define GPIO_DOUT31_0_DIO17 0x00020000 +#define GPIO_DOUT31_0_DIO17_BITN 17 +#define GPIO_DOUT31_0_DIO17_M 0x00020000 +#define GPIO_DOUT31_0_DIO17_S 17 // Field: [16] DIO16 // // Data output for DIO 16 -#define GPIO_DOUT31_0_DIO16 0x00010000 -#define GPIO_DOUT31_0_DIO16_BITN 16 -#define GPIO_DOUT31_0_DIO16_M 0x00010000 -#define GPIO_DOUT31_0_DIO16_S 16 +#define GPIO_DOUT31_0_DIO16 0x00010000 +#define GPIO_DOUT31_0_DIO16_BITN 16 +#define GPIO_DOUT31_0_DIO16_M 0x00010000 +#define GPIO_DOUT31_0_DIO16_S 16 // Field: [15] DIO15 // // Data output for DIO 15 -#define GPIO_DOUT31_0_DIO15 0x00008000 -#define GPIO_DOUT31_0_DIO15_BITN 15 -#define GPIO_DOUT31_0_DIO15_M 0x00008000 -#define GPIO_DOUT31_0_DIO15_S 15 +#define GPIO_DOUT31_0_DIO15 0x00008000 +#define GPIO_DOUT31_0_DIO15_BITN 15 +#define GPIO_DOUT31_0_DIO15_M 0x00008000 +#define GPIO_DOUT31_0_DIO15_S 15 // Field: [14] DIO14 // // Data output for DIO 14 -#define GPIO_DOUT31_0_DIO14 0x00004000 -#define GPIO_DOUT31_0_DIO14_BITN 14 -#define GPIO_DOUT31_0_DIO14_M 0x00004000 -#define GPIO_DOUT31_0_DIO14_S 14 +#define GPIO_DOUT31_0_DIO14 0x00004000 +#define GPIO_DOUT31_0_DIO14_BITN 14 +#define GPIO_DOUT31_0_DIO14_M 0x00004000 +#define GPIO_DOUT31_0_DIO14_S 14 // Field: [13] DIO13 // // Data output for DIO 13 -#define GPIO_DOUT31_0_DIO13 0x00002000 -#define GPIO_DOUT31_0_DIO13_BITN 13 -#define GPIO_DOUT31_0_DIO13_M 0x00002000 -#define GPIO_DOUT31_0_DIO13_S 13 +#define GPIO_DOUT31_0_DIO13 0x00002000 +#define GPIO_DOUT31_0_DIO13_BITN 13 +#define GPIO_DOUT31_0_DIO13_M 0x00002000 +#define GPIO_DOUT31_0_DIO13_S 13 // Field: [12] DIO12 // // Data output for DIO 12 -#define GPIO_DOUT31_0_DIO12 0x00001000 -#define GPIO_DOUT31_0_DIO12_BITN 12 -#define GPIO_DOUT31_0_DIO12_M 0x00001000 -#define GPIO_DOUT31_0_DIO12_S 12 +#define GPIO_DOUT31_0_DIO12 0x00001000 +#define GPIO_DOUT31_0_DIO12_BITN 12 +#define GPIO_DOUT31_0_DIO12_M 0x00001000 +#define GPIO_DOUT31_0_DIO12_S 12 // Field: [11] DIO11 // // Data output for DIO 11 -#define GPIO_DOUT31_0_DIO11 0x00000800 -#define GPIO_DOUT31_0_DIO11_BITN 11 -#define GPIO_DOUT31_0_DIO11_M 0x00000800 -#define GPIO_DOUT31_0_DIO11_S 11 +#define GPIO_DOUT31_0_DIO11 0x00000800 +#define GPIO_DOUT31_0_DIO11_BITN 11 +#define GPIO_DOUT31_0_DIO11_M 0x00000800 +#define GPIO_DOUT31_0_DIO11_S 11 // Field: [10] DIO10 // // Data output for DIO 10 -#define GPIO_DOUT31_0_DIO10 0x00000400 -#define GPIO_DOUT31_0_DIO10_BITN 10 -#define GPIO_DOUT31_0_DIO10_M 0x00000400 -#define GPIO_DOUT31_0_DIO10_S 10 +#define GPIO_DOUT31_0_DIO10 0x00000400 +#define GPIO_DOUT31_0_DIO10_BITN 10 +#define GPIO_DOUT31_0_DIO10_M 0x00000400 +#define GPIO_DOUT31_0_DIO10_S 10 // Field: [9] DIO9 // // Data output for DIO 9 -#define GPIO_DOUT31_0_DIO9 0x00000200 -#define GPIO_DOUT31_0_DIO9_BITN 9 -#define GPIO_DOUT31_0_DIO9_M 0x00000200 -#define GPIO_DOUT31_0_DIO9_S 9 +#define GPIO_DOUT31_0_DIO9 0x00000200 +#define GPIO_DOUT31_0_DIO9_BITN 9 +#define GPIO_DOUT31_0_DIO9_M 0x00000200 +#define GPIO_DOUT31_0_DIO9_S 9 // Field: [8] DIO8 // // Data output for DIO 8 -#define GPIO_DOUT31_0_DIO8 0x00000100 -#define GPIO_DOUT31_0_DIO8_BITN 8 -#define GPIO_DOUT31_0_DIO8_M 0x00000100 -#define GPIO_DOUT31_0_DIO8_S 8 +#define GPIO_DOUT31_0_DIO8 0x00000100 +#define GPIO_DOUT31_0_DIO8_BITN 8 +#define GPIO_DOUT31_0_DIO8_M 0x00000100 +#define GPIO_DOUT31_0_DIO8_S 8 // Field: [7] DIO7 // // Data output for DIO 7 -#define GPIO_DOUT31_0_DIO7 0x00000080 -#define GPIO_DOUT31_0_DIO7_BITN 7 -#define GPIO_DOUT31_0_DIO7_M 0x00000080 -#define GPIO_DOUT31_0_DIO7_S 7 +#define GPIO_DOUT31_0_DIO7 0x00000080 +#define GPIO_DOUT31_0_DIO7_BITN 7 +#define GPIO_DOUT31_0_DIO7_M 0x00000080 +#define GPIO_DOUT31_0_DIO7_S 7 // Field: [6] DIO6 // // Data output for DIO 6 -#define GPIO_DOUT31_0_DIO6 0x00000040 -#define GPIO_DOUT31_0_DIO6_BITN 6 -#define GPIO_DOUT31_0_DIO6_M 0x00000040 -#define GPIO_DOUT31_0_DIO6_S 6 +#define GPIO_DOUT31_0_DIO6 0x00000040 +#define GPIO_DOUT31_0_DIO6_BITN 6 +#define GPIO_DOUT31_0_DIO6_M 0x00000040 +#define GPIO_DOUT31_0_DIO6_S 6 // Field: [5] DIO5 // // Data output for DIO 5 -#define GPIO_DOUT31_0_DIO5 0x00000020 -#define GPIO_DOUT31_0_DIO5_BITN 5 -#define GPIO_DOUT31_0_DIO5_M 0x00000020 -#define GPIO_DOUT31_0_DIO5_S 5 +#define GPIO_DOUT31_0_DIO5 0x00000020 +#define GPIO_DOUT31_0_DIO5_BITN 5 +#define GPIO_DOUT31_0_DIO5_M 0x00000020 +#define GPIO_DOUT31_0_DIO5_S 5 // Field: [4] DIO4 // // Data output for DIO 4 -#define GPIO_DOUT31_0_DIO4 0x00000010 -#define GPIO_DOUT31_0_DIO4_BITN 4 -#define GPIO_DOUT31_0_DIO4_M 0x00000010 -#define GPIO_DOUT31_0_DIO4_S 4 +#define GPIO_DOUT31_0_DIO4 0x00000010 +#define GPIO_DOUT31_0_DIO4_BITN 4 +#define GPIO_DOUT31_0_DIO4_M 0x00000010 +#define GPIO_DOUT31_0_DIO4_S 4 // Field: [3] DIO3 // // Data output for DIO 3 -#define GPIO_DOUT31_0_DIO3 0x00000008 -#define GPIO_DOUT31_0_DIO3_BITN 3 -#define GPIO_DOUT31_0_DIO3_M 0x00000008 -#define GPIO_DOUT31_0_DIO3_S 3 +#define GPIO_DOUT31_0_DIO3 0x00000008 +#define GPIO_DOUT31_0_DIO3_BITN 3 +#define GPIO_DOUT31_0_DIO3_M 0x00000008 +#define GPIO_DOUT31_0_DIO3_S 3 // Field: [2] DIO2 // // Data output for DIO 2 -#define GPIO_DOUT31_0_DIO2 0x00000004 -#define GPIO_DOUT31_0_DIO2_BITN 2 -#define GPIO_DOUT31_0_DIO2_M 0x00000004 -#define GPIO_DOUT31_0_DIO2_S 2 +#define GPIO_DOUT31_0_DIO2 0x00000004 +#define GPIO_DOUT31_0_DIO2_BITN 2 +#define GPIO_DOUT31_0_DIO2_M 0x00000004 +#define GPIO_DOUT31_0_DIO2_S 2 // Field: [1] DIO1 // // Data output for DIO 1 -#define GPIO_DOUT31_0_DIO1 0x00000002 -#define GPIO_DOUT31_0_DIO1_BITN 1 -#define GPIO_DOUT31_0_DIO1_M 0x00000002 -#define GPIO_DOUT31_0_DIO1_S 1 +#define GPIO_DOUT31_0_DIO1 0x00000002 +#define GPIO_DOUT31_0_DIO1_BITN 1 +#define GPIO_DOUT31_0_DIO1_M 0x00000002 +#define GPIO_DOUT31_0_DIO1_S 1 // Field: [0] DIO0 // // Data output for DIO 0 -#define GPIO_DOUT31_0_DIO0 0x00000001 -#define GPIO_DOUT31_0_DIO0_BITN 0 -#define GPIO_DOUT31_0_DIO0_M 0x00000001 -#define GPIO_DOUT31_0_DIO0_S 0 +#define GPIO_DOUT31_0_DIO0 0x00000001 +#define GPIO_DOUT31_0_DIO0_BITN 0 +#define GPIO_DOUT31_0_DIO0_M 0x00000001 +#define GPIO_DOUT31_0_DIO0_S 0 //***************************************************************************** // @@ -685,258 +685,258 @@ // Field: [31] DIO31 // // Set bit 31 -#define GPIO_DOUTSET31_0_DIO31 0x80000000 -#define GPIO_DOUTSET31_0_DIO31_BITN 31 -#define GPIO_DOUTSET31_0_DIO31_M 0x80000000 -#define GPIO_DOUTSET31_0_DIO31_S 31 +#define GPIO_DOUTSET31_0_DIO31 0x80000000 +#define GPIO_DOUTSET31_0_DIO31_BITN 31 +#define GPIO_DOUTSET31_0_DIO31_M 0x80000000 +#define GPIO_DOUTSET31_0_DIO31_S 31 // Field: [30] DIO30 // // Set bit 30 -#define GPIO_DOUTSET31_0_DIO30 0x40000000 -#define GPIO_DOUTSET31_0_DIO30_BITN 30 -#define GPIO_DOUTSET31_0_DIO30_M 0x40000000 -#define GPIO_DOUTSET31_0_DIO30_S 30 +#define GPIO_DOUTSET31_0_DIO30 0x40000000 +#define GPIO_DOUTSET31_0_DIO30_BITN 30 +#define GPIO_DOUTSET31_0_DIO30_M 0x40000000 +#define GPIO_DOUTSET31_0_DIO30_S 30 // Field: [29] DIO29 // // Set bit 29 -#define GPIO_DOUTSET31_0_DIO29 0x20000000 -#define GPIO_DOUTSET31_0_DIO29_BITN 29 -#define GPIO_DOUTSET31_0_DIO29_M 0x20000000 -#define GPIO_DOUTSET31_0_DIO29_S 29 +#define GPIO_DOUTSET31_0_DIO29 0x20000000 +#define GPIO_DOUTSET31_0_DIO29_BITN 29 +#define GPIO_DOUTSET31_0_DIO29_M 0x20000000 +#define GPIO_DOUTSET31_0_DIO29_S 29 // Field: [28] DIO28 // // Set bit 28 -#define GPIO_DOUTSET31_0_DIO28 0x10000000 -#define GPIO_DOUTSET31_0_DIO28_BITN 28 -#define GPIO_DOUTSET31_0_DIO28_M 0x10000000 -#define GPIO_DOUTSET31_0_DIO28_S 28 +#define GPIO_DOUTSET31_0_DIO28 0x10000000 +#define GPIO_DOUTSET31_0_DIO28_BITN 28 +#define GPIO_DOUTSET31_0_DIO28_M 0x10000000 +#define GPIO_DOUTSET31_0_DIO28_S 28 // Field: [27] DIO27 // // Set bit 27 -#define GPIO_DOUTSET31_0_DIO27 0x08000000 -#define GPIO_DOUTSET31_0_DIO27_BITN 27 -#define GPIO_DOUTSET31_0_DIO27_M 0x08000000 -#define GPIO_DOUTSET31_0_DIO27_S 27 +#define GPIO_DOUTSET31_0_DIO27 0x08000000 +#define GPIO_DOUTSET31_0_DIO27_BITN 27 +#define GPIO_DOUTSET31_0_DIO27_M 0x08000000 +#define GPIO_DOUTSET31_0_DIO27_S 27 // Field: [26] DIO26 // // Set bit 26 -#define GPIO_DOUTSET31_0_DIO26 0x04000000 -#define GPIO_DOUTSET31_0_DIO26_BITN 26 -#define GPIO_DOUTSET31_0_DIO26_M 0x04000000 -#define GPIO_DOUTSET31_0_DIO26_S 26 +#define GPIO_DOUTSET31_0_DIO26 0x04000000 +#define GPIO_DOUTSET31_0_DIO26_BITN 26 +#define GPIO_DOUTSET31_0_DIO26_M 0x04000000 +#define GPIO_DOUTSET31_0_DIO26_S 26 // Field: [25] DIO25 // // Set bit 25 -#define GPIO_DOUTSET31_0_DIO25 0x02000000 -#define GPIO_DOUTSET31_0_DIO25_BITN 25 -#define GPIO_DOUTSET31_0_DIO25_M 0x02000000 -#define GPIO_DOUTSET31_0_DIO25_S 25 +#define GPIO_DOUTSET31_0_DIO25 0x02000000 +#define GPIO_DOUTSET31_0_DIO25_BITN 25 +#define GPIO_DOUTSET31_0_DIO25_M 0x02000000 +#define GPIO_DOUTSET31_0_DIO25_S 25 // Field: [24] DIO24 // // Set bit 24 -#define GPIO_DOUTSET31_0_DIO24 0x01000000 -#define GPIO_DOUTSET31_0_DIO24_BITN 24 -#define GPIO_DOUTSET31_0_DIO24_M 0x01000000 -#define GPIO_DOUTSET31_0_DIO24_S 24 +#define GPIO_DOUTSET31_0_DIO24 0x01000000 +#define GPIO_DOUTSET31_0_DIO24_BITN 24 +#define GPIO_DOUTSET31_0_DIO24_M 0x01000000 +#define GPIO_DOUTSET31_0_DIO24_S 24 // Field: [23] DIO23 // // Set bit 23 -#define GPIO_DOUTSET31_0_DIO23 0x00800000 -#define GPIO_DOUTSET31_0_DIO23_BITN 23 -#define GPIO_DOUTSET31_0_DIO23_M 0x00800000 -#define GPIO_DOUTSET31_0_DIO23_S 23 +#define GPIO_DOUTSET31_0_DIO23 0x00800000 +#define GPIO_DOUTSET31_0_DIO23_BITN 23 +#define GPIO_DOUTSET31_0_DIO23_M 0x00800000 +#define GPIO_DOUTSET31_0_DIO23_S 23 // Field: [22] DIO22 // // Set bit 22 -#define GPIO_DOUTSET31_0_DIO22 0x00400000 -#define GPIO_DOUTSET31_0_DIO22_BITN 22 -#define GPIO_DOUTSET31_0_DIO22_M 0x00400000 -#define GPIO_DOUTSET31_0_DIO22_S 22 +#define GPIO_DOUTSET31_0_DIO22 0x00400000 +#define GPIO_DOUTSET31_0_DIO22_BITN 22 +#define GPIO_DOUTSET31_0_DIO22_M 0x00400000 +#define GPIO_DOUTSET31_0_DIO22_S 22 // Field: [21] DIO21 // // Set bit 21 -#define GPIO_DOUTSET31_0_DIO21 0x00200000 -#define GPIO_DOUTSET31_0_DIO21_BITN 21 -#define GPIO_DOUTSET31_0_DIO21_M 0x00200000 -#define GPIO_DOUTSET31_0_DIO21_S 21 +#define GPIO_DOUTSET31_0_DIO21 0x00200000 +#define GPIO_DOUTSET31_0_DIO21_BITN 21 +#define GPIO_DOUTSET31_0_DIO21_M 0x00200000 +#define GPIO_DOUTSET31_0_DIO21_S 21 // Field: [20] DIO20 // // Set bit 20 -#define GPIO_DOUTSET31_0_DIO20 0x00100000 -#define GPIO_DOUTSET31_0_DIO20_BITN 20 -#define GPIO_DOUTSET31_0_DIO20_M 0x00100000 -#define GPIO_DOUTSET31_0_DIO20_S 20 +#define GPIO_DOUTSET31_0_DIO20 0x00100000 +#define GPIO_DOUTSET31_0_DIO20_BITN 20 +#define GPIO_DOUTSET31_0_DIO20_M 0x00100000 +#define GPIO_DOUTSET31_0_DIO20_S 20 // Field: [19] DIO19 // // Set bit 19 -#define GPIO_DOUTSET31_0_DIO19 0x00080000 -#define GPIO_DOUTSET31_0_DIO19_BITN 19 -#define GPIO_DOUTSET31_0_DIO19_M 0x00080000 -#define GPIO_DOUTSET31_0_DIO19_S 19 +#define GPIO_DOUTSET31_0_DIO19 0x00080000 +#define GPIO_DOUTSET31_0_DIO19_BITN 19 +#define GPIO_DOUTSET31_0_DIO19_M 0x00080000 +#define GPIO_DOUTSET31_0_DIO19_S 19 // Field: [18] DIO18 // // Set bit 18 -#define GPIO_DOUTSET31_0_DIO18 0x00040000 -#define GPIO_DOUTSET31_0_DIO18_BITN 18 -#define GPIO_DOUTSET31_0_DIO18_M 0x00040000 -#define GPIO_DOUTSET31_0_DIO18_S 18 +#define GPIO_DOUTSET31_0_DIO18 0x00040000 +#define GPIO_DOUTSET31_0_DIO18_BITN 18 +#define GPIO_DOUTSET31_0_DIO18_M 0x00040000 +#define GPIO_DOUTSET31_0_DIO18_S 18 // Field: [17] DIO17 // // Set bit 17 -#define GPIO_DOUTSET31_0_DIO17 0x00020000 -#define GPIO_DOUTSET31_0_DIO17_BITN 17 -#define GPIO_DOUTSET31_0_DIO17_M 0x00020000 -#define GPIO_DOUTSET31_0_DIO17_S 17 +#define GPIO_DOUTSET31_0_DIO17 0x00020000 +#define GPIO_DOUTSET31_0_DIO17_BITN 17 +#define GPIO_DOUTSET31_0_DIO17_M 0x00020000 +#define GPIO_DOUTSET31_0_DIO17_S 17 // Field: [16] DIO16 // // Set bit 16 -#define GPIO_DOUTSET31_0_DIO16 0x00010000 -#define GPIO_DOUTSET31_0_DIO16_BITN 16 -#define GPIO_DOUTSET31_0_DIO16_M 0x00010000 -#define GPIO_DOUTSET31_0_DIO16_S 16 +#define GPIO_DOUTSET31_0_DIO16 0x00010000 +#define GPIO_DOUTSET31_0_DIO16_BITN 16 +#define GPIO_DOUTSET31_0_DIO16_M 0x00010000 +#define GPIO_DOUTSET31_0_DIO16_S 16 // Field: [15] DIO15 // // Set bit 15 -#define GPIO_DOUTSET31_0_DIO15 0x00008000 -#define GPIO_DOUTSET31_0_DIO15_BITN 15 -#define GPIO_DOUTSET31_0_DIO15_M 0x00008000 -#define GPIO_DOUTSET31_0_DIO15_S 15 +#define GPIO_DOUTSET31_0_DIO15 0x00008000 +#define GPIO_DOUTSET31_0_DIO15_BITN 15 +#define GPIO_DOUTSET31_0_DIO15_M 0x00008000 +#define GPIO_DOUTSET31_0_DIO15_S 15 // Field: [14] DIO14 // // Set bit 14 -#define GPIO_DOUTSET31_0_DIO14 0x00004000 -#define GPIO_DOUTSET31_0_DIO14_BITN 14 -#define GPIO_DOUTSET31_0_DIO14_M 0x00004000 -#define GPIO_DOUTSET31_0_DIO14_S 14 +#define GPIO_DOUTSET31_0_DIO14 0x00004000 +#define GPIO_DOUTSET31_0_DIO14_BITN 14 +#define GPIO_DOUTSET31_0_DIO14_M 0x00004000 +#define GPIO_DOUTSET31_0_DIO14_S 14 // Field: [13] DIO13 // // Set bit 13 -#define GPIO_DOUTSET31_0_DIO13 0x00002000 -#define GPIO_DOUTSET31_0_DIO13_BITN 13 -#define GPIO_DOUTSET31_0_DIO13_M 0x00002000 -#define GPIO_DOUTSET31_0_DIO13_S 13 +#define GPIO_DOUTSET31_0_DIO13 0x00002000 +#define GPIO_DOUTSET31_0_DIO13_BITN 13 +#define GPIO_DOUTSET31_0_DIO13_M 0x00002000 +#define GPIO_DOUTSET31_0_DIO13_S 13 // Field: [12] DIO12 // // Set bit 12 -#define GPIO_DOUTSET31_0_DIO12 0x00001000 -#define GPIO_DOUTSET31_0_DIO12_BITN 12 -#define GPIO_DOUTSET31_0_DIO12_M 0x00001000 -#define GPIO_DOUTSET31_0_DIO12_S 12 +#define GPIO_DOUTSET31_0_DIO12 0x00001000 +#define GPIO_DOUTSET31_0_DIO12_BITN 12 +#define GPIO_DOUTSET31_0_DIO12_M 0x00001000 +#define GPIO_DOUTSET31_0_DIO12_S 12 // Field: [11] DIO11 // // Set bit 11 -#define GPIO_DOUTSET31_0_DIO11 0x00000800 -#define GPIO_DOUTSET31_0_DIO11_BITN 11 -#define GPIO_DOUTSET31_0_DIO11_M 0x00000800 -#define GPIO_DOUTSET31_0_DIO11_S 11 +#define GPIO_DOUTSET31_0_DIO11 0x00000800 +#define GPIO_DOUTSET31_0_DIO11_BITN 11 +#define GPIO_DOUTSET31_0_DIO11_M 0x00000800 +#define GPIO_DOUTSET31_0_DIO11_S 11 // Field: [10] DIO10 // // Set bit 10 -#define GPIO_DOUTSET31_0_DIO10 0x00000400 -#define GPIO_DOUTSET31_0_DIO10_BITN 10 -#define GPIO_DOUTSET31_0_DIO10_M 0x00000400 -#define GPIO_DOUTSET31_0_DIO10_S 10 +#define GPIO_DOUTSET31_0_DIO10 0x00000400 +#define GPIO_DOUTSET31_0_DIO10_BITN 10 +#define GPIO_DOUTSET31_0_DIO10_M 0x00000400 +#define GPIO_DOUTSET31_0_DIO10_S 10 // Field: [9] DIO9 // // Set bit 9 -#define GPIO_DOUTSET31_0_DIO9 0x00000200 -#define GPIO_DOUTSET31_0_DIO9_BITN 9 -#define GPIO_DOUTSET31_0_DIO9_M 0x00000200 -#define GPIO_DOUTSET31_0_DIO9_S 9 +#define GPIO_DOUTSET31_0_DIO9 0x00000200 +#define GPIO_DOUTSET31_0_DIO9_BITN 9 +#define GPIO_DOUTSET31_0_DIO9_M 0x00000200 +#define GPIO_DOUTSET31_0_DIO9_S 9 // Field: [8] DIO8 // // Set bit 8 -#define GPIO_DOUTSET31_0_DIO8 0x00000100 -#define GPIO_DOUTSET31_0_DIO8_BITN 8 -#define GPIO_DOUTSET31_0_DIO8_M 0x00000100 -#define GPIO_DOUTSET31_0_DIO8_S 8 +#define GPIO_DOUTSET31_0_DIO8 0x00000100 +#define GPIO_DOUTSET31_0_DIO8_BITN 8 +#define GPIO_DOUTSET31_0_DIO8_M 0x00000100 +#define GPIO_DOUTSET31_0_DIO8_S 8 // Field: [7] DIO7 // // Set bit 7 -#define GPIO_DOUTSET31_0_DIO7 0x00000080 -#define GPIO_DOUTSET31_0_DIO7_BITN 7 -#define GPIO_DOUTSET31_0_DIO7_M 0x00000080 -#define GPIO_DOUTSET31_0_DIO7_S 7 +#define GPIO_DOUTSET31_0_DIO7 0x00000080 +#define GPIO_DOUTSET31_0_DIO7_BITN 7 +#define GPIO_DOUTSET31_0_DIO7_M 0x00000080 +#define GPIO_DOUTSET31_0_DIO7_S 7 // Field: [6] DIO6 // // Set bit 6 -#define GPIO_DOUTSET31_0_DIO6 0x00000040 -#define GPIO_DOUTSET31_0_DIO6_BITN 6 -#define GPIO_DOUTSET31_0_DIO6_M 0x00000040 -#define GPIO_DOUTSET31_0_DIO6_S 6 +#define GPIO_DOUTSET31_0_DIO6 0x00000040 +#define GPIO_DOUTSET31_0_DIO6_BITN 6 +#define GPIO_DOUTSET31_0_DIO6_M 0x00000040 +#define GPIO_DOUTSET31_0_DIO6_S 6 // Field: [5] DIO5 // // Set bit 5 -#define GPIO_DOUTSET31_0_DIO5 0x00000020 -#define GPIO_DOUTSET31_0_DIO5_BITN 5 -#define GPIO_DOUTSET31_0_DIO5_M 0x00000020 -#define GPIO_DOUTSET31_0_DIO5_S 5 +#define GPIO_DOUTSET31_0_DIO5 0x00000020 +#define GPIO_DOUTSET31_0_DIO5_BITN 5 +#define GPIO_DOUTSET31_0_DIO5_M 0x00000020 +#define GPIO_DOUTSET31_0_DIO5_S 5 // Field: [4] DIO4 // // Set bit 4 -#define GPIO_DOUTSET31_0_DIO4 0x00000010 -#define GPIO_DOUTSET31_0_DIO4_BITN 4 -#define GPIO_DOUTSET31_0_DIO4_M 0x00000010 -#define GPIO_DOUTSET31_0_DIO4_S 4 +#define GPIO_DOUTSET31_0_DIO4 0x00000010 +#define GPIO_DOUTSET31_0_DIO4_BITN 4 +#define GPIO_DOUTSET31_0_DIO4_M 0x00000010 +#define GPIO_DOUTSET31_0_DIO4_S 4 // Field: [3] DIO3 // // Set bit 3 -#define GPIO_DOUTSET31_0_DIO3 0x00000008 -#define GPIO_DOUTSET31_0_DIO3_BITN 3 -#define GPIO_DOUTSET31_0_DIO3_M 0x00000008 -#define GPIO_DOUTSET31_0_DIO3_S 3 +#define GPIO_DOUTSET31_0_DIO3 0x00000008 +#define GPIO_DOUTSET31_0_DIO3_BITN 3 +#define GPIO_DOUTSET31_0_DIO3_M 0x00000008 +#define GPIO_DOUTSET31_0_DIO3_S 3 // Field: [2] DIO2 // // Set bit 2 -#define GPIO_DOUTSET31_0_DIO2 0x00000004 -#define GPIO_DOUTSET31_0_DIO2_BITN 2 -#define GPIO_DOUTSET31_0_DIO2_M 0x00000004 -#define GPIO_DOUTSET31_0_DIO2_S 2 +#define GPIO_DOUTSET31_0_DIO2 0x00000004 +#define GPIO_DOUTSET31_0_DIO2_BITN 2 +#define GPIO_DOUTSET31_0_DIO2_M 0x00000004 +#define GPIO_DOUTSET31_0_DIO2_S 2 // Field: [1] DIO1 // // Set bit 1 -#define GPIO_DOUTSET31_0_DIO1 0x00000002 -#define GPIO_DOUTSET31_0_DIO1_BITN 1 -#define GPIO_DOUTSET31_0_DIO1_M 0x00000002 -#define GPIO_DOUTSET31_0_DIO1_S 1 +#define GPIO_DOUTSET31_0_DIO1 0x00000002 +#define GPIO_DOUTSET31_0_DIO1_BITN 1 +#define GPIO_DOUTSET31_0_DIO1_M 0x00000002 +#define GPIO_DOUTSET31_0_DIO1_S 1 // Field: [0] DIO0 // // Set bit 0 -#define GPIO_DOUTSET31_0_DIO0 0x00000001 -#define GPIO_DOUTSET31_0_DIO0_BITN 0 -#define GPIO_DOUTSET31_0_DIO0_M 0x00000001 -#define GPIO_DOUTSET31_0_DIO0_S 0 +#define GPIO_DOUTSET31_0_DIO0 0x00000001 +#define GPIO_DOUTSET31_0_DIO0_BITN 0 +#define GPIO_DOUTSET31_0_DIO0_M 0x00000001 +#define GPIO_DOUTSET31_0_DIO0_S 0 //***************************************************************************** // @@ -946,258 +946,258 @@ // Field: [31] DIO31 // // Clears bit 31 -#define GPIO_DOUTCLR31_0_DIO31 0x80000000 -#define GPIO_DOUTCLR31_0_DIO31_BITN 31 -#define GPIO_DOUTCLR31_0_DIO31_M 0x80000000 -#define GPIO_DOUTCLR31_0_DIO31_S 31 +#define GPIO_DOUTCLR31_0_DIO31 0x80000000 +#define GPIO_DOUTCLR31_0_DIO31_BITN 31 +#define GPIO_DOUTCLR31_0_DIO31_M 0x80000000 +#define GPIO_DOUTCLR31_0_DIO31_S 31 // Field: [30] DIO30 // // Clears bit 30 -#define GPIO_DOUTCLR31_0_DIO30 0x40000000 -#define GPIO_DOUTCLR31_0_DIO30_BITN 30 -#define GPIO_DOUTCLR31_0_DIO30_M 0x40000000 -#define GPIO_DOUTCLR31_0_DIO30_S 30 +#define GPIO_DOUTCLR31_0_DIO30 0x40000000 +#define GPIO_DOUTCLR31_0_DIO30_BITN 30 +#define GPIO_DOUTCLR31_0_DIO30_M 0x40000000 +#define GPIO_DOUTCLR31_0_DIO30_S 30 // Field: [29] DIO29 // // Clears bit 29 -#define GPIO_DOUTCLR31_0_DIO29 0x20000000 -#define GPIO_DOUTCLR31_0_DIO29_BITN 29 -#define GPIO_DOUTCLR31_0_DIO29_M 0x20000000 -#define GPIO_DOUTCLR31_0_DIO29_S 29 +#define GPIO_DOUTCLR31_0_DIO29 0x20000000 +#define GPIO_DOUTCLR31_0_DIO29_BITN 29 +#define GPIO_DOUTCLR31_0_DIO29_M 0x20000000 +#define GPIO_DOUTCLR31_0_DIO29_S 29 // Field: [28] DIO28 // // Clears bit 28 -#define GPIO_DOUTCLR31_0_DIO28 0x10000000 -#define GPIO_DOUTCLR31_0_DIO28_BITN 28 -#define GPIO_DOUTCLR31_0_DIO28_M 0x10000000 -#define GPIO_DOUTCLR31_0_DIO28_S 28 +#define GPIO_DOUTCLR31_0_DIO28 0x10000000 +#define GPIO_DOUTCLR31_0_DIO28_BITN 28 +#define GPIO_DOUTCLR31_0_DIO28_M 0x10000000 +#define GPIO_DOUTCLR31_0_DIO28_S 28 // Field: [27] DIO27 // // Clears bit 27 -#define GPIO_DOUTCLR31_0_DIO27 0x08000000 -#define GPIO_DOUTCLR31_0_DIO27_BITN 27 -#define GPIO_DOUTCLR31_0_DIO27_M 0x08000000 -#define GPIO_DOUTCLR31_0_DIO27_S 27 +#define GPIO_DOUTCLR31_0_DIO27 0x08000000 +#define GPIO_DOUTCLR31_0_DIO27_BITN 27 +#define GPIO_DOUTCLR31_0_DIO27_M 0x08000000 +#define GPIO_DOUTCLR31_0_DIO27_S 27 // Field: [26] DIO26 // // Clears bit 26 -#define GPIO_DOUTCLR31_0_DIO26 0x04000000 -#define GPIO_DOUTCLR31_0_DIO26_BITN 26 -#define GPIO_DOUTCLR31_0_DIO26_M 0x04000000 -#define GPIO_DOUTCLR31_0_DIO26_S 26 +#define GPIO_DOUTCLR31_0_DIO26 0x04000000 +#define GPIO_DOUTCLR31_0_DIO26_BITN 26 +#define GPIO_DOUTCLR31_0_DIO26_M 0x04000000 +#define GPIO_DOUTCLR31_0_DIO26_S 26 // Field: [25] DIO25 // // Clears bit 25 -#define GPIO_DOUTCLR31_0_DIO25 0x02000000 -#define GPIO_DOUTCLR31_0_DIO25_BITN 25 -#define GPIO_DOUTCLR31_0_DIO25_M 0x02000000 -#define GPIO_DOUTCLR31_0_DIO25_S 25 +#define GPIO_DOUTCLR31_0_DIO25 0x02000000 +#define GPIO_DOUTCLR31_0_DIO25_BITN 25 +#define GPIO_DOUTCLR31_0_DIO25_M 0x02000000 +#define GPIO_DOUTCLR31_0_DIO25_S 25 // Field: [24] DIO24 // // Clears bit 24 -#define GPIO_DOUTCLR31_0_DIO24 0x01000000 -#define GPIO_DOUTCLR31_0_DIO24_BITN 24 -#define GPIO_DOUTCLR31_0_DIO24_M 0x01000000 -#define GPIO_DOUTCLR31_0_DIO24_S 24 +#define GPIO_DOUTCLR31_0_DIO24 0x01000000 +#define GPIO_DOUTCLR31_0_DIO24_BITN 24 +#define GPIO_DOUTCLR31_0_DIO24_M 0x01000000 +#define GPIO_DOUTCLR31_0_DIO24_S 24 // Field: [23] DIO23 // // Clears bit 23 -#define GPIO_DOUTCLR31_0_DIO23 0x00800000 -#define GPIO_DOUTCLR31_0_DIO23_BITN 23 -#define GPIO_DOUTCLR31_0_DIO23_M 0x00800000 -#define GPIO_DOUTCLR31_0_DIO23_S 23 +#define GPIO_DOUTCLR31_0_DIO23 0x00800000 +#define GPIO_DOUTCLR31_0_DIO23_BITN 23 +#define GPIO_DOUTCLR31_0_DIO23_M 0x00800000 +#define GPIO_DOUTCLR31_0_DIO23_S 23 // Field: [22] DIO22 // // Clears bit 22 -#define GPIO_DOUTCLR31_0_DIO22 0x00400000 -#define GPIO_DOUTCLR31_0_DIO22_BITN 22 -#define GPIO_DOUTCLR31_0_DIO22_M 0x00400000 -#define GPIO_DOUTCLR31_0_DIO22_S 22 +#define GPIO_DOUTCLR31_0_DIO22 0x00400000 +#define GPIO_DOUTCLR31_0_DIO22_BITN 22 +#define GPIO_DOUTCLR31_0_DIO22_M 0x00400000 +#define GPIO_DOUTCLR31_0_DIO22_S 22 // Field: [21] DIO21 // // Clears bit 21 -#define GPIO_DOUTCLR31_0_DIO21 0x00200000 -#define GPIO_DOUTCLR31_0_DIO21_BITN 21 -#define GPIO_DOUTCLR31_0_DIO21_M 0x00200000 -#define GPIO_DOUTCLR31_0_DIO21_S 21 +#define GPIO_DOUTCLR31_0_DIO21 0x00200000 +#define GPIO_DOUTCLR31_0_DIO21_BITN 21 +#define GPIO_DOUTCLR31_0_DIO21_M 0x00200000 +#define GPIO_DOUTCLR31_0_DIO21_S 21 // Field: [20] DIO20 // // Clears bit 20 -#define GPIO_DOUTCLR31_0_DIO20 0x00100000 -#define GPIO_DOUTCLR31_0_DIO20_BITN 20 -#define GPIO_DOUTCLR31_0_DIO20_M 0x00100000 -#define GPIO_DOUTCLR31_0_DIO20_S 20 +#define GPIO_DOUTCLR31_0_DIO20 0x00100000 +#define GPIO_DOUTCLR31_0_DIO20_BITN 20 +#define GPIO_DOUTCLR31_0_DIO20_M 0x00100000 +#define GPIO_DOUTCLR31_0_DIO20_S 20 // Field: [19] DIO19 // // Clears bit 19 -#define GPIO_DOUTCLR31_0_DIO19 0x00080000 -#define GPIO_DOUTCLR31_0_DIO19_BITN 19 -#define GPIO_DOUTCLR31_0_DIO19_M 0x00080000 -#define GPIO_DOUTCLR31_0_DIO19_S 19 +#define GPIO_DOUTCLR31_0_DIO19 0x00080000 +#define GPIO_DOUTCLR31_0_DIO19_BITN 19 +#define GPIO_DOUTCLR31_0_DIO19_M 0x00080000 +#define GPIO_DOUTCLR31_0_DIO19_S 19 // Field: [18] DIO18 // // Clears bit 18 -#define GPIO_DOUTCLR31_0_DIO18 0x00040000 -#define GPIO_DOUTCLR31_0_DIO18_BITN 18 -#define GPIO_DOUTCLR31_0_DIO18_M 0x00040000 -#define GPIO_DOUTCLR31_0_DIO18_S 18 +#define GPIO_DOUTCLR31_0_DIO18 0x00040000 +#define GPIO_DOUTCLR31_0_DIO18_BITN 18 +#define GPIO_DOUTCLR31_0_DIO18_M 0x00040000 +#define GPIO_DOUTCLR31_0_DIO18_S 18 // Field: [17] DIO17 // // Clears bit 17 -#define GPIO_DOUTCLR31_0_DIO17 0x00020000 -#define GPIO_DOUTCLR31_0_DIO17_BITN 17 -#define GPIO_DOUTCLR31_0_DIO17_M 0x00020000 -#define GPIO_DOUTCLR31_0_DIO17_S 17 +#define GPIO_DOUTCLR31_0_DIO17 0x00020000 +#define GPIO_DOUTCLR31_0_DIO17_BITN 17 +#define GPIO_DOUTCLR31_0_DIO17_M 0x00020000 +#define GPIO_DOUTCLR31_0_DIO17_S 17 // Field: [16] DIO16 // // Clears bit 16 -#define GPIO_DOUTCLR31_0_DIO16 0x00010000 -#define GPIO_DOUTCLR31_0_DIO16_BITN 16 -#define GPIO_DOUTCLR31_0_DIO16_M 0x00010000 -#define GPIO_DOUTCLR31_0_DIO16_S 16 +#define GPIO_DOUTCLR31_0_DIO16 0x00010000 +#define GPIO_DOUTCLR31_0_DIO16_BITN 16 +#define GPIO_DOUTCLR31_0_DIO16_M 0x00010000 +#define GPIO_DOUTCLR31_0_DIO16_S 16 // Field: [15] DIO15 // // Clears bit 15 -#define GPIO_DOUTCLR31_0_DIO15 0x00008000 -#define GPIO_DOUTCLR31_0_DIO15_BITN 15 -#define GPIO_DOUTCLR31_0_DIO15_M 0x00008000 -#define GPIO_DOUTCLR31_0_DIO15_S 15 +#define GPIO_DOUTCLR31_0_DIO15 0x00008000 +#define GPIO_DOUTCLR31_0_DIO15_BITN 15 +#define GPIO_DOUTCLR31_0_DIO15_M 0x00008000 +#define GPIO_DOUTCLR31_0_DIO15_S 15 // Field: [14] DIO14 // // Clears bit 14 -#define GPIO_DOUTCLR31_0_DIO14 0x00004000 -#define GPIO_DOUTCLR31_0_DIO14_BITN 14 -#define GPIO_DOUTCLR31_0_DIO14_M 0x00004000 -#define GPIO_DOUTCLR31_0_DIO14_S 14 +#define GPIO_DOUTCLR31_0_DIO14 0x00004000 +#define GPIO_DOUTCLR31_0_DIO14_BITN 14 +#define GPIO_DOUTCLR31_0_DIO14_M 0x00004000 +#define GPIO_DOUTCLR31_0_DIO14_S 14 // Field: [13] DIO13 // // Clears bit 13 -#define GPIO_DOUTCLR31_0_DIO13 0x00002000 -#define GPIO_DOUTCLR31_0_DIO13_BITN 13 -#define GPIO_DOUTCLR31_0_DIO13_M 0x00002000 -#define GPIO_DOUTCLR31_0_DIO13_S 13 +#define GPIO_DOUTCLR31_0_DIO13 0x00002000 +#define GPIO_DOUTCLR31_0_DIO13_BITN 13 +#define GPIO_DOUTCLR31_0_DIO13_M 0x00002000 +#define GPIO_DOUTCLR31_0_DIO13_S 13 // Field: [12] DIO12 // // Clears bit 12 -#define GPIO_DOUTCLR31_0_DIO12 0x00001000 -#define GPIO_DOUTCLR31_0_DIO12_BITN 12 -#define GPIO_DOUTCLR31_0_DIO12_M 0x00001000 -#define GPIO_DOUTCLR31_0_DIO12_S 12 +#define GPIO_DOUTCLR31_0_DIO12 0x00001000 +#define GPIO_DOUTCLR31_0_DIO12_BITN 12 +#define GPIO_DOUTCLR31_0_DIO12_M 0x00001000 +#define GPIO_DOUTCLR31_0_DIO12_S 12 // Field: [11] DIO11 // // Clears bit 11 -#define GPIO_DOUTCLR31_0_DIO11 0x00000800 -#define GPIO_DOUTCLR31_0_DIO11_BITN 11 -#define GPIO_DOUTCLR31_0_DIO11_M 0x00000800 -#define GPIO_DOUTCLR31_0_DIO11_S 11 +#define GPIO_DOUTCLR31_0_DIO11 0x00000800 +#define GPIO_DOUTCLR31_0_DIO11_BITN 11 +#define GPIO_DOUTCLR31_0_DIO11_M 0x00000800 +#define GPIO_DOUTCLR31_0_DIO11_S 11 // Field: [10] DIO10 // // Clears bit 10 -#define GPIO_DOUTCLR31_0_DIO10 0x00000400 -#define GPIO_DOUTCLR31_0_DIO10_BITN 10 -#define GPIO_DOUTCLR31_0_DIO10_M 0x00000400 -#define GPIO_DOUTCLR31_0_DIO10_S 10 +#define GPIO_DOUTCLR31_0_DIO10 0x00000400 +#define GPIO_DOUTCLR31_0_DIO10_BITN 10 +#define GPIO_DOUTCLR31_0_DIO10_M 0x00000400 +#define GPIO_DOUTCLR31_0_DIO10_S 10 // Field: [9] DIO9 // // Clears bit 9 -#define GPIO_DOUTCLR31_0_DIO9 0x00000200 -#define GPIO_DOUTCLR31_0_DIO9_BITN 9 -#define GPIO_DOUTCLR31_0_DIO9_M 0x00000200 -#define GPIO_DOUTCLR31_0_DIO9_S 9 +#define GPIO_DOUTCLR31_0_DIO9 0x00000200 +#define GPIO_DOUTCLR31_0_DIO9_BITN 9 +#define GPIO_DOUTCLR31_0_DIO9_M 0x00000200 +#define GPIO_DOUTCLR31_0_DIO9_S 9 // Field: [8] DIO8 // // Clears bit 8 -#define GPIO_DOUTCLR31_0_DIO8 0x00000100 -#define GPIO_DOUTCLR31_0_DIO8_BITN 8 -#define GPIO_DOUTCLR31_0_DIO8_M 0x00000100 -#define GPIO_DOUTCLR31_0_DIO8_S 8 +#define GPIO_DOUTCLR31_0_DIO8 0x00000100 +#define GPIO_DOUTCLR31_0_DIO8_BITN 8 +#define GPIO_DOUTCLR31_0_DIO8_M 0x00000100 +#define GPIO_DOUTCLR31_0_DIO8_S 8 // Field: [7] DIO7 // // Clears bit 7 -#define GPIO_DOUTCLR31_0_DIO7 0x00000080 -#define GPIO_DOUTCLR31_0_DIO7_BITN 7 -#define GPIO_DOUTCLR31_0_DIO7_M 0x00000080 -#define GPIO_DOUTCLR31_0_DIO7_S 7 +#define GPIO_DOUTCLR31_0_DIO7 0x00000080 +#define GPIO_DOUTCLR31_0_DIO7_BITN 7 +#define GPIO_DOUTCLR31_0_DIO7_M 0x00000080 +#define GPIO_DOUTCLR31_0_DIO7_S 7 // Field: [6] DIO6 // // Clears bit 6 -#define GPIO_DOUTCLR31_0_DIO6 0x00000040 -#define GPIO_DOUTCLR31_0_DIO6_BITN 6 -#define GPIO_DOUTCLR31_0_DIO6_M 0x00000040 -#define GPIO_DOUTCLR31_0_DIO6_S 6 +#define GPIO_DOUTCLR31_0_DIO6 0x00000040 +#define GPIO_DOUTCLR31_0_DIO6_BITN 6 +#define GPIO_DOUTCLR31_0_DIO6_M 0x00000040 +#define GPIO_DOUTCLR31_0_DIO6_S 6 // Field: [5] DIO5 // // Clears bit 5 -#define GPIO_DOUTCLR31_0_DIO5 0x00000020 -#define GPIO_DOUTCLR31_0_DIO5_BITN 5 -#define GPIO_DOUTCLR31_0_DIO5_M 0x00000020 -#define GPIO_DOUTCLR31_0_DIO5_S 5 +#define GPIO_DOUTCLR31_0_DIO5 0x00000020 +#define GPIO_DOUTCLR31_0_DIO5_BITN 5 +#define GPIO_DOUTCLR31_0_DIO5_M 0x00000020 +#define GPIO_DOUTCLR31_0_DIO5_S 5 // Field: [4] DIO4 // // Clears bit 4 -#define GPIO_DOUTCLR31_0_DIO4 0x00000010 -#define GPIO_DOUTCLR31_0_DIO4_BITN 4 -#define GPIO_DOUTCLR31_0_DIO4_M 0x00000010 -#define GPIO_DOUTCLR31_0_DIO4_S 4 +#define GPIO_DOUTCLR31_0_DIO4 0x00000010 +#define GPIO_DOUTCLR31_0_DIO4_BITN 4 +#define GPIO_DOUTCLR31_0_DIO4_M 0x00000010 +#define GPIO_DOUTCLR31_0_DIO4_S 4 // Field: [3] DIO3 // // Clears bit 3 -#define GPIO_DOUTCLR31_0_DIO3 0x00000008 -#define GPIO_DOUTCLR31_0_DIO3_BITN 3 -#define GPIO_DOUTCLR31_0_DIO3_M 0x00000008 -#define GPIO_DOUTCLR31_0_DIO3_S 3 +#define GPIO_DOUTCLR31_0_DIO3 0x00000008 +#define GPIO_DOUTCLR31_0_DIO3_BITN 3 +#define GPIO_DOUTCLR31_0_DIO3_M 0x00000008 +#define GPIO_DOUTCLR31_0_DIO3_S 3 // Field: [2] DIO2 // // Clears bit 2 -#define GPIO_DOUTCLR31_0_DIO2 0x00000004 -#define GPIO_DOUTCLR31_0_DIO2_BITN 2 -#define GPIO_DOUTCLR31_0_DIO2_M 0x00000004 -#define GPIO_DOUTCLR31_0_DIO2_S 2 +#define GPIO_DOUTCLR31_0_DIO2 0x00000004 +#define GPIO_DOUTCLR31_0_DIO2_BITN 2 +#define GPIO_DOUTCLR31_0_DIO2_M 0x00000004 +#define GPIO_DOUTCLR31_0_DIO2_S 2 // Field: [1] DIO1 // // Clears bit 1 -#define GPIO_DOUTCLR31_0_DIO1 0x00000002 -#define GPIO_DOUTCLR31_0_DIO1_BITN 1 -#define GPIO_DOUTCLR31_0_DIO1_M 0x00000002 -#define GPIO_DOUTCLR31_0_DIO1_S 1 +#define GPIO_DOUTCLR31_0_DIO1 0x00000002 +#define GPIO_DOUTCLR31_0_DIO1_BITN 1 +#define GPIO_DOUTCLR31_0_DIO1_M 0x00000002 +#define GPIO_DOUTCLR31_0_DIO1_S 1 // Field: [0] DIO0 // // Clears bit 0 -#define GPIO_DOUTCLR31_0_DIO0 0x00000001 -#define GPIO_DOUTCLR31_0_DIO0_BITN 0 -#define GPIO_DOUTCLR31_0_DIO0_M 0x00000001 -#define GPIO_DOUTCLR31_0_DIO0_S 0 +#define GPIO_DOUTCLR31_0_DIO0 0x00000001 +#define GPIO_DOUTCLR31_0_DIO0_BITN 0 +#define GPIO_DOUTCLR31_0_DIO0_M 0x00000001 +#define GPIO_DOUTCLR31_0_DIO0_S 0 //***************************************************************************** // @@ -1207,258 +1207,258 @@ // Field: [31] DIO31 // // Toggles bit 31 -#define GPIO_DOUTTGL31_0_DIO31 0x80000000 -#define GPIO_DOUTTGL31_0_DIO31_BITN 31 -#define GPIO_DOUTTGL31_0_DIO31_M 0x80000000 -#define GPIO_DOUTTGL31_0_DIO31_S 31 +#define GPIO_DOUTTGL31_0_DIO31 0x80000000 +#define GPIO_DOUTTGL31_0_DIO31_BITN 31 +#define GPIO_DOUTTGL31_0_DIO31_M 0x80000000 +#define GPIO_DOUTTGL31_0_DIO31_S 31 // Field: [30] DIO30 // // Toggles bit 30 -#define GPIO_DOUTTGL31_0_DIO30 0x40000000 -#define GPIO_DOUTTGL31_0_DIO30_BITN 30 -#define GPIO_DOUTTGL31_0_DIO30_M 0x40000000 -#define GPIO_DOUTTGL31_0_DIO30_S 30 +#define GPIO_DOUTTGL31_0_DIO30 0x40000000 +#define GPIO_DOUTTGL31_0_DIO30_BITN 30 +#define GPIO_DOUTTGL31_0_DIO30_M 0x40000000 +#define GPIO_DOUTTGL31_0_DIO30_S 30 // Field: [29] DIO29 // // Toggles bit 29 -#define GPIO_DOUTTGL31_0_DIO29 0x20000000 -#define GPIO_DOUTTGL31_0_DIO29_BITN 29 -#define GPIO_DOUTTGL31_0_DIO29_M 0x20000000 -#define GPIO_DOUTTGL31_0_DIO29_S 29 +#define GPIO_DOUTTGL31_0_DIO29 0x20000000 +#define GPIO_DOUTTGL31_0_DIO29_BITN 29 +#define GPIO_DOUTTGL31_0_DIO29_M 0x20000000 +#define GPIO_DOUTTGL31_0_DIO29_S 29 // Field: [28] DIO28 // // Toggles bit 28 -#define GPIO_DOUTTGL31_0_DIO28 0x10000000 -#define GPIO_DOUTTGL31_0_DIO28_BITN 28 -#define GPIO_DOUTTGL31_0_DIO28_M 0x10000000 -#define GPIO_DOUTTGL31_0_DIO28_S 28 +#define GPIO_DOUTTGL31_0_DIO28 0x10000000 +#define GPIO_DOUTTGL31_0_DIO28_BITN 28 +#define GPIO_DOUTTGL31_0_DIO28_M 0x10000000 +#define GPIO_DOUTTGL31_0_DIO28_S 28 // Field: [27] DIO27 // // Toggles bit 27 -#define GPIO_DOUTTGL31_0_DIO27 0x08000000 -#define GPIO_DOUTTGL31_0_DIO27_BITN 27 -#define GPIO_DOUTTGL31_0_DIO27_M 0x08000000 -#define GPIO_DOUTTGL31_0_DIO27_S 27 +#define GPIO_DOUTTGL31_0_DIO27 0x08000000 +#define GPIO_DOUTTGL31_0_DIO27_BITN 27 +#define GPIO_DOUTTGL31_0_DIO27_M 0x08000000 +#define GPIO_DOUTTGL31_0_DIO27_S 27 // Field: [26] DIO26 // // Toggles bit 26 -#define GPIO_DOUTTGL31_0_DIO26 0x04000000 -#define GPIO_DOUTTGL31_0_DIO26_BITN 26 -#define GPIO_DOUTTGL31_0_DIO26_M 0x04000000 -#define GPIO_DOUTTGL31_0_DIO26_S 26 +#define GPIO_DOUTTGL31_0_DIO26 0x04000000 +#define GPIO_DOUTTGL31_0_DIO26_BITN 26 +#define GPIO_DOUTTGL31_0_DIO26_M 0x04000000 +#define GPIO_DOUTTGL31_0_DIO26_S 26 // Field: [25] DIO25 // // Toggles bit 25 -#define GPIO_DOUTTGL31_0_DIO25 0x02000000 -#define GPIO_DOUTTGL31_0_DIO25_BITN 25 -#define GPIO_DOUTTGL31_0_DIO25_M 0x02000000 -#define GPIO_DOUTTGL31_0_DIO25_S 25 +#define GPIO_DOUTTGL31_0_DIO25 0x02000000 +#define GPIO_DOUTTGL31_0_DIO25_BITN 25 +#define GPIO_DOUTTGL31_0_DIO25_M 0x02000000 +#define GPIO_DOUTTGL31_0_DIO25_S 25 // Field: [24] DIO24 // // Toggles bit 24 -#define GPIO_DOUTTGL31_0_DIO24 0x01000000 -#define GPIO_DOUTTGL31_0_DIO24_BITN 24 -#define GPIO_DOUTTGL31_0_DIO24_M 0x01000000 -#define GPIO_DOUTTGL31_0_DIO24_S 24 +#define GPIO_DOUTTGL31_0_DIO24 0x01000000 +#define GPIO_DOUTTGL31_0_DIO24_BITN 24 +#define GPIO_DOUTTGL31_0_DIO24_M 0x01000000 +#define GPIO_DOUTTGL31_0_DIO24_S 24 // Field: [23] DIO23 // // Toggles bit 23 -#define GPIO_DOUTTGL31_0_DIO23 0x00800000 -#define GPIO_DOUTTGL31_0_DIO23_BITN 23 -#define GPIO_DOUTTGL31_0_DIO23_M 0x00800000 -#define GPIO_DOUTTGL31_0_DIO23_S 23 +#define GPIO_DOUTTGL31_0_DIO23 0x00800000 +#define GPIO_DOUTTGL31_0_DIO23_BITN 23 +#define GPIO_DOUTTGL31_0_DIO23_M 0x00800000 +#define GPIO_DOUTTGL31_0_DIO23_S 23 // Field: [22] DIO22 // // Toggles bit 22 -#define GPIO_DOUTTGL31_0_DIO22 0x00400000 -#define GPIO_DOUTTGL31_0_DIO22_BITN 22 -#define GPIO_DOUTTGL31_0_DIO22_M 0x00400000 -#define GPIO_DOUTTGL31_0_DIO22_S 22 +#define GPIO_DOUTTGL31_0_DIO22 0x00400000 +#define GPIO_DOUTTGL31_0_DIO22_BITN 22 +#define GPIO_DOUTTGL31_0_DIO22_M 0x00400000 +#define GPIO_DOUTTGL31_0_DIO22_S 22 // Field: [21] DIO21 // // Toggles bit 21 -#define GPIO_DOUTTGL31_0_DIO21 0x00200000 -#define GPIO_DOUTTGL31_0_DIO21_BITN 21 -#define GPIO_DOUTTGL31_0_DIO21_M 0x00200000 -#define GPIO_DOUTTGL31_0_DIO21_S 21 +#define GPIO_DOUTTGL31_0_DIO21 0x00200000 +#define GPIO_DOUTTGL31_0_DIO21_BITN 21 +#define GPIO_DOUTTGL31_0_DIO21_M 0x00200000 +#define GPIO_DOUTTGL31_0_DIO21_S 21 // Field: [20] DIO20 // // Toggles bit 20 -#define GPIO_DOUTTGL31_0_DIO20 0x00100000 -#define GPIO_DOUTTGL31_0_DIO20_BITN 20 -#define GPIO_DOUTTGL31_0_DIO20_M 0x00100000 -#define GPIO_DOUTTGL31_0_DIO20_S 20 +#define GPIO_DOUTTGL31_0_DIO20 0x00100000 +#define GPIO_DOUTTGL31_0_DIO20_BITN 20 +#define GPIO_DOUTTGL31_0_DIO20_M 0x00100000 +#define GPIO_DOUTTGL31_0_DIO20_S 20 // Field: [19] DIO19 // // Toggles bit 19 -#define GPIO_DOUTTGL31_0_DIO19 0x00080000 -#define GPIO_DOUTTGL31_0_DIO19_BITN 19 -#define GPIO_DOUTTGL31_0_DIO19_M 0x00080000 -#define GPIO_DOUTTGL31_0_DIO19_S 19 +#define GPIO_DOUTTGL31_0_DIO19 0x00080000 +#define GPIO_DOUTTGL31_0_DIO19_BITN 19 +#define GPIO_DOUTTGL31_0_DIO19_M 0x00080000 +#define GPIO_DOUTTGL31_0_DIO19_S 19 // Field: [18] DIO18 // // Toggles bit 18 -#define GPIO_DOUTTGL31_0_DIO18 0x00040000 -#define GPIO_DOUTTGL31_0_DIO18_BITN 18 -#define GPIO_DOUTTGL31_0_DIO18_M 0x00040000 -#define GPIO_DOUTTGL31_0_DIO18_S 18 +#define GPIO_DOUTTGL31_0_DIO18 0x00040000 +#define GPIO_DOUTTGL31_0_DIO18_BITN 18 +#define GPIO_DOUTTGL31_0_DIO18_M 0x00040000 +#define GPIO_DOUTTGL31_0_DIO18_S 18 // Field: [17] DIO17 // // Toggles bit 17 -#define GPIO_DOUTTGL31_0_DIO17 0x00020000 -#define GPIO_DOUTTGL31_0_DIO17_BITN 17 -#define GPIO_DOUTTGL31_0_DIO17_M 0x00020000 -#define GPIO_DOUTTGL31_0_DIO17_S 17 +#define GPIO_DOUTTGL31_0_DIO17 0x00020000 +#define GPIO_DOUTTGL31_0_DIO17_BITN 17 +#define GPIO_DOUTTGL31_0_DIO17_M 0x00020000 +#define GPIO_DOUTTGL31_0_DIO17_S 17 // Field: [16] DIO16 // // Toggles bit 16 -#define GPIO_DOUTTGL31_0_DIO16 0x00010000 -#define GPIO_DOUTTGL31_0_DIO16_BITN 16 -#define GPIO_DOUTTGL31_0_DIO16_M 0x00010000 -#define GPIO_DOUTTGL31_0_DIO16_S 16 +#define GPIO_DOUTTGL31_0_DIO16 0x00010000 +#define GPIO_DOUTTGL31_0_DIO16_BITN 16 +#define GPIO_DOUTTGL31_0_DIO16_M 0x00010000 +#define GPIO_DOUTTGL31_0_DIO16_S 16 // Field: [15] DIO15 // // Toggles bit 15 -#define GPIO_DOUTTGL31_0_DIO15 0x00008000 -#define GPIO_DOUTTGL31_0_DIO15_BITN 15 -#define GPIO_DOUTTGL31_0_DIO15_M 0x00008000 -#define GPIO_DOUTTGL31_0_DIO15_S 15 +#define GPIO_DOUTTGL31_0_DIO15 0x00008000 +#define GPIO_DOUTTGL31_0_DIO15_BITN 15 +#define GPIO_DOUTTGL31_0_DIO15_M 0x00008000 +#define GPIO_DOUTTGL31_0_DIO15_S 15 // Field: [14] DIO14 // // Toggles bit 14 -#define GPIO_DOUTTGL31_0_DIO14 0x00004000 -#define GPIO_DOUTTGL31_0_DIO14_BITN 14 -#define GPIO_DOUTTGL31_0_DIO14_M 0x00004000 -#define GPIO_DOUTTGL31_0_DIO14_S 14 +#define GPIO_DOUTTGL31_0_DIO14 0x00004000 +#define GPIO_DOUTTGL31_0_DIO14_BITN 14 +#define GPIO_DOUTTGL31_0_DIO14_M 0x00004000 +#define GPIO_DOUTTGL31_0_DIO14_S 14 // Field: [13] DIO13 // // Toggles bit 13 -#define GPIO_DOUTTGL31_0_DIO13 0x00002000 -#define GPIO_DOUTTGL31_0_DIO13_BITN 13 -#define GPIO_DOUTTGL31_0_DIO13_M 0x00002000 -#define GPIO_DOUTTGL31_0_DIO13_S 13 +#define GPIO_DOUTTGL31_0_DIO13 0x00002000 +#define GPIO_DOUTTGL31_0_DIO13_BITN 13 +#define GPIO_DOUTTGL31_0_DIO13_M 0x00002000 +#define GPIO_DOUTTGL31_0_DIO13_S 13 // Field: [12] DIO12 // // Toggles bit 12 -#define GPIO_DOUTTGL31_0_DIO12 0x00001000 -#define GPIO_DOUTTGL31_0_DIO12_BITN 12 -#define GPIO_DOUTTGL31_0_DIO12_M 0x00001000 -#define GPIO_DOUTTGL31_0_DIO12_S 12 +#define GPIO_DOUTTGL31_0_DIO12 0x00001000 +#define GPIO_DOUTTGL31_0_DIO12_BITN 12 +#define GPIO_DOUTTGL31_0_DIO12_M 0x00001000 +#define GPIO_DOUTTGL31_0_DIO12_S 12 // Field: [11] DIO11 // // Toggles bit 11 -#define GPIO_DOUTTGL31_0_DIO11 0x00000800 -#define GPIO_DOUTTGL31_0_DIO11_BITN 11 -#define GPIO_DOUTTGL31_0_DIO11_M 0x00000800 -#define GPIO_DOUTTGL31_0_DIO11_S 11 +#define GPIO_DOUTTGL31_0_DIO11 0x00000800 +#define GPIO_DOUTTGL31_0_DIO11_BITN 11 +#define GPIO_DOUTTGL31_0_DIO11_M 0x00000800 +#define GPIO_DOUTTGL31_0_DIO11_S 11 // Field: [10] DIO10 // // Toggles bit 10 -#define GPIO_DOUTTGL31_0_DIO10 0x00000400 -#define GPIO_DOUTTGL31_0_DIO10_BITN 10 -#define GPIO_DOUTTGL31_0_DIO10_M 0x00000400 -#define GPIO_DOUTTGL31_0_DIO10_S 10 +#define GPIO_DOUTTGL31_0_DIO10 0x00000400 +#define GPIO_DOUTTGL31_0_DIO10_BITN 10 +#define GPIO_DOUTTGL31_0_DIO10_M 0x00000400 +#define GPIO_DOUTTGL31_0_DIO10_S 10 // Field: [9] DIO9 // // Toggles bit 9 -#define GPIO_DOUTTGL31_0_DIO9 0x00000200 -#define GPIO_DOUTTGL31_0_DIO9_BITN 9 -#define GPIO_DOUTTGL31_0_DIO9_M 0x00000200 -#define GPIO_DOUTTGL31_0_DIO9_S 9 +#define GPIO_DOUTTGL31_0_DIO9 0x00000200 +#define GPIO_DOUTTGL31_0_DIO9_BITN 9 +#define GPIO_DOUTTGL31_0_DIO9_M 0x00000200 +#define GPIO_DOUTTGL31_0_DIO9_S 9 // Field: [8] DIO8 // // Toggles bit 8 -#define GPIO_DOUTTGL31_0_DIO8 0x00000100 -#define GPIO_DOUTTGL31_0_DIO8_BITN 8 -#define GPIO_DOUTTGL31_0_DIO8_M 0x00000100 -#define GPIO_DOUTTGL31_0_DIO8_S 8 +#define GPIO_DOUTTGL31_0_DIO8 0x00000100 +#define GPIO_DOUTTGL31_0_DIO8_BITN 8 +#define GPIO_DOUTTGL31_0_DIO8_M 0x00000100 +#define GPIO_DOUTTGL31_0_DIO8_S 8 // Field: [7] DIO7 // // Toggles bit 7 -#define GPIO_DOUTTGL31_0_DIO7 0x00000080 -#define GPIO_DOUTTGL31_0_DIO7_BITN 7 -#define GPIO_DOUTTGL31_0_DIO7_M 0x00000080 -#define GPIO_DOUTTGL31_0_DIO7_S 7 +#define GPIO_DOUTTGL31_0_DIO7 0x00000080 +#define GPIO_DOUTTGL31_0_DIO7_BITN 7 +#define GPIO_DOUTTGL31_0_DIO7_M 0x00000080 +#define GPIO_DOUTTGL31_0_DIO7_S 7 // Field: [6] DIO6 // // Toggles bit 6 -#define GPIO_DOUTTGL31_0_DIO6 0x00000040 -#define GPIO_DOUTTGL31_0_DIO6_BITN 6 -#define GPIO_DOUTTGL31_0_DIO6_M 0x00000040 -#define GPIO_DOUTTGL31_0_DIO6_S 6 +#define GPIO_DOUTTGL31_0_DIO6 0x00000040 +#define GPIO_DOUTTGL31_0_DIO6_BITN 6 +#define GPIO_DOUTTGL31_0_DIO6_M 0x00000040 +#define GPIO_DOUTTGL31_0_DIO6_S 6 // Field: [5] DIO5 // // Toggles bit 5 -#define GPIO_DOUTTGL31_0_DIO5 0x00000020 -#define GPIO_DOUTTGL31_0_DIO5_BITN 5 -#define GPIO_DOUTTGL31_0_DIO5_M 0x00000020 -#define GPIO_DOUTTGL31_0_DIO5_S 5 +#define GPIO_DOUTTGL31_0_DIO5 0x00000020 +#define GPIO_DOUTTGL31_0_DIO5_BITN 5 +#define GPIO_DOUTTGL31_0_DIO5_M 0x00000020 +#define GPIO_DOUTTGL31_0_DIO5_S 5 // Field: [4] DIO4 // // Toggles bit 4 -#define GPIO_DOUTTGL31_0_DIO4 0x00000010 -#define GPIO_DOUTTGL31_0_DIO4_BITN 4 -#define GPIO_DOUTTGL31_0_DIO4_M 0x00000010 -#define GPIO_DOUTTGL31_0_DIO4_S 4 +#define GPIO_DOUTTGL31_0_DIO4 0x00000010 +#define GPIO_DOUTTGL31_0_DIO4_BITN 4 +#define GPIO_DOUTTGL31_0_DIO4_M 0x00000010 +#define GPIO_DOUTTGL31_0_DIO4_S 4 // Field: [3] DIO3 // // Toggles bit 3 -#define GPIO_DOUTTGL31_0_DIO3 0x00000008 -#define GPIO_DOUTTGL31_0_DIO3_BITN 3 -#define GPIO_DOUTTGL31_0_DIO3_M 0x00000008 -#define GPIO_DOUTTGL31_0_DIO3_S 3 +#define GPIO_DOUTTGL31_0_DIO3 0x00000008 +#define GPIO_DOUTTGL31_0_DIO3_BITN 3 +#define GPIO_DOUTTGL31_0_DIO3_M 0x00000008 +#define GPIO_DOUTTGL31_0_DIO3_S 3 // Field: [2] DIO2 // // Toggles bit 2 -#define GPIO_DOUTTGL31_0_DIO2 0x00000004 -#define GPIO_DOUTTGL31_0_DIO2_BITN 2 -#define GPIO_DOUTTGL31_0_DIO2_M 0x00000004 -#define GPIO_DOUTTGL31_0_DIO2_S 2 +#define GPIO_DOUTTGL31_0_DIO2 0x00000004 +#define GPIO_DOUTTGL31_0_DIO2_BITN 2 +#define GPIO_DOUTTGL31_0_DIO2_M 0x00000004 +#define GPIO_DOUTTGL31_0_DIO2_S 2 // Field: [1] DIO1 // // Toggles bit 1 -#define GPIO_DOUTTGL31_0_DIO1 0x00000002 -#define GPIO_DOUTTGL31_0_DIO1_BITN 1 -#define GPIO_DOUTTGL31_0_DIO1_M 0x00000002 -#define GPIO_DOUTTGL31_0_DIO1_S 1 +#define GPIO_DOUTTGL31_0_DIO1 0x00000002 +#define GPIO_DOUTTGL31_0_DIO1_BITN 1 +#define GPIO_DOUTTGL31_0_DIO1_M 0x00000002 +#define GPIO_DOUTTGL31_0_DIO1_S 1 // Field: [0] DIO0 // // Toggles bit 0 -#define GPIO_DOUTTGL31_0_DIO0 0x00000001 -#define GPIO_DOUTTGL31_0_DIO0_BITN 0 -#define GPIO_DOUTTGL31_0_DIO0_M 0x00000001 -#define GPIO_DOUTTGL31_0_DIO0_S 0 +#define GPIO_DOUTTGL31_0_DIO0 0x00000001 +#define GPIO_DOUTTGL31_0_DIO0_BITN 0 +#define GPIO_DOUTTGL31_0_DIO0_M 0x00000001 +#define GPIO_DOUTTGL31_0_DIO0_S 0 //***************************************************************************** // @@ -1468,258 +1468,258 @@ // Field: [31] DIO31 // // Data input from DIO 31 -#define GPIO_DIN31_0_DIO31 0x80000000 -#define GPIO_DIN31_0_DIO31_BITN 31 -#define GPIO_DIN31_0_DIO31_M 0x80000000 -#define GPIO_DIN31_0_DIO31_S 31 +#define GPIO_DIN31_0_DIO31 0x80000000 +#define GPIO_DIN31_0_DIO31_BITN 31 +#define GPIO_DIN31_0_DIO31_M 0x80000000 +#define GPIO_DIN31_0_DIO31_S 31 // Field: [30] DIO30 // // Data input from DIO 30 -#define GPIO_DIN31_0_DIO30 0x40000000 -#define GPIO_DIN31_0_DIO30_BITN 30 -#define GPIO_DIN31_0_DIO30_M 0x40000000 -#define GPIO_DIN31_0_DIO30_S 30 +#define GPIO_DIN31_0_DIO30 0x40000000 +#define GPIO_DIN31_0_DIO30_BITN 30 +#define GPIO_DIN31_0_DIO30_M 0x40000000 +#define GPIO_DIN31_0_DIO30_S 30 // Field: [29] DIO29 // // Data input from DIO 29 -#define GPIO_DIN31_0_DIO29 0x20000000 -#define GPIO_DIN31_0_DIO29_BITN 29 -#define GPIO_DIN31_0_DIO29_M 0x20000000 -#define GPIO_DIN31_0_DIO29_S 29 +#define GPIO_DIN31_0_DIO29 0x20000000 +#define GPIO_DIN31_0_DIO29_BITN 29 +#define GPIO_DIN31_0_DIO29_M 0x20000000 +#define GPIO_DIN31_0_DIO29_S 29 // Field: [28] DIO28 // // Data input from DIO 28 -#define GPIO_DIN31_0_DIO28 0x10000000 -#define GPIO_DIN31_0_DIO28_BITN 28 -#define GPIO_DIN31_0_DIO28_M 0x10000000 -#define GPIO_DIN31_0_DIO28_S 28 +#define GPIO_DIN31_0_DIO28 0x10000000 +#define GPIO_DIN31_0_DIO28_BITN 28 +#define GPIO_DIN31_0_DIO28_M 0x10000000 +#define GPIO_DIN31_0_DIO28_S 28 // Field: [27] DIO27 // // Data input from DIO 27 -#define GPIO_DIN31_0_DIO27 0x08000000 -#define GPIO_DIN31_0_DIO27_BITN 27 -#define GPIO_DIN31_0_DIO27_M 0x08000000 -#define GPIO_DIN31_0_DIO27_S 27 +#define GPIO_DIN31_0_DIO27 0x08000000 +#define GPIO_DIN31_0_DIO27_BITN 27 +#define GPIO_DIN31_0_DIO27_M 0x08000000 +#define GPIO_DIN31_0_DIO27_S 27 // Field: [26] DIO26 // // Data input from DIO 26 -#define GPIO_DIN31_0_DIO26 0x04000000 -#define GPIO_DIN31_0_DIO26_BITN 26 -#define GPIO_DIN31_0_DIO26_M 0x04000000 -#define GPIO_DIN31_0_DIO26_S 26 +#define GPIO_DIN31_0_DIO26 0x04000000 +#define GPIO_DIN31_0_DIO26_BITN 26 +#define GPIO_DIN31_0_DIO26_M 0x04000000 +#define GPIO_DIN31_0_DIO26_S 26 // Field: [25] DIO25 // // Data input from DIO 25 -#define GPIO_DIN31_0_DIO25 0x02000000 -#define GPIO_DIN31_0_DIO25_BITN 25 -#define GPIO_DIN31_0_DIO25_M 0x02000000 -#define GPIO_DIN31_0_DIO25_S 25 +#define GPIO_DIN31_0_DIO25 0x02000000 +#define GPIO_DIN31_0_DIO25_BITN 25 +#define GPIO_DIN31_0_DIO25_M 0x02000000 +#define GPIO_DIN31_0_DIO25_S 25 // Field: [24] DIO24 // // Data input from DIO 24 -#define GPIO_DIN31_0_DIO24 0x01000000 -#define GPIO_DIN31_0_DIO24_BITN 24 -#define GPIO_DIN31_0_DIO24_M 0x01000000 -#define GPIO_DIN31_0_DIO24_S 24 +#define GPIO_DIN31_0_DIO24 0x01000000 +#define GPIO_DIN31_0_DIO24_BITN 24 +#define GPIO_DIN31_0_DIO24_M 0x01000000 +#define GPIO_DIN31_0_DIO24_S 24 // Field: [23] DIO23 // // Data input from DIO 23 -#define GPIO_DIN31_0_DIO23 0x00800000 -#define GPIO_DIN31_0_DIO23_BITN 23 -#define GPIO_DIN31_0_DIO23_M 0x00800000 -#define GPIO_DIN31_0_DIO23_S 23 +#define GPIO_DIN31_0_DIO23 0x00800000 +#define GPIO_DIN31_0_DIO23_BITN 23 +#define GPIO_DIN31_0_DIO23_M 0x00800000 +#define GPIO_DIN31_0_DIO23_S 23 // Field: [22] DIO22 // // Data input from DIO 22 -#define GPIO_DIN31_0_DIO22 0x00400000 -#define GPIO_DIN31_0_DIO22_BITN 22 -#define GPIO_DIN31_0_DIO22_M 0x00400000 -#define GPIO_DIN31_0_DIO22_S 22 +#define GPIO_DIN31_0_DIO22 0x00400000 +#define GPIO_DIN31_0_DIO22_BITN 22 +#define GPIO_DIN31_0_DIO22_M 0x00400000 +#define GPIO_DIN31_0_DIO22_S 22 // Field: [21] DIO21 // // Data input from DIO 21 -#define GPIO_DIN31_0_DIO21 0x00200000 -#define GPIO_DIN31_0_DIO21_BITN 21 -#define GPIO_DIN31_0_DIO21_M 0x00200000 -#define GPIO_DIN31_0_DIO21_S 21 +#define GPIO_DIN31_0_DIO21 0x00200000 +#define GPIO_DIN31_0_DIO21_BITN 21 +#define GPIO_DIN31_0_DIO21_M 0x00200000 +#define GPIO_DIN31_0_DIO21_S 21 // Field: [20] DIO20 // // Data input from DIO 20 -#define GPIO_DIN31_0_DIO20 0x00100000 -#define GPIO_DIN31_0_DIO20_BITN 20 -#define GPIO_DIN31_0_DIO20_M 0x00100000 -#define GPIO_DIN31_0_DIO20_S 20 +#define GPIO_DIN31_0_DIO20 0x00100000 +#define GPIO_DIN31_0_DIO20_BITN 20 +#define GPIO_DIN31_0_DIO20_M 0x00100000 +#define GPIO_DIN31_0_DIO20_S 20 // Field: [19] DIO19 // // Data input from DIO 19 -#define GPIO_DIN31_0_DIO19 0x00080000 -#define GPIO_DIN31_0_DIO19_BITN 19 -#define GPIO_DIN31_0_DIO19_M 0x00080000 -#define GPIO_DIN31_0_DIO19_S 19 +#define GPIO_DIN31_0_DIO19 0x00080000 +#define GPIO_DIN31_0_DIO19_BITN 19 +#define GPIO_DIN31_0_DIO19_M 0x00080000 +#define GPIO_DIN31_0_DIO19_S 19 // Field: [18] DIO18 // // Data input from DIO 18 -#define GPIO_DIN31_0_DIO18 0x00040000 -#define GPIO_DIN31_0_DIO18_BITN 18 -#define GPIO_DIN31_0_DIO18_M 0x00040000 -#define GPIO_DIN31_0_DIO18_S 18 +#define GPIO_DIN31_0_DIO18 0x00040000 +#define GPIO_DIN31_0_DIO18_BITN 18 +#define GPIO_DIN31_0_DIO18_M 0x00040000 +#define GPIO_DIN31_0_DIO18_S 18 // Field: [17] DIO17 // // Data input from DIO 17 -#define GPIO_DIN31_0_DIO17 0x00020000 -#define GPIO_DIN31_0_DIO17_BITN 17 -#define GPIO_DIN31_0_DIO17_M 0x00020000 -#define GPIO_DIN31_0_DIO17_S 17 +#define GPIO_DIN31_0_DIO17 0x00020000 +#define GPIO_DIN31_0_DIO17_BITN 17 +#define GPIO_DIN31_0_DIO17_M 0x00020000 +#define GPIO_DIN31_0_DIO17_S 17 // Field: [16] DIO16 // // Data input from DIO 16 -#define GPIO_DIN31_0_DIO16 0x00010000 -#define GPIO_DIN31_0_DIO16_BITN 16 -#define GPIO_DIN31_0_DIO16_M 0x00010000 -#define GPIO_DIN31_0_DIO16_S 16 +#define GPIO_DIN31_0_DIO16 0x00010000 +#define GPIO_DIN31_0_DIO16_BITN 16 +#define GPIO_DIN31_0_DIO16_M 0x00010000 +#define GPIO_DIN31_0_DIO16_S 16 // Field: [15] DIO15 // // Data input from DIO 15 -#define GPIO_DIN31_0_DIO15 0x00008000 -#define GPIO_DIN31_0_DIO15_BITN 15 -#define GPIO_DIN31_0_DIO15_M 0x00008000 -#define GPIO_DIN31_0_DIO15_S 15 +#define GPIO_DIN31_0_DIO15 0x00008000 +#define GPIO_DIN31_0_DIO15_BITN 15 +#define GPIO_DIN31_0_DIO15_M 0x00008000 +#define GPIO_DIN31_0_DIO15_S 15 // Field: [14] DIO14 // // Data input from DIO 14 -#define GPIO_DIN31_0_DIO14 0x00004000 -#define GPIO_DIN31_0_DIO14_BITN 14 -#define GPIO_DIN31_0_DIO14_M 0x00004000 -#define GPIO_DIN31_0_DIO14_S 14 +#define GPIO_DIN31_0_DIO14 0x00004000 +#define GPIO_DIN31_0_DIO14_BITN 14 +#define GPIO_DIN31_0_DIO14_M 0x00004000 +#define GPIO_DIN31_0_DIO14_S 14 // Field: [13] DIO13 // // Data input from DIO 13 -#define GPIO_DIN31_0_DIO13 0x00002000 -#define GPIO_DIN31_0_DIO13_BITN 13 -#define GPIO_DIN31_0_DIO13_M 0x00002000 -#define GPIO_DIN31_0_DIO13_S 13 +#define GPIO_DIN31_0_DIO13 0x00002000 +#define GPIO_DIN31_0_DIO13_BITN 13 +#define GPIO_DIN31_0_DIO13_M 0x00002000 +#define GPIO_DIN31_0_DIO13_S 13 // Field: [12] DIO12 // // Data input from DIO 12 -#define GPIO_DIN31_0_DIO12 0x00001000 -#define GPIO_DIN31_0_DIO12_BITN 12 -#define GPIO_DIN31_0_DIO12_M 0x00001000 -#define GPIO_DIN31_0_DIO12_S 12 +#define GPIO_DIN31_0_DIO12 0x00001000 +#define GPIO_DIN31_0_DIO12_BITN 12 +#define GPIO_DIN31_0_DIO12_M 0x00001000 +#define GPIO_DIN31_0_DIO12_S 12 // Field: [11] DIO11 // // Data input from DIO 11 -#define GPIO_DIN31_0_DIO11 0x00000800 -#define GPIO_DIN31_0_DIO11_BITN 11 -#define GPIO_DIN31_0_DIO11_M 0x00000800 -#define GPIO_DIN31_0_DIO11_S 11 +#define GPIO_DIN31_0_DIO11 0x00000800 +#define GPIO_DIN31_0_DIO11_BITN 11 +#define GPIO_DIN31_0_DIO11_M 0x00000800 +#define GPIO_DIN31_0_DIO11_S 11 // Field: [10] DIO10 // // Data input from DIO 10 -#define GPIO_DIN31_0_DIO10 0x00000400 -#define GPIO_DIN31_0_DIO10_BITN 10 -#define GPIO_DIN31_0_DIO10_M 0x00000400 -#define GPIO_DIN31_0_DIO10_S 10 +#define GPIO_DIN31_0_DIO10 0x00000400 +#define GPIO_DIN31_0_DIO10_BITN 10 +#define GPIO_DIN31_0_DIO10_M 0x00000400 +#define GPIO_DIN31_0_DIO10_S 10 // Field: [9] DIO9 // // Data input from DIO 9 -#define GPIO_DIN31_0_DIO9 0x00000200 -#define GPIO_DIN31_0_DIO9_BITN 9 -#define GPIO_DIN31_0_DIO9_M 0x00000200 -#define GPIO_DIN31_0_DIO9_S 9 +#define GPIO_DIN31_0_DIO9 0x00000200 +#define GPIO_DIN31_0_DIO9_BITN 9 +#define GPIO_DIN31_0_DIO9_M 0x00000200 +#define GPIO_DIN31_0_DIO9_S 9 // Field: [8] DIO8 // // Data input from DIO 8 -#define GPIO_DIN31_0_DIO8 0x00000100 -#define GPIO_DIN31_0_DIO8_BITN 8 -#define GPIO_DIN31_0_DIO8_M 0x00000100 -#define GPIO_DIN31_0_DIO8_S 8 +#define GPIO_DIN31_0_DIO8 0x00000100 +#define GPIO_DIN31_0_DIO8_BITN 8 +#define GPIO_DIN31_0_DIO8_M 0x00000100 +#define GPIO_DIN31_0_DIO8_S 8 // Field: [7] DIO7 // // Data input from DIO 7 -#define GPIO_DIN31_0_DIO7 0x00000080 -#define GPIO_DIN31_0_DIO7_BITN 7 -#define GPIO_DIN31_0_DIO7_M 0x00000080 -#define GPIO_DIN31_0_DIO7_S 7 +#define GPIO_DIN31_0_DIO7 0x00000080 +#define GPIO_DIN31_0_DIO7_BITN 7 +#define GPIO_DIN31_0_DIO7_M 0x00000080 +#define GPIO_DIN31_0_DIO7_S 7 // Field: [6] DIO6 // // Data input from DIO 6 -#define GPIO_DIN31_0_DIO6 0x00000040 -#define GPIO_DIN31_0_DIO6_BITN 6 -#define GPIO_DIN31_0_DIO6_M 0x00000040 -#define GPIO_DIN31_0_DIO6_S 6 +#define GPIO_DIN31_0_DIO6 0x00000040 +#define GPIO_DIN31_0_DIO6_BITN 6 +#define GPIO_DIN31_0_DIO6_M 0x00000040 +#define GPIO_DIN31_0_DIO6_S 6 // Field: [5] DIO5 // // Data input from DIO 5 -#define GPIO_DIN31_0_DIO5 0x00000020 -#define GPIO_DIN31_0_DIO5_BITN 5 -#define GPIO_DIN31_0_DIO5_M 0x00000020 -#define GPIO_DIN31_0_DIO5_S 5 +#define GPIO_DIN31_0_DIO5 0x00000020 +#define GPIO_DIN31_0_DIO5_BITN 5 +#define GPIO_DIN31_0_DIO5_M 0x00000020 +#define GPIO_DIN31_0_DIO5_S 5 // Field: [4] DIO4 // // Data input from DIO 4 -#define GPIO_DIN31_0_DIO4 0x00000010 -#define GPIO_DIN31_0_DIO4_BITN 4 -#define GPIO_DIN31_0_DIO4_M 0x00000010 -#define GPIO_DIN31_0_DIO4_S 4 +#define GPIO_DIN31_0_DIO4 0x00000010 +#define GPIO_DIN31_0_DIO4_BITN 4 +#define GPIO_DIN31_0_DIO4_M 0x00000010 +#define GPIO_DIN31_0_DIO4_S 4 // Field: [3] DIO3 // // Data input from DIO 3 -#define GPIO_DIN31_0_DIO3 0x00000008 -#define GPIO_DIN31_0_DIO3_BITN 3 -#define GPIO_DIN31_0_DIO3_M 0x00000008 -#define GPIO_DIN31_0_DIO3_S 3 +#define GPIO_DIN31_0_DIO3 0x00000008 +#define GPIO_DIN31_0_DIO3_BITN 3 +#define GPIO_DIN31_0_DIO3_M 0x00000008 +#define GPIO_DIN31_0_DIO3_S 3 // Field: [2] DIO2 // // Data input from DIO 2 -#define GPIO_DIN31_0_DIO2 0x00000004 -#define GPIO_DIN31_0_DIO2_BITN 2 -#define GPIO_DIN31_0_DIO2_M 0x00000004 -#define GPIO_DIN31_0_DIO2_S 2 +#define GPIO_DIN31_0_DIO2 0x00000004 +#define GPIO_DIN31_0_DIO2_BITN 2 +#define GPIO_DIN31_0_DIO2_M 0x00000004 +#define GPIO_DIN31_0_DIO2_S 2 // Field: [1] DIO1 // // Data input from DIO 1 -#define GPIO_DIN31_0_DIO1 0x00000002 -#define GPIO_DIN31_0_DIO1_BITN 1 -#define GPIO_DIN31_0_DIO1_M 0x00000002 -#define GPIO_DIN31_0_DIO1_S 1 +#define GPIO_DIN31_0_DIO1 0x00000002 +#define GPIO_DIN31_0_DIO1_BITN 1 +#define GPIO_DIN31_0_DIO1_M 0x00000002 +#define GPIO_DIN31_0_DIO1_S 1 // Field: [0] DIO0 // // Data input from DIO 0 -#define GPIO_DIN31_0_DIO0 0x00000001 -#define GPIO_DIN31_0_DIO0_BITN 0 -#define GPIO_DIN31_0_DIO0_M 0x00000001 -#define GPIO_DIN31_0_DIO0_S 0 +#define GPIO_DIN31_0_DIO0 0x00000001 +#define GPIO_DIN31_0_DIO0_BITN 0 +#define GPIO_DIN31_0_DIO0_M 0x00000001 +#define GPIO_DIN31_0_DIO0_S 0 //***************************************************************************** // @@ -1729,258 +1729,258 @@ // Field: [31] DIO31 // // Data output enable for DIO 31 -#define GPIO_DOE31_0_DIO31 0x80000000 -#define GPIO_DOE31_0_DIO31_BITN 31 -#define GPIO_DOE31_0_DIO31_M 0x80000000 -#define GPIO_DOE31_0_DIO31_S 31 +#define GPIO_DOE31_0_DIO31 0x80000000 +#define GPIO_DOE31_0_DIO31_BITN 31 +#define GPIO_DOE31_0_DIO31_M 0x80000000 +#define GPIO_DOE31_0_DIO31_S 31 // Field: [30] DIO30 // // Data output enable for DIO 30 -#define GPIO_DOE31_0_DIO30 0x40000000 -#define GPIO_DOE31_0_DIO30_BITN 30 -#define GPIO_DOE31_0_DIO30_M 0x40000000 -#define GPIO_DOE31_0_DIO30_S 30 +#define GPIO_DOE31_0_DIO30 0x40000000 +#define GPIO_DOE31_0_DIO30_BITN 30 +#define GPIO_DOE31_0_DIO30_M 0x40000000 +#define GPIO_DOE31_0_DIO30_S 30 // Field: [29] DIO29 // // Data output enable for DIO 29 -#define GPIO_DOE31_0_DIO29 0x20000000 -#define GPIO_DOE31_0_DIO29_BITN 29 -#define GPIO_DOE31_0_DIO29_M 0x20000000 -#define GPIO_DOE31_0_DIO29_S 29 +#define GPIO_DOE31_0_DIO29 0x20000000 +#define GPIO_DOE31_0_DIO29_BITN 29 +#define GPIO_DOE31_0_DIO29_M 0x20000000 +#define GPIO_DOE31_0_DIO29_S 29 // Field: [28] DIO28 // // Data output enable for DIO 28 -#define GPIO_DOE31_0_DIO28 0x10000000 -#define GPIO_DOE31_0_DIO28_BITN 28 -#define GPIO_DOE31_0_DIO28_M 0x10000000 -#define GPIO_DOE31_0_DIO28_S 28 +#define GPIO_DOE31_0_DIO28 0x10000000 +#define GPIO_DOE31_0_DIO28_BITN 28 +#define GPIO_DOE31_0_DIO28_M 0x10000000 +#define GPIO_DOE31_0_DIO28_S 28 // Field: [27] DIO27 // // Data output enable for DIO 27 -#define GPIO_DOE31_0_DIO27 0x08000000 -#define GPIO_DOE31_0_DIO27_BITN 27 -#define GPIO_DOE31_0_DIO27_M 0x08000000 -#define GPIO_DOE31_0_DIO27_S 27 +#define GPIO_DOE31_0_DIO27 0x08000000 +#define GPIO_DOE31_0_DIO27_BITN 27 +#define GPIO_DOE31_0_DIO27_M 0x08000000 +#define GPIO_DOE31_0_DIO27_S 27 // Field: [26] DIO26 // // Data output enable for DIO 26 -#define GPIO_DOE31_0_DIO26 0x04000000 -#define GPIO_DOE31_0_DIO26_BITN 26 -#define GPIO_DOE31_0_DIO26_M 0x04000000 -#define GPIO_DOE31_0_DIO26_S 26 +#define GPIO_DOE31_0_DIO26 0x04000000 +#define GPIO_DOE31_0_DIO26_BITN 26 +#define GPIO_DOE31_0_DIO26_M 0x04000000 +#define GPIO_DOE31_0_DIO26_S 26 // Field: [25] DIO25 // // Data output enable for DIO 25 -#define GPIO_DOE31_0_DIO25 0x02000000 -#define GPIO_DOE31_0_DIO25_BITN 25 -#define GPIO_DOE31_0_DIO25_M 0x02000000 -#define GPIO_DOE31_0_DIO25_S 25 +#define GPIO_DOE31_0_DIO25 0x02000000 +#define GPIO_DOE31_0_DIO25_BITN 25 +#define GPIO_DOE31_0_DIO25_M 0x02000000 +#define GPIO_DOE31_0_DIO25_S 25 // Field: [24] DIO24 // // Data output enable for DIO 24 -#define GPIO_DOE31_0_DIO24 0x01000000 -#define GPIO_DOE31_0_DIO24_BITN 24 -#define GPIO_DOE31_0_DIO24_M 0x01000000 -#define GPIO_DOE31_0_DIO24_S 24 +#define GPIO_DOE31_0_DIO24 0x01000000 +#define GPIO_DOE31_0_DIO24_BITN 24 +#define GPIO_DOE31_0_DIO24_M 0x01000000 +#define GPIO_DOE31_0_DIO24_S 24 // Field: [23] DIO23 // // Data output enable for DIO 23 -#define GPIO_DOE31_0_DIO23 0x00800000 -#define GPIO_DOE31_0_DIO23_BITN 23 -#define GPIO_DOE31_0_DIO23_M 0x00800000 -#define GPIO_DOE31_0_DIO23_S 23 +#define GPIO_DOE31_0_DIO23 0x00800000 +#define GPIO_DOE31_0_DIO23_BITN 23 +#define GPIO_DOE31_0_DIO23_M 0x00800000 +#define GPIO_DOE31_0_DIO23_S 23 // Field: [22] DIO22 // // Data output enable for DIO 22 -#define GPIO_DOE31_0_DIO22 0x00400000 -#define GPIO_DOE31_0_DIO22_BITN 22 -#define GPIO_DOE31_0_DIO22_M 0x00400000 -#define GPIO_DOE31_0_DIO22_S 22 +#define GPIO_DOE31_0_DIO22 0x00400000 +#define GPIO_DOE31_0_DIO22_BITN 22 +#define GPIO_DOE31_0_DIO22_M 0x00400000 +#define GPIO_DOE31_0_DIO22_S 22 // Field: [21] DIO21 // // Data output enable for DIO 21 -#define GPIO_DOE31_0_DIO21 0x00200000 -#define GPIO_DOE31_0_DIO21_BITN 21 -#define GPIO_DOE31_0_DIO21_M 0x00200000 -#define GPIO_DOE31_0_DIO21_S 21 +#define GPIO_DOE31_0_DIO21 0x00200000 +#define GPIO_DOE31_0_DIO21_BITN 21 +#define GPIO_DOE31_0_DIO21_M 0x00200000 +#define GPIO_DOE31_0_DIO21_S 21 // Field: [20] DIO20 // // Data output enable for DIO 20 -#define GPIO_DOE31_0_DIO20 0x00100000 -#define GPIO_DOE31_0_DIO20_BITN 20 -#define GPIO_DOE31_0_DIO20_M 0x00100000 -#define GPIO_DOE31_0_DIO20_S 20 +#define GPIO_DOE31_0_DIO20 0x00100000 +#define GPIO_DOE31_0_DIO20_BITN 20 +#define GPIO_DOE31_0_DIO20_M 0x00100000 +#define GPIO_DOE31_0_DIO20_S 20 // Field: [19] DIO19 // // Data output enable for DIO 19 -#define GPIO_DOE31_0_DIO19 0x00080000 -#define GPIO_DOE31_0_DIO19_BITN 19 -#define GPIO_DOE31_0_DIO19_M 0x00080000 -#define GPIO_DOE31_0_DIO19_S 19 +#define GPIO_DOE31_0_DIO19 0x00080000 +#define GPIO_DOE31_0_DIO19_BITN 19 +#define GPIO_DOE31_0_DIO19_M 0x00080000 +#define GPIO_DOE31_0_DIO19_S 19 // Field: [18] DIO18 // // Data output enable for DIO 18 -#define GPIO_DOE31_0_DIO18 0x00040000 -#define GPIO_DOE31_0_DIO18_BITN 18 -#define GPIO_DOE31_0_DIO18_M 0x00040000 -#define GPIO_DOE31_0_DIO18_S 18 +#define GPIO_DOE31_0_DIO18 0x00040000 +#define GPIO_DOE31_0_DIO18_BITN 18 +#define GPIO_DOE31_0_DIO18_M 0x00040000 +#define GPIO_DOE31_0_DIO18_S 18 // Field: [17] DIO17 // // Data output enable for DIO 17 -#define GPIO_DOE31_0_DIO17 0x00020000 -#define GPIO_DOE31_0_DIO17_BITN 17 -#define GPIO_DOE31_0_DIO17_M 0x00020000 -#define GPIO_DOE31_0_DIO17_S 17 +#define GPIO_DOE31_0_DIO17 0x00020000 +#define GPIO_DOE31_0_DIO17_BITN 17 +#define GPIO_DOE31_0_DIO17_M 0x00020000 +#define GPIO_DOE31_0_DIO17_S 17 // Field: [16] DIO16 // // Data output enable for DIO 16 -#define GPIO_DOE31_0_DIO16 0x00010000 -#define GPIO_DOE31_0_DIO16_BITN 16 -#define GPIO_DOE31_0_DIO16_M 0x00010000 -#define GPIO_DOE31_0_DIO16_S 16 +#define GPIO_DOE31_0_DIO16 0x00010000 +#define GPIO_DOE31_0_DIO16_BITN 16 +#define GPIO_DOE31_0_DIO16_M 0x00010000 +#define GPIO_DOE31_0_DIO16_S 16 // Field: [15] DIO15 // // Data output enable for DIO 15 -#define GPIO_DOE31_0_DIO15 0x00008000 -#define GPIO_DOE31_0_DIO15_BITN 15 -#define GPIO_DOE31_0_DIO15_M 0x00008000 -#define GPIO_DOE31_0_DIO15_S 15 +#define GPIO_DOE31_0_DIO15 0x00008000 +#define GPIO_DOE31_0_DIO15_BITN 15 +#define GPIO_DOE31_0_DIO15_M 0x00008000 +#define GPIO_DOE31_0_DIO15_S 15 // Field: [14] DIO14 // // Data output enable for DIO 14 -#define GPIO_DOE31_0_DIO14 0x00004000 -#define GPIO_DOE31_0_DIO14_BITN 14 -#define GPIO_DOE31_0_DIO14_M 0x00004000 -#define GPIO_DOE31_0_DIO14_S 14 +#define GPIO_DOE31_0_DIO14 0x00004000 +#define GPIO_DOE31_0_DIO14_BITN 14 +#define GPIO_DOE31_0_DIO14_M 0x00004000 +#define GPIO_DOE31_0_DIO14_S 14 // Field: [13] DIO13 // // Data output enable for DIO 13 -#define GPIO_DOE31_0_DIO13 0x00002000 -#define GPIO_DOE31_0_DIO13_BITN 13 -#define GPIO_DOE31_0_DIO13_M 0x00002000 -#define GPIO_DOE31_0_DIO13_S 13 +#define GPIO_DOE31_0_DIO13 0x00002000 +#define GPIO_DOE31_0_DIO13_BITN 13 +#define GPIO_DOE31_0_DIO13_M 0x00002000 +#define GPIO_DOE31_0_DIO13_S 13 // Field: [12] DIO12 // // Data output enable for DIO 12 -#define GPIO_DOE31_0_DIO12 0x00001000 -#define GPIO_DOE31_0_DIO12_BITN 12 -#define GPIO_DOE31_0_DIO12_M 0x00001000 -#define GPIO_DOE31_0_DIO12_S 12 +#define GPIO_DOE31_0_DIO12 0x00001000 +#define GPIO_DOE31_0_DIO12_BITN 12 +#define GPIO_DOE31_0_DIO12_M 0x00001000 +#define GPIO_DOE31_0_DIO12_S 12 // Field: [11] DIO11 // // Data output enable for DIO 11 -#define GPIO_DOE31_0_DIO11 0x00000800 -#define GPIO_DOE31_0_DIO11_BITN 11 -#define GPIO_DOE31_0_DIO11_M 0x00000800 -#define GPIO_DOE31_0_DIO11_S 11 +#define GPIO_DOE31_0_DIO11 0x00000800 +#define GPIO_DOE31_0_DIO11_BITN 11 +#define GPIO_DOE31_0_DIO11_M 0x00000800 +#define GPIO_DOE31_0_DIO11_S 11 // Field: [10] DIO10 // // Data output enable for DIO 10 -#define GPIO_DOE31_0_DIO10 0x00000400 -#define GPIO_DOE31_0_DIO10_BITN 10 -#define GPIO_DOE31_0_DIO10_M 0x00000400 -#define GPIO_DOE31_0_DIO10_S 10 +#define GPIO_DOE31_0_DIO10 0x00000400 +#define GPIO_DOE31_0_DIO10_BITN 10 +#define GPIO_DOE31_0_DIO10_M 0x00000400 +#define GPIO_DOE31_0_DIO10_S 10 // Field: [9] DIO9 // // Data output enable for DIO 9 -#define GPIO_DOE31_0_DIO9 0x00000200 -#define GPIO_DOE31_0_DIO9_BITN 9 -#define GPIO_DOE31_0_DIO9_M 0x00000200 -#define GPIO_DOE31_0_DIO9_S 9 +#define GPIO_DOE31_0_DIO9 0x00000200 +#define GPIO_DOE31_0_DIO9_BITN 9 +#define GPIO_DOE31_0_DIO9_M 0x00000200 +#define GPIO_DOE31_0_DIO9_S 9 // Field: [8] DIO8 // // Data output enable for DIO 8 -#define GPIO_DOE31_0_DIO8 0x00000100 -#define GPIO_DOE31_0_DIO8_BITN 8 -#define GPIO_DOE31_0_DIO8_M 0x00000100 -#define GPIO_DOE31_0_DIO8_S 8 +#define GPIO_DOE31_0_DIO8 0x00000100 +#define GPIO_DOE31_0_DIO8_BITN 8 +#define GPIO_DOE31_0_DIO8_M 0x00000100 +#define GPIO_DOE31_0_DIO8_S 8 // Field: [7] DIO7 // // Data output enable for DIO 7 -#define GPIO_DOE31_0_DIO7 0x00000080 -#define GPIO_DOE31_0_DIO7_BITN 7 -#define GPIO_DOE31_0_DIO7_M 0x00000080 -#define GPIO_DOE31_0_DIO7_S 7 +#define GPIO_DOE31_0_DIO7 0x00000080 +#define GPIO_DOE31_0_DIO7_BITN 7 +#define GPIO_DOE31_0_DIO7_M 0x00000080 +#define GPIO_DOE31_0_DIO7_S 7 // Field: [6] DIO6 // // Data output enable for DIO 6 -#define GPIO_DOE31_0_DIO6 0x00000040 -#define GPIO_DOE31_0_DIO6_BITN 6 -#define GPIO_DOE31_0_DIO6_M 0x00000040 -#define GPIO_DOE31_0_DIO6_S 6 +#define GPIO_DOE31_0_DIO6 0x00000040 +#define GPIO_DOE31_0_DIO6_BITN 6 +#define GPIO_DOE31_0_DIO6_M 0x00000040 +#define GPIO_DOE31_0_DIO6_S 6 // Field: [5] DIO5 // // Data output enable for DIO 5 -#define GPIO_DOE31_0_DIO5 0x00000020 -#define GPIO_DOE31_0_DIO5_BITN 5 -#define GPIO_DOE31_0_DIO5_M 0x00000020 -#define GPIO_DOE31_0_DIO5_S 5 +#define GPIO_DOE31_0_DIO5 0x00000020 +#define GPIO_DOE31_0_DIO5_BITN 5 +#define GPIO_DOE31_0_DIO5_M 0x00000020 +#define GPIO_DOE31_0_DIO5_S 5 // Field: [4] DIO4 // // Data output enable for DIO 4 -#define GPIO_DOE31_0_DIO4 0x00000010 -#define GPIO_DOE31_0_DIO4_BITN 4 -#define GPIO_DOE31_0_DIO4_M 0x00000010 -#define GPIO_DOE31_0_DIO4_S 4 +#define GPIO_DOE31_0_DIO4 0x00000010 +#define GPIO_DOE31_0_DIO4_BITN 4 +#define GPIO_DOE31_0_DIO4_M 0x00000010 +#define GPIO_DOE31_0_DIO4_S 4 // Field: [3] DIO3 // // Data output enable for DIO 3 -#define GPIO_DOE31_0_DIO3 0x00000008 -#define GPIO_DOE31_0_DIO3_BITN 3 -#define GPIO_DOE31_0_DIO3_M 0x00000008 -#define GPIO_DOE31_0_DIO3_S 3 +#define GPIO_DOE31_0_DIO3 0x00000008 +#define GPIO_DOE31_0_DIO3_BITN 3 +#define GPIO_DOE31_0_DIO3_M 0x00000008 +#define GPIO_DOE31_0_DIO3_S 3 // Field: [2] DIO2 // // Data output enable for DIO 2 -#define GPIO_DOE31_0_DIO2 0x00000004 -#define GPIO_DOE31_0_DIO2_BITN 2 -#define GPIO_DOE31_0_DIO2_M 0x00000004 -#define GPIO_DOE31_0_DIO2_S 2 +#define GPIO_DOE31_0_DIO2 0x00000004 +#define GPIO_DOE31_0_DIO2_BITN 2 +#define GPIO_DOE31_0_DIO2_M 0x00000004 +#define GPIO_DOE31_0_DIO2_S 2 // Field: [1] DIO1 // // Data output enable for DIO 1 -#define GPIO_DOE31_0_DIO1 0x00000002 -#define GPIO_DOE31_0_DIO1_BITN 1 -#define GPIO_DOE31_0_DIO1_M 0x00000002 -#define GPIO_DOE31_0_DIO1_S 1 +#define GPIO_DOE31_0_DIO1 0x00000002 +#define GPIO_DOE31_0_DIO1_BITN 1 +#define GPIO_DOE31_0_DIO1_M 0x00000002 +#define GPIO_DOE31_0_DIO1_S 1 // Field: [0] DIO0 // // Data output enable for DIO 0 -#define GPIO_DOE31_0_DIO0 0x00000001 -#define GPIO_DOE31_0_DIO0_BITN 0 -#define GPIO_DOE31_0_DIO0_M 0x00000001 -#define GPIO_DOE31_0_DIO0_S 0 +#define GPIO_DOE31_0_DIO0 0x00000001 +#define GPIO_DOE31_0_DIO0_BITN 0 +#define GPIO_DOE31_0_DIO0_M 0x00000001 +#define GPIO_DOE31_0_DIO0_S 0 //***************************************************************************** // @@ -1990,258 +1990,257 @@ // Field: [31] DIO31 // // Event for DIO 31 -#define GPIO_EVFLAGS31_0_DIO31 0x80000000 -#define GPIO_EVFLAGS31_0_DIO31_BITN 31 -#define GPIO_EVFLAGS31_0_DIO31_M 0x80000000 -#define GPIO_EVFLAGS31_0_DIO31_S 31 +#define GPIO_EVFLAGS31_0_DIO31 0x80000000 +#define GPIO_EVFLAGS31_0_DIO31_BITN 31 +#define GPIO_EVFLAGS31_0_DIO31_M 0x80000000 +#define GPIO_EVFLAGS31_0_DIO31_S 31 // Field: [30] DIO30 // // Event for DIO 30 -#define GPIO_EVFLAGS31_0_DIO30 0x40000000 -#define GPIO_EVFLAGS31_0_DIO30_BITN 30 -#define GPIO_EVFLAGS31_0_DIO30_M 0x40000000 -#define GPIO_EVFLAGS31_0_DIO30_S 30 +#define GPIO_EVFLAGS31_0_DIO30 0x40000000 +#define GPIO_EVFLAGS31_0_DIO30_BITN 30 +#define GPIO_EVFLAGS31_0_DIO30_M 0x40000000 +#define GPIO_EVFLAGS31_0_DIO30_S 30 // Field: [29] DIO29 // // Event for DIO 29 -#define GPIO_EVFLAGS31_0_DIO29 0x20000000 -#define GPIO_EVFLAGS31_0_DIO29_BITN 29 -#define GPIO_EVFLAGS31_0_DIO29_M 0x20000000 -#define GPIO_EVFLAGS31_0_DIO29_S 29 +#define GPIO_EVFLAGS31_0_DIO29 0x20000000 +#define GPIO_EVFLAGS31_0_DIO29_BITN 29 +#define GPIO_EVFLAGS31_0_DIO29_M 0x20000000 +#define GPIO_EVFLAGS31_0_DIO29_S 29 // Field: [28] DIO28 // // Event for DIO 28 -#define GPIO_EVFLAGS31_0_DIO28 0x10000000 -#define GPIO_EVFLAGS31_0_DIO28_BITN 28 -#define GPIO_EVFLAGS31_0_DIO28_M 0x10000000 -#define GPIO_EVFLAGS31_0_DIO28_S 28 +#define GPIO_EVFLAGS31_0_DIO28 0x10000000 +#define GPIO_EVFLAGS31_0_DIO28_BITN 28 +#define GPIO_EVFLAGS31_0_DIO28_M 0x10000000 +#define GPIO_EVFLAGS31_0_DIO28_S 28 // Field: [27] DIO27 // // Event for DIO 27 -#define GPIO_EVFLAGS31_0_DIO27 0x08000000 -#define GPIO_EVFLAGS31_0_DIO27_BITN 27 -#define GPIO_EVFLAGS31_0_DIO27_M 0x08000000 -#define GPIO_EVFLAGS31_0_DIO27_S 27 +#define GPIO_EVFLAGS31_0_DIO27 0x08000000 +#define GPIO_EVFLAGS31_0_DIO27_BITN 27 +#define GPIO_EVFLAGS31_0_DIO27_M 0x08000000 +#define GPIO_EVFLAGS31_0_DIO27_S 27 // Field: [26] DIO26 // // Event for DIO 26 -#define GPIO_EVFLAGS31_0_DIO26 0x04000000 -#define GPIO_EVFLAGS31_0_DIO26_BITN 26 -#define GPIO_EVFLAGS31_0_DIO26_M 0x04000000 -#define GPIO_EVFLAGS31_0_DIO26_S 26 +#define GPIO_EVFLAGS31_0_DIO26 0x04000000 +#define GPIO_EVFLAGS31_0_DIO26_BITN 26 +#define GPIO_EVFLAGS31_0_DIO26_M 0x04000000 +#define GPIO_EVFLAGS31_0_DIO26_S 26 // Field: [25] DIO25 // // Event for DIO 25 -#define GPIO_EVFLAGS31_0_DIO25 0x02000000 -#define GPIO_EVFLAGS31_0_DIO25_BITN 25 -#define GPIO_EVFLAGS31_0_DIO25_M 0x02000000 -#define GPIO_EVFLAGS31_0_DIO25_S 25 +#define GPIO_EVFLAGS31_0_DIO25 0x02000000 +#define GPIO_EVFLAGS31_0_DIO25_BITN 25 +#define GPIO_EVFLAGS31_0_DIO25_M 0x02000000 +#define GPIO_EVFLAGS31_0_DIO25_S 25 // Field: [24] DIO24 // // Event for DIO 24 -#define GPIO_EVFLAGS31_0_DIO24 0x01000000 -#define GPIO_EVFLAGS31_0_DIO24_BITN 24 -#define GPIO_EVFLAGS31_0_DIO24_M 0x01000000 -#define GPIO_EVFLAGS31_0_DIO24_S 24 +#define GPIO_EVFLAGS31_0_DIO24 0x01000000 +#define GPIO_EVFLAGS31_0_DIO24_BITN 24 +#define GPIO_EVFLAGS31_0_DIO24_M 0x01000000 +#define GPIO_EVFLAGS31_0_DIO24_S 24 // Field: [23] DIO23 // // Event for DIO 23 -#define GPIO_EVFLAGS31_0_DIO23 0x00800000 -#define GPIO_EVFLAGS31_0_DIO23_BITN 23 -#define GPIO_EVFLAGS31_0_DIO23_M 0x00800000 -#define GPIO_EVFLAGS31_0_DIO23_S 23 +#define GPIO_EVFLAGS31_0_DIO23 0x00800000 +#define GPIO_EVFLAGS31_0_DIO23_BITN 23 +#define GPIO_EVFLAGS31_0_DIO23_M 0x00800000 +#define GPIO_EVFLAGS31_0_DIO23_S 23 // Field: [22] DIO22 // // Event for DIO 22 -#define GPIO_EVFLAGS31_0_DIO22 0x00400000 -#define GPIO_EVFLAGS31_0_DIO22_BITN 22 -#define GPIO_EVFLAGS31_0_DIO22_M 0x00400000 -#define GPIO_EVFLAGS31_0_DIO22_S 22 +#define GPIO_EVFLAGS31_0_DIO22 0x00400000 +#define GPIO_EVFLAGS31_0_DIO22_BITN 22 +#define GPIO_EVFLAGS31_0_DIO22_M 0x00400000 +#define GPIO_EVFLAGS31_0_DIO22_S 22 // Field: [21] DIO21 // // Event for DIO 21 -#define GPIO_EVFLAGS31_0_DIO21 0x00200000 -#define GPIO_EVFLAGS31_0_DIO21_BITN 21 -#define GPIO_EVFLAGS31_0_DIO21_M 0x00200000 -#define GPIO_EVFLAGS31_0_DIO21_S 21 +#define GPIO_EVFLAGS31_0_DIO21 0x00200000 +#define GPIO_EVFLAGS31_0_DIO21_BITN 21 +#define GPIO_EVFLAGS31_0_DIO21_M 0x00200000 +#define GPIO_EVFLAGS31_0_DIO21_S 21 // Field: [20] DIO20 // // Event for DIO 20 -#define GPIO_EVFLAGS31_0_DIO20 0x00100000 -#define GPIO_EVFLAGS31_0_DIO20_BITN 20 -#define GPIO_EVFLAGS31_0_DIO20_M 0x00100000 -#define GPIO_EVFLAGS31_0_DIO20_S 20 +#define GPIO_EVFLAGS31_0_DIO20 0x00100000 +#define GPIO_EVFLAGS31_0_DIO20_BITN 20 +#define GPIO_EVFLAGS31_0_DIO20_M 0x00100000 +#define GPIO_EVFLAGS31_0_DIO20_S 20 // Field: [19] DIO19 // // Event for DIO 19 -#define GPIO_EVFLAGS31_0_DIO19 0x00080000 -#define GPIO_EVFLAGS31_0_DIO19_BITN 19 -#define GPIO_EVFLAGS31_0_DIO19_M 0x00080000 -#define GPIO_EVFLAGS31_0_DIO19_S 19 +#define GPIO_EVFLAGS31_0_DIO19 0x00080000 +#define GPIO_EVFLAGS31_0_DIO19_BITN 19 +#define GPIO_EVFLAGS31_0_DIO19_M 0x00080000 +#define GPIO_EVFLAGS31_0_DIO19_S 19 // Field: [18] DIO18 // // Event for DIO 18 -#define GPIO_EVFLAGS31_0_DIO18 0x00040000 -#define GPIO_EVFLAGS31_0_DIO18_BITN 18 -#define GPIO_EVFLAGS31_0_DIO18_M 0x00040000 -#define GPIO_EVFLAGS31_0_DIO18_S 18 +#define GPIO_EVFLAGS31_0_DIO18 0x00040000 +#define GPIO_EVFLAGS31_0_DIO18_BITN 18 +#define GPIO_EVFLAGS31_0_DIO18_M 0x00040000 +#define GPIO_EVFLAGS31_0_DIO18_S 18 // Field: [17] DIO17 // // Event for DIO 17 -#define GPIO_EVFLAGS31_0_DIO17 0x00020000 -#define GPIO_EVFLAGS31_0_DIO17_BITN 17 -#define GPIO_EVFLAGS31_0_DIO17_M 0x00020000 -#define GPIO_EVFLAGS31_0_DIO17_S 17 +#define GPIO_EVFLAGS31_0_DIO17 0x00020000 +#define GPIO_EVFLAGS31_0_DIO17_BITN 17 +#define GPIO_EVFLAGS31_0_DIO17_M 0x00020000 +#define GPIO_EVFLAGS31_0_DIO17_S 17 // Field: [16] DIO16 // // Event for DIO 16 -#define GPIO_EVFLAGS31_0_DIO16 0x00010000 -#define GPIO_EVFLAGS31_0_DIO16_BITN 16 -#define GPIO_EVFLAGS31_0_DIO16_M 0x00010000 -#define GPIO_EVFLAGS31_0_DIO16_S 16 +#define GPIO_EVFLAGS31_0_DIO16 0x00010000 +#define GPIO_EVFLAGS31_0_DIO16_BITN 16 +#define GPIO_EVFLAGS31_0_DIO16_M 0x00010000 +#define GPIO_EVFLAGS31_0_DIO16_S 16 // Field: [15] DIO15 // // Event for DIO 15 -#define GPIO_EVFLAGS31_0_DIO15 0x00008000 -#define GPIO_EVFLAGS31_0_DIO15_BITN 15 -#define GPIO_EVFLAGS31_0_DIO15_M 0x00008000 -#define GPIO_EVFLAGS31_0_DIO15_S 15 +#define GPIO_EVFLAGS31_0_DIO15 0x00008000 +#define GPIO_EVFLAGS31_0_DIO15_BITN 15 +#define GPIO_EVFLAGS31_0_DIO15_M 0x00008000 +#define GPIO_EVFLAGS31_0_DIO15_S 15 // Field: [14] DIO14 // // Event for DIO 14 -#define GPIO_EVFLAGS31_0_DIO14 0x00004000 -#define GPIO_EVFLAGS31_0_DIO14_BITN 14 -#define GPIO_EVFLAGS31_0_DIO14_M 0x00004000 -#define GPIO_EVFLAGS31_0_DIO14_S 14 +#define GPIO_EVFLAGS31_0_DIO14 0x00004000 +#define GPIO_EVFLAGS31_0_DIO14_BITN 14 +#define GPIO_EVFLAGS31_0_DIO14_M 0x00004000 +#define GPIO_EVFLAGS31_0_DIO14_S 14 // Field: [13] DIO13 // // Event for DIO 13 -#define GPIO_EVFLAGS31_0_DIO13 0x00002000 -#define GPIO_EVFLAGS31_0_DIO13_BITN 13 -#define GPIO_EVFLAGS31_0_DIO13_M 0x00002000 -#define GPIO_EVFLAGS31_0_DIO13_S 13 +#define GPIO_EVFLAGS31_0_DIO13 0x00002000 +#define GPIO_EVFLAGS31_0_DIO13_BITN 13 +#define GPIO_EVFLAGS31_0_DIO13_M 0x00002000 +#define GPIO_EVFLAGS31_0_DIO13_S 13 // Field: [12] DIO12 // // Event for DIO 12 -#define GPIO_EVFLAGS31_0_DIO12 0x00001000 -#define GPIO_EVFLAGS31_0_DIO12_BITN 12 -#define GPIO_EVFLAGS31_0_DIO12_M 0x00001000 -#define GPIO_EVFLAGS31_0_DIO12_S 12 +#define GPIO_EVFLAGS31_0_DIO12 0x00001000 +#define GPIO_EVFLAGS31_0_DIO12_BITN 12 +#define GPIO_EVFLAGS31_0_DIO12_M 0x00001000 +#define GPIO_EVFLAGS31_0_DIO12_S 12 // Field: [11] DIO11 // // Event for DIO 11 -#define GPIO_EVFLAGS31_0_DIO11 0x00000800 -#define GPIO_EVFLAGS31_0_DIO11_BITN 11 -#define GPIO_EVFLAGS31_0_DIO11_M 0x00000800 -#define GPIO_EVFLAGS31_0_DIO11_S 11 +#define GPIO_EVFLAGS31_0_DIO11 0x00000800 +#define GPIO_EVFLAGS31_0_DIO11_BITN 11 +#define GPIO_EVFLAGS31_0_DIO11_M 0x00000800 +#define GPIO_EVFLAGS31_0_DIO11_S 11 // Field: [10] DIO10 // // Event for DIO 10 -#define GPIO_EVFLAGS31_0_DIO10 0x00000400 -#define GPIO_EVFLAGS31_0_DIO10_BITN 10 -#define GPIO_EVFLAGS31_0_DIO10_M 0x00000400 -#define GPIO_EVFLAGS31_0_DIO10_S 10 +#define GPIO_EVFLAGS31_0_DIO10 0x00000400 +#define GPIO_EVFLAGS31_0_DIO10_BITN 10 +#define GPIO_EVFLAGS31_0_DIO10_M 0x00000400 +#define GPIO_EVFLAGS31_0_DIO10_S 10 // Field: [9] DIO9 // // Event for DIO 9 -#define GPIO_EVFLAGS31_0_DIO9 0x00000200 -#define GPIO_EVFLAGS31_0_DIO9_BITN 9 -#define GPIO_EVFLAGS31_0_DIO9_M 0x00000200 -#define GPIO_EVFLAGS31_0_DIO9_S 9 +#define GPIO_EVFLAGS31_0_DIO9 0x00000200 +#define GPIO_EVFLAGS31_0_DIO9_BITN 9 +#define GPIO_EVFLAGS31_0_DIO9_M 0x00000200 +#define GPIO_EVFLAGS31_0_DIO9_S 9 // Field: [8] DIO8 // // Event for DIO 8 -#define GPIO_EVFLAGS31_0_DIO8 0x00000100 -#define GPIO_EVFLAGS31_0_DIO8_BITN 8 -#define GPIO_EVFLAGS31_0_DIO8_M 0x00000100 -#define GPIO_EVFLAGS31_0_DIO8_S 8 +#define GPIO_EVFLAGS31_0_DIO8 0x00000100 +#define GPIO_EVFLAGS31_0_DIO8_BITN 8 +#define GPIO_EVFLAGS31_0_DIO8_M 0x00000100 +#define GPIO_EVFLAGS31_0_DIO8_S 8 // Field: [7] DIO7 // // Event for DIO 7 -#define GPIO_EVFLAGS31_0_DIO7 0x00000080 -#define GPIO_EVFLAGS31_0_DIO7_BITN 7 -#define GPIO_EVFLAGS31_0_DIO7_M 0x00000080 -#define GPIO_EVFLAGS31_0_DIO7_S 7 +#define GPIO_EVFLAGS31_0_DIO7 0x00000080 +#define GPIO_EVFLAGS31_0_DIO7_BITN 7 +#define GPIO_EVFLAGS31_0_DIO7_M 0x00000080 +#define GPIO_EVFLAGS31_0_DIO7_S 7 // Field: [6] DIO6 // // Event for DIO 6 -#define GPIO_EVFLAGS31_0_DIO6 0x00000040 -#define GPIO_EVFLAGS31_0_DIO6_BITN 6 -#define GPIO_EVFLAGS31_0_DIO6_M 0x00000040 -#define GPIO_EVFLAGS31_0_DIO6_S 6 +#define GPIO_EVFLAGS31_0_DIO6 0x00000040 +#define GPIO_EVFLAGS31_0_DIO6_BITN 6 +#define GPIO_EVFLAGS31_0_DIO6_M 0x00000040 +#define GPIO_EVFLAGS31_0_DIO6_S 6 // Field: [5] DIO5 // // Event for DIO 5 -#define GPIO_EVFLAGS31_0_DIO5 0x00000020 -#define GPIO_EVFLAGS31_0_DIO5_BITN 5 -#define GPIO_EVFLAGS31_0_DIO5_M 0x00000020 -#define GPIO_EVFLAGS31_0_DIO5_S 5 +#define GPIO_EVFLAGS31_0_DIO5 0x00000020 +#define GPIO_EVFLAGS31_0_DIO5_BITN 5 +#define GPIO_EVFLAGS31_0_DIO5_M 0x00000020 +#define GPIO_EVFLAGS31_0_DIO5_S 5 // Field: [4] DIO4 // // Event for DIO 4 -#define GPIO_EVFLAGS31_0_DIO4 0x00000010 -#define GPIO_EVFLAGS31_0_DIO4_BITN 4 -#define GPIO_EVFLAGS31_0_DIO4_M 0x00000010 -#define GPIO_EVFLAGS31_0_DIO4_S 4 +#define GPIO_EVFLAGS31_0_DIO4 0x00000010 +#define GPIO_EVFLAGS31_0_DIO4_BITN 4 +#define GPIO_EVFLAGS31_0_DIO4_M 0x00000010 +#define GPIO_EVFLAGS31_0_DIO4_S 4 // Field: [3] DIO3 // // Event for DIO 3 -#define GPIO_EVFLAGS31_0_DIO3 0x00000008 -#define GPIO_EVFLAGS31_0_DIO3_BITN 3 -#define GPIO_EVFLAGS31_0_DIO3_M 0x00000008 -#define GPIO_EVFLAGS31_0_DIO3_S 3 +#define GPIO_EVFLAGS31_0_DIO3 0x00000008 +#define GPIO_EVFLAGS31_0_DIO3_BITN 3 +#define GPIO_EVFLAGS31_0_DIO3_M 0x00000008 +#define GPIO_EVFLAGS31_0_DIO3_S 3 // Field: [2] DIO2 // // Event for DIO 2 -#define GPIO_EVFLAGS31_0_DIO2 0x00000004 -#define GPIO_EVFLAGS31_0_DIO2_BITN 2 -#define GPIO_EVFLAGS31_0_DIO2_M 0x00000004 -#define GPIO_EVFLAGS31_0_DIO2_S 2 +#define GPIO_EVFLAGS31_0_DIO2 0x00000004 +#define GPIO_EVFLAGS31_0_DIO2_BITN 2 +#define GPIO_EVFLAGS31_0_DIO2_M 0x00000004 +#define GPIO_EVFLAGS31_0_DIO2_S 2 // Field: [1] DIO1 // // Event for DIO 1 -#define GPIO_EVFLAGS31_0_DIO1 0x00000002 -#define GPIO_EVFLAGS31_0_DIO1_BITN 1 -#define GPIO_EVFLAGS31_0_DIO1_M 0x00000002 -#define GPIO_EVFLAGS31_0_DIO1_S 1 +#define GPIO_EVFLAGS31_0_DIO1 0x00000002 +#define GPIO_EVFLAGS31_0_DIO1_BITN 1 +#define GPIO_EVFLAGS31_0_DIO1_M 0x00000002 +#define GPIO_EVFLAGS31_0_DIO1_S 1 // Field: [0] DIO0 // // Event for DIO 0 -#define GPIO_EVFLAGS31_0_DIO0 0x00000001 -#define GPIO_EVFLAGS31_0_DIO0_BITN 0 -#define GPIO_EVFLAGS31_0_DIO0_M 0x00000001 -#define GPIO_EVFLAGS31_0_DIO0_S 0 - +#define GPIO_EVFLAGS31_0_DIO0 0x00000001 +#define GPIO_EVFLAGS31_0_DIO0_BITN 0 +#define GPIO_EVFLAGS31_0_DIO0_M 0x00000001 +#define GPIO_EVFLAGS31_0_DIO0_S 0 #endif // __GPIO__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_gpram.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_gpram.h index cbd0988..a4aeb9a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_gpram.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_gpram.h @@ -1,48 +1,45 @@ /****************************************************************************** -* Filename: hw_gpram_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_gpram_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_GPRAM_H__ #define __HW_GPRAM_H__ +#define GPRAM_O_BANK0 0x00000000 +#define GPRAM_BANK0_BYTE_SIZE 8192 -#define GPRAM_O_BANK0 0x00000000 -#define GPRAM_BANK0_BYTE_SIZE 8192 - -#define GPRAM_TOT_BYTE_SIZE 8192 - - +#define GPRAM_TOT_BYTE_SIZE 8192 #endif // __HW_GPRAM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_gpt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_gpt.h index d9cc05d..fd4646f 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_gpt.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_gpt.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_gpt_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_gpt_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_GPT_H__ #define __HW_GPT_H__ @@ -44,88 +44,88 @@ // //***************************************************************************** // Configuration -#define GPT_O_CFG 0x00000000 +#define GPT_O_CFG 0x00000000 // Timer A Mode -#define GPT_O_TAMR 0x00000004 +#define GPT_O_TAMR 0x00000004 // Timer B Mode -#define GPT_O_TBMR 0x00000008 +#define GPT_O_TBMR 0x00000008 // Control -#define GPT_O_CTL 0x0000000C +#define GPT_O_CTL 0x0000000C // Synch Register -#define GPT_O_SYNC 0x00000010 +#define GPT_O_SYNC 0x00000010 // Interrupt Mask -#define GPT_O_IMR 0x00000018 +#define GPT_O_IMR 0x00000018 // Raw Interrupt Status -#define GPT_O_RIS 0x0000001C +#define GPT_O_RIS 0x0000001C // Masked Interrupt Status -#define GPT_O_MIS 0x00000020 +#define GPT_O_MIS 0x00000020 // Interrupt Clear -#define GPT_O_ICLR 0x00000024 +#define GPT_O_ICLR 0x00000024 // Timer A Interval Load Register -#define GPT_O_TAILR 0x00000028 +#define GPT_O_TAILR 0x00000028 // Timer B Interval Load Register -#define GPT_O_TBILR 0x0000002C +#define GPT_O_TBILR 0x0000002C // Timer A Match Register -#define GPT_O_TAMATCHR 0x00000030 +#define GPT_O_TAMATCHR 0x00000030 // Timer B Match Register -#define GPT_O_TBMATCHR 0x00000034 +#define GPT_O_TBMATCHR 0x00000034 // Timer A Pre-scale -#define GPT_O_TAPR 0x00000038 +#define GPT_O_TAPR 0x00000038 // Timer B Pre-scale -#define GPT_O_TBPR 0x0000003C +#define GPT_O_TBPR 0x0000003C // Timer A Pre-scale Match -#define GPT_O_TAPMR 0x00000040 +#define GPT_O_TAPMR 0x00000040 // Timer B Pre-scale Match -#define GPT_O_TBPMR 0x00000044 +#define GPT_O_TBPMR 0x00000044 // Timer A Register -#define GPT_O_TAR 0x00000048 +#define GPT_O_TAR 0x00000048 // Timer B Register -#define GPT_O_TBR 0x0000004C +#define GPT_O_TBR 0x0000004C // Timer A Value -#define GPT_O_TAV 0x00000050 +#define GPT_O_TAV 0x00000050 // Timer B Value -#define GPT_O_TBV 0x00000054 +#define GPT_O_TBV 0x00000054 // Timer A Pre-scale Snap-shot -#define GPT_O_TAPS 0x0000005C +#define GPT_O_TAPS 0x0000005C // Timer B Pre-scale Snap-shot -#define GPT_O_TBPS 0x00000060 +#define GPT_O_TBPS 0x00000060 // Timer A Pre-scale Value -#define GPT_O_TAPV 0x00000064 +#define GPT_O_TAPV 0x00000064 // Timer B Pre-scale Value -#define GPT_O_TBPV 0x00000068 +#define GPT_O_TBPV 0x00000068 // DMA Event -#define GPT_O_DMAEV 0x0000006C +#define GPT_O_DMAEV 0x0000006C // Peripheral Version -#define GPT_O_VERSION 0x00000FB0 +#define GPT_O_VERSION 0x00000FB0 // Combined CCP Output -#define GPT_O_ANDCCP 0x00000FB4 +#define GPT_O_ANDCCP 0x00000FB4 //***************************************************************************** // @@ -144,11 +144,11 @@ // Also see TAMR.TAMR and // TBMR.TBMR. // 32BIT_TIMER 32-bit timer configuration -#define GPT_CFG_CFG_W 3 -#define GPT_CFG_CFG_M 0x00000007 -#define GPT_CFG_CFG_S 0 -#define GPT_CFG_CFG_16BIT_TIMER 0x00000004 -#define GPT_CFG_CFG_32BIT_TIMER 0x00000000 +#define GPT_CFG_CFG_W 3 +#define GPT_CFG_CFG_M 0x00000007 +#define GPT_CFG_CFG_S 0 +#define GPT_CFG_CFG_16BIT_TIMER 0x00000004 +#define GPT_CFG_CFG_32BIT_TIMER 0x00000000 //***************************************************************************** // @@ -171,17 +171,17 @@ // CLR_ON_TO Clear CCP output pin on Time-Out // TOG_ON_TO Toggle State on Time-Out // DIS_CMP Disable compare operations -#define GPT_TAMR_TCACT_W 3 -#define GPT_TAMR_TCACT_M 0x0000E000 -#define GPT_TAMR_TCACT_S 13 -#define GPT_TAMR_TCACT_CLRSET_ON_TO 0x0000E000 -#define GPT_TAMR_TCACT_SETCLR_ON_TO 0x0000C000 -#define GPT_TAMR_TCACT_CLRTOG_ON_TO 0x0000A000 -#define GPT_TAMR_TCACT_SETTOG_ON_TO 0x00008000 -#define GPT_TAMR_TCACT_SET_ON_TO 0x00006000 -#define GPT_TAMR_TCACT_CLR_ON_TO 0x00004000 -#define GPT_TAMR_TCACT_TOG_ON_TO 0x00002000 -#define GPT_TAMR_TCACT_DIS_CMP 0x00000000 +#define GPT_TAMR_TCACT_W 3 +#define GPT_TAMR_TCACT_M 0x0000E000 +#define GPT_TAMR_TCACT_S 13 +#define GPT_TAMR_TCACT_CLRSET_ON_TO 0x0000E000 +#define GPT_TAMR_TCACT_SETCLR_ON_TO 0x0000C000 +#define GPT_TAMR_TCACT_CLRTOG_ON_TO 0x0000A000 +#define GPT_TAMR_TCACT_SETTOG_ON_TO 0x00008000 +#define GPT_TAMR_TCACT_SET_ON_TO 0x00006000 +#define GPT_TAMR_TCACT_CLR_ON_TO 0x00004000 +#define GPT_TAMR_TCACT_TOG_ON_TO 0x00002000 +#define GPT_TAMR_TCACT_DIS_CMP 0x00000000 // Field: [12] TACINTD // @@ -189,12 +189,12 @@ // ENUMs: // DIS_TO_INTR Time-out interrupt are disabled // EN_TO_INTR Time-out interrupt function as normal -#define GPT_TAMR_TACINTD 0x00001000 -#define GPT_TAMR_TACINTD_BITN 12 -#define GPT_TAMR_TACINTD_M 0x00001000 -#define GPT_TAMR_TACINTD_S 12 -#define GPT_TAMR_TACINTD_DIS_TO_INTR 0x00001000 -#define GPT_TAMR_TACINTD_EN_TO_INTR 0x00000000 +#define GPT_TAMR_TACINTD 0x00001000 +#define GPT_TAMR_TACINTD_BITN 12 +#define GPT_TAMR_TACINTD_M 0x00001000 +#define GPT_TAMR_TACINTD_S 12 +#define GPT_TAMR_TACINTD_DIS_TO_INTR 0x00001000 +#define GPT_TAMR_TACINTD_EN_TO_INTR 0x00000000 // Field: [11] TAPLO // @@ -210,12 +210,12 @@ // ENUMs: // CCP_ON_TO CCP output pin is set to 1 on time-out // LEGACY Legacy operation -#define GPT_TAMR_TAPLO 0x00000800 -#define GPT_TAMR_TAPLO_BITN 11 -#define GPT_TAMR_TAPLO_M 0x00000800 -#define GPT_TAMR_TAPLO_S 11 -#define GPT_TAMR_TAPLO_CCP_ON_TO 0x00000800 -#define GPT_TAMR_TAPLO_LEGACY 0x00000000 +#define GPT_TAMR_TAPLO 0x00000800 +#define GPT_TAMR_TAPLO_BITN 11 +#define GPT_TAMR_TAPLO_M 0x00000800 +#define GPT_TAMR_TAPLO_S 11 +#define GPT_TAMR_TAPLO_CCP_ON_TO 0x00000800 +#define GPT_TAMR_TAPLO_LEGACY 0x00000000 // Field: [10] TAMRSU // @@ -232,12 +232,12 @@ // time-out. // CYCLEUPDATE Update TAMATCHR and TAPR, if used, on the next // cycle. -#define GPT_TAMR_TAMRSU 0x00000400 -#define GPT_TAMR_TAMRSU_BITN 10 -#define GPT_TAMR_TAMRSU_M 0x00000400 -#define GPT_TAMR_TAMRSU_S 10 -#define GPT_TAMR_TAMRSU_TOUPDATE 0x00000400 -#define GPT_TAMR_TAMRSU_CYCLEUPDATE 0x00000000 +#define GPT_TAMR_TAMRSU 0x00000400 +#define GPT_TAMR_TAMRSU_BITN 10 +#define GPT_TAMR_TAMRSU_M 0x00000400 +#define GPT_TAMR_TAMRSU_S 10 +#define GPT_TAMR_TAMRSU_TOUPDATE 0x00000400 +#define GPT_TAMR_TAMRSU_CYCLEUPDATE 0x00000000 // Field: [9] TAPWMIE // @@ -256,12 +256,12 @@ // EN Interrupt is enabled. This bit is only valid in // PWM mode. // DIS Interrupt is disabled. -#define GPT_TAMR_TAPWMIE 0x00000200 -#define GPT_TAMR_TAPWMIE_BITN 9 -#define GPT_TAMR_TAPWMIE_M 0x00000200 -#define GPT_TAMR_TAPWMIE_S 9 -#define GPT_TAMR_TAPWMIE_EN 0x00000200 -#define GPT_TAMR_TAPWMIE_DIS 0x00000000 +#define GPT_TAMR_TAPWMIE 0x00000200 +#define GPT_TAMR_TAPWMIE_BITN 9 +#define GPT_TAMR_TAPWMIE_M 0x00000200 +#define GPT_TAMR_TAPWMIE_S 9 +#define GPT_TAMR_TAPWMIE_EN 0x00000200 +#define GPT_TAMR_TAPWMIE_DIS 0x00000000 // Field: [8] TAILD // @@ -277,12 +277,12 @@ // pre-scaler is used, update the TAPS register // with the value in the TAPR register on the next // clock cycle. -#define GPT_TAMR_TAILD 0x00000100 -#define GPT_TAMR_TAILD_BITN 8 -#define GPT_TAMR_TAILD_M 0x00000100 -#define GPT_TAMR_TAILD_S 8 -#define GPT_TAMR_TAILD_TOUPDATE 0x00000100 -#define GPT_TAMR_TAILD_CYCLEUPDATE 0x00000000 +#define GPT_TAMR_TAILD 0x00000100 +#define GPT_TAMR_TAILD_BITN 8 +#define GPT_TAMR_TAILD_M 0x00000100 +#define GPT_TAMR_TAILD_S 8 +#define GPT_TAMR_TAILD_TOUPDATE 0x00000100 +#define GPT_TAMR_TAILD_CYCLEUPDATE 0x00000000 // Field: [7] TASNAPS // @@ -293,12 +293,12 @@ // at the time-out event into the GPT Timer A // (TAR) register. // DIS Snap-shot mode is disabled. -#define GPT_TAMR_TASNAPS 0x00000080 -#define GPT_TAMR_TASNAPS_BITN 7 -#define GPT_TAMR_TASNAPS_M 0x00000080 -#define GPT_TAMR_TASNAPS_S 7 -#define GPT_TAMR_TASNAPS_EN 0x00000080 -#define GPT_TAMR_TASNAPS_DIS 0x00000000 +#define GPT_TAMR_TASNAPS 0x00000080 +#define GPT_TAMR_TASNAPS_BITN 7 +#define GPT_TAMR_TASNAPS_M 0x00000080 +#define GPT_TAMR_TASNAPS_S 7 +#define GPT_TAMR_TASNAPS_EN 0x00000080 +#define GPT_TAMR_TASNAPS_DIS 0x00000000 // Field: [6] TAWOT // @@ -311,12 +311,12 @@ // Module 0, Timer A. This function is valid for // one-shot, periodic, and PWM modes // NOWAIT Timer A begins counting as soon as it is enabled. -#define GPT_TAMR_TAWOT 0x00000040 -#define GPT_TAMR_TAWOT_BITN 6 -#define GPT_TAMR_TAWOT_M 0x00000040 -#define GPT_TAMR_TAWOT_S 6 -#define GPT_TAMR_TAWOT_WAIT 0x00000040 -#define GPT_TAMR_TAWOT_NOWAIT 0x00000000 +#define GPT_TAMR_TAWOT 0x00000040 +#define GPT_TAMR_TAWOT_BITN 6 +#define GPT_TAMR_TAWOT_M 0x00000040 +#define GPT_TAMR_TAWOT_S 6 +#define GPT_TAMR_TAWOT_WAIT 0x00000040 +#define GPT_TAMR_TAWOT_NOWAIT 0x00000000 // Field: [5] TAMIE // @@ -328,12 +328,12 @@ // DIS The match interrupt is disabled for match events. // Additionally, output triggers on match events // are prevented. -#define GPT_TAMR_TAMIE 0x00000020 -#define GPT_TAMR_TAMIE_BITN 5 -#define GPT_TAMR_TAMIE_M 0x00000020 -#define GPT_TAMR_TAMIE_S 5 -#define GPT_TAMR_TAMIE_EN 0x00000020 -#define GPT_TAMR_TAMIE_DIS 0x00000000 +#define GPT_TAMR_TAMIE 0x00000020 +#define GPT_TAMR_TAMIE_BITN 5 +#define GPT_TAMR_TAMIE_M 0x00000020 +#define GPT_TAMR_TAMIE_S 5 +#define GPT_TAMR_TAMIE_EN 0x00000020 +#define GPT_TAMR_TAMIE_DIS 0x00000000 // Field: [4] TACDIR // @@ -342,12 +342,12 @@ // UP The timer counts up. When counting up, the timer // starts from a value of 0x0. // DOWN The timer counts down. -#define GPT_TAMR_TACDIR 0x00000010 -#define GPT_TAMR_TACDIR_BITN 4 -#define GPT_TAMR_TACDIR_M 0x00000010 -#define GPT_TAMR_TACDIR_S 4 -#define GPT_TAMR_TACDIR_UP 0x00000010 -#define GPT_TAMR_TACDIR_DOWN 0x00000000 +#define GPT_TAMR_TACDIR 0x00000010 +#define GPT_TAMR_TACDIR_BITN 4 +#define GPT_TAMR_TACDIR_M 0x00000010 +#define GPT_TAMR_TACDIR_S 4 +#define GPT_TAMR_TACDIR_UP 0x00000010 +#define GPT_TAMR_TACDIR_DOWN 0x00000000 // Field: [3] TAAMS // @@ -358,12 +358,12 @@ // ENUMs: // PWM PWM mode is enabled // CAP_COMP Capture/Compare mode is enabled. -#define GPT_TAMR_TAAMS 0x00000008 -#define GPT_TAMR_TAAMS_BITN 3 -#define GPT_TAMR_TAAMS_M 0x00000008 -#define GPT_TAMR_TAAMS_S 3 -#define GPT_TAMR_TAAMS_PWM 0x00000008 -#define GPT_TAMR_TAAMS_CAP_COMP 0x00000000 +#define GPT_TAMR_TAAMS 0x00000008 +#define GPT_TAMR_TAAMS_BITN 3 +#define GPT_TAMR_TAAMS_M 0x00000008 +#define GPT_TAMR_TAAMS_S 3 +#define GPT_TAMR_TAAMS_PWM 0x00000008 +#define GPT_TAMR_TAAMS_CAP_COMP 0x00000000 // Field: [2] TACM // @@ -371,12 +371,12 @@ // ENUMs: // EDGTIME Edge-Time mode // EDGCNT Edge-Count mode -#define GPT_TAMR_TACM 0x00000004 -#define GPT_TAMR_TACM_BITN 2 -#define GPT_TAMR_TACM_M 0x00000004 -#define GPT_TAMR_TACM_S 2 -#define GPT_TAMR_TACM_EDGTIME 0x00000004 -#define GPT_TAMR_TACM_EDGCNT 0x00000000 +#define GPT_TAMR_TACM 0x00000004 +#define GPT_TAMR_TACM_BITN 2 +#define GPT_TAMR_TACM_M 0x00000004 +#define GPT_TAMR_TACM_S 2 +#define GPT_TAMR_TACM_EDGTIME 0x00000004 +#define GPT_TAMR_TACM_EDGCNT 0x00000000 // Field: [1:0] TAMR // @@ -392,12 +392,12 @@ // CAPTURE Capture mode // PERIODIC Periodic Timer mode // ONE_SHOT One-Shot Timer mode -#define GPT_TAMR_TAMR_W 2 -#define GPT_TAMR_TAMR_M 0x00000003 -#define GPT_TAMR_TAMR_S 0 -#define GPT_TAMR_TAMR_CAPTURE 0x00000003 -#define GPT_TAMR_TAMR_PERIODIC 0x00000002 -#define GPT_TAMR_TAMR_ONE_SHOT 0x00000001 +#define GPT_TAMR_TAMR_W 2 +#define GPT_TAMR_TAMR_M 0x00000003 +#define GPT_TAMR_TAMR_S 0 +#define GPT_TAMR_TAMR_CAPTURE 0x00000003 +#define GPT_TAMR_TAMR_PERIODIC 0x00000002 +#define GPT_TAMR_TAMR_ONE_SHOT 0x00000001 //***************************************************************************** // @@ -420,17 +420,17 @@ // CLR_ON_TO Clear CCP output pin on Time-Out // TOG_ON_TO Toggle State on Time-Out // DIS_CMP Disable compare operations -#define GPT_TBMR_TCACT_W 3 -#define GPT_TBMR_TCACT_M 0x0000E000 -#define GPT_TBMR_TCACT_S 13 -#define GPT_TBMR_TCACT_CLRSET_ON_TO 0x0000E000 -#define GPT_TBMR_TCACT_SETCLR_ON_TO 0x0000C000 -#define GPT_TBMR_TCACT_CLRTOG_ON_TO 0x0000A000 -#define GPT_TBMR_TCACT_SETTOG_ON_TO 0x00008000 -#define GPT_TBMR_TCACT_SET_ON_TO 0x00006000 -#define GPT_TBMR_TCACT_CLR_ON_TO 0x00004000 -#define GPT_TBMR_TCACT_TOG_ON_TO 0x00002000 -#define GPT_TBMR_TCACT_DIS_CMP 0x00000000 +#define GPT_TBMR_TCACT_W 3 +#define GPT_TBMR_TCACT_M 0x0000E000 +#define GPT_TBMR_TCACT_S 13 +#define GPT_TBMR_TCACT_CLRSET_ON_TO 0x0000E000 +#define GPT_TBMR_TCACT_SETCLR_ON_TO 0x0000C000 +#define GPT_TBMR_TCACT_CLRTOG_ON_TO 0x0000A000 +#define GPT_TBMR_TCACT_SETTOG_ON_TO 0x00008000 +#define GPT_TBMR_TCACT_SET_ON_TO 0x00006000 +#define GPT_TBMR_TCACT_CLR_ON_TO 0x00004000 +#define GPT_TBMR_TCACT_TOG_ON_TO 0x00002000 +#define GPT_TBMR_TCACT_DIS_CMP 0x00000000 // Field: [12] TBCINTD // @@ -438,12 +438,12 @@ // ENUMs: // DIS_TO_INTR Mask Time-Out Interrupt // EN_TO_INTR Normal Time-Out Interrupt -#define GPT_TBMR_TBCINTD 0x00001000 -#define GPT_TBMR_TBCINTD_BITN 12 -#define GPT_TBMR_TBCINTD_M 0x00001000 -#define GPT_TBMR_TBCINTD_S 12 -#define GPT_TBMR_TBCINTD_DIS_TO_INTR 0x00001000 -#define GPT_TBMR_TBCINTD_EN_TO_INTR 0x00000000 +#define GPT_TBMR_TBCINTD 0x00001000 +#define GPT_TBMR_TBCINTD_BITN 12 +#define GPT_TBMR_TBCINTD_M 0x00001000 +#define GPT_TBMR_TBCINTD_S 12 +#define GPT_TBMR_TBCINTD_DIS_TO_INTR 0x00001000 +#define GPT_TBMR_TBCINTD_EN_TO_INTR 0x00000000 // Field: [11] TBPLO // @@ -459,12 +459,12 @@ // ENUMs: // CCP_ON_TO CCP output pin is set to 1 on time-out // LEGACY Legacy operation -#define GPT_TBMR_TBPLO 0x00000800 -#define GPT_TBMR_TBPLO_BITN 11 -#define GPT_TBMR_TBPLO_M 0x00000800 -#define GPT_TBMR_TBPLO_S 11 -#define GPT_TBMR_TBPLO_CCP_ON_TO 0x00000800 -#define GPT_TBMR_TBPLO_LEGACY 0x00000000 +#define GPT_TBMR_TBPLO 0x00000800 +#define GPT_TBMR_TBPLO_BITN 11 +#define GPT_TBMR_TBPLO_M 0x00000800 +#define GPT_TBMR_TBPLO_S 11 +#define GPT_TBMR_TBPLO_CCP_ON_TO 0x00000800 +#define GPT_TBMR_TBPLO_LEGACY 0x00000000 // Field: [10] TBMRSU // @@ -481,12 +481,12 @@ // time-out. // CYCLEUPDATE Update TBMATCHR and TBPR, if used, on the next // cycle. -#define GPT_TBMR_TBMRSU 0x00000400 -#define GPT_TBMR_TBMRSU_BITN 10 -#define GPT_TBMR_TBMRSU_M 0x00000400 -#define GPT_TBMR_TBMRSU_S 10 -#define GPT_TBMR_TBMRSU_TOUPDATE 0x00000400 -#define GPT_TBMR_TBMRSU_CYCLEUPDATE 0x00000000 +#define GPT_TBMR_TBMRSU 0x00000400 +#define GPT_TBMR_TBMRSU_BITN 10 +#define GPT_TBMR_TBMRSU_M 0x00000400 +#define GPT_TBMR_TBMRSU_S 10 +#define GPT_TBMR_TBMRSU_TOUPDATE 0x00000400 +#define GPT_TBMR_TBMRSU_CYCLEUPDATE 0x00000000 // Field: [9] TBPWMIE // @@ -505,12 +505,12 @@ // EN Interrupt is enabled. This bit is only valid in // PWM mode. // DIS Interrupt is disabled. -#define GPT_TBMR_TBPWMIE 0x00000200 -#define GPT_TBMR_TBPWMIE_BITN 9 -#define GPT_TBMR_TBPWMIE_M 0x00000200 -#define GPT_TBMR_TBPWMIE_S 9 -#define GPT_TBMR_TBPWMIE_EN 0x00000200 -#define GPT_TBMR_TBPWMIE_DIS 0x00000000 +#define GPT_TBMR_TBPWMIE 0x00000200 +#define GPT_TBMR_TBPWMIE_BITN 9 +#define GPT_TBMR_TBPWMIE_M 0x00000200 +#define GPT_TBMR_TBPWMIE_S 9 +#define GPT_TBMR_TBPWMIE_EN 0x00000200 +#define GPT_TBMR_TBPWMIE_DIS 0x00000000 // Field: [8] TBILD // @@ -526,12 +526,12 @@ // pre-scaler is used, update the TBPS register // with the value in the TBPR register on the next // clock cycle. -#define GPT_TBMR_TBILD 0x00000100 -#define GPT_TBMR_TBILD_BITN 8 -#define GPT_TBMR_TBILD_M 0x00000100 -#define GPT_TBMR_TBILD_S 8 -#define GPT_TBMR_TBILD_TOUPDATE 0x00000100 -#define GPT_TBMR_TBILD_CYCLEUPDATE 0x00000000 +#define GPT_TBMR_TBILD 0x00000100 +#define GPT_TBMR_TBILD_BITN 8 +#define GPT_TBMR_TBILD_M 0x00000100 +#define GPT_TBMR_TBILD_S 8 +#define GPT_TBMR_TBILD_TOUPDATE 0x00000100 +#define GPT_TBMR_TBILD_CYCLEUPDATE 0x00000000 // Field: [7] TBSNAPS // @@ -539,12 +539,12 @@ // ENUMs: // EN If Timer B is configured in the periodic mode // DIS Snap-shot mode is disabled. -#define GPT_TBMR_TBSNAPS 0x00000080 -#define GPT_TBMR_TBSNAPS_BITN 7 -#define GPT_TBMR_TBSNAPS_M 0x00000080 -#define GPT_TBMR_TBSNAPS_S 7 -#define GPT_TBMR_TBSNAPS_EN 0x00000080 -#define GPT_TBMR_TBSNAPS_DIS 0x00000000 +#define GPT_TBMR_TBSNAPS 0x00000080 +#define GPT_TBMR_TBSNAPS_BITN 7 +#define GPT_TBMR_TBSNAPS_M 0x00000080 +#define GPT_TBMR_TBSNAPS_S 7 +#define GPT_TBMR_TBSNAPS_EN 0x00000080 +#define GPT_TBMR_TBSNAPS_DIS 0x00000000 // Field: [6] TBWOT // @@ -556,12 +556,12 @@ // in the daisy chain. This function is valid for // one-shot, periodic, and PWM modes // NOWAIT Timer B begins counting as soon as it is enabled. -#define GPT_TBMR_TBWOT 0x00000040 -#define GPT_TBMR_TBWOT_BITN 6 -#define GPT_TBMR_TBWOT_M 0x00000040 -#define GPT_TBMR_TBWOT_S 6 -#define GPT_TBMR_TBWOT_WAIT 0x00000040 -#define GPT_TBMR_TBWOT_NOWAIT 0x00000000 +#define GPT_TBMR_TBWOT 0x00000040 +#define GPT_TBMR_TBWOT_BITN 6 +#define GPT_TBMR_TBWOT_M 0x00000040 +#define GPT_TBMR_TBWOT_S 6 +#define GPT_TBMR_TBWOT_WAIT 0x00000040 +#define GPT_TBMR_TBWOT_NOWAIT 0x00000000 // Field: [5] TBMIE // @@ -573,12 +573,12 @@ // DIS The match interrupt is disabled for match events. // Additionally, output triggers on match events // are prevented. -#define GPT_TBMR_TBMIE 0x00000020 -#define GPT_TBMR_TBMIE_BITN 5 -#define GPT_TBMR_TBMIE_M 0x00000020 -#define GPT_TBMR_TBMIE_S 5 -#define GPT_TBMR_TBMIE_EN 0x00000020 -#define GPT_TBMR_TBMIE_DIS 0x00000000 +#define GPT_TBMR_TBMIE 0x00000020 +#define GPT_TBMR_TBMIE_BITN 5 +#define GPT_TBMR_TBMIE_M 0x00000020 +#define GPT_TBMR_TBMIE_S 5 +#define GPT_TBMR_TBMIE_EN 0x00000020 +#define GPT_TBMR_TBMIE_DIS 0x00000000 // Field: [4] TBCDIR // @@ -587,12 +587,12 @@ // UP The timer counts up. When counting up, the timer // starts from a value of 0x0. // DOWN The timer counts down. -#define GPT_TBMR_TBCDIR 0x00000010 -#define GPT_TBMR_TBCDIR_BITN 4 -#define GPT_TBMR_TBCDIR_M 0x00000010 -#define GPT_TBMR_TBCDIR_S 4 -#define GPT_TBMR_TBCDIR_UP 0x00000010 -#define GPT_TBMR_TBCDIR_DOWN 0x00000000 +#define GPT_TBMR_TBCDIR 0x00000010 +#define GPT_TBMR_TBCDIR_BITN 4 +#define GPT_TBMR_TBCDIR_M 0x00000010 +#define GPT_TBMR_TBCDIR_S 4 +#define GPT_TBMR_TBCDIR_UP 0x00000010 +#define GPT_TBMR_TBCDIR_DOWN 0x00000000 // Field: [3] TBAMS // @@ -603,12 +603,12 @@ // ENUMs: // PWM PWM mode is enabled // CAP_COMP Capture/Compare mode is enabled. -#define GPT_TBMR_TBAMS 0x00000008 -#define GPT_TBMR_TBAMS_BITN 3 -#define GPT_TBMR_TBAMS_M 0x00000008 -#define GPT_TBMR_TBAMS_S 3 -#define GPT_TBMR_TBAMS_PWM 0x00000008 -#define GPT_TBMR_TBAMS_CAP_COMP 0x00000000 +#define GPT_TBMR_TBAMS 0x00000008 +#define GPT_TBMR_TBAMS_BITN 3 +#define GPT_TBMR_TBAMS_M 0x00000008 +#define GPT_TBMR_TBAMS_S 3 +#define GPT_TBMR_TBAMS_PWM 0x00000008 +#define GPT_TBMR_TBAMS_CAP_COMP 0x00000000 // Field: [2] TBCM // @@ -616,12 +616,12 @@ // ENUMs: // EDGTIME Edge-Time mode // EDGCNT Edge-Count mode -#define GPT_TBMR_TBCM 0x00000004 -#define GPT_TBMR_TBCM_BITN 2 -#define GPT_TBMR_TBCM_M 0x00000004 -#define GPT_TBMR_TBCM_S 2 -#define GPT_TBMR_TBCM_EDGTIME 0x00000004 -#define GPT_TBMR_TBCM_EDGCNT 0x00000000 +#define GPT_TBMR_TBCM 0x00000004 +#define GPT_TBMR_TBCM_BITN 2 +#define GPT_TBMR_TBCM_M 0x00000004 +#define GPT_TBMR_TBCM_S 2 +#define GPT_TBMR_TBCM_EDGTIME 0x00000004 +#define GPT_TBMR_TBCM_EDGCNT 0x00000000 // Field: [1:0] TBMR // @@ -637,12 +637,12 @@ // CAPTURE Capture mode // PERIODIC Periodic Timer mode // ONE_SHOT One-Shot Timer mode -#define GPT_TBMR_TBMR_W 2 -#define GPT_TBMR_TBMR_M 0x00000003 -#define GPT_TBMR_TBMR_S 0 -#define GPT_TBMR_TBMR_CAPTURE 0x00000003 -#define GPT_TBMR_TBMR_PERIODIC 0x00000002 -#define GPT_TBMR_TBMR_ONE_SHOT 0x00000001 +#define GPT_TBMR_TBMR_W 2 +#define GPT_TBMR_TBMR_M 0x00000003 +#define GPT_TBMR_TBMR_S 0 +#define GPT_TBMR_TBMR_CAPTURE 0x00000003 +#define GPT_TBMR_TBMR_PERIODIC 0x00000002 +#define GPT_TBMR_TBMR_ONE_SHOT 0x00000001 //***************************************************************************** // @@ -658,12 +658,12 @@ // ENUMs: // INVERTED Inverted // NORMAL Not inverted -#define GPT_CTL_TBPWML 0x00004000 -#define GPT_CTL_TBPWML_BITN 14 -#define GPT_CTL_TBPWML_M 0x00004000 -#define GPT_CTL_TBPWML_S 14 -#define GPT_CTL_TBPWML_INVERTED 0x00004000 -#define GPT_CTL_TBPWML_NORMAL 0x00000000 +#define GPT_CTL_TBPWML 0x00004000 +#define GPT_CTL_TBPWML_BITN 14 +#define GPT_CTL_TBPWML_M 0x00004000 +#define GPT_CTL_TBPWML_S 14 +#define GPT_CTL_TBPWML_INVERTED 0x00004000 +#define GPT_CTL_TBPWML_NORMAL 0x00000000 // Field: [11:10] TBEVENT // @@ -684,12 +684,12 @@ // BOTH Both edges // NEG Negative edge // POS Positive edge -#define GPT_CTL_TBEVENT_W 2 -#define GPT_CTL_TBEVENT_M 0x00000C00 -#define GPT_CTL_TBEVENT_S 10 -#define GPT_CTL_TBEVENT_BOTH 0x00000C00 -#define GPT_CTL_TBEVENT_NEG 0x00000400 -#define GPT_CTL_TBEVENT_POS 0x00000000 +#define GPT_CTL_TBEVENT_W 2 +#define GPT_CTL_TBEVENT_M 0x00000C00 +#define GPT_CTL_TBEVENT_S 10 +#define GPT_CTL_TBEVENT_BOTH 0x00000C00 +#define GPT_CTL_TBEVENT_NEG 0x00000400 +#define GPT_CTL_TBEVENT_POS 0x00000000 // Field: [9] TBSTALL // @@ -699,12 +699,12 @@ // halted by the debugger. // DIS Timer B continues counting while the processor is // halted by the debugger. -#define GPT_CTL_TBSTALL 0x00000200 -#define GPT_CTL_TBSTALL_BITN 9 -#define GPT_CTL_TBSTALL_M 0x00000200 -#define GPT_CTL_TBSTALL_S 9 -#define GPT_CTL_TBSTALL_EN 0x00000200 -#define GPT_CTL_TBSTALL_DIS 0x00000000 +#define GPT_CTL_TBSTALL 0x00000200 +#define GPT_CTL_TBSTALL_BITN 9 +#define GPT_CTL_TBSTALL_M 0x00000200 +#define GPT_CTL_TBSTALL_S 9 +#define GPT_CTL_TBSTALL_EN 0x00000200 +#define GPT_CTL_TBSTALL_DIS 0x00000000 // Field: [8] TBEN // @@ -713,12 +713,12 @@ // EN Timer B is enabled and begins counting or the // capture logic is enabled based on CFG register. // DIS Timer B is disabled. -#define GPT_CTL_TBEN 0x00000100 -#define GPT_CTL_TBEN_BITN 8 -#define GPT_CTL_TBEN_M 0x00000100 -#define GPT_CTL_TBEN_S 8 -#define GPT_CTL_TBEN_EN 0x00000100 -#define GPT_CTL_TBEN_DIS 0x00000000 +#define GPT_CTL_TBEN 0x00000100 +#define GPT_CTL_TBEN_BITN 8 +#define GPT_CTL_TBEN_M 0x00000100 +#define GPT_CTL_TBEN_S 8 +#define GPT_CTL_TBEN_EN 0x00000100 +#define GPT_CTL_TBEN_DIS 0x00000000 // Field: [6] TAPWML // @@ -726,12 +726,12 @@ // ENUMs: // INVERTED Inverted // NORMAL Not inverted -#define GPT_CTL_TAPWML 0x00000040 -#define GPT_CTL_TAPWML_BITN 6 -#define GPT_CTL_TAPWML_M 0x00000040 -#define GPT_CTL_TAPWML_S 6 -#define GPT_CTL_TAPWML_INVERTED 0x00000040 -#define GPT_CTL_TAPWML_NORMAL 0x00000000 +#define GPT_CTL_TAPWML 0x00000040 +#define GPT_CTL_TAPWML_BITN 6 +#define GPT_CTL_TAPWML_M 0x00000040 +#define GPT_CTL_TAPWML_S 6 +#define GPT_CTL_TAPWML_INVERTED 0x00000040 +#define GPT_CTL_TAPWML_NORMAL 0x00000000 // Field: [3:2] TAEVENT // @@ -752,12 +752,12 @@ // BOTH Both edges // NEG Negative edge // POS Positive edge -#define GPT_CTL_TAEVENT_W 2 -#define GPT_CTL_TAEVENT_M 0x0000000C -#define GPT_CTL_TAEVENT_S 2 -#define GPT_CTL_TAEVENT_BOTH 0x0000000C -#define GPT_CTL_TAEVENT_NEG 0x00000004 -#define GPT_CTL_TAEVENT_POS 0x00000000 +#define GPT_CTL_TAEVENT_W 2 +#define GPT_CTL_TAEVENT_M 0x0000000C +#define GPT_CTL_TAEVENT_S 2 +#define GPT_CTL_TAEVENT_BOTH 0x0000000C +#define GPT_CTL_TAEVENT_NEG 0x00000004 +#define GPT_CTL_TAEVENT_POS 0x00000000 // Field: [1] TASTALL // @@ -767,12 +767,12 @@ // halted by the debugger. // DIS Timer A continues counting while the processor is // halted by the debugger. -#define GPT_CTL_TASTALL 0x00000002 -#define GPT_CTL_TASTALL_BITN 1 -#define GPT_CTL_TASTALL_M 0x00000002 -#define GPT_CTL_TASTALL_S 1 -#define GPT_CTL_TASTALL_EN 0x00000002 -#define GPT_CTL_TASTALL_DIS 0x00000000 +#define GPT_CTL_TASTALL 0x00000002 +#define GPT_CTL_TASTALL_BITN 1 +#define GPT_CTL_TASTALL_M 0x00000002 +#define GPT_CTL_TASTALL_S 1 +#define GPT_CTL_TASTALL_EN 0x00000002 +#define GPT_CTL_TASTALL_DIS 0x00000000 // Field: [0] TAEN // @@ -782,12 +782,12 @@ // capture logic is enabled based on the CFG // register. // DIS Timer A is disabled. -#define GPT_CTL_TAEN 0x00000001 -#define GPT_CTL_TAEN_BITN 0 -#define GPT_CTL_TAEN_M 0x00000001 -#define GPT_CTL_TAEN_S 0 -#define GPT_CTL_TAEN_EN 0x00000001 -#define GPT_CTL_TAEN_DIS 0x00000000 +#define GPT_CTL_TAEN 0x00000001 +#define GPT_CTL_TAEN_BITN 0 +#define GPT_CTL_TAEN_M 0x00000001 +#define GPT_CTL_TAEN_S 0 +#define GPT_CTL_TAEN_EN 0x00000001 +#define GPT_CTL_TAEN_DIS 0x00000000 //***************************************************************************** // @@ -803,13 +803,13 @@ // TIMERB A timeout event for Timer B of GPT3 is triggered // TIMERA A timeout event for Timer A of GPT3 is triggered // NOSYNC No Sync. GPT3 is not affected. -#define GPT_SYNC_SYNC3_W 2 -#define GPT_SYNC_SYNC3_M 0x000000C0 -#define GPT_SYNC_SYNC3_S 6 -#define GPT_SYNC_SYNC3_BOTH 0x000000C0 -#define GPT_SYNC_SYNC3_TIMERB 0x00000080 -#define GPT_SYNC_SYNC3_TIMERA 0x00000040 -#define GPT_SYNC_SYNC3_NOSYNC 0x00000000 +#define GPT_SYNC_SYNC3_W 2 +#define GPT_SYNC_SYNC3_M 0x000000C0 +#define GPT_SYNC_SYNC3_S 6 +#define GPT_SYNC_SYNC3_BOTH 0x000000C0 +#define GPT_SYNC_SYNC3_TIMERB 0x00000080 +#define GPT_SYNC_SYNC3_TIMERA 0x00000040 +#define GPT_SYNC_SYNC3_NOSYNC 0x00000000 // Field: [5:4] SYNC2 // @@ -820,13 +820,13 @@ // TIMERB A timeout event for Timer B of GPT2 is triggered // TIMERA A timeout event for Timer A of GPT2 is triggered // NOSYNC No Sync. GPT2 is not affected. -#define GPT_SYNC_SYNC2_W 2 -#define GPT_SYNC_SYNC2_M 0x00000030 -#define GPT_SYNC_SYNC2_S 4 -#define GPT_SYNC_SYNC2_BOTH 0x00000030 -#define GPT_SYNC_SYNC2_TIMERB 0x00000020 -#define GPT_SYNC_SYNC2_TIMERA 0x00000010 -#define GPT_SYNC_SYNC2_NOSYNC 0x00000000 +#define GPT_SYNC_SYNC2_W 2 +#define GPT_SYNC_SYNC2_M 0x00000030 +#define GPT_SYNC_SYNC2_S 4 +#define GPT_SYNC_SYNC2_BOTH 0x00000030 +#define GPT_SYNC_SYNC2_TIMERB 0x00000020 +#define GPT_SYNC_SYNC2_TIMERA 0x00000010 +#define GPT_SYNC_SYNC2_NOSYNC 0x00000000 // Field: [3:2] SYNC1 // @@ -837,13 +837,13 @@ // TIMERB A timeout event for Timer B of GPT1 is triggered // TIMERA A timeout event for Timer A of GPT1 is triggered // NOSYNC No Sync. GPT1 is not affected. -#define GPT_SYNC_SYNC1_W 2 -#define GPT_SYNC_SYNC1_M 0x0000000C -#define GPT_SYNC_SYNC1_S 2 -#define GPT_SYNC_SYNC1_BOTH 0x0000000C -#define GPT_SYNC_SYNC1_TIMERB 0x00000008 -#define GPT_SYNC_SYNC1_TIMERA 0x00000004 -#define GPT_SYNC_SYNC1_NOSYNC 0x00000000 +#define GPT_SYNC_SYNC1_W 2 +#define GPT_SYNC_SYNC1_M 0x0000000C +#define GPT_SYNC_SYNC1_S 2 +#define GPT_SYNC_SYNC1_BOTH 0x0000000C +#define GPT_SYNC_SYNC1_TIMERB 0x00000008 +#define GPT_SYNC_SYNC1_TIMERA 0x00000004 +#define GPT_SYNC_SYNC1_NOSYNC 0x00000000 // Field: [1:0] SYNC0 // @@ -854,13 +854,13 @@ // TIMERB A timeout event for Timer B of GPT0 is triggered // TIMERA A timeout event for Timer A of GPT0 is triggered // NOSYNC No Sync. GPT0 is not affected. -#define GPT_SYNC_SYNC0_W 2 -#define GPT_SYNC_SYNC0_M 0x00000003 -#define GPT_SYNC_SYNC0_S 0 -#define GPT_SYNC_SYNC0_BOTH 0x00000003 -#define GPT_SYNC_SYNC0_TIMERB 0x00000002 -#define GPT_SYNC_SYNC0_TIMERA 0x00000001 -#define GPT_SYNC_SYNC0_NOSYNC 0x00000000 +#define GPT_SYNC_SYNC0_W 2 +#define GPT_SYNC_SYNC0_M 0x00000003 +#define GPT_SYNC_SYNC0_S 0 +#define GPT_SYNC_SYNC0_BOTH 0x00000003 +#define GPT_SYNC_SYNC0_TIMERB 0x00000002 +#define GPT_SYNC_SYNC0_TIMERA 0x00000001 +#define GPT_SYNC_SYNC0_NOSYNC 0x00000000 //***************************************************************************** // @@ -874,12 +874,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_DMABIM 0x00002000 -#define GPT_IMR_DMABIM_BITN 13 -#define GPT_IMR_DMABIM_M 0x00002000 -#define GPT_IMR_DMABIM_S 13 -#define GPT_IMR_DMABIM_EN 0x00002000 -#define GPT_IMR_DMABIM_DIS 0x00000000 +#define GPT_IMR_DMABIM 0x00002000 +#define GPT_IMR_DMABIM_BITN 13 +#define GPT_IMR_DMABIM_M 0x00002000 +#define GPT_IMR_DMABIM_S 13 +#define GPT_IMR_DMABIM_EN 0x00002000 +#define GPT_IMR_DMABIM_DIS 0x00000000 // Field: [11] TBMIM // @@ -887,12 +887,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_TBMIM 0x00000800 -#define GPT_IMR_TBMIM_BITN 11 -#define GPT_IMR_TBMIM_M 0x00000800 -#define GPT_IMR_TBMIM_S 11 -#define GPT_IMR_TBMIM_EN 0x00000800 -#define GPT_IMR_TBMIM_DIS 0x00000000 +#define GPT_IMR_TBMIM 0x00000800 +#define GPT_IMR_TBMIM_BITN 11 +#define GPT_IMR_TBMIM_M 0x00000800 +#define GPT_IMR_TBMIM_S 11 +#define GPT_IMR_TBMIM_EN 0x00000800 +#define GPT_IMR_TBMIM_DIS 0x00000000 // Field: [10] CBEIM // @@ -900,12 +900,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_CBEIM 0x00000400 -#define GPT_IMR_CBEIM_BITN 10 -#define GPT_IMR_CBEIM_M 0x00000400 -#define GPT_IMR_CBEIM_S 10 -#define GPT_IMR_CBEIM_EN 0x00000400 -#define GPT_IMR_CBEIM_DIS 0x00000000 +#define GPT_IMR_CBEIM 0x00000400 +#define GPT_IMR_CBEIM_BITN 10 +#define GPT_IMR_CBEIM_M 0x00000400 +#define GPT_IMR_CBEIM_S 10 +#define GPT_IMR_CBEIM_EN 0x00000400 +#define GPT_IMR_CBEIM_DIS 0x00000000 // Field: [9] CBMIM // @@ -913,12 +913,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_CBMIM 0x00000200 -#define GPT_IMR_CBMIM_BITN 9 -#define GPT_IMR_CBMIM_M 0x00000200 -#define GPT_IMR_CBMIM_S 9 -#define GPT_IMR_CBMIM_EN 0x00000200 -#define GPT_IMR_CBMIM_DIS 0x00000000 +#define GPT_IMR_CBMIM 0x00000200 +#define GPT_IMR_CBMIM_BITN 9 +#define GPT_IMR_CBMIM_M 0x00000200 +#define GPT_IMR_CBMIM_S 9 +#define GPT_IMR_CBMIM_EN 0x00000200 +#define GPT_IMR_CBMIM_DIS 0x00000000 // Field: [8] TBTOIM // @@ -927,12 +927,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_TBTOIM 0x00000100 -#define GPT_IMR_TBTOIM_BITN 8 -#define GPT_IMR_TBTOIM_M 0x00000100 -#define GPT_IMR_TBTOIM_S 8 -#define GPT_IMR_TBTOIM_EN 0x00000100 -#define GPT_IMR_TBTOIM_DIS 0x00000000 +#define GPT_IMR_TBTOIM 0x00000100 +#define GPT_IMR_TBTOIM_BITN 8 +#define GPT_IMR_TBTOIM_M 0x00000100 +#define GPT_IMR_TBTOIM_S 8 +#define GPT_IMR_TBTOIM_EN 0x00000100 +#define GPT_IMR_TBTOIM_DIS 0x00000000 // Field: [5] DMAAIM // @@ -941,12 +941,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_DMAAIM 0x00000020 -#define GPT_IMR_DMAAIM_BITN 5 -#define GPT_IMR_DMAAIM_M 0x00000020 -#define GPT_IMR_DMAAIM_S 5 -#define GPT_IMR_DMAAIM_EN 0x00000020 -#define GPT_IMR_DMAAIM_DIS 0x00000000 +#define GPT_IMR_DMAAIM 0x00000020 +#define GPT_IMR_DMAAIM_BITN 5 +#define GPT_IMR_DMAAIM_M 0x00000020 +#define GPT_IMR_DMAAIM_S 5 +#define GPT_IMR_DMAAIM_EN 0x00000020 +#define GPT_IMR_DMAAIM_DIS 0x00000000 // Field: [4] TAMIM // @@ -954,12 +954,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_TAMIM 0x00000010 -#define GPT_IMR_TAMIM_BITN 4 -#define GPT_IMR_TAMIM_M 0x00000010 -#define GPT_IMR_TAMIM_S 4 -#define GPT_IMR_TAMIM_EN 0x00000010 -#define GPT_IMR_TAMIM_DIS 0x00000000 +#define GPT_IMR_TAMIM 0x00000010 +#define GPT_IMR_TAMIM_BITN 4 +#define GPT_IMR_TAMIM_M 0x00000010 +#define GPT_IMR_TAMIM_S 4 +#define GPT_IMR_TAMIM_EN 0x00000010 +#define GPT_IMR_TAMIM_DIS 0x00000000 // Field: [2] CAEIM // @@ -967,12 +967,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_CAEIM 0x00000004 -#define GPT_IMR_CAEIM_BITN 2 -#define GPT_IMR_CAEIM_M 0x00000004 -#define GPT_IMR_CAEIM_S 2 -#define GPT_IMR_CAEIM_EN 0x00000004 -#define GPT_IMR_CAEIM_DIS 0x00000000 +#define GPT_IMR_CAEIM 0x00000004 +#define GPT_IMR_CAEIM_BITN 2 +#define GPT_IMR_CAEIM_M 0x00000004 +#define GPT_IMR_CAEIM_S 2 +#define GPT_IMR_CAEIM_EN 0x00000004 +#define GPT_IMR_CAEIM_DIS 0x00000000 // Field: [1] CAMIM // @@ -980,12 +980,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_CAMIM 0x00000002 -#define GPT_IMR_CAMIM_BITN 1 -#define GPT_IMR_CAMIM_M 0x00000002 -#define GPT_IMR_CAMIM_S 1 -#define GPT_IMR_CAMIM_EN 0x00000002 -#define GPT_IMR_CAMIM_DIS 0x00000000 +#define GPT_IMR_CAMIM 0x00000002 +#define GPT_IMR_CAMIM_BITN 1 +#define GPT_IMR_CAMIM_M 0x00000002 +#define GPT_IMR_CAMIM_S 1 +#define GPT_IMR_CAMIM_EN 0x00000002 +#define GPT_IMR_CAMIM_DIS 0x00000000 // Field: [0] TATOIM // @@ -994,12 +994,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_TATOIM 0x00000001 -#define GPT_IMR_TATOIM_BITN 0 -#define GPT_IMR_TATOIM_M 0x00000001 -#define GPT_IMR_TATOIM_S 0 -#define GPT_IMR_TATOIM_EN 0x00000001 -#define GPT_IMR_TATOIM_DIS 0x00000000 +#define GPT_IMR_TATOIM 0x00000001 +#define GPT_IMR_TATOIM_BITN 0 +#define GPT_IMR_TATOIM_M 0x00000001 +#define GPT_IMR_TATOIM_S 0 +#define GPT_IMR_TATOIM_EN 0x00000001 +#define GPT_IMR_TATOIM_DIS 0x00000000 //***************************************************************************** // @@ -1012,10 +1012,10 @@ // // 0: Transfer has not completed // 1: Transfer has completed -#define GPT_RIS_DMABRIS 0x00002000 -#define GPT_RIS_DMABRIS_BITN 13 -#define GPT_RIS_DMABRIS_M 0x00002000 -#define GPT_RIS_DMABRIS_S 13 +#define GPT_RIS_DMABRIS 0x00002000 +#define GPT_RIS_DMABRIS_BITN 13 +#define GPT_RIS_DMABRIS_M 0x00002000 +#define GPT_RIS_DMABRIS_S 13 // Field: [11] TBMRIS // @@ -1026,10 +1026,10 @@ // // TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR // have been reached when configured in one-shot or periodic mode. -#define GPT_RIS_TBMRIS 0x00000800 -#define GPT_RIS_TBMRIS_BITN 11 -#define GPT_RIS_TBMRIS_M 0x00000800 -#define GPT_RIS_TBMRIS_S 11 +#define GPT_RIS_TBMRIS 0x00000800 +#define GPT_RIS_TBMRIS_BITN 11 +#define GPT_RIS_TBMRIS_M 0x00000800 +#define GPT_RIS_TBMRIS_S 11 // Field: [10] CBERIS // @@ -1040,10 +1040,10 @@ // // This interrupt asserts when the subtimer is configured in Input Edge-Time // mode -#define GPT_RIS_CBERIS 0x00000400 -#define GPT_RIS_CBERIS_BITN 10 -#define GPT_RIS_CBERIS_M 0x00000400 -#define GPT_RIS_CBERIS_S 10 +#define GPT_RIS_CBERIS 0x00000400 +#define GPT_RIS_CBERIS_BITN 10 +#define GPT_RIS_CBERIS_M 0x00000400 +#define GPT_RIS_CBERIS_S 10 // Field: [9] CBMRIS // @@ -1056,10 +1056,10 @@ // when configured in Input Edge-Time mode. // // This bit is cleared by writing a 1 to the ICLR.CBMCINT bit. -#define GPT_RIS_CBMRIS 0x00000200 -#define GPT_RIS_CBMRIS_BITN 9 -#define GPT_RIS_CBMRIS_M 0x00000200 -#define GPT_RIS_CBMRIS_S 9 +#define GPT_RIS_CBMRIS 0x00000200 +#define GPT_RIS_CBMRIS_BITN 9 +#define GPT_RIS_CBMRIS_M 0x00000200 +#define GPT_RIS_CBMRIS_S 9 // Field: [8] TBTORIS // @@ -1071,10 +1071,10 @@ // This interrupt is asserted when a one-shot or periodic mode timer reaches // its count limit. The count limit is 0 or the value loaded into TBILR, // depending on the count direction. -#define GPT_RIS_TBTORIS 0x00000100 -#define GPT_RIS_TBTORIS_BITN 8 -#define GPT_RIS_TBTORIS_M 0x00000100 -#define GPT_RIS_TBTORIS_S 8 +#define GPT_RIS_TBTORIS 0x00000100 +#define GPT_RIS_TBTORIS_BITN 8 +#define GPT_RIS_TBTORIS_M 0x00000100 +#define GPT_RIS_TBTORIS_S 8 // Field: [5] DMAARIS // @@ -1082,10 +1082,10 @@ // // 0: Transfer has not completed // 1: Transfer has completed -#define GPT_RIS_DMAARIS 0x00000020 -#define GPT_RIS_DMAARIS_BITN 5 -#define GPT_RIS_DMAARIS_M 0x00000020 -#define GPT_RIS_DMAARIS_S 5 +#define GPT_RIS_DMAARIS 0x00000020 +#define GPT_RIS_DMAARIS_BITN 5 +#define GPT_RIS_DMAARIS_M 0x00000020 +#define GPT_RIS_DMAARIS_S 5 // Field: [4] TAMRIS // @@ -1096,10 +1096,10 @@ // // TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR // have been reached when configured in one-shot or periodic mode. -#define GPT_RIS_TAMRIS 0x00000010 -#define GPT_RIS_TAMRIS_BITN 4 -#define GPT_RIS_TAMRIS_M 0x00000010 -#define GPT_RIS_TAMRIS_S 4 +#define GPT_RIS_TAMRIS 0x00000010 +#define GPT_RIS_TAMRIS_BITN 4 +#define GPT_RIS_TAMRIS_M 0x00000010 +#define GPT_RIS_TAMRIS_S 4 // Field: [2] CAERIS // @@ -1110,10 +1110,10 @@ // // This interrupt asserts when the subtimer is configured in Input Edge-Time // mode -#define GPT_RIS_CAERIS 0x00000004 -#define GPT_RIS_CAERIS_BITN 2 -#define GPT_RIS_CAERIS_M 0x00000004 -#define GPT_RIS_CAERIS_S 2 +#define GPT_RIS_CAERIS 0x00000004 +#define GPT_RIS_CAERIS_BITN 2 +#define GPT_RIS_CAERIS_M 0x00000004 +#define GPT_RIS_CAERIS_S 2 // Field: [1] CAMRIS // @@ -1126,10 +1126,10 @@ // when configured in Input Edge-Time mode. // // This bit is cleared by writing a 1 to the ICLR.CAMCINT bit. -#define GPT_RIS_CAMRIS 0x00000002 -#define GPT_RIS_CAMRIS_BITN 1 -#define GPT_RIS_CAMRIS_M 0x00000002 -#define GPT_RIS_CAMRIS_S 1 +#define GPT_RIS_CAMRIS 0x00000002 +#define GPT_RIS_CAMRIS_BITN 1 +#define GPT_RIS_CAMRIS_M 0x00000002 +#define GPT_RIS_CAMRIS_S 1 // Field: [0] TATORIS // @@ -1141,10 +1141,10 @@ // This interrupt is asserted when a one-shot or periodic mode timer reaches // its count limit. The count limit is 0 or the value loaded into TAILR, // depending on the count direction. -#define GPT_RIS_TATORIS 0x00000001 -#define GPT_RIS_TATORIS_BITN 0 -#define GPT_RIS_TATORIS_M 0x00000001 -#define GPT_RIS_TATORIS_S 0 +#define GPT_RIS_TATORIS 0x00000001 +#define GPT_RIS_TATORIS_BITN 0 +#define GPT_RIS_TATORIS_M 0x00000001 +#define GPT_RIS_TATORIS_S 0 //***************************************************************************** // @@ -1155,91 +1155,91 @@ // // 0: No interrupt or interrupt not enabled // 1: RIS.DMABRIS = 1 && IMR.DMABIM = 1 -#define GPT_MIS_DMABMIS 0x00002000 -#define GPT_MIS_DMABMIS_BITN 13 -#define GPT_MIS_DMABMIS_M 0x00002000 -#define GPT_MIS_DMABMIS_S 13 +#define GPT_MIS_DMABMIS 0x00002000 +#define GPT_MIS_DMABMIS_BITN 13 +#define GPT_MIS_DMABMIS_M 0x00002000 +#define GPT_MIS_DMABMIS_S 13 // Field: [11] TBMMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.TBMRIS = 1 && IMR.TBMIM = 1 -#define GPT_MIS_TBMMIS 0x00000800 -#define GPT_MIS_TBMMIS_BITN 11 -#define GPT_MIS_TBMMIS_M 0x00000800 -#define GPT_MIS_TBMMIS_S 11 +#define GPT_MIS_TBMMIS 0x00000800 +#define GPT_MIS_TBMMIS_BITN 11 +#define GPT_MIS_TBMMIS_M 0x00000800 +#define GPT_MIS_TBMMIS_S 11 // Field: [10] CBEMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.CBERIS = 1 && IMR.CBEIM = 1 -#define GPT_MIS_CBEMIS 0x00000400 -#define GPT_MIS_CBEMIS_BITN 10 -#define GPT_MIS_CBEMIS_M 0x00000400 -#define GPT_MIS_CBEMIS_S 10 +#define GPT_MIS_CBEMIS 0x00000400 +#define GPT_MIS_CBEMIS_BITN 10 +#define GPT_MIS_CBEMIS_M 0x00000400 +#define GPT_MIS_CBEMIS_S 10 // Field: [9] CBMMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.CBMRIS = 1 && IMR.CBMIM = 1 -#define GPT_MIS_CBMMIS 0x00000200 -#define GPT_MIS_CBMMIS_BITN 9 -#define GPT_MIS_CBMMIS_M 0x00000200 -#define GPT_MIS_CBMMIS_S 9 +#define GPT_MIS_CBMMIS 0x00000200 +#define GPT_MIS_CBMMIS_BITN 9 +#define GPT_MIS_CBMMIS_M 0x00000200 +#define GPT_MIS_CBMMIS_S 9 // Field: [8] TBTOMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1 -#define GPT_MIS_TBTOMIS 0x00000100 -#define GPT_MIS_TBTOMIS_BITN 8 -#define GPT_MIS_TBTOMIS_M 0x00000100 -#define GPT_MIS_TBTOMIS_S 8 +#define GPT_MIS_TBTOMIS 0x00000100 +#define GPT_MIS_TBTOMIS_BITN 8 +#define GPT_MIS_TBTOMIS_M 0x00000100 +#define GPT_MIS_TBTOMIS_S 8 // Field: [5] DMAAMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1 -#define GPT_MIS_DMAAMIS 0x00000020 -#define GPT_MIS_DMAAMIS_BITN 5 -#define GPT_MIS_DMAAMIS_M 0x00000020 -#define GPT_MIS_DMAAMIS_S 5 +#define GPT_MIS_DMAAMIS 0x00000020 +#define GPT_MIS_DMAAMIS_BITN 5 +#define GPT_MIS_DMAAMIS_M 0x00000020 +#define GPT_MIS_DMAAMIS_S 5 // Field: [4] TAMMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.TAMRIS = 1 && IMR.TAMIM = 1 -#define GPT_MIS_TAMMIS 0x00000010 -#define GPT_MIS_TAMMIS_BITN 4 -#define GPT_MIS_TAMMIS_M 0x00000010 -#define GPT_MIS_TAMMIS_S 4 +#define GPT_MIS_TAMMIS 0x00000010 +#define GPT_MIS_TAMMIS_BITN 4 +#define GPT_MIS_TAMMIS_M 0x00000010 +#define GPT_MIS_TAMMIS_S 4 // Field: [2] CAEMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.CAERIS = 1 && IMR.CAEIM = 1 -#define GPT_MIS_CAEMIS 0x00000004 -#define GPT_MIS_CAEMIS_BITN 2 -#define GPT_MIS_CAEMIS_M 0x00000004 -#define GPT_MIS_CAEMIS_S 2 +#define GPT_MIS_CAEMIS 0x00000004 +#define GPT_MIS_CAEMIS_BITN 2 +#define GPT_MIS_CAEMIS_M 0x00000004 +#define GPT_MIS_CAEMIS_S 2 // Field: [1] CAMMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.CAMRIS = 1 && IMR.CAMIM = 1 -#define GPT_MIS_CAMMIS 0x00000002 -#define GPT_MIS_CAMMIS_BITN 1 -#define GPT_MIS_CAMMIS_M 0x00000002 -#define GPT_MIS_CAMMIS_S 1 +#define GPT_MIS_CAMMIS 0x00000002 +#define GPT_MIS_CAMMIS_BITN 1 +#define GPT_MIS_CAMMIS_M 0x00000002 +#define GPT_MIS_CAMMIS_S 1 // Field: [0] TATOMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.TATORIS = 1 && IMR.TATOIM = 1 -#define GPT_MIS_TATOMIS 0x00000001 -#define GPT_MIS_TATOMIS_BITN 0 -#define GPT_MIS_TATOMIS_M 0x00000001 -#define GPT_MIS_TATOMIS_S 0 +#define GPT_MIS_TATOMIS 0x00000001 +#define GPT_MIS_TATOMIS_BITN 0 +#define GPT_MIS_TATOMIS_M 0x00000001 +#define GPT_MIS_TATOMIS_S 0 //***************************************************************************** // @@ -1250,91 +1250,91 @@ // // 0: Do nothing. // 1: Clear RIS.DMABRIS and MIS.DMABMIS -#define GPT_ICLR_DMABINT 0x00002000 -#define GPT_ICLR_DMABINT_BITN 13 -#define GPT_ICLR_DMABINT_M 0x00002000 -#define GPT_ICLR_DMABINT_S 13 +#define GPT_ICLR_DMABINT 0x00002000 +#define GPT_ICLR_DMABINT_BITN 13 +#define GPT_ICLR_DMABINT_M 0x00002000 +#define GPT_ICLR_DMABINT_S 13 // Field: [11] TBMCINT // // 0: Do nothing. // 1: Clear RIS.TBMRIS and MIS.TBMMIS -#define GPT_ICLR_TBMCINT 0x00000800 -#define GPT_ICLR_TBMCINT_BITN 11 -#define GPT_ICLR_TBMCINT_M 0x00000800 -#define GPT_ICLR_TBMCINT_S 11 +#define GPT_ICLR_TBMCINT 0x00000800 +#define GPT_ICLR_TBMCINT_BITN 11 +#define GPT_ICLR_TBMCINT_M 0x00000800 +#define GPT_ICLR_TBMCINT_S 11 // Field: [10] CBECINT // // 0: Do nothing. // 1: Clear RIS.CBERIS and MIS.CBEMIS -#define GPT_ICLR_CBECINT 0x00000400 -#define GPT_ICLR_CBECINT_BITN 10 -#define GPT_ICLR_CBECINT_M 0x00000400 -#define GPT_ICLR_CBECINT_S 10 +#define GPT_ICLR_CBECINT 0x00000400 +#define GPT_ICLR_CBECINT_BITN 10 +#define GPT_ICLR_CBECINT_M 0x00000400 +#define GPT_ICLR_CBECINT_S 10 // Field: [9] CBMCINT // // 0: Do nothing. // 1: Clear RIS.CBMRIS and MIS.CBMMIS -#define GPT_ICLR_CBMCINT 0x00000200 -#define GPT_ICLR_CBMCINT_BITN 9 -#define GPT_ICLR_CBMCINT_M 0x00000200 -#define GPT_ICLR_CBMCINT_S 9 +#define GPT_ICLR_CBMCINT 0x00000200 +#define GPT_ICLR_CBMCINT_BITN 9 +#define GPT_ICLR_CBMCINT_M 0x00000200 +#define GPT_ICLR_CBMCINT_S 9 // Field: [8] TBTOCINT // // 0: Do nothing. // 1: Clear RIS.TBTORIS and MIS.TBTOMIS -#define GPT_ICLR_TBTOCINT 0x00000100 -#define GPT_ICLR_TBTOCINT_BITN 8 -#define GPT_ICLR_TBTOCINT_M 0x00000100 -#define GPT_ICLR_TBTOCINT_S 8 +#define GPT_ICLR_TBTOCINT 0x00000100 +#define GPT_ICLR_TBTOCINT_BITN 8 +#define GPT_ICLR_TBTOCINT_M 0x00000100 +#define GPT_ICLR_TBTOCINT_S 8 // Field: [5] DMAAINT // // 0: Do nothing. // 1: Clear RIS.DMAARIS and MIS.DMAAMIS -#define GPT_ICLR_DMAAINT 0x00000020 -#define GPT_ICLR_DMAAINT_BITN 5 -#define GPT_ICLR_DMAAINT_M 0x00000020 -#define GPT_ICLR_DMAAINT_S 5 +#define GPT_ICLR_DMAAINT 0x00000020 +#define GPT_ICLR_DMAAINT_BITN 5 +#define GPT_ICLR_DMAAINT_M 0x00000020 +#define GPT_ICLR_DMAAINT_S 5 // Field: [4] TAMCINT // // 0: Do nothing. // 1: Clear RIS.TAMRIS and MIS.TAMMIS -#define GPT_ICLR_TAMCINT 0x00000010 -#define GPT_ICLR_TAMCINT_BITN 4 -#define GPT_ICLR_TAMCINT_M 0x00000010 -#define GPT_ICLR_TAMCINT_S 4 +#define GPT_ICLR_TAMCINT 0x00000010 +#define GPT_ICLR_TAMCINT_BITN 4 +#define GPT_ICLR_TAMCINT_M 0x00000010 +#define GPT_ICLR_TAMCINT_S 4 // Field: [2] CAECINT // // 0: Do nothing. // 1: Clear RIS.CAERIS and MIS.CAEMIS -#define GPT_ICLR_CAECINT 0x00000004 -#define GPT_ICLR_CAECINT_BITN 2 -#define GPT_ICLR_CAECINT_M 0x00000004 -#define GPT_ICLR_CAECINT_S 2 +#define GPT_ICLR_CAECINT 0x00000004 +#define GPT_ICLR_CAECINT_BITN 2 +#define GPT_ICLR_CAECINT_M 0x00000004 +#define GPT_ICLR_CAECINT_S 2 // Field: [1] CAMCINT // // 0: Do nothing. // 1: Clear RIS.CAMRIS and MIS.CAMMIS -#define GPT_ICLR_CAMCINT 0x00000002 -#define GPT_ICLR_CAMCINT_BITN 1 -#define GPT_ICLR_CAMCINT_M 0x00000002 -#define GPT_ICLR_CAMCINT_S 1 +#define GPT_ICLR_CAMCINT 0x00000002 +#define GPT_ICLR_CAMCINT_BITN 1 +#define GPT_ICLR_CAMCINT_M 0x00000002 +#define GPT_ICLR_CAMCINT_S 1 // Field: [0] TATOCINT // // 0: Do nothing. // 1: Clear RIS.TATORIS and MIS.TATOMIS -#define GPT_ICLR_TATOCINT 0x00000001 -#define GPT_ICLR_TATOCINT_BITN 0 -#define GPT_ICLR_TATOCINT_M 0x00000001 -#define GPT_ICLR_TATOCINT_S 0 +#define GPT_ICLR_TATOCINT 0x00000001 +#define GPT_ICLR_TATOCINT_BITN 0 +#define GPT_ICLR_TATOCINT_M 0x00000001 +#define GPT_ICLR_TATOCINT_S 0 //***************************************************************************** // @@ -1347,9 +1347,9 @@ // // Writing this field loads the counter for Timer A. A read returns the current // value of TAILR. -#define GPT_TAILR_TAILR_W 32 -#define GPT_TAILR_TAILR_M 0xFFFFFFFF -#define GPT_TAILR_TAILR_S 0 +#define GPT_TAILR_TAILR_W 32 +#define GPT_TAILR_TAILR_M 0xFFFFFFFF +#define GPT_TAILR_TAILR_S 0 //***************************************************************************** // @@ -1362,9 +1362,9 @@ // // Writing this field loads the counter for Timer B. A read returns the current // value of TBILR. -#define GPT_TBILR_TBILR_W 32 -#define GPT_TBILR_TBILR_M 0xFFFFFFFF -#define GPT_TBILR_TBILR_S 0 +#define GPT_TBILR_TBILR_W 32 +#define GPT_TBILR_TBILR_M 0xFFFFFFFF +#define GPT_TBILR_TBILR_S 0 //***************************************************************************** // @@ -1374,9 +1374,9 @@ // Field: [31:0] TAMATCHR // // GPT Timer A Match Register -#define GPT_TAMATCHR_TAMATCHR_W 32 -#define GPT_TAMATCHR_TAMATCHR_M 0xFFFFFFFF -#define GPT_TAMATCHR_TAMATCHR_S 0 +#define GPT_TAMATCHR_TAMATCHR_W 32 +#define GPT_TAMATCHR_TAMATCHR_M 0xFFFFFFFF +#define GPT_TAMATCHR_TAMATCHR_S 0 //***************************************************************************** // @@ -1386,9 +1386,9 @@ // Field: [15:0] TBMATCHR // // GPT Timer B Match Register -#define GPT_TBMATCHR_TBMATCHR_W 16 -#define GPT_TBMATCHR_TBMATCHR_M 0x0000FFFF -#define GPT_TBMATCHR_TBMATCHR_S 0 +#define GPT_TBMATCHR_TBMATCHR_W 16 +#define GPT_TBMATCHR_TBMATCHR_M 0x0000FFFF +#define GPT_TBMATCHR_TBMATCHR_S 0 //***************************************************************************** // @@ -1406,9 +1406,9 @@ // 2: Prescaler ratio = 3 // ... // 255: Prescaler ratio = 256 -#define GPT_TAPR_TAPSR_W 8 -#define GPT_TAPR_TAPSR_M 0x000000FF -#define GPT_TAPR_TAPSR_S 0 +#define GPT_TAPR_TAPSR_W 8 +#define GPT_TAPR_TAPSR_M 0x000000FF +#define GPT_TAPR_TAPSR_S 0 //***************************************************************************** // @@ -1426,9 +1426,9 @@ // 2: Prescaler ratio = 3 // ... // 255: Prescaler ratio = 256 -#define GPT_TBPR_TBPSR_W 8 -#define GPT_TBPR_TBPSR_M 0x000000FF -#define GPT_TBPR_TBPSR_S 0 +#define GPT_TBPR_TBPSR_W 8 +#define GPT_TBPR_TBPSR_M 0x000000FF +#define GPT_TBPR_TBPSR_S 0 //***************************************************************************** // @@ -1438,9 +1438,9 @@ // Field: [7:0] TAPSMR // // GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16. -#define GPT_TAPMR_TAPSMR_W 8 -#define GPT_TAPMR_TAPSMR_M 0x000000FF -#define GPT_TAPMR_TAPSMR_S 0 +#define GPT_TAPMR_TAPSMR_W 8 +#define GPT_TAPMR_TAPSMR_M 0x000000FF +#define GPT_TAPMR_TAPSMR_S 0 //***************************************************************************** // @@ -1451,9 +1451,9 @@ // // GPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits // 23 to 16. -#define GPT_TBPMR_TBPSMR_W 8 -#define GPT_TBPMR_TBPSMR_M 0x000000FF -#define GPT_TBPMR_TBPSMR_S 0 +#define GPT_TBPMR_TBPSMR_W 8 +#define GPT_TBPMR_TBPSMR_M 0x000000FF +#define GPT_TBPMR_TBPSMR_S 0 //***************************************************************************** // @@ -1473,9 +1473,9 @@ // In the Input Edge Count Mode, this register contains the number of edges // that have occurred. In the Input Edge Time mode, this register contains the // time at which the last edge event took place. -#define GPT_TAR_TAR_W 32 -#define GPT_TAR_TAR_M 0xFFFFFFFF -#define GPT_TAR_TAR_S 0 +#define GPT_TAR_TAR_W 32 +#define GPT_TAR_TAR_M 0xFFFFFFFF +#define GPT_TAR_TAR_S 0 //***************************************************************************** // @@ -1495,9 +1495,9 @@ // In the Input Edge Count Mode, this register contains the number of edges // that have occurred. In the Input Edge Time mode, this register contains the // time at which the last edge event took place. -#define GPT_TBR_TBR_W 32 -#define GPT_TBR_TBR_M 0xFFFFFFFF -#define GPT_TBR_TBR_S 0 +#define GPT_TBR_TBR_W 32 +#define GPT_TBR_TBR_M 0xFFFFFFFF +#define GPT_TBR_TBR_S 0 //***************************************************************************** // @@ -1513,9 +1513,9 @@ // Note: In 16-bit mode, only the lower 16-bits of this // register can be written with a new value. Writes to the prescaler bits have // no effect -#define GPT_TAV_TAV_W 32 -#define GPT_TAV_TAV_M 0xFFFFFFFF -#define GPT_TAV_TAV_S 0 +#define GPT_TAV_TAV_W 32 +#define GPT_TAV_TAV_M 0xFFFFFFFF +#define GPT_TAV_TAV_S 0 //***************************************************************************** // @@ -1531,9 +1531,9 @@ // Note: In 16-bit mode, only the lower 16-bits of this // register can be written with a new value. Writes to the prescaler bits have // no effect -#define GPT_TBV_TBV_W 32 -#define GPT_TBV_TBV_M 0xFFFFFFFF -#define GPT_TBV_TBV_S 0 +#define GPT_TBV_TBV_W 32 +#define GPT_TBV_TBV_M 0xFFFFFFFF +#define GPT_TBV_TBV_S 0 //***************************************************************************** // @@ -1543,9 +1543,9 @@ // Field: [7:0] PSS // // GPT Timer A Pre-scaler -#define GPT_TAPS_PSS_W 8 -#define GPT_TAPS_PSS_M 0x000000FF -#define GPT_TAPS_PSS_S 0 +#define GPT_TAPS_PSS_W 8 +#define GPT_TAPS_PSS_M 0x000000FF +#define GPT_TAPS_PSS_S 0 //***************************************************************************** // @@ -1555,9 +1555,9 @@ // Field: [7:0] PSS // // GPT Timer B Pre-scaler -#define GPT_TBPS_PSS_W 8 -#define GPT_TBPS_PSS_M 0x000000FF -#define GPT_TBPS_PSS_S 0 +#define GPT_TBPS_PSS_W 8 +#define GPT_TBPS_PSS_M 0x000000FF +#define GPT_TBPS_PSS_S 0 //***************************************************************************** // @@ -1567,9 +1567,9 @@ // Field: [7:0] PSV // // GPT Timer A Pre-scaler Value -#define GPT_TAPV_PSV_W 8 -#define GPT_TAPV_PSV_M 0x000000FF -#define GPT_TAPV_PSV_S 0 +#define GPT_TAPV_PSV_W 8 +#define GPT_TAPV_PSV_M 0x000000FF +#define GPT_TAPV_PSV_S 0 //***************************************************************************** // @@ -1579,9 +1579,9 @@ // Field: [7:0] PSV // // GPT Timer B Pre-scaler Value -#define GPT_TBPV_PSV_W 8 -#define GPT_TBPV_PSV_M 0x000000FF -#define GPT_TBPV_PSV_S 0 +#define GPT_TBPV_PSV_W 8 +#define GPT_TBPV_PSV_M 0x000000FF +#define GPT_TBPV_PSV_S 0 //***************************************************************************** // @@ -1591,66 +1591,66 @@ // Field: [11] TBMDMAEN // // GPT Timer B Match DMA Trigger Enable -#define GPT_DMAEV_TBMDMAEN 0x00000800 -#define GPT_DMAEV_TBMDMAEN_BITN 11 -#define GPT_DMAEV_TBMDMAEN_M 0x00000800 -#define GPT_DMAEV_TBMDMAEN_S 11 +#define GPT_DMAEV_TBMDMAEN 0x00000800 +#define GPT_DMAEV_TBMDMAEN_BITN 11 +#define GPT_DMAEV_TBMDMAEN_M 0x00000800 +#define GPT_DMAEV_TBMDMAEN_S 11 // Field: [10] CBEDMAEN // // GPT Timer B Capture Event DMA Trigger Enable -#define GPT_DMAEV_CBEDMAEN 0x00000400 -#define GPT_DMAEV_CBEDMAEN_BITN 10 -#define GPT_DMAEV_CBEDMAEN_M 0x00000400 -#define GPT_DMAEV_CBEDMAEN_S 10 +#define GPT_DMAEV_CBEDMAEN 0x00000400 +#define GPT_DMAEV_CBEDMAEN_BITN 10 +#define GPT_DMAEV_CBEDMAEN_M 0x00000400 +#define GPT_DMAEV_CBEDMAEN_S 10 // Field: [9] CBMDMAEN // // GPT Timer B Capture Match DMA Trigger Enable -#define GPT_DMAEV_CBMDMAEN 0x00000200 -#define GPT_DMAEV_CBMDMAEN_BITN 9 -#define GPT_DMAEV_CBMDMAEN_M 0x00000200 -#define GPT_DMAEV_CBMDMAEN_S 9 +#define GPT_DMAEV_CBMDMAEN 0x00000200 +#define GPT_DMAEV_CBMDMAEN_BITN 9 +#define GPT_DMAEV_CBMDMAEN_M 0x00000200 +#define GPT_DMAEV_CBMDMAEN_S 9 // Field: [8] TBTODMAEN // // GPT Timer B Time-Out DMA Trigger Enable -#define GPT_DMAEV_TBTODMAEN 0x00000100 -#define GPT_DMAEV_TBTODMAEN_BITN 8 -#define GPT_DMAEV_TBTODMAEN_M 0x00000100 -#define GPT_DMAEV_TBTODMAEN_S 8 +#define GPT_DMAEV_TBTODMAEN 0x00000100 +#define GPT_DMAEV_TBTODMAEN_BITN 8 +#define GPT_DMAEV_TBTODMAEN_M 0x00000100 +#define GPT_DMAEV_TBTODMAEN_S 8 // Field: [4] TAMDMAEN // // GPT Timer A Match DMA Trigger Enable -#define GPT_DMAEV_TAMDMAEN 0x00000010 -#define GPT_DMAEV_TAMDMAEN_BITN 4 -#define GPT_DMAEV_TAMDMAEN_M 0x00000010 -#define GPT_DMAEV_TAMDMAEN_S 4 +#define GPT_DMAEV_TAMDMAEN 0x00000010 +#define GPT_DMAEV_TAMDMAEN_BITN 4 +#define GPT_DMAEV_TAMDMAEN_M 0x00000010 +#define GPT_DMAEV_TAMDMAEN_S 4 // Field: [2] CAEDMAEN // // GPT Timer A Capture Event DMA Trigger Enable -#define GPT_DMAEV_CAEDMAEN 0x00000004 -#define GPT_DMAEV_CAEDMAEN_BITN 2 -#define GPT_DMAEV_CAEDMAEN_M 0x00000004 -#define GPT_DMAEV_CAEDMAEN_S 2 +#define GPT_DMAEV_CAEDMAEN 0x00000004 +#define GPT_DMAEV_CAEDMAEN_BITN 2 +#define GPT_DMAEV_CAEDMAEN_M 0x00000004 +#define GPT_DMAEV_CAEDMAEN_S 2 // Field: [1] CAMDMAEN // // GPT Timer A Capture Match DMA Trigger Enable -#define GPT_DMAEV_CAMDMAEN 0x00000002 -#define GPT_DMAEV_CAMDMAEN_BITN 1 -#define GPT_DMAEV_CAMDMAEN_M 0x00000002 -#define GPT_DMAEV_CAMDMAEN_S 1 +#define GPT_DMAEV_CAMDMAEN 0x00000002 +#define GPT_DMAEV_CAMDMAEN_BITN 1 +#define GPT_DMAEV_CAMDMAEN_M 0x00000002 +#define GPT_DMAEV_CAMDMAEN_S 1 // Field: [0] TATODMAEN // // GPT Timer A Time-Out DMA Trigger Enable -#define GPT_DMAEV_TATODMAEN 0x00000001 -#define GPT_DMAEV_TATODMAEN_BITN 0 -#define GPT_DMAEV_TATODMAEN_M 0x00000001 -#define GPT_DMAEV_TATODMAEN_S 0 +#define GPT_DMAEV_TATODMAEN 0x00000001 +#define GPT_DMAEV_TATODMAEN_BITN 0 +#define GPT_DMAEV_TATODMAEN_M 0x00000001 +#define GPT_DMAEV_TATODMAEN_S 0 //***************************************************************************** // @@ -1660,9 +1660,9 @@ // Field: [31:0] VERSION // // Timer Revision. -#define GPT_VERSION_VERSION_W 32 -#define GPT_VERSION_VERSION_M 0xFFFFFFFF -#define GPT_VERSION_VERSION_S 0 +#define GPT_VERSION_VERSION_W 32 +#define GPT_VERSION_VERSION_M 0xFFFFFFFF +#define GPT_VERSION_VERSION_S 0 //***************************************************************************** // @@ -1675,10 +1675,10 @@ // // 0: PWM assertion happens when counter matches load value // 1: PWM assertion happens at timeout of the counter -#define GPT_ANDCCP_LD_TO_EN 0x00000002 -#define GPT_ANDCCP_LD_TO_EN_BITN 1 -#define GPT_ANDCCP_LD_TO_EN_M 0x00000002 -#define GPT_ANDCCP_LD_TO_EN_S 1 +#define GPT_ANDCCP_LD_TO_EN 0x00000002 +#define GPT_ANDCCP_LD_TO_EN_BITN 1 +#define GPT_ANDCCP_LD_TO_EN_M 0x00000002 +#define GPT_ANDCCP_LD_TO_EN_S 1 // Field: [0] CCP_AND_EN // @@ -1688,10 +1688,9 @@ // signals of the respective timers. // 1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM // signals and Timer B PWM ouput is Timer B PWM signal only. -#define GPT_ANDCCP_CCP_AND_EN 0x00000001 -#define GPT_ANDCCP_CCP_AND_EN_BITN 0 -#define GPT_ANDCCP_CCP_AND_EN_M 0x00000001 -#define GPT_ANDCCP_CCP_AND_EN_S 0 - +#define GPT_ANDCCP_CCP_AND_EN 0x00000001 +#define GPT_ANDCCP_CCP_AND_EN_BITN 0 +#define GPT_ANDCCP_CCP_AND_EN_M 0x00000001 +#define GPT_ANDCCP_CCP_AND_EN_S 0 #endif // __GPT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_i2c.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_i2c.h index 3c23b78..a33a275 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_i2c.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_i2c.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_i2c_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_i2c_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_I2C_H__ #define __HW_I2C_H__ @@ -44,58 +44,58 @@ // //***************************************************************************** // Slave Own Address -#define I2C_O_SOAR 0x00000000 +#define I2C_O_SOAR 0x00000000 // Slave Status -#define I2C_O_SSTAT 0x00000004 +#define I2C_O_SSTAT 0x00000004 // Slave Control -#define I2C_O_SCTL 0x00000004 +#define I2C_O_SCTL 0x00000004 // Slave Data -#define I2C_O_SDR 0x00000008 +#define I2C_O_SDR 0x00000008 // Slave Interrupt Mask -#define I2C_O_SIMR 0x0000000C +#define I2C_O_SIMR 0x0000000C // Slave Raw Interrupt Status -#define I2C_O_SRIS 0x00000010 +#define I2C_O_SRIS 0x00000010 // Slave Masked Interrupt Status -#define I2C_O_SMIS 0x00000014 +#define I2C_O_SMIS 0x00000014 // Slave Interrupt Clear -#define I2C_O_SICR 0x00000018 +#define I2C_O_SICR 0x00000018 // Master Salve Address -#define I2C_O_MSA 0x00000800 +#define I2C_O_MSA 0x00000800 // Master Status -#define I2C_O_MSTAT 0x00000804 +#define I2C_O_MSTAT 0x00000804 // Master Control -#define I2C_O_MCTRL 0x00000804 +#define I2C_O_MCTRL 0x00000804 // Master Data -#define I2C_O_MDR 0x00000808 +#define I2C_O_MDR 0x00000808 // I2C Master Timer Period -#define I2C_O_MTPR 0x0000080C +#define I2C_O_MTPR 0x0000080C // Master Interrupt Mask -#define I2C_O_MIMR 0x00000810 +#define I2C_O_MIMR 0x00000810 // Master Raw Interrupt Status -#define I2C_O_MRIS 0x00000814 +#define I2C_O_MRIS 0x00000814 // Master Masked Interrupt Status -#define I2C_O_MMIS 0x00000818 +#define I2C_O_MMIS 0x00000818 // Master Interrupt Clear -#define I2C_O_MICR 0x0000081C +#define I2C_O_MICR 0x0000081C // Master Configuration -#define I2C_O_MCR 0x00000820 +#define I2C_O_MCR 0x00000820 //***************************************************************************** // @@ -106,9 +106,9 @@ // // I2C slave own address // This field specifies bits a6 through a0 of the slave address. -#define I2C_SOAR_OAR_W 7 -#define I2C_SOAR_OAR_M 0x0000007F -#define I2C_SOAR_OAR_S 0 +#define I2C_SOAR_OAR_W 7 +#define I2C_SOAR_OAR_M 0x0000007F +#define I2C_SOAR_OAR_S 0 //***************************************************************************** // @@ -125,10 +125,10 @@ // This bit is only valid when the RREQ bit is set and is automatically cleared // when data has been read from the SDR register. // Note: This bit is not used for slave transmit operations. -#define I2C_SSTAT_FBR 0x00000004 -#define I2C_SSTAT_FBR_BITN 2 -#define I2C_SSTAT_FBR_M 0x00000004 -#define I2C_SSTAT_FBR_S 2 +#define I2C_SSTAT_FBR 0x00000004 +#define I2C_SSTAT_FBR_BITN 2 +#define I2C_SSTAT_FBR_M 0x00000004 +#define I2C_SSTAT_FBR_S 2 // Field: [1] TREQ // @@ -138,10 +138,10 @@ // 1: The I2C controller has been addressed as a slave transmitter and is using // clock stretching to delay the master until data has been written to the SDR // register. -#define I2C_SSTAT_TREQ 0x00000002 -#define I2C_SSTAT_TREQ_BITN 1 -#define I2C_SSTAT_TREQ_M 0x00000002 -#define I2C_SSTAT_TREQ_S 1 +#define I2C_SSTAT_TREQ 0x00000002 +#define I2C_SSTAT_TREQ_BITN 1 +#define I2C_SSTAT_TREQ_M 0x00000002 +#define I2C_SSTAT_TREQ_S 1 // Field: [0] RREQ // @@ -151,10 +151,10 @@ // 1: The I2C controller has outstanding receive data from the I2C master and // is using clock stretching to delay the master until data has been read from // the SDR register. -#define I2C_SSTAT_RREQ 0x00000001 -#define I2C_SSTAT_RREQ_BITN 0 -#define I2C_SSTAT_RREQ_M 0x00000001 -#define I2C_SSTAT_RREQ_S 0 +#define I2C_SSTAT_RREQ 0x00000001 +#define I2C_SSTAT_RREQ_BITN 0 +#define I2C_SSTAT_RREQ_M 0x00000001 +#define I2C_SSTAT_RREQ_S 0 //***************************************************************************** // @@ -167,10 +167,10 @@ // // 0: Disables the I2C slave operation // 1: Enables the I2C slave operation -#define I2C_SCTL_DA 0x00000001 -#define I2C_SCTL_DA_BITN 0 -#define I2C_SCTL_DA_M 0x00000001 -#define I2C_SCTL_DA_S 0 +#define I2C_SCTL_DA 0x00000001 +#define I2C_SCTL_DA_BITN 0 +#define I2C_SCTL_DA_M 0x00000001 +#define I2C_SCTL_DA_S 0 //***************************************************************************** // @@ -185,9 +185,9 @@ // read, this register returns the last data received. // Data is stored until next update, either by a system write for transmit or // by an external master for receive. -#define I2C_SDR_DATA_W 8 -#define I2C_SDR_DATA_M 0x000000FF -#define I2C_SDR_DATA_S 0 +#define I2C_SDR_DATA_W 8 +#define I2C_SDR_DATA_M 0x000000FF +#define I2C_SDR_DATA_S 0 //***************************************************************************** // @@ -205,12 +205,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define I2C_SIMR_STOPIM 0x00000004 -#define I2C_SIMR_STOPIM_BITN 2 -#define I2C_SIMR_STOPIM_M 0x00000004 -#define I2C_SIMR_STOPIM_S 2 -#define I2C_SIMR_STOPIM_EN 0x00000004 -#define I2C_SIMR_STOPIM_DIS 0x00000000 +#define I2C_SIMR_STOPIM 0x00000004 +#define I2C_SIMR_STOPIM_BITN 2 +#define I2C_SIMR_STOPIM_M 0x00000004 +#define I2C_SIMR_STOPIM_S 2 +#define I2C_SIMR_STOPIM_EN 0x00000004 +#define I2C_SIMR_STOPIM_DIS 0x00000000 // Field: [1] STARTIM // @@ -223,12 +223,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define I2C_SIMR_STARTIM 0x00000002 -#define I2C_SIMR_STARTIM_BITN 1 -#define I2C_SIMR_STARTIM_M 0x00000002 -#define I2C_SIMR_STARTIM_S 1 -#define I2C_SIMR_STARTIM_EN 0x00000002 -#define I2C_SIMR_STARTIM_DIS 0x00000000 +#define I2C_SIMR_STARTIM 0x00000002 +#define I2C_SIMR_STARTIM_BITN 1 +#define I2C_SIMR_STARTIM_M 0x00000002 +#define I2C_SIMR_STARTIM_S 1 +#define I2C_SIMR_STARTIM_EN 0x00000002 +#define I2C_SIMR_STARTIM_DIS 0x00000000 // Field: [0] DATAIM // @@ -238,10 +238,10 @@ // controller. // 1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt // controller. -#define I2C_SIMR_DATAIM 0x00000001 -#define I2C_SIMR_DATAIM_BITN 0 -#define I2C_SIMR_DATAIM_M 0x00000001 -#define I2C_SIMR_DATAIM_S 0 +#define I2C_SIMR_DATAIM 0x00000001 +#define I2C_SIMR_DATAIM_BITN 0 +#define I2C_SIMR_DATAIM_M 0x00000001 +#define I2C_SIMR_DATAIM_S 0 //***************************************************************************** // @@ -256,10 +256,10 @@ // 1: A Stop condition interrupt is pending. // // This bit is cleared by writing a 1 to SICR.STOPIC. -#define I2C_SRIS_STOPRIS 0x00000004 -#define I2C_SRIS_STOPRIS_BITN 2 -#define I2C_SRIS_STOPRIS_M 0x00000004 -#define I2C_SRIS_STOPRIS_S 2 +#define I2C_SRIS_STOPRIS 0x00000004 +#define I2C_SRIS_STOPRIS_BITN 2 +#define I2C_SRIS_STOPRIS_M 0x00000004 +#define I2C_SRIS_STOPRIS_S 2 // Field: [1] STARTRIS // @@ -269,10 +269,10 @@ // 1: A Start condition interrupt is pending. // // This bit is cleared by writing a 1 to SICR.STARTIC. -#define I2C_SRIS_STARTRIS 0x00000002 -#define I2C_SRIS_STARTRIS_BITN 1 -#define I2C_SRIS_STARTRIS_M 0x00000002 -#define I2C_SRIS_STARTRIS_S 1 +#define I2C_SRIS_STARTRIS 0x00000002 +#define I2C_SRIS_STARTRIS_BITN 1 +#define I2C_SRIS_STARTRIS_M 0x00000002 +#define I2C_SRIS_STARTRIS_S 1 // Field: [0] DATARIS // @@ -282,10 +282,10 @@ // 1: A data received or data requested interrupt is pending. // // This bit is cleared by writing a 1 to the SICR.DATAIC. -#define I2C_SRIS_DATARIS 0x00000001 -#define I2C_SRIS_DATARIS_BITN 0 -#define I2C_SRIS_DATARIS_M 0x00000001 -#define I2C_SRIS_DATARIS_S 0 +#define I2C_SRIS_DATARIS 0x00000001 +#define I2C_SRIS_DATARIS_BITN 0 +#define I2C_SRIS_DATARIS_M 0x00000001 +#define I2C_SRIS_DATARIS_S 0 //***************************************************************************** // @@ -300,10 +300,10 @@ // 1: An unmasked Stop condition interrupt is pending. // // This bit is cleared by writing a 1 to the SICR.STOPIC. -#define I2C_SMIS_STOPMIS 0x00000004 -#define I2C_SMIS_STOPMIS_BITN 2 -#define I2C_SMIS_STOPMIS_M 0x00000004 -#define I2C_SMIS_STOPMIS_S 2 +#define I2C_SMIS_STOPMIS 0x00000004 +#define I2C_SMIS_STOPMIS_BITN 2 +#define I2C_SMIS_STOPMIS_M 0x00000004 +#define I2C_SMIS_STOPMIS_S 2 // Field: [1] STARTMIS // @@ -313,10 +313,10 @@ // 1: An unmasked Start condition interrupt is pending. // // This bit is cleared by writing a 1 to the SICR.STARTIC. -#define I2C_SMIS_STARTMIS 0x00000002 -#define I2C_SMIS_STARTMIS_BITN 1 -#define I2C_SMIS_STARTMIS_M 0x00000002 -#define I2C_SMIS_STARTMIS_S 1 +#define I2C_SMIS_STARTMIS 0x00000002 +#define I2C_SMIS_STARTMIS_BITN 1 +#define I2C_SMIS_STARTMIS_M 0x00000002 +#define I2C_SMIS_STARTMIS_S 1 // Field: [0] DATAMIS // @@ -326,10 +326,10 @@ // 1: An unmasked data received or data requested interrupt is pending. // // This bit is cleared by writing a 1 to the SICR.DATAIC. -#define I2C_SMIS_DATAMIS 0x00000001 -#define I2C_SMIS_DATAMIS_BITN 0 -#define I2C_SMIS_DATAMIS_M 0x00000001 -#define I2C_SMIS_DATAMIS_S 0 +#define I2C_SMIS_DATAMIS 0x00000001 +#define I2C_SMIS_DATAMIS_BITN 0 +#define I2C_SMIS_DATAMIS_M 0x00000001 +#define I2C_SMIS_DATAMIS_S 0 //***************************************************************************** // @@ -341,30 +341,30 @@ // Stop condition interrupt clear // // Writing 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS. -#define I2C_SICR_STOPIC 0x00000004 -#define I2C_SICR_STOPIC_BITN 2 -#define I2C_SICR_STOPIC_M 0x00000004 -#define I2C_SICR_STOPIC_S 2 +#define I2C_SICR_STOPIC 0x00000004 +#define I2C_SICR_STOPIC_BITN 2 +#define I2C_SICR_STOPIC_M 0x00000004 +#define I2C_SICR_STOPIC_S 2 // Field: [1] STARTIC // // Start condition interrupt clear // // Writing 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS. -#define I2C_SICR_STARTIC 0x00000002 -#define I2C_SICR_STARTIC_BITN 1 -#define I2C_SICR_STARTIC_M 0x00000002 -#define I2C_SICR_STARTIC_S 1 +#define I2C_SICR_STARTIC 0x00000002 +#define I2C_SICR_STARTIC_BITN 1 +#define I2C_SICR_STARTIC_M 0x00000002 +#define I2C_SICR_STARTIC_S 1 // Field: [0] DATAIC // // Data interrupt clear // // Writing 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS. -#define I2C_SICR_DATAIC 0x00000001 -#define I2C_SICR_DATAIC_BITN 0 -#define I2C_SICR_DATAIC_M 0x00000001 -#define I2C_SICR_DATAIC_S 0 +#define I2C_SICR_DATAIC 0x00000001 +#define I2C_SICR_DATAIC_BITN 0 +#define I2C_SICR_DATAIC_M 0x00000001 +#define I2C_SICR_DATAIC_S 0 //***************************************************************************** // @@ -375,9 +375,9 @@ // // I2C master slave address // Defines which slave is addressed for the transaction in master mode -#define I2C_MSA_SA_W 7 -#define I2C_MSA_SA_M 0x000000FE -#define I2C_MSA_SA_S 1 +#define I2C_MSA_SA_W 7 +#define I2C_MSA_SA_M 0x000000FE +#define I2C_MSA_SA_S 1 // Field: [0] RS // @@ -387,12 +387,12 @@ // ENUMs: // RX Receive data from slave // TX Transmit/send data to slave -#define I2C_MSA_RS 0x00000001 -#define I2C_MSA_RS_BITN 0 -#define I2C_MSA_RS_M 0x00000001 -#define I2C_MSA_RS_S 0 -#define I2C_MSA_RS_RX 0x00000001 -#define I2C_MSA_RS_TX 0x00000000 +#define I2C_MSA_RS 0x00000001 +#define I2C_MSA_RS_BITN 0 +#define I2C_MSA_RS_M 0x00000001 +#define I2C_MSA_RS_S 0 +#define I2C_MSA_RS_RX 0x00000001 +#define I2C_MSA_RS_TX 0x00000000 //***************************************************************************** // @@ -407,10 +407,10 @@ // 1: The I2C bus is busy. // // The bit changes based on the MCTRL.START and MCTRL.STOP conditions. -#define I2C_MSTAT_BUSBSY 0x00000040 -#define I2C_MSTAT_BUSBSY_BITN 6 -#define I2C_MSTAT_BUSBSY_M 0x00000040 -#define I2C_MSTAT_BUSBSY_S 6 +#define I2C_MSTAT_BUSBSY 0x00000040 +#define I2C_MSTAT_BUSBSY_BITN 6 +#define I2C_MSTAT_BUSBSY_M 0x00000040 +#define I2C_MSTAT_BUSBSY_S 6 // Field: [5] IDLE // @@ -418,10 +418,10 @@ // // 0: The I2C controller is not idle. // 1: The I2C controller is idle. -#define I2C_MSTAT_IDLE 0x00000020 -#define I2C_MSTAT_IDLE_BITN 5 -#define I2C_MSTAT_IDLE_M 0x00000020 -#define I2C_MSTAT_IDLE_S 5 +#define I2C_MSTAT_IDLE 0x00000020 +#define I2C_MSTAT_IDLE_BITN 5 +#define I2C_MSTAT_IDLE_M 0x00000020 +#define I2C_MSTAT_IDLE_S 5 // Field: [4] ARBLST // @@ -429,10 +429,10 @@ // // 0: The I2C controller won arbitration. // 1: The I2C controller lost arbitration. -#define I2C_MSTAT_ARBLST 0x00000010 -#define I2C_MSTAT_ARBLST_BITN 4 -#define I2C_MSTAT_ARBLST_M 0x00000010 -#define I2C_MSTAT_ARBLST_S 4 +#define I2C_MSTAT_ARBLST 0x00000010 +#define I2C_MSTAT_ARBLST_BITN 4 +#define I2C_MSTAT_ARBLST_M 0x00000010 +#define I2C_MSTAT_ARBLST_S 4 // Field: [3] DATACK_N // @@ -440,10 +440,10 @@ // // 0: The transmitted data was acknowledged. // 1: The transmitted data was not acknowledged. -#define I2C_MSTAT_DATACK_N 0x00000008 -#define I2C_MSTAT_DATACK_N_BITN 3 -#define I2C_MSTAT_DATACK_N_M 0x00000008 -#define I2C_MSTAT_DATACK_N_S 3 +#define I2C_MSTAT_DATACK_N 0x00000008 +#define I2C_MSTAT_DATACK_N_BITN 3 +#define I2C_MSTAT_DATACK_N_M 0x00000008 +#define I2C_MSTAT_DATACK_N_S 3 // Field: [2] ADRACK_N // @@ -451,10 +451,10 @@ // // 0: The transmitted address was acknowledged. // 1: The transmitted address was not acknowledged. -#define I2C_MSTAT_ADRACK_N 0x00000004 -#define I2C_MSTAT_ADRACK_N_BITN 2 -#define I2C_MSTAT_ADRACK_N_M 0x00000004 -#define I2C_MSTAT_ADRACK_N_S 2 +#define I2C_MSTAT_ADRACK_N 0x00000004 +#define I2C_MSTAT_ADRACK_N_BITN 2 +#define I2C_MSTAT_ADRACK_N_M 0x00000004 +#define I2C_MSTAT_ADRACK_N_S 2 // Field: [1] ERR // @@ -462,10 +462,10 @@ // // 0: No error was detected on the last operation. // 1: An error occurred on the last operation. -#define I2C_MSTAT_ERR 0x00000002 -#define I2C_MSTAT_ERR_BITN 1 -#define I2C_MSTAT_ERR_M 0x00000002 -#define I2C_MSTAT_ERR_S 1 +#define I2C_MSTAT_ERR 0x00000002 +#define I2C_MSTAT_ERR_BITN 1 +#define I2C_MSTAT_ERR_M 0x00000002 +#define I2C_MSTAT_ERR_S 1 // Field: [0] BUSY // @@ -483,10 +483,10 @@ // four SYSBUS clock cycles before issuing a controller status inquiry through // MSTAT register. // Any prior inquiry would result in wrong status being reported. -#define I2C_MSTAT_BUSY 0x00000001 -#define I2C_MSTAT_BUSY_BITN 0 -#define I2C_MSTAT_BUSY_M 0x00000001 -#define I2C_MSTAT_BUSY_S 0 +#define I2C_MSTAT_BUSY 0x00000001 +#define I2C_MSTAT_BUSY_BITN 0 +#define I2C_MSTAT_BUSY_M 0x00000001 +#define I2C_MSTAT_BUSY_S 0 //***************************************************************************** // @@ -505,12 +505,12 @@ // ENUMs: // EN Enable acknowledge // DIS Disable acknowledge -#define I2C_MCTRL_ACK 0x00000008 -#define I2C_MCTRL_ACK_BITN 3 -#define I2C_MCTRL_ACK_M 0x00000008 -#define I2C_MCTRL_ACK_S 3 -#define I2C_MCTRL_ACK_EN 0x00000008 -#define I2C_MCTRL_ACK_DIS 0x00000000 +#define I2C_MCTRL_ACK 0x00000008 +#define I2C_MCTRL_ACK_BITN 3 +#define I2C_MCTRL_ACK_M 0x00000008 +#define I2C_MCTRL_ACK_S 3 +#define I2C_MCTRL_ACK_EN 0x00000008 +#define I2C_MCTRL_ACK_DIS 0x00000000 // Field: [2] STOP // @@ -522,12 +522,12 @@ // ENUMs: // EN Enable STOP // DIS Disable STOP -#define I2C_MCTRL_STOP 0x00000004 -#define I2C_MCTRL_STOP_BITN 2 -#define I2C_MCTRL_STOP_M 0x00000004 -#define I2C_MCTRL_STOP_S 2 -#define I2C_MCTRL_STOP_EN 0x00000004 -#define I2C_MCTRL_STOP_DIS 0x00000000 +#define I2C_MCTRL_STOP 0x00000004 +#define I2C_MCTRL_STOP_BITN 2 +#define I2C_MCTRL_STOP_M 0x00000004 +#define I2C_MCTRL_STOP_S 2 +#define I2C_MCTRL_STOP_EN 0x00000004 +#define I2C_MCTRL_STOP_DIS 0x00000000 // Field: [1] START // @@ -538,12 +538,12 @@ // ENUMs: // EN Enable START // DIS Disable START -#define I2C_MCTRL_START 0x00000002 -#define I2C_MCTRL_START_BITN 1 -#define I2C_MCTRL_START_M 0x00000002 -#define I2C_MCTRL_START_S 1 -#define I2C_MCTRL_START_EN 0x00000002 -#define I2C_MCTRL_START_DIS 0x00000000 +#define I2C_MCTRL_START 0x00000002 +#define I2C_MCTRL_START_BITN 1 +#define I2C_MCTRL_START_M 0x00000002 +#define I2C_MCTRL_START_S 1 +#define I2C_MCTRL_START_EN 0x00000002 +#define I2C_MCTRL_START_DIS 0x00000000 // Field: [0] RUN // @@ -554,12 +554,12 @@ // ENUMs: // EN Enable Master // DIS Disable Master -#define I2C_MCTRL_RUN 0x00000001 -#define I2C_MCTRL_RUN_BITN 0 -#define I2C_MCTRL_RUN_M 0x00000001 -#define I2C_MCTRL_RUN_S 0 -#define I2C_MCTRL_RUN_EN 0x00000001 -#define I2C_MCTRL_RUN_DIS 0x00000000 +#define I2C_MCTRL_RUN 0x00000001 +#define I2C_MCTRL_RUN_BITN 0 +#define I2C_MCTRL_RUN_M 0x00000001 +#define I2C_MCTRL_RUN_S 0 +#define I2C_MCTRL_RUN_EN 0x00000001 +#define I2C_MCTRL_RUN_DIS 0x00000000 //***************************************************************************** // @@ -570,9 +570,9 @@ // // When Read: Last RX Data is returned // When Written: Data is transferred during TX transaction -#define I2C_MDR_DATA_W 8 -#define I2C_MDR_DATA_M 0x000000FF -#define I2C_MDR_DATA_S 0 +#define I2C_MDR_DATA_W 8 +#define I2C_MDR_DATA_M 0x000000FF +#define I2C_MDR_DATA_S 0 //***************************************************************************** // @@ -582,10 +582,10 @@ // Field: [7] TPR_7 // // Must be set to 0 to set TPR. If set to 1, a write to TPR will be ignored. -#define I2C_MTPR_TPR_7 0x00000080 -#define I2C_MTPR_TPR_7_BITN 7 -#define I2C_MTPR_TPR_7_M 0x00000080 -#define I2C_MTPR_TPR_7_S 7 +#define I2C_MTPR_TPR_7 0x00000080 +#define I2C_MTPR_TPR_7_BITN 7 +#define I2C_MTPR_TPR_7_M 0x00000080 +#define I2C_MTPR_TPR_7_S 7 // Field: [6:0] TPR // @@ -598,9 +598,9 @@ // SCL_LP is the SCL low period (fixed at 6). // SCL_HP is the SCL high period (fixed at 4). // CLK_PRD is the system clock period in ns. -#define I2C_MTPR_TPR_W 7 -#define I2C_MTPR_TPR_M 0x0000007F -#define I2C_MTPR_TPR_S 0 +#define I2C_MTPR_TPR_W 7 +#define I2C_MTPR_TPR_M 0x0000007F +#define I2C_MTPR_TPR_S 0 //***************************************************************************** // @@ -618,12 +618,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define I2C_MIMR_IM 0x00000001 -#define I2C_MIMR_IM_BITN 0 -#define I2C_MIMR_IM_M 0x00000001 -#define I2C_MIMR_IM_S 0 -#define I2C_MIMR_IM_EN 0x00000001 -#define I2C_MIMR_IM_DIS 0x00000000 +#define I2C_MIMR_IM 0x00000001 +#define I2C_MIMR_IM_BITN 0 +#define I2C_MIMR_IM_M 0x00000001 +#define I2C_MIMR_IM_S 0 +#define I2C_MIMR_IM_EN 0x00000001 +#define I2C_MIMR_IM_DIS 0x00000000 //***************************************************************************** // @@ -638,10 +638,10 @@ // 1: A master interrupt is pending. // // This bit is cleared by writing 1 to the MICR.IC bit . -#define I2C_MRIS_RIS 0x00000001 -#define I2C_MRIS_RIS_BITN 0 -#define I2C_MRIS_RIS_M 0x00000001 -#define I2C_MRIS_RIS_S 0 +#define I2C_MRIS_RIS 0x00000001 +#define I2C_MRIS_RIS_BITN 0 +#define I2C_MRIS_RIS_M 0x00000001 +#define I2C_MRIS_RIS_S 0 //***************************************************************************** // @@ -656,10 +656,10 @@ // 1: A master interrupt is pending. // // This bit is cleared by writing 1 to the MICR.IC bit . -#define I2C_MMIS_MIS 0x00000001 -#define I2C_MMIS_MIS_BITN 0 -#define I2C_MMIS_MIS_M 0x00000001 -#define I2C_MMIS_MIS_S 0 +#define I2C_MMIS_MIS 0x00000001 +#define I2C_MMIS_MIS_BITN 0 +#define I2C_MMIS_MIS_M 0x00000001 +#define I2C_MMIS_MIS_S 0 //***************************************************************************** // @@ -672,10 +672,10 @@ // Writing 1 to this bit clears MRIS.RIS and MMIS.MIS . // // Reading this register returns no meaningful data. -#define I2C_MICR_IC 0x00000001 -#define I2C_MICR_IC_BITN 0 -#define I2C_MICR_IC_M 0x00000001 -#define I2C_MICR_IC_S 0 +#define I2C_MICR_IC 0x00000001 +#define I2C_MICR_IC_BITN 0 +#define I2C_MICR_IC_M 0x00000001 +#define I2C_MICR_IC_S 0 //***************************************************************************** // @@ -688,12 +688,12 @@ // ENUMs: // EN Slave mode is enabled. // DIS Slave mode is disabled. -#define I2C_MCR_SFE 0x00000020 -#define I2C_MCR_SFE_BITN 5 -#define I2C_MCR_SFE_M 0x00000020 -#define I2C_MCR_SFE_S 5 -#define I2C_MCR_SFE_EN 0x00000020 -#define I2C_MCR_SFE_DIS 0x00000000 +#define I2C_MCR_SFE 0x00000020 +#define I2C_MCR_SFE_BITN 5 +#define I2C_MCR_SFE_M 0x00000020 +#define I2C_MCR_SFE_S 5 +#define I2C_MCR_SFE_EN 0x00000020 +#define I2C_MCR_SFE_DIS 0x00000000 // Field: [4] MFE // @@ -701,12 +701,12 @@ // ENUMs: // EN Master mode is enabled. // DIS Master mode is disabled. -#define I2C_MCR_MFE 0x00000010 -#define I2C_MCR_MFE_BITN 4 -#define I2C_MCR_MFE_M 0x00000010 -#define I2C_MCR_MFE_S 4 -#define I2C_MCR_MFE_EN 0x00000010 -#define I2C_MCR_MFE_DIS 0x00000000 +#define I2C_MCR_MFE 0x00000010 +#define I2C_MCR_MFE_BITN 4 +#define I2C_MCR_MFE_M 0x00000010 +#define I2C_MCR_MFE_S 4 +#define I2C_MCR_MFE_EN 0x00000010 +#define I2C_MCR_MFE_DIS 0x00000000 // Field: [0] LPBK // @@ -717,12 +717,11 @@ // ENUMs: // EN Enable Test Mode // DIS Disable Test Mode -#define I2C_MCR_LPBK 0x00000001 -#define I2C_MCR_LPBK_BITN 0 -#define I2C_MCR_LPBK_M 0x00000001 -#define I2C_MCR_LPBK_S 0 -#define I2C_MCR_LPBK_EN 0x00000001 -#define I2C_MCR_LPBK_DIS 0x00000000 - +#define I2C_MCR_LPBK 0x00000001 +#define I2C_MCR_LPBK_BITN 0 +#define I2C_MCR_LPBK_M 0x00000001 +#define I2C_MCR_LPBK_S 0 +#define I2C_MCR_LPBK_EN 0x00000001 +#define I2C_MCR_LPBK_DIS 0x00000000 #endif // __I2C__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_i2s.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_i2s.h index a0bfed9..f9f30b8 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_i2s.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_i2s.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_i2s_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_i2s_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_I2S_H__ #define __HW_I2S_H__ @@ -44,91 +44,91 @@ // //***************************************************************************** // WCLK Source Selection -#define I2S_O_AIFWCLKSRC 0x00000000 +#define I2S_O_AIFWCLKSRC 0x00000000 // DMA Buffer Size Configuration -#define I2S_O_AIFDMACFG 0x00000004 +#define I2S_O_AIFDMACFG 0x00000004 // Pin Direction -#define I2S_O_AIFDIRCFG 0x00000008 +#define I2S_O_AIFDIRCFG 0x00000008 // Serial Interface Format Configuration -#define I2S_O_AIFFMTCFG 0x0000000C +#define I2S_O_AIFFMTCFG 0x0000000C // Word Selection Bit Mask for Pin 0 -#define I2S_O_AIFWMASK0 0x00000010 +#define I2S_O_AIFWMASK0 0x00000010 // Word Selection Bit Mask for Pin 1 -#define I2S_O_AIFWMASK1 0x00000014 +#define I2S_O_AIFWMASK1 0x00000014 // Audio Interface PWM Debug Value -#define I2S_O_AIFPWMVALUE 0x0000001C +#define I2S_O_AIFPWMVALUE 0x0000001C // DMA Input Buffer Next Pointer -#define I2S_O_AIFINPTRNEXT 0x00000020 +#define I2S_O_AIFINPTRNEXT 0x00000020 // DMA Input Buffer Current Pointer -#define I2S_O_AIFINPTR 0x00000024 +#define I2S_O_AIFINPTR 0x00000024 // DMA Output Buffer Next Pointer -#define I2S_O_AIFOUTPTRNEXT 0x00000028 +#define I2S_O_AIFOUTPTRNEXT 0x00000028 // DMA Output Buffer Current Pointer -#define I2S_O_AIFOUTPTR 0x0000002C +#define I2S_O_AIFOUTPTR 0x0000002C // Samplestamp Generator Control Register -#define I2S_O_STMPCTL 0x00000034 +#define I2S_O_STMPCTL 0x00000034 // Captured XOSC Counter Value, Capture Channel 0 -#define I2S_O_STMPXCNTCAPT0 0x00000038 +#define I2S_O_STMPXCNTCAPT0 0x00000038 // XOSC Period Value -#define I2S_O_STMPXPER 0x0000003C +#define I2S_O_STMPXPER 0x0000003C // Captured WCLK Counter Value, Capture Channel 0 -#define I2S_O_STMPWCNTCAPT0 0x00000040 +#define I2S_O_STMPWCNTCAPT0 0x00000040 // WCLK Counter Period Value -#define I2S_O_STMPWPER 0x00000044 +#define I2S_O_STMPWPER 0x00000044 // WCLK Counter Trigger Value for Input Pins -#define I2S_O_STMPINTRIG 0x00000048 +#define I2S_O_STMPINTRIG 0x00000048 // WCLK Counter Trigger Value for Output Pins -#define I2S_O_STMPOUTTRIG 0x0000004C +#define I2S_O_STMPOUTTRIG 0x0000004C // WCLK Counter Set Operation -#define I2S_O_STMPWSET 0x00000050 +#define I2S_O_STMPWSET 0x00000050 // WCLK Counter Add Operation -#define I2S_O_STMPWADD 0x00000054 +#define I2S_O_STMPWADD 0x00000054 // XOSC Minimum Period Value -#define I2S_O_STMPXPERMIN 0x00000058 +#define I2S_O_STMPXPERMIN 0x00000058 // Current Value of WCNT -#define I2S_O_STMPWCNT 0x0000005C +#define I2S_O_STMPWCNT 0x0000005C // Current Value of XCNT -#define I2S_O_STMPXCNT 0x00000060 +#define I2S_O_STMPXCNT 0x00000060 // Internal -#define I2S_O_STMPXCNTCAPT1 0x00000064 +#define I2S_O_STMPXCNTCAPT1 0x00000064 // Internal -#define I2S_O_STMPWCNTCAPT1 0x00000068 +#define I2S_O_STMPWCNTCAPT1 0x00000068 // Interrupt Mask Register -#define I2S_O_IRQMASK 0x00000070 +#define I2S_O_IRQMASK 0x00000070 // Raw Interrupt Status Register -#define I2S_O_IRQFLAGS 0x00000074 +#define I2S_O_IRQFLAGS 0x00000074 // Interrupt Set Register -#define I2S_O_IRQSET 0x00000078 +#define I2S_O_IRQSET 0x00000078 // Interrupt Clear Register -#define I2S_O_IRQCLR 0x0000007C +#define I2S_O_IRQCLR 0x0000007C //***************************************************************************** // @@ -141,10 +141,10 @@ // // 0: Not inverted // 1: Inverted -#define I2S_AIFWCLKSRC_WCLK_INV 0x00000004 -#define I2S_AIFWCLKSRC_WCLK_INV_BITN 2 -#define I2S_AIFWCLKSRC_WCLK_INV_M 0x00000004 -#define I2S_AIFWCLKSRC_WCLK_INV_S 2 +#define I2S_AIFWCLKSRC_WCLK_INV 0x00000004 +#define I2S_AIFWCLKSRC_WCLK_INV_BITN 2 +#define I2S_AIFWCLKSRC_WCLK_INV_M 0x00000004 +#define I2S_AIFWCLKSRC_WCLK_INV_S 2 // Field: [1:0] WCLK_SRC // @@ -156,13 +156,13 @@ // INT Internal WCLK generator, from module PRCM // EXT External WCLK generator, from pad // NONE None ('0') -#define I2S_AIFWCLKSRC_WCLK_SRC_W 2 -#define I2S_AIFWCLKSRC_WCLK_SRC_M 0x00000003 -#define I2S_AIFWCLKSRC_WCLK_SRC_S 0 -#define I2S_AIFWCLKSRC_WCLK_SRC_RESERVED 0x00000003 -#define I2S_AIFWCLKSRC_WCLK_SRC_INT 0x00000002 -#define I2S_AIFWCLKSRC_WCLK_SRC_EXT 0x00000001 -#define I2S_AIFWCLKSRC_WCLK_SRC_NONE 0x00000000 +#define I2S_AIFWCLKSRC_WCLK_SRC_W 2 +#define I2S_AIFWCLKSRC_WCLK_SRC_M 0x00000003 +#define I2S_AIFWCLKSRC_WCLK_SRC_S 0 +#define I2S_AIFWCLKSRC_WCLK_SRC_RESERVED 0x00000003 +#define I2S_AIFWCLKSRC_WCLK_SRC_INT 0x00000002 +#define I2S_AIFWCLKSRC_WCLK_SRC_EXT 0x00000001 +#define I2S_AIFWCLKSRC_WCLK_SRC_NONE 0x00000000 //***************************************************************************** // @@ -175,9 +175,9 @@ // register field enables and initializes AIF. Note that before doing so, all // other configuration must have been done, and AIFINPTRNEXT/AIFOUTPTRNEXT must // have been loaded. -#define I2S_AIFDMACFG_END_FRAME_IDX_W 8 -#define I2S_AIFDMACFG_END_FRAME_IDX_M 0x000000FF -#define I2S_AIFDMACFG_END_FRAME_IDX_S 0 +#define I2S_AIFDMACFG_END_FRAME_IDX_W 8 +#define I2S_AIFDMACFG_END_FRAME_IDX_M 0x000000FF +#define I2S_AIFDMACFG_END_FRAME_IDX_S 0 //***************************************************************************** // @@ -193,12 +193,12 @@ // OUT Output mode // IN Input mode // DIS Not in use (disabled) -#define I2S_AIFDIRCFG_AD1_W 2 -#define I2S_AIFDIRCFG_AD1_M 0x00000030 -#define I2S_AIFDIRCFG_AD1_S 4 -#define I2S_AIFDIRCFG_AD1_OUT 0x00000020 -#define I2S_AIFDIRCFG_AD1_IN 0x00000010 -#define I2S_AIFDIRCFG_AD1_DIS 0x00000000 +#define I2S_AIFDIRCFG_AD1_W 2 +#define I2S_AIFDIRCFG_AD1_M 0x00000030 +#define I2S_AIFDIRCFG_AD1_S 4 +#define I2S_AIFDIRCFG_AD1_OUT 0x00000020 +#define I2S_AIFDIRCFG_AD1_IN 0x00000010 +#define I2S_AIFDIRCFG_AD1_DIS 0x00000000 // Field: [1:0] AD0 // @@ -209,12 +209,12 @@ // OUT Output mode // IN Input mode // DIS Not in use (disabled) -#define I2S_AIFDIRCFG_AD0_W 2 -#define I2S_AIFDIRCFG_AD0_M 0x00000003 -#define I2S_AIFDIRCFG_AD0_S 0 -#define I2S_AIFDIRCFG_AD0_OUT 0x00000002 -#define I2S_AIFDIRCFG_AD0_IN 0x00000001 -#define I2S_AIFDIRCFG_AD0_DIS 0x00000000 +#define I2S_AIFDIRCFG_AD0_W 2 +#define I2S_AIFDIRCFG_AD0_M 0x00000003 +#define I2S_AIFDIRCFG_AD0_S 0 +#define I2S_AIFDIRCFG_AD0_OUT 0x00000002 +#define I2S_AIFDIRCFG_AD0_IN 0x00000001 +#define I2S_AIFDIRCFG_AD0_DIS 0x00000000 //***************************************************************************** // @@ -235,9 +235,9 @@ // Note: When 0, MSB of the next word will be output in the idle period between // LSB of the previous word and the start of the next word. Otherwise logical 0 // will be output until the data delay has expired. -#define I2S_AIFFMTCFG_DATA_DELAY_W 8 -#define I2S_AIFFMTCFG_DATA_DELAY_M 0x0000FF00 -#define I2S_AIFFMTCFG_DATA_DELAY_S 8 +#define I2S_AIFFMTCFG_DATA_DELAY_W 8 +#define I2S_AIFFMTCFG_DATA_DELAY_M 0x0000FF00 +#define I2S_AIFFMTCFG_DATA_DELAY_S 8 // Field: [7] MEM_LEN_24 // @@ -246,12 +246,12 @@ // 24BIT 24-bit (one 8 bit and one 16 bit locked access per // sample) // 16BIT 16-bit (one 16 bit access per sample) -#define I2S_AIFFMTCFG_MEM_LEN_24 0x00000080 -#define I2S_AIFFMTCFG_MEM_LEN_24_BITN 7 -#define I2S_AIFFMTCFG_MEM_LEN_24_M 0x00000080 -#define I2S_AIFFMTCFG_MEM_LEN_24_S 7 -#define I2S_AIFFMTCFG_MEM_LEN_24_24BIT 0x00000080 -#define I2S_AIFFMTCFG_MEM_LEN_24_16BIT 0x00000000 +#define I2S_AIFFMTCFG_MEM_LEN_24 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_BITN 7 +#define I2S_AIFFMTCFG_MEM_LEN_24_M 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_S 7 +#define I2S_AIFFMTCFG_MEM_LEN_24_24BIT 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_16BIT 0x00000000 // Field: [6] SMPL_EDGE // @@ -262,12 +262,12 @@ // out on the negative edge. // NEG Data is sampled on the negative edge and clocked // out on the positive edge. -#define I2S_AIFFMTCFG_SMPL_EDGE 0x00000040 -#define I2S_AIFFMTCFG_SMPL_EDGE_BITN 6 -#define I2S_AIFFMTCFG_SMPL_EDGE_M 0x00000040 -#define I2S_AIFFMTCFG_SMPL_EDGE_S 6 -#define I2S_AIFFMTCFG_SMPL_EDGE_POS 0x00000040 -#define I2S_AIFFMTCFG_SMPL_EDGE_NEG 0x00000000 +#define I2S_AIFFMTCFG_SMPL_EDGE 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_BITN 6 +#define I2S_AIFFMTCFG_SMPL_EDGE_M 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_S 6 +#define I2S_AIFFMTCFG_SMPL_EDGE_POS 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_NEG 0x00000000 // Field: [5] DUAL_PHASE // @@ -275,10 +275,10 @@ // // 0: Single-phase: DSP format // 1: Dual-phase: I2S, LJF and RJF formats -#define I2S_AIFFMTCFG_DUAL_PHASE 0x00000020 -#define I2S_AIFFMTCFG_DUAL_PHASE_BITN 5 -#define I2S_AIFFMTCFG_DUAL_PHASE_M 0x00000020 -#define I2S_AIFFMTCFG_DUAL_PHASE_S 5 +#define I2S_AIFFMTCFG_DUAL_PHASE 0x00000020 +#define I2S_AIFFMTCFG_DUAL_PHASE_BITN 5 +#define I2S_AIFFMTCFG_DUAL_PHASE_M 0x00000020 +#define I2S_AIFFMTCFG_DUAL_PHASE_S 5 // Field: [4:0] WORD_LEN // @@ -289,9 +289,9 @@ // Values below 8 and above 24 give undefined behavior. Data written to memory // is always aligned to 16 or 24 bits as defined by MEM_LEN_24. Bit widths that // differ from this alignment will either be truncated or zero padded. -#define I2S_AIFFMTCFG_WORD_LEN_W 5 -#define I2S_AIFFMTCFG_WORD_LEN_M 0x0000001F -#define I2S_AIFFMTCFG_WORD_LEN_S 0 +#define I2S_AIFFMTCFG_WORD_LEN_W 5 +#define I2S_AIFFMTCFG_WORD_LEN_M 0x0000001F +#define I2S_AIFFMTCFG_WORD_LEN_S 0 //***************************************************************************** // @@ -318,9 +318,9 @@ // If all bits are zero, no input words will be stored to memory, and the // output data lines will be constant '0'. This can be utilized when PWM debug // output is desired without any actively used output pins. -#define I2S_AIFWMASK0_MASK_W 8 -#define I2S_AIFWMASK0_MASK_M 0x000000FF -#define I2S_AIFWMASK0_MASK_S 0 +#define I2S_AIFWMASK0_MASK_W 8 +#define I2S_AIFWMASK0_MASK_M 0x000000FF +#define I2S_AIFWMASK0_MASK_S 0 //***************************************************************************** // @@ -347,9 +347,9 @@ // If all bits are zero, no input words will be stored to memory, and the // output data lines will be constant '0'. This can be utilized when PWM debug // output is desired without any actively used output pins. -#define I2S_AIFWMASK1_MASK_W 8 -#define I2S_AIFWMASK1_MASK_M 0x000000FF -#define I2S_AIFWMASK1_MASK_S 0 +#define I2S_AIFWMASK1_MASK_W 8 +#define I2S_AIFWMASK1_MASK_M 0x000000FF +#define I2S_AIFWMASK1_MASK_S 0 //***************************************************************************** // @@ -367,9 +367,9 @@ // ... // 0xFFFE: Width of the pulse (number of BCLK cycles, here 65534). // 0xFFFF: Constant high -#define I2S_AIFPWMVALUE_PULSE_WIDTH_W 16 -#define I2S_AIFPWMVALUE_PULSE_WIDTH_M 0x0000FFFF -#define I2S_AIFPWMVALUE_PULSE_WIDTH_S 0 +#define I2S_AIFPWMVALUE_PULSE_WIDTH_W 16 +#define I2S_AIFPWMVALUE_PULSE_WIDTH_M 0x0000FFFF +#define I2S_AIFPWMVALUE_PULSE_WIDTH_S 0 //***************************************************************************** // @@ -391,9 +391,9 @@ // The next pointer must be written to this register while the DMA function // uses the previously written pointer. If not written in time, // IRQFLAGS.PTR_ERR will be raised and all input pins will be disabled. -#define I2S_AIFINPTRNEXT_PTR_W 32 -#define I2S_AIFINPTRNEXT_PTR_M 0xFFFFFFFF -#define I2S_AIFINPTRNEXT_PTR_S 0 +#define I2S_AIFINPTRNEXT_PTR_W 32 +#define I2S_AIFINPTRNEXT_PTR_M 0xFFFFFFFF +#define I2S_AIFINPTRNEXT_PTR_S 0 //***************************************************************************** // @@ -404,9 +404,9 @@ // // Value of the DMA input buffer pointer currently used by the DMA controller. // Incremented by 1 (byte) or 2 (word) for each AHB access. -#define I2S_AIFINPTR_PTR_W 32 -#define I2S_AIFINPTR_PTR_M 0xFFFFFFFF -#define I2S_AIFINPTR_PTR_S 0 +#define I2S_AIFINPTR_PTR_W 32 +#define I2S_AIFINPTR_PTR_M 0xFFFFFFFF +#define I2S_AIFINPTR_PTR_S 0 //***************************************************************************** // @@ -429,9 +429,9 @@ // The next pointer must be written to this register while the DMA function // uses the previously written pointer. If not written in time, // IRQFLAGS.PTR_ERR will be raised and all output pins will be disabled. -#define I2S_AIFOUTPTRNEXT_PTR_W 32 -#define I2S_AIFOUTPTRNEXT_PTR_M 0xFFFFFFFF -#define I2S_AIFOUTPTRNEXT_PTR_S 0 +#define I2S_AIFOUTPTRNEXT_PTR_W 32 +#define I2S_AIFOUTPTRNEXT_PTR_M 0xFFFFFFFF +#define I2S_AIFOUTPTRNEXT_PTR_S 0 //***************************************************************************** // @@ -442,9 +442,9 @@ // // Value of the DMA output buffer pointer currently used by the DMA controller // Incremented by 1 (byte) or 2 (word) for each AHB access. -#define I2S_AIFOUTPTR_PTR_W 32 -#define I2S_AIFOUTPTR_PTR_M 0xFFFFFFFF -#define I2S_AIFOUTPTR_PTR_S 0 +#define I2S_AIFOUTPTR_PTR_W 32 +#define I2S_AIFOUTPTR_PTR_M 0xFFFFFFFF +#define I2S_AIFOUTPTR_PTR_S 0 //***************************************************************************** // @@ -456,20 +456,20 @@ // Low until the output pins are ready to be started by the samplestamp // generator. When started (that is STMPOUTTRIG equals the WCLK counter) the // bit goes back low. -#define I2S_STMPCTL_OUT_RDY 0x00000004 -#define I2S_STMPCTL_OUT_RDY_BITN 2 -#define I2S_STMPCTL_OUT_RDY_M 0x00000004 -#define I2S_STMPCTL_OUT_RDY_S 2 +#define I2S_STMPCTL_OUT_RDY 0x00000004 +#define I2S_STMPCTL_OUT_RDY_BITN 2 +#define I2S_STMPCTL_OUT_RDY_M 0x00000004 +#define I2S_STMPCTL_OUT_RDY_S 2 // Field: [1] IN_RDY // // Low until the input pins are ready to be started by the samplestamp // generator. When started (that is STMPINTRIG equals the WCLK counter) the bit // goes back low. -#define I2S_STMPCTL_IN_RDY 0x00000002 -#define I2S_STMPCTL_IN_RDY_BITN 1 -#define I2S_STMPCTL_IN_RDY_M 0x00000002 -#define I2S_STMPCTL_IN_RDY_S 1 +#define I2S_STMPCTL_IN_RDY 0x00000002 +#define I2S_STMPCTL_IN_RDY_BITN 1 +#define I2S_STMPCTL_IN_RDY_M 0x00000002 +#define I2S_STMPCTL_IN_RDY_S 1 // Field: [0] STMP_EN // @@ -477,10 +477,10 @@ // enabled after it has been properly configured. // When cleared, all samplestamp generator counters and capture values are // cleared. -#define I2S_STMPCTL_STMP_EN 0x00000001 -#define I2S_STMPCTL_STMP_EN_BITN 0 -#define I2S_STMPCTL_STMP_EN_M 0x00000001 -#define I2S_STMPCTL_STMP_EN_S 0 +#define I2S_STMPCTL_STMP_EN 0x00000001 +#define I2S_STMPCTL_STMP_EN_BITN 0 +#define I2S_STMPCTL_STMP_EN_M 0x00000001 +#define I2S_STMPCTL_STMP_EN_S 0 //***************************************************************************** // @@ -498,9 +498,9 @@ // number of BCLK periods and clk periods. // Note: When calculating the fractional part of the sample stamp, STMPXPER may // be less than this bit field. -#define I2S_STMPXCNTCAPT0_CAPT_VALUE_W 16 -#define I2S_STMPXCNTCAPT0_CAPT_VALUE_M 0x0000FFFF -#define I2S_STMPXCNTCAPT0_CAPT_VALUE_S 0 +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_W 16 +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_S 0 //***************************************************************************** // @@ -513,9 +513,9 @@ // the next value of the XOSC counter at the positive WCLK edge, had it not // been reset to 0). // The value is cleared when STMPCTL.STMP_EN = 0. -#define I2S_STMPXPER_VALUE_W 16 -#define I2S_STMPXPER_VALUE_M 0x0000FFFF -#define I2S_STMPXPER_VALUE_S 0 +#define I2S_STMPXPER_VALUE_W 16 +#define I2S_STMPXPER_VALUE_M 0x0000FFFF +#define I2S_STMPXPER_VALUE_S 0 //***************************************************************************** // @@ -530,9 +530,9 @@ // samplestamp generator was enabled (not taking modification through // STMPWADD/STMPWSET into account). // The value is cleared when STMPCTL.STMP_EN = 0. -#define I2S_STMPWCNTCAPT0_CAPT_VALUE_W 16 -#define I2S_STMPWCNTCAPT0_CAPT_VALUE_M 0x0000FFFF -#define I2S_STMPWCNTCAPT0_CAPT_VALUE_S 0 +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_W 16 +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_S 0 //***************************************************************************** // @@ -545,9 +545,9 @@ // found for the size of the sample buffer. This is thus a modulo value for the // WCLK counter. This number must correspond to the size of the sample buffer // used by the system (that is the index of the last sample plus 1). -#define I2S_STMPWPER_VALUE_W 16 -#define I2S_STMPWPER_VALUE_M 0x0000FFFF -#define I2S_STMPWPER_VALUE_S 0 +#define I2S_STMPWPER_VALUE_W 16 +#define I2S_STMPWPER_VALUE_M 0x0000FFFF +#define I2S_STMPWPER_VALUE_S 0 //***************************************************************************** // @@ -569,9 +569,9 @@ // // Note: To avoid false triggers, this bit field should be set higher than // STMPWPER.VALUE. -#define I2S_STMPINTRIG_IN_START_WCNT_W 16 -#define I2S_STMPINTRIG_IN_START_WCNT_M 0x0000FFFF -#define I2S_STMPINTRIG_IN_START_WCNT_S 0 +#define I2S_STMPINTRIG_IN_START_WCNT_W 16 +#define I2S_STMPINTRIG_IN_START_WCNT_M 0x0000FFFF +#define I2S_STMPINTRIG_IN_START_WCNT_S 0 //***************************************************************************** // @@ -598,9 +598,9 @@ // // Note: To avoid false triggers, this bit field should be set higher than // STMPWPER.VALUE. -#define I2S_STMPOUTTRIG_OUT_START_WCNT_W 16 -#define I2S_STMPOUTTRIG_OUT_START_WCNT_M 0x0000FFFF -#define I2S_STMPOUTTRIG_OUT_START_WCNT_S 0 +#define I2S_STMPOUTTRIG_OUT_START_WCNT_W 16 +#define I2S_STMPOUTTRIG_OUT_START_WCNT_M 0x0000FFFF +#define I2S_STMPOUTTRIG_OUT_START_WCNT_S 0 //***************************************************************************** // @@ -611,9 +611,9 @@ // // WCLK counter modification: Sets the running WCLK counter equal to the // written value. -#define I2S_STMPWSET_VALUE_W 16 -#define I2S_STMPWSET_VALUE_M 0x0000FFFF -#define I2S_STMPWSET_VALUE_S 0 +#define I2S_STMPWSET_VALUE_W 16 +#define I2S_STMPWSET_VALUE_M 0x0000FFFF +#define I2S_STMPWSET_VALUE_S 0 //***************************************************************************** // @@ -627,9 +627,9 @@ // operation, this will be taken into account. // To add a negative value, write "STMPWPER.VALUE - value". // -#define I2S_STMPWADD_VALUE_INC_W 16 -#define I2S_STMPWADD_VALUE_INC_M 0x0000FFFF -#define I2S_STMPWADD_VALUE_INC_S 0 +#define I2S_STMPWADD_VALUE_INC_W 16 +#define I2S_STMPWADD_VALUE_INC_M 0x0000FFFF +#define I2S_STMPWADD_VALUE_INC_S 0 //***************************************************************************** // @@ -644,9 +644,9 @@ // value written. // The minimum value can be used to detect extra WCLK pulses (this registers // value will be significantly smaller than STMPXPER.VALUE). -#define I2S_STMPXPERMIN_VALUE_W 16 -#define I2S_STMPXPERMIN_VALUE_M 0x0000FFFF -#define I2S_STMPXPERMIN_VALUE_S 0 +#define I2S_STMPXPERMIN_VALUE_W 16 +#define I2S_STMPXPERMIN_VALUE_M 0x0000FFFF +#define I2S_STMPXPERMIN_VALUE_S 0 //***************************************************************************** // @@ -656,9 +656,9 @@ // Field: [15:0] CURR_VALUE // // Current value of the WCLK counter -#define I2S_STMPWCNT_CURR_VALUE_W 16 -#define I2S_STMPWCNT_CURR_VALUE_M 0x0000FFFF -#define I2S_STMPWCNT_CURR_VALUE_S 0 +#define I2S_STMPWCNT_CURR_VALUE_W 16 +#define I2S_STMPWCNT_CURR_VALUE_M 0x0000FFFF +#define I2S_STMPWCNT_CURR_VALUE_S 0 //***************************************************************************** // @@ -668,9 +668,9 @@ // Field: [15:0] CURR_VALUE // // Current value of the XOSC counter, latched when reading STMPWCNT. -#define I2S_STMPXCNT_CURR_VALUE_W 16 -#define I2S_STMPXCNT_CURR_VALUE_M 0x0000FFFF -#define I2S_STMPXCNT_CURR_VALUE_S 0 +#define I2S_STMPXCNT_CURR_VALUE_W 16 +#define I2S_STMPXCNT_CURR_VALUE_M 0x0000FFFF +#define I2S_STMPXCNT_CURR_VALUE_S 0 //***************************************************************************** // @@ -680,9 +680,9 @@ // Field: [15:0] CAPT_VALUE // // Internal. Only to be used through TI provided API. -#define I2S_STMPXCNTCAPT1_CAPT_VALUE_W 16 -#define I2S_STMPXCNTCAPT1_CAPT_VALUE_M 0x0000FFFF -#define I2S_STMPXCNTCAPT1_CAPT_VALUE_S 0 +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_W 16 +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_S 0 //***************************************************************************** // @@ -692,9 +692,9 @@ // Field: [15:0] CAPT_VALUE // // Internal. Only to be used through TI provided API. -#define I2S_STMPWCNTCAPT1_CAPT_VALUE_W 16 -#define I2S_STMPWCNTCAPT1_CAPT_VALUE_M 0x0000FFFF -#define I2S_STMPWCNTCAPT1_CAPT_VALUE_S 0 +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_W 16 +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_S 0 //***************************************************************************** // @@ -707,10 +707,10 @@ // // 0: Disable // 1: Enable -#define I2S_IRQMASK_AIF_DMA_IN 0x00000020 -#define I2S_IRQMASK_AIF_DMA_IN_BITN 5 -#define I2S_IRQMASK_AIF_DMA_IN_M 0x00000020 -#define I2S_IRQMASK_AIF_DMA_IN_S 5 +#define I2S_IRQMASK_AIF_DMA_IN 0x00000020 +#define I2S_IRQMASK_AIF_DMA_IN_BITN 5 +#define I2S_IRQMASK_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQMASK_AIF_DMA_IN_S 5 // Field: [4] AIF_DMA_OUT // @@ -718,10 +718,10 @@ // // 0: Disable // 1: Enable -#define I2S_IRQMASK_AIF_DMA_OUT 0x00000010 -#define I2S_IRQMASK_AIF_DMA_OUT_BITN 4 -#define I2S_IRQMASK_AIF_DMA_OUT_M 0x00000010 -#define I2S_IRQMASK_AIF_DMA_OUT_S 4 +#define I2S_IRQMASK_AIF_DMA_OUT 0x00000010 +#define I2S_IRQMASK_AIF_DMA_OUT_BITN 4 +#define I2S_IRQMASK_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQMASK_AIF_DMA_OUT_S 4 // Field: [3] WCLK_TIMEOUT // @@ -729,10 +729,10 @@ // // 0: Disable // 1: Enable -#define I2S_IRQMASK_WCLK_TIMEOUT 0x00000008 -#define I2S_IRQMASK_WCLK_TIMEOUT_BITN 3 -#define I2S_IRQMASK_WCLK_TIMEOUT_M 0x00000008 -#define I2S_IRQMASK_WCLK_TIMEOUT_S 3 +#define I2S_IRQMASK_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQMASK_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQMASK_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQMASK_WCLK_TIMEOUT_S 3 // Field: [2] BUS_ERR // @@ -740,10 +740,10 @@ // // 0: Disable // 1: Enable -#define I2S_IRQMASK_BUS_ERR 0x00000004 -#define I2S_IRQMASK_BUS_ERR_BITN 2 -#define I2S_IRQMASK_BUS_ERR_M 0x00000004 -#define I2S_IRQMASK_BUS_ERR_S 2 +#define I2S_IRQMASK_BUS_ERR 0x00000004 +#define I2S_IRQMASK_BUS_ERR_BITN 2 +#define I2S_IRQMASK_BUS_ERR_M 0x00000004 +#define I2S_IRQMASK_BUS_ERR_S 2 // Field: [1] WCLK_ERR // @@ -751,10 +751,10 @@ // // 0: Disable // 1: Enable -#define I2S_IRQMASK_WCLK_ERR 0x00000002 -#define I2S_IRQMASK_WCLK_ERR_BITN 1 -#define I2S_IRQMASK_WCLK_ERR_M 0x00000002 -#define I2S_IRQMASK_WCLK_ERR_S 1 +#define I2S_IRQMASK_WCLK_ERR 0x00000002 +#define I2S_IRQMASK_WCLK_ERR_BITN 1 +#define I2S_IRQMASK_WCLK_ERR_M 0x00000002 +#define I2S_IRQMASK_WCLK_ERR_S 1 // Field: [0] PTR_ERR // @@ -762,10 +762,10 @@ // // 0: Disable // 1: Enable -#define I2S_IRQMASK_PTR_ERR 0x00000001 -#define I2S_IRQMASK_PTR_ERR_BITN 0 -#define I2S_IRQMASK_PTR_ERR_M 0x00000001 -#define I2S_IRQMASK_PTR_ERR_S 0 +#define I2S_IRQMASK_PTR_ERR 0x00000001 +#define I2S_IRQMASK_PTR_ERR_BITN 0 +#define I2S_IRQMASK_PTR_ERR_M 0x00000001 +#define I2S_IRQMASK_PTR_ERR_S 0 //***************************************************************************** // @@ -777,20 +777,20 @@ // Set when condition for this bit field event occurs (auto cleared when input // pointer is updated - AIFINPTRNEXT), see description of AIFINPTRNEXT register // for details. -#define I2S_IRQFLAGS_AIF_DMA_IN 0x00000020 -#define I2S_IRQFLAGS_AIF_DMA_IN_BITN 5 -#define I2S_IRQFLAGS_AIF_DMA_IN_M 0x00000020 -#define I2S_IRQFLAGS_AIF_DMA_IN_S 5 +#define I2S_IRQFLAGS_AIF_DMA_IN 0x00000020 +#define I2S_IRQFLAGS_AIF_DMA_IN_BITN 5 +#define I2S_IRQFLAGS_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQFLAGS_AIF_DMA_IN_S 5 // Field: [4] AIF_DMA_OUT // // Set when condition for this bit field event occurs (auto cleared when output // pointer is updated - AIFOUTPTRNEXT), see description of AIFOUTPTRNEXT // register for details -#define I2S_IRQFLAGS_AIF_DMA_OUT 0x00000010 -#define I2S_IRQFLAGS_AIF_DMA_OUT_BITN 4 -#define I2S_IRQFLAGS_AIF_DMA_OUT_M 0x00000010 -#define I2S_IRQFLAGS_AIF_DMA_OUT_S 4 +#define I2S_IRQFLAGS_AIF_DMA_OUT 0x00000010 +#define I2S_IRQFLAGS_AIF_DMA_OUT_BITN 4 +#define I2S_IRQFLAGS_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQFLAGS_AIF_DMA_OUT_S 4 // Field: [3] WCLK_TIMEOUT // @@ -800,10 +800,10 @@ // // The bit is sticky and may only be cleared by software (by writing '1' to // IRQCLR.WCLK_TIMEOUT). -#define I2S_IRQFLAGS_WCLK_TIMEOUT 0x00000008 -#define I2S_IRQFLAGS_WCLK_TIMEOUT_BITN 3 -#define I2S_IRQFLAGS_WCLK_TIMEOUT_M 0x00000008 -#define I2S_IRQFLAGS_WCLK_TIMEOUT_S 3 +#define I2S_IRQFLAGS_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_S 3 // Field: [2] BUS_ERR // @@ -815,10 +815,10 @@ // // Note that DMA initiated transactions to illegal addresses will not trigger // an interrupt. The response to such transactions is undefined. -#define I2S_IRQFLAGS_BUS_ERR 0x00000004 -#define I2S_IRQFLAGS_BUS_ERR_BITN 2 -#define I2S_IRQFLAGS_BUS_ERR_M 0x00000004 -#define I2S_IRQFLAGS_BUS_ERR_S 2 +#define I2S_IRQFLAGS_BUS_ERR 0x00000004 +#define I2S_IRQFLAGS_BUS_ERR_BITN 2 +#define I2S_IRQFLAGS_BUS_ERR_M 0x00000004 +#define I2S_IRQFLAGS_BUS_ERR_S 2 // Field: [1] WCLK_ERR // @@ -832,10 +832,10 @@ // This error requires a complete restart since word synchronization has been // lost. The bit is sticky and may only be cleared by software (by writing '1' // to IRQCLR.WCLK_ERR). -#define I2S_IRQFLAGS_WCLK_ERR 0x00000002 -#define I2S_IRQFLAGS_WCLK_ERR_BITN 1 -#define I2S_IRQFLAGS_WCLK_ERR_M 0x00000002 -#define I2S_IRQFLAGS_WCLK_ERR_S 1 +#define I2S_IRQFLAGS_WCLK_ERR 0x00000002 +#define I2S_IRQFLAGS_WCLK_ERR_BITN 1 +#define I2S_IRQFLAGS_WCLK_ERR_M 0x00000002 +#define I2S_IRQFLAGS_WCLK_ERR_S 1 // Field: [0] PTR_ERR // @@ -844,10 +844,10 @@ // This error requires a complete restart since word synchronization has been // lost. The bit is sticky and may only be cleared by software (by writing '1' // to IRQCLR.PTR_ERR). -#define I2S_IRQFLAGS_PTR_ERR 0x00000001 -#define I2S_IRQFLAGS_PTR_ERR_BITN 0 -#define I2S_IRQFLAGS_PTR_ERR_M 0x00000001 -#define I2S_IRQFLAGS_PTR_ERR_S 0 +#define I2S_IRQFLAGS_PTR_ERR 0x00000001 +#define I2S_IRQFLAGS_PTR_ERR_BITN 0 +#define I2S_IRQFLAGS_PTR_ERR_M 0x00000001 +#define I2S_IRQFLAGS_PTR_ERR_S 0 //***************************************************************************** // @@ -858,51 +858,51 @@ // // 1: Sets the interrupt of IRQFLAGS.AIF_DMA_IN (unless a auto clear criteria // was given at the same time, in which the set will be ignored) -#define I2S_IRQSET_AIF_DMA_IN 0x00000020 -#define I2S_IRQSET_AIF_DMA_IN_BITN 5 -#define I2S_IRQSET_AIF_DMA_IN_M 0x00000020 -#define I2S_IRQSET_AIF_DMA_IN_S 5 +#define I2S_IRQSET_AIF_DMA_IN 0x00000020 +#define I2S_IRQSET_AIF_DMA_IN_BITN 5 +#define I2S_IRQSET_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQSET_AIF_DMA_IN_S 5 // Field: [4] AIF_DMA_OUT // // 1: Sets the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a auto clear criteria // was given at the same time, in which the set will be ignored) -#define I2S_IRQSET_AIF_DMA_OUT 0x00000010 -#define I2S_IRQSET_AIF_DMA_OUT_BITN 4 -#define I2S_IRQSET_AIF_DMA_OUT_M 0x00000010 -#define I2S_IRQSET_AIF_DMA_OUT_S 4 +#define I2S_IRQSET_AIF_DMA_OUT 0x00000010 +#define I2S_IRQSET_AIF_DMA_OUT_BITN 4 +#define I2S_IRQSET_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQSET_AIF_DMA_OUT_S 4 // Field: [3] WCLK_TIMEOUT // // 1: Sets the interrupt of IRQFLAGS.WCLK_TIMEOUT -#define I2S_IRQSET_WCLK_TIMEOUT 0x00000008 -#define I2S_IRQSET_WCLK_TIMEOUT_BITN 3 -#define I2S_IRQSET_WCLK_TIMEOUT_M 0x00000008 -#define I2S_IRQSET_WCLK_TIMEOUT_S 3 +#define I2S_IRQSET_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQSET_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQSET_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQSET_WCLK_TIMEOUT_S 3 // Field: [2] BUS_ERR // // 1: Sets the interrupt of IRQFLAGS.BUS_ERR -#define I2S_IRQSET_BUS_ERR 0x00000004 -#define I2S_IRQSET_BUS_ERR_BITN 2 -#define I2S_IRQSET_BUS_ERR_M 0x00000004 -#define I2S_IRQSET_BUS_ERR_S 2 +#define I2S_IRQSET_BUS_ERR 0x00000004 +#define I2S_IRQSET_BUS_ERR_BITN 2 +#define I2S_IRQSET_BUS_ERR_M 0x00000004 +#define I2S_IRQSET_BUS_ERR_S 2 // Field: [1] WCLK_ERR // // 1: Sets the interrupt of IRQFLAGS.WCLK_ERR -#define I2S_IRQSET_WCLK_ERR 0x00000002 -#define I2S_IRQSET_WCLK_ERR_BITN 1 -#define I2S_IRQSET_WCLK_ERR_M 0x00000002 -#define I2S_IRQSET_WCLK_ERR_S 1 +#define I2S_IRQSET_WCLK_ERR 0x00000002 +#define I2S_IRQSET_WCLK_ERR_BITN 1 +#define I2S_IRQSET_WCLK_ERR_M 0x00000002 +#define I2S_IRQSET_WCLK_ERR_S 1 // Field: [0] PTR_ERR // // 1: Sets the interrupt of IRQFLAGS.PTR_ERR -#define I2S_IRQSET_PTR_ERR 0x00000001 -#define I2S_IRQSET_PTR_ERR_BITN 0 -#define I2S_IRQSET_PTR_ERR_M 0x00000001 -#define I2S_IRQSET_PTR_ERR_S 0 +#define I2S_IRQSET_PTR_ERR 0x00000001 +#define I2S_IRQSET_PTR_ERR_BITN 0 +#define I2S_IRQSET_PTR_ERR_M 0x00000001 +#define I2S_IRQSET_PTR_ERR_S 0 //***************************************************************************** // @@ -913,55 +913,54 @@ // // 1: Clears the interrupt of IRQFLAGS.AIF_DMA_IN (unless a set criteria was // given at the same time in which the clear will be ignored) -#define I2S_IRQCLR_AIF_DMA_IN 0x00000020 -#define I2S_IRQCLR_AIF_DMA_IN_BITN 5 -#define I2S_IRQCLR_AIF_DMA_IN_M 0x00000020 -#define I2S_IRQCLR_AIF_DMA_IN_S 5 +#define I2S_IRQCLR_AIF_DMA_IN 0x00000020 +#define I2S_IRQCLR_AIF_DMA_IN_BITN 5 +#define I2S_IRQCLR_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQCLR_AIF_DMA_IN_S 5 // Field: [4] AIF_DMA_OUT // // 1: Clears the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a set criteria was // given at the same time in which the clear will be ignored) -#define I2S_IRQCLR_AIF_DMA_OUT 0x00000010 -#define I2S_IRQCLR_AIF_DMA_OUT_BITN 4 -#define I2S_IRQCLR_AIF_DMA_OUT_M 0x00000010 -#define I2S_IRQCLR_AIF_DMA_OUT_S 4 +#define I2S_IRQCLR_AIF_DMA_OUT 0x00000010 +#define I2S_IRQCLR_AIF_DMA_OUT_BITN 4 +#define I2S_IRQCLR_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQCLR_AIF_DMA_OUT_S 4 // Field: [3] WCLK_TIMEOUT // // 1: Clears the interrupt of IRQFLAGS.WCLK_TIMEOUT (unless a set criteria was // given at the same time in which the clear will be ignored) -#define I2S_IRQCLR_WCLK_TIMEOUT 0x00000008 -#define I2S_IRQCLR_WCLK_TIMEOUT_BITN 3 -#define I2S_IRQCLR_WCLK_TIMEOUT_M 0x00000008 -#define I2S_IRQCLR_WCLK_TIMEOUT_S 3 +#define I2S_IRQCLR_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQCLR_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQCLR_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQCLR_WCLK_TIMEOUT_S 3 // Field: [2] BUS_ERR // // 1: Clears the interrupt of IRQFLAGS.BUS_ERR (unless a set criteria was given // at the same time in which the clear will be ignored) -#define I2S_IRQCLR_BUS_ERR 0x00000004 -#define I2S_IRQCLR_BUS_ERR_BITN 2 -#define I2S_IRQCLR_BUS_ERR_M 0x00000004 -#define I2S_IRQCLR_BUS_ERR_S 2 +#define I2S_IRQCLR_BUS_ERR 0x00000004 +#define I2S_IRQCLR_BUS_ERR_BITN 2 +#define I2S_IRQCLR_BUS_ERR_M 0x00000004 +#define I2S_IRQCLR_BUS_ERR_S 2 // Field: [1] WCLK_ERR // // 1: Clears the interrupt of IRQFLAGS.WCLK_ERR (unless a set criteria was // given at the same time in which the clear will be ignored) -#define I2S_IRQCLR_WCLK_ERR 0x00000002 -#define I2S_IRQCLR_WCLK_ERR_BITN 1 -#define I2S_IRQCLR_WCLK_ERR_M 0x00000002 -#define I2S_IRQCLR_WCLK_ERR_S 1 +#define I2S_IRQCLR_WCLK_ERR 0x00000002 +#define I2S_IRQCLR_WCLK_ERR_BITN 1 +#define I2S_IRQCLR_WCLK_ERR_M 0x00000002 +#define I2S_IRQCLR_WCLK_ERR_S 1 // Field: [0] PTR_ERR // // 1: Clears the interrupt of IRQFLAGS.PTR_ERR (unless a set criteria was given // at the same time in which the clear will be ignored) -#define I2S_IRQCLR_PTR_ERR 0x00000001 -#define I2S_IRQCLR_PTR_ERR_BITN 0 -#define I2S_IRQCLR_PTR_ERR_M 0x00000001 -#define I2S_IRQCLR_PTR_ERR_S 0 - +#define I2S_IRQCLR_PTR_ERR 0x00000001 +#define I2S_IRQCLR_PTR_ERR_BITN 0 +#define I2S_IRQCLR_PTR_ERR_M 0x00000001 +#define I2S_IRQCLR_PTR_ERR_S 0 #endif // __I2S__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ints.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ints.h index 6ded7b6..4b2d9e8 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ints.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ints.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_ints_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_ints_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_INTS_H__ #define __HW_INTS_H__ @@ -42,60 +42,60 @@ // The following are defines for the interrupt assignments. // //***************************************************************************** -#define INT_NMI_FAULT 2 // NMI Fault -#define INT_HARD_FAULT 3 // Hard Fault -#define INT_MEMMANAGE_FAULT 4 // Memory Management (MemManage) +#define INT_NMI_FAULT 2 // NMI Fault +#define INT_HARD_FAULT 3 // Hard Fault +#define INT_MEMMANAGE_FAULT 4 // Memory Management (MemManage) // Fault -#define INT_BUS_FAULT 5 // Bus Fault -#define INT_USAGE_FAULT 6 // Usage Fault -#define INT_SVCALL 11 // Supervisor Call (SVCall) -#define INT_DEBUG 12 // Debug Monitor -#define INT_PENDSV 14 // Pending Service Call (PendSV) -#define INT_SYSTICK 15 // SysTick Interrupt from the +#define INT_BUS_FAULT 5 // Bus Fault +#define INT_USAGE_FAULT 6 // Usage Fault +#define INT_SVCALL 11 // Supervisor Call (SVCall) +#define INT_DEBUG 12 // Debug Monitor +#define INT_PENDSV 14 // Pending Service Call (PendSV) +#define INT_SYSTICK 15 // SysTick Interrupt from the // System Timer in NVIC. -#define INT_AON_GPIO_EDGE 16 // Edge detect event from IOC -#define INT_I2C_IRQ 17 // Interrupt event from I2C -#define INT_RFC_CPE_1 18 // Combined Interrupt for CPE +#define INT_AON_GPIO_EDGE 16 // Edge detect event from IOC +#define INT_I2C_IRQ 17 // Interrupt event from I2C +#define INT_RFC_CPE_1 18 // Combined Interrupt for CPE // Generated events -#define INT_PKA_IRQ 19 // PKA Interrupt event -#define INT_AON_RTC_COMB 20 // Event from AON_RTC -#define INT_UART0_COMB 21 // UART0 combined interrupt -#define INT_AUX_SWEV0 22 // AUX software event 0 -#define INT_SSI0_COMB 23 // SSI0 combined interrupt -#define INT_SSI1_COMB 24 // SSI1 combined interrupt -#define INT_RFC_CPE_0 25 // Combined Interrupt for CPE +#define INT_PKA_IRQ 19 // PKA Interrupt event +#define INT_AON_RTC_COMB 20 // Event from AON_RTC +#define INT_UART0_COMB 21 // UART0 combined interrupt +#define INT_AUX_SWEV0 22 // AUX software event 0 +#define INT_SSI0_COMB 23 // SSI0 combined interrupt +#define INT_SSI1_COMB 24 // SSI1 combined interrupt +#define INT_RFC_CPE_0 25 // Combined Interrupt for CPE // Generated events -#define INT_RFC_HW_COMB 26 // Combined RFC hardware interrupt -#define INT_RFC_CMD_ACK 27 // RFC Doorbell Command +#define INT_RFC_HW_COMB 26 // Combined RFC hardware interrupt +#define INT_RFC_CMD_ACK 27 // RFC Doorbell Command // Acknowledgement Interrupt -#define INT_I2S_IRQ 28 // Interrupt event from I2S -#define INT_AUX_SWEV1 29 // AUX software event 1 -#define INT_WDT_IRQ 30 // Watchdog interrupt event -#define INT_GPT0A 31 // GPT0A interrupt event -#define INT_GPT0B 32 // GPT0B interrupt event -#define INT_GPT1A 33 // GPT1A interrupt event -#define INT_GPT1B 34 // GPT1B interrupt event -#define INT_GPT2A 35 // GPT2A interrupt event -#define INT_GPT2B 36 // GPT2B interrupt event -#define INT_GPT3A 37 // GPT3A interrupt event -#define INT_GPT3B 38 // GPT3B interrupt event -#define INT_CRYPTO_RESULT_AVAIL_IRQ 39 // CRYPTO result available interupt +#define INT_I2S_IRQ 28 // Interrupt event from I2S +#define INT_AUX_SWEV1 29 // AUX software event 1 +#define INT_WDT_IRQ 30 // Watchdog interrupt event +#define INT_GPT0A 31 // GPT0A interrupt event +#define INT_GPT0B 32 // GPT0B interrupt event +#define INT_GPT1A 33 // GPT1A interrupt event +#define INT_GPT1B 34 // GPT1B interrupt event +#define INT_GPT2A 35 // GPT2A interrupt event +#define INT_GPT2B 36 // GPT2B interrupt event +#define INT_GPT3A 37 // GPT3A interrupt event +#define INT_GPT3B 38 // GPT3B interrupt event +#define INT_CRYPTO_RESULT_AVAIL_IRQ 39 // CRYPTO result available interupt // event -#define INT_DMA_DONE_COMB 40 // Combined DMA done -#define INT_DMA_ERR 41 // DMA bus error -#define INT_FLASH 42 // FLASH controller error event -#define INT_SWEV0 43 // Software event 0 -#define INT_AUX_COMB 44 // AUX combined event -#define INT_AON_PROG0 45 // AON programmable event 0 -#define INT_PROG0 46 // Programmable Interrupt 0 -#define INT_AUX_COMPA 47 // AUX Compare A event -#define INT_AUX_ADC_IRQ 48 // AUX ADC interrupt event -#define INT_TRNG_IRQ 49 // TRNG Interrupt event -#define INT_OSC_COMB 50 // Combined event from Oscillator +#define INT_DMA_DONE_COMB 40 // Combined DMA done +#define INT_DMA_ERR 41 // DMA bus error +#define INT_FLASH 42 // FLASH controller error event +#define INT_SWEV0 43 // Software event 0 +#define INT_AUX_COMB 44 // AUX combined event +#define INT_AON_PROG0 45 // AON programmable event 0 +#define INT_PROG0 46 // Programmable Interrupt 0 +#define INT_AUX_COMPA 47 // AUX Compare A event +#define INT_AUX_ADC_IRQ 48 // AUX ADC interrupt event +#define INT_TRNG_IRQ 49 // TRNG Interrupt event +#define INT_OSC_COMB 50 // Combined event from Oscillator // control -#define INT_AUX_TIMER2_EV0 51 // AUX Timer2 event 0 -#define INT_UART1_COMB 52 // UART1 combined interrupt -#define INT_BATMON_COMB 53 // Combined event from battery +#define INT_AUX_TIMER2_EV0 51 // AUX Timer2 event 0 +#define INT_UART1_COMB 52 // UART1 combined interrupt +#define INT_BATMON_COMB 53 // Combined event from battery // monitor //***************************************************************************** @@ -103,10 +103,9 @@ // The following are defines for number of interrupts and priority levels. // //***************************************************************************** -#define NUM_INTERRUPTS 54 // Number of interrupts -#define NUM_PRIORITY_BITS 3 // Number of Priority bits -#define NUM_PRIORITY 8 // Number of priority levels - +#define NUM_INTERRUPTS 54 // Number of interrupts +#define NUM_PRIORITY_BITS 3 // Number of Priority bits +#define NUM_PRIORITY 8 // Number of priority levels //***************************************************************************** // @@ -114,7 +113,7 @@ // //***************************************************************************** -#define INT_AON_AUX_SWEV0 INT_AUX_SWEV0 -#define INT_AON_AUX_SWEV1 INT_AUX_SWEV1 +#define INT_AON_AUX_SWEV0 INT_AUX_SWEV0 +#define INT_AON_AUX_SWEV1 INT_AUX_SWEV1 #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ioc.h index 53ab201..eca7701 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ioc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ioc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_ioc_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_ioc_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_IOC_H__ #define __HW_IOC_H__ @@ -44,100 +44,100 @@ // //***************************************************************************** // Configuration of DIO0 -#define IOC_O_IOCFG0 0x00000000 +#define IOC_O_IOCFG0 0x00000000 // Configuration of DIO1 -#define IOC_O_IOCFG1 0x00000004 +#define IOC_O_IOCFG1 0x00000004 // Configuration of DIO2 -#define IOC_O_IOCFG2 0x00000008 +#define IOC_O_IOCFG2 0x00000008 // Configuration of DIO3 -#define IOC_O_IOCFG3 0x0000000C +#define IOC_O_IOCFG3 0x0000000C // Configuration of DIO4 -#define IOC_O_IOCFG4 0x00000010 +#define IOC_O_IOCFG4 0x00000010 // Configuration of DIO5 -#define IOC_O_IOCFG5 0x00000014 +#define IOC_O_IOCFG5 0x00000014 // Configuration of DIO6 -#define IOC_O_IOCFG6 0x00000018 +#define IOC_O_IOCFG6 0x00000018 // Configuration of DIO7 -#define IOC_O_IOCFG7 0x0000001C +#define IOC_O_IOCFG7 0x0000001C // Configuration of DIO8 -#define IOC_O_IOCFG8 0x00000020 +#define IOC_O_IOCFG8 0x00000020 // Configuration of DIO9 -#define IOC_O_IOCFG9 0x00000024 +#define IOC_O_IOCFG9 0x00000024 // Configuration of DIO10 -#define IOC_O_IOCFG10 0x00000028 +#define IOC_O_IOCFG10 0x00000028 // Configuration of DIO11 -#define IOC_O_IOCFG11 0x0000002C +#define IOC_O_IOCFG11 0x0000002C // Configuration of DIO12 -#define IOC_O_IOCFG12 0x00000030 +#define IOC_O_IOCFG12 0x00000030 // Configuration of DIO13 -#define IOC_O_IOCFG13 0x00000034 +#define IOC_O_IOCFG13 0x00000034 // Configuration of DIO14 -#define IOC_O_IOCFG14 0x00000038 +#define IOC_O_IOCFG14 0x00000038 // Configuration of DIO15 -#define IOC_O_IOCFG15 0x0000003C +#define IOC_O_IOCFG15 0x0000003C // Configuration of DIO16 -#define IOC_O_IOCFG16 0x00000040 +#define IOC_O_IOCFG16 0x00000040 // Configuration of DIO17 -#define IOC_O_IOCFG17 0x00000044 +#define IOC_O_IOCFG17 0x00000044 // Configuration of DIO18 -#define IOC_O_IOCFG18 0x00000048 +#define IOC_O_IOCFG18 0x00000048 // Configuration of DIO19 -#define IOC_O_IOCFG19 0x0000004C +#define IOC_O_IOCFG19 0x0000004C // Configuration of DIO20 -#define IOC_O_IOCFG20 0x00000050 +#define IOC_O_IOCFG20 0x00000050 // Configuration of DIO21 -#define IOC_O_IOCFG21 0x00000054 +#define IOC_O_IOCFG21 0x00000054 // Configuration of DIO22 -#define IOC_O_IOCFG22 0x00000058 +#define IOC_O_IOCFG22 0x00000058 // Configuration of DIO23 -#define IOC_O_IOCFG23 0x0000005C +#define IOC_O_IOCFG23 0x0000005C // Configuration of DIO24 -#define IOC_O_IOCFG24 0x00000060 +#define IOC_O_IOCFG24 0x00000060 // Configuration of DIO25 -#define IOC_O_IOCFG25 0x00000064 +#define IOC_O_IOCFG25 0x00000064 // Configuration of DIO26 -#define IOC_O_IOCFG26 0x00000068 +#define IOC_O_IOCFG26 0x00000068 // Configuration of DIO27 -#define IOC_O_IOCFG27 0x0000006C +#define IOC_O_IOCFG27 0x0000006C // Configuration of DIO28 -#define IOC_O_IOCFG28 0x00000070 +#define IOC_O_IOCFG28 0x00000070 // Configuration of DIO29 -#define IOC_O_IOCFG29 0x00000074 +#define IOC_O_IOCFG29 0x00000074 // Configuration of DIO30 -#define IOC_O_IOCFG30 0x00000078 +#define IOC_O_IOCFG30 0x00000078 // Configuration of DIO31 -#define IOC_O_IOCFG31 0x0000007C +#define IOC_O_IOCFG31 0x0000007C //***************************************************************************** // @@ -148,10 +148,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG0_HYST_EN 0x40000000 -#define IOC_IOCFG0_HYST_EN_BITN 30 -#define IOC_IOCFG0_HYST_EN_M 0x40000000 -#define IOC_IOCFG0_HYST_EN_S 30 +#define IOC_IOCFG0_HYST_EN 0x40000000 +#define IOC_IOCFG0_HYST_EN_BITN 30 +#define IOC_IOCFG0_HYST_EN_M 0x40000000 +#define IOC_IOCFG0_HYST_EN_S 30 // Field: [29] IE // @@ -160,10 +160,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG0_IE 0x20000000 -#define IOC_IOCFG0_IE_BITN 29 -#define IOC_IOCFG0_IE_M 0x20000000 -#define IOC_IOCFG0_IE_S 29 +#define IOC_IOCFG0_IE 0x20000000 +#define IOC_IOCFG0_IE_BITN 29 +#define IOC_IOCFG0_IE_M 0x20000000 +#define IOC_IOCFG0_IE_S 29 // Field: [28:27] WU_CFG // @@ -185,9 +185,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG0_WU_CFG_W 2 -#define IOC_IOCFG0_WU_CFG_M 0x18000000 -#define IOC_IOCFG0_WU_CFG_S 27 +#define IOC_IOCFG0_WU_CFG_W 2 +#define IOC_IOCFG0_WU_CFG_M 0x18000000 +#define IOC_IOCFG0_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -209,15 +209,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG0_IOMODE_W 3 -#define IOC_IOCFG0_IOMODE_M 0x07000000 -#define IOC_IOCFG0_IOMODE_S 24 -#define IOC_IOCFG0_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG0_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG0_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG0_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG0_IOMODE_INV 0x01000000 -#define IOC_IOCFG0_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG0_IOMODE_W 3 +#define IOC_IOCFG0_IOMODE_M 0x07000000 +#define IOC_IOCFG0_IOMODE_S 24 +#define IOC_IOCFG0_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG0_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG0_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG0_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG0_IOMODE_INV 0x01000000 +#define IOC_IOCFG0_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -225,10 +225,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG0_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG0_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG0_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG0_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG0_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG0_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG0_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG0_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -236,10 +236,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG0_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG0_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG0_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG0_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG0_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG0_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG0_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG0_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -247,20 +247,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG0_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG0_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG0_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG0_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG0_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG0_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG0_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG0_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG0_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG0_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG0_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG0_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG0_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG0_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG0_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG0_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -270,13 +270,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG0_EDGE_DET_W 2 -#define IOC_IOCFG0_EDGE_DET_M 0x00030000 -#define IOC_IOCFG0_EDGE_DET_S 16 -#define IOC_IOCFG0_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG0_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG0_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG0_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG0_EDGE_DET_W 2 +#define IOC_IOCFG0_EDGE_DET_M 0x00030000 +#define IOC_IOCFG0_EDGE_DET_S 16 +#define IOC_IOCFG0_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG0_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG0_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG0_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -285,21 +285,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG0_PULL_CTL_W 2 -#define IOC_IOCFG0_PULL_CTL_M 0x00006000 -#define IOC_IOCFG0_PULL_CTL_S 13 -#define IOC_IOCFG0_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG0_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG0_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG0_PULL_CTL_W 2 +#define IOC_IOCFG0_PULL_CTL_M 0x00006000 +#define IOC_IOCFG0_PULL_CTL_S 13 +#define IOC_IOCFG0_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG0_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG0_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG0_SLEW_RED 0x00001000 -#define IOC_IOCFG0_SLEW_RED_BITN 12 -#define IOC_IOCFG0_SLEW_RED_M 0x00001000 -#define IOC_IOCFG0_SLEW_RED_S 12 +#define IOC_IOCFG0_SLEW_RED 0x00001000 +#define IOC_IOCFG0_SLEW_RED_BITN 12 +#define IOC_IOCFG0_SLEW_RED_M 0x00001000 +#define IOC_IOCFG0_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -312,12 +312,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG0_IOCURR_W 2 -#define IOC_IOCFG0_IOCURR_M 0x00000C00 -#define IOC_IOCFG0_IOCURR_S 10 -#define IOC_IOCFG0_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG0_IOCURR_4MA 0x00000400 -#define IOC_IOCFG0_IOCURR_2MA 0x00000000 +#define IOC_IOCFG0_IOCURR_W 2 +#define IOC_IOCFG0_IOCURR_M 0x00000C00 +#define IOC_IOCFG0_IOCURR_S 10 +#define IOC_IOCFG0_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG0_IOCURR_4MA 0x00000400 +#define IOC_IOCFG0_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -336,13 +336,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG0_IOSTR_W 2 -#define IOC_IOCFG0_IOSTR_M 0x00000300 -#define IOC_IOCFG0_IOSTR_S 8 -#define IOC_IOCFG0_IOSTR_MAX 0x00000300 -#define IOC_IOCFG0_IOSTR_MED 0x00000200 -#define IOC_IOCFG0_IOSTR_MIN 0x00000100 -#define IOC_IOCFG0_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG0_IOSTR_W 2 +#define IOC_IOCFG0_IOSTR_M 0x00000300 +#define IOC_IOCFG0_IOSTR_S 8 +#define IOC_IOCFG0_IOSTR_MAX 0x00000300 +#define IOC_IOCFG0_IOSTR_MED 0x00000200 +#define IOC_IOCFG0_IOSTR_MIN 0x00000100 +#define IOC_IOCFG0_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -350,10 +350,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG0_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG0_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG0_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG0_IOEV_RTC_EN_S 7 +#define IOC_IOCFG0_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG0_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG0_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG0_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -361,10 +361,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG0_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG0_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG0_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG0_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG0_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG0_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG0_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG0_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -456,55 +456,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG0_PORT_ID_W 6 -#define IOC_IOCFG0_PORT_ID_M 0x0000003F -#define IOC_IOCFG0_PORT_ID_S 0 -#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG0_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG0_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG0_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG0_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG0_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG0_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG0_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG0_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG0_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG0_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG0_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG0_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG0_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG0_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG0_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG0_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG0_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG0_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG0_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG0_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG0_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG0_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG0_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG0_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG0_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG0_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG0_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG0_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG0_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG0_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG0_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG0_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG0_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG0_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG0_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG0_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG0_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG0_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG0_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG0_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG0_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG0_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG0_PORT_ID_W 6 +#define IOC_IOCFG0_PORT_ID_M 0x0000003F +#define IOC_IOCFG0_PORT_ID_S 0 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG0_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG0_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG0_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG0_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG0_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG0_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG0_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG0_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG0_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG0_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG0_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG0_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG0_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG0_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG0_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG0_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG0_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG0_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG0_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG0_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG0_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG0_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG0_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG0_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG0_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG0_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG0_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG0_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG0_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG0_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG0_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG0_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG0_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG0_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG0_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG0_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG0_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG0_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG0_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -515,10 +515,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG1_HYST_EN 0x40000000 -#define IOC_IOCFG1_HYST_EN_BITN 30 -#define IOC_IOCFG1_HYST_EN_M 0x40000000 -#define IOC_IOCFG1_HYST_EN_S 30 +#define IOC_IOCFG1_HYST_EN 0x40000000 +#define IOC_IOCFG1_HYST_EN_BITN 30 +#define IOC_IOCFG1_HYST_EN_M 0x40000000 +#define IOC_IOCFG1_HYST_EN_S 30 // Field: [29] IE // @@ -527,10 +527,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG1_IE 0x20000000 -#define IOC_IOCFG1_IE_BITN 29 -#define IOC_IOCFG1_IE_M 0x20000000 -#define IOC_IOCFG1_IE_S 29 +#define IOC_IOCFG1_IE 0x20000000 +#define IOC_IOCFG1_IE_BITN 29 +#define IOC_IOCFG1_IE_M 0x20000000 +#define IOC_IOCFG1_IE_S 29 // Field: [28:27] WU_CFG // @@ -552,9 +552,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG1_WU_CFG_W 2 -#define IOC_IOCFG1_WU_CFG_M 0x18000000 -#define IOC_IOCFG1_WU_CFG_S 27 +#define IOC_IOCFG1_WU_CFG_W 2 +#define IOC_IOCFG1_WU_CFG_M 0x18000000 +#define IOC_IOCFG1_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -576,15 +576,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG1_IOMODE_W 3 -#define IOC_IOCFG1_IOMODE_M 0x07000000 -#define IOC_IOCFG1_IOMODE_S 24 -#define IOC_IOCFG1_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG1_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG1_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG1_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG1_IOMODE_INV 0x01000000 -#define IOC_IOCFG1_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG1_IOMODE_W 3 +#define IOC_IOCFG1_IOMODE_M 0x07000000 +#define IOC_IOCFG1_IOMODE_S 24 +#define IOC_IOCFG1_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG1_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG1_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG1_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG1_IOMODE_INV 0x01000000 +#define IOC_IOCFG1_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -592,10 +592,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG1_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG1_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG1_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG1_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG1_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG1_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG1_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG1_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -603,10 +603,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG1_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG1_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG1_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG1_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG1_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG1_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG1_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG1_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -614,20 +614,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG1_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG1_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG1_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG1_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG1_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG1_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG1_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG1_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG1_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG1_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG1_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG1_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG1_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG1_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG1_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG1_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -637,13 +637,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG1_EDGE_DET_W 2 -#define IOC_IOCFG1_EDGE_DET_M 0x00030000 -#define IOC_IOCFG1_EDGE_DET_S 16 -#define IOC_IOCFG1_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG1_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG1_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG1_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG1_EDGE_DET_W 2 +#define IOC_IOCFG1_EDGE_DET_M 0x00030000 +#define IOC_IOCFG1_EDGE_DET_S 16 +#define IOC_IOCFG1_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG1_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG1_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG1_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -652,21 +652,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG1_PULL_CTL_W 2 -#define IOC_IOCFG1_PULL_CTL_M 0x00006000 -#define IOC_IOCFG1_PULL_CTL_S 13 -#define IOC_IOCFG1_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG1_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG1_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG1_PULL_CTL_W 2 +#define IOC_IOCFG1_PULL_CTL_M 0x00006000 +#define IOC_IOCFG1_PULL_CTL_S 13 +#define IOC_IOCFG1_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG1_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG1_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG1_SLEW_RED 0x00001000 -#define IOC_IOCFG1_SLEW_RED_BITN 12 -#define IOC_IOCFG1_SLEW_RED_M 0x00001000 -#define IOC_IOCFG1_SLEW_RED_S 12 +#define IOC_IOCFG1_SLEW_RED 0x00001000 +#define IOC_IOCFG1_SLEW_RED_BITN 12 +#define IOC_IOCFG1_SLEW_RED_M 0x00001000 +#define IOC_IOCFG1_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -679,12 +679,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG1_IOCURR_W 2 -#define IOC_IOCFG1_IOCURR_M 0x00000C00 -#define IOC_IOCFG1_IOCURR_S 10 -#define IOC_IOCFG1_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG1_IOCURR_4MA 0x00000400 -#define IOC_IOCFG1_IOCURR_2MA 0x00000000 +#define IOC_IOCFG1_IOCURR_W 2 +#define IOC_IOCFG1_IOCURR_M 0x00000C00 +#define IOC_IOCFG1_IOCURR_S 10 +#define IOC_IOCFG1_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG1_IOCURR_4MA 0x00000400 +#define IOC_IOCFG1_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -703,13 +703,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG1_IOSTR_W 2 -#define IOC_IOCFG1_IOSTR_M 0x00000300 -#define IOC_IOCFG1_IOSTR_S 8 -#define IOC_IOCFG1_IOSTR_MAX 0x00000300 -#define IOC_IOCFG1_IOSTR_MED 0x00000200 -#define IOC_IOCFG1_IOSTR_MIN 0x00000100 -#define IOC_IOCFG1_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG1_IOSTR_W 2 +#define IOC_IOCFG1_IOSTR_M 0x00000300 +#define IOC_IOCFG1_IOSTR_S 8 +#define IOC_IOCFG1_IOSTR_MAX 0x00000300 +#define IOC_IOCFG1_IOSTR_MED 0x00000200 +#define IOC_IOCFG1_IOSTR_MIN 0x00000100 +#define IOC_IOCFG1_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -717,10 +717,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG1_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG1_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG1_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG1_IOEV_RTC_EN_S 7 +#define IOC_IOCFG1_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG1_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG1_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG1_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -728,10 +728,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG1_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG1_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG1_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG1_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG1_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG1_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG1_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG1_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -823,55 +823,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG1_PORT_ID_W 6 -#define IOC_IOCFG1_PORT_ID_M 0x0000003F -#define IOC_IOCFG1_PORT_ID_S 0 -#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG1_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG1_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG1_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG1_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG1_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG1_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG1_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG1_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG1_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG1_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG1_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG1_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG1_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG1_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG1_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG1_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG1_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG1_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG1_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG1_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG1_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG1_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG1_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG1_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG1_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG1_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG1_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG1_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG1_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG1_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG1_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG1_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG1_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG1_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG1_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG1_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG1_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG1_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG1_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG1_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG1_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG1_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG1_PORT_ID_W 6 +#define IOC_IOCFG1_PORT_ID_M 0x0000003F +#define IOC_IOCFG1_PORT_ID_S 0 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG1_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG1_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG1_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG1_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG1_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG1_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG1_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG1_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG1_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG1_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG1_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG1_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG1_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG1_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG1_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG1_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG1_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG1_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG1_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG1_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG1_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG1_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG1_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG1_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG1_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG1_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG1_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG1_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG1_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG1_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG1_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG1_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG1_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG1_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG1_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG1_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG1_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG1_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG1_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -882,10 +882,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG2_HYST_EN 0x40000000 -#define IOC_IOCFG2_HYST_EN_BITN 30 -#define IOC_IOCFG2_HYST_EN_M 0x40000000 -#define IOC_IOCFG2_HYST_EN_S 30 +#define IOC_IOCFG2_HYST_EN 0x40000000 +#define IOC_IOCFG2_HYST_EN_BITN 30 +#define IOC_IOCFG2_HYST_EN_M 0x40000000 +#define IOC_IOCFG2_HYST_EN_S 30 // Field: [29] IE // @@ -894,10 +894,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG2_IE 0x20000000 -#define IOC_IOCFG2_IE_BITN 29 -#define IOC_IOCFG2_IE_M 0x20000000 -#define IOC_IOCFG2_IE_S 29 +#define IOC_IOCFG2_IE 0x20000000 +#define IOC_IOCFG2_IE_BITN 29 +#define IOC_IOCFG2_IE_M 0x20000000 +#define IOC_IOCFG2_IE_S 29 // Field: [28:27] WU_CFG // @@ -919,9 +919,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG2_WU_CFG_W 2 -#define IOC_IOCFG2_WU_CFG_M 0x18000000 -#define IOC_IOCFG2_WU_CFG_S 27 +#define IOC_IOCFG2_WU_CFG_W 2 +#define IOC_IOCFG2_WU_CFG_M 0x18000000 +#define IOC_IOCFG2_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -943,15 +943,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG2_IOMODE_W 3 -#define IOC_IOCFG2_IOMODE_M 0x07000000 -#define IOC_IOCFG2_IOMODE_S 24 -#define IOC_IOCFG2_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG2_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG2_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG2_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG2_IOMODE_INV 0x01000000 -#define IOC_IOCFG2_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG2_IOMODE_W 3 +#define IOC_IOCFG2_IOMODE_M 0x07000000 +#define IOC_IOCFG2_IOMODE_S 24 +#define IOC_IOCFG2_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG2_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG2_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG2_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG2_IOMODE_INV 0x01000000 +#define IOC_IOCFG2_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -959,10 +959,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG2_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG2_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG2_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG2_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG2_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG2_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG2_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG2_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -970,10 +970,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG2_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG2_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG2_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG2_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG2_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG2_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG2_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG2_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -981,20 +981,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG2_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG2_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG2_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG2_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG2_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG2_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG2_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG2_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG2_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG2_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG2_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG2_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG2_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG2_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG2_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG2_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -1004,13 +1004,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG2_EDGE_DET_W 2 -#define IOC_IOCFG2_EDGE_DET_M 0x00030000 -#define IOC_IOCFG2_EDGE_DET_S 16 -#define IOC_IOCFG2_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG2_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG2_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG2_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG2_EDGE_DET_W 2 +#define IOC_IOCFG2_EDGE_DET_M 0x00030000 +#define IOC_IOCFG2_EDGE_DET_S 16 +#define IOC_IOCFG2_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG2_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG2_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG2_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -1019,21 +1019,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG2_PULL_CTL_W 2 -#define IOC_IOCFG2_PULL_CTL_M 0x00006000 -#define IOC_IOCFG2_PULL_CTL_S 13 -#define IOC_IOCFG2_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG2_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG2_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG2_PULL_CTL_W 2 +#define IOC_IOCFG2_PULL_CTL_M 0x00006000 +#define IOC_IOCFG2_PULL_CTL_S 13 +#define IOC_IOCFG2_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG2_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG2_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG2_SLEW_RED 0x00001000 -#define IOC_IOCFG2_SLEW_RED_BITN 12 -#define IOC_IOCFG2_SLEW_RED_M 0x00001000 -#define IOC_IOCFG2_SLEW_RED_S 12 +#define IOC_IOCFG2_SLEW_RED 0x00001000 +#define IOC_IOCFG2_SLEW_RED_BITN 12 +#define IOC_IOCFG2_SLEW_RED_M 0x00001000 +#define IOC_IOCFG2_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -1046,12 +1046,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG2_IOCURR_W 2 -#define IOC_IOCFG2_IOCURR_M 0x00000C00 -#define IOC_IOCFG2_IOCURR_S 10 -#define IOC_IOCFG2_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG2_IOCURR_4MA 0x00000400 -#define IOC_IOCFG2_IOCURR_2MA 0x00000000 +#define IOC_IOCFG2_IOCURR_W 2 +#define IOC_IOCFG2_IOCURR_M 0x00000C00 +#define IOC_IOCFG2_IOCURR_S 10 +#define IOC_IOCFG2_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG2_IOCURR_4MA 0x00000400 +#define IOC_IOCFG2_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -1070,13 +1070,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG2_IOSTR_W 2 -#define IOC_IOCFG2_IOSTR_M 0x00000300 -#define IOC_IOCFG2_IOSTR_S 8 -#define IOC_IOCFG2_IOSTR_MAX 0x00000300 -#define IOC_IOCFG2_IOSTR_MED 0x00000200 -#define IOC_IOCFG2_IOSTR_MIN 0x00000100 -#define IOC_IOCFG2_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG2_IOSTR_W 2 +#define IOC_IOCFG2_IOSTR_M 0x00000300 +#define IOC_IOCFG2_IOSTR_S 8 +#define IOC_IOCFG2_IOSTR_MAX 0x00000300 +#define IOC_IOCFG2_IOSTR_MED 0x00000200 +#define IOC_IOCFG2_IOSTR_MIN 0x00000100 +#define IOC_IOCFG2_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -1084,10 +1084,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG2_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG2_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG2_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG2_IOEV_RTC_EN_S 7 +#define IOC_IOCFG2_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG2_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG2_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG2_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -1095,10 +1095,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG2_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG2_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG2_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG2_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG2_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG2_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG2_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG2_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -1190,55 +1190,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG2_PORT_ID_W 6 -#define IOC_IOCFG2_PORT_ID_M 0x0000003F -#define IOC_IOCFG2_PORT_ID_S 0 -#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG2_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG2_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG2_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG2_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG2_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG2_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG2_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG2_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG2_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG2_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG2_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG2_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG2_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG2_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG2_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG2_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG2_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG2_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG2_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG2_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG2_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG2_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG2_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG2_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG2_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG2_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG2_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG2_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG2_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG2_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG2_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG2_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG2_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG2_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG2_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG2_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG2_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG2_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG2_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG2_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG2_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG2_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG2_PORT_ID_W 6 +#define IOC_IOCFG2_PORT_ID_M 0x0000003F +#define IOC_IOCFG2_PORT_ID_S 0 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG2_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG2_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG2_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG2_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG2_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG2_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG2_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG2_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG2_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG2_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG2_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG2_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG2_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG2_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG2_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG2_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG2_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG2_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG2_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG2_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG2_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG2_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG2_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG2_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG2_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG2_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG2_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG2_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG2_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG2_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG2_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG2_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG2_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG2_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG2_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG2_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG2_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG2_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG2_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -1249,10 +1249,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG3_HYST_EN 0x40000000 -#define IOC_IOCFG3_HYST_EN_BITN 30 -#define IOC_IOCFG3_HYST_EN_M 0x40000000 -#define IOC_IOCFG3_HYST_EN_S 30 +#define IOC_IOCFG3_HYST_EN 0x40000000 +#define IOC_IOCFG3_HYST_EN_BITN 30 +#define IOC_IOCFG3_HYST_EN_M 0x40000000 +#define IOC_IOCFG3_HYST_EN_S 30 // Field: [29] IE // @@ -1261,10 +1261,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG3_IE 0x20000000 -#define IOC_IOCFG3_IE_BITN 29 -#define IOC_IOCFG3_IE_M 0x20000000 -#define IOC_IOCFG3_IE_S 29 +#define IOC_IOCFG3_IE 0x20000000 +#define IOC_IOCFG3_IE_BITN 29 +#define IOC_IOCFG3_IE_M 0x20000000 +#define IOC_IOCFG3_IE_S 29 // Field: [28:27] WU_CFG // @@ -1286,9 +1286,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG3_WU_CFG_W 2 -#define IOC_IOCFG3_WU_CFG_M 0x18000000 -#define IOC_IOCFG3_WU_CFG_S 27 +#define IOC_IOCFG3_WU_CFG_W 2 +#define IOC_IOCFG3_WU_CFG_M 0x18000000 +#define IOC_IOCFG3_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -1310,15 +1310,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG3_IOMODE_W 3 -#define IOC_IOCFG3_IOMODE_M 0x07000000 -#define IOC_IOCFG3_IOMODE_S 24 -#define IOC_IOCFG3_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG3_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG3_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG3_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG3_IOMODE_INV 0x01000000 -#define IOC_IOCFG3_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG3_IOMODE_W 3 +#define IOC_IOCFG3_IOMODE_M 0x07000000 +#define IOC_IOCFG3_IOMODE_S 24 +#define IOC_IOCFG3_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG3_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG3_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG3_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG3_IOMODE_INV 0x01000000 +#define IOC_IOCFG3_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -1326,10 +1326,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG3_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG3_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG3_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG3_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG3_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG3_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG3_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG3_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -1337,10 +1337,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG3_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG3_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG3_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG3_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG3_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG3_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG3_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG3_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -1348,20 +1348,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG3_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG3_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG3_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG3_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG3_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG3_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG3_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG3_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG3_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG3_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG3_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG3_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG3_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG3_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG3_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG3_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -1371,13 +1371,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG3_EDGE_DET_W 2 -#define IOC_IOCFG3_EDGE_DET_M 0x00030000 -#define IOC_IOCFG3_EDGE_DET_S 16 -#define IOC_IOCFG3_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG3_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG3_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG3_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG3_EDGE_DET_W 2 +#define IOC_IOCFG3_EDGE_DET_M 0x00030000 +#define IOC_IOCFG3_EDGE_DET_S 16 +#define IOC_IOCFG3_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG3_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG3_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG3_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -1386,21 +1386,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG3_PULL_CTL_W 2 -#define IOC_IOCFG3_PULL_CTL_M 0x00006000 -#define IOC_IOCFG3_PULL_CTL_S 13 -#define IOC_IOCFG3_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG3_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG3_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG3_PULL_CTL_W 2 +#define IOC_IOCFG3_PULL_CTL_M 0x00006000 +#define IOC_IOCFG3_PULL_CTL_S 13 +#define IOC_IOCFG3_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG3_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG3_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG3_SLEW_RED 0x00001000 -#define IOC_IOCFG3_SLEW_RED_BITN 12 -#define IOC_IOCFG3_SLEW_RED_M 0x00001000 -#define IOC_IOCFG3_SLEW_RED_S 12 +#define IOC_IOCFG3_SLEW_RED 0x00001000 +#define IOC_IOCFG3_SLEW_RED_BITN 12 +#define IOC_IOCFG3_SLEW_RED_M 0x00001000 +#define IOC_IOCFG3_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -1413,12 +1413,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG3_IOCURR_W 2 -#define IOC_IOCFG3_IOCURR_M 0x00000C00 -#define IOC_IOCFG3_IOCURR_S 10 -#define IOC_IOCFG3_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG3_IOCURR_4MA 0x00000400 -#define IOC_IOCFG3_IOCURR_2MA 0x00000000 +#define IOC_IOCFG3_IOCURR_W 2 +#define IOC_IOCFG3_IOCURR_M 0x00000C00 +#define IOC_IOCFG3_IOCURR_S 10 +#define IOC_IOCFG3_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG3_IOCURR_4MA 0x00000400 +#define IOC_IOCFG3_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -1437,13 +1437,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG3_IOSTR_W 2 -#define IOC_IOCFG3_IOSTR_M 0x00000300 -#define IOC_IOCFG3_IOSTR_S 8 -#define IOC_IOCFG3_IOSTR_MAX 0x00000300 -#define IOC_IOCFG3_IOSTR_MED 0x00000200 -#define IOC_IOCFG3_IOSTR_MIN 0x00000100 -#define IOC_IOCFG3_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG3_IOSTR_W 2 +#define IOC_IOCFG3_IOSTR_M 0x00000300 +#define IOC_IOCFG3_IOSTR_S 8 +#define IOC_IOCFG3_IOSTR_MAX 0x00000300 +#define IOC_IOCFG3_IOSTR_MED 0x00000200 +#define IOC_IOCFG3_IOSTR_MIN 0x00000100 +#define IOC_IOCFG3_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -1451,10 +1451,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG3_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG3_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG3_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG3_IOEV_RTC_EN_S 7 +#define IOC_IOCFG3_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG3_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG3_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG3_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -1462,10 +1462,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG3_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG3_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG3_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG3_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG3_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG3_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG3_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG3_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -1557,55 +1557,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG3_PORT_ID_W 6 -#define IOC_IOCFG3_PORT_ID_M 0x0000003F -#define IOC_IOCFG3_PORT_ID_S 0 -#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG3_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG3_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG3_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG3_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG3_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG3_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG3_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG3_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG3_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG3_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG3_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG3_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG3_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG3_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG3_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG3_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG3_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG3_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG3_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG3_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG3_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG3_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG3_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG3_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG3_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG3_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG3_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG3_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG3_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG3_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG3_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG3_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG3_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG3_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG3_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG3_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG3_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG3_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG3_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG3_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG3_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG3_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG3_PORT_ID_W 6 +#define IOC_IOCFG3_PORT_ID_M 0x0000003F +#define IOC_IOCFG3_PORT_ID_S 0 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG3_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG3_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG3_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG3_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG3_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG3_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG3_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG3_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG3_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG3_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG3_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG3_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG3_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG3_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG3_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG3_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG3_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG3_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG3_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG3_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG3_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG3_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG3_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG3_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG3_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG3_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG3_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG3_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG3_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG3_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG3_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG3_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG3_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG3_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG3_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG3_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG3_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG3_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG3_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -1616,10 +1616,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG4_HYST_EN 0x40000000 -#define IOC_IOCFG4_HYST_EN_BITN 30 -#define IOC_IOCFG4_HYST_EN_M 0x40000000 -#define IOC_IOCFG4_HYST_EN_S 30 +#define IOC_IOCFG4_HYST_EN 0x40000000 +#define IOC_IOCFG4_HYST_EN_BITN 30 +#define IOC_IOCFG4_HYST_EN_M 0x40000000 +#define IOC_IOCFG4_HYST_EN_S 30 // Field: [29] IE // @@ -1628,10 +1628,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG4_IE 0x20000000 -#define IOC_IOCFG4_IE_BITN 29 -#define IOC_IOCFG4_IE_M 0x20000000 -#define IOC_IOCFG4_IE_S 29 +#define IOC_IOCFG4_IE 0x20000000 +#define IOC_IOCFG4_IE_BITN 29 +#define IOC_IOCFG4_IE_M 0x20000000 +#define IOC_IOCFG4_IE_S 29 // Field: [28:27] WU_CFG // @@ -1653,9 +1653,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG4_WU_CFG_W 2 -#define IOC_IOCFG4_WU_CFG_M 0x18000000 -#define IOC_IOCFG4_WU_CFG_S 27 +#define IOC_IOCFG4_WU_CFG_W 2 +#define IOC_IOCFG4_WU_CFG_M 0x18000000 +#define IOC_IOCFG4_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -1677,15 +1677,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG4_IOMODE_W 3 -#define IOC_IOCFG4_IOMODE_M 0x07000000 -#define IOC_IOCFG4_IOMODE_S 24 -#define IOC_IOCFG4_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG4_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG4_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG4_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG4_IOMODE_INV 0x01000000 -#define IOC_IOCFG4_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG4_IOMODE_W 3 +#define IOC_IOCFG4_IOMODE_M 0x07000000 +#define IOC_IOCFG4_IOMODE_S 24 +#define IOC_IOCFG4_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG4_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG4_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG4_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG4_IOMODE_INV 0x01000000 +#define IOC_IOCFG4_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -1693,10 +1693,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG4_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG4_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG4_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG4_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG4_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG4_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG4_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG4_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -1704,10 +1704,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG4_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG4_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG4_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG4_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG4_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG4_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG4_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG4_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -1715,20 +1715,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG4_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG4_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG4_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG4_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG4_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG4_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG4_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG4_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG4_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG4_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG4_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG4_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG4_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG4_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG4_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG4_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -1738,13 +1738,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG4_EDGE_DET_W 2 -#define IOC_IOCFG4_EDGE_DET_M 0x00030000 -#define IOC_IOCFG4_EDGE_DET_S 16 -#define IOC_IOCFG4_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG4_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG4_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG4_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG4_EDGE_DET_W 2 +#define IOC_IOCFG4_EDGE_DET_M 0x00030000 +#define IOC_IOCFG4_EDGE_DET_S 16 +#define IOC_IOCFG4_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG4_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG4_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG4_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -1753,21 +1753,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG4_PULL_CTL_W 2 -#define IOC_IOCFG4_PULL_CTL_M 0x00006000 -#define IOC_IOCFG4_PULL_CTL_S 13 -#define IOC_IOCFG4_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG4_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG4_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG4_PULL_CTL_W 2 +#define IOC_IOCFG4_PULL_CTL_M 0x00006000 +#define IOC_IOCFG4_PULL_CTL_S 13 +#define IOC_IOCFG4_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG4_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG4_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG4_SLEW_RED 0x00001000 -#define IOC_IOCFG4_SLEW_RED_BITN 12 -#define IOC_IOCFG4_SLEW_RED_M 0x00001000 -#define IOC_IOCFG4_SLEW_RED_S 12 +#define IOC_IOCFG4_SLEW_RED 0x00001000 +#define IOC_IOCFG4_SLEW_RED_BITN 12 +#define IOC_IOCFG4_SLEW_RED_M 0x00001000 +#define IOC_IOCFG4_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -1780,12 +1780,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG4_IOCURR_W 2 -#define IOC_IOCFG4_IOCURR_M 0x00000C00 -#define IOC_IOCFG4_IOCURR_S 10 -#define IOC_IOCFG4_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG4_IOCURR_4MA 0x00000400 -#define IOC_IOCFG4_IOCURR_2MA 0x00000000 +#define IOC_IOCFG4_IOCURR_W 2 +#define IOC_IOCFG4_IOCURR_M 0x00000C00 +#define IOC_IOCFG4_IOCURR_S 10 +#define IOC_IOCFG4_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG4_IOCURR_4MA 0x00000400 +#define IOC_IOCFG4_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -1804,13 +1804,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG4_IOSTR_W 2 -#define IOC_IOCFG4_IOSTR_M 0x00000300 -#define IOC_IOCFG4_IOSTR_S 8 -#define IOC_IOCFG4_IOSTR_MAX 0x00000300 -#define IOC_IOCFG4_IOSTR_MED 0x00000200 -#define IOC_IOCFG4_IOSTR_MIN 0x00000100 -#define IOC_IOCFG4_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG4_IOSTR_W 2 +#define IOC_IOCFG4_IOSTR_M 0x00000300 +#define IOC_IOCFG4_IOSTR_S 8 +#define IOC_IOCFG4_IOSTR_MAX 0x00000300 +#define IOC_IOCFG4_IOSTR_MED 0x00000200 +#define IOC_IOCFG4_IOSTR_MIN 0x00000100 +#define IOC_IOCFG4_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -1818,10 +1818,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG4_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG4_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG4_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG4_IOEV_RTC_EN_S 7 +#define IOC_IOCFG4_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG4_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG4_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG4_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -1829,10 +1829,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG4_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG4_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG4_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG4_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG4_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG4_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG4_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG4_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -1924,55 +1924,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG4_PORT_ID_W 6 -#define IOC_IOCFG4_PORT_ID_M 0x0000003F -#define IOC_IOCFG4_PORT_ID_S 0 -#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG4_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG4_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG4_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG4_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG4_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG4_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG4_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG4_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG4_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG4_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG4_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG4_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG4_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG4_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG4_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG4_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG4_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG4_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG4_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG4_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG4_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG4_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG4_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG4_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG4_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG4_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG4_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG4_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG4_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG4_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG4_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG4_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG4_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG4_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG4_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG4_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG4_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG4_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG4_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG4_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG4_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG4_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG4_PORT_ID_W 6 +#define IOC_IOCFG4_PORT_ID_M 0x0000003F +#define IOC_IOCFG4_PORT_ID_S 0 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG4_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG4_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG4_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG4_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG4_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG4_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG4_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG4_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG4_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG4_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG4_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG4_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG4_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG4_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG4_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG4_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG4_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG4_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG4_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG4_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG4_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG4_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG4_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG4_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG4_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG4_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG4_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG4_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG4_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG4_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG4_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG4_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG4_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG4_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG4_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG4_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG4_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG4_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG4_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -1983,10 +1983,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG5_HYST_EN 0x40000000 -#define IOC_IOCFG5_HYST_EN_BITN 30 -#define IOC_IOCFG5_HYST_EN_M 0x40000000 -#define IOC_IOCFG5_HYST_EN_S 30 +#define IOC_IOCFG5_HYST_EN 0x40000000 +#define IOC_IOCFG5_HYST_EN_BITN 30 +#define IOC_IOCFG5_HYST_EN_M 0x40000000 +#define IOC_IOCFG5_HYST_EN_S 30 // Field: [29] IE // @@ -1995,10 +1995,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG5_IE 0x20000000 -#define IOC_IOCFG5_IE_BITN 29 -#define IOC_IOCFG5_IE_M 0x20000000 -#define IOC_IOCFG5_IE_S 29 +#define IOC_IOCFG5_IE 0x20000000 +#define IOC_IOCFG5_IE_BITN 29 +#define IOC_IOCFG5_IE_M 0x20000000 +#define IOC_IOCFG5_IE_S 29 // Field: [28:27] WU_CFG // @@ -2020,9 +2020,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG5_WU_CFG_W 2 -#define IOC_IOCFG5_WU_CFG_M 0x18000000 -#define IOC_IOCFG5_WU_CFG_S 27 +#define IOC_IOCFG5_WU_CFG_W 2 +#define IOC_IOCFG5_WU_CFG_M 0x18000000 +#define IOC_IOCFG5_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -2044,15 +2044,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG5_IOMODE_W 3 -#define IOC_IOCFG5_IOMODE_M 0x07000000 -#define IOC_IOCFG5_IOMODE_S 24 -#define IOC_IOCFG5_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG5_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG5_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG5_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG5_IOMODE_INV 0x01000000 -#define IOC_IOCFG5_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG5_IOMODE_W 3 +#define IOC_IOCFG5_IOMODE_M 0x07000000 +#define IOC_IOCFG5_IOMODE_S 24 +#define IOC_IOCFG5_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG5_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG5_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG5_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG5_IOMODE_INV 0x01000000 +#define IOC_IOCFG5_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -2060,10 +2060,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG5_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG5_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG5_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG5_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG5_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG5_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG5_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG5_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -2071,10 +2071,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG5_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG5_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG5_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG5_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG5_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG5_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG5_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG5_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -2082,20 +2082,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG5_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG5_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG5_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG5_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG5_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG5_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG5_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG5_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG5_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG5_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG5_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG5_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG5_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG5_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG5_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG5_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -2105,13 +2105,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG5_EDGE_DET_W 2 -#define IOC_IOCFG5_EDGE_DET_M 0x00030000 -#define IOC_IOCFG5_EDGE_DET_S 16 -#define IOC_IOCFG5_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG5_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG5_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG5_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG5_EDGE_DET_W 2 +#define IOC_IOCFG5_EDGE_DET_M 0x00030000 +#define IOC_IOCFG5_EDGE_DET_S 16 +#define IOC_IOCFG5_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG5_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG5_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG5_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -2120,21 +2120,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG5_PULL_CTL_W 2 -#define IOC_IOCFG5_PULL_CTL_M 0x00006000 -#define IOC_IOCFG5_PULL_CTL_S 13 -#define IOC_IOCFG5_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG5_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG5_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG5_PULL_CTL_W 2 +#define IOC_IOCFG5_PULL_CTL_M 0x00006000 +#define IOC_IOCFG5_PULL_CTL_S 13 +#define IOC_IOCFG5_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG5_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG5_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG5_SLEW_RED 0x00001000 -#define IOC_IOCFG5_SLEW_RED_BITN 12 -#define IOC_IOCFG5_SLEW_RED_M 0x00001000 -#define IOC_IOCFG5_SLEW_RED_S 12 +#define IOC_IOCFG5_SLEW_RED 0x00001000 +#define IOC_IOCFG5_SLEW_RED_BITN 12 +#define IOC_IOCFG5_SLEW_RED_M 0x00001000 +#define IOC_IOCFG5_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -2147,12 +2147,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG5_IOCURR_W 2 -#define IOC_IOCFG5_IOCURR_M 0x00000C00 -#define IOC_IOCFG5_IOCURR_S 10 -#define IOC_IOCFG5_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG5_IOCURR_4MA 0x00000400 -#define IOC_IOCFG5_IOCURR_2MA 0x00000000 +#define IOC_IOCFG5_IOCURR_W 2 +#define IOC_IOCFG5_IOCURR_M 0x00000C00 +#define IOC_IOCFG5_IOCURR_S 10 +#define IOC_IOCFG5_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG5_IOCURR_4MA 0x00000400 +#define IOC_IOCFG5_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -2171,13 +2171,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG5_IOSTR_W 2 -#define IOC_IOCFG5_IOSTR_M 0x00000300 -#define IOC_IOCFG5_IOSTR_S 8 -#define IOC_IOCFG5_IOSTR_MAX 0x00000300 -#define IOC_IOCFG5_IOSTR_MED 0x00000200 -#define IOC_IOCFG5_IOSTR_MIN 0x00000100 -#define IOC_IOCFG5_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG5_IOSTR_W 2 +#define IOC_IOCFG5_IOSTR_M 0x00000300 +#define IOC_IOCFG5_IOSTR_S 8 +#define IOC_IOCFG5_IOSTR_MAX 0x00000300 +#define IOC_IOCFG5_IOSTR_MED 0x00000200 +#define IOC_IOCFG5_IOSTR_MIN 0x00000100 +#define IOC_IOCFG5_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -2185,10 +2185,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG5_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG5_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG5_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG5_IOEV_RTC_EN_S 7 +#define IOC_IOCFG5_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG5_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG5_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG5_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -2196,10 +2196,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG5_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG5_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG5_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG5_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG5_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG5_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG5_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG5_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -2291,55 +2291,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG5_PORT_ID_W 6 -#define IOC_IOCFG5_PORT_ID_M 0x0000003F -#define IOC_IOCFG5_PORT_ID_S 0 -#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG5_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG5_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG5_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG5_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG5_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG5_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG5_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG5_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG5_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG5_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG5_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG5_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG5_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG5_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG5_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG5_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG5_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG5_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG5_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG5_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG5_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG5_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG5_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG5_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG5_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG5_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG5_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG5_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG5_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG5_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG5_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG5_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG5_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG5_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG5_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG5_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG5_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG5_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG5_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG5_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG5_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG5_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG5_PORT_ID_W 6 +#define IOC_IOCFG5_PORT_ID_M 0x0000003F +#define IOC_IOCFG5_PORT_ID_S 0 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG5_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG5_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG5_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG5_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG5_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG5_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG5_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG5_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG5_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG5_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG5_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG5_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG5_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG5_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG5_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG5_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG5_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG5_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG5_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG5_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG5_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG5_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG5_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG5_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG5_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG5_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG5_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG5_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG5_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG5_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG5_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG5_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG5_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG5_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG5_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG5_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG5_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG5_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG5_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -2350,10 +2350,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG6_HYST_EN 0x40000000 -#define IOC_IOCFG6_HYST_EN_BITN 30 -#define IOC_IOCFG6_HYST_EN_M 0x40000000 -#define IOC_IOCFG6_HYST_EN_S 30 +#define IOC_IOCFG6_HYST_EN 0x40000000 +#define IOC_IOCFG6_HYST_EN_BITN 30 +#define IOC_IOCFG6_HYST_EN_M 0x40000000 +#define IOC_IOCFG6_HYST_EN_S 30 // Field: [29] IE // @@ -2362,10 +2362,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG6_IE 0x20000000 -#define IOC_IOCFG6_IE_BITN 29 -#define IOC_IOCFG6_IE_M 0x20000000 -#define IOC_IOCFG6_IE_S 29 +#define IOC_IOCFG6_IE 0x20000000 +#define IOC_IOCFG6_IE_BITN 29 +#define IOC_IOCFG6_IE_M 0x20000000 +#define IOC_IOCFG6_IE_S 29 // Field: [28:27] WU_CFG // @@ -2387,9 +2387,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG6_WU_CFG_W 2 -#define IOC_IOCFG6_WU_CFG_M 0x18000000 -#define IOC_IOCFG6_WU_CFG_S 27 +#define IOC_IOCFG6_WU_CFG_W 2 +#define IOC_IOCFG6_WU_CFG_M 0x18000000 +#define IOC_IOCFG6_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -2411,15 +2411,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG6_IOMODE_W 3 -#define IOC_IOCFG6_IOMODE_M 0x07000000 -#define IOC_IOCFG6_IOMODE_S 24 -#define IOC_IOCFG6_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG6_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG6_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG6_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG6_IOMODE_INV 0x01000000 -#define IOC_IOCFG6_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG6_IOMODE_W 3 +#define IOC_IOCFG6_IOMODE_M 0x07000000 +#define IOC_IOCFG6_IOMODE_S 24 +#define IOC_IOCFG6_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG6_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG6_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG6_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG6_IOMODE_INV 0x01000000 +#define IOC_IOCFG6_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -2427,10 +2427,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG6_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG6_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG6_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG6_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG6_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG6_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG6_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG6_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -2438,10 +2438,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG6_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG6_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG6_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG6_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG6_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG6_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG6_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG6_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -2449,20 +2449,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG6_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG6_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG6_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG6_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG6_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG6_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG6_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG6_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG6_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG6_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG6_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG6_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG6_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG6_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG6_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG6_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -2472,13 +2472,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG6_EDGE_DET_W 2 -#define IOC_IOCFG6_EDGE_DET_M 0x00030000 -#define IOC_IOCFG6_EDGE_DET_S 16 -#define IOC_IOCFG6_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG6_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG6_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG6_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG6_EDGE_DET_W 2 +#define IOC_IOCFG6_EDGE_DET_M 0x00030000 +#define IOC_IOCFG6_EDGE_DET_S 16 +#define IOC_IOCFG6_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG6_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG6_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG6_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -2487,21 +2487,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG6_PULL_CTL_W 2 -#define IOC_IOCFG6_PULL_CTL_M 0x00006000 -#define IOC_IOCFG6_PULL_CTL_S 13 -#define IOC_IOCFG6_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG6_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG6_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG6_PULL_CTL_W 2 +#define IOC_IOCFG6_PULL_CTL_M 0x00006000 +#define IOC_IOCFG6_PULL_CTL_S 13 +#define IOC_IOCFG6_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG6_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG6_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG6_SLEW_RED 0x00001000 -#define IOC_IOCFG6_SLEW_RED_BITN 12 -#define IOC_IOCFG6_SLEW_RED_M 0x00001000 -#define IOC_IOCFG6_SLEW_RED_S 12 +#define IOC_IOCFG6_SLEW_RED 0x00001000 +#define IOC_IOCFG6_SLEW_RED_BITN 12 +#define IOC_IOCFG6_SLEW_RED_M 0x00001000 +#define IOC_IOCFG6_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -2514,12 +2514,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG6_IOCURR_W 2 -#define IOC_IOCFG6_IOCURR_M 0x00000C00 -#define IOC_IOCFG6_IOCURR_S 10 -#define IOC_IOCFG6_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG6_IOCURR_4MA 0x00000400 -#define IOC_IOCFG6_IOCURR_2MA 0x00000000 +#define IOC_IOCFG6_IOCURR_W 2 +#define IOC_IOCFG6_IOCURR_M 0x00000C00 +#define IOC_IOCFG6_IOCURR_S 10 +#define IOC_IOCFG6_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG6_IOCURR_4MA 0x00000400 +#define IOC_IOCFG6_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -2538,13 +2538,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG6_IOSTR_W 2 -#define IOC_IOCFG6_IOSTR_M 0x00000300 -#define IOC_IOCFG6_IOSTR_S 8 -#define IOC_IOCFG6_IOSTR_MAX 0x00000300 -#define IOC_IOCFG6_IOSTR_MED 0x00000200 -#define IOC_IOCFG6_IOSTR_MIN 0x00000100 -#define IOC_IOCFG6_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG6_IOSTR_W 2 +#define IOC_IOCFG6_IOSTR_M 0x00000300 +#define IOC_IOCFG6_IOSTR_S 8 +#define IOC_IOCFG6_IOSTR_MAX 0x00000300 +#define IOC_IOCFG6_IOSTR_MED 0x00000200 +#define IOC_IOCFG6_IOSTR_MIN 0x00000100 +#define IOC_IOCFG6_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -2552,10 +2552,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG6_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG6_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG6_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG6_IOEV_RTC_EN_S 7 +#define IOC_IOCFG6_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG6_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG6_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG6_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -2563,10 +2563,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG6_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG6_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG6_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG6_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG6_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG6_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG6_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG6_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -2658,55 +2658,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG6_PORT_ID_W 6 -#define IOC_IOCFG6_PORT_ID_M 0x0000003F -#define IOC_IOCFG6_PORT_ID_S 0 -#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG6_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG6_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG6_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG6_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG6_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG6_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG6_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG6_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG6_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG6_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG6_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG6_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG6_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG6_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG6_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG6_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG6_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG6_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG6_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG6_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG6_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG6_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG6_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG6_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG6_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG6_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG6_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG6_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG6_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG6_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG6_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG6_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG6_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG6_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG6_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG6_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG6_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG6_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG6_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG6_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG6_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG6_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG6_PORT_ID_W 6 +#define IOC_IOCFG6_PORT_ID_M 0x0000003F +#define IOC_IOCFG6_PORT_ID_S 0 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG6_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG6_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG6_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG6_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG6_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG6_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG6_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG6_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG6_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG6_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG6_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG6_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG6_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG6_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG6_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG6_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG6_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG6_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG6_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG6_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG6_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG6_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG6_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG6_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG6_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG6_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG6_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG6_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG6_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG6_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG6_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG6_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG6_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG6_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG6_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG6_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG6_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG6_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG6_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -2717,10 +2717,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG7_HYST_EN 0x40000000 -#define IOC_IOCFG7_HYST_EN_BITN 30 -#define IOC_IOCFG7_HYST_EN_M 0x40000000 -#define IOC_IOCFG7_HYST_EN_S 30 +#define IOC_IOCFG7_HYST_EN 0x40000000 +#define IOC_IOCFG7_HYST_EN_BITN 30 +#define IOC_IOCFG7_HYST_EN_M 0x40000000 +#define IOC_IOCFG7_HYST_EN_S 30 // Field: [29] IE // @@ -2729,10 +2729,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG7_IE 0x20000000 -#define IOC_IOCFG7_IE_BITN 29 -#define IOC_IOCFG7_IE_M 0x20000000 -#define IOC_IOCFG7_IE_S 29 +#define IOC_IOCFG7_IE 0x20000000 +#define IOC_IOCFG7_IE_BITN 29 +#define IOC_IOCFG7_IE_M 0x20000000 +#define IOC_IOCFG7_IE_S 29 // Field: [28:27] WU_CFG // @@ -2754,9 +2754,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG7_WU_CFG_W 2 -#define IOC_IOCFG7_WU_CFG_M 0x18000000 -#define IOC_IOCFG7_WU_CFG_S 27 +#define IOC_IOCFG7_WU_CFG_W 2 +#define IOC_IOCFG7_WU_CFG_M 0x18000000 +#define IOC_IOCFG7_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -2778,15 +2778,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG7_IOMODE_W 3 -#define IOC_IOCFG7_IOMODE_M 0x07000000 -#define IOC_IOCFG7_IOMODE_S 24 -#define IOC_IOCFG7_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG7_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG7_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG7_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG7_IOMODE_INV 0x01000000 -#define IOC_IOCFG7_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG7_IOMODE_W 3 +#define IOC_IOCFG7_IOMODE_M 0x07000000 +#define IOC_IOCFG7_IOMODE_S 24 +#define IOC_IOCFG7_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG7_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG7_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG7_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG7_IOMODE_INV 0x01000000 +#define IOC_IOCFG7_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -2794,10 +2794,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG7_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG7_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG7_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG7_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG7_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG7_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG7_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG7_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -2805,10 +2805,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG7_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG7_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG7_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG7_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG7_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG7_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG7_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG7_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -2816,20 +2816,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG7_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG7_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG7_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG7_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG7_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG7_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG7_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG7_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG7_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG7_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG7_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG7_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG7_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG7_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG7_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG7_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -2839,13 +2839,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG7_EDGE_DET_W 2 -#define IOC_IOCFG7_EDGE_DET_M 0x00030000 -#define IOC_IOCFG7_EDGE_DET_S 16 -#define IOC_IOCFG7_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG7_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG7_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG7_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG7_EDGE_DET_W 2 +#define IOC_IOCFG7_EDGE_DET_M 0x00030000 +#define IOC_IOCFG7_EDGE_DET_S 16 +#define IOC_IOCFG7_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG7_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG7_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG7_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -2854,21 +2854,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG7_PULL_CTL_W 2 -#define IOC_IOCFG7_PULL_CTL_M 0x00006000 -#define IOC_IOCFG7_PULL_CTL_S 13 -#define IOC_IOCFG7_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG7_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG7_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG7_PULL_CTL_W 2 +#define IOC_IOCFG7_PULL_CTL_M 0x00006000 +#define IOC_IOCFG7_PULL_CTL_S 13 +#define IOC_IOCFG7_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG7_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG7_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG7_SLEW_RED 0x00001000 -#define IOC_IOCFG7_SLEW_RED_BITN 12 -#define IOC_IOCFG7_SLEW_RED_M 0x00001000 -#define IOC_IOCFG7_SLEW_RED_S 12 +#define IOC_IOCFG7_SLEW_RED 0x00001000 +#define IOC_IOCFG7_SLEW_RED_BITN 12 +#define IOC_IOCFG7_SLEW_RED_M 0x00001000 +#define IOC_IOCFG7_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -2881,12 +2881,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG7_IOCURR_W 2 -#define IOC_IOCFG7_IOCURR_M 0x00000C00 -#define IOC_IOCFG7_IOCURR_S 10 -#define IOC_IOCFG7_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG7_IOCURR_4MA 0x00000400 -#define IOC_IOCFG7_IOCURR_2MA 0x00000000 +#define IOC_IOCFG7_IOCURR_W 2 +#define IOC_IOCFG7_IOCURR_M 0x00000C00 +#define IOC_IOCFG7_IOCURR_S 10 +#define IOC_IOCFG7_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG7_IOCURR_4MA 0x00000400 +#define IOC_IOCFG7_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -2905,13 +2905,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG7_IOSTR_W 2 -#define IOC_IOCFG7_IOSTR_M 0x00000300 -#define IOC_IOCFG7_IOSTR_S 8 -#define IOC_IOCFG7_IOSTR_MAX 0x00000300 -#define IOC_IOCFG7_IOSTR_MED 0x00000200 -#define IOC_IOCFG7_IOSTR_MIN 0x00000100 -#define IOC_IOCFG7_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG7_IOSTR_W 2 +#define IOC_IOCFG7_IOSTR_M 0x00000300 +#define IOC_IOCFG7_IOSTR_S 8 +#define IOC_IOCFG7_IOSTR_MAX 0x00000300 +#define IOC_IOCFG7_IOSTR_MED 0x00000200 +#define IOC_IOCFG7_IOSTR_MIN 0x00000100 +#define IOC_IOCFG7_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -2919,10 +2919,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG7_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG7_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG7_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG7_IOEV_RTC_EN_S 7 +#define IOC_IOCFG7_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG7_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG7_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG7_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -2930,10 +2930,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG7_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG7_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG7_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG7_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG7_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG7_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG7_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG7_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -3025,55 +3025,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG7_PORT_ID_W 6 -#define IOC_IOCFG7_PORT_ID_M 0x0000003F -#define IOC_IOCFG7_PORT_ID_S 0 -#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG7_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG7_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG7_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG7_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG7_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG7_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG7_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG7_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG7_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG7_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG7_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG7_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG7_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG7_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG7_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG7_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG7_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG7_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG7_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG7_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG7_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG7_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG7_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG7_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG7_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG7_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG7_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG7_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG7_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG7_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG7_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG7_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG7_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG7_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG7_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG7_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG7_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG7_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG7_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG7_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG7_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG7_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG7_PORT_ID_W 6 +#define IOC_IOCFG7_PORT_ID_M 0x0000003F +#define IOC_IOCFG7_PORT_ID_S 0 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG7_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG7_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG7_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG7_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG7_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG7_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG7_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG7_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG7_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG7_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG7_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG7_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG7_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG7_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG7_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG7_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG7_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG7_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG7_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG7_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG7_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG7_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG7_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG7_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG7_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG7_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG7_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG7_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG7_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG7_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG7_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG7_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG7_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG7_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG7_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG7_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG7_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG7_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG7_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -3084,10 +3084,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG8_HYST_EN 0x40000000 -#define IOC_IOCFG8_HYST_EN_BITN 30 -#define IOC_IOCFG8_HYST_EN_M 0x40000000 -#define IOC_IOCFG8_HYST_EN_S 30 +#define IOC_IOCFG8_HYST_EN 0x40000000 +#define IOC_IOCFG8_HYST_EN_BITN 30 +#define IOC_IOCFG8_HYST_EN_M 0x40000000 +#define IOC_IOCFG8_HYST_EN_S 30 // Field: [29] IE // @@ -3096,10 +3096,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG8_IE 0x20000000 -#define IOC_IOCFG8_IE_BITN 29 -#define IOC_IOCFG8_IE_M 0x20000000 -#define IOC_IOCFG8_IE_S 29 +#define IOC_IOCFG8_IE 0x20000000 +#define IOC_IOCFG8_IE_BITN 29 +#define IOC_IOCFG8_IE_M 0x20000000 +#define IOC_IOCFG8_IE_S 29 // Field: [28:27] WU_CFG // @@ -3121,9 +3121,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG8_WU_CFG_W 2 -#define IOC_IOCFG8_WU_CFG_M 0x18000000 -#define IOC_IOCFG8_WU_CFG_S 27 +#define IOC_IOCFG8_WU_CFG_W 2 +#define IOC_IOCFG8_WU_CFG_M 0x18000000 +#define IOC_IOCFG8_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -3145,15 +3145,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG8_IOMODE_W 3 -#define IOC_IOCFG8_IOMODE_M 0x07000000 -#define IOC_IOCFG8_IOMODE_S 24 -#define IOC_IOCFG8_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG8_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG8_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG8_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG8_IOMODE_INV 0x01000000 -#define IOC_IOCFG8_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG8_IOMODE_W 3 +#define IOC_IOCFG8_IOMODE_M 0x07000000 +#define IOC_IOCFG8_IOMODE_S 24 +#define IOC_IOCFG8_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG8_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG8_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG8_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG8_IOMODE_INV 0x01000000 +#define IOC_IOCFG8_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -3161,10 +3161,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG8_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG8_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG8_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG8_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG8_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG8_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG8_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG8_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -3172,10 +3172,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG8_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG8_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG8_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG8_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG8_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG8_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG8_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG8_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -3183,20 +3183,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG8_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG8_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG8_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG8_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG8_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG8_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG8_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG8_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG8_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG8_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG8_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG8_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG8_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG8_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG8_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG8_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -3206,13 +3206,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG8_EDGE_DET_W 2 -#define IOC_IOCFG8_EDGE_DET_M 0x00030000 -#define IOC_IOCFG8_EDGE_DET_S 16 -#define IOC_IOCFG8_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG8_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG8_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG8_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG8_EDGE_DET_W 2 +#define IOC_IOCFG8_EDGE_DET_M 0x00030000 +#define IOC_IOCFG8_EDGE_DET_S 16 +#define IOC_IOCFG8_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG8_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG8_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG8_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -3221,21 +3221,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG8_PULL_CTL_W 2 -#define IOC_IOCFG8_PULL_CTL_M 0x00006000 -#define IOC_IOCFG8_PULL_CTL_S 13 -#define IOC_IOCFG8_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG8_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG8_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG8_PULL_CTL_W 2 +#define IOC_IOCFG8_PULL_CTL_M 0x00006000 +#define IOC_IOCFG8_PULL_CTL_S 13 +#define IOC_IOCFG8_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG8_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG8_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG8_SLEW_RED 0x00001000 -#define IOC_IOCFG8_SLEW_RED_BITN 12 -#define IOC_IOCFG8_SLEW_RED_M 0x00001000 -#define IOC_IOCFG8_SLEW_RED_S 12 +#define IOC_IOCFG8_SLEW_RED 0x00001000 +#define IOC_IOCFG8_SLEW_RED_BITN 12 +#define IOC_IOCFG8_SLEW_RED_M 0x00001000 +#define IOC_IOCFG8_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -3248,12 +3248,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG8_IOCURR_W 2 -#define IOC_IOCFG8_IOCURR_M 0x00000C00 -#define IOC_IOCFG8_IOCURR_S 10 -#define IOC_IOCFG8_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG8_IOCURR_4MA 0x00000400 -#define IOC_IOCFG8_IOCURR_2MA 0x00000000 +#define IOC_IOCFG8_IOCURR_W 2 +#define IOC_IOCFG8_IOCURR_M 0x00000C00 +#define IOC_IOCFG8_IOCURR_S 10 +#define IOC_IOCFG8_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG8_IOCURR_4MA 0x00000400 +#define IOC_IOCFG8_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -3272,13 +3272,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG8_IOSTR_W 2 -#define IOC_IOCFG8_IOSTR_M 0x00000300 -#define IOC_IOCFG8_IOSTR_S 8 -#define IOC_IOCFG8_IOSTR_MAX 0x00000300 -#define IOC_IOCFG8_IOSTR_MED 0x00000200 -#define IOC_IOCFG8_IOSTR_MIN 0x00000100 -#define IOC_IOCFG8_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG8_IOSTR_W 2 +#define IOC_IOCFG8_IOSTR_M 0x00000300 +#define IOC_IOCFG8_IOSTR_S 8 +#define IOC_IOCFG8_IOSTR_MAX 0x00000300 +#define IOC_IOCFG8_IOSTR_MED 0x00000200 +#define IOC_IOCFG8_IOSTR_MIN 0x00000100 +#define IOC_IOCFG8_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -3286,10 +3286,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG8_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG8_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG8_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG8_IOEV_RTC_EN_S 7 +#define IOC_IOCFG8_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG8_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG8_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG8_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -3297,10 +3297,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG8_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG8_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG8_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG8_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG8_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG8_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG8_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG8_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -3392,55 +3392,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG8_PORT_ID_W 6 -#define IOC_IOCFG8_PORT_ID_M 0x0000003F -#define IOC_IOCFG8_PORT_ID_S 0 -#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG8_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG8_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG8_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG8_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG8_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG8_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG8_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG8_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG8_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG8_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG8_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG8_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG8_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG8_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG8_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG8_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG8_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG8_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG8_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG8_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG8_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG8_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG8_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG8_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG8_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG8_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG8_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG8_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG8_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG8_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG8_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG8_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG8_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG8_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG8_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG8_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG8_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG8_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG8_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG8_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG8_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG8_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG8_PORT_ID_W 6 +#define IOC_IOCFG8_PORT_ID_M 0x0000003F +#define IOC_IOCFG8_PORT_ID_S 0 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG8_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG8_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG8_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG8_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG8_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG8_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG8_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG8_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG8_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG8_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG8_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG8_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG8_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG8_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG8_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG8_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG8_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG8_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG8_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG8_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG8_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG8_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG8_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG8_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG8_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG8_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG8_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG8_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG8_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG8_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG8_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG8_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG8_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG8_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG8_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG8_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG8_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG8_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG8_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -3451,10 +3451,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG9_HYST_EN 0x40000000 -#define IOC_IOCFG9_HYST_EN_BITN 30 -#define IOC_IOCFG9_HYST_EN_M 0x40000000 -#define IOC_IOCFG9_HYST_EN_S 30 +#define IOC_IOCFG9_HYST_EN 0x40000000 +#define IOC_IOCFG9_HYST_EN_BITN 30 +#define IOC_IOCFG9_HYST_EN_M 0x40000000 +#define IOC_IOCFG9_HYST_EN_S 30 // Field: [29] IE // @@ -3463,10 +3463,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG9_IE 0x20000000 -#define IOC_IOCFG9_IE_BITN 29 -#define IOC_IOCFG9_IE_M 0x20000000 -#define IOC_IOCFG9_IE_S 29 +#define IOC_IOCFG9_IE 0x20000000 +#define IOC_IOCFG9_IE_BITN 29 +#define IOC_IOCFG9_IE_M 0x20000000 +#define IOC_IOCFG9_IE_S 29 // Field: [28:27] WU_CFG // @@ -3488,9 +3488,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG9_WU_CFG_W 2 -#define IOC_IOCFG9_WU_CFG_M 0x18000000 -#define IOC_IOCFG9_WU_CFG_S 27 +#define IOC_IOCFG9_WU_CFG_W 2 +#define IOC_IOCFG9_WU_CFG_M 0x18000000 +#define IOC_IOCFG9_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -3512,15 +3512,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG9_IOMODE_W 3 -#define IOC_IOCFG9_IOMODE_M 0x07000000 -#define IOC_IOCFG9_IOMODE_S 24 -#define IOC_IOCFG9_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG9_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG9_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG9_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG9_IOMODE_INV 0x01000000 -#define IOC_IOCFG9_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG9_IOMODE_W 3 +#define IOC_IOCFG9_IOMODE_M 0x07000000 +#define IOC_IOCFG9_IOMODE_S 24 +#define IOC_IOCFG9_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG9_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG9_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG9_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG9_IOMODE_INV 0x01000000 +#define IOC_IOCFG9_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -3528,10 +3528,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG9_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG9_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG9_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG9_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG9_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG9_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG9_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG9_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -3539,10 +3539,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG9_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG9_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG9_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG9_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG9_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG9_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG9_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG9_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -3550,20 +3550,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG9_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG9_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG9_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG9_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG9_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG9_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG9_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG9_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG9_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG9_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG9_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG9_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG9_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG9_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG9_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG9_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -3573,13 +3573,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG9_EDGE_DET_W 2 -#define IOC_IOCFG9_EDGE_DET_M 0x00030000 -#define IOC_IOCFG9_EDGE_DET_S 16 -#define IOC_IOCFG9_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG9_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG9_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG9_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG9_EDGE_DET_W 2 +#define IOC_IOCFG9_EDGE_DET_M 0x00030000 +#define IOC_IOCFG9_EDGE_DET_S 16 +#define IOC_IOCFG9_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG9_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG9_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG9_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -3588,21 +3588,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG9_PULL_CTL_W 2 -#define IOC_IOCFG9_PULL_CTL_M 0x00006000 -#define IOC_IOCFG9_PULL_CTL_S 13 -#define IOC_IOCFG9_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG9_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG9_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG9_PULL_CTL_W 2 +#define IOC_IOCFG9_PULL_CTL_M 0x00006000 +#define IOC_IOCFG9_PULL_CTL_S 13 +#define IOC_IOCFG9_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG9_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG9_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG9_SLEW_RED 0x00001000 -#define IOC_IOCFG9_SLEW_RED_BITN 12 -#define IOC_IOCFG9_SLEW_RED_M 0x00001000 -#define IOC_IOCFG9_SLEW_RED_S 12 +#define IOC_IOCFG9_SLEW_RED 0x00001000 +#define IOC_IOCFG9_SLEW_RED_BITN 12 +#define IOC_IOCFG9_SLEW_RED_M 0x00001000 +#define IOC_IOCFG9_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -3615,12 +3615,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG9_IOCURR_W 2 -#define IOC_IOCFG9_IOCURR_M 0x00000C00 -#define IOC_IOCFG9_IOCURR_S 10 -#define IOC_IOCFG9_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG9_IOCURR_4MA 0x00000400 -#define IOC_IOCFG9_IOCURR_2MA 0x00000000 +#define IOC_IOCFG9_IOCURR_W 2 +#define IOC_IOCFG9_IOCURR_M 0x00000C00 +#define IOC_IOCFG9_IOCURR_S 10 +#define IOC_IOCFG9_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG9_IOCURR_4MA 0x00000400 +#define IOC_IOCFG9_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -3639,13 +3639,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG9_IOSTR_W 2 -#define IOC_IOCFG9_IOSTR_M 0x00000300 -#define IOC_IOCFG9_IOSTR_S 8 -#define IOC_IOCFG9_IOSTR_MAX 0x00000300 -#define IOC_IOCFG9_IOSTR_MED 0x00000200 -#define IOC_IOCFG9_IOSTR_MIN 0x00000100 -#define IOC_IOCFG9_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG9_IOSTR_W 2 +#define IOC_IOCFG9_IOSTR_M 0x00000300 +#define IOC_IOCFG9_IOSTR_S 8 +#define IOC_IOCFG9_IOSTR_MAX 0x00000300 +#define IOC_IOCFG9_IOSTR_MED 0x00000200 +#define IOC_IOCFG9_IOSTR_MIN 0x00000100 +#define IOC_IOCFG9_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -3653,10 +3653,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG9_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG9_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG9_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG9_IOEV_RTC_EN_S 7 +#define IOC_IOCFG9_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG9_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG9_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG9_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -3664,10 +3664,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG9_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG9_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG9_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG9_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG9_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG9_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG9_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG9_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -3759,55 +3759,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG9_PORT_ID_W 6 -#define IOC_IOCFG9_PORT_ID_M 0x0000003F -#define IOC_IOCFG9_PORT_ID_S 0 -#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG9_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG9_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG9_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG9_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG9_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG9_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG9_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG9_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG9_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG9_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG9_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG9_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG9_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG9_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG9_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG9_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG9_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG9_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG9_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG9_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG9_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG9_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG9_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG9_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG9_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG9_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG9_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG9_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG9_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG9_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG9_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG9_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG9_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG9_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG9_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG9_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG9_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG9_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG9_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG9_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG9_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG9_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG9_PORT_ID_W 6 +#define IOC_IOCFG9_PORT_ID_M 0x0000003F +#define IOC_IOCFG9_PORT_ID_S 0 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG9_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG9_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG9_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG9_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG9_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG9_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG9_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG9_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG9_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG9_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG9_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG9_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG9_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG9_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG9_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG9_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG9_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG9_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG9_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG9_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG9_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG9_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG9_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG9_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG9_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG9_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG9_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG9_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG9_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG9_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG9_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG9_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG9_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG9_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG9_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG9_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG9_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG9_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG9_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -3818,10 +3818,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG10_HYST_EN 0x40000000 -#define IOC_IOCFG10_HYST_EN_BITN 30 -#define IOC_IOCFG10_HYST_EN_M 0x40000000 -#define IOC_IOCFG10_HYST_EN_S 30 +#define IOC_IOCFG10_HYST_EN 0x40000000 +#define IOC_IOCFG10_HYST_EN_BITN 30 +#define IOC_IOCFG10_HYST_EN_M 0x40000000 +#define IOC_IOCFG10_HYST_EN_S 30 // Field: [29] IE // @@ -3830,10 +3830,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG10_IE 0x20000000 -#define IOC_IOCFG10_IE_BITN 29 -#define IOC_IOCFG10_IE_M 0x20000000 -#define IOC_IOCFG10_IE_S 29 +#define IOC_IOCFG10_IE 0x20000000 +#define IOC_IOCFG10_IE_BITN 29 +#define IOC_IOCFG10_IE_M 0x20000000 +#define IOC_IOCFG10_IE_S 29 // Field: [28:27] WU_CFG // @@ -3855,9 +3855,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG10_WU_CFG_W 2 -#define IOC_IOCFG10_WU_CFG_M 0x18000000 -#define IOC_IOCFG10_WU_CFG_S 27 +#define IOC_IOCFG10_WU_CFG_W 2 +#define IOC_IOCFG10_WU_CFG_M 0x18000000 +#define IOC_IOCFG10_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -3879,15 +3879,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG10_IOMODE_W 3 -#define IOC_IOCFG10_IOMODE_M 0x07000000 -#define IOC_IOCFG10_IOMODE_S 24 -#define IOC_IOCFG10_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG10_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG10_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG10_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG10_IOMODE_INV 0x01000000 -#define IOC_IOCFG10_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG10_IOMODE_W 3 +#define IOC_IOCFG10_IOMODE_M 0x07000000 +#define IOC_IOCFG10_IOMODE_S 24 +#define IOC_IOCFG10_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG10_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG10_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG10_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG10_IOMODE_INV 0x01000000 +#define IOC_IOCFG10_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -3895,10 +3895,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG10_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG10_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG10_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG10_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG10_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG10_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG10_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG10_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -3906,10 +3906,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG10_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG10_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG10_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG10_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG10_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG10_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG10_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG10_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -3917,20 +3917,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG10_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG10_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG10_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG10_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG10_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG10_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG10_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG10_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG10_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG10_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG10_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG10_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG10_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG10_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG10_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG10_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -3940,13 +3940,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG10_EDGE_DET_W 2 -#define IOC_IOCFG10_EDGE_DET_M 0x00030000 -#define IOC_IOCFG10_EDGE_DET_S 16 -#define IOC_IOCFG10_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG10_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG10_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG10_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG10_EDGE_DET_W 2 +#define IOC_IOCFG10_EDGE_DET_M 0x00030000 +#define IOC_IOCFG10_EDGE_DET_S 16 +#define IOC_IOCFG10_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG10_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG10_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG10_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -3955,21 +3955,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG10_PULL_CTL_W 2 -#define IOC_IOCFG10_PULL_CTL_M 0x00006000 -#define IOC_IOCFG10_PULL_CTL_S 13 -#define IOC_IOCFG10_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG10_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG10_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG10_PULL_CTL_W 2 +#define IOC_IOCFG10_PULL_CTL_M 0x00006000 +#define IOC_IOCFG10_PULL_CTL_S 13 +#define IOC_IOCFG10_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG10_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG10_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG10_SLEW_RED 0x00001000 -#define IOC_IOCFG10_SLEW_RED_BITN 12 -#define IOC_IOCFG10_SLEW_RED_M 0x00001000 -#define IOC_IOCFG10_SLEW_RED_S 12 +#define IOC_IOCFG10_SLEW_RED 0x00001000 +#define IOC_IOCFG10_SLEW_RED_BITN 12 +#define IOC_IOCFG10_SLEW_RED_M 0x00001000 +#define IOC_IOCFG10_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -3982,12 +3982,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG10_IOCURR_W 2 -#define IOC_IOCFG10_IOCURR_M 0x00000C00 -#define IOC_IOCFG10_IOCURR_S 10 -#define IOC_IOCFG10_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG10_IOCURR_4MA 0x00000400 -#define IOC_IOCFG10_IOCURR_2MA 0x00000000 +#define IOC_IOCFG10_IOCURR_W 2 +#define IOC_IOCFG10_IOCURR_M 0x00000C00 +#define IOC_IOCFG10_IOCURR_S 10 +#define IOC_IOCFG10_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG10_IOCURR_4MA 0x00000400 +#define IOC_IOCFG10_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -4006,13 +4006,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG10_IOSTR_W 2 -#define IOC_IOCFG10_IOSTR_M 0x00000300 -#define IOC_IOCFG10_IOSTR_S 8 -#define IOC_IOCFG10_IOSTR_MAX 0x00000300 -#define IOC_IOCFG10_IOSTR_MED 0x00000200 -#define IOC_IOCFG10_IOSTR_MIN 0x00000100 -#define IOC_IOCFG10_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG10_IOSTR_W 2 +#define IOC_IOCFG10_IOSTR_M 0x00000300 +#define IOC_IOCFG10_IOSTR_S 8 +#define IOC_IOCFG10_IOSTR_MAX 0x00000300 +#define IOC_IOCFG10_IOSTR_MED 0x00000200 +#define IOC_IOCFG10_IOSTR_MIN 0x00000100 +#define IOC_IOCFG10_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -4020,10 +4020,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG10_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG10_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG10_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG10_IOEV_RTC_EN_S 7 +#define IOC_IOCFG10_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG10_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG10_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG10_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -4031,10 +4031,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG10_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG10_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG10_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG10_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG10_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG10_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG10_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG10_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -4126,55 +4126,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG10_PORT_ID_W 6 -#define IOC_IOCFG10_PORT_ID_M 0x0000003F -#define IOC_IOCFG10_PORT_ID_S 0 -#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG10_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG10_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG10_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG10_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG10_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG10_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG10_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG10_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG10_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG10_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG10_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG10_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG10_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG10_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG10_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG10_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG10_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG10_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG10_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG10_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG10_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG10_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG10_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG10_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG10_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG10_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG10_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG10_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG10_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG10_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG10_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG10_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG10_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG10_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG10_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG10_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG10_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG10_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG10_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG10_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG10_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG10_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG10_PORT_ID_W 6 +#define IOC_IOCFG10_PORT_ID_M 0x0000003F +#define IOC_IOCFG10_PORT_ID_S 0 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG10_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG10_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG10_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG10_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG10_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG10_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG10_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG10_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG10_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG10_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG10_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG10_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG10_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG10_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG10_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG10_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG10_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG10_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG10_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG10_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG10_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG10_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG10_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG10_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG10_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG10_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG10_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG10_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG10_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG10_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG10_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG10_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG10_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG10_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG10_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG10_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG10_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG10_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG10_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -4185,10 +4185,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG11_HYST_EN 0x40000000 -#define IOC_IOCFG11_HYST_EN_BITN 30 -#define IOC_IOCFG11_HYST_EN_M 0x40000000 -#define IOC_IOCFG11_HYST_EN_S 30 +#define IOC_IOCFG11_HYST_EN 0x40000000 +#define IOC_IOCFG11_HYST_EN_BITN 30 +#define IOC_IOCFG11_HYST_EN_M 0x40000000 +#define IOC_IOCFG11_HYST_EN_S 30 // Field: [29] IE // @@ -4197,10 +4197,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG11_IE 0x20000000 -#define IOC_IOCFG11_IE_BITN 29 -#define IOC_IOCFG11_IE_M 0x20000000 -#define IOC_IOCFG11_IE_S 29 +#define IOC_IOCFG11_IE 0x20000000 +#define IOC_IOCFG11_IE_BITN 29 +#define IOC_IOCFG11_IE_M 0x20000000 +#define IOC_IOCFG11_IE_S 29 // Field: [28:27] WU_CFG // @@ -4222,9 +4222,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG11_WU_CFG_W 2 -#define IOC_IOCFG11_WU_CFG_M 0x18000000 -#define IOC_IOCFG11_WU_CFG_S 27 +#define IOC_IOCFG11_WU_CFG_W 2 +#define IOC_IOCFG11_WU_CFG_M 0x18000000 +#define IOC_IOCFG11_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -4246,15 +4246,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG11_IOMODE_W 3 -#define IOC_IOCFG11_IOMODE_M 0x07000000 -#define IOC_IOCFG11_IOMODE_S 24 -#define IOC_IOCFG11_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG11_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG11_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG11_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG11_IOMODE_INV 0x01000000 -#define IOC_IOCFG11_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG11_IOMODE_W 3 +#define IOC_IOCFG11_IOMODE_M 0x07000000 +#define IOC_IOCFG11_IOMODE_S 24 +#define IOC_IOCFG11_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG11_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG11_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG11_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG11_IOMODE_INV 0x01000000 +#define IOC_IOCFG11_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -4262,10 +4262,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG11_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG11_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG11_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG11_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG11_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG11_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG11_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG11_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -4273,10 +4273,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG11_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG11_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG11_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG11_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG11_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG11_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG11_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG11_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -4284,20 +4284,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG11_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG11_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG11_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG11_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG11_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG11_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG11_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG11_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG11_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG11_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG11_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG11_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG11_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG11_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG11_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG11_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -4307,13 +4307,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG11_EDGE_DET_W 2 -#define IOC_IOCFG11_EDGE_DET_M 0x00030000 -#define IOC_IOCFG11_EDGE_DET_S 16 -#define IOC_IOCFG11_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG11_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG11_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG11_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG11_EDGE_DET_W 2 +#define IOC_IOCFG11_EDGE_DET_M 0x00030000 +#define IOC_IOCFG11_EDGE_DET_S 16 +#define IOC_IOCFG11_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG11_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG11_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG11_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -4322,21 +4322,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG11_PULL_CTL_W 2 -#define IOC_IOCFG11_PULL_CTL_M 0x00006000 -#define IOC_IOCFG11_PULL_CTL_S 13 -#define IOC_IOCFG11_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG11_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG11_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG11_PULL_CTL_W 2 +#define IOC_IOCFG11_PULL_CTL_M 0x00006000 +#define IOC_IOCFG11_PULL_CTL_S 13 +#define IOC_IOCFG11_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG11_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG11_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG11_SLEW_RED 0x00001000 -#define IOC_IOCFG11_SLEW_RED_BITN 12 -#define IOC_IOCFG11_SLEW_RED_M 0x00001000 -#define IOC_IOCFG11_SLEW_RED_S 12 +#define IOC_IOCFG11_SLEW_RED 0x00001000 +#define IOC_IOCFG11_SLEW_RED_BITN 12 +#define IOC_IOCFG11_SLEW_RED_M 0x00001000 +#define IOC_IOCFG11_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -4349,12 +4349,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG11_IOCURR_W 2 -#define IOC_IOCFG11_IOCURR_M 0x00000C00 -#define IOC_IOCFG11_IOCURR_S 10 -#define IOC_IOCFG11_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG11_IOCURR_4MA 0x00000400 -#define IOC_IOCFG11_IOCURR_2MA 0x00000000 +#define IOC_IOCFG11_IOCURR_W 2 +#define IOC_IOCFG11_IOCURR_M 0x00000C00 +#define IOC_IOCFG11_IOCURR_S 10 +#define IOC_IOCFG11_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG11_IOCURR_4MA 0x00000400 +#define IOC_IOCFG11_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -4373,13 +4373,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG11_IOSTR_W 2 -#define IOC_IOCFG11_IOSTR_M 0x00000300 -#define IOC_IOCFG11_IOSTR_S 8 -#define IOC_IOCFG11_IOSTR_MAX 0x00000300 -#define IOC_IOCFG11_IOSTR_MED 0x00000200 -#define IOC_IOCFG11_IOSTR_MIN 0x00000100 -#define IOC_IOCFG11_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG11_IOSTR_W 2 +#define IOC_IOCFG11_IOSTR_M 0x00000300 +#define IOC_IOCFG11_IOSTR_S 8 +#define IOC_IOCFG11_IOSTR_MAX 0x00000300 +#define IOC_IOCFG11_IOSTR_MED 0x00000200 +#define IOC_IOCFG11_IOSTR_MIN 0x00000100 +#define IOC_IOCFG11_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -4387,10 +4387,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG11_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG11_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG11_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG11_IOEV_RTC_EN_S 7 +#define IOC_IOCFG11_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG11_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG11_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG11_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -4398,10 +4398,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG11_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG11_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG11_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG11_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG11_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG11_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG11_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG11_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -4493,55 +4493,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG11_PORT_ID_W 6 -#define IOC_IOCFG11_PORT_ID_M 0x0000003F -#define IOC_IOCFG11_PORT_ID_S 0 -#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG11_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG11_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG11_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG11_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG11_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG11_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG11_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG11_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG11_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG11_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG11_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG11_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG11_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG11_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG11_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG11_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG11_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG11_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG11_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG11_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG11_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG11_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG11_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG11_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG11_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG11_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG11_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG11_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG11_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG11_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG11_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG11_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG11_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG11_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG11_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG11_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG11_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG11_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG11_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG11_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG11_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG11_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG11_PORT_ID_W 6 +#define IOC_IOCFG11_PORT_ID_M 0x0000003F +#define IOC_IOCFG11_PORT_ID_S 0 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG11_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG11_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG11_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG11_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG11_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG11_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG11_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG11_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG11_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG11_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG11_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG11_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG11_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG11_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG11_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG11_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG11_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG11_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG11_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG11_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG11_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG11_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG11_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG11_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG11_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG11_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG11_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG11_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG11_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG11_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG11_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG11_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG11_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG11_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG11_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG11_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG11_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG11_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG11_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -4552,10 +4552,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG12_HYST_EN 0x40000000 -#define IOC_IOCFG12_HYST_EN_BITN 30 -#define IOC_IOCFG12_HYST_EN_M 0x40000000 -#define IOC_IOCFG12_HYST_EN_S 30 +#define IOC_IOCFG12_HYST_EN 0x40000000 +#define IOC_IOCFG12_HYST_EN_BITN 30 +#define IOC_IOCFG12_HYST_EN_M 0x40000000 +#define IOC_IOCFG12_HYST_EN_S 30 // Field: [29] IE // @@ -4564,10 +4564,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG12_IE 0x20000000 -#define IOC_IOCFG12_IE_BITN 29 -#define IOC_IOCFG12_IE_M 0x20000000 -#define IOC_IOCFG12_IE_S 29 +#define IOC_IOCFG12_IE 0x20000000 +#define IOC_IOCFG12_IE_BITN 29 +#define IOC_IOCFG12_IE_M 0x20000000 +#define IOC_IOCFG12_IE_S 29 // Field: [28:27] WU_CFG // @@ -4589,9 +4589,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG12_WU_CFG_W 2 -#define IOC_IOCFG12_WU_CFG_M 0x18000000 -#define IOC_IOCFG12_WU_CFG_S 27 +#define IOC_IOCFG12_WU_CFG_W 2 +#define IOC_IOCFG12_WU_CFG_M 0x18000000 +#define IOC_IOCFG12_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -4613,15 +4613,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG12_IOMODE_W 3 -#define IOC_IOCFG12_IOMODE_M 0x07000000 -#define IOC_IOCFG12_IOMODE_S 24 -#define IOC_IOCFG12_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG12_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG12_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG12_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG12_IOMODE_INV 0x01000000 -#define IOC_IOCFG12_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG12_IOMODE_W 3 +#define IOC_IOCFG12_IOMODE_M 0x07000000 +#define IOC_IOCFG12_IOMODE_S 24 +#define IOC_IOCFG12_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG12_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG12_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG12_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG12_IOMODE_INV 0x01000000 +#define IOC_IOCFG12_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -4629,10 +4629,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG12_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG12_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG12_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG12_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG12_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG12_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG12_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG12_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -4640,10 +4640,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG12_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG12_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG12_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG12_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG12_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG12_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG12_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG12_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -4651,20 +4651,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG12_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG12_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG12_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG12_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG12_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG12_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG12_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG12_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG12_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG12_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG12_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG12_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG12_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG12_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG12_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG12_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -4674,13 +4674,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG12_EDGE_DET_W 2 -#define IOC_IOCFG12_EDGE_DET_M 0x00030000 -#define IOC_IOCFG12_EDGE_DET_S 16 -#define IOC_IOCFG12_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG12_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG12_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG12_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG12_EDGE_DET_W 2 +#define IOC_IOCFG12_EDGE_DET_M 0x00030000 +#define IOC_IOCFG12_EDGE_DET_S 16 +#define IOC_IOCFG12_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG12_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG12_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG12_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -4689,21 +4689,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG12_PULL_CTL_W 2 -#define IOC_IOCFG12_PULL_CTL_M 0x00006000 -#define IOC_IOCFG12_PULL_CTL_S 13 -#define IOC_IOCFG12_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG12_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG12_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG12_PULL_CTL_W 2 +#define IOC_IOCFG12_PULL_CTL_M 0x00006000 +#define IOC_IOCFG12_PULL_CTL_S 13 +#define IOC_IOCFG12_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG12_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG12_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG12_SLEW_RED 0x00001000 -#define IOC_IOCFG12_SLEW_RED_BITN 12 -#define IOC_IOCFG12_SLEW_RED_M 0x00001000 -#define IOC_IOCFG12_SLEW_RED_S 12 +#define IOC_IOCFG12_SLEW_RED 0x00001000 +#define IOC_IOCFG12_SLEW_RED_BITN 12 +#define IOC_IOCFG12_SLEW_RED_M 0x00001000 +#define IOC_IOCFG12_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -4716,12 +4716,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG12_IOCURR_W 2 -#define IOC_IOCFG12_IOCURR_M 0x00000C00 -#define IOC_IOCFG12_IOCURR_S 10 -#define IOC_IOCFG12_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG12_IOCURR_4MA 0x00000400 -#define IOC_IOCFG12_IOCURR_2MA 0x00000000 +#define IOC_IOCFG12_IOCURR_W 2 +#define IOC_IOCFG12_IOCURR_M 0x00000C00 +#define IOC_IOCFG12_IOCURR_S 10 +#define IOC_IOCFG12_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG12_IOCURR_4MA 0x00000400 +#define IOC_IOCFG12_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -4740,13 +4740,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG12_IOSTR_W 2 -#define IOC_IOCFG12_IOSTR_M 0x00000300 -#define IOC_IOCFG12_IOSTR_S 8 -#define IOC_IOCFG12_IOSTR_MAX 0x00000300 -#define IOC_IOCFG12_IOSTR_MED 0x00000200 -#define IOC_IOCFG12_IOSTR_MIN 0x00000100 -#define IOC_IOCFG12_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG12_IOSTR_W 2 +#define IOC_IOCFG12_IOSTR_M 0x00000300 +#define IOC_IOCFG12_IOSTR_S 8 +#define IOC_IOCFG12_IOSTR_MAX 0x00000300 +#define IOC_IOCFG12_IOSTR_MED 0x00000200 +#define IOC_IOCFG12_IOSTR_MIN 0x00000100 +#define IOC_IOCFG12_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -4754,10 +4754,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG12_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG12_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG12_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG12_IOEV_RTC_EN_S 7 +#define IOC_IOCFG12_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG12_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG12_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG12_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -4765,10 +4765,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG12_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG12_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG12_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG12_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG12_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG12_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG12_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG12_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -4860,55 +4860,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG12_PORT_ID_W 6 -#define IOC_IOCFG12_PORT_ID_M 0x0000003F -#define IOC_IOCFG12_PORT_ID_S 0 -#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG12_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG12_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG12_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG12_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG12_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG12_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG12_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG12_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG12_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG12_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG12_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG12_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG12_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG12_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG12_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG12_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG12_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG12_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG12_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG12_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG12_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG12_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG12_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG12_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG12_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG12_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG12_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG12_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG12_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG12_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG12_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG12_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG12_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG12_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG12_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG12_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG12_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG12_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG12_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG12_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG12_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG12_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG12_PORT_ID_W 6 +#define IOC_IOCFG12_PORT_ID_M 0x0000003F +#define IOC_IOCFG12_PORT_ID_S 0 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG12_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG12_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG12_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG12_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG12_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG12_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG12_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG12_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG12_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG12_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG12_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG12_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG12_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG12_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG12_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG12_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG12_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG12_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG12_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG12_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG12_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG12_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG12_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG12_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG12_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG12_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG12_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG12_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG12_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG12_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG12_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG12_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG12_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG12_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG12_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG12_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG12_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG12_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG12_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -4919,10 +4919,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG13_HYST_EN 0x40000000 -#define IOC_IOCFG13_HYST_EN_BITN 30 -#define IOC_IOCFG13_HYST_EN_M 0x40000000 -#define IOC_IOCFG13_HYST_EN_S 30 +#define IOC_IOCFG13_HYST_EN 0x40000000 +#define IOC_IOCFG13_HYST_EN_BITN 30 +#define IOC_IOCFG13_HYST_EN_M 0x40000000 +#define IOC_IOCFG13_HYST_EN_S 30 // Field: [29] IE // @@ -4931,10 +4931,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG13_IE 0x20000000 -#define IOC_IOCFG13_IE_BITN 29 -#define IOC_IOCFG13_IE_M 0x20000000 -#define IOC_IOCFG13_IE_S 29 +#define IOC_IOCFG13_IE 0x20000000 +#define IOC_IOCFG13_IE_BITN 29 +#define IOC_IOCFG13_IE_M 0x20000000 +#define IOC_IOCFG13_IE_S 29 // Field: [28:27] WU_CFG // @@ -4956,9 +4956,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG13_WU_CFG_W 2 -#define IOC_IOCFG13_WU_CFG_M 0x18000000 -#define IOC_IOCFG13_WU_CFG_S 27 +#define IOC_IOCFG13_WU_CFG_W 2 +#define IOC_IOCFG13_WU_CFG_M 0x18000000 +#define IOC_IOCFG13_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -4980,15 +4980,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG13_IOMODE_W 3 -#define IOC_IOCFG13_IOMODE_M 0x07000000 -#define IOC_IOCFG13_IOMODE_S 24 -#define IOC_IOCFG13_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG13_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG13_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG13_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG13_IOMODE_INV 0x01000000 -#define IOC_IOCFG13_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG13_IOMODE_W 3 +#define IOC_IOCFG13_IOMODE_M 0x07000000 +#define IOC_IOCFG13_IOMODE_S 24 +#define IOC_IOCFG13_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG13_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG13_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG13_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG13_IOMODE_INV 0x01000000 +#define IOC_IOCFG13_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -4996,10 +4996,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG13_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG13_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG13_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG13_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG13_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG13_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG13_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG13_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -5007,10 +5007,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG13_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG13_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG13_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG13_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG13_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG13_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG13_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG13_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -5018,20 +5018,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG13_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG13_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG13_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG13_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG13_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG13_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG13_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG13_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG13_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG13_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG13_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG13_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG13_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG13_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG13_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG13_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -5041,13 +5041,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG13_EDGE_DET_W 2 -#define IOC_IOCFG13_EDGE_DET_M 0x00030000 -#define IOC_IOCFG13_EDGE_DET_S 16 -#define IOC_IOCFG13_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG13_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG13_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG13_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG13_EDGE_DET_W 2 +#define IOC_IOCFG13_EDGE_DET_M 0x00030000 +#define IOC_IOCFG13_EDGE_DET_S 16 +#define IOC_IOCFG13_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG13_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG13_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG13_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -5056,21 +5056,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG13_PULL_CTL_W 2 -#define IOC_IOCFG13_PULL_CTL_M 0x00006000 -#define IOC_IOCFG13_PULL_CTL_S 13 -#define IOC_IOCFG13_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG13_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG13_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG13_PULL_CTL_W 2 +#define IOC_IOCFG13_PULL_CTL_M 0x00006000 +#define IOC_IOCFG13_PULL_CTL_S 13 +#define IOC_IOCFG13_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG13_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG13_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG13_SLEW_RED 0x00001000 -#define IOC_IOCFG13_SLEW_RED_BITN 12 -#define IOC_IOCFG13_SLEW_RED_M 0x00001000 -#define IOC_IOCFG13_SLEW_RED_S 12 +#define IOC_IOCFG13_SLEW_RED 0x00001000 +#define IOC_IOCFG13_SLEW_RED_BITN 12 +#define IOC_IOCFG13_SLEW_RED_M 0x00001000 +#define IOC_IOCFG13_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -5083,12 +5083,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG13_IOCURR_W 2 -#define IOC_IOCFG13_IOCURR_M 0x00000C00 -#define IOC_IOCFG13_IOCURR_S 10 -#define IOC_IOCFG13_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG13_IOCURR_4MA 0x00000400 -#define IOC_IOCFG13_IOCURR_2MA 0x00000000 +#define IOC_IOCFG13_IOCURR_W 2 +#define IOC_IOCFG13_IOCURR_M 0x00000C00 +#define IOC_IOCFG13_IOCURR_S 10 +#define IOC_IOCFG13_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG13_IOCURR_4MA 0x00000400 +#define IOC_IOCFG13_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -5107,13 +5107,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG13_IOSTR_W 2 -#define IOC_IOCFG13_IOSTR_M 0x00000300 -#define IOC_IOCFG13_IOSTR_S 8 -#define IOC_IOCFG13_IOSTR_MAX 0x00000300 -#define IOC_IOCFG13_IOSTR_MED 0x00000200 -#define IOC_IOCFG13_IOSTR_MIN 0x00000100 -#define IOC_IOCFG13_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG13_IOSTR_W 2 +#define IOC_IOCFG13_IOSTR_M 0x00000300 +#define IOC_IOCFG13_IOSTR_S 8 +#define IOC_IOCFG13_IOSTR_MAX 0x00000300 +#define IOC_IOCFG13_IOSTR_MED 0x00000200 +#define IOC_IOCFG13_IOSTR_MIN 0x00000100 +#define IOC_IOCFG13_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -5121,10 +5121,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG13_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG13_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG13_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG13_IOEV_RTC_EN_S 7 +#define IOC_IOCFG13_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG13_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG13_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG13_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -5132,10 +5132,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG13_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG13_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG13_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG13_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG13_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG13_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG13_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG13_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -5227,55 +5227,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG13_PORT_ID_W 6 -#define IOC_IOCFG13_PORT_ID_M 0x0000003F -#define IOC_IOCFG13_PORT_ID_S 0 -#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG13_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG13_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG13_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG13_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG13_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG13_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG13_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG13_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG13_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG13_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG13_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG13_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG13_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG13_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG13_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG13_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG13_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG13_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG13_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG13_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG13_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG13_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG13_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG13_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG13_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG13_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG13_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG13_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG13_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG13_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG13_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG13_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG13_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG13_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG13_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG13_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG13_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG13_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG13_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG13_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG13_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG13_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG13_PORT_ID_W 6 +#define IOC_IOCFG13_PORT_ID_M 0x0000003F +#define IOC_IOCFG13_PORT_ID_S 0 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG13_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG13_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG13_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG13_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG13_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG13_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG13_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG13_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG13_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG13_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG13_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG13_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG13_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG13_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG13_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG13_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG13_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG13_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG13_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG13_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG13_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG13_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG13_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG13_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG13_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG13_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG13_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG13_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG13_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG13_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG13_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG13_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG13_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG13_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG13_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG13_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG13_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG13_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG13_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -5286,10 +5286,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG14_HYST_EN 0x40000000 -#define IOC_IOCFG14_HYST_EN_BITN 30 -#define IOC_IOCFG14_HYST_EN_M 0x40000000 -#define IOC_IOCFG14_HYST_EN_S 30 +#define IOC_IOCFG14_HYST_EN 0x40000000 +#define IOC_IOCFG14_HYST_EN_BITN 30 +#define IOC_IOCFG14_HYST_EN_M 0x40000000 +#define IOC_IOCFG14_HYST_EN_S 30 // Field: [29] IE // @@ -5298,10 +5298,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG14_IE 0x20000000 -#define IOC_IOCFG14_IE_BITN 29 -#define IOC_IOCFG14_IE_M 0x20000000 -#define IOC_IOCFG14_IE_S 29 +#define IOC_IOCFG14_IE 0x20000000 +#define IOC_IOCFG14_IE_BITN 29 +#define IOC_IOCFG14_IE_M 0x20000000 +#define IOC_IOCFG14_IE_S 29 // Field: [28:27] WU_CFG // @@ -5323,9 +5323,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG14_WU_CFG_W 2 -#define IOC_IOCFG14_WU_CFG_M 0x18000000 -#define IOC_IOCFG14_WU_CFG_S 27 +#define IOC_IOCFG14_WU_CFG_W 2 +#define IOC_IOCFG14_WU_CFG_M 0x18000000 +#define IOC_IOCFG14_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -5347,15 +5347,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG14_IOMODE_W 3 -#define IOC_IOCFG14_IOMODE_M 0x07000000 -#define IOC_IOCFG14_IOMODE_S 24 -#define IOC_IOCFG14_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG14_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG14_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG14_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG14_IOMODE_INV 0x01000000 -#define IOC_IOCFG14_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG14_IOMODE_W 3 +#define IOC_IOCFG14_IOMODE_M 0x07000000 +#define IOC_IOCFG14_IOMODE_S 24 +#define IOC_IOCFG14_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG14_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG14_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG14_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG14_IOMODE_INV 0x01000000 +#define IOC_IOCFG14_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -5363,10 +5363,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG14_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG14_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG14_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG14_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG14_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG14_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG14_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG14_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -5374,10 +5374,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG14_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG14_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG14_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG14_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG14_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG14_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG14_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG14_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -5385,20 +5385,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG14_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG14_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG14_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG14_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG14_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG14_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG14_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG14_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG14_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG14_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG14_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG14_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG14_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG14_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG14_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG14_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -5408,13 +5408,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG14_EDGE_DET_W 2 -#define IOC_IOCFG14_EDGE_DET_M 0x00030000 -#define IOC_IOCFG14_EDGE_DET_S 16 -#define IOC_IOCFG14_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG14_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG14_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG14_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG14_EDGE_DET_W 2 +#define IOC_IOCFG14_EDGE_DET_M 0x00030000 +#define IOC_IOCFG14_EDGE_DET_S 16 +#define IOC_IOCFG14_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG14_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG14_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG14_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -5423,21 +5423,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG14_PULL_CTL_W 2 -#define IOC_IOCFG14_PULL_CTL_M 0x00006000 -#define IOC_IOCFG14_PULL_CTL_S 13 -#define IOC_IOCFG14_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG14_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG14_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG14_PULL_CTL_W 2 +#define IOC_IOCFG14_PULL_CTL_M 0x00006000 +#define IOC_IOCFG14_PULL_CTL_S 13 +#define IOC_IOCFG14_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG14_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG14_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG14_SLEW_RED 0x00001000 -#define IOC_IOCFG14_SLEW_RED_BITN 12 -#define IOC_IOCFG14_SLEW_RED_M 0x00001000 -#define IOC_IOCFG14_SLEW_RED_S 12 +#define IOC_IOCFG14_SLEW_RED 0x00001000 +#define IOC_IOCFG14_SLEW_RED_BITN 12 +#define IOC_IOCFG14_SLEW_RED_M 0x00001000 +#define IOC_IOCFG14_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -5450,12 +5450,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG14_IOCURR_W 2 -#define IOC_IOCFG14_IOCURR_M 0x00000C00 -#define IOC_IOCFG14_IOCURR_S 10 -#define IOC_IOCFG14_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG14_IOCURR_4MA 0x00000400 -#define IOC_IOCFG14_IOCURR_2MA 0x00000000 +#define IOC_IOCFG14_IOCURR_W 2 +#define IOC_IOCFG14_IOCURR_M 0x00000C00 +#define IOC_IOCFG14_IOCURR_S 10 +#define IOC_IOCFG14_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG14_IOCURR_4MA 0x00000400 +#define IOC_IOCFG14_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -5474,13 +5474,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG14_IOSTR_W 2 -#define IOC_IOCFG14_IOSTR_M 0x00000300 -#define IOC_IOCFG14_IOSTR_S 8 -#define IOC_IOCFG14_IOSTR_MAX 0x00000300 -#define IOC_IOCFG14_IOSTR_MED 0x00000200 -#define IOC_IOCFG14_IOSTR_MIN 0x00000100 -#define IOC_IOCFG14_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG14_IOSTR_W 2 +#define IOC_IOCFG14_IOSTR_M 0x00000300 +#define IOC_IOCFG14_IOSTR_S 8 +#define IOC_IOCFG14_IOSTR_MAX 0x00000300 +#define IOC_IOCFG14_IOSTR_MED 0x00000200 +#define IOC_IOCFG14_IOSTR_MIN 0x00000100 +#define IOC_IOCFG14_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -5488,10 +5488,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG14_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG14_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG14_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG14_IOEV_RTC_EN_S 7 +#define IOC_IOCFG14_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG14_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG14_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG14_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -5499,10 +5499,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG14_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG14_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG14_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG14_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG14_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG14_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG14_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG14_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -5594,55 +5594,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG14_PORT_ID_W 6 -#define IOC_IOCFG14_PORT_ID_M 0x0000003F -#define IOC_IOCFG14_PORT_ID_S 0 -#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG14_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG14_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG14_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG14_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG14_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG14_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG14_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG14_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG14_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG14_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG14_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG14_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG14_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG14_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG14_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG14_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG14_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG14_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG14_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG14_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG14_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG14_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG14_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG14_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG14_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG14_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG14_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG14_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG14_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG14_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG14_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG14_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG14_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG14_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG14_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG14_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG14_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG14_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG14_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG14_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG14_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG14_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG14_PORT_ID_W 6 +#define IOC_IOCFG14_PORT_ID_M 0x0000003F +#define IOC_IOCFG14_PORT_ID_S 0 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG14_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG14_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG14_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG14_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG14_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG14_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG14_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG14_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG14_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG14_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG14_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG14_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG14_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG14_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG14_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG14_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG14_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG14_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG14_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG14_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG14_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG14_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG14_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG14_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG14_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG14_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG14_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG14_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG14_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG14_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG14_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG14_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG14_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG14_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG14_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG14_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG14_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG14_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG14_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -5653,10 +5653,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG15_HYST_EN 0x40000000 -#define IOC_IOCFG15_HYST_EN_BITN 30 -#define IOC_IOCFG15_HYST_EN_M 0x40000000 -#define IOC_IOCFG15_HYST_EN_S 30 +#define IOC_IOCFG15_HYST_EN 0x40000000 +#define IOC_IOCFG15_HYST_EN_BITN 30 +#define IOC_IOCFG15_HYST_EN_M 0x40000000 +#define IOC_IOCFG15_HYST_EN_S 30 // Field: [29] IE // @@ -5665,10 +5665,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG15_IE 0x20000000 -#define IOC_IOCFG15_IE_BITN 29 -#define IOC_IOCFG15_IE_M 0x20000000 -#define IOC_IOCFG15_IE_S 29 +#define IOC_IOCFG15_IE 0x20000000 +#define IOC_IOCFG15_IE_BITN 29 +#define IOC_IOCFG15_IE_M 0x20000000 +#define IOC_IOCFG15_IE_S 29 // Field: [28:27] WU_CFG // @@ -5690,9 +5690,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG15_WU_CFG_W 2 -#define IOC_IOCFG15_WU_CFG_M 0x18000000 -#define IOC_IOCFG15_WU_CFG_S 27 +#define IOC_IOCFG15_WU_CFG_W 2 +#define IOC_IOCFG15_WU_CFG_M 0x18000000 +#define IOC_IOCFG15_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -5714,15 +5714,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG15_IOMODE_W 3 -#define IOC_IOCFG15_IOMODE_M 0x07000000 -#define IOC_IOCFG15_IOMODE_S 24 -#define IOC_IOCFG15_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG15_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG15_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG15_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG15_IOMODE_INV 0x01000000 -#define IOC_IOCFG15_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG15_IOMODE_W 3 +#define IOC_IOCFG15_IOMODE_M 0x07000000 +#define IOC_IOCFG15_IOMODE_S 24 +#define IOC_IOCFG15_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG15_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG15_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG15_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG15_IOMODE_INV 0x01000000 +#define IOC_IOCFG15_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -5730,10 +5730,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG15_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG15_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG15_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG15_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG15_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG15_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG15_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG15_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -5741,10 +5741,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG15_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG15_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG15_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG15_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG15_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG15_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG15_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG15_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -5752,20 +5752,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG15_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG15_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG15_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG15_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG15_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG15_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG15_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG15_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG15_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG15_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG15_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG15_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG15_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG15_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG15_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG15_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -5775,13 +5775,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG15_EDGE_DET_W 2 -#define IOC_IOCFG15_EDGE_DET_M 0x00030000 -#define IOC_IOCFG15_EDGE_DET_S 16 -#define IOC_IOCFG15_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG15_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG15_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG15_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG15_EDGE_DET_W 2 +#define IOC_IOCFG15_EDGE_DET_M 0x00030000 +#define IOC_IOCFG15_EDGE_DET_S 16 +#define IOC_IOCFG15_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG15_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG15_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG15_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -5790,21 +5790,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG15_PULL_CTL_W 2 -#define IOC_IOCFG15_PULL_CTL_M 0x00006000 -#define IOC_IOCFG15_PULL_CTL_S 13 -#define IOC_IOCFG15_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG15_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG15_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG15_PULL_CTL_W 2 +#define IOC_IOCFG15_PULL_CTL_M 0x00006000 +#define IOC_IOCFG15_PULL_CTL_S 13 +#define IOC_IOCFG15_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG15_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG15_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG15_SLEW_RED 0x00001000 -#define IOC_IOCFG15_SLEW_RED_BITN 12 -#define IOC_IOCFG15_SLEW_RED_M 0x00001000 -#define IOC_IOCFG15_SLEW_RED_S 12 +#define IOC_IOCFG15_SLEW_RED 0x00001000 +#define IOC_IOCFG15_SLEW_RED_BITN 12 +#define IOC_IOCFG15_SLEW_RED_M 0x00001000 +#define IOC_IOCFG15_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -5817,12 +5817,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG15_IOCURR_W 2 -#define IOC_IOCFG15_IOCURR_M 0x00000C00 -#define IOC_IOCFG15_IOCURR_S 10 -#define IOC_IOCFG15_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG15_IOCURR_4MA 0x00000400 -#define IOC_IOCFG15_IOCURR_2MA 0x00000000 +#define IOC_IOCFG15_IOCURR_W 2 +#define IOC_IOCFG15_IOCURR_M 0x00000C00 +#define IOC_IOCFG15_IOCURR_S 10 +#define IOC_IOCFG15_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG15_IOCURR_4MA 0x00000400 +#define IOC_IOCFG15_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -5841,13 +5841,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG15_IOSTR_W 2 -#define IOC_IOCFG15_IOSTR_M 0x00000300 -#define IOC_IOCFG15_IOSTR_S 8 -#define IOC_IOCFG15_IOSTR_MAX 0x00000300 -#define IOC_IOCFG15_IOSTR_MED 0x00000200 -#define IOC_IOCFG15_IOSTR_MIN 0x00000100 -#define IOC_IOCFG15_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG15_IOSTR_W 2 +#define IOC_IOCFG15_IOSTR_M 0x00000300 +#define IOC_IOCFG15_IOSTR_S 8 +#define IOC_IOCFG15_IOSTR_MAX 0x00000300 +#define IOC_IOCFG15_IOSTR_MED 0x00000200 +#define IOC_IOCFG15_IOSTR_MIN 0x00000100 +#define IOC_IOCFG15_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -5855,10 +5855,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG15_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG15_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG15_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG15_IOEV_RTC_EN_S 7 +#define IOC_IOCFG15_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG15_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG15_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG15_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -5866,10 +5866,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG15_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG15_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG15_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG15_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG15_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG15_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG15_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG15_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -5961,55 +5961,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG15_PORT_ID_W 6 -#define IOC_IOCFG15_PORT_ID_M 0x0000003F -#define IOC_IOCFG15_PORT_ID_S 0 -#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG15_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG15_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG15_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG15_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG15_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG15_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG15_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG15_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG15_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG15_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG15_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG15_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG15_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG15_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG15_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG15_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG15_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG15_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG15_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG15_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG15_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG15_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG15_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG15_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG15_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG15_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG15_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG15_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG15_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG15_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG15_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG15_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG15_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG15_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG15_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG15_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG15_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG15_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG15_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG15_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG15_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG15_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG15_PORT_ID_W 6 +#define IOC_IOCFG15_PORT_ID_M 0x0000003F +#define IOC_IOCFG15_PORT_ID_S 0 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG15_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG15_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG15_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG15_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG15_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG15_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG15_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG15_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG15_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG15_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG15_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG15_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG15_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG15_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG15_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG15_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG15_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG15_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG15_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG15_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG15_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG15_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG15_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG15_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG15_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG15_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG15_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG15_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG15_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG15_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG15_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG15_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG15_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG15_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG15_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG15_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG15_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG15_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG15_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -6020,10 +6020,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG16_HYST_EN 0x40000000 -#define IOC_IOCFG16_HYST_EN_BITN 30 -#define IOC_IOCFG16_HYST_EN_M 0x40000000 -#define IOC_IOCFG16_HYST_EN_S 30 +#define IOC_IOCFG16_HYST_EN 0x40000000 +#define IOC_IOCFG16_HYST_EN_BITN 30 +#define IOC_IOCFG16_HYST_EN_M 0x40000000 +#define IOC_IOCFG16_HYST_EN_S 30 // Field: [29] IE // @@ -6032,10 +6032,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG16_IE 0x20000000 -#define IOC_IOCFG16_IE_BITN 29 -#define IOC_IOCFG16_IE_M 0x20000000 -#define IOC_IOCFG16_IE_S 29 +#define IOC_IOCFG16_IE 0x20000000 +#define IOC_IOCFG16_IE_BITN 29 +#define IOC_IOCFG16_IE_M 0x20000000 +#define IOC_IOCFG16_IE_S 29 // Field: [28:27] WU_CFG // @@ -6057,9 +6057,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG16_WU_CFG_W 2 -#define IOC_IOCFG16_WU_CFG_M 0x18000000 -#define IOC_IOCFG16_WU_CFG_S 27 +#define IOC_IOCFG16_WU_CFG_W 2 +#define IOC_IOCFG16_WU_CFG_M 0x18000000 +#define IOC_IOCFG16_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -6081,15 +6081,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG16_IOMODE_W 3 -#define IOC_IOCFG16_IOMODE_M 0x07000000 -#define IOC_IOCFG16_IOMODE_S 24 -#define IOC_IOCFG16_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG16_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG16_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG16_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG16_IOMODE_INV 0x01000000 -#define IOC_IOCFG16_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG16_IOMODE_W 3 +#define IOC_IOCFG16_IOMODE_M 0x07000000 +#define IOC_IOCFG16_IOMODE_S 24 +#define IOC_IOCFG16_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG16_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG16_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG16_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG16_IOMODE_INV 0x01000000 +#define IOC_IOCFG16_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -6097,10 +6097,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG16_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG16_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG16_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG16_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG16_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG16_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG16_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG16_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -6108,10 +6108,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG16_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG16_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG16_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG16_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG16_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG16_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG16_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG16_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -6119,20 +6119,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG16_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG16_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG16_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG16_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG16_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG16_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG16_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG16_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG16_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG16_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG16_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG16_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG16_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG16_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG16_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG16_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -6142,13 +6142,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG16_EDGE_DET_W 2 -#define IOC_IOCFG16_EDGE_DET_M 0x00030000 -#define IOC_IOCFG16_EDGE_DET_S 16 -#define IOC_IOCFG16_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG16_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG16_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG16_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG16_EDGE_DET_W 2 +#define IOC_IOCFG16_EDGE_DET_M 0x00030000 +#define IOC_IOCFG16_EDGE_DET_S 16 +#define IOC_IOCFG16_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG16_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG16_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG16_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -6157,21 +6157,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG16_PULL_CTL_W 2 -#define IOC_IOCFG16_PULL_CTL_M 0x00006000 -#define IOC_IOCFG16_PULL_CTL_S 13 -#define IOC_IOCFG16_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG16_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG16_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG16_PULL_CTL_W 2 +#define IOC_IOCFG16_PULL_CTL_M 0x00006000 +#define IOC_IOCFG16_PULL_CTL_S 13 +#define IOC_IOCFG16_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG16_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG16_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG16_SLEW_RED 0x00001000 -#define IOC_IOCFG16_SLEW_RED_BITN 12 -#define IOC_IOCFG16_SLEW_RED_M 0x00001000 -#define IOC_IOCFG16_SLEW_RED_S 12 +#define IOC_IOCFG16_SLEW_RED 0x00001000 +#define IOC_IOCFG16_SLEW_RED_BITN 12 +#define IOC_IOCFG16_SLEW_RED_M 0x00001000 +#define IOC_IOCFG16_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -6184,12 +6184,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG16_IOCURR_W 2 -#define IOC_IOCFG16_IOCURR_M 0x00000C00 -#define IOC_IOCFG16_IOCURR_S 10 -#define IOC_IOCFG16_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG16_IOCURR_4MA 0x00000400 -#define IOC_IOCFG16_IOCURR_2MA 0x00000000 +#define IOC_IOCFG16_IOCURR_W 2 +#define IOC_IOCFG16_IOCURR_M 0x00000C00 +#define IOC_IOCFG16_IOCURR_S 10 +#define IOC_IOCFG16_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG16_IOCURR_4MA 0x00000400 +#define IOC_IOCFG16_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -6208,13 +6208,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG16_IOSTR_W 2 -#define IOC_IOCFG16_IOSTR_M 0x00000300 -#define IOC_IOCFG16_IOSTR_S 8 -#define IOC_IOCFG16_IOSTR_MAX 0x00000300 -#define IOC_IOCFG16_IOSTR_MED 0x00000200 -#define IOC_IOCFG16_IOSTR_MIN 0x00000100 -#define IOC_IOCFG16_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG16_IOSTR_W 2 +#define IOC_IOCFG16_IOSTR_M 0x00000300 +#define IOC_IOCFG16_IOSTR_S 8 +#define IOC_IOCFG16_IOSTR_MAX 0x00000300 +#define IOC_IOCFG16_IOSTR_MED 0x00000200 +#define IOC_IOCFG16_IOSTR_MIN 0x00000100 +#define IOC_IOCFG16_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -6222,10 +6222,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG16_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG16_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG16_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG16_IOEV_RTC_EN_S 7 +#define IOC_IOCFG16_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG16_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG16_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG16_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -6233,10 +6233,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG16_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG16_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG16_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG16_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG16_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG16_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG16_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG16_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -6328,55 +6328,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG16_PORT_ID_W 6 -#define IOC_IOCFG16_PORT_ID_M 0x0000003F -#define IOC_IOCFG16_PORT_ID_S 0 -#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG16_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG16_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG16_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG16_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG16_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG16_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG16_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG16_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG16_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG16_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG16_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG16_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG16_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG16_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG16_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG16_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG16_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG16_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG16_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG16_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG16_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG16_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG16_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG16_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG16_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG16_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG16_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG16_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG16_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG16_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG16_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG16_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG16_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG16_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG16_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG16_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG16_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG16_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG16_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG16_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG16_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG16_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG16_PORT_ID_W 6 +#define IOC_IOCFG16_PORT_ID_M 0x0000003F +#define IOC_IOCFG16_PORT_ID_S 0 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG16_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG16_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG16_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG16_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG16_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG16_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG16_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG16_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG16_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG16_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG16_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG16_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG16_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG16_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG16_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG16_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG16_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG16_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG16_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG16_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG16_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG16_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG16_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG16_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG16_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG16_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG16_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG16_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG16_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG16_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG16_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG16_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG16_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG16_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG16_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG16_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG16_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG16_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG16_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -6387,10 +6387,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG17_HYST_EN 0x40000000 -#define IOC_IOCFG17_HYST_EN_BITN 30 -#define IOC_IOCFG17_HYST_EN_M 0x40000000 -#define IOC_IOCFG17_HYST_EN_S 30 +#define IOC_IOCFG17_HYST_EN 0x40000000 +#define IOC_IOCFG17_HYST_EN_BITN 30 +#define IOC_IOCFG17_HYST_EN_M 0x40000000 +#define IOC_IOCFG17_HYST_EN_S 30 // Field: [29] IE // @@ -6399,10 +6399,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG17_IE 0x20000000 -#define IOC_IOCFG17_IE_BITN 29 -#define IOC_IOCFG17_IE_M 0x20000000 -#define IOC_IOCFG17_IE_S 29 +#define IOC_IOCFG17_IE 0x20000000 +#define IOC_IOCFG17_IE_BITN 29 +#define IOC_IOCFG17_IE_M 0x20000000 +#define IOC_IOCFG17_IE_S 29 // Field: [28:27] WU_CFG // @@ -6424,9 +6424,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG17_WU_CFG_W 2 -#define IOC_IOCFG17_WU_CFG_M 0x18000000 -#define IOC_IOCFG17_WU_CFG_S 27 +#define IOC_IOCFG17_WU_CFG_W 2 +#define IOC_IOCFG17_WU_CFG_M 0x18000000 +#define IOC_IOCFG17_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -6448,15 +6448,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG17_IOMODE_W 3 -#define IOC_IOCFG17_IOMODE_M 0x07000000 -#define IOC_IOCFG17_IOMODE_S 24 -#define IOC_IOCFG17_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG17_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG17_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG17_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG17_IOMODE_INV 0x01000000 -#define IOC_IOCFG17_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG17_IOMODE_W 3 +#define IOC_IOCFG17_IOMODE_M 0x07000000 +#define IOC_IOCFG17_IOMODE_S 24 +#define IOC_IOCFG17_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG17_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG17_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG17_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG17_IOMODE_INV 0x01000000 +#define IOC_IOCFG17_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -6464,10 +6464,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG17_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG17_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG17_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG17_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG17_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG17_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG17_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG17_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -6475,10 +6475,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG17_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG17_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG17_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG17_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG17_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG17_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG17_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG17_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -6486,20 +6486,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG17_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG17_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG17_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG17_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG17_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG17_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG17_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG17_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG17_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG17_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG17_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG17_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG17_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG17_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG17_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG17_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -6509,13 +6509,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG17_EDGE_DET_W 2 -#define IOC_IOCFG17_EDGE_DET_M 0x00030000 -#define IOC_IOCFG17_EDGE_DET_S 16 -#define IOC_IOCFG17_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG17_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG17_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG17_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG17_EDGE_DET_W 2 +#define IOC_IOCFG17_EDGE_DET_M 0x00030000 +#define IOC_IOCFG17_EDGE_DET_S 16 +#define IOC_IOCFG17_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG17_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG17_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG17_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -6524,21 +6524,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG17_PULL_CTL_W 2 -#define IOC_IOCFG17_PULL_CTL_M 0x00006000 -#define IOC_IOCFG17_PULL_CTL_S 13 -#define IOC_IOCFG17_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG17_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG17_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG17_PULL_CTL_W 2 +#define IOC_IOCFG17_PULL_CTL_M 0x00006000 +#define IOC_IOCFG17_PULL_CTL_S 13 +#define IOC_IOCFG17_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG17_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG17_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG17_SLEW_RED 0x00001000 -#define IOC_IOCFG17_SLEW_RED_BITN 12 -#define IOC_IOCFG17_SLEW_RED_M 0x00001000 -#define IOC_IOCFG17_SLEW_RED_S 12 +#define IOC_IOCFG17_SLEW_RED 0x00001000 +#define IOC_IOCFG17_SLEW_RED_BITN 12 +#define IOC_IOCFG17_SLEW_RED_M 0x00001000 +#define IOC_IOCFG17_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -6551,12 +6551,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG17_IOCURR_W 2 -#define IOC_IOCFG17_IOCURR_M 0x00000C00 -#define IOC_IOCFG17_IOCURR_S 10 -#define IOC_IOCFG17_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG17_IOCURR_4MA 0x00000400 -#define IOC_IOCFG17_IOCURR_2MA 0x00000000 +#define IOC_IOCFG17_IOCURR_W 2 +#define IOC_IOCFG17_IOCURR_M 0x00000C00 +#define IOC_IOCFG17_IOCURR_S 10 +#define IOC_IOCFG17_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG17_IOCURR_4MA 0x00000400 +#define IOC_IOCFG17_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -6575,13 +6575,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG17_IOSTR_W 2 -#define IOC_IOCFG17_IOSTR_M 0x00000300 -#define IOC_IOCFG17_IOSTR_S 8 -#define IOC_IOCFG17_IOSTR_MAX 0x00000300 -#define IOC_IOCFG17_IOSTR_MED 0x00000200 -#define IOC_IOCFG17_IOSTR_MIN 0x00000100 -#define IOC_IOCFG17_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG17_IOSTR_W 2 +#define IOC_IOCFG17_IOSTR_M 0x00000300 +#define IOC_IOCFG17_IOSTR_S 8 +#define IOC_IOCFG17_IOSTR_MAX 0x00000300 +#define IOC_IOCFG17_IOSTR_MED 0x00000200 +#define IOC_IOCFG17_IOSTR_MIN 0x00000100 +#define IOC_IOCFG17_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -6589,10 +6589,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG17_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG17_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG17_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG17_IOEV_RTC_EN_S 7 +#define IOC_IOCFG17_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG17_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG17_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG17_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -6600,10 +6600,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG17_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG17_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG17_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG17_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG17_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG17_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG17_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG17_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -6695,55 +6695,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG17_PORT_ID_W 6 -#define IOC_IOCFG17_PORT_ID_M 0x0000003F -#define IOC_IOCFG17_PORT_ID_S 0 -#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG17_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG17_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG17_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG17_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG17_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG17_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG17_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG17_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG17_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG17_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG17_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG17_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG17_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG17_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG17_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG17_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG17_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG17_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG17_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG17_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG17_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG17_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG17_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG17_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG17_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG17_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG17_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG17_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG17_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG17_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG17_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG17_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG17_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG17_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG17_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG17_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG17_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG17_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG17_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG17_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG17_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG17_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG17_PORT_ID_W 6 +#define IOC_IOCFG17_PORT_ID_M 0x0000003F +#define IOC_IOCFG17_PORT_ID_S 0 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG17_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG17_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG17_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG17_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG17_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG17_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG17_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG17_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG17_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG17_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG17_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG17_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG17_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG17_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG17_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG17_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG17_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG17_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG17_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG17_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG17_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG17_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG17_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG17_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG17_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG17_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG17_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG17_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG17_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG17_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG17_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG17_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG17_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG17_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG17_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG17_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG17_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG17_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG17_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -6754,10 +6754,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG18_HYST_EN 0x40000000 -#define IOC_IOCFG18_HYST_EN_BITN 30 -#define IOC_IOCFG18_HYST_EN_M 0x40000000 -#define IOC_IOCFG18_HYST_EN_S 30 +#define IOC_IOCFG18_HYST_EN 0x40000000 +#define IOC_IOCFG18_HYST_EN_BITN 30 +#define IOC_IOCFG18_HYST_EN_M 0x40000000 +#define IOC_IOCFG18_HYST_EN_S 30 // Field: [29] IE // @@ -6766,10 +6766,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG18_IE 0x20000000 -#define IOC_IOCFG18_IE_BITN 29 -#define IOC_IOCFG18_IE_M 0x20000000 -#define IOC_IOCFG18_IE_S 29 +#define IOC_IOCFG18_IE 0x20000000 +#define IOC_IOCFG18_IE_BITN 29 +#define IOC_IOCFG18_IE_M 0x20000000 +#define IOC_IOCFG18_IE_S 29 // Field: [28:27] WU_CFG // @@ -6791,9 +6791,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG18_WU_CFG_W 2 -#define IOC_IOCFG18_WU_CFG_M 0x18000000 -#define IOC_IOCFG18_WU_CFG_S 27 +#define IOC_IOCFG18_WU_CFG_W 2 +#define IOC_IOCFG18_WU_CFG_M 0x18000000 +#define IOC_IOCFG18_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -6815,15 +6815,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG18_IOMODE_W 3 -#define IOC_IOCFG18_IOMODE_M 0x07000000 -#define IOC_IOCFG18_IOMODE_S 24 -#define IOC_IOCFG18_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG18_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG18_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG18_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG18_IOMODE_INV 0x01000000 -#define IOC_IOCFG18_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG18_IOMODE_W 3 +#define IOC_IOCFG18_IOMODE_M 0x07000000 +#define IOC_IOCFG18_IOMODE_S 24 +#define IOC_IOCFG18_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG18_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG18_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG18_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG18_IOMODE_INV 0x01000000 +#define IOC_IOCFG18_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -6831,10 +6831,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG18_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG18_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG18_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG18_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG18_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG18_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG18_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG18_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -6842,10 +6842,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG18_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG18_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG18_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG18_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG18_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG18_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG18_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG18_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -6853,20 +6853,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG18_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG18_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG18_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG18_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG18_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG18_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG18_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG18_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG18_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG18_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG18_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG18_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG18_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG18_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG18_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG18_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -6876,13 +6876,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG18_EDGE_DET_W 2 -#define IOC_IOCFG18_EDGE_DET_M 0x00030000 -#define IOC_IOCFG18_EDGE_DET_S 16 -#define IOC_IOCFG18_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG18_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG18_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG18_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG18_EDGE_DET_W 2 +#define IOC_IOCFG18_EDGE_DET_M 0x00030000 +#define IOC_IOCFG18_EDGE_DET_S 16 +#define IOC_IOCFG18_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG18_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG18_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG18_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -6891,21 +6891,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG18_PULL_CTL_W 2 -#define IOC_IOCFG18_PULL_CTL_M 0x00006000 -#define IOC_IOCFG18_PULL_CTL_S 13 -#define IOC_IOCFG18_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG18_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG18_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG18_PULL_CTL_W 2 +#define IOC_IOCFG18_PULL_CTL_M 0x00006000 +#define IOC_IOCFG18_PULL_CTL_S 13 +#define IOC_IOCFG18_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG18_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG18_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG18_SLEW_RED 0x00001000 -#define IOC_IOCFG18_SLEW_RED_BITN 12 -#define IOC_IOCFG18_SLEW_RED_M 0x00001000 -#define IOC_IOCFG18_SLEW_RED_S 12 +#define IOC_IOCFG18_SLEW_RED 0x00001000 +#define IOC_IOCFG18_SLEW_RED_BITN 12 +#define IOC_IOCFG18_SLEW_RED_M 0x00001000 +#define IOC_IOCFG18_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -6918,12 +6918,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG18_IOCURR_W 2 -#define IOC_IOCFG18_IOCURR_M 0x00000C00 -#define IOC_IOCFG18_IOCURR_S 10 -#define IOC_IOCFG18_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG18_IOCURR_4MA 0x00000400 -#define IOC_IOCFG18_IOCURR_2MA 0x00000000 +#define IOC_IOCFG18_IOCURR_W 2 +#define IOC_IOCFG18_IOCURR_M 0x00000C00 +#define IOC_IOCFG18_IOCURR_S 10 +#define IOC_IOCFG18_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG18_IOCURR_4MA 0x00000400 +#define IOC_IOCFG18_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -6942,13 +6942,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG18_IOSTR_W 2 -#define IOC_IOCFG18_IOSTR_M 0x00000300 -#define IOC_IOCFG18_IOSTR_S 8 -#define IOC_IOCFG18_IOSTR_MAX 0x00000300 -#define IOC_IOCFG18_IOSTR_MED 0x00000200 -#define IOC_IOCFG18_IOSTR_MIN 0x00000100 -#define IOC_IOCFG18_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG18_IOSTR_W 2 +#define IOC_IOCFG18_IOSTR_M 0x00000300 +#define IOC_IOCFG18_IOSTR_S 8 +#define IOC_IOCFG18_IOSTR_MAX 0x00000300 +#define IOC_IOCFG18_IOSTR_MED 0x00000200 +#define IOC_IOCFG18_IOSTR_MIN 0x00000100 +#define IOC_IOCFG18_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -6956,10 +6956,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG18_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG18_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG18_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG18_IOEV_RTC_EN_S 7 +#define IOC_IOCFG18_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG18_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG18_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG18_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -6967,10 +6967,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG18_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG18_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG18_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG18_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG18_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG18_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG18_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG18_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -7062,55 +7062,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG18_PORT_ID_W 6 -#define IOC_IOCFG18_PORT_ID_M 0x0000003F -#define IOC_IOCFG18_PORT_ID_S 0 -#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG18_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG18_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG18_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG18_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG18_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG18_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG18_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG18_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG18_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG18_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG18_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG18_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG18_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG18_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG18_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG18_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG18_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG18_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG18_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG18_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG18_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG18_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG18_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG18_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG18_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG18_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG18_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG18_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG18_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG18_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG18_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG18_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG18_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG18_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG18_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG18_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG18_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG18_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG18_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG18_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG18_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG18_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG18_PORT_ID_W 6 +#define IOC_IOCFG18_PORT_ID_M 0x0000003F +#define IOC_IOCFG18_PORT_ID_S 0 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG18_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG18_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG18_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG18_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG18_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG18_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG18_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG18_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG18_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG18_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG18_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG18_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG18_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG18_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG18_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG18_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG18_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG18_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG18_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG18_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG18_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG18_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG18_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG18_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG18_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG18_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG18_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG18_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG18_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG18_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG18_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG18_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG18_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG18_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG18_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG18_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG18_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG18_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG18_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -7121,10 +7121,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG19_HYST_EN 0x40000000 -#define IOC_IOCFG19_HYST_EN_BITN 30 -#define IOC_IOCFG19_HYST_EN_M 0x40000000 -#define IOC_IOCFG19_HYST_EN_S 30 +#define IOC_IOCFG19_HYST_EN 0x40000000 +#define IOC_IOCFG19_HYST_EN_BITN 30 +#define IOC_IOCFG19_HYST_EN_M 0x40000000 +#define IOC_IOCFG19_HYST_EN_S 30 // Field: [29] IE // @@ -7133,10 +7133,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG19_IE 0x20000000 -#define IOC_IOCFG19_IE_BITN 29 -#define IOC_IOCFG19_IE_M 0x20000000 -#define IOC_IOCFG19_IE_S 29 +#define IOC_IOCFG19_IE 0x20000000 +#define IOC_IOCFG19_IE_BITN 29 +#define IOC_IOCFG19_IE_M 0x20000000 +#define IOC_IOCFG19_IE_S 29 // Field: [28:27] WU_CFG // @@ -7158,9 +7158,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG19_WU_CFG_W 2 -#define IOC_IOCFG19_WU_CFG_M 0x18000000 -#define IOC_IOCFG19_WU_CFG_S 27 +#define IOC_IOCFG19_WU_CFG_W 2 +#define IOC_IOCFG19_WU_CFG_M 0x18000000 +#define IOC_IOCFG19_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -7182,15 +7182,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG19_IOMODE_W 3 -#define IOC_IOCFG19_IOMODE_M 0x07000000 -#define IOC_IOCFG19_IOMODE_S 24 -#define IOC_IOCFG19_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG19_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG19_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG19_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG19_IOMODE_INV 0x01000000 -#define IOC_IOCFG19_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG19_IOMODE_W 3 +#define IOC_IOCFG19_IOMODE_M 0x07000000 +#define IOC_IOCFG19_IOMODE_S 24 +#define IOC_IOCFG19_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG19_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG19_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG19_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG19_IOMODE_INV 0x01000000 +#define IOC_IOCFG19_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -7198,10 +7198,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG19_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG19_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG19_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG19_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG19_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG19_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG19_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG19_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -7209,10 +7209,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG19_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG19_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG19_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG19_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG19_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG19_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG19_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG19_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -7220,20 +7220,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG19_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG19_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG19_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG19_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG19_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG19_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG19_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG19_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG19_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG19_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG19_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG19_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG19_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG19_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG19_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG19_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -7243,13 +7243,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG19_EDGE_DET_W 2 -#define IOC_IOCFG19_EDGE_DET_M 0x00030000 -#define IOC_IOCFG19_EDGE_DET_S 16 -#define IOC_IOCFG19_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG19_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG19_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG19_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG19_EDGE_DET_W 2 +#define IOC_IOCFG19_EDGE_DET_M 0x00030000 +#define IOC_IOCFG19_EDGE_DET_S 16 +#define IOC_IOCFG19_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG19_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG19_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG19_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -7258,21 +7258,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG19_PULL_CTL_W 2 -#define IOC_IOCFG19_PULL_CTL_M 0x00006000 -#define IOC_IOCFG19_PULL_CTL_S 13 -#define IOC_IOCFG19_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG19_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG19_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG19_PULL_CTL_W 2 +#define IOC_IOCFG19_PULL_CTL_M 0x00006000 +#define IOC_IOCFG19_PULL_CTL_S 13 +#define IOC_IOCFG19_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG19_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG19_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG19_SLEW_RED 0x00001000 -#define IOC_IOCFG19_SLEW_RED_BITN 12 -#define IOC_IOCFG19_SLEW_RED_M 0x00001000 -#define IOC_IOCFG19_SLEW_RED_S 12 +#define IOC_IOCFG19_SLEW_RED 0x00001000 +#define IOC_IOCFG19_SLEW_RED_BITN 12 +#define IOC_IOCFG19_SLEW_RED_M 0x00001000 +#define IOC_IOCFG19_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -7285,12 +7285,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG19_IOCURR_W 2 -#define IOC_IOCFG19_IOCURR_M 0x00000C00 -#define IOC_IOCFG19_IOCURR_S 10 -#define IOC_IOCFG19_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG19_IOCURR_4MA 0x00000400 -#define IOC_IOCFG19_IOCURR_2MA 0x00000000 +#define IOC_IOCFG19_IOCURR_W 2 +#define IOC_IOCFG19_IOCURR_M 0x00000C00 +#define IOC_IOCFG19_IOCURR_S 10 +#define IOC_IOCFG19_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG19_IOCURR_4MA 0x00000400 +#define IOC_IOCFG19_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -7309,13 +7309,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG19_IOSTR_W 2 -#define IOC_IOCFG19_IOSTR_M 0x00000300 -#define IOC_IOCFG19_IOSTR_S 8 -#define IOC_IOCFG19_IOSTR_MAX 0x00000300 -#define IOC_IOCFG19_IOSTR_MED 0x00000200 -#define IOC_IOCFG19_IOSTR_MIN 0x00000100 -#define IOC_IOCFG19_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG19_IOSTR_W 2 +#define IOC_IOCFG19_IOSTR_M 0x00000300 +#define IOC_IOCFG19_IOSTR_S 8 +#define IOC_IOCFG19_IOSTR_MAX 0x00000300 +#define IOC_IOCFG19_IOSTR_MED 0x00000200 +#define IOC_IOCFG19_IOSTR_MIN 0x00000100 +#define IOC_IOCFG19_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -7323,10 +7323,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG19_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG19_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG19_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG19_IOEV_RTC_EN_S 7 +#define IOC_IOCFG19_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG19_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG19_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG19_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -7334,10 +7334,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG19_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG19_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG19_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG19_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG19_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG19_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG19_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG19_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -7429,55 +7429,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG19_PORT_ID_W 6 -#define IOC_IOCFG19_PORT_ID_M 0x0000003F -#define IOC_IOCFG19_PORT_ID_S 0 -#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG19_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG19_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG19_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG19_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG19_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG19_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG19_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG19_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG19_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG19_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG19_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG19_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG19_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG19_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG19_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG19_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG19_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG19_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG19_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG19_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG19_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG19_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG19_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG19_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG19_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG19_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG19_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG19_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG19_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG19_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG19_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG19_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG19_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG19_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG19_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG19_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG19_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG19_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG19_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG19_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG19_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG19_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG19_PORT_ID_W 6 +#define IOC_IOCFG19_PORT_ID_M 0x0000003F +#define IOC_IOCFG19_PORT_ID_S 0 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG19_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG19_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG19_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG19_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG19_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG19_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG19_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG19_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG19_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG19_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG19_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG19_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG19_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG19_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG19_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG19_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG19_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG19_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG19_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG19_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG19_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG19_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG19_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG19_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG19_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG19_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG19_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG19_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG19_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG19_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG19_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG19_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG19_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG19_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG19_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG19_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG19_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG19_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG19_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -7488,10 +7488,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG20_HYST_EN 0x40000000 -#define IOC_IOCFG20_HYST_EN_BITN 30 -#define IOC_IOCFG20_HYST_EN_M 0x40000000 -#define IOC_IOCFG20_HYST_EN_S 30 +#define IOC_IOCFG20_HYST_EN 0x40000000 +#define IOC_IOCFG20_HYST_EN_BITN 30 +#define IOC_IOCFG20_HYST_EN_M 0x40000000 +#define IOC_IOCFG20_HYST_EN_S 30 // Field: [29] IE // @@ -7500,10 +7500,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG20_IE 0x20000000 -#define IOC_IOCFG20_IE_BITN 29 -#define IOC_IOCFG20_IE_M 0x20000000 -#define IOC_IOCFG20_IE_S 29 +#define IOC_IOCFG20_IE 0x20000000 +#define IOC_IOCFG20_IE_BITN 29 +#define IOC_IOCFG20_IE_M 0x20000000 +#define IOC_IOCFG20_IE_S 29 // Field: [28:27] WU_CFG // @@ -7525,9 +7525,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG20_WU_CFG_W 2 -#define IOC_IOCFG20_WU_CFG_M 0x18000000 -#define IOC_IOCFG20_WU_CFG_S 27 +#define IOC_IOCFG20_WU_CFG_W 2 +#define IOC_IOCFG20_WU_CFG_M 0x18000000 +#define IOC_IOCFG20_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -7549,15 +7549,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG20_IOMODE_W 3 -#define IOC_IOCFG20_IOMODE_M 0x07000000 -#define IOC_IOCFG20_IOMODE_S 24 -#define IOC_IOCFG20_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG20_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG20_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG20_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG20_IOMODE_INV 0x01000000 -#define IOC_IOCFG20_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG20_IOMODE_W 3 +#define IOC_IOCFG20_IOMODE_M 0x07000000 +#define IOC_IOCFG20_IOMODE_S 24 +#define IOC_IOCFG20_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG20_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG20_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG20_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG20_IOMODE_INV 0x01000000 +#define IOC_IOCFG20_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -7565,10 +7565,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG20_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG20_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG20_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG20_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG20_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG20_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG20_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG20_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -7576,10 +7576,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG20_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG20_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG20_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG20_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG20_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG20_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG20_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG20_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -7587,20 +7587,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG20_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG20_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG20_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG20_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG20_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG20_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG20_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG20_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG20_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG20_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG20_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG20_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG20_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG20_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG20_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG20_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -7610,13 +7610,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG20_EDGE_DET_W 2 -#define IOC_IOCFG20_EDGE_DET_M 0x00030000 -#define IOC_IOCFG20_EDGE_DET_S 16 -#define IOC_IOCFG20_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG20_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG20_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG20_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG20_EDGE_DET_W 2 +#define IOC_IOCFG20_EDGE_DET_M 0x00030000 +#define IOC_IOCFG20_EDGE_DET_S 16 +#define IOC_IOCFG20_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG20_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG20_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG20_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -7625,21 +7625,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG20_PULL_CTL_W 2 -#define IOC_IOCFG20_PULL_CTL_M 0x00006000 -#define IOC_IOCFG20_PULL_CTL_S 13 -#define IOC_IOCFG20_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG20_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG20_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG20_PULL_CTL_W 2 +#define IOC_IOCFG20_PULL_CTL_M 0x00006000 +#define IOC_IOCFG20_PULL_CTL_S 13 +#define IOC_IOCFG20_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG20_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG20_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG20_SLEW_RED 0x00001000 -#define IOC_IOCFG20_SLEW_RED_BITN 12 -#define IOC_IOCFG20_SLEW_RED_M 0x00001000 -#define IOC_IOCFG20_SLEW_RED_S 12 +#define IOC_IOCFG20_SLEW_RED 0x00001000 +#define IOC_IOCFG20_SLEW_RED_BITN 12 +#define IOC_IOCFG20_SLEW_RED_M 0x00001000 +#define IOC_IOCFG20_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -7652,12 +7652,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG20_IOCURR_W 2 -#define IOC_IOCFG20_IOCURR_M 0x00000C00 -#define IOC_IOCFG20_IOCURR_S 10 -#define IOC_IOCFG20_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG20_IOCURR_4MA 0x00000400 -#define IOC_IOCFG20_IOCURR_2MA 0x00000000 +#define IOC_IOCFG20_IOCURR_W 2 +#define IOC_IOCFG20_IOCURR_M 0x00000C00 +#define IOC_IOCFG20_IOCURR_S 10 +#define IOC_IOCFG20_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG20_IOCURR_4MA 0x00000400 +#define IOC_IOCFG20_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -7676,13 +7676,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG20_IOSTR_W 2 -#define IOC_IOCFG20_IOSTR_M 0x00000300 -#define IOC_IOCFG20_IOSTR_S 8 -#define IOC_IOCFG20_IOSTR_MAX 0x00000300 -#define IOC_IOCFG20_IOSTR_MED 0x00000200 -#define IOC_IOCFG20_IOSTR_MIN 0x00000100 -#define IOC_IOCFG20_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG20_IOSTR_W 2 +#define IOC_IOCFG20_IOSTR_M 0x00000300 +#define IOC_IOCFG20_IOSTR_S 8 +#define IOC_IOCFG20_IOSTR_MAX 0x00000300 +#define IOC_IOCFG20_IOSTR_MED 0x00000200 +#define IOC_IOCFG20_IOSTR_MIN 0x00000100 +#define IOC_IOCFG20_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -7690,10 +7690,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG20_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG20_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG20_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG20_IOEV_RTC_EN_S 7 +#define IOC_IOCFG20_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG20_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG20_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG20_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -7701,10 +7701,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG20_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG20_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG20_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG20_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG20_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG20_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG20_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG20_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -7796,55 +7796,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG20_PORT_ID_W 6 -#define IOC_IOCFG20_PORT_ID_M 0x0000003F -#define IOC_IOCFG20_PORT_ID_S 0 -#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG20_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG20_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG20_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG20_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG20_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG20_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG20_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG20_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG20_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG20_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG20_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG20_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG20_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG20_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG20_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG20_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG20_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG20_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG20_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG20_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG20_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG20_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG20_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG20_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG20_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG20_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG20_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG20_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG20_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG20_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG20_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG20_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG20_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG20_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG20_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG20_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG20_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG20_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG20_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG20_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG20_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG20_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG20_PORT_ID_W 6 +#define IOC_IOCFG20_PORT_ID_M 0x0000003F +#define IOC_IOCFG20_PORT_ID_S 0 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG20_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG20_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG20_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG20_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG20_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG20_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG20_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG20_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG20_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG20_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG20_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG20_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG20_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG20_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG20_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG20_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG20_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG20_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG20_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG20_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG20_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG20_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG20_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG20_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG20_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG20_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG20_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG20_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG20_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG20_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG20_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG20_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG20_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG20_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG20_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG20_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG20_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG20_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG20_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -7855,10 +7855,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG21_HYST_EN 0x40000000 -#define IOC_IOCFG21_HYST_EN_BITN 30 -#define IOC_IOCFG21_HYST_EN_M 0x40000000 -#define IOC_IOCFG21_HYST_EN_S 30 +#define IOC_IOCFG21_HYST_EN 0x40000000 +#define IOC_IOCFG21_HYST_EN_BITN 30 +#define IOC_IOCFG21_HYST_EN_M 0x40000000 +#define IOC_IOCFG21_HYST_EN_S 30 // Field: [29] IE // @@ -7867,10 +7867,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG21_IE 0x20000000 -#define IOC_IOCFG21_IE_BITN 29 -#define IOC_IOCFG21_IE_M 0x20000000 -#define IOC_IOCFG21_IE_S 29 +#define IOC_IOCFG21_IE 0x20000000 +#define IOC_IOCFG21_IE_BITN 29 +#define IOC_IOCFG21_IE_M 0x20000000 +#define IOC_IOCFG21_IE_S 29 // Field: [28:27] WU_CFG // @@ -7892,9 +7892,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG21_WU_CFG_W 2 -#define IOC_IOCFG21_WU_CFG_M 0x18000000 -#define IOC_IOCFG21_WU_CFG_S 27 +#define IOC_IOCFG21_WU_CFG_W 2 +#define IOC_IOCFG21_WU_CFG_M 0x18000000 +#define IOC_IOCFG21_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -7916,15 +7916,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG21_IOMODE_W 3 -#define IOC_IOCFG21_IOMODE_M 0x07000000 -#define IOC_IOCFG21_IOMODE_S 24 -#define IOC_IOCFG21_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG21_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG21_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG21_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG21_IOMODE_INV 0x01000000 -#define IOC_IOCFG21_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG21_IOMODE_W 3 +#define IOC_IOCFG21_IOMODE_M 0x07000000 +#define IOC_IOCFG21_IOMODE_S 24 +#define IOC_IOCFG21_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG21_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG21_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG21_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG21_IOMODE_INV 0x01000000 +#define IOC_IOCFG21_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -7932,10 +7932,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG21_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG21_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG21_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG21_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG21_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG21_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG21_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG21_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -7943,10 +7943,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG21_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG21_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG21_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG21_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG21_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG21_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG21_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG21_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -7954,20 +7954,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG21_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG21_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG21_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG21_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG21_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG21_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG21_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG21_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG21_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG21_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG21_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG21_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG21_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG21_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG21_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG21_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -7977,13 +7977,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG21_EDGE_DET_W 2 -#define IOC_IOCFG21_EDGE_DET_M 0x00030000 -#define IOC_IOCFG21_EDGE_DET_S 16 -#define IOC_IOCFG21_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG21_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG21_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG21_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG21_EDGE_DET_W 2 +#define IOC_IOCFG21_EDGE_DET_M 0x00030000 +#define IOC_IOCFG21_EDGE_DET_S 16 +#define IOC_IOCFG21_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG21_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG21_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG21_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -7992,21 +7992,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG21_PULL_CTL_W 2 -#define IOC_IOCFG21_PULL_CTL_M 0x00006000 -#define IOC_IOCFG21_PULL_CTL_S 13 -#define IOC_IOCFG21_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG21_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG21_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG21_PULL_CTL_W 2 +#define IOC_IOCFG21_PULL_CTL_M 0x00006000 +#define IOC_IOCFG21_PULL_CTL_S 13 +#define IOC_IOCFG21_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG21_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG21_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG21_SLEW_RED 0x00001000 -#define IOC_IOCFG21_SLEW_RED_BITN 12 -#define IOC_IOCFG21_SLEW_RED_M 0x00001000 -#define IOC_IOCFG21_SLEW_RED_S 12 +#define IOC_IOCFG21_SLEW_RED 0x00001000 +#define IOC_IOCFG21_SLEW_RED_BITN 12 +#define IOC_IOCFG21_SLEW_RED_M 0x00001000 +#define IOC_IOCFG21_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -8019,12 +8019,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG21_IOCURR_W 2 -#define IOC_IOCFG21_IOCURR_M 0x00000C00 -#define IOC_IOCFG21_IOCURR_S 10 -#define IOC_IOCFG21_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG21_IOCURR_4MA 0x00000400 -#define IOC_IOCFG21_IOCURR_2MA 0x00000000 +#define IOC_IOCFG21_IOCURR_W 2 +#define IOC_IOCFG21_IOCURR_M 0x00000C00 +#define IOC_IOCFG21_IOCURR_S 10 +#define IOC_IOCFG21_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG21_IOCURR_4MA 0x00000400 +#define IOC_IOCFG21_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -8043,13 +8043,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG21_IOSTR_W 2 -#define IOC_IOCFG21_IOSTR_M 0x00000300 -#define IOC_IOCFG21_IOSTR_S 8 -#define IOC_IOCFG21_IOSTR_MAX 0x00000300 -#define IOC_IOCFG21_IOSTR_MED 0x00000200 -#define IOC_IOCFG21_IOSTR_MIN 0x00000100 -#define IOC_IOCFG21_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG21_IOSTR_W 2 +#define IOC_IOCFG21_IOSTR_M 0x00000300 +#define IOC_IOCFG21_IOSTR_S 8 +#define IOC_IOCFG21_IOSTR_MAX 0x00000300 +#define IOC_IOCFG21_IOSTR_MED 0x00000200 +#define IOC_IOCFG21_IOSTR_MIN 0x00000100 +#define IOC_IOCFG21_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -8057,10 +8057,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG21_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG21_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG21_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG21_IOEV_RTC_EN_S 7 +#define IOC_IOCFG21_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG21_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG21_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG21_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -8068,10 +8068,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG21_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG21_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG21_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG21_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG21_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG21_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG21_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG21_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -8163,55 +8163,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG21_PORT_ID_W 6 -#define IOC_IOCFG21_PORT_ID_M 0x0000003F -#define IOC_IOCFG21_PORT_ID_S 0 -#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG21_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG21_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG21_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG21_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG21_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG21_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG21_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG21_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG21_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG21_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG21_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG21_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG21_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG21_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG21_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG21_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG21_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG21_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG21_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG21_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG21_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG21_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG21_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG21_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG21_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG21_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG21_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG21_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG21_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG21_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG21_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG21_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG21_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG21_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG21_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG21_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG21_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG21_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG21_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG21_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG21_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG21_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG21_PORT_ID_W 6 +#define IOC_IOCFG21_PORT_ID_M 0x0000003F +#define IOC_IOCFG21_PORT_ID_S 0 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG21_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG21_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG21_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG21_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG21_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG21_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG21_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG21_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG21_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG21_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG21_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG21_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG21_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG21_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG21_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG21_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG21_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG21_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG21_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG21_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG21_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG21_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG21_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG21_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG21_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG21_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG21_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG21_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG21_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG21_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG21_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG21_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG21_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG21_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG21_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG21_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG21_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG21_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG21_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -8222,10 +8222,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG22_HYST_EN 0x40000000 -#define IOC_IOCFG22_HYST_EN_BITN 30 -#define IOC_IOCFG22_HYST_EN_M 0x40000000 -#define IOC_IOCFG22_HYST_EN_S 30 +#define IOC_IOCFG22_HYST_EN 0x40000000 +#define IOC_IOCFG22_HYST_EN_BITN 30 +#define IOC_IOCFG22_HYST_EN_M 0x40000000 +#define IOC_IOCFG22_HYST_EN_S 30 // Field: [29] IE // @@ -8234,10 +8234,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG22_IE 0x20000000 -#define IOC_IOCFG22_IE_BITN 29 -#define IOC_IOCFG22_IE_M 0x20000000 -#define IOC_IOCFG22_IE_S 29 +#define IOC_IOCFG22_IE 0x20000000 +#define IOC_IOCFG22_IE_BITN 29 +#define IOC_IOCFG22_IE_M 0x20000000 +#define IOC_IOCFG22_IE_S 29 // Field: [28:27] WU_CFG // @@ -8259,9 +8259,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG22_WU_CFG_W 2 -#define IOC_IOCFG22_WU_CFG_M 0x18000000 -#define IOC_IOCFG22_WU_CFG_S 27 +#define IOC_IOCFG22_WU_CFG_W 2 +#define IOC_IOCFG22_WU_CFG_M 0x18000000 +#define IOC_IOCFG22_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -8283,15 +8283,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG22_IOMODE_W 3 -#define IOC_IOCFG22_IOMODE_M 0x07000000 -#define IOC_IOCFG22_IOMODE_S 24 -#define IOC_IOCFG22_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG22_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG22_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG22_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG22_IOMODE_INV 0x01000000 -#define IOC_IOCFG22_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG22_IOMODE_W 3 +#define IOC_IOCFG22_IOMODE_M 0x07000000 +#define IOC_IOCFG22_IOMODE_S 24 +#define IOC_IOCFG22_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG22_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG22_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG22_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG22_IOMODE_INV 0x01000000 +#define IOC_IOCFG22_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -8299,10 +8299,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG22_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG22_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG22_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG22_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG22_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG22_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG22_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG22_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -8310,10 +8310,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG22_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG22_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG22_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG22_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG22_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG22_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG22_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG22_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -8321,20 +8321,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG22_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG22_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG22_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG22_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG22_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG22_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG22_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG22_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG22_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG22_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG22_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG22_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG22_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG22_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG22_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG22_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -8344,13 +8344,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG22_EDGE_DET_W 2 -#define IOC_IOCFG22_EDGE_DET_M 0x00030000 -#define IOC_IOCFG22_EDGE_DET_S 16 -#define IOC_IOCFG22_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG22_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG22_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG22_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG22_EDGE_DET_W 2 +#define IOC_IOCFG22_EDGE_DET_M 0x00030000 +#define IOC_IOCFG22_EDGE_DET_S 16 +#define IOC_IOCFG22_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG22_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG22_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG22_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -8359,21 +8359,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG22_PULL_CTL_W 2 -#define IOC_IOCFG22_PULL_CTL_M 0x00006000 -#define IOC_IOCFG22_PULL_CTL_S 13 -#define IOC_IOCFG22_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG22_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG22_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG22_PULL_CTL_W 2 +#define IOC_IOCFG22_PULL_CTL_M 0x00006000 +#define IOC_IOCFG22_PULL_CTL_S 13 +#define IOC_IOCFG22_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG22_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG22_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG22_SLEW_RED 0x00001000 -#define IOC_IOCFG22_SLEW_RED_BITN 12 -#define IOC_IOCFG22_SLEW_RED_M 0x00001000 -#define IOC_IOCFG22_SLEW_RED_S 12 +#define IOC_IOCFG22_SLEW_RED 0x00001000 +#define IOC_IOCFG22_SLEW_RED_BITN 12 +#define IOC_IOCFG22_SLEW_RED_M 0x00001000 +#define IOC_IOCFG22_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -8386,12 +8386,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG22_IOCURR_W 2 -#define IOC_IOCFG22_IOCURR_M 0x00000C00 -#define IOC_IOCFG22_IOCURR_S 10 -#define IOC_IOCFG22_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG22_IOCURR_4MA 0x00000400 -#define IOC_IOCFG22_IOCURR_2MA 0x00000000 +#define IOC_IOCFG22_IOCURR_W 2 +#define IOC_IOCFG22_IOCURR_M 0x00000C00 +#define IOC_IOCFG22_IOCURR_S 10 +#define IOC_IOCFG22_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG22_IOCURR_4MA 0x00000400 +#define IOC_IOCFG22_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -8410,13 +8410,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG22_IOSTR_W 2 -#define IOC_IOCFG22_IOSTR_M 0x00000300 -#define IOC_IOCFG22_IOSTR_S 8 -#define IOC_IOCFG22_IOSTR_MAX 0x00000300 -#define IOC_IOCFG22_IOSTR_MED 0x00000200 -#define IOC_IOCFG22_IOSTR_MIN 0x00000100 -#define IOC_IOCFG22_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG22_IOSTR_W 2 +#define IOC_IOCFG22_IOSTR_M 0x00000300 +#define IOC_IOCFG22_IOSTR_S 8 +#define IOC_IOCFG22_IOSTR_MAX 0x00000300 +#define IOC_IOCFG22_IOSTR_MED 0x00000200 +#define IOC_IOCFG22_IOSTR_MIN 0x00000100 +#define IOC_IOCFG22_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -8424,10 +8424,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG22_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG22_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG22_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG22_IOEV_RTC_EN_S 7 +#define IOC_IOCFG22_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG22_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG22_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG22_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -8435,10 +8435,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG22_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG22_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG22_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG22_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG22_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG22_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG22_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG22_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -8530,55 +8530,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG22_PORT_ID_W 6 -#define IOC_IOCFG22_PORT_ID_M 0x0000003F -#define IOC_IOCFG22_PORT_ID_S 0 -#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG22_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG22_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG22_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG22_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG22_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG22_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG22_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG22_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG22_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG22_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG22_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG22_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG22_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG22_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG22_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG22_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG22_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG22_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG22_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG22_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG22_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG22_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG22_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG22_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG22_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG22_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG22_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG22_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG22_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG22_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG22_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG22_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG22_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG22_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG22_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG22_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG22_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG22_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG22_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG22_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG22_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG22_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG22_PORT_ID_W 6 +#define IOC_IOCFG22_PORT_ID_M 0x0000003F +#define IOC_IOCFG22_PORT_ID_S 0 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG22_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG22_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG22_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG22_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG22_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG22_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG22_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG22_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG22_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG22_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG22_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG22_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG22_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG22_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG22_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG22_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG22_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG22_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG22_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG22_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG22_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG22_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG22_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG22_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG22_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG22_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG22_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG22_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG22_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG22_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG22_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG22_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG22_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG22_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG22_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG22_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG22_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG22_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG22_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -8589,10 +8589,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG23_HYST_EN 0x40000000 -#define IOC_IOCFG23_HYST_EN_BITN 30 -#define IOC_IOCFG23_HYST_EN_M 0x40000000 -#define IOC_IOCFG23_HYST_EN_S 30 +#define IOC_IOCFG23_HYST_EN 0x40000000 +#define IOC_IOCFG23_HYST_EN_BITN 30 +#define IOC_IOCFG23_HYST_EN_M 0x40000000 +#define IOC_IOCFG23_HYST_EN_S 30 // Field: [29] IE // @@ -8601,10 +8601,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG23_IE 0x20000000 -#define IOC_IOCFG23_IE_BITN 29 -#define IOC_IOCFG23_IE_M 0x20000000 -#define IOC_IOCFG23_IE_S 29 +#define IOC_IOCFG23_IE 0x20000000 +#define IOC_IOCFG23_IE_BITN 29 +#define IOC_IOCFG23_IE_M 0x20000000 +#define IOC_IOCFG23_IE_S 29 // Field: [28:27] WU_CFG // @@ -8626,9 +8626,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG23_WU_CFG_W 2 -#define IOC_IOCFG23_WU_CFG_M 0x18000000 -#define IOC_IOCFG23_WU_CFG_S 27 +#define IOC_IOCFG23_WU_CFG_W 2 +#define IOC_IOCFG23_WU_CFG_M 0x18000000 +#define IOC_IOCFG23_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -8650,15 +8650,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG23_IOMODE_W 3 -#define IOC_IOCFG23_IOMODE_M 0x07000000 -#define IOC_IOCFG23_IOMODE_S 24 -#define IOC_IOCFG23_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG23_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG23_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG23_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG23_IOMODE_INV 0x01000000 -#define IOC_IOCFG23_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG23_IOMODE_W 3 +#define IOC_IOCFG23_IOMODE_M 0x07000000 +#define IOC_IOCFG23_IOMODE_S 24 +#define IOC_IOCFG23_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG23_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG23_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG23_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG23_IOMODE_INV 0x01000000 +#define IOC_IOCFG23_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -8666,10 +8666,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG23_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG23_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG23_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG23_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG23_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG23_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG23_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG23_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -8677,10 +8677,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG23_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG23_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG23_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG23_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG23_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG23_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG23_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG23_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -8688,20 +8688,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG23_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG23_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG23_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG23_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG23_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG23_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG23_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG23_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG23_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG23_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG23_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG23_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG23_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG23_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG23_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG23_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -8711,13 +8711,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG23_EDGE_DET_W 2 -#define IOC_IOCFG23_EDGE_DET_M 0x00030000 -#define IOC_IOCFG23_EDGE_DET_S 16 -#define IOC_IOCFG23_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG23_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG23_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG23_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG23_EDGE_DET_W 2 +#define IOC_IOCFG23_EDGE_DET_M 0x00030000 +#define IOC_IOCFG23_EDGE_DET_S 16 +#define IOC_IOCFG23_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG23_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG23_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG23_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -8726,21 +8726,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG23_PULL_CTL_W 2 -#define IOC_IOCFG23_PULL_CTL_M 0x00006000 -#define IOC_IOCFG23_PULL_CTL_S 13 -#define IOC_IOCFG23_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG23_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG23_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG23_PULL_CTL_W 2 +#define IOC_IOCFG23_PULL_CTL_M 0x00006000 +#define IOC_IOCFG23_PULL_CTL_S 13 +#define IOC_IOCFG23_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG23_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG23_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG23_SLEW_RED 0x00001000 -#define IOC_IOCFG23_SLEW_RED_BITN 12 -#define IOC_IOCFG23_SLEW_RED_M 0x00001000 -#define IOC_IOCFG23_SLEW_RED_S 12 +#define IOC_IOCFG23_SLEW_RED 0x00001000 +#define IOC_IOCFG23_SLEW_RED_BITN 12 +#define IOC_IOCFG23_SLEW_RED_M 0x00001000 +#define IOC_IOCFG23_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -8753,12 +8753,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG23_IOCURR_W 2 -#define IOC_IOCFG23_IOCURR_M 0x00000C00 -#define IOC_IOCFG23_IOCURR_S 10 -#define IOC_IOCFG23_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG23_IOCURR_4MA 0x00000400 -#define IOC_IOCFG23_IOCURR_2MA 0x00000000 +#define IOC_IOCFG23_IOCURR_W 2 +#define IOC_IOCFG23_IOCURR_M 0x00000C00 +#define IOC_IOCFG23_IOCURR_S 10 +#define IOC_IOCFG23_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG23_IOCURR_4MA 0x00000400 +#define IOC_IOCFG23_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -8777,13 +8777,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG23_IOSTR_W 2 -#define IOC_IOCFG23_IOSTR_M 0x00000300 -#define IOC_IOCFG23_IOSTR_S 8 -#define IOC_IOCFG23_IOSTR_MAX 0x00000300 -#define IOC_IOCFG23_IOSTR_MED 0x00000200 -#define IOC_IOCFG23_IOSTR_MIN 0x00000100 -#define IOC_IOCFG23_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG23_IOSTR_W 2 +#define IOC_IOCFG23_IOSTR_M 0x00000300 +#define IOC_IOCFG23_IOSTR_S 8 +#define IOC_IOCFG23_IOSTR_MAX 0x00000300 +#define IOC_IOCFG23_IOSTR_MED 0x00000200 +#define IOC_IOCFG23_IOSTR_MIN 0x00000100 +#define IOC_IOCFG23_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -8791,10 +8791,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG23_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG23_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG23_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG23_IOEV_RTC_EN_S 7 +#define IOC_IOCFG23_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG23_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG23_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG23_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -8802,10 +8802,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG23_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG23_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG23_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG23_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG23_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG23_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG23_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG23_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -8897,55 +8897,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG23_PORT_ID_W 6 -#define IOC_IOCFG23_PORT_ID_M 0x0000003F -#define IOC_IOCFG23_PORT_ID_S 0 -#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG23_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG23_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG23_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG23_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG23_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG23_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG23_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG23_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG23_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG23_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG23_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG23_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG23_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG23_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG23_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG23_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG23_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG23_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG23_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG23_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG23_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG23_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG23_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG23_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG23_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG23_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG23_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG23_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG23_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG23_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG23_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG23_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG23_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG23_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG23_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG23_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG23_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG23_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG23_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG23_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG23_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG23_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG23_PORT_ID_W 6 +#define IOC_IOCFG23_PORT_ID_M 0x0000003F +#define IOC_IOCFG23_PORT_ID_S 0 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG23_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG23_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG23_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG23_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG23_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG23_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG23_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG23_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG23_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG23_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG23_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG23_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG23_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG23_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG23_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG23_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG23_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG23_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG23_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG23_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG23_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG23_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG23_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG23_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG23_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG23_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG23_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG23_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG23_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG23_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG23_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG23_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG23_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG23_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG23_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG23_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG23_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG23_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG23_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -8956,10 +8956,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG24_HYST_EN 0x40000000 -#define IOC_IOCFG24_HYST_EN_BITN 30 -#define IOC_IOCFG24_HYST_EN_M 0x40000000 -#define IOC_IOCFG24_HYST_EN_S 30 +#define IOC_IOCFG24_HYST_EN 0x40000000 +#define IOC_IOCFG24_HYST_EN_BITN 30 +#define IOC_IOCFG24_HYST_EN_M 0x40000000 +#define IOC_IOCFG24_HYST_EN_S 30 // Field: [29] IE // @@ -8968,10 +8968,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG24_IE 0x20000000 -#define IOC_IOCFG24_IE_BITN 29 -#define IOC_IOCFG24_IE_M 0x20000000 -#define IOC_IOCFG24_IE_S 29 +#define IOC_IOCFG24_IE 0x20000000 +#define IOC_IOCFG24_IE_BITN 29 +#define IOC_IOCFG24_IE_M 0x20000000 +#define IOC_IOCFG24_IE_S 29 // Field: [28:27] WU_CFG // @@ -8993,9 +8993,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG24_WU_CFG_W 2 -#define IOC_IOCFG24_WU_CFG_M 0x18000000 -#define IOC_IOCFG24_WU_CFG_S 27 +#define IOC_IOCFG24_WU_CFG_W 2 +#define IOC_IOCFG24_WU_CFG_M 0x18000000 +#define IOC_IOCFG24_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -9017,15 +9017,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG24_IOMODE_W 3 -#define IOC_IOCFG24_IOMODE_M 0x07000000 -#define IOC_IOCFG24_IOMODE_S 24 -#define IOC_IOCFG24_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG24_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG24_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG24_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG24_IOMODE_INV 0x01000000 -#define IOC_IOCFG24_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG24_IOMODE_W 3 +#define IOC_IOCFG24_IOMODE_M 0x07000000 +#define IOC_IOCFG24_IOMODE_S 24 +#define IOC_IOCFG24_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG24_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG24_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG24_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG24_IOMODE_INV 0x01000000 +#define IOC_IOCFG24_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -9033,10 +9033,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG24_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG24_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG24_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG24_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG24_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG24_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG24_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG24_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -9044,10 +9044,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG24_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG24_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG24_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG24_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG24_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG24_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG24_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG24_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -9055,20 +9055,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG24_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG24_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG24_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG24_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG24_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG24_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG24_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG24_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG24_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG24_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG24_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG24_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG24_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG24_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG24_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG24_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -9078,13 +9078,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG24_EDGE_DET_W 2 -#define IOC_IOCFG24_EDGE_DET_M 0x00030000 -#define IOC_IOCFG24_EDGE_DET_S 16 -#define IOC_IOCFG24_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG24_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG24_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG24_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG24_EDGE_DET_W 2 +#define IOC_IOCFG24_EDGE_DET_M 0x00030000 +#define IOC_IOCFG24_EDGE_DET_S 16 +#define IOC_IOCFG24_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG24_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG24_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG24_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -9093,21 +9093,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG24_PULL_CTL_W 2 -#define IOC_IOCFG24_PULL_CTL_M 0x00006000 -#define IOC_IOCFG24_PULL_CTL_S 13 -#define IOC_IOCFG24_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG24_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG24_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG24_PULL_CTL_W 2 +#define IOC_IOCFG24_PULL_CTL_M 0x00006000 +#define IOC_IOCFG24_PULL_CTL_S 13 +#define IOC_IOCFG24_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG24_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG24_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG24_SLEW_RED 0x00001000 -#define IOC_IOCFG24_SLEW_RED_BITN 12 -#define IOC_IOCFG24_SLEW_RED_M 0x00001000 -#define IOC_IOCFG24_SLEW_RED_S 12 +#define IOC_IOCFG24_SLEW_RED 0x00001000 +#define IOC_IOCFG24_SLEW_RED_BITN 12 +#define IOC_IOCFG24_SLEW_RED_M 0x00001000 +#define IOC_IOCFG24_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -9120,12 +9120,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG24_IOCURR_W 2 -#define IOC_IOCFG24_IOCURR_M 0x00000C00 -#define IOC_IOCFG24_IOCURR_S 10 -#define IOC_IOCFG24_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG24_IOCURR_4MA 0x00000400 -#define IOC_IOCFG24_IOCURR_2MA 0x00000000 +#define IOC_IOCFG24_IOCURR_W 2 +#define IOC_IOCFG24_IOCURR_M 0x00000C00 +#define IOC_IOCFG24_IOCURR_S 10 +#define IOC_IOCFG24_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG24_IOCURR_4MA 0x00000400 +#define IOC_IOCFG24_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -9144,13 +9144,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG24_IOSTR_W 2 -#define IOC_IOCFG24_IOSTR_M 0x00000300 -#define IOC_IOCFG24_IOSTR_S 8 -#define IOC_IOCFG24_IOSTR_MAX 0x00000300 -#define IOC_IOCFG24_IOSTR_MED 0x00000200 -#define IOC_IOCFG24_IOSTR_MIN 0x00000100 -#define IOC_IOCFG24_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG24_IOSTR_W 2 +#define IOC_IOCFG24_IOSTR_M 0x00000300 +#define IOC_IOCFG24_IOSTR_S 8 +#define IOC_IOCFG24_IOSTR_MAX 0x00000300 +#define IOC_IOCFG24_IOSTR_MED 0x00000200 +#define IOC_IOCFG24_IOSTR_MIN 0x00000100 +#define IOC_IOCFG24_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -9158,10 +9158,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG24_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG24_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG24_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG24_IOEV_RTC_EN_S 7 +#define IOC_IOCFG24_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG24_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG24_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG24_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -9169,10 +9169,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG24_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG24_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG24_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG24_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG24_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG24_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG24_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG24_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -9264,55 +9264,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG24_PORT_ID_W 6 -#define IOC_IOCFG24_PORT_ID_M 0x0000003F -#define IOC_IOCFG24_PORT_ID_S 0 -#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG24_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG24_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG24_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG24_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG24_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG24_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG24_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG24_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG24_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG24_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG24_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG24_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG24_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG24_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG24_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG24_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG24_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG24_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG24_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG24_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG24_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG24_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG24_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG24_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG24_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG24_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG24_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG24_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG24_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG24_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG24_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG24_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG24_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG24_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG24_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG24_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG24_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG24_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG24_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG24_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG24_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG24_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG24_PORT_ID_W 6 +#define IOC_IOCFG24_PORT_ID_M 0x0000003F +#define IOC_IOCFG24_PORT_ID_S 0 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG24_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG24_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG24_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG24_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG24_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG24_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG24_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG24_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG24_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG24_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG24_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG24_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG24_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG24_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG24_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG24_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG24_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG24_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG24_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG24_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG24_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG24_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG24_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG24_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG24_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG24_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG24_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG24_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG24_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG24_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG24_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG24_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG24_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG24_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG24_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG24_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG24_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG24_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG24_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -9323,10 +9323,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG25_HYST_EN 0x40000000 -#define IOC_IOCFG25_HYST_EN_BITN 30 -#define IOC_IOCFG25_HYST_EN_M 0x40000000 -#define IOC_IOCFG25_HYST_EN_S 30 +#define IOC_IOCFG25_HYST_EN 0x40000000 +#define IOC_IOCFG25_HYST_EN_BITN 30 +#define IOC_IOCFG25_HYST_EN_M 0x40000000 +#define IOC_IOCFG25_HYST_EN_S 30 // Field: [29] IE // @@ -9335,10 +9335,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG25_IE 0x20000000 -#define IOC_IOCFG25_IE_BITN 29 -#define IOC_IOCFG25_IE_M 0x20000000 -#define IOC_IOCFG25_IE_S 29 +#define IOC_IOCFG25_IE 0x20000000 +#define IOC_IOCFG25_IE_BITN 29 +#define IOC_IOCFG25_IE_M 0x20000000 +#define IOC_IOCFG25_IE_S 29 // Field: [28:27] WU_CFG // @@ -9360,9 +9360,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG25_WU_CFG_W 2 -#define IOC_IOCFG25_WU_CFG_M 0x18000000 -#define IOC_IOCFG25_WU_CFG_S 27 +#define IOC_IOCFG25_WU_CFG_W 2 +#define IOC_IOCFG25_WU_CFG_M 0x18000000 +#define IOC_IOCFG25_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -9384,15 +9384,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG25_IOMODE_W 3 -#define IOC_IOCFG25_IOMODE_M 0x07000000 -#define IOC_IOCFG25_IOMODE_S 24 -#define IOC_IOCFG25_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG25_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG25_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG25_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG25_IOMODE_INV 0x01000000 -#define IOC_IOCFG25_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG25_IOMODE_W 3 +#define IOC_IOCFG25_IOMODE_M 0x07000000 +#define IOC_IOCFG25_IOMODE_S 24 +#define IOC_IOCFG25_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG25_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG25_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG25_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG25_IOMODE_INV 0x01000000 +#define IOC_IOCFG25_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -9400,10 +9400,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG25_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG25_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG25_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG25_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG25_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG25_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG25_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG25_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -9411,10 +9411,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG25_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG25_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG25_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG25_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG25_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG25_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG25_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG25_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -9422,20 +9422,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG25_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG25_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG25_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG25_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG25_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG25_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG25_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG25_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG25_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG25_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG25_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG25_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG25_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG25_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG25_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG25_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -9445,13 +9445,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG25_EDGE_DET_W 2 -#define IOC_IOCFG25_EDGE_DET_M 0x00030000 -#define IOC_IOCFG25_EDGE_DET_S 16 -#define IOC_IOCFG25_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG25_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG25_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG25_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG25_EDGE_DET_W 2 +#define IOC_IOCFG25_EDGE_DET_M 0x00030000 +#define IOC_IOCFG25_EDGE_DET_S 16 +#define IOC_IOCFG25_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG25_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG25_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG25_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -9460,21 +9460,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG25_PULL_CTL_W 2 -#define IOC_IOCFG25_PULL_CTL_M 0x00006000 -#define IOC_IOCFG25_PULL_CTL_S 13 -#define IOC_IOCFG25_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG25_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG25_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG25_PULL_CTL_W 2 +#define IOC_IOCFG25_PULL_CTL_M 0x00006000 +#define IOC_IOCFG25_PULL_CTL_S 13 +#define IOC_IOCFG25_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG25_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG25_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG25_SLEW_RED 0x00001000 -#define IOC_IOCFG25_SLEW_RED_BITN 12 -#define IOC_IOCFG25_SLEW_RED_M 0x00001000 -#define IOC_IOCFG25_SLEW_RED_S 12 +#define IOC_IOCFG25_SLEW_RED 0x00001000 +#define IOC_IOCFG25_SLEW_RED_BITN 12 +#define IOC_IOCFG25_SLEW_RED_M 0x00001000 +#define IOC_IOCFG25_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -9487,12 +9487,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG25_IOCURR_W 2 -#define IOC_IOCFG25_IOCURR_M 0x00000C00 -#define IOC_IOCFG25_IOCURR_S 10 -#define IOC_IOCFG25_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG25_IOCURR_4MA 0x00000400 -#define IOC_IOCFG25_IOCURR_2MA 0x00000000 +#define IOC_IOCFG25_IOCURR_W 2 +#define IOC_IOCFG25_IOCURR_M 0x00000C00 +#define IOC_IOCFG25_IOCURR_S 10 +#define IOC_IOCFG25_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG25_IOCURR_4MA 0x00000400 +#define IOC_IOCFG25_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -9511,13 +9511,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG25_IOSTR_W 2 -#define IOC_IOCFG25_IOSTR_M 0x00000300 -#define IOC_IOCFG25_IOSTR_S 8 -#define IOC_IOCFG25_IOSTR_MAX 0x00000300 -#define IOC_IOCFG25_IOSTR_MED 0x00000200 -#define IOC_IOCFG25_IOSTR_MIN 0x00000100 -#define IOC_IOCFG25_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG25_IOSTR_W 2 +#define IOC_IOCFG25_IOSTR_M 0x00000300 +#define IOC_IOCFG25_IOSTR_S 8 +#define IOC_IOCFG25_IOSTR_MAX 0x00000300 +#define IOC_IOCFG25_IOSTR_MED 0x00000200 +#define IOC_IOCFG25_IOSTR_MIN 0x00000100 +#define IOC_IOCFG25_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -9525,10 +9525,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG25_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG25_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG25_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG25_IOEV_RTC_EN_S 7 +#define IOC_IOCFG25_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG25_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG25_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG25_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -9536,10 +9536,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG25_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG25_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG25_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG25_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG25_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG25_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG25_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG25_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -9631,55 +9631,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG25_PORT_ID_W 6 -#define IOC_IOCFG25_PORT_ID_M 0x0000003F -#define IOC_IOCFG25_PORT_ID_S 0 -#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG25_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG25_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG25_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG25_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG25_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG25_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG25_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG25_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG25_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG25_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG25_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG25_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG25_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG25_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG25_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG25_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG25_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG25_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG25_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG25_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG25_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG25_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG25_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG25_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG25_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG25_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG25_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG25_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG25_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG25_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG25_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG25_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG25_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG25_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG25_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG25_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG25_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG25_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG25_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG25_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG25_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG25_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG25_PORT_ID_W 6 +#define IOC_IOCFG25_PORT_ID_M 0x0000003F +#define IOC_IOCFG25_PORT_ID_S 0 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG25_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG25_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG25_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG25_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG25_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG25_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG25_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG25_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG25_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG25_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG25_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG25_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG25_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG25_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG25_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG25_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG25_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG25_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG25_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG25_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG25_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG25_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG25_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG25_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG25_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG25_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG25_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG25_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG25_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG25_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG25_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG25_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG25_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG25_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG25_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG25_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG25_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG25_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG25_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -9690,10 +9690,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG26_HYST_EN 0x40000000 -#define IOC_IOCFG26_HYST_EN_BITN 30 -#define IOC_IOCFG26_HYST_EN_M 0x40000000 -#define IOC_IOCFG26_HYST_EN_S 30 +#define IOC_IOCFG26_HYST_EN 0x40000000 +#define IOC_IOCFG26_HYST_EN_BITN 30 +#define IOC_IOCFG26_HYST_EN_M 0x40000000 +#define IOC_IOCFG26_HYST_EN_S 30 // Field: [29] IE // @@ -9702,10 +9702,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG26_IE 0x20000000 -#define IOC_IOCFG26_IE_BITN 29 -#define IOC_IOCFG26_IE_M 0x20000000 -#define IOC_IOCFG26_IE_S 29 +#define IOC_IOCFG26_IE 0x20000000 +#define IOC_IOCFG26_IE_BITN 29 +#define IOC_IOCFG26_IE_M 0x20000000 +#define IOC_IOCFG26_IE_S 29 // Field: [28:27] WU_CFG // @@ -9727,9 +9727,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG26_WU_CFG_W 2 -#define IOC_IOCFG26_WU_CFG_M 0x18000000 -#define IOC_IOCFG26_WU_CFG_S 27 +#define IOC_IOCFG26_WU_CFG_W 2 +#define IOC_IOCFG26_WU_CFG_M 0x18000000 +#define IOC_IOCFG26_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -9751,15 +9751,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG26_IOMODE_W 3 -#define IOC_IOCFG26_IOMODE_M 0x07000000 -#define IOC_IOCFG26_IOMODE_S 24 -#define IOC_IOCFG26_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG26_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG26_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG26_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG26_IOMODE_INV 0x01000000 -#define IOC_IOCFG26_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG26_IOMODE_W 3 +#define IOC_IOCFG26_IOMODE_M 0x07000000 +#define IOC_IOCFG26_IOMODE_S 24 +#define IOC_IOCFG26_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG26_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG26_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG26_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG26_IOMODE_INV 0x01000000 +#define IOC_IOCFG26_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -9767,10 +9767,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG26_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG26_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG26_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG26_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG26_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG26_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG26_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG26_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -9778,10 +9778,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG26_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG26_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG26_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG26_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG26_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG26_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG26_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG26_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -9789,20 +9789,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG26_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG26_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG26_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG26_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG26_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG26_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG26_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG26_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG26_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG26_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG26_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG26_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG26_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG26_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG26_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG26_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -9812,13 +9812,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG26_EDGE_DET_W 2 -#define IOC_IOCFG26_EDGE_DET_M 0x00030000 -#define IOC_IOCFG26_EDGE_DET_S 16 -#define IOC_IOCFG26_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG26_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG26_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG26_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG26_EDGE_DET_W 2 +#define IOC_IOCFG26_EDGE_DET_M 0x00030000 +#define IOC_IOCFG26_EDGE_DET_S 16 +#define IOC_IOCFG26_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG26_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG26_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG26_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -9827,21 +9827,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG26_PULL_CTL_W 2 -#define IOC_IOCFG26_PULL_CTL_M 0x00006000 -#define IOC_IOCFG26_PULL_CTL_S 13 -#define IOC_IOCFG26_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG26_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG26_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG26_PULL_CTL_W 2 +#define IOC_IOCFG26_PULL_CTL_M 0x00006000 +#define IOC_IOCFG26_PULL_CTL_S 13 +#define IOC_IOCFG26_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG26_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG26_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG26_SLEW_RED 0x00001000 -#define IOC_IOCFG26_SLEW_RED_BITN 12 -#define IOC_IOCFG26_SLEW_RED_M 0x00001000 -#define IOC_IOCFG26_SLEW_RED_S 12 +#define IOC_IOCFG26_SLEW_RED 0x00001000 +#define IOC_IOCFG26_SLEW_RED_BITN 12 +#define IOC_IOCFG26_SLEW_RED_M 0x00001000 +#define IOC_IOCFG26_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -9854,12 +9854,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG26_IOCURR_W 2 -#define IOC_IOCFG26_IOCURR_M 0x00000C00 -#define IOC_IOCFG26_IOCURR_S 10 -#define IOC_IOCFG26_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG26_IOCURR_4MA 0x00000400 -#define IOC_IOCFG26_IOCURR_2MA 0x00000000 +#define IOC_IOCFG26_IOCURR_W 2 +#define IOC_IOCFG26_IOCURR_M 0x00000C00 +#define IOC_IOCFG26_IOCURR_S 10 +#define IOC_IOCFG26_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG26_IOCURR_4MA 0x00000400 +#define IOC_IOCFG26_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -9878,13 +9878,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG26_IOSTR_W 2 -#define IOC_IOCFG26_IOSTR_M 0x00000300 -#define IOC_IOCFG26_IOSTR_S 8 -#define IOC_IOCFG26_IOSTR_MAX 0x00000300 -#define IOC_IOCFG26_IOSTR_MED 0x00000200 -#define IOC_IOCFG26_IOSTR_MIN 0x00000100 -#define IOC_IOCFG26_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG26_IOSTR_W 2 +#define IOC_IOCFG26_IOSTR_M 0x00000300 +#define IOC_IOCFG26_IOSTR_S 8 +#define IOC_IOCFG26_IOSTR_MAX 0x00000300 +#define IOC_IOCFG26_IOSTR_MED 0x00000200 +#define IOC_IOCFG26_IOSTR_MIN 0x00000100 +#define IOC_IOCFG26_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -9892,10 +9892,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG26_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG26_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG26_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG26_IOEV_RTC_EN_S 7 +#define IOC_IOCFG26_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG26_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG26_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG26_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -9903,10 +9903,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG26_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG26_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG26_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG26_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG26_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG26_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG26_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG26_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -9998,55 +9998,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG26_PORT_ID_W 6 -#define IOC_IOCFG26_PORT_ID_M 0x0000003F -#define IOC_IOCFG26_PORT_ID_S 0 -#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG26_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG26_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG26_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG26_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG26_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG26_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG26_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG26_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG26_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG26_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG26_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG26_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG26_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG26_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG26_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG26_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG26_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG26_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG26_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG26_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG26_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG26_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG26_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG26_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG26_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG26_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG26_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG26_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG26_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG26_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG26_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG26_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG26_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG26_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG26_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG26_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG26_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG26_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG26_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG26_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG26_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG26_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG26_PORT_ID_W 6 +#define IOC_IOCFG26_PORT_ID_M 0x0000003F +#define IOC_IOCFG26_PORT_ID_S 0 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG26_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG26_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG26_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG26_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG26_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG26_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG26_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG26_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG26_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG26_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG26_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG26_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG26_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG26_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG26_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG26_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG26_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG26_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG26_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG26_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG26_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG26_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG26_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG26_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG26_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG26_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG26_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG26_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG26_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG26_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG26_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG26_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG26_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG26_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG26_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG26_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG26_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG26_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG26_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -10057,10 +10057,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG27_HYST_EN 0x40000000 -#define IOC_IOCFG27_HYST_EN_BITN 30 -#define IOC_IOCFG27_HYST_EN_M 0x40000000 -#define IOC_IOCFG27_HYST_EN_S 30 +#define IOC_IOCFG27_HYST_EN 0x40000000 +#define IOC_IOCFG27_HYST_EN_BITN 30 +#define IOC_IOCFG27_HYST_EN_M 0x40000000 +#define IOC_IOCFG27_HYST_EN_S 30 // Field: [29] IE // @@ -10069,10 +10069,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG27_IE 0x20000000 -#define IOC_IOCFG27_IE_BITN 29 -#define IOC_IOCFG27_IE_M 0x20000000 -#define IOC_IOCFG27_IE_S 29 +#define IOC_IOCFG27_IE 0x20000000 +#define IOC_IOCFG27_IE_BITN 29 +#define IOC_IOCFG27_IE_M 0x20000000 +#define IOC_IOCFG27_IE_S 29 // Field: [28:27] WU_CFG // @@ -10094,9 +10094,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG27_WU_CFG_W 2 -#define IOC_IOCFG27_WU_CFG_M 0x18000000 -#define IOC_IOCFG27_WU_CFG_S 27 +#define IOC_IOCFG27_WU_CFG_W 2 +#define IOC_IOCFG27_WU_CFG_M 0x18000000 +#define IOC_IOCFG27_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -10118,15 +10118,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG27_IOMODE_W 3 -#define IOC_IOCFG27_IOMODE_M 0x07000000 -#define IOC_IOCFG27_IOMODE_S 24 -#define IOC_IOCFG27_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG27_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG27_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG27_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG27_IOMODE_INV 0x01000000 -#define IOC_IOCFG27_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG27_IOMODE_W 3 +#define IOC_IOCFG27_IOMODE_M 0x07000000 +#define IOC_IOCFG27_IOMODE_S 24 +#define IOC_IOCFG27_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG27_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG27_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG27_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG27_IOMODE_INV 0x01000000 +#define IOC_IOCFG27_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -10134,10 +10134,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG27_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG27_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG27_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG27_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG27_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG27_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG27_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG27_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -10145,10 +10145,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG27_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG27_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG27_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG27_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG27_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG27_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG27_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG27_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -10156,20 +10156,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG27_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG27_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG27_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG27_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG27_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG27_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG27_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG27_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG27_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG27_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG27_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG27_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG27_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG27_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG27_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG27_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -10179,13 +10179,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG27_EDGE_DET_W 2 -#define IOC_IOCFG27_EDGE_DET_M 0x00030000 -#define IOC_IOCFG27_EDGE_DET_S 16 -#define IOC_IOCFG27_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG27_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG27_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG27_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG27_EDGE_DET_W 2 +#define IOC_IOCFG27_EDGE_DET_M 0x00030000 +#define IOC_IOCFG27_EDGE_DET_S 16 +#define IOC_IOCFG27_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG27_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG27_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG27_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -10194,21 +10194,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG27_PULL_CTL_W 2 -#define IOC_IOCFG27_PULL_CTL_M 0x00006000 -#define IOC_IOCFG27_PULL_CTL_S 13 -#define IOC_IOCFG27_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG27_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG27_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG27_PULL_CTL_W 2 +#define IOC_IOCFG27_PULL_CTL_M 0x00006000 +#define IOC_IOCFG27_PULL_CTL_S 13 +#define IOC_IOCFG27_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG27_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG27_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG27_SLEW_RED 0x00001000 -#define IOC_IOCFG27_SLEW_RED_BITN 12 -#define IOC_IOCFG27_SLEW_RED_M 0x00001000 -#define IOC_IOCFG27_SLEW_RED_S 12 +#define IOC_IOCFG27_SLEW_RED 0x00001000 +#define IOC_IOCFG27_SLEW_RED_BITN 12 +#define IOC_IOCFG27_SLEW_RED_M 0x00001000 +#define IOC_IOCFG27_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -10221,12 +10221,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG27_IOCURR_W 2 -#define IOC_IOCFG27_IOCURR_M 0x00000C00 -#define IOC_IOCFG27_IOCURR_S 10 -#define IOC_IOCFG27_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG27_IOCURR_4MA 0x00000400 -#define IOC_IOCFG27_IOCURR_2MA 0x00000000 +#define IOC_IOCFG27_IOCURR_W 2 +#define IOC_IOCFG27_IOCURR_M 0x00000C00 +#define IOC_IOCFG27_IOCURR_S 10 +#define IOC_IOCFG27_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG27_IOCURR_4MA 0x00000400 +#define IOC_IOCFG27_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -10245,13 +10245,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG27_IOSTR_W 2 -#define IOC_IOCFG27_IOSTR_M 0x00000300 -#define IOC_IOCFG27_IOSTR_S 8 -#define IOC_IOCFG27_IOSTR_MAX 0x00000300 -#define IOC_IOCFG27_IOSTR_MED 0x00000200 -#define IOC_IOCFG27_IOSTR_MIN 0x00000100 -#define IOC_IOCFG27_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG27_IOSTR_W 2 +#define IOC_IOCFG27_IOSTR_M 0x00000300 +#define IOC_IOCFG27_IOSTR_S 8 +#define IOC_IOCFG27_IOSTR_MAX 0x00000300 +#define IOC_IOCFG27_IOSTR_MED 0x00000200 +#define IOC_IOCFG27_IOSTR_MIN 0x00000100 +#define IOC_IOCFG27_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -10259,10 +10259,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG27_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG27_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG27_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG27_IOEV_RTC_EN_S 7 +#define IOC_IOCFG27_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG27_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG27_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG27_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -10270,10 +10270,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG27_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG27_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG27_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG27_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG27_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG27_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG27_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG27_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -10365,55 +10365,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG27_PORT_ID_W 6 -#define IOC_IOCFG27_PORT_ID_M 0x0000003F -#define IOC_IOCFG27_PORT_ID_S 0 -#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG27_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG27_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG27_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG27_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG27_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG27_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG27_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG27_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG27_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG27_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG27_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG27_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG27_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG27_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG27_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG27_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG27_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG27_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG27_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG27_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG27_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG27_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG27_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG27_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG27_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG27_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG27_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG27_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG27_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG27_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG27_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG27_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG27_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG27_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG27_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG27_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG27_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG27_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG27_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG27_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG27_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG27_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG27_PORT_ID_W 6 +#define IOC_IOCFG27_PORT_ID_M 0x0000003F +#define IOC_IOCFG27_PORT_ID_S 0 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG27_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG27_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG27_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG27_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG27_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG27_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG27_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG27_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG27_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG27_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG27_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG27_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG27_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG27_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG27_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG27_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG27_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG27_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG27_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG27_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG27_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG27_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG27_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG27_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG27_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG27_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG27_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG27_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG27_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG27_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG27_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG27_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG27_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG27_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG27_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG27_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG27_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG27_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG27_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -10424,10 +10424,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG28_HYST_EN 0x40000000 -#define IOC_IOCFG28_HYST_EN_BITN 30 -#define IOC_IOCFG28_HYST_EN_M 0x40000000 -#define IOC_IOCFG28_HYST_EN_S 30 +#define IOC_IOCFG28_HYST_EN 0x40000000 +#define IOC_IOCFG28_HYST_EN_BITN 30 +#define IOC_IOCFG28_HYST_EN_M 0x40000000 +#define IOC_IOCFG28_HYST_EN_S 30 // Field: [29] IE // @@ -10436,10 +10436,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG28_IE 0x20000000 -#define IOC_IOCFG28_IE_BITN 29 -#define IOC_IOCFG28_IE_M 0x20000000 -#define IOC_IOCFG28_IE_S 29 +#define IOC_IOCFG28_IE 0x20000000 +#define IOC_IOCFG28_IE_BITN 29 +#define IOC_IOCFG28_IE_M 0x20000000 +#define IOC_IOCFG28_IE_S 29 // Field: [28:27] WU_CFG // @@ -10461,9 +10461,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG28_WU_CFG_W 2 -#define IOC_IOCFG28_WU_CFG_M 0x18000000 -#define IOC_IOCFG28_WU_CFG_S 27 +#define IOC_IOCFG28_WU_CFG_W 2 +#define IOC_IOCFG28_WU_CFG_M 0x18000000 +#define IOC_IOCFG28_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -10485,15 +10485,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG28_IOMODE_W 3 -#define IOC_IOCFG28_IOMODE_M 0x07000000 -#define IOC_IOCFG28_IOMODE_S 24 -#define IOC_IOCFG28_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG28_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG28_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG28_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG28_IOMODE_INV 0x01000000 -#define IOC_IOCFG28_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG28_IOMODE_W 3 +#define IOC_IOCFG28_IOMODE_M 0x07000000 +#define IOC_IOCFG28_IOMODE_S 24 +#define IOC_IOCFG28_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG28_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG28_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG28_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG28_IOMODE_INV 0x01000000 +#define IOC_IOCFG28_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -10501,10 +10501,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG28_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG28_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG28_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG28_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG28_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG28_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG28_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG28_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -10512,10 +10512,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG28_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG28_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG28_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG28_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG28_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG28_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG28_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG28_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -10523,20 +10523,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG28_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG28_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG28_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG28_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG28_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG28_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG28_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG28_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG28_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG28_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG28_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG28_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG28_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG28_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG28_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG28_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -10546,13 +10546,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG28_EDGE_DET_W 2 -#define IOC_IOCFG28_EDGE_DET_M 0x00030000 -#define IOC_IOCFG28_EDGE_DET_S 16 -#define IOC_IOCFG28_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG28_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG28_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG28_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG28_EDGE_DET_W 2 +#define IOC_IOCFG28_EDGE_DET_M 0x00030000 +#define IOC_IOCFG28_EDGE_DET_S 16 +#define IOC_IOCFG28_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG28_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG28_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG28_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -10561,21 +10561,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG28_PULL_CTL_W 2 -#define IOC_IOCFG28_PULL_CTL_M 0x00006000 -#define IOC_IOCFG28_PULL_CTL_S 13 -#define IOC_IOCFG28_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG28_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG28_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG28_PULL_CTL_W 2 +#define IOC_IOCFG28_PULL_CTL_M 0x00006000 +#define IOC_IOCFG28_PULL_CTL_S 13 +#define IOC_IOCFG28_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG28_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG28_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG28_SLEW_RED 0x00001000 -#define IOC_IOCFG28_SLEW_RED_BITN 12 -#define IOC_IOCFG28_SLEW_RED_M 0x00001000 -#define IOC_IOCFG28_SLEW_RED_S 12 +#define IOC_IOCFG28_SLEW_RED 0x00001000 +#define IOC_IOCFG28_SLEW_RED_BITN 12 +#define IOC_IOCFG28_SLEW_RED_M 0x00001000 +#define IOC_IOCFG28_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -10588,12 +10588,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG28_IOCURR_W 2 -#define IOC_IOCFG28_IOCURR_M 0x00000C00 -#define IOC_IOCFG28_IOCURR_S 10 -#define IOC_IOCFG28_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG28_IOCURR_4MA 0x00000400 -#define IOC_IOCFG28_IOCURR_2MA 0x00000000 +#define IOC_IOCFG28_IOCURR_W 2 +#define IOC_IOCFG28_IOCURR_M 0x00000C00 +#define IOC_IOCFG28_IOCURR_S 10 +#define IOC_IOCFG28_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG28_IOCURR_4MA 0x00000400 +#define IOC_IOCFG28_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -10612,13 +10612,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG28_IOSTR_W 2 -#define IOC_IOCFG28_IOSTR_M 0x00000300 -#define IOC_IOCFG28_IOSTR_S 8 -#define IOC_IOCFG28_IOSTR_MAX 0x00000300 -#define IOC_IOCFG28_IOSTR_MED 0x00000200 -#define IOC_IOCFG28_IOSTR_MIN 0x00000100 -#define IOC_IOCFG28_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG28_IOSTR_W 2 +#define IOC_IOCFG28_IOSTR_M 0x00000300 +#define IOC_IOCFG28_IOSTR_S 8 +#define IOC_IOCFG28_IOSTR_MAX 0x00000300 +#define IOC_IOCFG28_IOSTR_MED 0x00000200 +#define IOC_IOCFG28_IOSTR_MIN 0x00000100 +#define IOC_IOCFG28_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -10626,10 +10626,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG28_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG28_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG28_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG28_IOEV_RTC_EN_S 7 +#define IOC_IOCFG28_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG28_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG28_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG28_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -10637,10 +10637,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG28_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG28_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG28_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG28_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG28_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG28_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG28_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG28_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -10732,55 +10732,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG28_PORT_ID_W 6 -#define IOC_IOCFG28_PORT_ID_M 0x0000003F -#define IOC_IOCFG28_PORT_ID_S 0 -#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG28_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG28_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG28_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG28_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG28_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG28_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG28_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG28_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG28_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG28_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG28_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG28_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG28_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG28_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG28_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG28_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG28_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG28_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG28_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG28_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG28_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG28_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG28_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG28_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG28_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG28_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG28_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG28_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG28_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG28_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG28_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG28_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG28_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG28_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG28_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG28_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG28_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG28_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG28_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG28_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG28_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG28_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG28_PORT_ID_W 6 +#define IOC_IOCFG28_PORT_ID_M 0x0000003F +#define IOC_IOCFG28_PORT_ID_S 0 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG28_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG28_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG28_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG28_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG28_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG28_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG28_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG28_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG28_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG28_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG28_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG28_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG28_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG28_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG28_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG28_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG28_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG28_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG28_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG28_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG28_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG28_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG28_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG28_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG28_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG28_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG28_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG28_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG28_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG28_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG28_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG28_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG28_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG28_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG28_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG28_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG28_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG28_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG28_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -10791,10 +10791,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG29_HYST_EN 0x40000000 -#define IOC_IOCFG29_HYST_EN_BITN 30 -#define IOC_IOCFG29_HYST_EN_M 0x40000000 -#define IOC_IOCFG29_HYST_EN_S 30 +#define IOC_IOCFG29_HYST_EN 0x40000000 +#define IOC_IOCFG29_HYST_EN_BITN 30 +#define IOC_IOCFG29_HYST_EN_M 0x40000000 +#define IOC_IOCFG29_HYST_EN_S 30 // Field: [29] IE // @@ -10803,10 +10803,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG29_IE 0x20000000 -#define IOC_IOCFG29_IE_BITN 29 -#define IOC_IOCFG29_IE_M 0x20000000 -#define IOC_IOCFG29_IE_S 29 +#define IOC_IOCFG29_IE 0x20000000 +#define IOC_IOCFG29_IE_BITN 29 +#define IOC_IOCFG29_IE_M 0x20000000 +#define IOC_IOCFG29_IE_S 29 // Field: [28:27] WU_CFG // @@ -10828,9 +10828,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG29_WU_CFG_W 2 -#define IOC_IOCFG29_WU_CFG_M 0x18000000 -#define IOC_IOCFG29_WU_CFG_S 27 +#define IOC_IOCFG29_WU_CFG_W 2 +#define IOC_IOCFG29_WU_CFG_M 0x18000000 +#define IOC_IOCFG29_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -10852,15 +10852,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG29_IOMODE_W 3 -#define IOC_IOCFG29_IOMODE_M 0x07000000 -#define IOC_IOCFG29_IOMODE_S 24 -#define IOC_IOCFG29_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG29_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG29_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG29_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG29_IOMODE_INV 0x01000000 -#define IOC_IOCFG29_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG29_IOMODE_W 3 +#define IOC_IOCFG29_IOMODE_M 0x07000000 +#define IOC_IOCFG29_IOMODE_S 24 +#define IOC_IOCFG29_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG29_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG29_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG29_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG29_IOMODE_INV 0x01000000 +#define IOC_IOCFG29_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -10868,10 +10868,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG29_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG29_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG29_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG29_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG29_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG29_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG29_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG29_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -10879,10 +10879,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG29_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG29_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG29_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG29_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG29_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG29_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG29_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG29_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -10890,20 +10890,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG29_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG29_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG29_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG29_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG29_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG29_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG29_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG29_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG29_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG29_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG29_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG29_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG29_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG29_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG29_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG29_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -10913,13 +10913,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG29_EDGE_DET_W 2 -#define IOC_IOCFG29_EDGE_DET_M 0x00030000 -#define IOC_IOCFG29_EDGE_DET_S 16 -#define IOC_IOCFG29_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG29_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG29_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG29_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG29_EDGE_DET_W 2 +#define IOC_IOCFG29_EDGE_DET_M 0x00030000 +#define IOC_IOCFG29_EDGE_DET_S 16 +#define IOC_IOCFG29_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG29_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG29_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG29_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -10928,21 +10928,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG29_PULL_CTL_W 2 -#define IOC_IOCFG29_PULL_CTL_M 0x00006000 -#define IOC_IOCFG29_PULL_CTL_S 13 -#define IOC_IOCFG29_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG29_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG29_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG29_PULL_CTL_W 2 +#define IOC_IOCFG29_PULL_CTL_M 0x00006000 +#define IOC_IOCFG29_PULL_CTL_S 13 +#define IOC_IOCFG29_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG29_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG29_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG29_SLEW_RED 0x00001000 -#define IOC_IOCFG29_SLEW_RED_BITN 12 -#define IOC_IOCFG29_SLEW_RED_M 0x00001000 -#define IOC_IOCFG29_SLEW_RED_S 12 +#define IOC_IOCFG29_SLEW_RED 0x00001000 +#define IOC_IOCFG29_SLEW_RED_BITN 12 +#define IOC_IOCFG29_SLEW_RED_M 0x00001000 +#define IOC_IOCFG29_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -10955,12 +10955,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG29_IOCURR_W 2 -#define IOC_IOCFG29_IOCURR_M 0x00000C00 -#define IOC_IOCFG29_IOCURR_S 10 -#define IOC_IOCFG29_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG29_IOCURR_4MA 0x00000400 -#define IOC_IOCFG29_IOCURR_2MA 0x00000000 +#define IOC_IOCFG29_IOCURR_W 2 +#define IOC_IOCFG29_IOCURR_M 0x00000C00 +#define IOC_IOCFG29_IOCURR_S 10 +#define IOC_IOCFG29_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG29_IOCURR_4MA 0x00000400 +#define IOC_IOCFG29_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -10979,13 +10979,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG29_IOSTR_W 2 -#define IOC_IOCFG29_IOSTR_M 0x00000300 -#define IOC_IOCFG29_IOSTR_S 8 -#define IOC_IOCFG29_IOSTR_MAX 0x00000300 -#define IOC_IOCFG29_IOSTR_MED 0x00000200 -#define IOC_IOCFG29_IOSTR_MIN 0x00000100 -#define IOC_IOCFG29_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG29_IOSTR_W 2 +#define IOC_IOCFG29_IOSTR_M 0x00000300 +#define IOC_IOCFG29_IOSTR_S 8 +#define IOC_IOCFG29_IOSTR_MAX 0x00000300 +#define IOC_IOCFG29_IOSTR_MED 0x00000200 +#define IOC_IOCFG29_IOSTR_MIN 0x00000100 +#define IOC_IOCFG29_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -10993,10 +10993,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG29_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG29_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG29_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG29_IOEV_RTC_EN_S 7 +#define IOC_IOCFG29_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG29_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG29_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG29_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -11004,10 +11004,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG29_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG29_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG29_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG29_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG29_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG29_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG29_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG29_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -11099,55 +11099,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG29_PORT_ID_W 6 -#define IOC_IOCFG29_PORT_ID_M 0x0000003F -#define IOC_IOCFG29_PORT_ID_S 0 -#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG29_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG29_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG29_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG29_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG29_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG29_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG29_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG29_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG29_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG29_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG29_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG29_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG29_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG29_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG29_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG29_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG29_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG29_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG29_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG29_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG29_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG29_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG29_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG29_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG29_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG29_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG29_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG29_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG29_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG29_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG29_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG29_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG29_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG29_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG29_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG29_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG29_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG29_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG29_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG29_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG29_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG29_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG29_PORT_ID_W 6 +#define IOC_IOCFG29_PORT_ID_M 0x0000003F +#define IOC_IOCFG29_PORT_ID_S 0 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG29_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG29_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG29_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG29_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG29_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG29_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG29_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG29_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG29_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG29_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG29_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG29_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG29_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG29_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG29_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG29_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG29_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG29_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG29_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG29_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG29_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG29_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG29_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG29_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG29_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG29_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG29_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG29_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG29_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG29_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG29_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG29_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG29_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG29_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG29_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG29_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG29_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG29_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG29_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -11158,10 +11158,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG30_HYST_EN 0x40000000 -#define IOC_IOCFG30_HYST_EN_BITN 30 -#define IOC_IOCFG30_HYST_EN_M 0x40000000 -#define IOC_IOCFG30_HYST_EN_S 30 +#define IOC_IOCFG30_HYST_EN 0x40000000 +#define IOC_IOCFG30_HYST_EN_BITN 30 +#define IOC_IOCFG30_HYST_EN_M 0x40000000 +#define IOC_IOCFG30_HYST_EN_S 30 // Field: [29] IE // @@ -11170,10 +11170,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG30_IE 0x20000000 -#define IOC_IOCFG30_IE_BITN 29 -#define IOC_IOCFG30_IE_M 0x20000000 -#define IOC_IOCFG30_IE_S 29 +#define IOC_IOCFG30_IE 0x20000000 +#define IOC_IOCFG30_IE_BITN 29 +#define IOC_IOCFG30_IE_M 0x20000000 +#define IOC_IOCFG30_IE_S 29 // Field: [28:27] WU_CFG // @@ -11195,9 +11195,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG30_WU_CFG_W 2 -#define IOC_IOCFG30_WU_CFG_M 0x18000000 -#define IOC_IOCFG30_WU_CFG_S 27 +#define IOC_IOCFG30_WU_CFG_W 2 +#define IOC_IOCFG30_WU_CFG_M 0x18000000 +#define IOC_IOCFG30_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -11219,15 +11219,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG30_IOMODE_W 3 -#define IOC_IOCFG30_IOMODE_M 0x07000000 -#define IOC_IOCFG30_IOMODE_S 24 -#define IOC_IOCFG30_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG30_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG30_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG30_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG30_IOMODE_INV 0x01000000 -#define IOC_IOCFG30_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG30_IOMODE_W 3 +#define IOC_IOCFG30_IOMODE_M 0x07000000 +#define IOC_IOCFG30_IOMODE_S 24 +#define IOC_IOCFG30_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG30_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG30_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG30_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG30_IOMODE_INV 0x01000000 +#define IOC_IOCFG30_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -11235,10 +11235,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG30_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG30_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG30_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG30_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG30_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG30_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG30_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG30_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -11246,10 +11246,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG30_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG30_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG30_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG30_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG30_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG30_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG30_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG30_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -11257,20 +11257,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG30_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG30_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG30_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG30_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG30_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG30_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG30_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG30_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG30_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG30_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG30_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG30_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG30_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG30_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG30_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG30_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -11280,13 +11280,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG30_EDGE_DET_W 2 -#define IOC_IOCFG30_EDGE_DET_M 0x00030000 -#define IOC_IOCFG30_EDGE_DET_S 16 -#define IOC_IOCFG30_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG30_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG30_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG30_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG30_EDGE_DET_W 2 +#define IOC_IOCFG30_EDGE_DET_M 0x00030000 +#define IOC_IOCFG30_EDGE_DET_S 16 +#define IOC_IOCFG30_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG30_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG30_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG30_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -11295,21 +11295,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG30_PULL_CTL_W 2 -#define IOC_IOCFG30_PULL_CTL_M 0x00006000 -#define IOC_IOCFG30_PULL_CTL_S 13 -#define IOC_IOCFG30_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG30_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG30_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG30_PULL_CTL_W 2 +#define IOC_IOCFG30_PULL_CTL_M 0x00006000 +#define IOC_IOCFG30_PULL_CTL_S 13 +#define IOC_IOCFG30_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG30_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG30_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG30_SLEW_RED 0x00001000 -#define IOC_IOCFG30_SLEW_RED_BITN 12 -#define IOC_IOCFG30_SLEW_RED_M 0x00001000 -#define IOC_IOCFG30_SLEW_RED_S 12 +#define IOC_IOCFG30_SLEW_RED 0x00001000 +#define IOC_IOCFG30_SLEW_RED_BITN 12 +#define IOC_IOCFG30_SLEW_RED_M 0x00001000 +#define IOC_IOCFG30_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -11322,12 +11322,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG30_IOCURR_W 2 -#define IOC_IOCFG30_IOCURR_M 0x00000C00 -#define IOC_IOCFG30_IOCURR_S 10 -#define IOC_IOCFG30_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG30_IOCURR_4MA 0x00000400 -#define IOC_IOCFG30_IOCURR_2MA 0x00000000 +#define IOC_IOCFG30_IOCURR_W 2 +#define IOC_IOCFG30_IOCURR_M 0x00000C00 +#define IOC_IOCFG30_IOCURR_S 10 +#define IOC_IOCFG30_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG30_IOCURR_4MA 0x00000400 +#define IOC_IOCFG30_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -11346,13 +11346,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG30_IOSTR_W 2 -#define IOC_IOCFG30_IOSTR_M 0x00000300 -#define IOC_IOCFG30_IOSTR_S 8 -#define IOC_IOCFG30_IOSTR_MAX 0x00000300 -#define IOC_IOCFG30_IOSTR_MED 0x00000200 -#define IOC_IOCFG30_IOSTR_MIN 0x00000100 -#define IOC_IOCFG30_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG30_IOSTR_W 2 +#define IOC_IOCFG30_IOSTR_M 0x00000300 +#define IOC_IOCFG30_IOSTR_S 8 +#define IOC_IOCFG30_IOSTR_MAX 0x00000300 +#define IOC_IOCFG30_IOSTR_MED 0x00000200 +#define IOC_IOCFG30_IOSTR_MIN 0x00000100 +#define IOC_IOCFG30_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -11360,10 +11360,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG30_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG30_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG30_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG30_IOEV_RTC_EN_S 7 +#define IOC_IOCFG30_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG30_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG30_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG30_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -11371,10 +11371,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG30_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG30_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG30_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG30_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG30_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG30_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG30_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG30_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -11466,55 +11466,55 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG30_PORT_ID_W 6 -#define IOC_IOCFG30_PORT_ID_M 0x0000003F -#define IOC_IOCFG30_PORT_ID_S 0 -#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG30_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG30_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG30_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG30_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG30_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG30_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG30_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG30_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG30_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG30_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG30_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG30_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG30_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG30_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG30_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG30_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG30_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG30_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG30_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG30_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG30_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG30_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG30_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG30_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG30_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG30_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG30_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG30_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG30_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG30_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG30_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG30_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG30_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG30_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG30_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG30_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG30_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG30_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG30_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG30_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG30_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG30_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG30_PORT_ID_W 6 +#define IOC_IOCFG30_PORT_ID_M 0x0000003F +#define IOC_IOCFG30_PORT_ID_S 0 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG30_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG30_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG30_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG30_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG30_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG30_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG30_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG30_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG30_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG30_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG30_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG30_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG30_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG30_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG30_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG30_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG30_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG30_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG30_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG30_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG30_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG30_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG30_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG30_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG30_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG30_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG30_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG30_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG30_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG30_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG30_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG30_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG30_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG30_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG30_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG30_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG30_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG30_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG30_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -11525,10 +11525,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG31_HYST_EN 0x40000000 -#define IOC_IOCFG31_HYST_EN_BITN 30 -#define IOC_IOCFG31_HYST_EN_M 0x40000000 -#define IOC_IOCFG31_HYST_EN_S 30 +#define IOC_IOCFG31_HYST_EN 0x40000000 +#define IOC_IOCFG31_HYST_EN_BITN 30 +#define IOC_IOCFG31_HYST_EN_M 0x40000000 +#define IOC_IOCFG31_HYST_EN_S 30 // Field: [29] IE // @@ -11537,10 +11537,10 @@ // // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG31_IE 0x20000000 -#define IOC_IOCFG31_IE_BITN 29 -#define IOC_IOCFG31_IE_M 0x20000000 -#define IOC_IOCFG31_IE_S 29 +#define IOC_IOCFG31_IE 0x20000000 +#define IOC_IOCFG31_IE_BITN 29 +#define IOC_IOCFG31_IE_M 0x20000000 +#define IOC_IOCFG31_IE_S 29 // Field: [28:27] WU_CFG // @@ -11562,9 +11562,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG31_WU_CFG_W 2 -#define IOC_IOCFG31_WU_CFG_M 0x18000000 -#define IOC_IOCFG31_WU_CFG_S 27 +#define IOC_IOCFG31_WU_CFG_W 2 +#define IOC_IOCFG31_WU_CFG_M 0x18000000 +#define IOC_IOCFG31_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -11586,15 +11586,15 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG31_IOMODE_W 3 -#define IOC_IOCFG31_IOMODE_M 0x07000000 -#define IOC_IOCFG31_IOMODE_S 24 -#define IOC_IOCFG31_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG31_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG31_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG31_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG31_IOMODE_INV 0x01000000 -#define IOC_IOCFG31_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG31_IOMODE_W 3 +#define IOC_IOCFG31_IOMODE_M 0x07000000 +#define IOC_IOCFG31_IOMODE_S 24 +#define IOC_IOCFG31_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG31_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG31_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG31_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG31_IOMODE_INV 0x01000000 +#define IOC_IOCFG31_IOMODE_NORMAL 0x00000000 // Field: [23] IOEV_AON_PROG2_EN // @@ -11602,10 +11602,10 @@ // // 0: Input edge detection does not assert AON_PROG2 event // 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG31_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG31_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG31_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG31_IOEV_AON_PROG2_EN_S 23 +#define IOC_IOCFG31_IOEV_AON_PROG2_EN 0x00800000 +#define IOC_IOCFG31_IOEV_AON_PROG2_EN_BITN 23 +#define IOC_IOCFG31_IOEV_AON_PROG2_EN_M 0x00800000 +#define IOC_IOCFG31_IOEV_AON_PROG2_EN_S 23 // Field: [22] IOEV_AON_PROG1_EN // @@ -11613,10 +11613,10 @@ // // 0: Input edge detection does not assert AON_PROG1 event // 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG31_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG31_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG31_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG31_IOEV_AON_PROG1_EN_S 22 +#define IOC_IOCFG31_IOEV_AON_PROG1_EN 0x00400000 +#define IOC_IOCFG31_IOEV_AON_PROG1_EN_BITN 22 +#define IOC_IOCFG31_IOEV_AON_PROG1_EN_M 0x00400000 +#define IOC_IOCFG31_IOEV_AON_PROG1_EN_S 22 // Field: [21] IOEV_AON_PROG0_EN // @@ -11624,20 +11624,20 @@ // // 0: Input edge detection does not assert AON_PROG0 event // 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG31_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG31_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG31_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG31_IOEV_AON_PROG0_EN_S 21 +#define IOC_IOCFG31_IOEV_AON_PROG0_EN 0x00200000 +#define IOC_IOCFG31_IOEV_AON_PROG0_EN_BITN 21 +#define IOC_IOCFG31_IOEV_AON_PROG0_EN_M 0x00200000 +#define IOC_IOCFG31_IOEV_AON_PROG0_EN_S 21 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG31_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG31_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG31_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG31_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG31_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG31_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG31_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG31_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -11647,13 +11647,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG31_EDGE_DET_W 2 -#define IOC_IOCFG31_EDGE_DET_M 0x00030000 -#define IOC_IOCFG31_EDGE_DET_S 16 -#define IOC_IOCFG31_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG31_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG31_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG31_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG31_EDGE_DET_W 2 +#define IOC_IOCFG31_EDGE_DET_M 0x00030000 +#define IOC_IOCFG31_EDGE_DET_S 16 +#define IOC_IOCFG31_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG31_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG31_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG31_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -11662,21 +11662,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG31_PULL_CTL_W 2 -#define IOC_IOCFG31_PULL_CTL_M 0x00006000 -#define IOC_IOCFG31_PULL_CTL_S 13 -#define IOC_IOCFG31_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG31_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG31_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG31_PULL_CTL_W 2 +#define IOC_IOCFG31_PULL_CTL_M 0x00006000 +#define IOC_IOCFG31_PULL_CTL_S 13 +#define IOC_IOCFG31_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG31_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG31_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG31_SLEW_RED 0x00001000 -#define IOC_IOCFG31_SLEW_RED_BITN 12 -#define IOC_IOCFG31_SLEW_RED_M 0x00001000 -#define IOC_IOCFG31_SLEW_RED_S 12 +#define IOC_IOCFG31_SLEW_RED 0x00001000 +#define IOC_IOCFG31_SLEW_RED_BITN 12 +#define IOC_IOCFG31_SLEW_RED_M 0x00001000 +#define IOC_IOCFG31_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -11689,12 +11689,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG31_IOCURR_W 2 -#define IOC_IOCFG31_IOCURR_M 0x00000C00 -#define IOC_IOCFG31_IOCURR_S 10 -#define IOC_IOCFG31_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG31_IOCURR_4MA 0x00000400 -#define IOC_IOCFG31_IOCURR_2MA 0x00000000 +#define IOC_IOCFG31_IOCURR_W 2 +#define IOC_IOCFG31_IOCURR_M 0x00000C00 +#define IOC_IOCFG31_IOCURR_S 10 +#define IOC_IOCFG31_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG31_IOCURR_4MA 0x00000400 +#define IOC_IOCFG31_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -11713,13 +11713,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG31_IOSTR_W 2 -#define IOC_IOCFG31_IOSTR_M 0x00000300 -#define IOC_IOCFG31_IOSTR_S 8 -#define IOC_IOCFG31_IOSTR_MAX 0x00000300 -#define IOC_IOCFG31_IOSTR_MED 0x00000200 -#define IOC_IOCFG31_IOSTR_MIN 0x00000100 -#define IOC_IOCFG31_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG31_IOSTR_W 2 +#define IOC_IOCFG31_IOSTR_M 0x00000300 +#define IOC_IOCFG31_IOSTR_S 8 +#define IOC_IOCFG31_IOSTR_MAX 0x00000300 +#define IOC_IOCFG31_IOSTR_MED 0x00000200 +#define IOC_IOCFG31_IOSTR_MIN 0x00000100 +#define IOC_IOCFG31_IOSTR_AUTO 0x00000000 // Field: [7] IOEV_RTC_EN // @@ -11727,10 +11727,10 @@ // // 0: Input edge detection does not assert RTC event // 1: Input edge detection asserts RTC event -#define IOC_IOCFG31_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG31_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG31_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG31_IOEV_RTC_EN_S 7 +#define IOC_IOCFG31_IOEV_RTC_EN 0x00000080 +#define IOC_IOCFG31_IOEV_RTC_EN_BITN 7 +#define IOC_IOCFG31_IOEV_RTC_EN_M 0x00000080 +#define IOC_IOCFG31_IOEV_RTC_EN_S 7 // Field: [6] IOEV_MCU_WU_EN // @@ -11738,10 +11738,10 @@ // // 0: Input edge detection does not assert MCU_WU event // 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG31_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG31_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG31_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG31_IOEV_MCU_WU_EN_S 6 +#define IOC_IOCFG31_IOEV_MCU_WU_EN 0x00000040 +#define IOC_IOCFG31_IOEV_MCU_WU_EN_BITN 6 +#define IOC_IOCFG31_IOEV_MCU_WU_EN_M 0x00000040 +#define IOC_IOCFG31_IOEV_MCU_WU_EN_S 6 // Field: [5:0] PORT_ID // @@ -11833,55 +11833,54 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG31_PORT_ID_W 6 -#define IOC_IOCFG31_PORT_ID_M 0x0000003F -#define IOC_IOCFG31_PORT_ID_S 0 -#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG31_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG31_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG31_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG31_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG31_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG31_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG31_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG31_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG31_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG31_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG31_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG31_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG31_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG31_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG31_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG31_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG31_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG31_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG31_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG31_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG31_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG31_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG31_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG31_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG31_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG31_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG31_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG31_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG31_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG31_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG31_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG31_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG31_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG31_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG31_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG31_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG31_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG31_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG31_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG31_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG31_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG31_PORT_ID_GPIO 0x00000000 - +#define IOC_IOCFG31_PORT_ID_W 6 +#define IOC_IOCFG31_PORT_ID_M 0x0000003F +#define IOC_IOCFG31_PORT_ID_S 0 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG31_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG31_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG31_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG31_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG31_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG31_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG31_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG31_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG31_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG31_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG31_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG31_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG31_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG31_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG31_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG31_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG31_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG31_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG31_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG31_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG31_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG31_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG31_PORT_ID_UART1_RTS 0x00000016 +#define IOC_IOCFG31_PORT_ID_UART1_CTS 0x00000015 +#define IOC_IOCFG31_PORT_ID_UART1_TX 0x00000014 +#define IOC_IOCFG31_PORT_ID_UART1_RX 0x00000013 +#define IOC_IOCFG31_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG31_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG31_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG31_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG31_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG31_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG31_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG31_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG31_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG31_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG31_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG31_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG31_PORT_ID_GPIO 0x00000000 #endif // __IOC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_memmap.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_memmap.h index 2f93631..44f8a4a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_memmap.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_memmap.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_memmap_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_memmap_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_MEMMAP_H__ #define __HW_MEMMAP_H__ @@ -43,121 +43,121 @@ // peripherals on the CPU_MMAP interface // //***************************************************************************** -#define FLASHMEM_BASE 0x00000000 // FLASHMEM -#define BROM_BASE 0x10000000 // BROM -#define GPRAM_BASE 0x11000000 // GPRAM -#define SRAM_BASE 0x20000000 // SRAM -#define RFC_RAM_BASE 0x21000000 // RFC_RAM -#define RFC_ULLRAM_BASE 0x21004000 // RFC_ULLRAM -#define SSI0_BASE 0x40000000 // SSI -#define UART0_BASE 0x40001000 // UART -#define I2C0_BASE 0x40002000 // I2C -#define SSI1_BASE 0x40008000 // SSI -#define UART1_BASE 0x4000B000 // UART -#define GPT0_BASE 0x40010000 // GPT -#define GPT1_BASE 0x40011000 // GPT -#define GPT2_BASE 0x40012000 // GPT -#define GPT3_BASE 0x40013000 // GPT -#define UDMA0_BASE 0x40020000 // UDMA -#define I2S0_BASE 0x40021000 // I2S -#define GPIO_BASE 0x40022000 // GPIO -#define CRYPTO_BASE 0x40024000 // CRYPTO -#define PKA_BASE 0x40025000 // PKA -#define PKA_RAM_BASE 0x40026000 // PKA_RAM -#define PKA_INT_BASE 0x40027000 // PKA_INT -#define TRNG_BASE 0x40028000 // TRNG -#define FLASH_BASE 0x40030000 // FLASH -#define VIMS_BASE 0x40034000 // VIMS -#define SRAM_MMR_BASE 0x40035000 // SRAM_MMR -#define RFC_PWR_BASE 0x40040000 // RFC_PWR -#define RFC_DBELL_BASE 0x40041000 // RFC_DBELL -#define RFC_RAT_BASE 0x40043000 // RFC_RAT -#define RFC_FSCA_BASE 0x40044000 // RFC_FSCA -#define WDT_BASE 0x40080000 // WDT -#define IOC_BASE 0x40081000 // IOC -#define PRCM_BASE 0x40082000 // PRCM -#define EVENT_BASE 0x40083000 // EVENT -#define SMPH_BASE 0x40084000 // SMPH -#define ADI2_BASE 0x40086000 // ADI -#define ADI3_BASE 0x40086200 // ADI -#define AON_PMCTL_BASE 0x40090000 // AON_PMCTL -#define AON_RTC_BASE 0x40092000 // AON_RTC -#define AON_EVENT_BASE 0x40093000 // AON_EVENT -#define AON_IOC_BASE 0x40094000 // AON_IOC -#define AON_BATMON_BASE 0x40095000 // AON_BATMON -#define AUX_SPIM_BASE 0x400C1000 // AUX_SPIM -#define AUX_MAC_BASE 0x400C2000 // AUX_MAC -#define AUX_TIMER2_BASE 0x400C3000 // AUX_TIMER2 -#define AUX_TDC_BASE 0x400C4000 // AUX_TDC -#define AUX_EVCTL_BASE 0x400C5000 // AUX_EVCTL -#define AUX_SYSIF_BASE 0x400C6000 // AUX_SYSIF -#define AUX_TIMER01_BASE 0x400C7000 // AUX_TIMER01 -#define AUX_SMPH_BASE 0x400C8000 // AUX_SMPH -#define AUX_ANAIF_BASE 0x400C9000 // AUX_ANAIF -#define AUX_DDI0_OSC_BASE 0x400CA000 // DDI -#define AUX_ADI4_BASE 0x400CB000 // ADI -#define AUX_AIODIO0_BASE 0x400CC000 // AUX_AIODIO -#define AUX_AIODIO1_BASE 0x400CD000 // AUX_AIODIO -#define AUX_AIODIO2_BASE 0x400CE000 // AUX_AIODIO -#define AUX_AIODIO3_BASE 0x400CF000 // AUX_AIODIO -#define AUX_RAM_BASE 0x400E0000 // AUX_RAM -#define AUX_SCE_BASE 0x400E1000 // AUX_SCE -#define FLASH_CFG_BASE 0x50000000 // CC26_DUMMY_COMP -#define FCFG1_BASE 0x50001000 // FCFG1 -#define FCFG2_BASE 0x50002000 // FCFG2 +#define FLASHMEM_BASE 0x00000000 // FLASHMEM +#define BROM_BASE 0x10000000 // BROM +#define GPRAM_BASE 0x11000000 // GPRAM +#define SRAM_BASE 0x20000000 // SRAM +#define RFC_RAM_BASE 0x21000000 // RFC_RAM +#define RFC_ULLRAM_BASE 0x21004000 // RFC_ULLRAM +#define SSI0_BASE 0x40000000 // SSI +#define UART0_BASE 0x40001000 // UART +#define I2C0_BASE 0x40002000 // I2C +#define SSI1_BASE 0x40008000 // SSI +#define UART1_BASE 0x4000B000 // UART +#define GPT0_BASE 0x40010000 // GPT +#define GPT1_BASE 0x40011000 // GPT +#define GPT2_BASE 0x40012000 // GPT +#define GPT3_BASE 0x40013000 // GPT +#define UDMA0_BASE 0x40020000 // UDMA +#define I2S0_BASE 0x40021000 // I2S +#define GPIO_BASE 0x40022000 // GPIO +#define CRYPTO_BASE 0x40024000 // CRYPTO +#define PKA_BASE 0x40025000 // PKA +#define PKA_RAM_BASE 0x40026000 // PKA_RAM +#define PKA_INT_BASE 0x40027000 // PKA_INT +#define TRNG_BASE 0x40028000 // TRNG +#define FLASH_BASE 0x40030000 // FLASH +#define VIMS_BASE 0x40034000 // VIMS +#define SRAM_MMR_BASE 0x40035000 // SRAM_MMR +#define RFC_PWR_BASE 0x40040000 // RFC_PWR +#define RFC_DBELL_BASE 0x40041000 // RFC_DBELL +#define RFC_RAT_BASE 0x40043000 // RFC_RAT +#define RFC_FSCA_BASE 0x40044000 // RFC_FSCA +#define WDT_BASE 0x40080000 // WDT +#define IOC_BASE 0x40081000 // IOC +#define PRCM_BASE 0x40082000 // PRCM +#define EVENT_BASE 0x40083000 // EVENT +#define SMPH_BASE 0x40084000 // SMPH +#define ADI2_BASE 0x40086000 // ADI +#define ADI3_BASE 0x40086200 // ADI +#define AON_PMCTL_BASE 0x40090000 // AON_PMCTL +#define AON_RTC_BASE 0x40092000 // AON_RTC +#define AON_EVENT_BASE 0x40093000 // AON_EVENT +#define AON_IOC_BASE 0x40094000 // AON_IOC +#define AON_BATMON_BASE 0x40095000 // AON_BATMON +#define AUX_SPIM_BASE 0x400C1000 // AUX_SPIM +#define AUX_MAC_BASE 0x400C2000 // AUX_MAC +#define AUX_TIMER2_BASE 0x400C3000 // AUX_TIMER2 +#define AUX_TDC_BASE 0x400C4000 // AUX_TDC +#define AUX_EVCTL_BASE 0x400C5000 // AUX_EVCTL +#define AUX_SYSIF_BASE 0x400C6000 // AUX_SYSIF +#define AUX_TIMER01_BASE 0x400C7000 // AUX_TIMER01 +#define AUX_SMPH_BASE 0x400C8000 // AUX_SMPH +#define AUX_ANAIF_BASE 0x400C9000 // AUX_ANAIF +#define AUX_DDI0_OSC_BASE 0x400CA000 // DDI +#define AUX_ADI4_BASE 0x400CB000 // ADI +#define AUX_AIODIO0_BASE 0x400CC000 // AUX_AIODIO +#define AUX_AIODIO1_BASE 0x400CD000 // AUX_AIODIO +#define AUX_AIODIO2_BASE 0x400CE000 // AUX_AIODIO +#define AUX_AIODIO3_BASE 0x400CF000 // AUX_AIODIO +#define AUX_RAM_BASE 0x400E0000 // AUX_RAM +#define AUX_SCE_BASE 0x400E1000 // AUX_SCE +#define FLASH_CFG_BASE 0x50000000 // CC26_DUMMY_COMP +#define FCFG1_BASE 0x50001000 // FCFG1 +#define FCFG2_BASE 0x50002000 // FCFG2 #ifndef CCFG_BASE - #define CCFG_BASE 0x50003000 // CCFG +#define CCFG_BASE 0x50003000 // CCFG #endif -#define CCFG_BASE_DEFAULT 0x50003000 // CCFG -#define SSI0_NONBUF_BASE 0x60000000 // SSI CPU nonbuf base -#define UART0_NONBUF_BASE 0x60001000 // UART CPU nonbuf base -#define I2C0_NONBUF_BASE 0x60002000 // I2C CPU nonbuf base -#define SSI1_NONBUF_BASE 0x60008000 // SSI CPU nonbuf base -#define UART1_NONBUF_BASE 0x6000B000 // UART CPU nonbuf base -#define GPT0_NONBUF_BASE 0x60010000 // GPT CPU nonbuf base -#define GPT1_NONBUF_BASE 0x60011000 // GPT CPU nonbuf base -#define GPT2_NONBUF_BASE 0x60012000 // GPT CPU nonbuf base -#define GPT3_NONBUF_BASE 0x60013000 // GPT CPU nonbuf base -#define UDMA0_NONBUF_BASE 0x60020000 // UDMA CPU nonbuf base -#define I2S0_NONBUF_BASE 0x60021000 // I2S CPU nonbuf base -#define GPIO_NONBUF_BASE 0x60022000 // GPIO CPU nonbuf base -#define CRYPTO_NONBUF_BASE 0x60024000 // CRYPTO CPU nonbuf base -#define PKA_NONBUF_BASE 0x60025000 // PKA CPU nonbuf base -#define PKA_RAM_NONBUF_BASE 0x60026000 // PKA_RAM CPU nonbuf base -#define PKA_INT_NONBUF_BASE 0x60027000 // PKA_INT CPU nonbuf base -#define TRNG_NONBUF_BASE 0x60028000 // TRNG CPU nonbuf base -#define FLASH_NONBUF_BASE 0x60030000 // FLASH CPU nonbuf base -#define VIMS_NONBUF_BASE 0x60034000 // VIMS CPU nonbuf base -#define SRAM_MMR_NONBUF_BASE 0x60035000 // SRAM_MMR CPU nonbuf base -#define RFC_PWR_NONBUF_BASE 0x60040000 // RFC_PWR CPU nonbuf base -#define RFC_DBELL_NONBUF_BASE 0x60041000 // RFC_DBELL CPU nonbuf base -#define RFC_RAT_NONBUF_BASE 0x60043000 // RFC_RAT CPU nonbuf base -#define RFC_FSCA_NONBUF_BASE 0x60044000 // RFC_FSCA CPU nonbuf base -#define WDT_NONBUF_BASE 0x60080000 // WDT CPU nonbuf base -#define IOC_NONBUF_BASE 0x60081000 // IOC CPU nonbuf base -#define PRCM_NONBUF_BASE 0x60082000 // PRCM CPU nonbuf base -#define EVENT_NONBUF_BASE 0x60083000 // EVENT CPU nonbuf base -#define SMPH_NONBUF_BASE 0x60084000 // SMPH CPU nonbuf base -#define ADI2_NONBUF_BASE 0x60086000 // ADI CPU nonbuf base -#define ADI3_NONBUF_BASE 0x60086200 // ADI CPU nonbuf base -#define AON_PMCTL_NONBUF_BASE 0x60090000 // AON_PMCTL CPU nonbuf base -#define AON_RTC_NONBUF_BASE 0x60092000 // AON_RTC CPU nonbuf base -#define AON_EVENT_NONBUF_BASE 0x60093000 // AON_EVENT CPU nonbuf base -#define AON_IOC_NONBUF_BASE 0x60094000 // AON_IOC CPU nonbuf base -#define AON_BATMON_NONBUF_BASE 0x60095000 // AON_BATMON CPU nonbuf base -#define AUX_SPIM_NONBUF_BASE 0x600C1000 // AUX_SPIM CPU nonbuf base -#define AUX_MAC_NONBUF_BASE 0x600C2000 // AUX_MAC CPU nonbuf base -#define AUX_TIMER2_NONBUF_BASE 0x600C3000 // AUX_TIMER2 CPU nonbuf base -#define AUX_TDC_NONBUF_BASE 0x600C4000 // AUX_TDC CPU nonbuf base -#define AUX_EVCTL_NONBUF_BASE 0x600C5000 // AUX_EVCTL CPU nonbuf base -#define AUX_SYSIF_NONBUF_BASE 0x600C6000 // AUX_SYSIF CPU nonbuf base +#define CCFG_BASE_DEFAULT 0x50003000 // CCFG +#define SSI0_NONBUF_BASE 0x60000000 // SSI CPU nonbuf base +#define UART0_NONBUF_BASE 0x60001000 // UART CPU nonbuf base +#define I2C0_NONBUF_BASE 0x60002000 // I2C CPU nonbuf base +#define SSI1_NONBUF_BASE 0x60008000 // SSI CPU nonbuf base +#define UART1_NONBUF_BASE 0x6000B000 // UART CPU nonbuf base +#define GPT0_NONBUF_BASE 0x60010000 // GPT CPU nonbuf base +#define GPT1_NONBUF_BASE 0x60011000 // GPT CPU nonbuf base +#define GPT2_NONBUF_BASE 0x60012000 // GPT CPU nonbuf base +#define GPT3_NONBUF_BASE 0x60013000 // GPT CPU nonbuf base +#define UDMA0_NONBUF_BASE 0x60020000 // UDMA CPU nonbuf base +#define I2S0_NONBUF_BASE 0x60021000 // I2S CPU nonbuf base +#define GPIO_NONBUF_BASE 0x60022000 // GPIO CPU nonbuf base +#define CRYPTO_NONBUF_BASE 0x60024000 // CRYPTO CPU nonbuf base +#define PKA_NONBUF_BASE 0x60025000 // PKA CPU nonbuf base +#define PKA_RAM_NONBUF_BASE 0x60026000 // PKA_RAM CPU nonbuf base +#define PKA_INT_NONBUF_BASE 0x60027000 // PKA_INT CPU nonbuf base +#define TRNG_NONBUF_BASE 0x60028000 // TRNG CPU nonbuf base +#define FLASH_NONBUF_BASE 0x60030000 // FLASH CPU nonbuf base +#define VIMS_NONBUF_BASE 0x60034000 // VIMS CPU nonbuf base +#define SRAM_MMR_NONBUF_BASE 0x60035000 // SRAM_MMR CPU nonbuf base +#define RFC_PWR_NONBUF_BASE 0x60040000 // RFC_PWR CPU nonbuf base +#define RFC_DBELL_NONBUF_BASE 0x60041000 // RFC_DBELL CPU nonbuf base +#define RFC_RAT_NONBUF_BASE 0x60043000 // RFC_RAT CPU nonbuf base +#define RFC_FSCA_NONBUF_BASE 0x60044000 // RFC_FSCA CPU nonbuf base +#define WDT_NONBUF_BASE 0x60080000 // WDT CPU nonbuf base +#define IOC_NONBUF_BASE 0x60081000 // IOC CPU nonbuf base +#define PRCM_NONBUF_BASE 0x60082000 // PRCM CPU nonbuf base +#define EVENT_NONBUF_BASE 0x60083000 // EVENT CPU nonbuf base +#define SMPH_NONBUF_BASE 0x60084000 // SMPH CPU nonbuf base +#define ADI2_NONBUF_BASE 0x60086000 // ADI CPU nonbuf base +#define ADI3_NONBUF_BASE 0x60086200 // ADI CPU nonbuf base +#define AON_PMCTL_NONBUF_BASE 0x60090000 // AON_PMCTL CPU nonbuf base +#define AON_RTC_NONBUF_BASE 0x60092000 // AON_RTC CPU nonbuf base +#define AON_EVENT_NONBUF_BASE 0x60093000 // AON_EVENT CPU nonbuf base +#define AON_IOC_NONBUF_BASE 0x60094000 // AON_IOC CPU nonbuf base +#define AON_BATMON_NONBUF_BASE 0x60095000 // AON_BATMON CPU nonbuf base +#define AUX_SPIM_NONBUF_BASE 0x600C1000 // AUX_SPIM CPU nonbuf base +#define AUX_MAC_NONBUF_BASE 0x600C2000 // AUX_MAC CPU nonbuf base +#define AUX_TIMER2_NONBUF_BASE 0x600C3000 // AUX_TIMER2 CPU nonbuf base +#define AUX_TDC_NONBUF_BASE 0x600C4000 // AUX_TDC CPU nonbuf base +#define AUX_EVCTL_NONBUF_BASE 0x600C5000 // AUX_EVCTL CPU nonbuf base +#define AUX_SYSIF_NONBUF_BASE 0x600C6000 // AUX_SYSIF CPU nonbuf base #define AUX_TIMER01_NONBUF_BASE \ - 0x600C7000 // AUX_TIMER01 CPU nonbuf base -#define AUX_SMPH_NONBUF_BASE 0x600C8000 // AUX_SMPH CPU nonbuf base -#define AUX_ANAIF_NONBUF_BASE 0x600C9000 // AUX_ANAIF CPU nonbuf base + 0x600C7000 // AUX_TIMER01 CPU nonbuf base +#define AUX_SMPH_NONBUF_BASE 0x600C8000 // AUX_SMPH CPU nonbuf base +#define AUX_ANAIF_NONBUF_BASE 0x600C9000 // AUX_ANAIF CPU nonbuf base #define AUX_DDI0_OSC_NONBUF_BASE \ - 0x600CA000 // DDI CPU nonbuf base -#define AUX_ADI4_NONBUF_BASE 0x600CB000 // ADI CPU nonbuf base + 0x600CA000 // DDI CPU nonbuf base +#define AUX_ADI4_NONBUF_BASE 0x600CB000 // ADI CPU nonbuf base #define AUX_AIODIO0_NONBUF_BASE \ 0x600CC000 // AUX_AIODIO CPU nonbuf base #define AUX_AIODIO1_NONBUF_BASE \ @@ -165,16 +165,16 @@ #define AUX_AIODIO2_NONBUF_BASE \ 0x600CE000 // AUX_AIODIO CPU nonbuf base #define AUX_AIODIO3_NONBUF_BASE \ - 0x600CF000 // AUX_AIODIO CPU nonbuf base -#define AUX_RAM_NONBUF_BASE 0x600E0000 // AUX_RAM CPU nonbuf base -#define AUX_SCE_NONBUF_BASE 0x600E1000 // AUX_SCE CPU nonbuf base -#define FLASHMEM_ALIAS_BASE 0xA0000000 // FLASHMEM Alias base -#define CPU_ITM_BASE 0xE0000000 // CPU_ITM -#define CPU_DWT_BASE 0xE0001000 // CPU_DWT -#define CPU_FPB_BASE 0xE0002000 // CPU_FPB -#define CPU_SCS_BASE 0xE000E000 // CPU_SCS -#define CPU_TPIU_BASE 0xE0040000 // CPU_TPIU -#define CPU_TIPROP_BASE 0xE00FE000 // CPU_TIPROP -#define CPU_ROM_TABLE_BASE 0xE00FF000 // CPU_ROM_TABLE + 0x600CF000 // AUX_AIODIO CPU nonbuf base +#define AUX_RAM_NONBUF_BASE 0x600E0000 // AUX_RAM CPU nonbuf base +#define AUX_SCE_NONBUF_BASE 0x600E1000 // AUX_SCE CPU nonbuf base +#define FLASHMEM_ALIAS_BASE 0xA0000000 // FLASHMEM Alias base +#define CPU_ITM_BASE 0xE0000000 // CPU_ITM +#define CPU_DWT_BASE 0xE0001000 // CPU_DWT +#define CPU_FPB_BASE 0xE0002000 // CPU_FPB +#define CPU_SCS_BASE 0xE000E000 // CPU_SCS +#define CPU_TPIU_BASE 0xE0040000 // CPU_TPIU +#define CPU_TIPROP_BASE 0xE00FE000 // CPU_TIPROP +#define CPU_ROM_TABLE_BASE 0xE00FF000 // CPU_ROM_TABLE #endif // __HW_MEMMAP__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_nvic.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_nvic.h index 6f1f2d0..4ee246d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_nvic.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_nvic.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_nvic.h -* Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) -* Revision: 42365 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_nvic.h + * Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) + * Revision: 42365 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_NVIC_H__ #define __HW_NVIC_H__ @@ -42,89 +42,89 @@ // The following are defines for the NVIC register addresses. // //***************************************************************************** -#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg -#define NVIC_ACTLR 0xE000E008 // Auxiliary Control -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg +#define NVIC_ACTLR 0xE000E008 // Auxiliary Control +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status // Register -#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register -#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register -#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg -#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable -#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable -#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable -#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable -#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending -#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending -#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending -#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending -#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit -#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit -#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority -#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority -#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority -#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority -#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority -#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority -#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority -#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority -#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority -#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority -#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority -#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority -#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority -#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority -#define NVIC_CPUID 0xE000ED00 // CPU ID Base -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset -#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg +#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable +#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable +#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable +#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable +#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending +#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending +#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending +#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending +#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit +#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit +#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority +#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority +#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority +#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority +#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority +#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority +#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority +#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority +#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority +#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority +#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority +#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority +#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority +#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority +#define NVIC_CPUID 0xE000ED00 // CPU ID Base +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset +#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset // Control -#define NVIC_SYS_CTRL 0xE000ED10 // System Control -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control -#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 -#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 -#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 -#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status -#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size -#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 -#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size +#define NVIC_SYS_CTRL 0xE000ED10 // System Control +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control +#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 +#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 +#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size +#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 +#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size // Alias 1 -#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 -#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size +#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 +#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size // Alias 2 -#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 -#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size +#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 +#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size // Alias 3 -#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg -#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select -#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data -#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt //***************************************************************************** // // The following are defines for the bit fields in the NVIC_INT_TYPE register. // //***************************************************************************** -#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) -#define NVIC_INT_TYPE_LINES_S 0 +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_ACTLR register. // //***************************************************************************** -#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding -#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer -#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple // Cycle Instructions //***************************************************************************** @@ -132,18 +132,18 @@ // The following are defines for the bit fields in the NVIC_ST_CTRL register. // //***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable //***************************************************************************** // // The following are defines for the bit fields in the NVIC_ST_RELOAD register. // //***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value -#define NVIC_ST_RELOAD_S 0 +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value +#define NVIC_ST_RELOAD_S 0 //***************************************************************************** // @@ -151,609 +151,609 @@ // register. // //***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value -#define NVIC_ST_CURRENT_S 0 +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value +#define NVIC_ST_CURRENT_S 0 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_ST_CAL register. // //***************************************************************************** -#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock -#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew -#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value -#define NVIC_ST_CAL_ONEMS_S 0 +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_EN0 register. // //***************************************************************************** -#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable -#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable //***************************************************************************** // // The following are defines for the bit fields in the NVIC_EN1 register. // //***************************************************************************** -#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable -#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable -#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable -#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable -#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable -#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable -#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable -#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable -#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable -#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable -#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable -#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable -#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable -#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable -#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable -#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable -#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable -#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable -#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable -#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable -#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable -#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable -#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable -#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable +#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable +#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable +#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable +#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable +#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable +#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable +#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable +#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable +#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable +#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable +#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable +#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable +#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable +#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable +#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable +#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable +#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable +#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable +#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable +#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable +#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable +#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable +#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable +#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable //***************************************************************************** // // The following are defines for the bit fields in the NVIC_DIS0 register. // //***************************************************************************** -#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable -#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable //***************************************************************************** // // The following are defines for the bit fields in the NVIC_DIS1 register. // //***************************************************************************** -#define NVIC_DIS1_INT_M 0x007FFFFF // Interrupt Disable -#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable -#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable -#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable -#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable -#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable -#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable -#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable -#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable -#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable -#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable -#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable -#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable -#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable -#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable -#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable -#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable -#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable -#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable -#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable -#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable -#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable -#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable -#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable +#define NVIC_DIS1_INT_M 0x007FFFFF // Interrupt Disable +#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable +#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable +#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable +#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable +#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable +#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable +#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable +#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable +#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable +#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable +#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable +#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable +#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable +#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable +#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable +#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable +#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable +#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable +#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable +#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable +#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable +#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable +#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PEND0 register. // //***************************************************************************** -#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending -#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PEND1 register. // //***************************************************************************** -#define NVIC_PEND1_INT_M 0x007FFFFF // Interrupt Set Pending -#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend -#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend -#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend -#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend -#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend -#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend -#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend -#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend -#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend -#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend -#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend -#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend -#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend -#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend -#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend -#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend -#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend -#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend -#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend -#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend -#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend -#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend -#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend +#define NVIC_PEND1_INT_M 0x007FFFFF // Interrupt Set Pending +#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend +#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend +#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend +#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend +#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend +#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend +#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend +#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend +#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend +#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend +#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend +#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend +#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend +#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend +#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend +#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend +#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend +#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend +#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend +#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend +#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend +#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend +#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend //***************************************************************************** // // The following are defines for the bit fields in the NVIC_UNPEND0 register. // //***************************************************************************** -#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending -#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend //***************************************************************************** // // The following are defines for the bit fields in the NVIC_UNPEND1 register. // //***************************************************************************** -#define NVIC_UNPEND1_INT_M 0x007FFFFF // Interrupt Clear Pending -#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend -#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend -#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend -#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend -#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend -#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend -#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend -#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend -#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend -#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend -#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend -#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend -#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend -#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend -#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend -#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend -#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend -#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend -#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend -#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend -#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend -#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend -#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend +#define NVIC_UNPEND1_INT_M 0x007FFFFF // Interrupt Clear Pending +#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend +#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend +#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend +#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend +#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend +#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend +#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend +#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend +#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend +#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend +#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend +#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend +#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend +#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend +#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend +#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend +#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend +#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend +#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend +#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend +#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend +#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend +#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend //***************************************************************************** // // The following are defines for the bit fields in the NVIC_ACTIVE0 register. // //***************************************************************************** -#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active -#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active //***************************************************************************** // // The following are defines for the bit fields in the NVIC_ACTIVE1 register. // //***************************************************************************** -#define NVIC_ACTIVE1_INT_M 0x007FFFFF // Interrupt Active -#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active -#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active -#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active -#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active -#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active -#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active -#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active -#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active -#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active -#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active -#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active -#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active -#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active -#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active -#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active -#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active -#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active -#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active -#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active -#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active -#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active -#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active -#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active +#define NVIC_ACTIVE1_INT_M 0x007FFFFF // Interrupt Active +#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active +#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active +#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active +#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active +#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active +#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active +#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active +#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active +#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active +#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active +#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active +#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active +#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active +#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active +#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active +#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active +#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active +#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active +#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active +#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active +#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active +#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active +#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI0 register. // //***************************************************************************** -#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask -#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask -#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask -#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask -#define NVIC_PRI0_INT3_S 29 -#define NVIC_PRI0_INT2_S 21 -#define NVIC_PRI0_INT1_S 13 -#define NVIC_PRI0_INT0_S 5 +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI1 register. // //***************************************************************************** -#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask -#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask -#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask -#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask -#define NVIC_PRI1_INT7_S 29 -#define NVIC_PRI1_INT6_S 21 -#define NVIC_PRI1_INT5_S 13 -#define NVIC_PRI1_INT4_S 5 +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI2 register. // //***************************************************************************** -#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask -#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask -#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask -#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask -#define NVIC_PRI2_INT11_S 29 -#define NVIC_PRI2_INT10_S 21 -#define NVIC_PRI2_INT9_S 13 -#define NVIC_PRI2_INT8_S 5 +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI3 register. // //***************************************************************************** -#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask -#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask -#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask -#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask -#define NVIC_PRI3_INT15_S 29 -#define NVIC_PRI3_INT14_S 21 -#define NVIC_PRI3_INT13_S 13 -#define NVIC_PRI3_INT12_S 5 +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI4 register. // //***************************************************************************** -#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask -#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask -#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask -#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask -#define NVIC_PRI4_INT19_S 29 -#define NVIC_PRI4_INT18_S 21 -#define NVIC_PRI4_INT17_S 13 -#define NVIC_PRI4_INT16_S 5 +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI5 register. // //***************************************************************************** -#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask -#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask -#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask -#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask -#define NVIC_PRI5_INT23_S 29 -#define NVIC_PRI5_INT22_S 21 -#define NVIC_PRI5_INT21_S 13 -#define NVIC_PRI5_INT20_S 5 +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI6 register. // //***************************************************************************** -#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask -#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask -#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask -#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask -#define NVIC_PRI6_INT27_S 29 -#define NVIC_PRI6_INT26_S 21 -#define NVIC_PRI6_INT25_S 13 -#define NVIC_PRI6_INT24_S 5 +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI7 register. // //***************************************************************************** -#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask -#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask -#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask -#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask -#define NVIC_PRI7_INT31_S 29 -#define NVIC_PRI7_INT30_S 21 -#define NVIC_PRI7_INT29_S 13 -#define NVIC_PRI7_INT28_S 5 +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI8 register. // //***************************************************************************** -#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask -#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask -#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask -#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask -#define NVIC_PRI8_INT35_S 29 -#define NVIC_PRI8_INT34_S 21 -#define NVIC_PRI8_INT33_S 13 -#define NVIC_PRI8_INT32_S 5 +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI9 register. // //***************************************************************************** -#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask -#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask -#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask -#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask -#define NVIC_PRI9_INT39_S 29 -#define NVIC_PRI9_INT38_S 21 -#define NVIC_PRI9_INT37_S 13 -#define NVIC_PRI9_INT36_S 5 +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI10 register. // //***************************************************************************** -#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask -#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask -#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask -#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask -#define NVIC_PRI10_INT43_S 29 -#define NVIC_PRI10_INT42_S 21 -#define NVIC_PRI10_INT41_S 13 -#define NVIC_PRI10_INT40_S 5 +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI11 register. // //***************************************************************************** -#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask -#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask -#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask -#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask -#define NVIC_PRI11_INT47_S 29 -#define NVIC_PRI11_INT46_S 21 -#define NVIC_PRI11_INT45_S 13 -#define NVIC_PRI11_INT44_S 5 +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI12 register. // //***************************************************************************** -#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask -#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask -#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask -#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask -#define NVIC_PRI12_INT51_S 29 -#define NVIC_PRI12_INT50_S 21 -#define NVIC_PRI12_INT49_S 13 -#define NVIC_PRI12_INT48_S 5 +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI13 register. // //***************************************************************************** -#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask -#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask -#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask -#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask -#define NVIC_PRI13_INT55_S 29 -#define NVIC_PRI13_INT54_S 21 -#define NVIC_PRI13_INT53_S 13 -#define NVIC_PRI13_INT52_S 5 +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_CPUID register. // //***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code -#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number -#define NVIC_CPUID_CON_M 0x000F0000 // Constant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number -#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor -#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor -#define NVIC_CPUID_REV_M 0x0000000F // Revision Number +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number //***************************************************************************** // // The following are defines for the bit fields in the NVIC_INT_CTRL register. // //***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending -#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending -#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number #undef NVIC_INT_CTRL_VEC_PEN_M -#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number #define NVIC_INT_CTRL_VEC_PEN_NMI \ - 0x00002000 // NMI + 0x00002000 // NMI #define NVIC_INT_CTRL_VEC_PEN_HARD \ - 0x00003000 // Hard fault + 0x00003000 // Hard fault #define NVIC_INT_CTRL_VEC_PEN_MEM \ - 0x00004000 // Memory management fault + 0x00004000 // Memory management fault #define NVIC_INT_CTRL_VEC_PEN_BUS \ - 0x00005000 // Bus fault + 0x00005000 // Bus fault #define NVIC_INT_CTRL_VEC_PEN_USG \ - 0x00006000 // Usage fault + 0x00006000 // Usage fault #define NVIC_INT_CTRL_VEC_PEN_SVC \ - 0x0000B000 // SVCall + 0x0000B000 // SVCall #define NVIC_INT_CTRL_VEC_PEN_PNDSV \ - 0x0000E000 // PendSV + 0x0000E000 // PendSV #define NVIC_INT_CTRL_VEC_PEN_TICK \ - 0x0000F000 // SysTick -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base -#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number #undef NVIC_INT_CTRL_VEC_ACT_M -#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number #define NVIC_INT_CTRL_VEC_PEN_S 12 #define NVIC_INT_CTRL_VEC_ACT_S 0 @@ -762,89 +762,89 @@ // The following are defines for the bit fields in the NVIC_VTABLE register. // //***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset +#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset #undef NVIC_VTABLE_OFFSET_M -#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset -#define NVIC_VTABLE_OFFSET_S 9 +#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset +#define NVIC_VTABLE_OFFSET_S 9 #undef NVIC_VTABLE_OFFSET_S -#define NVIC_VTABLE_OFFSET_S 10 +#define NVIC_VTABLE_OFFSET_S 10 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_APINT register. // //***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault -#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset //***************************************************************************** // // The following are defines for the bit fields in the NVIC_SYS_CTRL register. // //***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit //***************************************************************************** // // The following are defines for the bit fields in the NVIC_CFG_CTRL register. // //***************************************************************************** -#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception // Entry -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and // Fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control //***************************************************************************** // // The following are defines for the bit fields in the NVIC_SYS_PRI1 register. // //***************************************************************************** -#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority -#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority -#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority -#define NVIC_SYS_PRI1_USAGE_S 21 -#define NVIC_SYS_PRI1_BUS_S 13 -#define NVIC_SYS_PRI1_MEM_S 5 +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_SYS_PRI2 register. // //***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority -#define NVIC_SYS_PRI2_SVC_S 29 +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_SYS_PRI3 register. // //***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority -#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority -#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority -#define NVIC_SYS_PRI3_TICK_S 29 -#define NVIC_SYS_PRI3_PENDSV_S 21 -#define NVIC_SYS_PRI3_DEBUG_S 5 +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 //***************************************************************************** // @@ -852,21 +852,21 @@ // register. // //***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending -#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending #define NVIC_SYS_HND_CTRL_USAGEP \ - 0x00001000 // Usage Fault Pending -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active //***************************************************************************** // @@ -874,30 +874,30 @@ // register. // //***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage // Fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid -#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy // State Preservation -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error -#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address // Register Valid -#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on // Floating-Point Lazy State // Preservation -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation //***************************************************************************** // @@ -905,9 +905,9 @@ // register. // //***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault //***************************************************************************** // @@ -915,19 +915,19 @@ // register. // //***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request //***************************************************************************** // // The following are defines for the bit fields in the NVIC_MM_ADDR register. // //***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_MM_ADDR_S 0 +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_MM_ADDR_S 0 //***************************************************************************** // @@ -935,92 +935,92 @@ // register. // //***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_FAULT_ADDR_S 0 +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_FAULT_ADDR_S 0 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_DBG_CTRL register. // //***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key #define NVIC_DBG_CTRL_S_RESET_ST \ - 0x02000000 // Core has reset since last read + 0x02000000 // Core has reset since last read #define NVIC_DBG_CTRL_S_RETIRE_ST \ - 0x01000000 // Core has executed insruction + 0x01000000 // Core has executed insruction // since last read -#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up -#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available #define NVIC_DBG_CTRL_C_SNAPSTALL \ - 0x00000020 // Breaks a stalled load/store -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug //***************************************************************************** // // The following are defines for the bit fields in the NVIC_DBG_XFER register. // //***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask //***************************************************************************** // // The following are defines for the bit fields in the NVIC_DBG_DATA register. // //***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_DBG_INT register. // //***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch //***************************************************************************** // // The following are defines for the bit fields in the NVIC_SW_TRIG register. // //***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID -#define NVIC_SW_TRIG_INTID_S 0 +#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID +#define NVIC_SW_TRIG_INTID_S 0 #endif // __HW_NVIC_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_pka.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_pka.h index ffe4e40..923c5f4 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_pka.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_pka.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_pka_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_pka_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_PKA_H__ #define __HW_PKA_H__ @@ -44,49 +44,49 @@ // //***************************************************************************** // PKA Vector A Address -#define PKA_O_APTR 0x00000000 +#define PKA_O_APTR 0x00000000 // PKA Vector B Address -#define PKA_O_BPTR 0x00000004 +#define PKA_O_BPTR 0x00000004 // PKA Vector C Address -#define PKA_O_CPTR 0x00000008 +#define PKA_O_CPTR 0x00000008 // PKA Vector D Address -#define PKA_O_DPTR 0x0000000C +#define PKA_O_DPTR 0x0000000C // PKA Vector A Length -#define PKA_O_ALENGTH 0x00000010 +#define PKA_O_ALENGTH 0x00000010 // PKA Vector B Length -#define PKA_O_BLENGTH 0x00000014 +#define PKA_O_BLENGTH 0x00000014 // PKA Bit Shift Value -#define PKA_O_SHIFT 0x00000018 +#define PKA_O_SHIFT 0x00000018 // PKA Function -#define PKA_O_FUNCTION 0x0000001C +#define PKA_O_FUNCTION 0x0000001C // PKA compare result -#define PKA_O_COMPARE 0x00000020 +#define PKA_O_COMPARE 0x00000020 // PKA most-significant-word of result vector -#define PKA_O_MSW 0x00000024 +#define PKA_O_MSW 0x00000024 // PKA most-significant-word of divide remainder -#define PKA_O_DIVMSW 0x00000028 +#define PKA_O_DIVMSW 0x00000028 // PKA sequencer control and status register -#define PKA_O_SEQCTRL 0x000000C8 +#define PKA_O_SEQCTRL 0x000000C8 // PKA hardware options register -#define PKA_O_OPTIONS 0x000000F4 +#define PKA_O_OPTIONS 0x000000F4 // PKA firmware revision and capabilities register -#define PKA_O_FWREV 0x000000F8 +#define PKA_O_FWREV 0x000000F8 // PKA hardware revision register -#define PKA_O_HWREV 0x000000FC +#define PKA_O_HWREV 0x000000FC //***************************************************************************** // @@ -99,9 +99,9 @@ // are identified through the location of their least-significant 32-bit word. // Note that bit [0] must be zero to ensure that the vector starts at an 8-byte // boundary. -#define PKA_APTR_APTR_W 11 -#define PKA_APTR_APTR_M 0x000007FF -#define PKA_APTR_APTR_S 0 +#define PKA_APTR_APTR_W 11 +#define PKA_APTR_APTR_M 0x000007FF +#define PKA_APTR_APTR_S 0 //***************************************************************************** // @@ -114,9 +114,9 @@ // are identified through the location of their least-significant 32-bit word. // Note that bit [0] must be zero to ensure that the vector starts at an 8-byte // boundary. -#define PKA_BPTR_BPTR_W 11 -#define PKA_BPTR_BPTR_M 0x000007FF -#define PKA_BPTR_BPTR_S 0 +#define PKA_BPTR_BPTR_W 11 +#define PKA_BPTR_BPTR_M 0x000007FF +#define PKA_BPTR_BPTR_S 0 //***************************************************************************** // @@ -129,9 +129,9 @@ // are identified through the location of their least-significant 32-bit word. // Note that bit [0] must be zero to ensure that the vector starts at an 8-byte // boundary. -#define PKA_CPTR_CPTR_W 11 -#define PKA_CPTR_CPTR_M 0x000007FF -#define PKA_CPTR_CPTR_S 0 +#define PKA_CPTR_CPTR_W 11 +#define PKA_CPTR_CPTR_M 0x000007FF +#define PKA_CPTR_CPTR_S 0 //***************************************************************************** // @@ -144,9 +144,9 @@ // are identified through the location of their least-significant 32-bit word. // Note that bit [0] must be zero to ensure that the vector starts at an 8-byte // boundary. -#define PKA_DPTR_DPTR_W 11 -#define PKA_DPTR_DPTR_M 0x000007FF -#define PKA_DPTR_DPTR_S 0 +#define PKA_DPTR_DPTR_W 11 +#define PKA_DPTR_DPTR_M 0x000007FF +#define PKA_DPTR_DPTR_S 0 //***************************************************************************** // @@ -156,9 +156,9 @@ // Field: [8:0] ALENGTH // // This register specifies the length (in 32-bit words) of Vector A. -#define PKA_ALENGTH_ALENGTH_W 9 -#define PKA_ALENGTH_ALENGTH_M 0x000001FF -#define PKA_ALENGTH_ALENGTH_S 0 +#define PKA_ALENGTH_ALENGTH_W 9 +#define PKA_ALENGTH_ALENGTH_M 0x000001FF +#define PKA_ALENGTH_ALENGTH_S 0 //***************************************************************************** // @@ -168,9 +168,9 @@ // Field: [8:0] BLENGTH // // This register specifies the length (in 32-bit words) of Vector B. -#define PKA_BLENGTH_BLENGTH_W 9 -#define PKA_BLENGTH_BLENGTH_M 0x000001FF -#define PKA_BLENGTH_BLENGTH_S 0 +#define PKA_BLENGTH_BLENGTH_W 9 +#define PKA_BLENGTH_BLENGTH_M 0x000001FF +#define PKA_BLENGTH_BLENGTH_S 0 //***************************************************************************** // @@ -181,9 +181,9 @@ // // This register specifies the number of bits to shift the input vector (in the // range 0-31) during a Rshift or Lshift operation. -#define PKA_SHIFT_NUM_BITS_TO_SHIFT_W 5 -#define PKA_SHIFT_NUM_BITS_TO_SHIFT_M 0x0000001F -#define PKA_SHIFT_NUM_BITS_TO_SHIFT_S 0 +#define PKA_SHIFT_NUM_BITS_TO_SHIFT_W 5 +#define PKA_SHIFT_NUM_BITS_TO_SHIFT_M 0x0000001F +#define PKA_SHIFT_NUM_BITS_TO_SHIFT_S 0 //***************************************************************************** // @@ -200,10 +200,10 @@ // waiting, the result registers is updated and the run bit is reset in the // clock cycle following writing the stall result bit back to 0b. The Stall // result function may only be used for basic PKCP operations. -#define PKA_FUNCTION_STALL_RESULT 0x01000000 -#define PKA_FUNCTION_STALL_RESULT_BITN 24 -#define PKA_FUNCTION_STALL_RESULT_M 0x01000000 -#define PKA_FUNCTION_STALL_RESULT_S 24 +#define PKA_FUNCTION_STALL_RESULT 0x01000000 +#define PKA_FUNCTION_STALL_RESULT_BITN 24 +#define PKA_FUNCTION_STALL_RESULT_M 0x01000000 +#define PKA_FUNCTION_STALL_RESULT_S 24 // Field: [15] RUN // @@ -221,10 +221,10 @@ // execute the FW. The first instruction clears the run bit. // In both cases a few clock cycles are needed before the first instruction is // executed and the run bit state has been propagated. -#define PKA_FUNCTION_RUN 0x00008000 -#define PKA_FUNCTION_RUN_BITN 15 -#define PKA_FUNCTION_RUN_M 0x00008000 -#define PKA_FUNCTION_RUN_S 15 +#define PKA_FUNCTION_RUN 0x00008000 +#define PKA_FUNCTION_RUN_BITN 15 +#define PKA_FUNCTION_RUN_M 0x00008000 +#define PKA_FUNCTION_RUN_S 15 // Field: [14:12] SEQUENCER_OPERATIONS // @@ -238,73 +238,73 @@ // 0x6: ExpMod-variable // 0x7: ModInv (if available in firmware, otherwise reserved) // The encoding of these operations is determined by sequencer firmware. -#define PKA_FUNCTION_SEQUENCER_OPERATIONS_W 3 -#define PKA_FUNCTION_SEQUENCER_OPERATIONS_M 0x00007000 -#define PKA_FUNCTION_SEQUENCER_OPERATIONS_S 12 +#define PKA_FUNCTION_SEQUENCER_OPERATIONS_W 3 +#define PKA_FUNCTION_SEQUENCER_OPERATIONS_M 0x00007000 +#define PKA_FUNCTION_SEQUENCER_OPERATIONS_S 12 // Field: [11] COPY // // Perform copy operation -#define PKA_FUNCTION_COPY 0x00000800 -#define PKA_FUNCTION_COPY_BITN 11 -#define PKA_FUNCTION_COPY_M 0x00000800 -#define PKA_FUNCTION_COPY_S 11 +#define PKA_FUNCTION_COPY 0x00000800 +#define PKA_FUNCTION_COPY_BITN 11 +#define PKA_FUNCTION_COPY_M 0x00000800 +#define PKA_FUNCTION_COPY_S 11 // Field: [10] COMPARE // // Perform compare operation -#define PKA_FUNCTION_COMPARE 0x00000400 -#define PKA_FUNCTION_COMPARE_BITN 10 -#define PKA_FUNCTION_COMPARE_M 0x00000400 -#define PKA_FUNCTION_COMPARE_S 10 +#define PKA_FUNCTION_COMPARE 0x00000400 +#define PKA_FUNCTION_COMPARE_BITN 10 +#define PKA_FUNCTION_COMPARE_M 0x00000400 +#define PKA_FUNCTION_COMPARE_S 10 // Field: [9] MODULO // // Perform modulo operation -#define PKA_FUNCTION_MODULO 0x00000200 -#define PKA_FUNCTION_MODULO_BITN 9 -#define PKA_FUNCTION_MODULO_M 0x00000200 -#define PKA_FUNCTION_MODULO_S 9 +#define PKA_FUNCTION_MODULO 0x00000200 +#define PKA_FUNCTION_MODULO_BITN 9 +#define PKA_FUNCTION_MODULO_M 0x00000200 +#define PKA_FUNCTION_MODULO_S 9 // Field: [8] DIVIDE // // Perform divide operation -#define PKA_FUNCTION_DIVIDE 0x00000100 -#define PKA_FUNCTION_DIVIDE_BITN 8 -#define PKA_FUNCTION_DIVIDE_M 0x00000100 -#define PKA_FUNCTION_DIVIDE_S 8 +#define PKA_FUNCTION_DIVIDE 0x00000100 +#define PKA_FUNCTION_DIVIDE_BITN 8 +#define PKA_FUNCTION_DIVIDE_M 0x00000100 +#define PKA_FUNCTION_DIVIDE_S 8 // Field: [7] LSHIFT // // Perform left shift operation -#define PKA_FUNCTION_LSHIFT 0x00000080 -#define PKA_FUNCTION_LSHIFT_BITN 7 -#define PKA_FUNCTION_LSHIFT_M 0x00000080 -#define PKA_FUNCTION_LSHIFT_S 7 +#define PKA_FUNCTION_LSHIFT 0x00000080 +#define PKA_FUNCTION_LSHIFT_BITN 7 +#define PKA_FUNCTION_LSHIFT_M 0x00000080 +#define PKA_FUNCTION_LSHIFT_S 7 // Field: [6] RSHIFT // // Perform right shift operation -#define PKA_FUNCTION_RSHIFT 0x00000040 -#define PKA_FUNCTION_RSHIFT_BITN 6 -#define PKA_FUNCTION_RSHIFT_M 0x00000040 -#define PKA_FUNCTION_RSHIFT_S 6 +#define PKA_FUNCTION_RSHIFT 0x00000040 +#define PKA_FUNCTION_RSHIFT_BITN 6 +#define PKA_FUNCTION_RSHIFT_M 0x00000040 +#define PKA_FUNCTION_RSHIFT_S 6 // Field: [5] SUBTRACT // // Perform subtract operation -#define PKA_FUNCTION_SUBTRACT 0x00000020 -#define PKA_FUNCTION_SUBTRACT_BITN 5 -#define PKA_FUNCTION_SUBTRACT_M 0x00000020 -#define PKA_FUNCTION_SUBTRACT_S 5 +#define PKA_FUNCTION_SUBTRACT 0x00000020 +#define PKA_FUNCTION_SUBTRACT_BITN 5 +#define PKA_FUNCTION_SUBTRACT_M 0x00000020 +#define PKA_FUNCTION_SUBTRACT_S 5 // Field: [4] ADD // // Perform add operation -#define PKA_FUNCTION_ADD 0x00000010 -#define PKA_FUNCTION_ADD_BITN 4 -#define PKA_FUNCTION_ADD_M 0x00000010 -#define PKA_FUNCTION_ADD_S 4 +#define PKA_FUNCTION_ADD 0x00000010 +#define PKA_FUNCTION_ADD_BITN 4 +#define PKA_FUNCTION_ADD_M 0x00000010 +#define PKA_FUNCTION_ADD_S 4 // Field: [3] MS_ONE // @@ -312,26 +312,26 @@ // indicated in the MSW register into bits [4:0] of the DIVMSW.MSW_ADDRESS // register - can only be used with basic PKCP operations, except for Divide, // Modulo and Compare. -#define PKA_FUNCTION_MS_ONE 0x00000008 -#define PKA_FUNCTION_MS_ONE_BITN 3 -#define PKA_FUNCTION_MS_ONE_M 0x00000008 -#define PKA_FUNCTION_MS_ONE_S 3 +#define PKA_FUNCTION_MS_ONE 0x00000008 +#define PKA_FUNCTION_MS_ONE_BITN 3 +#define PKA_FUNCTION_MS_ONE_M 0x00000008 +#define PKA_FUNCTION_MS_ONE_S 3 // Field: [1] ADDSUB // // Perform combined add/subtract operation -#define PKA_FUNCTION_ADDSUB 0x00000002 -#define PKA_FUNCTION_ADDSUB_BITN 1 -#define PKA_FUNCTION_ADDSUB_M 0x00000002 -#define PKA_FUNCTION_ADDSUB_S 1 +#define PKA_FUNCTION_ADDSUB 0x00000002 +#define PKA_FUNCTION_ADDSUB_BITN 1 +#define PKA_FUNCTION_ADDSUB_M 0x00000002 +#define PKA_FUNCTION_ADDSUB_S 1 // Field: [0] MULTIPLY // // Perform multiply operation -#define PKA_FUNCTION_MULTIPLY 0x00000001 -#define PKA_FUNCTION_MULTIPLY_BITN 0 -#define PKA_FUNCTION_MULTIPLY_M 0x00000001 -#define PKA_FUNCTION_MULTIPLY_S 0 +#define PKA_FUNCTION_MULTIPLY 0x00000001 +#define PKA_FUNCTION_MULTIPLY_BITN 0 +#define PKA_FUNCTION_MULTIPLY_M 0x00000001 +#define PKA_FUNCTION_MULTIPLY_S 0 //***************************************************************************** // @@ -341,26 +341,26 @@ // Field: [2] A_GREATER_THAN_B // // Vector_A is greater than Vector_B -#define PKA_COMPARE_A_GREATER_THAN_B 0x00000004 -#define PKA_COMPARE_A_GREATER_THAN_B_BITN 2 -#define PKA_COMPARE_A_GREATER_THAN_B_M 0x00000004 -#define PKA_COMPARE_A_GREATER_THAN_B_S 2 +#define PKA_COMPARE_A_GREATER_THAN_B 0x00000004 +#define PKA_COMPARE_A_GREATER_THAN_B_BITN 2 +#define PKA_COMPARE_A_GREATER_THAN_B_M 0x00000004 +#define PKA_COMPARE_A_GREATER_THAN_B_S 2 // Field: [1] A_LESS_THAN_B // // Vector_A is less than Vector_B -#define PKA_COMPARE_A_LESS_THAN_B 0x00000002 -#define PKA_COMPARE_A_LESS_THAN_B_BITN 1 -#define PKA_COMPARE_A_LESS_THAN_B_M 0x00000002 -#define PKA_COMPARE_A_LESS_THAN_B_S 1 +#define PKA_COMPARE_A_LESS_THAN_B 0x00000002 +#define PKA_COMPARE_A_LESS_THAN_B_BITN 1 +#define PKA_COMPARE_A_LESS_THAN_B_M 0x00000002 +#define PKA_COMPARE_A_LESS_THAN_B_S 1 // Field: [0] A_EQUALS_B // // Vector_A is equal to Vector_B -#define PKA_COMPARE_A_EQUALS_B 0x00000001 -#define PKA_COMPARE_A_EQUALS_B_BITN 0 -#define PKA_COMPARE_A_EQUALS_B_M 0x00000001 -#define PKA_COMPARE_A_EQUALS_B_S 0 +#define PKA_COMPARE_A_EQUALS_B 0x00000001 +#define PKA_COMPARE_A_EQUALS_B_BITN 0 +#define PKA_COMPARE_A_EQUALS_B_M 0x00000001 +#define PKA_COMPARE_A_EQUALS_B_S 0 //***************************************************************************** // @@ -370,18 +370,18 @@ // Field: [15] RESULT_IS_ZERO // // The result vector is all zeroes, ignore the address returned in bits [10:0] -#define PKA_MSW_RESULT_IS_ZERO 0x00008000 -#define PKA_MSW_RESULT_IS_ZERO_BITN 15 -#define PKA_MSW_RESULT_IS_ZERO_M 0x00008000 -#define PKA_MSW_RESULT_IS_ZERO_S 15 +#define PKA_MSW_RESULT_IS_ZERO 0x00008000 +#define PKA_MSW_RESULT_IS_ZERO_BITN 15 +#define PKA_MSW_RESULT_IS_ZERO_M 0x00008000 +#define PKA_MSW_RESULT_IS_ZERO_S 15 // Field: [10:0] MSW_ADDRESS // // Address of the most-significant nonzero 32-bit word of the result vector in // PKA RAM -#define PKA_MSW_MSW_ADDRESS_W 11 -#define PKA_MSW_MSW_ADDRESS_M 0x000007FF -#define PKA_MSW_MSW_ADDRESS_S 0 +#define PKA_MSW_MSW_ADDRESS_W 11 +#define PKA_MSW_MSW_ADDRESS_M 0x000007FF +#define PKA_MSW_MSW_ADDRESS_S 0 //***************************************************************************** // @@ -391,18 +391,18 @@ // Field: [15] RESULT_IS_ZERO // // The result vector is all zeroes, ignore the address returned in bits [10:0] -#define PKA_DIVMSW_RESULT_IS_ZERO 0x00008000 -#define PKA_DIVMSW_RESULT_IS_ZERO_BITN 15 -#define PKA_DIVMSW_RESULT_IS_ZERO_M 0x00008000 -#define PKA_DIVMSW_RESULT_IS_ZERO_S 15 +#define PKA_DIVMSW_RESULT_IS_ZERO 0x00008000 +#define PKA_DIVMSW_RESULT_IS_ZERO_BITN 15 +#define PKA_DIVMSW_RESULT_IS_ZERO_M 0x00008000 +#define PKA_DIVMSW_RESULT_IS_ZERO_S 15 // Field: [10:0] MSW_ADDRESS // // Address of the most significant nonzero 32-bit word of the remainder result // vector in PKA RAM -#define PKA_DIVMSW_MSW_ADDRESS_W 11 -#define PKA_DIVMSW_MSW_ADDRESS_M 0x000007FF -#define PKA_DIVMSW_MSW_ADDRESS_S 0 +#define PKA_DIVMSW_MSW_ADDRESS_W 11 +#define PKA_DIVMSW_MSW_ADDRESS_M 0x000007FF +#define PKA_DIVMSW_MSW_ADDRESS_S 0 //***************************************************************************** // @@ -425,10 +425,10 @@ // Resetting the sequencer (in order to load other firmware) should only be // done when the PKA Engine is not performing any operations (i.e. the // FUNCTION.RUN bit should be zero). -#define PKA_SEQCTRL_RESET 0x80000000 -#define PKA_SEQCTRL_RESET_BITN 31 -#define PKA_SEQCTRL_RESET_M 0x80000000 -#define PKA_SEQCTRL_RESET_S 31 +#define PKA_SEQCTRL_RESET 0x80000000 +#define PKA_SEQCTRL_RESET_BITN 31 +#define PKA_SEQCTRL_RESET_M 0x80000000 +#define PKA_SEQCTRL_RESET_S 31 // Field: [15:8] SEQUENCER_STAT // @@ -436,9 +436,9 @@ // the outside world. Bit [8] is also used as sequencer interrupt, with the // complement of this bit ORed into the FUNCTION.RUN bit. This field should // always be written with zeroes and ignored when reading this register. -#define PKA_SEQCTRL_SEQUENCER_STAT_W 8 -#define PKA_SEQCTRL_SEQUENCER_STAT_M 0x0000FF00 -#define PKA_SEQCTRL_SEQUENCER_STAT_S 8 +#define PKA_SEQCTRL_SEQUENCER_STAT_W 8 +#define PKA_SEQCTRL_SEQUENCER_STAT_M 0x0000FF00 +#define PKA_SEQCTRL_SEQUENCER_STAT_S 8 // Field: [7:0] SW_CONTROL_STAT // @@ -448,9 +448,9 @@ // Setting the FUNCTION.RUN bit together with a nonzero sequencer operations // field automatically sets bit [0] here. This field should always be written // with zeroes and ignored when reading this register. -#define PKA_SEQCTRL_SW_CONTROL_STAT_W 8 -#define PKA_SEQCTRL_SW_CONTROL_STAT_M 0x000000FF -#define PKA_SEQCTRL_SW_CONTROL_STAT_S 0 +#define PKA_SEQCTRL_SW_CONTROL_STAT_W 8 +#define PKA_SEQCTRL_SW_CONTROL_STAT_M 0x000000FF +#define PKA_SEQCTRL_SW_CONTROL_STAT_S 0 //***************************************************************************** // @@ -465,10 +465,10 @@ // register, 0x1 : indicates // that interrupt masking logic is present for this output. // Note: Reset value is undefined -#define PKA_OPTIONS_INT_MASKING 0x00000800 -#define PKA_OPTIONS_INT_MASKING_BITN 11 -#define PKA_OPTIONS_INT_MASKING_M 0x00000800 -#define PKA_OPTIONS_INT_MASKING_S 11 +#define PKA_OPTIONS_INT_MASKING 0x00000800 +#define PKA_OPTIONS_INT_MASKING_BITN 11 +#define PKA_OPTIONS_INT_MASKING_M 0x00000800 +#define PKA_OPTIONS_INT_MASKING_S 11 // Field: [10:8] PROTECTION_OPTION // @@ -479,9 +479,9 @@ // 0x2: Reserved // 0x3: indicates the PROT option; // Note: Reset value is undefined -#define PKA_OPTIONS_PROTECTION_OPTION_W 3 -#define PKA_OPTIONS_PROTECTION_OPTION_M 0x00000700 -#define PKA_OPTIONS_PROTECTION_OPTION_S 8 +#define PKA_OPTIONS_PROTECTION_OPTION_W 3 +#define PKA_OPTIONS_PROTECTION_OPTION_M 0x00000700 +#define PKA_OPTIONS_PROTECTION_OPTION_S 8 // Field: [7] PROGRAM_RAM // @@ -489,10 +489,10 @@ // 0x1: indicates sequencer program storage in RAM, 0x0: // indicates sequencer program storage in ROM. // Note: Reset value is undefined -#define PKA_OPTIONS_PROGRAM_RAM 0x00000080 -#define PKA_OPTIONS_PROGRAM_RAM_BITN 7 -#define PKA_OPTIONS_PROGRAM_RAM_M 0x00000080 -#define PKA_OPTIONS_PROGRAM_RAM_S 7 +#define PKA_OPTIONS_PROGRAM_RAM 0x00000080 +#define PKA_OPTIONS_PROGRAM_RAM_BITN 7 +#define PKA_OPTIONS_PROGRAM_RAM_M 0x00000080 +#define PKA_OPTIONS_PROGRAM_RAM_S 7 // Field: [6:5] SEQUENCER_CONFIGURATION // @@ -501,9 +501,9 @@ // 0x1 : Indicates a standard sequencer // 0x2: Reserved // 0x3: Reserved -#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_W 2 -#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_M 0x00000060 -#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_S 5 +#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_W 2 +#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_M 0x00000060 +#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_S 5 // Field: [1:0] PKCP_CONFIGURATION // @@ -512,9 +512,9 @@ // 0x1 : Indicates a PKCP with a 16x16 multiplier, 0x2: // indicates a PKCP with a 32x32 multiplier, 0x3 : Reserved // Note: Reset value is undefined. -#define PKA_OPTIONS_PKCP_CONFIGURATION_W 2 -#define PKA_OPTIONS_PKCP_CONFIGURATION_M 0x00000003 -#define PKA_OPTIONS_PKCP_CONFIGURATION_S 0 +#define PKA_OPTIONS_PKCP_CONFIGURATION_W 2 +#define PKA_OPTIONS_PKCP_CONFIGURATION_M 0x00000003 +#define PKA_OPTIONS_PKCP_CONFIGURATION_S 0 //***************************************************************************** // @@ -531,23 +531,23 @@ // adds Modular Inversion, 0x2: value // 2 adds Modular Inversion and ECC operations. // 0x3-0xF : Reserved. -#define PKA_FWREV_FW_CAPABILITIES_W 4 -#define PKA_FWREV_FW_CAPABILITIES_M 0xF0000000 -#define PKA_FWREV_FW_CAPABILITIES_S 28 +#define PKA_FWREV_FW_CAPABILITIES_W 4 +#define PKA_FWREV_FW_CAPABILITIES_M 0xF0000000 +#define PKA_FWREV_FW_CAPABILITIES_S 28 // Field: [27:24] MAJOR_FW_REVISION // // 4-bit binary encoding of the major firmware revision number -#define PKA_FWREV_MAJOR_FW_REVISION_W 4 -#define PKA_FWREV_MAJOR_FW_REVISION_M 0x0F000000 -#define PKA_FWREV_MAJOR_FW_REVISION_S 24 +#define PKA_FWREV_MAJOR_FW_REVISION_W 4 +#define PKA_FWREV_MAJOR_FW_REVISION_M 0x0F000000 +#define PKA_FWREV_MAJOR_FW_REVISION_S 24 // Field: [23:20] MINOR_FW_REVISION // // 4-bit binary encoding of the minor firmware revision number -#define PKA_FWREV_MINOR_FW_REVISION_W 4 -#define PKA_FWREV_MINOR_FW_REVISION_M 0x00F00000 -#define PKA_FWREV_MINOR_FW_REVISION_S 20 +#define PKA_FWREV_MINOR_FW_REVISION_W 4 +#define PKA_FWREV_MINOR_FW_REVISION_M 0x00F00000 +#define PKA_FWREV_MINOR_FW_REVISION_S 20 // Field: [19:16] FW_PATCH_LEVEL // @@ -555,9 +555,9 @@ // carry value zero // Patches are used to remove bugs without changing the functionality or // interface of a module. -#define PKA_FWREV_FW_PATCH_LEVEL_W 4 -#define PKA_FWREV_FW_PATCH_LEVEL_M 0x000F0000 -#define PKA_FWREV_FW_PATCH_LEVEL_S 16 +#define PKA_FWREV_FW_PATCH_LEVEL_W 4 +#define PKA_FWREV_FW_PATCH_LEVEL_M 0x000F0000 +#define PKA_FWREV_FW_PATCH_LEVEL_S 16 //***************************************************************************** // @@ -567,16 +567,16 @@ // Field: [27:24] MAJOR_HW_REVISION // // 4-bit binary encoding of the major hardware revision number -#define PKA_HWREV_MAJOR_HW_REVISION_W 4 -#define PKA_HWREV_MAJOR_HW_REVISION_M 0x0F000000 -#define PKA_HWREV_MAJOR_HW_REVISION_S 24 +#define PKA_HWREV_MAJOR_HW_REVISION_W 4 +#define PKA_HWREV_MAJOR_HW_REVISION_M 0x0F000000 +#define PKA_HWREV_MAJOR_HW_REVISION_S 24 // Field: [23:20] MINOR_HW_REVISION // // 4-bit binary encoding of the minor hardware revision number -#define PKA_HWREV_MINOR_HW_REVISION_W 4 -#define PKA_HWREV_MINOR_HW_REVISION_M 0x00F00000 -#define PKA_HWREV_MINOR_HW_REVISION_S 20 +#define PKA_HWREV_MINOR_HW_REVISION_W 4 +#define PKA_HWREV_MINOR_HW_REVISION_M 0x00F00000 +#define PKA_HWREV_MINOR_HW_REVISION_S 20 // Field: [19:16] HW_PATCH_LEVEL // @@ -584,23 +584,22 @@ // carry value zero // Patches are used to remove bugs without changing the functionality or // interface of a module. -#define PKA_HWREV_HW_PATCH_LEVEL_W 4 -#define PKA_HWREV_HW_PATCH_LEVEL_M 0x000F0000 -#define PKA_HWREV_HW_PATCH_LEVEL_S 16 +#define PKA_HWREV_HW_PATCH_LEVEL_W 4 +#define PKA_HWREV_HW_PATCH_LEVEL_M 0x000F0000 +#define PKA_HWREV_HW_PATCH_LEVEL_S 16 // Field: [15:8] COMPLEMENT_OF_BASIC_EIP_NUMBER // // Bit-by-bit logic complement of bits [7:0], EIP-28 gives 0xE3 -#define PKA_HWREV_COMPLEMENT_OF_BASIC_EIP_NUMBER_W 8 -#define PKA_HWREV_COMPLEMENT_OF_BASIC_EIP_NUMBER_M 0x0000FF00 -#define PKA_HWREV_COMPLEMENT_OF_BASIC_EIP_NUMBER_S 8 +#define PKA_HWREV_COMPLEMENT_OF_BASIC_EIP_NUMBER_W 8 +#define PKA_HWREV_COMPLEMENT_OF_BASIC_EIP_NUMBER_M 0x0000FF00 +#define PKA_HWREV_COMPLEMENT_OF_BASIC_EIP_NUMBER_S 8 // Field: [7:0] BASIC_EIP_NUMBER // // 8-bit binary encoding of the EIP number, EIP-28 gives 0x1C -#define PKA_HWREV_BASIC_EIP_NUMBER_W 8 -#define PKA_HWREV_BASIC_EIP_NUMBER_M 0x000000FF -#define PKA_HWREV_BASIC_EIP_NUMBER_S 0 - +#define PKA_HWREV_BASIC_EIP_NUMBER_W 8 +#define PKA_HWREV_BASIC_EIP_NUMBER_M 0x000000FF +#define PKA_HWREV_BASIC_EIP_NUMBER_S 0 #endif // __PKA__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_int.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_int.h index 5920199..6a78aa7 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_int.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_int.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_pka_int_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_pka_int_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_PKA_INT_H__ #define __HW_PKA_INT_H__ @@ -44,10 +44,10 @@ // //***************************************************************************** // PKA Options register -#define PKA_INT_O_OPTIONS 0x00000FF8 +#define PKA_INT_O_OPTIONS 0x00000FF8 // PKA hardware revision register -#define PKA_INT_O_REVISION 0x00000FFC +#define PKA_INT_O_REVISION 0x00000FFC //***************************************************************************** // @@ -57,59 +57,59 @@ // Field: [10] AIC_PRESENT // // When set to '1', indicates that an EIP201 AIC is included in the EIP150 -#define PKA_INT_OPTIONS_AIC_PRESENT 0x00000400 -#define PKA_INT_OPTIONS_AIC_PRESENT_BITN 10 -#define PKA_INT_OPTIONS_AIC_PRESENT_M 0x00000400 -#define PKA_INT_OPTIONS_AIC_PRESENT_S 10 +#define PKA_INT_OPTIONS_AIC_PRESENT 0x00000400 +#define PKA_INT_OPTIONS_AIC_PRESENT_BITN 10 +#define PKA_INT_OPTIONS_AIC_PRESENT_M 0x00000400 +#define PKA_INT_OPTIONS_AIC_PRESENT_S 10 // Field: [9] EIP76_PRESENT // // When set to '1', indicates that the EIP76 TRNG is included in the EIP150 -#define PKA_INT_OPTIONS_EIP76_PRESENT 0x00000200 -#define PKA_INT_OPTIONS_EIP76_PRESENT_BITN 9 -#define PKA_INT_OPTIONS_EIP76_PRESENT_M 0x00000200 -#define PKA_INT_OPTIONS_EIP76_PRESENT_S 9 +#define PKA_INT_OPTIONS_EIP76_PRESENT 0x00000200 +#define PKA_INT_OPTIONS_EIP76_PRESENT_BITN 9 +#define PKA_INT_OPTIONS_EIP76_PRESENT_M 0x00000200 +#define PKA_INT_OPTIONS_EIP76_PRESENT_S 9 // Field: [8] EIP28_PRESENT // // When set to '1', indicates that the EIP28 PKA is included in the EIP150 -#define PKA_INT_OPTIONS_EIP28_PRESENT 0x00000100 -#define PKA_INT_OPTIONS_EIP28_PRESENT_BITN 8 -#define PKA_INT_OPTIONS_EIP28_PRESENT_M 0x00000100 -#define PKA_INT_OPTIONS_EIP28_PRESENT_S 8 +#define PKA_INT_OPTIONS_EIP28_PRESENT 0x00000100 +#define PKA_INT_OPTIONS_EIP28_PRESENT_BITN 8 +#define PKA_INT_OPTIONS_EIP28_PRESENT_M 0x00000100 +#define PKA_INT_OPTIONS_EIP28_PRESENT_S 8 // Field: [3] AXI_INTERFACE // // When set to '1', indicates that the EIP150 is equipped with a AXI interface -#define PKA_INT_OPTIONS_AXI_INTERFACE 0x00000008 -#define PKA_INT_OPTIONS_AXI_INTERFACE_BITN 3 -#define PKA_INT_OPTIONS_AXI_INTERFACE_M 0x00000008 -#define PKA_INT_OPTIONS_AXI_INTERFACE_S 3 +#define PKA_INT_OPTIONS_AXI_INTERFACE 0x00000008 +#define PKA_INT_OPTIONS_AXI_INTERFACE_BITN 3 +#define PKA_INT_OPTIONS_AXI_INTERFACE_M 0x00000008 +#define PKA_INT_OPTIONS_AXI_INTERFACE_S 3 // Field: [2] AHB_IS_ASYNC // // When set to '1', indicates that AHB interface is asynchronous Only // applicable when AHB_INTERFACE is 1 -#define PKA_INT_OPTIONS_AHB_IS_ASYNC 0x00000004 -#define PKA_INT_OPTIONS_AHB_IS_ASYNC_BITN 2 -#define PKA_INT_OPTIONS_AHB_IS_ASYNC_M 0x00000004 -#define PKA_INT_OPTIONS_AHB_IS_ASYNC_S 2 +#define PKA_INT_OPTIONS_AHB_IS_ASYNC 0x00000004 +#define PKA_INT_OPTIONS_AHB_IS_ASYNC_BITN 2 +#define PKA_INT_OPTIONS_AHB_IS_ASYNC_M 0x00000004 +#define PKA_INT_OPTIONS_AHB_IS_ASYNC_S 2 // Field: [1] AHB_INTERFACE // // When set to '1', indicates that the EIP150 is equipped with a AHB interface -#define PKA_INT_OPTIONS_AHB_INTERFACE 0x00000002 -#define PKA_INT_OPTIONS_AHB_INTERFACE_BITN 1 -#define PKA_INT_OPTIONS_AHB_INTERFACE_M 0x00000002 -#define PKA_INT_OPTIONS_AHB_INTERFACE_S 1 +#define PKA_INT_OPTIONS_AHB_INTERFACE 0x00000002 +#define PKA_INT_OPTIONS_AHB_INTERFACE_BITN 1 +#define PKA_INT_OPTIONS_AHB_INTERFACE_M 0x00000002 +#define PKA_INT_OPTIONS_AHB_INTERFACE_S 1 // Field: [0] PLB_INTERFACE // // When set to '1', indicates that the EIP150 is equipped with a PLB interface -#define PKA_INT_OPTIONS_PLB_INTERFACE 0x00000001 -#define PKA_INT_OPTIONS_PLB_INTERFACE_BITN 0 -#define PKA_INT_OPTIONS_PLB_INTERFACE_M 0x00000001 -#define PKA_INT_OPTIONS_PLB_INTERFACE_S 0 +#define PKA_INT_OPTIONS_PLB_INTERFACE 0x00000001 +#define PKA_INT_OPTIONS_PLB_INTERFACE_BITN 0 +#define PKA_INT_OPTIONS_PLB_INTERFACE_M 0x00000001 +#define PKA_INT_OPTIONS_PLB_INTERFACE_S 0 //***************************************************************************** // @@ -119,39 +119,38 @@ // Field: [27:24] MAJOR_REVISION // // These bits encode the major version number for this module -#define PKA_INT_REVISION_MAJOR_REVISION_W 4 -#define PKA_INT_REVISION_MAJOR_REVISION_M 0x0F000000 -#define PKA_INT_REVISION_MAJOR_REVISION_S 24 +#define PKA_INT_REVISION_MAJOR_REVISION_W 4 +#define PKA_INT_REVISION_MAJOR_REVISION_M 0x0F000000 +#define PKA_INT_REVISION_MAJOR_REVISION_S 24 // Field: [23:20] MINOR_REVISION // // These bits encode the minor version number for this module -#define PKA_INT_REVISION_MINOR_REVISION_W 4 -#define PKA_INT_REVISION_MINOR_REVISION_M 0x00F00000 -#define PKA_INT_REVISION_MINOR_REVISION_S 20 +#define PKA_INT_REVISION_MINOR_REVISION_W 4 +#define PKA_INT_REVISION_MINOR_REVISION_M 0x00F00000 +#define PKA_INT_REVISION_MINOR_REVISION_S 20 // Field: [19:16] PATCH_LEVEL // // These bits encode the hardware patch level for this module they start at // value 0 on the first release -#define PKA_INT_REVISION_PATCH_LEVEL_W 4 -#define PKA_INT_REVISION_PATCH_LEVEL_M 0x000F0000 -#define PKA_INT_REVISION_PATCH_LEVEL_S 16 +#define PKA_INT_REVISION_PATCH_LEVEL_W 4 +#define PKA_INT_REVISION_PATCH_LEVEL_M 0x000F0000 +#define PKA_INT_REVISION_PATCH_LEVEL_S 16 // Field: [15:8] COMP_EIP_NUM // // These bits simply contain the complement of bits [7:0], used by a driver to // ascertain that the EIP150 revision register is indeed read -#define PKA_INT_REVISION_COMP_EIP_NUM_W 8 -#define PKA_INT_REVISION_COMP_EIP_NUM_M 0x0000FF00 -#define PKA_INT_REVISION_COMP_EIP_NUM_S 8 +#define PKA_INT_REVISION_COMP_EIP_NUM_W 8 +#define PKA_INT_REVISION_COMP_EIP_NUM_M 0x0000FF00 +#define PKA_INT_REVISION_COMP_EIP_NUM_S 8 // Field: [7:0] EIP_NUM // // These bits encode the AuthenTec EIP number for the EIP150 -#define PKA_INT_REVISION_EIP_NUM_W 8 -#define PKA_INT_REVISION_EIP_NUM_M 0x000000FF -#define PKA_INT_REVISION_EIP_NUM_S 0 - +#define PKA_INT_REVISION_EIP_NUM_W 8 +#define PKA_INT_REVISION_EIP_NUM_M 0x000000FF +#define PKA_INT_REVISION_EIP_NUM_S 0 #endif // __PKA_INT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_ram.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_ram.h index 4c4599e..22142f0 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_ram.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_ram.h @@ -1,48 +1,45 @@ /****************************************************************************** -* Filename: hw_pka_ram_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_pka_ram_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_PKA_RAM_H__ #define __HW_PKA_RAM_H__ +#define PKA_RAM_O_BANK0 0x00000000 +#define PKA_RAM_BANK0_BYTE_SIZE 2048 -#define PKA_RAM_O_BANK0 0x00000000 -#define PKA_RAM_BANK0_BYTE_SIZE 2048 - -#define PKA_RAM_TOT_BYTE_SIZE 2048 - - +#define PKA_RAM_TOT_BYTE_SIZE 2048 #endif // __HW_PKA_RAM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_prcm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_prcm.h index 38fecfa..7a4fa06 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_prcm.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_prcm.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_prcm_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_prcm_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_PRCM_H__ #define __HW_PRCM_H__ @@ -44,217 +44,217 @@ // //***************************************************************************** // Infrastructure Clock Division Factor For Run Mode -#define PRCM_O_INFRCLKDIVR 0x00000000 +#define PRCM_O_INFRCLKDIVR 0x00000000 // Infrastructure Clock Division Factor For Sleep Mode -#define PRCM_O_INFRCLKDIVS 0x00000004 +#define PRCM_O_INFRCLKDIVS 0x00000004 // Infrastructure Clock Division Factor For DeepSleep Mode -#define PRCM_O_INFRCLKDIVDS 0x00000008 +#define PRCM_O_INFRCLKDIVDS 0x00000008 // MCU Voltage Domain Control -#define PRCM_O_VDCTL 0x0000000C +#define PRCM_O_VDCTL 0x0000000C // Load PRCM Settings To CLKCTRL Power Domain -#define PRCM_O_CLKLOADCTL 0x00000028 +#define PRCM_O_CLKLOADCTL 0x00000028 // RFC Clock Gate -#define PRCM_O_RFCCLKG 0x0000002C +#define PRCM_O_RFCCLKG 0x0000002C // VIMS Clock Gate -#define PRCM_O_VIMSCLKG 0x00000030 +#define PRCM_O_VIMSCLKG 0x00000030 // SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes -#define PRCM_O_SECDMACLKGR 0x0000003C +#define PRCM_O_SECDMACLKGR 0x0000003C // SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode -#define PRCM_O_SECDMACLKGS 0x00000040 +#define PRCM_O_SECDMACLKGS 0x00000040 // SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode -#define PRCM_O_SECDMACLKGDS 0x00000044 +#define PRCM_O_SECDMACLKGDS 0x00000044 // GPIO Clock Gate For Run And All Modes -#define PRCM_O_GPIOCLKGR 0x00000048 +#define PRCM_O_GPIOCLKGR 0x00000048 // GPIO Clock Gate For Sleep Mode -#define PRCM_O_GPIOCLKGS 0x0000004C +#define PRCM_O_GPIOCLKGS 0x0000004C // GPIO Clock Gate For Deep Sleep Mode -#define PRCM_O_GPIOCLKGDS 0x00000050 +#define PRCM_O_GPIOCLKGDS 0x00000050 // GPT Clock Gate For Run And All Modes -#define PRCM_O_GPTCLKGR 0x00000054 +#define PRCM_O_GPTCLKGR 0x00000054 // GPT Clock Gate For Sleep Mode -#define PRCM_O_GPTCLKGS 0x00000058 +#define PRCM_O_GPTCLKGS 0x00000058 // GPT Clock Gate For Deep Sleep Mode -#define PRCM_O_GPTCLKGDS 0x0000005C +#define PRCM_O_GPTCLKGDS 0x0000005C // I2C Clock Gate For Run And All Modes -#define PRCM_O_I2CCLKGR 0x00000060 +#define PRCM_O_I2CCLKGR 0x00000060 // I2C Clock Gate For Sleep Mode -#define PRCM_O_I2CCLKGS 0x00000064 +#define PRCM_O_I2CCLKGS 0x00000064 // I2C Clock Gate For Deep Sleep Mode -#define PRCM_O_I2CCLKGDS 0x00000068 +#define PRCM_O_I2CCLKGDS 0x00000068 // UART Clock Gate For Run And All Modes -#define PRCM_O_UARTCLKGR 0x0000006C +#define PRCM_O_UARTCLKGR 0x0000006C // UART Clock Gate For Sleep Mode -#define PRCM_O_UARTCLKGS 0x00000070 +#define PRCM_O_UARTCLKGS 0x00000070 // UART Clock Gate For Deep Sleep Mode -#define PRCM_O_UARTCLKGDS 0x00000074 +#define PRCM_O_UARTCLKGDS 0x00000074 // SSI Clock Gate For Run And All Modes -#define PRCM_O_SSICLKGR 0x00000078 +#define PRCM_O_SSICLKGR 0x00000078 // SSI Clock Gate For Sleep Mode -#define PRCM_O_SSICLKGS 0x0000007C +#define PRCM_O_SSICLKGS 0x0000007C // SSI Clock Gate For Deep Sleep Mode -#define PRCM_O_SSICLKGDS 0x00000080 +#define PRCM_O_SSICLKGDS 0x00000080 // I2S Clock Gate For Run And All Modes -#define PRCM_O_I2SCLKGR 0x00000084 +#define PRCM_O_I2SCLKGR 0x00000084 // I2S Clock Gate For Sleep Mode -#define PRCM_O_I2SCLKGS 0x00000088 +#define PRCM_O_I2SCLKGS 0x00000088 // I2S Clock Gate For Deep Sleep Mode -#define PRCM_O_I2SCLKGDS 0x0000008C +#define PRCM_O_I2SCLKGDS 0x0000008C // Internal -#define PRCM_O_SYSBUSCLKDIV 0x000000B4 +#define PRCM_O_SYSBUSCLKDIV 0x000000B4 // Internal -#define PRCM_O_CPUCLKDIV 0x000000B8 +#define PRCM_O_CPUCLKDIV 0x000000B8 // Internal -#define PRCM_O_PERBUSCPUCLKDIV 0x000000BC +#define PRCM_O_PERBUSCPUCLKDIV 0x000000BC // Internal -#define PRCM_O_PERDMACLKDIV 0x000000C4 +#define PRCM_O_PERDMACLKDIV 0x000000C4 // I2S Clock Control -#define PRCM_O_I2SBCLKSEL 0x000000C8 +#define PRCM_O_I2SBCLKSEL 0x000000C8 // GPT Scalar -#define PRCM_O_GPTCLKDIV 0x000000CC +#define PRCM_O_GPTCLKDIV 0x000000CC // I2S Clock Control -#define PRCM_O_I2SCLKCTL 0x000000D0 +#define PRCM_O_I2SCLKCTL 0x000000D0 // MCLK Division Ratio -#define PRCM_O_I2SMCLKDIV 0x000000D4 +#define PRCM_O_I2SMCLKDIV 0x000000D4 // BCLK Division Ratio -#define PRCM_O_I2SBCLKDIV 0x000000D8 +#define PRCM_O_I2SBCLKDIV 0x000000D8 // WCLK Division Ratio -#define PRCM_O_I2SWCLKDIV 0x000000DC +#define PRCM_O_I2SWCLKDIV 0x000000DC // RESET For SEC (PKA And TRNG And CRYPTO) And UDMA -#define PRCM_O_RESETSECDMA 0x000000F0 +#define PRCM_O_RESETSECDMA 0x000000F0 // RESET For GPIO IPs -#define PRCM_O_RESETGPIO 0x000000F4 +#define PRCM_O_RESETGPIO 0x000000F4 // RESET For GPT Ips -#define PRCM_O_RESETGPT 0x000000F8 +#define PRCM_O_RESETGPT 0x000000F8 // RESET For I2C IPs -#define PRCM_O_RESETI2C 0x000000FC +#define PRCM_O_RESETI2C 0x000000FC // RESET For UART IPs -#define PRCM_O_RESETUART 0x00000100 +#define PRCM_O_RESETUART 0x00000100 // RESET For SSI IPs -#define PRCM_O_RESETSSI 0x00000104 +#define PRCM_O_RESETSSI 0x00000104 // RESET For I2S IP -#define PRCM_O_RESETI2S 0x00000108 +#define PRCM_O_RESETI2S 0x00000108 // Power Domain Control -#define PRCM_O_PDCTL0 0x0000012C +#define PRCM_O_PDCTL0 0x0000012C // RFC Power Domain Control -#define PRCM_O_PDCTL0RFC 0x00000130 +#define PRCM_O_PDCTL0RFC 0x00000130 // SERIAL Power Domain Control -#define PRCM_O_PDCTL0SERIAL 0x00000134 +#define PRCM_O_PDCTL0SERIAL 0x00000134 // PERIPH Power Domain Control -#define PRCM_O_PDCTL0PERIPH 0x00000138 +#define PRCM_O_PDCTL0PERIPH 0x00000138 // Power Domain Status -#define PRCM_O_PDSTAT0 0x00000140 +#define PRCM_O_PDSTAT0 0x00000140 // RFC Power Domain Status -#define PRCM_O_PDSTAT0RFC 0x00000144 +#define PRCM_O_PDSTAT0RFC 0x00000144 // SERIAL Power Domain Status -#define PRCM_O_PDSTAT0SERIAL 0x00000148 +#define PRCM_O_PDSTAT0SERIAL 0x00000148 // PERIPH Power Domain Status -#define PRCM_O_PDSTAT0PERIPH 0x0000014C +#define PRCM_O_PDSTAT0PERIPH 0x0000014C // Power Domain Control -#define PRCM_O_PDCTL1 0x0000017C +#define PRCM_O_PDCTL1 0x0000017C // CPU Power Domain Direct Control -#define PRCM_O_PDCTL1CPU 0x00000184 +#define PRCM_O_PDCTL1CPU 0x00000184 // RFC Power Domain Direct Control -#define PRCM_O_PDCTL1RFC 0x00000188 +#define PRCM_O_PDCTL1RFC 0x00000188 // VIMS Mode Direct Control -#define PRCM_O_PDCTL1VIMS 0x0000018C +#define PRCM_O_PDCTL1VIMS 0x0000018C // Power Manager Status -#define PRCM_O_PDSTAT1 0x00000194 +#define PRCM_O_PDSTAT1 0x00000194 // BUS Power Domain Direct Read Status -#define PRCM_O_PDSTAT1BUS 0x00000198 +#define PRCM_O_PDSTAT1BUS 0x00000198 // RFC Power Domain Direct Read Status -#define PRCM_O_PDSTAT1RFC 0x0000019C +#define PRCM_O_PDSTAT1RFC 0x0000019C // CPU Power Domain Direct Read Status -#define PRCM_O_PDSTAT1CPU 0x000001A0 +#define PRCM_O_PDSTAT1CPU 0x000001A0 // VIMS Mode Direct Read Status -#define PRCM_O_PDSTAT1VIMS 0x000001A4 +#define PRCM_O_PDSTAT1VIMS 0x000001A4 // Control To RFC -#define PRCM_O_RFCBITS 0x000001CC +#define PRCM_O_RFCBITS 0x000001CC // Selected RFC Mode -#define PRCM_O_RFCMODESEL 0x000001D0 +#define PRCM_O_RFCMODESEL 0x000001D0 // Allowed RFC Modes -#define PRCM_O_RFCMODEHWOPT 0x000001D4 +#define PRCM_O_RFCMODEHWOPT 0x000001D4 // Power Profiler Register -#define PRCM_O_PWRPROFSTAT 0x000001E0 +#define PRCM_O_PWRPROFSTAT 0x000001E0 // MCU SRAM configuration -#define PRCM_O_MCUSRAMCFG 0x0000021C +#define PRCM_O_MCUSRAMCFG 0x0000021C // Memory Retention Control -#define PRCM_O_RAMRETEN 0x00000224 +#define PRCM_O_RAMRETEN 0x00000224 // Oscillator Interrupt Mask -#define PRCM_O_OSCIMSC 0x00000290 +#define PRCM_O_OSCIMSC 0x00000290 // Oscillator Raw Interrupt Status -#define PRCM_O_OSCRIS 0x00000294 +#define PRCM_O_OSCRIS 0x00000294 // Oscillator Raw Interrupt Clear -#define PRCM_O_OSCICR 0x00000298 +#define PRCM_O_OSCICR 0x00000298 //***************************************************************************** // @@ -271,13 +271,13 @@ // DIV8 Divide by 8 // DIV2 Divide by 2 // DIV1 Divide by 1 -#define PRCM_INFRCLKDIVR_RATIO_W 2 -#define PRCM_INFRCLKDIVR_RATIO_M 0x00000003 -#define PRCM_INFRCLKDIVR_RATIO_S 0 -#define PRCM_INFRCLKDIVR_RATIO_DIV32 0x00000003 -#define PRCM_INFRCLKDIVR_RATIO_DIV8 0x00000002 -#define PRCM_INFRCLKDIVR_RATIO_DIV2 0x00000001 -#define PRCM_INFRCLKDIVR_RATIO_DIV1 0x00000000 +#define PRCM_INFRCLKDIVR_RATIO_W 2 +#define PRCM_INFRCLKDIVR_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVR_RATIO_S 0 +#define PRCM_INFRCLKDIVR_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVR_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVR_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVR_RATIO_DIV1 0x00000000 //***************************************************************************** // @@ -294,13 +294,13 @@ // DIV8 Divide by 8 // DIV2 Divide by 2 // DIV1 Divide by 1 -#define PRCM_INFRCLKDIVS_RATIO_W 2 -#define PRCM_INFRCLKDIVS_RATIO_M 0x00000003 -#define PRCM_INFRCLKDIVS_RATIO_S 0 -#define PRCM_INFRCLKDIVS_RATIO_DIV32 0x00000003 -#define PRCM_INFRCLKDIVS_RATIO_DIV8 0x00000002 -#define PRCM_INFRCLKDIVS_RATIO_DIV2 0x00000001 -#define PRCM_INFRCLKDIVS_RATIO_DIV1 0x00000000 +#define PRCM_INFRCLKDIVS_RATIO_W 2 +#define PRCM_INFRCLKDIVS_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVS_RATIO_S 0 +#define PRCM_INFRCLKDIVS_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVS_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVS_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVS_RATIO_DIV1 0x00000000 //***************************************************************************** // @@ -317,13 +317,13 @@ // DIV8 Divide by 8 // DIV2 Divide by 2 // DIV1 Divide by 1 -#define PRCM_INFRCLKDIVDS_RATIO_W 2 -#define PRCM_INFRCLKDIVDS_RATIO_M 0x00000003 -#define PRCM_INFRCLKDIVDS_RATIO_S 0 -#define PRCM_INFRCLKDIVDS_RATIO_DIV32 0x00000003 -#define PRCM_INFRCLKDIVDS_RATIO_DIV8 0x00000002 -#define PRCM_INFRCLKDIVDS_RATIO_DIV2 0x00000001 -#define PRCM_INFRCLKDIVDS_RATIO_DIV1 0x00000000 +#define PRCM_INFRCLKDIVDS_RATIO_W 2 +#define PRCM_INFRCLKDIVDS_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVDS_RATIO_S 0 +#define PRCM_INFRCLKDIVDS_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVDS_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVDS_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVDS_RATIO_DIV1 0x00000000 //***************************************************************************** // @@ -349,10 +349,10 @@ // loaded with CLKLOADCTL.LOAD) // 6. RFC do no request access to BUS // 7. System CPU in deepsleep -#define PRCM_VDCTL_ULDO 0x00000001 -#define PRCM_VDCTL_ULDO_BITN 0 -#define PRCM_VDCTL_ULDO_M 0x00000001 -#define PRCM_VDCTL_ULDO_S 0 +#define PRCM_VDCTL_ULDO 0x00000001 +#define PRCM_VDCTL_ULDO_BITN 0 +#define PRCM_VDCTL_ULDO_M 0x00000001 +#define PRCM_VDCTL_ULDO_S 0 //***************************************************************************** // @@ -369,10 +369,10 @@ // // 0 : One or more registers have been write accessed after last LOAD // 1 : No registers are write accessed after last LOAD -#define PRCM_CLKLOADCTL_LOAD_DONE 0x00000002 -#define PRCM_CLKLOADCTL_LOAD_DONE_BITN 1 -#define PRCM_CLKLOADCTL_LOAD_DONE_M 0x00000002 -#define PRCM_CLKLOADCTL_LOAD_DONE_S 1 +#define PRCM_CLKLOADCTL_LOAD_DONE 0x00000002 +#define PRCM_CLKLOADCTL_LOAD_DONE_BITN 1 +#define PRCM_CLKLOADCTL_LOAD_DONE_M 0x00000002 +#define PRCM_CLKLOADCTL_LOAD_DONE_S 1 // Field: [0] LOAD // @@ -420,10 +420,10 @@ // - I2SMCLKDIV // - I2SBCLKDIV // - I2SWCLKDIV -#define PRCM_CLKLOADCTL_LOAD 0x00000001 -#define PRCM_CLKLOADCTL_LOAD_BITN 0 -#define PRCM_CLKLOADCTL_LOAD_M 0x00000001 -#define PRCM_CLKLOADCTL_LOAD_S 0 +#define PRCM_CLKLOADCTL_LOAD 0x00000001 +#define PRCM_CLKLOADCTL_LOAD_BITN 0 +#define PRCM_CLKLOADCTL_LOAD_M 0x00000001 +#define PRCM_CLKLOADCTL_LOAD_S 0 //***************************************************************************** // @@ -437,10 +437,10 @@ // 1: Enable clock if RFC power domain is on // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_RFCCLKG_CLK_EN 0x00000001 -#define PRCM_RFCCLKG_CLK_EN_BITN 0 -#define PRCM_RFCCLKG_CLK_EN_M 0x00000001 -#define PRCM_RFCCLKG_CLK_EN_S 0 +#define PRCM_RFCCLKG_CLK_EN 0x00000001 +#define PRCM_RFCCLKG_CLK_EN_BITN 0 +#define PRCM_RFCCLKG_CLK_EN_M 0x00000001 +#define PRCM_RFCCLKG_CLK_EN_S 0 //***************************************************************************** // @@ -454,9 +454,9 @@ // 11: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_VIMSCLKG_CLK_EN_W 2 -#define PRCM_VIMSCLKG_CLK_EN_M 0x00000003 -#define PRCM_VIMSCLKG_CLK_EN_S 0 +#define PRCM_VIMSCLKG_CLK_EN_W 2 +#define PRCM_VIMSCLKG_CLK_EN_M 0x00000003 +#define PRCM_VIMSCLKG_CLK_EN_S 0 //***************************************************************************** // @@ -475,10 +475,10 @@ // SYSBUS clock will always run when enabled // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN 0x01000000 -#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_BITN 24 -#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_M 0x01000000 -#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_S 24 +#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN 0x01000000 +#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_BITN 24 +#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_M 0x01000000 +#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_S 24 // Field: [19] PKA_ZERIOZE_RESET_N // @@ -489,10 +489,10 @@ // // This register must remain active until the memory are completely zeroized // which requires 256 periods on systembus clock. -#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N 0x00080000 -#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_BITN 19 -#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_M 0x00080000 -#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_S 19 +#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N 0x00080000 +#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_BITN 19 +#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_M 0x00080000 +#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_S 19 // Field: [18] PKA_AM_CLK_EN // @@ -504,10 +504,10 @@ // when enabled. // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN 0x00040000 -#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_BITN 18 -#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_M 0x00040000 -#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_S 18 +#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN 0x00040000 +#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_BITN 18 +#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_M 0x00040000 +#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_S 18 // Field: [17] TRNG_AM_CLK_EN // @@ -519,10 +519,10 @@ // when enabled. // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN 0x00020000 -#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_BITN 17 -#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_M 0x00020000 -#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_S 17 +#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN 0x00020000 +#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_BITN 17 +#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_M 0x00020000 +#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_S 17 // Field: [16] CRYPTO_AM_CLK_EN // @@ -536,10 +536,10 @@ // SYSBUS clock will always run when enabled // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN 0x00010000 -#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_BITN 16 -#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_M 0x00010000 -#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_S 16 +#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN 0x00010000 +#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_BITN 16 +#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_M 0x00010000 +#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_S 16 // Field: [8] DMA_CLK_EN // @@ -550,10 +550,10 @@ // Can be forced on by DMA_AM_CLK_EN // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_DMA_CLK_EN 0x00000100 -#define PRCM_SECDMACLKGR_DMA_CLK_EN_BITN 8 -#define PRCM_SECDMACLKGR_DMA_CLK_EN_M 0x00000100 -#define PRCM_SECDMACLKGR_DMA_CLK_EN_S 8 +#define PRCM_SECDMACLKGR_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_S 8 // Field: [2] PKA_CLK_EN // @@ -564,10 +564,10 @@ // Can be forced on by PKA_AM_CLK_EN // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_PKA_CLK_EN 0x00000004 -#define PRCM_SECDMACLKGR_PKA_CLK_EN_BITN 2 -#define PRCM_SECDMACLKGR_PKA_CLK_EN_M 0x00000004 -#define PRCM_SECDMACLKGR_PKA_CLK_EN_S 2 +#define PRCM_SECDMACLKGR_PKA_CLK_EN 0x00000004 +#define PRCM_SECDMACLKGR_PKA_CLK_EN_BITN 2 +#define PRCM_SECDMACLKGR_PKA_CLK_EN_M 0x00000004 +#define PRCM_SECDMACLKGR_PKA_CLK_EN_S 2 // Field: [1] TRNG_CLK_EN // @@ -578,10 +578,10 @@ // Can be forced on by TRNG_AM_CLK_EN // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_TRNG_CLK_EN 0x00000002 -#define PRCM_SECDMACLKGR_TRNG_CLK_EN_BITN 1 -#define PRCM_SECDMACLKGR_TRNG_CLK_EN_M 0x00000002 -#define PRCM_SECDMACLKGR_TRNG_CLK_EN_S 1 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_S 1 // Field: [0] CRYPTO_CLK_EN // @@ -592,10 +592,10 @@ // Can be forced on by CRYPTO_AM_CLK_EN // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN 0x00000001 -#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_BITN 0 -#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_M 0x00000001 -#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S 0 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S 0 //***************************************************************************** // @@ -611,10 +611,10 @@ // Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGS_DMA_CLK_EN 0x00000100 -#define PRCM_SECDMACLKGS_DMA_CLK_EN_BITN 8 -#define PRCM_SECDMACLKGS_DMA_CLK_EN_M 0x00000100 -#define PRCM_SECDMACLKGS_DMA_CLK_EN_S 8 +#define PRCM_SECDMACLKGS_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_S 8 // Field: [2] PKA_CLK_EN // @@ -625,10 +625,10 @@ // Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGS_PKA_CLK_EN 0x00000004 -#define PRCM_SECDMACLKGS_PKA_CLK_EN_BITN 2 -#define PRCM_SECDMACLKGS_PKA_CLK_EN_M 0x00000004 -#define PRCM_SECDMACLKGS_PKA_CLK_EN_S 2 +#define PRCM_SECDMACLKGS_PKA_CLK_EN 0x00000004 +#define PRCM_SECDMACLKGS_PKA_CLK_EN_BITN 2 +#define PRCM_SECDMACLKGS_PKA_CLK_EN_M 0x00000004 +#define PRCM_SECDMACLKGS_PKA_CLK_EN_S 2 // Field: [1] TRNG_CLK_EN // @@ -639,10 +639,10 @@ // Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGS_TRNG_CLK_EN 0x00000002 -#define PRCM_SECDMACLKGS_TRNG_CLK_EN_BITN 1 -#define PRCM_SECDMACLKGS_TRNG_CLK_EN_M 0x00000002 -#define PRCM_SECDMACLKGS_TRNG_CLK_EN_S 1 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_S 1 // Field: [0] CRYPTO_CLK_EN // @@ -653,10 +653,10 @@ // Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN 0x00000001 -#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_BITN 0 -#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_M 0x00000001 -#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_S 0 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_S 0 //***************************************************************************** // @@ -672,10 +672,10 @@ // Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGDS_DMA_CLK_EN 0x00000100 -#define PRCM_SECDMACLKGDS_DMA_CLK_EN_BITN 8 -#define PRCM_SECDMACLKGDS_DMA_CLK_EN_M 0x00000100 -#define PRCM_SECDMACLKGDS_DMA_CLK_EN_S 8 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_S 8 // Field: [2] PKA_CLK_EN // @@ -686,10 +686,10 @@ // Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGDS_PKA_CLK_EN 0x00000004 -#define PRCM_SECDMACLKGDS_PKA_CLK_EN_BITN 2 -#define PRCM_SECDMACLKGDS_PKA_CLK_EN_M 0x00000004 -#define PRCM_SECDMACLKGDS_PKA_CLK_EN_S 2 +#define PRCM_SECDMACLKGDS_PKA_CLK_EN 0x00000004 +#define PRCM_SECDMACLKGDS_PKA_CLK_EN_BITN 2 +#define PRCM_SECDMACLKGDS_PKA_CLK_EN_M 0x00000004 +#define PRCM_SECDMACLKGDS_PKA_CLK_EN_S 2 // Field: [1] TRNG_CLK_EN // @@ -702,10 +702,10 @@ // Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGDS_TRNG_CLK_EN 0x00000002 -#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_BITN 1 -#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_M 0x00000002 -#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_S 1 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_S 1 // Field: [0] CRYPTO_CLK_EN // @@ -718,10 +718,10 @@ // Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN 0x00000001 -#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_BITN 0 -#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_M 0x00000001 -#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_S 0 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_S 0 //***************************************************************************** // @@ -737,10 +737,10 @@ // Overrides CLK_EN, GPIOCLKGS.CLK_EN and GPIOCLKGDS.CLK_EN when enabled. // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_GPIOCLKGR_AM_CLK_EN 0x00000100 -#define PRCM_GPIOCLKGR_AM_CLK_EN_BITN 8 -#define PRCM_GPIOCLKGR_AM_CLK_EN_M 0x00000100 -#define PRCM_GPIOCLKGR_AM_CLK_EN_S 8 +#define PRCM_GPIOCLKGR_AM_CLK_EN 0x00000100 +#define PRCM_GPIOCLKGR_AM_CLK_EN_BITN 8 +#define PRCM_GPIOCLKGR_AM_CLK_EN_M 0x00000100 +#define PRCM_GPIOCLKGR_AM_CLK_EN_S 8 // Field: [0] CLK_EN // @@ -751,10 +751,10 @@ // Can be forced on by AM_CLK_EN // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_GPIOCLKGR_CLK_EN 0x00000001 -#define PRCM_GPIOCLKGR_CLK_EN_BITN 0 -#define PRCM_GPIOCLKGR_CLK_EN_M 0x00000001 -#define PRCM_GPIOCLKGR_CLK_EN_S 0 +#define PRCM_GPIOCLKGR_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGR_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGR_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGR_CLK_EN_S 0 //***************************************************************************** // @@ -770,10 +770,10 @@ // Can be forced on by GPIOCLKGR.AM_CLK_EN // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_GPIOCLKGS_CLK_EN 0x00000001 -#define PRCM_GPIOCLKGS_CLK_EN_BITN 0 -#define PRCM_GPIOCLKGS_CLK_EN_M 0x00000001 -#define PRCM_GPIOCLKGS_CLK_EN_S 0 +#define PRCM_GPIOCLKGS_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGS_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGS_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGS_CLK_EN_S 0 //***************************************************************************** // @@ -789,10 +789,10 @@ // Can be forced on by GPIOCLKGR.AM_CLK_EN // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_GPIOCLKGDS_CLK_EN 0x00000001 -#define PRCM_GPIOCLKGDS_CLK_EN_BITN 0 -#define PRCM_GPIOCLKGDS_CLK_EN_M 0x00000001 -#define PRCM_GPIOCLKGDS_CLK_EN_S 0 +#define PRCM_GPIOCLKGDS_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGDS_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGDS_CLK_EN_S 0 //***************************************************************************** // @@ -815,13 +815,13 @@ // AM_GPT2 Enable clock for GPT2 in all modes // AM_GPT1 Enable clock for GPT1 in all modes // AM_GPT0 Enable clock for GPT0 in all modes -#define PRCM_GPTCLKGR_AM_CLK_EN_W 4 -#define PRCM_GPTCLKGR_AM_CLK_EN_M 0x00000F00 -#define PRCM_GPTCLKGR_AM_CLK_EN_S 8 -#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT3 0x00000800 -#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT2 0x00000400 -#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT1 0x00000200 -#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT0 0x00000100 +#define PRCM_GPTCLKGR_AM_CLK_EN_W 4 +#define PRCM_GPTCLKGR_AM_CLK_EN_M 0x00000F00 +#define PRCM_GPTCLKGR_AM_CLK_EN_S 8 +#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT3 0x00000800 +#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT2 0x00000400 +#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT1 0x00000200 +#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT0 0x00000100 // Field: [3:0] CLK_EN // @@ -839,13 +839,13 @@ // GPT2 Enable clock for GPT2 // GPT1 Enable clock for GPT1 // GPT0 Enable clock for GPT0 -#define PRCM_GPTCLKGR_CLK_EN_W 4 -#define PRCM_GPTCLKGR_CLK_EN_M 0x0000000F -#define PRCM_GPTCLKGR_CLK_EN_S 0 -#define PRCM_GPTCLKGR_CLK_EN_GPT3 0x00000008 -#define PRCM_GPTCLKGR_CLK_EN_GPT2 0x00000004 -#define PRCM_GPTCLKGR_CLK_EN_GPT1 0x00000002 -#define PRCM_GPTCLKGR_CLK_EN_GPT0 0x00000001 +#define PRCM_GPTCLKGR_CLK_EN_W 4 +#define PRCM_GPTCLKGR_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGR_CLK_EN_S 0 +#define PRCM_GPTCLKGR_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGR_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGR_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGR_CLK_EN_GPT0 0x00000001 //***************************************************************************** // @@ -868,13 +868,13 @@ // GPT2 Enable clock for GPT2 // GPT1 Enable clock for GPT1 // GPT0 Enable clock for GPT0 -#define PRCM_GPTCLKGS_CLK_EN_W 4 -#define PRCM_GPTCLKGS_CLK_EN_M 0x0000000F -#define PRCM_GPTCLKGS_CLK_EN_S 0 -#define PRCM_GPTCLKGS_CLK_EN_GPT3 0x00000008 -#define PRCM_GPTCLKGS_CLK_EN_GPT2 0x00000004 -#define PRCM_GPTCLKGS_CLK_EN_GPT1 0x00000002 -#define PRCM_GPTCLKGS_CLK_EN_GPT0 0x00000001 +#define PRCM_GPTCLKGS_CLK_EN_W 4 +#define PRCM_GPTCLKGS_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGS_CLK_EN_S 0 +#define PRCM_GPTCLKGS_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGS_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGS_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGS_CLK_EN_GPT0 0x00000001 //***************************************************************************** // @@ -897,13 +897,13 @@ // GPT2 Enable clock for GPT2 // GPT1 Enable clock for GPT1 // GPT0 Enable clock for GPT0 -#define PRCM_GPTCLKGDS_CLK_EN_W 4 -#define PRCM_GPTCLKGDS_CLK_EN_M 0x0000000F -#define PRCM_GPTCLKGDS_CLK_EN_S 0 -#define PRCM_GPTCLKGDS_CLK_EN_GPT3 0x00000008 -#define PRCM_GPTCLKGDS_CLK_EN_GPT2 0x00000004 -#define PRCM_GPTCLKGDS_CLK_EN_GPT1 0x00000002 -#define PRCM_GPTCLKGDS_CLK_EN_GPT0 0x00000001 +#define PRCM_GPTCLKGDS_CLK_EN_W 4 +#define PRCM_GPTCLKGDS_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGDS_CLK_EN_S 0 +#define PRCM_GPTCLKGDS_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGDS_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGDS_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGDS_CLK_EN_GPT0 0x00000001 //***************************************************************************** // @@ -919,10 +919,10 @@ // Overrides CLK_EN, I2CCLKGS.CLK_EN and I2CCLKGDS.CLK_EN when enabled. // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2CCLKGR_AM_CLK_EN 0x00000100 -#define PRCM_I2CCLKGR_AM_CLK_EN_BITN 8 -#define PRCM_I2CCLKGR_AM_CLK_EN_M 0x00000100 -#define PRCM_I2CCLKGR_AM_CLK_EN_S 8 +#define PRCM_I2CCLKGR_AM_CLK_EN 0x00000100 +#define PRCM_I2CCLKGR_AM_CLK_EN_BITN 8 +#define PRCM_I2CCLKGR_AM_CLK_EN_M 0x00000100 +#define PRCM_I2CCLKGR_AM_CLK_EN_S 8 // Field: [0] CLK_EN // @@ -933,10 +933,10 @@ // Can be forced on by AM_CLK_EN // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2CCLKGR_CLK_EN 0x00000001 -#define PRCM_I2CCLKGR_CLK_EN_BITN 0 -#define PRCM_I2CCLKGR_CLK_EN_M 0x00000001 -#define PRCM_I2CCLKGR_CLK_EN_S 0 +#define PRCM_I2CCLKGR_CLK_EN 0x00000001 +#define PRCM_I2CCLKGR_CLK_EN_BITN 0 +#define PRCM_I2CCLKGR_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGR_CLK_EN_S 0 //***************************************************************************** // @@ -952,10 +952,10 @@ // Can be forced on by I2CCLKGR.AM_CLK_EN // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2CCLKGS_CLK_EN 0x00000001 -#define PRCM_I2CCLKGS_CLK_EN_BITN 0 -#define PRCM_I2CCLKGS_CLK_EN_M 0x00000001 -#define PRCM_I2CCLKGS_CLK_EN_S 0 +#define PRCM_I2CCLKGS_CLK_EN 0x00000001 +#define PRCM_I2CCLKGS_CLK_EN_BITN 0 +#define PRCM_I2CCLKGS_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGS_CLK_EN_S 0 //***************************************************************************** // @@ -971,10 +971,10 @@ // Can be forced on by I2CCLKGR.AM_CLK_EN // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2CCLKGDS_CLK_EN 0x00000001 -#define PRCM_I2CCLKGDS_CLK_EN_BITN 0 -#define PRCM_I2CCLKGDS_CLK_EN_M 0x00000001 -#define PRCM_I2CCLKGDS_CLK_EN_S 0 +#define PRCM_I2CCLKGDS_CLK_EN 0x00000001 +#define PRCM_I2CCLKGDS_CLK_EN_BITN 0 +#define PRCM_I2CCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGDS_CLK_EN_S 0 //***************************************************************************** // @@ -993,11 +993,11 @@ // ENUMs: // AM_UART1 Enable clock for UART1 // AM_UART0 Enable clock for UART0 -#define PRCM_UARTCLKGR_AM_CLK_EN_W 2 -#define PRCM_UARTCLKGR_AM_CLK_EN_M 0x00000300 -#define PRCM_UARTCLKGR_AM_CLK_EN_S 8 -#define PRCM_UARTCLKGR_AM_CLK_EN_AM_UART1 0x00000200 -#define PRCM_UARTCLKGR_AM_CLK_EN_AM_UART0 0x00000100 +#define PRCM_UARTCLKGR_AM_CLK_EN_W 2 +#define PRCM_UARTCLKGR_AM_CLK_EN_M 0x00000300 +#define PRCM_UARTCLKGR_AM_CLK_EN_S 8 +#define PRCM_UARTCLKGR_AM_CLK_EN_AM_UART1 0x00000200 +#define PRCM_UARTCLKGR_AM_CLK_EN_AM_UART0 0x00000100 // Field: [1:0] CLK_EN // @@ -1011,11 +1011,11 @@ // ENUMs: // UART1 Enable clock for UART1 // UART0 Enable clock for UART0 -#define PRCM_UARTCLKGR_CLK_EN_W 2 -#define PRCM_UARTCLKGR_CLK_EN_M 0x00000003 -#define PRCM_UARTCLKGR_CLK_EN_S 0 -#define PRCM_UARTCLKGR_CLK_EN_UART1 0x00000002 -#define PRCM_UARTCLKGR_CLK_EN_UART0 0x00000001 +#define PRCM_UARTCLKGR_CLK_EN_W 2 +#define PRCM_UARTCLKGR_CLK_EN_M 0x00000003 +#define PRCM_UARTCLKGR_CLK_EN_S 0 +#define PRCM_UARTCLKGR_CLK_EN_UART1 0x00000002 +#define PRCM_UARTCLKGR_CLK_EN_UART0 0x00000001 //***************************************************************************** // @@ -1034,11 +1034,11 @@ // ENUMs: // AM_UART1 Enable clock for UART1 // AM_UART0 Enable clock for UART0 -#define PRCM_UARTCLKGS_CLK_EN_W 2 -#define PRCM_UARTCLKGS_CLK_EN_M 0x00000003 -#define PRCM_UARTCLKGS_CLK_EN_S 0 -#define PRCM_UARTCLKGS_CLK_EN_AM_UART1 0x00000002 -#define PRCM_UARTCLKGS_CLK_EN_AM_UART0 0x00000001 +#define PRCM_UARTCLKGS_CLK_EN_W 2 +#define PRCM_UARTCLKGS_CLK_EN_M 0x00000003 +#define PRCM_UARTCLKGS_CLK_EN_S 0 +#define PRCM_UARTCLKGS_CLK_EN_AM_UART1 0x00000002 +#define PRCM_UARTCLKGS_CLK_EN_AM_UART0 0x00000001 //***************************************************************************** // @@ -1057,11 +1057,11 @@ // ENUMs: // AM_UART1 Enable clock for UART1 // AM_UART0 Enable clock for UART0 -#define PRCM_UARTCLKGDS_CLK_EN_W 2 -#define PRCM_UARTCLKGDS_CLK_EN_M 0x00000003 -#define PRCM_UARTCLKGDS_CLK_EN_S 0 -#define PRCM_UARTCLKGDS_CLK_EN_AM_UART1 0x00000002 -#define PRCM_UARTCLKGDS_CLK_EN_AM_UART0 0x00000001 +#define PRCM_UARTCLKGDS_CLK_EN_W 2 +#define PRCM_UARTCLKGDS_CLK_EN_M 0x00000003 +#define PRCM_UARTCLKGDS_CLK_EN_S 0 +#define PRCM_UARTCLKGDS_CLK_EN_AM_UART1 0x00000002 +#define PRCM_UARTCLKGDS_CLK_EN_AM_UART0 0x00000001 //***************************************************************************** // @@ -1080,11 +1080,11 @@ // ENUMs: // SSI1 Enable clock for SSI1 // SSI0 Enable clock for SSI0 -#define PRCM_SSICLKGR_AM_CLK_EN_W 2 -#define PRCM_SSICLKGR_AM_CLK_EN_M 0x00000300 -#define PRCM_SSICLKGR_AM_CLK_EN_S 8 -#define PRCM_SSICLKGR_AM_CLK_EN_SSI1 0x00000200 -#define PRCM_SSICLKGR_AM_CLK_EN_SSI0 0x00000100 +#define PRCM_SSICLKGR_AM_CLK_EN_W 2 +#define PRCM_SSICLKGR_AM_CLK_EN_M 0x00000300 +#define PRCM_SSICLKGR_AM_CLK_EN_S 8 +#define PRCM_SSICLKGR_AM_CLK_EN_SSI1 0x00000200 +#define PRCM_SSICLKGR_AM_CLK_EN_SSI0 0x00000100 // Field: [1:0] CLK_EN // @@ -1098,11 +1098,11 @@ // ENUMs: // SSI1 Enable clock for SSI1 // SSI0 Enable clock for SSI0 -#define PRCM_SSICLKGR_CLK_EN_W 2 -#define PRCM_SSICLKGR_CLK_EN_M 0x00000003 -#define PRCM_SSICLKGR_CLK_EN_S 0 -#define PRCM_SSICLKGR_CLK_EN_SSI1 0x00000002 -#define PRCM_SSICLKGR_CLK_EN_SSI0 0x00000001 +#define PRCM_SSICLKGR_CLK_EN_W 2 +#define PRCM_SSICLKGR_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGR_CLK_EN_S 0 +#define PRCM_SSICLKGR_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGR_CLK_EN_SSI0 0x00000001 //***************************************************************************** // @@ -1121,11 +1121,11 @@ // ENUMs: // SSI1 Enable clock for SSI1 // SSI0 Enable clock for SSI0 -#define PRCM_SSICLKGS_CLK_EN_W 2 -#define PRCM_SSICLKGS_CLK_EN_M 0x00000003 -#define PRCM_SSICLKGS_CLK_EN_S 0 -#define PRCM_SSICLKGS_CLK_EN_SSI1 0x00000002 -#define PRCM_SSICLKGS_CLK_EN_SSI0 0x00000001 +#define PRCM_SSICLKGS_CLK_EN_W 2 +#define PRCM_SSICLKGS_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGS_CLK_EN_S 0 +#define PRCM_SSICLKGS_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGS_CLK_EN_SSI0 0x00000001 //***************************************************************************** // @@ -1144,11 +1144,11 @@ // ENUMs: // SSI1 Enable clock for SSI1 // SSI0 Enable clock for SSI0 -#define PRCM_SSICLKGDS_CLK_EN_W 2 -#define PRCM_SSICLKGDS_CLK_EN_M 0x00000003 -#define PRCM_SSICLKGDS_CLK_EN_S 0 -#define PRCM_SSICLKGDS_CLK_EN_SSI1 0x00000002 -#define PRCM_SSICLKGDS_CLK_EN_SSI0 0x00000001 +#define PRCM_SSICLKGDS_CLK_EN_W 2 +#define PRCM_SSICLKGDS_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGDS_CLK_EN_S 0 +#define PRCM_SSICLKGDS_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGDS_CLK_EN_SSI0 0x00000001 //***************************************************************************** // @@ -1165,10 +1165,10 @@ // SYSBUS clock will always run when enabled // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKGR_AM_CLK_EN 0x00000100 -#define PRCM_I2SCLKGR_AM_CLK_EN_BITN 8 -#define PRCM_I2SCLKGR_AM_CLK_EN_M 0x00000100 -#define PRCM_I2SCLKGR_AM_CLK_EN_S 8 +#define PRCM_I2SCLKGR_AM_CLK_EN 0x00000100 +#define PRCM_I2SCLKGR_AM_CLK_EN_BITN 8 +#define PRCM_I2SCLKGR_AM_CLK_EN_M 0x00000100 +#define PRCM_I2SCLKGR_AM_CLK_EN_S 8 // Field: [0] CLK_EN // @@ -1179,10 +1179,10 @@ // Can be forced on by AM_CLK_EN // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKGR_CLK_EN 0x00000001 -#define PRCM_I2SCLKGR_CLK_EN_BITN 0 -#define PRCM_I2SCLKGR_CLK_EN_M 0x00000001 -#define PRCM_I2SCLKGR_CLK_EN_S 0 +#define PRCM_I2SCLKGR_CLK_EN 0x00000001 +#define PRCM_I2SCLKGR_CLK_EN_BITN 0 +#define PRCM_I2SCLKGR_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGR_CLK_EN_S 0 //***************************************************************************** // @@ -1198,10 +1198,10 @@ // Can be forced on by I2SCLKGR.AM_CLK_EN // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKGS_CLK_EN 0x00000001 -#define PRCM_I2SCLKGS_CLK_EN_BITN 0 -#define PRCM_I2SCLKGS_CLK_EN_M 0x00000001 -#define PRCM_I2SCLKGS_CLK_EN_S 0 +#define PRCM_I2SCLKGS_CLK_EN 0x00000001 +#define PRCM_I2SCLKGS_CLK_EN_BITN 0 +#define PRCM_I2SCLKGS_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGS_CLK_EN_S 0 //***************************************************************************** // @@ -1219,10 +1219,10 @@ // Can be forced on by I2SCLKGR.AM_CLK_EN // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKGDS_CLK_EN 0x00000001 -#define PRCM_I2SCLKGDS_CLK_EN_BITN 0 -#define PRCM_I2SCLKGDS_CLK_EN_M 0x00000001 -#define PRCM_I2SCLKGDS_CLK_EN_S 0 +#define PRCM_I2SCLKGDS_CLK_EN 0x00000001 +#define PRCM_I2SCLKGDS_CLK_EN_BITN 0 +#define PRCM_I2SCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGDS_CLK_EN_S 0 //***************************************************************************** // @@ -1235,11 +1235,11 @@ // ENUMs: // DIV2 Internal. Only to be used through TI provided API. // DIV1 Internal. Only to be used through TI provided API. -#define PRCM_SYSBUSCLKDIV_RATIO_W 3 -#define PRCM_SYSBUSCLKDIV_RATIO_M 0x00000007 -#define PRCM_SYSBUSCLKDIV_RATIO_S 0 -#define PRCM_SYSBUSCLKDIV_RATIO_DIV2 0x00000001 -#define PRCM_SYSBUSCLKDIV_RATIO_DIV1 0x00000000 +#define PRCM_SYSBUSCLKDIV_RATIO_W 3 +#define PRCM_SYSBUSCLKDIV_RATIO_M 0x00000007 +#define PRCM_SYSBUSCLKDIV_RATIO_S 0 +#define PRCM_SYSBUSCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_SYSBUSCLKDIV_RATIO_DIV1 0x00000000 //***************************************************************************** // @@ -1252,12 +1252,12 @@ // ENUMs: // DIV2 Internal. Only to be used through TI provided API. // DIV1 Internal. Only to be used through TI provided API. -#define PRCM_CPUCLKDIV_RATIO 0x00000001 -#define PRCM_CPUCLKDIV_RATIO_BITN 0 -#define PRCM_CPUCLKDIV_RATIO_M 0x00000001 -#define PRCM_CPUCLKDIV_RATIO_S 0 -#define PRCM_CPUCLKDIV_RATIO_DIV2 0x00000001 -#define PRCM_CPUCLKDIV_RATIO_DIV1 0x00000000 +#define PRCM_CPUCLKDIV_RATIO 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_BITN 0 +#define PRCM_CPUCLKDIV_RATIO_M 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_S 0 +#define PRCM_CPUCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_DIV1 0x00000000 //***************************************************************************** // @@ -1277,18 +1277,18 @@ // DIV4 Internal. Only to be used through TI provided API. // DIV2 Internal. Only to be used through TI provided API. // DIV1 Internal. Only to be used through TI provided API. -#define PRCM_PERBUSCPUCLKDIV_RATIO_W 4 -#define PRCM_PERBUSCPUCLKDIV_RATIO_M 0x0000000F -#define PRCM_PERBUSCPUCLKDIV_RATIO_S 0 -#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV256 0x00000008 -#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV128 0x00000007 -#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV64 0x00000006 -#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV32 0x00000005 -#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV16 0x00000004 -#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV8 0x00000003 -#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV4 0x00000002 -#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV2 0x00000001 -#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV1 0x00000000 +#define PRCM_PERBUSCPUCLKDIV_RATIO_W 4 +#define PRCM_PERBUSCPUCLKDIV_RATIO_M 0x0000000F +#define PRCM_PERBUSCPUCLKDIV_RATIO_S 0 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV256 0x00000008 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV128 0x00000007 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV64 0x00000006 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV32 0x00000005 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV16 0x00000004 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV8 0x00000003 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV4 0x00000002 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV1 0x00000000 //***************************************************************************** // @@ -1308,18 +1308,18 @@ // DIV4 Internal. Only to be used through TI provided API. // DIV2 Internal. Only to be used through TI provided API. // DIV1 Internal. Only to be used through TI provided API. -#define PRCM_PERDMACLKDIV_RATIO_W 4 -#define PRCM_PERDMACLKDIV_RATIO_M 0x0000000F -#define PRCM_PERDMACLKDIV_RATIO_S 0 -#define PRCM_PERDMACLKDIV_RATIO_DIV256 0x00000008 -#define PRCM_PERDMACLKDIV_RATIO_DIV128 0x00000007 -#define PRCM_PERDMACLKDIV_RATIO_DIV64 0x00000006 -#define PRCM_PERDMACLKDIV_RATIO_DIV32 0x00000005 -#define PRCM_PERDMACLKDIV_RATIO_DIV16 0x00000004 -#define PRCM_PERDMACLKDIV_RATIO_DIV8 0x00000003 -#define PRCM_PERDMACLKDIV_RATIO_DIV4 0x00000002 -#define PRCM_PERDMACLKDIV_RATIO_DIV2 0x00000001 -#define PRCM_PERDMACLKDIV_RATIO_DIV1 0x00000000 +#define PRCM_PERDMACLKDIV_RATIO_W 4 +#define PRCM_PERDMACLKDIV_RATIO_M 0x0000000F +#define PRCM_PERDMACLKDIV_RATIO_S 0 +#define PRCM_PERDMACLKDIV_RATIO_DIV256 0x00000008 +#define PRCM_PERDMACLKDIV_RATIO_DIV128 0x00000007 +#define PRCM_PERDMACLKDIV_RATIO_DIV64 0x00000006 +#define PRCM_PERDMACLKDIV_RATIO_DIV32 0x00000005 +#define PRCM_PERDMACLKDIV_RATIO_DIV16 0x00000004 +#define PRCM_PERDMACLKDIV_RATIO_DIV8 0x00000003 +#define PRCM_PERDMACLKDIV_RATIO_DIV4 0x00000002 +#define PRCM_PERDMACLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_PERDMACLKDIV_RATIO_DIV1 0x00000000 //***************************************************************************** // @@ -1334,10 +1334,10 @@ // 1: Use internally generated clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SBCLKSEL_SRC 0x00000001 -#define PRCM_I2SBCLKSEL_SRC_BITN 0 -#define PRCM_I2SBCLKSEL_SRC_M 0x00000001 -#define PRCM_I2SBCLKSEL_SRC_S 0 +#define PRCM_I2SBCLKSEL_SRC 0x00000001 +#define PRCM_I2SBCLKSEL_SRC_BITN 0 +#define PRCM_I2SBCLKSEL_SRC_M 0x00000001 +#define PRCM_I2SBCLKSEL_SRC_S 0 //***************************************************************************** // @@ -1359,18 +1359,18 @@ // DIV4 Divide by 4 // DIV2 Divide by 2 // DIV1 Divide by 1 -#define PRCM_GPTCLKDIV_RATIO_W 4 -#define PRCM_GPTCLKDIV_RATIO_M 0x0000000F -#define PRCM_GPTCLKDIV_RATIO_S 0 -#define PRCM_GPTCLKDIV_RATIO_DIV256 0x00000008 -#define PRCM_GPTCLKDIV_RATIO_DIV128 0x00000007 -#define PRCM_GPTCLKDIV_RATIO_DIV64 0x00000006 -#define PRCM_GPTCLKDIV_RATIO_DIV32 0x00000005 -#define PRCM_GPTCLKDIV_RATIO_DIV16 0x00000004 -#define PRCM_GPTCLKDIV_RATIO_DIV8 0x00000003 -#define PRCM_GPTCLKDIV_RATIO_DIV4 0x00000002 -#define PRCM_GPTCLKDIV_RATIO_DIV2 0x00000001 -#define PRCM_GPTCLKDIV_RATIO_DIV1 0x00000000 +#define PRCM_GPTCLKDIV_RATIO_W 4 +#define PRCM_GPTCLKDIV_RATIO_M 0x0000000F +#define PRCM_GPTCLKDIV_RATIO_S 0 +#define PRCM_GPTCLKDIV_RATIO_DIV256 0x00000008 +#define PRCM_GPTCLKDIV_RATIO_DIV128 0x00000007 +#define PRCM_GPTCLKDIV_RATIO_DIV64 0x00000006 +#define PRCM_GPTCLKDIV_RATIO_DIV32 0x00000005 +#define PRCM_GPTCLKDIV_RATIO_DIV16 0x00000004 +#define PRCM_GPTCLKDIV_RATIO_DIV8 0x00000003 +#define PRCM_GPTCLKDIV_RATIO_DIV4 0x00000002 +#define PRCM_GPTCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_GPTCLKDIV_RATIO_DIV1 0x00000000 //***************************************************************************** // @@ -1388,10 +1388,10 @@ // negative edge. // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE 0x00000008 -#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_BITN 3 -#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M 0x00000008 -#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S 3 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE 0x00000008 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_BITN 3 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M 0x00000008 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S 3 // Field: [2:1] WCLK_PHASE // @@ -1404,9 +1404,9 @@ // 3: Reserved/Undefined // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKCTL_WCLK_PHASE_W 2 -#define PRCM_I2SCLKCTL_WCLK_PHASE_M 0x00000006 -#define PRCM_I2SCLKCTL_WCLK_PHASE_S 1 +#define PRCM_I2SCLKCTL_WCLK_PHASE_W 2 +#define PRCM_I2SCLKCTL_WCLK_PHASE_M 0x00000006 +#define PRCM_I2SCLKCTL_WCLK_PHASE_S 1 // Field: [0] EN // @@ -1415,10 +1415,10 @@ // 1: Enables the generation of MCLK, BCLK and WCLK // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKCTL_EN 0x00000001 -#define PRCM_I2SCLKCTL_EN_BITN 0 -#define PRCM_I2SCLKCTL_EN_M 0x00000001 -#define PRCM_I2SCLKCTL_EN_S 0 +#define PRCM_I2SCLKCTL_EN 0x00000001 +#define PRCM_I2SCLKCTL_EN_BITN 0 +#define PRCM_I2SCLKCTL_EN_M 0x00000001 +#define PRCM_I2SCLKCTL_EN_S 0 //***************************************************************************** // @@ -1438,9 +1438,9 @@ // the high phase. // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SMCLKDIV_MDIV_W 10 -#define PRCM_I2SMCLKDIV_MDIV_M 0x000003FF -#define PRCM_I2SMCLKDIV_MDIV_S 0 +#define PRCM_I2SMCLKDIV_MDIV_W 10 +#define PRCM_I2SMCLKDIV_MDIV_M 0x000003FF +#define PRCM_I2SMCLKDIV_MDIV_S 0 //***************************************************************************** // @@ -1462,9 +1462,9 @@ // clock is one MCUCLK period longer than the low phase. // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SBCLKDIV_BDIV_W 10 -#define PRCM_I2SBCLKDIV_BDIV_M 0x000003FF -#define PRCM_I2SBCLKDIV_BDIV_S 0 +#define PRCM_I2SBCLKDIV_BDIV_W 10 +#define PRCM_I2SBCLKDIV_BDIV_M 0x000003FF +#define PRCM_I2SBCLKDIV_BDIV_S 0 //***************************************************************************** // @@ -1493,9 +1493,9 @@ // WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz] // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SWCLKDIV_WDIV_W 16 -#define PRCM_I2SWCLKDIV_WDIV_M 0x0000FFFF -#define PRCM_I2SWCLKDIV_WDIV_S 0 +#define PRCM_I2SWCLKDIV_WDIV_W 16 +#define PRCM_I2SWCLKDIV_WDIV_M 0x0000FFFF +#define PRCM_I2SWCLKDIV_WDIV_S 0 //***************************************************************************** // @@ -1510,10 +1510,10 @@ // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not // activated while executing from flash. This means one cannot execute from // flash when using the SW reset. -#define PRCM_RESETSECDMA_DMA 0x00000100 -#define PRCM_RESETSECDMA_DMA_BITN 8 -#define PRCM_RESETSECDMA_DMA_M 0x00000100 -#define PRCM_RESETSECDMA_DMA_S 8 +#define PRCM_RESETSECDMA_DMA 0x00000100 +#define PRCM_RESETSECDMA_DMA_BITN 8 +#define PRCM_RESETSECDMA_DMA_M 0x00000100 +#define PRCM_RESETSECDMA_DMA_S 8 // Field: [2] PKA // @@ -1523,10 +1523,10 @@ // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not // activated while executing from flash. This means one cannot execute from // flash when using the SW reset. -#define PRCM_RESETSECDMA_PKA 0x00000004 -#define PRCM_RESETSECDMA_PKA_BITN 2 -#define PRCM_RESETSECDMA_PKA_M 0x00000004 -#define PRCM_RESETSECDMA_PKA_S 2 +#define PRCM_RESETSECDMA_PKA 0x00000004 +#define PRCM_RESETSECDMA_PKA_BITN 2 +#define PRCM_RESETSECDMA_PKA_M 0x00000004 +#define PRCM_RESETSECDMA_PKA_S 2 // Field: [1] TRNG // @@ -1536,10 +1536,10 @@ // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not // activated while executing from flash. This means one cannot execute from // flash when using the SW reset. -#define PRCM_RESETSECDMA_TRNG 0x00000002 -#define PRCM_RESETSECDMA_TRNG_BITN 1 -#define PRCM_RESETSECDMA_TRNG_M 0x00000002 -#define PRCM_RESETSECDMA_TRNG_S 1 +#define PRCM_RESETSECDMA_TRNG 0x00000002 +#define PRCM_RESETSECDMA_TRNG_BITN 1 +#define PRCM_RESETSECDMA_TRNG_M 0x00000002 +#define PRCM_RESETSECDMA_TRNG_S 1 // Field: [0] CRYPTO // @@ -1549,10 +1549,10 @@ // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not // activated while executing from flash. This means one cannot execute from // flash when using the SW reset. -#define PRCM_RESETSECDMA_CRYPTO 0x00000001 -#define PRCM_RESETSECDMA_CRYPTO_BITN 0 -#define PRCM_RESETSECDMA_CRYPTO_M 0x00000001 -#define PRCM_RESETSECDMA_CRYPTO_S 0 +#define PRCM_RESETSECDMA_CRYPTO 0x00000001 +#define PRCM_RESETSECDMA_CRYPTO_BITN 0 +#define PRCM_RESETSECDMA_CRYPTO_M 0x00000001 +#define PRCM_RESETSECDMA_CRYPTO_S 0 //***************************************************************************** // @@ -1570,10 +1570,10 @@ // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not // activated while executing from flash. This means one cannot execute from // flash when using the SW reset. -#define PRCM_RESETGPIO_GPIO 0x00000001 -#define PRCM_RESETGPIO_GPIO_BITN 0 -#define PRCM_RESETGPIO_GPIO_M 0x00000001 -#define PRCM_RESETGPIO_GPIO_S 0 +#define PRCM_RESETGPIO_GPIO 0x00000001 +#define PRCM_RESETGPIO_GPIO_BITN 0 +#define PRCM_RESETGPIO_GPIO_M 0x00000001 +#define PRCM_RESETGPIO_GPIO_S 0 //***************************************************************************** // @@ -1591,10 +1591,10 @@ // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not // activated while executing from flash. This means one cannot execute from // flash when using the SW reset. -#define PRCM_RESETGPT_GPT 0x00000001 -#define PRCM_RESETGPT_GPT_BITN 0 -#define PRCM_RESETGPT_GPT_M 0x00000001 -#define PRCM_RESETGPT_GPT_S 0 +#define PRCM_RESETGPT_GPT 0x00000001 +#define PRCM_RESETGPT_GPT_BITN 0 +#define PRCM_RESETGPT_GPT_M 0x00000001 +#define PRCM_RESETGPT_GPT_S 0 //***************************************************************************** // @@ -1612,10 +1612,10 @@ // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not // activated while executing from flash. This means one cannot execute from // flash when using the SW reset. -#define PRCM_RESETI2C_I2C 0x00000001 -#define PRCM_RESETI2C_I2C_BITN 0 -#define PRCM_RESETI2C_I2C_M 0x00000001 -#define PRCM_RESETI2C_I2C_S 0 +#define PRCM_RESETI2C_I2C 0x00000001 +#define PRCM_RESETI2C_I2C_BITN 0 +#define PRCM_RESETI2C_I2C_M 0x00000001 +#define PRCM_RESETI2C_I2C_S 0 //***************************************************************************** // @@ -1633,10 +1633,10 @@ // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not // activated while executing from flash. This means one cannot execute from // flash when using the SW reset. -#define PRCM_RESETUART_UART1 0x00000002 -#define PRCM_RESETUART_UART1_BITN 1 -#define PRCM_RESETUART_UART1_M 0x00000002 -#define PRCM_RESETUART_UART1_S 1 +#define PRCM_RESETUART_UART1 0x00000002 +#define PRCM_RESETUART_UART1_BITN 1 +#define PRCM_RESETUART_UART1_M 0x00000002 +#define PRCM_RESETUART_UART1_S 1 // Field: [0] UART0 // @@ -1649,10 +1649,10 @@ // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not // activated while executing from flash. This means one cannot execute from // flash when using the SW reset. -#define PRCM_RESETUART_UART0 0x00000001 -#define PRCM_RESETUART_UART0_BITN 0 -#define PRCM_RESETUART_UART0_M 0x00000001 -#define PRCM_RESETUART_UART0_S 0 +#define PRCM_RESETUART_UART0 0x00000001 +#define PRCM_RESETUART_UART0_BITN 0 +#define PRCM_RESETUART_UART0_M 0x00000001 +#define PRCM_RESETUART_UART0_S 0 //***************************************************************************** // @@ -1682,9 +1682,9 @@ // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not // activated while executing from flash. This means one cannot execute from // flash when using the SW reset. -#define PRCM_RESETSSI_SSI_W 2 -#define PRCM_RESETSSI_SSI_M 0x00000003 -#define PRCM_RESETSSI_SSI_S 0 +#define PRCM_RESETSSI_SSI_W 2 +#define PRCM_RESETSSI_SSI_M 0x00000003 +#define PRCM_RESETSSI_SSI_S 0 //***************************************************************************** // @@ -1702,10 +1702,10 @@ // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not // activated while executing from flash. This means one cannot execute from // flash when using the SW reset. -#define PRCM_RESETI2S_I2S 0x00000001 -#define PRCM_RESETI2S_I2S_BITN 0 -#define PRCM_RESETI2S_I2S_M 0x00000001 -#define PRCM_RESETI2S_I2S_S 0 +#define PRCM_RESETI2S_I2S 0x00000001 +#define PRCM_RESETI2S_I2S_BITN 0 +#define PRCM_RESETI2S_I2S_M 0x00000001 +#define PRCM_RESETI2S_I2S_S 0 //***************************************************************************** // @@ -1718,10 +1718,10 @@ // // 0: PERIPH power domain is powered down // 1: PERIPH power domain is powered up -#define PRCM_PDCTL0_PERIPH_ON 0x00000004 -#define PRCM_PDCTL0_PERIPH_ON_BITN 2 -#define PRCM_PDCTL0_PERIPH_ON_M 0x00000004 -#define PRCM_PDCTL0_PERIPH_ON_S 2 +#define PRCM_PDCTL0_PERIPH_ON 0x00000004 +#define PRCM_PDCTL0_PERIPH_ON_BITN 2 +#define PRCM_PDCTL0_PERIPH_ON_M 0x00000004 +#define PRCM_PDCTL0_PERIPH_ON_S 2 // Field: [1] SERIAL_ON // @@ -1729,20 +1729,20 @@ // // 0: SERIAL power domain is powered down // 1: SERIAL power domain is powered up -#define PRCM_PDCTL0_SERIAL_ON 0x00000002 -#define PRCM_PDCTL0_SERIAL_ON_BITN 1 -#define PRCM_PDCTL0_SERIAL_ON_M 0x00000002 -#define PRCM_PDCTL0_SERIAL_ON_S 1 +#define PRCM_PDCTL0_SERIAL_ON 0x00000002 +#define PRCM_PDCTL0_SERIAL_ON_BITN 1 +#define PRCM_PDCTL0_SERIAL_ON_M 0x00000002 +#define PRCM_PDCTL0_SERIAL_ON_S 1 // Field: [0] RFC_ON // // // 0: RFC power domain powered off if also PDCTL1.RFC_ON = 0 // 1: RFC power domain powered on -#define PRCM_PDCTL0_RFC_ON 0x00000001 -#define PRCM_PDCTL0_RFC_ON_BITN 0 -#define PRCM_PDCTL0_RFC_ON_M 0x00000001 -#define PRCM_PDCTL0_RFC_ON_S 0 +#define PRCM_PDCTL0_RFC_ON 0x00000001 +#define PRCM_PDCTL0_RFC_ON_BITN 0 +#define PRCM_PDCTL0_RFC_ON_M 0x00000001 +#define PRCM_PDCTL0_RFC_ON_S 0 //***************************************************************************** // @@ -1752,10 +1752,10 @@ // Field: [0] ON // // Alias for PDCTL0.RFC_ON -#define PRCM_PDCTL0RFC_ON 0x00000001 -#define PRCM_PDCTL0RFC_ON_BITN 0 -#define PRCM_PDCTL0RFC_ON_M 0x00000001 -#define PRCM_PDCTL0RFC_ON_S 0 +#define PRCM_PDCTL0RFC_ON 0x00000001 +#define PRCM_PDCTL0RFC_ON_BITN 0 +#define PRCM_PDCTL0RFC_ON_M 0x00000001 +#define PRCM_PDCTL0RFC_ON_S 0 //***************************************************************************** // @@ -1765,10 +1765,10 @@ // Field: [0] ON // // Alias for PDCTL0.SERIAL_ON -#define PRCM_PDCTL0SERIAL_ON 0x00000001 -#define PRCM_PDCTL0SERIAL_ON_BITN 0 -#define PRCM_PDCTL0SERIAL_ON_M 0x00000001 -#define PRCM_PDCTL0SERIAL_ON_S 0 +#define PRCM_PDCTL0SERIAL_ON 0x00000001 +#define PRCM_PDCTL0SERIAL_ON_BITN 0 +#define PRCM_PDCTL0SERIAL_ON_M 0x00000001 +#define PRCM_PDCTL0SERIAL_ON_S 0 //***************************************************************************** // @@ -1778,10 +1778,10 @@ // Field: [0] ON // // Alias for PDCTL0.PERIPH_ON -#define PRCM_PDCTL0PERIPH_ON 0x00000001 -#define PRCM_PDCTL0PERIPH_ON_BITN 0 -#define PRCM_PDCTL0PERIPH_ON_M 0x00000001 -#define PRCM_PDCTL0PERIPH_ON_S 0 +#define PRCM_PDCTL0PERIPH_ON 0x00000001 +#define PRCM_PDCTL0PERIPH_ON_BITN 0 +#define PRCM_PDCTL0PERIPH_ON_M 0x00000001 +#define PRCM_PDCTL0PERIPH_ON_S 0 //***************************************************************************** // @@ -1794,10 +1794,10 @@ // // 0: Domain may be powered down // 1: Domain powered up (guaranteed) -#define PRCM_PDSTAT0_PERIPH_ON 0x00000004 -#define PRCM_PDSTAT0_PERIPH_ON_BITN 2 -#define PRCM_PDSTAT0_PERIPH_ON_M 0x00000004 -#define PRCM_PDSTAT0_PERIPH_ON_S 2 +#define PRCM_PDSTAT0_PERIPH_ON 0x00000004 +#define PRCM_PDSTAT0_PERIPH_ON_BITN 2 +#define PRCM_PDSTAT0_PERIPH_ON_M 0x00000004 +#define PRCM_PDSTAT0_PERIPH_ON_S 2 // Field: [1] SERIAL_ON // @@ -1805,10 +1805,10 @@ // // 0: Domain may be powered down // 1: Domain powered up (guaranteed) -#define PRCM_PDSTAT0_SERIAL_ON 0x00000002 -#define PRCM_PDSTAT0_SERIAL_ON_BITN 1 -#define PRCM_PDSTAT0_SERIAL_ON_M 0x00000002 -#define PRCM_PDSTAT0_SERIAL_ON_S 1 +#define PRCM_PDSTAT0_SERIAL_ON 0x00000002 +#define PRCM_PDSTAT0_SERIAL_ON_BITN 1 +#define PRCM_PDSTAT0_SERIAL_ON_M 0x00000002 +#define PRCM_PDSTAT0_SERIAL_ON_S 1 // Field: [0] RFC_ON // @@ -1816,10 +1816,10 @@ // // 0: Domain may be powered down // 1: Domain powered up (guaranteed) -#define PRCM_PDSTAT0_RFC_ON 0x00000001 -#define PRCM_PDSTAT0_RFC_ON_BITN 0 -#define PRCM_PDSTAT0_RFC_ON_M 0x00000001 -#define PRCM_PDSTAT0_RFC_ON_S 0 +#define PRCM_PDSTAT0_RFC_ON 0x00000001 +#define PRCM_PDSTAT0_RFC_ON_BITN 0 +#define PRCM_PDSTAT0_RFC_ON_M 0x00000001 +#define PRCM_PDSTAT0_RFC_ON_S 0 //***************************************************************************** // @@ -1829,10 +1829,10 @@ // Field: [0] ON // // Alias for PDSTAT0.RFC_ON -#define PRCM_PDSTAT0RFC_ON 0x00000001 -#define PRCM_PDSTAT0RFC_ON_BITN 0 -#define PRCM_PDSTAT0RFC_ON_M 0x00000001 -#define PRCM_PDSTAT0RFC_ON_S 0 +#define PRCM_PDSTAT0RFC_ON 0x00000001 +#define PRCM_PDSTAT0RFC_ON_BITN 0 +#define PRCM_PDSTAT0RFC_ON_M 0x00000001 +#define PRCM_PDSTAT0RFC_ON_S 0 //***************************************************************************** // @@ -1842,10 +1842,10 @@ // Field: [0] ON // // Alias for PDSTAT0.SERIAL_ON -#define PRCM_PDSTAT0SERIAL_ON 0x00000001 -#define PRCM_PDSTAT0SERIAL_ON_BITN 0 -#define PRCM_PDSTAT0SERIAL_ON_M 0x00000001 -#define PRCM_PDSTAT0SERIAL_ON_S 0 +#define PRCM_PDSTAT0SERIAL_ON 0x00000001 +#define PRCM_PDSTAT0SERIAL_ON_BITN 0 +#define PRCM_PDSTAT0SERIAL_ON_M 0x00000001 +#define PRCM_PDSTAT0SERIAL_ON_S 0 //***************************************************************************** // @@ -1855,10 +1855,10 @@ // Field: [0] ON // // Alias for PDSTAT0.PERIPH_ON -#define PRCM_PDSTAT0PERIPH_ON 0x00000001 -#define PRCM_PDSTAT0PERIPH_ON_BITN 0 -#define PRCM_PDSTAT0PERIPH_ON_M 0x00000001 -#define PRCM_PDSTAT0PERIPH_ON_S 0 +#define PRCM_PDSTAT0PERIPH_ON 0x00000001 +#define PRCM_PDSTAT0PERIPH_ON_BITN 0 +#define PRCM_PDSTAT0PERIPH_ON_M 0x00000001 +#define PRCM_PDSTAT0PERIPH_ON_S 0 //***************************************************************************** // @@ -1872,19 +1872,19 @@ // 01: VIMS power domain is powered whenever the BUS power domain is powered. // 1X: Block power up of VIMS power domain at next wake up. This mode only has // effect when VIMS power domain is not powered. Used for Autonomous RF Core. -#define PRCM_PDCTL1_VIMS_MODE_W 2 -#define PRCM_PDCTL1_VIMS_MODE_M 0x00000018 -#define PRCM_PDCTL1_VIMS_MODE_S 3 +#define PRCM_PDCTL1_VIMS_MODE_W 2 +#define PRCM_PDCTL1_VIMS_MODE_M 0x00000018 +#define PRCM_PDCTL1_VIMS_MODE_S 3 // Field: [2] RFC_ON // // 0: RFC power domain powered off if also PDCTL0.RFC_ON = 0 1: RFC power // domain powered on Bit shall be used by RFC in autonomous mode but there is // no HW restrictions fom system CPU to access the bit. -#define PRCM_PDCTL1_RFC_ON 0x00000004 -#define PRCM_PDCTL1_RFC_ON_BITN 2 -#define PRCM_PDCTL1_RFC_ON_M 0x00000004 -#define PRCM_PDCTL1_RFC_ON_S 2 +#define PRCM_PDCTL1_RFC_ON 0x00000004 +#define PRCM_PDCTL1_RFC_ON_BITN 2 +#define PRCM_PDCTL1_RFC_ON_M 0x00000004 +#define PRCM_PDCTL1_RFC_ON_S 2 // Field: [1] CPU_ON // @@ -1894,10 +1894,10 @@ // 1: Initiates power-on of the CPU power domain. // // This bit is automatically set by a WIC power-on event. -#define PRCM_PDCTL1_CPU_ON 0x00000002 -#define PRCM_PDCTL1_CPU_ON_BITN 1 -#define PRCM_PDCTL1_CPU_ON_M 0x00000002 -#define PRCM_PDCTL1_CPU_ON_S 1 +#define PRCM_PDCTL1_CPU_ON 0x00000002 +#define PRCM_PDCTL1_CPU_ON_BITN 1 +#define PRCM_PDCTL1_CPU_ON_M 0x00000002 +#define PRCM_PDCTL1_CPU_ON_S 1 //***************************************************************************** // @@ -1907,10 +1907,10 @@ // Field: [0] ON // // This is an alias for PDCTL1.CPU_ON -#define PRCM_PDCTL1CPU_ON 0x00000001 -#define PRCM_PDCTL1CPU_ON_BITN 0 -#define PRCM_PDCTL1CPU_ON_M 0x00000001 -#define PRCM_PDCTL1CPU_ON_S 0 +#define PRCM_PDCTL1CPU_ON 0x00000001 +#define PRCM_PDCTL1CPU_ON_BITN 0 +#define PRCM_PDCTL1CPU_ON_M 0x00000001 +#define PRCM_PDCTL1CPU_ON_S 0 //***************************************************************************** // @@ -1920,10 +1920,10 @@ // Field: [0] ON // // This is an alias for PDCTL1.RFC_ON -#define PRCM_PDCTL1RFC_ON 0x00000001 -#define PRCM_PDCTL1RFC_ON_BITN 0 -#define PRCM_PDCTL1RFC_ON_M 0x00000001 -#define PRCM_PDCTL1RFC_ON_S 0 +#define PRCM_PDCTL1RFC_ON 0x00000001 +#define PRCM_PDCTL1RFC_ON_BITN 0 +#define PRCM_PDCTL1RFC_ON_M 0x00000001 +#define PRCM_PDCTL1RFC_ON_S 0 //***************************************************************************** // @@ -1933,9 +1933,9 @@ // Field: [1:0] MODE // // This is an alias for PDCTL1.VIMS_MODE -#define PRCM_PDCTL1VIMS_MODE_W 2 -#define PRCM_PDCTL1VIMS_MODE_M 0x00000003 -#define PRCM_PDCTL1VIMS_MODE_S 0 +#define PRCM_PDCTL1VIMS_MODE_W 2 +#define PRCM_PDCTL1VIMS_MODE_M 0x00000003 +#define PRCM_PDCTL1VIMS_MODE_S 0 //***************************************************************************** // @@ -1947,40 +1947,40 @@ // // 0: BUS domain not accessible // 1: BUS domain is currently accessible -#define PRCM_PDSTAT1_BUS_ON 0x00000010 -#define PRCM_PDSTAT1_BUS_ON_BITN 4 -#define PRCM_PDSTAT1_BUS_ON_M 0x00000010 -#define PRCM_PDSTAT1_BUS_ON_S 4 +#define PRCM_PDSTAT1_BUS_ON 0x00000010 +#define PRCM_PDSTAT1_BUS_ON_BITN 4 +#define PRCM_PDSTAT1_BUS_ON_M 0x00000010 +#define PRCM_PDSTAT1_BUS_ON_S 4 // Field: [3] VIMS_ON // // // 0: VIMS domain not accessible // 1: VIMS domain is currently accessible -#define PRCM_PDSTAT1_VIMS_ON 0x00000008 -#define PRCM_PDSTAT1_VIMS_ON_BITN 3 -#define PRCM_PDSTAT1_VIMS_ON_M 0x00000008 -#define PRCM_PDSTAT1_VIMS_ON_S 3 +#define PRCM_PDSTAT1_VIMS_ON 0x00000008 +#define PRCM_PDSTAT1_VIMS_ON_BITN 3 +#define PRCM_PDSTAT1_VIMS_ON_M 0x00000008 +#define PRCM_PDSTAT1_VIMS_ON_S 3 // Field: [2] RFC_ON // // // 0: RFC domain not accessible // 1: RFC domain is currently accessible -#define PRCM_PDSTAT1_RFC_ON 0x00000004 -#define PRCM_PDSTAT1_RFC_ON_BITN 2 -#define PRCM_PDSTAT1_RFC_ON_M 0x00000004 -#define PRCM_PDSTAT1_RFC_ON_S 2 +#define PRCM_PDSTAT1_RFC_ON 0x00000004 +#define PRCM_PDSTAT1_RFC_ON_BITN 2 +#define PRCM_PDSTAT1_RFC_ON_M 0x00000004 +#define PRCM_PDSTAT1_RFC_ON_S 2 // Field: [1] CPU_ON // // // 0: CPU and BUS domain not accessible // 1: CPU and BUS domains are both currently accessible -#define PRCM_PDSTAT1_CPU_ON 0x00000002 -#define PRCM_PDSTAT1_CPU_ON_BITN 1 -#define PRCM_PDSTAT1_CPU_ON_M 0x00000002 -#define PRCM_PDSTAT1_CPU_ON_S 1 +#define PRCM_PDSTAT1_CPU_ON 0x00000002 +#define PRCM_PDSTAT1_CPU_ON_BITN 1 +#define PRCM_PDSTAT1_CPU_ON_M 0x00000002 +#define PRCM_PDSTAT1_CPU_ON_S 1 //***************************************************************************** // @@ -1990,10 +1990,10 @@ // Field: [0] ON // // This is an alias for PDSTAT1.BUS_ON -#define PRCM_PDSTAT1BUS_ON 0x00000001 -#define PRCM_PDSTAT1BUS_ON_BITN 0 -#define PRCM_PDSTAT1BUS_ON_M 0x00000001 -#define PRCM_PDSTAT1BUS_ON_S 0 +#define PRCM_PDSTAT1BUS_ON 0x00000001 +#define PRCM_PDSTAT1BUS_ON_BITN 0 +#define PRCM_PDSTAT1BUS_ON_M 0x00000001 +#define PRCM_PDSTAT1BUS_ON_S 0 //***************************************************************************** // @@ -2003,10 +2003,10 @@ // Field: [0] ON // // This is an alias for PDSTAT1.RFC_ON -#define PRCM_PDSTAT1RFC_ON 0x00000001 -#define PRCM_PDSTAT1RFC_ON_BITN 0 -#define PRCM_PDSTAT1RFC_ON_M 0x00000001 -#define PRCM_PDSTAT1RFC_ON_S 0 +#define PRCM_PDSTAT1RFC_ON 0x00000001 +#define PRCM_PDSTAT1RFC_ON_BITN 0 +#define PRCM_PDSTAT1RFC_ON_M 0x00000001 +#define PRCM_PDSTAT1RFC_ON_S 0 //***************************************************************************** // @@ -2016,10 +2016,10 @@ // Field: [0] ON // // This is an alias for PDSTAT1.CPU_ON -#define PRCM_PDSTAT1CPU_ON 0x00000001 -#define PRCM_PDSTAT1CPU_ON_BITN 0 -#define PRCM_PDSTAT1CPU_ON_M 0x00000001 -#define PRCM_PDSTAT1CPU_ON_S 0 +#define PRCM_PDSTAT1CPU_ON 0x00000001 +#define PRCM_PDSTAT1CPU_ON_BITN 0 +#define PRCM_PDSTAT1CPU_ON_M 0x00000001 +#define PRCM_PDSTAT1CPU_ON_S 0 //***************************************************************************** // @@ -2029,10 +2029,10 @@ // Field: [0] ON // // This is an alias for PDSTAT1.VIMS_ON -#define PRCM_PDSTAT1VIMS_ON 0x00000001 -#define PRCM_PDSTAT1VIMS_ON_BITN 0 -#define PRCM_PDSTAT1VIMS_ON_M 0x00000001 -#define PRCM_PDSTAT1VIMS_ON_S 0 +#define PRCM_PDSTAT1VIMS_ON 0x00000001 +#define PRCM_PDSTAT1VIMS_ON_BITN 0 +#define PRCM_PDSTAT1VIMS_ON_M 0x00000001 +#define PRCM_PDSTAT1VIMS_ON_S 0 //***************************************************************************** // @@ -2046,9 +2046,9 @@ // to perform some tasks at its start-up. The supported functionality is // ROM-defined and may vary. See the technical reference manual for more // details. -#define PRCM_RFCBITS_READ_W 32 -#define PRCM_RFCBITS_READ_M 0xFFFFFFFF -#define PRCM_RFCBITS_READ_S 0 +#define PRCM_RFCBITS_READ_W 32 +#define PRCM_RFCBITS_READ_M 0xFFFFFFFF +#define PRCM_RFCBITS_READ_S 0 //***************************************************************************** // @@ -2069,17 +2069,17 @@ // MODE2 Select Mode 2 // MODE1 Select Mode 1 // MODE0 Select Mode 0 -#define PRCM_RFCMODESEL_CURR_W 3 -#define PRCM_RFCMODESEL_CURR_M 0x00000007 -#define PRCM_RFCMODESEL_CURR_S 0 -#define PRCM_RFCMODESEL_CURR_MODE7 0x00000007 -#define PRCM_RFCMODESEL_CURR_MODE6 0x00000006 -#define PRCM_RFCMODESEL_CURR_MODE5 0x00000005 -#define PRCM_RFCMODESEL_CURR_MODE4 0x00000004 -#define PRCM_RFCMODESEL_CURR_MODE3 0x00000003 -#define PRCM_RFCMODESEL_CURR_MODE2 0x00000002 -#define PRCM_RFCMODESEL_CURR_MODE1 0x00000001 -#define PRCM_RFCMODESEL_CURR_MODE0 0x00000000 +#define PRCM_RFCMODESEL_CURR_W 3 +#define PRCM_RFCMODESEL_CURR_M 0x00000007 +#define PRCM_RFCMODESEL_CURR_S 0 +#define PRCM_RFCMODESEL_CURR_MODE7 0x00000007 +#define PRCM_RFCMODESEL_CURR_MODE6 0x00000006 +#define PRCM_RFCMODESEL_CURR_MODE5 0x00000005 +#define PRCM_RFCMODESEL_CURR_MODE4 0x00000004 +#define PRCM_RFCMODESEL_CURR_MODE3 0x00000003 +#define PRCM_RFCMODESEL_CURR_MODE2 0x00000002 +#define PRCM_RFCMODESEL_CURR_MODE1 0x00000001 +#define PRCM_RFCMODESEL_CURR_MODE0 0x00000000 //***************************************************************************** // @@ -2098,17 +2098,17 @@ // MODE2 Mode 2 permitted // MODE1 Mode 1 permitted // MODE0 Mode 0 permitted -#define PRCM_RFCMODEHWOPT_AVAIL_W 8 -#define PRCM_RFCMODEHWOPT_AVAIL_M 0x000000FF -#define PRCM_RFCMODEHWOPT_AVAIL_S 0 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE7 0x00000080 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE6 0x00000040 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE5 0x00000020 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE4 0x00000010 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE3 0x00000008 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE2 0x00000004 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE1 0x00000002 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE0 0x00000001 +#define PRCM_RFCMODEHWOPT_AVAIL_W 8 +#define PRCM_RFCMODEHWOPT_AVAIL_M 0x000000FF +#define PRCM_RFCMODEHWOPT_AVAIL_S 0 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE7 0x00000080 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE6 0x00000040 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE5 0x00000020 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE4 0x00000010 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE3 0x00000008 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE2 0x00000004 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE1 0x00000002 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE0 0x00000001 //***************************************************************************** // @@ -2120,9 +2120,9 @@ // SW can use these bits to timestamp the application. These bits are also // available through the testtap and can thus be used by the emulator to // profile in real time. -#define PRCM_PWRPROFSTAT_VALUE_W 8 -#define PRCM_PWRPROFSTAT_VALUE_M 0x000000FF -#define PRCM_PWRPROFSTAT_VALUE_S 0 +#define PRCM_PWRPROFSTAT_VALUE_W 8 +#define PRCM_PWRPROFSTAT_VALUE_M 0x000000FF +#define PRCM_PWRPROFSTAT_VALUE_S 0 //***************************************************************************** // @@ -2135,10 +2135,10 @@ // // 0: Burst Mode enabled. // 1: Burst Mode off. -#define PRCM_MCUSRAMCFG_BM_OFF 0x00000020 -#define PRCM_MCUSRAMCFG_BM_OFF_BITN 5 -#define PRCM_MCUSRAMCFG_BM_OFF_M 0x00000020 -#define PRCM_MCUSRAMCFG_BM_OFF_S 5 +#define PRCM_MCUSRAMCFG_BM_OFF 0x00000020 +#define PRCM_MCUSRAMCFG_BM_OFF_BITN 5 +#define PRCM_MCUSRAMCFG_BM_OFF_M 0x00000020 +#define PRCM_MCUSRAMCFG_BM_OFF_S 5 // Field: [4] PAGE // @@ -2149,19 +2149,19 @@ // will select either LSB half or MSB half of the word based on PGS setting. // // This mode can be used for additional power saving -#define PRCM_MCUSRAMCFG_PAGE 0x00000010 -#define PRCM_MCUSRAMCFG_PAGE_BITN 4 -#define PRCM_MCUSRAMCFG_PAGE_M 0x00000010 -#define PRCM_MCUSRAMCFG_PAGE_S 4 +#define PRCM_MCUSRAMCFG_PAGE 0x00000010 +#define PRCM_MCUSRAMCFG_PAGE_BITN 4 +#define PRCM_MCUSRAMCFG_PAGE_M 0x00000010 +#define PRCM_MCUSRAMCFG_PAGE_S 4 // Field: [3] PGS // // 0: Select LSB half of word during Page Mode, PAGE = 1 // 1: Select MSB half of word during Page Mode, PAGE = 1 -#define PRCM_MCUSRAMCFG_PGS 0x00000008 -#define PRCM_MCUSRAMCFG_PGS_BITN 3 -#define PRCM_MCUSRAMCFG_PGS_M 0x00000008 -#define PRCM_MCUSRAMCFG_PGS_S 3 +#define PRCM_MCUSRAMCFG_PGS 0x00000008 +#define PRCM_MCUSRAMCFG_PGS_BITN 3 +#define PRCM_MCUSRAMCFG_PGS_M 0x00000008 +#define PRCM_MCUSRAMCFG_PGS_S 3 // Field: [2] BM // @@ -2173,28 +2173,28 @@ // When in Burst Mode bitline precharge and wordline firing depends on PCH_F // and PCH_L. // Burst Mode results in reduction in active power. -#define PRCM_MCUSRAMCFG_BM 0x00000004 -#define PRCM_MCUSRAMCFG_BM_BITN 2 -#define PRCM_MCUSRAMCFG_BM_M 0x00000004 -#define PRCM_MCUSRAMCFG_BM_S 2 +#define PRCM_MCUSRAMCFG_BM 0x00000004 +#define PRCM_MCUSRAMCFG_BM_BITN 2 +#define PRCM_MCUSRAMCFG_BM_M 0x00000004 +#define PRCM_MCUSRAMCFG_BM_S 2 // Field: [1] PCH_F // // 0: No bitline precharge in second half of cycle // 1: Bitline precharge in second half of cycle when in Burst Mode, BM = 1 -#define PRCM_MCUSRAMCFG_PCH_F 0x00000002 -#define PRCM_MCUSRAMCFG_PCH_F_BITN 1 -#define PRCM_MCUSRAMCFG_PCH_F_M 0x00000002 -#define PRCM_MCUSRAMCFG_PCH_F_S 1 +#define PRCM_MCUSRAMCFG_PCH_F 0x00000002 +#define PRCM_MCUSRAMCFG_PCH_F_BITN 1 +#define PRCM_MCUSRAMCFG_PCH_F_M 0x00000002 +#define PRCM_MCUSRAMCFG_PCH_F_S 1 // Field: [0] PCH_L // // 0: No bitline precharge in first half of cycle // 1: Bitline precharge in first half of cycle when in Burst Mode, BM = 1 -#define PRCM_MCUSRAMCFG_PCH_L 0x00000001 -#define PRCM_MCUSRAMCFG_PCH_L_BITN 0 -#define PRCM_MCUSRAMCFG_PCH_L_M 0x00000001 -#define PRCM_MCUSRAMCFG_PCH_L_S 0 +#define PRCM_MCUSRAMCFG_PCH_L 0x00000001 +#define PRCM_MCUSRAMCFG_PCH_L_BITN 0 +#define PRCM_MCUSRAMCFG_PCH_L_M 0x00000001 +#define PRCM_MCUSRAMCFG_PCH_L_S 0 //***************************************************************************** // @@ -2208,10 +2208,10 @@ // // Memories controlled: // CPEULLRAM -#define PRCM_RAMRETEN_RFCULL 0x00000008 -#define PRCM_RAMRETEN_RFCULL_BITN 3 -#define PRCM_RAMRETEN_RFCULL_M 0x00000008 -#define PRCM_RAMRETEN_RFCULL_S 3 +#define PRCM_RAMRETEN_RFCULL 0x00000008 +#define PRCM_RAMRETEN_RFCULL_BITN 3 +#define PRCM_RAMRETEN_RFCULL_M 0x00000008 +#define PRCM_RAMRETEN_RFCULL_S 3 // Field: [2] RFC // @@ -2219,10 +2219,10 @@ // 1: Retention for RFC SRAM enabled // // Memories controlled: CPERAM MCERAM RFERAM DSBRAM -#define PRCM_RAMRETEN_RFC 0x00000004 -#define PRCM_RAMRETEN_RFC_BITN 2 -#define PRCM_RAMRETEN_RFC_M 0x00000004 -#define PRCM_RAMRETEN_RFC_S 2 +#define PRCM_RAMRETEN_RFC 0x00000004 +#define PRCM_RAMRETEN_RFC_BITN 2 +#define PRCM_RAMRETEN_RFC_M 0x00000004 +#define PRCM_RAMRETEN_RFC_S 2 // Field: [1:0] VIMS // @@ -2242,9 +2242,9 @@ // or SPILT mode. // 10: Illegal mode // 11: No restrictions -#define PRCM_RAMRETEN_VIMS_W 2 -#define PRCM_RAMRETEN_VIMS_M 0x00000003 -#define PRCM_RAMRETEN_VIMS_S 0 +#define PRCM_RAMRETEN_VIMS_W 2 +#define PRCM_RAMRETEN_VIMS_M 0x00000003 +#define PRCM_RAMRETEN_VIMS_S 0 //***************************************************************************** // @@ -2255,73 +2255,73 @@ // // 0: Disable interrupt generation when HFSRCPEND is qualified // 1: Enable interrupt generation when HFSRCPEND is qualified -#define PRCM_OSCIMSC_HFSRCPENDIM 0x00000080 -#define PRCM_OSCIMSC_HFSRCPENDIM_BITN 7 -#define PRCM_OSCIMSC_HFSRCPENDIM_M 0x00000080 -#define PRCM_OSCIMSC_HFSRCPENDIM_S 7 +#define PRCM_OSCIMSC_HFSRCPENDIM 0x00000080 +#define PRCM_OSCIMSC_HFSRCPENDIM_BITN 7 +#define PRCM_OSCIMSC_HFSRCPENDIM_M 0x00000080 +#define PRCM_OSCIMSC_HFSRCPENDIM_S 7 // Field: [6] LFSRCDONEIM // // 0: Disable interrupt generation when LFSRCDONE is qualified // 1: Enable interrupt generation when LFSRCDONE is qualified -#define PRCM_OSCIMSC_LFSRCDONEIM 0x00000040 -#define PRCM_OSCIMSC_LFSRCDONEIM_BITN 6 -#define PRCM_OSCIMSC_LFSRCDONEIM_M 0x00000040 -#define PRCM_OSCIMSC_LFSRCDONEIM_S 6 +#define PRCM_OSCIMSC_LFSRCDONEIM 0x00000040 +#define PRCM_OSCIMSC_LFSRCDONEIM_BITN 6 +#define PRCM_OSCIMSC_LFSRCDONEIM_M 0x00000040 +#define PRCM_OSCIMSC_LFSRCDONEIM_S 6 // Field: [5] XOSCDLFIM // // 0: Disable interrupt generation when XOSCDLF is qualified // 1: Enable interrupt generation when XOSCDLF is qualified -#define PRCM_OSCIMSC_XOSCDLFIM 0x00000020 -#define PRCM_OSCIMSC_XOSCDLFIM_BITN 5 -#define PRCM_OSCIMSC_XOSCDLFIM_M 0x00000020 -#define PRCM_OSCIMSC_XOSCDLFIM_S 5 +#define PRCM_OSCIMSC_XOSCDLFIM 0x00000020 +#define PRCM_OSCIMSC_XOSCDLFIM_BITN 5 +#define PRCM_OSCIMSC_XOSCDLFIM_M 0x00000020 +#define PRCM_OSCIMSC_XOSCDLFIM_S 5 // Field: [4] XOSCLFIM // // 0: Disable interrupt generation when XOSCLF is qualified // 1: Enable interrupt generation when XOSCLF is qualified -#define PRCM_OSCIMSC_XOSCLFIM 0x00000010 -#define PRCM_OSCIMSC_XOSCLFIM_BITN 4 -#define PRCM_OSCIMSC_XOSCLFIM_M 0x00000010 -#define PRCM_OSCIMSC_XOSCLFIM_S 4 +#define PRCM_OSCIMSC_XOSCLFIM 0x00000010 +#define PRCM_OSCIMSC_XOSCLFIM_BITN 4 +#define PRCM_OSCIMSC_XOSCLFIM_M 0x00000010 +#define PRCM_OSCIMSC_XOSCLFIM_S 4 // Field: [3] RCOSCDLFIM // // 0: Disable interrupt generation when RCOSCDLF is qualified // 1: Enable interrupt generation when RCOSCDLF is qualified -#define PRCM_OSCIMSC_RCOSCDLFIM 0x00000008 -#define PRCM_OSCIMSC_RCOSCDLFIM_BITN 3 -#define PRCM_OSCIMSC_RCOSCDLFIM_M 0x00000008 -#define PRCM_OSCIMSC_RCOSCDLFIM_S 3 +#define PRCM_OSCIMSC_RCOSCDLFIM 0x00000008 +#define PRCM_OSCIMSC_RCOSCDLFIM_BITN 3 +#define PRCM_OSCIMSC_RCOSCDLFIM_M 0x00000008 +#define PRCM_OSCIMSC_RCOSCDLFIM_S 3 // Field: [2] RCOSCLFIM // // 0: Disable interrupt generation when RCOSCLF is qualified // 1: Enable interrupt generation when RCOSCLF is qualified -#define PRCM_OSCIMSC_RCOSCLFIM 0x00000004 -#define PRCM_OSCIMSC_RCOSCLFIM_BITN 2 -#define PRCM_OSCIMSC_RCOSCLFIM_M 0x00000004 -#define PRCM_OSCIMSC_RCOSCLFIM_S 2 +#define PRCM_OSCIMSC_RCOSCLFIM 0x00000004 +#define PRCM_OSCIMSC_RCOSCLFIM_BITN 2 +#define PRCM_OSCIMSC_RCOSCLFIM_M 0x00000004 +#define PRCM_OSCIMSC_RCOSCLFIM_S 2 // Field: [1] XOSCHFIM // // 0: Disable interrupt generation when XOSCHF is qualified // 1: Enable interrupt generation when XOSCHF is qualified -#define PRCM_OSCIMSC_XOSCHFIM 0x00000002 -#define PRCM_OSCIMSC_XOSCHFIM_BITN 1 -#define PRCM_OSCIMSC_XOSCHFIM_M 0x00000002 -#define PRCM_OSCIMSC_XOSCHFIM_S 1 +#define PRCM_OSCIMSC_XOSCHFIM 0x00000002 +#define PRCM_OSCIMSC_XOSCHFIM_BITN 1 +#define PRCM_OSCIMSC_XOSCHFIM_M 0x00000002 +#define PRCM_OSCIMSC_XOSCHFIM_S 1 // Field: [0] RCOSCHFIM // // 0: Disable interrupt generation when RCOSCHF is qualified // 1: Enable interrupt generation when RCOSCHF is qualified -#define PRCM_OSCIMSC_RCOSCHFIM 0x00000001 -#define PRCM_OSCIMSC_RCOSCHFIM_BITN 0 -#define PRCM_OSCIMSC_RCOSCHFIM_M 0x00000001 -#define PRCM_OSCIMSC_RCOSCHFIM_S 0 +#define PRCM_OSCIMSC_RCOSCHFIM 0x00000001 +#define PRCM_OSCIMSC_RCOSCHFIM_BITN 0 +#define PRCM_OSCIMSC_RCOSCHFIM_M 0x00000001 +#define PRCM_OSCIMSC_RCOSCHFIM_S 0 //***************************************************************************** // @@ -2338,10 +2338,10 @@ // generating an OSC Interrupt. // // Set by HW. Cleared by writing to OSCICR.HFSRCPENDC -#define PRCM_OSCRIS_HFSRCPENDRIS 0x00000080 -#define PRCM_OSCRIS_HFSRCPENDRIS_BITN 7 -#define PRCM_OSCRIS_HFSRCPENDRIS_M 0x00000080 -#define PRCM_OSCRIS_HFSRCPENDRIS_S 7 +#define PRCM_OSCRIS_HFSRCPENDRIS 0x00000080 +#define PRCM_OSCRIS_HFSRCPENDRIS_BITN 7 +#define PRCM_OSCRIS_HFSRCPENDRIS_M 0x00000080 +#define PRCM_OSCRIS_HFSRCPENDRIS_S 7 // Field: [6] LFSRCDONERIS // @@ -2353,10 +2353,10 @@ // generating an OSC Interrupt. // // Set by HW. Cleared by writing to OSCICR.LFSRCDONEC -#define PRCM_OSCRIS_LFSRCDONERIS 0x00000040 -#define PRCM_OSCRIS_LFSRCDONERIS_BITN 6 -#define PRCM_OSCRIS_LFSRCDONERIS_M 0x00000040 -#define PRCM_OSCRIS_LFSRCDONERIS_S 6 +#define PRCM_OSCRIS_LFSRCDONERIS 0x00000040 +#define PRCM_OSCRIS_LFSRCDONERIS_BITN 6 +#define PRCM_OSCRIS_LFSRCDONERIS_M 0x00000040 +#define PRCM_OSCRIS_LFSRCDONERIS_S 6 // Field: [5] XOSCDLFRIS // @@ -2368,10 +2368,10 @@ // generating an OSC Interrupt. // // Set by HW. Cleared by writing to OSCICR.XOSCDLFC -#define PRCM_OSCRIS_XOSCDLFRIS 0x00000020 -#define PRCM_OSCRIS_XOSCDLFRIS_BITN 5 -#define PRCM_OSCRIS_XOSCDLFRIS_M 0x00000020 -#define PRCM_OSCRIS_XOSCDLFRIS_S 5 +#define PRCM_OSCRIS_XOSCDLFRIS 0x00000020 +#define PRCM_OSCRIS_XOSCDLFRIS_BITN 5 +#define PRCM_OSCRIS_XOSCDLFRIS_M 0x00000020 +#define PRCM_OSCRIS_XOSCDLFRIS_S 5 // Field: [4] XOSCLFRIS // @@ -2383,10 +2383,10 @@ // generating an OSC Interrupt. // // Set by HW. Cleared by writing to OSCICR.XOSCLFC -#define PRCM_OSCRIS_XOSCLFRIS 0x00000010 -#define PRCM_OSCRIS_XOSCLFRIS_BITN 4 -#define PRCM_OSCRIS_XOSCLFRIS_M 0x00000010 -#define PRCM_OSCRIS_XOSCLFRIS_S 4 +#define PRCM_OSCRIS_XOSCLFRIS 0x00000010 +#define PRCM_OSCRIS_XOSCLFRIS_BITN 4 +#define PRCM_OSCRIS_XOSCLFRIS_M 0x00000010 +#define PRCM_OSCRIS_XOSCLFRIS_S 4 // Field: [3] RCOSCDLFRIS // @@ -2398,10 +2398,10 @@ // generating an OSC Interrupt. // // Set by HW. Cleared by writing to OSCICR.RCOSCDLFC -#define PRCM_OSCRIS_RCOSCDLFRIS 0x00000008 -#define PRCM_OSCRIS_RCOSCDLFRIS_BITN 3 -#define PRCM_OSCRIS_RCOSCDLFRIS_M 0x00000008 -#define PRCM_OSCRIS_RCOSCDLFRIS_S 3 +#define PRCM_OSCRIS_RCOSCDLFRIS 0x00000008 +#define PRCM_OSCRIS_RCOSCDLFRIS_BITN 3 +#define PRCM_OSCRIS_RCOSCDLFRIS_M 0x00000008 +#define PRCM_OSCRIS_RCOSCDLFRIS_S 3 // Field: [2] RCOSCLFRIS // @@ -2413,10 +2413,10 @@ // generating an OSC Interrupt. // // Set by HW. Cleared by writing to OSCICR.RCOSCLFC -#define PRCM_OSCRIS_RCOSCLFRIS 0x00000004 -#define PRCM_OSCRIS_RCOSCLFRIS_BITN 2 -#define PRCM_OSCRIS_RCOSCLFRIS_M 0x00000004 -#define PRCM_OSCRIS_RCOSCLFRIS_S 2 +#define PRCM_OSCRIS_RCOSCLFRIS 0x00000004 +#define PRCM_OSCRIS_RCOSCLFRIS_BITN 2 +#define PRCM_OSCRIS_RCOSCLFRIS_M 0x00000004 +#define PRCM_OSCRIS_RCOSCLFRIS_S 2 // Field: [1] XOSCHFRIS // @@ -2428,10 +2428,10 @@ // generating an OSC Interrupt. // // Set by HW. Cleared by writing to OSCICR.XOSCHFC -#define PRCM_OSCRIS_XOSCHFRIS 0x00000002 -#define PRCM_OSCRIS_XOSCHFRIS_BITN 1 -#define PRCM_OSCRIS_XOSCHFRIS_M 0x00000002 -#define PRCM_OSCRIS_XOSCHFRIS_S 1 +#define PRCM_OSCRIS_XOSCHFRIS 0x00000002 +#define PRCM_OSCRIS_XOSCHFRIS_BITN 1 +#define PRCM_OSCRIS_XOSCHFRIS_M 0x00000002 +#define PRCM_OSCRIS_XOSCHFRIS_S 1 // Field: [0] RCOSCHFRIS // @@ -2443,10 +2443,10 @@ // generating an OSC Interrupt. // // Set by HW. Cleared by writing to OSCICR.RCOSCHFC -#define PRCM_OSCRIS_RCOSCHFRIS 0x00000001 -#define PRCM_OSCRIS_RCOSCHFRIS_BITN 0 -#define PRCM_OSCRIS_RCOSCHFRIS_M 0x00000001 -#define PRCM_OSCRIS_RCOSCHFRIS_S 0 +#define PRCM_OSCRIS_RCOSCHFRIS 0x00000001 +#define PRCM_OSCRIS_RCOSCHFRIS_BITN 0 +#define PRCM_OSCRIS_RCOSCHFRIS_M 0x00000001 +#define PRCM_OSCRIS_RCOSCHFRIS_S 0 //***************************************************************************** // @@ -2457,73 +2457,72 @@ // // Writing 1 to this field clears the HFSRCPEND raw interrupt status. Writing 0 // has no effect. -#define PRCM_OSCICR_HFSRCPENDC 0x00000080 -#define PRCM_OSCICR_HFSRCPENDC_BITN 7 -#define PRCM_OSCICR_HFSRCPENDC_M 0x00000080 -#define PRCM_OSCICR_HFSRCPENDC_S 7 +#define PRCM_OSCICR_HFSRCPENDC 0x00000080 +#define PRCM_OSCICR_HFSRCPENDC_BITN 7 +#define PRCM_OSCICR_HFSRCPENDC_M 0x00000080 +#define PRCM_OSCICR_HFSRCPENDC_S 7 // Field: [6] LFSRCDONEC // // Writing 1 to this field clears the LFSRCDONE raw interrupt status. Writing 0 // has no effect. -#define PRCM_OSCICR_LFSRCDONEC 0x00000040 -#define PRCM_OSCICR_LFSRCDONEC_BITN 6 -#define PRCM_OSCICR_LFSRCDONEC_M 0x00000040 -#define PRCM_OSCICR_LFSRCDONEC_S 6 +#define PRCM_OSCICR_LFSRCDONEC 0x00000040 +#define PRCM_OSCICR_LFSRCDONEC_BITN 6 +#define PRCM_OSCICR_LFSRCDONEC_M 0x00000040 +#define PRCM_OSCICR_LFSRCDONEC_S 6 // Field: [5] XOSCDLFC // // Writing 1 to this field clears the XOSCDLF raw interrupt status. Writing 0 // has no effect. -#define PRCM_OSCICR_XOSCDLFC 0x00000020 -#define PRCM_OSCICR_XOSCDLFC_BITN 5 -#define PRCM_OSCICR_XOSCDLFC_M 0x00000020 -#define PRCM_OSCICR_XOSCDLFC_S 5 +#define PRCM_OSCICR_XOSCDLFC 0x00000020 +#define PRCM_OSCICR_XOSCDLFC_BITN 5 +#define PRCM_OSCICR_XOSCDLFC_M 0x00000020 +#define PRCM_OSCICR_XOSCDLFC_S 5 // Field: [4] XOSCLFC // // Writing 1 to this field clears the XOSCLF raw interrupt status. Writing 0 // has no effect. -#define PRCM_OSCICR_XOSCLFC 0x00000010 -#define PRCM_OSCICR_XOSCLFC_BITN 4 -#define PRCM_OSCICR_XOSCLFC_M 0x00000010 -#define PRCM_OSCICR_XOSCLFC_S 4 +#define PRCM_OSCICR_XOSCLFC 0x00000010 +#define PRCM_OSCICR_XOSCLFC_BITN 4 +#define PRCM_OSCICR_XOSCLFC_M 0x00000010 +#define PRCM_OSCICR_XOSCLFC_S 4 // Field: [3] RCOSCDLFC // // Writing 1 to this field clears the RCOSCDLF raw interrupt status. Writing 0 // has no effect. -#define PRCM_OSCICR_RCOSCDLFC 0x00000008 -#define PRCM_OSCICR_RCOSCDLFC_BITN 3 -#define PRCM_OSCICR_RCOSCDLFC_M 0x00000008 -#define PRCM_OSCICR_RCOSCDLFC_S 3 +#define PRCM_OSCICR_RCOSCDLFC 0x00000008 +#define PRCM_OSCICR_RCOSCDLFC_BITN 3 +#define PRCM_OSCICR_RCOSCDLFC_M 0x00000008 +#define PRCM_OSCICR_RCOSCDLFC_S 3 // Field: [2] RCOSCLFC // // Writing 1 to this field clears the RCOSCLF raw interrupt status. Writing 0 // has no effect. -#define PRCM_OSCICR_RCOSCLFC 0x00000004 -#define PRCM_OSCICR_RCOSCLFC_BITN 2 -#define PRCM_OSCICR_RCOSCLFC_M 0x00000004 -#define PRCM_OSCICR_RCOSCLFC_S 2 +#define PRCM_OSCICR_RCOSCLFC 0x00000004 +#define PRCM_OSCICR_RCOSCLFC_BITN 2 +#define PRCM_OSCICR_RCOSCLFC_M 0x00000004 +#define PRCM_OSCICR_RCOSCLFC_S 2 // Field: [1] XOSCHFC // // Writing 1 to this field clears the XOSCHF raw interrupt status. Writing 0 // has no effect. -#define PRCM_OSCICR_XOSCHFC 0x00000002 -#define PRCM_OSCICR_XOSCHFC_BITN 1 -#define PRCM_OSCICR_XOSCHFC_M 0x00000002 -#define PRCM_OSCICR_XOSCHFC_S 1 +#define PRCM_OSCICR_XOSCHFC 0x00000002 +#define PRCM_OSCICR_XOSCHFC_BITN 1 +#define PRCM_OSCICR_XOSCHFC_M 0x00000002 +#define PRCM_OSCICR_XOSCHFC_S 1 // Field: [0] RCOSCHFC // // Writing 1 to this field clears the RCOSCHF raw interrupt status. Writing 0 // has no effect. -#define PRCM_OSCICR_RCOSCHFC 0x00000001 -#define PRCM_OSCICR_RCOSCHFC_BITN 0 -#define PRCM_OSCICR_RCOSCHFC_M 0x00000001 -#define PRCM_OSCICR_RCOSCHFC_S 0 - +#define PRCM_OSCICR_RCOSCHFC 0x00000001 +#define PRCM_OSCICR_RCOSCHFC_BITN 0 +#define PRCM_OSCICR_RCOSCHFC_M 0x00000001 +#define PRCM_OSCICR_RCOSCHFC_S 0 #endif // __PRCM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_dbell.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_dbell.h index 262827d..744284d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_dbell.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_dbell.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_rfc_dbell_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_rfc_dbell_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_RFC_DBELL_H__ #define __HW_RFC_DBELL_H__ @@ -44,32 +44,32 @@ // //***************************************************************************** // Doorbell Command Register -#define RFC_DBELL_O_CMDR 0x00000000 +#define RFC_DBELL_O_CMDR 0x00000000 // Doorbell Command Status Register -#define RFC_DBELL_O_CMDSTA 0x00000004 +#define RFC_DBELL_O_CMDSTA 0x00000004 // Interrupt Flags From RF Hardware Modules -#define RFC_DBELL_O_RFHWIFG 0x00000008 +#define RFC_DBELL_O_RFHWIFG 0x00000008 // Interrupt Enable For RF Hardware Modules -#define RFC_DBELL_O_RFHWIEN 0x0000000C +#define RFC_DBELL_O_RFHWIEN 0x0000000C // Interrupt Flags For Command and Packet Engine Generated Interrupts -#define RFC_DBELL_O_RFCPEIFG 0x00000010 +#define RFC_DBELL_O_RFCPEIFG 0x00000010 // Interrupt Enable For Command and Packet Engine Generated Interrupts -#define RFC_DBELL_O_RFCPEIEN 0x00000014 +#define RFC_DBELL_O_RFCPEIEN 0x00000014 // Interrupt Vector Selection For Command and Packet Engine Generated // Interrupts -#define RFC_DBELL_O_RFCPEISL 0x00000018 +#define RFC_DBELL_O_RFCPEISL 0x00000018 // Doorbell Command Acknowledgement Interrupt Flag -#define RFC_DBELL_O_RFACKIFG 0x0000001C +#define RFC_DBELL_O_RFACKIFG 0x0000001C // RF Core General Purpose Output Control -#define RFC_DBELL_O_SYSGPOCTL 0x00000020 +#define RFC_DBELL_O_SYSGPOCTL 0x00000020 //***************************************************************************** // @@ -80,9 +80,9 @@ // // Command register. Raises an interrupt to the Command and packet engine (CPE) // upon write. -#define RFC_DBELL_CMDR_CMD_W 32 -#define RFC_DBELL_CMDR_CMD_M 0xFFFFFFFF -#define RFC_DBELL_CMDR_CMD_S 0 +#define RFC_DBELL_CMDR_CMD_W 32 +#define RFC_DBELL_CMDR_CMD_M 0xFFFFFFFF +#define RFC_DBELL_CMDR_CMD_S 0 //***************************************************************************** // @@ -92,9 +92,9 @@ // Field: [31:0] STAT // // Status of the last command used -#define RFC_DBELL_CMDSTA_STAT_W 32 -#define RFC_DBELL_CMDSTA_STAT_M 0xFFFFFFFF -#define RFC_DBELL_CMDSTA_STAT_S 0 +#define RFC_DBELL_CMDSTA_STAT_W 32 +#define RFC_DBELL_CMDSTA_STAT_M 0xFFFFFFFF +#define RFC_DBELL_CMDSTA_STAT_S 0 //***************************************************************************** // @@ -105,163 +105,163 @@ // // Radio timer channel 7 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH7 0x00080000 -#define RFC_DBELL_RFHWIFG_RATCH7_BITN 19 -#define RFC_DBELL_RFHWIFG_RATCH7_M 0x00080000 -#define RFC_DBELL_RFHWIFG_RATCH7_S 19 +#define RFC_DBELL_RFHWIFG_RATCH7 0x00080000 +#define RFC_DBELL_RFHWIFG_RATCH7_BITN 19 +#define RFC_DBELL_RFHWIFG_RATCH7_M 0x00080000 +#define RFC_DBELL_RFHWIFG_RATCH7_S 19 // Field: [18] RATCH6 // // Radio timer channel 6 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH6 0x00040000 -#define RFC_DBELL_RFHWIFG_RATCH6_BITN 18 -#define RFC_DBELL_RFHWIFG_RATCH6_M 0x00040000 -#define RFC_DBELL_RFHWIFG_RATCH6_S 18 +#define RFC_DBELL_RFHWIFG_RATCH6 0x00040000 +#define RFC_DBELL_RFHWIFG_RATCH6_BITN 18 +#define RFC_DBELL_RFHWIFG_RATCH6_M 0x00040000 +#define RFC_DBELL_RFHWIFG_RATCH6_S 18 // Field: [17] RATCH5 // // Radio timer channel 5 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH5 0x00020000 -#define RFC_DBELL_RFHWIFG_RATCH5_BITN 17 -#define RFC_DBELL_RFHWIFG_RATCH5_M 0x00020000 -#define RFC_DBELL_RFHWIFG_RATCH5_S 17 +#define RFC_DBELL_RFHWIFG_RATCH5 0x00020000 +#define RFC_DBELL_RFHWIFG_RATCH5_BITN 17 +#define RFC_DBELL_RFHWIFG_RATCH5_M 0x00020000 +#define RFC_DBELL_RFHWIFG_RATCH5_S 17 // Field: [16] RATCH4 // // Radio timer channel 4 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH4 0x00010000 -#define RFC_DBELL_RFHWIFG_RATCH4_BITN 16 -#define RFC_DBELL_RFHWIFG_RATCH4_M 0x00010000 -#define RFC_DBELL_RFHWIFG_RATCH4_S 16 +#define RFC_DBELL_RFHWIFG_RATCH4 0x00010000 +#define RFC_DBELL_RFHWIFG_RATCH4_BITN 16 +#define RFC_DBELL_RFHWIFG_RATCH4_M 0x00010000 +#define RFC_DBELL_RFHWIFG_RATCH4_S 16 // Field: [15] RATCH3 // // Radio timer channel 3 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH3 0x00008000 -#define RFC_DBELL_RFHWIFG_RATCH3_BITN 15 -#define RFC_DBELL_RFHWIFG_RATCH3_M 0x00008000 -#define RFC_DBELL_RFHWIFG_RATCH3_S 15 +#define RFC_DBELL_RFHWIFG_RATCH3 0x00008000 +#define RFC_DBELL_RFHWIFG_RATCH3_BITN 15 +#define RFC_DBELL_RFHWIFG_RATCH3_M 0x00008000 +#define RFC_DBELL_RFHWIFG_RATCH3_S 15 // Field: [14] RATCH2 // // Radio timer channel 2 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH2 0x00004000 -#define RFC_DBELL_RFHWIFG_RATCH2_BITN 14 -#define RFC_DBELL_RFHWIFG_RATCH2_M 0x00004000 -#define RFC_DBELL_RFHWIFG_RATCH2_S 14 +#define RFC_DBELL_RFHWIFG_RATCH2 0x00004000 +#define RFC_DBELL_RFHWIFG_RATCH2_BITN 14 +#define RFC_DBELL_RFHWIFG_RATCH2_M 0x00004000 +#define RFC_DBELL_RFHWIFG_RATCH2_S 14 // Field: [13] RATCH1 // // Radio timer channel 1 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH1 0x00002000 -#define RFC_DBELL_RFHWIFG_RATCH1_BITN 13 -#define RFC_DBELL_RFHWIFG_RATCH1_M 0x00002000 -#define RFC_DBELL_RFHWIFG_RATCH1_S 13 +#define RFC_DBELL_RFHWIFG_RATCH1 0x00002000 +#define RFC_DBELL_RFHWIFG_RATCH1_BITN 13 +#define RFC_DBELL_RFHWIFG_RATCH1_M 0x00002000 +#define RFC_DBELL_RFHWIFG_RATCH1_S 13 // Field: [12] RATCH0 // // Radio timer channel 0 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH0 0x00001000 -#define RFC_DBELL_RFHWIFG_RATCH0_BITN 12 -#define RFC_DBELL_RFHWIFG_RATCH0_M 0x00001000 -#define RFC_DBELL_RFHWIFG_RATCH0_S 12 +#define RFC_DBELL_RFHWIFG_RATCH0 0x00001000 +#define RFC_DBELL_RFHWIFG_RATCH0_BITN 12 +#define RFC_DBELL_RFHWIFG_RATCH0_M 0x00001000 +#define RFC_DBELL_RFHWIFG_RATCH0_S 12 // Field: [11] RFESOFT2 // // RF engine software defined interrupt 2 flag. Write zero to clear flag. Write // to one has no effect. -#define RFC_DBELL_RFHWIFG_RFESOFT2 0x00000800 -#define RFC_DBELL_RFHWIFG_RFESOFT2_BITN 11 -#define RFC_DBELL_RFHWIFG_RFESOFT2_M 0x00000800 -#define RFC_DBELL_RFHWIFG_RFESOFT2_S 11 +#define RFC_DBELL_RFHWIFG_RFESOFT2 0x00000800 +#define RFC_DBELL_RFHWIFG_RFESOFT2_BITN 11 +#define RFC_DBELL_RFHWIFG_RFESOFT2_M 0x00000800 +#define RFC_DBELL_RFHWIFG_RFESOFT2_S 11 // Field: [10] RFESOFT1 // // RF engine software defined interrupt 1 flag. Write zero to clear flag. Write // to one has no effect. -#define RFC_DBELL_RFHWIFG_RFESOFT1 0x00000400 -#define RFC_DBELL_RFHWIFG_RFESOFT1_BITN 10 -#define RFC_DBELL_RFHWIFG_RFESOFT1_M 0x00000400 -#define RFC_DBELL_RFHWIFG_RFESOFT1_S 10 +#define RFC_DBELL_RFHWIFG_RFESOFT1 0x00000400 +#define RFC_DBELL_RFHWIFG_RFESOFT1_BITN 10 +#define RFC_DBELL_RFHWIFG_RFESOFT1_M 0x00000400 +#define RFC_DBELL_RFHWIFG_RFESOFT1_S 10 // Field: [9] RFESOFT0 // // RF engine software defined interrupt 0 flag. Write zero to clear flag. Write // to one has no effect. -#define RFC_DBELL_RFHWIFG_RFESOFT0 0x00000200 -#define RFC_DBELL_RFHWIFG_RFESOFT0_BITN 9 -#define RFC_DBELL_RFHWIFG_RFESOFT0_M 0x00000200 -#define RFC_DBELL_RFHWIFG_RFESOFT0_S 9 +#define RFC_DBELL_RFHWIFG_RFESOFT0 0x00000200 +#define RFC_DBELL_RFHWIFG_RFESOFT0_BITN 9 +#define RFC_DBELL_RFHWIFG_RFESOFT0_M 0x00000200 +#define RFC_DBELL_RFHWIFG_RFESOFT0_S 9 // Field: [8] RFEDONE // // RF engine command done interrupt flag. Write zero to clear flag. Write to // one has no effect. -#define RFC_DBELL_RFHWIFG_RFEDONE 0x00000100 -#define RFC_DBELL_RFHWIFG_RFEDONE_BITN 8 -#define RFC_DBELL_RFHWIFG_RFEDONE_M 0x00000100 -#define RFC_DBELL_RFHWIFG_RFEDONE_S 8 +#define RFC_DBELL_RFHWIFG_RFEDONE 0x00000100 +#define RFC_DBELL_RFHWIFG_RFEDONE_BITN 8 +#define RFC_DBELL_RFHWIFG_RFEDONE_M 0x00000100 +#define RFC_DBELL_RFHWIFG_RFEDONE_S 8 // Field: [6] TRCTK // // Debug tracer system tick interrupt flag. Write zero to clear flag. Write to // one has no effect. -#define RFC_DBELL_RFHWIFG_TRCTK 0x00000040 -#define RFC_DBELL_RFHWIFG_TRCTK_BITN 6 -#define RFC_DBELL_RFHWIFG_TRCTK_M 0x00000040 -#define RFC_DBELL_RFHWIFG_TRCTK_S 6 +#define RFC_DBELL_RFHWIFG_TRCTK 0x00000040 +#define RFC_DBELL_RFHWIFG_TRCTK_BITN 6 +#define RFC_DBELL_RFHWIFG_TRCTK_M 0x00000040 +#define RFC_DBELL_RFHWIFG_TRCTK_S 6 // Field: [5] MDMSOFT // // Modem software defined interrupt flag. Write zero to clear flag. Write to // one has no effect. -#define RFC_DBELL_RFHWIFG_MDMSOFT 0x00000020 -#define RFC_DBELL_RFHWIFG_MDMSOFT_BITN 5 -#define RFC_DBELL_RFHWIFG_MDMSOFT_M 0x00000020 -#define RFC_DBELL_RFHWIFG_MDMSOFT_S 5 +#define RFC_DBELL_RFHWIFG_MDMSOFT 0x00000020 +#define RFC_DBELL_RFHWIFG_MDMSOFT_BITN 5 +#define RFC_DBELL_RFHWIFG_MDMSOFT_M 0x00000020 +#define RFC_DBELL_RFHWIFG_MDMSOFT_S 5 // Field: [4] MDMOUT // // Modem FIFO output interrupt flag. Write zero to clear flag. Write to one has // no effect. -#define RFC_DBELL_RFHWIFG_MDMOUT 0x00000010 -#define RFC_DBELL_RFHWIFG_MDMOUT_BITN 4 -#define RFC_DBELL_RFHWIFG_MDMOUT_M 0x00000010 -#define RFC_DBELL_RFHWIFG_MDMOUT_S 4 +#define RFC_DBELL_RFHWIFG_MDMOUT 0x00000010 +#define RFC_DBELL_RFHWIFG_MDMOUT_BITN 4 +#define RFC_DBELL_RFHWIFG_MDMOUT_M 0x00000010 +#define RFC_DBELL_RFHWIFG_MDMOUT_S 4 // Field: [3] MDMIN // // Modem FIFO input interrupt flag. Write zero to clear flag. Write to one has // no effect. -#define RFC_DBELL_RFHWIFG_MDMIN 0x00000008 -#define RFC_DBELL_RFHWIFG_MDMIN_BITN 3 -#define RFC_DBELL_RFHWIFG_MDMIN_M 0x00000008 -#define RFC_DBELL_RFHWIFG_MDMIN_S 3 +#define RFC_DBELL_RFHWIFG_MDMIN 0x00000008 +#define RFC_DBELL_RFHWIFG_MDMIN_BITN 3 +#define RFC_DBELL_RFHWIFG_MDMIN_M 0x00000008 +#define RFC_DBELL_RFHWIFG_MDMIN_S 3 // Field: [2] MDMDONE // // Modem command done interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_MDMDONE 0x00000004 -#define RFC_DBELL_RFHWIFG_MDMDONE_BITN 2 -#define RFC_DBELL_RFHWIFG_MDMDONE_M 0x00000004 -#define RFC_DBELL_RFHWIFG_MDMDONE_S 2 +#define RFC_DBELL_RFHWIFG_MDMDONE 0x00000004 +#define RFC_DBELL_RFHWIFG_MDMDONE_BITN 2 +#define RFC_DBELL_RFHWIFG_MDMDONE_M 0x00000004 +#define RFC_DBELL_RFHWIFG_MDMDONE_S 2 // Field: [1] FSCA // // Frequency synthesizer calibration accelerator interrupt flag. Write zero to // clear flag. Write to one has no effect. -#define RFC_DBELL_RFHWIFG_FSCA 0x00000002 -#define RFC_DBELL_RFHWIFG_FSCA_BITN 1 -#define RFC_DBELL_RFHWIFG_FSCA_M 0x00000002 -#define RFC_DBELL_RFHWIFG_FSCA_S 1 +#define RFC_DBELL_RFHWIFG_FSCA 0x00000002 +#define RFC_DBELL_RFHWIFG_FSCA_BITN 1 +#define RFC_DBELL_RFHWIFG_FSCA_M 0x00000002 +#define RFC_DBELL_RFHWIFG_FSCA_S 1 //***************************************************************************** // @@ -271,146 +271,146 @@ // Field: [19] RATCH7 // // Interrupt enable for RFHWIFG.RATCH7. -#define RFC_DBELL_RFHWIEN_RATCH7 0x00080000 -#define RFC_DBELL_RFHWIEN_RATCH7_BITN 19 -#define RFC_DBELL_RFHWIEN_RATCH7_M 0x00080000 -#define RFC_DBELL_RFHWIEN_RATCH7_S 19 +#define RFC_DBELL_RFHWIEN_RATCH7 0x00080000 +#define RFC_DBELL_RFHWIEN_RATCH7_BITN 19 +#define RFC_DBELL_RFHWIEN_RATCH7_M 0x00080000 +#define RFC_DBELL_RFHWIEN_RATCH7_S 19 // Field: [18] RATCH6 // // Interrupt enable for RFHWIFG.RATCH6. -#define RFC_DBELL_RFHWIEN_RATCH6 0x00040000 -#define RFC_DBELL_RFHWIEN_RATCH6_BITN 18 -#define RFC_DBELL_RFHWIEN_RATCH6_M 0x00040000 -#define RFC_DBELL_RFHWIEN_RATCH6_S 18 +#define RFC_DBELL_RFHWIEN_RATCH6 0x00040000 +#define RFC_DBELL_RFHWIEN_RATCH6_BITN 18 +#define RFC_DBELL_RFHWIEN_RATCH6_M 0x00040000 +#define RFC_DBELL_RFHWIEN_RATCH6_S 18 // Field: [17] RATCH5 // // Interrupt enable for RFHWIFG.RATCH5. -#define RFC_DBELL_RFHWIEN_RATCH5 0x00020000 -#define RFC_DBELL_RFHWIEN_RATCH5_BITN 17 -#define RFC_DBELL_RFHWIEN_RATCH5_M 0x00020000 -#define RFC_DBELL_RFHWIEN_RATCH5_S 17 +#define RFC_DBELL_RFHWIEN_RATCH5 0x00020000 +#define RFC_DBELL_RFHWIEN_RATCH5_BITN 17 +#define RFC_DBELL_RFHWIEN_RATCH5_M 0x00020000 +#define RFC_DBELL_RFHWIEN_RATCH5_S 17 // Field: [16] RATCH4 // // Interrupt enable for RFHWIFG.RATCH4. -#define RFC_DBELL_RFHWIEN_RATCH4 0x00010000 -#define RFC_DBELL_RFHWIEN_RATCH4_BITN 16 -#define RFC_DBELL_RFHWIEN_RATCH4_M 0x00010000 -#define RFC_DBELL_RFHWIEN_RATCH4_S 16 +#define RFC_DBELL_RFHWIEN_RATCH4 0x00010000 +#define RFC_DBELL_RFHWIEN_RATCH4_BITN 16 +#define RFC_DBELL_RFHWIEN_RATCH4_M 0x00010000 +#define RFC_DBELL_RFHWIEN_RATCH4_S 16 // Field: [15] RATCH3 // // Interrupt enable for RFHWIFG.RATCH3. -#define RFC_DBELL_RFHWIEN_RATCH3 0x00008000 -#define RFC_DBELL_RFHWIEN_RATCH3_BITN 15 -#define RFC_DBELL_RFHWIEN_RATCH3_M 0x00008000 -#define RFC_DBELL_RFHWIEN_RATCH3_S 15 +#define RFC_DBELL_RFHWIEN_RATCH3 0x00008000 +#define RFC_DBELL_RFHWIEN_RATCH3_BITN 15 +#define RFC_DBELL_RFHWIEN_RATCH3_M 0x00008000 +#define RFC_DBELL_RFHWIEN_RATCH3_S 15 // Field: [14] RATCH2 // // Interrupt enable for RFHWIFG.RATCH2. -#define RFC_DBELL_RFHWIEN_RATCH2 0x00004000 -#define RFC_DBELL_RFHWIEN_RATCH2_BITN 14 -#define RFC_DBELL_RFHWIEN_RATCH2_M 0x00004000 -#define RFC_DBELL_RFHWIEN_RATCH2_S 14 +#define RFC_DBELL_RFHWIEN_RATCH2 0x00004000 +#define RFC_DBELL_RFHWIEN_RATCH2_BITN 14 +#define RFC_DBELL_RFHWIEN_RATCH2_M 0x00004000 +#define RFC_DBELL_RFHWIEN_RATCH2_S 14 // Field: [13] RATCH1 // // Interrupt enable for RFHWIFG.RATCH1. -#define RFC_DBELL_RFHWIEN_RATCH1 0x00002000 -#define RFC_DBELL_RFHWIEN_RATCH1_BITN 13 -#define RFC_DBELL_RFHWIEN_RATCH1_M 0x00002000 -#define RFC_DBELL_RFHWIEN_RATCH1_S 13 +#define RFC_DBELL_RFHWIEN_RATCH1 0x00002000 +#define RFC_DBELL_RFHWIEN_RATCH1_BITN 13 +#define RFC_DBELL_RFHWIEN_RATCH1_M 0x00002000 +#define RFC_DBELL_RFHWIEN_RATCH1_S 13 // Field: [12] RATCH0 // // Interrupt enable for RFHWIFG.RATCH0. -#define RFC_DBELL_RFHWIEN_RATCH0 0x00001000 -#define RFC_DBELL_RFHWIEN_RATCH0_BITN 12 -#define RFC_DBELL_RFHWIEN_RATCH0_M 0x00001000 -#define RFC_DBELL_RFHWIEN_RATCH0_S 12 +#define RFC_DBELL_RFHWIEN_RATCH0 0x00001000 +#define RFC_DBELL_RFHWIEN_RATCH0_BITN 12 +#define RFC_DBELL_RFHWIEN_RATCH0_M 0x00001000 +#define RFC_DBELL_RFHWIEN_RATCH0_S 12 // Field: [11] RFESOFT2 // // Interrupt enable for RFHWIFG.RFESOFT2. -#define RFC_DBELL_RFHWIEN_RFESOFT2 0x00000800 -#define RFC_DBELL_RFHWIEN_RFESOFT2_BITN 11 -#define RFC_DBELL_RFHWIEN_RFESOFT2_M 0x00000800 -#define RFC_DBELL_RFHWIEN_RFESOFT2_S 11 +#define RFC_DBELL_RFHWIEN_RFESOFT2 0x00000800 +#define RFC_DBELL_RFHWIEN_RFESOFT2_BITN 11 +#define RFC_DBELL_RFHWIEN_RFESOFT2_M 0x00000800 +#define RFC_DBELL_RFHWIEN_RFESOFT2_S 11 // Field: [10] RFESOFT1 // // Interrupt enable for RFHWIFG.RFESOFT1. -#define RFC_DBELL_RFHWIEN_RFESOFT1 0x00000400 -#define RFC_DBELL_RFHWIEN_RFESOFT1_BITN 10 -#define RFC_DBELL_RFHWIEN_RFESOFT1_M 0x00000400 -#define RFC_DBELL_RFHWIEN_RFESOFT1_S 10 +#define RFC_DBELL_RFHWIEN_RFESOFT1 0x00000400 +#define RFC_DBELL_RFHWIEN_RFESOFT1_BITN 10 +#define RFC_DBELL_RFHWIEN_RFESOFT1_M 0x00000400 +#define RFC_DBELL_RFHWIEN_RFESOFT1_S 10 // Field: [9] RFESOFT0 // // Interrupt enable for RFHWIFG.RFESOFT0. -#define RFC_DBELL_RFHWIEN_RFESOFT0 0x00000200 -#define RFC_DBELL_RFHWIEN_RFESOFT0_BITN 9 -#define RFC_DBELL_RFHWIEN_RFESOFT0_M 0x00000200 -#define RFC_DBELL_RFHWIEN_RFESOFT0_S 9 +#define RFC_DBELL_RFHWIEN_RFESOFT0 0x00000200 +#define RFC_DBELL_RFHWIEN_RFESOFT0_BITN 9 +#define RFC_DBELL_RFHWIEN_RFESOFT0_M 0x00000200 +#define RFC_DBELL_RFHWIEN_RFESOFT0_S 9 // Field: [8] RFEDONE // // Interrupt enable for RFHWIFG.RFEDONE. -#define RFC_DBELL_RFHWIEN_RFEDONE 0x00000100 -#define RFC_DBELL_RFHWIEN_RFEDONE_BITN 8 -#define RFC_DBELL_RFHWIEN_RFEDONE_M 0x00000100 -#define RFC_DBELL_RFHWIEN_RFEDONE_S 8 +#define RFC_DBELL_RFHWIEN_RFEDONE 0x00000100 +#define RFC_DBELL_RFHWIEN_RFEDONE_BITN 8 +#define RFC_DBELL_RFHWIEN_RFEDONE_M 0x00000100 +#define RFC_DBELL_RFHWIEN_RFEDONE_S 8 // Field: [6] TRCTK // // Interrupt enable for RFHWIFG.TRCTK. -#define RFC_DBELL_RFHWIEN_TRCTK 0x00000040 -#define RFC_DBELL_RFHWIEN_TRCTK_BITN 6 -#define RFC_DBELL_RFHWIEN_TRCTK_M 0x00000040 -#define RFC_DBELL_RFHWIEN_TRCTK_S 6 +#define RFC_DBELL_RFHWIEN_TRCTK 0x00000040 +#define RFC_DBELL_RFHWIEN_TRCTK_BITN 6 +#define RFC_DBELL_RFHWIEN_TRCTK_M 0x00000040 +#define RFC_DBELL_RFHWIEN_TRCTK_S 6 // Field: [5] MDMSOFT // // Interrupt enable for RFHWIFG.MDMSOFT. -#define RFC_DBELL_RFHWIEN_MDMSOFT 0x00000020 -#define RFC_DBELL_RFHWIEN_MDMSOFT_BITN 5 -#define RFC_DBELL_RFHWIEN_MDMSOFT_M 0x00000020 -#define RFC_DBELL_RFHWIEN_MDMSOFT_S 5 +#define RFC_DBELL_RFHWIEN_MDMSOFT 0x00000020 +#define RFC_DBELL_RFHWIEN_MDMSOFT_BITN 5 +#define RFC_DBELL_RFHWIEN_MDMSOFT_M 0x00000020 +#define RFC_DBELL_RFHWIEN_MDMSOFT_S 5 // Field: [4] MDMOUT // // Interrupt enable for RFHWIFG.MDMOUT. -#define RFC_DBELL_RFHWIEN_MDMOUT 0x00000010 -#define RFC_DBELL_RFHWIEN_MDMOUT_BITN 4 -#define RFC_DBELL_RFHWIEN_MDMOUT_M 0x00000010 -#define RFC_DBELL_RFHWIEN_MDMOUT_S 4 +#define RFC_DBELL_RFHWIEN_MDMOUT 0x00000010 +#define RFC_DBELL_RFHWIEN_MDMOUT_BITN 4 +#define RFC_DBELL_RFHWIEN_MDMOUT_M 0x00000010 +#define RFC_DBELL_RFHWIEN_MDMOUT_S 4 // Field: [3] MDMIN // // Interrupt enable for RFHWIFG.MDMIN. -#define RFC_DBELL_RFHWIEN_MDMIN 0x00000008 -#define RFC_DBELL_RFHWIEN_MDMIN_BITN 3 -#define RFC_DBELL_RFHWIEN_MDMIN_M 0x00000008 -#define RFC_DBELL_RFHWIEN_MDMIN_S 3 +#define RFC_DBELL_RFHWIEN_MDMIN 0x00000008 +#define RFC_DBELL_RFHWIEN_MDMIN_BITN 3 +#define RFC_DBELL_RFHWIEN_MDMIN_M 0x00000008 +#define RFC_DBELL_RFHWIEN_MDMIN_S 3 // Field: [2] MDMDONE // // Interrupt enable for RFHWIFG.MDMDONE. -#define RFC_DBELL_RFHWIEN_MDMDONE 0x00000004 -#define RFC_DBELL_RFHWIEN_MDMDONE_BITN 2 -#define RFC_DBELL_RFHWIEN_MDMDONE_M 0x00000004 -#define RFC_DBELL_RFHWIEN_MDMDONE_S 2 +#define RFC_DBELL_RFHWIEN_MDMDONE 0x00000004 +#define RFC_DBELL_RFHWIEN_MDMDONE_BITN 2 +#define RFC_DBELL_RFHWIEN_MDMDONE_M 0x00000004 +#define RFC_DBELL_RFHWIEN_MDMDONE_S 2 // Field: [1] FSCA // // Interrupt enable for RFHWIFG.FSCA. -#define RFC_DBELL_RFHWIEN_FSCA 0x00000002 -#define RFC_DBELL_RFHWIEN_FSCA_BITN 1 -#define RFC_DBELL_RFHWIEN_FSCA_M 0x00000002 -#define RFC_DBELL_RFHWIEN_FSCA_S 1 +#define RFC_DBELL_RFHWIEN_FSCA 0x00000002 +#define RFC_DBELL_RFHWIEN_FSCA_BITN 1 +#define RFC_DBELL_RFHWIEN_FSCA_M 0x00000002 +#define RFC_DBELL_RFHWIEN_FSCA_S 1 //***************************************************************************** // @@ -423,82 +423,82 @@ // unexpected error. A reset of the CPE is needed. This can be done by // switching the RF Core power domain off and on in PRCM:PDCTL1RFC. Write zero // to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR 0x80000000 -#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_BITN 31 -#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_M 0x80000000 -#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_S 31 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_S 31 // Field: [30] BOOT_DONE // // Interrupt flag 30. The command and packet engine (CPE) boot is finished. // Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_BOOT_DONE 0x40000000 -#define RFC_DBELL_RFCPEIFG_BOOT_DONE_BITN 30 -#define RFC_DBELL_RFCPEIFG_BOOT_DONE_M 0x40000000 -#define RFC_DBELL_RFCPEIFG_BOOT_DONE_S 30 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_S 30 // Field: [29] MODULES_UNLOCKED // // Interrupt flag 29. As part of command and packet engine (CPE) boot process, // it has opened access to RF Core modules and memories. Write zero to clear // flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED 0x20000000 -#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_BITN 29 -#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_M 0x20000000 -#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_S 29 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_S 29 // Field: [28] SYNTH_NO_LOCK // // Interrupt flag 28. The phase-locked loop in frequency synthesizer has // reported loss of lock. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK 0x10000000 -#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_BITN 28 -#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_M 0x10000000 -#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_S 28 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_S 28 // Field: [27] IRQ27 // // Interrupt flag 27. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_IRQ27 0x08000000 -#define RFC_DBELL_RFCPEIFG_IRQ27_BITN 27 -#define RFC_DBELL_RFCPEIFG_IRQ27_M 0x08000000 -#define RFC_DBELL_RFCPEIFG_IRQ27_S 27 +#define RFC_DBELL_RFCPEIFG_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEIFG_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEIFG_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEIFG_IRQ27_S 27 // Field: [26] RX_ABORTED // // Interrupt flag 26. Packet reception stopped before packet was done. Write // zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_ABORTED 0x04000000 -#define RFC_DBELL_RFCPEIFG_RX_ABORTED_BITN 26 -#define RFC_DBELL_RFCPEIFG_RX_ABORTED_M 0x04000000 -#define RFC_DBELL_RFCPEIFG_RX_ABORTED_S 26 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_S 26 // Field: [25] RX_N_DATA_WRITTEN // // Interrupt flag 25. Specified number of bytes written to partial read Rx // buffer. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN 0x02000000 -#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_BITN 25 -#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_M 0x02000000 -#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_S 25 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_S 25 // Field: [24] RX_DATA_WRITTEN // // Interrupt flag 24. Data written to partial read Rx buffer. Write zero to // clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN 0x01000000 -#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_BITN 24 -#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_M 0x01000000 -#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_S 24 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_S 24 // Field: [23] RX_ENTRY_DONE // // Interrupt flag 23. Rx queue data entry changing state to finished. Write // zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE 0x00800000 -#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_BITN 23 -#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_M 0x00800000 -#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_S 23 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_S 23 // Field: [22] RX_BUF_FULL // @@ -506,195 +506,195 @@ // Packet received that did not fit in the Rx queue. IEEE 802.15.4 mode: Frame // received that did not fit in the Rx queue. Write zero to clear flag. Write // to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL 0x00400000 -#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_BITN 22 -#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_M 0x00400000 -#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_S 22 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_S 22 // Field: [21] RX_CTRL_ACK // // Interrupt flag 21. BLE mode only: LL control packet received with CRC OK, // not to be ignored, then acknowledgement sent. Write zero to clear flag. // Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK 0x00200000 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_BITN 21 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_M 0x00200000 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_S 21 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_S 21 // Field: [20] RX_CTRL // // Interrupt flag 20. BLE mode only: LL control packet received with CRC OK, // not to be ignored. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_CTRL 0x00100000 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_BITN 20 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_M 0x00100000 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_S 20 +#define RFC_DBELL_RFCPEIFG_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_S 20 // Field: [19] RX_EMPTY // // Interrupt flag 19. BLE mode only: Packet received with CRC OK, not to be // ignored, no payload. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_EMPTY 0x00080000 -#define RFC_DBELL_RFCPEIFG_RX_EMPTY_BITN 19 -#define RFC_DBELL_RFCPEIFG_RX_EMPTY_M 0x00080000 -#define RFC_DBELL_RFCPEIFG_RX_EMPTY_S 19 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_S 19 // Field: [18] RX_IGNORED // // Interrupt flag 18. Packet received, but can be ignored. BLE mode: Packet // received with CRC OK, but to be ignored. IEEE 802.15.4 mode: Frame received // with ignore flag set. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_IGNORED 0x00040000 -#define RFC_DBELL_RFCPEIFG_RX_IGNORED_BITN 18 -#define RFC_DBELL_RFCPEIFG_RX_IGNORED_M 0x00040000 -#define RFC_DBELL_RFCPEIFG_RX_IGNORED_S 18 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_S 18 // Field: [17] RX_NOK // // Interrupt flag 17. Packet received with CRC error. BLE mode: Packet received // with CRC error. IEEE 802.15.4 mode: Frame received with CRC error. Write // zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_NOK 0x00020000 -#define RFC_DBELL_RFCPEIFG_RX_NOK_BITN 17 -#define RFC_DBELL_RFCPEIFG_RX_NOK_M 0x00020000 -#define RFC_DBELL_RFCPEIFG_RX_NOK_S 17 +#define RFC_DBELL_RFCPEIFG_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEIFG_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEIFG_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEIFG_RX_NOK_S 17 // Field: [16] RX_OK // // Interrupt flag 16. Packet received correctly. BLE mode: Packet received with // CRC OK, payload, and not to be ignored. IEEE 802.15.4 mode: Frame received // with CRC OK. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_OK 0x00010000 -#define RFC_DBELL_RFCPEIFG_RX_OK_BITN 16 -#define RFC_DBELL_RFCPEIFG_RX_OK_M 0x00010000 -#define RFC_DBELL_RFCPEIFG_RX_OK_S 16 +#define RFC_DBELL_RFCPEIFG_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEIFG_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEIFG_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEIFG_RX_OK_S 16 // Field: [15] IRQ15 // // Interrupt flag 15. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_IRQ15 0x00008000 -#define RFC_DBELL_RFCPEIFG_IRQ15_BITN 15 -#define RFC_DBELL_RFCPEIFG_IRQ15_M 0x00008000 -#define RFC_DBELL_RFCPEIFG_IRQ15_S 15 +#define RFC_DBELL_RFCPEIFG_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEIFG_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEIFG_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEIFG_IRQ15_S 15 // Field: [14] IRQ14 // // Interrupt flag 14. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_IRQ14 0x00004000 -#define RFC_DBELL_RFCPEIFG_IRQ14_BITN 14 -#define RFC_DBELL_RFCPEIFG_IRQ14_M 0x00004000 -#define RFC_DBELL_RFCPEIFG_IRQ14_S 14 +#define RFC_DBELL_RFCPEIFG_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEIFG_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEIFG_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEIFG_IRQ14_S 14 // Field: [13] FG_COMMAND_STARTED // // Interrupt flag 13. IEEE 802.15.4 mode only: A foreground radio operation // command has gone into active state. -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED 0x00002000 -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED_BITN 13 -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED_M 0x00002000 -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED_S 13 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED 0x00002000 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED_BITN 13 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED_M 0x00002000 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED_S 13 // Field: [12] COMMAND_STARTED // // Interrupt flag 12. A radio operation command has gone into active state. -#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED 0x00001000 -#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED_BITN 12 -#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED_M 0x00001000 -#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED_S 12 +#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED 0x00001000 +#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED_BITN 12 +#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED_M 0x00001000 +#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED_S 12 // Field: [11] TX_BUFFER_CHANGED // // Interrupt flag 11. BLE mode only: A buffer change is complete after // CMD_BLE_ADV_PAYLOAD. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED 0x00000800 -#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_BITN 11 -#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_M 0x00000800 -#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_S 11 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_S 11 // Field: [10] TX_ENTRY_DONE // // Interrupt flag 10. Tx queue data entry state changed to finished. Write zero // to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE 0x00000400 -#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_BITN 10 -#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_M 0x00000400 -#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_S 10 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_S 10 // Field: [9] TX_RETRANS // // Interrupt flag 9. BLE mode only: Packet retransmitted. Write zero to clear // flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_RETRANS 0x00000200 -#define RFC_DBELL_RFCPEIFG_TX_RETRANS_BITN 9 -#define RFC_DBELL_RFCPEIFG_TX_RETRANS_M 0x00000200 -#define RFC_DBELL_RFCPEIFG_TX_RETRANS_S 9 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_S 9 // Field: [8] TX_CTRL_ACK_ACK // // Interrupt flag 8. BLE mode only: Acknowledgement received on a transmitted // LL control packet, and acknowledgement transmitted for that packet. Write // zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK 0x00000100 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_BITN 8 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_M 0x00000100 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_S 8 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_S 8 // Field: [7] TX_CTRL_ACK // // Interrupt flag 7. BLE mode: Acknowledgement received on a transmitted LL // control packet. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK 0x00000080 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_BITN 7 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_M 0x00000080 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_S 7 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_S 7 // Field: [6] TX_CTRL // // Interrupt flag 6. BLE mode: Transmitted LL control packet. Write zero to // clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_CTRL 0x00000040 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_BITN 6 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_M 0x00000040 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_S 6 +#define RFC_DBELL_RFCPEIFG_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_S 6 // Field: [5] TX_ACK // // Interrupt flag 5. BLE mode: Acknowledgement received on a transmitted // packet. IEEE 802.15.4 mode: Transmitted automatic ACK frame. Write zero to // clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_ACK 0x00000020 -#define RFC_DBELL_RFCPEIFG_TX_ACK_BITN 5 -#define RFC_DBELL_RFCPEIFG_TX_ACK_M 0x00000020 -#define RFC_DBELL_RFCPEIFG_TX_ACK_S 5 +#define RFC_DBELL_RFCPEIFG_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEIFG_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEIFG_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEIFG_TX_ACK_S 5 // Field: [4] TX_DONE // // Interrupt flag 4. Packet transmitted. (BLE mode: A packet has been // transmitted.) (IEEE 802.15.4 mode: A frame has been transmitted). Write zero // to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_DONE 0x00000010 -#define RFC_DBELL_RFCPEIFG_TX_DONE_BITN 4 -#define RFC_DBELL_RFCPEIFG_TX_DONE_M 0x00000010 -#define RFC_DBELL_RFCPEIFG_TX_DONE_S 4 +#define RFC_DBELL_RFCPEIFG_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEIFG_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEIFG_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEIFG_TX_DONE_S 4 // Field: [3] LAST_FG_COMMAND_DONE // // Interrupt flag 3. IEEE 802.15.4 mode only: The last foreground radio // operation command in a chain of commands has finished. Write zero to clear // flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE 0x00000008 -#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_BITN 3 -#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M 0x00000008 -#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_S 3 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_S 3 // Field: [2] FG_COMMAND_DONE // // Interrupt flag 2. IEEE 802.15.4 mode only: A foreground radio operation // command has finished. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE 0x00000004 -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_BITN 2 -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_M 0x00000004 -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_S 2 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_S 2 // Field: [1] LAST_COMMAND_DONE // @@ -702,20 +702,20 @@ // has finished. (IEEE 802.15.4 mode: The last background level radio operation // command in a chain of commands has finished.) Write zero to clear flag. // Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE 0x00000002 -#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_BITN 1 -#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M 0x00000002 -#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_S 1 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_S 1 // Field: [0] COMMAND_DONE // // Interrupt flag 0. A radio operation has finished. (IEEE 802.15.4 mode: A // background level radio operation command has finished.) Write zero to clear // flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_COMMAND_DONE 0x00000001 -#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_BITN 0 -#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_M 0x00000001 -#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_S 0 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_S 0 //***************************************************************************** // @@ -725,258 +725,258 @@ // Field: [31] INTERNAL_ERROR // // Interrupt enable for RFCPEIFG.INTERNAL_ERROR. -#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR 0x80000000 -#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_BITN 31 -#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_M 0x80000000 -#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_S 31 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_S 31 // Field: [30] BOOT_DONE // // Interrupt enable for RFCPEIFG.BOOT_DONE. -#define RFC_DBELL_RFCPEIEN_BOOT_DONE 0x40000000 -#define RFC_DBELL_RFCPEIEN_BOOT_DONE_BITN 30 -#define RFC_DBELL_RFCPEIEN_BOOT_DONE_M 0x40000000 -#define RFC_DBELL_RFCPEIEN_BOOT_DONE_S 30 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_S 30 // Field: [29] MODULES_UNLOCKED // // Interrupt enable for RFCPEIFG.MODULES_UNLOCKED. -#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED 0x20000000 -#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_BITN 29 -#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_M 0x20000000 -#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_S 29 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_S 29 // Field: [28] SYNTH_NO_LOCK // // Interrupt enable for RFCPEIFG.SYNTH_NO_LOCK. -#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK 0x10000000 -#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_BITN 28 -#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_M 0x10000000 -#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_S 28 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_S 28 // Field: [27] IRQ27 // // Interrupt enable for RFCPEIFG.IRQ27. -#define RFC_DBELL_RFCPEIEN_IRQ27 0x08000000 -#define RFC_DBELL_RFCPEIEN_IRQ27_BITN 27 -#define RFC_DBELL_RFCPEIEN_IRQ27_M 0x08000000 -#define RFC_DBELL_RFCPEIEN_IRQ27_S 27 +#define RFC_DBELL_RFCPEIEN_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEIEN_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEIEN_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEIEN_IRQ27_S 27 // Field: [26] RX_ABORTED // // Interrupt enable for RFCPEIFG.RX_ABORTED. -#define RFC_DBELL_RFCPEIEN_RX_ABORTED 0x04000000 -#define RFC_DBELL_RFCPEIEN_RX_ABORTED_BITN 26 -#define RFC_DBELL_RFCPEIEN_RX_ABORTED_M 0x04000000 -#define RFC_DBELL_RFCPEIEN_RX_ABORTED_S 26 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_S 26 // Field: [25] RX_N_DATA_WRITTEN // // Interrupt enable for RFCPEIFG.RX_N_DATA_WRITTEN. -#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN 0x02000000 -#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_BITN 25 -#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_M 0x02000000 -#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_S 25 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_S 25 // Field: [24] RX_DATA_WRITTEN // // Interrupt enable for RFCPEIFG.RX_DATA_WRITTEN. -#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN 0x01000000 -#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_BITN 24 -#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_M 0x01000000 -#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_S 24 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_S 24 // Field: [23] RX_ENTRY_DONE // // Interrupt enable for RFCPEIFG.RX_ENTRY_DONE. -#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE 0x00800000 -#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_BITN 23 -#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_M 0x00800000 -#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_S 23 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_S 23 // Field: [22] RX_BUF_FULL // // Interrupt enable for RFCPEIFG.RX_BUF_FULL. -#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL 0x00400000 -#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_BITN 22 -#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_M 0x00400000 -#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_S 22 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_S 22 // Field: [21] RX_CTRL_ACK // // Interrupt enable for RFCPEIFG.RX_CTRL_ACK. -#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK 0x00200000 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_BITN 21 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_M 0x00200000 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_S 21 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_S 21 // Field: [20] RX_CTRL // // Interrupt enable for RFCPEIFG.RX_CTRL. -#define RFC_DBELL_RFCPEIEN_RX_CTRL 0x00100000 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_BITN 20 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_M 0x00100000 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_S 20 +#define RFC_DBELL_RFCPEIEN_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_S 20 // Field: [19] RX_EMPTY // // Interrupt enable for RFCPEIFG.RX_EMPTY. -#define RFC_DBELL_RFCPEIEN_RX_EMPTY 0x00080000 -#define RFC_DBELL_RFCPEIEN_RX_EMPTY_BITN 19 -#define RFC_DBELL_RFCPEIEN_RX_EMPTY_M 0x00080000 -#define RFC_DBELL_RFCPEIEN_RX_EMPTY_S 19 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_S 19 // Field: [18] RX_IGNORED // // Interrupt enable for RFCPEIFG.RX_IGNORED. -#define RFC_DBELL_RFCPEIEN_RX_IGNORED 0x00040000 -#define RFC_DBELL_RFCPEIEN_RX_IGNORED_BITN 18 -#define RFC_DBELL_RFCPEIEN_RX_IGNORED_M 0x00040000 -#define RFC_DBELL_RFCPEIEN_RX_IGNORED_S 18 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_S 18 // Field: [17] RX_NOK // // Interrupt enable for RFCPEIFG.RX_NOK. -#define RFC_DBELL_RFCPEIEN_RX_NOK 0x00020000 -#define RFC_DBELL_RFCPEIEN_RX_NOK_BITN 17 -#define RFC_DBELL_RFCPEIEN_RX_NOK_M 0x00020000 -#define RFC_DBELL_RFCPEIEN_RX_NOK_S 17 +#define RFC_DBELL_RFCPEIEN_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEIEN_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEIEN_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEIEN_RX_NOK_S 17 // Field: [16] RX_OK // // Interrupt enable for RFCPEIFG.RX_OK. -#define RFC_DBELL_RFCPEIEN_RX_OK 0x00010000 -#define RFC_DBELL_RFCPEIEN_RX_OK_BITN 16 -#define RFC_DBELL_RFCPEIEN_RX_OK_M 0x00010000 -#define RFC_DBELL_RFCPEIEN_RX_OK_S 16 +#define RFC_DBELL_RFCPEIEN_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEIEN_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEIEN_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEIEN_RX_OK_S 16 // Field: [15] IRQ15 // // Interrupt enable for RFCPEIFG.IRQ15. -#define RFC_DBELL_RFCPEIEN_IRQ15 0x00008000 -#define RFC_DBELL_RFCPEIEN_IRQ15_BITN 15 -#define RFC_DBELL_RFCPEIEN_IRQ15_M 0x00008000 -#define RFC_DBELL_RFCPEIEN_IRQ15_S 15 +#define RFC_DBELL_RFCPEIEN_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEIEN_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEIEN_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEIEN_IRQ15_S 15 // Field: [14] IRQ14 // // Interrupt enable for RFCPEIFG.IRQ14. -#define RFC_DBELL_RFCPEIEN_IRQ14 0x00004000 -#define RFC_DBELL_RFCPEIEN_IRQ14_BITN 14 -#define RFC_DBELL_RFCPEIEN_IRQ14_M 0x00004000 -#define RFC_DBELL_RFCPEIEN_IRQ14_S 14 +#define RFC_DBELL_RFCPEIEN_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEIEN_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEIEN_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEIEN_IRQ14_S 14 // Field: [13] FG_COMMAND_STARTED // // Interrupt enable for RFCPEIFG.FG_COMMAND_STARTED. -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED 0x00002000 -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED_BITN 13 -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED_M 0x00002000 -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED_S 13 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED 0x00002000 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED_BITN 13 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED_M 0x00002000 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED_S 13 // Field: [12] COMMAND_STARTED // // Interrupt enable for RFCPEIFG.COMMAND_STARTED. -#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED 0x00001000 -#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED_BITN 12 -#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED_M 0x00001000 -#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED_S 12 +#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED 0x00001000 +#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED_BITN 12 +#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED_M 0x00001000 +#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED_S 12 // Field: [11] TX_BUFFER_CHANGED // // Interrupt enable for RFCPEIFG.TX_BUFFER_CHANGED. -#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED 0x00000800 -#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_BITN 11 -#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_M 0x00000800 -#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_S 11 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_S 11 // Field: [10] TX_ENTRY_DONE // // Interrupt enable for RFCPEIFG.TX_ENTRY_DONE. -#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE 0x00000400 -#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_BITN 10 -#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_M 0x00000400 -#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_S 10 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_S 10 // Field: [9] TX_RETRANS // // Interrupt enable for RFCPEIFG.TX_RETRANS. -#define RFC_DBELL_RFCPEIEN_TX_RETRANS 0x00000200 -#define RFC_DBELL_RFCPEIEN_TX_RETRANS_BITN 9 -#define RFC_DBELL_RFCPEIEN_TX_RETRANS_M 0x00000200 -#define RFC_DBELL_RFCPEIEN_TX_RETRANS_S 9 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_S 9 // Field: [8] TX_CTRL_ACK_ACK // // Interrupt enable for RFCPEIFG.TX_CTRL_ACK_ACK. -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK 0x00000100 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_BITN 8 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_M 0x00000100 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_S 8 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_S 8 // Field: [7] TX_CTRL_ACK // // Interrupt enable for RFCPEIFG.TX_CTRL_ACK. -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK 0x00000080 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_BITN 7 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_M 0x00000080 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_S 7 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_S 7 // Field: [6] TX_CTRL // // Interrupt enable for RFCPEIFG.TX_CTRL. -#define RFC_DBELL_RFCPEIEN_TX_CTRL 0x00000040 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_BITN 6 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_M 0x00000040 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_S 6 +#define RFC_DBELL_RFCPEIEN_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_S 6 // Field: [5] TX_ACK // // Interrupt enable for RFCPEIFG.TX_ACK. -#define RFC_DBELL_RFCPEIEN_TX_ACK 0x00000020 -#define RFC_DBELL_RFCPEIEN_TX_ACK_BITN 5 -#define RFC_DBELL_RFCPEIEN_TX_ACK_M 0x00000020 -#define RFC_DBELL_RFCPEIEN_TX_ACK_S 5 +#define RFC_DBELL_RFCPEIEN_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEIEN_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEIEN_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEIEN_TX_ACK_S 5 // Field: [4] TX_DONE // // Interrupt enable for RFCPEIFG.TX_DONE. -#define RFC_DBELL_RFCPEIEN_TX_DONE 0x00000010 -#define RFC_DBELL_RFCPEIEN_TX_DONE_BITN 4 -#define RFC_DBELL_RFCPEIEN_TX_DONE_M 0x00000010 -#define RFC_DBELL_RFCPEIEN_TX_DONE_S 4 +#define RFC_DBELL_RFCPEIEN_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEIEN_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEIEN_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEIEN_TX_DONE_S 4 // Field: [3] LAST_FG_COMMAND_DONE // // Interrupt enable for RFCPEIFG.LAST_FG_COMMAND_DONE. -#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE 0x00000008 -#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_BITN 3 -#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_M 0x00000008 -#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_S 3 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_S 3 // Field: [2] FG_COMMAND_DONE // // Interrupt enable for RFCPEIFG.FG_COMMAND_DONE. -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE 0x00000004 -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_BITN 2 -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_M 0x00000004 -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_S 2 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_S 2 // Field: [1] LAST_COMMAND_DONE // // Interrupt enable for RFCPEIFG.LAST_COMMAND_DONE. -#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE 0x00000002 -#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_BITN 1 -#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_M 0x00000002 -#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_S 1 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_S 1 // Field: [0] COMMAND_DONE // // Interrupt enable for RFCPEIFG.COMMAND_DONE. -#define RFC_DBELL_RFCPEIEN_COMMAND_DONE 0x00000001 -#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_BITN 0 -#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_M 0x00000001 -#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_S 0 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_S 0 //***************************************************************************** // @@ -992,12 +992,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR 0x80000000 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_BITN 31 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_M 0x80000000 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_S 31 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE1 0x80000000 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_S 31 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE1 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE0 0x00000000 // Field: [30] BOOT_DONE // @@ -1008,12 +1008,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_BOOT_DONE 0x40000000 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_BITN 30 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_M 0x40000000 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_S 30 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE1 0x40000000 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_S 30 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE1 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE0 0x00000000 // Field: [29] MODULES_UNLOCKED // @@ -1024,12 +1024,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED 0x20000000 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_BITN 29 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_M 0x20000000 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_S 29 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE1 0x20000000 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_S 29 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE1 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE0 0x00000000 // Field: [28] SYNTH_NO_LOCK // @@ -1040,12 +1040,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK 0x10000000 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_BITN 28 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_M 0x10000000 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_S 28 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE1 0x10000000 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_S 28 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE1 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE0 0x00000000 // Field: [27] IRQ27 // @@ -1055,12 +1055,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_IRQ27 0x08000000 -#define RFC_DBELL_RFCPEISL_IRQ27_BITN 27 -#define RFC_DBELL_RFCPEISL_IRQ27_M 0x08000000 -#define RFC_DBELL_RFCPEISL_IRQ27_S 27 -#define RFC_DBELL_RFCPEISL_IRQ27_CPE1 0x08000000 -#define RFC_DBELL_RFCPEISL_IRQ27_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEISL_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_S 27 +#define RFC_DBELL_RFCPEISL_IRQ27_CPE1 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_CPE0 0x00000000 // Field: [26] RX_ABORTED // @@ -1071,12 +1071,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_ABORTED 0x04000000 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_BITN 26 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_M 0x04000000 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_S 26 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE1 0x04000000 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_S 26 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE1 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE0 0x00000000 // Field: [25] RX_N_DATA_WRITTEN // @@ -1087,12 +1087,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN 0x02000000 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_BITN 25 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_M 0x02000000 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_S 25 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE1 0x02000000 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_S 25 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE1 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE0 0x00000000 // Field: [24] RX_DATA_WRITTEN // @@ -1103,12 +1103,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN 0x01000000 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_BITN 24 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_M 0x01000000 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_S 24 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE1 0x01000000 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_S 24 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE1 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE0 0x00000000 // Field: [23] RX_ENTRY_DONE // @@ -1119,12 +1119,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE 0x00800000 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_BITN 23 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_M 0x00800000 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_S 23 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE1 0x00800000 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_S 23 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE1 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE0 0x00000000 // Field: [22] RX_BUF_FULL // @@ -1135,12 +1135,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL 0x00400000 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_BITN 22 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_M 0x00400000 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_S 22 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE1 0x00400000 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_S 22 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE1 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE0 0x00000000 // Field: [21] RX_CTRL_ACK // @@ -1151,12 +1151,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK 0x00200000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_BITN 21 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_M 0x00200000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_S 21 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE1 0x00200000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_S 21 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE1 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE0 0x00000000 // Field: [20] RX_CTRL // @@ -1166,12 +1166,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_CTRL 0x00100000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_BITN 20 -#define RFC_DBELL_RFCPEISL_RX_CTRL_M 0x00100000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_S 20 -#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE1 0x00100000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEISL_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_S 20 +#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE1 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE0 0x00000000 // Field: [19] RX_EMPTY // @@ -1182,12 +1182,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_EMPTY 0x00080000 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_BITN 19 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_M 0x00080000 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_S 19 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE1 0x00080000 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_S 19 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE1 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE0 0x00000000 // Field: [18] RX_IGNORED // @@ -1198,12 +1198,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_IGNORED 0x00040000 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_BITN 18 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_M 0x00040000 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_S 18 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE1 0x00040000 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_S 18 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE1 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE0 0x00000000 // Field: [17] RX_NOK // @@ -1213,12 +1213,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_NOK 0x00020000 -#define RFC_DBELL_RFCPEISL_RX_NOK_BITN 17 -#define RFC_DBELL_RFCPEISL_RX_NOK_M 0x00020000 -#define RFC_DBELL_RFCPEISL_RX_NOK_S 17 -#define RFC_DBELL_RFCPEISL_RX_NOK_CPE1 0x00020000 -#define RFC_DBELL_RFCPEISL_RX_NOK_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEISL_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_S 17 +#define RFC_DBELL_RFCPEISL_RX_NOK_CPE1 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_CPE0 0x00000000 // Field: [16] RX_OK // @@ -1228,12 +1228,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_OK 0x00010000 -#define RFC_DBELL_RFCPEISL_RX_OK_BITN 16 -#define RFC_DBELL_RFCPEISL_RX_OK_M 0x00010000 -#define RFC_DBELL_RFCPEISL_RX_OK_S 16 -#define RFC_DBELL_RFCPEISL_RX_OK_CPE1 0x00010000 -#define RFC_DBELL_RFCPEISL_RX_OK_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEISL_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_S 16 +#define RFC_DBELL_RFCPEISL_RX_OK_CPE1 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_CPE0 0x00000000 // Field: [15] IRQ15 // @@ -1243,12 +1243,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_IRQ15 0x00008000 -#define RFC_DBELL_RFCPEISL_IRQ15_BITN 15 -#define RFC_DBELL_RFCPEISL_IRQ15_M 0x00008000 -#define RFC_DBELL_RFCPEISL_IRQ15_S 15 -#define RFC_DBELL_RFCPEISL_IRQ15_CPE1 0x00008000 -#define RFC_DBELL_RFCPEISL_IRQ15_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEISL_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_S 15 +#define RFC_DBELL_RFCPEISL_IRQ15_CPE1 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_CPE0 0x00000000 // Field: [14] IRQ14 // @@ -1258,12 +1258,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_IRQ14 0x00004000 -#define RFC_DBELL_RFCPEISL_IRQ14_BITN 14 -#define RFC_DBELL_RFCPEISL_IRQ14_M 0x00004000 -#define RFC_DBELL_RFCPEISL_IRQ14_S 14 -#define RFC_DBELL_RFCPEISL_IRQ14_CPE1 0x00004000 -#define RFC_DBELL_RFCPEISL_IRQ14_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEISL_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_S 14 +#define RFC_DBELL_RFCPEISL_IRQ14_CPE1 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_CPE0 0x00000000 // Field: [13] FG_COMMAND_STARTED // @@ -1274,12 +1274,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED 0x00002000 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_BITN 13 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_M 0x00002000 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_S 13 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_CPE1 0x00002000 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED 0x00002000 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_BITN 13 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_M 0x00002000 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_S 13 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_CPE1 0x00002000 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_CPE0 0x00000000 // Field: [12] COMMAND_STARTED // @@ -1290,12 +1290,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_COMMAND_STARTED 0x00001000 -#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_BITN 12 -#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_M 0x00001000 -#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_S 12 -#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_CPE1 0x00001000 -#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_COMMAND_STARTED 0x00001000 +#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_BITN 12 +#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_M 0x00001000 +#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_S 12 +#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_CPE1 0x00001000 +#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_CPE0 0x00000000 // Field: [11] TX_BUFFER_CHANGED // @@ -1306,12 +1306,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED 0x00000800 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_BITN 11 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_M 0x00000800 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_S 11 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE1 0x00000800 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_S 11 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE1 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE0 0x00000000 // Field: [10] TX_ENTRY_DONE // @@ -1322,12 +1322,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE 0x00000400 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_BITN 10 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_M 0x00000400 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_S 10 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE1 0x00000400 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_S 10 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE1 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE0 0x00000000 // Field: [9] TX_RETRANS // @@ -1338,12 +1338,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_RETRANS 0x00000200 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_BITN 9 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_M 0x00000200 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_S 9 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE1 0x00000200 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_S 9 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE1 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE0 0x00000000 // Field: [8] TX_CTRL_ACK_ACK // @@ -1354,12 +1354,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK 0x00000100 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_BITN 8 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_M 0x00000100 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_S 8 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE1 0x00000100 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_S 8 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE1 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE0 0x00000000 // Field: [7] TX_CTRL_ACK // @@ -1370,12 +1370,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK 0x00000080 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_BITN 7 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_M 0x00000080 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_S 7 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE1 0x00000080 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_S 7 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE1 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE0 0x00000000 // Field: [6] TX_CTRL // @@ -1385,12 +1385,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_CTRL 0x00000040 -#define RFC_DBELL_RFCPEISL_TX_CTRL_BITN 6 -#define RFC_DBELL_RFCPEISL_TX_CTRL_M 0x00000040 -#define RFC_DBELL_RFCPEISL_TX_CTRL_S 6 -#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE1 0x00000040 -#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEISL_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_S 6 +#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE1 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE0 0x00000000 // Field: [5] TX_ACK // @@ -1400,12 +1400,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_ACK 0x00000020 -#define RFC_DBELL_RFCPEISL_TX_ACK_BITN 5 -#define RFC_DBELL_RFCPEISL_TX_ACK_M 0x00000020 -#define RFC_DBELL_RFCPEISL_TX_ACK_S 5 -#define RFC_DBELL_RFCPEISL_TX_ACK_CPE1 0x00000020 -#define RFC_DBELL_RFCPEISL_TX_ACK_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEISL_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_S 5 +#define RFC_DBELL_RFCPEISL_TX_ACK_CPE1 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_CPE0 0x00000000 // Field: [4] TX_DONE // @@ -1415,12 +1415,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_DONE 0x00000010 -#define RFC_DBELL_RFCPEISL_TX_DONE_BITN 4 -#define RFC_DBELL_RFCPEISL_TX_DONE_M 0x00000010 -#define RFC_DBELL_RFCPEISL_TX_DONE_S 4 -#define RFC_DBELL_RFCPEISL_TX_DONE_CPE1 0x00000010 -#define RFC_DBELL_RFCPEISL_TX_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEISL_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_S 4 +#define RFC_DBELL_RFCPEISL_TX_DONE_CPE1 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_CPE0 0x00000000 // Field: [3] LAST_FG_COMMAND_DONE // @@ -1431,12 +1431,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE 0x00000008 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_BITN 3 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_M 0x00000008 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_S 3 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE1 0x00000008 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_S 3 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE1 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE0 0x00000000 // Field: [2] FG_COMMAND_DONE // @@ -1447,12 +1447,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE 0x00000004 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_BITN 2 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_M 0x00000004 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_S 2 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE1 0x00000004 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_S 2 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE1 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE0 0x00000000 // Field: [1] LAST_COMMAND_DONE // @@ -1463,12 +1463,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE 0x00000002 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_BITN 1 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_M 0x00000002 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_S 1 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE1 0x00000002 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_S 1 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE1 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE0 0x00000000 // Field: [0] COMMAND_DONE // @@ -1479,12 +1479,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_COMMAND_DONE 0x00000001 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_BITN 0 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_M 0x00000001 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_S 0 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE1 0x00000001 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_S 0 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE1 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE0 0x00000000 //***************************************************************************** // @@ -1494,10 +1494,10 @@ // Field: [0] ACKFLAG // // Interrupt flag for Command ACK -#define RFC_DBELL_RFACKIFG_ACKFLAG 0x00000001 -#define RFC_DBELL_RFACKIFG_ACKFLAG_BITN 0 -#define RFC_DBELL_RFACKIFG_ACKFLAG_M 0x00000001 -#define RFC_DBELL_RFACKIFG_ACKFLAG_S 0 +#define RFC_DBELL_RFACKIFG_ACKFLAG 0x00000001 +#define RFC_DBELL_RFACKIFG_ACKFLAG_BITN 0 +#define RFC_DBELL_RFACKIFG_ACKFLAG_M 0x00000001 +#define RFC_DBELL_RFACKIFG_ACKFLAG_S 0 //***************************************************************************** // @@ -1525,25 +1525,25 @@ // CPEGPO2 CPE GPO line 2 // CPEGPO1 CPE GPO line 1 // CPEGPO0 CPE GPO line 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_W 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_M 0x0000F000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_S 12 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO3 0x0000F000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO2 0x0000E000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO1 0x0000D000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO0 0x0000C000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO3 0x0000B000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO2 0x0000A000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO1 0x00009000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO0 0x00008000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO3 0x00007000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO2 0x00006000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO1 0x00005000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO0 0x00004000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO3 0x00003000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO2 0x00002000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO1 0x00001000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO0 0x00000000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_M 0x0000F000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_S 12 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO3 0x0000F000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO2 0x0000E000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO1 0x0000D000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO0 0x0000C000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO3 0x0000B000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO2 0x0000A000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO1 0x00009000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO0 0x00008000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO3 0x00007000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO2 0x00006000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO1 0x00005000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO0 0x00004000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO3 0x00003000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO2 0x00002000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO1 0x00001000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO0 0x00000000 // Field: [11:8] GPOCTL2 // @@ -1566,25 +1566,25 @@ // CPEGPO2 CPE GPO line 2 // CPEGPO1 CPE GPO line 1 // CPEGPO0 CPE GPO line 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_W 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_M 0x00000F00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_S 8 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO3 0x00000F00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO2 0x00000E00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO1 0x00000D00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO0 0x00000C00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO3 0x00000B00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO2 0x00000A00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO1 0x00000900 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO0 0x00000800 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO3 0x00000700 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO2 0x00000600 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO1 0x00000500 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO0 0x00000400 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO3 0x00000300 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO2 0x00000200 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO1 0x00000100 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO0 0x00000000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_M 0x00000F00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_S 8 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO3 0x00000F00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO2 0x00000E00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO1 0x00000D00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO0 0x00000C00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO3 0x00000B00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO2 0x00000A00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO1 0x00000900 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO0 0x00000800 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO3 0x00000700 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO2 0x00000600 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO1 0x00000500 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO0 0x00000400 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO3 0x00000300 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO2 0x00000200 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO1 0x00000100 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO0 0x00000000 // Field: [7:4] GPOCTL1 // @@ -1607,25 +1607,25 @@ // CPEGPO2 CPE GPO line 2 // CPEGPO1 CPE GPO line 1 // CPEGPO0 CPE GPO line 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_W 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_M 0x000000F0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_S 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO3 0x000000F0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO2 0x000000E0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO1 0x000000D0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO0 0x000000C0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO3 0x000000B0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO2 0x000000A0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO1 0x00000090 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO0 0x00000080 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO3 0x00000070 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO2 0x00000060 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO1 0x00000050 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO0 0x00000040 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO3 0x00000030 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO2 0x00000020 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO1 0x00000010 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO0 0x00000000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_M 0x000000F0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_S 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO3 0x000000F0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO2 0x000000E0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO1 0x000000D0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO0 0x000000C0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO3 0x000000B0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO2 0x000000A0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO1 0x00000090 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO0 0x00000080 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO3 0x00000070 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO2 0x00000060 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO1 0x00000050 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO0 0x00000040 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO3 0x00000030 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO2 0x00000020 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO1 0x00000010 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO0 0x00000000 // Field: [3:0] GPOCTL0 // @@ -1648,25 +1648,24 @@ // CPEGPO2 CPE GPO line 2 // CPEGPO1 CPE GPO line 1 // CPEGPO0 CPE GPO line 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_W 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_M 0x0000000F -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_S 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO3 0x0000000F -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO2 0x0000000E -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO1 0x0000000D -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO0 0x0000000C -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO3 0x0000000B -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO2 0x0000000A -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO1 0x00000009 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO0 0x00000008 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO3 0x00000007 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO2 0x00000006 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO1 0x00000005 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO0 0x00000004 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO3 0x00000003 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO2 0x00000002 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO1 0x00000001 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO0 0x00000000 - +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_M 0x0000000F +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_S 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO3 0x0000000F +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO2 0x0000000E +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO1 0x0000000D +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO0 0x0000000C +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO3 0x0000000B +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO2 0x0000000A +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO1 0x00000009 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO0 0x00000008 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO3 0x00000007 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO2 0x00000006 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO1 0x00000005 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO0 0x00000004 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO3 0x00000003 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO2 0x00000002 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO1 0x00000001 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO0 0x00000000 #endif // __RFC_DBELL__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_pwr.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_pwr.h index 7c636d9..b6a3a14 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_pwr.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_pwr.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_rfc_pwr_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_rfc_pwr_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_RFC_PWR_H__ #define __HW_RFC_PWR_H__ @@ -44,7 +44,7 @@ // //***************************************************************************** // RF Core Power Management and Clock Enable -#define RFC_PWR_O_PWMCLKEN 0x00000000 +#define RFC_PWR_O_PWMCLKEN 0x00000000 //***************************************************************************** // @@ -54,87 +54,87 @@ // Field: [10] RFCTRC // // Enable clock to the RF Core Tracer (RFCTRC) module. -#define RFC_PWR_PWMCLKEN_RFCTRC 0x00000400 -#define RFC_PWR_PWMCLKEN_RFCTRC_BITN 10 -#define RFC_PWR_PWMCLKEN_RFCTRC_M 0x00000400 -#define RFC_PWR_PWMCLKEN_RFCTRC_S 10 +#define RFC_PWR_PWMCLKEN_RFCTRC 0x00000400 +#define RFC_PWR_PWMCLKEN_RFCTRC_BITN 10 +#define RFC_PWR_PWMCLKEN_RFCTRC_M 0x00000400 +#define RFC_PWR_PWMCLKEN_RFCTRC_S 10 // Field: [9] FSCA // // Enable clock to the Frequency Synthesizer Calibration Accelerator (FSCA) // module. -#define RFC_PWR_PWMCLKEN_FSCA 0x00000200 -#define RFC_PWR_PWMCLKEN_FSCA_BITN 9 -#define RFC_PWR_PWMCLKEN_FSCA_M 0x00000200 -#define RFC_PWR_PWMCLKEN_FSCA_S 9 +#define RFC_PWR_PWMCLKEN_FSCA 0x00000200 +#define RFC_PWR_PWMCLKEN_FSCA_BITN 9 +#define RFC_PWR_PWMCLKEN_FSCA_M 0x00000200 +#define RFC_PWR_PWMCLKEN_FSCA_S 9 // Field: [8] PHA // // Enable clock to the Packet Handling Accelerator (PHA) module. -#define RFC_PWR_PWMCLKEN_PHA 0x00000100 -#define RFC_PWR_PWMCLKEN_PHA_BITN 8 -#define RFC_PWR_PWMCLKEN_PHA_M 0x00000100 -#define RFC_PWR_PWMCLKEN_PHA_S 8 +#define RFC_PWR_PWMCLKEN_PHA 0x00000100 +#define RFC_PWR_PWMCLKEN_PHA_BITN 8 +#define RFC_PWR_PWMCLKEN_PHA_M 0x00000100 +#define RFC_PWR_PWMCLKEN_PHA_S 8 // Field: [7] RAT // // Enable clock to the Radio Timer (RAT) module. -#define RFC_PWR_PWMCLKEN_RAT 0x00000080 -#define RFC_PWR_PWMCLKEN_RAT_BITN 7 -#define RFC_PWR_PWMCLKEN_RAT_M 0x00000080 -#define RFC_PWR_PWMCLKEN_RAT_S 7 +#define RFC_PWR_PWMCLKEN_RAT 0x00000080 +#define RFC_PWR_PWMCLKEN_RAT_BITN 7 +#define RFC_PWR_PWMCLKEN_RAT_M 0x00000080 +#define RFC_PWR_PWMCLKEN_RAT_S 7 // Field: [6] RFERAM // // Enable clock to the RF Engine RAM module. -#define RFC_PWR_PWMCLKEN_RFERAM 0x00000040 -#define RFC_PWR_PWMCLKEN_RFERAM_BITN 6 -#define RFC_PWR_PWMCLKEN_RFERAM_M 0x00000040 -#define RFC_PWR_PWMCLKEN_RFERAM_S 6 +#define RFC_PWR_PWMCLKEN_RFERAM 0x00000040 +#define RFC_PWR_PWMCLKEN_RFERAM_BITN 6 +#define RFC_PWR_PWMCLKEN_RFERAM_M 0x00000040 +#define RFC_PWR_PWMCLKEN_RFERAM_S 6 // Field: [5] RFE // // Enable clock to the RF Engine (RFE) module. -#define RFC_PWR_PWMCLKEN_RFE 0x00000020 -#define RFC_PWR_PWMCLKEN_RFE_BITN 5 -#define RFC_PWR_PWMCLKEN_RFE_M 0x00000020 -#define RFC_PWR_PWMCLKEN_RFE_S 5 +#define RFC_PWR_PWMCLKEN_RFE 0x00000020 +#define RFC_PWR_PWMCLKEN_RFE_BITN 5 +#define RFC_PWR_PWMCLKEN_RFE_M 0x00000020 +#define RFC_PWR_PWMCLKEN_RFE_S 5 // Field: [4] MDMRAM // // Enable clock to the Modem RAM module. -#define RFC_PWR_PWMCLKEN_MDMRAM 0x00000010 -#define RFC_PWR_PWMCLKEN_MDMRAM_BITN 4 -#define RFC_PWR_PWMCLKEN_MDMRAM_M 0x00000010 -#define RFC_PWR_PWMCLKEN_MDMRAM_S 4 +#define RFC_PWR_PWMCLKEN_MDMRAM 0x00000010 +#define RFC_PWR_PWMCLKEN_MDMRAM_BITN 4 +#define RFC_PWR_PWMCLKEN_MDMRAM_M 0x00000010 +#define RFC_PWR_PWMCLKEN_MDMRAM_S 4 // Field: [3] MDM // // Enable clock to the Modem (MDM) module. -#define RFC_PWR_PWMCLKEN_MDM 0x00000008 -#define RFC_PWR_PWMCLKEN_MDM_BITN 3 -#define RFC_PWR_PWMCLKEN_MDM_M 0x00000008 -#define RFC_PWR_PWMCLKEN_MDM_S 3 +#define RFC_PWR_PWMCLKEN_MDM 0x00000008 +#define RFC_PWR_PWMCLKEN_MDM_BITN 3 +#define RFC_PWR_PWMCLKEN_MDM_M 0x00000008 +#define RFC_PWR_PWMCLKEN_MDM_S 3 // Field: [2] CPERAM // // Enable clock to the Command and Packet Engine (CPE) RAM module. As part of // RF Core initialization, set this bit together with CPE bit to enable CPE to // boot. -#define RFC_PWR_PWMCLKEN_CPERAM 0x00000004 -#define RFC_PWR_PWMCLKEN_CPERAM_BITN 2 -#define RFC_PWR_PWMCLKEN_CPERAM_M 0x00000004 -#define RFC_PWR_PWMCLKEN_CPERAM_S 2 +#define RFC_PWR_PWMCLKEN_CPERAM 0x00000004 +#define RFC_PWR_PWMCLKEN_CPERAM_BITN 2 +#define RFC_PWR_PWMCLKEN_CPERAM_M 0x00000004 +#define RFC_PWR_PWMCLKEN_CPERAM_S 2 // Field: [1] CPE // // Enable processor clock (hclk) to the Command and Packet Engine (CPE). As // part of RF Core initialization, set this bit together with CPERAM bit to // enable CPE to boot. -#define RFC_PWR_PWMCLKEN_CPE 0x00000002 -#define RFC_PWR_PWMCLKEN_CPE_BITN 1 -#define RFC_PWR_PWMCLKEN_CPE_M 0x00000002 -#define RFC_PWR_PWMCLKEN_CPE_S 1 +#define RFC_PWR_PWMCLKEN_CPE 0x00000002 +#define RFC_PWR_PWMCLKEN_CPE_BITN 1 +#define RFC_PWR_PWMCLKEN_CPE_M 0x00000002 +#define RFC_PWR_PWMCLKEN_CPE_S 1 // Field: [0] RFC // @@ -144,10 +144,9 @@ // remove possibility of locking yourself out from the RF Core, this bit can // not be cleared. If you need to disable all clocks to the RF Core, see the // PRCM:RFCCLKG.CLK_EN register. -#define RFC_PWR_PWMCLKEN_RFC 0x00000001 -#define RFC_PWR_PWMCLKEN_RFC_BITN 0 -#define RFC_PWR_PWMCLKEN_RFC_M 0x00000001 -#define RFC_PWR_PWMCLKEN_RFC_S 0 - +#define RFC_PWR_PWMCLKEN_RFC 0x00000001 +#define RFC_PWR_PWMCLKEN_RFC_BITN 0 +#define RFC_PWR_PWMCLKEN_RFC_M 0x00000001 +#define RFC_PWR_PWMCLKEN_RFC_S 0 #endif // __RFC_PWR__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_rat.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_rat.h index b2bdfd6..1987b72 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_rat.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_rat.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_rfc_rat_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_rfc_rat_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_RFC_RAT_H__ #define __HW_RFC_RAT_H__ @@ -44,31 +44,31 @@ // //***************************************************************************** // Radio Timer Counter Value -#define RFC_RAT_O_RATCNT 0x00000004 +#define RFC_RAT_O_RATCNT 0x00000004 // Timer Channel 0 Capture/Compare Register -#define RFC_RAT_O_RATCH0VAL 0x00000080 +#define RFC_RAT_O_RATCH0VAL 0x00000080 // Timer Channel 1 Capture/Compare Register -#define RFC_RAT_O_RATCH1VAL 0x00000084 +#define RFC_RAT_O_RATCH1VAL 0x00000084 // Timer Channel 2 Capture/Compare Register -#define RFC_RAT_O_RATCH2VAL 0x00000088 +#define RFC_RAT_O_RATCH2VAL 0x00000088 // Timer Channel 3 Capture/Compare Register -#define RFC_RAT_O_RATCH3VAL 0x0000008C +#define RFC_RAT_O_RATCH3VAL 0x0000008C // Timer Channel 4 Capture/Compare Register -#define RFC_RAT_O_RATCH4VAL 0x00000090 +#define RFC_RAT_O_RATCH4VAL 0x00000090 // Timer Channel 5 Capture/Compare Register -#define RFC_RAT_O_RATCH5VAL 0x00000094 +#define RFC_RAT_O_RATCH5VAL 0x00000094 // Timer Channel 6 Capture/Compare Register -#define RFC_RAT_O_RATCH6VAL 0x00000098 +#define RFC_RAT_O_RATCH6VAL 0x00000098 // Timer Channel 7 Capture/Compare Register -#define RFC_RAT_O_RATCH7VAL 0x0000009C +#define RFC_RAT_O_RATCH7VAL 0x0000009C //***************************************************************************** // @@ -78,9 +78,9 @@ // Field: [31:0] CNT // // Counter value. This is not writable while radio timer counter is enabled. -#define RFC_RAT_RATCNT_CNT_W 32 -#define RFC_RAT_RATCNT_CNT_M 0xFFFFFFFF -#define RFC_RAT_RATCNT_CNT_S 0 +#define RFC_RAT_RATCNT_CNT_W 32 +#define RFC_RAT_RATCNT_CNT_M 0xFFFFFFFF +#define RFC_RAT_RATCNT_CNT_S 0 //***************************************************************************** // @@ -92,9 +92,9 @@ // Capture/compare value. Only writable when the channel is configured for // compare mode. In compare mode, a write to this register will auto-arm the // channel. -#define RFC_RAT_RATCH0VAL_VAL_W 32 -#define RFC_RAT_RATCH0VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH0VAL_VAL_S 0 +#define RFC_RAT_RATCH0VAL_VAL_W 32 +#define RFC_RAT_RATCH0VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH0VAL_VAL_S 0 //***************************************************************************** // @@ -106,9 +106,9 @@ // Capture/compare value. Only writable when the channel is configured for // compare mode. In compare mode, a write to this register will auto-arm the // channel. -#define RFC_RAT_RATCH1VAL_VAL_W 32 -#define RFC_RAT_RATCH1VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH1VAL_VAL_S 0 +#define RFC_RAT_RATCH1VAL_VAL_W 32 +#define RFC_RAT_RATCH1VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH1VAL_VAL_S 0 //***************************************************************************** // @@ -120,9 +120,9 @@ // Capture/compare value. Only writable when the channel is configured for // compare mode. In compare mode, a write to this register will auto-arm the // channel. -#define RFC_RAT_RATCH2VAL_VAL_W 32 -#define RFC_RAT_RATCH2VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH2VAL_VAL_S 0 +#define RFC_RAT_RATCH2VAL_VAL_W 32 +#define RFC_RAT_RATCH2VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH2VAL_VAL_S 0 //***************************************************************************** // @@ -134,9 +134,9 @@ // Capture/compare value. Only writable when the channel is configured for // compare mode. In compare mode, a write to this register will auto-arm the // channel. -#define RFC_RAT_RATCH3VAL_VAL_W 32 -#define RFC_RAT_RATCH3VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH3VAL_VAL_S 0 +#define RFC_RAT_RATCH3VAL_VAL_W 32 +#define RFC_RAT_RATCH3VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH3VAL_VAL_S 0 //***************************************************************************** // @@ -148,9 +148,9 @@ // Capture/compare value. Only writable when the channel is configured for // compare mode. In compare mode, a write to this register will auto-arm the // channel. -#define RFC_RAT_RATCH4VAL_VAL_W 32 -#define RFC_RAT_RATCH4VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH4VAL_VAL_S 0 +#define RFC_RAT_RATCH4VAL_VAL_W 32 +#define RFC_RAT_RATCH4VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH4VAL_VAL_S 0 //***************************************************************************** // @@ -162,9 +162,9 @@ // Capture/compare value. Only writable when the channel is configured for // compare mode. In compare mode, a write to this register will auto-arm the // channel. -#define RFC_RAT_RATCH5VAL_VAL_W 32 -#define RFC_RAT_RATCH5VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH5VAL_VAL_S 0 +#define RFC_RAT_RATCH5VAL_VAL_W 32 +#define RFC_RAT_RATCH5VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH5VAL_VAL_S 0 //***************************************************************************** // @@ -176,9 +176,9 @@ // Capture/compare value. Only writable when the channel is configured for // compare mode. In compare mode, a write to this register will auto-arm the // channel. -#define RFC_RAT_RATCH6VAL_VAL_W 32 -#define RFC_RAT_RATCH6VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH6VAL_VAL_S 0 +#define RFC_RAT_RATCH6VAL_VAL_W 32 +#define RFC_RAT_RATCH6VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH6VAL_VAL_S 0 //***************************************************************************** // @@ -190,9 +190,8 @@ // Capture/compare value. Only writable when the channel is configured for // compare mode. In compare mode, a write to this register will auto-arm the // channel. -#define RFC_RAT_RATCH7VAL_VAL_W 32 -#define RFC_RAT_RATCH7VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH7VAL_VAL_S 0 - +#define RFC_RAT_RATCH7VAL_VAL_W 32 +#define RFC_RAT_RATCH7VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH7VAL_VAL_S 0 #endif // __RFC_RAT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_ullram.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_ullram.h index 717184e..edb46d5 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_ullram.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_ullram.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_rfc_ullram_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_rfc_ullram_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_RFC_ULLRAM_H__ #define __HW_RFC_ULLRAM_H__ @@ -44,6148 +44,6148 @@ // //***************************************************************************** // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK10 0x00000000 +#define RFC_ULLRAM_O_BANK10 0x00000000 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11 0x00000004 +#define RFC_ULLRAM_O_BANK11 0x00000004 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12 0x00000008 +#define RFC_ULLRAM_O_BANK12 0x00000008 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK13 0x0000000C +#define RFC_ULLRAM_O_BANK13 0x0000000C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK14 0x00000010 +#define RFC_ULLRAM_O_BANK14 0x00000010 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK15 0x00000014 +#define RFC_ULLRAM_O_BANK15 0x00000014 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK16 0x00000018 +#define RFC_ULLRAM_O_BANK16 0x00000018 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK17 0x0000001C +#define RFC_ULLRAM_O_BANK17 0x0000001C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK18 0x00000020 +#define RFC_ULLRAM_O_BANK18 0x00000020 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK19 0x00000024 +#define RFC_ULLRAM_O_BANK19 0x00000024 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK110 0x00000028 +#define RFC_ULLRAM_O_BANK110 0x00000028 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK111 0x0000002C +#define RFC_ULLRAM_O_BANK111 0x0000002C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK112 0x00000030 +#define RFC_ULLRAM_O_BANK112 0x00000030 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK113 0x00000034 +#define RFC_ULLRAM_O_BANK113 0x00000034 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK114 0x00000038 +#define RFC_ULLRAM_O_BANK114 0x00000038 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK115 0x0000003C +#define RFC_ULLRAM_O_BANK115 0x0000003C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK116 0x00000040 +#define RFC_ULLRAM_O_BANK116 0x00000040 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK117 0x00000044 +#define RFC_ULLRAM_O_BANK117 0x00000044 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK118 0x00000048 +#define RFC_ULLRAM_O_BANK118 0x00000048 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK119 0x0000004C +#define RFC_ULLRAM_O_BANK119 0x0000004C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK120 0x00000050 +#define RFC_ULLRAM_O_BANK120 0x00000050 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK121 0x00000054 +#define RFC_ULLRAM_O_BANK121 0x00000054 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK122 0x00000058 +#define RFC_ULLRAM_O_BANK122 0x00000058 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK123 0x0000005C +#define RFC_ULLRAM_O_BANK123 0x0000005C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK124 0x00000060 +#define RFC_ULLRAM_O_BANK124 0x00000060 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK125 0x00000064 +#define RFC_ULLRAM_O_BANK125 0x00000064 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK126 0x00000068 +#define RFC_ULLRAM_O_BANK126 0x00000068 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK127 0x0000006C +#define RFC_ULLRAM_O_BANK127 0x0000006C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK128 0x00000070 +#define RFC_ULLRAM_O_BANK128 0x00000070 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK129 0x00000074 +#define RFC_ULLRAM_O_BANK129 0x00000074 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK130 0x00000078 +#define RFC_ULLRAM_O_BANK130 0x00000078 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK131 0x0000007C +#define RFC_ULLRAM_O_BANK131 0x0000007C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK132 0x00000080 +#define RFC_ULLRAM_O_BANK132 0x00000080 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK133 0x00000084 +#define RFC_ULLRAM_O_BANK133 0x00000084 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK134 0x00000088 +#define RFC_ULLRAM_O_BANK134 0x00000088 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK135 0x0000008C +#define RFC_ULLRAM_O_BANK135 0x0000008C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK136 0x00000090 +#define RFC_ULLRAM_O_BANK136 0x00000090 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK137 0x00000094 +#define RFC_ULLRAM_O_BANK137 0x00000094 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK138 0x00000098 +#define RFC_ULLRAM_O_BANK138 0x00000098 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK139 0x0000009C +#define RFC_ULLRAM_O_BANK139 0x0000009C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK140 0x000000A0 +#define RFC_ULLRAM_O_BANK140 0x000000A0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK141 0x000000A4 +#define RFC_ULLRAM_O_BANK141 0x000000A4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK142 0x000000A8 +#define RFC_ULLRAM_O_BANK142 0x000000A8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK143 0x000000AC +#define RFC_ULLRAM_O_BANK143 0x000000AC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK144 0x000000B0 +#define RFC_ULLRAM_O_BANK144 0x000000B0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK145 0x000000B4 +#define RFC_ULLRAM_O_BANK145 0x000000B4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK146 0x000000B8 +#define RFC_ULLRAM_O_BANK146 0x000000B8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK147 0x000000BC +#define RFC_ULLRAM_O_BANK147 0x000000BC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK148 0x000000C0 +#define RFC_ULLRAM_O_BANK148 0x000000C0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK149 0x000000C4 +#define RFC_ULLRAM_O_BANK149 0x000000C4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK150 0x000000C8 +#define RFC_ULLRAM_O_BANK150 0x000000C8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK151 0x000000CC +#define RFC_ULLRAM_O_BANK151 0x000000CC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK152 0x000000D0 +#define RFC_ULLRAM_O_BANK152 0x000000D0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK153 0x000000D4 +#define RFC_ULLRAM_O_BANK153 0x000000D4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK154 0x000000D8 +#define RFC_ULLRAM_O_BANK154 0x000000D8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK155 0x000000DC +#define RFC_ULLRAM_O_BANK155 0x000000DC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK156 0x000000E0 +#define RFC_ULLRAM_O_BANK156 0x000000E0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK157 0x000000E4 +#define RFC_ULLRAM_O_BANK157 0x000000E4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK158 0x000000E8 +#define RFC_ULLRAM_O_BANK158 0x000000E8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK159 0x000000EC +#define RFC_ULLRAM_O_BANK159 0x000000EC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK160 0x000000F0 +#define RFC_ULLRAM_O_BANK160 0x000000F0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK161 0x000000F4 +#define RFC_ULLRAM_O_BANK161 0x000000F4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK162 0x000000F8 +#define RFC_ULLRAM_O_BANK162 0x000000F8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK163 0x000000FC +#define RFC_ULLRAM_O_BANK163 0x000000FC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK164 0x00000100 +#define RFC_ULLRAM_O_BANK164 0x00000100 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK165 0x00000104 +#define RFC_ULLRAM_O_BANK165 0x00000104 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK166 0x00000108 +#define RFC_ULLRAM_O_BANK166 0x00000108 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK167 0x0000010C +#define RFC_ULLRAM_O_BANK167 0x0000010C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK168 0x00000110 +#define RFC_ULLRAM_O_BANK168 0x00000110 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK169 0x00000114 +#define RFC_ULLRAM_O_BANK169 0x00000114 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK170 0x00000118 +#define RFC_ULLRAM_O_BANK170 0x00000118 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK171 0x0000011C +#define RFC_ULLRAM_O_BANK171 0x0000011C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK172 0x00000120 +#define RFC_ULLRAM_O_BANK172 0x00000120 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK173 0x00000124 +#define RFC_ULLRAM_O_BANK173 0x00000124 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK174 0x00000128 +#define RFC_ULLRAM_O_BANK174 0x00000128 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK175 0x0000012C +#define RFC_ULLRAM_O_BANK175 0x0000012C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK176 0x00000130 +#define RFC_ULLRAM_O_BANK176 0x00000130 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK177 0x00000134 +#define RFC_ULLRAM_O_BANK177 0x00000134 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK178 0x00000138 +#define RFC_ULLRAM_O_BANK178 0x00000138 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK179 0x0000013C +#define RFC_ULLRAM_O_BANK179 0x0000013C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK180 0x00000140 +#define RFC_ULLRAM_O_BANK180 0x00000140 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK181 0x00000144 +#define RFC_ULLRAM_O_BANK181 0x00000144 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK182 0x00000148 +#define RFC_ULLRAM_O_BANK182 0x00000148 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK183 0x0000014C +#define RFC_ULLRAM_O_BANK183 0x0000014C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK184 0x00000150 +#define RFC_ULLRAM_O_BANK184 0x00000150 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK185 0x00000154 +#define RFC_ULLRAM_O_BANK185 0x00000154 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK186 0x00000158 +#define RFC_ULLRAM_O_BANK186 0x00000158 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK187 0x0000015C +#define RFC_ULLRAM_O_BANK187 0x0000015C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK188 0x00000160 +#define RFC_ULLRAM_O_BANK188 0x00000160 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK189 0x00000164 +#define RFC_ULLRAM_O_BANK189 0x00000164 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK190 0x00000168 +#define RFC_ULLRAM_O_BANK190 0x00000168 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK191 0x0000016C +#define RFC_ULLRAM_O_BANK191 0x0000016C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK192 0x00000170 +#define RFC_ULLRAM_O_BANK192 0x00000170 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK193 0x00000174 +#define RFC_ULLRAM_O_BANK193 0x00000174 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK194 0x00000178 +#define RFC_ULLRAM_O_BANK194 0x00000178 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK195 0x0000017C +#define RFC_ULLRAM_O_BANK195 0x0000017C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK196 0x00000180 +#define RFC_ULLRAM_O_BANK196 0x00000180 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK197 0x00000184 +#define RFC_ULLRAM_O_BANK197 0x00000184 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK198 0x00000188 +#define RFC_ULLRAM_O_BANK198 0x00000188 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK199 0x0000018C +#define RFC_ULLRAM_O_BANK199 0x0000018C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1100 0x00000190 +#define RFC_ULLRAM_O_BANK1100 0x00000190 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1101 0x00000194 +#define RFC_ULLRAM_O_BANK1101 0x00000194 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1102 0x00000198 +#define RFC_ULLRAM_O_BANK1102 0x00000198 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1103 0x0000019C +#define RFC_ULLRAM_O_BANK1103 0x0000019C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1104 0x000001A0 +#define RFC_ULLRAM_O_BANK1104 0x000001A0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1105 0x000001A4 +#define RFC_ULLRAM_O_BANK1105 0x000001A4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1106 0x000001A8 +#define RFC_ULLRAM_O_BANK1106 0x000001A8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1107 0x000001AC +#define RFC_ULLRAM_O_BANK1107 0x000001AC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1108 0x000001B0 +#define RFC_ULLRAM_O_BANK1108 0x000001B0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1109 0x000001B4 +#define RFC_ULLRAM_O_BANK1109 0x000001B4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1110 0x000001B8 +#define RFC_ULLRAM_O_BANK1110 0x000001B8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1111 0x000001BC +#define RFC_ULLRAM_O_BANK1111 0x000001BC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1112 0x000001C0 +#define RFC_ULLRAM_O_BANK1112 0x000001C0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1113 0x000001C4 +#define RFC_ULLRAM_O_BANK1113 0x000001C4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1114 0x000001C8 +#define RFC_ULLRAM_O_BANK1114 0x000001C8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1115 0x000001CC +#define RFC_ULLRAM_O_BANK1115 0x000001CC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1116 0x000001D0 +#define RFC_ULLRAM_O_BANK1116 0x000001D0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1117 0x000001D4 +#define RFC_ULLRAM_O_BANK1117 0x000001D4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1118 0x000001D8 +#define RFC_ULLRAM_O_BANK1118 0x000001D8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1119 0x000001DC +#define RFC_ULLRAM_O_BANK1119 0x000001DC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1120 0x000001E0 +#define RFC_ULLRAM_O_BANK1120 0x000001E0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1121 0x000001E4 +#define RFC_ULLRAM_O_BANK1121 0x000001E4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1122 0x000001E8 +#define RFC_ULLRAM_O_BANK1122 0x000001E8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1123 0x000001EC +#define RFC_ULLRAM_O_BANK1123 0x000001EC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1124 0x000001F0 +#define RFC_ULLRAM_O_BANK1124 0x000001F0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1125 0x000001F4 +#define RFC_ULLRAM_O_BANK1125 0x000001F4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1126 0x000001F8 +#define RFC_ULLRAM_O_BANK1126 0x000001F8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1127 0x000001FC +#define RFC_ULLRAM_O_BANK1127 0x000001FC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1128 0x00000200 +#define RFC_ULLRAM_O_BANK1128 0x00000200 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1129 0x00000204 +#define RFC_ULLRAM_O_BANK1129 0x00000204 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1130 0x00000208 +#define RFC_ULLRAM_O_BANK1130 0x00000208 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1131 0x0000020C +#define RFC_ULLRAM_O_BANK1131 0x0000020C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1132 0x00000210 +#define RFC_ULLRAM_O_BANK1132 0x00000210 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1133 0x00000214 +#define RFC_ULLRAM_O_BANK1133 0x00000214 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1134 0x00000218 +#define RFC_ULLRAM_O_BANK1134 0x00000218 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1135 0x0000021C +#define RFC_ULLRAM_O_BANK1135 0x0000021C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1136 0x00000220 +#define RFC_ULLRAM_O_BANK1136 0x00000220 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1137 0x00000224 +#define RFC_ULLRAM_O_BANK1137 0x00000224 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1138 0x00000228 +#define RFC_ULLRAM_O_BANK1138 0x00000228 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1139 0x0000022C +#define RFC_ULLRAM_O_BANK1139 0x0000022C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1140 0x00000230 +#define RFC_ULLRAM_O_BANK1140 0x00000230 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1141 0x00000234 +#define RFC_ULLRAM_O_BANK1141 0x00000234 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1142 0x00000238 +#define RFC_ULLRAM_O_BANK1142 0x00000238 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1143 0x0000023C +#define RFC_ULLRAM_O_BANK1143 0x0000023C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1144 0x00000240 +#define RFC_ULLRAM_O_BANK1144 0x00000240 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1145 0x00000244 +#define RFC_ULLRAM_O_BANK1145 0x00000244 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1146 0x00000248 +#define RFC_ULLRAM_O_BANK1146 0x00000248 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1147 0x0000024C +#define RFC_ULLRAM_O_BANK1147 0x0000024C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1148 0x00000250 +#define RFC_ULLRAM_O_BANK1148 0x00000250 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1149 0x00000254 +#define RFC_ULLRAM_O_BANK1149 0x00000254 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1150 0x00000258 +#define RFC_ULLRAM_O_BANK1150 0x00000258 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1151 0x0000025C +#define RFC_ULLRAM_O_BANK1151 0x0000025C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1152 0x00000260 +#define RFC_ULLRAM_O_BANK1152 0x00000260 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1153 0x00000264 +#define RFC_ULLRAM_O_BANK1153 0x00000264 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1154 0x00000268 +#define RFC_ULLRAM_O_BANK1154 0x00000268 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1155 0x0000026C +#define RFC_ULLRAM_O_BANK1155 0x0000026C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1156 0x00000270 +#define RFC_ULLRAM_O_BANK1156 0x00000270 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1157 0x00000274 +#define RFC_ULLRAM_O_BANK1157 0x00000274 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1158 0x00000278 +#define RFC_ULLRAM_O_BANK1158 0x00000278 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1159 0x0000027C +#define RFC_ULLRAM_O_BANK1159 0x0000027C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1160 0x00000280 +#define RFC_ULLRAM_O_BANK1160 0x00000280 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1161 0x00000284 +#define RFC_ULLRAM_O_BANK1161 0x00000284 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1162 0x00000288 +#define RFC_ULLRAM_O_BANK1162 0x00000288 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1163 0x0000028C +#define RFC_ULLRAM_O_BANK1163 0x0000028C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1164 0x00000290 +#define RFC_ULLRAM_O_BANK1164 0x00000290 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1165 0x00000294 +#define RFC_ULLRAM_O_BANK1165 0x00000294 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1166 0x00000298 +#define RFC_ULLRAM_O_BANK1166 0x00000298 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1167 0x0000029C +#define RFC_ULLRAM_O_BANK1167 0x0000029C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1168 0x000002A0 +#define RFC_ULLRAM_O_BANK1168 0x000002A0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1169 0x000002A4 +#define RFC_ULLRAM_O_BANK1169 0x000002A4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1170 0x000002A8 +#define RFC_ULLRAM_O_BANK1170 0x000002A8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1171 0x000002AC +#define RFC_ULLRAM_O_BANK1171 0x000002AC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1172 0x000002B0 +#define RFC_ULLRAM_O_BANK1172 0x000002B0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1173 0x000002B4 +#define RFC_ULLRAM_O_BANK1173 0x000002B4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1174 0x000002B8 +#define RFC_ULLRAM_O_BANK1174 0x000002B8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1175 0x000002BC +#define RFC_ULLRAM_O_BANK1175 0x000002BC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1176 0x000002C0 +#define RFC_ULLRAM_O_BANK1176 0x000002C0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1177 0x000002C4 +#define RFC_ULLRAM_O_BANK1177 0x000002C4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1178 0x000002C8 +#define RFC_ULLRAM_O_BANK1178 0x000002C8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1179 0x000002CC +#define RFC_ULLRAM_O_BANK1179 0x000002CC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1180 0x000002D0 +#define RFC_ULLRAM_O_BANK1180 0x000002D0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1181 0x000002D4 +#define RFC_ULLRAM_O_BANK1181 0x000002D4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1182 0x000002D8 +#define RFC_ULLRAM_O_BANK1182 0x000002D8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1183 0x000002DC +#define RFC_ULLRAM_O_BANK1183 0x000002DC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1184 0x000002E0 +#define RFC_ULLRAM_O_BANK1184 0x000002E0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1185 0x000002E4 +#define RFC_ULLRAM_O_BANK1185 0x000002E4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1186 0x000002E8 +#define RFC_ULLRAM_O_BANK1186 0x000002E8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1187 0x000002EC +#define RFC_ULLRAM_O_BANK1187 0x000002EC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1188 0x000002F0 +#define RFC_ULLRAM_O_BANK1188 0x000002F0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1189 0x000002F4 +#define RFC_ULLRAM_O_BANK1189 0x000002F4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1190 0x000002F8 +#define RFC_ULLRAM_O_BANK1190 0x000002F8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1191 0x000002FC +#define RFC_ULLRAM_O_BANK1191 0x000002FC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1192 0x00000300 +#define RFC_ULLRAM_O_BANK1192 0x00000300 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1193 0x00000304 +#define RFC_ULLRAM_O_BANK1193 0x00000304 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1194 0x00000308 +#define RFC_ULLRAM_O_BANK1194 0x00000308 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1195 0x0000030C +#define RFC_ULLRAM_O_BANK1195 0x0000030C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1196 0x00000310 +#define RFC_ULLRAM_O_BANK1196 0x00000310 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1197 0x00000314 +#define RFC_ULLRAM_O_BANK1197 0x00000314 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1198 0x00000318 +#define RFC_ULLRAM_O_BANK1198 0x00000318 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1199 0x0000031C +#define RFC_ULLRAM_O_BANK1199 0x0000031C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1200 0x00000320 +#define RFC_ULLRAM_O_BANK1200 0x00000320 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1201 0x00000324 +#define RFC_ULLRAM_O_BANK1201 0x00000324 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1202 0x00000328 +#define RFC_ULLRAM_O_BANK1202 0x00000328 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1203 0x0000032C +#define RFC_ULLRAM_O_BANK1203 0x0000032C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1204 0x00000330 +#define RFC_ULLRAM_O_BANK1204 0x00000330 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1205 0x00000334 +#define RFC_ULLRAM_O_BANK1205 0x00000334 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1206 0x00000338 +#define RFC_ULLRAM_O_BANK1206 0x00000338 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1207 0x0000033C +#define RFC_ULLRAM_O_BANK1207 0x0000033C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1208 0x00000340 +#define RFC_ULLRAM_O_BANK1208 0x00000340 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1209 0x00000344 +#define RFC_ULLRAM_O_BANK1209 0x00000344 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1210 0x00000348 +#define RFC_ULLRAM_O_BANK1210 0x00000348 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1211 0x0000034C +#define RFC_ULLRAM_O_BANK1211 0x0000034C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1212 0x00000350 +#define RFC_ULLRAM_O_BANK1212 0x00000350 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1213 0x00000354 +#define RFC_ULLRAM_O_BANK1213 0x00000354 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1214 0x00000358 +#define RFC_ULLRAM_O_BANK1214 0x00000358 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1215 0x0000035C +#define RFC_ULLRAM_O_BANK1215 0x0000035C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1216 0x00000360 +#define RFC_ULLRAM_O_BANK1216 0x00000360 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1217 0x00000364 +#define RFC_ULLRAM_O_BANK1217 0x00000364 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1218 0x00000368 +#define RFC_ULLRAM_O_BANK1218 0x00000368 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1219 0x0000036C +#define RFC_ULLRAM_O_BANK1219 0x0000036C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1220 0x00000370 +#define RFC_ULLRAM_O_BANK1220 0x00000370 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1221 0x00000374 +#define RFC_ULLRAM_O_BANK1221 0x00000374 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1222 0x00000378 +#define RFC_ULLRAM_O_BANK1222 0x00000378 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1223 0x0000037C +#define RFC_ULLRAM_O_BANK1223 0x0000037C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1224 0x00000380 +#define RFC_ULLRAM_O_BANK1224 0x00000380 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1225 0x00000384 +#define RFC_ULLRAM_O_BANK1225 0x00000384 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1226 0x00000388 +#define RFC_ULLRAM_O_BANK1226 0x00000388 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1227 0x0000038C +#define RFC_ULLRAM_O_BANK1227 0x0000038C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1228 0x00000390 +#define RFC_ULLRAM_O_BANK1228 0x00000390 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1229 0x00000394 +#define RFC_ULLRAM_O_BANK1229 0x00000394 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1230 0x00000398 +#define RFC_ULLRAM_O_BANK1230 0x00000398 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1231 0x0000039C +#define RFC_ULLRAM_O_BANK1231 0x0000039C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1232 0x000003A0 +#define RFC_ULLRAM_O_BANK1232 0x000003A0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1233 0x000003A4 +#define RFC_ULLRAM_O_BANK1233 0x000003A4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1234 0x000003A8 +#define RFC_ULLRAM_O_BANK1234 0x000003A8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1235 0x000003AC +#define RFC_ULLRAM_O_BANK1235 0x000003AC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1236 0x000003B0 +#define RFC_ULLRAM_O_BANK1236 0x000003B0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1237 0x000003B4 +#define RFC_ULLRAM_O_BANK1237 0x000003B4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1238 0x000003B8 +#define RFC_ULLRAM_O_BANK1238 0x000003B8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1239 0x000003BC +#define RFC_ULLRAM_O_BANK1239 0x000003BC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1240 0x000003C0 +#define RFC_ULLRAM_O_BANK1240 0x000003C0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1241 0x000003C4 +#define RFC_ULLRAM_O_BANK1241 0x000003C4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1242 0x000003C8 +#define RFC_ULLRAM_O_BANK1242 0x000003C8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1243 0x000003CC +#define RFC_ULLRAM_O_BANK1243 0x000003CC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1244 0x000003D0 +#define RFC_ULLRAM_O_BANK1244 0x000003D0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1245 0x000003D4 +#define RFC_ULLRAM_O_BANK1245 0x000003D4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1246 0x000003D8 +#define RFC_ULLRAM_O_BANK1246 0x000003D8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1247 0x000003DC +#define RFC_ULLRAM_O_BANK1247 0x000003DC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1248 0x000003E0 +#define RFC_ULLRAM_O_BANK1248 0x000003E0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1249 0x000003E4 +#define RFC_ULLRAM_O_BANK1249 0x000003E4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1250 0x000003E8 +#define RFC_ULLRAM_O_BANK1250 0x000003E8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1251 0x000003EC +#define RFC_ULLRAM_O_BANK1251 0x000003EC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1252 0x000003F0 +#define RFC_ULLRAM_O_BANK1252 0x000003F0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1253 0x000003F4 +#define RFC_ULLRAM_O_BANK1253 0x000003F4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1254 0x000003F8 +#define RFC_ULLRAM_O_BANK1254 0x000003F8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1255 0x000003FC +#define RFC_ULLRAM_O_BANK1255 0x000003FC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1256 0x00000400 +#define RFC_ULLRAM_O_BANK1256 0x00000400 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1257 0x00000404 +#define RFC_ULLRAM_O_BANK1257 0x00000404 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1258 0x00000408 +#define RFC_ULLRAM_O_BANK1258 0x00000408 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1259 0x0000040C +#define RFC_ULLRAM_O_BANK1259 0x0000040C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1260 0x00000410 +#define RFC_ULLRAM_O_BANK1260 0x00000410 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1261 0x00000414 +#define RFC_ULLRAM_O_BANK1261 0x00000414 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1262 0x00000418 +#define RFC_ULLRAM_O_BANK1262 0x00000418 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1263 0x0000041C +#define RFC_ULLRAM_O_BANK1263 0x0000041C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1264 0x00000420 +#define RFC_ULLRAM_O_BANK1264 0x00000420 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1265 0x00000424 +#define RFC_ULLRAM_O_BANK1265 0x00000424 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1266 0x00000428 +#define RFC_ULLRAM_O_BANK1266 0x00000428 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1267 0x0000042C +#define RFC_ULLRAM_O_BANK1267 0x0000042C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1268 0x00000430 +#define RFC_ULLRAM_O_BANK1268 0x00000430 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1269 0x00000434 +#define RFC_ULLRAM_O_BANK1269 0x00000434 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1270 0x00000438 +#define RFC_ULLRAM_O_BANK1270 0x00000438 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1271 0x0000043C +#define RFC_ULLRAM_O_BANK1271 0x0000043C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1272 0x00000440 +#define RFC_ULLRAM_O_BANK1272 0x00000440 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1273 0x00000444 +#define RFC_ULLRAM_O_BANK1273 0x00000444 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1274 0x00000448 +#define RFC_ULLRAM_O_BANK1274 0x00000448 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1275 0x0000044C +#define RFC_ULLRAM_O_BANK1275 0x0000044C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1276 0x00000450 +#define RFC_ULLRAM_O_BANK1276 0x00000450 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1277 0x00000454 +#define RFC_ULLRAM_O_BANK1277 0x00000454 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1278 0x00000458 +#define RFC_ULLRAM_O_BANK1278 0x00000458 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1279 0x0000045C +#define RFC_ULLRAM_O_BANK1279 0x0000045C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1280 0x00000460 +#define RFC_ULLRAM_O_BANK1280 0x00000460 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1281 0x00000464 +#define RFC_ULLRAM_O_BANK1281 0x00000464 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1282 0x00000468 +#define RFC_ULLRAM_O_BANK1282 0x00000468 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1283 0x0000046C +#define RFC_ULLRAM_O_BANK1283 0x0000046C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1284 0x00000470 +#define RFC_ULLRAM_O_BANK1284 0x00000470 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1285 0x00000474 +#define RFC_ULLRAM_O_BANK1285 0x00000474 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1286 0x00000478 +#define RFC_ULLRAM_O_BANK1286 0x00000478 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1287 0x0000047C +#define RFC_ULLRAM_O_BANK1287 0x0000047C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1288 0x00000480 +#define RFC_ULLRAM_O_BANK1288 0x00000480 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1289 0x00000484 +#define RFC_ULLRAM_O_BANK1289 0x00000484 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1290 0x00000488 +#define RFC_ULLRAM_O_BANK1290 0x00000488 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1291 0x0000048C +#define RFC_ULLRAM_O_BANK1291 0x0000048C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1292 0x00000490 +#define RFC_ULLRAM_O_BANK1292 0x00000490 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1293 0x00000494 +#define RFC_ULLRAM_O_BANK1293 0x00000494 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1294 0x00000498 +#define RFC_ULLRAM_O_BANK1294 0x00000498 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1295 0x0000049C +#define RFC_ULLRAM_O_BANK1295 0x0000049C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1296 0x000004A0 +#define RFC_ULLRAM_O_BANK1296 0x000004A0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1297 0x000004A4 +#define RFC_ULLRAM_O_BANK1297 0x000004A4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1298 0x000004A8 +#define RFC_ULLRAM_O_BANK1298 0x000004A8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1299 0x000004AC +#define RFC_ULLRAM_O_BANK1299 0x000004AC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1300 0x000004B0 +#define RFC_ULLRAM_O_BANK1300 0x000004B0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1301 0x000004B4 +#define RFC_ULLRAM_O_BANK1301 0x000004B4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1302 0x000004B8 +#define RFC_ULLRAM_O_BANK1302 0x000004B8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1303 0x000004BC +#define RFC_ULLRAM_O_BANK1303 0x000004BC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1304 0x000004C0 +#define RFC_ULLRAM_O_BANK1304 0x000004C0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1305 0x000004C4 +#define RFC_ULLRAM_O_BANK1305 0x000004C4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1306 0x000004C8 +#define RFC_ULLRAM_O_BANK1306 0x000004C8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1307 0x000004CC +#define RFC_ULLRAM_O_BANK1307 0x000004CC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1308 0x000004D0 +#define RFC_ULLRAM_O_BANK1308 0x000004D0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1309 0x000004D4 +#define RFC_ULLRAM_O_BANK1309 0x000004D4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1310 0x000004D8 +#define RFC_ULLRAM_O_BANK1310 0x000004D8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1311 0x000004DC +#define RFC_ULLRAM_O_BANK1311 0x000004DC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1312 0x000004E0 +#define RFC_ULLRAM_O_BANK1312 0x000004E0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1313 0x000004E4 +#define RFC_ULLRAM_O_BANK1313 0x000004E4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1314 0x000004E8 +#define RFC_ULLRAM_O_BANK1314 0x000004E8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1315 0x000004EC +#define RFC_ULLRAM_O_BANK1315 0x000004EC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1316 0x000004F0 +#define RFC_ULLRAM_O_BANK1316 0x000004F0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1317 0x000004F4 +#define RFC_ULLRAM_O_BANK1317 0x000004F4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1318 0x000004F8 +#define RFC_ULLRAM_O_BANK1318 0x000004F8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1319 0x000004FC +#define RFC_ULLRAM_O_BANK1319 0x000004FC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1320 0x00000500 +#define RFC_ULLRAM_O_BANK1320 0x00000500 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1321 0x00000504 +#define RFC_ULLRAM_O_BANK1321 0x00000504 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1322 0x00000508 +#define RFC_ULLRAM_O_BANK1322 0x00000508 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1323 0x0000050C +#define RFC_ULLRAM_O_BANK1323 0x0000050C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1324 0x00000510 +#define RFC_ULLRAM_O_BANK1324 0x00000510 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1325 0x00000514 +#define RFC_ULLRAM_O_BANK1325 0x00000514 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1326 0x00000518 +#define RFC_ULLRAM_O_BANK1326 0x00000518 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1327 0x0000051C +#define RFC_ULLRAM_O_BANK1327 0x0000051C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1328 0x00000520 +#define RFC_ULLRAM_O_BANK1328 0x00000520 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1329 0x00000524 +#define RFC_ULLRAM_O_BANK1329 0x00000524 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1330 0x00000528 +#define RFC_ULLRAM_O_BANK1330 0x00000528 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1331 0x0000052C +#define RFC_ULLRAM_O_BANK1331 0x0000052C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1332 0x00000530 +#define RFC_ULLRAM_O_BANK1332 0x00000530 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1333 0x00000534 +#define RFC_ULLRAM_O_BANK1333 0x00000534 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1334 0x00000538 +#define RFC_ULLRAM_O_BANK1334 0x00000538 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1335 0x0000053C +#define RFC_ULLRAM_O_BANK1335 0x0000053C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1336 0x00000540 +#define RFC_ULLRAM_O_BANK1336 0x00000540 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1337 0x00000544 +#define RFC_ULLRAM_O_BANK1337 0x00000544 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1338 0x00000548 +#define RFC_ULLRAM_O_BANK1338 0x00000548 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1339 0x0000054C +#define RFC_ULLRAM_O_BANK1339 0x0000054C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1340 0x00000550 +#define RFC_ULLRAM_O_BANK1340 0x00000550 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1341 0x00000554 +#define RFC_ULLRAM_O_BANK1341 0x00000554 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1342 0x00000558 +#define RFC_ULLRAM_O_BANK1342 0x00000558 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1343 0x0000055C +#define RFC_ULLRAM_O_BANK1343 0x0000055C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1344 0x00000560 +#define RFC_ULLRAM_O_BANK1344 0x00000560 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1345 0x00000564 +#define RFC_ULLRAM_O_BANK1345 0x00000564 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1346 0x00000568 +#define RFC_ULLRAM_O_BANK1346 0x00000568 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1347 0x0000056C +#define RFC_ULLRAM_O_BANK1347 0x0000056C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1348 0x00000570 +#define RFC_ULLRAM_O_BANK1348 0x00000570 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1349 0x00000574 +#define RFC_ULLRAM_O_BANK1349 0x00000574 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1350 0x00000578 +#define RFC_ULLRAM_O_BANK1350 0x00000578 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1351 0x0000057C +#define RFC_ULLRAM_O_BANK1351 0x0000057C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1352 0x00000580 +#define RFC_ULLRAM_O_BANK1352 0x00000580 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1353 0x00000584 +#define RFC_ULLRAM_O_BANK1353 0x00000584 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1354 0x00000588 +#define RFC_ULLRAM_O_BANK1354 0x00000588 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1355 0x0000058C +#define RFC_ULLRAM_O_BANK1355 0x0000058C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1356 0x00000590 +#define RFC_ULLRAM_O_BANK1356 0x00000590 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1357 0x00000594 +#define RFC_ULLRAM_O_BANK1357 0x00000594 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1358 0x00000598 +#define RFC_ULLRAM_O_BANK1358 0x00000598 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1359 0x0000059C +#define RFC_ULLRAM_O_BANK1359 0x0000059C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1360 0x000005A0 +#define RFC_ULLRAM_O_BANK1360 0x000005A0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1361 0x000005A4 +#define RFC_ULLRAM_O_BANK1361 0x000005A4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1362 0x000005A8 +#define RFC_ULLRAM_O_BANK1362 0x000005A8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1363 0x000005AC +#define RFC_ULLRAM_O_BANK1363 0x000005AC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1364 0x000005B0 +#define RFC_ULLRAM_O_BANK1364 0x000005B0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1365 0x000005B4 +#define RFC_ULLRAM_O_BANK1365 0x000005B4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1366 0x000005B8 +#define RFC_ULLRAM_O_BANK1366 0x000005B8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1367 0x000005BC +#define RFC_ULLRAM_O_BANK1367 0x000005BC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1368 0x000005C0 +#define RFC_ULLRAM_O_BANK1368 0x000005C0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1369 0x000005C4 +#define RFC_ULLRAM_O_BANK1369 0x000005C4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1370 0x000005C8 +#define RFC_ULLRAM_O_BANK1370 0x000005C8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1371 0x000005CC +#define RFC_ULLRAM_O_BANK1371 0x000005CC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1372 0x000005D0 +#define RFC_ULLRAM_O_BANK1372 0x000005D0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1373 0x000005D4 +#define RFC_ULLRAM_O_BANK1373 0x000005D4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1374 0x000005D8 +#define RFC_ULLRAM_O_BANK1374 0x000005D8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1375 0x000005DC +#define RFC_ULLRAM_O_BANK1375 0x000005DC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1376 0x000005E0 +#define RFC_ULLRAM_O_BANK1376 0x000005E0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1377 0x000005E4 +#define RFC_ULLRAM_O_BANK1377 0x000005E4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1378 0x000005E8 +#define RFC_ULLRAM_O_BANK1378 0x000005E8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1379 0x000005EC +#define RFC_ULLRAM_O_BANK1379 0x000005EC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1380 0x000005F0 +#define RFC_ULLRAM_O_BANK1380 0x000005F0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1381 0x000005F4 +#define RFC_ULLRAM_O_BANK1381 0x000005F4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1382 0x000005F8 +#define RFC_ULLRAM_O_BANK1382 0x000005F8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1383 0x000005FC +#define RFC_ULLRAM_O_BANK1383 0x000005FC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1384 0x00000600 +#define RFC_ULLRAM_O_BANK1384 0x00000600 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1385 0x00000604 +#define RFC_ULLRAM_O_BANK1385 0x00000604 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1386 0x00000608 +#define RFC_ULLRAM_O_BANK1386 0x00000608 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1387 0x0000060C +#define RFC_ULLRAM_O_BANK1387 0x0000060C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1388 0x00000610 +#define RFC_ULLRAM_O_BANK1388 0x00000610 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1389 0x00000614 +#define RFC_ULLRAM_O_BANK1389 0x00000614 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1390 0x00000618 +#define RFC_ULLRAM_O_BANK1390 0x00000618 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1391 0x0000061C +#define RFC_ULLRAM_O_BANK1391 0x0000061C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1392 0x00000620 +#define RFC_ULLRAM_O_BANK1392 0x00000620 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1393 0x00000624 +#define RFC_ULLRAM_O_BANK1393 0x00000624 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1394 0x00000628 +#define RFC_ULLRAM_O_BANK1394 0x00000628 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1395 0x0000062C +#define RFC_ULLRAM_O_BANK1395 0x0000062C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1396 0x00000630 +#define RFC_ULLRAM_O_BANK1396 0x00000630 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1397 0x00000634 +#define RFC_ULLRAM_O_BANK1397 0x00000634 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1398 0x00000638 +#define RFC_ULLRAM_O_BANK1398 0x00000638 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1399 0x0000063C +#define RFC_ULLRAM_O_BANK1399 0x0000063C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1400 0x00000640 +#define RFC_ULLRAM_O_BANK1400 0x00000640 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1401 0x00000644 +#define RFC_ULLRAM_O_BANK1401 0x00000644 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1402 0x00000648 +#define RFC_ULLRAM_O_BANK1402 0x00000648 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1403 0x0000064C +#define RFC_ULLRAM_O_BANK1403 0x0000064C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1404 0x00000650 +#define RFC_ULLRAM_O_BANK1404 0x00000650 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1405 0x00000654 +#define RFC_ULLRAM_O_BANK1405 0x00000654 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1406 0x00000658 +#define RFC_ULLRAM_O_BANK1406 0x00000658 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1407 0x0000065C +#define RFC_ULLRAM_O_BANK1407 0x0000065C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1408 0x00000660 +#define RFC_ULLRAM_O_BANK1408 0x00000660 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1409 0x00000664 +#define RFC_ULLRAM_O_BANK1409 0x00000664 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1410 0x00000668 +#define RFC_ULLRAM_O_BANK1410 0x00000668 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1411 0x0000066C +#define RFC_ULLRAM_O_BANK1411 0x0000066C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1412 0x00000670 +#define RFC_ULLRAM_O_BANK1412 0x00000670 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1413 0x00000674 +#define RFC_ULLRAM_O_BANK1413 0x00000674 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1414 0x00000678 +#define RFC_ULLRAM_O_BANK1414 0x00000678 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1415 0x0000067C +#define RFC_ULLRAM_O_BANK1415 0x0000067C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1416 0x00000680 +#define RFC_ULLRAM_O_BANK1416 0x00000680 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1417 0x00000684 +#define RFC_ULLRAM_O_BANK1417 0x00000684 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1418 0x00000688 +#define RFC_ULLRAM_O_BANK1418 0x00000688 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1419 0x0000068C +#define RFC_ULLRAM_O_BANK1419 0x0000068C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1420 0x00000690 +#define RFC_ULLRAM_O_BANK1420 0x00000690 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1421 0x00000694 +#define RFC_ULLRAM_O_BANK1421 0x00000694 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1422 0x00000698 +#define RFC_ULLRAM_O_BANK1422 0x00000698 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1423 0x0000069C +#define RFC_ULLRAM_O_BANK1423 0x0000069C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1424 0x000006A0 +#define RFC_ULLRAM_O_BANK1424 0x000006A0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1425 0x000006A4 +#define RFC_ULLRAM_O_BANK1425 0x000006A4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1426 0x000006A8 +#define RFC_ULLRAM_O_BANK1426 0x000006A8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1427 0x000006AC +#define RFC_ULLRAM_O_BANK1427 0x000006AC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1428 0x000006B0 +#define RFC_ULLRAM_O_BANK1428 0x000006B0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1429 0x000006B4 +#define RFC_ULLRAM_O_BANK1429 0x000006B4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1430 0x000006B8 +#define RFC_ULLRAM_O_BANK1430 0x000006B8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1431 0x000006BC +#define RFC_ULLRAM_O_BANK1431 0x000006BC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1432 0x000006C0 +#define RFC_ULLRAM_O_BANK1432 0x000006C0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1433 0x000006C4 +#define RFC_ULLRAM_O_BANK1433 0x000006C4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1434 0x000006C8 +#define RFC_ULLRAM_O_BANK1434 0x000006C8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1435 0x000006CC +#define RFC_ULLRAM_O_BANK1435 0x000006CC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1436 0x000006D0 +#define RFC_ULLRAM_O_BANK1436 0x000006D0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1437 0x000006D4 +#define RFC_ULLRAM_O_BANK1437 0x000006D4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1438 0x000006D8 +#define RFC_ULLRAM_O_BANK1438 0x000006D8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1439 0x000006DC +#define RFC_ULLRAM_O_BANK1439 0x000006DC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1440 0x000006E0 +#define RFC_ULLRAM_O_BANK1440 0x000006E0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1441 0x000006E4 +#define RFC_ULLRAM_O_BANK1441 0x000006E4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1442 0x000006E8 +#define RFC_ULLRAM_O_BANK1442 0x000006E8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1443 0x000006EC +#define RFC_ULLRAM_O_BANK1443 0x000006EC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1444 0x000006F0 +#define RFC_ULLRAM_O_BANK1444 0x000006F0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1445 0x000006F4 +#define RFC_ULLRAM_O_BANK1445 0x000006F4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1446 0x000006F8 +#define RFC_ULLRAM_O_BANK1446 0x000006F8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1447 0x000006FC +#define RFC_ULLRAM_O_BANK1447 0x000006FC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1448 0x00000700 +#define RFC_ULLRAM_O_BANK1448 0x00000700 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1449 0x00000704 +#define RFC_ULLRAM_O_BANK1449 0x00000704 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1450 0x00000708 +#define RFC_ULLRAM_O_BANK1450 0x00000708 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1451 0x0000070C +#define RFC_ULLRAM_O_BANK1451 0x0000070C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1452 0x00000710 +#define RFC_ULLRAM_O_BANK1452 0x00000710 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1453 0x00000714 +#define RFC_ULLRAM_O_BANK1453 0x00000714 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1454 0x00000718 +#define RFC_ULLRAM_O_BANK1454 0x00000718 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1455 0x0000071C +#define RFC_ULLRAM_O_BANK1455 0x0000071C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1456 0x00000720 +#define RFC_ULLRAM_O_BANK1456 0x00000720 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1457 0x00000724 +#define RFC_ULLRAM_O_BANK1457 0x00000724 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1458 0x00000728 +#define RFC_ULLRAM_O_BANK1458 0x00000728 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1459 0x0000072C +#define RFC_ULLRAM_O_BANK1459 0x0000072C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1460 0x00000730 +#define RFC_ULLRAM_O_BANK1460 0x00000730 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1461 0x00000734 +#define RFC_ULLRAM_O_BANK1461 0x00000734 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1462 0x00000738 +#define RFC_ULLRAM_O_BANK1462 0x00000738 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1463 0x0000073C +#define RFC_ULLRAM_O_BANK1463 0x0000073C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1464 0x00000740 +#define RFC_ULLRAM_O_BANK1464 0x00000740 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1465 0x00000744 +#define RFC_ULLRAM_O_BANK1465 0x00000744 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1466 0x00000748 +#define RFC_ULLRAM_O_BANK1466 0x00000748 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1467 0x0000074C +#define RFC_ULLRAM_O_BANK1467 0x0000074C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1468 0x00000750 +#define RFC_ULLRAM_O_BANK1468 0x00000750 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1469 0x00000754 +#define RFC_ULLRAM_O_BANK1469 0x00000754 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1470 0x00000758 +#define RFC_ULLRAM_O_BANK1470 0x00000758 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1471 0x0000075C +#define RFC_ULLRAM_O_BANK1471 0x0000075C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1472 0x00000760 +#define RFC_ULLRAM_O_BANK1472 0x00000760 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1473 0x00000764 +#define RFC_ULLRAM_O_BANK1473 0x00000764 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1474 0x00000768 +#define RFC_ULLRAM_O_BANK1474 0x00000768 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1475 0x0000076C +#define RFC_ULLRAM_O_BANK1475 0x0000076C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1476 0x00000770 +#define RFC_ULLRAM_O_BANK1476 0x00000770 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1477 0x00000774 +#define RFC_ULLRAM_O_BANK1477 0x00000774 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1478 0x00000778 +#define RFC_ULLRAM_O_BANK1478 0x00000778 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1479 0x0000077C +#define RFC_ULLRAM_O_BANK1479 0x0000077C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1480 0x00000780 +#define RFC_ULLRAM_O_BANK1480 0x00000780 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1481 0x00000784 +#define RFC_ULLRAM_O_BANK1481 0x00000784 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1482 0x00000788 +#define RFC_ULLRAM_O_BANK1482 0x00000788 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1483 0x0000078C +#define RFC_ULLRAM_O_BANK1483 0x0000078C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1484 0x00000790 +#define RFC_ULLRAM_O_BANK1484 0x00000790 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1485 0x00000794 +#define RFC_ULLRAM_O_BANK1485 0x00000794 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1486 0x00000798 +#define RFC_ULLRAM_O_BANK1486 0x00000798 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1487 0x0000079C +#define RFC_ULLRAM_O_BANK1487 0x0000079C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1488 0x000007A0 +#define RFC_ULLRAM_O_BANK1488 0x000007A0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1489 0x000007A4 +#define RFC_ULLRAM_O_BANK1489 0x000007A4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1490 0x000007A8 +#define RFC_ULLRAM_O_BANK1490 0x000007A8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1491 0x000007AC +#define RFC_ULLRAM_O_BANK1491 0x000007AC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1492 0x000007B0 +#define RFC_ULLRAM_O_BANK1492 0x000007B0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1493 0x000007B4 +#define RFC_ULLRAM_O_BANK1493 0x000007B4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1494 0x000007B8 +#define RFC_ULLRAM_O_BANK1494 0x000007B8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1495 0x000007BC +#define RFC_ULLRAM_O_BANK1495 0x000007BC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1496 0x000007C0 +#define RFC_ULLRAM_O_BANK1496 0x000007C0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1497 0x000007C4 +#define RFC_ULLRAM_O_BANK1497 0x000007C4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1498 0x000007C8 +#define RFC_ULLRAM_O_BANK1498 0x000007C8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1499 0x000007CC +#define RFC_ULLRAM_O_BANK1499 0x000007CC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1500 0x000007D0 +#define RFC_ULLRAM_O_BANK1500 0x000007D0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1501 0x000007D4 +#define RFC_ULLRAM_O_BANK1501 0x000007D4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1502 0x000007D8 +#define RFC_ULLRAM_O_BANK1502 0x000007D8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1503 0x000007DC +#define RFC_ULLRAM_O_BANK1503 0x000007DC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1504 0x000007E0 +#define RFC_ULLRAM_O_BANK1504 0x000007E0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1505 0x000007E4 +#define RFC_ULLRAM_O_BANK1505 0x000007E4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1506 0x000007E8 +#define RFC_ULLRAM_O_BANK1506 0x000007E8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1507 0x000007EC +#define RFC_ULLRAM_O_BANK1507 0x000007EC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1508 0x000007F0 +#define RFC_ULLRAM_O_BANK1508 0x000007F0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1509 0x000007F4 +#define RFC_ULLRAM_O_BANK1509 0x000007F4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1510 0x000007F8 +#define RFC_ULLRAM_O_BANK1510 0x000007F8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1511 0x000007FC +#define RFC_ULLRAM_O_BANK1511 0x000007FC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1512 0x00000800 +#define RFC_ULLRAM_O_BANK1512 0x00000800 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1513 0x00000804 +#define RFC_ULLRAM_O_BANK1513 0x00000804 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1514 0x00000808 +#define RFC_ULLRAM_O_BANK1514 0x00000808 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1515 0x0000080C +#define RFC_ULLRAM_O_BANK1515 0x0000080C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1516 0x00000810 +#define RFC_ULLRAM_O_BANK1516 0x00000810 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1517 0x00000814 +#define RFC_ULLRAM_O_BANK1517 0x00000814 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1518 0x00000818 +#define RFC_ULLRAM_O_BANK1518 0x00000818 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1519 0x0000081C +#define RFC_ULLRAM_O_BANK1519 0x0000081C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1520 0x00000820 +#define RFC_ULLRAM_O_BANK1520 0x00000820 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1521 0x00000824 +#define RFC_ULLRAM_O_BANK1521 0x00000824 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1522 0x00000828 +#define RFC_ULLRAM_O_BANK1522 0x00000828 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1523 0x0000082C +#define RFC_ULLRAM_O_BANK1523 0x0000082C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1524 0x00000830 +#define RFC_ULLRAM_O_BANK1524 0x00000830 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1525 0x00000834 +#define RFC_ULLRAM_O_BANK1525 0x00000834 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1526 0x00000838 +#define RFC_ULLRAM_O_BANK1526 0x00000838 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1527 0x0000083C +#define RFC_ULLRAM_O_BANK1527 0x0000083C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1528 0x00000840 +#define RFC_ULLRAM_O_BANK1528 0x00000840 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1529 0x00000844 +#define RFC_ULLRAM_O_BANK1529 0x00000844 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1530 0x00000848 +#define RFC_ULLRAM_O_BANK1530 0x00000848 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1531 0x0000084C +#define RFC_ULLRAM_O_BANK1531 0x0000084C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1532 0x00000850 +#define RFC_ULLRAM_O_BANK1532 0x00000850 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1533 0x00000854 +#define RFC_ULLRAM_O_BANK1533 0x00000854 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1534 0x00000858 +#define RFC_ULLRAM_O_BANK1534 0x00000858 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1535 0x0000085C +#define RFC_ULLRAM_O_BANK1535 0x0000085C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1536 0x00000860 +#define RFC_ULLRAM_O_BANK1536 0x00000860 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1537 0x00000864 +#define RFC_ULLRAM_O_BANK1537 0x00000864 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1538 0x00000868 +#define RFC_ULLRAM_O_BANK1538 0x00000868 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1539 0x0000086C +#define RFC_ULLRAM_O_BANK1539 0x0000086C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1540 0x00000870 +#define RFC_ULLRAM_O_BANK1540 0x00000870 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1541 0x00000874 +#define RFC_ULLRAM_O_BANK1541 0x00000874 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1542 0x00000878 +#define RFC_ULLRAM_O_BANK1542 0x00000878 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1543 0x0000087C +#define RFC_ULLRAM_O_BANK1543 0x0000087C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1544 0x00000880 +#define RFC_ULLRAM_O_BANK1544 0x00000880 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1545 0x00000884 +#define RFC_ULLRAM_O_BANK1545 0x00000884 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1546 0x00000888 +#define RFC_ULLRAM_O_BANK1546 0x00000888 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1547 0x0000088C +#define RFC_ULLRAM_O_BANK1547 0x0000088C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1548 0x00000890 +#define RFC_ULLRAM_O_BANK1548 0x00000890 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1549 0x00000894 +#define RFC_ULLRAM_O_BANK1549 0x00000894 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1550 0x00000898 +#define RFC_ULLRAM_O_BANK1550 0x00000898 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1551 0x0000089C +#define RFC_ULLRAM_O_BANK1551 0x0000089C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1552 0x000008A0 +#define RFC_ULLRAM_O_BANK1552 0x000008A0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1553 0x000008A4 +#define RFC_ULLRAM_O_BANK1553 0x000008A4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1554 0x000008A8 +#define RFC_ULLRAM_O_BANK1554 0x000008A8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1555 0x000008AC +#define RFC_ULLRAM_O_BANK1555 0x000008AC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1556 0x000008B0 +#define RFC_ULLRAM_O_BANK1556 0x000008B0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1557 0x000008B4 +#define RFC_ULLRAM_O_BANK1557 0x000008B4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1558 0x000008B8 +#define RFC_ULLRAM_O_BANK1558 0x000008B8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1559 0x000008BC +#define RFC_ULLRAM_O_BANK1559 0x000008BC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1560 0x000008C0 +#define RFC_ULLRAM_O_BANK1560 0x000008C0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1561 0x000008C4 +#define RFC_ULLRAM_O_BANK1561 0x000008C4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1562 0x000008C8 +#define RFC_ULLRAM_O_BANK1562 0x000008C8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1563 0x000008CC +#define RFC_ULLRAM_O_BANK1563 0x000008CC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1564 0x000008D0 +#define RFC_ULLRAM_O_BANK1564 0x000008D0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1565 0x000008D4 +#define RFC_ULLRAM_O_BANK1565 0x000008D4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1566 0x000008D8 +#define RFC_ULLRAM_O_BANK1566 0x000008D8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1567 0x000008DC +#define RFC_ULLRAM_O_BANK1567 0x000008DC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1568 0x000008E0 +#define RFC_ULLRAM_O_BANK1568 0x000008E0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1569 0x000008E4 +#define RFC_ULLRAM_O_BANK1569 0x000008E4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1570 0x000008E8 +#define RFC_ULLRAM_O_BANK1570 0x000008E8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1571 0x000008EC +#define RFC_ULLRAM_O_BANK1571 0x000008EC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1572 0x000008F0 +#define RFC_ULLRAM_O_BANK1572 0x000008F0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1573 0x000008F4 +#define RFC_ULLRAM_O_BANK1573 0x000008F4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1574 0x000008F8 +#define RFC_ULLRAM_O_BANK1574 0x000008F8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1575 0x000008FC +#define RFC_ULLRAM_O_BANK1575 0x000008FC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1576 0x00000900 +#define RFC_ULLRAM_O_BANK1576 0x00000900 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1577 0x00000904 +#define RFC_ULLRAM_O_BANK1577 0x00000904 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1578 0x00000908 +#define RFC_ULLRAM_O_BANK1578 0x00000908 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1579 0x0000090C +#define RFC_ULLRAM_O_BANK1579 0x0000090C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1580 0x00000910 +#define RFC_ULLRAM_O_BANK1580 0x00000910 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1581 0x00000914 +#define RFC_ULLRAM_O_BANK1581 0x00000914 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1582 0x00000918 +#define RFC_ULLRAM_O_BANK1582 0x00000918 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1583 0x0000091C +#define RFC_ULLRAM_O_BANK1583 0x0000091C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1584 0x00000920 +#define RFC_ULLRAM_O_BANK1584 0x00000920 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1585 0x00000924 +#define RFC_ULLRAM_O_BANK1585 0x00000924 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1586 0x00000928 +#define RFC_ULLRAM_O_BANK1586 0x00000928 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1587 0x0000092C +#define RFC_ULLRAM_O_BANK1587 0x0000092C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1588 0x00000930 +#define RFC_ULLRAM_O_BANK1588 0x00000930 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1589 0x00000934 +#define RFC_ULLRAM_O_BANK1589 0x00000934 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1590 0x00000938 +#define RFC_ULLRAM_O_BANK1590 0x00000938 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1591 0x0000093C +#define RFC_ULLRAM_O_BANK1591 0x0000093C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1592 0x00000940 +#define RFC_ULLRAM_O_BANK1592 0x00000940 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1593 0x00000944 +#define RFC_ULLRAM_O_BANK1593 0x00000944 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1594 0x00000948 +#define RFC_ULLRAM_O_BANK1594 0x00000948 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1595 0x0000094C +#define RFC_ULLRAM_O_BANK1595 0x0000094C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1596 0x00000950 +#define RFC_ULLRAM_O_BANK1596 0x00000950 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1597 0x00000954 +#define RFC_ULLRAM_O_BANK1597 0x00000954 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1598 0x00000958 +#define RFC_ULLRAM_O_BANK1598 0x00000958 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1599 0x0000095C +#define RFC_ULLRAM_O_BANK1599 0x0000095C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1600 0x00000960 +#define RFC_ULLRAM_O_BANK1600 0x00000960 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1601 0x00000964 +#define RFC_ULLRAM_O_BANK1601 0x00000964 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1602 0x00000968 +#define RFC_ULLRAM_O_BANK1602 0x00000968 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1603 0x0000096C +#define RFC_ULLRAM_O_BANK1603 0x0000096C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1604 0x00000970 +#define RFC_ULLRAM_O_BANK1604 0x00000970 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1605 0x00000974 +#define RFC_ULLRAM_O_BANK1605 0x00000974 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1606 0x00000978 +#define RFC_ULLRAM_O_BANK1606 0x00000978 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1607 0x0000097C +#define RFC_ULLRAM_O_BANK1607 0x0000097C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1608 0x00000980 +#define RFC_ULLRAM_O_BANK1608 0x00000980 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1609 0x00000984 +#define RFC_ULLRAM_O_BANK1609 0x00000984 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1610 0x00000988 +#define RFC_ULLRAM_O_BANK1610 0x00000988 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1611 0x0000098C +#define RFC_ULLRAM_O_BANK1611 0x0000098C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1612 0x00000990 +#define RFC_ULLRAM_O_BANK1612 0x00000990 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1613 0x00000994 +#define RFC_ULLRAM_O_BANK1613 0x00000994 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1614 0x00000998 +#define RFC_ULLRAM_O_BANK1614 0x00000998 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1615 0x0000099C +#define RFC_ULLRAM_O_BANK1615 0x0000099C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1616 0x000009A0 +#define RFC_ULLRAM_O_BANK1616 0x000009A0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1617 0x000009A4 +#define RFC_ULLRAM_O_BANK1617 0x000009A4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1618 0x000009A8 +#define RFC_ULLRAM_O_BANK1618 0x000009A8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1619 0x000009AC +#define RFC_ULLRAM_O_BANK1619 0x000009AC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1620 0x000009B0 +#define RFC_ULLRAM_O_BANK1620 0x000009B0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1621 0x000009B4 +#define RFC_ULLRAM_O_BANK1621 0x000009B4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1622 0x000009B8 +#define RFC_ULLRAM_O_BANK1622 0x000009B8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1623 0x000009BC +#define RFC_ULLRAM_O_BANK1623 0x000009BC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1624 0x000009C0 +#define RFC_ULLRAM_O_BANK1624 0x000009C0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1625 0x000009C4 +#define RFC_ULLRAM_O_BANK1625 0x000009C4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1626 0x000009C8 +#define RFC_ULLRAM_O_BANK1626 0x000009C8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1627 0x000009CC +#define RFC_ULLRAM_O_BANK1627 0x000009CC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1628 0x000009D0 +#define RFC_ULLRAM_O_BANK1628 0x000009D0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1629 0x000009D4 +#define RFC_ULLRAM_O_BANK1629 0x000009D4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1630 0x000009D8 +#define RFC_ULLRAM_O_BANK1630 0x000009D8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1631 0x000009DC +#define RFC_ULLRAM_O_BANK1631 0x000009DC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1632 0x000009E0 +#define RFC_ULLRAM_O_BANK1632 0x000009E0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1633 0x000009E4 +#define RFC_ULLRAM_O_BANK1633 0x000009E4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1634 0x000009E8 +#define RFC_ULLRAM_O_BANK1634 0x000009E8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1635 0x000009EC +#define RFC_ULLRAM_O_BANK1635 0x000009EC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1636 0x000009F0 +#define RFC_ULLRAM_O_BANK1636 0x000009F0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1637 0x000009F4 +#define RFC_ULLRAM_O_BANK1637 0x000009F4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1638 0x000009F8 +#define RFC_ULLRAM_O_BANK1638 0x000009F8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1639 0x000009FC +#define RFC_ULLRAM_O_BANK1639 0x000009FC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1640 0x00000A00 +#define RFC_ULLRAM_O_BANK1640 0x00000A00 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1641 0x00000A04 +#define RFC_ULLRAM_O_BANK1641 0x00000A04 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1642 0x00000A08 +#define RFC_ULLRAM_O_BANK1642 0x00000A08 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1643 0x00000A0C +#define RFC_ULLRAM_O_BANK1643 0x00000A0C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1644 0x00000A10 +#define RFC_ULLRAM_O_BANK1644 0x00000A10 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1645 0x00000A14 +#define RFC_ULLRAM_O_BANK1645 0x00000A14 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1646 0x00000A18 +#define RFC_ULLRAM_O_BANK1646 0x00000A18 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1647 0x00000A1C +#define RFC_ULLRAM_O_BANK1647 0x00000A1C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1648 0x00000A20 +#define RFC_ULLRAM_O_BANK1648 0x00000A20 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1649 0x00000A24 +#define RFC_ULLRAM_O_BANK1649 0x00000A24 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1650 0x00000A28 +#define RFC_ULLRAM_O_BANK1650 0x00000A28 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1651 0x00000A2C +#define RFC_ULLRAM_O_BANK1651 0x00000A2C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1652 0x00000A30 +#define RFC_ULLRAM_O_BANK1652 0x00000A30 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1653 0x00000A34 +#define RFC_ULLRAM_O_BANK1653 0x00000A34 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1654 0x00000A38 +#define RFC_ULLRAM_O_BANK1654 0x00000A38 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1655 0x00000A3C +#define RFC_ULLRAM_O_BANK1655 0x00000A3C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1656 0x00000A40 +#define RFC_ULLRAM_O_BANK1656 0x00000A40 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1657 0x00000A44 +#define RFC_ULLRAM_O_BANK1657 0x00000A44 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1658 0x00000A48 +#define RFC_ULLRAM_O_BANK1658 0x00000A48 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1659 0x00000A4C +#define RFC_ULLRAM_O_BANK1659 0x00000A4C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1660 0x00000A50 +#define RFC_ULLRAM_O_BANK1660 0x00000A50 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1661 0x00000A54 +#define RFC_ULLRAM_O_BANK1661 0x00000A54 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1662 0x00000A58 +#define RFC_ULLRAM_O_BANK1662 0x00000A58 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1663 0x00000A5C +#define RFC_ULLRAM_O_BANK1663 0x00000A5C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1664 0x00000A60 +#define RFC_ULLRAM_O_BANK1664 0x00000A60 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1665 0x00000A64 +#define RFC_ULLRAM_O_BANK1665 0x00000A64 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1666 0x00000A68 +#define RFC_ULLRAM_O_BANK1666 0x00000A68 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1667 0x00000A6C +#define RFC_ULLRAM_O_BANK1667 0x00000A6C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1668 0x00000A70 +#define RFC_ULLRAM_O_BANK1668 0x00000A70 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1669 0x00000A74 +#define RFC_ULLRAM_O_BANK1669 0x00000A74 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1670 0x00000A78 +#define RFC_ULLRAM_O_BANK1670 0x00000A78 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1671 0x00000A7C +#define RFC_ULLRAM_O_BANK1671 0x00000A7C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1672 0x00000A80 +#define RFC_ULLRAM_O_BANK1672 0x00000A80 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1673 0x00000A84 +#define RFC_ULLRAM_O_BANK1673 0x00000A84 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1674 0x00000A88 +#define RFC_ULLRAM_O_BANK1674 0x00000A88 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1675 0x00000A8C +#define RFC_ULLRAM_O_BANK1675 0x00000A8C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1676 0x00000A90 +#define RFC_ULLRAM_O_BANK1676 0x00000A90 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1677 0x00000A94 +#define RFC_ULLRAM_O_BANK1677 0x00000A94 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1678 0x00000A98 +#define RFC_ULLRAM_O_BANK1678 0x00000A98 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1679 0x00000A9C +#define RFC_ULLRAM_O_BANK1679 0x00000A9C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1680 0x00000AA0 +#define RFC_ULLRAM_O_BANK1680 0x00000AA0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1681 0x00000AA4 +#define RFC_ULLRAM_O_BANK1681 0x00000AA4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1682 0x00000AA8 +#define RFC_ULLRAM_O_BANK1682 0x00000AA8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1683 0x00000AAC +#define RFC_ULLRAM_O_BANK1683 0x00000AAC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1684 0x00000AB0 +#define RFC_ULLRAM_O_BANK1684 0x00000AB0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1685 0x00000AB4 +#define RFC_ULLRAM_O_BANK1685 0x00000AB4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1686 0x00000AB8 +#define RFC_ULLRAM_O_BANK1686 0x00000AB8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1687 0x00000ABC +#define RFC_ULLRAM_O_BANK1687 0x00000ABC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1688 0x00000AC0 +#define RFC_ULLRAM_O_BANK1688 0x00000AC0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1689 0x00000AC4 +#define RFC_ULLRAM_O_BANK1689 0x00000AC4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1690 0x00000AC8 +#define RFC_ULLRAM_O_BANK1690 0x00000AC8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1691 0x00000ACC +#define RFC_ULLRAM_O_BANK1691 0x00000ACC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1692 0x00000AD0 +#define RFC_ULLRAM_O_BANK1692 0x00000AD0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1693 0x00000AD4 +#define RFC_ULLRAM_O_BANK1693 0x00000AD4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1694 0x00000AD8 +#define RFC_ULLRAM_O_BANK1694 0x00000AD8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1695 0x00000ADC +#define RFC_ULLRAM_O_BANK1695 0x00000ADC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1696 0x00000AE0 +#define RFC_ULLRAM_O_BANK1696 0x00000AE0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1697 0x00000AE4 +#define RFC_ULLRAM_O_BANK1697 0x00000AE4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1698 0x00000AE8 +#define RFC_ULLRAM_O_BANK1698 0x00000AE8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1699 0x00000AEC +#define RFC_ULLRAM_O_BANK1699 0x00000AEC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1700 0x00000AF0 +#define RFC_ULLRAM_O_BANK1700 0x00000AF0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1701 0x00000AF4 +#define RFC_ULLRAM_O_BANK1701 0x00000AF4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1702 0x00000AF8 +#define RFC_ULLRAM_O_BANK1702 0x00000AF8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1703 0x00000AFC +#define RFC_ULLRAM_O_BANK1703 0x00000AFC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1704 0x00000B00 +#define RFC_ULLRAM_O_BANK1704 0x00000B00 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1705 0x00000B04 +#define RFC_ULLRAM_O_BANK1705 0x00000B04 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1706 0x00000B08 +#define RFC_ULLRAM_O_BANK1706 0x00000B08 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1707 0x00000B0C +#define RFC_ULLRAM_O_BANK1707 0x00000B0C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1708 0x00000B10 +#define RFC_ULLRAM_O_BANK1708 0x00000B10 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1709 0x00000B14 +#define RFC_ULLRAM_O_BANK1709 0x00000B14 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1710 0x00000B18 +#define RFC_ULLRAM_O_BANK1710 0x00000B18 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1711 0x00000B1C +#define RFC_ULLRAM_O_BANK1711 0x00000B1C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1712 0x00000B20 +#define RFC_ULLRAM_O_BANK1712 0x00000B20 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1713 0x00000B24 +#define RFC_ULLRAM_O_BANK1713 0x00000B24 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1714 0x00000B28 +#define RFC_ULLRAM_O_BANK1714 0x00000B28 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1715 0x00000B2C +#define RFC_ULLRAM_O_BANK1715 0x00000B2C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1716 0x00000B30 +#define RFC_ULLRAM_O_BANK1716 0x00000B30 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1717 0x00000B34 +#define RFC_ULLRAM_O_BANK1717 0x00000B34 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1718 0x00000B38 +#define RFC_ULLRAM_O_BANK1718 0x00000B38 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1719 0x00000B3C +#define RFC_ULLRAM_O_BANK1719 0x00000B3C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1720 0x00000B40 +#define RFC_ULLRAM_O_BANK1720 0x00000B40 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1721 0x00000B44 +#define RFC_ULLRAM_O_BANK1721 0x00000B44 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1722 0x00000B48 +#define RFC_ULLRAM_O_BANK1722 0x00000B48 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1723 0x00000B4C +#define RFC_ULLRAM_O_BANK1723 0x00000B4C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1724 0x00000B50 +#define RFC_ULLRAM_O_BANK1724 0x00000B50 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1725 0x00000B54 +#define RFC_ULLRAM_O_BANK1725 0x00000B54 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1726 0x00000B58 +#define RFC_ULLRAM_O_BANK1726 0x00000B58 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1727 0x00000B5C +#define RFC_ULLRAM_O_BANK1727 0x00000B5C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1728 0x00000B60 +#define RFC_ULLRAM_O_BANK1728 0x00000B60 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1729 0x00000B64 +#define RFC_ULLRAM_O_BANK1729 0x00000B64 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1730 0x00000B68 +#define RFC_ULLRAM_O_BANK1730 0x00000B68 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1731 0x00000B6C +#define RFC_ULLRAM_O_BANK1731 0x00000B6C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1732 0x00000B70 +#define RFC_ULLRAM_O_BANK1732 0x00000B70 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1733 0x00000B74 +#define RFC_ULLRAM_O_BANK1733 0x00000B74 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1734 0x00000B78 +#define RFC_ULLRAM_O_BANK1734 0x00000B78 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1735 0x00000B7C +#define RFC_ULLRAM_O_BANK1735 0x00000B7C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1736 0x00000B80 +#define RFC_ULLRAM_O_BANK1736 0x00000B80 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1737 0x00000B84 +#define RFC_ULLRAM_O_BANK1737 0x00000B84 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1738 0x00000B88 +#define RFC_ULLRAM_O_BANK1738 0x00000B88 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1739 0x00000B8C +#define RFC_ULLRAM_O_BANK1739 0x00000B8C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1740 0x00000B90 +#define RFC_ULLRAM_O_BANK1740 0x00000B90 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1741 0x00000B94 +#define RFC_ULLRAM_O_BANK1741 0x00000B94 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1742 0x00000B98 +#define RFC_ULLRAM_O_BANK1742 0x00000B98 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1743 0x00000B9C +#define RFC_ULLRAM_O_BANK1743 0x00000B9C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1744 0x00000BA0 +#define RFC_ULLRAM_O_BANK1744 0x00000BA0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1745 0x00000BA4 +#define RFC_ULLRAM_O_BANK1745 0x00000BA4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1746 0x00000BA8 +#define RFC_ULLRAM_O_BANK1746 0x00000BA8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1747 0x00000BAC +#define RFC_ULLRAM_O_BANK1747 0x00000BAC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1748 0x00000BB0 +#define RFC_ULLRAM_O_BANK1748 0x00000BB0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1749 0x00000BB4 +#define RFC_ULLRAM_O_BANK1749 0x00000BB4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1750 0x00000BB8 +#define RFC_ULLRAM_O_BANK1750 0x00000BB8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1751 0x00000BBC +#define RFC_ULLRAM_O_BANK1751 0x00000BBC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1752 0x00000BC0 +#define RFC_ULLRAM_O_BANK1752 0x00000BC0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1753 0x00000BC4 +#define RFC_ULLRAM_O_BANK1753 0x00000BC4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1754 0x00000BC8 +#define RFC_ULLRAM_O_BANK1754 0x00000BC8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1755 0x00000BCC +#define RFC_ULLRAM_O_BANK1755 0x00000BCC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1756 0x00000BD0 +#define RFC_ULLRAM_O_BANK1756 0x00000BD0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1757 0x00000BD4 +#define RFC_ULLRAM_O_BANK1757 0x00000BD4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1758 0x00000BD8 +#define RFC_ULLRAM_O_BANK1758 0x00000BD8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1759 0x00000BDC +#define RFC_ULLRAM_O_BANK1759 0x00000BDC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1760 0x00000BE0 +#define RFC_ULLRAM_O_BANK1760 0x00000BE0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1761 0x00000BE4 +#define RFC_ULLRAM_O_BANK1761 0x00000BE4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1762 0x00000BE8 +#define RFC_ULLRAM_O_BANK1762 0x00000BE8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1763 0x00000BEC +#define RFC_ULLRAM_O_BANK1763 0x00000BEC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1764 0x00000BF0 +#define RFC_ULLRAM_O_BANK1764 0x00000BF0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1765 0x00000BF4 +#define RFC_ULLRAM_O_BANK1765 0x00000BF4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1766 0x00000BF8 +#define RFC_ULLRAM_O_BANK1766 0x00000BF8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1767 0x00000BFC +#define RFC_ULLRAM_O_BANK1767 0x00000BFC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1768 0x00000C00 +#define RFC_ULLRAM_O_BANK1768 0x00000C00 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1769 0x00000C04 +#define RFC_ULLRAM_O_BANK1769 0x00000C04 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1770 0x00000C08 +#define RFC_ULLRAM_O_BANK1770 0x00000C08 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1771 0x00000C0C +#define RFC_ULLRAM_O_BANK1771 0x00000C0C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1772 0x00000C10 +#define RFC_ULLRAM_O_BANK1772 0x00000C10 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1773 0x00000C14 +#define RFC_ULLRAM_O_BANK1773 0x00000C14 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1774 0x00000C18 +#define RFC_ULLRAM_O_BANK1774 0x00000C18 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1775 0x00000C1C +#define RFC_ULLRAM_O_BANK1775 0x00000C1C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1776 0x00000C20 +#define RFC_ULLRAM_O_BANK1776 0x00000C20 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1777 0x00000C24 +#define RFC_ULLRAM_O_BANK1777 0x00000C24 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1778 0x00000C28 +#define RFC_ULLRAM_O_BANK1778 0x00000C28 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1779 0x00000C2C +#define RFC_ULLRAM_O_BANK1779 0x00000C2C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1780 0x00000C30 +#define RFC_ULLRAM_O_BANK1780 0x00000C30 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1781 0x00000C34 +#define RFC_ULLRAM_O_BANK1781 0x00000C34 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1782 0x00000C38 +#define RFC_ULLRAM_O_BANK1782 0x00000C38 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1783 0x00000C3C +#define RFC_ULLRAM_O_BANK1783 0x00000C3C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1784 0x00000C40 +#define RFC_ULLRAM_O_BANK1784 0x00000C40 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1785 0x00000C44 +#define RFC_ULLRAM_O_BANK1785 0x00000C44 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1786 0x00000C48 +#define RFC_ULLRAM_O_BANK1786 0x00000C48 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1787 0x00000C4C +#define RFC_ULLRAM_O_BANK1787 0x00000C4C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1788 0x00000C50 +#define RFC_ULLRAM_O_BANK1788 0x00000C50 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1789 0x00000C54 +#define RFC_ULLRAM_O_BANK1789 0x00000C54 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1790 0x00000C58 +#define RFC_ULLRAM_O_BANK1790 0x00000C58 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1791 0x00000C5C +#define RFC_ULLRAM_O_BANK1791 0x00000C5C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1792 0x00000C60 +#define RFC_ULLRAM_O_BANK1792 0x00000C60 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1793 0x00000C64 +#define RFC_ULLRAM_O_BANK1793 0x00000C64 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1794 0x00000C68 +#define RFC_ULLRAM_O_BANK1794 0x00000C68 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1795 0x00000C6C +#define RFC_ULLRAM_O_BANK1795 0x00000C6C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1796 0x00000C70 +#define RFC_ULLRAM_O_BANK1796 0x00000C70 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1797 0x00000C74 +#define RFC_ULLRAM_O_BANK1797 0x00000C74 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1798 0x00000C78 +#define RFC_ULLRAM_O_BANK1798 0x00000C78 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1799 0x00000C7C +#define RFC_ULLRAM_O_BANK1799 0x00000C7C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1800 0x00000C80 +#define RFC_ULLRAM_O_BANK1800 0x00000C80 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1801 0x00000C84 +#define RFC_ULLRAM_O_BANK1801 0x00000C84 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1802 0x00000C88 +#define RFC_ULLRAM_O_BANK1802 0x00000C88 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1803 0x00000C8C +#define RFC_ULLRAM_O_BANK1803 0x00000C8C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1804 0x00000C90 +#define RFC_ULLRAM_O_BANK1804 0x00000C90 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1805 0x00000C94 +#define RFC_ULLRAM_O_BANK1805 0x00000C94 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1806 0x00000C98 +#define RFC_ULLRAM_O_BANK1806 0x00000C98 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1807 0x00000C9C +#define RFC_ULLRAM_O_BANK1807 0x00000C9C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1808 0x00000CA0 +#define RFC_ULLRAM_O_BANK1808 0x00000CA0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1809 0x00000CA4 +#define RFC_ULLRAM_O_BANK1809 0x00000CA4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1810 0x00000CA8 +#define RFC_ULLRAM_O_BANK1810 0x00000CA8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1811 0x00000CAC +#define RFC_ULLRAM_O_BANK1811 0x00000CAC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1812 0x00000CB0 +#define RFC_ULLRAM_O_BANK1812 0x00000CB0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1813 0x00000CB4 +#define RFC_ULLRAM_O_BANK1813 0x00000CB4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1814 0x00000CB8 +#define RFC_ULLRAM_O_BANK1814 0x00000CB8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1815 0x00000CBC +#define RFC_ULLRAM_O_BANK1815 0x00000CBC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1816 0x00000CC0 +#define RFC_ULLRAM_O_BANK1816 0x00000CC0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1817 0x00000CC4 +#define RFC_ULLRAM_O_BANK1817 0x00000CC4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1818 0x00000CC8 +#define RFC_ULLRAM_O_BANK1818 0x00000CC8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1819 0x00000CCC +#define RFC_ULLRAM_O_BANK1819 0x00000CCC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1820 0x00000CD0 +#define RFC_ULLRAM_O_BANK1820 0x00000CD0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1821 0x00000CD4 +#define RFC_ULLRAM_O_BANK1821 0x00000CD4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1822 0x00000CD8 +#define RFC_ULLRAM_O_BANK1822 0x00000CD8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1823 0x00000CDC +#define RFC_ULLRAM_O_BANK1823 0x00000CDC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1824 0x00000CE0 +#define RFC_ULLRAM_O_BANK1824 0x00000CE0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1825 0x00000CE4 +#define RFC_ULLRAM_O_BANK1825 0x00000CE4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1826 0x00000CE8 +#define RFC_ULLRAM_O_BANK1826 0x00000CE8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1827 0x00000CEC +#define RFC_ULLRAM_O_BANK1827 0x00000CEC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1828 0x00000CF0 +#define RFC_ULLRAM_O_BANK1828 0x00000CF0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1829 0x00000CF4 +#define RFC_ULLRAM_O_BANK1829 0x00000CF4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1830 0x00000CF8 +#define RFC_ULLRAM_O_BANK1830 0x00000CF8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1831 0x00000CFC +#define RFC_ULLRAM_O_BANK1831 0x00000CFC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1832 0x00000D00 +#define RFC_ULLRAM_O_BANK1832 0x00000D00 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1833 0x00000D04 +#define RFC_ULLRAM_O_BANK1833 0x00000D04 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1834 0x00000D08 +#define RFC_ULLRAM_O_BANK1834 0x00000D08 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1835 0x00000D0C +#define RFC_ULLRAM_O_BANK1835 0x00000D0C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1836 0x00000D10 +#define RFC_ULLRAM_O_BANK1836 0x00000D10 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1837 0x00000D14 +#define RFC_ULLRAM_O_BANK1837 0x00000D14 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1838 0x00000D18 +#define RFC_ULLRAM_O_BANK1838 0x00000D18 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1839 0x00000D1C +#define RFC_ULLRAM_O_BANK1839 0x00000D1C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1840 0x00000D20 +#define RFC_ULLRAM_O_BANK1840 0x00000D20 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1841 0x00000D24 +#define RFC_ULLRAM_O_BANK1841 0x00000D24 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1842 0x00000D28 +#define RFC_ULLRAM_O_BANK1842 0x00000D28 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1843 0x00000D2C +#define RFC_ULLRAM_O_BANK1843 0x00000D2C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1844 0x00000D30 +#define RFC_ULLRAM_O_BANK1844 0x00000D30 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1845 0x00000D34 +#define RFC_ULLRAM_O_BANK1845 0x00000D34 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1846 0x00000D38 +#define RFC_ULLRAM_O_BANK1846 0x00000D38 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1847 0x00000D3C +#define RFC_ULLRAM_O_BANK1847 0x00000D3C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1848 0x00000D40 +#define RFC_ULLRAM_O_BANK1848 0x00000D40 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1849 0x00000D44 +#define RFC_ULLRAM_O_BANK1849 0x00000D44 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1850 0x00000D48 +#define RFC_ULLRAM_O_BANK1850 0x00000D48 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1851 0x00000D4C +#define RFC_ULLRAM_O_BANK1851 0x00000D4C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1852 0x00000D50 +#define RFC_ULLRAM_O_BANK1852 0x00000D50 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1853 0x00000D54 +#define RFC_ULLRAM_O_BANK1853 0x00000D54 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1854 0x00000D58 +#define RFC_ULLRAM_O_BANK1854 0x00000D58 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1855 0x00000D5C +#define RFC_ULLRAM_O_BANK1855 0x00000D5C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1856 0x00000D60 +#define RFC_ULLRAM_O_BANK1856 0x00000D60 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1857 0x00000D64 +#define RFC_ULLRAM_O_BANK1857 0x00000D64 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1858 0x00000D68 +#define RFC_ULLRAM_O_BANK1858 0x00000D68 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1859 0x00000D6C +#define RFC_ULLRAM_O_BANK1859 0x00000D6C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1860 0x00000D70 +#define RFC_ULLRAM_O_BANK1860 0x00000D70 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1861 0x00000D74 +#define RFC_ULLRAM_O_BANK1861 0x00000D74 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1862 0x00000D78 +#define RFC_ULLRAM_O_BANK1862 0x00000D78 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1863 0x00000D7C +#define RFC_ULLRAM_O_BANK1863 0x00000D7C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1864 0x00000D80 +#define RFC_ULLRAM_O_BANK1864 0x00000D80 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1865 0x00000D84 +#define RFC_ULLRAM_O_BANK1865 0x00000D84 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1866 0x00000D88 +#define RFC_ULLRAM_O_BANK1866 0x00000D88 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1867 0x00000D8C +#define RFC_ULLRAM_O_BANK1867 0x00000D8C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1868 0x00000D90 +#define RFC_ULLRAM_O_BANK1868 0x00000D90 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1869 0x00000D94 +#define RFC_ULLRAM_O_BANK1869 0x00000D94 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1870 0x00000D98 +#define RFC_ULLRAM_O_BANK1870 0x00000D98 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1871 0x00000D9C +#define RFC_ULLRAM_O_BANK1871 0x00000D9C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1872 0x00000DA0 +#define RFC_ULLRAM_O_BANK1872 0x00000DA0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1873 0x00000DA4 +#define RFC_ULLRAM_O_BANK1873 0x00000DA4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1874 0x00000DA8 +#define RFC_ULLRAM_O_BANK1874 0x00000DA8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1875 0x00000DAC +#define RFC_ULLRAM_O_BANK1875 0x00000DAC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1876 0x00000DB0 +#define RFC_ULLRAM_O_BANK1876 0x00000DB0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1877 0x00000DB4 +#define RFC_ULLRAM_O_BANK1877 0x00000DB4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1878 0x00000DB8 +#define RFC_ULLRAM_O_BANK1878 0x00000DB8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1879 0x00000DBC +#define RFC_ULLRAM_O_BANK1879 0x00000DBC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1880 0x00000DC0 +#define RFC_ULLRAM_O_BANK1880 0x00000DC0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1881 0x00000DC4 +#define RFC_ULLRAM_O_BANK1881 0x00000DC4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1882 0x00000DC8 +#define RFC_ULLRAM_O_BANK1882 0x00000DC8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1883 0x00000DCC +#define RFC_ULLRAM_O_BANK1883 0x00000DCC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1884 0x00000DD0 +#define RFC_ULLRAM_O_BANK1884 0x00000DD0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1885 0x00000DD4 +#define RFC_ULLRAM_O_BANK1885 0x00000DD4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1886 0x00000DD8 +#define RFC_ULLRAM_O_BANK1886 0x00000DD8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1887 0x00000DDC +#define RFC_ULLRAM_O_BANK1887 0x00000DDC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1888 0x00000DE0 +#define RFC_ULLRAM_O_BANK1888 0x00000DE0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1889 0x00000DE4 +#define RFC_ULLRAM_O_BANK1889 0x00000DE4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1890 0x00000DE8 +#define RFC_ULLRAM_O_BANK1890 0x00000DE8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1891 0x00000DEC +#define RFC_ULLRAM_O_BANK1891 0x00000DEC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1892 0x00000DF0 +#define RFC_ULLRAM_O_BANK1892 0x00000DF0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1893 0x00000DF4 +#define RFC_ULLRAM_O_BANK1893 0x00000DF4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1894 0x00000DF8 +#define RFC_ULLRAM_O_BANK1894 0x00000DF8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1895 0x00000DFC +#define RFC_ULLRAM_O_BANK1895 0x00000DFC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1896 0x00000E00 +#define RFC_ULLRAM_O_BANK1896 0x00000E00 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1897 0x00000E04 +#define RFC_ULLRAM_O_BANK1897 0x00000E04 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1898 0x00000E08 +#define RFC_ULLRAM_O_BANK1898 0x00000E08 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1899 0x00000E0C +#define RFC_ULLRAM_O_BANK1899 0x00000E0C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1900 0x00000E10 +#define RFC_ULLRAM_O_BANK1900 0x00000E10 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1901 0x00000E14 +#define RFC_ULLRAM_O_BANK1901 0x00000E14 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1902 0x00000E18 +#define RFC_ULLRAM_O_BANK1902 0x00000E18 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1903 0x00000E1C +#define RFC_ULLRAM_O_BANK1903 0x00000E1C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1904 0x00000E20 +#define RFC_ULLRAM_O_BANK1904 0x00000E20 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1905 0x00000E24 +#define RFC_ULLRAM_O_BANK1905 0x00000E24 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1906 0x00000E28 +#define RFC_ULLRAM_O_BANK1906 0x00000E28 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1907 0x00000E2C +#define RFC_ULLRAM_O_BANK1907 0x00000E2C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1908 0x00000E30 +#define RFC_ULLRAM_O_BANK1908 0x00000E30 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1909 0x00000E34 +#define RFC_ULLRAM_O_BANK1909 0x00000E34 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1910 0x00000E38 +#define RFC_ULLRAM_O_BANK1910 0x00000E38 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1911 0x00000E3C +#define RFC_ULLRAM_O_BANK1911 0x00000E3C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1912 0x00000E40 +#define RFC_ULLRAM_O_BANK1912 0x00000E40 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1913 0x00000E44 +#define RFC_ULLRAM_O_BANK1913 0x00000E44 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1914 0x00000E48 +#define RFC_ULLRAM_O_BANK1914 0x00000E48 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1915 0x00000E4C +#define RFC_ULLRAM_O_BANK1915 0x00000E4C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1916 0x00000E50 +#define RFC_ULLRAM_O_BANK1916 0x00000E50 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1917 0x00000E54 +#define RFC_ULLRAM_O_BANK1917 0x00000E54 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1918 0x00000E58 +#define RFC_ULLRAM_O_BANK1918 0x00000E58 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1919 0x00000E5C +#define RFC_ULLRAM_O_BANK1919 0x00000E5C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1920 0x00000E60 +#define RFC_ULLRAM_O_BANK1920 0x00000E60 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1921 0x00000E64 +#define RFC_ULLRAM_O_BANK1921 0x00000E64 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1922 0x00000E68 +#define RFC_ULLRAM_O_BANK1922 0x00000E68 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1923 0x00000E6C +#define RFC_ULLRAM_O_BANK1923 0x00000E6C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1924 0x00000E70 +#define RFC_ULLRAM_O_BANK1924 0x00000E70 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1925 0x00000E74 +#define RFC_ULLRAM_O_BANK1925 0x00000E74 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1926 0x00000E78 +#define RFC_ULLRAM_O_BANK1926 0x00000E78 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1927 0x00000E7C +#define RFC_ULLRAM_O_BANK1927 0x00000E7C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1928 0x00000E80 +#define RFC_ULLRAM_O_BANK1928 0x00000E80 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1929 0x00000E84 +#define RFC_ULLRAM_O_BANK1929 0x00000E84 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1930 0x00000E88 +#define RFC_ULLRAM_O_BANK1930 0x00000E88 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1931 0x00000E8C +#define RFC_ULLRAM_O_BANK1931 0x00000E8C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1932 0x00000E90 +#define RFC_ULLRAM_O_BANK1932 0x00000E90 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1933 0x00000E94 +#define RFC_ULLRAM_O_BANK1933 0x00000E94 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1934 0x00000E98 +#define RFC_ULLRAM_O_BANK1934 0x00000E98 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1935 0x00000E9C +#define RFC_ULLRAM_O_BANK1935 0x00000E9C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1936 0x00000EA0 +#define RFC_ULLRAM_O_BANK1936 0x00000EA0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1937 0x00000EA4 +#define RFC_ULLRAM_O_BANK1937 0x00000EA4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1938 0x00000EA8 +#define RFC_ULLRAM_O_BANK1938 0x00000EA8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1939 0x00000EAC +#define RFC_ULLRAM_O_BANK1939 0x00000EAC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1940 0x00000EB0 +#define RFC_ULLRAM_O_BANK1940 0x00000EB0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1941 0x00000EB4 +#define RFC_ULLRAM_O_BANK1941 0x00000EB4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1942 0x00000EB8 +#define RFC_ULLRAM_O_BANK1942 0x00000EB8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1943 0x00000EBC +#define RFC_ULLRAM_O_BANK1943 0x00000EBC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1944 0x00000EC0 +#define RFC_ULLRAM_O_BANK1944 0x00000EC0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1945 0x00000EC4 +#define RFC_ULLRAM_O_BANK1945 0x00000EC4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1946 0x00000EC8 +#define RFC_ULLRAM_O_BANK1946 0x00000EC8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1947 0x00000ECC +#define RFC_ULLRAM_O_BANK1947 0x00000ECC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1948 0x00000ED0 +#define RFC_ULLRAM_O_BANK1948 0x00000ED0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1949 0x00000ED4 +#define RFC_ULLRAM_O_BANK1949 0x00000ED4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1950 0x00000ED8 +#define RFC_ULLRAM_O_BANK1950 0x00000ED8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1951 0x00000EDC +#define RFC_ULLRAM_O_BANK1951 0x00000EDC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1952 0x00000EE0 +#define RFC_ULLRAM_O_BANK1952 0x00000EE0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1953 0x00000EE4 +#define RFC_ULLRAM_O_BANK1953 0x00000EE4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1954 0x00000EE8 +#define RFC_ULLRAM_O_BANK1954 0x00000EE8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1955 0x00000EEC +#define RFC_ULLRAM_O_BANK1955 0x00000EEC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1956 0x00000EF0 +#define RFC_ULLRAM_O_BANK1956 0x00000EF0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1957 0x00000EF4 +#define RFC_ULLRAM_O_BANK1957 0x00000EF4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1958 0x00000EF8 +#define RFC_ULLRAM_O_BANK1958 0x00000EF8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1959 0x00000EFC +#define RFC_ULLRAM_O_BANK1959 0x00000EFC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1960 0x00000F00 +#define RFC_ULLRAM_O_BANK1960 0x00000F00 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1961 0x00000F04 +#define RFC_ULLRAM_O_BANK1961 0x00000F04 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1962 0x00000F08 +#define RFC_ULLRAM_O_BANK1962 0x00000F08 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1963 0x00000F0C +#define RFC_ULLRAM_O_BANK1963 0x00000F0C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1964 0x00000F10 +#define RFC_ULLRAM_O_BANK1964 0x00000F10 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1965 0x00000F14 +#define RFC_ULLRAM_O_BANK1965 0x00000F14 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1966 0x00000F18 +#define RFC_ULLRAM_O_BANK1966 0x00000F18 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1967 0x00000F1C +#define RFC_ULLRAM_O_BANK1967 0x00000F1C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1968 0x00000F20 +#define RFC_ULLRAM_O_BANK1968 0x00000F20 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1969 0x00000F24 +#define RFC_ULLRAM_O_BANK1969 0x00000F24 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1970 0x00000F28 +#define RFC_ULLRAM_O_BANK1970 0x00000F28 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1971 0x00000F2C +#define RFC_ULLRAM_O_BANK1971 0x00000F2C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1972 0x00000F30 +#define RFC_ULLRAM_O_BANK1972 0x00000F30 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1973 0x00000F34 +#define RFC_ULLRAM_O_BANK1973 0x00000F34 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1974 0x00000F38 +#define RFC_ULLRAM_O_BANK1974 0x00000F38 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1975 0x00000F3C +#define RFC_ULLRAM_O_BANK1975 0x00000F3C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1976 0x00000F40 +#define RFC_ULLRAM_O_BANK1976 0x00000F40 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1977 0x00000F44 +#define RFC_ULLRAM_O_BANK1977 0x00000F44 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1978 0x00000F48 +#define RFC_ULLRAM_O_BANK1978 0x00000F48 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1979 0x00000F4C +#define RFC_ULLRAM_O_BANK1979 0x00000F4C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1980 0x00000F50 +#define RFC_ULLRAM_O_BANK1980 0x00000F50 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1981 0x00000F54 +#define RFC_ULLRAM_O_BANK1981 0x00000F54 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1982 0x00000F58 +#define RFC_ULLRAM_O_BANK1982 0x00000F58 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1983 0x00000F5C +#define RFC_ULLRAM_O_BANK1983 0x00000F5C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1984 0x00000F60 +#define RFC_ULLRAM_O_BANK1984 0x00000F60 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1985 0x00000F64 +#define RFC_ULLRAM_O_BANK1985 0x00000F64 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1986 0x00000F68 +#define RFC_ULLRAM_O_BANK1986 0x00000F68 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1987 0x00000F6C +#define RFC_ULLRAM_O_BANK1987 0x00000F6C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1988 0x00000F70 +#define RFC_ULLRAM_O_BANK1988 0x00000F70 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1989 0x00000F74 +#define RFC_ULLRAM_O_BANK1989 0x00000F74 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1990 0x00000F78 +#define RFC_ULLRAM_O_BANK1990 0x00000F78 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1991 0x00000F7C +#define RFC_ULLRAM_O_BANK1991 0x00000F7C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1992 0x00000F80 +#define RFC_ULLRAM_O_BANK1992 0x00000F80 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1993 0x00000F84 +#define RFC_ULLRAM_O_BANK1993 0x00000F84 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1994 0x00000F88 +#define RFC_ULLRAM_O_BANK1994 0x00000F88 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1995 0x00000F8C +#define RFC_ULLRAM_O_BANK1995 0x00000F8C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1996 0x00000F90 +#define RFC_ULLRAM_O_BANK1996 0x00000F90 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1997 0x00000F94 +#define RFC_ULLRAM_O_BANK1997 0x00000F94 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1998 0x00000F98 +#define RFC_ULLRAM_O_BANK1998 0x00000F98 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1999 0x00000F9C +#define RFC_ULLRAM_O_BANK1999 0x00000F9C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11000 0x00000FA0 +#define RFC_ULLRAM_O_BANK11000 0x00000FA0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11001 0x00000FA4 +#define RFC_ULLRAM_O_BANK11001 0x00000FA4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11002 0x00000FA8 +#define RFC_ULLRAM_O_BANK11002 0x00000FA8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11003 0x00000FAC +#define RFC_ULLRAM_O_BANK11003 0x00000FAC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11004 0x00000FB0 +#define RFC_ULLRAM_O_BANK11004 0x00000FB0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11005 0x00000FB4 +#define RFC_ULLRAM_O_BANK11005 0x00000FB4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11006 0x00000FB8 +#define RFC_ULLRAM_O_BANK11006 0x00000FB8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11007 0x00000FBC +#define RFC_ULLRAM_O_BANK11007 0x00000FBC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11008 0x00000FC0 +#define RFC_ULLRAM_O_BANK11008 0x00000FC0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11009 0x00000FC4 +#define RFC_ULLRAM_O_BANK11009 0x00000FC4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11010 0x00000FC8 +#define RFC_ULLRAM_O_BANK11010 0x00000FC8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11011 0x00000FCC +#define RFC_ULLRAM_O_BANK11011 0x00000FCC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11012 0x00000FD0 +#define RFC_ULLRAM_O_BANK11012 0x00000FD0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11013 0x00000FD4 +#define RFC_ULLRAM_O_BANK11013 0x00000FD4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11014 0x00000FD8 +#define RFC_ULLRAM_O_BANK11014 0x00000FD8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11015 0x00000FDC +#define RFC_ULLRAM_O_BANK11015 0x00000FDC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11016 0x00000FE0 +#define RFC_ULLRAM_O_BANK11016 0x00000FE0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11017 0x00000FE4 +#define RFC_ULLRAM_O_BANK11017 0x00000FE4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11018 0x00000FE8 +#define RFC_ULLRAM_O_BANK11018 0x00000FE8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11019 0x00000FEC +#define RFC_ULLRAM_O_BANK11019 0x00000FEC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11020 0x00000FF0 +#define RFC_ULLRAM_O_BANK11020 0x00000FF0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11021 0x00000FF4 +#define RFC_ULLRAM_O_BANK11021 0x00000FF4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11022 0x00000FF8 +#define RFC_ULLRAM_O_BANK11022 0x00000FF8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11023 0x00000FFC +#define RFC_ULLRAM_O_BANK11023 0x00000FFC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11024 0x00001000 +#define RFC_ULLRAM_O_BANK11024 0x00001000 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11025 0x00001004 +#define RFC_ULLRAM_O_BANK11025 0x00001004 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11026 0x00001008 +#define RFC_ULLRAM_O_BANK11026 0x00001008 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11027 0x0000100C +#define RFC_ULLRAM_O_BANK11027 0x0000100C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11028 0x00001010 +#define RFC_ULLRAM_O_BANK11028 0x00001010 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11029 0x00001014 +#define RFC_ULLRAM_O_BANK11029 0x00001014 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11030 0x00001018 +#define RFC_ULLRAM_O_BANK11030 0x00001018 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11031 0x0000101C +#define RFC_ULLRAM_O_BANK11031 0x0000101C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11032 0x00001020 +#define RFC_ULLRAM_O_BANK11032 0x00001020 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11033 0x00001024 +#define RFC_ULLRAM_O_BANK11033 0x00001024 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11034 0x00001028 +#define RFC_ULLRAM_O_BANK11034 0x00001028 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11035 0x0000102C +#define RFC_ULLRAM_O_BANK11035 0x0000102C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11036 0x00001030 +#define RFC_ULLRAM_O_BANK11036 0x00001030 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11037 0x00001034 +#define RFC_ULLRAM_O_BANK11037 0x00001034 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11038 0x00001038 +#define RFC_ULLRAM_O_BANK11038 0x00001038 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11039 0x0000103C +#define RFC_ULLRAM_O_BANK11039 0x0000103C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11040 0x00001040 +#define RFC_ULLRAM_O_BANK11040 0x00001040 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11041 0x00001044 +#define RFC_ULLRAM_O_BANK11041 0x00001044 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11042 0x00001048 +#define RFC_ULLRAM_O_BANK11042 0x00001048 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11043 0x0000104C +#define RFC_ULLRAM_O_BANK11043 0x0000104C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11044 0x00001050 +#define RFC_ULLRAM_O_BANK11044 0x00001050 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11045 0x00001054 +#define RFC_ULLRAM_O_BANK11045 0x00001054 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11046 0x00001058 +#define RFC_ULLRAM_O_BANK11046 0x00001058 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11047 0x0000105C +#define RFC_ULLRAM_O_BANK11047 0x0000105C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11048 0x00001060 +#define RFC_ULLRAM_O_BANK11048 0x00001060 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11049 0x00001064 +#define RFC_ULLRAM_O_BANK11049 0x00001064 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11050 0x00001068 +#define RFC_ULLRAM_O_BANK11050 0x00001068 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11051 0x0000106C +#define RFC_ULLRAM_O_BANK11051 0x0000106C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11052 0x00001070 +#define RFC_ULLRAM_O_BANK11052 0x00001070 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11053 0x00001074 +#define RFC_ULLRAM_O_BANK11053 0x00001074 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11054 0x00001078 +#define RFC_ULLRAM_O_BANK11054 0x00001078 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11055 0x0000107C +#define RFC_ULLRAM_O_BANK11055 0x0000107C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11056 0x00001080 +#define RFC_ULLRAM_O_BANK11056 0x00001080 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11057 0x00001084 +#define RFC_ULLRAM_O_BANK11057 0x00001084 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11058 0x00001088 +#define RFC_ULLRAM_O_BANK11058 0x00001088 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11059 0x0000108C +#define RFC_ULLRAM_O_BANK11059 0x0000108C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11060 0x00001090 +#define RFC_ULLRAM_O_BANK11060 0x00001090 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11061 0x00001094 +#define RFC_ULLRAM_O_BANK11061 0x00001094 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11062 0x00001098 +#define RFC_ULLRAM_O_BANK11062 0x00001098 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11063 0x0000109C +#define RFC_ULLRAM_O_BANK11063 0x0000109C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11064 0x000010A0 +#define RFC_ULLRAM_O_BANK11064 0x000010A0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11065 0x000010A4 +#define RFC_ULLRAM_O_BANK11065 0x000010A4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11066 0x000010A8 +#define RFC_ULLRAM_O_BANK11066 0x000010A8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11067 0x000010AC +#define RFC_ULLRAM_O_BANK11067 0x000010AC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11068 0x000010B0 +#define RFC_ULLRAM_O_BANK11068 0x000010B0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11069 0x000010B4 +#define RFC_ULLRAM_O_BANK11069 0x000010B4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11070 0x000010B8 +#define RFC_ULLRAM_O_BANK11070 0x000010B8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11071 0x000010BC +#define RFC_ULLRAM_O_BANK11071 0x000010BC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11072 0x000010C0 +#define RFC_ULLRAM_O_BANK11072 0x000010C0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11073 0x000010C4 +#define RFC_ULLRAM_O_BANK11073 0x000010C4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11074 0x000010C8 +#define RFC_ULLRAM_O_BANK11074 0x000010C8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11075 0x000010CC +#define RFC_ULLRAM_O_BANK11075 0x000010CC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11076 0x000010D0 +#define RFC_ULLRAM_O_BANK11076 0x000010D0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11077 0x000010D4 +#define RFC_ULLRAM_O_BANK11077 0x000010D4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11078 0x000010D8 +#define RFC_ULLRAM_O_BANK11078 0x000010D8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11079 0x000010DC +#define RFC_ULLRAM_O_BANK11079 0x000010DC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11080 0x000010E0 +#define RFC_ULLRAM_O_BANK11080 0x000010E0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11081 0x000010E4 +#define RFC_ULLRAM_O_BANK11081 0x000010E4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11082 0x000010E8 +#define RFC_ULLRAM_O_BANK11082 0x000010E8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11083 0x000010EC +#define RFC_ULLRAM_O_BANK11083 0x000010EC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11084 0x000010F0 +#define RFC_ULLRAM_O_BANK11084 0x000010F0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11085 0x000010F4 +#define RFC_ULLRAM_O_BANK11085 0x000010F4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11086 0x000010F8 +#define RFC_ULLRAM_O_BANK11086 0x000010F8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11087 0x000010FC +#define RFC_ULLRAM_O_BANK11087 0x000010FC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11088 0x00001100 +#define RFC_ULLRAM_O_BANK11088 0x00001100 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11089 0x00001104 +#define RFC_ULLRAM_O_BANK11089 0x00001104 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11090 0x00001108 +#define RFC_ULLRAM_O_BANK11090 0x00001108 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11091 0x0000110C +#define RFC_ULLRAM_O_BANK11091 0x0000110C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11092 0x00001110 +#define RFC_ULLRAM_O_BANK11092 0x00001110 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11093 0x00001114 +#define RFC_ULLRAM_O_BANK11093 0x00001114 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11094 0x00001118 +#define RFC_ULLRAM_O_BANK11094 0x00001118 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11095 0x0000111C +#define RFC_ULLRAM_O_BANK11095 0x0000111C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11096 0x00001120 +#define RFC_ULLRAM_O_BANK11096 0x00001120 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11097 0x00001124 +#define RFC_ULLRAM_O_BANK11097 0x00001124 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11098 0x00001128 +#define RFC_ULLRAM_O_BANK11098 0x00001128 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11099 0x0000112C +#define RFC_ULLRAM_O_BANK11099 0x0000112C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11100 0x00001130 +#define RFC_ULLRAM_O_BANK11100 0x00001130 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11101 0x00001134 +#define RFC_ULLRAM_O_BANK11101 0x00001134 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11102 0x00001138 +#define RFC_ULLRAM_O_BANK11102 0x00001138 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11103 0x0000113C +#define RFC_ULLRAM_O_BANK11103 0x0000113C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11104 0x00001140 +#define RFC_ULLRAM_O_BANK11104 0x00001140 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11105 0x00001144 +#define RFC_ULLRAM_O_BANK11105 0x00001144 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11106 0x00001148 +#define RFC_ULLRAM_O_BANK11106 0x00001148 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11107 0x0000114C +#define RFC_ULLRAM_O_BANK11107 0x0000114C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11108 0x00001150 +#define RFC_ULLRAM_O_BANK11108 0x00001150 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11109 0x00001154 +#define RFC_ULLRAM_O_BANK11109 0x00001154 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11110 0x00001158 +#define RFC_ULLRAM_O_BANK11110 0x00001158 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11111 0x0000115C +#define RFC_ULLRAM_O_BANK11111 0x0000115C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11112 0x00001160 +#define RFC_ULLRAM_O_BANK11112 0x00001160 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11113 0x00001164 +#define RFC_ULLRAM_O_BANK11113 0x00001164 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11114 0x00001168 +#define RFC_ULLRAM_O_BANK11114 0x00001168 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11115 0x0000116C +#define RFC_ULLRAM_O_BANK11115 0x0000116C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11116 0x00001170 +#define RFC_ULLRAM_O_BANK11116 0x00001170 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11117 0x00001174 +#define RFC_ULLRAM_O_BANK11117 0x00001174 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11118 0x00001178 +#define RFC_ULLRAM_O_BANK11118 0x00001178 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11119 0x0000117C +#define RFC_ULLRAM_O_BANK11119 0x0000117C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11120 0x00001180 +#define RFC_ULLRAM_O_BANK11120 0x00001180 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11121 0x00001184 +#define RFC_ULLRAM_O_BANK11121 0x00001184 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11122 0x00001188 +#define RFC_ULLRAM_O_BANK11122 0x00001188 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11123 0x0000118C +#define RFC_ULLRAM_O_BANK11123 0x0000118C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11124 0x00001190 +#define RFC_ULLRAM_O_BANK11124 0x00001190 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11125 0x00001194 +#define RFC_ULLRAM_O_BANK11125 0x00001194 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11126 0x00001198 +#define RFC_ULLRAM_O_BANK11126 0x00001198 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11127 0x0000119C +#define RFC_ULLRAM_O_BANK11127 0x0000119C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11128 0x000011A0 +#define RFC_ULLRAM_O_BANK11128 0x000011A0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11129 0x000011A4 +#define RFC_ULLRAM_O_BANK11129 0x000011A4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11130 0x000011A8 +#define RFC_ULLRAM_O_BANK11130 0x000011A8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11131 0x000011AC +#define RFC_ULLRAM_O_BANK11131 0x000011AC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11132 0x000011B0 +#define RFC_ULLRAM_O_BANK11132 0x000011B0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11133 0x000011B4 +#define RFC_ULLRAM_O_BANK11133 0x000011B4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11134 0x000011B8 +#define RFC_ULLRAM_O_BANK11134 0x000011B8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11135 0x000011BC +#define RFC_ULLRAM_O_BANK11135 0x000011BC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11136 0x000011C0 +#define RFC_ULLRAM_O_BANK11136 0x000011C0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11137 0x000011C4 +#define RFC_ULLRAM_O_BANK11137 0x000011C4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11138 0x000011C8 +#define RFC_ULLRAM_O_BANK11138 0x000011C8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11139 0x000011CC +#define RFC_ULLRAM_O_BANK11139 0x000011CC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11140 0x000011D0 +#define RFC_ULLRAM_O_BANK11140 0x000011D0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11141 0x000011D4 +#define RFC_ULLRAM_O_BANK11141 0x000011D4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11142 0x000011D8 +#define RFC_ULLRAM_O_BANK11142 0x000011D8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11143 0x000011DC +#define RFC_ULLRAM_O_BANK11143 0x000011DC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11144 0x000011E0 +#define RFC_ULLRAM_O_BANK11144 0x000011E0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11145 0x000011E4 +#define RFC_ULLRAM_O_BANK11145 0x000011E4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11146 0x000011E8 +#define RFC_ULLRAM_O_BANK11146 0x000011E8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11147 0x000011EC +#define RFC_ULLRAM_O_BANK11147 0x000011EC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11148 0x000011F0 +#define RFC_ULLRAM_O_BANK11148 0x000011F0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11149 0x000011F4 +#define RFC_ULLRAM_O_BANK11149 0x000011F4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11150 0x000011F8 +#define RFC_ULLRAM_O_BANK11150 0x000011F8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11151 0x000011FC +#define RFC_ULLRAM_O_BANK11151 0x000011FC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11152 0x00001200 +#define RFC_ULLRAM_O_BANK11152 0x00001200 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11153 0x00001204 +#define RFC_ULLRAM_O_BANK11153 0x00001204 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11154 0x00001208 +#define RFC_ULLRAM_O_BANK11154 0x00001208 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11155 0x0000120C +#define RFC_ULLRAM_O_BANK11155 0x0000120C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11156 0x00001210 +#define RFC_ULLRAM_O_BANK11156 0x00001210 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11157 0x00001214 +#define RFC_ULLRAM_O_BANK11157 0x00001214 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11158 0x00001218 +#define RFC_ULLRAM_O_BANK11158 0x00001218 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11159 0x0000121C +#define RFC_ULLRAM_O_BANK11159 0x0000121C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11160 0x00001220 +#define RFC_ULLRAM_O_BANK11160 0x00001220 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11161 0x00001224 +#define RFC_ULLRAM_O_BANK11161 0x00001224 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11162 0x00001228 +#define RFC_ULLRAM_O_BANK11162 0x00001228 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11163 0x0000122C +#define RFC_ULLRAM_O_BANK11163 0x0000122C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11164 0x00001230 +#define RFC_ULLRAM_O_BANK11164 0x00001230 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11165 0x00001234 +#define RFC_ULLRAM_O_BANK11165 0x00001234 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11166 0x00001238 +#define RFC_ULLRAM_O_BANK11166 0x00001238 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11167 0x0000123C +#define RFC_ULLRAM_O_BANK11167 0x0000123C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11168 0x00001240 +#define RFC_ULLRAM_O_BANK11168 0x00001240 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11169 0x00001244 +#define RFC_ULLRAM_O_BANK11169 0x00001244 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11170 0x00001248 +#define RFC_ULLRAM_O_BANK11170 0x00001248 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11171 0x0000124C +#define RFC_ULLRAM_O_BANK11171 0x0000124C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11172 0x00001250 +#define RFC_ULLRAM_O_BANK11172 0x00001250 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11173 0x00001254 +#define RFC_ULLRAM_O_BANK11173 0x00001254 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11174 0x00001258 +#define RFC_ULLRAM_O_BANK11174 0x00001258 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11175 0x0000125C +#define RFC_ULLRAM_O_BANK11175 0x0000125C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11176 0x00001260 +#define RFC_ULLRAM_O_BANK11176 0x00001260 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11177 0x00001264 +#define RFC_ULLRAM_O_BANK11177 0x00001264 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11178 0x00001268 +#define RFC_ULLRAM_O_BANK11178 0x00001268 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11179 0x0000126C +#define RFC_ULLRAM_O_BANK11179 0x0000126C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11180 0x00001270 +#define RFC_ULLRAM_O_BANK11180 0x00001270 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11181 0x00001274 +#define RFC_ULLRAM_O_BANK11181 0x00001274 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11182 0x00001278 +#define RFC_ULLRAM_O_BANK11182 0x00001278 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11183 0x0000127C +#define RFC_ULLRAM_O_BANK11183 0x0000127C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11184 0x00001280 +#define RFC_ULLRAM_O_BANK11184 0x00001280 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11185 0x00001284 +#define RFC_ULLRAM_O_BANK11185 0x00001284 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11186 0x00001288 +#define RFC_ULLRAM_O_BANK11186 0x00001288 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11187 0x0000128C +#define RFC_ULLRAM_O_BANK11187 0x0000128C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11188 0x00001290 +#define RFC_ULLRAM_O_BANK11188 0x00001290 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11189 0x00001294 +#define RFC_ULLRAM_O_BANK11189 0x00001294 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11190 0x00001298 +#define RFC_ULLRAM_O_BANK11190 0x00001298 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11191 0x0000129C +#define RFC_ULLRAM_O_BANK11191 0x0000129C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11192 0x000012A0 +#define RFC_ULLRAM_O_BANK11192 0x000012A0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11193 0x000012A4 +#define RFC_ULLRAM_O_BANK11193 0x000012A4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11194 0x000012A8 +#define RFC_ULLRAM_O_BANK11194 0x000012A8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11195 0x000012AC +#define RFC_ULLRAM_O_BANK11195 0x000012AC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11196 0x000012B0 +#define RFC_ULLRAM_O_BANK11196 0x000012B0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11197 0x000012B4 +#define RFC_ULLRAM_O_BANK11197 0x000012B4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11198 0x000012B8 +#define RFC_ULLRAM_O_BANK11198 0x000012B8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11199 0x000012BC +#define RFC_ULLRAM_O_BANK11199 0x000012BC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11200 0x000012C0 +#define RFC_ULLRAM_O_BANK11200 0x000012C0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11201 0x000012C4 +#define RFC_ULLRAM_O_BANK11201 0x000012C4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11202 0x000012C8 +#define RFC_ULLRAM_O_BANK11202 0x000012C8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11203 0x000012CC +#define RFC_ULLRAM_O_BANK11203 0x000012CC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11204 0x000012D0 +#define RFC_ULLRAM_O_BANK11204 0x000012D0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11205 0x000012D4 +#define RFC_ULLRAM_O_BANK11205 0x000012D4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11206 0x000012D8 +#define RFC_ULLRAM_O_BANK11206 0x000012D8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11207 0x000012DC +#define RFC_ULLRAM_O_BANK11207 0x000012DC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11208 0x000012E0 +#define RFC_ULLRAM_O_BANK11208 0x000012E0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11209 0x000012E4 +#define RFC_ULLRAM_O_BANK11209 0x000012E4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11210 0x000012E8 +#define RFC_ULLRAM_O_BANK11210 0x000012E8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11211 0x000012EC +#define RFC_ULLRAM_O_BANK11211 0x000012EC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11212 0x000012F0 +#define RFC_ULLRAM_O_BANK11212 0x000012F0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11213 0x000012F4 +#define RFC_ULLRAM_O_BANK11213 0x000012F4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11214 0x000012F8 +#define RFC_ULLRAM_O_BANK11214 0x000012F8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11215 0x000012FC +#define RFC_ULLRAM_O_BANK11215 0x000012FC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11216 0x00001300 +#define RFC_ULLRAM_O_BANK11216 0x00001300 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11217 0x00001304 +#define RFC_ULLRAM_O_BANK11217 0x00001304 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11218 0x00001308 +#define RFC_ULLRAM_O_BANK11218 0x00001308 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11219 0x0000130C +#define RFC_ULLRAM_O_BANK11219 0x0000130C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11220 0x00001310 +#define RFC_ULLRAM_O_BANK11220 0x00001310 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11221 0x00001314 +#define RFC_ULLRAM_O_BANK11221 0x00001314 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11222 0x00001318 +#define RFC_ULLRAM_O_BANK11222 0x00001318 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11223 0x0000131C +#define RFC_ULLRAM_O_BANK11223 0x0000131C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11224 0x00001320 +#define RFC_ULLRAM_O_BANK11224 0x00001320 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11225 0x00001324 +#define RFC_ULLRAM_O_BANK11225 0x00001324 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11226 0x00001328 +#define RFC_ULLRAM_O_BANK11226 0x00001328 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11227 0x0000132C +#define RFC_ULLRAM_O_BANK11227 0x0000132C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11228 0x00001330 +#define RFC_ULLRAM_O_BANK11228 0x00001330 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11229 0x00001334 +#define RFC_ULLRAM_O_BANK11229 0x00001334 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11230 0x00001338 +#define RFC_ULLRAM_O_BANK11230 0x00001338 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11231 0x0000133C +#define RFC_ULLRAM_O_BANK11231 0x0000133C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11232 0x00001340 +#define RFC_ULLRAM_O_BANK11232 0x00001340 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11233 0x00001344 +#define RFC_ULLRAM_O_BANK11233 0x00001344 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11234 0x00001348 +#define RFC_ULLRAM_O_BANK11234 0x00001348 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11235 0x0000134C +#define RFC_ULLRAM_O_BANK11235 0x0000134C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11236 0x00001350 +#define RFC_ULLRAM_O_BANK11236 0x00001350 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11237 0x00001354 +#define RFC_ULLRAM_O_BANK11237 0x00001354 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11238 0x00001358 +#define RFC_ULLRAM_O_BANK11238 0x00001358 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11239 0x0000135C +#define RFC_ULLRAM_O_BANK11239 0x0000135C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11240 0x00001360 +#define RFC_ULLRAM_O_BANK11240 0x00001360 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11241 0x00001364 +#define RFC_ULLRAM_O_BANK11241 0x00001364 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11242 0x00001368 +#define RFC_ULLRAM_O_BANK11242 0x00001368 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11243 0x0000136C +#define RFC_ULLRAM_O_BANK11243 0x0000136C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11244 0x00001370 +#define RFC_ULLRAM_O_BANK11244 0x00001370 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11245 0x00001374 +#define RFC_ULLRAM_O_BANK11245 0x00001374 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11246 0x00001378 +#define RFC_ULLRAM_O_BANK11246 0x00001378 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11247 0x0000137C +#define RFC_ULLRAM_O_BANK11247 0x0000137C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11248 0x00001380 +#define RFC_ULLRAM_O_BANK11248 0x00001380 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11249 0x00001384 +#define RFC_ULLRAM_O_BANK11249 0x00001384 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11250 0x00001388 +#define RFC_ULLRAM_O_BANK11250 0x00001388 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11251 0x0000138C +#define RFC_ULLRAM_O_BANK11251 0x0000138C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11252 0x00001390 +#define RFC_ULLRAM_O_BANK11252 0x00001390 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11253 0x00001394 +#define RFC_ULLRAM_O_BANK11253 0x00001394 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11254 0x00001398 +#define RFC_ULLRAM_O_BANK11254 0x00001398 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11255 0x0000139C +#define RFC_ULLRAM_O_BANK11255 0x0000139C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11256 0x000013A0 +#define RFC_ULLRAM_O_BANK11256 0x000013A0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11257 0x000013A4 +#define RFC_ULLRAM_O_BANK11257 0x000013A4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11258 0x000013A8 +#define RFC_ULLRAM_O_BANK11258 0x000013A8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11259 0x000013AC +#define RFC_ULLRAM_O_BANK11259 0x000013AC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11260 0x000013B0 +#define RFC_ULLRAM_O_BANK11260 0x000013B0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11261 0x000013B4 +#define RFC_ULLRAM_O_BANK11261 0x000013B4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11262 0x000013B8 +#define RFC_ULLRAM_O_BANK11262 0x000013B8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11263 0x000013BC +#define RFC_ULLRAM_O_BANK11263 0x000013BC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11264 0x000013C0 +#define RFC_ULLRAM_O_BANK11264 0x000013C0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11265 0x000013C4 +#define RFC_ULLRAM_O_BANK11265 0x000013C4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11266 0x000013C8 +#define RFC_ULLRAM_O_BANK11266 0x000013C8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11267 0x000013CC +#define RFC_ULLRAM_O_BANK11267 0x000013CC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11268 0x000013D0 +#define RFC_ULLRAM_O_BANK11268 0x000013D0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11269 0x000013D4 +#define RFC_ULLRAM_O_BANK11269 0x000013D4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11270 0x000013D8 +#define RFC_ULLRAM_O_BANK11270 0x000013D8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11271 0x000013DC +#define RFC_ULLRAM_O_BANK11271 0x000013DC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11272 0x000013E0 +#define RFC_ULLRAM_O_BANK11272 0x000013E0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11273 0x000013E4 +#define RFC_ULLRAM_O_BANK11273 0x000013E4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11274 0x000013E8 +#define RFC_ULLRAM_O_BANK11274 0x000013E8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11275 0x000013EC +#define RFC_ULLRAM_O_BANK11275 0x000013EC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11276 0x000013F0 +#define RFC_ULLRAM_O_BANK11276 0x000013F0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11277 0x000013F4 +#define RFC_ULLRAM_O_BANK11277 0x000013F4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11278 0x000013F8 +#define RFC_ULLRAM_O_BANK11278 0x000013F8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11279 0x000013FC +#define RFC_ULLRAM_O_BANK11279 0x000013FC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11280 0x00001400 +#define RFC_ULLRAM_O_BANK11280 0x00001400 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11281 0x00001404 +#define RFC_ULLRAM_O_BANK11281 0x00001404 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11282 0x00001408 +#define RFC_ULLRAM_O_BANK11282 0x00001408 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11283 0x0000140C +#define RFC_ULLRAM_O_BANK11283 0x0000140C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11284 0x00001410 +#define RFC_ULLRAM_O_BANK11284 0x00001410 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11285 0x00001414 +#define RFC_ULLRAM_O_BANK11285 0x00001414 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11286 0x00001418 +#define RFC_ULLRAM_O_BANK11286 0x00001418 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11287 0x0000141C +#define RFC_ULLRAM_O_BANK11287 0x0000141C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11288 0x00001420 +#define RFC_ULLRAM_O_BANK11288 0x00001420 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11289 0x00001424 +#define RFC_ULLRAM_O_BANK11289 0x00001424 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11290 0x00001428 +#define RFC_ULLRAM_O_BANK11290 0x00001428 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11291 0x0000142C +#define RFC_ULLRAM_O_BANK11291 0x0000142C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11292 0x00001430 +#define RFC_ULLRAM_O_BANK11292 0x00001430 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11293 0x00001434 +#define RFC_ULLRAM_O_BANK11293 0x00001434 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11294 0x00001438 +#define RFC_ULLRAM_O_BANK11294 0x00001438 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11295 0x0000143C +#define RFC_ULLRAM_O_BANK11295 0x0000143C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11296 0x00001440 +#define RFC_ULLRAM_O_BANK11296 0x00001440 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11297 0x00001444 +#define RFC_ULLRAM_O_BANK11297 0x00001444 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11298 0x00001448 +#define RFC_ULLRAM_O_BANK11298 0x00001448 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11299 0x0000144C +#define RFC_ULLRAM_O_BANK11299 0x0000144C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11300 0x00001450 +#define RFC_ULLRAM_O_BANK11300 0x00001450 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11301 0x00001454 +#define RFC_ULLRAM_O_BANK11301 0x00001454 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11302 0x00001458 +#define RFC_ULLRAM_O_BANK11302 0x00001458 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11303 0x0000145C +#define RFC_ULLRAM_O_BANK11303 0x0000145C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11304 0x00001460 +#define RFC_ULLRAM_O_BANK11304 0x00001460 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11305 0x00001464 +#define RFC_ULLRAM_O_BANK11305 0x00001464 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11306 0x00001468 +#define RFC_ULLRAM_O_BANK11306 0x00001468 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11307 0x0000146C +#define RFC_ULLRAM_O_BANK11307 0x0000146C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11308 0x00001470 +#define RFC_ULLRAM_O_BANK11308 0x00001470 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11309 0x00001474 +#define RFC_ULLRAM_O_BANK11309 0x00001474 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11310 0x00001478 +#define RFC_ULLRAM_O_BANK11310 0x00001478 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11311 0x0000147C +#define RFC_ULLRAM_O_BANK11311 0x0000147C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11312 0x00001480 +#define RFC_ULLRAM_O_BANK11312 0x00001480 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11313 0x00001484 +#define RFC_ULLRAM_O_BANK11313 0x00001484 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11314 0x00001488 +#define RFC_ULLRAM_O_BANK11314 0x00001488 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11315 0x0000148C +#define RFC_ULLRAM_O_BANK11315 0x0000148C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11316 0x00001490 +#define RFC_ULLRAM_O_BANK11316 0x00001490 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11317 0x00001494 +#define RFC_ULLRAM_O_BANK11317 0x00001494 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11318 0x00001498 +#define RFC_ULLRAM_O_BANK11318 0x00001498 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11319 0x0000149C +#define RFC_ULLRAM_O_BANK11319 0x0000149C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11320 0x000014A0 +#define RFC_ULLRAM_O_BANK11320 0x000014A0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11321 0x000014A4 +#define RFC_ULLRAM_O_BANK11321 0x000014A4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11322 0x000014A8 +#define RFC_ULLRAM_O_BANK11322 0x000014A8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11323 0x000014AC +#define RFC_ULLRAM_O_BANK11323 0x000014AC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11324 0x000014B0 +#define RFC_ULLRAM_O_BANK11324 0x000014B0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11325 0x000014B4 +#define RFC_ULLRAM_O_BANK11325 0x000014B4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11326 0x000014B8 +#define RFC_ULLRAM_O_BANK11326 0x000014B8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11327 0x000014BC +#define RFC_ULLRAM_O_BANK11327 0x000014BC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11328 0x000014C0 +#define RFC_ULLRAM_O_BANK11328 0x000014C0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11329 0x000014C4 +#define RFC_ULLRAM_O_BANK11329 0x000014C4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11330 0x000014C8 +#define RFC_ULLRAM_O_BANK11330 0x000014C8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11331 0x000014CC +#define RFC_ULLRAM_O_BANK11331 0x000014CC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11332 0x000014D0 +#define RFC_ULLRAM_O_BANK11332 0x000014D0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11333 0x000014D4 +#define RFC_ULLRAM_O_BANK11333 0x000014D4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11334 0x000014D8 +#define RFC_ULLRAM_O_BANK11334 0x000014D8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11335 0x000014DC +#define RFC_ULLRAM_O_BANK11335 0x000014DC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11336 0x000014E0 +#define RFC_ULLRAM_O_BANK11336 0x000014E0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11337 0x000014E4 +#define RFC_ULLRAM_O_BANK11337 0x000014E4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11338 0x000014E8 +#define RFC_ULLRAM_O_BANK11338 0x000014E8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11339 0x000014EC +#define RFC_ULLRAM_O_BANK11339 0x000014EC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11340 0x000014F0 +#define RFC_ULLRAM_O_BANK11340 0x000014F0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11341 0x000014F4 +#define RFC_ULLRAM_O_BANK11341 0x000014F4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11342 0x000014F8 +#define RFC_ULLRAM_O_BANK11342 0x000014F8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11343 0x000014FC +#define RFC_ULLRAM_O_BANK11343 0x000014FC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11344 0x00001500 +#define RFC_ULLRAM_O_BANK11344 0x00001500 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11345 0x00001504 +#define RFC_ULLRAM_O_BANK11345 0x00001504 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11346 0x00001508 +#define RFC_ULLRAM_O_BANK11346 0x00001508 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11347 0x0000150C +#define RFC_ULLRAM_O_BANK11347 0x0000150C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11348 0x00001510 +#define RFC_ULLRAM_O_BANK11348 0x00001510 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11349 0x00001514 +#define RFC_ULLRAM_O_BANK11349 0x00001514 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11350 0x00001518 +#define RFC_ULLRAM_O_BANK11350 0x00001518 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11351 0x0000151C +#define RFC_ULLRAM_O_BANK11351 0x0000151C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11352 0x00001520 +#define RFC_ULLRAM_O_BANK11352 0x00001520 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11353 0x00001524 +#define RFC_ULLRAM_O_BANK11353 0x00001524 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11354 0x00001528 +#define RFC_ULLRAM_O_BANK11354 0x00001528 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11355 0x0000152C +#define RFC_ULLRAM_O_BANK11355 0x0000152C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11356 0x00001530 +#define RFC_ULLRAM_O_BANK11356 0x00001530 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11357 0x00001534 +#define RFC_ULLRAM_O_BANK11357 0x00001534 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11358 0x00001538 +#define RFC_ULLRAM_O_BANK11358 0x00001538 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11359 0x0000153C +#define RFC_ULLRAM_O_BANK11359 0x0000153C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11360 0x00001540 +#define RFC_ULLRAM_O_BANK11360 0x00001540 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11361 0x00001544 +#define RFC_ULLRAM_O_BANK11361 0x00001544 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11362 0x00001548 +#define RFC_ULLRAM_O_BANK11362 0x00001548 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11363 0x0000154C +#define RFC_ULLRAM_O_BANK11363 0x0000154C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11364 0x00001550 +#define RFC_ULLRAM_O_BANK11364 0x00001550 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11365 0x00001554 +#define RFC_ULLRAM_O_BANK11365 0x00001554 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11366 0x00001558 +#define RFC_ULLRAM_O_BANK11366 0x00001558 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11367 0x0000155C +#define RFC_ULLRAM_O_BANK11367 0x0000155C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11368 0x00001560 +#define RFC_ULLRAM_O_BANK11368 0x00001560 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11369 0x00001564 +#define RFC_ULLRAM_O_BANK11369 0x00001564 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11370 0x00001568 +#define RFC_ULLRAM_O_BANK11370 0x00001568 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11371 0x0000156C +#define RFC_ULLRAM_O_BANK11371 0x0000156C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11372 0x00001570 +#define RFC_ULLRAM_O_BANK11372 0x00001570 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11373 0x00001574 +#define RFC_ULLRAM_O_BANK11373 0x00001574 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11374 0x00001578 +#define RFC_ULLRAM_O_BANK11374 0x00001578 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11375 0x0000157C +#define RFC_ULLRAM_O_BANK11375 0x0000157C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11376 0x00001580 +#define RFC_ULLRAM_O_BANK11376 0x00001580 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11377 0x00001584 +#define RFC_ULLRAM_O_BANK11377 0x00001584 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11378 0x00001588 +#define RFC_ULLRAM_O_BANK11378 0x00001588 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11379 0x0000158C +#define RFC_ULLRAM_O_BANK11379 0x0000158C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11380 0x00001590 +#define RFC_ULLRAM_O_BANK11380 0x00001590 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11381 0x00001594 +#define RFC_ULLRAM_O_BANK11381 0x00001594 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11382 0x00001598 +#define RFC_ULLRAM_O_BANK11382 0x00001598 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11383 0x0000159C +#define RFC_ULLRAM_O_BANK11383 0x0000159C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11384 0x000015A0 +#define RFC_ULLRAM_O_BANK11384 0x000015A0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11385 0x000015A4 +#define RFC_ULLRAM_O_BANK11385 0x000015A4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11386 0x000015A8 +#define RFC_ULLRAM_O_BANK11386 0x000015A8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11387 0x000015AC +#define RFC_ULLRAM_O_BANK11387 0x000015AC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11388 0x000015B0 +#define RFC_ULLRAM_O_BANK11388 0x000015B0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11389 0x000015B4 +#define RFC_ULLRAM_O_BANK11389 0x000015B4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11390 0x000015B8 +#define RFC_ULLRAM_O_BANK11390 0x000015B8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11391 0x000015BC +#define RFC_ULLRAM_O_BANK11391 0x000015BC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11392 0x000015C0 +#define RFC_ULLRAM_O_BANK11392 0x000015C0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11393 0x000015C4 +#define RFC_ULLRAM_O_BANK11393 0x000015C4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11394 0x000015C8 +#define RFC_ULLRAM_O_BANK11394 0x000015C8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11395 0x000015CC +#define RFC_ULLRAM_O_BANK11395 0x000015CC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11396 0x000015D0 +#define RFC_ULLRAM_O_BANK11396 0x000015D0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11397 0x000015D4 +#define RFC_ULLRAM_O_BANK11397 0x000015D4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11398 0x000015D8 +#define RFC_ULLRAM_O_BANK11398 0x000015D8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11399 0x000015DC +#define RFC_ULLRAM_O_BANK11399 0x000015DC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11400 0x000015E0 +#define RFC_ULLRAM_O_BANK11400 0x000015E0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11401 0x000015E4 +#define RFC_ULLRAM_O_BANK11401 0x000015E4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11402 0x000015E8 +#define RFC_ULLRAM_O_BANK11402 0x000015E8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11403 0x000015EC +#define RFC_ULLRAM_O_BANK11403 0x000015EC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11404 0x000015F0 +#define RFC_ULLRAM_O_BANK11404 0x000015F0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11405 0x000015F4 +#define RFC_ULLRAM_O_BANK11405 0x000015F4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11406 0x000015F8 +#define RFC_ULLRAM_O_BANK11406 0x000015F8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11407 0x000015FC +#define RFC_ULLRAM_O_BANK11407 0x000015FC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11408 0x00001600 +#define RFC_ULLRAM_O_BANK11408 0x00001600 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11409 0x00001604 +#define RFC_ULLRAM_O_BANK11409 0x00001604 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11410 0x00001608 +#define RFC_ULLRAM_O_BANK11410 0x00001608 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11411 0x0000160C +#define RFC_ULLRAM_O_BANK11411 0x0000160C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11412 0x00001610 +#define RFC_ULLRAM_O_BANK11412 0x00001610 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11413 0x00001614 +#define RFC_ULLRAM_O_BANK11413 0x00001614 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11414 0x00001618 +#define RFC_ULLRAM_O_BANK11414 0x00001618 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11415 0x0000161C +#define RFC_ULLRAM_O_BANK11415 0x0000161C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11416 0x00001620 +#define RFC_ULLRAM_O_BANK11416 0x00001620 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11417 0x00001624 +#define RFC_ULLRAM_O_BANK11417 0x00001624 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11418 0x00001628 +#define RFC_ULLRAM_O_BANK11418 0x00001628 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11419 0x0000162C +#define RFC_ULLRAM_O_BANK11419 0x0000162C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11420 0x00001630 +#define RFC_ULLRAM_O_BANK11420 0x00001630 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11421 0x00001634 +#define RFC_ULLRAM_O_BANK11421 0x00001634 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11422 0x00001638 +#define RFC_ULLRAM_O_BANK11422 0x00001638 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11423 0x0000163C +#define RFC_ULLRAM_O_BANK11423 0x0000163C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11424 0x00001640 +#define RFC_ULLRAM_O_BANK11424 0x00001640 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11425 0x00001644 +#define RFC_ULLRAM_O_BANK11425 0x00001644 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11426 0x00001648 +#define RFC_ULLRAM_O_BANK11426 0x00001648 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11427 0x0000164C +#define RFC_ULLRAM_O_BANK11427 0x0000164C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11428 0x00001650 +#define RFC_ULLRAM_O_BANK11428 0x00001650 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11429 0x00001654 +#define RFC_ULLRAM_O_BANK11429 0x00001654 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11430 0x00001658 +#define RFC_ULLRAM_O_BANK11430 0x00001658 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11431 0x0000165C +#define RFC_ULLRAM_O_BANK11431 0x0000165C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11432 0x00001660 +#define RFC_ULLRAM_O_BANK11432 0x00001660 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11433 0x00001664 +#define RFC_ULLRAM_O_BANK11433 0x00001664 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11434 0x00001668 +#define RFC_ULLRAM_O_BANK11434 0x00001668 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11435 0x0000166C +#define RFC_ULLRAM_O_BANK11435 0x0000166C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11436 0x00001670 +#define RFC_ULLRAM_O_BANK11436 0x00001670 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11437 0x00001674 +#define RFC_ULLRAM_O_BANK11437 0x00001674 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11438 0x00001678 +#define RFC_ULLRAM_O_BANK11438 0x00001678 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11439 0x0000167C +#define RFC_ULLRAM_O_BANK11439 0x0000167C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11440 0x00001680 +#define RFC_ULLRAM_O_BANK11440 0x00001680 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11441 0x00001684 +#define RFC_ULLRAM_O_BANK11441 0x00001684 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11442 0x00001688 +#define RFC_ULLRAM_O_BANK11442 0x00001688 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11443 0x0000168C +#define RFC_ULLRAM_O_BANK11443 0x0000168C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11444 0x00001690 +#define RFC_ULLRAM_O_BANK11444 0x00001690 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11445 0x00001694 +#define RFC_ULLRAM_O_BANK11445 0x00001694 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11446 0x00001698 +#define RFC_ULLRAM_O_BANK11446 0x00001698 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11447 0x0000169C +#define RFC_ULLRAM_O_BANK11447 0x0000169C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11448 0x000016A0 +#define RFC_ULLRAM_O_BANK11448 0x000016A0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11449 0x000016A4 +#define RFC_ULLRAM_O_BANK11449 0x000016A4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11450 0x000016A8 +#define RFC_ULLRAM_O_BANK11450 0x000016A8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11451 0x000016AC +#define RFC_ULLRAM_O_BANK11451 0x000016AC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11452 0x000016B0 +#define RFC_ULLRAM_O_BANK11452 0x000016B0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11453 0x000016B4 +#define RFC_ULLRAM_O_BANK11453 0x000016B4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11454 0x000016B8 +#define RFC_ULLRAM_O_BANK11454 0x000016B8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11455 0x000016BC +#define RFC_ULLRAM_O_BANK11455 0x000016BC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11456 0x000016C0 +#define RFC_ULLRAM_O_BANK11456 0x000016C0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11457 0x000016C4 +#define RFC_ULLRAM_O_BANK11457 0x000016C4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11458 0x000016C8 +#define RFC_ULLRAM_O_BANK11458 0x000016C8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11459 0x000016CC +#define RFC_ULLRAM_O_BANK11459 0x000016CC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11460 0x000016D0 +#define RFC_ULLRAM_O_BANK11460 0x000016D0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11461 0x000016D4 +#define RFC_ULLRAM_O_BANK11461 0x000016D4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11462 0x000016D8 +#define RFC_ULLRAM_O_BANK11462 0x000016D8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11463 0x000016DC +#define RFC_ULLRAM_O_BANK11463 0x000016DC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11464 0x000016E0 +#define RFC_ULLRAM_O_BANK11464 0x000016E0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11465 0x000016E4 +#define RFC_ULLRAM_O_BANK11465 0x000016E4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11466 0x000016E8 +#define RFC_ULLRAM_O_BANK11466 0x000016E8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11467 0x000016EC +#define RFC_ULLRAM_O_BANK11467 0x000016EC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11468 0x000016F0 +#define RFC_ULLRAM_O_BANK11468 0x000016F0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11469 0x000016F4 +#define RFC_ULLRAM_O_BANK11469 0x000016F4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11470 0x000016F8 +#define RFC_ULLRAM_O_BANK11470 0x000016F8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11471 0x000016FC +#define RFC_ULLRAM_O_BANK11471 0x000016FC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11472 0x00001700 +#define RFC_ULLRAM_O_BANK11472 0x00001700 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11473 0x00001704 +#define RFC_ULLRAM_O_BANK11473 0x00001704 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11474 0x00001708 +#define RFC_ULLRAM_O_BANK11474 0x00001708 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11475 0x0000170C +#define RFC_ULLRAM_O_BANK11475 0x0000170C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11476 0x00001710 +#define RFC_ULLRAM_O_BANK11476 0x00001710 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11477 0x00001714 +#define RFC_ULLRAM_O_BANK11477 0x00001714 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11478 0x00001718 +#define RFC_ULLRAM_O_BANK11478 0x00001718 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11479 0x0000171C +#define RFC_ULLRAM_O_BANK11479 0x0000171C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11480 0x00001720 +#define RFC_ULLRAM_O_BANK11480 0x00001720 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11481 0x00001724 +#define RFC_ULLRAM_O_BANK11481 0x00001724 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11482 0x00001728 +#define RFC_ULLRAM_O_BANK11482 0x00001728 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11483 0x0000172C +#define RFC_ULLRAM_O_BANK11483 0x0000172C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11484 0x00001730 +#define RFC_ULLRAM_O_BANK11484 0x00001730 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11485 0x00001734 +#define RFC_ULLRAM_O_BANK11485 0x00001734 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11486 0x00001738 +#define RFC_ULLRAM_O_BANK11486 0x00001738 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11487 0x0000173C +#define RFC_ULLRAM_O_BANK11487 0x0000173C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11488 0x00001740 +#define RFC_ULLRAM_O_BANK11488 0x00001740 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11489 0x00001744 +#define RFC_ULLRAM_O_BANK11489 0x00001744 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11490 0x00001748 +#define RFC_ULLRAM_O_BANK11490 0x00001748 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11491 0x0000174C +#define RFC_ULLRAM_O_BANK11491 0x0000174C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11492 0x00001750 +#define RFC_ULLRAM_O_BANK11492 0x00001750 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11493 0x00001754 +#define RFC_ULLRAM_O_BANK11493 0x00001754 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11494 0x00001758 +#define RFC_ULLRAM_O_BANK11494 0x00001758 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11495 0x0000175C +#define RFC_ULLRAM_O_BANK11495 0x0000175C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11496 0x00001760 +#define RFC_ULLRAM_O_BANK11496 0x00001760 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11497 0x00001764 +#define RFC_ULLRAM_O_BANK11497 0x00001764 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11498 0x00001768 +#define RFC_ULLRAM_O_BANK11498 0x00001768 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11499 0x0000176C +#define RFC_ULLRAM_O_BANK11499 0x0000176C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11500 0x00001770 +#define RFC_ULLRAM_O_BANK11500 0x00001770 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11501 0x00001774 +#define RFC_ULLRAM_O_BANK11501 0x00001774 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11502 0x00001778 +#define RFC_ULLRAM_O_BANK11502 0x00001778 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11503 0x0000177C +#define RFC_ULLRAM_O_BANK11503 0x0000177C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11504 0x00001780 +#define RFC_ULLRAM_O_BANK11504 0x00001780 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11505 0x00001784 +#define RFC_ULLRAM_O_BANK11505 0x00001784 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11506 0x00001788 +#define RFC_ULLRAM_O_BANK11506 0x00001788 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11507 0x0000178C +#define RFC_ULLRAM_O_BANK11507 0x0000178C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11508 0x00001790 +#define RFC_ULLRAM_O_BANK11508 0x00001790 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11509 0x00001794 +#define RFC_ULLRAM_O_BANK11509 0x00001794 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11510 0x00001798 +#define RFC_ULLRAM_O_BANK11510 0x00001798 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11511 0x0000179C +#define RFC_ULLRAM_O_BANK11511 0x0000179C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11512 0x000017A0 +#define RFC_ULLRAM_O_BANK11512 0x000017A0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11513 0x000017A4 +#define RFC_ULLRAM_O_BANK11513 0x000017A4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11514 0x000017A8 +#define RFC_ULLRAM_O_BANK11514 0x000017A8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11515 0x000017AC +#define RFC_ULLRAM_O_BANK11515 0x000017AC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11516 0x000017B0 +#define RFC_ULLRAM_O_BANK11516 0x000017B0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11517 0x000017B4 +#define RFC_ULLRAM_O_BANK11517 0x000017B4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11518 0x000017B8 +#define RFC_ULLRAM_O_BANK11518 0x000017B8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11519 0x000017BC +#define RFC_ULLRAM_O_BANK11519 0x000017BC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11520 0x000017C0 +#define RFC_ULLRAM_O_BANK11520 0x000017C0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11521 0x000017C4 +#define RFC_ULLRAM_O_BANK11521 0x000017C4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11522 0x000017C8 +#define RFC_ULLRAM_O_BANK11522 0x000017C8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11523 0x000017CC +#define RFC_ULLRAM_O_BANK11523 0x000017CC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11524 0x000017D0 +#define RFC_ULLRAM_O_BANK11524 0x000017D0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11525 0x000017D4 +#define RFC_ULLRAM_O_BANK11525 0x000017D4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11526 0x000017D8 +#define RFC_ULLRAM_O_BANK11526 0x000017D8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11527 0x000017DC +#define RFC_ULLRAM_O_BANK11527 0x000017DC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11528 0x000017E0 +#define RFC_ULLRAM_O_BANK11528 0x000017E0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11529 0x000017E4 +#define RFC_ULLRAM_O_BANK11529 0x000017E4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11530 0x000017E8 +#define RFC_ULLRAM_O_BANK11530 0x000017E8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11531 0x000017EC +#define RFC_ULLRAM_O_BANK11531 0x000017EC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11532 0x000017F0 +#define RFC_ULLRAM_O_BANK11532 0x000017F0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11533 0x000017F4 +#define RFC_ULLRAM_O_BANK11533 0x000017F4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11534 0x000017F8 +#define RFC_ULLRAM_O_BANK11534 0x000017F8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11535 0x000017FC +#define RFC_ULLRAM_O_BANK11535 0x000017FC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11536 0x00001800 +#define RFC_ULLRAM_O_BANK11536 0x00001800 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11537 0x00001804 +#define RFC_ULLRAM_O_BANK11537 0x00001804 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11538 0x00001808 +#define RFC_ULLRAM_O_BANK11538 0x00001808 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11539 0x0000180C +#define RFC_ULLRAM_O_BANK11539 0x0000180C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11540 0x00001810 +#define RFC_ULLRAM_O_BANK11540 0x00001810 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11541 0x00001814 +#define RFC_ULLRAM_O_BANK11541 0x00001814 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11542 0x00001818 +#define RFC_ULLRAM_O_BANK11542 0x00001818 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11543 0x0000181C +#define RFC_ULLRAM_O_BANK11543 0x0000181C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11544 0x00001820 +#define RFC_ULLRAM_O_BANK11544 0x00001820 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11545 0x00001824 +#define RFC_ULLRAM_O_BANK11545 0x00001824 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11546 0x00001828 +#define RFC_ULLRAM_O_BANK11546 0x00001828 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11547 0x0000182C +#define RFC_ULLRAM_O_BANK11547 0x0000182C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11548 0x00001830 +#define RFC_ULLRAM_O_BANK11548 0x00001830 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11549 0x00001834 +#define RFC_ULLRAM_O_BANK11549 0x00001834 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11550 0x00001838 +#define RFC_ULLRAM_O_BANK11550 0x00001838 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11551 0x0000183C +#define RFC_ULLRAM_O_BANK11551 0x0000183C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11552 0x00001840 +#define RFC_ULLRAM_O_BANK11552 0x00001840 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11553 0x00001844 +#define RFC_ULLRAM_O_BANK11553 0x00001844 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11554 0x00001848 +#define RFC_ULLRAM_O_BANK11554 0x00001848 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11555 0x0000184C +#define RFC_ULLRAM_O_BANK11555 0x0000184C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11556 0x00001850 +#define RFC_ULLRAM_O_BANK11556 0x00001850 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11557 0x00001854 +#define RFC_ULLRAM_O_BANK11557 0x00001854 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11558 0x00001858 +#define RFC_ULLRAM_O_BANK11558 0x00001858 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11559 0x0000185C +#define RFC_ULLRAM_O_BANK11559 0x0000185C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11560 0x00001860 +#define RFC_ULLRAM_O_BANK11560 0x00001860 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11561 0x00001864 +#define RFC_ULLRAM_O_BANK11561 0x00001864 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11562 0x00001868 +#define RFC_ULLRAM_O_BANK11562 0x00001868 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11563 0x0000186C +#define RFC_ULLRAM_O_BANK11563 0x0000186C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11564 0x00001870 +#define RFC_ULLRAM_O_BANK11564 0x00001870 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11565 0x00001874 +#define RFC_ULLRAM_O_BANK11565 0x00001874 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11566 0x00001878 +#define RFC_ULLRAM_O_BANK11566 0x00001878 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11567 0x0000187C +#define RFC_ULLRAM_O_BANK11567 0x0000187C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11568 0x00001880 +#define RFC_ULLRAM_O_BANK11568 0x00001880 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11569 0x00001884 +#define RFC_ULLRAM_O_BANK11569 0x00001884 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11570 0x00001888 +#define RFC_ULLRAM_O_BANK11570 0x00001888 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11571 0x0000188C +#define RFC_ULLRAM_O_BANK11571 0x0000188C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11572 0x00001890 +#define RFC_ULLRAM_O_BANK11572 0x00001890 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11573 0x00001894 +#define RFC_ULLRAM_O_BANK11573 0x00001894 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11574 0x00001898 +#define RFC_ULLRAM_O_BANK11574 0x00001898 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11575 0x0000189C +#define RFC_ULLRAM_O_BANK11575 0x0000189C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11576 0x000018A0 +#define RFC_ULLRAM_O_BANK11576 0x000018A0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11577 0x000018A4 +#define RFC_ULLRAM_O_BANK11577 0x000018A4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11578 0x000018A8 +#define RFC_ULLRAM_O_BANK11578 0x000018A8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11579 0x000018AC +#define RFC_ULLRAM_O_BANK11579 0x000018AC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11580 0x000018B0 +#define RFC_ULLRAM_O_BANK11580 0x000018B0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11581 0x000018B4 +#define RFC_ULLRAM_O_BANK11581 0x000018B4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11582 0x000018B8 +#define RFC_ULLRAM_O_BANK11582 0x000018B8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11583 0x000018BC +#define RFC_ULLRAM_O_BANK11583 0x000018BC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11584 0x000018C0 +#define RFC_ULLRAM_O_BANK11584 0x000018C0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11585 0x000018C4 +#define RFC_ULLRAM_O_BANK11585 0x000018C4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11586 0x000018C8 +#define RFC_ULLRAM_O_BANK11586 0x000018C8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11587 0x000018CC +#define RFC_ULLRAM_O_BANK11587 0x000018CC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11588 0x000018D0 +#define RFC_ULLRAM_O_BANK11588 0x000018D0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11589 0x000018D4 +#define RFC_ULLRAM_O_BANK11589 0x000018D4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11590 0x000018D8 +#define RFC_ULLRAM_O_BANK11590 0x000018D8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11591 0x000018DC +#define RFC_ULLRAM_O_BANK11591 0x000018DC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11592 0x000018E0 +#define RFC_ULLRAM_O_BANK11592 0x000018E0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11593 0x000018E4 +#define RFC_ULLRAM_O_BANK11593 0x000018E4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11594 0x000018E8 +#define RFC_ULLRAM_O_BANK11594 0x000018E8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11595 0x000018EC +#define RFC_ULLRAM_O_BANK11595 0x000018EC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11596 0x000018F0 +#define RFC_ULLRAM_O_BANK11596 0x000018F0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11597 0x000018F4 +#define RFC_ULLRAM_O_BANK11597 0x000018F4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11598 0x000018F8 +#define RFC_ULLRAM_O_BANK11598 0x000018F8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11599 0x000018FC +#define RFC_ULLRAM_O_BANK11599 0x000018FC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11600 0x00001900 +#define RFC_ULLRAM_O_BANK11600 0x00001900 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11601 0x00001904 +#define RFC_ULLRAM_O_BANK11601 0x00001904 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11602 0x00001908 +#define RFC_ULLRAM_O_BANK11602 0x00001908 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11603 0x0000190C +#define RFC_ULLRAM_O_BANK11603 0x0000190C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11604 0x00001910 +#define RFC_ULLRAM_O_BANK11604 0x00001910 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11605 0x00001914 +#define RFC_ULLRAM_O_BANK11605 0x00001914 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11606 0x00001918 +#define RFC_ULLRAM_O_BANK11606 0x00001918 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11607 0x0000191C +#define RFC_ULLRAM_O_BANK11607 0x0000191C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11608 0x00001920 +#define RFC_ULLRAM_O_BANK11608 0x00001920 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11609 0x00001924 +#define RFC_ULLRAM_O_BANK11609 0x00001924 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11610 0x00001928 +#define RFC_ULLRAM_O_BANK11610 0x00001928 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11611 0x0000192C +#define RFC_ULLRAM_O_BANK11611 0x0000192C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11612 0x00001930 +#define RFC_ULLRAM_O_BANK11612 0x00001930 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11613 0x00001934 +#define RFC_ULLRAM_O_BANK11613 0x00001934 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11614 0x00001938 +#define RFC_ULLRAM_O_BANK11614 0x00001938 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11615 0x0000193C +#define RFC_ULLRAM_O_BANK11615 0x0000193C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11616 0x00001940 +#define RFC_ULLRAM_O_BANK11616 0x00001940 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11617 0x00001944 +#define RFC_ULLRAM_O_BANK11617 0x00001944 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11618 0x00001948 +#define RFC_ULLRAM_O_BANK11618 0x00001948 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11619 0x0000194C +#define RFC_ULLRAM_O_BANK11619 0x0000194C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11620 0x00001950 +#define RFC_ULLRAM_O_BANK11620 0x00001950 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11621 0x00001954 +#define RFC_ULLRAM_O_BANK11621 0x00001954 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11622 0x00001958 +#define RFC_ULLRAM_O_BANK11622 0x00001958 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11623 0x0000195C +#define RFC_ULLRAM_O_BANK11623 0x0000195C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11624 0x00001960 +#define RFC_ULLRAM_O_BANK11624 0x00001960 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11625 0x00001964 +#define RFC_ULLRAM_O_BANK11625 0x00001964 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11626 0x00001968 +#define RFC_ULLRAM_O_BANK11626 0x00001968 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11627 0x0000196C +#define RFC_ULLRAM_O_BANK11627 0x0000196C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11628 0x00001970 +#define RFC_ULLRAM_O_BANK11628 0x00001970 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11629 0x00001974 +#define RFC_ULLRAM_O_BANK11629 0x00001974 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11630 0x00001978 +#define RFC_ULLRAM_O_BANK11630 0x00001978 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11631 0x0000197C +#define RFC_ULLRAM_O_BANK11631 0x0000197C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11632 0x00001980 +#define RFC_ULLRAM_O_BANK11632 0x00001980 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11633 0x00001984 +#define RFC_ULLRAM_O_BANK11633 0x00001984 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11634 0x00001988 +#define RFC_ULLRAM_O_BANK11634 0x00001988 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11635 0x0000198C +#define RFC_ULLRAM_O_BANK11635 0x0000198C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11636 0x00001990 +#define RFC_ULLRAM_O_BANK11636 0x00001990 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11637 0x00001994 +#define RFC_ULLRAM_O_BANK11637 0x00001994 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11638 0x00001998 +#define RFC_ULLRAM_O_BANK11638 0x00001998 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11639 0x0000199C +#define RFC_ULLRAM_O_BANK11639 0x0000199C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11640 0x000019A0 +#define RFC_ULLRAM_O_BANK11640 0x000019A0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11641 0x000019A4 +#define RFC_ULLRAM_O_BANK11641 0x000019A4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11642 0x000019A8 +#define RFC_ULLRAM_O_BANK11642 0x000019A8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11643 0x000019AC +#define RFC_ULLRAM_O_BANK11643 0x000019AC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11644 0x000019B0 +#define RFC_ULLRAM_O_BANK11644 0x000019B0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11645 0x000019B4 +#define RFC_ULLRAM_O_BANK11645 0x000019B4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11646 0x000019B8 +#define RFC_ULLRAM_O_BANK11646 0x000019B8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11647 0x000019BC +#define RFC_ULLRAM_O_BANK11647 0x000019BC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11648 0x000019C0 +#define RFC_ULLRAM_O_BANK11648 0x000019C0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11649 0x000019C4 +#define RFC_ULLRAM_O_BANK11649 0x000019C4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11650 0x000019C8 +#define RFC_ULLRAM_O_BANK11650 0x000019C8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11651 0x000019CC +#define RFC_ULLRAM_O_BANK11651 0x000019CC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11652 0x000019D0 +#define RFC_ULLRAM_O_BANK11652 0x000019D0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11653 0x000019D4 +#define RFC_ULLRAM_O_BANK11653 0x000019D4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11654 0x000019D8 +#define RFC_ULLRAM_O_BANK11654 0x000019D8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11655 0x000019DC +#define RFC_ULLRAM_O_BANK11655 0x000019DC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11656 0x000019E0 +#define RFC_ULLRAM_O_BANK11656 0x000019E0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11657 0x000019E4 +#define RFC_ULLRAM_O_BANK11657 0x000019E4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11658 0x000019E8 +#define RFC_ULLRAM_O_BANK11658 0x000019E8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11659 0x000019EC +#define RFC_ULLRAM_O_BANK11659 0x000019EC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11660 0x000019F0 +#define RFC_ULLRAM_O_BANK11660 0x000019F0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11661 0x000019F4 +#define RFC_ULLRAM_O_BANK11661 0x000019F4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11662 0x000019F8 +#define RFC_ULLRAM_O_BANK11662 0x000019F8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11663 0x000019FC +#define RFC_ULLRAM_O_BANK11663 0x000019FC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11664 0x00001A00 +#define RFC_ULLRAM_O_BANK11664 0x00001A00 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11665 0x00001A04 +#define RFC_ULLRAM_O_BANK11665 0x00001A04 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11666 0x00001A08 +#define RFC_ULLRAM_O_BANK11666 0x00001A08 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11667 0x00001A0C +#define RFC_ULLRAM_O_BANK11667 0x00001A0C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11668 0x00001A10 +#define RFC_ULLRAM_O_BANK11668 0x00001A10 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11669 0x00001A14 +#define RFC_ULLRAM_O_BANK11669 0x00001A14 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11670 0x00001A18 +#define RFC_ULLRAM_O_BANK11670 0x00001A18 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11671 0x00001A1C +#define RFC_ULLRAM_O_BANK11671 0x00001A1C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11672 0x00001A20 +#define RFC_ULLRAM_O_BANK11672 0x00001A20 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11673 0x00001A24 +#define RFC_ULLRAM_O_BANK11673 0x00001A24 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11674 0x00001A28 +#define RFC_ULLRAM_O_BANK11674 0x00001A28 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11675 0x00001A2C +#define RFC_ULLRAM_O_BANK11675 0x00001A2C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11676 0x00001A30 +#define RFC_ULLRAM_O_BANK11676 0x00001A30 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11677 0x00001A34 +#define RFC_ULLRAM_O_BANK11677 0x00001A34 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11678 0x00001A38 +#define RFC_ULLRAM_O_BANK11678 0x00001A38 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11679 0x00001A3C +#define RFC_ULLRAM_O_BANK11679 0x00001A3C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11680 0x00001A40 +#define RFC_ULLRAM_O_BANK11680 0x00001A40 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11681 0x00001A44 +#define RFC_ULLRAM_O_BANK11681 0x00001A44 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11682 0x00001A48 +#define RFC_ULLRAM_O_BANK11682 0x00001A48 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11683 0x00001A4C +#define RFC_ULLRAM_O_BANK11683 0x00001A4C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11684 0x00001A50 +#define RFC_ULLRAM_O_BANK11684 0x00001A50 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11685 0x00001A54 +#define RFC_ULLRAM_O_BANK11685 0x00001A54 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11686 0x00001A58 +#define RFC_ULLRAM_O_BANK11686 0x00001A58 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11687 0x00001A5C +#define RFC_ULLRAM_O_BANK11687 0x00001A5C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11688 0x00001A60 +#define RFC_ULLRAM_O_BANK11688 0x00001A60 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11689 0x00001A64 +#define RFC_ULLRAM_O_BANK11689 0x00001A64 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11690 0x00001A68 +#define RFC_ULLRAM_O_BANK11690 0x00001A68 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11691 0x00001A6C +#define RFC_ULLRAM_O_BANK11691 0x00001A6C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11692 0x00001A70 +#define RFC_ULLRAM_O_BANK11692 0x00001A70 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11693 0x00001A74 +#define RFC_ULLRAM_O_BANK11693 0x00001A74 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11694 0x00001A78 +#define RFC_ULLRAM_O_BANK11694 0x00001A78 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11695 0x00001A7C +#define RFC_ULLRAM_O_BANK11695 0x00001A7C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11696 0x00001A80 +#define RFC_ULLRAM_O_BANK11696 0x00001A80 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11697 0x00001A84 +#define RFC_ULLRAM_O_BANK11697 0x00001A84 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11698 0x00001A88 +#define RFC_ULLRAM_O_BANK11698 0x00001A88 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11699 0x00001A8C +#define RFC_ULLRAM_O_BANK11699 0x00001A8C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11700 0x00001A90 +#define RFC_ULLRAM_O_BANK11700 0x00001A90 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11701 0x00001A94 +#define RFC_ULLRAM_O_BANK11701 0x00001A94 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11702 0x00001A98 +#define RFC_ULLRAM_O_BANK11702 0x00001A98 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11703 0x00001A9C +#define RFC_ULLRAM_O_BANK11703 0x00001A9C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11704 0x00001AA0 +#define RFC_ULLRAM_O_BANK11704 0x00001AA0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11705 0x00001AA4 +#define RFC_ULLRAM_O_BANK11705 0x00001AA4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11706 0x00001AA8 +#define RFC_ULLRAM_O_BANK11706 0x00001AA8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11707 0x00001AAC +#define RFC_ULLRAM_O_BANK11707 0x00001AAC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11708 0x00001AB0 +#define RFC_ULLRAM_O_BANK11708 0x00001AB0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11709 0x00001AB4 +#define RFC_ULLRAM_O_BANK11709 0x00001AB4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11710 0x00001AB8 +#define RFC_ULLRAM_O_BANK11710 0x00001AB8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11711 0x00001ABC +#define RFC_ULLRAM_O_BANK11711 0x00001ABC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11712 0x00001AC0 +#define RFC_ULLRAM_O_BANK11712 0x00001AC0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11713 0x00001AC4 +#define RFC_ULLRAM_O_BANK11713 0x00001AC4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11714 0x00001AC8 +#define RFC_ULLRAM_O_BANK11714 0x00001AC8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11715 0x00001ACC +#define RFC_ULLRAM_O_BANK11715 0x00001ACC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11716 0x00001AD0 +#define RFC_ULLRAM_O_BANK11716 0x00001AD0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11717 0x00001AD4 +#define RFC_ULLRAM_O_BANK11717 0x00001AD4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11718 0x00001AD8 +#define RFC_ULLRAM_O_BANK11718 0x00001AD8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11719 0x00001ADC +#define RFC_ULLRAM_O_BANK11719 0x00001ADC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11720 0x00001AE0 +#define RFC_ULLRAM_O_BANK11720 0x00001AE0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11721 0x00001AE4 +#define RFC_ULLRAM_O_BANK11721 0x00001AE4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11722 0x00001AE8 +#define RFC_ULLRAM_O_BANK11722 0x00001AE8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11723 0x00001AEC +#define RFC_ULLRAM_O_BANK11723 0x00001AEC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11724 0x00001AF0 +#define RFC_ULLRAM_O_BANK11724 0x00001AF0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11725 0x00001AF4 +#define RFC_ULLRAM_O_BANK11725 0x00001AF4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11726 0x00001AF8 +#define RFC_ULLRAM_O_BANK11726 0x00001AF8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11727 0x00001AFC +#define RFC_ULLRAM_O_BANK11727 0x00001AFC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11728 0x00001B00 +#define RFC_ULLRAM_O_BANK11728 0x00001B00 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11729 0x00001B04 +#define RFC_ULLRAM_O_BANK11729 0x00001B04 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11730 0x00001B08 +#define RFC_ULLRAM_O_BANK11730 0x00001B08 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11731 0x00001B0C +#define RFC_ULLRAM_O_BANK11731 0x00001B0C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11732 0x00001B10 +#define RFC_ULLRAM_O_BANK11732 0x00001B10 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11733 0x00001B14 +#define RFC_ULLRAM_O_BANK11733 0x00001B14 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11734 0x00001B18 +#define RFC_ULLRAM_O_BANK11734 0x00001B18 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11735 0x00001B1C +#define RFC_ULLRAM_O_BANK11735 0x00001B1C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11736 0x00001B20 +#define RFC_ULLRAM_O_BANK11736 0x00001B20 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11737 0x00001B24 +#define RFC_ULLRAM_O_BANK11737 0x00001B24 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11738 0x00001B28 +#define RFC_ULLRAM_O_BANK11738 0x00001B28 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11739 0x00001B2C +#define RFC_ULLRAM_O_BANK11739 0x00001B2C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11740 0x00001B30 +#define RFC_ULLRAM_O_BANK11740 0x00001B30 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11741 0x00001B34 +#define RFC_ULLRAM_O_BANK11741 0x00001B34 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11742 0x00001B38 +#define RFC_ULLRAM_O_BANK11742 0x00001B38 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11743 0x00001B3C +#define RFC_ULLRAM_O_BANK11743 0x00001B3C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11744 0x00001B40 +#define RFC_ULLRAM_O_BANK11744 0x00001B40 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11745 0x00001B44 +#define RFC_ULLRAM_O_BANK11745 0x00001B44 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11746 0x00001B48 +#define RFC_ULLRAM_O_BANK11746 0x00001B48 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11747 0x00001B4C +#define RFC_ULLRAM_O_BANK11747 0x00001B4C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11748 0x00001B50 +#define RFC_ULLRAM_O_BANK11748 0x00001B50 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11749 0x00001B54 +#define RFC_ULLRAM_O_BANK11749 0x00001B54 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11750 0x00001B58 +#define RFC_ULLRAM_O_BANK11750 0x00001B58 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11751 0x00001B5C +#define RFC_ULLRAM_O_BANK11751 0x00001B5C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11752 0x00001B60 +#define RFC_ULLRAM_O_BANK11752 0x00001B60 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11753 0x00001B64 +#define RFC_ULLRAM_O_BANK11753 0x00001B64 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11754 0x00001B68 +#define RFC_ULLRAM_O_BANK11754 0x00001B68 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11755 0x00001B6C +#define RFC_ULLRAM_O_BANK11755 0x00001B6C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11756 0x00001B70 +#define RFC_ULLRAM_O_BANK11756 0x00001B70 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11757 0x00001B74 +#define RFC_ULLRAM_O_BANK11757 0x00001B74 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11758 0x00001B78 +#define RFC_ULLRAM_O_BANK11758 0x00001B78 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11759 0x00001B7C +#define RFC_ULLRAM_O_BANK11759 0x00001B7C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11760 0x00001B80 +#define RFC_ULLRAM_O_BANK11760 0x00001B80 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11761 0x00001B84 +#define RFC_ULLRAM_O_BANK11761 0x00001B84 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11762 0x00001B88 +#define RFC_ULLRAM_O_BANK11762 0x00001B88 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11763 0x00001B8C +#define RFC_ULLRAM_O_BANK11763 0x00001B8C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11764 0x00001B90 +#define RFC_ULLRAM_O_BANK11764 0x00001B90 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11765 0x00001B94 +#define RFC_ULLRAM_O_BANK11765 0x00001B94 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11766 0x00001B98 +#define RFC_ULLRAM_O_BANK11766 0x00001B98 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11767 0x00001B9C +#define RFC_ULLRAM_O_BANK11767 0x00001B9C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11768 0x00001BA0 +#define RFC_ULLRAM_O_BANK11768 0x00001BA0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11769 0x00001BA4 +#define RFC_ULLRAM_O_BANK11769 0x00001BA4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11770 0x00001BA8 +#define RFC_ULLRAM_O_BANK11770 0x00001BA8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11771 0x00001BAC +#define RFC_ULLRAM_O_BANK11771 0x00001BAC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11772 0x00001BB0 +#define RFC_ULLRAM_O_BANK11772 0x00001BB0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11773 0x00001BB4 +#define RFC_ULLRAM_O_BANK11773 0x00001BB4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11774 0x00001BB8 +#define RFC_ULLRAM_O_BANK11774 0x00001BB8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11775 0x00001BBC +#define RFC_ULLRAM_O_BANK11775 0x00001BBC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11776 0x00001BC0 +#define RFC_ULLRAM_O_BANK11776 0x00001BC0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11777 0x00001BC4 +#define RFC_ULLRAM_O_BANK11777 0x00001BC4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11778 0x00001BC8 +#define RFC_ULLRAM_O_BANK11778 0x00001BC8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11779 0x00001BCC +#define RFC_ULLRAM_O_BANK11779 0x00001BCC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11780 0x00001BD0 +#define RFC_ULLRAM_O_BANK11780 0x00001BD0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11781 0x00001BD4 +#define RFC_ULLRAM_O_BANK11781 0x00001BD4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11782 0x00001BD8 +#define RFC_ULLRAM_O_BANK11782 0x00001BD8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11783 0x00001BDC +#define RFC_ULLRAM_O_BANK11783 0x00001BDC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11784 0x00001BE0 +#define RFC_ULLRAM_O_BANK11784 0x00001BE0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11785 0x00001BE4 +#define RFC_ULLRAM_O_BANK11785 0x00001BE4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11786 0x00001BE8 +#define RFC_ULLRAM_O_BANK11786 0x00001BE8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11787 0x00001BEC +#define RFC_ULLRAM_O_BANK11787 0x00001BEC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11788 0x00001BF0 +#define RFC_ULLRAM_O_BANK11788 0x00001BF0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11789 0x00001BF4 +#define RFC_ULLRAM_O_BANK11789 0x00001BF4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11790 0x00001BF8 +#define RFC_ULLRAM_O_BANK11790 0x00001BF8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11791 0x00001BFC +#define RFC_ULLRAM_O_BANK11791 0x00001BFC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11792 0x00001C00 +#define RFC_ULLRAM_O_BANK11792 0x00001C00 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11793 0x00001C04 +#define RFC_ULLRAM_O_BANK11793 0x00001C04 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11794 0x00001C08 +#define RFC_ULLRAM_O_BANK11794 0x00001C08 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11795 0x00001C0C +#define RFC_ULLRAM_O_BANK11795 0x00001C0C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11796 0x00001C10 +#define RFC_ULLRAM_O_BANK11796 0x00001C10 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11797 0x00001C14 +#define RFC_ULLRAM_O_BANK11797 0x00001C14 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11798 0x00001C18 +#define RFC_ULLRAM_O_BANK11798 0x00001C18 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11799 0x00001C1C +#define RFC_ULLRAM_O_BANK11799 0x00001C1C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11800 0x00001C20 +#define RFC_ULLRAM_O_BANK11800 0x00001C20 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11801 0x00001C24 +#define RFC_ULLRAM_O_BANK11801 0x00001C24 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11802 0x00001C28 +#define RFC_ULLRAM_O_BANK11802 0x00001C28 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11803 0x00001C2C +#define RFC_ULLRAM_O_BANK11803 0x00001C2C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11804 0x00001C30 +#define RFC_ULLRAM_O_BANK11804 0x00001C30 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11805 0x00001C34 +#define RFC_ULLRAM_O_BANK11805 0x00001C34 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11806 0x00001C38 +#define RFC_ULLRAM_O_BANK11806 0x00001C38 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11807 0x00001C3C +#define RFC_ULLRAM_O_BANK11807 0x00001C3C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11808 0x00001C40 +#define RFC_ULLRAM_O_BANK11808 0x00001C40 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11809 0x00001C44 +#define RFC_ULLRAM_O_BANK11809 0x00001C44 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11810 0x00001C48 +#define RFC_ULLRAM_O_BANK11810 0x00001C48 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11811 0x00001C4C +#define RFC_ULLRAM_O_BANK11811 0x00001C4C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11812 0x00001C50 +#define RFC_ULLRAM_O_BANK11812 0x00001C50 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11813 0x00001C54 +#define RFC_ULLRAM_O_BANK11813 0x00001C54 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11814 0x00001C58 +#define RFC_ULLRAM_O_BANK11814 0x00001C58 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11815 0x00001C5C +#define RFC_ULLRAM_O_BANK11815 0x00001C5C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11816 0x00001C60 +#define RFC_ULLRAM_O_BANK11816 0x00001C60 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11817 0x00001C64 +#define RFC_ULLRAM_O_BANK11817 0x00001C64 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11818 0x00001C68 +#define RFC_ULLRAM_O_BANK11818 0x00001C68 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11819 0x00001C6C +#define RFC_ULLRAM_O_BANK11819 0x00001C6C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11820 0x00001C70 +#define RFC_ULLRAM_O_BANK11820 0x00001C70 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11821 0x00001C74 +#define RFC_ULLRAM_O_BANK11821 0x00001C74 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11822 0x00001C78 +#define RFC_ULLRAM_O_BANK11822 0x00001C78 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11823 0x00001C7C +#define RFC_ULLRAM_O_BANK11823 0x00001C7C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11824 0x00001C80 +#define RFC_ULLRAM_O_BANK11824 0x00001C80 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11825 0x00001C84 +#define RFC_ULLRAM_O_BANK11825 0x00001C84 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11826 0x00001C88 +#define RFC_ULLRAM_O_BANK11826 0x00001C88 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11827 0x00001C8C +#define RFC_ULLRAM_O_BANK11827 0x00001C8C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11828 0x00001C90 +#define RFC_ULLRAM_O_BANK11828 0x00001C90 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11829 0x00001C94 +#define RFC_ULLRAM_O_BANK11829 0x00001C94 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11830 0x00001C98 +#define RFC_ULLRAM_O_BANK11830 0x00001C98 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11831 0x00001C9C +#define RFC_ULLRAM_O_BANK11831 0x00001C9C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11832 0x00001CA0 +#define RFC_ULLRAM_O_BANK11832 0x00001CA0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11833 0x00001CA4 +#define RFC_ULLRAM_O_BANK11833 0x00001CA4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11834 0x00001CA8 +#define RFC_ULLRAM_O_BANK11834 0x00001CA8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11835 0x00001CAC +#define RFC_ULLRAM_O_BANK11835 0x00001CAC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11836 0x00001CB0 +#define RFC_ULLRAM_O_BANK11836 0x00001CB0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11837 0x00001CB4 +#define RFC_ULLRAM_O_BANK11837 0x00001CB4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11838 0x00001CB8 +#define RFC_ULLRAM_O_BANK11838 0x00001CB8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11839 0x00001CBC +#define RFC_ULLRAM_O_BANK11839 0x00001CBC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11840 0x00001CC0 +#define RFC_ULLRAM_O_BANK11840 0x00001CC0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11841 0x00001CC4 +#define RFC_ULLRAM_O_BANK11841 0x00001CC4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11842 0x00001CC8 +#define RFC_ULLRAM_O_BANK11842 0x00001CC8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11843 0x00001CCC +#define RFC_ULLRAM_O_BANK11843 0x00001CCC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11844 0x00001CD0 +#define RFC_ULLRAM_O_BANK11844 0x00001CD0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11845 0x00001CD4 +#define RFC_ULLRAM_O_BANK11845 0x00001CD4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11846 0x00001CD8 +#define RFC_ULLRAM_O_BANK11846 0x00001CD8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11847 0x00001CDC +#define RFC_ULLRAM_O_BANK11847 0x00001CDC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11848 0x00001CE0 +#define RFC_ULLRAM_O_BANK11848 0x00001CE0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11849 0x00001CE4 +#define RFC_ULLRAM_O_BANK11849 0x00001CE4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11850 0x00001CE8 +#define RFC_ULLRAM_O_BANK11850 0x00001CE8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11851 0x00001CEC +#define RFC_ULLRAM_O_BANK11851 0x00001CEC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11852 0x00001CF0 +#define RFC_ULLRAM_O_BANK11852 0x00001CF0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11853 0x00001CF4 +#define RFC_ULLRAM_O_BANK11853 0x00001CF4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11854 0x00001CF8 +#define RFC_ULLRAM_O_BANK11854 0x00001CF8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11855 0x00001CFC +#define RFC_ULLRAM_O_BANK11855 0x00001CFC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11856 0x00001D00 +#define RFC_ULLRAM_O_BANK11856 0x00001D00 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11857 0x00001D04 +#define RFC_ULLRAM_O_BANK11857 0x00001D04 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11858 0x00001D08 +#define RFC_ULLRAM_O_BANK11858 0x00001D08 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11859 0x00001D0C +#define RFC_ULLRAM_O_BANK11859 0x00001D0C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11860 0x00001D10 +#define RFC_ULLRAM_O_BANK11860 0x00001D10 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11861 0x00001D14 +#define RFC_ULLRAM_O_BANK11861 0x00001D14 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11862 0x00001D18 +#define RFC_ULLRAM_O_BANK11862 0x00001D18 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11863 0x00001D1C +#define RFC_ULLRAM_O_BANK11863 0x00001D1C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11864 0x00001D20 +#define RFC_ULLRAM_O_BANK11864 0x00001D20 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11865 0x00001D24 +#define RFC_ULLRAM_O_BANK11865 0x00001D24 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11866 0x00001D28 +#define RFC_ULLRAM_O_BANK11866 0x00001D28 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11867 0x00001D2C +#define RFC_ULLRAM_O_BANK11867 0x00001D2C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11868 0x00001D30 +#define RFC_ULLRAM_O_BANK11868 0x00001D30 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11869 0x00001D34 +#define RFC_ULLRAM_O_BANK11869 0x00001D34 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11870 0x00001D38 +#define RFC_ULLRAM_O_BANK11870 0x00001D38 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11871 0x00001D3C +#define RFC_ULLRAM_O_BANK11871 0x00001D3C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11872 0x00001D40 +#define RFC_ULLRAM_O_BANK11872 0x00001D40 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11873 0x00001D44 +#define RFC_ULLRAM_O_BANK11873 0x00001D44 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11874 0x00001D48 +#define RFC_ULLRAM_O_BANK11874 0x00001D48 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11875 0x00001D4C +#define RFC_ULLRAM_O_BANK11875 0x00001D4C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11876 0x00001D50 +#define RFC_ULLRAM_O_BANK11876 0x00001D50 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11877 0x00001D54 +#define RFC_ULLRAM_O_BANK11877 0x00001D54 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11878 0x00001D58 +#define RFC_ULLRAM_O_BANK11878 0x00001D58 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11879 0x00001D5C +#define RFC_ULLRAM_O_BANK11879 0x00001D5C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11880 0x00001D60 +#define RFC_ULLRAM_O_BANK11880 0x00001D60 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11881 0x00001D64 +#define RFC_ULLRAM_O_BANK11881 0x00001D64 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11882 0x00001D68 +#define RFC_ULLRAM_O_BANK11882 0x00001D68 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11883 0x00001D6C +#define RFC_ULLRAM_O_BANK11883 0x00001D6C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11884 0x00001D70 +#define RFC_ULLRAM_O_BANK11884 0x00001D70 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11885 0x00001D74 +#define RFC_ULLRAM_O_BANK11885 0x00001D74 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11886 0x00001D78 +#define RFC_ULLRAM_O_BANK11886 0x00001D78 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11887 0x00001D7C +#define RFC_ULLRAM_O_BANK11887 0x00001D7C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11888 0x00001D80 +#define RFC_ULLRAM_O_BANK11888 0x00001D80 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11889 0x00001D84 +#define RFC_ULLRAM_O_BANK11889 0x00001D84 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11890 0x00001D88 +#define RFC_ULLRAM_O_BANK11890 0x00001D88 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11891 0x00001D8C +#define RFC_ULLRAM_O_BANK11891 0x00001D8C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11892 0x00001D90 +#define RFC_ULLRAM_O_BANK11892 0x00001D90 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11893 0x00001D94 +#define RFC_ULLRAM_O_BANK11893 0x00001D94 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11894 0x00001D98 +#define RFC_ULLRAM_O_BANK11894 0x00001D98 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11895 0x00001D9C +#define RFC_ULLRAM_O_BANK11895 0x00001D9C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11896 0x00001DA0 +#define RFC_ULLRAM_O_BANK11896 0x00001DA0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11897 0x00001DA4 +#define RFC_ULLRAM_O_BANK11897 0x00001DA4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11898 0x00001DA8 +#define RFC_ULLRAM_O_BANK11898 0x00001DA8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11899 0x00001DAC +#define RFC_ULLRAM_O_BANK11899 0x00001DAC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11900 0x00001DB0 +#define RFC_ULLRAM_O_BANK11900 0x00001DB0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11901 0x00001DB4 +#define RFC_ULLRAM_O_BANK11901 0x00001DB4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11902 0x00001DB8 +#define RFC_ULLRAM_O_BANK11902 0x00001DB8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11903 0x00001DBC +#define RFC_ULLRAM_O_BANK11903 0x00001DBC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11904 0x00001DC0 +#define RFC_ULLRAM_O_BANK11904 0x00001DC0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11905 0x00001DC4 +#define RFC_ULLRAM_O_BANK11905 0x00001DC4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11906 0x00001DC8 +#define RFC_ULLRAM_O_BANK11906 0x00001DC8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11907 0x00001DCC +#define RFC_ULLRAM_O_BANK11907 0x00001DCC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11908 0x00001DD0 +#define RFC_ULLRAM_O_BANK11908 0x00001DD0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11909 0x00001DD4 +#define RFC_ULLRAM_O_BANK11909 0x00001DD4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11910 0x00001DD8 +#define RFC_ULLRAM_O_BANK11910 0x00001DD8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11911 0x00001DDC +#define RFC_ULLRAM_O_BANK11911 0x00001DDC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11912 0x00001DE0 +#define RFC_ULLRAM_O_BANK11912 0x00001DE0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11913 0x00001DE4 +#define RFC_ULLRAM_O_BANK11913 0x00001DE4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11914 0x00001DE8 +#define RFC_ULLRAM_O_BANK11914 0x00001DE8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11915 0x00001DEC +#define RFC_ULLRAM_O_BANK11915 0x00001DEC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11916 0x00001DF0 +#define RFC_ULLRAM_O_BANK11916 0x00001DF0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11917 0x00001DF4 +#define RFC_ULLRAM_O_BANK11917 0x00001DF4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11918 0x00001DF8 +#define RFC_ULLRAM_O_BANK11918 0x00001DF8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11919 0x00001DFC +#define RFC_ULLRAM_O_BANK11919 0x00001DFC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11920 0x00001E00 +#define RFC_ULLRAM_O_BANK11920 0x00001E00 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11921 0x00001E04 +#define RFC_ULLRAM_O_BANK11921 0x00001E04 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11922 0x00001E08 +#define RFC_ULLRAM_O_BANK11922 0x00001E08 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11923 0x00001E0C +#define RFC_ULLRAM_O_BANK11923 0x00001E0C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11924 0x00001E10 +#define RFC_ULLRAM_O_BANK11924 0x00001E10 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11925 0x00001E14 +#define RFC_ULLRAM_O_BANK11925 0x00001E14 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11926 0x00001E18 +#define RFC_ULLRAM_O_BANK11926 0x00001E18 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11927 0x00001E1C +#define RFC_ULLRAM_O_BANK11927 0x00001E1C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11928 0x00001E20 +#define RFC_ULLRAM_O_BANK11928 0x00001E20 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11929 0x00001E24 +#define RFC_ULLRAM_O_BANK11929 0x00001E24 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11930 0x00001E28 +#define RFC_ULLRAM_O_BANK11930 0x00001E28 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11931 0x00001E2C +#define RFC_ULLRAM_O_BANK11931 0x00001E2C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11932 0x00001E30 +#define RFC_ULLRAM_O_BANK11932 0x00001E30 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11933 0x00001E34 +#define RFC_ULLRAM_O_BANK11933 0x00001E34 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11934 0x00001E38 +#define RFC_ULLRAM_O_BANK11934 0x00001E38 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11935 0x00001E3C +#define RFC_ULLRAM_O_BANK11935 0x00001E3C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11936 0x00001E40 +#define RFC_ULLRAM_O_BANK11936 0x00001E40 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11937 0x00001E44 +#define RFC_ULLRAM_O_BANK11937 0x00001E44 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11938 0x00001E48 +#define RFC_ULLRAM_O_BANK11938 0x00001E48 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11939 0x00001E4C +#define RFC_ULLRAM_O_BANK11939 0x00001E4C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11940 0x00001E50 +#define RFC_ULLRAM_O_BANK11940 0x00001E50 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11941 0x00001E54 +#define RFC_ULLRAM_O_BANK11941 0x00001E54 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11942 0x00001E58 +#define RFC_ULLRAM_O_BANK11942 0x00001E58 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11943 0x00001E5C +#define RFC_ULLRAM_O_BANK11943 0x00001E5C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11944 0x00001E60 +#define RFC_ULLRAM_O_BANK11944 0x00001E60 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11945 0x00001E64 +#define RFC_ULLRAM_O_BANK11945 0x00001E64 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11946 0x00001E68 +#define RFC_ULLRAM_O_BANK11946 0x00001E68 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11947 0x00001E6C +#define RFC_ULLRAM_O_BANK11947 0x00001E6C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11948 0x00001E70 +#define RFC_ULLRAM_O_BANK11948 0x00001E70 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11949 0x00001E74 +#define RFC_ULLRAM_O_BANK11949 0x00001E74 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11950 0x00001E78 +#define RFC_ULLRAM_O_BANK11950 0x00001E78 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11951 0x00001E7C +#define RFC_ULLRAM_O_BANK11951 0x00001E7C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11952 0x00001E80 +#define RFC_ULLRAM_O_BANK11952 0x00001E80 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11953 0x00001E84 +#define RFC_ULLRAM_O_BANK11953 0x00001E84 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11954 0x00001E88 +#define RFC_ULLRAM_O_BANK11954 0x00001E88 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11955 0x00001E8C +#define RFC_ULLRAM_O_BANK11955 0x00001E8C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11956 0x00001E90 +#define RFC_ULLRAM_O_BANK11956 0x00001E90 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11957 0x00001E94 +#define RFC_ULLRAM_O_BANK11957 0x00001E94 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11958 0x00001E98 +#define RFC_ULLRAM_O_BANK11958 0x00001E98 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11959 0x00001E9C +#define RFC_ULLRAM_O_BANK11959 0x00001E9C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11960 0x00001EA0 +#define RFC_ULLRAM_O_BANK11960 0x00001EA0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11961 0x00001EA4 +#define RFC_ULLRAM_O_BANK11961 0x00001EA4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11962 0x00001EA8 +#define RFC_ULLRAM_O_BANK11962 0x00001EA8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11963 0x00001EAC +#define RFC_ULLRAM_O_BANK11963 0x00001EAC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11964 0x00001EB0 +#define RFC_ULLRAM_O_BANK11964 0x00001EB0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11965 0x00001EB4 +#define RFC_ULLRAM_O_BANK11965 0x00001EB4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11966 0x00001EB8 +#define RFC_ULLRAM_O_BANK11966 0x00001EB8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11967 0x00001EBC +#define RFC_ULLRAM_O_BANK11967 0x00001EBC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11968 0x00001EC0 +#define RFC_ULLRAM_O_BANK11968 0x00001EC0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11969 0x00001EC4 +#define RFC_ULLRAM_O_BANK11969 0x00001EC4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11970 0x00001EC8 +#define RFC_ULLRAM_O_BANK11970 0x00001EC8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11971 0x00001ECC +#define RFC_ULLRAM_O_BANK11971 0x00001ECC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11972 0x00001ED0 +#define RFC_ULLRAM_O_BANK11972 0x00001ED0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11973 0x00001ED4 +#define RFC_ULLRAM_O_BANK11973 0x00001ED4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11974 0x00001ED8 +#define RFC_ULLRAM_O_BANK11974 0x00001ED8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11975 0x00001EDC +#define RFC_ULLRAM_O_BANK11975 0x00001EDC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11976 0x00001EE0 +#define RFC_ULLRAM_O_BANK11976 0x00001EE0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11977 0x00001EE4 +#define RFC_ULLRAM_O_BANK11977 0x00001EE4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11978 0x00001EE8 +#define RFC_ULLRAM_O_BANK11978 0x00001EE8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11979 0x00001EEC +#define RFC_ULLRAM_O_BANK11979 0x00001EEC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11980 0x00001EF0 +#define RFC_ULLRAM_O_BANK11980 0x00001EF0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11981 0x00001EF4 +#define RFC_ULLRAM_O_BANK11981 0x00001EF4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11982 0x00001EF8 +#define RFC_ULLRAM_O_BANK11982 0x00001EF8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11983 0x00001EFC +#define RFC_ULLRAM_O_BANK11983 0x00001EFC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11984 0x00001F00 +#define RFC_ULLRAM_O_BANK11984 0x00001F00 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11985 0x00001F04 +#define RFC_ULLRAM_O_BANK11985 0x00001F04 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11986 0x00001F08 +#define RFC_ULLRAM_O_BANK11986 0x00001F08 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11987 0x00001F0C +#define RFC_ULLRAM_O_BANK11987 0x00001F0C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11988 0x00001F10 +#define RFC_ULLRAM_O_BANK11988 0x00001F10 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11989 0x00001F14 +#define RFC_ULLRAM_O_BANK11989 0x00001F14 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11990 0x00001F18 +#define RFC_ULLRAM_O_BANK11990 0x00001F18 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11991 0x00001F1C +#define RFC_ULLRAM_O_BANK11991 0x00001F1C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11992 0x00001F20 +#define RFC_ULLRAM_O_BANK11992 0x00001F20 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11993 0x00001F24 +#define RFC_ULLRAM_O_BANK11993 0x00001F24 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11994 0x00001F28 +#define RFC_ULLRAM_O_BANK11994 0x00001F28 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11995 0x00001F2C +#define RFC_ULLRAM_O_BANK11995 0x00001F2C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11996 0x00001F30 +#define RFC_ULLRAM_O_BANK11996 0x00001F30 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11997 0x00001F34 +#define RFC_ULLRAM_O_BANK11997 0x00001F34 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11998 0x00001F38 +#define RFC_ULLRAM_O_BANK11998 0x00001F38 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11999 0x00001F3C +#define RFC_ULLRAM_O_BANK11999 0x00001F3C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12000 0x00001F40 +#define RFC_ULLRAM_O_BANK12000 0x00001F40 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12001 0x00001F44 +#define RFC_ULLRAM_O_BANK12001 0x00001F44 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12002 0x00001F48 +#define RFC_ULLRAM_O_BANK12002 0x00001F48 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12003 0x00001F4C +#define RFC_ULLRAM_O_BANK12003 0x00001F4C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12004 0x00001F50 +#define RFC_ULLRAM_O_BANK12004 0x00001F50 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12005 0x00001F54 +#define RFC_ULLRAM_O_BANK12005 0x00001F54 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12006 0x00001F58 +#define RFC_ULLRAM_O_BANK12006 0x00001F58 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12007 0x00001F5C +#define RFC_ULLRAM_O_BANK12007 0x00001F5C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12008 0x00001F60 +#define RFC_ULLRAM_O_BANK12008 0x00001F60 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12009 0x00001F64 +#define RFC_ULLRAM_O_BANK12009 0x00001F64 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12010 0x00001F68 +#define RFC_ULLRAM_O_BANK12010 0x00001F68 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12011 0x00001F6C +#define RFC_ULLRAM_O_BANK12011 0x00001F6C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12012 0x00001F70 +#define RFC_ULLRAM_O_BANK12012 0x00001F70 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12013 0x00001F74 +#define RFC_ULLRAM_O_BANK12013 0x00001F74 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12014 0x00001F78 +#define RFC_ULLRAM_O_BANK12014 0x00001F78 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12015 0x00001F7C +#define RFC_ULLRAM_O_BANK12015 0x00001F7C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12016 0x00001F80 +#define RFC_ULLRAM_O_BANK12016 0x00001F80 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12017 0x00001F84 +#define RFC_ULLRAM_O_BANK12017 0x00001F84 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12018 0x00001F88 +#define RFC_ULLRAM_O_BANK12018 0x00001F88 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12019 0x00001F8C +#define RFC_ULLRAM_O_BANK12019 0x00001F8C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12020 0x00001F90 +#define RFC_ULLRAM_O_BANK12020 0x00001F90 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12021 0x00001F94 +#define RFC_ULLRAM_O_BANK12021 0x00001F94 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12022 0x00001F98 +#define RFC_ULLRAM_O_BANK12022 0x00001F98 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12023 0x00001F9C +#define RFC_ULLRAM_O_BANK12023 0x00001F9C // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12024 0x00001FA0 +#define RFC_ULLRAM_O_BANK12024 0x00001FA0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12025 0x00001FA4 +#define RFC_ULLRAM_O_BANK12025 0x00001FA4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12026 0x00001FA8 +#define RFC_ULLRAM_O_BANK12026 0x00001FA8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12027 0x00001FAC +#define RFC_ULLRAM_O_BANK12027 0x00001FAC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12028 0x00001FB0 +#define RFC_ULLRAM_O_BANK12028 0x00001FB0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12029 0x00001FB4 +#define RFC_ULLRAM_O_BANK12029 0x00001FB4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12030 0x00001FB8 +#define RFC_ULLRAM_O_BANK12030 0x00001FB8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12031 0x00001FBC +#define RFC_ULLRAM_O_BANK12031 0x00001FBC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12032 0x00001FC0 +#define RFC_ULLRAM_O_BANK12032 0x00001FC0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12033 0x00001FC4 +#define RFC_ULLRAM_O_BANK12033 0x00001FC4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12034 0x00001FC8 +#define RFC_ULLRAM_O_BANK12034 0x00001FC8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12035 0x00001FCC +#define RFC_ULLRAM_O_BANK12035 0x00001FCC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12036 0x00001FD0 +#define RFC_ULLRAM_O_BANK12036 0x00001FD0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12037 0x00001FD4 +#define RFC_ULLRAM_O_BANK12037 0x00001FD4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12038 0x00001FD8 +#define RFC_ULLRAM_O_BANK12038 0x00001FD8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12039 0x00001FDC +#define RFC_ULLRAM_O_BANK12039 0x00001FDC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12040 0x00001FE0 +#define RFC_ULLRAM_O_BANK12040 0x00001FE0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12041 0x00001FE4 +#define RFC_ULLRAM_O_BANK12041 0x00001FE4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12042 0x00001FE8 +#define RFC_ULLRAM_O_BANK12042 0x00001FE8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12043 0x00001FEC +#define RFC_ULLRAM_O_BANK12043 0x00001FEC // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12044 0x00001FF0 +#define RFC_ULLRAM_O_BANK12044 0x00001FF0 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12045 0x00001FF4 +#define RFC_ULLRAM_O_BANK12045 0x00001FF4 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12046 0x00001FF8 +#define RFC_ULLRAM_O_BANK12046 0x00001FF8 // 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12047 0x00001FFC +#define RFC_ULLRAM_O_BANK12047 0x00001FFC //***************************************************************************** // @@ -6195,9 +6195,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK10_DATA_W 32 -#define RFC_ULLRAM_BANK10_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK10_DATA_S 0 +#define RFC_ULLRAM_BANK10_DATA_W 32 +#define RFC_ULLRAM_BANK10_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK10_DATA_S 0 //***************************************************************************** // @@ -6207,9 +6207,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11_DATA_W 32 -#define RFC_ULLRAM_BANK11_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11_DATA_S 0 +#define RFC_ULLRAM_BANK11_DATA_W 32 +#define RFC_ULLRAM_BANK11_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11_DATA_S 0 //***************************************************************************** // @@ -6219,9 +6219,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12_DATA_W 32 -#define RFC_ULLRAM_BANK12_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12_DATA_S 0 +#define RFC_ULLRAM_BANK12_DATA_W 32 +#define RFC_ULLRAM_BANK12_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12_DATA_S 0 //***************************************************************************** // @@ -6231,9 +6231,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK13_DATA_W 32 -#define RFC_ULLRAM_BANK13_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK13_DATA_S 0 +#define RFC_ULLRAM_BANK13_DATA_W 32 +#define RFC_ULLRAM_BANK13_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK13_DATA_S 0 //***************************************************************************** // @@ -6243,9 +6243,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK14_DATA_W 32 -#define RFC_ULLRAM_BANK14_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK14_DATA_S 0 +#define RFC_ULLRAM_BANK14_DATA_W 32 +#define RFC_ULLRAM_BANK14_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK14_DATA_S 0 //***************************************************************************** // @@ -6255,9 +6255,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK15_DATA_W 32 -#define RFC_ULLRAM_BANK15_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK15_DATA_S 0 +#define RFC_ULLRAM_BANK15_DATA_W 32 +#define RFC_ULLRAM_BANK15_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK15_DATA_S 0 //***************************************************************************** // @@ -6267,9 +6267,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK16_DATA_W 32 -#define RFC_ULLRAM_BANK16_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK16_DATA_S 0 +#define RFC_ULLRAM_BANK16_DATA_W 32 +#define RFC_ULLRAM_BANK16_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK16_DATA_S 0 //***************************************************************************** // @@ -6279,9 +6279,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK17_DATA_W 32 -#define RFC_ULLRAM_BANK17_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK17_DATA_S 0 +#define RFC_ULLRAM_BANK17_DATA_W 32 +#define RFC_ULLRAM_BANK17_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK17_DATA_S 0 //***************************************************************************** // @@ -6291,9 +6291,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK18_DATA_W 32 -#define RFC_ULLRAM_BANK18_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK18_DATA_S 0 +#define RFC_ULLRAM_BANK18_DATA_W 32 +#define RFC_ULLRAM_BANK18_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK18_DATA_S 0 //***************************************************************************** // @@ -6303,9 +6303,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK19_DATA_W 32 -#define RFC_ULLRAM_BANK19_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK19_DATA_S 0 +#define RFC_ULLRAM_BANK19_DATA_W 32 +#define RFC_ULLRAM_BANK19_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK19_DATA_S 0 //***************************************************************************** // @@ -6315,9 +6315,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK110_DATA_W 32 -#define RFC_ULLRAM_BANK110_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK110_DATA_S 0 +#define RFC_ULLRAM_BANK110_DATA_W 32 +#define RFC_ULLRAM_BANK110_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK110_DATA_S 0 //***************************************************************************** // @@ -6327,9 +6327,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK111_DATA_W 32 -#define RFC_ULLRAM_BANK111_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK111_DATA_S 0 +#define RFC_ULLRAM_BANK111_DATA_W 32 +#define RFC_ULLRAM_BANK111_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK111_DATA_S 0 //***************************************************************************** // @@ -6339,9 +6339,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK112_DATA_W 32 -#define RFC_ULLRAM_BANK112_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK112_DATA_S 0 +#define RFC_ULLRAM_BANK112_DATA_W 32 +#define RFC_ULLRAM_BANK112_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK112_DATA_S 0 //***************************************************************************** // @@ -6351,9 +6351,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK113_DATA_W 32 -#define RFC_ULLRAM_BANK113_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK113_DATA_S 0 +#define RFC_ULLRAM_BANK113_DATA_W 32 +#define RFC_ULLRAM_BANK113_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK113_DATA_S 0 //***************************************************************************** // @@ -6363,9 +6363,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK114_DATA_W 32 -#define RFC_ULLRAM_BANK114_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK114_DATA_S 0 +#define RFC_ULLRAM_BANK114_DATA_W 32 +#define RFC_ULLRAM_BANK114_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK114_DATA_S 0 //***************************************************************************** // @@ -6375,9 +6375,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK115_DATA_W 32 -#define RFC_ULLRAM_BANK115_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK115_DATA_S 0 +#define RFC_ULLRAM_BANK115_DATA_W 32 +#define RFC_ULLRAM_BANK115_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK115_DATA_S 0 //***************************************************************************** // @@ -6387,9 +6387,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK116_DATA_W 32 -#define RFC_ULLRAM_BANK116_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK116_DATA_S 0 +#define RFC_ULLRAM_BANK116_DATA_W 32 +#define RFC_ULLRAM_BANK116_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK116_DATA_S 0 //***************************************************************************** // @@ -6399,9 +6399,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK117_DATA_W 32 -#define RFC_ULLRAM_BANK117_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK117_DATA_S 0 +#define RFC_ULLRAM_BANK117_DATA_W 32 +#define RFC_ULLRAM_BANK117_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK117_DATA_S 0 //***************************************************************************** // @@ -6411,9 +6411,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK118_DATA_W 32 -#define RFC_ULLRAM_BANK118_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK118_DATA_S 0 +#define RFC_ULLRAM_BANK118_DATA_W 32 +#define RFC_ULLRAM_BANK118_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK118_DATA_S 0 //***************************************************************************** // @@ -6423,9 +6423,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK119_DATA_W 32 -#define RFC_ULLRAM_BANK119_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK119_DATA_S 0 +#define RFC_ULLRAM_BANK119_DATA_W 32 +#define RFC_ULLRAM_BANK119_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK119_DATA_S 0 //***************************************************************************** // @@ -6435,9 +6435,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK120_DATA_W 32 -#define RFC_ULLRAM_BANK120_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK120_DATA_S 0 +#define RFC_ULLRAM_BANK120_DATA_W 32 +#define RFC_ULLRAM_BANK120_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK120_DATA_S 0 //***************************************************************************** // @@ -6447,9 +6447,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK121_DATA_W 32 -#define RFC_ULLRAM_BANK121_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK121_DATA_S 0 +#define RFC_ULLRAM_BANK121_DATA_W 32 +#define RFC_ULLRAM_BANK121_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK121_DATA_S 0 //***************************************************************************** // @@ -6459,9 +6459,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK122_DATA_W 32 -#define RFC_ULLRAM_BANK122_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK122_DATA_S 0 +#define RFC_ULLRAM_BANK122_DATA_W 32 +#define RFC_ULLRAM_BANK122_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK122_DATA_S 0 //***************************************************************************** // @@ -6471,9 +6471,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK123_DATA_W 32 -#define RFC_ULLRAM_BANK123_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK123_DATA_S 0 +#define RFC_ULLRAM_BANK123_DATA_W 32 +#define RFC_ULLRAM_BANK123_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK123_DATA_S 0 //***************************************************************************** // @@ -6483,9 +6483,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK124_DATA_W 32 -#define RFC_ULLRAM_BANK124_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK124_DATA_S 0 +#define RFC_ULLRAM_BANK124_DATA_W 32 +#define RFC_ULLRAM_BANK124_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK124_DATA_S 0 //***************************************************************************** // @@ -6495,9 +6495,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK125_DATA_W 32 -#define RFC_ULLRAM_BANK125_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK125_DATA_S 0 +#define RFC_ULLRAM_BANK125_DATA_W 32 +#define RFC_ULLRAM_BANK125_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK125_DATA_S 0 //***************************************************************************** // @@ -6507,9 +6507,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK126_DATA_W 32 -#define RFC_ULLRAM_BANK126_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK126_DATA_S 0 +#define RFC_ULLRAM_BANK126_DATA_W 32 +#define RFC_ULLRAM_BANK126_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK126_DATA_S 0 //***************************************************************************** // @@ -6519,9 +6519,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK127_DATA_W 32 -#define RFC_ULLRAM_BANK127_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK127_DATA_S 0 +#define RFC_ULLRAM_BANK127_DATA_W 32 +#define RFC_ULLRAM_BANK127_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK127_DATA_S 0 //***************************************************************************** // @@ -6531,9 +6531,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK128_DATA_W 32 -#define RFC_ULLRAM_BANK128_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK128_DATA_S 0 +#define RFC_ULLRAM_BANK128_DATA_W 32 +#define RFC_ULLRAM_BANK128_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK128_DATA_S 0 //***************************************************************************** // @@ -6543,9 +6543,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK129_DATA_W 32 -#define RFC_ULLRAM_BANK129_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK129_DATA_S 0 +#define RFC_ULLRAM_BANK129_DATA_W 32 +#define RFC_ULLRAM_BANK129_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK129_DATA_S 0 //***************************************************************************** // @@ -6555,9 +6555,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK130_DATA_W 32 -#define RFC_ULLRAM_BANK130_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK130_DATA_S 0 +#define RFC_ULLRAM_BANK130_DATA_W 32 +#define RFC_ULLRAM_BANK130_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK130_DATA_S 0 //***************************************************************************** // @@ -6567,9 +6567,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK131_DATA_W 32 -#define RFC_ULLRAM_BANK131_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK131_DATA_S 0 +#define RFC_ULLRAM_BANK131_DATA_W 32 +#define RFC_ULLRAM_BANK131_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK131_DATA_S 0 //***************************************************************************** // @@ -6579,9 +6579,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK132_DATA_W 32 -#define RFC_ULLRAM_BANK132_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK132_DATA_S 0 +#define RFC_ULLRAM_BANK132_DATA_W 32 +#define RFC_ULLRAM_BANK132_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK132_DATA_S 0 //***************************************************************************** // @@ -6591,9 +6591,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK133_DATA_W 32 -#define RFC_ULLRAM_BANK133_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK133_DATA_S 0 +#define RFC_ULLRAM_BANK133_DATA_W 32 +#define RFC_ULLRAM_BANK133_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK133_DATA_S 0 //***************************************************************************** // @@ -6603,9 +6603,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK134_DATA_W 32 -#define RFC_ULLRAM_BANK134_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK134_DATA_S 0 +#define RFC_ULLRAM_BANK134_DATA_W 32 +#define RFC_ULLRAM_BANK134_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK134_DATA_S 0 //***************************************************************************** // @@ -6615,9 +6615,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK135_DATA_W 32 -#define RFC_ULLRAM_BANK135_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK135_DATA_S 0 +#define RFC_ULLRAM_BANK135_DATA_W 32 +#define RFC_ULLRAM_BANK135_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK135_DATA_S 0 //***************************************************************************** // @@ -6627,9 +6627,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK136_DATA_W 32 -#define RFC_ULLRAM_BANK136_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK136_DATA_S 0 +#define RFC_ULLRAM_BANK136_DATA_W 32 +#define RFC_ULLRAM_BANK136_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK136_DATA_S 0 //***************************************************************************** // @@ -6639,9 +6639,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK137_DATA_W 32 -#define RFC_ULLRAM_BANK137_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK137_DATA_S 0 +#define RFC_ULLRAM_BANK137_DATA_W 32 +#define RFC_ULLRAM_BANK137_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK137_DATA_S 0 //***************************************************************************** // @@ -6651,9 +6651,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK138_DATA_W 32 -#define RFC_ULLRAM_BANK138_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK138_DATA_S 0 +#define RFC_ULLRAM_BANK138_DATA_W 32 +#define RFC_ULLRAM_BANK138_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK138_DATA_S 0 //***************************************************************************** // @@ -6663,9 +6663,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK139_DATA_W 32 -#define RFC_ULLRAM_BANK139_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK139_DATA_S 0 +#define RFC_ULLRAM_BANK139_DATA_W 32 +#define RFC_ULLRAM_BANK139_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK139_DATA_S 0 //***************************************************************************** // @@ -6675,9 +6675,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK140_DATA_W 32 -#define RFC_ULLRAM_BANK140_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK140_DATA_S 0 +#define RFC_ULLRAM_BANK140_DATA_W 32 +#define RFC_ULLRAM_BANK140_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK140_DATA_S 0 //***************************************************************************** // @@ -6687,9 +6687,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK141_DATA_W 32 -#define RFC_ULLRAM_BANK141_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK141_DATA_S 0 +#define RFC_ULLRAM_BANK141_DATA_W 32 +#define RFC_ULLRAM_BANK141_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK141_DATA_S 0 //***************************************************************************** // @@ -6699,9 +6699,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK142_DATA_W 32 -#define RFC_ULLRAM_BANK142_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK142_DATA_S 0 +#define RFC_ULLRAM_BANK142_DATA_W 32 +#define RFC_ULLRAM_BANK142_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK142_DATA_S 0 //***************************************************************************** // @@ -6711,9 +6711,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK143_DATA_W 32 -#define RFC_ULLRAM_BANK143_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK143_DATA_S 0 +#define RFC_ULLRAM_BANK143_DATA_W 32 +#define RFC_ULLRAM_BANK143_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK143_DATA_S 0 //***************************************************************************** // @@ -6723,9 +6723,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK144_DATA_W 32 -#define RFC_ULLRAM_BANK144_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK144_DATA_S 0 +#define RFC_ULLRAM_BANK144_DATA_W 32 +#define RFC_ULLRAM_BANK144_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK144_DATA_S 0 //***************************************************************************** // @@ -6735,9 +6735,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK145_DATA_W 32 -#define RFC_ULLRAM_BANK145_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK145_DATA_S 0 +#define RFC_ULLRAM_BANK145_DATA_W 32 +#define RFC_ULLRAM_BANK145_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK145_DATA_S 0 //***************************************************************************** // @@ -6747,9 +6747,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK146_DATA_W 32 -#define RFC_ULLRAM_BANK146_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK146_DATA_S 0 +#define RFC_ULLRAM_BANK146_DATA_W 32 +#define RFC_ULLRAM_BANK146_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK146_DATA_S 0 //***************************************************************************** // @@ -6759,9 +6759,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK147_DATA_W 32 -#define RFC_ULLRAM_BANK147_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK147_DATA_S 0 +#define RFC_ULLRAM_BANK147_DATA_W 32 +#define RFC_ULLRAM_BANK147_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK147_DATA_S 0 //***************************************************************************** // @@ -6771,9 +6771,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK148_DATA_W 32 -#define RFC_ULLRAM_BANK148_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK148_DATA_S 0 +#define RFC_ULLRAM_BANK148_DATA_W 32 +#define RFC_ULLRAM_BANK148_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK148_DATA_S 0 //***************************************************************************** // @@ -6783,9 +6783,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK149_DATA_W 32 -#define RFC_ULLRAM_BANK149_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK149_DATA_S 0 +#define RFC_ULLRAM_BANK149_DATA_W 32 +#define RFC_ULLRAM_BANK149_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK149_DATA_S 0 //***************************************************************************** // @@ -6795,9 +6795,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK150_DATA_W 32 -#define RFC_ULLRAM_BANK150_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK150_DATA_S 0 +#define RFC_ULLRAM_BANK150_DATA_W 32 +#define RFC_ULLRAM_BANK150_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK150_DATA_S 0 //***************************************************************************** // @@ -6807,9 +6807,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK151_DATA_W 32 -#define RFC_ULLRAM_BANK151_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK151_DATA_S 0 +#define RFC_ULLRAM_BANK151_DATA_W 32 +#define RFC_ULLRAM_BANK151_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK151_DATA_S 0 //***************************************************************************** // @@ -6819,9 +6819,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK152_DATA_W 32 -#define RFC_ULLRAM_BANK152_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK152_DATA_S 0 +#define RFC_ULLRAM_BANK152_DATA_W 32 +#define RFC_ULLRAM_BANK152_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK152_DATA_S 0 //***************************************************************************** // @@ -6831,9 +6831,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK153_DATA_W 32 -#define RFC_ULLRAM_BANK153_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK153_DATA_S 0 +#define RFC_ULLRAM_BANK153_DATA_W 32 +#define RFC_ULLRAM_BANK153_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK153_DATA_S 0 //***************************************************************************** // @@ -6843,9 +6843,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK154_DATA_W 32 -#define RFC_ULLRAM_BANK154_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK154_DATA_S 0 +#define RFC_ULLRAM_BANK154_DATA_W 32 +#define RFC_ULLRAM_BANK154_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK154_DATA_S 0 //***************************************************************************** // @@ -6855,9 +6855,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK155_DATA_W 32 -#define RFC_ULLRAM_BANK155_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK155_DATA_S 0 +#define RFC_ULLRAM_BANK155_DATA_W 32 +#define RFC_ULLRAM_BANK155_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK155_DATA_S 0 //***************************************************************************** // @@ -6867,9 +6867,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK156_DATA_W 32 -#define RFC_ULLRAM_BANK156_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK156_DATA_S 0 +#define RFC_ULLRAM_BANK156_DATA_W 32 +#define RFC_ULLRAM_BANK156_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK156_DATA_S 0 //***************************************************************************** // @@ -6879,9 +6879,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK157_DATA_W 32 -#define RFC_ULLRAM_BANK157_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK157_DATA_S 0 +#define RFC_ULLRAM_BANK157_DATA_W 32 +#define RFC_ULLRAM_BANK157_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK157_DATA_S 0 //***************************************************************************** // @@ -6891,9 +6891,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK158_DATA_W 32 -#define RFC_ULLRAM_BANK158_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK158_DATA_S 0 +#define RFC_ULLRAM_BANK158_DATA_W 32 +#define RFC_ULLRAM_BANK158_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK158_DATA_S 0 //***************************************************************************** // @@ -6903,9 +6903,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK159_DATA_W 32 -#define RFC_ULLRAM_BANK159_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK159_DATA_S 0 +#define RFC_ULLRAM_BANK159_DATA_W 32 +#define RFC_ULLRAM_BANK159_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK159_DATA_S 0 //***************************************************************************** // @@ -6915,9 +6915,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK160_DATA_W 32 -#define RFC_ULLRAM_BANK160_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK160_DATA_S 0 +#define RFC_ULLRAM_BANK160_DATA_W 32 +#define RFC_ULLRAM_BANK160_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK160_DATA_S 0 //***************************************************************************** // @@ -6927,9 +6927,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK161_DATA_W 32 -#define RFC_ULLRAM_BANK161_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK161_DATA_S 0 +#define RFC_ULLRAM_BANK161_DATA_W 32 +#define RFC_ULLRAM_BANK161_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK161_DATA_S 0 //***************************************************************************** // @@ -6939,9 +6939,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK162_DATA_W 32 -#define RFC_ULLRAM_BANK162_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK162_DATA_S 0 +#define RFC_ULLRAM_BANK162_DATA_W 32 +#define RFC_ULLRAM_BANK162_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK162_DATA_S 0 //***************************************************************************** // @@ -6951,9 +6951,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK163_DATA_W 32 -#define RFC_ULLRAM_BANK163_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK163_DATA_S 0 +#define RFC_ULLRAM_BANK163_DATA_W 32 +#define RFC_ULLRAM_BANK163_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK163_DATA_S 0 //***************************************************************************** // @@ -6963,9 +6963,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK164_DATA_W 32 -#define RFC_ULLRAM_BANK164_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK164_DATA_S 0 +#define RFC_ULLRAM_BANK164_DATA_W 32 +#define RFC_ULLRAM_BANK164_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK164_DATA_S 0 //***************************************************************************** // @@ -6975,9 +6975,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK165_DATA_W 32 -#define RFC_ULLRAM_BANK165_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK165_DATA_S 0 +#define RFC_ULLRAM_BANK165_DATA_W 32 +#define RFC_ULLRAM_BANK165_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK165_DATA_S 0 //***************************************************************************** // @@ -6987,9 +6987,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK166_DATA_W 32 -#define RFC_ULLRAM_BANK166_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK166_DATA_S 0 +#define RFC_ULLRAM_BANK166_DATA_W 32 +#define RFC_ULLRAM_BANK166_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK166_DATA_S 0 //***************************************************************************** // @@ -6999,9 +6999,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK167_DATA_W 32 -#define RFC_ULLRAM_BANK167_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK167_DATA_S 0 +#define RFC_ULLRAM_BANK167_DATA_W 32 +#define RFC_ULLRAM_BANK167_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK167_DATA_S 0 //***************************************************************************** // @@ -7011,9 +7011,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK168_DATA_W 32 -#define RFC_ULLRAM_BANK168_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK168_DATA_S 0 +#define RFC_ULLRAM_BANK168_DATA_W 32 +#define RFC_ULLRAM_BANK168_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK168_DATA_S 0 //***************************************************************************** // @@ -7023,9 +7023,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK169_DATA_W 32 -#define RFC_ULLRAM_BANK169_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK169_DATA_S 0 +#define RFC_ULLRAM_BANK169_DATA_W 32 +#define RFC_ULLRAM_BANK169_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK169_DATA_S 0 //***************************************************************************** // @@ -7035,9 +7035,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK170_DATA_W 32 -#define RFC_ULLRAM_BANK170_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK170_DATA_S 0 +#define RFC_ULLRAM_BANK170_DATA_W 32 +#define RFC_ULLRAM_BANK170_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK170_DATA_S 0 //***************************************************************************** // @@ -7047,9 +7047,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK171_DATA_W 32 -#define RFC_ULLRAM_BANK171_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK171_DATA_S 0 +#define RFC_ULLRAM_BANK171_DATA_W 32 +#define RFC_ULLRAM_BANK171_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK171_DATA_S 0 //***************************************************************************** // @@ -7059,9 +7059,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK172_DATA_W 32 -#define RFC_ULLRAM_BANK172_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK172_DATA_S 0 +#define RFC_ULLRAM_BANK172_DATA_W 32 +#define RFC_ULLRAM_BANK172_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK172_DATA_S 0 //***************************************************************************** // @@ -7071,9 +7071,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK173_DATA_W 32 -#define RFC_ULLRAM_BANK173_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK173_DATA_S 0 +#define RFC_ULLRAM_BANK173_DATA_W 32 +#define RFC_ULLRAM_BANK173_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK173_DATA_S 0 //***************************************************************************** // @@ -7083,9 +7083,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK174_DATA_W 32 -#define RFC_ULLRAM_BANK174_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK174_DATA_S 0 +#define RFC_ULLRAM_BANK174_DATA_W 32 +#define RFC_ULLRAM_BANK174_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK174_DATA_S 0 //***************************************************************************** // @@ -7095,9 +7095,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK175_DATA_W 32 -#define RFC_ULLRAM_BANK175_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK175_DATA_S 0 +#define RFC_ULLRAM_BANK175_DATA_W 32 +#define RFC_ULLRAM_BANK175_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK175_DATA_S 0 //***************************************************************************** // @@ -7107,9 +7107,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK176_DATA_W 32 -#define RFC_ULLRAM_BANK176_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK176_DATA_S 0 +#define RFC_ULLRAM_BANK176_DATA_W 32 +#define RFC_ULLRAM_BANK176_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK176_DATA_S 0 //***************************************************************************** // @@ -7119,9 +7119,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK177_DATA_W 32 -#define RFC_ULLRAM_BANK177_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK177_DATA_S 0 +#define RFC_ULLRAM_BANK177_DATA_W 32 +#define RFC_ULLRAM_BANK177_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK177_DATA_S 0 //***************************************************************************** // @@ -7131,9 +7131,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK178_DATA_W 32 -#define RFC_ULLRAM_BANK178_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK178_DATA_S 0 +#define RFC_ULLRAM_BANK178_DATA_W 32 +#define RFC_ULLRAM_BANK178_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK178_DATA_S 0 //***************************************************************************** // @@ -7143,9 +7143,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK179_DATA_W 32 -#define RFC_ULLRAM_BANK179_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK179_DATA_S 0 +#define RFC_ULLRAM_BANK179_DATA_W 32 +#define RFC_ULLRAM_BANK179_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK179_DATA_S 0 //***************************************************************************** // @@ -7155,9 +7155,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK180_DATA_W 32 -#define RFC_ULLRAM_BANK180_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK180_DATA_S 0 +#define RFC_ULLRAM_BANK180_DATA_W 32 +#define RFC_ULLRAM_BANK180_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK180_DATA_S 0 //***************************************************************************** // @@ -7167,9 +7167,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK181_DATA_W 32 -#define RFC_ULLRAM_BANK181_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK181_DATA_S 0 +#define RFC_ULLRAM_BANK181_DATA_W 32 +#define RFC_ULLRAM_BANK181_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK181_DATA_S 0 //***************************************************************************** // @@ -7179,9 +7179,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK182_DATA_W 32 -#define RFC_ULLRAM_BANK182_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK182_DATA_S 0 +#define RFC_ULLRAM_BANK182_DATA_W 32 +#define RFC_ULLRAM_BANK182_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK182_DATA_S 0 //***************************************************************************** // @@ -7191,9 +7191,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK183_DATA_W 32 -#define RFC_ULLRAM_BANK183_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK183_DATA_S 0 +#define RFC_ULLRAM_BANK183_DATA_W 32 +#define RFC_ULLRAM_BANK183_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK183_DATA_S 0 //***************************************************************************** // @@ -7203,9 +7203,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK184_DATA_W 32 -#define RFC_ULLRAM_BANK184_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK184_DATA_S 0 +#define RFC_ULLRAM_BANK184_DATA_W 32 +#define RFC_ULLRAM_BANK184_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK184_DATA_S 0 //***************************************************************************** // @@ -7215,9 +7215,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK185_DATA_W 32 -#define RFC_ULLRAM_BANK185_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK185_DATA_S 0 +#define RFC_ULLRAM_BANK185_DATA_W 32 +#define RFC_ULLRAM_BANK185_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK185_DATA_S 0 //***************************************************************************** // @@ -7227,9 +7227,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK186_DATA_W 32 -#define RFC_ULLRAM_BANK186_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK186_DATA_S 0 +#define RFC_ULLRAM_BANK186_DATA_W 32 +#define RFC_ULLRAM_BANK186_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK186_DATA_S 0 //***************************************************************************** // @@ -7239,9 +7239,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK187_DATA_W 32 -#define RFC_ULLRAM_BANK187_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK187_DATA_S 0 +#define RFC_ULLRAM_BANK187_DATA_W 32 +#define RFC_ULLRAM_BANK187_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK187_DATA_S 0 //***************************************************************************** // @@ -7251,9 +7251,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK188_DATA_W 32 -#define RFC_ULLRAM_BANK188_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK188_DATA_S 0 +#define RFC_ULLRAM_BANK188_DATA_W 32 +#define RFC_ULLRAM_BANK188_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK188_DATA_S 0 //***************************************************************************** // @@ -7263,9 +7263,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK189_DATA_W 32 -#define RFC_ULLRAM_BANK189_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK189_DATA_S 0 +#define RFC_ULLRAM_BANK189_DATA_W 32 +#define RFC_ULLRAM_BANK189_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK189_DATA_S 0 //***************************************************************************** // @@ -7275,9 +7275,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK190_DATA_W 32 -#define RFC_ULLRAM_BANK190_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK190_DATA_S 0 +#define RFC_ULLRAM_BANK190_DATA_W 32 +#define RFC_ULLRAM_BANK190_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK190_DATA_S 0 //***************************************************************************** // @@ -7287,9 +7287,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK191_DATA_W 32 -#define RFC_ULLRAM_BANK191_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK191_DATA_S 0 +#define RFC_ULLRAM_BANK191_DATA_W 32 +#define RFC_ULLRAM_BANK191_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK191_DATA_S 0 //***************************************************************************** // @@ -7299,9 +7299,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK192_DATA_W 32 -#define RFC_ULLRAM_BANK192_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK192_DATA_S 0 +#define RFC_ULLRAM_BANK192_DATA_W 32 +#define RFC_ULLRAM_BANK192_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK192_DATA_S 0 //***************************************************************************** // @@ -7311,9 +7311,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK193_DATA_W 32 -#define RFC_ULLRAM_BANK193_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK193_DATA_S 0 +#define RFC_ULLRAM_BANK193_DATA_W 32 +#define RFC_ULLRAM_BANK193_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK193_DATA_S 0 //***************************************************************************** // @@ -7323,9 +7323,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK194_DATA_W 32 -#define RFC_ULLRAM_BANK194_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK194_DATA_S 0 +#define RFC_ULLRAM_BANK194_DATA_W 32 +#define RFC_ULLRAM_BANK194_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK194_DATA_S 0 //***************************************************************************** // @@ -7335,9 +7335,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK195_DATA_W 32 -#define RFC_ULLRAM_BANK195_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK195_DATA_S 0 +#define RFC_ULLRAM_BANK195_DATA_W 32 +#define RFC_ULLRAM_BANK195_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK195_DATA_S 0 //***************************************************************************** // @@ -7347,9 +7347,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK196_DATA_W 32 -#define RFC_ULLRAM_BANK196_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK196_DATA_S 0 +#define RFC_ULLRAM_BANK196_DATA_W 32 +#define RFC_ULLRAM_BANK196_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK196_DATA_S 0 //***************************************************************************** // @@ -7359,9 +7359,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK197_DATA_W 32 -#define RFC_ULLRAM_BANK197_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK197_DATA_S 0 +#define RFC_ULLRAM_BANK197_DATA_W 32 +#define RFC_ULLRAM_BANK197_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK197_DATA_S 0 //***************************************************************************** // @@ -7371,9 +7371,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK198_DATA_W 32 -#define RFC_ULLRAM_BANK198_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK198_DATA_S 0 +#define RFC_ULLRAM_BANK198_DATA_W 32 +#define RFC_ULLRAM_BANK198_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK198_DATA_S 0 //***************************************************************************** // @@ -7383,9 +7383,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK199_DATA_W 32 -#define RFC_ULLRAM_BANK199_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK199_DATA_S 0 +#define RFC_ULLRAM_BANK199_DATA_W 32 +#define RFC_ULLRAM_BANK199_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK199_DATA_S 0 //***************************************************************************** // @@ -7395,9 +7395,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1100_DATA_W 32 -#define RFC_ULLRAM_BANK1100_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1100_DATA_S 0 +#define RFC_ULLRAM_BANK1100_DATA_W 32 +#define RFC_ULLRAM_BANK1100_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1100_DATA_S 0 //***************************************************************************** // @@ -7407,9 +7407,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1101_DATA_W 32 -#define RFC_ULLRAM_BANK1101_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1101_DATA_S 0 +#define RFC_ULLRAM_BANK1101_DATA_W 32 +#define RFC_ULLRAM_BANK1101_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1101_DATA_S 0 //***************************************************************************** // @@ -7419,9 +7419,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1102_DATA_W 32 -#define RFC_ULLRAM_BANK1102_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1102_DATA_S 0 +#define RFC_ULLRAM_BANK1102_DATA_W 32 +#define RFC_ULLRAM_BANK1102_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1102_DATA_S 0 //***************************************************************************** // @@ -7431,9 +7431,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1103_DATA_W 32 -#define RFC_ULLRAM_BANK1103_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1103_DATA_S 0 +#define RFC_ULLRAM_BANK1103_DATA_W 32 +#define RFC_ULLRAM_BANK1103_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1103_DATA_S 0 //***************************************************************************** // @@ -7443,9 +7443,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1104_DATA_W 32 -#define RFC_ULLRAM_BANK1104_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1104_DATA_S 0 +#define RFC_ULLRAM_BANK1104_DATA_W 32 +#define RFC_ULLRAM_BANK1104_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1104_DATA_S 0 //***************************************************************************** // @@ -7455,9 +7455,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1105_DATA_W 32 -#define RFC_ULLRAM_BANK1105_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1105_DATA_S 0 +#define RFC_ULLRAM_BANK1105_DATA_W 32 +#define RFC_ULLRAM_BANK1105_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1105_DATA_S 0 //***************************************************************************** // @@ -7467,9 +7467,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1106_DATA_W 32 -#define RFC_ULLRAM_BANK1106_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1106_DATA_S 0 +#define RFC_ULLRAM_BANK1106_DATA_W 32 +#define RFC_ULLRAM_BANK1106_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1106_DATA_S 0 //***************************************************************************** // @@ -7479,9 +7479,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1107_DATA_W 32 -#define RFC_ULLRAM_BANK1107_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1107_DATA_S 0 +#define RFC_ULLRAM_BANK1107_DATA_W 32 +#define RFC_ULLRAM_BANK1107_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1107_DATA_S 0 //***************************************************************************** // @@ -7491,9 +7491,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1108_DATA_W 32 -#define RFC_ULLRAM_BANK1108_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1108_DATA_S 0 +#define RFC_ULLRAM_BANK1108_DATA_W 32 +#define RFC_ULLRAM_BANK1108_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1108_DATA_S 0 //***************************************************************************** // @@ -7503,9 +7503,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1109_DATA_W 32 -#define RFC_ULLRAM_BANK1109_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1109_DATA_S 0 +#define RFC_ULLRAM_BANK1109_DATA_W 32 +#define RFC_ULLRAM_BANK1109_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1109_DATA_S 0 //***************************************************************************** // @@ -7515,9 +7515,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1110_DATA_W 32 -#define RFC_ULLRAM_BANK1110_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1110_DATA_S 0 +#define RFC_ULLRAM_BANK1110_DATA_W 32 +#define RFC_ULLRAM_BANK1110_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1110_DATA_S 0 //***************************************************************************** // @@ -7527,9 +7527,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1111_DATA_W 32 -#define RFC_ULLRAM_BANK1111_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1111_DATA_S 0 +#define RFC_ULLRAM_BANK1111_DATA_W 32 +#define RFC_ULLRAM_BANK1111_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1111_DATA_S 0 //***************************************************************************** // @@ -7539,9 +7539,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1112_DATA_W 32 -#define RFC_ULLRAM_BANK1112_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1112_DATA_S 0 +#define RFC_ULLRAM_BANK1112_DATA_W 32 +#define RFC_ULLRAM_BANK1112_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1112_DATA_S 0 //***************************************************************************** // @@ -7551,9 +7551,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1113_DATA_W 32 -#define RFC_ULLRAM_BANK1113_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1113_DATA_S 0 +#define RFC_ULLRAM_BANK1113_DATA_W 32 +#define RFC_ULLRAM_BANK1113_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1113_DATA_S 0 //***************************************************************************** // @@ -7563,9 +7563,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1114_DATA_W 32 -#define RFC_ULLRAM_BANK1114_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1114_DATA_S 0 +#define RFC_ULLRAM_BANK1114_DATA_W 32 +#define RFC_ULLRAM_BANK1114_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1114_DATA_S 0 //***************************************************************************** // @@ -7575,9 +7575,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1115_DATA_W 32 -#define RFC_ULLRAM_BANK1115_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1115_DATA_S 0 +#define RFC_ULLRAM_BANK1115_DATA_W 32 +#define RFC_ULLRAM_BANK1115_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1115_DATA_S 0 //***************************************************************************** // @@ -7587,9 +7587,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1116_DATA_W 32 -#define RFC_ULLRAM_BANK1116_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1116_DATA_S 0 +#define RFC_ULLRAM_BANK1116_DATA_W 32 +#define RFC_ULLRAM_BANK1116_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1116_DATA_S 0 //***************************************************************************** // @@ -7599,9 +7599,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1117_DATA_W 32 -#define RFC_ULLRAM_BANK1117_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1117_DATA_S 0 +#define RFC_ULLRAM_BANK1117_DATA_W 32 +#define RFC_ULLRAM_BANK1117_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1117_DATA_S 0 //***************************************************************************** // @@ -7611,9 +7611,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1118_DATA_W 32 -#define RFC_ULLRAM_BANK1118_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1118_DATA_S 0 +#define RFC_ULLRAM_BANK1118_DATA_W 32 +#define RFC_ULLRAM_BANK1118_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1118_DATA_S 0 //***************************************************************************** // @@ -7623,9 +7623,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1119_DATA_W 32 -#define RFC_ULLRAM_BANK1119_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1119_DATA_S 0 +#define RFC_ULLRAM_BANK1119_DATA_W 32 +#define RFC_ULLRAM_BANK1119_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1119_DATA_S 0 //***************************************************************************** // @@ -7635,9 +7635,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1120_DATA_W 32 -#define RFC_ULLRAM_BANK1120_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1120_DATA_S 0 +#define RFC_ULLRAM_BANK1120_DATA_W 32 +#define RFC_ULLRAM_BANK1120_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1120_DATA_S 0 //***************************************************************************** // @@ -7647,9 +7647,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1121_DATA_W 32 -#define RFC_ULLRAM_BANK1121_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1121_DATA_S 0 +#define RFC_ULLRAM_BANK1121_DATA_W 32 +#define RFC_ULLRAM_BANK1121_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1121_DATA_S 0 //***************************************************************************** // @@ -7659,9 +7659,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1122_DATA_W 32 -#define RFC_ULLRAM_BANK1122_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1122_DATA_S 0 +#define RFC_ULLRAM_BANK1122_DATA_W 32 +#define RFC_ULLRAM_BANK1122_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1122_DATA_S 0 //***************************************************************************** // @@ -7671,9 +7671,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1123_DATA_W 32 -#define RFC_ULLRAM_BANK1123_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1123_DATA_S 0 +#define RFC_ULLRAM_BANK1123_DATA_W 32 +#define RFC_ULLRAM_BANK1123_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1123_DATA_S 0 //***************************************************************************** // @@ -7683,9 +7683,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1124_DATA_W 32 -#define RFC_ULLRAM_BANK1124_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1124_DATA_S 0 +#define RFC_ULLRAM_BANK1124_DATA_W 32 +#define RFC_ULLRAM_BANK1124_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1124_DATA_S 0 //***************************************************************************** // @@ -7695,9 +7695,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1125_DATA_W 32 -#define RFC_ULLRAM_BANK1125_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1125_DATA_S 0 +#define RFC_ULLRAM_BANK1125_DATA_W 32 +#define RFC_ULLRAM_BANK1125_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1125_DATA_S 0 //***************************************************************************** // @@ -7707,9 +7707,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1126_DATA_W 32 -#define RFC_ULLRAM_BANK1126_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1126_DATA_S 0 +#define RFC_ULLRAM_BANK1126_DATA_W 32 +#define RFC_ULLRAM_BANK1126_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1126_DATA_S 0 //***************************************************************************** // @@ -7719,9 +7719,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1127_DATA_W 32 -#define RFC_ULLRAM_BANK1127_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1127_DATA_S 0 +#define RFC_ULLRAM_BANK1127_DATA_W 32 +#define RFC_ULLRAM_BANK1127_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1127_DATA_S 0 //***************************************************************************** // @@ -7731,9 +7731,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1128_DATA_W 32 -#define RFC_ULLRAM_BANK1128_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1128_DATA_S 0 +#define RFC_ULLRAM_BANK1128_DATA_W 32 +#define RFC_ULLRAM_BANK1128_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1128_DATA_S 0 //***************************************************************************** // @@ -7743,9 +7743,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1129_DATA_W 32 -#define RFC_ULLRAM_BANK1129_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1129_DATA_S 0 +#define RFC_ULLRAM_BANK1129_DATA_W 32 +#define RFC_ULLRAM_BANK1129_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1129_DATA_S 0 //***************************************************************************** // @@ -7755,9 +7755,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1130_DATA_W 32 -#define RFC_ULLRAM_BANK1130_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1130_DATA_S 0 +#define RFC_ULLRAM_BANK1130_DATA_W 32 +#define RFC_ULLRAM_BANK1130_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1130_DATA_S 0 //***************************************************************************** // @@ -7767,9 +7767,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1131_DATA_W 32 -#define RFC_ULLRAM_BANK1131_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1131_DATA_S 0 +#define RFC_ULLRAM_BANK1131_DATA_W 32 +#define RFC_ULLRAM_BANK1131_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1131_DATA_S 0 //***************************************************************************** // @@ -7779,9 +7779,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1132_DATA_W 32 -#define RFC_ULLRAM_BANK1132_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1132_DATA_S 0 +#define RFC_ULLRAM_BANK1132_DATA_W 32 +#define RFC_ULLRAM_BANK1132_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1132_DATA_S 0 //***************************************************************************** // @@ -7791,9 +7791,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1133_DATA_W 32 -#define RFC_ULLRAM_BANK1133_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1133_DATA_S 0 +#define RFC_ULLRAM_BANK1133_DATA_W 32 +#define RFC_ULLRAM_BANK1133_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1133_DATA_S 0 //***************************************************************************** // @@ -7803,9 +7803,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1134_DATA_W 32 -#define RFC_ULLRAM_BANK1134_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1134_DATA_S 0 +#define RFC_ULLRAM_BANK1134_DATA_W 32 +#define RFC_ULLRAM_BANK1134_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1134_DATA_S 0 //***************************************************************************** // @@ -7815,9 +7815,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1135_DATA_W 32 -#define RFC_ULLRAM_BANK1135_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1135_DATA_S 0 +#define RFC_ULLRAM_BANK1135_DATA_W 32 +#define RFC_ULLRAM_BANK1135_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1135_DATA_S 0 //***************************************************************************** // @@ -7827,9 +7827,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1136_DATA_W 32 -#define RFC_ULLRAM_BANK1136_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1136_DATA_S 0 +#define RFC_ULLRAM_BANK1136_DATA_W 32 +#define RFC_ULLRAM_BANK1136_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1136_DATA_S 0 //***************************************************************************** // @@ -7839,9 +7839,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1137_DATA_W 32 -#define RFC_ULLRAM_BANK1137_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1137_DATA_S 0 +#define RFC_ULLRAM_BANK1137_DATA_W 32 +#define RFC_ULLRAM_BANK1137_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1137_DATA_S 0 //***************************************************************************** // @@ -7851,9 +7851,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1138_DATA_W 32 -#define RFC_ULLRAM_BANK1138_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1138_DATA_S 0 +#define RFC_ULLRAM_BANK1138_DATA_W 32 +#define RFC_ULLRAM_BANK1138_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1138_DATA_S 0 //***************************************************************************** // @@ -7863,9 +7863,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1139_DATA_W 32 -#define RFC_ULLRAM_BANK1139_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1139_DATA_S 0 +#define RFC_ULLRAM_BANK1139_DATA_W 32 +#define RFC_ULLRAM_BANK1139_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1139_DATA_S 0 //***************************************************************************** // @@ -7875,9 +7875,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1140_DATA_W 32 -#define RFC_ULLRAM_BANK1140_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1140_DATA_S 0 +#define RFC_ULLRAM_BANK1140_DATA_W 32 +#define RFC_ULLRAM_BANK1140_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1140_DATA_S 0 //***************************************************************************** // @@ -7887,9 +7887,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1141_DATA_W 32 -#define RFC_ULLRAM_BANK1141_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1141_DATA_S 0 +#define RFC_ULLRAM_BANK1141_DATA_W 32 +#define RFC_ULLRAM_BANK1141_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1141_DATA_S 0 //***************************************************************************** // @@ -7899,9 +7899,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1142_DATA_W 32 -#define RFC_ULLRAM_BANK1142_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1142_DATA_S 0 +#define RFC_ULLRAM_BANK1142_DATA_W 32 +#define RFC_ULLRAM_BANK1142_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1142_DATA_S 0 //***************************************************************************** // @@ -7911,9 +7911,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1143_DATA_W 32 -#define RFC_ULLRAM_BANK1143_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1143_DATA_S 0 +#define RFC_ULLRAM_BANK1143_DATA_W 32 +#define RFC_ULLRAM_BANK1143_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1143_DATA_S 0 //***************************************************************************** // @@ -7923,9 +7923,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1144_DATA_W 32 -#define RFC_ULLRAM_BANK1144_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1144_DATA_S 0 +#define RFC_ULLRAM_BANK1144_DATA_W 32 +#define RFC_ULLRAM_BANK1144_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1144_DATA_S 0 //***************************************************************************** // @@ -7935,9 +7935,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1145_DATA_W 32 -#define RFC_ULLRAM_BANK1145_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1145_DATA_S 0 +#define RFC_ULLRAM_BANK1145_DATA_W 32 +#define RFC_ULLRAM_BANK1145_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1145_DATA_S 0 //***************************************************************************** // @@ -7947,9 +7947,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1146_DATA_W 32 -#define RFC_ULLRAM_BANK1146_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1146_DATA_S 0 +#define RFC_ULLRAM_BANK1146_DATA_W 32 +#define RFC_ULLRAM_BANK1146_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1146_DATA_S 0 //***************************************************************************** // @@ -7959,9 +7959,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1147_DATA_W 32 -#define RFC_ULLRAM_BANK1147_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1147_DATA_S 0 +#define RFC_ULLRAM_BANK1147_DATA_W 32 +#define RFC_ULLRAM_BANK1147_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1147_DATA_S 0 //***************************************************************************** // @@ -7971,9 +7971,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1148_DATA_W 32 -#define RFC_ULLRAM_BANK1148_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1148_DATA_S 0 +#define RFC_ULLRAM_BANK1148_DATA_W 32 +#define RFC_ULLRAM_BANK1148_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1148_DATA_S 0 //***************************************************************************** // @@ -7983,9 +7983,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1149_DATA_W 32 -#define RFC_ULLRAM_BANK1149_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1149_DATA_S 0 +#define RFC_ULLRAM_BANK1149_DATA_W 32 +#define RFC_ULLRAM_BANK1149_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1149_DATA_S 0 //***************************************************************************** // @@ -7995,9 +7995,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1150_DATA_W 32 -#define RFC_ULLRAM_BANK1150_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1150_DATA_S 0 +#define RFC_ULLRAM_BANK1150_DATA_W 32 +#define RFC_ULLRAM_BANK1150_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1150_DATA_S 0 //***************************************************************************** // @@ -8007,9 +8007,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1151_DATA_W 32 -#define RFC_ULLRAM_BANK1151_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1151_DATA_S 0 +#define RFC_ULLRAM_BANK1151_DATA_W 32 +#define RFC_ULLRAM_BANK1151_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1151_DATA_S 0 //***************************************************************************** // @@ -8019,9 +8019,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1152_DATA_W 32 -#define RFC_ULLRAM_BANK1152_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1152_DATA_S 0 +#define RFC_ULLRAM_BANK1152_DATA_W 32 +#define RFC_ULLRAM_BANK1152_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1152_DATA_S 0 //***************************************************************************** // @@ -8031,9 +8031,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1153_DATA_W 32 -#define RFC_ULLRAM_BANK1153_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1153_DATA_S 0 +#define RFC_ULLRAM_BANK1153_DATA_W 32 +#define RFC_ULLRAM_BANK1153_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1153_DATA_S 0 //***************************************************************************** // @@ -8043,9 +8043,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1154_DATA_W 32 -#define RFC_ULLRAM_BANK1154_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1154_DATA_S 0 +#define RFC_ULLRAM_BANK1154_DATA_W 32 +#define RFC_ULLRAM_BANK1154_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1154_DATA_S 0 //***************************************************************************** // @@ -8055,9 +8055,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1155_DATA_W 32 -#define RFC_ULLRAM_BANK1155_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1155_DATA_S 0 +#define RFC_ULLRAM_BANK1155_DATA_W 32 +#define RFC_ULLRAM_BANK1155_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1155_DATA_S 0 //***************************************************************************** // @@ -8067,9 +8067,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1156_DATA_W 32 -#define RFC_ULLRAM_BANK1156_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1156_DATA_S 0 +#define RFC_ULLRAM_BANK1156_DATA_W 32 +#define RFC_ULLRAM_BANK1156_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1156_DATA_S 0 //***************************************************************************** // @@ -8079,9 +8079,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1157_DATA_W 32 -#define RFC_ULLRAM_BANK1157_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1157_DATA_S 0 +#define RFC_ULLRAM_BANK1157_DATA_W 32 +#define RFC_ULLRAM_BANK1157_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1157_DATA_S 0 //***************************************************************************** // @@ -8091,9 +8091,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1158_DATA_W 32 -#define RFC_ULLRAM_BANK1158_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1158_DATA_S 0 +#define RFC_ULLRAM_BANK1158_DATA_W 32 +#define RFC_ULLRAM_BANK1158_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1158_DATA_S 0 //***************************************************************************** // @@ -8103,9 +8103,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1159_DATA_W 32 -#define RFC_ULLRAM_BANK1159_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1159_DATA_S 0 +#define RFC_ULLRAM_BANK1159_DATA_W 32 +#define RFC_ULLRAM_BANK1159_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1159_DATA_S 0 //***************************************************************************** // @@ -8115,9 +8115,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1160_DATA_W 32 -#define RFC_ULLRAM_BANK1160_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1160_DATA_S 0 +#define RFC_ULLRAM_BANK1160_DATA_W 32 +#define RFC_ULLRAM_BANK1160_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1160_DATA_S 0 //***************************************************************************** // @@ -8127,9 +8127,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1161_DATA_W 32 -#define RFC_ULLRAM_BANK1161_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1161_DATA_S 0 +#define RFC_ULLRAM_BANK1161_DATA_W 32 +#define RFC_ULLRAM_BANK1161_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1161_DATA_S 0 //***************************************************************************** // @@ -8139,9 +8139,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1162_DATA_W 32 -#define RFC_ULLRAM_BANK1162_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1162_DATA_S 0 +#define RFC_ULLRAM_BANK1162_DATA_W 32 +#define RFC_ULLRAM_BANK1162_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1162_DATA_S 0 //***************************************************************************** // @@ -8151,9 +8151,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1163_DATA_W 32 -#define RFC_ULLRAM_BANK1163_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1163_DATA_S 0 +#define RFC_ULLRAM_BANK1163_DATA_W 32 +#define RFC_ULLRAM_BANK1163_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1163_DATA_S 0 //***************************************************************************** // @@ -8163,9 +8163,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1164_DATA_W 32 -#define RFC_ULLRAM_BANK1164_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1164_DATA_S 0 +#define RFC_ULLRAM_BANK1164_DATA_W 32 +#define RFC_ULLRAM_BANK1164_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1164_DATA_S 0 //***************************************************************************** // @@ -8175,9 +8175,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1165_DATA_W 32 -#define RFC_ULLRAM_BANK1165_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1165_DATA_S 0 +#define RFC_ULLRAM_BANK1165_DATA_W 32 +#define RFC_ULLRAM_BANK1165_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1165_DATA_S 0 //***************************************************************************** // @@ -8187,9 +8187,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1166_DATA_W 32 -#define RFC_ULLRAM_BANK1166_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1166_DATA_S 0 +#define RFC_ULLRAM_BANK1166_DATA_W 32 +#define RFC_ULLRAM_BANK1166_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1166_DATA_S 0 //***************************************************************************** // @@ -8199,9 +8199,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1167_DATA_W 32 -#define RFC_ULLRAM_BANK1167_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1167_DATA_S 0 +#define RFC_ULLRAM_BANK1167_DATA_W 32 +#define RFC_ULLRAM_BANK1167_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1167_DATA_S 0 //***************************************************************************** // @@ -8211,9 +8211,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1168_DATA_W 32 -#define RFC_ULLRAM_BANK1168_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1168_DATA_S 0 +#define RFC_ULLRAM_BANK1168_DATA_W 32 +#define RFC_ULLRAM_BANK1168_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1168_DATA_S 0 //***************************************************************************** // @@ -8223,9 +8223,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1169_DATA_W 32 -#define RFC_ULLRAM_BANK1169_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1169_DATA_S 0 +#define RFC_ULLRAM_BANK1169_DATA_W 32 +#define RFC_ULLRAM_BANK1169_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1169_DATA_S 0 //***************************************************************************** // @@ -8235,9 +8235,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1170_DATA_W 32 -#define RFC_ULLRAM_BANK1170_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1170_DATA_S 0 +#define RFC_ULLRAM_BANK1170_DATA_W 32 +#define RFC_ULLRAM_BANK1170_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1170_DATA_S 0 //***************************************************************************** // @@ -8247,9 +8247,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1171_DATA_W 32 -#define RFC_ULLRAM_BANK1171_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1171_DATA_S 0 +#define RFC_ULLRAM_BANK1171_DATA_W 32 +#define RFC_ULLRAM_BANK1171_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1171_DATA_S 0 //***************************************************************************** // @@ -8259,9 +8259,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1172_DATA_W 32 -#define RFC_ULLRAM_BANK1172_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1172_DATA_S 0 +#define RFC_ULLRAM_BANK1172_DATA_W 32 +#define RFC_ULLRAM_BANK1172_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1172_DATA_S 0 //***************************************************************************** // @@ -8271,9 +8271,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1173_DATA_W 32 -#define RFC_ULLRAM_BANK1173_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1173_DATA_S 0 +#define RFC_ULLRAM_BANK1173_DATA_W 32 +#define RFC_ULLRAM_BANK1173_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1173_DATA_S 0 //***************************************************************************** // @@ -8283,9 +8283,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1174_DATA_W 32 -#define RFC_ULLRAM_BANK1174_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1174_DATA_S 0 +#define RFC_ULLRAM_BANK1174_DATA_W 32 +#define RFC_ULLRAM_BANK1174_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1174_DATA_S 0 //***************************************************************************** // @@ -8295,9 +8295,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1175_DATA_W 32 -#define RFC_ULLRAM_BANK1175_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1175_DATA_S 0 +#define RFC_ULLRAM_BANK1175_DATA_W 32 +#define RFC_ULLRAM_BANK1175_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1175_DATA_S 0 //***************************************************************************** // @@ -8307,9 +8307,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1176_DATA_W 32 -#define RFC_ULLRAM_BANK1176_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1176_DATA_S 0 +#define RFC_ULLRAM_BANK1176_DATA_W 32 +#define RFC_ULLRAM_BANK1176_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1176_DATA_S 0 //***************************************************************************** // @@ -8319,9 +8319,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1177_DATA_W 32 -#define RFC_ULLRAM_BANK1177_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1177_DATA_S 0 +#define RFC_ULLRAM_BANK1177_DATA_W 32 +#define RFC_ULLRAM_BANK1177_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1177_DATA_S 0 //***************************************************************************** // @@ -8331,9 +8331,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1178_DATA_W 32 -#define RFC_ULLRAM_BANK1178_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1178_DATA_S 0 +#define RFC_ULLRAM_BANK1178_DATA_W 32 +#define RFC_ULLRAM_BANK1178_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1178_DATA_S 0 //***************************************************************************** // @@ -8343,9 +8343,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1179_DATA_W 32 -#define RFC_ULLRAM_BANK1179_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1179_DATA_S 0 +#define RFC_ULLRAM_BANK1179_DATA_W 32 +#define RFC_ULLRAM_BANK1179_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1179_DATA_S 0 //***************************************************************************** // @@ -8355,9 +8355,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1180_DATA_W 32 -#define RFC_ULLRAM_BANK1180_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1180_DATA_S 0 +#define RFC_ULLRAM_BANK1180_DATA_W 32 +#define RFC_ULLRAM_BANK1180_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1180_DATA_S 0 //***************************************************************************** // @@ -8367,9 +8367,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1181_DATA_W 32 -#define RFC_ULLRAM_BANK1181_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1181_DATA_S 0 +#define RFC_ULLRAM_BANK1181_DATA_W 32 +#define RFC_ULLRAM_BANK1181_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1181_DATA_S 0 //***************************************************************************** // @@ -8379,9 +8379,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1182_DATA_W 32 -#define RFC_ULLRAM_BANK1182_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1182_DATA_S 0 +#define RFC_ULLRAM_BANK1182_DATA_W 32 +#define RFC_ULLRAM_BANK1182_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1182_DATA_S 0 //***************************************************************************** // @@ -8391,9 +8391,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1183_DATA_W 32 -#define RFC_ULLRAM_BANK1183_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1183_DATA_S 0 +#define RFC_ULLRAM_BANK1183_DATA_W 32 +#define RFC_ULLRAM_BANK1183_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1183_DATA_S 0 //***************************************************************************** // @@ -8403,9 +8403,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1184_DATA_W 32 -#define RFC_ULLRAM_BANK1184_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1184_DATA_S 0 +#define RFC_ULLRAM_BANK1184_DATA_W 32 +#define RFC_ULLRAM_BANK1184_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1184_DATA_S 0 //***************************************************************************** // @@ -8415,9 +8415,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1185_DATA_W 32 -#define RFC_ULLRAM_BANK1185_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1185_DATA_S 0 +#define RFC_ULLRAM_BANK1185_DATA_W 32 +#define RFC_ULLRAM_BANK1185_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1185_DATA_S 0 //***************************************************************************** // @@ -8427,9 +8427,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1186_DATA_W 32 -#define RFC_ULLRAM_BANK1186_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1186_DATA_S 0 +#define RFC_ULLRAM_BANK1186_DATA_W 32 +#define RFC_ULLRAM_BANK1186_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1186_DATA_S 0 //***************************************************************************** // @@ -8439,9 +8439,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1187_DATA_W 32 -#define RFC_ULLRAM_BANK1187_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1187_DATA_S 0 +#define RFC_ULLRAM_BANK1187_DATA_W 32 +#define RFC_ULLRAM_BANK1187_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1187_DATA_S 0 //***************************************************************************** // @@ -8451,9 +8451,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1188_DATA_W 32 -#define RFC_ULLRAM_BANK1188_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1188_DATA_S 0 +#define RFC_ULLRAM_BANK1188_DATA_W 32 +#define RFC_ULLRAM_BANK1188_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1188_DATA_S 0 //***************************************************************************** // @@ -8463,9 +8463,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1189_DATA_W 32 -#define RFC_ULLRAM_BANK1189_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1189_DATA_S 0 +#define RFC_ULLRAM_BANK1189_DATA_W 32 +#define RFC_ULLRAM_BANK1189_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1189_DATA_S 0 //***************************************************************************** // @@ -8475,9 +8475,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1190_DATA_W 32 -#define RFC_ULLRAM_BANK1190_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1190_DATA_S 0 +#define RFC_ULLRAM_BANK1190_DATA_W 32 +#define RFC_ULLRAM_BANK1190_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1190_DATA_S 0 //***************************************************************************** // @@ -8487,9 +8487,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1191_DATA_W 32 -#define RFC_ULLRAM_BANK1191_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1191_DATA_S 0 +#define RFC_ULLRAM_BANK1191_DATA_W 32 +#define RFC_ULLRAM_BANK1191_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1191_DATA_S 0 //***************************************************************************** // @@ -8499,9 +8499,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1192_DATA_W 32 -#define RFC_ULLRAM_BANK1192_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1192_DATA_S 0 +#define RFC_ULLRAM_BANK1192_DATA_W 32 +#define RFC_ULLRAM_BANK1192_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1192_DATA_S 0 //***************************************************************************** // @@ -8511,9 +8511,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1193_DATA_W 32 -#define RFC_ULLRAM_BANK1193_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1193_DATA_S 0 +#define RFC_ULLRAM_BANK1193_DATA_W 32 +#define RFC_ULLRAM_BANK1193_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1193_DATA_S 0 //***************************************************************************** // @@ -8523,9 +8523,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1194_DATA_W 32 -#define RFC_ULLRAM_BANK1194_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1194_DATA_S 0 +#define RFC_ULLRAM_BANK1194_DATA_W 32 +#define RFC_ULLRAM_BANK1194_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1194_DATA_S 0 //***************************************************************************** // @@ -8535,9 +8535,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1195_DATA_W 32 -#define RFC_ULLRAM_BANK1195_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1195_DATA_S 0 +#define RFC_ULLRAM_BANK1195_DATA_W 32 +#define RFC_ULLRAM_BANK1195_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1195_DATA_S 0 //***************************************************************************** // @@ -8547,9 +8547,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1196_DATA_W 32 -#define RFC_ULLRAM_BANK1196_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1196_DATA_S 0 +#define RFC_ULLRAM_BANK1196_DATA_W 32 +#define RFC_ULLRAM_BANK1196_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1196_DATA_S 0 //***************************************************************************** // @@ -8559,9 +8559,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1197_DATA_W 32 -#define RFC_ULLRAM_BANK1197_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1197_DATA_S 0 +#define RFC_ULLRAM_BANK1197_DATA_W 32 +#define RFC_ULLRAM_BANK1197_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1197_DATA_S 0 //***************************************************************************** // @@ -8571,9 +8571,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1198_DATA_W 32 -#define RFC_ULLRAM_BANK1198_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1198_DATA_S 0 +#define RFC_ULLRAM_BANK1198_DATA_W 32 +#define RFC_ULLRAM_BANK1198_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1198_DATA_S 0 //***************************************************************************** // @@ -8583,9 +8583,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1199_DATA_W 32 -#define RFC_ULLRAM_BANK1199_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1199_DATA_S 0 +#define RFC_ULLRAM_BANK1199_DATA_W 32 +#define RFC_ULLRAM_BANK1199_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1199_DATA_S 0 //***************************************************************************** // @@ -8595,9 +8595,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1200_DATA_W 32 -#define RFC_ULLRAM_BANK1200_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1200_DATA_S 0 +#define RFC_ULLRAM_BANK1200_DATA_W 32 +#define RFC_ULLRAM_BANK1200_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1200_DATA_S 0 //***************************************************************************** // @@ -8607,9 +8607,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1201_DATA_W 32 -#define RFC_ULLRAM_BANK1201_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1201_DATA_S 0 +#define RFC_ULLRAM_BANK1201_DATA_W 32 +#define RFC_ULLRAM_BANK1201_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1201_DATA_S 0 //***************************************************************************** // @@ -8619,9 +8619,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1202_DATA_W 32 -#define RFC_ULLRAM_BANK1202_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1202_DATA_S 0 +#define RFC_ULLRAM_BANK1202_DATA_W 32 +#define RFC_ULLRAM_BANK1202_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1202_DATA_S 0 //***************************************************************************** // @@ -8631,9 +8631,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1203_DATA_W 32 -#define RFC_ULLRAM_BANK1203_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1203_DATA_S 0 +#define RFC_ULLRAM_BANK1203_DATA_W 32 +#define RFC_ULLRAM_BANK1203_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1203_DATA_S 0 //***************************************************************************** // @@ -8643,9 +8643,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1204_DATA_W 32 -#define RFC_ULLRAM_BANK1204_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1204_DATA_S 0 +#define RFC_ULLRAM_BANK1204_DATA_W 32 +#define RFC_ULLRAM_BANK1204_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1204_DATA_S 0 //***************************************************************************** // @@ -8655,9 +8655,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1205_DATA_W 32 -#define RFC_ULLRAM_BANK1205_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1205_DATA_S 0 +#define RFC_ULLRAM_BANK1205_DATA_W 32 +#define RFC_ULLRAM_BANK1205_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1205_DATA_S 0 //***************************************************************************** // @@ -8667,9 +8667,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1206_DATA_W 32 -#define RFC_ULLRAM_BANK1206_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1206_DATA_S 0 +#define RFC_ULLRAM_BANK1206_DATA_W 32 +#define RFC_ULLRAM_BANK1206_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1206_DATA_S 0 //***************************************************************************** // @@ -8679,9 +8679,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1207_DATA_W 32 -#define RFC_ULLRAM_BANK1207_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1207_DATA_S 0 +#define RFC_ULLRAM_BANK1207_DATA_W 32 +#define RFC_ULLRAM_BANK1207_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1207_DATA_S 0 //***************************************************************************** // @@ -8691,9 +8691,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1208_DATA_W 32 -#define RFC_ULLRAM_BANK1208_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1208_DATA_S 0 +#define RFC_ULLRAM_BANK1208_DATA_W 32 +#define RFC_ULLRAM_BANK1208_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1208_DATA_S 0 //***************************************************************************** // @@ -8703,9 +8703,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1209_DATA_W 32 -#define RFC_ULLRAM_BANK1209_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1209_DATA_S 0 +#define RFC_ULLRAM_BANK1209_DATA_W 32 +#define RFC_ULLRAM_BANK1209_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1209_DATA_S 0 //***************************************************************************** // @@ -8715,9 +8715,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1210_DATA_W 32 -#define RFC_ULLRAM_BANK1210_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1210_DATA_S 0 +#define RFC_ULLRAM_BANK1210_DATA_W 32 +#define RFC_ULLRAM_BANK1210_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1210_DATA_S 0 //***************************************************************************** // @@ -8727,9 +8727,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1211_DATA_W 32 -#define RFC_ULLRAM_BANK1211_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1211_DATA_S 0 +#define RFC_ULLRAM_BANK1211_DATA_W 32 +#define RFC_ULLRAM_BANK1211_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1211_DATA_S 0 //***************************************************************************** // @@ -8739,9 +8739,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1212_DATA_W 32 -#define RFC_ULLRAM_BANK1212_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1212_DATA_S 0 +#define RFC_ULLRAM_BANK1212_DATA_W 32 +#define RFC_ULLRAM_BANK1212_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1212_DATA_S 0 //***************************************************************************** // @@ -8751,9 +8751,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1213_DATA_W 32 -#define RFC_ULLRAM_BANK1213_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1213_DATA_S 0 +#define RFC_ULLRAM_BANK1213_DATA_W 32 +#define RFC_ULLRAM_BANK1213_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1213_DATA_S 0 //***************************************************************************** // @@ -8763,9 +8763,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1214_DATA_W 32 -#define RFC_ULLRAM_BANK1214_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1214_DATA_S 0 +#define RFC_ULLRAM_BANK1214_DATA_W 32 +#define RFC_ULLRAM_BANK1214_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1214_DATA_S 0 //***************************************************************************** // @@ -8775,9 +8775,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1215_DATA_W 32 -#define RFC_ULLRAM_BANK1215_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1215_DATA_S 0 +#define RFC_ULLRAM_BANK1215_DATA_W 32 +#define RFC_ULLRAM_BANK1215_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1215_DATA_S 0 //***************************************************************************** // @@ -8787,9 +8787,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1216_DATA_W 32 -#define RFC_ULLRAM_BANK1216_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1216_DATA_S 0 +#define RFC_ULLRAM_BANK1216_DATA_W 32 +#define RFC_ULLRAM_BANK1216_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1216_DATA_S 0 //***************************************************************************** // @@ -8799,9 +8799,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1217_DATA_W 32 -#define RFC_ULLRAM_BANK1217_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1217_DATA_S 0 +#define RFC_ULLRAM_BANK1217_DATA_W 32 +#define RFC_ULLRAM_BANK1217_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1217_DATA_S 0 //***************************************************************************** // @@ -8811,9 +8811,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1218_DATA_W 32 -#define RFC_ULLRAM_BANK1218_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1218_DATA_S 0 +#define RFC_ULLRAM_BANK1218_DATA_W 32 +#define RFC_ULLRAM_BANK1218_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1218_DATA_S 0 //***************************************************************************** // @@ -8823,9 +8823,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1219_DATA_W 32 -#define RFC_ULLRAM_BANK1219_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1219_DATA_S 0 +#define RFC_ULLRAM_BANK1219_DATA_W 32 +#define RFC_ULLRAM_BANK1219_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1219_DATA_S 0 //***************************************************************************** // @@ -8835,9 +8835,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1220_DATA_W 32 -#define RFC_ULLRAM_BANK1220_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1220_DATA_S 0 +#define RFC_ULLRAM_BANK1220_DATA_W 32 +#define RFC_ULLRAM_BANK1220_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1220_DATA_S 0 //***************************************************************************** // @@ -8847,9 +8847,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1221_DATA_W 32 -#define RFC_ULLRAM_BANK1221_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1221_DATA_S 0 +#define RFC_ULLRAM_BANK1221_DATA_W 32 +#define RFC_ULLRAM_BANK1221_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1221_DATA_S 0 //***************************************************************************** // @@ -8859,9 +8859,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1222_DATA_W 32 -#define RFC_ULLRAM_BANK1222_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1222_DATA_S 0 +#define RFC_ULLRAM_BANK1222_DATA_W 32 +#define RFC_ULLRAM_BANK1222_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1222_DATA_S 0 //***************************************************************************** // @@ -8871,9 +8871,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1223_DATA_W 32 -#define RFC_ULLRAM_BANK1223_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1223_DATA_S 0 +#define RFC_ULLRAM_BANK1223_DATA_W 32 +#define RFC_ULLRAM_BANK1223_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1223_DATA_S 0 //***************************************************************************** // @@ -8883,9 +8883,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1224_DATA_W 32 -#define RFC_ULLRAM_BANK1224_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1224_DATA_S 0 +#define RFC_ULLRAM_BANK1224_DATA_W 32 +#define RFC_ULLRAM_BANK1224_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1224_DATA_S 0 //***************************************************************************** // @@ -8895,9 +8895,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1225_DATA_W 32 -#define RFC_ULLRAM_BANK1225_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1225_DATA_S 0 +#define RFC_ULLRAM_BANK1225_DATA_W 32 +#define RFC_ULLRAM_BANK1225_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1225_DATA_S 0 //***************************************************************************** // @@ -8907,9 +8907,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1226_DATA_W 32 -#define RFC_ULLRAM_BANK1226_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1226_DATA_S 0 +#define RFC_ULLRAM_BANK1226_DATA_W 32 +#define RFC_ULLRAM_BANK1226_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1226_DATA_S 0 //***************************************************************************** // @@ -8919,9 +8919,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1227_DATA_W 32 -#define RFC_ULLRAM_BANK1227_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1227_DATA_S 0 +#define RFC_ULLRAM_BANK1227_DATA_W 32 +#define RFC_ULLRAM_BANK1227_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1227_DATA_S 0 //***************************************************************************** // @@ -8931,9 +8931,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1228_DATA_W 32 -#define RFC_ULLRAM_BANK1228_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1228_DATA_S 0 +#define RFC_ULLRAM_BANK1228_DATA_W 32 +#define RFC_ULLRAM_BANK1228_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1228_DATA_S 0 //***************************************************************************** // @@ -8943,9 +8943,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1229_DATA_W 32 -#define RFC_ULLRAM_BANK1229_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1229_DATA_S 0 +#define RFC_ULLRAM_BANK1229_DATA_W 32 +#define RFC_ULLRAM_BANK1229_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1229_DATA_S 0 //***************************************************************************** // @@ -8955,9 +8955,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1230_DATA_W 32 -#define RFC_ULLRAM_BANK1230_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1230_DATA_S 0 +#define RFC_ULLRAM_BANK1230_DATA_W 32 +#define RFC_ULLRAM_BANK1230_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1230_DATA_S 0 //***************************************************************************** // @@ -8967,9 +8967,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1231_DATA_W 32 -#define RFC_ULLRAM_BANK1231_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1231_DATA_S 0 +#define RFC_ULLRAM_BANK1231_DATA_W 32 +#define RFC_ULLRAM_BANK1231_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1231_DATA_S 0 //***************************************************************************** // @@ -8979,9 +8979,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1232_DATA_W 32 -#define RFC_ULLRAM_BANK1232_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1232_DATA_S 0 +#define RFC_ULLRAM_BANK1232_DATA_W 32 +#define RFC_ULLRAM_BANK1232_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1232_DATA_S 0 //***************************************************************************** // @@ -8991,9 +8991,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1233_DATA_W 32 -#define RFC_ULLRAM_BANK1233_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1233_DATA_S 0 +#define RFC_ULLRAM_BANK1233_DATA_W 32 +#define RFC_ULLRAM_BANK1233_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1233_DATA_S 0 //***************************************************************************** // @@ -9003,9 +9003,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1234_DATA_W 32 -#define RFC_ULLRAM_BANK1234_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1234_DATA_S 0 +#define RFC_ULLRAM_BANK1234_DATA_W 32 +#define RFC_ULLRAM_BANK1234_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1234_DATA_S 0 //***************************************************************************** // @@ -9015,9 +9015,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1235_DATA_W 32 -#define RFC_ULLRAM_BANK1235_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1235_DATA_S 0 +#define RFC_ULLRAM_BANK1235_DATA_W 32 +#define RFC_ULLRAM_BANK1235_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1235_DATA_S 0 //***************************************************************************** // @@ -9027,9 +9027,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1236_DATA_W 32 -#define RFC_ULLRAM_BANK1236_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1236_DATA_S 0 +#define RFC_ULLRAM_BANK1236_DATA_W 32 +#define RFC_ULLRAM_BANK1236_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1236_DATA_S 0 //***************************************************************************** // @@ -9039,9 +9039,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1237_DATA_W 32 -#define RFC_ULLRAM_BANK1237_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1237_DATA_S 0 +#define RFC_ULLRAM_BANK1237_DATA_W 32 +#define RFC_ULLRAM_BANK1237_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1237_DATA_S 0 //***************************************************************************** // @@ -9051,9 +9051,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1238_DATA_W 32 -#define RFC_ULLRAM_BANK1238_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1238_DATA_S 0 +#define RFC_ULLRAM_BANK1238_DATA_W 32 +#define RFC_ULLRAM_BANK1238_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1238_DATA_S 0 //***************************************************************************** // @@ -9063,9 +9063,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1239_DATA_W 32 -#define RFC_ULLRAM_BANK1239_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1239_DATA_S 0 +#define RFC_ULLRAM_BANK1239_DATA_W 32 +#define RFC_ULLRAM_BANK1239_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1239_DATA_S 0 //***************************************************************************** // @@ -9075,9 +9075,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1240_DATA_W 32 -#define RFC_ULLRAM_BANK1240_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1240_DATA_S 0 +#define RFC_ULLRAM_BANK1240_DATA_W 32 +#define RFC_ULLRAM_BANK1240_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1240_DATA_S 0 //***************************************************************************** // @@ -9087,9 +9087,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1241_DATA_W 32 -#define RFC_ULLRAM_BANK1241_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1241_DATA_S 0 +#define RFC_ULLRAM_BANK1241_DATA_W 32 +#define RFC_ULLRAM_BANK1241_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1241_DATA_S 0 //***************************************************************************** // @@ -9099,9 +9099,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1242_DATA_W 32 -#define RFC_ULLRAM_BANK1242_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1242_DATA_S 0 +#define RFC_ULLRAM_BANK1242_DATA_W 32 +#define RFC_ULLRAM_BANK1242_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1242_DATA_S 0 //***************************************************************************** // @@ -9111,9 +9111,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1243_DATA_W 32 -#define RFC_ULLRAM_BANK1243_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1243_DATA_S 0 +#define RFC_ULLRAM_BANK1243_DATA_W 32 +#define RFC_ULLRAM_BANK1243_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1243_DATA_S 0 //***************************************************************************** // @@ -9123,9 +9123,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1244_DATA_W 32 -#define RFC_ULLRAM_BANK1244_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1244_DATA_S 0 +#define RFC_ULLRAM_BANK1244_DATA_W 32 +#define RFC_ULLRAM_BANK1244_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1244_DATA_S 0 //***************************************************************************** // @@ -9135,9 +9135,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1245_DATA_W 32 -#define RFC_ULLRAM_BANK1245_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1245_DATA_S 0 +#define RFC_ULLRAM_BANK1245_DATA_W 32 +#define RFC_ULLRAM_BANK1245_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1245_DATA_S 0 //***************************************************************************** // @@ -9147,9 +9147,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1246_DATA_W 32 -#define RFC_ULLRAM_BANK1246_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1246_DATA_S 0 +#define RFC_ULLRAM_BANK1246_DATA_W 32 +#define RFC_ULLRAM_BANK1246_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1246_DATA_S 0 //***************************************************************************** // @@ -9159,9 +9159,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1247_DATA_W 32 -#define RFC_ULLRAM_BANK1247_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1247_DATA_S 0 +#define RFC_ULLRAM_BANK1247_DATA_W 32 +#define RFC_ULLRAM_BANK1247_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1247_DATA_S 0 //***************************************************************************** // @@ -9171,9 +9171,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1248_DATA_W 32 -#define RFC_ULLRAM_BANK1248_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1248_DATA_S 0 +#define RFC_ULLRAM_BANK1248_DATA_W 32 +#define RFC_ULLRAM_BANK1248_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1248_DATA_S 0 //***************************************************************************** // @@ -9183,9 +9183,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1249_DATA_W 32 -#define RFC_ULLRAM_BANK1249_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1249_DATA_S 0 +#define RFC_ULLRAM_BANK1249_DATA_W 32 +#define RFC_ULLRAM_BANK1249_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1249_DATA_S 0 //***************************************************************************** // @@ -9195,9 +9195,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1250_DATA_W 32 -#define RFC_ULLRAM_BANK1250_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1250_DATA_S 0 +#define RFC_ULLRAM_BANK1250_DATA_W 32 +#define RFC_ULLRAM_BANK1250_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1250_DATA_S 0 //***************************************************************************** // @@ -9207,9 +9207,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1251_DATA_W 32 -#define RFC_ULLRAM_BANK1251_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1251_DATA_S 0 +#define RFC_ULLRAM_BANK1251_DATA_W 32 +#define RFC_ULLRAM_BANK1251_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1251_DATA_S 0 //***************************************************************************** // @@ -9219,9 +9219,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1252_DATA_W 32 -#define RFC_ULLRAM_BANK1252_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1252_DATA_S 0 +#define RFC_ULLRAM_BANK1252_DATA_W 32 +#define RFC_ULLRAM_BANK1252_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1252_DATA_S 0 //***************************************************************************** // @@ -9231,9 +9231,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1253_DATA_W 32 -#define RFC_ULLRAM_BANK1253_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1253_DATA_S 0 +#define RFC_ULLRAM_BANK1253_DATA_W 32 +#define RFC_ULLRAM_BANK1253_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1253_DATA_S 0 //***************************************************************************** // @@ -9243,9 +9243,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1254_DATA_W 32 -#define RFC_ULLRAM_BANK1254_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1254_DATA_S 0 +#define RFC_ULLRAM_BANK1254_DATA_W 32 +#define RFC_ULLRAM_BANK1254_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1254_DATA_S 0 //***************************************************************************** // @@ -9255,9 +9255,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1255_DATA_W 32 -#define RFC_ULLRAM_BANK1255_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1255_DATA_S 0 +#define RFC_ULLRAM_BANK1255_DATA_W 32 +#define RFC_ULLRAM_BANK1255_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1255_DATA_S 0 //***************************************************************************** // @@ -9267,9 +9267,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1256_DATA_W 32 -#define RFC_ULLRAM_BANK1256_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1256_DATA_S 0 +#define RFC_ULLRAM_BANK1256_DATA_W 32 +#define RFC_ULLRAM_BANK1256_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1256_DATA_S 0 //***************************************************************************** // @@ -9279,9 +9279,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1257_DATA_W 32 -#define RFC_ULLRAM_BANK1257_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1257_DATA_S 0 +#define RFC_ULLRAM_BANK1257_DATA_W 32 +#define RFC_ULLRAM_BANK1257_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1257_DATA_S 0 //***************************************************************************** // @@ -9291,9 +9291,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1258_DATA_W 32 -#define RFC_ULLRAM_BANK1258_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1258_DATA_S 0 +#define RFC_ULLRAM_BANK1258_DATA_W 32 +#define RFC_ULLRAM_BANK1258_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1258_DATA_S 0 //***************************************************************************** // @@ -9303,9 +9303,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1259_DATA_W 32 -#define RFC_ULLRAM_BANK1259_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1259_DATA_S 0 +#define RFC_ULLRAM_BANK1259_DATA_W 32 +#define RFC_ULLRAM_BANK1259_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1259_DATA_S 0 //***************************************************************************** // @@ -9315,9 +9315,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1260_DATA_W 32 -#define RFC_ULLRAM_BANK1260_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1260_DATA_S 0 +#define RFC_ULLRAM_BANK1260_DATA_W 32 +#define RFC_ULLRAM_BANK1260_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1260_DATA_S 0 //***************************************************************************** // @@ -9327,9 +9327,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1261_DATA_W 32 -#define RFC_ULLRAM_BANK1261_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1261_DATA_S 0 +#define RFC_ULLRAM_BANK1261_DATA_W 32 +#define RFC_ULLRAM_BANK1261_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1261_DATA_S 0 //***************************************************************************** // @@ -9339,9 +9339,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1262_DATA_W 32 -#define RFC_ULLRAM_BANK1262_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1262_DATA_S 0 +#define RFC_ULLRAM_BANK1262_DATA_W 32 +#define RFC_ULLRAM_BANK1262_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1262_DATA_S 0 //***************************************************************************** // @@ -9351,9 +9351,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1263_DATA_W 32 -#define RFC_ULLRAM_BANK1263_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1263_DATA_S 0 +#define RFC_ULLRAM_BANK1263_DATA_W 32 +#define RFC_ULLRAM_BANK1263_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1263_DATA_S 0 //***************************************************************************** // @@ -9363,9 +9363,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1264_DATA_W 32 -#define RFC_ULLRAM_BANK1264_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1264_DATA_S 0 +#define RFC_ULLRAM_BANK1264_DATA_W 32 +#define RFC_ULLRAM_BANK1264_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1264_DATA_S 0 //***************************************************************************** // @@ -9375,9 +9375,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1265_DATA_W 32 -#define RFC_ULLRAM_BANK1265_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1265_DATA_S 0 +#define RFC_ULLRAM_BANK1265_DATA_W 32 +#define RFC_ULLRAM_BANK1265_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1265_DATA_S 0 //***************************************************************************** // @@ -9387,9 +9387,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1266_DATA_W 32 -#define RFC_ULLRAM_BANK1266_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1266_DATA_S 0 +#define RFC_ULLRAM_BANK1266_DATA_W 32 +#define RFC_ULLRAM_BANK1266_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1266_DATA_S 0 //***************************************************************************** // @@ -9399,9 +9399,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1267_DATA_W 32 -#define RFC_ULLRAM_BANK1267_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1267_DATA_S 0 +#define RFC_ULLRAM_BANK1267_DATA_W 32 +#define RFC_ULLRAM_BANK1267_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1267_DATA_S 0 //***************************************************************************** // @@ -9411,9 +9411,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1268_DATA_W 32 -#define RFC_ULLRAM_BANK1268_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1268_DATA_S 0 +#define RFC_ULLRAM_BANK1268_DATA_W 32 +#define RFC_ULLRAM_BANK1268_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1268_DATA_S 0 //***************************************************************************** // @@ -9423,9 +9423,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1269_DATA_W 32 -#define RFC_ULLRAM_BANK1269_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1269_DATA_S 0 +#define RFC_ULLRAM_BANK1269_DATA_W 32 +#define RFC_ULLRAM_BANK1269_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1269_DATA_S 0 //***************************************************************************** // @@ -9435,9 +9435,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1270_DATA_W 32 -#define RFC_ULLRAM_BANK1270_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1270_DATA_S 0 +#define RFC_ULLRAM_BANK1270_DATA_W 32 +#define RFC_ULLRAM_BANK1270_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1270_DATA_S 0 //***************************************************************************** // @@ -9447,9 +9447,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1271_DATA_W 32 -#define RFC_ULLRAM_BANK1271_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1271_DATA_S 0 +#define RFC_ULLRAM_BANK1271_DATA_W 32 +#define RFC_ULLRAM_BANK1271_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1271_DATA_S 0 //***************************************************************************** // @@ -9459,9 +9459,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1272_DATA_W 32 -#define RFC_ULLRAM_BANK1272_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1272_DATA_S 0 +#define RFC_ULLRAM_BANK1272_DATA_W 32 +#define RFC_ULLRAM_BANK1272_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1272_DATA_S 0 //***************************************************************************** // @@ -9471,9 +9471,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1273_DATA_W 32 -#define RFC_ULLRAM_BANK1273_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1273_DATA_S 0 +#define RFC_ULLRAM_BANK1273_DATA_W 32 +#define RFC_ULLRAM_BANK1273_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1273_DATA_S 0 //***************************************************************************** // @@ -9483,9 +9483,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1274_DATA_W 32 -#define RFC_ULLRAM_BANK1274_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1274_DATA_S 0 +#define RFC_ULLRAM_BANK1274_DATA_W 32 +#define RFC_ULLRAM_BANK1274_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1274_DATA_S 0 //***************************************************************************** // @@ -9495,9 +9495,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1275_DATA_W 32 -#define RFC_ULLRAM_BANK1275_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1275_DATA_S 0 +#define RFC_ULLRAM_BANK1275_DATA_W 32 +#define RFC_ULLRAM_BANK1275_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1275_DATA_S 0 //***************************************************************************** // @@ -9507,9 +9507,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1276_DATA_W 32 -#define RFC_ULLRAM_BANK1276_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1276_DATA_S 0 +#define RFC_ULLRAM_BANK1276_DATA_W 32 +#define RFC_ULLRAM_BANK1276_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1276_DATA_S 0 //***************************************************************************** // @@ -9519,9 +9519,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1277_DATA_W 32 -#define RFC_ULLRAM_BANK1277_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1277_DATA_S 0 +#define RFC_ULLRAM_BANK1277_DATA_W 32 +#define RFC_ULLRAM_BANK1277_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1277_DATA_S 0 //***************************************************************************** // @@ -9531,9 +9531,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1278_DATA_W 32 -#define RFC_ULLRAM_BANK1278_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1278_DATA_S 0 +#define RFC_ULLRAM_BANK1278_DATA_W 32 +#define RFC_ULLRAM_BANK1278_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1278_DATA_S 0 //***************************************************************************** // @@ -9543,9 +9543,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1279_DATA_W 32 -#define RFC_ULLRAM_BANK1279_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1279_DATA_S 0 +#define RFC_ULLRAM_BANK1279_DATA_W 32 +#define RFC_ULLRAM_BANK1279_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1279_DATA_S 0 //***************************************************************************** // @@ -9555,9 +9555,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1280_DATA_W 32 -#define RFC_ULLRAM_BANK1280_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1280_DATA_S 0 +#define RFC_ULLRAM_BANK1280_DATA_W 32 +#define RFC_ULLRAM_BANK1280_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1280_DATA_S 0 //***************************************************************************** // @@ -9567,9 +9567,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1281_DATA_W 32 -#define RFC_ULLRAM_BANK1281_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1281_DATA_S 0 +#define RFC_ULLRAM_BANK1281_DATA_W 32 +#define RFC_ULLRAM_BANK1281_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1281_DATA_S 0 //***************************************************************************** // @@ -9579,9 +9579,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1282_DATA_W 32 -#define RFC_ULLRAM_BANK1282_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1282_DATA_S 0 +#define RFC_ULLRAM_BANK1282_DATA_W 32 +#define RFC_ULLRAM_BANK1282_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1282_DATA_S 0 //***************************************************************************** // @@ -9591,9 +9591,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1283_DATA_W 32 -#define RFC_ULLRAM_BANK1283_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1283_DATA_S 0 +#define RFC_ULLRAM_BANK1283_DATA_W 32 +#define RFC_ULLRAM_BANK1283_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1283_DATA_S 0 //***************************************************************************** // @@ -9603,9 +9603,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1284_DATA_W 32 -#define RFC_ULLRAM_BANK1284_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1284_DATA_S 0 +#define RFC_ULLRAM_BANK1284_DATA_W 32 +#define RFC_ULLRAM_BANK1284_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1284_DATA_S 0 //***************************************************************************** // @@ -9615,9 +9615,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1285_DATA_W 32 -#define RFC_ULLRAM_BANK1285_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1285_DATA_S 0 +#define RFC_ULLRAM_BANK1285_DATA_W 32 +#define RFC_ULLRAM_BANK1285_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1285_DATA_S 0 //***************************************************************************** // @@ -9627,9 +9627,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1286_DATA_W 32 -#define RFC_ULLRAM_BANK1286_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1286_DATA_S 0 +#define RFC_ULLRAM_BANK1286_DATA_W 32 +#define RFC_ULLRAM_BANK1286_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1286_DATA_S 0 //***************************************************************************** // @@ -9639,9 +9639,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1287_DATA_W 32 -#define RFC_ULLRAM_BANK1287_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1287_DATA_S 0 +#define RFC_ULLRAM_BANK1287_DATA_W 32 +#define RFC_ULLRAM_BANK1287_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1287_DATA_S 0 //***************************************************************************** // @@ -9651,9 +9651,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1288_DATA_W 32 -#define RFC_ULLRAM_BANK1288_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1288_DATA_S 0 +#define RFC_ULLRAM_BANK1288_DATA_W 32 +#define RFC_ULLRAM_BANK1288_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1288_DATA_S 0 //***************************************************************************** // @@ -9663,9 +9663,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1289_DATA_W 32 -#define RFC_ULLRAM_BANK1289_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1289_DATA_S 0 +#define RFC_ULLRAM_BANK1289_DATA_W 32 +#define RFC_ULLRAM_BANK1289_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1289_DATA_S 0 //***************************************************************************** // @@ -9675,9 +9675,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1290_DATA_W 32 -#define RFC_ULLRAM_BANK1290_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1290_DATA_S 0 +#define RFC_ULLRAM_BANK1290_DATA_W 32 +#define RFC_ULLRAM_BANK1290_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1290_DATA_S 0 //***************************************************************************** // @@ -9687,9 +9687,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1291_DATA_W 32 -#define RFC_ULLRAM_BANK1291_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1291_DATA_S 0 +#define RFC_ULLRAM_BANK1291_DATA_W 32 +#define RFC_ULLRAM_BANK1291_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1291_DATA_S 0 //***************************************************************************** // @@ -9699,9 +9699,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1292_DATA_W 32 -#define RFC_ULLRAM_BANK1292_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1292_DATA_S 0 +#define RFC_ULLRAM_BANK1292_DATA_W 32 +#define RFC_ULLRAM_BANK1292_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1292_DATA_S 0 //***************************************************************************** // @@ -9711,9 +9711,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1293_DATA_W 32 -#define RFC_ULLRAM_BANK1293_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1293_DATA_S 0 +#define RFC_ULLRAM_BANK1293_DATA_W 32 +#define RFC_ULLRAM_BANK1293_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1293_DATA_S 0 //***************************************************************************** // @@ -9723,9 +9723,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1294_DATA_W 32 -#define RFC_ULLRAM_BANK1294_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1294_DATA_S 0 +#define RFC_ULLRAM_BANK1294_DATA_W 32 +#define RFC_ULLRAM_BANK1294_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1294_DATA_S 0 //***************************************************************************** // @@ -9735,9 +9735,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1295_DATA_W 32 -#define RFC_ULLRAM_BANK1295_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1295_DATA_S 0 +#define RFC_ULLRAM_BANK1295_DATA_W 32 +#define RFC_ULLRAM_BANK1295_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1295_DATA_S 0 //***************************************************************************** // @@ -9747,9 +9747,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1296_DATA_W 32 -#define RFC_ULLRAM_BANK1296_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1296_DATA_S 0 +#define RFC_ULLRAM_BANK1296_DATA_W 32 +#define RFC_ULLRAM_BANK1296_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1296_DATA_S 0 //***************************************************************************** // @@ -9759,9 +9759,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1297_DATA_W 32 -#define RFC_ULLRAM_BANK1297_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1297_DATA_S 0 +#define RFC_ULLRAM_BANK1297_DATA_W 32 +#define RFC_ULLRAM_BANK1297_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1297_DATA_S 0 //***************************************************************************** // @@ -9771,9 +9771,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1298_DATA_W 32 -#define RFC_ULLRAM_BANK1298_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1298_DATA_S 0 +#define RFC_ULLRAM_BANK1298_DATA_W 32 +#define RFC_ULLRAM_BANK1298_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1298_DATA_S 0 //***************************************************************************** // @@ -9783,9 +9783,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1299_DATA_W 32 -#define RFC_ULLRAM_BANK1299_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1299_DATA_S 0 +#define RFC_ULLRAM_BANK1299_DATA_W 32 +#define RFC_ULLRAM_BANK1299_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1299_DATA_S 0 //***************************************************************************** // @@ -9795,9 +9795,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1300_DATA_W 32 -#define RFC_ULLRAM_BANK1300_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1300_DATA_S 0 +#define RFC_ULLRAM_BANK1300_DATA_W 32 +#define RFC_ULLRAM_BANK1300_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1300_DATA_S 0 //***************************************************************************** // @@ -9807,9 +9807,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1301_DATA_W 32 -#define RFC_ULLRAM_BANK1301_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1301_DATA_S 0 +#define RFC_ULLRAM_BANK1301_DATA_W 32 +#define RFC_ULLRAM_BANK1301_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1301_DATA_S 0 //***************************************************************************** // @@ -9819,9 +9819,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1302_DATA_W 32 -#define RFC_ULLRAM_BANK1302_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1302_DATA_S 0 +#define RFC_ULLRAM_BANK1302_DATA_W 32 +#define RFC_ULLRAM_BANK1302_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1302_DATA_S 0 //***************************************************************************** // @@ -9831,9 +9831,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1303_DATA_W 32 -#define RFC_ULLRAM_BANK1303_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1303_DATA_S 0 +#define RFC_ULLRAM_BANK1303_DATA_W 32 +#define RFC_ULLRAM_BANK1303_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1303_DATA_S 0 //***************************************************************************** // @@ -9843,9 +9843,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1304_DATA_W 32 -#define RFC_ULLRAM_BANK1304_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1304_DATA_S 0 +#define RFC_ULLRAM_BANK1304_DATA_W 32 +#define RFC_ULLRAM_BANK1304_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1304_DATA_S 0 //***************************************************************************** // @@ -9855,9 +9855,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1305_DATA_W 32 -#define RFC_ULLRAM_BANK1305_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1305_DATA_S 0 +#define RFC_ULLRAM_BANK1305_DATA_W 32 +#define RFC_ULLRAM_BANK1305_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1305_DATA_S 0 //***************************************************************************** // @@ -9867,9 +9867,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1306_DATA_W 32 -#define RFC_ULLRAM_BANK1306_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1306_DATA_S 0 +#define RFC_ULLRAM_BANK1306_DATA_W 32 +#define RFC_ULLRAM_BANK1306_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1306_DATA_S 0 //***************************************************************************** // @@ -9879,9 +9879,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1307_DATA_W 32 -#define RFC_ULLRAM_BANK1307_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1307_DATA_S 0 +#define RFC_ULLRAM_BANK1307_DATA_W 32 +#define RFC_ULLRAM_BANK1307_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1307_DATA_S 0 //***************************************************************************** // @@ -9891,9 +9891,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1308_DATA_W 32 -#define RFC_ULLRAM_BANK1308_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1308_DATA_S 0 +#define RFC_ULLRAM_BANK1308_DATA_W 32 +#define RFC_ULLRAM_BANK1308_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1308_DATA_S 0 //***************************************************************************** // @@ -9903,9 +9903,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1309_DATA_W 32 -#define RFC_ULLRAM_BANK1309_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1309_DATA_S 0 +#define RFC_ULLRAM_BANK1309_DATA_W 32 +#define RFC_ULLRAM_BANK1309_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1309_DATA_S 0 //***************************************************************************** // @@ -9915,9 +9915,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1310_DATA_W 32 -#define RFC_ULLRAM_BANK1310_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1310_DATA_S 0 +#define RFC_ULLRAM_BANK1310_DATA_W 32 +#define RFC_ULLRAM_BANK1310_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1310_DATA_S 0 //***************************************************************************** // @@ -9927,9 +9927,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1311_DATA_W 32 -#define RFC_ULLRAM_BANK1311_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1311_DATA_S 0 +#define RFC_ULLRAM_BANK1311_DATA_W 32 +#define RFC_ULLRAM_BANK1311_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1311_DATA_S 0 //***************************************************************************** // @@ -9939,9 +9939,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1312_DATA_W 32 -#define RFC_ULLRAM_BANK1312_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1312_DATA_S 0 +#define RFC_ULLRAM_BANK1312_DATA_W 32 +#define RFC_ULLRAM_BANK1312_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1312_DATA_S 0 //***************************************************************************** // @@ -9951,9 +9951,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1313_DATA_W 32 -#define RFC_ULLRAM_BANK1313_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1313_DATA_S 0 +#define RFC_ULLRAM_BANK1313_DATA_W 32 +#define RFC_ULLRAM_BANK1313_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1313_DATA_S 0 //***************************************************************************** // @@ -9963,9 +9963,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1314_DATA_W 32 -#define RFC_ULLRAM_BANK1314_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1314_DATA_S 0 +#define RFC_ULLRAM_BANK1314_DATA_W 32 +#define RFC_ULLRAM_BANK1314_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1314_DATA_S 0 //***************************************************************************** // @@ -9975,9 +9975,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1315_DATA_W 32 -#define RFC_ULLRAM_BANK1315_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1315_DATA_S 0 +#define RFC_ULLRAM_BANK1315_DATA_W 32 +#define RFC_ULLRAM_BANK1315_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1315_DATA_S 0 //***************************************************************************** // @@ -9987,9 +9987,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1316_DATA_W 32 -#define RFC_ULLRAM_BANK1316_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1316_DATA_S 0 +#define RFC_ULLRAM_BANK1316_DATA_W 32 +#define RFC_ULLRAM_BANK1316_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1316_DATA_S 0 //***************************************************************************** // @@ -9999,9 +9999,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1317_DATA_W 32 -#define RFC_ULLRAM_BANK1317_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1317_DATA_S 0 +#define RFC_ULLRAM_BANK1317_DATA_W 32 +#define RFC_ULLRAM_BANK1317_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1317_DATA_S 0 //***************************************************************************** // @@ -10011,9 +10011,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1318_DATA_W 32 -#define RFC_ULLRAM_BANK1318_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1318_DATA_S 0 +#define RFC_ULLRAM_BANK1318_DATA_W 32 +#define RFC_ULLRAM_BANK1318_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1318_DATA_S 0 //***************************************************************************** // @@ -10023,9 +10023,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1319_DATA_W 32 -#define RFC_ULLRAM_BANK1319_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1319_DATA_S 0 +#define RFC_ULLRAM_BANK1319_DATA_W 32 +#define RFC_ULLRAM_BANK1319_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1319_DATA_S 0 //***************************************************************************** // @@ -10035,9 +10035,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1320_DATA_W 32 -#define RFC_ULLRAM_BANK1320_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1320_DATA_S 0 +#define RFC_ULLRAM_BANK1320_DATA_W 32 +#define RFC_ULLRAM_BANK1320_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1320_DATA_S 0 //***************************************************************************** // @@ -10047,9 +10047,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1321_DATA_W 32 -#define RFC_ULLRAM_BANK1321_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1321_DATA_S 0 +#define RFC_ULLRAM_BANK1321_DATA_W 32 +#define RFC_ULLRAM_BANK1321_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1321_DATA_S 0 //***************************************************************************** // @@ -10059,9 +10059,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1322_DATA_W 32 -#define RFC_ULLRAM_BANK1322_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1322_DATA_S 0 +#define RFC_ULLRAM_BANK1322_DATA_W 32 +#define RFC_ULLRAM_BANK1322_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1322_DATA_S 0 //***************************************************************************** // @@ -10071,9 +10071,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1323_DATA_W 32 -#define RFC_ULLRAM_BANK1323_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1323_DATA_S 0 +#define RFC_ULLRAM_BANK1323_DATA_W 32 +#define RFC_ULLRAM_BANK1323_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1323_DATA_S 0 //***************************************************************************** // @@ -10083,9 +10083,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1324_DATA_W 32 -#define RFC_ULLRAM_BANK1324_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1324_DATA_S 0 +#define RFC_ULLRAM_BANK1324_DATA_W 32 +#define RFC_ULLRAM_BANK1324_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1324_DATA_S 0 //***************************************************************************** // @@ -10095,9 +10095,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1325_DATA_W 32 -#define RFC_ULLRAM_BANK1325_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1325_DATA_S 0 +#define RFC_ULLRAM_BANK1325_DATA_W 32 +#define RFC_ULLRAM_BANK1325_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1325_DATA_S 0 //***************************************************************************** // @@ -10107,9 +10107,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1326_DATA_W 32 -#define RFC_ULLRAM_BANK1326_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1326_DATA_S 0 +#define RFC_ULLRAM_BANK1326_DATA_W 32 +#define RFC_ULLRAM_BANK1326_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1326_DATA_S 0 //***************************************************************************** // @@ -10119,9 +10119,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1327_DATA_W 32 -#define RFC_ULLRAM_BANK1327_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1327_DATA_S 0 +#define RFC_ULLRAM_BANK1327_DATA_W 32 +#define RFC_ULLRAM_BANK1327_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1327_DATA_S 0 //***************************************************************************** // @@ -10131,9 +10131,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1328_DATA_W 32 -#define RFC_ULLRAM_BANK1328_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1328_DATA_S 0 +#define RFC_ULLRAM_BANK1328_DATA_W 32 +#define RFC_ULLRAM_BANK1328_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1328_DATA_S 0 //***************************************************************************** // @@ -10143,9 +10143,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1329_DATA_W 32 -#define RFC_ULLRAM_BANK1329_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1329_DATA_S 0 +#define RFC_ULLRAM_BANK1329_DATA_W 32 +#define RFC_ULLRAM_BANK1329_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1329_DATA_S 0 //***************************************************************************** // @@ -10155,9 +10155,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1330_DATA_W 32 -#define RFC_ULLRAM_BANK1330_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1330_DATA_S 0 +#define RFC_ULLRAM_BANK1330_DATA_W 32 +#define RFC_ULLRAM_BANK1330_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1330_DATA_S 0 //***************************************************************************** // @@ -10167,9 +10167,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1331_DATA_W 32 -#define RFC_ULLRAM_BANK1331_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1331_DATA_S 0 +#define RFC_ULLRAM_BANK1331_DATA_W 32 +#define RFC_ULLRAM_BANK1331_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1331_DATA_S 0 //***************************************************************************** // @@ -10179,9 +10179,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1332_DATA_W 32 -#define RFC_ULLRAM_BANK1332_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1332_DATA_S 0 +#define RFC_ULLRAM_BANK1332_DATA_W 32 +#define RFC_ULLRAM_BANK1332_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1332_DATA_S 0 //***************************************************************************** // @@ -10191,9 +10191,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1333_DATA_W 32 -#define RFC_ULLRAM_BANK1333_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1333_DATA_S 0 +#define RFC_ULLRAM_BANK1333_DATA_W 32 +#define RFC_ULLRAM_BANK1333_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1333_DATA_S 0 //***************************************************************************** // @@ -10203,9 +10203,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1334_DATA_W 32 -#define RFC_ULLRAM_BANK1334_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1334_DATA_S 0 +#define RFC_ULLRAM_BANK1334_DATA_W 32 +#define RFC_ULLRAM_BANK1334_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1334_DATA_S 0 //***************************************************************************** // @@ -10215,9 +10215,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1335_DATA_W 32 -#define RFC_ULLRAM_BANK1335_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1335_DATA_S 0 +#define RFC_ULLRAM_BANK1335_DATA_W 32 +#define RFC_ULLRAM_BANK1335_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1335_DATA_S 0 //***************************************************************************** // @@ -10227,9 +10227,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1336_DATA_W 32 -#define RFC_ULLRAM_BANK1336_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1336_DATA_S 0 +#define RFC_ULLRAM_BANK1336_DATA_W 32 +#define RFC_ULLRAM_BANK1336_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1336_DATA_S 0 //***************************************************************************** // @@ -10239,9 +10239,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1337_DATA_W 32 -#define RFC_ULLRAM_BANK1337_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1337_DATA_S 0 +#define RFC_ULLRAM_BANK1337_DATA_W 32 +#define RFC_ULLRAM_BANK1337_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1337_DATA_S 0 //***************************************************************************** // @@ -10251,9 +10251,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1338_DATA_W 32 -#define RFC_ULLRAM_BANK1338_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1338_DATA_S 0 +#define RFC_ULLRAM_BANK1338_DATA_W 32 +#define RFC_ULLRAM_BANK1338_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1338_DATA_S 0 //***************************************************************************** // @@ -10263,9 +10263,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1339_DATA_W 32 -#define RFC_ULLRAM_BANK1339_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1339_DATA_S 0 +#define RFC_ULLRAM_BANK1339_DATA_W 32 +#define RFC_ULLRAM_BANK1339_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1339_DATA_S 0 //***************************************************************************** // @@ -10275,9 +10275,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1340_DATA_W 32 -#define RFC_ULLRAM_BANK1340_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1340_DATA_S 0 +#define RFC_ULLRAM_BANK1340_DATA_W 32 +#define RFC_ULLRAM_BANK1340_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1340_DATA_S 0 //***************************************************************************** // @@ -10287,9 +10287,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1341_DATA_W 32 -#define RFC_ULLRAM_BANK1341_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1341_DATA_S 0 +#define RFC_ULLRAM_BANK1341_DATA_W 32 +#define RFC_ULLRAM_BANK1341_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1341_DATA_S 0 //***************************************************************************** // @@ -10299,9 +10299,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1342_DATA_W 32 -#define RFC_ULLRAM_BANK1342_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1342_DATA_S 0 +#define RFC_ULLRAM_BANK1342_DATA_W 32 +#define RFC_ULLRAM_BANK1342_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1342_DATA_S 0 //***************************************************************************** // @@ -10311,9 +10311,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1343_DATA_W 32 -#define RFC_ULLRAM_BANK1343_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1343_DATA_S 0 +#define RFC_ULLRAM_BANK1343_DATA_W 32 +#define RFC_ULLRAM_BANK1343_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1343_DATA_S 0 //***************************************************************************** // @@ -10323,9 +10323,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1344_DATA_W 32 -#define RFC_ULLRAM_BANK1344_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1344_DATA_S 0 +#define RFC_ULLRAM_BANK1344_DATA_W 32 +#define RFC_ULLRAM_BANK1344_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1344_DATA_S 0 //***************************************************************************** // @@ -10335,9 +10335,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1345_DATA_W 32 -#define RFC_ULLRAM_BANK1345_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1345_DATA_S 0 +#define RFC_ULLRAM_BANK1345_DATA_W 32 +#define RFC_ULLRAM_BANK1345_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1345_DATA_S 0 //***************************************************************************** // @@ -10347,9 +10347,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1346_DATA_W 32 -#define RFC_ULLRAM_BANK1346_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1346_DATA_S 0 +#define RFC_ULLRAM_BANK1346_DATA_W 32 +#define RFC_ULLRAM_BANK1346_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1346_DATA_S 0 //***************************************************************************** // @@ -10359,9 +10359,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1347_DATA_W 32 -#define RFC_ULLRAM_BANK1347_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1347_DATA_S 0 +#define RFC_ULLRAM_BANK1347_DATA_W 32 +#define RFC_ULLRAM_BANK1347_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1347_DATA_S 0 //***************************************************************************** // @@ -10371,9 +10371,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1348_DATA_W 32 -#define RFC_ULLRAM_BANK1348_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1348_DATA_S 0 +#define RFC_ULLRAM_BANK1348_DATA_W 32 +#define RFC_ULLRAM_BANK1348_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1348_DATA_S 0 //***************************************************************************** // @@ -10383,9 +10383,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1349_DATA_W 32 -#define RFC_ULLRAM_BANK1349_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1349_DATA_S 0 +#define RFC_ULLRAM_BANK1349_DATA_W 32 +#define RFC_ULLRAM_BANK1349_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1349_DATA_S 0 //***************************************************************************** // @@ -10395,9 +10395,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1350_DATA_W 32 -#define RFC_ULLRAM_BANK1350_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1350_DATA_S 0 +#define RFC_ULLRAM_BANK1350_DATA_W 32 +#define RFC_ULLRAM_BANK1350_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1350_DATA_S 0 //***************************************************************************** // @@ -10407,9 +10407,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1351_DATA_W 32 -#define RFC_ULLRAM_BANK1351_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1351_DATA_S 0 +#define RFC_ULLRAM_BANK1351_DATA_W 32 +#define RFC_ULLRAM_BANK1351_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1351_DATA_S 0 //***************************************************************************** // @@ -10419,9 +10419,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1352_DATA_W 32 -#define RFC_ULLRAM_BANK1352_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1352_DATA_S 0 +#define RFC_ULLRAM_BANK1352_DATA_W 32 +#define RFC_ULLRAM_BANK1352_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1352_DATA_S 0 //***************************************************************************** // @@ -10431,9 +10431,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1353_DATA_W 32 -#define RFC_ULLRAM_BANK1353_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1353_DATA_S 0 +#define RFC_ULLRAM_BANK1353_DATA_W 32 +#define RFC_ULLRAM_BANK1353_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1353_DATA_S 0 //***************************************************************************** // @@ -10443,9 +10443,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1354_DATA_W 32 -#define RFC_ULLRAM_BANK1354_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1354_DATA_S 0 +#define RFC_ULLRAM_BANK1354_DATA_W 32 +#define RFC_ULLRAM_BANK1354_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1354_DATA_S 0 //***************************************************************************** // @@ -10455,9 +10455,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1355_DATA_W 32 -#define RFC_ULLRAM_BANK1355_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1355_DATA_S 0 +#define RFC_ULLRAM_BANK1355_DATA_W 32 +#define RFC_ULLRAM_BANK1355_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1355_DATA_S 0 //***************************************************************************** // @@ -10467,9 +10467,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1356_DATA_W 32 -#define RFC_ULLRAM_BANK1356_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1356_DATA_S 0 +#define RFC_ULLRAM_BANK1356_DATA_W 32 +#define RFC_ULLRAM_BANK1356_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1356_DATA_S 0 //***************************************************************************** // @@ -10479,9 +10479,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1357_DATA_W 32 -#define RFC_ULLRAM_BANK1357_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1357_DATA_S 0 +#define RFC_ULLRAM_BANK1357_DATA_W 32 +#define RFC_ULLRAM_BANK1357_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1357_DATA_S 0 //***************************************************************************** // @@ -10491,9 +10491,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1358_DATA_W 32 -#define RFC_ULLRAM_BANK1358_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1358_DATA_S 0 +#define RFC_ULLRAM_BANK1358_DATA_W 32 +#define RFC_ULLRAM_BANK1358_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1358_DATA_S 0 //***************************************************************************** // @@ -10503,9 +10503,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1359_DATA_W 32 -#define RFC_ULLRAM_BANK1359_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1359_DATA_S 0 +#define RFC_ULLRAM_BANK1359_DATA_W 32 +#define RFC_ULLRAM_BANK1359_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1359_DATA_S 0 //***************************************************************************** // @@ -10515,9 +10515,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1360_DATA_W 32 -#define RFC_ULLRAM_BANK1360_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1360_DATA_S 0 +#define RFC_ULLRAM_BANK1360_DATA_W 32 +#define RFC_ULLRAM_BANK1360_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1360_DATA_S 0 //***************************************************************************** // @@ -10527,9 +10527,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1361_DATA_W 32 -#define RFC_ULLRAM_BANK1361_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1361_DATA_S 0 +#define RFC_ULLRAM_BANK1361_DATA_W 32 +#define RFC_ULLRAM_BANK1361_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1361_DATA_S 0 //***************************************************************************** // @@ -10539,9 +10539,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1362_DATA_W 32 -#define RFC_ULLRAM_BANK1362_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1362_DATA_S 0 +#define RFC_ULLRAM_BANK1362_DATA_W 32 +#define RFC_ULLRAM_BANK1362_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1362_DATA_S 0 //***************************************************************************** // @@ -10551,9 +10551,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1363_DATA_W 32 -#define RFC_ULLRAM_BANK1363_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1363_DATA_S 0 +#define RFC_ULLRAM_BANK1363_DATA_W 32 +#define RFC_ULLRAM_BANK1363_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1363_DATA_S 0 //***************************************************************************** // @@ -10563,9 +10563,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1364_DATA_W 32 -#define RFC_ULLRAM_BANK1364_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1364_DATA_S 0 +#define RFC_ULLRAM_BANK1364_DATA_W 32 +#define RFC_ULLRAM_BANK1364_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1364_DATA_S 0 //***************************************************************************** // @@ -10575,9 +10575,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1365_DATA_W 32 -#define RFC_ULLRAM_BANK1365_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1365_DATA_S 0 +#define RFC_ULLRAM_BANK1365_DATA_W 32 +#define RFC_ULLRAM_BANK1365_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1365_DATA_S 0 //***************************************************************************** // @@ -10587,9 +10587,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1366_DATA_W 32 -#define RFC_ULLRAM_BANK1366_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1366_DATA_S 0 +#define RFC_ULLRAM_BANK1366_DATA_W 32 +#define RFC_ULLRAM_BANK1366_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1366_DATA_S 0 //***************************************************************************** // @@ -10599,9 +10599,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1367_DATA_W 32 -#define RFC_ULLRAM_BANK1367_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1367_DATA_S 0 +#define RFC_ULLRAM_BANK1367_DATA_W 32 +#define RFC_ULLRAM_BANK1367_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1367_DATA_S 0 //***************************************************************************** // @@ -10611,9 +10611,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1368_DATA_W 32 -#define RFC_ULLRAM_BANK1368_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1368_DATA_S 0 +#define RFC_ULLRAM_BANK1368_DATA_W 32 +#define RFC_ULLRAM_BANK1368_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1368_DATA_S 0 //***************************************************************************** // @@ -10623,9 +10623,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1369_DATA_W 32 -#define RFC_ULLRAM_BANK1369_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1369_DATA_S 0 +#define RFC_ULLRAM_BANK1369_DATA_W 32 +#define RFC_ULLRAM_BANK1369_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1369_DATA_S 0 //***************************************************************************** // @@ -10635,9 +10635,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1370_DATA_W 32 -#define RFC_ULLRAM_BANK1370_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1370_DATA_S 0 +#define RFC_ULLRAM_BANK1370_DATA_W 32 +#define RFC_ULLRAM_BANK1370_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1370_DATA_S 0 //***************************************************************************** // @@ -10647,9 +10647,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1371_DATA_W 32 -#define RFC_ULLRAM_BANK1371_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1371_DATA_S 0 +#define RFC_ULLRAM_BANK1371_DATA_W 32 +#define RFC_ULLRAM_BANK1371_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1371_DATA_S 0 //***************************************************************************** // @@ -10659,9 +10659,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1372_DATA_W 32 -#define RFC_ULLRAM_BANK1372_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1372_DATA_S 0 +#define RFC_ULLRAM_BANK1372_DATA_W 32 +#define RFC_ULLRAM_BANK1372_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1372_DATA_S 0 //***************************************************************************** // @@ -10671,9 +10671,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1373_DATA_W 32 -#define RFC_ULLRAM_BANK1373_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1373_DATA_S 0 +#define RFC_ULLRAM_BANK1373_DATA_W 32 +#define RFC_ULLRAM_BANK1373_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1373_DATA_S 0 //***************************************************************************** // @@ -10683,9 +10683,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1374_DATA_W 32 -#define RFC_ULLRAM_BANK1374_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1374_DATA_S 0 +#define RFC_ULLRAM_BANK1374_DATA_W 32 +#define RFC_ULLRAM_BANK1374_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1374_DATA_S 0 //***************************************************************************** // @@ -10695,9 +10695,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1375_DATA_W 32 -#define RFC_ULLRAM_BANK1375_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1375_DATA_S 0 +#define RFC_ULLRAM_BANK1375_DATA_W 32 +#define RFC_ULLRAM_BANK1375_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1375_DATA_S 0 //***************************************************************************** // @@ -10707,9 +10707,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1376_DATA_W 32 -#define RFC_ULLRAM_BANK1376_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1376_DATA_S 0 +#define RFC_ULLRAM_BANK1376_DATA_W 32 +#define RFC_ULLRAM_BANK1376_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1376_DATA_S 0 //***************************************************************************** // @@ -10719,9 +10719,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1377_DATA_W 32 -#define RFC_ULLRAM_BANK1377_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1377_DATA_S 0 +#define RFC_ULLRAM_BANK1377_DATA_W 32 +#define RFC_ULLRAM_BANK1377_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1377_DATA_S 0 //***************************************************************************** // @@ -10731,9 +10731,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1378_DATA_W 32 -#define RFC_ULLRAM_BANK1378_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1378_DATA_S 0 +#define RFC_ULLRAM_BANK1378_DATA_W 32 +#define RFC_ULLRAM_BANK1378_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1378_DATA_S 0 //***************************************************************************** // @@ -10743,9 +10743,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1379_DATA_W 32 -#define RFC_ULLRAM_BANK1379_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1379_DATA_S 0 +#define RFC_ULLRAM_BANK1379_DATA_W 32 +#define RFC_ULLRAM_BANK1379_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1379_DATA_S 0 //***************************************************************************** // @@ -10755,9 +10755,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1380_DATA_W 32 -#define RFC_ULLRAM_BANK1380_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1380_DATA_S 0 +#define RFC_ULLRAM_BANK1380_DATA_W 32 +#define RFC_ULLRAM_BANK1380_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1380_DATA_S 0 //***************************************************************************** // @@ -10767,9 +10767,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1381_DATA_W 32 -#define RFC_ULLRAM_BANK1381_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1381_DATA_S 0 +#define RFC_ULLRAM_BANK1381_DATA_W 32 +#define RFC_ULLRAM_BANK1381_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1381_DATA_S 0 //***************************************************************************** // @@ -10779,9 +10779,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1382_DATA_W 32 -#define RFC_ULLRAM_BANK1382_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1382_DATA_S 0 +#define RFC_ULLRAM_BANK1382_DATA_W 32 +#define RFC_ULLRAM_BANK1382_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1382_DATA_S 0 //***************************************************************************** // @@ -10791,9 +10791,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1383_DATA_W 32 -#define RFC_ULLRAM_BANK1383_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1383_DATA_S 0 +#define RFC_ULLRAM_BANK1383_DATA_W 32 +#define RFC_ULLRAM_BANK1383_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1383_DATA_S 0 //***************************************************************************** // @@ -10803,9 +10803,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1384_DATA_W 32 -#define RFC_ULLRAM_BANK1384_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1384_DATA_S 0 +#define RFC_ULLRAM_BANK1384_DATA_W 32 +#define RFC_ULLRAM_BANK1384_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1384_DATA_S 0 //***************************************************************************** // @@ -10815,9 +10815,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1385_DATA_W 32 -#define RFC_ULLRAM_BANK1385_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1385_DATA_S 0 +#define RFC_ULLRAM_BANK1385_DATA_W 32 +#define RFC_ULLRAM_BANK1385_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1385_DATA_S 0 //***************************************************************************** // @@ -10827,9 +10827,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1386_DATA_W 32 -#define RFC_ULLRAM_BANK1386_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1386_DATA_S 0 +#define RFC_ULLRAM_BANK1386_DATA_W 32 +#define RFC_ULLRAM_BANK1386_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1386_DATA_S 0 //***************************************************************************** // @@ -10839,9 +10839,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1387_DATA_W 32 -#define RFC_ULLRAM_BANK1387_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1387_DATA_S 0 +#define RFC_ULLRAM_BANK1387_DATA_W 32 +#define RFC_ULLRAM_BANK1387_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1387_DATA_S 0 //***************************************************************************** // @@ -10851,9 +10851,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1388_DATA_W 32 -#define RFC_ULLRAM_BANK1388_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1388_DATA_S 0 +#define RFC_ULLRAM_BANK1388_DATA_W 32 +#define RFC_ULLRAM_BANK1388_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1388_DATA_S 0 //***************************************************************************** // @@ -10863,9 +10863,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1389_DATA_W 32 -#define RFC_ULLRAM_BANK1389_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1389_DATA_S 0 +#define RFC_ULLRAM_BANK1389_DATA_W 32 +#define RFC_ULLRAM_BANK1389_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1389_DATA_S 0 //***************************************************************************** // @@ -10875,9 +10875,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1390_DATA_W 32 -#define RFC_ULLRAM_BANK1390_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1390_DATA_S 0 +#define RFC_ULLRAM_BANK1390_DATA_W 32 +#define RFC_ULLRAM_BANK1390_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1390_DATA_S 0 //***************************************************************************** // @@ -10887,9 +10887,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1391_DATA_W 32 -#define RFC_ULLRAM_BANK1391_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1391_DATA_S 0 +#define RFC_ULLRAM_BANK1391_DATA_W 32 +#define RFC_ULLRAM_BANK1391_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1391_DATA_S 0 //***************************************************************************** // @@ -10899,9 +10899,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1392_DATA_W 32 -#define RFC_ULLRAM_BANK1392_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1392_DATA_S 0 +#define RFC_ULLRAM_BANK1392_DATA_W 32 +#define RFC_ULLRAM_BANK1392_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1392_DATA_S 0 //***************************************************************************** // @@ -10911,9 +10911,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1393_DATA_W 32 -#define RFC_ULLRAM_BANK1393_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1393_DATA_S 0 +#define RFC_ULLRAM_BANK1393_DATA_W 32 +#define RFC_ULLRAM_BANK1393_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1393_DATA_S 0 //***************************************************************************** // @@ -10923,9 +10923,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1394_DATA_W 32 -#define RFC_ULLRAM_BANK1394_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1394_DATA_S 0 +#define RFC_ULLRAM_BANK1394_DATA_W 32 +#define RFC_ULLRAM_BANK1394_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1394_DATA_S 0 //***************************************************************************** // @@ -10935,9 +10935,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1395_DATA_W 32 -#define RFC_ULLRAM_BANK1395_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1395_DATA_S 0 +#define RFC_ULLRAM_BANK1395_DATA_W 32 +#define RFC_ULLRAM_BANK1395_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1395_DATA_S 0 //***************************************************************************** // @@ -10947,9 +10947,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1396_DATA_W 32 -#define RFC_ULLRAM_BANK1396_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1396_DATA_S 0 +#define RFC_ULLRAM_BANK1396_DATA_W 32 +#define RFC_ULLRAM_BANK1396_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1396_DATA_S 0 //***************************************************************************** // @@ -10959,9 +10959,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1397_DATA_W 32 -#define RFC_ULLRAM_BANK1397_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1397_DATA_S 0 +#define RFC_ULLRAM_BANK1397_DATA_W 32 +#define RFC_ULLRAM_BANK1397_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1397_DATA_S 0 //***************************************************************************** // @@ -10971,9 +10971,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1398_DATA_W 32 -#define RFC_ULLRAM_BANK1398_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1398_DATA_S 0 +#define RFC_ULLRAM_BANK1398_DATA_W 32 +#define RFC_ULLRAM_BANK1398_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1398_DATA_S 0 //***************************************************************************** // @@ -10983,9 +10983,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1399_DATA_W 32 -#define RFC_ULLRAM_BANK1399_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1399_DATA_S 0 +#define RFC_ULLRAM_BANK1399_DATA_W 32 +#define RFC_ULLRAM_BANK1399_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1399_DATA_S 0 //***************************************************************************** // @@ -10995,9 +10995,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1400_DATA_W 32 -#define RFC_ULLRAM_BANK1400_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1400_DATA_S 0 +#define RFC_ULLRAM_BANK1400_DATA_W 32 +#define RFC_ULLRAM_BANK1400_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1400_DATA_S 0 //***************************************************************************** // @@ -11007,9 +11007,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1401_DATA_W 32 -#define RFC_ULLRAM_BANK1401_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1401_DATA_S 0 +#define RFC_ULLRAM_BANK1401_DATA_W 32 +#define RFC_ULLRAM_BANK1401_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1401_DATA_S 0 //***************************************************************************** // @@ -11019,9 +11019,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1402_DATA_W 32 -#define RFC_ULLRAM_BANK1402_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1402_DATA_S 0 +#define RFC_ULLRAM_BANK1402_DATA_W 32 +#define RFC_ULLRAM_BANK1402_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1402_DATA_S 0 //***************************************************************************** // @@ -11031,9 +11031,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1403_DATA_W 32 -#define RFC_ULLRAM_BANK1403_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1403_DATA_S 0 +#define RFC_ULLRAM_BANK1403_DATA_W 32 +#define RFC_ULLRAM_BANK1403_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1403_DATA_S 0 //***************************************************************************** // @@ -11043,9 +11043,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1404_DATA_W 32 -#define RFC_ULLRAM_BANK1404_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1404_DATA_S 0 +#define RFC_ULLRAM_BANK1404_DATA_W 32 +#define RFC_ULLRAM_BANK1404_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1404_DATA_S 0 //***************************************************************************** // @@ -11055,9 +11055,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1405_DATA_W 32 -#define RFC_ULLRAM_BANK1405_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1405_DATA_S 0 +#define RFC_ULLRAM_BANK1405_DATA_W 32 +#define RFC_ULLRAM_BANK1405_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1405_DATA_S 0 //***************************************************************************** // @@ -11067,9 +11067,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1406_DATA_W 32 -#define RFC_ULLRAM_BANK1406_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1406_DATA_S 0 +#define RFC_ULLRAM_BANK1406_DATA_W 32 +#define RFC_ULLRAM_BANK1406_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1406_DATA_S 0 //***************************************************************************** // @@ -11079,9 +11079,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1407_DATA_W 32 -#define RFC_ULLRAM_BANK1407_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1407_DATA_S 0 +#define RFC_ULLRAM_BANK1407_DATA_W 32 +#define RFC_ULLRAM_BANK1407_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1407_DATA_S 0 //***************************************************************************** // @@ -11091,9 +11091,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1408_DATA_W 32 -#define RFC_ULLRAM_BANK1408_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1408_DATA_S 0 +#define RFC_ULLRAM_BANK1408_DATA_W 32 +#define RFC_ULLRAM_BANK1408_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1408_DATA_S 0 //***************************************************************************** // @@ -11103,9 +11103,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1409_DATA_W 32 -#define RFC_ULLRAM_BANK1409_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1409_DATA_S 0 +#define RFC_ULLRAM_BANK1409_DATA_W 32 +#define RFC_ULLRAM_BANK1409_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1409_DATA_S 0 //***************************************************************************** // @@ -11115,9 +11115,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1410_DATA_W 32 -#define RFC_ULLRAM_BANK1410_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1410_DATA_S 0 +#define RFC_ULLRAM_BANK1410_DATA_W 32 +#define RFC_ULLRAM_BANK1410_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1410_DATA_S 0 //***************************************************************************** // @@ -11127,9 +11127,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1411_DATA_W 32 -#define RFC_ULLRAM_BANK1411_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1411_DATA_S 0 +#define RFC_ULLRAM_BANK1411_DATA_W 32 +#define RFC_ULLRAM_BANK1411_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1411_DATA_S 0 //***************************************************************************** // @@ -11139,9 +11139,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1412_DATA_W 32 -#define RFC_ULLRAM_BANK1412_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1412_DATA_S 0 +#define RFC_ULLRAM_BANK1412_DATA_W 32 +#define RFC_ULLRAM_BANK1412_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1412_DATA_S 0 //***************************************************************************** // @@ -11151,9 +11151,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1413_DATA_W 32 -#define RFC_ULLRAM_BANK1413_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1413_DATA_S 0 +#define RFC_ULLRAM_BANK1413_DATA_W 32 +#define RFC_ULLRAM_BANK1413_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1413_DATA_S 0 //***************************************************************************** // @@ -11163,9 +11163,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1414_DATA_W 32 -#define RFC_ULLRAM_BANK1414_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1414_DATA_S 0 +#define RFC_ULLRAM_BANK1414_DATA_W 32 +#define RFC_ULLRAM_BANK1414_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1414_DATA_S 0 //***************************************************************************** // @@ -11175,9 +11175,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1415_DATA_W 32 -#define RFC_ULLRAM_BANK1415_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1415_DATA_S 0 +#define RFC_ULLRAM_BANK1415_DATA_W 32 +#define RFC_ULLRAM_BANK1415_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1415_DATA_S 0 //***************************************************************************** // @@ -11187,9 +11187,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1416_DATA_W 32 -#define RFC_ULLRAM_BANK1416_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1416_DATA_S 0 +#define RFC_ULLRAM_BANK1416_DATA_W 32 +#define RFC_ULLRAM_BANK1416_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1416_DATA_S 0 //***************************************************************************** // @@ -11199,9 +11199,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1417_DATA_W 32 -#define RFC_ULLRAM_BANK1417_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1417_DATA_S 0 +#define RFC_ULLRAM_BANK1417_DATA_W 32 +#define RFC_ULLRAM_BANK1417_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1417_DATA_S 0 //***************************************************************************** // @@ -11211,9 +11211,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1418_DATA_W 32 -#define RFC_ULLRAM_BANK1418_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1418_DATA_S 0 +#define RFC_ULLRAM_BANK1418_DATA_W 32 +#define RFC_ULLRAM_BANK1418_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1418_DATA_S 0 //***************************************************************************** // @@ -11223,9 +11223,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1419_DATA_W 32 -#define RFC_ULLRAM_BANK1419_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1419_DATA_S 0 +#define RFC_ULLRAM_BANK1419_DATA_W 32 +#define RFC_ULLRAM_BANK1419_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1419_DATA_S 0 //***************************************************************************** // @@ -11235,9 +11235,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1420_DATA_W 32 -#define RFC_ULLRAM_BANK1420_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1420_DATA_S 0 +#define RFC_ULLRAM_BANK1420_DATA_W 32 +#define RFC_ULLRAM_BANK1420_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1420_DATA_S 0 //***************************************************************************** // @@ -11247,9 +11247,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1421_DATA_W 32 -#define RFC_ULLRAM_BANK1421_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1421_DATA_S 0 +#define RFC_ULLRAM_BANK1421_DATA_W 32 +#define RFC_ULLRAM_BANK1421_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1421_DATA_S 0 //***************************************************************************** // @@ -11259,9 +11259,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1422_DATA_W 32 -#define RFC_ULLRAM_BANK1422_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1422_DATA_S 0 +#define RFC_ULLRAM_BANK1422_DATA_W 32 +#define RFC_ULLRAM_BANK1422_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1422_DATA_S 0 //***************************************************************************** // @@ -11271,9 +11271,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1423_DATA_W 32 -#define RFC_ULLRAM_BANK1423_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1423_DATA_S 0 +#define RFC_ULLRAM_BANK1423_DATA_W 32 +#define RFC_ULLRAM_BANK1423_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1423_DATA_S 0 //***************************************************************************** // @@ -11283,9 +11283,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1424_DATA_W 32 -#define RFC_ULLRAM_BANK1424_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1424_DATA_S 0 +#define RFC_ULLRAM_BANK1424_DATA_W 32 +#define RFC_ULLRAM_BANK1424_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1424_DATA_S 0 //***************************************************************************** // @@ -11295,9 +11295,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1425_DATA_W 32 -#define RFC_ULLRAM_BANK1425_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1425_DATA_S 0 +#define RFC_ULLRAM_BANK1425_DATA_W 32 +#define RFC_ULLRAM_BANK1425_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1425_DATA_S 0 //***************************************************************************** // @@ -11307,9 +11307,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1426_DATA_W 32 -#define RFC_ULLRAM_BANK1426_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1426_DATA_S 0 +#define RFC_ULLRAM_BANK1426_DATA_W 32 +#define RFC_ULLRAM_BANK1426_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1426_DATA_S 0 //***************************************************************************** // @@ -11319,9 +11319,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1427_DATA_W 32 -#define RFC_ULLRAM_BANK1427_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1427_DATA_S 0 +#define RFC_ULLRAM_BANK1427_DATA_W 32 +#define RFC_ULLRAM_BANK1427_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1427_DATA_S 0 //***************************************************************************** // @@ -11331,9 +11331,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1428_DATA_W 32 -#define RFC_ULLRAM_BANK1428_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1428_DATA_S 0 +#define RFC_ULLRAM_BANK1428_DATA_W 32 +#define RFC_ULLRAM_BANK1428_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1428_DATA_S 0 //***************************************************************************** // @@ -11343,9 +11343,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1429_DATA_W 32 -#define RFC_ULLRAM_BANK1429_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1429_DATA_S 0 +#define RFC_ULLRAM_BANK1429_DATA_W 32 +#define RFC_ULLRAM_BANK1429_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1429_DATA_S 0 //***************************************************************************** // @@ -11355,9 +11355,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1430_DATA_W 32 -#define RFC_ULLRAM_BANK1430_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1430_DATA_S 0 +#define RFC_ULLRAM_BANK1430_DATA_W 32 +#define RFC_ULLRAM_BANK1430_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1430_DATA_S 0 //***************************************************************************** // @@ -11367,9 +11367,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1431_DATA_W 32 -#define RFC_ULLRAM_BANK1431_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1431_DATA_S 0 +#define RFC_ULLRAM_BANK1431_DATA_W 32 +#define RFC_ULLRAM_BANK1431_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1431_DATA_S 0 //***************************************************************************** // @@ -11379,9 +11379,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1432_DATA_W 32 -#define RFC_ULLRAM_BANK1432_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1432_DATA_S 0 +#define RFC_ULLRAM_BANK1432_DATA_W 32 +#define RFC_ULLRAM_BANK1432_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1432_DATA_S 0 //***************************************************************************** // @@ -11391,9 +11391,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1433_DATA_W 32 -#define RFC_ULLRAM_BANK1433_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1433_DATA_S 0 +#define RFC_ULLRAM_BANK1433_DATA_W 32 +#define RFC_ULLRAM_BANK1433_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1433_DATA_S 0 //***************************************************************************** // @@ -11403,9 +11403,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1434_DATA_W 32 -#define RFC_ULLRAM_BANK1434_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1434_DATA_S 0 +#define RFC_ULLRAM_BANK1434_DATA_W 32 +#define RFC_ULLRAM_BANK1434_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1434_DATA_S 0 //***************************************************************************** // @@ -11415,9 +11415,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1435_DATA_W 32 -#define RFC_ULLRAM_BANK1435_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1435_DATA_S 0 +#define RFC_ULLRAM_BANK1435_DATA_W 32 +#define RFC_ULLRAM_BANK1435_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1435_DATA_S 0 //***************************************************************************** // @@ -11427,9 +11427,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1436_DATA_W 32 -#define RFC_ULLRAM_BANK1436_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1436_DATA_S 0 +#define RFC_ULLRAM_BANK1436_DATA_W 32 +#define RFC_ULLRAM_BANK1436_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1436_DATA_S 0 //***************************************************************************** // @@ -11439,9 +11439,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1437_DATA_W 32 -#define RFC_ULLRAM_BANK1437_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1437_DATA_S 0 +#define RFC_ULLRAM_BANK1437_DATA_W 32 +#define RFC_ULLRAM_BANK1437_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1437_DATA_S 0 //***************************************************************************** // @@ -11451,9 +11451,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1438_DATA_W 32 -#define RFC_ULLRAM_BANK1438_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1438_DATA_S 0 +#define RFC_ULLRAM_BANK1438_DATA_W 32 +#define RFC_ULLRAM_BANK1438_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1438_DATA_S 0 //***************************************************************************** // @@ -11463,9 +11463,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1439_DATA_W 32 -#define RFC_ULLRAM_BANK1439_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1439_DATA_S 0 +#define RFC_ULLRAM_BANK1439_DATA_W 32 +#define RFC_ULLRAM_BANK1439_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1439_DATA_S 0 //***************************************************************************** // @@ -11475,9 +11475,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1440_DATA_W 32 -#define RFC_ULLRAM_BANK1440_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1440_DATA_S 0 +#define RFC_ULLRAM_BANK1440_DATA_W 32 +#define RFC_ULLRAM_BANK1440_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1440_DATA_S 0 //***************************************************************************** // @@ -11487,9 +11487,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1441_DATA_W 32 -#define RFC_ULLRAM_BANK1441_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1441_DATA_S 0 +#define RFC_ULLRAM_BANK1441_DATA_W 32 +#define RFC_ULLRAM_BANK1441_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1441_DATA_S 0 //***************************************************************************** // @@ -11499,9 +11499,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1442_DATA_W 32 -#define RFC_ULLRAM_BANK1442_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1442_DATA_S 0 +#define RFC_ULLRAM_BANK1442_DATA_W 32 +#define RFC_ULLRAM_BANK1442_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1442_DATA_S 0 //***************************************************************************** // @@ -11511,9 +11511,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1443_DATA_W 32 -#define RFC_ULLRAM_BANK1443_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1443_DATA_S 0 +#define RFC_ULLRAM_BANK1443_DATA_W 32 +#define RFC_ULLRAM_BANK1443_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1443_DATA_S 0 //***************************************************************************** // @@ -11523,9 +11523,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1444_DATA_W 32 -#define RFC_ULLRAM_BANK1444_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1444_DATA_S 0 +#define RFC_ULLRAM_BANK1444_DATA_W 32 +#define RFC_ULLRAM_BANK1444_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1444_DATA_S 0 //***************************************************************************** // @@ -11535,9 +11535,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1445_DATA_W 32 -#define RFC_ULLRAM_BANK1445_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1445_DATA_S 0 +#define RFC_ULLRAM_BANK1445_DATA_W 32 +#define RFC_ULLRAM_BANK1445_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1445_DATA_S 0 //***************************************************************************** // @@ -11547,9 +11547,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1446_DATA_W 32 -#define RFC_ULLRAM_BANK1446_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1446_DATA_S 0 +#define RFC_ULLRAM_BANK1446_DATA_W 32 +#define RFC_ULLRAM_BANK1446_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1446_DATA_S 0 //***************************************************************************** // @@ -11559,9 +11559,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1447_DATA_W 32 -#define RFC_ULLRAM_BANK1447_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1447_DATA_S 0 +#define RFC_ULLRAM_BANK1447_DATA_W 32 +#define RFC_ULLRAM_BANK1447_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1447_DATA_S 0 //***************************************************************************** // @@ -11571,9 +11571,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1448_DATA_W 32 -#define RFC_ULLRAM_BANK1448_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1448_DATA_S 0 +#define RFC_ULLRAM_BANK1448_DATA_W 32 +#define RFC_ULLRAM_BANK1448_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1448_DATA_S 0 //***************************************************************************** // @@ -11583,9 +11583,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1449_DATA_W 32 -#define RFC_ULLRAM_BANK1449_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1449_DATA_S 0 +#define RFC_ULLRAM_BANK1449_DATA_W 32 +#define RFC_ULLRAM_BANK1449_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1449_DATA_S 0 //***************************************************************************** // @@ -11595,9 +11595,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1450_DATA_W 32 -#define RFC_ULLRAM_BANK1450_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1450_DATA_S 0 +#define RFC_ULLRAM_BANK1450_DATA_W 32 +#define RFC_ULLRAM_BANK1450_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1450_DATA_S 0 //***************************************************************************** // @@ -11607,9 +11607,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1451_DATA_W 32 -#define RFC_ULLRAM_BANK1451_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1451_DATA_S 0 +#define RFC_ULLRAM_BANK1451_DATA_W 32 +#define RFC_ULLRAM_BANK1451_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1451_DATA_S 0 //***************************************************************************** // @@ -11619,9 +11619,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1452_DATA_W 32 -#define RFC_ULLRAM_BANK1452_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1452_DATA_S 0 +#define RFC_ULLRAM_BANK1452_DATA_W 32 +#define RFC_ULLRAM_BANK1452_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1452_DATA_S 0 //***************************************************************************** // @@ -11631,9 +11631,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1453_DATA_W 32 -#define RFC_ULLRAM_BANK1453_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1453_DATA_S 0 +#define RFC_ULLRAM_BANK1453_DATA_W 32 +#define RFC_ULLRAM_BANK1453_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1453_DATA_S 0 //***************************************************************************** // @@ -11643,9 +11643,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1454_DATA_W 32 -#define RFC_ULLRAM_BANK1454_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1454_DATA_S 0 +#define RFC_ULLRAM_BANK1454_DATA_W 32 +#define RFC_ULLRAM_BANK1454_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1454_DATA_S 0 //***************************************************************************** // @@ -11655,9 +11655,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1455_DATA_W 32 -#define RFC_ULLRAM_BANK1455_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1455_DATA_S 0 +#define RFC_ULLRAM_BANK1455_DATA_W 32 +#define RFC_ULLRAM_BANK1455_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1455_DATA_S 0 //***************************************************************************** // @@ -11667,9 +11667,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1456_DATA_W 32 -#define RFC_ULLRAM_BANK1456_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1456_DATA_S 0 +#define RFC_ULLRAM_BANK1456_DATA_W 32 +#define RFC_ULLRAM_BANK1456_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1456_DATA_S 0 //***************************************************************************** // @@ -11679,9 +11679,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1457_DATA_W 32 -#define RFC_ULLRAM_BANK1457_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1457_DATA_S 0 +#define RFC_ULLRAM_BANK1457_DATA_W 32 +#define RFC_ULLRAM_BANK1457_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1457_DATA_S 0 //***************************************************************************** // @@ -11691,9 +11691,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1458_DATA_W 32 -#define RFC_ULLRAM_BANK1458_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1458_DATA_S 0 +#define RFC_ULLRAM_BANK1458_DATA_W 32 +#define RFC_ULLRAM_BANK1458_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1458_DATA_S 0 //***************************************************************************** // @@ -11703,9 +11703,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1459_DATA_W 32 -#define RFC_ULLRAM_BANK1459_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1459_DATA_S 0 +#define RFC_ULLRAM_BANK1459_DATA_W 32 +#define RFC_ULLRAM_BANK1459_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1459_DATA_S 0 //***************************************************************************** // @@ -11715,9 +11715,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1460_DATA_W 32 -#define RFC_ULLRAM_BANK1460_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1460_DATA_S 0 +#define RFC_ULLRAM_BANK1460_DATA_W 32 +#define RFC_ULLRAM_BANK1460_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1460_DATA_S 0 //***************************************************************************** // @@ -11727,9 +11727,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1461_DATA_W 32 -#define RFC_ULLRAM_BANK1461_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1461_DATA_S 0 +#define RFC_ULLRAM_BANK1461_DATA_W 32 +#define RFC_ULLRAM_BANK1461_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1461_DATA_S 0 //***************************************************************************** // @@ -11739,9 +11739,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1462_DATA_W 32 -#define RFC_ULLRAM_BANK1462_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1462_DATA_S 0 +#define RFC_ULLRAM_BANK1462_DATA_W 32 +#define RFC_ULLRAM_BANK1462_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1462_DATA_S 0 //***************************************************************************** // @@ -11751,9 +11751,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1463_DATA_W 32 -#define RFC_ULLRAM_BANK1463_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1463_DATA_S 0 +#define RFC_ULLRAM_BANK1463_DATA_W 32 +#define RFC_ULLRAM_BANK1463_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1463_DATA_S 0 //***************************************************************************** // @@ -11763,9 +11763,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1464_DATA_W 32 -#define RFC_ULLRAM_BANK1464_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1464_DATA_S 0 +#define RFC_ULLRAM_BANK1464_DATA_W 32 +#define RFC_ULLRAM_BANK1464_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1464_DATA_S 0 //***************************************************************************** // @@ -11775,9 +11775,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1465_DATA_W 32 -#define RFC_ULLRAM_BANK1465_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1465_DATA_S 0 +#define RFC_ULLRAM_BANK1465_DATA_W 32 +#define RFC_ULLRAM_BANK1465_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1465_DATA_S 0 //***************************************************************************** // @@ -11787,9 +11787,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1466_DATA_W 32 -#define RFC_ULLRAM_BANK1466_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1466_DATA_S 0 +#define RFC_ULLRAM_BANK1466_DATA_W 32 +#define RFC_ULLRAM_BANK1466_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1466_DATA_S 0 //***************************************************************************** // @@ -11799,9 +11799,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1467_DATA_W 32 -#define RFC_ULLRAM_BANK1467_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1467_DATA_S 0 +#define RFC_ULLRAM_BANK1467_DATA_W 32 +#define RFC_ULLRAM_BANK1467_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1467_DATA_S 0 //***************************************************************************** // @@ -11811,9 +11811,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1468_DATA_W 32 -#define RFC_ULLRAM_BANK1468_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1468_DATA_S 0 +#define RFC_ULLRAM_BANK1468_DATA_W 32 +#define RFC_ULLRAM_BANK1468_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1468_DATA_S 0 //***************************************************************************** // @@ -11823,9 +11823,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1469_DATA_W 32 -#define RFC_ULLRAM_BANK1469_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1469_DATA_S 0 +#define RFC_ULLRAM_BANK1469_DATA_W 32 +#define RFC_ULLRAM_BANK1469_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1469_DATA_S 0 //***************************************************************************** // @@ -11835,9 +11835,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1470_DATA_W 32 -#define RFC_ULLRAM_BANK1470_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1470_DATA_S 0 +#define RFC_ULLRAM_BANK1470_DATA_W 32 +#define RFC_ULLRAM_BANK1470_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1470_DATA_S 0 //***************************************************************************** // @@ -11847,9 +11847,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1471_DATA_W 32 -#define RFC_ULLRAM_BANK1471_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1471_DATA_S 0 +#define RFC_ULLRAM_BANK1471_DATA_W 32 +#define RFC_ULLRAM_BANK1471_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1471_DATA_S 0 //***************************************************************************** // @@ -11859,9 +11859,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1472_DATA_W 32 -#define RFC_ULLRAM_BANK1472_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1472_DATA_S 0 +#define RFC_ULLRAM_BANK1472_DATA_W 32 +#define RFC_ULLRAM_BANK1472_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1472_DATA_S 0 //***************************************************************************** // @@ -11871,9 +11871,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1473_DATA_W 32 -#define RFC_ULLRAM_BANK1473_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1473_DATA_S 0 +#define RFC_ULLRAM_BANK1473_DATA_W 32 +#define RFC_ULLRAM_BANK1473_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1473_DATA_S 0 //***************************************************************************** // @@ -11883,9 +11883,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1474_DATA_W 32 -#define RFC_ULLRAM_BANK1474_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1474_DATA_S 0 +#define RFC_ULLRAM_BANK1474_DATA_W 32 +#define RFC_ULLRAM_BANK1474_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1474_DATA_S 0 //***************************************************************************** // @@ -11895,9 +11895,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1475_DATA_W 32 -#define RFC_ULLRAM_BANK1475_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1475_DATA_S 0 +#define RFC_ULLRAM_BANK1475_DATA_W 32 +#define RFC_ULLRAM_BANK1475_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1475_DATA_S 0 //***************************************************************************** // @@ -11907,9 +11907,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1476_DATA_W 32 -#define RFC_ULLRAM_BANK1476_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1476_DATA_S 0 +#define RFC_ULLRAM_BANK1476_DATA_W 32 +#define RFC_ULLRAM_BANK1476_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1476_DATA_S 0 //***************************************************************************** // @@ -11919,9 +11919,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1477_DATA_W 32 -#define RFC_ULLRAM_BANK1477_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1477_DATA_S 0 +#define RFC_ULLRAM_BANK1477_DATA_W 32 +#define RFC_ULLRAM_BANK1477_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1477_DATA_S 0 //***************************************************************************** // @@ -11931,9 +11931,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1478_DATA_W 32 -#define RFC_ULLRAM_BANK1478_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1478_DATA_S 0 +#define RFC_ULLRAM_BANK1478_DATA_W 32 +#define RFC_ULLRAM_BANK1478_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1478_DATA_S 0 //***************************************************************************** // @@ -11943,9 +11943,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1479_DATA_W 32 -#define RFC_ULLRAM_BANK1479_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1479_DATA_S 0 +#define RFC_ULLRAM_BANK1479_DATA_W 32 +#define RFC_ULLRAM_BANK1479_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1479_DATA_S 0 //***************************************************************************** // @@ -11955,9 +11955,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1480_DATA_W 32 -#define RFC_ULLRAM_BANK1480_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1480_DATA_S 0 +#define RFC_ULLRAM_BANK1480_DATA_W 32 +#define RFC_ULLRAM_BANK1480_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1480_DATA_S 0 //***************************************************************************** // @@ -11967,9 +11967,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1481_DATA_W 32 -#define RFC_ULLRAM_BANK1481_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1481_DATA_S 0 +#define RFC_ULLRAM_BANK1481_DATA_W 32 +#define RFC_ULLRAM_BANK1481_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1481_DATA_S 0 //***************************************************************************** // @@ -11979,9 +11979,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1482_DATA_W 32 -#define RFC_ULLRAM_BANK1482_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1482_DATA_S 0 +#define RFC_ULLRAM_BANK1482_DATA_W 32 +#define RFC_ULLRAM_BANK1482_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1482_DATA_S 0 //***************************************************************************** // @@ -11991,9 +11991,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1483_DATA_W 32 -#define RFC_ULLRAM_BANK1483_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1483_DATA_S 0 +#define RFC_ULLRAM_BANK1483_DATA_W 32 +#define RFC_ULLRAM_BANK1483_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1483_DATA_S 0 //***************************************************************************** // @@ -12003,9 +12003,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1484_DATA_W 32 -#define RFC_ULLRAM_BANK1484_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1484_DATA_S 0 +#define RFC_ULLRAM_BANK1484_DATA_W 32 +#define RFC_ULLRAM_BANK1484_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1484_DATA_S 0 //***************************************************************************** // @@ -12015,9 +12015,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1485_DATA_W 32 -#define RFC_ULLRAM_BANK1485_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1485_DATA_S 0 +#define RFC_ULLRAM_BANK1485_DATA_W 32 +#define RFC_ULLRAM_BANK1485_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1485_DATA_S 0 //***************************************************************************** // @@ -12027,9 +12027,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1486_DATA_W 32 -#define RFC_ULLRAM_BANK1486_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1486_DATA_S 0 +#define RFC_ULLRAM_BANK1486_DATA_W 32 +#define RFC_ULLRAM_BANK1486_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1486_DATA_S 0 //***************************************************************************** // @@ -12039,9 +12039,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1487_DATA_W 32 -#define RFC_ULLRAM_BANK1487_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1487_DATA_S 0 +#define RFC_ULLRAM_BANK1487_DATA_W 32 +#define RFC_ULLRAM_BANK1487_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1487_DATA_S 0 //***************************************************************************** // @@ -12051,9 +12051,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1488_DATA_W 32 -#define RFC_ULLRAM_BANK1488_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1488_DATA_S 0 +#define RFC_ULLRAM_BANK1488_DATA_W 32 +#define RFC_ULLRAM_BANK1488_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1488_DATA_S 0 //***************************************************************************** // @@ -12063,9 +12063,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1489_DATA_W 32 -#define RFC_ULLRAM_BANK1489_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1489_DATA_S 0 +#define RFC_ULLRAM_BANK1489_DATA_W 32 +#define RFC_ULLRAM_BANK1489_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1489_DATA_S 0 //***************************************************************************** // @@ -12075,9 +12075,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1490_DATA_W 32 -#define RFC_ULLRAM_BANK1490_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1490_DATA_S 0 +#define RFC_ULLRAM_BANK1490_DATA_W 32 +#define RFC_ULLRAM_BANK1490_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1490_DATA_S 0 //***************************************************************************** // @@ -12087,9 +12087,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1491_DATA_W 32 -#define RFC_ULLRAM_BANK1491_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1491_DATA_S 0 +#define RFC_ULLRAM_BANK1491_DATA_W 32 +#define RFC_ULLRAM_BANK1491_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1491_DATA_S 0 //***************************************************************************** // @@ -12099,9 +12099,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1492_DATA_W 32 -#define RFC_ULLRAM_BANK1492_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1492_DATA_S 0 +#define RFC_ULLRAM_BANK1492_DATA_W 32 +#define RFC_ULLRAM_BANK1492_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1492_DATA_S 0 //***************************************************************************** // @@ -12111,9 +12111,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1493_DATA_W 32 -#define RFC_ULLRAM_BANK1493_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1493_DATA_S 0 +#define RFC_ULLRAM_BANK1493_DATA_W 32 +#define RFC_ULLRAM_BANK1493_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1493_DATA_S 0 //***************************************************************************** // @@ -12123,9 +12123,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1494_DATA_W 32 -#define RFC_ULLRAM_BANK1494_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1494_DATA_S 0 +#define RFC_ULLRAM_BANK1494_DATA_W 32 +#define RFC_ULLRAM_BANK1494_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1494_DATA_S 0 //***************************************************************************** // @@ -12135,9 +12135,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1495_DATA_W 32 -#define RFC_ULLRAM_BANK1495_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1495_DATA_S 0 +#define RFC_ULLRAM_BANK1495_DATA_W 32 +#define RFC_ULLRAM_BANK1495_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1495_DATA_S 0 //***************************************************************************** // @@ -12147,9 +12147,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1496_DATA_W 32 -#define RFC_ULLRAM_BANK1496_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1496_DATA_S 0 +#define RFC_ULLRAM_BANK1496_DATA_W 32 +#define RFC_ULLRAM_BANK1496_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1496_DATA_S 0 //***************************************************************************** // @@ -12159,9 +12159,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1497_DATA_W 32 -#define RFC_ULLRAM_BANK1497_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1497_DATA_S 0 +#define RFC_ULLRAM_BANK1497_DATA_W 32 +#define RFC_ULLRAM_BANK1497_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1497_DATA_S 0 //***************************************************************************** // @@ -12171,9 +12171,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1498_DATA_W 32 -#define RFC_ULLRAM_BANK1498_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1498_DATA_S 0 +#define RFC_ULLRAM_BANK1498_DATA_W 32 +#define RFC_ULLRAM_BANK1498_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1498_DATA_S 0 //***************************************************************************** // @@ -12183,9 +12183,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1499_DATA_W 32 -#define RFC_ULLRAM_BANK1499_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1499_DATA_S 0 +#define RFC_ULLRAM_BANK1499_DATA_W 32 +#define RFC_ULLRAM_BANK1499_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1499_DATA_S 0 //***************************************************************************** // @@ -12195,9 +12195,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1500_DATA_W 32 -#define RFC_ULLRAM_BANK1500_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1500_DATA_S 0 +#define RFC_ULLRAM_BANK1500_DATA_W 32 +#define RFC_ULLRAM_BANK1500_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1500_DATA_S 0 //***************************************************************************** // @@ -12207,9 +12207,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1501_DATA_W 32 -#define RFC_ULLRAM_BANK1501_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1501_DATA_S 0 +#define RFC_ULLRAM_BANK1501_DATA_W 32 +#define RFC_ULLRAM_BANK1501_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1501_DATA_S 0 //***************************************************************************** // @@ -12219,9 +12219,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1502_DATA_W 32 -#define RFC_ULLRAM_BANK1502_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1502_DATA_S 0 +#define RFC_ULLRAM_BANK1502_DATA_W 32 +#define RFC_ULLRAM_BANK1502_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1502_DATA_S 0 //***************************************************************************** // @@ -12231,9 +12231,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1503_DATA_W 32 -#define RFC_ULLRAM_BANK1503_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1503_DATA_S 0 +#define RFC_ULLRAM_BANK1503_DATA_W 32 +#define RFC_ULLRAM_BANK1503_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1503_DATA_S 0 //***************************************************************************** // @@ -12243,9 +12243,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1504_DATA_W 32 -#define RFC_ULLRAM_BANK1504_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1504_DATA_S 0 +#define RFC_ULLRAM_BANK1504_DATA_W 32 +#define RFC_ULLRAM_BANK1504_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1504_DATA_S 0 //***************************************************************************** // @@ -12255,9 +12255,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1505_DATA_W 32 -#define RFC_ULLRAM_BANK1505_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1505_DATA_S 0 +#define RFC_ULLRAM_BANK1505_DATA_W 32 +#define RFC_ULLRAM_BANK1505_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1505_DATA_S 0 //***************************************************************************** // @@ -12267,9 +12267,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1506_DATA_W 32 -#define RFC_ULLRAM_BANK1506_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1506_DATA_S 0 +#define RFC_ULLRAM_BANK1506_DATA_W 32 +#define RFC_ULLRAM_BANK1506_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1506_DATA_S 0 //***************************************************************************** // @@ -12279,9 +12279,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1507_DATA_W 32 -#define RFC_ULLRAM_BANK1507_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1507_DATA_S 0 +#define RFC_ULLRAM_BANK1507_DATA_W 32 +#define RFC_ULLRAM_BANK1507_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1507_DATA_S 0 //***************************************************************************** // @@ -12291,9 +12291,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1508_DATA_W 32 -#define RFC_ULLRAM_BANK1508_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1508_DATA_S 0 +#define RFC_ULLRAM_BANK1508_DATA_W 32 +#define RFC_ULLRAM_BANK1508_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1508_DATA_S 0 //***************************************************************************** // @@ -12303,9 +12303,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1509_DATA_W 32 -#define RFC_ULLRAM_BANK1509_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1509_DATA_S 0 +#define RFC_ULLRAM_BANK1509_DATA_W 32 +#define RFC_ULLRAM_BANK1509_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1509_DATA_S 0 //***************************************************************************** // @@ -12315,9 +12315,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1510_DATA_W 32 -#define RFC_ULLRAM_BANK1510_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1510_DATA_S 0 +#define RFC_ULLRAM_BANK1510_DATA_W 32 +#define RFC_ULLRAM_BANK1510_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1510_DATA_S 0 //***************************************************************************** // @@ -12327,9 +12327,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1511_DATA_W 32 -#define RFC_ULLRAM_BANK1511_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1511_DATA_S 0 +#define RFC_ULLRAM_BANK1511_DATA_W 32 +#define RFC_ULLRAM_BANK1511_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1511_DATA_S 0 //***************************************************************************** // @@ -12339,9 +12339,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1512_DATA_W 32 -#define RFC_ULLRAM_BANK1512_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1512_DATA_S 0 +#define RFC_ULLRAM_BANK1512_DATA_W 32 +#define RFC_ULLRAM_BANK1512_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1512_DATA_S 0 //***************************************************************************** // @@ -12351,9 +12351,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1513_DATA_W 32 -#define RFC_ULLRAM_BANK1513_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1513_DATA_S 0 +#define RFC_ULLRAM_BANK1513_DATA_W 32 +#define RFC_ULLRAM_BANK1513_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1513_DATA_S 0 //***************************************************************************** // @@ -12363,9 +12363,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1514_DATA_W 32 -#define RFC_ULLRAM_BANK1514_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1514_DATA_S 0 +#define RFC_ULLRAM_BANK1514_DATA_W 32 +#define RFC_ULLRAM_BANK1514_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1514_DATA_S 0 //***************************************************************************** // @@ -12375,9 +12375,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1515_DATA_W 32 -#define RFC_ULLRAM_BANK1515_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1515_DATA_S 0 +#define RFC_ULLRAM_BANK1515_DATA_W 32 +#define RFC_ULLRAM_BANK1515_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1515_DATA_S 0 //***************************************************************************** // @@ -12387,9 +12387,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1516_DATA_W 32 -#define RFC_ULLRAM_BANK1516_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1516_DATA_S 0 +#define RFC_ULLRAM_BANK1516_DATA_W 32 +#define RFC_ULLRAM_BANK1516_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1516_DATA_S 0 //***************************************************************************** // @@ -12399,9 +12399,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1517_DATA_W 32 -#define RFC_ULLRAM_BANK1517_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1517_DATA_S 0 +#define RFC_ULLRAM_BANK1517_DATA_W 32 +#define RFC_ULLRAM_BANK1517_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1517_DATA_S 0 //***************************************************************************** // @@ -12411,9 +12411,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1518_DATA_W 32 -#define RFC_ULLRAM_BANK1518_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1518_DATA_S 0 +#define RFC_ULLRAM_BANK1518_DATA_W 32 +#define RFC_ULLRAM_BANK1518_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1518_DATA_S 0 //***************************************************************************** // @@ -12423,9 +12423,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1519_DATA_W 32 -#define RFC_ULLRAM_BANK1519_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1519_DATA_S 0 +#define RFC_ULLRAM_BANK1519_DATA_W 32 +#define RFC_ULLRAM_BANK1519_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1519_DATA_S 0 //***************************************************************************** // @@ -12435,9 +12435,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1520_DATA_W 32 -#define RFC_ULLRAM_BANK1520_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1520_DATA_S 0 +#define RFC_ULLRAM_BANK1520_DATA_W 32 +#define RFC_ULLRAM_BANK1520_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1520_DATA_S 0 //***************************************************************************** // @@ -12447,9 +12447,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1521_DATA_W 32 -#define RFC_ULLRAM_BANK1521_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1521_DATA_S 0 +#define RFC_ULLRAM_BANK1521_DATA_W 32 +#define RFC_ULLRAM_BANK1521_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1521_DATA_S 0 //***************************************************************************** // @@ -12459,9 +12459,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1522_DATA_W 32 -#define RFC_ULLRAM_BANK1522_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1522_DATA_S 0 +#define RFC_ULLRAM_BANK1522_DATA_W 32 +#define RFC_ULLRAM_BANK1522_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1522_DATA_S 0 //***************************************************************************** // @@ -12471,9 +12471,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1523_DATA_W 32 -#define RFC_ULLRAM_BANK1523_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1523_DATA_S 0 +#define RFC_ULLRAM_BANK1523_DATA_W 32 +#define RFC_ULLRAM_BANK1523_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1523_DATA_S 0 //***************************************************************************** // @@ -12483,9 +12483,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1524_DATA_W 32 -#define RFC_ULLRAM_BANK1524_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1524_DATA_S 0 +#define RFC_ULLRAM_BANK1524_DATA_W 32 +#define RFC_ULLRAM_BANK1524_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1524_DATA_S 0 //***************************************************************************** // @@ -12495,9 +12495,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1525_DATA_W 32 -#define RFC_ULLRAM_BANK1525_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1525_DATA_S 0 +#define RFC_ULLRAM_BANK1525_DATA_W 32 +#define RFC_ULLRAM_BANK1525_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1525_DATA_S 0 //***************************************************************************** // @@ -12507,9 +12507,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1526_DATA_W 32 -#define RFC_ULLRAM_BANK1526_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1526_DATA_S 0 +#define RFC_ULLRAM_BANK1526_DATA_W 32 +#define RFC_ULLRAM_BANK1526_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1526_DATA_S 0 //***************************************************************************** // @@ -12519,9 +12519,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1527_DATA_W 32 -#define RFC_ULLRAM_BANK1527_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1527_DATA_S 0 +#define RFC_ULLRAM_BANK1527_DATA_W 32 +#define RFC_ULLRAM_BANK1527_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1527_DATA_S 0 //***************************************************************************** // @@ -12531,9 +12531,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1528_DATA_W 32 -#define RFC_ULLRAM_BANK1528_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1528_DATA_S 0 +#define RFC_ULLRAM_BANK1528_DATA_W 32 +#define RFC_ULLRAM_BANK1528_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1528_DATA_S 0 //***************************************************************************** // @@ -12543,9 +12543,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1529_DATA_W 32 -#define RFC_ULLRAM_BANK1529_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1529_DATA_S 0 +#define RFC_ULLRAM_BANK1529_DATA_W 32 +#define RFC_ULLRAM_BANK1529_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1529_DATA_S 0 //***************************************************************************** // @@ -12555,9 +12555,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1530_DATA_W 32 -#define RFC_ULLRAM_BANK1530_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1530_DATA_S 0 +#define RFC_ULLRAM_BANK1530_DATA_W 32 +#define RFC_ULLRAM_BANK1530_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1530_DATA_S 0 //***************************************************************************** // @@ -12567,9 +12567,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1531_DATA_W 32 -#define RFC_ULLRAM_BANK1531_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1531_DATA_S 0 +#define RFC_ULLRAM_BANK1531_DATA_W 32 +#define RFC_ULLRAM_BANK1531_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1531_DATA_S 0 //***************************************************************************** // @@ -12579,9 +12579,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1532_DATA_W 32 -#define RFC_ULLRAM_BANK1532_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1532_DATA_S 0 +#define RFC_ULLRAM_BANK1532_DATA_W 32 +#define RFC_ULLRAM_BANK1532_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1532_DATA_S 0 //***************************************************************************** // @@ -12591,9 +12591,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1533_DATA_W 32 -#define RFC_ULLRAM_BANK1533_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1533_DATA_S 0 +#define RFC_ULLRAM_BANK1533_DATA_W 32 +#define RFC_ULLRAM_BANK1533_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1533_DATA_S 0 //***************************************************************************** // @@ -12603,9 +12603,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1534_DATA_W 32 -#define RFC_ULLRAM_BANK1534_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1534_DATA_S 0 +#define RFC_ULLRAM_BANK1534_DATA_W 32 +#define RFC_ULLRAM_BANK1534_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1534_DATA_S 0 //***************************************************************************** // @@ -12615,9 +12615,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1535_DATA_W 32 -#define RFC_ULLRAM_BANK1535_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1535_DATA_S 0 +#define RFC_ULLRAM_BANK1535_DATA_W 32 +#define RFC_ULLRAM_BANK1535_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1535_DATA_S 0 //***************************************************************************** // @@ -12627,9 +12627,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1536_DATA_W 32 -#define RFC_ULLRAM_BANK1536_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1536_DATA_S 0 +#define RFC_ULLRAM_BANK1536_DATA_W 32 +#define RFC_ULLRAM_BANK1536_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1536_DATA_S 0 //***************************************************************************** // @@ -12639,9 +12639,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1537_DATA_W 32 -#define RFC_ULLRAM_BANK1537_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1537_DATA_S 0 +#define RFC_ULLRAM_BANK1537_DATA_W 32 +#define RFC_ULLRAM_BANK1537_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1537_DATA_S 0 //***************************************************************************** // @@ -12651,9 +12651,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1538_DATA_W 32 -#define RFC_ULLRAM_BANK1538_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1538_DATA_S 0 +#define RFC_ULLRAM_BANK1538_DATA_W 32 +#define RFC_ULLRAM_BANK1538_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1538_DATA_S 0 //***************************************************************************** // @@ -12663,9 +12663,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1539_DATA_W 32 -#define RFC_ULLRAM_BANK1539_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1539_DATA_S 0 +#define RFC_ULLRAM_BANK1539_DATA_W 32 +#define RFC_ULLRAM_BANK1539_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1539_DATA_S 0 //***************************************************************************** // @@ -12675,9 +12675,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1540_DATA_W 32 -#define RFC_ULLRAM_BANK1540_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1540_DATA_S 0 +#define RFC_ULLRAM_BANK1540_DATA_W 32 +#define RFC_ULLRAM_BANK1540_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1540_DATA_S 0 //***************************************************************************** // @@ -12687,9 +12687,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1541_DATA_W 32 -#define RFC_ULLRAM_BANK1541_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1541_DATA_S 0 +#define RFC_ULLRAM_BANK1541_DATA_W 32 +#define RFC_ULLRAM_BANK1541_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1541_DATA_S 0 //***************************************************************************** // @@ -12699,9 +12699,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1542_DATA_W 32 -#define RFC_ULLRAM_BANK1542_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1542_DATA_S 0 +#define RFC_ULLRAM_BANK1542_DATA_W 32 +#define RFC_ULLRAM_BANK1542_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1542_DATA_S 0 //***************************************************************************** // @@ -12711,9 +12711,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1543_DATA_W 32 -#define RFC_ULLRAM_BANK1543_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1543_DATA_S 0 +#define RFC_ULLRAM_BANK1543_DATA_W 32 +#define RFC_ULLRAM_BANK1543_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1543_DATA_S 0 //***************************************************************************** // @@ -12723,9 +12723,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1544_DATA_W 32 -#define RFC_ULLRAM_BANK1544_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1544_DATA_S 0 +#define RFC_ULLRAM_BANK1544_DATA_W 32 +#define RFC_ULLRAM_BANK1544_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1544_DATA_S 0 //***************************************************************************** // @@ -12735,9 +12735,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1545_DATA_W 32 -#define RFC_ULLRAM_BANK1545_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1545_DATA_S 0 +#define RFC_ULLRAM_BANK1545_DATA_W 32 +#define RFC_ULLRAM_BANK1545_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1545_DATA_S 0 //***************************************************************************** // @@ -12747,9 +12747,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1546_DATA_W 32 -#define RFC_ULLRAM_BANK1546_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1546_DATA_S 0 +#define RFC_ULLRAM_BANK1546_DATA_W 32 +#define RFC_ULLRAM_BANK1546_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1546_DATA_S 0 //***************************************************************************** // @@ -12759,9 +12759,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1547_DATA_W 32 -#define RFC_ULLRAM_BANK1547_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1547_DATA_S 0 +#define RFC_ULLRAM_BANK1547_DATA_W 32 +#define RFC_ULLRAM_BANK1547_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1547_DATA_S 0 //***************************************************************************** // @@ -12771,9 +12771,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1548_DATA_W 32 -#define RFC_ULLRAM_BANK1548_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1548_DATA_S 0 +#define RFC_ULLRAM_BANK1548_DATA_W 32 +#define RFC_ULLRAM_BANK1548_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1548_DATA_S 0 //***************************************************************************** // @@ -12783,9 +12783,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1549_DATA_W 32 -#define RFC_ULLRAM_BANK1549_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1549_DATA_S 0 +#define RFC_ULLRAM_BANK1549_DATA_W 32 +#define RFC_ULLRAM_BANK1549_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1549_DATA_S 0 //***************************************************************************** // @@ -12795,9 +12795,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1550_DATA_W 32 -#define RFC_ULLRAM_BANK1550_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1550_DATA_S 0 +#define RFC_ULLRAM_BANK1550_DATA_W 32 +#define RFC_ULLRAM_BANK1550_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1550_DATA_S 0 //***************************************************************************** // @@ -12807,9 +12807,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1551_DATA_W 32 -#define RFC_ULLRAM_BANK1551_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1551_DATA_S 0 +#define RFC_ULLRAM_BANK1551_DATA_W 32 +#define RFC_ULLRAM_BANK1551_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1551_DATA_S 0 //***************************************************************************** // @@ -12819,9 +12819,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1552_DATA_W 32 -#define RFC_ULLRAM_BANK1552_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1552_DATA_S 0 +#define RFC_ULLRAM_BANK1552_DATA_W 32 +#define RFC_ULLRAM_BANK1552_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1552_DATA_S 0 //***************************************************************************** // @@ -12831,9 +12831,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1553_DATA_W 32 -#define RFC_ULLRAM_BANK1553_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1553_DATA_S 0 +#define RFC_ULLRAM_BANK1553_DATA_W 32 +#define RFC_ULLRAM_BANK1553_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1553_DATA_S 0 //***************************************************************************** // @@ -12843,9 +12843,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1554_DATA_W 32 -#define RFC_ULLRAM_BANK1554_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1554_DATA_S 0 +#define RFC_ULLRAM_BANK1554_DATA_W 32 +#define RFC_ULLRAM_BANK1554_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1554_DATA_S 0 //***************************************************************************** // @@ -12855,9 +12855,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1555_DATA_W 32 -#define RFC_ULLRAM_BANK1555_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1555_DATA_S 0 +#define RFC_ULLRAM_BANK1555_DATA_W 32 +#define RFC_ULLRAM_BANK1555_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1555_DATA_S 0 //***************************************************************************** // @@ -12867,9 +12867,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1556_DATA_W 32 -#define RFC_ULLRAM_BANK1556_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1556_DATA_S 0 +#define RFC_ULLRAM_BANK1556_DATA_W 32 +#define RFC_ULLRAM_BANK1556_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1556_DATA_S 0 //***************************************************************************** // @@ -12879,9 +12879,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1557_DATA_W 32 -#define RFC_ULLRAM_BANK1557_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1557_DATA_S 0 +#define RFC_ULLRAM_BANK1557_DATA_W 32 +#define RFC_ULLRAM_BANK1557_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1557_DATA_S 0 //***************************************************************************** // @@ -12891,9 +12891,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1558_DATA_W 32 -#define RFC_ULLRAM_BANK1558_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1558_DATA_S 0 +#define RFC_ULLRAM_BANK1558_DATA_W 32 +#define RFC_ULLRAM_BANK1558_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1558_DATA_S 0 //***************************************************************************** // @@ -12903,9 +12903,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1559_DATA_W 32 -#define RFC_ULLRAM_BANK1559_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1559_DATA_S 0 +#define RFC_ULLRAM_BANK1559_DATA_W 32 +#define RFC_ULLRAM_BANK1559_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1559_DATA_S 0 //***************************************************************************** // @@ -12915,9 +12915,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1560_DATA_W 32 -#define RFC_ULLRAM_BANK1560_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1560_DATA_S 0 +#define RFC_ULLRAM_BANK1560_DATA_W 32 +#define RFC_ULLRAM_BANK1560_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1560_DATA_S 0 //***************************************************************************** // @@ -12927,9 +12927,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1561_DATA_W 32 -#define RFC_ULLRAM_BANK1561_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1561_DATA_S 0 +#define RFC_ULLRAM_BANK1561_DATA_W 32 +#define RFC_ULLRAM_BANK1561_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1561_DATA_S 0 //***************************************************************************** // @@ -12939,9 +12939,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1562_DATA_W 32 -#define RFC_ULLRAM_BANK1562_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1562_DATA_S 0 +#define RFC_ULLRAM_BANK1562_DATA_W 32 +#define RFC_ULLRAM_BANK1562_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1562_DATA_S 0 //***************************************************************************** // @@ -12951,9 +12951,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1563_DATA_W 32 -#define RFC_ULLRAM_BANK1563_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1563_DATA_S 0 +#define RFC_ULLRAM_BANK1563_DATA_W 32 +#define RFC_ULLRAM_BANK1563_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1563_DATA_S 0 //***************************************************************************** // @@ -12963,9 +12963,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1564_DATA_W 32 -#define RFC_ULLRAM_BANK1564_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1564_DATA_S 0 +#define RFC_ULLRAM_BANK1564_DATA_W 32 +#define RFC_ULLRAM_BANK1564_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1564_DATA_S 0 //***************************************************************************** // @@ -12975,9 +12975,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1565_DATA_W 32 -#define RFC_ULLRAM_BANK1565_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1565_DATA_S 0 +#define RFC_ULLRAM_BANK1565_DATA_W 32 +#define RFC_ULLRAM_BANK1565_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1565_DATA_S 0 //***************************************************************************** // @@ -12987,9 +12987,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1566_DATA_W 32 -#define RFC_ULLRAM_BANK1566_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1566_DATA_S 0 +#define RFC_ULLRAM_BANK1566_DATA_W 32 +#define RFC_ULLRAM_BANK1566_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1566_DATA_S 0 //***************************************************************************** // @@ -12999,9 +12999,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1567_DATA_W 32 -#define RFC_ULLRAM_BANK1567_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1567_DATA_S 0 +#define RFC_ULLRAM_BANK1567_DATA_W 32 +#define RFC_ULLRAM_BANK1567_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1567_DATA_S 0 //***************************************************************************** // @@ -13011,9 +13011,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1568_DATA_W 32 -#define RFC_ULLRAM_BANK1568_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1568_DATA_S 0 +#define RFC_ULLRAM_BANK1568_DATA_W 32 +#define RFC_ULLRAM_BANK1568_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1568_DATA_S 0 //***************************************************************************** // @@ -13023,9 +13023,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1569_DATA_W 32 -#define RFC_ULLRAM_BANK1569_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1569_DATA_S 0 +#define RFC_ULLRAM_BANK1569_DATA_W 32 +#define RFC_ULLRAM_BANK1569_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1569_DATA_S 0 //***************************************************************************** // @@ -13035,9 +13035,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1570_DATA_W 32 -#define RFC_ULLRAM_BANK1570_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1570_DATA_S 0 +#define RFC_ULLRAM_BANK1570_DATA_W 32 +#define RFC_ULLRAM_BANK1570_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1570_DATA_S 0 //***************************************************************************** // @@ -13047,9 +13047,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1571_DATA_W 32 -#define RFC_ULLRAM_BANK1571_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1571_DATA_S 0 +#define RFC_ULLRAM_BANK1571_DATA_W 32 +#define RFC_ULLRAM_BANK1571_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1571_DATA_S 0 //***************************************************************************** // @@ -13059,9 +13059,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1572_DATA_W 32 -#define RFC_ULLRAM_BANK1572_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1572_DATA_S 0 +#define RFC_ULLRAM_BANK1572_DATA_W 32 +#define RFC_ULLRAM_BANK1572_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1572_DATA_S 0 //***************************************************************************** // @@ -13071,9 +13071,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1573_DATA_W 32 -#define RFC_ULLRAM_BANK1573_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1573_DATA_S 0 +#define RFC_ULLRAM_BANK1573_DATA_W 32 +#define RFC_ULLRAM_BANK1573_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1573_DATA_S 0 //***************************************************************************** // @@ -13083,9 +13083,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1574_DATA_W 32 -#define RFC_ULLRAM_BANK1574_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1574_DATA_S 0 +#define RFC_ULLRAM_BANK1574_DATA_W 32 +#define RFC_ULLRAM_BANK1574_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1574_DATA_S 0 //***************************************************************************** // @@ -13095,9 +13095,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1575_DATA_W 32 -#define RFC_ULLRAM_BANK1575_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1575_DATA_S 0 +#define RFC_ULLRAM_BANK1575_DATA_W 32 +#define RFC_ULLRAM_BANK1575_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1575_DATA_S 0 //***************************************************************************** // @@ -13107,9 +13107,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1576_DATA_W 32 -#define RFC_ULLRAM_BANK1576_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1576_DATA_S 0 +#define RFC_ULLRAM_BANK1576_DATA_W 32 +#define RFC_ULLRAM_BANK1576_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1576_DATA_S 0 //***************************************************************************** // @@ -13119,9 +13119,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1577_DATA_W 32 -#define RFC_ULLRAM_BANK1577_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1577_DATA_S 0 +#define RFC_ULLRAM_BANK1577_DATA_W 32 +#define RFC_ULLRAM_BANK1577_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1577_DATA_S 0 //***************************************************************************** // @@ -13131,9 +13131,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1578_DATA_W 32 -#define RFC_ULLRAM_BANK1578_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1578_DATA_S 0 +#define RFC_ULLRAM_BANK1578_DATA_W 32 +#define RFC_ULLRAM_BANK1578_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1578_DATA_S 0 //***************************************************************************** // @@ -13143,9 +13143,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1579_DATA_W 32 -#define RFC_ULLRAM_BANK1579_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1579_DATA_S 0 +#define RFC_ULLRAM_BANK1579_DATA_W 32 +#define RFC_ULLRAM_BANK1579_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1579_DATA_S 0 //***************************************************************************** // @@ -13155,9 +13155,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1580_DATA_W 32 -#define RFC_ULLRAM_BANK1580_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1580_DATA_S 0 +#define RFC_ULLRAM_BANK1580_DATA_W 32 +#define RFC_ULLRAM_BANK1580_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1580_DATA_S 0 //***************************************************************************** // @@ -13167,9 +13167,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1581_DATA_W 32 -#define RFC_ULLRAM_BANK1581_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1581_DATA_S 0 +#define RFC_ULLRAM_BANK1581_DATA_W 32 +#define RFC_ULLRAM_BANK1581_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1581_DATA_S 0 //***************************************************************************** // @@ -13179,9 +13179,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1582_DATA_W 32 -#define RFC_ULLRAM_BANK1582_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1582_DATA_S 0 +#define RFC_ULLRAM_BANK1582_DATA_W 32 +#define RFC_ULLRAM_BANK1582_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1582_DATA_S 0 //***************************************************************************** // @@ -13191,9 +13191,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1583_DATA_W 32 -#define RFC_ULLRAM_BANK1583_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1583_DATA_S 0 +#define RFC_ULLRAM_BANK1583_DATA_W 32 +#define RFC_ULLRAM_BANK1583_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1583_DATA_S 0 //***************************************************************************** // @@ -13203,9 +13203,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1584_DATA_W 32 -#define RFC_ULLRAM_BANK1584_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1584_DATA_S 0 +#define RFC_ULLRAM_BANK1584_DATA_W 32 +#define RFC_ULLRAM_BANK1584_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1584_DATA_S 0 //***************************************************************************** // @@ -13215,9 +13215,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1585_DATA_W 32 -#define RFC_ULLRAM_BANK1585_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1585_DATA_S 0 +#define RFC_ULLRAM_BANK1585_DATA_W 32 +#define RFC_ULLRAM_BANK1585_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1585_DATA_S 0 //***************************************************************************** // @@ -13227,9 +13227,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1586_DATA_W 32 -#define RFC_ULLRAM_BANK1586_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1586_DATA_S 0 +#define RFC_ULLRAM_BANK1586_DATA_W 32 +#define RFC_ULLRAM_BANK1586_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1586_DATA_S 0 //***************************************************************************** // @@ -13239,9 +13239,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1587_DATA_W 32 -#define RFC_ULLRAM_BANK1587_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1587_DATA_S 0 +#define RFC_ULLRAM_BANK1587_DATA_W 32 +#define RFC_ULLRAM_BANK1587_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1587_DATA_S 0 //***************************************************************************** // @@ -13251,9 +13251,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1588_DATA_W 32 -#define RFC_ULLRAM_BANK1588_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1588_DATA_S 0 +#define RFC_ULLRAM_BANK1588_DATA_W 32 +#define RFC_ULLRAM_BANK1588_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1588_DATA_S 0 //***************************************************************************** // @@ -13263,9 +13263,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1589_DATA_W 32 -#define RFC_ULLRAM_BANK1589_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1589_DATA_S 0 +#define RFC_ULLRAM_BANK1589_DATA_W 32 +#define RFC_ULLRAM_BANK1589_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1589_DATA_S 0 //***************************************************************************** // @@ -13275,9 +13275,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1590_DATA_W 32 -#define RFC_ULLRAM_BANK1590_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1590_DATA_S 0 +#define RFC_ULLRAM_BANK1590_DATA_W 32 +#define RFC_ULLRAM_BANK1590_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1590_DATA_S 0 //***************************************************************************** // @@ -13287,9 +13287,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1591_DATA_W 32 -#define RFC_ULLRAM_BANK1591_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1591_DATA_S 0 +#define RFC_ULLRAM_BANK1591_DATA_W 32 +#define RFC_ULLRAM_BANK1591_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1591_DATA_S 0 //***************************************************************************** // @@ -13299,9 +13299,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1592_DATA_W 32 -#define RFC_ULLRAM_BANK1592_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1592_DATA_S 0 +#define RFC_ULLRAM_BANK1592_DATA_W 32 +#define RFC_ULLRAM_BANK1592_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1592_DATA_S 0 //***************************************************************************** // @@ -13311,9 +13311,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1593_DATA_W 32 -#define RFC_ULLRAM_BANK1593_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1593_DATA_S 0 +#define RFC_ULLRAM_BANK1593_DATA_W 32 +#define RFC_ULLRAM_BANK1593_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1593_DATA_S 0 //***************************************************************************** // @@ -13323,9 +13323,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1594_DATA_W 32 -#define RFC_ULLRAM_BANK1594_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1594_DATA_S 0 +#define RFC_ULLRAM_BANK1594_DATA_W 32 +#define RFC_ULLRAM_BANK1594_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1594_DATA_S 0 //***************************************************************************** // @@ -13335,9 +13335,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1595_DATA_W 32 -#define RFC_ULLRAM_BANK1595_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1595_DATA_S 0 +#define RFC_ULLRAM_BANK1595_DATA_W 32 +#define RFC_ULLRAM_BANK1595_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1595_DATA_S 0 //***************************************************************************** // @@ -13347,9 +13347,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1596_DATA_W 32 -#define RFC_ULLRAM_BANK1596_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1596_DATA_S 0 +#define RFC_ULLRAM_BANK1596_DATA_W 32 +#define RFC_ULLRAM_BANK1596_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1596_DATA_S 0 //***************************************************************************** // @@ -13359,9 +13359,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1597_DATA_W 32 -#define RFC_ULLRAM_BANK1597_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1597_DATA_S 0 +#define RFC_ULLRAM_BANK1597_DATA_W 32 +#define RFC_ULLRAM_BANK1597_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1597_DATA_S 0 //***************************************************************************** // @@ -13371,9 +13371,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1598_DATA_W 32 -#define RFC_ULLRAM_BANK1598_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1598_DATA_S 0 +#define RFC_ULLRAM_BANK1598_DATA_W 32 +#define RFC_ULLRAM_BANK1598_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1598_DATA_S 0 //***************************************************************************** // @@ -13383,9 +13383,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1599_DATA_W 32 -#define RFC_ULLRAM_BANK1599_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1599_DATA_S 0 +#define RFC_ULLRAM_BANK1599_DATA_W 32 +#define RFC_ULLRAM_BANK1599_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1599_DATA_S 0 //***************************************************************************** // @@ -13395,9 +13395,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1600_DATA_W 32 -#define RFC_ULLRAM_BANK1600_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1600_DATA_S 0 +#define RFC_ULLRAM_BANK1600_DATA_W 32 +#define RFC_ULLRAM_BANK1600_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1600_DATA_S 0 //***************************************************************************** // @@ -13407,9 +13407,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1601_DATA_W 32 -#define RFC_ULLRAM_BANK1601_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1601_DATA_S 0 +#define RFC_ULLRAM_BANK1601_DATA_W 32 +#define RFC_ULLRAM_BANK1601_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1601_DATA_S 0 //***************************************************************************** // @@ -13419,9 +13419,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1602_DATA_W 32 -#define RFC_ULLRAM_BANK1602_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1602_DATA_S 0 +#define RFC_ULLRAM_BANK1602_DATA_W 32 +#define RFC_ULLRAM_BANK1602_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1602_DATA_S 0 //***************************************************************************** // @@ -13431,9 +13431,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1603_DATA_W 32 -#define RFC_ULLRAM_BANK1603_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1603_DATA_S 0 +#define RFC_ULLRAM_BANK1603_DATA_W 32 +#define RFC_ULLRAM_BANK1603_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1603_DATA_S 0 //***************************************************************************** // @@ -13443,9 +13443,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1604_DATA_W 32 -#define RFC_ULLRAM_BANK1604_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1604_DATA_S 0 +#define RFC_ULLRAM_BANK1604_DATA_W 32 +#define RFC_ULLRAM_BANK1604_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1604_DATA_S 0 //***************************************************************************** // @@ -13455,9 +13455,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1605_DATA_W 32 -#define RFC_ULLRAM_BANK1605_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1605_DATA_S 0 +#define RFC_ULLRAM_BANK1605_DATA_W 32 +#define RFC_ULLRAM_BANK1605_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1605_DATA_S 0 //***************************************************************************** // @@ -13467,9 +13467,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1606_DATA_W 32 -#define RFC_ULLRAM_BANK1606_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1606_DATA_S 0 +#define RFC_ULLRAM_BANK1606_DATA_W 32 +#define RFC_ULLRAM_BANK1606_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1606_DATA_S 0 //***************************************************************************** // @@ -13479,9 +13479,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1607_DATA_W 32 -#define RFC_ULLRAM_BANK1607_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1607_DATA_S 0 +#define RFC_ULLRAM_BANK1607_DATA_W 32 +#define RFC_ULLRAM_BANK1607_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1607_DATA_S 0 //***************************************************************************** // @@ -13491,9 +13491,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1608_DATA_W 32 -#define RFC_ULLRAM_BANK1608_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1608_DATA_S 0 +#define RFC_ULLRAM_BANK1608_DATA_W 32 +#define RFC_ULLRAM_BANK1608_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1608_DATA_S 0 //***************************************************************************** // @@ -13503,9 +13503,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1609_DATA_W 32 -#define RFC_ULLRAM_BANK1609_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1609_DATA_S 0 +#define RFC_ULLRAM_BANK1609_DATA_W 32 +#define RFC_ULLRAM_BANK1609_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1609_DATA_S 0 //***************************************************************************** // @@ -13515,9 +13515,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1610_DATA_W 32 -#define RFC_ULLRAM_BANK1610_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1610_DATA_S 0 +#define RFC_ULLRAM_BANK1610_DATA_W 32 +#define RFC_ULLRAM_BANK1610_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1610_DATA_S 0 //***************************************************************************** // @@ -13527,9 +13527,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1611_DATA_W 32 -#define RFC_ULLRAM_BANK1611_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1611_DATA_S 0 +#define RFC_ULLRAM_BANK1611_DATA_W 32 +#define RFC_ULLRAM_BANK1611_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1611_DATA_S 0 //***************************************************************************** // @@ -13539,9 +13539,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1612_DATA_W 32 -#define RFC_ULLRAM_BANK1612_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1612_DATA_S 0 +#define RFC_ULLRAM_BANK1612_DATA_W 32 +#define RFC_ULLRAM_BANK1612_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1612_DATA_S 0 //***************************************************************************** // @@ -13551,9 +13551,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1613_DATA_W 32 -#define RFC_ULLRAM_BANK1613_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1613_DATA_S 0 +#define RFC_ULLRAM_BANK1613_DATA_W 32 +#define RFC_ULLRAM_BANK1613_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1613_DATA_S 0 //***************************************************************************** // @@ -13563,9 +13563,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1614_DATA_W 32 -#define RFC_ULLRAM_BANK1614_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1614_DATA_S 0 +#define RFC_ULLRAM_BANK1614_DATA_W 32 +#define RFC_ULLRAM_BANK1614_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1614_DATA_S 0 //***************************************************************************** // @@ -13575,9 +13575,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1615_DATA_W 32 -#define RFC_ULLRAM_BANK1615_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1615_DATA_S 0 +#define RFC_ULLRAM_BANK1615_DATA_W 32 +#define RFC_ULLRAM_BANK1615_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1615_DATA_S 0 //***************************************************************************** // @@ -13587,9 +13587,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1616_DATA_W 32 -#define RFC_ULLRAM_BANK1616_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1616_DATA_S 0 +#define RFC_ULLRAM_BANK1616_DATA_W 32 +#define RFC_ULLRAM_BANK1616_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1616_DATA_S 0 //***************************************************************************** // @@ -13599,9 +13599,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1617_DATA_W 32 -#define RFC_ULLRAM_BANK1617_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1617_DATA_S 0 +#define RFC_ULLRAM_BANK1617_DATA_W 32 +#define RFC_ULLRAM_BANK1617_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1617_DATA_S 0 //***************************************************************************** // @@ -13611,9 +13611,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1618_DATA_W 32 -#define RFC_ULLRAM_BANK1618_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1618_DATA_S 0 +#define RFC_ULLRAM_BANK1618_DATA_W 32 +#define RFC_ULLRAM_BANK1618_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1618_DATA_S 0 //***************************************************************************** // @@ -13623,9 +13623,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1619_DATA_W 32 -#define RFC_ULLRAM_BANK1619_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1619_DATA_S 0 +#define RFC_ULLRAM_BANK1619_DATA_W 32 +#define RFC_ULLRAM_BANK1619_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1619_DATA_S 0 //***************************************************************************** // @@ -13635,9 +13635,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1620_DATA_W 32 -#define RFC_ULLRAM_BANK1620_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1620_DATA_S 0 +#define RFC_ULLRAM_BANK1620_DATA_W 32 +#define RFC_ULLRAM_BANK1620_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1620_DATA_S 0 //***************************************************************************** // @@ -13647,9 +13647,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1621_DATA_W 32 -#define RFC_ULLRAM_BANK1621_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1621_DATA_S 0 +#define RFC_ULLRAM_BANK1621_DATA_W 32 +#define RFC_ULLRAM_BANK1621_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1621_DATA_S 0 //***************************************************************************** // @@ -13659,9 +13659,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1622_DATA_W 32 -#define RFC_ULLRAM_BANK1622_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1622_DATA_S 0 +#define RFC_ULLRAM_BANK1622_DATA_W 32 +#define RFC_ULLRAM_BANK1622_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1622_DATA_S 0 //***************************************************************************** // @@ -13671,9 +13671,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1623_DATA_W 32 -#define RFC_ULLRAM_BANK1623_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1623_DATA_S 0 +#define RFC_ULLRAM_BANK1623_DATA_W 32 +#define RFC_ULLRAM_BANK1623_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1623_DATA_S 0 //***************************************************************************** // @@ -13683,9 +13683,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1624_DATA_W 32 -#define RFC_ULLRAM_BANK1624_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1624_DATA_S 0 +#define RFC_ULLRAM_BANK1624_DATA_W 32 +#define RFC_ULLRAM_BANK1624_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1624_DATA_S 0 //***************************************************************************** // @@ -13695,9 +13695,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1625_DATA_W 32 -#define RFC_ULLRAM_BANK1625_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1625_DATA_S 0 +#define RFC_ULLRAM_BANK1625_DATA_W 32 +#define RFC_ULLRAM_BANK1625_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1625_DATA_S 0 //***************************************************************************** // @@ -13707,9 +13707,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1626_DATA_W 32 -#define RFC_ULLRAM_BANK1626_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1626_DATA_S 0 +#define RFC_ULLRAM_BANK1626_DATA_W 32 +#define RFC_ULLRAM_BANK1626_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1626_DATA_S 0 //***************************************************************************** // @@ -13719,9 +13719,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1627_DATA_W 32 -#define RFC_ULLRAM_BANK1627_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1627_DATA_S 0 +#define RFC_ULLRAM_BANK1627_DATA_W 32 +#define RFC_ULLRAM_BANK1627_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1627_DATA_S 0 //***************************************************************************** // @@ -13731,9 +13731,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1628_DATA_W 32 -#define RFC_ULLRAM_BANK1628_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1628_DATA_S 0 +#define RFC_ULLRAM_BANK1628_DATA_W 32 +#define RFC_ULLRAM_BANK1628_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1628_DATA_S 0 //***************************************************************************** // @@ -13743,9 +13743,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1629_DATA_W 32 -#define RFC_ULLRAM_BANK1629_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1629_DATA_S 0 +#define RFC_ULLRAM_BANK1629_DATA_W 32 +#define RFC_ULLRAM_BANK1629_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1629_DATA_S 0 //***************************************************************************** // @@ -13755,9 +13755,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1630_DATA_W 32 -#define RFC_ULLRAM_BANK1630_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1630_DATA_S 0 +#define RFC_ULLRAM_BANK1630_DATA_W 32 +#define RFC_ULLRAM_BANK1630_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1630_DATA_S 0 //***************************************************************************** // @@ -13767,9 +13767,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1631_DATA_W 32 -#define RFC_ULLRAM_BANK1631_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1631_DATA_S 0 +#define RFC_ULLRAM_BANK1631_DATA_W 32 +#define RFC_ULLRAM_BANK1631_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1631_DATA_S 0 //***************************************************************************** // @@ -13779,9 +13779,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1632_DATA_W 32 -#define RFC_ULLRAM_BANK1632_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1632_DATA_S 0 +#define RFC_ULLRAM_BANK1632_DATA_W 32 +#define RFC_ULLRAM_BANK1632_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1632_DATA_S 0 //***************************************************************************** // @@ -13791,9 +13791,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1633_DATA_W 32 -#define RFC_ULLRAM_BANK1633_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1633_DATA_S 0 +#define RFC_ULLRAM_BANK1633_DATA_W 32 +#define RFC_ULLRAM_BANK1633_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1633_DATA_S 0 //***************************************************************************** // @@ -13803,9 +13803,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1634_DATA_W 32 -#define RFC_ULLRAM_BANK1634_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1634_DATA_S 0 +#define RFC_ULLRAM_BANK1634_DATA_W 32 +#define RFC_ULLRAM_BANK1634_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1634_DATA_S 0 //***************************************************************************** // @@ -13815,9 +13815,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1635_DATA_W 32 -#define RFC_ULLRAM_BANK1635_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1635_DATA_S 0 +#define RFC_ULLRAM_BANK1635_DATA_W 32 +#define RFC_ULLRAM_BANK1635_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1635_DATA_S 0 //***************************************************************************** // @@ -13827,9 +13827,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1636_DATA_W 32 -#define RFC_ULLRAM_BANK1636_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1636_DATA_S 0 +#define RFC_ULLRAM_BANK1636_DATA_W 32 +#define RFC_ULLRAM_BANK1636_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1636_DATA_S 0 //***************************************************************************** // @@ -13839,9 +13839,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1637_DATA_W 32 -#define RFC_ULLRAM_BANK1637_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1637_DATA_S 0 +#define RFC_ULLRAM_BANK1637_DATA_W 32 +#define RFC_ULLRAM_BANK1637_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1637_DATA_S 0 //***************************************************************************** // @@ -13851,9 +13851,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1638_DATA_W 32 -#define RFC_ULLRAM_BANK1638_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1638_DATA_S 0 +#define RFC_ULLRAM_BANK1638_DATA_W 32 +#define RFC_ULLRAM_BANK1638_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1638_DATA_S 0 //***************************************************************************** // @@ -13863,9 +13863,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1639_DATA_W 32 -#define RFC_ULLRAM_BANK1639_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1639_DATA_S 0 +#define RFC_ULLRAM_BANK1639_DATA_W 32 +#define RFC_ULLRAM_BANK1639_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1639_DATA_S 0 //***************************************************************************** // @@ -13875,9 +13875,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1640_DATA_W 32 -#define RFC_ULLRAM_BANK1640_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1640_DATA_S 0 +#define RFC_ULLRAM_BANK1640_DATA_W 32 +#define RFC_ULLRAM_BANK1640_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1640_DATA_S 0 //***************************************************************************** // @@ -13887,9 +13887,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1641_DATA_W 32 -#define RFC_ULLRAM_BANK1641_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1641_DATA_S 0 +#define RFC_ULLRAM_BANK1641_DATA_W 32 +#define RFC_ULLRAM_BANK1641_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1641_DATA_S 0 //***************************************************************************** // @@ -13899,9 +13899,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1642_DATA_W 32 -#define RFC_ULLRAM_BANK1642_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1642_DATA_S 0 +#define RFC_ULLRAM_BANK1642_DATA_W 32 +#define RFC_ULLRAM_BANK1642_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1642_DATA_S 0 //***************************************************************************** // @@ -13911,9 +13911,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1643_DATA_W 32 -#define RFC_ULLRAM_BANK1643_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1643_DATA_S 0 +#define RFC_ULLRAM_BANK1643_DATA_W 32 +#define RFC_ULLRAM_BANK1643_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1643_DATA_S 0 //***************************************************************************** // @@ -13923,9 +13923,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1644_DATA_W 32 -#define RFC_ULLRAM_BANK1644_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1644_DATA_S 0 +#define RFC_ULLRAM_BANK1644_DATA_W 32 +#define RFC_ULLRAM_BANK1644_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1644_DATA_S 0 //***************************************************************************** // @@ -13935,9 +13935,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1645_DATA_W 32 -#define RFC_ULLRAM_BANK1645_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1645_DATA_S 0 +#define RFC_ULLRAM_BANK1645_DATA_W 32 +#define RFC_ULLRAM_BANK1645_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1645_DATA_S 0 //***************************************************************************** // @@ -13947,9 +13947,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1646_DATA_W 32 -#define RFC_ULLRAM_BANK1646_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1646_DATA_S 0 +#define RFC_ULLRAM_BANK1646_DATA_W 32 +#define RFC_ULLRAM_BANK1646_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1646_DATA_S 0 //***************************************************************************** // @@ -13959,9 +13959,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1647_DATA_W 32 -#define RFC_ULLRAM_BANK1647_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1647_DATA_S 0 +#define RFC_ULLRAM_BANK1647_DATA_W 32 +#define RFC_ULLRAM_BANK1647_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1647_DATA_S 0 //***************************************************************************** // @@ -13971,9 +13971,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1648_DATA_W 32 -#define RFC_ULLRAM_BANK1648_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1648_DATA_S 0 +#define RFC_ULLRAM_BANK1648_DATA_W 32 +#define RFC_ULLRAM_BANK1648_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1648_DATA_S 0 //***************************************************************************** // @@ -13983,9 +13983,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1649_DATA_W 32 -#define RFC_ULLRAM_BANK1649_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1649_DATA_S 0 +#define RFC_ULLRAM_BANK1649_DATA_W 32 +#define RFC_ULLRAM_BANK1649_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1649_DATA_S 0 //***************************************************************************** // @@ -13995,9 +13995,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1650_DATA_W 32 -#define RFC_ULLRAM_BANK1650_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1650_DATA_S 0 +#define RFC_ULLRAM_BANK1650_DATA_W 32 +#define RFC_ULLRAM_BANK1650_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1650_DATA_S 0 //***************************************************************************** // @@ -14007,9 +14007,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1651_DATA_W 32 -#define RFC_ULLRAM_BANK1651_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1651_DATA_S 0 +#define RFC_ULLRAM_BANK1651_DATA_W 32 +#define RFC_ULLRAM_BANK1651_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1651_DATA_S 0 //***************************************************************************** // @@ -14019,9 +14019,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1652_DATA_W 32 -#define RFC_ULLRAM_BANK1652_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1652_DATA_S 0 +#define RFC_ULLRAM_BANK1652_DATA_W 32 +#define RFC_ULLRAM_BANK1652_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1652_DATA_S 0 //***************************************************************************** // @@ -14031,9 +14031,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1653_DATA_W 32 -#define RFC_ULLRAM_BANK1653_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1653_DATA_S 0 +#define RFC_ULLRAM_BANK1653_DATA_W 32 +#define RFC_ULLRAM_BANK1653_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1653_DATA_S 0 //***************************************************************************** // @@ -14043,9 +14043,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1654_DATA_W 32 -#define RFC_ULLRAM_BANK1654_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1654_DATA_S 0 +#define RFC_ULLRAM_BANK1654_DATA_W 32 +#define RFC_ULLRAM_BANK1654_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1654_DATA_S 0 //***************************************************************************** // @@ -14055,9 +14055,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1655_DATA_W 32 -#define RFC_ULLRAM_BANK1655_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1655_DATA_S 0 +#define RFC_ULLRAM_BANK1655_DATA_W 32 +#define RFC_ULLRAM_BANK1655_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1655_DATA_S 0 //***************************************************************************** // @@ -14067,9 +14067,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1656_DATA_W 32 -#define RFC_ULLRAM_BANK1656_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1656_DATA_S 0 +#define RFC_ULLRAM_BANK1656_DATA_W 32 +#define RFC_ULLRAM_BANK1656_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1656_DATA_S 0 //***************************************************************************** // @@ -14079,9 +14079,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1657_DATA_W 32 -#define RFC_ULLRAM_BANK1657_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1657_DATA_S 0 +#define RFC_ULLRAM_BANK1657_DATA_W 32 +#define RFC_ULLRAM_BANK1657_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1657_DATA_S 0 //***************************************************************************** // @@ -14091,9 +14091,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1658_DATA_W 32 -#define RFC_ULLRAM_BANK1658_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1658_DATA_S 0 +#define RFC_ULLRAM_BANK1658_DATA_W 32 +#define RFC_ULLRAM_BANK1658_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1658_DATA_S 0 //***************************************************************************** // @@ -14103,9 +14103,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1659_DATA_W 32 -#define RFC_ULLRAM_BANK1659_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1659_DATA_S 0 +#define RFC_ULLRAM_BANK1659_DATA_W 32 +#define RFC_ULLRAM_BANK1659_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1659_DATA_S 0 //***************************************************************************** // @@ -14115,9 +14115,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1660_DATA_W 32 -#define RFC_ULLRAM_BANK1660_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1660_DATA_S 0 +#define RFC_ULLRAM_BANK1660_DATA_W 32 +#define RFC_ULLRAM_BANK1660_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1660_DATA_S 0 //***************************************************************************** // @@ -14127,9 +14127,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1661_DATA_W 32 -#define RFC_ULLRAM_BANK1661_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1661_DATA_S 0 +#define RFC_ULLRAM_BANK1661_DATA_W 32 +#define RFC_ULLRAM_BANK1661_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1661_DATA_S 0 //***************************************************************************** // @@ -14139,9 +14139,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1662_DATA_W 32 -#define RFC_ULLRAM_BANK1662_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1662_DATA_S 0 +#define RFC_ULLRAM_BANK1662_DATA_W 32 +#define RFC_ULLRAM_BANK1662_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1662_DATA_S 0 //***************************************************************************** // @@ -14151,9 +14151,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1663_DATA_W 32 -#define RFC_ULLRAM_BANK1663_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1663_DATA_S 0 +#define RFC_ULLRAM_BANK1663_DATA_W 32 +#define RFC_ULLRAM_BANK1663_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1663_DATA_S 0 //***************************************************************************** // @@ -14163,9 +14163,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1664_DATA_W 32 -#define RFC_ULLRAM_BANK1664_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1664_DATA_S 0 +#define RFC_ULLRAM_BANK1664_DATA_W 32 +#define RFC_ULLRAM_BANK1664_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1664_DATA_S 0 //***************************************************************************** // @@ -14175,9 +14175,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1665_DATA_W 32 -#define RFC_ULLRAM_BANK1665_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1665_DATA_S 0 +#define RFC_ULLRAM_BANK1665_DATA_W 32 +#define RFC_ULLRAM_BANK1665_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1665_DATA_S 0 //***************************************************************************** // @@ -14187,9 +14187,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1666_DATA_W 32 -#define RFC_ULLRAM_BANK1666_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1666_DATA_S 0 +#define RFC_ULLRAM_BANK1666_DATA_W 32 +#define RFC_ULLRAM_BANK1666_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1666_DATA_S 0 //***************************************************************************** // @@ -14199,9 +14199,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1667_DATA_W 32 -#define RFC_ULLRAM_BANK1667_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1667_DATA_S 0 +#define RFC_ULLRAM_BANK1667_DATA_W 32 +#define RFC_ULLRAM_BANK1667_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1667_DATA_S 0 //***************************************************************************** // @@ -14211,9 +14211,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1668_DATA_W 32 -#define RFC_ULLRAM_BANK1668_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1668_DATA_S 0 +#define RFC_ULLRAM_BANK1668_DATA_W 32 +#define RFC_ULLRAM_BANK1668_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1668_DATA_S 0 //***************************************************************************** // @@ -14223,9 +14223,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1669_DATA_W 32 -#define RFC_ULLRAM_BANK1669_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1669_DATA_S 0 +#define RFC_ULLRAM_BANK1669_DATA_W 32 +#define RFC_ULLRAM_BANK1669_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1669_DATA_S 0 //***************************************************************************** // @@ -14235,9 +14235,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1670_DATA_W 32 -#define RFC_ULLRAM_BANK1670_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1670_DATA_S 0 +#define RFC_ULLRAM_BANK1670_DATA_W 32 +#define RFC_ULLRAM_BANK1670_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1670_DATA_S 0 //***************************************************************************** // @@ -14247,9 +14247,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1671_DATA_W 32 -#define RFC_ULLRAM_BANK1671_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1671_DATA_S 0 +#define RFC_ULLRAM_BANK1671_DATA_W 32 +#define RFC_ULLRAM_BANK1671_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1671_DATA_S 0 //***************************************************************************** // @@ -14259,9 +14259,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1672_DATA_W 32 -#define RFC_ULLRAM_BANK1672_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1672_DATA_S 0 +#define RFC_ULLRAM_BANK1672_DATA_W 32 +#define RFC_ULLRAM_BANK1672_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1672_DATA_S 0 //***************************************************************************** // @@ -14271,9 +14271,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1673_DATA_W 32 -#define RFC_ULLRAM_BANK1673_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1673_DATA_S 0 +#define RFC_ULLRAM_BANK1673_DATA_W 32 +#define RFC_ULLRAM_BANK1673_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1673_DATA_S 0 //***************************************************************************** // @@ -14283,9 +14283,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1674_DATA_W 32 -#define RFC_ULLRAM_BANK1674_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1674_DATA_S 0 +#define RFC_ULLRAM_BANK1674_DATA_W 32 +#define RFC_ULLRAM_BANK1674_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1674_DATA_S 0 //***************************************************************************** // @@ -14295,9 +14295,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1675_DATA_W 32 -#define RFC_ULLRAM_BANK1675_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1675_DATA_S 0 +#define RFC_ULLRAM_BANK1675_DATA_W 32 +#define RFC_ULLRAM_BANK1675_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1675_DATA_S 0 //***************************************************************************** // @@ -14307,9 +14307,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1676_DATA_W 32 -#define RFC_ULLRAM_BANK1676_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1676_DATA_S 0 +#define RFC_ULLRAM_BANK1676_DATA_W 32 +#define RFC_ULLRAM_BANK1676_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1676_DATA_S 0 //***************************************************************************** // @@ -14319,9 +14319,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1677_DATA_W 32 -#define RFC_ULLRAM_BANK1677_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1677_DATA_S 0 +#define RFC_ULLRAM_BANK1677_DATA_W 32 +#define RFC_ULLRAM_BANK1677_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1677_DATA_S 0 //***************************************************************************** // @@ -14331,9 +14331,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1678_DATA_W 32 -#define RFC_ULLRAM_BANK1678_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1678_DATA_S 0 +#define RFC_ULLRAM_BANK1678_DATA_W 32 +#define RFC_ULLRAM_BANK1678_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1678_DATA_S 0 //***************************************************************************** // @@ -14343,9 +14343,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1679_DATA_W 32 -#define RFC_ULLRAM_BANK1679_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1679_DATA_S 0 +#define RFC_ULLRAM_BANK1679_DATA_W 32 +#define RFC_ULLRAM_BANK1679_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1679_DATA_S 0 //***************************************************************************** // @@ -14355,9 +14355,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1680_DATA_W 32 -#define RFC_ULLRAM_BANK1680_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1680_DATA_S 0 +#define RFC_ULLRAM_BANK1680_DATA_W 32 +#define RFC_ULLRAM_BANK1680_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1680_DATA_S 0 //***************************************************************************** // @@ -14367,9 +14367,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1681_DATA_W 32 -#define RFC_ULLRAM_BANK1681_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1681_DATA_S 0 +#define RFC_ULLRAM_BANK1681_DATA_W 32 +#define RFC_ULLRAM_BANK1681_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1681_DATA_S 0 //***************************************************************************** // @@ -14379,9 +14379,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1682_DATA_W 32 -#define RFC_ULLRAM_BANK1682_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1682_DATA_S 0 +#define RFC_ULLRAM_BANK1682_DATA_W 32 +#define RFC_ULLRAM_BANK1682_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1682_DATA_S 0 //***************************************************************************** // @@ -14391,9 +14391,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1683_DATA_W 32 -#define RFC_ULLRAM_BANK1683_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1683_DATA_S 0 +#define RFC_ULLRAM_BANK1683_DATA_W 32 +#define RFC_ULLRAM_BANK1683_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1683_DATA_S 0 //***************************************************************************** // @@ -14403,9 +14403,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1684_DATA_W 32 -#define RFC_ULLRAM_BANK1684_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1684_DATA_S 0 +#define RFC_ULLRAM_BANK1684_DATA_W 32 +#define RFC_ULLRAM_BANK1684_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1684_DATA_S 0 //***************************************************************************** // @@ -14415,9 +14415,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1685_DATA_W 32 -#define RFC_ULLRAM_BANK1685_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1685_DATA_S 0 +#define RFC_ULLRAM_BANK1685_DATA_W 32 +#define RFC_ULLRAM_BANK1685_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1685_DATA_S 0 //***************************************************************************** // @@ -14427,9 +14427,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1686_DATA_W 32 -#define RFC_ULLRAM_BANK1686_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1686_DATA_S 0 +#define RFC_ULLRAM_BANK1686_DATA_W 32 +#define RFC_ULLRAM_BANK1686_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1686_DATA_S 0 //***************************************************************************** // @@ -14439,9 +14439,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1687_DATA_W 32 -#define RFC_ULLRAM_BANK1687_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1687_DATA_S 0 +#define RFC_ULLRAM_BANK1687_DATA_W 32 +#define RFC_ULLRAM_BANK1687_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1687_DATA_S 0 //***************************************************************************** // @@ -14451,9 +14451,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1688_DATA_W 32 -#define RFC_ULLRAM_BANK1688_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1688_DATA_S 0 +#define RFC_ULLRAM_BANK1688_DATA_W 32 +#define RFC_ULLRAM_BANK1688_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1688_DATA_S 0 //***************************************************************************** // @@ -14463,9 +14463,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1689_DATA_W 32 -#define RFC_ULLRAM_BANK1689_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1689_DATA_S 0 +#define RFC_ULLRAM_BANK1689_DATA_W 32 +#define RFC_ULLRAM_BANK1689_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1689_DATA_S 0 //***************************************************************************** // @@ -14475,9 +14475,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1690_DATA_W 32 -#define RFC_ULLRAM_BANK1690_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1690_DATA_S 0 +#define RFC_ULLRAM_BANK1690_DATA_W 32 +#define RFC_ULLRAM_BANK1690_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1690_DATA_S 0 //***************************************************************************** // @@ -14487,9 +14487,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1691_DATA_W 32 -#define RFC_ULLRAM_BANK1691_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1691_DATA_S 0 +#define RFC_ULLRAM_BANK1691_DATA_W 32 +#define RFC_ULLRAM_BANK1691_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1691_DATA_S 0 //***************************************************************************** // @@ -14499,9 +14499,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1692_DATA_W 32 -#define RFC_ULLRAM_BANK1692_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1692_DATA_S 0 +#define RFC_ULLRAM_BANK1692_DATA_W 32 +#define RFC_ULLRAM_BANK1692_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1692_DATA_S 0 //***************************************************************************** // @@ -14511,9 +14511,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1693_DATA_W 32 -#define RFC_ULLRAM_BANK1693_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1693_DATA_S 0 +#define RFC_ULLRAM_BANK1693_DATA_W 32 +#define RFC_ULLRAM_BANK1693_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1693_DATA_S 0 //***************************************************************************** // @@ -14523,9 +14523,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1694_DATA_W 32 -#define RFC_ULLRAM_BANK1694_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1694_DATA_S 0 +#define RFC_ULLRAM_BANK1694_DATA_W 32 +#define RFC_ULLRAM_BANK1694_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1694_DATA_S 0 //***************************************************************************** // @@ -14535,9 +14535,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1695_DATA_W 32 -#define RFC_ULLRAM_BANK1695_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1695_DATA_S 0 +#define RFC_ULLRAM_BANK1695_DATA_W 32 +#define RFC_ULLRAM_BANK1695_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1695_DATA_S 0 //***************************************************************************** // @@ -14547,9 +14547,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1696_DATA_W 32 -#define RFC_ULLRAM_BANK1696_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1696_DATA_S 0 +#define RFC_ULLRAM_BANK1696_DATA_W 32 +#define RFC_ULLRAM_BANK1696_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1696_DATA_S 0 //***************************************************************************** // @@ -14559,9 +14559,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1697_DATA_W 32 -#define RFC_ULLRAM_BANK1697_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1697_DATA_S 0 +#define RFC_ULLRAM_BANK1697_DATA_W 32 +#define RFC_ULLRAM_BANK1697_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1697_DATA_S 0 //***************************************************************************** // @@ -14571,9 +14571,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1698_DATA_W 32 -#define RFC_ULLRAM_BANK1698_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1698_DATA_S 0 +#define RFC_ULLRAM_BANK1698_DATA_W 32 +#define RFC_ULLRAM_BANK1698_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1698_DATA_S 0 //***************************************************************************** // @@ -14583,9 +14583,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1699_DATA_W 32 -#define RFC_ULLRAM_BANK1699_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1699_DATA_S 0 +#define RFC_ULLRAM_BANK1699_DATA_W 32 +#define RFC_ULLRAM_BANK1699_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1699_DATA_S 0 //***************************************************************************** // @@ -14595,9 +14595,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1700_DATA_W 32 -#define RFC_ULLRAM_BANK1700_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1700_DATA_S 0 +#define RFC_ULLRAM_BANK1700_DATA_W 32 +#define RFC_ULLRAM_BANK1700_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1700_DATA_S 0 //***************************************************************************** // @@ -14607,9 +14607,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1701_DATA_W 32 -#define RFC_ULLRAM_BANK1701_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1701_DATA_S 0 +#define RFC_ULLRAM_BANK1701_DATA_W 32 +#define RFC_ULLRAM_BANK1701_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1701_DATA_S 0 //***************************************************************************** // @@ -14619,9 +14619,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1702_DATA_W 32 -#define RFC_ULLRAM_BANK1702_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1702_DATA_S 0 +#define RFC_ULLRAM_BANK1702_DATA_W 32 +#define RFC_ULLRAM_BANK1702_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1702_DATA_S 0 //***************************************************************************** // @@ -14631,9 +14631,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1703_DATA_W 32 -#define RFC_ULLRAM_BANK1703_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1703_DATA_S 0 +#define RFC_ULLRAM_BANK1703_DATA_W 32 +#define RFC_ULLRAM_BANK1703_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1703_DATA_S 0 //***************************************************************************** // @@ -14643,9 +14643,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1704_DATA_W 32 -#define RFC_ULLRAM_BANK1704_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1704_DATA_S 0 +#define RFC_ULLRAM_BANK1704_DATA_W 32 +#define RFC_ULLRAM_BANK1704_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1704_DATA_S 0 //***************************************************************************** // @@ -14655,9 +14655,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1705_DATA_W 32 -#define RFC_ULLRAM_BANK1705_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1705_DATA_S 0 +#define RFC_ULLRAM_BANK1705_DATA_W 32 +#define RFC_ULLRAM_BANK1705_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1705_DATA_S 0 //***************************************************************************** // @@ -14667,9 +14667,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1706_DATA_W 32 -#define RFC_ULLRAM_BANK1706_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1706_DATA_S 0 +#define RFC_ULLRAM_BANK1706_DATA_W 32 +#define RFC_ULLRAM_BANK1706_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1706_DATA_S 0 //***************************************************************************** // @@ -14679,9 +14679,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1707_DATA_W 32 -#define RFC_ULLRAM_BANK1707_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1707_DATA_S 0 +#define RFC_ULLRAM_BANK1707_DATA_W 32 +#define RFC_ULLRAM_BANK1707_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1707_DATA_S 0 //***************************************************************************** // @@ -14691,9 +14691,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1708_DATA_W 32 -#define RFC_ULLRAM_BANK1708_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1708_DATA_S 0 +#define RFC_ULLRAM_BANK1708_DATA_W 32 +#define RFC_ULLRAM_BANK1708_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1708_DATA_S 0 //***************************************************************************** // @@ -14703,9 +14703,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1709_DATA_W 32 -#define RFC_ULLRAM_BANK1709_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1709_DATA_S 0 +#define RFC_ULLRAM_BANK1709_DATA_W 32 +#define RFC_ULLRAM_BANK1709_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1709_DATA_S 0 //***************************************************************************** // @@ -14715,9 +14715,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1710_DATA_W 32 -#define RFC_ULLRAM_BANK1710_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1710_DATA_S 0 +#define RFC_ULLRAM_BANK1710_DATA_W 32 +#define RFC_ULLRAM_BANK1710_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1710_DATA_S 0 //***************************************************************************** // @@ -14727,9 +14727,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1711_DATA_W 32 -#define RFC_ULLRAM_BANK1711_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1711_DATA_S 0 +#define RFC_ULLRAM_BANK1711_DATA_W 32 +#define RFC_ULLRAM_BANK1711_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1711_DATA_S 0 //***************************************************************************** // @@ -14739,9 +14739,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1712_DATA_W 32 -#define RFC_ULLRAM_BANK1712_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1712_DATA_S 0 +#define RFC_ULLRAM_BANK1712_DATA_W 32 +#define RFC_ULLRAM_BANK1712_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1712_DATA_S 0 //***************************************************************************** // @@ -14751,9 +14751,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1713_DATA_W 32 -#define RFC_ULLRAM_BANK1713_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1713_DATA_S 0 +#define RFC_ULLRAM_BANK1713_DATA_W 32 +#define RFC_ULLRAM_BANK1713_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1713_DATA_S 0 //***************************************************************************** // @@ -14763,9 +14763,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1714_DATA_W 32 -#define RFC_ULLRAM_BANK1714_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1714_DATA_S 0 +#define RFC_ULLRAM_BANK1714_DATA_W 32 +#define RFC_ULLRAM_BANK1714_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1714_DATA_S 0 //***************************************************************************** // @@ -14775,9 +14775,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1715_DATA_W 32 -#define RFC_ULLRAM_BANK1715_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1715_DATA_S 0 +#define RFC_ULLRAM_BANK1715_DATA_W 32 +#define RFC_ULLRAM_BANK1715_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1715_DATA_S 0 //***************************************************************************** // @@ -14787,9 +14787,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1716_DATA_W 32 -#define RFC_ULLRAM_BANK1716_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1716_DATA_S 0 +#define RFC_ULLRAM_BANK1716_DATA_W 32 +#define RFC_ULLRAM_BANK1716_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1716_DATA_S 0 //***************************************************************************** // @@ -14799,9 +14799,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1717_DATA_W 32 -#define RFC_ULLRAM_BANK1717_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1717_DATA_S 0 +#define RFC_ULLRAM_BANK1717_DATA_W 32 +#define RFC_ULLRAM_BANK1717_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1717_DATA_S 0 //***************************************************************************** // @@ -14811,9 +14811,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1718_DATA_W 32 -#define RFC_ULLRAM_BANK1718_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1718_DATA_S 0 +#define RFC_ULLRAM_BANK1718_DATA_W 32 +#define RFC_ULLRAM_BANK1718_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1718_DATA_S 0 //***************************************************************************** // @@ -14823,9 +14823,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1719_DATA_W 32 -#define RFC_ULLRAM_BANK1719_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1719_DATA_S 0 +#define RFC_ULLRAM_BANK1719_DATA_W 32 +#define RFC_ULLRAM_BANK1719_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1719_DATA_S 0 //***************************************************************************** // @@ -14835,9 +14835,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1720_DATA_W 32 -#define RFC_ULLRAM_BANK1720_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1720_DATA_S 0 +#define RFC_ULLRAM_BANK1720_DATA_W 32 +#define RFC_ULLRAM_BANK1720_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1720_DATA_S 0 //***************************************************************************** // @@ -14847,9 +14847,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1721_DATA_W 32 -#define RFC_ULLRAM_BANK1721_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1721_DATA_S 0 +#define RFC_ULLRAM_BANK1721_DATA_W 32 +#define RFC_ULLRAM_BANK1721_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1721_DATA_S 0 //***************************************************************************** // @@ -14859,9 +14859,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1722_DATA_W 32 -#define RFC_ULLRAM_BANK1722_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1722_DATA_S 0 +#define RFC_ULLRAM_BANK1722_DATA_W 32 +#define RFC_ULLRAM_BANK1722_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1722_DATA_S 0 //***************************************************************************** // @@ -14871,9 +14871,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1723_DATA_W 32 -#define RFC_ULLRAM_BANK1723_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1723_DATA_S 0 +#define RFC_ULLRAM_BANK1723_DATA_W 32 +#define RFC_ULLRAM_BANK1723_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1723_DATA_S 0 //***************************************************************************** // @@ -14883,9 +14883,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1724_DATA_W 32 -#define RFC_ULLRAM_BANK1724_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1724_DATA_S 0 +#define RFC_ULLRAM_BANK1724_DATA_W 32 +#define RFC_ULLRAM_BANK1724_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1724_DATA_S 0 //***************************************************************************** // @@ -14895,9 +14895,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1725_DATA_W 32 -#define RFC_ULLRAM_BANK1725_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1725_DATA_S 0 +#define RFC_ULLRAM_BANK1725_DATA_W 32 +#define RFC_ULLRAM_BANK1725_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1725_DATA_S 0 //***************************************************************************** // @@ -14907,9 +14907,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1726_DATA_W 32 -#define RFC_ULLRAM_BANK1726_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1726_DATA_S 0 +#define RFC_ULLRAM_BANK1726_DATA_W 32 +#define RFC_ULLRAM_BANK1726_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1726_DATA_S 0 //***************************************************************************** // @@ -14919,9 +14919,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1727_DATA_W 32 -#define RFC_ULLRAM_BANK1727_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1727_DATA_S 0 +#define RFC_ULLRAM_BANK1727_DATA_W 32 +#define RFC_ULLRAM_BANK1727_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1727_DATA_S 0 //***************************************************************************** // @@ -14931,9 +14931,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1728_DATA_W 32 -#define RFC_ULLRAM_BANK1728_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1728_DATA_S 0 +#define RFC_ULLRAM_BANK1728_DATA_W 32 +#define RFC_ULLRAM_BANK1728_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1728_DATA_S 0 //***************************************************************************** // @@ -14943,9 +14943,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1729_DATA_W 32 -#define RFC_ULLRAM_BANK1729_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1729_DATA_S 0 +#define RFC_ULLRAM_BANK1729_DATA_W 32 +#define RFC_ULLRAM_BANK1729_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1729_DATA_S 0 //***************************************************************************** // @@ -14955,9 +14955,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1730_DATA_W 32 -#define RFC_ULLRAM_BANK1730_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1730_DATA_S 0 +#define RFC_ULLRAM_BANK1730_DATA_W 32 +#define RFC_ULLRAM_BANK1730_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1730_DATA_S 0 //***************************************************************************** // @@ -14967,9 +14967,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1731_DATA_W 32 -#define RFC_ULLRAM_BANK1731_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1731_DATA_S 0 +#define RFC_ULLRAM_BANK1731_DATA_W 32 +#define RFC_ULLRAM_BANK1731_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1731_DATA_S 0 //***************************************************************************** // @@ -14979,9 +14979,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1732_DATA_W 32 -#define RFC_ULLRAM_BANK1732_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1732_DATA_S 0 +#define RFC_ULLRAM_BANK1732_DATA_W 32 +#define RFC_ULLRAM_BANK1732_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1732_DATA_S 0 //***************************************************************************** // @@ -14991,9 +14991,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1733_DATA_W 32 -#define RFC_ULLRAM_BANK1733_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1733_DATA_S 0 +#define RFC_ULLRAM_BANK1733_DATA_W 32 +#define RFC_ULLRAM_BANK1733_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1733_DATA_S 0 //***************************************************************************** // @@ -15003,9 +15003,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1734_DATA_W 32 -#define RFC_ULLRAM_BANK1734_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1734_DATA_S 0 +#define RFC_ULLRAM_BANK1734_DATA_W 32 +#define RFC_ULLRAM_BANK1734_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1734_DATA_S 0 //***************************************************************************** // @@ -15015,9 +15015,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1735_DATA_W 32 -#define RFC_ULLRAM_BANK1735_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1735_DATA_S 0 +#define RFC_ULLRAM_BANK1735_DATA_W 32 +#define RFC_ULLRAM_BANK1735_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1735_DATA_S 0 //***************************************************************************** // @@ -15027,9 +15027,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1736_DATA_W 32 -#define RFC_ULLRAM_BANK1736_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1736_DATA_S 0 +#define RFC_ULLRAM_BANK1736_DATA_W 32 +#define RFC_ULLRAM_BANK1736_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1736_DATA_S 0 //***************************************************************************** // @@ -15039,9 +15039,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1737_DATA_W 32 -#define RFC_ULLRAM_BANK1737_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1737_DATA_S 0 +#define RFC_ULLRAM_BANK1737_DATA_W 32 +#define RFC_ULLRAM_BANK1737_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1737_DATA_S 0 //***************************************************************************** // @@ -15051,9 +15051,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1738_DATA_W 32 -#define RFC_ULLRAM_BANK1738_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1738_DATA_S 0 +#define RFC_ULLRAM_BANK1738_DATA_W 32 +#define RFC_ULLRAM_BANK1738_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1738_DATA_S 0 //***************************************************************************** // @@ -15063,9 +15063,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1739_DATA_W 32 -#define RFC_ULLRAM_BANK1739_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1739_DATA_S 0 +#define RFC_ULLRAM_BANK1739_DATA_W 32 +#define RFC_ULLRAM_BANK1739_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1739_DATA_S 0 //***************************************************************************** // @@ -15075,9 +15075,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1740_DATA_W 32 -#define RFC_ULLRAM_BANK1740_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1740_DATA_S 0 +#define RFC_ULLRAM_BANK1740_DATA_W 32 +#define RFC_ULLRAM_BANK1740_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1740_DATA_S 0 //***************************************************************************** // @@ -15087,9 +15087,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1741_DATA_W 32 -#define RFC_ULLRAM_BANK1741_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1741_DATA_S 0 +#define RFC_ULLRAM_BANK1741_DATA_W 32 +#define RFC_ULLRAM_BANK1741_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1741_DATA_S 0 //***************************************************************************** // @@ -15099,9 +15099,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1742_DATA_W 32 -#define RFC_ULLRAM_BANK1742_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1742_DATA_S 0 +#define RFC_ULLRAM_BANK1742_DATA_W 32 +#define RFC_ULLRAM_BANK1742_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1742_DATA_S 0 //***************************************************************************** // @@ -15111,9 +15111,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1743_DATA_W 32 -#define RFC_ULLRAM_BANK1743_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1743_DATA_S 0 +#define RFC_ULLRAM_BANK1743_DATA_W 32 +#define RFC_ULLRAM_BANK1743_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1743_DATA_S 0 //***************************************************************************** // @@ -15123,9 +15123,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1744_DATA_W 32 -#define RFC_ULLRAM_BANK1744_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1744_DATA_S 0 +#define RFC_ULLRAM_BANK1744_DATA_W 32 +#define RFC_ULLRAM_BANK1744_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1744_DATA_S 0 //***************************************************************************** // @@ -15135,9 +15135,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1745_DATA_W 32 -#define RFC_ULLRAM_BANK1745_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1745_DATA_S 0 +#define RFC_ULLRAM_BANK1745_DATA_W 32 +#define RFC_ULLRAM_BANK1745_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1745_DATA_S 0 //***************************************************************************** // @@ -15147,9 +15147,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1746_DATA_W 32 -#define RFC_ULLRAM_BANK1746_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1746_DATA_S 0 +#define RFC_ULLRAM_BANK1746_DATA_W 32 +#define RFC_ULLRAM_BANK1746_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1746_DATA_S 0 //***************************************************************************** // @@ -15159,9 +15159,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1747_DATA_W 32 -#define RFC_ULLRAM_BANK1747_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1747_DATA_S 0 +#define RFC_ULLRAM_BANK1747_DATA_W 32 +#define RFC_ULLRAM_BANK1747_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1747_DATA_S 0 //***************************************************************************** // @@ -15171,9 +15171,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1748_DATA_W 32 -#define RFC_ULLRAM_BANK1748_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1748_DATA_S 0 +#define RFC_ULLRAM_BANK1748_DATA_W 32 +#define RFC_ULLRAM_BANK1748_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1748_DATA_S 0 //***************************************************************************** // @@ -15183,9 +15183,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1749_DATA_W 32 -#define RFC_ULLRAM_BANK1749_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1749_DATA_S 0 +#define RFC_ULLRAM_BANK1749_DATA_W 32 +#define RFC_ULLRAM_BANK1749_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1749_DATA_S 0 //***************************************************************************** // @@ -15195,9 +15195,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1750_DATA_W 32 -#define RFC_ULLRAM_BANK1750_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1750_DATA_S 0 +#define RFC_ULLRAM_BANK1750_DATA_W 32 +#define RFC_ULLRAM_BANK1750_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1750_DATA_S 0 //***************************************************************************** // @@ -15207,9 +15207,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1751_DATA_W 32 -#define RFC_ULLRAM_BANK1751_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1751_DATA_S 0 +#define RFC_ULLRAM_BANK1751_DATA_W 32 +#define RFC_ULLRAM_BANK1751_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1751_DATA_S 0 //***************************************************************************** // @@ -15219,9 +15219,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1752_DATA_W 32 -#define RFC_ULLRAM_BANK1752_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1752_DATA_S 0 +#define RFC_ULLRAM_BANK1752_DATA_W 32 +#define RFC_ULLRAM_BANK1752_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1752_DATA_S 0 //***************************************************************************** // @@ -15231,9 +15231,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1753_DATA_W 32 -#define RFC_ULLRAM_BANK1753_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1753_DATA_S 0 +#define RFC_ULLRAM_BANK1753_DATA_W 32 +#define RFC_ULLRAM_BANK1753_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1753_DATA_S 0 //***************************************************************************** // @@ -15243,9 +15243,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1754_DATA_W 32 -#define RFC_ULLRAM_BANK1754_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1754_DATA_S 0 +#define RFC_ULLRAM_BANK1754_DATA_W 32 +#define RFC_ULLRAM_BANK1754_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1754_DATA_S 0 //***************************************************************************** // @@ -15255,9 +15255,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1755_DATA_W 32 -#define RFC_ULLRAM_BANK1755_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1755_DATA_S 0 +#define RFC_ULLRAM_BANK1755_DATA_W 32 +#define RFC_ULLRAM_BANK1755_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1755_DATA_S 0 //***************************************************************************** // @@ -15267,9 +15267,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1756_DATA_W 32 -#define RFC_ULLRAM_BANK1756_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1756_DATA_S 0 +#define RFC_ULLRAM_BANK1756_DATA_W 32 +#define RFC_ULLRAM_BANK1756_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1756_DATA_S 0 //***************************************************************************** // @@ -15279,9 +15279,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1757_DATA_W 32 -#define RFC_ULLRAM_BANK1757_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1757_DATA_S 0 +#define RFC_ULLRAM_BANK1757_DATA_W 32 +#define RFC_ULLRAM_BANK1757_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1757_DATA_S 0 //***************************************************************************** // @@ -15291,9 +15291,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1758_DATA_W 32 -#define RFC_ULLRAM_BANK1758_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1758_DATA_S 0 +#define RFC_ULLRAM_BANK1758_DATA_W 32 +#define RFC_ULLRAM_BANK1758_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1758_DATA_S 0 //***************************************************************************** // @@ -15303,9 +15303,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1759_DATA_W 32 -#define RFC_ULLRAM_BANK1759_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1759_DATA_S 0 +#define RFC_ULLRAM_BANK1759_DATA_W 32 +#define RFC_ULLRAM_BANK1759_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1759_DATA_S 0 //***************************************************************************** // @@ -15315,9 +15315,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1760_DATA_W 32 -#define RFC_ULLRAM_BANK1760_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1760_DATA_S 0 +#define RFC_ULLRAM_BANK1760_DATA_W 32 +#define RFC_ULLRAM_BANK1760_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1760_DATA_S 0 //***************************************************************************** // @@ -15327,9 +15327,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1761_DATA_W 32 -#define RFC_ULLRAM_BANK1761_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1761_DATA_S 0 +#define RFC_ULLRAM_BANK1761_DATA_W 32 +#define RFC_ULLRAM_BANK1761_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1761_DATA_S 0 //***************************************************************************** // @@ -15339,9 +15339,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1762_DATA_W 32 -#define RFC_ULLRAM_BANK1762_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1762_DATA_S 0 +#define RFC_ULLRAM_BANK1762_DATA_W 32 +#define RFC_ULLRAM_BANK1762_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1762_DATA_S 0 //***************************************************************************** // @@ -15351,9 +15351,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1763_DATA_W 32 -#define RFC_ULLRAM_BANK1763_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1763_DATA_S 0 +#define RFC_ULLRAM_BANK1763_DATA_W 32 +#define RFC_ULLRAM_BANK1763_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1763_DATA_S 0 //***************************************************************************** // @@ -15363,9 +15363,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1764_DATA_W 32 -#define RFC_ULLRAM_BANK1764_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1764_DATA_S 0 +#define RFC_ULLRAM_BANK1764_DATA_W 32 +#define RFC_ULLRAM_BANK1764_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1764_DATA_S 0 //***************************************************************************** // @@ -15375,9 +15375,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1765_DATA_W 32 -#define RFC_ULLRAM_BANK1765_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1765_DATA_S 0 +#define RFC_ULLRAM_BANK1765_DATA_W 32 +#define RFC_ULLRAM_BANK1765_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1765_DATA_S 0 //***************************************************************************** // @@ -15387,9 +15387,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1766_DATA_W 32 -#define RFC_ULLRAM_BANK1766_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1766_DATA_S 0 +#define RFC_ULLRAM_BANK1766_DATA_W 32 +#define RFC_ULLRAM_BANK1766_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1766_DATA_S 0 //***************************************************************************** // @@ -15399,9 +15399,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1767_DATA_W 32 -#define RFC_ULLRAM_BANK1767_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1767_DATA_S 0 +#define RFC_ULLRAM_BANK1767_DATA_W 32 +#define RFC_ULLRAM_BANK1767_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1767_DATA_S 0 //***************************************************************************** // @@ -15411,9 +15411,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1768_DATA_W 32 -#define RFC_ULLRAM_BANK1768_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1768_DATA_S 0 +#define RFC_ULLRAM_BANK1768_DATA_W 32 +#define RFC_ULLRAM_BANK1768_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1768_DATA_S 0 //***************************************************************************** // @@ -15423,9 +15423,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1769_DATA_W 32 -#define RFC_ULLRAM_BANK1769_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1769_DATA_S 0 +#define RFC_ULLRAM_BANK1769_DATA_W 32 +#define RFC_ULLRAM_BANK1769_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1769_DATA_S 0 //***************************************************************************** // @@ -15435,9 +15435,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1770_DATA_W 32 -#define RFC_ULLRAM_BANK1770_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1770_DATA_S 0 +#define RFC_ULLRAM_BANK1770_DATA_W 32 +#define RFC_ULLRAM_BANK1770_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1770_DATA_S 0 //***************************************************************************** // @@ -15447,9 +15447,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1771_DATA_W 32 -#define RFC_ULLRAM_BANK1771_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1771_DATA_S 0 +#define RFC_ULLRAM_BANK1771_DATA_W 32 +#define RFC_ULLRAM_BANK1771_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1771_DATA_S 0 //***************************************************************************** // @@ -15459,9 +15459,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1772_DATA_W 32 -#define RFC_ULLRAM_BANK1772_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1772_DATA_S 0 +#define RFC_ULLRAM_BANK1772_DATA_W 32 +#define RFC_ULLRAM_BANK1772_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1772_DATA_S 0 //***************************************************************************** // @@ -15471,9 +15471,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1773_DATA_W 32 -#define RFC_ULLRAM_BANK1773_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1773_DATA_S 0 +#define RFC_ULLRAM_BANK1773_DATA_W 32 +#define RFC_ULLRAM_BANK1773_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1773_DATA_S 0 //***************************************************************************** // @@ -15483,9 +15483,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1774_DATA_W 32 -#define RFC_ULLRAM_BANK1774_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1774_DATA_S 0 +#define RFC_ULLRAM_BANK1774_DATA_W 32 +#define RFC_ULLRAM_BANK1774_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1774_DATA_S 0 //***************************************************************************** // @@ -15495,9 +15495,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1775_DATA_W 32 -#define RFC_ULLRAM_BANK1775_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1775_DATA_S 0 +#define RFC_ULLRAM_BANK1775_DATA_W 32 +#define RFC_ULLRAM_BANK1775_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1775_DATA_S 0 //***************************************************************************** // @@ -15507,9 +15507,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1776_DATA_W 32 -#define RFC_ULLRAM_BANK1776_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1776_DATA_S 0 +#define RFC_ULLRAM_BANK1776_DATA_W 32 +#define RFC_ULLRAM_BANK1776_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1776_DATA_S 0 //***************************************************************************** // @@ -15519,9 +15519,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1777_DATA_W 32 -#define RFC_ULLRAM_BANK1777_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1777_DATA_S 0 +#define RFC_ULLRAM_BANK1777_DATA_W 32 +#define RFC_ULLRAM_BANK1777_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1777_DATA_S 0 //***************************************************************************** // @@ -15531,9 +15531,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1778_DATA_W 32 -#define RFC_ULLRAM_BANK1778_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1778_DATA_S 0 +#define RFC_ULLRAM_BANK1778_DATA_W 32 +#define RFC_ULLRAM_BANK1778_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1778_DATA_S 0 //***************************************************************************** // @@ -15543,9 +15543,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1779_DATA_W 32 -#define RFC_ULLRAM_BANK1779_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1779_DATA_S 0 +#define RFC_ULLRAM_BANK1779_DATA_W 32 +#define RFC_ULLRAM_BANK1779_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1779_DATA_S 0 //***************************************************************************** // @@ -15555,9 +15555,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1780_DATA_W 32 -#define RFC_ULLRAM_BANK1780_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1780_DATA_S 0 +#define RFC_ULLRAM_BANK1780_DATA_W 32 +#define RFC_ULLRAM_BANK1780_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1780_DATA_S 0 //***************************************************************************** // @@ -15567,9 +15567,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1781_DATA_W 32 -#define RFC_ULLRAM_BANK1781_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1781_DATA_S 0 +#define RFC_ULLRAM_BANK1781_DATA_W 32 +#define RFC_ULLRAM_BANK1781_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1781_DATA_S 0 //***************************************************************************** // @@ -15579,9 +15579,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1782_DATA_W 32 -#define RFC_ULLRAM_BANK1782_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1782_DATA_S 0 +#define RFC_ULLRAM_BANK1782_DATA_W 32 +#define RFC_ULLRAM_BANK1782_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1782_DATA_S 0 //***************************************************************************** // @@ -15591,9 +15591,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1783_DATA_W 32 -#define RFC_ULLRAM_BANK1783_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1783_DATA_S 0 +#define RFC_ULLRAM_BANK1783_DATA_W 32 +#define RFC_ULLRAM_BANK1783_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1783_DATA_S 0 //***************************************************************************** // @@ -15603,9 +15603,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1784_DATA_W 32 -#define RFC_ULLRAM_BANK1784_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1784_DATA_S 0 +#define RFC_ULLRAM_BANK1784_DATA_W 32 +#define RFC_ULLRAM_BANK1784_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1784_DATA_S 0 //***************************************************************************** // @@ -15615,9 +15615,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1785_DATA_W 32 -#define RFC_ULLRAM_BANK1785_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1785_DATA_S 0 +#define RFC_ULLRAM_BANK1785_DATA_W 32 +#define RFC_ULLRAM_BANK1785_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1785_DATA_S 0 //***************************************************************************** // @@ -15627,9 +15627,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1786_DATA_W 32 -#define RFC_ULLRAM_BANK1786_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1786_DATA_S 0 +#define RFC_ULLRAM_BANK1786_DATA_W 32 +#define RFC_ULLRAM_BANK1786_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1786_DATA_S 0 //***************************************************************************** // @@ -15639,9 +15639,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1787_DATA_W 32 -#define RFC_ULLRAM_BANK1787_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1787_DATA_S 0 +#define RFC_ULLRAM_BANK1787_DATA_W 32 +#define RFC_ULLRAM_BANK1787_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1787_DATA_S 0 //***************************************************************************** // @@ -15651,9 +15651,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1788_DATA_W 32 -#define RFC_ULLRAM_BANK1788_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1788_DATA_S 0 +#define RFC_ULLRAM_BANK1788_DATA_W 32 +#define RFC_ULLRAM_BANK1788_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1788_DATA_S 0 //***************************************************************************** // @@ -15663,9 +15663,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1789_DATA_W 32 -#define RFC_ULLRAM_BANK1789_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1789_DATA_S 0 +#define RFC_ULLRAM_BANK1789_DATA_W 32 +#define RFC_ULLRAM_BANK1789_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1789_DATA_S 0 //***************************************************************************** // @@ -15675,9 +15675,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1790_DATA_W 32 -#define RFC_ULLRAM_BANK1790_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1790_DATA_S 0 +#define RFC_ULLRAM_BANK1790_DATA_W 32 +#define RFC_ULLRAM_BANK1790_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1790_DATA_S 0 //***************************************************************************** // @@ -15687,9 +15687,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1791_DATA_W 32 -#define RFC_ULLRAM_BANK1791_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1791_DATA_S 0 +#define RFC_ULLRAM_BANK1791_DATA_W 32 +#define RFC_ULLRAM_BANK1791_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1791_DATA_S 0 //***************************************************************************** // @@ -15699,9 +15699,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1792_DATA_W 32 -#define RFC_ULLRAM_BANK1792_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1792_DATA_S 0 +#define RFC_ULLRAM_BANK1792_DATA_W 32 +#define RFC_ULLRAM_BANK1792_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1792_DATA_S 0 //***************************************************************************** // @@ -15711,9 +15711,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1793_DATA_W 32 -#define RFC_ULLRAM_BANK1793_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1793_DATA_S 0 +#define RFC_ULLRAM_BANK1793_DATA_W 32 +#define RFC_ULLRAM_BANK1793_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1793_DATA_S 0 //***************************************************************************** // @@ -15723,9 +15723,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1794_DATA_W 32 -#define RFC_ULLRAM_BANK1794_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1794_DATA_S 0 +#define RFC_ULLRAM_BANK1794_DATA_W 32 +#define RFC_ULLRAM_BANK1794_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1794_DATA_S 0 //***************************************************************************** // @@ -15735,9 +15735,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1795_DATA_W 32 -#define RFC_ULLRAM_BANK1795_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1795_DATA_S 0 +#define RFC_ULLRAM_BANK1795_DATA_W 32 +#define RFC_ULLRAM_BANK1795_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1795_DATA_S 0 //***************************************************************************** // @@ -15747,9 +15747,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1796_DATA_W 32 -#define RFC_ULLRAM_BANK1796_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1796_DATA_S 0 +#define RFC_ULLRAM_BANK1796_DATA_W 32 +#define RFC_ULLRAM_BANK1796_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1796_DATA_S 0 //***************************************************************************** // @@ -15759,9 +15759,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1797_DATA_W 32 -#define RFC_ULLRAM_BANK1797_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1797_DATA_S 0 +#define RFC_ULLRAM_BANK1797_DATA_W 32 +#define RFC_ULLRAM_BANK1797_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1797_DATA_S 0 //***************************************************************************** // @@ -15771,9 +15771,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1798_DATA_W 32 -#define RFC_ULLRAM_BANK1798_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1798_DATA_S 0 +#define RFC_ULLRAM_BANK1798_DATA_W 32 +#define RFC_ULLRAM_BANK1798_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1798_DATA_S 0 //***************************************************************************** // @@ -15783,9 +15783,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1799_DATA_W 32 -#define RFC_ULLRAM_BANK1799_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1799_DATA_S 0 +#define RFC_ULLRAM_BANK1799_DATA_W 32 +#define RFC_ULLRAM_BANK1799_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1799_DATA_S 0 //***************************************************************************** // @@ -15795,9 +15795,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1800_DATA_W 32 -#define RFC_ULLRAM_BANK1800_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1800_DATA_S 0 +#define RFC_ULLRAM_BANK1800_DATA_W 32 +#define RFC_ULLRAM_BANK1800_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1800_DATA_S 0 //***************************************************************************** // @@ -15807,9 +15807,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1801_DATA_W 32 -#define RFC_ULLRAM_BANK1801_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1801_DATA_S 0 +#define RFC_ULLRAM_BANK1801_DATA_W 32 +#define RFC_ULLRAM_BANK1801_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1801_DATA_S 0 //***************************************************************************** // @@ -15819,9 +15819,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1802_DATA_W 32 -#define RFC_ULLRAM_BANK1802_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1802_DATA_S 0 +#define RFC_ULLRAM_BANK1802_DATA_W 32 +#define RFC_ULLRAM_BANK1802_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1802_DATA_S 0 //***************************************************************************** // @@ -15831,9 +15831,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1803_DATA_W 32 -#define RFC_ULLRAM_BANK1803_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1803_DATA_S 0 +#define RFC_ULLRAM_BANK1803_DATA_W 32 +#define RFC_ULLRAM_BANK1803_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1803_DATA_S 0 //***************************************************************************** // @@ -15843,9 +15843,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1804_DATA_W 32 -#define RFC_ULLRAM_BANK1804_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1804_DATA_S 0 +#define RFC_ULLRAM_BANK1804_DATA_W 32 +#define RFC_ULLRAM_BANK1804_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1804_DATA_S 0 //***************************************************************************** // @@ -15855,9 +15855,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1805_DATA_W 32 -#define RFC_ULLRAM_BANK1805_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1805_DATA_S 0 +#define RFC_ULLRAM_BANK1805_DATA_W 32 +#define RFC_ULLRAM_BANK1805_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1805_DATA_S 0 //***************************************************************************** // @@ -15867,9 +15867,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1806_DATA_W 32 -#define RFC_ULLRAM_BANK1806_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1806_DATA_S 0 +#define RFC_ULLRAM_BANK1806_DATA_W 32 +#define RFC_ULLRAM_BANK1806_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1806_DATA_S 0 //***************************************************************************** // @@ -15879,9 +15879,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1807_DATA_W 32 -#define RFC_ULLRAM_BANK1807_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1807_DATA_S 0 +#define RFC_ULLRAM_BANK1807_DATA_W 32 +#define RFC_ULLRAM_BANK1807_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1807_DATA_S 0 //***************************************************************************** // @@ -15891,9 +15891,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1808_DATA_W 32 -#define RFC_ULLRAM_BANK1808_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1808_DATA_S 0 +#define RFC_ULLRAM_BANK1808_DATA_W 32 +#define RFC_ULLRAM_BANK1808_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1808_DATA_S 0 //***************************************************************************** // @@ -15903,9 +15903,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1809_DATA_W 32 -#define RFC_ULLRAM_BANK1809_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1809_DATA_S 0 +#define RFC_ULLRAM_BANK1809_DATA_W 32 +#define RFC_ULLRAM_BANK1809_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1809_DATA_S 0 //***************************************************************************** // @@ -15915,9 +15915,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1810_DATA_W 32 -#define RFC_ULLRAM_BANK1810_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1810_DATA_S 0 +#define RFC_ULLRAM_BANK1810_DATA_W 32 +#define RFC_ULLRAM_BANK1810_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1810_DATA_S 0 //***************************************************************************** // @@ -15927,9 +15927,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1811_DATA_W 32 -#define RFC_ULLRAM_BANK1811_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1811_DATA_S 0 +#define RFC_ULLRAM_BANK1811_DATA_W 32 +#define RFC_ULLRAM_BANK1811_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1811_DATA_S 0 //***************************************************************************** // @@ -15939,9 +15939,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1812_DATA_W 32 -#define RFC_ULLRAM_BANK1812_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1812_DATA_S 0 +#define RFC_ULLRAM_BANK1812_DATA_W 32 +#define RFC_ULLRAM_BANK1812_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1812_DATA_S 0 //***************************************************************************** // @@ -15951,9 +15951,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1813_DATA_W 32 -#define RFC_ULLRAM_BANK1813_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1813_DATA_S 0 +#define RFC_ULLRAM_BANK1813_DATA_W 32 +#define RFC_ULLRAM_BANK1813_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1813_DATA_S 0 //***************************************************************************** // @@ -15963,9 +15963,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1814_DATA_W 32 -#define RFC_ULLRAM_BANK1814_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1814_DATA_S 0 +#define RFC_ULLRAM_BANK1814_DATA_W 32 +#define RFC_ULLRAM_BANK1814_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1814_DATA_S 0 //***************************************************************************** // @@ -15975,9 +15975,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1815_DATA_W 32 -#define RFC_ULLRAM_BANK1815_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1815_DATA_S 0 +#define RFC_ULLRAM_BANK1815_DATA_W 32 +#define RFC_ULLRAM_BANK1815_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1815_DATA_S 0 //***************************************************************************** // @@ -15987,9 +15987,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1816_DATA_W 32 -#define RFC_ULLRAM_BANK1816_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1816_DATA_S 0 +#define RFC_ULLRAM_BANK1816_DATA_W 32 +#define RFC_ULLRAM_BANK1816_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1816_DATA_S 0 //***************************************************************************** // @@ -15999,9 +15999,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1817_DATA_W 32 -#define RFC_ULLRAM_BANK1817_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1817_DATA_S 0 +#define RFC_ULLRAM_BANK1817_DATA_W 32 +#define RFC_ULLRAM_BANK1817_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1817_DATA_S 0 //***************************************************************************** // @@ -16011,9 +16011,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1818_DATA_W 32 -#define RFC_ULLRAM_BANK1818_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1818_DATA_S 0 +#define RFC_ULLRAM_BANK1818_DATA_W 32 +#define RFC_ULLRAM_BANK1818_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1818_DATA_S 0 //***************************************************************************** // @@ -16023,9 +16023,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1819_DATA_W 32 -#define RFC_ULLRAM_BANK1819_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1819_DATA_S 0 +#define RFC_ULLRAM_BANK1819_DATA_W 32 +#define RFC_ULLRAM_BANK1819_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1819_DATA_S 0 //***************************************************************************** // @@ -16035,9 +16035,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1820_DATA_W 32 -#define RFC_ULLRAM_BANK1820_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1820_DATA_S 0 +#define RFC_ULLRAM_BANK1820_DATA_W 32 +#define RFC_ULLRAM_BANK1820_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1820_DATA_S 0 //***************************************************************************** // @@ -16047,9 +16047,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1821_DATA_W 32 -#define RFC_ULLRAM_BANK1821_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1821_DATA_S 0 +#define RFC_ULLRAM_BANK1821_DATA_W 32 +#define RFC_ULLRAM_BANK1821_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1821_DATA_S 0 //***************************************************************************** // @@ -16059,9 +16059,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1822_DATA_W 32 -#define RFC_ULLRAM_BANK1822_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1822_DATA_S 0 +#define RFC_ULLRAM_BANK1822_DATA_W 32 +#define RFC_ULLRAM_BANK1822_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1822_DATA_S 0 //***************************************************************************** // @@ -16071,9 +16071,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1823_DATA_W 32 -#define RFC_ULLRAM_BANK1823_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1823_DATA_S 0 +#define RFC_ULLRAM_BANK1823_DATA_W 32 +#define RFC_ULLRAM_BANK1823_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1823_DATA_S 0 //***************************************************************************** // @@ -16083,9 +16083,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1824_DATA_W 32 -#define RFC_ULLRAM_BANK1824_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1824_DATA_S 0 +#define RFC_ULLRAM_BANK1824_DATA_W 32 +#define RFC_ULLRAM_BANK1824_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1824_DATA_S 0 //***************************************************************************** // @@ -16095,9 +16095,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1825_DATA_W 32 -#define RFC_ULLRAM_BANK1825_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1825_DATA_S 0 +#define RFC_ULLRAM_BANK1825_DATA_W 32 +#define RFC_ULLRAM_BANK1825_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1825_DATA_S 0 //***************************************************************************** // @@ -16107,9 +16107,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1826_DATA_W 32 -#define RFC_ULLRAM_BANK1826_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1826_DATA_S 0 +#define RFC_ULLRAM_BANK1826_DATA_W 32 +#define RFC_ULLRAM_BANK1826_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1826_DATA_S 0 //***************************************************************************** // @@ -16119,9 +16119,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1827_DATA_W 32 -#define RFC_ULLRAM_BANK1827_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1827_DATA_S 0 +#define RFC_ULLRAM_BANK1827_DATA_W 32 +#define RFC_ULLRAM_BANK1827_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1827_DATA_S 0 //***************************************************************************** // @@ -16131,9 +16131,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1828_DATA_W 32 -#define RFC_ULLRAM_BANK1828_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1828_DATA_S 0 +#define RFC_ULLRAM_BANK1828_DATA_W 32 +#define RFC_ULLRAM_BANK1828_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1828_DATA_S 0 //***************************************************************************** // @@ -16143,9 +16143,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1829_DATA_W 32 -#define RFC_ULLRAM_BANK1829_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1829_DATA_S 0 +#define RFC_ULLRAM_BANK1829_DATA_W 32 +#define RFC_ULLRAM_BANK1829_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1829_DATA_S 0 //***************************************************************************** // @@ -16155,9 +16155,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1830_DATA_W 32 -#define RFC_ULLRAM_BANK1830_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1830_DATA_S 0 +#define RFC_ULLRAM_BANK1830_DATA_W 32 +#define RFC_ULLRAM_BANK1830_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1830_DATA_S 0 //***************************************************************************** // @@ -16167,9 +16167,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1831_DATA_W 32 -#define RFC_ULLRAM_BANK1831_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1831_DATA_S 0 +#define RFC_ULLRAM_BANK1831_DATA_W 32 +#define RFC_ULLRAM_BANK1831_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1831_DATA_S 0 //***************************************************************************** // @@ -16179,9 +16179,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1832_DATA_W 32 -#define RFC_ULLRAM_BANK1832_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1832_DATA_S 0 +#define RFC_ULLRAM_BANK1832_DATA_W 32 +#define RFC_ULLRAM_BANK1832_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1832_DATA_S 0 //***************************************************************************** // @@ -16191,9 +16191,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1833_DATA_W 32 -#define RFC_ULLRAM_BANK1833_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1833_DATA_S 0 +#define RFC_ULLRAM_BANK1833_DATA_W 32 +#define RFC_ULLRAM_BANK1833_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1833_DATA_S 0 //***************************************************************************** // @@ -16203,9 +16203,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1834_DATA_W 32 -#define RFC_ULLRAM_BANK1834_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1834_DATA_S 0 +#define RFC_ULLRAM_BANK1834_DATA_W 32 +#define RFC_ULLRAM_BANK1834_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1834_DATA_S 0 //***************************************************************************** // @@ -16215,9 +16215,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1835_DATA_W 32 -#define RFC_ULLRAM_BANK1835_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1835_DATA_S 0 +#define RFC_ULLRAM_BANK1835_DATA_W 32 +#define RFC_ULLRAM_BANK1835_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1835_DATA_S 0 //***************************************************************************** // @@ -16227,9 +16227,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1836_DATA_W 32 -#define RFC_ULLRAM_BANK1836_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1836_DATA_S 0 +#define RFC_ULLRAM_BANK1836_DATA_W 32 +#define RFC_ULLRAM_BANK1836_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1836_DATA_S 0 //***************************************************************************** // @@ -16239,9 +16239,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1837_DATA_W 32 -#define RFC_ULLRAM_BANK1837_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1837_DATA_S 0 +#define RFC_ULLRAM_BANK1837_DATA_W 32 +#define RFC_ULLRAM_BANK1837_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1837_DATA_S 0 //***************************************************************************** // @@ -16251,9 +16251,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1838_DATA_W 32 -#define RFC_ULLRAM_BANK1838_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1838_DATA_S 0 +#define RFC_ULLRAM_BANK1838_DATA_W 32 +#define RFC_ULLRAM_BANK1838_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1838_DATA_S 0 //***************************************************************************** // @@ -16263,9 +16263,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1839_DATA_W 32 -#define RFC_ULLRAM_BANK1839_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1839_DATA_S 0 +#define RFC_ULLRAM_BANK1839_DATA_W 32 +#define RFC_ULLRAM_BANK1839_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1839_DATA_S 0 //***************************************************************************** // @@ -16275,9 +16275,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1840_DATA_W 32 -#define RFC_ULLRAM_BANK1840_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1840_DATA_S 0 +#define RFC_ULLRAM_BANK1840_DATA_W 32 +#define RFC_ULLRAM_BANK1840_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1840_DATA_S 0 //***************************************************************************** // @@ -16287,9 +16287,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1841_DATA_W 32 -#define RFC_ULLRAM_BANK1841_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1841_DATA_S 0 +#define RFC_ULLRAM_BANK1841_DATA_W 32 +#define RFC_ULLRAM_BANK1841_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1841_DATA_S 0 //***************************************************************************** // @@ -16299,9 +16299,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1842_DATA_W 32 -#define RFC_ULLRAM_BANK1842_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1842_DATA_S 0 +#define RFC_ULLRAM_BANK1842_DATA_W 32 +#define RFC_ULLRAM_BANK1842_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1842_DATA_S 0 //***************************************************************************** // @@ -16311,9 +16311,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1843_DATA_W 32 -#define RFC_ULLRAM_BANK1843_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1843_DATA_S 0 +#define RFC_ULLRAM_BANK1843_DATA_W 32 +#define RFC_ULLRAM_BANK1843_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1843_DATA_S 0 //***************************************************************************** // @@ -16323,9 +16323,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1844_DATA_W 32 -#define RFC_ULLRAM_BANK1844_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1844_DATA_S 0 +#define RFC_ULLRAM_BANK1844_DATA_W 32 +#define RFC_ULLRAM_BANK1844_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1844_DATA_S 0 //***************************************************************************** // @@ -16335,9 +16335,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1845_DATA_W 32 -#define RFC_ULLRAM_BANK1845_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1845_DATA_S 0 +#define RFC_ULLRAM_BANK1845_DATA_W 32 +#define RFC_ULLRAM_BANK1845_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1845_DATA_S 0 //***************************************************************************** // @@ -16347,9 +16347,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1846_DATA_W 32 -#define RFC_ULLRAM_BANK1846_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1846_DATA_S 0 +#define RFC_ULLRAM_BANK1846_DATA_W 32 +#define RFC_ULLRAM_BANK1846_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1846_DATA_S 0 //***************************************************************************** // @@ -16359,9 +16359,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1847_DATA_W 32 -#define RFC_ULLRAM_BANK1847_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1847_DATA_S 0 +#define RFC_ULLRAM_BANK1847_DATA_W 32 +#define RFC_ULLRAM_BANK1847_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1847_DATA_S 0 //***************************************************************************** // @@ -16371,9 +16371,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1848_DATA_W 32 -#define RFC_ULLRAM_BANK1848_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1848_DATA_S 0 +#define RFC_ULLRAM_BANK1848_DATA_W 32 +#define RFC_ULLRAM_BANK1848_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1848_DATA_S 0 //***************************************************************************** // @@ -16383,9 +16383,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1849_DATA_W 32 -#define RFC_ULLRAM_BANK1849_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1849_DATA_S 0 +#define RFC_ULLRAM_BANK1849_DATA_W 32 +#define RFC_ULLRAM_BANK1849_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1849_DATA_S 0 //***************************************************************************** // @@ -16395,9 +16395,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1850_DATA_W 32 -#define RFC_ULLRAM_BANK1850_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1850_DATA_S 0 +#define RFC_ULLRAM_BANK1850_DATA_W 32 +#define RFC_ULLRAM_BANK1850_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1850_DATA_S 0 //***************************************************************************** // @@ -16407,9 +16407,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1851_DATA_W 32 -#define RFC_ULLRAM_BANK1851_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1851_DATA_S 0 +#define RFC_ULLRAM_BANK1851_DATA_W 32 +#define RFC_ULLRAM_BANK1851_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1851_DATA_S 0 //***************************************************************************** // @@ -16419,9 +16419,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1852_DATA_W 32 -#define RFC_ULLRAM_BANK1852_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1852_DATA_S 0 +#define RFC_ULLRAM_BANK1852_DATA_W 32 +#define RFC_ULLRAM_BANK1852_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1852_DATA_S 0 //***************************************************************************** // @@ -16431,9 +16431,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1853_DATA_W 32 -#define RFC_ULLRAM_BANK1853_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1853_DATA_S 0 +#define RFC_ULLRAM_BANK1853_DATA_W 32 +#define RFC_ULLRAM_BANK1853_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1853_DATA_S 0 //***************************************************************************** // @@ -16443,9 +16443,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1854_DATA_W 32 -#define RFC_ULLRAM_BANK1854_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1854_DATA_S 0 +#define RFC_ULLRAM_BANK1854_DATA_W 32 +#define RFC_ULLRAM_BANK1854_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1854_DATA_S 0 //***************************************************************************** // @@ -16455,9 +16455,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1855_DATA_W 32 -#define RFC_ULLRAM_BANK1855_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1855_DATA_S 0 +#define RFC_ULLRAM_BANK1855_DATA_W 32 +#define RFC_ULLRAM_BANK1855_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1855_DATA_S 0 //***************************************************************************** // @@ -16467,9 +16467,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1856_DATA_W 32 -#define RFC_ULLRAM_BANK1856_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1856_DATA_S 0 +#define RFC_ULLRAM_BANK1856_DATA_W 32 +#define RFC_ULLRAM_BANK1856_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1856_DATA_S 0 //***************************************************************************** // @@ -16479,9 +16479,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1857_DATA_W 32 -#define RFC_ULLRAM_BANK1857_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1857_DATA_S 0 +#define RFC_ULLRAM_BANK1857_DATA_W 32 +#define RFC_ULLRAM_BANK1857_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1857_DATA_S 0 //***************************************************************************** // @@ -16491,9 +16491,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1858_DATA_W 32 -#define RFC_ULLRAM_BANK1858_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1858_DATA_S 0 +#define RFC_ULLRAM_BANK1858_DATA_W 32 +#define RFC_ULLRAM_BANK1858_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1858_DATA_S 0 //***************************************************************************** // @@ -16503,9 +16503,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1859_DATA_W 32 -#define RFC_ULLRAM_BANK1859_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1859_DATA_S 0 +#define RFC_ULLRAM_BANK1859_DATA_W 32 +#define RFC_ULLRAM_BANK1859_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1859_DATA_S 0 //***************************************************************************** // @@ -16515,9 +16515,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1860_DATA_W 32 -#define RFC_ULLRAM_BANK1860_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1860_DATA_S 0 +#define RFC_ULLRAM_BANK1860_DATA_W 32 +#define RFC_ULLRAM_BANK1860_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1860_DATA_S 0 //***************************************************************************** // @@ -16527,9 +16527,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1861_DATA_W 32 -#define RFC_ULLRAM_BANK1861_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1861_DATA_S 0 +#define RFC_ULLRAM_BANK1861_DATA_W 32 +#define RFC_ULLRAM_BANK1861_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1861_DATA_S 0 //***************************************************************************** // @@ -16539,9 +16539,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1862_DATA_W 32 -#define RFC_ULLRAM_BANK1862_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1862_DATA_S 0 +#define RFC_ULLRAM_BANK1862_DATA_W 32 +#define RFC_ULLRAM_BANK1862_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1862_DATA_S 0 //***************************************************************************** // @@ -16551,9 +16551,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1863_DATA_W 32 -#define RFC_ULLRAM_BANK1863_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1863_DATA_S 0 +#define RFC_ULLRAM_BANK1863_DATA_W 32 +#define RFC_ULLRAM_BANK1863_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1863_DATA_S 0 //***************************************************************************** // @@ -16563,9 +16563,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1864_DATA_W 32 -#define RFC_ULLRAM_BANK1864_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1864_DATA_S 0 +#define RFC_ULLRAM_BANK1864_DATA_W 32 +#define RFC_ULLRAM_BANK1864_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1864_DATA_S 0 //***************************************************************************** // @@ -16575,9 +16575,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1865_DATA_W 32 -#define RFC_ULLRAM_BANK1865_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1865_DATA_S 0 +#define RFC_ULLRAM_BANK1865_DATA_W 32 +#define RFC_ULLRAM_BANK1865_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1865_DATA_S 0 //***************************************************************************** // @@ -16587,9 +16587,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1866_DATA_W 32 -#define RFC_ULLRAM_BANK1866_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1866_DATA_S 0 +#define RFC_ULLRAM_BANK1866_DATA_W 32 +#define RFC_ULLRAM_BANK1866_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1866_DATA_S 0 //***************************************************************************** // @@ -16599,9 +16599,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1867_DATA_W 32 -#define RFC_ULLRAM_BANK1867_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1867_DATA_S 0 +#define RFC_ULLRAM_BANK1867_DATA_W 32 +#define RFC_ULLRAM_BANK1867_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1867_DATA_S 0 //***************************************************************************** // @@ -16611,9 +16611,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1868_DATA_W 32 -#define RFC_ULLRAM_BANK1868_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1868_DATA_S 0 +#define RFC_ULLRAM_BANK1868_DATA_W 32 +#define RFC_ULLRAM_BANK1868_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1868_DATA_S 0 //***************************************************************************** // @@ -16623,9 +16623,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1869_DATA_W 32 -#define RFC_ULLRAM_BANK1869_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1869_DATA_S 0 +#define RFC_ULLRAM_BANK1869_DATA_W 32 +#define RFC_ULLRAM_BANK1869_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1869_DATA_S 0 //***************************************************************************** // @@ -16635,9 +16635,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1870_DATA_W 32 -#define RFC_ULLRAM_BANK1870_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1870_DATA_S 0 +#define RFC_ULLRAM_BANK1870_DATA_W 32 +#define RFC_ULLRAM_BANK1870_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1870_DATA_S 0 //***************************************************************************** // @@ -16647,9 +16647,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1871_DATA_W 32 -#define RFC_ULLRAM_BANK1871_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1871_DATA_S 0 +#define RFC_ULLRAM_BANK1871_DATA_W 32 +#define RFC_ULLRAM_BANK1871_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1871_DATA_S 0 //***************************************************************************** // @@ -16659,9 +16659,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1872_DATA_W 32 -#define RFC_ULLRAM_BANK1872_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1872_DATA_S 0 +#define RFC_ULLRAM_BANK1872_DATA_W 32 +#define RFC_ULLRAM_BANK1872_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1872_DATA_S 0 //***************************************************************************** // @@ -16671,9 +16671,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1873_DATA_W 32 -#define RFC_ULLRAM_BANK1873_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1873_DATA_S 0 +#define RFC_ULLRAM_BANK1873_DATA_W 32 +#define RFC_ULLRAM_BANK1873_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1873_DATA_S 0 //***************************************************************************** // @@ -16683,9 +16683,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1874_DATA_W 32 -#define RFC_ULLRAM_BANK1874_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1874_DATA_S 0 +#define RFC_ULLRAM_BANK1874_DATA_W 32 +#define RFC_ULLRAM_BANK1874_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1874_DATA_S 0 //***************************************************************************** // @@ -16695,9 +16695,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1875_DATA_W 32 -#define RFC_ULLRAM_BANK1875_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1875_DATA_S 0 +#define RFC_ULLRAM_BANK1875_DATA_W 32 +#define RFC_ULLRAM_BANK1875_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1875_DATA_S 0 //***************************************************************************** // @@ -16707,9 +16707,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1876_DATA_W 32 -#define RFC_ULLRAM_BANK1876_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1876_DATA_S 0 +#define RFC_ULLRAM_BANK1876_DATA_W 32 +#define RFC_ULLRAM_BANK1876_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1876_DATA_S 0 //***************************************************************************** // @@ -16719,9 +16719,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1877_DATA_W 32 -#define RFC_ULLRAM_BANK1877_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1877_DATA_S 0 +#define RFC_ULLRAM_BANK1877_DATA_W 32 +#define RFC_ULLRAM_BANK1877_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1877_DATA_S 0 //***************************************************************************** // @@ -16731,9 +16731,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1878_DATA_W 32 -#define RFC_ULLRAM_BANK1878_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1878_DATA_S 0 +#define RFC_ULLRAM_BANK1878_DATA_W 32 +#define RFC_ULLRAM_BANK1878_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1878_DATA_S 0 //***************************************************************************** // @@ -16743,9 +16743,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1879_DATA_W 32 -#define RFC_ULLRAM_BANK1879_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1879_DATA_S 0 +#define RFC_ULLRAM_BANK1879_DATA_W 32 +#define RFC_ULLRAM_BANK1879_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1879_DATA_S 0 //***************************************************************************** // @@ -16755,9 +16755,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1880_DATA_W 32 -#define RFC_ULLRAM_BANK1880_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1880_DATA_S 0 +#define RFC_ULLRAM_BANK1880_DATA_W 32 +#define RFC_ULLRAM_BANK1880_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1880_DATA_S 0 //***************************************************************************** // @@ -16767,9 +16767,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1881_DATA_W 32 -#define RFC_ULLRAM_BANK1881_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1881_DATA_S 0 +#define RFC_ULLRAM_BANK1881_DATA_W 32 +#define RFC_ULLRAM_BANK1881_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1881_DATA_S 0 //***************************************************************************** // @@ -16779,9 +16779,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1882_DATA_W 32 -#define RFC_ULLRAM_BANK1882_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1882_DATA_S 0 +#define RFC_ULLRAM_BANK1882_DATA_W 32 +#define RFC_ULLRAM_BANK1882_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1882_DATA_S 0 //***************************************************************************** // @@ -16791,9 +16791,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1883_DATA_W 32 -#define RFC_ULLRAM_BANK1883_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1883_DATA_S 0 +#define RFC_ULLRAM_BANK1883_DATA_W 32 +#define RFC_ULLRAM_BANK1883_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1883_DATA_S 0 //***************************************************************************** // @@ -16803,9 +16803,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1884_DATA_W 32 -#define RFC_ULLRAM_BANK1884_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1884_DATA_S 0 +#define RFC_ULLRAM_BANK1884_DATA_W 32 +#define RFC_ULLRAM_BANK1884_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1884_DATA_S 0 //***************************************************************************** // @@ -16815,9 +16815,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1885_DATA_W 32 -#define RFC_ULLRAM_BANK1885_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1885_DATA_S 0 +#define RFC_ULLRAM_BANK1885_DATA_W 32 +#define RFC_ULLRAM_BANK1885_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1885_DATA_S 0 //***************************************************************************** // @@ -16827,9 +16827,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1886_DATA_W 32 -#define RFC_ULLRAM_BANK1886_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1886_DATA_S 0 +#define RFC_ULLRAM_BANK1886_DATA_W 32 +#define RFC_ULLRAM_BANK1886_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1886_DATA_S 0 //***************************************************************************** // @@ -16839,9 +16839,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1887_DATA_W 32 -#define RFC_ULLRAM_BANK1887_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1887_DATA_S 0 +#define RFC_ULLRAM_BANK1887_DATA_W 32 +#define RFC_ULLRAM_BANK1887_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1887_DATA_S 0 //***************************************************************************** // @@ -16851,9 +16851,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1888_DATA_W 32 -#define RFC_ULLRAM_BANK1888_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1888_DATA_S 0 +#define RFC_ULLRAM_BANK1888_DATA_W 32 +#define RFC_ULLRAM_BANK1888_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1888_DATA_S 0 //***************************************************************************** // @@ -16863,9 +16863,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1889_DATA_W 32 -#define RFC_ULLRAM_BANK1889_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1889_DATA_S 0 +#define RFC_ULLRAM_BANK1889_DATA_W 32 +#define RFC_ULLRAM_BANK1889_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1889_DATA_S 0 //***************************************************************************** // @@ -16875,9 +16875,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1890_DATA_W 32 -#define RFC_ULLRAM_BANK1890_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1890_DATA_S 0 +#define RFC_ULLRAM_BANK1890_DATA_W 32 +#define RFC_ULLRAM_BANK1890_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1890_DATA_S 0 //***************************************************************************** // @@ -16887,9 +16887,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1891_DATA_W 32 -#define RFC_ULLRAM_BANK1891_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1891_DATA_S 0 +#define RFC_ULLRAM_BANK1891_DATA_W 32 +#define RFC_ULLRAM_BANK1891_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1891_DATA_S 0 //***************************************************************************** // @@ -16899,9 +16899,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1892_DATA_W 32 -#define RFC_ULLRAM_BANK1892_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1892_DATA_S 0 +#define RFC_ULLRAM_BANK1892_DATA_W 32 +#define RFC_ULLRAM_BANK1892_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1892_DATA_S 0 //***************************************************************************** // @@ -16911,9 +16911,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1893_DATA_W 32 -#define RFC_ULLRAM_BANK1893_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1893_DATA_S 0 +#define RFC_ULLRAM_BANK1893_DATA_W 32 +#define RFC_ULLRAM_BANK1893_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1893_DATA_S 0 //***************************************************************************** // @@ -16923,9 +16923,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1894_DATA_W 32 -#define RFC_ULLRAM_BANK1894_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1894_DATA_S 0 +#define RFC_ULLRAM_BANK1894_DATA_W 32 +#define RFC_ULLRAM_BANK1894_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1894_DATA_S 0 //***************************************************************************** // @@ -16935,9 +16935,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1895_DATA_W 32 -#define RFC_ULLRAM_BANK1895_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1895_DATA_S 0 +#define RFC_ULLRAM_BANK1895_DATA_W 32 +#define RFC_ULLRAM_BANK1895_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1895_DATA_S 0 //***************************************************************************** // @@ -16947,9 +16947,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1896_DATA_W 32 -#define RFC_ULLRAM_BANK1896_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1896_DATA_S 0 +#define RFC_ULLRAM_BANK1896_DATA_W 32 +#define RFC_ULLRAM_BANK1896_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1896_DATA_S 0 //***************************************************************************** // @@ -16959,9 +16959,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1897_DATA_W 32 -#define RFC_ULLRAM_BANK1897_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1897_DATA_S 0 +#define RFC_ULLRAM_BANK1897_DATA_W 32 +#define RFC_ULLRAM_BANK1897_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1897_DATA_S 0 //***************************************************************************** // @@ -16971,9 +16971,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1898_DATA_W 32 -#define RFC_ULLRAM_BANK1898_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1898_DATA_S 0 +#define RFC_ULLRAM_BANK1898_DATA_W 32 +#define RFC_ULLRAM_BANK1898_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1898_DATA_S 0 //***************************************************************************** // @@ -16983,9 +16983,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1899_DATA_W 32 -#define RFC_ULLRAM_BANK1899_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1899_DATA_S 0 +#define RFC_ULLRAM_BANK1899_DATA_W 32 +#define RFC_ULLRAM_BANK1899_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1899_DATA_S 0 //***************************************************************************** // @@ -16995,9 +16995,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1900_DATA_W 32 -#define RFC_ULLRAM_BANK1900_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1900_DATA_S 0 +#define RFC_ULLRAM_BANK1900_DATA_W 32 +#define RFC_ULLRAM_BANK1900_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1900_DATA_S 0 //***************************************************************************** // @@ -17007,9 +17007,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1901_DATA_W 32 -#define RFC_ULLRAM_BANK1901_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1901_DATA_S 0 +#define RFC_ULLRAM_BANK1901_DATA_W 32 +#define RFC_ULLRAM_BANK1901_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1901_DATA_S 0 //***************************************************************************** // @@ -17019,9 +17019,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1902_DATA_W 32 -#define RFC_ULLRAM_BANK1902_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1902_DATA_S 0 +#define RFC_ULLRAM_BANK1902_DATA_W 32 +#define RFC_ULLRAM_BANK1902_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1902_DATA_S 0 //***************************************************************************** // @@ -17031,9 +17031,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1903_DATA_W 32 -#define RFC_ULLRAM_BANK1903_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1903_DATA_S 0 +#define RFC_ULLRAM_BANK1903_DATA_W 32 +#define RFC_ULLRAM_BANK1903_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1903_DATA_S 0 //***************************************************************************** // @@ -17043,9 +17043,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1904_DATA_W 32 -#define RFC_ULLRAM_BANK1904_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1904_DATA_S 0 +#define RFC_ULLRAM_BANK1904_DATA_W 32 +#define RFC_ULLRAM_BANK1904_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1904_DATA_S 0 //***************************************************************************** // @@ -17055,9 +17055,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1905_DATA_W 32 -#define RFC_ULLRAM_BANK1905_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1905_DATA_S 0 +#define RFC_ULLRAM_BANK1905_DATA_W 32 +#define RFC_ULLRAM_BANK1905_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1905_DATA_S 0 //***************************************************************************** // @@ -17067,9 +17067,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1906_DATA_W 32 -#define RFC_ULLRAM_BANK1906_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1906_DATA_S 0 +#define RFC_ULLRAM_BANK1906_DATA_W 32 +#define RFC_ULLRAM_BANK1906_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1906_DATA_S 0 //***************************************************************************** // @@ -17079,9 +17079,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1907_DATA_W 32 -#define RFC_ULLRAM_BANK1907_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1907_DATA_S 0 +#define RFC_ULLRAM_BANK1907_DATA_W 32 +#define RFC_ULLRAM_BANK1907_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1907_DATA_S 0 //***************************************************************************** // @@ -17091,9 +17091,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1908_DATA_W 32 -#define RFC_ULLRAM_BANK1908_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1908_DATA_S 0 +#define RFC_ULLRAM_BANK1908_DATA_W 32 +#define RFC_ULLRAM_BANK1908_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1908_DATA_S 0 //***************************************************************************** // @@ -17103,9 +17103,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1909_DATA_W 32 -#define RFC_ULLRAM_BANK1909_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1909_DATA_S 0 +#define RFC_ULLRAM_BANK1909_DATA_W 32 +#define RFC_ULLRAM_BANK1909_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1909_DATA_S 0 //***************************************************************************** // @@ -17115,9 +17115,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1910_DATA_W 32 -#define RFC_ULLRAM_BANK1910_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1910_DATA_S 0 +#define RFC_ULLRAM_BANK1910_DATA_W 32 +#define RFC_ULLRAM_BANK1910_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1910_DATA_S 0 //***************************************************************************** // @@ -17127,9 +17127,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1911_DATA_W 32 -#define RFC_ULLRAM_BANK1911_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1911_DATA_S 0 +#define RFC_ULLRAM_BANK1911_DATA_W 32 +#define RFC_ULLRAM_BANK1911_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1911_DATA_S 0 //***************************************************************************** // @@ -17139,9 +17139,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1912_DATA_W 32 -#define RFC_ULLRAM_BANK1912_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1912_DATA_S 0 +#define RFC_ULLRAM_BANK1912_DATA_W 32 +#define RFC_ULLRAM_BANK1912_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1912_DATA_S 0 //***************************************************************************** // @@ -17151,9 +17151,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1913_DATA_W 32 -#define RFC_ULLRAM_BANK1913_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1913_DATA_S 0 +#define RFC_ULLRAM_BANK1913_DATA_W 32 +#define RFC_ULLRAM_BANK1913_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1913_DATA_S 0 //***************************************************************************** // @@ -17163,9 +17163,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1914_DATA_W 32 -#define RFC_ULLRAM_BANK1914_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1914_DATA_S 0 +#define RFC_ULLRAM_BANK1914_DATA_W 32 +#define RFC_ULLRAM_BANK1914_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1914_DATA_S 0 //***************************************************************************** // @@ -17175,9 +17175,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1915_DATA_W 32 -#define RFC_ULLRAM_BANK1915_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1915_DATA_S 0 +#define RFC_ULLRAM_BANK1915_DATA_W 32 +#define RFC_ULLRAM_BANK1915_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1915_DATA_S 0 //***************************************************************************** // @@ -17187,9 +17187,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1916_DATA_W 32 -#define RFC_ULLRAM_BANK1916_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1916_DATA_S 0 +#define RFC_ULLRAM_BANK1916_DATA_W 32 +#define RFC_ULLRAM_BANK1916_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1916_DATA_S 0 //***************************************************************************** // @@ -17199,9 +17199,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1917_DATA_W 32 -#define RFC_ULLRAM_BANK1917_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1917_DATA_S 0 +#define RFC_ULLRAM_BANK1917_DATA_W 32 +#define RFC_ULLRAM_BANK1917_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1917_DATA_S 0 //***************************************************************************** // @@ -17211,9 +17211,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1918_DATA_W 32 -#define RFC_ULLRAM_BANK1918_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1918_DATA_S 0 +#define RFC_ULLRAM_BANK1918_DATA_W 32 +#define RFC_ULLRAM_BANK1918_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1918_DATA_S 0 //***************************************************************************** // @@ -17223,9 +17223,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1919_DATA_W 32 -#define RFC_ULLRAM_BANK1919_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1919_DATA_S 0 +#define RFC_ULLRAM_BANK1919_DATA_W 32 +#define RFC_ULLRAM_BANK1919_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1919_DATA_S 0 //***************************************************************************** // @@ -17235,9 +17235,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1920_DATA_W 32 -#define RFC_ULLRAM_BANK1920_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1920_DATA_S 0 +#define RFC_ULLRAM_BANK1920_DATA_W 32 +#define RFC_ULLRAM_BANK1920_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1920_DATA_S 0 //***************************************************************************** // @@ -17247,9 +17247,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1921_DATA_W 32 -#define RFC_ULLRAM_BANK1921_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1921_DATA_S 0 +#define RFC_ULLRAM_BANK1921_DATA_W 32 +#define RFC_ULLRAM_BANK1921_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1921_DATA_S 0 //***************************************************************************** // @@ -17259,9 +17259,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1922_DATA_W 32 -#define RFC_ULLRAM_BANK1922_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1922_DATA_S 0 +#define RFC_ULLRAM_BANK1922_DATA_W 32 +#define RFC_ULLRAM_BANK1922_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1922_DATA_S 0 //***************************************************************************** // @@ -17271,9 +17271,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1923_DATA_W 32 -#define RFC_ULLRAM_BANK1923_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1923_DATA_S 0 +#define RFC_ULLRAM_BANK1923_DATA_W 32 +#define RFC_ULLRAM_BANK1923_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1923_DATA_S 0 //***************************************************************************** // @@ -17283,9 +17283,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1924_DATA_W 32 -#define RFC_ULLRAM_BANK1924_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1924_DATA_S 0 +#define RFC_ULLRAM_BANK1924_DATA_W 32 +#define RFC_ULLRAM_BANK1924_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1924_DATA_S 0 //***************************************************************************** // @@ -17295,9 +17295,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1925_DATA_W 32 -#define RFC_ULLRAM_BANK1925_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1925_DATA_S 0 +#define RFC_ULLRAM_BANK1925_DATA_W 32 +#define RFC_ULLRAM_BANK1925_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1925_DATA_S 0 //***************************************************************************** // @@ -17307,9 +17307,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1926_DATA_W 32 -#define RFC_ULLRAM_BANK1926_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1926_DATA_S 0 +#define RFC_ULLRAM_BANK1926_DATA_W 32 +#define RFC_ULLRAM_BANK1926_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1926_DATA_S 0 //***************************************************************************** // @@ -17319,9 +17319,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1927_DATA_W 32 -#define RFC_ULLRAM_BANK1927_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1927_DATA_S 0 +#define RFC_ULLRAM_BANK1927_DATA_W 32 +#define RFC_ULLRAM_BANK1927_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1927_DATA_S 0 //***************************************************************************** // @@ -17331,9 +17331,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1928_DATA_W 32 -#define RFC_ULLRAM_BANK1928_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1928_DATA_S 0 +#define RFC_ULLRAM_BANK1928_DATA_W 32 +#define RFC_ULLRAM_BANK1928_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1928_DATA_S 0 //***************************************************************************** // @@ -17343,9 +17343,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1929_DATA_W 32 -#define RFC_ULLRAM_BANK1929_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1929_DATA_S 0 +#define RFC_ULLRAM_BANK1929_DATA_W 32 +#define RFC_ULLRAM_BANK1929_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1929_DATA_S 0 //***************************************************************************** // @@ -17355,9 +17355,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1930_DATA_W 32 -#define RFC_ULLRAM_BANK1930_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1930_DATA_S 0 +#define RFC_ULLRAM_BANK1930_DATA_W 32 +#define RFC_ULLRAM_BANK1930_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1930_DATA_S 0 //***************************************************************************** // @@ -17367,9 +17367,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1931_DATA_W 32 -#define RFC_ULLRAM_BANK1931_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1931_DATA_S 0 +#define RFC_ULLRAM_BANK1931_DATA_W 32 +#define RFC_ULLRAM_BANK1931_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1931_DATA_S 0 //***************************************************************************** // @@ -17379,9 +17379,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1932_DATA_W 32 -#define RFC_ULLRAM_BANK1932_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1932_DATA_S 0 +#define RFC_ULLRAM_BANK1932_DATA_W 32 +#define RFC_ULLRAM_BANK1932_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1932_DATA_S 0 //***************************************************************************** // @@ -17391,9 +17391,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1933_DATA_W 32 -#define RFC_ULLRAM_BANK1933_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1933_DATA_S 0 +#define RFC_ULLRAM_BANK1933_DATA_W 32 +#define RFC_ULLRAM_BANK1933_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1933_DATA_S 0 //***************************************************************************** // @@ -17403,9 +17403,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1934_DATA_W 32 -#define RFC_ULLRAM_BANK1934_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1934_DATA_S 0 +#define RFC_ULLRAM_BANK1934_DATA_W 32 +#define RFC_ULLRAM_BANK1934_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1934_DATA_S 0 //***************************************************************************** // @@ -17415,9 +17415,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1935_DATA_W 32 -#define RFC_ULLRAM_BANK1935_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1935_DATA_S 0 +#define RFC_ULLRAM_BANK1935_DATA_W 32 +#define RFC_ULLRAM_BANK1935_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1935_DATA_S 0 //***************************************************************************** // @@ -17427,9 +17427,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1936_DATA_W 32 -#define RFC_ULLRAM_BANK1936_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1936_DATA_S 0 +#define RFC_ULLRAM_BANK1936_DATA_W 32 +#define RFC_ULLRAM_BANK1936_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1936_DATA_S 0 //***************************************************************************** // @@ -17439,9 +17439,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1937_DATA_W 32 -#define RFC_ULLRAM_BANK1937_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1937_DATA_S 0 +#define RFC_ULLRAM_BANK1937_DATA_W 32 +#define RFC_ULLRAM_BANK1937_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1937_DATA_S 0 //***************************************************************************** // @@ -17451,9 +17451,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1938_DATA_W 32 -#define RFC_ULLRAM_BANK1938_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1938_DATA_S 0 +#define RFC_ULLRAM_BANK1938_DATA_W 32 +#define RFC_ULLRAM_BANK1938_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1938_DATA_S 0 //***************************************************************************** // @@ -17463,9 +17463,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1939_DATA_W 32 -#define RFC_ULLRAM_BANK1939_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1939_DATA_S 0 +#define RFC_ULLRAM_BANK1939_DATA_W 32 +#define RFC_ULLRAM_BANK1939_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1939_DATA_S 0 //***************************************************************************** // @@ -17475,9 +17475,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1940_DATA_W 32 -#define RFC_ULLRAM_BANK1940_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1940_DATA_S 0 +#define RFC_ULLRAM_BANK1940_DATA_W 32 +#define RFC_ULLRAM_BANK1940_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1940_DATA_S 0 //***************************************************************************** // @@ -17487,9 +17487,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1941_DATA_W 32 -#define RFC_ULLRAM_BANK1941_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1941_DATA_S 0 +#define RFC_ULLRAM_BANK1941_DATA_W 32 +#define RFC_ULLRAM_BANK1941_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1941_DATA_S 0 //***************************************************************************** // @@ -17499,9 +17499,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1942_DATA_W 32 -#define RFC_ULLRAM_BANK1942_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1942_DATA_S 0 +#define RFC_ULLRAM_BANK1942_DATA_W 32 +#define RFC_ULLRAM_BANK1942_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1942_DATA_S 0 //***************************************************************************** // @@ -17511,9 +17511,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1943_DATA_W 32 -#define RFC_ULLRAM_BANK1943_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1943_DATA_S 0 +#define RFC_ULLRAM_BANK1943_DATA_W 32 +#define RFC_ULLRAM_BANK1943_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1943_DATA_S 0 //***************************************************************************** // @@ -17523,9 +17523,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1944_DATA_W 32 -#define RFC_ULLRAM_BANK1944_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1944_DATA_S 0 +#define RFC_ULLRAM_BANK1944_DATA_W 32 +#define RFC_ULLRAM_BANK1944_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1944_DATA_S 0 //***************************************************************************** // @@ -17535,9 +17535,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1945_DATA_W 32 -#define RFC_ULLRAM_BANK1945_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1945_DATA_S 0 +#define RFC_ULLRAM_BANK1945_DATA_W 32 +#define RFC_ULLRAM_BANK1945_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1945_DATA_S 0 //***************************************************************************** // @@ -17547,9 +17547,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1946_DATA_W 32 -#define RFC_ULLRAM_BANK1946_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1946_DATA_S 0 +#define RFC_ULLRAM_BANK1946_DATA_W 32 +#define RFC_ULLRAM_BANK1946_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1946_DATA_S 0 //***************************************************************************** // @@ -17559,9 +17559,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1947_DATA_W 32 -#define RFC_ULLRAM_BANK1947_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1947_DATA_S 0 +#define RFC_ULLRAM_BANK1947_DATA_W 32 +#define RFC_ULLRAM_BANK1947_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1947_DATA_S 0 //***************************************************************************** // @@ -17571,9 +17571,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1948_DATA_W 32 -#define RFC_ULLRAM_BANK1948_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1948_DATA_S 0 +#define RFC_ULLRAM_BANK1948_DATA_W 32 +#define RFC_ULLRAM_BANK1948_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1948_DATA_S 0 //***************************************************************************** // @@ -17583,9 +17583,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1949_DATA_W 32 -#define RFC_ULLRAM_BANK1949_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1949_DATA_S 0 +#define RFC_ULLRAM_BANK1949_DATA_W 32 +#define RFC_ULLRAM_BANK1949_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1949_DATA_S 0 //***************************************************************************** // @@ -17595,9 +17595,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1950_DATA_W 32 -#define RFC_ULLRAM_BANK1950_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1950_DATA_S 0 +#define RFC_ULLRAM_BANK1950_DATA_W 32 +#define RFC_ULLRAM_BANK1950_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1950_DATA_S 0 //***************************************************************************** // @@ -17607,9 +17607,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1951_DATA_W 32 -#define RFC_ULLRAM_BANK1951_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1951_DATA_S 0 +#define RFC_ULLRAM_BANK1951_DATA_W 32 +#define RFC_ULLRAM_BANK1951_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1951_DATA_S 0 //***************************************************************************** // @@ -17619,9 +17619,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1952_DATA_W 32 -#define RFC_ULLRAM_BANK1952_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1952_DATA_S 0 +#define RFC_ULLRAM_BANK1952_DATA_W 32 +#define RFC_ULLRAM_BANK1952_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1952_DATA_S 0 //***************************************************************************** // @@ -17631,9 +17631,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1953_DATA_W 32 -#define RFC_ULLRAM_BANK1953_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1953_DATA_S 0 +#define RFC_ULLRAM_BANK1953_DATA_W 32 +#define RFC_ULLRAM_BANK1953_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1953_DATA_S 0 //***************************************************************************** // @@ -17643,9 +17643,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1954_DATA_W 32 -#define RFC_ULLRAM_BANK1954_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1954_DATA_S 0 +#define RFC_ULLRAM_BANK1954_DATA_W 32 +#define RFC_ULLRAM_BANK1954_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1954_DATA_S 0 //***************************************************************************** // @@ -17655,9 +17655,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1955_DATA_W 32 -#define RFC_ULLRAM_BANK1955_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1955_DATA_S 0 +#define RFC_ULLRAM_BANK1955_DATA_W 32 +#define RFC_ULLRAM_BANK1955_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1955_DATA_S 0 //***************************************************************************** // @@ -17667,9 +17667,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1956_DATA_W 32 -#define RFC_ULLRAM_BANK1956_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1956_DATA_S 0 +#define RFC_ULLRAM_BANK1956_DATA_W 32 +#define RFC_ULLRAM_BANK1956_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1956_DATA_S 0 //***************************************************************************** // @@ -17679,9 +17679,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1957_DATA_W 32 -#define RFC_ULLRAM_BANK1957_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1957_DATA_S 0 +#define RFC_ULLRAM_BANK1957_DATA_W 32 +#define RFC_ULLRAM_BANK1957_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1957_DATA_S 0 //***************************************************************************** // @@ -17691,9 +17691,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1958_DATA_W 32 -#define RFC_ULLRAM_BANK1958_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1958_DATA_S 0 +#define RFC_ULLRAM_BANK1958_DATA_W 32 +#define RFC_ULLRAM_BANK1958_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1958_DATA_S 0 //***************************************************************************** // @@ -17703,9 +17703,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1959_DATA_W 32 -#define RFC_ULLRAM_BANK1959_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1959_DATA_S 0 +#define RFC_ULLRAM_BANK1959_DATA_W 32 +#define RFC_ULLRAM_BANK1959_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1959_DATA_S 0 //***************************************************************************** // @@ -17715,9 +17715,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1960_DATA_W 32 -#define RFC_ULLRAM_BANK1960_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1960_DATA_S 0 +#define RFC_ULLRAM_BANK1960_DATA_W 32 +#define RFC_ULLRAM_BANK1960_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1960_DATA_S 0 //***************************************************************************** // @@ -17727,9 +17727,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1961_DATA_W 32 -#define RFC_ULLRAM_BANK1961_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1961_DATA_S 0 +#define RFC_ULLRAM_BANK1961_DATA_W 32 +#define RFC_ULLRAM_BANK1961_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1961_DATA_S 0 //***************************************************************************** // @@ -17739,9 +17739,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1962_DATA_W 32 -#define RFC_ULLRAM_BANK1962_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1962_DATA_S 0 +#define RFC_ULLRAM_BANK1962_DATA_W 32 +#define RFC_ULLRAM_BANK1962_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1962_DATA_S 0 //***************************************************************************** // @@ -17751,9 +17751,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1963_DATA_W 32 -#define RFC_ULLRAM_BANK1963_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1963_DATA_S 0 +#define RFC_ULLRAM_BANK1963_DATA_W 32 +#define RFC_ULLRAM_BANK1963_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1963_DATA_S 0 //***************************************************************************** // @@ -17763,9 +17763,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1964_DATA_W 32 -#define RFC_ULLRAM_BANK1964_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1964_DATA_S 0 +#define RFC_ULLRAM_BANK1964_DATA_W 32 +#define RFC_ULLRAM_BANK1964_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1964_DATA_S 0 //***************************************************************************** // @@ -17775,9 +17775,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1965_DATA_W 32 -#define RFC_ULLRAM_BANK1965_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1965_DATA_S 0 +#define RFC_ULLRAM_BANK1965_DATA_W 32 +#define RFC_ULLRAM_BANK1965_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1965_DATA_S 0 //***************************************************************************** // @@ -17787,9 +17787,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1966_DATA_W 32 -#define RFC_ULLRAM_BANK1966_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1966_DATA_S 0 +#define RFC_ULLRAM_BANK1966_DATA_W 32 +#define RFC_ULLRAM_BANK1966_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1966_DATA_S 0 //***************************************************************************** // @@ -17799,9 +17799,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1967_DATA_W 32 -#define RFC_ULLRAM_BANK1967_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1967_DATA_S 0 +#define RFC_ULLRAM_BANK1967_DATA_W 32 +#define RFC_ULLRAM_BANK1967_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1967_DATA_S 0 //***************************************************************************** // @@ -17811,9 +17811,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1968_DATA_W 32 -#define RFC_ULLRAM_BANK1968_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1968_DATA_S 0 +#define RFC_ULLRAM_BANK1968_DATA_W 32 +#define RFC_ULLRAM_BANK1968_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1968_DATA_S 0 //***************************************************************************** // @@ -17823,9 +17823,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1969_DATA_W 32 -#define RFC_ULLRAM_BANK1969_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1969_DATA_S 0 +#define RFC_ULLRAM_BANK1969_DATA_W 32 +#define RFC_ULLRAM_BANK1969_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1969_DATA_S 0 //***************************************************************************** // @@ -17835,9 +17835,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1970_DATA_W 32 -#define RFC_ULLRAM_BANK1970_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1970_DATA_S 0 +#define RFC_ULLRAM_BANK1970_DATA_W 32 +#define RFC_ULLRAM_BANK1970_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1970_DATA_S 0 //***************************************************************************** // @@ -17847,9 +17847,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1971_DATA_W 32 -#define RFC_ULLRAM_BANK1971_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1971_DATA_S 0 +#define RFC_ULLRAM_BANK1971_DATA_W 32 +#define RFC_ULLRAM_BANK1971_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1971_DATA_S 0 //***************************************************************************** // @@ -17859,9 +17859,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1972_DATA_W 32 -#define RFC_ULLRAM_BANK1972_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1972_DATA_S 0 +#define RFC_ULLRAM_BANK1972_DATA_W 32 +#define RFC_ULLRAM_BANK1972_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1972_DATA_S 0 //***************************************************************************** // @@ -17871,9 +17871,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1973_DATA_W 32 -#define RFC_ULLRAM_BANK1973_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1973_DATA_S 0 +#define RFC_ULLRAM_BANK1973_DATA_W 32 +#define RFC_ULLRAM_BANK1973_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1973_DATA_S 0 //***************************************************************************** // @@ -17883,9 +17883,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1974_DATA_W 32 -#define RFC_ULLRAM_BANK1974_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1974_DATA_S 0 +#define RFC_ULLRAM_BANK1974_DATA_W 32 +#define RFC_ULLRAM_BANK1974_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1974_DATA_S 0 //***************************************************************************** // @@ -17895,9 +17895,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1975_DATA_W 32 -#define RFC_ULLRAM_BANK1975_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1975_DATA_S 0 +#define RFC_ULLRAM_BANK1975_DATA_W 32 +#define RFC_ULLRAM_BANK1975_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1975_DATA_S 0 //***************************************************************************** // @@ -17907,9 +17907,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1976_DATA_W 32 -#define RFC_ULLRAM_BANK1976_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1976_DATA_S 0 +#define RFC_ULLRAM_BANK1976_DATA_W 32 +#define RFC_ULLRAM_BANK1976_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1976_DATA_S 0 //***************************************************************************** // @@ -17919,9 +17919,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1977_DATA_W 32 -#define RFC_ULLRAM_BANK1977_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1977_DATA_S 0 +#define RFC_ULLRAM_BANK1977_DATA_W 32 +#define RFC_ULLRAM_BANK1977_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1977_DATA_S 0 //***************************************************************************** // @@ -17931,9 +17931,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1978_DATA_W 32 -#define RFC_ULLRAM_BANK1978_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1978_DATA_S 0 +#define RFC_ULLRAM_BANK1978_DATA_W 32 +#define RFC_ULLRAM_BANK1978_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1978_DATA_S 0 //***************************************************************************** // @@ -17943,9 +17943,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1979_DATA_W 32 -#define RFC_ULLRAM_BANK1979_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1979_DATA_S 0 +#define RFC_ULLRAM_BANK1979_DATA_W 32 +#define RFC_ULLRAM_BANK1979_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1979_DATA_S 0 //***************************************************************************** // @@ -17955,9 +17955,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1980_DATA_W 32 -#define RFC_ULLRAM_BANK1980_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1980_DATA_S 0 +#define RFC_ULLRAM_BANK1980_DATA_W 32 +#define RFC_ULLRAM_BANK1980_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1980_DATA_S 0 //***************************************************************************** // @@ -17967,9 +17967,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1981_DATA_W 32 -#define RFC_ULLRAM_BANK1981_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1981_DATA_S 0 +#define RFC_ULLRAM_BANK1981_DATA_W 32 +#define RFC_ULLRAM_BANK1981_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1981_DATA_S 0 //***************************************************************************** // @@ -17979,9 +17979,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1982_DATA_W 32 -#define RFC_ULLRAM_BANK1982_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1982_DATA_S 0 +#define RFC_ULLRAM_BANK1982_DATA_W 32 +#define RFC_ULLRAM_BANK1982_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1982_DATA_S 0 //***************************************************************************** // @@ -17991,9 +17991,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1983_DATA_W 32 -#define RFC_ULLRAM_BANK1983_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1983_DATA_S 0 +#define RFC_ULLRAM_BANK1983_DATA_W 32 +#define RFC_ULLRAM_BANK1983_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1983_DATA_S 0 //***************************************************************************** // @@ -18003,9 +18003,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1984_DATA_W 32 -#define RFC_ULLRAM_BANK1984_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1984_DATA_S 0 +#define RFC_ULLRAM_BANK1984_DATA_W 32 +#define RFC_ULLRAM_BANK1984_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1984_DATA_S 0 //***************************************************************************** // @@ -18015,9 +18015,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1985_DATA_W 32 -#define RFC_ULLRAM_BANK1985_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1985_DATA_S 0 +#define RFC_ULLRAM_BANK1985_DATA_W 32 +#define RFC_ULLRAM_BANK1985_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1985_DATA_S 0 //***************************************************************************** // @@ -18027,9 +18027,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1986_DATA_W 32 -#define RFC_ULLRAM_BANK1986_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1986_DATA_S 0 +#define RFC_ULLRAM_BANK1986_DATA_W 32 +#define RFC_ULLRAM_BANK1986_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1986_DATA_S 0 //***************************************************************************** // @@ -18039,9 +18039,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1987_DATA_W 32 -#define RFC_ULLRAM_BANK1987_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1987_DATA_S 0 +#define RFC_ULLRAM_BANK1987_DATA_W 32 +#define RFC_ULLRAM_BANK1987_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1987_DATA_S 0 //***************************************************************************** // @@ -18051,9 +18051,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1988_DATA_W 32 -#define RFC_ULLRAM_BANK1988_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1988_DATA_S 0 +#define RFC_ULLRAM_BANK1988_DATA_W 32 +#define RFC_ULLRAM_BANK1988_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1988_DATA_S 0 //***************************************************************************** // @@ -18063,9 +18063,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1989_DATA_W 32 -#define RFC_ULLRAM_BANK1989_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1989_DATA_S 0 +#define RFC_ULLRAM_BANK1989_DATA_W 32 +#define RFC_ULLRAM_BANK1989_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1989_DATA_S 0 //***************************************************************************** // @@ -18075,9 +18075,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1990_DATA_W 32 -#define RFC_ULLRAM_BANK1990_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1990_DATA_S 0 +#define RFC_ULLRAM_BANK1990_DATA_W 32 +#define RFC_ULLRAM_BANK1990_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1990_DATA_S 0 //***************************************************************************** // @@ -18087,9 +18087,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1991_DATA_W 32 -#define RFC_ULLRAM_BANK1991_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1991_DATA_S 0 +#define RFC_ULLRAM_BANK1991_DATA_W 32 +#define RFC_ULLRAM_BANK1991_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1991_DATA_S 0 //***************************************************************************** // @@ -18099,9 +18099,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1992_DATA_W 32 -#define RFC_ULLRAM_BANK1992_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1992_DATA_S 0 +#define RFC_ULLRAM_BANK1992_DATA_W 32 +#define RFC_ULLRAM_BANK1992_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1992_DATA_S 0 //***************************************************************************** // @@ -18111,9 +18111,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1993_DATA_W 32 -#define RFC_ULLRAM_BANK1993_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1993_DATA_S 0 +#define RFC_ULLRAM_BANK1993_DATA_W 32 +#define RFC_ULLRAM_BANK1993_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1993_DATA_S 0 //***************************************************************************** // @@ -18123,9 +18123,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1994_DATA_W 32 -#define RFC_ULLRAM_BANK1994_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1994_DATA_S 0 +#define RFC_ULLRAM_BANK1994_DATA_W 32 +#define RFC_ULLRAM_BANK1994_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1994_DATA_S 0 //***************************************************************************** // @@ -18135,9 +18135,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1995_DATA_W 32 -#define RFC_ULLRAM_BANK1995_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1995_DATA_S 0 +#define RFC_ULLRAM_BANK1995_DATA_W 32 +#define RFC_ULLRAM_BANK1995_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1995_DATA_S 0 //***************************************************************************** // @@ -18147,9 +18147,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1996_DATA_W 32 -#define RFC_ULLRAM_BANK1996_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1996_DATA_S 0 +#define RFC_ULLRAM_BANK1996_DATA_W 32 +#define RFC_ULLRAM_BANK1996_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1996_DATA_S 0 //***************************************************************************** // @@ -18159,9 +18159,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1997_DATA_W 32 -#define RFC_ULLRAM_BANK1997_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1997_DATA_S 0 +#define RFC_ULLRAM_BANK1997_DATA_W 32 +#define RFC_ULLRAM_BANK1997_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1997_DATA_S 0 //***************************************************************************** // @@ -18171,9 +18171,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1998_DATA_W 32 -#define RFC_ULLRAM_BANK1998_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1998_DATA_S 0 +#define RFC_ULLRAM_BANK1998_DATA_W 32 +#define RFC_ULLRAM_BANK1998_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1998_DATA_S 0 //***************************************************************************** // @@ -18183,9 +18183,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK1999_DATA_W 32 -#define RFC_ULLRAM_BANK1999_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1999_DATA_S 0 +#define RFC_ULLRAM_BANK1999_DATA_W 32 +#define RFC_ULLRAM_BANK1999_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK1999_DATA_S 0 //***************************************************************************** // @@ -18195,9 +18195,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11000_DATA_W 32 -#define RFC_ULLRAM_BANK11000_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11000_DATA_S 0 +#define RFC_ULLRAM_BANK11000_DATA_W 32 +#define RFC_ULLRAM_BANK11000_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11000_DATA_S 0 //***************************************************************************** // @@ -18207,9 +18207,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11001_DATA_W 32 -#define RFC_ULLRAM_BANK11001_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11001_DATA_S 0 +#define RFC_ULLRAM_BANK11001_DATA_W 32 +#define RFC_ULLRAM_BANK11001_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11001_DATA_S 0 //***************************************************************************** // @@ -18219,9 +18219,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11002_DATA_W 32 -#define RFC_ULLRAM_BANK11002_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11002_DATA_S 0 +#define RFC_ULLRAM_BANK11002_DATA_W 32 +#define RFC_ULLRAM_BANK11002_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11002_DATA_S 0 //***************************************************************************** // @@ -18231,9 +18231,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11003_DATA_W 32 -#define RFC_ULLRAM_BANK11003_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11003_DATA_S 0 +#define RFC_ULLRAM_BANK11003_DATA_W 32 +#define RFC_ULLRAM_BANK11003_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11003_DATA_S 0 //***************************************************************************** // @@ -18243,9 +18243,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11004_DATA_W 32 -#define RFC_ULLRAM_BANK11004_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11004_DATA_S 0 +#define RFC_ULLRAM_BANK11004_DATA_W 32 +#define RFC_ULLRAM_BANK11004_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11004_DATA_S 0 //***************************************************************************** // @@ -18255,9 +18255,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11005_DATA_W 32 -#define RFC_ULLRAM_BANK11005_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11005_DATA_S 0 +#define RFC_ULLRAM_BANK11005_DATA_W 32 +#define RFC_ULLRAM_BANK11005_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11005_DATA_S 0 //***************************************************************************** // @@ -18267,9 +18267,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11006_DATA_W 32 -#define RFC_ULLRAM_BANK11006_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11006_DATA_S 0 +#define RFC_ULLRAM_BANK11006_DATA_W 32 +#define RFC_ULLRAM_BANK11006_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11006_DATA_S 0 //***************************************************************************** // @@ -18279,9 +18279,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11007_DATA_W 32 -#define RFC_ULLRAM_BANK11007_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11007_DATA_S 0 +#define RFC_ULLRAM_BANK11007_DATA_W 32 +#define RFC_ULLRAM_BANK11007_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11007_DATA_S 0 //***************************************************************************** // @@ -18291,9 +18291,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11008_DATA_W 32 -#define RFC_ULLRAM_BANK11008_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11008_DATA_S 0 +#define RFC_ULLRAM_BANK11008_DATA_W 32 +#define RFC_ULLRAM_BANK11008_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11008_DATA_S 0 //***************************************************************************** // @@ -18303,9 +18303,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11009_DATA_W 32 -#define RFC_ULLRAM_BANK11009_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11009_DATA_S 0 +#define RFC_ULLRAM_BANK11009_DATA_W 32 +#define RFC_ULLRAM_BANK11009_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11009_DATA_S 0 //***************************************************************************** // @@ -18315,9 +18315,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11010_DATA_W 32 -#define RFC_ULLRAM_BANK11010_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11010_DATA_S 0 +#define RFC_ULLRAM_BANK11010_DATA_W 32 +#define RFC_ULLRAM_BANK11010_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11010_DATA_S 0 //***************************************************************************** // @@ -18327,9 +18327,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11011_DATA_W 32 -#define RFC_ULLRAM_BANK11011_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11011_DATA_S 0 +#define RFC_ULLRAM_BANK11011_DATA_W 32 +#define RFC_ULLRAM_BANK11011_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11011_DATA_S 0 //***************************************************************************** // @@ -18339,9 +18339,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11012_DATA_W 32 -#define RFC_ULLRAM_BANK11012_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11012_DATA_S 0 +#define RFC_ULLRAM_BANK11012_DATA_W 32 +#define RFC_ULLRAM_BANK11012_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11012_DATA_S 0 //***************************************************************************** // @@ -18351,9 +18351,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11013_DATA_W 32 -#define RFC_ULLRAM_BANK11013_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11013_DATA_S 0 +#define RFC_ULLRAM_BANK11013_DATA_W 32 +#define RFC_ULLRAM_BANK11013_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11013_DATA_S 0 //***************************************************************************** // @@ -18363,9 +18363,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11014_DATA_W 32 -#define RFC_ULLRAM_BANK11014_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11014_DATA_S 0 +#define RFC_ULLRAM_BANK11014_DATA_W 32 +#define RFC_ULLRAM_BANK11014_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11014_DATA_S 0 //***************************************************************************** // @@ -18375,9 +18375,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11015_DATA_W 32 -#define RFC_ULLRAM_BANK11015_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11015_DATA_S 0 +#define RFC_ULLRAM_BANK11015_DATA_W 32 +#define RFC_ULLRAM_BANK11015_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11015_DATA_S 0 //***************************************************************************** // @@ -18387,9 +18387,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11016_DATA_W 32 -#define RFC_ULLRAM_BANK11016_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11016_DATA_S 0 +#define RFC_ULLRAM_BANK11016_DATA_W 32 +#define RFC_ULLRAM_BANK11016_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11016_DATA_S 0 //***************************************************************************** // @@ -18399,9 +18399,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11017_DATA_W 32 -#define RFC_ULLRAM_BANK11017_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11017_DATA_S 0 +#define RFC_ULLRAM_BANK11017_DATA_W 32 +#define RFC_ULLRAM_BANK11017_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11017_DATA_S 0 //***************************************************************************** // @@ -18411,9 +18411,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11018_DATA_W 32 -#define RFC_ULLRAM_BANK11018_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11018_DATA_S 0 +#define RFC_ULLRAM_BANK11018_DATA_W 32 +#define RFC_ULLRAM_BANK11018_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11018_DATA_S 0 //***************************************************************************** // @@ -18423,9 +18423,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11019_DATA_W 32 -#define RFC_ULLRAM_BANK11019_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11019_DATA_S 0 +#define RFC_ULLRAM_BANK11019_DATA_W 32 +#define RFC_ULLRAM_BANK11019_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11019_DATA_S 0 //***************************************************************************** // @@ -18435,9 +18435,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11020_DATA_W 32 -#define RFC_ULLRAM_BANK11020_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11020_DATA_S 0 +#define RFC_ULLRAM_BANK11020_DATA_W 32 +#define RFC_ULLRAM_BANK11020_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11020_DATA_S 0 //***************************************************************************** // @@ -18447,9 +18447,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11021_DATA_W 32 -#define RFC_ULLRAM_BANK11021_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11021_DATA_S 0 +#define RFC_ULLRAM_BANK11021_DATA_W 32 +#define RFC_ULLRAM_BANK11021_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11021_DATA_S 0 //***************************************************************************** // @@ -18459,9 +18459,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11022_DATA_W 32 -#define RFC_ULLRAM_BANK11022_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11022_DATA_S 0 +#define RFC_ULLRAM_BANK11022_DATA_W 32 +#define RFC_ULLRAM_BANK11022_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11022_DATA_S 0 //***************************************************************************** // @@ -18471,9 +18471,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11023_DATA_W 32 -#define RFC_ULLRAM_BANK11023_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11023_DATA_S 0 +#define RFC_ULLRAM_BANK11023_DATA_W 32 +#define RFC_ULLRAM_BANK11023_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11023_DATA_S 0 //***************************************************************************** // @@ -18483,9 +18483,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11024_DATA_W 32 -#define RFC_ULLRAM_BANK11024_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11024_DATA_S 0 +#define RFC_ULLRAM_BANK11024_DATA_W 32 +#define RFC_ULLRAM_BANK11024_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11024_DATA_S 0 //***************************************************************************** // @@ -18495,9 +18495,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11025_DATA_W 32 -#define RFC_ULLRAM_BANK11025_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11025_DATA_S 0 +#define RFC_ULLRAM_BANK11025_DATA_W 32 +#define RFC_ULLRAM_BANK11025_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11025_DATA_S 0 //***************************************************************************** // @@ -18507,9 +18507,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11026_DATA_W 32 -#define RFC_ULLRAM_BANK11026_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11026_DATA_S 0 +#define RFC_ULLRAM_BANK11026_DATA_W 32 +#define RFC_ULLRAM_BANK11026_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11026_DATA_S 0 //***************************************************************************** // @@ -18519,9 +18519,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11027_DATA_W 32 -#define RFC_ULLRAM_BANK11027_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11027_DATA_S 0 +#define RFC_ULLRAM_BANK11027_DATA_W 32 +#define RFC_ULLRAM_BANK11027_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11027_DATA_S 0 //***************************************************************************** // @@ -18531,9 +18531,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11028_DATA_W 32 -#define RFC_ULLRAM_BANK11028_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11028_DATA_S 0 +#define RFC_ULLRAM_BANK11028_DATA_W 32 +#define RFC_ULLRAM_BANK11028_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11028_DATA_S 0 //***************************************************************************** // @@ -18543,9 +18543,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11029_DATA_W 32 -#define RFC_ULLRAM_BANK11029_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11029_DATA_S 0 +#define RFC_ULLRAM_BANK11029_DATA_W 32 +#define RFC_ULLRAM_BANK11029_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11029_DATA_S 0 //***************************************************************************** // @@ -18555,9 +18555,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11030_DATA_W 32 -#define RFC_ULLRAM_BANK11030_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11030_DATA_S 0 +#define RFC_ULLRAM_BANK11030_DATA_W 32 +#define RFC_ULLRAM_BANK11030_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11030_DATA_S 0 //***************************************************************************** // @@ -18567,9 +18567,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11031_DATA_W 32 -#define RFC_ULLRAM_BANK11031_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11031_DATA_S 0 +#define RFC_ULLRAM_BANK11031_DATA_W 32 +#define RFC_ULLRAM_BANK11031_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11031_DATA_S 0 //***************************************************************************** // @@ -18579,9 +18579,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11032_DATA_W 32 -#define RFC_ULLRAM_BANK11032_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11032_DATA_S 0 +#define RFC_ULLRAM_BANK11032_DATA_W 32 +#define RFC_ULLRAM_BANK11032_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11032_DATA_S 0 //***************************************************************************** // @@ -18591,9 +18591,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11033_DATA_W 32 -#define RFC_ULLRAM_BANK11033_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11033_DATA_S 0 +#define RFC_ULLRAM_BANK11033_DATA_W 32 +#define RFC_ULLRAM_BANK11033_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11033_DATA_S 0 //***************************************************************************** // @@ -18603,9 +18603,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11034_DATA_W 32 -#define RFC_ULLRAM_BANK11034_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11034_DATA_S 0 +#define RFC_ULLRAM_BANK11034_DATA_W 32 +#define RFC_ULLRAM_BANK11034_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11034_DATA_S 0 //***************************************************************************** // @@ -18615,9 +18615,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11035_DATA_W 32 -#define RFC_ULLRAM_BANK11035_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11035_DATA_S 0 +#define RFC_ULLRAM_BANK11035_DATA_W 32 +#define RFC_ULLRAM_BANK11035_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11035_DATA_S 0 //***************************************************************************** // @@ -18627,9 +18627,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11036_DATA_W 32 -#define RFC_ULLRAM_BANK11036_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11036_DATA_S 0 +#define RFC_ULLRAM_BANK11036_DATA_W 32 +#define RFC_ULLRAM_BANK11036_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11036_DATA_S 0 //***************************************************************************** // @@ -18639,9 +18639,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11037_DATA_W 32 -#define RFC_ULLRAM_BANK11037_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11037_DATA_S 0 +#define RFC_ULLRAM_BANK11037_DATA_W 32 +#define RFC_ULLRAM_BANK11037_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11037_DATA_S 0 //***************************************************************************** // @@ -18651,9 +18651,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11038_DATA_W 32 -#define RFC_ULLRAM_BANK11038_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11038_DATA_S 0 +#define RFC_ULLRAM_BANK11038_DATA_W 32 +#define RFC_ULLRAM_BANK11038_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11038_DATA_S 0 //***************************************************************************** // @@ -18663,9 +18663,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11039_DATA_W 32 -#define RFC_ULLRAM_BANK11039_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11039_DATA_S 0 +#define RFC_ULLRAM_BANK11039_DATA_W 32 +#define RFC_ULLRAM_BANK11039_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11039_DATA_S 0 //***************************************************************************** // @@ -18675,9 +18675,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11040_DATA_W 32 -#define RFC_ULLRAM_BANK11040_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11040_DATA_S 0 +#define RFC_ULLRAM_BANK11040_DATA_W 32 +#define RFC_ULLRAM_BANK11040_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11040_DATA_S 0 //***************************************************************************** // @@ -18687,9 +18687,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11041_DATA_W 32 -#define RFC_ULLRAM_BANK11041_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11041_DATA_S 0 +#define RFC_ULLRAM_BANK11041_DATA_W 32 +#define RFC_ULLRAM_BANK11041_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11041_DATA_S 0 //***************************************************************************** // @@ -18699,9 +18699,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11042_DATA_W 32 -#define RFC_ULLRAM_BANK11042_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11042_DATA_S 0 +#define RFC_ULLRAM_BANK11042_DATA_W 32 +#define RFC_ULLRAM_BANK11042_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11042_DATA_S 0 //***************************************************************************** // @@ -18711,9 +18711,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11043_DATA_W 32 -#define RFC_ULLRAM_BANK11043_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11043_DATA_S 0 +#define RFC_ULLRAM_BANK11043_DATA_W 32 +#define RFC_ULLRAM_BANK11043_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11043_DATA_S 0 //***************************************************************************** // @@ -18723,9 +18723,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11044_DATA_W 32 -#define RFC_ULLRAM_BANK11044_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11044_DATA_S 0 +#define RFC_ULLRAM_BANK11044_DATA_W 32 +#define RFC_ULLRAM_BANK11044_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11044_DATA_S 0 //***************************************************************************** // @@ -18735,9 +18735,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11045_DATA_W 32 -#define RFC_ULLRAM_BANK11045_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11045_DATA_S 0 +#define RFC_ULLRAM_BANK11045_DATA_W 32 +#define RFC_ULLRAM_BANK11045_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11045_DATA_S 0 //***************************************************************************** // @@ -18747,9 +18747,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11046_DATA_W 32 -#define RFC_ULLRAM_BANK11046_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11046_DATA_S 0 +#define RFC_ULLRAM_BANK11046_DATA_W 32 +#define RFC_ULLRAM_BANK11046_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11046_DATA_S 0 //***************************************************************************** // @@ -18759,9 +18759,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11047_DATA_W 32 -#define RFC_ULLRAM_BANK11047_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11047_DATA_S 0 +#define RFC_ULLRAM_BANK11047_DATA_W 32 +#define RFC_ULLRAM_BANK11047_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11047_DATA_S 0 //***************************************************************************** // @@ -18771,9 +18771,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11048_DATA_W 32 -#define RFC_ULLRAM_BANK11048_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11048_DATA_S 0 +#define RFC_ULLRAM_BANK11048_DATA_W 32 +#define RFC_ULLRAM_BANK11048_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11048_DATA_S 0 //***************************************************************************** // @@ -18783,9 +18783,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11049_DATA_W 32 -#define RFC_ULLRAM_BANK11049_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11049_DATA_S 0 +#define RFC_ULLRAM_BANK11049_DATA_W 32 +#define RFC_ULLRAM_BANK11049_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11049_DATA_S 0 //***************************************************************************** // @@ -18795,9 +18795,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11050_DATA_W 32 -#define RFC_ULLRAM_BANK11050_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11050_DATA_S 0 +#define RFC_ULLRAM_BANK11050_DATA_W 32 +#define RFC_ULLRAM_BANK11050_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11050_DATA_S 0 //***************************************************************************** // @@ -18807,9 +18807,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11051_DATA_W 32 -#define RFC_ULLRAM_BANK11051_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11051_DATA_S 0 +#define RFC_ULLRAM_BANK11051_DATA_W 32 +#define RFC_ULLRAM_BANK11051_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11051_DATA_S 0 //***************************************************************************** // @@ -18819,9 +18819,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11052_DATA_W 32 -#define RFC_ULLRAM_BANK11052_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11052_DATA_S 0 +#define RFC_ULLRAM_BANK11052_DATA_W 32 +#define RFC_ULLRAM_BANK11052_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11052_DATA_S 0 //***************************************************************************** // @@ -18831,9 +18831,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11053_DATA_W 32 -#define RFC_ULLRAM_BANK11053_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11053_DATA_S 0 +#define RFC_ULLRAM_BANK11053_DATA_W 32 +#define RFC_ULLRAM_BANK11053_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11053_DATA_S 0 //***************************************************************************** // @@ -18843,9 +18843,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11054_DATA_W 32 -#define RFC_ULLRAM_BANK11054_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11054_DATA_S 0 +#define RFC_ULLRAM_BANK11054_DATA_W 32 +#define RFC_ULLRAM_BANK11054_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11054_DATA_S 0 //***************************************************************************** // @@ -18855,9 +18855,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11055_DATA_W 32 -#define RFC_ULLRAM_BANK11055_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11055_DATA_S 0 +#define RFC_ULLRAM_BANK11055_DATA_W 32 +#define RFC_ULLRAM_BANK11055_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11055_DATA_S 0 //***************************************************************************** // @@ -18867,9 +18867,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11056_DATA_W 32 -#define RFC_ULLRAM_BANK11056_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11056_DATA_S 0 +#define RFC_ULLRAM_BANK11056_DATA_W 32 +#define RFC_ULLRAM_BANK11056_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11056_DATA_S 0 //***************************************************************************** // @@ -18879,9 +18879,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11057_DATA_W 32 -#define RFC_ULLRAM_BANK11057_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11057_DATA_S 0 +#define RFC_ULLRAM_BANK11057_DATA_W 32 +#define RFC_ULLRAM_BANK11057_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11057_DATA_S 0 //***************************************************************************** // @@ -18891,9 +18891,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11058_DATA_W 32 -#define RFC_ULLRAM_BANK11058_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11058_DATA_S 0 +#define RFC_ULLRAM_BANK11058_DATA_W 32 +#define RFC_ULLRAM_BANK11058_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11058_DATA_S 0 //***************************************************************************** // @@ -18903,9 +18903,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11059_DATA_W 32 -#define RFC_ULLRAM_BANK11059_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11059_DATA_S 0 +#define RFC_ULLRAM_BANK11059_DATA_W 32 +#define RFC_ULLRAM_BANK11059_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11059_DATA_S 0 //***************************************************************************** // @@ -18915,9 +18915,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11060_DATA_W 32 -#define RFC_ULLRAM_BANK11060_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11060_DATA_S 0 +#define RFC_ULLRAM_BANK11060_DATA_W 32 +#define RFC_ULLRAM_BANK11060_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11060_DATA_S 0 //***************************************************************************** // @@ -18927,9 +18927,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11061_DATA_W 32 -#define RFC_ULLRAM_BANK11061_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11061_DATA_S 0 +#define RFC_ULLRAM_BANK11061_DATA_W 32 +#define RFC_ULLRAM_BANK11061_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11061_DATA_S 0 //***************************************************************************** // @@ -18939,9 +18939,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11062_DATA_W 32 -#define RFC_ULLRAM_BANK11062_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11062_DATA_S 0 +#define RFC_ULLRAM_BANK11062_DATA_W 32 +#define RFC_ULLRAM_BANK11062_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11062_DATA_S 0 //***************************************************************************** // @@ -18951,9 +18951,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11063_DATA_W 32 -#define RFC_ULLRAM_BANK11063_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11063_DATA_S 0 +#define RFC_ULLRAM_BANK11063_DATA_W 32 +#define RFC_ULLRAM_BANK11063_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11063_DATA_S 0 //***************************************************************************** // @@ -18963,9 +18963,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11064_DATA_W 32 -#define RFC_ULLRAM_BANK11064_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11064_DATA_S 0 +#define RFC_ULLRAM_BANK11064_DATA_W 32 +#define RFC_ULLRAM_BANK11064_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11064_DATA_S 0 //***************************************************************************** // @@ -18975,9 +18975,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11065_DATA_W 32 -#define RFC_ULLRAM_BANK11065_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11065_DATA_S 0 +#define RFC_ULLRAM_BANK11065_DATA_W 32 +#define RFC_ULLRAM_BANK11065_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11065_DATA_S 0 //***************************************************************************** // @@ -18987,9 +18987,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11066_DATA_W 32 -#define RFC_ULLRAM_BANK11066_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11066_DATA_S 0 +#define RFC_ULLRAM_BANK11066_DATA_W 32 +#define RFC_ULLRAM_BANK11066_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11066_DATA_S 0 //***************************************************************************** // @@ -18999,9 +18999,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11067_DATA_W 32 -#define RFC_ULLRAM_BANK11067_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11067_DATA_S 0 +#define RFC_ULLRAM_BANK11067_DATA_W 32 +#define RFC_ULLRAM_BANK11067_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11067_DATA_S 0 //***************************************************************************** // @@ -19011,9 +19011,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11068_DATA_W 32 -#define RFC_ULLRAM_BANK11068_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11068_DATA_S 0 +#define RFC_ULLRAM_BANK11068_DATA_W 32 +#define RFC_ULLRAM_BANK11068_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11068_DATA_S 0 //***************************************************************************** // @@ -19023,9 +19023,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11069_DATA_W 32 -#define RFC_ULLRAM_BANK11069_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11069_DATA_S 0 +#define RFC_ULLRAM_BANK11069_DATA_W 32 +#define RFC_ULLRAM_BANK11069_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11069_DATA_S 0 //***************************************************************************** // @@ -19035,9 +19035,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11070_DATA_W 32 -#define RFC_ULLRAM_BANK11070_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11070_DATA_S 0 +#define RFC_ULLRAM_BANK11070_DATA_W 32 +#define RFC_ULLRAM_BANK11070_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11070_DATA_S 0 //***************************************************************************** // @@ -19047,9 +19047,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11071_DATA_W 32 -#define RFC_ULLRAM_BANK11071_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11071_DATA_S 0 +#define RFC_ULLRAM_BANK11071_DATA_W 32 +#define RFC_ULLRAM_BANK11071_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11071_DATA_S 0 //***************************************************************************** // @@ -19059,9 +19059,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11072_DATA_W 32 -#define RFC_ULLRAM_BANK11072_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11072_DATA_S 0 +#define RFC_ULLRAM_BANK11072_DATA_W 32 +#define RFC_ULLRAM_BANK11072_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11072_DATA_S 0 //***************************************************************************** // @@ -19071,9 +19071,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11073_DATA_W 32 -#define RFC_ULLRAM_BANK11073_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11073_DATA_S 0 +#define RFC_ULLRAM_BANK11073_DATA_W 32 +#define RFC_ULLRAM_BANK11073_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11073_DATA_S 0 //***************************************************************************** // @@ -19083,9 +19083,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11074_DATA_W 32 -#define RFC_ULLRAM_BANK11074_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11074_DATA_S 0 +#define RFC_ULLRAM_BANK11074_DATA_W 32 +#define RFC_ULLRAM_BANK11074_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11074_DATA_S 0 //***************************************************************************** // @@ -19095,9 +19095,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11075_DATA_W 32 -#define RFC_ULLRAM_BANK11075_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11075_DATA_S 0 +#define RFC_ULLRAM_BANK11075_DATA_W 32 +#define RFC_ULLRAM_BANK11075_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11075_DATA_S 0 //***************************************************************************** // @@ -19107,9 +19107,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11076_DATA_W 32 -#define RFC_ULLRAM_BANK11076_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11076_DATA_S 0 +#define RFC_ULLRAM_BANK11076_DATA_W 32 +#define RFC_ULLRAM_BANK11076_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11076_DATA_S 0 //***************************************************************************** // @@ -19119,9 +19119,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11077_DATA_W 32 -#define RFC_ULLRAM_BANK11077_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11077_DATA_S 0 +#define RFC_ULLRAM_BANK11077_DATA_W 32 +#define RFC_ULLRAM_BANK11077_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11077_DATA_S 0 //***************************************************************************** // @@ -19131,9 +19131,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11078_DATA_W 32 -#define RFC_ULLRAM_BANK11078_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11078_DATA_S 0 +#define RFC_ULLRAM_BANK11078_DATA_W 32 +#define RFC_ULLRAM_BANK11078_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11078_DATA_S 0 //***************************************************************************** // @@ -19143,9 +19143,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11079_DATA_W 32 -#define RFC_ULLRAM_BANK11079_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11079_DATA_S 0 +#define RFC_ULLRAM_BANK11079_DATA_W 32 +#define RFC_ULLRAM_BANK11079_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11079_DATA_S 0 //***************************************************************************** // @@ -19155,9 +19155,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11080_DATA_W 32 -#define RFC_ULLRAM_BANK11080_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11080_DATA_S 0 +#define RFC_ULLRAM_BANK11080_DATA_W 32 +#define RFC_ULLRAM_BANK11080_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11080_DATA_S 0 //***************************************************************************** // @@ -19167,9 +19167,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11081_DATA_W 32 -#define RFC_ULLRAM_BANK11081_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11081_DATA_S 0 +#define RFC_ULLRAM_BANK11081_DATA_W 32 +#define RFC_ULLRAM_BANK11081_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11081_DATA_S 0 //***************************************************************************** // @@ -19179,9 +19179,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11082_DATA_W 32 -#define RFC_ULLRAM_BANK11082_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11082_DATA_S 0 +#define RFC_ULLRAM_BANK11082_DATA_W 32 +#define RFC_ULLRAM_BANK11082_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11082_DATA_S 0 //***************************************************************************** // @@ -19191,9 +19191,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11083_DATA_W 32 -#define RFC_ULLRAM_BANK11083_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11083_DATA_S 0 +#define RFC_ULLRAM_BANK11083_DATA_W 32 +#define RFC_ULLRAM_BANK11083_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11083_DATA_S 0 //***************************************************************************** // @@ -19203,9 +19203,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11084_DATA_W 32 -#define RFC_ULLRAM_BANK11084_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11084_DATA_S 0 +#define RFC_ULLRAM_BANK11084_DATA_W 32 +#define RFC_ULLRAM_BANK11084_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11084_DATA_S 0 //***************************************************************************** // @@ -19215,9 +19215,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11085_DATA_W 32 -#define RFC_ULLRAM_BANK11085_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11085_DATA_S 0 +#define RFC_ULLRAM_BANK11085_DATA_W 32 +#define RFC_ULLRAM_BANK11085_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11085_DATA_S 0 //***************************************************************************** // @@ -19227,9 +19227,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11086_DATA_W 32 -#define RFC_ULLRAM_BANK11086_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11086_DATA_S 0 +#define RFC_ULLRAM_BANK11086_DATA_W 32 +#define RFC_ULLRAM_BANK11086_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11086_DATA_S 0 //***************************************************************************** // @@ -19239,9 +19239,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11087_DATA_W 32 -#define RFC_ULLRAM_BANK11087_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11087_DATA_S 0 +#define RFC_ULLRAM_BANK11087_DATA_W 32 +#define RFC_ULLRAM_BANK11087_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11087_DATA_S 0 //***************************************************************************** // @@ -19251,9 +19251,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11088_DATA_W 32 -#define RFC_ULLRAM_BANK11088_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11088_DATA_S 0 +#define RFC_ULLRAM_BANK11088_DATA_W 32 +#define RFC_ULLRAM_BANK11088_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11088_DATA_S 0 //***************************************************************************** // @@ -19263,9 +19263,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11089_DATA_W 32 -#define RFC_ULLRAM_BANK11089_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11089_DATA_S 0 +#define RFC_ULLRAM_BANK11089_DATA_W 32 +#define RFC_ULLRAM_BANK11089_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11089_DATA_S 0 //***************************************************************************** // @@ -19275,9 +19275,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11090_DATA_W 32 -#define RFC_ULLRAM_BANK11090_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11090_DATA_S 0 +#define RFC_ULLRAM_BANK11090_DATA_W 32 +#define RFC_ULLRAM_BANK11090_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11090_DATA_S 0 //***************************************************************************** // @@ -19287,9 +19287,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11091_DATA_W 32 -#define RFC_ULLRAM_BANK11091_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11091_DATA_S 0 +#define RFC_ULLRAM_BANK11091_DATA_W 32 +#define RFC_ULLRAM_BANK11091_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11091_DATA_S 0 //***************************************************************************** // @@ -19299,9 +19299,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11092_DATA_W 32 -#define RFC_ULLRAM_BANK11092_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11092_DATA_S 0 +#define RFC_ULLRAM_BANK11092_DATA_W 32 +#define RFC_ULLRAM_BANK11092_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11092_DATA_S 0 //***************************************************************************** // @@ -19311,9 +19311,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11093_DATA_W 32 -#define RFC_ULLRAM_BANK11093_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11093_DATA_S 0 +#define RFC_ULLRAM_BANK11093_DATA_W 32 +#define RFC_ULLRAM_BANK11093_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11093_DATA_S 0 //***************************************************************************** // @@ -19323,9 +19323,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11094_DATA_W 32 -#define RFC_ULLRAM_BANK11094_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11094_DATA_S 0 +#define RFC_ULLRAM_BANK11094_DATA_W 32 +#define RFC_ULLRAM_BANK11094_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11094_DATA_S 0 //***************************************************************************** // @@ -19335,9 +19335,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11095_DATA_W 32 -#define RFC_ULLRAM_BANK11095_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11095_DATA_S 0 +#define RFC_ULLRAM_BANK11095_DATA_W 32 +#define RFC_ULLRAM_BANK11095_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11095_DATA_S 0 //***************************************************************************** // @@ -19347,9 +19347,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11096_DATA_W 32 -#define RFC_ULLRAM_BANK11096_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11096_DATA_S 0 +#define RFC_ULLRAM_BANK11096_DATA_W 32 +#define RFC_ULLRAM_BANK11096_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11096_DATA_S 0 //***************************************************************************** // @@ -19359,9 +19359,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11097_DATA_W 32 -#define RFC_ULLRAM_BANK11097_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11097_DATA_S 0 +#define RFC_ULLRAM_BANK11097_DATA_W 32 +#define RFC_ULLRAM_BANK11097_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11097_DATA_S 0 //***************************************************************************** // @@ -19371,9 +19371,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11098_DATA_W 32 -#define RFC_ULLRAM_BANK11098_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11098_DATA_S 0 +#define RFC_ULLRAM_BANK11098_DATA_W 32 +#define RFC_ULLRAM_BANK11098_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11098_DATA_S 0 //***************************************************************************** // @@ -19383,9 +19383,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11099_DATA_W 32 -#define RFC_ULLRAM_BANK11099_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11099_DATA_S 0 +#define RFC_ULLRAM_BANK11099_DATA_W 32 +#define RFC_ULLRAM_BANK11099_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11099_DATA_S 0 //***************************************************************************** // @@ -19395,9 +19395,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11100_DATA_W 32 -#define RFC_ULLRAM_BANK11100_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11100_DATA_S 0 +#define RFC_ULLRAM_BANK11100_DATA_W 32 +#define RFC_ULLRAM_BANK11100_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11100_DATA_S 0 //***************************************************************************** // @@ -19407,9 +19407,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11101_DATA_W 32 -#define RFC_ULLRAM_BANK11101_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11101_DATA_S 0 +#define RFC_ULLRAM_BANK11101_DATA_W 32 +#define RFC_ULLRAM_BANK11101_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11101_DATA_S 0 //***************************************************************************** // @@ -19419,9 +19419,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11102_DATA_W 32 -#define RFC_ULLRAM_BANK11102_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11102_DATA_S 0 +#define RFC_ULLRAM_BANK11102_DATA_W 32 +#define RFC_ULLRAM_BANK11102_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11102_DATA_S 0 //***************************************************************************** // @@ -19431,9 +19431,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11103_DATA_W 32 -#define RFC_ULLRAM_BANK11103_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11103_DATA_S 0 +#define RFC_ULLRAM_BANK11103_DATA_W 32 +#define RFC_ULLRAM_BANK11103_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11103_DATA_S 0 //***************************************************************************** // @@ -19443,9 +19443,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11104_DATA_W 32 -#define RFC_ULLRAM_BANK11104_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11104_DATA_S 0 +#define RFC_ULLRAM_BANK11104_DATA_W 32 +#define RFC_ULLRAM_BANK11104_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11104_DATA_S 0 //***************************************************************************** // @@ -19455,9 +19455,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11105_DATA_W 32 -#define RFC_ULLRAM_BANK11105_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11105_DATA_S 0 +#define RFC_ULLRAM_BANK11105_DATA_W 32 +#define RFC_ULLRAM_BANK11105_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11105_DATA_S 0 //***************************************************************************** // @@ -19467,9 +19467,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11106_DATA_W 32 -#define RFC_ULLRAM_BANK11106_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11106_DATA_S 0 +#define RFC_ULLRAM_BANK11106_DATA_W 32 +#define RFC_ULLRAM_BANK11106_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11106_DATA_S 0 //***************************************************************************** // @@ -19479,9 +19479,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11107_DATA_W 32 -#define RFC_ULLRAM_BANK11107_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11107_DATA_S 0 +#define RFC_ULLRAM_BANK11107_DATA_W 32 +#define RFC_ULLRAM_BANK11107_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11107_DATA_S 0 //***************************************************************************** // @@ -19491,9 +19491,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11108_DATA_W 32 -#define RFC_ULLRAM_BANK11108_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11108_DATA_S 0 +#define RFC_ULLRAM_BANK11108_DATA_W 32 +#define RFC_ULLRAM_BANK11108_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11108_DATA_S 0 //***************************************************************************** // @@ -19503,9 +19503,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11109_DATA_W 32 -#define RFC_ULLRAM_BANK11109_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11109_DATA_S 0 +#define RFC_ULLRAM_BANK11109_DATA_W 32 +#define RFC_ULLRAM_BANK11109_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11109_DATA_S 0 //***************************************************************************** // @@ -19515,9 +19515,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11110_DATA_W 32 -#define RFC_ULLRAM_BANK11110_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11110_DATA_S 0 +#define RFC_ULLRAM_BANK11110_DATA_W 32 +#define RFC_ULLRAM_BANK11110_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11110_DATA_S 0 //***************************************************************************** // @@ -19527,9 +19527,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11111_DATA_W 32 -#define RFC_ULLRAM_BANK11111_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11111_DATA_S 0 +#define RFC_ULLRAM_BANK11111_DATA_W 32 +#define RFC_ULLRAM_BANK11111_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11111_DATA_S 0 //***************************************************************************** // @@ -19539,9 +19539,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11112_DATA_W 32 -#define RFC_ULLRAM_BANK11112_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11112_DATA_S 0 +#define RFC_ULLRAM_BANK11112_DATA_W 32 +#define RFC_ULLRAM_BANK11112_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11112_DATA_S 0 //***************************************************************************** // @@ -19551,9 +19551,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11113_DATA_W 32 -#define RFC_ULLRAM_BANK11113_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11113_DATA_S 0 +#define RFC_ULLRAM_BANK11113_DATA_W 32 +#define RFC_ULLRAM_BANK11113_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11113_DATA_S 0 //***************************************************************************** // @@ -19563,9 +19563,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11114_DATA_W 32 -#define RFC_ULLRAM_BANK11114_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11114_DATA_S 0 +#define RFC_ULLRAM_BANK11114_DATA_W 32 +#define RFC_ULLRAM_BANK11114_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11114_DATA_S 0 //***************************************************************************** // @@ -19575,9 +19575,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11115_DATA_W 32 -#define RFC_ULLRAM_BANK11115_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11115_DATA_S 0 +#define RFC_ULLRAM_BANK11115_DATA_W 32 +#define RFC_ULLRAM_BANK11115_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11115_DATA_S 0 //***************************************************************************** // @@ -19587,9 +19587,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11116_DATA_W 32 -#define RFC_ULLRAM_BANK11116_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11116_DATA_S 0 +#define RFC_ULLRAM_BANK11116_DATA_W 32 +#define RFC_ULLRAM_BANK11116_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11116_DATA_S 0 //***************************************************************************** // @@ -19599,9 +19599,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11117_DATA_W 32 -#define RFC_ULLRAM_BANK11117_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11117_DATA_S 0 +#define RFC_ULLRAM_BANK11117_DATA_W 32 +#define RFC_ULLRAM_BANK11117_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11117_DATA_S 0 //***************************************************************************** // @@ -19611,9 +19611,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11118_DATA_W 32 -#define RFC_ULLRAM_BANK11118_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11118_DATA_S 0 +#define RFC_ULLRAM_BANK11118_DATA_W 32 +#define RFC_ULLRAM_BANK11118_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11118_DATA_S 0 //***************************************************************************** // @@ -19623,9 +19623,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11119_DATA_W 32 -#define RFC_ULLRAM_BANK11119_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11119_DATA_S 0 +#define RFC_ULLRAM_BANK11119_DATA_W 32 +#define RFC_ULLRAM_BANK11119_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11119_DATA_S 0 //***************************************************************************** // @@ -19635,9 +19635,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11120_DATA_W 32 -#define RFC_ULLRAM_BANK11120_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11120_DATA_S 0 +#define RFC_ULLRAM_BANK11120_DATA_W 32 +#define RFC_ULLRAM_BANK11120_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11120_DATA_S 0 //***************************************************************************** // @@ -19647,9 +19647,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11121_DATA_W 32 -#define RFC_ULLRAM_BANK11121_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11121_DATA_S 0 +#define RFC_ULLRAM_BANK11121_DATA_W 32 +#define RFC_ULLRAM_BANK11121_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11121_DATA_S 0 //***************************************************************************** // @@ -19659,9 +19659,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11122_DATA_W 32 -#define RFC_ULLRAM_BANK11122_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11122_DATA_S 0 +#define RFC_ULLRAM_BANK11122_DATA_W 32 +#define RFC_ULLRAM_BANK11122_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11122_DATA_S 0 //***************************************************************************** // @@ -19671,9 +19671,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11123_DATA_W 32 -#define RFC_ULLRAM_BANK11123_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11123_DATA_S 0 +#define RFC_ULLRAM_BANK11123_DATA_W 32 +#define RFC_ULLRAM_BANK11123_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11123_DATA_S 0 //***************************************************************************** // @@ -19683,9 +19683,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11124_DATA_W 32 -#define RFC_ULLRAM_BANK11124_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11124_DATA_S 0 +#define RFC_ULLRAM_BANK11124_DATA_W 32 +#define RFC_ULLRAM_BANK11124_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11124_DATA_S 0 //***************************************************************************** // @@ -19695,9 +19695,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11125_DATA_W 32 -#define RFC_ULLRAM_BANK11125_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11125_DATA_S 0 +#define RFC_ULLRAM_BANK11125_DATA_W 32 +#define RFC_ULLRAM_BANK11125_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11125_DATA_S 0 //***************************************************************************** // @@ -19707,9 +19707,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11126_DATA_W 32 -#define RFC_ULLRAM_BANK11126_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11126_DATA_S 0 +#define RFC_ULLRAM_BANK11126_DATA_W 32 +#define RFC_ULLRAM_BANK11126_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11126_DATA_S 0 //***************************************************************************** // @@ -19719,9 +19719,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11127_DATA_W 32 -#define RFC_ULLRAM_BANK11127_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11127_DATA_S 0 +#define RFC_ULLRAM_BANK11127_DATA_W 32 +#define RFC_ULLRAM_BANK11127_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11127_DATA_S 0 //***************************************************************************** // @@ -19731,9 +19731,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11128_DATA_W 32 -#define RFC_ULLRAM_BANK11128_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11128_DATA_S 0 +#define RFC_ULLRAM_BANK11128_DATA_W 32 +#define RFC_ULLRAM_BANK11128_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11128_DATA_S 0 //***************************************************************************** // @@ -19743,9 +19743,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11129_DATA_W 32 -#define RFC_ULLRAM_BANK11129_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11129_DATA_S 0 +#define RFC_ULLRAM_BANK11129_DATA_W 32 +#define RFC_ULLRAM_BANK11129_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11129_DATA_S 0 //***************************************************************************** // @@ -19755,9 +19755,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11130_DATA_W 32 -#define RFC_ULLRAM_BANK11130_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11130_DATA_S 0 +#define RFC_ULLRAM_BANK11130_DATA_W 32 +#define RFC_ULLRAM_BANK11130_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11130_DATA_S 0 //***************************************************************************** // @@ -19767,9 +19767,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11131_DATA_W 32 -#define RFC_ULLRAM_BANK11131_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11131_DATA_S 0 +#define RFC_ULLRAM_BANK11131_DATA_W 32 +#define RFC_ULLRAM_BANK11131_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11131_DATA_S 0 //***************************************************************************** // @@ -19779,9 +19779,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11132_DATA_W 32 -#define RFC_ULLRAM_BANK11132_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11132_DATA_S 0 +#define RFC_ULLRAM_BANK11132_DATA_W 32 +#define RFC_ULLRAM_BANK11132_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11132_DATA_S 0 //***************************************************************************** // @@ -19791,9 +19791,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11133_DATA_W 32 -#define RFC_ULLRAM_BANK11133_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11133_DATA_S 0 +#define RFC_ULLRAM_BANK11133_DATA_W 32 +#define RFC_ULLRAM_BANK11133_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11133_DATA_S 0 //***************************************************************************** // @@ -19803,9 +19803,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11134_DATA_W 32 -#define RFC_ULLRAM_BANK11134_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11134_DATA_S 0 +#define RFC_ULLRAM_BANK11134_DATA_W 32 +#define RFC_ULLRAM_BANK11134_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11134_DATA_S 0 //***************************************************************************** // @@ -19815,9 +19815,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11135_DATA_W 32 -#define RFC_ULLRAM_BANK11135_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11135_DATA_S 0 +#define RFC_ULLRAM_BANK11135_DATA_W 32 +#define RFC_ULLRAM_BANK11135_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11135_DATA_S 0 //***************************************************************************** // @@ -19827,9 +19827,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11136_DATA_W 32 -#define RFC_ULLRAM_BANK11136_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11136_DATA_S 0 +#define RFC_ULLRAM_BANK11136_DATA_W 32 +#define RFC_ULLRAM_BANK11136_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11136_DATA_S 0 //***************************************************************************** // @@ -19839,9 +19839,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11137_DATA_W 32 -#define RFC_ULLRAM_BANK11137_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11137_DATA_S 0 +#define RFC_ULLRAM_BANK11137_DATA_W 32 +#define RFC_ULLRAM_BANK11137_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11137_DATA_S 0 //***************************************************************************** // @@ -19851,9 +19851,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11138_DATA_W 32 -#define RFC_ULLRAM_BANK11138_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11138_DATA_S 0 +#define RFC_ULLRAM_BANK11138_DATA_W 32 +#define RFC_ULLRAM_BANK11138_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11138_DATA_S 0 //***************************************************************************** // @@ -19863,9 +19863,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11139_DATA_W 32 -#define RFC_ULLRAM_BANK11139_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11139_DATA_S 0 +#define RFC_ULLRAM_BANK11139_DATA_W 32 +#define RFC_ULLRAM_BANK11139_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11139_DATA_S 0 //***************************************************************************** // @@ -19875,9 +19875,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11140_DATA_W 32 -#define RFC_ULLRAM_BANK11140_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11140_DATA_S 0 +#define RFC_ULLRAM_BANK11140_DATA_W 32 +#define RFC_ULLRAM_BANK11140_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11140_DATA_S 0 //***************************************************************************** // @@ -19887,9 +19887,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11141_DATA_W 32 -#define RFC_ULLRAM_BANK11141_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11141_DATA_S 0 +#define RFC_ULLRAM_BANK11141_DATA_W 32 +#define RFC_ULLRAM_BANK11141_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11141_DATA_S 0 //***************************************************************************** // @@ -19899,9 +19899,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11142_DATA_W 32 -#define RFC_ULLRAM_BANK11142_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11142_DATA_S 0 +#define RFC_ULLRAM_BANK11142_DATA_W 32 +#define RFC_ULLRAM_BANK11142_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11142_DATA_S 0 //***************************************************************************** // @@ -19911,9 +19911,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11143_DATA_W 32 -#define RFC_ULLRAM_BANK11143_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11143_DATA_S 0 +#define RFC_ULLRAM_BANK11143_DATA_W 32 +#define RFC_ULLRAM_BANK11143_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11143_DATA_S 0 //***************************************************************************** // @@ -19923,9 +19923,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11144_DATA_W 32 -#define RFC_ULLRAM_BANK11144_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11144_DATA_S 0 +#define RFC_ULLRAM_BANK11144_DATA_W 32 +#define RFC_ULLRAM_BANK11144_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11144_DATA_S 0 //***************************************************************************** // @@ -19935,9 +19935,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11145_DATA_W 32 -#define RFC_ULLRAM_BANK11145_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11145_DATA_S 0 +#define RFC_ULLRAM_BANK11145_DATA_W 32 +#define RFC_ULLRAM_BANK11145_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11145_DATA_S 0 //***************************************************************************** // @@ -19947,9 +19947,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11146_DATA_W 32 -#define RFC_ULLRAM_BANK11146_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11146_DATA_S 0 +#define RFC_ULLRAM_BANK11146_DATA_W 32 +#define RFC_ULLRAM_BANK11146_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11146_DATA_S 0 //***************************************************************************** // @@ -19959,9 +19959,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11147_DATA_W 32 -#define RFC_ULLRAM_BANK11147_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11147_DATA_S 0 +#define RFC_ULLRAM_BANK11147_DATA_W 32 +#define RFC_ULLRAM_BANK11147_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11147_DATA_S 0 //***************************************************************************** // @@ -19971,9 +19971,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11148_DATA_W 32 -#define RFC_ULLRAM_BANK11148_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11148_DATA_S 0 +#define RFC_ULLRAM_BANK11148_DATA_W 32 +#define RFC_ULLRAM_BANK11148_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11148_DATA_S 0 //***************************************************************************** // @@ -19983,9 +19983,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11149_DATA_W 32 -#define RFC_ULLRAM_BANK11149_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11149_DATA_S 0 +#define RFC_ULLRAM_BANK11149_DATA_W 32 +#define RFC_ULLRAM_BANK11149_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11149_DATA_S 0 //***************************************************************************** // @@ -19995,9 +19995,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11150_DATA_W 32 -#define RFC_ULLRAM_BANK11150_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11150_DATA_S 0 +#define RFC_ULLRAM_BANK11150_DATA_W 32 +#define RFC_ULLRAM_BANK11150_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11150_DATA_S 0 //***************************************************************************** // @@ -20007,9 +20007,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11151_DATA_W 32 -#define RFC_ULLRAM_BANK11151_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11151_DATA_S 0 +#define RFC_ULLRAM_BANK11151_DATA_W 32 +#define RFC_ULLRAM_BANK11151_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11151_DATA_S 0 //***************************************************************************** // @@ -20019,9 +20019,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11152_DATA_W 32 -#define RFC_ULLRAM_BANK11152_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11152_DATA_S 0 +#define RFC_ULLRAM_BANK11152_DATA_W 32 +#define RFC_ULLRAM_BANK11152_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11152_DATA_S 0 //***************************************************************************** // @@ -20031,9 +20031,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11153_DATA_W 32 -#define RFC_ULLRAM_BANK11153_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11153_DATA_S 0 +#define RFC_ULLRAM_BANK11153_DATA_W 32 +#define RFC_ULLRAM_BANK11153_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11153_DATA_S 0 //***************************************************************************** // @@ -20043,9 +20043,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11154_DATA_W 32 -#define RFC_ULLRAM_BANK11154_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11154_DATA_S 0 +#define RFC_ULLRAM_BANK11154_DATA_W 32 +#define RFC_ULLRAM_BANK11154_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11154_DATA_S 0 //***************************************************************************** // @@ -20055,9 +20055,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11155_DATA_W 32 -#define RFC_ULLRAM_BANK11155_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11155_DATA_S 0 +#define RFC_ULLRAM_BANK11155_DATA_W 32 +#define RFC_ULLRAM_BANK11155_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11155_DATA_S 0 //***************************************************************************** // @@ -20067,9 +20067,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11156_DATA_W 32 -#define RFC_ULLRAM_BANK11156_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11156_DATA_S 0 +#define RFC_ULLRAM_BANK11156_DATA_W 32 +#define RFC_ULLRAM_BANK11156_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11156_DATA_S 0 //***************************************************************************** // @@ -20079,9 +20079,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11157_DATA_W 32 -#define RFC_ULLRAM_BANK11157_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11157_DATA_S 0 +#define RFC_ULLRAM_BANK11157_DATA_W 32 +#define RFC_ULLRAM_BANK11157_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11157_DATA_S 0 //***************************************************************************** // @@ -20091,9 +20091,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11158_DATA_W 32 -#define RFC_ULLRAM_BANK11158_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11158_DATA_S 0 +#define RFC_ULLRAM_BANK11158_DATA_W 32 +#define RFC_ULLRAM_BANK11158_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11158_DATA_S 0 //***************************************************************************** // @@ -20103,9 +20103,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11159_DATA_W 32 -#define RFC_ULLRAM_BANK11159_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11159_DATA_S 0 +#define RFC_ULLRAM_BANK11159_DATA_W 32 +#define RFC_ULLRAM_BANK11159_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11159_DATA_S 0 //***************************************************************************** // @@ -20115,9 +20115,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11160_DATA_W 32 -#define RFC_ULLRAM_BANK11160_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11160_DATA_S 0 +#define RFC_ULLRAM_BANK11160_DATA_W 32 +#define RFC_ULLRAM_BANK11160_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11160_DATA_S 0 //***************************************************************************** // @@ -20127,9 +20127,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11161_DATA_W 32 -#define RFC_ULLRAM_BANK11161_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11161_DATA_S 0 +#define RFC_ULLRAM_BANK11161_DATA_W 32 +#define RFC_ULLRAM_BANK11161_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11161_DATA_S 0 //***************************************************************************** // @@ -20139,9 +20139,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11162_DATA_W 32 -#define RFC_ULLRAM_BANK11162_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11162_DATA_S 0 +#define RFC_ULLRAM_BANK11162_DATA_W 32 +#define RFC_ULLRAM_BANK11162_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11162_DATA_S 0 //***************************************************************************** // @@ -20151,9 +20151,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11163_DATA_W 32 -#define RFC_ULLRAM_BANK11163_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11163_DATA_S 0 +#define RFC_ULLRAM_BANK11163_DATA_W 32 +#define RFC_ULLRAM_BANK11163_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11163_DATA_S 0 //***************************************************************************** // @@ -20163,9 +20163,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11164_DATA_W 32 -#define RFC_ULLRAM_BANK11164_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11164_DATA_S 0 +#define RFC_ULLRAM_BANK11164_DATA_W 32 +#define RFC_ULLRAM_BANK11164_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11164_DATA_S 0 //***************************************************************************** // @@ -20175,9 +20175,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11165_DATA_W 32 -#define RFC_ULLRAM_BANK11165_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11165_DATA_S 0 +#define RFC_ULLRAM_BANK11165_DATA_W 32 +#define RFC_ULLRAM_BANK11165_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11165_DATA_S 0 //***************************************************************************** // @@ -20187,9 +20187,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11166_DATA_W 32 -#define RFC_ULLRAM_BANK11166_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11166_DATA_S 0 +#define RFC_ULLRAM_BANK11166_DATA_W 32 +#define RFC_ULLRAM_BANK11166_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11166_DATA_S 0 //***************************************************************************** // @@ -20199,9 +20199,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11167_DATA_W 32 -#define RFC_ULLRAM_BANK11167_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11167_DATA_S 0 +#define RFC_ULLRAM_BANK11167_DATA_W 32 +#define RFC_ULLRAM_BANK11167_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11167_DATA_S 0 //***************************************************************************** // @@ -20211,9 +20211,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11168_DATA_W 32 -#define RFC_ULLRAM_BANK11168_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11168_DATA_S 0 +#define RFC_ULLRAM_BANK11168_DATA_W 32 +#define RFC_ULLRAM_BANK11168_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11168_DATA_S 0 //***************************************************************************** // @@ -20223,9 +20223,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11169_DATA_W 32 -#define RFC_ULLRAM_BANK11169_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11169_DATA_S 0 +#define RFC_ULLRAM_BANK11169_DATA_W 32 +#define RFC_ULLRAM_BANK11169_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11169_DATA_S 0 //***************************************************************************** // @@ -20235,9 +20235,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11170_DATA_W 32 -#define RFC_ULLRAM_BANK11170_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11170_DATA_S 0 +#define RFC_ULLRAM_BANK11170_DATA_W 32 +#define RFC_ULLRAM_BANK11170_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11170_DATA_S 0 //***************************************************************************** // @@ -20247,9 +20247,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11171_DATA_W 32 -#define RFC_ULLRAM_BANK11171_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11171_DATA_S 0 +#define RFC_ULLRAM_BANK11171_DATA_W 32 +#define RFC_ULLRAM_BANK11171_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11171_DATA_S 0 //***************************************************************************** // @@ -20259,9 +20259,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11172_DATA_W 32 -#define RFC_ULLRAM_BANK11172_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11172_DATA_S 0 +#define RFC_ULLRAM_BANK11172_DATA_W 32 +#define RFC_ULLRAM_BANK11172_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11172_DATA_S 0 //***************************************************************************** // @@ -20271,9 +20271,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11173_DATA_W 32 -#define RFC_ULLRAM_BANK11173_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11173_DATA_S 0 +#define RFC_ULLRAM_BANK11173_DATA_W 32 +#define RFC_ULLRAM_BANK11173_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11173_DATA_S 0 //***************************************************************************** // @@ -20283,9 +20283,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11174_DATA_W 32 -#define RFC_ULLRAM_BANK11174_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11174_DATA_S 0 +#define RFC_ULLRAM_BANK11174_DATA_W 32 +#define RFC_ULLRAM_BANK11174_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11174_DATA_S 0 //***************************************************************************** // @@ -20295,9 +20295,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11175_DATA_W 32 -#define RFC_ULLRAM_BANK11175_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11175_DATA_S 0 +#define RFC_ULLRAM_BANK11175_DATA_W 32 +#define RFC_ULLRAM_BANK11175_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11175_DATA_S 0 //***************************************************************************** // @@ -20307,9 +20307,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11176_DATA_W 32 -#define RFC_ULLRAM_BANK11176_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11176_DATA_S 0 +#define RFC_ULLRAM_BANK11176_DATA_W 32 +#define RFC_ULLRAM_BANK11176_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11176_DATA_S 0 //***************************************************************************** // @@ -20319,9 +20319,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11177_DATA_W 32 -#define RFC_ULLRAM_BANK11177_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11177_DATA_S 0 +#define RFC_ULLRAM_BANK11177_DATA_W 32 +#define RFC_ULLRAM_BANK11177_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11177_DATA_S 0 //***************************************************************************** // @@ -20331,9 +20331,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11178_DATA_W 32 -#define RFC_ULLRAM_BANK11178_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11178_DATA_S 0 +#define RFC_ULLRAM_BANK11178_DATA_W 32 +#define RFC_ULLRAM_BANK11178_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11178_DATA_S 0 //***************************************************************************** // @@ -20343,9 +20343,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11179_DATA_W 32 -#define RFC_ULLRAM_BANK11179_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11179_DATA_S 0 +#define RFC_ULLRAM_BANK11179_DATA_W 32 +#define RFC_ULLRAM_BANK11179_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11179_DATA_S 0 //***************************************************************************** // @@ -20355,9 +20355,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11180_DATA_W 32 -#define RFC_ULLRAM_BANK11180_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11180_DATA_S 0 +#define RFC_ULLRAM_BANK11180_DATA_W 32 +#define RFC_ULLRAM_BANK11180_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11180_DATA_S 0 //***************************************************************************** // @@ -20367,9 +20367,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11181_DATA_W 32 -#define RFC_ULLRAM_BANK11181_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11181_DATA_S 0 +#define RFC_ULLRAM_BANK11181_DATA_W 32 +#define RFC_ULLRAM_BANK11181_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11181_DATA_S 0 //***************************************************************************** // @@ -20379,9 +20379,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11182_DATA_W 32 -#define RFC_ULLRAM_BANK11182_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11182_DATA_S 0 +#define RFC_ULLRAM_BANK11182_DATA_W 32 +#define RFC_ULLRAM_BANK11182_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11182_DATA_S 0 //***************************************************************************** // @@ -20391,9 +20391,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11183_DATA_W 32 -#define RFC_ULLRAM_BANK11183_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11183_DATA_S 0 +#define RFC_ULLRAM_BANK11183_DATA_W 32 +#define RFC_ULLRAM_BANK11183_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11183_DATA_S 0 //***************************************************************************** // @@ -20403,9 +20403,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11184_DATA_W 32 -#define RFC_ULLRAM_BANK11184_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11184_DATA_S 0 +#define RFC_ULLRAM_BANK11184_DATA_W 32 +#define RFC_ULLRAM_BANK11184_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11184_DATA_S 0 //***************************************************************************** // @@ -20415,9 +20415,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11185_DATA_W 32 -#define RFC_ULLRAM_BANK11185_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11185_DATA_S 0 +#define RFC_ULLRAM_BANK11185_DATA_W 32 +#define RFC_ULLRAM_BANK11185_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11185_DATA_S 0 //***************************************************************************** // @@ -20427,9 +20427,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11186_DATA_W 32 -#define RFC_ULLRAM_BANK11186_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11186_DATA_S 0 +#define RFC_ULLRAM_BANK11186_DATA_W 32 +#define RFC_ULLRAM_BANK11186_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11186_DATA_S 0 //***************************************************************************** // @@ -20439,9 +20439,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11187_DATA_W 32 -#define RFC_ULLRAM_BANK11187_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11187_DATA_S 0 +#define RFC_ULLRAM_BANK11187_DATA_W 32 +#define RFC_ULLRAM_BANK11187_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11187_DATA_S 0 //***************************************************************************** // @@ -20451,9 +20451,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11188_DATA_W 32 -#define RFC_ULLRAM_BANK11188_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11188_DATA_S 0 +#define RFC_ULLRAM_BANK11188_DATA_W 32 +#define RFC_ULLRAM_BANK11188_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11188_DATA_S 0 //***************************************************************************** // @@ -20463,9 +20463,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11189_DATA_W 32 -#define RFC_ULLRAM_BANK11189_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11189_DATA_S 0 +#define RFC_ULLRAM_BANK11189_DATA_W 32 +#define RFC_ULLRAM_BANK11189_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11189_DATA_S 0 //***************************************************************************** // @@ -20475,9 +20475,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11190_DATA_W 32 -#define RFC_ULLRAM_BANK11190_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11190_DATA_S 0 +#define RFC_ULLRAM_BANK11190_DATA_W 32 +#define RFC_ULLRAM_BANK11190_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11190_DATA_S 0 //***************************************************************************** // @@ -20487,9 +20487,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11191_DATA_W 32 -#define RFC_ULLRAM_BANK11191_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11191_DATA_S 0 +#define RFC_ULLRAM_BANK11191_DATA_W 32 +#define RFC_ULLRAM_BANK11191_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11191_DATA_S 0 //***************************************************************************** // @@ -20499,9 +20499,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11192_DATA_W 32 -#define RFC_ULLRAM_BANK11192_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11192_DATA_S 0 +#define RFC_ULLRAM_BANK11192_DATA_W 32 +#define RFC_ULLRAM_BANK11192_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11192_DATA_S 0 //***************************************************************************** // @@ -20511,9 +20511,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11193_DATA_W 32 -#define RFC_ULLRAM_BANK11193_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11193_DATA_S 0 +#define RFC_ULLRAM_BANK11193_DATA_W 32 +#define RFC_ULLRAM_BANK11193_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11193_DATA_S 0 //***************************************************************************** // @@ -20523,9 +20523,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11194_DATA_W 32 -#define RFC_ULLRAM_BANK11194_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11194_DATA_S 0 +#define RFC_ULLRAM_BANK11194_DATA_W 32 +#define RFC_ULLRAM_BANK11194_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11194_DATA_S 0 //***************************************************************************** // @@ -20535,9 +20535,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11195_DATA_W 32 -#define RFC_ULLRAM_BANK11195_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11195_DATA_S 0 +#define RFC_ULLRAM_BANK11195_DATA_W 32 +#define RFC_ULLRAM_BANK11195_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11195_DATA_S 0 //***************************************************************************** // @@ -20547,9 +20547,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11196_DATA_W 32 -#define RFC_ULLRAM_BANK11196_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11196_DATA_S 0 +#define RFC_ULLRAM_BANK11196_DATA_W 32 +#define RFC_ULLRAM_BANK11196_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11196_DATA_S 0 //***************************************************************************** // @@ -20559,9 +20559,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11197_DATA_W 32 -#define RFC_ULLRAM_BANK11197_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11197_DATA_S 0 +#define RFC_ULLRAM_BANK11197_DATA_W 32 +#define RFC_ULLRAM_BANK11197_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11197_DATA_S 0 //***************************************************************************** // @@ -20571,9 +20571,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11198_DATA_W 32 -#define RFC_ULLRAM_BANK11198_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11198_DATA_S 0 +#define RFC_ULLRAM_BANK11198_DATA_W 32 +#define RFC_ULLRAM_BANK11198_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11198_DATA_S 0 //***************************************************************************** // @@ -20583,9 +20583,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11199_DATA_W 32 -#define RFC_ULLRAM_BANK11199_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11199_DATA_S 0 +#define RFC_ULLRAM_BANK11199_DATA_W 32 +#define RFC_ULLRAM_BANK11199_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11199_DATA_S 0 //***************************************************************************** // @@ -20595,9 +20595,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11200_DATA_W 32 -#define RFC_ULLRAM_BANK11200_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11200_DATA_S 0 +#define RFC_ULLRAM_BANK11200_DATA_W 32 +#define RFC_ULLRAM_BANK11200_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11200_DATA_S 0 //***************************************************************************** // @@ -20607,9 +20607,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11201_DATA_W 32 -#define RFC_ULLRAM_BANK11201_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11201_DATA_S 0 +#define RFC_ULLRAM_BANK11201_DATA_W 32 +#define RFC_ULLRAM_BANK11201_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11201_DATA_S 0 //***************************************************************************** // @@ -20619,9 +20619,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11202_DATA_W 32 -#define RFC_ULLRAM_BANK11202_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11202_DATA_S 0 +#define RFC_ULLRAM_BANK11202_DATA_W 32 +#define RFC_ULLRAM_BANK11202_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11202_DATA_S 0 //***************************************************************************** // @@ -20631,9 +20631,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11203_DATA_W 32 -#define RFC_ULLRAM_BANK11203_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11203_DATA_S 0 +#define RFC_ULLRAM_BANK11203_DATA_W 32 +#define RFC_ULLRAM_BANK11203_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11203_DATA_S 0 //***************************************************************************** // @@ -20643,9 +20643,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11204_DATA_W 32 -#define RFC_ULLRAM_BANK11204_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11204_DATA_S 0 +#define RFC_ULLRAM_BANK11204_DATA_W 32 +#define RFC_ULLRAM_BANK11204_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11204_DATA_S 0 //***************************************************************************** // @@ -20655,9 +20655,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11205_DATA_W 32 -#define RFC_ULLRAM_BANK11205_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11205_DATA_S 0 +#define RFC_ULLRAM_BANK11205_DATA_W 32 +#define RFC_ULLRAM_BANK11205_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11205_DATA_S 0 //***************************************************************************** // @@ -20667,9 +20667,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11206_DATA_W 32 -#define RFC_ULLRAM_BANK11206_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11206_DATA_S 0 +#define RFC_ULLRAM_BANK11206_DATA_W 32 +#define RFC_ULLRAM_BANK11206_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11206_DATA_S 0 //***************************************************************************** // @@ -20679,9 +20679,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11207_DATA_W 32 -#define RFC_ULLRAM_BANK11207_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11207_DATA_S 0 +#define RFC_ULLRAM_BANK11207_DATA_W 32 +#define RFC_ULLRAM_BANK11207_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11207_DATA_S 0 //***************************************************************************** // @@ -20691,9 +20691,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11208_DATA_W 32 -#define RFC_ULLRAM_BANK11208_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11208_DATA_S 0 +#define RFC_ULLRAM_BANK11208_DATA_W 32 +#define RFC_ULLRAM_BANK11208_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11208_DATA_S 0 //***************************************************************************** // @@ -20703,9 +20703,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11209_DATA_W 32 -#define RFC_ULLRAM_BANK11209_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11209_DATA_S 0 +#define RFC_ULLRAM_BANK11209_DATA_W 32 +#define RFC_ULLRAM_BANK11209_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11209_DATA_S 0 //***************************************************************************** // @@ -20715,9 +20715,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11210_DATA_W 32 -#define RFC_ULLRAM_BANK11210_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11210_DATA_S 0 +#define RFC_ULLRAM_BANK11210_DATA_W 32 +#define RFC_ULLRAM_BANK11210_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11210_DATA_S 0 //***************************************************************************** // @@ -20727,9 +20727,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11211_DATA_W 32 -#define RFC_ULLRAM_BANK11211_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11211_DATA_S 0 +#define RFC_ULLRAM_BANK11211_DATA_W 32 +#define RFC_ULLRAM_BANK11211_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11211_DATA_S 0 //***************************************************************************** // @@ -20739,9 +20739,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11212_DATA_W 32 -#define RFC_ULLRAM_BANK11212_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11212_DATA_S 0 +#define RFC_ULLRAM_BANK11212_DATA_W 32 +#define RFC_ULLRAM_BANK11212_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11212_DATA_S 0 //***************************************************************************** // @@ -20751,9 +20751,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11213_DATA_W 32 -#define RFC_ULLRAM_BANK11213_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11213_DATA_S 0 +#define RFC_ULLRAM_BANK11213_DATA_W 32 +#define RFC_ULLRAM_BANK11213_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11213_DATA_S 0 //***************************************************************************** // @@ -20763,9 +20763,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11214_DATA_W 32 -#define RFC_ULLRAM_BANK11214_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11214_DATA_S 0 +#define RFC_ULLRAM_BANK11214_DATA_W 32 +#define RFC_ULLRAM_BANK11214_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11214_DATA_S 0 //***************************************************************************** // @@ -20775,9 +20775,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11215_DATA_W 32 -#define RFC_ULLRAM_BANK11215_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11215_DATA_S 0 +#define RFC_ULLRAM_BANK11215_DATA_W 32 +#define RFC_ULLRAM_BANK11215_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11215_DATA_S 0 //***************************************************************************** // @@ -20787,9 +20787,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11216_DATA_W 32 -#define RFC_ULLRAM_BANK11216_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11216_DATA_S 0 +#define RFC_ULLRAM_BANK11216_DATA_W 32 +#define RFC_ULLRAM_BANK11216_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11216_DATA_S 0 //***************************************************************************** // @@ -20799,9 +20799,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11217_DATA_W 32 -#define RFC_ULLRAM_BANK11217_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11217_DATA_S 0 +#define RFC_ULLRAM_BANK11217_DATA_W 32 +#define RFC_ULLRAM_BANK11217_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11217_DATA_S 0 //***************************************************************************** // @@ -20811,9 +20811,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11218_DATA_W 32 -#define RFC_ULLRAM_BANK11218_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11218_DATA_S 0 +#define RFC_ULLRAM_BANK11218_DATA_W 32 +#define RFC_ULLRAM_BANK11218_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11218_DATA_S 0 //***************************************************************************** // @@ -20823,9 +20823,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11219_DATA_W 32 -#define RFC_ULLRAM_BANK11219_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11219_DATA_S 0 +#define RFC_ULLRAM_BANK11219_DATA_W 32 +#define RFC_ULLRAM_BANK11219_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11219_DATA_S 0 //***************************************************************************** // @@ -20835,9 +20835,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11220_DATA_W 32 -#define RFC_ULLRAM_BANK11220_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11220_DATA_S 0 +#define RFC_ULLRAM_BANK11220_DATA_W 32 +#define RFC_ULLRAM_BANK11220_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11220_DATA_S 0 //***************************************************************************** // @@ -20847,9 +20847,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11221_DATA_W 32 -#define RFC_ULLRAM_BANK11221_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11221_DATA_S 0 +#define RFC_ULLRAM_BANK11221_DATA_W 32 +#define RFC_ULLRAM_BANK11221_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11221_DATA_S 0 //***************************************************************************** // @@ -20859,9 +20859,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11222_DATA_W 32 -#define RFC_ULLRAM_BANK11222_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11222_DATA_S 0 +#define RFC_ULLRAM_BANK11222_DATA_W 32 +#define RFC_ULLRAM_BANK11222_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11222_DATA_S 0 //***************************************************************************** // @@ -20871,9 +20871,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11223_DATA_W 32 -#define RFC_ULLRAM_BANK11223_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11223_DATA_S 0 +#define RFC_ULLRAM_BANK11223_DATA_W 32 +#define RFC_ULLRAM_BANK11223_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11223_DATA_S 0 //***************************************************************************** // @@ -20883,9 +20883,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11224_DATA_W 32 -#define RFC_ULLRAM_BANK11224_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11224_DATA_S 0 +#define RFC_ULLRAM_BANK11224_DATA_W 32 +#define RFC_ULLRAM_BANK11224_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11224_DATA_S 0 //***************************************************************************** // @@ -20895,9 +20895,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11225_DATA_W 32 -#define RFC_ULLRAM_BANK11225_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11225_DATA_S 0 +#define RFC_ULLRAM_BANK11225_DATA_W 32 +#define RFC_ULLRAM_BANK11225_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11225_DATA_S 0 //***************************************************************************** // @@ -20907,9 +20907,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11226_DATA_W 32 -#define RFC_ULLRAM_BANK11226_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11226_DATA_S 0 +#define RFC_ULLRAM_BANK11226_DATA_W 32 +#define RFC_ULLRAM_BANK11226_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11226_DATA_S 0 //***************************************************************************** // @@ -20919,9 +20919,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11227_DATA_W 32 -#define RFC_ULLRAM_BANK11227_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11227_DATA_S 0 +#define RFC_ULLRAM_BANK11227_DATA_W 32 +#define RFC_ULLRAM_BANK11227_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11227_DATA_S 0 //***************************************************************************** // @@ -20931,9 +20931,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11228_DATA_W 32 -#define RFC_ULLRAM_BANK11228_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11228_DATA_S 0 +#define RFC_ULLRAM_BANK11228_DATA_W 32 +#define RFC_ULLRAM_BANK11228_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11228_DATA_S 0 //***************************************************************************** // @@ -20943,9 +20943,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11229_DATA_W 32 -#define RFC_ULLRAM_BANK11229_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11229_DATA_S 0 +#define RFC_ULLRAM_BANK11229_DATA_W 32 +#define RFC_ULLRAM_BANK11229_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11229_DATA_S 0 //***************************************************************************** // @@ -20955,9 +20955,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11230_DATA_W 32 -#define RFC_ULLRAM_BANK11230_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11230_DATA_S 0 +#define RFC_ULLRAM_BANK11230_DATA_W 32 +#define RFC_ULLRAM_BANK11230_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11230_DATA_S 0 //***************************************************************************** // @@ -20967,9 +20967,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11231_DATA_W 32 -#define RFC_ULLRAM_BANK11231_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11231_DATA_S 0 +#define RFC_ULLRAM_BANK11231_DATA_W 32 +#define RFC_ULLRAM_BANK11231_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11231_DATA_S 0 //***************************************************************************** // @@ -20979,9 +20979,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11232_DATA_W 32 -#define RFC_ULLRAM_BANK11232_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11232_DATA_S 0 +#define RFC_ULLRAM_BANK11232_DATA_W 32 +#define RFC_ULLRAM_BANK11232_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11232_DATA_S 0 //***************************************************************************** // @@ -20991,9 +20991,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11233_DATA_W 32 -#define RFC_ULLRAM_BANK11233_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11233_DATA_S 0 +#define RFC_ULLRAM_BANK11233_DATA_W 32 +#define RFC_ULLRAM_BANK11233_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11233_DATA_S 0 //***************************************************************************** // @@ -21003,9 +21003,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11234_DATA_W 32 -#define RFC_ULLRAM_BANK11234_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11234_DATA_S 0 +#define RFC_ULLRAM_BANK11234_DATA_W 32 +#define RFC_ULLRAM_BANK11234_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11234_DATA_S 0 //***************************************************************************** // @@ -21015,9 +21015,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11235_DATA_W 32 -#define RFC_ULLRAM_BANK11235_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11235_DATA_S 0 +#define RFC_ULLRAM_BANK11235_DATA_W 32 +#define RFC_ULLRAM_BANK11235_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11235_DATA_S 0 //***************************************************************************** // @@ -21027,9 +21027,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11236_DATA_W 32 -#define RFC_ULLRAM_BANK11236_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11236_DATA_S 0 +#define RFC_ULLRAM_BANK11236_DATA_W 32 +#define RFC_ULLRAM_BANK11236_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11236_DATA_S 0 //***************************************************************************** // @@ -21039,9 +21039,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11237_DATA_W 32 -#define RFC_ULLRAM_BANK11237_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11237_DATA_S 0 +#define RFC_ULLRAM_BANK11237_DATA_W 32 +#define RFC_ULLRAM_BANK11237_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11237_DATA_S 0 //***************************************************************************** // @@ -21051,9 +21051,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11238_DATA_W 32 -#define RFC_ULLRAM_BANK11238_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11238_DATA_S 0 +#define RFC_ULLRAM_BANK11238_DATA_W 32 +#define RFC_ULLRAM_BANK11238_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11238_DATA_S 0 //***************************************************************************** // @@ -21063,9 +21063,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11239_DATA_W 32 -#define RFC_ULLRAM_BANK11239_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11239_DATA_S 0 +#define RFC_ULLRAM_BANK11239_DATA_W 32 +#define RFC_ULLRAM_BANK11239_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11239_DATA_S 0 //***************************************************************************** // @@ -21075,9 +21075,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11240_DATA_W 32 -#define RFC_ULLRAM_BANK11240_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11240_DATA_S 0 +#define RFC_ULLRAM_BANK11240_DATA_W 32 +#define RFC_ULLRAM_BANK11240_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11240_DATA_S 0 //***************************************************************************** // @@ -21087,9 +21087,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11241_DATA_W 32 -#define RFC_ULLRAM_BANK11241_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11241_DATA_S 0 +#define RFC_ULLRAM_BANK11241_DATA_W 32 +#define RFC_ULLRAM_BANK11241_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11241_DATA_S 0 //***************************************************************************** // @@ -21099,9 +21099,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11242_DATA_W 32 -#define RFC_ULLRAM_BANK11242_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11242_DATA_S 0 +#define RFC_ULLRAM_BANK11242_DATA_W 32 +#define RFC_ULLRAM_BANK11242_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11242_DATA_S 0 //***************************************************************************** // @@ -21111,9 +21111,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11243_DATA_W 32 -#define RFC_ULLRAM_BANK11243_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11243_DATA_S 0 +#define RFC_ULLRAM_BANK11243_DATA_W 32 +#define RFC_ULLRAM_BANK11243_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11243_DATA_S 0 //***************************************************************************** // @@ -21123,9 +21123,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11244_DATA_W 32 -#define RFC_ULLRAM_BANK11244_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11244_DATA_S 0 +#define RFC_ULLRAM_BANK11244_DATA_W 32 +#define RFC_ULLRAM_BANK11244_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11244_DATA_S 0 //***************************************************************************** // @@ -21135,9 +21135,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11245_DATA_W 32 -#define RFC_ULLRAM_BANK11245_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11245_DATA_S 0 +#define RFC_ULLRAM_BANK11245_DATA_W 32 +#define RFC_ULLRAM_BANK11245_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11245_DATA_S 0 //***************************************************************************** // @@ -21147,9 +21147,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11246_DATA_W 32 -#define RFC_ULLRAM_BANK11246_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11246_DATA_S 0 +#define RFC_ULLRAM_BANK11246_DATA_W 32 +#define RFC_ULLRAM_BANK11246_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11246_DATA_S 0 //***************************************************************************** // @@ -21159,9 +21159,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11247_DATA_W 32 -#define RFC_ULLRAM_BANK11247_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11247_DATA_S 0 +#define RFC_ULLRAM_BANK11247_DATA_W 32 +#define RFC_ULLRAM_BANK11247_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11247_DATA_S 0 //***************************************************************************** // @@ -21171,9 +21171,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11248_DATA_W 32 -#define RFC_ULLRAM_BANK11248_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11248_DATA_S 0 +#define RFC_ULLRAM_BANK11248_DATA_W 32 +#define RFC_ULLRAM_BANK11248_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11248_DATA_S 0 //***************************************************************************** // @@ -21183,9 +21183,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11249_DATA_W 32 -#define RFC_ULLRAM_BANK11249_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11249_DATA_S 0 +#define RFC_ULLRAM_BANK11249_DATA_W 32 +#define RFC_ULLRAM_BANK11249_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11249_DATA_S 0 //***************************************************************************** // @@ -21195,9 +21195,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11250_DATA_W 32 -#define RFC_ULLRAM_BANK11250_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11250_DATA_S 0 +#define RFC_ULLRAM_BANK11250_DATA_W 32 +#define RFC_ULLRAM_BANK11250_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11250_DATA_S 0 //***************************************************************************** // @@ -21207,9 +21207,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11251_DATA_W 32 -#define RFC_ULLRAM_BANK11251_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11251_DATA_S 0 +#define RFC_ULLRAM_BANK11251_DATA_W 32 +#define RFC_ULLRAM_BANK11251_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11251_DATA_S 0 //***************************************************************************** // @@ -21219,9 +21219,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11252_DATA_W 32 -#define RFC_ULLRAM_BANK11252_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11252_DATA_S 0 +#define RFC_ULLRAM_BANK11252_DATA_W 32 +#define RFC_ULLRAM_BANK11252_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11252_DATA_S 0 //***************************************************************************** // @@ -21231,9 +21231,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11253_DATA_W 32 -#define RFC_ULLRAM_BANK11253_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11253_DATA_S 0 +#define RFC_ULLRAM_BANK11253_DATA_W 32 +#define RFC_ULLRAM_BANK11253_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11253_DATA_S 0 //***************************************************************************** // @@ -21243,9 +21243,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11254_DATA_W 32 -#define RFC_ULLRAM_BANK11254_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11254_DATA_S 0 +#define RFC_ULLRAM_BANK11254_DATA_W 32 +#define RFC_ULLRAM_BANK11254_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11254_DATA_S 0 //***************************************************************************** // @@ -21255,9 +21255,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11255_DATA_W 32 -#define RFC_ULLRAM_BANK11255_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11255_DATA_S 0 +#define RFC_ULLRAM_BANK11255_DATA_W 32 +#define RFC_ULLRAM_BANK11255_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11255_DATA_S 0 //***************************************************************************** // @@ -21267,9 +21267,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11256_DATA_W 32 -#define RFC_ULLRAM_BANK11256_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11256_DATA_S 0 +#define RFC_ULLRAM_BANK11256_DATA_W 32 +#define RFC_ULLRAM_BANK11256_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11256_DATA_S 0 //***************************************************************************** // @@ -21279,9 +21279,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11257_DATA_W 32 -#define RFC_ULLRAM_BANK11257_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11257_DATA_S 0 +#define RFC_ULLRAM_BANK11257_DATA_W 32 +#define RFC_ULLRAM_BANK11257_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11257_DATA_S 0 //***************************************************************************** // @@ -21291,9 +21291,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11258_DATA_W 32 -#define RFC_ULLRAM_BANK11258_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11258_DATA_S 0 +#define RFC_ULLRAM_BANK11258_DATA_W 32 +#define RFC_ULLRAM_BANK11258_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11258_DATA_S 0 //***************************************************************************** // @@ -21303,9 +21303,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11259_DATA_W 32 -#define RFC_ULLRAM_BANK11259_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11259_DATA_S 0 +#define RFC_ULLRAM_BANK11259_DATA_W 32 +#define RFC_ULLRAM_BANK11259_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11259_DATA_S 0 //***************************************************************************** // @@ -21315,9 +21315,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11260_DATA_W 32 -#define RFC_ULLRAM_BANK11260_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11260_DATA_S 0 +#define RFC_ULLRAM_BANK11260_DATA_W 32 +#define RFC_ULLRAM_BANK11260_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11260_DATA_S 0 //***************************************************************************** // @@ -21327,9 +21327,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11261_DATA_W 32 -#define RFC_ULLRAM_BANK11261_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11261_DATA_S 0 +#define RFC_ULLRAM_BANK11261_DATA_W 32 +#define RFC_ULLRAM_BANK11261_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11261_DATA_S 0 //***************************************************************************** // @@ -21339,9 +21339,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11262_DATA_W 32 -#define RFC_ULLRAM_BANK11262_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11262_DATA_S 0 +#define RFC_ULLRAM_BANK11262_DATA_W 32 +#define RFC_ULLRAM_BANK11262_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11262_DATA_S 0 //***************************************************************************** // @@ -21351,9 +21351,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11263_DATA_W 32 -#define RFC_ULLRAM_BANK11263_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11263_DATA_S 0 +#define RFC_ULLRAM_BANK11263_DATA_W 32 +#define RFC_ULLRAM_BANK11263_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11263_DATA_S 0 //***************************************************************************** // @@ -21363,9 +21363,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11264_DATA_W 32 -#define RFC_ULLRAM_BANK11264_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11264_DATA_S 0 +#define RFC_ULLRAM_BANK11264_DATA_W 32 +#define RFC_ULLRAM_BANK11264_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11264_DATA_S 0 //***************************************************************************** // @@ -21375,9 +21375,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11265_DATA_W 32 -#define RFC_ULLRAM_BANK11265_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11265_DATA_S 0 +#define RFC_ULLRAM_BANK11265_DATA_W 32 +#define RFC_ULLRAM_BANK11265_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11265_DATA_S 0 //***************************************************************************** // @@ -21387,9 +21387,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11266_DATA_W 32 -#define RFC_ULLRAM_BANK11266_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11266_DATA_S 0 +#define RFC_ULLRAM_BANK11266_DATA_W 32 +#define RFC_ULLRAM_BANK11266_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11266_DATA_S 0 //***************************************************************************** // @@ -21399,9 +21399,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11267_DATA_W 32 -#define RFC_ULLRAM_BANK11267_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11267_DATA_S 0 +#define RFC_ULLRAM_BANK11267_DATA_W 32 +#define RFC_ULLRAM_BANK11267_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11267_DATA_S 0 //***************************************************************************** // @@ -21411,9 +21411,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11268_DATA_W 32 -#define RFC_ULLRAM_BANK11268_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11268_DATA_S 0 +#define RFC_ULLRAM_BANK11268_DATA_W 32 +#define RFC_ULLRAM_BANK11268_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11268_DATA_S 0 //***************************************************************************** // @@ -21423,9 +21423,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11269_DATA_W 32 -#define RFC_ULLRAM_BANK11269_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11269_DATA_S 0 +#define RFC_ULLRAM_BANK11269_DATA_W 32 +#define RFC_ULLRAM_BANK11269_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11269_DATA_S 0 //***************************************************************************** // @@ -21435,9 +21435,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11270_DATA_W 32 -#define RFC_ULLRAM_BANK11270_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11270_DATA_S 0 +#define RFC_ULLRAM_BANK11270_DATA_W 32 +#define RFC_ULLRAM_BANK11270_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11270_DATA_S 0 //***************************************************************************** // @@ -21447,9 +21447,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11271_DATA_W 32 -#define RFC_ULLRAM_BANK11271_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11271_DATA_S 0 +#define RFC_ULLRAM_BANK11271_DATA_W 32 +#define RFC_ULLRAM_BANK11271_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11271_DATA_S 0 //***************************************************************************** // @@ -21459,9 +21459,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11272_DATA_W 32 -#define RFC_ULLRAM_BANK11272_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11272_DATA_S 0 +#define RFC_ULLRAM_BANK11272_DATA_W 32 +#define RFC_ULLRAM_BANK11272_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11272_DATA_S 0 //***************************************************************************** // @@ -21471,9 +21471,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11273_DATA_W 32 -#define RFC_ULLRAM_BANK11273_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11273_DATA_S 0 +#define RFC_ULLRAM_BANK11273_DATA_W 32 +#define RFC_ULLRAM_BANK11273_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11273_DATA_S 0 //***************************************************************************** // @@ -21483,9 +21483,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11274_DATA_W 32 -#define RFC_ULLRAM_BANK11274_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11274_DATA_S 0 +#define RFC_ULLRAM_BANK11274_DATA_W 32 +#define RFC_ULLRAM_BANK11274_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11274_DATA_S 0 //***************************************************************************** // @@ -21495,9 +21495,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11275_DATA_W 32 -#define RFC_ULLRAM_BANK11275_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11275_DATA_S 0 +#define RFC_ULLRAM_BANK11275_DATA_W 32 +#define RFC_ULLRAM_BANK11275_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11275_DATA_S 0 //***************************************************************************** // @@ -21507,9 +21507,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11276_DATA_W 32 -#define RFC_ULLRAM_BANK11276_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11276_DATA_S 0 +#define RFC_ULLRAM_BANK11276_DATA_W 32 +#define RFC_ULLRAM_BANK11276_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11276_DATA_S 0 //***************************************************************************** // @@ -21519,9 +21519,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11277_DATA_W 32 -#define RFC_ULLRAM_BANK11277_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11277_DATA_S 0 +#define RFC_ULLRAM_BANK11277_DATA_W 32 +#define RFC_ULLRAM_BANK11277_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11277_DATA_S 0 //***************************************************************************** // @@ -21531,9 +21531,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11278_DATA_W 32 -#define RFC_ULLRAM_BANK11278_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11278_DATA_S 0 +#define RFC_ULLRAM_BANK11278_DATA_W 32 +#define RFC_ULLRAM_BANK11278_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11278_DATA_S 0 //***************************************************************************** // @@ -21543,9 +21543,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11279_DATA_W 32 -#define RFC_ULLRAM_BANK11279_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11279_DATA_S 0 +#define RFC_ULLRAM_BANK11279_DATA_W 32 +#define RFC_ULLRAM_BANK11279_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11279_DATA_S 0 //***************************************************************************** // @@ -21555,9 +21555,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11280_DATA_W 32 -#define RFC_ULLRAM_BANK11280_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11280_DATA_S 0 +#define RFC_ULLRAM_BANK11280_DATA_W 32 +#define RFC_ULLRAM_BANK11280_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11280_DATA_S 0 //***************************************************************************** // @@ -21567,9 +21567,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11281_DATA_W 32 -#define RFC_ULLRAM_BANK11281_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11281_DATA_S 0 +#define RFC_ULLRAM_BANK11281_DATA_W 32 +#define RFC_ULLRAM_BANK11281_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11281_DATA_S 0 //***************************************************************************** // @@ -21579,9 +21579,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11282_DATA_W 32 -#define RFC_ULLRAM_BANK11282_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11282_DATA_S 0 +#define RFC_ULLRAM_BANK11282_DATA_W 32 +#define RFC_ULLRAM_BANK11282_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11282_DATA_S 0 //***************************************************************************** // @@ -21591,9 +21591,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11283_DATA_W 32 -#define RFC_ULLRAM_BANK11283_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11283_DATA_S 0 +#define RFC_ULLRAM_BANK11283_DATA_W 32 +#define RFC_ULLRAM_BANK11283_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11283_DATA_S 0 //***************************************************************************** // @@ -21603,9 +21603,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11284_DATA_W 32 -#define RFC_ULLRAM_BANK11284_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11284_DATA_S 0 +#define RFC_ULLRAM_BANK11284_DATA_W 32 +#define RFC_ULLRAM_BANK11284_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11284_DATA_S 0 //***************************************************************************** // @@ -21615,9 +21615,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11285_DATA_W 32 -#define RFC_ULLRAM_BANK11285_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11285_DATA_S 0 +#define RFC_ULLRAM_BANK11285_DATA_W 32 +#define RFC_ULLRAM_BANK11285_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11285_DATA_S 0 //***************************************************************************** // @@ -21627,9 +21627,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11286_DATA_W 32 -#define RFC_ULLRAM_BANK11286_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11286_DATA_S 0 +#define RFC_ULLRAM_BANK11286_DATA_W 32 +#define RFC_ULLRAM_BANK11286_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11286_DATA_S 0 //***************************************************************************** // @@ -21639,9 +21639,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11287_DATA_W 32 -#define RFC_ULLRAM_BANK11287_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11287_DATA_S 0 +#define RFC_ULLRAM_BANK11287_DATA_W 32 +#define RFC_ULLRAM_BANK11287_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11287_DATA_S 0 //***************************************************************************** // @@ -21651,9 +21651,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11288_DATA_W 32 -#define RFC_ULLRAM_BANK11288_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11288_DATA_S 0 +#define RFC_ULLRAM_BANK11288_DATA_W 32 +#define RFC_ULLRAM_BANK11288_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11288_DATA_S 0 //***************************************************************************** // @@ -21663,9 +21663,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11289_DATA_W 32 -#define RFC_ULLRAM_BANK11289_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11289_DATA_S 0 +#define RFC_ULLRAM_BANK11289_DATA_W 32 +#define RFC_ULLRAM_BANK11289_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11289_DATA_S 0 //***************************************************************************** // @@ -21675,9 +21675,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11290_DATA_W 32 -#define RFC_ULLRAM_BANK11290_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11290_DATA_S 0 +#define RFC_ULLRAM_BANK11290_DATA_W 32 +#define RFC_ULLRAM_BANK11290_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11290_DATA_S 0 //***************************************************************************** // @@ -21687,9 +21687,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11291_DATA_W 32 -#define RFC_ULLRAM_BANK11291_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11291_DATA_S 0 +#define RFC_ULLRAM_BANK11291_DATA_W 32 +#define RFC_ULLRAM_BANK11291_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11291_DATA_S 0 //***************************************************************************** // @@ -21699,9 +21699,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11292_DATA_W 32 -#define RFC_ULLRAM_BANK11292_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11292_DATA_S 0 +#define RFC_ULLRAM_BANK11292_DATA_W 32 +#define RFC_ULLRAM_BANK11292_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11292_DATA_S 0 //***************************************************************************** // @@ -21711,9 +21711,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11293_DATA_W 32 -#define RFC_ULLRAM_BANK11293_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11293_DATA_S 0 +#define RFC_ULLRAM_BANK11293_DATA_W 32 +#define RFC_ULLRAM_BANK11293_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11293_DATA_S 0 //***************************************************************************** // @@ -21723,9 +21723,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11294_DATA_W 32 -#define RFC_ULLRAM_BANK11294_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11294_DATA_S 0 +#define RFC_ULLRAM_BANK11294_DATA_W 32 +#define RFC_ULLRAM_BANK11294_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11294_DATA_S 0 //***************************************************************************** // @@ -21735,9 +21735,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11295_DATA_W 32 -#define RFC_ULLRAM_BANK11295_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11295_DATA_S 0 +#define RFC_ULLRAM_BANK11295_DATA_W 32 +#define RFC_ULLRAM_BANK11295_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11295_DATA_S 0 //***************************************************************************** // @@ -21747,9 +21747,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11296_DATA_W 32 -#define RFC_ULLRAM_BANK11296_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11296_DATA_S 0 +#define RFC_ULLRAM_BANK11296_DATA_W 32 +#define RFC_ULLRAM_BANK11296_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11296_DATA_S 0 //***************************************************************************** // @@ -21759,9 +21759,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11297_DATA_W 32 -#define RFC_ULLRAM_BANK11297_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11297_DATA_S 0 +#define RFC_ULLRAM_BANK11297_DATA_W 32 +#define RFC_ULLRAM_BANK11297_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11297_DATA_S 0 //***************************************************************************** // @@ -21771,9 +21771,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11298_DATA_W 32 -#define RFC_ULLRAM_BANK11298_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11298_DATA_S 0 +#define RFC_ULLRAM_BANK11298_DATA_W 32 +#define RFC_ULLRAM_BANK11298_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11298_DATA_S 0 //***************************************************************************** // @@ -21783,9 +21783,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11299_DATA_W 32 -#define RFC_ULLRAM_BANK11299_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11299_DATA_S 0 +#define RFC_ULLRAM_BANK11299_DATA_W 32 +#define RFC_ULLRAM_BANK11299_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11299_DATA_S 0 //***************************************************************************** // @@ -21795,9 +21795,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11300_DATA_W 32 -#define RFC_ULLRAM_BANK11300_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11300_DATA_S 0 +#define RFC_ULLRAM_BANK11300_DATA_W 32 +#define RFC_ULLRAM_BANK11300_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11300_DATA_S 0 //***************************************************************************** // @@ -21807,9 +21807,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11301_DATA_W 32 -#define RFC_ULLRAM_BANK11301_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11301_DATA_S 0 +#define RFC_ULLRAM_BANK11301_DATA_W 32 +#define RFC_ULLRAM_BANK11301_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11301_DATA_S 0 //***************************************************************************** // @@ -21819,9 +21819,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11302_DATA_W 32 -#define RFC_ULLRAM_BANK11302_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11302_DATA_S 0 +#define RFC_ULLRAM_BANK11302_DATA_W 32 +#define RFC_ULLRAM_BANK11302_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11302_DATA_S 0 //***************************************************************************** // @@ -21831,9 +21831,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11303_DATA_W 32 -#define RFC_ULLRAM_BANK11303_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11303_DATA_S 0 +#define RFC_ULLRAM_BANK11303_DATA_W 32 +#define RFC_ULLRAM_BANK11303_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11303_DATA_S 0 //***************************************************************************** // @@ -21843,9 +21843,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11304_DATA_W 32 -#define RFC_ULLRAM_BANK11304_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11304_DATA_S 0 +#define RFC_ULLRAM_BANK11304_DATA_W 32 +#define RFC_ULLRAM_BANK11304_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11304_DATA_S 0 //***************************************************************************** // @@ -21855,9 +21855,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11305_DATA_W 32 -#define RFC_ULLRAM_BANK11305_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11305_DATA_S 0 +#define RFC_ULLRAM_BANK11305_DATA_W 32 +#define RFC_ULLRAM_BANK11305_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11305_DATA_S 0 //***************************************************************************** // @@ -21867,9 +21867,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11306_DATA_W 32 -#define RFC_ULLRAM_BANK11306_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11306_DATA_S 0 +#define RFC_ULLRAM_BANK11306_DATA_W 32 +#define RFC_ULLRAM_BANK11306_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11306_DATA_S 0 //***************************************************************************** // @@ -21879,9 +21879,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11307_DATA_W 32 -#define RFC_ULLRAM_BANK11307_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11307_DATA_S 0 +#define RFC_ULLRAM_BANK11307_DATA_W 32 +#define RFC_ULLRAM_BANK11307_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11307_DATA_S 0 //***************************************************************************** // @@ -21891,9 +21891,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11308_DATA_W 32 -#define RFC_ULLRAM_BANK11308_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11308_DATA_S 0 +#define RFC_ULLRAM_BANK11308_DATA_W 32 +#define RFC_ULLRAM_BANK11308_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11308_DATA_S 0 //***************************************************************************** // @@ -21903,9 +21903,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11309_DATA_W 32 -#define RFC_ULLRAM_BANK11309_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11309_DATA_S 0 +#define RFC_ULLRAM_BANK11309_DATA_W 32 +#define RFC_ULLRAM_BANK11309_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11309_DATA_S 0 //***************************************************************************** // @@ -21915,9 +21915,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11310_DATA_W 32 -#define RFC_ULLRAM_BANK11310_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11310_DATA_S 0 +#define RFC_ULLRAM_BANK11310_DATA_W 32 +#define RFC_ULLRAM_BANK11310_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11310_DATA_S 0 //***************************************************************************** // @@ -21927,9 +21927,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11311_DATA_W 32 -#define RFC_ULLRAM_BANK11311_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11311_DATA_S 0 +#define RFC_ULLRAM_BANK11311_DATA_W 32 +#define RFC_ULLRAM_BANK11311_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11311_DATA_S 0 //***************************************************************************** // @@ -21939,9 +21939,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11312_DATA_W 32 -#define RFC_ULLRAM_BANK11312_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11312_DATA_S 0 +#define RFC_ULLRAM_BANK11312_DATA_W 32 +#define RFC_ULLRAM_BANK11312_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11312_DATA_S 0 //***************************************************************************** // @@ -21951,9 +21951,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11313_DATA_W 32 -#define RFC_ULLRAM_BANK11313_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11313_DATA_S 0 +#define RFC_ULLRAM_BANK11313_DATA_W 32 +#define RFC_ULLRAM_BANK11313_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11313_DATA_S 0 //***************************************************************************** // @@ -21963,9 +21963,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11314_DATA_W 32 -#define RFC_ULLRAM_BANK11314_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11314_DATA_S 0 +#define RFC_ULLRAM_BANK11314_DATA_W 32 +#define RFC_ULLRAM_BANK11314_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11314_DATA_S 0 //***************************************************************************** // @@ -21975,9 +21975,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11315_DATA_W 32 -#define RFC_ULLRAM_BANK11315_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11315_DATA_S 0 +#define RFC_ULLRAM_BANK11315_DATA_W 32 +#define RFC_ULLRAM_BANK11315_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11315_DATA_S 0 //***************************************************************************** // @@ -21987,9 +21987,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11316_DATA_W 32 -#define RFC_ULLRAM_BANK11316_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11316_DATA_S 0 +#define RFC_ULLRAM_BANK11316_DATA_W 32 +#define RFC_ULLRAM_BANK11316_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11316_DATA_S 0 //***************************************************************************** // @@ -21999,9 +21999,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11317_DATA_W 32 -#define RFC_ULLRAM_BANK11317_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11317_DATA_S 0 +#define RFC_ULLRAM_BANK11317_DATA_W 32 +#define RFC_ULLRAM_BANK11317_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11317_DATA_S 0 //***************************************************************************** // @@ -22011,9 +22011,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11318_DATA_W 32 -#define RFC_ULLRAM_BANK11318_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11318_DATA_S 0 +#define RFC_ULLRAM_BANK11318_DATA_W 32 +#define RFC_ULLRAM_BANK11318_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11318_DATA_S 0 //***************************************************************************** // @@ -22023,9 +22023,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11319_DATA_W 32 -#define RFC_ULLRAM_BANK11319_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11319_DATA_S 0 +#define RFC_ULLRAM_BANK11319_DATA_W 32 +#define RFC_ULLRAM_BANK11319_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11319_DATA_S 0 //***************************************************************************** // @@ -22035,9 +22035,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11320_DATA_W 32 -#define RFC_ULLRAM_BANK11320_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11320_DATA_S 0 +#define RFC_ULLRAM_BANK11320_DATA_W 32 +#define RFC_ULLRAM_BANK11320_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11320_DATA_S 0 //***************************************************************************** // @@ -22047,9 +22047,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11321_DATA_W 32 -#define RFC_ULLRAM_BANK11321_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11321_DATA_S 0 +#define RFC_ULLRAM_BANK11321_DATA_W 32 +#define RFC_ULLRAM_BANK11321_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11321_DATA_S 0 //***************************************************************************** // @@ -22059,9 +22059,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11322_DATA_W 32 -#define RFC_ULLRAM_BANK11322_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11322_DATA_S 0 +#define RFC_ULLRAM_BANK11322_DATA_W 32 +#define RFC_ULLRAM_BANK11322_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11322_DATA_S 0 //***************************************************************************** // @@ -22071,9 +22071,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11323_DATA_W 32 -#define RFC_ULLRAM_BANK11323_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11323_DATA_S 0 +#define RFC_ULLRAM_BANK11323_DATA_W 32 +#define RFC_ULLRAM_BANK11323_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11323_DATA_S 0 //***************************************************************************** // @@ -22083,9 +22083,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11324_DATA_W 32 -#define RFC_ULLRAM_BANK11324_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11324_DATA_S 0 +#define RFC_ULLRAM_BANK11324_DATA_W 32 +#define RFC_ULLRAM_BANK11324_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11324_DATA_S 0 //***************************************************************************** // @@ -22095,9 +22095,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11325_DATA_W 32 -#define RFC_ULLRAM_BANK11325_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11325_DATA_S 0 +#define RFC_ULLRAM_BANK11325_DATA_W 32 +#define RFC_ULLRAM_BANK11325_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11325_DATA_S 0 //***************************************************************************** // @@ -22107,9 +22107,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11326_DATA_W 32 -#define RFC_ULLRAM_BANK11326_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11326_DATA_S 0 +#define RFC_ULLRAM_BANK11326_DATA_W 32 +#define RFC_ULLRAM_BANK11326_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11326_DATA_S 0 //***************************************************************************** // @@ -22119,9 +22119,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11327_DATA_W 32 -#define RFC_ULLRAM_BANK11327_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11327_DATA_S 0 +#define RFC_ULLRAM_BANK11327_DATA_W 32 +#define RFC_ULLRAM_BANK11327_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11327_DATA_S 0 //***************************************************************************** // @@ -22131,9 +22131,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11328_DATA_W 32 -#define RFC_ULLRAM_BANK11328_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11328_DATA_S 0 +#define RFC_ULLRAM_BANK11328_DATA_W 32 +#define RFC_ULLRAM_BANK11328_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11328_DATA_S 0 //***************************************************************************** // @@ -22143,9 +22143,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11329_DATA_W 32 -#define RFC_ULLRAM_BANK11329_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11329_DATA_S 0 +#define RFC_ULLRAM_BANK11329_DATA_W 32 +#define RFC_ULLRAM_BANK11329_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11329_DATA_S 0 //***************************************************************************** // @@ -22155,9 +22155,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11330_DATA_W 32 -#define RFC_ULLRAM_BANK11330_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11330_DATA_S 0 +#define RFC_ULLRAM_BANK11330_DATA_W 32 +#define RFC_ULLRAM_BANK11330_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11330_DATA_S 0 //***************************************************************************** // @@ -22167,9 +22167,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11331_DATA_W 32 -#define RFC_ULLRAM_BANK11331_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11331_DATA_S 0 +#define RFC_ULLRAM_BANK11331_DATA_W 32 +#define RFC_ULLRAM_BANK11331_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11331_DATA_S 0 //***************************************************************************** // @@ -22179,9 +22179,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11332_DATA_W 32 -#define RFC_ULLRAM_BANK11332_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11332_DATA_S 0 +#define RFC_ULLRAM_BANK11332_DATA_W 32 +#define RFC_ULLRAM_BANK11332_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11332_DATA_S 0 //***************************************************************************** // @@ -22191,9 +22191,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11333_DATA_W 32 -#define RFC_ULLRAM_BANK11333_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11333_DATA_S 0 +#define RFC_ULLRAM_BANK11333_DATA_W 32 +#define RFC_ULLRAM_BANK11333_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11333_DATA_S 0 //***************************************************************************** // @@ -22203,9 +22203,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11334_DATA_W 32 -#define RFC_ULLRAM_BANK11334_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11334_DATA_S 0 +#define RFC_ULLRAM_BANK11334_DATA_W 32 +#define RFC_ULLRAM_BANK11334_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11334_DATA_S 0 //***************************************************************************** // @@ -22215,9 +22215,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11335_DATA_W 32 -#define RFC_ULLRAM_BANK11335_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11335_DATA_S 0 +#define RFC_ULLRAM_BANK11335_DATA_W 32 +#define RFC_ULLRAM_BANK11335_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11335_DATA_S 0 //***************************************************************************** // @@ -22227,9 +22227,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11336_DATA_W 32 -#define RFC_ULLRAM_BANK11336_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11336_DATA_S 0 +#define RFC_ULLRAM_BANK11336_DATA_W 32 +#define RFC_ULLRAM_BANK11336_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11336_DATA_S 0 //***************************************************************************** // @@ -22239,9 +22239,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11337_DATA_W 32 -#define RFC_ULLRAM_BANK11337_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11337_DATA_S 0 +#define RFC_ULLRAM_BANK11337_DATA_W 32 +#define RFC_ULLRAM_BANK11337_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11337_DATA_S 0 //***************************************************************************** // @@ -22251,9 +22251,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11338_DATA_W 32 -#define RFC_ULLRAM_BANK11338_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11338_DATA_S 0 +#define RFC_ULLRAM_BANK11338_DATA_W 32 +#define RFC_ULLRAM_BANK11338_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11338_DATA_S 0 //***************************************************************************** // @@ -22263,9 +22263,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11339_DATA_W 32 -#define RFC_ULLRAM_BANK11339_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11339_DATA_S 0 +#define RFC_ULLRAM_BANK11339_DATA_W 32 +#define RFC_ULLRAM_BANK11339_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11339_DATA_S 0 //***************************************************************************** // @@ -22275,9 +22275,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11340_DATA_W 32 -#define RFC_ULLRAM_BANK11340_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11340_DATA_S 0 +#define RFC_ULLRAM_BANK11340_DATA_W 32 +#define RFC_ULLRAM_BANK11340_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11340_DATA_S 0 //***************************************************************************** // @@ -22287,9 +22287,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11341_DATA_W 32 -#define RFC_ULLRAM_BANK11341_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11341_DATA_S 0 +#define RFC_ULLRAM_BANK11341_DATA_W 32 +#define RFC_ULLRAM_BANK11341_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11341_DATA_S 0 //***************************************************************************** // @@ -22299,9 +22299,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11342_DATA_W 32 -#define RFC_ULLRAM_BANK11342_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11342_DATA_S 0 +#define RFC_ULLRAM_BANK11342_DATA_W 32 +#define RFC_ULLRAM_BANK11342_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11342_DATA_S 0 //***************************************************************************** // @@ -22311,9 +22311,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11343_DATA_W 32 -#define RFC_ULLRAM_BANK11343_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11343_DATA_S 0 +#define RFC_ULLRAM_BANK11343_DATA_W 32 +#define RFC_ULLRAM_BANK11343_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11343_DATA_S 0 //***************************************************************************** // @@ -22323,9 +22323,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11344_DATA_W 32 -#define RFC_ULLRAM_BANK11344_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11344_DATA_S 0 +#define RFC_ULLRAM_BANK11344_DATA_W 32 +#define RFC_ULLRAM_BANK11344_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11344_DATA_S 0 //***************************************************************************** // @@ -22335,9 +22335,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11345_DATA_W 32 -#define RFC_ULLRAM_BANK11345_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11345_DATA_S 0 +#define RFC_ULLRAM_BANK11345_DATA_W 32 +#define RFC_ULLRAM_BANK11345_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11345_DATA_S 0 //***************************************************************************** // @@ -22347,9 +22347,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11346_DATA_W 32 -#define RFC_ULLRAM_BANK11346_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11346_DATA_S 0 +#define RFC_ULLRAM_BANK11346_DATA_W 32 +#define RFC_ULLRAM_BANK11346_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11346_DATA_S 0 //***************************************************************************** // @@ -22359,9 +22359,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11347_DATA_W 32 -#define RFC_ULLRAM_BANK11347_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11347_DATA_S 0 +#define RFC_ULLRAM_BANK11347_DATA_W 32 +#define RFC_ULLRAM_BANK11347_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11347_DATA_S 0 //***************************************************************************** // @@ -22371,9 +22371,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11348_DATA_W 32 -#define RFC_ULLRAM_BANK11348_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11348_DATA_S 0 +#define RFC_ULLRAM_BANK11348_DATA_W 32 +#define RFC_ULLRAM_BANK11348_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11348_DATA_S 0 //***************************************************************************** // @@ -22383,9 +22383,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11349_DATA_W 32 -#define RFC_ULLRAM_BANK11349_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11349_DATA_S 0 +#define RFC_ULLRAM_BANK11349_DATA_W 32 +#define RFC_ULLRAM_BANK11349_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11349_DATA_S 0 //***************************************************************************** // @@ -22395,9 +22395,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11350_DATA_W 32 -#define RFC_ULLRAM_BANK11350_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11350_DATA_S 0 +#define RFC_ULLRAM_BANK11350_DATA_W 32 +#define RFC_ULLRAM_BANK11350_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11350_DATA_S 0 //***************************************************************************** // @@ -22407,9 +22407,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11351_DATA_W 32 -#define RFC_ULLRAM_BANK11351_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11351_DATA_S 0 +#define RFC_ULLRAM_BANK11351_DATA_W 32 +#define RFC_ULLRAM_BANK11351_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11351_DATA_S 0 //***************************************************************************** // @@ -22419,9 +22419,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11352_DATA_W 32 -#define RFC_ULLRAM_BANK11352_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11352_DATA_S 0 +#define RFC_ULLRAM_BANK11352_DATA_W 32 +#define RFC_ULLRAM_BANK11352_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11352_DATA_S 0 //***************************************************************************** // @@ -22431,9 +22431,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11353_DATA_W 32 -#define RFC_ULLRAM_BANK11353_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11353_DATA_S 0 +#define RFC_ULLRAM_BANK11353_DATA_W 32 +#define RFC_ULLRAM_BANK11353_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11353_DATA_S 0 //***************************************************************************** // @@ -22443,9 +22443,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11354_DATA_W 32 -#define RFC_ULLRAM_BANK11354_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11354_DATA_S 0 +#define RFC_ULLRAM_BANK11354_DATA_W 32 +#define RFC_ULLRAM_BANK11354_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11354_DATA_S 0 //***************************************************************************** // @@ -22455,9 +22455,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11355_DATA_W 32 -#define RFC_ULLRAM_BANK11355_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11355_DATA_S 0 +#define RFC_ULLRAM_BANK11355_DATA_W 32 +#define RFC_ULLRAM_BANK11355_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11355_DATA_S 0 //***************************************************************************** // @@ -22467,9 +22467,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11356_DATA_W 32 -#define RFC_ULLRAM_BANK11356_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11356_DATA_S 0 +#define RFC_ULLRAM_BANK11356_DATA_W 32 +#define RFC_ULLRAM_BANK11356_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11356_DATA_S 0 //***************************************************************************** // @@ -22479,9 +22479,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11357_DATA_W 32 -#define RFC_ULLRAM_BANK11357_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11357_DATA_S 0 +#define RFC_ULLRAM_BANK11357_DATA_W 32 +#define RFC_ULLRAM_BANK11357_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11357_DATA_S 0 //***************************************************************************** // @@ -22491,9 +22491,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11358_DATA_W 32 -#define RFC_ULLRAM_BANK11358_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11358_DATA_S 0 +#define RFC_ULLRAM_BANK11358_DATA_W 32 +#define RFC_ULLRAM_BANK11358_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11358_DATA_S 0 //***************************************************************************** // @@ -22503,9 +22503,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11359_DATA_W 32 -#define RFC_ULLRAM_BANK11359_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11359_DATA_S 0 +#define RFC_ULLRAM_BANK11359_DATA_W 32 +#define RFC_ULLRAM_BANK11359_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11359_DATA_S 0 //***************************************************************************** // @@ -22515,9 +22515,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11360_DATA_W 32 -#define RFC_ULLRAM_BANK11360_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11360_DATA_S 0 +#define RFC_ULLRAM_BANK11360_DATA_W 32 +#define RFC_ULLRAM_BANK11360_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11360_DATA_S 0 //***************************************************************************** // @@ -22527,9 +22527,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11361_DATA_W 32 -#define RFC_ULLRAM_BANK11361_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11361_DATA_S 0 +#define RFC_ULLRAM_BANK11361_DATA_W 32 +#define RFC_ULLRAM_BANK11361_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11361_DATA_S 0 //***************************************************************************** // @@ -22539,9 +22539,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11362_DATA_W 32 -#define RFC_ULLRAM_BANK11362_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11362_DATA_S 0 +#define RFC_ULLRAM_BANK11362_DATA_W 32 +#define RFC_ULLRAM_BANK11362_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11362_DATA_S 0 //***************************************************************************** // @@ -22551,9 +22551,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11363_DATA_W 32 -#define RFC_ULLRAM_BANK11363_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11363_DATA_S 0 +#define RFC_ULLRAM_BANK11363_DATA_W 32 +#define RFC_ULLRAM_BANK11363_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11363_DATA_S 0 //***************************************************************************** // @@ -22563,9 +22563,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11364_DATA_W 32 -#define RFC_ULLRAM_BANK11364_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11364_DATA_S 0 +#define RFC_ULLRAM_BANK11364_DATA_W 32 +#define RFC_ULLRAM_BANK11364_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11364_DATA_S 0 //***************************************************************************** // @@ -22575,9 +22575,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11365_DATA_W 32 -#define RFC_ULLRAM_BANK11365_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11365_DATA_S 0 +#define RFC_ULLRAM_BANK11365_DATA_W 32 +#define RFC_ULLRAM_BANK11365_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11365_DATA_S 0 //***************************************************************************** // @@ -22587,9 +22587,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11366_DATA_W 32 -#define RFC_ULLRAM_BANK11366_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11366_DATA_S 0 +#define RFC_ULLRAM_BANK11366_DATA_W 32 +#define RFC_ULLRAM_BANK11366_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11366_DATA_S 0 //***************************************************************************** // @@ -22599,9 +22599,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11367_DATA_W 32 -#define RFC_ULLRAM_BANK11367_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11367_DATA_S 0 +#define RFC_ULLRAM_BANK11367_DATA_W 32 +#define RFC_ULLRAM_BANK11367_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11367_DATA_S 0 //***************************************************************************** // @@ -22611,9 +22611,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11368_DATA_W 32 -#define RFC_ULLRAM_BANK11368_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11368_DATA_S 0 +#define RFC_ULLRAM_BANK11368_DATA_W 32 +#define RFC_ULLRAM_BANK11368_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11368_DATA_S 0 //***************************************************************************** // @@ -22623,9 +22623,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11369_DATA_W 32 -#define RFC_ULLRAM_BANK11369_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11369_DATA_S 0 +#define RFC_ULLRAM_BANK11369_DATA_W 32 +#define RFC_ULLRAM_BANK11369_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11369_DATA_S 0 //***************************************************************************** // @@ -22635,9 +22635,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11370_DATA_W 32 -#define RFC_ULLRAM_BANK11370_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11370_DATA_S 0 +#define RFC_ULLRAM_BANK11370_DATA_W 32 +#define RFC_ULLRAM_BANK11370_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11370_DATA_S 0 //***************************************************************************** // @@ -22647,9 +22647,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11371_DATA_W 32 -#define RFC_ULLRAM_BANK11371_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11371_DATA_S 0 +#define RFC_ULLRAM_BANK11371_DATA_W 32 +#define RFC_ULLRAM_BANK11371_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11371_DATA_S 0 //***************************************************************************** // @@ -22659,9 +22659,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11372_DATA_W 32 -#define RFC_ULLRAM_BANK11372_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11372_DATA_S 0 +#define RFC_ULLRAM_BANK11372_DATA_W 32 +#define RFC_ULLRAM_BANK11372_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11372_DATA_S 0 //***************************************************************************** // @@ -22671,9 +22671,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11373_DATA_W 32 -#define RFC_ULLRAM_BANK11373_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11373_DATA_S 0 +#define RFC_ULLRAM_BANK11373_DATA_W 32 +#define RFC_ULLRAM_BANK11373_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11373_DATA_S 0 //***************************************************************************** // @@ -22683,9 +22683,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11374_DATA_W 32 -#define RFC_ULLRAM_BANK11374_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11374_DATA_S 0 +#define RFC_ULLRAM_BANK11374_DATA_W 32 +#define RFC_ULLRAM_BANK11374_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11374_DATA_S 0 //***************************************************************************** // @@ -22695,9 +22695,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11375_DATA_W 32 -#define RFC_ULLRAM_BANK11375_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11375_DATA_S 0 +#define RFC_ULLRAM_BANK11375_DATA_W 32 +#define RFC_ULLRAM_BANK11375_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11375_DATA_S 0 //***************************************************************************** // @@ -22707,9 +22707,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11376_DATA_W 32 -#define RFC_ULLRAM_BANK11376_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11376_DATA_S 0 +#define RFC_ULLRAM_BANK11376_DATA_W 32 +#define RFC_ULLRAM_BANK11376_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11376_DATA_S 0 //***************************************************************************** // @@ -22719,9 +22719,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11377_DATA_W 32 -#define RFC_ULLRAM_BANK11377_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11377_DATA_S 0 +#define RFC_ULLRAM_BANK11377_DATA_W 32 +#define RFC_ULLRAM_BANK11377_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11377_DATA_S 0 //***************************************************************************** // @@ -22731,9 +22731,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11378_DATA_W 32 -#define RFC_ULLRAM_BANK11378_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11378_DATA_S 0 +#define RFC_ULLRAM_BANK11378_DATA_W 32 +#define RFC_ULLRAM_BANK11378_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11378_DATA_S 0 //***************************************************************************** // @@ -22743,9 +22743,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11379_DATA_W 32 -#define RFC_ULLRAM_BANK11379_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11379_DATA_S 0 +#define RFC_ULLRAM_BANK11379_DATA_W 32 +#define RFC_ULLRAM_BANK11379_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11379_DATA_S 0 //***************************************************************************** // @@ -22755,9 +22755,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11380_DATA_W 32 -#define RFC_ULLRAM_BANK11380_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11380_DATA_S 0 +#define RFC_ULLRAM_BANK11380_DATA_W 32 +#define RFC_ULLRAM_BANK11380_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11380_DATA_S 0 //***************************************************************************** // @@ -22767,9 +22767,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11381_DATA_W 32 -#define RFC_ULLRAM_BANK11381_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11381_DATA_S 0 +#define RFC_ULLRAM_BANK11381_DATA_W 32 +#define RFC_ULLRAM_BANK11381_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11381_DATA_S 0 //***************************************************************************** // @@ -22779,9 +22779,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11382_DATA_W 32 -#define RFC_ULLRAM_BANK11382_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11382_DATA_S 0 +#define RFC_ULLRAM_BANK11382_DATA_W 32 +#define RFC_ULLRAM_BANK11382_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11382_DATA_S 0 //***************************************************************************** // @@ -22791,9 +22791,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11383_DATA_W 32 -#define RFC_ULLRAM_BANK11383_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11383_DATA_S 0 +#define RFC_ULLRAM_BANK11383_DATA_W 32 +#define RFC_ULLRAM_BANK11383_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11383_DATA_S 0 //***************************************************************************** // @@ -22803,9 +22803,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11384_DATA_W 32 -#define RFC_ULLRAM_BANK11384_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11384_DATA_S 0 +#define RFC_ULLRAM_BANK11384_DATA_W 32 +#define RFC_ULLRAM_BANK11384_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11384_DATA_S 0 //***************************************************************************** // @@ -22815,9 +22815,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11385_DATA_W 32 -#define RFC_ULLRAM_BANK11385_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11385_DATA_S 0 +#define RFC_ULLRAM_BANK11385_DATA_W 32 +#define RFC_ULLRAM_BANK11385_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11385_DATA_S 0 //***************************************************************************** // @@ -22827,9 +22827,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11386_DATA_W 32 -#define RFC_ULLRAM_BANK11386_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11386_DATA_S 0 +#define RFC_ULLRAM_BANK11386_DATA_W 32 +#define RFC_ULLRAM_BANK11386_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11386_DATA_S 0 //***************************************************************************** // @@ -22839,9 +22839,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11387_DATA_W 32 -#define RFC_ULLRAM_BANK11387_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11387_DATA_S 0 +#define RFC_ULLRAM_BANK11387_DATA_W 32 +#define RFC_ULLRAM_BANK11387_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11387_DATA_S 0 //***************************************************************************** // @@ -22851,9 +22851,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11388_DATA_W 32 -#define RFC_ULLRAM_BANK11388_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11388_DATA_S 0 +#define RFC_ULLRAM_BANK11388_DATA_W 32 +#define RFC_ULLRAM_BANK11388_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11388_DATA_S 0 //***************************************************************************** // @@ -22863,9 +22863,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11389_DATA_W 32 -#define RFC_ULLRAM_BANK11389_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11389_DATA_S 0 +#define RFC_ULLRAM_BANK11389_DATA_W 32 +#define RFC_ULLRAM_BANK11389_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11389_DATA_S 0 //***************************************************************************** // @@ -22875,9 +22875,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11390_DATA_W 32 -#define RFC_ULLRAM_BANK11390_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11390_DATA_S 0 +#define RFC_ULLRAM_BANK11390_DATA_W 32 +#define RFC_ULLRAM_BANK11390_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11390_DATA_S 0 //***************************************************************************** // @@ -22887,9 +22887,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11391_DATA_W 32 -#define RFC_ULLRAM_BANK11391_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11391_DATA_S 0 +#define RFC_ULLRAM_BANK11391_DATA_W 32 +#define RFC_ULLRAM_BANK11391_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11391_DATA_S 0 //***************************************************************************** // @@ -22899,9 +22899,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11392_DATA_W 32 -#define RFC_ULLRAM_BANK11392_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11392_DATA_S 0 +#define RFC_ULLRAM_BANK11392_DATA_W 32 +#define RFC_ULLRAM_BANK11392_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11392_DATA_S 0 //***************************************************************************** // @@ -22911,9 +22911,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11393_DATA_W 32 -#define RFC_ULLRAM_BANK11393_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11393_DATA_S 0 +#define RFC_ULLRAM_BANK11393_DATA_W 32 +#define RFC_ULLRAM_BANK11393_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11393_DATA_S 0 //***************************************************************************** // @@ -22923,9 +22923,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11394_DATA_W 32 -#define RFC_ULLRAM_BANK11394_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11394_DATA_S 0 +#define RFC_ULLRAM_BANK11394_DATA_W 32 +#define RFC_ULLRAM_BANK11394_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11394_DATA_S 0 //***************************************************************************** // @@ -22935,9 +22935,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11395_DATA_W 32 -#define RFC_ULLRAM_BANK11395_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11395_DATA_S 0 +#define RFC_ULLRAM_BANK11395_DATA_W 32 +#define RFC_ULLRAM_BANK11395_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11395_DATA_S 0 //***************************************************************************** // @@ -22947,9 +22947,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11396_DATA_W 32 -#define RFC_ULLRAM_BANK11396_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11396_DATA_S 0 +#define RFC_ULLRAM_BANK11396_DATA_W 32 +#define RFC_ULLRAM_BANK11396_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11396_DATA_S 0 //***************************************************************************** // @@ -22959,9 +22959,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11397_DATA_W 32 -#define RFC_ULLRAM_BANK11397_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11397_DATA_S 0 +#define RFC_ULLRAM_BANK11397_DATA_W 32 +#define RFC_ULLRAM_BANK11397_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11397_DATA_S 0 //***************************************************************************** // @@ -22971,9 +22971,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11398_DATA_W 32 -#define RFC_ULLRAM_BANK11398_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11398_DATA_S 0 +#define RFC_ULLRAM_BANK11398_DATA_W 32 +#define RFC_ULLRAM_BANK11398_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11398_DATA_S 0 //***************************************************************************** // @@ -22983,9 +22983,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11399_DATA_W 32 -#define RFC_ULLRAM_BANK11399_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11399_DATA_S 0 +#define RFC_ULLRAM_BANK11399_DATA_W 32 +#define RFC_ULLRAM_BANK11399_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11399_DATA_S 0 //***************************************************************************** // @@ -22995,9 +22995,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11400_DATA_W 32 -#define RFC_ULLRAM_BANK11400_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11400_DATA_S 0 +#define RFC_ULLRAM_BANK11400_DATA_W 32 +#define RFC_ULLRAM_BANK11400_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11400_DATA_S 0 //***************************************************************************** // @@ -23007,9 +23007,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11401_DATA_W 32 -#define RFC_ULLRAM_BANK11401_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11401_DATA_S 0 +#define RFC_ULLRAM_BANK11401_DATA_W 32 +#define RFC_ULLRAM_BANK11401_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11401_DATA_S 0 //***************************************************************************** // @@ -23019,9 +23019,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11402_DATA_W 32 -#define RFC_ULLRAM_BANK11402_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11402_DATA_S 0 +#define RFC_ULLRAM_BANK11402_DATA_W 32 +#define RFC_ULLRAM_BANK11402_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11402_DATA_S 0 //***************************************************************************** // @@ -23031,9 +23031,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11403_DATA_W 32 -#define RFC_ULLRAM_BANK11403_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11403_DATA_S 0 +#define RFC_ULLRAM_BANK11403_DATA_W 32 +#define RFC_ULLRAM_BANK11403_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11403_DATA_S 0 //***************************************************************************** // @@ -23043,9 +23043,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11404_DATA_W 32 -#define RFC_ULLRAM_BANK11404_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11404_DATA_S 0 +#define RFC_ULLRAM_BANK11404_DATA_W 32 +#define RFC_ULLRAM_BANK11404_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11404_DATA_S 0 //***************************************************************************** // @@ -23055,9 +23055,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11405_DATA_W 32 -#define RFC_ULLRAM_BANK11405_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11405_DATA_S 0 +#define RFC_ULLRAM_BANK11405_DATA_W 32 +#define RFC_ULLRAM_BANK11405_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11405_DATA_S 0 //***************************************************************************** // @@ -23067,9 +23067,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11406_DATA_W 32 -#define RFC_ULLRAM_BANK11406_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11406_DATA_S 0 +#define RFC_ULLRAM_BANK11406_DATA_W 32 +#define RFC_ULLRAM_BANK11406_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11406_DATA_S 0 //***************************************************************************** // @@ -23079,9 +23079,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11407_DATA_W 32 -#define RFC_ULLRAM_BANK11407_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11407_DATA_S 0 +#define RFC_ULLRAM_BANK11407_DATA_W 32 +#define RFC_ULLRAM_BANK11407_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11407_DATA_S 0 //***************************************************************************** // @@ -23091,9 +23091,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11408_DATA_W 32 -#define RFC_ULLRAM_BANK11408_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11408_DATA_S 0 +#define RFC_ULLRAM_BANK11408_DATA_W 32 +#define RFC_ULLRAM_BANK11408_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11408_DATA_S 0 //***************************************************************************** // @@ -23103,9 +23103,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11409_DATA_W 32 -#define RFC_ULLRAM_BANK11409_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11409_DATA_S 0 +#define RFC_ULLRAM_BANK11409_DATA_W 32 +#define RFC_ULLRAM_BANK11409_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11409_DATA_S 0 //***************************************************************************** // @@ -23115,9 +23115,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11410_DATA_W 32 -#define RFC_ULLRAM_BANK11410_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11410_DATA_S 0 +#define RFC_ULLRAM_BANK11410_DATA_W 32 +#define RFC_ULLRAM_BANK11410_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11410_DATA_S 0 //***************************************************************************** // @@ -23127,9 +23127,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11411_DATA_W 32 -#define RFC_ULLRAM_BANK11411_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11411_DATA_S 0 +#define RFC_ULLRAM_BANK11411_DATA_W 32 +#define RFC_ULLRAM_BANK11411_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11411_DATA_S 0 //***************************************************************************** // @@ -23139,9 +23139,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11412_DATA_W 32 -#define RFC_ULLRAM_BANK11412_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11412_DATA_S 0 +#define RFC_ULLRAM_BANK11412_DATA_W 32 +#define RFC_ULLRAM_BANK11412_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11412_DATA_S 0 //***************************************************************************** // @@ -23151,9 +23151,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11413_DATA_W 32 -#define RFC_ULLRAM_BANK11413_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11413_DATA_S 0 +#define RFC_ULLRAM_BANK11413_DATA_W 32 +#define RFC_ULLRAM_BANK11413_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11413_DATA_S 0 //***************************************************************************** // @@ -23163,9 +23163,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11414_DATA_W 32 -#define RFC_ULLRAM_BANK11414_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11414_DATA_S 0 +#define RFC_ULLRAM_BANK11414_DATA_W 32 +#define RFC_ULLRAM_BANK11414_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11414_DATA_S 0 //***************************************************************************** // @@ -23175,9 +23175,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11415_DATA_W 32 -#define RFC_ULLRAM_BANK11415_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11415_DATA_S 0 +#define RFC_ULLRAM_BANK11415_DATA_W 32 +#define RFC_ULLRAM_BANK11415_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11415_DATA_S 0 //***************************************************************************** // @@ -23187,9 +23187,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11416_DATA_W 32 -#define RFC_ULLRAM_BANK11416_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11416_DATA_S 0 +#define RFC_ULLRAM_BANK11416_DATA_W 32 +#define RFC_ULLRAM_BANK11416_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11416_DATA_S 0 //***************************************************************************** // @@ -23199,9 +23199,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11417_DATA_W 32 -#define RFC_ULLRAM_BANK11417_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11417_DATA_S 0 +#define RFC_ULLRAM_BANK11417_DATA_W 32 +#define RFC_ULLRAM_BANK11417_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11417_DATA_S 0 //***************************************************************************** // @@ -23211,9 +23211,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11418_DATA_W 32 -#define RFC_ULLRAM_BANK11418_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11418_DATA_S 0 +#define RFC_ULLRAM_BANK11418_DATA_W 32 +#define RFC_ULLRAM_BANK11418_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11418_DATA_S 0 //***************************************************************************** // @@ -23223,9 +23223,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11419_DATA_W 32 -#define RFC_ULLRAM_BANK11419_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11419_DATA_S 0 +#define RFC_ULLRAM_BANK11419_DATA_W 32 +#define RFC_ULLRAM_BANK11419_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11419_DATA_S 0 //***************************************************************************** // @@ -23235,9 +23235,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11420_DATA_W 32 -#define RFC_ULLRAM_BANK11420_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11420_DATA_S 0 +#define RFC_ULLRAM_BANK11420_DATA_W 32 +#define RFC_ULLRAM_BANK11420_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11420_DATA_S 0 //***************************************************************************** // @@ -23247,9 +23247,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11421_DATA_W 32 -#define RFC_ULLRAM_BANK11421_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11421_DATA_S 0 +#define RFC_ULLRAM_BANK11421_DATA_W 32 +#define RFC_ULLRAM_BANK11421_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11421_DATA_S 0 //***************************************************************************** // @@ -23259,9 +23259,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11422_DATA_W 32 -#define RFC_ULLRAM_BANK11422_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11422_DATA_S 0 +#define RFC_ULLRAM_BANK11422_DATA_W 32 +#define RFC_ULLRAM_BANK11422_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11422_DATA_S 0 //***************************************************************************** // @@ -23271,9 +23271,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11423_DATA_W 32 -#define RFC_ULLRAM_BANK11423_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11423_DATA_S 0 +#define RFC_ULLRAM_BANK11423_DATA_W 32 +#define RFC_ULLRAM_BANK11423_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11423_DATA_S 0 //***************************************************************************** // @@ -23283,9 +23283,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11424_DATA_W 32 -#define RFC_ULLRAM_BANK11424_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11424_DATA_S 0 +#define RFC_ULLRAM_BANK11424_DATA_W 32 +#define RFC_ULLRAM_BANK11424_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11424_DATA_S 0 //***************************************************************************** // @@ -23295,9 +23295,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11425_DATA_W 32 -#define RFC_ULLRAM_BANK11425_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11425_DATA_S 0 +#define RFC_ULLRAM_BANK11425_DATA_W 32 +#define RFC_ULLRAM_BANK11425_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11425_DATA_S 0 //***************************************************************************** // @@ -23307,9 +23307,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11426_DATA_W 32 -#define RFC_ULLRAM_BANK11426_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11426_DATA_S 0 +#define RFC_ULLRAM_BANK11426_DATA_W 32 +#define RFC_ULLRAM_BANK11426_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11426_DATA_S 0 //***************************************************************************** // @@ -23319,9 +23319,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11427_DATA_W 32 -#define RFC_ULLRAM_BANK11427_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11427_DATA_S 0 +#define RFC_ULLRAM_BANK11427_DATA_W 32 +#define RFC_ULLRAM_BANK11427_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11427_DATA_S 0 //***************************************************************************** // @@ -23331,9 +23331,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11428_DATA_W 32 -#define RFC_ULLRAM_BANK11428_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11428_DATA_S 0 +#define RFC_ULLRAM_BANK11428_DATA_W 32 +#define RFC_ULLRAM_BANK11428_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11428_DATA_S 0 //***************************************************************************** // @@ -23343,9 +23343,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11429_DATA_W 32 -#define RFC_ULLRAM_BANK11429_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11429_DATA_S 0 +#define RFC_ULLRAM_BANK11429_DATA_W 32 +#define RFC_ULLRAM_BANK11429_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11429_DATA_S 0 //***************************************************************************** // @@ -23355,9 +23355,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11430_DATA_W 32 -#define RFC_ULLRAM_BANK11430_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11430_DATA_S 0 +#define RFC_ULLRAM_BANK11430_DATA_W 32 +#define RFC_ULLRAM_BANK11430_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11430_DATA_S 0 //***************************************************************************** // @@ -23367,9 +23367,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11431_DATA_W 32 -#define RFC_ULLRAM_BANK11431_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11431_DATA_S 0 +#define RFC_ULLRAM_BANK11431_DATA_W 32 +#define RFC_ULLRAM_BANK11431_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11431_DATA_S 0 //***************************************************************************** // @@ -23379,9 +23379,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11432_DATA_W 32 -#define RFC_ULLRAM_BANK11432_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11432_DATA_S 0 +#define RFC_ULLRAM_BANK11432_DATA_W 32 +#define RFC_ULLRAM_BANK11432_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11432_DATA_S 0 //***************************************************************************** // @@ -23391,9 +23391,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11433_DATA_W 32 -#define RFC_ULLRAM_BANK11433_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11433_DATA_S 0 +#define RFC_ULLRAM_BANK11433_DATA_W 32 +#define RFC_ULLRAM_BANK11433_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11433_DATA_S 0 //***************************************************************************** // @@ -23403,9 +23403,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11434_DATA_W 32 -#define RFC_ULLRAM_BANK11434_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11434_DATA_S 0 +#define RFC_ULLRAM_BANK11434_DATA_W 32 +#define RFC_ULLRAM_BANK11434_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11434_DATA_S 0 //***************************************************************************** // @@ -23415,9 +23415,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11435_DATA_W 32 -#define RFC_ULLRAM_BANK11435_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11435_DATA_S 0 +#define RFC_ULLRAM_BANK11435_DATA_W 32 +#define RFC_ULLRAM_BANK11435_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11435_DATA_S 0 //***************************************************************************** // @@ -23427,9 +23427,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11436_DATA_W 32 -#define RFC_ULLRAM_BANK11436_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11436_DATA_S 0 +#define RFC_ULLRAM_BANK11436_DATA_W 32 +#define RFC_ULLRAM_BANK11436_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11436_DATA_S 0 //***************************************************************************** // @@ -23439,9 +23439,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11437_DATA_W 32 -#define RFC_ULLRAM_BANK11437_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11437_DATA_S 0 +#define RFC_ULLRAM_BANK11437_DATA_W 32 +#define RFC_ULLRAM_BANK11437_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11437_DATA_S 0 //***************************************************************************** // @@ -23451,9 +23451,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11438_DATA_W 32 -#define RFC_ULLRAM_BANK11438_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11438_DATA_S 0 +#define RFC_ULLRAM_BANK11438_DATA_W 32 +#define RFC_ULLRAM_BANK11438_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11438_DATA_S 0 //***************************************************************************** // @@ -23463,9 +23463,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11439_DATA_W 32 -#define RFC_ULLRAM_BANK11439_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11439_DATA_S 0 +#define RFC_ULLRAM_BANK11439_DATA_W 32 +#define RFC_ULLRAM_BANK11439_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11439_DATA_S 0 //***************************************************************************** // @@ -23475,9 +23475,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11440_DATA_W 32 -#define RFC_ULLRAM_BANK11440_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11440_DATA_S 0 +#define RFC_ULLRAM_BANK11440_DATA_W 32 +#define RFC_ULLRAM_BANK11440_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11440_DATA_S 0 //***************************************************************************** // @@ -23487,9 +23487,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11441_DATA_W 32 -#define RFC_ULLRAM_BANK11441_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11441_DATA_S 0 +#define RFC_ULLRAM_BANK11441_DATA_W 32 +#define RFC_ULLRAM_BANK11441_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11441_DATA_S 0 //***************************************************************************** // @@ -23499,9 +23499,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11442_DATA_W 32 -#define RFC_ULLRAM_BANK11442_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11442_DATA_S 0 +#define RFC_ULLRAM_BANK11442_DATA_W 32 +#define RFC_ULLRAM_BANK11442_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11442_DATA_S 0 //***************************************************************************** // @@ -23511,9 +23511,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11443_DATA_W 32 -#define RFC_ULLRAM_BANK11443_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11443_DATA_S 0 +#define RFC_ULLRAM_BANK11443_DATA_W 32 +#define RFC_ULLRAM_BANK11443_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11443_DATA_S 0 //***************************************************************************** // @@ -23523,9 +23523,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11444_DATA_W 32 -#define RFC_ULLRAM_BANK11444_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11444_DATA_S 0 +#define RFC_ULLRAM_BANK11444_DATA_W 32 +#define RFC_ULLRAM_BANK11444_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11444_DATA_S 0 //***************************************************************************** // @@ -23535,9 +23535,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11445_DATA_W 32 -#define RFC_ULLRAM_BANK11445_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11445_DATA_S 0 +#define RFC_ULLRAM_BANK11445_DATA_W 32 +#define RFC_ULLRAM_BANK11445_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11445_DATA_S 0 //***************************************************************************** // @@ -23547,9 +23547,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11446_DATA_W 32 -#define RFC_ULLRAM_BANK11446_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11446_DATA_S 0 +#define RFC_ULLRAM_BANK11446_DATA_W 32 +#define RFC_ULLRAM_BANK11446_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11446_DATA_S 0 //***************************************************************************** // @@ -23559,9 +23559,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11447_DATA_W 32 -#define RFC_ULLRAM_BANK11447_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11447_DATA_S 0 +#define RFC_ULLRAM_BANK11447_DATA_W 32 +#define RFC_ULLRAM_BANK11447_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11447_DATA_S 0 //***************************************************************************** // @@ -23571,9 +23571,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11448_DATA_W 32 -#define RFC_ULLRAM_BANK11448_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11448_DATA_S 0 +#define RFC_ULLRAM_BANK11448_DATA_W 32 +#define RFC_ULLRAM_BANK11448_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11448_DATA_S 0 //***************************************************************************** // @@ -23583,9 +23583,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11449_DATA_W 32 -#define RFC_ULLRAM_BANK11449_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11449_DATA_S 0 +#define RFC_ULLRAM_BANK11449_DATA_W 32 +#define RFC_ULLRAM_BANK11449_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11449_DATA_S 0 //***************************************************************************** // @@ -23595,9 +23595,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11450_DATA_W 32 -#define RFC_ULLRAM_BANK11450_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11450_DATA_S 0 +#define RFC_ULLRAM_BANK11450_DATA_W 32 +#define RFC_ULLRAM_BANK11450_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11450_DATA_S 0 //***************************************************************************** // @@ -23607,9 +23607,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11451_DATA_W 32 -#define RFC_ULLRAM_BANK11451_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11451_DATA_S 0 +#define RFC_ULLRAM_BANK11451_DATA_W 32 +#define RFC_ULLRAM_BANK11451_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11451_DATA_S 0 //***************************************************************************** // @@ -23619,9 +23619,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11452_DATA_W 32 -#define RFC_ULLRAM_BANK11452_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11452_DATA_S 0 +#define RFC_ULLRAM_BANK11452_DATA_W 32 +#define RFC_ULLRAM_BANK11452_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11452_DATA_S 0 //***************************************************************************** // @@ -23631,9 +23631,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11453_DATA_W 32 -#define RFC_ULLRAM_BANK11453_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11453_DATA_S 0 +#define RFC_ULLRAM_BANK11453_DATA_W 32 +#define RFC_ULLRAM_BANK11453_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11453_DATA_S 0 //***************************************************************************** // @@ -23643,9 +23643,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11454_DATA_W 32 -#define RFC_ULLRAM_BANK11454_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11454_DATA_S 0 +#define RFC_ULLRAM_BANK11454_DATA_W 32 +#define RFC_ULLRAM_BANK11454_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11454_DATA_S 0 //***************************************************************************** // @@ -23655,9 +23655,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11455_DATA_W 32 -#define RFC_ULLRAM_BANK11455_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11455_DATA_S 0 +#define RFC_ULLRAM_BANK11455_DATA_W 32 +#define RFC_ULLRAM_BANK11455_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11455_DATA_S 0 //***************************************************************************** // @@ -23667,9 +23667,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11456_DATA_W 32 -#define RFC_ULLRAM_BANK11456_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11456_DATA_S 0 +#define RFC_ULLRAM_BANK11456_DATA_W 32 +#define RFC_ULLRAM_BANK11456_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11456_DATA_S 0 //***************************************************************************** // @@ -23679,9 +23679,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11457_DATA_W 32 -#define RFC_ULLRAM_BANK11457_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11457_DATA_S 0 +#define RFC_ULLRAM_BANK11457_DATA_W 32 +#define RFC_ULLRAM_BANK11457_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11457_DATA_S 0 //***************************************************************************** // @@ -23691,9 +23691,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11458_DATA_W 32 -#define RFC_ULLRAM_BANK11458_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11458_DATA_S 0 +#define RFC_ULLRAM_BANK11458_DATA_W 32 +#define RFC_ULLRAM_BANK11458_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11458_DATA_S 0 //***************************************************************************** // @@ -23703,9 +23703,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11459_DATA_W 32 -#define RFC_ULLRAM_BANK11459_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11459_DATA_S 0 +#define RFC_ULLRAM_BANK11459_DATA_W 32 +#define RFC_ULLRAM_BANK11459_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11459_DATA_S 0 //***************************************************************************** // @@ -23715,9 +23715,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11460_DATA_W 32 -#define RFC_ULLRAM_BANK11460_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11460_DATA_S 0 +#define RFC_ULLRAM_BANK11460_DATA_W 32 +#define RFC_ULLRAM_BANK11460_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11460_DATA_S 0 //***************************************************************************** // @@ -23727,9 +23727,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11461_DATA_W 32 -#define RFC_ULLRAM_BANK11461_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11461_DATA_S 0 +#define RFC_ULLRAM_BANK11461_DATA_W 32 +#define RFC_ULLRAM_BANK11461_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11461_DATA_S 0 //***************************************************************************** // @@ -23739,9 +23739,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11462_DATA_W 32 -#define RFC_ULLRAM_BANK11462_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11462_DATA_S 0 +#define RFC_ULLRAM_BANK11462_DATA_W 32 +#define RFC_ULLRAM_BANK11462_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11462_DATA_S 0 //***************************************************************************** // @@ -23751,9 +23751,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11463_DATA_W 32 -#define RFC_ULLRAM_BANK11463_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11463_DATA_S 0 +#define RFC_ULLRAM_BANK11463_DATA_W 32 +#define RFC_ULLRAM_BANK11463_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11463_DATA_S 0 //***************************************************************************** // @@ -23763,9 +23763,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11464_DATA_W 32 -#define RFC_ULLRAM_BANK11464_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11464_DATA_S 0 +#define RFC_ULLRAM_BANK11464_DATA_W 32 +#define RFC_ULLRAM_BANK11464_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11464_DATA_S 0 //***************************************************************************** // @@ -23775,9 +23775,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11465_DATA_W 32 -#define RFC_ULLRAM_BANK11465_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11465_DATA_S 0 +#define RFC_ULLRAM_BANK11465_DATA_W 32 +#define RFC_ULLRAM_BANK11465_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11465_DATA_S 0 //***************************************************************************** // @@ -23787,9 +23787,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11466_DATA_W 32 -#define RFC_ULLRAM_BANK11466_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11466_DATA_S 0 +#define RFC_ULLRAM_BANK11466_DATA_W 32 +#define RFC_ULLRAM_BANK11466_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11466_DATA_S 0 //***************************************************************************** // @@ -23799,9 +23799,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11467_DATA_W 32 -#define RFC_ULLRAM_BANK11467_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11467_DATA_S 0 +#define RFC_ULLRAM_BANK11467_DATA_W 32 +#define RFC_ULLRAM_BANK11467_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11467_DATA_S 0 //***************************************************************************** // @@ -23811,9 +23811,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11468_DATA_W 32 -#define RFC_ULLRAM_BANK11468_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11468_DATA_S 0 +#define RFC_ULLRAM_BANK11468_DATA_W 32 +#define RFC_ULLRAM_BANK11468_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11468_DATA_S 0 //***************************************************************************** // @@ -23823,9 +23823,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11469_DATA_W 32 -#define RFC_ULLRAM_BANK11469_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11469_DATA_S 0 +#define RFC_ULLRAM_BANK11469_DATA_W 32 +#define RFC_ULLRAM_BANK11469_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11469_DATA_S 0 //***************************************************************************** // @@ -23835,9 +23835,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11470_DATA_W 32 -#define RFC_ULLRAM_BANK11470_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11470_DATA_S 0 +#define RFC_ULLRAM_BANK11470_DATA_W 32 +#define RFC_ULLRAM_BANK11470_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11470_DATA_S 0 //***************************************************************************** // @@ -23847,9 +23847,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11471_DATA_W 32 -#define RFC_ULLRAM_BANK11471_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11471_DATA_S 0 +#define RFC_ULLRAM_BANK11471_DATA_W 32 +#define RFC_ULLRAM_BANK11471_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11471_DATA_S 0 //***************************************************************************** // @@ -23859,9 +23859,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11472_DATA_W 32 -#define RFC_ULLRAM_BANK11472_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11472_DATA_S 0 +#define RFC_ULLRAM_BANK11472_DATA_W 32 +#define RFC_ULLRAM_BANK11472_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11472_DATA_S 0 //***************************************************************************** // @@ -23871,9 +23871,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11473_DATA_W 32 -#define RFC_ULLRAM_BANK11473_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11473_DATA_S 0 +#define RFC_ULLRAM_BANK11473_DATA_W 32 +#define RFC_ULLRAM_BANK11473_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11473_DATA_S 0 //***************************************************************************** // @@ -23883,9 +23883,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11474_DATA_W 32 -#define RFC_ULLRAM_BANK11474_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11474_DATA_S 0 +#define RFC_ULLRAM_BANK11474_DATA_W 32 +#define RFC_ULLRAM_BANK11474_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11474_DATA_S 0 //***************************************************************************** // @@ -23895,9 +23895,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11475_DATA_W 32 -#define RFC_ULLRAM_BANK11475_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11475_DATA_S 0 +#define RFC_ULLRAM_BANK11475_DATA_W 32 +#define RFC_ULLRAM_BANK11475_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11475_DATA_S 0 //***************************************************************************** // @@ -23907,9 +23907,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11476_DATA_W 32 -#define RFC_ULLRAM_BANK11476_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11476_DATA_S 0 +#define RFC_ULLRAM_BANK11476_DATA_W 32 +#define RFC_ULLRAM_BANK11476_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11476_DATA_S 0 //***************************************************************************** // @@ -23919,9 +23919,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11477_DATA_W 32 -#define RFC_ULLRAM_BANK11477_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11477_DATA_S 0 +#define RFC_ULLRAM_BANK11477_DATA_W 32 +#define RFC_ULLRAM_BANK11477_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11477_DATA_S 0 //***************************************************************************** // @@ -23931,9 +23931,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11478_DATA_W 32 -#define RFC_ULLRAM_BANK11478_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11478_DATA_S 0 +#define RFC_ULLRAM_BANK11478_DATA_W 32 +#define RFC_ULLRAM_BANK11478_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11478_DATA_S 0 //***************************************************************************** // @@ -23943,9 +23943,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11479_DATA_W 32 -#define RFC_ULLRAM_BANK11479_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11479_DATA_S 0 +#define RFC_ULLRAM_BANK11479_DATA_W 32 +#define RFC_ULLRAM_BANK11479_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11479_DATA_S 0 //***************************************************************************** // @@ -23955,9 +23955,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11480_DATA_W 32 -#define RFC_ULLRAM_BANK11480_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11480_DATA_S 0 +#define RFC_ULLRAM_BANK11480_DATA_W 32 +#define RFC_ULLRAM_BANK11480_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11480_DATA_S 0 //***************************************************************************** // @@ -23967,9 +23967,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11481_DATA_W 32 -#define RFC_ULLRAM_BANK11481_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11481_DATA_S 0 +#define RFC_ULLRAM_BANK11481_DATA_W 32 +#define RFC_ULLRAM_BANK11481_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11481_DATA_S 0 //***************************************************************************** // @@ -23979,9 +23979,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11482_DATA_W 32 -#define RFC_ULLRAM_BANK11482_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11482_DATA_S 0 +#define RFC_ULLRAM_BANK11482_DATA_W 32 +#define RFC_ULLRAM_BANK11482_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11482_DATA_S 0 //***************************************************************************** // @@ -23991,9 +23991,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11483_DATA_W 32 -#define RFC_ULLRAM_BANK11483_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11483_DATA_S 0 +#define RFC_ULLRAM_BANK11483_DATA_W 32 +#define RFC_ULLRAM_BANK11483_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11483_DATA_S 0 //***************************************************************************** // @@ -24003,9 +24003,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11484_DATA_W 32 -#define RFC_ULLRAM_BANK11484_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11484_DATA_S 0 +#define RFC_ULLRAM_BANK11484_DATA_W 32 +#define RFC_ULLRAM_BANK11484_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11484_DATA_S 0 //***************************************************************************** // @@ -24015,9 +24015,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11485_DATA_W 32 -#define RFC_ULLRAM_BANK11485_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11485_DATA_S 0 +#define RFC_ULLRAM_BANK11485_DATA_W 32 +#define RFC_ULLRAM_BANK11485_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11485_DATA_S 0 //***************************************************************************** // @@ -24027,9 +24027,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11486_DATA_W 32 -#define RFC_ULLRAM_BANK11486_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11486_DATA_S 0 +#define RFC_ULLRAM_BANK11486_DATA_W 32 +#define RFC_ULLRAM_BANK11486_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11486_DATA_S 0 //***************************************************************************** // @@ -24039,9 +24039,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11487_DATA_W 32 -#define RFC_ULLRAM_BANK11487_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11487_DATA_S 0 +#define RFC_ULLRAM_BANK11487_DATA_W 32 +#define RFC_ULLRAM_BANK11487_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11487_DATA_S 0 //***************************************************************************** // @@ -24051,9 +24051,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11488_DATA_W 32 -#define RFC_ULLRAM_BANK11488_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11488_DATA_S 0 +#define RFC_ULLRAM_BANK11488_DATA_W 32 +#define RFC_ULLRAM_BANK11488_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11488_DATA_S 0 //***************************************************************************** // @@ -24063,9 +24063,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11489_DATA_W 32 -#define RFC_ULLRAM_BANK11489_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11489_DATA_S 0 +#define RFC_ULLRAM_BANK11489_DATA_W 32 +#define RFC_ULLRAM_BANK11489_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11489_DATA_S 0 //***************************************************************************** // @@ -24075,9 +24075,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11490_DATA_W 32 -#define RFC_ULLRAM_BANK11490_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11490_DATA_S 0 +#define RFC_ULLRAM_BANK11490_DATA_W 32 +#define RFC_ULLRAM_BANK11490_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11490_DATA_S 0 //***************************************************************************** // @@ -24087,9 +24087,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11491_DATA_W 32 -#define RFC_ULLRAM_BANK11491_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11491_DATA_S 0 +#define RFC_ULLRAM_BANK11491_DATA_W 32 +#define RFC_ULLRAM_BANK11491_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11491_DATA_S 0 //***************************************************************************** // @@ -24099,9 +24099,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11492_DATA_W 32 -#define RFC_ULLRAM_BANK11492_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11492_DATA_S 0 +#define RFC_ULLRAM_BANK11492_DATA_W 32 +#define RFC_ULLRAM_BANK11492_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11492_DATA_S 0 //***************************************************************************** // @@ -24111,9 +24111,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11493_DATA_W 32 -#define RFC_ULLRAM_BANK11493_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11493_DATA_S 0 +#define RFC_ULLRAM_BANK11493_DATA_W 32 +#define RFC_ULLRAM_BANK11493_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11493_DATA_S 0 //***************************************************************************** // @@ -24123,9 +24123,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11494_DATA_W 32 -#define RFC_ULLRAM_BANK11494_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11494_DATA_S 0 +#define RFC_ULLRAM_BANK11494_DATA_W 32 +#define RFC_ULLRAM_BANK11494_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11494_DATA_S 0 //***************************************************************************** // @@ -24135,9 +24135,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11495_DATA_W 32 -#define RFC_ULLRAM_BANK11495_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11495_DATA_S 0 +#define RFC_ULLRAM_BANK11495_DATA_W 32 +#define RFC_ULLRAM_BANK11495_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11495_DATA_S 0 //***************************************************************************** // @@ -24147,9 +24147,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11496_DATA_W 32 -#define RFC_ULLRAM_BANK11496_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11496_DATA_S 0 +#define RFC_ULLRAM_BANK11496_DATA_W 32 +#define RFC_ULLRAM_BANK11496_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11496_DATA_S 0 //***************************************************************************** // @@ -24159,9 +24159,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11497_DATA_W 32 -#define RFC_ULLRAM_BANK11497_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11497_DATA_S 0 +#define RFC_ULLRAM_BANK11497_DATA_W 32 +#define RFC_ULLRAM_BANK11497_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11497_DATA_S 0 //***************************************************************************** // @@ -24171,9 +24171,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11498_DATA_W 32 -#define RFC_ULLRAM_BANK11498_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11498_DATA_S 0 +#define RFC_ULLRAM_BANK11498_DATA_W 32 +#define RFC_ULLRAM_BANK11498_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11498_DATA_S 0 //***************************************************************************** // @@ -24183,9 +24183,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11499_DATA_W 32 -#define RFC_ULLRAM_BANK11499_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11499_DATA_S 0 +#define RFC_ULLRAM_BANK11499_DATA_W 32 +#define RFC_ULLRAM_BANK11499_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11499_DATA_S 0 //***************************************************************************** // @@ -24195,9 +24195,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11500_DATA_W 32 -#define RFC_ULLRAM_BANK11500_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11500_DATA_S 0 +#define RFC_ULLRAM_BANK11500_DATA_W 32 +#define RFC_ULLRAM_BANK11500_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11500_DATA_S 0 //***************************************************************************** // @@ -24207,9 +24207,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11501_DATA_W 32 -#define RFC_ULLRAM_BANK11501_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11501_DATA_S 0 +#define RFC_ULLRAM_BANK11501_DATA_W 32 +#define RFC_ULLRAM_BANK11501_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11501_DATA_S 0 //***************************************************************************** // @@ -24219,9 +24219,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11502_DATA_W 32 -#define RFC_ULLRAM_BANK11502_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11502_DATA_S 0 +#define RFC_ULLRAM_BANK11502_DATA_W 32 +#define RFC_ULLRAM_BANK11502_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11502_DATA_S 0 //***************************************************************************** // @@ -24231,9 +24231,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11503_DATA_W 32 -#define RFC_ULLRAM_BANK11503_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11503_DATA_S 0 +#define RFC_ULLRAM_BANK11503_DATA_W 32 +#define RFC_ULLRAM_BANK11503_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11503_DATA_S 0 //***************************************************************************** // @@ -24243,9 +24243,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11504_DATA_W 32 -#define RFC_ULLRAM_BANK11504_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11504_DATA_S 0 +#define RFC_ULLRAM_BANK11504_DATA_W 32 +#define RFC_ULLRAM_BANK11504_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11504_DATA_S 0 //***************************************************************************** // @@ -24255,9 +24255,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11505_DATA_W 32 -#define RFC_ULLRAM_BANK11505_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11505_DATA_S 0 +#define RFC_ULLRAM_BANK11505_DATA_W 32 +#define RFC_ULLRAM_BANK11505_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11505_DATA_S 0 //***************************************************************************** // @@ -24267,9 +24267,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11506_DATA_W 32 -#define RFC_ULLRAM_BANK11506_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11506_DATA_S 0 +#define RFC_ULLRAM_BANK11506_DATA_W 32 +#define RFC_ULLRAM_BANK11506_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11506_DATA_S 0 //***************************************************************************** // @@ -24279,9 +24279,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11507_DATA_W 32 -#define RFC_ULLRAM_BANK11507_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11507_DATA_S 0 +#define RFC_ULLRAM_BANK11507_DATA_W 32 +#define RFC_ULLRAM_BANK11507_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11507_DATA_S 0 //***************************************************************************** // @@ -24291,9 +24291,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11508_DATA_W 32 -#define RFC_ULLRAM_BANK11508_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11508_DATA_S 0 +#define RFC_ULLRAM_BANK11508_DATA_W 32 +#define RFC_ULLRAM_BANK11508_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11508_DATA_S 0 //***************************************************************************** // @@ -24303,9 +24303,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11509_DATA_W 32 -#define RFC_ULLRAM_BANK11509_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11509_DATA_S 0 +#define RFC_ULLRAM_BANK11509_DATA_W 32 +#define RFC_ULLRAM_BANK11509_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11509_DATA_S 0 //***************************************************************************** // @@ -24315,9 +24315,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11510_DATA_W 32 -#define RFC_ULLRAM_BANK11510_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11510_DATA_S 0 +#define RFC_ULLRAM_BANK11510_DATA_W 32 +#define RFC_ULLRAM_BANK11510_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11510_DATA_S 0 //***************************************************************************** // @@ -24327,9 +24327,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11511_DATA_W 32 -#define RFC_ULLRAM_BANK11511_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11511_DATA_S 0 +#define RFC_ULLRAM_BANK11511_DATA_W 32 +#define RFC_ULLRAM_BANK11511_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11511_DATA_S 0 //***************************************************************************** // @@ -24339,9 +24339,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11512_DATA_W 32 -#define RFC_ULLRAM_BANK11512_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11512_DATA_S 0 +#define RFC_ULLRAM_BANK11512_DATA_W 32 +#define RFC_ULLRAM_BANK11512_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11512_DATA_S 0 //***************************************************************************** // @@ -24351,9 +24351,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11513_DATA_W 32 -#define RFC_ULLRAM_BANK11513_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11513_DATA_S 0 +#define RFC_ULLRAM_BANK11513_DATA_W 32 +#define RFC_ULLRAM_BANK11513_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11513_DATA_S 0 //***************************************************************************** // @@ -24363,9 +24363,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11514_DATA_W 32 -#define RFC_ULLRAM_BANK11514_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11514_DATA_S 0 +#define RFC_ULLRAM_BANK11514_DATA_W 32 +#define RFC_ULLRAM_BANK11514_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11514_DATA_S 0 //***************************************************************************** // @@ -24375,9 +24375,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11515_DATA_W 32 -#define RFC_ULLRAM_BANK11515_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11515_DATA_S 0 +#define RFC_ULLRAM_BANK11515_DATA_W 32 +#define RFC_ULLRAM_BANK11515_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11515_DATA_S 0 //***************************************************************************** // @@ -24387,9 +24387,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11516_DATA_W 32 -#define RFC_ULLRAM_BANK11516_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11516_DATA_S 0 +#define RFC_ULLRAM_BANK11516_DATA_W 32 +#define RFC_ULLRAM_BANK11516_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11516_DATA_S 0 //***************************************************************************** // @@ -24399,9 +24399,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11517_DATA_W 32 -#define RFC_ULLRAM_BANK11517_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11517_DATA_S 0 +#define RFC_ULLRAM_BANK11517_DATA_W 32 +#define RFC_ULLRAM_BANK11517_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11517_DATA_S 0 //***************************************************************************** // @@ -24411,9 +24411,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11518_DATA_W 32 -#define RFC_ULLRAM_BANK11518_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11518_DATA_S 0 +#define RFC_ULLRAM_BANK11518_DATA_W 32 +#define RFC_ULLRAM_BANK11518_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11518_DATA_S 0 //***************************************************************************** // @@ -24423,9 +24423,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11519_DATA_W 32 -#define RFC_ULLRAM_BANK11519_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11519_DATA_S 0 +#define RFC_ULLRAM_BANK11519_DATA_W 32 +#define RFC_ULLRAM_BANK11519_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11519_DATA_S 0 //***************************************************************************** // @@ -24435,9 +24435,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11520_DATA_W 32 -#define RFC_ULLRAM_BANK11520_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11520_DATA_S 0 +#define RFC_ULLRAM_BANK11520_DATA_W 32 +#define RFC_ULLRAM_BANK11520_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11520_DATA_S 0 //***************************************************************************** // @@ -24447,9 +24447,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11521_DATA_W 32 -#define RFC_ULLRAM_BANK11521_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11521_DATA_S 0 +#define RFC_ULLRAM_BANK11521_DATA_W 32 +#define RFC_ULLRAM_BANK11521_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11521_DATA_S 0 //***************************************************************************** // @@ -24459,9 +24459,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11522_DATA_W 32 -#define RFC_ULLRAM_BANK11522_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11522_DATA_S 0 +#define RFC_ULLRAM_BANK11522_DATA_W 32 +#define RFC_ULLRAM_BANK11522_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11522_DATA_S 0 //***************************************************************************** // @@ -24471,9 +24471,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11523_DATA_W 32 -#define RFC_ULLRAM_BANK11523_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11523_DATA_S 0 +#define RFC_ULLRAM_BANK11523_DATA_W 32 +#define RFC_ULLRAM_BANK11523_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11523_DATA_S 0 //***************************************************************************** // @@ -24483,9 +24483,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11524_DATA_W 32 -#define RFC_ULLRAM_BANK11524_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11524_DATA_S 0 +#define RFC_ULLRAM_BANK11524_DATA_W 32 +#define RFC_ULLRAM_BANK11524_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11524_DATA_S 0 //***************************************************************************** // @@ -24495,9 +24495,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11525_DATA_W 32 -#define RFC_ULLRAM_BANK11525_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11525_DATA_S 0 +#define RFC_ULLRAM_BANK11525_DATA_W 32 +#define RFC_ULLRAM_BANK11525_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11525_DATA_S 0 //***************************************************************************** // @@ -24507,9 +24507,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11526_DATA_W 32 -#define RFC_ULLRAM_BANK11526_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11526_DATA_S 0 +#define RFC_ULLRAM_BANK11526_DATA_W 32 +#define RFC_ULLRAM_BANK11526_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11526_DATA_S 0 //***************************************************************************** // @@ -24519,9 +24519,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11527_DATA_W 32 -#define RFC_ULLRAM_BANK11527_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11527_DATA_S 0 +#define RFC_ULLRAM_BANK11527_DATA_W 32 +#define RFC_ULLRAM_BANK11527_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11527_DATA_S 0 //***************************************************************************** // @@ -24531,9 +24531,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11528_DATA_W 32 -#define RFC_ULLRAM_BANK11528_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11528_DATA_S 0 +#define RFC_ULLRAM_BANK11528_DATA_W 32 +#define RFC_ULLRAM_BANK11528_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11528_DATA_S 0 //***************************************************************************** // @@ -24543,9 +24543,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11529_DATA_W 32 -#define RFC_ULLRAM_BANK11529_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11529_DATA_S 0 +#define RFC_ULLRAM_BANK11529_DATA_W 32 +#define RFC_ULLRAM_BANK11529_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11529_DATA_S 0 //***************************************************************************** // @@ -24555,9 +24555,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11530_DATA_W 32 -#define RFC_ULLRAM_BANK11530_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11530_DATA_S 0 +#define RFC_ULLRAM_BANK11530_DATA_W 32 +#define RFC_ULLRAM_BANK11530_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11530_DATA_S 0 //***************************************************************************** // @@ -24567,9 +24567,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11531_DATA_W 32 -#define RFC_ULLRAM_BANK11531_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11531_DATA_S 0 +#define RFC_ULLRAM_BANK11531_DATA_W 32 +#define RFC_ULLRAM_BANK11531_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11531_DATA_S 0 //***************************************************************************** // @@ -24579,9 +24579,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11532_DATA_W 32 -#define RFC_ULLRAM_BANK11532_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11532_DATA_S 0 +#define RFC_ULLRAM_BANK11532_DATA_W 32 +#define RFC_ULLRAM_BANK11532_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11532_DATA_S 0 //***************************************************************************** // @@ -24591,9 +24591,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11533_DATA_W 32 -#define RFC_ULLRAM_BANK11533_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11533_DATA_S 0 +#define RFC_ULLRAM_BANK11533_DATA_W 32 +#define RFC_ULLRAM_BANK11533_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11533_DATA_S 0 //***************************************************************************** // @@ -24603,9 +24603,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11534_DATA_W 32 -#define RFC_ULLRAM_BANK11534_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11534_DATA_S 0 +#define RFC_ULLRAM_BANK11534_DATA_W 32 +#define RFC_ULLRAM_BANK11534_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11534_DATA_S 0 //***************************************************************************** // @@ -24615,9 +24615,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11535_DATA_W 32 -#define RFC_ULLRAM_BANK11535_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11535_DATA_S 0 +#define RFC_ULLRAM_BANK11535_DATA_W 32 +#define RFC_ULLRAM_BANK11535_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11535_DATA_S 0 //***************************************************************************** // @@ -24627,9 +24627,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11536_DATA_W 32 -#define RFC_ULLRAM_BANK11536_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11536_DATA_S 0 +#define RFC_ULLRAM_BANK11536_DATA_W 32 +#define RFC_ULLRAM_BANK11536_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11536_DATA_S 0 //***************************************************************************** // @@ -24639,9 +24639,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11537_DATA_W 32 -#define RFC_ULLRAM_BANK11537_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11537_DATA_S 0 +#define RFC_ULLRAM_BANK11537_DATA_W 32 +#define RFC_ULLRAM_BANK11537_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11537_DATA_S 0 //***************************************************************************** // @@ -24651,9 +24651,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11538_DATA_W 32 -#define RFC_ULLRAM_BANK11538_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11538_DATA_S 0 +#define RFC_ULLRAM_BANK11538_DATA_W 32 +#define RFC_ULLRAM_BANK11538_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11538_DATA_S 0 //***************************************************************************** // @@ -24663,9 +24663,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11539_DATA_W 32 -#define RFC_ULLRAM_BANK11539_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11539_DATA_S 0 +#define RFC_ULLRAM_BANK11539_DATA_W 32 +#define RFC_ULLRAM_BANK11539_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11539_DATA_S 0 //***************************************************************************** // @@ -24675,9 +24675,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11540_DATA_W 32 -#define RFC_ULLRAM_BANK11540_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11540_DATA_S 0 +#define RFC_ULLRAM_BANK11540_DATA_W 32 +#define RFC_ULLRAM_BANK11540_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11540_DATA_S 0 //***************************************************************************** // @@ -24687,9 +24687,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11541_DATA_W 32 -#define RFC_ULLRAM_BANK11541_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11541_DATA_S 0 +#define RFC_ULLRAM_BANK11541_DATA_W 32 +#define RFC_ULLRAM_BANK11541_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11541_DATA_S 0 //***************************************************************************** // @@ -24699,9 +24699,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11542_DATA_W 32 -#define RFC_ULLRAM_BANK11542_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11542_DATA_S 0 +#define RFC_ULLRAM_BANK11542_DATA_W 32 +#define RFC_ULLRAM_BANK11542_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11542_DATA_S 0 //***************************************************************************** // @@ -24711,9 +24711,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11543_DATA_W 32 -#define RFC_ULLRAM_BANK11543_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11543_DATA_S 0 +#define RFC_ULLRAM_BANK11543_DATA_W 32 +#define RFC_ULLRAM_BANK11543_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11543_DATA_S 0 //***************************************************************************** // @@ -24723,9 +24723,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11544_DATA_W 32 -#define RFC_ULLRAM_BANK11544_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11544_DATA_S 0 +#define RFC_ULLRAM_BANK11544_DATA_W 32 +#define RFC_ULLRAM_BANK11544_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11544_DATA_S 0 //***************************************************************************** // @@ -24735,9 +24735,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11545_DATA_W 32 -#define RFC_ULLRAM_BANK11545_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11545_DATA_S 0 +#define RFC_ULLRAM_BANK11545_DATA_W 32 +#define RFC_ULLRAM_BANK11545_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11545_DATA_S 0 //***************************************************************************** // @@ -24747,9 +24747,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11546_DATA_W 32 -#define RFC_ULLRAM_BANK11546_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11546_DATA_S 0 +#define RFC_ULLRAM_BANK11546_DATA_W 32 +#define RFC_ULLRAM_BANK11546_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11546_DATA_S 0 //***************************************************************************** // @@ -24759,9 +24759,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11547_DATA_W 32 -#define RFC_ULLRAM_BANK11547_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11547_DATA_S 0 +#define RFC_ULLRAM_BANK11547_DATA_W 32 +#define RFC_ULLRAM_BANK11547_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11547_DATA_S 0 //***************************************************************************** // @@ -24771,9 +24771,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11548_DATA_W 32 -#define RFC_ULLRAM_BANK11548_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11548_DATA_S 0 +#define RFC_ULLRAM_BANK11548_DATA_W 32 +#define RFC_ULLRAM_BANK11548_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11548_DATA_S 0 //***************************************************************************** // @@ -24783,9 +24783,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11549_DATA_W 32 -#define RFC_ULLRAM_BANK11549_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11549_DATA_S 0 +#define RFC_ULLRAM_BANK11549_DATA_W 32 +#define RFC_ULLRAM_BANK11549_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11549_DATA_S 0 //***************************************************************************** // @@ -24795,9 +24795,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11550_DATA_W 32 -#define RFC_ULLRAM_BANK11550_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11550_DATA_S 0 +#define RFC_ULLRAM_BANK11550_DATA_W 32 +#define RFC_ULLRAM_BANK11550_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11550_DATA_S 0 //***************************************************************************** // @@ -24807,9 +24807,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11551_DATA_W 32 -#define RFC_ULLRAM_BANK11551_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11551_DATA_S 0 +#define RFC_ULLRAM_BANK11551_DATA_W 32 +#define RFC_ULLRAM_BANK11551_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11551_DATA_S 0 //***************************************************************************** // @@ -24819,9 +24819,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11552_DATA_W 32 -#define RFC_ULLRAM_BANK11552_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11552_DATA_S 0 +#define RFC_ULLRAM_BANK11552_DATA_W 32 +#define RFC_ULLRAM_BANK11552_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11552_DATA_S 0 //***************************************************************************** // @@ -24831,9 +24831,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11553_DATA_W 32 -#define RFC_ULLRAM_BANK11553_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11553_DATA_S 0 +#define RFC_ULLRAM_BANK11553_DATA_W 32 +#define RFC_ULLRAM_BANK11553_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11553_DATA_S 0 //***************************************************************************** // @@ -24843,9 +24843,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11554_DATA_W 32 -#define RFC_ULLRAM_BANK11554_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11554_DATA_S 0 +#define RFC_ULLRAM_BANK11554_DATA_W 32 +#define RFC_ULLRAM_BANK11554_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11554_DATA_S 0 //***************************************************************************** // @@ -24855,9 +24855,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11555_DATA_W 32 -#define RFC_ULLRAM_BANK11555_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11555_DATA_S 0 +#define RFC_ULLRAM_BANK11555_DATA_W 32 +#define RFC_ULLRAM_BANK11555_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11555_DATA_S 0 //***************************************************************************** // @@ -24867,9 +24867,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11556_DATA_W 32 -#define RFC_ULLRAM_BANK11556_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11556_DATA_S 0 +#define RFC_ULLRAM_BANK11556_DATA_W 32 +#define RFC_ULLRAM_BANK11556_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11556_DATA_S 0 //***************************************************************************** // @@ -24879,9 +24879,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11557_DATA_W 32 -#define RFC_ULLRAM_BANK11557_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11557_DATA_S 0 +#define RFC_ULLRAM_BANK11557_DATA_W 32 +#define RFC_ULLRAM_BANK11557_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11557_DATA_S 0 //***************************************************************************** // @@ -24891,9 +24891,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11558_DATA_W 32 -#define RFC_ULLRAM_BANK11558_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11558_DATA_S 0 +#define RFC_ULLRAM_BANK11558_DATA_W 32 +#define RFC_ULLRAM_BANK11558_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11558_DATA_S 0 //***************************************************************************** // @@ -24903,9 +24903,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11559_DATA_W 32 -#define RFC_ULLRAM_BANK11559_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11559_DATA_S 0 +#define RFC_ULLRAM_BANK11559_DATA_W 32 +#define RFC_ULLRAM_BANK11559_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11559_DATA_S 0 //***************************************************************************** // @@ -24915,9 +24915,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11560_DATA_W 32 -#define RFC_ULLRAM_BANK11560_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11560_DATA_S 0 +#define RFC_ULLRAM_BANK11560_DATA_W 32 +#define RFC_ULLRAM_BANK11560_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11560_DATA_S 0 //***************************************************************************** // @@ -24927,9 +24927,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11561_DATA_W 32 -#define RFC_ULLRAM_BANK11561_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11561_DATA_S 0 +#define RFC_ULLRAM_BANK11561_DATA_W 32 +#define RFC_ULLRAM_BANK11561_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11561_DATA_S 0 //***************************************************************************** // @@ -24939,9 +24939,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11562_DATA_W 32 -#define RFC_ULLRAM_BANK11562_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11562_DATA_S 0 +#define RFC_ULLRAM_BANK11562_DATA_W 32 +#define RFC_ULLRAM_BANK11562_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11562_DATA_S 0 //***************************************************************************** // @@ -24951,9 +24951,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11563_DATA_W 32 -#define RFC_ULLRAM_BANK11563_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11563_DATA_S 0 +#define RFC_ULLRAM_BANK11563_DATA_W 32 +#define RFC_ULLRAM_BANK11563_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11563_DATA_S 0 //***************************************************************************** // @@ -24963,9 +24963,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11564_DATA_W 32 -#define RFC_ULLRAM_BANK11564_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11564_DATA_S 0 +#define RFC_ULLRAM_BANK11564_DATA_W 32 +#define RFC_ULLRAM_BANK11564_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11564_DATA_S 0 //***************************************************************************** // @@ -24975,9 +24975,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11565_DATA_W 32 -#define RFC_ULLRAM_BANK11565_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11565_DATA_S 0 +#define RFC_ULLRAM_BANK11565_DATA_W 32 +#define RFC_ULLRAM_BANK11565_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11565_DATA_S 0 //***************************************************************************** // @@ -24987,9 +24987,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11566_DATA_W 32 -#define RFC_ULLRAM_BANK11566_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11566_DATA_S 0 +#define RFC_ULLRAM_BANK11566_DATA_W 32 +#define RFC_ULLRAM_BANK11566_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11566_DATA_S 0 //***************************************************************************** // @@ -24999,9 +24999,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11567_DATA_W 32 -#define RFC_ULLRAM_BANK11567_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11567_DATA_S 0 +#define RFC_ULLRAM_BANK11567_DATA_W 32 +#define RFC_ULLRAM_BANK11567_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11567_DATA_S 0 //***************************************************************************** // @@ -25011,9 +25011,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11568_DATA_W 32 -#define RFC_ULLRAM_BANK11568_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11568_DATA_S 0 +#define RFC_ULLRAM_BANK11568_DATA_W 32 +#define RFC_ULLRAM_BANK11568_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11568_DATA_S 0 //***************************************************************************** // @@ -25023,9 +25023,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11569_DATA_W 32 -#define RFC_ULLRAM_BANK11569_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11569_DATA_S 0 +#define RFC_ULLRAM_BANK11569_DATA_W 32 +#define RFC_ULLRAM_BANK11569_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11569_DATA_S 0 //***************************************************************************** // @@ -25035,9 +25035,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11570_DATA_W 32 -#define RFC_ULLRAM_BANK11570_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11570_DATA_S 0 +#define RFC_ULLRAM_BANK11570_DATA_W 32 +#define RFC_ULLRAM_BANK11570_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11570_DATA_S 0 //***************************************************************************** // @@ -25047,9 +25047,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11571_DATA_W 32 -#define RFC_ULLRAM_BANK11571_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11571_DATA_S 0 +#define RFC_ULLRAM_BANK11571_DATA_W 32 +#define RFC_ULLRAM_BANK11571_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11571_DATA_S 0 //***************************************************************************** // @@ -25059,9 +25059,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11572_DATA_W 32 -#define RFC_ULLRAM_BANK11572_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11572_DATA_S 0 +#define RFC_ULLRAM_BANK11572_DATA_W 32 +#define RFC_ULLRAM_BANK11572_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11572_DATA_S 0 //***************************************************************************** // @@ -25071,9 +25071,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11573_DATA_W 32 -#define RFC_ULLRAM_BANK11573_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11573_DATA_S 0 +#define RFC_ULLRAM_BANK11573_DATA_W 32 +#define RFC_ULLRAM_BANK11573_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11573_DATA_S 0 //***************************************************************************** // @@ -25083,9 +25083,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11574_DATA_W 32 -#define RFC_ULLRAM_BANK11574_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11574_DATA_S 0 +#define RFC_ULLRAM_BANK11574_DATA_W 32 +#define RFC_ULLRAM_BANK11574_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11574_DATA_S 0 //***************************************************************************** // @@ -25095,9 +25095,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11575_DATA_W 32 -#define RFC_ULLRAM_BANK11575_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11575_DATA_S 0 +#define RFC_ULLRAM_BANK11575_DATA_W 32 +#define RFC_ULLRAM_BANK11575_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11575_DATA_S 0 //***************************************************************************** // @@ -25107,9 +25107,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11576_DATA_W 32 -#define RFC_ULLRAM_BANK11576_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11576_DATA_S 0 +#define RFC_ULLRAM_BANK11576_DATA_W 32 +#define RFC_ULLRAM_BANK11576_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11576_DATA_S 0 //***************************************************************************** // @@ -25119,9 +25119,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11577_DATA_W 32 -#define RFC_ULLRAM_BANK11577_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11577_DATA_S 0 +#define RFC_ULLRAM_BANK11577_DATA_W 32 +#define RFC_ULLRAM_BANK11577_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11577_DATA_S 0 //***************************************************************************** // @@ -25131,9 +25131,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11578_DATA_W 32 -#define RFC_ULLRAM_BANK11578_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11578_DATA_S 0 +#define RFC_ULLRAM_BANK11578_DATA_W 32 +#define RFC_ULLRAM_BANK11578_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11578_DATA_S 0 //***************************************************************************** // @@ -25143,9 +25143,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11579_DATA_W 32 -#define RFC_ULLRAM_BANK11579_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11579_DATA_S 0 +#define RFC_ULLRAM_BANK11579_DATA_W 32 +#define RFC_ULLRAM_BANK11579_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11579_DATA_S 0 //***************************************************************************** // @@ -25155,9 +25155,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11580_DATA_W 32 -#define RFC_ULLRAM_BANK11580_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11580_DATA_S 0 +#define RFC_ULLRAM_BANK11580_DATA_W 32 +#define RFC_ULLRAM_BANK11580_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11580_DATA_S 0 //***************************************************************************** // @@ -25167,9 +25167,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11581_DATA_W 32 -#define RFC_ULLRAM_BANK11581_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11581_DATA_S 0 +#define RFC_ULLRAM_BANK11581_DATA_W 32 +#define RFC_ULLRAM_BANK11581_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11581_DATA_S 0 //***************************************************************************** // @@ -25179,9 +25179,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11582_DATA_W 32 -#define RFC_ULLRAM_BANK11582_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11582_DATA_S 0 +#define RFC_ULLRAM_BANK11582_DATA_W 32 +#define RFC_ULLRAM_BANK11582_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11582_DATA_S 0 //***************************************************************************** // @@ -25191,9 +25191,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11583_DATA_W 32 -#define RFC_ULLRAM_BANK11583_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11583_DATA_S 0 +#define RFC_ULLRAM_BANK11583_DATA_W 32 +#define RFC_ULLRAM_BANK11583_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11583_DATA_S 0 //***************************************************************************** // @@ -25203,9 +25203,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11584_DATA_W 32 -#define RFC_ULLRAM_BANK11584_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11584_DATA_S 0 +#define RFC_ULLRAM_BANK11584_DATA_W 32 +#define RFC_ULLRAM_BANK11584_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11584_DATA_S 0 //***************************************************************************** // @@ -25215,9 +25215,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11585_DATA_W 32 -#define RFC_ULLRAM_BANK11585_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11585_DATA_S 0 +#define RFC_ULLRAM_BANK11585_DATA_W 32 +#define RFC_ULLRAM_BANK11585_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11585_DATA_S 0 //***************************************************************************** // @@ -25227,9 +25227,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11586_DATA_W 32 -#define RFC_ULLRAM_BANK11586_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11586_DATA_S 0 +#define RFC_ULLRAM_BANK11586_DATA_W 32 +#define RFC_ULLRAM_BANK11586_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11586_DATA_S 0 //***************************************************************************** // @@ -25239,9 +25239,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11587_DATA_W 32 -#define RFC_ULLRAM_BANK11587_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11587_DATA_S 0 +#define RFC_ULLRAM_BANK11587_DATA_W 32 +#define RFC_ULLRAM_BANK11587_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11587_DATA_S 0 //***************************************************************************** // @@ -25251,9 +25251,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11588_DATA_W 32 -#define RFC_ULLRAM_BANK11588_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11588_DATA_S 0 +#define RFC_ULLRAM_BANK11588_DATA_W 32 +#define RFC_ULLRAM_BANK11588_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11588_DATA_S 0 //***************************************************************************** // @@ -25263,9 +25263,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11589_DATA_W 32 -#define RFC_ULLRAM_BANK11589_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11589_DATA_S 0 +#define RFC_ULLRAM_BANK11589_DATA_W 32 +#define RFC_ULLRAM_BANK11589_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11589_DATA_S 0 //***************************************************************************** // @@ -25275,9 +25275,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11590_DATA_W 32 -#define RFC_ULLRAM_BANK11590_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11590_DATA_S 0 +#define RFC_ULLRAM_BANK11590_DATA_W 32 +#define RFC_ULLRAM_BANK11590_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11590_DATA_S 0 //***************************************************************************** // @@ -25287,9 +25287,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11591_DATA_W 32 -#define RFC_ULLRAM_BANK11591_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11591_DATA_S 0 +#define RFC_ULLRAM_BANK11591_DATA_W 32 +#define RFC_ULLRAM_BANK11591_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11591_DATA_S 0 //***************************************************************************** // @@ -25299,9 +25299,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11592_DATA_W 32 -#define RFC_ULLRAM_BANK11592_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11592_DATA_S 0 +#define RFC_ULLRAM_BANK11592_DATA_W 32 +#define RFC_ULLRAM_BANK11592_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11592_DATA_S 0 //***************************************************************************** // @@ -25311,9 +25311,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11593_DATA_W 32 -#define RFC_ULLRAM_BANK11593_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11593_DATA_S 0 +#define RFC_ULLRAM_BANK11593_DATA_W 32 +#define RFC_ULLRAM_BANK11593_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11593_DATA_S 0 //***************************************************************************** // @@ -25323,9 +25323,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11594_DATA_W 32 -#define RFC_ULLRAM_BANK11594_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11594_DATA_S 0 +#define RFC_ULLRAM_BANK11594_DATA_W 32 +#define RFC_ULLRAM_BANK11594_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11594_DATA_S 0 //***************************************************************************** // @@ -25335,9 +25335,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11595_DATA_W 32 -#define RFC_ULLRAM_BANK11595_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11595_DATA_S 0 +#define RFC_ULLRAM_BANK11595_DATA_W 32 +#define RFC_ULLRAM_BANK11595_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11595_DATA_S 0 //***************************************************************************** // @@ -25347,9 +25347,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11596_DATA_W 32 -#define RFC_ULLRAM_BANK11596_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11596_DATA_S 0 +#define RFC_ULLRAM_BANK11596_DATA_W 32 +#define RFC_ULLRAM_BANK11596_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11596_DATA_S 0 //***************************************************************************** // @@ -25359,9 +25359,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11597_DATA_W 32 -#define RFC_ULLRAM_BANK11597_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11597_DATA_S 0 +#define RFC_ULLRAM_BANK11597_DATA_W 32 +#define RFC_ULLRAM_BANK11597_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11597_DATA_S 0 //***************************************************************************** // @@ -25371,9 +25371,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11598_DATA_W 32 -#define RFC_ULLRAM_BANK11598_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11598_DATA_S 0 +#define RFC_ULLRAM_BANK11598_DATA_W 32 +#define RFC_ULLRAM_BANK11598_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11598_DATA_S 0 //***************************************************************************** // @@ -25383,9 +25383,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11599_DATA_W 32 -#define RFC_ULLRAM_BANK11599_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11599_DATA_S 0 +#define RFC_ULLRAM_BANK11599_DATA_W 32 +#define RFC_ULLRAM_BANK11599_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11599_DATA_S 0 //***************************************************************************** // @@ -25395,9 +25395,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11600_DATA_W 32 -#define RFC_ULLRAM_BANK11600_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11600_DATA_S 0 +#define RFC_ULLRAM_BANK11600_DATA_W 32 +#define RFC_ULLRAM_BANK11600_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11600_DATA_S 0 //***************************************************************************** // @@ -25407,9 +25407,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11601_DATA_W 32 -#define RFC_ULLRAM_BANK11601_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11601_DATA_S 0 +#define RFC_ULLRAM_BANK11601_DATA_W 32 +#define RFC_ULLRAM_BANK11601_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11601_DATA_S 0 //***************************************************************************** // @@ -25419,9 +25419,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11602_DATA_W 32 -#define RFC_ULLRAM_BANK11602_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11602_DATA_S 0 +#define RFC_ULLRAM_BANK11602_DATA_W 32 +#define RFC_ULLRAM_BANK11602_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11602_DATA_S 0 //***************************************************************************** // @@ -25431,9 +25431,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11603_DATA_W 32 -#define RFC_ULLRAM_BANK11603_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11603_DATA_S 0 +#define RFC_ULLRAM_BANK11603_DATA_W 32 +#define RFC_ULLRAM_BANK11603_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11603_DATA_S 0 //***************************************************************************** // @@ -25443,9 +25443,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11604_DATA_W 32 -#define RFC_ULLRAM_BANK11604_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11604_DATA_S 0 +#define RFC_ULLRAM_BANK11604_DATA_W 32 +#define RFC_ULLRAM_BANK11604_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11604_DATA_S 0 //***************************************************************************** // @@ -25455,9 +25455,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11605_DATA_W 32 -#define RFC_ULLRAM_BANK11605_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11605_DATA_S 0 +#define RFC_ULLRAM_BANK11605_DATA_W 32 +#define RFC_ULLRAM_BANK11605_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11605_DATA_S 0 //***************************************************************************** // @@ -25467,9 +25467,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11606_DATA_W 32 -#define RFC_ULLRAM_BANK11606_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11606_DATA_S 0 +#define RFC_ULLRAM_BANK11606_DATA_W 32 +#define RFC_ULLRAM_BANK11606_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11606_DATA_S 0 //***************************************************************************** // @@ -25479,9 +25479,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11607_DATA_W 32 -#define RFC_ULLRAM_BANK11607_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11607_DATA_S 0 +#define RFC_ULLRAM_BANK11607_DATA_W 32 +#define RFC_ULLRAM_BANK11607_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11607_DATA_S 0 //***************************************************************************** // @@ -25491,9 +25491,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11608_DATA_W 32 -#define RFC_ULLRAM_BANK11608_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11608_DATA_S 0 +#define RFC_ULLRAM_BANK11608_DATA_W 32 +#define RFC_ULLRAM_BANK11608_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11608_DATA_S 0 //***************************************************************************** // @@ -25503,9 +25503,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11609_DATA_W 32 -#define RFC_ULLRAM_BANK11609_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11609_DATA_S 0 +#define RFC_ULLRAM_BANK11609_DATA_W 32 +#define RFC_ULLRAM_BANK11609_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11609_DATA_S 0 //***************************************************************************** // @@ -25515,9 +25515,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11610_DATA_W 32 -#define RFC_ULLRAM_BANK11610_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11610_DATA_S 0 +#define RFC_ULLRAM_BANK11610_DATA_W 32 +#define RFC_ULLRAM_BANK11610_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11610_DATA_S 0 //***************************************************************************** // @@ -25527,9 +25527,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11611_DATA_W 32 -#define RFC_ULLRAM_BANK11611_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11611_DATA_S 0 +#define RFC_ULLRAM_BANK11611_DATA_W 32 +#define RFC_ULLRAM_BANK11611_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11611_DATA_S 0 //***************************************************************************** // @@ -25539,9 +25539,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11612_DATA_W 32 -#define RFC_ULLRAM_BANK11612_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11612_DATA_S 0 +#define RFC_ULLRAM_BANK11612_DATA_W 32 +#define RFC_ULLRAM_BANK11612_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11612_DATA_S 0 //***************************************************************************** // @@ -25551,9 +25551,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11613_DATA_W 32 -#define RFC_ULLRAM_BANK11613_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11613_DATA_S 0 +#define RFC_ULLRAM_BANK11613_DATA_W 32 +#define RFC_ULLRAM_BANK11613_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11613_DATA_S 0 //***************************************************************************** // @@ -25563,9 +25563,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11614_DATA_W 32 -#define RFC_ULLRAM_BANK11614_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11614_DATA_S 0 +#define RFC_ULLRAM_BANK11614_DATA_W 32 +#define RFC_ULLRAM_BANK11614_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11614_DATA_S 0 //***************************************************************************** // @@ -25575,9 +25575,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11615_DATA_W 32 -#define RFC_ULLRAM_BANK11615_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11615_DATA_S 0 +#define RFC_ULLRAM_BANK11615_DATA_W 32 +#define RFC_ULLRAM_BANK11615_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11615_DATA_S 0 //***************************************************************************** // @@ -25587,9 +25587,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11616_DATA_W 32 -#define RFC_ULLRAM_BANK11616_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11616_DATA_S 0 +#define RFC_ULLRAM_BANK11616_DATA_W 32 +#define RFC_ULLRAM_BANK11616_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11616_DATA_S 0 //***************************************************************************** // @@ -25599,9 +25599,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11617_DATA_W 32 -#define RFC_ULLRAM_BANK11617_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11617_DATA_S 0 +#define RFC_ULLRAM_BANK11617_DATA_W 32 +#define RFC_ULLRAM_BANK11617_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11617_DATA_S 0 //***************************************************************************** // @@ -25611,9 +25611,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11618_DATA_W 32 -#define RFC_ULLRAM_BANK11618_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11618_DATA_S 0 +#define RFC_ULLRAM_BANK11618_DATA_W 32 +#define RFC_ULLRAM_BANK11618_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11618_DATA_S 0 //***************************************************************************** // @@ -25623,9 +25623,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11619_DATA_W 32 -#define RFC_ULLRAM_BANK11619_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11619_DATA_S 0 +#define RFC_ULLRAM_BANK11619_DATA_W 32 +#define RFC_ULLRAM_BANK11619_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11619_DATA_S 0 //***************************************************************************** // @@ -25635,9 +25635,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11620_DATA_W 32 -#define RFC_ULLRAM_BANK11620_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11620_DATA_S 0 +#define RFC_ULLRAM_BANK11620_DATA_W 32 +#define RFC_ULLRAM_BANK11620_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11620_DATA_S 0 //***************************************************************************** // @@ -25647,9 +25647,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11621_DATA_W 32 -#define RFC_ULLRAM_BANK11621_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11621_DATA_S 0 +#define RFC_ULLRAM_BANK11621_DATA_W 32 +#define RFC_ULLRAM_BANK11621_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11621_DATA_S 0 //***************************************************************************** // @@ -25659,9 +25659,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11622_DATA_W 32 -#define RFC_ULLRAM_BANK11622_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11622_DATA_S 0 +#define RFC_ULLRAM_BANK11622_DATA_W 32 +#define RFC_ULLRAM_BANK11622_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11622_DATA_S 0 //***************************************************************************** // @@ -25671,9 +25671,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11623_DATA_W 32 -#define RFC_ULLRAM_BANK11623_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11623_DATA_S 0 +#define RFC_ULLRAM_BANK11623_DATA_W 32 +#define RFC_ULLRAM_BANK11623_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11623_DATA_S 0 //***************************************************************************** // @@ -25683,9 +25683,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11624_DATA_W 32 -#define RFC_ULLRAM_BANK11624_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11624_DATA_S 0 +#define RFC_ULLRAM_BANK11624_DATA_W 32 +#define RFC_ULLRAM_BANK11624_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11624_DATA_S 0 //***************************************************************************** // @@ -25695,9 +25695,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11625_DATA_W 32 -#define RFC_ULLRAM_BANK11625_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11625_DATA_S 0 +#define RFC_ULLRAM_BANK11625_DATA_W 32 +#define RFC_ULLRAM_BANK11625_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11625_DATA_S 0 //***************************************************************************** // @@ -25707,9 +25707,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11626_DATA_W 32 -#define RFC_ULLRAM_BANK11626_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11626_DATA_S 0 +#define RFC_ULLRAM_BANK11626_DATA_W 32 +#define RFC_ULLRAM_BANK11626_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11626_DATA_S 0 //***************************************************************************** // @@ -25719,9 +25719,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11627_DATA_W 32 -#define RFC_ULLRAM_BANK11627_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11627_DATA_S 0 +#define RFC_ULLRAM_BANK11627_DATA_W 32 +#define RFC_ULLRAM_BANK11627_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11627_DATA_S 0 //***************************************************************************** // @@ -25731,9 +25731,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11628_DATA_W 32 -#define RFC_ULLRAM_BANK11628_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11628_DATA_S 0 +#define RFC_ULLRAM_BANK11628_DATA_W 32 +#define RFC_ULLRAM_BANK11628_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11628_DATA_S 0 //***************************************************************************** // @@ -25743,9 +25743,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11629_DATA_W 32 -#define RFC_ULLRAM_BANK11629_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11629_DATA_S 0 +#define RFC_ULLRAM_BANK11629_DATA_W 32 +#define RFC_ULLRAM_BANK11629_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11629_DATA_S 0 //***************************************************************************** // @@ -25755,9 +25755,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11630_DATA_W 32 -#define RFC_ULLRAM_BANK11630_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11630_DATA_S 0 +#define RFC_ULLRAM_BANK11630_DATA_W 32 +#define RFC_ULLRAM_BANK11630_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11630_DATA_S 0 //***************************************************************************** // @@ -25767,9 +25767,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11631_DATA_W 32 -#define RFC_ULLRAM_BANK11631_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11631_DATA_S 0 +#define RFC_ULLRAM_BANK11631_DATA_W 32 +#define RFC_ULLRAM_BANK11631_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11631_DATA_S 0 //***************************************************************************** // @@ -25779,9 +25779,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11632_DATA_W 32 -#define RFC_ULLRAM_BANK11632_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11632_DATA_S 0 +#define RFC_ULLRAM_BANK11632_DATA_W 32 +#define RFC_ULLRAM_BANK11632_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11632_DATA_S 0 //***************************************************************************** // @@ -25791,9 +25791,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11633_DATA_W 32 -#define RFC_ULLRAM_BANK11633_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11633_DATA_S 0 +#define RFC_ULLRAM_BANK11633_DATA_W 32 +#define RFC_ULLRAM_BANK11633_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11633_DATA_S 0 //***************************************************************************** // @@ -25803,9 +25803,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11634_DATA_W 32 -#define RFC_ULLRAM_BANK11634_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11634_DATA_S 0 +#define RFC_ULLRAM_BANK11634_DATA_W 32 +#define RFC_ULLRAM_BANK11634_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11634_DATA_S 0 //***************************************************************************** // @@ -25815,9 +25815,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11635_DATA_W 32 -#define RFC_ULLRAM_BANK11635_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11635_DATA_S 0 +#define RFC_ULLRAM_BANK11635_DATA_W 32 +#define RFC_ULLRAM_BANK11635_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11635_DATA_S 0 //***************************************************************************** // @@ -25827,9 +25827,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11636_DATA_W 32 -#define RFC_ULLRAM_BANK11636_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11636_DATA_S 0 +#define RFC_ULLRAM_BANK11636_DATA_W 32 +#define RFC_ULLRAM_BANK11636_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11636_DATA_S 0 //***************************************************************************** // @@ -25839,9 +25839,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11637_DATA_W 32 -#define RFC_ULLRAM_BANK11637_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11637_DATA_S 0 +#define RFC_ULLRAM_BANK11637_DATA_W 32 +#define RFC_ULLRAM_BANK11637_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11637_DATA_S 0 //***************************************************************************** // @@ -25851,9 +25851,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11638_DATA_W 32 -#define RFC_ULLRAM_BANK11638_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11638_DATA_S 0 +#define RFC_ULLRAM_BANK11638_DATA_W 32 +#define RFC_ULLRAM_BANK11638_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11638_DATA_S 0 //***************************************************************************** // @@ -25863,9 +25863,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11639_DATA_W 32 -#define RFC_ULLRAM_BANK11639_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11639_DATA_S 0 +#define RFC_ULLRAM_BANK11639_DATA_W 32 +#define RFC_ULLRAM_BANK11639_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11639_DATA_S 0 //***************************************************************************** // @@ -25875,9 +25875,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11640_DATA_W 32 -#define RFC_ULLRAM_BANK11640_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11640_DATA_S 0 +#define RFC_ULLRAM_BANK11640_DATA_W 32 +#define RFC_ULLRAM_BANK11640_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11640_DATA_S 0 //***************************************************************************** // @@ -25887,9 +25887,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11641_DATA_W 32 -#define RFC_ULLRAM_BANK11641_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11641_DATA_S 0 +#define RFC_ULLRAM_BANK11641_DATA_W 32 +#define RFC_ULLRAM_BANK11641_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11641_DATA_S 0 //***************************************************************************** // @@ -25899,9 +25899,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11642_DATA_W 32 -#define RFC_ULLRAM_BANK11642_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11642_DATA_S 0 +#define RFC_ULLRAM_BANK11642_DATA_W 32 +#define RFC_ULLRAM_BANK11642_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11642_DATA_S 0 //***************************************************************************** // @@ -25911,9 +25911,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11643_DATA_W 32 -#define RFC_ULLRAM_BANK11643_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11643_DATA_S 0 +#define RFC_ULLRAM_BANK11643_DATA_W 32 +#define RFC_ULLRAM_BANK11643_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11643_DATA_S 0 //***************************************************************************** // @@ -25923,9 +25923,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11644_DATA_W 32 -#define RFC_ULLRAM_BANK11644_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11644_DATA_S 0 +#define RFC_ULLRAM_BANK11644_DATA_W 32 +#define RFC_ULLRAM_BANK11644_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11644_DATA_S 0 //***************************************************************************** // @@ -25935,9 +25935,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11645_DATA_W 32 -#define RFC_ULLRAM_BANK11645_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11645_DATA_S 0 +#define RFC_ULLRAM_BANK11645_DATA_W 32 +#define RFC_ULLRAM_BANK11645_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11645_DATA_S 0 //***************************************************************************** // @@ -25947,9 +25947,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11646_DATA_W 32 -#define RFC_ULLRAM_BANK11646_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11646_DATA_S 0 +#define RFC_ULLRAM_BANK11646_DATA_W 32 +#define RFC_ULLRAM_BANK11646_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11646_DATA_S 0 //***************************************************************************** // @@ -25959,9 +25959,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11647_DATA_W 32 -#define RFC_ULLRAM_BANK11647_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11647_DATA_S 0 +#define RFC_ULLRAM_BANK11647_DATA_W 32 +#define RFC_ULLRAM_BANK11647_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11647_DATA_S 0 //***************************************************************************** // @@ -25971,9 +25971,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11648_DATA_W 32 -#define RFC_ULLRAM_BANK11648_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11648_DATA_S 0 +#define RFC_ULLRAM_BANK11648_DATA_W 32 +#define RFC_ULLRAM_BANK11648_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11648_DATA_S 0 //***************************************************************************** // @@ -25983,9 +25983,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11649_DATA_W 32 -#define RFC_ULLRAM_BANK11649_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11649_DATA_S 0 +#define RFC_ULLRAM_BANK11649_DATA_W 32 +#define RFC_ULLRAM_BANK11649_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11649_DATA_S 0 //***************************************************************************** // @@ -25995,9 +25995,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11650_DATA_W 32 -#define RFC_ULLRAM_BANK11650_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11650_DATA_S 0 +#define RFC_ULLRAM_BANK11650_DATA_W 32 +#define RFC_ULLRAM_BANK11650_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11650_DATA_S 0 //***************************************************************************** // @@ -26007,9 +26007,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11651_DATA_W 32 -#define RFC_ULLRAM_BANK11651_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11651_DATA_S 0 +#define RFC_ULLRAM_BANK11651_DATA_W 32 +#define RFC_ULLRAM_BANK11651_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11651_DATA_S 0 //***************************************************************************** // @@ -26019,9 +26019,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11652_DATA_W 32 -#define RFC_ULLRAM_BANK11652_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11652_DATA_S 0 +#define RFC_ULLRAM_BANK11652_DATA_W 32 +#define RFC_ULLRAM_BANK11652_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11652_DATA_S 0 //***************************************************************************** // @@ -26031,9 +26031,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11653_DATA_W 32 -#define RFC_ULLRAM_BANK11653_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11653_DATA_S 0 +#define RFC_ULLRAM_BANK11653_DATA_W 32 +#define RFC_ULLRAM_BANK11653_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11653_DATA_S 0 //***************************************************************************** // @@ -26043,9 +26043,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11654_DATA_W 32 -#define RFC_ULLRAM_BANK11654_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11654_DATA_S 0 +#define RFC_ULLRAM_BANK11654_DATA_W 32 +#define RFC_ULLRAM_BANK11654_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11654_DATA_S 0 //***************************************************************************** // @@ -26055,9 +26055,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11655_DATA_W 32 -#define RFC_ULLRAM_BANK11655_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11655_DATA_S 0 +#define RFC_ULLRAM_BANK11655_DATA_W 32 +#define RFC_ULLRAM_BANK11655_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11655_DATA_S 0 //***************************************************************************** // @@ -26067,9 +26067,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11656_DATA_W 32 -#define RFC_ULLRAM_BANK11656_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11656_DATA_S 0 +#define RFC_ULLRAM_BANK11656_DATA_W 32 +#define RFC_ULLRAM_BANK11656_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11656_DATA_S 0 //***************************************************************************** // @@ -26079,9 +26079,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11657_DATA_W 32 -#define RFC_ULLRAM_BANK11657_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11657_DATA_S 0 +#define RFC_ULLRAM_BANK11657_DATA_W 32 +#define RFC_ULLRAM_BANK11657_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11657_DATA_S 0 //***************************************************************************** // @@ -26091,9 +26091,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11658_DATA_W 32 -#define RFC_ULLRAM_BANK11658_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11658_DATA_S 0 +#define RFC_ULLRAM_BANK11658_DATA_W 32 +#define RFC_ULLRAM_BANK11658_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11658_DATA_S 0 //***************************************************************************** // @@ -26103,9 +26103,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11659_DATA_W 32 -#define RFC_ULLRAM_BANK11659_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11659_DATA_S 0 +#define RFC_ULLRAM_BANK11659_DATA_W 32 +#define RFC_ULLRAM_BANK11659_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11659_DATA_S 0 //***************************************************************************** // @@ -26115,9 +26115,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11660_DATA_W 32 -#define RFC_ULLRAM_BANK11660_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11660_DATA_S 0 +#define RFC_ULLRAM_BANK11660_DATA_W 32 +#define RFC_ULLRAM_BANK11660_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11660_DATA_S 0 //***************************************************************************** // @@ -26127,9 +26127,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11661_DATA_W 32 -#define RFC_ULLRAM_BANK11661_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11661_DATA_S 0 +#define RFC_ULLRAM_BANK11661_DATA_W 32 +#define RFC_ULLRAM_BANK11661_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11661_DATA_S 0 //***************************************************************************** // @@ -26139,9 +26139,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11662_DATA_W 32 -#define RFC_ULLRAM_BANK11662_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11662_DATA_S 0 +#define RFC_ULLRAM_BANK11662_DATA_W 32 +#define RFC_ULLRAM_BANK11662_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11662_DATA_S 0 //***************************************************************************** // @@ -26151,9 +26151,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11663_DATA_W 32 -#define RFC_ULLRAM_BANK11663_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11663_DATA_S 0 +#define RFC_ULLRAM_BANK11663_DATA_W 32 +#define RFC_ULLRAM_BANK11663_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11663_DATA_S 0 //***************************************************************************** // @@ -26163,9 +26163,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11664_DATA_W 32 -#define RFC_ULLRAM_BANK11664_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11664_DATA_S 0 +#define RFC_ULLRAM_BANK11664_DATA_W 32 +#define RFC_ULLRAM_BANK11664_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11664_DATA_S 0 //***************************************************************************** // @@ -26175,9 +26175,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11665_DATA_W 32 -#define RFC_ULLRAM_BANK11665_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11665_DATA_S 0 +#define RFC_ULLRAM_BANK11665_DATA_W 32 +#define RFC_ULLRAM_BANK11665_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11665_DATA_S 0 //***************************************************************************** // @@ -26187,9 +26187,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11666_DATA_W 32 -#define RFC_ULLRAM_BANK11666_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11666_DATA_S 0 +#define RFC_ULLRAM_BANK11666_DATA_W 32 +#define RFC_ULLRAM_BANK11666_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11666_DATA_S 0 //***************************************************************************** // @@ -26199,9 +26199,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11667_DATA_W 32 -#define RFC_ULLRAM_BANK11667_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11667_DATA_S 0 +#define RFC_ULLRAM_BANK11667_DATA_W 32 +#define RFC_ULLRAM_BANK11667_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11667_DATA_S 0 //***************************************************************************** // @@ -26211,9 +26211,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11668_DATA_W 32 -#define RFC_ULLRAM_BANK11668_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11668_DATA_S 0 +#define RFC_ULLRAM_BANK11668_DATA_W 32 +#define RFC_ULLRAM_BANK11668_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11668_DATA_S 0 //***************************************************************************** // @@ -26223,9 +26223,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11669_DATA_W 32 -#define RFC_ULLRAM_BANK11669_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11669_DATA_S 0 +#define RFC_ULLRAM_BANK11669_DATA_W 32 +#define RFC_ULLRAM_BANK11669_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11669_DATA_S 0 //***************************************************************************** // @@ -26235,9 +26235,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11670_DATA_W 32 -#define RFC_ULLRAM_BANK11670_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11670_DATA_S 0 +#define RFC_ULLRAM_BANK11670_DATA_W 32 +#define RFC_ULLRAM_BANK11670_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11670_DATA_S 0 //***************************************************************************** // @@ -26247,9 +26247,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11671_DATA_W 32 -#define RFC_ULLRAM_BANK11671_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11671_DATA_S 0 +#define RFC_ULLRAM_BANK11671_DATA_W 32 +#define RFC_ULLRAM_BANK11671_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11671_DATA_S 0 //***************************************************************************** // @@ -26259,9 +26259,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11672_DATA_W 32 -#define RFC_ULLRAM_BANK11672_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11672_DATA_S 0 +#define RFC_ULLRAM_BANK11672_DATA_W 32 +#define RFC_ULLRAM_BANK11672_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11672_DATA_S 0 //***************************************************************************** // @@ -26271,9 +26271,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11673_DATA_W 32 -#define RFC_ULLRAM_BANK11673_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11673_DATA_S 0 +#define RFC_ULLRAM_BANK11673_DATA_W 32 +#define RFC_ULLRAM_BANK11673_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11673_DATA_S 0 //***************************************************************************** // @@ -26283,9 +26283,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11674_DATA_W 32 -#define RFC_ULLRAM_BANK11674_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11674_DATA_S 0 +#define RFC_ULLRAM_BANK11674_DATA_W 32 +#define RFC_ULLRAM_BANK11674_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11674_DATA_S 0 //***************************************************************************** // @@ -26295,9 +26295,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11675_DATA_W 32 -#define RFC_ULLRAM_BANK11675_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11675_DATA_S 0 +#define RFC_ULLRAM_BANK11675_DATA_W 32 +#define RFC_ULLRAM_BANK11675_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11675_DATA_S 0 //***************************************************************************** // @@ -26307,9 +26307,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11676_DATA_W 32 -#define RFC_ULLRAM_BANK11676_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11676_DATA_S 0 +#define RFC_ULLRAM_BANK11676_DATA_W 32 +#define RFC_ULLRAM_BANK11676_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11676_DATA_S 0 //***************************************************************************** // @@ -26319,9 +26319,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11677_DATA_W 32 -#define RFC_ULLRAM_BANK11677_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11677_DATA_S 0 +#define RFC_ULLRAM_BANK11677_DATA_W 32 +#define RFC_ULLRAM_BANK11677_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11677_DATA_S 0 //***************************************************************************** // @@ -26331,9 +26331,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11678_DATA_W 32 -#define RFC_ULLRAM_BANK11678_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11678_DATA_S 0 +#define RFC_ULLRAM_BANK11678_DATA_W 32 +#define RFC_ULLRAM_BANK11678_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11678_DATA_S 0 //***************************************************************************** // @@ -26343,9 +26343,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11679_DATA_W 32 -#define RFC_ULLRAM_BANK11679_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11679_DATA_S 0 +#define RFC_ULLRAM_BANK11679_DATA_W 32 +#define RFC_ULLRAM_BANK11679_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11679_DATA_S 0 //***************************************************************************** // @@ -26355,9 +26355,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11680_DATA_W 32 -#define RFC_ULLRAM_BANK11680_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11680_DATA_S 0 +#define RFC_ULLRAM_BANK11680_DATA_W 32 +#define RFC_ULLRAM_BANK11680_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11680_DATA_S 0 //***************************************************************************** // @@ -26367,9 +26367,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11681_DATA_W 32 -#define RFC_ULLRAM_BANK11681_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11681_DATA_S 0 +#define RFC_ULLRAM_BANK11681_DATA_W 32 +#define RFC_ULLRAM_BANK11681_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11681_DATA_S 0 //***************************************************************************** // @@ -26379,9 +26379,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11682_DATA_W 32 -#define RFC_ULLRAM_BANK11682_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11682_DATA_S 0 +#define RFC_ULLRAM_BANK11682_DATA_W 32 +#define RFC_ULLRAM_BANK11682_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11682_DATA_S 0 //***************************************************************************** // @@ -26391,9 +26391,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11683_DATA_W 32 -#define RFC_ULLRAM_BANK11683_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11683_DATA_S 0 +#define RFC_ULLRAM_BANK11683_DATA_W 32 +#define RFC_ULLRAM_BANK11683_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11683_DATA_S 0 //***************************************************************************** // @@ -26403,9 +26403,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11684_DATA_W 32 -#define RFC_ULLRAM_BANK11684_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11684_DATA_S 0 +#define RFC_ULLRAM_BANK11684_DATA_W 32 +#define RFC_ULLRAM_BANK11684_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11684_DATA_S 0 //***************************************************************************** // @@ -26415,9 +26415,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11685_DATA_W 32 -#define RFC_ULLRAM_BANK11685_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11685_DATA_S 0 +#define RFC_ULLRAM_BANK11685_DATA_W 32 +#define RFC_ULLRAM_BANK11685_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11685_DATA_S 0 //***************************************************************************** // @@ -26427,9 +26427,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11686_DATA_W 32 -#define RFC_ULLRAM_BANK11686_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11686_DATA_S 0 +#define RFC_ULLRAM_BANK11686_DATA_W 32 +#define RFC_ULLRAM_BANK11686_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11686_DATA_S 0 //***************************************************************************** // @@ -26439,9 +26439,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11687_DATA_W 32 -#define RFC_ULLRAM_BANK11687_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11687_DATA_S 0 +#define RFC_ULLRAM_BANK11687_DATA_W 32 +#define RFC_ULLRAM_BANK11687_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11687_DATA_S 0 //***************************************************************************** // @@ -26451,9 +26451,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11688_DATA_W 32 -#define RFC_ULLRAM_BANK11688_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11688_DATA_S 0 +#define RFC_ULLRAM_BANK11688_DATA_W 32 +#define RFC_ULLRAM_BANK11688_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11688_DATA_S 0 //***************************************************************************** // @@ -26463,9 +26463,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11689_DATA_W 32 -#define RFC_ULLRAM_BANK11689_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11689_DATA_S 0 +#define RFC_ULLRAM_BANK11689_DATA_W 32 +#define RFC_ULLRAM_BANK11689_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11689_DATA_S 0 //***************************************************************************** // @@ -26475,9 +26475,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11690_DATA_W 32 -#define RFC_ULLRAM_BANK11690_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11690_DATA_S 0 +#define RFC_ULLRAM_BANK11690_DATA_W 32 +#define RFC_ULLRAM_BANK11690_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11690_DATA_S 0 //***************************************************************************** // @@ -26487,9 +26487,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11691_DATA_W 32 -#define RFC_ULLRAM_BANK11691_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11691_DATA_S 0 +#define RFC_ULLRAM_BANK11691_DATA_W 32 +#define RFC_ULLRAM_BANK11691_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11691_DATA_S 0 //***************************************************************************** // @@ -26499,9 +26499,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11692_DATA_W 32 -#define RFC_ULLRAM_BANK11692_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11692_DATA_S 0 +#define RFC_ULLRAM_BANK11692_DATA_W 32 +#define RFC_ULLRAM_BANK11692_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11692_DATA_S 0 //***************************************************************************** // @@ -26511,9 +26511,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11693_DATA_W 32 -#define RFC_ULLRAM_BANK11693_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11693_DATA_S 0 +#define RFC_ULLRAM_BANK11693_DATA_W 32 +#define RFC_ULLRAM_BANK11693_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11693_DATA_S 0 //***************************************************************************** // @@ -26523,9 +26523,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11694_DATA_W 32 -#define RFC_ULLRAM_BANK11694_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11694_DATA_S 0 +#define RFC_ULLRAM_BANK11694_DATA_W 32 +#define RFC_ULLRAM_BANK11694_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11694_DATA_S 0 //***************************************************************************** // @@ -26535,9 +26535,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11695_DATA_W 32 -#define RFC_ULLRAM_BANK11695_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11695_DATA_S 0 +#define RFC_ULLRAM_BANK11695_DATA_W 32 +#define RFC_ULLRAM_BANK11695_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11695_DATA_S 0 //***************************************************************************** // @@ -26547,9 +26547,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11696_DATA_W 32 -#define RFC_ULLRAM_BANK11696_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11696_DATA_S 0 +#define RFC_ULLRAM_BANK11696_DATA_W 32 +#define RFC_ULLRAM_BANK11696_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11696_DATA_S 0 //***************************************************************************** // @@ -26559,9 +26559,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11697_DATA_W 32 -#define RFC_ULLRAM_BANK11697_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11697_DATA_S 0 +#define RFC_ULLRAM_BANK11697_DATA_W 32 +#define RFC_ULLRAM_BANK11697_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11697_DATA_S 0 //***************************************************************************** // @@ -26571,9 +26571,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11698_DATA_W 32 -#define RFC_ULLRAM_BANK11698_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11698_DATA_S 0 +#define RFC_ULLRAM_BANK11698_DATA_W 32 +#define RFC_ULLRAM_BANK11698_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11698_DATA_S 0 //***************************************************************************** // @@ -26583,9 +26583,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11699_DATA_W 32 -#define RFC_ULLRAM_BANK11699_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11699_DATA_S 0 +#define RFC_ULLRAM_BANK11699_DATA_W 32 +#define RFC_ULLRAM_BANK11699_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11699_DATA_S 0 //***************************************************************************** // @@ -26595,9 +26595,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11700_DATA_W 32 -#define RFC_ULLRAM_BANK11700_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11700_DATA_S 0 +#define RFC_ULLRAM_BANK11700_DATA_W 32 +#define RFC_ULLRAM_BANK11700_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11700_DATA_S 0 //***************************************************************************** // @@ -26607,9 +26607,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11701_DATA_W 32 -#define RFC_ULLRAM_BANK11701_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11701_DATA_S 0 +#define RFC_ULLRAM_BANK11701_DATA_W 32 +#define RFC_ULLRAM_BANK11701_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11701_DATA_S 0 //***************************************************************************** // @@ -26619,9 +26619,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11702_DATA_W 32 -#define RFC_ULLRAM_BANK11702_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11702_DATA_S 0 +#define RFC_ULLRAM_BANK11702_DATA_W 32 +#define RFC_ULLRAM_BANK11702_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11702_DATA_S 0 //***************************************************************************** // @@ -26631,9 +26631,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11703_DATA_W 32 -#define RFC_ULLRAM_BANK11703_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11703_DATA_S 0 +#define RFC_ULLRAM_BANK11703_DATA_W 32 +#define RFC_ULLRAM_BANK11703_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11703_DATA_S 0 //***************************************************************************** // @@ -26643,9 +26643,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11704_DATA_W 32 -#define RFC_ULLRAM_BANK11704_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11704_DATA_S 0 +#define RFC_ULLRAM_BANK11704_DATA_W 32 +#define RFC_ULLRAM_BANK11704_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11704_DATA_S 0 //***************************************************************************** // @@ -26655,9 +26655,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11705_DATA_W 32 -#define RFC_ULLRAM_BANK11705_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11705_DATA_S 0 +#define RFC_ULLRAM_BANK11705_DATA_W 32 +#define RFC_ULLRAM_BANK11705_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11705_DATA_S 0 //***************************************************************************** // @@ -26667,9 +26667,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11706_DATA_W 32 -#define RFC_ULLRAM_BANK11706_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11706_DATA_S 0 +#define RFC_ULLRAM_BANK11706_DATA_W 32 +#define RFC_ULLRAM_BANK11706_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11706_DATA_S 0 //***************************************************************************** // @@ -26679,9 +26679,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11707_DATA_W 32 -#define RFC_ULLRAM_BANK11707_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11707_DATA_S 0 +#define RFC_ULLRAM_BANK11707_DATA_W 32 +#define RFC_ULLRAM_BANK11707_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11707_DATA_S 0 //***************************************************************************** // @@ -26691,9 +26691,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11708_DATA_W 32 -#define RFC_ULLRAM_BANK11708_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11708_DATA_S 0 +#define RFC_ULLRAM_BANK11708_DATA_W 32 +#define RFC_ULLRAM_BANK11708_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11708_DATA_S 0 //***************************************************************************** // @@ -26703,9 +26703,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11709_DATA_W 32 -#define RFC_ULLRAM_BANK11709_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11709_DATA_S 0 +#define RFC_ULLRAM_BANK11709_DATA_W 32 +#define RFC_ULLRAM_BANK11709_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11709_DATA_S 0 //***************************************************************************** // @@ -26715,9 +26715,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11710_DATA_W 32 -#define RFC_ULLRAM_BANK11710_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11710_DATA_S 0 +#define RFC_ULLRAM_BANK11710_DATA_W 32 +#define RFC_ULLRAM_BANK11710_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11710_DATA_S 0 //***************************************************************************** // @@ -26727,9 +26727,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11711_DATA_W 32 -#define RFC_ULLRAM_BANK11711_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11711_DATA_S 0 +#define RFC_ULLRAM_BANK11711_DATA_W 32 +#define RFC_ULLRAM_BANK11711_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11711_DATA_S 0 //***************************************************************************** // @@ -26739,9 +26739,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11712_DATA_W 32 -#define RFC_ULLRAM_BANK11712_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11712_DATA_S 0 +#define RFC_ULLRAM_BANK11712_DATA_W 32 +#define RFC_ULLRAM_BANK11712_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11712_DATA_S 0 //***************************************************************************** // @@ -26751,9 +26751,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11713_DATA_W 32 -#define RFC_ULLRAM_BANK11713_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11713_DATA_S 0 +#define RFC_ULLRAM_BANK11713_DATA_W 32 +#define RFC_ULLRAM_BANK11713_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11713_DATA_S 0 //***************************************************************************** // @@ -26763,9 +26763,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11714_DATA_W 32 -#define RFC_ULLRAM_BANK11714_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11714_DATA_S 0 +#define RFC_ULLRAM_BANK11714_DATA_W 32 +#define RFC_ULLRAM_BANK11714_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11714_DATA_S 0 //***************************************************************************** // @@ -26775,9 +26775,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11715_DATA_W 32 -#define RFC_ULLRAM_BANK11715_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11715_DATA_S 0 +#define RFC_ULLRAM_BANK11715_DATA_W 32 +#define RFC_ULLRAM_BANK11715_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11715_DATA_S 0 //***************************************************************************** // @@ -26787,9 +26787,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11716_DATA_W 32 -#define RFC_ULLRAM_BANK11716_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11716_DATA_S 0 +#define RFC_ULLRAM_BANK11716_DATA_W 32 +#define RFC_ULLRAM_BANK11716_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11716_DATA_S 0 //***************************************************************************** // @@ -26799,9 +26799,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11717_DATA_W 32 -#define RFC_ULLRAM_BANK11717_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11717_DATA_S 0 +#define RFC_ULLRAM_BANK11717_DATA_W 32 +#define RFC_ULLRAM_BANK11717_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11717_DATA_S 0 //***************************************************************************** // @@ -26811,9 +26811,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11718_DATA_W 32 -#define RFC_ULLRAM_BANK11718_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11718_DATA_S 0 +#define RFC_ULLRAM_BANK11718_DATA_W 32 +#define RFC_ULLRAM_BANK11718_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11718_DATA_S 0 //***************************************************************************** // @@ -26823,9 +26823,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11719_DATA_W 32 -#define RFC_ULLRAM_BANK11719_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11719_DATA_S 0 +#define RFC_ULLRAM_BANK11719_DATA_W 32 +#define RFC_ULLRAM_BANK11719_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11719_DATA_S 0 //***************************************************************************** // @@ -26835,9 +26835,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11720_DATA_W 32 -#define RFC_ULLRAM_BANK11720_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11720_DATA_S 0 +#define RFC_ULLRAM_BANK11720_DATA_W 32 +#define RFC_ULLRAM_BANK11720_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11720_DATA_S 0 //***************************************************************************** // @@ -26847,9 +26847,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11721_DATA_W 32 -#define RFC_ULLRAM_BANK11721_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11721_DATA_S 0 +#define RFC_ULLRAM_BANK11721_DATA_W 32 +#define RFC_ULLRAM_BANK11721_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11721_DATA_S 0 //***************************************************************************** // @@ -26859,9 +26859,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11722_DATA_W 32 -#define RFC_ULLRAM_BANK11722_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11722_DATA_S 0 +#define RFC_ULLRAM_BANK11722_DATA_W 32 +#define RFC_ULLRAM_BANK11722_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11722_DATA_S 0 //***************************************************************************** // @@ -26871,9 +26871,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11723_DATA_W 32 -#define RFC_ULLRAM_BANK11723_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11723_DATA_S 0 +#define RFC_ULLRAM_BANK11723_DATA_W 32 +#define RFC_ULLRAM_BANK11723_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11723_DATA_S 0 //***************************************************************************** // @@ -26883,9 +26883,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11724_DATA_W 32 -#define RFC_ULLRAM_BANK11724_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11724_DATA_S 0 +#define RFC_ULLRAM_BANK11724_DATA_W 32 +#define RFC_ULLRAM_BANK11724_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11724_DATA_S 0 //***************************************************************************** // @@ -26895,9 +26895,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11725_DATA_W 32 -#define RFC_ULLRAM_BANK11725_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11725_DATA_S 0 +#define RFC_ULLRAM_BANK11725_DATA_W 32 +#define RFC_ULLRAM_BANK11725_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11725_DATA_S 0 //***************************************************************************** // @@ -26907,9 +26907,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11726_DATA_W 32 -#define RFC_ULLRAM_BANK11726_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11726_DATA_S 0 +#define RFC_ULLRAM_BANK11726_DATA_W 32 +#define RFC_ULLRAM_BANK11726_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11726_DATA_S 0 //***************************************************************************** // @@ -26919,9 +26919,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11727_DATA_W 32 -#define RFC_ULLRAM_BANK11727_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11727_DATA_S 0 +#define RFC_ULLRAM_BANK11727_DATA_W 32 +#define RFC_ULLRAM_BANK11727_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11727_DATA_S 0 //***************************************************************************** // @@ -26931,9 +26931,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11728_DATA_W 32 -#define RFC_ULLRAM_BANK11728_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11728_DATA_S 0 +#define RFC_ULLRAM_BANK11728_DATA_W 32 +#define RFC_ULLRAM_BANK11728_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11728_DATA_S 0 //***************************************************************************** // @@ -26943,9 +26943,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11729_DATA_W 32 -#define RFC_ULLRAM_BANK11729_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11729_DATA_S 0 +#define RFC_ULLRAM_BANK11729_DATA_W 32 +#define RFC_ULLRAM_BANK11729_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11729_DATA_S 0 //***************************************************************************** // @@ -26955,9 +26955,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11730_DATA_W 32 -#define RFC_ULLRAM_BANK11730_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11730_DATA_S 0 +#define RFC_ULLRAM_BANK11730_DATA_W 32 +#define RFC_ULLRAM_BANK11730_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11730_DATA_S 0 //***************************************************************************** // @@ -26967,9 +26967,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11731_DATA_W 32 -#define RFC_ULLRAM_BANK11731_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11731_DATA_S 0 +#define RFC_ULLRAM_BANK11731_DATA_W 32 +#define RFC_ULLRAM_BANK11731_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11731_DATA_S 0 //***************************************************************************** // @@ -26979,9 +26979,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11732_DATA_W 32 -#define RFC_ULLRAM_BANK11732_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11732_DATA_S 0 +#define RFC_ULLRAM_BANK11732_DATA_W 32 +#define RFC_ULLRAM_BANK11732_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11732_DATA_S 0 //***************************************************************************** // @@ -26991,9 +26991,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11733_DATA_W 32 -#define RFC_ULLRAM_BANK11733_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11733_DATA_S 0 +#define RFC_ULLRAM_BANK11733_DATA_W 32 +#define RFC_ULLRAM_BANK11733_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11733_DATA_S 0 //***************************************************************************** // @@ -27003,9 +27003,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11734_DATA_W 32 -#define RFC_ULLRAM_BANK11734_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11734_DATA_S 0 +#define RFC_ULLRAM_BANK11734_DATA_W 32 +#define RFC_ULLRAM_BANK11734_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11734_DATA_S 0 //***************************************************************************** // @@ -27015,9 +27015,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11735_DATA_W 32 -#define RFC_ULLRAM_BANK11735_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11735_DATA_S 0 +#define RFC_ULLRAM_BANK11735_DATA_W 32 +#define RFC_ULLRAM_BANK11735_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11735_DATA_S 0 //***************************************************************************** // @@ -27027,9 +27027,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11736_DATA_W 32 -#define RFC_ULLRAM_BANK11736_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11736_DATA_S 0 +#define RFC_ULLRAM_BANK11736_DATA_W 32 +#define RFC_ULLRAM_BANK11736_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11736_DATA_S 0 //***************************************************************************** // @@ -27039,9 +27039,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11737_DATA_W 32 -#define RFC_ULLRAM_BANK11737_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11737_DATA_S 0 +#define RFC_ULLRAM_BANK11737_DATA_W 32 +#define RFC_ULLRAM_BANK11737_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11737_DATA_S 0 //***************************************************************************** // @@ -27051,9 +27051,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11738_DATA_W 32 -#define RFC_ULLRAM_BANK11738_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11738_DATA_S 0 +#define RFC_ULLRAM_BANK11738_DATA_W 32 +#define RFC_ULLRAM_BANK11738_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11738_DATA_S 0 //***************************************************************************** // @@ -27063,9 +27063,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11739_DATA_W 32 -#define RFC_ULLRAM_BANK11739_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11739_DATA_S 0 +#define RFC_ULLRAM_BANK11739_DATA_W 32 +#define RFC_ULLRAM_BANK11739_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11739_DATA_S 0 //***************************************************************************** // @@ -27075,9 +27075,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11740_DATA_W 32 -#define RFC_ULLRAM_BANK11740_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11740_DATA_S 0 +#define RFC_ULLRAM_BANK11740_DATA_W 32 +#define RFC_ULLRAM_BANK11740_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11740_DATA_S 0 //***************************************************************************** // @@ -27087,9 +27087,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11741_DATA_W 32 -#define RFC_ULLRAM_BANK11741_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11741_DATA_S 0 +#define RFC_ULLRAM_BANK11741_DATA_W 32 +#define RFC_ULLRAM_BANK11741_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11741_DATA_S 0 //***************************************************************************** // @@ -27099,9 +27099,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11742_DATA_W 32 -#define RFC_ULLRAM_BANK11742_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11742_DATA_S 0 +#define RFC_ULLRAM_BANK11742_DATA_W 32 +#define RFC_ULLRAM_BANK11742_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11742_DATA_S 0 //***************************************************************************** // @@ -27111,9 +27111,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11743_DATA_W 32 -#define RFC_ULLRAM_BANK11743_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11743_DATA_S 0 +#define RFC_ULLRAM_BANK11743_DATA_W 32 +#define RFC_ULLRAM_BANK11743_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11743_DATA_S 0 //***************************************************************************** // @@ -27123,9 +27123,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11744_DATA_W 32 -#define RFC_ULLRAM_BANK11744_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11744_DATA_S 0 +#define RFC_ULLRAM_BANK11744_DATA_W 32 +#define RFC_ULLRAM_BANK11744_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11744_DATA_S 0 //***************************************************************************** // @@ -27135,9 +27135,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11745_DATA_W 32 -#define RFC_ULLRAM_BANK11745_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11745_DATA_S 0 +#define RFC_ULLRAM_BANK11745_DATA_W 32 +#define RFC_ULLRAM_BANK11745_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11745_DATA_S 0 //***************************************************************************** // @@ -27147,9 +27147,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11746_DATA_W 32 -#define RFC_ULLRAM_BANK11746_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11746_DATA_S 0 +#define RFC_ULLRAM_BANK11746_DATA_W 32 +#define RFC_ULLRAM_BANK11746_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11746_DATA_S 0 //***************************************************************************** // @@ -27159,9 +27159,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11747_DATA_W 32 -#define RFC_ULLRAM_BANK11747_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11747_DATA_S 0 +#define RFC_ULLRAM_BANK11747_DATA_W 32 +#define RFC_ULLRAM_BANK11747_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11747_DATA_S 0 //***************************************************************************** // @@ -27171,9 +27171,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11748_DATA_W 32 -#define RFC_ULLRAM_BANK11748_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11748_DATA_S 0 +#define RFC_ULLRAM_BANK11748_DATA_W 32 +#define RFC_ULLRAM_BANK11748_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11748_DATA_S 0 //***************************************************************************** // @@ -27183,9 +27183,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11749_DATA_W 32 -#define RFC_ULLRAM_BANK11749_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11749_DATA_S 0 +#define RFC_ULLRAM_BANK11749_DATA_W 32 +#define RFC_ULLRAM_BANK11749_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11749_DATA_S 0 //***************************************************************************** // @@ -27195,9 +27195,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11750_DATA_W 32 -#define RFC_ULLRAM_BANK11750_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11750_DATA_S 0 +#define RFC_ULLRAM_BANK11750_DATA_W 32 +#define RFC_ULLRAM_BANK11750_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11750_DATA_S 0 //***************************************************************************** // @@ -27207,9 +27207,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11751_DATA_W 32 -#define RFC_ULLRAM_BANK11751_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11751_DATA_S 0 +#define RFC_ULLRAM_BANK11751_DATA_W 32 +#define RFC_ULLRAM_BANK11751_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11751_DATA_S 0 //***************************************************************************** // @@ -27219,9 +27219,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11752_DATA_W 32 -#define RFC_ULLRAM_BANK11752_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11752_DATA_S 0 +#define RFC_ULLRAM_BANK11752_DATA_W 32 +#define RFC_ULLRAM_BANK11752_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11752_DATA_S 0 //***************************************************************************** // @@ -27231,9 +27231,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11753_DATA_W 32 -#define RFC_ULLRAM_BANK11753_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11753_DATA_S 0 +#define RFC_ULLRAM_BANK11753_DATA_W 32 +#define RFC_ULLRAM_BANK11753_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11753_DATA_S 0 //***************************************************************************** // @@ -27243,9 +27243,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11754_DATA_W 32 -#define RFC_ULLRAM_BANK11754_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11754_DATA_S 0 +#define RFC_ULLRAM_BANK11754_DATA_W 32 +#define RFC_ULLRAM_BANK11754_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11754_DATA_S 0 //***************************************************************************** // @@ -27255,9 +27255,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11755_DATA_W 32 -#define RFC_ULLRAM_BANK11755_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11755_DATA_S 0 +#define RFC_ULLRAM_BANK11755_DATA_W 32 +#define RFC_ULLRAM_BANK11755_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11755_DATA_S 0 //***************************************************************************** // @@ -27267,9 +27267,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11756_DATA_W 32 -#define RFC_ULLRAM_BANK11756_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11756_DATA_S 0 +#define RFC_ULLRAM_BANK11756_DATA_W 32 +#define RFC_ULLRAM_BANK11756_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11756_DATA_S 0 //***************************************************************************** // @@ -27279,9 +27279,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11757_DATA_W 32 -#define RFC_ULLRAM_BANK11757_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11757_DATA_S 0 +#define RFC_ULLRAM_BANK11757_DATA_W 32 +#define RFC_ULLRAM_BANK11757_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11757_DATA_S 0 //***************************************************************************** // @@ -27291,9 +27291,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11758_DATA_W 32 -#define RFC_ULLRAM_BANK11758_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11758_DATA_S 0 +#define RFC_ULLRAM_BANK11758_DATA_W 32 +#define RFC_ULLRAM_BANK11758_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11758_DATA_S 0 //***************************************************************************** // @@ -27303,9 +27303,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11759_DATA_W 32 -#define RFC_ULLRAM_BANK11759_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11759_DATA_S 0 +#define RFC_ULLRAM_BANK11759_DATA_W 32 +#define RFC_ULLRAM_BANK11759_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11759_DATA_S 0 //***************************************************************************** // @@ -27315,9 +27315,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11760_DATA_W 32 -#define RFC_ULLRAM_BANK11760_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11760_DATA_S 0 +#define RFC_ULLRAM_BANK11760_DATA_W 32 +#define RFC_ULLRAM_BANK11760_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11760_DATA_S 0 //***************************************************************************** // @@ -27327,9 +27327,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11761_DATA_W 32 -#define RFC_ULLRAM_BANK11761_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11761_DATA_S 0 +#define RFC_ULLRAM_BANK11761_DATA_W 32 +#define RFC_ULLRAM_BANK11761_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11761_DATA_S 0 //***************************************************************************** // @@ -27339,9 +27339,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11762_DATA_W 32 -#define RFC_ULLRAM_BANK11762_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11762_DATA_S 0 +#define RFC_ULLRAM_BANK11762_DATA_W 32 +#define RFC_ULLRAM_BANK11762_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11762_DATA_S 0 //***************************************************************************** // @@ -27351,9 +27351,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11763_DATA_W 32 -#define RFC_ULLRAM_BANK11763_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11763_DATA_S 0 +#define RFC_ULLRAM_BANK11763_DATA_W 32 +#define RFC_ULLRAM_BANK11763_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11763_DATA_S 0 //***************************************************************************** // @@ -27363,9 +27363,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11764_DATA_W 32 -#define RFC_ULLRAM_BANK11764_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11764_DATA_S 0 +#define RFC_ULLRAM_BANK11764_DATA_W 32 +#define RFC_ULLRAM_BANK11764_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11764_DATA_S 0 //***************************************************************************** // @@ -27375,9 +27375,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11765_DATA_W 32 -#define RFC_ULLRAM_BANK11765_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11765_DATA_S 0 +#define RFC_ULLRAM_BANK11765_DATA_W 32 +#define RFC_ULLRAM_BANK11765_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11765_DATA_S 0 //***************************************************************************** // @@ -27387,9 +27387,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11766_DATA_W 32 -#define RFC_ULLRAM_BANK11766_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11766_DATA_S 0 +#define RFC_ULLRAM_BANK11766_DATA_W 32 +#define RFC_ULLRAM_BANK11766_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11766_DATA_S 0 //***************************************************************************** // @@ -27399,9 +27399,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11767_DATA_W 32 -#define RFC_ULLRAM_BANK11767_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11767_DATA_S 0 +#define RFC_ULLRAM_BANK11767_DATA_W 32 +#define RFC_ULLRAM_BANK11767_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11767_DATA_S 0 //***************************************************************************** // @@ -27411,9 +27411,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11768_DATA_W 32 -#define RFC_ULLRAM_BANK11768_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11768_DATA_S 0 +#define RFC_ULLRAM_BANK11768_DATA_W 32 +#define RFC_ULLRAM_BANK11768_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11768_DATA_S 0 //***************************************************************************** // @@ -27423,9 +27423,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11769_DATA_W 32 -#define RFC_ULLRAM_BANK11769_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11769_DATA_S 0 +#define RFC_ULLRAM_BANK11769_DATA_W 32 +#define RFC_ULLRAM_BANK11769_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11769_DATA_S 0 //***************************************************************************** // @@ -27435,9 +27435,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11770_DATA_W 32 -#define RFC_ULLRAM_BANK11770_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11770_DATA_S 0 +#define RFC_ULLRAM_BANK11770_DATA_W 32 +#define RFC_ULLRAM_BANK11770_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11770_DATA_S 0 //***************************************************************************** // @@ -27447,9 +27447,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11771_DATA_W 32 -#define RFC_ULLRAM_BANK11771_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11771_DATA_S 0 +#define RFC_ULLRAM_BANK11771_DATA_W 32 +#define RFC_ULLRAM_BANK11771_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11771_DATA_S 0 //***************************************************************************** // @@ -27459,9 +27459,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11772_DATA_W 32 -#define RFC_ULLRAM_BANK11772_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11772_DATA_S 0 +#define RFC_ULLRAM_BANK11772_DATA_W 32 +#define RFC_ULLRAM_BANK11772_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11772_DATA_S 0 //***************************************************************************** // @@ -27471,9 +27471,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11773_DATA_W 32 -#define RFC_ULLRAM_BANK11773_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11773_DATA_S 0 +#define RFC_ULLRAM_BANK11773_DATA_W 32 +#define RFC_ULLRAM_BANK11773_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11773_DATA_S 0 //***************************************************************************** // @@ -27483,9 +27483,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11774_DATA_W 32 -#define RFC_ULLRAM_BANK11774_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11774_DATA_S 0 +#define RFC_ULLRAM_BANK11774_DATA_W 32 +#define RFC_ULLRAM_BANK11774_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11774_DATA_S 0 //***************************************************************************** // @@ -27495,9 +27495,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11775_DATA_W 32 -#define RFC_ULLRAM_BANK11775_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11775_DATA_S 0 +#define RFC_ULLRAM_BANK11775_DATA_W 32 +#define RFC_ULLRAM_BANK11775_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11775_DATA_S 0 //***************************************************************************** // @@ -27507,9 +27507,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11776_DATA_W 32 -#define RFC_ULLRAM_BANK11776_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11776_DATA_S 0 +#define RFC_ULLRAM_BANK11776_DATA_W 32 +#define RFC_ULLRAM_BANK11776_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11776_DATA_S 0 //***************************************************************************** // @@ -27519,9 +27519,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11777_DATA_W 32 -#define RFC_ULLRAM_BANK11777_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11777_DATA_S 0 +#define RFC_ULLRAM_BANK11777_DATA_W 32 +#define RFC_ULLRAM_BANK11777_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11777_DATA_S 0 //***************************************************************************** // @@ -27531,9 +27531,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11778_DATA_W 32 -#define RFC_ULLRAM_BANK11778_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11778_DATA_S 0 +#define RFC_ULLRAM_BANK11778_DATA_W 32 +#define RFC_ULLRAM_BANK11778_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11778_DATA_S 0 //***************************************************************************** // @@ -27543,9 +27543,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11779_DATA_W 32 -#define RFC_ULLRAM_BANK11779_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11779_DATA_S 0 +#define RFC_ULLRAM_BANK11779_DATA_W 32 +#define RFC_ULLRAM_BANK11779_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11779_DATA_S 0 //***************************************************************************** // @@ -27555,9 +27555,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11780_DATA_W 32 -#define RFC_ULLRAM_BANK11780_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11780_DATA_S 0 +#define RFC_ULLRAM_BANK11780_DATA_W 32 +#define RFC_ULLRAM_BANK11780_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11780_DATA_S 0 //***************************************************************************** // @@ -27567,9 +27567,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11781_DATA_W 32 -#define RFC_ULLRAM_BANK11781_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11781_DATA_S 0 +#define RFC_ULLRAM_BANK11781_DATA_W 32 +#define RFC_ULLRAM_BANK11781_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11781_DATA_S 0 //***************************************************************************** // @@ -27579,9 +27579,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11782_DATA_W 32 -#define RFC_ULLRAM_BANK11782_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11782_DATA_S 0 +#define RFC_ULLRAM_BANK11782_DATA_W 32 +#define RFC_ULLRAM_BANK11782_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11782_DATA_S 0 //***************************************************************************** // @@ -27591,9 +27591,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11783_DATA_W 32 -#define RFC_ULLRAM_BANK11783_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11783_DATA_S 0 +#define RFC_ULLRAM_BANK11783_DATA_W 32 +#define RFC_ULLRAM_BANK11783_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11783_DATA_S 0 //***************************************************************************** // @@ -27603,9 +27603,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11784_DATA_W 32 -#define RFC_ULLRAM_BANK11784_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11784_DATA_S 0 +#define RFC_ULLRAM_BANK11784_DATA_W 32 +#define RFC_ULLRAM_BANK11784_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11784_DATA_S 0 //***************************************************************************** // @@ -27615,9 +27615,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11785_DATA_W 32 -#define RFC_ULLRAM_BANK11785_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11785_DATA_S 0 +#define RFC_ULLRAM_BANK11785_DATA_W 32 +#define RFC_ULLRAM_BANK11785_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11785_DATA_S 0 //***************************************************************************** // @@ -27627,9 +27627,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11786_DATA_W 32 -#define RFC_ULLRAM_BANK11786_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11786_DATA_S 0 +#define RFC_ULLRAM_BANK11786_DATA_W 32 +#define RFC_ULLRAM_BANK11786_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11786_DATA_S 0 //***************************************************************************** // @@ -27639,9 +27639,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11787_DATA_W 32 -#define RFC_ULLRAM_BANK11787_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11787_DATA_S 0 +#define RFC_ULLRAM_BANK11787_DATA_W 32 +#define RFC_ULLRAM_BANK11787_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11787_DATA_S 0 //***************************************************************************** // @@ -27651,9 +27651,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11788_DATA_W 32 -#define RFC_ULLRAM_BANK11788_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11788_DATA_S 0 +#define RFC_ULLRAM_BANK11788_DATA_W 32 +#define RFC_ULLRAM_BANK11788_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11788_DATA_S 0 //***************************************************************************** // @@ -27663,9 +27663,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11789_DATA_W 32 -#define RFC_ULLRAM_BANK11789_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11789_DATA_S 0 +#define RFC_ULLRAM_BANK11789_DATA_W 32 +#define RFC_ULLRAM_BANK11789_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11789_DATA_S 0 //***************************************************************************** // @@ -27675,9 +27675,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11790_DATA_W 32 -#define RFC_ULLRAM_BANK11790_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11790_DATA_S 0 +#define RFC_ULLRAM_BANK11790_DATA_W 32 +#define RFC_ULLRAM_BANK11790_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11790_DATA_S 0 //***************************************************************************** // @@ -27687,9 +27687,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11791_DATA_W 32 -#define RFC_ULLRAM_BANK11791_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11791_DATA_S 0 +#define RFC_ULLRAM_BANK11791_DATA_W 32 +#define RFC_ULLRAM_BANK11791_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11791_DATA_S 0 //***************************************************************************** // @@ -27699,9 +27699,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11792_DATA_W 32 -#define RFC_ULLRAM_BANK11792_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11792_DATA_S 0 +#define RFC_ULLRAM_BANK11792_DATA_W 32 +#define RFC_ULLRAM_BANK11792_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11792_DATA_S 0 //***************************************************************************** // @@ -27711,9 +27711,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11793_DATA_W 32 -#define RFC_ULLRAM_BANK11793_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11793_DATA_S 0 +#define RFC_ULLRAM_BANK11793_DATA_W 32 +#define RFC_ULLRAM_BANK11793_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11793_DATA_S 0 //***************************************************************************** // @@ -27723,9 +27723,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11794_DATA_W 32 -#define RFC_ULLRAM_BANK11794_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11794_DATA_S 0 +#define RFC_ULLRAM_BANK11794_DATA_W 32 +#define RFC_ULLRAM_BANK11794_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11794_DATA_S 0 //***************************************************************************** // @@ -27735,9 +27735,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11795_DATA_W 32 -#define RFC_ULLRAM_BANK11795_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11795_DATA_S 0 +#define RFC_ULLRAM_BANK11795_DATA_W 32 +#define RFC_ULLRAM_BANK11795_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11795_DATA_S 0 //***************************************************************************** // @@ -27747,9 +27747,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11796_DATA_W 32 -#define RFC_ULLRAM_BANK11796_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11796_DATA_S 0 +#define RFC_ULLRAM_BANK11796_DATA_W 32 +#define RFC_ULLRAM_BANK11796_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11796_DATA_S 0 //***************************************************************************** // @@ -27759,9 +27759,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11797_DATA_W 32 -#define RFC_ULLRAM_BANK11797_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11797_DATA_S 0 +#define RFC_ULLRAM_BANK11797_DATA_W 32 +#define RFC_ULLRAM_BANK11797_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11797_DATA_S 0 //***************************************************************************** // @@ -27771,9 +27771,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11798_DATA_W 32 -#define RFC_ULLRAM_BANK11798_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11798_DATA_S 0 +#define RFC_ULLRAM_BANK11798_DATA_W 32 +#define RFC_ULLRAM_BANK11798_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11798_DATA_S 0 //***************************************************************************** // @@ -27783,9 +27783,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11799_DATA_W 32 -#define RFC_ULLRAM_BANK11799_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11799_DATA_S 0 +#define RFC_ULLRAM_BANK11799_DATA_W 32 +#define RFC_ULLRAM_BANK11799_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11799_DATA_S 0 //***************************************************************************** // @@ -27795,9 +27795,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11800_DATA_W 32 -#define RFC_ULLRAM_BANK11800_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11800_DATA_S 0 +#define RFC_ULLRAM_BANK11800_DATA_W 32 +#define RFC_ULLRAM_BANK11800_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11800_DATA_S 0 //***************************************************************************** // @@ -27807,9 +27807,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11801_DATA_W 32 -#define RFC_ULLRAM_BANK11801_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11801_DATA_S 0 +#define RFC_ULLRAM_BANK11801_DATA_W 32 +#define RFC_ULLRAM_BANK11801_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11801_DATA_S 0 //***************************************************************************** // @@ -27819,9 +27819,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11802_DATA_W 32 -#define RFC_ULLRAM_BANK11802_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11802_DATA_S 0 +#define RFC_ULLRAM_BANK11802_DATA_W 32 +#define RFC_ULLRAM_BANK11802_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11802_DATA_S 0 //***************************************************************************** // @@ -27831,9 +27831,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11803_DATA_W 32 -#define RFC_ULLRAM_BANK11803_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11803_DATA_S 0 +#define RFC_ULLRAM_BANK11803_DATA_W 32 +#define RFC_ULLRAM_BANK11803_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11803_DATA_S 0 //***************************************************************************** // @@ -27843,9 +27843,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11804_DATA_W 32 -#define RFC_ULLRAM_BANK11804_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11804_DATA_S 0 +#define RFC_ULLRAM_BANK11804_DATA_W 32 +#define RFC_ULLRAM_BANK11804_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11804_DATA_S 0 //***************************************************************************** // @@ -27855,9 +27855,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11805_DATA_W 32 -#define RFC_ULLRAM_BANK11805_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11805_DATA_S 0 +#define RFC_ULLRAM_BANK11805_DATA_W 32 +#define RFC_ULLRAM_BANK11805_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11805_DATA_S 0 //***************************************************************************** // @@ -27867,9 +27867,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11806_DATA_W 32 -#define RFC_ULLRAM_BANK11806_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11806_DATA_S 0 +#define RFC_ULLRAM_BANK11806_DATA_W 32 +#define RFC_ULLRAM_BANK11806_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11806_DATA_S 0 //***************************************************************************** // @@ -27879,9 +27879,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11807_DATA_W 32 -#define RFC_ULLRAM_BANK11807_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11807_DATA_S 0 +#define RFC_ULLRAM_BANK11807_DATA_W 32 +#define RFC_ULLRAM_BANK11807_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11807_DATA_S 0 //***************************************************************************** // @@ -27891,9 +27891,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11808_DATA_W 32 -#define RFC_ULLRAM_BANK11808_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11808_DATA_S 0 +#define RFC_ULLRAM_BANK11808_DATA_W 32 +#define RFC_ULLRAM_BANK11808_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11808_DATA_S 0 //***************************************************************************** // @@ -27903,9 +27903,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11809_DATA_W 32 -#define RFC_ULLRAM_BANK11809_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11809_DATA_S 0 +#define RFC_ULLRAM_BANK11809_DATA_W 32 +#define RFC_ULLRAM_BANK11809_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11809_DATA_S 0 //***************************************************************************** // @@ -27915,9 +27915,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11810_DATA_W 32 -#define RFC_ULLRAM_BANK11810_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11810_DATA_S 0 +#define RFC_ULLRAM_BANK11810_DATA_W 32 +#define RFC_ULLRAM_BANK11810_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11810_DATA_S 0 //***************************************************************************** // @@ -27927,9 +27927,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11811_DATA_W 32 -#define RFC_ULLRAM_BANK11811_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11811_DATA_S 0 +#define RFC_ULLRAM_BANK11811_DATA_W 32 +#define RFC_ULLRAM_BANK11811_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11811_DATA_S 0 //***************************************************************************** // @@ -27939,9 +27939,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11812_DATA_W 32 -#define RFC_ULLRAM_BANK11812_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11812_DATA_S 0 +#define RFC_ULLRAM_BANK11812_DATA_W 32 +#define RFC_ULLRAM_BANK11812_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11812_DATA_S 0 //***************************************************************************** // @@ -27951,9 +27951,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11813_DATA_W 32 -#define RFC_ULLRAM_BANK11813_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11813_DATA_S 0 +#define RFC_ULLRAM_BANK11813_DATA_W 32 +#define RFC_ULLRAM_BANK11813_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11813_DATA_S 0 //***************************************************************************** // @@ -27963,9 +27963,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11814_DATA_W 32 -#define RFC_ULLRAM_BANK11814_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11814_DATA_S 0 +#define RFC_ULLRAM_BANK11814_DATA_W 32 +#define RFC_ULLRAM_BANK11814_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11814_DATA_S 0 //***************************************************************************** // @@ -27975,9 +27975,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11815_DATA_W 32 -#define RFC_ULLRAM_BANK11815_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11815_DATA_S 0 +#define RFC_ULLRAM_BANK11815_DATA_W 32 +#define RFC_ULLRAM_BANK11815_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11815_DATA_S 0 //***************************************************************************** // @@ -27987,9 +27987,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11816_DATA_W 32 -#define RFC_ULLRAM_BANK11816_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11816_DATA_S 0 +#define RFC_ULLRAM_BANK11816_DATA_W 32 +#define RFC_ULLRAM_BANK11816_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11816_DATA_S 0 //***************************************************************************** // @@ -27999,9 +27999,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11817_DATA_W 32 -#define RFC_ULLRAM_BANK11817_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11817_DATA_S 0 +#define RFC_ULLRAM_BANK11817_DATA_W 32 +#define RFC_ULLRAM_BANK11817_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11817_DATA_S 0 //***************************************************************************** // @@ -28011,9 +28011,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11818_DATA_W 32 -#define RFC_ULLRAM_BANK11818_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11818_DATA_S 0 +#define RFC_ULLRAM_BANK11818_DATA_W 32 +#define RFC_ULLRAM_BANK11818_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11818_DATA_S 0 //***************************************************************************** // @@ -28023,9 +28023,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11819_DATA_W 32 -#define RFC_ULLRAM_BANK11819_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11819_DATA_S 0 +#define RFC_ULLRAM_BANK11819_DATA_W 32 +#define RFC_ULLRAM_BANK11819_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11819_DATA_S 0 //***************************************************************************** // @@ -28035,9 +28035,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11820_DATA_W 32 -#define RFC_ULLRAM_BANK11820_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11820_DATA_S 0 +#define RFC_ULLRAM_BANK11820_DATA_W 32 +#define RFC_ULLRAM_BANK11820_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11820_DATA_S 0 //***************************************************************************** // @@ -28047,9 +28047,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11821_DATA_W 32 -#define RFC_ULLRAM_BANK11821_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11821_DATA_S 0 +#define RFC_ULLRAM_BANK11821_DATA_W 32 +#define RFC_ULLRAM_BANK11821_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11821_DATA_S 0 //***************************************************************************** // @@ -28059,9 +28059,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11822_DATA_W 32 -#define RFC_ULLRAM_BANK11822_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11822_DATA_S 0 +#define RFC_ULLRAM_BANK11822_DATA_W 32 +#define RFC_ULLRAM_BANK11822_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11822_DATA_S 0 //***************************************************************************** // @@ -28071,9 +28071,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11823_DATA_W 32 -#define RFC_ULLRAM_BANK11823_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11823_DATA_S 0 +#define RFC_ULLRAM_BANK11823_DATA_W 32 +#define RFC_ULLRAM_BANK11823_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11823_DATA_S 0 //***************************************************************************** // @@ -28083,9 +28083,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11824_DATA_W 32 -#define RFC_ULLRAM_BANK11824_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11824_DATA_S 0 +#define RFC_ULLRAM_BANK11824_DATA_W 32 +#define RFC_ULLRAM_BANK11824_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11824_DATA_S 0 //***************************************************************************** // @@ -28095,9 +28095,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11825_DATA_W 32 -#define RFC_ULLRAM_BANK11825_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11825_DATA_S 0 +#define RFC_ULLRAM_BANK11825_DATA_W 32 +#define RFC_ULLRAM_BANK11825_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11825_DATA_S 0 //***************************************************************************** // @@ -28107,9 +28107,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11826_DATA_W 32 -#define RFC_ULLRAM_BANK11826_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11826_DATA_S 0 +#define RFC_ULLRAM_BANK11826_DATA_W 32 +#define RFC_ULLRAM_BANK11826_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11826_DATA_S 0 //***************************************************************************** // @@ -28119,9 +28119,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11827_DATA_W 32 -#define RFC_ULLRAM_BANK11827_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11827_DATA_S 0 +#define RFC_ULLRAM_BANK11827_DATA_W 32 +#define RFC_ULLRAM_BANK11827_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11827_DATA_S 0 //***************************************************************************** // @@ -28131,9 +28131,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11828_DATA_W 32 -#define RFC_ULLRAM_BANK11828_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11828_DATA_S 0 +#define RFC_ULLRAM_BANK11828_DATA_W 32 +#define RFC_ULLRAM_BANK11828_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11828_DATA_S 0 //***************************************************************************** // @@ -28143,9 +28143,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11829_DATA_W 32 -#define RFC_ULLRAM_BANK11829_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11829_DATA_S 0 +#define RFC_ULLRAM_BANK11829_DATA_W 32 +#define RFC_ULLRAM_BANK11829_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11829_DATA_S 0 //***************************************************************************** // @@ -28155,9 +28155,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11830_DATA_W 32 -#define RFC_ULLRAM_BANK11830_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11830_DATA_S 0 +#define RFC_ULLRAM_BANK11830_DATA_W 32 +#define RFC_ULLRAM_BANK11830_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11830_DATA_S 0 //***************************************************************************** // @@ -28167,9 +28167,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11831_DATA_W 32 -#define RFC_ULLRAM_BANK11831_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11831_DATA_S 0 +#define RFC_ULLRAM_BANK11831_DATA_W 32 +#define RFC_ULLRAM_BANK11831_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11831_DATA_S 0 //***************************************************************************** // @@ -28179,9 +28179,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11832_DATA_W 32 -#define RFC_ULLRAM_BANK11832_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11832_DATA_S 0 +#define RFC_ULLRAM_BANK11832_DATA_W 32 +#define RFC_ULLRAM_BANK11832_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11832_DATA_S 0 //***************************************************************************** // @@ -28191,9 +28191,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11833_DATA_W 32 -#define RFC_ULLRAM_BANK11833_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11833_DATA_S 0 +#define RFC_ULLRAM_BANK11833_DATA_W 32 +#define RFC_ULLRAM_BANK11833_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11833_DATA_S 0 //***************************************************************************** // @@ -28203,9 +28203,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11834_DATA_W 32 -#define RFC_ULLRAM_BANK11834_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11834_DATA_S 0 +#define RFC_ULLRAM_BANK11834_DATA_W 32 +#define RFC_ULLRAM_BANK11834_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11834_DATA_S 0 //***************************************************************************** // @@ -28215,9 +28215,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11835_DATA_W 32 -#define RFC_ULLRAM_BANK11835_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11835_DATA_S 0 +#define RFC_ULLRAM_BANK11835_DATA_W 32 +#define RFC_ULLRAM_BANK11835_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11835_DATA_S 0 //***************************************************************************** // @@ -28227,9 +28227,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11836_DATA_W 32 -#define RFC_ULLRAM_BANK11836_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11836_DATA_S 0 +#define RFC_ULLRAM_BANK11836_DATA_W 32 +#define RFC_ULLRAM_BANK11836_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11836_DATA_S 0 //***************************************************************************** // @@ -28239,9 +28239,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11837_DATA_W 32 -#define RFC_ULLRAM_BANK11837_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11837_DATA_S 0 +#define RFC_ULLRAM_BANK11837_DATA_W 32 +#define RFC_ULLRAM_BANK11837_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11837_DATA_S 0 //***************************************************************************** // @@ -28251,9 +28251,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11838_DATA_W 32 -#define RFC_ULLRAM_BANK11838_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11838_DATA_S 0 +#define RFC_ULLRAM_BANK11838_DATA_W 32 +#define RFC_ULLRAM_BANK11838_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11838_DATA_S 0 //***************************************************************************** // @@ -28263,9 +28263,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11839_DATA_W 32 -#define RFC_ULLRAM_BANK11839_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11839_DATA_S 0 +#define RFC_ULLRAM_BANK11839_DATA_W 32 +#define RFC_ULLRAM_BANK11839_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11839_DATA_S 0 //***************************************************************************** // @@ -28275,9 +28275,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11840_DATA_W 32 -#define RFC_ULLRAM_BANK11840_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11840_DATA_S 0 +#define RFC_ULLRAM_BANK11840_DATA_W 32 +#define RFC_ULLRAM_BANK11840_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11840_DATA_S 0 //***************************************************************************** // @@ -28287,9 +28287,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11841_DATA_W 32 -#define RFC_ULLRAM_BANK11841_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11841_DATA_S 0 +#define RFC_ULLRAM_BANK11841_DATA_W 32 +#define RFC_ULLRAM_BANK11841_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11841_DATA_S 0 //***************************************************************************** // @@ -28299,9 +28299,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11842_DATA_W 32 -#define RFC_ULLRAM_BANK11842_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11842_DATA_S 0 +#define RFC_ULLRAM_BANK11842_DATA_W 32 +#define RFC_ULLRAM_BANK11842_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11842_DATA_S 0 //***************************************************************************** // @@ -28311,9 +28311,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11843_DATA_W 32 -#define RFC_ULLRAM_BANK11843_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11843_DATA_S 0 +#define RFC_ULLRAM_BANK11843_DATA_W 32 +#define RFC_ULLRAM_BANK11843_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11843_DATA_S 0 //***************************************************************************** // @@ -28323,9 +28323,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11844_DATA_W 32 -#define RFC_ULLRAM_BANK11844_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11844_DATA_S 0 +#define RFC_ULLRAM_BANK11844_DATA_W 32 +#define RFC_ULLRAM_BANK11844_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11844_DATA_S 0 //***************************************************************************** // @@ -28335,9 +28335,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11845_DATA_W 32 -#define RFC_ULLRAM_BANK11845_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11845_DATA_S 0 +#define RFC_ULLRAM_BANK11845_DATA_W 32 +#define RFC_ULLRAM_BANK11845_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11845_DATA_S 0 //***************************************************************************** // @@ -28347,9 +28347,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11846_DATA_W 32 -#define RFC_ULLRAM_BANK11846_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11846_DATA_S 0 +#define RFC_ULLRAM_BANK11846_DATA_W 32 +#define RFC_ULLRAM_BANK11846_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11846_DATA_S 0 //***************************************************************************** // @@ -28359,9 +28359,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11847_DATA_W 32 -#define RFC_ULLRAM_BANK11847_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11847_DATA_S 0 +#define RFC_ULLRAM_BANK11847_DATA_W 32 +#define RFC_ULLRAM_BANK11847_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11847_DATA_S 0 //***************************************************************************** // @@ -28371,9 +28371,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11848_DATA_W 32 -#define RFC_ULLRAM_BANK11848_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11848_DATA_S 0 +#define RFC_ULLRAM_BANK11848_DATA_W 32 +#define RFC_ULLRAM_BANK11848_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11848_DATA_S 0 //***************************************************************************** // @@ -28383,9 +28383,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11849_DATA_W 32 -#define RFC_ULLRAM_BANK11849_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11849_DATA_S 0 +#define RFC_ULLRAM_BANK11849_DATA_W 32 +#define RFC_ULLRAM_BANK11849_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11849_DATA_S 0 //***************************************************************************** // @@ -28395,9 +28395,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11850_DATA_W 32 -#define RFC_ULLRAM_BANK11850_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11850_DATA_S 0 +#define RFC_ULLRAM_BANK11850_DATA_W 32 +#define RFC_ULLRAM_BANK11850_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11850_DATA_S 0 //***************************************************************************** // @@ -28407,9 +28407,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11851_DATA_W 32 -#define RFC_ULLRAM_BANK11851_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11851_DATA_S 0 +#define RFC_ULLRAM_BANK11851_DATA_W 32 +#define RFC_ULLRAM_BANK11851_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11851_DATA_S 0 //***************************************************************************** // @@ -28419,9 +28419,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11852_DATA_W 32 -#define RFC_ULLRAM_BANK11852_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11852_DATA_S 0 +#define RFC_ULLRAM_BANK11852_DATA_W 32 +#define RFC_ULLRAM_BANK11852_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11852_DATA_S 0 //***************************************************************************** // @@ -28431,9 +28431,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11853_DATA_W 32 -#define RFC_ULLRAM_BANK11853_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11853_DATA_S 0 +#define RFC_ULLRAM_BANK11853_DATA_W 32 +#define RFC_ULLRAM_BANK11853_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11853_DATA_S 0 //***************************************************************************** // @@ -28443,9 +28443,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11854_DATA_W 32 -#define RFC_ULLRAM_BANK11854_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11854_DATA_S 0 +#define RFC_ULLRAM_BANK11854_DATA_W 32 +#define RFC_ULLRAM_BANK11854_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11854_DATA_S 0 //***************************************************************************** // @@ -28455,9 +28455,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11855_DATA_W 32 -#define RFC_ULLRAM_BANK11855_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11855_DATA_S 0 +#define RFC_ULLRAM_BANK11855_DATA_W 32 +#define RFC_ULLRAM_BANK11855_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11855_DATA_S 0 //***************************************************************************** // @@ -28467,9 +28467,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11856_DATA_W 32 -#define RFC_ULLRAM_BANK11856_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11856_DATA_S 0 +#define RFC_ULLRAM_BANK11856_DATA_W 32 +#define RFC_ULLRAM_BANK11856_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11856_DATA_S 0 //***************************************************************************** // @@ -28479,9 +28479,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11857_DATA_W 32 -#define RFC_ULLRAM_BANK11857_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11857_DATA_S 0 +#define RFC_ULLRAM_BANK11857_DATA_W 32 +#define RFC_ULLRAM_BANK11857_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11857_DATA_S 0 //***************************************************************************** // @@ -28491,9 +28491,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11858_DATA_W 32 -#define RFC_ULLRAM_BANK11858_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11858_DATA_S 0 +#define RFC_ULLRAM_BANK11858_DATA_W 32 +#define RFC_ULLRAM_BANK11858_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11858_DATA_S 0 //***************************************************************************** // @@ -28503,9 +28503,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11859_DATA_W 32 -#define RFC_ULLRAM_BANK11859_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11859_DATA_S 0 +#define RFC_ULLRAM_BANK11859_DATA_W 32 +#define RFC_ULLRAM_BANK11859_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11859_DATA_S 0 //***************************************************************************** // @@ -28515,9 +28515,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11860_DATA_W 32 -#define RFC_ULLRAM_BANK11860_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11860_DATA_S 0 +#define RFC_ULLRAM_BANK11860_DATA_W 32 +#define RFC_ULLRAM_BANK11860_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11860_DATA_S 0 //***************************************************************************** // @@ -28527,9 +28527,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11861_DATA_W 32 -#define RFC_ULLRAM_BANK11861_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11861_DATA_S 0 +#define RFC_ULLRAM_BANK11861_DATA_W 32 +#define RFC_ULLRAM_BANK11861_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11861_DATA_S 0 //***************************************************************************** // @@ -28539,9 +28539,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11862_DATA_W 32 -#define RFC_ULLRAM_BANK11862_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11862_DATA_S 0 +#define RFC_ULLRAM_BANK11862_DATA_W 32 +#define RFC_ULLRAM_BANK11862_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11862_DATA_S 0 //***************************************************************************** // @@ -28551,9 +28551,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11863_DATA_W 32 -#define RFC_ULLRAM_BANK11863_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11863_DATA_S 0 +#define RFC_ULLRAM_BANK11863_DATA_W 32 +#define RFC_ULLRAM_BANK11863_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11863_DATA_S 0 //***************************************************************************** // @@ -28563,9 +28563,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11864_DATA_W 32 -#define RFC_ULLRAM_BANK11864_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11864_DATA_S 0 +#define RFC_ULLRAM_BANK11864_DATA_W 32 +#define RFC_ULLRAM_BANK11864_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11864_DATA_S 0 //***************************************************************************** // @@ -28575,9 +28575,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11865_DATA_W 32 -#define RFC_ULLRAM_BANK11865_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11865_DATA_S 0 +#define RFC_ULLRAM_BANK11865_DATA_W 32 +#define RFC_ULLRAM_BANK11865_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11865_DATA_S 0 //***************************************************************************** // @@ -28587,9 +28587,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11866_DATA_W 32 -#define RFC_ULLRAM_BANK11866_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11866_DATA_S 0 +#define RFC_ULLRAM_BANK11866_DATA_W 32 +#define RFC_ULLRAM_BANK11866_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11866_DATA_S 0 //***************************************************************************** // @@ -28599,9 +28599,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11867_DATA_W 32 -#define RFC_ULLRAM_BANK11867_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11867_DATA_S 0 +#define RFC_ULLRAM_BANK11867_DATA_W 32 +#define RFC_ULLRAM_BANK11867_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11867_DATA_S 0 //***************************************************************************** // @@ -28611,9 +28611,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11868_DATA_W 32 -#define RFC_ULLRAM_BANK11868_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11868_DATA_S 0 +#define RFC_ULLRAM_BANK11868_DATA_W 32 +#define RFC_ULLRAM_BANK11868_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11868_DATA_S 0 //***************************************************************************** // @@ -28623,9 +28623,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11869_DATA_W 32 -#define RFC_ULLRAM_BANK11869_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11869_DATA_S 0 +#define RFC_ULLRAM_BANK11869_DATA_W 32 +#define RFC_ULLRAM_BANK11869_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11869_DATA_S 0 //***************************************************************************** // @@ -28635,9 +28635,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11870_DATA_W 32 -#define RFC_ULLRAM_BANK11870_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11870_DATA_S 0 +#define RFC_ULLRAM_BANK11870_DATA_W 32 +#define RFC_ULLRAM_BANK11870_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11870_DATA_S 0 //***************************************************************************** // @@ -28647,9 +28647,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11871_DATA_W 32 -#define RFC_ULLRAM_BANK11871_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11871_DATA_S 0 +#define RFC_ULLRAM_BANK11871_DATA_W 32 +#define RFC_ULLRAM_BANK11871_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11871_DATA_S 0 //***************************************************************************** // @@ -28659,9 +28659,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11872_DATA_W 32 -#define RFC_ULLRAM_BANK11872_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11872_DATA_S 0 +#define RFC_ULLRAM_BANK11872_DATA_W 32 +#define RFC_ULLRAM_BANK11872_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11872_DATA_S 0 //***************************************************************************** // @@ -28671,9 +28671,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11873_DATA_W 32 -#define RFC_ULLRAM_BANK11873_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11873_DATA_S 0 +#define RFC_ULLRAM_BANK11873_DATA_W 32 +#define RFC_ULLRAM_BANK11873_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11873_DATA_S 0 //***************************************************************************** // @@ -28683,9 +28683,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11874_DATA_W 32 -#define RFC_ULLRAM_BANK11874_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11874_DATA_S 0 +#define RFC_ULLRAM_BANK11874_DATA_W 32 +#define RFC_ULLRAM_BANK11874_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11874_DATA_S 0 //***************************************************************************** // @@ -28695,9 +28695,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11875_DATA_W 32 -#define RFC_ULLRAM_BANK11875_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11875_DATA_S 0 +#define RFC_ULLRAM_BANK11875_DATA_W 32 +#define RFC_ULLRAM_BANK11875_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11875_DATA_S 0 //***************************************************************************** // @@ -28707,9 +28707,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11876_DATA_W 32 -#define RFC_ULLRAM_BANK11876_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11876_DATA_S 0 +#define RFC_ULLRAM_BANK11876_DATA_W 32 +#define RFC_ULLRAM_BANK11876_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11876_DATA_S 0 //***************************************************************************** // @@ -28719,9 +28719,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11877_DATA_W 32 -#define RFC_ULLRAM_BANK11877_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11877_DATA_S 0 +#define RFC_ULLRAM_BANK11877_DATA_W 32 +#define RFC_ULLRAM_BANK11877_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11877_DATA_S 0 //***************************************************************************** // @@ -28731,9 +28731,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11878_DATA_W 32 -#define RFC_ULLRAM_BANK11878_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11878_DATA_S 0 +#define RFC_ULLRAM_BANK11878_DATA_W 32 +#define RFC_ULLRAM_BANK11878_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11878_DATA_S 0 //***************************************************************************** // @@ -28743,9 +28743,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11879_DATA_W 32 -#define RFC_ULLRAM_BANK11879_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11879_DATA_S 0 +#define RFC_ULLRAM_BANK11879_DATA_W 32 +#define RFC_ULLRAM_BANK11879_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11879_DATA_S 0 //***************************************************************************** // @@ -28755,9 +28755,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11880_DATA_W 32 -#define RFC_ULLRAM_BANK11880_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11880_DATA_S 0 +#define RFC_ULLRAM_BANK11880_DATA_W 32 +#define RFC_ULLRAM_BANK11880_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11880_DATA_S 0 //***************************************************************************** // @@ -28767,9 +28767,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11881_DATA_W 32 -#define RFC_ULLRAM_BANK11881_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11881_DATA_S 0 +#define RFC_ULLRAM_BANK11881_DATA_W 32 +#define RFC_ULLRAM_BANK11881_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11881_DATA_S 0 //***************************************************************************** // @@ -28779,9 +28779,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11882_DATA_W 32 -#define RFC_ULLRAM_BANK11882_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11882_DATA_S 0 +#define RFC_ULLRAM_BANK11882_DATA_W 32 +#define RFC_ULLRAM_BANK11882_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11882_DATA_S 0 //***************************************************************************** // @@ -28791,9 +28791,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11883_DATA_W 32 -#define RFC_ULLRAM_BANK11883_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11883_DATA_S 0 +#define RFC_ULLRAM_BANK11883_DATA_W 32 +#define RFC_ULLRAM_BANK11883_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11883_DATA_S 0 //***************************************************************************** // @@ -28803,9 +28803,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11884_DATA_W 32 -#define RFC_ULLRAM_BANK11884_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11884_DATA_S 0 +#define RFC_ULLRAM_BANK11884_DATA_W 32 +#define RFC_ULLRAM_BANK11884_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11884_DATA_S 0 //***************************************************************************** // @@ -28815,9 +28815,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11885_DATA_W 32 -#define RFC_ULLRAM_BANK11885_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11885_DATA_S 0 +#define RFC_ULLRAM_BANK11885_DATA_W 32 +#define RFC_ULLRAM_BANK11885_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11885_DATA_S 0 //***************************************************************************** // @@ -28827,9 +28827,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11886_DATA_W 32 -#define RFC_ULLRAM_BANK11886_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11886_DATA_S 0 +#define RFC_ULLRAM_BANK11886_DATA_W 32 +#define RFC_ULLRAM_BANK11886_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11886_DATA_S 0 //***************************************************************************** // @@ -28839,9 +28839,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11887_DATA_W 32 -#define RFC_ULLRAM_BANK11887_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11887_DATA_S 0 +#define RFC_ULLRAM_BANK11887_DATA_W 32 +#define RFC_ULLRAM_BANK11887_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11887_DATA_S 0 //***************************************************************************** // @@ -28851,9 +28851,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11888_DATA_W 32 -#define RFC_ULLRAM_BANK11888_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11888_DATA_S 0 +#define RFC_ULLRAM_BANK11888_DATA_W 32 +#define RFC_ULLRAM_BANK11888_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11888_DATA_S 0 //***************************************************************************** // @@ -28863,9 +28863,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11889_DATA_W 32 -#define RFC_ULLRAM_BANK11889_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11889_DATA_S 0 +#define RFC_ULLRAM_BANK11889_DATA_W 32 +#define RFC_ULLRAM_BANK11889_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11889_DATA_S 0 //***************************************************************************** // @@ -28875,9 +28875,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11890_DATA_W 32 -#define RFC_ULLRAM_BANK11890_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11890_DATA_S 0 +#define RFC_ULLRAM_BANK11890_DATA_W 32 +#define RFC_ULLRAM_BANK11890_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11890_DATA_S 0 //***************************************************************************** // @@ -28887,9 +28887,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11891_DATA_W 32 -#define RFC_ULLRAM_BANK11891_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11891_DATA_S 0 +#define RFC_ULLRAM_BANK11891_DATA_W 32 +#define RFC_ULLRAM_BANK11891_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11891_DATA_S 0 //***************************************************************************** // @@ -28899,9 +28899,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11892_DATA_W 32 -#define RFC_ULLRAM_BANK11892_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11892_DATA_S 0 +#define RFC_ULLRAM_BANK11892_DATA_W 32 +#define RFC_ULLRAM_BANK11892_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11892_DATA_S 0 //***************************************************************************** // @@ -28911,9 +28911,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11893_DATA_W 32 -#define RFC_ULLRAM_BANK11893_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11893_DATA_S 0 +#define RFC_ULLRAM_BANK11893_DATA_W 32 +#define RFC_ULLRAM_BANK11893_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11893_DATA_S 0 //***************************************************************************** // @@ -28923,9 +28923,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11894_DATA_W 32 -#define RFC_ULLRAM_BANK11894_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11894_DATA_S 0 +#define RFC_ULLRAM_BANK11894_DATA_W 32 +#define RFC_ULLRAM_BANK11894_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11894_DATA_S 0 //***************************************************************************** // @@ -28935,9 +28935,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11895_DATA_W 32 -#define RFC_ULLRAM_BANK11895_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11895_DATA_S 0 +#define RFC_ULLRAM_BANK11895_DATA_W 32 +#define RFC_ULLRAM_BANK11895_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11895_DATA_S 0 //***************************************************************************** // @@ -28947,9 +28947,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11896_DATA_W 32 -#define RFC_ULLRAM_BANK11896_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11896_DATA_S 0 +#define RFC_ULLRAM_BANK11896_DATA_W 32 +#define RFC_ULLRAM_BANK11896_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11896_DATA_S 0 //***************************************************************************** // @@ -28959,9 +28959,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11897_DATA_W 32 -#define RFC_ULLRAM_BANK11897_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11897_DATA_S 0 +#define RFC_ULLRAM_BANK11897_DATA_W 32 +#define RFC_ULLRAM_BANK11897_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11897_DATA_S 0 //***************************************************************************** // @@ -28971,9 +28971,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11898_DATA_W 32 -#define RFC_ULLRAM_BANK11898_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11898_DATA_S 0 +#define RFC_ULLRAM_BANK11898_DATA_W 32 +#define RFC_ULLRAM_BANK11898_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11898_DATA_S 0 //***************************************************************************** // @@ -28983,9 +28983,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11899_DATA_W 32 -#define RFC_ULLRAM_BANK11899_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11899_DATA_S 0 +#define RFC_ULLRAM_BANK11899_DATA_W 32 +#define RFC_ULLRAM_BANK11899_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11899_DATA_S 0 //***************************************************************************** // @@ -28995,9 +28995,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11900_DATA_W 32 -#define RFC_ULLRAM_BANK11900_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11900_DATA_S 0 +#define RFC_ULLRAM_BANK11900_DATA_W 32 +#define RFC_ULLRAM_BANK11900_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11900_DATA_S 0 //***************************************************************************** // @@ -29007,9 +29007,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11901_DATA_W 32 -#define RFC_ULLRAM_BANK11901_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11901_DATA_S 0 +#define RFC_ULLRAM_BANK11901_DATA_W 32 +#define RFC_ULLRAM_BANK11901_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11901_DATA_S 0 //***************************************************************************** // @@ -29019,9 +29019,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11902_DATA_W 32 -#define RFC_ULLRAM_BANK11902_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11902_DATA_S 0 +#define RFC_ULLRAM_BANK11902_DATA_W 32 +#define RFC_ULLRAM_BANK11902_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11902_DATA_S 0 //***************************************************************************** // @@ -29031,9 +29031,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11903_DATA_W 32 -#define RFC_ULLRAM_BANK11903_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11903_DATA_S 0 +#define RFC_ULLRAM_BANK11903_DATA_W 32 +#define RFC_ULLRAM_BANK11903_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11903_DATA_S 0 //***************************************************************************** // @@ -29043,9 +29043,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11904_DATA_W 32 -#define RFC_ULLRAM_BANK11904_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11904_DATA_S 0 +#define RFC_ULLRAM_BANK11904_DATA_W 32 +#define RFC_ULLRAM_BANK11904_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11904_DATA_S 0 //***************************************************************************** // @@ -29055,9 +29055,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11905_DATA_W 32 -#define RFC_ULLRAM_BANK11905_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11905_DATA_S 0 +#define RFC_ULLRAM_BANK11905_DATA_W 32 +#define RFC_ULLRAM_BANK11905_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11905_DATA_S 0 //***************************************************************************** // @@ -29067,9 +29067,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11906_DATA_W 32 -#define RFC_ULLRAM_BANK11906_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11906_DATA_S 0 +#define RFC_ULLRAM_BANK11906_DATA_W 32 +#define RFC_ULLRAM_BANK11906_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11906_DATA_S 0 //***************************************************************************** // @@ -29079,9 +29079,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11907_DATA_W 32 -#define RFC_ULLRAM_BANK11907_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11907_DATA_S 0 +#define RFC_ULLRAM_BANK11907_DATA_W 32 +#define RFC_ULLRAM_BANK11907_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11907_DATA_S 0 //***************************************************************************** // @@ -29091,9 +29091,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11908_DATA_W 32 -#define RFC_ULLRAM_BANK11908_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11908_DATA_S 0 +#define RFC_ULLRAM_BANK11908_DATA_W 32 +#define RFC_ULLRAM_BANK11908_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11908_DATA_S 0 //***************************************************************************** // @@ -29103,9 +29103,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11909_DATA_W 32 -#define RFC_ULLRAM_BANK11909_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11909_DATA_S 0 +#define RFC_ULLRAM_BANK11909_DATA_W 32 +#define RFC_ULLRAM_BANK11909_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11909_DATA_S 0 //***************************************************************************** // @@ -29115,9 +29115,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11910_DATA_W 32 -#define RFC_ULLRAM_BANK11910_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11910_DATA_S 0 +#define RFC_ULLRAM_BANK11910_DATA_W 32 +#define RFC_ULLRAM_BANK11910_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11910_DATA_S 0 //***************************************************************************** // @@ -29127,9 +29127,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11911_DATA_W 32 -#define RFC_ULLRAM_BANK11911_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11911_DATA_S 0 +#define RFC_ULLRAM_BANK11911_DATA_W 32 +#define RFC_ULLRAM_BANK11911_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11911_DATA_S 0 //***************************************************************************** // @@ -29139,9 +29139,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11912_DATA_W 32 -#define RFC_ULLRAM_BANK11912_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11912_DATA_S 0 +#define RFC_ULLRAM_BANK11912_DATA_W 32 +#define RFC_ULLRAM_BANK11912_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11912_DATA_S 0 //***************************************************************************** // @@ -29151,9 +29151,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11913_DATA_W 32 -#define RFC_ULLRAM_BANK11913_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11913_DATA_S 0 +#define RFC_ULLRAM_BANK11913_DATA_W 32 +#define RFC_ULLRAM_BANK11913_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11913_DATA_S 0 //***************************************************************************** // @@ -29163,9 +29163,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11914_DATA_W 32 -#define RFC_ULLRAM_BANK11914_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11914_DATA_S 0 +#define RFC_ULLRAM_BANK11914_DATA_W 32 +#define RFC_ULLRAM_BANK11914_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11914_DATA_S 0 //***************************************************************************** // @@ -29175,9 +29175,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11915_DATA_W 32 -#define RFC_ULLRAM_BANK11915_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11915_DATA_S 0 +#define RFC_ULLRAM_BANK11915_DATA_W 32 +#define RFC_ULLRAM_BANK11915_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11915_DATA_S 0 //***************************************************************************** // @@ -29187,9 +29187,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11916_DATA_W 32 -#define RFC_ULLRAM_BANK11916_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11916_DATA_S 0 +#define RFC_ULLRAM_BANK11916_DATA_W 32 +#define RFC_ULLRAM_BANK11916_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11916_DATA_S 0 //***************************************************************************** // @@ -29199,9 +29199,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11917_DATA_W 32 -#define RFC_ULLRAM_BANK11917_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11917_DATA_S 0 +#define RFC_ULLRAM_BANK11917_DATA_W 32 +#define RFC_ULLRAM_BANK11917_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11917_DATA_S 0 //***************************************************************************** // @@ -29211,9 +29211,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11918_DATA_W 32 -#define RFC_ULLRAM_BANK11918_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11918_DATA_S 0 +#define RFC_ULLRAM_BANK11918_DATA_W 32 +#define RFC_ULLRAM_BANK11918_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11918_DATA_S 0 //***************************************************************************** // @@ -29223,9 +29223,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11919_DATA_W 32 -#define RFC_ULLRAM_BANK11919_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11919_DATA_S 0 +#define RFC_ULLRAM_BANK11919_DATA_W 32 +#define RFC_ULLRAM_BANK11919_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11919_DATA_S 0 //***************************************************************************** // @@ -29235,9 +29235,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11920_DATA_W 32 -#define RFC_ULLRAM_BANK11920_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11920_DATA_S 0 +#define RFC_ULLRAM_BANK11920_DATA_W 32 +#define RFC_ULLRAM_BANK11920_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11920_DATA_S 0 //***************************************************************************** // @@ -29247,9 +29247,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11921_DATA_W 32 -#define RFC_ULLRAM_BANK11921_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11921_DATA_S 0 +#define RFC_ULLRAM_BANK11921_DATA_W 32 +#define RFC_ULLRAM_BANK11921_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11921_DATA_S 0 //***************************************************************************** // @@ -29259,9 +29259,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11922_DATA_W 32 -#define RFC_ULLRAM_BANK11922_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11922_DATA_S 0 +#define RFC_ULLRAM_BANK11922_DATA_W 32 +#define RFC_ULLRAM_BANK11922_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11922_DATA_S 0 //***************************************************************************** // @@ -29271,9 +29271,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11923_DATA_W 32 -#define RFC_ULLRAM_BANK11923_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11923_DATA_S 0 +#define RFC_ULLRAM_BANK11923_DATA_W 32 +#define RFC_ULLRAM_BANK11923_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11923_DATA_S 0 //***************************************************************************** // @@ -29283,9 +29283,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11924_DATA_W 32 -#define RFC_ULLRAM_BANK11924_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11924_DATA_S 0 +#define RFC_ULLRAM_BANK11924_DATA_W 32 +#define RFC_ULLRAM_BANK11924_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11924_DATA_S 0 //***************************************************************************** // @@ -29295,9 +29295,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11925_DATA_W 32 -#define RFC_ULLRAM_BANK11925_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11925_DATA_S 0 +#define RFC_ULLRAM_BANK11925_DATA_W 32 +#define RFC_ULLRAM_BANK11925_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11925_DATA_S 0 //***************************************************************************** // @@ -29307,9 +29307,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11926_DATA_W 32 -#define RFC_ULLRAM_BANK11926_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11926_DATA_S 0 +#define RFC_ULLRAM_BANK11926_DATA_W 32 +#define RFC_ULLRAM_BANK11926_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11926_DATA_S 0 //***************************************************************************** // @@ -29319,9 +29319,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11927_DATA_W 32 -#define RFC_ULLRAM_BANK11927_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11927_DATA_S 0 +#define RFC_ULLRAM_BANK11927_DATA_W 32 +#define RFC_ULLRAM_BANK11927_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11927_DATA_S 0 //***************************************************************************** // @@ -29331,9 +29331,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11928_DATA_W 32 -#define RFC_ULLRAM_BANK11928_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11928_DATA_S 0 +#define RFC_ULLRAM_BANK11928_DATA_W 32 +#define RFC_ULLRAM_BANK11928_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11928_DATA_S 0 //***************************************************************************** // @@ -29343,9 +29343,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11929_DATA_W 32 -#define RFC_ULLRAM_BANK11929_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11929_DATA_S 0 +#define RFC_ULLRAM_BANK11929_DATA_W 32 +#define RFC_ULLRAM_BANK11929_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11929_DATA_S 0 //***************************************************************************** // @@ -29355,9 +29355,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11930_DATA_W 32 -#define RFC_ULLRAM_BANK11930_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11930_DATA_S 0 +#define RFC_ULLRAM_BANK11930_DATA_W 32 +#define RFC_ULLRAM_BANK11930_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11930_DATA_S 0 //***************************************************************************** // @@ -29367,9 +29367,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11931_DATA_W 32 -#define RFC_ULLRAM_BANK11931_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11931_DATA_S 0 +#define RFC_ULLRAM_BANK11931_DATA_W 32 +#define RFC_ULLRAM_BANK11931_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11931_DATA_S 0 //***************************************************************************** // @@ -29379,9 +29379,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11932_DATA_W 32 -#define RFC_ULLRAM_BANK11932_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11932_DATA_S 0 +#define RFC_ULLRAM_BANK11932_DATA_W 32 +#define RFC_ULLRAM_BANK11932_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11932_DATA_S 0 //***************************************************************************** // @@ -29391,9 +29391,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11933_DATA_W 32 -#define RFC_ULLRAM_BANK11933_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11933_DATA_S 0 +#define RFC_ULLRAM_BANK11933_DATA_W 32 +#define RFC_ULLRAM_BANK11933_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11933_DATA_S 0 //***************************************************************************** // @@ -29403,9 +29403,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11934_DATA_W 32 -#define RFC_ULLRAM_BANK11934_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11934_DATA_S 0 +#define RFC_ULLRAM_BANK11934_DATA_W 32 +#define RFC_ULLRAM_BANK11934_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11934_DATA_S 0 //***************************************************************************** // @@ -29415,9 +29415,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11935_DATA_W 32 -#define RFC_ULLRAM_BANK11935_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11935_DATA_S 0 +#define RFC_ULLRAM_BANK11935_DATA_W 32 +#define RFC_ULLRAM_BANK11935_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11935_DATA_S 0 //***************************************************************************** // @@ -29427,9 +29427,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11936_DATA_W 32 -#define RFC_ULLRAM_BANK11936_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11936_DATA_S 0 +#define RFC_ULLRAM_BANK11936_DATA_W 32 +#define RFC_ULLRAM_BANK11936_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11936_DATA_S 0 //***************************************************************************** // @@ -29439,9 +29439,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11937_DATA_W 32 -#define RFC_ULLRAM_BANK11937_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11937_DATA_S 0 +#define RFC_ULLRAM_BANK11937_DATA_W 32 +#define RFC_ULLRAM_BANK11937_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11937_DATA_S 0 //***************************************************************************** // @@ -29451,9 +29451,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11938_DATA_W 32 -#define RFC_ULLRAM_BANK11938_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11938_DATA_S 0 +#define RFC_ULLRAM_BANK11938_DATA_W 32 +#define RFC_ULLRAM_BANK11938_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11938_DATA_S 0 //***************************************************************************** // @@ -29463,9 +29463,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11939_DATA_W 32 -#define RFC_ULLRAM_BANK11939_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11939_DATA_S 0 +#define RFC_ULLRAM_BANK11939_DATA_W 32 +#define RFC_ULLRAM_BANK11939_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11939_DATA_S 0 //***************************************************************************** // @@ -29475,9 +29475,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11940_DATA_W 32 -#define RFC_ULLRAM_BANK11940_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11940_DATA_S 0 +#define RFC_ULLRAM_BANK11940_DATA_W 32 +#define RFC_ULLRAM_BANK11940_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11940_DATA_S 0 //***************************************************************************** // @@ -29487,9 +29487,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11941_DATA_W 32 -#define RFC_ULLRAM_BANK11941_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11941_DATA_S 0 +#define RFC_ULLRAM_BANK11941_DATA_W 32 +#define RFC_ULLRAM_BANK11941_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11941_DATA_S 0 //***************************************************************************** // @@ -29499,9 +29499,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11942_DATA_W 32 -#define RFC_ULLRAM_BANK11942_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11942_DATA_S 0 +#define RFC_ULLRAM_BANK11942_DATA_W 32 +#define RFC_ULLRAM_BANK11942_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11942_DATA_S 0 //***************************************************************************** // @@ -29511,9 +29511,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11943_DATA_W 32 -#define RFC_ULLRAM_BANK11943_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11943_DATA_S 0 +#define RFC_ULLRAM_BANK11943_DATA_W 32 +#define RFC_ULLRAM_BANK11943_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11943_DATA_S 0 //***************************************************************************** // @@ -29523,9 +29523,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11944_DATA_W 32 -#define RFC_ULLRAM_BANK11944_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11944_DATA_S 0 +#define RFC_ULLRAM_BANK11944_DATA_W 32 +#define RFC_ULLRAM_BANK11944_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11944_DATA_S 0 //***************************************************************************** // @@ -29535,9 +29535,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11945_DATA_W 32 -#define RFC_ULLRAM_BANK11945_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11945_DATA_S 0 +#define RFC_ULLRAM_BANK11945_DATA_W 32 +#define RFC_ULLRAM_BANK11945_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11945_DATA_S 0 //***************************************************************************** // @@ -29547,9 +29547,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11946_DATA_W 32 -#define RFC_ULLRAM_BANK11946_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11946_DATA_S 0 +#define RFC_ULLRAM_BANK11946_DATA_W 32 +#define RFC_ULLRAM_BANK11946_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11946_DATA_S 0 //***************************************************************************** // @@ -29559,9 +29559,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11947_DATA_W 32 -#define RFC_ULLRAM_BANK11947_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11947_DATA_S 0 +#define RFC_ULLRAM_BANK11947_DATA_W 32 +#define RFC_ULLRAM_BANK11947_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11947_DATA_S 0 //***************************************************************************** // @@ -29571,9 +29571,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11948_DATA_W 32 -#define RFC_ULLRAM_BANK11948_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11948_DATA_S 0 +#define RFC_ULLRAM_BANK11948_DATA_W 32 +#define RFC_ULLRAM_BANK11948_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11948_DATA_S 0 //***************************************************************************** // @@ -29583,9 +29583,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11949_DATA_W 32 -#define RFC_ULLRAM_BANK11949_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11949_DATA_S 0 +#define RFC_ULLRAM_BANK11949_DATA_W 32 +#define RFC_ULLRAM_BANK11949_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11949_DATA_S 0 //***************************************************************************** // @@ -29595,9 +29595,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11950_DATA_W 32 -#define RFC_ULLRAM_BANK11950_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11950_DATA_S 0 +#define RFC_ULLRAM_BANK11950_DATA_W 32 +#define RFC_ULLRAM_BANK11950_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11950_DATA_S 0 //***************************************************************************** // @@ -29607,9 +29607,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11951_DATA_W 32 -#define RFC_ULLRAM_BANK11951_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11951_DATA_S 0 +#define RFC_ULLRAM_BANK11951_DATA_W 32 +#define RFC_ULLRAM_BANK11951_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11951_DATA_S 0 //***************************************************************************** // @@ -29619,9 +29619,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11952_DATA_W 32 -#define RFC_ULLRAM_BANK11952_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11952_DATA_S 0 +#define RFC_ULLRAM_BANK11952_DATA_W 32 +#define RFC_ULLRAM_BANK11952_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11952_DATA_S 0 //***************************************************************************** // @@ -29631,9 +29631,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11953_DATA_W 32 -#define RFC_ULLRAM_BANK11953_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11953_DATA_S 0 +#define RFC_ULLRAM_BANK11953_DATA_W 32 +#define RFC_ULLRAM_BANK11953_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11953_DATA_S 0 //***************************************************************************** // @@ -29643,9 +29643,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11954_DATA_W 32 -#define RFC_ULLRAM_BANK11954_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11954_DATA_S 0 +#define RFC_ULLRAM_BANK11954_DATA_W 32 +#define RFC_ULLRAM_BANK11954_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11954_DATA_S 0 //***************************************************************************** // @@ -29655,9 +29655,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11955_DATA_W 32 -#define RFC_ULLRAM_BANK11955_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11955_DATA_S 0 +#define RFC_ULLRAM_BANK11955_DATA_W 32 +#define RFC_ULLRAM_BANK11955_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11955_DATA_S 0 //***************************************************************************** // @@ -29667,9 +29667,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11956_DATA_W 32 -#define RFC_ULLRAM_BANK11956_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11956_DATA_S 0 +#define RFC_ULLRAM_BANK11956_DATA_W 32 +#define RFC_ULLRAM_BANK11956_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11956_DATA_S 0 //***************************************************************************** // @@ -29679,9 +29679,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11957_DATA_W 32 -#define RFC_ULLRAM_BANK11957_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11957_DATA_S 0 +#define RFC_ULLRAM_BANK11957_DATA_W 32 +#define RFC_ULLRAM_BANK11957_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11957_DATA_S 0 //***************************************************************************** // @@ -29691,9 +29691,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11958_DATA_W 32 -#define RFC_ULLRAM_BANK11958_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11958_DATA_S 0 +#define RFC_ULLRAM_BANK11958_DATA_W 32 +#define RFC_ULLRAM_BANK11958_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11958_DATA_S 0 //***************************************************************************** // @@ -29703,9 +29703,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11959_DATA_W 32 -#define RFC_ULLRAM_BANK11959_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11959_DATA_S 0 +#define RFC_ULLRAM_BANK11959_DATA_W 32 +#define RFC_ULLRAM_BANK11959_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11959_DATA_S 0 //***************************************************************************** // @@ -29715,9 +29715,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11960_DATA_W 32 -#define RFC_ULLRAM_BANK11960_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11960_DATA_S 0 +#define RFC_ULLRAM_BANK11960_DATA_W 32 +#define RFC_ULLRAM_BANK11960_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11960_DATA_S 0 //***************************************************************************** // @@ -29727,9 +29727,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11961_DATA_W 32 -#define RFC_ULLRAM_BANK11961_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11961_DATA_S 0 +#define RFC_ULLRAM_BANK11961_DATA_W 32 +#define RFC_ULLRAM_BANK11961_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11961_DATA_S 0 //***************************************************************************** // @@ -29739,9 +29739,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11962_DATA_W 32 -#define RFC_ULLRAM_BANK11962_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11962_DATA_S 0 +#define RFC_ULLRAM_BANK11962_DATA_W 32 +#define RFC_ULLRAM_BANK11962_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11962_DATA_S 0 //***************************************************************************** // @@ -29751,9 +29751,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11963_DATA_W 32 -#define RFC_ULLRAM_BANK11963_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11963_DATA_S 0 +#define RFC_ULLRAM_BANK11963_DATA_W 32 +#define RFC_ULLRAM_BANK11963_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11963_DATA_S 0 //***************************************************************************** // @@ -29763,9 +29763,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11964_DATA_W 32 -#define RFC_ULLRAM_BANK11964_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11964_DATA_S 0 +#define RFC_ULLRAM_BANK11964_DATA_W 32 +#define RFC_ULLRAM_BANK11964_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11964_DATA_S 0 //***************************************************************************** // @@ -29775,9 +29775,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11965_DATA_W 32 -#define RFC_ULLRAM_BANK11965_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11965_DATA_S 0 +#define RFC_ULLRAM_BANK11965_DATA_W 32 +#define RFC_ULLRAM_BANK11965_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11965_DATA_S 0 //***************************************************************************** // @@ -29787,9 +29787,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11966_DATA_W 32 -#define RFC_ULLRAM_BANK11966_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11966_DATA_S 0 +#define RFC_ULLRAM_BANK11966_DATA_W 32 +#define RFC_ULLRAM_BANK11966_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11966_DATA_S 0 //***************************************************************************** // @@ -29799,9 +29799,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11967_DATA_W 32 -#define RFC_ULLRAM_BANK11967_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11967_DATA_S 0 +#define RFC_ULLRAM_BANK11967_DATA_W 32 +#define RFC_ULLRAM_BANK11967_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11967_DATA_S 0 //***************************************************************************** // @@ -29811,9 +29811,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11968_DATA_W 32 -#define RFC_ULLRAM_BANK11968_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11968_DATA_S 0 +#define RFC_ULLRAM_BANK11968_DATA_W 32 +#define RFC_ULLRAM_BANK11968_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11968_DATA_S 0 //***************************************************************************** // @@ -29823,9 +29823,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11969_DATA_W 32 -#define RFC_ULLRAM_BANK11969_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11969_DATA_S 0 +#define RFC_ULLRAM_BANK11969_DATA_W 32 +#define RFC_ULLRAM_BANK11969_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11969_DATA_S 0 //***************************************************************************** // @@ -29835,9 +29835,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11970_DATA_W 32 -#define RFC_ULLRAM_BANK11970_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11970_DATA_S 0 +#define RFC_ULLRAM_BANK11970_DATA_W 32 +#define RFC_ULLRAM_BANK11970_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11970_DATA_S 0 //***************************************************************************** // @@ -29847,9 +29847,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11971_DATA_W 32 -#define RFC_ULLRAM_BANK11971_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11971_DATA_S 0 +#define RFC_ULLRAM_BANK11971_DATA_W 32 +#define RFC_ULLRAM_BANK11971_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11971_DATA_S 0 //***************************************************************************** // @@ -29859,9 +29859,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11972_DATA_W 32 -#define RFC_ULLRAM_BANK11972_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11972_DATA_S 0 +#define RFC_ULLRAM_BANK11972_DATA_W 32 +#define RFC_ULLRAM_BANK11972_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11972_DATA_S 0 //***************************************************************************** // @@ -29871,9 +29871,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11973_DATA_W 32 -#define RFC_ULLRAM_BANK11973_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11973_DATA_S 0 +#define RFC_ULLRAM_BANK11973_DATA_W 32 +#define RFC_ULLRAM_BANK11973_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11973_DATA_S 0 //***************************************************************************** // @@ -29883,9 +29883,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11974_DATA_W 32 -#define RFC_ULLRAM_BANK11974_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11974_DATA_S 0 +#define RFC_ULLRAM_BANK11974_DATA_W 32 +#define RFC_ULLRAM_BANK11974_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11974_DATA_S 0 //***************************************************************************** // @@ -29895,9 +29895,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11975_DATA_W 32 -#define RFC_ULLRAM_BANK11975_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11975_DATA_S 0 +#define RFC_ULLRAM_BANK11975_DATA_W 32 +#define RFC_ULLRAM_BANK11975_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11975_DATA_S 0 //***************************************************************************** // @@ -29907,9 +29907,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11976_DATA_W 32 -#define RFC_ULLRAM_BANK11976_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11976_DATA_S 0 +#define RFC_ULLRAM_BANK11976_DATA_W 32 +#define RFC_ULLRAM_BANK11976_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11976_DATA_S 0 //***************************************************************************** // @@ -29919,9 +29919,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11977_DATA_W 32 -#define RFC_ULLRAM_BANK11977_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11977_DATA_S 0 +#define RFC_ULLRAM_BANK11977_DATA_W 32 +#define RFC_ULLRAM_BANK11977_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11977_DATA_S 0 //***************************************************************************** // @@ -29931,9 +29931,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11978_DATA_W 32 -#define RFC_ULLRAM_BANK11978_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11978_DATA_S 0 +#define RFC_ULLRAM_BANK11978_DATA_W 32 +#define RFC_ULLRAM_BANK11978_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11978_DATA_S 0 //***************************************************************************** // @@ -29943,9 +29943,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11979_DATA_W 32 -#define RFC_ULLRAM_BANK11979_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11979_DATA_S 0 +#define RFC_ULLRAM_BANK11979_DATA_W 32 +#define RFC_ULLRAM_BANK11979_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11979_DATA_S 0 //***************************************************************************** // @@ -29955,9 +29955,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11980_DATA_W 32 -#define RFC_ULLRAM_BANK11980_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11980_DATA_S 0 +#define RFC_ULLRAM_BANK11980_DATA_W 32 +#define RFC_ULLRAM_BANK11980_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11980_DATA_S 0 //***************************************************************************** // @@ -29967,9 +29967,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11981_DATA_W 32 -#define RFC_ULLRAM_BANK11981_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11981_DATA_S 0 +#define RFC_ULLRAM_BANK11981_DATA_W 32 +#define RFC_ULLRAM_BANK11981_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11981_DATA_S 0 //***************************************************************************** // @@ -29979,9 +29979,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11982_DATA_W 32 -#define RFC_ULLRAM_BANK11982_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11982_DATA_S 0 +#define RFC_ULLRAM_BANK11982_DATA_W 32 +#define RFC_ULLRAM_BANK11982_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11982_DATA_S 0 //***************************************************************************** // @@ -29991,9 +29991,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11983_DATA_W 32 -#define RFC_ULLRAM_BANK11983_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11983_DATA_S 0 +#define RFC_ULLRAM_BANK11983_DATA_W 32 +#define RFC_ULLRAM_BANK11983_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11983_DATA_S 0 //***************************************************************************** // @@ -30003,9 +30003,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11984_DATA_W 32 -#define RFC_ULLRAM_BANK11984_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11984_DATA_S 0 +#define RFC_ULLRAM_BANK11984_DATA_W 32 +#define RFC_ULLRAM_BANK11984_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11984_DATA_S 0 //***************************************************************************** // @@ -30015,9 +30015,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11985_DATA_W 32 -#define RFC_ULLRAM_BANK11985_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11985_DATA_S 0 +#define RFC_ULLRAM_BANK11985_DATA_W 32 +#define RFC_ULLRAM_BANK11985_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11985_DATA_S 0 //***************************************************************************** // @@ -30027,9 +30027,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11986_DATA_W 32 -#define RFC_ULLRAM_BANK11986_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11986_DATA_S 0 +#define RFC_ULLRAM_BANK11986_DATA_W 32 +#define RFC_ULLRAM_BANK11986_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11986_DATA_S 0 //***************************************************************************** // @@ -30039,9 +30039,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11987_DATA_W 32 -#define RFC_ULLRAM_BANK11987_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11987_DATA_S 0 +#define RFC_ULLRAM_BANK11987_DATA_W 32 +#define RFC_ULLRAM_BANK11987_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11987_DATA_S 0 //***************************************************************************** // @@ -30051,9 +30051,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11988_DATA_W 32 -#define RFC_ULLRAM_BANK11988_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11988_DATA_S 0 +#define RFC_ULLRAM_BANK11988_DATA_W 32 +#define RFC_ULLRAM_BANK11988_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11988_DATA_S 0 //***************************************************************************** // @@ -30063,9 +30063,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11989_DATA_W 32 -#define RFC_ULLRAM_BANK11989_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11989_DATA_S 0 +#define RFC_ULLRAM_BANK11989_DATA_W 32 +#define RFC_ULLRAM_BANK11989_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11989_DATA_S 0 //***************************************************************************** // @@ -30075,9 +30075,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11990_DATA_W 32 -#define RFC_ULLRAM_BANK11990_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11990_DATA_S 0 +#define RFC_ULLRAM_BANK11990_DATA_W 32 +#define RFC_ULLRAM_BANK11990_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11990_DATA_S 0 //***************************************************************************** // @@ -30087,9 +30087,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11991_DATA_W 32 -#define RFC_ULLRAM_BANK11991_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11991_DATA_S 0 +#define RFC_ULLRAM_BANK11991_DATA_W 32 +#define RFC_ULLRAM_BANK11991_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11991_DATA_S 0 //***************************************************************************** // @@ -30099,9 +30099,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11992_DATA_W 32 -#define RFC_ULLRAM_BANK11992_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11992_DATA_S 0 +#define RFC_ULLRAM_BANK11992_DATA_W 32 +#define RFC_ULLRAM_BANK11992_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11992_DATA_S 0 //***************************************************************************** // @@ -30111,9 +30111,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11993_DATA_W 32 -#define RFC_ULLRAM_BANK11993_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11993_DATA_S 0 +#define RFC_ULLRAM_BANK11993_DATA_W 32 +#define RFC_ULLRAM_BANK11993_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11993_DATA_S 0 //***************************************************************************** // @@ -30123,9 +30123,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11994_DATA_W 32 -#define RFC_ULLRAM_BANK11994_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11994_DATA_S 0 +#define RFC_ULLRAM_BANK11994_DATA_W 32 +#define RFC_ULLRAM_BANK11994_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11994_DATA_S 0 //***************************************************************************** // @@ -30135,9 +30135,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11995_DATA_W 32 -#define RFC_ULLRAM_BANK11995_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11995_DATA_S 0 +#define RFC_ULLRAM_BANK11995_DATA_W 32 +#define RFC_ULLRAM_BANK11995_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11995_DATA_S 0 //***************************************************************************** // @@ -30147,9 +30147,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11996_DATA_W 32 -#define RFC_ULLRAM_BANK11996_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11996_DATA_S 0 +#define RFC_ULLRAM_BANK11996_DATA_W 32 +#define RFC_ULLRAM_BANK11996_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11996_DATA_S 0 //***************************************************************************** // @@ -30159,9 +30159,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11997_DATA_W 32 -#define RFC_ULLRAM_BANK11997_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11997_DATA_S 0 +#define RFC_ULLRAM_BANK11997_DATA_W 32 +#define RFC_ULLRAM_BANK11997_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11997_DATA_S 0 //***************************************************************************** // @@ -30171,9 +30171,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11998_DATA_W 32 -#define RFC_ULLRAM_BANK11998_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11998_DATA_S 0 +#define RFC_ULLRAM_BANK11998_DATA_W 32 +#define RFC_ULLRAM_BANK11998_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11998_DATA_S 0 //***************************************************************************** // @@ -30183,9 +30183,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK11999_DATA_W 32 -#define RFC_ULLRAM_BANK11999_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11999_DATA_S 0 +#define RFC_ULLRAM_BANK11999_DATA_W 32 +#define RFC_ULLRAM_BANK11999_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK11999_DATA_S 0 //***************************************************************************** // @@ -30195,9 +30195,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12000_DATA_W 32 -#define RFC_ULLRAM_BANK12000_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12000_DATA_S 0 +#define RFC_ULLRAM_BANK12000_DATA_W 32 +#define RFC_ULLRAM_BANK12000_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12000_DATA_S 0 //***************************************************************************** // @@ -30207,9 +30207,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12001_DATA_W 32 -#define RFC_ULLRAM_BANK12001_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12001_DATA_S 0 +#define RFC_ULLRAM_BANK12001_DATA_W 32 +#define RFC_ULLRAM_BANK12001_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12001_DATA_S 0 //***************************************************************************** // @@ -30219,9 +30219,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12002_DATA_W 32 -#define RFC_ULLRAM_BANK12002_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12002_DATA_S 0 +#define RFC_ULLRAM_BANK12002_DATA_W 32 +#define RFC_ULLRAM_BANK12002_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12002_DATA_S 0 //***************************************************************************** // @@ -30231,9 +30231,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12003_DATA_W 32 -#define RFC_ULLRAM_BANK12003_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12003_DATA_S 0 +#define RFC_ULLRAM_BANK12003_DATA_W 32 +#define RFC_ULLRAM_BANK12003_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12003_DATA_S 0 //***************************************************************************** // @@ -30243,9 +30243,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12004_DATA_W 32 -#define RFC_ULLRAM_BANK12004_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12004_DATA_S 0 +#define RFC_ULLRAM_BANK12004_DATA_W 32 +#define RFC_ULLRAM_BANK12004_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12004_DATA_S 0 //***************************************************************************** // @@ -30255,9 +30255,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12005_DATA_W 32 -#define RFC_ULLRAM_BANK12005_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12005_DATA_S 0 +#define RFC_ULLRAM_BANK12005_DATA_W 32 +#define RFC_ULLRAM_BANK12005_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12005_DATA_S 0 //***************************************************************************** // @@ -30267,9 +30267,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12006_DATA_W 32 -#define RFC_ULLRAM_BANK12006_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12006_DATA_S 0 +#define RFC_ULLRAM_BANK12006_DATA_W 32 +#define RFC_ULLRAM_BANK12006_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12006_DATA_S 0 //***************************************************************************** // @@ -30279,9 +30279,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12007_DATA_W 32 -#define RFC_ULLRAM_BANK12007_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12007_DATA_S 0 +#define RFC_ULLRAM_BANK12007_DATA_W 32 +#define RFC_ULLRAM_BANK12007_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12007_DATA_S 0 //***************************************************************************** // @@ -30291,9 +30291,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12008_DATA_W 32 -#define RFC_ULLRAM_BANK12008_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12008_DATA_S 0 +#define RFC_ULLRAM_BANK12008_DATA_W 32 +#define RFC_ULLRAM_BANK12008_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12008_DATA_S 0 //***************************************************************************** // @@ -30303,9 +30303,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12009_DATA_W 32 -#define RFC_ULLRAM_BANK12009_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12009_DATA_S 0 +#define RFC_ULLRAM_BANK12009_DATA_W 32 +#define RFC_ULLRAM_BANK12009_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12009_DATA_S 0 //***************************************************************************** // @@ -30315,9 +30315,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12010_DATA_W 32 -#define RFC_ULLRAM_BANK12010_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12010_DATA_S 0 +#define RFC_ULLRAM_BANK12010_DATA_W 32 +#define RFC_ULLRAM_BANK12010_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12010_DATA_S 0 //***************************************************************************** // @@ -30327,9 +30327,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12011_DATA_W 32 -#define RFC_ULLRAM_BANK12011_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12011_DATA_S 0 +#define RFC_ULLRAM_BANK12011_DATA_W 32 +#define RFC_ULLRAM_BANK12011_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12011_DATA_S 0 //***************************************************************************** // @@ -30339,9 +30339,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12012_DATA_W 32 -#define RFC_ULLRAM_BANK12012_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12012_DATA_S 0 +#define RFC_ULLRAM_BANK12012_DATA_W 32 +#define RFC_ULLRAM_BANK12012_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12012_DATA_S 0 //***************************************************************************** // @@ -30351,9 +30351,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12013_DATA_W 32 -#define RFC_ULLRAM_BANK12013_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12013_DATA_S 0 +#define RFC_ULLRAM_BANK12013_DATA_W 32 +#define RFC_ULLRAM_BANK12013_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12013_DATA_S 0 //***************************************************************************** // @@ -30363,9 +30363,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12014_DATA_W 32 -#define RFC_ULLRAM_BANK12014_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12014_DATA_S 0 +#define RFC_ULLRAM_BANK12014_DATA_W 32 +#define RFC_ULLRAM_BANK12014_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12014_DATA_S 0 //***************************************************************************** // @@ -30375,9 +30375,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12015_DATA_W 32 -#define RFC_ULLRAM_BANK12015_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12015_DATA_S 0 +#define RFC_ULLRAM_BANK12015_DATA_W 32 +#define RFC_ULLRAM_BANK12015_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12015_DATA_S 0 //***************************************************************************** // @@ -30387,9 +30387,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12016_DATA_W 32 -#define RFC_ULLRAM_BANK12016_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12016_DATA_S 0 +#define RFC_ULLRAM_BANK12016_DATA_W 32 +#define RFC_ULLRAM_BANK12016_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12016_DATA_S 0 //***************************************************************************** // @@ -30399,9 +30399,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12017_DATA_W 32 -#define RFC_ULLRAM_BANK12017_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12017_DATA_S 0 +#define RFC_ULLRAM_BANK12017_DATA_W 32 +#define RFC_ULLRAM_BANK12017_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12017_DATA_S 0 //***************************************************************************** // @@ -30411,9 +30411,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12018_DATA_W 32 -#define RFC_ULLRAM_BANK12018_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12018_DATA_S 0 +#define RFC_ULLRAM_BANK12018_DATA_W 32 +#define RFC_ULLRAM_BANK12018_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12018_DATA_S 0 //***************************************************************************** // @@ -30423,9 +30423,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12019_DATA_W 32 -#define RFC_ULLRAM_BANK12019_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12019_DATA_S 0 +#define RFC_ULLRAM_BANK12019_DATA_W 32 +#define RFC_ULLRAM_BANK12019_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12019_DATA_S 0 //***************************************************************************** // @@ -30435,9 +30435,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12020_DATA_W 32 -#define RFC_ULLRAM_BANK12020_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12020_DATA_S 0 +#define RFC_ULLRAM_BANK12020_DATA_W 32 +#define RFC_ULLRAM_BANK12020_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12020_DATA_S 0 //***************************************************************************** // @@ -30447,9 +30447,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12021_DATA_W 32 -#define RFC_ULLRAM_BANK12021_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12021_DATA_S 0 +#define RFC_ULLRAM_BANK12021_DATA_W 32 +#define RFC_ULLRAM_BANK12021_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12021_DATA_S 0 //***************************************************************************** // @@ -30459,9 +30459,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12022_DATA_W 32 -#define RFC_ULLRAM_BANK12022_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12022_DATA_S 0 +#define RFC_ULLRAM_BANK12022_DATA_W 32 +#define RFC_ULLRAM_BANK12022_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12022_DATA_S 0 //***************************************************************************** // @@ -30471,9 +30471,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12023_DATA_W 32 -#define RFC_ULLRAM_BANK12023_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12023_DATA_S 0 +#define RFC_ULLRAM_BANK12023_DATA_W 32 +#define RFC_ULLRAM_BANK12023_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12023_DATA_S 0 //***************************************************************************** // @@ -30483,9 +30483,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12024_DATA_W 32 -#define RFC_ULLRAM_BANK12024_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12024_DATA_S 0 +#define RFC_ULLRAM_BANK12024_DATA_W 32 +#define RFC_ULLRAM_BANK12024_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12024_DATA_S 0 //***************************************************************************** // @@ -30495,9 +30495,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12025_DATA_W 32 -#define RFC_ULLRAM_BANK12025_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12025_DATA_S 0 +#define RFC_ULLRAM_BANK12025_DATA_W 32 +#define RFC_ULLRAM_BANK12025_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12025_DATA_S 0 //***************************************************************************** // @@ -30507,9 +30507,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12026_DATA_W 32 -#define RFC_ULLRAM_BANK12026_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12026_DATA_S 0 +#define RFC_ULLRAM_BANK12026_DATA_W 32 +#define RFC_ULLRAM_BANK12026_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12026_DATA_S 0 //***************************************************************************** // @@ -30519,9 +30519,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12027_DATA_W 32 -#define RFC_ULLRAM_BANK12027_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12027_DATA_S 0 +#define RFC_ULLRAM_BANK12027_DATA_W 32 +#define RFC_ULLRAM_BANK12027_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12027_DATA_S 0 //***************************************************************************** // @@ -30531,9 +30531,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12028_DATA_W 32 -#define RFC_ULLRAM_BANK12028_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12028_DATA_S 0 +#define RFC_ULLRAM_BANK12028_DATA_W 32 +#define RFC_ULLRAM_BANK12028_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12028_DATA_S 0 //***************************************************************************** // @@ -30543,9 +30543,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12029_DATA_W 32 -#define RFC_ULLRAM_BANK12029_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12029_DATA_S 0 +#define RFC_ULLRAM_BANK12029_DATA_W 32 +#define RFC_ULLRAM_BANK12029_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12029_DATA_S 0 //***************************************************************************** // @@ -30555,9 +30555,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12030_DATA_W 32 -#define RFC_ULLRAM_BANK12030_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12030_DATA_S 0 +#define RFC_ULLRAM_BANK12030_DATA_W 32 +#define RFC_ULLRAM_BANK12030_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12030_DATA_S 0 //***************************************************************************** // @@ -30567,9 +30567,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12031_DATA_W 32 -#define RFC_ULLRAM_BANK12031_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12031_DATA_S 0 +#define RFC_ULLRAM_BANK12031_DATA_W 32 +#define RFC_ULLRAM_BANK12031_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12031_DATA_S 0 //***************************************************************************** // @@ -30579,9 +30579,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12032_DATA_W 32 -#define RFC_ULLRAM_BANK12032_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12032_DATA_S 0 +#define RFC_ULLRAM_BANK12032_DATA_W 32 +#define RFC_ULLRAM_BANK12032_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12032_DATA_S 0 //***************************************************************************** // @@ -30591,9 +30591,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12033_DATA_W 32 -#define RFC_ULLRAM_BANK12033_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12033_DATA_S 0 +#define RFC_ULLRAM_BANK12033_DATA_W 32 +#define RFC_ULLRAM_BANK12033_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12033_DATA_S 0 //***************************************************************************** // @@ -30603,9 +30603,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12034_DATA_W 32 -#define RFC_ULLRAM_BANK12034_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12034_DATA_S 0 +#define RFC_ULLRAM_BANK12034_DATA_W 32 +#define RFC_ULLRAM_BANK12034_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12034_DATA_S 0 //***************************************************************************** // @@ -30615,9 +30615,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12035_DATA_W 32 -#define RFC_ULLRAM_BANK12035_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12035_DATA_S 0 +#define RFC_ULLRAM_BANK12035_DATA_W 32 +#define RFC_ULLRAM_BANK12035_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12035_DATA_S 0 //***************************************************************************** // @@ -30627,9 +30627,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12036_DATA_W 32 -#define RFC_ULLRAM_BANK12036_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12036_DATA_S 0 +#define RFC_ULLRAM_BANK12036_DATA_W 32 +#define RFC_ULLRAM_BANK12036_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12036_DATA_S 0 //***************************************************************************** // @@ -30639,9 +30639,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12037_DATA_W 32 -#define RFC_ULLRAM_BANK12037_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12037_DATA_S 0 +#define RFC_ULLRAM_BANK12037_DATA_W 32 +#define RFC_ULLRAM_BANK12037_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12037_DATA_S 0 //***************************************************************************** // @@ -30651,9 +30651,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12038_DATA_W 32 -#define RFC_ULLRAM_BANK12038_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12038_DATA_S 0 +#define RFC_ULLRAM_BANK12038_DATA_W 32 +#define RFC_ULLRAM_BANK12038_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12038_DATA_S 0 //***************************************************************************** // @@ -30663,9 +30663,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12039_DATA_W 32 -#define RFC_ULLRAM_BANK12039_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12039_DATA_S 0 +#define RFC_ULLRAM_BANK12039_DATA_W 32 +#define RFC_ULLRAM_BANK12039_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12039_DATA_S 0 //***************************************************************************** // @@ -30675,9 +30675,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12040_DATA_W 32 -#define RFC_ULLRAM_BANK12040_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12040_DATA_S 0 +#define RFC_ULLRAM_BANK12040_DATA_W 32 +#define RFC_ULLRAM_BANK12040_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12040_DATA_S 0 //***************************************************************************** // @@ -30687,9 +30687,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12041_DATA_W 32 -#define RFC_ULLRAM_BANK12041_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12041_DATA_S 0 +#define RFC_ULLRAM_BANK12041_DATA_W 32 +#define RFC_ULLRAM_BANK12041_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12041_DATA_S 0 //***************************************************************************** // @@ -30699,9 +30699,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12042_DATA_W 32 -#define RFC_ULLRAM_BANK12042_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12042_DATA_S 0 +#define RFC_ULLRAM_BANK12042_DATA_W 32 +#define RFC_ULLRAM_BANK12042_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12042_DATA_S 0 //***************************************************************************** // @@ -30711,9 +30711,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12043_DATA_W 32 -#define RFC_ULLRAM_BANK12043_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12043_DATA_S 0 +#define RFC_ULLRAM_BANK12043_DATA_W 32 +#define RFC_ULLRAM_BANK12043_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12043_DATA_S 0 //***************************************************************************** // @@ -30723,9 +30723,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12044_DATA_W 32 -#define RFC_ULLRAM_BANK12044_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12044_DATA_S 0 +#define RFC_ULLRAM_BANK12044_DATA_W 32 +#define RFC_ULLRAM_BANK12044_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12044_DATA_S 0 //***************************************************************************** // @@ -30735,9 +30735,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12045_DATA_W 32 -#define RFC_ULLRAM_BANK12045_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12045_DATA_S 0 +#define RFC_ULLRAM_BANK12045_DATA_W 32 +#define RFC_ULLRAM_BANK12045_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12045_DATA_S 0 //***************************************************************************** // @@ -30747,9 +30747,9 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12046_DATA_W 32 -#define RFC_ULLRAM_BANK12046_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12046_DATA_S 0 +#define RFC_ULLRAM_BANK12046_DATA_W 32 +#define RFC_ULLRAM_BANK12046_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12046_DATA_S 0 //***************************************************************************** // @@ -30759,9 +30759,8 @@ // Field: [31:0] DATA // // SRAM data -#define RFC_ULLRAM_BANK12047_DATA_W 32 -#define RFC_ULLRAM_BANK12047_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12047_DATA_S 0 - +#define RFC_ULLRAM_BANK12047_DATA_W 32 +#define RFC_ULLRAM_BANK12047_DATA_M 0xFFFFFFFF +#define RFC_ULLRAM_BANK12047_DATA_S 0 #endif // __RFC_ULLRAM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_smph.h index c111576..76d92cb 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_smph.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_smph.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_smph_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_smph_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_SMPH_H__ #define __HW_SMPH_H__ @@ -44,196 +44,196 @@ // //***************************************************************************** // MCU SEMAPHORE 0 -#define SMPH_O_SMPH0 0x00000000 +#define SMPH_O_SMPH0 0x00000000 // MCU SEMAPHORE 1 -#define SMPH_O_SMPH1 0x00000004 +#define SMPH_O_SMPH1 0x00000004 // MCU SEMAPHORE 2 -#define SMPH_O_SMPH2 0x00000008 +#define SMPH_O_SMPH2 0x00000008 // MCU SEMAPHORE 3 -#define SMPH_O_SMPH3 0x0000000C +#define SMPH_O_SMPH3 0x0000000C // MCU SEMAPHORE 4 -#define SMPH_O_SMPH4 0x00000010 +#define SMPH_O_SMPH4 0x00000010 // MCU SEMAPHORE 5 -#define SMPH_O_SMPH5 0x00000014 +#define SMPH_O_SMPH5 0x00000014 // MCU SEMAPHORE 6 -#define SMPH_O_SMPH6 0x00000018 +#define SMPH_O_SMPH6 0x00000018 // MCU SEMAPHORE 7 -#define SMPH_O_SMPH7 0x0000001C +#define SMPH_O_SMPH7 0x0000001C // MCU SEMAPHORE 8 -#define SMPH_O_SMPH8 0x00000020 +#define SMPH_O_SMPH8 0x00000020 // MCU SEMAPHORE 9 -#define SMPH_O_SMPH9 0x00000024 +#define SMPH_O_SMPH9 0x00000024 // MCU SEMAPHORE 10 -#define SMPH_O_SMPH10 0x00000028 +#define SMPH_O_SMPH10 0x00000028 // MCU SEMAPHORE 11 -#define SMPH_O_SMPH11 0x0000002C +#define SMPH_O_SMPH11 0x0000002C // MCU SEMAPHORE 12 -#define SMPH_O_SMPH12 0x00000030 +#define SMPH_O_SMPH12 0x00000030 // MCU SEMAPHORE 13 -#define SMPH_O_SMPH13 0x00000034 +#define SMPH_O_SMPH13 0x00000034 // MCU SEMAPHORE 14 -#define SMPH_O_SMPH14 0x00000038 +#define SMPH_O_SMPH14 0x00000038 // MCU SEMAPHORE 15 -#define SMPH_O_SMPH15 0x0000003C +#define SMPH_O_SMPH15 0x0000003C // MCU SEMAPHORE 16 -#define SMPH_O_SMPH16 0x00000040 +#define SMPH_O_SMPH16 0x00000040 // MCU SEMAPHORE 17 -#define SMPH_O_SMPH17 0x00000044 +#define SMPH_O_SMPH17 0x00000044 // MCU SEMAPHORE 18 -#define SMPH_O_SMPH18 0x00000048 +#define SMPH_O_SMPH18 0x00000048 // MCU SEMAPHORE 19 -#define SMPH_O_SMPH19 0x0000004C +#define SMPH_O_SMPH19 0x0000004C // MCU SEMAPHORE 20 -#define SMPH_O_SMPH20 0x00000050 +#define SMPH_O_SMPH20 0x00000050 // MCU SEMAPHORE 21 -#define SMPH_O_SMPH21 0x00000054 +#define SMPH_O_SMPH21 0x00000054 // MCU SEMAPHORE 22 -#define SMPH_O_SMPH22 0x00000058 +#define SMPH_O_SMPH22 0x00000058 // MCU SEMAPHORE 23 -#define SMPH_O_SMPH23 0x0000005C +#define SMPH_O_SMPH23 0x0000005C // MCU SEMAPHORE 24 -#define SMPH_O_SMPH24 0x00000060 +#define SMPH_O_SMPH24 0x00000060 // MCU SEMAPHORE 25 -#define SMPH_O_SMPH25 0x00000064 +#define SMPH_O_SMPH25 0x00000064 // MCU SEMAPHORE 26 -#define SMPH_O_SMPH26 0x00000068 +#define SMPH_O_SMPH26 0x00000068 // MCU SEMAPHORE 27 -#define SMPH_O_SMPH27 0x0000006C +#define SMPH_O_SMPH27 0x0000006C // MCU SEMAPHORE 28 -#define SMPH_O_SMPH28 0x00000070 +#define SMPH_O_SMPH28 0x00000070 // MCU SEMAPHORE 29 -#define SMPH_O_SMPH29 0x00000074 +#define SMPH_O_SMPH29 0x00000074 // MCU SEMAPHORE 30 -#define SMPH_O_SMPH30 0x00000078 +#define SMPH_O_SMPH30 0x00000078 // MCU SEMAPHORE 31 -#define SMPH_O_SMPH31 0x0000007C +#define SMPH_O_SMPH31 0x0000007C // MCU SEMAPHORE 0 ALIAS -#define SMPH_O_PEEK0 0x00000800 +#define SMPH_O_PEEK0 0x00000800 // MCU SEMAPHORE 1 ALIAS -#define SMPH_O_PEEK1 0x00000804 +#define SMPH_O_PEEK1 0x00000804 // MCU SEMAPHORE 2 ALIAS -#define SMPH_O_PEEK2 0x00000808 +#define SMPH_O_PEEK2 0x00000808 // MCU SEMAPHORE 3 ALIAS -#define SMPH_O_PEEK3 0x0000080C +#define SMPH_O_PEEK3 0x0000080C // MCU SEMAPHORE 4 ALIAS -#define SMPH_O_PEEK4 0x00000810 +#define SMPH_O_PEEK4 0x00000810 // MCU SEMAPHORE 5 ALIAS -#define SMPH_O_PEEK5 0x00000814 +#define SMPH_O_PEEK5 0x00000814 // MCU SEMAPHORE 6 ALIAS -#define SMPH_O_PEEK6 0x00000818 +#define SMPH_O_PEEK6 0x00000818 // MCU SEMAPHORE 7 ALIAS -#define SMPH_O_PEEK7 0x0000081C +#define SMPH_O_PEEK7 0x0000081C // MCU SEMAPHORE 8 ALIAS -#define SMPH_O_PEEK8 0x00000820 +#define SMPH_O_PEEK8 0x00000820 // MCU SEMAPHORE 9 ALIAS -#define SMPH_O_PEEK9 0x00000824 +#define SMPH_O_PEEK9 0x00000824 // MCU SEMAPHORE 10 ALIAS -#define SMPH_O_PEEK10 0x00000828 +#define SMPH_O_PEEK10 0x00000828 // MCU SEMAPHORE 11 ALIAS -#define SMPH_O_PEEK11 0x0000082C +#define SMPH_O_PEEK11 0x0000082C // MCU SEMAPHORE 12 ALIAS -#define SMPH_O_PEEK12 0x00000830 +#define SMPH_O_PEEK12 0x00000830 // MCU SEMAPHORE 13 ALIAS -#define SMPH_O_PEEK13 0x00000834 +#define SMPH_O_PEEK13 0x00000834 // MCU SEMAPHORE 14 ALIAS -#define SMPH_O_PEEK14 0x00000838 +#define SMPH_O_PEEK14 0x00000838 // MCU SEMAPHORE 15 ALIAS -#define SMPH_O_PEEK15 0x0000083C +#define SMPH_O_PEEK15 0x0000083C // MCU SEMAPHORE 16 ALIAS -#define SMPH_O_PEEK16 0x00000840 +#define SMPH_O_PEEK16 0x00000840 // MCU SEMAPHORE 17 ALIAS -#define SMPH_O_PEEK17 0x00000844 +#define SMPH_O_PEEK17 0x00000844 // MCU SEMAPHORE 18 ALIAS -#define SMPH_O_PEEK18 0x00000848 +#define SMPH_O_PEEK18 0x00000848 // MCU SEMAPHORE 19 ALIAS -#define SMPH_O_PEEK19 0x0000084C +#define SMPH_O_PEEK19 0x0000084C // MCU SEMAPHORE 20 ALIAS -#define SMPH_O_PEEK20 0x00000850 +#define SMPH_O_PEEK20 0x00000850 // MCU SEMAPHORE 21 ALIAS -#define SMPH_O_PEEK21 0x00000854 +#define SMPH_O_PEEK21 0x00000854 // MCU SEMAPHORE 22 ALIAS -#define SMPH_O_PEEK22 0x00000858 +#define SMPH_O_PEEK22 0x00000858 // MCU SEMAPHORE 23 ALIAS -#define SMPH_O_PEEK23 0x0000085C +#define SMPH_O_PEEK23 0x0000085C // MCU SEMAPHORE 24 ALIAS -#define SMPH_O_PEEK24 0x00000860 +#define SMPH_O_PEEK24 0x00000860 // MCU SEMAPHORE 25 ALIAS -#define SMPH_O_PEEK25 0x00000864 +#define SMPH_O_PEEK25 0x00000864 // MCU SEMAPHORE 26 ALIAS -#define SMPH_O_PEEK26 0x00000868 +#define SMPH_O_PEEK26 0x00000868 // MCU SEMAPHORE 27 ALIAS -#define SMPH_O_PEEK27 0x0000086C +#define SMPH_O_PEEK27 0x0000086C // MCU SEMAPHORE 28 ALIAS -#define SMPH_O_PEEK28 0x00000870 +#define SMPH_O_PEEK28 0x00000870 // MCU SEMAPHORE 29 ALIAS -#define SMPH_O_PEEK29 0x00000874 +#define SMPH_O_PEEK29 0x00000874 // MCU SEMAPHORE 30 ALIAS -#define SMPH_O_PEEK30 0x00000878 +#define SMPH_O_PEEK30 0x00000878 // MCU SEMAPHORE 31 ALIAS -#define SMPH_O_PEEK31 0x0000087C +#define SMPH_O_PEEK31 0x0000087C //***************************************************************************** // @@ -249,10 +249,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH0_STAT 0x00000001 -#define SMPH_SMPH0_STAT_BITN 0 -#define SMPH_SMPH0_STAT_M 0x00000001 -#define SMPH_SMPH0_STAT_S 0 +#define SMPH_SMPH0_STAT 0x00000001 +#define SMPH_SMPH0_STAT_BITN 0 +#define SMPH_SMPH0_STAT_M 0x00000001 +#define SMPH_SMPH0_STAT_S 0 //***************************************************************************** // @@ -268,10 +268,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH1_STAT 0x00000001 -#define SMPH_SMPH1_STAT_BITN 0 -#define SMPH_SMPH1_STAT_M 0x00000001 -#define SMPH_SMPH1_STAT_S 0 +#define SMPH_SMPH1_STAT 0x00000001 +#define SMPH_SMPH1_STAT_BITN 0 +#define SMPH_SMPH1_STAT_M 0x00000001 +#define SMPH_SMPH1_STAT_S 0 //***************************************************************************** // @@ -287,10 +287,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH2_STAT 0x00000001 -#define SMPH_SMPH2_STAT_BITN 0 -#define SMPH_SMPH2_STAT_M 0x00000001 -#define SMPH_SMPH2_STAT_S 0 +#define SMPH_SMPH2_STAT 0x00000001 +#define SMPH_SMPH2_STAT_BITN 0 +#define SMPH_SMPH2_STAT_M 0x00000001 +#define SMPH_SMPH2_STAT_S 0 //***************************************************************************** // @@ -306,10 +306,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH3_STAT 0x00000001 -#define SMPH_SMPH3_STAT_BITN 0 -#define SMPH_SMPH3_STAT_M 0x00000001 -#define SMPH_SMPH3_STAT_S 0 +#define SMPH_SMPH3_STAT 0x00000001 +#define SMPH_SMPH3_STAT_BITN 0 +#define SMPH_SMPH3_STAT_M 0x00000001 +#define SMPH_SMPH3_STAT_S 0 //***************************************************************************** // @@ -325,10 +325,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH4_STAT 0x00000001 -#define SMPH_SMPH4_STAT_BITN 0 -#define SMPH_SMPH4_STAT_M 0x00000001 -#define SMPH_SMPH4_STAT_S 0 +#define SMPH_SMPH4_STAT 0x00000001 +#define SMPH_SMPH4_STAT_BITN 0 +#define SMPH_SMPH4_STAT_M 0x00000001 +#define SMPH_SMPH4_STAT_S 0 //***************************************************************************** // @@ -344,10 +344,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH5_STAT 0x00000001 -#define SMPH_SMPH5_STAT_BITN 0 -#define SMPH_SMPH5_STAT_M 0x00000001 -#define SMPH_SMPH5_STAT_S 0 +#define SMPH_SMPH5_STAT 0x00000001 +#define SMPH_SMPH5_STAT_BITN 0 +#define SMPH_SMPH5_STAT_M 0x00000001 +#define SMPH_SMPH5_STAT_S 0 //***************************************************************************** // @@ -363,10 +363,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH6_STAT 0x00000001 -#define SMPH_SMPH6_STAT_BITN 0 -#define SMPH_SMPH6_STAT_M 0x00000001 -#define SMPH_SMPH6_STAT_S 0 +#define SMPH_SMPH6_STAT 0x00000001 +#define SMPH_SMPH6_STAT_BITN 0 +#define SMPH_SMPH6_STAT_M 0x00000001 +#define SMPH_SMPH6_STAT_S 0 //***************************************************************************** // @@ -382,10 +382,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH7_STAT 0x00000001 -#define SMPH_SMPH7_STAT_BITN 0 -#define SMPH_SMPH7_STAT_M 0x00000001 -#define SMPH_SMPH7_STAT_S 0 +#define SMPH_SMPH7_STAT 0x00000001 +#define SMPH_SMPH7_STAT_BITN 0 +#define SMPH_SMPH7_STAT_M 0x00000001 +#define SMPH_SMPH7_STAT_S 0 //***************************************************************************** // @@ -401,10 +401,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH8_STAT 0x00000001 -#define SMPH_SMPH8_STAT_BITN 0 -#define SMPH_SMPH8_STAT_M 0x00000001 -#define SMPH_SMPH8_STAT_S 0 +#define SMPH_SMPH8_STAT 0x00000001 +#define SMPH_SMPH8_STAT_BITN 0 +#define SMPH_SMPH8_STAT_M 0x00000001 +#define SMPH_SMPH8_STAT_S 0 //***************************************************************************** // @@ -420,10 +420,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH9_STAT 0x00000001 -#define SMPH_SMPH9_STAT_BITN 0 -#define SMPH_SMPH9_STAT_M 0x00000001 -#define SMPH_SMPH9_STAT_S 0 +#define SMPH_SMPH9_STAT 0x00000001 +#define SMPH_SMPH9_STAT_BITN 0 +#define SMPH_SMPH9_STAT_M 0x00000001 +#define SMPH_SMPH9_STAT_S 0 //***************************************************************************** // @@ -439,10 +439,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH10_STAT 0x00000001 -#define SMPH_SMPH10_STAT_BITN 0 -#define SMPH_SMPH10_STAT_M 0x00000001 -#define SMPH_SMPH10_STAT_S 0 +#define SMPH_SMPH10_STAT 0x00000001 +#define SMPH_SMPH10_STAT_BITN 0 +#define SMPH_SMPH10_STAT_M 0x00000001 +#define SMPH_SMPH10_STAT_S 0 //***************************************************************************** // @@ -458,10 +458,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH11_STAT 0x00000001 -#define SMPH_SMPH11_STAT_BITN 0 -#define SMPH_SMPH11_STAT_M 0x00000001 -#define SMPH_SMPH11_STAT_S 0 +#define SMPH_SMPH11_STAT 0x00000001 +#define SMPH_SMPH11_STAT_BITN 0 +#define SMPH_SMPH11_STAT_M 0x00000001 +#define SMPH_SMPH11_STAT_S 0 //***************************************************************************** // @@ -477,10 +477,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH12_STAT 0x00000001 -#define SMPH_SMPH12_STAT_BITN 0 -#define SMPH_SMPH12_STAT_M 0x00000001 -#define SMPH_SMPH12_STAT_S 0 +#define SMPH_SMPH12_STAT 0x00000001 +#define SMPH_SMPH12_STAT_BITN 0 +#define SMPH_SMPH12_STAT_M 0x00000001 +#define SMPH_SMPH12_STAT_S 0 //***************************************************************************** // @@ -496,10 +496,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH13_STAT 0x00000001 -#define SMPH_SMPH13_STAT_BITN 0 -#define SMPH_SMPH13_STAT_M 0x00000001 -#define SMPH_SMPH13_STAT_S 0 +#define SMPH_SMPH13_STAT 0x00000001 +#define SMPH_SMPH13_STAT_BITN 0 +#define SMPH_SMPH13_STAT_M 0x00000001 +#define SMPH_SMPH13_STAT_S 0 //***************************************************************************** // @@ -515,10 +515,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH14_STAT 0x00000001 -#define SMPH_SMPH14_STAT_BITN 0 -#define SMPH_SMPH14_STAT_M 0x00000001 -#define SMPH_SMPH14_STAT_S 0 +#define SMPH_SMPH14_STAT 0x00000001 +#define SMPH_SMPH14_STAT_BITN 0 +#define SMPH_SMPH14_STAT_M 0x00000001 +#define SMPH_SMPH14_STAT_S 0 //***************************************************************************** // @@ -534,10 +534,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH15_STAT 0x00000001 -#define SMPH_SMPH15_STAT_BITN 0 -#define SMPH_SMPH15_STAT_M 0x00000001 -#define SMPH_SMPH15_STAT_S 0 +#define SMPH_SMPH15_STAT 0x00000001 +#define SMPH_SMPH15_STAT_BITN 0 +#define SMPH_SMPH15_STAT_M 0x00000001 +#define SMPH_SMPH15_STAT_S 0 //***************************************************************************** // @@ -553,10 +553,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH16_STAT 0x00000001 -#define SMPH_SMPH16_STAT_BITN 0 -#define SMPH_SMPH16_STAT_M 0x00000001 -#define SMPH_SMPH16_STAT_S 0 +#define SMPH_SMPH16_STAT 0x00000001 +#define SMPH_SMPH16_STAT_BITN 0 +#define SMPH_SMPH16_STAT_M 0x00000001 +#define SMPH_SMPH16_STAT_S 0 //***************************************************************************** // @@ -572,10 +572,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH17_STAT 0x00000001 -#define SMPH_SMPH17_STAT_BITN 0 -#define SMPH_SMPH17_STAT_M 0x00000001 -#define SMPH_SMPH17_STAT_S 0 +#define SMPH_SMPH17_STAT 0x00000001 +#define SMPH_SMPH17_STAT_BITN 0 +#define SMPH_SMPH17_STAT_M 0x00000001 +#define SMPH_SMPH17_STAT_S 0 //***************************************************************************** // @@ -591,10 +591,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH18_STAT 0x00000001 -#define SMPH_SMPH18_STAT_BITN 0 -#define SMPH_SMPH18_STAT_M 0x00000001 -#define SMPH_SMPH18_STAT_S 0 +#define SMPH_SMPH18_STAT 0x00000001 +#define SMPH_SMPH18_STAT_BITN 0 +#define SMPH_SMPH18_STAT_M 0x00000001 +#define SMPH_SMPH18_STAT_S 0 //***************************************************************************** // @@ -610,10 +610,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH19_STAT 0x00000001 -#define SMPH_SMPH19_STAT_BITN 0 -#define SMPH_SMPH19_STAT_M 0x00000001 -#define SMPH_SMPH19_STAT_S 0 +#define SMPH_SMPH19_STAT 0x00000001 +#define SMPH_SMPH19_STAT_BITN 0 +#define SMPH_SMPH19_STAT_M 0x00000001 +#define SMPH_SMPH19_STAT_S 0 //***************************************************************************** // @@ -629,10 +629,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH20_STAT 0x00000001 -#define SMPH_SMPH20_STAT_BITN 0 -#define SMPH_SMPH20_STAT_M 0x00000001 -#define SMPH_SMPH20_STAT_S 0 +#define SMPH_SMPH20_STAT 0x00000001 +#define SMPH_SMPH20_STAT_BITN 0 +#define SMPH_SMPH20_STAT_M 0x00000001 +#define SMPH_SMPH20_STAT_S 0 //***************************************************************************** // @@ -648,10 +648,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH21_STAT 0x00000001 -#define SMPH_SMPH21_STAT_BITN 0 -#define SMPH_SMPH21_STAT_M 0x00000001 -#define SMPH_SMPH21_STAT_S 0 +#define SMPH_SMPH21_STAT 0x00000001 +#define SMPH_SMPH21_STAT_BITN 0 +#define SMPH_SMPH21_STAT_M 0x00000001 +#define SMPH_SMPH21_STAT_S 0 //***************************************************************************** // @@ -667,10 +667,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH22_STAT 0x00000001 -#define SMPH_SMPH22_STAT_BITN 0 -#define SMPH_SMPH22_STAT_M 0x00000001 -#define SMPH_SMPH22_STAT_S 0 +#define SMPH_SMPH22_STAT 0x00000001 +#define SMPH_SMPH22_STAT_BITN 0 +#define SMPH_SMPH22_STAT_M 0x00000001 +#define SMPH_SMPH22_STAT_S 0 //***************************************************************************** // @@ -686,10 +686,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH23_STAT 0x00000001 -#define SMPH_SMPH23_STAT_BITN 0 -#define SMPH_SMPH23_STAT_M 0x00000001 -#define SMPH_SMPH23_STAT_S 0 +#define SMPH_SMPH23_STAT 0x00000001 +#define SMPH_SMPH23_STAT_BITN 0 +#define SMPH_SMPH23_STAT_M 0x00000001 +#define SMPH_SMPH23_STAT_S 0 //***************************************************************************** // @@ -705,10 +705,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH24_STAT 0x00000001 -#define SMPH_SMPH24_STAT_BITN 0 -#define SMPH_SMPH24_STAT_M 0x00000001 -#define SMPH_SMPH24_STAT_S 0 +#define SMPH_SMPH24_STAT 0x00000001 +#define SMPH_SMPH24_STAT_BITN 0 +#define SMPH_SMPH24_STAT_M 0x00000001 +#define SMPH_SMPH24_STAT_S 0 //***************************************************************************** // @@ -724,10 +724,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH25_STAT 0x00000001 -#define SMPH_SMPH25_STAT_BITN 0 -#define SMPH_SMPH25_STAT_M 0x00000001 -#define SMPH_SMPH25_STAT_S 0 +#define SMPH_SMPH25_STAT 0x00000001 +#define SMPH_SMPH25_STAT_BITN 0 +#define SMPH_SMPH25_STAT_M 0x00000001 +#define SMPH_SMPH25_STAT_S 0 //***************************************************************************** // @@ -743,10 +743,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH26_STAT 0x00000001 -#define SMPH_SMPH26_STAT_BITN 0 -#define SMPH_SMPH26_STAT_M 0x00000001 -#define SMPH_SMPH26_STAT_S 0 +#define SMPH_SMPH26_STAT 0x00000001 +#define SMPH_SMPH26_STAT_BITN 0 +#define SMPH_SMPH26_STAT_M 0x00000001 +#define SMPH_SMPH26_STAT_S 0 //***************************************************************************** // @@ -762,10 +762,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH27_STAT 0x00000001 -#define SMPH_SMPH27_STAT_BITN 0 -#define SMPH_SMPH27_STAT_M 0x00000001 -#define SMPH_SMPH27_STAT_S 0 +#define SMPH_SMPH27_STAT 0x00000001 +#define SMPH_SMPH27_STAT_BITN 0 +#define SMPH_SMPH27_STAT_M 0x00000001 +#define SMPH_SMPH27_STAT_S 0 //***************************************************************************** // @@ -781,10 +781,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH28_STAT 0x00000001 -#define SMPH_SMPH28_STAT_BITN 0 -#define SMPH_SMPH28_STAT_M 0x00000001 -#define SMPH_SMPH28_STAT_S 0 +#define SMPH_SMPH28_STAT 0x00000001 +#define SMPH_SMPH28_STAT_BITN 0 +#define SMPH_SMPH28_STAT_M 0x00000001 +#define SMPH_SMPH28_STAT_S 0 //***************************************************************************** // @@ -800,10 +800,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH29_STAT 0x00000001 -#define SMPH_SMPH29_STAT_BITN 0 -#define SMPH_SMPH29_STAT_M 0x00000001 -#define SMPH_SMPH29_STAT_S 0 +#define SMPH_SMPH29_STAT 0x00000001 +#define SMPH_SMPH29_STAT_BITN 0 +#define SMPH_SMPH29_STAT_M 0x00000001 +#define SMPH_SMPH29_STAT_S 0 //***************************************************************************** // @@ -819,10 +819,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH30_STAT 0x00000001 -#define SMPH_SMPH30_STAT_BITN 0 -#define SMPH_SMPH30_STAT_M 0x00000001 -#define SMPH_SMPH30_STAT_S 0 +#define SMPH_SMPH30_STAT 0x00000001 +#define SMPH_SMPH30_STAT_BITN 0 +#define SMPH_SMPH30_STAT_M 0x00000001 +#define SMPH_SMPH30_STAT_S 0 //***************************************************************************** // @@ -838,10 +838,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH31_STAT 0x00000001 -#define SMPH_SMPH31_STAT_BITN 0 -#define SMPH_SMPH31_STAT_M 0x00000001 -#define SMPH_SMPH31_STAT_S 0 +#define SMPH_SMPH31_STAT 0x00000001 +#define SMPH_SMPH31_STAT_BITN 0 +#define SMPH_SMPH31_STAT_M 0x00000001 +#define SMPH_SMPH31_STAT_S 0 //***************************************************************************** // @@ -857,10 +857,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK0_STAT 0x00000001 -#define SMPH_PEEK0_STAT_BITN 0 -#define SMPH_PEEK0_STAT_M 0x00000001 -#define SMPH_PEEK0_STAT_S 0 +#define SMPH_PEEK0_STAT 0x00000001 +#define SMPH_PEEK0_STAT_BITN 0 +#define SMPH_PEEK0_STAT_M 0x00000001 +#define SMPH_PEEK0_STAT_S 0 //***************************************************************************** // @@ -876,10 +876,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK1_STAT 0x00000001 -#define SMPH_PEEK1_STAT_BITN 0 -#define SMPH_PEEK1_STAT_M 0x00000001 -#define SMPH_PEEK1_STAT_S 0 +#define SMPH_PEEK1_STAT 0x00000001 +#define SMPH_PEEK1_STAT_BITN 0 +#define SMPH_PEEK1_STAT_M 0x00000001 +#define SMPH_PEEK1_STAT_S 0 //***************************************************************************** // @@ -895,10 +895,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK2_STAT 0x00000001 -#define SMPH_PEEK2_STAT_BITN 0 -#define SMPH_PEEK2_STAT_M 0x00000001 -#define SMPH_PEEK2_STAT_S 0 +#define SMPH_PEEK2_STAT 0x00000001 +#define SMPH_PEEK2_STAT_BITN 0 +#define SMPH_PEEK2_STAT_M 0x00000001 +#define SMPH_PEEK2_STAT_S 0 //***************************************************************************** // @@ -914,10 +914,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK3_STAT 0x00000001 -#define SMPH_PEEK3_STAT_BITN 0 -#define SMPH_PEEK3_STAT_M 0x00000001 -#define SMPH_PEEK3_STAT_S 0 +#define SMPH_PEEK3_STAT 0x00000001 +#define SMPH_PEEK3_STAT_BITN 0 +#define SMPH_PEEK3_STAT_M 0x00000001 +#define SMPH_PEEK3_STAT_S 0 //***************************************************************************** // @@ -933,10 +933,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK4_STAT 0x00000001 -#define SMPH_PEEK4_STAT_BITN 0 -#define SMPH_PEEK4_STAT_M 0x00000001 -#define SMPH_PEEK4_STAT_S 0 +#define SMPH_PEEK4_STAT 0x00000001 +#define SMPH_PEEK4_STAT_BITN 0 +#define SMPH_PEEK4_STAT_M 0x00000001 +#define SMPH_PEEK4_STAT_S 0 //***************************************************************************** // @@ -952,10 +952,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK5_STAT 0x00000001 -#define SMPH_PEEK5_STAT_BITN 0 -#define SMPH_PEEK5_STAT_M 0x00000001 -#define SMPH_PEEK5_STAT_S 0 +#define SMPH_PEEK5_STAT 0x00000001 +#define SMPH_PEEK5_STAT_BITN 0 +#define SMPH_PEEK5_STAT_M 0x00000001 +#define SMPH_PEEK5_STAT_S 0 //***************************************************************************** // @@ -971,10 +971,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK6_STAT 0x00000001 -#define SMPH_PEEK6_STAT_BITN 0 -#define SMPH_PEEK6_STAT_M 0x00000001 -#define SMPH_PEEK6_STAT_S 0 +#define SMPH_PEEK6_STAT 0x00000001 +#define SMPH_PEEK6_STAT_BITN 0 +#define SMPH_PEEK6_STAT_M 0x00000001 +#define SMPH_PEEK6_STAT_S 0 //***************************************************************************** // @@ -990,10 +990,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK7_STAT 0x00000001 -#define SMPH_PEEK7_STAT_BITN 0 -#define SMPH_PEEK7_STAT_M 0x00000001 -#define SMPH_PEEK7_STAT_S 0 +#define SMPH_PEEK7_STAT 0x00000001 +#define SMPH_PEEK7_STAT_BITN 0 +#define SMPH_PEEK7_STAT_M 0x00000001 +#define SMPH_PEEK7_STAT_S 0 //***************************************************************************** // @@ -1009,10 +1009,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK8_STAT 0x00000001 -#define SMPH_PEEK8_STAT_BITN 0 -#define SMPH_PEEK8_STAT_M 0x00000001 -#define SMPH_PEEK8_STAT_S 0 +#define SMPH_PEEK8_STAT 0x00000001 +#define SMPH_PEEK8_STAT_BITN 0 +#define SMPH_PEEK8_STAT_M 0x00000001 +#define SMPH_PEEK8_STAT_S 0 //***************************************************************************** // @@ -1028,10 +1028,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK9_STAT 0x00000001 -#define SMPH_PEEK9_STAT_BITN 0 -#define SMPH_PEEK9_STAT_M 0x00000001 -#define SMPH_PEEK9_STAT_S 0 +#define SMPH_PEEK9_STAT 0x00000001 +#define SMPH_PEEK9_STAT_BITN 0 +#define SMPH_PEEK9_STAT_M 0x00000001 +#define SMPH_PEEK9_STAT_S 0 //***************************************************************************** // @@ -1047,10 +1047,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK10_STAT 0x00000001 -#define SMPH_PEEK10_STAT_BITN 0 -#define SMPH_PEEK10_STAT_M 0x00000001 -#define SMPH_PEEK10_STAT_S 0 +#define SMPH_PEEK10_STAT 0x00000001 +#define SMPH_PEEK10_STAT_BITN 0 +#define SMPH_PEEK10_STAT_M 0x00000001 +#define SMPH_PEEK10_STAT_S 0 //***************************************************************************** // @@ -1066,10 +1066,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK11_STAT 0x00000001 -#define SMPH_PEEK11_STAT_BITN 0 -#define SMPH_PEEK11_STAT_M 0x00000001 -#define SMPH_PEEK11_STAT_S 0 +#define SMPH_PEEK11_STAT 0x00000001 +#define SMPH_PEEK11_STAT_BITN 0 +#define SMPH_PEEK11_STAT_M 0x00000001 +#define SMPH_PEEK11_STAT_S 0 //***************************************************************************** // @@ -1085,10 +1085,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK12_STAT 0x00000001 -#define SMPH_PEEK12_STAT_BITN 0 -#define SMPH_PEEK12_STAT_M 0x00000001 -#define SMPH_PEEK12_STAT_S 0 +#define SMPH_PEEK12_STAT 0x00000001 +#define SMPH_PEEK12_STAT_BITN 0 +#define SMPH_PEEK12_STAT_M 0x00000001 +#define SMPH_PEEK12_STAT_S 0 //***************************************************************************** // @@ -1104,10 +1104,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK13_STAT 0x00000001 -#define SMPH_PEEK13_STAT_BITN 0 -#define SMPH_PEEK13_STAT_M 0x00000001 -#define SMPH_PEEK13_STAT_S 0 +#define SMPH_PEEK13_STAT 0x00000001 +#define SMPH_PEEK13_STAT_BITN 0 +#define SMPH_PEEK13_STAT_M 0x00000001 +#define SMPH_PEEK13_STAT_S 0 //***************************************************************************** // @@ -1123,10 +1123,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK14_STAT 0x00000001 -#define SMPH_PEEK14_STAT_BITN 0 -#define SMPH_PEEK14_STAT_M 0x00000001 -#define SMPH_PEEK14_STAT_S 0 +#define SMPH_PEEK14_STAT 0x00000001 +#define SMPH_PEEK14_STAT_BITN 0 +#define SMPH_PEEK14_STAT_M 0x00000001 +#define SMPH_PEEK14_STAT_S 0 //***************************************************************************** // @@ -1142,10 +1142,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK15_STAT 0x00000001 -#define SMPH_PEEK15_STAT_BITN 0 -#define SMPH_PEEK15_STAT_M 0x00000001 -#define SMPH_PEEK15_STAT_S 0 +#define SMPH_PEEK15_STAT 0x00000001 +#define SMPH_PEEK15_STAT_BITN 0 +#define SMPH_PEEK15_STAT_M 0x00000001 +#define SMPH_PEEK15_STAT_S 0 //***************************************************************************** // @@ -1161,10 +1161,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK16_STAT 0x00000001 -#define SMPH_PEEK16_STAT_BITN 0 -#define SMPH_PEEK16_STAT_M 0x00000001 -#define SMPH_PEEK16_STAT_S 0 +#define SMPH_PEEK16_STAT 0x00000001 +#define SMPH_PEEK16_STAT_BITN 0 +#define SMPH_PEEK16_STAT_M 0x00000001 +#define SMPH_PEEK16_STAT_S 0 //***************************************************************************** // @@ -1180,10 +1180,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK17_STAT 0x00000001 -#define SMPH_PEEK17_STAT_BITN 0 -#define SMPH_PEEK17_STAT_M 0x00000001 -#define SMPH_PEEK17_STAT_S 0 +#define SMPH_PEEK17_STAT 0x00000001 +#define SMPH_PEEK17_STAT_BITN 0 +#define SMPH_PEEK17_STAT_M 0x00000001 +#define SMPH_PEEK17_STAT_S 0 //***************************************************************************** // @@ -1199,10 +1199,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK18_STAT 0x00000001 -#define SMPH_PEEK18_STAT_BITN 0 -#define SMPH_PEEK18_STAT_M 0x00000001 -#define SMPH_PEEK18_STAT_S 0 +#define SMPH_PEEK18_STAT 0x00000001 +#define SMPH_PEEK18_STAT_BITN 0 +#define SMPH_PEEK18_STAT_M 0x00000001 +#define SMPH_PEEK18_STAT_S 0 //***************************************************************************** // @@ -1218,10 +1218,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK19_STAT 0x00000001 -#define SMPH_PEEK19_STAT_BITN 0 -#define SMPH_PEEK19_STAT_M 0x00000001 -#define SMPH_PEEK19_STAT_S 0 +#define SMPH_PEEK19_STAT 0x00000001 +#define SMPH_PEEK19_STAT_BITN 0 +#define SMPH_PEEK19_STAT_M 0x00000001 +#define SMPH_PEEK19_STAT_S 0 //***************************************************************************** // @@ -1237,10 +1237,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK20_STAT 0x00000001 -#define SMPH_PEEK20_STAT_BITN 0 -#define SMPH_PEEK20_STAT_M 0x00000001 -#define SMPH_PEEK20_STAT_S 0 +#define SMPH_PEEK20_STAT 0x00000001 +#define SMPH_PEEK20_STAT_BITN 0 +#define SMPH_PEEK20_STAT_M 0x00000001 +#define SMPH_PEEK20_STAT_S 0 //***************************************************************************** // @@ -1256,10 +1256,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK21_STAT 0x00000001 -#define SMPH_PEEK21_STAT_BITN 0 -#define SMPH_PEEK21_STAT_M 0x00000001 -#define SMPH_PEEK21_STAT_S 0 +#define SMPH_PEEK21_STAT 0x00000001 +#define SMPH_PEEK21_STAT_BITN 0 +#define SMPH_PEEK21_STAT_M 0x00000001 +#define SMPH_PEEK21_STAT_S 0 //***************************************************************************** // @@ -1275,10 +1275,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK22_STAT 0x00000001 -#define SMPH_PEEK22_STAT_BITN 0 -#define SMPH_PEEK22_STAT_M 0x00000001 -#define SMPH_PEEK22_STAT_S 0 +#define SMPH_PEEK22_STAT 0x00000001 +#define SMPH_PEEK22_STAT_BITN 0 +#define SMPH_PEEK22_STAT_M 0x00000001 +#define SMPH_PEEK22_STAT_S 0 //***************************************************************************** // @@ -1294,10 +1294,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK23_STAT 0x00000001 -#define SMPH_PEEK23_STAT_BITN 0 -#define SMPH_PEEK23_STAT_M 0x00000001 -#define SMPH_PEEK23_STAT_S 0 +#define SMPH_PEEK23_STAT 0x00000001 +#define SMPH_PEEK23_STAT_BITN 0 +#define SMPH_PEEK23_STAT_M 0x00000001 +#define SMPH_PEEK23_STAT_S 0 //***************************************************************************** // @@ -1313,10 +1313,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK24_STAT 0x00000001 -#define SMPH_PEEK24_STAT_BITN 0 -#define SMPH_PEEK24_STAT_M 0x00000001 -#define SMPH_PEEK24_STAT_S 0 +#define SMPH_PEEK24_STAT 0x00000001 +#define SMPH_PEEK24_STAT_BITN 0 +#define SMPH_PEEK24_STAT_M 0x00000001 +#define SMPH_PEEK24_STAT_S 0 //***************************************************************************** // @@ -1332,10 +1332,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK25_STAT 0x00000001 -#define SMPH_PEEK25_STAT_BITN 0 -#define SMPH_PEEK25_STAT_M 0x00000001 -#define SMPH_PEEK25_STAT_S 0 +#define SMPH_PEEK25_STAT 0x00000001 +#define SMPH_PEEK25_STAT_BITN 0 +#define SMPH_PEEK25_STAT_M 0x00000001 +#define SMPH_PEEK25_STAT_S 0 //***************************************************************************** // @@ -1351,10 +1351,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK26_STAT 0x00000001 -#define SMPH_PEEK26_STAT_BITN 0 -#define SMPH_PEEK26_STAT_M 0x00000001 -#define SMPH_PEEK26_STAT_S 0 +#define SMPH_PEEK26_STAT 0x00000001 +#define SMPH_PEEK26_STAT_BITN 0 +#define SMPH_PEEK26_STAT_M 0x00000001 +#define SMPH_PEEK26_STAT_S 0 //***************************************************************************** // @@ -1370,10 +1370,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK27_STAT 0x00000001 -#define SMPH_PEEK27_STAT_BITN 0 -#define SMPH_PEEK27_STAT_M 0x00000001 -#define SMPH_PEEK27_STAT_S 0 +#define SMPH_PEEK27_STAT 0x00000001 +#define SMPH_PEEK27_STAT_BITN 0 +#define SMPH_PEEK27_STAT_M 0x00000001 +#define SMPH_PEEK27_STAT_S 0 //***************************************************************************** // @@ -1389,10 +1389,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK28_STAT 0x00000001 -#define SMPH_PEEK28_STAT_BITN 0 -#define SMPH_PEEK28_STAT_M 0x00000001 -#define SMPH_PEEK28_STAT_S 0 +#define SMPH_PEEK28_STAT 0x00000001 +#define SMPH_PEEK28_STAT_BITN 0 +#define SMPH_PEEK28_STAT_M 0x00000001 +#define SMPH_PEEK28_STAT_S 0 //***************************************************************************** // @@ -1408,10 +1408,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK29_STAT 0x00000001 -#define SMPH_PEEK29_STAT_BITN 0 -#define SMPH_PEEK29_STAT_M 0x00000001 -#define SMPH_PEEK29_STAT_S 0 +#define SMPH_PEEK29_STAT 0x00000001 +#define SMPH_PEEK29_STAT_BITN 0 +#define SMPH_PEEK29_STAT_M 0x00000001 +#define SMPH_PEEK29_STAT_S 0 //***************************************************************************** // @@ -1427,10 +1427,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK30_STAT 0x00000001 -#define SMPH_PEEK30_STAT_BITN 0 -#define SMPH_PEEK30_STAT_M 0x00000001 -#define SMPH_PEEK30_STAT_S 0 +#define SMPH_PEEK30_STAT 0x00000001 +#define SMPH_PEEK30_STAT_BITN 0 +#define SMPH_PEEK30_STAT_M 0x00000001 +#define SMPH_PEEK30_STAT_S 0 //***************************************************************************** // @@ -1446,10 +1446,9 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK31_STAT 0x00000001 -#define SMPH_PEEK31_STAT_BITN 0 -#define SMPH_PEEK31_STAT_M 0x00000001 -#define SMPH_PEEK31_STAT_S 0 - +#define SMPH_PEEK31_STAT 0x00000001 +#define SMPH_PEEK31_STAT_BITN 0 +#define SMPH_PEEK31_STAT_M 0x00000001 +#define SMPH_PEEK31_STAT_S 0 #endif // __SMPH__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_sram_mmr.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_sram_mmr.h index e16dd83..c4a26f2 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_sram_mmr.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_sram_mmr.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_sram_mmr_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_sram_mmr_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_SRAM_MMR_H__ #define __HW_SRAM_MMR_H__ @@ -44,16 +44,16 @@ // //***************************************************************************** // Parity Error Control -#define SRAM_MMR_O_PER_CTL 0x00000000 +#define SRAM_MMR_O_PER_CTL 0x00000000 // Parity Error Check -#define SRAM_MMR_O_PER_CHK 0x00000004 +#define SRAM_MMR_O_PER_CHK 0x00000004 // Parity Error Debug -#define SRAM_MMR_O_PER_DBG 0x00000008 +#define SRAM_MMR_O_PER_DBG 0x00000008 // Memory Control -#define SRAM_MMR_O_MEM_CTL 0x0000000C +#define SRAM_MMR_O_MEM_CTL 0x0000000C //***************************************************************************** // @@ -66,10 +66,10 @@ // // 0: A parity error will update PER_CHK.PER_ADDR field // 1: Parity error does not update PER_CHK.PER_ADDR field -#define SRAM_MMR_PER_CTL_PER_DISABLE 0x00000100 -#define SRAM_MMR_PER_CTL_PER_DISABLE_BITN 8 -#define SRAM_MMR_PER_CTL_PER_DISABLE_M 0x00000100 -#define SRAM_MMR_PER_CTL_PER_DISABLE_S 8 +#define SRAM_MMR_PER_CTL_PER_DISABLE 0x00000100 +#define SRAM_MMR_PER_CTL_PER_DISABLE_BITN 8 +#define SRAM_MMR_PER_CTL_PER_DISABLE_M 0x00000100 +#define SRAM_MMR_PER_CTL_PER_DISABLE_S 8 // Field: [0] PER_DEBUG_ENABLE // @@ -78,10 +78,10 @@ // 0: Normal operation // 1: An address offset can be written to PER_DBG.PER_DEBUG_ADDR and parity // errors will be generated on reads from within this offset -#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE 0x00000001 -#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE_BITN 0 -#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE_M 0x00000001 -#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE_S 0 +#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE 0x00000001 +#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE_BITN 0 +#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE_M 0x00000001 +#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE_S 0 //***************************************************************************** // @@ -96,9 +96,9 @@ // that contains the location with the parity error. For parity faults on non // word-aligned accesses, CPU_SCS:BFAR.ADDRESS will hold the address of the // location that resulted in parity error. -#define SRAM_MMR_PER_CHK_PER_ADDR_W 24 -#define SRAM_MMR_PER_CHK_PER_ADDR_M 0x00FFFFFF -#define SRAM_MMR_PER_CHK_PER_ADDR_S 0 +#define SRAM_MMR_PER_CHK_PER_ADDR_W 24 +#define SRAM_MMR_PER_CHK_PER_ADDR_M 0x00FFFFFF +#define SRAM_MMR_PER_CHK_PER_ADDR_S 0 //***************************************************************************** // @@ -113,9 +113,9 @@ // within this address offset will force incorrect parity bits to be stored // together with the data written. The following reads within this same address // offset will thus result in parity errors to be generated. -#define SRAM_MMR_PER_DBG_PER_DEBUG_ADDR_W 24 -#define SRAM_MMR_PER_DBG_PER_DEBUG_ADDR_M 0x00FFFFFF -#define SRAM_MMR_PER_DBG_PER_DEBUG_ADDR_S 0 +#define SRAM_MMR_PER_DBG_PER_DEBUG_ADDR_W 24 +#define SRAM_MMR_PER_DBG_PER_DEBUG_ADDR_M 0x00FFFFFF +#define SRAM_MMR_PER_DBG_PER_DEBUG_ADDR_S 0 //***************************************************************************** // @@ -129,10 +129,10 @@ // 0: Memory accepts transfers // 1: Memory controller is busy during initialization. Read and write transfers // are not performed. -#define SRAM_MMR_MEM_CTL_MEM_BUSY 0x00000002 -#define SRAM_MMR_MEM_CTL_MEM_BUSY_BITN 1 -#define SRAM_MMR_MEM_CTL_MEM_BUSY_M 0x00000002 -#define SRAM_MMR_MEM_CTL_MEM_BUSY_S 1 +#define SRAM_MMR_MEM_CTL_MEM_BUSY 0x00000002 +#define SRAM_MMR_MEM_CTL_MEM_BUSY_BITN 1 +#define SRAM_MMR_MEM_CTL_MEM_BUSY_M 0x00000002 +#define SRAM_MMR_MEM_CTL_MEM_BUSY_S 1 // Field: [0] MEM_CLR_EN // @@ -141,10 +141,9 @@ // Writing 1 to MEM_CLR_EN will start memory initialization. The contents of // all byte locations will be initialized to 0x00. MEM_BUSY will be 1 until // memory initialization has completed. -#define SRAM_MMR_MEM_CTL_MEM_CLR_EN 0x00000001 -#define SRAM_MMR_MEM_CTL_MEM_CLR_EN_BITN 0 -#define SRAM_MMR_MEM_CTL_MEM_CLR_EN_M 0x00000001 -#define SRAM_MMR_MEM_CTL_MEM_CLR_EN_S 0 - +#define SRAM_MMR_MEM_CTL_MEM_CLR_EN 0x00000001 +#define SRAM_MMR_MEM_CTL_MEM_CLR_EN_BITN 0 +#define SRAM_MMR_MEM_CTL_MEM_CLR_EN_M 0x00000001 +#define SRAM_MMR_MEM_CTL_MEM_CLR_EN_S 0 #endif // __SRAM_MMR__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ssi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ssi.h index e8acb3d..4f7fa60 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ssi.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_ssi.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_ssi_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_ssi_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_SSI_H__ #define __HW_SSI_H__ @@ -44,34 +44,34 @@ // //***************************************************************************** // Control 0 -#define SSI_O_CR0 0x00000000 +#define SSI_O_CR0 0x00000000 // Control 1 -#define SSI_O_CR1 0x00000004 +#define SSI_O_CR1 0x00000004 // Data -#define SSI_O_DR 0x00000008 +#define SSI_O_DR 0x00000008 // Status -#define SSI_O_SR 0x0000000C +#define SSI_O_SR 0x0000000C // Clock Prescale -#define SSI_O_CPSR 0x00000010 +#define SSI_O_CPSR 0x00000010 // Interrupt Mask Set and Clear -#define SSI_O_IMSC 0x00000014 +#define SSI_O_IMSC 0x00000014 // Raw Interrupt Status -#define SSI_O_RIS 0x00000018 +#define SSI_O_RIS 0x00000018 // Masked Interrupt Status -#define SSI_O_MIS 0x0000001C +#define SSI_O_MIS 0x0000001C // Interrupt Clear -#define SSI_O_ICR 0x00000020 +#define SSI_O_ICR 0x00000020 // DMA Control -#define SSI_O_DMACR 0x00000024 +#define SSI_O_DMACR 0x00000024 //***************************************************************************** // @@ -85,9 +85,9 @@ // bit rate is // (SSI's clock frequency)/((SCR+1)*CPSR.CPSDVSR). // SCR is a value from 0-255. -#define SSI_CR0_SCR_W 8 -#define SSI_CR0_SCR_M 0x0000FF00 -#define SSI_CR0_SCR_S 8 +#define SSI_CR0_SCR_W 8 +#define SSI_CR0_SCR_M 0x0000FF00 +#define SSI_CR0_SCR_S 8 // Field: [7] SPH // @@ -101,12 +101,12 @@ // transition. // 1ST_CLK_EDGE Data is captured on the first clock edge // transition. -#define SSI_CR0_SPH 0x00000080 -#define SSI_CR0_SPH_BITN 7 -#define SSI_CR0_SPH_M 0x00000080 -#define SSI_CR0_SPH_S 7 -#define SSI_CR0_SPH_2ND_CLK_EDGE 0x00000080 -#define SSI_CR0_SPH_1ST_CLK_EDGE 0x00000000 +#define SSI_CR0_SPH 0x00000080 +#define SSI_CR0_SPH_BITN 7 +#define SSI_CR0_SPH_M 0x00000080 +#define SSI_CR0_SPH_S 7 +#define SSI_CR0_SPH_2ND_CLK_EDGE 0x00000080 +#define SSI_CR0_SPH_1ST_CLK_EDGE 0x00000000 // Field: [6] SPO // @@ -117,12 +117,12 @@ // LOW SSI produces a steady state LOW value on the // CLKOUT pin when data is // not being transferred. -#define SSI_CR0_SPO 0x00000040 -#define SSI_CR0_SPO_BITN 6 -#define SSI_CR0_SPO_M 0x00000040 -#define SSI_CR0_SPO_S 6 -#define SSI_CR0_SPO_HIGH 0x00000040 -#define SSI_CR0_SPO_LOW 0x00000000 +#define SSI_CR0_SPO 0x00000040 +#define SSI_CR0_SPO_BITN 6 +#define SSI_CR0_SPO_M 0x00000040 +#define SSI_CR0_SPO_S 6 +#define SSI_CR0_SPO_HIGH 0x00000040 +#define SSI_CR0_SPO_LOW 0x00000000 // Field: [5:4] FRF // @@ -134,12 +134,12 @@ // NATIONAL_MICROWIRE National Microwire frame format // TI_SYNC_SERIAL TI synchronous serial frame format // MOTOROLA_SPI Motorola SPI frame format -#define SSI_CR0_FRF_W 2 -#define SSI_CR0_FRF_M 0x00000030 -#define SSI_CR0_FRF_S 4 -#define SSI_CR0_FRF_NATIONAL_MICROWIRE 0x00000020 -#define SSI_CR0_FRF_TI_SYNC_SERIAL 0x00000010 -#define SSI_CR0_FRF_MOTOROLA_SPI 0x00000000 +#define SSI_CR0_FRF_W 2 +#define SSI_CR0_FRF_M 0x00000030 +#define SSI_CR0_FRF_S 4 +#define SSI_CR0_FRF_NATIONAL_MICROWIRE 0x00000020 +#define SSI_CR0_FRF_TI_SYNC_SERIAL 0x00000010 +#define SSI_CR0_FRF_MOTOROLA_SPI 0x00000000 // Field: [3:0] DSS // @@ -159,22 +159,22 @@ // 6_BIT 6-bit data // 5_BIT 5-bit data // 4_BIT 4-bit data -#define SSI_CR0_DSS_W 4 -#define SSI_CR0_DSS_M 0x0000000F -#define SSI_CR0_DSS_S 0 -#define SSI_CR0_DSS_16_BIT 0x0000000F -#define SSI_CR0_DSS_15_BIT 0x0000000E -#define SSI_CR0_DSS_14_BIT 0x0000000D -#define SSI_CR0_DSS_13_BIT 0x0000000C -#define SSI_CR0_DSS_12_BIT 0x0000000B -#define SSI_CR0_DSS_11_BIT 0x0000000A -#define SSI_CR0_DSS_10_BIT 0x00000009 -#define SSI_CR0_DSS_9_BIT 0x00000008 -#define SSI_CR0_DSS_8_BIT 0x00000007 -#define SSI_CR0_DSS_7_BIT 0x00000006 -#define SSI_CR0_DSS_6_BIT 0x00000005 -#define SSI_CR0_DSS_5_BIT 0x00000004 -#define SSI_CR0_DSS_4_BIT 0x00000003 +#define SSI_CR0_DSS_W 4 +#define SSI_CR0_DSS_M 0x0000000F +#define SSI_CR0_DSS_S 0 +#define SSI_CR0_DSS_16_BIT 0x0000000F +#define SSI_CR0_DSS_15_BIT 0x0000000E +#define SSI_CR0_DSS_14_BIT 0x0000000D +#define SSI_CR0_DSS_13_BIT 0x0000000C +#define SSI_CR0_DSS_12_BIT 0x0000000B +#define SSI_CR0_DSS_11_BIT 0x0000000A +#define SSI_CR0_DSS_10_BIT 0x00000009 +#define SSI_CR0_DSS_9_BIT 0x00000008 +#define SSI_CR0_DSS_8_BIT 0x00000007 +#define SSI_CR0_DSS_7_BIT 0x00000006 +#define SSI_CR0_DSS_6_BIT 0x00000005 +#define SSI_CR0_DSS_5_BIT 0x00000004 +#define SSI_CR0_DSS_4_BIT 0x00000003 //***************************************************************************** // @@ -193,10 +193,10 @@ // // 0: SSI can drive the TXD output in slave mode. // 1: SSI cannot drive the TXD output in slave mode. -#define SSI_CR1_SOD 0x00000008 -#define SSI_CR1_SOD_BITN 3 -#define SSI_CR1_SOD_M 0x00000008 -#define SSI_CR1_SOD_S 3 +#define SSI_CR1_SOD 0x00000008 +#define SSI_CR1_SOD_BITN 3 +#define SSI_CR1_SOD_M 0x00000008 +#define SSI_CR1_SOD_S 3 // Field: [2] MS // @@ -205,12 +205,12 @@ // ENUMs: // SLAVE Device configured as slave // MASTER Device configured as master -#define SSI_CR1_MS 0x00000004 -#define SSI_CR1_MS_BITN 2 -#define SSI_CR1_MS_M 0x00000004 -#define SSI_CR1_MS_S 2 -#define SSI_CR1_MS_SLAVE 0x00000004 -#define SSI_CR1_MS_MASTER 0x00000000 +#define SSI_CR1_MS 0x00000004 +#define SSI_CR1_MS_BITN 2 +#define SSI_CR1_MS_M 0x00000004 +#define SSI_CR1_MS_S 2 +#define SSI_CR1_MS_SLAVE 0x00000004 +#define SSI_CR1_MS_MASTER 0x00000000 // Field: [1] SSE // @@ -218,12 +218,12 @@ // ENUMs: // SSI_ENABLED Operation enabled // SSI_DISABLED Operation disabled -#define SSI_CR1_SSE 0x00000002 -#define SSI_CR1_SSE_BITN 1 -#define SSI_CR1_SSE_M 0x00000002 -#define SSI_CR1_SSE_S 1 -#define SSI_CR1_SSE_SSI_ENABLED 0x00000002 -#define SSI_CR1_SSE_SSI_DISABLED 0x00000000 +#define SSI_CR1_SSE 0x00000002 +#define SSI_CR1_SSE_BITN 1 +#define SSI_CR1_SSE_M 0x00000002 +#define SSI_CR1_SSE_S 1 +#define SSI_CR1_SSE_SSI_ENABLED 0x00000002 +#define SSI_CR1_SSE_SSI_DISABLED 0x00000000 // Field: [0] LBM // @@ -232,10 +232,10 @@ // 0: Normal serial port operation enabled. // 1: Output of transmit serial shifter is connected to input of receive serial // shifter internally. -#define SSI_CR1_LBM 0x00000001 -#define SSI_CR1_LBM_BITN 0 -#define SSI_CR1_LBM_M 0x00000001 -#define SSI_CR1_LBM_S 0 +#define SSI_CR1_LBM 0x00000001 +#define SSI_CR1_LBM_BITN 0 +#define SSI_CR1_LBM_M 0x00000001 +#define SSI_CR1_LBM_S 0 //***************************************************************************** // @@ -249,9 +249,9 @@ // right-justified when SSI is programmed for a data size that is less than 16 // bits (CR0.DSS != 0b1111). Unused bits at the top are ignored by transmit // logic. The receive logic automatically right-justifies. -#define SSI_DR_DATA_W 16 -#define SSI_DR_DATA_M 0x0000FFFF -#define SSI_DR_DATA_S 0 +#define SSI_DR_DATA_W 16 +#define SSI_DR_DATA_M 0x0000FFFF +#define SSI_DR_DATA_S 0 //***************************************************************************** // @@ -265,10 +265,10 @@ // 0: SSI is idle // 1: SSI is currently transmitting and/or receiving a frame or the transmit // FIFO is not empty. -#define SSI_SR_BSY 0x00000010 -#define SSI_SR_BSY_BITN 4 -#define SSI_SR_BSY_M 0x00000010 -#define SSI_SR_BSY_S 4 +#define SSI_SR_BSY 0x00000010 +#define SSI_SR_BSY_BITN 4 +#define SSI_SR_BSY_M 0x00000010 +#define SSI_SR_BSY_S 4 // Field: [3] RFF // @@ -276,10 +276,10 @@ // // 0: Receive FIFO is not full. // 1: Receive FIFO is full. -#define SSI_SR_RFF 0x00000008 -#define SSI_SR_RFF_BITN 3 -#define SSI_SR_RFF_M 0x00000008 -#define SSI_SR_RFF_S 3 +#define SSI_SR_RFF 0x00000008 +#define SSI_SR_RFF_BITN 3 +#define SSI_SR_RFF_M 0x00000008 +#define SSI_SR_RFF_S 3 // Field: [2] RNE // @@ -287,10 +287,10 @@ // // 0: Receive FIFO is empty. // 1: Receive FIFO is not empty. -#define SSI_SR_RNE 0x00000004 -#define SSI_SR_RNE_BITN 2 -#define SSI_SR_RNE_M 0x00000004 -#define SSI_SR_RNE_S 2 +#define SSI_SR_RNE 0x00000004 +#define SSI_SR_RNE_BITN 2 +#define SSI_SR_RNE_M 0x00000004 +#define SSI_SR_RNE_S 2 // Field: [1] TNF // @@ -298,10 +298,10 @@ // // 0: Transmit FIFO is full. // 1: Transmit FIFO is not full. -#define SSI_SR_TNF 0x00000002 -#define SSI_SR_TNF_BITN 1 -#define SSI_SR_TNF_M 0x00000002 -#define SSI_SR_TNF_S 1 +#define SSI_SR_TNF 0x00000002 +#define SSI_SR_TNF_BITN 1 +#define SSI_SR_TNF_M 0x00000002 +#define SSI_SR_TNF_S 1 // Field: [0] TFE // @@ -309,10 +309,10 @@ // // 0: Transmit FIFO is not empty. // 1: Transmit FIFO is empty. -#define SSI_SR_TFE 0x00000001 -#define SSI_SR_TFE_BITN 0 -#define SSI_SR_TFE_M 0x00000001 -#define SSI_SR_TFE_S 0 +#define SSI_SR_TFE 0x00000001 +#define SSI_SR_TFE_BITN 0 +#define SSI_SR_TFE_M 0x00000001 +#define SSI_SR_TFE_S 0 //***************************************************************************** // @@ -328,9 +328,9 @@ // (2-254). The least significant bit of the programmed number is hard-coded to // zero. If an odd number is written to this register, data read back from // this register has the least significant bit as zero. -#define SSI_CPSR_CPSDVSR_W 8 -#define SSI_CPSR_CPSDVSR_M 0x000000FF -#define SSI_CPSR_CPSDVSR_S 0 +#define SSI_CPSR_CPSDVSR_W 8 +#define SSI_CPSR_CPSDVSR_M 0x000000FF +#define SSI_CPSR_CPSDVSR_S 0 //***************************************************************************** // @@ -344,10 +344,10 @@ // 1, the mask for transmit FIFO interrupt is set which means the interrupt // state will be reflected in MIS.TXMIS. A write of 0 clears the mask which // means MIS.TXMIS will not reflect the interrupt. -#define SSI_IMSC_TXIM 0x00000008 -#define SSI_IMSC_TXIM_BITN 3 -#define SSI_IMSC_TXIM_M 0x00000008 -#define SSI_IMSC_TXIM_S 3 +#define SSI_IMSC_TXIM 0x00000008 +#define SSI_IMSC_TXIM_BITN 3 +#define SSI_IMSC_TXIM_M 0x00000008 +#define SSI_IMSC_TXIM_S 3 // Field: [2] RXIM // @@ -356,10 +356,10 @@ // the mask for receive FIFO interrupt is set which means the interrupt state // will be reflected in MIS.RXMIS. A write of 0 clears the mask which means // MIS.RXMIS will not reflect the interrupt. -#define SSI_IMSC_RXIM 0x00000004 -#define SSI_IMSC_RXIM_BITN 2 -#define SSI_IMSC_RXIM_M 0x00000004 -#define SSI_IMSC_RXIM_S 2 +#define SSI_IMSC_RXIM 0x00000004 +#define SSI_IMSC_RXIM_BITN 2 +#define SSI_IMSC_RXIM_M 0x00000004 +#define SSI_IMSC_RXIM_S 2 // Field: [1] RTIM // @@ -368,10 +368,10 @@ // 1, the mask for receive timeout interrupt is set which means the interrupt // state will be reflected in MIS.RTMIS. A write of 0 clears the mask which // means MIS.RTMIS will not reflect the interrupt. -#define SSI_IMSC_RTIM 0x00000002 -#define SSI_IMSC_RTIM_BITN 1 -#define SSI_IMSC_RTIM_M 0x00000002 -#define SSI_IMSC_RTIM_S 1 +#define SSI_IMSC_RTIM 0x00000002 +#define SSI_IMSC_RTIM_BITN 1 +#define SSI_IMSC_RTIM_M 0x00000002 +#define SSI_IMSC_RTIM_S 1 // Field: [0] RORIM // @@ -380,10 +380,10 @@ // 1, the mask for receive overrun interrupt is set which means the interrupt // state will be reflected in MIS.RORMIS. A write of 0 clears the mask which // means MIS.RORMIS will not reflect the interrupt. -#define SSI_IMSC_RORIM 0x00000001 -#define SSI_IMSC_RORIM_BITN 0 -#define SSI_IMSC_RORIM_M 0x00000001 -#define SSI_IMSC_RORIM_S 0 +#define SSI_IMSC_RORIM 0x00000001 +#define SSI_IMSC_RORIM_BITN 0 +#define SSI_IMSC_RORIM_M 0x00000001 +#define SSI_IMSC_RORIM_S 0 //***************************************************************************** // @@ -401,20 +401,20 @@ // interrupts. // - SSI and interrupts can be enabled so that data can be written to the // transmit FIFO by an interrupt service routine. -#define SSI_RIS_TXRIS 0x00000008 -#define SSI_RIS_TXRIS_BITN 3 -#define SSI_RIS_TXRIS_M 0x00000008 -#define SSI_RIS_TXRIS_S 3 +#define SSI_RIS_TXRIS 0x00000008 +#define SSI_RIS_TXRIS_BITN 3 +#define SSI_RIS_TXRIS_M 0x00000008 +#define SSI_RIS_TXRIS_S 3 // Field: [2] RXRIS // // Raw interrupt state of receive FIFO interrupt: // The receive interrupt is asserted when there are four or more valid entries // in the receive FIFO. -#define SSI_RIS_RXRIS 0x00000004 -#define SSI_RIS_RXRIS_BITN 2 -#define SSI_RIS_RXRIS_M 0x00000004 -#define SSI_RIS_RXRIS_S 2 +#define SSI_RIS_RXRIS 0x00000004 +#define SSI_RIS_RXRIS_BITN 2 +#define SSI_RIS_RXRIS_M 0x00000004 +#define SSI_RIS_RXRIS_S 2 // Field: [1] RTRIS // @@ -425,10 +425,10 @@ // requires servicing. This interrupt is deasserted if the receive FIFO becomes // empty by subsequent reads, or if new data is received on RXD. // It can also be cleared by writing to ICR.RTIC. -#define SSI_RIS_RTRIS 0x00000002 -#define SSI_RIS_RTRIS_BITN 1 -#define SSI_RIS_RTRIS_M 0x00000002 -#define SSI_RIS_RTRIS_S 1 +#define SSI_RIS_RTRIS 0x00000002 +#define SSI_RIS_RTRIS_BITN 1 +#define SSI_RIS_RTRIS_M 0x00000002 +#define SSI_RIS_RTRIS_S 1 // Field: [0] RORRIS // @@ -438,10 +438,10 @@ // is over-written in the // receive shift register, but not the FIFO so the FIFO contents stay valid. // It can also be cleared by writing to ICR.RORIC. -#define SSI_RIS_RORRIS 0x00000001 -#define SSI_RIS_RORRIS_BITN 0 -#define SSI_RIS_RORRIS_M 0x00000001 -#define SSI_RIS_RORRIS_S 0 +#define SSI_RIS_RORRIS 0x00000001 +#define SSI_RIS_RORRIS_BITN 0 +#define SSI_RIS_RORRIS_M 0x00000001 +#define SSI_RIS_RORRIS_S 0 //***************************************************************************** // @@ -454,10 +454,10 @@ // This field returns the masked interrupt state of transmit FIFO interrupt // which is the AND product of raw interrupt state RIS.TXRIS and the mask // setting IMSC.TXIM. -#define SSI_MIS_TXMIS 0x00000008 -#define SSI_MIS_TXMIS_BITN 3 -#define SSI_MIS_TXMIS_M 0x00000008 -#define SSI_MIS_TXMIS_S 3 +#define SSI_MIS_TXMIS 0x00000008 +#define SSI_MIS_TXMIS_BITN 3 +#define SSI_MIS_TXMIS_M 0x00000008 +#define SSI_MIS_TXMIS_S 3 // Field: [2] RXMIS // @@ -465,10 +465,10 @@ // This field returns the masked interrupt state of receive FIFO interrupt // which is the AND product of raw interrupt state RIS.RXRIS and the mask // setting IMSC.RXIM. -#define SSI_MIS_RXMIS 0x00000004 -#define SSI_MIS_RXMIS_BITN 2 -#define SSI_MIS_RXMIS_M 0x00000004 -#define SSI_MIS_RXMIS_S 2 +#define SSI_MIS_RXMIS 0x00000004 +#define SSI_MIS_RXMIS_BITN 2 +#define SSI_MIS_RXMIS_M 0x00000004 +#define SSI_MIS_RXMIS_S 2 // Field: [1] RTMIS // @@ -476,10 +476,10 @@ // This field returns the masked interrupt state of receive timeout interrupt // which is the AND product of raw interrupt state RIS.RTRIS and the mask // setting IMSC.RTIM. -#define SSI_MIS_RTMIS 0x00000002 -#define SSI_MIS_RTMIS_BITN 1 -#define SSI_MIS_RTMIS_M 0x00000002 -#define SSI_MIS_RTMIS_S 1 +#define SSI_MIS_RTMIS 0x00000002 +#define SSI_MIS_RTMIS_BITN 1 +#define SSI_MIS_RTMIS_M 0x00000002 +#define SSI_MIS_RTMIS_S 1 // Field: [0] RORMIS // @@ -487,10 +487,10 @@ // This field returns the masked interrupt state of receive overrun interrupt // which is the AND product of raw interrupt state RIS.RORRIS and the mask // setting IMSC.RORIM. -#define SSI_MIS_RORMIS 0x00000001 -#define SSI_MIS_RORMIS_BITN 0 -#define SSI_MIS_RORMIS_M 0x00000001 -#define SSI_MIS_RORMIS_S 0 +#define SSI_MIS_RORMIS 0x00000001 +#define SSI_MIS_RORMIS_BITN 0 +#define SSI_MIS_RORMIS_M 0x00000001 +#define SSI_MIS_RORMIS_S 0 //***************************************************************************** // @@ -502,20 +502,20 @@ // Clear the receive timeout interrupt: // Writing 1 to this field clears the timeout interrupt (RIS.RTRIS). Writing 0 // has no effect. -#define SSI_ICR_RTIC 0x00000002 -#define SSI_ICR_RTIC_BITN 1 -#define SSI_ICR_RTIC_M 0x00000002 -#define SSI_ICR_RTIC_S 1 +#define SSI_ICR_RTIC 0x00000002 +#define SSI_ICR_RTIC_BITN 1 +#define SSI_ICR_RTIC_M 0x00000002 +#define SSI_ICR_RTIC_S 1 // Field: [0] RORIC // // Clear the receive overrun interrupt: // Writing 1 to this field clears the overrun error interrupt (RIS.RORRIS). // Writing 0 has no effect. -#define SSI_ICR_RORIC 0x00000001 -#define SSI_ICR_RORIC_BITN 0 -#define SSI_ICR_RORIC_M 0x00000001 -#define SSI_ICR_RORIC_S 0 +#define SSI_ICR_RORIC 0x00000001 +#define SSI_ICR_RORIC_BITN 0 +#define SSI_ICR_RORIC_M 0x00000001 +#define SSI_ICR_RORIC_S 0 //***************************************************************************** // @@ -526,19 +526,18 @@ // // Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is // enabled. -#define SSI_DMACR_TXDMAE 0x00000002 -#define SSI_DMACR_TXDMAE_BITN 1 -#define SSI_DMACR_TXDMAE_M 0x00000002 -#define SSI_DMACR_TXDMAE_S 1 +#define SSI_DMACR_TXDMAE 0x00000002 +#define SSI_DMACR_TXDMAE_BITN 1 +#define SSI_DMACR_TXDMAE_M 0x00000002 +#define SSI_DMACR_TXDMAE_S 1 // Field: [0] RXDMAE // // Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is // enabled. -#define SSI_DMACR_RXDMAE 0x00000001 -#define SSI_DMACR_RXDMAE_BITN 0 -#define SSI_DMACR_RXDMAE_M 0x00000001 -#define SSI_DMACR_RXDMAE_S 0 - +#define SSI_DMACR_RXDMAE 0x00000001 +#define SSI_DMACR_RXDMAE_BITN 0 +#define SSI_DMACR_RXDMAE_M 0x00000001 +#define SSI_DMACR_RXDMAE_S 0 #endif // __SSI__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_sysctl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_sysctl.h index 1ddd6bb..9a8fada 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_sysctl.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_sysctl.h @@ -1,49 +1,47 @@ /****************************************************************************** -* Filename: hw_sysctl.h -* Revised: 2015-03-16 14:43:45 +0100 (Mon, 16 Mar 2015) -* Revision: 42989 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_sysctl.h + * Revised: 2015-03-16 14:43:45 +0100 (Mon, 16 Mar 2015) + * Revision: 42989 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_SYSCTL_H__ #define __HW_SYSCTL_H__ - //***************************************************************************** // // The following are initial defines for the MCU clock // //***************************************************************************** -#define GET_MCU_CLOCK 48000000 - +#define GET_MCU_CLOCK 48000000 #endif // __HW_SYSCTL_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_trng.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_trng.h index 6ea8bd7..6b1c0e1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_trng.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_trng.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_trng_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_trng_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_TRNG_H__ #define __HW_TRNG_H__ @@ -44,70 +44,70 @@ // //***************************************************************************** // Random Number Lower Word Readout Value -#define TRNG_O_OUT0 0x00000000 +#define TRNG_O_OUT0 0x00000000 // Random Number Upper Word Readout Value -#define TRNG_O_OUT1 0x00000004 +#define TRNG_O_OUT1 0x00000004 // Interrupt Status -#define TRNG_O_IRQFLAGSTAT 0x00000008 +#define TRNG_O_IRQFLAGSTAT 0x00000008 // Interrupt Mask -#define TRNG_O_IRQFLAGMASK 0x0000000C +#define TRNG_O_IRQFLAGMASK 0x0000000C // Interrupt Flag Clear -#define TRNG_O_IRQFLAGCLR 0x00000010 +#define TRNG_O_IRQFLAGCLR 0x00000010 // Control -#define TRNG_O_CTL 0x00000014 +#define TRNG_O_CTL 0x00000014 // Configuration 0 -#define TRNG_O_CFG0 0x00000018 +#define TRNG_O_CFG0 0x00000018 // Alarm Control -#define TRNG_O_ALARMCNT 0x0000001C +#define TRNG_O_ALARMCNT 0x0000001C // FRO Enable -#define TRNG_O_FROEN 0x00000020 +#define TRNG_O_FROEN 0x00000020 // FRO De-tune Bit -#define TRNG_O_FRODETUNE 0x00000024 +#define TRNG_O_FRODETUNE 0x00000024 // Alarm Event -#define TRNG_O_ALARMMASK 0x00000028 +#define TRNG_O_ALARMMASK 0x00000028 // Alarm Shutdown -#define TRNG_O_ALARMSTOP 0x0000002C +#define TRNG_O_ALARMSTOP 0x0000002C // LFSR Readout Value -#define TRNG_O_LFSR0 0x00000030 +#define TRNG_O_LFSR0 0x00000030 // LFSR Readout Value -#define TRNG_O_LFSR1 0x00000034 +#define TRNG_O_LFSR1 0x00000034 // LFSR Readout Value -#define TRNG_O_LFSR2 0x00000038 +#define TRNG_O_LFSR2 0x00000038 // TRNG Engine Options Information -#define TRNG_O_HWOPT 0x00000078 +#define TRNG_O_HWOPT 0x00000078 // HW Version 0 -#define TRNG_O_HWVER0 0x0000007C +#define TRNG_O_HWVER0 0x0000007C // Interrupt Status After Masking -#define TRNG_O_IRQSTATMASK 0x00001FD8 +#define TRNG_O_IRQSTATMASK 0x00001FD8 // HW Version 1 -#define TRNG_O_HWVER1 0x00001FE0 +#define TRNG_O_HWVER1 0x00001FE0 // Interrupt Set -#define TRNG_O_IRQSET 0x00001FEC +#define TRNG_O_IRQSET 0x00001FEC // SW Reset Control -#define TRNG_O_SWRESET 0x00001FF0 +#define TRNG_O_SWRESET 0x00001FF0 // Interrupt Status -#define TRNG_O_IRQSTAT 0x00001FF8 +#define TRNG_O_IRQSTAT 0x00001FF8 //***************************************************************************** // @@ -117,9 +117,9 @@ // Field: [31:0] VALUE_31_0 // // LSW of 64- bit random value. New value ready when IRQFLAGSTAT.RDY = 1. -#define TRNG_OUT0_VALUE_31_0_W 32 -#define TRNG_OUT0_VALUE_31_0_M 0xFFFFFFFF -#define TRNG_OUT0_VALUE_31_0_S 0 +#define TRNG_OUT0_VALUE_31_0_W 32 +#define TRNG_OUT0_VALUE_31_0_M 0xFFFFFFFF +#define TRNG_OUT0_VALUE_31_0_S 0 //***************************************************************************** // @@ -129,9 +129,9 @@ // Field: [31:0] VALUE_63_32 // // MSW of 64-bit random value. New value ready when IRQFLAGSTAT.RDY = 1. -#define TRNG_OUT1_VALUE_63_32_W 32 -#define TRNG_OUT1_VALUE_63_32_M 0xFFFFFFFF -#define TRNG_OUT1_VALUE_63_32_S 0 +#define TRNG_OUT1_VALUE_63_32_W 32 +#define TRNG_OUT1_VALUE_63_32_M 0xFFFFFFFF +#define TRNG_OUT1_VALUE_63_32_S 0 //***************************************************************************** // @@ -144,10 +144,10 @@ // test modes - clocks may not be turned off and the power supply voltage must // be kept stable. // 0: TRNG is idle and can be shut down -#define TRNG_IRQFLAGSTAT_NEED_CLOCK 0x80000000 -#define TRNG_IRQFLAGSTAT_NEED_CLOCK_BITN 31 -#define TRNG_IRQFLAGSTAT_NEED_CLOCK_M 0x80000000 -#define TRNG_IRQFLAGSTAT_NEED_CLOCK_S 31 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK 0x80000000 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_BITN 31 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_M 0x80000000 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_S 31 // Field: [1] SHUTDOWN_OVF // @@ -155,10 +155,10 @@ // ALARMSTOP register) has exceeded the threshold set by ALARMCNT.SHUTDOWN_THR // // Writing '1' to IRQFLAGCLR.SHUTDOWN_OVF clears this bit to '0' again. -#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF 0x00000002 -#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_BITN 1 -#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_M 0x00000002 -#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_S 1 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_S 1 // Field: [0] RDY // @@ -169,10 +169,10 @@ // If a new number is already available in the internal register of the TRNG, // the number is directly clocked into the result register. In this case the // status bit is asserted again, after one clock cycle. -#define TRNG_IRQFLAGSTAT_RDY 0x00000001 -#define TRNG_IRQFLAGSTAT_RDY_BITN 0 -#define TRNG_IRQFLAGSTAT_RDY_M 0x00000001 -#define TRNG_IRQFLAGSTAT_RDY_S 0 +#define TRNG_IRQFLAGSTAT_RDY 0x00000001 +#define TRNG_IRQFLAGSTAT_RDY_BITN 0 +#define TRNG_IRQFLAGSTAT_RDY_M 0x00000001 +#define TRNG_IRQFLAGSTAT_RDY_S 0 //***************************************************************************** // @@ -183,18 +183,18 @@ // // 1: Allow IRQFLAGSTAT.SHUTDOWN_OVF to activate the interrupt from this // module. -#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF 0x00000002 -#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_BITN 1 -#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_M 0x00000002 -#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_S 1 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_S 1 // Field: [0] RDY // // 1: Allow IRQFLAGSTAT.RDY to activate the interrupt from this module. -#define TRNG_IRQFLAGMASK_RDY 0x00000001 -#define TRNG_IRQFLAGMASK_RDY_BITN 0 -#define TRNG_IRQFLAGMASK_RDY_M 0x00000001 -#define TRNG_IRQFLAGMASK_RDY_S 0 +#define TRNG_IRQFLAGMASK_RDY 0x00000001 +#define TRNG_IRQFLAGMASK_RDY_BITN 0 +#define TRNG_IRQFLAGMASK_RDY_M 0x00000001 +#define TRNG_IRQFLAGMASK_RDY_S 0 //***************************************************************************** // @@ -204,18 +204,18 @@ // Field: [1] SHUTDOWN_OVF // // 1: Clear IRQFLAGSTAT.SHUTDOWN_OVF. -#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF 0x00000002 -#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_BITN 1 -#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_M 0x00000002 -#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_S 1 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_S 1 // Field: [0] RDY // // 1: Clear IRQFLAGSTAT.RDY. -#define TRNG_IRQFLAGCLR_RDY 0x00000001 -#define TRNG_IRQFLAGCLR_RDY_BITN 0 -#define TRNG_IRQFLAGCLR_RDY_M 0x00000001 -#define TRNG_IRQFLAGCLR_RDY_S 0 +#define TRNG_IRQFLAGCLR_RDY 0x00000001 +#define TRNG_IRQFLAGCLR_RDY_BITN 0 +#define TRNG_IRQFLAGCLR_RDY_M 0x00000001 +#define TRNG_IRQFLAGCLR_RDY_S 0 //***************************************************************************** // @@ -241,19 +241,19 @@ // // This field can only be modified while TRNG_EN is 0. If 1 an update will be // ignored. -#define TRNG_CTL_STARTUP_CYCLES_W 16 -#define TRNG_CTL_STARTUP_CYCLES_M 0xFFFF0000 -#define TRNG_CTL_STARTUP_CYCLES_S 16 +#define TRNG_CTL_STARTUP_CYCLES_W 16 +#define TRNG_CTL_STARTUP_CYCLES_M 0xFFFF0000 +#define TRNG_CTL_STARTUP_CYCLES_S 16 // Field: [10] TRNG_EN // // 0: Forces all TRNG logic back into the idle state immediately. // 1: Starts TRNG, gathering entropy from the FROs for the number of samples // determined by STARTUP_CYCLES. -#define TRNG_CTL_TRNG_EN 0x00000400 -#define TRNG_CTL_TRNG_EN_BITN 10 -#define TRNG_CTL_TRNG_EN_M 0x00000400 -#define TRNG_CTL_TRNG_EN_S 10 +#define TRNG_CTL_TRNG_EN 0x00000400 +#define TRNG_CTL_TRNG_EN_BITN 10 +#define TRNG_CTL_TRNG_EN_M 0x00000400 +#define TRNG_CTL_TRNG_EN_S 10 // Field: [2] NO_LFSR_FB // @@ -263,10 +263,10 @@ // // This bit can only be set to '1' when TEST_MODE is also set to '1' and should // not be used for other than test purposes -#define TRNG_CTL_NO_LFSR_FB 0x00000004 -#define TRNG_CTL_NO_LFSR_FB_BITN 2 -#define TRNG_CTL_NO_LFSR_FB_M 0x00000004 -#define TRNG_CTL_NO_LFSR_FB_S 2 +#define TRNG_CTL_NO_LFSR_FB 0x00000004 +#define TRNG_CTL_NO_LFSR_FB_BITN 2 +#define TRNG_CTL_NO_LFSR_FB_M 0x00000004 +#define TRNG_CTL_NO_LFSR_FB_S 2 // Field: [1] TEST_MODE // @@ -277,10 +277,10 @@ // This bit shall not be used unless you need to change the LFSR seed prior to // creating a new random value. All other testing is done external to register // control. -#define TRNG_CTL_TEST_MODE 0x00000002 -#define TRNG_CTL_TEST_MODE_BITN 1 -#define TRNG_CTL_TEST_MODE_M 0x00000002 -#define TRNG_CTL_TEST_MODE_S 1 +#define TRNG_CTL_TEST_MODE 0x00000002 +#define TRNG_CTL_TEST_MODE_BITN 1 +#define TRNG_CTL_TEST_MODE_M 0x00000002 +#define TRNG_CTL_TEST_MODE_S 1 //***************************************************************************** // @@ -306,9 +306,9 @@ // 0xFFFF: 65535*2^8 samples // // This field can only be modified while CTL.TRNG_EN is 0. -#define TRNG_CFG0_MAX_REFILL_CYCLES_W 16 -#define TRNG_CFG0_MAX_REFILL_CYCLES_M 0xFFFF0000 -#define TRNG_CFG0_MAX_REFILL_CYCLES_S 16 +#define TRNG_CFG0_MAX_REFILL_CYCLES_W 16 +#define TRNG_CFG0_MAX_REFILL_CYCLES_M 0xFFFF0000 +#define TRNG_CFG0_MAX_REFILL_CYCLES_S 16 // Field: [11:8] SMPL_DIV // @@ -321,9 +321,9 @@ // conditions) has a cycle time less than twice the sample period. // // This field can only be modified while CTL.TRNG_EN is '0'. -#define TRNG_CFG0_SMPL_DIV_W 4 -#define TRNG_CFG0_SMPL_DIV_M 0x00000F00 -#define TRNG_CFG0_SMPL_DIV_S 8 +#define TRNG_CFG0_SMPL_DIV_W 4 +#define TRNG_CFG0_SMPL_DIV_M 0x00000F00 +#define TRNG_CFG0_SMPL_DIV_S 8 // Field: [7:0] MIN_REFILL_CYCLES // @@ -345,9 +345,9 @@ // 0x02: 2*2^6 samples // ... // 0xFF: 255*2^6 samples -#define TRNG_CFG0_MIN_REFILL_CYCLES_W 8 -#define TRNG_CFG0_MIN_REFILL_CYCLES_M 0x000000FF -#define TRNG_CFG0_MIN_REFILL_CYCLES_S 0 +#define TRNG_CFG0_MIN_REFILL_CYCLES_W 8 +#define TRNG_CFG0_MIN_REFILL_CYCLES_M 0x000000FF +#define TRNG_CFG0_MIN_REFILL_CYCLES_S 0 //***************************************************************************** // @@ -358,17 +358,17 @@ // // Read-only, indicates the number of '1' bits in ALARMSTOP register. // The maximum value equals the number of FROs. -#define TRNG_ALARMCNT_SHUTDOWN_CNT_W 6 -#define TRNG_ALARMCNT_SHUTDOWN_CNT_M 0x3F000000 -#define TRNG_ALARMCNT_SHUTDOWN_CNT_S 24 +#define TRNG_ALARMCNT_SHUTDOWN_CNT_W 6 +#define TRNG_ALARMCNT_SHUTDOWN_CNT_M 0x3F000000 +#define TRNG_ALARMCNT_SHUTDOWN_CNT_S 24 // Field: [20:16] SHUTDOWN_THR // // Threshold setting for generating IRQFLAGSTAT.SHUTDOWN_OVF interrupt. The // interrupt is triggered when SHUTDOWN_CNT value exceeds this bit field. -#define TRNG_ALARMCNT_SHUTDOWN_THR_W 5 -#define TRNG_ALARMCNT_SHUTDOWN_THR_M 0x001F0000 -#define TRNG_ALARMCNT_SHUTDOWN_THR_S 16 +#define TRNG_ALARMCNT_SHUTDOWN_THR_W 5 +#define TRNG_ALARMCNT_SHUTDOWN_THR_M 0x001F0000 +#define TRNG_ALARMCNT_SHUTDOWN_THR_S 16 // Field: [7:0] ALARM_THR // @@ -377,9 +377,9 @@ // samples length) is detected continuously for the number of samples defined // by this field's value. Reset value 0xFF should keep the number of 'alarm // events' to a manageable level. -#define TRNG_ALARMCNT_ALARM_THR_W 8 -#define TRNG_ALARMCNT_ALARM_THR_M 0x000000FF -#define TRNG_ALARMCNT_ALARM_THR_S 0 +#define TRNG_ALARMCNT_ALARM_THR_W 8 +#define TRNG_ALARMCNT_ALARM_THR_M 0x000000FF +#define TRNG_ALARMCNT_ALARM_THR_S 0 //***************************************************************************** // @@ -394,9 +394,9 @@ // // Bits are automatically forced to '0' here (and cannot be written to '1') // while the corresponding bit in ALARMSTOP.FRO_FLAGS has value '1'. -#define TRNG_FROEN_FRO_MASK_W 24 -#define TRNG_FROEN_FRO_MASK_M 0x00FFFFFF -#define TRNG_FROEN_FRO_MASK_S 0 +#define TRNG_FROEN_FRO_MASK_W 24 +#define TRNG_FROEN_FRO_MASK_M 0x00FFFFFF +#define TRNG_FROEN_FRO_MASK_S 0 //***************************************************************************** // @@ -410,9 +410,9 @@ // while the corresponding FRO is turned off (by temporarily writing a '0' in // the corresponding // bit of the FROEN.FRO_MASK register). -#define TRNG_FRODETUNE_FRO_MASK_W 24 -#define TRNG_FRODETUNE_FRO_MASK_M 0x00FFFFFF -#define TRNG_FRODETUNE_FRO_MASK_S 0 +#define TRNG_FRODETUNE_FRO_MASK_W 24 +#define TRNG_FRODETUNE_FRO_MASK_M 0x00FFFFFF +#define TRNG_FRODETUNE_FRO_MASK_S 0 //***************************************************************************** // @@ -423,9 +423,9 @@ // // Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] // indicates FRO 'n' experienced an 'alarm event'. -#define TRNG_ALARMMASK_FRO_MASK_W 24 -#define TRNG_ALARMMASK_FRO_MASK_M 0x00FFFFFF -#define TRNG_ALARMMASK_FRO_MASK_S 0 +#define TRNG_ALARMMASK_FRO_MASK_W 24 +#define TRNG_ALARMMASK_FRO_MASK_M 0x00FFFFFF +#define TRNG_ALARMMASK_FRO_MASK_S 0 //***************************************************************************** // @@ -438,9 +438,9 @@ // indicates FRO 'n' experienced more than one 'alarm event' in quick // succession and has been turned off. A '1' in this field forces the // corresponding bit in FROEN.FRO_MASK to '0'. -#define TRNG_ALARMSTOP_FRO_FLAGS_W 24 -#define TRNG_ALARMSTOP_FRO_FLAGS_M 0x00FFFFFF -#define TRNG_ALARMSTOP_FRO_FLAGS_S 0 +#define TRNG_ALARMSTOP_FRO_FLAGS_W 24 +#define TRNG_ALARMSTOP_FRO_FLAGS_M 0x00FFFFFF +#define TRNG_ALARMSTOP_FRO_FLAGS_S 0 //***************************************************************************** // @@ -452,9 +452,9 @@ // Bits [31:0] of the main entropy accumulation LFSR. Register can only be // accessed when CTL.TEST_MODE = 1. // Register contents will be cleared to zero before access is enabled. -#define TRNG_LFSR0_LFSR_31_0_W 32 -#define TRNG_LFSR0_LFSR_31_0_M 0xFFFFFFFF -#define TRNG_LFSR0_LFSR_31_0_S 0 +#define TRNG_LFSR0_LFSR_31_0_W 32 +#define TRNG_LFSR0_LFSR_31_0_M 0xFFFFFFFF +#define TRNG_LFSR0_LFSR_31_0_S 0 //***************************************************************************** // @@ -466,9 +466,9 @@ // Bits [63:32] of the main entropy accumulation LFSR. Register can only be // accessed when CTL.TEST_MODE = 1. // Register contents will be cleared to zero before access is enabled. -#define TRNG_LFSR1_LFSR_63_32_W 32 -#define TRNG_LFSR1_LFSR_63_32_M 0xFFFFFFFF -#define TRNG_LFSR1_LFSR_63_32_S 0 +#define TRNG_LFSR1_LFSR_63_32_W 32 +#define TRNG_LFSR1_LFSR_63_32_M 0xFFFFFFFF +#define TRNG_LFSR1_LFSR_63_32_S 0 //***************************************************************************** // @@ -480,9 +480,9 @@ // Bits [80:64] of the main entropy accumulation LFSR. Register can only be // accessed when CTL.TEST_MODE = 1. // Register contents will be cleared to zero before access is enabled. -#define TRNG_LFSR2_LFSR_80_64_W 17 -#define TRNG_LFSR2_LFSR_80_64_M 0x0001FFFF -#define TRNG_LFSR2_LFSR_80_64_S 0 +#define TRNG_LFSR2_LFSR_80_64_W 17 +#define TRNG_LFSR2_LFSR_80_64_M 0x0001FFFF +#define TRNG_LFSR2_LFSR_80_64_S 0 //***************************************************************************** // @@ -492,9 +492,9 @@ // Field: [11:6] NR_OF_FROS // // Number of FROs implemented in this TRNG, value 24 (decimal). -#define TRNG_HWOPT_NR_OF_FROS_W 6 -#define TRNG_HWOPT_NR_OF_FROS_M 0x00000FC0 -#define TRNG_HWOPT_NR_OF_FROS_S 6 +#define TRNG_HWOPT_NR_OF_FROS_W 6 +#define TRNG_HWOPT_NR_OF_FROS_M 0x00000FC0 +#define TRNG_HWOPT_NR_OF_FROS_S 6 //***************************************************************************** // @@ -504,38 +504,38 @@ // Field: [27:24] HW_MAJOR_VER // // 4 bits binary encoding of the major hardware revision number. -#define TRNG_HWVER0_HW_MAJOR_VER_W 4 -#define TRNG_HWVER0_HW_MAJOR_VER_M 0x0F000000 -#define TRNG_HWVER0_HW_MAJOR_VER_S 24 +#define TRNG_HWVER0_HW_MAJOR_VER_W 4 +#define TRNG_HWVER0_HW_MAJOR_VER_M 0x0F000000 +#define TRNG_HWVER0_HW_MAJOR_VER_S 24 // Field: [23:20] HW_MINOR_VER // // 4 bits binary encoding of the minor hardware revision number. -#define TRNG_HWVER0_HW_MINOR_VER_W 4 -#define TRNG_HWVER0_HW_MINOR_VER_M 0x00F00000 -#define TRNG_HWVER0_HW_MINOR_VER_S 20 +#define TRNG_HWVER0_HW_MINOR_VER_W 4 +#define TRNG_HWVER0_HW_MINOR_VER_M 0x00F00000 +#define TRNG_HWVER0_HW_MINOR_VER_S 20 // Field: [19:16] HW_PATCH_LVL // // 4 bits binary encoding of the hardware patch level, initial release will // carry value zero. -#define TRNG_HWVER0_HW_PATCH_LVL_W 4 -#define TRNG_HWVER0_HW_PATCH_LVL_M 0x000F0000 -#define TRNG_HWVER0_HW_PATCH_LVL_S 16 +#define TRNG_HWVER0_HW_PATCH_LVL_W 4 +#define TRNG_HWVER0_HW_PATCH_LVL_M 0x000F0000 +#define TRNG_HWVER0_HW_PATCH_LVL_S 16 // Field: [15:8] EIP_NUM_COMPL // // Bit-by-bit logic complement of bits [7:0]. This TRNG gives 0xB4. -#define TRNG_HWVER0_EIP_NUM_COMPL_W 8 -#define TRNG_HWVER0_EIP_NUM_COMPL_M 0x0000FF00 -#define TRNG_HWVER0_EIP_NUM_COMPL_S 8 +#define TRNG_HWVER0_EIP_NUM_COMPL_W 8 +#define TRNG_HWVER0_EIP_NUM_COMPL_M 0x0000FF00 +#define TRNG_HWVER0_EIP_NUM_COMPL_S 8 // Field: [7:0] EIP_NUM // // 8 bits binary encoding of the module number. This TRNG gives 0x4B. -#define TRNG_HWVER0_EIP_NUM_W 8 -#define TRNG_HWVER0_EIP_NUM_M 0x000000FF -#define TRNG_HWVER0_EIP_NUM_S 0 +#define TRNG_HWVER0_EIP_NUM_W 8 +#define TRNG_HWVER0_EIP_NUM_M 0x000000FF +#define TRNG_HWVER0_EIP_NUM_S 0 //***************************************************************************** // @@ -546,19 +546,19 @@ // // Shutdown Overflow (result of IRQFLAGSTAT.SHUTDOWN_OVF AND'ed with // IRQFLAGMASK.SHUTDOWN_OVF) -#define TRNG_IRQSTATMASK_SHUTDOWN_OVF 0x00000002 -#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_BITN 1 -#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_M 0x00000002 -#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_S 1 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_S 1 // Field: [0] RDY // // New random value available (result of IRQFLAGSTAT.RDY AND'ed with // IRQFLAGMASK.RDY) -#define TRNG_IRQSTATMASK_RDY 0x00000001 -#define TRNG_IRQSTATMASK_RDY_BITN 0 -#define TRNG_IRQSTATMASK_RDY_M 0x00000001 -#define TRNG_IRQSTATMASK_RDY_S 0 +#define TRNG_IRQSTATMASK_RDY 0x00000001 +#define TRNG_IRQSTATMASK_RDY_BITN 0 +#define TRNG_IRQSTATMASK_RDY_M 0x00000001 +#define TRNG_IRQSTATMASK_RDY_S 0 //***************************************************************************** // @@ -568,9 +568,9 @@ // Field: [7:0] REV // // The revision number of this module is Rev 2.0. -#define TRNG_HWVER1_REV_W 8 -#define TRNG_HWVER1_REV_M 0x000000FF -#define TRNG_HWVER1_REV_S 0 +#define TRNG_HWVER1_REV_W 8 +#define TRNG_HWVER1_REV_M 0x000000FF +#define TRNG_HWVER1_REV_S 0 //***************************************************************************** // @@ -586,10 +586,10 @@ // // Write '1' to soft reset , reset will be low for 4-5 clock cycles. Poll to 0 // for reset to be completed. -#define TRNG_SWRESET_RESET 0x00000001 -#define TRNG_SWRESET_RESET_BITN 0 -#define TRNG_SWRESET_RESET_M 0x00000001 -#define TRNG_SWRESET_RESET_S 0 +#define TRNG_SWRESET_RESET 0x00000001 +#define TRNG_SWRESET_RESET_BITN 0 +#define TRNG_SWRESET_RESET_M 0x00000001 +#define TRNG_SWRESET_RESET_S 0 //***************************************************************************** // @@ -600,10 +600,9 @@ // // TRNG Interrupt status. OR'ed version of IRQFLAGSTAT.SHUTDOWN_OVF and // IRQFLAGSTAT.RDY -#define TRNG_IRQSTAT_STAT 0x00000001 -#define TRNG_IRQSTAT_STAT_BITN 0 -#define TRNG_IRQSTAT_STAT_M 0x00000001 -#define TRNG_IRQSTAT_STAT_S 0 - +#define TRNG_IRQSTAT_STAT 0x00000001 +#define TRNG_IRQSTAT_STAT_BITN 0 +#define TRNG_IRQSTAT_STAT_M 0x00000001 +#define TRNG_IRQSTAT_STAT_S 0 #endif // __TRNG__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_types.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_types.h index 142601b..c92d027 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_types.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_types.h @@ -1,55 +1,55 @@ /****************************************************************************** -* Filename: hw_types.h -* Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) -* Revision: 47152 -* -* Description: Common types and macros. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_types.h + * Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) + * Revision: 47152 + * + * Description: Common types and macros. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_TYPES_H__ #define __HW_TYPES_H__ -#include -#include #include "../inc/hw_chip_def.h" +#include +#include //***************************************************************************** // // Common driverlib types // //***************************************************************************** -typedef void (* FPTR_VOID_VOID_T) (void); -typedef void (* FPTR_VOID_UINT8_T) (uint8_t); +typedef void (*FPTR_VOID_VOID_T)(void); +typedef void (*FPTR_VOID_UINT8_T)(uint8_t); //***************************************************************************** // @@ -58,7 +58,7 @@ typedef void (* FPTR_VOID_UINT8_T) (uint8_t); // //***************************************************************************** #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline +#define __STATIC_INLINE static inline #endif //***************************************************************************** @@ -66,7 +66,7 @@ typedef void (* FPTR_VOID_UINT8_T) (uint8_t); // C99 types only allows bitfield defintions on certain datatypes. // //***************************************************************************** -typedef unsigned int __UINT32; +typedef unsigned int __UINT32; //***************************************************************************** // @@ -79,19 +79,19 @@ typedef unsigned int __UINT32; // Word (32 bit) access to address x // Read example : my32BitVar = HWREG(base_addr + offset) ; // Write example : HWREG(base_addr + offset) = my32BitVar ; -#define HWREG(x) \ +#define HWREG(x) \ (*((volatile unsigned long *)(x))) // Half word (16 bit) access to address x // Read example : my16BitVar = HWREGH(base_addr + offset) ; // Write example : HWREGH(base_addr + offset) = my16BitVar ; -#define HWREGH(x) \ +#define HWREGH(x) \ (*((volatile unsigned short *)(x))) // Byte (8 bit) access to address x // Read example : my8BitVar = HWREGB(base_addr + offset) ; // Write example : HWREGB(base_addr + offset) = my8BitVar ; -#define HWREGB(x) \ +#define HWREGB(x) \ (*((volatile unsigned char *)(x))) //***************************************************************************** @@ -105,19 +105,18 @@ typedef unsigned int __UINT32; // //***************************************************************************** // Bit-band access to address x bit number b using word access (32 bit) -#define HWREGBITW(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) // Bit-band access to address x bit number b using half word access (16 bit) -#define HWREGBITH(x, b) \ - HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) // Bit-band access to address x bit number b using byte access (8 bit) -#define HWREGBITB(x, b) \ - HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - #endif // __HW_TYPES_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_uart.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_uart.h index f0b1bab..3d90b1e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_uart.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_uart.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_uart_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_uart_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_UART_H__ #define __HW_UART_H__ @@ -44,46 +44,46 @@ // //***************************************************************************** // Data -#define UART_O_DR 0x00000000 +#define UART_O_DR 0x00000000 // Status -#define UART_O_RSR 0x00000004 +#define UART_O_RSR 0x00000004 // Error Clear -#define UART_O_ECR 0x00000004 +#define UART_O_ECR 0x00000004 // Flag -#define UART_O_FR 0x00000018 +#define UART_O_FR 0x00000018 // Integer Baud-Rate Divisor -#define UART_O_IBRD 0x00000024 +#define UART_O_IBRD 0x00000024 // Fractional Baud-Rate Divisor -#define UART_O_FBRD 0x00000028 +#define UART_O_FBRD 0x00000028 // Line Control -#define UART_O_LCRH 0x0000002C +#define UART_O_LCRH 0x0000002C // Control -#define UART_O_CTL 0x00000030 +#define UART_O_CTL 0x00000030 // Interrupt FIFO Level Select -#define UART_O_IFLS 0x00000034 +#define UART_O_IFLS 0x00000034 // Interrupt Mask Set/Clear -#define UART_O_IMSC 0x00000038 +#define UART_O_IMSC 0x00000038 // Raw Interrupt Status -#define UART_O_RIS 0x0000003C +#define UART_O_RIS 0x0000003C // Masked Interrupt Status -#define UART_O_MIS 0x00000040 +#define UART_O_MIS 0x00000040 // Interrupt Clear -#define UART_O_ICR 0x00000044 +#define UART_O_ICR 0x00000044 // DMA Control -#define UART_O_DMACTL 0x00000048 +#define UART_O_DMACTL 0x00000048 //***************************************************************************** // @@ -98,10 +98,10 @@ // the FIFO is full, , only the contents of the shift register are overwritten. // This is cleared to 0 once there is an empty space in the FIFO and a new // character can be written to it. -#define UART_DR_OE 0x00000800 -#define UART_DR_OE_BITN 11 -#define UART_DR_OE_M 0x00000800 -#define UART_DR_OE_S 11 +#define UART_DR_OE 0x00000800 +#define UART_DR_OE_BITN 11 +#define UART_DR_OE_M 0x00000800 +#define UART_DR_OE_S 11 // Field: [10] BE // @@ -114,10 +114,10 @@ // break occurs, a 0 character is loaded into the FIFO. The next character is // enabled after the receive data input (UARTRXD input pin) goes to a 1 // (marking state), and the next valid start bit is received. -#define UART_DR_BE 0x00000400 -#define UART_DR_BE_BITN 10 -#define UART_DR_BE_M 0x00000400 -#define UART_DR_BE_S 10 +#define UART_DR_BE 0x00000400 +#define UART_DR_BE_BITN 10 +#define UART_DR_BE_M 0x00000400 +#define UART_DR_BE_S 10 // Field: [9] PE // @@ -126,10 +126,10 @@ // does not match the parity that the LCRH.EPS and LCRH.SPS select. // In FIFO mode, this error is associated with the character at the top of the // FIFO (that is, the oldest received data character since last read). -#define UART_DR_PE 0x00000200 -#define UART_DR_PE_BITN 9 -#define UART_DR_PE_M 0x00000200 -#define UART_DR_PE_S 9 +#define UART_DR_PE 0x00000200 +#define UART_DR_PE_BITN 9 +#define UART_DR_PE_M 0x00000200 +#define UART_DR_PE_S 9 // Field: [8] FE // @@ -138,10 +138,10 @@ // stop bit (a valid stop bit is 1). // In FIFO mode, this error is associated with the character at the top of the // FIFO (that is., the oldest received data character since last read). -#define UART_DR_FE 0x00000100 -#define UART_DR_FE_BITN 8 -#define UART_DR_FE_M 0x00000100 -#define UART_DR_FE_S 8 +#define UART_DR_FE 0x00000100 +#define UART_DR_FE_BITN 8 +#define UART_DR_FE_M 0x00000100 +#define UART_DR_FE_S 8 // Field: [7:0] DATA // @@ -149,9 +149,9 @@ // On writes, the transmit data character is pushed into the FIFO. // On reads, the oldest received data character since the last read is // returned. -#define UART_DR_DATA_W 8 -#define UART_DR_DATA_M 0x000000FF -#define UART_DR_DATA_S 0 +#define UART_DR_DATA_W 8 +#define UART_DR_DATA_M 0x000000FF +#define UART_DR_DATA_S 0 //***************************************************************************** // @@ -166,10 +166,10 @@ // the FIFO is full, , only the contents of the shift register are overwritten. // This is cleared to 0 once there is an empty space in the FIFO and a new // character can be written to it. -#define UART_RSR_OE 0x00000008 -#define UART_RSR_OE_BITN 3 -#define UART_RSR_OE_M 0x00000008 -#define UART_RSR_OE_S 3 +#define UART_RSR_OE 0x00000008 +#define UART_RSR_OE_BITN 3 +#define UART_RSR_OE_M 0x00000008 +#define UART_RSR_OE_S 3 // Field: [2] BE // @@ -180,30 +180,30 @@ // When a break occurs, a 0 character is loaded into the FIFO. The next // character is enabled after the receive data input (UARTRXD input pin) goes // to a 1 (marking state), and the next valid start bit is received. -#define UART_RSR_BE 0x00000004 -#define UART_RSR_BE_BITN 2 -#define UART_RSR_BE_M 0x00000004 -#define UART_RSR_BE_S 2 +#define UART_RSR_BE 0x00000004 +#define UART_RSR_BE_BITN 2 +#define UART_RSR_BE_M 0x00000004 +#define UART_RSR_BE_S 2 // Field: [1] PE // // UART Parity Error: // When set to 1, it indicates that the parity of the received data character // does not match the parity that the LCRH.EPS and LCRH.SPS select. -#define UART_RSR_PE 0x00000002 -#define UART_RSR_PE_BITN 1 -#define UART_RSR_PE_M 0x00000002 -#define UART_RSR_PE_S 1 +#define UART_RSR_PE 0x00000002 +#define UART_RSR_PE_BITN 1 +#define UART_RSR_PE_M 0x00000002 +#define UART_RSR_PE_S 1 // Field: [0] FE // // UART Framing Error: // When set to 1, it indicates that the received character did not have a valid // stop bit (a valid stop bit is 1). -#define UART_RSR_FE 0x00000001 -#define UART_RSR_FE_BITN 0 -#define UART_RSR_FE_M 0x00000001 -#define UART_RSR_FE_S 0 +#define UART_RSR_FE 0x00000001 +#define UART_RSR_FE_BITN 0 +#define UART_RSR_FE_M 0x00000001 +#define UART_RSR_FE_S 0 //***************************************************************************** // @@ -214,37 +214,37 @@ // // The framing (FE), parity (PE), break (BE) and overrun (OE) errors are // cleared to 0 by any write to this register. -#define UART_ECR_OE 0x00000008 -#define UART_ECR_OE_BITN 3 -#define UART_ECR_OE_M 0x00000008 -#define UART_ECR_OE_S 3 +#define UART_ECR_OE 0x00000008 +#define UART_ECR_OE_BITN 3 +#define UART_ECR_OE_M 0x00000008 +#define UART_ECR_OE_S 3 // Field: [2] BE // // The framing (FE), parity (PE), break (BE) and overrun (OE) errors are // cleared to 0 by any write to this register. -#define UART_ECR_BE 0x00000004 -#define UART_ECR_BE_BITN 2 -#define UART_ECR_BE_M 0x00000004 -#define UART_ECR_BE_S 2 +#define UART_ECR_BE 0x00000004 +#define UART_ECR_BE_BITN 2 +#define UART_ECR_BE_M 0x00000004 +#define UART_ECR_BE_S 2 // Field: [1] PE // // The framing (FE), parity (PE), break (BE) and overrun (OE) errors are // cleared to 0 by any write to this register. -#define UART_ECR_PE 0x00000002 -#define UART_ECR_PE_BITN 1 -#define UART_ECR_PE_M 0x00000002 -#define UART_ECR_PE_S 1 +#define UART_ECR_PE 0x00000002 +#define UART_ECR_PE_BITN 1 +#define UART_ECR_PE_M 0x00000002 +#define UART_ECR_PE_S 1 // Field: [0] FE // // The framing (FE), parity (PE), break (BE) and overrun (OE) errors are // cleared to 0 by any write to this register. -#define UART_ECR_FE 0x00000001 -#define UART_ECR_FE_BITN 0 -#define UART_ECR_FE_M 0x00000001 -#define UART_ECR_FE_S 0 +#define UART_ECR_FE 0x00000001 +#define UART_ECR_FE_BITN 0 +#define UART_ECR_FE_M 0x00000001 +#define UART_ECR_FE_S 0 //***************************************************************************** // @@ -259,10 +259,10 @@ // register is empty. // - If the FIFO is enabled, this bit is set when the transmit FIFO is empty. // This bit does not indicate if there is data in the transmit shift register. -#define UART_FR_TXFE 0x00000080 -#define UART_FR_TXFE_BITN 7 -#define UART_FR_TXFE_M 0x00000080 -#define UART_FR_TXFE_S 7 +#define UART_FR_TXFE 0x00000080 +#define UART_FR_TXFE_BITN 7 +#define UART_FR_TXFE_M 0x00000080 +#define UART_FR_TXFE_S 7 // Field: [6] RXFF // @@ -271,10 +271,10 @@ // - If the FIFO is disabled, this bit is set when the receive holding // register is full. // - If the FIFO is enabled, this bit is set when the receive FIFO is full. -#define UART_FR_RXFF 0x00000040 -#define UART_FR_RXFF_BITN 6 -#define UART_FR_RXFF_M 0x00000040 -#define UART_FR_RXFF_S 6 +#define UART_FR_RXFF 0x00000040 +#define UART_FR_RXFF_BITN 6 +#define UART_FR_RXFF_M 0x00000040 +#define UART_FR_RXFF_S 6 // Field: [5] TXFF // @@ -284,10 +284,10 @@ // - If the FIFO is disabled, this bit is set when the transmit holding // register is full. // - If the FIFO is enabled, this bit is set when the transmit FIFO is full. -#define UART_FR_TXFF 0x00000020 -#define UART_FR_TXFF_BITN 5 -#define UART_FR_TXFF_M 0x00000020 -#define UART_FR_TXFF_S 5 +#define UART_FR_TXFF 0x00000020 +#define UART_FR_TXFF_BITN 5 +#define UART_FR_TXFF_M 0x00000020 +#define UART_FR_TXFF_S 5 // Field: [4] RXFE // @@ -297,10 +297,10 @@ // - If the FIFO is disabled, this bit is set when the receive holding // register is empty. // - If the FIFO is enabled, this bit is set when the receive FIFO is empty. -#define UART_FR_RXFE 0x00000010 -#define UART_FR_RXFE_BITN 4 -#define UART_FR_RXFE_M 0x00000010 -#define UART_FR_RXFE_S 4 +#define UART_FR_RXFE 0x00000010 +#define UART_FR_RXFE_BITN 4 +#define UART_FR_RXFE_M 0x00000010 +#define UART_FR_RXFE_S 4 // Field: [3] BUSY // @@ -310,20 +310,20 @@ // sent from the shift register. // This bit is set as soon as the transmit FIFO becomes non-empty, regardless // of whether the UART is enabled or not. -#define UART_FR_BUSY 0x00000008 -#define UART_FR_BUSY_BITN 3 -#define UART_FR_BUSY_M 0x00000008 -#define UART_FR_BUSY_S 3 +#define UART_FR_BUSY 0x00000008 +#define UART_FR_BUSY_BITN 3 +#define UART_FR_BUSY_M 0x00000008 +#define UART_FR_BUSY_S 3 // Field: [0] CTS // // Clear To Send: // This bit is the complement of the active-low UART CTS input pin. // That is, the bit is 1 when CTS input pin is LOW. -#define UART_FR_CTS 0x00000001 -#define UART_FR_CTS_BITN 0 -#define UART_FR_CTS_M 0x00000001 -#define UART_FR_CTS_S 0 +#define UART_FR_CTS 0x00000001 +#define UART_FR_CTS_BITN 0 +#define UART_FR_CTS_M 0x00000001 +#define UART_FR_CTS_S 0 //***************************************************************************** // @@ -341,9 +341,9 @@ // illegal. // A valid value must be written to this field before the UART can be used for // RX or TX operations. -#define UART_IBRD_DIVINT_W 16 -#define UART_IBRD_DIVINT_M 0x0000FFFF -#define UART_IBRD_DIVINT_S 0 +#define UART_IBRD_DIVINT_W 16 +#define UART_IBRD_DIVINT_M 0x0000FFFF +#define UART_IBRD_DIVINT_S 0 //***************************************************************************** // @@ -361,9 +361,9 @@ // illegal. // A valid value must be written to this field before the UART can be used for // RX or TX operations. -#define UART_FBRD_DIVFRAC_W 6 -#define UART_FBRD_DIVFRAC_M 0x0000003F -#define UART_FBRD_DIVFRAC_S 0 +#define UART_FBRD_DIVFRAC_W 6 +#define UART_FBRD_DIVFRAC_M 0x0000003F +#define UART_FBRD_DIVFRAC_S 0 //***************************************************************************** // @@ -379,10 +379,10 @@ // the parity bit is transmitted and checked as 1 when EPS = 0). // // This bit has no effect when PEN disables parity checking and generation. -#define UART_LCRH_SPS 0x00000080 -#define UART_LCRH_SPS_BITN 7 -#define UART_LCRH_SPS_M 0x00000080 -#define UART_LCRH_SPS_S 7 +#define UART_LCRH_SPS 0x00000080 +#define UART_LCRH_SPS_BITN 7 +#define UART_LCRH_SPS_M 0x00000080 +#define UART_LCRH_SPS_S 7 // Field: [6:5] WLEN // @@ -394,13 +394,13 @@ // 7 Word Length 7 bits // 6 Word Length 6 bits // 5 Word Length 5 bits -#define UART_LCRH_WLEN_W 2 -#define UART_LCRH_WLEN_M 0x00000060 -#define UART_LCRH_WLEN_S 5 -#define UART_LCRH_WLEN_8 0x00000060 -#define UART_LCRH_WLEN_7 0x00000040 -#define UART_LCRH_WLEN_6 0x00000020 -#define UART_LCRH_WLEN_5 0x00000000 +#define UART_LCRH_WLEN_W 2 +#define UART_LCRH_WLEN_M 0x00000060 +#define UART_LCRH_WLEN_S 5 +#define UART_LCRH_WLEN_8 0x00000060 +#define UART_LCRH_WLEN_7 0x00000040 +#define UART_LCRH_WLEN_6 0x00000020 +#define UART_LCRH_WLEN_5 0x00000000 // Field: [4] FEN // @@ -410,22 +410,22 @@ // (FIFO mode) // DIS FIFOs are disabled (character mode) that is, the // FIFOs become 1-byte-deep holding registers. -#define UART_LCRH_FEN 0x00000010 -#define UART_LCRH_FEN_BITN 4 -#define UART_LCRH_FEN_M 0x00000010 -#define UART_LCRH_FEN_S 4 -#define UART_LCRH_FEN_EN 0x00000010 -#define UART_LCRH_FEN_DIS 0x00000000 +#define UART_LCRH_FEN 0x00000010 +#define UART_LCRH_FEN_BITN 4 +#define UART_LCRH_FEN_M 0x00000010 +#define UART_LCRH_FEN_S 4 +#define UART_LCRH_FEN_EN 0x00000010 +#define UART_LCRH_FEN_DIS 0x00000000 // Field: [3] STP2 // // UART Two Stop Bits Select: // If this bit is set to 1, two stop bits are transmitted at the end of the // frame. The receive logic does not check for two stop bits being received. -#define UART_LCRH_STP2 0x00000008 -#define UART_LCRH_STP2_BITN 3 -#define UART_LCRH_STP2_M 0x00000008 -#define UART_LCRH_STP2_S 3 +#define UART_LCRH_STP2 0x00000008 +#define UART_LCRH_STP2_BITN 3 +#define UART_LCRH_STP2_M 0x00000008 +#define UART_LCRH_STP2_S 3 // Field: [2] EPS // @@ -435,12 +435,12 @@ // even number of 1s in the data and parity bits. // ODD Odd parity: The UART generates or checks for an // odd number of 1s in the data and parity bits. -#define UART_LCRH_EPS 0x00000004 -#define UART_LCRH_EPS_BITN 2 -#define UART_LCRH_EPS_M 0x00000004 -#define UART_LCRH_EPS_S 2 -#define UART_LCRH_EPS_EVEN 0x00000004 -#define UART_LCRH_EPS_ODD 0x00000000 +#define UART_LCRH_EPS 0x00000004 +#define UART_LCRH_EPS_BITN 2 +#define UART_LCRH_EPS_M 0x00000004 +#define UART_LCRH_EPS_S 2 +#define UART_LCRH_EPS_EVEN 0x00000004 +#define UART_LCRH_EPS_ODD 0x00000000 // Field: [1] PEN // @@ -450,12 +450,12 @@ // EN Parity checking and generation is enabled. // DIS Parity is disabled and no parity bit is added to // the data frame -#define UART_LCRH_PEN 0x00000002 -#define UART_LCRH_PEN_BITN 1 -#define UART_LCRH_PEN_M 0x00000002 -#define UART_LCRH_PEN_S 1 -#define UART_LCRH_PEN_EN 0x00000002 -#define UART_LCRH_PEN_DIS 0x00000000 +#define UART_LCRH_PEN 0x00000002 +#define UART_LCRH_PEN_BITN 1 +#define UART_LCRH_PEN_M 0x00000002 +#define UART_LCRH_PEN_S 1 +#define UART_LCRH_PEN_EN 0x00000002 +#define UART_LCRH_PEN_DIS 0x00000000 // Field: [0] BRK // @@ -465,10 +465,10 @@ // proper execution of the break command, the // software must set this bit for at least two complete frames. For normal use, // this bit must be cleared to 0. -#define UART_LCRH_BRK 0x00000001 -#define UART_LCRH_BRK_BITN 0 -#define UART_LCRH_BRK_M 0x00000001 -#define UART_LCRH_BRK_S 0 +#define UART_LCRH_BRK 0x00000001 +#define UART_LCRH_BRK_BITN 0 +#define UART_LCRH_BRK_M 0x00000001 +#define UART_LCRH_BRK_S 0 //***************************************************************************** // @@ -481,12 +481,12 @@ // ENUMs: // EN CTS hardware flow control enabled // DIS CTS hardware flow control disabled -#define UART_CTL_CTSEN 0x00008000 -#define UART_CTL_CTSEN_BITN 15 -#define UART_CTL_CTSEN_M 0x00008000 -#define UART_CTL_CTSEN_S 15 -#define UART_CTL_CTSEN_EN 0x00008000 -#define UART_CTL_CTSEN_DIS 0x00000000 +#define UART_CTL_CTSEN 0x00008000 +#define UART_CTL_CTSEN_BITN 15 +#define UART_CTL_CTSEN_M 0x00008000 +#define UART_CTL_CTSEN_S 15 +#define UART_CTL_CTSEN_EN 0x00008000 +#define UART_CTL_CTSEN_DIS 0x00000000 // Field: [14] RTSEN // @@ -494,22 +494,22 @@ // ENUMs: // EN RTS hardware flow control enabled // DIS RTS hardware flow control disabled -#define UART_CTL_RTSEN 0x00004000 -#define UART_CTL_RTSEN_BITN 14 -#define UART_CTL_RTSEN_M 0x00004000 -#define UART_CTL_RTSEN_S 14 -#define UART_CTL_RTSEN_EN 0x00004000 -#define UART_CTL_RTSEN_DIS 0x00000000 +#define UART_CTL_RTSEN 0x00004000 +#define UART_CTL_RTSEN_BITN 14 +#define UART_CTL_RTSEN_M 0x00004000 +#define UART_CTL_RTSEN_S 14 +#define UART_CTL_RTSEN_EN 0x00004000 +#define UART_CTL_RTSEN_DIS 0x00000000 // Field: [11] RTS // // Request to Send // This bit is the complement of the active-low UART RTS output. That is, when // the bit is programmed to a 1 then RTS output on the pins is LOW. -#define UART_CTL_RTS 0x00000800 -#define UART_CTL_RTS_BITN 11 -#define UART_CTL_RTS_M 0x00000800 -#define UART_CTL_RTS_S 11 +#define UART_CTL_RTS 0x00000800 +#define UART_CTL_RTS_BITN 11 +#define UART_CTL_RTS_M 0x00000800 +#define UART_CTL_RTS_S 11 // Field: [9] RXE // @@ -519,12 +519,12 @@ // ENUMs: // EN UART Receive enabled // DIS UART Receive disabled -#define UART_CTL_RXE 0x00000200 -#define UART_CTL_RXE_BITN 9 -#define UART_CTL_RXE_M 0x00000200 -#define UART_CTL_RXE_S 9 -#define UART_CTL_RXE_EN 0x00000200 -#define UART_CTL_RXE_DIS 0x00000000 +#define UART_CTL_RXE 0x00000200 +#define UART_CTL_RXE_BITN 9 +#define UART_CTL_RXE_M 0x00000200 +#define UART_CTL_RXE_S 9 +#define UART_CTL_RXE_EN 0x00000200 +#define UART_CTL_RXE_DIS 0x00000000 // Field: [8] TXE // @@ -534,12 +534,12 @@ // ENUMs: // EN UART Transmit enabled // DIS UART Transmit disabled -#define UART_CTL_TXE 0x00000100 -#define UART_CTL_TXE_BITN 8 -#define UART_CTL_TXE_M 0x00000100 -#define UART_CTL_TXE_S 8 -#define UART_CTL_TXE_EN 0x00000100 -#define UART_CTL_TXE_DIS 0x00000000 +#define UART_CTL_TXE 0x00000100 +#define UART_CTL_TXE_BITN 8 +#define UART_CTL_TXE_M 0x00000100 +#define UART_CTL_TXE_S 8 +#define UART_CTL_TXE_EN 0x00000100 +#define UART_CTL_TXE_DIS 0x00000000 // Field: [7] LBE // @@ -549,12 +549,12 @@ // ENUMs: // EN Loop Back enabled // DIS Loop Back disabled -#define UART_CTL_LBE 0x00000080 -#define UART_CTL_LBE_BITN 7 -#define UART_CTL_LBE_M 0x00000080 -#define UART_CTL_LBE_S 7 -#define UART_CTL_LBE_EN 0x00000080 -#define UART_CTL_LBE_DIS 0x00000000 +#define UART_CTL_LBE 0x00000080 +#define UART_CTL_LBE_BITN 7 +#define UART_CTL_LBE_M 0x00000080 +#define UART_CTL_LBE_S 7 +#define UART_CTL_LBE_EN 0x00000080 +#define UART_CTL_LBE_DIS 0x00000000 // Field: [0] UARTEN // @@ -562,12 +562,12 @@ // ENUMs: // EN UART enabled // DIS UART disabled -#define UART_CTL_UARTEN 0x00000001 -#define UART_CTL_UARTEN_BITN 0 -#define UART_CTL_UARTEN_M 0x00000001 -#define UART_CTL_UARTEN_S 0 -#define UART_CTL_UARTEN_EN 0x00000001 -#define UART_CTL_UARTEN_DIS 0x00000000 +#define UART_CTL_UARTEN 0x00000001 +#define UART_CTL_UARTEN_BITN 0 +#define UART_CTL_UARTEN_M 0x00000001 +#define UART_CTL_UARTEN_S 0 +#define UART_CTL_UARTEN_EN 0x00000001 +#define UART_CTL_UARTEN_DIS 0x00000000 //***************************************************************************** // @@ -585,14 +585,14 @@ // 4_8 Receive FIFO becomes >= 1/2 full // 2_8 Receive FIFO becomes >= 1/4 full // 1_8 Receive FIFO becomes >= 1/8 full -#define UART_IFLS_RXSEL_W 3 -#define UART_IFLS_RXSEL_M 0x00000038 -#define UART_IFLS_RXSEL_S 3 -#define UART_IFLS_RXSEL_7_8 0x00000020 -#define UART_IFLS_RXSEL_6_8 0x00000018 -#define UART_IFLS_RXSEL_4_8 0x00000010 -#define UART_IFLS_RXSEL_2_8 0x00000008 -#define UART_IFLS_RXSEL_1_8 0x00000000 +#define UART_IFLS_RXSEL_W 3 +#define UART_IFLS_RXSEL_M 0x00000038 +#define UART_IFLS_RXSEL_S 3 +#define UART_IFLS_RXSEL_7_8 0x00000020 +#define UART_IFLS_RXSEL_6_8 0x00000018 +#define UART_IFLS_RXSEL_4_8 0x00000010 +#define UART_IFLS_RXSEL_2_8 0x00000008 +#define UART_IFLS_RXSEL_1_8 0x00000000 // Field: [2:0] TXSEL // @@ -605,14 +605,14 @@ // 4_8 Transmit FIFO becomes <= 1/2 full // 2_8 Transmit FIFO becomes <= 1/4 full // 1_8 Transmit FIFO becomes <= 1/8 full -#define UART_IFLS_TXSEL_W 3 -#define UART_IFLS_TXSEL_M 0x00000007 -#define UART_IFLS_TXSEL_S 0 -#define UART_IFLS_TXSEL_7_8 0x00000004 -#define UART_IFLS_TXSEL_6_8 0x00000003 -#define UART_IFLS_TXSEL_4_8 0x00000002 -#define UART_IFLS_TXSEL_2_8 0x00000001 -#define UART_IFLS_TXSEL_1_8 0x00000000 +#define UART_IFLS_TXSEL_W 3 +#define UART_IFLS_TXSEL_M 0x00000007 +#define UART_IFLS_TXSEL_S 0 +#define UART_IFLS_TXSEL_7_8 0x00000004 +#define UART_IFLS_TXSEL_6_8 0x00000003 +#define UART_IFLS_TXSEL_4_8 0x00000002 +#define UART_IFLS_TXSEL_2_8 0x00000001 +#define UART_IFLS_TXSEL_1_8 0x00000000 //***************************************************************************** // @@ -625,10 +625,10 @@ // UART's EoT interrupt. On a write of 1, the mask of the EoT interrupt is set // which means the interrupt state will be reflected in MIS.EOTMIS. A write of // 0 clears the mask which means MIS.EOTMIS will not reflect the interrupt. -#define UART_IMSC_EOTIM 0x00000800 -#define UART_IMSC_EOTIM_BITN 11 -#define UART_IMSC_EOTIM_M 0x00000800 -#define UART_IMSC_EOTIM_S 11 +#define UART_IMSC_EOTIM 0x00000800 +#define UART_IMSC_EOTIM_BITN 11 +#define UART_IMSC_EOTIM_M 0x00000800 +#define UART_IMSC_EOTIM_S 11 // Field: [10] OEIM // @@ -637,10 +637,10 @@ // interrupt is set which means the interrupt state will be reflected in // MIS.OEMIS. A write of 0 clears the mask which means MIS.OEMIS will not // reflect the interrupt. -#define UART_IMSC_OEIM 0x00000400 -#define UART_IMSC_OEIM_BITN 10 -#define UART_IMSC_OEIM_M 0x00000400 -#define UART_IMSC_OEIM_S 10 +#define UART_IMSC_OEIM 0x00000400 +#define UART_IMSC_OEIM_BITN 10 +#define UART_IMSC_OEIM_M 0x00000400 +#define UART_IMSC_OEIM_S 10 // Field: [9] BEIM // @@ -648,10 +648,10 @@ // error interrupt. On a write of 1, the mask of the overrun error interrupt is // set which means the interrupt state will be reflected in MIS.BEMIS. A write // of 0 clears the mask which means MIS.BEMIS will not reflect the interrupt. -#define UART_IMSC_BEIM 0x00000200 -#define UART_IMSC_BEIM_BITN 9 -#define UART_IMSC_BEIM_M 0x00000200 -#define UART_IMSC_BEIM_S 9 +#define UART_IMSC_BEIM 0x00000200 +#define UART_IMSC_BEIM_BITN 9 +#define UART_IMSC_BEIM_M 0x00000200 +#define UART_IMSC_BEIM_S 9 // Field: [8] PEIM // @@ -660,10 +660,10 @@ // interrupt is set which means the interrupt state will be reflected in // MIS.PEMIS. A write of 0 clears the mask which means MIS.PEMIS will not // reflect the interrupt. -#define UART_IMSC_PEIM 0x00000100 -#define UART_IMSC_PEIM_BITN 8 -#define UART_IMSC_PEIM_M 0x00000100 -#define UART_IMSC_PEIM_S 8 +#define UART_IMSC_PEIM 0x00000100 +#define UART_IMSC_PEIM_BITN 8 +#define UART_IMSC_PEIM_M 0x00000100 +#define UART_IMSC_PEIM_S 8 // Field: [7] FEIM // @@ -672,10 +672,10 @@ // interrupt is set which means the interrupt state will be reflected in // MIS.FEMIS. A write of 0 clears the mask which means MIS.FEMIS will not // reflect the interrupt. -#define UART_IMSC_FEIM 0x00000080 -#define UART_IMSC_FEIM_BITN 7 -#define UART_IMSC_FEIM_M 0x00000080 -#define UART_IMSC_FEIM_S 7 +#define UART_IMSC_FEIM 0x00000080 +#define UART_IMSC_FEIM_BITN 7 +#define UART_IMSC_FEIM_M 0x00000080 +#define UART_IMSC_FEIM_S 7 // Field: [6] RTIM // @@ -687,10 +687,10 @@ // The raw interrupt for receive timeout RIS.RTRIS cannot be set unless the // mask is set (RTIM = 1). This is because the mask acts as an enable for power // saving. That is, the same status can be read from MIS.RTMIS and RIS.RTRIS. -#define UART_IMSC_RTIM 0x00000040 -#define UART_IMSC_RTIM_BITN 6 -#define UART_IMSC_RTIM_M 0x00000040 -#define UART_IMSC_RTIM_S 6 +#define UART_IMSC_RTIM 0x00000040 +#define UART_IMSC_RTIM_BITN 6 +#define UART_IMSC_RTIM_M 0x00000040 +#define UART_IMSC_RTIM_S 6 // Field: [5] TXIM // @@ -698,10 +698,10 @@ // interrupt. On a write of 1, the mask of the overrun error interrupt is set // which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 // clears the mask which means MIS.TXMIS will not reflect the interrupt. -#define UART_IMSC_TXIM 0x00000020 -#define UART_IMSC_TXIM_BITN 5 -#define UART_IMSC_TXIM_M 0x00000020 -#define UART_IMSC_TXIM_S 5 +#define UART_IMSC_TXIM 0x00000020 +#define UART_IMSC_TXIM_BITN 5 +#define UART_IMSC_TXIM_M 0x00000020 +#define UART_IMSC_TXIM_S 5 // Field: [4] RXIM // @@ -709,10 +709,10 @@ // interrupt. On a write of 1, the mask of the overrun error interrupt is set // which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 // clears the mask which means MIS.RXMIS will not reflect the interrupt. -#define UART_IMSC_RXIM 0x00000010 -#define UART_IMSC_RXIM_BITN 4 -#define UART_IMSC_RXIM_M 0x00000010 -#define UART_IMSC_RXIM_S 4 +#define UART_IMSC_RXIM 0x00000010 +#define UART_IMSC_RXIM_BITN 4 +#define UART_IMSC_RXIM_M 0x00000010 +#define UART_IMSC_RXIM_S 4 // Field: [1] CTSMIM // @@ -721,10 +721,10 @@ // error interrupt is set which means the interrupt state will be reflected in // MIS.CTSMMIS. A write of 0 clears the mask which means MIS.CTSMMIS will not // reflect the interrupt. -#define UART_IMSC_CTSMIM 0x00000002 -#define UART_IMSC_CTSMIM_BITN 1 -#define UART_IMSC_CTSMIM_M 0x00000002 -#define UART_IMSC_CTSMIM_S 1 +#define UART_IMSC_CTSMIM 0x00000002 +#define UART_IMSC_CTSMIM_BITN 1 +#define UART_IMSC_CTSMIM_M 0x00000002 +#define UART_IMSC_CTSMIM_S 1 //***************************************************************************** // @@ -737,10 +737,10 @@ // This field returns the raw interrupt state of UART's end of transmission // interrupt. End of transmission flag is set when all the Transmit data in the // FIFO and on the TX Line is tranmitted. -#define UART_RIS_EOTRIS 0x00000800 -#define UART_RIS_EOTRIS_BITN 11 -#define UART_RIS_EOTRIS_M 0x00000800 -#define UART_RIS_EOTRIS_S 11 +#define UART_RIS_EOTRIS 0x00000800 +#define UART_RIS_EOTRIS_BITN 11 +#define UART_RIS_EOTRIS_M 0x00000800 +#define UART_RIS_EOTRIS_S 11 // Field: [10] OERIS // @@ -748,10 +748,10 @@ // This field returns the raw interrupt state of UART's overrun error // interrupt. Overrun error occurs if data is received and the receive FIFO is // full. -#define UART_RIS_OERIS 0x00000400 -#define UART_RIS_OERIS_BITN 10 -#define UART_RIS_OERIS_M 0x00000400 -#define UART_RIS_OERIS_S 10 +#define UART_RIS_OERIS 0x00000400 +#define UART_RIS_OERIS_BITN 10 +#define UART_RIS_OERIS_M 0x00000400 +#define UART_RIS_OERIS_S 10 // Field: [9] BERIS // @@ -760,10 +760,10 @@ // Break error is set when a break condition is detected, indicating that the // received data input (UARTRXD input pin) was held LOW for longer than a // full-word transmission time (defined as start, data, parity and stop bits). -#define UART_RIS_BERIS 0x00000200 -#define UART_RIS_BERIS_BITN 9 -#define UART_RIS_BERIS_M 0x00000200 -#define UART_RIS_BERIS_S 9 +#define UART_RIS_BERIS 0x00000200 +#define UART_RIS_BERIS_BITN 9 +#define UART_RIS_BERIS_M 0x00000200 +#define UART_RIS_BERIS_S 9 // Field: [8] PERIS // @@ -771,10 +771,10 @@ // This field returns the raw interrupt state of UART's parity error interrupt. // Parity error is set if the parity of the received data character does not // match the parity that the LCRH.EPS and LCRH.SPS select. -#define UART_RIS_PERIS 0x00000100 -#define UART_RIS_PERIS_BITN 8 -#define UART_RIS_PERIS_M 0x00000100 -#define UART_RIS_PERIS_S 8 +#define UART_RIS_PERIS 0x00000100 +#define UART_RIS_PERIS_BITN 8 +#define UART_RIS_PERIS_M 0x00000100 +#define UART_RIS_PERIS_S 8 // Field: [7] FERIS // @@ -782,10 +782,10 @@ // This field returns the raw interrupt state of UART's framing error // interrupt. Framing error is set if the received character does not have a // valid stop bit (a valid stop bit is 1). -#define UART_RIS_FERIS 0x00000080 -#define UART_RIS_FERIS_BITN 7 -#define UART_RIS_FERIS_M 0x00000080 -#define UART_RIS_FERIS_S 7 +#define UART_RIS_FERIS 0x00000080 +#define UART_RIS_FERIS_BITN 7 +#define UART_RIS_FERIS_M 0x00000080 +#define UART_RIS_FERIS_S 7 // Field: [6] RTRIS // @@ -798,10 +798,10 @@ // The raw interrupt for receive timeout cannot be set unless the mask is set // (IMSC.RTIM = 1). This is because the mask acts as an enable for power // saving. That is, the same status can be read from MIS.RTMIS and RTRIS. -#define UART_RIS_RTRIS 0x00000040 -#define UART_RIS_RTRIS_BITN 6 -#define UART_RIS_RTRIS_M 0x00000040 -#define UART_RIS_RTRIS_S 6 +#define UART_RIS_RTRIS 0x00000040 +#define UART_RIS_RTRIS_BITN 6 +#define UART_RIS_RTRIS_M 0x00000040 +#define UART_RIS_RTRIS_S 6 // Field: [5] TXRIS // @@ -816,10 +816,10 @@ // location, the transmit interrupt is asserted if there is no data present in // the transmitters single location. It is cleared by performing a single write // to the transmit FIFO, or by clearing the interrupt through ICR.TXIC. -#define UART_RIS_TXRIS 0x00000020 -#define UART_RIS_TXRIS_BITN 5 -#define UART_RIS_TXRIS_M 0x00000020 -#define UART_RIS_TXRIS_S 5 +#define UART_RIS_TXRIS 0x00000020 +#define UART_RIS_TXRIS_BITN 5 +#define UART_RIS_TXRIS_M 0x00000020 +#define UART_RIS_TXRIS_S 5 // Field: [4] RXRIS // @@ -835,20 +835,20 @@ // thereby filling the location. The receive interrupt is cleared by performing // a single read of the receive FIFO, or by clearing the interrupt through // ICR.RXIC. -#define UART_RIS_RXRIS 0x00000010 -#define UART_RIS_RXRIS_BITN 4 -#define UART_RIS_RXRIS_M 0x00000010 -#define UART_RIS_RXRIS_S 4 +#define UART_RIS_RXRIS 0x00000010 +#define UART_RIS_RXRIS_BITN 4 +#define UART_RIS_RXRIS_M 0x00000010 +#define UART_RIS_RXRIS_S 4 // Field: [1] CTSRMIS // // Clear to Send (CTS) modem interrupt status: // This field returns the raw interrupt state of UART's clear to send // interrupt. -#define UART_RIS_CTSRMIS 0x00000002 -#define UART_RIS_CTSRMIS_BITN 1 -#define UART_RIS_CTSRMIS_M 0x00000002 -#define UART_RIS_CTSRMIS_S 1 +#define UART_RIS_CTSRMIS 0x00000002 +#define UART_RIS_CTSRMIS_BITN 1 +#define UART_RIS_CTSRMIS_M 0x00000002 +#define UART_RIS_CTSRMIS_S 1 //***************************************************************************** // @@ -861,10 +861,10 @@ // This field returns the masked interrupt state of the overrun interrupt which // is the AND product of raw interrupt state RIS.EOTRIS and the mask setting // IMSC.EOTIM. -#define UART_MIS_EOTMIS 0x00000800 -#define UART_MIS_EOTMIS_BITN 11 -#define UART_MIS_EOTMIS_M 0x00000800 -#define UART_MIS_EOTMIS_S 11 +#define UART_MIS_EOTMIS 0x00000800 +#define UART_MIS_EOTMIS_BITN 11 +#define UART_MIS_EOTMIS_M 0x00000800 +#define UART_MIS_EOTMIS_S 11 // Field: [10] OEMIS // @@ -872,10 +872,10 @@ // This field returns the masked interrupt state of the overrun interrupt which // is the AND product of raw interrupt state RIS.OERIS and the mask setting // IMSC.OEIM. -#define UART_MIS_OEMIS 0x00000400 -#define UART_MIS_OEMIS_BITN 10 -#define UART_MIS_OEMIS_M 0x00000400 -#define UART_MIS_OEMIS_S 10 +#define UART_MIS_OEMIS 0x00000400 +#define UART_MIS_OEMIS_BITN 10 +#define UART_MIS_OEMIS_M 0x00000400 +#define UART_MIS_OEMIS_S 10 // Field: [9] BEMIS // @@ -883,10 +883,10 @@ // This field returns the masked interrupt state of the break error interrupt // which is the AND product of raw interrupt state RIS.BERIS and the mask // setting IMSC.BEIM. -#define UART_MIS_BEMIS 0x00000200 -#define UART_MIS_BEMIS_BITN 9 -#define UART_MIS_BEMIS_M 0x00000200 -#define UART_MIS_BEMIS_S 9 +#define UART_MIS_BEMIS 0x00000200 +#define UART_MIS_BEMIS_BITN 9 +#define UART_MIS_BEMIS_M 0x00000200 +#define UART_MIS_BEMIS_S 9 // Field: [8] PEMIS // @@ -894,20 +894,20 @@ // This field returns the masked interrupt state of the parity error interrupt // which is the AND product of raw interrupt state RIS.PERIS and the mask // setting IMSC.PEIM. -#define UART_MIS_PEMIS 0x00000100 -#define UART_MIS_PEMIS_BITN 8 -#define UART_MIS_PEMIS_M 0x00000100 -#define UART_MIS_PEMIS_S 8 +#define UART_MIS_PEMIS 0x00000100 +#define UART_MIS_PEMIS_BITN 8 +#define UART_MIS_PEMIS_M 0x00000100 +#define UART_MIS_PEMIS_S 8 // Field: [7] FEMIS // // Framing error masked interrupt status: Returns the masked interrupt state of // the framing error interrupt which is the AND product of raw interrupt state // RIS.FERIS and the mask setting IMSC.FEIM. -#define UART_MIS_FEMIS 0x00000080 -#define UART_MIS_FEMIS_BITN 7 -#define UART_MIS_FEMIS_M 0x00000080 -#define UART_MIS_FEMIS_S 7 +#define UART_MIS_FEMIS 0x00000080 +#define UART_MIS_FEMIS_BITN 7 +#define UART_MIS_FEMIS_M 0x00000080 +#define UART_MIS_FEMIS_S 7 // Field: [6] RTMIS // @@ -916,10 +916,10 @@ // The raw interrupt for receive timeout cannot be set unless the mask is set // (IMSC.RTIM = 1). This is because the mask acts as an enable for power // saving. That is, the same status can be read from RTMIS and RIS.RTRIS. -#define UART_MIS_RTMIS 0x00000040 -#define UART_MIS_RTMIS_BITN 6 -#define UART_MIS_RTMIS_M 0x00000040 -#define UART_MIS_RTMIS_S 6 +#define UART_MIS_RTMIS 0x00000040 +#define UART_MIS_RTMIS_BITN 6 +#define UART_MIS_RTMIS_M 0x00000040 +#define UART_MIS_RTMIS_S 6 // Field: [5] TXMIS // @@ -927,10 +927,10 @@ // This field returns the masked interrupt state of the transmit interrupt // which is the AND product of raw interrupt state RIS.TXRIS and the mask // setting IMSC.TXIM. -#define UART_MIS_TXMIS 0x00000020 -#define UART_MIS_TXMIS_BITN 5 -#define UART_MIS_TXMIS_M 0x00000020 -#define UART_MIS_TXMIS_S 5 +#define UART_MIS_TXMIS 0x00000020 +#define UART_MIS_TXMIS_BITN 5 +#define UART_MIS_TXMIS_M 0x00000020 +#define UART_MIS_TXMIS_S 5 // Field: [4] RXMIS // @@ -938,10 +938,10 @@ // This field returns the masked interrupt state of the receive interrupt // which is the AND product of raw interrupt state RIS.RXRIS and the mask // setting IMSC.RXIM. -#define UART_MIS_RXMIS 0x00000010 -#define UART_MIS_RXMIS_BITN 4 -#define UART_MIS_RXMIS_M 0x00000010 -#define UART_MIS_RXMIS_S 4 +#define UART_MIS_RXMIS 0x00000010 +#define UART_MIS_RXMIS_BITN 4 +#define UART_MIS_RXMIS_M 0x00000010 +#define UART_MIS_RXMIS_S 4 // Field: [1] CTSMMIS // @@ -949,10 +949,10 @@ // This field returns the masked interrupt state of the clear to send interrupt // which is the AND product of raw interrupt state RIS.CTSRMIS and the mask // setting IMSC.CTSMIM. -#define UART_MIS_CTSMMIS 0x00000002 -#define UART_MIS_CTSMMIS_BITN 1 -#define UART_MIS_CTSMMIS_M 0x00000002 -#define UART_MIS_CTSMMIS_S 1 +#define UART_MIS_CTSMMIS 0x00000002 +#define UART_MIS_CTSMMIS_BITN 1 +#define UART_MIS_CTSMMIS_M 0x00000002 +#define UART_MIS_CTSMMIS_S 1 //***************************************************************************** // @@ -964,90 +964,90 @@ // End of Transmission interrupt clear: // Writing 1 to this field clears the overrun error interrupt (RIS.EOTRIS). // Writing 0 has no effect. -#define UART_ICR_EOTIC 0x00000800 -#define UART_ICR_EOTIC_BITN 11 -#define UART_ICR_EOTIC_M 0x00000800 -#define UART_ICR_EOTIC_S 11 +#define UART_ICR_EOTIC 0x00000800 +#define UART_ICR_EOTIC_BITN 11 +#define UART_ICR_EOTIC_M 0x00000800 +#define UART_ICR_EOTIC_S 11 // Field: [10] OEIC // // Overrun error interrupt clear: // Writing 1 to this field clears the overrun error interrupt (RIS.OERIS). // Writing 0 has no effect. -#define UART_ICR_OEIC 0x00000400 -#define UART_ICR_OEIC_BITN 10 -#define UART_ICR_OEIC_M 0x00000400 -#define UART_ICR_OEIC_S 10 +#define UART_ICR_OEIC 0x00000400 +#define UART_ICR_OEIC_BITN 10 +#define UART_ICR_OEIC_M 0x00000400 +#define UART_ICR_OEIC_S 10 // Field: [9] BEIC // // Break error interrupt clear: // Writing 1 to this field clears the break error interrupt (RIS.BERIS). // Writing 0 has no effect. -#define UART_ICR_BEIC 0x00000200 -#define UART_ICR_BEIC_BITN 9 -#define UART_ICR_BEIC_M 0x00000200 -#define UART_ICR_BEIC_S 9 +#define UART_ICR_BEIC 0x00000200 +#define UART_ICR_BEIC_BITN 9 +#define UART_ICR_BEIC_M 0x00000200 +#define UART_ICR_BEIC_S 9 // Field: [8] PEIC // // Parity error interrupt clear: // Writing 1 to this field clears the parity error interrupt (RIS.PERIS). // Writing 0 has no effect. -#define UART_ICR_PEIC 0x00000100 -#define UART_ICR_PEIC_BITN 8 -#define UART_ICR_PEIC_M 0x00000100 -#define UART_ICR_PEIC_S 8 +#define UART_ICR_PEIC 0x00000100 +#define UART_ICR_PEIC_BITN 8 +#define UART_ICR_PEIC_M 0x00000100 +#define UART_ICR_PEIC_S 8 // Field: [7] FEIC // // Framing error interrupt clear: // Writing 1 to this field clears the framing error interrupt (RIS.FERIS). // Writing 0 has no effect. -#define UART_ICR_FEIC 0x00000080 -#define UART_ICR_FEIC_BITN 7 -#define UART_ICR_FEIC_M 0x00000080 -#define UART_ICR_FEIC_S 7 +#define UART_ICR_FEIC 0x00000080 +#define UART_ICR_FEIC_BITN 7 +#define UART_ICR_FEIC_M 0x00000080 +#define UART_ICR_FEIC_S 7 // Field: [6] RTIC // // Receive timeout interrupt clear: // Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS). // Writing 0 has no effect. -#define UART_ICR_RTIC 0x00000040 -#define UART_ICR_RTIC_BITN 6 -#define UART_ICR_RTIC_M 0x00000040 -#define UART_ICR_RTIC_S 6 +#define UART_ICR_RTIC 0x00000040 +#define UART_ICR_RTIC_BITN 6 +#define UART_ICR_RTIC_M 0x00000040 +#define UART_ICR_RTIC_S 6 // Field: [5] TXIC // // Transmit interrupt clear: // Writing 1 to this field clears the transmit interrupt (RIS.TXRIS). Writing 0 // has no effect. -#define UART_ICR_TXIC 0x00000020 -#define UART_ICR_TXIC_BITN 5 -#define UART_ICR_TXIC_M 0x00000020 -#define UART_ICR_TXIC_S 5 +#define UART_ICR_TXIC 0x00000020 +#define UART_ICR_TXIC_BITN 5 +#define UART_ICR_TXIC_M 0x00000020 +#define UART_ICR_TXIC_S 5 // Field: [4] RXIC // // Receive interrupt clear: // Writing 1 to this field clears the receive interrupt (RIS.RXRIS). Writing 0 // has no effect. -#define UART_ICR_RXIC 0x00000010 -#define UART_ICR_RXIC_BITN 4 -#define UART_ICR_RXIC_M 0x00000010 -#define UART_ICR_RXIC_S 4 +#define UART_ICR_RXIC 0x00000010 +#define UART_ICR_RXIC_BITN 4 +#define UART_ICR_RXIC_M 0x00000010 +#define UART_ICR_RXIC_S 4 // Field: [1] CTSMIC // // Clear to Send (CTS) modem interrupt clear: // Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS). // Writing 0 has no effect. -#define UART_ICR_CTSMIC 0x00000002 -#define UART_ICR_CTSMIC_BITN 1 -#define UART_ICR_CTSMIC_M 0x00000002 -#define UART_ICR_CTSMIC_S 1 +#define UART_ICR_CTSMIC 0x00000002 +#define UART_ICR_CTSMIC_BITN 1 +#define UART_ICR_CTSMIC_M 0x00000002 +#define UART_ICR_CTSMIC_S 1 //***************************************************************************** // @@ -1060,28 +1060,27 @@ // single and burst requests) are disabled when the UART error interrupt is // asserted (more specifically if any of the error interrupts RIS.PERIS, // RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted). -#define UART_DMACTL_DMAONERR 0x00000004 -#define UART_DMACTL_DMAONERR_BITN 2 -#define UART_DMACTL_DMAONERR_M 0x00000004 -#define UART_DMACTL_DMAONERR_S 2 +#define UART_DMACTL_DMAONERR 0x00000004 +#define UART_DMACTL_DMAONERR_BITN 2 +#define UART_DMACTL_DMAONERR_M 0x00000004 +#define UART_DMACTL_DMAONERR_S 2 // Field: [1] TXDMAE // // Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is // enabled. -#define UART_DMACTL_TXDMAE 0x00000002 -#define UART_DMACTL_TXDMAE_BITN 1 -#define UART_DMACTL_TXDMAE_M 0x00000002 -#define UART_DMACTL_TXDMAE_S 1 +#define UART_DMACTL_TXDMAE 0x00000002 +#define UART_DMACTL_TXDMAE_BITN 1 +#define UART_DMACTL_TXDMAE_M 0x00000002 +#define UART_DMACTL_TXDMAE_S 1 // Field: [0] RXDMAE // // Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is // enabled. -#define UART_DMACTL_RXDMAE 0x00000001 -#define UART_DMACTL_RXDMAE_BITN 0 -#define UART_DMACTL_RXDMAE_M 0x00000001 -#define UART_DMACTL_RXDMAE_S 0 - +#define UART_DMACTL_RXDMAE 0x00000001 +#define UART_DMACTL_RXDMAE_BITN 0 +#define UART_DMACTL_RXDMAE_M 0x00000001 +#define UART_DMACTL_RXDMAE_S 0 #endif // __UART__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_udma.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_udma.h index 566192b..75ae138 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_udma.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_udma.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_udma_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_udma_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_UDMA_H__ #define __HW_UDMA_H__ @@ -44,61 +44,61 @@ // //***************************************************************************** // Status -#define UDMA_O_STATUS 0x00000000 +#define UDMA_O_STATUS 0x00000000 // Configuration -#define UDMA_O_CFG 0x00000004 +#define UDMA_O_CFG 0x00000004 // Channel Control Data Base Pointer -#define UDMA_O_CTRL 0x00000008 +#define UDMA_O_CTRL 0x00000008 // Channel Alternate Control Data Base Pointer -#define UDMA_O_ALTCTRL 0x0000000C +#define UDMA_O_ALTCTRL 0x0000000C // Channel Wait On Request Status -#define UDMA_O_WAITONREQ 0x00000010 +#define UDMA_O_WAITONREQ 0x00000010 // Channel Software Request -#define UDMA_O_SOFTREQ 0x00000014 +#define UDMA_O_SOFTREQ 0x00000014 // Channel Set UseBurst -#define UDMA_O_SETBURST 0x00000018 +#define UDMA_O_SETBURST 0x00000018 // Channel Clear UseBurst -#define UDMA_O_CLEARBURST 0x0000001C +#define UDMA_O_CLEARBURST 0x0000001C // Channel Set Request Mask -#define UDMA_O_SETREQMASK 0x00000020 +#define UDMA_O_SETREQMASK 0x00000020 // Clear Channel Request Mask -#define UDMA_O_CLEARREQMASK 0x00000024 +#define UDMA_O_CLEARREQMASK 0x00000024 // Set Channel Enable -#define UDMA_O_SETCHANNELEN 0x00000028 +#define UDMA_O_SETCHANNELEN 0x00000028 // Clear Channel Enable -#define UDMA_O_CLEARCHANNELEN 0x0000002C +#define UDMA_O_CLEARCHANNELEN 0x0000002C // Channel Set Primary-Alternate -#define UDMA_O_SETCHNLPRIALT 0x00000030 +#define UDMA_O_SETCHNLPRIALT 0x00000030 // Channel Clear Primary-Alternate -#define UDMA_O_CLEARCHNLPRIALT 0x00000034 +#define UDMA_O_CLEARCHNLPRIALT 0x00000034 // Set Channel Priority -#define UDMA_O_SETCHNLPRIORITY 0x00000038 +#define UDMA_O_SETCHNLPRIORITY 0x00000038 // Clear Channel Priority -#define UDMA_O_CLEARCHNLPRIORITY 0x0000003C +#define UDMA_O_CLEARCHNLPRIORITY 0x0000003C // Error Status and Clear -#define UDMA_O_ERROR 0x0000004C +#define UDMA_O_ERROR 0x0000004C // Channel Request Done -#define UDMA_O_REQDONE 0x00000504 +#define UDMA_O_REQDONE 0x00000504 // Channel Request Done Mask -#define UDMA_O_DONEMASK 0x00000520 +#define UDMA_O_DONEMASK 0x00000520 //***************************************************************************** // @@ -113,9 +113,9 @@ // 0x2: Undefined // ... // 0xF: Undefined -#define UDMA_STATUS_TEST_W 4 -#define UDMA_STATUS_TEST_M 0xF0000000 -#define UDMA_STATUS_TEST_S 28 +#define UDMA_STATUS_TEST_W 4 +#define UDMA_STATUS_TEST_M 0xF0000000 +#define UDMA_STATUS_TEST_S 28 // Field: [20:16] TOTALCHANNELS // @@ -127,9 +127,9 @@ // ... // 0x1F: Shows that the controller is configured to use 32 uDMA channels // (32-1=31=0x1F) -#define UDMA_STATUS_TOTALCHANNELS_W 5 -#define UDMA_STATUS_TOTALCHANNELS_M 0x001F0000 -#define UDMA_STATUS_TOTALCHANNELS_S 16 +#define UDMA_STATUS_TOTALCHANNELS_W 5 +#define UDMA_STATUS_TOTALCHANNELS_M 0x001F0000 +#define UDMA_STATUS_TOTALCHANNELS_S 16 // Field: [7:4] STATE // @@ -150,9 +150,9 @@ // 0xB: Undefined // ... // 0xF: Undefined. -#define UDMA_STATUS_STATE_W 4 -#define UDMA_STATUS_STATE_M 0x000000F0 -#define UDMA_STATUS_STATE_S 4 +#define UDMA_STATUS_STATE_W 4 +#define UDMA_STATUS_STATE_M 0x000000F0 +#define UDMA_STATUS_STATE_S 4 // Field: [0] MASTERENABLE // @@ -160,10 +160,10 @@ // // 0: Controller is disabled // 1: Controller is enabled -#define UDMA_STATUS_MASTERENABLE 0x00000001 -#define UDMA_STATUS_MASTERENABLE_BITN 0 -#define UDMA_STATUS_MASTERENABLE_M 0x00000001 -#define UDMA_STATUS_MASTERENABLE_S 0 +#define UDMA_STATUS_MASTERENABLE 0x00000001 +#define UDMA_STATUS_MASTERENABLE_BITN 0 +#define UDMA_STATUS_MASTERENABLE_M 0x00000001 +#define UDMA_STATUS_MASTERENABLE_S 0 //***************************************************************************** // @@ -188,9 +188,9 @@ // - the write to the address indicated by destination address pointer // HProt[3:1] for these two exceptions can be controlled by dedicated fields in // the channel configutation descriptor. -#define UDMA_CFG_PRTOCTRL_W 3 -#define UDMA_CFG_PRTOCTRL_M 0x000000E0 -#define UDMA_CFG_PRTOCTRL_S 5 +#define UDMA_CFG_PRTOCTRL_W 3 +#define UDMA_CFG_PRTOCTRL_M 0x000000E0 +#define UDMA_CFG_PRTOCTRL_S 5 // Field: [0] MASTERENABLE // @@ -198,10 +198,10 @@ // // 0: Disables the controller // 1: Enables the controller -#define UDMA_CFG_MASTERENABLE 0x00000001 -#define UDMA_CFG_MASTERENABLE_BITN 0 -#define UDMA_CFG_MASTERENABLE_M 0x00000001 -#define UDMA_CFG_MASTERENABLE_S 0 +#define UDMA_CFG_MASTERENABLE 0x00000001 +#define UDMA_CFG_MASTERENABLE_BITN 0 +#define UDMA_CFG_MASTERENABLE_M 0x00000001 +#define UDMA_CFG_MASTERENABLE_S 0 //***************************************************************************** // @@ -213,9 +213,9 @@ // This register point to the base address for the primary data structures of // each DMA channel. This is not stored in module, but in system memory, thus // space must be allocated for this usage when DMA is in usage -#define UDMA_CTRL_BASEPTR_W 22 -#define UDMA_CTRL_BASEPTR_M 0xFFFFFC00 -#define UDMA_CTRL_BASEPTR_S 10 +#define UDMA_CTRL_BASEPTR_W 22 +#define UDMA_CTRL_BASEPTR_M 0xFFFFFC00 +#define UDMA_CTRL_BASEPTR_S 10 //***************************************************************************** // @@ -226,9 +226,9 @@ // // This register shows the base address for the alternate data structures and // is calculated by module, thus read only -#define UDMA_ALTCTRL_BASEPTR_W 32 -#define UDMA_ALTCTRL_BASEPTR_M 0xFFFFFFFF -#define UDMA_ALTCTRL_BASEPTR_S 0 +#define UDMA_ALTCTRL_BASEPTR_W 32 +#define UDMA_ALTCTRL_BASEPTR_M 0xFFFFFFFF +#define UDMA_ALTCTRL_BASEPTR_S 0 //***************************************************************************** // @@ -245,9 +245,9 @@ // keeps channel Ch in active state until the requests are deasserted. This // handshake is necessary for channels where the requester is in an // asynchronous domain or can run at slower clock speed than uDMA -#define UDMA_WAITONREQ_CHNLSTATUS_W 32 -#define UDMA_WAITONREQ_CHNLSTATUS_M 0xFFFFFFFF -#define UDMA_WAITONREQ_CHNLSTATUS_S 0 +#define UDMA_WAITONREQ_CHNLSTATUS_W 32 +#define UDMA_WAITONREQ_CHNLSTATUS_M 0xFFFFFFFF +#define UDMA_WAITONREQ_CHNLSTATUS_S 0 //***************************************************************************** // @@ -264,9 +264,9 @@ // // Writing to a bit where a uDMA channel is not implemented does not create a // uDMA request for that channel -#define UDMA_SOFTREQ_CHNLS_W 32 -#define UDMA_SOFTREQ_CHNLS_M 0xFFFFFFFF -#define UDMA_SOFTREQ_CHNLS_S 0 +#define UDMA_SOFTREQ_CHNLS_W 32 +#define UDMA_SOFTREQ_CHNLS_M 0xFFFFFFFF +#define UDMA_SOFTREQ_CHNLS_S 0 //***************************************************************************** // @@ -294,9 +294,9 @@ // controller performs 2^R transfers for burst requests. // // Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_SETBURST_CHNLS_W 32 -#define UDMA_SETBURST_CHNLS_M 0xFFFFFFFF -#define UDMA_SETBURST_CHNLS_S 0 +#define UDMA_SETBURST_CHNLS_W 32 +#define UDMA_SETBURST_CHNLS_M 0xFFFFFFFF +#define UDMA_SETBURST_CHNLS_S 0 //***************************************************************************** // @@ -315,9 +315,9 @@ // Bit [Ch] = 1: Enables single transfer requests on channel Ch. // // Writing to a bit where a DMA channel is not implemented has no effect. -#define UDMA_CLEARBURST_CHNLS_W 32 -#define UDMA_CLEARBURST_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARBURST_CHNLS_S 0 +#define UDMA_CLEARBURST_CHNLS_W 32 +#define UDMA_CLEARBURST_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARBURST_CHNLS_S 0 //***************************************************************************** // @@ -339,9 +339,9 @@ // request channel [C] input from generating uDMA requests. // // Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_SETREQMASK_CHNLS_W 32 -#define UDMA_SETREQMASK_CHNLS_M 0xFFFFFFFF -#define UDMA_SETREQMASK_CHNLS_S 0 +#define UDMA_SETREQMASK_CHNLS_W 32 +#define UDMA_SETREQMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_SETREQMASK_CHNLS_S 0 //***************************************************************************** // @@ -358,9 +358,9 @@ // Bit [Ch] = 1: Enables channel [C] to generate DMA requests. // // Writing to a bit where a DMA channel is not implemented has no effect. -#define UDMA_CLEARREQMASK_CHNLS_W 32 -#define UDMA_CLEARREQMASK_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARREQMASK_CHNLS_S 0 +#define UDMA_CLEARREQMASK_CHNLS_W 32 +#define UDMA_CLEARREQMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARREQMASK_CHNLS_S 0 //***************************************************************************** // @@ -381,9 +381,9 @@ // Bit [Ch] = 1: Enables channel Ch // // Writing to a bit where a DMA channel is not implemented has no effect -#define UDMA_SETCHANNELEN_CHNLS_W 32 -#define UDMA_SETCHANNELEN_CHNLS_M 0xFFFFFFFF -#define UDMA_SETCHANNELEN_CHNLS_S 0 +#define UDMA_SETCHANNELEN_CHNLS_W 32 +#define UDMA_SETCHANNELEN_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHANNELEN_CHNLS_S 0 //***************************************************************************** // @@ -399,9 +399,9 @@ // Bit [Ch] = 1: Disables channel Ch // // Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_CLEARCHANNELEN_CHNLS_W 32 -#define UDMA_CLEARCHANNELEN_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARCHANNELEN_CHNLS_S 0 +#define UDMA_CLEARCHANNELEN_CHNLS_W 32 +#define UDMA_CLEARCHANNELEN_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHANNELEN_CHNLS_S 0 //***************************************************************************** // @@ -422,9 +422,9 @@ // Bit [Ch] = 1: Selects the alternate data structure for channel Ch // // Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_SETCHNLPRIALT_CHNLS_W 32 -#define UDMA_SETCHNLPRIALT_CHNLS_M 0xFFFFFFFF -#define UDMA_SETCHNLPRIALT_CHNLS_S 0 +#define UDMA_SETCHNLPRIALT_CHNLS_W 32 +#define UDMA_SETCHNLPRIALT_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHNLPRIALT_CHNLS_S 0 //***************************************************************************** // @@ -442,9 +442,9 @@ // Bit [Ch] = 1: Selects the primary data structure for channel Ch. // // Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_CLEARCHNLPRIALT_CHNLS_W 32 -#define UDMA_CLEARCHNLPRIALT_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARCHNLPRIALT_CHNLS_S 0 +#define UDMA_CLEARCHNLPRIALT_CHNLS_W 32 +#define UDMA_CLEARCHNLPRIALT_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHNLPRIALT_CHNLS_S 0 //***************************************************************************** // @@ -466,9 +466,9 @@ // Bit [Ch] = 1: Channel Ch uses the high priority level. // // Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_SETCHNLPRIORITY_CHNLS_W 32 -#define UDMA_SETCHNLPRIORITY_CHNLS_M 0xFFFFFFFF -#define UDMA_SETCHNLPRIORITY_CHNLS_S 0 +#define UDMA_SETCHNLPRIORITY_CHNLS_W 32 +#define UDMA_SETCHNLPRIORITY_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHNLPRIORITY_CHNLS_S 0 //***************************************************************************** // @@ -486,9 +486,9 @@ // Bit [Ch] = 1: Channel Ch uses the default priority level. // // Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_CLEARCHNLPRIORITY_CHNLS_W 32 -#define UDMA_CLEARCHNLPRIORITY_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARCHNLPRIORITY_CHNLS_S 0 +#define UDMA_CLEARCHNLPRIORITY_CHNLS_W 32 +#define UDMA_CLEARCHNLPRIORITY_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHNLPRIORITY_CHNLS_S 0 //***************************************************************************** // @@ -508,10 +508,10 @@ // // 0: No effect, status of bus error flag is unchanged. // 1: Clears the bus error flag. -#define UDMA_ERROR_STATUS 0x00000001 -#define UDMA_ERROR_STATUS_BITN 0 -#define UDMA_ERROR_STATUS_M 0x00000001 -#define UDMA_ERROR_STATUS_S 0 +#define UDMA_ERROR_STATUS 0x00000001 +#define UDMA_ERROR_STATUS_BITN 0 +#define UDMA_ERROR_STATUS_M 0x00000001 +#define UDMA_ERROR_STATUS_S 0 //***************************************************************************** // @@ -532,9 +532,9 @@ // Write as: // Bit [Ch] = 0: No effect. // Bit [Ch] = 1: The corresponding [Ch] bit is cleared and is set to 0 -#define UDMA_REQDONE_CHNLS_W 32 -#define UDMA_REQDONE_CHNLS_M 0xFFFFFFFF -#define UDMA_REQDONE_CHNLS_S 0 +#define UDMA_REQDONE_CHNLS_W 32 +#define UDMA_REQDONE_CHNLS_M 0xFFFFFFFF +#define UDMA_REQDONE_CHNLS_S 0 //***************************************************************************** // @@ -567,9 +567,8 @@ // peripherals. // Note that this enables uDMA done for channel [Ch] to contribute to // generation of combined uDMA done signal. -#define UDMA_DONEMASK_CHNLS_W 32 -#define UDMA_DONEMASK_CHNLS_M 0xFFFFFFFF -#define UDMA_DONEMASK_CHNLS_S 0 - +#define UDMA_DONEMASK_CHNLS_W 32 +#define UDMA_DONEMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_DONEMASK_CHNLS_S 0 #endif // __UDMA__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_vims.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_vims.h index c668670..19baf85 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_vims.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_vims.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_vims_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_vims_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_VIMS_H__ #define __HW_VIMS_H__ @@ -44,10 +44,10 @@ // //***************************************************************************** // Status -#define VIMS_O_STAT 0x00000000 +#define VIMS_O_STAT 0x00000000 // Control -#define VIMS_O_CTL 0x00000004 +#define VIMS_O_CTL 0x00000004 //***************************************************************************** // @@ -60,10 +60,10 @@ // // 0: Enabled or in transition to disabled // 1: Disabled and flushed -#define VIMS_STAT_IDCODE_LB_DIS 0x00000020 -#define VIMS_STAT_IDCODE_LB_DIS_BITN 5 -#define VIMS_STAT_IDCODE_LB_DIS_M 0x00000020 -#define VIMS_STAT_IDCODE_LB_DIS_S 5 +#define VIMS_STAT_IDCODE_LB_DIS 0x00000020 +#define VIMS_STAT_IDCODE_LB_DIS_BITN 5 +#define VIMS_STAT_IDCODE_LB_DIS_M 0x00000020 +#define VIMS_STAT_IDCODE_LB_DIS_S 5 // Field: [4] SYSBUS_LB_DIS // @@ -71,10 +71,10 @@ // // 0: Enabled or in transition to disabled // 1: Disabled and flushed -#define VIMS_STAT_SYSBUS_LB_DIS 0x00000010 -#define VIMS_STAT_SYSBUS_LB_DIS_BITN 4 -#define VIMS_STAT_SYSBUS_LB_DIS_M 0x00000010 -#define VIMS_STAT_SYSBUS_LB_DIS_S 4 +#define VIMS_STAT_SYSBUS_LB_DIS 0x00000010 +#define VIMS_STAT_SYSBUS_LB_DIS_BITN 4 +#define VIMS_STAT_SYSBUS_LB_DIS_M 0x00000010 +#define VIMS_STAT_SYSBUS_LB_DIS_S 4 // Field: [3] MODE_CHANGING // @@ -82,18 +82,18 @@ // // 0: VIMS is in the mode defined by MODE // 1: VIMS is in the process of changing to the mode given in CTL.MODE -#define VIMS_STAT_MODE_CHANGING 0x00000008 -#define VIMS_STAT_MODE_CHANGING_BITN 3 -#define VIMS_STAT_MODE_CHANGING_M 0x00000008 -#define VIMS_STAT_MODE_CHANGING_S 3 +#define VIMS_STAT_MODE_CHANGING 0x00000008 +#define VIMS_STAT_MODE_CHANGING_BITN 3 +#define VIMS_STAT_MODE_CHANGING_M 0x00000008 +#define VIMS_STAT_MODE_CHANGING_S 3 // Field: [2] INV // // This bit is set when invalidation of the cache memory is active / ongoing -#define VIMS_STAT_INV 0x00000004 -#define VIMS_STAT_INV_BITN 2 -#define VIMS_STAT_INV_M 0x00000004 -#define VIMS_STAT_INV_S 2 +#define VIMS_STAT_INV 0x00000004 +#define VIMS_STAT_INV_BITN 2 +#define VIMS_STAT_INV_M 0x00000004 +#define VIMS_STAT_INV_S 2 // Field: [1:0] MODE // @@ -102,12 +102,12 @@ // OFF VIMS Off mode // CACHE VIMS Cache mode // GPRAM VIMS GPRAM mode -#define VIMS_STAT_MODE_W 2 -#define VIMS_STAT_MODE_M 0x00000003 -#define VIMS_STAT_MODE_S 0 -#define VIMS_STAT_MODE_OFF 0x00000003 -#define VIMS_STAT_MODE_CACHE 0x00000001 -#define VIMS_STAT_MODE_GPRAM 0x00000000 +#define VIMS_STAT_MODE_W 2 +#define VIMS_STAT_MODE_M 0x00000003 +#define VIMS_STAT_MODE_S 0 +#define VIMS_STAT_MODE_OFF 0x00000003 +#define VIMS_STAT_MODE_CACHE 0x00000001 +#define VIMS_STAT_MODE_GPRAM 0x00000000 //***************************************************************************** // @@ -117,28 +117,28 @@ // Field: [31] STATS_CLR // // Set this bit to clear statistic counters. -#define VIMS_CTL_STATS_CLR 0x80000000 -#define VIMS_CTL_STATS_CLR_BITN 31 -#define VIMS_CTL_STATS_CLR_M 0x80000000 -#define VIMS_CTL_STATS_CLR_S 31 +#define VIMS_CTL_STATS_CLR 0x80000000 +#define VIMS_CTL_STATS_CLR_BITN 31 +#define VIMS_CTL_STATS_CLR_M 0x80000000 +#define VIMS_CTL_STATS_CLR_S 31 // Field: [30] STATS_EN // // Set this bit to enable statistic counters. -#define VIMS_CTL_STATS_EN 0x40000000 -#define VIMS_CTL_STATS_EN_BITN 30 -#define VIMS_CTL_STATS_EN_M 0x40000000 -#define VIMS_CTL_STATS_EN_S 30 +#define VIMS_CTL_STATS_EN 0x40000000 +#define VIMS_CTL_STATS_EN_BITN 30 +#define VIMS_CTL_STATS_EN_M 0x40000000 +#define VIMS_CTL_STATS_EN_S 30 // Field: [29] DYN_CG_EN // // 0: The in-built clock gate functionality is bypassed. // 1: The in-built clock gate functionality is enabled, automatically gating // the clock when not needed. -#define VIMS_CTL_DYN_CG_EN 0x20000000 -#define VIMS_CTL_DYN_CG_EN_BITN 29 -#define VIMS_CTL_DYN_CG_EN_M 0x20000000 -#define VIMS_CTL_DYN_CG_EN_S 29 +#define VIMS_CTL_DYN_CG_EN 0x20000000 +#define VIMS_CTL_DYN_CG_EN_BITN 29 +#define VIMS_CTL_DYN_CG_EN_M 0x20000000 +#define VIMS_CTL_DYN_CG_EN_S 29 // Field: [5] IDCODE_LB_DIS // @@ -146,10 +146,10 @@ // // 0: Enable // 1: Disable -#define VIMS_CTL_IDCODE_LB_DIS 0x00000020 -#define VIMS_CTL_IDCODE_LB_DIS_BITN 5 -#define VIMS_CTL_IDCODE_LB_DIS_M 0x00000020 -#define VIMS_CTL_IDCODE_LB_DIS_S 5 +#define VIMS_CTL_IDCODE_LB_DIS 0x00000020 +#define VIMS_CTL_IDCODE_LB_DIS_BITN 5 +#define VIMS_CTL_IDCODE_LB_DIS_M 0x00000020 +#define VIMS_CTL_IDCODE_LB_DIS_S 5 // Field: [4] SYSBUS_LB_DIS // @@ -157,10 +157,10 @@ // // 0: Enable // 1: Disable -#define VIMS_CTL_SYSBUS_LB_DIS 0x00000010 -#define VIMS_CTL_SYSBUS_LB_DIS_BITN 4 -#define VIMS_CTL_SYSBUS_LB_DIS_M 0x00000010 -#define VIMS_CTL_SYSBUS_LB_DIS_S 4 +#define VIMS_CTL_SYSBUS_LB_DIS 0x00000010 +#define VIMS_CTL_SYSBUS_LB_DIS_BITN 4 +#define VIMS_CTL_SYSBUS_LB_DIS_M 0x00000010 +#define VIMS_CTL_SYSBUS_LB_DIS_S 4 // Field: [3] ARB_CFG // @@ -168,10 +168,10 @@ // // 0: Static arbitration (icode/docde > sysbus) // 1: Round-robin arbitration -#define VIMS_CTL_ARB_CFG 0x00000008 -#define VIMS_CTL_ARB_CFG_BITN 3 -#define VIMS_CTL_ARB_CFG_M 0x00000008 -#define VIMS_CTL_ARB_CFG_S 3 +#define VIMS_CTL_ARB_CFG 0x00000008 +#define VIMS_CTL_ARB_CFG_BITN 3 +#define VIMS_CTL_ARB_CFG_M 0x00000008 +#define VIMS_CTL_ARB_CFG_S 3 // Field: [2] PREF_EN // @@ -179,10 +179,10 @@ // // 0: Disabled // 1: Enabled -#define VIMS_CTL_PREF_EN 0x00000004 -#define VIMS_CTL_PREF_EN_BITN 2 -#define VIMS_CTL_PREF_EN_M 0x00000004 -#define VIMS_CTL_PREF_EN_S 2 +#define VIMS_CTL_PREF_EN 0x00000004 +#define VIMS_CTL_PREF_EN_BITN 2 +#define VIMS_CTL_PREF_EN_M 0x00000004 +#define VIMS_CTL_PREF_EN_S 2 // Field: [1:0] MODE // @@ -193,12 +193,11 @@ // OFF VIMS Off mode // CACHE VIMS Cache mode // GPRAM VIMS GPRAM mode -#define VIMS_CTL_MODE_W 2 -#define VIMS_CTL_MODE_M 0x00000003 -#define VIMS_CTL_MODE_S 0 -#define VIMS_CTL_MODE_OFF 0x00000003 -#define VIMS_CTL_MODE_CACHE 0x00000001 -#define VIMS_CTL_MODE_GPRAM 0x00000000 - +#define VIMS_CTL_MODE_W 2 +#define VIMS_CTL_MODE_M 0x00000003 +#define VIMS_CTL_MODE_S 0 +#define VIMS_CTL_MODE_OFF 0x00000003 +#define VIMS_CTL_MODE_CACHE 0x00000001 +#define VIMS_CTL_MODE_GPRAM 0x00000000 #endif // __VIMS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_wdt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_wdt.h index 5c1155c..60e6add 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_wdt.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/inc/hw_wdt.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_wdt_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_wdt_h + * Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) + * Revision: 51990 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_WDT_H__ #define __HW_WDT_H__ @@ -44,31 +44,31 @@ // //***************************************************************************** // Configuration -#define WDT_O_LOAD 0x00000000 +#define WDT_O_LOAD 0x00000000 // Current Count Value -#define WDT_O_VALUE 0x00000004 +#define WDT_O_VALUE 0x00000004 // Control -#define WDT_O_CTL 0x00000008 +#define WDT_O_CTL 0x00000008 // Interrupt Clear -#define WDT_O_ICR 0x0000000C +#define WDT_O_ICR 0x0000000C // Raw Interrupt Status -#define WDT_O_RIS 0x00000010 +#define WDT_O_RIS 0x00000010 // Masked Interrupt Status -#define WDT_O_MIS 0x00000014 +#define WDT_O_MIS 0x00000014 // Test Mode -#define WDT_O_TEST 0x00000418 +#define WDT_O_TEST 0x00000418 // Interrupt Cause Test Mode -#define WDT_O_INT_CAUS 0x0000041C +#define WDT_O_INT_CAUS 0x0000041C // Lock -#define WDT_O_LOCK 0x00000C00 +#define WDT_O_LOCK 0x00000C00 //***************************************************************************** // @@ -81,9 +81,9 @@ // this register is written, the value is immediately loaded and the counter is // restarted to count down from the new value. If this register is loaded with // 0x0000.0000, an interrupt is immediately generated. -#define WDT_LOAD_WDTLOAD_W 32 -#define WDT_LOAD_WDTLOAD_M 0xFFFFFFFF -#define WDT_LOAD_WDTLOAD_S 0 +#define WDT_LOAD_WDTLOAD_W 32 +#define WDT_LOAD_WDTLOAD_M 0xFFFFFFFF +#define WDT_LOAD_WDTLOAD_S 0 //***************************************************************************** // @@ -93,9 +93,9 @@ // Field: [31:0] WDTVALUE // // This register contains the current count value of the timer. -#define WDT_VALUE_WDTVALUE_W 32 -#define WDT_VALUE_WDTVALUE_M 0xFFFFFFFF -#define WDT_VALUE_WDTVALUE_S 0 +#define WDT_VALUE_WDTVALUE_W 32 +#define WDT_VALUE_WDTVALUE_M 0xFFFFFFFF +#define WDT_VALUE_WDTVALUE_S 0 //***************************************************************************** // @@ -111,12 +111,12 @@ // ENUMs: // NONMASKABLE Non-maskable interrupt // MASKABLE Maskable interrupt -#define WDT_CTL_INTTYPE 0x00000004 -#define WDT_CTL_INTTYPE_BITN 2 -#define WDT_CTL_INTTYPE_M 0x00000004 -#define WDT_CTL_INTTYPE_S 2 -#define WDT_CTL_INTTYPE_NONMASKABLE 0x00000004 -#define WDT_CTL_INTTYPE_MASKABLE 0x00000000 +#define WDT_CTL_INTTYPE 0x00000004 +#define WDT_CTL_INTTYPE_BITN 2 +#define WDT_CTL_INTTYPE_M 0x00000004 +#define WDT_CTL_INTTYPE_S 2 +#define WDT_CTL_INTTYPE_NONMASKABLE 0x00000004 +#define WDT_CTL_INTTYPE_MASKABLE 0x00000000 // Field: [1] RESEN // @@ -128,12 +128,12 @@ // ENUMs: // EN Reset output Enabled // DIS Reset output Disabled -#define WDT_CTL_RESEN 0x00000002 -#define WDT_CTL_RESEN_BITN 1 -#define WDT_CTL_RESEN_M 0x00000002 -#define WDT_CTL_RESEN_S 1 -#define WDT_CTL_RESEN_EN 0x00000002 -#define WDT_CTL_RESEN_DIS 0x00000000 +#define WDT_CTL_RESEN 0x00000002 +#define WDT_CTL_RESEN_BITN 1 +#define WDT_CTL_RESEN_M 0x00000002 +#define WDT_CTL_RESEN_S 1 +#define WDT_CTL_RESEN_EN 0x00000002 +#define WDT_CTL_RESEN_DIS 0x00000000 // Field: [0] INTEN // @@ -145,12 +145,12 @@ // ENUMs: // EN Interrupt Enabled // DIS Interrupt Disabled -#define WDT_CTL_INTEN 0x00000001 -#define WDT_CTL_INTEN_BITN 0 -#define WDT_CTL_INTEN_M 0x00000001 -#define WDT_CTL_INTEN_S 0 -#define WDT_CTL_INTEN_EN 0x00000001 -#define WDT_CTL_INTEN_DIS 0x00000000 +#define WDT_CTL_INTEN 0x00000001 +#define WDT_CTL_INTEN_BITN 0 +#define WDT_CTL_INTEN_M 0x00000001 +#define WDT_CTL_INTEN_S 0 +#define WDT_CTL_INTEN_EN 0x00000001 +#define WDT_CTL_INTEN_DIS 0x00000000 //***************************************************************************** // @@ -162,9 +162,9 @@ // This register is the interrupt clear register. A write of any value to this // register clears the WDT interrupt and reloads the 32-bit counter from the // LOAD register. -#define WDT_ICR_WDTICR_W 32 -#define WDT_ICR_WDTICR_M 0xFFFFFFFF -#define WDT_ICR_WDTICR_S 0 +#define WDT_ICR_WDTICR_W 32 +#define WDT_ICR_WDTICR_M 0xFFFFFFFF +#define WDT_ICR_WDTICR_S 0 //***************************************************************************** // @@ -181,10 +181,10 @@ // 0: The WDT has not timed out // 1: A WDT time-out event has occurred // -#define WDT_RIS_WDTRIS 0x00000001 -#define WDT_RIS_WDTRIS_BITN 0 -#define WDT_RIS_WDTRIS_M 0x00000001 -#define WDT_RIS_WDTRIS_S 0 +#define WDT_RIS_WDTRIS 0x00000001 +#define WDT_RIS_WDTRIS_BITN 0 +#define WDT_RIS_WDTRIS_M 0x00000001 +#define WDT_RIS_WDTRIS_S 0 //***************************************************************************** // @@ -201,10 +201,10 @@ // // 0: The WDT has not timed out or is masked. // 1: An unmasked WDT time-out event has occurred. -#define WDT_MIS_WDTMIS 0x00000001 -#define WDT_MIS_WDTMIS_BITN 0 -#define WDT_MIS_WDTMIS_M 0x00000001 -#define WDT_MIS_WDTMIS_S 0 +#define WDT_MIS_WDTMIS 0x00000001 +#define WDT_MIS_WDTMIS_BITN 0 +#define WDT_MIS_WDTMIS_M 0x00000001 +#define WDT_MIS_WDTMIS_S 0 //***************************************************************************** // @@ -221,12 +221,12 @@ // ENUMs: // EN Enable STALL // DIS Disable STALL -#define WDT_TEST_STALL 0x00000100 -#define WDT_TEST_STALL_BITN 8 -#define WDT_TEST_STALL_M 0x00000100 -#define WDT_TEST_STALL_S 8 -#define WDT_TEST_STALL_EN 0x00000100 -#define WDT_TEST_STALL_DIS 0x00000000 +#define WDT_TEST_STALL 0x00000100 +#define WDT_TEST_STALL_BITN 8 +#define WDT_TEST_STALL_M 0x00000100 +#define WDT_TEST_STALL_S 8 +#define WDT_TEST_STALL_EN 0x00000100 +#define WDT_TEST_STALL_DIS 0x00000000 // Field: [0] TEST_EN // @@ -238,12 +238,12 @@ // ENUMs: // EN Test mode Enabled // DIS Test mode Disabled -#define WDT_TEST_TEST_EN 0x00000001 -#define WDT_TEST_TEST_EN_BITN 0 -#define WDT_TEST_TEST_EN_M 0x00000001 -#define WDT_TEST_TEST_EN_S 0 -#define WDT_TEST_TEST_EN_EN 0x00000001 -#define WDT_TEST_TEST_EN_DIS 0x00000000 +#define WDT_TEST_TEST_EN 0x00000001 +#define WDT_TEST_TEST_EN_BITN 0 +#define WDT_TEST_TEST_EN_M 0x00000001 +#define WDT_TEST_TEST_EN_S 0 +#define WDT_TEST_TEST_EN_EN 0x00000001 +#define WDT_TEST_TEST_EN_DIS 0x00000000 //***************************************************************************** // @@ -254,18 +254,18 @@ // // Indicates that the cause of an interrupt was a reset generated but blocked // due to TEST.TEST_EN (only possible when TEST.TEST_EN is set). -#define WDT_INT_CAUS_CAUSE_RESET 0x00000002 -#define WDT_INT_CAUS_CAUSE_RESET_BITN 1 -#define WDT_INT_CAUS_CAUSE_RESET_M 0x00000002 -#define WDT_INT_CAUS_CAUSE_RESET_S 1 +#define WDT_INT_CAUS_CAUSE_RESET 0x00000002 +#define WDT_INT_CAUS_CAUSE_RESET_BITN 1 +#define WDT_INT_CAUS_CAUSE_RESET_M 0x00000002 +#define WDT_INT_CAUS_CAUSE_RESET_S 1 // Field: [0] CAUSE_INTR // // Replica of RIS.WDTRIS -#define WDT_INT_CAUS_CAUSE_INTR 0x00000001 -#define WDT_INT_CAUS_CAUSE_INTR_BITN 0 -#define WDT_INT_CAUS_CAUSE_INTR_M 0x00000001 -#define WDT_INT_CAUS_CAUSE_INTR_S 0 +#define WDT_INT_CAUS_CAUSE_INTR 0x00000001 +#define WDT_INT_CAUS_CAUSE_INTR_BITN 0 +#define WDT_INT_CAUS_CAUSE_INTR_M 0x00000001 +#define WDT_INT_CAUS_CAUSE_INTR_S 0 //***************************************************************************** // @@ -282,9 +282,8 @@ // // 0x0000.0000: Unlocked // 0x0000.0001: Locked -#define WDT_LOCK_WDTLOCK_W 32 -#define WDT_LOCK_WDTLOCK_M 0xFFFFFFFF -#define WDT_LOCK_WDTLOCK_S 0 - +#define WDT_LOCK_WDTLOCK_W 32 +#define WDT_LOCK_WDTLOCK_M 0xFFFFFFFF +#define WDT_LOCK_WDTLOCK_S 0 #endif // __WDT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_bt5.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_bt5.h index 251c7a4..c34019d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_bt5.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_bt5.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_patch_cpe_bt5.h -* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ -* Revision: $Revision: 18889 $ -* -* Description: RF core patch for Bluetooth 5 support ("BLE" and "BLE5" API command sets) in CC13x2 and CC26x2 -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_cpe_bt5.h + * Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ + * Revision: $Revision: 18889 $ + * + * Description: RF core patch for Bluetooth 5 support ("BLE" and "BLE5" API command sets) in CC13x2 and CC26x2 + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_CPE_BT5_H #define _RF_PATCH_CPE_BT5_H @@ -45,8 +45,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include @@ -68,46 +67,45 @@ extern "C" #define _APPLY_PATCH_TAB #endif - CPE_PATCH_TYPE patchImageBt5[] = -{ - 0x21004059, - 0x210040a5, - 0x21004085, - 0x79654c07, - 0xf809f000, - 0x40697961, - 0xd5030749, - 0x4a042101, - 0x60110389, - 0xb570bd70, - 0x47084902, - 0x21000380, - 0x40041108, - 0x0000592d, - 0x21014805, - 0x438a6802, - 0x6b836002, - 0x6383438b, - 0x6002430a, - 0x47004801, - 0x40046000, - 0x00005b3f, - 0x490cb510, - 0x4a0c4788, - 0x5e512106, - 0xd0072900, - 0xd0052902, - 0xd0032909, - 0xd0012910, - 0xd1072911, - 0x43c92177, - 0xdd014288, - 0xdd012800, - 0x43c0207f, - 0x0000bd10, - 0x000065a9, - 0x21000380, + { + 0x21004059, + 0x210040a5, + 0x21004085, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, + 0x47084902, + 0x21000380, + 0x40041108, + 0x0000592d, + 0x21014805, + 0x438a6802, + 0x6b836002, + 0x6383438b, + 0x6002430a, + 0x47004801, + 0x40046000, + 0x00005b3f, + 0x490cb510, + 0x4a0c4788, + 0x5e512106, + 0xd0072900, + 0xd0052902, + 0xd0032909, + 0xd0012910, + 0xd1072911, + 0x43c92177, + 0xdd014288, + 0xdd012800, + 0x43c0207f, + 0x0000bd10, + 0x000065a9, + 0x21000380, }; #define _NWORD_PATCHIMAGE_BT5 37 @@ -115,8 +113,6 @@ CPE_PATCH_TYPE patchImageBt5[] = #define _NWORD_PATCHSYS_BT5 0 - - #ifndef _BT5_SYSRAM_START #define _BT5_SYSRAM_START 0x20000000 #endif @@ -141,7 +137,7 @@ static uint8_t bBt5PatchEntered = 0; PATCH_FUN_SPEC void enterBt5CpePatch(void) { #if (_NWORD_PATCHIMAGE_BT5 > 0) - uint32_t* pPatchVec = (uint32_t*) (_BT5_CPERAM_START + _BT5_PATCH_VEC_OFFSET); + uint32_t* pPatchVec = (uint32_t*)(_BT5_CPERAM_START + _BT5_PATCH_VEC_OFFSET); memcpy(pPatchVec, patchImageBt5, sizeof(patchImageBt5)); #endif @@ -150,7 +146,7 @@ PATCH_FUN_SPEC void enterBt5CpePatch(void) PATCH_FUN_SPEC void enterBt5CpeHdPatch(void) { #if (_NWORD_PATCHCPEHD_BT5 > 0) - uint32_t* pPatchCpeHd = (uint32_t*) (_BT5_CPERAM_START + _BT5_PATCH_CPEHD_OFFSET); + uint32_t* pPatchCpeHd = (uint32_t*)(_BT5_CPERAM_START + _BT5_PATCH_CPEHD_OFFSET); memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); #endif @@ -162,8 +158,7 @@ PATCH_FUN_SPEC void enterBt5SysPatch(void) PATCH_FUN_SPEC void configureBt5Patch(void) { - uint8_t* pPatchTab = (uint8_t*) (_BT5_CPERAM_START + _BT5_PATCH_TAB_OFFSET); - + uint8_t* pPatchTab = (uint8_t*)(_BT5_CPERAM_START + _BT5_PATCH_TAB_OFFSET); pPatchTab[76] = 0; pPatchTab[91] = 1; @@ -207,7 +202,6 @@ PATCH_FUN_SPEC void rf_patch_cpe_bt5(void) applyBt5Patch(); } - //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. @@ -218,4 +212,3 @@ PATCH_FUN_SPEC void rf_patch_cpe_bt5(void) #endif #endif // _RF_PATCH_CPE_BT5_H - diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_ieee_802_15_4.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_ieee_802_15_4.h index 65a1f0d..2e73430 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_ieee_802_15_4.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_ieee_802_15_4.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_patch_cpe_ieee_802_15_4.h -* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ -* Revision: $Revision: 18889 $ -* -* Description: RF core patch for IEEE 802.15.4-2006 support ("IEEE" API command set) in CC13x2 and CC26x2 -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_cpe_ieee_802_15_4.h + * Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ + * Revision: $Revision: 18889 $ + * + * Description: RF core patch for IEEE 802.15.4-2006 support ("IEEE" API command set) in CC13x2 and CC26x2 + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_CPE_IEEE_802_15_4_H #define _RF_PATCH_CPE_IEEE_802_15_4_H @@ -45,8 +45,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include @@ -68,21 +67,20 @@ extern "C" #define _APPLY_PATCH_TAB #endif - CPE_PATCH_TYPE patchImageIeee802154[] = -{ - 0x21004051, - 0x79654c07, - 0xf809f000, - 0x40697961, - 0xd5030749, - 0x4a042101, - 0x60110389, - 0xb570bd70, - 0x47084902, - 0x21000380, - 0x40041108, - 0x0000592d, + { + 0x21004051, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, + 0x47084902, + 0x21000380, + 0x40041108, + 0x0000592d, }; #define _NWORD_PATCHIMAGE_IEEE_802_15_4 12 @@ -90,8 +88,6 @@ CPE_PATCH_TYPE patchImageIeee802154[] = #define _NWORD_PATCHSYS_IEEE_802_15_4 0 - - #ifndef _IEEE_802_15_4_SYSRAM_START #define _IEEE_802_15_4_SYSRAM_START 0x20000000 #endif @@ -116,7 +112,7 @@ static uint8_t bIeee802154PatchEntered = 0; PATCH_FUN_SPEC void enterIeee802154CpePatch(void) { #if (_NWORD_PATCHIMAGE_IEEE_802_15_4 > 0) - uint32_t* pPatchVec = (uint32_t*) (_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_PATCH_VEC_OFFSET); + uint32_t* pPatchVec = (uint32_t*)(_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_PATCH_VEC_OFFSET); memcpy(pPatchVec, patchImageIeee802154, sizeof(patchImageIeee802154)); #endif @@ -125,7 +121,7 @@ PATCH_FUN_SPEC void enterIeee802154CpePatch(void) PATCH_FUN_SPEC void enterIeee802154CpeHdPatch(void) { #if (_NWORD_PATCHCPEHD_IEEE_802_15_4 > 0) - uint32_t* pPatchCpeHd = (uint32_t*) (_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_PATCH_CPEHD_OFFSET); + uint32_t* pPatchCpeHd = (uint32_t*)(_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_PATCH_CPEHD_OFFSET); memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); #endif @@ -137,8 +133,7 @@ PATCH_FUN_SPEC void enterIeee802154SysPatch(void) PATCH_FUN_SPEC void configureIeee802154Patch(void) { - uint8_t* pPatchTab = (uint8_t*) (_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_PATCH_TAB_OFFSET); - + uint8_t* pPatchTab = (uint8_t*)(_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_PATCH_TAB_OFFSET); pPatchTab[76] = 0; } @@ -180,7 +175,6 @@ PATCH_FUN_SPEC void rf_patch_cpe_ieee_802_15_4(void) applyIeee802154Patch(); } - //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. @@ -191,4 +185,3 @@ PATCH_FUN_SPEC void rf_patch_cpe_ieee_802_15_4(void) #endif #endif // _RF_PATCH_CPE_IEEE_802_15_4_H - diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol.h index 6fcaae8..aa6c8a5 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_patch_cpe_multi_protocol.h -* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ -* Revision: $Revision: 18889 $ -* -* Description: RF core patch for multi-protocol support (all available API command sets) in CC13x2 and CC26x2 -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_cpe_multi_protocol.h + * Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ + * Revision: $Revision: 18889 $ + * + * Description: RF core patch for multi-protocol support (all available API command sets) in CC13x2 and CC26x2 + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_CPE_MULTI_PROTOCOL_H #define _RF_PATCH_CPE_MULTI_PROTOCOL_H @@ -45,8 +45,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include @@ -68,72 +67,71 @@ extern "C" #define _APPLY_PATCH_TAB #endif - CPE_PATCH_TYPE patchImageMultiProtocol[] = -{ - 0x21004061, - 0x210040cb, - 0x2100408d, - 0x2100410d, - 0x210040ed, - 0x79654c07, - 0xf809f000, - 0x40697961, - 0xd5030749, - 0x4a042101, - 0x60110389, - 0xb570bd70, - 0x47084902, - 0x21000380, - 0x40041108, - 0x0000592d, - 0xf819f000, - 0x296cb2e1, - 0x2804d00b, - 0x2806d001, - 0x490ed107, - 0x07c97809, - 0x7821d103, - 0xd4000709, - 0x490b2002, - 0x210c780a, - 0xd0024211, - 0x22804909, - 0xb003600a, - 0xb5f0bdf0, - 0x4907b083, - 0x48044708, - 0x22407801, - 0x70014391, - 0x47004804, - 0x210000c8, - 0x21000133, - 0xe000e200, - 0x00031641, - 0x00031b23, - 0x21014805, - 0x438a6802, - 0x6b836002, - 0x6383438b, - 0x6002430a, - 0x47004801, - 0x40046000, - 0x00005b3f, - 0x490cb510, - 0x4a0c4788, - 0x5e512106, - 0xd0072900, - 0xd0052902, - 0xd0032909, - 0xd0012910, - 0xd1072911, - 0x43c92177, - 0xdd014288, - 0xdd012800, - 0x43c0207f, - 0x0000bd10, - 0x000065a9, - 0x21000380, + { + 0x21004061, + 0x210040cb, + 0x2100408d, + 0x2100410d, + 0x210040ed, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, + 0x47084902, + 0x21000380, + 0x40041108, + 0x0000592d, + 0xf819f000, + 0x296cb2e1, + 0x2804d00b, + 0x2806d001, + 0x490ed107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490b2002, + 0x210c780a, + 0xd0024211, + 0x22804909, + 0xb003600a, + 0xb5f0bdf0, + 0x4907b083, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000133, + 0xe000e200, + 0x00031641, + 0x00031b23, + 0x21014805, + 0x438a6802, + 0x6b836002, + 0x6383438b, + 0x6002430a, + 0x47004801, + 0x40046000, + 0x00005b3f, + 0x490cb510, + 0x4a0c4788, + 0x5e512106, + 0xd0072900, + 0xd0052902, + 0xd0032909, + 0xd0012910, + 0xd1072911, + 0x43c92177, + 0xdd014288, + 0xdd012800, + 0x43c0207f, + 0x0000bd10, + 0x000065a9, + 0x21000380, }; #define _NWORD_PATCHIMAGE_MULTI_PROTOCOL 63 @@ -141,8 +139,6 @@ CPE_PATCH_TYPE patchImageMultiProtocol[] = #define _NWORD_PATCHSYS_MULTI_PROTOCOL 0 - - #ifndef _MULTI_PROTOCOL_SYSRAM_START #define _MULTI_PROTOCOL_SYSRAM_START 0x20000000 #endif @@ -167,7 +163,7 @@ static uint8_t bMultiProtocolPatchEntered = 0; PATCH_FUN_SPEC void enterMultiProtocolCpePatch(void) { #if (_NWORD_PATCHIMAGE_MULTI_PROTOCOL > 0) - uint32_t* pPatchVec = (uint32_t*) (_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_PATCH_VEC_OFFSET); + uint32_t* pPatchVec = (uint32_t*)(_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_PATCH_VEC_OFFSET); memcpy(pPatchVec, patchImageMultiProtocol, sizeof(patchImageMultiProtocol)); #endif @@ -176,7 +172,7 @@ PATCH_FUN_SPEC void enterMultiProtocolCpePatch(void) PATCH_FUN_SPEC void enterMultiProtocolCpeHdPatch(void) { #if (_NWORD_PATCHCPEHD_MULTI_PROTOCOL > 0) - uint32_t* pPatchCpeHd = (uint32_t*) (_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_PATCH_CPEHD_OFFSET); + uint32_t* pPatchCpeHd = (uint32_t*)(_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_PATCH_CPEHD_OFFSET); memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); #endif @@ -188,8 +184,7 @@ PATCH_FUN_SPEC void enterMultiProtocolSysPatch(void) PATCH_FUN_SPEC void configureMultiProtocolPatch(void) { - uint8_t* pPatchTab = (uint8_t*) (_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_PATCH_TAB_OFFSET); - + uint8_t* pPatchTab = (uint8_t*)(_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_PATCH_TAB_OFFSET); pPatchTab[76] = 0; pPatchTab[62] = 1; @@ -235,7 +230,6 @@ PATCH_FUN_SPEC void rf_patch_cpe_multi_protocol(void) applyMultiProtocolPatch(); } - //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. @@ -246,4 +240,3 @@ PATCH_FUN_SPEC void rf_patch_cpe_multi_protocol(void) #endif #endif // _RF_PATCH_CPE_MULTI_PROTOCOL_H - diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol_rtls.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol_rtls.h index ac5f57f..c9b9a68 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol_rtls.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol_rtls.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_patch_cpe_multi_protocol_rtls.h -* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ -* Revision: $Revision: 18889 $ -* -* Description: RF core patch for multi-protocol support (all available API command sets) with RTLS components in CC13x2 and CC26x2 -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_cpe_multi_protocol_rtls.h + * Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ + * Revision: $Revision: 18889 $ + * + * Description: RF core patch for multi-protocol support (all available API command sets) with RTLS components in CC13x2 and CC26x2 + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_CPE_MULTI_PROTOCOL_RTLS_H #define _RF_PATCH_CPE_MULTI_PROTOCOL_RTLS_H @@ -45,8 +45,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include @@ -68,1283 +67,1280 @@ extern "C" #define _APPLY_PATCH_TAB #endif - CPE_PATCH_TYPE patchImageMultiProtocolRtls[] = -{ - 0x21004631, - 0x21004683, - 0x21004075, - 0x2100486f, - 0x210040ad, - 0x21004117, - 0x210040d9, - 0x2100492d, - 0x21004139, - 0x21005349, - 0x68084908, - 0x43902221, - 0x48076008, - 0x68c34700, - 0x230260c3, - 0xd1fd1e5b, - 0x68c32210, - 0x60c34393, - 0x4770618a, - 0x40048000, - 0x00005c01, - 0x4801b430, - 0x00004700, - 0x00020efd, - 0x79654c07, - 0xf809f000, - 0x40697961, - 0xd5030749, - 0x4a042101, - 0x60110389, - 0xb570bd70, - 0x47084902, - 0x21000380, - 0x40041108, - 0x0000592d, - 0xf819f000, - 0x296cb2e1, - 0x2804d00b, - 0x2806d001, - 0x490ed107, - 0x07c97809, - 0x7821d103, - 0xd4000709, - 0x490b2002, - 0x210c780a, - 0xd0024211, - 0x22804909, - 0xb003600a, - 0xb5f0bdf0, - 0x4907b083, - 0x48044708, - 0x22407801, - 0x70014391, - 0x47004804, - 0x210000c8, - 0x21000133, - 0xe000e200, - 0x00031641, - 0x00031b23, - 0x21014805, - 0x438a6802, - 0x6b836002, - 0x6383438b, - 0x6002430a, - 0x47004801, - 0x40046000, - 0x00005b3f, - 0x4803b510, - 0x30106800, - 0xfe72f000, - 0x47084901, - 0x21000108, - 0x000095e3, - 0x4cffb570, - 0x5d002044, - 0x008049fe, - 0x68801840, - 0x46054780, - 0xd0112801, - 0x5d00207e, - 0xd30d2805, - 0x06002021, - 0x00897e41, - 0x7f0a1809, - 0xd0072a02, - 0x77082003, - 0x49f43480, - 0x478888a0, - 0xbd704628, - 0x77012104, - 0x700148f1, - 0xb5ffe7f4, - 0x7e934aec, - 0x49ef185b, - 0x3280600b, - 0x09897891, - 0x49edd16e, - 0x29006909, - 0x680bd06a, - 0x041bb2da, - 0x4be40e1c, - 0x7edb3360, - 0xd01b2c01, - 0x005b2410, - 0x1edb46a6, - 0x4be5469c, - 0x681b684d, - 0x00923108, - 0x1f121852, - 0x9202402b, - 0x4ae13030, - 0x93002401, - 0x60549103, - 0x26224adf, - 0x27106914, - 0x6114433c, - 0xe0302200, - 0x009b2408, - 0x1f9b46a6, - 0xc910e7e2, - 0x40634fd9, - 0x9301402b, - 0x24014623, - 0x603c0364, - 0x34404cd3, - 0x4cd26060, - 0x68643c40, - 0xd5061a24, - 0x3c804cd1, - 0x04bf6827, - 0xbf20d401, - 0x4fcbe7fa, - 0x633c9c01, - 0x44709c02, - 0xd90042a1, - 0x4cc59903, - 0x42346864, - 0x4cc3d006, - 0x68263c80, - 0x43be2702, - 0x26006026, - 0x45621c52, - 0x9c00d3d1, - 0x405c49c0, - 0x3940402c, - 0x1a12684a, - 0x48bcd4fc, - 0x48bc6304, - 0x60412100, - 0x690248bb, - 0x438a2110, - 0xbdff6102, - 0x212248b4, - 0x420a6842, - 0x4ab2d0fc, - 0x68103a80, - 0x43882102, - 0xbdff6010, - 0x4daab5f3, - 0x5d46202f, - 0xb08148b2, - 0x05806900, - 0x2e011600, - 0x1c40d002, - 0xe0001040, - 0x49ad301e, - 0x6a093140, - 0x4ba14aac, - 0x691a4351, - 0x6a1b0e09, - 0xd0222e01, - 0x01591852, - 0x316731ff, - 0x18544b9f, - 0x68d93340, - 0xb2894fa0, - 0xb2821a08, - 0x68783f40, - 0xd4fc1b00, - 0x462860da, - 0x90003060, - 0x49958381, - 0x31122050, - 0x35804788, - 0x980180a8, - 0xd0082800, - 0x990278aa, - 0xfabef000, - 0x1852e007, - 0x31ce0119, - 0x4896e7dc, - 0x99006ac0, - 0x489577c8, - 0x68407829, - 0x08c14348, - 0xd00b2e01, - 0x38134620, - 0x687a340e, - 0xd4fc1b12, - 0x0c0b4a8f, - 0xb2896193, - 0xbdfe6151, - 0x38114620, - 0xe7f23409, - 0x4c7cb570, - 0x35604625, - 0x1e407fa8, - 0xd80d2802, - 0x28006aa0, - 0x2182d004, - 0x70015d09, - 0x62a01c40, - 0x1e406a60, - 0x7fa86260, - 0x77a81cc0, - 0x28057fa8, - 0xd112d322, - 0x28026a60, - 0x497ddd08, - 0x47881e80, - 0x62611c81, - 0xd0012800, - 0xbd702001, - 0x46082100, - 0xff7af7ff, - 0xf7ff2110, - 0x486afef2, - 0x6ac13840, - 0xd0fc07c9, - 0x38804867, - 0x22026801, - 0x60014311, - 0x8ba84964, - 0x60c83140, - 0x36404626, - 0x495e7930, - 0x18400080, - 0x47806880, - 0xd1de2800, - 0x29057fa9, - 0x7fead301, - 0x29047172, - 0x7de1d3d7, - 0xd1022900, - 0x29007e21, - 0x7eead0d1, - 0x015268e1, - 0x60e11889, - 0xb570bd70, - 0x20444d4f, - 0x48535d46, - 0x3820494e, - 0x00b07ec4, - 0x68801840, - 0x4b5a4780, - 0x781a09a1, - 0xd10a4211, - 0x21ff2221, - 0x76510612, - 0x22004948, - 0x600a1f09, - 0x2101604a, - 0x212f7019, - 0x29025d49, - 0x2e31d008, - 0x07e1d003, - 0xd0032900, - 0x0861e003, - 0xe7f907c9, - 0x35802400, - 0xbd70706c, - 0x4c39b5f8, - 0x46272500, - 0x723d3760, - 0x5d00202f, - 0xd03a2802, - 0x47804845, - 0x36404626, - 0x7ff04937, - 0x62203920, - 0x43087849, - 0x48347560, - 0x38406265, - 0x2d007fc5, - 0x7d20d006, - 0x43082120, - 0x06e87520, - 0x72380ec0, - 0x7f30493a, - 0x4a3a4788, - 0xd0112d00, - 0x61c54839, - 0x20074b28, - 0x63983b40, - 0x21054d26, - 0x07806950, - 0x6868d1fc, - 0xd0f94208, - 0x30404831, - 0x63186800, - 0x28007f30, - 0x6e60d001, - 0x6be16210, - 0x47882039, - 0x20006420, - 0x482cbdf8, - 0xb5f0e7fa, - 0x20444915, - 0x2b045c43, - 0x460ad00a, - 0x78103268, - 0x28004f12, - 0x28ffd070, - 0x2b04d012, - 0xe006d003, - 0x327b460a, - 0x68cce7f3, - 0x19640145, - 0x242f60cc, - 0x2c015c64, - 0x0640d101, - 0x62480e00, - 0x701020ff, - 0x4c09202f, - 0x60200200, - 0x6a484d07, - 0x68623d40, - 0xd03f07d2, - 0xe02b220f, - 0x21000160, - 0x00025500, - 0x0000423d, - 0x21000020, - 0x40045080, - 0x210000e8, - 0x40022080, - 0x40043040, - 0xe000ed00, - 0xe000e280, - 0x400452c0, - 0x00155556, - 0x40046040, - 0x210002c0, - 0x40045180, - 0x0002175f, - 0x210004e0, - 0x00020749, - 0x00020e45, - 0x40042000, - 0x40042100, - 0x0002469d, - 0x4ec363aa, - 0x2801e003, - 0x632edd07, - 0x28001e80, - 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0x68f06932, + 0x4a2ce002, + 0x61326852, + 0x428a1a12, + 0x2d00d3f9, + 0x2c00d006, + 0x6931d004, + 0x46601a09, + 0x1bc31a08, + 0x1ac06930, + 0x2c0060f0, + 0x2000d001, + 0x2000bdfe, + 0xbdfe43c0, + 0x4605b538, + 0xff39f7ff, + 0x2100481a, + 0x210862c1, + 0x4c1a6201, + 0x93007823, + 0x4b2068a0, + 0x0f000500, + 0xf7ff7862, + 0x2000ff07, + 0xfee2f7ff, + 0x2d006861, + 0xd1006808, + 0x462a8dc8, + 0xf7ff2101, + 0xbd38ff52, + 0x4c0db530, + 0x62e52500, + 0x3a100112, + 0x430a1e49, + 0x626361e2, + 0x1c800200, + 0x480961a0, + 0x60012101, + 0x61456942, + 0x32404a06, + 0x68406011, + 0xe0173028, + 0x40041100, + 0x40046000, + 0x40045040, + 0x210053e8, + 0x40043000, + 0x40045300, + 0x400451c0, + 0x40044040, + 0x08180532, + 0x0818070e, + 0xfff000ff, + 0x0000aaaa, + 0x318049ff, + 0xbd306008, + 0x4605b538, + 0xfee5f7ff, + 0x210048fc, + 0x210662c1, + 0x4cfb6201, + 0x78232108, + 0x68a09300, + 0x05004bf9, + 0x78620f00, + 0xffb8f7ff, + 0x48f749f8, + 0x200161c8, + 0xfe8af7ff, + 0x462a6860, + 0x21016800, + 0xfefdf7ff, + 0xb530bd38, + 0x4bf24df2, + 0x35804cf2, + 0xd00e2a40, + 0x58420089, + 0x625a0c12, + 0xb2925842, + 0x1808629a, + 0x0c096841, + 0x684062a1, + 0x6328b280, + 0x00c9bd30, + 0x0c125842, + 0x584262da, + 0x631ab292, + 0x68411808, + 0x62590c09, + 0xb2896841, + 0x68816299, + 0x49e00c0a, + 0x634a31c0, + 0xb2926882, + 0x68c1638a, + 0x62a10c09, + 0xe7e168c0, + 0x4606b5f0, + 0x2080b089, + 0xfa8ef000, + 0x2500b662, + 0x204f4cd2, + 0x60e56066, + 0x00c049d6, + 0x47889501, + 0x68606125, + 0x290079c1, + 0x21ffd001, + 0x30203101, + 0x4acf60a1, + 0x62117901, + 0x21207902, + 0xd1002a00, + 0x70212140, + 0x21027980, + 0xd1002800, + 0x48ca2101, + 0x47807061, + 0x49c06860, + 0x79403020, + 0x62c83180, + 0x478048c6, + 0x80602000, + 0x384048bf, + 0x48c56bc0, + 0x610149c3, + 0x90002000, + 0x684849b8, + 0x24003020, + 0x46267c40, + 0x46259405, + 0x90029403, + 0x48b3e20c, + 0x4ab02700, + 0x68506147, + 0x31504601, + 0x48ade001, + 0x42886840, + 0x48b8d3fb, + 0x48b64780, + 0x48b76147, + 0x7ac07ac1, + 0x0fc907c9, + 0x40102202, + 0xd0024301, + 0xb00948b3, + 0x48a5bdf0, + 0x80412100, + 0x97076847, + 0x7cf93720, + 0x90060860, + 0xfa32f000, + 0xd1142900, + 0x42a09805, + 0x9802d011, + 0xd03b2800, + 0x07c09902, + 0x0fc00849, + 0x28009102, + 0x7cb8d002, + 0x90024048, + 0x98027c39, + 0xfa1cf000, + 0x9807460d, + 0x6b409405, + 0x5bc200ef, + 0x428a9900, + 0x1db9d02e, + 0x1d395a43, + 0x5c439300, + 0x5c421cb9, + 0x5c411cf9, + 0xf000200e, + 0x488afa0d, + 0x68402201, + 0x6b402300, + 0x5bc04611, + 0xf0000400, + 0x488dfa09, + 0x48924780, + 0x29037801, + 0x4882d1fc, + 0x8f096841, + 0x497e8041, + 0x46026848, + 0xe0073238, + 0x7c381c6d, + 0x42a8b2ed, + 0x2500d8cd, + 0x6848e7cb, + 0xd3fc4290, + 0x68404878, + 0x5bc06b40, + 0x48799000, + 0x68813840, + 0xf000207e, + 0x4873f9eb, + 0x6a386847, + 0xd0062800, + 0x46200041, + 0xf9d0f000, + 0xd0052900, + 0x496de014, + 0x780a69b8, + 0xe0334621, + 0xd00b2c00, + 0x30204638, + 0x07ca7fc1, + 0x2201d018, + 0x43917782, + 0x496f77c1, + 0x608802d0, + 0x900469b8, + 0x90076a38, + 0x46200041, + 0xf9b2f000, + 0x42819807, + 0x2c00d113, + 0x4638d00f, + 0x7fc13020, + 0xd401078a, + 0xe7664869, + 0x77822202, + 0x401122fd, + 0x200177c1, + 0x02c04960, + 0x69f86088, + 0x46209004, + 0xf0006a39, + 0x4852f997, + 0x98047802, + 0xfec1f7ff, + 0xd1042c00, + 0x6840484e, + 0x28027980, + 0x9806d00c, + 0x484b9001, + 0x79806840, + 0xd0072801, + 0x28004f48, + 0x2802d058, + 0xe078d07e, + 0xe12f2402, + 0xf7ff4620, + 0xb280fe87, + 0x48414684, + 0x6ac33040, + 0x68504a40, + 0x98016907, + 0x1d4800c1, + 0x6850543b, + 0x1d086903, + 0x4660541d, + 0xd00e2800, + 0x20006852, + 0x691243c0, + 0x50502c00, + 0xe002d167, + 0xb2a41ca4, + 0x9803e053, + 0x90031c40, + 0x6857e04f, + 0x5dc02027, + 0xd0012801, + 0xe0146950, + 0x30804832, + 0x071b6a83, + 0x61530f1b, + 0x05806a80, + 0x2b070e80, + 0x3b10dd01, + 0x281f6153, + 0x3840dd01, + 0x0100b200, + 0x010018c0, + 0x30ff6150, + 0x30014b33, + 0xd3014298, + 0x61502000, + 0x30804824, + 0x69536a40, + 0x18c00200, + 0x5058693b, + 0xb2816950, + 0xe0ca207f, + 0xf7ff4620, + 0xb281fddf, + 0x30404817, + 0x48176ac3, + 0x69076840, + 0x00c09801, + 0x54bb1d42, + 0x1d034a13, + 0x29006852, + 0x54d56912, + 0x4910d04e, + 0x68492200, + 0x690943d2, + 0x500a2c00, + 0x1c76d0af, + 0x2c01b2b6, + 0xf7ffd8a8, + 0x4809fbf5, + 0x8d386847, + 0xe00042b0, + 0xd303e040, + 0x99038d7a, + 0xd27e428a, + 0x42884914, + 0xe054e028, + 0x40043000, + 0x40046000, + 0x210053e8, + 0x0000aaaa, + 0x08180532, + 0x40044040, + 0x40045140, + 0x40045300, + 0x0000424f, + 0x00009083, + 0x00004be3, + 0x0000c210, + 0x40041100, + 0x00000de5, + 0x21000128, + 0x04040003, + 0x210002e4, + 0x04060003, + 0x00000201, + 0x0000ffff, + 0x8d78d102, + 0xd06f4288, + 0x484d2101, + 0x60810449, + 0xe684484c, + 0x21004a4c, + 0x69126852, + 0xe75f5011, + 0xf7ff4620, + 0xb282fcc6, + 0x46946878, + 0x98016903, + 0x00c04639, + 0x549d1d02, + 0x6ad34a44, + 0x6917687a, + 0x54bb1d42, + 0x2a004662, + 0x6849d00a, + 0x43d22200, + 0x2c026909, + 0xd800500a, + 0x1c76e745, + 0xe73fb2b6, + 0x68494939, + 0x3120468c, + 0x290179c9, + 0x4938d125, + 0x07136a8a, + 0x0f1b4a37, + 0x6a896997, + 0x0f3f073f, + 0x69920589, + 0x05920e89, + 0x2b070e92, + 0x3b10dd00, + 0xdd002f07, + 0x291f3f10, + 0x3940dd01, + 0x2a1fb209, + 0x3a40dd03, + 0xe01fe000, + 0x0109b212, + 0x19c918c9, + 0x18890112, + 0x4924010a, + 0x4923614a, + 0x694a4b26, + 0x320132ff, + 0xd301429a, + 0x614a2200, + 0x6a524a20, + 0x0212694b, + 0x466218d3, + 0x50136912, + 0xb2816948, + 0xf0002083, + 0xe6fbf873, + 0x98018fb9, + 0xf856f000, + 0xd1072900, + 0x28009801, + 0x8778d004, + 0x48102101, + 0x608103c9, + 0x68414810, + 0x42a18889, + 0xe5ecd900, + 0x480b2101, + 0x60810409, + 0x1e49480b, + 0x8d026840, + 0xd103428a, + 0x42888d40, + 0xe5d3d100, + 0x98014906, + 0x87486849, + 0xf0002081, + 0x2000f825, + 0x0000e5ef, + 0x40041100, + 0x04030003, + 0x210053e8, + 0x40046040, + 0x400451c0, + 0x40045080, + 0x00000201, + 0x49068800, + 0xd1064288, + 0x21004805, + 0x49058501, + 0x20016241, + 0x20824770, + 0x00004770, + 0x00006801, + 0x21000108, + 0x21004159, + 0x4801b403, + 0xbd019001, + 0x00003cc3, + 0x4801b403, + 0xbd019001, + 0x0000937d, + 0x4801b403, + 0xbd019001, + 0x00009361, + 0x4801b403, + 0xbd019001, + 0x0000867b, + 0x4801b403, + 0xbd019001, + 0x000049a3, + 0x4801b403, + 0xbd019001, + 0x00003c8f, + 0x4801b403, + 0xbd019001, + 0x00003ca9, + 0x4674b430, + 0x78251e64, + 0x42ab1c64, + 0x461dd200, + 0x005b5d63, + 0xbc3018e3, + 0x00004718, + 0x08180532, + 0x0818070e, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, }; #define _NWORD_PATCHIMAGE_MULTI_PROTOCOL_RTLS 1261 CPE_PATCH_TYPE patchCpeHd[] = -{ - 0x00000000, + { + 0x00000000, }; #define _NWORD_PATCHCPEHD_MULTI_PROTOCOL_RTLS 1 #define _NWORD_PATCHSYS_MULTI_PROTOCOL_RTLS 0 - - #ifndef _MULTI_PROTOCOL_RTLS_SYSRAM_START #define _MULTI_PROTOCOL_RTLS_SYSRAM_START 0x20000000 #endif @@ -1369,7 +1365,7 @@ static uint8_t bMultiProtocolRtlsPatchEntered = 0; PATCH_FUN_SPEC void enterMultiProtocolRtlsCpePatch(void) { #if (_NWORD_PATCHIMAGE_MULTI_PROTOCOL_RTLS > 0) - uint32_t* pPatchVec = (uint32_t*) (_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_PATCH_VEC_OFFSET); + uint32_t* pPatchVec = (uint32_t*)(_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_PATCH_VEC_OFFSET); memcpy(pPatchVec, patchImageMultiProtocolRtls, sizeof(patchImageMultiProtocolRtls)); #endif @@ -1378,7 +1374,7 @@ PATCH_FUN_SPEC void enterMultiProtocolRtlsCpePatch(void) PATCH_FUN_SPEC void enterMultiProtocolRtlsCpeHdPatch(void) { #if (_NWORD_PATCHCPEHD_MULTI_PROTOCOL_RTLS > 0) - uint32_t* pPatchCpeHd = (uint32_t*) (_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_PATCH_CPEHD_OFFSET); + uint32_t* pPatchCpeHd = (uint32_t*)(_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_PATCH_CPEHD_OFFSET); memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); #endif @@ -1390,8 +1386,7 @@ PATCH_FUN_SPEC void enterMultiProtocolRtlsSysPatch(void) PATCH_FUN_SPEC void configureMultiProtocolRtlsPatch(void) { - uint8_t* pPatchTab = (uint8_t*) (_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_PATCH_TAB_OFFSET); - + uint8_t* pPatchTab = (uint8_t*)(_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_PATCH_TAB_OFFSET); pPatchTab[1] = 0; pPatchTab[18] = 1; @@ -1442,7 +1437,6 @@ PATCH_FUN_SPEC void rf_patch_cpe_multi_protocol_rtls(void) applyMultiProtocolRtlsPatch(); } - //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. @@ -1453,4 +1447,3 @@ PATCH_FUN_SPEC void rf_patch_cpe_multi_protocol_rtls(void) #endif #endif // _RF_PATCH_CPE_MULTI_PROTOCOL_RTLS_H - diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_prop.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_prop.h index bcc133f..0103cbf 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_prop.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_prop.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_patch_cpe_prop.h -* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ -* Revision: $Revision: 18889 $ -* -* Description: RF core patch for proprietary radio support ("PROP" API command set) in CC13x2 and CC26x2 -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_cpe_prop.h + * Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ + * Revision: $Revision: 18889 $ + * + * Description: RF core patch for proprietary radio support ("PROP" API command set) in CC13x2 and CC26x2 + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_CPE_PROP_H #define _RF_PATCH_CPE_PROP_H @@ -45,8 +45,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include @@ -68,47 +67,46 @@ extern "C" #define _APPLY_PATCH_TAB #endif - CPE_PATCH_TYPE patchImageProp[] = -{ - 0x21004059, - 0x210040c3, - 0x21004085, - 0x79654c07, - 0xf809f000, - 0x40697961, - 0xd5030749, - 0x4a042101, - 0x60110389, - 0xb570bd70, - 0x47084902, - 0x21000380, - 0x40041108, - 0x0000592d, - 0xf819f000, - 0x296cb2e1, - 0x2804d00b, - 0x2806d001, - 0x490ed107, - 0x07c97809, - 0x7821d103, - 0xd4000709, - 0x490b2002, - 0x210c780a, - 0xd0024211, - 0x22804909, - 0xb003600a, - 0xb5f0bdf0, - 0x4907b083, - 0x48044708, - 0x22407801, - 0x70014391, - 0x47004804, - 0x210000c8, - 0x21000133, - 0xe000e200, - 0x00031641, - 0x00031b23, + { + 0x21004059, + 0x210040c3, + 0x21004085, + 0x79654c07, + 0xf809f000, + 0x40697961, + 0xd5030749, + 0x4a042101, + 0x60110389, + 0xb570bd70, + 0x47084902, + 0x21000380, + 0x40041108, + 0x0000592d, + 0xf819f000, + 0x296cb2e1, + 0x2804d00b, + 0x2806d001, + 0x490ed107, + 0x07c97809, + 0x7821d103, + 0xd4000709, + 0x490b2002, + 0x210c780a, + 0xd0024211, + 0x22804909, + 0xb003600a, + 0xb5f0bdf0, + 0x4907b083, + 0x48044708, + 0x22407801, + 0x70014391, + 0x47004804, + 0x210000c8, + 0x21000133, + 0xe000e200, + 0x00031641, + 0x00031b23, }; #define _NWORD_PATCHIMAGE_PROP 38 @@ -116,8 +114,6 @@ CPE_PATCH_TYPE patchImageProp[] = #define _NWORD_PATCHSYS_PROP 0 - - #ifndef _PROP_SYSRAM_START #define _PROP_SYSRAM_START 0x20000000 #endif @@ -142,7 +138,7 @@ static uint8_t bPropPatchEntered = 0; PATCH_FUN_SPEC void enterPropCpePatch(void) { #if (_NWORD_PATCHIMAGE_PROP > 0) - uint32_t* pPatchVec = (uint32_t*) (_PROP_CPERAM_START + _PROP_PATCH_VEC_OFFSET); + uint32_t* pPatchVec = (uint32_t*)(_PROP_CPERAM_START + _PROP_PATCH_VEC_OFFSET); memcpy(pPatchVec, patchImageProp, sizeof(patchImageProp)); #endif @@ -151,7 +147,7 @@ PATCH_FUN_SPEC void enterPropCpePatch(void) PATCH_FUN_SPEC void enterPropCpeHdPatch(void) { #if (_NWORD_PATCHCPEHD_PROP > 0) - uint32_t* pPatchCpeHd = (uint32_t*) (_PROP_CPERAM_START + _PROP_PATCH_CPEHD_OFFSET); + uint32_t* pPatchCpeHd = (uint32_t*)(_PROP_CPERAM_START + _PROP_PATCH_CPEHD_OFFSET); memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); #endif @@ -163,8 +159,7 @@ PATCH_FUN_SPEC void enterPropSysPatch(void) PATCH_FUN_SPEC void configurePropPatch(void) { - uint8_t* pPatchTab = (uint8_t*) (_PROP_CPERAM_START + _PROP_PATCH_TAB_OFFSET); - + uint8_t* pPatchTab = (uint8_t*)(_PROP_CPERAM_START + _PROP_PATCH_TAB_OFFSET); pPatchTab[76] = 0; pPatchTab[62] = 1; @@ -208,7 +203,6 @@ PATCH_FUN_SPEC void rf_patch_cpe_prop(void) applyPropPatch(); } - //***************************************************************************** // // Mark the end of the C bindings section for C++ compilers. @@ -219,4 +213,3 @@ PATCH_FUN_SPEC void rf_patch_cpe_prop(void) #endif #endif // _RF_PATCH_CPE_PROP_H - diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_iqdump.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_iqdump.h index 3c52031..9cd99a0 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_iqdump.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_iqdump.h @@ -1,403 +1,402 @@ /****************************************************************************** -* Filename: rf_patch_mce_iqdump.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for IQ-dump support in CC13x2 PG2.1 and CC26x2 PG2.1 -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_mce_iqdump.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for IQ-dump support in CC13x2 PG2.1 and CC26x2 PG2.1 + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_MCE_IQDUMP_H #define _RF_PATCH_MCE_IQDUMP_H -#include #include "../inc/hw_types.h" +#include #ifndef MCE_PATCH_TYPE - #define MCE_PATCH_TYPE static const uint32_t +#define MCE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_MCERAM_BASE - #define RFC_MCERAM_BASE 0x21008000 +#define RFC_MCERAM_BASE 0x21008000 #endif #ifndef MCE_PATCH_MODE - #define MCE_PATCH_MODE 0 +#define MCE_PATCH_MODE 0 #endif MCE_PATCH_TYPE patchIqdumpMce[337] = -{ - 0x2fcf6030, - 0x00013f9d, - 0xff00003f, - 0x07ff0fff, - 0x0300f800, - 0x00068080, - 0x00170003, - 0x00003d1f, - 0x08000000, - 0x0000000f, - 0x00000387, - 0x00434074, - 0x00828000, - 0x06f00080, - 0x091e0000, - 0x00540510, - 0x00000007, - 0x00505014, - 0xc02f0000, - 0x017f0c30, - 0x00000000, - 0x00000000, - 0x00000000, - 0x0000aa00, - 0x66957223, - 0xa4e5a35d, - 0x73057303, - 0x73047203, - 0x72047306, - 0x72917391, - 0xffc0b008, - 0xa0089010, - 0x720e720d, - 0x7210720f, - 0x7100b0d0, - 0xa0d0b110, - 0x8162721b, - 0x39521020, - 0x00200670, - 0x11011630, - 0x6c011401, - 0x60816080, - 0x610b60fd, - 0x60806080, - 0x60806080, - 0x60816080, - 0x61af60fd, - 0x60806080, - 0x60806080, - 0x60816080, - 0x611b60fd, - 0x60806080, - 0x60806080, - 0x60816080, - 0x61cb60fd, - 0x60806080, - 0x60806080, - 0x60816080, - 0x615360fd, - 0x72231210, - 0x73127311, - 0x81b17313, - 0x91b00010, - 0x6044b070, - 0xc0306076, - 0xc0c1669b, - 0xc4e0c2b2, - 0x6f131820, - 0x16116e23, - 0x68871612, - 0x99c07830, - 0x948078a0, - 0xc4f29490, - 0x1820c750, - 0x12034099, - 0x16126e23, - 0x78b06896, - 0x72639990, - 0x6076b63c, - 0x96408190, - 0x39808170, - 0x10012a70, - 0x84a21611, - 0xc0f384b4, - 0xc200c0f5, - 0x40c21c01, - 0x1c10c100, - 0x4cba40b8, - 0x18031013, - 0x1a131830, - 0x39121a10, - 0x60c268b5, - 0x60c213f3, - 0x101513f3, - 0x1850c100, - 0x1a101a15, - 0x68c03914, - 0x7100b0e8, - 0xa0e8b128, - 0xb910b230, - 0x99308990, - 0xb0d1b111, - 0xb0027100, - 0xb111b012, - 0x7291a0d1, - 0xb003b630, - 0x722cb013, - 0x7100b0e0, - 0x8170b120, - 0x710092c0, - 0x8170b120, - 0x44db22f0, - 0x1c0313f0, - 0x92c340e7, - 0x71009642, - 0x92c5b120, - 0x71009644, - 0xb0e0b120, - 0x7000a630, - 0xc030a0e1, - 0xc0409910, - 0xb1119930, - 0x7100b0d1, - 0xa0d1b111, - 0xa0037291, - 0xa230a002, - 0x73117000, - 0xc0407312, - 0xc100669b, - 0x649e91f0, - 0xb113b633, - 0x7100b0d3, - 0x64eea0d3, - 0xa0d26076, - 0xa0f3a0f0, - 0x73127311, - 0xc050660f, - 0xb0d2669b, - 0x7100c035, - 0xba389b75, - 0xb112b074, - 0xa0d26115, - 0xa0f3a0f0, - 0x73127311, - 0xc18b660f, - 0x91e0c000, - 0x1218120c, - 0x787d786a, - 0x10a9788e, - 0xb0d2b074, - 0xb112c020, - 0x692d7100, - 0x669bc060, - 0xb112c035, - 0x9b757100, - 0x65a48bf0, - 0x22018ca1, - 0x10804140, - 0x453f1ca8, - 0x16181208, - 0x8c00659b, - 0x8ca165a4, - 0x414b2201, - 0x1a191090, - 0x454b1e09, - 0x659b10a9, - 0x1e048184, - 0x14bc4133, - 0x4e7e1c4c, - 0xa0d26133, - 0xa0f3a0f0, - 0x73127311, - 0x721e660f, - 0x1205120c, - 0xb0d2b074, - 0xb112c020, - 0x695f7100, - 0x669bc070, - 0x89ce789d, - 0x7100b112, - 0x22008c90, - 0x8230416f, - 0x456f2210, - 0x9a3db231, - 0x31828ab2, - 0x8af03d82, - 0x3d803180, - 0x063e1802, - 0x41911e0e, - 0x41831e2e, - 0x418a1e3e, - 0x14261056, - 0x10653d16, - 0x10566192, - 0x18563126, - 0x3d261426, - 0x61921065, - 0x31361056, - 0x14261856, - 0x10653d36, - 0x10266192, - 0x91c63976, - 0x1e048184, - 0x161c4166, - 0x4e7e1c4c, - 0x10016166, - 0x91c1c0b0, - 0x10003911, - 0x10001000, - 0x7000699d, - 0x3d303130, - 0x4dab1cd0, - 0x49ad1ce0, - 0x10d07000, - 0x10e07000, - 0xc0807000, - 0xa0d2669b, - 0xa0f3a0f0, - 0x73127311, - 0xb130660f, - 0x7100b0f0, - 0x220080b0, - 0x61b945be, - 0xc090b231, - 0xb130669b, - 0xb0d2a0f0, - 0x7100c035, - 0xba389b75, - 0xb112b074, - 0xc0a061c5, - 0xa0d2669b, - 0xa0f3a0f0, - 0x73127311, - 0xc18b660f, - 0x91e0c000, - 0x1218120c, - 0x787d786a, - 0x10a9788e, - 0xb0f0b130, - 0x80b07100, - 0x45e32200, - 0xb07461de, - 0xc0b0b231, - 0xb130669b, - 0xb0d2a0f0, - 0xb112c020, - 0x69eb7100, - 0xb112c035, - 0x9b757100, - 0x65a48bf0, - 0x22018ca1, - 0x108041fc, - 0x45fb1ca8, - 0x16181208, - 0x8c00659b, - 0x8ca165a4, - 0x42072201, - 0x1a191090, - 0x46071e09, - 0x659b10a9, - 0x1e048184, - 0x14bc41ef, - 0x4e7e1c4c, - 0x824061ef, - 0x46172230, - 0x7100b0d5, - 0xa0d5b115, - 0xc0c0620f, - 0xb118669b, - 0xb016b006, - 0xb014b004, - 0xb012b002, - 0x78428440, - 0x81730420, - 0x2a733983, - 0xc1f294e3, - 0x31621832, - 0x31511021, - 0x00200012, - 0x10309440, - 0x39301610, - 0x42352210, - 0x31501220, - 0x31801003, - 0x93801630, - 0x12041202, - 0x42472273, - 0x997084a0, - 0x1a828982, - 0x997084c0, - 0x1a848984, - 0x22636249, - 0x84b04254, - 0x89809970, - 0x14021a80, - 0x997084d0, - 0x1a808980, - 0x62601404, - 0x785184b0, - 0x99700410, - 0x1a428982, - 0x785184d0, - 0x99700410, - 0x1a448984, - 0x31543152, - 0x06333963, - 0x38321613, - 0x31823834, - 0x31843982, - 0x97220042, - 0x959084a0, - 0x95a084b0, - 0x95b084c0, - 0x95c084d0, - 0x90307810, - 0x78209050, - 0x90609040, - 0xcd90b235, - 0x70009170, - 0xb112a235, - 0xa0d27100, - 0xba3cb112, - 0x8b5481b0, - 0x31843924, - 0x91b40004, - 0x669bc0d0, - 0x72917391, - 0x72066695, - 0x72047202, - 0x73067305, - 0x86306076, - 0x3151c801, - 0x96300410, - 0x9a007000, - 0x220089f0, - 0xb9e0469c, - 0x00007000 -}; + { + 0x2fcf6030, + 0x00013f9d, + 0xff00003f, + 0x07ff0fff, + 0x0300f800, + 0x00068080, + 0x00170003, + 0x00003d1f, + 0x08000000, + 0x0000000f, + 0x00000387, + 0x00434074, + 0x00828000, + 0x06f00080, + 0x091e0000, + 0x00540510, + 0x00000007, + 0x00505014, + 0xc02f0000, + 0x017f0c30, + 0x00000000, + 0x00000000, + 0x00000000, + 0x0000aa00, + 0x66957223, + 0xa4e5a35d, + 0x73057303, + 0x73047203, + 0x72047306, + 0x72917391, + 0xffc0b008, + 0xa0089010, + 0x720e720d, + 0x7210720f, + 0x7100b0d0, + 0xa0d0b110, + 0x8162721b, + 0x39521020, + 0x00200670, + 0x11011630, + 0x6c011401, + 0x60816080, + 0x610b60fd, + 0x60806080, + 0x60806080, + 0x60816080, + 0x61af60fd, + 0x60806080, + 0x60806080, + 0x60816080, + 0x611b60fd, + 0x60806080, + 0x60806080, + 0x60816080, + 0x61cb60fd, + 0x60806080, + 0x60806080, + 0x60816080, + 0x615360fd, + 0x72231210, + 0x73127311, + 0x81b17313, + 0x91b00010, + 0x6044b070, + 0xc0306076, + 0xc0c1669b, + 0xc4e0c2b2, + 0x6f131820, + 0x16116e23, + 0x68871612, + 0x99c07830, + 0x948078a0, + 0xc4f29490, + 0x1820c750, + 0x12034099, + 0x16126e23, + 0x78b06896, + 0x72639990, + 0x6076b63c, + 0x96408190, + 0x39808170, + 0x10012a70, + 0x84a21611, + 0xc0f384b4, + 0xc200c0f5, + 0x40c21c01, + 0x1c10c100, + 0x4cba40b8, + 0x18031013, + 0x1a131830, + 0x39121a10, + 0x60c268b5, + 0x60c213f3, + 0x101513f3, + 0x1850c100, + 0x1a101a15, + 0x68c03914, + 0x7100b0e8, + 0xa0e8b128, + 0xb910b230, + 0x99308990, + 0xb0d1b111, + 0xb0027100, + 0xb111b012, + 0x7291a0d1, + 0xb003b630, + 0x722cb013, + 0x7100b0e0, + 0x8170b120, + 0x710092c0, + 0x8170b120, + 0x44db22f0, + 0x1c0313f0, + 0x92c340e7, + 0x71009642, + 0x92c5b120, + 0x71009644, + 0xb0e0b120, + 0x7000a630, + 0xc030a0e1, + 0xc0409910, + 0xb1119930, + 0x7100b0d1, + 0xa0d1b111, + 0xa0037291, + 0xa230a002, + 0x73117000, + 0xc0407312, + 0xc100669b, + 0x649e91f0, + 0xb113b633, + 0x7100b0d3, + 0x64eea0d3, + 0xa0d26076, + 0xa0f3a0f0, + 0x73127311, + 0xc050660f, + 0xb0d2669b, + 0x7100c035, + 0xba389b75, + 0xb112b074, + 0xa0d26115, + 0xa0f3a0f0, + 0x73127311, + 0xc18b660f, + 0x91e0c000, + 0x1218120c, + 0x787d786a, + 0x10a9788e, + 0xb0d2b074, + 0xb112c020, + 0x692d7100, + 0x669bc060, + 0xb112c035, + 0x9b757100, + 0x65a48bf0, + 0x22018ca1, + 0x10804140, + 0x453f1ca8, + 0x16181208, + 0x8c00659b, + 0x8ca165a4, + 0x414b2201, + 0x1a191090, + 0x454b1e09, + 0x659b10a9, + 0x1e048184, + 0x14bc4133, + 0x4e7e1c4c, + 0xa0d26133, + 0xa0f3a0f0, + 0x73127311, + 0x721e660f, + 0x1205120c, + 0xb0d2b074, + 0xb112c020, + 0x695f7100, + 0x669bc070, + 0x89ce789d, + 0x7100b112, + 0x22008c90, + 0x8230416f, + 0x456f2210, + 0x9a3db231, + 0x31828ab2, + 0x8af03d82, + 0x3d803180, + 0x063e1802, + 0x41911e0e, + 0x41831e2e, + 0x418a1e3e, + 0x14261056, + 0x10653d16, + 0x10566192, + 0x18563126, + 0x3d261426, + 0x61921065, + 0x31361056, + 0x14261856, + 0x10653d36, + 0x10266192, + 0x91c63976, + 0x1e048184, + 0x161c4166, + 0x4e7e1c4c, + 0x10016166, + 0x91c1c0b0, + 0x10003911, + 0x10001000, + 0x7000699d, + 0x3d303130, + 0x4dab1cd0, + 0x49ad1ce0, + 0x10d07000, + 0x10e07000, + 0xc0807000, + 0xa0d2669b, + 0xa0f3a0f0, + 0x73127311, + 0xb130660f, + 0x7100b0f0, + 0x220080b0, + 0x61b945be, + 0xc090b231, + 0xb130669b, + 0xb0d2a0f0, + 0x7100c035, + 0xba389b75, + 0xb112b074, + 0xc0a061c5, + 0xa0d2669b, + 0xa0f3a0f0, + 0x73127311, + 0xc18b660f, + 0x91e0c000, + 0x1218120c, + 0x787d786a, + 0x10a9788e, + 0xb0f0b130, + 0x80b07100, + 0x45e32200, + 0xb07461de, + 0xc0b0b231, + 0xb130669b, + 0xb0d2a0f0, + 0xb112c020, + 0x69eb7100, + 0xb112c035, + 0x9b757100, + 0x65a48bf0, + 0x22018ca1, + 0x108041fc, + 0x45fb1ca8, + 0x16181208, + 0x8c00659b, + 0x8ca165a4, + 0x42072201, + 0x1a191090, + 0x46071e09, + 0x659b10a9, + 0x1e048184, + 0x14bc41ef, + 0x4e7e1c4c, + 0x824061ef, + 0x46172230, + 0x7100b0d5, + 0xa0d5b115, + 0xc0c0620f, + 0xb118669b, + 0xb016b006, + 0xb014b004, + 0xb012b002, + 0x78428440, + 0x81730420, + 0x2a733983, + 0xc1f294e3, + 0x31621832, + 0x31511021, + 0x00200012, + 0x10309440, + 0x39301610, + 0x42352210, + 0x31501220, + 0x31801003, + 0x93801630, + 0x12041202, + 0x42472273, + 0x997084a0, + 0x1a828982, + 0x997084c0, + 0x1a848984, + 0x22636249, + 0x84b04254, + 0x89809970, + 0x14021a80, + 0x997084d0, + 0x1a808980, + 0x62601404, + 0x785184b0, + 0x99700410, + 0x1a428982, + 0x785184d0, + 0x99700410, + 0x1a448984, + 0x31543152, + 0x06333963, + 0x38321613, + 0x31823834, + 0x31843982, + 0x97220042, + 0x959084a0, + 0x95a084b0, + 0x95b084c0, + 0x95c084d0, + 0x90307810, + 0x78209050, + 0x90609040, + 0xcd90b235, + 0x70009170, + 0xb112a235, + 0xa0d27100, + 0xba3cb112, + 0x8b5481b0, + 0x31843924, + 0x91b40004, + 0x669bc0d0, + 0x72917391, + 0x72066695, + 0x72047202, + 0x73067305, + 0x86306076, + 0x3151c801, + 0x96300410, + 0x9a007000, + 0x220089f0, + 0xb9e0469c, + 0x00007000}; PATCH_FUN_SPEC void rf_patch_mce_iqdump(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_tof.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_tof.h index fe0ffaa..d82d3ba 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_tof.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_tof.h @@ -1,572 +1,571 @@ /****************************************************************************** -* Filename: rf_patch_mce_tof.h -* Revised: $Date: 2019-01-31 15:04:59 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18843 $ -* -* Description: RF core MCE patch for time of flight 2Mbps PHY for CC13x2 and CC26x2 -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_mce_tof.h + * Revised: $Date: 2019-01-31 15:04:59 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18843 $ + * + * Description: RF core MCE patch for time of flight 2Mbps PHY for CC13x2 and CC26x2 + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_MCE_TOF_H #define _RF_PATCH_MCE_TOF_H -#include #include "../inc/hw_types.h" +#include #ifndef MCE_PATCH_TYPE - #define MCE_PATCH_TYPE static const uint32_t +#define MCE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_MCERAM_BASE - #define RFC_MCERAM_BASE 0x21008000 +#define RFC_MCERAM_BASE 0x21008000 #endif #ifndef MCE_PATCH_MODE - #define MCE_PATCH_MODE 0 +#define MCE_PATCH_MODE 0 #endif MCE_PATCH_TYPE patchTofMce[506] = -{ - 0x0003605b, - 0x00f1000f, - 0x00000000, - 0x000c8000, - 0x00000000, - 0x0c650000, - 0x80000000, - 0x00800010, - 0x00000000, - 0x0594091e, - 0x00000350, - 0x7c200000, - 0x000000c2, - 0x34340013, - 0x0003005a, - 0x00000032, - 0xfe6b2840, - 0xdeade8ca, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x07d00011, - 0x6fdd2fea, - 0x0fb00ff0, - 0xf80f0003, - 0x007f7f30, - 0x3434001f, - 0x8010005a, - 0x01900000, - 0x40000800, - 0xc0300c65, - 0x722367ee, - 0xa35d7263, - 0x73057303, - 0x73047203, - 0x72047306, - 0x72917391, - 0x8001c7c0, - 0x90010001, - 0x08019010, - 0x720d9001, - 0x720f720e, - 0xb0d07210, - 0xc0407100, - 0xa0d067ee, - 0x721bb110, - 0x10208162, - 0x06703952, - 0x16300020, - 0x14011101, - 0x60936c01, - 0x60c260a4, - 0x6219617b, - 0x60936093, - 0x60936093, - 0x60c260a4, - 0x6219617b, - 0x60936093, - 0x60976093, - 0x12206095, - 0xc050609a, - 0x121267ee, - 0x73117223, - 0x73137312, - 0x81b17314, - 0x91b20012, - 0x6073b070, - 0xc2b2c011, - 0x1820c710, - 0x6e236f13, - 0x16121611, - 0x7d7068a8, - 0xc0229990, - 0x39818161, - 0xd0601812, - 0x67ee9a12, - 0x40971e01, - 0x99907d80, - 0x93807d50, - 0x93307d60, - 0x93007d90, - 0x6097b360, - 0xc07067e5, - 0x677e67ee, - 0x91f0c070, - 0x670bb750, - 0xb233b914, - 0xa750672d, - 0x95b488d4, - 0x95c488e4, - 0x95948ca4, - 0x95a487c4, - 0x2a007cb0, - 0x88d49060, - 0x88e495d4, - 0xc0f495e4, - 0x91449134, - 0x22008c80, - 0xb0f040e5, - 0xb0f6b130, - 0xb0d5b0d0, - 0xb110b136, - 0xb140b100, - 0x73137314, - 0x2a007cb0, - 0xc0f19060, - 0x40f51e0e, - 0x99311611, - 0xc037b912, - 0xb115b041, - 0xa910c031, - 0xb0737100, - 0xba3eb910, - 0x22008090, - 0x80b24574, - 0x45182262, - 0x220280c2, - 0xb061410b, - 0x2250b140, - 0x824040f9, - 0x45152200, - 0x40f9220f, - 0x679e100f, - 0x100f60f9, - 0x60f967b4, - 0xb234a913, - 0x93acba39, - 0xa0d58462, - 0xb0d1720f, - 0x7100b111, - 0xb1119937, - 0xb35d7100, - 0x9930c3f0, - 0xc0d0b074, - 0x894193f0, - 0x67bf9791, - 0x14018941, - 0x7100b111, - 0xba3aba3b, - 0xc210b078, - 0xa2329930, - 0xb111b235, - 0xa35d7100, - 0x7291b06e, - 0x8af2a0d1, - 0x3d823182, - 0x67eec080, - 0x8c528c33, - 0x8c441423, - 0x14248c62, - 0x06f28b32, - 0x31418b21, - 0x97a20012, - 0x0424cff2, - 0x31433143, - 0x97b40034, - 0x6957c8f0, - 0xb130b235, - 0xb136a0f0, - 0xb140a0f6, - 0xb914a100, - 0xa7507291, - 0xa002a003, - 0x9010c7c0, - 0x72047203, - 0x73067305, - 0xa23267e5, - 0x8242b235, - 0x456b1e02, - 0xc0907223, - 0x609767ee, - 0xa232b235, - 0xd0a08942, - 0x67ee9a12, - 0x67e56159, - 0x677ec00f, - 0x91f0c070, - 0xc0b0670b, - 0xb01367ee, - 0x22008c80, - 0xb0f04189, - 0xb0f6b130, - 0xb0d5b0d0, - 0xb136b111, - 0x72917313, - 0xc0e1b912, - 0x41951e0e, - 0x99311611, - 0xb041c037, - 0xc031b232, - 0xb115a910, - 0xb0737100, - 0xba3eb910, - 0x22008090, - 0x80b24614, - 0x45b32262, - 0x41992250, - 0x22008240, - 0x220f45b0, - 0x100f4199, - 0x6199679e, - 0x67b4100f, - 0xb9136199, - 0xba39b234, - 0xa0d593ac, - 0x7313720f, - 0x73147210, - 0x264081b0, - 0xb0d191b0, - 0x7100b111, - 0x9937b041, - 0x7100b111, - 0xc3f0b35d, - 0xb0749930, - 0x93f0c0d0, - 0x7100b111, - 0xc210b078, - 0xa2329930, - 0x7100b111, - 0xb06ea35d, - 0xa0d1a910, - 0x899167bf, - 0x81a01401, - 0x99311401, - 0xb0d6b116, - 0xb1167100, - 0x8090a0d6, - 0x46142200, - 0x88d4b012, - 0x88e495b4, - 0x8ca495c4, - 0x87c49594, - 0x729195a4, - 0x2a208230, - 0x92302630, - 0xc070672d, - 0x8af287b1, - 0x3d823182, - 0x69fbc310, - 0xb111b064, - 0xa0f6b136, - 0xa0f0b130, - 0x8242b235, - 0x46021e02, - 0x7291b914, - 0xa002a003, - 0x9010c7c0, - 0x72047203, - 0x73067305, - 0x67eec0c0, - 0x609767e5, - 0x67eec0d0, - 0x7291b235, - 0x677e6202, - 0xc070c00b, - 0x670b91f0, - 0x67eec0e0, - 0x727ab914, - 0xb0137226, - 0x73147313, - 0x8c8072c9, - 0x422d2200, - 0xb130b0f0, - 0x85b06231, - 0x95d085c1, - 0xb10095e1, - 0xb110b140, - 0xb0f6b064, - 0xb0d5b0d0, - 0x7313b136, - 0xb041b061, - 0x42411e1b, - 0xb9127291, - 0xc13772c9, - 0x1e0ec070, - 0x16104247, - 0x9930c0b7, - 0xb115b232, - 0xa910c031, - 0xb0737100, - 0xba3eb910, - 0x22008090, - 0x80b24705, - 0x46682262, - 0x220280c2, - 0xb061425b, - 0x2250b140, - 0x82404249, - 0x46652200, - 0x4249220f, - 0x679e100f, - 0x100f6249, - 0x624967b4, - 0x1e1bb234, - 0xa9154285, - 0xb913b916, - 0x8b33ba3b, - 0x8b2406f3, - 0x00433144, - 0x8c3397a3, - 0x14038c50, - 0x8c448c60, - 0x31431404, - 0x00343143, - 0x81b097b4, - 0x91b02650, - 0x67eec0f0, - 0xa91362bf, - 0x264081b0, - 0x993791b0, - 0x93acba39, - 0x720fa0d5, - 0xb111b0d1, - 0x7100b111, - 0xc3e0b35d, - 0xb0749930, - 0x93f0c0d0, - 0x97918941, - 0xb11167bf, - 0xb0787100, - 0x9930c210, - 0xb235a232, - 0x7100b111, - 0xb06ea35d, - 0xa0d17291, - 0x31828af2, - 0xba3b3d82, - 0x06f38b33, - 0x31448b24, - 0x92630043, - 0x8c508c33, - 0x8c601403, - 0x14048c44, - 0x31433143, - 0x97b40034, - 0x6abdc8f0, - 0xbc9062e3, - 0x95b488d4, - 0x95c488e4, - 0x95948ca4, - 0x95a487c4, - 0x85b0c01b, - 0x95d085c1, - 0x731195e1, - 0x73137312, - 0xb1007314, - 0xb0f6b140, - 0xb110b136, - 0xa232b064, - 0x22628242, - 0x722342d7, - 0xb115b064, - 0xc410b232, - 0x679e6ae0, - 0xb2356249, - 0xa100b140, - 0xa0f6b136, - 0x7291b914, - 0xa003a750, - 0xc7c0a002, - 0x72039010, - 0x73057204, - 0x73117306, - 0x73137312, - 0x720f7314, - 0x7210720d, - 0x7223720e, - 0xb235a232, - 0x1e028242, - 0x722346fc, - 0x67eec100, - 0xc1106097, - 0xb23567ee, - 0x8942a232, - 0x824262e4, - 0x430b2212, - 0xb016b006, - 0xb002b012, - 0xb014b004, - 0x90307ca0, - 0x7cb09050, - 0x90609040, - 0x73127311, - 0x73147313, - 0x720e720d, - 0x7210720f, - 0xb0e1b121, - 0xb0727100, - 0xd680a0e1, - 0x679e6b28, - 0x93f0c090, - 0xbc907000, - 0x9930c040, - 0xb910b911, - 0xb111b0d1, - 0x72917100, - 0xb111a0d1, - 0x9635722c, - 0xc0f38c82, - 0xb013b003, - 0x92c08170, - 0x96408190, - 0xb120b0e0, - 0x22027100, - 0x85b04750, - 0x92c39640, - 0x7100b120, - 0x964085c0, - 0x7100b120, - 0x96408590, - 0xb12092c3, - 0x85a07100, - 0xb1209640, - 0x8cb07100, - 0x0410cff1, - 0xb1209640, - 0x96367100, - 0x9930c040, - 0xb910b911, - 0xb111b0d1, - 0xb120a0e0, - 0x72917100, - 0xb111a0d1, - 0x1e108750, - 0xb2354371, - 0xa9156378, - 0xb913b916, - 0x2a308230, - 0x92302620, - 0x6b79c090, - 0xc120ac90, - 0x700067ee, - 0x721b7223, - 0x92c0c0f0, - 0xc1f1722f, - 0xc01592d1, - 0x7c977c86, - 0x8c807ccc, - 0x43912200, - 0x94407cf0, - 0x94607d10, - 0x7d206393, - 0xac909440, - 0xc1009636, - 0x816e91e0, - 0xc01d398e, - 0x439d1e0e, - 0x7000c03d, - 0x726a7269, - 0xb0537ce2, - 0xc76093a2, - 0x73a36ba4, - 0x96908a40, - 0x96a18a51, - 0x7cd093a6, - 0x8a4393a0, - 0x31338a54, - 0x31343d33, - 0x70003d34, - 0x8a439a31, - 0x31338a54, - 0x31343d63, - 0x96933d64, - 0xb05396a4, - 0x1e0e7000, - 0x8c3143d6, - 0x18108c40, - 0xc0024fd0, - 0x161110d1, - 0x16201812, - 0x1c203d20, - 0x10204fe4, - 0x63e41610, - 0x3d201620, - 0x4be41cd0, - 0x63e410d0, - 0xc082c000, - 0x8c448c33, - 0x1c241834, - 0x14424fe0, - 0x63e44be2, - 0x63e410d0, - 0x18d0c000, - 0x720d7000, - 0x720f720e, - 0x73117210, - 0x73137312, - 0x70007314, - 0x89f09a00, - 0x47ef2200, - 0x7000b9e0 -}; + { + 0x0003605b, + 0x00f1000f, + 0x00000000, + 0x000c8000, + 0x00000000, + 0x0c650000, + 0x80000000, + 0x00800010, + 0x00000000, + 0x0594091e, + 0x00000350, + 0x7c200000, + 0x000000c2, + 0x34340013, + 0x0003005a, + 0x00000032, + 0xfe6b2840, + 0xdeade8ca, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x07d00011, + 0x6fdd2fea, + 0x0fb00ff0, + 0xf80f0003, + 0x007f7f30, + 0x3434001f, + 0x8010005a, + 0x01900000, + 0x40000800, + 0xc0300c65, + 0x722367ee, + 0xa35d7263, + 0x73057303, + 0x73047203, + 0x72047306, + 0x72917391, + 0x8001c7c0, + 0x90010001, + 0x08019010, + 0x720d9001, + 0x720f720e, + 0xb0d07210, + 0xc0407100, + 0xa0d067ee, + 0x721bb110, + 0x10208162, + 0x06703952, + 0x16300020, + 0x14011101, + 0x60936c01, + 0x60c260a4, + 0x6219617b, + 0x60936093, + 0x60936093, + 0x60c260a4, + 0x6219617b, + 0x60936093, + 0x60976093, + 0x12206095, + 0xc050609a, + 0x121267ee, + 0x73117223, + 0x73137312, + 0x81b17314, + 0x91b20012, + 0x6073b070, + 0xc2b2c011, + 0x1820c710, + 0x6e236f13, + 0x16121611, + 0x7d7068a8, + 0xc0229990, + 0x39818161, + 0xd0601812, + 0x67ee9a12, + 0x40971e01, + 0x99907d80, + 0x93807d50, + 0x93307d60, + 0x93007d90, + 0x6097b360, + 0xc07067e5, + 0x677e67ee, + 0x91f0c070, + 0x670bb750, + 0xb233b914, + 0xa750672d, + 0x95b488d4, + 0x95c488e4, + 0x95948ca4, + 0x95a487c4, + 0x2a007cb0, + 0x88d49060, + 0x88e495d4, + 0xc0f495e4, + 0x91449134, + 0x22008c80, + 0xb0f040e5, + 0xb0f6b130, + 0xb0d5b0d0, + 0xb110b136, + 0xb140b100, + 0x73137314, + 0x2a007cb0, + 0xc0f19060, + 0x40f51e0e, + 0x99311611, + 0xc037b912, + 0xb115b041, + 0xa910c031, + 0xb0737100, + 0xba3eb910, + 0x22008090, + 0x80b24574, + 0x45182262, + 0x220280c2, + 0xb061410b, + 0x2250b140, + 0x824040f9, + 0x45152200, + 0x40f9220f, + 0x679e100f, + 0x100f60f9, + 0x60f967b4, + 0xb234a913, + 0x93acba39, + 0xa0d58462, + 0xb0d1720f, + 0x7100b111, + 0xb1119937, + 0xb35d7100, + 0x9930c3f0, + 0xc0d0b074, + 0x894193f0, + 0x67bf9791, + 0x14018941, + 0x7100b111, + 0xba3aba3b, + 0xc210b078, + 0xa2329930, + 0xb111b235, + 0xa35d7100, + 0x7291b06e, + 0x8af2a0d1, + 0x3d823182, + 0x67eec080, + 0x8c528c33, + 0x8c441423, + 0x14248c62, + 0x06f28b32, + 0x31418b21, + 0x97a20012, + 0x0424cff2, + 0x31433143, + 0x97b40034, + 0x6957c8f0, + 0xb130b235, + 0xb136a0f0, + 0xb140a0f6, + 0xb914a100, + 0xa7507291, + 0xa002a003, + 0x9010c7c0, + 0x72047203, + 0x73067305, + 0xa23267e5, + 0x8242b235, + 0x456b1e02, + 0xc0907223, + 0x609767ee, + 0xa232b235, + 0xd0a08942, + 0x67ee9a12, + 0x67e56159, + 0x677ec00f, + 0x91f0c070, + 0xc0b0670b, + 0xb01367ee, + 0x22008c80, + 0xb0f04189, + 0xb0f6b130, + 0xb0d5b0d0, + 0xb136b111, + 0x72917313, + 0xc0e1b912, + 0x41951e0e, + 0x99311611, + 0xb041c037, + 0xc031b232, + 0xb115a910, + 0xb0737100, + 0xba3eb910, + 0x22008090, + 0x80b24614, + 0x45b32262, + 0x41992250, + 0x22008240, + 0x220f45b0, + 0x100f4199, + 0x6199679e, + 0x67b4100f, + 0xb9136199, + 0xba39b234, + 0xa0d593ac, + 0x7313720f, + 0x73147210, + 0x264081b0, + 0xb0d191b0, + 0x7100b111, + 0x9937b041, + 0x7100b111, + 0xc3f0b35d, + 0xb0749930, + 0x93f0c0d0, + 0x7100b111, + 0xc210b078, + 0xa2329930, + 0x7100b111, + 0xb06ea35d, + 0xa0d1a910, + 0x899167bf, + 0x81a01401, + 0x99311401, + 0xb0d6b116, + 0xb1167100, + 0x8090a0d6, + 0x46142200, + 0x88d4b012, + 0x88e495b4, + 0x8ca495c4, + 0x87c49594, + 0x729195a4, + 0x2a208230, + 0x92302630, + 0xc070672d, + 0x8af287b1, + 0x3d823182, + 0x69fbc310, + 0xb111b064, + 0xa0f6b136, + 0xa0f0b130, + 0x8242b235, + 0x46021e02, + 0x7291b914, + 0xa002a003, + 0x9010c7c0, + 0x72047203, + 0x73067305, + 0x67eec0c0, + 0x609767e5, + 0x67eec0d0, + 0x7291b235, + 0x677e6202, + 0xc070c00b, + 0x670b91f0, + 0x67eec0e0, + 0x727ab914, + 0xb0137226, + 0x73147313, + 0x8c8072c9, + 0x422d2200, + 0xb130b0f0, + 0x85b06231, + 0x95d085c1, + 0xb10095e1, + 0xb110b140, + 0xb0f6b064, + 0xb0d5b0d0, + 0x7313b136, + 0xb041b061, + 0x42411e1b, + 0xb9127291, + 0xc13772c9, + 0x1e0ec070, + 0x16104247, + 0x9930c0b7, + 0xb115b232, + 0xa910c031, + 0xb0737100, + 0xba3eb910, + 0x22008090, + 0x80b24705, + 0x46682262, + 0x220280c2, + 0xb061425b, + 0x2250b140, + 0x82404249, + 0x46652200, + 0x4249220f, + 0x679e100f, + 0x100f6249, + 0x624967b4, + 0x1e1bb234, + 0xa9154285, + 0xb913b916, + 0x8b33ba3b, + 0x8b2406f3, + 0x00433144, + 0x8c3397a3, + 0x14038c50, + 0x8c448c60, + 0x31431404, + 0x00343143, + 0x81b097b4, + 0x91b02650, + 0x67eec0f0, + 0xa91362bf, + 0x264081b0, + 0x993791b0, + 0x93acba39, + 0x720fa0d5, + 0xb111b0d1, + 0x7100b111, + 0xc3e0b35d, + 0xb0749930, + 0x93f0c0d0, + 0x97918941, + 0xb11167bf, + 0xb0787100, + 0x9930c210, + 0xb235a232, + 0x7100b111, + 0xb06ea35d, + 0xa0d17291, + 0x31828af2, + 0xba3b3d82, + 0x06f38b33, + 0x31448b24, + 0x92630043, + 0x8c508c33, + 0x8c601403, + 0x14048c44, + 0x31433143, + 0x97b40034, + 0x6abdc8f0, + 0xbc9062e3, + 0x95b488d4, + 0x95c488e4, + 0x95948ca4, + 0x95a487c4, + 0x85b0c01b, + 0x95d085c1, + 0x731195e1, + 0x73137312, + 0xb1007314, + 0xb0f6b140, + 0xb110b136, + 0xa232b064, + 0x22628242, + 0x722342d7, + 0xb115b064, + 0xc410b232, + 0x679e6ae0, + 0xb2356249, + 0xa100b140, + 0xa0f6b136, + 0x7291b914, + 0xa003a750, + 0xc7c0a002, + 0x72039010, + 0x73057204, + 0x73117306, + 0x73137312, + 0x720f7314, + 0x7210720d, + 0x7223720e, + 0xb235a232, + 0x1e028242, + 0x722346fc, + 0x67eec100, + 0xc1106097, + 0xb23567ee, + 0x8942a232, + 0x824262e4, + 0x430b2212, + 0xb016b006, + 0xb002b012, + 0xb014b004, + 0x90307ca0, + 0x7cb09050, + 0x90609040, + 0x73127311, + 0x73147313, + 0x720e720d, + 0x7210720f, + 0xb0e1b121, + 0xb0727100, + 0xd680a0e1, + 0x679e6b28, + 0x93f0c090, + 0xbc907000, + 0x9930c040, + 0xb910b911, + 0xb111b0d1, + 0x72917100, + 0xb111a0d1, + 0x9635722c, + 0xc0f38c82, + 0xb013b003, + 0x92c08170, + 0x96408190, + 0xb120b0e0, + 0x22027100, + 0x85b04750, + 0x92c39640, + 0x7100b120, + 0x964085c0, + 0x7100b120, + 0x96408590, + 0xb12092c3, + 0x85a07100, + 0xb1209640, + 0x8cb07100, + 0x0410cff1, + 0xb1209640, + 0x96367100, + 0x9930c040, + 0xb910b911, + 0xb111b0d1, + 0xb120a0e0, + 0x72917100, + 0xb111a0d1, + 0x1e108750, + 0xb2354371, + 0xa9156378, + 0xb913b916, + 0x2a308230, + 0x92302620, + 0x6b79c090, + 0xc120ac90, + 0x700067ee, + 0x721b7223, + 0x92c0c0f0, + 0xc1f1722f, + 0xc01592d1, + 0x7c977c86, + 0x8c807ccc, + 0x43912200, + 0x94407cf0, + 0x94607d10, + 0x7d206393, + 0xac909440, + 0xc1009636, + 0x816e91e0, + 0xc01d398e, + 0x439d1e0e, + 0x7000c03d, + 0x726a7269, + 0xb0537ce2, + 0xc76093a2, + 0x73a36ba4, + 0x96908a40, + 0x96a18a51, + 0x7cd093a6, + 0x8a4393a0, + 0x31338a54, + 0x31343d33, + 0x70003d34, + 0x8a439a31, + 0x31338a54, + 0x31343d63, + 0x96933d64, + 0xb05396a4, + 0x1e0e7000, + 0x8c3143d6, + 0x18108c40, + 0xc0024fd0, + 0x161110d1, + 0x16201812, + 0x1c203d20, + 0x10204fe4, + 0x63e41610, + 0x3d201620, + 0x4be41cd0, + 0x63e410d0, + 0xc082c000, + 0x8c448c33, + 0x1c241834, + 0x14424fe0, + 0x63e44be2, + 0x63e410d0, + 0x18d0c000, + 0x720d7000, + 0x720f720e, + 0x73117210, + 0x73137312, + 0x70007314, + 0x89f09a00, + 0x47ef2200, + 0x7000b9e0}; PATCH_FUN_SPEC void rf_patch_mce_tof(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_tof.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_tof.h index 04efae0..f0d6000 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_tof.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_tof.h @@ -1,528 +1,526 @@ /****************************************************************************** -* Filename: rf_patch_rfe_tof.h -* Revised: $Date: 2019-01-31 15:04:59 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18843 $ -* -* Description: RF core RFE patch for time of flight 2Mbps PHY for CC13x2 and CC26x2 -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - + * Filename: rf_patch_rfe_tof.h + * Revised: $Date: 2019-01-31 15:04:59 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18843 $ + * + * Description: RF core RFE patch for time of flight 2Mbps PHY for CC13x2 and CC26x2 + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_RFE_TOF_H #define _RF_PATCH_RFE_TOF_H -#include #include "../inc/hw_types.h" +#include #ifndef RFE_PATCH_TYPE - #define RFE_PATCH_TYPE static const uint32_t +#define RFE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_RFERAM_BASE - #define RFC_RFERAM_BASE 0x2100C000 +#define RFC_RFERAM_BASE 0x2100C000 #endif #ifndef RFE_PATCH_MODE - #define RFE_PATCH_MODE 0 +#define RFE_PATCH_MODE 0 #endif RFE_PATCH_TYPE patchTofRfe[461] = -{ - 0x00006194, - 0x004535aa, - 0x0421a355, - 0x1f40004c, - 0x0000003f, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x43cf41cf, - 0x4fcf47cf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x6fcf7fcf, - 0x4fcf5fcf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x00000000, - 0x00000000, - 0x9100c050, - 0xc0707000, - 0x70009100, - 0x00213182, - 0xb1109131, - 0x81017000, - 0xa100b101, - 0x91323182, - 0x9101b110, - 0x81411011, - 0x40772241, - 0x700006f1, - 0x9150c050, - 0xc0707000, - 0x70009150, - 0x00213182, - 0xb1609181, - 0x10257000, - 0x9100c050, - 0xc140c3f4, - 0x6f031420, - 0x04411031, - 0x22f082a0, - 0x26514094, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0x04411031, - 0x3182c082, - 0x91310021, - 0x3963b110, - 0xc0a21031, - 0x00213182, - 0xb1109131, - 0x31151050, - 0x92551405, - 0x64677000, - 0x1031c2b2, - 0x31610631, - 0x646a02c1, - 0x1031c112, - 0x06713921, - 0x02e13151, - 0x7000646a, - 0x82b16464, - 0x39813181, - 0x646ac0e2, - 0xc1116467, - 0x646ac122, - 0x68c7c470, - 0xc0c2c111, - 0x64e0646a, - 0x700064f3, - 0x82b1647c, - 0x39813181, - 0x6482c182, - 0xc111647f, - 0x6482c0a2, - 0x68d9c470, - 0xc162c331, - 0x64e06482, - 0x700064f3, - 0xb054b050, - 0x80407100, - 0x44ed2240, - 0x40e02200, - 0x8081b060, - 0x44e01e11, - 0xa0547000, - 0x80f0b064, - 0x40e02200, - 0x12407000, - 0xb03290b0, - 0x395382a3, - 0x64ad3953, - 0x68fbc2f0, - 0xc1f18080, - 0xc1510410, - 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0x80f191b5, + 0x46ae2241, + 0x80416b79, + 0x46e12201, + 0x92148204, + 0x1cc58225, + 0x18954ad7, + 0x80f091b5, + 0x43852240, + 0x933062ae, + 0x22008320, + 0xb3104794, + 0x00007000}; PATCH_FUN_SPEC void rf_patch_rfe_tof(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/adi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/adi.h index 03de7e2..feab0b1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/adi.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/adi.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: adi.h -* Revised: 2016-11-17 16:39:28 +0100 (Thu, 17 Nov 2016) -* Revision: 47706 -* -* Description: Defines and prototypes for the ADI master interface. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: adi.h + * Revised: 2016-11-17 16:39:28 +0100 (Thu, 17 Nov 2016) + * Revision: 47706 + * + * Description: Defines and prototypes for the ADI master interface. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,36 +55,34 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include +#include "../inc/hw_adi.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" #include "../inc/hw_types.h" #include "../inc/hw_uart.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_adi.h" -#include "debug.h" #include "ddi.h" +#include "debug.h" +#include +#include //***************************************************************************** // // Number of registers in the ADI slave // //***************************************************************************** -#define ADI_SLAVE_REGS 16 - +#define ADI_SLAVE_REGS 16 //***************************************************************************** // // Defines that is used to control the ADI slave and master // //***************************************************************************** -#define ADI_PROTECT 0x00000080 -#define ADI_ACK 0x00000001 -#define ADI_SYNC 0x00000000 +#define ADI_PROTECT 0x00000080 +#define ADI_ACK 0x00000001 +#define ADI_SYNC 0x00000000 //***************************************************************************** // @@ -114,10 +112,6 @@ ADIBaseValid(uint32_t ui32Base) } #endif - - - - //***************************************************************************** // //! \brief Write an 8 bit value to a register in an ADI slave. @@ -883,8 +877,8 @@ ADI16SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, // "bus arbitration" issue. // //***************************************************************************** -void SafeHapiVoid( FPTR_VOID_VOID_T fPtr ); -void SafeHapiAuxAdiSelect( FPTR_VOID_UINT8_T fPtr, uint8_t ut8Signal ); +void SafeHapiVoid(FPTR_VOID_VOID_T fPtr); +void SafeHapiAuxAdiSelect(FPTR_VOID_UINT8_T fPtr, uint8_t ut8Signal); //***************************************************************************** // diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/adi_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/adi_doc.h index 5543464..cb66827 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/adi_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/adi_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: adi_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: adi_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup adi_api //! @{ //! \section sec_adi Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aes.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aes.h index 2f21964..59b5085 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aes.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aes.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aes.h -* Revised: 2019-01-25 14:45:16 +0100 (Fri, 25 Jan 2019) -* Revision: 54287 -* -* Description: AES header file. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aes.h + * Revised: 2019-01-25 14:45:16 +0100 (Fri, 25 Jan 2019) + * Revision: 54287 + * + * Description: AES header file. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,20 +55,19 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_crypto.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" #include #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_crypto.h" -#include "debug.h" -#include "interrupt.h" -#include "cpu.h" //***************************************************************************** // @@ -84,18 +83,17 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AESStartDMAOperation NOROM_AESStartDMAOperation -#define AESSetInitializationVector NOROM_AESSetInitializationVector +#define AESStartDMAOperation NOROM_AESStartDMAOperation +#define AESSetInitializationVector NOROM_AESSetInitializationVector #define AESWriteCCMInitializationVector NOROM_AESWriteCCMInitializationVector -#define AESReadTag NOROM_AESReadTag -#define AESVerifyTag NOROM_AESVerifyTag -#define AESWriteToKeyStore NOROM_AESWriteToKeyStore -#define AESReadFromKeyStore NOROM_AESReadFromKeyStore -#define AESWaitForIRQFlags NOROM_AESWaitForIRQFlags -#define AESConfigureCCMCtrl NOROM_AESConfigureCCMCtrl +#define AESReadTag NOROM_AESReadTag +#define AESVerifyTag NOROM_AESVerifyTag +#define AESWriteToKeyStore NOROM_AESWriteToKeyStore +#define AESReadFromKeyStore NOROM_AESReadFromKeyStore +#define AESWaitForIRQFlags NOROM_AESWaitForIRQFlags +#define AESConfigureCCMCtrl NOROM_AESConfigureCCMCtrl #endif - //***************************************************************************** // // Values that can be passed to AESIntEnable, AESIntDisable, and AESIntClear @@ -104,12 +102,11 @@ extern "C" // function to see if it supports other interrupt status flags. // //***************************************************************************** -#define AES_DMA_IN_DONE CRYPTO_IRQEN_DMA_IN_DONE_M -#define AES_RESULT_RDY CRYPTO_IRQEN_RESULT_AVAIL_M -#define AES_DMA_BUS_ERR CRYPTO_IRQCLR_DMA_BUS_ERR_M -#define AES_KEY_ST_WR_ERR CRYPTO_IRQCLR_KEY_ST_WR_ERR_M -#define AES_KEY_ST_RD_ERR CRYPTO_IRQCLR_KEY_ST_RD_ERR_M - +#define AES_DMA_IN_DONE CRYPTO_IRQEN_DMA_IN_DONE_M +#define AES_RESULT_RDY CRYPTO_IRQEN_RESULT_AVAIL_M +#define AES_DMA_BUS_ERR CRYPTO_IRQCLR_DMA_BUS_ERR_M +#define AES_KEY_ST_WR_ERR CRYPTO_IRQCLR_KEY_ST_WR_ERR_M +#define AES_KEY_ST_RD_ERR CRYPTO_IRQCLR_KEY_ST_RD_ERR_M //***************************************************************************** // @@ -118,33 +115,32 @@ extern "C" //***************************************************************************** // AES module return codes -#define AES_SUCCESS 0 -#define AES_KEYSTORE_ERROR 1 -#define AES_KEYSTORE_AREA_INVALID 2 -#define AES_DMA_BUSY 3 -#define AES_DMA_ERROR 4 -#define AES_TAG_NOT_READY 5 -#define AES_TAG_VERIFICATION_FAILED 6 +#define AES_SUCCESS 0 +#define AES_KEYSTORE_ERROR 1 +#define AES_KEYSTORE_AREA_INVALID 2 +#define AES_DMA_BUSY 3 +#define AES_DMA_ERROR 4 +#define AES_TAG_NOT_READY 5 +#define AES_TAG_VERIFICATION_FAILED 6 // Key store module defines -#define AES_IV_LENGTH_BYTES 16 -#define AES_TAG_LENGTH_BYTES 16 -#define AES_128_KEY_LENGTH_BYTES (128 / 8) -#define AES_192_KEY_LENGTH_BYTES (192 / 8) -#define AES_256_KEY_LENGTH_BYTES (256 / 8) +#define AES_IV_LENGTH_BYTES 16 +#define AES_TAG_LENGTH_BYTES 16 +#define AES_128_KEY_LENGTH_BYTES (128 / 8) +#define AES_192_KEY_LENGTH_BYTES (192 / 8) +#define AES_256_KEY_LENGTH_BYTES (256 / 8) -#define AES_BLOCK_SIZE 16 +#define AES_BLOCK_SIZE 16 // DMA status codes -#define AES_DMA_CHANNEL0_ACTIVE CRYPTO_DMASTAT_CH0_ACT_M -#define AES_DMA_CHANNEL1_ACTIVE CRYPTO_DMASTAT_CH1_ACT_M -#define AES_DMA_PORT_ERROR CRYPTO_DMASTAT_PORT_ERR_M +#define AES_DMA_CHANNEL0_ACTIVE CRYPTO_DMASTAT_CH0_ACT_M +#define AES_DMA_CHANNEL1_ACTIVE CRYPTO_DMASTAT_CH1_ACT_M +#define AES_DMA_PORT_ERROR CRYPTO_DMASTAT_PORT_ERR_M // Crypto module operation types -#define AES_ALGSEL_AES CRYPTO_ALGSEL_AES_M -#define AES_ALGSEL_KEY_STORE CRYPTO_ALGSEL_KEY_STORE_M -#define AES_ALGSEL_TAG CRYPTO_ALGSEL_TAG_M - +#define AES_ALGSEL_AES CRYPTO_ALGSEL_AES_M +#define AES_ALGSEL_KEY_STORE CRYPTO_ALGSEL_KEY_STORE_M +#define AES_ALGSEL_TAG CRYPTO_ALGSEL_TAG_M //***************************************************************************** // @@ -153,24 +149,24 @@ extern "C" // may be odd. Do not attempt to write a 256-bit key to AES_KEY_AREA_7. // //***************************************************************************** -#define AES_KEY_AREA_0 0 -#define AES_KEY_AREA_1 1 -#define AES_KEY_AREA_2 2 -#define AES_KEY_AREA_3 3 -#define AES_KEY_AREA_4 4 -#define AES_KEY_AREA_5 5 -#define AES_KEY_AREA_6 6 -#define AES_KEY_AREA_7 7 +#define AES_KEY_AREA_0 0 +#define AES_KEY_AREA_1 1 +#define AES_KEY_AREA_2 2 +#define AES_KEY_AREA_3 3 +#define AES_KEY_AREA_4 4 +#define AES_KEY_AREA_5 5 +#define AES_KEY_AREA_6 6 +#define AES_KEY_AREA_7 7 //***************************************************************************** // // Defines for the AES-CTR mode counter width // //***************************************************************************** -#define AES_CTR_WIDTH_32 0x0 -#define AES_CTR_WIDTH_64 0x1 -#define AES_CTR_WIDTH_96 0x2 -#define AES_CTR_WIDTH_128 0x3 +#define AES_CTR_WIDTH_32 0x0 +#define AES_CTR_WIDTH_64 0x1 +#define AES_CTR_WIDTH_96 0x2 +#define AES_CTR_WIDTH_128 0x3 //***************************************************************************** // @@ -213,7 +209,7 @@ extern "C" //! \return None // //***************************************************************************** -extern void AESStartDMAOperation(const uint8_t* channel0Addr, uint32_t channel0Length, uint8_t* channel1Addr, uint32_t channel1Length); +extern void AESStartDMAOperation(const uint8_t* channel0Addr, uint32_t channel0Length, uint8_t* channel1Addr, uint32_t channel1Length); //***************************************************************************** // @@ -406,7 +402,6 @@ extern uint32_t AESWriteToKeyStore(const uint8_t* aesKey, uint32_t aesKeyLength, //***************************************************************************** extern uint32_t AESReadFromKeyStore(uint32_t keyStoreArea); - //***************************************************************************** // //! \brief Poll the interrupt status register and clear when done. @@ -786,40 +781,40 @@ __STATIC_INLINE void AESIntUnregister(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AESStartDMAOperation -#undef AESStartDMAOperation -#define AESStartDMAOperation ROM_AESStartDMAOperation +#undef AESStartDMAOperation +#define AESStartDMAOperation ROM_AESStartDMAOperation #endif #ifdef ROM_AESSetInitializationVector -#undef AESSetInitializationVector -#define AESSetInitializationVector ROM_AESSetInitializationVector +#undef AESSetInitializationVector +#define AESSetInitializationVector ROM_AESSetInitializationVector #endif #ifdef ROM_AESWriteCCMInitializationVector -#undef AESWriteCCMInitializationVector +#undef AESWriteCCMInitializationVector #define AESWriteCCMInitializationVector ROM_AESWriteCCMInitializationVector #endif #ifdef ROM_AESReadTag -#undef AESReadTag -#define AESReadTag ROM_AESReadTag +#undef AESReadTag +#define AESReadTag ROM_AESReadTag #endif #ifdef ROM_AESVerifyTag -#undef AESVerifyTag -#define AESVerifyTag ROM_AESVerifyTag +#undef AESVerifyTag +#define AESVerifyTag ROM_AESVerifyTag #endif #ifdef ROM_AESWriteToKeyStore -#undef AESWriteToKeyStore -#define AESWriteToKeyStore ROM_AESWriteToKeyStore +#undef AESWriteToKeyStore +#define AESWriteToKeyStore ROM_AESWriteToKeyStore #endif #ifdef ROM_AESReadFromKeyStore -#undef AESReadFromKeyStore -#define AESReadFromKeyStore ROM_AESReadFromKeyStore +#undef AESReadFromKeyStore +#define AESReadFromKeyStore ROM_AESReadFromKeyStore #endif #ifdef ROM_AESWaitForIRQFlags -#undef AESWaitForIRQFlags -#define AESWaitForIRQFlags ROM_AESWaitForIRQFlags +#undef AESWaitForIRQFlags +#define AESWaitForIRQFlags ROM_AESWaitForIRQFlags #endif #ifdef ROM_AESConfigureCCMCtrl -#undef AESConfigureCCMCtrl -#define AESConfigureCCMCtrl ROM_AESConfigureCCMCtrl +#undef AESConfigureCCMCtrl +#define AESConfigureCCMCtrl ROM_AESConfigureCCMCtrl #endif #endif @@ -832,7 +827,7 @@ __STATIC_INLINE void AESIntUnregister(void) } #endif -#endif // __AES_H__ +#endif // __AES_H__ //***************************************************************************** // diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_batmon.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_batmon.h index 0a186b6..dc8e0a4 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_batmon.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_batmon.h @@ -1,41 +1,41 @@ /****************************************************************************** -* Filename: aon_batmon.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the AON Battery and Temperature -* Monitor -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_batmon.h + * Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) + * Revision: 47343 + * + * Description: Defines and prototypes for the AON Battery and Temperature + * Monitor + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -56,16 +56,15 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aon_batmon.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aon_batmon.h" -#include "debug.h" //***************************************************************************** // @@ -81,10 +80,9 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC +#define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC #endif - //***************************************************************************** // // API Functions and prototypes @@ -145,7 +143,6 @@ AONBatMonDisable(void) HWREG(AON_BATMON_BASE + AON_BATMON_O_CTL) = 0; } - //***************************************************************************** // //! \brief Get the current temperature measurement as a signed value in Deg Celsius. @@ -163,7 +160,7 @@ AONBatMonDisable(void) //! \sa AONBatMonNewTempMeasureReady() // //***************************************************************************** -extern int32_t AONBatMonTemperatureGetDegC( void ); +extern int32_t AONBatMonTemperatureGetDegC(void); //***************************************************************************** // @@ -221,7 +218,9 @@ AONBatMonNewBatteryMeasureReady(void) // Check the status bit. bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_BATUPD) & - AON_BATMON_BATUPD_STAT ? true : false; + AON_BATMON_BATUPD_STAT + ? true + : false; // Clear status bit if set. if (bStatus) @@ -260,7 +259,9 @@ AONBatMonNewTempMeasureReady(void) // Check the status bit. bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_TEMPUPD) & - AON_BATMON_TEMPUPD_STAT ? true : false; + AON_BATMON_TEMPUPD_STAT + ? true + : false; // Clear status bit if set. if (bStatus) @@ -281,8 +282,8 @@ AONBatMonNewTempMeasureReady(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AONBatMonTemperatureGetDegC -#undef AONBatMonTemperatureGetDegC -#define AONBatMonTemperatureGetDegC ROM_AONBatMonTemperatureGetDegC +#undef AONBatMonTemperatureGetDegC +#define AONBatMonTemperatureGetDegC ROM_AONBatMonTemperatureGetDegC #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_event.h index 4792562..c660d13 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_event.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_event.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aon_event.h -* Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017) -* Revision: 49506 -* -* Description: Defines and prototypes for the AON Event fabric. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_event.h + * Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017) + * Revision: 49506 + * + * Description: Defines and prototypes for the AON Event fabric. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,17 +55,16 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aon_event.h" +#include "../inc/hw_device.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_device.h" -#include "../inc/hw_aon_event.h" -#include "debug.h" //***************************************************************************** // @@ -81,12 +80,12 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet -#define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet -#define AONEventAuxWakeUpSet NOROM_AONEventAuxWakeUpSet -#define AONEventAuxWakeUpGet NOROM_AONEventAuxWakeUpGet -#define AONEventMcuSet NOROM_AONEventMcuSet -#define AONEventMcuGet NOROM_AONEventMcuGet +#define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet +#define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet +#define AONEventAuxWakeUpSet NOROM_AONEventAuxWakeUpSet +#define AONEventAuxWakeUpGet NOROM_AONEventAuxWakeUpGet +#define AONEventMcuSet NOROM_AONEventMcuSet +#define AONEventMcuGet NOROM_AONEventMcuGet #endif //***************************************************************************** @@ -98,36 +97,36 @@ extern "C" // AON_EVENT_DIO0 // Edge detect on DIO0. See hw_device.h // ... // ... // AON_EVENT_DIO31 // Edge detect on DIO31. See hw_device.h -#define AON_EVENT_IO 32 // Edge detect on any DIO. Edge detect is enabled and configured in IOC. +#define AON_EVENT_IO 32 // Edge detect on any DIO. Edge detect is enabled and configured in IOC. // Event ID 33 is reserved for future use // Event ID 34 is reserved for future use -#define AON_EVENT_RTC_CH0 35 // RTC channel 0 -#define AON_EVENT_RTC_CH1 36 // RTC channel 1 -#define AON_EVENT_RTC_CH2 37 // RTC channel 2 -#define AON_EVENT_RTC_CH0_DLY 38 // RTC channel 0 - delayed event -#define AON_EVENT_RTC_CH1_DLY 39 // RTC channel 1 - delayed event -#define AON_EVENT_RTC_CH2_DLY 40 // RTC channel 2 - delayed event -#define AON_EVENT_RTC_COMB_DLY 41 // RTC combined delayed event -#define AON_EVENT_RTC_UPD 42 // RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) -#define AON_EVENT_JTAG 43 // JTAG generated event -#define AON_EVENT_AUX_SWEV0 44 // AUX Software triggered event #0 -#define AON_EVENT_AUX_SWEV1 45 // AUX Software triggered event #1 -#define AON_EVENT_AUX_SWEV2 46 // AUX Software triggered event #2 -#define AON_EVENT_AUX_COMPA 47 // Comparator A triggered (synchronized in AUX) -#define AON_EVENT_AUX_COMPB 48 // Comparator B triggered (synchronized in AUX) -#define AON_EVENT_AUX_ADC_DONE 49 // ADC conversion completed -#define AON_EVENT_AUX_TDC_DONE 50 // TDC completed or timed out -#define AON_EVENT_AUX_TIMER0_EV 51 // Timer 0 event -#define AON_EVENT_AUX_TIMER1_EV 52 // Timer 1 event -#define AON_EVENT_BATMON_TEMP 53 // BATMON temperature update event -#define AON_EVENT_BATMON_VOLT 54 // BATMON voltage update event -#define AON_EVENT_AUX_COMPB_ASYNC 55 // Comparator B triggered. Asynchronous signal directly from the AUX Comparator B +#define AON_EVENT_RTC_CH0 35 // RTC channel 0 +#define AON_EVENT_RTC_CH1 36 // RTC channel 1 +#define AON_EVENT_RTC_CH2 37 // RTC channel 2 +#define AON_EVENT_RTC_CH0_DLY 38 // RTC channel 0 - delayed event +#define AON_EVENT_RTC_CH1_DLY 39 // RTC channel 1 - delayed event +#define AON_EVENT_RTC_CH2_DLY 40 // RTC channel 2 - delayed event +#define AON_EVENT_RTC_COMB_DLY 41 // RTC combined delayed event +#define AON_EVENT_RTC_UPD 42 // RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) +#define AON_EVENT_JTAG 43 // JTAG generated event +#define AON_EVENT_AUX_SWEV0 44 // AUX Software triggered event #0 +#define AON_EVENT_AUX_SWEV1 45 // AUX Software triggered event #1 +#define AON_EVENT_AUX_SWEV2 46 // AUX Software triggered event #2 +#define AON_EVENT_AUX_COMPA 47 // Comparator A triggered (synchronized in AUX) +#define AON_EVENT_AUX_COMPB 48 // Comparator B triggered (synchronized in AUX) +#define AON_EVENT_AUX_ADC_DONE 49 // ADC conversion completed +#define AON_EVENT_AUX_TDC_DONE 50 // TDC completed or timed out +#define AON_EVENT_AUX_TIMER0_EV 51 // Timer 0 event +#define AON_EVENT_AUX_TIMER1_EV 52 // Timer 1 event +#define AON_EVENT_BATMON_TEMP 53 // BATMON temperature update event +#define AON_EVENT_BATMON_VOLT 54 // BATMON voltage update event +#define AON_EVENT_AUX_COMPB_ASYNC 55 // Comparator B triggered. Asynchronous signal directly from the AUX Comparator B #define AON_EVENT_AUX_COMPB_ASYNC_N 56 // Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B // Event ID 57-62 is reserved for future use -#define AON_EVENT_NONE 63 // No event, always low +#define AON_EVENT_NONE 63 // No event, always low // Keeping backward compatibility until major revision number is incremented -#define AON_EVENT_RTC0 ( AON_EVENT_RTC_CH0 ) +#define AON_EVENT_RTC0 (AON_EVENT_RTC_CH0) //***************************************************************************** // @@ -135,28 +134,28 @@ extern "C" // by AONEventMCUWakeUpGet(). // //***************************************************************************** -#define AON_EVENT_MCU_WU0 0 // Programmable MCU wake-up event 0 -#define AON_EVENT_MCU_WU1 1 // Programmable MCU wake-up event 1 -#define AON_EVENT_MCU_WU2 2 // Programmable MCU wake-up event 2 -#define AON_EVENT_MCU_WU3 3 // Programmable MCU wake-up event 3 +#define AON_EVENT_MCU_WU0 0 // Programmable MCU wake-up event 0 +#define AON_EVENT_MCU_WU1 1 // Programmable MCU wake-up event 1 +#define AON_EVENT_MCU_WU2 2 // Programmable MCU wake-up event 2 +#define AON_EVENT_MCU_WU3 3 // Programmable MCU wake-up event 3 //***************************************************************************** // // Values that can be passed to AONEventAuxWakeUpSet() and AONEventAuxWakeUpGet() // //***************************************************************************** -#define AON_EVENT_AUX_WU0 0 // Programmable AUX wake-up event 0 -#define AON_EVENT_AUX_WU1 1 // Programmable AUX wake-up event 1 -#define AON_EVENT_AUX_WU2 2 // Programmable AUX wake-up event 2 +#define AON_EVENT_AUX_WU0 0 // Programmable AUX wake-up event 0 +#define AON_EVENT_AUX_WU1 1 // Programmable AUX wake-up event 1 +#define AON_EVENT_AUX_WU2 2 // Programmable AUX wake-up event 2 //***************************************************************************** // // Values that can be passed to AONEventMcuSet() and AONEventMcuGet() // //***************************************************************************** -#define AON_EVENT_MCU_EVENT0 0 // Programmable event source fed to MCU event fabric (first of 3) -#define AON_EVENT_MCU_EVENT1 1 // Programmable event source fed to MCU event fabric (second of 3) -#define AON_EVENT_MCU_EVENT2 2 // Programmable event source fed to MCU event fabric (third of 3) +#define AON_EVENT_MCU_EVENT0 0 // Programmable event source fed to MCU event fabric (first of 3) +#define AON_EVENT_MCU_EVENT1 1 // Programmable event source fed to MCU event fabric (second of 3) +#define AON_EVENT_MCU_EVENT2 2 // Programmable event source fed to MCU event fabric (third of 3) //***************************************************************************** // @@ -575,28 +574,28 @@ AONEventRtcGet(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AONEventMcuWakeUpSet -#undef AONEventMcuWakeUpSet -#define AONEventMcuWakeUpSet ROM_AONEventMcuWakeUpSet +#undef AONEventMcuWakeUpSet +#define AONEventMcuWakeUpSet ROM_AONEventMcuWakeUpSet #endif #ifdef ROM_AONEventMcuWakeUpGet -#undef AONEventMcuWakeUpGet -#define AONEventMcuWakeUpGet ROM_AONEventMcuWakeUpGet +#undef AONEventMcuWakeUpGet +#define AONEventMcuWakeUpGet ROM_AONEventMcuWakeUpGet #endif #ifdef ROM_AONEventAuxWakeUpSet -#undef AONEventAuxWakeUpSet -#define AONEventAuxWakeUpSet ROM_AONEventAuxWakeUpSet +#undef AONEventAuxWakeUpSet +#define AONEventAuxWakeUpSet ROM_AONEventAuxWakeUpSet #endif #ifdef ROM_AONEventAuxWakeUpGet -#undef AONEventAuxWakeUpGet -#define AONEventAuxWakeUpGet ROM_AONEventAuxWakeUpGet +#undef AONEventAuxWakeUpGet +#define AONEventAuxWakeUpGet ROM_AONEventAuxWakeUpGet #endif #ifdef ROM_AONEventMcuSet -#undef AONEventMcuSet -#define AONEventMcuSet ROM_AONEventMcuSet +#undef AONEventMcuSet +#define AONEventMcuSet ROM_AONEventMcuSet #endif #ifdef ROM_AONEventMcuGet -#undef AONEventMcuGet -#define AONEventMcuGet ROM_AONEventMcuGet +#undef AONEventMcuGet +#define AONEventMcuGet ROM_AONEventMcuGet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_event_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_event_doc.h index e1fcea8..dfeed44 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_event_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_event_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: aon_event_doc.h -* Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017) -* Revision: 49506 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_event_doc.h + * Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017) + * Revision: 49506 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup aonevent_api //! @{ //! \section sec_aonevent Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_ioc.h index f60cb03..baffd83 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_ioc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_ioc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aon_ioc.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the AON IO Controller -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_ioc.h + * Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) + * Revision: 47343 + * + * Description: Defines and prototypes for the AON IO Controller + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,34 +55,33 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aon_ioc.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aon_ioc.h" -#include "debug.h" //***************************************************************************** // // Defines for the drive strength // //***************************************************************************** -#define AONIOC_DRV_STR_1 0x00000000 // Lowest drive strength -#define AONIOC_DRV_STR_2 0x00000001 -#define AONIOC_DRV_STR_3 0x00000003 -#define AONIOC_DRV_STR_4 0x00000002 -#define AONIOC_DRV_STR_5 0x00000006 -#define AONIOC_DRV_STR_6 0x00000007 -#define AONIOC_DRV_STR_7 0x00000005 -#define AONIOC_DRV_STR_8 0x00000004 // Highest drive strength +#define AONIOC_DRV_STR_1 0x00000000 // Lowest drive strength +#define AONIOC_DRV_STR_2 0x00000001 +#define AONIOC_DRV_STR_3 0x00000003 +#define AONIOC_DRV_STR_4 0x00000002 +#define AONIOC_DRV_STR_5 0x00000006 +#define AONIOC_DRV_STR_6 0x00000007 +#define AONIOC_DRV_STR_7 0x00000005 +#define AONIOC_DRV_STR_8 0x00000004 // Highest drive strength -#define AONIOC_DRV_LVL_MIN (AON_IOC_O_IOSTRMIN) -#define AONIOC_DRV_LVL_MED (AON_IOC_O_IOSTRMED) -#define AONIOC_DRV_LVL_MAX (AON_IOC_O_IOSTRMAX) +#define AONIOC_DRV_LVL_MIN (AON_IOC_O_IOSTRMIN) +#define AONIOC_DRV_LVL_MED (AON_IOC_O_IOSTRMED) +#define AONIOC_DRV_LVL_MAX (AON_IOC_O_IOSTRMAX) //***************************************************************************** // @@ -186,7 +185,7 @@ AONIOCDriveStrengthGet(uint32_t ui32DriveLevel) (ui32DriveLevel == AONIOC_DRV_LVL_MAX)); // Return the drive strength value. - return ( HWREG(AON_IOC_BASE + ui32DriveLevel) ); + return (HWREG(AON_IOC_BASE + ui32DriveLevel)); } //***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_ioc_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_ioc_doc.h index 7fe0e93..e90c20c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_ioc_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_ioc_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: aon_ioc_doc.h -* Revised: 2016-03-30 11:01:30 +0200 (Wed, 30 Mar 2016) -* Revision: 45969 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_ioc_doc.h + * Revised: 2016-03-30 11:01:30 +0200 (Wed, 30 Mar 2016) + * Revision: 45969 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup aonioc_api //! @{ //! \section sec_aonioc Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_rtc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_rtc.h index 569fe22..9d1654b 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_rtc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_rtc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aon_rtc.h -* Revised: 2017-08-16 15:13:43 +0200 (Wed, 16 Aug 2017) -* Revision: 49593 -* -* Description: Defines and prototypes for the AON RTC -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_rtc.h + * Revised: 2017-08-16 15:13:43 +0200 (Wed, 16 Aug 2017) + * Revision: 49593 + * + * Description: Defines and prototypes for the AON RTC + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,16 +55,15 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aon_rtc.h" -#include "debug.h" //***************************************************************************** // @@ -80,8 +79,8 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AONRTCCurrentCompareValueGet NOROM_AONRTCCurrentCompareValueGet -#define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet +#define AONRTCCurrentCompareValueGet NOROM_AONRTCCurrentCompareValueGet +#define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet #endif //***************************************************************************** @@ -90,11 +89,11 @@ extern "C" // parameter. // //***************************************************************************** -#define AON_RTC_CH_NONE 0x0 // RTC No channel -#define AON_RTC_CH0 0x1 // RTC Channel 0 -#define AON_RTC_CH1 0x2 // RTC Channel 1 -#define AON_RTC_CH2 0x4 // RTC Channel 2 -#define AON_RTC_ACTIVE 0x8 // RTC Active +#define AON_RTC_CH_NONE 0x0 // RTC No channel +#define AON_RTC_CH0 0x1 // RTC Channel 0 +#define AON_RTC_CH1 0x2 // RTC Channel 1 +#define AON_RTC_CH2 0x4 // RTC Channel 2 +#define AON_RTC_ACTIVE 0x8 // RTC Active //***************************************************************************** // @@ -102,19 +101,19 @@ extern "C" // //***************************************************************************** #define AON_RTC_CONFIG_DELAY_NODELAY 0 // NO DELAY -#define AON_RTC_CONFIG_DELAY_1 1 // Delay of 1 clk cycle -#define AON_RTC_CONFIG_DELAY_2 2 // Delay of 2 clk cycles -#define AON_RTC_CONFIG_DELAY_4 3 // Delay of 4 clk cycles -#define AON_RTC_CONFIG_DELAY_8 4 // Delay of 8 clk cycles -#define AON_RTC_CONFIG_DELAY_16 5 // Delay of 16 clk cycles -#define AON_RTC_CONFIG_DELAY_32 6 // Delay of 32 clk cycles -#define AON_RTC_CONFIG_DELAY_48 7 // Delay of 48 clk cycles -#define AON_RTC_CONFIG_DELAY_64 8 // Delay of 64 clk cycles -#define AON_RTC_CONFIG_DELAY_80 9 // Delay of 80 clk cycles -#define AON_RTC_CONFIG_DELAY_96 10 // Delay of 96 clk cycles -#define AON_RTC_CONFIG_DELAY_112 11 // Delay of 112 clk cycles -#define AON_RTC_CONFIG_DELAY_128 12 // Delay of 128 clk cycles -#define AON_RTC_CONFIG_DELAY_144 13 // Delay of 144 clk cycles +#define AON_RTC_CONFIG_DELAY_1 1 // Delay of 1 clk cycle +#define AON_RTC_CONFIG_DELAY_2 2 // Delay of 2 clk cycles +#define AON_RTC_CONFIG_DELAY_4 3 // Delay of 4 clk cycles +#define AON_RTC_CONFIG_DELAY_8 4 // Delay of 8 clk cycles +#define AON_RTC_CONFIG_DELAY_16 5 // Delay of 16 clk cycles +#define AON_RTC_CONFIG_DELAY_32 6 // Delay of 32 clk cycles +#define AON_RTC_CONFIG_DELAY_48 7 // Delay of 48 clk cycles +#define AON_RTC_CONFIG_DELAY_64 8 // Delay of 64 clk cycles +#define AON_RTC_CONFIG_DELAY_80 9 // Delay of 80 clk cycles +#define AON_RTC_CONFIG_DELAY_96 10 // Delay of 96 clk cycles +#define AON_RTC_CONFIG_DELAY_112 11 // Delay of 112 clk cycles +#define AON_RTC_CONFIG_DELAY_128 12 // Delay of 128 clk cycles +#define AON_RTC_CONFIG_DELAY_144 13 // Delay of 144 clk cycles //***************************************************************************** // @@ -122,8 +121,8 @@ extern "C" // parameter. // //***************************************************************************** -#define AON_RTC_MODE_CH1_CAPTURE 1 // Capture mode -#define AON_RTC_MODE_CH1_COMPARE 0 // Compare Mode +#define AON_RTC_MODE_CH1_CAPTURE 1 // Capture mode +#define AON_RTC_MODE_CH1_COMPARE 0 // Compare Mode //***************************************************************************** // @@ -131,7 +130,7 @@ extern "C" // parameter. // //***************************************************************************** -#define AON_RTC_MODE_CH2_CONTINUOUS 1 // Continuous mode +#define AON_RTC_MODE_CH2_CONTINUOUS 1 // Continuous mode #define AON_RTC_MODE_CH2_NORMALCOMPARE 0 // Normal compare mode //***************************************************************************** @@ -148,7 +147,7 @@ extern "C" // ( 4 * FACTOR_SEC_TO_COMP_VAL_FORMAT ) // //***************************************************************************** -#define FACTOR_SEC_TO_COMP_VAL_FORMAT 0x00010000 +#define FACTOR_SEC_TO_COMP_VAL_FORMAT 0x00010000 //***************************************************************************** // @@ -306,8 +305,7 @@ AONRTCDelayConfig(uint32_t ui32Delay) // Check the arguments. ASSERT(ui32Delay <= AON_RTC_CONFIG_DELAY_144); - - ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); + ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); ui32Cfg &= ~(AON_RTC_CTL_EV_DELAY_M); ui32Cfg |= (ui32Delay << AON_RTC_CTL_EV_DELAY_S); @@ -339,10 +337,10 @@ AONRTCCombinedEventConfig(uint32_t ui32Channels) uint32_t ui32Cfg; // Check the arguments. - ASSERT( (ui32Channels & (AON_RTC_CH0 | AON_RTC_CH1 | AON_RTC_CH2)) || - (ui32Channels == AON_RTC_CH_NONE) ); + ASSERT((ui32Channels & (AON_RTC_CH0 | AON_RTC_CH1 | AON_RTC_CH2)) || + (ui32Channels == AON_RTC_CH_NONE)); - ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); + ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); ui32Cfg &= ~(AON_RTC_CTL_COMB_EV_MASK_M); ui32Cfg |= (ui32Channels << AON_RTC_CTL_COMB_EV_MASK_S); @@ -907,12 +905,12 @@ AONRTCCaptureValueCh1Get(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AONRTCCurrentCompareValueGet -#undef AONRTCCurrentCompareValueGet -#define AONRTCCurrentCompareValueGet ROM_AONRTCCurrentCompareValueGet +#undef AONRTCCurrentCompareValueGet +#define AONRTCCurrentCompareValueGet ROM_AONRTCCurrentCompareValueGet #endif #ifdef ROM_AONRTCCurrent64BitValueGet -#undef AONRTCCurrent64BitValueGet -#define AONRTCCurrent64BitValueGet ROM_AONRTCCurrent64BitValueGet +#undef AONRTCCurrent64BitValueGet +#define AONRTCCurrent64BitValueGet ROM_AONRTCCurrent64BitValueGet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_rtc_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_rtc_doc.h index b3c142b..35dd310 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_rtc_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_rtc_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: aon_rtc_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_rtc_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup aonrtc_api //! @{ //! \section sec_aonrtc Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_wuc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_wuc.h index a915840..f507b5c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_wuc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aon_wuc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aon_wuc.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Defines and prototypes for the AON Wake-Up Controller -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_wuc.h + * Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) + * Revision: 49096 + * + * Description: Defines and prototypes for the AON Wake-Up Controller + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,19 +55,18 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_aon_wuc.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" +#include "interrupt.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_aon_wuc.h" -#include "../inc/hw_aon_rtc.h" -#include "interrupt.h" -#include "debug.h" //***************************************************************************** // @@ -83,9 +82,9 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AONWUCAuxReset NOROM_AONWUCAuxReset -#define AONWUCRechargeCtrlConfigSet NOROM_AONWUCRechargeCtrlConfigSet -#define AONWUCOscConfig NOROM_AONWUCOscConfig +#define AONWUCAuxReset NOROM_AONWUCAuxReset +#define AONWUCRechargeCtrlConfigSet NOROM_AONWUCRechargeCtrlConfigSet +#define AONWUCOscConfig NOROM_AONWUCOscConfig #endif //***************************************************************************** @@ -93,11 +92,11 @@ extern "C" // Defines the possible clock source for the MCU and AUX domain. // //***************************************************************************** -#define AONWUC_CLOCK_SRC_HF 0x00000003 // System clock high frequency - +#define AONWUC_CLOCK_SRC_HF 0x00000003 // System clock high frequency - // 48 MHz. -#define AONWUC_CLOCK_SRC_LF 0x00000001 // System clock low frequency - +#define AONWUC_CLOCK_SRC_LF 0x00000001 // System clock low frequency - // 32 kHz. -#define AONWUC_NO_CLOCK 0x00000000 // System clock low frequency - +#define AONWUC_NO_CLOCK 0x00000000 // System clock low frequency - // 32 kHz. //***************************************************************************** @@ -105,30 +104,30 @@ extern "C" // Defines the possible clock division factors for the AUX domain. // //***************************************************************************** -#define AUX_CLOCK_DIV_2 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV2 ) -#define AUX_CLOCK_DIV_4 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV4 ) -#define AUX_CLOCK_DIV_8 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV8 ) -#define AUX_CLOCK_DIV_16 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV16 ) -#define AUX_CLOCK_DIV_32 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV32 ) -#define AUX_CLOCK_DIV_64 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV64 ) -#define AUX_CLOCK_DIV_128 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV128 ) -#define AUX_CLOCK_DIV_256 ( AON_WUC_AUXCLK_SCLK_HF_DIV_DIV256 ) -#define AUX_CLOCK_DIV_UNUSED ( AON_WUC_AUXCLK_SCLK_HF_DIV_M + ( 1 << AON_WUC_AUXCLK_SCLK_HF_DIV_S )) -#define AUX_CLOCK_DIV_M ( AON_WUC_AUXCLK_SCLK_HF_DIV_M ) +#define AUX_CLOCK_DIV_2 (AON_WUC_AUXCLK_SCLK_HF_DIV_DIV2) +#define AUX_CLOCK_DIV_4 (AON_WUC_AUXCLK_SCLK_HF_DIV_DIV4) +#define AUX_CLOCK_DIV_8 (AON_WUC_AUXCLK_SCLK_HF_DIV_DIV8) +#define AUX_CLOCK_DIV_16 (AON_WUC_AUXCLK_SCLK_HF_DIV_DIV16) +#define AUX_CLOCK_DIV_32 (AON_WUC_AUXCLK_SCLK_HF_DIV_DIV32) +#define AUX_CLOCK_DIV_64 (AON_WUC_AUXCLK_SCLK_HF_DIV_DIV64) +#define AUX_CLOCK_DIV_128 (AON_WUC_AUXCLK_SCLK_HF_DIV_DIV128) +#define AUX_CLOCK_DIV_256 (AON_WUC_AUXCLK_SCLK_HF_DIV_DIV256) +#define AUX_CLOCK_DIV_UNUSED (AON_WUC_AUXCLK_SCLK_HF_DIV_M + (1 << AON_WUC_AUXCLK_SCLK_HF_DIV_S)) +#define AUX_CLOCK_DIV_M (AON_WUC_AUXCLK_SCLK_HF_DIV_M) //***************************************************************************** // // Defines used for configuring the power-off and wake up procedure. // //***************************************************************************** -#define MCU_VIRT_PWOFF_DISABLE 0x00000000 -#define MCU_VIRT_PWOFF_ENABLE 0x00020000 -#define MCU_IMM_WAKE_UP 0x00000000 -#define MCU_FIXED_WAKE_UP 0x00010000 -#define AUX_VIRT_PWOFF_DISABLE 0x00000000 -#define AUX_VIRT_PWOFF_ENABLE 0x00020000 -#define AUX_IMM_WAKE_UP 0x00000000 -#define AUX_FIXED_WAKE_UP 0x00010000 +#define MCU_VIRT_PWOFF_DISABLE 0x00000000 +#define MCU_VIRT_PWOFF_ENABLE 0x00020000 +#define MCU_IMM_WAKE_UP 0x00000000 +#define MCU_FIXED_WAKE_UP 0x00010000 +#define AUX_VIRT_PWOFF_DISABLE 0x00000000 +#define AUX_VIRT_PWOFF_ENABLE 0x00020000 +#define AUX_IMM_WAKE_UP 0x00000000 +#define AUX_FIXED_WAKE_UP 0x00010000 //***************************************************************************** // @@ -136,12 +135,12 @@ extern "C" // retention on the SRAM in both the MCU and the AUX domain. // //***************************************************************************** -#define MCU_RAM0_RETENTION 0x00000001 -#define MCU_RAM1_RETENTION 0x00000002 -#define MCU_RAM2_RETENTION 0x00000004 -#define MCU_RAM3_RETENTION 0x00000008 +#define MCU_RAM0_RETENTION 0x00000001 +#define MCU_RAM1_RETENTION 0x00000002 +#define MCU_RAM2_RETENTION 0x00000004 +#define MCU_RAM3_RETENTION 0x00000008 #define MCU_RAM_BLOCK_RETENTION 0x0000000F -#define MCU_AUX_RET_ENABLE 0x00000001 +#define MCU_AUX_RET_ENABLE 0x00000001 //***************************************************************************** // @@ -149,8 +148,8 @@ extern "C" // AONWUCAuxWakeUpEvent() . // //***************************************************************************** -#define AONWUC_AUX_WAKEUP 0x00000001 -#define AONWUC_AUX_ALLOW_SLEEP 0x00000000 +#define AONWUC_AUX_WAKEUP 0x00000001 +#define AONWUC_AUX_ALLOW_SLEEP 0x00000000 //***************************************************************************** // @@ -158,42 +157,41 @@ extern "C" // AONWUCPowerStatusGet() . // //***************************************************************************** -#define AONWUC_OSC_GBIAS_REQ 0x00400000 // OSC is requesting GBias -#define AONWUC_AUX_GBIAS_REQ 0x00200000 // AUX is requesting GBias -#define AONWUC_MCU_GBIAS_REQ 0x00100000 // MCU is requesting GBias -#define AONWUC_OSC_BGAP_REQ 0x00040000 // OSC is requesting BGap -#define AONWUC_AUX_BGAP_REQ 0x00020000 // AUX is requesting BGap -#define AONWUC_MCU_BGAP_REQ 0x00010000 // MCU is requesting BGap -#define AONWUC_GBIAS_ON 0x00002000 // Global Bias is on -#define AONWUC_BGAP_ON 0x00001000 // Band Gap is on -#define AONWUC_AUX_POWER_DOWN 0x00000200 // AUX is in powerdown mode -#define AONWUC_MCU_POWER_DOWN 0x00000100 // MCU is in powerdown mode -#define AONWUC_JTAG_POWER_ON 0x00000040 // JTAG is powered on -#define AONWUC_AUX_POWER_ON 0x00000020 // AUX is powered on -#define AONWUC_MCU_POWER_ON 0x00000010 // MCU is powered on -#define AONWUC_SPLY_POWER_DOWN 0x00000001 // Power supply is in power down - +#define AONWUC_OSC_GBIAS_REQ 0x00400000 // OSC is requesting GBias +#define AONWUC_AUX_GBIAS_REQ 0x00200000 // AUX is requesting GBias +#define AONWUC_MCU_GBIAS_REQ 0x00100000 // MCU is requesting GBias +#define AONWUC_OSC_BGAP_REQ 0x00040000 // OSC is requesting BGap +#define AONWUC_AUX_BGAP_REQ 0x00020000 // AUX is requesting BGap +#define AONWUC_MCU_BGAP_REQ 0x00010000 // MCU is requesting BGap +#define AONWUC_GBIAS_ON 0x00002000 // Global Bias is on +#define AONWUC_BGAP_ON 0x00001000 // Band Gap is on +#define AONWUC_AUX_POWER_DOWN 0x00000200 // AUX is in powerdown mode +#define AONWUC_MCU_POWER_DOWN 0x00000100 // MCU is in powerdown mode +#define AONWUC_JTAG_POWER_ON 0x00000040 // JTAG is powered on +#define AONWUC_AUX_POWER_ON 0x00000020 // AUX is powered on +#define AONWUC_MCU_POWER_ON 0x00000010 // MCU is powered on +#define AONWUC_SPLY_POWER_DOWN 0x00000001 // Power supply is in power down //***************************************************************************** // // RAM repair status bits. Values are returned by AOXWUCRamRepairStatusGet() . // //***************************************************************************** -#define MCU_RAMREPAIR_DONE 0x00000001 -#define AUX_RAMREPAIR_DONE 0x00000002 +#define MCU_RAMREPAIR_DONE 0x00000001 +#define AUX_RAMREPAIR_DONE 0x00000002 //***************************************************************************** //***************************************************************************** -#define RC_RATE_MAX 768 // Maximum recharge rate for the +#define RC_RATE_MAX 768 // Maximum recharge rate for the // recharge controller. -#define RC_RATE_MIN 2 // Minimum recharge rate for the +#define RC_RATE_MIN 2 // Minimum recharge rate for the // recharge controller. //***************************************************************************** -#define AONWUC_MCU_RESET_SRC 0x00000002 // MCU reset source can be SW or +#define AONWUC_MCU_RESET_SRC 0x00000002 // MCU reset source can be SW or // JTAG -#define AONWUC_MCU_WARM_RESET 0x00000001 // MCU reset type and can be warm +#define AONWUC_MCU_WARM_RESET 0x00000001 // MCU reset type and can be warm // or not warm. //***************************************************************************** @@ -235,8 +233,7 @@ AONWUCMcuPowerDownConfig(uint32_t ui32ClkSrc) ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_MCUCLK); ui32Reg &= ~AON_WUC_MCUCLK_PWR_DWN_SRC_M; HWREG(AON_WUC_BASE + AON_WUC_O_MCUCLK) = ui32Reg | - (ui32ClkSrc << - AON_WUC_MCUCLK_PWR_DWN_SRC_S); + (ui32ClkSrc << AON_WUC_MCUCLK_PWR_DWN_SRC_S); } //***************************************************************************** @@ -338,7 +335,6 @@ AONWUCMcuSRamConfig(uint32_t ui32Retention) HWREG(AON_WUC_BASE + AON_WUC_O_MCUCFG) = ui32Reg; } - //***************************************************************************** // //! \brief Return the clock configuration for the AUX domain. @@ -399,11 +395,9 @@ AONWUCAuxPowerDownConfig(uint32_t ui32ClkSrc) ui32Reg = HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK); ui32Reg &= ~AON_WUC_AUXCLK_PWR_DWN_SRC_M; HWREG(AON_WUC_BASE + AON_WUC_O_AUXCLK) = ui32Reg | - (ui32ClkSrc << - AON_WUC_AUXCLK_PWR_DWN_SRC_S); + (ui32ClkSrc << AON_WUC_AUXCLK_PWR_DWN_SRC_S); } - //***************************************************************************** // //! \brief Configure the retention on the AUX SRAM. @@ -795,7 +789,6 @@ AONWUCJtagPowerOff(void) HWREG(AON_WUC_BASE + AON_WUC_O_JTAGCFG) = 0; } - //***************************************************************************** // // Support for DriverLib in ROM: @@ -805,16 +798,16 @@ AONWUCJtagPowerOff(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AONWUCAuxReset -#undef AONWUCAuxReset -#define AONWUCAuxReset ROM_AONWUCAuxReset +#undef AONWUCAuxReset +#define AONWUCAuxReset ROM_AONWUCAuxReset #endif #ifdef ROM_AONWUCRechargeCtrlConfigSet -#undef AONWUCRechargeCtrlConfigSet -#define AONWUCRechargeCtrlConfigSet ROM_AONWUCRechargeCtrlConfigSet +#undef AONWUCRechargeCtrlConfigSet +#define AONWUCRechargeCtrlConfigSet ROM_AONWUCRechargeCtrlConfigSet #endif #ifdef ROM_AONWUCOscConfig -#undef AONWUCOscConfig -#define AONWUCOscConfig ROM_AONWUCOscConfig +#undef AONWUCOscConfig +#define AONWUCOscConfig ROM_AONWUCOscConfig #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_adc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_adc.h index 34a0557..c5a3665 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_adc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_adc.h @@ -1,41 +1,41 @@ /****************************************************************************** -* Filename: aux_adc.h -* Revised: 2018-02-07 09:45:39 +0100 (Wed, 07 Feb 2018) -* Revision: 51437 -* -* Description: Defines and prototypes for the AUX Analog-to-Digital -* Converter -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aux_adc.h + * Revised: 2018-02-07 09:45:39 +0100 (Wed, 07 Feb 2018) + * Revision: 51437 + * + * Description: Defines and prototypes for the AUX Analog-to-Digital + * Converter + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -56,19 +56,18 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_event.h" #include "../inc/hw_adi.h" #include "../inc/hw_adi_4_aux.h" #include "../inc/hw_aux_anaif.h" +#include "../inc/hw_event.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "rom.h" +#include +#include //***************************************************************************** // @@ -84,17 +83,17 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AUXADCDisable NOROM_AUXADCDisable -#define AUXADCEnableAsync NOROM_AUXADCEnableAsync -#define AUXADCEnableSync NOROM_AUXADCEnableSync -#define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling -#define AUXADCFlushFifo NOROM_AUXADCFlushFifo -#define AUXADCReadFifo NOROM_AUXADCReadFifo -#define AUXADCPopFifo NOROM_AUXADCPopFifo -#define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain -#define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset -#define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts -#define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue +#define AUXADCDisable NOROM_AUXADCDisable +#define AUXADCEnableAsync NOROM_AUXADCEnableAsync +#define AUXADCEnableSync NOROM_AUXADCEnableSync +#define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling +#define AUXADCFlushFifo NOROM_AUXADCFlushFifo +#define AUXADCReadFifo NOROM_AUXADCReadFifo +#define AUXADCPopFifo NOROM_AUXADCPopFifo +#define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain +#define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset +#define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts +#define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue #define AUXADCAdjustValueForGainAndOffset NOROM_AUXADCAdjustValueForGainAndOffset #define AUXADCUnadjustValueForGainAndOffset NOROM_AUXADCUnadjustValueForGainAndOffset #endif @@ -104,62 +103,61 @@ extern "C" // Defines for ADC reference sources. // //***************************************************************************** -#define AUXADC_REF_FIXED (0 << ADI_4_AUX_ADCREF0_SRC_S) -#define AUXADC_REF_VDDS_REL (1 << ADI_4_AUX_ADCREF0_SRC_S) +#define AUXADC_REF_FIXED (0 << ADI_4_AUX_ADCREF0_SRC_S) +#define AUXADC_REF_VDDS_REL (1 << ADI_4_AUX_ADCREF0_SRC_S) //***************************************************************************** // // Defines for the ADC FIFO status bits. // //***************************************************************************** -#define AUXADC_FIFO_EMPTY_M (AUX_ANAIF_ADCFIFOSTAT_EMPTY_M) -#define AUXADC_FIFO_ALMOST_FULL_M (AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M) -#define AUXADC_FIFO_FULL_M (AUX_ANAIF_ADCFIFOSTAT_FULL_M) -#define AUXADC_FIFO_UNDERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M) -#define AUXADC_FIFO_OVERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M) +#define AUXADC_FIFO_EMPTY_M (AUX_ANAIF_ADCFIFOSTAT_EMPTY_M) +#define AUXADC_FIFO_ALMOST_FULL_M (AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M) +#define AUXADC_FIFO_FULL_M (AUX_ANAIF_ADCFIFOSTAT_FULL_M) +#define AUXADC_FIFO_UNDERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M) +#define AUXADC_FIFO_OVERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M) //***************************************************************************** // // Defines for supported ADC triggers. // //***************************************************************************** -#define AUXADC_TRIGGER_MANUAL (EVENT_AUXSEL0_EV_NONE) -#define AUXADC_TRIGGER_GPT0A (EVENT_AUXSEL0_EV_GPT0A) -#define AUXADC_TRIGGER_GPT0B (EVENT_AUXSEL0_EV_GPT0B) -#define AUXADC_TRIGGER_GPT1A (EVENT_AUXSEL0_EV_GPT1A) -#define AUXADC_TRIGGER_GPT1B (EVENT_AUXSEL0_EV_GPT1B) -#define AUXADC_TRIGGER_GPT2A (EVENT_AUXSEL0_EV_GPT2A) -#define AUXADC_TRIGGER_GPT2B (EVENT_AUXSEL0_EV_GPT2B) -#define AUXADC_TRIGGER_GPT3A (EVENT_AUXSEL0_EV_GPT3A) -#define AUXADC_TRIGGER_GPT3B (EVENT_AUXSEL0_EV_GPT3B) +#define AUXADC_TRIGGER_MANUAL (EVENT_AUXSEL0_EV_NONE) +#define AUXADC_TRIGGER_GPT0A (EVENT_AUXSEL0_EV_GPT0A) +#define AUXADC_TRIGGER_GPT0B (EVENT_AUXSEL0_EV_GPT0B) +#define AUXADC_TRIGGER_GPT1A (EVENT_AUXSEL0_EV_GPT1A) +#define AUXADC_TRIGGER_GPT1B (EVENT_AUXSEL0_EV_GPT1B) +#define AUXADC_TRIGGER_GPT2A (EVENT_AUXSEL0_EV_GPT2A) +#define AUXADC_TRIGGER_GPT2B (EVENT_AUXSEL0_EV_GPT2B) +#define AUXADC_TRIGGER_GPT3A (EVENT_AUXSEL0_EV_GPT3A) +#define AUXADC_TRIGGER_GPT3B (EVENT_AUXSEL0_EV_GPT3B) //***************************************************************************** // // Defines for ADC sampling type for synchronous operation. // //***************************************************************************** -#define AUXADC_SAMPLE_TIME_2P7_US 3 -#define AUXADC_SAMPLE_TIME_5P3_US 4 -#define AUXADC_SAMPLE_TIME_10P6_US 5 -#define AUXADC_SAMPLE_TIME_21P3_US 6 -#define AUXADC_SAMPLE_TIME_42P6_US 7 -#define AUXADC_SAMPLE_TIME_85P3_US 8 -#define AUXADC_SAMPLE_TIME_170_US 9 -#define AUXADC_SAMPLE_TIME_341_US 10 -#define AUXADC_SAMPLE_TIME_682_US 11 -#define AUXADC_SAMPLE_TIME_1P37_MS 12 -#define AUXADC_SAMPLE_TIME_2P73_MS 13 -#define AUXADC_SAMPLE_TIME_5P46_MS 14 -#define AUXADC_SAMPLE_TIME_10P9_MS 15 +#define AUXADC_SAMPLE_TIME_2P7_US 3 +#define AUXADC_SAMPLE_TIME_5P3_US 4 +#define AUXADC_SAMPLE_TIME_10P6_US 5 +#define AUXADC_SAMPLE_TIME_21P3_US 6 +#define AUXADC_SAMPLE_TIME_42P6_US 7 +#define AUXADC_SAMPLE_TIME_85P3_US 8 +#define AUXADC_SAMPLE_TIME_170_US 9 +#define AUXADC_SAMPLE_TIME_341_US 10 +#define AUXADC_SAMPLE_TIME_682_US 11 +#define AUXADC_SAMPLE_TIME_1P37_MS 12 +#define AUXADC_SAMPLE_TIME_2P73_MS 13 +#define AUXADC_SAMPLE_TIME_5P46_MS 14 +#define AUXADC_SAMPLE_TIME_10P9_MS 15 //***************************************************************************** // // Equivalent voltages for fixed ADC reference, in microvolts. // //***************************************************************************** -#define AUXADC_FIXED_REF_VOLTAGE_NORMAL 4300000 -#define AUXADC_FIXED_REF_VOLTAGE_UNSCALED 1478500 - +#define AUXADC_FIXED_REF_VOLTAGE_NORMAL 4300000 +#define AUXADC_FIXED_REF_VOLTAGE_UNSCALED 1478500 //***************************************************************************** // @@ -167,7 +165,6 @@ extern "C" // //***************************************************************************** - //***************************************************************************** // //! \brief Disables the ADC. @@ -517,55 +514,55 @@ extern int32_t AUXADCUnadjustValueForGainAndOffset(int32_t adcValue, int32_t gai #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AUXADCDisable -#undef AUXADCDisable -#define AUXADCDisable ROM_AUXADCDisable +#undef AUXADCDisable +#define AUXADCDisable ROM_AUXADCDisable #endif #ifdef ROM_AUXADCEnableAsync -#undef AUXADCEnableAsync -#define AUXADCEnableAsync ROM_AUXADCEnableAsync +#undef AUXADCEnableAsync +#define AUXADCEnableAsync ROM_AUXADCEnableAsync #endif #ifdef ROM_AUXADCEnableSync -#undef AUXADCEnableSync -#define AUXADCEnableSync ROM_AUXADCEnableSync +#undef AUXADCEnableSync +#define AUXADCEnableSync ROM_AUXADCEnableSync #endif #ifdef ROM_AUXADCDisableInputScaling -#undef AUXADCDisableInputScaling -#define AUXADCDisableInputScaling ROM_AUXADCDisableInputScaling +#undef AUXADCDisableInputScaling +#define AUXADCDisableInputScaling ROM_AUXADCDisableInputScaling #endif #ifdef ROM_AUXADCFlushFifo -#undef AUXADCFlushFifo -#define AUXADCFlushFifo ROM_AUXADCFlushFifo +#undef AUXADCFlushFifo +#define AUXADCFlushFifo ROM_AUXADCFlushFifo #endif #ifdef ROM_AUXADCReadFifo -#undef AUXADCReadFifo -#define AUXADCReadFifo ROM_AUXADCReadFifo +#undef AUXADCReadFifo +#define AUXADCReadFifo ROM_AUXADCReadFifo #endif #ifdef ROM_AUXADCPopFifo -#undef AUXADCPopFifo -#define AUXADCPopFifo ROM_AUXADCPopFifo +#undef AUXADCPopFifo +#define AUXADCPopFifo ROM_AUXADCPopFifo #endif #ifdef ROM_AUXADCGetAdjustmentGain -#undef AUXADCGetAdjustmentGain -#define AUXADCGetAdjustmentGain ROM_AUXADCGetAdjustmentGain +#undef AUXADCGetAdjustmentGain +#define AUXADCGetAdjustmentGain ROM_AUXADCGetAdjustmentGain #endif #ifdef ROM_AUXADCGetAdjustmentOffset -#undef AUXADCGetAdjustmentOffset -#define AUXADCGetAdjustmentOffset ROM_AUXADCGetAdjustmentOffset +#undef AUXADCGetAdjustmentOffset +#define AUXADCGetAdjustmentOffset ROM_AUXADCGetAdjustmentOffset #endif #ifdef ROM_AUXADCValueToMicrovolts -#undef AUXADCValueToMicrovolts -#define AUXADCValueToMicrovolts ROM_AUXADCValueToMicrovolts +#undef AUXADCValueToMicrovolts +#define AUXADCValueToMicrovolts ROM_AUXADCValueToMicrovolts #endif #ifdef ROM_AUXADCMicrovoltsToValue -#undef AUXADCMicrovoltsToValue -#define AUXADCMicrovoltsToValue ROM_AUXADCMicrovoltsToValue +#undef AUXADCMicrovoltsToValue +#define AUXADCMicrovoltsToValue ROM_AUXADCMicrovoltsToValue #endif #ifdef ROM_AUXADCAdjustValueForGainAndOffset -#undef AUXADCAdjustValueForGainAndOffset +#undef AUXADCAdjustValueForGainAndOffset #define AUXADCAdjustValueForGainAndOffset ROM_AUXADCAdjustValueForGainAndOffset #endif #ifdef ROM_AUXADCUnadjustValueForGainAndOffset -#undef AUXADCUnadjustValueForGainAndOffset +#undef AUXADCUnadjustValueForGainAndOffset #define AUXADCUnadjustValueForGainAndOffset ROM_AUXADCUnadjustValueForGainAndOffset #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_smph.h index a83b619..d2c25b4 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_smph.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_smph.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aux_smph.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the AUX Semaphore -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aux_smph.h + * Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) + * Revision: 47343 + * + * Description: Defines and prototypes for the AUX Semaphore + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,24 +55,23 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" #include "../inc/hw_aux_smph.h" #include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "debug.h" +#include +#include //***************************************************************************** // // General constants and defines // //***************************************************************************** -#define AUX_SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed -#define AUX_SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed +#define AUX_SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed +#define AUX_SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed //***************************************************************************** // @@ -80,14 +79,14 @@ extern "C" // as the ui32Semaphore parameter. // //***************************************************************************** -#define AUX_SMPH_0 0 // AUX Semaphore 0 -#define AUX_SMPH_1 1 // AUX Semaphore 1 -#define AUX_SMPH_2 2 // AUX Semaphore 2 -#define AUX_SMPH_3 3 // AUX Semaphore 3 -#define AUX_SMPH_4 4 // AUX Semaphore 4 -#define AUX_SMPH_5 5 // AUX Semaphore 5 -#define AUX_SMPH_6 6 // AUX Semaphore 6 -#define AUX_SMPH_7 7 // AUX Semaphore 7 +#define AUX_SMPH_0 0 // AUX Semaphore 0 +#define AUX_SMPH_1 1 // AUX Semaphore 1 +#define AUX_SMPH_2 2 // AUX Semaphore 2 +#define AUX_SMPH_3 3 // AUX Semaphore 3 +#define AUX_SMPH_4 4 // AUX Semaphore 4 +#define AUX_SMPH_5 5 // AUX Semaphore 5 +#define AUX_SMPH_6 6 // AUX Semaphore 6 +#define AUX_SMPH_7 7 // AUX Semaphore 7 //***************************************************************************** // @@ -138,7 +137,7 @@ AUXSMPHAcquire(uint32_t ui32Semaphore) // Semaphore register reads 1 when lock was acquired otherwise 0 // (i.e. AUX_SMPH_CLAIMED). while (HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore) == - AUX_SMPH_CLAIMED) + AUX_SMPH_CLAIMED) { } } diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_tdc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_tdc.h index 4a6691c..ebb205b 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_tdc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_tdc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aux_tdc.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Defines and prototypes for the AUX Time-to-Digital Converter -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aux_tdc.h + * Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) + * Revision: 49096 + * + * Description: Defines and prototypes for the AUX Time-to-Digital Converter + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,17 +55,16 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aux_tdc.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_aux_tdc.h" -#include "debug.h" //***************************************************************************** // @@ -81,8 +80,8 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AUXTDCConfigSet NOROM_AUXTDCConfigSet -#define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone +#define AUXTDCConfigSet NOROM_AUXTDCConfigSet +#define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone #endif //***************************************************************************** @@ -90,132 +89,132 @@ extern "C" // Defines for the status of a AUX TDC measurement. // //***************************************************************************** -#define AUX_TDC_BUSY 0x00000001 -#define AUX_TDC_TIMEOUT 0x00000002 -#define AUX_TDC_DONE 0x00000004 +#define AUX_TDC_BUSY 0x00000001 +#define AUX_TDC_TIMEOUT 0x00000002 +#define AUX_TDC_DONE 0x00000004 //***************************************************************************** // // Defines for the control of a AUX TDC. // //***************************************************************************** -#define AUX_TDC_RUNSYNC 0x00000001 -#define AUX_TDC_RUN 0x00000002 -#define AUX_TDC_ABORT 0x00000003 +#define AUX_TDC_RUNSYNC 0x00000001 +#define AUX_TDC_RUN 0x00000002 +#define AUX_TDC_ABORT 0x00000003 //***************************************************************************** // // Defines for possible states of the TDC internal state machine. // //***************************************************************************** -#define AUXTDC_WAIT_START (AUX_TDC_STAT_STATE_WAIT_START) -#define AUXTDC_WAIT_START_CNTEN (AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN) -#define AUXTDC_IDLE (AUX_TDC_STAT_STATE_IDLE) -#define AUXTDC_CLRCNT (AUX_TDC_STAT_STATE_CLR_CNT) -#define AUXTDC_WAIT_STOP (AUX_TDC_STAT_STATE_WAIT_STOP) -#define AUXTDC_WAIT_STOP_CNTDOWN (AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN) -#define AUXTDC_GETRESULTS (AUX_TDC_STAT_STATE_GET_RESULT) -#define AUXTDC_POR (AUX_TDC_STAT_STATE_POR) -#define AUXTDC_WAIT_CLRCNT_DONE (AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE) -#define AUXTDC_START_FALL (AUX_TDC_STAT_STATE_START_FALL) -#define AUXTDC_FORCE_STOP (AUX_TDC_STAT_STATE_FORCE_STOP) +#define AUXTDC_WAIT_START (AUX_TDC_STAT_STATE_WAIT_START) +#define AUXTDC_WAIT_START_CNTEN (AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN) +#define AUXTDC_IDLE (AUX_TDC_STAT_STATE_IDLE) +#define AUXTDC_CLRCNT (AUX_TDC_STAT_STATE_CLR_CNT) +#define AUXTDC_WAIT_STOP (AUX_TDC_STAT_STATE_WAIT_STOP) +#define AUXTDC_WAIT_STOP_CNTDOWN (AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN) +#define AUXTDC_GETRESULTS (AUX_TDC_STAT_STATE_GET_RESULT) +#define AUXTDC_POR (AUX_TDC_STAT_STATE_POR) +#define AUXTDC_WAIT_CLRCNT_DONE (AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE) +#define AUXTDC_START_FALL (AUX_TDC_STAT_STATE_START_FALL) +#define AUXTDC_FORCE_STOP (AUX_TDC_STAT_STATE_FORCE_STOP) //***************************************************************************** // // Defines for controlling the AUX TDC. Values can be passed to AUXTDCConfigSet(). // //***************************************************************************** -#define AUXTDC_STOPPOL_RIS (AUX_TDC_TRIGSRC_STOP_POL_HIGH) // Rising edge polarity for stop event -#define AUXTDC_STOPPOL_FALL (AUX_TDC_TRIGSRC_STOP_POL_LOW) // Falling edge polarity for stop event +#define AUXTDC_STOPPOL_RIS (AUX_TDC_TRIGSRC_STOP_POL_HIGH) // Rising edge polarity for stop event +#define AUXTDC_STOPPOL_FALL (AUX_TDC_TRIGSRC_STOP_POL_LOW) // Falling edge polarity for stop event -#define AUXTDC_STOP_AUXIO0 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0) -#define AUXTDC_STOP_AUXIO1 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1) -#define AUXTDC_STOP_AUXIO2 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2) -#define AUXTDC_STOP_AUXIO3 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3) -#define AUXTDC_STOP_AUXIO4 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4) -#define AUXTDC_STOP_AUXIO5 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5) -#define AUXTDC_STOP_AUXIO6 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6) -#define AUXTDC_STOP_AUXIO7 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7) -#define AUXTDC_STOP_AUXIO8 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8) -#define AUXTDC_STOP_AUXIO9 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9) -#define AUXTDC_STOP_AUXIO10 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10) -#define AUXTDC_STOP_AUXIO11 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11) -#define AUXTDC_STOP_AUXIO12 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12) -#define AUXTDC_STOP_AUXIO13 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13) -#define AUXTDC_STOP_AUXIO14 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14) -#define AUXTDC_STOP_AUXIO15 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15) -#define AUXTDC_STOP_ADC_DONE (AUX_TDC_TRIGSRC_STOP_SRC_ADC_DONE) -#define AUXTDC_STOP_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_STOP_SRC_ADC_FIFO_ALMOST_FULL) -#define AUXTDC_STOP_AON_PROG_WU (AUX_TDC_TRIGSRC_STOP_SRC_AON_PROG_WU) -#define AUXTDC_STOP_AON_SW (AUX_TDC_TRIGSRC_STOP_SRC_AON_SW) -#define AUXTDC_STOP_ISRC_RESET (AUX_TDC_TRIGSRC_STOP_SRC_ISRC_RESET) -#define AUXTDC_STOP_OBSMUX0 (AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX0) -#define AUXTDC_STOP_OBSMUX1 (AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX1) -#define AUXTDC_STOP_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_STOP_SRC_SMPH_AUTOTAKE_DONE) -#define AUXTDC_STOP_TDC_PRE (AUX_TDC_TRIGSRC_STOP_SRC_TDC_PRE) -#define AUXTDC_STOP_TIMER0_EV (AUX_TDC_TRIGSRC_STOP_SRC_TIMER0_EV) -#define AUXTDC_STOP_TIMER1_EV (AUX_TDC_TRIGSRC_STOP_SRC_TIMER1_EV) -#define AUXTDC_STOP_AON_RTC_CH2 (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2) -#define AUXTDC_STOP_AUX_COMPA (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA) -#define AUXTDC_STOP_AUX_COMPB (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB) -#define AUXTDC_STOP_ACLK_REF (AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF) -#define AUXTDC_STOP_MCU_EV (AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV) +#define AUXTDC_STOP_AUXIO0 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0) +#define AUXTDC_STOP_AUXIO1 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1) +#define AUXTDC_STOP_AUXIO2 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2) +#define AUXTDC_STOP_AUXIO3 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3) +#define AUXTDC_STOP_AUXIO4 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4) +#define AUXTDC_STOP_AUXIO5 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5) +#define AUXTDC_STOP_AUXIO6 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6) +#define AUXTDC_STOP_AUXIO7 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7) +#define AUXTDC_STOP_AUXIO8 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8) +#define AUXTDC_STOP_AUXIO9 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9) +#define AUXTDC_STOP_AUXIO10 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10) +#define AUXTDC_STOP_AUXIO11 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11) +#define AUXTDC_STOP_AUXIO12 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12) +#define AUXTDC_STOP_AUXIO13 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13) +#define AUXTDC_STOP_AUXIO14 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14) +#define AUXTDC_STOP_AUXIO15 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15) +#define AUXTDC_STOP_ADC_DONE (AUX_TDC_TRIGSRC_STOP_SRC_ADC_DONE) +#define AUXTDC_STOP_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_STOP_SRC_ADC_FIFO_ALMOST_FULL) +#define AUXTDC_STOP_AON_PROG_WU (AUX_TDC_TRIGSRC_STOP_SRC_AON_PROG_WU) +#define AUXTDC_STOP_AON_SW (AUX_TDC_TRIGSRC_STOP_SRC_AON_SW) +#define AUXTDC_STOP_ISRC_RESET (AUX_TDC_TRIGSRC_STOP_SRC_ISRC_RESET) +#define AUXTDC_STOP_OBSMUX0 (AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX0) +#define AUXTDC_STOP_OBSMUX1 (AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX1) +#define AUXTDC_STOP_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_STOP_SRC_SMPH_AUTOTAKE_DONE) +#define AUXTDC_STOP_TDC_PRE (AUX_TDC_TRIGSRC_STOP_SRC_TDC_PRE) +#define AUXTDC_STOP_TIMER0_EV (AUX_TDC_TRIGSRC_STOP_SRC_TIMER0_EV) +#define AUXTDC_STOP_TIMER1_EV (AUX_TDC_TRIGSRC_STOP_SRC_TIMER1_EV) +#define AUXTDC_STOP_AON_RTC_CH2 (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2) +#define AUXTDC_STOP_AUX_COMPA (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA) +#define AUXTDC_STOP_AUX_COMPB (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB) +#define AUXTDC_STOP_ACLK_REF (AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF) +#define AUXTDC_STOP_MCU_EV (AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV) -#define AUXTDC_STARTPOL_RIS (AUX_TDC_TRIGSRC_START_POL_HIGH) // Rising edge polarity for start event -#define AUXTDC_STARTPOL_FALL (AUX_TDC_TRIGSRC_START_POL_LOW) // Falling edge polarity for start event +#define AUXTDC_STARTPOL_RIS (AUX_TDC_TRIGSRC_START_POL_HIGH) // Rising edge polarity for start event +#define AUXTDC_STARTPOL_FALL (AUX_TDC_TRIGSRC_START_POL_LOW) // Falling edge polarity for start event -#define AUXTDC_START_AUXIO0 (AUX_TDC_TRIGSRC_START_SRC_AUXIO0) -#define AUXTDC_START_AUXIO1 (AUX_TDC_TRIGSRC_START_SRC_AUXIO1) -#define AUXTDC_START_AUXIO2 (AUX_TDC_TRIGSRC_START_SRC_AUXIO2) -#define AUXTDC_START_AUXIO3 (AUX_TDC_TRIGSRC_START_SRC_AUXIO3) -#define AUXTDC_START_AUXIO4 (AUX_TDC_TRIGSRC_START_SRC_AUXIO4) -#define AUXTDC_START_AUXIO5 (AUX_TDC_TRIGSRC_START_SRC_AUXIO5) -#define AUXTDC_START_AUXIO6 (AUX_TDC_TRIGSRC_START_SRC_AUXIO6) -#define AUXTDC_START_AUXIO7 (AUX_TDC_TRIGSRC_START_SRC_AUXIO7) -#define AUXTDC_START_AUXIO8 (AUX_TDC_TRIGSRC_START_SRC_AUXIO8) -#define AUXTDC_START_AUXIO9 (AUX_TDC_TRIGSRC_START_SRC_AUXIO9) -#define AUXTDC_START_AUXIO10 (AUX_TDC_TRIGSRC_START_SRC_AUXIO10) -#define AUXTDC_START_AUXIO11 (AUX_TDC_TRIGSRC_START_SRC_AUXIO11) -#define AUXTDC_START_AUXIO12 (AUX_TDC_TRIGSRC_START_SRC_AUXIO12) -#define AUXTDC_START_AUXIO13 (AUX_TDC_TRIGSRC_START_SRC_AUXIO13) -#define AUXTDC_START_AUXIO14 (AUX_TDC_TRIGSRC_START_SRC_AUXIO14) -#define AUXTDC_START_AUXIO15 (AUX_TDC_TRIGSRC_START_SRC_AUXIO15) -#define AUXTDC_START_ADC_DONE (AUX_TDC_TRIGSRC_START_SRC_ADC_DONE) +#define AUXTDC_START_AUXIO0 (AUX_TDC_TRIGSRC_START_SRC_AUXIO0) +#define AUXTDC_START_AUXIO1 (AUX_TDC_TRIGSRC_START_SRC_AUXIO1) +#define AUXTDC_START_AUXIO2 (AUX_TDC_TRIGSRC_START_SRC_AUXIO2) +#define AUXTDC_START_AUXIO3 (AUX_TDC_TRIGSRC_START_SRC_AUXIO3) +#define AUXTDC_START_AUXIO4 (AUX_TDC_TRIGSRC_START_SRC_AUXIO4) +#define AUXTDC_START_AUXIO5 (AUX_TDC_TRIGSRC_START_SRC_AUXIO5) +#define AUXTDC_START_AUXIO6 (AUX_TDC_TRIGSRC_START_SRC_AUXIO6) +#define AUXTDC_START_AUXIO7 (AUX_TDC_TRIGSRC_START_SRC_AUXIO7) +#define AUXTDC_START_AUXIO8 (AUX_TDC_TRIGSRC_START_SRC_AUXIO8) +#define AUXTDC_START_AUXIO9 (AUX_TDC_TRIGSRC_START_SRC_AUXIO9) +#define AUXTDC_START_AUXIO10 (AUX_TDC_TRIGSRC_START_SRC_AUXIO10) +#define AUXTDC_START_AUXIO11 (AUX_TDC_TRIGSRC_START_SRC_AUXIO11) +#define AUXTDC_START_AUXIO12 (AUX_TDC_TRIGSRC_START_SRC_AUXIO12) +#define AUXTDC_START_AUXIO13 (AUX_TDC_TRIGSRC_START_SRC_AUXIO13) +#define AUXTDC_START_AUXIO14 (AUX_TDC_TRIGSRC_START_SRC_AUXIO14) +#define AUXTDC_START_AUXIO15 (AUX_TDC_TRIGSRC_START_SRC_AUXIO15) +#define AUXTDC_START_ADC_DONE (AUX_TDC_TRIGSRC_START_SRC_ADC_DONE) #define AUXTDC_START_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_START_SRC_ADC_FIFO_ALMOST_FULL) -#define AUXTDC_START_AON_PROG_WU (AUX_TDC_TRIGSRC_START_SRC_AON_PROG_WU) -#define AUXTDC_START_AON_SW (AUX_TDC_TRIGSRC_START_SRC_AON_SW) -#define AUXTDC_START_ISRC_RESET (AUX_TDC_TRIGSRC_START_SRC_ISRC_RESET) -#define AUXTDC_START_OBSMUX0 (AUX_TDC_TRIGSRC_START_SRC_OBSMUX0) -#define AUXTDC_START_OBSMUX1 (AUX_TDC_TRIGSRC_START_SRC_OBSMUX1) -#define AUXTDC_START_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_START_SRC_SMPH_AUTOTAKE_DONE) -#define AUXTDC_START_TDC_PRE (AUX_TDC_TRIGSRC_START_SRC_TDC_PRE) -#define AUXTDC_START_TIMER0_EV (AUX_TDC_TRIGSRC_START_SRC_TIMER0_EV) -#define AUXTDC_START_TIMER1_EV (AUX_TDC_TRIGSRC_START_SRC_TIMER1_EV) -#define AUXTDC_START_AON_RTC_CH2 (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2) -#define AUXTDC_START_AUX_COMPA (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA) -#define AUXTDC_START_AUX_COMPB (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB) -#define AUXTDC_START_ACLK_REF (AUX_TDC_TRIGSRC_START_SRC_ACLK_REF) -#define AUXTDC_START_MCU_EV (AUX_TDC_TRIGSRC_START_SRC_MCU_EV) +#define AUXTDC_START_AON_PROG_WU (AUX_TDC_TRIGSRC_START_SRC_AON_PROG_WU) +#define AUXTDC_START_AON_SW (AUX_TDC_TRIGSRC_START_SRC_AON_SW) +#define AUXTDC_START_ISRC_RESET (AUX_TDC_TRIGSRC_START_SRC_ISRC_RESET) +#define AUXTDC_START_OBSMUX0 (AUX_TDC_TRIGSRC_START_SRC_OBSMUX0) +#define AUXTDC_START_OBSMUX1 (AUX_TDC_TRIGSRC_START_SRC_OBSMUX1) +#define AUXTDC_START_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_START_SRC_SMPH_AUTOTAKE_DONE) +#define AUXTDC_START_TDC_PRE (AUX_TDC_TRIGSRC_START_SRC_TDC_PRE) +#define AUXTDC_START_TIMER0_EV (AUX_TDC_TRIGSRC_START_SRC_TIMER0_EV) +#define AUXTDC_START_TIMER1_EV (AUX_TDC_TRIGSRC_START_SRC_TIMER1_EV) +#define AUXTDC_START_AON_RTC_CH2 (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2) +#define AUXTDC_START_AUX_COMPA (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA) +#define AUXTDC_START_AUX_COMPB (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB) +#define AUXTDC_START_ACLK_REF (AUX_TDC_TRIGSRC_START_SRC_ACLK_REF) +#define AUXTDC_START_MCU_EV (AUX_TDC_TRIGSRC_START_SRC_MCU_EV) //***************************************************************************** // // Defines for the possible saturation values set using AUXTDCLimitSet(). // //***************************************************************************** -#define AUXTDC_SAT_4096 (AUX_TDC_SATCFG_LIMIT_R12) -#define AUXTDC_SAT_8192 (AUX_TDC_SATCFG_LIMIT_R13) -#define AUXTDC_SAT_16384 (AUX_TDC_SATCFG_LIMIT_R14) -#define AUXTDC_SAT_32768 (AUX_TDC_SATCFG_LIMIT_R15) -#define AUXTDC_SAT_65536 (AUX_TDC_SATCFG_LIMIT_R16) -#define AUXTDC_SAT_131072 (AUX_TDC_SATCFG_LIMIT_R17) -#define AUXTDC_SAT_262144 (AUX_TDC_SATCFG_LIMIT_R18) -#define AUXTDC_SAT_524288 (AUX_TDC_SATCFG_LIMIT_R19) -#define AUXTDC_SAT_1048576 (AUX_TDC_SATCFG_LIMIT_R20) -#define AUXTDC_SAT_2097152 (AUX_TDC_SATCFG_LIMIT_R21) -#define AUXTDC_SAT_4194304 (AUX_TDC_SATCFG_LIMIT_R22) -#define AUXTDC_SAT_8388608 (AUX_TDC_SATCFG_LIMIT_R23) -#define AUXTDC_SAT_16777216 (AUX_TDC_SATCFG_LIMIT_R24) -#define AUXTDC_NUM_SAT_VALS 16 +#define AUXTDC_SAT_4096 (AUX_TDC_SATCFG_LIMIT_R12) +#define AUXTDC_SAT_8192 (AUX_TDC_SATCFG_LIMIT_R13) +#define AUXTDC_SAT_16384 (AUX_TDC_SATCFG_LIMIT_R14) +#define AUXTDC_SAT_32768 (AUX_TDC_SATCFG_LIMIT_R15) +#define AUXTDC_SAT_65536 (AUX_TDC_SATCFG_LIMIT_R16) +#define AUXTDC_SAT_131072 (AUX_TDC_SATCFG_LIMIT_R17) +#define AUXTDC_SAT_262144 (AUX_TDC_SATCFG_LIMIT_R18) +#define AUXTDC_SAT_524288 (AUX_TDC_SATCFG_LIMIT_R19) +#define AUXTDC_SAT_1048576 (AUX_TDC_SATCFG_LIMIT_R20) +#define AUXTDC_SAT_2097152 (AUX_TDC_SATCFG_LIMIT_R21) +#define AUXTDC_SAT_4194304 (AUX_TDC_SATCFG_LIMIT_R22) +#define AUXTDC_SAT_8388608 (AUX_TDC_SATCFG_LIMIT_R23) +#define AUXTDC_SAT_16777216 (AUX_TDC_SATCFG_LIMIT_R24) +#define AUXTDC_NUM_SAT_VALS 16 //***************************************************************************** // @@ -399,7 +398,9 @@ AUXTDCIdle(uint32_t ui32Base) // Check if the AUX TDC is in the Idle state. return (((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE) ? true : false); + AUX_TDC_STAT_STATE_IDLE) + ? true + : false); } //***************************************************************************** @@ -621,7 +622,7 @@ AUXTDCCounterEnable(uint32_t ui32Base) // Check if the AUX TDC is in idle mode. If not in Idle mode, the counter // will not be enabled. if (!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE)) + AUX_TDC_STAT_STATE_IDLE)) { return false; } @@ -657,7 +658,7 @@ AUXTDCCounterDisable(uint32_t ui32Base) // Check if the AUX TDC is in Idle mode. If not in Idle mode, the counter // will not be disabled. if (!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE)) + AUX_TDC_STAT_STATE_IDLE)) { return false; } @@ -698,7 +699,7 @@ AUXTDCCounterSet(uint32_t ui32Base, uint32_t ui32Events) // Check if the AUX TDC is in idle mode. If not in idle mode, the counter // will not be disabled. if (!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE)) + AUX_TDC_STAT_STATE_IDLE)) { return false; } @@ -747,12 +748,12 @@ AUXTDCCounterGet(uint32_t ui32Base) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AUXTDCConfigSet -#undef AUXTDCConfigSet -#define AUXTDCConfigSet ROM_AUXTDCConfigSet +#undef AUXTDCConfigSet +#define AUXTDCConfigSet ROM_AUXTDCConfigSet #endif #ifdef ROM_AUXTDCMeasurementDone -#undef AUXTDCMeasurementDone -#define AUXTDCMeasurementDone ROM_AUXTDCMeasurementDone +#undef AUXTDCMeasurementDone +#define AUXTDCMeasurementDone ROM_AUXTDCMeasurementDone #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_timer.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_timer.h index 45289b7..f9f4a2b 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_timer.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_timer.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aux_timer.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Defines and prototypes for the AUX Timer -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aux_timer.h + * Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) + * Revision: 49096 + * + * Description: Defines and prototypes for the AUX Timer + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,18 +55,17 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" +#include "../inc/hw_aux_timer.h" #include "../inc/hw_ints.h" #include "../inc/hw_memmap.h" -#include "../inc/hw_aux_timer.h" +#include "../inc/hw_types.h" #include "debug.h" #include "interrupt.h" +#include +#include //***************************************************************************** // @@ -82,11 +81,11 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AUXTimerConfigure NOROM_AUXTimerConfigure -#define AUXTimerStart NOROM_AUXTimerStart -#define AUXTimerStop NOROM_AUXTimerStop -#define AUXTimerPrescaleSet NOROM_AUXTimerPrescaleSet -#define AUXTimerPrescaleGet NOROM_AUXTimerPrescaleGet +#define AUXTimerConfigure NOROM_AUXTimerConfigure +#define AUXTimerStart NOROM_AUXTimerStart +#define AUXTimerStop NOROM_AUXTimerStop +#define AUXTimerPrescaleSet NOROM_AUXTimerPrescaleSet +#define AUXTimerPrescaleGet NOROM_AUXTimerPrescaleGet #endif //***************************************************************************** @@ -94,45 +93,45 @@ extern "C" // Values that can be passed to AUXTimerConfigure(). // //***************************************************************************** -#define AUX_TIMER_CFG_ONE_SHOT (AUX_TIMER_T0CFG_RELOAD_MAN) // One-shot timer mode -#define AUX_TIMER_CFG_PERIODIC (AUX_TIMER_T0CFG_RELOAD_CONT) // Period timer mode -#define AUX_TIMER_CFG_ONE_SHOT_EDGE_COUNT ((AUX_TIMER_T0CFG_RELOAD_MAN) | (AUX_TIMER_T0CFG_MODE_TICK)) // One-shot timer with edge count -#define AUX_TIMER_CFG_PERIODIC_EDGE_COUNT ((AUX_TIMER_T0CFG_RELOAD_CONT) | (AUX_TIMER_T0CFG_MODE_TICK)) // Periodic timer with edge count -#define AUX_TIMER_CFG_RISING_EDGE (AUX_TIMER_T0CFG_TICK_SRC_POL_RISE) // Count rising edges (used with edge count mode) -#define AUX_TIMER_CFG_FALLING_EDGE (AUX_TIMER_T0CFG_TICK_SRC_POL_FALL) // Count falling edges (used with edge count mode) +#define AUX_TIMER_CFG_ONE_SHOT (AUX_TIMER_T0CFG_RELOAD_MAN) // One-shot timer mode +#define AUX_TIMER_CFG_PERIODIC (AUX_TIMER_T0CFG_RELOAD_CONT) // Period timer mode +#define AUX_TIMER_CFG_ONE_SHOT_EDGE_COUNT ((AUX_TIMER_T0CFG_RELOAD_MAN) | (AUX_TIMER_T0CFG_MODE_TICK)) // One-shot timer with edge count +#define AUX_TIMER_CFG_PERIODIC_EDGE_COUNT ((AUX_TIMER_T0CFG_RELOAD_CONT) | (AUX_TIMER_T0CFG_MODE_TICK)) // Periodic timer with edge count +#define AUX_TIMER_CFG_RISING_EDGE (AUX_TIMER_T0CFG_TICK_SRC_POL_RISE) // Count rising edges (used with edge count mode) +#define AUX_TIMER_CFG_FALLING_EDGE (AUX_TIMER_T0CFG_TICK_SRC_POL_FALL) // Count falling edges (used with edge count mode) -#define AUX_TIMER_CFG_TICK_SRC_RTC_EVENT (AUX_TIMER_T0CFG_TICK_SRC_RTC_CH2_EV) // AON wake-up event -#define AUX_TIMER_CFG_TICK_SRC_CMP_A (AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPA) // Comparator A -#define AUX_TIMER_CFG_TICK_SRC_CMP_B (AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPB) // Comparator B -#define AUX_TIMER_CFG_TICK_SRC_TDCDONE (AUX_TIMER_T0CFG_TICK_SRC_TDC_DONE) // TDC Done -#define AUX_TIMER_CFG_TICK_SRC_TIMER0_EVENT (AUX_TIMER_T1CFG_TICK_SRC_TIMER0_EV) // Timer 0 event -#define AUX_TIMER_CFG_TICK_SRC_TIMER1_EVENT (AUX_TIMER_T0CFG_TICK_SRC_TIMER1_EV) // Timer 1 event +#define AUX_TIMER_CFG_TICK_SRC_RTC_EVENT (AUX_TIMER_T0CFG_TICK_SRC_RTC_CH2_EV) // AON wake-up event +#define AUX_TIMER_CFG_TICK_SRC_CMP_A (AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPA) // Comparator A +#define AUX_TIMER_CFG_TICK_SRC_CMP_B (AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPB) // Comparator B +#define AUX_TIMER_CFG_TICK_SRC_TDCDONE (AUX_TIMER_T0CFG_TICK_SRC_TDC_DONE) // TDC Done +#define AUX_TIMER_CFG_TICK_SRC_TIMER0_EVENT (AUX_TIMER_T1CFG_TICK_SRC_TIMER0_EV) // Timer 0 event +#define AUX_TIMER_CFG_TICK_SRC_TIMER1_EVENT (AUX_TIMER_T0CFG_TICK_SRC_TIMER1_EV) // Timer 1 event #define AUX_TIMER_CFG_TICK_SRC_SMPH_RELEASE (AUX_TIMER_T0CFG_TICK_SRC_SMPH_AUTOTAKE_DONE) // Semaphore release -#define AUX_TIMER_CFG_TICK_SRC_ADC_DONE (AUX_TIMER_T0CFG_TICK_SRC_ADC_DONE) // ADC done -#define AUX_TIMER_CFG_TICK_SRC_RTC_4KHZ (AUX_TIMER_T0CFG_TICK_SRC_RTC_4KHZ) -#define AUX_TIMER_CFG_TICK_SRC_OBSMUX0 (AUX_TIMER_T0CFG_TICK_SRC_OBSMUX0) -#define AUX_TIMER_CFG_TICK_SRC_OBSMUX1 (AUX_TIMER_T0CFG_TICK_SRC_OBSMUX1) -#define AUX_TIMER_CFG_TICK_SRC_AON_SW (AUX_TIMER_T0CFG_TICK_SRC_AON_SW) -#define AUX_TIMER_CFG_TICK_SRC_AON_PROG_WU (AUX_TIMER_T0CFG_TICK_SRC_AON_PROG_WU) -#define AUX_TIMER_CFG_TICK_SRC_AIO0 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO0) // AIO_DAT[ 0] -#define AUX_TIMER_CFG_TICK_SRC_AIO1 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO1) // AIO_DAT[ 1] -#define AUX_TIMER_CFG_TICK_SRC_AIO2 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO2) // AIO_DAT[ 2] -#define AUX_TIMER_CFG_TICK_SRC_AIO3 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO3) // AIO_DAT[ 3] -#define AUX_TIMER_CFG_TICK_SRC_AIO4 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO4) // AIO_DAT[ 4] -#define AUX_TIMER_CFG_TICK_SRC_AIO5 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO5) // AIO_DAT[ 5] -#define AUX_TIMER_CFG_TICK_SRC_AIO6 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO6) // AIO_DAT[ 6] -#define AUX_TIMER_CFG_TICK_SRC_AIO7 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO7) // AIO_DAT[ 7] -#define AUX_TIMER_CFG_TICK_SRC_AIO8 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO8) // AIO_DAT[ 8] -#define AUX_TIMER_CFG_TICK_SRC_AIO9 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO9) // AIO_DAT[ 9] -#define AUX_TIMER_CFG_TICK_SRC_AIO10 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO10) // AIO_DAT[10] -#define AUX_TIMER_CFG_TICK_SRC_AIO11 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO11) // AIO_DAT[11] -#define AUX_TIMER_CFG_TICK_SRC_AIO12 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO12) // AIO_DAT[12] -#define AUX_TIMER_CFG_TICK_SRC_AIO13 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO13) // AIO_DAT[13] -#define AUX_TIMER_CFG_TICK_SRC_AIO14 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO14) // AIO_DAT[14] -#define AUX_TIMER_CFG_TICK_SRC_AIO15 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO15) // AIO_DAT[15] -#define AUX_TIMER_CFG_TICK_SRC_ACLK_REF (AUX_TIMER_T0CFG_TICK_SRC_ACLK_REF) // ACLK_REF_i -#define AUX_TIMER_CFG_TICK_SRC_MCU_EVENT (AUX_TIMER_T0CFG_TICK_SRC_MCU_EVENT) // MCU event -#define AUX_TIMER_CFG_TICK_SRC_ADC_IRQ (AUX_TIMER_T0CFG_TICK_SRC_ADC_IRQ) // DMA done +#define AUX_TIMER_CFG_TICK_SRC_ADC_DONE (AUX_TIMER_T0CFG_TICK_SRC_ADC_DONE) // ADC done +#define AUX_TIMER_CFG_TICK_SRC_RTC_4KHZ (AUX_TIMER_T0CFG_TICK_SRC_RTC_4KHZ) +#define AUX_TIMER_CFG_TICK_SRC_OBSMUX0 (AUX_TIMER_T0CFG_TICK_SRC_OBSMUX0) +#define AUX_TIMER_CFG_TICK_SRC_OBSMUX1 (AUX_TIMER_T0CFG_TICK_SRC_OBSMUX1) +#define AUX_TIMER_CFG_TICK_SRC_AON_SW (AUX_TIMER_T0CFG_TICK_SRC_AON_SW) +#define AUX_TIMER_CFG_TICK_SRC_AON_PROG_WU (AUX_TIMER_T0CFG_TICK_SRC_AON_PROG_WU) +#define AUX_TIMER_CFG_TICK_SRC_AIO0 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO0) // AIO_DAT[ 0] +#define AUX_TIMER_CFG_TICK_SRC_AIO1 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO1) // AIO_DAT[ 1] +#define AUX_TIMER_CFG_TICK_SRC_AIO2 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO2) // AIO_DAT[ 2] +#define AUX_TIMER_CFG_TICK_SRC_AIO3 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO3) // AIO_DAT[ 3] +#define AUX_TIMER_CFG_TICK_SRC_AIO4 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO4) // AIO_DAT[ 4] +#define AUX_TIMER_CFG_TICK_SRC_AIO5 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO5) // AIO_DAT[ 5] +#define AUX_TIMER_CFG_TICK_SRC_AIO6 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO6) // AIO_DAT[ 6] +#define AUX_TIMER_CFG_TICK_SRC_AIO7 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO7) // AIO_DAT[ 7] +#define AUX_TIMER_CFG_TICK_SRC_AIO8 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO8) // AIO_DAT[ 8] +#define AUX_TIMER_CFG_TICK_SRC_AIO9 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO9) // AIO_DAT[ 9] +#define AUX_TIMER_CFG_TICK_SRC_AIO10 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO10) // AIO_DAT[10] +#define AUX_TIMER_CFG_TICK_SRC_AIO11 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO11) // AIO_DAT[11] +#define AUX_TIMER_CFG_TICK_SRC_AIO12 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO12) // AIO_DAT[12] +#define AUX_TIMER_CFG_TICK_SRC_AIO13 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO13) // AIO_DAT[13] +#define AUX_TIMER_CFG_TICK_SRC_AIO14 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO14) // AIO_DAT[14] +#define AUX_TIMER_CFG_TICK_SRC_AIO15 (AUX_TIMER_T0CFG_TICK_SRC_AUXIO15) // AIO_DAT[15] +#define AUX_TIMER_CFG_TICK_SRC_ACLK_REF (AUX_TIMER_T0CFG_TICK_SRC_ACLK_REF) // ACLK_REF_i +#define AUX_TIMER_CFG_TICK_SRC_MCU_EVENT (AUX_TIMER_T0CFG_TICK_SRC_MCU_EVENT) // MCU event +#define AUX_TIMER_CFG_TICK_SRC_ADC_IRQ (AUX_TIMER_T0CFG_TICK_SRC_ADC_IRQ) // DMA done //***************************************************************************** // @@ -140,9 +139,9 @@ extern "C" // parameter. // //***************************************************************************** -#define AUX_TIMER_0 0x0000FFFF // AUX Timer 0 -#define AUX_TIMER_1 0x00FF0000 // AUX Timer 1 -#define AUX_TIMER_BOTH 0x00FFFFFF // AUX Timer Both 0 and 1 +#define AUX_TIMER_0 0x0000FFFF // AUX Timer 0 +#define AUX_TIMER_1 0x00FF0000 // AUX Timer 1 +#define AUX_TIMER_BOTH 0x00FFFFFF // AUX Timer Both 0 and 1 //***************************************************************************** // @@ -150,22 +149,22 @@ extern "C" // AUXTimerPrescaleGet. // //***************************************************************************** -#define AUX_TIMER_PRESCALE_DIV_1 0x00000000 // Prescale division ratio 1 -#define AUX_TIMER_PRESCALE_DIV_2 0x00000001 // Prescale division ratio 2 -#define AUX_TIMER_PRESCALE_DIV_4 0x00000002 // Prescale division ratio 4 -#define AUX_TIMER_PRESCALE_DIV_8 0x00000003 // Prescale division ratio 8 -#define AUX_TIMER_PRESCALE_DIV_16 0x00000004 // Prescale division ratio 16 -#define AUX_TIMER_PRESCALE_DIV_32 0x00000005 // Prescale division ratio 32 -#define AUX_TIMER_PRESCALE_DIV_64 0x00000006 // Prescale division ratio 64 -#define AUX_TIMER_PRESCALE_DIV_128 0x00000007 // Prescale division ratio 128 -#define AUX_TIMER_PRESCALE_DIV_256 0x00000008 // Prescale division ratio 256 -#define AUX_TIMER_PRESCALE_DIV_512 0x00000009 // Prescale division ratio 512 -#define AUX_TIMER_PRESCALE_DIV_1028 0x0000000A // Prescale div. ratio 1028 -#define AUX_TIMER_PRESCALE_DIV_2048 0x0000000B // Prescale div. ratio 2048 -#define AUX_TIMER_PRESCALE_DIV_4096 0x0000000C // Prescale div. ratio 4096 -#define AUX_TIMER_PRESCALE_DIV_8192 0x0000000D // Prescale div. ratio 8192 -#define AUX_TIMER_PRESCALE_DIV_16384 0x0000000E // Prescale div. ratio 16384 -#define AUX_TIMER_PRESCALE_DIV_32768 0x0000000F // Prescale div. ratio 32768 +#define AUX_TIMER_PRESCALE_DIV_1 0x00000000 // Prescale division ratio 1 +#define AUX_TIMER_PRESCALE_DIV_2 0x00000001 // Prescale division ratio 2 +#define AUX_TIMER_PRESCALE_DIV_4 0x00000002 // Prescale division ratio 4 +#define AUX_TIMER_PRESCALE_DIV_8 0x00000003 // Prescale division ratio 8 +#define AUX_TIMER_PRESCALE_DIV_16 0x00000004 // Prescale division ratio 16 +#define AUX_TIMER_PRESCALE_DIV_32 0x00000005 // Prescale division ratio 32 +#define AUX_TIMER_PRESCALE_DIV_64 0x00000006 // Prescale division ratio 64 +#define AUX_TIMER_PRESCALE_DIV_128 0x00000007 // Prescale division ratio 128 +#define AUX_TIMER_PRESCALE_DIV_256 0x00000008 // Prescale division ratio 256 +#define AUX_TIMER_PRESCALE_DIV_512 0x00000009 // Prescale division ratio 512 +#define AUX_TIMER_PRESCALE_DIV_1028 0x0000000A // Prescale div. ratio 1028 +#define AUX_TIMER_PRESCALE_DIV_2048 0x0000000B // Prescale div. ratio 2048 +#define AUX_TIMER_PRESCALE_DIV_4096 0x0000000C // Prescale div. ratio 4096 +#define AUX_TIMER_PRESCALE_DIV_8192 0x0000000D // Prescale div. ratio 8192 +#define AUX_TIMER_PRESCALE_DIV_16384 0x0000000E // Prescale div. ratio 16384 +#define AUX_TIMER_PRESCALE_DIV_32768 0x0000000F // Prescale div. ratio 32768 //***************************************************************************** // @@ -325,9 +324,7 @@ AUXTimerTargetValSet(uint32_t ui32Timer, uint32_t ui32Target) ASSERT(((ui32Timer & AUX_TIMER_0) && (ui32Target <= 65535)) || ((ui32Timer & AUX_TIMER_1) && (ui32Target <= 255))); - ui32Addr = (ui32Timer & AUX_TIMER_0) ? - (AUX_TIMER_BASE + AUX_TIMER_O_T0TARGET) : - (AUX_TIMER_BASE + AUX_TIMER_O_T1TARGET); + ui32Addr = (ui32Timer & AUX_TIMER_0) ? (AUX_TIMER_BASE + AUX_TIMER_O_T0TARGET) : (AUX_TIMER_BASE + AUX_TIMER_O_T1TARGET); HWREG(ui32Addr) = ui32Target; } @@ -355,9 +352,7 @@ AUXTimerTargetValGet(uint32_t ui32Timer) // Check the arguments. ASSERT((ui32Timer == AUX_TIMER_0) || (ui32Timer == AUX_TIMER_1)); - return (HWREG((ui32Timer & AUX_TIMER_0) ? - (AUX_TIMER_BASE + AUX_TIMER_O_T0TARGET) : - (AUX_TIMER_BASE + AUX_TIMER_O_T1TARGET))); + return (HWREG((ui32Timer & AUX_TIMER_0) ? (AUX_TIMER_BASE + AUX_TIMER_O_T0TARGET) : (AUX_TIMER_BASE + AUX_TIMER_O_T1TARGET))); } //***************************************************************************** @@ -441,24 +436,24 @@ extern uint32_t AUXTimerPrescaleGet(uint32_t ui32Timer); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AUXTimerConfigure -#undef AUXTimerConfigure -#define AUXTimerConfigure ROM_AUXTimerConfigure +#undef AUXTimerConfigure +#define AUXTimerConfigure ROM_AUXTimerConfigure #endif #ifdef ROM_AUXTimerStart -#undef AUXTimerStart -#define AUXTimerStart ROM_AUXTimerStart +#undef AUXTimerStart +#define AUXTimerStart ROM_AUXTimerStart #endif #ifdef ROM_AUXTimerStop -#undef AUXTimerStop -#define AUXTimerStop ROM_AUXTimerStop +#undef AUXTimerStop +#define AUXTimerStop ROM_AUXTimerStop #endif #ifdef ROM_AUXTimerPrescaleSet -#undef AUXTimerPrescaleSet -#define AUXTimerPrescaleSet ROM_AUXTimerPrescaleSet +#undef AUXTimerPrescaleSet +#define AUXTimerPrescaleSet ROM_AUXTimerPrescaleSet #endif #ifdef ROM_AUXTimerPrescaleGet -#undef AUXTimerPrescaleGet -#define AUXTimerPrescaleGet ROM_AUXTimerPrescaleGet +#undef AUXTimerPrescaleGet +#define AUXTimerPrescaleGet ROM_AUXTimerPrescaleGet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_wuc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_wuc.h index a812536..f05b4f8 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_wuc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/aux_wuc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: aon_wuc.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Defines and prototypes for the AUX Wakeup Controller -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: aon_wuc.h + * Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) + * Revision: 49096 + * + * Description: Defines and prototypes for the AUX Wakeup Controller + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //**************************************************************************** // @@ -55,16 +55,15 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aux_wuc.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aux_wuc.h" -#include "debug.h" //***************************************************************************** // @@ -80,10 +79,10 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define AUXWUCClockEnable NOROM_AUXWUCClockEnable -#define AUXWUCClockDisable NOROM_AUXWUCClockDisable -#define AUXWUCClockStatus NOROM_AUXWUCClockStatus -#define AUXWUCPowerCtrl NOROM_AUXWUCPowerCtrl +#define AUXWUCClockEnable NOROM_AUXWUCClockEnable +#define AUXWUCClockDisable NOROM_AUXWUCClockDisable +#define AUXWUCClockStatus NOROM_AUXWUCClockStatus +#define AUXWUCPowerCtrl NOROM_AUXWUCPowerCtrl #endif //***************************************************************************** @@ -91,35 +90,35 @@ extern "C" // Defines for the AUX power control. // //***************************************************************************** -#define AUX_WUC_POWER_OFF 0x00000001 -#define AUX_WUC_POWER_DOWN 0x00000002 -#define AUX_WUC_POWER_ACTIVE 0x00000004 +#define AUX_WUC_POWER_OFF 0x00000001 +#define AUX_WUC_POWER_DOWN 0x00000002 +#define AUX_WUC_POWER_ACTIVE 0x00000004 //***************************************************************************** // // Defines for the AUX peripherals clock control. // //***************************************************************************** -#define AUX_WUC_SMPH_CLOCK (AUX_WUC_MODCLKEN0_SMPH_EN) -#define AUX_WUC_AIODIO0_CLOCK (AUX_WUC_MODCLKEN0_AIODIO0_EN) -#define AUX_WUC_AIODIO1_CLOCK (AUX_WUC_MODCLKEN0_AIODIO1_EN) -#define AUX_WUC_TIMER_CLOCK (AUX_WUC_MODCLKEN0_TIMER_EN) -#define AUX_WUC_ANAIF_CLOCK (AUX_WUC_MODCLKEN0_ANAIF_EN) -#define AUX_WUC_TDCIF_CLOCK (AUX_WUC_MODCLKEN0_TDC_EN) -#define AUX_WUC_OSCCTRL_CLOCK (AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_EN) -#define AUX_WUC_ADI_CLOCK (AUX_WUC_MODCLKEN0_AUX_ADI4_EN) -#define AUX_WUC_MODCLK_MASK 0x000000FF +#define AUX_WUC_SMPH_CLOCK (AUX_WUC_MODCLKEN0_SMPH_EN) +#define AUX_WUC_AIODIO0_CLOCK (AUX_WUC_MODCLKEN0_AIODIO0_EN) +#define AUX_WUC_AIODIO1_CLOCK (AUX_WUC_MODCLKEN0_AIODIO1_EN) +#define AUX_WUC_TIMER_CLOCK (AUX_WUC_MODCLKEN0_TIMER_EN) +#define AUX_WUC_ANAIF_CLOCK (AUX_WUC_MODCLKEN0_ANAIF_EN) +#define AUX_WUC_TDCIF_CLOCK (AUX_WUC_MODCLKEN0_TDC_EN) +#define AUX_WUC_OSCCTRL_CLOCK (AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_EN) +#define AUX_WUC_ADI_CLOCK (AUX_WUC_MODCLKEN0_AUX_ADI4_EN) +#define AUX_WUC_MODCLK_MASK 0x000000FF -#define AUX_WUC_TDC_CLOCK 0x00000100 -#define AUX_WUC_ADC_CLOCK 0x00000200 -#define AUX_WUC_REF_CLOCK 0x00000400 +#define AUX_WUC_TDC_CLOCK 0x00000100 +#define AUX_WUC_ADC_CLOCK 0x00000200 +#define AUX_WUC_REF_CLOCK 0x00000400 -#define AUX_WUC_CLOCK_OFF 0x00000000 -#define AUX_WUC_CLOCK_UNSTABLE 0x00000001 -#define AUX_WUC_CLOCK_READY 0x00000011 +#define AUX_WUC_CLOCK_OFF 0x00000000 +#define AUX_WUC_CLOCK_UNSTABLE 0x00000001 +#define AUX_WUC_CLOCK_READY 0x00000011 -#define AUX_WUC_CLOCK_HIFREQ 0x00000000 -#define AUX_WUC_CLOCK_LOFREQ 0x00000001 +#define AUX_WUC_CLOCK_HIFREQ 0x00000000 +#define AUX_WUC_CLOCK_LOFREQ 0x00000001 //***************************************************************************** // @@ -310,20 +309,20 @@ AUXWUCFreezeDisable(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_AUXWUCClockEnable -#undef AUXWUCClockEnable -#define AUXWUCClockEnable ROM_AUXWUCClockEnable +#undef AUXWUCClockEnable +#define AUXWUCClockEnable ROM_AUXWUCClockEnable #endif #ifdef ROM_AUXWUCClockDisable -#undef AUXWUCClockDisable -#define AUXWUCClockDisable ROM_AUXWUCClockDisable +#undef AUXWUCClockDisable +#define AUXWUCClockDisable ROM_AUXWUCClockDisable #endif #ifdef ROM_AUXWUCClockStatus -#undef AUXWUCClockStatus -#define AUXWUCClockStatus ROM_AUXWUCClockStatus +#undef AUXWUCClockStatus +#define AUXWUCClockStatus ROM_AUXWUCClockStatus #endif #ifdef ROM_AUXWUCPowerCtrl -#undef AUXWUCPowerCtrl -#define AUXWUCPowerCtrl ROM_AUXWUCPowerCtrl +#undef AUXWUCPowerCtrl +#define AUXWUCPowerCtrl ROM_AUXWUCPowerCtrl #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ccfgread.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ccfgread.h index 3dec1eb..291eb62 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ccfgread.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ccfgread.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: ccfgread.h -* Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) -* Revision: 47152 -* -* Description: API for reading CCFG. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: ccfgread.h + * Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) + * Revision: 47152 + * + * Description: API for reading CCFG. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,15 +55,14 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_ccfg.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ccfg.h" //***************************************************************************** // @@ -71,7 +70,6 @@ extern "C" // //***************************************************************************** - //***************************************************************************** // // API Functions and prototypes @@ -86,11 +84,11 @@ extern "C" // //***************************************************************************** __STATIC_INLINE bool -CCFGRead_DIS_GPRAM( void ) +CCFGRead_DIS_GPRAM(void) { - return (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & - CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) >> - CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S ) ; + return ((HWREG(CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS) & + CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M) >> + CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S); } //***************************************************************************** @@ -101,11 +99,11 @@ CCFGRead_DIS_GPRAM( void ) // //***************************************************************************** __STATIC_INLINE bool -CCFGRead_EXT_LF_CLK_DIO( void ) +CCFGRead_EXT_LF_CLK_DIO(void) { - return (( HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK ) & - CCFG_EXT_LF_CLK_DIO_M ) >> - CCFG_EXT_LF_CLK_DIO_S ) ; + return ((HWREG(CCFG_BASE + CCFG_O_EXT_LF_CLK) & + CCFG_EXT_LF_CLK_DIO_M) >> + CCFG_EXT_LF_CLK_DIO_S); } //***************************************************************************** @@ -113,10 +111,10 @@ CCFGRead_EXT_LF_CLK_DIO( void ) // Defines the possible values returned from CCFGRead_SCLK_LF_OPTION() // //***************************************************************************** -#define CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF ( CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) -#define CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) -#define CCFGREAD_SCLK_LF_OPTION_XOSC_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) -#define CCFGREAD_SCLK_LF_OPTION_RCOSC_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) +#define CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF (CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S) +#define CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF (CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S) +#define CCFGREAD_SCLK_LF_OPTION_XOSC_LF (CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S) +#define CCFGREAD_SCLK_LF_OPTION_RCOSC_LF (CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S) //***************************************************************************** // @@ -131,11 +129,11 @@ CCFGRead_EXT_LF_CLK_DIO( void ) // //***************************************************************************** __STATIC_INLINE uint32_t -CCFGRead_SCLK_LF_OPTION( void ) +CCFGRead_SCLK_LF_OPTION(void) { - return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF ) & - CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> - CCFG_MODE_CONF_SCLK_LF_OPTION_S ) ; + return ((HWREG(CCFG_BASE + CCFG_O_MODE_CONF) & + CCFG_MODE_CONF_SCLK_LF_OPTION_M) >> + CCFG_MODE_CONF_SCLK_LF_OPTION_S); } //***************************************************************************** @@ -143,9 +141,9 @@ CCFGRead_SCLK_LF_OPTION( void ) // Defines the possible values returned from CCFGRead_XOSC_FREQ() // //***************************************************************************** -#define CCFGREAD_XOSC_FREQ_24M ( CCFG_MODE_CONF_XOSC_FREQ_24M >> CCFG_MODE_CONF_XOSC_FREQ_S ) -#define CCFGREAD_XOSC_FREQ_48M ( CCFG_MODE_CONF_XOSC_FREQ_48M >> CCFG_MODE_CONF_XOSC_FREQ_S ) -#define CCFGREAD_XOSC_FREQ_HPOSC ( CCFG_MODE_CONF_XOSC_FREQ_HPOSC >> CCFG_MODE_CONF_XOSC_FREQ_S ) +#define CCFGREAD_XOSC_FREQ_24M (CCFG_MODE_CONF_XOSC_FREQ_24M >> CCFG_MODE_CONF_XOSC_FREQ_S) +#define CCFGREAD_XOSC_FREQ_48M (CCFG_MODE_CONF_XOSC_FREQ_48M >> CCFG_MODE_CONF_XOSC_FREQ_S) +#define CCFGREAD_XOSC_FREQ_HPOSC (CCFG_MODE_CONF_XOSC_FREQ_HPOSC >> CCFG_MODE_CONF_XOSC_FREQ_S) //***************************************************************************** // @@ -160,11 +158,11 @@ CCFGRead_SCLK_LF_OPTION( void ) // //***************************************************************************** __STATIC_INLINE uint32_t -CCFGRead_XOSC_FREQ( void ) +CCFGRead_XOSC_FREQ(void) { - return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF ) & - CCFG_MODE_CONF_XOSC_FREQ_M ) >> - CCFG_MODE_CONF_XOSC_FREQ_S ) ; + return ((HWREG(CCFG_BASE + CCFG_O_MODE_CONF) & + CCFG_MODE_CONF_XOSC_FREQ_M) >> + CCFG_MODE_CONF_XOSC_FREQ_S); } //***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ccfgread_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ccfgread_doc.h index f3175fb..f8e9b82 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ccfgread_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ccfgread_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: ccfgread_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: ccfgread_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup ccfgread_api //! @{ //! \section sec_ccfgread Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/chipinfo.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/chipinfo.h index c1ce08a..8a6b06e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/chipinfo.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/chipinfo.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: chipinfo.h -* Revised: 2018-06-18 10:26:12 +0200 (Mon, 18 Jun 2018) -* Revision: 52189 -* -* Description: Collection of functions returning chip information. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: chipinfo.h + * Revised: 2018-06-18 10:26:12 +0200 (Mon, 18 Jun 2018) + * Revision: 52189 + * + * Description: Collection of functions returning chip information. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,15 +55,14 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" #include "../inc/hw_fcfg1.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include +#include //***************************************************************************** // @@ -80,10 +79,10 @@ extern "C" //***************************************************************************** #if !defined(DOXYGEN) #define ChipInfo_GetSupportedProtocol_BV NOROM_ChipInfo_GetSupportedProtocol_BV -#define ChipInfo_GetPackageType NOROM_ChipInfo_GetPackageType -#define ChipInfo_GetChipType NOROM_ChipInfo_GetChipType -#define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily -#define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision +#define ChipInfo_GetPackageType NOROM_ChipInfo_GetPackageType +#define ChipInfo_GetChipType NOROM_ChipInfo_GetChipType +#define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily +#define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision #define ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated NOROM_ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated #endif @@ -98,10 +97,10 @@ extern "C" //***************************************************************************** typedef enum { - PROTOCOL_Unknown = 0, //!< None of the known protocols are supported. - PROTOCOLBIT_BLE = 0x02, //!< Bit[1] set, indicates that Bluetooth Low Energy is supported. + PROTOCOL_Unknown = 0, //!< None of the known protocols are supported. + PROTOCOLBIT_BLE = 0x02, //!< Bit[1] set, indicates that Bluetooth Low Energy is supported. PROTOCOLBIT_IEEE_802_15_4 = 0x04, //!< Bit[2] set, indicates that IEEE 802.15.4 is supported. - PROTOCOLBIT_Proprietary = 0x08 //!< Bit[3] set, indicates that proprietary protocols are supported. + PROTOCOLBIT_Proprietary = 0x08 //!< Bit[3] set, indicates that proprietary protocols are supported. } ProtocolBitVector_t; //***************************************************************************** @@ -112,7 +111,7 @@ typedef enum //! Returns \ref ProtocolBitVector_t which is a bit vector indicating supported protocols. // //***************************************************************************** -extern ProtocolBitVector_t ChipInfo_GetSupportedProtocol_BV( void ); +extern ProtocolBitVector_t ChipInfo_GetSupportedProtocol_BV(void); //***************************************************************************** // @@ -123,9 +122,9 @@ extern ProtocolBitVector_t ChipInfo_GetSupportedProtocol_BV( void ); // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_SupportsBLE( void ) +ChipInfo_SupportsBLE(void) { - return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_BLE ) != 0 ); + return ((ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_BLE) != 0); } //***************************************************************************** @@ -137,9 +136,9 @@ ChipInfo_SupportsBLE( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_SupportsIEEE_802_15_4( void ) +ChipInfo_SupportsIEEE_802_15_4(void) { - return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_IEEE_802_15_4 ) != 0 ); + return ((ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_IEEE_802_15_4) != 0); } //***************************************************************************** @@ -151,9 +150,9 @@ ChipInfo_SupportsIEEE_802_15_4( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_SupportsPROPRIETARY( void ) +ChipInfo_SupportsPROPRIETARY(void) { - return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_Proprietary ) != 0 ); + return ((ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_Proprietary) != 0); } //***************************************************************************** @@ -166,13 +165,13 @@ ChipInfo_SupportsPROPRIETARY( void ) //***************************************************************************** typedef enum { - PACKAGE_Unknown = -1, //!< -1 means that current package type is unknown. - PACKAGE_4x4 = 0, //!< 0 means that this is a 4x4 mm QFN (RHB) package. - PACKAGE_5x5 = 1, //!< 1 means that this is a 5x5 mm QFN (RSM) package. - PACKAGE_7x7 = 2, //!< 2 means that this is a 7x7 mm QFN (RGZ) package. - PACKAGE_WAFER = 3, //!< 3 means that this is a wafer sale package (naked die). - PACKAGE_WCSP = 4, //!< 4 means that this is a 2.7x2.7 mm WCSP (YFV). - PACKAGE_7x7_Q1 = 5 //!< 5 means that this is a 7x7 mm QFN package with Wettable Flanks. + PACKAGE_Unknown = -1, //!< -1 means that current package type is unknown. + PACKAGE_4x4 = 0, //!< 0 means that this is a 4x4 mm QFN (RHB) package. + PACKAGE_5x5 = 1, //!< 1 means that this is a 5x5 mm QFN (RSM) package. + PACKAGE_7x7 = 2, //!< 2 means that this is a 7x7 mm QFN (RGZ) package. + PACKAGE_WAFER = 3, //!< 3 means that this is a wafer sale package (naked die). + PACKAGE_WCSP = 4, //!< 4 means that this is a 2.7x2.7 mm WCSP (YFV). + PACKAGE_7x7_Q1 = 5 //!< 5 means that this is a 7x7 mm QFN package with Wettable Flanks. } PackageType_t; //***************************************************************************** @@ -183,7 +182,7 @@ typedef enum //! Returns \ref PackageType_t // //***************************************************************************** -extern PackageType_t ChipInfo_GetPackageType( void ); +extern PackageType_t ChipInfo_GetPackageType(void); //***************************************************************************** // @@ -194,9 +193,9 @@ extern PackageType_t ChipInfo_GetPackageType( void ); // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_PackageTypeIs4x4( void ) +ChipInfo_PackageTypeIs4x4(void) { - return ( ChipInfo_GetPackageType() == PACKAGE_4x4 ); + return (ChipInfo_GetPackageType() == PACKAGE_4x4); } //***************************************************************************** @@ -208,9 +207,9 @@ ChipInfo_PackageTypeIs4x4( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_PackageTypeIs5x5( void ) +ChipInfo_PackageTypeIs5x5(void) { - return ( ChipInfo_GetPackageType() == PACKAGE_5x5 ); + return (ChipInfo_GetPackageType() == PACKAGE_5x5); } //***************************************************************************** @@ -222,9 +221,9 @@ ChipInfo_PackageTypeIs5x5( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_PackageTypeIs7x7( void ) +ChipInfo_PackageTypeIs7x7(void) { - return ( ChipInfo_GetPackageType() == PACKAGE_7x7 ); + return (ChipInfo_GetPackageType() == PACKAGE_7x7); } //***************************************************************************** @@ -236,9 +235,9 @@ ChipInfo_PackageTypeIs7x7( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_PackageTypeIsWAFER( void ) +ChipInfo_PackageTypeIsWAFER(void) { - return ( ChipInfo_GetPackageType() == PACKAGE_WAFER ); + return (ChipInfo_GetPackageType() == PACKAGE_WAFER); } //***************************************************************************** @@ -250,9 +249,9 @@ ChipInfo_PackageTypeIsWAFER( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_PackageTypeIsWCSP( void ) +ChipInfo_PackageTypeIsWCSP(void) { - return ( ChipInfo_GetPackageType() == PACKAGE_WCSP ); + return (ChipInfo_GetPackageType() == PACKAGE_WCSP); } //***************************************************************************** @@ -264,9 +263,9 @@ ChipInfo_PackageTypeIsWCSP( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_PackageTypeIs7x7Q1( void ) +ChipInfo_PackageTypeIs7x7Q1(void) { - return ( ChipInfo_GetPackageType() == PACKAGE_7x7_Q1 ); + return (ChipInfo_GetPackageType() == PACKAGE_7x7_Q1); } //***************************************************************************** @@ -277,10 +276,10 @@ ChipInfo_PackageTypeIs7x7Q1( void ) //! Returns the internal chip HW revision code (in range 0-15) //***************************************************************************** __STATIC_INLINE uint32_t -ChipInfo_GetDeviceIdHwRevCode( void ) +ChipInfo_GetDeviceIdHwRevCode(void) { // Returns HwRevCode = FCFG1_O_ICEPICK_DEVICE_ID[31:28] - return ( HWREG( FCFG1_BASE + FCFG1_O_ICEPICK_DEVICE_ID ) >> 28 ); + return (HWREG(FCFG1_BASE + FCFG1_O_ICEPICK_DEVICE_ID) >> 28); } //***************************************************************************** @@ -295,18 +294,18 @@ ChipInfo_GetDeviceIdHwRevCode( void ) // //***************************************************************************** __STATIC_INLINE uint32_t -ChipInfo_GetMinorHwRev( void ) +ChipInfo_GetMinorHwRev(void) { - uint32_t minorRev = (( HWREG( FCFG1_BASE + FCFG1_O_MISC_CONF_1 ) & - FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M ) >> - FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S ) ; + uint32_t minorRev = ((HWREG(FCFG1_BASE + FCFG1_O_MISC_CONF_1) & + FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M) >> + FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S); - if ( minorRev >= 0x80 ) + if (minorRev >= 0x80) { minorRev = 0; } - return ( minorRev ); + return (minorRev); } //***************************************************************************** @@ -320,9 +319,9 @@ ChipInfo_GetMinorHwRev( void ) // //***************************************************************************** __STATIC_INLINE uint32_t -ChipInfo_GetUserId( void ) +ChipInfo_GetUserId(void) { - return ( HWREG( FCFG1_BASE + FCFG1_O_USER_ID )); + return (HWREG(FCFG1_BASE + FCFG1_O_USER_ID)); } //***************************************************************************** @@ -332,22 +331,22 @@ ChipInfo_GetUserId( void ) //***************************************************************************** typedef enum { - CHIP_TYPE_Unknown = -1, //!< -1 means that the chip type is unknown. - CHIP_TYPE_CC1310 = 0, //!< 0 means that this is a CC1310 chip. - CHIP_TYPE_CC1350 = 1, //!< 1 means that this is a CC1350 chip. - CHIP_TYPE_CC2620 = 2, //!< 2 means that this is a CC2620 chip. - CHIP_TYPE_CC2630 = 3, //!< 3 means that this is a CC2630 chip. - CHIP_TYPE_CC2640 = 4, //!< 4 means that this is a CC2640 chip. - CHIP_TYPE_CC2650 = 5, //!< 5 means that this is a CC2650 chip. - CHIP_TYPE_CUSTOM_0 = 6, //!< 6 means that this is a CUSTOM_0 chip. - CHIP_TYPE_CUSTOM_1 = 7, //!< 7 means that this is a CUSTOM_1 chip. - CHIP_TYPE_CC2640R2 = 8, //!< 8 means that this is a CC2640R2 chip. - CHIP_TYPE_CC2642 = 9, //!< 9 means that this is a CC2642 chip. - CHIP_TYPE_unused = 10,//!< 10 unused value - CHIP_TYPE_CC2652 = 11,//!< 11 means that this is a CC2652 chip. - CHIP_TYPE_CC1312 = 12,//!< 12 means that this is a CC1312 chip. - CHIP_TYPE_CC1352 = 13,//!< 13 means that this is a CC1352 chip. - CHIP_TYPE_CC1352P = 14 //!< 14 means that this is a CC1352P chip. + CHIP_TYPE_Unknown = -1, //!< -1 means that the chip type is unknown. + CHIP_TYPE_CC1310 = 0, //!< 0 means that this is a CC1310 chip. + CHIP_TYPE_CC1350 = 1, //!< 1 means that this is a CC1350 chip. + CHIP_TYPE_CC2620 = 2, //!< 2 means that this is a CC2620 chip. + CHIP_TYPE_CC2630 = 3, //!< 3 means that this is a CC2630 chip. + CHIP_TYPE_CC2640 = 4, //!< 4 means that this is a CC2640 chip. + CHIP_TYPE_CC2650 = 5, //!< 5 means that this is a CC2650 chip. + CHIP_TYPE_CUSTOM_0 = 6, //!< 6 means that this is a CUSTOM_0 chip. + CHIP_TYPE_CUSTOM_1 = 7, //!< 7 means that this is a CUSTOM_1 chip. + CHIP_TYPE_CC2640R2 = 8, //!< 8 means that this is a CC2640R2 chip. + CHIP_TYPE_CC2642 = 9, //!< 9 means that this is a CC2642 chip. + CHIP_TYPE_unused = 10, //!< 10 unused value + CHIP_TYPE_CC2652 = 11, //!< 11 means that this is a CC2652 chip. + CHIP_TYPE_CC1312 = 12, //!< 12 means that this is a CC1312 chip. + CHIP_TYPE_CC1352 = 13, //!< 13 means that this is a CC1352 chip. + CHIP_TYPE_CC1352P = 14 //!< 14 means that this is a CC1352P chip. } ChipType_t; //***************************************************************************** @@ -358,7 +357,7 @@ typedef enum //! Returns \ref ChipType_t // //***************************************************************************** -extern ChipType_t ChipInfo_GetChipType( void ); +extern ChipType_t ChipInfo_GetChipType(void); //***************************************************************************** // @@ -367,12 +366,12 @@ extern ChipType_t ChipInfo_GetChipType( void ); //***************************************************************************** typedef enum { - FAMILY_Unknown = -1, //!< -1 means that the chip's family member is unknown. - FAMILY_CC26x0 = 0, //!< 0 means that the chip is a CC26x0 family member. - FAMILY_CC13x0 = 1, //!< 1 means that the chip is a CC13x0 family member. - FAMILY_CC26x1 = 2, //!< 2 means that the chip is a CC26x1 family member. - FAMILY_CC26x0R2 = 3, //!< 3 means that the chip is a CC26x0R2 family (new ROM contents). - FAMILY_CC13x2_CC26x2 = 4 //!< 4 means that the chip is a CC13x2, CC26x2 family member. + FAMILY_Unknown = -1, //!< -1 means that the chip's family member is unknown. + FAMILY_CC26x0 = 0, //!< 0 means that the chip is a CC26x0 family member. + FAMILY_CC13x0 = 1, //!< 1 means that the chip is a CC13x0 family member. + FAMILY_CC26x1 = 2, //!< 2 means that the chip is a CC26x1 family member. + FAMILY_CC26x0R2 = 3, //!< 3 means that the chip is a CC26x0R2 family (new ROM contents). + FAMILY_CC13x2_CC26x2 = 4 //!< 4 means that the chip is a CC13x2, CC26x2 family member. } ChipFamily_t; //***************************************************************************** @@ -383,17 +382,17 @@ typedef enum //! Returns \ref ChipFamily_t // //***************************************************************************** -extern ChipFamily_t ChipInfo_GetChipFamily( void ); +extern ChipFamily_t ChipInfo_GetChipFamily(void); //***************************************************************************** // // Options for the define THIS_DRIVERLIB_BUILD // //***************************************************************************** -#define DRIVERLIB_BUILD_CC26X0 0 //!< 0 is the driverlib build ID for the cc26x0 driverlib. -#define DRIVERLIB_BUILD_CC13X0 1 //!< 1 is the driverlib build ID for the cc13x0 driverlib. -#define DRIVERLIB_BUILD_CC26X1 2 //!< 2 is the driverlib build ID for the cc26x1 driverlib. -#define DRIVERLIB_BUILD_CC26X0R2 3 //!< 3 is the driverlib build ID for the cc26x0r2 driverlib. +#define DRIVERLIB_BUILD_CC26X0 0 //!< 0 is the driverlib build ID for the cc26x0 driverlib. +#define DRIVERLIB_BUILD_CC13X0 1 //!< 1 is the driverlib build ID for the cc13x0 driverlib. +#define DRIVERLIB_BUILD_CC26X1 2 //!< 2 is the driverlib build ID for the cc26x1 driverlib. +#define DRIVERLIB_BUILD_CC26X0R2 3 //!< 3 is the driverlib build ID for the cc26x0r2 driverlib. #define DRIVERLIB_BUILD_CC13X2_CC26X2 4 //!< 4 is the driverlib build ID for the cc13x2_cc26x2 driverlib. //***************************************************************************** @@ -403,7 +402,7 @@ extern ChipFamily_t ChipInfo_GetChipFamily( void ); //! This driverlib build identifier can be useful for compile time checking/optimization (supporting C preprocessor expressions). // //***************************************************************************** -#define THIS_DRIVERLIB_BUILD DRIVERLIB_BUILD_CC26X0 +#define THIS_DRIVERLIB_BUILD DRIVERLIB_BUILD_CC26X0 //***************************************************************************** // @@ -414,9 +413,9 @@ extern ChipFamily_t ChipInfo_GetChipFamily( void ); // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_ChipFamilyIs_CC13x0( void ) +ChipInfo_ChipFamilyIs_CC13x0(void) { - return ( ChipInfo_GetChipFamily() == FAMILY_CC13x0 ); + return (ChipInfo_GetChipFamily() == FAMILY_CC13x0); } //***************************************************************************** @@ -428,9 +427,9 @@ ChipInfo_ChipFamilyIs_CC13x0( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_ChipFamilyIs_CC26x0( void ) +ChipInfo_ChipFamilyIs_CC26x0(void) { - return ( ChipInfo_GetChipFamily() == FAMILY_CC26x0 ); + return (ChipInfo_GetChipFamily() == FAMILY_CC26x0); } //***************************************************************************** @@ -442,9 +441,9 @@ ChipInfo_ChipFamilyIs_CC26x0( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_ChipFamilyIs_CC26x0R2( void ) +ChipInfo_ChipFamilyIs_CC26x0R2(void) { - return ( ChipInfo_GetChipFamily() == FAMILY_CC26x0R2 ); + return (ChipInfo_GetChipFamily() == FAMILY_CC26x0R2); } //***************************************************************************** @@ -456,9 +455,9 @@ ChipInfo_ChipFamilyIs_CC26x0R2( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_ChipFamilyIs_CC26x1( void ) +ChipInfo_ChipFamilyIs_CC26x1(void) { - return ( ChipInfo_GetChipFamily() == FAMILY_CC26x1 ); + return (ChipInfo_GetChipFamily() == FAMILY_CC26x1); } //***************************************************************************** @@ -470,9 +469,9 @@ ChipInfo_ChipFamilyIs_CC26x1( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_ChipFamilyIs_CC13x2_CC26x2( void ) +ChipInfo_ChipFamilyIs_CC13x2_CC26x2(void) { - return ( ChipInfo_GetChipFamily() == FAMILY_CC13x2_CC26x2 ); + return (ChipInfo_GetChipFamily() == FAMILY_CC13x2_CC26x2); } //***************************************************************************** @@ -482,14 +481,14 @@ ChipInfo_ChipFamilyIs_CC13x2_CC26x2( void ) //***************************************************************************** typedef enum { - HWREV_Unknown = -1, //!< -1 means that the chip's HW revision is unknown. - HWREV_1_0 = 10, //!< 10 means that the chip's HW revision is 1.0 - HWREV_1_1 = 11, //!< 11 means that the chip's HW revision is 1.1 - HWREV_2_0 = 20, //!< 20 means that the chip's HW revision is 2.0 - HWREV_2_1 = 21, //!< 21 means that the chip's HW revision is 2.1 - HWREV_2_2 = 22, //!< 22 means that the chip's HW revision is 2.2 - HWREV_2_3 = 23, //!< 23 means that the chip's HW revision is 2.3 - HWREV_2_4 = 24 //!< 24 means that the chip's HW revision is 2.4 + HWREV_Unknown = -1, //!< -1 means that the chip's HW revision is unknown. + HWREV_1_0 = 10, //!< 10 means that the chip's HW revision is 1.0 + HWREV_1_1 = 11, //!< 11 means that the chip's HW revision is 1.1 + HWREV_2_0 = 20, //!< 20 means that the chip's HW revision is 2.0 + HWREV_2_1 = 21, //!< 21 means that the chip's HW revision is 2.1 + HWREV_2_2 = 22, //!< 22 means that the chip's HW revision is 2.2 + HWREV_2_3 = 23, //!< 23 means that the chip's HW revision is 2.3 + HWREV_2_4 = 24 //!< 24 means that the chip's HW revision is 2.4 } HwRevision_t; //***************************************************************************** @@ -500,7 +499,7 @@ typedef enum //! Returns \ref HwRevision_t // //***************************************************************************** -extern HwRevision_t ChipInfo_GetHwRevision( void ); +extern HwRevision_t ChipInfo_GetHwRevision(void); //***************************************************************************** // @@ -511,9 +510,9 @@ extern HwRevision_t ChipInfo_GetHwRevision( void ); // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_1_0( void ) +ChipInfo_HwRevisionIs_1_0(void) { - return ( ChipInfo_GetHwRevision() == HWREV_1_0 ); + return (ChipInfo_GetHwRevision() == HWREV_1_0); } //***************************************************************************** @@ -525,9 +524,9 @@ ChipInfo_HwRevisionIs_1_0( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_2_0( void ) +ChipInfo_HwRevisionIs_2_0(void) { - return ( ChipInfo_GetHwRevision() == HWREV_2_0 ); + return (ChipInfo_GetHwRevision() == HWREV_2_0); } //***************************************************************************** @@ -539,9 +538,9 @@ ChipInfo_HwRevisionIs_2_0( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_GTEQ_2_0( void ) +ChipInfo_HwRevisionIs_GTEQ_2_0(void) { - return ( ChipInfo_GetHwRevision() >= HWREV_2_0 ); + return (ChipInfo_GetHwRevision() >= HWREV_2_0); } //***************************************************************************** @@ -553,9 +552,9 @@ ChipInfo_HwRevisionIs_GTEQ_2_0( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_2_1( void ) +ChipInfo_HwRevisionIs_2_1(void) { - return ( ChipInfo_GetHwRevision() == HWREV_2_1 ); + return (ChipInfo_GetHwRevision() == HWREV_2_1); } //***************************************************************************** @@ -567,9 +566,9 @@ ChipInfo_HwRevisionIs_2_1( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_GTEQ_2_1( void ) +ChipInfo_HwRevisionIs_GTEQ_2_1(void) { - return ( ChipInfo_GetHwRevision() >= HWREV_2_1 ); + return (ChipInfo_GetHwRevision() >= HWREV_2_1); } //***************************************************************************** @@ -581,9 +580,9 @@ ChipInfo_HwRevisionIs_GTEQ_2_1( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_2_2( void ) +ChipInfo_HwRevisionIs_2_2(void) { - return ( ChipInfo_GetHwRevision() == HWREV_2_2 ); + return (ChipInfo_GetHwRevision() == HWREV_2_2); } //***************************************************************************** @@ -595,9 +594,9 @@ ChipInfo_HwRevisionIs_2_2( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_GTEQ_2_2( void ) +ChipInfo_HwRevisionIs_GTEQ_2_2(void) { - return ( ChipInfo_GetHwRevision() >= HWREV_2_2 ); + return (ChipInfo_GetHwRevision() >= HWREV_2_2); } //***************************************************************************** @@ -609,9 +608,9 @@ ChipInfo_HwRevisionIs_GTEQ_2_2( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_GTEQ_2_3( void ) +ChipInfo_HwRevisionIs_GTEQ_2_3(void) { - return ( ChipInfo_GetHwRevision() >= HWREV_2_3 ); + return (ChipInfo_GetHwRevision() >= HWREV_2_3); } //***************************************************************************** @@ -623,9 +622,9 @@ ChipInfo_HwRevisionIs_GTEQ_2_3( void ) // //***************************************************************************** __STATIC_INLINE bool -ChipInfo_HwRevisionIs_GTEQ_2_4( void ) +ChipInfo_HwRevisionIs_GTEQ_2_4(void) { - return ( ChipInfo_GetHwRevision() >= HWREV_2_4 ); + return (ChipInfo_GetHwRevision() >= HWREV_2_4); } //***************************************************************************** @@ -635,7 +634,7 @@ ChipInfo_HwRevisionIs_GTEQ_2_4( void ) //! \return None // //***************************************************************************** -extern void ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated( void ); +extern void ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated(void); //***************************************************************************** // @@ -646,27 +645,27 @@ extern void ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated( void ); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_ChipInfo_GetSupportedProtocol_BV -#undef ChipInfo_GetSupportedProtocol_BV +#undef ChipInfo_GetSupportedProtocol_BV #define ChipInfo_GetSupportedProtocol_BV ROM_ChipInfo_GetSupportedProtocol_BV #endif #ifdef ROM_ChipInfo_GetPackageType -#undef ChipInfo_GetPackageType -#define ChipInfo_GetPackageType ROM_ChipInfo_GetPackageType +#undef ChipInfo_GetPackageType +#define ChipInfo_GetPackageType ROM_ChipInfo_GetPackageType #endif #ifdef ROM_ChipInfo_GetChipType -#undef ChipInfo_GetChipType -#define ChipInfo_GetChipType ROM_ChipInfo_GetChipType +#undef ChipInfo_GetChipType +#define ChipInfo_GetChipType ROM_ChipInfo_GetChipType #endif #ifdef ROM_ChipInfo_GetChipFamily -#undef ChipInfo_GetChipFamily -#define ChipInfo_GetChipFamily ROM_ChipInfo_GetChipFamily +#undef ChipInfo_GetChipFamily +#define ChipInfo_GetChipFamily ROM_ChipInfo_GetChipFamily #endif #ifdef ROM_ChipInfo_GetHwRevision -#undef ChipInfo_GetHwRevision -#define ChipInfo_GetHwRevision ROM_ChipInfo_GetHwRevision +#undef ChipInfo_GetHwRevision +#define ChipInfo_GetHwRevision ROM_ChipInfo_GetHwRevision #endif #ifdef ROM_ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated -#undef ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated +#undef ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated #define ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated ROM_ThisLibraryIsFor_CC26x0_HwRev22AndLater_HaltIfViolated #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/cpu.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/cpu.h index 947687f..c039cf7 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/cpu.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/cpu.h @@ -1,41 +1,41 @@ /****************************************************************************** -* Filename: cpu.h -* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) -* Revision: 52111 -* -* Description: Defines and prototypes for the CPU instruction wrapper -* functions. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: cpu.h + * Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) + * Revision: 52111 + * + * Description: Defines and prototypes for the CPU instruction wrapper + * functions. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -56,15 +56,14 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_cpu_scs.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_cpu_scs.h" //***************************************************************************** // @@ -80,11 +79,11 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define CPUcpsid NOROM_CPUcpsid -#define CPUprimask NOROM_CPUprimask -#define CPUcpsie NOROM_CPUcpsie -#define CPUbasepriGet NOROM_CPUbasepriGet -#define CPUdelay NOROM_CPUdelay +#define CPUcpsid NOROM_CPUcpsid +#define CPUprimask NOROM_CPUprimask +#define CPUcpsie NOROM_CPUcpsie +#define CPUbasepriGet NOROM_CPUbasepriGet +#define CPUdelay NOROM_CPUdelay #endif //***************************************************************************** @@ -207,7 +206,7 @@ CPUwfi(void) { // Wait for the next interrupt. wfi; - bx lr + bx lr } #elif defined(__TI_COMPILER_VERSION__) __STATIC_INLINE void @@ -221,7 +220,7 @@ __STATIC_INLINE void __attribute__((always_inline)) CPUwfi(void) { // Wait for the next interrupt. - __asm volatile (" wfi\n"); + __asm volatile(" wfi\n"); } #endif @@ -254,7 +253,7 @@ CPUwfe(void) { // Wait for the next event. wfe; - bx lr + bx lr } #elif defined(__TI_COMPILER_VERSION__) __STATIC_INLINE void @@ -268,7 +267,7 @@ __STATIC_INLINE void __attribute__((always_inline)) CPUwfe(void) { // Wait for the next event. - __asm volatile (" wfe\n"); + __asm volatile(" wfe\n"); } #endif @@ -301,7 +300,7 @@ CPUsev(void) { // Send event. sev; - bx lr + bx lr } #elif defined(__TI_COMPILER_VERSION__) __STATIC_INLINE void @@ -315,11 +314,10 @@ __STATIC_INLINE void __attribute__((always_inline)) CPUsev(void) { // Send event. - __asm volatile (" sev\n"); + __asm volatile(" sev\n"); } #endif - //***************************************************************************** // //! \brief Update the interrupt priority disable level. @@ -350,8 +348,8 @@ __asm __STATIC_INLINE void CPUbasepriSet(uint32_t ui32NewBasepri) { // Set the BASEPRI register. - msr BASEPRI, r0; - bx lr + msr BASEPRI, r0; + bx lr } #elif defined(__TI_COMPILER_VERSION__) __STATIC_INLINE void @@ -363,15 +361,14 @@ CPUbasepriSet(uint32_t ui32NewBasepri) #else #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wattributes" -__STATIC_INLINE void __attribute__ ((naked)) +__STATIC_INLINE void __attribute__((naked)) CPUbasepriSet(uint32_t ui32NewBasepri) { // Set the BASEPRI register. - __asm volatile (" msr BASEPRI, %0\n" - " bx lr\n" - : /* No output */ - : "r" (ui32NewBasepri) - ); + __asm volatile(" msr BASEPRI, %0\n" + " bx lr\n" + : /* No output */ + : "r"(ui32NewBasepri)); } #pragma GCC diagnostic pop #endif @@ -393,9 +390,9 @@ CPUbasepriSet(uint32_t ui32NewBasepri) // //***************************************************************************** __STATIC_INLINE void -CPU_WriteBufferDisable( void ) +CPU_WriteBufferDisable(void) { - HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 1; + HWREGBITW(CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN) = 1; } //***************************************************************************** @@ -411,9 +408,9 @@ CPU_WriteBufferDisable( void ) // //***************************************************************************** __STATIC_INLINE void -CPU_WriteBufferEnable( void ) +CPU_WriteBufferEnable(void) { - HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 0; + HWREGBITW(CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN) = 0; } //***************************************************************************** @@ -425,24 +422,24 @@ CPU_WriteBufferEnable( void ) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_CPUcpsid -#undef CPUcpsid -#define CPUcpsid ROM_CPUcpsid +#undef CPUcpsid +#define CPUcpsid ROM_CPUcpsid #endif #ifdef ROM_CPUprimask -#undef CPUprimask -#define CPUprimask ROM_CPUprimask +#undef CPUprimask +#define CPUprimask ROM_CPUprimask #endif #ifdef ROM_CPUcpsie -#undef CPUcpsie -#define CPUcpsie ROM_CPUcpsie +#undef CPUcpsie +#define CPUcpsie ROM_CPUcpsie #endif #ifdef ROM_CPUbasepriGet -#undef CPUbasepriGet -#define CPUbasepriGet ROM_CPUbasepriGet +#undef CPUbasepriGet +#define CPUbasepriGet ROM_CPUbasepriGet #endif #ifdef ROM_CPUdelay -#undef CPUdelay -#define CPUdelay ROM_CPUdelay +#undef CPUdelay +#define CPUdelay ROM_CPUdelay #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/cpu_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/cpu_doc.h index 7f17aa3..4295c5e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/cpu_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/cpu_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: cpu_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: cpu_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup cpu_api //! @{ //! \section sec_cpu Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/crypto.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/crypto.h index 11760a6..4c64649 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/crypto.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/crypto.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: crypto.h -* Revised: 2018-01-12 18:46:31 +0100 (Fri, 12 Jan 2018) -* Revision: 51161 -* -* Description: AES header file. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: crypto.h + * Revised: 2018-01-12 18:46:31 +0100 (Fri, 12 Jan 2018) + * Revision: 51161 + * + * Description: AES header file. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,19 +55,18 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" #include "../inc/hw_crypto.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "cpu.h" #include "debug.h" #include "interrupt.h" -#include "cpu.h" +#include +#include //***************************************************************************** // @@ -83,19 +82,19 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define CRYPTOAesLoadKey NOROM_CRYPTOAesLoadKey -#define CRYPTOAesCbc NOROM_CRYPTOAesCbc -#define CRYPTOAesCbcStatus NOROM_CRYPTOAesCbcStatus -#define CRYPTOAesEcb NOROM_CRYPTOAesEcb -#define CRYPTOAesEcbStatus NOROM_CRYPTOAesEcbStatus -#define CRYPTOCcmAuthEncrypt NOROM_CRYPTOCcmAuthEncrypt -#define CRYPTOCcmAuthEncryptStatus NOROM_CRYPTOCcmAuthEncryptStatus -#define CRYPTOCcmAuthEncryptResultGet NOROM_CRYPTOCcmAuthEncryptResultGet -#define CRYPTOCcmInvAuthDecrypt NOROM_CRYPTOCcmInvAuthDecrypt -#define CRYPTOCcmInvAuthDecryptStatus NOROM_CRYPTOCcmInvAuthDecryptStatus +#define CRYPTOAesLoadKey NOROM_CRYPTOAesLoadKey +#define CRYPTOAesCbc NOROM_CRYPTOAesCbc +#define CRYPTOAesCbcStatus NOROM_CRYPTOAesCbcStatus +#define CRYPTOAesEcb NOROM_CRYPTOAesEcb +#define CRYPTOAesEcbStatus NOROM_CRYPTOAesEcbStatus +#define CRYPTOCcmAuthEncrypt NOROM_CRYPTOCcmAuthEncrypt +#define CRYPTOCcmAuthEncryptStatus NOROM_CRYPTOCcmAuthEncryptStatus +#define CRYPTOCcmAuthEncryptResultGet NOROM_CRYPTOCcmAuthEncryptResultGet +#define CRYPTOCcmInvAuthDecrypt NOROM_CRYPTOCcmInvAuthDecrypt +#define CRYPTOCcmInvAuthDecryptStatus NOROM_CRYPTOCcmInvAuthDecryptStatus #define CRYPTOCcmInvAuthDecryptResultGet NOROM_CRYPTOCcmInvAuthDecryptResultGet -#define CRYPTODmaEnable NOROM_CRYPTODmaEnable -#define CRYPTODmaDisable NOROM_CRYPTODmaDisable +#define CRYPTODmaEnable NOROM_CRYPTODmaEnable +#define CRYPTODmaDisable NOROM_CRYPTODmaDisable #endif //***************************************************************************** @@ -103,7 +102,7 @@ extern "C" // Length of AES Electronic Code Book (ECB) block in bytes // //***************************************************************************** -#define AES_ECB_LENGTH 16 +#define AES_ECB_LENGTH 16 //***************************************************************************** // @@ -111,24 +110,24 @@ extern "C" // as the ui32IntFlags parameter, and returned from CryptoIntStatus. // //***************************************************************************** -#define CRYPTO_DMA_IN_DONE 0x00000002 // DMA done interrupt mask -#define CRYPTO_RESULT_RDY 0x00000001 // Result ready interrupt mask -#define CRYPTO_DMA_BUS_ERR 0x80000000 // DMA Bus error -#define CRYPTO_KEY_ST_WR_ERR 0x40000000 // Key Store Write failed -#define CRYPTO_KEY_ST_RD_ERR 0x20000000 // Key Store Read failed +#define CRYPTO_DMA_IN_DONE 0x00000002 // DMA done interrupt mask +#define CRYPTO_RESULT_RDY 0x00000001 // Result ready interrupt mask +#define CRYPTO_DMA_BUS_ERR 0x80000000 // DMA Bus error +#define CRYPTO_KEY_ST_WR_ERR 0x40000000 // Key Store Write failed +#define CRYPTO_KEY_ST_RD_ERR 0x20000000 // Key Store Read failed -#define CRYPTO_IRQTYPE_LEVEL 0x00000001 // Crypto Level interrupt enabled -#define CRYPTO_IRQTYPE_PULSE 0x00000000 // Crypto pulse interrupt enabled +#define CRYPTO_IRQTYPE_LEVEL 0x00000001 // Crypto Level interrupt enabled +#define CRYPTO_IRQTYPE_PULSE 0x00000000 // Crypto pulse interrupt enabled -#define CRYPTO_DMA_CHAN0 0x00000001 // Crypto DMA Channel 0 -#define CRYPTO_DMA_CHAN1 0x00000002 // Crypto DMA Channel 1 +#define CRYPTO_DMA_CHAN0 0x00000001 // Crypto DMA Channel 0 +#define CRYPTO_DMA_CHAN1 0x00000002 // Crypto DMA Channel 1 -#define CRYPTO_AES128_ENCRYPT 0x0000000C // -#define CRYPTO_AES128_DECRYPT 0x00000008 // +#define CRYPTO_AES128_ENCRYPT 0x0000000C // +#define CRYPTO_AES128_DECRYPT 0x00000008 // -#define CRYPTO_DMA_READY 0x00000000 // DMA ready -#define CRYPTO_DMA_BSY 0x00000003 // DMA busy -#define CRYPTO_DMA_BUS_ERROR 0x00020000 // DMA encountered bus error +#define CRYPTO_DMA_READY 0x00000000 // DMA ready +#define CRYPTO_DMA_BSY 0x00000003 // DMA busy +#define CRYPTO_DMA_BUS_ERROR 0x00020000 // DMA encountered bus error //***************************************************************************** // @@ -137,25 +136,25 @@ extern "C" //***************************************************************************** // AES module return codes -#define AES_SUCCESS 0 -#define AES_KEYSTORE_READ_ERROR 1 -#define AES_KEYSTORE_WRITE_ERROR 2 -#define AES_DMA_BUS_ERROR 3 -#define CCM_AUTHENTICATION_FAILED 4 -#define AES_ECB_TEST_ERROR 8 -#define AES_NULL_ERROR 9 -#define AES_CCM_TEST_ERROR 10 -#define AES_DMA_BSY 11 +#define AES_SUCCESS 0 +#define AES_KEYSTORE_READ_ERROR 1 +#define AES_KEYSTORE_WRITE_ERROR 2 +#define AES_DMA_BUS_ERROR 3 +#define CCM_AUTHENTICATION_FAILED 4 +#define AES_ECB_TEST_ERROR 8 +#define AES_NULL_ERROR 9 +#define AES_CCM_TEST_ERROR 10 +#define AES_DMA_BSY 11 // Key store module defines -#define STATE_BLENGTH 16 // Number of bytes in State -#define KEY_BLENGTH 16 // Number of bytes in Key -#define KEY_EXP_LENGTH 176 // Nb * (Nr+1) * 4 +#define STATE_BLENGTH 16 // Number of bytes in State +#define KEY_BLENGTH 16 // Number of bytes in Key +#define KEY_EXP_LENGTH 176 // Nb * (Nr+1) * 4 -#define KEY_STORE_SIZE_128 0x00000001 -#define KEY_STORE_SIZE_192 0x00000002 -#define KEY_STORE_SIZE_256 0x00000003 -#define KEY_STORE_SIZE_BITS 0x00000003 +#define KEY_STORE_SIZE_128 0x00000001 +#define KEY_STORE_SIZE_192 0x00000002 +#define KEY_STORE_SIZE_256 0x00000003 +#define KEY_STORE_SIZE_BITS 0x00000003 //***************************************************************************** // @@ -164,36 +163,36 @@ extern "C" // are valid. // //***************************************************************************** -#define CRYPTO_KEY_AREA_0 0 -#define CRYPTO_KEY_AREA_1 1 -#define CRYPTO_KEY_AREA_2 2 -#define CRYPTO_KEY_AREA_3 3 -#define CRYPTO_KEY_AREA_4 4 -#define CRYPTO_KEY_AREA_5 5 -#define CRYPTO_KEY_AREA_6 6 -#define CRYPTO_KEY_AREA_7 7 +#define CRYPTO_KEY_AREA_0 0 +#define CRYPTO_KEY_AREA_1 1 +#define CRYPTO_KEY_AREA_2 2 +#define CRYPTO_KEY_AREA_3 3 +#define CRYPTO_KEY_AREA_4 4 +#define CRYPTO_KEY_AREA_5 5 +#define CRYPTO_KEY_AREA_6 6 +#define CRYPTO_KEY_AREA_7 7 //***************************************************************************** // // Defines for the current AES operation // //***************************************************************************** -#define CRYPTO_AES_NONE 0 -#define CRYPTO_AES_KEYL0AD 1 -#define CRYPTO_AES_ECB 2 -#define CRYPTO_AES_CCM 3 -#define CRYPTO_AES_RNG 4 -#define CRYPTO_AES_CBC 5 +#define CRYPTO_AES_NONE 0 +#define CRYPTO_AES_KEYL0AD 1 +#define CRYPTO_AES_ECB 2 +#define CRYPTO_AES_CCM 3 +#define CRYPTO_AES_RNG 4 +#define CRYPTO_AES_CBC 5 //***************************************************************************** // // Defines for the AES-CTR mode counter width // //***************************************************************************** -#define CRYPTO_AES_CTR_32 0x0 -#define CRYPTO_AES_CTR_64 0x1 -#define CRYPTO_AES_CTR_96 0x2 -#define CRYPTO_AES_CTR_128 0x3 +#define CRYPTO_AES_CTR_32 0x0 +#define CRYPTO_AES_CTR_64 0x1 +#define CRYPTO_AES_CTR_96 0x2 +#define CRYPTO_AES_CTR_128 0x3 //***************************************************************************** // @@ -457,7 +456,7 @@ extern uint32_t CRYPTOCcmAuthEncryptStatus(void); // //***************************************************************************** extern uint32_t CRYPTOCcmAuthEncryptResultGet(uint32_t ui32TagLength, - uint32_t* pui32CcmTag); + uint32_t* pui32CcmTag); //***************************************************************************** // @@ -530,9 +529,9 @@ extern uint32_t CRYPTOCcmInvAuthDecryptStatus(void); // //***************************************************************************** extern uint32_t CRYPTOCcmInvAuthDecryptResultGet(uint32_t ui32AuthLength, - uint32_t* pui32CipherText, - uint32_t ui32CipherTextLength, - uint32_t* pui32CcmTag); + uint32_t* pui32CipherText, + uint32_t ui32CipherTextLength, + uint32_t* pui32CcmTag); //***************************************************************************** // @@ -783,56 +782,56 @@ CRYPTOIntUnregister(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_CRYPTOAesLoadKey -#undef CRYPTOAesLoadKey -#define CRYPTOAesLoadKey ROM_CRYPTOAesLoadKey +#undef CRYPTOAesLoadKey +#define CRYPTOAesLoadKey ROM_CRYPTOAesLoadKey #endif #ifdef ROM_CRYPTOAesCbc -#undef CRYPTOAesCbc -#define CRYPTOAesCbc ROM_CRYPTOAesCbc +#undef CRYPTOAesCbc +#define CRYPTOAesCbc ROM_CRYPTOAesCbc #endif #ifdef ROM_CRYPTOAesCbcStatus -#undef CRYPTOAesCbcStatus -#define CRYPTOAesCbcStatus ROM_CRYPTOAesCbcStatus +#undef CRYPTOAesCbcStatus +#define CRYPTOAesCbcStatus ROM_CRYPTOAesCbcStatus #endif #ifdef ROM_CRYPTOAesEcb -#undef CRYPTOAesEcb -#define CRYPTOAesEcb ROM_CRYPTOAesEcb +#undef CRYPTOAesEcb +#define CRYPTOAesEcb ROM_CRYPTOAesEcb #endif #ifdef ROM_CRYPTOAesEcbStatus -#undef CRYPTOAesEcbStatus -#define CRYPTOAesEcbStatus ROM_CRYPTOAesEcbStatus +#undef CRYPTOAesEcbStatus +#define CRYPTOAesEcbStatus ROM_CRYPTOAesEcbStatus #endif #ifdef ROM_CRYPTOCcmAuthEncrypt -#undef CRYPTOCcmAuthEncrypt -#define CRYPTOCcmAuthEncrypt ROM_CRYPTOCcmAuthEncrypt +#undef CRYPTOCcmAuthEncrypt +#define CRYPTOCcmAuthEncrypt ROM_CRYPTOCcmAuthEncrypt #endif #ifdef ROM_CRYPTOCcmAuthEncryptStatus -#undef CRYPTOCcmAuthEncryptStatus -#define CRYPTOCcmAuthEncryptStatus ROM_CRYPTOCcmAuthEncryptStatus +#undef CRYPTOCcmAuthEncryptStatus +#define CRYPTOCcmAuthEncryptStatus ROM_CRYPTOCcmAuthEncryptStatus #endif #ifdef ROM_CRYPTOCcmAuthEncryptResultGet -#undef CRYPTOCcmAuthEncryptResultGet -#define CRYPTOCcmAuthEncryptResultGet ROM_CRYPTOCcmAuthEncryptResultGet +#undef CRYPTOCcmAuthEncryptResultGet +#define CRYPTOCcmAuthEncryptResultGet ROM_CRYPTOCcmAuthEncryptResultGet #endif #ifdef ROM_CRYPTOCcmInvAuthDecrypt -#undef CRYPTOCcmInvAuthDecrypt -#define CRYPTOCcmInvAuthDecrypt ROM_CRYPTOCcmInvAuthDecrypt +#undef CRYPTOCcmInvAuthDecrypt +#define CRYPTOCcmInvAuthDecrypt ROM_CRYPTOCcmInvAuthDecrypt #endif #ifdef ROM_CRYPTOCcmInvAuthDecryptStatus -#undef CRYPTOCcmInvAuthDecryptStatus -#define CRYPTOCcmInvAuthDecryptStatus ROM_CRYPTOCcmInvAuthDecryptStatus +#undef CRYPTOCcmInvAuthDecryptStatus +#define CRYPTOCcmInvAuthDecryptStatus ROM_CRYPTOCcmInvAuthDecryptStatus #endif #ifdef ROM_CRYPTOCcmInvAuthDecryptResultGet -#undef CRYPTOCcmInvAuthDecryptResultGet +#undef CRYPTOCcmInvAuthDecryptResultGet #define CRYPTOCcmInvAuthDecryptResultGet ROM_CRYPTOCcmInvAuthDecryptResultGet #endif #ifdef ROM_CRYPTODmaEnable -#undef CRYPTODmaEnable -#define CRYPTODmaEnable ROM_CRYPTODmaEnable +#undef CRYPTODmaEnable +#define CRYPTODmaEnable ROM_CRYPTODmaEnable #endif #ifdef ROM_CRYPTODmaDisable -#undef CRYPTODmaDisable -#define CRYPTODmaDisable ROM_CRYPTODmaDisable +#undef CRYPTODmaDisable +#define CRYPTODmaDisable ROM_CRYPTODmaDisable #endif #endif @@ -845,7 +844,7 @@ CRYPTOIntUnregister(void) } #endif -#endif // __CRYPTO_H__ +#endif // __CRYPTO_H__ //***************************************************************************** // diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ddi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ddi.h index e0a3036..d748e1d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ddi.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ddi.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: ddi.h -* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) -* Revision: 52111 -* -* Description: Defines and prototypes for the DDI master interface. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: ddi.h + * Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) + * Revision: 52111 + * + * Description: Defines and prototypes for the DDI master interface. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,18 +55,17 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aux_smph.h" +#include "../inc/hw_ddi.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "cpu.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ddi.h" -#include "../inc/hw_aux_smph.h" -#include "debug.h" -#include "cpu.h" //***************************************************************************** // @@ -82,11 +81,11 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define DDI32RegWrite NOROM_DDI32RegWrite -#define DDI16BitWrite NOROM_DDI16BitWrite -#define DDI16BitfieldWrite NOROM_DDI16BitfieldWrite -#define DDI16BitRead NOROM_DDI16BitRead -#define DDI16BitfieldRead NOROM_DDI16BitfieldRead +#define DDI32RegWrite NOROM_DDI32RegWrite +#define DDI16BitWrite NOROM_DDI16BitWrite +#define DDI16BitfieldWrite NOROM_DDI16BitfieldWrite +#define DDI16BitRead NOROM_DDI16BitRead +#define DDI16BitfieldRead NOROM_DDI16BitfieldRead #endif //***************************************************************************** @@ -94,17 +93,16 @@ extern "C" // Number of register in the DDI slave // //***************************************************************************** -#define DDI_SLAVE_REGS 64 - +#define DDI_SLAVE_REGS 64 //***************************************************************************** // // Defines that is used to control the ADI slave and master // //***************************************************************************** -#define DDI_PROTECT 0x00000080 -#define DDI_ACK 0x00000001 -#define DDI_SYNC 0x00000000 +#define DDI_PROTECT 0x00000080 +#define DDI_ACK 0x00000001 +#define DDI_SYNC 0x00000000 //***************************************************************************** // @@ -112,7 +110,6 @@ extern "C" // //***************************************************************************** - //***************************************************************************** // // Helper functions @@ -140,7 +137,8 @@ AuxAdiDdiSafeWrite(uint32_t nAddr, uint32_t nData, uint32_t nSize) bool bIrqEnabled = !CPUcpsid(); // Acquire semaphore for accessing ADI/DDI in AUX, perform access, release semaphore - while (!HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0)); + while (!HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0)) + ; switch (nSize) { @@ -154,7 +152,7 @@ AuxAdiDdiSafeWrite(uint32_t nAddr, uint32_t nData, uint32_t nSize) case 4: default: - HWREG(nAddr) = nData; + HWREG(nAddr) = nData; break; } @@ -188,7 +186,8 @@ AuxAdiDdiSafeRead(uint32_t nAddr, uint32_t nSize) bool bIrqEnabled = !CPUcpsid(); // Acquire semaphore for accessing ADI/DDI in AUX, perform access, release semaphore - while (!HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0)); + while (!HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0)) + ; switch (nSize) { @@ -241,7 +240,6 @@ DDIBaseValid(uint32_t ui32Base) } #endif - //***************************************************************************** // //! \brief Read the value in a 32 bit register. @@ -480,7 +478,6 @@ extern void DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) extern void DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32WrData); - //***************************************************************************** // //! \brief Write a bit field via the DDI using 16-bit maskable write. @@ -549,24 +546,24 @@ extern uint16_t DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg, #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_DDI32RegWrite -#undef DDI32RegWrite -#define DDI32RegWrite ROM_DDI32RegWrite +#undef DDI32RegWrite +#define DDI32RegWrite ROM_DDI32RegWrite #endif #ifdef ROM_DDI16BitWrite -#undef DDI16BitWrite -#define DDI16BitWrite ROM_DDI16BitWrite +#undef DDI16BitWrite +#define DDI16BitWrite ROM_DDI16BitWrite #endif #ifdef ROM_DDI16BitfieldWrite -#undef DDI16BitfieldWrite -#define DDI16BitfieldWrite ROM_DDI16BitfieldWrite +#undef DDI16BitfieldWrite +#define DDI16BitfieldWrite ROM_DDI16BitfieldWrite #endif #ifdef ROM_DDI16BitRead -#undef DDI16BitRead -#define DDI16BitRead ROM_DDI16BitRead +#undef DDI16BitRead +#define DDI16BitRead ROM_DDI16BitRead #endif #ifdef ROM_DDI16BitfieldRead -#undef DDI16BitfieldRead -#define DDI16BitfieldRead ROM_DDI16BitfieldRead +#undef DDI16BitfieldRead +#define DDI16BitfieldRead ROM_DDI16BitfieldRead #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ddi_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ddi_doc.h index 1c96d73..45760d6 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ddi_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ddi_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: ddi_doc.h -* Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016) -* Revision: 47080 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: ddi_doc.h + * Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016) + * Revision: 47080 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup ddi_api //! @{ //! \section sec_ddi Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/debug.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/debug.h index cbd4527..0f5bbcb 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/debug.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/debug.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: debug.h -* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) -* Revision: 48852 -* -* Description: Macros for assisting debug of the driver library. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: debug.h + * Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) + * Revision: 48852 + * + * Description: Macros for assisting debug of the driver library. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -62,8 +62,9 @@ extern void __error__(char* pcFilename, uint32_t ui32Line); // //***************************************************************************** #ifdef DRIVERLIB_DEBUG -#define ASSERT(expr) { \ - if(!(expr)) \ +#define ASSERT(expr) \ + { \ + if (!(expr)) \ { \ __error__(__FILE__, __LINE__); \ } \ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/driverlib_release.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/driverlib_release.h index b7a0434..2518c30 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/driverlib_release.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/driverlib_release.h @@ -1,41 +1,41 @@ /****************************************************************************** -* Filename: driverlib_release.h -* Revised: $Date: 2015-07-16 12:12:04 +0200 (Thu, 16 Jul 2015) $ -* Revision: $Revision: 44151 $ -* -* Description: Provides macros for ensuring that a specfic release of -* DriverLib is used. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: driverlib_release.h + * Revised: $Date: 2015-07-16 12:12:04 +0200 (Thu, 16 Jul 2015) $ + * Revision: $Revision: 44151 $ + * + * Description: Provides macros for ensuring that a specfic release of + * DriverLib is used. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -49,24 +49,16 @@ #ifndef __DRIVERLIB_RELEASE_H__ #define __DRIVERLIB_RELEASE_H__ - #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include - - - /// DriverLib release group number -#define DRIVERLIB_RELEASE_GROUP 0 +#define DRIVERLIB_RELEASE_GROUP 0 /// DriverLib release build number -#define DRIVERLIB_RELEASE_BUILD 54539 - - - +#define DRIVERLIB_RELEASE_BUILD 54539 //***************************************************************************** // @@ -85,9 +77,6 @@ extern "C" /// External declaration of the DriverLib release locking object extern DRIVERLIB_DECLARE_RELEASE(0, 54539); - - - //***************************************************************************** // //! This macro shall be called once from within a function of a precompiled @@ -112,9 +101,6 @@ extern DRIVERLIB_DECLARE_RELEASE(0, 54539); #define DRIVERLIB_ASSERT_RELEASE(group, build) \ (driverlib_release_##group##_##build) - - - //***************************************************************************** // //! This macro shall be called once from within a function of a precompiled @@ -137,16 +123,12 @@ extern DRIVERLIB_DECLARE_RELEASE(0, 54539); #define DRIVERLIB_ASSERT_CURR_RELEASE() \ DRIVERLIB_ASSERT_RELEASE(0, 54539) - - - #ifdef __cplusplus } #endif #endif // __DRIVERLIB_RELEASE_H__ - //***************************************************************************** // //! Close the Doxygen group. diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/event.h index f8f0c21..2df0cfa 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/event.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/event.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: event.h -* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) -* Revision: 47179 -* -* Description: Defines and prototypes for the Event Handler. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: event.h + * Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) + * Revision: 47179 + * + * Description: Defines and prototypes for the Event Handler. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,17 +55,15 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_event.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_event.h" -#include "debug.h" - //***************************************************************************** // @@ -142,28 +140,28 @@ __STATIC_INLINE void EventRegister(uint32_t ui32EventSubscriber, uint32_t ui32EventSource) { // Check the arguments. - ASSERT(( ui32EventSubscriber == EVENT_O_CPUIRQSEL30 ) || - ( ui32EventSubscriber == EVENT_O_RFCSEL9 ) || - ( ui32EventSubscriber == EVENT_O_GPT0ACAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT0BCAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT1ACAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT1BCAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT2ACAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT2BCAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT3ACAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT3BCAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH9SSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH9BSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH10SSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH10BSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH11SSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH11BSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH12SSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH12BSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH14BSEL ) || - ( ui32EventSubscriber == EVENT_O_AUXSEL0 ) || - ( ui32EventSubscriber == EVENT_O_I2SSTMPSEL0 ) || - ( ui32EventSubscriber == EVENT_O_FRZSEL0 ) ); + ASSERT((ui32EventSubscriber == EVENT_O_CPUIRQSEL30) || + (ui32EventSubscriber == EVENT_O_RFCSEL9) || + (ui32EventSubscriber == EVENT_O_GPT0ACAPTSEL) || + (ui32EventSubscriber == EVENT_O_GPT0BCAPTSEL) || + (ui32EventSubscriber == EVENT_O_GPT1ACAPTSEL) || + (ui32EventSubscriber == EVENT_O_GPT1BCAPTSEL) || + (ui32EventSubscriber == EVENT_O_GPT2ACAPTSEL) || + (ui32EventSubscriber == EVENT_O_GPT2BCAPTSEL) || + (ui32EventSubscriber == EVENT_O_GPT3ACAPTSEL) || + (ui32EventSubscriber == EVENT_O_GPT3BCAPTSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH9SSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH9BSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH10SSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH10BSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH11SSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH11BSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH12SSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH12BSEL) || + (ui32EventSubscriber == EVENT_O_UDMACH14BSEL) || + (ui32EventSubscriber == EVENT_O_AUXSEL0) || + (ui32EventSubscriber == EVENT_O_I2SSTMPSEL0) || + (ui32EventSubscriber == EVENT_O_FRZSEL0)); // Map the event source to the event subscriber HWREG(EVENT_BASE + ui32EventSubscriber) = ui32EventSource; @@ -193,7 +191,7 @@ __STATIC_INLINE void EventSwEventSet(uint32_t ui32SwEvent) { // Check the arguments. - ASSERT( ui32SwEvent <= 3 ); + ASSERT(ui32SwEvent <= 3); // Each software event is byte accessible HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent) = 1; @@ -216,7 +214,7 @@ __STATIC_INLINE void EventSwEventClear(uint32_t ui32SwEvent) { // Check the arguments. - ASSERT( ui32SwEvent <= 3 ); + ASSERT(ui32SwEvent <= 3); // Each software event is byte accessible HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent) = 0; @@ -241,10 +239,10 @@ __STATIC_INLINE uint32_t EventSwEventGet(uint32_t ui32SwEvent) { // Check the arguments. - ASSERT( ui32SwEvent <= 3 ); + ASSERT(ui32SwEvent <= 3); // Each software event is byte accessible - return ( HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent)); + return (HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent)); } //***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/event_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/event_doc.h index a17b238..a410558 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/event_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/event_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: event_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: event_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup event_api //! @{ //! \section sec_event Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/flash.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/flash.h index d9c3aad..54f8358 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/flash.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/flash.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: flash.h -* Revised: 2017-11-02 16:09:32 +0100 (Thu, 02 Nov 2017) -* Revision: 50166 -* -* Description: Defines and prototypes for the Flash driver. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: flash.h + * Revised: 2017-11-02 16:09:32 +0100 (Thu, 02 Nov 2017) + * Revision: 50166 + * + * Description: Defines and prototypes for the Flash driver. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,20 +55,19 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_flash.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" #include "../inc/hw_aon_sysctl.h" #include "../inc/hw_fcfg1.h" -#include "interrupt.h" +#include "../inc/hw_flash.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "debug.h" +#include "interrupt.h" +#include +#include //***************************************************************************** // @@ -84,15 +83,15 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define FlashPowerModeSet NOROM_FlashPowerModeSet -#define FlashPowerModeGet NOROM_FlashPowerModeGet -#define FlashProtectionSet NOROM_FlashProtectionSet -#define FlashProtectionGet NOROM_FlashProtectionGet -#define FlashProtectionSave NOROM_FlashProtectionSave -#define FlashSectorErase NOROM_FlashSectorErase -#define FlashProgram NOROM_FlashProgram -#define FlashEfuseReadRow NOROM_FlashEfuseReadRow -#define FlashDisableSectorsForWrite NOROM_FlashDisableSectorsForWrite +#define FlashPowerModeSet NOROM_FlashPowerModeSet +#define FlashPowerModeGet NOROM_FlashPowerModeGet +#define FlashProtectionSet NOROM_FlashProtectionSet +#define FlashProtectionGet NOROM_FlashProtectionGet +#define FlashProtectionSave NOROM_FlashProtectionSave +#define FlashSectorErase NOROM_FlashSectorErase +#define FlashProgram NOROM_FlashProgram +#define FlashEfuseReadRow NOROM_FlashEfuseReadRow +#define FlashDisableSectorsForWrite NOROM_FlashDisableSectorsForWrite #endif //***************************************************************************** @@ -100,12 +99,12 @@ extern "C" // Values that can be returned from the API functions // //***************************************************************************** -#define FAPI_STATUS_SUCCESS 0x00000000 // Function completed successfully -#define FAPI_STATUS_FSM_BUSY 0x00000001 // FSM is Busy -#define FAPI_STATUS_FSM_READY 0x00000002 // FSM is Ready +#define FAPI_STATUS_SUCCESS 0x00000000 // Function completed successfully +#define FAPI_STATUS_FSM_BUSY 0x00000001 // FSM is Busy +#define FAPI_STATUS_FSM_READY 0x00000002 // FSM is Ready #define FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH \ - 0x00000003 // Incorrect parameter value -#define FAPI_STATUS_FSM_ERROR 0x00000004 // Operation failed + 0x00000003 // Incorrect parameter value +#define FAPI_STATUS_FSM_ERROR 0x00000004 // Operation failed //***************************************************************************** // @@ -113,16 +112,16 @@ extern "C" // returned from FlashIntStatus(). // //***************************************************************************** -#define FLASH_INT_FSM_DONE 0x00400000 // FSM Done Interrupt Mask -#define FLASH_INT_RV 0x00010000 // Read Verify error Interrupt Mask +#define FLASH_INT_FSM_DONE 0x00400000 // FSM Done Interrupt Mask +#define FLASH_INT_RV 0x00010000 // Read Verify error Interrupt Mask //***************************************************************************** // // Values passed to FlashSetPowerMode() and returned from FlashGetPowerMode(). // //***************************************************************************** -#define FLASH_PWR_ACTIVE_MODE 0x00000000 -#define FLASH_PWR_OFF_MODE 0x00000001 +#define FLASH_PWR_ACTIVE_MODE 0x00000000 +#define FLASH_PWR_OFF_MODE 0x00000001 #define FLASH_PWR_DEEP_STDBY_MODE \ 0x00000002 @@ -131,8 +130,8 @@ extern "C" // Values passed to FlashSetProtection() and returned from FlashGetProtection(). // //***************************************************************************** -#define FLASH_NO_PROTECT 0x00000000 // Sector not protected -#define FLASH_WRITE_PROTECT 0x00000001 // Sector erase and program +#define FLASH_NO_PROTECT 0x00000000 // Sector not protected +#define FLASH_WRITE_PROTECT 0x00000001 // Sector erase and program // protected //***************************************************************************** @@ -140,21 +139,21 @@ extern "C" // Define used by the flash programming and erase functions // //***************************************************************************** -#define ADDR_OFFSET (0x1F800000 - FLASHMEM_BASE) +#define ADDR_OFFSET (0x1F800000 - FLASHMEM_BASE) //***************************************************************************** // // Define used for access to factory configuration area. // //***************************************************************************** -#define FCFG1_OFFSET 0x1000 +#define FCFG1_OFFSET 0x1000 //***************************************************************************** // // Define for the clock frequency input to the flash module in number of MHz // //***************************************************************************** -#define FLASH_MODULE_CLK_FREQ 48 +#define FLASH_MODULE_CLK_FREQ 48 //***************************************************************************** // @@ -163,16 +162,16 @@ extern "C" //***************************************************************************** typedef enum { - FAPI_PROGRAM_DATA = 0x0002, //!< Program data. - FAPI_ERASE_SECTOR = 0x0006, //!< Erase sector. - FAPI_ERASE_BANK = 0x0008, //!< Erase bank. + FAPI_PROGRAM_DATA = 0x0002, //!< Program data. + FAPI_ERASE_SECTOR = 0x0006, //!< Erase sector. + FAPI_ERASE_BANK = 0x0008, //!< Erase bank. FAPI_VALIDATE_SECTOR = 0x000E, //!< Validate sector. - FAPI_CLEAR_STATUS = 0x0010, //!< Clear status. - FAPI_PROGRAM_RESUME = 0x0014, //!< Program resume. - FAPI_ERASE_RESUME = 0x0016, //!< Erase resume. - FAPI_CLEAR_MORE = 0x0018, //!< Clear more. - FAPI_PROGRAM_SECTOR = 0x0020, //!< Program sector. - FAPI_ERASE_OTP = 0x0030 //!< Erase OTP. + FAPI_CLEAR_STATUS = 0x0010, //!< Clear status. + FAPI_PROGRAM_RESUME = 0x0014, //!< Program resume. + FAPI_ERASE_RESUME = 0x0016, //!< Erase resume. + FAPI_CLEAR_MORE = 0x0018, //!< Clear more. + FAPI_PROGRAM_SECTOR = 0x0020, //!< Program sector. + FAPI_ERASE_OTP = 0x0030 //!< Erase OTP. } tFlashStateCommandsType; //***************************************************************************** @@ -180,39 +179,39 @@ typedef enum // Defines for values written to the FLASH_O_FSM_WR_ENA register // //***************************************************************************** -#define FSM_REG_WRT_ENABLE 5 -#define FSM_REG_WRT_DISABLE 2 +#define FSM_REG_WRT_ENABLE 5 +#define FSM_REG_WRT_DISABLE 2 //***************************************************************************** // // Defines for the bank power mode field the FLASH_O_FBFALLBACK register // //***************************************************************************** -#define FBFALLBACK_SLEEP 0 -#define FBFALLBACK_DEEP_STDBY 1 -#define FBFALLBACK_ACTIVE 3 +#define FBFALLBACK_SLEEP 0 +#define FBFALLBACK_DEEP_STDBY 1 +#define FBFALLBACK_ACTIVE 3 //***************************************************************************** // // Defines for the bank grace period and pump grace period // //***************************************************************************** -#define FLASH_BAGP 0x14 -#define FLASH_PAGP 0x14 +#define FLASH_BAGP 0x14 +#define FLASH_PAGP 0x14 //***************************************************************************** // // Defines used by the FlashProgramPattern() function // //***************************************************************************** -#define PATTERN_BITS 0x20 // No of bits in data pattern to program +#define PATTERN_BITS 0x20 // No of bits in data pattern to program //***************************************************************************** // // Defines for the FW flag bits in the FLASH_O_FWFLAG register // //***************************************************************************** -#define FW_WRT_TRIMMED 0x00000001 +#define FW_WRT_TRIMMED 0x00000001 //***************************************************************************** // @@ -220,21 +219,21 @@ typedef enum // //***************************************************************************** typedef volatile uint8_t tFwpWriteByte; -#define FWPWRITE_BYTE_ADDRESS ((tFwpWriteByte *)((FLASH_BASE + FLASH_O_FWPWRITE0))) +#define FWPWRITE_BYTE_ADDRESS ((tFwpWriteByte*)((FLASH_BASE + FLASH_O_FWPWRITE0))) //***************************************************************************** // // Define for efuse instruction // //***************************************************************************** -#define DUMPWORD_INSTR 0x04 +#define DUMPWORD_INSTR 0x04 //***************************************************************************** // // Define for FSM command execution // //***************************************************************************** -#define FLASH_CMD_EXEC 0x15 +#define FLASH_CMD_EXEC 0x15 //***************************************************************************** // @@ -671,7 +670,6 @@ FlashIntClear(uint32_t ui32IntFlags) //***************************************************************************** extern uint32_t FlashSectorErase(uint32_t ui32SectorAddress); - //***************************************************************************** // //! \brief Programs unprotected flash sectors in the main bank. @@ -750,7 +748,6 @@ extern bool FlashEfuseReadRow(uint32_t* pui32EfuseData, //***************************************************************************** extern void FlashDisableSectorsForWrite(void); - //***************************************************************************** // // Support for DriverLib in ROM: @@ -760,40 +757,40 @@ extern void FlashDisableSectorsForWrite(void); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_FlashPowerModeSet -#undef FlashPowerModeSet -#define FlashPowerModeSet ROM_FlashPowerModeSet +#undef FlashPowerModeSet +#define FlashPowerModeSet ROM_FlashPowerModeSet #endif #ifdef ROM_FlashPowerModeGet -#undef FlashPowerModeGet -#define FlashPowerModeGet ROM_FlashPowerModeGet +#undef FlashPowerModeGet +#define FlashPowerModeGet ROM_FlashPowerModeGet #endif #ifdef ROM_FlashProtectionSet -#undef FlashProtectionSet -#define FlashProtectionSet ROM_FlashProtectionSet +#undef FlashProtectionSet +#define FlashProtectionSet ROM_FlashProtectionSet #endif #ifdef ROM_FlashProtectionGet -#undef FlashProtectionGet -#define FlashProtectionGet ROM_FlashProtectionGet +#undef FlashProtectionGet +#define FlashProtectionGet ROM_FlashProtectionGet #endif #ifdef ROM_FlashProtectionSave -#undef FlashProtectionSave -#define FlashProtectionSave ROM_FlashProtectionSave +#undef FlashProtectionSave +#define FlashProtectionSave ROM_FlashProtectionSave #endif #ifdef ROM_FlashSectorErase -#undef FlashSectorErase -#define FlashSectorErase ROM_FlashSectorErase +#undef FlashSectorErase +#define FlashSectorErase ROM_FlashSectorErase #endif #ifdef ROM_FlashProgram -#undef FlashProgram -#define FlashProgram ROM_FlashProgram +#undef FlashProgram +#define FlashProgram ROM_FlashProgram #endif #ifdef ROM_FlashEfuseReadRow -#undef FlashEfuseReadRow -#define FlashEfuseReadRow ROM_FlashEfuseReadRow +#undef FlashEfuseReadRow +#define FlashEfuseReadRow ROM_FlashEfuseReadRow #endif #ifdef ROM_FlashDisableSectorsForWrite -#undef FlashDisableSectorsForWrite -#define FlashDisableSectorsForWrite ROM_FlashDisableSectorsForWrite +#undef FlashDisableSectorsForWrite +#define FlashDisableSectorsForWrite ROM_FlashDisableSectorsForWrite #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/gpio.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/gpio.h index ffc16ef..f36f851 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/gpio.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/gpio.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: gpio.h -* Revised: 2018-05-02 11:11:40 +0200 (Wed, 02 May 2018) -* Revision: 51951 -* -* Description: Defines and prototypes for the GPIO. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: gpio.h + * Revised: 2018-05-02 11:11:40 +0200 (Wed, 02 May 2018) + * Revision: 51951 + * + * Description: Defines and prototypes for the GPIO. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,15 +55,14 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" #include "../inc/hw_gpio.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "debug.h" +#include //***************************************************************************** // @@ -75,29 +74,28 @@ extern "C" #include "chipinfo.h" static bool -dioNumberLegal( uint32_t dioNumber ) +dioNumberLegal(uint32_t dioNumber) { uint32_t ioCount = - (( HWREG( FCFG1_BASE + FCFG1_O_IOCONF ) & - FCFG1_IOCONF_GPIO_CNT_M ) >> - FCFG1_IOCONF_GPIO_CNT_S ) ; + ((HWREG(FCFG1_BASE + FCFG1_O_IOCONF) & + FCFG1_IOCONF_GPIO_CNT_M) >> + FCFG1_IOCONF_GPIO_CNT_S); // CC13x2 + CC26x2 - if ( ChipInfo_ChipFamilyIs_CC13x2_CC26x2() ) + if (ChipInfo_ChipFamilyIs_CC13x2_CC26x2()) { - return ( (dioNumber >= (31 - ioCount)) && (dioNumber < 31) ) + return ((dioNumber >= (31 - ioCount)) && (dioNumber < 31)) } // Special handling of CC13x0 7x7, where IO_CNT = 30 and legal range is 1..30 // for all other chips legal range is 0..(dioNumber-1) - else if (( ioCount == 30 ) && ChipInfo_ChipFamilyIs_CC13x0() ) + else if ((ioCount == 30) && ChipInfo_ChipFamilyIs_CC13x0()) { - return (( dioNumber > 0 ) && ( dioNumber <= ioCount )); + return ((dioNumber > 0) && (dioNumber <= ioCount)); } else { - return ( dioNumber < ioCount ); + return (dioNumber < ioCount); } - } #endif @@ -106,39 +104,39 @@ dioNumberLegal( uint32_t dioNumber ) // The following values define the bit field for the GPIO DIOs. // //***************************************************************************** -#define GPIO_DIO_0_MASK 0x00000001 // GPIO DIO 0 mask -#define GPIO_DIO_1_MASK 0x00000002 // GPIO DIO 1 mask -#define GPIO_DIO_2_MASK 0x00000004 // GPIO DIO 2 mask -#define GPIO_DIO_3_MASK 0x00000008 // GPIO DIO 3 mask -#define GPIO_DIO_4_MASK 0x00000010 // GPIO DIO 4 mask -#define GPIO_DIO_5_MASK 0x00000020 // GPIO DIO 5 mask -#define GPIO_DIO_6_MASK 0x00000040 // GPIO DIO 6 mask -#define GPIO_DIO_7_MASK 0x00000080 // GPIO DIO 7 mask -#define GPIO_DIO_8_MASK 0x00000100 // GPIO DIO 8 mask -#define GPIO_DIO_9_MASK 0x00000200 // GPIO DIO 9 mask -#define GPIO_DIO_10_MASK 0x00000400 // GPIO DIO 10 mask -#define GPIO_DIO_11_MASK 0x00000800 // GPIO DIO 11 mask -#define GPIO_DIO_12_MASK 0x00001000 // GPIO DIO 12 mask -#define GPIO_DIO_13_MASK 0x00002000 // GPIO DIO 13 mask -#define GPIO_DIO_14_MASK 0x00004000 // GPIO DIO 14 mask -#define GPIO_DIO_15_MASK 0x00008000 // GPIO DIO 15 mask -#define GPIO_DIO_16_MASK 0x00010000 // GPIO DIO 16 mask -#define GPIO_DIO_17_MASK 0x00020000 // GPIO DIO 17 mask -#define GPIO_DIO_18_MASK 0x00040000 // GPIO DIO 18 mask -#define GPIO_DIO_19_MASK 0x00080000 // GPIO DIO 19 mask -#define GPIO_DIO_20_MASK 0x00100000 // GPIO DIO 20 mask -#define GPIO_DIO_21_MASK 0x00200000 // GPIO DIO 21 mask -#define GPIO_DIO_22_MASK 0x00400000 // GPIO DIO 22 mask -#define GPIO_DIO_23_MASK 0x00800000 // GPIO DIO 23 mask -#define GPIO_DIO_24_MASK 0x01000000 // GPIO DIO 24 mask -#define GPIO_DIO_25_MASK 0x02000000 // GPIO DIO 25 mask -#define GPIO_DIO_26_MASK 0x04000000 // GPIO DIO 26 mask -#define GPIO_DIO_27_MASK 0x08000000 // GPIO DIO 27 mask -#define GPIO_DIO_28_MASK 0x10000000 // GPIO DIO 28 mask -#define GPIO_DIO_29_MASK 0x20000000 // GPIO DIO 29 mask -#define GPIO_DIO_30_MASK 0x40000000 // GPIO DIO 30 mask -#define GPIO_DIO_31_MASK 0x80000000 // GPIO DIO 31 mask -#define GPIO_DIO_ALL_MASK 0xFFFFFFFF // GPIO all DIOs mask +#define GPIO_DIO_0_MASK 0x00000001 // GPIO DIO 0 mask +#define GPIO_DIO_1_MASK 0x00000002 // GPIO DIO 1 mask +#define GPIO_DIO_2_MASK 0x00000004 // GPIO DIO 2 mask +#define GPIO_DIO_3_MASK 0x00000008 // GPIO DIO 3 mask +#define GPIO_DIO_4_MASK 0x00000010 // GPIO DIO 4 mask +#define GPIO_DIO_5_MASK 0x00000020 // GPIO DIO 5 mask +#define GPIO_DIO_6_MASK 0x00000040 // GPIO DIO 6 mask +#define GPIO_DIO_7_MASK 0x00000080 // GPIO DIO 7 mask +#define GPIO_DIO_8_MASK 0x00000100 // GPIO DIO 8 mask +#define GPIO_DIO_9_MASK 0x00000200 // GPIO DIO 9 mask +#define GPIO_DIO_10_MASK 0x00000400 // GPIO DIO 10 mask +#define GPIO_DIO_11_MASK 0x00000800 // GPIO DIO 11 mask +#define GPIO_DIO_12_MASK 0x00001000 // GPIO DIO 12 mask +#define GPIO_DIO_13_MASK 0x00002000 // GPIO DIO 13 mask +#define GPIO_DIO_14_MASK 0x00004000 // GPIO DIO 14 mask +#define GPIO_DIO_15_MASK 0x00008000 // GPIO DIO 15 mask +#define GPIO_DIO_16_MASK 0x00010000 // GPIO DIO 16 mask +#define GPIO_DIO_17_MASK 0x00020000 // GPIO DIO 17 mask +#define GPIO_DIO_18_MASK 0x00040000 // GPIO DIO 18 mask +#define GPIO_DIO_19_MASK 0x00080000 // GPIO DIO 19 mask +#define GPIO_DIO_20_MASK 0x00100000 // GPIO DIO 20 mask +#define GPIO_DIO_21_MASK 0x00200000 // GPIO DIO 21 mask +#define GPIO_DIO_22_MASK 0x00400000 // GPIO DIO 22 mask +#define GPIO_DIO_23_MASK 0x00800000 // GPIO DIO 23 mask +#define GPIO_DIO_24_MASK 0x01000000 // GPIO DIO 24 mask +#define GPIO_DIO_25_MASK 0x02000000 // GPIO DIO 25 mask +#define GPIO_DIO_26_MASK 0x04000000 // GPIO DIO 26 mask +#define GPIO_DIO_27_MASK 0x08000000 // GPIO DIO 27 mask +#define GPIO_DIO_28_MASK 0x10000000 // GPIO DIO 28 mask +#define GPIO_DIO_29_MASK 0x20000000 // GPIO DIO 29 mask +#define GPIO_DIO_30_MASK 0x40000000 // GPIO DIO 30 mask +#define GPIO_DIO_31_MASK 0x80000000 // GPIO DIO 31 mask +#define GPIO_DIO_ALL_MASK 0xFFFFFFFF // GPIO all DIOs mask //***************************************************************************** // @@ -147,8 +145,8 @@ dioNumberLegal( uint32_t dioNumber ) // GPIO_getOutputEnableDio(). // //***************************************************************************** -#define GPIO_OUTPUT_DISABLE 0x00000000 // DIO output is disabled -#define GPIO_OUTPUT_ENABLE 0x00000001 // DIO output is enabled +#define GPIO_OUTPUT_DISABLE 0x00000000 // DIO output is disabled +#define GPIO_OUTPUT_ENABLE 0x00000001 // DIO output is enabled //***************************************************************************** // @@ -168,13 +166,13 @@ dioNumberLegal( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE uint32_t -GPIO_readDio( uint32_t dioNumber ) +GPIO_readDio(uint32_t dioNumber) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); + ASSERT(dioNumberLegal(dioNumber)); // Return the input value from the specified DIO. - return (( HWREG( GPIO_BASE + GPIO_O_DIN31_0 ) >> dioNumber ) & 1 ); + return ((HWREG(GPIO_BASE + GPIO_O_DIN31_0) >> dioNumber) & 1); } //***************************************************************************** @@ -198,13 +196,13 @@ GPIO_readDio( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE uint32_t -GPIO_readMultiDio( uint32_t dioMask ) +GPIO_readMultiDio(uint32_t dioMask) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); // Return the input value from the specified DIOs. - return ( HWREG( GPIO_BASE + GPIO_O_DIN31_0 ) & dioMask ); + return (HWREG(GPIO_BASE + GPIO_O_DIN31_0) & dioMask); } //***************************************************************************** @@ -222,14 +220,14 @@ GPIO_readMultiDio( uint32_t dioMask ) // //***************************************************************************** __STATIC_INLINE void -GPIO_writeDio( uint32_t dioNumber, uint32_t value ) +GPIO_writeDio(uint32_t dioNumber, uint32_t value) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); - ASSERT(( value == 0 ) || ( value == 1 )); + ASSERT(dioNumberLegal(dioNumber)); + ASSERT((value == 0) || (value == 1)); // Write 0 or 1 to the byte indexed DOUT map - HWREGB( GPIO_BASE + dioNumber ) = value; + HWREGB(GPIO_BASE + dioNumber) = value; } //***************************************************************************** @@ -254,14 +252,14 @@ GPIO_writeDio( uint32_t dioNumber, uint32_t value ) // //***************************************************************************** __STATIC_INLINE void -GPIO_writeMultiDio( uint32_t dioMask, uint32_t bitVectoredValue ) +GPIO_writeMultiDio(uint32_t dioMask, uint32_t bitVectoredValue) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); - HWREG( GPIO_BASE + GPIO_O_DOUT31_0 ) = - ( HWREG( GPIO_BASE + GPIO_O_DOUT31_0 ) & ~dioMask ) | - ( bitVectoredValue & dioMask ); + HWREG(GPIO_BASE + GPIO_O_DOUT31_0) = + (HWREG(GPIO_BASE + GPIO_O_DOUT31_0) & ~dioMask) | + (bitVectoredValue & dioMask); } //***************************************************************************** @@ -276,13 +274,13 @@ GPIO_writeMultiDio( uint32_t dioMask, uint32_t bitVectoredValue ) // //***************************************************************************** __STATIC_INLINE void -GPIO_setDio( uint32_t dioNumber ) +GPIO_setDio(uint32_t dioNumber) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); + ASSERT(dioNumberLegal(dioNumber)); // Set the specified DIO. - HWREG( GPIO_BASE + GPIO_O_DOUTSET31_0 ) = ( 1 << dioNumber ); + HWREG(GPIO_BASE + GPIO_O_DOUTSET31_0) = (1 << dioNumber); } //***************************************************************************** @@ -301,13 +299,13 @@ GPIO_setDio( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE void -GPIO_setMultiDio( uint32_t dioMask ) +GPIO_setMultiDio(uint32_t dioMask) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); // Set the DIOs. - HWREG( GPIO_BASE + GPIO_O_DOUTSET31_0 ) = dioMask; + HWREG(GPIO_BASE + GPIO_O_DOUTSET31_0) = dioMask; } //***************************************************************************** @@ -322,13 +320,13 @@ GPIO_setMultiDio( uint32_t dioMask ) // //***************************************************************************** __STATIC_INLINE void -GPIO_clearDio( uint32_t dioNumber ) +GPIO_clearDio(uint32_t dioNumber) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); + ASSERT(dioNumberLegal(dioNumber)); // Clear the specified DIO. - HWREG( GPIO_BASE + GPIO_O_DOUTCLR31_0 ) = ( 1 << dioNumber ); + HWREG(GPIO_BASE + GPIO_O_DOUTCLR31_0) = (1 << dioNumber); } //***************************************************************************** @@ -347,13 +345,13 @@ GPIO_clearDio( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE void -GPIO_clearMultiDio( uint32_t dioMask ) +GPIO_clearMultiDio(uint32_t dioMask) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); // Clear the DIOs. - HWREG( GPIO_BASE + GPIO_O_DOUTCLR31_0 ) = dioMask; + HWREG(GPIO_BASE + GPIO_O_DOUTCLR31_0) = dioMask; } //***************************************************************************** @@ -368,13 +366,13 @@ GPIO_clearMultiDio( uint32_t dioMask ) // //***************************************************************************** __STATIC_INLINE void -GPIO_toggleDio( uint32_t dioNumber ) +GPIO_toggleDio(uint32_t dioNumber) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); + ASSERT(dioNumberLegal(dioNumber)); // Toggle the specified DIO. - HWREG( GPIO_BASE + GPIO_O_DOUTTGL31_0 ) = ( 1 << dioNumber ); + HWREG(GPIO_BASE + GPIO_O_DOUTTGL31_0) = (1 << dioNumber); } //***************************************************************************** @@ -393,13 +391,13 @@ GPIO_toggleDio( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE void -GPIO_toggleMultiDio( uint32_t dioMask ) +GPIO_toggleMultiDio(uint32_t dioMask) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); // Toggle the DIOs. - HWREG( GPIO_BASE + GPIO_O_DOUTTGL31_0 ) = dioMask; + HWREG(GPIO_BASE + GPIO_O_DOUTTGL31_0) = dioMask; } //***************************************************************************** @@ -419,13 +417,13 @@ GPIO_toggleMultiDio( uint32_t dioMask ) // //***************************************************************************** __STATIC_INLINE uint32_t -GPIO_getOutputEnableDio( uint32_t dioNumber ) +GPIO_getOutputEnableDio(uint32_t dioNumber) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); + ASSERT(dioNumberLegal(dioNumber)); // Return the output enable status for the specified DIO. - return (( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) >> dioNumber ) & 1 ); + return ((HWREG(GPIO_BASE + GPIO_O_DOE31_0) >> dioNumber) & 1); } //***************************************************************************** @@ -449,13 +447,13 @@ GPIO_getOutputEnableDio( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE uint32_t -GPIO_getOutputEnableMultiDio( uint32_t dioMask ) +GPIO_getOutputEnableMultiDio(uint32_t dioMask) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); // Return the output enable value for the specified DIOs. - return ( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) & dioMask ); + return (HWREG(GPIO_BASE + GPIO_O_DOE31_0) & dioMask); } //***************************************************************************** @@ -476,15 +474,15 @@ GPIO_getOutputEnableMultiDio( uint32_t dioMask ) // //***************************************************************************** __STATIC_INLINE void -GPIO_setOutputEnableDio( uint32_t dioNumber, uint32_t outputEnableValue ) +GPIO_setOutputEnableDio(uint32_t dioNumber, uint32_t outputEnableValue) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); - ASSERT(( outputEnableValue == GPIO_OUTPUT_DISABLE ) || - ( outputEnableValue == GPIO_OUTPUT_ENABLE ) ); + ASSERT(dioNumberLegal(dioNumber)); + ASSERT((outputEnableValue == GPIO_OUTPUT_DISABLE) || + (outputEnableValue == GPIO_OUTPUT_ENABLE)); // Update the output enable bit for the specified DIO. - HWREGBITW( GPIO_BASE + GPIO_O_DOE31_0, dioNumber ) = outputEnableValue; + HWREGBITW(GPIO_BASE + GPIO_O_DOE31_0, dioNumber) = outputEnableValue; } //***************************************************************************** @@ -512,14 +510,14 @@ GPIO_setOutputEnableDio( uint32_t dioNumber, uint32_t outputEnableValue ) // //***************************************************************************** __STATIC_INLINE void -GPIO_setOutputEnableMultiDio( uint32_t dioMask, uint32_t bitVectoredOutputEnable ) +GPIO_setOutputEnableMultiDio(uint32_t dioMask, uint32_t bitVectoredOutputEnable) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); - HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) = - ( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) & ~dioMask ) | - ( bitVectoredOutputEnable & dioMask ); + HWREG(GPIO_BASE + GPIO_O_DOE31_0) = + (HWREG(GPIO_BASE + GPIO_O_DOE31_0) & ~dioMask) | + (bitVectoredOutputEnable & dioMask); } //***************************************************************************** @@ -536,13 +534,13 @@ GPIO_setOutputEnableMultiDio( uint32_t dioMask, uint32_t bitVectoredOutputEnable // //***************************************************************************** __STATIC_INLINE uint32_t -GPIO_getEventDio( uint32_t dioNumber ) +GPIO_getEventDio(uint32_t dioNumber) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); + ASSERT(dioNumberLegal(dioNumber)); // Return the event status for the specified DIO. - return (( HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) >> dioNumber ) & 1 ); + return ((HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0) >> dioNumber) & 1); } //***************************************************************************** @@ -567,13 +565,13 @@ GPIO_getEventDio( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE uint32_t -GPIO_getEventMultiDio( uint32_t dioMask ) +GPIO_getEventMultiDio(uint32_t dioMask) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); // Return the event status for the specified DIO. - return ( HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) & dioMask ); + return (HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0) & dioMask); } //***************************************************************************** @@ -588,13 +586,13 @@ GPIO_getEventMultiDio( uint32_t dioMask ) // //***************************************************************************** __STATIC_INLINE void -GPIO_clearEventDio( uint32_t dioNumber ) +GPIO_clearEventDio(uint32_t dioNumber) { // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); + ASSERT(dioNumberLegal(dioNumber)); // Clear the event status for the specified DIO. - HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) = ( 1 << dioNumber ); + HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0) = (1 << dioNumber); } //***************************************************************************** @@ -614,13 +612,13 @@ GPIO_clearEventDio( uint32_t dioNumber ) // //***************************************************************************** __STATIC_INLINE void -GPIO_clearEventMultiDio( uint32_t dioMask ) +GPIO_clearEventMultiDio(uint32_t dioMask) { // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); + ASSERT(dioMask & GPIO_DIO_ALL_MASK); // Clear the event status for the specified DIOs. - HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) = dioMask; + HWREG(GPIO_BASE + GPIO_O_EVFLAGS31_0) = dioMask; } //***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/gpio_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/gpio_doc.h index b4548af..0fe98bb 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/gpio_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/gpio_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: gpio_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: gpio_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup gpio_api //! @{ //! \section sec_gpio Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/group_analog_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/group_analog_doc.h index d6346b3..755fa72 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/group_analog_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/group_analog_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: group_analog_doc.h -* Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016) -* Revision: 47080 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: group_analog_doc.h + * Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016) + * Revision: 47080 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup analog_group //! @{ //! \section sec_analog Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/group_aon_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/group_aon_doc.h index c5056d9..ee6b114 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/group_aon_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/group_aon_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: group_aon_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: group_aon_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup aon_group //! @{ //! \section sec_aon Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/group_aux_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/group_aux_doc.h index 63ddcfd..b3c5402 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/group_aux_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/group_aux_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: group_aux_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: group_aux_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup aux_group //! @{ //! \section sec_aux Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2c.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2c.h index c4ece78..5361dbf 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2c.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2c.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: i2c.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and prototypes for the I2C. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: i2c.h + * Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) + * Revision: 49048 + * + * Description: Defines and prototypes for the I2C. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,20 +55,19 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" +#include "../inc/hw_i2c.h" #include "../inc/hw_ints.h" #include "../inc/hw_memmap.h" -#include "../inc/hw_i2c.h" #include "../inc/hw_sysctl.h" +#include "../inc/hw_types.h" +#include "cpu.h" #include "debug.h" #include "interrupt.h" -#include "cpu.h" +#include +#include //***************************************************************************** // @@ -84,10 +83,10 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define I2CMasterInitExpClk NOROM_I2CMasterInitExpClk -#define I2CMasterErr NOROM_I2CMasterErr -#define I2CIntRegister NOROM_I2CIntRegister -#define I2CIntUnregister NOROM_I2CIntUnregister +#define I2CMasterInitExpClk NOROM_I2CMasterInitExpClk +#define I2CMasterErr NOROM_I2CMasterErr +#define I2CIntRegister NOROM_I2CIntRegister +#define I2CIntUnregister NOROM_I2CIntUnregister #endif //***************************************************************************** @@ -95,25 +94,25 @@ extern "C" // I2C Master commands // //***************************************************************************** -#define I2C_MASTER_CMD_SINGLE_SEND \ +#define I2C_MASTER_CMD_SINGLE_SEND \ 0x00000007 -#define I2C_MASTER_CMD_SINGLE_RECEIVE \ +#define I2C_MASTER_CMD_SINGLE_RECEIVE \ 0x00000007 -#define I2C_MASTER_CMD_BURST_SEND_START \ +#define I2C_MASTER_CMD_BURST_SEND_START \ 0x00000003 -#define I2C_MASTER_CMD_BURST_SEND_CONT \ +#define I2C_MASTER_CMD_BURST_SEND_CONT \ 0x00000001 -#define I2C_MASTER_CMD_BURST_SEND_FINISH \ +#define I2C_MASTER_CMD_BURST_SEND_FINISH \ 0x00000005 -#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ +#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ 0x00000004 -#define I2C_MASTER_CMD_BURST_RECEIVE_START \ +#define I2C_MASTER_CMD_BURST_RECEIVE_START \ 0x0000000b -#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ +#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ 0x00000009 -#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ +#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ 0x00000005 -#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ +#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ 0x00000004 //***************************************************************************** @@ -121,7 +120,7 @@ extern "C" // I2C Master error status // //***************************************************************************** -#define I2C_MASTER_ERR_NONE 0 +#define I2C_MASTER_ERR_NONE 0 #define I2C_MASTER_ERR_ADDR_ACK 0x00000004 #define I2C_MASTER_ERR_DATA_ACK 0x00000008 #define I2C_MASTER_ERR_ARB_LOST 0x00000010 @@ -131,19 +130,19 @@ extern "C" // I2C Slave action requests // //***************************************************************************** -#define I2C_SLAVE_ACT_NONE 0 -#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data -#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data -#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte +#define I2C_SLAVE_ACT_NONE 0 +#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data +#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data +#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte //***************************************************************************** // // I2C Slave interrupts // //***************************************************************************** -#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt. -#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt. -#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt. +#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt. +#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt. +#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt. //***************************************************************************** // @@ -937,20 +936,20 @@ extern void I2CIntUnregister(uint32_t ui32Base); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_I2CMasterInitExpClk -#undef I2CMasterInitExpClk -#define I2CMasterInitExpClk ROM_I2CMasterInitExpClk +#undef I2CMasterInitExpClk +#define I2CMasterInitExpClk ROM_I2CMasterInitExpClk #endif #ifdef ROM_I2CMasterErr -#undef I2CMasterErr -#define I2CMasterErr ROM_I2CMasterErr +#undef I2CMasterErr +#define I2CMasterErr ROM_I2CMasterErr #endif #ifdef ROM_I2CIntRegister -#undef I2CIntRegister -#define I2CIntRegister ROM_I2CIntRegister +#undef I2CIntRegister +#define I2CIntRegister ROM_I2CIntRegister #endif #ifdef ROM_I2CIntUnregister -#undef I2CIntUnregister -#define I2CIntUnregister ROM_I2CIntUnregister +#undef I2CIntUnregister +#define I2CIntUnregister ROM_I2CIntUnregister #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2c_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2c_doc.h index c339318..c2206dd 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2c_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2c_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: i2c_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: i2c_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup i2c_api //! @{ //! \section sec_i2c Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2s.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2s.h index 116b252..c158837 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2s.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2s.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: i2s.h -* Revised: 2018-11-16 11:16:53 +0100 (Fri, 16 Nov 2018) -* Revision: 53356 -* -* Description: Defines and prototypes for the I2S. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: i2s.h + * Revised: 2018-11-16 11:16:53 +0100 (Fri, 16 Nov 2018) + * Revision: 53356 + * + * Description: Defines and prototypes for the I2S. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //**************************************************************************** // @@ -55,18 +55,17 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" #include "../inc/hw_i2s.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "debug.h" #include "interrupt.h" +#include +#include //***************************************************************************** // @@ -82,14 +81,14 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define I2SEnable NOROM_I2SEnable -#define I2SAudioFormatConfigure NOROM_I2SAudioFormatConfigure -#define I2SChannelConfigure NOROM_I2SChannelConfigure -#define I2SBufferConfig NOROM_I2SBufferConfig -#define I2SPointerUpdate NOROM_I2SPointerUpdate -#define I2SPointerSet NOROM_I2SPointerSet -#define I2SSampleStampConfigure NOROM_I2SSampleStampConfigure -#define I2SSampleStampGet NOROM_I2SSampleStampGet +#define I2SEnable NOROM_I2SEnable +#define I2SAudioFormatConfigure NOROM_I2SAudioFormatConfigure +#define I2SChannelConfigure NOROM_I2SChannelConfigure +#define I2SBufferConfig NOROM_I2SBufferConfig +#define I2SPointerUpdate NOROM_I2SPointerUpdate +#define I2SPointerSet NOROM_I2SPointerSet +#define I2SSampleStampConfigure NOROM_I2SSampleStampConfigure +#define I2SSampleStampGet NOROM_I2SSampleStampGet #endif //***************************************************************************** @@ -118,15 +117,15 @@ extern "C" #ifndef DEPRECATED typedef struct { - uint16_t ui16DMABufSize; //!< Size of DMA buffer in number of samples. - uint16_t ui16ChBufSize; //!< Size of Channel buffer. - uint8_t ui8InChan; //!< Input Channel. - uint8_t ui8OutChan; //!< Output Channel. - uint16_t ui16MemLen; //!< Length of the audio words stored in memory. - uint32_t ui32InBase; //!< Base address of the input buffer. - uint32_t ui32InOffset; //!< Value of the current input pointer offset. - uint32_t ui32OutBase; //!< Base address of the output buffer. - uint32_t ui32OutOffset; //!< Value of the current output pointer offset. + uint16_t ui16DMABufSize; //!< Size of DMA buffer in number of samples. + uint16_t ui16ChBufSize; //!< Size of Channel buffer. + uint8_t ui8InChan; //!< Input Channel. + uint8_t ui8OutChan; //!< Output Channel. + uint16_t ui16MemLen; //!< Length of the audio words stored in memory. + uint32_t ui32InBase; //!< Base address of the input buffer. + uint32_t ui32InOffset; //!< Value of the current input pointer offset. + uint32_t ui32OutBase; //!< Base address of the output buffer. + uint32_t ui32OutOffset; //!< Value of the current output pointer offset. } I2SControlTable; #endif @@ -151,9 +150,9 @@ extern I2SControlTable* g_pControlTable; // //***************************************************************************** #ifndef DEPRECATED -#define I2S_DMA_BUF_SIZE_64 0x00000040 -#define I2S_DMA_BUF_SIZE_128 0x00000080 -#define I2S_DMA_BUF_SIZE_256 0x00000100 +#define I2S_DMA_BUF_SIZE_64 0x00000040 +#define I2S_DMA_BUF_SIZE_128 0x00000080 +#define I2S_DMA_BUF_SIZE_256 0x00000100 #endif //***************************************************************************** @@ -162,10 +161,10 @@ extern I2SControlTable* g_pControlTable; // //***************************************************************************** #ifndef DEPRECATED -#define I2S_EXT_WCLK 0x00000001 -#define I2S_INT_WCLK 0x00000002 -#define I2S_INVERT_WCLK 0x00000004 -#define I2S_NORMAL_WCLK 0x00000000 +#define I2S_EXT_WCLK 0x00000001 +#define I2S_INT_WCLK 0x00000002 +#define I2S_INVERT_WCLK 0x00000004 +#define I2S_NORMAL_WCLK 0x00000000 #endif //***************************************************************************** @@ -174,10 +173,10 @@ extern I2SControlTable* g_pControlTable; // //***************************************************************************** #ifndef DEPRECATED -#define I2S_LINE_UNUSED 0x00000000 -#define I2S_LINE_INPUT 0x00000001 -#define I2S_LINE_OUTPUT 0x00000002 -#define I2S_LINE_MASK 0x00000003 +#define I2S_LINE_UNUSED 0x00000000 +#define I2S_LINE_INPUT 0x00000001 +#define I2S_LINE_OUTPUT 0x00000002 +#define I2S_LINE_MASK 0x00000003 #endif //***************************************************************************** @@ -186,42 +185,42 @@ extern I2SControlTable* g_pControlTable; // //***************************************************************************** #ifndef DEPRECATED -#define I2S_CHAN0_ACT 0x00000100 -#define I2S_CHAN1_ACT 0x00000200 -#define I2S_CHAN2_ACT 0x00000400 -#define I2S_CHAN3_ACT 0x00000800 -#define I2S_CHAN4_ACT 0x00001000 -#define I2S_CHAN5_ACT 0x00002000 -#define I2S_CHAN6_ACT 0x00004000 -#define I2S_CHAN7_ACT 0x00008000 -#define I2S_MONO_MODE 0x00000100 -#define I2S_STEREO_MODE 0x00000300 -#define I2S_CHAN_CFG_MASK 0x0000FF00 +#define I2S_CHAN0_ACT 0x00000100 +#define I2S_CHAN1_ACT 0x00000200 +#define I2S_CHAN2_ACT 0x00000400 +#define I2S_CHAN3_ACT 0x00000800 +#define I2S_CHAN4_ACT 0x00001000 +#define I2S_CHAN5_ACT 0x00002000 +#define I2S_CHAN6_ACT 0x00004000 +#define I2S_CHAN7_ACT 0x00008000 +#define I2S_MONO_MODE 0x00000100 +#define I2S_STEREO_MODE 0x00000300 +#define I2S_CHAN_CFG_MASK 0x0000FF00 #endif -#define I2S_CHAN0_MASK 0x00000001 -#define I2S_CHAN1_MASK 0x00000002 -#define I2S_CHAN2_MASK 0x00000004 -#define I2S_CHAN3_MASK 0x00000008 -#define I2S_CHAN4_MASK 0x00000010 -#define I2S_CHAN5_MASK 0x00000020 -#define I2S_CHAN6_MASK 0x00000040 -#define I2S_CHAN7_MASK 0x00000080 +#define I2S_CHAN0_MASK 0x00000001 +#define I2S_CHAN1_MASK 0x00000002 +#define I2S_CHAN2_MASK 0x00000004 +#define I2S_CHAN3_MASK 0x00000008 +#define I2S_CHAN4_MASK 0x00000010 +#define I2S_CHAN5_MASK 0x00000020 +#define I2S_CHAN6_MASK 0x00000040 +#define I2S_CHAN7_MASK 0x00000080 //***************************************************************************** // // Defines for the audio format configuration // //***************************************************************************** -#define I2S_MEM_LENGTH_16 0x00000000 // 16 bit size of word in memory -#define I2S_MEM_LENGTH_24 0x00000080 // 24 bit size of word in memory -#define I2S_POS_EDGE 0x00000040 // Sample on positive edge -#define I2S_NEG_EDGE 0x00000000 // Sample on negative edge -#define I2S_DUAL_PHASE_FMT 0x00000020 // Dual Phased audio format -#define I2S_SINGLE_PHASE_FMT 0x00000000 // Single Phased audio format -#define I2S_WORD_LENGTH_8 0x00000008 // Word length is 8 bits -#define I2S_WORD_LENGTH_16 0x00000010 // Word length is 16 bits -#define I2S_WORD_LENGTH_24 0x00000018 // Word length is 24 bits +#define I2S_MEM_LENGTH_16 0x00000000 // 16 bit size of word in memory +#define I2S_MEM_LENGTH_24 0x00000080 // 24 bit size of word in memory +#define I2S_POS_EDGE 0x00000040 // Sample on positive edge +#define I2S_NEG_EDGE 0x00000000 // Sample on negative edge +#define I2S_DUAL_PHASE_FMT 0x00000020 // Dual Phased audio format +#define I2S_SINGLE_PHASE_FMT 0x00000000 // Single Phased audio format +#define I2S_WORD_LENGTH_8 0x00000008 // Word length is 8 bits +#define I2S_WORD_LENGTH_16 0x00000010 // Word length is 16 bits +#define I2S_WORD_LENGTH_24 0x00000018 // Word length is 24 bits //***************************************************************************** // @@ -229,10 +228,10 @@ extern I2SControlTable* g_pControlTable; // //***************************************************************************** #ifndef DEPRECATED -#define I2S_STMP0 0x00000001 // Sample stamp counter channel 0 -#define I2S_STMP1 0x00000002 // Sample stamp counter channel 1 +#define I2S_STMP0 0x00000001 // Sample stamp counter channel 0 +#define I2S_STMP1 0x00000002 // Sample stamp counter channel 1 #endif -#define I2S_STMP_SATURATION 0x0000FFFF // The saturation value used when +#define I2S_STMP_SATURATION 0x0000FFFF // The saturation value used when // calculating the sample stamp //***************************************************************************** @@ -240,13 +239,13 @@ extern I2SControlTable* g_pControlTable; // Defines for the interrupt // //***************************************************************************** -#define I2S_INT_DMA_IN 0x00000020 // DMA output buffer full interrupt -#define I2S_INT_DMA_OUT 0x00000010 // DMA input buffer empty interrupt -#define I2S_INT_TIMEOUT 0x00000008 // Word Clock Timeout -#define I2S_INT_BUS_ERR 0x00000004 // DMA Bus error -#define I2S_INT_WCLK_ERR 0x00000002 // Word Clock error -#define I2S_INT_PTR_ERR 0x00000001 // Data pointer error (DMA data was not updated in time). -#define I2S_INT_ALL 0x0000003F // All interrupts +#define I2S_INT_DMA_IN 0x00000020 // DMA output buffer full interrupt +#define I2S_INT_DMA_OUT 0x00000010 // DMA input buffer empty interrupt +#define I2S_INT_TIMEOUT 0x00000008 // Word Clock Timeout +#define I2S_INT_BUS_ERR 0x00000004 // DMA Bus error +#define I2S_INT_WCLK_ERR 0x00000002 // Word Clock error +#define I2S_INT_PTR_ERR 0x00000001 // Data pointer error (DMA data was not updated in time). +#define I2S_INT_ALL 0x0000003F // All interrupts //***************************************************************************** // @@ -842,7 +841,6 @@ I2SSampleStampDisable(uint32_t ui32Base) // Clear the enable bit. HWREG(I2S0_BASE + I2S_O_STMPCTL) = 0; - } //***************************************************************************** @@ -955,11 +953,11 @@ __STATIC_INLINE void I2SStop(uint32_t ui32Base) //***************************************************************************** __STATIC_INLINE void I2SFormatConfigure(uint32_t ui32Base, - uint8_t ui8iDataDelay, - uint8_t ui8iMemory24Bits, - uint8_t ui8iSamplingEdge, - bool boolDualPhase, - uint8_t ui8BitsPerSample, + uint8_t ui8iDataDelay, + uint8_t ui8iMemory24Bits, + uint8_t ui8iSamplingEdge, + bool boolDualPhase, + uint8_t ui8BitsPerSample, uint16_t ui16transmissionDelay) { // Check the arguments. @@ -969,11 +967,11 @@ I2SFormatConfigure(uint32_t ui32Base, // Setup register AIFFMTCFG Source. HWREGH(I2S0_BASE + I2S_O_AIFFMTCFG) = - (ui8iDataDelay << I2S_AIFFMTCFG_DATA_DELAY_S) | - (ui8iMemory24Bits << I2S_AIFFMTCFG_MEM_LEN_24_S) | - (ui8iSamplingEdge << I2S_AIFFMTCFG_SMPL_EDGE_S ) | - (boolDualPhase << I2S_AIFFMTCFG_DUAL_PHASE_S) | - (ui8BitsPerSample << I2S_AIFFMTCFG_WORD_LEN_S ); + (ui8iDataDelay << I2S_AIFFMTCFG_DATA_DELAY_S) | + (ui8iMemory24Bits << I2S_AIFFMTCFG_MEM_LEN_24_S) | + (ui8iSamplingEdge << I2S_AIFFMTCFG_SMPL_EDGE_S) | + (boolDualPhase << I2S_AIFFMTCFG_DUAL_PHASE_S) | + (ui8BitsPerSample << I2S_AIFFMTCFG_WORD_LEN_S); // Number of WCLK periods before the first read / write HWREGH(I2S0_BASE + I2S_O_STMPWPER) = ui16transmissionDelay; @@ -1022,8 +1020,8 @@ I2SFormatConfigure(uint32_t ui32Base, //**************************************************************************** __STATIC_INLINE void I2SFrameConfigure(uint32_t ui32Base, - uint8_t ui8StatusAD0, uint8_t ui8ChanAD0, - uint8_t ui8StatusAD1, uint8_t ui8ChanAD1) + uint8_t ui8StatusAD0, uint8_t ui8ChanAD0, + uint8_t ui8StatusAD1, uint8_t ui8ChanAD1) { // Check the arguments. ASSERT(I2SBaseValid(ui32Base)); @@ -1058,8 +1056,8 @@ I2SFrameConfigure(uint32_t ui32Base, //**************************************************************************** __STATIC_INLINE void I2SWclkConfigure(uint32_t ui32Base, - bool boolMaster, - bool boolWCLKInvert) + bool boolMaster, + bool boolWCLKInvert) { // Check the arguments. ASSERT(I2SBaseValid(ui32Base)); @@ -1071,8 +1069,8 @@ I2SWclkConfigure(uint32_t ui32Base, // Setup register WCLK Source. HWREGB(I2S0_BASE + I2S_O_AIFWCLKSRC) = - ((ui8ClkSource << I2S_AIFWCLKSRC_WCLK_SRC_S) | - (boolWCLKInvert << I2S_AIFWCLKSRC_WCLK_INV_S )); + ((ui8ClkSource << I2S_AIFWCLKSRC_WCLK_SRC_S) | + (boolWCLKInvert << I2S_AIFWCLKSRC_WCLK_INV_S)); } //**************************************************************************** @@ -1151,7 +1149,6 @@ I2SInPointerNextGet(uint32_t ui32Base) return (HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT)); } - //**************************************************************************** // //! \brief Get value stored in PTR NEXT OUT register @@ -1306,36 +1303,36 @@ I2SWclkCounterReset(uint32_t ui32Base) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_I2SEnable -#undef I2SEnable -#define I2SEnable ROM_I2SEnable +#undef I2SEnable +#define I2SEnable ROM_I2SEnable #endif #ifdef ROM_I2SAudioFormatConfigure -#undef I2SAudioFormatConfigure -#define I2SAudioFormatConfigure ROM_I2SAudioFormatConfigure +#undef I2SAudioFormatConfigure +#define I2SAudioFormatConfigure ROM_I2SAudioFormatConfigure #endif #ifdef ROM_I2SChannelConfigure -#undef I2SChannelConfigure -#define I2SChannelConfigure ROM_I2SChannelConfigure +#undef I2SChannelConfigure +#define I2SChannelConfigure ROM_I2SChannelConfigure #endif #ifdef ROM_I2SBufferConfig -#undef I2SBufferConfig -#define I2SBufferConfig ROM_I2SBufferConfig +#undef I2SBufferConfig +#define I2SBufferConfig ROM_I2SBufferConfig #endif #ifdef ROM_I2SPointerUpdate -#undef I2SPointerUpdate -#define I2SPointerUpdate ROM_I2SPointerUpdate +#undef I2SPointerUpdate +#define I2SPointerUpdate ROM_I2SPointerUpdate #endif #ifdef ROM_I2SPointerSet -#undef I2SPointerSet -#define I2SPointerSet ROM_I2SPointerSet +#undef I2SPointerSet +#define I2SPointerSet ROM_I2SPointerSet #endif #ifdef ROM_I2SSampleStampConfigure -#undef I2SSampleStampConfigure -#define I2SSampleStampConfigure ROM_I2SSampleStampConfigure +#undef I2SSampleStampConfigure +#define I2SSampleStampConfigure ROM_I2SSampleStampConfigure #endif #ifdef ROM_I2SSampleStampGet -#undef I2SSampleStampGet -#define I2SSampleStampGet ROM_I2SSampleStampGet +#undef I2SSampleStampGet +#define I2SSampleStampGet ROM_I2SSampleStampGet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2s_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2s_doc.h index 27ddceb..d72ccd4 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2s_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/i2s_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: i2s_doc.h -* Revised: $$ -* Revision: $$ -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: i2s_doc.h + * Revised: $$ + * Revision: $$ + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup i2s_api //! @{ //! \section sec_i2s Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/interrupt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/interrupt.h index c297aeb..031bea1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/interrupt.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/interrupt.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: interrupt.h -* Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017) -* Revision: 50272 -* -* Description: Defines and prototypes for the NVIC Interrupt Controller -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: interrupt.h + * Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017) + * Revision: 50272 + * + * Description: Defines and prototypes for the NVIC Interrupt Controller + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,17 +55,16 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_ints.h" +#include "../inc/hw_nvic.h" +#include "../inc/hw_types.h" +#include "cpu.h" +#include "debug.h" #include #include -#include "../inc/hw_ints.h" -#include "../inc/hw_types.h" -#include "../inc/hw_nvic.h" -#include "debug.h" -#include "cpu.h" //***************************************************************************** // @@ -81,17 +80,17 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define IntRegister NOROM_IntRegister -#define IntUnregister NOROM_IntUnregister -#define IntPriorityGroupingSet NOROM_IntPriorityGroupingSet -#define IntPriorityGroupingGet NOROM_IntPriorityGroupingGet -#define IntPrioritySet NOROM_IntPrioritySet -#define IntPriorityGet NOROM_IntPriorityGet -#define IntEnable NOROM_IntEnable -#define IntDisable NOROM_IntDisable -#define IntPendSet NOROM_IntPendSet -#define IntPendGet NOROM_IntPendGet -#define IntPendClear NOROM_IntPendClear +#define IntRegister NOROM_IntRegister +#define IntUnregister NOROM_IntUnregister +#define IntPriorityGroupingSet NOROM_IntPriorityGroupingSet +#define IntPriorityGroupingGet NOROM_IntPriorityGroupingGet +#define IntPrioritySet NOROM_IntPrioritySet +#define IntPriorityGet NOROM_IntPriorityGet +#define IntEnable NOROM_IntEnable +#define IntDisable NOROM_IntDisable +#define IntPendSet NOROM_IntPendSet +#define IntPendGet NOROM_IntPendGet +#define IntPendClear NOROM_IntPendClear #endif //***************************************************************************** @@ -104,15 +103,15 @@ extern "C" // INT_PRIORITY_MASK = ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) // //***************************************************************************** -#define INT_PRIORITY_MASK 0x000000E0 -#define INT_PRI_LEVEL0 0x00000000 -#define INT_PRI_LEVEL1 0x00000020 -#define INT_PRI_LEVEL2 0x00000040 -#define INT_PRI_LEVEL3 0x00000060 -#define INT_PRI_LEVEL4 0x00000080 -#define INT_PRI_LEVEL5 0x000000A0 -#define INT_PRI_LEVEL6 0x000000C0 -#define INT_PRI_LEVEL7 0x000000E0 +#define INT_PRIORITY_MASK 0x000000E0 +#define INT_PRI_LEVEL0 0x00000000 +#define INT_PRI_LEVEL1 0x00000020 +#define INT_PRI_LEVEL2 0x00000040 +#define INT_PRI_LEVEL3 0x00000060 +#define INT_PRI_LEVEL4 0x00000080 +#define INT_PRI_LEVEL5 0x000000A0 +#define INT_PRI_LEVEL6 0x000000C0 +#define INT_PRI_LEVEL7 0x000000E0 //***************************************************************************** // @@ -637,48 +636,48 @@ IntPriorityMaskGet(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_IntRegister -#undef IntRegister -#define IntRegister ROM_IntRegister +#undef IntRegister +#define IntRegister ROM_IntRegister #endif #ifdef ROM_IntUnregister -#undef IntUnregister -#define IntUnregister ROM_IntUnregister +#undef IntUnregister +#define IntUnregister ROM_IntUnregister #endif #ifdef ROM_IntPriorityGroupingSet -#undef IntPriorityGroupingSet -#define IntPriorityGroupingSet ROM_IntPriorityGroupingSet +#undef IntPriorityGroupingSet +#define IntPriorityGroupingSet ROM_IntPriorityGroupingSet #endif #ifdef ROM_IntPriorityGroupingGet -#undef IntPriorityGroupingGet -#define IntPriorityGroupingGet ROM_IntPriorityGroupingGet +#undef IntPriorityGroupingGet +#define IntPriorityGroupingGet ROM_IntPriorityGroupingGet #endif #ifdef ROM_IntPrioritySet -#undef IntPrioritySet -#define IntPrioritySet ROM_IntPrioritySet +#undef IntPrioritySet +#define IntPrioritySet ROM_IntPrioritySet #endif #ifdef ROM_IntPriorityGet -#undef IntPriorityGet -#define IntPriorityGet ROM_IntPriorityGet +#undef IntPriorityGet +#define IntPriorityGet ROM_IntPriorityGet #endif #ifdef ROM_IntEnable -#undef IntEnable -#define IntEnable ROM_IntEnable +#undef IntEnable +#define IntEnable ROM_IntEnable #endif #ifdef ROM_IntDisable -#undef IntDisable -#define IntDisable ROM_IntDisable +#undef IntDisable +#define IntDisable ROM_IntDisable #endif #ifdef ROM_IntPendSet -#undef IntPendSet -#define IntPendSet ROM_IntPendSet +#undef IntPendSet +#define IntPendSet ROM_IntPendSet #endif #ifdef ROM_IntPendGet -#undef IntPendGet -#define IntPendGet ROM_IntPendGet +#undef IntPendGet +#define IntPendGet ROM_IntPendGet #endif #ifdef ROM_IntPendClear -#undef IntPendClear -#define IntPendClear ROM_IntPendClear +#undef IntPendClear +#define IntPendClear ROM_IntPendClear #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/interrupt_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/interrupt_doc.h index ff02174..903851c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/interrupt_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/interrupt_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: interrupt_doc.h -* Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017) -* Revision: 50272 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: interrupt_doc.h + * Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017) + * Revision: 50272 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup interrupt_api //! @{ //! \section sec_interrupt Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ioc.h index b612410..6002559 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ioc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ioc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: ioc.h -* Revised: 2017-11-02 14:16:14 +0100 (Thu, 02 Nov 2017) -* Revision: 50156 -* -* Description: Defines and prototypes for the IO Controller. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: ioc.h + * Revised: 2017-11-02 14:16:14 +0100 (Thu, 02 Nov 2017) + * Revision: 50156 + * + * Description: Defines and prototypes for the IO Controller. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,19 +55,18 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ioc.h" #include "../inc/hw_ints.h" -#include "interrupt.h" +#include "../inc/hw_ioc.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "debug.h" #include "gpio.h" +#include "interrupt.h" +#include +#include //***************************************************************************** // @@ -83,26 +82,26 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define IOCPortConfigureSet NOROM_IOCPortConfigureSet -#define IOCPortConfigureGet NOROM_IOCPortConfigureGet -#define IOCIOShutdownSet NOROM_IOCIOShutdownSet -#define IOCIOModeSet NOROM_IOCIOModeSet -#define IOCIOIntSet NOROM_IOCIOIntSet -#define IOCIOPortPullSet NOROM_IOCIOPortPullSet -#define IOCIOHystSet NOROM_IOCIOHystSet -#define IOCIOInputSet NOROM_IOCIOInputSet -#define IOCIOSlewCtrlSet NOROM_IOCIOSlewCtrlSet -#define IOCIODrvStrengthSet NOROM_IOCIODrvStrengthSet -#define IOCIOPortIdSet NOROM_IOCIOPortIdSet -#define IOCIntEnable NOROM_IOCIntEnable -#define IOCIntDisable NOROM_IOCIntDisable -#define IOCPinTypeGpioInput NOROM_IOCPinTypeGpioInput -#define IOCPinTypeGpioOutput NOROM_IOCPinTypeGpioOutput -#define IOCPinTypeUart NOROM_IOCPinTypeUart -#define IOCPinTypeSsiMaster NOROM_IOCPinTypeSsiMaster -#define IOCPinTypeSsiSlave NOROM_IOCPinTypeSsiSlave -#define IOCPinTypeI2c NOROM_IOCPinTypeI2c -#define IOCPinTypeAux NOROM_IOCPinTypeAux +#define IOCPortConfigureSet NOROM_IOCPortConfigureSet +#define IOCPortConfigureGet NOROM_IOCPortConfigureGet +#define IOCIOShutdownSet NOROM_IOCIOShutdownSet +#define IOCIOModeSet NOROM_IOCIOModeSet +#define IOCIOIntSet NOROM_IOCIOIntSet +#define IOCIOPortPullSet NOROM_IOCIOPortPullSet +#define IOCIOHystSet NOROM_IOCIOHystSet +#define IOCIOInputSet NOROM_IOCIOInputSet +#define IOCIOSlewCtrlSet NOROM_IOCIOSlewCtrlSet +#define IOCIODrvStrengthSet NOROM_IOCIODrvStrengthSet +#define IOCIOPortIdSet NOROM_IOCIOPortIdSet +#define IOCIntEnable NOROM_IOCIntEnable +#define IOCIntDisable NOROM_IOCIntDisable +#define IOCPinTypeGpioInput NOROM_IOCPinTypeGpioInput +#define IOCPinTypeGpioOutput NOROM_IOCPinTypeGpioOutput +#define IOCPinTypeUart NOROM_IOCPinTypeUart +#define IOCPinTypeSsiMaster NOROM_IOCPinTypeSsiMaster +#define IOCPinTypeSsiSlave NOROM_IOCPinTypeSsiSlave +#define IOCPinTypeI2c NOROM_IOCPinTypeI2c +#define IOCPinTypeAux NOROM_IOCPinTypeAux #endif //***************************************************************************** @@ -117,41 +116,41 @@ extern "C" // The following fields are IO Id for the IOC module // //***************************************************************************** -#define IOID_0 0x00000000 // IO Id 0 -#define IOID_1 0x00000001 // IO Id 1 -#define IOID_2 0x00000002 // IO Id 2 -#define IOID_3 0x00000003 // IO Id 3 -#define IOID_4 0x00000004 // IO Id 4 -#define IOID_5 0x00000005 // IO Id 5 -#define IOID_6 0x00000006 // IO Id 6 -#define IOID_7 0x00000007 // IO Id 7 -#define IOID_8 0x00000008 // IO Id 8 -#define IOID_9 0x00000009 // IO Id 9 -#define IOID_10 0x0000000A // IO Id 10 -#define IOID_11 0x0000000B // IO Id 11 -#define IOID_12 0x0000000C // IO Id 12 -#define IOID_13 0x0000000D // IO Id 13 -#define IOID_14 0x0000000E // IO Id 14 -#define IOID_15 0x0000000F // IO Id 15 -#define IOID_16 0x00000010 // IO Id 16 -#define IOID_17 0x00000011 // IO Id 17 -#define IOID_18 0x00000012 // IO Id 18 -#define IOID_19 0x00000013 // IO Id 19 -#define IOID_20 0x00000014 // IO Id 20 -#define IOID_21 0x00000015 // IO Id 21 -#define IOID_22 0x00000016 // IO Id 22 -#define IOID_23 0x00000017 // IO Id 23 -#define IOID_24 0x00000018 // IO Id 24 -#define IOID_25 0x00000019 // IO Id 25 -#define IOID_26 0x0000001A // IO Id 26 -#define IOID_27 0x0000001B // IO Id 27 -#define IOID_28 0x0000001C // IO Id 28 -#define IOID_29 0x0000001D // IO Id 29 -#define IOID_30 0x0000001E // IO Id 30 -#define IOID_31 0x0000001F // IO Id 31 -#define IOID_UNUSED 0xFFFFFFFF // Unused IO Id +#define IOID_0 0x00000000 // IO Id 0 +#define IOID_1 0x00000001 // IO Id 1 +#define IOID_2 0x00000002 // IO Id 2 +#define IOID_3 0x00000003 // IO Id 3 +#define IOID_4 0x00000004 // IO Id 4 +#define IOID_5 0x00000005 // IO Id 5 +#define IOID_6 0x00000006 // IO Id 6 +#define IOID_7 0x00000007 // IO Id 7 +#define IOID_8 0x00000008 // IO Id 8 +#define IOID_9 0x00000009 // IO Id 9 +#define IOID_10 0x0000000A // IO Id 10 +#define IOID_11 0x0000000B // IO Id 11 +#define IOID_12 0x0000000C // IO Id 12 +#define IOID_13 0x0000000D // IO Id 13 +#define IOID_14 0x0000000E // IO Id 14 +#define IOID_15 0x0000000F // IO Id 15 +#define IOID_16 0x00000010 // IO Id 16 +#define IOID_17 0x00000011 // IO Id 17 +#define IOID_18 0x00000012 // IO Id 18 +#define IOID_19 0x00000013 // IO Id 19 +#define IOID_20 0x00000014 // IO Id 20 +#define IOID_21 0x00000015 // IO Id 21 +#define IOID_22 0x00000016 // IO Id 22 +#define IOID_23 0x00000017 // IO Id 23 +#define IOID_24 0x00000018 // IO Id 24 +#define IOID_25 0x00000019 // IO Id 25 +#define IOID_26 0x0000001A // IO Id 26 +#define IOID_27 0x0000001B // IO Id 27 +#define IOID_28 0x0000001C // IO Id 28 +#define IOID_29 0x0000001D // IO Id 29 +#define IOID_30 0x0000001E // IO Id 30 +#define IOID_31 0x0000001F // IO Id 31 +#define IOID_UNUSED 0xFFFFFFFF // Unused IO Id -#define IOC_IOID_MASK 0x000000FF // IOC IO Id bit mask +#define IOC_IOID_MASK 0x000000FF // IOC IO Id bit mask //***************************************************************************** // @@ -165,86 +164,86 @@ extern "C" // IOC Peripheral Port Mapping // //***************************************************************************** -#define IOC_PORT_GPIO 0x00000000 // Default general purpose IO usage -#define IOC_PORT_AON_CLK32K 0x00000007 // AON External 32kHz clock -#define IOC_PORT_AUX_IO 0x00000008 // AUX IO Pin -#define IOC_PORT_MCU_SSI0_RX 0x00000009 // MCU SSI0 Receive Pin -#define IOC_PORT_MCU_SSI0_TX 0x0000000A // MCU SSI0 Transmit Pin -#define IOC_PORT_MCU_SSI0_FSS 0x0000000B // MCU SSI0 FSS Pin -#define IOC_PORT_MCU_SSI0_CLK 0x0000000C // MCU SSI0 Clock Pin -#define IOC_PORT_MCU_I2C_MSSDA 0x0000000D // MCU I2C Data Pin -#define IOC_PORT_MCU_I2C_MSSCL 0x0000000E // MCU I2C Clock Pin -#define IOC_PORT_MCU_UART0_RX 0x0000000F // MCU UART0 Receive Pin -#define IOC_PORT_MCU_UART0_TX 0x00000010 // MCU UART0 Transmit Pin -#define IOC_PORT_MCU_UART0_CTS 0x00000011 // MCU UART0 Clear To Send Pin -#define IOC_PORT_MCU_UART0_RTS 0x00000012 // MCU UART0 Request To Send Pin -#define IOC_PORT_MCU_PORT_EVENT0 0x00000017 // MCU PORT EVENT 0 -#define IOC_PORT_MCU_PORT_EVENT1 0x00000018 // MCU PORT EVENT 1 -#define IOC_PORT_MCU_PORT_EVENT2 0x00000019 // MCU PORT EVENT 2 -#define IOC_PORT_MCU_PORT_EVENT3 0x0000001A // MCU PORT EVENT 3 -#define IOC_PORT_MCU_PORT_EVENT4 0x0000001B // MCU PORT EVENT 4 -#define IOC_PORT_MCU_PORT_EVENT5 0x0000001C // MCU PORT EVENT 5 -#define IOC_PORT_MCU_PORT_EVENT6 0x0000001D // MCU PORT EVENT 6 -#define IOC_PORT_MCU_PORT_EVENT7 0x0000001E // MCU PORT EVENT 7 -#define IOC_PORT_MCU_SWV 0x00000020 // Serial Wire Viewer -#define IOC_PORT_MCU_SSI1_RX 0x00000021 // MCU SSI1 Receive Pin -#define IOC_PORT_MCU_SSI1_TX 0x00000022 // MCU SSI1 Transmit Pin -#define IOC_PORT_MCU_SSI1_FSS 0x00000023 // MCU SSI1 FSS Pin -#define IOC_PORT_MCU_SSI1_CLK 0x00000024 // MCU SSI1 Clock Pin -#define IOC_PORT_MCU_I2S_AD0 0x00000025 // MCU I2S Data Pin 0 -#define IOC_PORT_MCU_I2S_AD1 0x00000026 // MCU I2S Data Pin 1 -#define IOC_PORT_MCU_I2S_WCLK 0x00000027 // MCU I2S Frame/Word Clock -#define IOC_PORT_MCU_I2S_BCLK 0x00000028 // MCU I2S Bit Clock -#define IOC_PORT_MCU_I2S_MCLK 0x00000029 // MCU I2S Master clock 2 -#define IOC_PORT_RFC_TRC 0x0000002E // RF Core Tracer -#define IOC_PORT_RFC_GPO0 0x0000002F // RC Core Data Out Pin 0 -#define IOC_PORT_RFC_GPO1 0x00000030 // RC Core Data Out Pin 1 -#define IOC_PORT_RFC_GPO2 0x00000031 // RC Core Data Out Pin 2 -#define IOC_PORT_RFC_GPO3 0x00000032 // RC Core Data Out Pin 3 -#define IOC_PORT_RFC_GPI0 0x00000033 // RC Core Data In Pin 0 -#define IOC_PORT_RFC_GPI1 0x00000034 // RC Core Data In Pin 1 -#define IOC_PORT_RFC_SMI_DL_OUT 0x00000035 // RF Core SMI Data Link Out -#define IOC_PORT_RFC_SMI_DL_IN 0x00000036 // RF Core SMI Data Link in -#define IOC_PORT_RFC_SMI_CL_OUT 0x00000037 // RF Core SMI Command Link Out -#define IOC_PORT_RFC_SMI_CL_IN 0x00000038 // RF Core SMI Command Link In +#define IOC_PORT_GPIO 0x00000000 // Default general purpose IO usage +#define IOC_PORT_AON_CLK32K 0x00000007 // AON External 32kHz clock +#define IOC_PORT_AUX_IO 0x00000008 // AUX IO Pin +#define IOC_PORT_MCU_SSI0_RX 0x00000009 // MCU SSI0 Receive Pin +#define IOC_PORT_MCU_SSI0_TX 0x0000000A // MCU SSI0 Transmit Pin +#define IOC_PORT_MCU_SSI0_FSS 0x0000000B // MCU SSI0 FSS Pin +#define IOC_PORT_MCU_SSI0_CLK 0x0000000C // MCU SSI0 Clock Pin +#define IOC_PORT_MCU_I2C_MSSDA 0x0000000D // MCU I2C Data Pin +#define IOC_PORT_MCU_I2C_MSSCL 0x0000000E // MCU I2C Clock Pin +#define IOC_PORT_MCU_UART0_RX 0x0000000F // MCU UART0 Receive Pin +#define IOC_PORT_MCU_UART0_TX 0x00000010 // MCU UART0 Transmit Pin +#define IOC_PORT_MCU_UART0_CTS 0x00000011 // MCU UART0 Clear To Send Pin +#define IOC_PORT_MCU_UART0_RTS 0x00000012 // MCU UART0 Request To Send Pin +#define IOC_PORT_MCU_PORT_EVENT0 0x00000017 // MCU PORT EVENT 0 +#define IOC_PORT_MCU_PORT_EVENT1 0x00000018 // MCU PORT EVENT 1 +#define IOC_PORT_MCU_PORT_EVENT2 0x00000019 // MCU PORT EVENT 2 +#define IOC_PORT_MCU_PORT_EVENT3 0x0000001A // MCU PORT EVENT 3 +#define IOC_PORT_MCU_PORT_EVENT4 0x0000001B // MCU PORT EVENT 4 +#define IOC_PORT_MCU_PORT_EVENT5 0x0000001C // MCU PORT EVENT 5 +#define IOC_PORT_MCU_PORT_EVENT6 0x0000001D // MCU PORT EVENT 6 +#define IOC_PORT_MCU_PORT_EVENT7 0x0000001E // MCU PORT EVENT 7 +#define IOC_PORT_MCU_SWV 0x00000020 // Serial Wire Viewer +#define IOC_PORT_MCU_SSI1_RX 0x00000021 // MCU SSI1 Receive Pin +#define IOC_PORT_MCU_SSI1_TX 0x00000022 // MCU SSI1 Transmit Pin +#define IOC_PORT_MCU_SSI1_FSS 0x00000023 // MCU SSI1 FSS Pin +#define IOC_PORT_MCU_SSI1_CLK 0x00000024 // MCU SSI1 Clock Pin +#define IOC_PORT_MCU_I2S_AD0 0x00000025 // MCU I2S Data Pin 0 +#define IOC_PORT_MCU_I2S_AD1 0x00000026 // MCU I2S Data Pin 1 +#define IOC_PORT_MCU_I2S_WCLK 0x00000027 // MCU I2S Frame/Word Clock +#define IOC_PORT_MCU_I2S_BCLK 0x00000028 // MCU I2S Bit Clock +#define IOC_PORT_MCU_I2S_MCLK 0x00000029 // MCU I2S Master clock 2 +#define IOC_PORT_RFC_TRC 0x0000002E // RF Core Tracer +#define IOC_PORT_RFC_GPO0 0x0000002F // RC Core Data Out Pin 0 +#define IOC_PORT_RFC_GPO1 0x00000030 // RC Core Data Out Pin 1 +#define IOC_PORT_RFC_GPO2 0x00000031 // RC Core Data Out Pin 2 +#define IOC_PORT_RFC_GPO3 0x00000032 // RC Core Data Out Pin 3 +#define IOC_PORT_RFC_GPI0 0x00000033 // RC Core Data In Pin 0 +#define IOC_PORT_RFC_GPI1 0x00000034 // RC Core Data In Pin 1 +#define IOC_PORT_RFC_SMI_DL_OUT 0x00000035 // RF Core SMI Data Link Out +#define IOC_PORT_RFC_SMI_DL_IN 0x00000036 // RF Core SMI Data Link in +#define IOC_PORT_RFC_SMI_CL_OUT 0x00000037 // RF Core SMI Command Link Out +#define IOC_PORT_RFC_SMI_CL_IN 0x00000038 // RF Core SMI Command Link In //***************************************************************************** // // Defines for enabling/disabling an IO // //***************************************************************************** -#define IOC_SLEW_ENABLE 0x00001000 -#define IOC_SLEW_DISABLE 0x00000000 -#define IOC_INPUT_ENABLE 0x20000000 -#define IOC_INPUT_DISABLE 0x00000000 -#define IOC_HYST_ENABLE 0x40000000 -#define IOC_HYST_DISABLE 0x00000000 +#define IOC_SLEW_ENABLE 0x00001000 +#define IOC_SLEW_DISABLE 0x00000000 +#define IOC_INPUT_ENABLE 0x20000000 +#define IOC_INPUT_DISABLE 0x00000000 +#define IOC_HYST_ENABLE 0x40000000 +#define IOC_HYST_DISABLE 0x00000000 //***************************************************************************** // // Defines that can be used to set the shutdown mode of an IO // //***************************************************************************** -#define IOC_NO_WAKE_UP 0x00000000 -#define IOC_WAKE_ON_LOW 0x10000000 -#define IOC_WAKE_ON_HIGH 0x18000000 +#define IOC_NO_WAKE_UP 0x00000000 +#define IOC_WAKE_ON_LOW 0x10000000 +#define IOC_WAKE_ON_HIGH 0x18000000 //***************************************************************************** // // Defines that can be used to set the IO Mode of an IO // //***************************************************************************** -#define IOC_IOMODE_NORMAL 0x00000000 // Normal Input/Output -#define IOC_IOMODE_INV 0x01000000 // Inverted Input/Output +#define IOC_IOMODE_NORMAL 0x00000000 // Normal Input/Output +#define IOC_IOMODE_INV 0x01000000 // Inverted Input/Output #define IOC_IOMODE_OPEN_DRAIN_NORMAL \ - 0x04000000 // Open Drain, Normal Input/Output + 0x04000000 // Open Drain, Normal Input/Output #define IOC_IOMODE_OPEN_DRAIN_INV \ - 0x05000000 // Open Drain, Inverted + 0x05000000 // Open Drain, Inverted // Input/Output #define IOC_IOMODE_OPEN_SRC_NORMAL \ - 0x06000000 // Open Source, Normal Input/Output + 0x06000000 // Open Source, Normal Input/Output #define IOC_IOMODE_OPEN_SRC_INV \ - 0x07000000 // Open Source, Inverted + 0x07000000 // Open Source, Inverted // Input/Output //***************************************************************************** @@ -252,41 +251,41 @@ extern "C" // Defines that can be used to set the edge detection on an IO // //***************************************************************************** -#define IOC_NO_EDGE 0x00000000 // No edge detection -#define IOC_FALLING_EDGE 0x00010000 // Edge detection on falling edge -#define IOC_RISING_EDGE 0x00020000 // Edge detection on rising edge -#define IOC_BOTH_EDGES 0x00030000 // Edge detection on both edges -#define IOC_INT_ENABLE 0x00040000 // Enable interrupt on edge detect -#define IOC_INT_DISABLE 0x00000000 // Disable interrupt on edge detect -#define IOC_INT_M 0x00070000 // Int config mask +#define IOC_NO_EDGE 0x00000000 // No edge detection +#define IOC_FALLING_EDGE 0x00010000 // Edge detection on falling edge +#define IOC_RISING_EDGE 0x00020000 // Edge detection on rising edge +#define IOC_BOTH_EDGES 0x00030000 // Edge detection on both edges +#define IOC_INT_ENABLE 0x00040000 // Enable interrupt on edge detect +#define IOC_INT_DISABLE 0x00000000 // Disable interrupt on edge detect +#define IOC_INT_M 0x00070000 // Int config mask //***************************************************************************** // // Defines that be used to set pull on an IO // //***************************************************************************** -#define IOC_NO_IOPULL 0x00006000 // No IO pull -#define IOC_IOPULL_UP 0x00004000 // Pull up -#define IOC_IOPULL_DOWN 0x00002000 // Pull down -#define IOC_IOPULL_M 0x00006000 // Pull config mask -#define IOC_IOPULL_M 0x00006000 +#define IOC_NO_IOPULL 0x00006000 // No IO pull +#define IOC_IOPULL_UP 0x00004000 // Pull up +#define IOC_IOPULL_DOWN 0x00002000 // Pull down +#define IOC_IOPULL_M 0x00006000 // Pull config mask +#define IOC_IOPULL_M 0x00006000 //***************************************************************************** // // Defines that can be used to select the drive strength of an IO // //***************************************************************************** -#define IOC_CURRENT_2MA 0x00000000 // 2mA drive strength -#define IOC_CURRENT_4MA 0x00000400 // 4mA drive strength -#define IOC_CURRENT_8MA 0x00000800 // 4 or 8mA drive strength +#define IOC_CURRENT_2MA 0x00000000 // 2mA drive strength +#define IOC_CURRENT_4MA 0x00000400 // 4mA drive strength +#define IOC_CURRENT_8MA 0x00000800 // 4 or 8mA drive strength -#define IOC_STRENGTH_AUTO 0x00000000 // Automatic Drive Strength +#define IOC_STRENGTH_AUTO 0x00000000 // Automatic Drive Strength // (2/4/8 mA @ VVDS) -#define IOC_STRENGTH_MAX 0x00000300 // Maximum Drive Strength +#define IOC_STRENGTH_MAX 0x00000300 // Maximum Drive Strength // (2/4/8 mA @ 1.8V) -#define IOC_STRENGTH_MED 0x00000200 // Medium Drive Strength +#define IOC_STRENGTH_MED 0x00000200 // Medium Drive Strength // (2/4/8 mA @ 2.5V) -#define IOC_STRENGTH_MIN 0x00000100 // Minimum Drive Strength +#define IOC_STRENGTH_MIN 0x00000100 // Minimum Drive Strength // (2/4/8 mA @ 3.3V) //***************************************************************************** @@ -294,16 +293,16 @@ extern "C" // Defines for standard IO setup // //***************************************************************************** -#define IOC_STD_INPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ - IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ - IOC_HYST_DISABLE | IOC_NO_EDGE | \ - IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ - IOC_NO_WAKE_UP | IOC_INPUT_ENABLE ) -#define IOC_STD_OUTPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ - IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ - IOC_HYST_DISABLE | IOC_NO_EDGE | \ - IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ - IOC_NO_WAKE_UP | IOC_INPUT_DISABLE ) +#define IOC_STD_INPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ + IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ + IOC_HYST_DISABLE | IOC_NO_EDGE | \ + IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ + IOC_NO_WAKE_UP | IOC_INPUT_ENABLE) +#define IOC_STD_OUTPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ + IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ + IOC_HYST_DISABLE | IOC_NO_EDGE | \ + IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ + IOC_NO_WAKE_UP | IOC_INPUT_DISABLE) //***************************************************************************** // @@ -466,7 +465,6 @@ extern uint32_t IOCPortConfigureGet(uint32_t ui32IOId); //***************************************************************************** extern void IOCIOShutdownSet(uint32_t ui32IOId, uint32_t ui32IOShutdown); - //***************************************************************************** // //! \brief Set the IO Mode of an IO Port. @@ -837,7 +835,6 @@ IOCIntStatus(uint32_t ui32IOId) return (GPIO_getEventDio(ui32IOId)); } - //***************************************************************************** // //! \brief Setup an IO for standard GPIO input. @@ -1021,7 +1018,6 @@ extern void IOCPinTypeSsiSlave(uint32_t ui32Base, uint32_t ui32Rx, extern void IOCPinTypeI2c(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk); - //***************************************************************************** // //! \brief Configure an IO for AUX control. @@ -1053,84 +1049,84 @@ extern void IOCPinTypeAux(uint32_t ui32IOId); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_IOCPortConfigureSet -#undef IOCPortConfigureSet -#define IOCPortConfigureSet ROM_IOCPortConfigureSet +#undef IOCPortConfigureSet +#define IOCPortConfigureSet ROM_IOCPortConfigureSet #endif #ifdef ROM_IOCPortConfigureGet -#undef IOCPortConfigureGet -#define IOCPortConfigureGet ROM_IOCPortConfigureGet +#undef IOCPortConfigureGet +#define IOCPortConfigureGet ROM_IOCPortConfigureGet #endif #ifdef ROM_IOCIOShutdownSet -#undef IOCIOShutdownSet -#define IOCIOShutdownSet ROM_IOCIOShutdownSet +#undef IOCIOShutdownSet +#define IOCIOShutdownSet ROM_IOCIOShutdownSet #endif #ifdef ROM_IOCIOModeSet -#undef IOCIOModeSet -#define IOCIOModeSet ROM_IOCIOModeSet +#undef IOCIOModeSet +#define IOCIOModeSet ROM_IOCIOModeSet #endif #ifdef ROM_IOCIOIntSet -#undef IOCIOIntSet -#define IOCIOIntSet ROM_IOCIOIntSet +#undef IOCIOIntSet +#define IOCIOIntSet ROM_IOCIOIntSet #endif #ifdef ROM_IOCIOPortPullSet -#undef IOCIOPortPullSet -#define IOCIOPortPullSet ROM_IOCIOPortPullSet +#undef IOCIOPortPullSet +#define IOCIOPortPullSet ROM_IOCIOPortPullSet #endif #ifdef ROM_IOCIOHystSet -#undef IOCIOHystSet -#define IOCIOHystSet ROM_IOCIOHystSet +#undef IOCIOHystSet +#define IOCIOHystSet ROM_IOCIOHystSet #endif #ifdef ROM_IOCIOInputSet -#undef IOCIOInputSet -#define IOCIOInputSet ROM_IOCIOInputSet +#undef IOCIOInputSet +#define IOCIOInputSet ROM_IOCIOInputSet #endif #ifdef ROM_IOCIOSlewCtrlSet -#undef IOCIOSlewCtrlSet -#define IOCIOSlewCtrlSet ROM_IOCIOSlewCtrlSet +#undef IOCIOSlewCtrlSet +#define IOCIOSlewCtrlSet ROM_IOCIOSlewCtrlSet #endif #ifdef ROM_IOCIODrvStrengthSet -#undef IOCIODrvStrengthSet -#define IOCIODrvStrengthSet ROM_IOCIODrvStrengthSet +#undef IOCIODrvStrengthSet +#define IOCIODrvStrengthSet ROM_IOCIODrvStrengthSet #endif #ifdef ROM_IOCIOPortIdSet -#undef IOCIOPortIdSet -#define IOCIOPortIdSet ROM_IOCIOPortIdSet +#undef IOCIOPortIdSet +#define IOCIOPortIdSet ROM_IOCIOPortIdSet #endif #ifdef ROM_IOCIntEnable -#undef IOCIntEnable -#define IOCIntEnable ROM_IOCIntEnable +#undef IOCIntEnable +#define IOCIntEnable ROM_IOCIntEnable #endif #ifdef ROM_IOCIntDisable -#undef IOCIntDisable -#define IOCIntDisable ROM_IOCIntDisable +#undef IOCIntDisable +#define IOCIntDisable ROM_IOCIntDisable #endif #ifdef ROM_IOCPinTypeGpioInput -#undef IOCPinTypeGpioInput -#define IOCPinTypeGpioInput ROM_IOCPinTypeGpioInput +#undef IOCPinTypeGpioInput +#define IOCPinTypeGpioInput ROM_IOCPinTypeGpioInput #endif #ifdef ROM_IOCPinTypeGpioOutput -#undef IOCPinTypeGpioOutput -#define IOCPinTypeGpioOutput ROM_IOCPinTypeGpioOutput +#undef IOCPinTypeGpioOutput +#define IOCPinTypeGpioOutput ROM_IOCPinTypeGpioOutput #endif #ifdef ROM_IOCPinTypeUart -#undef IOCPinTypeUart -#define IOCPinTypeUart ROM_IOCPinTypeUart +#undef IOCPinTypeUart +#define IOCPinTypeUart ROM_IOCPinTypeUart #endif #ifdef ROM_IOCPinTypeSsiMaster -#undef IOCPinTypeSsiMaster -#define IOCPinTypeSsiMaster ROM_IOCPinTypeSsiMaster +#undef IOCPinTypeSsiMaster +#define IOCPinTypeSsiMaster ROM_IOCPinTypeSsiMaster #endif #ifdef ROM_IOCPinTypeSsiSlave -#undef IOCPinTypeSsiSlave -#define IOCPinTypeSsiSlave ROM_IOCPinTypeSsiSlave +#undef IOCPinTypeSsiSlave +#define IOCPinTypeSsiSlave ROM_IOCPinTypeSsiSlave #endif #ifdef ROM_IOCPinTypeI2c -#undef IOCPinTypeI2c -#define IOCPinTypeI2c ROM_IOCPinTypeI2c +#undef IOCPinTypeI2c +#define IOCPinTypeI2c ROM_IOCPinTypeI2c #endif #ifdef ROM_IOCPinTypeAux -#undef IOCPinTypeAux -#define IOCPinTypeAux ROM_IOCPinTypeAux +#undef IOCPinTypeAux +#define IOCPinTypeAux ROM_IOCPinTypeAux #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ioc_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ioc_doc.h index cd35eff..1e1a32e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ioc_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ioc_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: ioc_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: ioc_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup ioc_api //! @{ //! \section sec_ioc Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/osc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/osc.h index 3bfb71c..efc0efc 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/osc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/osc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: osc.h -* Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019) -* Revision: 54539 -* -* Description: Defines and prototypes for the system oscillator control. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: osc.h + * Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019) + * Revision: 54539 + * + * Description: Defines and prototypes for the system oscillator control. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,20 +55,19 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include #include "../inc/hw_aon_wuc.h" -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" #include "../inc/hw_ddi.h" #include "../inc/hw_ddi_0_osc.h" -#include "rom.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "ddi.h" #include "debug.h" +#include "rom.h" +#include +#include //***************************************************************************** // @@ -84,16 +83,16 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define OSCClockSourceSet NOROM_OSCClockSourceSet -#define OSCClockSourceGet NOROM_OSCClockSourceGet -#define OSCHF_GetStartupTime NOROM_OSCHF_GetStartupTime -#define OSCHF_TurnOnXosc NOROM_OSCHF_TurnOnXosc -#define OSCHF_AttemptToSwitchToXosc NOROM_OSCHF_AttemptToSwitchToXosc -#define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc -#define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude +#define OSCClockSourceSet NOROM_OSCClockSourceSet +#define OSCClockSourceGet NOROM_OSCClockSourceGet +#define OSCHF_GetStartupTime NOROM_OSCHF_GetStartupTime +#define OSCHF_TurnOnXosc NOROM_OSCHF_TurnOnXosc +#define OSCHF_AttemptToSwitchToXosc NOROM_OSCHF_AttemptToSwitchToXosc +#define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc +#define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude #define OSCHF_DebugGetExpectedAverageCrystalAmplitude NOROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude #define OSC_HPOSCRelativeFrequencyOffsetGet NOROM_OSC_HPOSCRelativeFrequencyOffsetGet -#define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray +#define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert NOROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert #endif @@ -102,33 +101,33 @@ extern "C" // Defines for the High Frequency XTAL Power mode // //***************************************************************************** -#define LOW_POWER_XOSC 1 -#define HIGH_POWER_XOSC 0 +#define LOW_POWER_XOSC 1 +#define HIGH_POWER_XOSC 0 //***************************************************************************** // // Defines for the High Frequency XTAL Power mode // //***************************************************************************** -#define OSC_SRC_CLK_HF 0x00000001 -#define OSC_SRC_CLK_MF 0x00000002 -#define OSC_SRC_CLK_LF 0x00000004 +#define OSC_SRC_CLK_HF 0x00000001 +#define OSC_SRC_CLK_MF 0x00000002 +#define OSC_SRC_CLK_LF 0x00000004 -#define OSC_RCOSC_HF 0x00000000 -#define OSC_XOSC_HF 0x00000001 -#define OSC_RCOSC_LF 0x00000002 -#define OSC_XOSC_LF 0x00000003 +#define OSC_RCOSC_HF 0x00000000 +#define OSC_XOSC_HF 0x00000001 +#define OSC_RCOSC_LF 0x00000002 +#define OSC_XOSC_LF 0x00000003 -#define SCLK_HF_RCOSC_HF 0 -#define SCLK_HF_XOSC_HF 1 +#define SCLK_HF_RCOSC_HF 0 +#define SCLK_HF_XOSC_HF 1 -#define SCLK_MF_RCOSC_HF 0 -#define SCLK_MF_XOSC_HF 1 +#define SCLK_MF_RCOSC_HF 0 +#define SCLK_MF_XOSC_HF 1 -#define SCLK_LF_FROM_RCOSC_HF 0 -#define SCLK_LF_FROM_XOSC_HF 1 -#define SCLK_LF_FROM_RCOSC_LF 2 -#define SCLK_LF_FROM_XOSC_LF 3 +#define SCLK_LF_FROM_RCOSC_HF 0 +#define SCLK_LF_FROM_XOSC_HF 1 +#define SCLK_LF_FROM_RCOSC_LF 2 +#define SCLK_LF_FROM_XOSC_LF 3 //***************************************************************************** // @@ -175,11 +174,11 @@ OSCXHfPowerModeSet(uint32_t ui32Mode) // //***************************************************************************** __STATIC_INLINE void -OSCClockLossEventEnable( void ) +OSCClockLossEventEnable(void) { - DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, - DDI_0_OSC_CTL0_CLK_LOSS_EN_M, - DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 1 ); + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_CLK_LOSS_EN_M, + DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 1); } //***************************************************************************** @@ -198,11 +197,11 @@ OSCClockLossEventEnable( void ) // //***************************************************************************** __STATIC_INLINE void -OSCClockLossEventDisable( void ) +OSCClockLossEventDisable(void) { - DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, - DDI_0_OSC_CTL0_CLK_LOSS_EN_M, - DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 0 ); + DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, + DDI_0_OSC_CTL0_CLK_LOSS_EN_M, + DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 0); } //***************************************************************************** @@ -289,8 +288,9 @@ OSCHfSourceReady(void) // Return the readiness of the HF clock source return (DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M, - DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S)) ? - true : false; + DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S)) + ? true + : false; } //***************************************************************************** @@ -331,7 +331,7 @@ OSCHfSourceSwitch(void) //! \return Time margin to use in microseconds. // //***************************************************************************** -extern uint32_t OSCHF_GetStartupTime( uint32_t timeUntilWakeupInMs ); +extern uint32_t OSCHF_GetStartupTime(uint32_t timeUntilWakeupInMs); //***************************************************************************** // @@ -343,7 +343,7 @@ extern uint32_t OSCHF_GetStartupTime( uint32_t timeUntilWakeupInMs ); //! \return None // //***************************************************************************** -extern void OSCHF_TurnOnXosc( void ); +extern void OSCHF_TurnOnXosc(void); //***************************************************************************** // @@ -358,7 +358,7 @@ extern void OSCHF_TurnOnXosc( void ); //! - \c false : Switching has not occurred. // //***************************************************************************** -extern bool OSCHF_AttemptToSwitchToXosc( void ); +extern bool OSCHF_AttemptToSwitchToXosc(void); //***************************************************************************** // @@ -370,7 +370,7 @@ extern bool OSCHF_AttemptToSwitchToXosc( void ); //! \return None // //***************************************************************************** -extern void OSCHF_SwitchToRcOscTurnOffXosc( void ); +extern void OSCHF_SwitchToRcOscTurnOffXosc(void); //***************************************************************************** // @@ -390,7 +390,7 @@ extern void OSCHF_SwitchToRcOscTurnOffXosc( void ); //! \sa OSCHF_DebugGetExpectedAverageCrystalAmplitude() // //***************************************************************************** -extern uint32_t OSCHF_DebugGetCrystalAmplitude( void ); +extern uint32_t OSCHF_DebugGetCrystalAmplitude(void); //***************************************************************************** // @@ -407,7 +407,7 @@ extern uint32_t OSCHF_DebugGetCrystalAmplitude( void ); //! \sa OSCHF_DebugGetCrystalAmplitude() // //***************************************************************************** -extern uint32_t OSCHF_DebugGetExpectedAverageCrystalAmplitude( void ); +extern uint32_t OSCHF_DebugGetExpectedAverageCrystalAmplitude(void); //***************************************************************************** // @@ -438,7 +438,7 @@ extern uint32_t OSCHF_DebugGetExpectedAverageCrystalAmplitude( void ); //! \sa OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert(), AONBatMonTemperatureGetDegC() // //***************************************************************************** -extern int32_t OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC ); +extern int32_t OSC_HPOSCRelativeFrequencyOffsetGet(int32_t tempDegC); //***************************************************************************** // @@ -456,7 +456,7 @@ extern int32_t OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC ); //! \return None // //***************************************************************************** -extern void OSC_AdjustXoscHfCapArray( int32_t capArrDelta ); +extern void OSC_AdjustXoscHfCapArray(int32_t capArrDelta); //***************************************************************************** // @@ -486,7 +486,7 @@ extern void OSC_AdjustXoscHfCapArray( int32_t capArrDelta ); //! \sa OSC_HPOSCRelativeFrequencyOffsetGet() // //***************************************************************************** -extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffset ); +extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert(int32_t HPOSC_RelFreqOffset); //***************************************************************************** // @@ -497,47 +497,47 @@ extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HP #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_OSCClockSourceSet -#undef OSCClockSourceSet -#define OSCClockSourceSet ROM_OSCClockSourceSet +#undef OSCClockSourceSet +#define OSCClockSourceSet ROM_OSCClockSourceSet #endif #ifdef ROM_OSCClockSourceGet -#undef OSCClockSourceGet -#define OSCClockSourceGet ROM_OSCClockSourceGet +#undef OSCClockSourceGet +#define OSCClockSourceGet ROM_OSCClockSourceGet #endif #ifdef ROM_OSCHF_GetStartupTime -#undef OSCHF_GetStartupTime -#define OSCHF_GetStartupTime ROM_OSCHF_GetStartupTime +#undef OSCHF_GetStartupTime +#define OSCHF_GetStartupTime ROM_OSCHF_GetStartupTime #endif #ifdef ROM_OSCHF_TurnOnXosc -#undef OSCHF_TurnOnXosc -#define OSCHF_TurnOnXosc ROM_OSCHF_TurnOnXosc +#undef OSCHF_TurnOnXosc +#define OSCHF_TurnOnXosc ROM_OSCHF_TurnOnXosc #endif #ifdef ROM_OSCHF_AttemptToSwitchToXosc -#undef OSCHF_AttemptToSwitchToXosc -#define OSCHF_AttemptToSwitchToXosc ROM_OSCHF_AttemptToSwitchToXosc +#undef OSCHF_AttemptToSwitchToXosc +#define OSCHF_AttemptToSwitchToXosc ROM_OSCHF_AttemptToSwitchToXosc #endif #ifdef ROM_OSCHF_SwitchToRcOscTurnOffXosc -#undef OSCHF_SwitchToRcOscTurnOffXosc -#define OSCHF_SwitchToRcOscTurnOffXosc ROM_OSCHF_SwitchToRcOscTurnOffXosc +#undef OSCHF_SwitchToRcOscTurnOffXosc +#define OSCHF_SwitchToRcOscTurnOffXosc ROM_OSCHF_SwitchToRcOscTurnOffXosc #endif #ifdef ROM_OSCHF_DebugGetCrystalAmplitude -#undef OSCHF_DebugGetCrystalAmplitude -#define OSCHF_DebugGetCrystalAmplitude ROM_OSCHF_DebugGetCrystalAmplitude +#undef OSCHF_DebugGetCrystalAmplitude +#define OSCHF_DebugGetCrystalAmplitude ROM_OSCHF_DebugGetCrystalAmplitude #endif #ifdef ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude -#undef OSCHF_DebugGetExpectedAverageCrystalAmplitude +#undef OSCHF_DebugGetExpectedAverageCrystalAmplitude #define OSCHF_DebugGetExpectedAverageCrystalAmplitude ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude #endif #ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetGet -#undef OSC_HPOSCRelativeFrequencyOffsetGet +#undef OSC_HPOSCRelativeFrequencyOffsetGet #define OSC_HPOSCRelativeFrequencyOffsetGet ROM_OSC_HPOSCRelativeFrequencyOffsetGet #endif #ifdef ROM_OSC_AdjustXoscHfCapArray -#undef OSC_AdjustXoscHfCapArray -#define OSC_AdjustXoscHfCapArray ROM_OSC_AdjustXoscHfCapArray +#undef OSC_AdjustXoscHfCapArray +#define OSC_AdjustXoscHfCapArray ROM_OSC_AdjustXoscHfCapArray #endif #ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert -#undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert +#undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/prcm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/prcm.h index becf1cd..3df189d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/prcm.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/prcm.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: prcm.h -* Revised: 2018-10-23 10:19:14 +0200 (Tue, 23 Oct 2018) -* Revision: 52979 -* -* Description: Defines and prototypes for the PRCM -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: prcm.h + * Revised: 2018-10-23 10:19:14 +0200 (Tue, 23 Oct 2018) + * Revision: 52979 + * + * Description: Defines and prototypes for the PRCM + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,22 +55,20 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_nvic.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_prcm.h" -#include "../inc/hw_nvic.h" -#include "../inc/hw_aon_rtc.h" -#include "interrupt.h" -#include "debug.h" -#include "cpu.h" - //***************************************************************************** // @@ -86,22 +84,22 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet -#define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet -#define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet +#define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet +#define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet +#define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet #define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride -#define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource -#define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource -#define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn -#define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff -#define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable -#define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable -#define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable -#define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable -#define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable -#define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable -#define PRCMPowerDomainStatus NOROM_PRCMPowerDomainStatus -#define PRCMDeepSleep NOROM_PRCMDeepSleep +#define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource +#define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource +#define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn +#define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff +#define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable +#define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable +#define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable +#define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable +#define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable +#define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable +#define PRCMPowerDomainStatus NOROM_PRCMPowerDomainStatus +#define PRCMDeepSleep NOROM_PRCMDeepSleep #endif //***************************************************************************** @@ -109,24 +107,24 @@ extern "C" // Defines for the different System CPU power modes. // //***************************************************************************** -#define PRCM_RUN_MODE 0x00000001 -#define PRCM_SLEEP_MODE 0x00000002 -#define PRCM_DEEP_SLEEP_MODE 0x00000004 +#define PRCM_RUN_MODE 0x00000001 +#define PRCM_SLEEP_MODE 0x00000002 +#define PRCM_DEEP_SLEEP_MODE 0x00000004 //***************************************************************************** // // Defines used for setting the clock division factors // //***************************************************************************** -#define PRCM_CLOCK_DIV_1 PRCM_GPTCLKDIV_RATIO_DIV1 -#define PRCM_CLOCK_DIV_2 PRCM_GPTCLKDIV_RATIO_DIV2 -#define PRCM_CLOCK_DIV_4 PRCM_GPTCLKDIV_RATIO_DIV4 -#define PRCM_CLOCK_DIV_8 PRCM_GPTCLKDIV_RATIO_DIV8 -#define PRCM_CLOCK_DIV_16 PRCM_GPTCLKDIV_RATIO_DIV16 -#define PRCM_CLOCK_DIV_32 PRCM_GPTCLKDIV_RATIO_DIV32 -#define PRCM_CLOCK_DIV_64 PRCM_GPTCLKDIV_RATIO_DIV64 -#define PRCM_CLOCK_DIV_128 PRCM_GPTCLKDIV_RATIO_DIV128 -#define PRCM_CLOCK_DIV_256 PRCM_GPTCLKDIV_RATIO_DIV256 +#define PRCM_CLOCK_DIV_1 PRCM_GPTCLKDIV_RATIO_DIV1 +#define PRCM_CLOCK_DIV_2 PRCM_GPTCLKDIV_RATIO_DIV2 +#define PRCM_CLOCK_DIV_4 PRCM_GPTCLKDIV_RATIO_DIV4 +#define PRCM_CLOCK_DIV_8 PRCM_GPTCLKDIV_RATIO_DIV8 +#define PRCM_CLOCK_DIV_16 PRCM_GPTCLKDIV_RATIO_DIV16 +#define PRCM_CLOCK_DIV_32 PRCM_GPTCLKDIV_RATIO_DIV32 +#define PRCM_CLOCK_DIV_64 PRCM_GPTCLKDIV_RATIO_DIV64 +#define PRCM_CLOCK_DIV_128 PRCM_GPTCLKDIV_RATIO_DIV128 +#define PRCM_CLOCK_DIV_256 PRCM_GPTCLKDIV_RATIO_DIV256 //***************************************************************************** // @@ -134,28 +132,28 @@ extern "C" // domain // //***************************************************************************** -#define PRCM_DOMAIN_RFCORE 0x00000001 // RF Core domain ID for +#define PRCM_DOMAIN_RFCORE 0x00000001 // RF Core domain ID for // clock/power control. -#define PRCM_DOMAIN_SERIAL 0x00000002 // Serial domain ID for +#define PRCM_DOMAIN_SERIAL 0x00000002 // Serial domain ID for // clock/power control. -#define PRCM_DOMAIN_PERIPH 0x00000004 // Peripheral domain ID for +#define PRCM_DOMAIN_PERIPH 0x00000004 // Peripheral domain ID for // clock/power control. -#define PRCM_DOMAIN_SYSBUS 0x00000008 // Bus domain ID for clock/power +#define PRCM_DOMAIN_SYSBUS 0x00000008 // Bus domain ID for clock/power // control. -#define PRCM_DOMAIN_VIMS 0x00000010 // VIMS domain ID for clock/power +#define PRCM_DOMAIN_VIMS 0x00000010 // VIMS domain ID for clock/power // control. -#define PRCM_DOMAIN_CPU 0x00000020 // CPU domain ID for clock/power +#define PRCM_DOMAIN_CPU 0x00000020 // CPU domain ID for clock/power // control. -#define PRCM_DOMAIN_TIMER 0x00000040 // GPT domain ID for clock +#define PRCM_DOMAIN_TIMER 0x00000040 // GPT domain ID for clock // control. -#define PRCM_DOMAIN_CLKCTRL 0x00000080 // Clock Control domain ID for +#define PRCM_DOMAIN_CLKCTRL 0x00000080 // Clock Control domain ID for // clock/power control. -#define PRCM_DOMAIN_MCU 0x00000100 // Reset control for entire MCU +#define PRCM_DOMAIN_MCU 0x00000100 // Reset control for entire MCU // domain. -#define PRCM_DOMAIN_POWER_OFF 0x00000002 // The domain is powered off -#define PRCM_DOMAIN_POWER_ON 0x00000001 // The domain is powered on -#define PRCM_DOMAIN_POWER_DOWN_READY \ - 0x00000000 // The domain is ready to be +#define PRCM_DOMAIN_POWER_OFF 0x00000002 // The domain is powered off +#define PRCM_DOMAIN_POWER_ON 0x00000001 // The domain is powered on +#define PRCM_DOMAIN_POWER_DOWN_READY \ + 0x00000000 // The domain is ready to be // powered down. //***************************************************************************** @@ -163,21 +161,21 @@ extern "C" // Defines for setting up the audio interface in the I2S module. // //***************************************************************************** -#define PRCM_WCLK_NEG_EDGE 0x00000008 -#define PRCM_WCLK_POS_EDGE 0x00000000 -#define PRCM_WCLK_SINGLE_PHASE 0x00000000 -#define PRCM_WCLK_DUAL_PHASE 0x00000002 -#define PRCM_WCLK_USER_DEF 0x00000004 -#define PRCM_I2S_WCLK_NEG_EDGE 0 -#define PRCM_I2S_WCLK_POS_EDGE 1 -#define PRCM_I2S_WCLK_SINGLE_PHASE 0 -#define PRCM_I2S_WCLK_DUAL_PHASE 1 -#define PRCM_I2S_WCLK_USER_DEF 2 +#define PRCM_WCLK_NEG_EDGE 0x00000008 +#define PRCM_WCLK_POS_EDGE 0x00000000 +#define PRCM_WCLK_SINGLE_PHASE 0x00000000 +#define PRCM_WCLK_DUAL_PHASE 0x00000002 +#define PRCM_WCLK_USER_DEF 0x00000004 +#define PRCM_I2S_WCLK_NEG_EDGE 0 +#define PRCM_I2S_WCLK_POS_EDGE 1 +#define PRCM_I2S_WCLK_SINGLE_PHASE 0 +#define PRCM_I2S_WCLK_DUAL_PHASE 1 +#define PRCM_I2S_WCLK_USER_DEF 2 -#define I2S_SAMPLE_RATE_16K 0x00000001 -#define I2S_SAMPLE_RATE_24K 0x00000002 -#define I2S_SAMPLE_RATE_32K 0x00000004 -#define I2S_SAMPLE_RATE_48K 0x00000008 +#define I2S_SAMPLE_RATE_16K 0x00000001 +#define I2S_SAMPLE_RATE_24K 0x00000002 +#define I2S_SAMPLE_RATE_32K 0x00000004 +#define I2S_SAMPLE_RATE_48K 0x00000008 //***************************************************************************** // @@ -187,19 +185,19 @@ extern "C" // bits[4:0] Defines the bit position within the register pointet on in [11:8] // //***************************************************************************** -#define PRCM_PERIPH_TIMER0 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S )) // Peripheral ID for GPT module 0 -#define PRCM_PERIPH_TIMER1 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 1 )) // Peripheral ID for GPT module 1 -#define PRCM_PERIPH_TIMER2 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 2 )) // Peripheral ID for GPT module 2 -#define PRCM_PERIPH_TIMER3 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 3 )) // Peripheral ID for GPT module 3 -#define PRCM_PERIPH_SSI0 ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S )) // Peripheral ID for SSI module 0 -#define PRCM_PERIPH_SSI1 ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S + 1 )) // Peripheral ID for SSI module 1 -#define PRCM_PERIPH_UART0 ( 0x00000200 | ( PRCM_UARTCLKGR_CLK_EN_S )) // Peripheral ID for UART module 0 -#define PRCM_PERIPH_I2C0 ( 0x00000300 | ( PRCM_I2CCLKGR_CLK_EN_S )) // Peripheral ID for I2C module 0 -#define PRCM_PERIPH_CRYPTO ( 0x00000400 | ( PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S )) // Peripheral ID for CRYPTO module -#define PRCM_PERIPH_TRNG ( 0x00000400 | ( PRCM_SECDMACLKGR_TRNG_CLK_EN_S )) // Peripheral ID for TRNG module -#define PRCM_PERIPH_UDMA ( 0x00000400 | ( PRCM_SECDMACLKGR_DMA_CLK_EN_S )) // Peripheral ID for UDMA module -#define PRCM_PERIPH_GPIO ( 0x00000500 | ( PRCM_GPIOCLKGR_CLK_EN_S )) // Peripheral ID for GPIO module -#define PRCM_PERIPH_I2S ( 0x00000600 | ( PRCM_I2SCLKGR_CLK_EN_S )) // Peripheral ID for I2S module +#define PRCM_PERIPH_TIMER0 (0x00000000 | (PRCM_GPTCLKGR_CLK_EN_S)) // Peripheral ID for GPT module 0 +#define PRCM_PERIPH_TIMER1 (0x00000000 | (PRCM_GPTCLKGR_CLK_EN_S + 1)) // Peripheral ID for GPT module 1 +#define PRCM_PERIPH_TIMER2 (0x00000000 | (PRCM_GPTCLKGR_CLK_EN_S + 2)) // Peripheral ID for GPT module 2 +#define PRCM_PERIPH_TIMER3 (0x00000000 | (PRCM_GPTCLKGR_CLK_EN_S + 3)) // Peripheral ID for GPT module 3 +#define PRCM_PERIPH_SSI0 (0x00000100 | (PRCM_SSICLKGR_CLK_EN_S)) // Peripheral ID for SSI module 0 +#define PRCM_PERIPH_SSI1 (0x00000100 | (PRCM_SSICLKGR_CLK_EN_S + 1)) // Peripheral ID for SSI module 1 +#define PRCM_PERIPH_UART0 (0x00000200 | (PRCM_UARTCLKGR_CLK_EN_S)) // Peripheral ID for UART module 0 +#define PRCM_PERIPH_I2C0 (0x00000300 | (PRCM_I2CCLKGR_CLK_EN_S)) // Peripheral ID for I2C module 0 +#define PRCM_PERIPH_CRYPTO (0x00000400 | (PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S)) // Peripheral ID for CRYPTO module +#define PRCM_PERIPH_TRNG (0x00000400 | (PRCM_SECDMACLKGR_TRNG_CLK_EN_S)) // Peripheral ID for TRNG module +#define PRCM_PERIPH_UDMA (0x00000400 | (PRCM_SECDMACLKGR_DMA_CLK_EN_S)) // Peripheral ID for UDMA module +#define PRCM_PERIPH_GPIO (0x00000500 | (PRCM_GPIOCLKGR_CLK_EN_S)) // Peripheral ID for GPIO module +#define PRCM_PERIPH_I2S (0x00000600 | (PRCM_I2SCLKGR_CLK_EN_S)) // Peripheral ID for I2S module //***************************************************************************** // @@ -224,18 +222,18 @@ extern "C" static bool PRCMPeripheralValid(uint32_t ui32Peripheral) { - return ((ui32Peripheral == PRCM_PERIPH_TIMER0) || - (ui32Peripheral == PRCM_PERIPH_TIMER1) || - (ui32Peripheral == PRCM_PERIPH_TIMER2) || - (ui32Peripheral == PRCM_PERIPH_TIMER3) || - (ui32Peripheral == PRCM_PERIPH_SSI0) || - (ui32Peripheral == PRCM_PERIPH_SSI1) || - (ui32Peripheral == PRCM_PERIPH_UART0) || - (ui32Peripheral == PRCM_PERIPH_I2C0) || - (ui32Peripheral == PRCM_PERIPH_CRYPTO) || - (ui32Peripheral == PRCM_PERIPH_TRNG) || - (ui32Peripheral == PRCM_PERIPH_UDMA) || - (ui32Peripheral == PRCM_PERIPH_GPIO) || + return ((ui32Peripheral == PRCM_PERIPH_TIMER0) || + (ui32Peripheral == PRCM_PERIPH_TIMER1) || + (ui32Peripheral == PRCM_PERIPH_TIMER2) || + (ui32Peripheral == PRCM_PERIPH_TIMER3) || + (ui32Peripheral == PRCM_PERIPH_SSI0) || + (ui32Peripheral == PRCM_PERIPH_SSI1) || + (ui32Peripheral == PRCM_PERIPH_UART0) || + (ui32Peripheral == PRCM_PERIPH_I2C0) || + (ui32Peripheral == PRCM_PERIPH_CRYPTO) || + (ui32Peripheral == PRCM_PERIPH_TRNG) || + (ui32Peripheral == PRCM_PERIPH_UDMA) || + (ui32Peripheral == PRCM_PERIPH_GPIO) || (ui32Peripheral == PRCM_PERIPH_I2S)); } #endif @@ -397,11 +395,11 @@ PRCMMcuUldoConfigure(uint32_t ui32Enable) // //***************************************************************************** __STATIC_INLINE void -PRCMGPTimerClockDivisionSet( uint32_t clkDiv ) +PRCMGPTimerClockDivisionSet(uint32_t clkDiv) { - ASSERT( clkDiv <= PRCM_GPTCLKDIV_RATIO_DIV256 ); + ASSERT(clkDiv <= PRCM_GPTCLKDIV_RATIO_DIV256); - HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV ) = clkDiv; + HWREG(PRCM_BASE + PRCM_O_GPTCLKDIV) = clkDiv; } //***************************************************************************** @@ -425,12 +423,11 @@ PRCMGPTimerClockDivisionSet( uint32_t clkDiv ) // //***************************************************************************** __STATIC_INLINE uint32_t -PRCMGPTimerClockDivisionGet( void ) +PRCMGPTimerClockDivisionGet(void) { - return ( HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV )); + return (HWREG(PRCM_BASE + PRCM_O_GPTCLKDIV)); } - //***************************************************************************** // //! \brief Enable the audio clock generation. @@ -530,7 +527,7 @@ extern void PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, //***************************************************************************** #ifndef DEPRECATED extern void PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, - uint32_t ui32BitDiv, uint32_t ui32WordDiv); + uint32_t ui32BitDiv, uint32_t ui32WordDiv); #endif //***************************************************************************** @@ -554,12 +551,11 @@ extern void PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui3 //! \return None //! //***************************************************************************** -extern void PRCMAudioClockConfigOverride -(uint8_t ui8SamplingEdge, - uint8_t ui8WCLKPhase, - uint32_t ui32MstDiv, - uint32_t ui32BitDiv, - uint32_t ui32WordDiv); +extern void PRCMAudioClockConfigOverride(uint8_t ui8SamplingEdge, + uint8_t ui8WCLKPhase, + uint32_t ui32MstDiv, + uint32_t ui32BitDiv, + uint32_t ui32WordDiv); //***************************************************************************** // @@ -636,8 +632,7 @@ __STATIC_INLINE bool PRCMLoadGet(void) { // Return the load status. - return ((HWREG(PRCM_BASE + PRCM_O_CLKLOADCTL) & PRCM_CLKLOADCTL_LOAD_DONE) ? - true : false); + return ((HWREG(PRCM_BASE + PRCM_O_CLKLOADCTL) & PRCM_CLKLOADCTL_LOAD_DONE) ? true : false); } //***************************************************************************** @@ -1088,10 +1083,11 @@ PRCMRfReady(void) { // Return the ready status of the RF Core. return ((HWREG(PRCM_BASE + PRCM_O_PDSTAT1RFC) & - PRCM_PDSTAT1RFC_ON) ? true : false); + PRCM_PDSTAT1RFC_ON) + ? true + : false); } - //***************************************************************************** // //! \brief Put the processor into sleep mode. @@ -1139,9 +1135,9 @@ extern void PRCMDeepSleep(void); // //***************************************************************************** __STATIC_INLINE void -PRCMCacheRetentionEnable( void ) +PRCMCacheRetentionEnable(void) { - HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) |= PRCM_RAMRETEN_VIMS_M; + HWREG(PRCM_BASE + PRCM_O_RAMRETEN) |= PRCM_RAMRETEN_VIMS_M; } //***************************************************************************** @@ -1154,12 +1150,11 @@ PRCMCacheRetentionEnable( void ) // //***************************************************************************** __STATIC_INLINE void -PRCMCacheRetentionDisable( void ) +PRCMCacheRetentionDisable(void) { - HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) &= ~PRCM_RAMRETEN_VIMS_M; + HWREG(PRCM_BASE + PRCM_O_RAMRETEN) &= ~PRCM_RAMRETEN_VIMS_M; } - //***************************************************************************** // // Support for DriverLib in ROM: @@ -1169,68 +1164,68 @@ PRCMCacheRetentionDisable( void ) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_PRCMInfClockConfigureSet -#undef PRCMInfClockConfigureSet -#define PRCMInfClockConfigureSet ROM_PRCMInfClockConfigureSet +#undef PRCMInfClockConfigureSet +#define PRCMInfClockConfigureSet ROM_PRCMInfClockConfigureSet #endif #ifdef ROM_PRCMInfClockConfigureGet -#undef PRCMInfClockConfigureGet -#define PRCMInfClockConfigureGet ROM_PRCMInfClockConfigureGet +#undef PRCMInfClockConfigureGet +#define PRCMInfClockConfigureGet ROM_PRCMInfClockConfigureGet #endif #ifdef ROM_PRCMAudioClockConfigSet -#undef PRCMAudioClockConfigSet -#define PRCMAudioClockConfigSet ROM_PRCMAudioClockConfigSet +#undef PRCMAudioClockConfigSet +#define PRCMAudioClockConfigSet ROM_PRCMAudioClockConfigSet #endif #ifdef ROM_PRCMAudioClockConfigSetOverride -#undef PRCMAudioClockConfigSetOverride +#undef PRCMAudioClockConfigSetOverride #define PRCMAudioClockConfigSetOverride ROM_PRCMAudioClockConfigSetOverride #endif #ifdef ROM_PRCMAudioClockInternalSource -#undef PRCMAudioClockInternalSource -#define PRCMAudioClockInternalSource ROM_PRCMAudioClockInternalSource +#undef PRCMAudioClockInternalSource +#define PRCMAudioClockInternalSource ROM_PRCMAudioClockInternalSource #endif #ifdef ROM_PRCMAudioClockExternalSource -#undef PRCMAudioClockExternalSource -#define PRCMAudioClockExternalSource ROM_PRCMAudioClockExternalSource +#undef PRCMAudioClockExternalSource +#define PRCMAudioClockExternalSource ROM_PRCMAudioClockExternalSource #endif #ifdef ROM_PRCMPowerDomainOn -#undef PRCMPowerDomainOn -#define PRCMPowerDomainOn ROM_PRCMPowerDomainOn +#undef PRCMPowerDomainOn +#define PRCMPowerDomainOn ROM_PRCMPowerDomainOn #endif #ifdef ROM_PRCMPowerDomainOff -#undef PRCMPowerDomainOff -#define PRCMPowerDomainOff ROM_PRCMPowerDomainOff +#undef PRCMPowerDomainOff +#define PRCMPowerDomainOff ROM_PRCMPowerDomainOff #endif #ifdef ROM_PRCMPeripheralRunEnable -#undef PRCMPeripheralRunEnable -#define PRCMPeripheralRunEnable ROM_PRCMPeripheralRunEnable +#undef PRCMPeripheralRunEnable +#define PRCMPeripheralRunEnable ROM_PRCMPeripheralRunEnable #endif #ifdef ROM_PRCMPeripheralRunDisable -#undef PRCMPeripheralRunDisable -#define PRCMPeripheralRunDisable ROM_PRCMPeripheralRunDisable +#undef PRCMPeripheralRunDisable +#define PRCMPeripheralRunDisable ROM_PRCMPeripheralRunDisable #endif #ifdef ROM_PRCMPeripheralSleepEnable -#undef PRCMPeripheralSleepEnable -#define PRCMPeripheralSleepEnable ROM_PRCMPeripheralSleepEnable +#undef PRCMPeripheralSleepEnable +#define PRCMPeripheralSleepEnable ROM_PRCMPeripheralSleepEnable #endif #ifdef ROM_PRCMPeripheralSleepDisable -#undef PRCMPeripheralSleepDisable -#define PRCMPeripheralSleepDisable ROM_PRCMPeripheralSleepDisable +#undef PRCMPeripheralSleepDisable +#define PRCMPeripheralSleepDisable ROM_PRCMPeripheralSleepDisable #endif #ifdef ROM_PRCMPeripheralDeepSleepEnable -#undef PRCMPeripheralDeepSleepEnable -#define PRCMPeripheralDeepSleepEnable ROM_PRCMPeripheralDeepSleepEnable +#undef PRCMPeripheralDeepSleepEnable +#define PRCMPeripheralDeepSleepEnable ROM_PRCMPeripheralDeepSleepEnable #endif #ifdef ROM_PRCMPeripheralDeepSleepDisable -#undef PRCMPeripheralDeepSleepDisable -#define PRCMPeripheralDeepSleepDisable ROM_PRCMPeripheralDeepSleepDisable +#undef PRCMPeripheralDeepSleepDisable +#define PRCMPeripheralDeepSleepDisable ROM_PRCMPeripheralDeepSleepDisable #endif #ifdef ROM_PRCMPowerDomainStatus -#undef PRCMPowerDomainStatus -#define PRCMPowerDomainStatus ROM_PRCMPowerDomainStatus +#undef PRCMPowerDomainStatus +#define PRCMPowerDomainStatus ROM_PRCMPowerDomainStatus #endif #ifdef ROM_PRCMDeepSleep -#undef PRCMDeepSleep -#define PRCMDeepSleep ROM_PRCMDeepSleep +#undef PRCMDeepSleep +#define PRCMDeepSleep ROM_PRCMDeepSleep #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/pwr_ctrl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/pwr_ctrl.h index e0ac7ce..ed94acb 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/pwr_ctrl.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/pwr_ctrl.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: pwr_ctrl.h -* Revised: 2017-11-02 15:41:14 +0100 (Thu, 02 Nov 2017) -* Revision: 50165 -* -* Description: Defines and prototypes for the System Power Control. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: pwr_ctrl.h + * Revised: 2017-11-02 15:41:14 +0100 (Thu, 02 Nov 2017) + * Revision: 50165 + * + * Description: Defines and prototypes for the System Power Control. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,26 +55,25 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_aon_wuc.h" -#include "../inc/hw_aon_sysctl.h" -#include "../inc/hw_aon_rtc.h" #include "../inc/hw_adi_2_refsys.h" +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_aon_sysctl.h" +#include "../inc/hw_aon_wuc.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "adi.h" +#include "aon_ioc.h" +#include "cpu.h" #include "debug.h" #include "interrupt.h" #include "osc.h" -#include "cpu.h" #include "prcm.h" -#include "aon_ioc.h" -#include "adi.h" +#include +#include //***************************************************************************** // @@ -90,7 +89,7 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define PowerCtrlSourceSet NOROM_PowerCtrlSourceSet +#define PowerCtrlSourceSet NOROM_PowerCtrlSourceSet #endif //***************************************************************************** @@ -98,37 +97,37 @@ extern "C" // Defines for the system power states // //***************************************************************************** -#define PWRCTRL_ACTIVE 0x00000001 -#define PWRCTRL_STANDBY 0x00000002 -#define PWRCTRL_POWER_DOWN 0x00000004 -#define PWRCTRL_SHUTDOWN 0x00000008 +#define PWRCTRL_ACTIVE 0x00000001 +#define PWRCTRL_STANDBY 0x00000002 +#define PWRCTRL_POWER_DOWN 0x00000004 +#define PWRCTRL_SHUTDOWN 0x00000008 //***************************************************************************** // // Defines for the power configuration in the AON System Control 1.2 V // //***************************************************************************** -#define PWRCTRL_IOSEG3_ENABLE 0x00000800 -#define PWRCTRL_IOSEG2_ENABLE 0x00000400 -#define PWRCTRL_IOSEG3_DISABLE 0x00000200 -#define PWRCTRL_IOSEG2_DISABLE 0x00000100 -#define PWRCTRL_PWRSRC_DCDC 0x00000001 -#define PWRCTRL_PWRSRC_GLDO 0x00000000 -#define PWRCTRL_PWRSRC_ULDO 0x00000002 +#define PWRCTRL_IOSEG3_ENABLE 0x00000800 +#define PWRCTRL_IOSEG2_ENABLE 0x00000400 +#define PWRCTRL_IOSEG3_DISABLE 0x00000200 +#define PWRCTRL_IOSEG2_DISABLE 0x00000100 +#define PWRCTRL_PWRSRC_DCDC 0x00000001 +#define PWRCTRL_PWRSRC_GLDO 0x00000000 +#define PWRCTRL_PWRSRC_ULDO 0x00000002 //***************************************************************************** // // The following are defines for the various reset source for the device. // //***************************************************************************** -#define PWRCTRL_RST_POWER_ON 0x00000000 // Reset by power on -#define PWRCTRL_RST_PIN 0x00000001 // Pin reset -#define PWRCTRL_RST_VDDS_BOD 0x00000002 // VDDS Brown Out Detect -#define PWRCTRL_RST_VDD_BOD 0x00000003 // VDD Brown Out Detect -#define PWRCTRL_RST_VDDR_BOD 0x00000004 // VDDR Brown Out Detect -#define PWRCTRL_RST_CLK_LOSS 0x00000005 // Clock loss Reset -#define PWRCTRL_RST_SW_PIN 0x00000006 // SYSRESET or pin reset -#define PWRCTRL_RST_WARM 0x00000007 // Reset via PRCM warm reset request +#define PWRCTRL_RST_POWER_ON 0x00000000 // Reset by power on +#define PWRCTRL_RST_PIN 0x00000001 // Pin reset +#define PWRCTRL_RST_VDDS_BOD 0x00000002 // VDDS Brown Out Detect +#define PWRCTRL_RST_VDD_BOD 0x00000003 // VDD Brown Out Detect +#define PWRCTRL_RST_VDDR_BOD 0x00000004 // VDDR Brown Out Detect +#define PWRCTRL_RST_CLK_LOSS 0x00000005 // Clock loss Reset +#define PWRCTRL_RST_SW_PIN 0x00000006 // SYSRESET or pin reset +#define PWRCTRL_RST_WARM 0x00000007 // Reset via PRCM warm reset request //***************************************************************************** // @@ -223,9 +222,9 @@ __STATIC_INLINE uint32_t PowerCtrlResetSourceGet(void) { // Get the reset source. - return (( HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) & - AON_SYSCTL_RESETCTL_RESET_SRC_M ) >> - AON_SYSCTL_RESETCTL_RESET_SRC_S ) ; + return ((HWREG(AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL) & + AON_SYSCTL_RESETCTL_RESET_SRC_M) >> + AON_SYSCTL_RESETCTL_RESET_SRC_S); } //***************************************************************************** @@ -272,8 +271,8 @@ PowerCtrlPadSleepDisable(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_PowerCtrlSourceSet -#undef PowerCtrlSourceSet -#define PowerCtrlSourceSet ROM_PowerCtrlSourceSet +#undef PowerCtrlSourceSet +#define PowerCtrlSourceSet ROM_PowerCtrlSourceSet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ble_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ble_cmd.h index f271ccd..f4904dc 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ble_cmd.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ble_cmd.h @@ -1,56 +1,56 @@ /****************************************************************************** -* Filename: rf_ble_cmd.h -* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) -* Revision: 18052 -* -* Description: CC26x0 API for Bluetooth Low Energy commands -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_ble_cmd.h + * Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) + * Revision: 18052 + * + * Description: CC26x0 API for Bluetooth Low Energy commands + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __BLE_CMD_H #define __BLE_CMD_H #ifndef __RFC_STRUCT - #define __RFC_STRUCT +#define __RFC_STRUCT #endif #ifndef __RFC_STRUCT_ATTR - #if defined(__GNUC__) - #define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) - #elif defined(__TI_ARM__) - #define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) - #else - #define __RFC_STRUCT_ATTR - #endif +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__((aligned(4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__((__packed__, aligned(4))) +#else +#define __RFC_STRUCT_ATTR +#endif #endif //! \addtogroup rfc @@ -59,9 +59,9 @@ //! \addtogroup ble_cmd //! @{ -#include -#include "rf_mailbox.h" #include "rf_common_cmd.h" +#include "rf_mailbox.h" +#include typedef struct __RFC_STRUCT rfc_bleRadioOp_s rfc_bleRadioOp_t; typedef struct __RFC_STRUCT rfc_CMD_BLE_SLAVE_s rfc_CMD_BLE_SLAVE_t; @@ -97,518 +97,518 @@ typedef struct __RFC_STRUCT rfc_bleRxStatus_s rfc_bleRxStatus_t; //! @{ struct __RFC_STRUCT rfc_bleRadioOp_s { - uint16_t commandNo; //!< The command ID number - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - uint8_t* pParams; //!< Pointer to command specific parameter structure - uint8_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + uint8_t* pParams; //!< Pointer to command specific parameter structure + uint8_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_SLAVE //! @{ -#define CMD_BLE_SLAVE 0x1801 +#define CMD_BLE_SLAVE 0x1801 //! BLE Slave Command struct __RFC_STRUCT rfc_CMD_BLE_SLAVE_s { - uint16_t commandNo; //!< The command ID number 0x1801 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleSlavePar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleMasterSlaveOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleSlavePar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleMasterSlaveOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_MASTER //! @{ -#define CMD_BLE_MASTER 0x1802 +#define CMD_BLE_MASTER 0x1802 //! BLE Master Command struct __RFC_STRUCT rfc_CMD_BLE_MASTER_s { - uint16_t commandNo; //!< The command ID number 0x1802 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleMasterPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleMasterSlaveOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleMasterPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleMasterSlaveOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_ADV //! @{ -#define CMD_BLE_ADV 0x1803 +#define CMD_BLE_ADV 0x1803 //! BLE Connectable Undirected Advertiser Command struct __RFC_STRUCT rfc_CMD_BLE_ADV_s { - uint16_t commandNo; //!< The command ID number 0x1803 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1803 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_ADV_DIR //! @{ -#define CMD_BLE_ADV_DIR 0x1804 +#define CMD_BLE_ADV_DIR 0x1804 //! BLE Connectable Directed Advertiser Command struct __RFC_STRUCT rfc_CMD_BLE_ADV_DIR_s { - uint16_t commandNo; //!< The command ID number 0x1804 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1804 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_ADV_NC //! @{ -#define CMD_BLE_ADV_NC 0x1805 +#define CMD_BLE_ADV_NC 0x1805 //! BLE Non-Connectable Advertiser Command struct __RFC_STRUCT rfc_CMD_BLE_ADV_NC_s { - uint16_t commandNo; //!< The command ID number 0x1805 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1805 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_ADV_SCAN //! @{ -#define CMD_BLE_ADV_SCAN 0x1806 +#define CMD_BLE_ADV_SCAN 0x1806 //! BLE Scannable Undirected Advertiser Command struct __RFC_STRUCT rfc_CMD_BLE_ADV_SCAN_s { - uint16_t commandNo; //!< The command ID number 0x1806 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1806 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleAdvPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleAdvOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_SCANNER //! @{ -#define CMD_BLE_SCANNER 0x1807 +#define CMD_BLE_SCANNER 0x1807 //! BLE Scanner Command struct __RFC_STRUCT rfc_CMD_BLE_SCANNER_s { - uint16_t commandNo; //!< The command ID number 0x1807 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleScannerPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleScannerOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1807 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleScannerPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleScannerOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_INITIATOR //! @{ -#define CMD_BLE_INITIATOR 0x1808 +#define CMD_BLE_INITIATOR 0x1808 //! BLE Initiator Command struct __RFC_STRUCT rfc_CMD_BLE_INITIATOR_s { - uint16_t commandNo; //!< The command ID number 0x1808 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleInitiatorPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleInitiatorOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1808 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleInitiatorPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleInitiatorOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_GENERIC_RX //! @{ -#define CMD_BLE_GENERIC_RX 0x1809 +#define CMD_BLE_GENERIC_RX 0x1809 //! BLE Generic Receiver Command struct __RFC_STRUCT rfc_CMD_BLE_GENERIC_RX_s { - uint16_t commandNo; //!< The command ID number 0x1809 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleGenericRxPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleGenericRxOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x1809 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleGenericRxPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleGenericRxOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_TX_TEST //! @{ -#define CMD_BLE_TX_TEST 0x180A +#define CMD_BLE_TX_TEST 0x180A //! BLE PHY Test Transmitter Command struct __RFC_STRUCT rfc_CMD_BLE_TX_TEST_s { - uint16_t commandNo; //!< The command ID number 0x180A - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel number
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct - { - uint8_t init: 7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride: 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleTxTestPar_t* pParams; //!< Pointer to command specific parameter structure - rfc_bleTxTestOutput_t* pOutput; //!< Pointer to command specific output structure + uint16_t commandNo; //!< The command ID number 0x180A + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to use
+ //!< 0--39: BLE advertising/data channel number
+ //!< 60--207: Custom frequency; (2300 + channel) MHz
+ //!< 255: Use existing frequency
+ //!< Others: Reserved + struct + { + uint8_t init : 7; //!< \brief If bOverride = 1 or custom frequency is used:
+ //!< 0: Do not use whitening
+ //!< Other value: Initialization for 7-bit LFSR whitener + uint8_t bOverride : 1; //!< \brief 0: Use default whitening for BLE advertising/data channels
+ //!< 1: Override whitening initialization with value of init + } whitening; + rfc_bleTxTestPar_t* pParams; //!< Pointer to command specific parameter structure + rfc_bleTxTestOutput_t* pOutput; //!< Pointer to command specific output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE_ADV_PAYLOAD //! @{ -#define CMD_BLE_ADV_PAYLOAD 0x1001 +#define CMD_BLE_ADV_PAYLOAD 0x1001 //! BLE Update Advertising Payload Command struct __RFC_STRUCT rfc_CMD_BLE_ADV_PAYLOAD_s { - uint16_t commandNo; //!< The command ID number 0x1001 - uint8_t payloadType; //!< \brief 0: Advertising data
- //!< 1: Scan response data - uint8_t newLen; //!< Length of the new payload - uint8_t* pNewData; //!< Pointer to the buffer containing the new data - rfc_bleAdvPar_t* pParams; //!< Pointer to the parameter structure to update + uint16_t commandNo; //!< The command ID number 0x1001 + uint8_t payloadType; //!< \brief 0: Advertising data
+ //!< 1: Scan response data + uint8_t newLen; //!< Length of the new payload + uint8_t* pNewData; //!< Pointer to the buffer containing the new data + rfc_bleAdvPar_t* pParams; //!< Pointer to the parameter structure to update } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BLE5_RADIO_SETUP //! @{ -#define CMD_BLE5_RADIO_SETUP 0x1820 +#define CMD_BLE5_RADIO_SETUP 0x1820 //! Define only for compatibility with CC26XXR2F family. Command will result in error if sent. struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_s { - uint8_t dummy0; + uint8_t dummy0; } __RFC_STRUCT_ATTR; //! @} @@ -617,36 +617,36 @@ struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_s //! @{ struct __RFC_STRUCT rfc_bleMasterSlavePar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - dataQueue_t* pTxQ; //!< Pointer to transmit queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t lastRxSn: 1; //!< The SN bit of the header of the last packet received with CRC OK - uint8_t lastTxSn: 1; //!< The SN bit of the header of the last transmitted packet - uint8_t nextTxSn: 1; //!< The SN bit of the header of the next packet to transmit - uint8_t bFirstPkt: 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise - uint8_t bAutoEmpty: 1; //!< 1 if the last transmitted packet was an auto-empty packet - uint8_t bLlCtrlTx: 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) - uint8_t bLlCtrlAckRx: 1; //!< 1 if the last received packet was the ACK of an LL control packet - uint8_t bLlCtrlAckPending: 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed - } seqStat; - uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit - uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit - uint32_t accessAddress; //!< Access address used on the connection - uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte - uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte - uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t lastRxSn : 1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn : 1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn : 1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt : 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty : 1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx : 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx : 1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending : 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte } __RFC_STRUCT_ATTR; //! @} @@ -657,47 +657,47 @@ struct __RFC_STRUCT rfc_bleMasterSlavePar_s struct __RFC_STRUCT rfc_bleMasterPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - dataQueue_t* pTxQ; //!< Pointer to transmit queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t lastRxSn: 1; //!< The SN bit of the header of the last packet received with CRC OK - uint8_t lastTxSn: 1; //!< The SN bit of the header of the last transmitted packet - uint8_t nextTxSn: 1; //!< The SN bit of the header of the next packet to transmit - uint8_t bFirstPkt: 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise - uint8_t bAutoEmpty: 1; //!< 1 if the last transmitted packet was an auto-empty packet - uint8_t bLlCtrlTx: 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) - uint8_t bLlCtrlAckRx: 1; //!< 1 if the last received packet was the ACK of an LL control packet - uint8_t bLlCtrlAckPending: 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed - } seqStat; - uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit - uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit - uint32_t accessAddress; //!< Access address used on the connection - uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte - uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte - uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< connection event as soon as allowed + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t lastRxSn : 1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn : 1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn : 1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt : 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty : 1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx : 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx : 1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending : 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< connection event as soon as allowed } __RFC_STRUCT_ATTR; //! @} @@ -708,60 +708,60 @@ struct __RFC_STRUCT rfc_bleMasterPar_s struct __RFC_STRUCT rfc_bleSlavePar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - dataQueue_t* pTxQ; //!< Pointer to transmit queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t lastRxSn: 1; //!< The SN bit of the header of the last packet received with CRC OK - uint8_t lastTxSn: 1; //!< The SN bit of the header of the last transmitted packet - uint8_t nextTxSn: 1; //!< The SN bit of the header of the next packet to transmit - uint8_t bFirstPkt: 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise - uint8_t bAutoEmpty: 1; //!< 1 if the last transmitted packet was an auto-empty packet - uint8_t bLlCtrlTx: 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) - uint8_t bLlCtrlAckRx: 1; //!< 1 if the last received packet was the ACK of an LL control packet - uint8_t bLlCtrlAckPending: 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed - } seqStat; - uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit - uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit - uint32_t accessAddress; //!< Access address used on the connection - uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte - uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte - uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } timeoutTrigger; //!< Trigger that defines timeout of the first receive operation - ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that defines timeout of the first - //!< receive operation - uint16_t __dummy0; - uint8_t __dummy1; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< connection event as soon as allowed + dataQueue_t* pRxQ; //!< Pointer to receive queue + dataQueue_t* pTxQ; //!< Pointer to transmit queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t lastRxSn : 1; //!< The SN bit of the header of the last packet received with CRC OK + uint8_t lastTxSn : 1; //!< The SN bit of the header of the last transmitted packet + uint8_t nextTxSn : 1; //!< The SN bit of the header of the next packet to transmit + uint8_t bFirstPkt : 1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise + uint8_t bAutoEmpty : 1; //!< 1 if the last transmitted packet was an auto-empty packet + uint8_t bLlCtrlTx : 1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) + uint8_t bLlCtrlAckRx : 1; //!< 1 if the last received packet was the ACK of an LL control packet + uint8_t bLlCtrlAckPending : 1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed + } seqStat; + uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit + uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that defines timeout of the first receive operation + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that defines timeout of the first + //!< receive operation + uint16_t __dummy0; + uint8_t __dummy1; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< connection event as soon as allowed } __RFC_STRUCT_ATTR; //! @} @@ -772,55 +772,55 @@ struct __RFC_STRUCT rfc_bleSlavePar_s struct __RFC_STRUCT rfc_bleAdvPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t advFilterPolicy: 2; //!< \brief Advertiser filter policy
- //!< 0: Process scan and connect requests from all devices
- //!< 1: Process connect requests from all devices and only scan requests from - //!< devices that are in the white list
- //!< 2: Process scan requests from all devices and only connect requests from - //!< devices that are in the white list
- //!< 3: Process scan and connect requests only from devices in the white list - uint8_t deviceAddrType: 1; //!< The type of the device address -- public (0) or random (1) - uint8_t peerAddrType: 1; //!< Directed advertiser: The type of the peer address -- public (0) or random (1) - uint8_t bStrictLenFilter: 1; //!< \brief 0: Accept any packet with a valid advertising packet length
- //!< 1: Discard messages with illegal length for the given packet type - uint8_t : 2; - uint8_t rpaMode: 1; //!< \brief Resolvable private address mode
- //!< 0: Normal operation
- //!< 1: Use white list for a received RPA regardless of filter policy - } advConfig; - uint8_t advLen; //!< Size of advertiser data - uint8_t scanRspLen; //!< Size of scan response data - uint8_t* pAdvData; //!< Pointer to buffer containing ADV*_IND data - uint8_t* pScanRspData; //!< Pointer to buffer containing SCAN_RSP data - uint16_t* pDeviceAddress; //!< Pointer to device address used for this device - rfc_bleWhiteListEntry_t* pWhiteList; //!< Pointer to white list or peer address (directed advertiser) - uint16_t __dummy0; - uint8_t __dummy1; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the advertiser event as soon as allowed - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< advertiser event as soon as allowed + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t advFilterPolicy : 2; //!< \brief Advertiser filter policy
+ //!< 0: Process scan and connect requests from all devices
+ //!< 1: Process connect requests from all devices and only scan requests from + //!< devices that are in the white list
+ //!< 2: Process scan requests from all devices and only connect requests from + //!< devices that are in the white list
+ //!< 3: Process scan and connect requests only from devices in the white list + uint8_t deviceAddrType : 1; //!< The type of the device address -- public (0) or random (1) + uint8_t peerAddrType : 1; //!< Directed advertiser: The type of the peer address -- public (0) or random (1) + uint8_t bStrictLenFilter : 1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t : 2; + uint8_t rpaMode : 1; //!< \brief Resolvable private address mode
+ //!< 0: Normal operation
+ //!< 1: Use white list for a received RPA regardless of filter policy + } advConfig; + uint8_t advLen; //!< Size of advertiser data + uint8_t scanRspLen; //!< Size of scan response data + uint8_t* pAdvData; //!< Pointer to buffer containing ADV*_IND data + uint8_t* pScanRspData; //!< Pointer to buffer containing SCAN_RSP data + uint16_t* pDeviceAddress; //!< Pointer to device address used for this device + rfc_bleWhiteListEntry_t* pWhiteList; //!< Pointer to white list or peer address (directed advertiser) + uint16_t __dummy0; + uint8_t __dummy1; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the advertiser event as soon as allowed + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< advertiser event as soon as allowed } __RFC_STRUCT_ATTR; //! @} @@ -831,74 +831,74 @@ struct __RFC_STRUCT rfc_bleAdvPar_s struct __RFC_STRUCT rfc_bleScannerPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t scanFilterPolicy: 1; //!< \brief Scanning filter policy
- //!< 0: Accept all advertisement packets
- //!< 1: Accept only advertisement packets from devices where the advertiser's address - //!< is in the White list. - uint8_t bActiveScan: 1; //!< \brief 0: Passive scan
- //!< 1: Active scan - uint8_t deviceAddrType: 1; //!< The type of the device address -- public (0) or random (1) - uint8_t : 1; - uint8_t bStrictLenFilter: 1; //!< \brief 0: Accept any packet with a valid advertising packet length
- //!< 1: Discard messages with illegal length for the given packet type - uint8_t bAutoWlIgnore: 1; //!< 1: Automatically set ignore bit in white list - uint8_t bEndOnRpt: 1; //!< \brief 0: Continue scanner operation after each reporting ADV*_IND or sending SCAN_RSP
- //!< 1: End scanner operation after each reported ADV*_IND and potentially SCAN_RSP - uint8_t rpaMode: 1; //!< \brief Resolvable private address mode
- //!< 0: Normal operation
- //!< 1: Use white list for a received RPA regardless of filter policy - } scanConfig; - uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure - uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth 4.0 spec - struct - { - uint8_t logUpperLimit: 4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure - uint8_t bLastSucceeded: 1; //!< \brief 1 if the last SCAN_RSP was successfully received and upperLimit - //!< not changed - uint8_t bLastFailed: 1; //!< \brief 1 if reception of the last SCAN_RSP failed and upperLimit was not - //!< changed - } backoffPar; - uint8_t scanReqLen; //!< Size of scan request data - uint8_t* pScanReqData; //!< Pointer to buffer containing SCAN_REQ data - uint16_t* pDeviceAddress; //!< Pointer to device address used for this device - rfc_bleWhiteListEntry_t* pWhiteList; //!< Pointer to white list - uint16_t __dummy0; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_ENDED + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t scanFilterPolicy : 1; //!< \brief Scanning filter policy
+ //!< 0: Accept all advertisement packets
+ //!< 1: Accept only advertisement packets from devices where the advertiser's address + //!< is in the White list. + uint8_t bActiveScan : 1; //!< \brief 0: Passive scan
+ //!< 1: Active scan + uint8_t deviceAddrType : 1; //!< The type of the device address -- public (0) or random (1) + uint8_t : 1; + uint8_t bStrictLenFilter : 1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + uint8_t bAutoWlIgnore : 1; //!< 1: Automatically set ignore bit in white list + uint8_t bEndOnRpt : 1; //!< \brief 0: Continue scanner operation after each reporting ADV*_IND or sending SCAN_RSP
+ //!< 1: End scanner operation after each reported ADV*_IND and potentially SCAN_RSP + uint8_t rpaMode : 1; //!< \brief Resolvable private address mode
+ //!< 0: Normal operation
+ //!< 1: Use white list for a received RPA regardless of filter policy + } scanConfig; + uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure + uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth 4.0 spec + struct + { + uint8_t logUpperLimit : 4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure + uint8_t bLastSucceeded : 1; //!< \brief 1 if the last SCAN_RSP was successfully received and upperLimit + //!< not changed + uint8_t bLastFailed : 1; //!< \brief 1 if reception of the last SCAN_RSP failed and upperLimit was not + //!< changed + } backoffPar; + uint8_t scanReqLen; //!< Size of scan request data + uint8_t* pScanReqData; //!< Pointer to buffer containing SCAN_REQ data + uint16_t* pDeviceAddress; //!< Pointer to device address used for this device + rfc_bleWhiteListEntry_t* pWhiteList; //!< Pointer to white list + uint16_t __dummy0; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_ENDED } __RFC_STRUCT_ATTR; //! @} @@ -909,61 +909,61 @@ struct __RFC_STRUCT rfc_bleScannerPar_s struct __RFC_STRUCT rfc_bleInitiatorPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct - { - uint8_t bUseWhiteList: 1; //!< \brief Initiator filter policy
- //!< 0: Use specific peer address
- //!< 1: Use white list - uint8_t bDynamicWinOffset: 1; //!< \brief 0: No dynamic WinOffset insertion
- //!< 1: Use dynamic WinOffset insertion - uint8_t deviceAddrType: 1; //!< The type of the device address -- public (0) or random (1) - uint8_t peerAddrType: 1; //!< The type of the peer address -- public (0) or random (1) - uint8_t bStrictLenFilter: 1; //!< \brief 0: Accept any packet with a valid advertising packet length
- //!< 1: Discard messages with illegal length for the given packet type - } initConfig; - uint8_t __dummy0; - uint8_t connectReqLen; //!< Size of connect request data - uint8_t* pConnectReqData; //!< Pointer to buffer containing LLData to go in the CONNECT_REQ - uint16_t* pDeviceAddress; //!< Pointer to device address used for this device - rfc_bleWhiteListEntry_t* pWhiteList; //!< Pointer to white list or peer address - ratmr_t connectTime; //!< \brief Indication of timer value of the first possible start time of the first connection event. - //!< Set to the calculated value if a connection is made and to the next possible connection - //!< time if not. - uint16_t __dummy1; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_ENDED + dataQueue_t* pRxQ; //!< Pointer to receive queue + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + struct + { + uint8_t bUseWhiteList : 1; //!< \brief Initiator filter policy
+ //!< 0: Use specific peer address
+ //!< 1: Use white list + uint8_t bDynamicWinOffset : 1; //!< \brief 0: No dynamic WinOffset insertion
+ //!< 1: Use dynamic WinOffset insertion + uint8_t deviceAddrType : 1; //!< The type of the device address -- public (0) or random (1) + uint8_t peerAddrType : 1; //!< The type of the peer address -- public (0) or random (1) + uint8_t bStrictLenFilter : 1; //!< \brief 0: Accept any packet with a valid advertising packet length
+ //!< 1: Discard messages with illegal length for the given packet type + } initConfig; + uint8_t __dummy0; + uint8_t connectReqLen; //!< Size of connect request data + uint8_t* pConnectReqData; //!< Pointer to buffer containing LLData to go in the CONNECT_REQ + uint16_t* pDeviceAddress; //!< Pointer to device address used for this device + rfc_bleWhiteListEntry_t* pWhiteList; //!< Pointer to white list or peer address + ratmr_t connectTime; //!< \brief Indication of timer value of the first possible start time of the first connection event. + //!< Set to the calculated value if a connection is made and to the next possible connection + //!< time if not. + uint16_t __dummy1; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed + ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop + //!< receiving as soon as allowed, ending with BLE_DONE_ENDED } __RFC_STRUCT_ATTR; //! @} @@ -974,36 +974,36 @@ struct __RFC_STRUCT rfc_bleInitiatorPar_s struct __RFC_STRUCT rfc_bleGenericRxPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue. May be NULL; if so, received packets are not stored - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty: 1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte: 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the Rx queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - uint8_t bRepeat; //!< \brief 0: End operation after receiving a packet
- //!< 1: Restart receiver after receiving a packet - uint16_t __dummy0; - uint32_t accessAddress; //!< Access address used on the connection - uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte - uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte - uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the Rx operation - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< Rx operation + dataQueue_t* pRxQ; //!< Pointer to receive queue. May be NULL; if so, received packets are not stored + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically remove ignored packets from Rx queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushEmpty : 1; //!< If 1, automatically remove empty packets from Rx queue + uint8_t bIncludeLenByte : 1; //!< If 1, include the received length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the Rx queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; //!< Configuration bits for the receive queue entries + uint8_t bRepeat; //!< \brief 0: End operation after receiving a packet
+ //!< 1: Restart receiver after receiving a packet + uint16_t __dummy0; + uint32_t accessAddress; //!< Access address used on the connection + uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte + uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte + uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Rx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< Rx operation } __RFC_STRUCT_ATTR; //! @} @@ -1014,34 +1014,34 @@ struct __RFC_STRUCT rfc_bleGenericRxPar_s struct __RFC_STRUCT rfc_bleTxTestPar_s { - uint16_t numPackets; //!< \brief Number of packets to transmit
- //!< 0: Transmit unlimited number of packets - uint8_t payloadLength; //!< The number of payload bytes in each packet. - uint8_t packetType; //!< \brief The packet type to be used, encoded according to the Bluetooth 4.0 spec, Volume 2, Part E, - //!< Section 7.8.29 - ratmr_t period; //!< Number of radio timer cycles between the start of each packet - struct - { - uint8_t bOverrideDefault: 1; //!< \brief 0: Use default packet encoding
- //!< 1: Override packet contents - uint8_t bUsePrbs9: 1; //!< \brief If bOverride is 1:
- //!< 1: Use PRBS9 encoding of packet - uint8_t bUsePrbs15: 1; //!< \brief If bOverride is 1:
- //!< 1: Use PRBS15 encoding of packet - } config; - uint8_t byteVal; //!< If config.bOverride is 1, value of each byte to be sent - uint8_t __dummy0; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the Test Tx operation - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< Test Tx operation + uint16_t numPackets; //!< \brief Number of packets to transmit
+ //!< 0: Transmit unlimited number of packets + uint8_t payloadLength; //!< The number of payload bytes in each packet. + uint8_t packetType; //!< \brief The packet type to be used, encoded according to the Bluetooth 4.0 spec, Volume 2, Part E, + //!< Section 7.8.29 + ratmr_t period; //!< Number of radio timer cycles between the start of each packet + struct + { + uint8_t bOverrideDefault : 1; //!< \brief 0: Use default packet encoding
+ //!< 1: Override packet contents + uint8_t bUsePrbs9 : 1; //!< \brief If bOverride is 1:
+ //!< 1: Use PRBS9 encoding of packet + uint8_t bUsePrbs15 : 1; //!< \brief If bOverride is 1:
+ //!< 1: Use PRBS15 encoding of packet + } config; + uint8_t byteVal; //!< If config.bOverride is 1, value of each byte to be sent + uint8_t __dummy0; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Test Tx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< Test Tx operation } __RFC_STRUCT_ATTR; //! @} @@ -1052,37 +1052,37 @@ struct __RFC_STRUCT rfc_bleTxTestPar_s struct __RFC_STRUCT rfc_bleMasterSlaveOutput_s { - uint8_t nTx; //!< \brief Total number of packets (including auto-empty and retransmissions) that have been - //!< transmitted - uint8_t nTxAck; //!< Total number of transmitted packets (including auto-empty) that have been ACK'ed - uint8_t nTxCtrl; //!< Number of unique LL control packets from the Tx queue that have been transmitted - uint8_t nTxCtrlAck; //!< Number of LL control packets from the Tx queue that have been finished (ACK'ed) - uint8_t nTxCtrlAckAck; //!< \brief Number of LL control packets that have been ACK'ed and where an ACK has been sent in - //!< response - uint8_t nTxRetrans; //!< Number of retransmissions that has been done - uint8_t nTxEntryDone; //!< Number of packets from the Tx queue that have been finished (ACK'ed) - uint8_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored - uint8_t nRxCtrl; //!< Number of LL control packets that have been received with CRC OK and not ignored - uint8_t nRxCtrlAck; //!< \brief Number of LL control packets that have been received with CRC OK and not ignored, and - //!< then ACK'ed - uint8_t nRxNok; //!< Number of packets that have been received with CRC error - uint8_t nRxIgnored; //!< \brief Number of packets that have been received with CRC OK and ignored due to repeated - //!< sequence number - uint8_t nRxEmpty; //!< Number of packets that have been received with CRC OK and no payload - uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space - int8_t lastRssi; //!< RSSI of last received packet - struct - { - uint8_t bTimeStampValid: 1; //!< 1 if a valid time stamp has been written to timeStamp; 0 otherwise - uint8_t bLastCrcErr: 1; //!< 1 if the last received packet had CRC error; 0 otherwise - uint8_t bLastIgnored: 1; //!< 1 if the last received packet with CRC OK was ignored; 0 otherwise - uint8_t bLastEmpty: 1; //!< 1 if the last received packet with CRC OK was empty; 0 otherwise - uint8_t bLastCtrl: 1; //!< 1 if the last received packet with CRC OK was empty; 0 otherwise - uint8_t bLastMd: 1; //!< 1 if the last received packet with CRC OK had MD = 1; 0 otherwise - uint8_t bLastAck: 1; //!< \brief 1 if the last received packet with CRC OK was an ACK of a transmitted packet; - //!< 0 otherwise - } pktStatus; - ratmr_t timeStamp; //!< Slave operation: Time stamp of first received packet + uint8_t nTx; //!< \brief Total number of packets (including auto-empty and retransmissions) that have been + //!< transmitted + uint8_t nTxAck; //!< Total number of transmitted packets (including auto-empty) that have been ACK'ed + uint8_t nTxCtrl; //!< Number of unique LL control packets from the Tx queue that have been transmitted + uint8_t nTxCtrlAck; //!< Number of LL control packets from the Tx queue that have been finished (ACK'ed) + uint8_t nTxCtrlAckAck; //!< \brief Number of LL control packets that have been ACK'ed and where an ACK has been sent in + //!< response + uint8_t nTxRetrans; //!< Number of retransmissions that has been done + uint8_t nTxEntryDone; //!< Number of packets from the Tx queue that have been finished (ACK'ed) + uint8_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored + uint8_t nRxCtrl; //!< Number of LL control packets that have been received with CRC OK and not ignored + uint8_t nRxCtrlAck; //!< \brief Number of LL control packets that have been received with CRC OK and not ignored, and + //!< then ACK'ed + uint8_t nRxNok; //!< Number of packets that have been received with CRC error + uint8_t nRxIgnored; //!< \brief Number of packets that have been received with CRC OK and ignored due to repeated + //!< sequence number + uint8_t nRxEmpty; //!< Number of packets that have been received with CRC OK and no payload + uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< RSSI of last received packet + struct + { + uint8_t bTimeStampValid : 1; //!< 1 if a valid time stamp has been written to timeStamp; 0 otherwise + uint8_t bLastCrcErr : 1; //!< 1 if the last received packet had CRC error; 0 otherwise + uint8_t bLastIgnored : 1; //!< 1 if the last received packet with CRC OK was ignored; 0 otherwise + uint8_t bLastEmpty : 1; //!< 1 if the last received packet with CRC OK was empty; 0 otherwise + uint8_t bLastCtrl : 1; //!< 1 if the last received packet with CRC OK was empty; 0 otherwise + uint8_t bLastMd : 1; //!< 1 if the last received packet with CRC OK had MD = 1; 0 otherwise + uint8_t bLastAck : 1; //!< \brief 1 if the last received packet with CRC OK was an ACK of a transmitted packet; + //!< 0 otherwise + } pktStatus; + ratmr_t timeStamp; //!< Slave operation: Time stamp of first received packet } __RFC_STRUCT_ATTR; //! @} @@ -1093,16 +1093,16 @@ struct __RFC_STRUCT rfc_bleMasterSlaveOutput_s struct __RFC_STRUCT rfc_bleAdvOutput_s { - uint16_t nTxAdvInd; //!< Number of ADV*_IND packets completely transmitted - uint8_t nTxScanRsp; //!< Number of SCAN_RSP packets transmitted - uint8_t nRxScanReq; //!< Number of SCAN_REQ packets received OK and not ignored - uint8_t nRxConnectReq; //!< Number of CONNECT_REQ packets received OK and not ignored - uint8_t __dummy0; - uint16_t nRxNok; //!< Number of packets received with CRC error - uint16_t nRxIgnored; //!< Number of packets received with CRC OK, but ignored - uint8_t nRxBufFull; //!< Number of packets received that did not fit in Rx queue - int8_t lastRssi; //!< The RSSI of the last received packet - ratmr_t timeStamp; //!< Time stamp of the last received packet + uint16_t nTxAdvInd; //!< Number of ADV*_IND packets completely transmitted + uint8_t nTxScanRsp; //!< Number of SCAN_RSP packets transmitted + uint8_t nRxScanReq; //!< Number of SCAN_REQ packets received OK and not ignored + uint8_t nRxConnectReq; //!< Number of CONNECT_REQ packets received OK and not ignored + uint8_t __dummy0; + uint16_t nRxNok; //!< Number of packets received with CRC error + uint16_t nRxIgnored; //!< Number of packets received with CRC OK, but ignored + uint8_t nRxBufFull; //!< Number of packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet + ratmr_t timeStamp; //!< Time stamp of the last received packet } __RFC_STRUCT_ATTR; //! @} @@ -1113,19 +1113,19 @@ struct __RFC_STRUCT rfc_bleAdvOutput_s struct __RFC_STRUCT rfc_bleScannerOutput_s { - uint16_t nTxScanReq; //!< Number of transmitted SCAN_REQ packets - uint16_t nBackedOffScanReq; //!< Number of SCAN_REQ packets not sent due to backoff procedure - uint16_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored - uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored - uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error - uint16_t nRxScanRspOk; //!< Number of SCAN_RSP packets received with CRC OK and not ignored - uint16_t nRxScanRspIgnored; //!< Number of SCAN_RSP packets received with CRC OK, but ignored - uint16_t nRxScanRspNok; //!< Number of SCAN_RSP packets received with CRC error - uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue - uint8_t nRxScanRspBufFull; //!< Number of SCAN_RSP packets received that did not fit in Rx queue - int8_t lastRssi; //!< The RSSI of the last received packet - uint8_t __dummy0; - ratmr_t timeStamp; //!< Time stamp of the last successfully received ADV*_IND packet that was not ignored + uint16_t nTxScanReq; //!< Number of transmitted SCAN_REQ packets + uint16_t nBackedOffScanReq; //!< Number of SCAN_REQ packets not sent due to backoff procedure + uint16_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored + uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored + uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error + uint16_t nRxScanRspOk; //!< Number of SCAN_RSP packets received with CRC OK and not ignored + uint16_t nRxScanRspIgnored; //!< Number of SCAN_RSP packets received with CRC OK, but ignored + uint16_t nRxScanRspNok; //!< Number of SCAN_RSP packets received with CRC error + uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue + uint8_t nRxScanRspBufFull; //!< Number of SCAN_RSP packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet + uint8_t __dummy0; + ratmr_t timeStamp; //!< Time stamp of the last successfully received ADV*_IND packet that was not ignored } __RFC_STRUCT_ATTR; //! @} @@ -1136,13 +1136,13 @@ struct __RFC_STRUCT rfc_bleScannerOutput_s struct __RFC_STRUCT rfc_bleInitiatorOutput_s { - uint8_t nTxConnectReq; //!< Number of transmitted CONNECT_REQ packets - uint8_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored - uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored - uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error - uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue - int8_t lastRssi; //!< The RSSI of the last received packet - ratmr_t timeStamp; //!< Time stamp of the received ADV*_IND packet that caused transmission of CONNECT_REQ + uint8_t nTxConnectReq; //!< Number of transmitted CONNECT_REQ packets + uint8_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored + uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored + uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error + uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue + int8_t lastRssi; //!< The RSSI of the last received packet + ratmr_t timeStamp; //!< Time stamp of the received ADV*_IND packet that caused transmission of CONNECT_REQ } __RFC_STRUCT_ATTR; //! @} @@ -1153,12 +1153,12 @@ struct __RFC_STRUCT rfc_bleInitiatorOutput_s struct __RFC_STRUCT rfc_bleGenericRxOutput_s { - uint16_t nRxOk; //!< Number of packets received with CRC OK - uint16_t nRxNok; //!< Number of packets received with CRC error - uint16_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space - int8_t lastRssi; //!< The RSSI of the last received packet - uint8_t __dummy0; - ratmr_t timeStamp; //!< Time stamp of the last received packet + uint16_t nRxOk; //!< Number of packets received with CRC OK + uint16_t nRxNok; //!< Number of packets received with CRC error + uint16_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< The RSSI of the last received packet + uint8_t __dummy0; + ratmr_t timeStamp; //!< Time stamp of the last received packet } __RFC_STRUCT_ATTR; //! @} @@ -1169,7 +1169,7 @@ struct __RFC_STRUCT rfc_bleGenericRxOutput_s struct __RFC_STRUCT rfc_bleTxTestOutput_s { - uint16_t nTx; //!< Number of packets transmitted + uint16_t nTx; //!< Number of packets transmitted } __RFC_STRUCT_ATTR; //! @} @@ -1180,19 +1180,19 @@ struct __RFC_STRUCT rfc_bleTxTestOutput_s struct __RFC_STRUCT rfc_bleWhiteListEntry_s { - uint8_t size; //!< Number of while list entries. Used in the first entry of the list only - struct - { - uint8_t bEnable: 1; //!< 1 if the entry is in use, 0 if the entry is not in use - uint8_t addrType: 1; //!< The type address in the entry -- public (0) or random (1) - uint8_t bWlIgn: 1; //!< \brief 1 if the entry is to be ignored by a scanner, 0 otherwise. Used to mask out - //!< entries that have already been scanned and reported. - uint8_t : 1; - uint8_t bIrkValid: 1; //!< \brief 1 if a valid IRK exists, so that the entry is to be ignored by an initiator, - //!< 0 otherwise - } conf; - uint16_t address; //!< Least significant 16 bits of the address contained in the entry - uint32_t addressHi; //!< Most significant 32 bits of the address contained in the entry + uint8_t size; //!< Number of while list entries. Used in the first entry of the list only + struct + { + uint8_t bEnable : 1; //!< 1 if the entry is in use, 0 if the entry is not in use + uint8_t addrType : 1; //!< The type address in the entry -- public (0) or random (1) + uint8_t bWlIgn : 1; //!< \brief 1 if the entry is to be ignored by a scanner, 0 otherwise. Used to mask out + //!< entries that have already been scanned and reported. + uint8_t : 1; + uint8_t bIrkValid : 1; //!< \brief 1 if a valid IRK exists, so that the entry is to be ignored by an initiator, + //!< 0 otherwise + } conf; + uint16_t address; //!< Least significant 16 bits of the address contained in the entry + uint32_t addressHi; //!< Most significant 32 bits of the address contained in the entry } __RFC_STRUCT_ATTR; //! @} @@ -1203,13 +1203,13 @@ struct __RFC_STRUCT rfc_bleWhiteListEntry_s struct __RFC_STRUCT rfc_bleRxStatus_s { - struct - { - uint8_t channel: 6; //!< \brief The channel on which the packet was received, provided channel is in the range - //!< 0--39; otherwise 0x3F - uint8_t bIgnore: 1; //!< 1 if the packet is marked as ignored, 0 otherwise - uint8_t bCrcErr: 1; //!< 1 if the packet was received with CRC error, 0 otherwise - } status; + struct + { + uint8_t channel : 6; //!< \brief The channel on which the packet was received, provided channel is in the range + //!< 0--39; otherwise 0x3F + uint8_t bIgnore : 1; //!< 1 if the packet is marked as ignored, 0 otherwise + uint8_t bCrcErr : 1; //!< 1 if the packet was received with CRC error, 0 otherwise + } status; } __RFC_STRUCT_ATTR; //! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ble_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ble_mailbox.h index 4158977..239448e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ble_mailbox.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ble_mailbox.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_ble_mailbox.h -* Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) -* Revision: 18032 -* -* Description: Definitions for BLE interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_ble_mailbox.h + * Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) + * Revision: 18032 + * + * Description: Definitions for BLE interface + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _BLE_MAILBOX_H #define _BLE_MAILBOX_H @@ -43,25 +43,25 @@ ///@{ /// \name Operation finished normally ///@{ -#define BLE_DONE_OK 0x1400 ///< Operation ended normally -#define BLE_DONE_RXTIMEOUT 0x1401 ///< Timeout of first Rx of slave operation or end of scan window -#define BLE_DONE_NOSYNC 0x1402 ///< Timeout of subsequent Rx -#define BLE_DONE_RXERR 0x1403 ///< Operation ended because of receive error (CRC or other) -#define BLE_DONE_CONNECT 0x1404 ///< CONNECT_REQ received or transmitted -#define BLE_DONE_MAXNACK 0x1405 ///< Maximum number of retransmissions exceeded -#define BLE_DONE_ENDED 0x1406 ///< Operation stopped after end trigger -#define BLE_DONE_ABORT 0x1407 ///< Operation aborted by command -#define BLE_DONE_STOPPED 0x1408 ///< Operation stopped after stop command +#define BLE_DONE_OK 0x1400 ///< Operation ended normally +#define BLE_DONE_RXTIMEOUT 0x1401 ///< Timeout of first Rx of slave operation or end of scan window +#define BLE_DONE_NOSYNC 0x1402 ///< Timeout of subsequent Rx +#define BLE_DONE_RXERR 0x1403 ///< Operation ended because of receive error (CRC or other) +#define BLE_DONE_CONNECT 0x1404 ///< CONNECT_REQ received or transmitted +#define BLE_DONE_MAXNACK 0x1405 ///< Maximum number of retransmissions exceeded +#define BLE_DONE_ENDED 0x1406 ///< Operation stopped after end trigger +#define BLE_DONE_ABORT 0x1407 ///< Operation aborted by command +#define BLE_DONE_STOPPED 0x1408 ///< Operation stopped after stop command ///@} /// \name Operation finished with error ///@{ -#define BLE_ERROR_PAR 0x1800 ///< Illegal parameter -#define BLE_ERROR_RXBUF 0x1801 ///< No available Rx buffer (Advertiser, Scanner, Initiator) -#define BLE_ERROR_NO_SETUP 0x1802 ///< Operation using Rx or Tx attemted when not in BLE mode -#define BLE_ERROR_NO_FS 0x1803 ///< Operation using Rx or Tx attemted without frequency synth configured -#define BLE_ERROR_SYNTH_PROG 0x1804 ///< Synthesizer programming failed to complete on time -#define BLE_ERROR_RXOVF 0x1805 ///< Receiver overflowed during operation -#define BLE_ERROR_TXUNF 0x1806 ///< Transmitter underflowed during operation +#define BLE_ERROR_PAR 0x1800 ///< Illegal parameter +#define BLE_ERROR_RXBUF 0x1801 ///< No available Rx buffer (Advertiser, Scanner, Initiator) +#define BLE_ERROR_NO_SETUP 0x1802 ///< Operation using Rx or Tx attemted when not in BLE mode +#define BLE_ERROR_NO_FS 0x1803 ///< Operation using Rx or Tx attemted without frequency synth configured +#define BLE_ERROR_SYNTH_PROG 0x1804 ///< Synthesizer programming failed to complete on time +#define BLE_ERROR_RXOVF 0x1805 ///< Receiver overflowed during operation +#define BLE_ERROR_TXUNF 0x1806 ///< Transmitter underflowed during operation ///@} ///@} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_common_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_common_cmd.h index bb5bf76..313ed0d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_common_cmd.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_common_cmd.h @@ -1,56 +1,56 @@ /****************************************************************************** -* Filename: rf_common_cmd.h -* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) -* Revision: 18052 -* -* Description: CC26x0 API for common/generic commands -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_common_cmd.h + * Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) + * Revision: 18052 + * + * Description: CC26x0 API for common/generic commands + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __COMMON_CMD_H #define __COMMON_CMD_H #ifndef __RFC_STRUCT - #define __RFC_STRUCT +#define __RFC_STRUCT #endif #ifndef __RFC_STRUCT_ATTR - #if defined(__GNUC__) - #define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) - #elif defined(__TI_ARM__) - #define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) - #else - #define __RFC_STRUCT_ATTR - #endif +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__((aligned(4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__((__packed__, aligned(4))) +#else +#define __RFC_STRUCT_ATTR +#endif #endif //! \addtogroup rfc @@ -59,8 +59,8 @@ //! \addtogroup common_cmd //! @{ -#include #include "rf_mailbox.h" +#include typedef struct __RFC_STRUCT rfc_command_s rfc_command_t; typedef struct __RFC_STRUCT rfc_radioOp_s rfc_radioOp_t; @@ -106,7 +106,7 @@ typedef struct __RFC_STRUCT rfc_CMD_BUS_REQUEST_s rfc_CMD_BUS_REQUEST_t; //! @{ struct __RFC_STRUCT rfc_command_s { - uint16_t commandNo; //!< The command ID number + uint16_t commandNo; //!< The command ID number } __RFC_STRUCT_ATTR; //! @} @@ -117,900 +117,900 @@ struct __RFC_STRUCT rfc_command_s struct __RFC_STRUCT rfc_radioOp_s { - uint16_t commandNo; //!< The command ID number - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; + uint16_t commandNo; //!< The command ID number + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_NOP //! @{ -#define CMD_NOP 0x0801 +#define CMD_NOP 0x0801 //! No Operation Command struct __RFC_STRUCT rfc_CMD_NOP_s { - uint16_t commandNo; //!< The command ID number 0x0801 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; + uint16_t commandNo; //!< The command ID number 0x0801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_RADIO_SETUP //! @{ -#define CMD_RADIO_SETUP 0x0802 +#define CMD_RADIO_SETUP 0x0802 //! Radio Setup Command for Pre-Defined Schemes struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_s { - uint16_t commandNo; //!< The command ID number 0x0802 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t mode; //!< \brief The main mode to use
- //!< 0x00: BLE
- //!< 0x01: IEEE 802.15.4
- //!< 0x02: 2 Mbps GFSK
- //!< 0x05: 5 Mbps coded 8-FSK
- //!< 0xFF: Keep existing mode; update overrides only
- //!< Others: Reserved - uint8_t __dummy0; - struct - { - uint16_t frontEndMode: 3; //!< \brief 0x00: Differential mode
- //!< 0x01: Single-ended mode RFP
- //!< 0x02: Single-ended mode RFN
- //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
- //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ uint16_t commandNo; //!< The command ID number 0x0802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t mode; //!< \brief The main mode to use
+ //!< 0x00: BLE
+ //!< 0x01: IEEE 802.15.4
+ //!< 0x02: 2 Mbps GFSK
+ //!< 0x05: 5 Mbps coded 8-FSK
+ //!< 0xFF: Keep existing mode; update overrides only
//!< Others: Reserved - uint16_t biasMode: 1; //!< \brief 0: Internal bias
- //!< 1: External bias - uint16_t analogCfgMode: 6; //!< \brief 0x00: Write analog configuration.
- //!< Required first time after boot and when changing frequency band - //!< or front-end configuration
- //!< 0x2D: Keep analog configuration.
- //!< May be used after standby or when changing mode with the same frequency - //!< band and front-end configuration
- //!< Others: Reserved - uint16_t bNoFsPowerUp: 1; //!< \brief 0: Power up frequency synth
- //!< 1: Do not power up frequency synth - } config; //!< Configuration options - uint16_t txPower; //!< \brief Transmit power - //!< Bits 0--5: IB - //!< Value to write to the PA power control field at 25 °C - //!< Bits 6--7: GC - //!< Value to write to the gain control of the 1st stage of the PA - //!< Bits 8--15: tempCoeff - //!< Temperature coefficient for IB. 0: No temperature compensation - uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no - //!< override is used. + uint8_t __dummy0; + struct + { + uint16_t frontEndMode : 3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode : 1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode : 6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp : 1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< \brief Transmit power + //!< Bits 0--5: IB + //!< Value to write to the PA power control field at 25 °C + //!< Bits 6--7: GC + //!< Value to write to the gain control of the 1st stage of the PA + //!< Bits 8--15: tempCoeff + //!< Temperature coefficient for IB. 0: No temperature compensation + uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no + //!< override is used. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_FS //! @{ -#define CMD_FS 0x0803 +#define CMD_FS 0x0803 //! Frequency Synthesizer Programming Command struct __RFC_STRUCT rfc_CMD_FS_s { - uint16_t commandNo; //!< The command ID number 0x0803 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t frequency; //!< The frequency in MHz to tune to - uint16_t fractFreq; //!< Fractional part of the frequency to tune to - struct - { - uint8_t bTxMode: 1; //!< \brief 0: Start synth in RX mode
- //!< 1: Start synth in TX mode - uint8_t refFreq: 6; //!< Reserved - } synthConf; - uint8_t __dummy0; //!< Reserved, always write 0 - uint8_t __dummy1; //!< Reserved - uint8_t __dummy2; //!< Reserved - uint16_t __dummy3; //!< Reserved + uint16_t commandNo; //!< The command ID number 0x0803 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t frequency; //!< The frequency in MHz to tune to + uint16_t fractFreq; //!< Fractional part of the frequency to tune to + struct + { + uint8_t bTxMode : 1; //!< \brief 0: Start synth in RX mode
+ //!< 1: Start synth in TX mode + uint8_t refFreq : 6; //!< Reserved + } synthConf; + uint8_t __dummy0; //!< Reserved, always write 0 + uint8_t __dummy1; //!< Reserved + uint8_t __dummy2; //!< Reserved + uint16_t __dummy3; //!< Reserved } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_FS_OFF //! @{ -#define CMD_FS_OFF 0x0804 +#define CMD_FS_OFF 0x0804 //! Command for Turning off Frequency Synthesizer struct __RFC_STRUCT rfc_CMD_FS_OFF_s { - uint16_t commandNo; //!< The command ID number 0x0804 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; + uint16_t commandNo; //!< The command ID number 0x0804 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_RX_TEST //! @{ -#define CMD_RX_TEST 0x0807 +#define CMD_RX_TEST 0x0807 //! Receiver Test Command struct __RFC_STRUCT rfc_CMD_RX_TEST_s { - uint16_t commandNo; //!< The command ID number 0x0807 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bEnaFifo: 1; //!< \brief 0: Do not enable FIFO in modem, so that received data is not available
- //!< 1: Enable FIFO in modem -- the data must be read out by the application - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bNoSync: 1; //!< \brief 0: Run sync search as normal for the configured mode
- //!< 1: Write correlation thresholds to the maximum value to avoid getting sync - } config; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - uint32_t syncWord; //!< Sync word to use for receiver - ratmr_t endTime; //!< Time to end the operation + uint16_t commandNo; //!< The command ID number 0x0807 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bEnaFifo : 1; //!< \brief 0: Do not enable FIFO in modem, so that received data is not available
+ //!< 1: Enable FIFO in modem -- the data must be read out by the application + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bNoSync : 1; //!< \brief 0: Run sync search as normal for the configured mode
+ //!< 1: Write correlation thresholds to the maximum value to avoid getting sync + } config; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + uint32_t syncWord; //!< Sync word to use for receiver + ratmr_t endTime; //!< Time to end the operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_TX_TEST //! @{ -#define CMD_TX_TEST 0x0808 +#define CMD_TX_TEST 0x0808 //! Transmitter Test Command struct __RFC_STRUCT rfc_CMD_TX_TEST_s { - uint16_t commandNo; //!< The command ID number 0x0808 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bUseCw: 1; //!< \brief 0: Send modulated signal
- //!< 1: Send continuous wave - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t whitenMode: 2; //!< \brief 0: No whitening
- //!< 1: Default whitening
- //!< 2: PRBS-15
- //!< 3: PRBS-32 - } config; - uint8_t __dummy0; - uint16_t txWord; //!< Value to send to the modem before whitening - uint8_t __dummy1; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - uint32_t syncWord; //!< Sync word to use for transmitter - ratmr_t endTime; //!< Time to end the operation + uint16_t commandNo; //!< The command ID number 0x0808 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bUseCw : 1; //!< \brief 0: Send modulated signal
+ //!< 1: Send continuous wave + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t whitenMode : 2; //!< \brief 0: No whitening
+ //!< 1: Default whitening
+ //!< 2: PRBS-15
+ //!< 3: PRBS-32 + } config; + uint8_t __dummy0; + uint16_t txWord; //!< Value to send to the modem before whitening + uint8_t __dummy1; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + uint32_t syncWord; //!< Sync word to use for transmitter + ratmr_t endTime; //!< Time to end the operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SYNC_STOP_RAT //! @{ -#define CMD_SYNC_STOP_RAT 0x0809 +#define CMD_SYNC_STOP_RAT 0x0809 //! Synchronize and Stop Radio Timer Command struct __RFC_STRUCT rfc_CMD_SYNC_STOP_RAT_s { - uint16_t commandNo; //!< The command ID number 0x0809 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t __dummy0; - ratmr_t rat0; //!< \brief The returned RAT timer value corresponding to the value the RAT would have had when the - //!< RTC was zero + uint16_t commandNo; //!< The command ID number 0x0809 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + ratmr_t rat0; //!< \brief The returned RAT timer value corresponding to the value the RAT would have had when the + //!< RTC was zero } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SYNC_START_RAT //! @{ -#define CMD_SYNC_START_RAT 0x080A +#define CMD_SYNC_START_RAT 0x080A //! Synchrously Start Radio Timer Command struct __RFC_STRUCT rfc_CMD_SYNC_START_RAT_s { - uint16_t commandNo; //!< The command ID number 0x080A - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t __dummy0; - ratmr_t rat0; //!< \brief The desired RAT timer value corresponding to the value the RAT would have had when the - //!< RTC was zero. This parameter is returned by CMD_SYNC_STOP_RAT + uint16_t commandNo; //!< The command ID number 0x080A + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + ratmr_t rat0; //!< \brief The desired RAT timer value corresponding to the value the RAT would have had when the + //!< RTC was zero. This parameter is returned by CMD_SYNC_STOP_RAT } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_COUNT //! @{ -#define CMD_COUNT 0x080B +#define CMD_COUNT 0x080B //! Counter Command struct __RFC_STRUCT rfc_CMD_COUNT_s { - uint16_t commandNo; //!< The command ID number 0x080B - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation - //!< differs if the result is zero + uint16_t commandNo; //!< The command ID number 0x080B + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation + //!< differs if the result is zero } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_FS_POWERUP //! @{ -#define CMD_FS_POWERUP 0x080C +#define CMD_FS_POWERUP 0x080C //! Power up Frequency Syntheszier Command struct __RFC_STRUCT rfc_CMD_FS_POWERUP_s { - uint16_t commandNo; //!< The command ID number 0x080C - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t __dummy0; - uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override. If NULL, no override is used. + uint16_t commandNo; //!< The command ID number 0x080C + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override. If NULL, no override is used. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_FS_POWERDOWN //! @{ -#define CMD_FS_POWERDOWN 0x080D +#define CMD_FS_POWERDOWN 0x080D //! Power down Frequency Syntheszier Command struct __RFC_STRUCT rfc_CMD_FS_POWERDOWN_s { - uint16_t commandNo; //!< The command ID number 0x080D - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; + uint16_t commandNo; //!< The command ID number 0x080D + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SCH_IMM //! @{ -#define CMD_SCH_IMM 0x0810 +#define CMD_SCH_IMM 0x0810 //! Run Immidiate Command as Radio Operation Command struct __RFC_STRUCT rfc_CMD_SCH_IMM_s { - uint16_t commandNo; //!< The command ID number 0x0810 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t __dummy0; - uint32_t cmdrVal; //!< Value as would be written to CMDR - uint32_t cmdstaVal; //!< Value as would be returned in CMDSTA + uint16_t commandNo; //!< The command ID number 0x0810 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t __dummy0; + uint32_t cmdrVal; //!< Value as would be written to CMDR + uint32_t cmdstaVal; //!< Value as would be returned in CMDSTA } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_COUNT_BRANCH //! @{ -#define CMD_COUNT_BRANCH 0x0812 +#define CMD_COUNT_BRANCH 0x0812 //! Counter Command with Branch of Command Chain struct __RFC_STRUCT rfc_CMD_COUNT_BRANCH_s { - uint16_t commandNo; //!< The command ID number 0x0812 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation - //!< differs if the result is zero - rfc_radioOp_t* pNextOpIfOk; //!< Pointer to next operation if counter did not expire + uint16_t commandNo; //!< The command ID number 0x0812 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation + //!< differs if the result is zero + rfc_radioOp_t* pNextOpIfOk; //!< Pointer to next operation if counter did not expire } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PATTERN_CHECK //! @{ -#define CMD_PATTERN_CHECK 0x0813 +#define CMD_PATTERN_CHECK 0x0813 //! Command for Checking a Value in Memory aginst a Pattern struct __RFC_STRUCT rfc_CMD_PATTERN_CHECK_s { - uint16_t commandNo; //!< The command ID number 0x0813 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint16_t operation: 2; //!< \brief Operation to perform
- //!< 0: True if value == compareVal
- //!< 1: True if value < compareVal
- //!< 2: True if value > compareVal
- //!< 3: Reserved - uint16_t bByteRev: 1; //!< \brief If 1, interchange the four bytes of the value, so that they are read - //!< most-significant-byte-first. - uint16_t bBitRev: 1; //!< If 1, perform bit reversal of the value - uint16_t signExtend: 5; //!< \brief 0: Treat value and compareVal as unsigned
- //!< 1--31: Treat value and compareVal as signed, where the value - //!< gives the number of the most significant bit in the signed number. - uint16_t bRxVal: 1; //!< \brief 0: Use pValue as a pointer
- //!< 1: Use pValue as a signed offset to the start of the last - //!< committed RX entry element - } patternOpt; //!< Options for comparison - rfc_radioOp_t* pNextOpIfOk; //!< Pointer to next operation if comparison result was true - uint8_t* pValue; //!< Pointer to read from, or offset from last RX entry if patternOpt.bRxVal == 1 - uint32_t mask; //!< Bit mask to apply before comparison - uint32_t compareVal; //!< Value to compare to + uint16_t commandNo; //!< The command ID number 0x0813 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint16_t operation : 2; //!< \brief Operation to perform
+ //!< 0: True if value == compareVal
+ //!< 1: True if value < compareVal
+ //!< 2: True if value > compareVal
+ //!< 3: Reserved + uint16_t bByteRev : 1; //!< \brief If 1, interchange the four bytes of the value, so that they are read + //!< most-significant-byte-first. + uint16_t bBitRev : 1; //!< If 1, perform bit reversal of the value + uint16_t signExtend : 5; //!< \brief 0: Treat value and compareVal as unsigned
+ //!< 1--31: Treat value and compareVal as signed, where the value + //!< gives the number of the most significant bit in the signed number. + uint16_t bRxVal : 1; //!< \brief 0: Use pValue as a pointer
+ //!< 1: Use pValue as a signed offset to the start of the last + //!< committed RX entry element + } patternOpt; //!< Options for comparison + rfc_radioOp_t* pNextOpIfOk; //!< Pointer to next operation if comparison result was true + uint8_t* pValue; //!< Pointer to read from, or offset from last RX entry if patternOpt.bRxVal == 1 + uint32_t mask; //!< Bit mask to apply before comparison + uint32_t compareVal; //!< Value to compare to } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_ABORT //! @{ -#define CMD_ABORT 0x0401 +#define CMD_ABORT 0x0401 //! Abort Running Radio Operation Command struct __RFC_STRUCT rfc_CMD_ABORT_s { - uint16_t commandNo; //!< The command ID number 0x0401 + uint16_t commandNo; //!< The command ID number 0x0401 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_STOP //! @{ -#define CMD_STOP 0x0402 +#define CMD_STOP 0x0402 //! Stop Running Radio Operation Command Gracefully struct __RFC_STRUCT rfc_CMD_STOP_s { - uint16_t commandNo; //!< The command ID number 0x0402 + uint16_t commandNo; //!< The command ID number 0x0402 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_GET_RSSI //! @{ -#define CMD_GET_RSSI 0x0403 +#define CMD_GET_RSSI 0x0403 //! Read RSSI Command struct __RFC_STRUCT rfc_CMD_GET_RSSI_s { - uint16_t commandNo; //!< The command ID number 0x0403 + uint16_t commandNo; //!< The command ID number 0x0403 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_UPDATE_RADIO_SETUP //! @{ -#define CMD_UPDATE_RADIO_SETUP 0x0001 +#define CMD_UPDATE_RADIO_SETUP 0x0001 //! Update Radio Settings Command struct __RFC_STRUCT rfc_CMD_UPDATE_RADIO_SETUP_s { - uint16_t commandNo; //!< The command ID number 0x0001 - uint16_t __dummy0; - uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override + uint16_t commandNo; //!< The command ID number 0x0001 + uint16_t __dummy0; + uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_TRIGGER //! @{ -#define CMD_TRIGGER 0x0404 +#define CMD_TRIGGER 0x0404 //! Generate Command Trigger struct __RFC_STRUCT rfc_CMD_TRIGGER_s { - uint16_t commandNo; //!< The command ID number 0x0404 - uint8_t triggerNo; //!< Command trigger number + uint16_t commandNo; //!< The command ID number 0x0404 + uint8_t triggerNo; //!< Command trigger number } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_GET_FW_INFO //! @{ -#define CMD_GET_FW_INFO 0x0002 +#define CMD_GET_FW_INFO 0x0002 //! Request Information on the RF Core ROM Firmware struct __RFC_STRUCT rfc_CMD_GET_FW_INFO_s { - uint16_t commandNo; //!< The command ID number 0x0002 - uint16_t versionNo; //!< Firmware version number - uint16_t startOffset; //!< The start of free RAM - uint16_t freeRamSz; //!< The size of free RAM - uint16_t availRatCh; //!< Bitmap of available RAT channels + uint16_t commandNo; //!< The command ID number 0x0002 + uint16_t versionNo; //!< Firmware version number + uint16_t startOffset; //!< The start of free RAM + uint16_t freeRamSz; //!< The size of free RAM + uint16_t availRatCh; //!< Bitmap of available RAT channels } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_START_RAT //! @{ -#define CMD_START_RAT 0x0405 +#define CMD_START_RAT 0x0405 //! Asynchronously Start Radio Timer Command struct __RFC_STRUCT rfc_CMD_START_RAT_s { - uint16_t commandNo; //!< The command ID number 0x0405 + uint16_t commandNo; //!< The command ID number 0x0405 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PING //! @{ -#define CMD_PING 0x0406 +#define CMD_PING 0x0406 //! Respond with Command ACK Only struct __RFC_STRUCT rfc_CMD_PING_s { - uint16_t commandNo; //!< The command ID number 0x0406 + uint16_t commandNo; //!< The command ID number 0x0406 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_READ_RFREG //! @{ -#define CMD_READ_RFREG 0x0601 +#define CMD_READ_RFREG 0x0601 //! Read RF Core Hardware Register struct __RFC_STRUCT rfc_CMD_READ_RFREG_s { - uint16_t commandNo; //!< The command ID number 0x0601 - uint16_t address; //!< The offset from the start of the RF core HW register bank (0x40040000) - uint32_t value; //!< Returned value of the register + uint16_t commandNo; //!< The command ID number 0x0601 + uint16_t address; //!< The offset from the start of the RF core HW register bank (0x40040000) + uint32_t value; //!< Returned value of the register } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_ADD_DATA_ENTRY //! @{ -#define CMD_ADD_DATA_ENTRY 0x0005 +#define CMD_ADD_DATA_ENTRY 0x0005 //! Add Data Entry to Queue struct __RFC_STRUCT rfc_CMD_ADD_DATA_ENTRY_s { - uint16_t commandNo; //!< The command ID number 0x0005 - uint16_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to the queue structure to which the entry will be added - uint8_t* pEntry; //!< Pointer to the entry + uint16_t commandNo; //!< The command ID number 0x0005 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to which the entry will be added + uint8_t* pEntry; //!< Pointer to the entry } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_REMOVE_DATA_ENTRY //! @{ -#define CMD_REMOVE_DATA_ENTRY 0x0006 +#define CMD_REMOVE_DATA_ENTRY 0x0006 //! Remove First Data Entry from Queue struct __RFC_STRUCT rfc_CMD_REMOVE_DATA_ENTRY_s { - uint16_t commandNo; //!< The command ID number 0x0006 - uint16_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to the queue structure from which the entry will be removed - uint8_t* pEntry; //!< Pointer to the entry that was removed + uint16_t commandNo; //!< The command ID number 0x0006 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure from which the entry will be removed + uint8_t* pEntry; //!< Pointer to the entry that was removed } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_FLUSH_QUEUE //! @{ -#define CMD_FLUSH_QUEUE 0x0007 +#define CMD_FLUSH_QUEUE 0x0007 //! Flush Data Queue struct __RFC_STRUCT rfc_CMD_FLUSH_QUEUE_s { - uint16_t commandNo; //!< The command ID number 0x0007 - uint16_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed - uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed + uint16_t commandNo; //!< The command ID number 0x0007 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed + uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_CLEAR_RX //! @{ -#define CMD_CLEAR_RX 0x0008 +#define CMD_CLEAR_RX 0x0008 //! Clear all RX Queue Entries struct __RFC_STRUCT rfc_CMD_CLEAR_RX_s { - uint16_t commandNo; //!< The command ID number 0x0008 - uint16_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to the queue structure to be cleared + uint16_t commandNo; //!< The command ID number 0x0008 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to be cleared } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_REMOVE_PENDING_ENTRIES //! @{ -#define CMD_REMOVE_PENDING_ENTRIES 0x0009 +#define CMD_REMOVE_PENDING_ENTRIES 0x0009 //! Remove Pending Entries from Queue struct __RFC_STRUCT rfc_CMD_REMOVE_PENDING_ENTRIES_s { - uint16_t commandNo; //!< The command ID number 0x0009 - uint16_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed - uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed + uint16_t commandNo; //!< The command ID number 0x0009 + uint16_t __dummy0; + dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed + uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SET_RAT_CMP //! @{ -#define CMD_SET_RAT_CMP 0x000A +#define CMD_SET_RAT_CMP 0x000A //! Set Radio Timer Channel in Compare Mode struct __RFC_STRUCT rfc_CMD_SET_RAT_CMP_s { - uint16_t commandNo; //!< The command ID number 0x000A - uint8_t ratCh; //!< The radio timer channel number - uint8_t __dummy0; - ratmr_t compareTime; //!< The time at which the compare occurs + uint16_t commandNo; //!< The command ID number 0x000A + uint8_t ratCh; //!< The radio timer channel number + uint8_t __dummy0; + ratmr_t compareTime; //!< The time at which the compare occurs } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SET_RAT_CPT //! @{ -#define CMD_SET_RAT_CPT 0x0603 +#define CMD_SET_RAT_CPT 0x0603 //! Set Radio Timer Channel in Capture Mode struct __RFC_STRUCT rfc_CMD_SET_RAT_CPT_s { - uint16_t commandNo; //!< The command ID number 0x0603 - struct - { - uint16_t : 3; - uint16_t inputSrc: 5; //!< Input source indicator - uint16_t ratCh: 4; //!< The radio timer channel number - uint16_t bRepeated: 1; //!< \brief 0: Single capture mode
- //!< 1: Repeated capture mode - uint16_t inputMode: 2; //!< \brief Input mode:
- //!< 0: Capture on rising edge
- //!< 1: Capture on falling edge
- //!< 2: Capture on both edges
- //!< 3: Reserved - } config; + uint16_t commandNo; //!< The command ID number 0x0603 + struct + { + uint16_t : 3; + uint16_t inputSrc : 5; //!< Input source indicator + uint16_t ratCh : 4; //!< The radio timer channel number + uint16_t bRepeated : 1; //!< \brief 0: Single capture mode
+ //!< 1: Repeated capture mode + uint16_t inputMode : 2; //!< \brief Input mode:
+ //!< 0: Capture on rising edge
+ //!< 1: Capture on falling edge
+ //!< 2: Capture on both edges
+ //!< 3: Reserved + } config; } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_DISABLE_RAT_CH //! @{ -#define CMD_DISABLE_RAT_CH 0x0408 +#define CMD_DISABLE_RAT_CH 0x0408 //! Disable Radio Timer Channel struct __RFC_STRUCT rfc_CMD_DISABLE_RAT_CH_s { - uint16_t commandNo; //!< The command ID number 0x0408 - uint8_t ratCh; //!< The radio timer channel number + uint16_t commandNo; //!< The command ID number 0x0408 + uint8_t ratCh; //!< The radio timer channel number } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SET_RAT_OUTPUT //! @{ -#define CMD_SET_RAT_OUTPUT 0x0604 +#define CMD_SET_RAT_OUTPUT 0x0604 //! Set Radio Timer Output to a Specified Mode struct __RFC_STRUCT rfc_CMD_SET_RAT_OUTPUT_s { - uint16_t commandNo; //!< The command ID number 0x0604 - struct - { - uint16_t : 2; - uint16_t outputSel: 3; //!< Output event indicator - uint16_t outputMode: 3; //!< \brief 0: Set output line low as default; and pulse on event. Duration of pulse is one RF Core clock period (ca. 41.67 ns).
- //!< 1: Set output line high on event
- //!< 2: Set output line low on event
- //!< 3: Toggle (invert) output line state on event
- //!< 4: Immediately set output line to low (does not change upon event)
- //!< 5: Immediately set output line to high (does not change upon event)
- //!< Others: Reserved - uint16_t ratCh: 4; //!< The radio timer channel number - } config; + uint16_t commandNo; //!< The command ID number 0x0604 + struct + { + uint16_t : 2; + uint16_t outputSel : 3; //!< Output event indicator + uint16_t outputMode : 3; //!< \brief 0: Set output line low as default; and pulse on event. Duration of pulse is one RF Core clock period (ca. 41.67 ns).
+ //!< 1: Set output line high on event
+ //!< 2: Set output line low on event
+ //!< 3: Toggle (invert) output line state on event
+ //!< 4: Immediately set output line to low (does not change upon event)
+ //!< 5: Immediately set output line to high (does not change upon event)
+ //!< Others: Reserved + uint16_t ratCh : 4; //!< The radio timer channel number + } config; } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_ARM_RAT_CH //! @{ -#define CMD_ARM_RAT_CH 0x0409 +#define CMD_ARM_RAT_CH 0x0409 //! Arm Radio Timer Channel struct __RFC_STRUCT rfc_CMD_ARM_RAT_CH_s { - uint16_t commandNo; //!< The command ID number 0x0409 - uint8_t ratCh; //!< The radio timer channel number + uint16_t commandNo; //!< The command ID number 0x0409 + uint8_t ratCh; //!< The radio timer channel number } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_DISARM_RAT_CH //! @{ -#define CMD_DISARM_RAT_CH 0x040A +#define CMD_DISARM_RAT_CH 0x040A //! Disarm Radio Timer Channel struct __RFC_STRUCT rfc_CMD_DISARM_RAT_CH_s { - uint16_t commandNo; //!< The command ID number 0x040A - uint8_t ratCh; //!< The radio timer channel number + uint16_t commandNo; //!< The command ID number 0x040A + uint8_t ratCh; //!< The radio timer channel number } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_SET_TX_POWER //! @{ -#define CMD_SET_TX_POWER 0x0010 +#define CMD_SET_TX_POWER 0x0010 //! Set Transmit Power struct __RFC_STRUCT rfc_CMD_SET_TX_POWER_s { - uint16_t commandNo; //!< The command ID number 0x0010 - uint16_t txPower; //!< \brief New TX power setting - //!< Bits 0--5: IB - //!< Value to write to the PA power control field at 25 °C - //!< Bits 6--7: GC - //!< Value to write to the gain control of the 1st stage of the PA - //!< Bits 8--15: tempCoeff - //!< Temperature coefficient for IB. 0: No temperature compensation + uint16_t commandNo; //!< The command ID number 0x0010 + uint16_t txPower; //!< \brief New TX power setting + //!< Bits 0--5: IB + //!< Value to write to the PA power control field at 25 °C + //!< Bits 6--7: GC + //!< Value to write to the gain control of the 1st stage of the PA + //!< Bits 8--15: tempCoeff + //!< Temperature coefficient for IB. 0: No temperature compensation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_UPDATE_FS //! @{ -#define CMD_UPDATE_FS 0x0011 +#define CMD_UPDATE_FS 0x0011 //! Set New Synthesizer Frequency without Recalibration struct __RFC_STRUCT rfc_CMD_UPDATE_FS_s { - uint16_t commandNo; //!< The command ID number 0x0011 - uint16_t __dummy0; - uint32_t __dummy1; - uint32_t __dummy2; - uint16_t __dummy3; - uint16_t frequency; //!< The frequency in MHz to tune to - uint16_t fractFreq; //!< Fractional part of the frequency to tune to + uint16_t commandNo; //!< The command ID number 0x0011 + uint16_t __dummy0; + uint32_t __dummy1; + uint32_t __dummy2; + uint16_t __dummy3; + uint16_t frequency; //!< The frequency in MHz to tune to + uint16_t fractFreq; //!< Fractional part of the frequency to tune to } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_BUS_REQUEST //! @{ -#define CMD_BUS_REQUEST 0x040E +#define CMD_BUS_REQUEST 0x040E //! Request System Bus to be Availbale struct __RFC_STRUCT rfc_CMD_BUS_REQUEST_s { - uint16_t commandNo; //!< The command ID number 0x040E - uint8_t bSysBusNeeded; //!< \brief 0: System bus may sleep
- //!< 1: System bus access needed + uint16_t commandNo; //!< The command ID number 0x040E + uint8_t bSysBusNeeded; //!< \brief 0: System bus may sleep
+ //!< 1: System bus access needed } __RFC_STRUCT_ATTR; //! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_data_entry.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_data_entry.h index 137b7b4..d525f3d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_data_entry.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_data_entry.h @@ -1,56 +1,56 @@ /****************************************************************************** -* Filename: rf_data_entry.h -* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) -* Revision: 18052 -* -* Description: Definition of API for data exchange -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_data_entry.h + * Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) + * Revision: 18052 + * + * Description: Definition of API for data exchange + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __DATA_ENTRY_H #define __DATA_ENTRY_H #ifndef __RFC_STRUCT - #define __RFC_STRUCT +#define __RFC_STRUCT #endif #ifndef __RFC_STRUCT_ATTR - #if defined(__GNUC__) - #define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) - #elif defined(__TI_ARM__) - #define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) - #else - #define __RFC_STRUCT_ATTR - #endif +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__((aligned(4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__((__packed__, aligned(4))) +#else +#define __RFC_STRUCT_ATTR +#endif #endif //! \addtogroup rfc @@ -59,8 +59,8 @@ //! \addtogroup data_entry //! @{ -#include #include "rf_mailbox.h" +#include typedef struct __RFC_STRUCT rfc_dataEntry_s rfc_dataEntry_t; typedef struct __RFC_STRUCT rfc_dataEntryGeneral_s rfc_dataEntryGeneral_t; @@ -72,25 +72,25 @@ typedef struct __RFC_STRUCT rfc_dataEntryPartial_s rfc_dataEntryPartial_t; //! @{ struct __RFC_STRUCT rfc_dataEntry_s { - uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry - uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to - struct - { - uint8_t type: 2; //!< \brief Type of data entry structure
- //!< 0: General data entry
- //!< 1: Multi-element Rx entry
- //!< 2: Pointer entry
- //!< 3: Partial read Rx entry - uint8_t lenSz: 2; //!< \brief Size of length word in start of each Rx entry element
- //!< 0: No length indicator
- //!< 1: One byte length indicator
- //!< 2: Two bytes length indicator
- //!< 3: Reserved - uint8_t irqIntv: 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated - //!< by the radio CPU (0: 16 bytes) - } config; - uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
- //!< For other entries: Number of bytes following this length field + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct + { + uint8_t type : 2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz : 2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv : 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field } __RFC_STRUCT_ATTR; //! @} @@ -101,26 +101,26 @@ struct __RFC_STRUCT rfc_dataEntry_s struct __RFC_STRUCT rfc_dataEntryGeneral_s { - uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry - uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to - struct - { - uint8_t type: 2; //!< \brief Type of data entry structure
- //!< 0: General data entry
- //!< 1: Multi-element Rx entry
- //!< 2: Pointer entry
- //!< 3: Partial read Rx entry - uint8_t lenSz: 2; //!< \brief Size of length word in start of each Rx entry element
- //!< 0: No length indicator
- //!< 1: One byte length indicator
- //!< 2: Two bytes length indicator
- //!< 3: Reserved - uint8_t irqIntv: 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated - //!< by the radio CPU (0: 16 bytes) - } config; - uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
- //!< For other entries: Number of bytes following this length field - uint8_t data; //!< First byte of the data array to be received or transmitted + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct + { + uint8_t type : 2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz : 2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv : 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + uint8_t data; //!< First byte of the data array to be received or transmitted } __RFC_STRUCT_ATTR; //! @} @@ -131,28 +131,28 @@ struct __RFC_STRUCT rfc_dataEntryGeneral_s struct __RFC_STRUCT rfc_dataEntryMulti_s { - uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry - uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to - struct - { - uint8_t type: 2; //!< \brief Type of data entry structure
- //!< 0: General data entry
- //!< 1: Multi-element Rx entry
- //!< 2: Pointer entry
- //!< 3: Partial read Rx entry - uint8_t lenSz: 2; //!< \brief Size of length word in start of each Rx entry element
- //!< 0: No length indicator
- //!< 1: One byte length indicator
- //!< 2: Two bytes length indicator
- //!< 3: Reserved - uint8_t irqIntv: 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated - //!< by the radio CPU (0: 16 bytes) - } config; - uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
- //!< For other entries: Number of bytes following this length field - uint16_t numElements; //!< Number of entry elements committed in the entry - uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU - uint8_t rxData; //!< First byte of the data array of received data entry elements + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct + { + uint8_t type : 2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz : 2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv : 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + uint16_t numElements; //!< Number of entry elements committed in the entry + uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU + uint8_t rxData; //!< First byte of the data array of received data entry elements } __RFC_STRUCT_ATTR; //! @} @@ -163,26 +163,26 @@ struct __RFC_STRUCT rfc_dataEntryMulti_s struct __RFC_STRUCT rfc_dataEntryPointer_s { - uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry - uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to - struct - { - uint8_t type: 2; //!< \brief Type of data entry structure
- //!< 0: General data entry
- //!< 1: Multi-element Rx entry
- //!< 2: Pointer entry
- //!< 3: Partial read Rx entry - uint8_t lenSz: 2; //!< \brief Size of length word in start of each Rx entry element
- //!< 0: No length indicator
- //!< 1: One byte length indicator
- //!< 2: Two bytes length indicator
- //!< 3: Reserved - uint8_t irqIntv: 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated - //!< by the radio CPU (0: 16 bytes) - } config; - uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
- //!< For other entries: Number of bytes following this length field - uint8_t* pData; //!< Pointer to data buffer of data to be received ro transmitted + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct + { + uint8_t type : 2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz : 2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv : 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + uint8_t* pData; //!< Pointer to data buffer of data to be received ro transmitted } __RFC_STRUCT_ATTR; //! @} @@ -193,34 +193,34 @@ struct __RFC_STRUCT rfc_dataEntryPointer_s struct __RFC_STRUCT rfc_dataEntryPartial_s { - uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry - uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to - struct - { - uint8_t type: 2; //!< \brief Type of data entry structure
- //!< 0: General data entry
- //!< 1: Multi-element Rx entry
- //!< 2: Pointer entry
- //!< 3: Partial read Rx entry - uint8_t lenSz: 2; //!< \brief Size of length word in start of each Rx entry element
- //!< 0: No length indicator
- //!< 1: One byte length indicator
- //!< 2: Two bytes length indicator
- //!< 3: Reserved - uint8_t irqIntv: 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated - //!< by the radio CPU (0: 16 bytes) - } config; - uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
- //!< For other entries: Number of bytes following this length field - struct - { - uint16_t numElements: 13; //!< Number of entry elements committed in the entry - uint16_t bEntryOpen: 1; //!< 1 if the entry contains an element that is still open for appending data - uint16_t bFirstCont: 1; //!< 1 if the first element is a continuation of the last packet from the previous entry - uint16_t bLastCont: 1; //!< 1 if the packet in the last element continues in the next entry - } pktStatus; - uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU - uint8_t rxData; //!< First byte of the data array of received data entry elements + uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry + uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to + struct + { + uint8_t type : 2; //!< \brief Type of data entry structure
+ //!< 0: General data entry
+ //!< 1: Multi-element Rx entry
+ //!< 2: Pointer entry
+ //!< 3: Partial read Rx entry + uint8_t lenSz : 2; //!< \brief Size of length word in start of each Rx entry element
+ //!< 0: No length indicator
+ //!< 1: One byte length indicator
+ //!< 2: Two bytes length indicator
+ //!< 3: Reserved + uint8_t irqIntv : 4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated + //!< by the radio CPU (0: 16 bytes) + } config; + uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
+ //!< For other entries: Number of bytes following this length field + struct + { + uint16_t numElements : 13; //!< Number of entry elements committed in the entry + uint16_t bEntryOpen : 1; //!< 1 if the entry contains an element that is still open for appending data + uint16_t bFirstCont : 1; //!< 1 if the first element is a continuation of the last packet from the previous entry + uint16_t bLastCont : 1; //!< 1 if the packet in the last element continues in the next entry + } pktStatus; + uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU + uint8_t rxData; //!< First byte of the data array of received data entry elements } __RFC_STRUCT_ATTR; //! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ieee_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ieee_cmd.h index 254541b..6678be0 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ieee_cmd.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ieee_cmd.h @@ -1,56 +1,56 @@ /****************************************************************************** -* Filename: rf_ieee_cmd.h -* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) -* Revision: 18052 -* -* Description: CC26x0 API for IEEE 802.15.4 commands -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_ieee_cmd.h + * Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) + * Revision: 18052 + * + * Description: CC26x0 API for IEEE 802.15.4 commands + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __IEEE_CMD_H #define __IEEE_CMD_H #ifndef __RFC_STRUCT - #define __RFC_STRUCT +#define __RFC_STRUCT #endif #ifndef __RFC_STRUCT_ATTR - #if defined(__GNUC__) - #define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) - #elif defined(__TI_ARM__) - #define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) - #else - #define __RFC_STRUCT_ATTR - #endif +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__((aligned(4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__((__packed__, aligned(4))) +#else +#define __RFC_STRUCT_ATTR +#endif #endif //! \addtogroup rfc @@ -59,9 +59,9 @@ //! \addtogroup ieee_cmd //! @{ -#include -#include "rf_mailbox.h" #include "rf_common_cmd.h" +#include "rf_mailbox.h" +#include typedef struct __RFC_STRUCT rfc_CMD_IEEE_RX_s rfc_CMD_IEEE_RX_t; typedef struct __RFC_STRUCT rfc_CMD_IEEE_ED_SCAN_s rfc_CMD_IEEE_ED_SCAN_t; @@ -81,537 +81,537 @@ typedef struct __RFC_STRUCT rfc_ieeeRxCorrCrc_s rfc_ieeeRxCorrCrc_t; //! \addtogroup CMD_IEEE_RX //! @{ -#define CMD_IEEE_RX 0x2801 +#define CMD_IEEE_RX 0x2801 //! IEEE 802.15.4 Receive Command struct __RFC_STRUCT rfc_CMD_IEEE_RX_s { - uint16_t commandNo; //!< The command ID number 0x2801 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to tune to in the start of the operation
- //!< 0: Use existing channel
- //!< 11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 × (channel - 11)) MHz
- //!< 60--207: Frequency is (2300 + channel) MHz
- //!< Others: Reserved - struct - { - uint8_t bAutoFlushCrc: 1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushIgn: 1; //!< If 1, automatically remove packets that can be ignored according to frame filtering from Rx queue - uint8_t bIncludePhyHdr: 1; //!< If 1, include the received PHY header field in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendCorrCrc: 1; //!< If 1, append a correlation value and CRC result byte to the packet in the Rx queue - uint8_t bAppendSrcInd: 1; //!< If 1, append an index from the source matching algorithm - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; - dataQueue_t* pRxQ; //!< Pointer to receive queue - rfc_ieeeRxOutput_t* pOutput; //!< Pointer to output structure (NULL: Do not store results) - struct - { - uint16_t frameFiltEn: 1; //!< \brief 0: Disable frame filtering
- //!< 1: Enable frame filtering - uint16_t frameFiltStop: 1; //!< \brief 0: Receive all packets to the end
- //!< 1: Stop receiving frame once frame filtering has caused the frame to be rejected. - uint16_t autoAckEn: 1; //!< \brief 0: Disable auto ACK
- //!< 1: Enable auto ACK. - uint16_t slottedAckEn: 1; //!< \brief 0: Non-slotted ACK
- //!< 1: Slotted ACK. - uint16_t autoPendEn: 1; //!< \brief 0: Auto-pend disabled
- //!< 1: Auto-pend enabled - uint16_t defaultPend: 1; //!< The value of the pending data bit in auto ACK packets that are not subject to auto-pend - uint16_t bPendDataReqOnly: 1; //!< \brief 0: Use auto-pend for any packet
- //!< 1: Use auto-pend for data request packets only - uint16_t bPanCoord: 1; //!< \brief 0: Device is not PAN coordinator
- //!< 1: Device is PAN coordinator - uint16_t maxFrameVersion: 2; //!< Reject frames where the frame version field in the FCF is greater than this value - uint16_t fcfReservedMask: 3; //!< Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero - uint16_t modifyFtFilter: 2; //!< \brief Treatment of MSB of frame type field before frame-type filtering:
- //!< 0: No modification
- //!< 1: Invert MSB
- //!< 2: Set MSB to 0
- //!< 3: Set MSB to 1 - uint16_t bStrictLenFilter: 1; //!< \brief 0: Accept acknowledgement frames of any length >= 5
- //!< 1: Accept only acknowledgement frames of length 5 - } frameFiltOpt; //!< Frame filtering options - struct - { - uint8_t bAcceptFt0Beacon: 1; //!< \brief Treatment of frames with frame type 000 (beacon):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt1Data: 1; //!< \brief Treatment of frames with frame type 001 (data):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt2Ack: 1; //!< \brief Treatment of frames with frame type 010 (ACK):
- //!< 0: Reject, unless running ACK receive command
- //!< 1: Always accept - uint8_t bAcceptFt3MacCmd: 1; //!< \brief Treatment of frames with frame type 011 (MAC command):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt4Reserved: 1; //!< \brief Treatment of frames with frame type 100 (reserved):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt5Reserved: 1; //!< \brief Treatment of frames with frame type 101 (reserved):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt6Reserved: 1; //!< \brief Treatment of frames with frame type 110 (reserved):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt7Reserved: 1; //!< \brief Treatment of frames with frame type 111 (reserved):
- //!< 0: Reject
- //!< 1: Accept - } frameTypes; //!< Frame types to receive in frame filtering - struct - { - uint8_t ccaEnEnergy: 1; //!< Enable energy scan as CCA source - uint8_t ccaEnCorr: 1; //!< Enable correlator based carrier sense as CCA source - uint8_t ccaEnSync: 1; //!< Enable sync found based carrier sense as CCA source - uint8_t ccaCorrOp: 1; //!< \brief Operator to use between energy based and correlator based CCA
- //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
- //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy - uint8_t ccaSyncOp: 1; //!< \brief Operator to use between sync found based CCA and the others
- //!< 0: Always report busy channel if ccaSync is busy
- //!< 1: Always report idle channel if ccaSync is idle - uint8_t ccaCorrThr: 2; //!< Threshold for number of correlation peaks in correlator based carrier sense - } ccaOpt; //!< CCA options - int8_t ccaRssiThr; //!< RSSI threshold for CCA - uint8_t __dummy0; - uint8_t numExtEntries; //!< Number of extended address entries - uint8_t numShortEntries; //!< Number of short address entries - uint32_t* pExtEntryList; //!< Pointer to list of extended address entries - uint32_t* pShortEntryList; //!< Pointer to list of short address entries - uint64_t localExtAddr; //!< The extended address of the local device - uint16_t localShortAddr; //!< The short address of the local device - uint16_t localPanID; //!< The PAN ID of the local device - uint16_t __dummy1; - uint8_t __dummy2; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the Rx operation - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the Rx - //!< operation + uint16_t commandNo; //!< The command ID number 0x2801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to tune to in the start of the operation
+ //!< 0: Use existing channel
+ //!< 11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 × (channel - 11)) MHz
+ //!< 60--207: Frequency is (2300 + channel) MHz
+ //!< Others: Reserved + struct + { + uint8_t bAutoFlushCrc : 1; //!< If 1, automatically remove packets with CRC error from Rx queue + uint8_t bAutoFlushIgn : 1; //!< If 1, automatically remove packets that can be ignored according to frame filtering from Rx queue + uint8_t bIncludePhyHdr : 1; //!< If 1, include the received PHY header field in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the Rx queue + uint8_t bAppendCorrCrc : 1; //!< If 1, append a correlation value and CRC result byte to the packet in the Rx queue + uint8_t bAppendSrcInd : 1; //!< If 1, append an index from the source matching algorithm + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the Rx queue + } rxConfig; + dataQueue_t* pRxQ; //!< Pointer to receive queue + rfc_ieeeRxOutput_t* pOutput; //!< Pointer to output structure (NULL: Do not store results) + struct + { + uint16_t frameFiltEn : 1; //!< \brief 0: Disable frame filtering
+ //!< 1: Enable frame filtering + uint16_t frameFiltStop : 1; //!< \brief 0: Receive all packets to the end
+ //!< 1: Stop receiving frame once frame filtering has caused the frame to be rejected. + uint16_t autoAckEn : 1; //!< \brief 0: Disable auto ACK
+ //!< 1: Enable auto ACK. + uint16_t slottedAckEn : 1; //!< \brief 0: Non-slotted ACK
+ //!< 1: Slotted ACK. + uint16_t autoPendEn : 1; //!< \brief 0: Auto-pend disabled
+ //!< 1: Auto-pend enabled + uint16_t defaultPend : 1; //!< The value of the pending data bit in auto ACK packets that are not subject to auto-pend + uint16_t bPendDataReqOnly : 1; //!< \brief 0: Use auto-pend for any packet
+ //!< 1: Use auto-pend for data request packets only + uint16_t bPanCoord : 1; //!< \brief 0: Device is not PAN coordinator
+ //!< 1: Device is PAN coordinator + uint16_t maxFrameVersion : 2; //!< Reject frames where the frame version field in the FCF is greater than this value + uint16_t fcfReservedMask : 3; //!< Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero + uint16_t modifyFtFilter : 2; //!< \brief Treatment of MSB of frame type field before frame-type filtering:
+ //!< 0: No modification
+ //!< 1: Invert MSB
+ //!< 2: Set MSB to 0
+ //!< 3: Set MSB to 1 + uint16_t bStrictLenFilter : 1; //!< \brief 0: Accept acknowledgement frames of any length >= 5
+ //!< 1: Accept only acknowledgement frames of length 5 + } frameFiltOpt; //!< Frame filtering options + struct + { + uint8_t bAcceptFt0Beacon : 1; //!< \brief Treatment of frames with frame type 000 (beacon):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt1Data : 1; //!< \brief Treatment of frames with frame type 001 (data):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt2Ack : 1; //!< \brief Treatment of frames with frame type 010 (ACK):
+ //!< 0: Reject, unless running ACK receive command
+ //!< 1: Always accept + uint8_t bAcceptFt3MacCmd : 1; //!< \brief Treatment of frames with frame type 011 (MAC command):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt4Reserved : 1; //!< \brief Treatment of frames with frame type 100 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt5Reserved : 1; //!< \brief Treatment of frames with frame type 101 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt6Reserved : 1; //!< \brief Treatment of frames with frame type 110 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt7Reserved : 1; //!< \brief Treatment of frames with frame type 111 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + } frameTypes; //!< Frame types to receive in frame filtering + struct + { + uint8_t ccaEnEnergy : 1; //!< Enable energy scan as CCA source + uint8_t ccaEnCorr : 1; //!< Enable correlator based carrier sense as CCA source + uint8_t ccaEnSync : 1; //!< Enable sync found based carrier sense as CCA source + uint8_t ccaCorrOp : 1; //!< \brief Operator to use between energy based and correlator based CCA
+ //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
+ //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy + uint8_t ccaSyncOp : 1; //!< \brief Operator to use between sync found based CCA and the others
+ //!< 0: Always report busy channel if ccaSync is busy
+ //!< 1: Always report idle channel if ccaSync is idle + uint8_t ccaCorrThr : 2; //!< Threshold for number of correlation peaks in correlator based carrier sense + } ccaOpt; //!< CCA options + int8_t ccaRssiThr; //!< RSSI threshold for CCA + uint8_t __dummy0; + uint8_t numExtEntries; //!< Number of extended address entries + uint8_t numShortEntries; //!< Number of short address entries + uint32_t* pExtEntryList; //!< Pointer to list of extended address entries + uint32_t* pShortEntryList; //!< Pointer to list of short address entries + uint64_t localExtAddr; //!< The extended address of the local device + uint16_t localShortAddr; //!< The short address of the local device + uint16_t localPanID; //!< The PAN ID of the local device + uint16_t __dummy1; + uint8_t __dummy2; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Rx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the Rx + //!< operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_ED_SCAN //! @{ -#define CMD_IEEE_ED_SCAN 0x2802 +#define CMD_IEEE_ED_SCAN 0x2802 //! IEEE 802.15.4 Energy Detect Scan Command struct __RFC_STRUCT rfc_CMD_IEEE_ED_SCAN_s { - uint16_t commandNo; //!< The command ID number 0x2802 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to tune to in the start of the operation
- //!< 0: Use existing channel
- //!< 11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 × (channel - 11)) MHz
- //!< 60--207: Frequency is (2300 + channel) MHz
- //!< Others: Reserved - struct - { - uint8_t ccaEnEnergy: 1; //!< Enable energy scan as CCA source - uint8_t ccaEnCorr: 1; //!< Enable correlator based carrier sense as CCA source - uint8_t ccaEnSync: 1; //!< Enable sync found based carrier sense as CCA source - uint8_t ccaCorrOp: 1; //!< \brief Operator to use between energy based and correlator based CCA
- //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
- //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy - uint8_t ccaSyncOp: 1; //!< \brief Operator to use between sync found based CCA and the others
- //!< 0: Always report busy channel if ccaSync is busy
- //!< 1: Always report idle channel if ccaSync is idle - uint8_t ccaCorrThr: 2; //!< Threshold for number of correlation peaks in correlator based carrier sense - } ccaOpt; //!< CCA options - int8_t ccaRssiThr; //!< RSSI threshold for CCA - uint8_t __dummy0; - int8_t maxRssi; //!< The maximum RSSI recorded during the ED scan - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the Rx operation - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the Rx - //!< operation + uint16_t commandNo; //!< The command ID number 0x2802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t channel; //!< \brief Channel to tune to in the start of the operation
+ //!< 0: Use existing channel
+ //!< 11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 × (channel - 11)) MHz
+ //!< 60--207: Frequency is (2300 + channel) MHz
+ //!< Others: Reserved + struct + { + uint8_t ccaEnEnergy : 1; //!< Enable energy scan as CCA source + uint8_t ccaEnCorr : 1; //!< Enable correlator based carrier sense as CCA source + uint8_t ccaEnSync : 1; //!< Enable sync found based carrier sense as CCA source + uint8_t ccaCorrOp : 1; //!< \brief Operator to use between energy based and correlator based CCA
+ //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
+ //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy + uint8_t ccaSyncOp : 1; //!< \brief Operator to use between sync found based CCA and the others
+ //!< 0: Always report busy channel if ccaSync is busy
+ //!< 1: Always report idle channel if ccaSync is idle + uint8_t ccaCorrThr : 2; //!< Threshold for number of correlation peaks in correlator based carrier sense + } ccaOpt; //!< CCA options + int8_t ccaRssiThr; //!< RSSI threshold for CCA + uint8_t __dummy0; + int8_t maxRssi; //!< The maximum RSSI recorded during the ED scan + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the Rx operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the Rx + //!< operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_TX //! @{ -#define CMD_IEEE_TX 0x2C01 +#define CMD_IEEE_TX 0x2C01 //! IEEE 802.15.4 Transmit Command struct __RFC_STRUCT rfc_CMD_IEEE_TX_s { - uint16_t commandNo; //!< The command ID number 0x2C01 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bIncludePhyHdr: 1; //!< \brief 0: Find PHY header automatically
- //!< 1: Insert PHY header from the buffer - uint8_t bIncludeCrc: 1; //!< \brief 0: Append automatically calculated CRC
- //!< 1: Insert FCS (CRC) from the buffer - uint8_t : 1; - uint8_t payloadLenMsb: 5; //!< \brief Most significant bits of payload length. Should only be non-zero to create long - //!< non-standard packets for test purposes - } txOpt; - uint8_t payloadLen; //!< Number of bytes in the payload - uint8_t* pPayload; //!< Pointer to payload buffer of size payloadLen - ratmr_t timeStamp; //!< Time stamp of transmitted frame + uint16_t commandNo; //!< The command ID number 0x2C01 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bIncludePhyHdr : 1; //!< \brief 0: Find PHY header automatically
+ //!< 1: Insert PHY header from the buffer + uint8_t bIncludeCrc : 1; //!< \brief 0: Append automatically calculated CRC
+ //!< 1: Insert FCS (CRC) from the buffer + uint8_t : 1; + uint8_t payloadLenMsb : 5; //!< \brief Most significant bits of payload length. Should only be non-zero to create long + //!< non-standard packets for test purposes + } txOpt; + uint8_t payloadLen; //!< Number of bytes in the payload + uint8_t* pPayload; //!< Pointer to payload buffer of size payloadLen + ratmr_t timeStamp; //!< Time stamp of transmitted frame } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_CSMA //! @{ -#define CMD_IEEE_CSMA 0x2C02 +#define CMD_IEEE_CSMA 0x2C02 //! IEEE 802.15.4 CSMA-CA Command struct __RFC_STRUCT rfc_CMD_IEEE_CSMA_s { - uint16_t commandNo; //!< The command ID number 0x2C02 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t randomState; //!< The state of the pseudo-random generator - uint8_t macMaxBE; //!< The IEEE 802.15.4 MAC parameter macMaxBE - uint8_t macMaxCSMABackoffs; //!< The IEEE 802.15.4 MAC parameter macMaxCSMABackoffs - struct - { - uint8_t initCW: 5; //!< The initialization value for the CW parameter - uint8_t bSlotted: 1; //!< \brief 0: non-slotted CSMA
- //!< 1: slotted CSMA - uint8_t rxOffMode: 2; //!< \brief 0: RX stays on during CSMA backoffs
- //!< 1: The CSMA-CA algorithm will suspend the receiver if no frame is being received
- //!< 2: The CSMA-CA algorithm will suspend the receiver if no frame is being received, - //!< or after finishing it (including auto ACK) otherwise
- //!< 3: The CSMA-CA algorithm will suspend the receiver immediately during back-offs - } csmaConfig; - uint8_t NB; //!< The NB parameter from the IEEE 802.15.4 CSMA-CA algorithm - uint8_t BE; //!< The BE parameter from the IEEE 802.15.4 CSMA-CA algorithm - uint8_t remainingPeriods; //!< The number of remaining periods from a paused backoff countdown - int8_t lastRssi; //!< RSSI measured at the last CCA operation - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the CSMA-CA operation - ratmr_t lastTimeStamp; //!< Time of the last CCA operation - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< CSMA-CA operation + uint16_t commandNo; //!< The command ID number 0x2C02 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint16_t randomState; //!< The state of the pseudo-random generator + uint8_t macMaxBE; //!< The IEEE 802.15.4 MAC parameter macMaxBE + uint8_t macMaxCSMABackoffs; //!< The IEEE 802.15.4 MAC parameter macMaxCSMABackoffs + struct + { + uint8_t initCW : 5; //!< The initialization value for the CW parameter + uint8_t bSlotted : 1; //!< \brief 0: non-slotted CSMA
+ //!< 1: slotted CSMA + uint8_t rxOffMode : 2; //!< \brief 0: RX stays on during CSMA backoffs
+ //!< 1: The CSMA-CA algorithm will suspend the receiver if no frame is being received
+ //!< 2: The CSMA-CA algorithm will suspend the receiver if no frame is being received, + //!< or after finishing it (including auto ACK) otherwise
+ //!< 3: The CSMA-CA algorithm will suspend the receiver immediately during back-offs + } csmaConfig; + uint8_t NB; //!< The NB parameter from the IEEE 802.15.4 CSMA-CA algorithm + uint8_t BE; //!< The BE parameter from the IEEE 802.15.4 CSMA-CA algorithm + uint8_t remainingPeriods; //!< The number of remaining periods from a paused backoff countdown + int8_t lastRssi; //!< RSSI measured at the last CCA operation + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to end the CSMA-CA operation + ratmr_t lastTimeStamp; //!< Time of the last CCA operation + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the + //!< CSMA-CA operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_RX_ACK //! @{ -#define CMD_IEEE_RX_ACK 0x2C03 +#define CMD_IEEE_RX_ACK 0x2C03 //! IEEE 802.15.4 Receive Acknowledgement Command struct __RFC_STRUCT rfc_CMD_IEEE_RX_ACK_s { - uint16_t commandNo; //!< The command ID number 0x2C03 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t seqNo; //!< Sequence number to expect - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to give up acknowledgement reception - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to give up - //!< acknowledgement reception + uint16_t commandNo; //!< The command ID number 0x2C03 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + uint8_t seqNo; //!< Sequence number to expect + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger that causes the device to give up acknowledgement reception + ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to give up + //!< acknowledgement reception } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_ABORT_BG //! @{ -#define CMD_IEEE_ABORT_BG 0x2C04 +#define CMD_IEEE_ABORT_BG 0x2C04 //! IEEE 802.15.4 Abort Background Level Command struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_BG_s { - uint16_t commandNo; //!< The command ID number 0x2C04 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; + uint16_t commandNo; //!< The command ID number 0x2C04 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_MOD_CCA //! @{ -#define CMD_IEEE_MOD_CCA 0x2001 +#define CMD_IEEE_MOD_CCA 0x2001 //! IEEE 802.15.4 Modify CCA Parameter Command struct __RFC_STRUCT rfc_CMD_IEEE_MOD_CCA_s { - uint16_t commandNo; //!< The command ID number 0x2001 - struct - { - uint8_t ccaEnEnergy: 1; //!< Enable energy scan as CCA source - uint8_t ccaEnCorr: 1; //!< Enable correlator based carrier sense as CCA source - uint8_t ccaEnSync: 1; //!< Enable sync found based carrier sense as CCA source - uint8_t ccaCorrOp: 1; //!< \brief Operator to use between energy based and correlator based CCA
- //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
- //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy - uint8_t ccaSyncOp: 1; //!< \brief Operator to use between sync found based CCA and the others
- //!< 0: Always report busy channel if ccaSync is busy
- //!< 1: Always report idle channel if ccaSync is idle - uint8_t ccaCorrThr: 2; //!< Threshold for number of correlation peaks in correlator based carrier sense - } newCcaOpt; //!< New value of ccaOpt for the running background level operation - int8_t newCcaRssiThr; //!< New value of ccaRssiThr for the running background level operation + uint16_t commandNo; //!< The command ID number 0x2001 + struct + { + uint8_t ccaEnEnergy : 1; //!< Enable energy scan as CCA source + uint8_t ccaEnCorr : 1; //!< Enable correlator based carrier sense as CCA source + uint8_t ccaEnSync : 1; //!< Enable sync found based carrier sense as CCA source + uint8_t ccaCorrOp : 1; //!< \brief Operator to use between energy based and correlator based CCA
+ //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
+ //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy + uint8_t ccaSyncOp : 1; //!< \brief Operator to use between sync found based CCA and the others
+ //!< 0: Always report busy channel if ccaSync is busy
+ //!< 1: Always report idle channel if ccaSync is idle + uint8_t ccaCorrThr : 2; //!< Threshold for number of correlation peaks in correlator based carrier sense + } newCcaOpt; //!< New value of ccaOpt for the running background level operation + int8_t newCcaRssiThr; //!< New value of ccaRssiThr for the running background level operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_MOD_FILT //! @{ -#define CMD_IEEE_MOD_FILT 0x2002 +#define CMD_IEEE_MOD_FILT 0x2002 //! IEEE 802.15.4 Modify Frame Filtering Parameter Command struct __RFC_STRUCT rfc_CMD_IEEE_MOD_FILT_s { - uint16_t commandNo; //!< The command ID number 0x2002 - struct - { - uint16_t frameFiltEn: 1; //!< \brief 0: Disable frame filtering
- //!< 1: Enable frame filtering - uint16_t frameFiltStop: 1; //!< \brief 0: Receive all packets to the end
- //!< 1: Stop receiving frame once frame filtering has caused the frame to be rejected. - uint16_t autoAckEn: 1; //!< \brief 0: Disable auto ACK
- //!< 1: Enable auto ACK. - uint16_t slottedAckEn: 1; //!< \brief 0: Non-slotted ACK
- //!< 1: Slotted ACK. - uint16_t autoPendEn: 1; //!< \brief 0: Auto-pend disabled
- //!< 1: Auto-pend enabled - uint16_t defaultPend: 1; //!< The value of the pending data bit in auto ACK packets that are not subject to auto-pend - uint16_t bPendDataReqOnly: 1; //!< \brief 0: Use auto-pend for any packet
- //!< 1: Use auto-pend for data request packets only - uint16_t bPanCoord: 1; //!< \brief 0: Device is not PAN coordinator
- //!< 1: Device is PAN coordinator - uint16_t maxFrameVersion: 2; //!< Reject frames where the frame version field in the FCF is greater than this value - uint16_t fcfReservedMask: 3; //!< Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero - uint16_t modifyFtFilter: 2; //!< \brief Treatment of MSB of frame type field before frame-type filtering:
- //!< 0: No modification
- //!< 1: Invert MSB
- //!< 2: Set MSB to 0
- //!< 3: Set MSB to 1 - uint16_t bStrictLenFilter: 1; //!< \brief 0: Accept acknowledgement frames of any length >= 5
- //!< 1: Accept only acknowledgement frames of length 5 - } newFrameFiltOpt; //!< New value of frameFiltOpt for the running background level operation - struct - { - uint8_t bAcceptFt0Beacon: 1; //!< \brief Treatment of frames with frame type 000 (beacon):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt1Data: 1; //!< \brief Treatment of frames with frame type 001 (data):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt2Ack: 1; //!< \brief Treatment of frames with frame type 010 (ACK):
- //!< 0: Reject, unless running ACK receive command
- //!< 1: Always accept - uint8_t bAcceptFt3MacCmd: 1; //!< \brief Treatment of frames with frame type 011 (MAC command):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt4Reserved: 1; //!< \brief Treatment of frames with frame type 100 (reserved):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt5Reserved: 1; //!< \brief Treatment of frames with frame type 101 (reserved):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt6Reserved: 1; //!< \brief Treatment of frames with frame type 110 (reserved):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt7Reserved: 1; //!< \brief Treatment of frames with frame type 111 (reserved):
- //!< 0: Reject
- //!< 1: Accept - } newFrameTypes; //!< New value of frameTypes for the running background level operation + uint16_t commandNo; //!< The command ID number 0x2002 + struct + { + uint16_t frameFiltEn : 1; //!< \brief 0: Disable frame filtering
+ //!< 1: Enable frame filtering + uint16_t frameFiltStop : 1; //!< \brief 0: Receive all packets to the end
+ //!< 1: Stop receiving frame once frame filtering has caused the frame to be rejected. + uint16_t autoAckEn : 1; //!< \brief 0: Disable auto ACK
+ //!< 1: Enable auto ACK. + uint16_t slottedAckEn : 1; //!< \brief 0: Non-slotted ACK
+ //!< 1: Slotted ACK. + uint16_t autoPendEn : 1; //!< \brief 0: Auto-pend disabled
+ //!< 1: Auto-pend enabled + uint16_t defaultPend : 1; //!< The value of the pending data bit in auto ACK packets that are not subject to auto-pend + uint16_t bPendDataReqOnly : 1; //!< \brief 0: Use auto-pend for any packet
+ //!< 1: Use auto-pend for data request packets only + uint16_t bPanCoord : 1; //!< \brief 0: Device is not PAN coordinator
+ //!< 1: Device is PAN coordinator + uint16_t maxFrameVersion : 2; //!< Reject frames where the frame version field in the FCF is greater than this value + uint16_t fcfReservedMask : 3; //!< Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero + uint16_t modifyFtFilter : 2; //!< \brief Treatment of MSB of frame type field before frame-type filtering:
+ //!< 0: No modification
+ //!< 1: Invert MSB
+ //!< 2: Set MSB to 0
+ //!< 3: Set MSB to 1 + uint16_t bStrictLenFilter : 1; //!< \brief 0: Accept acknowledgement frames of any length >= 5
+ //!< 1: Accept only acknowledgement frames of length 5 + } newFrameFiltOpt; //!< New value of frameFiltOpt for the running background level operation + struct + { + uint8_t bAcceptFt0Beacon : 1; //!< \brief Treatment of frames with frame type 000 (beacon):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt1Data : 1; //!< \brief Treatment of frames with frame type 001 (data):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt2Ack : 1; //!< \brief Treatment of frames with frame type 010 (ACK):
+ //!< 0: Reject, unless running ACK receive command
+ //!< 1: Always accept + uint8_t bAcceptFt3MacCmd : 1; //!< \brief Treatment of frames with frame type 011 (MAC command):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt4Reserved : 1; //!< \brief Treatment of frames with frame type 100 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt5Reserved : 1; //!< \brief Treatment of frames with frame type 101 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt6Reserved : 1; //!< \brief Treatment of frames with frame type 110 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + uint8_t bAcceptFt7Reserved : 1; //!< \brief Treatment of frames with frame type 111 (reserved):
+ //!< 0: Reject
+ //!< 1: Accept + } newFrameTypes; //!< New value of frameTypes for the running background level operation } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_MOD_SRC_MATCH //! @{ -#define CMD_IEEE_MOD_SRC_MATCH 0x2003 +#define CMD_IEEE_MOD_SRC_MATCH 0x2003 //! IEEE 802.15.4 Enable/Disable Source Matching Entry Command struct __RFC_STRUCT rfc_CMD_IEEE_MOD_SRC_MATCH_s { - uint16_t commandNo; //!< The command ID number 0x2003 - struct - { - uint8_t bEnable: 1; //!< \brief 0: Disable entry
- //!< 1: Enable entry - uint8_t srcPend: 1; //!< New value of the pending bit for the entry - uint8_t entryType: 1; //!< \brief 0: Short address
- //!< 1: Extended address - } options; - uint8_t entryNo; //!< Index of entry to enable or disable + uint16_t commandNo; //!< The command ID number 0x2003 + struct + { + uint8_t bEnable : 1; //!< \brief 0: Disable entry
+ //!< 1: Enable entry + uint8_t srcPend : 1; //!< New value of the pending bit for the entry + uint8_t entryType : 1; //!< \brief 0: Short address
+ //!< 1: Extended address + } options; + uint8_t entryNo; //!< Index of entry to enable or disable } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_ABORT_FG //! @{ -#define CMD_IEEE_ABORT_FG 0x2401 +#define CMD_IEEE_ABORT_FG 0x2401 //! IEEE 802.15.4 Abort Foreground Level Command struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_FG_s { - uint16_t commandNo; //!< The command ID number 0x2401 + uint16_t commandNo; //!< The command ID number 0x2401 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_STOP_FG //! @{ -#define CMD_IEEE_STOP_FG 0x2402 +#define CMD_IEEE_STOP_FG 0x2402 //! IEEE 802.15.4 Gracefully Stop Foreground Level Command struct __RFC_STRUCT rfc_CMD_IEEE_STOP_FG_s { - uint16_t commandNo; //!< The command ID number 0x2402 + uint16_t commandNo; //!< The command ID number 0x2402 } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_IEEE_CCA_REQ //! @{ -#define CMD_IEEE_CCA_REQ 0x2403 +#define CMD_IEEE_CCA_REQ 0x2403 //! IEEE 802.15.4 CCA and RSSI Information Request Command struct __RFC_STRUCT rfc_CMD_IEEE_CCA_REQ_s { - uint16_t commandNo; //!< The command ID number 0x2403 - int8_t currentRssi; //!< The RSSI currently observed on the channel - int8_t maxRssi; //!< The maximum RSSI observed on the channel since Rx was started - struct - { - uint8_t ccaState: 2; //!< \brief Value of the current CCA state
- //!< 0: Idle
- //!< 1: Busy
- //!< 2: Invalid - uint8_t ccaEnergy: 2; //!< \brief Value of the current energy detect CCA state
- //!< 0: Idle
- //!< 1: Busy
- //!< 2: Invalid - uint8_t ccaCorr: 2; //!< \brief Value of the current correlator based carrier sense CCA state
- //!< 0: Idle
- //!< 1: Busy
- //!< 2: Invalid - uint8_t ccaSync: 1; //!< \brief Value of the current sync found based carrier sense CCA state
- //!< 0: Idle
- //!< 1: Busy - } ccaInfo; + uint16_t commandNo; //!< The command ID number 0x2403 + int8_t currentRssi; //!< The RSSI currently observed on the channel + int8_t maxRssi; //!< The maximum RSSI observed on the channel since Rx was started + struct + { + uint8_t ccaState : 2; //!< \brief Value of the current CCA state
+ //!< 0: Idle
+ //!< 1: Busy
+ //!< 2: Invalid + uint8_t ccaEnergy : 2; //!< \brief Value of the current energy detect CCA state
+ //!< 0: Idle
+ //!< 1: Busy
+ //!< 2: Invalid + uint8_t ccaCorr : 2; //!< \brief Value of the current correlator based carrier sense CCA state
+ //!< 0: Idle
+ //!< 1: Busy
+ //!< 2: Invalid + uint8_t ccaSync : 1; //!< \brief Value of the current sync found based carrier sense CCA state
+ //!< 0: Idle
+ //!< 1: Busy + } ccaInfo; } __RFC_STRUCT_ATTR; //! @} @@ -622,19 +622,19 @@ struct __RFC_STRUCT rfc_CMD_IEEE_CCA_REQ_s struct __RFC_STRUCT rfc_ieeeRxOutput_s { - uint8_t nTxAck; //!< Total number of transmitted ACK frames - uint8_t nRxBeacon; //!< Number of received beacon frames - uint8_t nRxData; //!< Number of received data frames - uint8_t nRxAck; //!< Number of received acknowledgement frames - uint8_t nRxMacCmd; //!< Number of received MAC command frames - uint8_t nRxReserved; //!< Number of received frames with reserved frame type - uint8_t nRxNok; //!< Number of received frames with CRC error - uint8_t nRxIgnored; //!< Number of frames received that are to be ignored - uint8_t nRxBufFull; //!< Number of received frames discarded because the Rx buffer was full - int8_t lastRssi; //!< RSSI of last received frame - int8_t maxRssi; //!< Highest RSSI observed in the operation - uint8_t __dummy0; - ratmr_t beaconTimeStamp; //!< Time stamp of last received beacon frame + uint8_t nTxAck; //!< Total number of transmitted ACK frames + uint8_t nRxBeacon; //!< Number of received beacon frames + uint8_t nRxData; //!< Number of received data frames + uint8_t nRxAck; //!< Number of received acknowledgement frames + uint8_t nRxMacCmd; //!< Number of received MAC command frames + uint8_t nRxReserved; //!< Number of received frames with reserved frame type + uint8_t nRxNok; //!< Number of received frames with CRC error + uint8_t nRxIgnored; //!< Number of frames received that are to be ignored + uint8_t nRxBufFull; //!< Number of received frames discarded because the Rx buffer was full + int8_t lastRssi; //!< RSSI of last received frame + int8_t maxRssi; //!< Highest RSSI observed in the operation + uint8_t __dummy0; + ratmr_t beaconTimeStamp; //!< Time stamp of last received beacon frame } __RFC_STRUCT_ATTR; //! @} @@ -645,8 +645,8 @@ struct __RFC_STRUCT rfc_ieeeRxOutput_s struct __RFC_STRUCT rfc_shortAddrEntry_s { - uint16_t shortAddr; //!< Short address - uint16_t panId; //!< PAN ID + uint16_t shortAddr; //!< Short address + uint16_t panId; //!< PAN ID } __RFC_STRUCT_ATTR; //! @} @@ -657,12 +657,12 @@ struct __RFC_STRUCT rfc_shortAddrEntry_s struct __RFC_STRUCT rfc_ieeeRxCorrCrc_s { - struct - { - uint8_t corr: 6; //!< The correlation value - uint8_t bIgnore: 1; //!< 1 if the packet should be rejected by frame filtering, 0 otherwise - uint8_t bCrcErr: 1; //!< 1 if the packet was received with CRC error, 0 otherwise - } status; + struct + { + uint8_t corr : 6; //!< The correlation value + uint8_t bIgnore : 1; //!< 1 if the packet should be rejected by frame filtering, 0 otherwise + uint8_t bCrcErr : 1; //!< 1 if the packet was received with CRC error, 0 otherwise + } status; } __RFC_STRUCT_ATTR; //! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ieee_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ieee_mailbox.h index 8c9682a..96efcde 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ieee_mailbox.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_ieee_mailbox.h @@ -1,73 +1,72 @@ /****************************************************************************** -* Filename: rf_ieee_mailbox.h -* Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) -* Revision: 18032 -* -* Description: Definitions for IEEE 802.15.4 interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_ieee_mailbox.h + * Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) + * Revision: 18032 + * + * Description: Definitions for IEEE 802.15.4 interface + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _IEEE_MAILBOX_H #define _IEEE_MAILBOX_H #include "rf_mailbox.h" - /// \name Radio operation status ///@{ /// \name Operation not finished ///@{ -#define IEEE_SUSPENDED 0x2001 ///< Operation suspended +#define IEEE_SUSPENDED 0x2001 ///< Operation suspended ///@} /// \name Operation finished normally ///@{ -#define IEEE_DONE_OK 0x2400 ///< Operation ended normally -#define IEEE_DONE_BUSY 0x2401 ///< CSMA-CA operation ended with failure -#define IEEE_DONE_STOPPED 0x2402 ///< Operation stopped after stop command -#define IEEE_DONE_ACK 0x2403 ///< ACK packet received with pending data bit cleared -#define IEEE_DONE_ACKPEND 0x2404 ///< ACK packet received with pending data bit set -#define IEEE_DONE_TIMEOUT 0x2405 ///< Operation ended due to timeout -#define IEEE_DONE_BGEND 0x2406 ///< FG operation ended because necessary background level +#define IEEE_DONE_OK 0x2400 ///< Operation ended normally +#define IEEE_DONE_BUSY 0x2401 ///< CSMA-CA operation ended with failure +#define IEEE_DONE_STOPPED 0x2402 ///< Operation stopped after stop command +#define IEEE_DONE_ACK 0x2403 ///< ACK packet received with pending data bit cleared +#define IEEE_DONE_ACKPEND 0x2404 ///< ACK packet received with pending data bit set +#define IEEE_DONE_TIMEOUT 0x2405 ///< Operation ended due to timeout +#define IEEE_DONE_BGEND 0x2406 ///< FG operation ended because necessary background level ///< operation ended -#define IEEE_DONE_ABORT 0x2407 ///< Operation aborted by command +#define IEEE_DONE_ABORT 0x2407 ///< Operation aborted by command ///@} /// \name Operation finished with error ///@{ -#define IEEE_ERROR_PAR 0x2800 ///< Illegal parameter -#define IEEE_ERROR_NO_SETUP 0x2801 ///< Operation using Rx or Tx attemted when not in 15.4 mode -#define IEEE_ERROR_NO_FS 0x2802 ///< Operation using Rx or Tx attemted without frequency synth configured -#define IEEE_ERROR_SYNTH_PROG 0x2803 ///< Synthesizer programming failed to complete on time -#define IEEE_ERROR_RXOVF 0x2804 ///< Receiver overflowed during operation -#define IEEE_ERROR_TXUNF 0x2805 ///< Transmitter underflowed during operation +#define IEEE_ERROR_PAR 0x2800 ///< Illegal parameter +#define IEEE_ERROR_NO_SETUP 0x2801 ///< Operation using Rx or Tx attemted when not in 15.4 mode +#define IEEE_ERROR_NO_FS 0x2802 ///< Operation using Rx or Tx attemted without frequency synth configured +#define IEEE_ERROR_SYNTH_PROG 0x2803 ///< Synthesizer programming failed to complete on time +#define IEEE_ERROR_RXOVF 0x2804 ///< Receiver overflowed during operation +#define IEEE_ERROR_TXUNF 0x2805 ///< Transmitter underflowed during operation ///@} ///@} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_mailbox.h index 5d6009b..e28567e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_mailbox.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_mailbox.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_mailbox.h -* Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) -* Revision: 18032 -* -* Description: Definitions for interface between system and radio CPU -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_mailbox.h + * Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) + * Revision: 18032 + * + * Description: Definitions for interface between system and radio CPU + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _MAILBOX_H #define _MAILBOX_H @@ -42,124 +42,114 @@ #include #include - /// \name RF mode values /// Defines used to indicate mode of operation to radio core. ///@{ -#define RF_MODE_BLE 0x01 -#define RF_MODE_IEEE_15_4 0x02 -#define RF_MODE_PROPRIETARY_2_4 0x03 -#define RF_MODE_PROPRIETARY RF_MODE_PROPRIETARY_2_4 -#define RF_MODE_MULTIPLE 0x05 +#define RF_MODE_BLE 0x01 +#define RF_MODE_IEEE_15_4 0x02 +#define RF_MODE_PROPRIETARY_2_4 0x03 +#define RF_MODE_PROPRIETARY RF_MODE_PROPRIETARY_2_4 +#define RF_MODE_MULTIPLE 0x05 ///@} - /// Type definition for RAT typedef uint32_t ratmr_t; - - /// Type definition for a data queue typedef struct { - uint8_t* pCurrEntry; ///< Pointer to the data queue entry to be used, NULL for an empty queue - uint8_t* pLastEntry; ///< Pointer to the last entry in the queue, NULL for a circular queue + uint8_t* pCurrEntry; ///< Pointer to the data queue entry to be used, NULL for an empty queue + uint8_t* pLastEntry; ///< Pointer to the last entry in the queue, NULL for a circular queue } dataQueue_t; - - /// \name CPE interrupt definitions /// Interrupt masks for the CPE interrupt in RDBELL. ///@{ -#define IRQN_COMMAND_DONE 0 ///< Radio operation command finished -#define IRQN_LAST_COMMAND_DONE 1 ///< Last radio operation command in a chain finished -#define IRQN_FG_COMMAND_DONE 2 ///< FG level Radio operation command finished -#define IRQN_LAST_FG_COMMAND_DONE 3 ///< Last FG level radio operation command in a chain finished -#define IRQN_TX_DONE 4 ///< Packet transmitted -#define IRQN_TX_ACK 5 ///< ACK packet transmitted -#define IRQN_TX_CTRL 6 ///< Control packet transmitted -#define IRQN_TX_CTRL_ACK 7 ///< Acknowledgement received on a transmitted control packet -#define IRQN_TX_CTRL_ACK_ACK 8 ///< Acknowledgement received on a transmitted control packet, and acknowledgement transmitted for that packet -#define IRQN_TX_RETRANS 9 ///< Packet retransmitted -#define IRQN_TX_ENTRY_DONE 10 ///< Tx queue data entry state changed to Finished -#define IRQN_TX_BUFFER_CHANGED 11 ///< A buffer change is complete -#define IRQN_RX_OK 16 ///< Packet received with CRC OK, payload, and not to be ignored -#define IRQN_RX_NOK 17 ///< Packet received with CRC error -#define IRQN_RX_IGNORED 18 ///< Packet received with CRC OK, but to be ignored -#define IRQN_RX_EMPTY 19 ///< Packet received with CRC OK, not to be ignored, no payload -#define IRQN_RX_CTRL 20 ///< Control packet received with CRC OK, not to be ignored -#define IRQN_RX_CTRL_ACK 21 ///< Control packet received with CRC OK, not to be ignored, then ACK sent -#define IRQN_RX_BUF_FULL 22 ///< Packet received that did not fit in the Rx queue -#define IRQN_RX_ENTRY_DONE 23 ///< Rx queue data entry changing state to Finished -#define IRQN_RX_DATA_WRITTEN 24 ///< Data written to partial read Rx buffer -#define IRQN_RX_N_DATA_WRITTEN 25 ///< Specified number of bytes written to partial read Rx buffer -#define IRQN_RX_ABORTED 26 ///< Packet reception stopped before packet was done -#define IRQN_RX_COLLISION_DETECTED 27 ///< A collision was indicated during packet reception -#define IRQN_SYNTH_NO_LOCK 28 ///< The synth has gone out of lock after calibration -#define IRQN_MODULES_UNLOCKED 29 ///< As part of the boot process, the CM0 has opened access to RF core modules and memories -#define IRQN_BOOT_DONE 30 ///< The RF core CPU boot is finished +#define IRQN_COMMAND_DONE 0 ///< Radio operation command finished +#define IRQN_LAST_COMMAND_DONE 1 ///< Last radio operation command in a chain finished +#define IRQN_FG_COMMAND_DONE 2 ///< FG level Radio operation command finished +#define IRQN_LAST_FG_COMMAND_DONE 3 ///< Last FG level radio operation command in a chain finished +#define IRQN_TX_DONE 4 ///< Packet transmitted +#define IRQN_TX_ACK 5 ///< ACK packet transmitted +#define IRQN_TX_CTRL 6 ///< Control packet transmitted +#define IRQN_TX_CTRL_ACK 7 ///< Acknowledgement received on a transmitted control packet +#define IRQN_TX_CTRL_ACK_ACK 8 ///< Acknowledgement received on a transmitted control packet, and acknowledgement transmitted for that packet +#define IRQN_TX_RETRANS 9 ///< Packet retransmitted +#define IRQN_TX_ENTRY_DONE 10 ///< Tx queue data entry state changed to Finished +#define IRQN_TX_BUFFER_CHANGED 11 ///< A buffer change is complete +#define IRQN_RX_OK 16 ///< Packet received with CRC OK, payload, and not to be ignored +#define IRQN_RX_NOK 17 ///< Packet received with CRC error +#define IRQN_RX_IGNORED 18 ///< Packet received with CRC OK, but to be ignored +#define IRQN_RX_EMPTY 19 ///< Packet received with CRC OK, not to be ignored, no payload +#define IRQN_RX_CTRL 20 ///< Control packet received with CRC OK, not to be ignored +#define IRQN_RX_CTRL_ACK 21 ///< Control packet received with CRC OK, not to be ignored, then ACK sent +#define IRQN_RX_BUF_FULL 22 ///< Packet received that did not fit in the Rx queue +#define IRQN_RX_ENTRY_DONE 23 ///< Rx queue data entry changing state to Finished +#define IRQN_RX_DATA_WRITTEN 24 ///< Data written to partial read Rx buffer +#define IRQN_RX_N_DATA_WRITTEN 25 ///< Specified number of bytes written to partial read Rx buffer +#define IRQN_RX_ABORTED 26 ///< Packet reception stopped before packet was done +#define IRQN_RX_COLLISION_DETECTED 27 ///< A collision was indicated during packet reception +#define IRQN_SYNTH_NO_LOCK 28 ///< The synth has gone out of lock after calibration +#define IRQN_MODULES_UNLOCKED 29 ///< As part of the boot process, the CM0 has opened access to RF core modules and memories +#define IRQN_BOOT_DONE 30 ///< The RF core CPU boot is finished -#define IRQN_INTERNAL_ERROR 31 ///< Internal error observed +#define IRQN_INTERNAL_ERROR 31 ///< Internal error observed -#define IRQ_COMMAND_DONE (1U << IRQN_COMMAND_DONE) -#define IRQ_LAST_COMMAND_DONE (1U << IRQN_LAST_COMMAND_DONE) -#define IRQ_FG_COMMAND_DONE (1U << IRQN_FG_COMMAND_DONE) -#define IRQ_LAST_FG_COMMAND_DONE (1U << IRQN_LAST_FG_COMMAND_DONE) +#define IRQ_COMMAND_DONE (1U << IRQN_COMMAND_DONE) +#define IRQ_LAST_COMMAND_DONE (1U << IRQN_LAST_COMMAND_DONE) +#define IRQ_FG_COMMAND_DONE (1U << IRQN_FG_COMMAND_DONE) +#define IRQ_LAST_FG_COMMAND_DONE (1U << IRQN_LAST_FG_COMMAND_DONE) -#define IRQ_TX_DONE (1U << IRQN_TX_DONE) -#define IRQ_TX_ACK (1U << IRQN_TX_ACK) -#define IRQ_TX_CTRL (1U << IRQN_TX_CTRL) -#define IRQ_TX_CTRL_ACK (1U << IRQN_TX_CTRL_ACK) -#define IRQ_TX_CTRL_ACK_ACK (1U << IRQN_TX_CTRL_ACK_ACK) -#define IRQ_TX_RETRANS (1U << IRQN_TX_RETRANS) +#define IRQ_TX_DONE (1U << IRQN_TX_DONE) +#define IRQ_TX_ACK (1U << IRQN_TX_ACK) +#define IRQ_TX_CTRL (1U << IRQN_TX_CTRL) +#define IRQ_TX_CTRL_ACK (1U << IRQN_TX_CTRL_ACK) +#define IRQ_TX_CTRL_ACK_ACK (1U << IRQN_TX_CTRL_ACK_ACK) +#define IRQ_TX_RETRANS (1U << IRQN_TX_RETRANS) -#define IRQ_TX_ENTRY_DONE (1U << IRQN_TX_ENTRY_DONE) -#define IRQ_TX_BUFFER_CHANGED (1U << IRQN_TX_BUFFER_CHANGED) +#define IRQ_TX_ENTRY_DONE (1U << IRQN_TX_ENTRY_DONE) +#define IRQ_TX_BUFFER_CHANGED (1U << IRQN_TX_BUFFER_CHANGED) -#define IRQ_RX_OK (1U << IRQN_RX_OK) -#define IRQ_RX_NOK (1U << IRQN_RX_NOK) -#define IRQ_RX_IGNORED (1U << IRQN_RX_IGNORED) -#define IRQ_RX_EMPTY (1U << IRQN_RX_EMPTY) -#define IRQ_RX_CTRL (1U << IRQN_RX_CTRL) -#define IRQ_RX_CTRL_ACK (1U << IRQN_RX_CTRL_ACK) -#define IRQ_RX_BUF_FULL (1U << IRQN_RX_BUF_FULL) -#define IRQ_RX_ENTRY_DONE (1U << IRQN_RX_ENTRY_DONE) -#define IRQ_RX_DATA_WRITTEN (1U << IRQN_RX_DATA_WRITTEN) -#define IRQ_RX_N_DATA_WRITTEN (1U << IRQN_RX_N_DATA_WRITTEN) -#define IRQ_RX_ABORTED (1U << IRQN_RX_ABORTED) -#define IRQ_RX_COLLISION_DETECTED (1U << IRQN_RX_COLLISION_DETECTED) -#define IRQ_SYNTH_NO_LOCK (1U << IRQN_SYNTH_NO_LOCK) -#define IRQ_MODULES_UNLOCKED (1U << IRQN_MODULES_UNLOCKED) -#define IRQ_BOOT_DONE (1U << IRQN_BOOT_DONE) -#define IRQ_INTERNAL_ERROR (1U << IRQN_INTERNAL_ERROR) +#define IRQ_RX_OK (1U << IRQN_RX_OK) +#define IRQ_RX_NOK (1U << IRQN_RX_NOK) +#define IRQ_RX_IGNORED (1U << IRQN_RX_IGNORED) +#define IRQ_RX_EMPTY (1U << IRQN_RX_EMPTY) +#define IRQ_RX_CTRL (1U << IRQN_RX_CTRL) +#define IRQ_RX_CTRL_ACK (1U << IRQN_RX_CTRL_ACK) +#define IRQ_RX_BUF_FULL (1U << IRQN_RX_BUF_FULL) +#define IRQ_RX_ENTRY_DONE (1U << IRQN_RX_ENTRY_DONE) +#define IRQ_RX_DATA_WRITTEN (1U << IRQN_RX_DATA_WRITTEN) +#define IRQ_RX_N_DATA_WRITTEN (1U << IRQN_RX_N_DATA_WRITTEN) +#define IRQ_RX_ABORTED (1U << IRQN_RX_ABORTED) +#define IRQ_RX_COLLISION_DETECTED (1U << IRQN_RX_COLLISION_DETECTED) +#define IRQ_SYNTH_NO_LOCK (1U << IRQN_SYNTH_NO_LOCK) +#define IRQ_MODULES_UNLOCKED (1U << IRQN_MODULES_UNLOCKED) +#define IRQ_BOOT_DONE (1U << IRQN_BOOT_DONE) +#define IRQ_INTERNAL_ERROR (1U << IRQN_INTERNAL_ERROR) ///@} - - /// \name CMDSTA values /// Values returned in result byte of CMDSTA ///@{ -#define CMDSTA_Pending 0x00 ///< The command has not yet been parsed -#define CMDSTA_Done 0x01 ///< Command successfully parsed +#define CMDSTA_Pending 0x00 ///< The command has not yet been parsed +#define CMDSTA_Done 0x01 ///< Command successfully parsed -#define CMDSTA_IllegalPointer 0x81 ///< The pointer signaled in CMDR is not valid -#define CMDSTA_UnknownCommand 0x82 ///< The command number in the command structure is unknown -#define CMDSTA_UnknownDirCommand 0x83 ///< The command number for a direct command is unknown, or the +#define CMDSTA_IllegalPointer 0x81 ///< The pointer signaled in CMDR is not valid +#define CMDSTA_UnknownCommand 0x82 ///< The command number in the command structure is unknown +#define CMDSTA_UnknownDirCommand 0x83 ///< The command number for a direct command is unknown, or the ///< command is not a direct command -#define CMDSTA_ContextError 0x85 ///< An immediate or direct command was issued in a context +#define CMDSTA_ContextError 0x85 ///< An immediate or direct command was issued in a context ///< where it is not supported -#define CMDSTA_SchedulingError 0x86 ///< A radio operation command was attempted to be scheduled +#define CMDSTA_SchedulingError 0x86 ///< A radio operation command was attempted to be scheduled ///< while another operation was already running in the RF core -#define CMDSTA_ParError 0x87 ///< There were errors in the command parameters that are parsed +#define CMDSTA_ParError 0x87 ///< There were errors in the command parameters that are parsed ///< on submission. -#define CMDSTA_QueueError 0x88 ///< An operation on a data entry queue was attempted that was +#define CMDSTA_QueueError 0x88 ///< An operation on a data entry queue was attempted that was ///< not supported by the queue in its current state -#define CMDSTA_QueueBusy 0x89 ///< An operation on a data entry was attempted while that entry +#define CMDSTA_QueueBusy 0x89 ///< An operation on a data entry was attempted while that entry ///< was busy ///@} - - /// \name Macros for sending direct commands ///@{ /// Direct command with no parameter @@ -173,8 +163,6 @@ typedef struct ///@} - - /// \name Definitions for trigger types ///@{ #define TRIG_NOW 0 ///< Triggers immediately @@ -192,63 +180,59 @@ typedef struct ///< trigger happened in the past ///@} - /// \name Definitions for conditional execution ///@{ -#define COND_ALWAYS 0 ///< Always run next command (except in case of Abort) -#define COND_NEVER 1 ///< Never run next command -#define COND_STOP_ON_FALSE 2 ///< Run next command if this command returned True, stop if it returned +#define COND_ALWAYS 0 ///< Always run next command (except in case of Abort) +#define COND_NEVER 1 ///< Never run next command +#define COND_STOP_ON_FALSE 2 ///< Run next command if this command returned True, stop if it returned ///< False -#define COND_STOP_ON_TRUE 3 ///< Stop if this command returned True, run next command if it returned +#define COND_STOP_ON_TRUE 3 ///< Stop if this command returned True, run next command if it returned ///< False -#define COND_SKIP_ON_FALSE 4 ///< Run next command if this command returned True, skip a number of +#define COND_SKIP_ON_FALSE 4 ///< Run next command if this command returned True, skip a number of ///< commands if it returned False -#define COND_SKIP_ON_TRUE 5 ///< Skip a number of commands if this command returned True, run next +#define COND_SKIP_ON_TRUE 5 ///< Skip a number of commands if this command returned True, run next ///< command if it returned False ///@} - - /// \name Radio operation status ///@{ /// \name Operation not finished ///@{ -#define IDLE 0x0000 ///< Operation not started -#define PENDING 0x0001 ///< Start of command is pending -#define ACTIVE 0x0002 ///< Running -#define SKIPPED 0x0003 ///< Operation skipped due to condition in another command +#define IDLE 0x0000 ///< Operation not started +#define PENDING 0x0001 ///< Start of command is pending +#define ACTIVE 0x0002 ///< Running +#define SKIPPED 0x0003 ///< Operation skipped due to condition in another command ///@} /// \name Operation finished normally ///@{ -#define DONE_OK 0x0400 ///< Operation ended normally -#define DONE_COUNTDOWN 0x0401 ///< Counter reached zero -#define DONE_RXERR 0x0402 ///< Operation ended with CRC error -#define DONE_TIMEOUT 0x0403 ///< Operation ended with timeout -#define DONE_STOPPED 0x0404 ///< Operation stopped after CMD_STOP command -#define DONE_ABORT 0x0405 ///< Operation aborted by CMD_ABORT command -#define DONE_FAILED 0x0406 ///< Scheduled immediate command failed +#define DONE_OK 0x0400 ///< Operation ended normally +#define DONE_COUNTDOWN 0x0401 ///< Counter reached zero +#define DONE_RXERR 0x0402 ///< Operation ended with CRC error +#define DONE_TIMEOUT 0x0403 ///< Operation ended with timeout +#define DONE_STOPPED 0x0404 ///< Operation stopped after CMD_STOP command +#define DONE_ABORT 0x0405 ///< Operation aborted by CMD_ABORT command +#define DONE_FAILED 0x0406 ///< Scheduled immediate command failed ///@} /// \name Operation finished with error ///@{ -#define ERROR_PAST_START 0x0800 ///< The start trigger occurred in the past -#define ERROR_START_TRIG 0x0801 ///< Illegal start trigger parameter -#define ERROR_CONDITION 0x0802 ///< Illegal condition for next operation -#define ERROR_PAR 0x0803 ///< Error in a command specific parameter -#define ERROR_POINTER 0x0804 ///< Invalid pointer to next operation -#define ERROR_CMDID 0x0805 ///< Next operation has a command ID that is undefined or not a radio +#define ERROR_PAST_START 0x0800 ///< The start trigger occurred in the past +#define ERROR_START_TRIG 0x0801 ///< Illegal start trigger parameter +#define ERROR_CONDITION 0x0802 ///< Illegal condition for next operation +#define ERROR_PAR 0x0803 ///< Error in a command specific parameter +#define ERROR_POINTER 0x0804 ///< Invalid pointer to next operation +#define ERROR_CMDID 0x0805 ///< Next operation has a command ID that is undefined or not a radio ///< operation command -#define ERROR_WRONG_BG 0x0806 ///< FG level command not compatible with running BG level command -#define ERROR_NO_SETUP 0x0807 ///< Operation using Rx or Tx attemted without CMD_RADIO_SETUP -#define ERROR_NO_FS 0x0808 ///< Operation using Rx or Tx attemted without frequency synth configured -#define ERROR_SYNTH_PROG 0x0809 ///< Synthesizer calibration failed -#define ERROR_TXUNF 0x080A ///< Tx underflow observed -#define ERROR_RXOVF 0x080B ///< Rx overflow observed -#define ERROR_NO_RX 0x080C ///< Attempted to access data from Rx when no such data was yet received -#define ERROR_PENDING 0x080D ///< Command submitted in the future with another command at different level pending +#define ERROR_WRONG_BG 0x0806 ///< FG level command not compatible with running BG level command +#define ERROR_NO_SETUP 0x0807 ///< Operation using Rx or Tx attemted without CMD_RADIO_SETUP +#define ERROR_NO_FS 0x0808 ///< Operation using Rx or Tx attemted without frequency synth configured +#define ERROR_SYNTH_PROG 0x0809 ///< Synthesizer calibration failed +#define ERROR_TXUNF 0x080A ///< Tx underflow observed +#define ERROR_RXOVF 0x080B ///< Rx overflow observed +#define ERROR_NO_RX 0x080C ///< Attempted to access data from Rx when no such data was yet received +#define ERROR_PENDING 0x080D ///< Command submitted in the future with another command at different level pending ///@} ///@} - /// \name Data entry types ///@{ #define DATA_ENTRY_TYPE_GEN 0 ///< General type: Tx entry or single element Rx entry @@ -257,38 +241,34 @@ typedef struct #define DATA_ENTRY_TYPE_PARTIAL 3 ///< Partial read entry type ///@ - /// \name Data entry statuses ///@{ -#define DATA_ENTRY_PENDING 0 ///< Entry not yet used -#define DATA_ENTRY_ACTIVE 1 ///< Entry in use by radio CPU -#define DATA_ENTRY_BUSY 2 ///< Entry being updated -#define DATA_ENTRY_FINISHED 3 ///< Radio CPU is finished accessing the entry -#define DATA_ENTRY_UNFINISHED 4 ///< Radio CPU is finished accessing the entry, but packet could not be finished +#define DATA_ENTRY_PENDING 0 ///< Entry not yet used +#define DATA_ENTRY_ACTIVE 1 ///< Entry in use by radio CPU +#define DATA_ENTRY_BUSY 2 ///< Entry being updated +#define DATA_ENTRY_FINISHED 3 ///< Radio CPU is finished accessing the entry +#define DATA_ENTRY_UNFINISHED 4 ///< Radio CPU is finished accessing the entry, but packet could not be finished ///@} - - /// \name Macros for RF register override ///@{ /// Macro for ADI half-size value-mask combination #define ADI_VAL_MASK(addr, mask, value) \ - (((addr) & 1) ? (((mask) & 0x0F) | (((value) & 0x0F) << 4)) : \ - ((((mask) & 0x0F) << 4) | ((value) & 0x0F))) + (((addr) & 1) ? (((mask) & 0x0F) | (((value) & 0x0F) << 4)) : ((((mask) & 0x0F) << 4) | ((value) & 0x0F))) /// 32-bit write of 16-bit value -#define HW_REG_OVERRIDE(addr, val) ((((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(val) << 16)) +#define HW_REG_OVERRIDE(addr, val) ((((uintptr_t)(addr)) & 0xFFFC) | ((uint32_t)(val) << 16)) /// ADI register, full-size write #define ADI_REG_OVERRIDE(adiNo, addr, val) (2 | ((uint32_t)(val) << 16) | \ - (((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31)) + (((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31)) /// 2 ADI registers, full-size write -#define ADI_2REG_OVERRIDE(adiNo, addr, val, addr2, val2) \ +#define ADI_2REG_OVERRIDE(adiNo, addr, val, addr2, val2) \ (2 | ((uint32_t)(val2) << 2) | (((addr2) & 0x3F) << 10) | ((uint32_t)(val) << 16) | \ (((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31)) /// ADI register, half-size read-modify-write #define ADI_HALFREG_OVERRIDE(adiNo, addr, mask, val) (2 | (ADI_VAL_MASK(addr, mask, val) << 16) | \ - (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31)) + (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31)) /// 2 ADI registers, half-size read-modify-write -#define ADI_2HALFREG_OVERRIDE(adiNo, addr, mask, val, addr2, mask2, val2) \ +#define ADI_2HALFREG_OVERRIDE(adiNo, addr, mask, val, addr2, mask2, val2) \ (2 | (ADI_VAL_MASK(addr2, mask2, val2) << 2) | (((addr2) & 0x3F) << 10) | \ (ADI_VAL_MASK(addr, mask, val) << 16) | (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31)) @@ -296,37 +276,36 @@ typedef struct #define SW_REG_OVERRIDE(cmd, field, val) (3 | ((_POSITION_##cmd##_##field) << 4) | ((uint32_t)(val) << 16)) /// SW register as defined in radio_par_def.txt with added index (for use with registers > 16 bits). #define SW_REG_IND_OVERRIDE(cmd, field, offset, val) (3 | \ - (((_POSITION_##cmd##_##field) + ((offset) << 1)) << 4) | ((uint32_t)(val) << 16)) + (((_POSITION_##cmd##_##field) + ((offset) << 1)) << 4) | ((uint32_t)(val) << 16)) /// 8-bit SW register as defined in radio_par_def.txt #define SW_REG_BYTE_OVERRIDE(cmd, field, val) (0x8003 | ((_POSITION_##cmd##_##field) << 4) | \ - ((uint32_t)(val) << 16)) + ((uint32_t)(val) << 16)) /// Two 8-bit SW registers as defined in radio_par_def.txt; the one given by field and the next byte. #define SW_REG_2BYTE_OVERRIDE(cmd, field, val0, val1) (3 | (((_POSITION_##cmd##_##field) & 0xFFFE) << 4) | \ - (((uint32_t)(val0) << 16) & 0x00FF0000) | ((uint32_t)(val1) << 24)) -#define HW16_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) -#define HW32_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | \ - ((uint32_t)(length) << 16) | (1U << 30)) + (((uint32_t)(val0) << 16) & 0x00FF0000) | ((uint32_t)(val1) << 24)) +#define HW16_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t)(addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) +#define HW32_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t)(addr)) & 0xFFFC) | \ + ((uint32_t)(length) << 16) | (1U << 30)) #define ADI_ARRAY_OVERRIDE(adiNo, addr, bHalfSize, length) (1 | ((((addr) & 0x3F) << 2)) | \ - ((!!(bHalfSize)) << 8) | ((!!(adiNo)) << 9) | ((uint32_t)(length) << 16) | (2U << 30)) + ((!!(bHalfSize)) << 8) | ((!!(adiNo)) << 9) | ((uint32_t)(length) << 16) | (2U << 30)) #define SW_ARRAY_OVERRIDE(cmd, firstfield, length) (1 | (((_POSITION_##cmd##_##firstfield)) << 2) | \ - ((uint32_t)(length) << 16) | (3U << 30)) -#define MCE_RFE_OVERRIDE(bMceRam, mceRomBank, mceMode, bRfeRam, rfeRomBank, rfeMode) \ + ((uint32_t)(length) << 16) | (3U << 30)) +#define MCE_RFE_OVERRIDE(bMceRam, mceRomBank, mceMode, bRfeRam, rfeRomBank, rfeMode) \ (7 | ((!!(bMceRam)) << 8) | (((mceRomBank) & 0x07) << 9) | ((!!(bRfeRam)) << 12) | (((rfeRomBank) & 0x07) << 13) | \ (((mceMode) & 0x00FF) << 16) | (((rfeMode) & 0x00FF) << 24)) -#define NEW_OVERRIDE_SEGMENT(address) (((((uintptr_t)(address)) & 0x03FFFFFC) << 6) | 0x000F | \ - (((((uintptr_t)(address) >> 24) == 0x20) ? 0x01 : \ - (((uintptr_t)(address) >> 24) == 0x21) ? 0x02 : \ - (((uintptr_t)(address) >> 24) == 0xA0) ? 0x03 : \ - (((uintptr_t)(address) >> 24) == 0x00) ? 0x04 : \ - (((uintptr_t)(address) >> 24) == 0x10) ? 0x05 : \ - (((uintptr_t)(address) >> 24) == 0x11) ? 0x06 : \ - (((uintptr_t)(address) >> 24) == 0x40) ? 0x07 : \ - (((uintptr_t)(address) >> 24) == 0x50) ? 0x08 : \ - 0x09) << 4)) // Use illegal value for illegal address range +#define NEW_OVERRIDE_SEGMENT(address) (((((uintptr_t)(address)) & 0x03FFFFFC) << 6) | 0x000F | \ + (((((uintptr_t)(address) >> 24) == 0x20) ? 0x01 : (((uintptr_t)(address) >> 24) == 0x21) ? 0x02 \ + : (((uintptr_t)(address) >> 24) == 0xA0) ? 0x03 \ + : (((uintptr_t)(address) >> 24) == 0x00) ? 0x04 \ + : (((uintptr_t)(address) >> 24) == 0x10) ? 0x05 \ + : (((uintptr_t)(address) >> 24) == 0x11) ? 0x06 \ + : (((uintptr_t)(address) >> 24) == 0x40) ? 0x07 \ + : (((uintptr_t)(address) >> 24) == 0x50) ? 0x08 \ + : 0x09) \ + << 4)) // Use illegal value for illegal address range /// End of string for override register #define END_OVERRIDE 0xFFFFFFFF - /// ADI address-value pair #define ADI_ADDR_VAL(addr, value) ((((addr) & 0x7F) << 8) | ((value) & 0xFF)) #define ADI_ADDR_VAL_MASK(addr, mask, value) ((((addr) & 0x7F) << 8) | ADI_VAL_MASK(addr, mask, value)) @@ -337,5 +316,4 @@ typedef struct #define HIWORD(value) ((value) >> 16) ///@} - #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_prop_cmd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_prop_cmd.h index 872dbd1..4d1ec35 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_prop_cmd.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_prop_cmd.h @@ -1,56 +1,56 @@ /****************************************************************************** -* Filename: rf_prop_cmd.h -* Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) -* Revision: 18052 -* -* Description: CC26x0 API for Proprietary mode commands -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_prop_cmd.h + * Revised: 2017-11-10 10:42:47 +0100 (Fri, 10 Nov 2017) + * Revision: 18052 + * + * Description: CC26x0 API for Proprietary mode commands + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __PROP_CMD_H #define __PROP_CMD_H #ifndef __RFC_STRUCT - #define __RFC_STRUCT +#define __RFC_STRUCT #endif #ifndef __RFC_STRUCT_ATTR - #if defined(__GNUC__) - #define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) - #elif defined(__TI_ARM__) - #define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) - #else - #define __RFC_STRUCT_ATTR - #endif +#if defined(__GNUC__) +#define __RFC_STRUCT_ATTR __attribute__((aligned(4))) +#elif defined(__TI_ARM__) +#define __RFC_STRUCT_ATTR __attribute__((__packed__, aligned(4))) +#else +#define __RFC_STRUCT_ATTR +#endif #endif //! \addtogroup rfc @@ -59,9 +59,9 @@ //! \addtogroup prop_cmd //! @{ -#include -#include "rf_mailbox.h" #include "rf_common_cmd.h" +#include "rf_mailbox.h" +#include typedef struct __RFC_STRUCT rfc_CMD_PROP_TX_s rfc_CMD_PROP_TX_t; typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_s rfc_CMD_PROP_RX_t; @@ -76,421 +76,421 @@ typedef struct __RFC_STRUCT rfc_propRxStatus_s rfc_propRxStatus_t; //! \addtogroup CMD_PROP_TX //! @{ -#define CMD_PROP_TX 0x3801 +#define CMD_PROP_TX 0x3801 //! Proprietary Mode Transmit Command struct __RFC_STRUCT rfc_CMD_PROP_TX_s { - uint16_t commandNo; //!< The command ID number 0x3801 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t : 2; - uint8_t bUseCrc: 1; //!< \brief 0: Do not append CRC
- //!< 1: Append CRC - uint8_t bVarLen: 1; //!< \brief 0: Fixed length
- //!< 1: Transmit length as first byte - } pktConf; - uint8_t pktLen; //!< Packet length - uint32_t syncWord; //!< Sync word to transmit - uint8_t* pPkt; //!< Pointer to packet + uint16_t commandNo; //!< The command ID number 0x3801 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t : 2; + uint8_t bUseCrc : 1; //!< \brief 0: Do not append CRC
+ //!< 1: Append CRC + uint8_t bVarLen : 1; //!< \brief 0: Fixed length
+ //!< 1: Transmit length as first byte + } pktConf; + uint8_t pktLen; //!< Packet length + uint32_t syncWord; //!< Sync word to transmit + uint8_t* pPkt; //!< Pointer to packet } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_RX //! @{ -#define CMD_PROP_RX 0x3802 +#define CMD_PROP_RX 0x3802 //! Proprietary Mode Receive Command struct __RFC_STRUCT rfc_CMD_PROP_RX_s { - uint16_t commandNo; //!< The command ID number 0x3802 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bRepeatOk: 1; //!< \brief 0: End operation after receiving a packet correctly
- //!< 1: Go back to sync search after receiving a packet correctly - uint8_t bRepeatNok: 1; //!< \brief 0: End operation after receiving a packet with CRC error
- //!< 1: Go back to sync search after receiving a packet with CRC error - uint8_t bUseCrc: 1; //!< \brief 0: Do not check CRC
- //!< 1: Check CRC - uint8_t bVarLen: 1; //!< \brief 0: Fixed length
- //!< 1: Receive length as first byte - uint8_t bChkAddress: 1; //!< \brief 0: No address check
- //!< 1: Check address - uint8_t endType: 1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
- //!< 1: Packet reception is stopped if end trigger happens - uint8_t filterOp: 1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
- //!< 1: Receive packet and mark it as ignored on address mismatch - } pktConf; - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically discard ignored packets from RX queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically discard packets with CRC error from RX queue - uint8_t : 1; - uint8_t bIncludeHdr: 1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the RX queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the RX queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the RX queue - } rxConf; //!< RX configuration - uint32_t syncWord; //!< Sync word to listen for - uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
- //!< 0: Unlimited or unknown length - uint8_t address0; //!< Address - uint8_t address1; //!< \brief Address (set equal to address0 to accept only one address. If 0xFF, accept - //!< 0x00 as well) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - ratmr_t endTime; //!< Time used together with endTrigger for ending the operation - dataQueue_t* pQueue; //!< Pointer to receive queue - uint8_t* pOutput; //!< Pointer to output structure + uint16_t commandNo; //!< The command ID number 0x3802 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk : 1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok : 1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc : 1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bVarLen : 1; //!< \brief 0: Fixed length
+ //!< 1: Receive length as first byte + uint8_t bChkAddress : 1; //!< \brief 0: No address check
+ //!< 1: Check address + uint8_t endType : 1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp : 1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t : 1; + uint8_t bIncludeHdr : 1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord; //!< Sync word to listen for + uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + uint8_t address0; //!< Address + uint8_t address1; //!< \brief Address (set equal to address0 to accept only one address. If 0xFF, accept + //!< 0x00 as well) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_TX_ADV //! @{ -#define CMD_PROP_TX_ADV 0x3803 +#define CMD_PROP_TX_ADV 0x3803 //! Proprietary Mode Advanced Transmit Command struct __RFC_STRUCT rfc_CMD_PROP_TX_ADV_s { - uint16_t commandNo; //!< The command ID number 0x3803 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t : 2; - uint8_t bUseCrc: 1; //!< \brief 0: Do not append CRC
- //!< 1: Append CRC - uint8_t bCrcIncSw: 1; //!< \brief 0:Do not include sync word in CRC calculation
- //!< 1: Include sync word in CRC calculation - uint8_t bCrcIncHdr: 1; //!< \brief 0: Do not include header in CRC calculation
- //!< 1: Include header in CRC calculation - } pktConf; - uint8_t numHdrBits; //!< Number of bits in header (0--32) - uint16_t pktLen; //!< Packet length. 0: Unlimited - struct - { - uint8_t bExtTxTrig: 1; //!< \brief 0: Start packet on a fixed time from the command start trigger
- //!< 1: Start packet on an external trigger (input event to RAT) - uint8_t inputMode: 2; //!< \brief Input mode if external trigger is used for TX start
- //!< 0: Rising edge
- //!< 1: Falling edge
- //!< 2: Both edges
- //!< 3: Reserved - uint8_t source: 5; //!< RAT input event number used for capture if external trigger is used for TX start - } startConf; - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } preTrigger; //!< Trigger for transition from preamble to sync word - ratmr_t preTime; //!< \brief Time used together with preTrigger for transition from preamble to sync - //!< word. If preTrigger.triggerType is set to "now", one preamble as - //!< configured in the setup will be sent. Otherwise, the preamble will be repeated until - //!< this trigger is observed. - uint32_t syncWord; //!< Sync word to transmit - uint8_t* pPkt; //!< Pointer to packet, or TX queue for unlimited length + uint16_t commandNo; //!< The command ID number 0x3803 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t : 2; + uint8_t bUseCrc : 1; //!< \brief 0: Do not append CRC
+ //!< 1: Append CRC + uint8_t bCrcIncSw : 1; //!< \brief 0:Do not include sync word in CRC calculation
+ //!< 1: Include sync word in CRC calculation + uint8_t bCrcIncHdr : 1; //!< \brief 0: Do not include header in CRC calculation
+ //!< 1: Include header in CRC calculation + } pktConf; + uint8_t numHdrBits; //!< Number of bits in header (0--32) + uint16_t pktLen; //!< Packet length. 0: Unlimited + struct + { + uint8_t bExtTxTrig : 1; //!< \brief 0: Start packet on a fixed time from the command start trigger
+ //!< 1: Start packet on an external trigger (input event to RAT) + uint8_t inputMode : 2; //!< \brief Input mode if external trigger is used for TX start
+ //!< 0: Rising edge
+ //!< 1: Falling edge
+ //!< 2: Both edges
+ //!< 3: Reserved + uint8_t source : 5; //!< RAT input event number used for capture if external trigger is used for TX start + } startConf; + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } preTrigger; //!< Trigger for transition from preamble to sync word + ratmr_t preTime; //!< \brief Time used together with preTrigger for transition from preamble to sync + //!< word. If preTrigger.triggerType is set to "now", one preamble as + //!< configured in the setup will be sent. Otherwise, the preamble will be repeated until + //!< this trigger is observed. + uint32_t syncWord; //!< Sync word to transmit + uint8_t* pPkt; //!< Pointer to packet, or TX queue for unlimited length } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_RX_ADV //! @{ -#define CMD_PROP_RX_ADV 0x3804 +#define CMD_PROP_RX_ADV 0x3804 //! Proprietary Mode Advanced Receive Command struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_s { - uint16_t commandNo; //!< The command ID number 0x3804 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint8_t bFsOff: 1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bRepeatOk: 1; //!< \brief 0: End operation after receiving a packet correctly
- //!< 1: Go back to sync search after receiving a packet correctly - uint8_t bRepeatNok: 1; //!< \brief 0: End operation after receiving a packet with CRC error
- //!< 1: Go back to sync search after receiving a packet with CRC error - uint8_t bUseCrc: 1; //!< \brief 0: Do not check CRC
- //!< 1: Check CRC - uint8_t bCrcIncSw: 1; //!< \brief 0: Do not include sync word in CRC calculation
- //!< 1: Include sync word in CRC calculation - uint8_t bCrcIncHdr: 1; //!< \brief 0: Do not include header in CRC calculation
- //!< 1: Include header in CRC calculation - uint8_t endType: 1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
- //!< 1: Packet reception is stopped if end trigger happens - uint8_t filterOp: 1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
- //!< 1: Receive packet and mark it as ignored on address mismatch - } pktConf; - struct - { - uint8_t bAutoFlushIgnored: 1; //!< If 1, automatically discard ignored packets from RX queue - uint8_t bAutoFlushCrcErr: 1; //!< If 1, automatically discard packets with CRC error from RX queue - uint8_t : 1; - uint8_t bIncludeHdr: 1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc: 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi: 1; //!< If 1, append an RSSI byte to the packet in the RX queue - uint8_t bAppendTimestamp: 1; //!< If 1, append a timestamp to the packet in the RX queue - uint8_t bAppendStatus: 1; //!< If 1, append a status byte to the packet in the RX queue - } rxConf; //!< RX configuration - uint32_t syncWord0; //!< Sync word to listen for - uint32_t syncWord1; //!< Alternative sync word if non-zero - uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
- //!< 0: Unlimited or unknown length - struct - { - uint16_t numHdrBits: 6; //!< Number of bits in header (0--32) - uint16_t lenPos: 5; //!< Position of length field in header (0--31) - uint16_t numLenBits: 5; //!< Number of bits in length field (0--16) - } hdrConf; - struct - { - uint16_t addrType: 1; //!< \brief 0: Address after header
- //!< 1: Address in header - uint16_t addrSize: 5; //!< \brief If addrType = 0: Address size in bytes
- //!< If addrType = 1: Address size in bits - uint16_t addrPos: 5; //!< \brief If addrType = 1: Bit position of address in header
- //!< If addrType = 0: Non-zero to extend address with sync word identifier - uint16_t numAddr: 5; //!< Number of addresses in address list - } addrConf; - int8_t lenOffset; //!< Signed value to add to length field - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - ratmr_t endTime; //!< Time used together with endTrigger for ending the operation - uint8_t* pAddr; //!< Pointer to address list - dataQueue_t* pQueue; //!< Pointer to receive queue - uint8_t* pOutput; //!< Pointer to output structure + uint16_t commandNo; //!< The command ID number 0x3804 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint8_t bFsOff : 1; //!< \brief 0: Keep frequency synth on after command
+ //!< 1: Turn frequency synth off after command + uint8_t bRepeatOk : 1; //!< \brief 0: End operation after receiving a packet correctly
+ //!< 1: Go back to sync search after receiving a packet correctly + uint8_t bRepeatNok : 1; //!< \brief 0: End operation after receiving a packet with CRC error
+ //!< 1: Go back to sync search after receiving a packet with CRC error + uint8_t bUseCrc : 1; //!< \brief 0: Do not check CRC
+ //!< 1: Check CRC + uint8_t bCrcIncSw : 1; //!< \brief 0: Do not include sync word in CRC calculation
+ //!< 1: Include sync word in CRC calculation + uint8_t bCrcIncHdr : 1; //!< \brief 0: Do not include header in CRC calculation
+ //!< 1: Include header in CRC calculation + uint8_t endType : 1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
+ //!< 1: Packet reception is stopped if end trigger happens + uint8_t filterOp : 1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
+ //!< 1: Receive packet and mark it as ignored on address mismatch + } pktConf; + struct + { + uint8_t bAutoFlushIgnored : 1; //!< If 1, automatically discard ignored packets from RX queue + uint8_t bAutoFlushCrcErr : 1; //!< If 1, automatically discard packets with CRC error from RX queue + uint8_t : 1; + uint8_t bIncludeHdr : 1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it + uint8_t bIncludeCrc : 1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it + uint8_t bAppendRssi : 1; //!< If 1, append an RSSI byte to the packet in the RX queue + uint8_t bAppendTimestamp : 1; //!< If 1, append a timestamp to the packet in the RX queue + uint8_t bAppendStatus : 1; //!< If 1, append a status byte to the packet in the RX queue + } rxConf; //!< RX configuration + uint32_t syncWord0; //!< Sync word to listen for + uint32_t syncWord1; //!< Alternative sync word if non-zero + uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
+ //!< 0: Unlimited or unknown length + struct + { + uint16_t numHdrBits : 6; //!< Number of bits in header (0--32) + uint16_t lenPos : 5; //!< Position of length field in header (0--31) + uint16_t numLenBits : 5; //!< Number of bits in length field (0--16) + } hdrConf; + struct + { + uint16_t addrType : 1; //!< \brief 0: Address after header
+ //!< 1: Address in header + uint16_t addrSize : 5; //!< \brief If addrType = 0: Address size in bytes
+ //!< If addrType = 1: Address size in bits + uint16_t addrPos : 5; //!< \brief If addrType = 1: Bit position of address in header
+ //!< If addrType = 0: Non-zero to extend address with sync word identifier + uint16_t numAddr : 5; //!< Number of addresses in address list + } addrConf; + int8_t lenOffset; //!< Signed value to add to length field + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } endTrigger; //!< Trigger classifier for ending the operation + ratmr_t endTime; //!< Time used together with endTrigger for ending the operation + uint8_t* pAddr; //!< Pointer to address list + dataQueue_t* pQueue; //!< Pointer to receive queue + uint8_t* pOutput; //!< Pointer to output structure } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_RADIO_SETUP //! @{ -#define CMD_PROP_RADIO_SETUP 0x3806 +#define CMD_PROP_RADIO_SETUP 0x3806 //! Proprietary Mode Radio Setup Command struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_s { - uint16_t commandNo; //!< The command ID number 0x3806 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct - { - uint8_t triggerType: 4; //!< The type of trigger - uint8_t bEnaCmd: 1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo: 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig: 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct - { - uint8_t rule: 4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip: 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct - { - uint16_t modType: 3; //!< \brief 0: FSK
- //!< 1: GFSK
- //!< Others: Reserved - uint16_t deviation: 13; //!< Deviation (250 Hz steps) - } modulation; - struct - { - uint32_t preScale: 4; //!< Prescaler value - uint32_t : 4; - uint32_t rateWord: 21; //!< Rate word - } symbolRate; //!< Symbol rate setting - uint8_t rxBw; //!< Receiver bandwidth - struct - { - uint8_t nPreamBytes: 6; //!< \brief 0: 1 preamble bit
- //!< 1--16: Number of preamble bytes
- //!< 18, 20, ..., 30: Number of preamble bytes
- //!< 31: 4 preamble bits
- //!< 32: 32 preamble bytes
- //!< Others: Reserved - uint8_t preamMode: 2; //!< \brief 0: Send 0 as the first preamble bit
- //!< 1: Send 1 as the first preamble bit
- //!< 2: Send same first bit in preamble and sync word
- //!< 3: Send different first bit in preamble and sync word - } preamConf; - struct - { - uint16_t nSwBits: 6; //!< Number of sync word bits (8--32) - uint16_t bBitReversal: 1; //!< \brief 0: Use positive deviation for 1
- //!< 1: Use positive deviation for 0 - uint16_t bMsbFirst: 1; //!< \brief 0: Least significant bit transmitted first
- //!< 1: Most significant bit transmitted first - uint16_t fecMode: 4; //!< \brief Select coding
- //!< 0: Uncoded binary modulation
- //!< Others: Reserved - uint16_t bOuterCode: 1; //!< Reserved - uint16_t whitenMode: 2; //!< \brief 0: No whitening
- //!< 1: CC1101/CC2500 compatible whitening
- //!< 2: PN9 whitening without byte reversal
- //!< 3: Reserved - uint16_t bAgcDisable: 1; //!< Reserved - } formatConf; - struct - { - uint16_t frontEndMode: 3; //!< \brief 0x00: Differential mode
- //!< 0x01: Single-ended mode RFP
- //!< 0x02: Single-ended mode RFN
- //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
- //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
- //!< Others: Reserved - uint16_t biasMode: 1; //!< \brief 0: Internal bias
- //!< 1: External bias - uint16_t analogCfgMode: 6; //!< \brief 0x00: Write analog configuration.
- //!< Required first time after boot and when changing frequency band - //!< or front-end configuration
- //!< 0x2D: Keep analog configuration.
- //!< May be used after standby or when changing mode with the same frequency - //!< band and front-end configuration
- //!< Others: Reserved - uint16_t bNoFsPowerUp: 1; //!< \brief 0: Power up frequency synth
- //!< 1: Do not power up frequency synth - } config; //!< Configuration options - uint16_t txPower; //!< \brief Transmit power - //!< Bits 0--5: IB - //!< Value to write to the PA power control field at 25 °C - //!< Bits 6--7: GC - //!< Value to write to the gain control of the 1st stage of the PA - //!< Bits 8--15: tempCoeff - //!< Temperature coefficient for IB. 0: No temperature compensation - uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override. If NULL, no override is used. + uint16_t commandNo; //!< The command ID number 0x3806 + uint16_t status; //!< \brief An integer telling the status of the command. This value is + //!< updated by the radio CPU during operation and may be read by the + //!< system CPU at any time. + rfc_radioOp_t* pNextOp; //!< Pointer to the next operation to run after this operation is done + ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) + struct + { + uint8_t triggerType : 4; //!< The type of trigger + uint8_t bEnaCmd : 1; //!< \brief 0: No alternative trigger command
+ //!< 1: CMD_TRIGGER can be used as an alternative trigger + uint8_t triggerNo : 2; //!< The trigger number of the CMD_TRIGGER command that triggers this action + uint8_t pastTrig : 1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
+ //!< 1: A trigger in the past is triggered as soon as possible + } startTrigger; //!< Identification of the trigger that starts the operation + struct + { + uint8_t rule : 4; //!< Condition for running next command: Rule for how to proceed + uint8_t nSkip : 4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... + } condition; + struct + { + uint16_t modType : 3; //!< \brief 0: FSK
+ //!< 1: GFSK
+ //!< Others: Reserved + uint16_t deviation : 13; //!< Deviation (250 Hz steps) + } modulation; + struct + { + uint32_t preScale : 4; //!< Prescaler value + uint32_t : 4; + uint32_t rateWord : 21; //!< Rate word + } symbolRate; //!< Symbol rate setting + uint8_t rxBw; //!< Receiver bandwidth + struct + { + uint8_t nPreamBytes : 6; //!< \brief 0: 1 preamble bit
+ //!< 1--16: Number of preamble bytes
+ //!< 18, 20, ..., 30: Number of preamble bytes
+ //!< 31: 4 preamble bits
+ //!< 32: 32 preamble bytes
+ //!< Others: Reserved + uint8_t preamMode : 2; //!< \brief 0: Send 0 as the first preamble bit
+ //!< 1: Send 1 as the first preamble bit
+ //!< 2: Send same first bit in preamble and sync word
+ //!< 3: Send different first bit in preamble and sync word + } preamConf; + struct + { + uint16_t nSwBits : 6; //!< Number of sync word bits (8--32) + uint16_t bBitReversal : 1; //!< \brief 0: Use positive deviation for 1
+ //!< 1: Use positive deviation for 0 + uint16_t bMsbFirst : 1; //!< \brief 0: Least significant bit transmitted first
+ //!< 1: Most significant bit transmitted first + uint16_t fecMode : 4; //!< \brief Select coding
+ //!< 0: Uncoded binary modulation
+ //!< Others: Reserved + uint16_t bOuterCode : 1; //!< Reserved + uint16_t whitenMode : 2; //!< \brief 0: No whitening
+ //!< 1: CC1101/CC2500 compatible whitening
+ //!< 2: PN9 whitening without byte reversal
+ //!< 3: Reserved + uint16_t bAgcDisable : 1; //!< Reserved + } formatConf; + struct + { + uint16_t frontEndMode : 3; //!< \brief 0x00: Differential mode
+ //!< 0x01: Single-ended mode RFP
+ //!< 0x02: Single-ended mode RFN
+ //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
+ //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
+ //!< Others: Reserved + uint16_t biasMode : 1; //!< \brief 0: Internal bias
+ //!< 1: External bias + uint16_t analogCfgMode : 6; //!< \brief 0x00: Write analog configuration.
+ //!< Required first time after boot and when changing frequency band + //!< or front-end configuration
+ //!< 0x2D: Keep analog configuration.
+ //!< May be used after standby or when changing mode with the same frequency + //!< band and front-end configuration
+ //!< Others: Reserved + uint16_t bNoFsPowerUp : 1; //!< \brief 0: Power up frequency synth
+ //!< 1: Do not power up frequency synth + } config; //!< Configuration options + uint16_t txPower; //!< \brief Transmit power + //!< Bits 0--5: IB + //!< Value to write to the PA power control field at 25 °C + //!< Bits 6--7: GC + //!< Value to write to the gain control of the 1st stage of the PA + //!< Bits 8--15: tempCoeff + //!< Temperature coefficient for IB. 0: No temperature compensation + uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override. If NULL, no override is used. } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_RADIO_DIV_SETUP //! @{ -#define CMD_PROP_RADIO_DIV_SETUP 0x3807 +#define CMD_PROP_RADIO_DIV_SETUP 0x3807 //! Define only for compatibility with CC13XX family. Command will result in error if sent. struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_s { - uint8_t dummy0; + uint8_t dummy0; } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_SET_LEN //! @{ -#define CMD_PROP_SET_LEN 0x3401 +#define CMD_PROP_SET_LEN 0x3401 //! Set Packet Length Command struct __RFC_STRUCT rfc_CMD_PROP_SET_LEN_s { - uint16_t commandNo; //!< The command ID number 0x3401 - uint16_t rxLen; //!< Payload length to use + uint16_t commandNo; //!< The command ID number 0x3401 + uint16_t rxLen; //!< Payload length to use } __RFC_STRUCT_ATTR; //! @} //! \addtogroup CMD_PROP_RESTART_RX //! @{ -#define CMD_PROP_RESTART_RX 0x3402 +#define CMD_PROP_RESTART_RX 0x3402 //! Restart Packet Command struct __RFC_STRUCT rfc_CMD_PROP_RESTART_RX_s { - uint16_t commandNo; //!< The command ID number 0x3402 + uint16_t commandNo; //!< The command ID number 0x3402 } __RFC_STRUCT_ATTR; //! @} @@ -501,13 +501,13 @@ struct __RFC_STRUCT rfc_CMD_PROP_RESTART_RX_s struct __RFC_STRUCT rfc_propRxOutput_s { - uint16_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored - uint16_t nRxNok; //!< Number of packets that have been received with CRC error - uint8_t nRxIgnored; //!< Number of packets that have been received with CRC OK and ignored due to address mismatch - uint8_t nRxStopped; //!< Number of packets not received due to illegal length or address mismatch with pktConf.filterOp = 1 - uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space - int8_t lastRssi; //!< RSSI of last received packet - ratmr_t timeStamp; //!< Time stamp of last received packet + uint16_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored + uint16_t nRxNok; //!< Number of packets that have been received with CRC error + uint8_t nRxIgnored; //!< Number of packets that have been received with CRC OK and ignored due to address mismatch + uint8_t nRxStopped; //!< Number of packets not received due to illegal length or address mismatch with pktConf.filterOp = 1 + uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space + int8_t lastRssi; //!< RSSI of last received packet + ratmr_t timeStamp; //!< Time stamp of last received packet } __RFC_STRUCT_ATTR; //! @} @@ -518,15 +518,15 @@ struct __RFC_STRUCT rfc_propRxOutput_s struct __RFC_STRUCT rfc_propRxStatus_s { - struct - { - uint8_t addressInd: 5; //!< Index of address found (0 if not applicable) - uint8_t syncWordId: 1; //!< 0 for primary sync word, 1 for alternate sync word - uint8_t result: 2; //!< \brief 0: Packet received correctly, not ignored
- //!< 1: Packet received with CRC error
- //!< 2: Packet received correctly, but can be ignored
- //!< 3: Packet reception was aborted - } status; + struct + { + uint8_t addressInd : 5; //!< Index of address found (0 if not applicable) + uint8_t syncWordId : 1; //!< 0 for primary sync word, 1 for alternate sync word + uint8_t result : 2; //!< \brief 0: Packet received correctly, not ignored
+ //!< 1: Packet received with CRC error
+ //!< 2: Packet received correctly, but can be ignored
+ //!< 3: Packet reception was aborted + } status; } __RFC_STRUCT_ATTR; //! @} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_prop_mailbox.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_prop_mailbox.h index 7eb264b..b009d07 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_prop_mailbox.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rf_prop_mailbox.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_prop_mailbox.h -* Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) -* Revision: 18032 -* -* Description: Definitions for proprietary mode radio interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_prop_mailbox.h + * Revised: 2017-11-03 15:06:37 +0100 (Fri, 03 Nov 2017) + * Revision: 18032 + * + * Description: Definitions for proprietary mode radio interface + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _PROP_MAILBOX_H #define _PROP_MAILBOX_H @@ -43,28 +43,28 @@ ///@{ /// \name Operation finished normally ///@{ -#define PROP_DONE_OK 0x3400 ///< Operation ended normally -#define PROP_DONE_RXTIMEOUT 0x3401 ///< Operation stopped after end trigger while waiting for sync -#define PROP_DONE_BREAK 0x3402 ///< Rx stopped due to timeout in the middle of a packet -#define PROP_DONE_ENDED 0x3403 ///< Operation stopped after end trigger during reception -#define PROP_DONE_STOPPED 0x3404 ///< Operation stopped after stop command -#define PROP_DONE_ABORT 0x3405 ///< Operation aborted by abort command -#define PROP_DONE_RXERR 0x3406 ///< Operation ended after receiving packet with CRC error -#define PROP_DONE_IDLE 0x3407 ///< Carrier sense operation ended because of idle channel -#define PROP_DONE_BUSY 0x3408 ///< Carrier sense operation ended because of busy channel -#define PROP_DONE_IDLETIMEOUT 0x3409 ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 1 -#define PROP_DONE_BUSYTIMEOUT 0x340A ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 0 +#define PROP_DONE_OK 0x3400 ///< Operation ended normally +#define PROP_DONE_RXTIMEOUT 0x3401 ///< Operation stopped after end trigger while waiting for sync +#define PROP_DONE_BREAK 0x3402 ///< Rx stopped due to timeout in the middle of a packet +#define PROP_DONE_ENDED 0x3403 ///< Operation stopped after end trigger during reception +#define PROP_DONE_STOPPED 0x3404 ///< Operation stopped after stop command +#define PROP_DONE_ABORT 0x3405 ///< Operation aborted by abort command +#define PROP_DONE_RXERR 0x3406 ///< Operation ended after receiving packet with CRC error +#define PROP_DONE_IDLE 0x3407 ///< Carrier sense operation ended because of idle channel +#define PROP_DONE_BUSY 0x3408 ///< Carrier sense operation ended because of busy channel +#define PROP_DONE_IDLETIMEOUT 0x3409 ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 1 +#define PROP_DONE_BUSYTIMEOUT 0x340A ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 0 ///@} /// \name Operation finished with error ///@{ -#define PROP_ERROR_PAR 0x3800 ///< Illegal parameter -#define PROP_ERROR_RXBUF 0x3801 ///< No available Rx buffer at the start of a packet -#define PROP_ERROR_RXFULL 0x3802 ///< Out of Rx buffer during reception in a partial read buffer -#define PROP_ERROR_NO_SETUP 0x3803 ///< Radio was not set up in proprietary mode -#define PROP_ERROR_NO_FS 0x3804 ///< Synth was not programmed when running Rx or Tx -#define PROP_ERROR_RXOVF 0x3805 ///< Rx overflow observed during operation -#define PROP_ERROR_TXUNF 0x3806 ///< Tx underflow observed during operation +#define PROP_ERROR_PAR 0x3800 ///< Illegal parameter +#define PROP_ERROR_RXBUF 0x3801 ///< No available Rx buffer at the start of a packet +#define PROP_ERROR_RXFULL 0x3802 ///< Out of Rx buffer during reception in a partial read buffer +#define PROP_ERROR_NO_SETUP 0x3803 ///< Radio was not set up in proprietary mode +#define PROP_ERROR_NO_FS 0x3804 ///< Synth was not programmed when running Rx or Tx +#define PROP_ERROR_RXOVF 0x3805 ///< Rx overflow observed during operation +#define PROP_ERROR_TXUNF 0x3806 ///< Tx underflow observed during operation ///@} ///@} diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rfc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rfc.h index a2377ce..553afd0 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rfc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rfc.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rfc.h -* Revised: 2018-08-08 14:03:25 +0200 (Wed, 08 Aug 2018) -* Revision: 52338 -* -* Description: Defines and prototypes for the RF Core. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rfc.h + * Revised: 2018-08-08 14:03:25 +0200 (Wed, 08 Aug 2018) + * Revision: 52338 + * + * Description: Defines and prototypes for the RF Core. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -53,34 +53,33 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_rfc_pwr.h" -#include "../inc/hw_rfc_dbell.h" -#include "../inc/hw_fcfg1.h" -#include "../inc/hw_adi_3_refsys.h" #include "../inc/hw_adi.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_fcfg1.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_rfc_dbell.h" +#include "../inc/hw_rfc_pwr.h" +#include "../inc/hw_types.h" +#include "rf_ble_cmd.h" #include "rf_common_cmd.h" #include "rf_prop_cmd.h" -#include "rf_ble_cmd.h" +#include +#include // Definition of RFTRIM container typedef struct { - uint32_t configIfAdc; - uint32_t configRfFrontend; - uint32_t configSynth; - uint32_t configMiscAdc; + uint32_t configIfAdc; + uint32_t configRfFrontend; + uint32_t configSynth; + uint32_t configMiscAdc; } rfTrim_t; // Definition of maximum search depth used by the RFCOverrideUpdate function -#define RFC_MAX_SEARCH_DEPTH 5 +#define RFC_MAX_SEARCH_DEPTH 5 //***************************************************************************** // @@ -96,17 +95,17 @@ typedef struct // //***************************************************************************** #if !defined(DOXYGEN) -#define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear -#define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo -#define RFCSynthPowerDown NOROM_RFCSynthPowerDown -#define RFCCpePatchReset NOROM_RFCCpePatchReset -#define RFCOverrideSearch NOROM_RFCOverrideSearch -#define RFCOverrideUpdate NOROM_RFCOverrideUpdate -#define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear -#define RFCRfTrimRead NOROM_RFCRfTrimRead -#define RFCRfTrimSet NOROM_RFCRfTrimSet -#define RFCRTrim NOROM_RFCRTrim -#define RFCAdi3VcoLdoVoltageMode NOROM_RFCAdi3VcoLdoVoltageMode +#define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear +#define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo +#define RFCSynthPowerDown NOROM_RFCSynthPowerDown +#define RFCCpePatchReset NOROM_RFCCpePatchReset +#define RFCOverrideSearch NOROM_RFCOverrideSearch +#define RFCOverrideUpdate NOROM_RFCOverrideUpdate +#define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear +#define RFCRfTrimRead NOROM_RFCRfTrimRead +#define RFCRfTrimSet NOROM_RFCRfTrimSet +#define RFCRTrim NOROM_RFCRTrim +#define RFCAdi3VcoLdoVoltageMode NOROM_RFCAdi3VcoLdoVoltageMode #endif //***************************************************************************** @@ -130,12 +129,9 @@ __STATIC_INLINE void RFCClockEnable(void) { // Enable basic clocks to get the CPE run - HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = RFC_PWR_PWMCLKEN_CPERAM - | RFC_PWR_PWMCLKEN_CPE - | RFC_PWR_PWMCLKEN_RFC; + HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = RFC_PWR_PWMCLKEN_CPERAM | RFC_PWR_PWMCLKEN_CPE | RFC_PWR_PWMCLKEN_RFC; } - //***************************************************************************** // //! \brief Disable the RF core clocks. @@ -158,7 +154,6 @@ RFCClockDisable(void) HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = 0x0; } - //***************************************************************************** // //! Clear HW interrupt flags @@ -174,7 +169,6 @@ RFCCpeIntClear(uint32_t ui32Mask) } while (HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) & ui32Mask); } - //***************************************************************************** // //! Clear CPE interrupt flags. @@ -187,7 +181,6 @@ RFCHwIntClear(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) = ~ui32Mask; } - //***************************************************************************** // //! Select interrupt sources to CPE0 (assign to INT_RFC_CPE_0 interrupt vector). @@ -200,7 +193,6 @@ RFCCpe0IntSelect(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) &= ~ui32Mask; } - //***************************************************************************** // //! Select interrupt sources to CPE1 (assign to INT_RFC_CPE_1 interrupt vector). @@ -213,7 +205,6 @@ RFCCpe1IntSelect(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) |= ui32Mask; } - //***************************************************************************** // //! Enable CPEx interrupt sources. @@ -226,7 +217,6 @@ RFCCpeIntEnable(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) |= ui32Mask; } - //***************************************************************************** // //! Select, clear, and enable interrupt sources to CPE0. @@ -245,7 +235,6 @@ RFCCpe0IntSelectClearEnable(uint32_t ui32Mask) RFCCpeIntEnable(ui32Mask); } - //***************************************************************************** // //! Select, clear, and enable interrupt sources to CPE1. @@ -264,7 +253,6 @@ RFCCpe1IntSelectClearEnable(uint32_t ui32Mask) RFCCpeIntEnable(ui32Mask); } - //***************************************************************************** // //! Enable HW interrupt sources. @@ -277,7 +265,6 @@ RFCHwIntEnable(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) |= ui32Mask; } - //***************************************************************************** // //! Disable CPE interrupt sources. @@ -290,7 +277,6 @@ RFCCpeIntDisable(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) &= ~ui32Mask; } - //***************************************************************************** // //! Disable HW interrupt sources. @@ -303,7 +289,6 @@ RFCHwIntDisable(uint32_t ui32Mask) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) &= ~ui32Mask; } - //***************************************************************************** // //! Get and clear CPE interrupt flags. @@ -311,7 +296,6 @@ RFCHwIntDisable(uint32_t ui32Mask) //***************************************************************************** extern uint32_t RFCCpeIntGetAndClear(uint32_t ui32Mask); - //***************************************************************************** // //! Clear ACK interrupt flag. @@ -324,7 +308,6 @@ RFCAckIntClear(void) HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG) = 0x0; } - //***************************************************************************** // //! Send a radio operation to the doorbell and wait for an acknowledgment. @@ -332,7 +315,6 @@ RFCAckIntClear(void) //***************************************************************************** extern uint32_t RFCDoorbellSendTo(uint32_t pOp); - //***************************************************************************** // //! This function implements a fast way to turn off the synthesizer. @@ -340,7 +322,6 @@ extern uint32_t RFCDoorbellSendTo(uint32_t pOp); //***************************************************************************** extern void RFCSynthPowerDown(void); - //***************************************************************************** // //! Reset previously patched CPE RAM to a state where it can be patched again. @@ -348,7 +329,6 @@ extern void RFCSynthPowerDown(void); //***************************************************************************** extern void RFCCpePatchReset(void); - //***************************************************************************** // // Function to search an override list for the provided pattern within the search depth. @@ -356,7 +336,6 @@ extern void RFCCpePatchReset(void); //***************************************************************************** extern uint8_t RFCOverrideSearch(const uint32_t* pOverride, const uint32_t pattern, const uint32_t mask, const uint8_t searchDepth); - //***************************************************************************** // //! Function to update override list @@ -364,7 +343,6 @@ extern uint8_t RFCOverrideSearch(const uint32_t* pOverride, const uint32_t patte //***************************************************************************** extern uint8_t RFCOverrideUpdate(rfc_radioOp_t* pOpSetup, uint32_t* pParams); - //***************************************************************************** // //! Get and clear HW interrupt flags. @@ -372,14 +350,12 @@ extern uint8_t RFCOverrideUpdate(rfc_radioOp_t* pOpSetup, uint32_t* pParams); //***************************************************************************** extern uint32_t RFCHwIntGetAndClear(uint32_t ui32Mask); - //***************************************************************************** // //! Get the type of currently selected PA. // //***************************************************************************** - //***************************************************************************** // //! Read RF trim from flash using CM3. @@ -387,7 +363,6 @@ extern uint32_t RFCHwIntGetAndClear(uint32_t ui32Mask); //***************************************************************************** extern void RFCRfTrimRead(rfc_radioOp_t* pOpSetup, rfTrim_t* rfTrim); - //***************************************************************************** // //! Write preloaded RF trim values directly into CPE. @@ -395,7 +370,6 @@ extern void RFCRfTrimRead(rfc_radioOp_t* pOpSetup, rfTrim_t* rfTrim); //***************************************************************************** extern void RFCRfTrimSet(rfTrim_t* rfTrim); - //***************************************************************************** // //! Check Override RTrim vs FCFG RTrim. @@ -403,7 +377,6 @@ extern void RFCRfTrimSet(rfTrim_t* rfTrim); //***************************************************************************** extern uint8_t RFCRTrim(rfc_radioOp_t* pOpSetup); - //***************************************************************************** // //! Function to set VCOLDO reference to voltage mode. @@ -420,48 +393,48 @@ extern void RFCAdi3VcoLdoVoltageMode(bool bEnable); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_RFCCpeIntGetAndClear -#undef RFCCpeIntGetAndClear -#define RFCCpeIntGetAndClear ROM_RFCCpeIntGetAndClear +#undef RFCCpeIntGetAndClear +#define RFCCpeIntGetAndClear ROM_RFCCpeIntGetAndClear #endif #ifdef ROM_RFCDoorbellSendTo -#undef RFCDoorbellSendTo -#define RFCDoorbellSendTo ROM_RFCDoorbellSendTo +#undef RFCDoorbellSendTo +#define RFCDoorbellSendTo ROM_RFCDoorbellSendTo #endif #ifdef ROM_RFCSynthPowerDown -#undef RFCSynthPowerDown -#define RFCSynthPowerDown ROM_RFCSynthPowerDown +#undef RFCSynthPowerDown +#define RFCSynthPowerDown ROM_RFCSynthPowerDown #endif #ifdef ROM_RFCCpePatchReset -#undef RFCCpePatchReset -#define RFCCpePatchReset ROM_RFCCpePatchReset +#undef RFCCpePatchReset +#define RFCCpePatchReset ROM_RFCCpePatchReset #endif #ifdef ROM_RFCOverrideSearch -#undef RFCOverrideSearch -#define RFCOverrideSearch ROM_RFCOverrideSearch +#undef RFCOverrideSearch +#define RFCOverrideSearch ROM_RFCOverrideSearch #endif #ifdef ROM_RFCOverrideUpdate -#undef RFCOverrideUpdate -#define RFCOverrideUpdate ROM_RFCOverrideUpdate +#undef RFCOverrideUpdate +#define RFCOverrideUpdate ROM_RFCOverrideUpdate #endif #ifdef ROM_RFCHwIntGetAndClear -#undef RFCHwIntGetAndClear -#define RFCHwIntGetAndClear ROM_RFCHwIntGetAndClear +#undef RFCHwIntGetAndClear +#define RFCHwIntGetAndClear ROM_RFCHwIntGetAndClear #endif #ifdef ROM_RFCRfTrimRead -#undef RFCRfTrimRead -#define RFCRfTrimRead ROM_RFCRfTrimRead +#undef RFCRfTrimRead +#define RFCRfTrimRead ROM_RFCRfTrimRead #endif #ifdef ROM_RFCRfTrimSet -#undef RFCRfTrimSet -#define RFCRfTrimSet ROM_RFCRfTrimSet +#undef RFCRfTrimSet +#define RFCRfTrimSet ROM_RFCRfTrimSet #endif #ifdef ROM_RFCRTrim -#undef RFCRTrim -#define RFCRTrim ROM_RFCRTrim +#undef RFCRTrim +#define RFCRTrim ROM_RFCRTrim #endif #ifdef ROM_RFCAdi3VcoLdoVoltageMode -#undef RFCAdi3VcoLdoVoltageMode -#define RFCAdi3VcoLdoVoltageMode ROM_RFCAdi3VcoLdoVoltageMode +#undef RFCAdi3VcoLdoVoltageMode +#define RFCAdi3VcoLdoVoltageMode ROM_RFCAdi3VcoLdoVoltageMode #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rom.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rom.h index ac2061f..75302de 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rom.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rom.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rom.h -* Revised: 2018-11-02 13:54:49 +0100 (Fri, 02 Nov 2018) -* Revision: 53196 -* -* Description: Prototypes for the ROM utility functions. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rom.h + * Revised: 2018-11-02 13:54:49 +0100 (Fri, 02 Nov 2018) + * Revision: 53196 + * + * Description: Prototypes for the ROM utility functions. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __ROM_H__ #define __ROM_H__ @@ -46,8 +46,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include "../inc/hw_types.h" @@ -59,183 +58,183 @@ extern "C" #define ROM_HAPI_TABLE_ADDR 0x10000048 // ROM Hard-API function interface types -typedef uint32_t (* FPTR_CRC32_T) ( uint8_t* /* pui8Data */, \ - uint32_t /* ui32ByteCount */, \ - uint32_t /* ui32RepeatCount */); +typedef uint32_t (*FPTR_CRC32_T)(uint8_t* /* pui8Data */, + uint32_t /* ui32ByteCount */, + uint32_t /* ui32RepeatCount */); -typedef uint32_t (* FPTR_GETFLSIZE_T) ( void ); +typedef uint32_t (*FPTR_GETFLSIZE_T)(void); -typedef uint32_t (* FPTR_GETCHIPID_T) ( void ); +typedef uint32_t (*FPTR_GETCHIPID_T)(void); -typedef uint32_t (* FPTR_RESERVED1_T) ( uint32_t ); +typedef uint32_t (*FPTR_RESERVED1_T)(uint32_t); -typedef uint32_t (* FPTR_RESERVED2_T) ( void ); +typedef uint32_t (*FPTR_RESERVED2_T)(void); -typedef uint32_t (* FPTR_RESERVED3_T) ( uint8_t*, \ - uint32_t, \ - uint32_t ); -typedef void (* FPTR_RESETDEV_T) ( void ); +typedef uint32_t (*FPTR_RESERVED3_T)(uint8_t*, + uint32_t, + uint32_t); +typedef void (*FPTR_RESETDEV_T)(void); -typedef uint32_t (* FPTR_FLETCHER32_T) ( uint16_t* /* pui16Data */, \ - uint16_t /* ui16WordCount */, \ - uint16_t /* ui16RepeatCount */); +typedef uint32_t (*FPTR_FLETCHER32_T)(uint16_t* /* pui16Data */, + uint16_t /* ui16WordCount */, + uint16_t /* ui16RepeatCount */); -typedef uint32_t (* FPTR_MINVAL_T) ( uint32_t* /* ulpDataBuffer */, \ - uint32_t /* ui32DataCount */); +typedef uint32_t (*FPTR_MINVAL_T)(uint32_t* /* ulpDataBuffer */, + uint32_t /* ui32DataCount */); -typedef uint32_t (* FPTR_MAXVAL_T) ( uint32_t* /* pui32DataBuffer */, \ - uint32_t /* ui32DataCount */); +typedef uint32_t (*FPTR_MAXVAL_T)(uint32_t* /* pui32DataBuffer */, + uint32_t /* ui32DataCount */); -typedef uint32_t (* FPTR_MEANVAL_T) ( uint32_t* /* pui32DataBuffer */, \ - uint32_t /* ui32DataCount */); +typedef uint32_t (*FPTR_MEANVAL_T)(uint32_t* /* pui32DataBuffer */, + uint32_t /* ui32DataCount */); -typedef uint32_t (* FPTR_STDDVAL_T) ( uint32_t* /* pui32DataBuffer */, \ - uint32_t /* ui32DataCount */); +typedef uint32_t (*FPTR_STDDVAL_T)(uint32_t* /* pui32DataBuffer */, + uint32_t /* ui32DataCount */); -typedef void (* FPTR_HFSOURCESAFESWITCH_T) ( void ); +typedef void (*FPTR_HFSOURCESAFESWITCH_T)(void); -typedef void (* FPTR_RESERVED4_T) ( uint32_t ); +typedef void (*FPTR_RESERVED4_T)(uint32_t); -typedef void (* FPTR_RESERVED5_T) ( uint32_t ); +typedef void (*FPTR_RESERVED5_T)(uint32_t); -typedef void (* FPTR_COMPAIN_T) ( uint8_t /* ut8Signal */); +typedef void (*FPTR_COMPAIN_T)(uint8_t /* ut8Signal */); -typedef void (* FPTR_COMPAREF_T) ( uint8_t /* ut8Signal */); +typedef void (*FPTR_COMPAREF_T)(uint8_t /* ut8Signal */); -typedef void (* FPTR_ADCCOMPBIN_T) ( uint8_t /* ut8Signal */); +typedef void (*FPTR_ADCCOMPBIN_T)(uint8_t /* ut8Signal */); -typedef void (* FPTR_COMPBREF_T) ( uint8_t /* ut8Signal */); +typedef void (*FPTR_COMPBREF_T)(uint8_t /* ut8Signal */); extern uint32_t MemBusWrkAroundHapiProgramFlash(uint8_t* pui8DataBuffer, - uint32_t ui32Address, - uint32_t ui32Count); + uint32_t ui32Address, + uint32_t ui32Count); extern uint32_t MemBusWrkAroundHapiEraseSector(uint32_t ui32Address); // ROM Hard-API access table type typedef struct { - FPTR_CRC32_T Crc32; - FPTR_GETFLSIZE_T FlashGetSize; - FPTR_GETCHIPID_T GetChipId; - FPTR_RESERVED1_T ReservedLocation1; - FPTR_RESERVED2_T ReservedLocation2; - FPTR_RESERVED3_T ReservedLocation3; - FPTR_RESETDEV_T ResetDevice; - FPTR_FLETCHER32_T Fletcher32; - FPTR_MINVAL_T MinValue; - FPTR_MAXVAL_T MaxValue; - FPTR_MEANVAL_T MeanValue; - FPTR_STDDVAL_T StandDeviationValue; - FPTR_RESERVED4_T ReservedLocation4; - FPTR_RESERVED5_T ReservedLocation5; - FPTR_HFSOURCESAFESWITCH_T HFSourceSafeSwitch; - FPTR_COMPAIN_T SelectCompAInput; - FPTR_COMPAREF_T SelectCompARef; - FPTR_ADCCOMPBIN_T SelectADCCompBInput; - FPTR_COMPBREF_T SelectCompBRef; + FPTR_CRC32_T Crc32; + FPTR_GETFLSIZE_T FlashGetSize; + FPTR_GETCHIPID_T GetChipId; + FPTR_RESERVED1_T ReservedLocation1; + FPTR_RESERVED2_T ReservedLocation2; + FPTR_RESERVED3_T ReservedLocation3; + FPTR_RESETDEV_T ResetDevice; + FPTR_FLETCHER32_T Fletcher32; + FPTR_MINVAL_T MinValue; + FPTR_MAXVAL_T MaxValue; + FPTR_MEANVAL_T MeanValue; + FPTR_STDDVAL_T StandDeviationValue; + FPTR_RESERVED4_T ReservedLocation4; + FPTR_RESERVED5_T ReservedLocation5; + FPTR_HFSOURCESAFESWITCH_T HFSourceSafeSwitch; + FPTR_COMPAIN_T SelectCompAInput; + FPTR_COMPAREF_T SelectCompARef; + FPTR_ADCCOMPBIN_T SelectADCCompBInput; + FPTR_COMPBREF_T SelectCompBRef; } HARD_API_T; // Pointer to the ROM HAPI table -#define P_HARD_API ((HARD_API_T*) ROM_HAPI_TABLE_ADDR) +#define P_HARD_API ((HARD_API_T*)ROM_HAPI_TABLE_ADDR) // Add wrapper around the Hapi functions needing the "bus arbitration issue" workaround -extern void SafeHapiVoid( FPTR_VOID_VOID_T fPtr ); -extern void SafeHapiAuxAdiSelect( FPTR_VOID_UINT8_T fPtr, uint8_t ut8Signal ); +extern void SafeHapiVoid(FPTR_VOID_VOID_T fPtr); +extern void SafeHapiAuxAdiSelect(FPTR_VOID_UINT8_T fPtr, uint8_t ut8Signal); -#define HapiCrc32(a,b,c) P_HARD_API->Crc32(a,b,c) -#define HapiGetFlashSize() P_HARD_API->FlashGetSize() -#define HapiGetChipId() P_HARD_API->GetChipId() -#define HapiSectorErase(a) MemBusWrkAroundHapiEraseSector(a) -#define HapiProgramFlash(a,b,c) MemBusWrkAroundHapiProgramFlash(a,b,c) -#define HapiResetDevice() P_HARD_API->ResetDevice() -#define HapiFletcher32(a,b,c) P_HARD_API->Fletcher32(a,b,c) -#define HapiMinValue(a,b) P_HARD_API->MinValue(a,b) -#define HapiMaxValue(a,b) P_HARD_API->MaxValue(a,b) -#define HapiMeanValue(a,b) P_HARD_API->MeanValue(a,b) -#define HapiStandDeviationValue(a,b) P_HARD_API->StandDeviationValue(a,b) -#define HapiHFSourceSafeSwitch() SafeHapiVoid( P_HARD_API->HFSourceSafeSwitch ) -#define HapiSelectCompAInput(a) SafeHapiAuxAdiSelect( P_HARD_API->SelectCompAInput , a ) -#define HapiSelectCompARef(a) SafeHapiAuxAdiSelect( P_HARD_API->SelectCompARef , a ) -#define HapiSelectADCCompBInput(a) SafeHapiAuxAdiSelect( P_HARD_API->SelectADCCompBInput, a ) -#define HapiSelectCompBRef(a) SafeHapiAuxAdiSelect( P_HARD_API->SelectCompBRef , a ) +#define HapiCrc32(a, b, c) P_HARD_API->Crc32(a, b, c) +#define HapiGetFlashSize() P_HARD_API->FlashGetSize() +#define HapiGetChipId() P_HARD_API->GetChipId() +#define HapiSectorErase(a) MemBusWrkAroundHapiEraseSector(a) +#define HapiProgramFlash(a, b, c) MemBusWrkAroundHapiProgramFlash(a, b, c) +#define HapiResetDevice() P_HARD_API->ResetDevice() +#define HapiFletcher32(a, b, c) P_HARD_API->Fletcher32(a, b, c) +#define HapiMinValue(a, b) P_HARD_API->MinValue(a, b) +#define HapiMaxValue(a, b) P_HARD_API->MaxValue(a, b) +#define HapiMeanValue(a, b) P_HARD_API->MeanValue(a, b) +#define HapiStandDeviationValue(a, b) P_HARD_API->StandDeviationValue(a, b) +#define HapiHFSourceSafeSwitch() SafeHapiVoid(P_HARD_API->HFSourceSafeSwitch) +#define HapiSelectCompAInput(a) SafeHapiAuxAdiSelect(P_HARD_API->SelectCompAInput, a) +#define HapiSelectCompARef(a) SafeHapiAuxAdiSelect(P_HARD_API->SelectCompARef, a) +#define HapiSelectADCCompBInput(a) SafeHapiAuxAdiSelect(P_HARD_API->SelectADCCompBInput, a) +#define HapiSelectCompBRef(a) SafeHapiAuxAdiSelect(P_HARD_API->SelectCompBRef, a) // Defines for input parameter to the HapiSelectCompAInput function. -#define COMPA_IN_NC 0x00 +#define COMPA_IN_NC 0x00 // Defines used in CC13x0/CC26x0 devices -#define COMPA_IN_AUXIO7 0x09 -#define COMPA_IN_AUXIO6 0x0A -#define COMPA_IN_AUXIO5 0x0B -#define COMPA_IN_AUXIO4 0x0C -#define COMPA_IN_AUXIO3 0x0D -#define COMPA_IN_AUXIO2 0x0E -#define COMPA_IN_AUXIO1 0x0F -#define COMPA_IN_AUXIO0 0x10 +#define COMPA_IN_AUXIO7 0x09 +#define COMPA_IN_AUXIO6 0x0A +#define COMPA_IN_AUXIO5 0x0B +#define COMPA_IN_AUXIO4 0x0C +#define COMPA_IN_AUXIO3 0x0D +#define COMPA_IN_AUXIO2 0x0E +#define COMPA_IN_AUXIO1 0x0F +#define COMPA_IN_AUXIO0 0x10 // Defines used in CC13x2/CC26x2 devices -#define COMPA_IN_AUXIO26 COMPA_IN_AUXIO7 -#define COMPA_IN_AUXIO25 COMPA_IN_AUXIO6 -#define COMPA_IN_AUXIO24 COMPA_IN_AUXIO5 -#define COMPA_IN_AUXIO23 COMPA_IN_AUXIO4 -#define COMPA_IN_AUXIO22 COMPA_IN_AUXIO3 -#define COMPA_IN_AUXIO21 COMPA_IN_AUXIO2 -#define COMPA_IN_AUXIO20 COMPA_IN_AUXIO1 -#define COMPA_IN_AUXIO19 COMPA_IN_AUXIO0 +#define COMPA_IN_AUXIO26 COMPA_IN_AUXIO7 +#define COMPA_IN_AUXIO25 COMPA_IN_AUXIO6 +#define COMPA_IN_AUXIO24 COMPA_IN_AUXIO5 +#define COMPA_IN_AUXIO23 COMPA_IN_AUXIO4 +#define COMPA_IN_AUXIO22 COMPA_IN_AUXIO3 +#define COMPA_IN_AUXIO21 COMPA_IN_AUXIO2 +#define COMPA_IN_AUXIO20 COMPA_IN_AUXIO1 +#define COMPA_IN_AUXIO19 COMPA_IN_AUXIO0 // Defines for input parameter to the HapiSelectCompARef function. -#define COMPA_REF_NC 0x00 -#define COMPA_REF_DCOUPL 0x01 -#define COMPA_REF_VSS 0x02 -#define COMPA_REF_VDDS 0x03 -#define COMPA_REF_ADCVREFP 0x04 +#define COMPA_REF_NC 0x00 +#define COMPA_REF_DCOUPL 0x01 +#define COMPA_REF_VSS 0x02 +#define COMPA_REF_VDDS 0x03 +#define COMPA_REF_ADCVREFP 0x04 // Defines used in CC13x0/CC26x0 devices -#define COMPA_REF_AUXIO7 0x09 -#define COMPA_REF_AUXIO6 0x0A -#define COMPA_REF_AUXIO5 0x0B -#define COMPA_REF_AUXIO4 0x0C -#define COMPA_REF_AUXIO3 0x0D -#define COMPA_REF_AUXIO2 0x0E -#define COMPA_REF_AUXIO1 0x0F -#define COMPA_REF_AUXIO0 0x10 +#define COMPA_REF_AUXIO7 0x09 +#define COMPA_REF_AUXIO6 0x0A +#define COMPA_REF_AUXIO5 0x0B +#define COMPA_REF_AUXIO4 0x0C +#define COMPA_REF_AUXIO3 0x0D +#define COMPA_REF_AUXIO2 0x0E +#define COMPA_REF_AUXIO1 0x0F +#define COMPA_REF_AUXIO0 0x10 // Defines used in CC13x2/CC26x2 devices -#define COMPA_REF_AUXIO26 COMPA_REF_AUXIO7 -#define COMPA_REF_AUXIO25 COMPA_REF_AUXIO6 -#define COMPA_REF_AUXIO24 COMPA_REF_AUXIO5 -#define COMPA_REF_AUXIO23 COMPA_REF_AUXIO4 -#define COMPA_REF_AUXIO22 COMPA_REF_AUXIO3 -#define COMPA_REF_AUXIO21 COMPA_REF_AUXIO2 -#define COMPA_REF_AUXIO20 COMPA_REF_AUXIO1 -#define COMPA_REF_AUXIO19 COMPA_REF_AUXIO0 +#define COMPA_REF_AUXIO26 COMPA_REF_AUXIO7 +#define COMPA_REF_AUXIO25 COMPA_REF_AUXIO6 +#define COMPA_REF_AUXIO24 COMPA_REF_AUXIO5 +#define COMPA_REF_AUXIO23 COMPA_REF_AUXIO4 +#define COMPA_REF_AUXIO22 COMPA_REF_AUXIO3 +#define COMPA_REF_AUXIO21 COMPA_REF_AUXIO2 +#define COMPA_REF_AUXIO20 COMPA_REF_AUXIO1 +#define COMPA_REF_AUXIO19 COMPA_REF_AUXIO0 // Defines for input parameter to the HapiSelectADCCompBInput function. -#define ADC_COMPB_IN_NC 0x00 -#define ADC_COMPB_IN_DCOUPL 0x03 -#define ADC_COMPB_IN_VSS 0x04 -#define ADC_COMPB_IN_VDDS 0x05 +#define ADC_COMPB_IN_NC 0x00 +#define ADC_COMPB_IN_DCOUPL 0x03 +#define ADC_COMPB_IN_VSS 0x04 +#define ADC_COMPB_IN_VDDS 0x05 // Defines used in CC13x0/CC26x0 devices -#define ADC_COMPB_IN_AUXIO7 0x09 -#define ADC_COMPB_IN_AUXIO6 0x0A -#define ADC_COMPB_IN_AUXIO5 0x0B -#define ADC_COMPB_IN_AUXIO4 0x0C -#define ADC_COMPB_IN_AUXIO3 0x0D -#define ADC_COMPB_IN_AUXIO2 0x0E -#define ADC_COMPB_IN_AUXIO1 0x0F -#define ADC_COMPB_IN_AUXIO0 0x10 +#define ADC_COMPB_IN_AUXIO7 0x09 +#define ADC_COMPB_IN_AUXIO6 0x0A +#define ADC_COMPB_IN_AUXIO5 0x0B +#define ADC_COMPB_IN_AUXIO4 0x0C +#define ADC_COMPB_IN_AUXIO3 0x0D +#define ADC_COMPB_IN_AUXIO2 0x0E +#define ADC_COMPB_IN_AUXIO1 0x0F +#define ADC_COMPB_IN_AUXIO0 0x10 // Defines used in CC13x2/CC26x2 devices -#define ADC_COMPB_IN_AUXIO26 ADC_COMPB_IN_AUXIO7 -#define ADC_COMPB_IN_AUXIO25 ADC_COMPB_IN_AUXIO6 -#define ADC_COMPB_IN_AUXIO24 ADC_COMPB_IN_AUXIO5 -#define ADC_COMPB_IN_AUXIO23 ADC_COMPB_IN_AUXIO4 -#define ADC_COMPB_IN_AUXIO22 ADC_COMPB_IN_AUXIO3 -#define ADC_COMPB_IN_AUXIO21 ADC_COMPB_IN_AUXIO2 -#define ADC_COMPB_IN_AUXIO20 ADC_COMPB_IN_AUXIO1 -#define ADC_COMPB_IN_AUXIO19 ADC_COMPB_IN_AUXIO0 +#define ADC_COMPB_IN_AUXIO26 ADC_COMPB_IN_AUXIO7 +#define ADC_COMPB_IN_AUXIO25 ADC_COMPB_IN_AUXIO6 +#define ADC_COMPB_IN_AUXIO24 ADC_COMPB_IN_AUXIO5 +#define ADC_COMPB_IN_AUXIO23 ADC_COMPB_IN_AUXIO4 +#define ADC_COMPB_IN_AUXIO22 ADC_COMPB_IN_AUXIO3 +#define ADC_COMPB_IN_AUXIO21 ADC_COMPB_IN_AUXIO2 +#define ADC_COMPB_IN_AUXIO20 ADC_COMPB_IN_AUXIO1 +#define ADC_COMPB_IN_AUXIO19 ADC_COMPB_IN_AUXIO0 // Defines for input parameter to the HapiSelectCompBRef function. // The define values can not be changed! -#define COMPB_REF_NC 0x00 -#define COMPB_REF_DCOUPL 0x01 -#define COMPB_REF_VSS 0x02 -#define COMPB_REF_VDDS 0x03 +#define COMPB_REF_NC 0x00 +#define COMPB_REF_DCOUPL 0x01 +#define COMPB_REF_VSS 0x02 +#define COMPB_REF_VDDS 0x03 #endif // __HAPI_H__ @@ -244,436 +243,418 @@ extern void SafeHapiAuxAdiSelect( FPTR_VOID_UINT8_T fPtr, uint8_t ut8Signal ); // Pointers to the main API tables. // //***************************************************************************** -#define ROM_API_TABLE ((uint32_t *) 0x10000180) -#define ROM_VERSION (ROM_API_TABLE[0]) +#define ROM_API_TABLE ((uint32_t*)0x10000180) +#define ROM_VERSION (ROM_API_TABLE[0]) - -#define ROM_API_AON_EVENT_TABLE ((uint32_t*) (ROM_API_TABLE[1])) -#define ROM_API_AON_IOC_TABLE ((uint32_t*) (ROM_API_TABLE[2])) -#define ROM_API_AON_RTC_TABLE ((uint32_t*) (ROM_API_TABLE[3])) -#define ROM_API_AON_WUC_TABLE ((uint32_t*) (ROM_API_TABLE[4])) -#define ROM_API_AUX_CTRL_TABLE ((uint32_t*) (ROM_API_TABLE[5])) -#define ROM_API_AUX_TDC_TABLE ((uint32_t*) (ROM_API_TABLE[6])) -#define ROM_API_AUX_TIMER_TABLE ((uint32_t*) (ROM_API_TABLE[7])) -#define ROM_API_AUX_WUC_TABLE ((uint32_t*) (ROM_API_TABLE[8])) -#define ROM_API_DDI_TABLE ((uint32_t*) (ROM_API_TABLE[9])) -#define ROM_API_FLASH_TABLE ((uint32_t*) (ROM_API_TABLE[10])) -#define ROM_API_I2C_TABLE ((uint32_t*) (ROM_API_TABLE[11])) -#define ROM_API_INTERRUPT_TABLE ((uint32_t*) (ROM_API_TABLE[12])) -#define ROM_API_IOC_TABLE ((uint32_t*) (ROM_API_TABLE[13])) -#define ROM_API_PRCM_TABLE ((uint32_t*) (ROM_API_TABLE[14])) -#define ROM_API_SMPH_TABLE ((uint32_t*) (ROM_API_TABLE[15])) -#define ROM_API_SSI_TABLE ((uint32_t*) (ROM_API_TABLE[17])) -#define ROM_API_TIMER_TABLE ((uint32_t*) (ROM_API_TABLE[18])) -#define ROM_API_TRNG_TABLE ((uint32_t*) (ROM_API_TABLE[19])) -#define ROM_API_UART_TABLE ((uint32_t*) (ROM_API_TABLE[20])) -#define ROM_API_UDMA_TABLE ((uint32_t*) (ROM_API_TABLE[21])) -#define ROM_API_VIMS_TABLE ((uint32_t*) (ROM_API_TABLE[22])) +#define ROM_API_AON_EVENT_TABLE ((uint32_t*)(ROM_API_TABLE[1])) +#define ROM_API_AON_IOC_TABLE ((uint32_t*)(ROM_API_TABLE[2])) +#define ROM_API_AON_RTC_TABLE ((uint32_t*)(ROM_API_TABLE[3])) +#define ROM_API_AON_WUC_TABLE ((uint32_t*)(ROM_API_TABLE[4])) +#define ROM_API_AUX_CTRL_TABLE ((uint32_t*)(ROM_API_TABLE[5])) +#define ROM_API_AUX_TDC_TABLE ((uint32_t*)(ROM_API_TABLE[6])) +#define ROM_API_AUX_TIMER_TABLE ((uint32_t*)(ROM_API_TABLE[7])) +#define ROM_API_AUX_WUC_TABLE ((uint32_t*)(ROM_API_TABLE[8])) +#define ROM_API_DDI_TABLE ((uint32_t*)(ROM_API_TABLE[9])) +#define ROM_API_FLASH_TABLE ((uint32_t*)(ROM_API_TABLE[10])) +#define ROM_API_I2C_TABLE ((uint32_t*)(ROM_API_TABLE[11])) +#define ROM_API_INTERRUPT_TABLE ((uint32_t*)(ROM_API_TABLE[12])) +#define ROM_API_IOC_TABLE ((uint32_t*)(ROM_API_TABLE[13])) +#define ROM_API_PRCM_TABLE ((uint32_t*)(ROM_API_TABLE[14])) +#define ROM_API_SMPH_TABLE ((uint32_t*)(ROM_API_TABLE[15])) +#define ROM_API_SSI_TABLE ((uint32_t*)(ROM_API_TABLE[17])) +#define ROM_API_TIMER_TABLE ((uint32_t*)(ROM_API_TABLE[18])) +#define ROM_API_TRNG_TABLE ((uint32_t*)(ROM_API_TABLE[19])) +#define ROM_API_UART_TABLE ((uint32_t*)(ROM_API_TABLE[20])) +#define ROM_API_UDMA_TABLE ((uint32_t*)(ROM_API_TABLE[21])) +#define ROM_API_VIMS_TABLE ((uint32_t*)(ROM_API_TABLE[22])) // AON_EVENT FUNCTIONS -#define ROM_AONEventMcuWakeUpSet \ +#define ROM_AONEventMcuWakeUpSet \ ((void (*)(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc)) \ - ROM_API_AON_EVENT_TABLE[0]) + ROM_API_AON_EVENT_TABLE[0]) -#define ROM_AONEventMcuWakeUpGet \ - ((uint32_t (*)(uint32_t ui32MCUWUEvent)) \ - ROM_API_AON_EVENT_TABLE[1]) +#define ROM_AONEventMcuWakeUpGet \ + ((uint32_t(*)(uint32_t ui32MCUWUEvent)) \ + ROM_API_AON_EVENT_TABLE[1]) -#define ROM_AONEventAuxWakeUpSet \ +#define ROM_AONEventAuxWakeUpSet \ ((void (*)(uint32_t ui32AUXWUEvent, uint32_t ui32EventSrc)) \ - ROM_API_AON_EVENT_TABLE[2]) + ROM_API_AON_EVENT_TABLE[2]) -#define ROM_AONEventAuxWakeUpGet \ - ((uint32_t (*)(uint32_t ui32AUXWUEvent)) \ - ROM_API_AON_EVENT_TABLE[3]) +#define ROM_AONEventAuxWakeUpGet \ + ((uint32_t(*)(uint32_t ui32AUXWUEvent)) \ + ROM_API_AON_EVENT_TABLE[3]) -#define ROM_AONEventMcuSet \ +#define ROM_AONEventMcuSet \ ((void (*)(uint32_t ui32MCUEvent, uint32_t ui32EventSrc)) \ - ROM_API_AON_EVENT_TABLE[4]) - -#define ROM_AONEventMcuGet \ - ((uint32_t (*)(uint32_t ui32MCUEvent)) \ - ROM_API_AON_EVENT_TABLE[5]) + ROM_API_AON_EVENT_TABLE[4]) +#define ROM_AONEventMcuGet \ + ((uint32_t(*)(uint32_t ui32MCUEvent)) \ + ROM_API_AON_EVENT_TABLE[5]) // AON_WUC FUNCTIONS #define ROM_AONWUCAuxReset \ - ((void (*)(void)) \ - ROM_API_AON_WUC_TABLE[3]) + ((void (*)(void)) \ + ROM_API_AON_WUC_TABLE[3]) -#define ROM_AONWUCRechargeCtrlConfigSet \ +#define ROM_AONWUCRechargeCtrlConfigSet \ ((void (*)(bool bAdaptEnable, uint32_t ui32AdaptRate, uint32_t ui32Period, uint32_t ui32MaxPeriod)) \ - ROM_API_AON_WUC_TABLE[4]) + ROM_API_AON_WUC_TABLE[4]) -#define ROM_AONWUCOscConfig \ +#define ROM_AONWUCOscConfig \ ((void (*)(uint32_t ui32Period)) \ - ROM_API_AON_WUC_TABLE[5]) - + ROM_API_AON_WUC_TABLE[5]) // AUX_TDC FUNCTIONS -#define ROM_AUXTDCConfigSet \ +#define ROM_AUXTDCConfigSet \ ((void (*)(uint32_t ui32Base, uint32_t ui32StartCondition, uint32_t ui32StopCondition)) \ - ROM_API_AUX_TDC_TABLE[0]) - -#define ROM_AUXTDCMeasurementDone \ - ((uint32_t (*)(uint32_t ui32Base)) \ - ROM_API_AUX_TDC_TABLE[1]) + ROM_API_AUX_TDC_TABLE[0]) +#define ROM_AUXTDCMeasurementDone \ + ((uint32_t(*)(uint32_t ui32Base)) \ + ROM_API_AUX_TDC_TABLE[1]) // AUX_WUC FUNCTIONS -#define ROM_AUXWUCClockEnable \ +#define ROM_AUXWUCClockEnable \ ((void (*)(uint32_t ui32Clocks)) \ - ROM_API_AUX_WUC_TABLE[0]) + ROM_API_AUX_WUC_TABLE[0]) -#define ROM_AUXWUCClockDisable \ +#define ROM_AUXWUCClockDisable \ ((void (*)(uint32_t ui32Clocks)) \ - ROM_API_AUX_WUC_TABLE[1]) + ROM_API_AUX_WUC_TABLE[1]) -#define ROM_AUXWUCClockStatus \ - ((uint32_t (*)(uint32_t ui32Clocks)) \ - ROM_API_AUX_WUC_TABLE[2]) +#define ROM_AUXWUCClockStatus \ + ((uint32_t(*)(uint32_t ui32Clocks)) \ + ROM_API_AUX_WUC_TABLE[2]) -#define ROM_AUXWUCPowerCtrl \ +#define ROM_AUXWUCPowerCtrl \ ((void (*)(uint32_t ui32PowerMode)) \ - ROM_API_AUX_WUC_TABLE[3]) - + ROM_API_AUX_WUC_TABLE[3]) // FLASH FUNCTIONS #define ROM_FlashPowerModeGet \ - ((uint32_t (*)(void)) \ - ROM_API_FLASH_TABLE[1]) + ((uint32_t(*)(void)) \ + ROM_API_FLASH_TABLE[1]) -#define ROM_FlashProtectionSet \ +#define ROM_FlashProtectionSet \ ((void (*)(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode)) \ - ROM_API_FLASH_TABLE[2]) + ROM_API_FLASH_TABLE[2]) -#define ROM_FlashProtectionGet \ - ((uint32_t (*)(uint32_t ui32SectorAddress)) \ - ROM_API_FLASH_TABLE[3]) +#define ROM_FlashProtectionGet \ + ((uint32_t(*)(uint32_t ui32SectorAddress)) \ + ROM_API_FLASH_TABLE[3]) -#define ROM_FlashProtectionSave \ - ((uint32_t (*)(uint32_t ui32SectorAddress)) \ - ROM_API_FLASH_TABLE[4]) +#define ROM_FlashProtectionSave \ + ((uint32_t(*)(uint32_t ui32SectorAddress)) \ + ROM_API_FLASH_TABLE[4]) -#define ROM_FlashEfuseReadRow \ - ((bool (*)(uint32_t *pui32EfuseData, uint32_t ui32RowAddress)) \ - ROM_API_FLASH_TABLE[8]) +#define ROM_FlashEfuseReadRow \ + ((bool (*)(uint32_t * pui32EfuseData, uint32_t ui32RowAddress)) \ + ROM_API_FLASH_TABLE[8]) #define ROM_FlashDisableSectorsForWrite \ - ((void (*)(void)) \ - ROM_API_FLASH_TABLE[9]) - + ((void (*)(void)) \ + ROM_API_FLASH_TABLE[9]) // I2C FUNCTIONS -#define ROM_I2CMasterInitExpClk \ +#define ROM_I2CMasterInitExpClk \ ((void (*)(uint32_t ui32Base, uint32_t ui32I2CClk, bool bFast)) \ - ROM_API_I2C_TABLE[0]) - -#define ROM_I2CMasterErr \ - ((uint32_t (*)(uint32_t ui32Base)) \ - ROM_API_I2C_TABLE[1]) + ROM_API_I2C_TABLE[0]) +#define ROM_I2CMasterErr \ + ((uint32_t(*)(uint32_t ui32Base)) \ + ROM_API_I2C_TABLE[1]) // INTERRUPT FUNCTIONS #define ROM_IntPriorityGroupingSet \ ((void (*)(uint32_t ui32Bits)) \ - ROM_API_INTERRUPT_TABLE[0]) + ROM_API_INTERRUPT_TABLE[0]) #define ROM_IntPriorityGroupingGet \ - ((uint32_t (*)(void)) \ - ROM_API_INTERRUPT_TABLE[1]) + ((uint32_t(*)(void)) \ + ROM_API_INTERRUPT_TABLE[1]) -#define ROM_IntPrioritySet \ +#define ROM_IntPrioritySet \ ((void (*)(uint32_t ui32Interrupt, uint8_t ui8Priority)) \ - ROM_API_INTERRUPT_TABLE[2]) + ROM_API_INTERRUPT_TABLE[2]) -#define ROM_IntPriorityGet \ - ((int32_t (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[3]) +#define ROM_IntPriorityGet \ + ((int32_t(*)(uint32_t ui32Interrupt)) \ + ROM_API_INTERRUPT_TABLE[3]) -#define ROM_IntEnable \ +#define ROM_IntEnable \ ((void (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[4]) + ROM_API_INTERRUPT_TABLE[4]) -#define ROM_IntDisable \ +#define ROM_IntDisable \ ((void (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[5]) + ROM_API_INTERRUPT_TABLE[5]) -#define ROM_IntPendSet \ +#define ROM_IntPendSet \ ((void (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[6]) + ROM_API_INTERRUPT_TABLE[6]) -#define ROM_IntPendGet \ +#define ROM_IntPendGet \ ((bool (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[7]) + ROM_API_INTERRUPT_TABLE[7]) -#define ROM_IntPendClear \ +#define ROM_IntPendClear \ ((void (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[8]) - + ROM_API_INTERRUPT_TABLE[8]) // IOC FUNCTIONS -#define ROM_IOCPortConfigureSet \ +#define ROM_IOCPortConfigureSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId, uint32_t ui32IOConfig)) \ - ROM_API_IOC_TABLE[0]) + ROM_API_IOC_TABLE[0]) -#define ROM_IOCPortConfigureGet \ - ((uint32_t (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[1]) +#define ROM_IOCPortConfigureGet \ + ((uint32_t(*)(uint32_t ui32IOId)) \ + ROM_API_IOC_TABLE[1]) -#define ROM_IOCIOShutdownSet \ +#define ROM_IOCIOShutdownSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32IOShutdown)) \ - ROM_API_IOC_TABLE[2]) + ROM_API_IOC_TABLE[2]) -#define ROM_IOCIOModeSet \ +#define ROM_IOCIOModeSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32IOMode)) \ - ROM_API_IOC_TABLE[4]) + ROM_API_IOC_TABLE[4]) -#define ROM_IOCIOIntSet \ +#define ROM_IOCIOIntSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet)) \ - ROM_API_IOC_TABLE[5]) + ROM_API_IOC_TABLE[5]) -#define ROM_IOCIOPortPullSet \ +#define ROM_IOCIOPortPullSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32Pull)) \ - ROM_API_IOC_TABLE[6]) + ROM_API_IOC_TABLE[6]) -#define ROM_IOCIOHystSet \ +#define ROM_IOCIOHystSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32Hysteresis)) \ - ROM_API_IOC_TABLE[7]) + ROM_API_IOC_TABLE[7]) -#define ROM_IOCIOInputSet \ +#define ROM_IOCIOInputSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32Input)) \ - ROM_API_IOC_TABLE[8]) + ROM_API_IOC_TABLE[8]) -#define ROM_IOCIOSlewCtrlSet \ +#define ROM_IOCIOSlewCtrlSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32SlewEnable)) \ - ROM_API_IOC_TABLE[9]) + ROM_API_IOC_TABLE[9]) -#define ROM_IOCIODrvStrengthSet \ +#define ROM_IOCIODrvStrengthSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32IOCurrent, uint32_t ui32DrvStrength)) \ - ROM_API_IOC_TABLE[10]) + ROM_API_IOC_TABLE[10]) -#define ROM_IOCIOPortIdSet \ +#define ROM_IOCIOPortIdSet \ ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId)) \ - ROM_API_IOC_TABLE[11]) + ROM_API_IOC_TABLE[11]) -#define ROM_IOCIntEnable \ +#define ROM_IOCIntEnable \ ((void (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[12]) + ROM_API_IOC_TABLE[12]) -#define ROM_IOCIntDisable \ +#define ROM_IOCIntDisable \ ((void (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[13]) + ROM_API_IOC_TABLE[13]) -#define ROM_IOCPinTypeGpioInput \ +#define ROM_IOCPinTypeGpioInput \ ((void (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[14]) + ROM_API_IOC_TABLE[14]) -#define ROM_IOCPinTypeGpioOutput \ +#define ROM_IOCPinTypeGpioOutput \ ((void (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[15]) + ROM_API_IOC_TABLE[15]) -#define ROM_IOCPinTypeUart \ +#define ROM_IOCPinTypeUart \ ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Cts, uint32_t ui32Rts)) \ - ROM_API_IOC_TABLE[16]) + ROM_API_IOC_TABLE[16]) -#define ROM_IOCPinTypeSsiMaster \ +#define ROM_IOCPinTypeSsiMaster \ ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ - ROM_API_IOC_TABLE[17]) + ROM_API_IOC_TABLE[17]) -#define ROM_IOCPinTypeSsiSlave \ +#define ROM_IOCPinTypeSsiSlave \ ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ - ROM_API_IOC_TABLE[18]) + ROM_API_IOC_TABLE[18]) -#define ROM_IOCPinTypeI2c \ +#define ROM_IOCPinTypeI2c \ ((void (*)(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk)) \ - ROM_API_IOC_TABLE[19]) + ROM_API_IOC_TABLE[19]) -#define ROM_IOCPinTypeAux \ +#define ROM_IOCPinTypeAux \ ((void (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[21]) - + ROM_API_IOC_TABLE[21]) // PRCM FUNCTIONS -#define ROM_PRCMInfClockConfigureSet \ +#define ROM_PRCMInfClockConfigureSet \ ((void (*)(uint32_t ui32ClkDiv, uint32_t ui32PowerMode)) \ - ROM_API_PRCM_TABLE[0]) + ROM_API_PRCM_TABLE[0]) -#define ROM_PRCMInfClockConfigureGet \ - ((uint32_t (*)(uint32_t ui32PowerMode)) \ - ROM_API_PRCM_TABLE[1]) +#define ROM_PRCMInfClockConfigureGet \ + ((uint32_t(*)(uint32_t ui32PowerMode)) \ + ROM_API_PRCM_TABLE[1]) -#define ROM_PRCMAudioClockConfigSet \ +#define ROM_PRCMAudioClockConfigSet \ ((void (*)(uint32_t ui32ClkConfig, uint32_t ui32SampleRate)) \ - ROM_API_PRCM_TABLE[4]) + ROM_API_PRCM_TABLE[4]) -#define ROM_PRCMPowerDomainOn \ +#define ROM_PRCMPowerDomainOn \ ((void (*)(uint32_t ui32Domains)) \ - ROM_API_PRCM_TABLE[5]) + ROM_API_PRCM_TABLE[5]) -#define ROM_PRCMPowerDomainOff \ +#define ROM_PRCMPowerDomainOff \ ((void (*)(uint32_t ui32Domains)) \ - ROM_API_PRCM_TABLE[6]) + ROM_API_PRCM_TABLE[6]) -#define ROM_PRCMPeripheralRunEnable \ +#define ROM_PRCMPeripheralRunEnable \ ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[7]) + ROM_API_PRCM_TABLE[7]) -#define ROM_PRCMPeripheralRunDisable \ +#define ROM_PRCMPeripheralRunDisable \ ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[8]) + ROM_API_PRCM_TABLE[8]) -#define ROM_PRCMPeripheralSleepEnable \ +#define ROM_PRCMPeripheralSleepEnable \ ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[9]) + ROM_API_PRCM_TABLE[9]) -#define ROM_PRCMPeripheralSleepDisable \ +#define ROM_PRCMPeripheralSleepDisable \ ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[10]) + ROM_API_PRCM_TABLE[10]) #define ROM_PRCMPeripheralDeepSleepEnable \ - ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[11]) + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[11]) #define ROM_PRCMPeripheralDeepSleepDisable \ - ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[12]) + ((void (*)(uint32_t ui32Peripheral)) \ + ROM_API_PRCM_TABLE[12]) -#define ROM_PRCMPowerDomainStatus \ - ((uint32_t (*)(uint32_t ui32Domains)) \ - ROM_API_PRCM_TABLE[13]) +#define ROM_PRCMPowerDomainStatus \ + ((uint32_t(*)(uint32_t ui32Domains)) \ + ROM_API_PRCM_TABLE[13]) #define ROM_PRCMDeepSleep \ - ((void (*)(void)) \ - ROM_API_PRCM_TABLE[14]) - + ((void (*)(void)) \ + ROM_API_PRCM_TABLE[14]) // SMPH FUNCTIONS -#define ROM_SMPHAcquire \ +#define ROM_SMPHAcquire \ ((void (*)(uint32_t ui32Semaphore)) \ - ROM_API_SMPH_TABLE[0]) - + ROM_API_SMPH_TABLE[0]) // SSI FUNCTIONS -#define ROM_SSIConfigSetExpClk \ +#define ROM_SSIConfigSetExpClk \ ((void (*)(uint32_t ui32Base, uint32_t ui32SSIClk, uint32_t ui32Protocol, uint32_t ui32Mode, uint32_t ui32BitRate, uint32_t ui32DataWidth)) \ - ROM_API_SSI_TABLE[0]) + ROM_API_SSI_TABLE[0]) -#define ROM_SSIDataPut \ +#define ROM_SSIDataPut \ ((void (*)(uint32_t ui32Base, uint32_t ui32Data)) \ - ROM_API_SSI_TABLE[1]) + ROM_API_SSI_TABLE[1]) -#define ROM_SSIDataPutNonBlocking \ - ((int32_t (*)(uint32_t ui32Base, uint32_t ui32Data)) \ - ROM_API_SSI_TABLE[2]) +#define ROM_SSIDataPutNonBlocking \ + ((int32_t(*)(uint32_t ui32Base, uint32_t ui32Data)) \ + ROM_API_SSI_TABLE[2]) -#define ROM_SSIDataGet \ - ((void (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ - ROM_API_SSI_TABLE[3]) - -#define ROM_SSIDataGetNonBlocking \ - ((int32_t (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ - ROM_API_SSI_TABLE[4]) +#define ROM_SSIDataGet \ + ((void (*)(uint32_t ui32Base, uint32_t * pui32Data)) \ + ROM_API_SSI_TABLE[3]) +#define ROM_SSIDataGetNonBlocking \ + ((int32_t(*)(uint32_t ui32Base, uint32_t * pui32Data)) \ + ROM_API_SSI_TABLE[4]) // TIMER FUNCTIONS -#define ROM_TimerConfigure \ +#define ROM_TimerConfigure \ ((void (*)(uint32_t ui32Base, uint32_t ui32Config)) \ - ROM_API_TIMER_TABLE[0]) + ROM_API_TIMER_TABLE[0]) -#define ROM_TimerLevelControl \ +#define ROM_TimerLevelControl \ ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert)) \ - ROM_API_TIMER_TABLE[1]) + ROM_API_TIMER_TABLE[1]) -#define ROM_TimerStallControl \ +#define ROM_TimerStallControl \ ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bStall)) \ - ROM_API_TIMER_TABLE[3]) + ROM_API_TIMER_TABLE[3]) -#define ROM_TimerWaitOnTriggerControl \ +#define ROM_TimerWaitOnTriggerControl \ ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bWait)) \ - ROM_API_TIMER_TABLE[4]) - + ROM_API_TIMER_TABLE[4]) // TRNG FUNCTIONS -#define ROM_TRNGNumberGet \ - ((uint32_t (*)(uint32_t ui32Word)) \ - ROM_API_TRNG_TABLE[1]) - +#define ROM_TRNGNumberGet \ + ((uint32_t(*)(uint32_t ui32Word)) \ + ROM_API_TRNG_TABLE[1]) // UART FUNCTIONS -#define ROM_UARTFIFOLevelGet \ - ((void (*)(uint32_t ui32Base, uint32_t *pui32TxLevel, uint32_t *pui32RxLevel)) \ - ROM_API_UART_TABLE[0]) +#define ROM_UARTFIFOLevelGet \ + ((void (*)(uint32_t ui32Base, uint32_t * pui32TxLevel, uint32_t * pui32RxLevel)) \ + ROM_API_UART_TABLE[0]) -#define ROM_UARTConfigSetExpClk \ +#define ROM_UARTConfigSetExpClk \ ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t ui32Baud, uint32_t ui32Config)) \ - ROM_API_UART_TABLE[1]) + ROM_API_UART_TABLE[1]) -#define ROM_UARTConfigGetExpClk \ - ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t *pui32Baud, uint32_t *pui32Config)) \ - ROM_API_UART_TABLE[2]) +#define ROM_UARTConfigGetExpClk \ + ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t * pui32Baud, uint32_t * pui32Config)) \ + ROM_API_UART_TABLE[2]) -#define ROM_UARTDisable \ +#define ROM_UARTDisable \ ((void (*)(uint32_t ui32Base)) \ - ROM_API_UART_TABLE[3]) + ROM_API_UART_TABLE[3]) -#define ROM_UARTCharGetNonBlocking \ - ((int32_t (*)(uint32_t ui32Base)) \ - ROM_API_UART_TABLE[4]) +#define ROM_UARTCharGetNonBlocking \ + ((int32_t(*)(uint32_t ui32Base)) \ + ROM_API_UART_TABLE[4]) -#define ROM_UARTCharGet \ - ((int32_t (*)(uint32_t ui32Base)) \ - ROM_API_UART_TABLE[5]) +#define ROM_UARTCharGet \ + ((int32_t(*)(uint32_t ui32Base)) \ + ROM_API_UART_TABLE[5]) -#define ROM_UARTCharPutNonBlocking \ +#define ROM_UARTCharPutNonBlocking \ ((bool (*)(uint32_t ui32Base, uint8_t ui8Data)) \ - ROM_API_UART_TABLE[6]) + ROM_API_UART_TABLE[6]) -#define ROM_UARTCharPut \ +#define ROM_UARTCharPut \ ((void (*)(uint32_t ui32Base, uint8_t ui8Data)) \ - ROM_API_UART_TABLE[7]) - + ROM_API_UART_TABLE[7]) // UDMA FUNCTIONS -#define ROM_uDMAChannelAttributeEnable \ +#define ROM_uDMAChannelAttributeEnable \ ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ - ROM_API_UDMA_TABLE[0]) + ROM_API_UDMA_TABLE[0]) -#define ROM_uDMAChannelAttributeDisable \ +#define ROM_uDMAChannelAttributeDisable \ ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ - ROM_API_UDMA_TABLE[1]) + ROM_API_UDMA_TABLE[1]) -#define ROM_uDMAChannelAttributeGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelNum)) \ - ROM_API_UDMA_TABLE[2]) +#define ROM_uDMAChannelAttributeGet \ + ((uint32_t(*)(uint32_t ui32Base, uint32_t ui32ChannelNum)) \ + ROM_API_UDMA_TABLE[2]) -#define ROM_uDMAChannelControlSet \ +#define ROM_uDMAChannelControlSet \ ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Control)) \ - ROM_API_UDMA_TABLE[3]) + ROM_API_UDMA_TABLE[3]) -#define ROM_uDMAChannelScatterGatherSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void *pvTaskList, uint32_t ui32IsPeriphSG)) \ - ROM_API_UDMA_TABLE[5]) +#define ROM_uDMAChannelScatterGatherSet \ + ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void* pvTaskList, uint32_t ui32IsPeriphSG)) \ + ROM_API_UDMA_TABLE[5]) -#define ROM_uDMAChannelSizeGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ - ROM_API_UDMA_TABLE[6]) - -#define ROM_uDMAChannelModeGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ - ROM_API_UDMA_TABLE[7]) +#define ROM_uDMAChannelSizeGet \ + ((uint32_t(*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ + ROM_API_UDMA_TABLE[6]) +#define ROM_uDMAChannelModeGet \ + ((uint32_t(*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ + ROM_API_UDMA_TABLE[7]) // VIMS FUNCTIONS -#define ROM_VIMSConfigure \ +#define ROM_VIMSConfigure \ ((void (*)(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch)) \ - ROM_API_VIMS_TABLE[0]) + ROM_API_VIMS_TABLE[0]) -#define ROM_VIMSModeSet \ +#define ROM_VIMSModeSet \ ((void (*)(uint32_t ui32Base, uint32_t ui32Mode)) \ - ROM_API_VIMS_TABLE[1]) - - + ROM_API_VIMS_TABLE[1]) //***************************************************************************** // diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rom_crypto.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rom_crypto.h index 8974406..ee76fc8 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rom_crypto.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/rom_crypto.h @@ -1,41 +1,41 @@ /****************************************************************************** -* Filename: rom_crypto.h -* Revised: 2018-09-17 09:24:56 +0200 (Mon, 17 Sep 2018) -* Revision: 52624 -* -* Description: This header file is the API to the crypto functions -* built into ROM on the CC13xx/CC26xx. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -*******************************************************************************/ + * Filename: rom_crypto.h + * Revised: 2018-09-17 09:24:56 +0200 (Mon, 17 Sep 2018) + * Revision: 52624 + * + * Description: This header file is the API to the crypto functions + * built into ROM on the CC13xx/CC26xx. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *******************************************************************************/ //***************************************************************************** // @@ -50,8 +50,7 @@ #define ROM_CRYPTO_H #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif ///////////////////////////////////* AES-128 *////////////////////////////////// @@ -188,42 +187,42 @@ extern uint8_t AES_CTR_DecryptData(uint8_t* cipherText, uint16_t textLen, * ECC Return Status Flags. */ // Scalar multiplication status -#define ECC_MODULUS_EVEN 0xDC -#define ECC_MODULUS_LARGER_THAN_255_WORDS 0xD2 -#define ECC_MODULUS_LENGTH_ZERO 0x08 -#define ECC_MODULUS_MSW_IS_ZERO 0x30 -#define ECC_SCALAR_TOO_LONG 0x35 -#define ECC_SCALAR_LENGTH_ZERO 0x53 -#define ECC_ORDER_TOO_LONG 0xC6 -#define ECC_ORDER_LENGTH_ZERO 0x6C -#define ECC_X_COORD_TOO_LONG 0x3C -#define ECC_X_COORD_LENGTH_ZERO 0xC3 -#define ECC_Y_COORD_TOO_LONG 0x65 -#define ECC_Y_COORD_LENGTH_ZERO 0x56 -#define ECC_A_COEF_TOO_LONG 0x5C -#define ECC_A_COEF_LENGTH_ZERO 0xC5 -#define ECC_BAD_WINDOW_SIZE 0x66 -#define ECC_SCALAR_MUL_OK 0x99 +#define ECC_MODULUS_EVEN 0xDC +#define ECC_MODULUS_LARGER_THAN_255_WORDS 0xD2 +#define ECC_MODULUS_LENGTH_ZERO 0x08 +#define ECC_MODULUS_MSW_IS_ZERO 0x30 +#define ECC_SCALAR_TOO_LONG 0x35 +#define ECC_SCALAR_LENGTH_ZERO 0x53 +#define ECC_ORDER_TOO_LONG 0xC6 +#define ECC_ORDER_LENGTH_ZERO 0x6C +#define ECC_X_COORD_TOO_LONG 0x3C +#define ECC_X_COORD_LENGTH_ZERO 0xC3 +#define ECC_Y_COORD_TOO_LONG 0x65 +#define ECC_Y_COORD_LENGTH_ZERO 0x56 +#define ECC_A_COEF_TOO_LONG 0x5C +#define ECC_A_COEF_LENGTH_ZERO 0xC5 +#define ECC_BAD_WINDOW_SIZE 0x66 +#define ECC_SCALAR_MUL_OK 0x99 // ECDSA and ECDH status -#define ECC_ORDER_LARGER_THAN_255_WORDS 0x28 -#define ECC_ORDER_EVEN 0x82 -#define ECC_ORDER_MSW_IS_ZERO 0x23 -#define ECC_ECC_KEY_TOO_LONG 0x25 -#define ECC_ECC_KEY_LENGTH_ZERO 0x52 -#define ECC_DIGEST_TOO_LONG 0x27 -#define ECC_DIGEST_LENGTH_ZERO 0x72 -#define ECC_ECDSA_SIGN_OK 0x32 -#define ECC_ECDSA_INVALID_SIGNATURE 0x5A -#define ECC_ECDSA_VALID_SIGNATURE 0xA5 -#define ECC_SIG_P1_TOO_LONG 0x11 -#define ECC_SIG_P1_LENGTH_ZERO 0x12 -#define ECC_SIG_P2_TOO_LONG 0x22 -#define ECC_SIG_P2_LENGTH_ZERO 0x21 +#define ECC_ORDER_LARGER_THAN_255_WORDS 0x28 +#define ECC_ORDER_EVEN 0x82 +#define ECC_ORDER_MSW_IS_ZERO 0x23 +#define ECC_ECC_KEY_TOO_LONG 0x25 +#define ECC_ECC_KEY_LENGTH_ZERO 0x52 +#define ECC_DIGEST_TOO_LONG 0x27 +#define ECC_DIGEST_LENGTH_ZERO 0x72 +#define ECC_ECDSA_SIGN_OK 0x32 +#define ECC_ECDSA_INVALID_SIGNATURE 0x5A +#define ECC_ECDSA_VALID_SIGNATURE 0xA5 +#define ECC_SIG_P1_TOO_LONG 0x11 +#define ECC_SIG_P1_LENGTH_ZERO 0x12 +#define ECC_SIG_P2_TOO_LONG 0x22 +#define ECC_SIG_P2_LENGTH_ZERO 0x21 -#define ECC_ECDSA_KEYGEN_OK ECC_SCALAR_MUL_OK -#define ECC_ECDH_KEYGEN_OK ECC_SCALAR_MUL_OK -#define ECC_ECDH_COMMON_KEY_OK ECC_SCALAR_MUL_OK +#define ECC_ECDSA_KEYGEN_OK ECC_SCALAR_MUL_OK +#define ECC_ECDH_KEYGEN_OK ECC_SCALAR_MUL_OK +#define ECC_ECDH_COMMON_KEY_OK ECC_SCALAR_MUL_OK //***************************************************************************** /*! @@ -243,17 +242,17 @@ extern void ECC_initialize(uint32_t* pWorkzone); //***************************************************************************** /*! -* \brief Generate a key. -* -* This is used for both ECDH and ECDSA. -* -* \param randString Pointer to random string, input. -* \param privateKey Pointer to the private key, output. -* \param publicKey_x Pointer to public key X-coordinate, output. -* \param publicKey_y Pointer to public key Y-coordinate, output. -* -* \return Status -*/ + * \brief Generate a key. + * + * This is used for both ECDH and ECDSA. + * + * \param randString Pointer to random string, input. + * \param privateKey Pointer to the private key, output. + * \param publicKey_x Pointer to public key X-coordinate, output. + * \param publicKey_y Pointer to public key Y-coordinate, output. + * + * \return Status + */ //***************************************************************************** extern uint8_t ECC_generateKey(uint32_t* randString, uint32_t* privateKey, uint32_t* publicKey_x, uint32_t* publicKey_y); @@ -304,11 +303,10 @@ extern uint8_t ECC_ECDSA_verify(uint32_t* publicKey_x, uint32_t* publicKey_y, */ //***************************************************************************** extern uint8_t ECC_ECDH_computeSharedSecret(uint32_t* privateKey, - uint32_t* publicKey_x, - uint32_t* publicKey_y, - uint32_t* sharedSecret_x, - uint32_t* sharedSecret_y); - + uint32_t* publicKey_x, + uint32_t* publicKey_y, + uint32_t* sharedSecret_x, + uint32_t* sharedSecret_y); ///////////////////////////////////* SHA-256 *////////////////////////////////// @@ -316,9 +314,9 @@ extern uint8_t ECC_ECDH_computeSharedSecret(uint32_t* privateKey, //! SHA256 functions. typedef struct { - uint32_t state[8]; - uint32_t textLen[2]; - uint32_t W[16]; + uint32_t state[8]; + uint32_t textLen[2]; + uint32_t W[16]; } SHA256_memory_t; //***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup.h index 923bc71..db72a66 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: setup.h -* Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) -* Revision: 52993 -* -* Description: Prototypes and defines for the setup API. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: setup.h + * Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) + * Revision: 52993 + * + * Description: Prototypes and defines for the setup API. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,8 +55,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif // Hardware headers @@ -78,7 +77,7 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define SetupTrimDevice NOROM_SetupTrimDevice +#define SetupTrimDevice NOROM_SetupTrimDevice #endif //***************************************************************************** @@ -105,7 +104,7 @@ extern "C" //! \return None // //***************************************************************************** -extern void SetupTrimDevice( void ); +extern void SetupTrimDevice(void); //***************************************************************************** // @@ -116,8 +115,8 @@ extern void SetupTrimDevice( void ); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_SetupTrimDevice -#undef SetupTrimDevice -#define SetupTrimDevice ROM_SetupTrimDevice +#undef SetupTrimDevice +#define SetupTrimDevice ROM_SetupTrimDevice #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_doc.h index 07ab97e..1b46e56 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: setup_doc.h -* Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017) -* Revision: 49096 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: setup_doc.h + * Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017) + * Revision: 49096 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup setup_api //! @{ //! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_rom.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_rom.h index e79d908..059aea3 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_rom.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_rom.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: setup_rom.h -* Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) -* Revision: 52993 -* -* Description: Prototypes and defines for the setup API. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: setup_rom.h + * Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) + * Revision: 52993 + * + * Description: Prototypes and defines for the setup API. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,8 +55,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif // Hardware headers @@ -81,22 +80,22 @@ extern "C" #define SetupAfterColdResetWakeupFromShutDownCfg1 NOROM_SetupAfterColdResetWakeupFromShutDownCfg1 #define SetupAfterColdResetWakeupFromShutDownCfg2 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2 #define SetupAfterColdResetWakeupFromShutDownCfg3 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3 -#define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn -#define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn -#define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl -#define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1 -#define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2 -#define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1 +#define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn +#define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn +#define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl +#define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1 +#define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2 +#define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1 #define SetupGetTrimForDblrLoopFilterResetVoltage NOROM_SetupGetTrimForDblrLoopFilterResetVoltage -#define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg +#define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg #define SetupGetTrimForRcOscLfIBiasTrim NOROM_SetupGetTrimForRcOscLfIBiasTrim #define SetupGetTrimForRcOscLfRtuneCtuneTrim NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim -#define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl -#define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart +#define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl +#define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart #define SetupGetTrimForXoscHfIbiastherm NOROM_SetupGetTrimForXoscHfIbiastherm #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio #define SetupSetCacheModeAccordingToCcfgSetting NOROM_SetupSetCacheModeAccordingToCcfgSetting -#define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc +#define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc #endif //***************************************************************************** @@ -118,7 +117,7 @@ extern "C" //! \return None // //***************************************************************************** -extern void SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg ); +extern void SetupAfterColdResetWakeupFromShutDownCfg1(uint32_t ccfg_ModeConfReg); //***************************************************************************** // @@ -134,7 +133,7 @@ extern void SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg //! \return None // //***************************************************************************** -extern void SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg ); +extern void SetupAfterColdResetWakeupFromShutDownCfg2(uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg); //***************************************************************************** // @@ -154,7 +153,7 @@ extern void SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revisio //! \return None // //***************************************************************************** -extern void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ); +extern void SetupAfterColdResetWakeupFromShutDownCfg3(uint32_t ccfg_ModeConfReg); //***************************************************************************** // @@ -165,7 +164,7 @@ extern void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg //! \return Returns the trim value from FCFG1. // //***************************************************************************** -extern uint32_t SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForAdcShModeEn(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -176,7 +175,7 @@ extern uint32_t SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision ); //! \return Returns the trim value from FCFG1. // //***************************************************************************** -extern uint32_t SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForAdcShVbufEn(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -187,7 +186,7 @@ extern uint32_t SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForAmpcompCtrl(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -196,7 +195,7 @@ extern uint32_t SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForAmpcompTh1( void ); +extern uint32_t SetupGetTrimForAmpcompTh1(void); //***************************************************************************** // @@ -205,7 +204,7 @@ extern uint32_t SetupGetTrimForAmpcompTh1( void ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForAmpcompTh2( void ); +extern uint32_t SetupGetTrimForAmpcompTh2(void); //***************************************************************************** // @@ -216,7 +215,7 @@ extern uint32_t SetupGetTrimForAmpcompTh2( void ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ); +extern uint32_t SetupGetTrimForAnabypassValue1(uint32_t ccfg_ModeConfReg); //***************************************************************************** // @@ -227,7 +226,7 @@ extern uint32_t SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ); //! \return Returns the trim value from FCFG1. // //***************************************************************************** -extern uint32_t SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForDblrLoopFilterResetVoltage(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -238,7 +237,7 @@ extern uint32_t SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Rev //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForRadcExtCfg(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -249,7 +248,7 @@ extern uint32_t SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision ); //! \return Returns the trim value from FCFG1. // //***************************************************************************** -extern uint32_t SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForRcOscLfIBiasTrim(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -259,7 +258,7 @@ extern uint32_t SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim( void ); +extern uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim(void); //***************************************************************************** // @@ -270,7 +269,7 @@ extern uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim( void ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForXoscHfCtl(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -279,7 +278,7 @@ extern uint32_t SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForXoscHfFastStart( void ); +extern uint32_t SetupGetTrimForXoscHfFastStart(void); //***************************************************************************** // @@ -289,7 +288,7 @@ extern uint32_t SetupGetTrimForXoscHfFastStart( void ); //! \return Returns the trim value. // //***************************************************************************** -extern uint32_t SetupGetTrimForXoscHfIbiastherm( void ); +extern uint32_t SetupGetTrimForXoscHfIbiastherm(void); //***************************************************************************** // @@ -301,7 +300,7 @@ extern uint32_t SetupGetTrimForXoscHfIbiastherm( void ); //! \return Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet. // //***************************************************************************** -extern uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision ); +extern uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio(uint32_t ui32Fcfg1Revision); //***************************************************************************** // @@ -313,18 +312,18 @@ extern uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg // //***************************************************************************** __STATIC_INLINE int32_t -SetupSignExtendVddrTrimValue( uint32_t ui32VddrTrimVal ) +SetupSignExtendVddrTrimValue(uint32_t ui32VddrTrimVal) { // The VDDR trim value is 5 bits representing the range from -10 to +21 // (where -10=0x16, -1=0x1F, 0=0x00, 1=0x01 and +21=0x15) int32_t i32SignedVddrVal = ui32VddrTrimVal; - if ( i32SignedVddrVal > 0x15 ) + if (i32SignedVddrVal > 0x15) { i32SignedVddrVal -= 0x20; } - return ( i32SignedVddrVal ); + return (i32SignedVddrVal); } //***************************************************************************** @@ -334,7 +333,7 @@ SetupSignExtendVddrTrimValue( uint32_t ui32VddrTrimVal ) //! \return None // //***************************************************************************** -extern void SetupSetCacheModeAccordingToCcfgSetting( void ); +extern void SetupSetCacheModeAccordingToCcfgSetting(void); //***************************************************************************** // @@ -345,7 +344,7 @@ extern void SetupSetCacheModeAccordingToCcfgSetting( void ); //! \return None // //***************************************************************************** -extern void SetupSetAonRtcSubSecInc( uint32_t subSecInc ); +extern void SetupSetAonRtcSubSecInc(uint32_t subSecInc); //***************************************************************************** // @@ -356,80 +355,80 @@ extern void SetupSetAonRtcSubSecInc( uint32_t subSecInc ); #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg1 -#undef SetupAfterColdResetWakeupFromShutDownCfg1 +#undef SetupAfterColdResetWakeupFromShutDownCfg1 #define SetupAfterColdResetWakeupFromShutDownCfg1 ROM_SetupAfterColdResetWakeupFromShutDownCfg1 #endif #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg2 -#undef SetupAfterColdResetWakeupFromShutDownCfg2 +#undef SetupAfterColdResetWakeupFromShutDownCfg2 #define SetupAfterColdResetWakeupFromShutDownCfg2 ROM_SetupAfterColdResetWakeupFromShutDownCfg2 #endif #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg3 -#undef SetupAfterColdResetWakeupFromShutDownCfg3 +#undef SetupAfterColdResetWakeupFromShutDownCfg3 #define SetupAfterColdResetWakeupFromShutDownCfg3 ROM_SetupAfterColdResetWakeupFromShutDownCfg3 #endif #ifdef ROM_SetupGetTrimForAdcShModeEn -#undef SetupGetTrimForAdcShModeEn -#define SetupGetTrimForAdcShModeEn ROM_SetupGetTrimForAdcShModeEn +#undef SetupGetTrimForAdcShModeEn +#define SetupGetTrimForAdcShModeEn ROM_SetupGetTrimForAdcShModeEn #endif #ifdef ROM_SetupGetTrimForAdcShVbufEn -#undef SetupGetTrimForAdcShVbufEn -#define SetupGetTrimForAdcShVbufEn ROM_SetupGetTrimForAdcShVbufEn +#undef SetupGetTrimForAdcShVbufEn +#define SetupGetTrimForAdcShVbufEn ROM_SetupGetTrimForAdcShVbufEn #endif #ifdef ROM_SetupGetTrimForAmpcompCtrl -#undef SetupGetTrimForAmpcompCtrl -#define SetupGetTrimForAmpcompCtrl ROM_SetupGetTrimForAmpcompCtrl +#undef SetupGetTrimForAmpcompCtrl +#define SetupGetTrimForAmpcompCtrl ROM_SetupGetTrimForAmpcompCtrl #endif #ifdef ROM_SetupGetTrimForAmpcompTh1 -#undef SetupGetTrimForAmpcompTh1 -#define SetupGetTrimForAmpcompTh1 ROM_SetupGetTrimForAmpcompTh1 +#undef SetupGetTrimForAmpcompTh1 +#define SetupGetTrimForAmpcompTh1 ROM_SetupGetTrimForAmpcompTh1 #endif #ifdef ROM_SetupGetTrimForAmpcompTh2 -#undef SetupGetTrimForAmpcompTh2 -#define SetupGetTrimForAmpcompTh2 ROM_SetupGetTrimForAmpcompTh2 +#undef SetupGetTrimForAmpcompTh2 +#define SetupGetTrimForAmpcompTh2 ROM_SetupGetTrimForAmpcompTh2 #endif #ifdef ROM_SetupGetTrimForAnabypassValue1 -#undef SetupGetTrimForAnabypassValue1 -#define SetupGetTrimForAnabypassValue1 ROM_SetupGetTrimForAnabypassValue1 +#undef SetupGetTrimForAnabypassValue1 +#define SetupGetTrimForAnabypassValue1 ROM_SetupGetTrimForAnabypassValue1 #endif #ifdef ROM_SetupGetTrimForDblrLoopFilterResetVoltage -#undef SetupGetTrimForDblrLoopFilterResetVoltage +#undef SetupGetTrimForDblrLoopFilterResetVoltage #define SetupGetTrimForDblrLoopFilterResetVoltage ROM_SetupGetTrimForDblrLoopFilterResetVoltage #endif #ifdef ROM_SetupGetTrimForRadcExtCfg -#undef SetupGetTrimForRadcExtCfg -#define SetupGetTrimForRadcExtCfg ROM_SetupGetTrimForRadcExtCfg +#undef SetupGetTrimForRadcExtCfg +#define SetupGetTrimForRadcExtCfg ROM_SetupGetTrimForRadcExtCfg #endif #ifdef ROM_SetupGetTrimForRcOscLfIBiasTrim -#undef SetupGetTrimForRcOscLfIBiasTrim +#undef SetupGetTrimForRcOscLfIBiasTrim #define SetupGetTrimForRcOscLfIBiasTrim ROM_SetupGetTrimForRcOscLfIBiasTrim #endif #ifdef ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim -#undef SetupGetTrimForRcOscLfRtuneCtuneTrim +#undef SetupGetTrimForRcOscLfRtuneCtuneTrim #define SetupGetTrimForRcOscLfRtuneCtuneTrim ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim #endif #ifdef ROM_SetupGetTrimForXoscHfCtl -#undef SetupGetTrimForXoscHfCtl -#define SetupGetTrimForXoscHfCtl ROM_SetupGetTrimForXoscHfCtl +#undef SetupGetTrimForXoscHfCtl +#define SetupGetTrimForXoscHfCtl ROM_SetupGetTrimForXoscHfCtl #endif #ifdef ROM_SetupGetTrimForXoscHfFastStart -#undef SetupGetTrimForXoscHfFastStart -#define SetupGetTrimForXoscHfFastStart ROM_SetupGetTrimForXoscHfFastStart +#undef SetupGetTrimForXoscHfFastStart +#define SetupGetTrimForXoscHfFastStart ROM_SetupGetTrimForXoscHfFastStart #endif #ifdef ROM_SetupGetTrimForXoscHfIbiastherm -#undef SetupGetTrimForXoscHfIbiastherm +#undef SetupGetTrimForXoscHfIbiastherm #define SetupGetTrimForXoscHfIbiastherm ROM_SetupGetTrimForXoscHfIbiastherm #endif #ifdef ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio -#undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio +#undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio #endif #ifdef ROM_SetupSetCacheModeAccordingToCcfgSetting -#undef SetupSetCacheModeAccordingToCcfgSetting +#undef SetupSetCacheModeAccordingToCcfgSetting #define SetupSetCacheModeAccordingToCcfgSetting ROM_SetupSetCacheModeAccordingToCcfgSetting #endif #ifdef ROM_SetupSetAonRtcSubSecInc -#undef SetupSetAonRtcSubSecInc -#define SetupSetAonRtcSubSecInc ROM_SetupSetAonRtcSubSecInc +#undef SetupSetAonRtcSubSecInc +#define SetupSetAonRtcSubSecInc ROM_SetupSetAonRtcSubSecInc #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_rom_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_rom_doc.h index bafcf07..c8df48a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_rom_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/setup_rom_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: setup_rom_doc.h -* Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017) -* Revision: 49096 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: setup_rom_doc.h + * Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017) + * Revision: 49096 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup setup_rom_api //! @{ //! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/smph.h index e1bfc44..5e8ebb1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/smph.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/smph.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: smph.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the MCU Semaphore. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: smph.h + * Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) + * Revision: 47343 + * + * Description: Defines and prototypes for the MCU Semaphore. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,16 +55,15 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_memmap.h" +#include "../inc/hw_smph.h" +#include "../inc/hw_types.h" +#include "debug.h" #include #include -#include "../inc/hw_types.h" -#include "../inc/hw_smph.h" -#include "../inc/hw_memmap.h" -#include "debug.h" //***************************************************************************** // @@ -80,7 +79,7 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define SMPHAcquire NOROM_SMPHAcquire +#define SMPHAcquire NOROM_SMPHAcquire #endif //***************************************************************************** @@ -88,8 +87,8 @@ extern "C" // General constants and defines // //***************************************************************************** -#define SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed -#define SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed +#define SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed +#define SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed //***************************************************************************** // @@ -97,38 +96,38 @@ extern "C" // as the ui32Semaphore parameter. // //***************************************************************************** -#define SMPH_0 0 // MCU Semaphore 0 -#define SMPH_1 1 // MCU Semaphore 1 -#define SMPH_2 2 // MCU Semaphore 2 -#define SMPH_3 3 // MCU Semaphore 3 -#define SMPH_4 4 // MCU Semaphore 4 -#define SMPH_5 5 // MCU Semaphore 5 -#define SMPH_6 6 // MCU Semaphore 6 -#define SMPH_7 7 // MCU Semaphore 7 -#define SMPH_8 8 // MCU Semaphore 8 -#define SMPH_9 9 // MCU Semaphore 9 -#define SMPH_10 10 // MCU Semaphore 10 -#define SMPH_11 11 // MCU Semaphore 11 -#define SMPH_12 12 // MCU Semaphore 12 -#define SMPH_13 13 // MCU Semaphore 13 -#define SMPH_14 14 // MCU Semaphore 14 -#define SMPH_15 15 // MCU Semaphore 15 -#define SMPH_16 16 // MCU Semaphore 16 -#define SMPH_17 17 // MCU Semaphore 17 -#define SMPH_18 18 // MCU Semaphore 18 -#define SMPH_19 19 // MCU Semaphore 19 -#define SMPH_20 20 // MCU Semaphore 20 -#define SMPH_21 21 // MCU Semaphore 21 -#define SMPH_22 22 // MCU Semaphore 22 -#define SMPH_23 23 // MCU Semaphore 23 -#define SMPH_24 24 // MCU Semaphore 24 -#define SMPH_25 25 // MCU Semaphore 25 -#define SMPH_26 26 // MCU Semaphore 26 -#define SMPH_27 27 // MCU Semaphore 27 -#define SMPH_28 28 // MCU Semaphore 28 -#define SMPH_29 29 // MCU Semaphore 29 -#define SMPH_30 30 // MCU Semaphore 30 -#define SMPH_31 31 // MCU Semaphore 31 +#define SMPH_0 0 // MCU Semaphore 0 +#define SMPH_1 1 // MCU Semaphore 1 +#define SMPH_2 2 // MCU Semaphore 2 +#define SMPH_3 3 // MCU Semaphore 3 +#define SMPH_4 4 // MCU Semaphore 4 +#define SMPH_5 5 // MCU Semaphore 5 +#define SMPH_6 6 // MCU Semaphore 6 +#define SMPH_7 7 // MCU Semaphore 7 +#define SMPH_8 8 // MCU Semaphore 8 +#define SMPH_9 9 // MCU Semaphore 9 +#define SMPH_10 10 // MCU Semaphore 10 +#define SMPH_11 11 // MCU Semaphore 11 +#define SMPH_12 12 // MCU Semaphore 12 +#define SMPH_13 13 // MCU Semaphore 13 +#define SMPH_14 14 // MCU Semaphore 14 +#define SMPH_15 15 // MCU Semaphore 15 +#define SMPH_16 16 // MCU Semaphore 16 +#define SMPH_17 17 // MCU Semaphore 17 +#define SMPH_18 18 // MCU Semaphore 18 +#define SMPH_19 19 // MCU Semaphore 19 +#define SMPH_20 20 // MCU Semaphore 20 +#define SMPH_21 21 // MCU Semaphore 21 +#define SMPH_22 22 // MCU Semaphore 22 +#define SMPH_23 23 // MCU Semaphore 23 +#define SMPH_24 24 // MCU Semaphore 24 +#define SMPH_25 25 // MCU Semaphore 25 +#define SMPH_26 26 // MCU Semaphore 26 +#define SMPH_27 27 // MCU Semaphore 27 +#define SMPH_28 28 // MCU Semaphore 28 +#define SMPH_29 29 // MCU Semaphore 29 +#define SMPH_30 30 // MCU Semaphore 30 +#define SMPH_31 31 // MCU Semaphore 31 //***************************************************************************** // @@ -287,8 +286,8 @@ SMPHRelease(uint32_t ui32Semaphore) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_SMPHAcquire -#undef SMPHAcquire -#define SMPHAcquire ROM_SMPHAcquire +#undef SMPHAcquire +#define SMPHAcquire ROM_SMPHAcquire #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/smph_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/smph_doc.h index c66ef84..086359e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/smph_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/smph_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: smph_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: smph_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup mcusemaphore_api //! @{ //! \section sec_mcusemaphore Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ssi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ssi.h index 74eaa08..c09fc82 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ssi.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/ssi.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: ssi.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and macros for the SSI. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: ssi.h + * Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) + * Revision: 49048 + * + * Description: Defines and macros for the SSI. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,18 +55,17 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include #include "../inc/hw_ints.h" #include "../inc/hw_memmap.h" -#include "../inc/hw_types.h" #include "../inc/hw_ssi.h" +#include "../inc/hw_types.h" #include "debug.h" #include "interrupt.h" +#include +#include //***************************************************************************** // @@ -82,13 +81,13 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define SSIConfigSetExpClk NOROM_SSIConfigSetExpClk -#define SSIDataPut NOROM_SSIDataPut -#define SSIDataPutNonBlocking NOROM_SSIDataPutNonBlocking -#define SSIDataGet NOROM_SSIDataGet -#define SSIDataGetNonBlocking NOROM_SSIDataGetNonBlocking -#define SSIIntRegister NOROM_SSIIntRegister -#define SSIIntUnregister NOROM_SSIIntUnregister +#define SSIConfigSetExpClk NOROM_SSIConfigSetExpClk +#define SSIDataPut NOROM_SSIDataPut +#define SSIDataPutNonBlocking NOROM_SSIDataPutNonBlocking +#define SSIDataGet NOROM_SSIDataGet +#define SSIDataGetNonBlocking NOROM_SSIDataGetNonBlocking +#define SSIIntRegister NOROM_SSIIntRegister +#define SSIIntUnregister NOROM_SSIIntUnregister #endif //***************************************************************************** @@ -97,45 +96,45 @@ extern "C" // as the ui32IntFlags parameter, and returned by SSIIntStatus. // //***************************************************************************** -#define SSI_TXFF 0x00000008 // TX FIFO half full or less -#define SSI_RXFF 0x00000004 // RX FIFO half full or more -#define SSI_RXTO 0x00000002 // RX timeout -#define SSI_RXOR 0x00000001 // RX overrun +#define SSI_TXFF 0x00000008 // TX FIFO half full or less +#define SSI_RXFF 0x00000004 // RX FIFO half full or more +#define SSI_RXTO 0x00000002 // RX timeout +#define SSI_RXOR 0x00000001 // RX overrun //***************************************************************************** // // Values that are returned from SSIStatus // //***************************************************************************** -#define SSI_RX_FULL 0x00000008 // Receive FIFO full -#define SSI_RX_NOT_EMPTY 0x00000004 // Receive FIFO not empty -#define SSI_TX_NOT_FULL 0x00000002 // Transmit FIFO not full -#define SSI_TX_EMPTY 0x00000001 // Transmit FIFO empty -#define SSI_STATUS_MASK 0x0000000F +#define SSI_RX_FULL 0x00000008 // Receive FIFO full +#define SSI_RX_NOT_EMPTY 0x00000004 // Receive FIFO not empty +#define SSI_TX_NOT_FULL 0x00000002 // Transmit FIFO not full +#define SSI_TX_EMPTY 0x00000001 // Transmit FIFO empty +#define SSI_STATUS_MASK 0x0000000F //***************************************************************************** // // Values that can be passed to SSIConfigSetExpClk. // //***************************************************************************** -#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 -#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 -#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 -#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 -#define SSI_FRF_TI 0x00000010 // TI frame format -#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format +#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 +#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 +#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 +#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 +#define SSI_FRF_TI 0x00000010 // TI frame format +#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format -#define SSI_MODE_MASTER 0x00000000 // SSI master -#define SSI_MODE_SLAVE 0x00000001 // SSI slave -#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled +#define SSI_MODE_MASTER 0x00000000 // SSI master +#define SSI_MODE_SLAVE 0x00000001 // SSI slave +#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled //***************************************************************************** // // Values that can be passed to SSIDMAEnable() and SSIDMADisable(). // //***************************************************************************** -#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit -#define SSI_DMA_RX 0x00000001 // Enable DMA for receive +#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit +#define SSI_DMA_RX 0x00000001 // Enable DMA for receive //***************************************************************************** // @@ -651,32 +650,32 @@ SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_SSIConfigSetExpClk -#undef SSIConfigSetExpClk -#define SSIConfigSetExpClk ROM_SSIConfigSetExpClk +#undef SSIConfigSetExpClk +#define SSIConfigSetExpClk ROM_SSIConfigSetExpClk #endif #ifdef ROM_SSIDataPut -#undef SSIDataPut -#define SSIDataPut ROM_SSIDataPut +#undef SSIDataPut +#define SSIDataPut ROM_SSIDataPut #endif #ifdef ROM_SSIDataPutNonBlocking -#undef SSIDataPutNonBlocking -#define SSIDataPutNonBlocking ROM_SSIDataPutNonBlocking +#undef SSIDataPutNonBlocking +#define SSIDataPutNonBlocking ROM_SSIDataPutNonBlocking #endif #ifdef ROM_SSIDataGet -#undef SSIDataGet -#define SSIDataGet ROM_SSIDataGet +#undef SSIDataGet +#define SSIDataGet ROM_SSIDataGet #endif #ifdef ROM_SSIDataGetNonBlocking -#undef SSIDataGetNonBlocking -#define SSIDataGetNonBlocking ROM_SSIDataGetNonBlocking +#undef SSIDataGetNonBlocking +#define SSIDataGetNonBlocking ROM_SSIDataGetNonBlocking #endif #ifdef ROM_SSIIntRegister -#undef SSIIntRegister -#define SSIIntRegister ROM_SSIIntRegister +#undef SSIIntRegister +#define SSIIntRegister ROM_SSIIntRegister #endif #ifdef ROM_SSIIntUnregister -#undef SSIIntUnregister -#define SSIIntUnregister ROM_SSIIntUnregister +#undef SSIIntUnregister +#define SSIIntUnregister ROM_SSIIntUnregister #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-config.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-config.h index 2b338bd..93e071f 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-config.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-config.h @@ -1,8 +1,8 @@ /****************************************************************************** -* Filename: sw_ecrypt-config.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ + * Filename: sw_ecrypt-config.h + * Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) + * Revision: 47308 + ******************************************************************************/ /* ecrypt-config.h */ /* *** Normally, it should not be necessary to edit this file. *** */ @@ -17,46 +17,46 @@ /* * The LITTLE endian machines: */ -#if ( ! defined(ECRYPT_LITTLE_ENDIAN)) - #if defined(__ultrix) /* Older MIPS */ - #define ECRYPT_LITTLE_ENDIAN - #elif defined(__alpha) /* Alpha */ - #define ECRYPT_LITTLE_ENDIAN - #elif defined(i386) /* x86 (gcc) */ - #define ECRYPT_LITTLE_ENDIAN - #elif defined(__i386) /* x86 (gcc) */ - #define ECRYPT_LITTLE_ENDIAN - #elif defined(_M_IX86) /* x86 (MSC, Borland) */ - #define ECRYPT_LITTLE_ENDIAN - #elif defined(_MSC_VER) /* x86 (surely MSC) */ - #define ECRYPT_LITTLE_ENDIAN - #elif defined(__INTEL_COMPILER) /* x86 (surely Intel compiler icl.exe) */ - #define ECRYPT_LITTLE_ENDIAN +#if (!defined(ECRYPT_LITTLE_ENDIAN)) +#if defined(__ultrix) /* Older MIPS */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(__alpha) /* Alpha */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(i386) /* x86 (gcc) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(__i386) /* x86 (gcc) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(_M_IX86) /* x86 (MSC, Borland) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(_MSC_VER) /* x86 (surely MSC) */ +#define ECRYPT_LITTLE_ENDIAN +#elif defined(__INTEL_COMPILER) /* x86 (surely Intel compiler icl.exe) */ +#define ECRYPT_LITTLE_ENDIAN - /* - * The BIG endian machines: - */ - #elif defined(sun) /* Newer Sparc's */ - #define ECRYPT_BIG_ENDIAN - #elif defined(__ppc__) /* PowerPC */ - #define ECRYPT_BIG_ENDIAN +/* + * The BIG endian machines: + */ +#elif defined(sun) /* Newer Sparc's */ +#define ECRYPT_BIG_ENDIAN +#elif defined(__ppc__) /* PowerPC */ +#define ECRYPT_BIG_ENDIAN - /* - * Finally machines with UNKNOWN endianness: - */ - #elif defined (_AIX) /* RS6000 */ - #define ECRYPT_UNKNOWN - #elif defined(__hpux) /* HP-PA */ - #define ECRYPT_UNKNOWN - #elif defined(__aux) /* 68K */ - #define ECRYPT_UNKNOWN - #elif defined(__dgux) /* 88K (but P6 in latest boxes) */ - #define ECRYPT_UNKNOWN - #elif defined(__sgi) /* Newer MIPS */ - #define ECRYPT_UNKNOWN - #else /* Any other processor */ - #define ECRYPT_UNKNOWN - #endif +/* + * Finally machines with UNKNOWN endianness: + */ +#elif defined(_AIX) /* RS6000 */ +#define ECRYPT_UNKNOWN +#elif defined(__hpux) /* HP-PA */ +#define ECRYPT_UNKNOWN +#elif defined(__aux) /* 68K */ +#define ECRYPT_UNKNOWN +#elif defined(__dgux) /* 88K (but P6 in latest boxes) */ +#define ECRYPT_UNKNOWN +#elif defined(__sgi) /* Newer MIPS */ +#define ECRYPT_UNKNOWN +#else /* Any other processor */ +#define ECRYPT_UNKNOWN +#endif #endif /* ------------------------------------------------------------------------- */ @@ -75,188 +75,188 @@ /* --- check char --- */ #if (UCHAR_MAX / 0xFU > 0xFU) - #ifndef I8T - #define I8T char - #define U8C(v) (v##U) +#ifndef I8T +#define I8T char +#define U8C(v) (v##U) - #if (UCHAR_MAX == 0xFFU) - #define ECRYPT_I8T_IS_BYTE - #endif +#if (UCHAR_MAX == 0xFFU) +#define ECRYPT_I8T_IS_BYTE +#endif - #endif +#endif - #if (UCHAR_MAX / 0xFFU > 0xFFU) - #ifndef I16T - #define I16T char - #define U16C(v) (v##U) - #endif +#if (UCHAR_MAX / 0xFFU > 0xFFU) +#ifndef I16T +#define I16T char +#define U16C(v) (v##U) +#endif - #if (UCHAR_MAX / 0xFFFFU > 0xFFFFU) - #ifndef I32T - #define I32T char - #define U32C(v) (v##U) - #endif +#if (UCHAR_MAX / 0xFFFFU > 0xFFFFU) +#ifndef I32T +#define I32T char +#define U32C(v) (v##U) +#endif - #if (UCHAR_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) - #ifndef I64T - #define I64T char - #define U64C(v) (v##U) - #define ECRYPT_NATIVE64 - #endif +#if (UCHAR_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) +#ifndef I64T +#define I64T char +#define U64C(v) (v##U) +#define ECRYPT_NATIVE64 +#endif - #endif - #endif - #endif +#endif +#endif +#endif #endif /* --- check short --- */ #if (USHRT_MAX / 0xFU > 0xFU) - #ifndef I8T - #define I8T short - #define U8C(v) (v##U) +#ifndef I8T +#define I8T short +#define U8C(v) (v##U) - #if (USHRT_MAX == 0xFFU) - #define ECRYPT_I8T_IS_BYTE - #endif +#if (USHRT_MAX == 0xFFU) +#define ECRYPT_I8T_IS_BYTE +#endif - #endif +#endif - #if (USHRT_MAX / 0xFFU > 0xFFU) - #ifndef I16T - #define I16T short - #define U16C(v) (v##U) - #endif +#if (USHRT_MAX / 0xFFU > 0xFFU) +#ifndef I16T +#define I16T short +#define U16C(v) (v##U) +#endif - #if (USHRT_MAX / 0xFFFFU > 0xFFFFU) - #ifndef I32T - #define I32T short - #define U32C(v) (v##U) - #endif +#if (USHRT_MAX / 0xFFFFU > 0xFFFFU) +#ifndef I32T +#define I32T short +#define U32C(v) (v##U) +#endif - #if (USHRT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) - #ifndef I64T - #define I64T short - #define U64C(v) (v##U) - #define ECRYPT_NATIVE64 - #endif +#if (USHRT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) +#ifndef I64T +#define I64T short +#define U64C(v) (v##U) +#define ECRYPT_NATIVE64 +#endif - #endif - #endif - #endif +#endif +#endif +#endif #endif /* --- check int --- */ #if (UINT_MAX / 0xFU > 0xFU) - #ifndef I8T - #define I8T int - #define U8C(v) (v##U) +#ifndef I8T +#define I8T int +#define U8C(v) (v##U) - #if (ULONG_MAX == 0xFFU) - #define ECRYPT_I8T_IS_BYTE - #endif +#if (ULONG_MAX == 0xFFU) +#define ECRYPT_I8T_IS_BYTE +#endif - #endif +#endif - #if (UINT_MAX / 0xFFU > 0xFFU) - #ifndef I16T - #define I16T int - #define U16C(v) (v##U) - #endif +#if (UINT_MAX / 0xFFU > 0xFFU) +#ifndef I16T +#define I16T int +#define U16C(v) (v##U) +#endif - #if (UINT_MAX / 0xFFFFU > 0xFFFFU) - #ifndef I32T - #define I32T int - #define U32C(v) (v##U) - #endif +#if (UINT_MAX / 0xFFFFU > 0xFFFFU) +#ifndef I32T +#define I32T int +#define U32C(v) (v##U) +#endif - #if (UINT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) - #ifndef I64T - #define I64T int - #define U64C(v) (v##U) - #define ECRYPT_NATIVE64 - #endif +#if (UINT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) +#ifndef I64T +#define I64T int +#define U64C(v) (v##U) +#define ECRYPT_NATIVE64 +#endif - #endif - #endif - #endif +#endif +#endif +#endif #endif /* --- check long --- */ #if (ULONG_MAX / 0xFUL > 0xFUL) - #ifndef I8T - #define I8T long - #define U8C(v) (v##UL) +#ifndef I8T +#define I8T long +#define U8C(v) (v##UL) - #if (ULONG_MAX == 0xFFUL) - #define ECRYPT_I8T_IS_BYTE - #endif +#if (ULONG_MAX == 0xFFUL) +#define ECRYPT_I8T_IS_BYTE +#endif - #endif +#endif - #if (ULONG_MAX / 0xFFUL > 0xFFUL) - #ifndef I16T - #define I16T long - #define U16C(v) (v##UL) - #endif +#if (ULONG_MAX / 0xFFUL > 0xFFUL) +#ifndef I16T +#define I16T long +#define U16C(v) (v##UL) +#endif - #if (ULONG_MAX / 0xFFFFUL > 0xFFFFUL) - #ifndef I32T - #define I32T long - #define U32C(v) (v##UL) - #endif +#if (ULONG_MAX / 0xFFFFUL > 0xFFFFUL) +#ifndef I32T +#define I32T long +#define U32C(v) (v##UL) +#endif - #if (ULONG_MAX / 0xFFFFFFFFUL > 0xFFFFFFFFUL) - #ifndef I64T - #define I64T long - #define U64C(v) (v##UL) - #define ECRYPT_NATIVE64 - #endif +#if (ULONG_MAX / 0xFFFFFFFFUL > 0xFFFFFFFFUL) +#ifndef I64T +#define I64T long +#define U64C(v) (v##UL) +#define ECRYPT_NATIVE64 +#endif - #endif - #endif - #endif +#endif +#endif +#endif #endif /* --- check long long --- */ #ifdef ULLONG_MAX - #if (ULLONG_MAX / 0xFULL > 0xFULL) - #ifndef I8T - #define I8T long long - #define U8C(v) (v##ULL) +#if (ULLONG_MAX / 0xFULL > 0xFULL) +#ifndef I8T +#define I8T long long +#define U8C(v) (v##ULL) - #if (ULLONG_MAX == 0xFFULL) - #define ECRYPT_I8T_IS_BYTE - #endif +#if (ULLONG_MAX == 0xFFULL) +#define ECRYPT_I8T_IS_BYTE +#endif - #endif +#endif - #if (ULLONG_MAX / 0xFFULL > 0xFFULL) - #ifndef I16T - #define I16T long long - #define U16C(v) (v##ULL) - #endif +#if (ULLONG_MAX / 0xFFULL > 0xFFULL) +#ifndef I16T +#define I16T long long +#define U16C(v) (v##ULL) +#endif - #if (ULLONG_MAX / 0xFFFFULL > 0xFFFFULL) - #ifndef I32T - #define I32T long long - #define U32C(v) (v##ULL) - #endif +#if (ULLONG_MAX / 0xFFFFULL > 0xFFFFULL) +#ifndef I32T +#define I32T long long +#define U32C(v) (v##ULL) +#endif - #if (ULLONG_MAX / 0xFFFFFFFFULL > 0xFFFFFFFFULL) - #ifndef I64T - #define I64T long long - #define U64C(v) (v##ULL) - #endif +#if (ULLONG_MAX / 0xFFFFFFFFULL > 0xFFFFFFFFULL) +#ifndef I64T +#define I64T long long +#define U64C(v) (v##ULL) +#endif - #endif - #endif - #endif - #endif +#endif +#endif +#endif +#endif #endif @@ -264,13 +264,13 @@ #ifdef _UI64_MAX - #if (_UI64_MAX / 0xFFFFFFFFui64 > 0xFFFFFFFFui64) - #ifndef I64T - #define I64T __int64 - #define U64C(v) (v##ui64) - #endif +#if (_UI64_MAX / 0xFFFFFFFFui64 > 0xFFFFFFFFui64) +#ifndef I64T +#define I64T __int64 +#define U64C(v) (v##ui64) +#endif - #endif +#endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-machine.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-machine.h index a3eba88..48788a8 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-machine.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-machine.h @@ -1,8 +1,8 @@ /****************************************************************************** -* Filename: sw_ecrypt-machine.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ + * Filename: sw_ecrypt-machine.h + * Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) + * Revision: 47308 + ******************************************************************************/ /* ecrypt-machine.h */ /* @@ -16,23 +16,23 @@ #if (defined(ECRYPT_DEFAULT_ROT) && !defined(ECRYPT_MACHINE_ROT)) - #define ECRYPT_MACHINE_ROT +#define ECRYPT_MACHINE_ROT - #if (defined(WIN32) && defined(_MSC_VER)) +#if (defined(WIN32) && defined(_MSC_VER)) - #undef ROTL32 - #undef ROTR32 - #undef ROTL64 - #undef ROTR64 +#undef ROTL32 +#undef ROTR32 +#undef ROTL64 +#undef ROTR64 - #include +#include - #define ROTL32(v, n) _lrotl(v, n) - #define ROTR32(v, n) _lrotr(v, n) - #define ROTL64(v, n) _rotl64(v, n) - #define ROTR64(v, n) _rotr64(v, n) +#define ROTL32(v, n) _lrotl(v, n) +#define ROTR32(v, n) _lrotr(v, n) +#define ROTL64(v, n) _rotl64(v, n) +#define ROTR64(v, n) _rotr64(v, n) - #endif +#endif #endif @@ -40,11 +40,11 @@ #if (defined(ECRYPT_DEFAULT_SWAP) && !defined(ECRYPT_MACHINE_SWAP)) - #define ECRYPT_MACHINE_SWAP +#define ECRYPT_MACHINE_SWAP - /* - * If you want to overwrite the default swap macros, put it here. And so on. - */ +/* + * If you want to overwrite the default swap macros, put it here. And so on. + */ #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-portable.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-portable.h index 600c718..067451a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-portable.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-portable.h @@ -1,8 +1,8 @@ /****************************************************************************** -* Filename: sw_ecrypt-portable.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ + * Filename: sw_ecrypt-portable.h + * Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) + * Revision: 47308 + ******************************************************************************/ /* ecrypt-portable.h */ /* @@ -46,23 +46,23 @@ */ #ifdef I8T - typedef signed I8T s8; - typedef unsigned I8T u8; +typedef signed I8T s8; +typedef unsigned I8T u8; #endif #ifdef I16T - typedef signed I16T s16; - typedef unsigned I16T u16; +typedef signed I16T s16; +typedef unsigned I16T u16; #endif #ifdef I32T - typedef signed I32T s32; - typedef unsigned I32T u32; +typedef signed I32T s32; +typedef unsigned I32T u32; #endif #ifdef I64T - typedef signed I64T s64; - typedef unsigned I64T u64; +typedef signed I64T s64; +typedef unsigned I64T u64; #endif /* @@ -113,13 +113,13 @@ #define SWAP16(v) \ ROTL16(v, 8) -#define SWAP32(v) \ - ((ROTL32(v, 8) & U32C(0x00FF00FF)) | \ +#define SWAP32(v) \ + ((ROTL32(v, 8) & U32C(0x00FF00FF)) | \ (ROTL32(v, 24) & U32C(0xFF00FF00))) #ifdef ECRYPT_NATIVE64 -#define SWAP64(v) \ - ((ROTL64(v, 8) & U64C(0x000000FF000000FF)) | \ +#define SWAP64(v) \ + ((ROTL64(v, 8) & U64C(0x000000FF000000FF)) | \ (ROTL64(v, 24) & U64C(0x0000FF000000FF00)) | \ (ROTL64(v, 40) & U64C(0x00FF000000FF0000)) | \ (ROTL64(v, 56) & U64C(0xFF000000FF000000))) @@ -133,23 +133,23 @@ #define ECRYPT_DEFAULT_WTOW #ifdef ECRYPT_LITTLE_ENDIAN - #define U16TO16_LITTLE(v) (v) - #define U32TO32_LITTLE(v) (v) - #define U64TO64_LITTLE(v) (v) +#define U16TO16_LITTLE(v) (v) +#define U32TO32_LITTLE(v) (v) +#define U64TO64_LITTLE(v) (v) - #define U16TO16_BIG(v) SWAP16(v) - #define U32TO32_BIG(v) SWAP32(v) - #define U64TO64_BIG(v) SWAP64(v) +#define U16TO16_BIG(v) SWAP16(v) +#define U32TO32_BIG(v) SWAP32(v) +#define U64TO64_BIG(v) SWAP64(v) #endif #ifdef ECRYPT_BIG_ENDIAN - #define U16TO16_LITTLE(v) SWAP16(v) - #define U32TO32_LITTLE(v) SWAP32(v) - #define U64TO64_LITTLE(v) SWAP64(v) +#define U16TO16_LITTLE(v) SWAP16(v) +#define U32TO32_LITTLE(v) SWAP32(v) +#define U64TO64_LITTLE(v) SWAP64(v) - #define U16TO16_BIG(v) (v) - #define U32TO32_BIG(v) (v) - #define U64TO64_BIG(v) (v) +#define U16TO16_BIG(v) (v) +#define U32TO32_BIG(v) (v) +#define U64TO64_BIG(v) (v) #endif #include "sw_ecrypt-machine.h" @@ -163,38 +163,38 @@ #if (!defined(ECRYPT_UNKNOWN) && defined(ECRYPT_I8T_IS_BYTE)) -#define U8TO16_LITTLE(p) U16TO16_LITTLE(((u16*)(p))[0]) -#define U8TO32_LITTLE(p) U32TO32_LITTLE(((u32*)(p))[0]) -#define U8TO64_LITTLE(p) U64TO64_LITTLE(((u64*)(p))[0]) +#define U8TO16_LITTLE(p) U16TO16_LITTLE(((u16 *)(p))[0]) +#define U8TO32_LITTLE(p) U32TO32_LITTLE(((u32 *)(p))[0]) +#define U8TO64_LITTLE(p) U64TO64_LITTLE(((u64 *)(p))[0]) -#define U8TO16_BIG(p) U16TO16_BIG(((u16*)(p))[0]) -#define U8TO32_BIG(p) U32TO32_BIG(((u32*)(p))[0]) -#define U8TO64_BIG(p) U64TO64_BIG(((u64*)(p))[0]) +#define U8TO16_BIG(p) U16TO16_BIG(((u16 *)(p))[0]) +#define U8TO32_BIG(p) U32TO32_BIG(((u32 *)(p))[0]) +#define U8TO64_BIG(p) U64TO64_BIG(((u64 *)(p))[0]) -#define U16TO8_LITTLE(p, v) (((u16*)(p))[0] = U16TO16_LITTLE(v)) -#define U32TO8_LITTLE(p, v) (((u32*)(p))[0] = U32TO32_LITTLE(v)) -#define U64TO8_LITTLE(p, v) (((u64*)(p))[0] = U64TO64_LITTLE(v)) +#define U16TO8_LITTLE(p, v) (((u16 *)(p))[0] = U16TO16_LITTLE(v)) +#define U32TO8_LITTLE(p, v) (((u32 *)(p))[0] = U32TO32_LITTLE(v)) +#define U64TO8_LITTLE(p, v) (((u64 *)(p))[0] = U64TO64_LITTLE(v)) -#define U16TO8_BIG(p, v) (((u16*)(p))[0] = U16TO16_BIG(v)) -#define U32TO8_BIG(p, v) (((u32*)(p))[0] = U32TO32_BIG(v)) -#define U64TO8_BIG(p, v) (((u64*)(p))[0] = U64TO64_BIG(v)) +#define U16TO8_BIG(p, v) (((u16 *)(p))[0] = U16TO16_BIG(v)) +#define U32TO8_BIG(p, v) (((u32 *)(p))[0] = U32TO32_BIG(v)) +#define U64TO8_BIG(p, v) (((u64 *)(p))[0] = U64TO64_BIG(v)) #else #define U8TO16_LITTLE(p) \ - (((u16)((p)[0]) ) | \ - ((u16)((p)[1]) << 8)) + (((u16)((p)[0])) | \ + ((u16)((p)[1]) << 8)) -#define U8TO32_LITTLE(p) \ - (((u32)((p)[0]) ) | \ - ((u32)((p)[1]) << 8) | \ +#define U8TO32_LITTLE(p) \ + (((u32)((p)[0])) | \ + ((u32)((p)[1]) << 8) | \ ((u32)((p)[2]) << 16) | \ ((u32)((p)[3]) << 24)) #ifdef ECRYPT_NATIVE64 -#define U8TO64_LITTLE(p) \ - (((u64)((p)[0]) ) | \ - ((u64)((p)[1]) << 8) | \ +#define U8TO64_LITTLE(p) \ + (((u64)((p)[0])) | \ + ((u64)((p)[1]) << 8) | \ ((u64)((p)[2]) << 16) | \ ((u64)((p)[3]) << 24) | \ ((u64)((p)[4]) << 32) | \ @@ -206,50 +206,53 @@ ((u64)U8TO32_LITTLE(p) | ((u64)U8TO32_LITTLE((p) + 4) << 32)) #endif -#define U8TO16_BIG(p) \ - (((u16)((p)[0]) << 8) | \ - ((u16)((p)[1]) )) +#define U8TO16_BIG(p) \ + (((u16)((p)[0]) << 8) | \ + ((u16)((p)[1]))) -#define U8TO32_BIG(p) \ +#define U8TO32_BIG(p) \ (((u32)((p)[0]) << 24) | \ ((u32)((p)[1]) << 16) | \ - ((u32)((p)[2]) << 8) | \ - ((u32)((p)[3]) )) + ((u32)((p)[2]) << 8) | \ + ((u32)((p)[3]))) #ifdef ECRYPT_NATIVE64 -#define U8TO64_BIG(p) \ +#define U8TO64_BIG(p) \ (((u64)((p)[0]) << 56) | \ ((u64)((p)[1]) << 48) | \ ((u64)((p)[2]) << 40) | \ ((u64)((p)[3]) << 32) | \ ((u64)((p)[4]) << 24) | \ ((u64)((p)[5]) << 16) | \ - ((u64)((p)[6]) << 8) | \ - ((u64)((p)[7]) )) + ((u64)((p)[6]) << 8) | \ + ((u64)((p)[7]))) #else #define U8TO64_BIG(p) \ (((u64)U8TO32_BIG(p) << 32) | (u64)U8TO32_BIG((p) + 4)) #endif -#define U16TO8_LITTLE(p, v) \ - do { \ - (p)[0] = U8V((v) ); \ - (p)[1] = U8V((v) >> 8); \ +#define U16TO8_LITTLE(p, v) \ + do \ + { \ + (p)[0] = U8V((v)); \ + (p)[1] = U8V((v) >> 8); \ } while (0) -#define U32TO8_LITTLE(p, v) \ - do { \ - (p)[0] = U8V((v) ); \ - (p)[1] = U8V((v) >> 8); \ +#define U32TO8_LITTLE(p, v) \ + do \ + { \ + (p)[0] = U8V((v)); \ + (p)[1] = U8V((v) >> 8); \ (p)[2] = U8V((v) >> 16); \ (p)[3] = U8V((v) >> 24); \ } while (0) #ifdef ECRYPT_NATIVE64 -#define U64TO8_LITTLE(p, v) \ - do { \ - (p)[0] = U8V((v) ); \ - (p)[1] = U8V((v) >> 8); \ +#define U64TO8_LITTLE(p, v) \ + do \ + { \ + (p)[0] = U8V((v)); \ + (p)[1] = U8V((v) >> 8); \ (p)[2] = U8V((v) >> 16); \ (p)[3] = U8V((v) >> 24); \ (p)[4] = U8V((v) >> 32); \ @@ -258,44 +261,49 @@ (p)[7] = U8V((v) >> 56); \ } while (0) #else -#define U64TO8_LITTLE(p, v) \ - do { \ - U32TO8_LITTLE((p), U32V((v) )); \ +#define U64TO8_LITTLE(p, v) \ + do \ + { \ + U32TO8_LITTLE((p), U32V((v))); \ U32TO8_LITTLE((p) + 4, U32V((v) >> 32)); \ } while (0) #endif -#define U16TO8_BIG(p, v) \ - do { \ - (p)[0] = U8V((v) ); \ - (p)[1] = U8V((v) >> 8); \ +#define U16TO8_BIG(p, v) \ + do \ + { \ + (p)[0] = U8V((v)); \ + (p)[1] = U8V((v) >> 8); \ } while (0) -#define U32TO8_BIG(p, v) \ - do { \ +#define U32TO8_BIG(p, v) \ + do \ + { \ (p)[0] = U8V((v) >> 24); \ (p)[1] = U8V((v) >> 16); \ - (p)[2] = U8V((v) >> 8); \ - (p)[3] = U8V((v) ); \ + (p)[2] = U8V((v) >> 8); \ + (p)[3] = U8V((v)); \ } while (0) #ifdef ECRYPT_NATIVE64 -#define U64TO8_BIG(p, v) \ - do { \ +#define U64TO8_BIG(p, v) \ + do \ + { \ (p)[0] = U8V((v) >> 56); \ (p)[1] = U8V((v) >> 48); \ (p)[2] = U8V((v) >> 40); \ (p)[3] = U8V((v) >> 32); \ (p)[4] = U8V((v) >> 24); \ (p)[5] = U8V((v) >> 16); \ - (p)[6] = U8V((v) >> 8); \ - (p)[7] = U8V((v) ); \ + (p)[6] = U8V((v) >> 8); \ + (p)[7] = U8V((v)); \ } while (0) #else -#define U64TO8_BIG(p, v) \ - do { \ - U32TO8_BIG((p), U32V((v) >> 32)); \ - U32TO8_BIG((p) + 4, U32V((v) )); \ +#define U64TO8_BIG(p, v) \ + do \ + { \ + U32TO8_BIG((p), U32V((v) >> 32)); \ + U32TO8_BIG((p) + 4, U32V((v))); \ } while (0) #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-sync.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-sync.h index 7d9a344..e3ac4d2 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-sync.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_ecrypt-sync.h @@ -1,8 +1,8 @@ /****************************************************************************** -* Filename: sw_ecrypt-sync.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ + * Filename: sw_ecrypt-sync.h + * Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) + * Revision: 47308 + ******************************************************************************/ /* ecrypt-sync.h */ /* @@ -42,11 +42,11 @@ * All sizes are in bits. */ -#define ECRYPT_MAXKEYSIZE 256 /* [edit] */ -#define ECRYPT_KEYSIZE(i) (128 + (i)*128) /* [edit] */ +#define ECRYPT_MAXKEYSIZE 256 /* [edit] */ +#define ECRYPT_KEYSIZE(i) (128 + (i) * 128) /* [edit] */ -#define ECRYPT_MAXIVSIZE 64 /* [edit] */ -#define ECRYPT_IVSIZE(i) (64 + (i)*64) /* [edit] */ +#define ECRYPT_MAXIVSIZE 64 /* [edit] */ +#define ECRYPT_IVSIZE(i) (64 + (i) * 64) /* [edit] */ /* ------------------------------------------------------------------------- */ @@ -59,12 +59,12 @@ typedef struct { - u32 input[16]; /* could be compressed */ - /* - * [edit] - * - * Put here all state variable needed during the encryption process. - */ + u32 input[16]; /* could be compressed */ + /* + * [edit] + * + * Put here all state variable needed during the encryption process. + */ } ECRYPT_ctx; /* ------------------------------------------------------------------------- */ @@ -86,8 +86,8 @@ void ECRYPT_init(void); void ECRYPT_keysetup( ECRYPT_ctx* ctx, const u8* key, - u32 keysize, /* Key size in bits. */ - u32 ivsize); /* IV size in bits. */ + u32 keysize, /* Key size in bits. */ + u32 ivsize); /* IV size in bits. */ /* * IV setup. After having called ECRYPT_keysetup(), the user is @@ -141,13 +141,13 @@ void ECRYPT_encrypt_bytes( ECRYPT_ctx* ctx, const u8* plaintext, u8* ciphertext, - u32 msglen); /* Message length in bytes. */ + u32 msglen); /* Message length in bytes. */ void ECRYPT_decrypt_bytes( ECRYPT_ctx* ctx, const u8* ciphertext, u8* plaintext, - u32 msglen); /* Message length in bytes. */ + u32 msglen); /* Message length in bytes. */ /* ------------------------------------------------------------------------- */ @@ -167,7 +167,7 @@ void ECRYPT_decrypt_bytes( void ECRYPT_keystream_bytes( ECRYPT_ctx* ctx, u8* keystream, - u32 length); /* Length of keystream in bytes. */ + u32 length); /* Length of keystream in bytes. */ #endif @@ -188,7 +188,7 @@ void ECRYPT_keystream_bytes( * "ecrypt-sync.c". If you want to implement them differently, please * undef the ECRYPT_USES_DEFAULT_ALL_IN_ONE flag. */ -#define ECRYPT_USES_DEFAULT_ALL_IN_ONE /* [edit] */ +#define ECRYPT_USES_DEFAULT_ALL_IN_ONE /* [edit] */ void ECRYPT_encrypt_packet( ECRYPT_ctx* ctx, @@ -213,23 +213,23 @@ void ECRYPT_decrypt_packet( * declared below. */ -#define ECRYPT_BLOCKLENGTH 64 /* [edit] */ +#define ECRYPT_BLOCKLENGTH 64 /* [edit] */ -#define ECRYPT_USES_DEFAULT_BLOCK_MACROS /* [edit] */ +#define ECRYPT_USES_DEFAULT_BLOCK_MACROS /* [edit] */ #ifdef ECRYPT_USES_DEFAULT_BLOCK_MACROS -#define ECRYPT_encrypt_blocks(ctx, plaintext, ciphertext, blocks) \ - ECRYPT_encrypt_bytes(ctx, plaintext, ciphertext, \ +#define ECRYPT_encrypt_blocks(ctx, plaintext, ciphertext, blocks) \ + ECRYPT_encrypt_bytes(ctx, plaintext, ciphertext, \ (blocks) * ECRYPT_BLOCKLENGTH) -#define ECRYPT_decrypt_blocks(ctx, ciphertext, plaintext, blocks) \ - ECRYPT_decrypt_bytes(ctx, ciphertext, plaintext, \ +#define ECRYPT_decrypt_blocks(ctx, ciphertext, plaintext, blocks) \ + ECRYPT_decrypt_bytes(ctx, ciphertext, plaintext, \ (blocks) * ECRYPT_BLOCKLENGTH) #ifdef ECRYPT_GENERATES_KEYSTREAM -#define ECRYPT_keystream_blocks(ctx, keystream, blocks) \ - ECRYPT_keystream_bytes(ctx, keystream, \ +#define ECRYPT_keystream_blocks(ctx, keystream, blocks) \ + ECRYPT_keystream_bytes(ctx, keystream, \ (blocks) * ECRYPT_BLOCKLENGTH) #endif @@ -240,20 +240,20 @@ void ECRYPT_encrypt_blocks( ECRYPT_ctx* ctx, const u8* plaintext, u8* ciphertext, - u32 blocks); /* Message length in blocks. */ + u32 blocks); /* Message length in blocks. */ void ECRYPT_decrypt_blocks( ECRYPT_ctx* ctx, const u8* ciphertext, u8* plaintext, - u32 blocks); /* Message length in blocks. */ + u32 blocks); /* Message length in blocks. */ #ifdef ECRYPT_GENERATES_KEYSTREAM void ECRYPT_keystream_blocks( ECRYPT_ctx* ctx, const u8* keystream, - u32 blocks); /* Keystream length in blocks. */ + u32 blocks); /* Keystream length in blocks. */ #endif @@ -269,14 +269,14 @@ void ECRYPT_keystream_blocks( * 10). Note also that all variants should have exactly the same * external interface (i.e., the same ECRYPT_BLOCKLENGTH, etc.). */ -#define ECRYPT_MAXVARIANT 1 /* [edit] */ +#define ECRYPT_MAXVARIANT 1 /* [edit] */ #ifndef ECRYPT_VARIANT - #define ECRYPT_VARIANT 1 +#define ECRYPT_VARIANT 1 #endif #if (ECRYPT_VARIANT > ECRYPT_MAXVARIANT) - #error this variant does not exist +#error this variant does not exist #endif /* ------------------------------------------------------------------------- */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_poly1305-donna-32.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_poly1305-donna-32.h index 3e4eb10..73b809a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_poly1305-donna-32.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_poly1305-donna-32.h @@ -1,18 +1,18 @@ /****************************************************************************** -* Filename: sw_poly1305-donna-32.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ + * Filename: sw_poly1305-donna-32.h + * Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) + * Revision: 47308 + ******************************************************************************/ /* poly1305 implementation using 32 bit * 32 bit = 64 bit multiplication and 64 bit addition */ #if defined(_MSC_VER) - #define POLY1305_NOINLINE __declspec(noinline) +#define POLY1305_NOINLINE __declspec(noinline) #elif defined(__GNUC__) - #define POLY1305_NOINLINE __attribute__((noinline)) +#define POLY1305_NOINLINE __attribute__((noinline)) #else - #define POLY1305_NOINLINE +#define POLY1305_NOINLINE #endif #define poly1305_block_size 16 @@ -20,29 +20,28 @@ /* 17 + sizeof(size_t) + 14*sizeof(unsigned long) */ typedef struct { - unsigned long r[5]; - unsigned long h[5]; - unsigned long pad[4]; - size_t leftover; - unsigned char buffer[poly1305_block_size]; - unsigned char final; + unsigned long r[5]; + unsigned long h[5]; + unsigned long pad[4]; + size_t leftover; + unsigned char buffer[poly1305_block_size]; + unsigned char final; } poly1305_state_internal_t; /* interpret four 8 bit unsigned integers as a 32 bit unsigned integer in little endian */ static unsigned long U8TO32(const unsigned char* p) { - return - (((unsigned long)(p[0] & 0xff) ) | - ((unsigned long)(p[1] & 0xff) << 8) | - ((unsigned long)(p[2] & 0xff) << 16) | - ((unsigned long)(p[3] & 0xff) << 24)); + return (((unsigned long)(p[0] & 0xff)) | + ((unsigned long)(p[1] & 0xff) << 8) | + ((unsigned long)(p[2] & 0xff) << 16) | + ((unsigned long)(p[3] & 0xff) << 24)); } /* store a 32 bit unsigned integer as four 8 bit unsigned integers in little endian */ static void U32TO8(unsigned char* p, unsigned long v) { - p[0] = (v ) & 0xff; - p[1] = (v >> 8) & 0xff; + p[0] = (v) & 0xff; + p[1] = (v >> 8) & 0xff; p[2] = (v >> 16) & 0xff; p[3] = (v >> 24) & 0xff; } @@ -52,10 +51,10 @@ void poly1305_init(poly1305_context* ctx, const unsigned char key[32]) poly1305_state_internal_t* st = (poly1305_state_internal_t*)ctx; /* r &= 0xffffffc0ffffffc0ffffffc0fffffff */ - st->r[0] = (U8TO32(&key[ 0]) ) & 0x3ffffff; - st->r[1] = (U8TO32(&key[ 3]) >> 2) & 0x3ffff03; - st->r[2] = (U8TO32(&key[ 6]) >> 4) & 0x3ffc0ff; - st->r[3] = (U8TO32(&key[ 9]) >> 6) & 0x3f03fff; + st->r[0] = (U8TO32(&key[0])) & 0x3ffffff; + st->r[1] = (U8TO32(&key[3]) >> 2) & 0x3ffff03; + st->r[2] = (U8TO32(&key[6]) >> 4) & 0x3ffc0ff; + st->r[3] = (U8TO32(&key[9]) >> 6) & 0x3f03fff; st->r[4] = (U8TO32(&key[12]) >> 8) & 0x00fffff; /* h = 0 */ @@ -104,7 +103,7 @@ static void poly1305_blocks(poly1305_state_internal_t* st, const unsigned char* while (bytes >= poly1305_block_size) { /* h += m[i] */ - h0 += (U8TO32(m + 0) ) & 0x3ffffff; + h0 += (U8TO32(m + 0)) & 0x3ffffff; h1 += (U8TO32(m + 3) >> 2) & 0x3ffffff; h2 += (U8TO32(m + 6) >> 4) & 0x3ffffff; h3 += (U8TO32(m + 9) >> 6) & 0x3ffffff; @@ -133,8 +132,8 @@ static void poly1305_blocks(poly1305_state_internal_t* st, const unsigned char* c = (unsigned long)(d4 >> 26); h4 = (unsigned long)d4 & 0x3ffffff; h0 += c * 5; - c = (h0 >> 26); - h0 = h0 & 0x3ffffff; + c = (h0 >> 26); + h0 = h0 & 0x3ffffff; h1 += c; m += poly1305_block_size; @@ -178,19 +177,19 @@ POLY1305_NOINLINE void poly1305_finish(poly1305_context* ctx, unsigned char mac[ c = h1 >> 26; h1 = h1 & 0x3ffffff; - h2 += c; + h2 += c; c = h2 >> 26; h2 = h2 & 0x3ffffff; - h3 += c; + h3 += c; c = h3 >> 26; h3 = h3 & 0x3ffffff; - h4 += c; + h4 += c; c = h4 >> 26; h4 = h4 & 0x3ffffff; h0 += c * 5; c = h0 >> 26; h0 = h0 & 0x3ffffff; - h1 += c; + h1 += c; /* compute h + -p */ g0 = h0 + 5; @@ -222,13 +221,13 @@ POLY1305_NOINLINE void poly1305_finish(poly1305_context* ctx, unsigned char mac[ h4 = (h4 & mask) | g4; /* h = h % (2^128) */ - h0 = ((h0 ) | (h1 << 26)) & 0xffffffff; - h1 = ((h1 >> 6) | (h2 << 20)) & 0xffffffff; + h0 = ((h0) | (h1 << 26)) & 0xffffffff; + h1 = ((h1 >> 6) | (h2 << 20)) & 0xffffffff; h2 = ((h2 >> 12) | (h3 << 14)) & 0xffffffff; - h3 = ((h3 >> 18) | (h4 << 8)) & 0xffffffff; + h3 = ((h3 >> 18) | (h4 << 8)) & 0xffffffff; /* mac = (h + pad) % (2^128) */ - f = (unsigned long long)h0 + st->pad[0] ; + f = (unsigned long long)h0 + st->pad[0]; h0 = (unsigned long)f; f = (unsigned long long)h1 + st->pad[1] + (f >> 32); h1 = (unsigned long)f; @@ -237,9 +236,9 @@ POLY1305_NOINLINE void poly1305_finish(poly1305_context* ctx, unsigned char mac[ f = (unsigned long long)h3 + st->pad[3] + (f >> 32); h3 = (unsigned long)f; - U32TO8(mac + 0, h0); - U32TO8(mac + 4, h1); - U32TO8(mac + 8, h2); + U32TO8(mac + 0, h0); + U32TO8(mac + 4, h1); + U32TO8(mac + 8, h2); U32TO8(mac + 12, h3); /* zero out the state */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_poly1305-donna.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_poly1305-donna.h index a544927..3230064 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_poly1305-donna.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sw_poly1305-donna.h @@ -1,8 +1,8 @@ /****************************************************************************** -* Filename: sw_poly1305-donna.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ + * Filename: sw_poly1305-donna.h + * Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) + * Revision: 47308 + ******************************************************************************/ #ifndef POLY1305_DONNA_H #define POLY1305_DONNA_H @@ -11,8 +11,8 @@ typedef struct { - size_t aligner; - unsigned char opaque[136]; + size_t aligner; + unsigned char opaque[136]; } poly1305_context; void poly1305_init(poly1305_context* ctx, const unsigned char key[32]); diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sys_ctrl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sys_ctrl.h index 7ecddc4..356974c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sys_ctrl.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/sys_ctrl.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: sys_ctrl.h -* Revised: 2018-09-17 14:58:51 +0200 (Mon, 17 Sep 2018) -* Revision: 52634 -* -* Description: Defines and prototypes for the System Controller. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: sys_ctrl.h + * Revised: 2018-09-17 14:58:51 +0200 (Mon, 17 Sep 2018) + * Revision: 52634 + * + * Description: Defines and prototypes for the System Controller. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,39 +55,37 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_sysctl.h" -#include "../inc/hw_prcm.h" -#include "../inc/hw_nvic.h" +#include "../inc/hw_adi_3_refsys.h" +#include "../inc/hw_aon_ioc.h" +#include "../inc/hw_aon_rtc.h" +#include "../inc/hw_aon_sysctl.h" #include "../inc/hw_aon_wuc.h" #include "../inc/hw_aux_wuc.h" -#include "../inc/hw_aon_ioc.h" #include "../inc/hw_ddi_0_osc.h" -#include "../inc/hw_rfc_pwr.h" -#include "../inc/hw_prcm.h" -#include "../inc/hw_adi_3_refsys.h" -#include "../inc/hw_aon_sysctl.h" -#include "../inc/hw_aon_rtc.h" #include "../inc/hw_fcfg1.h" -#include "interrupt.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_nvic.h" +#include "../inc/hw_prcm.h" +#include "../inc/hw_rfc_pwr.h" +#include "../inc/hw_sysctl.h" +#include "../inc/hw_types.h" +#include "adi.h" +#include "aon_wuc.h" +#include "aux_wuc.h" +#include "cpu.h" +#include "ddi.h" #include "debug.h" -#include "pwr_ctrl.h" +#include "interrupt.h" #include "osc.h" #include "prcm.h" -#include "aux_wuc.h" -#include "aon_wuc.h" -#include "adi.h" -#include "ddi.h" -#include "cpu.h" +#include "pwr_ctrl.h" #include "vims.h" +#include +#include //***************************************************************************** // @@ -106,7 +104,7 @@ extern "C" #define SysCtrlSetRechargeBeforePowerDown NOROM_SysCtrlSetRechargeBeforePowerDown #define SysCtrlAdjustRechargeAfterPowerDown NOROM_SysCtrlAdjustRechargeAfterPowerDown #define SysCtrl_DCDC_VoltageConditionalControl NOROM_SysCtrl_DCDC_VoltageConditionalControl -#define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet +#define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet #endif //***************************************************************************** @@ -114,17 +112,17 @@ extern "C" // Defines for the settings of the main XOSC // //***************************************************************************** -#define SYSCTRL_SYSBUS_ON 0x00000001 -#define SYSCTRL_SYSBUS_OFF 0x00000000 +#define SYSCTRL_SYSBUS_ON 0x00000001 +#define SYSCTRL_SYSBUS_OFF 0x00000000 //***************************************************************************** // // Defines for the different power modes of the System CPU // //***************************************************************************** -#define CPU_RUN 0x00000000 -#define CPU_SLEEP 0x00000001 -#define CPU_DEEP_SLEEP 0x00000002 +#define CPU_RUN 0x00000000 +#define CPU_SLEEP 0x00000001 +#define CPU_DEEP_SLEEP 0x00000002 //***************************************************************************** // @@ -132,7 +130,7 @@ extern "C" // //***************************************************************************** #define XOSC_IN_HIGH_POWER_MODE 0 // When xosc_hf is in HIGH_POWER_XOSC -#define XOSC_IN_LOW_POWER_MODE 1 // When xosc_hf is in LOW_POWER_XOSC +#define XOSC_IN_LOW_POWER_MODE 1 // When xosc_hf is in LOW_POWER_XOSC //***************************************************************************** // @@ -153,10 +151,10 @@ extern "C" // //***************************************************************************** __STATIC_INLINE uint32_t -SysCtrlClockGet( void ) +SysCtrlClockGet(void) { // Return fixed clock speed - return ( GET_MCU_CLOCK ); + return (GET_MCU_CLOCK); } //***************************************************************************** @@ -230,7 +228,7 @@ SysCtrlAonUpdate(void) //! \return None // //***************************************************************************** -extern void SysCtrlSetRechargeBeforePowerDown( uint32_t xoscPowerMode ); +extern void SysCtrlSetRechargeBeforePowerDown(uint32_t xoscPowerMode); //***************************************************************************** // @@ -254,7 +252,7 @@ extern void SysCtrlSetRechargeBeforePowerDown( uint32_t xoscPowerMode ); //! \return None // //***************************************************************************** -extern void SysCtrlAdjustRechargeAfterPowerDown( uint32_t vddrRechargeMargin ); +extern void SysCtrlAdjustRechargeAfterPowerDown(uint32_t vddrRechargeMargin); //***************************************************************************** // @@ -271,20 +269,20 @@ extern void SysCtrlAdjustRechargeAfterPowerDown( uint32_t vddrRechargeMargin ); //! \return None // //***************************************************************************** -extern void SysCtrl_DCDC_VoltageConditionalControl( void ); +extern void SysCtrl_DCDC_VoltageConditionalControl(void); //***************************************************************************** // \name Return values from calling SysCtrlResetSourceGet() //@{ //***************************************************************************** -#define RSTSRC_PWR_ON (( AON_SYSCTL_RESETCTL_RESET_SRC_PWR_ON ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_PIN_RESET (( AON_SYSCTL_RESETCTL_RESET_SRC_PIN_RESET ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_VDDS_LOSS (( AON_SYSCTL_RESETCTL_RESET_SRC_VDDS_LOSS ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_VDDR_LOSS (( AON_SYSCTL_RESETCTL_RESET_SRC_VDDR_LOSS ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_CLK_LOSS (( AON_SYSCTL_RESETCTL_RESET_SRC_CLK_LOSS ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_SYSRESET (( AON_SYSCTL_RESETCTL_RESET_SRC_SYSRESET ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_WARMRESET (( AON_SYSCTL_RESETCTL_RESET_SRC_WARMRESET ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_WAKEUP_FROM_SHUTDOWN ((( AON_SYSCTL_RESETCTL_RESET_SRC_M ) >> ( AON_SYSCTL_RESETCTL_RESET_SRC_S )) + 1 ) +#define RSTSRC_PWR_ON ((AON_SYSCTL_RESETCTL_RESET_SRC_PWR_ON) >> (AON_SYSCTL_RESETCTL_RESET_SRC_S)) +#define RSTSRC_PIN_RESET ((AON_SYSCTL_RESETCTL_RESET_SRC_PIN_RESET) >> (AON_SYSCTL_RESETCTL_RESET_SRC_S)) +#define RSTSRC_VDDS_LOSS ((AON_SYSCTL_RESETCTL_RESET_SRC_VDDS_LOSS) >> (AON_SYSCTL_RESETCTL_RESET_SRC_S)) +#define RSTSRC_VDDR_LOSS ((AON_SYSCTL_RESETCTL_RESET_SRC_VDDR_LOSS) >> (AON_SYSCTL_RESETCTL_RESET_SRC_S)) +#define RSTSRC_CLK_LOSS ((AON_SYSCTL_RESETCTL_RESET_SRC_CLK_LOSS) >> (AON_SYSCTL_RESETCTL_RESET_SRC_S)) +#define RSTSRC_SYSRESET ((AON_SYSCTL_RESETCTL_RESET_SRC_SYSRESET) >> (AON_SYSCTL_RESETCTL_RESET_SRC_S)) +#define RSTSRC_WARMRESET ((AON_SYSCTL_RESETCTL_RESET_SRC_WARMRESET) >> (AON_SYSCTL_RESETCTL_RESET_SRC_S)) +#define RSTSRC_WAKEUP_FROM_SHUTDOWN (((AON_SYSCTL_RESETCTL_RESET_SRC_M) >> (AON_SYSCTL_RESETCTL_RESET_SRC_S)) + 1) //@} //***************************************************************************** @@ -306,7 +304,7 @@ extern void SysCtrl_DCDC_VoltageConditionalControl( void ); //! - \ref RSTSRC_WAKEUP_FROM_SHUTDOWN // //***************************************************************************** -extern uint32_t SysCtrlResetSourceGet( void ); +extern uint32_t SysCtrlResetSourceGet(void); //***************************************************************************** // @@ -316,15 +314,15 @@ extern uint32_t SysCtrlResetSourceGet( void ); // //***************************************************************************** __STATIC_INLINE void -SysCtrlSystemReset( void ) +SysCtrlSystemReset(void) { // Disable CPU interrupts CPUcpsid(); // Write reset register - HWREGBITW( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL, AON_SYSCTL_RESETCTL_SYSRESET_BITN ) = 1; + HWREGBITW(AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL, AON_SYSCTL_RESETCTL_SYSRESET_BITN) = 1; // Finally, wait until the above write propagates - while ( 1 ) + while (1) { // Do nothing, just wait for the reset (and never return from here) } @@ -383,20 +381,20 @@ SysCtrlClockLossResetDisable(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_SysCtrlSetRechargeBeforePowerDown -#undef SysCtrlSetRechargeBeforePowerDown +#undef SysCtrlSetRechargeBeforePowerDown #define SysCtrlSetRechargeBeforePowerDown ROM_SysCtrlSetRechargeBeforePowerDown #endif #ifdef ROM_SysCtrlAdjustRechargeAfterPowerDown -#undef SysCtrlAdjustRechargeAfterPowerDown +#undef SysCtrlAdjustRechargeAfterPowerDown #define SysCtrlAdjustRechargeAfterPowerDown ROM_SysCtrlAdjustRechargeAfterPowerDown #endif #ifdef ROM_SysCtrl_DCDC_VoltageConditionalControl -#undef SysCtrl_DCDC_VoltageConditionalControl +#undef SysCtrl_DCDC_VoltageConditionalControl #define SysCtrl_DCDC_VoltageConditionalControl ROM_SysCtrl_DCDC_VoltageConditionalControl #endif #ifdef ROM_SysCtrlResetSourceGet -#undef SysCtrlResetSourceGet -#define SysCtrlResetSourceGet ROM_SysCtrlResetSourceGet +#undef SysCtrlResetSourceGet +#define SysCtrlResetSourceGet ROM_SysCtrlResetSourceGet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/systick.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/systick.h index d065440..c471218 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/systick.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/systick.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: systick.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Prototypes for the SysTick driver. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: systick.h + * Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) + * Revision: 49048 + * + * Description: Prototypes for the SysTick driver. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,17 +55,16 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include #include "../inc/hw_ints.h" #include "../inc/hw_nvic.h" #include "../inc/hw_types.h" #include "debug.h" #include "interrupt.h" +#include +#include //***************************************************************************** // diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/systick_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/systick_doc.h index 70848fc..0eaecd3 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/systick_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/systick_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: systick_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: systick_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup systick_api //! @{ //! \section sec_systick Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/timer.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/timer.h index b010b3b..4110801 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/timer.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/timer.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: timer.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: timer.h + * Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) + * Revision: 49048 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //**************************************************************************** // @@ -53,18 +53,17 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif +#include "../inc/hw_gpt.h" +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" +#include "debug.h" +#include "interrupt.h" #include #include -#include "../inc/hw_ints.h" -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_gpt.h" -#include "interrupt.h" -#include "debug.h" //***************************************************************************** // @@ -80,14 +79,14 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define TimerConfigure NOROM_TimerConfigure -#define TimerLevelControl NOROM_TimerLevelControl -#define TimerStallControl NOROM_TimerStallControl -#define TimerWaitOnTriggerControl NOROM_TimerWaitOnTriggerControl -#define TimerIntRegister NOROM_TimerIntRegister -#define TimerIntUnregister NOROM_TimerIntUnregister -#define TimerMatchUpdateMode NOROM_TimerMatchUpdateMode -#define TimerIntervalLoadMode NOROM_TimerIntervalLoadMode +#define TimerConfigure NOROM_TimerConfigure +#define TimerLevelControl NOROM_TimerLevelControl +#define TimerStallControl NOROM_TimerStallControl +#define TimerWaitOnTriggerControl NOROM_TimerWaitOnTriggerControl +#define TimerIntRegister NOROM_TimerIntRegister +#define TimerIntUnregister NOROM_TimerIntUnregister +#define TimerMatchUpdateMode NOROM_TimerMatchUpdateMode +#define TimerIntervalLoadMode NOROM_TimerIntervalLoadMode #endif //***************************************************************************** @@ -95,29 +94,29 @@ extern "C" // Values that can be passed to TimerConfigure as the ui32Config parameter. // //***************************************************************************** -#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer -#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count timer -#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer -#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count timer -#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers -#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer -#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer -#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer -#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer -#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer -#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer -#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output +#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer +#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count timer +#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer +#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count timer +#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers +#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer +#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer +#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer +#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer +#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter +#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter +#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer +#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer +#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output +#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer +#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer +#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer +#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer +#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter +#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter +#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer +#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer +#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output //***************************************************************************** // @@ -126,25 +125,25 @@ extern "C" // TimerIntStatus. // //***************************************************************************** -#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt -#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt -#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt +#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt +#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt +#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt +#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt +#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt +#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt +#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt +#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt +#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt +#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt //***************************************************************************** // // Values that can be passed to TimerControlEvent as the ui32Event parameter. // //***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges +#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges +#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges +#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges //***************************************************************************** // @@ -152,39 +151,39 @@ extern "C" // parameter. // //***************************************************************************** -#define TIMER_A 0x000000FF // Timer A -#define TIMER_B 0x0000FF00 // Timer B -#define TIMER_BOTH 0x0000FFFF // Timer Both +#define TIMER_A 0x000000FF // Timer A +#define TIMER_B 0x0000FF00 // Timer B +#define TIMER_BOTH 0x0000FFFF // Timer Both //***************************************************************************** // // Values that can be passed to GPTSynchronize as the ui32Timers parameter // //***************************************************************************** -#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A -#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B -#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A -#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B -#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A -#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B -#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A -#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B +#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A +#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B +#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A +#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B +#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A +#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B +#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A +#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B //***************************************************************************** // // Values that can be passed to TimerMatchUpdateMode // //***************************************************************************** -#define TIMER_MATCHUPDATE_NEXTCYCLE 0x00000000 // Apply match register on next cycle -#define TIMER_MATCHUPDATE_TIMEOUT 0x00000001 // Apply match register on next timeout +#define TIMER_MATCHUPDATE_NEXTCYCLE 0x00000000 // Apply match register on next cycle +#define TIMER_MATCHUPDATE_TIMEOUT 0x00000001 // Apply match register on next timeout //***************************************************************************** // // Values that can be passed to TimerIntervalLoad // //***************************************************************************** -#define TIMER_INTERVALLOAD_NEXTCYCLE 0x00000000 // Load TxR register with the value in the TxILR register on the next clock cycle -#define TIMER_INTERVALLOAD_TIMEOUT 0x00000001 // Load TxR register with the value in the TxILR register on next timeout +#define TIMER_INTERVALLOAD_NEXTCYCLE 0x00000000 // Load TxR register with the value in the TxILR register on the next clock cycle +#define TIMER_INTERVALLOAD_TIMEOUT 0x00000001 // Load TxR register with the value in the TxILR register on next timeout //***************************************************************************** // @@ -522,8 +521,7 @@ TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer) (ui32Timer == TIMER_BOTH)); // Return the appropriate prescale value. - return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPR) : - HWREG(ui32Base + GPT_O_TBPR)); + return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPR) : HWREG(ui32Base + GPT_O_TBPR)); } //***************************************************************************** @@ -597,8 +595,7 @@ TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer) ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); // Return the appropriate prescale match value. - return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPMR) : - HWREG(ui32Base + GPT_O_TBPMR)); + return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPMR) : HWREG(ui32Base + GPT_O_TBPMR)); } //***************************************************************************** @@ -674,8 +671,7 @@ TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer) ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); // Return the appropriate load value. - return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAILR) : - HWREG(ui32Base + GPT_O_TBILR)); + return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAILR) : HWREG(ui32Base + GPT_O_TBILR)); } //***************************************************************************** @@ -706,8 +702,7 @@ TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer) ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); // Return the appropriate timer value. - return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAR) : - HWREG(ui32Base + GPT_O_TBR)); + return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAR) : HWREG(ui32Base + GPT_O_TBR)); } //***************************************************************************** @@ -786,8 +781,7 @@ TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer) ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); // Return the appropriate match value. - return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAMATCHR) : - HWREG(ui32Base + GPT_O_TBMATCHR)); + return ((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAMATCHR) : HWREG(ui32Base + GPT_O_TBMATCHR)); } //***************************************************************************** @@ -936,8 +930,7 @@ TimerIntStatus(uint32_t ui32Base, bool bMasked) // Return either the interrupt status or the raw interrupt status as // requested. - return (bMasked ? HWREG(ui32Base + GPT_O_MIS) : - HWREG(ui32Base + GPT_O_RIS)); + return (bMasked ? HWREG(ui32Base + GPT_O_MIS) : HWREG(ui32Base + GPT_O_RIS)); } //***************************************************************************** @@ -1123,36 +1116,36 @@ extern void TimerIntervalLoadMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_ #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_TimerConfigure -#undef TimerConfigure -#define TimerConfigure ROM_TimerConfigure +#undef TimerConfigure +#define TimerConfigure ROM_TimerConfigure #endif #ifdef ROM_TimerLevelControl -#undef TimerLevelControl -#define TimerLevelControl ROM_TimerLevelControl +#undef TimerLevelControl +#define TimerLevelControl ROM_TimerLevelControl #endif #ifdef ROM_TimerStallControl -#undef TimerStallControl -#define TimerStallControl ROM_TimerStallControl +#undef TimerStallControl +#define TimerStallControl ROM_TimerStallControl #endif #ifdef ROM_TimerWaitOnTriggerControl -#undef TimerWaitOnTriggerControl -#define TimerWaitOnTriggerControl ROM_TimerWaitOnTriggerControl +#undef TimerWaitOnTriggerControl +#define TimerWaitOnTriggerControl ROM_TimerWaitOnTriggerControl #endif #ifdef ROM_TimerIntRegister -#undef TimerIntRegister -#define TimerIntRegister ROM_TimerIntRegister +#undef TimerIntRegister +#define TimerIntRegister ROM_TimerIntRegister #endif #ifdef ROM_TimerIntUnregister -#undef TimerIntUnregister -#define TimerIntUnregister ROM_TimerIntUnregister +#undef TimerIntUnregister +#define TimerIntUnregister ROM_TimerIntUnregister #endif #ifdef ROM_TimerMatchUpdateMode -#undef TimerMatchUpdateMode -#define TimerMatchUpdateMode ROM_TimerMatchUpdateMode +#undef TimerMatchUpdateMode +#define TimerMatchUpdateMode ROM_TimerMatchUpdateMode #endif #ifdef ROM_TimerIntervalLoadMode -#undef TimerIntervalLoadMode -#define TimerIntervalLoadMode ROM_TimerIntervalLoadMode +#undef TimerIntervalLoadMode +#define TimerIntervalLoadMode ROM_TimerIntervalLoadMode #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/timer_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/timer_doc.h index d15c086..b9e9b91 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/timer_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/timer_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: timer_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: timer_doc.h + * Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) + * Revision: 45971 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup timer_api //! @{ //! \section sec_timer Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/trng.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/trng.h index e3cfd1e..1723dc7 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/trng.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/trng.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: trng.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and prototypes for the true random number gen. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: trng.h + * Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) + * Revision: 49048 + * + * Description: Defines and prototypes for the true random number gen. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,19 +55,18 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_trng.h" -#include "../inc/hw_memmap.h" #include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" +#include "../inc/hw_trng.h" +#include "../inc/hw_types.h" +#include "cpu.h" #include "debug.h" #include "interrupt.h" -#include "cpu.h" +#include +#include //***************************************************************************** // @@ -83,8 +82,8 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define TRNGConfigure NOROM_TRNGConfigure -#define TRNGNumberGet NOROM_TRNGNumberGet +#define TRNGConfigure NOROM_TRNGConfigure +#define TRNGNumberGet NOROM_TRNGNumberGet #endif //***************************************************************************** @@ -92,12 +91,12 @@ extern "C" // // //***************************************************************************** -#define TRNG_NUMBER_READY 0x00000001 // -#define TRNG_FRO_SHUTDOWN 0x00000002 // -#define TRNG_NEED_CLOCK 0x80000000 // +#define TRNG_NUMBER_READY 0x00000001 // +#define TRNG_FRO_SHUTDOWN 0x00000002 // +#define TRNG_NEED_CLOCK 0x80000000 // -#define TRNG_HI_WORD 0x00000001 -#define TRNG_LOW_WORD 0x00000002 +#define TRNG_HI_WORD 0x00000001 +#define TRNG_LOW_WORD 0x00000002 //***************************************************************************** // @@ -422,12 +421,12 @@ TRNGIntUnregister(void) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_TRNGConfigure -#undef TRNGConfigure -#define TRNGConfigure ROM_TRNGConfigure +#undef TRNGConfigure +#define TRNGConfigure ROM_TRNGConfigure #endif #ifdef ROM_TRNGNumberGet -#undef TRNGNumberGet -#define TRNGNumberGet ROM_TRNGNumberGet +#undef TRNGNumberGet +#define TRNGNumberGet ROM_TRNGNumberGet #endif #endif @@ -440,7 +439,7 @@ TRNGIntUnregister(void) } #endif -#endif // __TRNG_H__ +#endif // __TRNG_H__ //***************************************************************************** // diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/uart.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/uart.h index 05cd2eb..2212566 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/uart.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/uart.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: uart.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Defines and prototypes for the UART. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: uart.h + * Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) + * Revision: 49096 + * + * Description: Defines and prototypes for the UART. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,18 +55,17 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include +#include "../inc/hw_ints.h" +#include "../inc/hw_memmap.h" #include "../inc/hw_types.h" #include "../inc/hw_uart.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "interrupt.h" #include "debug.h" +#include "interrupt.h" +#include +#include //***************************************************************************** // @@ -82,16 +81,16 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define UARTFIFOLevelGet NOROM_UARTFIFOLevelGet -#define UARTConfigSetExpClk NOROM_UARTConfigSetExpClk -#define UARTConfigGetExpClk NOROM_UARTConfigGetExpClk -#define UARTDisable NOROM_UARTDisable -#define UARTCharGetNonBlocking NOROM_UARTCharGetNonBlocking -#define UARTCharGet NOROM_UARTCharGet -#define UARTCharPutNonBlocking NOROM_UARTCharPutNonBlocking -#define UARTCharPut NOROM_UARTCharPut -#define UARTIntRegister NOROM_UARTIntRegister -#define UARTIntUnregister NOROM_UARTIntUnregister +#define UARTFIFOLevelGet NOROM_UARTFIFOLevelGet +#define UARTConfigSetExpClk NOROM_UARTConfigSetExpClk +#define UARTConfigGetExpClk NOROM_UARTConfigGetExpClk +#define UARTDisable NOROM_UARTDisable +#define UARTCharGetNonBlocking NOROM_UARTCharGetNonBlocking +#define UARTCharGet NOROM_UARTCharGet +#define UARTCharPutNonBlocking NOROM_UARTCharPutNonBlocking +#define UARTCharPut NOROM_UARTCharPut +#define UARTIntRegister NOROM_UARTIntRegister +#define UARTIntUnregister NOROM_UARTIntUnregister #endif //***************************************************************************** @@ -100,14 +99,14 @@ extern "C" // as the ui32IntFlags parameter, and returned from UARTIntStatus. // //***************************************************************************** -#define UART_INT_OE ( UART_IMSC_OEIM ) // Overrun Error Interrupt Mask -#define UART_INT_BE ( UART_IMSC_BEIM ) // Break Error Interrupt Mask -#define UART_INT_PE ( UART_IMSC_PEIM ) // Parity Error Interrupt Mask -#define UART_INT_FE ( UART_IMSC_FEIM ) // Framing Error Interrupt Mask -#define UART_INT_RT ( UART_IMSC_RTIM ) // Receive Timeout Interrupt Mask -#define UART_INT_TX ( UART_IMSC_TXIM ) // Transmit Interrupt Mask -#define UART_INT_RX ( UART_IMSC_RXIM ) // Receive Interrupt Mask -#define UART_INT_CTS ( UART_IMSC_CTSMIM ) // CTS Modem Interrupt Mask +#define UART_INT_OE (UART_IMSC_OEIM) // Overrun Error Interrupt Mask +#define UART_INT_BE (UART_IMSC_BEIM) // Break Error Interrupt Mask +#define UART_INT_PE (UART_IMSC_PEIM) // Parity Error Interrupt Mask +#define UART_INT_FE (UART_IMSC_FEIM) // Framing Error Interrupt Mask +#define UART_INT_RT (UART_IMSC_RTIM) // Receive Timeout Interrupt Mask +#define UART_INT_TX (UART_IMSC_TXIM) // Transmit Interrupt Mask +#define UART_INT_RX (UART_IMSC_RXIM) // Receive Interrupt Mask +#define UART_INT_CTS (UART_IMSC_CTSMIM) // CTS Modem Interrupt Mask //***************************************************************************** // @@ -118,20 +117,20 @@ extern "C" // UARTParityModeGet. // //***************************************************************************** -#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length -#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data -#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data -#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data -#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data -#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits -#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit -#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits -#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity -#define UART_CONFIG_PAR_NONE 0x00000000 // No parity -#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity -#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity -#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one -#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero +#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length +#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data +#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data +#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data +#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data +#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits +#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit +#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits +#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity +#define UART_CONFIG_PAR_NONE 0x00000000 // No parity +#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity +#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity +#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one +#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero //***************************************************************************** // @@ -139,11 +138,11 @@ extern "C" // and returned by UARTFIFOLevelGet in the pui32TxLevel. // //***************************************************************************** -#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full -#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full -#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full -#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full -#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full +#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full +#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full +#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full +#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full +#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full //***************************************************************************** // @@ -151,38 +150,38 @@ extern "C" // and returned by UARTFIFOLevelGet in the pui32RxLevel. // //***************************************************************************** -#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full -#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full -#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full -#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full -#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full +#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full +#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full +#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full +#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full +#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full //***************************************************************************** // // Values that can be passed to UARTDMAEnable() and UARTDMADisable(). // //***************************************************************************** -#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error -#define UART_DMA_TX 0x00000002 // Enable DMA for transmit -#define UART_DMA_RX 0x00000001 // Enable DMA for receive +#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error +#define UART_DMA_TX 0x00000002 // Enable DMA for transmit +#define UART_DMA_RX 0x00000001 // Enable DMA for receive //***************************************************************************** // // Values returned from UARTRxErrorGet(). // //***************************************************************************** -#define UART_RXERROR_OVERRUN 0x00000008 -#define UART_RXERROR_BREAK 0x00000004 -#define UART_RXERROR_PARITY 0x00000002 -#define UART_RXERROR_FRAMING 0x00000001 +#define UART_RXERROR_OVERRUN 0x00000008 +#define UART_RXERROR_BREAK 0x00000004 +#define UART_RXERROR_PARITY 0x00000002 +#define UART_RXERROR_FRAMING 0x00000001 //***************************************************************************** // // Values returned from the UARTBusy(). // //***************************************************************************** -#define UART_BUSY 0x00000001 -#define UART_IDLE 0x00000000 +#define UART_BUSY 0x00000001 +#define UART_IDLE 0x00000000 //***************************************************************************** // @@ -208,7 +207,7 @@ extern "C" static bool UARTBaseValid(uint32_t ui32Base) { - return (( ui32Base == UART0_BASE ) || ( ui32Base == UART0_NONBUF_BASE )); + return ((ui32Base == UART0_BASE) || (ui32Base == UART0_NONBUF_BASE)); } #endif @@ -246,7 +245,8 @@ UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity) // Set the parity mode. HWREG(ui32Base + UART_O_LCRH) = ((HWREG(ui32Base + UART_O_LCRH) & ~(UART_LCRH_SPS | UART_LCRH_EPS | - UART_LCRH_PEN)) | ui32Parity); + UART_LCRH_PEN)) | + ui32Parity); } //***************************************************************************** @@ -639,8 +639,7 @@ UARTBusy(uint32_t ui32Base) ASSERT(UARTBaseValid(ui32Base)); // Determine if the UART is busy. - return ((HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) ? - UART_BUSY : UART_IDLE); + return ((HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) ? UART_BUSY : UART_IDLE); } //***************************************************************************** @@ -666,9 +665,7 @@ UARTBreakCtl(uint32_t ui32Base, bool bBreakState) // Set the break condition as requested. HWREG(ui32Base + UART_O_LCRH) = - (bBreakState ? - (HWREG(ui32Base + UART_O_LCRH) | UART_LCRH_BRK) : - (HWREG(ui32Base + UART_O_LCRH) & ~(UART_LCRH_BRK))); + (bBreakState ? (HWREG(ui32Base + UART_O_LCRH) | UART_LCRH_BRK) : (HWREG(ui32Base + UART_O_LCRH) & ~(UART_LCRH_BRK))); } //***************************************************************************** @@ -992,12 +989,12 @@ UARTRxErrorClear(uint32_t ui32Base) // //***************************************************************************** __STATIC_INLINE void -UARTHwFlowControlEnable( uint32_t ui32Base ) +UARTHwFlowControlEnable(uint32_t ui32Base) { // Check the arguments. - ASSERT( UARTBaseValid( ui32Base )); + ASSERT(UARTBaseValid(ui32Base)); - HWREG( ui32Base + UART_O_CTL ) |= ( UART_CTL_CTSEN | UART_CTL_RTSEN ); + HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_CTSEN | UART_CTL_RTSEN); } //***************************************************************************** @@ -1012,15 +1009,14 @@ UARTHwFlowControlEnable( uint32_t ui32Base ) // //***************************************************************************** __STATIC_INLINE void -UARTHwFlowControlDisable( uint32_t ui32Base ) +UARTHwFlowControlDisable(uint32_t ui32Base) { // Check the arguments. - ASSERT( UARTBaseValid( ui32Base )); + ASSERT(UARTBaseValid(ui32Base)); - HWREG( ui32Base + UART_O_CTL ) &= ~( UART_CTL_CTSEN | UART_CTL_RTSEN ); + HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_CTSEN | UART_CTL_RTSEN); } - //***************************************************************************** // // Support for DriverLib in ROM: @@ -1030,44 +1026,44 @@ UARTHwFlowControlDisable( uint32_t ui32Base ) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_UARTFIFOLevelGet -#undef UARTFIFOLevelGet -#define UARTFIFOLevelGet ROM_UARTFIFOLevelGet +#undef UARTFIFOLevelGet +#define UARTFIFOLevelGet ROM_UARTFIFOLevelGet #endif #ifdef ROM_UARTConfigSetExpClk -#undef UARTConfigSetExpClk -#define UARTConfigSetExpClk ROM_UARTConfigSetExpClk +#undef UARTConfigSetExpClk +#define UARTConfigSetExpClk ROM_UARTConfigSetExpClk #endif #ifdef ROM_UARTConfigGetExpClk -#undef UARTConfigGetExpClk -#define UARTConfigGetExpClk ROM_UARTConfigGetExpClk +#undef UARTConfigGetExpClk +#define UARTConfigGetExpClk ROM_UARTConfigGetExpClk #endif #ifdef ROM_UARTDisable -#undef UARTDisable -#define UARTDisable ROM_UARTDisable +#undef UARTDisable +#define UARTDisable ROM_UARTDisable #endif #ifdef ROM_UARTCharGetNonBlocking -#undef UARTCharGetNonBlocking -#define UARTCharGetNonBlocking ROM_UARTCharGetNonBlocking +#undef UARTCharGetNonBlocking +#define UARTCharGetNonBlocking ROM_UARTCharGetNonBlocking #endif #ifdef ROM_UARTCharGet -#undef UARTCharGet -#define UARTCharGet ROM_UARTCharGet +#undef UARTCharGet +#define UARTCharGet ROM_UARTCharGet #endif #ifdef ROM_UARTCharPutNonBlocking -#undef UARTCharPutNonBlocking -#define UARTCharPutNonBlocking ROM_UARTCharPutNonBlocking +#undef UARTCharPutNonBlocking +#define UARTCharPutNonBlocking ROM_UARTCharPutNonBlocking #endif #ifdef ROM_UARTCharPut -#undef UARTCharPut -#define UARTCharPut ROM_UARTCharPut +#undef UARTCharPut +#define UARTCharPut ROM_UARTCharPut #endif #ifdef ROM_UARTIntRegister -#undef UARTIntRegister -#define UARTIntRegister ROM_UARTIntRegister +#undef UARTIntRegister +#define UARTIntRegister ROM_UARTIntRegister #endif #ifdef ROM_UARTIntUnregister -#undef UARTIntUnregister -#define UARTIntUnregister ROM_UARTIntUnregister +#undef UARTIntUnregister +#define UARTIntUnregister ROM_UARTIntUnregister #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/uart_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/uart_doc.h index ba77f94..21d1bf9 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/uart_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/uart_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: uart_doc.h -* Revised: 2018-02-09 15:45:36 +0100 (fr, 09 feb 2018) -* Revision: 51470 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: uart_doc.h + * Revised: 2018-02-09 15:45:36 +0100 (fr, 09 feb 2018) + * Revision: 51470 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ /*! \addtogroup uart_api @{ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/udma.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/udma.h index 0ac722a..be36838 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/udma.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/udma.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: udma.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and prototypes for the uDMA controller. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: udma.h + * Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) + * Revision: 49048 + * + * Description: Defines and prototypes for the uDMA controller. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,18 +55,17 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" #include "../inc/hw_ints.h" #include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "../inc/hw_udma.h" #include "debug.h" #include "interrupt.h" +#include +#include //***************************************************************************** // @@ -82,14 +81,14 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable -#define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable -#define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet -#define uDMAChannelControlSet NOROM_uDMAChannelControlSet -#define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet -#define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet -#define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet -#define uDMAChannelModeGet NOROM_uDMAChannelModeGet +#define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable +#define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable +#define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet +#define uDMAChannelControlSet NOROM_uDMAChannelControlSet +#define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet +#define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet +#define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet +#define uDMAChannelModeGet NOROM_uDMAChannelModeGet #endif //***************************************************************************** @@ -102,12 +101,11 @@ extern "C" //***************************************************************************** typedef struct { - volatile void* pvSrcEndAddr; //!< The ending source address of the data transfer. - volatile void* pvDstEndAddr; //!< The ending destination address of the data transfer. - volatile uint32_t ui32Control; //!< The channel control mode. - volatile uint32_t ui32Spare; //!< An unused location. -} -tDMAControlTable; + volatile void* pvSrcEndAddr; //!< The ending source address of the data transfer. + volatile void* pvDstEndAddr; //!< The ending destination address of the data transfer. + volatile uint32_t ui32Control; //!< The channel control mode. + volatile uint32_t ui32Spare; //!< An unused location. +} tDMAControlTable; //***************************************************************************** // @@ -177,42 +175,40 @@ tDMAControlTable; //! \return None (this is not a function) // //***************************************************************************** -#define uDMATaskStructEntry(ui32TransferCount, \ - ui32ItemSize, \ - ui32SrcIncrement, \ - pvSrcAddr, \ - ui32DstIncrement, \ - pvDstAddr, \ - ui32ArbSize, \ - ui32Mode) \ -{ \ - (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (pvSrcAddr) : \ - ((void *)(&((uint8_t *)(pvSrcAddr))[((ui32TransferCount) << \ - ((ui32SrcIncrement) >> 26)) - 1]))), \ - (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (pvDstAddr) : \ - ((void *)(&((uint8_t *)(pvDstAddr))[((ui32TransferCount) << \ - ((ui32DstIncrement) >> 30)) - 1]))), \ - (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \ - (ui32ArbSize) | (((ui32TransferCount) - 1) << 4) | \ - ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ - ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ - (ui32Mode) | UDMA_MODE_ALT_SELECT : (ui32Mode)), 0 \ -} +#define uDMATaskStructEntry(ui32TransferCount, \ + ui32ItemSize, \ + ui32SrcIncrement, \ + pvSrcAddr, \ + ui32DstIncrement, \ + pvDstAddr, \ + ui32ArbSize, \ + ui32Mode) \ + { \ + (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (pvSrcAddr) : ((void*)(&((uint8_t*)(pvSrcAddr))[((ui32TransferCount) << ((ui32SrcIncrement) >> 26)) - 1]))), \ + (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (pvDstAddr) : ((void*)(&((uint8_t*)(pvDstAddr))[((ui32TransferCount) << ((ui32DstIncrement) >> 30)) - 1]))), \ + (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \ + (ui32ArbSize) | (((ui32TransferCount) - 1) << 4) | \ + ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ + ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) \ + ? (ui32Mode) | UDMA_MODE_ALT_SELECT \ + : (ui32Mode)), \ + 0 \ + } //***************************************************************************** // // The hardware configured number of uDMA channels. // //***************************************************************************** -#define UDMA_NUM_CHANNELS 21 +#define UDMA_NUM_CHANNELS 21 //***************************************************************************** // // The level of priority for the uDMA channels // //***************************************************************************** -#define UDMA_PRIORITY_LOW 0x00000000 -#define UDMA_PRIORITY_HIGH 0x00000001 +#define UDMA_PRIORITY_LOW 0x00000000 +#define UDMA_PRIORITY_HIGH 0x00000001 //***************************************************************************** // @@ -220,11 +216,11 @@ tDMAControlTable; // uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). // //***************************************************************************** -#define UDMA_ATTR_USEBURST 0x00000001 -#define UDMA_ATTR_ALTSELECT 0x00000002 +#define UDMA_ATTR_USEBURST 0x00000001 +#define UDMA_ATTR_ALTSELECT 0x00000002 #define UDMA_ATTR_HIGH_PRIORITY 0x00000004 -#define UDMA_ATTR_REQMASK 0x00000008 -#define UDMA_ATTR_ALL 0x0000000F +#define UDMA_ATTR_REQMASK 0x00000008 +#define UDMA_ATTR_ALL 0x0000000F //***************************************************************************** // @@ -232,56 +228,56 @@ tDMAControlTable; // uDMAChannelModeGet(). // //***************************************************************************** -#define UDMA_MODE_STOP 0x00000000 -#define UDMA_MODE_BASIC 0x00000001 -#define UDMA_MODE_AUTO 0x00000002 -#define UDMA_MODE_PINGPONG 0x00000003 -#define UDMA_MODE_MEM_SCATTER_GATHER \ +#define UDMA_MODE_STOP 0x00000000 +#define UDMA_MODE_BASIC 0x00000001 +#define UDMA_MODE_AUTO 0x00000002 +#define UDMA_MODE_PINGPONG 0x00000003 +#define UDMA_MODE_MEM_SCATTER_GATHER \ 0x00000004 -#define UDMA_MODE_PER_SCATTER_GATHER \ +#define UDMA_MODE_PER_SCATTER_GATHER \ 0x00000006 -#define UDMA_MODE_M 0x00000007 // uDMA Transfer Mode -#define UDMA_MODE_ALT_SELECT 0x00000001 +#define UDMA_MODE_M 0x00000007 // uDMA Transfer Mode +#define UDMA_MODE_ALT_SELECT 0x00000001 //***************************************************************************** // // Channel configuration values that can be passed to uDMAControlSet(). // //***************************************************************************** -#define UDMA_DST_INC_8 0x00000000 -#define UDMA_DST_INC_16 0x40000000 -#define UDMA_DST_INC_32 0x80000000 -#define UDMA_DST_INC_NONE 0xC0000000 -#define UDMA_DST_INC_M 0xC0000000 // Destination Address Increment -#define UDMA_DST_INC_S 30 -#define UDMA_SRC_INC_8 0x00000000 -#define UDMA_SRC_INC_16 0x04000000 -#define UDMA_SRC_INC_32 0x08000000 -#define UDMA_SRC_INC_NONE 0x0c000000 -#define UDMA_SRC_INC_M 0x0C000000 // Source Address Increment -#define UDMA_SRC_INC_S 26 -#define UDMA_SIZE_8 0x00000000 -#define UDMA_SIZE_16 0x11000000 -#define UDMA_SIZE_32 0x22000000 -#define UDMA_SIZE_M 0x33000000 // Data Size -#define UDMA_SIZE_S 24 -#define UDMA_ARB_1 0x00000000 -#define UDMA_ARB_2 0x00004000 -#define UDMA_ARB_4 0x00008000 -#define UDMA_ARB_8 0x0000c000 -#define UDMA_ARB_16 0x00010000 -#define UDMA_ARB_32 0x00014000 -#define UDMA_ARB_64 0x00018000 -#define UDMA_ARB_128 0x0001c000 -#define UDMA_ARB_256 0x00020000 -#define UDMA_ARB_512 0x00024000 -#define UDMA_ARB_1024 0x00028000 -#define UDMA_ARB_M 0x0003C000 // Arbitration Size -#define UDMA_ARB_S 14 -#define UDMA_NEXT_USEBURST 0x00000008 -#define UDMA_XFER_SIZE_MAX 1024 -#define UDMA_XFER_SIZE_M 0x00003FF0 // Transfer size -#define UDMA_XFER_SIZE_S 4 +#define UDMA_DST_INC_8 0x00000000 +#define UDMA_DST_INC_16 0x40000000 +#define UDMA_DST_INC_32 0x80000000 +#define UDMA_DST_INC_NONE 0xC0000000 +#define UDMA_DST_INC_M 0xC0000000 // Destination Address Increment +#define UDMA_DST_INC_S 30 +#define UDMA_SRC_INC_8 0x00000000 +#define UDMA_SRC_INC_16 0x04000000 +#define UDMA_SRC_INC_32 0x08000000 +#define UDMA_SRC_INC_NONE 0x0c000000 +#define UDMA_SRC_INC_M 0x0C000000 // Source Address Increment +#define UDMA_SRC_INC_S 26 +#define UDMA_SIZE_8 0x00000000 +#define UDMA_SIZE_16 0x11000000 +#define UDMA_SIZE_32 0x22000000 +#define UDMA_SIZE_M 0x33000000 // Data Size +#define UDMA_SIZE_S 24 +#define UDMA_ARB_1 0x00000000 +#define UDMA_ARB_2 0x00004000 +#define UDMA_ARB_4 0x00008000 +#define UDMA_ARB_8 0x0000c000 +#define UDMA_ARB_16 0x00010000 +#define UDMA_ARB_32 0x00014000 +#define UDMA_ARB_64 0x00018000 +#define UDMA_ARB_128 0x0001c000 +#define UDMA_ARB_256 0x00020000 +#define UDMA_ARB_512 0x00024000 +#define UDMA_ARB_1024 0x00028000 +#define UDMA_ARB_M 0x0003C000 // Arbitration Size +#define UDMA_ARB_S 14 +#define UDMA_NEXT_USEBURST 0x00000008 +#define UDMA_XFER_SIZE_MAX 1024 +#define UDMA_XFER_SIZE_M 0x00003FF0 // Transfer size +#define UDMA_XFER_SIZE_S 4 //***************************************************************************** // @@ -289,25 +285,25 @@ tDMAControlTable; // ID. // //***************************************************************************** -#define UDMA_CHAN_SW_EVT0 0 // Software Event Channel 0 -#define UDMA_CHAN_UART0_RX 1 // UART0 RX Data -#define UDMA_CHAN_UART0_TX 2 // UART0 RX Data -#define UDMA_CHAN_SSI0_RX 3 // SSI0 RX Data -#define UDMA_CHAN_SSI0_TX 4 // SSI0 RX Data -#define UDMA_CHAN_AUX_ADC 7 // AUX ADC event -#define UDMA_CHAN_AUX_SW 8 // AUX Software event -#define UDMA_CHAN_TIMER0_A 9 // Timer0 A event -#define UDMA_CHAN_TIMER0_B 10 // Timer0 B event -#define UDMA_CHAN_TIMER1_A 11 -#define UDMA_CHAN_TIMER1_B 12 -#define UDMA_CHAN_AON_PROG2 13 -#define UDMA_CHAN_DMA_PROG 14 -#define UDMA_CHAN_AON_RTC 15 -#define UDMA_CHAN_SSI1_RX 16 -#define UDMA_CHAN_SSI1_TX 17 -#define UDMA_CHAN_SW_EVT1 18 -#define UDMA_CHAN_SW_EVT2 19 -#define UDMA_CHAN_SW_EVT3 20 +#define UDMA_CHAN_SW_EVT0 0 // Software Event Channel 0 +#define UDMA_CHAN_UART0_RX 1 // UART0 RX Data +#define UDMA_CHAN_UART0_TX 2 // UART0 RX Data +#define UDMA_CHAN_SSI0_RX 3 // SSI0 RX Data +#define UDMA_CHAN_SSI0_TX 4 // SSI0 RX Data +#define UDMA_CHAN_AUX_ADC 7 // AUX ADC event +#define UDMA_CHAN_AUX_SW 8 // AUX Software event +#define UDMA_CHAN_TIMER0_A 9 // Timer0 A event +#define UDMA_CHAN_TIMER0_B 10 // Timer0 B event +#define UDMA_CHAN_TIMER1_A 11 +#define UDMA_CHAN_TIMER1_B 12 +#define UDMA_CHAN_AON_PROG2 13 +#define UDMA_CHAN_DMA_PROG 14 +#define UDMA_CHAN_AON_RTC 15 +#define UDMA_CHAN_SSI1_RX 16 +#define UDMA_CHAN_SSI1_TX 17 +#define UDMA_CHAN_SW_EVT1 18 +#define UDMA_CHAN_SW_EVT2 19 +#define UDMA_CHAN_SW_EVT3 20 //***************************************************************************** // @@ -315,8 +311,8 @@ tDMAControlTable; // control structure should be used. // //***************************************************************************** -#define UDMA_PRI_SELECT 0x00000000 -#define UDMA_ALT_SELECT 0x00000020 +#define UDMA_PRI_SELECT 0x00000000 +#define UDMA_ALT_SELECT 0x00000020 //***************************************************************************** // @@ -514,8 +510,7 @@ uDMAChannelIsEnabled(uint32_t ui32Base, uint32_t ui32ChannelNum) // AND the specified channel bit with the enable register, and return the // result. - return ((HWREG(ui32Base + UDMA_O_SETCHANNELEN) & (1 << ui32ChannelNum)) ? - true : false); + return ((HWREG(ui32Base + UDMA_O_SETCHANNELEN) & (1 << ui32ChannelNum)) ? true : false); } //***************************************************************************** @@ -1150,8 +1145,7 @@ uDMAChannelPriorityGet(uint32_t ui32Base, uint32_t ui32ChannelNum) ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); // Return the channel priority. - return (HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum) ? - UDMA_PRIORITY_HIGH : UDMA_PRIORITY_LOW); + return (HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum) ? UDMA_PRIORITY_HIGH : UDMA_PRIORITY_LOW); } //***************************************************************************** @@ -1187,36 +1181,36 @@ uDMAChannelPriorityClear(uint32_t ui32Base, uint32_t ui32ChannelNum) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_uDMAChannelAttributeEnable -#undef uDMAChannelAttributeEnable -#define uDMAChannelAttributeEnable ROM_uDMAChannelAttributeEnable +#undef uDMAChannelAttributeEnable +#define uDMAChannelAttributeEnable ROM_uDMAChannelAttributeEnable #endif #ifdef ROM_uDMAChannelAttributeDisable -#undef uDMAChannelAttributeDisable -#define uDMAChannelAttributeDisable ROM_uDMAChannelAttributeDisable +#undef uDMAChannelAttributeDisable +#define uDMAChannelAttributeDisable ROM_uDMAChannelAttributeDisable #endif #ifdef ROM_uDMAChannelAttributeGet -#undef uDMAChannelAttributeGet -#define uDMAChannelAttributeGet ROM_uDMAChannelAttributeGet +#undef uDMAChannelAttributeGet +#define uDMAChannelAttributeGet ROM_uDMAChannelAttributeGet #endif #ifdef ROM_uDMAChannelControlSet -#undef uDMAChannelControlSet -#define uDMAChannelControlSet ROM_uDMAChannelControlSet +#undef uDMAChannelControlSet +#define uDMAChannelControlSet ROM_uDMAChannelControlSet #endif #ifdef ROM_uDMAChannelTransferSet -#undef uDMAChannelTransferSet -#define uDMAChannelTransferSet ROM_uDMAChannelTransferSet +#undef uDMAChannelTransferSet +#define uDMAChannelTransferSet ROM_uDMAChannelTransferSet #endif #ifdef ROM_uDMAChannelScatterGatherSet -#undef uDMAChannelScatterGatherSet -#define uDMAChannelScatterGatherSet ROM_uDMAChannelScatterGatherSet +#undef uDMAChannelScatterGatherSet +#define uDMAChannelScatterGatherSet ROM_uDMAChannelScatterGatherSet #endif #ifdef ROM_uDMAChannelSizeGet -#undef uDMAChannelSizeGet -#define uDMAChannelSizeGet ROM_uDMAChannelSizeGet +#undef uDMAChannelSizeGet +#define uDMAChannelSizeGet ROM_uDMAChannelSizeGet #endif #ifdef ROM_uDMAChannelModeGet -#undef uDMAChannelModeGet -#define uDMAChannelModeGet ROM_uDMAChannelModeGet +#undef uDMAChannelModeGet +#define uDMAChannelModeGet ROM_uDMAChannelModeGet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/vims.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/vims.h index ac48eaf..58a72ff 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/vims.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/vims.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: vims.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the VIMS. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: vims.h + * Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) + * Revision: 47343 + * + * Description: Defines and prototypes for the VIMS. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,16 +55,15 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" #include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "../inc/hw_vims.h" #include "debug.h" +#include +#include //***************************************************************************** // @@ -80,10 +79,10 @@ extern "C" // //***************************************************************************** #if !defined(DOXYGEN) -#define VIMSConfigure NOROM_VIMSConfigure -#define VIMSModeSet NOROM_VIMSModeSet -#define VIMSModeGet NOROM_VIMSModeGet -#define VIMSModeSafeSet NOROM_VIMSModeSafeSet +#define VIMSConfigure NOROM_VIMSConfigure +#define VIMSModeSet NOROM_VIMSModeSet +#define VIMSModeGet NOROM_VIMSModeGet +#define VIMSModeSafeSet NOROM_VIMSModeSafeSet #endif //***************************************************************************** @@ -92,11 +91,11 @@ extern "C" // and returned from VIMSModeGet(). // //***************************************************************************** -#define VIMS_MODE_CHANGING 0x4 // VIMS mode is changing now and VIMS_MODE +#define VIMS_MODE_CHANGING 0x4 // VIMS mode is changing now and VIMS_MODE // can not be changed at moment. #define VIMS_MODE_DISABLED (VIMS_CTL_MODE_GPRAM) // Disabled mode (GPRAM enabled). -#define VIMS_MODE_ENABLED (VIMS_CTL_MODE_CACHE) // Enabled mode, only USERCODE is cached. -#define VIMS_MODE_OFF (VIMS_CTL_MODE_OFF) // VIMS Cache RAM is off +#define VIMS_MODE_ENABLED (VIMS_CTL_MODE_CACHE) // Enabled mode, only USERCODE is cached. +#define VIMS_MODE_OFF (VIMS_CTL_MODE_OFF) // VIMS Cache RAM is off //***************************************************************************** // @@ -277,9 +276,9 @@ extern uint32_t VIMSModeGet(uint32_t ui32Base); //! \sa \ref VIMSModeSet() and \ref VIMSModeGet() // //***************************************************************************** -extern void VIMSModeSafeSet( uint32_t ui32Base, - uint32_t ui32NewMode, - bool blocking ); +extern void VIMSModeSafeSet(uint32_t ui32Base, + uint32_t ui32NewMode, + bool blocking); //***************************************************************************** // @@ -334,20 +333,20 @@ VIMSLineBufEnable(uint32_t ui32Base) #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) #include "../driverlib/rom.h" #ifdef ROM_VIMSConfigure -#undef VIMSConfigure -#define VIMSConfigure ROM_VIMSConfigure +#undef VIMSConfigure +#define VIMSConfigure ROM_VIMSConfigure #endif #ifdef ROM_VIMSModeSet -#undef VIMSModeSet -#define VIMSModeSet ROM_VIMSModeSet +#undef VIMSModeSet +#define VIMSModeSet ROM_VIMSModeSet #endif #ifdef ROM_VIMSModeGet -#undef VIMSModeGet -#define VIMSModeGet ROM_VIMSModeGet +#undef VIMSModeGet +#define VIMSModeGet ROM_VIMSModeGet #endif #ifdef ROM_VIMSModeSafeSet -#undef VIMSModeSafeSet -#define VIMSModeSafeSet ROM_VIMSModeSafeSet +#undef VIMSModeSafeSet +#define VIMSModeSafeSet ROM_VIMSModeSafeSet #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/watchdog.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/watchdog.h index a964eb3..3db6a6c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/watchdog.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/watchdog.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: wdt.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and prototypes for the Watchdog Timer. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: wdt.h + * Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) + * Revision: 49048 + * + * Description: Defines and prototypes for the Watchdog Timer. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -55,27 +55,26 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif -#include -#include -#include "../inc/hw_types.h" #include "../inc/hw_ints.h" #include "../inc/hw_memmap.h" +#include "../inc/hw_types.h" #include "../inc/hw_wdt.h" #include "debug.h" #include "interrupt.h" +#include +#include //***************************************************************************** // // The following are defines for the bit fields in the WDT_O_LOCK register. // //***************************************************************************** -#define WATCHDOG_LOCK_UNLOCKED 0x00000000 // Unlocked -#define WATCHDOG_LOCK_LOCKED 0x00000001 // Locked -#define WATCHDOG_LOCK_UNLOCK 0x1ACCE551 // Unlocks the Watchdog Timer +#define WATCHDOG_LOCK_UNLOCKED 0x00000000 // Unlocked +#define WATCHDOG_LOCK_LOCKED 0x00000001 // Locked +#define WATCHDOG_LOCK_UNLOCK 0x1ACCE551 // Unlocks the Watchdog Timer //***************************************************************************** // @@ -83,15 +82,15 @@ extern "C" // WDT_MIS registers. // //***************************************************************************** -#define WATCHDOG_INT_TIMEOUT 0x00000001 // Watchdog timer expired +#define WATCHDOG_INT_TIMEOUT 0x00000001 // Watchdog timer expired //***************************************************************************** // // The type of interrupt that can be generated by the watchdog. // //***************************************************************************** -#define WATCHDOG_INT_TYPE_INT 0x00000000 -#define WATCHDOG_INT_TYPE_NMI 0x00000004 +#define WATCHDOG_INT_TYPE_INT 0x00000000 +#define WATCHDOG_INT_TYPE_NMI 0x00000004 //***************************************************************************** // @@ -231,8 +230,7 @@ __STATIC_INLINE bool WatchdogLockState(void) { // Get the lock state. - return ((HWREG(WDT_BASE + WDT_O_LOCK) == WATCHDOG_LOCK_LOCKED) ? - true : false); + return ((HWREG(WDT_BASE + WDT_O_LOCK) == WATCHDOG_LOCK_LOCKED) ? true : false); } //***************************************************************************** diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/watchdog_doc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/watchdog_doc.h index 877bab7..552cd74 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/watchdog_doc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/driverlib/watchdog_doc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: watchdog_doc.h -* Revised: 2018-02-09 15:45:36 +0100 (Fri, 09 Feb 2018) -* Revision: 51470 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: watchdog_doc.h + * Revised: 2018-02-09 15:45:36 +0100 (Fri, 09 Feb 2018) + * Revision: 51470 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //! \addtogroup wdt_api //! @{ //! \section sec_wdt Introduction diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/asmdefs.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/asmdefs.h index ddb5315..1d02ca8 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/asmdefs.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/asmdefs.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: asmdefs.h -* Revised: 2015-06-05 14:39:10 +0200 (Fri, 05 Jun 2015) -* Revision: 43803 -* -* Description: Macros to allow assembly code be portable among tool chains. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: asmdefs.h + * Revised: 2015-06-05 14:39:10 +0200 (Fri, 05 Jun 2015) + * Revision: 43803 + * + * Description: Macros to allow assembly code be portable among tool chains. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __ASMDEFS_H__ #define __ASMDEFS_H__ @@ -46,27 +46,27 @@ //***************************************************************************** #ifdef __IAR_SYSTEMS_ICC__ - // - // Section headers. - // - #define __LIBRARY__ module - #define __TEXT__ rseg CODE:CODE(2) - #define __DATA__ rseg DATA:DATA(2) - #define __BSS__ rseg DATA:DATA(2) - #define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) +// +// Section headers. +// +#define __LIBRARY__ module +#define __TEXT__ rseg CODE : CODE(2) +#define __DATA__ rseg DATA : DATA(2) +#define __BSS__ rseg DATA : DATA(2) +#define __TEXT_NOROOT__ rseg CODE : CODE : NOROOT(2) - // - // Assembler mnemonics. - // - #define __ALIGN__ alignrom 2 - #define __END__ end - #define __EXPORT__ export - #define __IMPORT__ import - #define __LABEL__ - #define __STR__ dcb - #define __THUMB_LABEL__ thumb - #define __WORD__ dcd - #define __INLINE_DATA__ data +// +// Assembler mnemonics. +// +#define __ALIGN__ alignrom 2 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ thumb +#define __WORD__ dcd +#define __INLINE_DATA__ data #endif // __IAR_SYSTEMS_ICC__ @@ -77,34 +77,34 @@ //***************************************************************************** #if defined(__GNUC__) - // - // The assembly code preamble required to put the assembler into the correct - // configuration. - // - .syntax unified +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// +.syntax unified .thumb - // - // Section headers. - // - #define __LIBRARY__ @ - #define __TEXT__ .text - #define __DATA__ .data - #define __BSS__ .bss - #define __TEXT_NOROOT__ .text +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text - // - // Assembler mnemonics. - // - #define __ALIGN__ .balign 4 - #define __END__ .end - #define __EXPORT__ .globl - #define __IMPORT__ .extern - #define __LABEL__ : - #define __STR__ .ascii - #define __THUMB_LABEL__ .thumb_func - #define __WORD__ .word - #define __INLINE_DATA__ +// +// Assembler mnemonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ #endif // __GNUC__ @@ -115,37 +115,35 @@ //***************************************************************************** #if defined(__CC_ARM) - // - // The assembly code preamble required to put the assembler into the correct - // configuration. - // - thumb - require8 - preserve8 + // + // The assembly code preamble required to put the assembler into the correct + // configuration. + // + thumb + require8 preserve8 - // - // Section headers. - // - #define __LIBRARY__ ; - #define __TEXT__ area ||.text||, code, readonly, align=2 - #define __DATA__ area ||.data||, data, align=2 - #define __BSS__ area ||.bss||, noinit, align=2 - #define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 +// +// Section headers. +// +#define __LIBRARY__ ; +#define __TEXT__ area ||.text ||, code, readonly, align = 2 +#define __DATA__ area ||.data ||, data, align = 2 +#define __BSS__ area ||.bss ||, noinit, align = 2 +#define __TEXT_NOROOT__ area ||.text ||, code, readonly, align = 2 - // - // Assembler mnemonics. - // - #define __ALIGN__ align 4 - #define __END__ end - #define __EXPORT__ export - #define __IMPORT__ import - #define __LABEL__ - #define __STR__ dcb - #define __THUMB_LABEL__ - #define __WORD__ dcd - #define __INLINE_DATA__ +// +// Assembler mnemonics. +// +#define __ALIGN__ align 4 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ +#define __WORD__ dcd +#define __INLINE_DATA__ #endif // __CC_ARM - #endif // __ASMDEF_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi.h index 7e7b603..692d892 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_adi.h -* Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) -* Revision: 42365 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_adi.h + * Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) + * Revision: 42365 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_ADI_H__ #define __HW_ADI_H__ @@ -154,21 +154,21 @@ // The following are defines for the ADI master instruction offsets. // //***************************************************************************** -#define ADI_O_DIR 0x00000000 // Offset for the direct access +#define ADI_O_DIR 0x00000000 // Offset for the direct access // instruction -#define ADI_O_SET 0x00000010 // Offset for 'Set' instruction. -#define ADI_O_CLR 0x00000020 // Offset for 'Clear' instruction. -#define ADI_O_MASK4B 0x00000040 // Offset for 4-bit masked access. +#define ADI_O_SET 0x00000010 // Offset for 'Set' instruction. +#define ADI_O_CLR 0x00000020 // Offset for 'Clear' instruction. +#define ADI_O_MASK4B 0x00000040 // Offset for 4-bit masked access. // Data bit[n] is written if mask // bit[n] is set ('1'). // Bits 7:4 are mask. Bits 3:0 are data. // Requires 'byte' write. -#define ADI_O_MASK8B 0x00000060 // Offset for 8-bit masked access. +#define ADI_O_MASK8B 0x00000060 // Offset for 8-bit masked access. // Data bit[n] is written if mask // bit[n] is set ('1'). Bits 15:8 are // mask. Bits 7:0 are data. Requires // 'short' write. -#define ADI_O_MASK16B 0x00000080 // Offset for 16-bit masked access. +#define ADI_O_MASK16B 0x00000080 // Offset for 16-bit masked access. // Data bit[n] is written if mask // bit[n] is set ('1'). Bits 31:16 // are mask. Bits 15:0 are data. @@ -179,8 +179,8 @@ // The following are defines for the ADI register offsets. // //***************************************************************************** -#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register -#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration +#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register +#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration //***************************************************************************** // @@ -188,26 +188,26 @@ // ADI_O_SLAVESTAT register. // //***************************************************************************** -#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ +#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ // signal. Writing 0 to this bit // forces a sync with slave, // ensuring that req will be 0. It // is recommended to write 0 to // this register before power down // of the master. -#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 -#define ADI_SLAVESTAT_DI_REQ_S 1 -#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK +#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 +#define ADI_SLAVESTAT_DI_REQ_S 1 +#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK // signal -#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 -#define ADI_SLAVESTAT_DI_ACK_S 0 +#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 +#define ADI_SLAVESTAT_DI_ACK_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_SLAVECONF register. // //***************************************************************************** -#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer +#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer // accessible when this bit is set. // (unless sticky_bit_overwrite is // asserted on top module) @@ -215,7 +215,7 @@ 0x00000080 #define ADI_SLAVECONF_CONFLOCK_S 7 #define ADI_SLAVECONF_WAITFORACK \ - 0x00000004 // A transaction on the ADI + 0x00000004 // A transaction on the ADI // interface does not end until ack // has been received from the slave // when this bit is set. @@ -224,7 +224,7 @@ 0x00000004 #define ADI_SLAVECONF_WAITFORACK_S 2 #define ADI_SLAVECONF_ADICLKSPEED_M \ - 0x00000003 // Sets the period of an ADI + 0x00000003 // Sets the period of an ADI // transactions. All transactions // takes an even number of clock // cycles,- ADI clock rising edge @@ -250,103 +250,103 @@ // to not use these. // //***************************************************************************** -#define ADI_O_DIR03 0x00000000 // Direct access for adi byte +#define ADI_O_DIR03 0x00000000 // Direct access for adi byte // offsets 0 to 3 -#define ADI_O_DIR47 0x00000004 // Direct access for adi byte +#define ADI_O_DIR47 0x00000004 // Direct access for adi byte // offsets 4 to 7 -#define ADI_O_DIR811 0x00000008 // Direct access for adi byte +#define ADI_O_DIR811 0x00000008 // Direct access for adi byte // offsets 8 to 11 -#define ADI_O_DIR1215 0x0000000C // Direct access for adi byte +#define ADI_O_DIR1215 0x0000000C // Direct access for adi byte // offsets 12 to 15 -#define ADI_O_SET03 0x00000010 // Set register for ADI byte +#define ADI_O_SET03 0x00000010 // Set register for ADI byte // offsets 0 to 3 -#define ADI_O_SET47 0x00000014 // Set register for ADI byte +#define ADI_O_SET47 0x00000014 // Set register for ADI byte // offsets 4 to 7 -#define ADI_O_SET811 0x00000018 // Set register for ADI byte +#define ADI_O_SET811 0x00000018 // Set register for ADI byte // offsets 8 to 11 -#define ADI_O_SET1215 0x0000001C // Set register for ADI byte +#define ADI_O_SET1215 0x0000001C // Set register for ADI byte // offsets 12 to 15 -#define ADI_O_CLR03 0x00000020 // Clear register for ADI byte +#define ADI_O_CLR03 0x00000020 // Clear register for ADI byte // offsets 0 to 3 -#define ADI_O_CLR47 0x00000024 // Clear register for ADI byte +#define ADI_O_CLR47 0x00000024 // Clear register for ADI byte // offsets 4 to 7 -#define ADI_O_CLR811 0x00000028 // Clear register for ADI byte +#define ADI_O_CLR811 0x00000028 // Clear register for ADI byte // offsets 8 to 11 -#define ADI_O_CLR1215 0x0000002C // Clear register for ADI byte +#define ADI_O_CLR1215 0x0000002C // Clear register for ADI byte // offsets 12 to 15 -#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register -#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration +#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register +#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration // register -#define ADI_O_MASK4B01 0x00000040 // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B01 0x00000040 // Masked access (4m/4d) for ADI // Registers at byte offsets 0 and // 1 -#define ADI_O_MASK4B23 0x00000044 // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B23 0x00000044 // Masked access (4m/4d) for ADI // Registers at byte offsets 2 and // 3 -#define ADI_O_MASK4B45 0x00000048 // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B45 0x00000048 // Masked access (4m/4d) for ADI // Registers at byte offsets 4 and // 5 -#define ADI_O_MASK4B67 0x0000004C // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B67 0x0000004C // Masked access (4m/4d) for ADI // Registers at byte offsets 6 and // 7 -#define ADI_O_MASK4B89 0x00000050 // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B89 0x00000050 // Masked access (4m/4d) for ADI // Registers at byte offsets 8 and // 9 -#define ADI_O_MASK4B1011 0x00000054 // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B1011 0x00000054 // Masked access (4m/4d) for ADI // Registers at byte offsets 10 and // 11 -#define ADI_O_MASK4B1213 0x00000058 // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B1213 0x00000058 // Masked access (4m/4d) for ADI // Registers at byte offsets 12 and // 13 -#define ADI_O_MASK4B1415 0x0000005C // Masked access (4m/4d) for ADI +#define ADI_O_MASK4B1415 0x0000005C // Masked access (4m/4d) for ADI // Registers at byte offsets 14 and // 15 -#define ADI_O_MASK8B01 0x00000060 // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B01 0x00000060 // Masked access (8m/8d) for ADI // Registers at byte offsets 0 and // 1 -#define ADI_O_MASK8B23 0x00000064 // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B23 0x00000064 // Masked access (8m/8d) for ADI // Registers at byte offsets 2 and // 3 -#define ADI_O_MASK8B45 0x00000068 // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B45 0x00000068 // Masked access (8m/8d) for ADI // Registers at byte offsets 4 and // 5 -#define ADI_O_MASK8B67 0x0000006C // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B67 0x0000006C // Masked access (8m/8d) for ADI // Registers at byte offsets 6 and // 7 -#define ADI_O_MASK8B89 0x00000070 // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B89 0x00000070 // Masked access (8m/8d) for ADI // Registers at byte offsets 8 and // 9 -#define ADI_O_MASK8B1011 0x00000074 // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B1011 0x00000074 // Masked access (8m/8d) for ADI // Registers at byte offsets 10 and // 11 -#define ADI_O_MASK8B1213 0x00000078 // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B1213 0x00000078 // Masked access (8m/8d) for ADI // Registers at byte offsets 12 and // 13 -#define ADI_O_MASK8B1415 0x0000007C // Masked access (8m/8d) for ADI +#define ADI_O_MASK8B1415 0x0000007C // Masked access (8m/8d) for ADI // Registers at byte offsets 14 and // 15 -#define ADI_O_MASK16B01 0x00000080 // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B01 0x00000080 // Masked access (16m/16d) for ADI // Registers at byte offsets 0 and // 1 -#define ADI_O_MASK16B23 0x00000084 // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B23 0x00000084 // Masked access (16m/16d) for ADI // Registers at byte offsets 2 and // 3 -#define ADI_O_MASK16B45 0x00000088 // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B45 0x00000088 // Masked access (16m/16d) for ADI // Registers at byte offsets 4 and // 5 -#define ADI_O_MASK16B67 0x0000008C // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B67 0x0000008C // Masked access (16m/16d) for ADI // Registers at byte offsets 6 and // 7 -#define ADI_O_MASK16B89 0x00000090 // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B89 0x00000090 // Masked access (16m/16d) for ADI // Registers at byte offsets 8 and // 9 -#define ADI_O_MASK16B1011 0x00000094 // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B1011 0x00000094 // Masked access (16m/16d) for ADI // Registers at byte offsets 10 and // 11 -#define ADI_O_MASK16B1213 0x00000098 // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B1213 0x00000098 // Masked access (16m/16d) for ADI // Registers at byte offsets 12 and // 13 -#define ADI_O_MASK16B1415 0x0000009C // Masked access (16m/16d) for ADI +#define ADI_O_MASK16B1415 0x0000009C // Masked access (16m/16d) for ADI // Registers at byte offsets 14 and // 15 @@ -355,253 +355,253 @@ // The following are defines for the bit fields in the ADI_O_DIR03 register. // //***************************************************************************** -#define ADI_DIR03_B3_M 0xFF000000 // Direct access to ADI register 3 -#define ADI_DIR03_B3_S 24 -#define ADI_DIR03_B2_M 0x00FF0000 // Direct access to ADI register 2 -#define ADI_DIR03_B2_S 16 -#define ADI_DIR03_B1_M 0x0000FF00 // Direct access to ADI register 1 -#define ADI_DIR03_B1_S 8 -#define ADI_DIR03_B0_M 0x000000FF // Direct access to ADI register 0 -#define ADI_DIR03_B0_S 0 +#define ADI_DIR03_B3_M 0xFF000000 // Direct access to ADI register 3 +#define ADI_DIR03_B3_S 24 +#define ADI_DIR03_B2_M 0x00FF0000 // Direct access to ADI register 2 +#define ADI_DIR03_B2_S 16 +#define ADI_DIR03_B1_M 0x0000FF00 // Direct access to ADI register 1 +#define ADI_DIR03_B1_S 8 +#define ADI_DIR03_B0_M 0x000000FF // Direct access to ADI register 0 +#define ADI_DIR03_B0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_DIR47 register. // //***************************************************************************** -#define ADI_DIR47_B3_M 0xFF000000 // Direct access to ADI register 7 -#define ADI_DIR47_B3_S 24 -#define ADI_DIR47_B2_M 0x00FF0000 // Direct access to ADI register 6 -#define ADI_DIR47_B2_S 16 -#define ADI_DIR47_B1_M 0x0000FF00 // Direct access to ADI register 5 -#define ADI_DIR47_B1_S 8 -#define ADI_DIR47_B0_M 0x000000FF // Direct access to ADI register 4 -#define ADI_DIR47_B0_S 0 +#define ADI_DIR47_B3_M 0xFF000000 // Direct access to ADI register 7 +#define ADI_DIR47_B3_S 24 +#define ADI_DIR47_B2_M 0x00FF0000 // Direct access to ADI register 6 +#define ADI_DIR47_B2_S 16 +#define ADI_DIR47_B1_M 0x0000FF00 // Direct access to ADI register 5 +#define ADI_DIR47_B1_S 8 +#define ADI_DIR47_B0_M 0x000000FF // Direct access to ADI register 4 +#define ADI_DIR47_B0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_DIR811 register. // //***************************************************************************** -#define ADI_DIR811_B3_M 0xFF000000 // Direct access to ADI register +#define ADI_DIR811_B3_M 0xFF000000 // Direct access to ADI register // 11 -#define ADI_DIR811_B3_S 24 -#define ADI_DIR811_B2_M 0x00FF0000 // Direct access to ADI register +#define ADI_DIR811_B3_S 24 +#define ADI_DIR811_B2_M 0x00FF0000 // Direct access to ADI register // 10 -#define ADI_DIR811_B2_S 16 -#define ADI_DIR811_B1_M 0x0000FF00 // Direct access to ADI register 9 -#define ADI_DIR811_B1_S 8 -#define ADI_DIR811_B0_M 0x000000FF // Direct access to ADI register 8 -#define ADI_DIR811_B0_S 0 +#define ADI_DIR811_B2_S 16 +#define ADI_DIR811_B1_M 0x0000FF00 // Direct access to ADI register 9 +#define ADI_DIR811_B1_S 8 +#define ADI_DIR811_B0_M 0x000000FF // Direct access to ADI register 8 +#define ADI_DIR811_B0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_DIR1215 register. // //***************************************************************************** -#define ADI_DIR1215_B3_M 0xFF000000 // Direct access to ADI register +#define ADI_DIR1215_B3_M 0xFF000000 // Direct access to ADI register // 15 -#define ADI_DIR1215_B3_S 24 -#define ADI_DIR1215_B2_M 0x00FF0000 // Direct access to ADI register +#define ADI_DIR1215_B3_S 24 +#define ADI_DIR1215_B2_M 0x00FF0000 // Direct access to ADI register // 14 -#define ADI_DIR1215_B2_S 16 -#define ADI_DIR1215_B1_M 0x0000FF00 // Direct access to ADI register +#define ADI_DIR1215_B2_S 16 +#define ADI_DIR1215_B1_M 0x0000FF00 // Direct access to ADI register // 13 -#define ADI_DIR1215_B1_S 8 -#define ADI_DIR1215_B0_M 0x000000FF // Direct access to ADI register +#define ADI_DIR1215_B1_S 8 +#define ADI_DIR1215_B0_M 0x000000FF // Direct access to ADI register // 12 -#define ADI_DIR1215_B0_S 0 +#define ADI_DIR1215_B0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_SET03 register. // //***************************************************************************** -#define ADI_SET03_S3_M 0xFF000000 // A high bit value will set the +#define ADI_SET03_S3_M 0xFF000000 // A high bit value will set the // corresponding bit in ADI // register 3. Read returns 0. -#define ADI_SET03_S3_S 24 -#define ADI_SET03_S2_M 0x00FF0000 // A high bit value will set the +#define ADI_SET03_S3_S 24 +#define ADI_SET03_S2_M 0x00FF0000 // A high bit value will set the // corresponding bit in ADI // register 2. Read returns 0. -#define ADI_SET03_S2_S 16 -#define ADI_SET03_S1_M 0x0000FF00 // A high bit value will set the +#define ADI_SET03_S2_S 16 +#define ADI_SET03_S1_M 0x0000FF00 // A high bit value will set the // corresponding bit in ADI // register 1. Read returns 0. -#define ADI_SET03_S1_S 8 -#define ADI_SET03_S0_M 0x000000FF // A high bit value will set the +#define ADI_SET03_S1_S 8 +#define ADI_SET03_S0_M 0x000000FF // A high bit value will set the // corresponding bit in ADI // register 0. Read returns 0. -#define ADI_SET03_S0_S 0 +#define ADI_SET03_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_SET47 register. // //***************************************************************************** -#define ADI_SET47_S3_M 0xFF000000 // A high bit value will set the +#define ADI_SET47_S3_M 0xFF000000 // A high bit value will set the // corresponding bit in ADI // register 7. Read returns 0. -#define ADI_SET47_S3_S 24 -#define ADI_SET47_S2_M 0x00FF0000 // A high bit value will set the +#define ADI_SET47_S3_S 24 +#define ADI_SET47_S2_M 0x00FF0000 // A high bit value will set the // corresponding bit in ADI // register 6. Read returns 0. -#define ADI_SET47_S2_S 16 -#define ADI_SET47_S1_M 0x0000FF00 // A high bit value will set the +#define ADI_SET47_S2_S 16 +#define ADI_SET47_S1_M 0x0000FF00 // A high bit value will set the // corresponding bit in ADI // register 5. Read returns 0. -#define ADI_SET47_S1_S 8 -#define ADI_SET47_S0_M 0x000000FF // A high bit value will set the +#define ADI_SET47_S1_S 8 +#define ADI_SET47_S0_M 0x000000FF // A high bit value will set the // corresponding bit in ADI // register 4. Read returns 0. -#define ADI_SET47_S0_S 0 +#define ADI_SET47_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_SET811 register. // //***************************************************************************** -#define ADI_SET811_S3_M 0xFF000000 // A high bit value will set the +#define ADI_SET811_S3_M 0xFF000000 // A high bit value will set the // corresponding bit in ADI // register 11. Read returns 0. -#define ADI_SET811_S3_S 24 -#define ADI_SET811_S2_M 0x00FF0000 // A high bit value will set the +#define ADI_SET811_S3_S 24 +#define ADI_SET811_S2_M 0x00FF0000 // A high bit value will set the // corresponding bit in ADI // register 10. Read returns 0. -#define ADI_SET811_S2_S 16 -#define ADI_SET811_S1_M 0x0000FF00 // A high bit value will set the +#define ADI_SET811_S2_S 16 +#define ADI_SET811_S1_M 0x0000FF00 // A high bit value will set the // corresponding bit in ADI // register 9. Read returns 0. -#define ADI_SET811_S1_S 8 -#define ADI_SET811_S0_M 0x000000FF // A high bit value will set the +#define ADI_SET811_S1_S 8 +#define ADI_SET811_S0_M 0x000000FF // A high bit value will set the // corresponding bit in ADI // register 8. Read returns 0. -#define ADI_SET811_S0_S 0 +#define ADI_SET811_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_SET1215 register. // //***************************************************************************** -#define ADI_SET1215_S3_M 0xFF000000 // A high bit value will set the +#define ADI_SET1215_S3_M 0xFF000000 // A high bit value will set the // corresponding bit in ADI // register 15. Read returns 0. -#define ADI_SET1215_S3_S 24 -#define ADI_SET1215_S2_M 0x00FF0000 // A high bit value will set the +#define ADI_SET1215_S3_S 24 +#define ADI_SET1215_S2_M 0x00FF0000 // A high bit value will set the // corresponding bit in ADI // register 14. Read returns 0. -#define ADI_SET1215_S2_S 16 -#define ADI_SET1215_S1_M 0x0000FF00 // A high bit value will set the +#define ADI_SET1215_S2_S 16 +#define ADI_SET1215_S1_M 0x0000FF00 // A high bit value will set the // corresponding bit in ADI // register 13. Read returns 0. -#define ADI_SET1215_S1_S 8 -#define ADI_SET1215_S0_M 0x000000FF // A high bit value will set the +#define ADI_SET1215_S1_S 8 +#define ADI_SET1215_S0_M 0x000000FF // A high bit value will set the // corresponding bit in ADI // register 12. Read returns 0. -#define ADI_SET1215_S0_S 0 +#define ADI_SET1215_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_CLR03 register. // //***************************************************************************** -#define ADI_CLR03_S3_M 0xFF000000 // A high bit value will clear the +#define ADI_CLR03_S3_M 0xFF000000 // A high bit value will clear the // corresponding bit in ADI // register 3 -#define ADI_CLR03_S3_S 24 -#define ADI_CLR03_S2_M 0x00FF0000 // A high bit value will clear the +#define ADI_CLR03_S3_S 24 +#define ADI_CLR03_S2_M 0x00FF0000 // A high bit value will clear the // corresponding bit in ADI // register 2 -#define ADI_CLR03_S2_S 16 -#define ADI_CLR03_S1_M 0x0000FF00 // A high bit value will clear the +#define ADI_CLR03_S2_S 16 +#define ADI_CLR03_S1_M 0x0000FF00 // A high bit value will clear the // corresponding bit in ADI // register 1 -#define ADI_CLR03_S1_S 8 -#define ADI_CLR03_S0_M 0x000000FF // A high bit value will clear the +#define ADI_CLR03_S1_S 8 +#define ADI_CLR03_S0_M 0x000000FF // A high bit value will clear the // corresponding bit in ADI // register 0 -#define ADI_CLR03_S0_S 0 +#define ADI_CLR03_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_CLR47 register. // //***************************************************************************** -#define ADI_CLR47_S3_M 0xFF000000 // A high bit value will clear the +#define ADI_CLR47_S3_M 0xFF000000 // A high bit value will clear the // corresponding bit in ADI // register 7 -#define ADI_CLR47_S3_S 24 -#define ADI_CLR47_S2_M 0x00FF0000 // A high bit value will clear the +#define ADI_CLR47_S3_S 24 +#define ADI_CLR47_S2_M 0x00FF0000 // A high bit value will clear the // corresponding bit in ADI // register 6 -#define ADI_CLR47_S2_S 16 -#define ADI_CLR47_S1_M 0x0000FF00 // A high bit value will clear the +#define ADI_CLR47_S2_S 16 +#define ADI_CLR47_S1_M 0x0000FF00 // A high bit value will clear the // corresponding bit in ADI // register 5 -#define ADI_CLR47_S1_S 8 -#define ADI_CLR47_S0_M 0x000000FF // A high bit value will clear the +#define ADI_CLR47_S1_S 8 +#define ADI_CLR47_S0_M 0x000000FF // A high bit value will clear the // corresponding bit in ADI // register 4 -#define ADI_CLR47_S0_S 0 +#define ADI_CLR47_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_CLR811 register. // //***************************************************************************** -#define ADI_CLR811_S3_M 0xFF000000 // A high bit value will clear the +#define ADI_CLR811_S3_M 0xFF000000 // A high bit value will clear the // corresponding bit in ADI // register 11 -#define ADI_CLR811_S3_S 24 -#define ADI_CLR811_S2_M 0x00FF0000 // A high bit value will clear the +#define ADI_CLR811_S3_S 24 +#define ADI_CLR811_S2_M 0x00FF0000 // A high bit value will clear the // corresponding bit in ADI // register 10 -#define ADI_CLR811_S2_S 16 -#define ADI_CLR811_S1_M 0x0000FF00 // A high bit value will clear the +#define ADI_CLR811_S2_S 16 +#define ADI_CLR811_S1_M 0x0000FF00 // A high bit value will clear the // corresponding bit in ADI // register 9 -#define ADI_CLR811_S1_S 8 -#define ADI_CLR811_S0_M 0x000000FF // A high bit value will clear the +#define ADI_CLR811_S1_S 8 +#define ADI_CLR811_S0_M 0x000000FF // A high bit value will clear the // corresponding bit in ADI // register 8 -#define ADI_CLR811_S0_S 0 +#define ADI_CLR811_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_CLR1215 register. // //***************************************************************************** -#define ADI_CLR1215_S3_M 0xFF000000 // A high bit value will clear the +#define ADI_CLR1215_S3_M 0xFF000000 // A high bit value will clear the // corresponding bit in ADI // register 15 -#define ADI_CLR1215_S3_S 24 -#define ADI_CLR1215_S2_M 0x00FF0000 // A high bit value will clear the +#define ADI_CLR1215_S3_S 24 +#define ADI_CLR1215_S2_M 0x00FF0000 // A high bit value will clear the // corresponding bit in ADI // register 14 -#define ADI_CLR1215_S2_S 16 -#define ADI_CLR1215_S1_M 0x0000FF00 // A high bit value will clear the +#define ADI_CLR1215_S2_S 16 +#define ADI_CLR1215_S1_M 0x0000FF00 // A high bit value will clear the // corresponding bit in ADI // register 13 -#define ADI_CLR1215_S1_S 8 -#define ADI_CLR1215_S0_M 0x000000FF // A high bit value will clear the +#define ADI_CLR1215_S1_S 8 +#define ADI_CLR1215_S0_M 0x000000FF // A high bit value will clear the // corresponding bit in ADI // register 12 -#define ADI_CLR1215_S0_S 0 +#define ADI_CLR1215_S0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_SLAVESTAT register. // //***************************************************************************** -#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ +#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ // signal. Writing 0 to this bit // forces a sync with slave, // ensuring that req will be 0. It // is recommended to write 0 to // this register before power down // of the master. -#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 -#define ADI_SLAVESTAT_DI_REQ_S 1 -#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK +#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 +#define ADI_SLAVESTAT_DI_REQ_S 1 +#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK // signal -#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 -#define ADI_SLAVESTAT_DI_ACK_S 0 +#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 +#define ADI_SLAVESTAT_DI_ACK_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_SLAVECONF register. // //***************************************************************************** -#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer +#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer // accessible when this bit is set. // (unless sticky_bit_overwrite is // asserted on top module) @@ -609,7 +609,7 @@ 0x00000080 #define ADI_SLAVECONF_CONFLOCK_S 7 #define ADI_SLAVECONF_WAITFORACK \ - 0x00000004 // A transaction on the ADI + 0x00000004 // A transaction on the ADI // interface does not end until ack // has been received from the slave // when this bit is set. @@ -618,7 +618,7 @@ 0x00000004 #define ADI_SLAVECONF_WAITFORACK_S 2 #define ADI_SLAVECONF_ADICLKSPEED_M \ - 0x00000003 // Sets the period of an ADI + 0x00000003 // Sets the period of an ADI // transactions. All transactions // takes an even number of clock // cycles,- ADI clock rising edge @@ -641,542 +641,542 @@ // The following are defines for the bit fields in the ADI_O_MASK4B01 register. // //***************************************************************************** -#define ADI_MASK4B01_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B01_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 1 -#define ADI_MASK4B01_M1H_S 28 -#define ADI_MASK4B01_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B01_M1H_S 28 +#define ADI_MASK4B01_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 1, - only bits selected // by mask M1H will be affected by // access -#define ADI_MASK4B01_D1H_S 24 -#define ADI_MASK4B01_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B01_D1H_S 24 +#define ADI_MASK4B01_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 1 -#define ADI_MASK4B01_M1L_S 20 -#define ADI_MASK4B01_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B01_M1L_S 20 +#define ADI_MASK4B01_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 1, - only bits selected // by mask M1L will be affected by // access -#define ADI_MASK4B01_D1L_S 16 -#define ADI_MASK4B01_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B01_D1L_S 16 +#define ADI_MASK4B01_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 0 -#define ADI_MASK4B01_M0H_S 12 -#define ADI_MASK4B01_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B01_M0H_S 12 +#define ADI_MASK4B01_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 0, - only bits selected // by mask M0H will be affected by // access -#define ADI_MASK4B01_D0H_S 8 -#define ADI_MASK4B01_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B01_D0H_S 8 +#define ADI_MASK4B01_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 0 -#define ADI_MASK4B01_M0L_S 4 -#define ADI_MASK4B01_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B01_M0L_S 4 +#define ADI_MASK4B01_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 0, - only bits selected // by mask M0L will be affected by // access -#define ADI_MASK4B01_D0L_S 0 +#define ADI_MASK4B01_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK4B23 register. // //***************************************************************************** -#define ADI_MASK4B23_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B23_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 3 -#define ADI_MASK4B23_M1H_S 28 -#define ADI_MASK4B23_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B23_M1H_S 28 +#define ADI_MASK4B23_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 3, - only bits selected // by mask M1H will be affected by // access -#define ADI_MASK4B23_D1H_S 24 -#define ADI_MASK4B23_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B23_D1H_S 24 +#define ADI_MASK4B23_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 3 -#define ADI_MASK4B23_M1L_S 20 -#define ADI_MASK4B23_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B23_M1L_S 20 +#define ADI_MASK4B23_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 3, - only bits selected // by mask M1L will be affected by // access -#define ADI_MASK4B23_D1L_S 16 -#define ADI_MASK4B23_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B23_D1L_S 16 +#define ADI_MASK4B23_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 2 -#define ADI_MASK4B23_M0H_S 12 -#define ADI_MASK4B23_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B23_M0H_S 12 +#define ADI_MASK4B23_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 2, - only bits selected // by mask M0H will be affected by // access -#define ADI_MASK4B23_D0H_S 8 -#define ADI_MASK4B23_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B23_D0H_S 8 +#define ADI_MASK4B23_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 2 -#define ADI_MASK4B23_M0L_S 4 -#define ADI_MASK4B23_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B23_M0L_S 4 +#define ADI_MASK4B23_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 2, - only bits selected // by mask M0L will be affected by // access -#define ADI_MASK4B23_D0L_S 0 +#define ADI_MASK4B23_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK4B45 register. // //***************************************************************************** -#define ADI_MASK4B45_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B45_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 5 -#define ADI_MASK4B45_M1H_S 28 -#define ADI_MASK4B45_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B45_M1H_S 28 +#define ADI_MASK4B45_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 5, - only bits selected // by mask M1H will be affected by // access -#define ADI_MASK4B45_D1H_S 24 -#define ADI_MASK4B45_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B45_D1H_S 24 +#define ADI_MASK4B45_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 5 -#define ADI_MASK4B45_M1L_S 20 -#define ADI_MASK4B45_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B45_M1L_S 20 +#define ADI_MASK4B45_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 5, - only bits selected // by mask M1L will be affected by // access -#define ADI_MASK4B45_D1L_S 16 -#define ADI_MASK4B45_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B45_D1L_S 16 +#define ADI_MASK4B45_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 4 -#define ADI_MASK4B45_M0H_S 12 -#define ADI_MASK4B45_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B45_M0H_S 12 +#define ADI_MASK4B45_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 4, - only bits selected // by mask M0H will be affected by // access -#define ADI_MASK4B45_D0H_S 8 -#define ADI_MASK4B45_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B45_D0H_S 8 +#define ADI_MASK4B45_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 4 -#define ADI_MASK4B45_M0L_S 4 -#define ADI_MASK4B45_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B45_M0L_S 4 +#define ADI_MASK4B45_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 4, - only bits selected // by mask M0L will be affected by // access -#define ADI_MASK4B45_D0L_S 0 +#define ADI_MASK4B45_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK4B67 register. // //***************************************************************************** -#define ADI_MASK4B67_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B67_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 7 -#define ADI_MASK4B67_M1H_S 28 -#define ADI_MASK4B67_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B67_M1H_S 28 +#define ADI_MASK4B67_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 7, - only bits selected // by mask M1H will be affected by // access -#define ADI_MASK4B67_D1H_S 24 -#define ADI_MASK4B67_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B67_D1H_S 24 +#define ADI_MASK4B67_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 7 -#define ADI_MASK4B67_M1L_S 20 -#define ADI_MASK4B67_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B67_M1L_S 20 +#define ADI_MASK4B67_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 7, - only bits selected // by mask M1L will be affected by // access -#define ADI_MASK4B67_D1L_S 16 -#define ADI_MASK4B67_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B67_D1L_S 16 +#define ADI_MASK4B67_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 6 -#define ADI_MASK4B67_M0H_S 12 -#define ADI_MASK4B67_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B67_M0H_S 12 +#define ADI_MASK4B67_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 6, - only bits selected // by mask M0H will be affected by // access -#define ADI_MASK4B67_D0H_S 8 -#define ADI_MASK4B67_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B67_D0H_S 8 +#define ADI_MASK4B67_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 6 -#define ADI_MASK4B67_M0L_S 4 -#define ADI_MASK4B67_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B67_M0L_S 4 +#define ADI_MASK4B67_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 6, - only bits selected // by mask M0L will be affected by // access -#define ADI_MASK4B67_D0L_S 0 +#define ADI_MASK4B67_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK4B89 register. // //***************************************************************************** -#define ADI_MASK4B89_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B89_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 9 -#define ADI_MASK4B89_M1H_S 28 -#define ADI_MASK4B89_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B89_M1H_S 28 +#define ADI_MASK4B89_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 9, - only bits selected // by mask M1H will be affected by // access -#define ADI_MASK4B89_D1H_S 24 -#define ADI_MASK4B89_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B89_D1H_S 24 +#define ADI_MASK4B89_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 9 -#define ADI_MASK4B89_M1L_S 20 -#define ADI_MASK4B89_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B89_M1L_S 20 +#define ADI_MASK4B89_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 9, - only bits selected // by mask M1L will be affected by // access -#define ADI_MASK4B89_D1L_S 16 -#define ADI_MASK4B89_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B89_D1L_S 16 +#define ADI_MASK4B89_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 8 -#define ADI_MASK4B89_M0H_S 12 -#define ADI_MASK4B89_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B89_M0H_S 12 +#define ADI_MASK4B89_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 8, - only bits selected // by mask M0H will be affected by // access -#define ADI_MASK4B89_D0H_S 8 -#define ADI_MASK4B89_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B89_D0H_S 8 +#define ADI_MASK4B89_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 8 -#define ADI_MASK4B89_M0L_S 4 -#define ADI_MASK4B89_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B89_M0L_S 4 +#define ADI_MASK4B89_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 8, - only bits selected // by mask M0L will be affected by // access -#define ADI_MASK4B89_D0L_S 0 +#define ADI_MASK4B89_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK4B1011 register. // //***************************************************************************** -#define ADI_MASK4B1011_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B1011_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 11 -#define ADI_MASK4B1011_M1H_S 28 -#define ADI_MASK4B1011_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B1011_M1H_S 28 +#define ADI_MASK4B1011_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 11, - only bits // selected by mask M1H will be // affected by access -#define ADI_MASK4B1011_D1H_S 24 -#define ADI_MASK4B1011_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B1011_D1H_S 24 +#define ADI_MASK4B1011_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 11 -#define ADI_MASK4B1011_M1L_S 20 -#define ADI_MASK4B1011_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B1011_M1L_S 20 +#define ADI_MASK4B1011_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 11, - only bits // selected by mask M1L will be // affected by access -#define ADI_MASK4B1011_D1L_S 16 -#define ADI_MASK4B1011_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B1011_D1L_S 16 +#define ADI_MASK4B1011_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 10 -#define ADI_MASK4B1011_M0H_S 12 -#define ADI_MASK4B1011_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B1011_M0H_S 12 +#define ADI_MASK4B1011_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 10, - only bits // selected by mask M0H will be // affected by access -#define ADI_MASK4B1011_D0H_S 8 -#define ADI_MASK4B1011_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B1011_D0H_S 8 +#define ADI_MASK4B1011_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 10 -#define ADI_MASK4B1011_M0L_S 4 -#define ADI_MASK4B1011_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B1011_M0L_S 4 +#define ADI_MASK4B1011_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 10, - only bits // selected by mask M0L will be // affected by access -#define ADI_MASK4B1011_D0L_S 0 +#define ADI_MASK4B1011_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK4B1213 register. // //***************************************************************************** -#define ADI_MASK4B1213_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B1213_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 13 -#define ADI_MASK4B1213_M1H_S 28 -#define ADI_MASK4B1213_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B1213_M1H_S 28 +#define ADI_MASK4B1213_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 13, - only bits // selected by mask M1H will be // affected by access -#define ADI_MASK4B1213_D1H_S 24 -#define ADI_MASK4B1213_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B1213_D1H_S 24 +#define ADI_MASK4B1213_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 13 -#define ADI_MASK4B1213_M1L_S 20 -#define ADI_MASK4B1213_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B1213_M1L_S 20 +#define ADI_MASK4B1213_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 13, - only bits // selected by mask M1L will be // affected by access -#define ADI_MASK4B1213_D1L_S 16 -#define ADI_MASK4B1213_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B1213_D1L_S 16 +#define ADI_MASK4B1213_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 12 -#define ADI_MASK4B1213_M0H_S 12 -#define ADI_MASK4B1213_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B1213_M0H_S 12 +#define ADI_MASK4B1213_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 12, - only bits // selected by mask M0H will be // affected by access -#define ADI_MASK4B1213_D0H_S 8 -#define ADI_MASK4B1213_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B1213_D0H_S 8 +#define ADI_MASK4B1213_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 12 -#define ADI_MASK4B1213_M0L_S 4 -#define ADI_MASK4B1213_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B1213_M0L_S 4 +#define ADI_MASK4B1213_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 12, - only bits // selected by mask M0L will be // affected by access -#define ADI_MASK4B1213_D0L_S 0 +#define ADI_MASK4B1213_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK4B1415 register. // //***************************************************************************** -#define ADI_MASK4B1415_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B1415_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI // register 15 -#define ADI_MASK4B1415_M1H_S 28 -#define ADI_MASK4B1415_D1H_M 0x0F000000 // Data for bits [7:4] in ADI +#define ADI_MASK4B1415_M1H_S 28 +#define ADI_MASK4B1415_D1H_M 0x0F000000 // Data for bits [7:4] in ADI // register 15, - only bits // selected by mask M1H will be // affected by access -#define ADI_MASK4B1415_D1H_S 24 -#define ADI_MASK4B1415_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI +#define ADI_MASK4B1415_D1H_S 24 +#define ADI_MASK4B1415_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI // register 15 -#define ADI_MASK4B1415_M1L_S 20 -#define ADI_MASK4B1415_D1L_M 0x000F0000 // Data for bits [3:0] in ADI +#define ADI_MASK4B1415_M1L_S 20 +#define ADI_MASK4B1415_D1L_M 0x000F0000 // Data for bits [3:0] in ADI // register 15, - only bits // selected by mask M1L will be // affected by access -#define ADI_MASK4B1415_D1L_S 16 -#define ADI_MASK4B1415_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI +#define ADI_MASK4B1415_D1L_S 16 +#define ADI_MASK4B1415_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI // register 14 -#define ADI_MASK4B1415_M0H_S 12 -#define ADI_MASK4B1415_D0H_M 0x00000F00 // Data for bits [7:4] in ADI +#define ADI_MASK4B1415_M0H_S 12 +#define ADI_MASK4B1415_D0H_M 0x00000F00 // Data for bits [7:4] in ADI // register 14, - only bits // selected by mask M0H will be // affected by access -#define ADI_MASK4B1415_D0H_S 8 -#define ADI_MASK4B1415_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI +#define ADI_MASK4B1415_D0H_S 8 +#define ADI_MASK4B1415_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI // register 14 -#define ADI_MASK4B1415_M0L_S 4 -#define ADI_MASK4B1415_D0L_M 0x0000000F // Data for bits [3:0] in ADI +#define ADI_MASK4B1415_M0L_S 4 +#define ADI_MASK4B1415_D0L_M 0x0000000F // Data for bits [3:0] in ADI // register 14, - only bits // selected by mask M0L will be // affected by access -#define ADI_MASK4B1415_D0L_S 0 +#define ADI_MASK4B1415_D0L_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK8B01 register. // //***************************************************************************** -#define ADI_MASK8B01_M1_M 0xFF000000 // Mask for ADI register 1 -#define ADI_MASK8B01_M1_S 24 -#define ADI_MASK8B01_D1_M 0x00FF0000 // Data for ADI register 1, - only +#define ADI_MASK8B01_M1_M 0xFF000000 // Mask for ADI register 1 +#define ADI_MASK8B01_M1_S 24 +#define ADI_MASK8B01_D1_M 0x00FF0000 // Data for ADI register 1, - only // bits selected by mask M1 will be // affected by access -#define ADI_MASK8B01_D1_S 16 -#define ADI_MASK8B01_M0_M 0x0000FF00 // Mask for ADI register 0 -#define ADI_MASK8B01_M0_S 8 -#define ADI_MASK8B01_D0_M 0x000000FF // Data for ADI register 0, - only +#define ADI_MASK8B01_D1_S 16 +#define ADI_MASK8B01_M0_M 0x0000FF00 // Mask for ADI register 0 +#define ADI_MASK8B01_M0_S 8 +#define ADI_MASK8B01_D0_M 0x000000FF // Data for ADI register 0, - only // bits selected by mask M0 will be // affected by access -#define ADI_MASK8B01_D0_S 0 +#define ADI_MASK8B01_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK8B23 register. // //***************************************************************************** -#define ADI_MASK8B23_M1_M 0xFF000000 // Mask for ADI register 3 -#define ADI_MASK8B23_M1_S 24 -#define ADI_MASK8B23_D1_M 0x00FF0000 // Data for ADI register 3, - only +#define ADI_MASK8B23_M1_M 0xFF000000 // Mask for ADI register 3 +#define ADI_MASK8B23_M1_S 24 +#define ADI_MASK8B23_D1_M 0x00FF0000 // Data for ADI register 3, - only // bits selected by mask M1 will be // affected by access -#define ADI_MASK8B23_D1_S 16 -#define ADI_MASK8B23_M0_M 0x0000FF00 // Mask for ADI register 2 -#define ADI_MASK8B23_M0_S 8 -#define ADI_MASK8B23_D0_M 0x000000FF // Data for ADI register 2, - only +#define ADI_MASK8B23_D1_S 16 +#define ADI_MASK8B23_M0_M 0x0000FF00 // Mask for ADI register 2 +#define ADI_MASK8B23_M0_S 8 +#define ADI_MASK8B23_D0_M 0x000000FF // Data for ADI register 2, - only // bits selected by mask M0 will be // affected by access -#define ADI_MASK8B23_D0_S 0 +#define ADI_MASK8B23_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK8B45 register. // //***************************************************************************** -#define ADI_MASK8B45_M1_M 0xFF000000 // Mask for ADI register 5 -#define ADI_MASK8B45_M1_S 24 -#define ADI_MASK8B45_D1_M 0x00FF0000 // Data for ADI register 5, - only +#define ADI_MASK8B45_M1_M 0xFF000000 // Mask for ADI register 5 +#define ADI_MASK8B45_M1_S 24 +#define ADI_MASK8B45_D1_M 0x00FF0000 // Data for ADI register 5, - only // bits selected by mask M1 will be // affected by access -#define ADI_MASK8B45_D1_S 16 -#define ADI_MASK8B45_M0_M 0x0000FF00 // Mask for ADI register 4 -#define ADI_MASK8B45_M0_S 8 -#define ADI_MASK8B45_D0_M 0x000000FF // Data for ADI register 4, - only +#define ADI_MASK8B45_D1_S 16 +#define ADI_MASK8B45_M0_M 0x0000FF00 // Mask for ADI register 4 +#define ADI_MASK8B45_M0_S 8 +#define ADI_MASK8B45_D0_M 0x000000FF // Data for ADI register 4, - only // bits selected by mask M0 will be // affected by access -#define ADI_MASK8B45_D0_S 0 +#define ADI_MASK8B45_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK8B67 register. // //***************************************************************************** -#define ADI_MASK8B67_M1_M 0xFF000000 // Mask for ADI register 7 -#define ADI_MASK8B67_M1_S 24 -#define ADI_MASK8B67_D1_M 0x00FF0000 // Data for ADI register 7, - only +#define ADI_MASK8B67_M1_M 0xFF000000 // Mask for ADI register 7 +#define ADI_MASK8B67_M1_S 24 +#define ADI_MASK8B67_D1_M 0x00FF0000 // Data for ADI register 7, - only // bits selected by mask M1 will be // affected by access -#define ADI_MASK8B67_D1_S 16 -#define ADI_MASK8B67_M0_M 0x0000FF00 // Mask for ADI register 6 -#define ADI_MASK8B67_M0_S 8 -#define ADI_MASK8B67_D0_M 0x000000FF // Data for ADI register 6, - only +#define ADI_MASK8B67_D1_S 16 +#define ADI_MASK8B67_M0_M 0x0000FF00 // Mask for ADI register 6 +#define ADI_MASK8B67_M0_S 8 +#define ADI_MASK8B67_D0_M 0x000000FF // Data for ADI register 6, - only // bits selected by mask M0 will be // affected by access -#define ADI_MASK8B67_D0_S 0 +#define ADI_MASK8B67_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the ADI_O_MASK8B89 register. // //***************************************************************************** -#define ADI_MASK8B89_M1_M 0xFF000000 // Mask for ADI register 9 -#define ADI_MASK8B89_M1_S 24 -#define ADI_MASK8B89_D1_M 0x00FF0000 // Data for ADI register 9, - only +#define ADI_MASK8B89_M1_M 0xFF000000 // Mask for ADI register 9 +#define ADI_MASK8B89_M1_S 24 +#define ADI_MASK8B89_D1_M 0x00FF0000 // Data for ADI register 9, - only // bits selected by mask M1 will be // affected by access -#define ADI_MASK8B89_D1_S 16 -#define ADI_MASK8B89_M0_M 0x0000FF00 // Mask for ADI register 8 -#define ADI_MASK8B89_M0_S 8 -#define ADI_MASK8B89_D0_M 0x000000FF // Data for ADI register 8, - only +#define ADI_MASK8B89_D1_S 16 +#define ADI_MASK8B89_M0_M 0x0000FF00 // Mask for ADI register 8 +#define ADI_MASK8B89_M0_S 8 +#define ADI_MASK8B89_D0_M 0x000000FF // Data for ADI register 8, - only // bits selected by mask M0 will be // affected by access -#define ADI_MASK8B89_D0_S 0 +#define ADI_MASK8B89_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK8B1011 register. // //***************************************************************************** -#define ADI_MASK8B1011_M1_M 0xFF000000 // Mask for ADI register 11 -#define ADI_MASK8B1011_M1_S 24 -#define ADI_MASK8B1011_D1_M 0x00FF0000 // Data for ADI register 11, - +#define ADI_MASK8B1011_M1_M 0xFF000000 // Mask for ADI register 11 +#define ADI_MASK8B1011_M1_S 24 +#define ADI_MASK8B1011_D1_M 0x00FF0000 // Data for ADI register 11, - // only bits selected by mask M1 // will be affected by access -#define ADI_MASK8B1011_D1_S 16 -#define ADI_MASK8B1011_M0_M 0x0000FF00 // Mask for ADI register 10 -#define ADI_MASK8B1011_M0_S 8 -#define ADI_MASK8B1011_D0_M 0x000000FF // Data for ADI register 10, - +#define ADI_MASK8B1011_D1_S 16 +#define ADI_MASK8B1011_M0_M 0x0000FF00 // Mask for ADI register 10 +#define ADI_MASK8B1011_M0_S 8 +#define ADI_MASK8B1011_D0_M 0x000000FF // Data for ADI register 10, - // only bits selected by mask M0 // will be affected by access -#define ADI_MASK8B1011_D0_S 0 +#define ADI_MASK8B1011_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK8B1213 register. // //***************************************************************************** -#define ADI_MASK8B1213_M1_M 0xFF000000 // Mask for ADI register 13 -#define ADI_MASK8B1213_M1_S 24 -#define ADI_MASK8B1213_D1_M 0x00FF0000 // Data for ADI register 13, - +#define ADI_MASK8B1213_M1_M 0xFF000000 // Mask for ADI register 13 +#define ADI_MASK8B1213_M1_S 24 +#define ADI_MASK8B1213_D1_M 0x00FF0000 // Data for ADI register 13, - // only bits selected by mask M1 // will be affected by access -#define ADI_MASK8B1213_D1_S 16 -#define ADI_MASK8B1213_M0_M 0x0000FF00 // Mask for ADI register 12 -#define ADI_MASK8B1213_M0_S 8 -#define ADI_MASK8B1213_D0_M 0x000000FF // Data for ADI register 12, - +#define ADI_MASK8B1213_D1_S 16 +#define ADI_MASK8B1213_M0_M 0x0000FF00 // Mask for ADI register 12 +#define ADI_MASK8B1213_M0_S 8 +#define ADI_MASK8B1213_D0_M 0x000000FF // Data for ADI register 12, - // only bits selected by mask M0 // will be affected by access -#define ADI_MASK8B1213_D0_S 0 +#define ADI_MASK8B1213_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK8B1415 register. // //***************************************************************************** -#define ADI_MASK8B1415_M1_M 0xFF000000 // Mask for ADI register 15 -#define ADI_MASK8B1415_M1_S 24 -#define ADI_MASK8B1415_D1_M 0x00FF0000 // Data for ADI register 15, - +#define ADI_MASK8B1415_M1_M 0xFF000000 // Mask for ADI register 15 +#define ADI_MASK8B1415_M1_S 24 +#define ADI_MASK8B1415_D1_M 0x00FF0000 // Data for ADI register 15, - // only bits selected by mask M1 // will be affected by access -#define ADI_MASK8B1415_D1_S 16 -#define ADI_MASK8B1415_M0_M 0x0000FF00 // Mask for ADI register 14 -#define ADI_MASK8B1415_M0_S 8 -#define ADI_MASK8B1415_D0_M 0x000000FF // Data for ADI register 14, - +#define ADI_MASK8B1415_D1_S 16 +#define ADI_MASK8B1415_M0_M 0x0000FF00 // Mask for ADI register 14 +#define ADI_MASK8B1415_M0_S 8 +#define ADI_MASK8B1415_D0_M 0x000000FF // Data for ADI register 14, - // only bits selected by mask M0 // will be affected by access -#define ADI_MASK8B1415_D0_S 0 +#define ADI_MASK8B1415_D0_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B01 register. // //***************************************************************************** -#define ADI_MASK16B01_M_M 0xFFFF0000 // Mask for ADI register 0 and 1 -#define ADI_MASK16B01_M_S 16 -#define ADI_MASK16B01_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B01_M_M 0xFFFF0000 // Mask for ADI register 0 and 1 +#define ADI_MASK16B01_M_S 16 +#define ADI_MASK16B01_D_M 0x0000FFFF // Data for ADI register at // offsets 0 and 1, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B01_D_S 0 +#define ADI_MASK16B01_D_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B23 register. // //***************************************************************************** -#define ADI_MASK16B23_M_M 0xFFFF0000 // Mask for ADI register 2 and 3 -#define ADI_MASK16B23_M_S 16 -#define ADI_MASK16B23_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B23_M_M 0xFFFF0000 // Mask for ADI register 2 and 3 +#define ADI_MASK16B23_M_S 16 +#define ADI_MASK16B23_D_M 0x0000FFFF // Data for ADI register at // offsets 2 and 3, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B23_D_S 0 +#define ADI_MASK16B23_D_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B45 register. // //***************************************************************************** -#define ADI_MASK16B45_M_M 0xFFFF0000 // Mask for ADI register 4 and 5 -#define ADI_MASK16B45_M_S 16 -#define ADI_MASK16B45_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B45_M_M 0xFFFF0000 // Mask for ADI register 4 and 5 +#define ADI_MASK16B45_M_S 16 +#define ADI_MASK16B45_D_M 0x0000FFFF // Data for ADI register at // offsets 4 and 5, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B45_D_S 0 +#define ADI_MASK16B45_D_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B67 register. // //***************************************************************************** -#define ADI_MASK16B67_M_M 0xFFFF0000 // Mask for ADI register 6 and 7 -#define ADI_MASK16B67_M_S 16 -#define ADI_MASK16B67_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B67_M_M 0xFFFF0000 // Mask for ADI register 6 and 7 +#define ADI_MASK16B67_M_S 16 +#define ADI_MASK16B67_D_M 0x0000FFFF // Data for ADI register at // offsets 6 and 7, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B67_D_S 0 +#define ADI_MASK16B67_D_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B89 register. // //***************************************************************************** -#define ADI_MASK16B89_M_M 0xFFFF0000 // Mask for ADI register 8 and 9 -#define ADI_MASK16B89_M_S 16 -#define ADI_MASK16B89_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B89_M_M 0xFFFF0000 // Mask for ADI register 8 and 9 +#define ADI_MASK16B89_M_S 16 +#define ADI_MASK16B89_D_M 0x0000FFFF // Data for ADI register at // offsets 8 and 9, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B89_D_S 0 +#define ADI_MASK16B89_D_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B1011 register. // //***************************************************************************** -#define ADI_MASK16B1011_M_M 0xFFFF0000 // Mask for ADI register 10 and 11 -#define ADI_MASK16B1011_M_S 16 -#define ADI_MASK16B1011_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B1011_M_M 0xFFFF0000 // Mask for ADI register 10 and 11 +#define ADI_MASK16B1011_M_S 16 +#define ADI_MASK16B1011_D_M 0x0000FFFF // Data for ADI register at // offsets 10 and 11, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B1011_D_S 0 +#define ADI_MASK16B1011_D_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B1213 register. // //***************************************************************************** -#define ADI_MASK16B1213_M_M 0xFFFF0000 // Mask for ADI register 12 and 13 -#define ADI_MASK16B1213_M_S 16 -#define ADI_MASK16B1213_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B1213_M_M 0xFFFF0000 // Mask for ADI register 12 and 13 +#define ADI_MASK16B1213_M_S 16 +#define ADI_MASK16B1213_D_M 0x0000FFFF // Data for ADI register at // offsets 12 and 13, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B1213_D_S 0 +#define ADI_MASK16B1213_D_S 0 //***************************************************************************** // // The following are defines for the bit fields in the // ADI_O_MASK16B1415 register. // //***************************************************************************** -#define ADI_MASK16B1415_M_M 0xFFFF0000 // Mask for ADI register 14 and 15 -#define ADI_MASK16B1415_M_S 16 -#define ADI_MASK16B1415_D_M 0x0000FFFF // Data for ADI register at +#define ADI_MASK16B1415_M_M 0xFFFF0000 // Mask for ADI register 14 and 15 +#define ADI_MASK16B1415_M_S 16 +#define ADI_MASK16B1415_D_M 0x0000FFFF // Data for ADI register at // offsets 14 and 15, - only bits // selected by mask M will be // affected by access -#define ADI_MASK16B1415_D_S 0 +#define ADI_MASK16B1415_D_S 0 #endif // __HW_ADI_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi_2_refsys.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi_2_refsys.h index 72ae2eb..2af8af2 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi_2_refsys.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi_2_refsys.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_adi_2_refsys_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_adi_2_refsys_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_ADI_2_REFSYS_H__ #define __HW_ADI_2_REFSYS_H__ @@ -44,34 +44,34 @@ // //***************************************************************************** // Internal -#define ADI_2_REFSYS_O_REFSYSCTL0 0x00000000 +#define ADI_2_REFSYS_O_REFSYSCTL0 0x00000000 // Internal -#define ADI_2_REFSYS_O_SOCLDOCTL0 0x00000002 +#define ADI_2_REFSYS_O_SOCLDOCTL0 0x00000002 // Internal -#define ADI_2_REFSYS_O_SOCLDOCTL1 0x00000003 +#define ADI_2_REFSYS_O_SOCLDOCTL1 0x00000003 // Internal -#define ADI_2_REFSYS_O_SOCLDOCTL2 0x00000004 +#define ADI_2_REFSYS_O_SOCLDOCTL2 0x00000004 // Internal -#define ADI_2_REFSYS_O_SOCLDOCTL3 0x00000005 +#define ADI_2_REFSYS_O_SOCLDOCTL3 0x00000005 // Internal -#define ADI_2_REFSYS_O_SOCLDOCTL4 0x00000006 +#define ADI_2_REFSYS_O_SOCLDOCTL4 0x00000006 // Internal -#define ADI_2_REFSYS_O_SOCLDOCTL5 0x00000007 +#define ADI_2_REFSYS_O_SOCLDOCTL5 0x00000007 // Internal -#define ADI_2_REFSYS_O_HPOSCCTL0 0x0000000A +#define ADI_2_REFSYS_O_HPOSCCTL0 0x0000000A // Internal -#define ADI_2_REFSYS_O_HPOSCCTL1 0x0000000B +#define ADI_2_REFSYS_O_HPOSCCTL1 0x0000000B // Internal -#define ADI_2_REFSYS_O_HPOSCCTL2 0x0000000C +#define ADI_2_REFSYS_O_HPOSCCTL2 0x0000000C //***************************************************************************** // @@ -81,9 +81,9 @@ // Field: [4:0] TRIM_IREF // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_W 5 -#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_M 0x0000001F -#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_S 0 +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_W 5 +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_M 0x0000001F +#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_S 0 //***************************************************************************** // @@ -93,16 +93,16 @@ // Field: [7:4] VTRIM_UDIG // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_W 4 -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_M 0x000000F0 -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_S 4 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_W 4 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_M 0x000000F0 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_S 4 // Field: [3:0] VTRIM_BOD // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_W 4 -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_M 0x0000000F -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_S 0 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_W 4 +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_M 0x0000000F +#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_S 0 //***************************************************************************** // @@ -112,16 +112,16 @@ // Field: [7:4] VTRIM_COARSE // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_W 4 -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_M 0x000000F0 -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_S 4 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_W 4 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_M 0x000000F0 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_S 4 // Field: [3:0] VTRIM_DIG // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_W 4 -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_M 0x0000000F -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_S 0 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_W 4 +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_M 0x0000000F +#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_S 0 //***************************************************************************** // @@ -131,9 +131,9 @@ // Field: [2:0] VTRIM_DELTA // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_W 3 -#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_M 0x00000007 -#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_S 0 +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_W 3 +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_S 0 //***************************************************************************** // @@ -143,9 +143,9 @@ // Field: [7:6] ITRIM_DIGLDO_LOAD // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_W 2 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_M 0x000000C0 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_S 6 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_W 2 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_M 0x000000C0 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_S 6 // Field: [5:3] ITRIM_DIGLDO // @@ -155,20 +155,20 @@ // BIAS_100P Internal. Only to be used through TI provided API. // BIAS_80P Internal. Only to be used through TI provided API. // BIAS_60P Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_W 3 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_M 0x00000038 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_S 3 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_120P 0x00000038 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_100P 0x00000028 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_80P 0x00000018 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_60P 0x00000000 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_W 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_M 0x00000038 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_S 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_120P 0x00000038 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_100P 0x00000028 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_80P 0x00000018 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_60P 0x00000000 // Field: [2:0] ITRIM_UDIGLDO // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_W 3 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_M 0x00000007 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_S 0 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_W 3 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_S 0 //***************************************************************************** // @@ -178,23 +178,23 @@ // Field: [6:5] UDIG_ITEST_EN // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_W 2 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_M 0x00000060 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_S 5 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_W 2 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_M 0x00000060 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_S 5 // Field: [4:2] DIG_ITEST_EN // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_W 3 -#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_M 0x0000001C -#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_S 2 +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_W 3 +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_M 0x0000001C +#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_S 2 // Field: [1] BIAS_DIS // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS 0x00000002 -#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_M 0x00000002 -#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_S 1 +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_M 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_S 1 // Field: [0] UDIG_LDO_EN // @@ -202,11 +202,11 @@ // ENUMs: // EN Internal. Only to be used through TI provided API. // DIS Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN 0x00000001 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_M 0x00000001 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_S 0 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_EN 0x00000001 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_DIS 0x00000000 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_M 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_S 0 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_EN 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_DIS 0x00000000 //***************************************************************************** // @@ -216,9 +216,9 @@ // Field: [3] IMON_ITEST_EN // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN 0x00000008 -#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_M 0x00000008 -#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_S 3 +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN 0x00000008 +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_M 0x00000008 +#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_S 3 // Field: [2:0] TESTSEL // @@ -228,13 +228,13 @@ // VREF_AMP Internal. Only to be used through TI provided API. // ITEST Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_W 3 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_M 0x00000007 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_S 0 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VDD_AON 0x00000004 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VREF_AMP 0x00000002 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_ITEST 0x00000001 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_NC 0x00000000 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_W 3 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_M 0x00000007 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_S 0 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VDD_AON 0x00000004 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VREF_AMP 0x00000002 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_ITEST 0x00000001 +#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_NC 0x00000000 //***************************************************************************** // @@ -244,9 +244,9 @@ // Field: [7] FILTER_EN // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN 0x00000080 -#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M 0x00000080 -#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S 7 +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S 7 // Field: [6:5] BIAS_RECHARGE_DLY // @@ -256,13 +256,13 @@ // MIN_DLY_X4 Internal. Only to be used through TI provided API. // MIN_DLY_X2 Internal. Only to be used through TI provided API. // MIN_DLY_X1 Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_W 2 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M 0x00000060 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S 5 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X8 0x00000060 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X4 0x00000040 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X2 0x00000020 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X1 0x00000000 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M 0x00000060 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S 5 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X8 0x00000060 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X4 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X2 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X1 0x00000000 // Field: [4:3] TUNE_CAP // @@ -272,20 +272,20 @@ // SHIFT_M70 Internal. Only to be used through TI provided API. // SHIFT_M35 Internal. Only to be used through TI provided API. // SHIFT_0 Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_W 2 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_M 0x00000018 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_S 3 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M108 0x00000018 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M70 0x00000010 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M35 0x00000008 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_0 0x00000000 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_M 0x00000018 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_S 3 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M108 0x00000018 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M70 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M35 0x00000008 +#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_0 0x00000000 // Field: [2:1] SERIES_CAP // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_W 2 -#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M 0x00000006 -#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S 1 +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_W 2 +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M 0x00000006 +#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S 1 // Field: [0] DIV3_BYPASS // @@ -293,11 +293,11 @@ // ENUMs: // HPOSC_2520MHZ Internal. Only to be used through TI provided API. // HPOSC_840MHZ Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS 0x00000001 -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M 0x00000001 -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S 0 -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_2520MHZ 0x00000001 -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_840MHZ 0x00000000 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S 0 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_2520MHZ 0x00000001 +#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_840MHZ 0x00000000 //***************************************************************************** // @@ -307,23 +307,23 @@ // Field: [5] BIAS_DIS // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS 0x00000020 -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_M 0x00000020 -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_S 5 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_M 0x00000020 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_S 5 // Field: [4] PWRDET_EN // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN 0x00000010 -#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_M 0x00000010 -#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_S 4 +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_M 0x00000010 +#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_S 4 // Field: [3:0] BIAS_RES_SET // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_W 4 -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M 0x0000000F -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S 0 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_W 4 +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M 0x0000000F +#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S 0 //***************************************************************************** // @@ -333,30 +333,29 @@ // Field: [7] BIAS_HOLD_MODE_EN // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN 0x00000080 -#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M 0x00000080 -#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S 7 +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M 0x00000080 +#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S 7 // Field: [6] TESTMUX_EN // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN 0x00000040 -#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_M 0x00000040 -#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_S 6 +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_M 0x00000040 +#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_S 6 // Field: [5:4] ATEST_SEL // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_W 2 -#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_M 0x00000030 -#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_S 4 +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_W 2 +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_M 0x00000030 +#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_S 4 // Field: [3:0] CURRMIRR_RATIO // // Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_W 4 -#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M 0x0000000F -#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S 0 - +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_W 4 +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M 0x0000000F +#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S 0 #endif // __ADI_2_REFSYS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi_3_refsys.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi_3_refsys.h index deedeba..2af46aa 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi_3_refsys.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi_3_refsys.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_adi_3_refsys_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_adi_3_refsys_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_ADI_3_REFSYS_H__ #define __HW_ADI_3_REFSYS_H__ @@ -44,37 +44,37 @@ // //***************************************************************************** // Analog Test Control -#define ADI_3_REFSYS_O_SPARE0 0x00000001 +#define ADI_3_REFSYS_O_SPARE0 0x00000001 // Internal -#define ADI_3_REFSYS_O_REFSYSCTL0 0x00000002 +#define ADI_3_REFSYS_O_REFSYSCTL0 0x00000002 // Internal -#define ADI_3_REFSYS_O_REFSYSCTL1 0x00000003 +#define ADI_3_REFSYS_O_REFSYSCTL1 0x00000003 // Internal -#define ADI_3_REFSYS_O_REFSYSCTL2 0x00000004 +#define ADI_3_REFSYS_O_REFSYSCTL2 0x00000004 // Internal -#define ADI_3_REFSYS_O_REFSYSCTL3 0x00000005 +#define ADI_3_REFSYS_O_REFSYSCTL3 0x00000005 // DCDC Control 0 -#define ADI_3_REFSYS_O_DCDCCTL0 0x00000006 +#define ADI_3_REFSYS_O_DCDCCTL0 0x00000006 // DCDC Control 1 -#define ADI_3_REFSYS_O_DCDCCTL1 0x00000007 +#define ADI_3_REFSYS_O_DCDCCTL1 0x00000007 // DCDC Control 2 -#define ADI_3_REFSYS_O_DCDCCTL2 0x00000008 +#define ADI_3_REFSYS_O_DCDCCTL2 0x00000008 // DCDC Control 3 -#define ADI_3_REFSYS_O_DCDCCTL3 0x00000009 +#define ADI_3_REFSYS_O_DCDCCTL3 0x00000009 // Internal -#define ADI_3_REFSYS_O_DCDCCTL4 0x0000000A +#define ADI_3_REFSYS_O_DCDCCTL4 0x0000000A // Internal -#define ADI_3_REFSYS_O_DCDCCTL5 0x0000000B +#define ADI_3_REFSYS_O_DCDCCTL5 0x0000000B //***************************************************************************** // @@ -85,9 +85,9 @@ // // Software should not rely on the value of a reserved. Writing any other value // than the reset value may result in undefined behavior. -#define ADI_3_REFSYS_SPARE0_SPARE0_W 8 -#define ADI_3_REFSYS_SPARE0_SPARE0_M 0x000000FF -#define ADI_3_REFSYS_SPARE0_SPARE0_S 0 +#define ADI_3_REFSYS_SPARE0_SPARE0_W 8 +#define ADI_3_REFSYS_SPARE0_SPARE0_M 0x000000FF +#define ADI_3_REFSYS_SPARE0_SPARE0_S 0 //***************************************************************************** // @@ -107,18 +107,18 @@ // IVREF4U Internal. Only to be used through TI provided API. // IPTAT2U Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_W 8 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_M 0x000000FF -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_S 0 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_BMCOMPOUT 0x00000080 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VTEMP 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VREF0P8V 0x00000020 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBGUNBUFF 0x00000010 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBG 0x00000008 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IREF4U 0x00000004 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IVREF4U 0x00000002 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IPTAT2U 0x00000001 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_NC 0x00000000 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_W 8 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_M 0x000000FF +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_S 0 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_BMCOMPOUT 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VTEMP 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VREF0P8V 0x00000020 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBGUNBUFF 0x00000010 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBG 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IREF4U 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IVREF4U 0x00000002 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IPTAT2U 0x00000001 +#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_NC 0x00000000 //***************************************************************************** // @@ -161,41 +161,41 @@ // POS_6 Internal. Only to be used through TI provided API. // POS_5 Internal. Only to be used through TI provided API. // POS_4 Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_W 5 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M 0x000000F8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S 3 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_27 0x000000F8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_26 0x000000F0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_25 0x000000E8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_24 0x000000E0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 0x000000D8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_30 0x000000D0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_29 0x000000C8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_28 0x000000C0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_19 0x000000B8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_18 0x000000B0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_17 0x000000A8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_16 0x000000A0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_23 0x00000098 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_22 0x00000090 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_21 0x00000088 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_20 0x00000080 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_11 0x00000078 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_10 0x00000070 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_9 0x00000068 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_8 0x00000060 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_15 0x00000058 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_14 0x00000050 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_13 0x00000048 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_12 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_3 0x00000038 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_2 0x00000030 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_1 0x00000028 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_0 0x00000020 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_7 0x00000018 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_6 0x00000010 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_5 0x00000008 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_4 0x00000000 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_W 5 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M 0x000000F8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S 3 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_27 0x000000F8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_26 0x000000F0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_25 0x000000E8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_24 0x000000E0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 0x000000D8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_30 0x000000D0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_29 0x000000C8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_28 0x000000C0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_19 0x000000B8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_18 0x000000B0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_17 0x000000A8 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_16 0x000000A0 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_23 0x00000098 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_22 0x00000090 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_21 0x00000088 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_20 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_11 0x00000078 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_10 0x00000070 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_9 0x00000068 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_8 0x00000060 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_15 0x00000058 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_14 0x00000050 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_13 0x00000048 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_12 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_3 0x00000038 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_2 0x00000030 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_1 0x00000028 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_0 0x00000020 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_7 0x00000018 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_6 0x00000010 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_5 0x00000008 +#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_4 0x00000000 // Field: [2] BATMON_COMP_TEST_EN // @@ -203,11 +203,11 @@ // ENUMs: // EN Internal. Only to be used through TI provided API. // DIS Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN 0x00000004 -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_M 0x00000004 -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_S 2 -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_EN 0x00000004 -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_DIS 0x00000000 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_M 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_S 2 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_EN 0x00000004 +#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_DIS 0x00000000 // Field: [1:0] TESTCTL // @@ -216,12 +216,12 @@ // IPTAT1U Internal. Only to be used through TI provided API. // BMCOMPIN Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_W 2 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_M 0x00000003 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_S 0 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_IPTAT1U 0x00000002 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_BMCOMPIN 0x00000001 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_NC 0x00000000 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_W 2 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_M 0x00000003 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_S 0 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_IPTAT1U 0x00000002 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_BMCOMPIN 0x00000001 +#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_NC 0x00000000 //***************************************************************************** // @@ -231,16 +231,16 @@ // Field: [7:4] TRIM_VREF // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_W 4 -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_M 0x000000F0 -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_S 4 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_W 4 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_M 0x000000F0 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_S 4 // Field: [1:0] TRIM_TSENSE // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_W 2 -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_M 0x00000003 -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_S 0 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_W 2 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_M 0x00000003 +#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_S 0 //***************************************************************************** // @@ -250,9 +250,9 @@ // Field: [7] BOD_BG_TRIM_EN // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN 0x00000080 -#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_M 0x00000080 -#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_S 7 +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_M 0x00000080 +#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_S 7 // Field: [6] VTEMP_EN // @@ -260,18 +260,18 @@ // ENUMs: // EN Internal. Only to be used through TI provided API. // DIS Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_M 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_S 6 -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_EN 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_DIS 0x00000000 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_M 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_S 6 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_EN 0x00000040 +#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_DIS 0x00000000 // Field: [5:0] TRIM_VBG // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W 6 -#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M 0x0000003F -#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S 0 +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W 6 +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M 0x0000003F +#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S 0 //***************************************************************************** // @@ -286,9 +286,9 @@ // 0x0: Default 11mA. // 0x3: Max 15mA. // 0x4: Max 5mA -#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_W 3 -#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_M 0x000000E0 -#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_S 5 +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_W 3 +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_M 0x000000E0 +#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_S 5 // Field: [4:0] VDDR_TRIM // @@ -303,9 +303,9 @@ // 0x05: Typical voltage after trim voltage 1.71V. // 0x15: Max voltage 1.96V. // 0x16: Min voltage 1.47V. -#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_W 5 -#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M 0x0000001F -#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S 0 +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_W 5 +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M 0x0000001F +#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S 0 //***************************************************************************** // @@ -321,9 +321,9 @@ // 0x1: Increase GLDO bias by 1.3x. // 0x2: Increase GLDO bias by 1.6x. // 0x3: Decrease GLDO bias by 0.7x. -#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_W 2 -#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_M 0x000000C0 -#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_S 6 +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_W 2 +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_M 0x000000C0 +#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_S 6 // Field: [5] VDDR_OK_HYST // @@ -331,9 +331,9 @@ // // 0: Hysteresis = 60mV // 1: Hysteresis = 70mV -#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST 0x00000020 -#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_M 0x00000020 -#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_S 5 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST 0x00000020 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_S 5 // Field: [4:0] VDDR_TRIM_SLEEP // @@ -348,9 +348,9 @@ // 0x19: Typical voltage after trim voltage 1.52V. // 0x15: Max voltage 1.96V. // 0x16: Min voltage 1.47V. -#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_W 5 -#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M 0x0000001F -#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S 0 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_W 5 +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M 0x0000001F +#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S 0 //***************************************************************************** // @@ -363,9 +363,9 @@ // // 0: Erroramp Off (Default) // 1: Erroramp On. Turns on GLDO error amp switch. -#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW 0x00000040 -#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_M 0x00000040 -#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_S 6 +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW 0x00000040 +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_M 0x00000040 +#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_S 6 // Field: [5] TEST_VDDR // @@ -375,9 +375,9 @@ // 1: Connected // // Set TESTSEL = 0x0 first before setting this bit. -#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR 0x00000020 -#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_M 0x00000020 -#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_S 5 +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR 0x00000020 +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_S 5 // Field: [4] BIAS_DIS // @@ -385,9 +385,9 @@ // // 0: Dummy bias current on (Default) // 1: Dummy bias current off -#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS 0x00000010 -#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_M 0x00000010 -#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_S 4 +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS 0x00000010 +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_M 0x00000010 +#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_S 4 // Field: [3:0] TESTSEL // @@ -399,14 +399,14 @@ // bus. // ERRAMP_OUT Error amp output voltage connected to test bus. // NC No signal connected to test bus. -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_W 4 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_M 0x0000000F -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_S 0 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_VDDROK 0x00000008 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_IB1U 0x00000004 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_PASSGATE 0x00000002 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_ERRAMP_OUT 0x00000001 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_NC 0x00000000 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_W 4 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_M 0x0000000F +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_S 0 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_VDDROK 0x00000008 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_IB1U 0x00000004 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_PASSGATE 0x00000002 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_ERRAMP_OUT 0x00000001 +#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_NC 0x00000000 //***************************************************************************** // @@ -421,23 +421,23 @@ // Field: [7:6] DEADTIME_TRIM // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_W 2 -#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_M 0x000000C0 -#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_S 6 +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_W 2 +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_M 0x000000C0 +#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_S 6 // Field: [5:3] LOW_EN_SEL // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_W 3 -#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_M 0x00000038 -#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_S 3 +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_W 3 +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_M 0x00000038 +#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_S 3 // Field: [2:0] HIGH_EN_SEL // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_W 3 -#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_M 0x00000007 -#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_S 0 +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_W 3 +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_M 0x00000007 +#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_S 0 //***************************************************************************** // @@ -447,16 +447,16 @@ // Field: [5] TESTN // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL5_TESTN 0x00000020 -#define ADI_3_REFSYS_DCDCCTL5_TESTN_M 0x00000020 -#define ADI_3_REFSYS_DCDCCTL5_TESTN_S 5 +#define ADI_3_REFSYS_DCDCCTL5_TESTN 0x00000020 +#define ADI_3_REFSYS_DCDCCTL5_TESTN_M 0x00000020 +#define ADI_3_REFSYS_DCDCCTL5_TESTN_S 5 // Field: [4] TESTP // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL5_TESTP 0x00000010 -#define ADI_3_REFSYS_DCDCCTL5_TESTP_M 0x00000010 -#define ADI_3_REFSYS_DCDCCTL5_TESTP_S 4 +#define ADI_3_REFSYS_DCDCCTL5_TESTP 0x00000010 +#define ADI_3_REFSYS_DCDCCTL5_TESTP_M 0x00000010 +#define ADI_3_REFSYS_DCDCCTL5_TESTP_S 4 // Field: [3] DITHER_EN // @@ -464,18 +464,17 @@ // ENUMs: // EN Internal. Only to be used through TI provided API. // DIS Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN 0x00000008 -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_M 0x00000008 -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_S 3 -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_EN 0x00000008 -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_DIS 0x00000000 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_M 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_S 3 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_EN 0x00000008 +#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_DIS 0x00000000 // Field: [2:0] IPEAK // // Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL5_IPEAK_W 3 -#define ADI_3_REFSYS_DCDCCTL5_IPEAK_M 0x00000007 -#define ADI_3_REFSYS_DCDCCTL5_IPEAK_S 0 - +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_W 3 +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_M 0x00000007 +#define ADI_3_REFSYS_DCDCCTL5_IPEAK_S 0 #endif // __ADI_3_REFSYS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi_4_aux.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi_4_aux.h index af14ac4..59f3ffb 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi_4_aux.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_adi_4_aux.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_adi_4_aux_h -* Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) -* Revision: 48904 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_adi_4_aux_h + * Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) + * Revision: 48904 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_ADI_4_AUX_H__ #define __HW_ADI_4_AUX_H__ @@ -44,37 +44,37 @@ // //***************************************************************************** // Internal -#define ADI_4_AUX_O_MUX0 0x00000000 +#define ADI_4_AUX_O_MUX0 0x00000000 // Internal -#define ADI_4_AUX_O_MUX1 0x00000001 +#define ADI_4_AUX_O_MUX1 0x00000001 // Internal -#define ADI_4_AUX_O_MUX2 0x00000002 +#define ADI_4_AUX_O_MUX2 0x00000002 // Internal -#define ADI_4_AUX_O_MUX3 0x00000003 +#define ADI_4_AUX_O_MUX3 0x00000003 // Current Source -#define ADI_4_AUX_O_ISRC 0x00000004 +#define ADI_4_AUX_O_ISRC 0x00000004 // Comparator -#define ADI_4_AUX_O_COMP 0x00000005 +#define ADI_4_AUX_O_COMP 0x00000005 // Internal -#define ADI_4_AUX_O_MUX4 0x00000007 +#define ADI_4_AUX_O_MUX4 0x00000007 // ADC Control 0 -#define ADI_4_AUX_O_ADC0 0x00000008 +#define ADI_4_AUX_O_ADC0 0x00000008 // ADC Control 1 -#define ADI_4_AUX_O_ADC1 0x00000009 +#define ADI_4_AUX_O_ADC1 0x00000009 // ADC Reference 0 -#define ADI_4_AUX_O_ADCREF0 0x0000000A +#define ADI_4_AUX_O_ADCREF0 0x0000000A // ADC Reference 1 -#define ADI_4_AUX_O_ADCREF1 0x0000000B +#define ADI_4_AUX_O_ADCREF1 0x0000000B //***************************************************************************** // @@ -90,14 +90,14 @@ // VSS Internal. Only to be used through TI provided API. // DCOUPL Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX0_COMPA_REF_W 4 -#define ADI_4_AUX_MUX0_COMPA_REF_M 0x0000000F -#define ADI_4_AUX_MUX0_COMPA_REF_S 0 -#define ADI_4_AUX_MUX0_COMPA_REF_ADCVREFP 0x00000008 -#define ADI_4_AUX_MUX0_COMPA_REF_VDDS 0x00000004 -#define ADI_4_AUX_MUX0_COMPA_REF_VSS 0x00000002 -#define ADI_4_AUX_MUX0_COMPA_REF_DCOUPL 0x00000001 -#define ADI_4_AUX_MUX0_COMPA_REF_NC 0x00000000 +#define ADI_4_AUX_MUX0_COMPA_REF_W 4 +#define ADI_4_AUX_MUX0_COMPA_REF_M 0x0000000F +#define ADI_4_AUX_MUX0_COMPA_REF_S 0 +#define ADI_4_AUX_MUX0_COMPA_REF_ADCVREFP 0x00000008 +#define ADI_4_AUX_MUX0_COMPA_REF_VDDS 0x00000004 +#define ADI_4_AUX_MUX0_COMPA_REF_VSS 0x00000002 +#define ADI_4_AUX_MUX0_COMPA_REF_DCOUPL 0x00000001 +#define ADI_4_AUX_MUX0_COMPA_REF_NC 0x00000000 //***************************************************************************** // @@ -117,18 +117,18 @@ // AUXIO6 Internal. Only to be used through TI provided API. // AUXIO7 Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX1_COMPA_IN_W 8 -#define ADI_4_AUX_MUX1_COMPA_IN_M 0x000000FF -#define ADI_4_AUX_MUX1_COMPA_IN_S 0 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO0 0x00000080 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO1 0x00000040 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO2 0x00000020 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO3 0x00000010 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO4 0x00000008 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO5 0x00000004 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO6 0x00000002 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO7 0x00000001 -#define ADI_4_AUX_MUX1_COMPA_IN_NC 0x00000000 +#define ADI_4_AUX_MUX1_COMPA_IN_W 8 +#define ADI_4_AUX_MUX1_COMPA_IN_M 0x000000FF +#define ADI_4_AUX_MUX1_COMPA_IN_S 0 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO0 0x00000080 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO1 0x00000040 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO2 0x00000020 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO3 0x00000010 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO4 0x00000008 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO5 0x00000004 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO6 0x00000002 +#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO7 0x00000001 +#define ADI_4_AUX_MUX1_COMPA_IN_NC 0x00000000 //***************************************************************************** // @@ -145,15 +145,15 @@ // ATEST1 Internal. Only to be used through TI provided API. // ATEST0 Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_W 5 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_M 0x000000F8 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_S 3 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VDDS 0x00000080 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VSS 0x00000040 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_DCOUPL 0x00000020 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST1 0x00000010 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST0 0x00000008 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_NC 0x00000000 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_W 5 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_M 0x000000F8 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_S 3 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VDDS 0x00000080 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VSS 0x00000040 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_DCOUPL 0x00000020 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST1 0x00000010 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST0 0x00000008 +#define ADI_4_AUX_MUX2_ADCCOMPB_IN_NC 0x00000000 // Field: [2:0] COMPB_REF // @@ -163,13 +163,13 @@ // VSS Internal. Only to be used through TI provided API. // DCOUPL Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX2_COMPB_REF_W 3 -#define ADI_4_AUX_MUX2_COMPB_REF_M 0x00000007 -#define ADI_4_AUX_MUX2_COMPB_REF_S 0 -#define ADI_4_AUX_MUX2_COMPB_REF_VDDS 0x00000004 -#define ADI_4_AUX_MUX2_COMPB_REF_VSS 0x00000002 -#define ADI_4_AUX_MUX2_COMPB_REF_DCOUPL 0x00000001 -#define ADI_4_AUX_MUX2_COMPB_REF_NC 0x00000000 +#define ADI_4_AUX_MUX2_COMPB_REF_W 3 +#define ADI_4_AUX_MUX2_COMPB_REF_M 0x00000007 +#define ADI_4_AUX_MUX2_COMPB_REF_S 0 +#define ADI_4_AUX_MUX2_COMPB_REF_VDDS 0x00000004 +#define ADI_4_AUX_MUX2_COMPB_REF_VSS 0x00000002 +#define ADI_4_AUX_MUX2_COMPB_REF_DCOUPL 0x00000001 +#define ADI_4_AUX_MUX2_COMPB_REF_NC 0x00000000 //***************************************************************************** // @@ -189,18 +189,18 @@ // AUXIO6 Internal. Only to be used through TI provided API. // AUXIO7 Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_W 8 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_M 0x000000FF -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_S 0 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO0 0x00000080 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO1 0x00000040 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO2 0x00000020 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO3 0x00000010 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO4 0x00000008 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO5 0x00000004 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO6 0x00000002 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO7 0x00000001 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_NC 0x00000000 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_W 8 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_M 0x000000FF +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_S 0 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO0 0x00000080 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO1 0x00000040 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO2 0x00000020 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO3 0x00000010 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO4 0x00000008 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO5 0x00000004 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO6 0x00000002 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO7 0x00000001 +#define ADI_4_AUX_MUX3_ADCCOMPB_IN_NC 0x00000000 //***************************************************************************** // @@ -220,23 +220,23 @@ // 0P5U 0.5 uA // 0P25U 0.25 uA // NC No current connected -#define ADI_4_AUX_ISRC_TRIM_W 6 -#define ADI_4_AUX_ISRC_TRIM_M 0x000000FC -#define ADI_4_AUX_ISRC_TRIM_S 2 -#define ADI_4_AUX_ISRC_TRIM_11P75U 0x00000080 -#define ADI_4_AUX_ISRC_TRIM_4P5U 0x00000040 -#define ADI_4_AUX_ISRC_TRIM_2P0U 0x00000020 -#define ADI_4_AUX_ISRC_TRIM_1P0U 0x00000010 -#define ADI_4_AUX_ISRC_TRIM_0P5U 0x00000008 -#define ADI_4_AUX_ISRC_TRIM_0P25U 0x00000004 -#define ADI_4_AUX_ISRC_TRIM_NC 0x00000000 +#define ADI_4_AUX_ISRC_TRIM_W 6 +#define ADI_4_AUX_ISRC_TRIM_M 0x000000FC +#define ADI_4_AUX_ISRC_TRIM_S 2 +#define ADI_4_AUX_ISRC_TRIM_11P75U 0x00000080 +#define ADI_4_AUX_ISRC_TRIM_4P5U 0x00000040 +#define ADI_4_AUX_ISRC_TRIM_2P0U 0x00000020 +#define ADI_4_AUX_ISRC_TRIM_1P0U 0x00000010 +#define ADI_4_AUX_ISRC_TRIM_0P5U 0x00000008 +#define ADI_4_AUX_ISRC_TRIM_0P25U 0x00000004 +#define ADI_4_AUX_ISRC_TRIM_NC 0x00000000 // Field: [0] EN // // Current source enable -#define ADI_4_AUX_ISRC_EN 0x00000001 -#define ADI_4_AUX_ISRC_EN_M 0x00000001 -#define ADI_4_AUX_ISRC_EN_S 0 +#define ADI_4_AUX_ISRC_EN 0x00000001 +#define ADI_4_AUX_ISRC_EN_M 0x00000001 +#define ADI_4_AUX_ISRC_EN_S 0 //***************************************************************************** // @@ -247,18 +247,18 @@ // // Enables 400kohm resistance from COMPA reference node to ground. Used with // COMPA_REF_CURR_EN to generate voltage reference for cap-sense. -#define ADI_4_AUX_COMP_COMPA_REF_RES_EN 0x00000080 -#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_M 0x00000080 -#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_S 7 +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN 0x00000080 +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_M 0x00000080 +#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_S 7 // Field: [6] COMPA_REF_CURR_EN // // Enables 2uA IPTAT current from ISRC to COMPA reference node. Requires // ISRC.EN = 1. Used with COMPA_REF_RES_EN to generate voltage reference for // cap-sense. -#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN 0x00000040 -#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_M 0x00000040 -#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_S 6 +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN 0x00000040 +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_M 0x00000040 +#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_S 6 // Field: [5:3] COMPB_TRIM // @@ -268,27 +268,27 @@ // DIV3 Divide reference by 3 // DIV2 Divide reference by 2 // DIV1 No reference division -#define ADI_4_AUX_COMP_COMPB_TRIM_W 3 -#define ADI_4_AUX_COMP_COMPB_TRIM_M 0x00000038 -#define ADI_4_AUX_COMP_COMPB_TRIM_S 3 -#define ADI_4_AUX_COMP_COMPB_TRIM_DIV4 0x00000038 -#define ADI_4_AUX_COMP_COMPB_TRIM_DIV3 0x00000018 -#define ADI_4_AUX_COMP_COMPB_TRIM_DIV2 0x00000008 -#define ADI_4_AUX_COMP_COMPB_TRIM_DIV1 0x00000000 +#define ADI_4_AUX_COMP_COMPB_TRIM_W 3 +#define ADI_4_AUX_COMP_COMPB_TRIM_M 0x00000038 +#define ADI_4_AUX_COMP_COMPB_TRIM_S 3 +#define ADI_4_AUX_COMP_COMPB_TRIM_DIV4 0x00000038 +#define ADI_4_AUX_COMP_COMPB_TRIM_DIV3 0x00000018 +#define ADI_4_AUX_COMP_COMPB_TRIM_DIV2 0x00000008 +#define ADI_4_AUX_COMP_COMPB_TRIM_DIV1 0x00000000 // Field: [2] COMPB_EN // // COMPB enable -#define ADI_4_AUX_COMP_COMPB_EN 0x00000004 -#define ADI_4_AUX_COMP_COMPB_EN_M 0x00000004 -#define ADI_4_AUX_COMP_COMPB_EN_S 2 +#define ADI_4_AUX_COMP_COMPB_EN 0x00000004 +#define ADI_4_AUX_COMP_COMPB_EN_M 0x00000004 +#define ADI_4_AUX_COMP_COMPB_EN_S 2 // Field: [0] COMPA_EN // // COMPA enable -#define ADI_4_AUX_COMP_COMPA_EN 0x00000001 -#define ADI_4_AUX_COMP_COMPA_EN_M 0x00000001 -#define ADI_4_AUX_COMP_COMPA_EN_S 0 +#define ADI_4_AUX_COMP_COMPA_EN 0x00000001 +#define ADI_4_AUX_COMP_COMPA_EN_M 0x00000001 +#define ADI_4_AUX_COMP_COMPA_EN_S 0 //***************************************************************************** // @@ -308,18 +308,18 @@ // AUXIO6 Internal. Only to be used through TI provided API. // AUXIO7 Internal. Only to be used through TI provided API. // NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX4_COMPA_REF_W 8 -#define ADI_4_AUX_MUX4_COMPA_REF_M 0x000000FF -#define ADI_4_AUX_MUX4_COMPA_REF_S 0 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO0 0x00000080 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO1 0x00000040 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO2 0x00000020 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO3 0x00000010 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO4 0x00000008 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO5 0x00000004 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO6 0x00000002 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO7 0x00000001 -#define ADI_4_AUX_MUX4_COMPA_REF_NC 0x00000000 +#define ADI_4_AUX_MUX4_COMPA_REF_W 8 +#define ADI_4_AUX_MUX4_COMPA_REF_M 0x000000FF +#define ADI_4_AUX_MUX4_COMPA_REF_S 0 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO0 0x00000080 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO1 0x00000040 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO2 0x00000020 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO3 0x00000010 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO4 0x00000008 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO5 0x00000004 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO6 0x00000002 +#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO7 0x00000001 +#define ADI_4_AUX_MUX4_COMPA_REF_NC 0x00000000 //***************************************************************************** // @@ -345,9 +345,9 @@ // signal. Sampling restarts when the conversion has finished. // Asynchronous mode is useful when it is important to avoid jitter in the // sampling instant of an externally driven signal -#define ADI_4_AUX_ADC0_SMPL_MODE 0x00000080 -#define ADI_4_AUX_ADC0_SMPL_MODE_M 0x00000080 -#define ADI_4_AUX_ADC0_SMPL_MODE_S 7 +#define ADI_4_AUX_ADC0_SMPL_MODE 0x00000080 +#define ADI_4_AUX_ADC0_SMPL_MODE_M 0x00000080 +#define ADI_4_AUX_ADC0_SMPL_MODE_S 7 // Field: [6:3] SMPL_CYCLE_EXP // @@ -368,22 +368,22 @@ // 10P6_US 64x 6 MHz clock periods = 10.6us // 5P3_US 32x 6 MHz clock periods = 5.3us // 2P7_US 16x 6 MHz clock periods = 2.7us -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_W 4 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M 0x00000078 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S 3 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P9_MS 0x00000078 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P46_MS 0x00000070 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P73_MS 0x00000068 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_1P37_MS 0x00000060 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_682_US 0x00000058 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_341_US 0x00000050 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_170_US 0x00000048 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_85P3_US 0x00000040 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_42P6_US 0x00000038 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_21P3_US 0x00000030 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P6_US 0x00000028 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P3_US 0x00000020 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P7_US 0x00000018 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_W 4 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M 0x00000078 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S 3 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P9_MS 0x00000078 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P46_MS 0x00000070 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P73_MS 0x00000068 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_1P37_MS 0x00000060 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_682_US 0x00000058 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_341_US 0x00000050 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_170_US 0x00000048 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_85P3_US 0x00000040 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_42P6_US 0x00000038 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_21P3_US 0x00000030 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P6_US 0x00000028 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P3_US 0x00000020 +#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P7_US 0x00000018 // Field: [1] RESET_N // @@ -392,9 +392,9 @@ // // 0: Reset // 1: Normal operation -#define ADI_4_AUX_ADC0_RESET_N 0x00000002 -#define ADI_4_AUX_ADC0_RESET_N_M 0x00000002 -#define ADI_4_AUX_ADC0_RESET_N_S 1 +#define ADI_4_AUX_ADC0_RESET_N 0x00000002 +#define ADI_4_AUX_ADC0_RESET_N_M 0x00000002 +#define ADI_4_AUX_ADC0_RESET_N_S 1 // Field: [0] EN // @@ -402,9 +402,9 @@ // // 0: Disable // 1: Enable -#define ADI_4_AUX_ADC0_EN 0x00000001 -#define ADI_4_AUX_ADC0_EN_M 0x00000001 -#define ADI_4_AUX_ADC0_EN_S 0 +#define ADI_4_AUX_ADC0_EN 0x00000001 +#define ADI_4_AUX_ADC0_EN_M 0x00000001 +#define ADI_4_AUX_ADC0_EN_S 0 //***************************************************************************** // @@ -414,9 +414,9 @@ // Field: [0] SCALE_DIS // // Internal. Only to be used through TI provided API. -#define ADI_4_AUX_ADC1_SCALE_DIS 0x00000001 -#define ADI_4_AUX_ADC1_SCALE_DIS_M 0x00000001 -#define ADI_4_AUX_ADC1_SCALE_DIS_S 0 +#define ADI_4_AUX_ADC1_SCALE_DIS 0x00000001 +#define ADI_4_AUX_ADC1_SCALE_DIS_M 0x00000001 +#define ADI_4_AUX_ADC1_SCALE_DIS_S 0 //***************************************************************************** // @@ -428,23 +428,23 @@ // Keep ADCREF powered up in IDLE state when ADC0.SMPL_MODE = 0. // // Set to 1 if ADC0.SMPL_CYCLE_EXP is less than 6 (21.3us sampling time) -#define ADI_4_AUX_ADCREF0_REF_ON_IDLE 0x00000040 -#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_M 0x00000040 -#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_S 6 +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE 0x00000040 +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_M 0x00000040 +#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_S 6 // Field: [5] IOMUX // // Internal. Only to be used through TI provided API. -#define ADI_4_AUX_ADCREF0_IOMUX 0x00000020 -#define ADI_4_AUX_ADCREF0_IOMUX_M 0x00000020 -#define ADI_4_AUX_ADCREF0_IOMUX_S 5 +#define ADI_4_AUX_ADCREF0_IOMUX 0x00000020 +#define ADI_4_AUX_ADCREF0_IOMUX_M 0x00000020 +#define ADI_4_AUX_ADCREF0_IOMUX_S 5 // Field: [4] EXT // // Internal. Only to be used through TI provided API. -#define ADI_4_AUX_ADCREF0_EXT 0x00000010 -#define ADI_4_AUX_ADCREF0_EXT_M 0x00000010 -#define ADI_4_AUX_ADCREF0_EXT_S 4 +#define ADI_4_AUX_ADCREF0_EXT 0x00000010 +#define ADI_4_AUX_ADCREF0_EXT_M 0x00000010 +#define ADI_4_AUX_ADCREF0_EXT_S 4 // Field: [3] SRC // @@ -452,9 +452,9 @@ // // 0: Fixed reference = 4.3V // 1: Relative reference = VDDS -#define ADI_4_AUX_ADCREF0_SRC 0x00000008 -#define ADI_4_AUX_ADCREF0_SRC_M 0x00000008 -#define ADI_4_AUX_ADCREF0_SRC_S 3 +#define ADI_4_AUX_ADCREF0_SRC 0x00000008 +#define ADI_4_AUX_ADCREF0_SRC_M 0x00000008 +#define ADI_4_AUX_ADCREF0_SRC_S 3 // Field: [0] EN // @@ -462,9 +462,9 @@ // // 0: ADC reference module powered down // 1: ADC reference module enabled -#define ADI_4_AUX_ADCREF0_EN 0x00000001 -#define ADI_4_AUX_ADCREF0_EN_M 0x00000001 -#define ADI_4_AUX_ADCREF0_EN_S 0 +#define ADI_4_AUX_ADCREF0_EN 0x00000001 +#define ADI_4_AUX_ADCREF0_EN_M 0x00000001 +#define ADI_4_AUX_ADCREF0_EN_S 0 //***************************************************************************** // @@ -482,9 +482,8 @@ // 0x3F - nominal - 0.4% 1.425V // 0x1F - maximum voltage 1.6V // 0x20 - minimum voltage 1.3V -#define ADI_4_AUX_ADCREF1_VTRIM_W 6 -#define ADI_4_AUX_ADCREF1_VTRIM_M 0x0000003F -#define ADI_4_AUX_ADCREF1_VTRIM_S 0 - +#define ADI_4_AUX_ADCREF1_VTRIM_W 6 +#define ADI_4_AUX_ADCREF1_VTRIM_M 0x0000003F +#define ADI_4_AUX_ADCREF1_VTRIM_S 0 #endif // __ADI_4_AUX__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_batmon.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_batmon.h index f09256d..a167301 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_batmon.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_batmon.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aon_batmon_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aon_batmon_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AON_BATMON_H__ #define __HW_AON_BATMON_H__ @@ -44,43 +44,43 @@ // //***************************************************************************** // Internal -#define AON_BATMON_O_CTL 0x00000000 +#define AON_BATMON_O_CTL 0x00000000 // Internal -#define AON_BATMON_O_MEASCFG 0x00000004 +#define AON_BATMON_O_MEASCFG 0x00000004 // Internal -#define AON_BATMON_O_TEMPP0 0x0000000C +#define AON_BATMON_O_TEMPP0 0x0000000C // Internal -#define AON_BATMON_O_TEMPP1 0x00000010 +#define AON_BATMON_O_TEMPP1 0x00000010 // Internal -#define AON_BATMON_O_TEMPP2 0x00000014 +#define AON_BATMON_O_TEMPP2 0x00000014 // Internal -#define AON_BATMON_O_BATMONP0 0x00000018 +#define AON_BATMON_O_BATMONP0 0x00000018 // Internal -#define AON_BATMON_O_BATMONP1 0x0000001C +#define AON_BATMON_O_BATMONP1 0x0000001C // Internal -#define AON_BATMON_O_IOSTRP0 0x00000020 +#define AON_BATMON_O_IOSTRP0 0x00000020 // Internal -#define AON_BATMON_O_FLASHPUMPP0 0x00000024 +#define AON_BATMON_O_FLASHPUMPP0 0x00000024 // Last Measured Battery Voltage -#define AON_BATMON_O_BAT 0x00000028 +#define AON_BATMON_O_BAT 0x00000028 // Battery Update -#define AON_BATMON_O_BATUPD 0x0000002C +#define AON_BATMON_O_BATUPD 0x0000002C // Temperature -#define AON_BATMON_O_TEMP 0x00000030 +#define AON_BATMON_O_TEMP 0x00000030 // Temperature Update -#define AON_BATMON_O_TEMPUPD 0x00000034 +#define AON_BATMON_O_TEMPUPD 0x00000034 //***************************************************************************** // @@ -90,18 +90,18 @@ // Field: [1] CALC_EN // // Internal. Only to be used through TI provided API. -#define AON_BATMON_CTL_CALC_EN 0x00000002 -#define AON_BATMON_CTL_CALC_EN_BITN 1 -#define AON_BATMON_CTL_CALC_EN_M 0x00000002 -#define AON_BATMON_CTL_CALC_EN_S 1 +#define AON_BATMON_CTL_CALC_EN 0x00000002 +#define AON_BATMON_CTL_CALC_EN_BITN 1 +#define AON_BATMON_CTL_CALC_EN_M 0x00000002 +#define AON_BATMON_CTL_CALC_EN_S 1 // Field: [0] MEAS_EN // // Internal. Only to be used through TI provided API. -#define AON_BATMON_CTL_MEAS_EN 0x00000001 -#define AON_BATMON_CTL_MEAS_EN_BITN 0 -#define AON_BATMON_CTL_MEAS_EN_M 0x00000001 -#define AON_BATMON_CTL_MEAS_EN_S 0 +#define AON_BATMON_CTL_MEAS_EN 0x00000001 +#define AON_BATMON_CTL_MEAS_EN_BITN 0 +#define AON_BATMON_CTL_MEAS_EN_M 0x00000001 +#define AON_BATMON_CTL_MEAS_EN_S 0 //***************************************************************************** // @@ -116,13 +116,13 @@ // 16CYC Internal. Only to be used through TI provided API. // 8CYC Internal. Only to be used through TI provided API. // CONT Internal. Only to be used through TI provided API. -#define AON_BATMON_MEASCFG_PER_W 2 -#define AON_BATMON_MEASCFG_PER_M 0x00000003 -#define AON_BATMON_MEASCFG_PER_S 0 -#define AON_BATMON_MEASCFG_PER_32CYC 0x00000003 -#define AON_BATMON_MEASCFG_PER_16CYC 0x00000002 -#define AON_BATMON_MEASCFG_PER_8CYC 0x00000001 -#define AON_BATMON_MEASCFG_PER_CONT 0x00000000 +#define AON_BATMON_MEASCFG_PER_W 2 +#define AON_BATMON_MEASCFG_PER_M 0x00000003 +#define AON_BATMON_MEASCFG_PER_S 0 +#define AON_BATMON_MEASCFG_PER_32CYC 0x00000003 +#define AON_BATMON_MEASCFG_PER_16CYC 0x00000002 +#define AON_BATMON_MEASCFG_PER_8CYC 0x00000001 +#define AON_BATMON_MEASCFG_PER_CONT 0x00000000 //***************************************************************************** // @@ -132,9 +132,9 @@ // Field: [7:0] CFG // // Internal. Only to be used through TI provided API. -#define AON_BATMON_TEMPP0_CFG_W 8 -#define AON_BATMON_TEMPP0_CFG_M 0x000000FF -#define AON_BATMON_TEMPP0_CFG_S 0 +#define AON_BATMON_TEMPP0_CFG_W 8 +#define AON_BATMON_TEMPP0_CFG_M 0x000000FF +#define AON_BATMON_TEMPP0_CFG_S 0 //***************************************************************************** // @@ -144,9 +144,9 @@ // Field: [5:0] CFG // // Internal. Only to be used through TI provided API. -#define AON_BATMON_TEMPP1_CFG_W 6 -#define AON_BATMON_TEMPP1_CFG_M 0x0000003F -#define AON_BATMON_TEMPP1_CFG_S 0 +#define AON_BATMON_TEMPP1_CFG_W 6 +#define AON_BATMON_TEMPP1_CFG_M 0x0000003F +#define AON_BATMON_TEMPP1_CFG_S 0 //***************************************************************************** // @@ -156,9 +156,9 @@ // Field: [4:0] CFG // // Internal. Only to be used through TI provided API. -#define AON_BATMON_TEMPP2_CFG_W 5 -#define AON_BATMON_TEMPP2_CFG_M 0x0000001F -#define AON_BATMON_TEMPP2_CFG_S 0 +#define AON_BATMON_TEMPP2_CFG_W 5 +#define AON_BATMON_TEMPP2_CFG_M 0x0000001F +#define AON_BATMON_TEMPP2_CFG_S 0 //***************************************************************************** // @@ -168,9 +168,9 @@ // Field: [5:0] CFG // // Internal. Only to be used through TI provided API. -#define AON_BATMON_BATMONP0_CFG_W 6 -#define AON_BATMON_BATMONP0_CFG_M 0x0000003F -#define AON_BATMON_BATMONP0_CFG_S 0 +#define AON_BATMON_BATMONP0_CFG_W 6 +#define AON_BATMON_BATMONP0_CFG_M 0x0000003F +#define AON_BATMON_BATMONP0_CFG_S 0 //***************************************************************************** // @@ -180,9 +180,9 @@ // Field: [5:0] CFG // // Internal. Only to be used through TI provided API. -#define AON_BATMON_BATMONP1_CFG_W 6 -#define AON_BATMON_BATMONP1_CFG_M 0x0000003F -#define AON_BATMON_BATMONP1_CFG_S 0 +#define AON_BATMON_BATMONP1_CFG_W 6 +#define AON_BATMON_BATMONP1_CFG_M 0x0000003F +#define AON_BATMON_BATMONP1_CFG_S 0 //***************************************************************************** // @@ -192,16 +192,16 @@ // Field: [5:4] CFG2 // // Internal. Only to be used through TI provided API. -#define AON_BATMON_IOSTRP0_CFG2_W 2 -#define AON_BATMON_IOSTRP0_CFG2_M 0x00000030 -#define AON_BATMON_IOSTRP0_CFG2_S 4 +#define AON_BATMON_IOSTRP0_CFG2_W 2 +#define AON_BATMON_IOSTRP0_CFG2_M 0x00000030 +#define AON_BATMON_IOSTRP0_CFG2_S 4 // Field: [3:0] CFG1 // // Internal. Only to be used through TI provided API. -#define AON_BATMON_IOSTRP0_CFG1_W 4 -#define AON_BATMON_IOSTRP0_CFG1_M 0x0000000F -#define AON_BATMON_IOSTRP0_CFG1_S 0 +#define AON_BATMON_IOSTRP0_CFG1_W 4 +#define AON_BATMON_IOSTRP0_CFG1_M 0x0000000F +#define AON_BATMON_IOSTRP0_CFG1_S 0 //***************************************************************************** // @@ -211,40 +211,40 @@ // Field: [8] FALLB // // Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_FALLB 0x00000100 -#define AON_BATMON_FLASHPUMPP0_FALLB_BITN 8 -#define AON_BATMON_FLASHPUMPP0_FALLB_M 0x00000100 -#define AON_BATMON_FLASHPUMPP0_FALLB_S 8 +#define AON_BATMON_FLASHPUMPP0_FALLB 0x00000100 +#define AON_BATMON_FLASHPUMPP0_FALLB_BITN 8 +#define AON_BATMON_FLASHPUMPP0_FALLB_M 0x00000100 +#define AON_BATMON_FLASHPUMPP0_FALLB_S 8 // Field: [7:6] HIGHLIM // // Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_HIGHLIM_W 2 -#define AON_BATMON_FLASHPUMPP0_HIGHLIM_M 0x000000C0 -#define AON_BATMON_FLASHPUMPP0_HIGHLIM_S 6 +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_W 2 +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_M 0x000000C0 +#define AON_BATMON_FLASHPUMPP0_HIGHLIM_S 6 // Field: [5] LOWLIM // // Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_LOWLIM 0x00000020 -#define AON_BATMON_FLASHPUMPP0_LOWLIM_BITN 5 -#define AON_BATMON_FLASHPUMPP0_LOWLIM_M 0x00000020 -#define AON_BATMON_FLASHPUMPP0_LOWLIM_S 5 +#define AON_BATMON_FLASHPUMPP0_LOWLIM 0x00000020 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_BITN 5 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_M 0x00000020 +#define AON_BATMON_FLASHPUMPP0_LOWLIM_S 5 // Field: [4] OVR // // Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_OVR 0x00000010 -#define AON_BATMON_FLASHPUMPP0_OVR_BITN 4 -#define AON_BATMON_FLASHPUMPP0_OVR_M 0x00000010 -#define AON_BATMON_FLASHPUMPP0_OVR_S 4 +#define AON_BATMON_FLASHPUMPP0_OVR 0x00000010 +#define AON_BATMON_FLASHPUMPP0_OVR_BITN 4 +#define AON_BATMON_FLASHPUMPP0_OVR_M 0x00000010 +#define AON_BATMON_FLASHPUMPP0_OVR_S 4 // Field: [3:0] CFG // // Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_CFG_W 4 -#define AON_BATMON_FLASHPUMPP0_CFG_M 0x0000000F -#define AON_BATMON_FLASHPUMPP0_CFG_S 0 +#define AON_BATMON_FLASHPUMPP0_CFG_W 4 +#define AON_BATMON_FLASHPUMPP0_CFG_M 0x0000000F +#define AON_BATMON_FLASHPUMPP0_CFG_S 0 //***************************************************************************** // @@ -259,9 +259,9 @@ // ... // 0x3: 3V + fractional part // 0x4: 4V + fractional part -#define AON_BATMON_BAT_INT_W 3 -#define AON_BATMON_BAT_INT_M 0x00000700 -#define AON_BATMON_BAT_INT_S 8 +#define AON_BATMON_BAT_INT_W 3 +#define AON_BATMON_BAT_INT_M 0x00000700 +#define AON_BATMON_BAT_INT_S 8 // Field: [7:0] FRAC // @@ -276,9 +276,9 @@ // 0xA0: 1/2 + 1/8 = .625V // ... // 0xFF: Max -#define AON_BATMON_BAT_FRAC_W 8 -#define AON_BATMON_BAT_FRAC_M 0x000000FF -#define AON_BATMON_BAT_FRAC_S 0 +#define AON_BATMON_BAT_FRAC_W 8 +#define AON_BATMON_BAT_FRAC_M 0x000000FF +#define AON_BATMON_BAT_FRAC_S 0 //***************************************************************************** // @@ -292,10 +292,10 @@ // 1: New battery voltage is present. // // Write 1 to clear the status. -#define AON_BATMON_BATUPD_STAT 0x00000001 -#define AON_BATMON_BATUPD_STAT_BITN 0 -#define AON_BATMON_BATUPD_STAT_M 0x00000001 -#define AON_BATMON_BATUPD_STAT_S 0 +#define AON_BATMON_BATUPD_STAT 0x00000001 +#define AON_BATMON_BATUPD_STAT_BITN 0 +#define AON_BATMON_BATUPD_STAT_M 0x00000001 +#define AON_BATMON_BATUPD_STAT_S 0 //***************************************************************************** // @@ -315,9 +315,9 @@ // 0x1B: 27C // 0x55: 85C // 0xFF: Max value -#define AON_BATMON_TEMP_INT_W 9 -#define AON_BATMON_TEMP_INT_M 0x0001FF00 -#define AON_BATMON_TEMP_INT_S 8 +#define AON_BATMON_TEMP_INT_W 9 +#define AON_BATMON_TEMP_INT_M 0x0001FF00 +#define AON_BATMON_TEMP_INT_S 8 //***************************************************************************** // @@ -331,10 +331,9 @@ // 1: New temperature is present. // // Write 1 to clear the status. -#define AON_BATMON_TEMPUPD_STAT 0x00000001 -#define AON_BATMON_TEMPUPD_STAT_BITN 0 -#define AON_BATMON_TEMPUPD_STAT_M 0x00000001 -#define AON_BATMON_TEMPUPD_STAT_S 0 - +#define AON_BATMON_TEMPUPD_STAT 0x00000001 +#define AON_BATMON_TEMPUPD_STAT_BITN 0 +#define AON_BATMON_TEMPUPD_STAT_M 0x00000001 +#define AON_BATMON_TEMPUPD_STAT_S 0 #endif // __AON_BATMON__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_event.h index 2896b81..1ea66b9 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_event.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_event.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aon_event_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aon_event_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AON_EVENT_H__ #define __HW_AON_EVENT_H__ @@ -44,16 +44,16 @@ // //***************************************************************************** // Wake-up Selector For MCU -#define AON_EVENT_O_MCUWUSEL 0x00000000 +#define AON_EVENT_O_MCUWUSEL 0x00000000 // Wake-up Selector For AUX -#define AON_EVENT_O_AUXWUSEL 0x00000004 +#define AON_EVENT_O_AUXWUSEL 0x00000004 // Event Selector For MCU Event Fabric -#define AON_EVENT_O_EVTOMCUSEL 0x00000008 +#define AON_EVENT_O_EVTOMCUSEL 0x00000008 // RTC Capture Event Selector For AON_RTC -#define AON_EVENT_O_RTCSEL 0x0000000C +#define AON_EVENT_O_RTCSEL 0x0000000C //***************************************************************************** // @@ -133,65 +133,65 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_MCUWUSEL_WU3_EV_W 6 -#define AON_EVENT_MCUWUSEL_WU3_EV_M 0x3F000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_S 24 -#define AON_EVENT_MCUWUSEL_WU3_EV_NONE 0x3F000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC_N 0x38000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC 0x37000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_VOLT 0x36000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP 0x35000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER1_EV 0x34000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER0_EV 0x33000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TDC_DONE 0x32000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_ADC_DONE 0x31000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB 0x30000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPA 0x2F000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV2 0x2E000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV1 0x2D000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV0 0x2C000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_JTAG 0x2B000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_UPD 0x2A000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_COMB_DLY 0x29000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2_DLY 0x28000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1_DLY 0x27000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0_DLY 0x26000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2 0x25000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1 0x24000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0 0x23000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD 0x20000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD31 0x1F000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD30 0x1E000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD29 0x1D000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD28 0x1C000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD27 0x1B000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD26 0x1A000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD25 0x19000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD24 0x18000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD23 0x17000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD22 0x16000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD21 0x15000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD20 0x14000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD19 0x13000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD18 0x12000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD17 0x11000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD16 0x10000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD15 0x0F000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD14 0x0E000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD13 0x0D000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD12 0x0C000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD11 0x0B000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD10 0x0A000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD9 0x09000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD8 0x08000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD7 0x07000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD6 0x06000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD5 0x05000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD4 0x04000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD3 0x03000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD2 0x02000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD1 0x01000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD0 0x00000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU3_EV_M 0x3F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_S 24 +#define AON_EVENT_MCUWUSEL_WU3_EV_NONE 0x3F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC_N 0x38000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC 0x37000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_VOLT 0x36000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP 0x35000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER1_EV 0x34000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER0_EV 0x33000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TDC_DONE 0x32000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_ADC_DONE 0x31000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB 0x30000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPA 0x2F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV2 0x2E000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV1 0x2D000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV0 0x2C000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_JTAG 0x2B000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_UPD 0x2A000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_COMB_DLY 0x29000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2_DLY 0x28000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1_DLY 0x27000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0_DLY 0x26000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2 0x25000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1 0x24000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0 0x23000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD 0x20000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD31 0x1F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD30 0x1E000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD29 0x1D000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD28 0x1C000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD27 0x1B000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD26 0x1A000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD25 0x19000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD24 0x18000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD23 0x17000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD22 0x16000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD21 0x15000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD20 0x14000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD19 0x13000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD18 0x12000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD17 0x11000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD16 0x10000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD15 0x0F000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD14 0x0E000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD13 0x0D000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD12 0x0C000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD11 0x0B000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD10 0x0A000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD9 0x09000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD8 0x08000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD7 0x07000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD6 0x06000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD5 0x05000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD4 0x04000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD3 0x03000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD2 0x02000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD1 0x01000000 +#define AON_EVENT_MCUWUSEL_WU3_EV_PAD0 0x00000000 // Field: [21:16] WU2_EV // @@ -266,65 +266,65 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_MCUWUSEL_WU2_EV_W 6 -#define AON_EVENT_MCUWUSEL_WU2_EV_M 0x003F0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_S 16 -#define AON_EVENT_MCUWUSEL_WU2_EV_NONE 0x003F0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000 -#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_VOLT 0x00360000 -#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP 0x00350000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB 0x00300000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPA 0x002F0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV2 0x002E0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV1 0x002D0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV0 0x002C0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_JTAG 0x002B0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_UPD 0x002A0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2 0x00250000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1 0x00240000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0 0x00230000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD 0x00200000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD31 0x001F0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD30 0x001E0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD29 0x001D0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD28 0x001C0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD27 0x001B0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD26 0x001A0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD25 0x00190000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD24 0x00180000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD23 0x00170000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD22 0x00160000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD21 0x00150000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD20 0x00140000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD19 0x00130000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD18 0x00120000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD17 0x00110000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD16 0x00100000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD15 0x000F0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD14 0x000E0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD13 0x000D0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD12 0x000C0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD11 0x000B0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD10 0x000A0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD9 0x00090000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD8 0x00080000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD7 0x00070000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD6 0x00060000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD5 0x00050000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD4 0x00040000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD3 0x00030000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD2 0x00020000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD1 0x00010000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD0 0x00000000 +#define AON_EVENT_MCUWUSEL_WU2_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU2_EV_M 0x003F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_S 16 +#define AON_EVENT_MCUWUSEL_WU2_EV_NONE 0x003F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_JTAG 0x002B0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2 0x00250000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1 0x00240000 +#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0 0x00230000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD 0x00200000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD31 0x001F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD30 0x001E0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD29 0x001D0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD28 0x001C0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD27 0x001B0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD26 0x001A0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD25 0x00190000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD24 0x00180000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD23 0x00170000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD22 0x00160000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD21 0x00150000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD20 0x00140000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD19 0x00130000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD18 0x00120000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD17 0x00110000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD16 0x00100000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD15 0x000F0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD14 0x000E0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD13 0x000D0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD12 0x000C0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD11 0x000B0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD10 0x000A0000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD9 0x00090000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD8 0x00080000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD7 0x00070000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD6 0x00060000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD5 0x00050000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD4 0x00040000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD3 0x00030000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD2 0x00020000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD1 0x00010000 +#define AON_EVENT_MCUWUSEL_WU2_EV_PAD0 0x00000000 // Field: [13:8] WU1_EV // @@ -399,65 +399,65 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_MCUWUSEL_WU1_EV_W 6 -#define AON_EVENT_MCUWUSEL_WU1_EV_M 0x00003F00 -#define AON_EVENT_MCUWUSEL_WU1_EV_S 8 -#define AON_EVENT_MCUWUSEL_WU1_EV_NONE 0x00003F00 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700 -#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_VOLT 0x00003600 -#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP 0x00003500 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB 0x00003000 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPA 0x00002F00 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV2 0x00002E00 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV1 0x00002D00 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV0 0x00002C00 -#define AON_EVENT_MCUWUSEL_WU1_EV_JTAG 0x00002B00 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_UPD 0x00002A00 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2 0x00002500 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1 0x00002400 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0 0x00002300 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD 0x00002000 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD31 0x00001F00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD30 0x00001E00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD29 0x00001D00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD28 0x00001C00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD27 0x00001B00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD26 0x00001A00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD25 0x00001900 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD24 0x00001800 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD23 0x00001700 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD22 0x00001600 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD21 0x00001500 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD20 0x00001400 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD19 0x00001300 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD18 0x00001200 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD17 0x00001100 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD16 0x00001000 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD15 0x00000F00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD14 0x00000E00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD13 0x00000D00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD12 0x00000C00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD11 0x00000B00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD10 0x00000A00 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD9 0x00000900 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD8 0x00000800 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD7 0x00000700 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD6 0x00000600 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD5 0x00000500 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD4 0x00000400 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD3 0x00000300 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD2 0x00000200 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD1 0x00000100 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD0 0x00000000 +#define AON_EVENT_MCUWUSEL_WU1_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU1_EV_M 0x00003F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_S 8 +#define AON_EVENT_MCUWUSEL_WU1_EV_NONE 0x00003F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_MCUWUSEL_WU1_EV_JTAG 0x00002B00 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2 0x00002500 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1 0x00002400 +#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0 0x00002300 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD 0x00002000 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD31 0x00001F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD30 0x00001E00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD29 0x00001D00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD28 0x00001C00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD27 0x00001B00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD26 0x00001A00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD25 0x00001900 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD24 0x00001800 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD23 0x00001700 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD22 0x00001600 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD21 0x00001500 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD20 0x00001400 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD19 0x00001300 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD18 0x00001200 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD17 0x00001100 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD16 0x00001000 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD15 0x00000F00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD14 0x00000E00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD13 0x00000D00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD12 0x00000C00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD11 0x00000B00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD10 0x00000A00 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD9 0x00000900 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD8 0x00000800 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD7 0x00000700 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD6 0x00000600 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD5 0x00000500 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD4 0x00000400 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD3 0x00000300 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD2 0x00000200 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD1 0x00000100 +#define AON_EVENT_MCUWUSEL_WU1_EV_PAD0 0x00000000 // Field: [5:0] WU0_EV // @@ -532,65 +532,65 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_MCUWUSEL_WU0_EV_W 6 -#define AON_EVENT_MCUWUSEL_WU0_EV_M 0x0000003F -#define AON_EVENT_MCUWUSEL_WU0_EV_S 0 -#define AON_EVENT_MCUWUSEL_WU0_EV_NONE 0x0000003F -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037 -#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_VOLT 0x00000036 -#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP 0x00000035 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB 0x00000030 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPA 0x0000002F -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV2 0x0000002E -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV1 0x0000002D -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV0 0x0000002C -#define AON_EVENT_MCUWUSEL_WU0_EV_JTAG 0x0000002B -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_UPD 0x0000002A -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2 0x00000025 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1 0x00000024 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0 0x00000023 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD 0x00000020 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD31 0x0000001F -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD30 0x0000001E -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD29 0x0000001D -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD28 0x0000001C -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD27 0x0000001B -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD26 0x0000001A -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD25 0x00000019 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD24 0x00000018 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD23 0x00000017 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD22 0x00000016 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD21 0x00000015 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD20 0x00000014 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD19 0x00000013 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD18 0x00000012 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD17 0x00000011 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD16 0x00000010 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD15 0x0000000F -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD14 0x0000000E -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD13 0x0000000D -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD12 0x0000000C -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD11 0x0000000B -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD10 0x0000000A -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD9 0x00000009 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD8 0x00000008 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD7 0x00000007 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD6 0x00000006 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD5 0x00000005 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD4 0x00000004 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD3 0x00000003 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD2 0x00000002 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD1 0x00000001 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD0 0x00000000 +#define AON_EVENT_MCUWUSEL_WU0_EV_W 6 +#define AON_EVENT_MCUWUSEL_WU0_EV_M 0x0000003F +#define AON_EVENT_MCUWUSEL_WU0_EV_S 0 +#define AON_EVENT_MCUWUSEL_WU0_EV_NONE 0x0000003F +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_MCUWUSEL_WU0_EV_JTAG 0x0000002B +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_UPD 0x0000002A +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2 0x00000025 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1 0x00000024 +#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0 0x00000023 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD 0x00000020 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD31 0x0000001F +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD30 0x0000001E +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD29 0x0000001D +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD28 0x0000001C +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD27 0x0000001B +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD26 0x0000001A +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD25 0x00000019 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD24 0x00000018 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD23 0x00000017 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD22 0x00000016 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD21 0x00000015 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD20 0x00000014 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD19 0x00000013 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD18 0x00000012 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD17 0x00000011 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD16 0x00000010 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD15 0x0000000F +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD14 0x0000000E +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD13 0x0000000D +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD12 0x0000000C +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD11 0x0000000B +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD10 0x0000000A +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD9 0x00000009 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD8 0x00000008 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD7 0x00000007 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD6 0x00000006 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD5 0x00000005 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD4 0x00000004 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD3 0x00000003 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD2 0x00000002 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD1 0x00000001 +#define AON_EVENT_MCUWUSEL_WU0_EV_PAD0 0x00000000 //***************************************************************************** // @@ -670,65 +670,65 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_AUXWUSEL_WU2_EV_W 6 -#define AON_EVENT_AUXWUSEL_WU2_EV_M 0x003F0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_S 16 -#define AON_EVENT_AUXWUSEL_WU2_EV_NONE 0x003F0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000 -#define AON_EVENT_AUXWUSEL_WU2_EV_BATMON_VOLT 0x00360000 -#define AON_EVENT_AUXWUSEL_WU2_EV_BATMON_TEMP 0x00350000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB 0x00300000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPA 0x002F0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV2 0x002E0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV1 0x002D0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV0 0x002C0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_JTAG 0x002B0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_UPD 0x002A0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH2 0x00250000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH1 0x00240000 -#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH0 0x00230000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD 0x00200000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD31 0x001F0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD30 0x001E0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD29 0x001D0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD28 0x001C0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD27 0x001B0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD26 0x001A0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD25 0x00190000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD24 0x00180000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD23 0x00170000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD22 0x00160000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD21 0x00150000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD20 0x00140000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD19 0x00130000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD18 0x00120000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD17 0x00110000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD16 0x00100000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD15 0x000F0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD14 0x000E0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD13 0x000D0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD12 0x000C0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD11 0x000B0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD10 0x000A0000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD9 0x00090000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD8 0x00080000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD7 0x00070000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD6 0x00060000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD5 0x00050000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD4 0x00040000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD3 0x00030000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD2 0x00020000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD1 0x00010000 -#define AON_EVENT_AUXWUSEL_WU2_EV_PAD0 0x00000000 +#define AON_EVENT_AUXWUSEL_WU2_EV_W 6 +#define AON_EVENT_AUXWUSEL_WU2_EV_M 0x003F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_S 16 +#define AON_EVENT_AUXWUSEL_WU2_EV_NONE 0x003F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_AUXWUSEL_WU2_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_AUXWUSEL_WU2_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_JTAG 0x002B0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH2 0x00250000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH1 0x00240000 +#define AON_EVENT_AUXWUSEL_WU2_EV_RTC_CH0 0x00230000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD 0x00200000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD31 0x001F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD30 0x001E0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD29 0x001D0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD28 0x001C0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD27 0x001B0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD26 0x001A0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD25 0x00190000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD24 0x00180000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD23 0x00170000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD22 0x00160000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD21 0x00150000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD20 0x00140000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD19 0x00130000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD18 0x00120000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD17 0x00110000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD16 0x00100000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD15 0x000F0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD14 0x000E0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD13 0x000D0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD12 0x000C0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD11 0x000B0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD10 0x000A0000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD9 0x00090000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD8 0x00080000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD7 0x00070000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD6 0x00060000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD5 0x00050000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD4 0x00040000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD3 0x00030000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD2 0x00020000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD1 0x00010000 +#define AON_EVENT_AUXWUSEL_WU2_EV_PAD0 0x00000000 // Field: [13:8] WU1_EV // @@ -803,65 +803,65 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_AUXWUSEL_WU1_EV_W 6 -#define AON_EVENT_AUXWUSEL_WU1_EV_M 0x00003F00 -#define AON_EVENT_AUXWUSEL_WU1_EV_S 8 -#define AON_EVENT_AUXWUSEL_WU1_EV_NONE 0x00003F00 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700 -#define AON_EVENT_AUXWUSEL_WU1_EV_BATMON_VOLT 0x00003600 -#define AON_EVENT_AUXWUSEL_WU1_EV_BATMON_TEMP 0x00003500 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB 0x00003000 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPA 0x00002F00 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV2 0x00002E00 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV1 0x00002D00 -#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV0 0x00002C00 -#define AON_EVENT_AUXWUSEL_WU1_EV_JTAG 0x00002B00 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_UPD 0x00002A00 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH2 0x00002500 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH1 0x00002400 -#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH0 0x00002300 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD 0x00002000 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD31 0x00001F00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD30 0x00001E00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD29 0x00001D00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD28 0x00001C00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD27 0x00001B00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD26 0x00001A00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD25 0x00001900 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD24 0x00001800 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD23 0x00001700 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD22 0x00001600 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD21 0x00001500 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD20 0x00001400 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD19 0x00001300 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD18 0x00001200 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD17 0x00001100 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD16 0x00001000 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD15 0x00000F00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD14 0x00000E00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD13 0x00000D00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD12 0x00000C00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD11 0x00000B00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD10 0x00000A00 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD9 0x00000900 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD8 0x00000800 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD7 0x00000700 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD6 0x00000600 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD5 0x00000500 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD4 0x00000400 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD3 0x00000300 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD2 0x00000200 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD1 0x00000100 -#define AON_EVENT_AUXWUSEL_WU1_EV_PAD0 0x00000000 +#define AON_EVENT_AUXWUSEL_WU1_EV_W 6 +#define AON_EVENT_AUXWUSEL_WU1_EV_M 0x00003F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_S 8 +#define AON_EVENT_AUXWUSEL_WU1_EV_NONE 0x00003F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_AUXWUSEL_WU1_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_AUXWUSEL_WU1_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_AUXWUSEL_WU1_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_AUXWUSEL_WU1_EV_JTAG 0x00002B00 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH2 0x00002500 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH1 0x00002400 +#define AON_EVENT_AUXWUSEL_WU1_EV_RTC_CH0 0x00002300 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD 0x00002000 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD31 0x00001F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD30 0x00001E00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD29 0x00001D00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD28 0x00001C00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD27 0x00001B00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD26 0x00001A00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD25 0x00001900 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD24 0x00001800 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD23 0x00001700 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD22 0x00001600 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD21 0x00001500 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD20 0x00001400 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD19 0x00001300 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD18 0x00001200 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD17 0x00001100 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD16 0x00001000 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD15 0x00000F00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD14 0x00000E00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD13 0x00000D00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD12 0x00000C00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD11 0x00000B00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD10 0x00000A00 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD9 0x00000900 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD8 0x00000800 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD7 0x00000700 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD6 0x00000600 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD5 0x00000500 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD4 0x00000400 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD3 0x00000300 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD2 0x00000200 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD1 0x00000100 +#define AON_EVENT_AUXWUSEL_WU1_EV_PAD0 0x00000000 // Field: [5:0] WU0_EV // @@ -936,65 +936,65 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_AUXWUSEL_WU0_EV_W 6 -#define AON_EVENT_AUXWUSEL_WU0_EV_M 0x0000003F -#define AON_EVENT_AUXWUSEL_WU0_EV_S 0 -#define AON_EVENT_AUXWUSEL_WU0_EV_NONE 0x0000003F -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038 -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037 -#define AON_EVENT_AUXWUSEL_WU0_EV_BATMON_VOLT 0x00000036 -#define AON_EVENT_AUXWUSEL_WU0_EV_BATMON_TEMP 0x00000035 -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034 -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033 -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032 -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031 -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB 0x00000030 -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPA 0x0000002F -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV2 0x0000002E -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV1 0x0000002D -#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV0 0x0000002C -#define AON_EVENT_AUXWUSEL_WU0_EV_JTAG 0x0000002B -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_UPD 0x0000002A -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029 -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028 -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027 -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026 -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH2 0x00000025 -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH1 0x00000024 -#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH0 0x00000023 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD 0x00000020 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD31 0x0000001F -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD30 0x0000001E -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD29 0x0000001D -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD28 0x0000001C -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD27 0x0000001B -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD26 0x0000001A -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD25 0x00000019 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD24 0x00000018 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD23 0x00000017 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD22 0x00000016 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD21 0x00000015 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD20 0x00000014 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD19 0x00000013 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD18 0x00000012 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD17 0x00000011 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD16 0x00000010 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD15 0x0000000F -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD14 0x0000000E -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD13 0x0000000D -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD12 0x0000000C -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD11 0x0000000B -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD10 0x0000000A -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD9 0x00000009 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD8 0x00000008 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD7 0x00000007 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD6 0x00000006 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD5 0x00000005 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD4 0x00000004 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD3 0x00000003 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD2 0x00000002 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD1 0x00000001 -#define AON_EVENT_AUXWUSEL_WU0_EV_PAD0 0x00000000 +#define AON_EVENT_AUXWUSEL_WU0_EV_W 6 +#define AON_EVENT_AUXWUSEL_WU0_EV_M 0x0000003F +#define AON_EVENT_AUXWUSEL_WU0_EV_S 0 +#define AON_EVENT_AUXWUSEL_WU0_EV_NONE 0x0000003F +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_AUXWUSEL_WU0_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_AUXWUSEL_WU0_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_AUXWUSEL_WU0_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_AUXWUSEL_WU0_EV_JTAG 0x0000002B +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_UPD 0x0000002A +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH2 0x00000025 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH1 0x00000024 +#define AON_EVENT_AUXWUSEL_WU0_EV_RTC_CH0 0x00000023 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD 0x00000020 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD31 0x0000001F +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD30 0x0000001E +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD29 0x0000001D +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD28 0x0000001C +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD27 0x0000001B +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD26 0x0000001A +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD25 0x00000019 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD24 0x00000018 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD23 0x00000017 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD22 0x00000016 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD21 0x00000015 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD20 0x00000014 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD19 0x00000013 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD18 0x00000012 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD17 0x00000011 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD16 0x00000010 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD15 0x0000000F +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD14 0x0000000E +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD13 0x0000000D +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD12 0x0000000C +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD11 0x0000000B +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD10 0x0000000A +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD9 0x00000009 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD8 0x00000008 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD7 0x00000007 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD6 0x00000006 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD5 0x00000005 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD4 0x00000004 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD3 0x00000003 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD2 0x00000002 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD1 0x00000001 +#define AON_EVENT_AUXWUSEL_WU0_EV_PAD0 0x00000000 //***************************************************************************** // @@ -1072,65 +1072,65 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_W 6 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M 0x003F0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S 16 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_NONE 0x003F0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC_N 0x00380000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC 0x00370000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_VOLT 0x00360000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP 0x00350000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER1_EV 0x00340000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER0_EV 0x00330000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TDC_DONE 0x00320000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_ADC_DONE 0x00310000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB 0x00300000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPA 0x002F0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV2 0x002E0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV1 0x002D0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV0 0x002C0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_JTAG 0x002B0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_UPD 0x002A0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_COMB_DLY 0x00290000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2_DLY 0x00280000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1_DLY 0x00270000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0_DLY 0x00260000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2 0x00250000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1 0x00240000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0 0x00230000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD 0x00200000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD31 0x001F0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD30 0x001E0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD29 0x001D0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD28 0x001C0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD27 0x001B0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD26 0x001A0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD25 0x00190000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD24 0x00180000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD23 0x00170000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD22 0x00160000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD21 0x00150000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD20 0x00140000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD19 0x00130000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD18 0x00120000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD17 0x00110000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD16 0x00100000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD15 0x000F0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD14 0x000E0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD13 0x000D0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD12 0x000C0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD11 0x000B0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD10 0x000A0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD9 0x00090000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD8 0x00080000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD7 0x00070000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD6 0x00060000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD5 0x00050000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD4 0x00040000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD3 0x00030000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD2 0x00020000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD1 0x00010000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD0 0x00000000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M 0x003F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S 16 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_NONE 0x003F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC_N 0x00380000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC 0x00370000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_VOLT 0x00360000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP 0x00350000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER1_EV 0x00340000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER0_EV 0x00330000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TDC_DONE 0x00320000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_ADC_DONE 0x00310000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB 0x00300000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPA 0x002F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV2 0x002E0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV1 0x002D0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV0 0x002C0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_JTAG 0x002B0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_UPD 0x002A0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_COMB_DLY 0x00290000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2_DLY 0x00280000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1_DLY 0x00270000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0_DLY 0x00260000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2 0x00250000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1 0x00240000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0 0x00230000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD 0x00200000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD31 0x001F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD30 0x001E0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD29 0x001D0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD28 0x001C0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD27 0x001B0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD26 0x001A0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD25 0x00190000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD24 0x00180000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD23 0x00170000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD22 0x00160000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD21 0x00150000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD20 0x00140000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD19 0x00130000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD18 0x00120000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD17 0x00110000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD16 0x00100000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD15 0x000F0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD14 0x000E0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD13 0x000D0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD12 0x000C0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD11 0x000B0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD10 0x000A0000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD9 0x00090000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD8 0x00080000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD7 0x00070000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD6 0x00060000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD5 0x00050000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD4 0x00040000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD3 0x00030000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD2 0x00020000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD1 0x00010000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD0 0x00000000 // Field: [13:8] AON_PROG1_EV // @@ -1203,65 +1203,65 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_W 6 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M 0x00003F00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S 8 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_NONE 0x00003F00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC_N 0x00003800 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC 0x00003700 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_VOLT 0x00003600 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP 0x00003500 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER1_EV 0x00003400 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER0_EV 0x00003300 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TDC_DONE 0x00003200 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_ADC_DONE 0x00003100 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB 0x00003000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPA 0x00002F00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV2 0x00002E00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV1 0x00002D00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV0 0x00002C00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_JTAG 0x00002B00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_UPD 0x00002A00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_COMB_DLY 0x00002900 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2_DLY 0x00002800 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1_DLY 0x00002700 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0_DLY 0x00002600 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2 0x00002500 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1 0x00002400 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0 0x00002300 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD 0x00002000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD31 0x00001F00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD30 0x00001E00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD29 0x00001D00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD28 0x00001C00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD27 0x00001B00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD26 0x00001A00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD25 0x00001900 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD24 0x00001800 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD23 0x00001700 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD22 0x00001600 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD21 0x00001500 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD20 0x00001400 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD19 0x00001300 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD18 0x00001200 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD17 0x00001100 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD16 0x00001000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD15 0x00000F00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD14 0x00000E00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD13 0x00000D00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD12 0x00000C00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD11 0x00000B00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD10 0x00000A00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD9 0x00000900 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD8 0x00000800 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD7 0x00000700 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD6 0x00000600 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD5 0x00000500 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD4 0x00000400 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD3 0x00000300 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD2 0x00000200 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD1 0x00000100 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD0 0x00000000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M 0x00003F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S 8 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_NONE 0x00003F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC_N 0x00003800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC 0x00003700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_VOLT 0x00003600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP 0x00003500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER1_EV 0x00003400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER0_EV 0x00003300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TDC_DONE 0x00003200 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_ADC_DONE 0x00003100 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB 0x00003000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPA 0x00002F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV2 0x00002E00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV1 0x00002D00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV0 0x00002C00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_JTAG 0x00002B00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_UPD 0x00002A00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_COMB_DLY 0x00002900 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2_DLY 0x00002800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1_DLY 0x00002700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0_DLY 0x00002600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2 0x00002500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1 0x00002400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0 0x00002300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD 0x00002000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD31 0x00001F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD30 0x00001E00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD29 0x00001D00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD28 0x00001C00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD27 0x00001B00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD26 0x00001A00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD25 0x00001900 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD24 0x00001800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD23 0x00001700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD22 0x00001600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD21 0x00001500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD20 0x00001400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD19 0x00001300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD18 0x00001200 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD17 0x00001100 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD16 0x00001000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD15 0x00000F00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD14 0x00000E00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD13 0x00000D00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD12 0x00000C00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD11 0x00000B00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD10 0x00000A00 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD9 0x00000900 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD8 0x00000800 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD7 0x00000700 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD6 0x00000600 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD5 0x00000500 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD4 0x00000400 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD3 0x00000300 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD2 0x00000200 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD1 0x00000100 +#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD0 0x00000000 // Field: [5:0] AON_PROG0_EV // @@ -1334,65 +1334,65 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_W 6 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M 0x0000003F -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S 0 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_NONE 0x0000003F -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC_N 0x00000038 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC 0x00000037 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_VOLT 0x00000036 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP 0x00000035 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER1_EV 0x00000034 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER0_EV 0x00000033 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TDC_DONE 0x00000032 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_ADC_DONE 0x00000031 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB 0x00000030 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPA 0x0000002F -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV2 0x0000002E -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV1 0x0000002D -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV0 0x0000002C -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_JTAG 0x0000002B -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_UPD 0x0000002A -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_COMB_DLY 0x00000029 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2_DLY 0x00000028 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1_DLY 0x00000027 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0_DLY 0x00000026 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2 0x00000025 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1 0x00000024 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0 0x00000023 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD 0x00000020 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD31 0x0000001F -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD30 0x0000001E -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD29 0x0000001D -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD28 0x0000001C -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD27 0x0000001B -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD26 0x0000001A -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD25 0x00000019 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD24 0x00000018 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD23 0x00000017 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD22 0x00000016 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD21 0x00000015 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD20 0x00000014 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD19 0x00000013 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD18 0x00000012 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD17 0x00000011 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD16 0x00000010 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD15 0x0000000F -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD14 0x0000000E -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD13 0x0000000D -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD12 0x0000000C -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD11 0x0000000B -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD10 0x0000000A -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD9 0x00000009 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD8 0x00000008 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD7 0x00000007 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD6 0x00000006 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD5 0x00000005 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD4 0x00000004 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD3 0x00000003 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD2 0x00000002 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD1 0x00000001 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD0 0x00000000 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_W 6 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M 0x0000003F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S 0 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_NONE 0x0000003F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_JTAG 0x0000002B +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_UPD 0x0000002A +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2 0x00000025 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1 0x00000024 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0 0x00000023 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD 0x00000020 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD31 0x0000001F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD30 0x0000001E +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD29 0x0000001D +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD28 0x0000001C +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD27 0x0000001B +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD26 0x0000001A +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD25 0x00000019 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD24 0x00000018 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD23 0x00000017 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD22 0x00000016 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD21 0x00000015 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD20 0x00000014 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD19 0x00000013 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD18 0x00000012 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD17 0x00000011 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD16 0x00000010 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD15 0x0000000F +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD14 0x0000000E +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD13 0x0000000D +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD12 0x0000000C +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD11 0x0000000B +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD10 0x0000000A +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD9 0x00000009 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD8 0x00000008 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD7 0x00000007 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD6 0x00000006 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD5 0x00000005 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD4 0x00000004 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD3 0x00000003 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD2 0x00000002 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD1 0x00000001 +#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD0 0x00000000 //***************************************************************************** // @@ -1469,65 +1469,64 @@ // PAD2 Edge detect on PAD2 // PAD1 Edge detect on PAD1 // PAD0 Edge detect on PAD0 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_W 6 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M 0x0000003F -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S 0 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_NONE 0x0000003F -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC_N 0x00000038 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC 0x00000037 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_VOLT 0x00000036 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP 0x00000035 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER1_EV 0x00000034 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER0_EV 0x00000033 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TDC_DONE 0x00000032 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_ADC_DONE 0x00000031 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB 0x00000030 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPA 0x0000002F -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV2 0x0000002E -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV1 0x0000002D -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV0 0x0000002C -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_JTAG 0x0000002B -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_UPD 0x0000002A -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_COMB_DLY 0x00000029 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2_DLY 0x00000028 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1_DLY 0x00000027 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0_DLY 0x00000026 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2 0x00000025 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1 0x00000024 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0 0x00000023 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD 0x00000020 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD31 0x0000001F -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD30 0x0000001E -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD29 0x0000001D -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD28 0x0000001C -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD27 0x0000001B -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD26 0x0000001A -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD25 0x00000019 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD24 0x00000018 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD23 0x00000017 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD22 0x00000016 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD21 0x00000015 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD20 0x00000014 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD19 0x00000013 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD18 0x00000012 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD17 0x00000011 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD16 0x00000010 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD15 0x0000000F -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD14 0x0000000E -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD13 0x0000000D -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD12 0x0000000C -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD11 0x0000000B -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD10 0x0000000A -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD9 0x00000009 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD8 0x00000008 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD7 0x00000007 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD6 0x00000006 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD5 0x00000005 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD4 0x00000004 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD3 0x00000003 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD2 0x00000002 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD1 0x00000001 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD0 0x00000000 - +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_W 6 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M 0x0000003F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S 0 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_NONE 0x0000003F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC_N 0x00000038 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC 0x00000037 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_VOLT 0x00000036 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP 0x00000035 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER1_EV 0x00000034 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER0_EV 0x00000033 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TDC_DONE 0x00000032 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_ADC_DONE 0x00000031 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB 0x00000030 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPA 0x0000002F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV2 0x0000002E +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV1 0x0000002D +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV0 0x0000002C +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_JTAG 0x0000002B +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_UPD 0x0000002A +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_COMB_DLY 0x00000029 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2_DLY 0x00000028 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1_DLY 0x00000027 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0_DLY 0x00000026 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2 0x00000025 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1 0x00000024 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0 0x00000023 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD 0x00000020 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD31 0x0000001F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD30 0x0000001E +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD29 0x0000001D +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD28 0x0000001C +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD27 0x0000001B +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD26 0x0000001A +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD25 0x00000019 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD24 0x00000018 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD23 0x00000017 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD22 0x00000016 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD21 0x00000015 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD20 0x00000014 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD19 0x00000013 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD18 0x00000012 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD17 0x00000011 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD16 0x00000010 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD15 0x0000000F +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD14 0x0000000E +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD13 0x0000000D +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD12 0x0000000C +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD11 0x0000000B +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD10 0x0000000A +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD9 0x00000009 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD8 0x00000008 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD7 0x00000007 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD6 0x00000006 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD5 0x00000005 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD4 0x00000004 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD3 0x00000003 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD2 0x00000002 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD1 0x00000001 +#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD0 0x00000000 #endif // __AON_EVENT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_ioc.h index 98ecbed..115c4f0 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_ioc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_ioc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aon_ioc_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aon_ioc_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AON_IOC_H__ #define __HW_AON_IOC_H__ @@ -44,19 +44,19 @@ // //***************************************************************************** // Internal -#define AON_IOC_O_IOSTRMIN 0x00000000 +#define AON_IOC_O_IOSTRMIN 0x00000000 // Internal -#define AON_IOC_O_IOSTRMED 0x00000004 +#define AON_IOC_O_IOSTRMED 0x00000004 // Internal -#define AON_IOC_O_IOSTRMAX 0x00000008 +#define AON_IOC_O_IOSTRMAX 0x00000008 // IO Latch Control -#define AON_IOC_O_IOCLATCH 0x0000000C +#define AON_IOC_O_IOCLATCH 0x0000000C // SCLK_LF External Output Control -#define AON_IOC_O_CLK32KCTL 0x00000010 +#define AON_IOC_O_CLK32KCTL 0x00000010 //***************************************************************************** // @@ -66,9 +66,9 @@ // Field: [2:0] GRAY_CODE // // Internal. Only to be used through TI provided API. -#define AON_IOC_IOSTRMIN_GRAY_CODE_W 3 -#define AON_IOC_IOSTRMIN_GRAY_CODE_M 0x00000007 -#define AON_IOC_IOSTRMIN_GRAY_CODE_S 0 +#define AON_IOC_IOSTRMIN_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMIN_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMIN_GRAY_CODE_S 0 //***************************************************************************** // @@ -78,9 +78,9 @@ // Field: [2:0] GRAY_CODE // // Internal. Only to be used through TI provided API. -#define AON_IOC_IOSTRMED_GRAY_CODE_W 3 -#define AON_IOC_IOSTRMED_GRAY_CODE_M 0x00000007 -#define AON_IOC_IOSTRMED_GRAY_CODE_S 0 +#define AON_IOC_IOSTRMED_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMED_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMED_GRAY_CODE_S 0 //***************************************************************************** // @@ -90,9 +90,9 @@ // Field: [2:0] GRAY_CODE // // Internal. Only to be used through TI provided API. -#define AON_IOC_IOSTRMAX_GRAY_CODE_W 3 -#define AON_IOC_IOSTRMAX_GRAY_CODE_M 0x00000007 -#define AON_IOC_IOSTRMAX_GRAY_CODE_S 0 +#define AON_IOC_IOSTRMAX_GRAY_CODE_W 3 +#define AON_IOC_IOSTRMAX_GRAY_CODE_M 0x00000007 +#define AON_IOC_IOSTRMAX_GRAY_CODE_S 0 //***************************************************************************** // @@ -115,12 +115,12 @@ // the IO pin is frozen by latches and kept even // if GPIO module or a peripheral module is turned // off -#define AON_IOC_IOCLATCH_EN 0x00000001 -#define AON_IOC_IOCLATCH_EN_BITN 0 -#define AON_IOC_IOCLATCH_EN_M 0x00000001 -#define AON_IOC_IOCLATCH_EN_S 0 -#define AON_IOC_IOCLATCH_EN_TRANSP 0x00000001 -#define AON_IOC_IOCLATCH_EN_STATIC 0x00000000 +#define AON_IOC_IOCLATCH_EN 0x00000001 +#define AON_IOC_IOCLATCH_EN_BITN 0 +#define AON_IOC_IOCLATCH_EN_M 0x00000001 +#define AON_IOC_IOCLATCH_EN_S 0 +#define AON_IOC_IOCLATCH_EN_TRANSP 0x00000001 +#define AON_IOC_IOCLATCH_EN_STATIC 0x00000000 //***************************************************************************** // @@ -132,10 +132,9 @@ // 0: Output enable active. SCLK_LF output on IO pin that has PORT_ID (e.g. // IOC:IOCFG0.PORT_ID) set to AON_CLK32K. // 1: Output enable not active -#define AON_IOC_CLK32KCTL_OE_N 0x00000001 -#define AON_IOC_CLK32KCTL_OE_N_BITN 0 -#define AON_IOC_CLK32KCTL_OE_N_M 0x00000001 -#define AON_IOC_CLK32KCTL_OE_N_S 0 - +#define AON_IOC_CLK32KCTL_OE_N 0x00000001 +#define AON_IOC_CLK32KCTL_OE_N_BITN 0 +#define AON_IOC_CLK32KCTL_OE_N_M 0x00000001 +#define AON_IOC_CLK32KCTL_OE_N_S 0 #endif // __AON_IOC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_rtc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_rtc.h index 521504d..e413a43 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_rtc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_rtc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aon_rtc_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aon_rtc_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AON_RTC_H__ #define __HW_AON_RTC_H__ @@ -44,40 +44,40 @@ // //***************************************************************************** // Control -#define AON_RTC_O_CTL 0x00000000 +#define AON_RTC_O_CTL 0x00000000 // Event Flags, RTC Status -#define AON_RTC_O_EVFLAGS 0x00000004 +#define AON_RTC_O_EVFLAGS 0x00000004 // Second Counter Value, Integer Part -#define AON_RTC_O_SEC 0x00000008 +#define AON_RTC_O_SEC 0x00000008 // Second Counter Value, Fractional Part -#define AON_RTC_O_SUBSEC 0x0000000C +#define AON_RTC_O_SUBSEC 0x0000000C // Subseconds Increment -#define AON_RTC_O_SUBSECINC 0x00000010 +#define AON_RTC_O_SUBSECINC 0x00000010 // Channel Configuration -#define AON_RTC_O_CHCTL 0x00000014 +#define AON_RTC_O_CHCTL 0x00000014 // Channel 0 Compare Value -#define AON_RTC_O_CH0CMP 0x00000018 +#define AON_RTC_O_CH0CMP 0x00000018 // Channel 1 Compare Value -#define AON_RTC_O_CH1CMP 0x0000001C +#define AON_RTC_O_CH1CMP 0x0000001C // Channel 2 Compare Value -#define AON_RTC_O_CH2CMP 0x00000020 +#define AON_RTC_O_CH2CMP 0x00000020 // Channel 2 Compare Value Auto-increment -#define AON_RTC_O_CH2CMPINC 0x00000024 +#define AON_RTC_O_CH2CMPINC 0x00000024 // Channel 1 Capture Value -#define AON_RTC_O_CH1CAPT 0x00000028 +#define AON_RTC_O_CH1CAPT 0x00000028 // AON Synchronization -#define AON_RTC_O_SYNC 0x0000002C +#define AON_RTC_O_SYNC 0x0000002C //***************************************************************************** // @@ -92,13 +92,13 @@ // CH1 Use Channel 1 delayed event in combined event // CH0 Use Channel 0 delayed event in combined event // NONE No event is selected for combined event. -#define AON_RTC_CTL_COMB_EV_MASK_W 3 -#define AON_RTC_CTL_COMB_EV_MASK_M 0x00070000 -#define AON_RTC_CTL_COMB_EV_MASK_S 16 -#define AON_RTC_CTL_COMB_EV_MASK_CH2 0x00040000 -#define AON_RTC_CTL_COMB_EV_MASK_CH1 0x00020000 -#define AON_RTC_CTL_COMB_EV_MASK_CH0 0x00010000 -#define AON_RTC_CTL_COMB_EV_MASK_NONE 0x00000000 +#define AON_RTC_CTL_COMB_EV_MASK_W 3 +#define AON_RTC_CTL_COMB_EV_MASK_M 0x00070000 +#define AON_RTC_CTL_COMB_EV_MASK_S 16 +#define AON_RTC_CTL_COMB_EV_MASK_CH2 0x00040000 +#define AON_RTC_CTL_COMB_EV_MASK_CH1 0x00020000 +#define AON_RTC_CTL_COMB_EV_MASK_CH0 0x00010000 +#define AON_RTC_CTL_COMB_EV_MASK_NONE 0x00000000 // Field: [11:8] EV_DELAY // @@ -119,23 +119,23 @@ // D2 Delay by 2 clock cycles // D1 Delay by 1 clock cycles // D0 No delay on delayed event -#define AON_RTC_CTL_EV_DELAY_W 4 -#define AON_RTC_CTL_EV_DELAY_M 0x00000F00 -#define AON_RTC_CTL_EV_DELAY_S 8 -#define AON_RTC_CTL_EV_DELAY_D144 0x00000D00 -#define AON_RTC_CTL_EV_DELAY_D128 0x00000C00 -#define AON_RTC_CTL_EV_DELAY_D112 0x00000B00 -#define AON_RTC_CTL_EV_DELAY_D96 0x00000A00 -#define AON_RTC_CTL_EV_DELAY_D80 0x00000900 -#define AON_RTC_CTL_EV_DELAY_D64 0x00000800 -#define AON_RTC_CTL_EV_DELAY_D48 0x00000700 -#define AON_RTC_CTL_EV_DELAY_D32 0x00000600 -#define AON_RTC_CTL_EV_DELAY_D16 0x00000500 -#define AON_RTC_CTL_EV_DELAY_D8 0x00000400 -#define AON_RTC_CTL_EV_DELAY_D4 0x00000300 -#define AON_RTC_CTL_EV_DELAY_D2 0x00000200 -#define AON_RTC_CTL_EV_DELAY_D1 0x00000100 -#define AON_RTC_CTL_EV_DELAY_D0 0x00000000 +#define AON_RTC_CTL_EV_DELAY_W 4 +#define AON_RTC_CTL_EV_DELAY_M 0x00000F00 +#define AON_RTC_CTL_EV_DELAY_S 8 +#define AON_RTC_CTL_EV_DELAY_D144 0x00000D00 +#define AON_RTC_CTL_EV_DELAY_D128 0x00000C00 +#define AON_RTC_CTL_EV_DELAY_D112 0x00000B00 +#define AON_RTC_CTL_EV_DELAY_D96 0x00000A00 +#define AON_RTC_CTL_EV_DELAY_D80 0x00000900 +#define AON_RTC_CTL_EV_DELAY_D64 0x00000800 +#define AON_RTC_CTL_EV_DELAY_D48 0x00000700 +#define AON_RTC_CTL_EV_DELAY_D32 0x00000600 +#define AON_RTC_CTL_EV_DELAY_D16 0x00000500 +#define AON_RTC_CTL_EV_DELAY_D8 0x00000400 +#define AON_RTC_CTL_EV_DELAY_D4 0x00000300 +#define AON_RTC_CTL_EV_DELAY_D2 0x00000200 +#define AON_RTC_CTL_EV_DELAY_D1 0x00000100 +#define AON_RTC_CTL_EV_DELAY_D0 0x00000000 // Field: [7] RESET // @@ -144,10 +144,10 @@ // Writing 1 to this bit will reset the RTC counter. // // This bit is cleared when reset takes effect -#define AON_RTC_CTL_RESET 0x00000080 -#define AON_RTC_CTL_RESET_BITN 7 -#define AON_RTC_CTL_RESET_M 0x00000080 -#define AON_RTC_CTL_RESET_S 7 +#define AON_RTC_CTL_RESET 0x00000080 +#define AON_RTC_CTL_RESET_BITN 7 +#define AON_RTC_CTL_RESET_M 0x00000080 +#define AON_RTC_CTL_RESET_S 7 // Field: [2] RTC_4KHZ_EN // @@ -156,10 +156,10 @@ // // 0: RTC_4KHZ signal is forced to 0 // 1: RTC_4KHZ is enabled ( provied that RTC is enabled EN) -#define AON_RTC_CTL_RTC_4KHZ_EN 0x00000004 -#define AON_RTC_CTL_RTC_4KHZ_EN_BITN 2 -#define AON_RTC_CTL_RTC_4KHZ_EN_M 0x00000004 -#define AON_RTC_CTL_RTC_4KHZ_EN_S 2 +#define AON_RTC_CTL_RTC_4KHZ_EN 0x00000004 +#define AON_RTC_CTL_RTC_4KHZ_EN_BITN 2 +#define AON_RTC_CTL_RTC_4KHZ_EN_M 0x00000004 +#define AON_RTC_CTL_RTC_4KHZ_EN_S 2 // Field: [1] RTC_UPD_EN // @@ -168,10 +168,10 @@ // // 0: RTC_UPD signal is forced to 0 // 1: RTC_UPD signal is toggling @16 kHz -#define AON_RTC_CTL_RTC_UPD_EN 0x00000002 -#define AON_RTC_CTL_RTC_UPD_EN_BITN 1 -#define AON_RTC_CTL_RTC_UPD_EN_M 0x00000002 -#define AON_RTC_CTL_RTC_UPD_EN_S 1 +#define AON_RTC_CTL_RTC_UPD_EN 0x00000002 +#define AON_RTC_CTL_RTC_UPD_EN_BITN 1 +#define AON_RTC_CTL_RTC_UPD_EN_M 0x00000002 +#define AON_RTC_CTL_RTC_UPD_EN_S 1 // Field: [0] EN // @@ -179,10 +179,10 @@ // // 0: Halted (frozen) // 1: Running -#define AON_RTC_CTL_EN 0x00000001 -#define AON_RTC_CTL_EN_BITN 0 -#define AON_RTC_CTL_EN_M 0x00000001 -#define AON_RTC_CTL_EN_S 0 +#define AON_RTC_CTL_EN 0x00000001 +#define AON_RTC_CTL_EN_BITN 0 +#define AON_RTC_CTL_EN_M 0x00000001 +#define AON_RTC_CTL_EN_S 0 //***************************************************************************** // @@ -203,10 +203,10 @@ // // AUX_SCE can read the flag through AUX_WUC:WUEVFLAGS.AON_RTC_CH2 and clear it // using AUX_WUC:WUEVCLR.AON_RTC_CH2. -#define AON_RTC_EVFLAGS_CH2 0x00010000 -#define AON_RTC_EVFLAGS_CH2_BITN 16 -#define AON_RTC_EVFLAGS_CH2_M 0x00010000 -#define AON_RTC_EVFLAGS_CH2_S 16 +#define AON_RTC_EVFLAGS_CH2 0x00010000 +#define AON_RTC_EVFLAGS_CH2_BITN 16 +#define AON_RTC_EVFLAGS_CH2_M 0x00010000 +#define AON_RTC_EVFLAGS_CH2_S 16 // Field: [8] CH1 // @@ -221,10 +221,10 @@ // // Writing 1 clears this flag. Note that a new event can not occur on this // channel in first 2 SCLK_LF cycles after a clearance. -#define AON_RTC_EVFLAGS_CH1 0x00000100 -#define AON_RTC_EVFLAGS_CH1_BITN 8 -#define AON_RTC_EVFLAGS_CH1_M 0x00000100 -#define AON_RTC_EVFLAGS_CH1_S 8 +#define AON_RTC_EVFLAGS_CH1 0x00000100 +#define AON_RTC_EVFLAGS_CH1_BITN 8 +#define AON_RTC_EVFLAGS_CH1_M 0x00000100 +#define AON_RTC_EVFLAGS_CH1_S 8 // Field: [0] CH0 // @@ -237,10 +237,10 @@ // // Writing 1 clears this flag. Note that a new event can not occur on this // channel in first 2 SCLK_LF cycles after a clearance. -#define AON_RTC_EVFLAGS_CH0 0x00000001 -#define AON_RTC_EVFLAGS_CH0_BITN 0 -#define AON_RTC_EVFLAGS_CH0_M 0x00000001 -#define AON_RTC_EVFLAGS_CH0_S 0 +#define AON_RTC_EVFLAGS_CH0 0x00000001 +#define AON_RTC_EVFLAGS_CH0_BITN 0 +#define AON_RTC_EVFLAGS_CH0_M 0x00000001 +#define AON_RTC_EVFLAGS_CH0_S 0 //***************************************************************************** // @@ -254,9 +254,9 @@ // When reading this register the content of SUBSEC.VALUE is simultaneously // latched. A consistent reading of the combined Real Time Clock can be // obtained by first reading this register, then reading SUBSEC register. -#define AON_RTC_SEC_VALUE_W 32 -#define AON_RTC_SEC_VALUE_M 0xFFFFFFFF -#define AON_RTC_SEC_VALUE_S 0 +#define AON_RTC_SEC_VALUE_W 32 +#define AON_RTC_SEC_VALUE_M 0xFFFFFFFF +#define AON_RTC_SEC_VALUE_S 0 //***************************************************************************** // @@ -273,9 +273,9 @@ // - 0x4000_0000 = 0.25 sec // - 0x8000_0000 = 0.5 sec // - 0xC000_0000 = 0.75 sec -#define AON_RTC_SUBSEC_VALUE_W 32 -#define AON_RTC_SUBSEC_VALUE_M 0xFFFFFFFF -#define AON_RTC_SUBSEC_VALUE_S 0 +#define AON_RTC_SUBSEC_VALUE_W 32 +#define AON_RTC_SUBSEC_VALUE_M 0xFFFFFFFF +#define AON_RTC_SUBSEC_VALUE_S 0 //***************************************************************************** // @@ -301,9 +301,9 @@ // NOTE: This register is read only. Modification of the register value must be // done using registers AUX_WUC:RTCSUBSECINC1 , AUX_WUC:RTCSUBSECINC0 and // AUX_WUC:RTCSUBSECINCCTL -#define AON_RTC_SUBSECINC_VALUEINC_W 24 -#define AON_RTC_SUBSECINC_VALUEINC_M 0x00FFFFFF -#define AON_RTC_SUBSECINC_VALUEINC_S 0 +#define AON_RTC_SUBSECINC_VALUEINC_W 24 +#define AON_RTC_SUBSECINC_VALUEINC_M 0x00FFFFFF +#define AON_RTC_SUBSECINC_VALUEINC_S 0 //***************************************************************************** // @@ -313,10 +313,10 @@ // Field: [18] CH2_CONT_EN // // Set to enable continuous operation of Channel 2 -#define AON_RTC_CHCTL_CH2_CONT_EN 0x00040000 -#define AON_RTC_CHCTL_CH2_CONT_EN_BITN 18 -#define AON_RTC_CHCTL_CH2_CONT_EN_M 0x00040000 -#define AON_RTC_CHCTL_CH2_CONT_EN_S 18 +#define AON_RTC_CHCTL_CH2_CONT_EN 0x00040000 +#define AON_RTC_CHCTL_CH2_CONT_EN_BITN 18 +#define AON_RTC_CHCTL_CH2_CONT_EN_M 0x00040000 +#define AON_RTC_CHCTL_CH2_CONT_EN_S 18 // Field: [16] CH2_EN // @@ -324,10 +324,10 @@ // // 0: Disable RTC Channel 2 // 1: Enable RTC Channel 2 -#define AON_RTC_CHCTL_CH2_EN 0x00010000 -#define AON_RTC_CHCTL_CH2_EN_BITN 16 -#define AON_RTC_CHCTL_CH2_EN_M 0x00010000 -#define AON_RTC_CHCTL_CH2_EN_S 16 +#define AON_RTC_CHCTL_CH2_EN 0x00010000 +#define AON_RTC_CHCTL_CH2_EN_BITN 16 +#define AON_RTC_CHCTL_CH2_EN_M 0x00010000 +#define AON_RTC_CHCTL_CH2_EN_S 16 // Field: [9] CH1_CAPT_EN // @@ -335,10 +335,10 @@ // // 0: Compare mode (default) // 1: Capture mode -#define AON_RTC_CHCTL_CH1_CAPT_EN 0x00000200 -#define AON_RTC_CHCTL_CH1_CAPT_EN_BITN 9 -#define AON_RTC_CHCTL_CH1_CAPT_EN_M 0x00000200 -#define AON_RTC_CHCTL_CH1_CAPT_EN_S 9 +#define AON_RTC_CHCTL_CH1_CAPT_EN 0x00000200 +#define AON_RTC_CHCTL_CH1_CAPT_EN_BITN 9 +#define AON_RTC_CHCTL_CH1_CAPT_EN_M 0x00000200 +#define AON_RTC_CHCTL_CH1_CAPT_EN_S 9 // Field: [8] CH1_EN // @@ -346,10 +346,10 @@ // // 0: Disable RTC Channel 1 // 1: Enable RTC Channel 1 -#define AON_RTC_CHCTL_CH1_EN 0x00000100 -#define AON_RTC_CHCTL_CH1_EN_BITN 8 -#define AON_RTC_CHCTL_CH1_EN_M 0x00000100 -#define AON_RTC_CHCTL_CH1_EN_S 8 +#define AON_RTC_CHCTL_CH1_EN 0x00000100 +#define AON_RTC_CHCTL_CH1_EN_BITN 8 +#define AON_RTC_CHCTL_CH1_EN_M 0x00000100 +#define AON_RTC_CHCTL_CH1_EN_S 8 // Field: [0] CH0_EN // @@ -357,10 +357,10 @@ // // 0: Disable RTC Channel 0 // 1: Enable RTC Channel 0 -#define AON_RTC_CHCTL_CH0_EN 0x00000001 -#define AON_RTC_CHCTL_CH0_EN_BITN 0 -#define AON_RTC_CHCTL_CH0_EN_M 0x00000001 -#define AON_RTC_CHCTL_CH0_EN_S 0 +#define AON_RTC_CHCTL_CH0_EN 0x00000001 +#define AON_RTC_CHCTL_CH0_EN_BITN 0 +#define AON_RTC_CHCTL_CH0_EN_M 0x00000001 +#define AON_RTC_CHCTL_CH0_EN_S 0 //***************************************************************************** // @@ -388,9 +388,9 @@ // // *) It can take up to 2 SCLK_LF clock cycles before event occurs due to // synchronization. -#define AON_RTC_CH0CMP_VALUE_W 32 -#define AON_RTC_CH0CMP_VALUE_M 0xFFFFFFFF -#define AON_RTC_CH0CMP_VALUE_S 0 +#define AON_RTC_CH0CMP_VALUE_W 32 +#define AON_RTC_CH0CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH0CMP_VALUE_S 0 //***************************************************************************** // @@ -418,9 +418,9 @@ // // *) It can take up to 2 SCLK_LF clock cycles before event occurs due to // synchronization. -#define AON_RTC_CH1CMP_VALUE_W 32 -#define AON_RTC_CH1CMP_VALUE_M 0xFFFFFFFF -#define AON_RTC_CH1CMP_VALUE_S 0 +#define AON_RTC_CH1CMP_VALUE_W 32 +#define AON_RTC_CH1CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH1CMP_VALUE_S 0 //***************************************************************************** // @@ -448,9 +448,9 @@ // // *) It can take up to 2 SCLK_LF clock cycles before event occurs due to // synchronization. -#define AON_RTC_CH2CMP_VALUE_W 32 -#define AON_RTC_CH2CMP_VALUE_M 0xFFFFFFFF -#define AON_RTC_CH2CMP_VALUE_S 0 +#define AON_RTC_CH2CMP_VALUE_W 32 +#define AON_RTC_CH2CMP_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH2CMP_VALUE_S 0 //***************************************************************************** // @@ -461,9 +461,9 @@ // // If CHCTL.CH2_CONT_EN is set, this value is added to CH2CMP.VALUE on every // channel 2 compare event. -#define AON_RTC_CH2CMPINC_VALUE_W 32 -#define AON_RTC_CH2CMPINC_VALUE_M 0xFFFFFFFF -#define AON_RTC_CH2CMPINC_VALUE_S 0 +#define AON_RTC_CH2CMPINC_VALUE_W 32 +#define AON_RTC_CH2CMPINC_VALUE_M 0xFFFFFFFF +#define AON_RTC_CH2CMPINC_VALUE_S 0 //***************************************************************************** // @@ -473,16 +473,16 @@ // Field: [31:16] SEC // // Value of SEC.VALUE bits 15:0 at capture time. -#define AON_RTC_CH1CAPT_SEC_W 16 -#define AON_RTC_CH1CAPT_SEC_M 0xFFFF0000 -#define AON_RTC_CH1CAPT_SEC_S 16 +#define AON_RTC_CH1CAPT_SEC_W 16 +#define AON_RTC_CH1CAPT_SEC_M 0xFFFF0000 +#define AON_RTC_CH1CAPT_SEC_S 16 // Field: [15:0] SUBSEC // // Value of SUBSEC.VALUE bits 31:16 at capture time. -#define AON_RTC_CH1CAPT_SUBSEC_W 16 -#define AON_RTC_CH1CAPT_SUBSEC_M 0x0000FFFF -#define AON_RTC_CH1CAPT_SUBSEC_S 0 +#define AON_RTC_CH1CAPT_SUBSEC_W 16 +#define AON_RTC_CH1CAPT_SUBSEC_M 0x0000FFFF +#define AON_RTC_CH1CAPT_SUBSEC_S 0 //***************************************************************************** // @@ -499,10 +499,9 @@ // waking up from sleep // Failure to do so may result in reading AON values from prior to going to // sleep -#define AON_RTC_SYNC_WBUSY 0x00000001 -#define AON_RTC_SYNC_WBUSY_BITN 0 -#define AON_RTC_SYNC_WBUSY_M 0x00000001 -#define AON_RTC_SYNC_WBUSY_S 0 - +#define AON_RTC_SYNC_WBUSY 0x00000001 +#define AON_RTC_SYNC_WBUSY_BITN 0 +#define AON_RTC_SYNC_WBUSY_M 0x00000001 +#define AON_RTC_SYNC_WBUSY_S 0 #endif // __AON_RTC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_sysctl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_sysctl.h index c8352c1..ff92824 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_sysctl.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_sysctl.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aon_sysctl_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aon_sysctl_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AON_SYSCTL_H__ #define __HW_AON_SYSCTL_H__ @@ -44,13 +44,13 @@ // //***************************************************************************** // Power Management -#define AON_SYSCTL_O_PWRCTL 0x00000000 +#define AON_SYSCTL_O_PWRCTL 0x00000000 // Reset Management -#define AON_SYSCTL_O_RESETCTL 0x00000004 +#define AON_SYSCTL_O_RESETCTL 0x00000004 // Sleep Mode -#define AON_SYSCTL_O_SLEEPCTL 0x00000008 +#define AON_SYSCTL_O_SLEEPCTL 0x00000008 //***************************************************************************** // @@ -63,10 +63,10 @@ // // 0: Use GLDO for regulation of VDDRin active mode. // 1: Use DCDC for regulation of VDDRin active mode. -#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE 0x00000004 -#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_BITN 2 -#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M 0x00000004 -#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_S 2 +#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE 0x00000004 +#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_BITN 2 +#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_M 0x00000004 +#define AON_SYSCTL_PWRCTL_DCDC_ACTIVE_S 2 // Field: [1] EXT_REG_MODE // @@ -74,10 +74,10 @@ // // 0: DCDC/GLDO are generating VDDR // 1: DCDC/GLDO are bypassed, external regulator supplies VDDR -#define AON_SYSCTL_PWRCTL_EXT_REG_MODE 0x00000002 -#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_BITN 1 -#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_M 0x00000002 -#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_S 1 +#define AON_SYSCTL_PWRCTL_EXT_REG_MODE 0x00000002 +#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_BITN 1 +#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_M 0x00000002 +#define AON_SYSCTL_PWRCTL_EXT_REG_MODE_S 1 // Field: [0] DCDC_EN // @@ -87,10 +87,10 @@ // 1: Use DCDC for recharge of VDDR // // Note: This bitfield should be set to the same as DCDC_ACTIVE -#define AON_SYSCTL_PWRCTL_DCDC_EN 0x00000001 -#define AON_SYSCTL_PWRCTL_DCDC_EN_BITN 0 -#define AON_SYSCTL_PWRCTL_DCDC_EN_M 0x00000001 -#define AON_SYSCTL_PWRCTL_DCDC_EN_S 0 +#define AON_SYSCTL_PWRCTL_DCDC_EN 0x00000001 +#define AON_SYSCTL_PWRCTL_DCDC_EN_BITN 0 +#define AON_SYSCTL_PWRCTL_DCDC_EN_M 0x00000001 +#define AON_SYSCTL_PWRCTL_DCDC_EN_S 0 //***************************************************************************** // @@ -104,42 +104,42 @@ // // 0: No effect // 1: Generate system reset. Appears as SYSRESET in RESET_SRC. -#define AON_SYSCTL_RESETCTL_SYSRESET 0x80000000 -#define AON_SYSCTL_RESETCTL_SYSRESET_BITN 31 -#define AON_SYSCTL_RESETCTL_SYSRESET_M 0x80000000 -#define AON_SYSCTL_RESETCTL_SYSRESET_S 31 +#define AON_SYSCTL_RESETCTL_SYSRESET 0x80000000 +#define AON_SYSCTL_RESETCTL_SYSRESET_BITN 31 +#define AON_SYSCTL_RESETCTL_SYSRESET_M 0x80000000 +#define AON_SYSCTL_RESETCTL_SYSRESET_S 31 // Field: [25] BOOT_DET_1_CLR // // Internal. Only to be used through TI provided API. -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR 0x02000000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_BITN 25 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_M 0x02000000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_S 25 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR 0x02000000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_BITN 25 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_M 0x02000000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_S 25 // Field: [24] BOOT_DET_0_CLR // // Internal. Only to be used through TI provided API. -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR 0x01000000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_BITN 24 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_M 0x01000000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_S 24 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR 0x01000000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_BITN 24 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_M 0x01000000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_S 24 // Field: [17] BOOT_DET_1_SET // // Internal. Only to be used through TI provided API. -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET 0x00020000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_BITN 17 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M 0x00020000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_S 17 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET 0x00020000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_BITN 17 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_M 0x00020000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_S 17 // Field: [16] BOOT_DET_0_SET // // Internal. Only to be used through TI provided API. -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET 0x00010000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_BITN 16 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_M 0x00010000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_S 16 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET 0x00010000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_BITN 16 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_M 0x00010000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_S 16 // Field: [15] WU_FROM_SD // @@ -155,10 +155,10 @@ // // Note: This flag can not be cleared and will therefor remain valid untill // poweroff/reset -#define AON_SYSCTL_RESETCTL_WU_FROM_SD 0x00008000 -#define AON_SYSCTL_RESETCTL_WU_FROM_SD_BITN 15 -#define AON_SYSCTL_RESETCTL_WU_FROM_SD_M 0x00008000 -#define AON_SYSCTL_RESETCTL_WU_FROM_SD_S 15 +#define AON_SYSCTL_RESETCTL_WU_FROM_SD 0x00008000 +#define AON_SYSCTL_RESETCTL_WU_FROM_SD_BITN 15 +#define AON_SYSCTL_RESETCTL_WU_FROM_SD_M 0x00008000 +#define AON_SYSCTL_RESETCTL_WU_FROM_SD_S 15 // Field: [14] GPIO_WU_FROM_SD // @@ -176,26 +176,26 @@ // // Note: This flag can not be cleared and will therefor remain valid untill // poweroff/reset -#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD 0x00004000 -#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_BITN 14 -#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_M 0x00004000 -#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_S 14 +#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD 0x00004000 +#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_BITN 14 +#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_M 0x00004000 +#define AON_SYSCTL_RESETCTL_GPIO_WU_FROM_SD_S 14 // Field: [13] BOOT_DET_1 // // Internal. Only to be used through TI provided API. -#define AON_SYSCTL_RESETCTL_BOOT_DET_1 0x00002000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_BITN 13 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_M 0x00002000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_1_S 13 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1 0x00002000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_BITN 13 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_M 0x00002000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_1_S 13 // Field: [12] BOOT_DET_0 // // Internal. Only to be used through TI provided API. -#define AON_SYSCTL_RESETCTL_BOOT_DET_0 0x00001000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_BITN 12 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_M 0x00001000 -#define AON_SYSCTL_RESETCTL_BOOT_DET_0_S 12 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0 0x00001000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_BITN 12 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_M 0x00001000 +#define AON_SYSCTL_RESETCTL_BOOT_DET_0_S 12 // Field: [11] VDDS_LOSS_EN_OVR // @@ -206,10 +206,10 @@ // VDDS_LOSS_EN) // // This bit can be locked -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR 0x00000800 -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_BITN 11 -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_M 0x00000800 -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_S 11 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR 0x00000800 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_BITN 11 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_M 0x00000800 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_OVR_S 11 // Field: [10] VDDR_LOSS_EN_OVR // @@ -220,10 +220,10 @@ // VDDR_LOSS_EN) // // This bit can be locked -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR 0x00000400 -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_BITN 10 -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_M 0x00000400 -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_S 10 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR 0x00000400 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_BITN 10 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_M 0x00000400 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_OVR_S 10 // Field: [9] VDD_LOSS_EN_OVR // @@ -234,10 +234,10 @@ // VDD_LOSS_EN) // // This bit can be locked -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR 0x00000200 -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_BITN 9 -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_M 0x00000200 -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_S 9 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR 0x00000200 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_BITN 9 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_M 0x00000200 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_OVR_S 9 // Field: [7] VDDS_LOSS_EN // @@ -245,10 +245,10 @@ // // 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1 // 1: Brown out detect of VDDS generates system reset -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN 0x00000080 -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_BITN 7 -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_M 0x00000080 -#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_S 7 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN 0x00000080 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_BITN 7 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_M 0x00000080 +#define AON_SYSCTL_RESETCTL_VDDS_LOSS_EN_S 7 // Field: [6] VDDR_LOSS_EN // @@ -256,10 +256,10 @@ // // 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1 // 1: Brown out detect of VDDR generates system reset -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN 0x00000040 -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_BITN 6 -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_M 0x00000040 -#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_S 6 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN 0x00000040 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_BITN 6 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_M 0x00000040 +#define AON_SYSCTL_RESETCTL_VDDR_LOSS_EN_S 6 // Field: [5] VDD_LOSS_EN // @@ -267,10 +267,10 @@ // // 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1 // 1: Brown out detect of VDD generates system reset -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN 0x00000020 -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_BITN 5 -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_M 0x00000020 -#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_S 5 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN 0x00000020 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_BITN 5 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_M 0x00000020 +#define AON_SYSCTL_RESETCTL_VDD_LOSS_EN_S 5 // Field: [4] CLK_LOSS_EN // @@ -285,10 +285,10 @@ // // 0: Clock loss is ignored // 1: Clock loss generates system reset -#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN 0x00000010 -#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_BITN 4 -#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_M 0x00000010 -#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_S 4 +#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN 0x00000010 +#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_BITN 4 +#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_M 0x00000010 +#define AON_SYSCTL_RESETCTL_CLK_LOSS_EN_S 4 // Field: [3:1] RESET_SRC // @@ -310,17 +310,17 @@ // VDDS_LOSS Brown out detect on VDDS // PIN_RESET Reset pin // PWR_ON Power on reset -#define AON_SYSCTL_RESETCTL_RESET_SRC_W 3 -#define AON_SYSCTL_RESETCTL_RESET_SRC_M 0x0000000E -#define AON_SYSCTL_RESETCTL_RESET_SRC_S 1 -#define AON_SYSCTL_RESETCTL_RESET_SRC_WARMRESET 0x0000000E -#define AON_SYSCTL_RESETCTL_RESET_SRC_SYSRESET 0x0000000C -#define AON_SYSCTL_RESETCTL_RESET_SRC_CLK_LOSS 0x0000000A -#define AON_SYSCTL_RESETCTL_RESET_SRC_VDDR_LOSS 0x00000008 -#define AON_SYSCTL_RESETCTL_RESET_SRC_VDD_LOSS 0x00000006 -#define AON_SYSCTL_RESETCTL_RESET_SRC_VDDS_LOSS 0x00000004 -#define AON_SYSCTL_RESETCTL_RESET_SRC_PIN_RESET 0x00000002 -#define AON_SYSCTL_RESETCTL_RESET_SRC_PWR_ON 0x00000000 +#define AON_SYSCTL_RESETCTL_RESET_SRC_W 3 +#define AON_SYSCTL_RESETCTL_RESET_SRC_M 0x0000000E +#define AON_SYSCTL_RESETCTL_RESET_SRC_S 1 +#define AON_SYSCTL_RESETCTL_RESET_SRC_WARMRESET 0x0000000E +#define AON_SYSCTL_RESETCTL_RESET_SRC_SYSRESET 0x0000000C +#define AON_SYSCTL_RESETCTL_RESET_SRC_CLK_LOSS 0x0000000A +#define AON_SYSCTL_RESETCTL_RESET_SRC_VDDR_LOSS 0x00000008 +#define AON_SYSCTL_RESETCTL_RESET_SRC_VDD_LOSS 0x00000006 +#define AON_SYSCTL_RESETCTL_RESET_SRC_VDDS_LOSS 0x00000004 +#define AON_SYSCTL_RESETCTL_RESET_SRC_PIN_RESET 0x00000002 +#define AON_SYSCTL_RESETCTL_RESET_SRC_PWR_ON 0x00000000 //***************************************************************************** // @@ -339,10 +339,9 @@ // // Application software may want to reconfigure the state for all IO's before // setting this bitfield upon waking up from a SHUTDOWN. -#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS 0x00000001 -#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN 0 -#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_M 0x00000001 -#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_S 0 - +#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS 0x00000001 +#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN 0 +#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_M 0x00000001 +#define AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_S 0 #endif // __AON_SYSCTL__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_wuc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_wuc.h index 9642cae..0b47dca 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_wuc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aon_wuc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aon_wuc_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aon_wuc_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AON_WUC_H__ #define __HW_AON_WUC_H__ @@ -44,46 +44,46 @@ // //***************************************************************************** // MCU Clock Management -#define AON_WUC_O_MCUCLK 0x00000000 +#define AON_WUC_O_MCUCLK 0x00000000 // AUX Clock Management -#define AON_WUC_O_AUXCLK 0x00000004 +#define AON_WUC_O_AUXCLK 0x00000004 // MCU Configuration -#define AON_WUC_O_MCUCFG 0x00000008 +#define AON_WUC_O_MCUCFG 0x00000008 // AUX Configuration -#define AON_WUC_O_AUXCFG 0x0000000C +#define AON_WUC_O_AUXCFG 0x0000000C // AUX Control -#define AON_WUC_O_AUXCTL 0x00000010 +#define AON_WUC_O_AUXCTL 0x00000010 // Power Status -#define AON_WUC_O_PWRSTAT 0x00000014 +#define AON_WUC_O_PWRSTAT 0x00000014 // Shutdown Control -#define AON_WUC_O_SHUTDOWN 0x00000018 +#define AON_WUC_O_SHUTDOWN 0x00000018 // Control 0 -#define AON_WUC_O_CTL0 0x00000020 +#define AON_WUC_O_CTL0 0x00000020 // Control 1 -#define AON_WUC_O_CTL1 0x00000024 +#define AON_WUC_O_CTL1 0x00000024 // Recharge Controller Configuration -#define AON_WUC_O_RECHARGECFG 0x00000030 +#define AON_WUC_O_RECHARGECFG 0x00000030 // Recharge Controller Status -#define AON_WUC_O_RECHARGESTAT 0x00000034 +#define AON_WUC_O_RECHARGESTAT 0x00000034 // Oscillator Configuration -#define AON_WUC_O_OSCCFG 0x00000038 +#define AON_WUC_O_OSCCFG 0x00000038 // JTAG Configuration -#define AON_WUC_O_JTAGCFG 0x00000040 +#define AON_WUC_O_JTAGCFG 0x00000040 // JTAG USERCODE -#define AON_WUC_O_JTAGUSERCODE 0x00000044 +#define AON_WUC_O_JTAGUSERCODE 0x00000044 //***************************************************************************** // @@ -98,10 +98,10 @@ // 1: RCOSC_HF is calibrated to 48 MHz, allowing FLASH to power up. // 0: RCOSC_HF is not yet calibrated, ie FLASH must not assume that the SCLK_HF // is safe -#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE 0x00000004 -#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_BITN 2 -#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_M 0x00000004 -#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_S 2 +#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE 0x00000004 +#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_BITN 2 +#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_M 0x00000004 +#define AON_WUC_MCUCLK_RCOSC_HF_CAL_DONE_S 2 // Field: [1:0] PWR_DWN_SRC // @@ -115,11 +115,11 @@ // ENUMs: // SCLK_LF Use SCLK_LF in Powerdown // NONE No clock in Powerdown -#define AON_WUC_MCUCLK_PWR_DWN_SRC_W 2 -#define AON_WUC_MCUCLK_PWR_DWN_SRC_M 0x00000003 -#define AON_WUC_MCUCLK_PWR_DWN_SRC_S 0 -#define AON_WUC_MCUCLK_PWR_DWN_SRC_SCLK_LF 0x00000001 -#define AON_WUC_MCUCLK_PWR_DWN_SRC_NONE 0x00000000 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_W 2 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_M 0x00000003 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_S 0 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_SCLK_LF 0x00000001 +#define AON_WUC_MCUCLK_PWR_DWN_SRC_NONE 0x00000000 //***************************************************************************** // @@ -134,11 +134,11 @@ // ENUMs: // SCLK_LF Use SCLK_LF in Powerdown // NONE No clock in Powerdown -#define AON_WUC_AUXCLK_PWR_DWN_SRC_W 2 -#define AON_WUC_AUXCLK_PWR_DWN_SRC_M 0x00001800 -#define AON_WUC_AUXCLK_PWR_DWN_SRC_S 11 -#define AON_WUC_AUXCLK_PWR_DWN_SRC_SCLK_LF 0x00000800 -#define AON_WUC_AUXCLK_PWR_DWN_SRC_NONE 0x00000000 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_W 2 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_M 0x00001800 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_S 11 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_SCLK_LF 0x00000800 +#define AON_WUC_AUXCLK_PWR_DWN_SRC_NONE 0x00000000 // Field: [10:8] SCLK_HF_DIV // @@ -155,17 +155,17 @@ // DIV8 Divide by 8 // DIV4 Divide by 4 // DIV2 Divide by 2 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_W 3 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_M 0x00000700 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_S 8 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV256 0x00000700 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV128 0x00000600 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV64 0x00000500 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV32 0x00000400 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV16 0x00000300 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV8 0x00000200 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV4 0x00000100 -#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV2 0x00000000 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_W 3 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_M 0x00000700 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_S 8 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV256 0x00000700 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV128 0x00000600 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV64 0x00000500 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV32 0x00000400 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV16 0x00000300 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV8 0x00000200 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV4 0x00000100 +#define AON_WUC_AUXCLK_SCLK_HF_DIV_DIV2 0x00000000 // Field: [2:0] SRC // @@ -175,11 +175,11 @@ // ENUMs: // SCLK_LF LF Clock (SCLK_LF) // SCLK_HF HF Clock (SCLK_HF) -#define AON_WUC_AUXCLK_SRC_W 3 -#define AON_WUC_AUXCLK_SRC_M 0x00000007 -#define AON_WUC_AUXCLK_SRC_S 0 -#define AON_WUC_AUXCLK_SRC_SCLK_LF 0x00000004 -#define AON_WUC_AUXCLK_SRC_SCLK_HF 0x00000001 +#define AON_WUC_AUXCLK_SRC_W 3 +#define AON_WUC_AUXCLK_SRC_M 0x00000007 +#define AON_WUC_AUXCLK_SRC_S 0 +#define AON_WUC_AUXCLK_SRC_SCLK_LF 0x00000004 +#define AON_WUC_AUXCLK_SRC_SCLK_HF 0x00000001 //***************************************************************************** // @@ -189,18 +189,18 @@ // Field: [17] VIRT_OFF // // Internal. Only to be used through TI provided API. -#define AON_WUC_MCUCFG_VIRT_OFF 0x00020000 -#define AON_WUC_MCUCFG_VIRT_OFF_BITN 17 -#define AON_WUC_MCUCFG_VIRT_OFF_M 0x00020000 -#define AON_WUC_MCUCFG_VIRT_OFF_S 17 +#define AON_WUC_MCUCFG_VIRT_OFF 0x00020000 +#define AON_WUC_MCUCFG_VIRT_OFF_BITN 17 +#define AON_WUC_MCUCFG_VIRT_OFF_M 0x00020000 +#define AON_WUC_MCUCFG_VIRT_OFF_S 17 // Field: [16] FIXED_WU_EN // // Internal. Only to be used through TI provided API. -#define AON_WUC_MCUCFG_FIXED_WU_EN 0x00010000 -#define AON_WUC_MCUCFG_FIXED_WU_EN_BITN 16 -#define AON_WUC_MCUCFG_FIXED_WU_EN_M 0x00010000 -#define AON_WUC_MCUCFG_FIXED_WU_EN_S 16 +#define AON_WUC_MCUCFG_FIXED_WU_EN 0x00010000 +#define AON_WUC_MCUCFG_FIXED_WU_EN_BITN 16 +#define AON_WUC_MCUCFG_FIXED_WU_EN_M 0x00010000 +#define AON_WUC_MCUCFG_FIXED_WU_EN_S 16 // Field: [3:0] SRAM_RET_EN // @@ -214,14 +214,14 @@ // RET_LEVEL2 Retention on for SRAM:BANK0 and SRAM:BANK1 // RET_LEVEL1 Retention on for SRAM:BANK0 // RET_NONE Retention is disabled -#define AON_WUC_MCUCFG_SRAM_RET_EN_W 4 -#define AON_WUC_MCUCFG_SRAM_RET_EN_M 0x0000000F -#define AON_WUC_MCUCFG_SRAM_RET_EN_S 0 -#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_FULL 0x0000000F -#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL3 0x00000007 -#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL2 0x00000003 -#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL1 0x00000001 -#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_NONE 0x00000000 +#define AON_WUC_MCUCFG_SRAM_RET_EN_W 4 +#define AON_WUC_MCUCFG_SRAM_RET_EN_M 0x0000000F +#define AON_WUC_MCUCFG_SRAM_RET_EN_S 0 +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_FULL 0x0000000F +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL3 0x00000007 +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL2 0x00000003 +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_LEVEL1 0x00000001 +#define AON_WUC_MCUCFG_SRAM_RET_EN_RET_NONE 0x00000000 //***************************************************************************** // @@ -237,10 +237,10 @@ // // NB: If retention is disabled, the AUX_RAM will be powered off when it would // otherwise be put in retention mode -#define AON_WUC_AUXCFG_RAM_RET_EN 0x00000001 -#define AON_WUC_AUXCFG_RAM_RET_EN_BITN 0 -#define AON_WUC_AUXCFG_RAM_RET_EN_M 0x00000001 -#define AON_WUC_AUXCFG_RAM_RET_EN_S 0 +#define AON_WUC_AUXCFG_RAM_RET_EN 0x00000001 +#define AON_WUC_AUXCFG_RAM_RET_EN_BITN 0 +#define AON_WUC_AUXCFG_RAM_RET_EN_M 0x00000001 +#define AON_WUC_AUXCFG_RAM_RET_EN_S 0 //***************************************************************************** // @@ -254,10 +254,10 @@ // // 0: AUX reset pin will be deasserted // 1: AUX reset pin will be asserted -#define AON_WUC_AUXCTL_RESET_REQ 0x80000000 -#define AON_WUC_AUXCTL_RESET_REQ_BITN 31 -#define AON_WUC_AUXCTL_RESET_REQ_M 0x80000000 -#define AON_WUC_AUXCTL_RESET_REQ_S 31 +#define AON_WUC_AUXCTL_RESET_REQ 0x80000000 +#define AON_WUC_AUXCTL_RESET_REQ_BITN 31 +#define AON_WUC_AUXCTL_RESET_REQ_M 0x80000000 +#define AON_WUC_AUXCTL_RESET_REQ_S 31 // Field: [2] SCE_RUN_EN // @@ -270,10 +270,10 @@ // // 0: AUX_SCE execution will be disabled if AUX_SCE:CTL.CLK_EN is 0 // 1: AUX_SCE execution is enabled. -#define AON_WUC_AUXCTL_SCE_RUN_EN 0x00000004 -#define AON_WUC_AUXCTL_SCE_RUN_EN_BITN 2 -#define AON_WUC_AUXCTL_SCE_RUN_EN_M 0x00000004 -#define AON_WUC_AUXCTL_SCE_RUN_EN_S 2 +#define AON_WUC_AUXCTL_SCE_RUN_EN 0x00000004 +#define AON_WUC_AUXCTL_SCE_RUN_EN_BITN 2 +#define AON_WUC_AUXCTL_SCE_RUN_EN_M 0x00000004 +#define AON_WUC_AUXCTL_SCE_RUN_EN_S 2 // Field: [1] SWEV // @@ -288,10 +288,10 @@ // // Note that it can take up to 1,5 SCLK_LF clock cycles to clear the event from // AUX. -#define AON_WUC_AUXCTL_SWEV 0x00000002 -#define AON_WUC_AUXCTL_SWEV_BITN 1 -#define AON_WUC_AUXCTL_SWEV_M 0x00000002 -#define AON_WUC_AUXCTL_SWEV_S 1 +#define AON_WUC_AUXCTL_SWEV 0x00000002 +#define AON_WUC_AUXCTL_SWEV_BITN 1 +#define AON_WUC_AUXCTL_SWEV_M 0x00000002 +#define AON_WUC_AUXCTL_SWEV_S 1 // Field: [0] AUX_FORCE_ON // @@ -305,10 +305,10 @@ // // 0: AUX is allowed to Power Off, Power Down or Disconnect. // 1: AUX Power OFF, Power Down or Disconnect requests will be overruled -#define AON_WUC_AUXCTL_AUX_FORCE_ON 0x00000001 -#define AON_WUC_AUXCTL_AUX_FORCE_ON_BITN 0 -#define AON_WUC_AUXCTL_AUX_FORCE_ON_M 0x00000001 -#define AON_WUC_AUXCTL_AUX_FORCE_ON_S 0 +#define AON_WUC_AUXCTL_AUX_FORCE_ON 0x00000001 +#define AON_WUC_AUXCTL_AUX_FORCE_ON_BITN 0 +#define AON_WUC_AUXCTL_AUX_FORCE_ON_M 0x00000001 +#define AON_WUC_AUXCTL_AUX_FORCE_ON_S 0 //***************************************************************************** // @@ -321,10 +321,10 @@ // // 0: Active mode // 1: AUX Powerdown request has been granted -#define AON_WUC_PWRSTAT_AUX_PWR_DWN 0x00000200 -#define AON_WUC_PWRSTAT_AUX_PWR_DWN_BITN 9 -#define AON_WUC_PWRSTAT_AUX_PWR_DWN_M 0x00000200 -#define AON_WUC_PWRSTAT_AUX_PWR_DWN_S 9 +#define AON_WUC_PWRSTAT_AUX_PWR_DWN 0x00000200 +#define AON_WUC_PWRSTAT_AUX_PWR_DWN_BITN 9 +#define AON_WUC_PWRSTAT_AUX_PWR_DWN_M 0x00000200 +#define AON_WUC_PWRSTAT_AUX_PWR_DWN_S 9 // Field: [6] JTAG_PD_ON // @@ -332,10 +332,10 @@ // // 0: JTAG is powered off // 1: JTAG is powered on -#define AON_WUC_PWRSTAT_JTAG_PD_ON 0x00000040 -#define AON_WUC_PWRSTAT_JTAG_PD_ON_BITN 6 -#define AON_WUC_PWRSTAT_JTAG_PD_ON_M 0x00000040 -#define AON_WUC_PWRSTAT_JTAG_PD_ON_S 6 +#define AON_WUC_PWRSTAT_JTAG_PD_ON 0x00000040 +#define AON_WUC_PWRSTAT_JTAG_PD_ON_BITN 6 +#define AON_WUC_PWRSTAT_JTAG_PD_ON_M 0x00000040 +#define AON_WUC_PWRSTAT_JTAG_PD_ON_S 6 // Field: [5] AUX_PD_ON // @@ -344,10 +344,10 @@ // 0: AUX is not ready for use ( may be powered off or in power state // transition ) // 1: AUX is powered on, connected to bus and ready for use, -#define AON_WUC_PWRSTAT_AUX_PD_ON 0x00000020 -#define AON_WUC_PWRSTAT_AUX_PD_ON_BITN 5 -#define AON_WUC_PWRSTAT_AUX_PD_ON_M 0x00000020 -#define AON_WUC_PWRSTAT_AUX_PD_ON_S 5 +#define AON_WUC_PWRSTAT_AUX_PD_ON 0x00000020 +#define AON_WUC_PWRSTAT_AUX_PD_ON_BITN 5 +#define AON_WUC_PWRSTAT_AUX_PD_ON_M 0x00000020 +#define AON_WUC_PWRSTAT_AUX_PD_ON_S 5 // Field: [4] MCU_PD_ON // @@ -357,10 +357,10 @@ // be reliable // 1: MCU Power sequencing is finalized and all MCU_AONIF registers are // reliable -#define AON_WUC_PWRSTAT_MCU_PD_ON 0x00000010 -#define AON_WUC_PWRSTAT_MCU_PD_ON_BITN 4 -#define AON_WUC_PWRSTAT_MCU_PD_ON_M 0x00000010 -#define AON_WUC_PWRSTAT_MCU_PD_ON_S 4 +#define AON_WUC_PWRSTAT_MCU_PD_ON 0x00000010 +#define AON_WUC_PWRSTAT_MCU_PD_ON_BITN 4 +#define AON_WUC_PWRSTAT_MCU_PD_ON_M 0x00000010 +#define AON_WUC_PWRSTAT_MCU_PD_ON_S 4 // Field: [2] AUX_BUS_CONNECTED // @@ -368,10 +368,10 @@ // // 0: AUX bus is not connected // 1: AUX bus is connected ( idle_ack = 0 ) -#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED 0x00000004 -#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_BITN 2 -#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_M 0x00000004 -#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_S 2 +#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED 0x00000004 +#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_BITN 2 +#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_M 0x00000004 +#define AON_WUC_PWRSTAT_AUX_BUS_CONNECTED_S 2 // Field: [1] AUX_RESET_DONE // @@ -379,10 +379,10 @@ // // 0: AUX is being reset // 1: AUX reset is released -#define AON_WUC_PWRSTAT_AUX_RESET_DONE 0x00000002 -#define AON_WUC_PWRSTAT_AUX_RESET_DONE_BITN 1 -#define AON_WUC_PWRSTAT_AUX_RESET_DONE_M 0x00000002 -#define AON_WUC_PWRSTAT_AUX_RESET_DONE_S 1 +#define AON_WUC_PWRSTAT_AUX_RESET_DONE 0x00000002 +#define AON_WUC_PWRSTAT_AUX_RESET_DONE_BITN 1 +#define AON_WUC_PWRSTAT_AUX_RESET_DONE_M 0x00000002 +#define AON_WUC_PWRSTAT_AUX_RESET_DONE_S 1 //***************************************************************************** // @@ -400,10 +400,10 @@ // conditions exists. At this time, the will not enter Powerdown mode, but // instead it will turn off all internal powersupplies, effectively putting the // device into Shutdown mode. -#define AON_WUC_SHUTDOWN_EN 0x00000001 -#define AON_WUC_SHUTDOWN_EN_BITN 0 -#define AON_WUC_SHUTDOWN_EN_M 0x00000001 -#define AON_WUC_SHUTDOWN_EN_S 0 +#define AON_WUC_SHUTDOWN_EN 0x00000001 +#define AON_WUC_SHUTDOWN_EN_BITN 0 +#define AON_WUC_SHUTDOWN_EN_M 0x00000001 +#define AON_WUC_SHUTDOWN_EN_S 0 //***************************************************************************** // @@ -417,26 +417,26 @@ // // 0: Enabled // 1: Disabled -#define AON_WUC_CTL0_PWR_DWN_DIS 0x00000100 -#define AON_WUC_CTL0_PWR_DWN_DIS_BITN 8 -#define AON_WUC_CTL0_PWR_DWN_DIS_M 0x00000100 -#define AON_WUC_CTL0_PWR_DWN_DIS_S 8 +#define AON_WUC_CTL0_PWR_DWN_DIS 0x00000100 +#define AON_WUC_CTL0_PWR_DWN_DIS_BITN 8 +#define AON_WUC_CTL0_PWR_DWN_DIS_M 0x00000100 +#define AON_WUC_CTL0_PWR_DWN_DIS_S 8 // Field: [3] AUX_SRAM_ERASE // // Internal. Only to be used through TI provided API. -#define AON_WUC_CTL0_AUX_SRAM_ERASE 0x00000008 -#define AON_WUC_CTL0_AUX_SRAM_ERASE_BITN 3 -#define AON_WUC_CTL0_AUX_SRAM_ERASE_M 0x00000008 -#define AON_WUC_CTL0_AUX_SRAM_ERASE_S 3 +#define AON_WUC_CTL0_AUX_SRAM_ERASE 0x00000008 +#define AON_WUC_CTL0_AUX_SRAM_ERASE_BITN 3 +#define AON_WUC_CTL0_AUX_SRAM_ERASE_M 0x00000008 +#define AON_WUC_CTL0_AUX_SRAM_ERASE_S 3 // Field: [2] MCU_SRAM_ERASE // // Internal. Only to be used through TI provided API. -#define AON_WUC_CTL0_MCU_SRAM_ERASE 0x00000004 -#define AON_WUC_CTL0_MCU_SRAM_ERASE_BITN 2 -#define AON_WUC_CTL0_MCU_SRAM_ERASE_M 0x00000004 -#define AON_WUC_CTL0_MCU_SRAM_ERASE_S 2 +#define AON_WUC_CTL0_MCU_SRAM_ERASE 0x00000004 +#define AON_WUC_CTL0_MCU_SRAM_ERASE_BITN 2 +#define AON_WUC_CTL0_MCU_SRAM_ERASE_M 0x00000004 +#define AON_WUC_CTL0_MCU_SRAM_ERASE_S 2 //***************************************************************************** // @@ -451,10 +451,10 @@ // 1: JTAG reset // // This bit can only be cleared by writing a 1 to it -#define AON_WUC_CTL1_MCU_RESET_SRC 0x00000002 -#define AON_WUC_CTL1_MCU_RESET_SRC_BITN 1 -#define AON_WUC_CTL1_MCU_RESET_SRC_M 0x00000002 -#define AON_WUC_CTL1_MCU_RESET_SRC_S 1 +#define AON_WUC_CTL1_MCU_RESET_SRC 0x00000002 +#define AON_WUC_CTL1_MCU_RESET_SRC_BITN 1 +#define AON_WUC_CTL1_MCU_RESET_SRC_M 0x00000002 +#define AON_WUC_CTL1_MCU_RESET_SRC_S 1 // Field: [0] MCU_WARM_RESET // @@ -465,10 +465,10 @@ // in MCU_RESET_SRC) // // This bit can only be cleared by writing a 1 to it -#define AON_WUC_CTL1_MCU_WARM_RESET 0x00000001 -#define AON_WUC_CTL1_MCU_WARM_RESET_BITN 0 -#define AON_WUC_CTL1_MCU_WARM_RESET_M 0x00000001 -#define AON_WUC_CTL1_MCU_WARM_RESET_S 0 +#define AON_WUC_CTL1_MCU_WARM_RESET 0x00000001 +#define AON_WUC_CTL1_MCU_WARM_RESET_BITN 0 +#define AON_WUC_CTL1_MCU_WARM_RESET_M 0x00000001 +#define AON_WUC_CTL1_MCU_WARM_RESET_S 0 //***************************************************************************** // @@ -481,10 +481,10 @@ // // Note: Recharge can be turned completely of by setting MAX_PER_E=7 and // MAX_PER_M=31 and this bitfield to 0 -#define AON_WUC_RECHARGECFG_ADAPTIVE_EN 0x80000000 -#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_BITN 31 -#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_M 0x80000000 -#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_S 31 +#define AON_WUC_RECHARGECFG_ADAPTIVE_EN 0x80000000 +#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_BITN 31 +#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_M 0x80000000 +#define AON_WUC_RECHARGECFG_ADAPTIVE_EN_S 31 // Field: [23:20] C2 // @@ -496,9 +496,9 @@ // Note: Rounding may cause adaptive recharge not to start for very small // values of both Gain and Initial period. Criteria for algorithm to start is // MAX(PERIOD*2^-C1,PERIOD*2^-C2) >= 1 -#define AON_WUC_RECHARGECFG_C2_W 4 -#define AON_WUC_RECHARGECFG_C2_M 0x00F00000 -#define AON_WUC_RECHARGECFG_C2_S 20 +#define AON_WUC_RECHARGECFG_C2_W 4 +#define AON_WUC_RECHARGECFG_C2_M 0x00F00000 +#define AON_WUC_RECHARGECFG_C2_S 20 // Field: [19:16] C1 // @@ -510,9 +510,9 @@ // Note: Rounding may cause adaptive recharge not to start for very small // values of both Gain and Initial period. Criteria for algorithm to start is // MAX(PERIOD*2^-C1,PERIOD*2^-C2) >= 1 -#define AON_WUC_RECHARGECFG_C1_W 4 -#define AON_WUC_RECHARGECFG_C1_M 0x000F0000 -#define AON_WUC_RECHARGECFG_C1_S 16 +#define AON_WUC_RECHARGECFG_C1_W 4 +#define AON_WUC_RECHARGECFG_C1_M 0x000F0000 +#define AON_WUC_RECHARGECFG_C1_S 16 // Field: [15:11] MAX_PER_M // @@ -522,9 +522,9 @@ // exponent: // MAXCYCLES=(MAX_PER_M*16+15)*2^MAX_PER_E // This field sets the mantissa of MAXCYCLES -#define AON_WUC_RECHARGECFG_MAX_PER_M_W 5 -#define AON_WUC_RECHARGECFG_MAX_PER_M_M 0x0000F800 -#define AON_WUC_RECHARGECFG_MAX_PER_M_S 11 +#define AON_WUC_RECHARGECFG_MAX_PER_M_W 5 +#define AON_WUC_RECHARGECFG_MAX_PER_M_M 0x0000F800 +#define AON_WUC_RECHARGECFG_MAX_PER_M_S 11 // Field: [10:8] MAX_PER_E // @@ -534,9 +534,9 @@ // exponent: // MAXCYCLES=(MAX_PER_M*16+15)*2^MAX_PER_E // This field sets the exponent MAXCYCLES -#define AON_WUC_RECHARGECFG_MAX_PER_E_W 3 -#define AON_WUC_RECHARGECFG_MAX_PER_E_M 0x00000700 -#define AON_WUC_RECHARGECFG_MAX_PER_E_S 8 +#define AON_WUC_RECHARGECFG_MAX_PER_E_W 3 +#define AON_WUC_RECHARGECFG_MAX_PER_E_M 0x00000700 +#define AON_WUC_RECHARGECFG_MAX_PER_E_S 8 // Field: [7:3] PER_M // @@ -547,9 +547,9 @@ // bit exponent: // This field sets the Mantissa of the Period. // PERIOD=(PER_M*16+15)*2^PER_E -#define AON_WUC_RECHARGECFG_PER_M_W 5 -#define AON_WUC_RECHARGECFG_PER_M_M 0x000000F8 -#define AON_WUC_RECHARGECFG_PER_M_S 3 +#define AON_WUC_RECHARGECFG_PER_M_W 5 +#define AON_WUC_RECHARGECFG_PER_M_M 0x000000F8 +#define AON_WUC_RECHARGECFG_PER_M_S 3 // Field: [2:0] PER_E // @@ -560,9 +560,9 @@ // bit exponent: // This field sets the Exponent of the Period. // PERIOD=(PER_M*16+15)*2^PER_E -#define AON_WUC_RECHARGECFG_PER_E_W 3 -#define AON_WUC_RECHARGECFG_PER_E_M 0x00000007 -#define AON_WUC_RECHARGECFG_PER_E_S 0 +#define AON_WUC_RECHARGECFG_PER_E_W 3 +#define AON_WUC_RECHARGECFG_PER_E_M 0x00000007 +#define AON_WUC_RECHARGECFG_PER_E_S 0 //***************************************************************************** // @@ -577,9 +577,9 @@ // and bit 0 is updated with the last VDDR sample, ie a 1 is shiftet in in case // VDDR > VDDR_threshold just before recharge starts. Otherwise a 0 will be // shifted in. -#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_W 4 -#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_M 0x000F0000 -#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_S 16 +#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_W 4 +#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_M 0x000F0000 +#define AON_WUC_RECHARGESTAT_VDDR_SMPLS_S 16 // Field: [15:0] MAX_USED_PER // @@ -593,9 +593,9 @@ // recharge. // // This bitfield is cleared to 0 when writing this register. -#define AON_WUC_RECHARGESTAT_MAX_USED_PER_W 16 -#define AON_WUC_RECHARGESTAT_MAX_USED_PER_M 0x0000FFFF -#define AON_WUC_RECHARGESTAT_MAX_USED_PER_S 0 +#define AON_WUC_RECHARGESTAT_MAX_USED_PER_W 16 +#define AON_WUC_RECHARGESTAT_MAX_USED_PER_M 0x0000FFFF +#define AON_WUC_RECHARGESTAT_MAX_USED_PER_S 0 //***************************************************************************** // @@ -616,9 +616,9 @@ // This field sets the mantissa // Note: Oscillator amplitude calibration is turned of when both this bitfield // and PER_E are set to 0 -#define AON_WUC_OSCCFG_PER_M_W 5 -#define AON_WUC_OSCCFG_PER_M_M 0x000000F8 -#define AON_WUC_OSCCFG_PER_M_S 3 +#define AON_WUC_OSCCFG_PER_M_W 5 +#define AON_WUC_OSCCFG_PER_M_M 0x000000F8 +#define AON_WUC_OSCCFG_PER_M_S 3 // Field: [2:0] PER_E // @@ -633,9 +633,9 @@ // This field sets the exponent // Note: Oscillator amplitude calibration is turned of when both PER_M and // this bitfield are set to 0 -#define AON_WUC_OSCCFG_PER_E_W 3 -#define AON_WUC_OSCCFG_PER_E_M 0x00000007 -#define AON_WUC_OSCCFG_PER_E_S 0 +#define AON_WUC_OSCCFG_PER_E_W 3 +#define AON_WUC_OSCCFG_PER_E_M 0x00000007 +#define AON_WUC_OSCCFG_PER_E_S 0 //***************************************************************************** // @@ -652,10 +652,10 @@ // // NB: The reset value causes JTAG Power Domain to be powered on by default. // Software must clear this bit to turn off the JTAG Power Domain -#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON 0x00000100 -#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_BITN 8 -#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_M 0x00000100 -#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_S 8 +#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON 0x00000100 +#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_BITN 8 +#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_M 0x00000100 +#define AON_WUC_JTAGCFG_JTAG_PD_FORCE_ON_S 8 //***************************************************************************** // @@ -666,9 +666,8 @@ // // 32-bit JTAG USERCODE register feeding main JTAG TAP // NB: This field can be locked -#define AON_WUC_JTAGUSERCODE_USER_CODE_W 32 -#define AON_WUC_JTAGUSERCODE_USER_CODE_M 0xFFFFFFFF -#define AON_WUC_JTAGUSERCODE_USER_CODE_S 0 - +#define AON_WUC_JTAGUSERCODE_USER_CODE_W 32 +#define AON_WUC_JTAGUSERCODE_USER_CODE_M 0xFFFFFFFF +#define AON_WUC_JTAGUSERCODE_USER_CODE_S 0 #endif // __AON_WUC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_aiodio.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_aiodio.h index 7d6b08f..a62ce47 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_aiodio.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_aiodio.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_aiodio_h -* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) -* Revision: 49005 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_aiodio_h + * Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) + * Revision: 49005 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_AIODIO_H__ #define __HW_AUX_AIODIO_H__ @@ -44,25 +44,25 @@ // //***************************************************************************** // General Purpose Input Output Data Out -#define AUX_AIODIO_O_GPIODOUT 0x00000000 +#define AUX_AIODIO_O_GPIODOUT 0x00000000 // Input Output Mode -#define AUX_AIODIO_O_IOMODE 0x00000004 +#define AUX_AIODIO_O_IOMODE 0x00000004 // General Purpose Input Output Data In -#define AUX_AIODIO_O_GPIODIN 0x00000008 +#define AUX_AIODIO_O_GPIODIN 0x00000008 // General Purpose Input Output Data Out Set -#define AUX_AIODIO_O_GPIODOUTSET 0x0000000C +#define AUX_AIODIO_O_GPIODOUTSET 0x0000000C // General Purpose Input Output Data Out Clear -#define AUX_AIODIO_O_GPIODOUTCLR 0x00000010 +#define AUX_AIODIO_O_GPIODOUTCLR 0x00000010 // General Purpose Input Output Data Out Toggle -#define AUX_AIODIO_O_GPIODOUTTGL 0x00000014 +#define AUX_AIODIO_O_GPIODOUTTGL 0x00000014 // General Purpose Input Output Digital Input Enable -#define AUX_AIODIO_O_GPIODIE 0x00000018 +#define AUX_AIODIO_O_GPIODIE 0x00000018 //***************************************************************************** // @@ -73,9 +73,9 @@ // // Write 1 to bit index n in this bit vector to set AUXIO[8i+n]. // Write 0 to bit index n in this bit vector to clear AUXIO[8i+n]. -#define AUX_AIODIO_GPIODOUT_IO7_0_W 8 -#define AUX_AIODIO_GPIODOUT_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODOUT_IO7_0_S 0 +#define AUX_AIODIO_GPIODOUT_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUT_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUT_IO7_0_S 0 //***************************************************************************** // @@ -114,13 +114,13 @@ // // GPIODOUT bit 7 drives // AUXIO[8i+7]. -#define AUX_AIODIO_IOMODE_IO7_W 2 -#define AUX_AIODIO_IOMODE_IO7_M 0x0000C000 -#define AUX_AIODIO_IOMODE_IO7_S 14 -#define AUX_AIODIO_IOMODE_IO7_OPEN_SOURCE 0x0000C000 -#define AUX_AIODIO_IOMODE_IO7_OPEN_DRAIN 0x00008000 -#define AUX_AIODIO_IOMODE_IO7_IN 0x00004000 -#define AUX_AIODIO_IOMODE_IO7_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO7_W 2 +#define AUX_AIODIO_IOMODE_IO7_M 0x0000C000 +#define AUX_AIODIO_IOMODE_IO7_S 14 +#define AUX_AIODIO_IOMODE_IO7_OPEN_SOURCE 0x0000C000 +#define AUX_AIODIO_IOMODE_IO7_OPEN_DRAIN 0x00008000 +#define AUX_AIODIO_IOMODE_IO7_IN 0x00004000 +#define AUX_AIODIO_IOMODE_IO7_OUT 0x00000000 // Field: [13:12] IO6 // @@ -154,13 +154,13 @@ // // GPIODOUT bit 6 drives // AUXIO[8i+6]. -#define AUX_AIODIO_IOMODE_IO6_W 2 -#define AUX_AIODIO_IOMODE_IO6_M 0x00003000 -#define AUX_AIODIO_IOMODE_IO6_S 12 -#define AUX_AIODIO_IOMODE_IO6_OPEN_SOURCE 0x00003000 -#define AUX_AIODIO_IOMODE_IO6_OPEN_DRAIN 0x00002000 -#define AUX_AIODIO_IOMODE_IO6_IN 0x00001000 -#define AUX_AIODIO_IOMODE_IO6_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO6_W 2 +#define AUX_AIODIO_IOMODE_IO6_M 0x00003000 +#define AUX_AIODIO_IOMODE_IO6_S 12 +#define AUX_AIODIO_IOMODE_IO6_OPEN_SOURCE 0x00003000 +#define AUX_AIODIO_IOMODE_IO6_OPEN_DRAIN 0x00002000 +#define AUX_AIODIO_IOMODE_IO6_IN 0x00001000 +#define AUX_AIODIO_IOMODE_IO6_OUT 0x00000000 // Field: [11:10] IO5 // @@ -194,13 +194,13 @@ // // GPIODOUT bit 5 drives // AUXIO[8i+5]. -#define AUX_AIODIO_IOMODE_IO5_W 2 -#define AUX_AIODIO_IOMODE_IO5_M 0x00000C00 -#define AUX_AIODIO_IOMODE_IO5_S 10 -#define AUX_AIODIO_IOMODE_IO5_OPEN_SOURCE 0x00000C00 -#define AUX_AIODIO_IOMODE_IO5_OPEN_DRAIN 0x00000800 -#define AUX_AIODIO_IOMODE_IO5_IN 0x00000400 -#define AUX_AIODIO_IOMODE_IO5_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO5_W 2 +#define AUX_AIODIO_IOMODE_IO5_M 0x00000C00 +#define AUX_AIODIO_IOMODE_IO5_S 10 +#define AUX_AIODIO_IOMODE_IO5_OPEN_SOURCE 0x00000C00 +#define AUX_AIODIO_IOMODE_IO5_OPEN_DRAIN 0x00000800 +#define AUX_AIODIO_IOMODE_IO5_IN 0x00000400 +#define AUX_AIODIO_IOMODE_IO5_OUT 0x00000000 // Field: [9:8] IO4 // @@ -234,13 +234,13 @@ // // GPIODOUT bit 4 drives // AUXIO[8i+4]. -#define AUX_AIODIO_IOMODE_IO4_W 2 -#define AUX_AIODIO_IOMODE_IO4_M 0x00000300 -#define AUX_AIODIO_IOMODE_IO4_S 8 -#define AUX_AIODIO_IOMODE_IO4_OPEN_SOURCE 0x00000300 -#define AUX_AIODIO_IOMODE_IO4_OPEN_DRAIN 0x00000200 -#define AUX_AIODIO_IOMODE_IO4_IN 0x00000100 -#define AUX_AIODIO_IOMODE_IO4_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO4_W 2 +#define AUX_AIODIO_IOMODE_IO4_M 0x00000300 +#define AUX_AIODIO_IOMODE_IO4_S 8 +#define AUX_AIODIO_IOMODE_IO4_OPEN_SOURCE 0x00000300 +#define AUX_AIODIO_IOMODE_IO4_OPEN_DRAIN 0x00000200 +#define AUX_AIODIO_IOMODE_IO4_IN 0x00000100 +#define AUX_AIODIO_IOMODE_IO4_OUT 0x00000000 // Field: [7:6] IO3 // @@ -274,13 +274,13 @@ // // GPIODOUT bit 3 drives // AUXIO[8i+3]. -#define AUX_AIODIO_IOMODE_IO3_W 2 -#define AUX_AIODIO_IOMODE_IO3_M 0x000000C0 -#define AUX_AIODIO_IOMODE_IO3_S 6 -#define AUX_AIODIO_IOMODE_IO3_OPEN_SOURCE 0x000000C0 -#define AUX_AIODIO_IOMODE_IO3_OPEN_DRAIN 0x00000080 -#define AUX_AIODIO_IOMODE_IO3_IN 0x00000040 -#define AUX_AIODIO_IOMODE_IO3_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO3_W 2 +#define AUX_AIODIO_IOMODE_IO3_M 0x000000C0 +#define AUX_AIODIO_IOMODE_IO3_S 6 +#define AUX_AIODIO_IOMODE_IO3_OPEN_SOURCE 0x000000C0 +#define AUX_AIODIO_IOMODE_IO3_OPEN_DRAIN 0x00000080 +#define AUX_AIODIO_IOMODE_IO3_IN 0x00000040 +#define AUX_AIODIO_IOMODE_IO3_OUT 0x00000000 // Field: [5:4] IO2 // @@ -314,13 +314,13 @@ // // GPIODOUT bit 2 drives // AUXIO[8i+2]. -#define AUX_AIODIO_IOMODE_IO2_W 2 -#define AUX_AIODIO_IOMODE_IO2_M 0x00000030 -#define AUX_AIODIO_IOMODE_IO2_S 4 -#define AUX_AIODIO_IOMODE_IO2_OPEN_SOURCE 0x00000030 -#define AUX_AIODIO_IOMODE_IO2_OPEN_DRAIN 0x00000020 -#define AUX_AIODIO_IOMODE_IO2_IN 0x00000010 -#define AUX_AIODIO_IOMODE_IO2_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO2_W 2 +#define AUX_AIODIO_IOMODE_IO2_M 0x00000030 +#define AUX_AIODIO_IOMODE_IO2_S 4 +#define AUX_AIODIO_IOMODE_IO2_OPEN_SOURCE 0x00000030 +#define AUX_AIODIO_IOMODE_IO2_OPEN_DRAIN 0x00000020 +#define AUX_AIODIO_IOMODE_IO2_IN 0x00000010 +#define AUX_AIODIO_IOMODE_IO2_OUT 0x00000000 // Field: [3:2] IO1 // @@ -354,13 +354,13 @@ // // GPIODOUT bit 1 drives // AUXIO[8i+1]. -#define AUX_AIODIO_IOMODE_IO1_W 2 -#define AUX_AIODIO_IOMODE_IO1_M 0x0000000C -#define AUX_AIODIO_IOMODE_IO1_S 2 -#define AUX_AIODIO_IOMODE_IO1_OPEN_SOURCE 0x0000000C -#define AUX_AIODIO_IOMODE_IO1_OPEN_DRAIN 0x00000008 -#define AUX_AIODIO_IOMODE_IO1_IN 0x00000004 -#define AUX_AIODIO_IOMODE_IO1_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO1_W 2 +#define AUX_AIODIO_IOMODE_IO1_M 0x0000000C +#define AUX_AIODIO_IOMODE_IO1_S 2 +#define AUX_AIODIO_IOMODE_IO1_OPEN_SOURCE 0x0000000C +#define AUX_AIODIO_IOMODE_IO1_OPEN_DRAIN 0x00000008 +#define AUX_AIODIO_IOMODE_IO1_IN 0x00000004 +#define AUX_AIODIO_IOMODE_IO1_OUT 0x00000000 // Field: [1:0] IO0 // @@ -394,13 +394,13 @@ // // GPIODOUT bit 0 drives // AUXIO[8i+0]. -#define AUX_AIODIO_IOMODE_IO0_W 2 -#define AUX_AIODIO_IOMODE_IO0_M 0x00000003 -#define AUX_AIODIO_IOMODE_IO0_S 0 -#define AUX_AIODIO_IOMODE_IO0_OPEN_SOURCE 0x00000003 -#define AUX_AIODIO_IOMODE_IO0_OPEN_DRAIN 0x00000002 -#define AUX_AIODIO_IOMODE_IO0_IN 0x00000001 -#define AUX_AIODIO_IOMODE_IO0_OUT 0x00000000 +#define AUX_AIODIO_IOMODE_IO0_W 2 +#define AUX_AIODIO_IOMODE_IO0_M 0x00000003 +#define AUX_AIODIO_IOMODE_IO0_S 0 +#define AUX_AIODIO_IOMODE_IO0_OPEN_SOURCE 0x00000003 +#define AUX_AIODIO_IOMODE_IO0_OPEN_DRAIN 0x00000002 +#define AUX_AIODIO_IOMODE_IO0_IN 0x00000001 +#define AUX_AIODIO_IOMODE_IO0_OUT 0x00000000 //***************************************************************************** // @@ -411,9 +411,9 @@ // // Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit // n is set. Otherwise, bit n value is old. -#define AUX_AIODIO_GPIODIN_IO7_0_W 8 -#define AUX_AIODIO_GPIODIN_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODIN_IO7_0_S 0 +#define AUX_AIODIO_GPIODIN_IO7_0_W 8 +#define AUX_AIODIO_GPIODIN_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODIN_IO7_0_S 0 //***************************************************************************** // @@ -425,9 +425,9 @@ // Write 1 to bit index n in this bit vector to set GPIODOUT bit n. // // Read value is 0. -#define AUX_AIODIO_GPIODOUTSET_IO7_0_W 8 -#define AUX_AIODIO_GPIODOUTSET_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODOUTSET_IO7_0_S 0 +#define AUX_AIODIO_GPIODOUTSET_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTSET_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTSET_IO7_0_S 0 //***************************************************************************** // @@ -439,9 +439,9 @@ // Write 1 to bit index n in this bit vector to clear GPIODOUT bit n. // // Read value is 0. -#define AUX_AIODIO_GPIODOUTCLR_IO7_0_W 8 -#define AUX_AIODIO_GPIODOUTCLR_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODOUTCLR_IO7_0_S 0 +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTCLR_IO7_0_S 0 //***************************************************************************** // @@ -453,9 +453,9 @@ // Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n. // // Read value is 0. -#define AUX_AIODIO_GPIODOUTTGL_IO7_0_W 8 -#define AUX_AIODIO_GPIODOUTTGL_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODOUTTGL_IO7_0_S 0 +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_W 8 +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODOUTTGL_IO7_0_S 0 //***************************************************************************** // @@ -473,9 +473,8 @@ // value in GPIODIN. // You must disable the digital input buffer for analog input or pins that // float to avoid current leakage. -#define AUX_AIODIO_GPIODIE_IO7_0_W 8 -#define AUX_AIODIO_GPIODIE_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODIE_IO7_0_S 0 - +#define AUX_AIODIO_GPIODIE_IO7_0_W 8 +#define AUX_AIODIO_GPIODIE_IO7_0_M 0x000000FF +#define AUX_AIODIO_GPIODIE_IO7_0_S 0 #endif // __AUX_AIODIO__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_anaif.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_anaif.h index f96db07..52a8103 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_anaif.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_anaif.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_anaif_h -* Revised: 2017-05-30 11:42:02 +0200 (Tue, 30 May 2017) -* Revision: 49074 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_anaif_h + * Revised: 2017-05-30 11:42:02 +0200 (Tue, 30 May 2017) + * Revision: 49074 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_ANAIF_H__ #define __HW_AUX_ANAIF_H__ @@ -44,19 +44,19 @@ // //***************************************************************************** // ADC Control -#define AUX_ANAIF_O_ADCCTL 0x00000010 +#define AUX_ANAIF_O_ADCCTL 0x00000010 // ADC FIFO Status -#define AUX_ANAIF_O_ADCFIFOSTAT 0x00000014 +#define AUX_ANAIF_O_ADCFIFOSTAT 0x00000014 // ADC FIFO -#define AUX_ANAIF_O_ADCFIFO 0x00000018 +#define AUX_ANAIF_O_ADCFIFO 0x00000018 // ADC Trigger -#define AUX_ANAIF_O_ADCTRIG 0x0000001C +#define AUX_ANAIF_O_ADCTRIG 0x0000001C // Current Source Control -#define AUX_ANAIF_O_ISRCCTL 0x00000020 +#define AUX_ANAIF_O_ISRCCTL 0x00000020 //***************************************************************************** // @@ -69,12 +69,12 @@ // ENUMs: // FALL Set ADC trigger on falling edge of event source. // RISE Set ADC trigger on rising edge of event source. -#define AUX_ANAIF_ADCCTL_START_POL 0x00002000 -#define AUX_ANAIF_ADCCTL_START_POL_BITN 13 -#define AUX_ANAIF_ADCCTL_START_POL_M 0x00002000 -#define AUX_ANAIF_ADCCTL_START_POL_S 13 -#define AUX_ANAIF_ADCCTL_START_POL_FALL 0x00002000 -#define AUX_ANAIF_ADCCTL_START_POL_RISE 0x00000000 +#define AUX_ANAIF_ADCCTL_START_POL 0x00002000 +#define AUX_ANAIF_ADCCTL_START_POL_BITN 13 +#define AUX_ANAIF_ADCCTL_START_POL_M 0x00002000 +#define AUX_ANAIF_ADCCTL_START_POL_S 13 +#define AUX_ANAIF_ADCCTL_START_POL_FALL 0x00002000 +#define AUX_ANAIF_ADCCTL_START_POL_RISE 0x00000000 // Field: [12:8] START_SRC // @@ -115,41 +115,41 @@ // AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB // AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA // RTC_CH2_EV AUX_EVCTL:EVSTAT0.AON_RTC_CH2 -#define AUX_ANAIF_ADCCTL_START_SRC_W 5 -#define AUX_ANAIF_ADCCTL_START_SRC_M 0x00001F00 -#define AUX_ANAIF_ADCCTL_START_SRC_S 8 -#define AUX_ANAIF_ADCCTL_START_SRC_ADC_IRQ 0x00001F00 -#define AUX_ANAIF_ADCCTL_START_SRC_MCU_EV 0x00001E00 -#define AUX_ANAIF_ADCCTL_START_SRC_ACLK_REF 0x00001D00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO15 0x00001C00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO14 0x00001B00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO13 0x00001A00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO12 0x00001900 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO11 0x00001800 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO10 0x00001700 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO9 0x00001600 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO8 0x00001500 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO7 0x00001400 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO6 0x00001300 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO5 0x00001200 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO4 0x00001100 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO3 0x00001000 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO2 0x00000F00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO1 0x00000E00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO0 0x00000D00 -#define AUX_ANAIF_ADCCTL_START_SRC_AON_PROG_WU 0x00000C00 -#define AUX_ANAIF_ADCCTL_START_SRC_AON_SW 0x00000B00 -#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT1 0x00000A00 -#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT0 0x00000900 -#define AUX_ANAIF_ADCCTL_START_SRC_RESERVED1 0x00000800 -#define AUX_ANAIF_ADCCTL_START_SRC_RESERVED0 0x00000700 -#define AUX_ANAIF_ADCCTL_START_SRC_SMPH_AUTOTAKE_DONE 0x00000600 -#define AUX_ANAIF_ADCCTL_START_SRC_TIMER1_EV 0x00000500 -#define AUX_ANAIF_ADCCTL_START_SRC_TIMER0_EV 0x00000400 -#define AUX_ANAIF_ADCCTL_START_SRC_TDC_DONE 0x00000300 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPB 0x00000200 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPA 0x00000100 -#define AUX_ANAIF_ADCCTL_START_SRC_RTC_CH2_EV 0x00000000 +#define AUX_ANAIF_ADCCTL_START_SRC_W 5 +#define AUX_ANAIF_ADCCTL_START_SRC_M 0x00001F00 +#define AUX_ANAIF_ADCCTL_START_SRC_S 8 +#define AUX_ANAIF_ADCCTL_START_SRC_ADC_IRQ 0x00001F00 +#define AUX_ANAIF_ADCCTL_START_SRC_MCU_EV 0x00001E00 +#define AUX_ANAIF_ADCCTL_START_SRC_ACLK_REF 0x00001D00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO15 0x00001C00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO14 0x00001B00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO13 0x00001A00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO12 0x00001900 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO11 0x00001800 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO10 0x00001700 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO9 0x00001600 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO8 0x00001500 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO7 0x00001400 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO6 0x00001300 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO5 0x00001200 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO4 0x00001100 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO3 0x00001000 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO2 0x00000F00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO1 0x00000E00 +#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO0 0x00000D00 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_PROG_WU 0x00000C00 +#define AUX_ANAIF_ADCCTL_START_SRC_AON_SW 0x00000B00 +#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT1 0x00000A00 +#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT0 0x00000900 +#define AUX_ANAIF_ADCCTL_START_SRC_RESERVED1 0x00000800 +#define AUX_ANAIF_ADCCTL_START_SRC_RESERVED0 0x00000700 +#define AUX_ANAIF_ADCCTL_START_SRC_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_ANAIF_ADCCTL_START_SRC_TIMER1_EV 0x00000500 +#define AUX_ANAIF_ADCCTL_START_SRC_TIMER0_EV 0x00000400 +#define AUX_ANAIF_ADCCTL_START_SRC_TDC_DONE 0x00000300 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPB 0x00000200 +#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPA 0x00000100 +#define AUX_ANAIF_ADCCTL_START_SRC_RTC_CH2_EV 0x00000000 // Field: [1:0] CMD // @@ -167,12 +167,12 @@ // clock cycles before it sets CMD to EN or DIS. // EN Enable ADC interface. // DIS Disable ADC interface. -#define AUX_ANAIF_ADCCTL_CMD_W 2 -#define AUX_ANAIF_ADCCTL_CMD_M 0x00000003 -#define AUX_ANAIF_ADCCTL_CMD_S 0 -#define AUX_ANAIF_ADCCTL_CMD_FLUSH 0x00000003 -#define AUX_ANAIF_ADCCTL_CMD_EN 0x00000001 -#define AUX_ANAIF_ADCCTL_CMD_DIS 0x00000000 +#define AUX_ANAIF_ADCCTL_CMD_W 2 +#define AUX_ANAIF_ADCCTL_CMD_M 0x00000003 +#define AUX_ANAIF_ADCCTL_CMD_S 0 +#define AUX_ANAIF_ADCCTL_CMD_FLUSH 0x00000003 +#define AUX_ANAIF_ADCCTL_CMD_EN 0x00000001 +#define AUX_ANAIF_ADCCTL_CMD_DIS 0x00000000 //***************************************************************************** // @@ -188,10 +188,10 @@ // // When the flag is set, the ADC FIFO write pointer is static. It is not // possible to add more samples to the ADC FIFO. Flush FIFO to clear the flag. -#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW 0x00000010 -#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_BITN 4 -#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M 0x00000010 -#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_S 4 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW 0x00000010 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_BITN 4 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M 0x00000010 +#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_S 4 // Field: [3] UNDERFLOW // @@ -202,10 +202,10 @@ // // When the flag is set, the ADC FIFO read pointer is static. Read returns the // previous sample that was read. Flush FIFO to clear the flag. -#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW 0x00000008 -#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_BITN 3 -#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M 0x00000008 -#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_S 3 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW 0x00000008 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_BITN 3 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M 0x00000008 +#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_S 3 // Field: [2] FULL // @@ -216,10 +216,10 @@ // // When the flag is set, it is not possible to add more samples to the ADC // FIFO. An attempt to add samples sets the OVERFLOW flag. -#define AUX_ANAIF_ADCFIFOSTAT_FULL 0x00000004 -#define AUX_ANAIF_ADCFIFOSTAT_FULL_BITN 2 -#define AUX_ANAIF_ADCFIFOSTAT_FULL_M 0x00000004 -#define AUX_ANAIF_ADCFIFOSTAT_FULL_S 2 +#define AUX_ANAIF_ADCFIFOSTAT_FULL 0x00000004 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_BITN 2 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_M 0x00000004 +#define AUX_ANAIF_ADCFIFOSTAT_FULL_S 2 // Field: [1] ALMOST_FULL // @@ -228,10 +228,10 @@ // 0: There are less than 3 samples in the FIFO, or the FIFO is full. The FULL // flag is also asserted in the latter case. // 1: There are 3 samples in the FIFO, there is room for one more sample. -#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL 0x00000002 -#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_BITN 1 -#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M 0x00000002 -#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_S 1 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL 0x00000002 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_BITN 1 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M 0x00000002 +#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_S 1 // Field: [0] EMPTY // @@ -242,10 +242,10 @@ // // When the flag is set, read returns the previous sample that was read and // sets the UNDERFLOW flag. -#define AUX_ANAIF_ADCFIFOSTAT_EMPTY 0x00000001 -#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_BITN 0 -#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_M 0x00000001 -#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_S 0 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY 0x00000001 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_BITN 0 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_M 0x00000001 +#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_S 0 //***************************************************************************** // @@ -262,9 +262,9 @@ // Write: // Write dummy sample to FIFO. This is useful for code development when you do // not have real ADC samples. -#define AUX_ANAIF_ADCFIFO_DATA_W 12 -#define AUX_ANAIF_ADCFIFO_DATA_M 0x00000FFF -#define AUX_ANAIF_ADCFIFO_DATA_S 0 +#define AUX_ANAIF_ADCFIFO_DATA_W 12 +#define AUX_ANAIF_ADCFIFO_DATA_M 0x00000FFF +#define AUX_ANAIF_ADCFIFO_DATA_S 0 //***************************************************************************** // @@ -280,10 +280,10 @@ // // To manually trigger the ADC, you must set ADCCTL.START_SRC to NO_EVENT to // avoid conflict with event-driven ADC trigger. -#define AUX_ANAIF_ADCTRIG_START 0x00000001 -#define AUX_ANAIF_ADCTRIG_START_BITN 0 -#define AUX_ANAIF_ADCTRIG_START_M 0x00000001 -#define AUX_ANAIF_ADCTRIG_START_S 0 +#define AUX_ANAIF_ADCTRIG_START 0x00000001 +#define AUX_ANAIF_ADCTRIG_START_BITN 0 +#define AUX_ANAIF_ADCTRIG_START_M 0x00000001 +#define AUX_ANAIF_ADCTRIG_START_S 0 //***************************************************************************** // @@ -296,10 +296,9 @@ // // 0: ISRC drives 0 uA. // 1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN. -#define AUX_ANAIF_ISRCCTL_RESET_N 0x00000001 -#define AUX_ANAIF_ISRCCTL_RESET_N_BITN 0 -#define AUX_ANAIF_ISRCCTL_RESET_N_M 0x00000001 -#define AUX_ANAIF_ISRCCTL_RESET_N_S 0 - +#define AUX_ANAIF_ISRCCTL_RESET_N 0x00000001 +#define AUX_ANAIF_ISRCCTL_RESET_N_BITN 0 +#define AUX_ANAIF_ISRCCTL_RESET_N_M 0x00000001 +#define AUX_ANAIF_ISRCCTL_RESET_N_S 0 #endif // __AUX_ANAIF__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_evctl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_evctl.h index 0969dfc..188554b 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_evctl.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_evctl.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_evctl_h -* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) -* Revision: 49005 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_evctl_h + * Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) + * Revision: 49005 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_EVCTL_H__ #define __HW_AUX_EVCTL_H__ @@ -44,52 +44,52 @@ // //***************************************************************************** // Vector Configuration 0 -#define AUX_EVCTL_O_VECCFG0 0x00000000 +#define AUX_EVCTL_O_VECCFG0 0x00000000 // Vector Configuration 1 -#define AUX_EVCTL_O_VECCFG1 0x00000004 +#define AUX_EVCTL_O_VECCFG1 0x00000004 // Sensor Controller Engine Wait Event Selection -#define AUX_EVCTL_O_SCEWEVSEL 0x00000008 +#define AUX_EVCTL_O_SCEWEVSEL 0x00000008 // Events To AON Flags -#define AUX_EVCTL_O_EVTOAONFLAGS 0x0000000C +#define AUX_EVCTL_O_EVTOAONFLAGS 0x0000000C // Events To AON Polarity -#define AUX_EVCTL_O_EVTOAONPOL 0x00000010 +#define AUX_EVCTL_O_EVTOAONPOL 0x00000010 // Direct Memory Access Control -#define AUX_EVCTL_O_DMACTL 0x00000014 +#define AUX_EVCTL_O_DMACTL 0x00000014 // Software Event Set -#define AUX_EVCTL_O_SWEVSET 0x00000018 +#define AUX_EVCTL_O_SWEVSET 0x00000018 // Event Status 0 -#define AUX_EVCTL_O_EVSTAT0 0x0000001C +#define AUX_EVCTL_O_EVSTAT0 0x0000001C // Event Status 1 -#define AUX_EVCTL_O_EVSTAT1 0x00000020 +#define AUX_EVCTL_O_EVSTAT1 0x00000020 // Event To MCU Polarity -#define AUX_EVCTL_O_EVTOMCUPOL 0x00000024 +#define AUX_EVCTL_O_EVTOMCUPOL 0x00000024 // Events to MCU Flags -#define AUX_EVCTL_O_EVTOMCUFLAGS 0x00000028 +#define AUX_EVCTL_O_EVTOMCUFLAGS 0x00000028 // Combined Event To MCU Mask -#define AUX_EVCTL_O_COMBEVTOMCUMASK 0x0000002C +#define AUX_EVCTL_O_COMBEVTOMCUMASK 0x0000002C // Vector Flags -#define AUX_EVCTL_O_VECFLAGS 0x00000034 +#define AUX_EVCTL_O_VECFLAGS 0x00000034 // Events To MCU Flags Clear -#define AUX_EVCTL_O_EVTOMCUFLAGSCLR 0x00000038 +#define AUX_EVCTL_O_EVTOMCUFLAGSCLR 0x00000038 // Events To AON Clear -#define AUX_EVCTL_O_EVTOAONFLAGSCLR 0x0000003C +#define AUX_EVCTL_O_EVTOAONFLAGSCLR 0x0000003C // Vector Flags Clear -#define AUX_EVCTL_O_VECFLAGSCLR 0x00000040 +#define AUX_EVCTL_O_VECFLAGSCLR 0x00000040 //***************************************************************************** // @@ -107,12 +107,12 @@ // ENUMs: // FALL Falling edge triggers vector 1 execution. // RISE Rising edge triggers vector 1 execution. -#define AUX_EVCTL_VECCFG0_VEC1_POL 0x00004000 -#define AUX_EVCTL_VECCFG0_VEC1_POL_BITN 14 -#define AUX_EVCTL_VECCFG0_VEC1_POL_M 0x00004000 -#define AUX_EVCTL_VECCFG0_VEC1_POL_S 14 -#define AUX_EVCTL_VECCFG0_VEC1_POL_FALL 0x00004000 -#define AUX_EVCTL_VECCFG0_VEC1_POL_RISE 0x00000000 +#define AUX_EVCTL_VECCFG0_VEC1_POL 0x00004000 +#define AUX_EVCTL_VECCFG0_VEC1_POL_BITN 14 +#define AUX_EVCTL_VECCFG0_VEC1_POL_M 0x00004000 +#define AUX_EVCTL_VECCFG0_VEC1_POL_S 14 +#define AUX_EVCTL_VECCFG0_VEC1_POL_FALL 0x00004000 +#define AUX_EVCTL_VECCFG0_VEC1_POL_RISE 0x00000000 // Field: [13] VEC1_EN // @@ -125,12 +125,12 @@ // ENUMs: // EN Enable vector 1 trigger. // DIS Disable vector 1 trigger. -#define AUX_EVCTL_VECCFG0_VEC1_EN 0x00002000 -#define AUX_EVCTL_VECCFG0_VEC1_EN_BITN 13 -#define AUX_EVCTL_VECCFG0_VEC1_EN_M 0x00002000 -#define AUX_EVCTL_VECCFG0_VEC1_EN_S 13 -#define AUX_EVCTL_VECCFG0_VEC1_EN_EN 0x00002000 -#define AUX_EVCTL_VECCFG0_VEC1_EN_DIS 0x00000000 +#define AUX_EVCTL_VECCFG0_VEC1_EN 0x00002000 +#define AUX_EVCTL_VECCFG0_VEC1_EN_BITN 13 +#define AUX_EVCTL_VECCFG0_VEC1_EN_M 0x00002000 +#define AUX_EVCTL_VECCFG0_VEC1_EN_S 13 +#define AUX_EVCTL_VECCFG0_VEC1_EN_EN 0x00002000 +#define AUX_EVCTL_VECCFG0_VEC1_EN_DIS 0x00000000 // Field: [12:8] VEC1_EV // @@ -168,41 +168,41 @@ // AUX_COMPB EVSTAT0.AUX_COMPB // AUX_COMPA EVSTAT0.AUX_COMPA // AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 -#define AUX_EVCTL_VECCFG0_VEC1_EV_W 5 -#define AUX_EVCTL_VECCFG0_VEC1_EV_M 0x00001F00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_S 8 -#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_IRQ 0x00001F00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_MCU_EV 0x00001E00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_ACLK_REF 0x00001D00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO15 0x00001C00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO14 0x00001B00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO13 0x00001A00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO12 0x00001900 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO11 0x00001800 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO10 0x00001700 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO9 0x00001600 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO8 0x00001500 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO7 0x00001400 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO6 0x00001300 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO5 0x00001200 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO4 0x00001100 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO3 0x00001000 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO2 0x00000F00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO1 0x00000E00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO0 0x00000D00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_PROG_WU 0x00000C00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_SW 0x00000B00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_OBSMUX1 0x00000A00 -#define AUX_EVCTL_VECCFG0_VEC1_EV_OBSMUX0 0x00000900 -#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_FIFO_ALMOST_FULL 0x00000800 -#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_DONE 0x00000700 -#define AUX_EVCTL_VECCFG0_VEC1_EV_SMPH_AUTOTAKE_DONE 0x00000600 -#define AUX_EVCTL_VECCFG0_VEC1_EV_TIMER1_EV 0x00000500 -#define AUX_EVCTL_VECCFG0_VEC1_EV_TIMER0_EV 0x00000400 -#define AUX_EVCTL_VECCFG0_VEC1_EV_TDC_DONE 0x00000300 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUX_COMPB 0x00000200 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AUX_COMPA 0x00000100 -#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_RTC_CH2 0x00000000 +#define AUX_EVCTL_VECCFG0_VEC1_EV_W 5 +#define AUX_EVCTL_VECCFG0_VEC1_EV_M 0x00001F00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_S 8 +#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_IRQ 0x00001F00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_MCU_EV 0x00001E00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_ACLK_REF 0x00001D00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO15 0x00001C00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO14 0x00001B00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO13 0x00001A00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO12 0x00001900 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO11 0x00001800 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO10 0x00001700 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO9 0x00001600 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO8 0x00001500 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO7 0x00001400 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO6 0x00001300 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO5 0x00001200 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO4 0x00001100 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO3 0x00001000 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO2 0x00000F00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO1 0x00000E00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUXIO0 0x00000D00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_PROG_WU 0x00000C00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_SW 0x00000B00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_OBSMUX1 0x00000A00 +#define AUX_EVCTL_VECCFG0_VEC1_EV_OBSMUX0 0x00000900 +#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_FIFO_ALMOST_FULL 0x00000800 +#define AUX_EVCTL_VECCFG0_VEC1_EV_ADC_DONE 0x00000700 +#define AUX_EVCTL_VECCFG0_VEC1_EV_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_EVCTL_VECCFG0_VEC1_EV_TIMER1_EV 0x00000500 +#define AUX_EVCTL_VECCFG0_VEC1_EV_TIMER0_EV 0x00000400 +#define AUX_EVCTL_VECCFG0_VEC1_EV_TDC_DONE 0x00000300 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUX_COMPB 0x00000200 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AUX_COMPA 0x00000100 +#define AUX_EVCTL_VECCFG0_VEC1_EV_AON_RTC_CH2 0x00000000 // Field: [6] VEC0_POL // @@ -215,12 +215,12 @@ // ENUMs: // FALL Falling edge triggers vector 0 execution. // RISE Rising edge triggers vector 0 execution. -#define AUX_EVCTL_VECCFG0_VEC0_POL 0x00000040 -#define AUX_EVCTL_VECCFG0_VEC0_POL_BITN 6 -#define AUX_EVCTL_VECCFG0_VEC0_POL_M 0x00000040 -#define AUX_EVCTL_VECCFG0_VEC0_POL_S 6 -#define AUX_EVCTL_VECCFG0_VEC0_POL_FALL 0x00000040 -#define AUX_EVCTL_VECCFG0_VEC0_POL_RISE 0x00000000 +#define AUX_EVCTL_VECCFG0_VEC0_POL 0x00000040 +#define AUX_EVCTL_VECCFG0_VEC0_POL_BITN 6 +#define AUX_EVCTL_VECCFG0_VEC0_POL_M 0x00000040 +#define AUX_EVCTL_VECCFG0_VEC0_POL_S 6 +#define AUX_EVCTL_VECCFG0_VEC0_POL_FALL 0x00000040 +#define AUX_EVCTL_VECCFG0_VEC0_POL_RISE 0x00000000 // Field: [5] VEC0_EN // @@ -231,12 +231,12 @@ // ENUMs: // EN Enable vector 0 trigger. // DIS Disable vector 0 trigger. -#define AUX_EVCTL_VECCFG0_VEC0_EN 0x00000020 -#define AUX_EVCTL_VECCFG0_VEC0_EN_BITN 5 -#define AUX_EVCTL_VECCFG0_VEC0_EN_M 0x00000020 -#define AUX_EVCTL_VECCFG0_VEC0_EN_S 5 -#define AUX_EVCTL_VECCFG0_VEC0_EN_EN 0x00000020 -#define AUX_EVCTL_VECCFG0_VEC0_EN_DIS 0x00000000 +#define AUX_EVCTL_VECCFG0_VEC0_EN 0x00000020 +#define AUX_EVCTL_VECCFG0_VEC0_EN_BITN 5 +#define AUX_EVCTL_VECCFG0_VEC0_EN_M 0x00000020 +#define AUX_EVCTL_VECCFG0_VEC0_EN_S 5 +#define AUX_EVCTL_VECCFG0_VEC0_EN_EN 0x00000020 +#define AUX_EVCTL_VECCFG0_VEC0_EN_DIS 0x00000000 // Field: [4:0] VEC0_EV // @@ -274,41 +274,41 @@ // AUX_COMPB EVSTAT0.AUX_COMPB // AUX_COMPA EVSTAT0.AUX_COMPA // AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 -#define AUX_EVCTL_VECCFG0_VEC0_EV_W 5 -#define AUX_EVCTL_VECCFG0_VEC0_EV_M 0x0000001F -#define AUX_EVCTL_VECCFG0_VEC0_EV_S 0 -#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_IRQ 0x0000001F -#define AUX_EVCTL_VECCFG0_VEC0_EV_MCU_EV 0x0000001E -#define AUX_EVCTL_VECCFG0_VEC0_EV_ACLK_REF 0x0000001D -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO15 0x0000001C -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO14 0x0000001B -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO13 0x0000001A -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO12 0x00000019 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO11 0x00000018 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO10 0x00000017 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO9 0x00000016 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO8 0x00000015 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO7 0x00000014 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO6 0x00000013 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO5 0x00000012 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO4 0x00000011 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO3 0x00000010 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO2 0x0000000F -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO1 0x0000000E -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO0 0x0000000D -#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_PROG_WU 0x0000000C -#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_SW 0x0000000B -#define AUX_EVCTL_VECCFG0_VEC0_EV_OBSMUX1 0x0000000A -#define AUX_EVCTL_VECCFG0_VEC0_EV_OBSMUX0 0x00000009 -#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_FIFO_ALMOST_FULL 0x00000008 -#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_DONE 0x00000007 -#define AUX_EVCTL_VECCFG0_VEC0_EV_SMPH_AUTOTAKE_DONE 0x00000006 -#define AUX_EVCTL_VECCFG0_VEC0_EV_TIMER1_EV 0x00000005 -#define AUX_EVCTL_VECCFG0_VEC0_EV_TIMER0_EV 0x00000004 -#define AUX_EVCTL_VECCFG0_VEC0_EV_TDC_DONE 0x00000003 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUX_COMPB 0x00000002 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AUX_COMPA 0x00000001 -#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_RTC_CH2 0x00000000 +#define AUX_EVCTL_VECCFG0_VEC0_EV_W 5 +#define AUX_EVCTL_VECCFG0_VEC0_EV_M 0x0000001F +#define AUX_EVCTL_VECCFG0_VEC0_EV_S 0 +#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_IRQ 0x0000001F +#define AUX_EVCTL_VECCFG0_VEC0_EV_MCU_EV 0x0000001E +#define AUX_EVCTL_VECCFG0_VEC0_EV_ACLK_REF 0x0000001D +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO15 0x0000001C +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO14 0x0000001B +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO13 0x0000001A +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO12 0x00000019 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO11 0x00000018 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO10 0x00000017 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO9 0x00000016 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO8 0x00000015 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO7 0x00000014 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO6 0x00000013 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO5 0x00000012 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO4 0x00000011 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO3 0x00000010 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO2 0x0000000F +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO1 0x0000000E +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUXIO0 0x0000000D +#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_PROG_WU 0x0000000C +#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_SW 0x0000000B +#define AUX_EVCTL_VECCFG0_VEC0_EV_OBSMUX1 0x0000000A +#define AUX_EVCTL_VECCFG0_VEC0_EV_OBSMUX0 0x00000009 +#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_EVCTL_VECCFG0_VEC0_EV_ADC_DONE 0x00000007 +#define AUX_EVCTL_VECCFG0_VEC0_EV_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_EVCTL_VECCFG0_VEC0_EV_TIMER1_EV 0x00000005 +#define AUX_EVCTL_VECCFG0_VEC0_EV_TIMER0_EV 0x00000004 +#define AUX_EVCTL_VECCFG0_VEC0_EV_TDC_DONE 0x00000003 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUX_COMPB 0x00000002 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AUX_COMPA 0x00000001 +#define AUX_EVCTL_VECCFG0_VEC0_EV_AON_RTC_CH2 0x00000000 //***************************************************************************** // @@ -326,12 +326,12 @@ // ENUMs: // FALL Falling edge triggers vector 3 execution. // RISE Rising edge triggers vector 3 execution. -#define AUX_EVCTL_VECCFG1_VEC3_POL 0x00004000 -#define AUX_EVCTL_VECCFG1_VEC3_POL_BITN 14 -#define AUX_EVCTL_VECCFG1_VEC3_POL_M 0x00004000 -#define AUX_EVCTL_VECCFG1_VEC3_POL_S 14 -#define AUX_EVCTL_VECCFG1_VEC3_POL_FALL 0x00004000 -#define AUX_EVCTL_VECCFG1_VEC3_POL_RISE 0x00000000 +#define AUX_EVCTL_VECCFG1_VEC3_POL 0x00004000 +#define AUX_EVCTL_VECCFG1_VEC3_POL_BITN 14 +#define AUX_EVCTL_VECCFG1_VEC3_POL_M 0x00004000 +#define AUX_EVCTL_VECCFG1_VEC3_POL_S 14 +#define AUX_EVCTL_VECCFG1_VEC3_POL_FALL 0x00004000 +#define AUX_EVCTL_VECCFG1_VEC3_POL_RISE 0x00000000 // Field: [13] VEC3_EN // @@ -344,12 +344,12 @@ // ENUMs: // EN Enable vector 3 trigger. // DIS Disable vector 3 trigger. -#define AUX_EVCTL_VECCFG1_VEC3_EN 0x00002000 -#define AUX_EVCTL_VECCFG1_VEC3_EN_BITN 13 -#define AUX_EVCTL_VECCFG1_VEC3_EN_M 0x00002000 -#define AUX_EVCTL_VECCFG1_VEC3_EN_S 13 -#define AUX_EVCTL_VECCFG1_VEC3_EN_EN 0x00002000 -#define AUX_EVCTL_VECCFG1_VEC3_EN_DIS 0x00000000 +#define AUX_EVCTL_VECCFG1_VEC3_EN 0x00002000 +#define AUX_EVCTL_VECCFG1_VEC3_EN_BITN 13 +#define AUX_EVCTL_VECCFG1_VEC3_EN_M 0x00002000 +#define AUX_EVCTL_VECCFG1_VEC3_EN_S 13 +#define AUX_EVCTL_VECCFG1_VEC3_EN_EN 0x00002000 +#define AUX_EVCTL_VECCFG1_VEC3_EN_DIS 0x00000000 // Field: [12:8] VEC3_EV // @@ -387,41 +387,41 @@ // AUX_COMPB EVSTAT0.AUX_COMPB // AUX_COMPA EVSTAT0.AUX_COMPA // AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 -#define AUX_EVCTL_VECCFG1_VEC3_EV_W 5 -#define AUX_EVCTL_VECCFG1_VEC3_EV_M 0x00001F00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_S 8 -#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_IRQ 0x00001F00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_MCU_EV 0x00001E00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_ACLK_REF 0x00001D00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO15 0x00001C00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO14 0x00001B00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO13 0x00001A00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO12 0x00001900 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO11 0x00001800 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO10 0x00001700 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO9 0x00001600 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO8 0x00001500 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO7 0x00001400 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO6 0x00001300 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO5 0x00001200 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO4 0x00001100 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO3 0x00001000 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO2 0x00000F00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO1 0x00000E00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO0 0x00000D00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_PROG_WU 0x00000C00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_SW 0x00000B00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_OBSMUX1 0x00000A00 -#define AUX_EVCTL_VECCFG1_VEC3_EV_OBSMUX0 0x00000900 -#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_FIFO_ALMOST_FULL 0x00000800 -#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_DONE 0x00000700 -#define AUX_EVCTL_VECCFG1_VEC3_EV_SMPH_AUTOTAKE_DONE 0x00000600 -#define AUX_EVCTL_VECCFG1_VEC3_EV_TIMER1_EV 0x00000500 -#define AUX_EVCTL_VECCFG1_VEC3_EV_TIMER0_EV 0x00000400 -#define AUX_EVCTL_VECCFG1_VEC3_EV_TDC_DONE 0x00000300 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUX_COMPB 0x00000200 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AUX_COMPA 0x00000100 -#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_RTC_CH2 0x00000000 +#define AUX_EVCTL_VECCFG1_VEC3_EV_W 5 +#define AUX_EVCTL_VECCFG1_VEC3_EV_M 0x00001F00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_S 8 +#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_IRQ 0x00001F00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_MCU_EV 0x00001E00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_ACLK_REF 0x00001D00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO15 0x00001C00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO14 0x00001B00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO13 0x00001A00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO12 0x00001900 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO11 0x00001800 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO10 0x00001700 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO9 0x00001600 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO8 0x00001500 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO7 0x00001400 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO6 0x00001300 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO5 0x00001200 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO4 0x00001100 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO3 0x00001000 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO2 0x00000F00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO1 0x00000E00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUXIO0 0x00000D00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_PROG_WU 0x00000C00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_SW 0x00000B00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_OBSMUX1 0x00000A00 +#define AUX_EVCTL_VECCFG1_VEC3_EV_OBSMUX0 0x00000900 +#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_FIFO_ALMOST_FULL 0x00000800 +#define AUX_EVCTL_VECCFG1_VEC3_EV_ADC_DONE 0x00000700 +#define AUX_EVCTL_VECCFG1_VEC3_EV_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_EVCTL_VECCFG1_VEC3_EV_TIMER1_EV 0x00000500 +#define AUX_EVCTL_VECCFG1_VEC3_EV_TIMER0_EV 0x00000400 +#define AUX_EVCTL_VECCFG1_VEC3_EV_TDC_DONE 0x00000300 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUX_COMPB 0x00000200 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AUX_COMPA 0x00000100 +#define AUX_EVCTL_VECCFG1_VEC3_EV_AON_RTC_CH2 0x00000000 // Field: [6] VEC2_POL // @@ -434,12 +434,12 @@ // ENUMs: // FALL Falling edge triggers vector 2 execution. // RISE Rising edge triggers vector 2 execution. -#define AUX_EVCTL_VECCFG1_VEC2_POL 0x00000040 -#define AUX_EVCTL_VECCFG1_VEC2_POL_BITN 6 -#define AUX_EVCTL_VECCFG1_VEC2_POL_M 0x00000040 -#define AUX_EVCTL_VECCFG1_VEC2_POL_S 6 -#define AUX_EVCTL_VECCFG1_VEC2_POL_FALL 0x00000040 -#define AUX_EVCTL_VECCFG1_VEC2_POL_RISE 0x00000000 +#define AUX_EVCTL_VECCFG1_VEC2_POL 0x00000040 +#define AUX_EVCTL_VECCFG1_VEC2_POL_BITN 6 +#define AUX_EVCTL_VECCFG1_VEC2_POL_M 0x00000040 +#define AUX_EVCTL_VECCFG1_VEC2_POL_S 6 +#define AUX_EVCTL_VECCFG1_VEC2_POL_FALL 0x00000040 +#define AUX_EVCTL_VECCFG1_VEC2_POL_RISE 0x00000000 // Field: [5] VEC2_EN // @@ -452,12 +452,12 @@ // ENUMs: // EN Enable vector 2 trigger. // DIS Disable vector 2 trigger. -#define AUX_EVCTL_VECCFG1_VEC2_EN 0x00000020 -#define AUX_EVCTL_VECCFG1_VEC2_EN_BITN 5 -#define AUX_EVCTL_VECCFG1_VEC2_EN_M 0x00000020 -#define AUX_EVCTL_VECCFG1_VEC2_EN_S 5 -#define AUX_EVCTL_VECCFG1_VEC2_EN_EN 0x00000020 -#define AUX_EVCTL_VECCFG1_VEC2_EN_DIS 0x00000000 +#define AUX_EVCTL_VECCFG1_VEC2_EN 0x00000020 +#define AUX_EVCTL_VECCFG1_VEC2_EN_BITN 5 +#define AUX_EVCTL_VECCFG1_VEC2_EN_M 0x00000020 +#define AUX_EVCTL_VECCFG1_VEC2_EN_S 5 +#define AUX_EVCTL_VECCFG1_VEC2_EN_EN 0x00000020 +#define AUX_EVCTL_VECCFG1_VEC2_EN_DIS 0x00000000 // Field: [4:0] VEC2_EV // @@ -495,41 +495,41 @@ // AUX_COMPB EVSTAT0.AUX_COMPB // AUX_COMPA EVSTAT0.AUX_COMPA // AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 -#define AUX_EVCTL_VECCFG1_VEC2_EV_W 5 -#define AUX_EVCTL_VECCFG1_VEC2_EV_M 0x0000001F -#define AUX_EVCTL_VECCFG1_VEC2_EV_S 0 -#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_IRQ 0x0000001F -#define AUX_EVCTL_VECCFG1_VEC2_EV_MCU_EV 0x0000001E -#define AUX_EVCTL_VECCFG1_VEC2_EV_ACLK_REF 0x0000001D -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO15 0x0000001C -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO14 0x0000001B -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO13 0x0000001A -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO12 0x00000019 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO11 0x00000018 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO10 0x00000017 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO9 0x00000016 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO8 0x00000015 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO7 0x00000014 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO6 0x00000013 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO5 0x00000012 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO4 0x00000011 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO3 0x00000010 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO2 0x0000000F -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO1 0x0000000E -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO0 0x0000000D -#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_PROG_WU 0x0000000C -#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_SW 0x0000000B -#define AUX_EVCTL_VECCFG1_VEC2_EV_OBSMUX1 0x0000000A -#define AUX_EVCTL_VECCFG1_VEC2_EV_OBSMUX0 0x00000009 -#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_FIFO_ALMOST_FULL 0x00000008 -#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_DONE 0x00000007 -#define AUX_EVCTL_VECCFG1_VEC2_EV_SMPH_AUTOTAKE_DONE 0x00000006 -#define AUX_EVCTL_VECCFG1_VEC2_EV_TIMER1_EV 0x00000005 -#define AUX_EVCTL_VECCFG1_VEC2_EV_TIMER0_EV 0x00000004 -#define AUX_EVCTL_VECCFG1_VEC2_EV_TDC_DONE 0x00000003 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUX_COMPB 0x00000002 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AUX_COMPA 0x00000001 -#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_RTC_CH2 0x00000000 +#define AUX_EVCTL_VECCFG1_VEC2_EV_W 5 +#define AUX_EVCTL_VECCFG1_VEC2_EV_M 0x0000001F +#define AUX_EVCTL_VECCFG1_VEC2_EV_S 0 +#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_IRQ 0x0000001F +#define AUX_EVCTL_VECCFG1_VEC2_EV_MCU_EV 0x0000001E +#define AUX_EVCTL_VECCFG1_VEC2_EV_ACLK_REF 0x0000001D +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO15 0x0000001C +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO14 0x0000001B +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO13 0x0000001A +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO12 0x00000019 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO11 0x00000018 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO10 0x00000017 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO9 0x00000016 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO8 0x00000015 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO7 0x00000014 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO6 0x00000013 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO5 0x00000012 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO4 0x00000011 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO3 0x00000010 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO2 0x0000000F +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO1 0x0000000E +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUXIO0 0x0000000D +#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_PROG_WU 0x0000000C +#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_SW 0x0000000B +#define AUX_EVCTL_VECCFG1_VEC2_EV_OBSMUX1 0x0000000A +#define AUX_EVCTL_VECCFG1_VEC2_EV_OBSMUX0 0x00000009 +#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_EVCTL_VECCFG1_VEC2_EV_ADC_DONE 0x00000007 +#define AUX_EVCTL_VECCFG1_VEC2_EV_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_EVCTL_VECCFG1_VEC2_EV_TIMER1_EV 0x00000005 +#define AUX_EVCTL_VECCFG1_VEC2_EV_TIMER0_EV 0x00000004 +#define AUX_EVCTL_VECCFG1_VEC2_EV_TDC_DONE 0x00000003 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUX_COMPB 0x00000002 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AUX_COMPA 0x00000001 +#define AUX_EVCTL_VECCFG1_VEC2_EV_AON_RTC_CH2 0x00000000 //***************************************************************************** // @@ -572,41 +572,41 @@ // AUX_COMPB EVSTAT0.AUX_COMPB // AUX_COMPA EVSTAT0.AUX_COMPA // AON_RTC_CH2 EVSTAT0.AON_RTC_CH2 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_W 5 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_M 0x0000001F -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_S 0 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_IRQ 0x0000001F -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_MCU_EV 0x0000001E -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ACLK_REF 0x0000001D -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO15 0x0000001C -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO14 0x0000001B -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO13 0x0000001A -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO12 0x00000019 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO11 0x00000018 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO10 0x00000017 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO9 0x00000016 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO8 0x00000015 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO7 0x00000014 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO6 0x00000013 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO5 0x00000012 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO4 0x00000011 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO3 0x00000010 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO2 0x0000000F -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO1 0x0000000E -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO0 0x0000000D -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_PROG_WU 0x0000000C -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_SW 0x0000000B -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_OBSMUX1 0x0000000A -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_OBSMUX0 0x00000009 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_FIFO_ALMOST_FULL 0x00000008 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_DONE 0x00000007 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_SMPH_AUTOTAKE_DONE 0x00000006 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TIMER1_EV 0x00000005 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TIMER0_EV 0x00000004 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TDC_DONE 0x00000003 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUX_COMPB 0x00000002 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUX_COMPA 0x00000001 -#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_RTC_CH2 0x00000000 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_W 5 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_M 0x0000001F +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_S 0 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_IRQ 0x0000001F +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_MCU_EV 0x0000001E +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ACLK_REF 0x0000001D +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO15 0x0000001C +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO14 0x0000001B +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO13 0x0000001A +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO12 0x00000019 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO11 0x00000018 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO10 0x00000017 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO9 0x00000016 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO8 0x00000015 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO7 0x00000014 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO6 0x00000013 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO5 0x00000012 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO4 0x00000011 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO3 0x00000010 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO2 0x0000000F +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO1 0x0000000E +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUXIO0 0x0000000D +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_PROG_WU 0x0000000C +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_SW 0x0000000B +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_OBSMUX1 0x0000000A +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_OBSMUX0 0x00000009 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_ADC_DONE 0x00000007 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TIMER1_EV 0x00000005 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TIMER0_EV 0x00000004 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_TDC_DONE 0x00000003 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUX_COMPB 0x00000002 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AUX_COMPA 0x00000001 +#define AUX_EVCTL_SCEWEVSEL_WEV7_EV_AON_RTC_CH2 0x00000000 //***************************************************************************** // @@ -617,79 +617,79 @@ // // This event flag is set when level selected by EVTOAONPOL.TIMER1_EV occurs on // EVSTAT0.TIMER1_EV. -#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV 0x00000100 -#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_BITN 8 -#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_M 0x00000100 -#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_S 8 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER1_EV_S 8 // Field: [7] TIMER0_EV // // This event flag is set when level selected by EVTOAONPOL.TIMER0_EV occurs on // EVSTAT0.TIMER0_EV. -#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV 0x00000080 -#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_BITN 7 -#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_M 0x00000080 -#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_S 7 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGS_TIMER0_EV_S 7 // Field: [6] TDC_DONE // // This event flag is set when level selected by EVTOAONPOL.TDC_DONE occurs on // EVSTAT0.TDC_DONE. -#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE 0x00000040 -#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_BITN 6 -#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_S 6 +#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGS_TDC_DONE_S 6 // Field: [5] ADC_DONE // // This event flag is set when level selected by EVTOAONPOL.ADC_DONE occurs on // EVSTAT0.ADC_DONE. -#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE 0x00000020 -#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_BITN 5 -#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_M 0x00000020 -#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_S 5 +#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGS_ADC_DONE_S 5 // Field: [4] AUX_COMPB // // This event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on // EVSTAT0.AUX_COMPB. -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB 0x00000010 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_BITN 4 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_M 0x00000010 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_S 4 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_S 4 // Field: [3] AUX_COMPA // // This event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on // EVSTAT0.AUX_COMPA. -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA 0x00000008 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_BITN 3 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_M 0x00000008 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_S 3 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_S 3 // Field: [2] SWEV2 // // This event flag is set when software writes a 1 to SWEVSET.SWEV2. -#define AUX_EVCTL_EVTOAONFLAGS_SWEV2 0x00000004 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_BITN 2 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_M 0x00000004 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_S 2 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_BITN 2 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_M 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_S 2 // Field: [1] SWEV1 // // This event flag is set when software writes a 1 to SWEVSET.SWEV1. -#define AUX_EVCTL_EVTOAONFLAGS_SWEV1 0x00000002 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_BITN 1 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_M 0x00000002 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_S 1 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_BITN 1 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_M 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_S 1 // Field: [0] SWEV0 // // This event flag is set when software writes a 1 to SWEVSET.SWEV0. -#define AUX_EVCTL_EVTOAONFLAGS_SWEV0 0x00000001 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_BITN 0 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_M 0x00000001 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_S 0 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_BITN 0 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_M 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_S 0 //***************************************************************************** // @@ -702,12 +702,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV 0x00000100 -#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_BITN 8 -#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_M 0x00000100 -#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_S 8 -#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_LOW 0x00000100 -#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_HIGH 0x00000000 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_S 8 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_LOW 0x00000100 +#define AUX_EVCTL_EVTOAONPOL_TIMER1_EV_HIGH 0x00000000 // Field: [7] TIMER0_EV // @@ -715,12 +715,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV 0x00000080 -#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_BITN 7 -#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_M 0x00000080 -#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_S 7 -#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_LOW 0x00000080 -#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_HIGH 0x00000000 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_S 7 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_LOW 0x00000080 +#define AUX_EVCTL_EVTOAONPOL_TIMER0_EV_HIGH 0x00000000 // Field: [6] TDC_DONE // @@ -728,12 +728,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOAONPOL_TDC_DONE 0x00000040 -#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_BITN 6 -#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_S 6 -#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_LOW 0x00000040 -#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_HIGH 0x00000000 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_S 6 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_LOW 0x00000040 +#define AUX_EVCTL_EVTOAONPOL_TDC_DONE_HIGH 0x00000000 // Field: [5] ADC_DONE // @@ -741,12 +741,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOAONPOL_ADC_DONE 0x00000020 -#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_BITN 5 -#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_M 0x00000020 -#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_S 5 -#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_LOW 0x00000020 -#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_HIGH 0x00000000 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_S 5 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_LOW 0x00000020 +#define AUX_EVCTL_EVTOAONPOL_ADC_DONE_HIGH 0x00000000 // Field: [4] AUX_COMPB // @@ -754,12 +754,12 @@ // ENUMs: // LOW Falling edge // HIGH Rising edge -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB 0x00000010 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_BITN 4 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_M 0x00000010 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_S 4 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_LOW 0x00000010 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_HIGH 0x00000000 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_S 4 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_LOW 0x00000010 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_HIGH 0x00000000 // Field: [3] AUX_COMPA // @@ -767,12 +767,12 @@ // ENUMs: // LOW Falling edge // HIGH Rising edge -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA 0x00000008 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_BITN 3 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_M 0x00000008 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_S 3 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_LOW 0x00000008 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_HIGH 0x00000000 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_S 3 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_LOW 0x00000008 +#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_HIGH 0x00000000 //***************************************************************************** // @@ -787,12 +787,12 @@ // when the condition configured in SEL is met. // BURST Burst requests are generated on UDMA0 channel 7 // when the condition configured in SEL is met. -#define AUX_EVCTL_DMACTL_REQ_MODE 0x00000004 -#define AUX_EVCTL_DMACTL_REQ_MODE_BITN 2 -#define AUX_EVCTL_DMACTL_REQ_MODE_M 0x00000004 -#define AUX_EVCTL_DMACTL_REQ_MODE_S 2 -#define AUX_EVCTL_DMACTL_REQ_MODE_SINGLE 0x00000004 -#define AUX_EVCTL_DMACTL_REQ_MODE_BURST 0x00000000 +#define AUX_EVCTL_DMACTL_REQ_MODE 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_BITN 2 +#define AUX_EVCTL_DMACTL_REQ_MODE_M 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_S 2 +#define AUX_EVCTL_DMACTL_REQ_MODE_SINGLE 0x00000004 +#define AUX_EVCTL_DMACTL_REQ_MODE_BURST 0x00000000 // Field: [1] EN // @@ -800,10 +800,10 @@ // // 0: Disable UDMA0 interface to ADC. // 1: Enable UDMA0 interface to ADC. -#define AUX_EVCTL_DMACTL_EN 0x00000002 -#define AUX_EVCTL_DMACTL_EN_BITN 1 -#define AUX_EVCTL_DMACTL_EN_M 0x00000002 -#define AUX_EVCTL_DMACTL_EN_S 1 +#define AUX_EVCTL_DMACTL_EN 0x00000002 +#define AUX_EVCTL_DMACTL_EN_BITN 1 +#define AUX_EVCTL_DMACTL_EN_M 0x00000002 +#define AUX_EVCTL_DMACTL_EN_S 1 // Field: [0] SEL // @@ -814,12 +814,12 @@ // FIFO is almost full (3/4 full). // FIFO_NOT_EMPTY UDMA0 trigger event will be generated when there // are samples in the ADC FIFO. -#define AUX_EVCTL_DMACTL_SEL 0x00000001 -#define AUX_EVCTL_DMACTL_SEL_BITN 0 -#define AUX_EVCTL_DMACTL_SEL_M 0x00000001 -#define AUX_EVCTL_DMACTL_SEL_S 0 -#define AUX_EVCTL_DMACTL_SEL_FIFO_ALMOST_FULL 0x00000001 -#define AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY 0x00000000 +#define AUX_EVCTL_DMACTL_SEL 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_BITN 0 +#define AUX_EVCTL_DMACTL_SEL_M 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_S 0 +#define AUX_EVCTL_DMACTL_SEL_FIFO_ALMOST_FULL 0x00000001 +#define AUX_EVCTL_DMACTL_SEL_FIFO_NOT_EMPTY 0x00000000 //***************************************************************************** // @@ -832,10 +832,10 @@ // // 0: No effect. // 1: Set software event flag 2. -#define AUX_EVCTL_SWEVSET_SWEV2 0x00000004 -#define AUX_EVCTL_SWEVSET_SWEV2_BITN 2 -#define AUX_EVCTL_SWEVSET_SWEV2_M 0x00000004 -#define AUX_EVCTL_SWEVSET_SWEV2_S 2 +#define AUX_EVCTL_SWEVSET_SWEV2 0x00000004 +#define AUX_EVCTL_SWEVSET_SWEV2_BITN 2 +#define AUX_EVCTL_SWEVSET_SWEV2_M 0x00000004 +#define AUX_EVCTL_SWEVSET_SWEV2_S 2 // Field: [1] SWEV1 // @@ -843,10 +843,10 @@ // // 0: No effect. // 1: Set software event flag 1. -#define AUX_EVCTL_SWEVSET_SWEV1 0x00000002 -#define AUX_EVCTL_SWEVSET_SWEV1_BITN 1 -#define AUX_EVCTL_SWEVSET_SWEV1_M 0x00000002 -#define AUX_EVCTL_SWEVSET_SWEV1_S 1 +#define AUX_EVCTL_SWEVSET_SWEV1 0x00000002 +#define AUX_EVCTL_SWEVSET_SWEV1_BITN 1 +#define AUX_EVCTL_SWEVSET_SWEV1_M 0x00000002 +#define AUX_EVCTL_SWEVSET_SWEV1_S 1 // Field: [0] SWEV0 // @@ -854,10 +854,10 @@ // // 0: No effect. // 1: Set software event flag 0. -#define AUX_EVCTL_SWEVSET_SWEV0 0x00000001 -#define AUX_EVCTL_SWEVSET_SWEV0_BITN 0 -#define AUX_EVCTL_SWEVSET_SWEV0_M 0x00000001 -#define AUX_EVCTL_SWEVSET_SWEV0_S 0 +#define AUX_EVCTL_SWEVSET_SWEV0 0x00000001 +#define AUX_EVCTL_SWEVSET_SWEV0_BITN 0 +#define AUX_EVCTL_SWEVSET_SWEV0_M 0x00000001 +#define AUX_EVCTL_SWEVSET_SWEV0_S 0 //***************************************************************************** // @@ -867,134 +867,134 @@ // Field: [15] AUXIO2 // // AUXIO2 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 2. -#define AUX_EVCTL_EVSTAT0_AUXIO2 0x00008000 -#define AUX_EVCTL_EVSTAT0_AUXIO2_BITN 15 -#define AUX_EVCTL_EVSTAT0_AUXIO2_M 0x00008000 -#define AUX_EVCTL_EVSTAT0_AUXIO2_S 15 +#define AUX_EVCTL_EVSTAT0_AUXIO2 0x00008000 +#define AUX_EVCTL_EVSTAT0_AUXIO2_BITN 15 +#define AUX_EVCTL_EVSTAT0_AUXIO2_M 0x00008000 +#define AUX_EVCTL_EVSTAT0_AUXIO2_S 15 // Field: [14] AUXIO1 // // AUXIO1 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 1. -#define AUX_EVCTL_EVSTAT0_AUXIO1 0x00004000 -#define AUX_EVCTL_EVSTAT0_AUXIO1_BITN 14 -#define AUX_EVCTL_EVSTAT0_AUXIO1_M 0x00004000 -#define AUX_EVCTL_EVSTAT0_AUXIO1_S 14 +#define AUX_EVCTL_EVSTAT0_AUXIO1 0x00004000 +#define AUX_EVCTL_EVSTAT0_AUXIO1_BITN 14 +#define AUX_EVCTL_EVSTAT0_AUXIO1_M 0x00004000 +#define AUX_EVCTL_EVSTAT0_AUXIO1_S 14 // Field: [13] AUXIO0 // // AUXIO0 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 0. -#define AUX_EVCTL_EVSTAT0_AUXIO0 0x00002000 -#define AUX_EVCTL_EVSTAT0_AUXIO0_BITN 13 -#define AUX_EVCTL_EVSTAT0_AUXIO0_M 0x00002000 -#define AUX_EVCTL_EVSTAT0_AUXIO0_S 13 +#define AUX_EVCTL_EVSTAT0_AUXIO0 0x00002000 +#define AUX_EVCTL_EVSTAT0_AUXIO0_BITN 13 +#define AUX_EVCTL_EVSTAT0_AUXIO0_M 0x00002000 +#define AUX_EVCTL_EVSTAT0_AUXIO0_S 13 // Field: [12] AON_PROG_WU // // AON_EVENT:AUXWUSEL.WU2_EV OR AON_EVENT:AUXWUSEL.WU1_EV OR // AON_EVENT:AUXWUSEL.WU0_EV -#define AUX_EVCTL_EVSTAT0_AON_PROG_WU 0x00001000 -#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_BITN 12 -#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_M 0x00001000 -#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_S 12 +#define AUX_EVCTL_EVSTAT0_AON_PROG_WU 0x00001000 +#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_BITN 12 +#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_M 0x00001000 +#define AUX_EVCTL_EVSTAT0_AON_PROG_WU_S 12 // Field: [11] AON_SW // // AON_WUC:AUXCTL.SWEV -#define AUX_EVCTL_EVSTAT0_AON_SW 0x00000800 -#define AUX_EVCTL_EVSTAT0_AON_SW_BITN 11 -#define AUX_EVCTL_EVSTAT0_AON_SW_M 0x00000800 -#define AUX_EVCTL_EVSTAT0_AON_SW_S 11 +#define AUX_EVCTL_EVSTAT0_AON_SW 0x00000800 +#define AUX_EVCTL_EVSTAT0_AON_SW_BITN 11 +#define AUX_EVCTL_EVSTAT0_AON_SW_M 0x00000800 +#define AUX_EVCTL_EVSTAT0_AON_SW_S 11 // Field: [10] OBSMUX1 // // Observation input 1 from IOC. // This event is configured by IOC:OBSAUXOUTPUT.SEL1. -#define AUX_EVCTL_EVSTAT0_OBSMUX1 0x00000400 -#define AUX_EVCTL_EVSTAT0_OBSMUX1_BITN 10 -#define AUX_EVCTL_EVSTAT0_OBSMUX1_M 0x00000400 -#define AUX_EVCTL_EVSTAT0_OBSMUX1_S 10 +#define AUX_EVCTL_EVSTAT0_OBSMUX1 0x00000400 +#define AUX_EVCTL_EVSTAT0_OBSMUX1_BITN 10 +#define AUX_EVCTL_EVSTAT0_OBSMUX1_M 0x00000400 +#define AUX_EVCTL_EVSTAT0_OBSMUX1_S 10 // Field: [9] OBSMUX0 // // Observation input 0 from IOC. // This event is configured by IOC:OBSAUXOUTPUT.SEL0 and can be overridden by // IOC:OBSAUXOUTPUT.SEL_MISC. -#define AUX_EVCTL_EVSTAT0_OBSMUX0 0x00000200 -#define AUX_EVCTL_EVSTAT0_OBSMUX0_BITN 9 -#define AUX_EVCTL_EVSTAT0_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_EVSTAT0_OBSMUX0_S 9 +#define AUX_EVCTL_EVSTAT0_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVSTAT0_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVSTAT0_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVSTAT0_OBSMUX0_S 9 // Field: [8] ADC_FIFO_ALMOST_FULL // // AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL -#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_S 8 +#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVSTAT0_ADC_FIFO_ALMOST_FULL_S 8 // Field: [7] ADC_DONE // // AUX_ANAIF ADC conversion done event. -#define AUX_EVCTL_EVSTAT0_ADC_DONE 0x00000080 -#define AUX_EVCTL_EVSTAT0_ADC_DONE_BITN 7 -#define AUX_EVCTL_EVSTAT0_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_EVSTAT0_ADC_DONE_S 7 +#define AUX_EVCTL_EVSTAT0_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVSTAT0_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVSTAT0_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVSTAT0_ADC_DONE_S 7 // Field: [6] SMPH_AUTOTAKE_DONE // // See AUX_SMPH:AUTOTAKE.SMPH_ID for description. -#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_S 6 +#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVSTAT0_SMPH_AUTOTAKE_DONE_S 6 // Field: [5] TIMER1_EV // // AUX_TIMER1_EV event, see AUX_TIMER:T1TARGET for description. -#define AUX_EVCTL_EVSTAT0_TIMER1_EV 0x00000020 -#define AUX_EVCTL_EVSTAT0_TIMER1_EV_BITN 5 -#define AUX_EVCTL_EVSTAT0_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_EVSTAT0_TIMER1_EV_S 5 +#define AUX_EVCTL_EVSTAT0_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVSTAT0_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVSTAT0_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVSTAT0_TIMER1_EV_S 5 // Field: [4] TIMER0_EV // // AUX_TIMER0_EV event, see AUX_TIMER:T0TARGET for description. -#define AUX_EVCTL_EVSTAT0_TIMER0_EV 0x00000010 -#define AUX_EVCTL_EVSTAT0_TIMER0_EV_BITN 4 -#define AUX_EVCTL_EVSTAT0_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_EVSTAT0_TIMER0_EV_S 4 +#define AUX_EVCTL_EVSTAT0_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVSTAT0_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVSTAT0_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVSTAT0_TIMER0_EV_S 4 // Field: [3] TDC_DONE // // AUX_TDC:STAT.DONE -#define AUX_EVCTL_EVSTAT0_TDC_DONE 0x00000008 -#define AUX_EVCTL_EVSTAT0_TDC_DONE_BITN 3 -#define AUX_EVCTL_EVSTAT0_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_EVSTAT0_TDC_DONE_S 3 +#define AUX_EVCTL_EVSTAT0_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVSTAT0_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVSTAT0_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVSTAT0_TDC_DONE_S 3 // Field: [2] AUX_COMPB // // Comparator B output -#define AUX_EVCTL_EVSTAT0_AUX_COMPB 0x00000004 -#define AUX_EVCTL_EVSTAT0_AUX_COMPB_BITN 2 -#define AUX_EVCTL_EVSTAT0_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_EVSTAT0_AUX_COMPB_S 2 +#define AUX_EVCTL_EVSTAT0_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVSTAT0_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVSTAT0_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVSTAT0_AUX_COMPB_S 2 // Field: [1] AUX_COMPA // // Comparator A output -#define AUX_EVCTL_EVSTAT0_AUX_COMPA 0x00000002 -#define AUX_EVCTL_EVSTAT0_AUX_COMPA_BITN 1 -#define AUX_EVCTL_EVSTAT0_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_EVSTAT0_AUX_COMPA_S 1 +#define AUX_EVCTL_EVSTAT0_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVSTAT0_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVSTAT0_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVSTAT0_AUX_COMPA_S 1 // Field: [0] AON_RTC_CH2 // // AON_RTC:EVFLAGS.CH2 -#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2 0x00000001 -#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_BITN 0 -#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_M 0x00000001 -#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_S 0 +#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2 0x00000001 +#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_BITN 0 +#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_M 0x00000001 +#define AUX_EVCTL_EVSTAT0_AON_RTC_CH2_S 0 //***************************************************************************** // @@ -1014,132 +1014,132 @@ // AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW // // Bit 7 in UDMA0:DONEMASK must be 0. -#define AUX_EVCTL_EVSTAT1_ADC_IRQ 0x00008000 -#define AUX_EVCTL_EVSTAT1_ADC_IRQ_BITN 15 -#define AUX_EVCTL_EVSTAT1_ADC_IRQ_M 0x00008000 -#define AUX_EVCTL_EVSTAT1_ADC_IRQ_S 15 +#define AUX_EVCTL_EVSTAT1_ADC_IRQ 0x00008000 +#define AUX_EVCTL_EVSTAT1_ADC_IRQ_BITN 15 +#define AUX_EVCTL_EVSTAT1_ADC_IRQ_M 0x00008000 +#define AUX_EVCTL_EVSTAT1_ADC_IRQ_S 15 // Field: [14] MCU_EV // // Event from EVENT configured by EVENT:AUXSEL0. -#define AUX_EVCTL_EVSTAT1_MCU_EV 0x00004000 -#define AUX_EVCTL_EVSTAT1_MCU_EV_BITN 14 -#define AUX_EVCTL_EVSTAT1_MCU_EV_M 0x00004000 -#define AUX_EVCTL_EVSTAT1_MCU_EV_S 14 +#define AUX_EVCTL_EVSTAT1_MCU_EV 0x00004000 +#define AUX_EVCTL_EVSTAT1_MCU_EV_BITN 14 +#define AUX_EVCTL_EVSTAT1_MCU_EV_M 0x00004000 +#define AUX_EVCTL_EVSTAT1_MCU_EV_S 14 // Field: [13] ACLK_REF // // TDC reference clock. // It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by // AUX_WUC:REFCLKCTL.REQ. -#define AUX_EVCTL_EVSTAT1_ACLK_REF 0x00002000 -#define AUX_EVCTL_EVSTAT1_ACLK_REF_BITN 13 -#define AUX_EVCTL_EVSTAT1_ACLK_REF_M 0x00002000 -#define AUX_EVCTL_EVSTAT1_ACLK_REF_S 13 +#define AUX_EVCTL_EVSTAT1_ACLK_REF 0x00002000 +#define AUX_EVCTL_EVSTAT1_ACLK_REF_BITN 13 +#define AUX_EVCTL_EVSTAT1_ACLK_REF_M 0x00002000 +#define AUX_EVCTL_EVSTAT1_ACLK_REF_S 13 // Field: [12] AUXIO15 // // AUXIO15 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 7. -#define AUX_EVCTL_EVSTAT1_AUXIO15 0x00001000 -#define AUX_EVCTL_EVSTAT1_AUXIO15_BITN 12 -#define AUX_EVCTL_EVSTAT1_AUXIO15_M 0x00001000 -#define AUX_EVCTL_EVSTAT1_AUXIO15_S 12 +#define AUX_EVCTL_EVSTAT1_AUXIO15 0x00001000 +#define AUX_EVCTL_EVSTAT1_AUXIO15_BITN 12 +#define AUX_EVCTL_EVSTAT1_AUXIO15_M 0x00001000 +#define AUX_EVCTL_EVSTAT1_AUXIO15_S 12 // Field: [11] AUXIO14 // // AUXIO14 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 6. -#define AUX_EVCTL_EVSTAT1_AUXIO14 0x00000800 -#define AUX_EVCTL_EVSTAT1_AUXIO14_BITN 11 -#define AUX_EVCTL_EVSTAT1_AUXIO14_M 0x00000800 -#define AUX_EVCTL_EVSTAT1_AUXIO14_S 11 +#define AUX_EVCTL_EVSTAT1_AUXIO14 0x00000800 +#define AUX_EVCTL_EVSTAT1_AUXIO14_BITN 11 +#define AUX_EVCTL_EVSTAT1_AUXIO14_M 0x00000800 +#define AUX_EVCTL_EVSTAT1_AUXIO14_S 11 // Field: [10] AUXIO13 // // AUXIO13 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 5. -#define AUX_EVCTL_EVSTAT1_AUXIO13 0x00000400 -#define AUX_EVCTL_EVSTAT1_AUXIO13_BITN 10 -#define AUX_EVCTL_EVSTAT1_AUXIO13_M 0x00000400 -#define AUX_EVCTL_EVSTAT1_AUXIO13_S 10 +#define AUX_EVCTL_EVSTAT1_AUXIO13 0x00000400 +#define AUX_EVCTL_EVSTAT1_AUXIO13_BITN 10 +#define AUX_EVCTL_EVSTAT1_AUXIO13_M 0x00000400 +#define AUX_EVCTL_EVSTAT1_AUXIO13_S 10 // Field: [9] AUXIO12 // // AUXIO12 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 4. -#define AUX_EVCTL_EVSTAT1_AUXIO12 0x00000200 -#define AUX_EVCTL_EVSTAT1_AUXIO12_BITN 9 -#define AUX_EVCTL_EVSTAT1_AUXIO12_M 0x00000200 -#define AUX_EVCTL_EVSTAT1_AUXIO12_S 9 +#define AUX_EVCTL_EVSTAT1_AUXIO12 0x00000200 +#define AUX_EVCTL_EVSTAT1_AUXIO12_BITN 9 +#define AUX_EVCTL_EVSTAT1_AUXIO12_M 0x00000200 +#define AUX_EVCTL_EVSTAT1_AUXIO12_S 9 // Field: [8] AUXIO11 // // AUXIO11 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 3. -#define AUX_EVCTL_EVSTAT1_AUXIO11 0x00000100 -#define AUX_EVCTL_EVSTAT1_AUXIO11_BITN 8 -#define AUX_EVCTL_EVSTAT1_AUXIO11_M 0x00000100 -#define AUX_EVCTL_EVSTAT1_AUXIO11_S 8 +#define AUX_EVCTL_EVSTAT1_AUXIO11 0x00000100 +#define AUX_EVCTL_EVSTAT1_AUXIO11_BITN 8 +#define AUX_EVCTL_EVSTAT1_AUXIO11_M 0x00000100 +#define AUX_EVCTL_EVSTAT1_AUXIO11_S 8 // Field: [7] AUXIO10 // // AUXIO10 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 2. -#define AUX_EVCTL_EVSTAT1_AUXIO10 0x00000080 -#define AUX_EVCTL_EVSTAT1_AUXIO10_BITN 7 -#define AUX_EVCTL_EVSTAT1_AUXIO10_M 0x00000080 -#define AUX_EVCTL_EVSTAT1_AUXIO10_S 7 +#define AUX_EVCTL_EVSTAT1_AUXIO10 0x00000080 +#define AUX_EVCTL_EVSTAT1_AUXIO10_BITN 7 +#define AUX_EVCTL_EVSTAT1_AUXIO10_M 0x00000080 +#define AUX_EVCTL_EVSTAT1_AUXIO10_S 7 // Field: [6] AUXIO9 // // AUXIO9 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 1. -#define AUX_EVCTL_EVSTAT1_AUXIO9 0x00000040 -#define AUX_EVCTL_EVSTAT1_AUXIO9_BITN 6 -#define AUX_EVCTL_EVSTAT1_AUXIO9_M 0x00000040 -#define AUX_EVCTL_EVSTAT1_AUXIO9_S 6 +#define AUX_EVCTL_EVSTAT1_AUXIO9 0x00000040 +#define AUX_EVCTL_EVSTAT1_AUXIO9_BITN 6 +#define AUX_EVCTL_EVSTAT1_AUXIO9_M 0x00000040 +#define AUX_EVCTL_EVSTAT1_AUXIO9_S 6 // Field: [5] AUXIO8 // // AUXIO8 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 0. -#define AUX_EVCTL_EVSTAT1_AUXIO8 0x00000020 -#define AUX_EVCTL_EVSTAT1_AUXIO8_BITN 5 -#define AUX_EVCTL_EVSTAT1_AUXIO8_M 0x00000020 -#define AUX_EVCTL_EVSTAT1_AUXIO8_S 5 +#define AUX_EVCTL_EVSTAT1_AUXIO8 0x00000020 +#define AUX_EVCTL_EVSTAT1_AUXIO8_BITN 5 +#define AUX_EVCTL_EVSTAT1_AUXIO8_M 0x00000020 +#define AUX_EVCTL_EVSTAT1_AUXIO8_S 5 // Field: [4] AUXIO7 // // AUXIO7 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 7. -#define AUX_EVCTL_EVSTAT1_AUXIO7 0x00000010 -#define AUX_EVCTL_EVSTAT1_AUXIO7_BITN 4 -#define AUX_EVCTL_EVSTAT1_AUXIO7_M 0x00000010 -#define AUX_EVCTL_EVSTAT1_AUXIO7_S 4 +#define AUX_EVCTL_EVSTAT1_AUXIO7 0x00000010 +#define AUX_EVCTL_EVSTAT1_AUXIO7_BITN 4 +#define AUX_EVCTL_EVSTAT1_AUXIO7_M 0x00000010 +#define AUX_EVCTL_EVSTAT1_AUXIO7_S 4 // Field: [3] AUXIO6 // // AUXIO6 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 6. -#define AUX_EVCTL_EVSTAT1_AUXIO6 0x00000008 -#define AUX_EVCTL_EVSTAT1_AUXIO6_BITN 3 -#define AUX_EVCTL_EVSTAT1_AUXIO6_M 0x00000008 -#define AUX_EVCTL_EVSTAT1_AUXIO6_S 3 +#define AUX_EVCTL_EVSTAT1_AUXIO6 0x00000008 +#define AUX_EVCTL_EVSTAT1_AUXIO6_BITN 3 +#define AUX_EVCTL_EVSTAT1_AUXIO6_M 0x00000008 +#define AUX_EVCTL_EVSTAT1_AUXIO6_S 3 // Field: [2] AUXIO5 // // AUXIO5 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 5. -#define AUX_EVCTL_EVSTAT1_AUXIO5 0x00000004 -#define AUX_EVCTL_EVSTAT1_AUXIO5_BITN 2 -#define AUX_EVCTL_EVSTAT1_AUXIO5_M 0x00000004 -#define AUX_EVCTL_EVSTAT1_AUXIO5_S 2 +#define AUX_EVCTL_EVSTAT1_AUXIO5 0x00000004 +#define AUX_EVCTL_EVSTAT1_AUXIO5_BITN 2 +#define AUX_EVCTL_EVSTAT1_AUXIO5_M 0x00000004 +#define AUX_EVCTL_EVSTAT1_AUXIO5_S 2 // Field: [1] AUXIO4 // // AUXIO4 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 4. -#define AUX_EVCTL_EVSTAT1_AUXIO4 0x00000002 -#define AUX_EVCTL_EVSTAT1_AUXIO4_BITN 1 -#define AUX_EVCTL_EVSTAT1_AUXIO4_M 0x00000002 -#define AUX_EVCTL_EVSTAT1_AUXIO4_S 1 +#define AUX_EVCTL_EVSTAT1_AUXIO4 0x00000002 +#define AUX_EVCTL_EVSTAT1_AUXIO4_BITN 1 +#define AUX_EVCTL_EVSTAT1_AUXIO4_M 0x00000002 +#define AUX_EVCTL_EVSTAT1_AUXIO4_S 1 // Field: [0] AUXIO3 // // AUXIO3 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 3. -#define AUX_EVCTL_EVSTAT1_AUXIO3 0x00000001 -#define AUX_EVCTL_EVSTAT1_AUXIO3_BITN 0 -#define AUX_EVCTL_EVSTAT1_AUXIO3_M 0x00000001 -#define AUX_EVCTL_EVSTAT1_AUXIO3_S 0 +#define AUX_EVCTL_EVSTAT1_AUXIO3 0x00000001 +#define AUX_EVCTL_EVSTAT1_AUXIO3_BITN 0 +#define AUX_EVCTL_EVSTAT1_AUXIO3_M 0x00000001 +#define AUX_EVCTL_EVSTAT1_AUXIO3_S 0 //***************************************************************************** // @@ -1152,12 +1152,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ 0x00000400 -#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_BITN 10 -#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_S 10 -#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_LOW 0x00000400 -#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_S 10 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_LOW 0x00000400 +#define AUX_EVCTL_EVTOMCUPOL_ADC_IRQ_HIGH 0x00000000 // Field: [9] OBSMUX0 // @@ -1165,12 +1165,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0 0x00000200 -#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_BITN 9 -#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_S 9 -#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_LOW 0x00000200 -#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_S 9 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_LOW 0x00000200 +#define AUX_EVCTL_EVTOMCUPOL_OBSMUX0_HIGH 0x00000000 // Field: [8] ADC_FIFO_ALMOST_FULL // @@ -1178,12 +1178,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_S 8 -#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_LOW 0x00000100 -#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_S 8 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_LOW 0x00000100 +#define AUX_EVCTL_EVTOMCUPOL_ADC_FIFO_ALMOST_FULL_HIGH 0x00000000 // Field: [7] ADC_DONE // @@ -1191,12 +1191,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE 0x00000080 -#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_BITN 7 -#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_S 7 -#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_LOW 0x00000080 -#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_S 7 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_LOW 0x00000080 +#define AUX_EVCTL_EVTOMCUPOL_ADC_DONE_HIGH 0x00000000 // Field: [6] SMPH_AUTOTAKE_DONE // @@ -1204,12 +1204,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_S 6 -#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_LOW 0x00000040 -#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_S 6 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_LOW 0x00000040 +#define AUX_EVCTL_EVTOMCUPOL_SMPH_AUTOTAKE_DONE_HIGH 0x00000000 // Field: [5] TIMER1_EV // @@ -1217,12 +1217,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV 0x00000020 -#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_BITN 5 -#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_S 5 -#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_LOW 0x00000020 -#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_S 5 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_LOW 0x00000020 +#define AUX_EVCTL_EVTOMCUPOL_TIMER1_EV_HIGH 0x00000000 // Field: [4] TIMER0_EV // @@ -1230,12 +1230,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV 0x00000010 -#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_BITN 4 -#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_S 4 -#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_LOW 0x00000010 -#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_S 4 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_LOW 0x00000010 +#define AUX_EVCTL_EVTOMCUPOL_TIMER0_EV_HIGH 0x00000000 // Field: [3] TDC_DONE // @@ -1243,12 +1243,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE 0x00000008 -#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_BITN 3 -#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_S 3 -#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_LOW 0x00000008 -#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_S 3 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_LOW 0x00000008 +#define AUX_EVCTL_EVTOMCUPOL_TDC_DONE_HIGH 0x00000000 // Field: [2] AUX_COMPB // @@ -1256,12 +1256,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB 0x00000004 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_BITN 2 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_S 2 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_LOW 0x00000004 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_S 2 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_LOW 0x00000004 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_HIGH 0x00000000 // Field: [1] AUX_COMPA // @@ -1269,12 +1269,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA 0x00000002 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_BITN 1 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_S 1 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_LOW 0x00000002 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_S 1 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_LOW 0x00000002 +#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_HIGH 0x00000000 // Field: [0] AON_WU_EV // @@ -1282,12 +1282,12 @@ // ENUMs: // LOW Low level // HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV 0x00000001 -#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_BITN 0 -#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_M 0x00000001 -#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_S 0 -#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_LOW 0x00000001 -#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_HIGH 0x00000000 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_S 0 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_LOW 0x00000001 +#define AUX_EVCTL_EVTOMCUPOL_AON_WU_EV_HIGH 0x00000000 //***************************************************************************** // @@ -1298,101 +1298,101 @@ // // This event flag is set when level selected by EVTOMCUPOL.ADC_IRQ occurs on // EVSTAT0.ADC_IRQ. -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ 0x00000400 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_BITN 10 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_S 10 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_IRQ_S 10 // Field: [9] OBSMUX0 // // This event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs // on EVSTAT0.MCU_OBSMUX0. -#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0 0x00000200 -#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_BITN 9 -#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_S 9 +#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGS_OBSMUX0_S 9 // Field: [8] ADC_FIFO_ALMOST_FULL // // This event flag is set when level selected by // EVTOMCUPOL.ADC_FIFO_ALMOST_FULL occurs on EVSTAT0.ADC_FIFO_ALMOST_FULL. -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_S 8 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_FIFO_ALMOST_FULL_S 8 // Field: [7] ADC_DONE // // This event flag is set when level selected by EVTOMCUPOL.ADC_DONE occurs on // EVSTAT0.ADC_DONE. -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE 0x00000080 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_BITN 7 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_S 7 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGS_ADC_DONE_S 7 // Field: [6] SMPH_AUTOTAKE_DONE // // This event flag is set when level selected by EVTOMCUPOL.SMPH_AUTOTAKE_DONE // occurs on EVSTAT0.SMPH_AUTOTAKE_DONE. -#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_S 6 +#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGS_SMPH_AUTOTAKE_DONE_S 6 // Field: [5] TIMER1_EV // // This event flag is set when level selected by EVTOMCUPOL.TIMER1_EV occurs on // EVSTAT0.TIMER1_EV. -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV 0x00000020 -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_BITN 5 -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_S 5 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER1_EV_S 5 // Field: [4] TIMER0_EV // // This event flag is set when level selected by EVTOMCUPOL.TIMER0_EV occurs on // EVSTAT0.TIMER0_EV. -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV 0x00000010 -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_BITN 4 -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_S 4 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGS_TIMER0_EV_S 4 // Field: [3] TDC_DONE // // This event flag is set when level selected by EVTOMCUPOL.TDC_DONE occurs on // EVSTAT0.TDC_DONE. -#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE 0x00000008 -#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_BITN 3 -#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_S 3 +#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGS_TDC_DONE_S 3 // Field: [2] AUX_COMPB // // This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on // EVSTAT0.AUX_COMPB. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB 0x00000004 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_BITN 2 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_S 2 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_S 2 // Field: [1] AUX_COMPA // // This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on // EVSTAT0.AUX_COMPA. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA 0x00000002 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_BITN 1 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_S 1 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_S 1 // Field: [0] AON_WU_EV // // This event flag is set when level selected by EVTOMCUPOL.AON_WU_EV occurs on // the reduction-OR of the AUX_EVCTL:EVSTAT0.RTC_CH2_EV, // AUX_EVCTL:EVSTAT0.AON_SW, and AUX_EVCTL:EVSTAT0.AON_PROG_WU events. -#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV 0x00000001 -#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_BITN 0 -#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_M 0x00000001 -#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_S 0 +#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGS_AON_WU_EV_S 0 //***************************************************************************** // @@ -1405,10 +1405,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ 0x00000400 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_BITN 10 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_S 10 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ 0x00000400 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_BITN 10 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_IRQ_S 10 // Field: [9] OBSMUX0 // @@ -1416,10 +1416,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0 0x00000200 -#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_BITN 9 -#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_S 9 +#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0 0x00000200 +#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_BITN 9 +#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_COMBEVTOMCUMASK_OBSMUX0_S 9 // Field: [8] ADC_FIFO_ALMOST_FULL // @@ -1427,10 +1427,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_S 8 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_FIFO_ALMOST_FULL_S 8 // Field: [7] ADC_DONE // @@ -1438,10 +1438,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE 0x00000080 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_BITN 7 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_S 7 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE 0x00000080 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_BITN 7 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_COMBEVTOMCUMASK_ADC_DONE_S 7 // Field: [6] SMPH_AUTOTAKE_DONE // @@ -1449,10 +1449,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_S 6 +#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_COMBEVTOMCUMASK_SMPH_AUTOTAKE_DONE_S 6 // Field: [5] TIMER1_EV // @@ -1460,10 +1460,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV 0x00000020 -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_BITN 5 -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_S 5 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV 0x00000020 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_BITN 5 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER1_EV_S 5 // Field: [4] TIMER0_EV // @@ -1471,10 +1471,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV 0x00000010 -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_BITN 4 -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_S 4 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV 0x00000010 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_BITN 4 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_COMBEVTOMCUMASK_TIMER0_EV_S 4 // Field: [3] TDC_DONE // @@ -1482,10 +1482,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE 0x00000008 -#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_BITN 3 -#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_S 3 +#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE 0x00000008 +#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_BITN 3 +#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_COMBEVTOMCUMASK_TDC_DONE_S 3 // Field: [2] AUX_COMPB // @@ -1493,10 +1493,10 @@ // // 0: Exclude // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB 0x00000004 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_BITN 2 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_S 2 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB 0x00000004 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_BITN 2 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_S 2 // Field: [1] AUX_COMPA // @@ -1504,10 +1504,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA 0x00000002 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_BITN 1 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_S 1 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA 0x00000002 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_BITN 1 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_S 1 // Field: [0] AON_WU_EV // @@ -1515,10 +1515,10 @@ // // 0: Exclude. // 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV 0x00000001 -#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_BITN 0 -#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_M 0x00000001 -#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_S 0 +#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV 0x00000001 +#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_BITN 0 +#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_M 0x00000001 +#define AUX_EVCTL_COMBEVTOMCUMASK_AON_WU_EV_S 0 //***************************************************************************** // @@ -1534,10 +1534,10 @@ // // The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to // VECFLAGSCLR.VEC3. -#define AUX_EVCTL_VECFLAGS_VEC3 0x00000008 -#define AUX_EVCTL_VECFLAGS_VEC3_BITN 3 -#define AUX_EVCTL_VECFLAGS_VEC3_M 0x00000008 -#define AUX_EVCTL_VECFLAGS_VEC3_S 3 +#define AUX_EVCTL_VECFLAGS_VEC3 0x00000008 +#define AUX_EVCTL_VECFLAGS_VEC3_BITN 3 +#define AUX_EVCTL_VECFLAGS_VEC3_M 0x00000008 +#define AUX_EVCTL_VECFLAGS_VEC3_S 3 // Field: [2] VEC2 // @@ -1548,10 +1548,10 @@ // // The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to // VECFLAGSCLR.VEC2. -#define AUX_EVCTL_VECFLAGS_VEC2 0x00000004 -#define AUX_EVCTL_VECFLAGS_VEC2_BITN 2 -#define AUX_EVCTL_VECFLAGS_VEC2_M 0x00000004 -#define AUX_EVCTL_VECFLAGS_VEC2_S 2 +#define AUX_EVCTL_VECFLAGS_VEC2 0x00000004 +#define AUX_EVCTL_VECFLAGS_VEC2_BITN 2 +#define AUX_EVCTL_VECFLAGS_VEC2_M 0x00000004 +#define AUX_EVCTL_VECFLAGS_VEC2_S 2 // Field: [1] VEC1 // @@ -1562,10 +1562,10 @@ // // The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to // VECFLAGSCLR.VEC1. -#define AUX_EVCTL_VECFLAGS_VEC1 0x00000002 -#define AUX_EVCTL_VECFLAGS_VEC1_BITN 1 -#define AUX_EVCTL_VECFLAGS_VEC1_M 0x00000002 -#define AUX_EVCTL_VECFLAGS_VEC1_S 1 +#define AUX_EVCTL_VECFLAGS_VEC1 0x00000002 +#define AUX_EVCTL_VECFLAGS_VEC1_BITN 1 +#define AUX_EVCTL_VECFLAGS_VEC1_M 0x00000002 +#define AUX_EVCTL_VECFLAGS_VEC1_S 1 // Field: [0] VEC0 // @@ -1576,10 +1576,10 @@ // // The flag is cleared by writing a 0 to this bit, or (preferably) a 1 to // VECFLAGSCLR.VEC0. -#define AUX_EVCTL_VECFLAGS_VEC0 0x00000001 -#define AUX_EVCTL_VECFLAGS_VEC0_BITN 0 -#define AUX_EVCTL_VECFLAGS_VEC0_M 0x00000001 -#define AUX_EVCTL_VECFLAGS_VEC0_S 0 +#define AUX_EVCTL_VECFLAGS_VEC0 0x00000001 +#define AUX_EVCTL_VECFLAGS_VEC0_BITN 0 +#define AUX_EVCTL_VECFLAGS_VEC0_M 0x00000001 +#define AUX_EVCTL_VECFLAGS_VEC0_S 0 //***************************************************************************** // @@ -1591,110 +1591,110 @@ // Write 1 to clear EVTOMCUFLAGS.ADC_IRQ. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ 0x00000400 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_BITN 10 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_S 10 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_BITN 10 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_M 0x00000400 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_IRQ_S 10 // Field: [9] OBSMUX0 // // Write 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0 0x00000200 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_BITN 9 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_S 9 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_BITN 9 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_M 0x00000200 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_OBSMUX0_S 9 // Field: [8] ADC_FIFO_ALMOST_FULL // // Write 1 to clear EVTOMCUFLAGS.ADC_FIFO_ALMOST_FULL. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_S 8 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_BITN 8 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_M 0x00000100 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_FIFO_ALMOST_FULL_S 8 // Field: [7] ADC_DONE // // Write 1 to clear EVTOMCUFLAGS.ADC_DONE. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE 0x00000080 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_BITN 7 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_S 7 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_BITN 7 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_M 0x00000080 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_ADC_DONE_S 7 // Field: [6] SMPH_AUTOTAKE_DONE // // Write 1 to clear EVTOMCUFLAGS.SMPH_AUTOTAKE_DONE. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_S 6 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_BITN 6 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_SMPH_AUTOTAKE_DONE_S 6 // Field: [5] TIMER1_EV // // Write 1 to clear EVTOMCUFLAGS.TIMER1_EV. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV 0x00000020 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_BITN 5 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_S 5 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_BITN 5 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_M 0x00000020 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER1_EV_S 5 // Field: [4] TIMER0_EV // // Write 1 to clear EVTOMCUFLAGS.TIMER0_EV. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV 0x00000010 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_BITN 4 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_S 4 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_BITN 4 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_M 0x00000010 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TIMER0_EV_S 4 // Field: [3] TDC_DONE // // Write 1 to clear EVTOMCUFLAGS.TDC_DONE. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE 0x00000008 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_BITN 3 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_S 3 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_BITN 3 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_M 0x00000008 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_TDC_DONE_S 3 // Field: [2] AUX_COMPB // // Write 1 to clear EVTOMCUFLAGS.AUX_COMPB. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB 0x00000004 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_BITN 2 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_S 2 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_BITN 2 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_M 0x00000004 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_S 2 // Field: [1] AUX_COMPA // // Write 1 to clear EVTOMCUFLAGS.AUX_COMPA. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA 0x00000002 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_BITN 1 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_S 1 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_BITN 1 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_M 0x00000002 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_S 1 // Field: [0] AON_WU_EV // // Write 1 to clear EVTOMCUFLAGS.AON_WU_EV. // // Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV 0x00000001 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_BITN 0 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_M 0x00000001 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_S 0 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_BITN 0 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_M 0x00000001 +#define AUX_EVCTL_EVTOMCUFLAGSCLR_AON_WU_EV_S 0 //***************************************************************************** // @@ -1706,90 +1706,90 @@ // Write 1 to clear EVTOAONFLAGS.TIMER1_EV. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV 0x00000100 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_BITN 8 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_M 0x00000100 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_S 8 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_BITN 8 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_M 0x00000100 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER1_EV_S 8 // Field: [7] TIMER0_EV // // Write 1 to clear EVTOAONFLAGS.TIMER0_EV. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV 0x00000080 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_BITN 7 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_M 0x00000080 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_S 7 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_BITN 7 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_M 0x00000080 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TIMER0_EV_S 7 // Field: [6] TDC_DONE // // Write 1 to clear EVTOAONFLAGS.TDC_DONE. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE 0x00000040 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_BITN 6 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_S 6 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_BITN 6 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_M 0x00000040 +#define AUX_EVCTL_EVTOAONFLAGSCLR_TDC_DONE_S 6 // Field: [5] ADC_DONE // // Write 1 to clear EVTOAONFLAGS.ADC_DONE. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE 0x00000020 -#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_BITN 5 -#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_M 0x00000020 -#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_S 5 +#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_BITN 5 +#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_M 0x00000020 +#define AUX_EVCTL_EVTOAONFLAGSCLR_ADC_DONE_S 5 // Field: [4] AUX_COMPB // // Write 1 to clear EVTOAONFLAGS.AUX_COMPB. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB 0x00000010 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_BITN 4 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_M 0x00000010 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_S 4 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_BITN 4 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_M 0x00000010 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_S 4 // Field: [3] AUX_COMPA // // Write 1 to clear EVTOAONFLAGS.AUX_COMPA. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA 0x00000008 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_BITN 3 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_M 0x00000008 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_S 3 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_BITN 3 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_M 0x00000008 +#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_S 3 // Field: [2] SWEV2 // // Write 1 to clear EVTOAONFLAGS.SWEV2. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2 0x00000004 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_BITN 2 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_M 0x00000004 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_S 2 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_BITN 2 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_M 0x00000004 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_S 2 // Field: [1] SWEV1 // // Write 1 to clear EVTOAONFLAGS.SWEV1. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1 0x00000002 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_BITN 1 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_M 0x00000002 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_S 1 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_BITN 1 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_M 0x00000002 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_S 1 // Field: [0] SWEV0 // // Write 1 to clear EVTOAONFLAGS.SWEV0. // // Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0 0x00000001 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_BITN 0 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_M 0x00000001 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_S 0 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_BITN 0 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_M 0x00000001 +#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_S 0 //***************************************************************************** // @@ -1804,10 +1804,10 @@ // 1: Clear VECFLAGS.VEC3. // // Read value is 0. -#define AUX_EVCTL_VECFLAGSCLR_VEC3 0x00000008 -#define AUX_EVCTL_VECFLAGSCLR_VEC3_BITN 3 -#define AUX_EVCTL_VECFLAGSCLR_VEC3_M 0x00000008 -#define AUX_EVCTL_VECFLAGSCLR_VEC3_S 3 +#define AUX_EVCTL_VECFLAGSCLR_VEC3 0x00000008 +#define AUX_EVCTL_VECFLAGSCLR_VEC3_BITN 3 +#define AUX_EVCTL_VECFLAGSCLR_VEC3_M 0x00000008 +#define AUX_EVCTL_VECFLAGSCLR_VEC3_S 3 // Field: [2] VEC2 // @@ -1817,10 +1817,10 @@ // 1: Clear VECFLAGS.VEC2. // // Read value is 0. -#define AUX_EVCTL_VECFLAGSCLR_VEC2 0x00000004 -#define AUX_EVCTL_VECFLAGSCLR_VEC2_BITN 2 -#define AUX_EVCTL_VECFLAGSCLR_VEC2_M 0x00000004 -#define AUX_EVCTL_VECFLAGSCLR_VEC2_S 2 +#define AUX_EVCTL_VECFLAGSCLR_VEC2 0x00000004 +#define AUX_EVCTL_VECFLAGSCLR_VEC2_BITN 2 +#define AUX_EVCTL_VECFLAGSCLR_VEC2_M 0x00000004 +#define AUX_EVCTL_VECFLAGSCLR_VEC2_S 2 // Field: [1] VEC1 // @@ -1830,10 +1830,10 @@ // 1: Clear VECFLAGS.VEC1. // // Read value is 0. -#define AUX_EVCTL_VECFLAGSCLR_VEC1 0x00000002 -#define AUX_EVCTL_VECFLAGSCLR_VEC1_BITN 1 -#define AUX_EVCTL_VECFLAGSCLR_VEC1_M 0x00000002 -#define AUX_EVCTL_VECFLAGSCLR_VEC1_S 1 +#define AUX_EVCTL_VECFLAGSCLR_VEC1 0x00000002 +#define AUX_EVCTL_VECFLAGSCLR_VEC1_BITN 1 +#define AUX_EVCTL_VECFLAGSCLR_VEC1_M 0x00000002 +#define AUX_EVCTL_VECFLAGSCLR_VEC1_S 1 // Field: [0] VEC0 // @@ -1843,10 +1843,9 @@ // 1: Clear VECFLAGS.VEC0. // // Read value is 0. -#define AUX_EVCTL_VECFLAGSCLR_VEC0 0x00000001 -#define AUX_EVCTL_VECFLAGSCLR_VEC0_BITN 0 -#define AUX_EVCTL_VECFLAGSCLR_VEC0_M 0x00000001 -#define AUX_EVCTL_VECFLAGSCLR_VEC0_S 0 - +#define AUX_EVCTL_VECFLAGSCLR_VEC0 0x00000001 +#define AUX_EVCTL_VECFLAGSCLR_VEC0_BITN 0 +#define AUX_EVCTL_VECFLAGSCLR_VEC0_M 0x00000001 +#define AUX_EVCTL_VECFLAGSCLR_VEC0_S 0 #endif // __AUX_EVCTL__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_sce.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_sce.h index 002242a..a39b085 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_sce.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_sce.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_sce_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_sce_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_SCE_H__ #define __HW_AUX_SCE_H__ @@ -44,34 +44,34 @@ // //***************************************************************************** // Internal -#define AUX_SCE_O_CTL 0x00000000 +#define AUX_SCE_O_CTL 0x00000000 // Internal -#define AUX_SCE_O_FETCHSTAT 0x00000004 +#define AUX_SCE_O_FETCHSTAT 0x00000004 // Internal -#define AUX_SCE_O_CPUSTAT 0x00000008 +#define AUX_SCE_O_CPUSTAT 0x00000008 // Internal -#define AUX_SCE_O_WUSTAT 0x0000000C +#define AUX_SCE_O_WUSTAT 0x0000000C // Internal -#define AUX_SCE_O_REG1_0 0x00000010 +#define AUX_SCE_O_REG1_0 0x00000010 // Internal -#define AUX_SCE_O_REG3_2 0x00000014 +#define AUX_SCE_O_REG3_2 0x00000014 // Internal -#define AUX_SCE_O_REG5_4 0x00000018 +#define AUX_SCE_O_REG5_4 0x00000018 // Internal -#define AUX_SCE_O_REG7_6 0x0000001C +#define AUX_SCE_O_REG7_6 0x0000001C // Internal -#define AUX_SCE_O_LOOPADDR 0x00000020 +#define AUX_SCE_O_LOOPADDR 0x00000020 // Internal -#define AUX_SCE_O_LOOPCNT 0x00000024 +#define AUX_SCE_O_LOOPCNT 0x00000024 //***************************************************************************** // @@ -81,79 +81,79 @@ // Field: [31:24] FORCE_EV_LOW // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_FORCE_EV_LOW_W 8 -#define AUX_SCE_CTL_FORCE_EV_LOW_M 0xFF000000 -#define AUX_SCE_CTL_FORCE_EV_LOW_S 24 +#define AUX_SCE_CTL_FORCE_EV_LOW_W 8 +#define AUX_SCE_CTL_FORCE_EV_LOW_M 0xFF000000 +#define AUX_SCE_CTL_FORCE_EV_LOW_S 24 // Field: [23:16] FORCE_EV_HIGH // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_FORCE_EV_HIGH_W 8 -#define AUX_SCE_CTL_FORCE_EV_HIGH_M 0x00FF0000 -#define AUX_SCE_CTL_FORCE_EV_HIGH_S 16 +#define AUX_SCE_CTL_FORCE_EV_HIGH_W 8 +#define AUX_SCE_CTL_FORCE_EV_HIGH_M 0x00FF0000 +#define AUX_SCE_CTL_FORCE_EV_HIGH_S 16 // Field: [11:8] RESET_VECTOR // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_RESET_VECTOR_W 4 -#define AUX_SCE_CTL_RESET_VECTOR_M 0x00000F00 -#define AUX_SCE_CTL_RESET_VECTOR_S 8 +#define AUX_SCE_CTL_RESET_VECTOR_W 4 +#define AUX_SCE_CTL_RESET_VECTOR_M 0x00000F00 +#define AUX_SCE_CTL_RESET_VECTOR_S 8 // Field: [6] DBG_FREEZE_EN // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_DBG_FREEZE_EN 0x00000040 -#define AUX_SCE_CTL_DBG_FREEZE_EN_BITN 6 -#define AUX_SCE_CTL_DBG_FREEZE_EN_M 0x00000040 -#define AUX_SCE_CTL_DBG_FREEZE_EN_S 6 +#define AUX_SCE_CTL_DBG_FREEZE_EN 0x00000040 +#define AUX_SCE_CTL_DBG_FREEZE_EN_BITN 6 +#define AUX_SCE_CTL_DBG_FREEZE_EN_M 0x00000040 +#define AUX_SCE_CTL_DBG_FREEZE_EN_S 6 // Field: [5] FORCE_WU_LOW // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_FORCE_WU_LOW 0x00000020 -#define AUX_SCE_CTL_FORCE_WU_LOW_BITN 5 -#define AUX_SCE_CTL_FORCE_WU_LOW_M 0x00000020 -#define AUX_SCE_CTL_FORCE_WU_LOW_S 5 +#define AUX_SCE_CTL_FORCE_WU_LOW 0x00000020 +#define AUX_SCE_CTL_FORCE_WU_LOW_BITN 5 +#define AUX_SCE_CTL_FORCE_WU_LOW_M 0x00000020 +#define AUX_SCE_CTL_FORCE_WU_LOW_S 5 // Field: [4] FORCE_WU_HIGH // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_FORCE_WU_HIGH 0x00000010 -#define AUX_SCE_CTL_FORCE_WU_HIGH_BITN 4 -#define AUX_SCE_CTL_FORCE_WU_HIGH_M 0x00000010 -#define AUX_SCE_CTL_FORCE_WU_HIGH_S 4 +#define AUX_SCE_CTL_FORCE_WU_HIGH 0x00000010 +#define AUX_SCE_CTL_FORCE_WU_HIGH_BITN 4 +#define AUX_SCE_CTL_FORCE_WU_HIGH_M 0x00000010 +#define AUX_SCE_CTL_FORCE_WU_HIGH_S 4 // Field: [3] RESTART // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_RESTART 0x00000008 -#define AUX_SCE_CTL_RESTART_BITN 3 -#define AUX_SCE_CTL_RESTART_M 0x00000008 -#define AUX_SCE_CTL_RESTART_S 3 +#define AUX_SCE_CTL_RESTART 0x00000008 +#define AUX_SCE_CTL_RESTART_BITN 3 +#define AUX_SCE_CTL_RESTART_M 0x00000008 +#define AUX_SCE_CTL_RESTART_S 3 // Field: [2] SINGLE_STEP // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_SINGLE_STEP 0x00000004 -#define AUX_SCE_CTL_SINGLE_STEP_BITN 2 -#define AUX_SCE_CTL_SINGLE_STEP_M 0x00000004 -#define AUX_SCE_CTL_SINGLE_STEP_S 2 +#define AUX_SCE_CTL_SINGLE_STEP 0x00000004 +#define AUX_SCE_CTL_SINGLE_STEP_BITN 2 +#define AUX_SCE_CTL_SINGLE_STEP_M 0x00000004 +#define AUX_SCE_CTL_SINGLE_STEP_S 2 // Field: [1] SUSPEND // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_SUSPEND 0x00000002 -#define AUX_SCE_CTL_SUSPEND_BITN 1 -#define AUX_SCE_CTL_SUSPEND_M 0x00000002 -#define AUX_SCE_CTL_SUSPEND_S 1 +#define AUX_SCE_CTL_SUSPEND 0x00000002 +#define AUX_SCE_CTL_SUSPEND_BITN 1 +#define AUX_SCE_CTL_SUSPEND_M 0x00000002 +#define AUX_SCE_CTL_SUSPEND_S 1 // Field: [0] CLK_EN // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_CLK_EN 0x00000001 -#define AUX_SCE_CTL_CLK_EN_BITN 0 -#define AUX_SCE_CTL_CLK_EN_M 0x00000001 -#define AUX_SCE_CTL_CLK_EN_S 0 +#define AUX_SCE_CTL_CLK_EN 0x00000001 +#define AUX_SCE_CTL_CLK_EN_BITN 0 +#define AUX_SCE_CTL_CLK_EN_M 0x00000001 +#define AUX_SCE_CTL_CLK_EN_S 0 //***************************************************************************** // @@ -163,16 +163,16 @@ // Field: [31:16] OPCODE // // Internal. Only to be used through TI provided API. -#define AUX_SCE_FETCHSTAT_OPCODE_W 16 -#define AUX_SCE_FETCHSTAT_OPCODE_M 0xFFFF0000 -#define AUX_SCE_FETCHSTAT_OPCODE_S 16 +#define AUX_SCE_FETCHSTAT_OPCODE_W 16 +#define AUX_SCE_FETCHSTAT_OPCODE_M 0xFFFF0000 +#define AUX_SCE_FETCHSTAT_OPCODE_S 16 // Field: [15:0] PC // // Internal. Only to be used through TI provided API. -#define AUX_SCE_FETCHSTAT_PC_W 16 -#define AUX_SCE_FETCHSTAT_PC_M 0x0000FFFF -#define AUX_SCE_FETCHSTAT_PC_S 0 +#define AUX_SCE_FETCHSTAT_PC_W 16 +#define AUX_SCE_FETCHSTAT_PC_M 0x0000FFFF +#define AUX_SCE_FETCHSTAT_PC_S 0 //***************************************************************************** // @@ -182,66 +182,66 @@ // Field: [11] BUS_ERROR // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_BUS_ERROR 0x00000800 -#define AUX_SCE_CPUSTAT_BUS_ERROR_BITN 11 -#define AUX_SCE_CPUSTAT_BUS_ERROR_M 0x00000800 -#define AUX_SCE_CPUSTAT_BUS_ERROR_S 11 +#define AUX_SCE_CPUSTAT_BUS_ERROR 0x00000800 +#define AUX_SCE_CPUSTAT_BUS_ERROR_BITN 11 +#define AUX_SCE_CPUSTAT_BUS_ERROR_M 0x00000800 +#define AUX_SCE_CPUSTAT_BUS_ERROR_S 11 // Field: [10] SLEEP // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_SLEEP 0x00000400 -#define AUX_SCE_CPUSTAT_SLEEP_BITN 10 -#define AUX_SCE_CPUSTAT_SLEEP_M 0x00000400 -#define AUX_SCE_CPUSTAT_SLEEP_S 10 +#define AUX_SCE_CPUSTAT_SLEEP 0x00000400 +#define AUX_SCE_CPUSTAT_SLEEP_BITN 10 +#define AUX_SCE_CPUSTAT_SLEEP_M 0x00000400 +#define AUX_SCE_CPUSTAT_SLEEP_S 10 // Field: [9] WEV // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_WEV 0x00000200 -#define AUX_SCE_CPUSTAT_WEV_BITN 9 -#define AUX_SCE_CPUSTAT_WEV_M 0x00000200 -#define AUX_SCE_CPUSTAT_WEV_S 9 +#define AUX_SCE_CPUSTAT_WEV 0x00000200 +#define AUX_SCE_CPUSTAT_WEV_BITN 9 +#define AUX_SCE_CPUSTAT_WEV_M 0x00000200 +#define AUX_SCE_CPUSTAT_WEV_S 9 // Field: [8] SELF_STOP // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_SELF_STOP 0x00000100 -#define AUX_SCE_CPUSTAT_SELF_STOP_BITN 8 -#define AUX_SCE_CPUSTAT_SELF_STOP_M 0x00000100 -#define AUX_SCE_CPUSTAT_SELF_STOP_S 8 +#define AUX_SCE_CPUSTAT_SELF_STOP 0x00000100 +#define AUX_SCE_CPUSTAT_SELF_STOP_BITN 8 +#define AUX_SCE_CPUSTAT_SELF_STOP_M 0x00000100 +#define AUX_SCE_CPUSTAT_SELF_STOP_S 8 // Field: [3] V_FLAG // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_V_FLAG 0x00000008 -#define AUX_SCE_CPUSTAT_V_FLAG_BITN 3 -#define AUX_SCE_CPUSTAT_V_FLAG_M 0x00000008 -#define AUX_SCE_CPUSTAT_V_FLAG_S 3 +#define AUX_SCE_CPUSTAT_V_FLAG 0x00000008 +#define AUX_SCE_CPUSTAT_V_FLAG_BITN 3 +#define AUX_SCE_CPUSTAT_V_FLAG_M 0x00000008 +#define AUX_SCE_CPUSTAT_V_FLAG_S 3 // Field: [2] C_FLAG // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_C_FLAG 0x00000004 -#define AUX_SCE_CPUSTAT_C_FLAG_BITN 2 -#define AUX_SCE_CPUSTAT_C_FLAG_M 0x00000004 -#define AUX_SCE_CPUSTAT_C_FLAG_S 2 +#define AUX_SCE_CPUSTAT_C_FLAG 0x00000004 +#define AUX_SCE_CPUSTAT_C_FLAG_BITN 2 +#define AUX_SCE_CPUSTAT_C_FLAG_M 0x00000004 +#define AUX_SCE_CPUSTAT_C_FLAG_S 2 // Field: [1] N_FLAG // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_N_FLAG 0x00000002 -#define AUX_SCE_CPUSTAT_N_FLAG_BITN 1 -#define AUX_SCE_CPUSTAT_N_FLAG_M 0x00000002 -#define AUX_SCE_CPUSTAT_N_FLAG_S 1 +#define AUX_SCE_CPUSTAT_N_FLAG 0x00000002 +#define AUX_SCE_CPUSTAT_N_FLAG_BITN 1 +#define AUX_SCE_CPUSTAT_N_FLAG_M 0x00000002 +#define AUX_SCE_CPUSTAT_N_FLAG_S 1 // Field: [0] Z_FLAG // // Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_Z_FLAG 0x00000001 -#define AUX_SCE_CPUSTAT_Z_FLAG_BITN 0 -#define AUX_SCE_CPUSTAT_Z_FLAG_M 0x00000001 -#define AUX_SCE_CPUSTAT_Z_FLAG_S 0 +#define AUX_SCE_CPUSTAT_Z_FLAG 0x00000001 +#define AUX_SCE_CPUSTAT_Z_FLAG_BITN 0 +#define AUX_SCE_CPUSTAT_Z_FLAG_M 0x00000001 +#define AUX_SCE_CPUSTAT_Z_FLAG_S 0 //***************************************************************************** // @@ -251,24 +251,24 @@ // Field: [17:16] EXC_VECTOR // // Internal. Only to be used through TI provided API. -#define AUX_SCE_WUSTAT_EXC_VECTOR_W 2 -#define AUX_SCE_WUSTAT_EXC_VECTOR_M 0x00030000 -#define AUX_SCE_WUSTAT_EXC_VECTOR_S 16 +#define AUX_SCE_WUSTAT_EXC_VECTOR_W 2 +#define AUX_SCE_WUSTAT_EXC_VECTOR_M 0x00030000 +#define AUX_SCE_WUSTAT_EXC_VECTOR_S 16 // Field: [8] WU_SIGNAL // // Internal. Only to be used through TI provided API. -#define AUX_SCE_WUSTAT_WU_SIGNAL 0x00000100 -#define AUX_SCE_WUSTAT_WU_SIGNAL_BITN 8 -#define AUX_SCE_WUSTAT_WU_SIGNAL_M 0x00000100 -#define AUX_SCE_WUSTAT_WU_SIGNAL_S 8 +#define AUX_SCE_WUSTAT_WU_SIGNAL 0x00000100 +#define AUX_SCE_WUSTAT_WU_SIGNAL_BITN 8 +#define AUX_SCE_WUSTAT_WU_SIGNAL_M 0x00000100 +#define AUX_SCE_WUSTAT_WU_SIGNAL_S 8 // Field: [7:0] EV_SIGNALS // // Internal. Only to be used through TI provided API. -#define AUX_SCE_WUSTAT_EV_SIGNALS_W 8 -#define AUX_SCE_WUSTAT_EV_SIGNALS_M 0x000000FF -#define AUX_SCE_WUSTAT_EV_SIGNALS_S 0 +#define AUX_SCE_WUSTAT_EV_SIGNALS_W 8 +#define AUX_SCE_WUSTAT_EV_SIGNALS_M 0x000000FF +#define AUX_SCE_WUSTAT_EV_SIGNALS_S 0 //***************************************************************************** // @@ -278,16 +278,16 @@ // Field: [31:16] REG1 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG1_0_REG1_W 16 -#define AUX_SCE_REG1_0_REG1_M 0xFFFF0000 -#define AUX_SCE_REG1_0_REG1_S 16 +#define AUX_SCE_REG1_0_REG1_W 16 +#define AUX_SCE_REG1_0_REG1_M 0xFFFF0000 +#define AUX_SCE_REG1_0_REG1_S 16 // Field: [15:0] REG0 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG1_0_REG0_W 16 -#define AUX_SCE_REG1_0_REG0_M 0x0000FFFF -#define AUX_SCE_REG1_0_REG0_S 0 +#define AUX_SCE_REG1_0_REG0_W 16 +#define AUX_SCE_REG1_0_REG0_M 0x0000FFFF +#define AUX_SCE_REG1_0_REG0_S 0 //***************************************************************************** // @@ -297,16 +297,16 @@ // Field: [31:16] REG3 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG3_2_REG3_W 16 -#define AUX_SCE_REG3_2_REG3_M 0xFFFF0000 -#define AUX_SCE_REG3_2_REG3_S 16 +#define AUX_SCE_REG3_2_REG3_W 16 +#define AUX_SCE_REG3_2_REG3_M 0xFFFF0000 +#define AUX_SCE_REG3_2_REG3_S 16 // Field: [15:0] REG2 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG3_2_REG2_W 16 -#define AUX_SCE_REG3_2_REG2_M 0x0000FFFF -#define AUX_SCE_REG3_2_REG2_S 0 +#define AUX_SCE_REG3_2_REG2_W 16 +#define AUX_SCE_REG3_2_REG2_M 0x0000FFFF +#define AUX_SCE_REG3_2_REG2_S 0 //***************************************************************************** // @@ -316,16 +316,16 @@ // Field: [31:16] REG5 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG5_4_REG5_W 16 -#define AUX_SCE_REG5_4_REG5_M 0xFFFF0000 -#define AUX_SCE_REG5_4_REG5_S 16 +#define AUX_SCE_REG5_4_REG5_W 16 +#define AUX_SCE_REG5_4_REG5_M 0xFFFF0000 +#define AUX_SCE_REG5_4_REG5_S 16 // Field: [15:0] REG4 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG5_4_REG4_W 16 -#define AUX_SCE_REG5_4_REG4_M 0x0000FFFF -#define AUX_SCE_REG5_4_REG4_S 0 +#define AUX_SCE_REG5_4_REG4_W 16 +#define AUX_SCE_REG5_4_REG4_M 0x0000FFFF +#define AUX_SCE_REG5_4_REG4_S 0 //***************************************************************************** // @@ -335,16 +335,16 @@ // Field: [31:16] REG7 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG7_6_REG7_W 16 -#define AUX_SCE_REG7_6_REG7_M 0xFFFF0000 -#define AUX_SCE_REG7_6_REG7_S 16 +#define AUX_SCE_REG7_6_REG7_W 16 +#define AUX_SCE_REG7_6_REG7_M 0xFFFF0000 +#define AUX_SCE_REG7_6_REG7_S 16 // Field: [15:0] REG6 // // Internal. Only to be used through TI provided API. -#define AUX_SCE_REG7_6_REG6_W 16 -#define AUX_SCE_REG7_6_REG6_M 0x0000FFFF -#define AUX_SCE_REG7_6_REG6_S 0 +#define AUX_SCE_REG7_6_REG6_W 16 +#define AUX_SCE_REG7_6_REG6_M 0x0000FFFF +#define AUX_SCE_REG7_6_REG6_S 0 //***************************************************************************** // @@ -354,16 +354,16 @@ // Field: [31:16] STOP // // Internal. Only to be used through TI provided API. -#define AUX_SCE_LOOPADDR_STOP_W 16 -#define AUX_SCE_LOOPADDR_STOP_M 0xFFFF0000 -#define AUX_SCE_LOOPADDR_STOP_S 16 +#define AUX_SCE_LOOPADDR_STOP_W 16 +#define AUX_SCE_LOOPADDR_STOP_M 0xFFFF0000 +#define AUX_SCE_LOOPADDR_STOP_S 16 // Field: [15:0] START // // Internal. Only to be used through TI provided API. -#define AUX_SCE_LOOPADDR_START_W 16 -#define AUX_SCE_LOOPADDR_START_M 0x0000FFFF -#define AUX_SCE_LOOPADDR_START_S 0 +#define AUX_SCE_LOOPADDR_START_W 16 +#define AUX_SCE_LOOPADDR_START_M 0x0000FFFF +#define AUX_SCE_LOOPADDR_START_S 0 //***************************************************************************** // @@ -373,9 +373,8 @@ // Field: [7:0] ITER_LEFT // // Internal. Only to be used through TI provided API. -#define AUX_SCE_LOOPCNT_ITER_LEFT_W 8 -#define AUX_SCE_LOOPCNT_ITER_LEFT_M 0x000000FF -#define AUX_SCE_LOOPCNT_ITER_LEFT_S 0 - +#define AUX_SCE_LOOPCNT_ITER_LEFT_W 8 +#define AUX_SCE_LOOPCNT_ITER_LEFT_M 0x000000FF +#define AUX_SCE_LOOPCNT_ITER_LEFT_S 0 #endif // __AUX_SCE__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_smph.h index ec7fa57..d00d843 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_smph.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_smph.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_smph_h -* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) -* Revision: 49005 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_smph_h + * Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) + * Revision: 49005 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_SMPH_H__ #define __HW_AUX_SMPH_H__ @@ -44,31 +44,31 @@ // //***************************************************************************** // Semaphore 0 -#define AUX_SMPH_O_SMPH0 0x00000000 +#define AUX_SMPH_O_SMPH0 0x00000000 // Semaphore 1 -#define AUX_SMPH_O_SMPH1 0x00000004 +#define AUX_SMPH_O_SMPH1 0x00000004 // Semaphore 2 -#define AUX_SMPH_O_SMPH2 0x00000008 +#define AUX_SMPH_O_SMPH2 0x00000008 // Semaphore 3 -#define AUX_SMPH_O_SMPH3 0x0000000C +#define AUX_SMPH_O_SMPH3 0x0000000C // Semaphore 4 -#define AUX_SMPH_O_SMPH4 0x00000010 +#define AUX_SMPH_O_SMPH4 0x00000010 // Semaphore 5 -#define AUX_SMPH_O_SMPH5 0x00000014 +#define AUX_SMPH_O_SMPH5 0x00000014 // Semaphore 6 -#define AUX_SMPH_O_SMPH6 0x00000018 +#define AUX_SMPH_O_SMPH6 0x00000018 // Semaphore 7 -#define AUX_SMPH_O_SMPH7 0x0000001C +#define AUX_SMPH_O_SMPH7 0x0000001C // Auto Take -#define AUX_SMPH_O_AUTOTAKE 0x00000020 +#define AUX_SMPH_O_AUTOTAKE 0x00000020 //***************************************************************************** // @@ -88,10 +88,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH0_STAT 0x00000001 -#define AUX_SMPH_SMPH0_STAT_BITN 0 -#define AUX_SMPH_SMPH0_STAT_M 0x00000001 -#define AUX_SMPH_SMPH0_STAT_S 0 +#define AUX_SMPH_SMPH0_STAT 0x00000001 +#define AUX_SMPH_SMPH0_STAT_BITN 0 +#define AUX_SMPH_SMPH0_STAT_M 0x00000001 +#define AUX_SMPH_SMPH0_STAT_S 0 //***************************************************************************** // @@ -111,10 +111,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH1_STAT 0x00000001 -#define AUX_SMPH_SMPH1_STAT_BITN 0 -#define AUX_SMPH_SMPH1_STAT_M 0x00000001 -#define AUX_SMPH_SMPH1_STAT_S 0 +#define AUX_SMPH_SMPH1_STAT 0x00000001 +#define AUX_SMPH_SMPH1_STAT_BITN 0 +#define AUX_SMPH_SMPH1_STAT_M 0x00000001 +#define AUX_SMPH_SMPH1_STAT_S 0 //***************************************************************************** // @@ -134,10 +134,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH2_STAT 0x00000001 -#define AUX_SMPH_SMPH2_STAT_BITN 0 -#define AUX_SMPH_SMPH2_STAT_M 0x00000001 -#define AUX_SMPH_SMPH2_STAT_S 0 +#define AUX_SMPH_SMPH2_STAT 0x00000001 +#define AUX_SMPH_SMPH2_STAT_BITN 0 +#define AUX_SMPH_SMPH2_STAT_M 0x00000001 +#define AUX_SMPH_SMPH2_STAT_S 0 //***************************************************************************** // @@ -157,10 +157,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH3_STAT 0x00000001 -#define AUX_SMPH_SMPH3_STAT_BITN 0 -#define AUX_SMPH_SMPH3_STAT_M 0x00000001 -#define AUX_SMPH_SMPH3_STAT_S 0 +#define AUX_SMPH_SMPH3_STAT 0x00000001 +#define AUX_SMPH_SMPH3_STAT_BITN 0 +#define AUX_SMPH_SMPH3_STAT_M 0x00000001 +#define AUX_SMPH_SMPH3_STAT_S 0 //***************************************************************************** // @@ -180,10 +180,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH4_STAT 0x00000001 -#define AUX_SMPH_SMPH4_STAT_BITN 0 -#define AUX_SMPH_SMPH4_STAT_M 0x00000001 -#define AUX_SMPH_SMPH4_STAT_S 0 +#define AUX_SMPH_SMPH4_STAT 0x00000001 +#define AUX_SMPH_SMPH4_STAT_BITN 0 +#define AUX_SMPH_SMPH4_STAT_M 0x00000001 +#define AUX_SMPH_SMPH4_STAT_S 0 //***************************************************************************** // @@ -203,10 +203,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH5_STAT 0x00000001 -#define AUX_SMPH_SMPH5_STAT_BITN 0 -#define AUX_SMPH_SMPH5_STAT_M 0x00000001 -#define AUX_SMPH_SMPH5_STAT_S 0 +#define AUX_SMPH_SMPH5_STAT 0x00000001 +#define AUX_SMPH_SMPH5_STAT_BITN 0 +#define AUX_SMPH_SMPH5_STAT_M 0x00000001 +#define AUX_SMPH_SMPH5_STAT_S 0 //***************************************************************************** // @@ -226,10 +226,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH6_STAT 0x00000001 -#define AUX_SMPH_SMPH6_STAT_BITN 0 -#define AUX_SMPH_SMPH6_STAT_M 0x00000001 -#define AUX_SMPH_SMPH6_STAT_S 0 +#define AUX_SMPH_SMPH6_STAT 0x00000001 +#define AUX_SMPH_SMPH6_STAT_BITN 0 +#define AUX_SMPH_SMPH6_STAT_M 0x00000001 +#define AUX_SMPH_SMPH6_STAT_S 0 //***************************************************************************** // @@ -249,10 +249,10 @@ // // 0: Do not use. // 1: Release semaphore. -#define AUX_SMPH_SMPH7_STAT 0x00000001 -#define AUX_SMPH_SMPH7_STAT_BITN 0 -#define AUX_SMPH_SMPH7_STAT_M 0x00000001 -#define AUX_SMPH_SMPH7_STAT_S 0 +#define AUX_SMPH_SMPH7_STAT 0x00000001 +#define AUX_SMPH_SMPH7_STAT_BITN 0 +#define AUX_SMPH_SMPH7_STAT_M 0x00000001 +#define AUX_SMPH_SMPH7_STAT_S 0 //***************************************************************************** // @@ -274,9 +274,8 @@ // - Usage of this functionality must be restricted to one CPU core. // - Software must wait until AUX_EVCTL:EVSTAT0.AUX_SMPH_AUTOTAKE_DONE is 1 // before it writes a new value to SMPH_ID. -#define AUX_SMPH_AUTOTAKE_SMPH_ID_W 3 -#define AUX_SMPH_AUTOTAKE_SMPH_ID_M 0x00000007 -#define AUX_SMPH_AUTOTAKE_SMPH_ID_S 0 - +#define AUX_SMPH_AUTOTAKE_SMPH_ID_W 3 +#define AUX_SMPH_AUTOTAKE_SMPH_ID_M 0x00000007 +#define AUX_SMPH_AUTOTAKE_SMPH_ID_S 0 #endif // __AUX_SMPH__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_tdc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_tdc.h index 21d490e..ac99cb6 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_tdc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_tdc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_tdc_h -* Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) -* Revision: 49005 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_tdc_h + * Revised: 2017-05-16 19:35:21 +0200 (Tue, 16 May 2017) + * Revision: 49005 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_TDC_H__ #define __HW_AUX_TDC_H__ @@ -44,34 +44,34 @@ // //***************************************************************************** // Control -#define AUX_TDC_O_CTL 0x00000000 +#define AUX_TDC_O_CTL 0x00000000 // Status -#define AUX_TDC_O_STAT 0x00000004 +#define AUX_TDC_O_STAT 0x00000004 // Result -#define AUX_TDC_O_RESULT 0x00000008 +#define AUX_TDC_O_RESULT 0x00000008 // Saturation Configuration -#define AUX_TDC_O_SATCFG 0x0000000C +#define AUX_TDC_O_SATCFG 0x0000000C // Trigger Source -#define AUX_TDC_O_TRIGSRC 0x00000010 +#define AUX_TDC_O_TRIGSRC 0x00000010 // Trigger Counter -#define AUX_TDC_O_TRIGCNT 0x00000014 +#define AUX_TDC_O_TRIGCNT 0x00000014 // Trigger Counter Load -#define AUX_TDC_O_TRIGCNTLOAD 0x00000018 +#define AUX_TDC_O_TRIGCNTLOAD 0x00000018 // Trigger Counter Configuration -#define AUX_TDC_O_TRIGCNTCFG 0x0000001C +#define AUX_TDC_O_TRIGCNTCFG 0x0000001C // Prescaler Control -#define AUX_TDC_O_PRECTL 0x00000020 +#define AUX_TDC_O_PRECTL 0x00000020 // Prescaler Counter -#define AUX_TDC_O_PRECNT 0x00000024 +#define AUX_TDC_O_PRECNT 0x00000024 //***************************************************************************** // @@ -107,13 +107,13 @@ // This is not needed as // prerequisite for a measurement. Reliable clear // is only guaranteed from IDLE state. -#define AUX_TDC_CTL_CMD_W 2 -#define AUX_TDC_CTL_CMD_M 0x00000003 -#define AUX_TDC_CTL_CMD_S 0 -#define AUX_TDC_CTL_CMD_ABORT 0x00000003 -#define AUX_TDC_CTL_CMD_RUN 0x00000002 -#define AUX_TDC_CTL_CMD_RUN_SYNC_START 0x00000001 -#define AUX_TDC_CTL_CMD_CLR_RESULT 0x00000000 +#define AUX_TDC_CTL_CMD_W 2 +#define AUX_TDC_CTL_CMD_M 0x00000003 +#define AUX_TDC_CTL_CMD_S 0 +#define AUX_TDC_CTL_CMD_ABORT 0x00000003 +#define AUX_TDC_CTL_CMD_RUN 0x00000002 +#define AUX_TDC_CTL_CMD_RUN_SYNC_START 0x00000001 +#define AUX_TDC_CTL_CMD_CLR_RESULT 0x00000000 //***************************************************************************** // @@ -129,10 +129,10 @@ // // This field is cleared when a new measurement is started or when CLR_RESULT // is written to CTL.CMD. -#define AUX_TDC_STAT_SAT 0x00000080 -#define AUX_TDC_STAT_SAT_BITN 7 -#define AUX_TDC_STAT_SAT_M 0x00000080 -#define AUX_TDC_STAT_SAT_S 7 +#define AUX_TDC_STAT_SAT 0x00000080 +#define AUX_TDC_STAT_SAT_BITN 7 +#define AUX_TDC_STAT_SAT_M 0x00000080 +#define AUX_TDC_STAT_SAT_S 7 // Field: [6] DONE // @@ -143,10 +143,10 @@ // // This field clears when a new TDC measurement starts or when you write // CLR_RESULT to CTL.CMD. -#define AUX_TDC_STAT_DONE 0x00000040 -#define AUX_TDC_STAT_DONE_BITN 6 -#define AUX_TDC_STAT_DONE_M 0x00000040 -#define AUX_TDC_STAT_DONE_S 6 +#define AUX_TDC_STAT_DONE 0x00000040 +#define AUX_TDC_STAT_DONE_BITN 6 +#define AUX_TDC_STAT_DONE_M 0x00000040 +#define AUX_TDC_STAT_DONE_S 6 // Field: [5:0] STATE // @@ -192,20 +192,20 @@ // looks for the start condition. The state // machine waits for the fast-counter to // increment. -#define AUX_TDC_STAT_STATE_W 6 -#define AUX_TDC_STAT_STATE_M 0x0000003F -#define AUX_TDC_STAT_STATE_S 0 -#define AUX_TDC_STAT_STATE_FORCE_STOP 0x0000002E -#define AUX_TDC_STAT_STATE_START_FALL 0x0000001E -#define AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE 0x00000016 -#define AUX_TDC_STAT_STATE_POR 0x0000000F -#define AUX_TDC_STAT_STATE_GET_RESULT 0x0000000E -#define AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN 0x0000000C -#define AUX_TDC_STAT_STATE_WAIT_STOP 0x00000008 -#define AUX_TDC_STAT_STATE_CLR_CNT 0x00000007 -#define AUX_TDC_STAT_STATE_IDLE 0x00000006 -#define AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN 0x00000004 -#define AUX_TDC_STAT_STATE_WAIT_START 0x00000000 +#define AUX_TDC_STAT_STATE_W 6 +#define AUX_TDC_STAT_STATE_M 0x0000003F +#define AUX_TDC_STAT_STATE_S 0 +#define AUX_TDC_STAT_STATE_FORCE_STOP 0x0000002E +#define AUX_TDC_STAT_STATE_START_FALL 0x0000001E +#define AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE 0x00000016 +#define AUX_TDC_STAT_STATE_POR 0x0000000F +#define AUX_TDC_STAT_STATE_GET_RESULT 0x0000000E +#define AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN 0x0000000C +#define AUX_TDC_STAT_STATE_WAIT_STOP 0x00000008 +#define AUX_TDC_STAT_STATE_CLR_CNT 0x00000007 +#define AUX_TDC_STAT_STATE_IDLE 0x00000006 +#define AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN 0x00000004 +#define AUX_TDC_STAT_STATE_WAIT_START 0x00000000 //***************************************************************************** // @@ -224,9 +224,9 @@ // takes a non-zero time to stop the measurement. Hence, the maximum value of // this field becomes slightly higher than 2^24 if you configure SATCFG.LIMIT // to R24. -#define AUX_TDC_RESULT_VALUE_W 25 -#define AUX_TDC_RESULT_VALUE_M 0x01FFFFFF -#define AUX_TDC_RESULT_VALUE_S 0 +#define AUX_TDC_RESULT_VALUE_W 25 +#define AUX_TDC_RESULT_VALUE_M 0x01FFFFFF +#define AUX_TDC_RESULT_VALUE_S 0 //***************************************************************************** // @@ -267,22 +267,22 @@ // when RESULT.VALUE[13] is set. // R12 Result bit 12: TDC conversion saturates and stops // when RESULT.VALUE[12] is set. -#define AUX_TDC_SATCFG_LIMIT_W 4 -#define AUX_TDC_SATCFG_LIMIT_M 0x0000000F -#define AUX_TDC_SATCFG_LIMIT_S 0 -#define AUX_TDC_SATCFG_LIMIT_R24 0x0000000F -#define AUX_TDC_SATCFG_LIMIT_R23 0x0000000E -#define AUX_TDC_SATCFG_LIMIT_R22 0x0000000D -#define AUX_TDC_SATCFG_LIMIT_R21 0x0000000C -#define AUX_TDC_SATCFG_LIMIT_R20 0x0000000B -#define AUX_TDC_SATCFG_LIMIT_R19 0x0000000A -#define AUX_TDC_SATCFG_LIMIT_R18 0x00000009 -#define AUX_TDC_SATCFG_LIMIT_R17 0x00000008 -#define AUX_TDC_SATCFG_LIMIT_R16 0x00000007 -#define AUX_TDC_SATCFG_LIMIT_R15 0x00000006 -#define AUX_TDC_SATCFG_LIMIT_R14 0x00000005 -#define AUX_TDC_SATCFG_LIMIT_R13 0x00000004 -#define AUX_TDC_SATCFG_LIMIT_R12 0x00000003 +#define AUX_TDC_SATCFG_LIMIT_W 4 +#define AUX_TDC_SATCFG_LIMIT_M 0x0000000F +#define AUX_TDC_SATCFG_LIMIT_S 0 +#define AUX_TDC_SATCFG_LIMIT_R24 0x0000000F +#define AUX_TDC_SATCFG_LIMIT_R23 0x0000000E +#define AUX_TDC_SATCFG_LIMIT_R22 0x0000000D +#define AUX_TDC_SATCFG_LIMIT_R21 0x0000000C +#define AUX_TDC_SATCFG_LIMIT_R20 0x0000000B +#define AUX_TDC_SATCFG_LIMIT_R19 0x0000000A +#define AUX_TDC_SATCFG_LIMIT_R18 0x00000009 +#define AUX_TDC_SATCFG_LIMIT_R17 0x00000008 +#define AUX_TDC_SATCFG_LIMIT_R16 0x00000007 +#define AUX_TDC_SATCFG_LIMIT_R15 0x00000006 +#define AUX_TDC_SATCFG_LIMIT_R14 0x00000005 +#define AUX_TDC_SATCFG_LIMIT_R13 0x00000004 +#define AUX_TDC_SATCFG_LIMIT_R12 0x00000003 //***************************************************************************** // @@ -297,12 +297,12 @@ // ENUMs: // LOW TDC conversion stops when low level is detected. // HIGH TDC conversion stops when high level is detected. -#define AUX_TDC_TRIGSRC_STOP_POL 0x00002000 -#define AUX_TDC_TRIGSRC_STOP_POL_BITN 13 -#define AUX_TDC_TRIGSRC_STOP_POL_M 0x00002000 -#define AUX_TDC_TRIGSRC_STOP_POL_S 13 -#define AUX_TDC_TRIGSRC_STOP_POL_LOW 0x00002000 -#define AUX_TDC_TRIGSRC_STOP_POL_HIGH 0x00000000 +#define AUX_TDC_TRIGSRC_STOP_POL 0x00002000 +#define AUX_TDC_TRIGSRC_STOP_POL_BITN 13 +#define AUX_TDC_TRIGSRC_STOP_POL_M 0x00002000 +#define AUX_TDC_TRIGSRC_STOP_POL_S 13 +#define AUX_TDC_TRIGSRC_STOP_POL_LOW 0x00002000 +#define AUX_TDC_TRIGSRC_STOP_POL_HIGH 0x00000000 // Field: [12:8] STOP_SRC // @@ -343,41 +343,41 @@ // AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB // AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA // AON_RTC_CH2 AUX_EVCTL:EVSTAT0.AON_RTC_CH2 -#define AUX_TDC_TRIGSRC_STOP_SRC_W 5 -#define AUX_TDC_TRIGSRC_STOP_SRC_M 0x00001F00 -#define AUX_TDC_TRIGSRC_STOP_SRC_S 8 -#define AUX_TDC_TRIGSRC_STOP_SRC_TDC_PRE 0x00001F00 -#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV 0x00001E00 -#define AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF 0x00001D00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15 0x00001C00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14 0x00001B00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13 0x00001A00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12 0x00001900 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11 0x00001800 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10 0x00001700 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9 0x00001600 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8 0x00001500 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7 0x00001400 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6 0x00001300 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5 0x00001200 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4 0x00001100 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3 0x00001000 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2 0x00000F00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1 0x00000E00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0 0x00000D00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AON_PROG_WU 0x00000C00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AON_SW 0x00000B00 -#define AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX1 0x00000A00 -#define AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX0 0x00000900 -#define AUX_TDC_TRIGSRC_STOP_SRC_ADC_FIFO_ALMOST_FULL 0x00000800 -#define AUX_TDC_TRIGSRC_STOP_SRC_ADC_DONE 0x00000700 -#define AUX_TDC_TRIGSRC_STOP_SRC_SMPH_AUTOTAKE_DONE 0x00000600 -#define AUX_TDC_TRIGSRC_STOP_SRC_TIMER1_EV 0x00000500 -#define AUX_TDC_TRIGSRC_STOP_SRC_TIMER0_EV 0x00000400 -#define AUX_TDC_TRIGSRC_STOP_SRC_ISRC_RESET 0x00000300 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB 0x00000200 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA 0x00000100 -#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2 0x00000000 +#define AUX_TDC_TRIGSRC_STOP_SRC_W 5 +#define AUX_TDC_TRIGSRC_STOP_SRC_M 0x00001F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_S 8 +#define AUX_TDC_TRIGSRC_STOP_SRC_TDC_PRE 0x00001F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV 0x00001E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF 0x00001D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15 0x00001C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14 0x00001B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13 0x00001A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12 0x00001900 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11 0x00001800 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10 0x00001700 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9 0x00001600 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8 0x00001500 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7 0x00001400 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6 0x00001300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5 0x00001200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4 0x00001100 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3 0x00001000 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2 0x00000F00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1 0x00000E00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0 0x00000D00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_PROG_WU 0x00000C00 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_SW 0x00000B00 +#define AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX1 0x00000A00 +#define AUX_TDC_TRIGSRC_STOP_SRC_OBSMUX0 0x00000900 +#define AUX_TDC_TRIGSRC_STOP_SRC_ADC_FIFO_ALMOST_FULL 0x00000800 +#define AUX_TDC_TRIGSRC_STOP_SRC_ADC_DONE 0x00000700 +#define AUX_TDC_TRIGSRC_STOP_SRC_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_TDC_TRIGSRC_STOP_SRC_TIMER1_EV 0x00000500 +#define AUX_TDC_TRIGSRC_STOP_SRC_TIMER0_EV 0x00000400 +#define AUX_TDC_TRIGSRC_STOP_SRC_ISRC_RESET 0x00000300 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB 0x00000200 +#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA 0x00000100 +#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2 0x00000000 // Field: [5] START_POL // @@ -387,12 +387,12 @@ // ENUMs: // LOW TDC conversion starts when low level is detected. // HIGH TDC conversion starts when high level is detected. -#define AUX_TDC_TRIGSRC_START_POL 0x00000020 -#define AUX_TDC_TRIGSRC_START_POL_BITN 5 -#define AUX_TDC_TRIGSRC_START_POL_M 0x00000020 -#define AUX_TDC_TRIGSRC_START_POL_S 5 -#define AUX_TDC_TRIGSRC_START_POL_LOW 0x00000020 -#define AUX_TDC_TRIGSRC_START_POL_HIGH 0x00000000 +#define AUX_TDC_TRIGSRC_START_POL 0x00000020 +#define AUX_TDC_TRIGSRC_START_POL_BITN 5 +#define AUX_TDC_TRIGSRC_START_POL_M 0x00000020 +#define AUX_TDC_TRIGSRC_START_POL_S 5 +#define AUX_TDC_TRIGSRC_START_POL_LOW 0x00000020 +#define AUX_TDC_TRIGSRC_START_POL_HIGH 0x00000000 // Field: [4:0] START_SRC // @@ -433,41 +433,41 @@ // AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB // AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA // AON_RTC_CH2 AUX_EVCTL:EVSTAT0.AON_RTC_CH2 -#define AUX_TDC_TRIGSRC_START_SRC_W 5 -#define AUX_TDC_TRIGSRC_START_SRC_M 0x0000001F -#define AUX_TDC_TRIGSRC_START_SRC_S 0 -#define AUX_TDC_TRIGSRC_START_SRC_TDC_PRE 0x0000001F -#define AUX_TDC_TRIGSRC_START_SRC_MCU_EV 0x0000001E -#define AUX_TDC_TRIGSRC_START_SRC_ACLK_REF 0x0000001D -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO15 0x0000001C -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO14 0x0000001B -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO13 0x0000001A -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO12 0x00000019 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO11 0x00000018 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO10 0x00000017 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO9 0x00000016 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO8 0x00000015 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO7 0x00000014 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO6 0x00000013 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO5 0x00000012 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO4 0x00000011 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO3 0x00000010 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO2 0x0000000F -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO1 0x0000000E -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO0 0x0000000D -#define AUX_TDC_TRIGSRC_START_SRC_AON_PROG_WU 0x0000000C -#define AUX_TDC_TRIGSRC_START_SRC_AON_SW 0x0000000B -#define AUX_TDC_TRIGSRC_START_SRC_OBSMUX1 0x0000000A -#define AUX_TDC_TRIGSRC_START_SRC_OBSMUX0 0x00000009 -#define AUX_TDC_TRIGSRC_START_SRC_ADC_FIFO_ALMOST_FULL 0x00000008 -#define AUX_TDC_TRIGSRC_START_SRC_ADC_DONE 0x00000007 -#define AUX_TDC_TRIGSRC_START_SRC_SMPH_AUTOTAKE_DONE 0x00000006 -#define AUX_TDC_TRIGSRC_START_SRC_TIMER1_EV 0x00000005 -#define AUX_TDC_TRIGSRC_START_SRC_TIMER0_EV 0x00000004 -#define AUX_TDC_TRIGSRC_START_SRC_ISRC_RESET 0x00000003 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB 0x00000002 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA 0x00000001 -#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2 0x00000000 +#define AUX_TDC_TRIGSRC_START_SRC_W 5 +#define AUX_TDC_TRIGSRC_START_SRC_M 0x0000001F +#define AUX_TDC_TRIGSRC_START_SRC_S 0 +#define AUX_TDC_TRIGSRC_START_SRC_TDC_PRE 0x0000001F +#define AUX_TDC_TRIGSRC_START_SRC_MCU_EV 0x0000001E +#define AUX_TDC_TRIGSRC_START_SRC_ACLK_REF 0x0000001D +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO15 0x0000001C +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO14 0x0000001B +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO13 0x0000001A +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO12 0x00000019 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO11 0x00000018 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO10 0x00000017 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO9 0x00000016 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO8 0x00000015 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO7 0x00000014 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO6 0x00000013 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO5 0x00000012 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO4 0x00000011 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO3 0x00000010 +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO2 0x0000000F +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO1 0x0000000E +#define AUX_TDC_TRIGSRC_START_SRC_AUXIO0 0x0000000D +#define AUX_TDC_TRIGSRC_START_SRC_AON_PROG_WU 0x0000000C +#define AUX_TDC_TRIGSRC_START_SRC_AON_SW 0x0000000B +#define AUX_TDC_TRIGSRC_START_SRC_OBSMUX1 0x0000000A +#define AUX_TDC_TRIGSRC_START_SRC_OBSMUX0 0x00000009 +#define AUX_TDC_TRIGSRC_START_SRC_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_TDC_TRIGSRC_START_SRC_ADC_DONE 0x00000007 +#define AUX_TDC_TRIGSRC_START_SRC_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_TDC_TRIGSRC_START_SRC_TIMER1_EV 0x00000005 +#define AUX_TDC_TRIGSRC_START_SRC_TIMER0_EV 0x00000004 +#define AUX_TDC_TRIGSRC_START_SRC_ISRC_RESET 0x00000003 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB 0x00000002 +#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA 0x00000001 +#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2 0x00000000 //***************************************************************************** // @@ -487,9 +487,9 @@ // // When AUX_TDC:TRIGCNTCFG.EN is 1, TRIGCNTLOAD.CNT is loaded into CNT at the // start of the measurement. -#define AUX_TDC_TRIGCNT_CNT_W 16 -#define AUX_TDC_TRIGCNT_CNT_M 0x0000FFFF -#define AUX_TDC_TRIGCNT_CNT_S 0 +#define AUX_TDC_TRIGCNT_CNT_W 16 +#define AUX_TDC_TRIGCNT_CNT_M 0x0000FFFF +#define AUX_TDC_TRIGCNT_CNT_S 0 //***************************************************************************** // @@ -518,9 +518,9 @@ // // When AUX_TDC:TRIGCNTCFG.EN is 1, CNT is loaded into TRIGCNT.CNT at the start // of the measurement. -#define AUX_TDC_TRIGCNTLOAD_CNT_W 16 -#define AUX_TDC_TRIGCNTLOAD_CNT_M 0x0000FFFF -#define AUX_TDC_TRIGCNTLOAD_CNT_S 0 +#define AUX_TDC_TRIGCNTLOAD_CNT_W 16 +#define AUX_TDC_TRIGCNTLOAD_CNT_M 0x0000FFFF +#define AUX_TDC_TRIGCNTLOAD_CNT_S 0 //***************************************************************************** // @@ -535,10 +535,10 @@ // 1: Enable stop-counter. // // Change only while STAT.STATE is IDLE. -#define AUX_TDC_TRIGCNTCFG_EN 0x00000001 -#define AUX_TDC_TRIGCNTCFG_EN_BITN 0 -#define AUX_TDC_TRIGCNTCFG_EN_M 0x00000001 -#define AUX_TDC_TRIGCNTCFG_EN_S 0 +#define AUX_TDC_TRIGCNTCFG_EN 0x00000001 +#define AUX_TDC_TRIGCNTCFG_EN_BITN 0 +#define AUX_TDC_TRIGCNTCFG_EN_M 0x00000001 +#define AUX_TDC_TRIGCNTCFG_EN_S 0 //***************************************************************************** // @@ -553,10 +553,10 @@ // 1: Release reset of prescaler. // // AUX_TDC_PRE event becomes 0 when you reset the prescaler. -#define AUX_TDC_PRECTL_RESET_N 0x00000080 -#define AUX_TDC_PRECTL_RESET_N_BITN 7 -#define AUX_TDC_PRECTL_RESET_N_M 0x00000080 -#define AUX_TDC_PRECTL_RESET_N_S 7 +#define AUX_TDC_PRECTL_RESET_N 0x00000080 +#define AUX_TDC_PRECTL_RESET_N_BITN 7 +#define AUX_TDC_PRECTL_RESET_N_M 0x00000080 +#define AUX_TDC_PRECTL_RESET_N_S 7 // Field: [6] RATIO // @@ -576,12 +576,12 @@ // rising edge for every 16 rising edges of the // input. AUX_TDC_PRE event toggles on every 8th // rising edge of the input. -#define AUX_TDC_PRECTL_RATIO 0x00000040 -#define AUX_TDC_PRECTL_RATIO_BITN 6 -#define AUX_TDC_PRECTL_RATIO_M 0x00000040 -#define AUX_TDC_PRECTL_RATIO_S 6 -#define AUX_TDC_PRECTL_RATIO_DIV64 0x00000040 -#define AUX_TDC_PRECTL_RATIO_DIV16 0x00000000 +#define AUX_TDC_PRECTL_RATIO 0x00000040 +#define AUX_TDC_PRECTL_RATIO_BITN 6 +#define AUX_TDC_PRECTL_RATIO_M 0x00000040 +#define AUX_TDC_PRECTL_RATIO_S 6 +#define AUX_TDC_PRECTL_RATIO_DIV64 0x00000040 +#define AUX_TDC_PRECTL_RATIO_DIV16 0x00000000 // Field: [4:0] SRC // @@ -624,41 +624,41 @@ // AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB // AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA // AON_RTC_CH2 AUX_EVCTL:EVSTAT0.AON_RTC_CH2 -#define AUX_TDC_PRECTL_SRC_W 5 -#define AUX_TDC_PRECTL_SRC_M 0x0000001F -#define AUX_TDC_PRECTL_SRC_S 0 -#define AUX_TDC_PRECTL_SRC_ADC_IRQ 0x0000001F -#define AUX_TDC_PRECTL_SRC_MCU_EV 0x0000001E -#define AUX_TDC_PRECTL_SRC_ACLK_REF 0x0000001D -#define AUX_TDC_PRECTL_SRC_AUXIO15 0x0000001C -#define AUX_TDC_PRECTL_SRC_AUXIO14 0x0000001B -#define AUX_TDC_PRECTL_SRC_AUXIO13 0x0000001A -#define AUX_TDC_PRECTL_SRC_AUXIO12 0x00000019 -#define AUX_TDC_PRECTL_SRC_AUXIO11 0x00000018 -#define AUX_TDC_PRECTL_SRC_AUXIO10 0x00000017 -#define AUX_TDC_PRECTL_SRC_AUXIO9 0x00000016 -#define AUX_TDC_PRECTL_SRC_AUXIO8 0x00000015 -#define AUX_TDC_PRECTL_SRC_AUXIO7 0x00000014 -#define AUX_TDC_PRECTL_SRC_AUXIO6 0x00000013 -#define AUX_TDC_PRECTL_SRC_AUXIO5 0x00000012 -#define AUX_TDC_PRECTL_SRC_AUXIO4 0x00000011 -#define AUX_TDC_PRECTL_SRC_AUXIO3 0x00000010 -#define AUX_TDC_PRECTL_SRC_AUXIO2 0x0000000F -#define AUX_TDC_PRECTL_SRC_AUXIO1 0x0000000E -#define AUX_TDC_PRECTL_SRC_AUXIO0 0x0000000D -#define AUX_TDC_PRECTL_SRC_AON_PROG_WU 0x0000000C -#define AUX_TDC_PRECTL_SRC_AON_SW 0x0000000B -#define AUX_TDC_PRECTL_SRC_OBSMUX1 0x0000000A -#define AUX_TDC_PRECTL_SRC_OBSMUX0 0x00000009 -#define AUX_TDC_PRECTL_SRC_ADC_FIFO_ALMOST_FULL 0x00000008 -#define AUX_TDC_PRECTL_SRC_ADC_DONE 0x00000007 -#define AUX_TDC_PRECTL_SRC_SMPH_AUTOTAKE_DONE 0x00000006 -#define AUX_TDC_PRECTL_SRC_TIMER1_EV 0x00000005 -#define AUX_TDC_PRECTL_SRC_TIMER0_EV 0x00000004 -#define AUX_TDC_PRECTL_SRC_ISRC_RESET 0x00000003 -#define AUX_TDC_PRECTL_SRC_AUX_COMPB 0x00000002 -#define AUX_TDC_PRECTL_SRC_AUX_COMPA 0x00000001 -#define AUX_TDC_PRECTL_SRC_AON_RTC_CH2 0x00000000 +#define AUX_TDC_PRECTL_SRC_W 5 +#define AUX_TDC_PRECTL_SRC_M 0x0000001F +#define AUX_TDC_PRECTL_SRC_S 0 +#define AUX_TDC_PRECTL_SRC_ADC_IRQ 0x0000001F +#define AUX_TDC_PRECTL_SRC_MCU_EV 0x0000001E +#define AUX_TDC_PRECTL_SRC_ACLK_REF 0x0000001D +#define AUX_TDC_PRECTL_SRC_AUXIO15 0x0000001C +#define AUX_TDC_PRECTL_SRC_AUXIO14 0x0000001B +#define AUX_TDC_PRECTL_SRC_AUXIO13 0x0000001A +#define AUX_TDC_PRECTL_SRC_AUXIO12 0x00000019 +#define AUX_TDC_PRECTL_SRC_AUXIO11 0x00000018 +#define AUX_TDC_PRECTL_SRC_AUXIO10 0x00000017 +#define AUX_TDC_PRECTL_SRC_AUXIO9 0x00000016 +#define AUX_TDC_PRECTL_SRC_AUXIO8 0x00000015 +#define AUX_TDC_PRECTL_SRC_AUXIO7 0x00000014 +#define AUX_TDC_PRECTL_SRC_AUXIO6 0x00000013 +#define AUX_TDC_PRECTL_SRC_AUXIO5 0x00000012 +#define AUX_TDC_PRECTL_SRC_AUXIO4 0x00000011 +#define AUX_TDC_PRECTL_SRC_AUXIO3 0x00000010 +#define AUX_TDC_PRECTL_SRC_AUXIO2 0x0000000F +#define AUX_TDC_PRECTL_SRC_AUXIO1 0x0000000E +#define AUX_TDC_PRECTL_SRC_AUXIO0 0x0000000D +#define AUX_TDC_PRECTL_SRC_AON_PROG_WU 0x0000000C +#define AUX_TDC_PRECTL_SRC_AON_SW 0x0000000B +#define AUX_TDC_PRECTL_SRC_OBSMUX1 0x0000000A +#define AUX_TDC_PRECTL_SRC_OBSMUX0 0x00000009 +#define AUX_TDC_PRECTL_SRC_ADC_FIFO_ALMOST_FULL 0x00000008 +#define AUX_TDC_PRECTL_SRC_ADC_DONE 0x00000007 +#define AUX_TDC_PRECTL_SRC_SMPH_AUTOTAKE_DONE 0x00000006 +#define AUX_TDC_PRECTL_SRC_TIMER1_EV 0x00000005 +#define AUX_TDC_PRECTL_SRC_TIMER0_EV 0x00000004 +#define AUX_TDC_PRECTL_SRC_ISRC_RESET 0x00000003 +#define AUX_TDC_PRECTL_SRC_AUX_COMPB 0x00000002 +#define AUX_TDC_PRECTL_SRC_AUX_COMPA 0x00000001 +#define AUX_TDC_PRECTL_SRC_AON_RTC_CH2 0x00000000 //***************************************************************************** // @@ -686,9 +686,8 @@ // - The prescaler counter is reset to 2 by PRECTL.RESET_N. // - The captured value is 2 when the number of rising edges on prescaler input // is less than 3. Otherwise, captured value equals number of event pulses - 1. -#define AUX_TDC_PRECNT_CNT_W 16 -#define AUX_TDC_PRECNT_CNT_M 0x0000FFFF -#define AUX_TDC_PRECNT_CNT_S 0 - +#define AUX_TDC_PRECNT_CNT_W 16 +#define AUX_TDC_PRECNT_CNT_M 0x0000FFFF +#define AUX_TDC_PRECNT_CNT_S 0 #endif // __AUX_TDC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_timer.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_timer.h index ad0aa1e..3342ade 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_timer.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_timer.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_timer_h -* Revised: 2017-05-22 18:50:33 +0200 (Mon, 22 May 2017) -* Revision: 49040 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_timer_h + * Revised: 2017-05-22 18:50:33 +0200 (Mon, 22 May 2017) + * Revision: 49040 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_TIMER_H__ #define __HW_AUX_TIMER_H__ @@ -44,22 +44,22 @@ // //***************************************************************************** // Timer 0 Configuration -#define AUX_TIMER_O_T0CFG 0x00000000 +#define AUX_TIMER_O_T0CFG 0x00000000 // Timer 1 Configuration -#define AUX_TIMER_O_T1CFG 0x00000004 +#define AUX_TIMER_O_T1CFG 0x00000004 // Timer 0 Control -#define AUX_TIMER_O_T0CTL 0x00000008 +#define AUX_TIMER_O_T0CTL 0x00000008 // Timer 0 Target -#define AUX_TIMER_O_T0TARGET 0x0000000C +#define AUX_TIMER_O_T0TARGET 0x0000000C // Timer 1 Target -#define AUX_TIMER_O_T1TARGET 0x00000010 +#define AUX_TIMER_O_T1TARGET 0x00000010 // Timer 1 Control -#define AUX_TIMER_O_T1CTL 0x00000014 +#define AUX_TIMER_O_T1CTL 0x00000014 //***************************************************************************** // @@ -72,12 +72,12 @@ // ENUMs: // FALL Count on falling edges of TICK_SRC. // RISE Count on rising edges of TICK_SRC. -#define AUX_TIMER_T0CFG_TICK_SRC_POL 0x00002000 -#define AUX_TIMER_T0CFG_TICK_SRC_POL_BITN 13 -#define AUX_TIMER_T0CFG_TICK_SRC_POL_M 0x00002000 -#define AUX_TIMER_T0CFG_TICK_SRC_POL_S 13 -#define AUX_TIMER_T0CFG_TICK_SRC_POL_FALL 0x00002000 -#define AUX_TIMER_T0CFG_TICK_SRC_POL_RISE 0x00000000 +#define AUX_TIMER_T0CFG_TICK_SRC_POL 0x00002000 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_BITN 13 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_M 0x00002000 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_S 13 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_FALL 0x00002000 +#define AUX_TIMER_T0CFG_TICK_SRC_POL_RISE 0x00000000 // Field: [12:8] TICK_SRC // @@ -115,40 +115,40 @@ // AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB // AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA // RTC_CH2_EV AUX_EVCTL:EVSTAT0.AON_RTC_CH2 -#define AUX_TIMER_T0CFG_TICK_SRC_W 5 -#define AUX_TIMER_T0CFG_TICK_SRC_M 0x00001F00 -#define AUX_TIMER_T0CFG_TICK_SRC_S 8 -#define AUX_TIMER_T0CFG_TICK_SRC_ADC_IRQ 0x00001F00 -#define AUX_TIMER_T0CFG_TICK_SRC_MCU_EVENT 0x00001E00 -#define AUX_TIMER_T0CFG_TICK_SRC_ACLK_REF 0x00001D00 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO15 0x00001C00 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO14 0x00001B00 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO13 0x00001A00 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO12 0x00001900 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO11 0x00001800 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO10 0x00001700 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO9 0x00001600 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO8 0x00001500 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO7 0x00001400 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO6 0x00001300 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO5 0x00001200 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO4 0x00001100 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO3 0x00001000 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO2 0x00000F00 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO1 0x00000E00 -#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO0 0x00000D00 -#define AUX_TIMER_T0CFG_TICK_SRC_AON_PROG_WU 0x00000C00 -#define AUX_TIMER_T0CFG_TICK_SRC_AON_SW 0x00000B00 -#define AUX_TIMER_T0CFG_TICK_SRC_OBSMUX1 0x00000A00 -#define AUX_TIMER_T0CFG_TICK_SRC_OBSMUX0 0x00000900 -#define AUX_TIMER_T0CFG_TICK_SRC_RTC_4KHZ 0x00000800 -#define AUX_TIMER_T0CFG_TICK_SRC_ADC_DONE 0x00000700 -#define AUX_TIMER_T0CFG_TICK_SRC_SMPH_AUTOTAKE_DONE 0x00000600 -#define AUX_TIMER_T0CFG_TICK_SRC_TIMER1_EV 0x00000500 -#define AUX_TIMER_T0CFG_TICK_SRC_TDC_DONE 0x00000300 -#define AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPB 0x00000200 -#define AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPA 0x00000100 -#define AUX_TIMER_T0CFG_TICK_SRC_RTC_CH2_EV 0x00000000 +#define AUX_TIMER_T0CFG_TICK_SRC_W 5 +#define AUX_TIMER_T0CFG_TICK_SRC_M 0x00001F00 +#define AUX_TIMER_T0CFG_TICK_SRC_S 8 +#define AUX_TIMER_T0CFG_TICK_SRC_ADC_IRQ 0x00001F00 +#define AUX_TIMER_T0CFG_TICK_SRC_MCU_EVENT 0x00001E00 +#define AUX_TIMER_T0CFG_TICK_SRC_ACLK_REF 0x00001D00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO15 0x00001C00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO14 0x00001B00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO13 0x00001A00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO12 0x00001900 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO11 0x00001800 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO10 0x00001700 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO9 0x00001600 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO8 0x00001500 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO7 0x00001400 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO6 0x00001300 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO5 0x00001200 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO4 0x00001100 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO3 0x00001000 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO2 0x00000F00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO1 0x00000E00 +#define AUX_TIMER_T0CFG_TICK_SRC_AUXIO0 0x00000D00 +#define AUX_TIMER_T0CFG_TICK_SRC_AON_PROG_WU 0x00000C00 +#define AUX_TIMER_T0CFG_TICK_SRC_AON_SW 0x00000B00 +#define AUX_TIMER_T0CFG_TICK_SRC_OBSMUX1 0x00000A00 +#define AUX_TIMER_T0CFG_TICK_SRC_OBSMUX0 0x00000900 +#define AUX_TIMER_T0CFG_TICK_SRC_RTC_4KHZ 0x00000800 +#define AUX_TIMER_T0CFG_TICK_SRC_ADC_DONE 0x00000700 +#define AUX_TIMER_T0CFG_TICK_SRC_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_TIMER_T0CFG_TICK_SRC_TIMER1_EV 0x00000500 +#define AUX_TIMER_T0CFG_TICK_SRC_TDC_DONE 0x00000300 +#define AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPB 0x00000200 +#define AUX_TIMER_T0CFG_TICK_SRC_AUX_COMPA 0x00000100 +#define AUX_TIMER_T0CFG_TICK_SRC_RTC_CH2_EV 0x00000000 // Field: [7:4] PRE // @@ -159,9 +159,9 @@ // 0x2: Divide by 4. // ... // 0xF: Divide by 32,768. -#define AUX_TIMER_T0CFG_PRE_W 4 -#define AUX_TIMER_T0CFG_PRE_M 0x000000F0 -#define AUX_TIMER_T0CFG_PRE_S 4 +#define AUX_TIMER_T0CFG_PRE_W 4 +#define AUX_TIMER_T0CFG_PRE_M 0x000000F0 +#define AUX_TIMER_T0CFG_PRE_S 4 // Field: [1] MODE // @@ -171,12 +171,12 @@ // ENUMs: // TICK Use event set by TICK_SRC as source for prescaler. // CLK Use AUX clock as source for prescaler. -#define AUX_TIMER_T0CFG_MODE 0x00000002 -#define AUX_TIMER_T0CFG_MODE_BITN 1 -#define AUX_TIMER_T0CFG_MODE_M 0x00000002 -#define AUX_TIMER_T0CFG_MODE_S 1 -#define AUX_TIMER_T0CFG_MODE_TICK 0x00000002 -#define AUX_TIMER_T0CFG_MODE_CLK 0x00000000 +#define AUX_TIMER_T0CFG_MODE 0x00000002 +#define AUX_TIMER_T0CFG_MODE_BITN 1 +#define AUX_TIMER_T0CFG_MODE_M 0x00000002 +#define AUX_TIMER_T0CFG_MODE_S 1 +#define AUX_TIMER_T0CFG_MODE_TICK 0x00000002 +#define AUX_TIMER_T0CFG_MODE_CLK 0x00000000 // Field: [0] RELOAD // @@ -193,12 +193,12 @@ // T0CTL.EN becomes 0 when the counter value // becomes equal to or greater than // T0TARGET.VALUE. -#define AUX_TIMER_T0CFG_RELOAD 0x00000001 -#define AUX_TIMER_T0CFG_RELOAD_BITN 0 -#define AUX_TIMER_T0CFG_RELOAD_M 0x00000001 -#define AUX_TIMER_T0CFG_RELOAD_S 0 -#define AUX_TIMER_T0CFG_RELOAD_CONT 0x00000001 -#define AUX_TIMER_T0CFG_RELOAD_MAN 0x00000000 +#define AUX_TIMER_T0CFG_RELOAD 0x00000001 +#define AUX_TIMER_T0CFG_RELOAD_BITN 0 +#define AUX_TIMER_T0CFG_RELOAD_M 0x00000001 +#define AUX_TIMER_T0CFG_RELOAD_S 0 +#define AUX_TIMER_T0CFG_RELOAD_CONT 0x00000001 +#define AUX_TIMER_T0CFG_RELOAD_MAN 0x00000000 //***************************************************************************** // @@ -211,12 +211,12 @@ // ENUMs: // FALL Count on falling edges of TICK_SRC. // RISE Count on rising edges of TICK_SRC. -#define AUX_TIMER_T1CFG_TICK_SRC_POL 0x00002000 -#define AUX_TIMER_T1CFG_TICK_SRC_POL_BITN 13 -#define AUX_TIMER_T1CFG_TICK_SRC_POL_M 0x00002000 -#define AUX_TIMER_T1CFG_TICK_SRC_POL_S 13 -#define AUX_TIMER_T1CFG_TICK_SRC_POL_FALL 0x00002000 -#define AUX_TIMER_T1CFG_TICK_SRC_POL_RISE 0x00000000 +#define AUX_TIMER_T1CFG_TICK_SRC_POL 0x00002000 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_BITN 13 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_M 0x00002000 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_S 13 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_FALL 0x00002000 +#define AUX_TIMER_T1CFG_TICK_SRC_POL_RISE 0x00000000 // Field: [12:8] TICK_SRC // @@ -254,40 +254,40 @@ // AUX_COMPB AUX_EVCTL:EVSTAT0.AUX_COMPB // AUX_COMPA AUX_EVCTL:EVSTAT0.AUX_COMPA // RTC_CH2_EV AUX_EVCTL:EVSTAT0.AON_RTC_CH2 -#define AUX_TIMER_T1CFG_TICK_SRC_W 5 -#define AUX_TIMER_T1CFG_TICK_SRC_M 0x00001F00 -#define AUX_TIMER_T1CFG_TICK_SRC_S 8 -#define AUX_TIMER_T1CFG_TICK_SRC_ADC_IRQ 0x00001F00 -#define AUX_TIMER_T1CFG_TICK_SRC_MCU_EVENT 0x00001E00 -#define AUX_TIMER_T1CFG_TICK_SRC_ACLK_REF 0x00001D00 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO15 0x00001C00 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO14 0x00001B00 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO13 0x00001A00 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO12 0x00001900 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO11 0x00001800 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO10 0x00001700 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO9 0x00001600 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO8 0x00001500 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO7 0x00001400 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO6 0x00001300 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO5 0x00001200 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO4 0x00001100 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO3 0x00001000 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO2 0x00000F00 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO1 0x00000E00 -#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO0 0x00000D00 -#define AUX_TIMER_T1CFG_TICK_SRC_AON_PROG_WU 0x00000C00 -#define AUX_TIMER_T1CFG_TICK_SRC_AON_SW 0x00000B00 -#define AUX_TIMER_T1CFG_TICK_SRC_OBSMUX1 0x00000A00 -#define AUX_TIMER_T1CFG_TICK_SRC_OBSMUX0 0x00000900 -#define AUX_TIMER_T1CFG_TICK_SRC_RTC_4KHZ 0x00000800 -#define AUX_TIMER_T1CFG_TICK_SRC_ADC_DONE 0x00000700 -#define AUX_TIMER_T1CFG_TICK_SRC_SMPH_AUTOTAKE_DONE 0x00000600 -#define AUX_TIMER_T1CFG_TICK_SRC_TIMER0_EV 0x00000400 -#define AUX_TIMER_T1CFG_TICK_SRC_TDC_DONE 0x00000300 -#define AUX_TIMER_T1CFG_TICK_SRC_AUX_COMPB 0x00000200 -#define AUX_TIMER_T1CFG_TICK_SRC_AUX_COMPA 0x00000100 -#define AUX_TIMER_T1CFG_TICK_SRC_RTC_CH2_EV 0x00000000 +#define AUX_TIMER_T1CFG_TICK_SRC_W 5 +#define AUX_TIMER_T1CFG_TICK_SRC_M 0x00001F00 +#define AUX_TIMER_T1CFG_TICK_SRC_S 8 +#define AUX_TIMER_T1CFG_TICK_SRC_ADC_IRQ 0x00001F00 +#define AUX_TIMER_T1CFG_TICK_SRC_MCU_EVENT 0x00001E00 +#define AUX_TIMER_T1CFG_TICK_SRC_ACLK_REF 0x00001D00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO15 0x00001C00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO14 0x00001B00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO13 0x00001A00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO12 0x00001900 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO11 0x00001800 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO10 0x00001700 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO9 0x00001600 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO8 0x00001500 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO7 0x00001400 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO6 0x00001300 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO5 0x00001200 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO4 0x00001100 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO3 0x00001000 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO2 0x00000F00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO1 0x00000E00 +#define AUX_TIMER_T1CFG_TICK_SRC_AUXIO0 0x00000D00 +#define AUX_TIMER_T1CFG_TICK_SRC_AON_PROG_WU 0x00000C00 +#define AUX_TIMER_T1CFG_TICK_SRC_AON_SW 0x00000B00 +#define AUX_TIMER_T1CFG_TICK_SRC_OBSMUX1 0x00000A00 +#define AUX_TIMER_T1CFG_TICK_SRC_OBSMUX0 0x00000900 +#define AUX_TIMER_T1CFG_TICK_SRC_RTC_4KHZ 0x00000800 +#define AUX_TIMER_T1CFG_TICK_SRC_ADC_DONE 0x00000700 +#define AUX_TIMER_T1CFG_TICK_SRC_SMPH_AUTOTAKE_DONE 0x00000600 +#define AUX_TIMER_T1CFG_TICK_SRC_TIMER0_EV 0x00000400 +#define AUX_TIMER_T1CFG_TICK_SRC_TDC_DONE 0x00000300 +#define AUX_TIMER_T1CFG_TICK_SRC_AUX_COMPB 0x00000200 +#define AUX_TIMER_T1CFG_TICK_SRC_AUX_COMPA 0x00000100 +#define AUX_TIMER_T1CFG_TICK_SRC_RTC_CH2_EV 0x00000000 // Field: [7:4] PRE // @@ -298,9 +298,9 @@ // 0x2: Divide by 4. // ... // 0xF: Divide by 32,768. -#define AUX_TIMER_T1CFG_PRE_W 4 -#define AUX_TIMER_T1CFG_PRE_M 0x000000F0 -#define AUX_TIMER_T1CFG_PRE_S 4 +#define AUX_TIMER_T1CFG_PRE_W 4 +#define AUX_TIMER_T1CFG_PRE_M 0x000000F0 +#define AUX_TIMER_T1CFG_PRE_S 4 // Field: [1] MODE // @@ -310,12 +310,12 @@ // ENUMs: // TICK Use event set by TICK_SRC as source for prescaler. // CLK Use AUX clock as source for prescaler. -#define AUX_TIMER_T1CFG_MODE 0x00000002 -#define AUX_TIMER_T1CFG_MODE_BITN 1 -#define AUX_TIMER_T1CFG_MODE_M 0x00000002 -#define AUX_TIMER_T1CFG_MODE_S 1 -#define AUX_TIMER_T1CFG_MODE_TICK 0x00000002 -#define AUX_TIMER_T1CFG_MODE_CLK 0x00000000 +#define AUX_TIMER_T1CFG_MODE 0x00000002 +#define AUX_TIMER_T1CFG_MODE_BITN 1 +#define AUX_TIMER_T1CFG_MODE_M 0x00000002 +#define AUX_TIMER_T1CFG_MODE_S 1 +#define AUX_TIMER_T1CFG_MODE_TICK 0x00000002 +#define AUX_TIMER_T1CFG_MODE_CLK 0x00000000 // Field: [0] RELOAD // @@ -332,12 +332,12 @@ // T1CTL.EN becomes 0 when the counter value // becomes equal to or greater than // T1TARGET.VALUE. -#define AUX_TIMER_T1CFG_RELOAD 0x00000001 -#define AUX_TIMER_T1CFG_RELOAD_BITN 0 -#define AUX_TIMER_T1CFG_RELOAD_M 0x00000001 -#define AUX_TIMER_T1CFG_RELOAD_S 0 -#define AUX_TIMER_T1CFG_RELOAD_CONT 0x00000001 -#define AUX_TIMER_T1CFG_RELOAD_MAN 0x00000000 +#define AUX_TIMER_T1CFG_RELOAD 0x00000001 +#define AUX_TIMER_T1CFG_RELOAD_BITN 0 +#define AUX_TIMER_T1CFG_RELOAD_M 0x00000001 +#define AUX_TIMER_T1CFG_RELOAD_S 0 +#define AUX_TIMER_T1CFG_RELOAD_CONT 0x00000001 +#define AUX_TIMER_T1CFG_RELOAD_MAN 0x00000000 //***************************************************************************** // @@ -352,10 +352,10 @@ // 1: Enable Timer 0. // // The counter restarts from 0 when you enable Timer 0. -#define AUX_TIMER_T0CTL_EN 0x00000001 -#define AUX_TIMER_T0CTL_EN_BITN 0 -#define AUX_TIMER_T0CTL_EN_M 0x00000001 -#define AUX_TIMER_T0CTL_EN_S 0 +#define AUX_TIMER_T0CTL_EN 0x00000001 +#define AUX_TIMER_T0CTL_EN_BITN 0 +#define AUX_TIMER_T0CTL_EN_M 0x00000001 +#define AUX_TIMER_T0CTL_EN_S 0 //***************************************************************************** // @@ -387,9 +387,9 @@ // // // It is allowed to update the VALUE while the timer runs. -#define AUX_TIMER_T0TARGET_VALUE_W 16 -#define AUX_TIMER_T0TARGET_VALUE_M 0x0000FFFF -#define AUX_TIMER_T0TARGET_VALUE_S 0 +#define AUX_TIMER_T0TARGET_VALUE_W 16 +#define AUX_TIMER_T0TARGET_VALUE_M 0x0000FFFF +#define AUX_TIMER_T0TARGET_VALUE_S 0 //***************************************************************************** // @@ -421,9 +421,9 @@ // // // It is allowed to update the VALUE while the timer runs. -#define AUX_TIMER_T1TARGET_VALUE_W 8 -#define AUX_TIMER_T1TARGET_VALUE_M 0x000000FF -#define AUX_TIMER_T1TARGET_VALUE_S 0 +#define AUX_TIMER_T1TARGET_VALUE_W 8 +#define AUX_TIMER_T1TARGET_VALUE_M 0x000000FF +#define AUX_TIMER_T1TARGET_VALUE_S 0 //***************************************************************************** // @@ -438,10 +438,9 @@ // 1: Enable Timer 1. // // The counter restarts from 0 when you enable Timer 1. -#define AUX_TIMER_T1CTL_EN 0x00000001 -#define AUX_TIMER_T1CTL_EN_BITN 0 -#define AUX_TIMER_T1CTL_EN_M 0x00000001 -#define AUX_TIMER_T1CTL_EN_S 0 - +#define AUX_TIMER_T1CTL_EN 0x00000001 +#define AUX_TIMER_T1CTL_EN_BITN 0 +#define AUX_TIMER_T1CTL_EN_M 0x00000001 +#define AUX_TIMER_T1CTL_EN_S 0 #endif // __AUX_TIMER__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_wuc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_wuc.h index f7dd3b0..db554b7 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_wuc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_aux_wuc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_aux_wuc_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_aux_wuc_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_AUX_WUC_H__ #define __HW_AUX_WUC_H__ @@ -44,61 +44,61 @@ // //***************************************************************************** // Module Clock Enable -#define AUX_WUC_O_MODCLKEN0 0x00000000 +#define AUX_WUC_O_MODCLKEN0 0x00000000 // Power Off Request -#define AUX_WUC_O_PWROFFREQ 0x00000004 +#define AUX_WUC_O_PWROFFREQ 0x00000004 // Power Down Request -#define AUX_WUC_O_PWRDWNREQ 0x00000008 +#define AUX_WUC_O_PWRDWNREQ 0x00000008 // Power Down Acknowledgment -#define AUX_WUC_O_PWRDWNACK 0x0000000C +#define AUX_WUC_O_PWRDWNACK 0x0000000C // Low Frequency Clock Request -#define AUX_WUC_O_CLKLFREQ 0x00000010 +#define AUX_WUC_O_CLKLFREQ 0x00000010 // Low Frequency Clock Acknowledgment -#define AUX_WUC_O_CLKLFACK 0x00000014 +#define AUX_WUC_O_CLKLFACK 0x00000014 // Wake-up Event Flags -#define AUX_WUC_O_WUEVFLAGS 0x00000028 +#define AUX_WUC_O_WUEVFLAGS 0x00000028 // Wake-up Event Clear -#define AUX_WUC_O_WUEVCLR 0x0000002C +#define AUX_WUC_O_WUEVCLR 0x0000002C // ADC Clock Control -#define AUX_WUC_O_ADCCLKCTL 0x00000030 +#define AUX_WUC_O_ADCCLKCTL 0x00000030 // TDC Clock Control -#define AUX_WUC_O_TDCCLKCTL 0x00000034 +#define AUX_WUC_O_TDCCLKCTL 0x00000034 // Reference Clock Control -#define AUX_WUC_O_REFCLKCTL 0x00000038 +#define AUX_WUC_O_REFCLKCTL 0x00000038 // Real Time Counter Sub Second Increment 0 -#define AUX_WUC_O_RTCSUBSECINC0 0x0000003C +#define AUX_WUC_O_RTCSUBSECINC0 0x0000003C // Real Time Counter Sub Second Increment 1 -#define AUX_WUC_O_RTCSUBSECINC1 0x00000040 +#define AUX_WUC_O_RTCSUBSECINC1 0x00000040 // Real Time Counter Sub Second Increment Control -#define AUX_WUC_O_RTCSUBSECINCCTL 0x00000044 +#define AUX_WUC_O_RTCSUBSECINCCTL 0x00000044 // MCU Bus Control -#define AUX_WUC_O_MCUBUSCTL 0x00000048 +#define AUX_WUC_O_MCUBUSCTL 0x00000048 // MCU Bus Status -#define AUX_WUC_O_MCUBUSSTAT 0x0000004C +#define AUX_WUC_O_MCUBUSSTAT 0x0000004C // AON Domain Control Status -#define AUX_WUC_O_AONCTLSTAT 0x00000050 +#define AUX_WUC_O_AONCTLSTAT 0x00000050 // AUX Input Output Latch -#define AUX_WUC_O_AUXIOLATCH 0x00000054 +#define AUX_WUC_O_AUXIOLATCH 0x00000054 // Module Clock Enable 1 -#define AUX_WUC_O_MODCLKEN1 0x0000005C +#define AUX_WUC_O_MODCLKEN1 0x0000005C //***************************************************************************** // @@ -111,12 +111,12 @@ // ENUMs: // EN System CPU has requested clock for AUX_ADI4 // DIS System CPU has not requested clock for AUX_ADI4 -#define AUX_WUC_MODCLKEN0_AUX_ADI4 0x00000080 -#define AUX_WUC_MODCLKEN0_AUX_ADI4_BITN 7 -#define AUX_WUC_MODCLKEN0_AUX_ADI4_M 0x00000080 -#define AUX_WUC_MODCLKEN0_AUX_ADI4_S 7 -#define AUX_WUC_MODCLKEN0_AUX_ADI4_EN 0x00000080 -#define AUX_WUC_MODCLKEN0_AUX_ADI4_DIS 0x00000000 +#define AUX_WUC_MODCLKEN0_AUX_ADI4 0x00000080 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_BITN 7 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_M 0x00000080 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_S 7 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_EN 0x00000080 +#define AUX_WUC_MODCLKEN0_AUX_ADI4_DIS 0x00000000 // Field: [6] AUX_DDI0_OSC // @@ -125,12 +125,12 @@ // EN System CPU has requested clock for AUX_DDI0_OSC // DIS System CPU has not requested clock for // AUX_DDI0_OSC -#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC 0x00000040 -#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_BITN 6 -#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_M 0x00000040 -#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_S 6 -#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_EN 0x00000040 -#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_DIS 0x00000000 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC 0x00000040 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_BITN 6 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_M 0x00000040 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_S 6 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_EN 0x00000040 +#define AUX_WUC_MODCLKEN0_AUX_DDI0_OSC_DIS 0x00000000 // Field: [5] TDC // @@ -141,12 +141,12 @@ // ENUMs: // EN System CPU has requested clock for TDC // DIS System CPU has not requested clock for TDC -#define AUX_WUC_MODCLKEN0_TDC 0x00000020 -#define AUX_WUC_MODCLKEN0_TDC_BITN 5 -#define AUX_WUC_MODCLKEN0_TDC_M 0x00000020 -#define AUX_WUC_MODCLKEN0_TDC_S 5 -#define AUX_WUC_MODCLKEN0_TDC_EN 0x00000020 -#define AUX_WUC_MODCLKEN0_TDC_DIS 0x00000000 +#define AUX_WUC_MODCLKEN0_TDC 0x00000020 +#define AUX_WUC_MODCLKEN0_TDC_BITN 5 +#define AUX_WUC_MODCLKEN0_TDC_M 0x00000020 +#define AUX_WUC_MODCLKEN0_TDC_S 5 +#define AUX_WUC_MODCLKEN0_TDC_EN 0x00000020 +#define AUX_WUC_MODCLKEN0_TDC_DIS 0x00000000 // Field: [4] ANAIF // @@ -157,12 +157,12 @@ // ENUMs: // EN System CPU has requested clock for ANAIF // DIS System CPU has not requested clock for ANAIF -#define AUX_WUC_MODCLKEN0_ANAIF 0x00000010 -#define AUX_WUC_MODCLKEN0_ANAIF_BITN 4 -#define AUX_WUC_MODCLKEN0_ANAIF_M 0x00000010 -#define AUX_WUC_MODCLKEN0_ANAIF_S 4 -#define AUX_WUC_MODCLKEN0_ANAIF_EN 0x00000010 -#define AUX_WUC_MODCLKEN0_ANAIF_DIS 0x00000000 +#define AUX_WUC_MODCLKEN0_ANAIF 0x00000010 +#define AUX_WUC_MODCLKEN0_ANAIF_BITN 4 +#define AUX_WUC_MODCLKEN0_ANAIF_M 0x00000010 +#define AUX_WUC_MODCLKEN0_ANAIF_S 4 +#define AUX_WUC_MODCLKEN0_ANAIF_EN 0x00000010 +#define AUX_WUC_MODCLKEN0_ANAIF_DIS 0x00000000 // Field: [3] TIMER // @@ -170,12 +170,12 @@ // ENUMs: // EN System CPU has requested clock for TIMER // DIS System CPU has not requested clock for TIMER -#define AUX_WUC_MODCLKEN0_TIMER 0x00000008 -#define AUX_WUC_MODCLKEN0_TIMER_BITN 3 -#define AUX_WUC_MODCLKEN0_TIMER_M 0x00000008 -#define AUX_WUC_MODCLKEN0_TIMER_S 3 -#define AUX_WUC_MODCLKEN0_TIMER_EN 0x00000008 -#define AUX_WUC_MODCLKEN0_TIMER_DIS 0x00000000 +#define AUX_WUC_MODCLKEN0_TIMER 0x00000008 +#define AUX_WUC_MODCLKEN0_TIMER_BITN 3 +#define AUX_WUC_MODCLKEN0_TIMER_M 0x00000008 +#define AUX_WUC_MODCLKEN0_TIMER_S 3 +#define AUX_WUC_MODCLKEN0_TIMER_EN 0x00000008 +#define AUX_WUC_MODCLKEN0_TIMER_DIS 0x00000000 // Field: [2] AIODIO1 // @@ -183,12 +183,12 @@ // ENUMs: // EN System CPU has requested clock for AIODIO1 // DIS System CPU has not requested clock for AIODIO1 -#define AUX_WUC_MODCLKEN0_AIODIO1 0x00000004 -#define AUX_WUC_MODCLKEN0_AIODIO1_BITN 2 -#define AUX_WUC_MODCLKEN0_AIODIO1_M 0x00000004 -#define AUX_WUC_MODCLKEN0_AIODIO1_S 2 -#define AUX_WUC_MODCLKEN0_AIODIO1_EN 0x00000004 -#define AUX_WUC_MODCLKEN0_AIODIO1_DIS 0x00000000 +#define AUX_WUC_MODCLKEN0_AIODIO1 0x00000004 +#define AUX_WUC_MODCLKEN0_AIODIO1_BITN 2 +#define AUX_WUC_MODCLKEN0_AIODIO1_M 0x00000004 +#define AUX_WUC_MODCLKEN0_AIODIO1_S 2 +#define AUX_WUC_MODCLKEN0_AIODIO1_EN 0x00000004 +#define AUX_WUC_MODCLKEN0_AIODIO1_DIS 0x00000000 // Field: [1] AIODIO0 // @@ -196,12 +196,12 @@ // ENUMs: // EN System CPU has requested clock for AIODIO0 // DIS System CPU has not requested clock for AIODIO0 -#define AUX_WUC_MODCLKEN0_AIODIO0 0x00000002 -#define AUX_WUC_MODCLKEN0_AIODIO0_BITN 1 -#define AUX_WUC_MODCLKEN0_AIODIO0_M 0x00000002 -#define AUX_WUC_MODCLKEN0_AIODIO0_S 1 -#define AUX_WUC_MODCLKEN0_AIODIO0_EN 0x00000002 -#define AUX_WUC_MODCLKEN0_AIODIO0_DIS 0x00000000 +#define AUX_WUC_MODCLKEN0_AIODIO0 0x00000002 +#define AUX_WUC_MODCLKEN0_AIODIO0_BITN 1 +#define AUX_WUC_MODCLKEN0_AIODIO0_M 0x00000002 +#define AUX_WUC_MODCLKEN0_AIODIO0_S 1 +#define AUX_WUC_MODCLKEN0_AIODIO0_EN 0x00000002 +#define AUX_WUC_MODCLKEN0_AIODIO0_DIS 0x00000000 // Field: [0] SMPH // @@ -209,12 +209,12 @@ // ENUMs: // EN System CPU has requested clock for SMPH // DIS System CPU has not requested clock for SMPH -#define AUX_WUC_MODCLKEN0_SMPH 0x00000001 -#define AUX_WUC_MODCLKEN0_SMPH_BITN 0 -#define AUX_WUC_MODCLKEN0_SMPH_M 0x00000001 -#define AUX_WUC_MODCLKEN0_SMPH_S 0 -#define AUX_WUC_MODCLKEN0_SMPH_EN 0x00000001 -#define AUX_WUC_MODCLKEN0_SMPH_DIS 0x00000000 +#define AUX_WUC_MODCLKEN0_SMPH 0x00000001 +#define AUX_WUC_MODCLKEN0_SMPH_BITN 0 +#define AUX_WUC_MODCLKEN0_SMPH_M 0x00000001 +#define AUX_WUC_MODCLKEN0_SMPH_S 0 +#define AUX_WUC_MODCLKEN0_SMPH_EN 0x00000001 +#define AUX_WUC_MODCLKEN0_SMPH_DIS 0x00000000 //***************************************************************************** // @@ -231,10 +231,10 @@ // // The request will only happen if AONCTLSTAT.AUX_FORCE_ON = 0 and // MCUBUSSTAT.DISCONNECTED=1. -#define AUX_WUC_PWROFFREQ_REQ 0x00000001 -#define AUX_WUC_PWROFFREQ_REQ_BITN 0 -#define AUX_WUC_PWROFFREQ_REQ_M 0x00000001 -#define AUX_WUC_PWROFFREQ_REQ_S 0 +#define AUX_WUC_PWROFFREQ_REQ 0x00000001 +#define AUX_WUC_PWROFFREQ_REQ_BITN 0 +#define AUX_WUC_PWROFFREQ_REQ_M 0x00000001 +#define AUX_WUC_PWROFFREQ_REQ_S 0 //***************************************************************************** // @@ -251,10 +251,10 @@ // When REQ is 1 one shall assume that the system is in power down, and that // current supply is limited. When setting REQ = 0, one shall assume that the // system is in power down until PWRDWNACK.ACK = 0 -#define AUX_WUC_PWRDWNREQ_REQ 0x00000001 -#define AUX_WUC_PWRDWNREQ_REQ_BITN 0 -#define AUX_WUC_PWRDWNREQ_REQ_M 0x00000001 -#define AUX_WUC_PWRDWNREQ_REQ_S 0 +#define AUX_WUC_PWRDWNREQ_REQ 0x00000001 +#define AUX_WUC_PWRDWNREQ_REQ_BITN 0 +#define AUX_WUC_PWRDWNREQ_REQ_M 0x00000001 +#define AUX_WUC_PWRDWNREQ_REQ_S 0 //***************************************************************************** // @@ -273,10 +273,10 @@ // The system CPU cannot use this bit since the bus bridge between MCU domain // and AUX domain is always disconnected when this bit is set. For AUX_SCE use // only -#define AUX_WUC_PWRDWNACK_ACK 0x00000001 -#define AUX_WUC_PWRDWNACK_ACK_BITN 0 -#define AUX_WUC_PWRDWNACK_ACK_M 0x00000001 -#define AUX_WUC_PWRDWNACK_ACK_S 0 +#define AUX_WUC_PWRDWNACK_ACK 0x00000001 +#define AUX_WUC_PWRDWNACK_ACK_BITN 0 +#define AUX_WUC_PWRDWNACK_ACK_M 0x00000001 +#define AUX_WUC_PWRDWNACK_ACK_S 0 //***************************************************************************** // @@ -292,10 +292,10 @@ // 1: Request low frequency clock SCLK_LF as the clock source for AUX // // This bit must not be modified unless CLKLFACK.ACK matches the current value -#define AUX_WUC_CLKLFREQ_REQ 0x00000001 -#define AUX_WUC_CLKLFREQ_REQ_BITN 0 -#define AUX_WUC_CLKLFREQ_REQ_M 0x00000001 -#define AUX_WUC_CLKLFREQ_REQ_S 0 +#define AUX_WUC_CLKLFREQ_REQ 0x00000001 +#define AUX_WUC_CLKLFREQ_REQ_BITN 0 +#define AUX_WUC_CLKLFREQ_REQ_M 0x00000001 +#define AUX_WUC_CLKLFREQ_REQ_S 0 //***************************************************************************** // @@ -310,10 +310,10 @@ // the system state // 1: Acknowledgement that the low frequency clock SCLK_LF is the clock source // for AUX -#define AUX_WUC_CLKLFACK_ACK 0x00000001 -#define AUX_WUC_CLKLFACK_ACK_BITN 0 -#define AUX_WUC_CLKLFACK_ACK_M 0x00000001 -#define AUX_WUC_CLKLFACK_ACK_S 0 +#define AUX_WUC_CLKLFACK_ACK 0x00000001 +#define AUX_WUC_CLKLFACK_ACK_BITN 0 +#define AUX_WUC_CLKLFACK_ACK_M 0x00000001 +#define AUX_WUC_CLKLFACK_ACK_S 0 //***************************************************************************** // @@ -327,29 +327,29 @@ // this event is a wake-up event. To make the AON_RTC_CH2 a wake-up event for // the AUX domain configure it as a wake-up event in AON_EVENT:AUXWUSEL.WU0_EV, // AON_EVENT:AUXWUSEL.WU1_EV or AON_EVENT:AUXWUSEL.WU2_EV. -#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2 0x00000004 -#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_BITN 2 -#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_M 0x00000004 -#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_S 2 +#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2 0x00000004 +#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_BITN 2 +#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_M 0x00000004 +#define AUX_WUC_WUEVFLAGS_AON_RTC_CH2_S 2 // Field: [1] AON_SW // // Indicates pending event triggered by system CPU writing a 1 to // AON_WUC:AUXCTL.SWEV. -#define AUX_WUC_WUEVFLAGS_AON_SW 0x00000002 -#define AUX_WUC_WUEVFLAGS_AON_SW_BITN 1 -#define AUX_WUC_WUEVFLAGS_AON_SW_M 0x00000002 -#define AUX_WUC_WUEVFLAGS_AON_SW_S 1 +#define AUX_WUC_WUEVFLAGS_AON_SW 0x00000002 +#define AUX_WUC_WUEVFLAGS_AON_SW_BITN 1 +#define AUX_WUC_WUEVFLAGS_AON_SW_M 0x00000002 +#define AUX_WUC_WUEVFLAGS_AON_SW_S 1 // Field: [0] AON_PROG_WU // // Indicates pending event triggered by the sources selected in // AON_EVENT:AUXWUSEL.WU0_EV, AON_EVENT:AUXWUSEL.WU1_EV and // AON_EVENT:AUXWUSEL.WU2_EV. -#define AUX_WUC_WUEVFLAGS_AON_PROG_WU 0x00000001 -#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_BITN 0 -#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_M 0x00000001 -#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_S 0 +#define AUX_WUC_WUEVFLAGS_AON_PROG_WU 0x00000001 +#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_BITN 0 +#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_M 0x00000001 +#define AUX_WUC_WUEVFLAGS_AON_PROG_WU_S 0 //***************************************************************************** // @@ -363,20 +363,20 @@ // WUEVFLAGS.AON_PROG_WU // // This bit must remain set until WUEVFLAGS.AON_RTC_CH2 returns to 0. -#define AUX_WUC_WUEVCLR_AON_RTC_CH2 0x00000004 -#define AUX_WUC_WUEVCLR_AON_RTC_CH2_BITN 2 -#define AUX_WUC_WUEVCLR_AON_RTC_CH2_M 0x00000004 -#define AUX_WUC_WUEVCLR_AON_RTC_CH2_S 2 +#define AUX_WUC_WUEVCLR_AON_RTC_CH2 0x00000004 +#define AUX_WUC_WUEVCLR_AON_RTC_CH2_BITN 2 +#define AUX_WUC_WUEVCLR_AON_RTC_CH2_M 0x00000004 +#define AUX_WUC_WUEVCLR_AON_RTC_CH2_S 2 // Field: [1] AON_SW // // Set to clear the WUEVFLAGS.AON_SW wake-up event. // // This bit must remain set until WUEVFLAGS.AON_SW returns to 0. -#define AUX_WUC_WUEVCLR_AON_SW 0x00000002 -#define AUX_WUC_WUEVCLR_AON_SW_BITN 1 -#define AUX_WUC_WUEVCLR_AON_SW_M 0x00000002 -#define AUX_WUC_WUEVCLR_AON_SW_S 1 +#define AUX_WUC_WUEVCLR_AON_SW 0x00000002 +#define AUX_WUC_WUEVCLR_AON_SW_BITN 1 +#define AUX_WUC_WUEVCLR_AON_SW_M 0x00000002 +#define AUX_WUC_WUEVCLR_AON_SW_S 1 // Field: [0] AON_PROG_WU // @@ -389,10 +389,10 @@ // effect. // // This bit must remain set until WUEVFLAGS.AON_PROG_WU returns to 0. -#define AUX_WUC_WUEVCLR_AON_PROG_WU 0x00000001 -#define AUX_WUC_WUEVCLR_AON_PROG_WU_BITN 0 -#define AUX_WUC_WUEVCLR_AON_PROG_WU_M 0x00000001 -#define AUX_WUC_WUEVCLR_AON_PROG_WU_S 0 +#define AUX_WUC_WUEVCLR_AON_PROG_WU 0x00000001 +#define AUX_WUC_WUEVCLR_AON_PROG_WU_BITN 0 +#define AUX_WUC_WUEVCLR_AON_PROG_WU_M 0x00000001 +#define AUX_WUC_WUEVCLR_AON_PROG_WU_S 0 //***************************************************************************** // @@ -402,20 +402,20 @@ // Field: [1] ACK // // Acknowledges the last value written to REQ. -#define AUX_WUC_ADCCLKCTL_ACK 0x00000002 -#define AUX_WUC_ADCCLKCTL_ACK_BITN 1 -#define AUX_WUC_ADCCLKCTL_ACK_M 0x00000002 -#define AUX_WUC_ADCCLKCTL_ACK_S 1 +#define AUX_WUC_ADCCLKCTL_ACK 0x00000002 +#define AUX_WUC_ADCCLKCTL_ACK_BITN 1 +#define AUX_WUC_ADCCLKCTL_ACK_M 0x00000002 +#define AUX_WUC_ADCCLKCTL_ACK_S 1 // Field: [0] REQ // // Enables(1) or disables (0) the ADC internal clock. // // This bit must not be modified unless ACK matches the current value. -#define AUX_WUC_ADCCLKCTL_REQ 0x00000001 -#define AUX_WUC_ADCCLKCTL_REQ_BITN 0 -#define AUX_WUC_ADCCLKCTL_REQ_M 0x00000001 -#define AUX_WUC_ADCCLKCTL_REQ_S 0 +#define AUX_WUC_ADCCLKCTL_REQ 0x00000001 +#define AUX_WUC_ADCCLKCTL_REQ_BITN 0 +#define AUX_WUC_ADCCLKCTL_REQ_M 0x00000001 +#define AUX_WUC_ADCCLKCTL_REQ_S 0 //***************************************************************************** // @@ -425,20 +425,20 @@ // Field: [1] ACK // // Acknowledges the last value written to REQ. -#define AUX_WUC_TDCCLKCTL_ACK 0x00000002 -#define AUX_WUC_TDCCLKCTL_ACK_BITN 1 -#define AUX_WUC_TDCCLKCTL_ACK_M 0x00000002 -#define AUX_WUC_TDCCLKCTL_ACK_S 1 +#define AUX_WUC_TDCCLKCTL_ACK 0x00000002 +#define AUX_WUC_TDCCLKCTL_ACK_BITN 1 +#define AUX_WUC_TDCCLKCTL_ACK_M 0x00000002 +#define AUX_WUC_TDCCLKCTL_ACK_S 1 // Field: [0] REQ // // Enables(1) or disables (0) the TDC counter clock source. // // This bit must not be modified unless ACK matches the current value. -#define AUX_WUC_TDCCLKCTL_REQ 0x00000001 -#define AUX_WUC_TDCCLKCTL_REQ_BITN 0 -#define AUX_WUC_TDCCLKCTL_REQ_M 0x00000001 -#define AUX_WUC_TDCCLKCTL_REQ_S 0 +#define AUX_WUC_TDCCLKCTL_REQ 0x00000001 +#define AUX_WUC_TDCCLKCTL_REQ_BITN 0 +#define AUX_WUC_TDCCLKCTL_REQ_M 0x00000001 +#define AUX_WUC_TDCCLKCTL_REQ_S 0 //***************************************************************************** // @@ -448,20 +448,20 @@ // Field: [1] ACK // // Acknowledges the last value written to REQ. -#define AUX_WUC_REFCLKCTL_ACK 0x00000002 -#define AUX_WUC_REFCLKCTL_ACK_BITN 1 -#define AUX_WUC_REFCLKCTL_ACK_M 0x00000002 -#define AUX_WUC_REFCLKCTL_ACK_S 1 +#define AUX_WUC_REFCLKCTL_ACK 0x00000002 +#define AUX_WUC_REFCLKCTL_ACK_BITN 1 +#define AUX_WUC_REFCLKCTL_ACK_M 0x00000002 +#define AUX_WUC_REFCLKCTL_ACK_S 1 // Field: [0] REQ // // Enables(1) or disables (0) the TDC reference clock source. // // This bit must not be modified unless ACK matches the current value. -#define AUX_WUC_REFCLKCTL_REQ 0x00000001 -#define AUX_WUC_REFCLKCTL_REQ_BITN 0 -#define AUX_WUC_REFCLKCTL_REQ_M 0x00000001 -#define AUX_WUC_REFCLKCTL_REQ_S 0 +#define AUX_WUC_REFCLKCTL_REQ 0x00000001 +#define AUX_WUC_REFCLKCTL_REQ_BITN 0 +#define AUX_WUC_REFCLKCTL_REQ_M 0x00000001 +#define AUX_WUC_REFCLKCTL_REQ_S 0 //***************************************************************************** // @@ -471,9 +471,9 @@ // Field: [15:0] INC15_0 // // Bits 15:0 of the RTC sub-second increment value. -#define AUX_WUC_RTCSUBSECINC0_INC15_0_W 16 -#define AUX_WUC_RTCSUBSECINC0_INC15_0_M 0x0000FFFF -#define AUX_WUC_RTCSUBSECINC0_INC15_0_S 0 +#define AUX_WUC_RTCSUBSECINC0_INC15_0_W 16 +#define AUX_WUC_RTCSUBSECINC0_INC15_0_M 0x0000FFFF +#define AUX_WUC_RTCSUBSECINC0_INC15_0_S 0 //***************************************************************************** // @@ -483,9 +483,9 @@ // Field: [7:0] INC23_16 // // Bits 23:16 of the RTC sub-second increment value. -#define AUX_WUC_RTCSUBSECINC1_INC23_16_W 8 -#define AUX_WUC_RTCSUBSECINC1_INC23_16_M 0x000000FF -#define AUX_WUC_RTCSUBSECINC1_INC23_16_S 0 +#define AUX_WUC_RTCSUBSECINC1_INC23_16_W 8 +#define AUX_WUC_RTCSUBSECINC1_INC23_16_M 0x000000FF +#define AUX_WUC_RTCSUBSECINC1_INC23_16_S 0 //***************************************************************************** // @@ -495,10 +495,10 @@ // Field: [1] UPD_ACK // // Acknowledgment of the UPD_REQ. -#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK 0x00000002 -#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_BITN 1 -#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_M 0x00000002 -#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_S 1 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK 0x00000002 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_BITN 1 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_M 0x00000002 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_ACK_S 1 // Field: [0] UPD_REQ // @@ -508,10 +508,10 @@ // 1: New sub second increment is available // // This bit must not be modified unless UPD_ACK matches the current value. -#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ 0x00000001 -#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_BITN 0 -#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_M 0x00000001 -#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_S 0 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ 0x00000001 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_BITN 0 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_M 0x00000001 +#define AUX_WUC_RTCSUBSECINCCTL_UPD_REQ_S 0 //***************************************************************************** // @@ -529,10 +529,10 @@ // It is recommended that this bit is set and remains set after initial // power-up, and that the system CPU uses AON_WUC:AUX_CTL.AUX_FORCE_ON to // connect/disconnect the bus. -#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ 0x00000001 -#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_BITN 0 -#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_M 0x00000001 -#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_S 0 +#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ 0x00000001 +#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_BITN 0 +#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_M 0x00000001 +#define AUX_WUC_MCUBUSCTL_DISCONNECT_REQ_S 0 //***************************************************************************** // @@ -543,10 +543,10 @@ // // Indicates whether the AUX domain and MCU domain buses are currently // disconnected (1) or connected (0). -#define AUX_WUC_MCUBUSSTAT_DISCONNECTED 0x00000002 -#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_BITN 1 -#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_M 0x00000002 -#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_S 1 +#define AUX_WUC_MCUBUSSTAT_DISCONNECTED 0x00000002 +#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_BITN 1 +#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_M 0x00000002 +#define AUX_WUC_MCUBUSSTAT_DISCONNECTED_S 1 // Field: [0] DISCONNECT_ACK // @@ -555,10 +555,10 @@ // // Note that if AON_WUC:AUXCTL.AUX_FORCE_ON = 1 a reconnect to the MCU domain // bus will be made regardless of the state of MCUBUSCTL.DISCONNECT_REQ -#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK 0x00000001 -#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_BITN 0 -#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_M 0x00000001 -#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_S 0 +#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK 0x00000001 +#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_BITN 0 +#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_M 0x00000001 +#define AUX_WUC_MCUBUSSTAT_DISCONNECT_ACK_S 0 //***************************************************************************** // @@ -568,18 +568,18 @@ // Field: [1] AUX_FORCE_ON // // Status of AON_WUC:AUX_CTL.AUX_FORCE_ON. -#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON 0x00000002 -#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_BITN 1 -#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_M 0x00000002 -#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_S 1 +#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON 0x00000002 +#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_BITN 1 +#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_M 0x00000002 +#define AUX_WUC_AONCTLSTAT_AUX_FORCE_ON_S 1 // Field: [0] SCE_RUN_EN // // Status of AON_WUC:AUX_CTL.SCE_RUN_EN. -#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN 0x00000001 -#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_BITN 0 -#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_M 0x00000001 -#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_S 0 +#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN 0x00000001 +#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_BITN 0 +#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_M 0x00000001 +#define AUX_WUC_AONCTLSTAT_SCE_RUN_EN_S 0 //***************************************************************************** // @@ -598,12 +598,12 @@ // ENUMs: // TRANSP Latches are transparent ( open ) // STATIC Latches are static ( closed ) -#define AUX_WUC_AUXIOLATCH_EN 0x00000001 -#define AUX_WUC_AUXIOLATCH_EN_BITN 0 -#define AUX_WUC_AUXIOLATCH_EN_M 0x00000001 -#define AUX_WUC_AUXIOLATCH_EN_S 0 -#define AUX_WUC_AUXIOLATCH_EN_TRANSP 0x00000001 -#define AUX_WUC_AUXIOLATCH_EN_STATIC 0x00000000 +#define AUX_WUC_AUXIOLATCH_EN 0x00000001 +#define AUX_WUC_AUXIOLATCH_EN_BITN 0 +#define AUX_WUC_AUXIOLATCH_EN_M 0x00000001 +#define AUX_WUC_AUXIOLATCH_EN_S 0 +#define AUX_WUC_AUXIOLATCH_EN_TRANSP 0x00000001 +#define AUX_WUC_AUXIOLATCH_EN_STATIC 0x00000000 //***************************************************************************** // @@ -616,12 +616,12 @@ // ENUMs: // EN AUX_SCE has requested clock for AUX_ADI4 // DIS AUX_SCE has not requested clock for AUX_ADI4 -#define AUX_WUC_MODCLKEN1_AUX_ADI4 0x00000080 -#define AUX_WUC_MODCLKEN1_AUX_ADI4_BITN 7 -#define AUX_WUC_MODCLKEN1_AUX_ADI4_M 0x00000080 -#define AUX_WUC_MODCLKEN1_AUX_ADI4_S 7 -#define AUX_WUC_MODCLKEN1_AUX_ADI4_EN 0x00000080 -#define AUX_WUC_MODCLKEN1_AUX_ADI4_DIS 0x00000000 +#define AUX_WUC_MODCLKEN1_AUX_ADI4 0x00000080 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_BITN 7 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_M 0x00000080 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_S 7 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_EN 0x00000080 +#define AUX_WUC_MODCLKEN1_AUX_ADI4_DIS 0x00000000 // Field: [6] AUX_DDI0_OSC // @@ -629,12 +629,12 @@ // ENUMs: // EN AUX_SCE has requested clock for AUX_DDI0_OSC // DIS AUX_SCE has not requested clock for AUX_DDI0_OSC -#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC 0x00000040 -#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_BITN 6 -#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_M 0x00000040 -#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_S 6 -#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_EN 0x00000040 -#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_DIS 0x00000000 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC 0x00000040 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_BITN 6 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_M 0x00000040 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_S 6 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_EN 0x00000040 +#define AUX_WUC_MODCLKEN1_AUX_DDI0_OSC_DIS 0x00000000 // Field: [4] ANAIF // @@ -642,12 +642,12 @@ // ENUMs: // EN AUX_SCE has requested clock for ANAIF // DIS AUX_SCE has not requested clock for ANAIF -#define AUX_WUC_MODCLKEN1_ANAIF 0x00000010 -#define AUX_WUC_MODCLKEN1_ANAIF_BITN 4 -#define AUX_WUC_MODCLKEN1_ANAIF_M 0x00000010 -#define AUX_WUC_MODCLKEN1_ANAIF_S 4 -#define AUX_WUC_MODCLKEN1_ANAIF_EN 0x00000010 -#define AUX_WUC_MODCLKEN1_ANAIF_DIS 0x00000000 +#define AUX_WUC_MODCLKEN1_ANAIF 0x00000010 +#define AUX_WUC_MODCLKEN1_ANAIF_BITN 4 +#define AUX_WUC_MODCLKEN1_ANAIF_M 0x00000010 +#define AUX_WUC_MODCLKEN1_ANAIF_S 4 +#define AUX_WUC_MODCLKEN1_ANAIF_EN 0x00000010 +#define AUX_WUC_MODCLKEN1_ANAIF_DIS 0x00000000 // Field: [3] TIMER // @@ -655,12 +655,12 @@ // ENUMs: // EN AUX_SCE has requested clock for TIMER // DIS AUX_SCE has not requested clock for TIMER -#define AUX_WUC_MODCLKEN1_TIMER 0x00000008 -#define AUX_WUC_MODCLKEN1_TIMER_BITN 3 -#define AUX_WUC_MODCLKEN1_TIMER_M 0x00000008 -#define AUX_WUC_MODCLKEN1_TIMER_S 3 -#define AUX_WUC_MODCLKEN1_TIMER_EN 0x00000008 -#define AUX_WUC_MODCLKEN1_TIMER_DIS 0x00000000 +#define AUX_WUC_MODCLKEN1_TIMER 0x00000008 +#define AUX_WUC_MODCLKEN1_TIMER_BITN 3 +#define AUX_WUC_MODCLKEN1_TIMER_M 0x00000008 +#define AUX_WUC_MODCLKEN1_TIMER_S 3 +#define AUX_WUC_MODCLKEN1_TIMER_EN 0x00000008 +#define AUX_WUC_MODCLKEN1_TIMER_DIS 0x00000000 // Field: [2] AIODIO1 // @@ -668,12 +668,12 @@ // ENUMs: // EN AUX_SCE has requested clock for AIODIO1 // DIS AUX_SCE has not requested clock for AIODIO1 -#define AUX_WUC_MODCLKEN1_AIODIO1 0x00000004 -#define AUX_WUC_MODCLKEN1_AIODIO1_BITN 2 -#define AUX_WUC_MODCLKEN1_AIODIO1_M 0x00000004 -#define AUX_WUC_MODCLKEN1_AIODIO1_S 2 -#define AUX_WUC_MODCLKEN1_AIODIO1_EN 0x00000004 -#define AUX_WUC_MODCLKEN1_AIODIO1_DIS 0x00000000 +#define AUX_WUC_MODCLKEN1_AIODIO1 0x00000004 +#define AUX_WUC_MODCLKEN1_AIODIO1_BITN 2 +#define AUX_WUC_MODCLKEN1_AIODIO1_M 0x00000004 +#define AUX_WUC_MODCLKEN1_AIODIO1_S 2 +#define AUX_WUC_MODCLKEN1_AIODIO1_EN 0x00000004 +#define AUX_WUC_MODCLKEN1_AIODIO1_DIS 0x00000000 // Field: [1] AIODIO0 // @@ -681,12 +681,12 @@ // ENUMs: // EN AUX_SCE has requested clock for AIODIO0 // DIS AUX_SCE has not requested clock for AIODIO0 -#define AUX_WUC_MODCLKEN1_AIODIO0 0x00000002 -#define AUX_WUC_MODCLKEN1_AIODIO0_BITN 1 -#define AUX_WUC_MODCLKEN1_AIODIO0_M 0x00000002 -#define AUX_WUC_MODCLKEN1_AIODIO0_S 1 -#define AUX_WUC_MODCLKEN1_AIODIO0_EN 0x00000002 -#define AUX_WUC_MODCLKEN1_AIODIO0_DIS 0x00000000 +#define AUX_WUC_MODCLKEN1_AIODIO0 0x00000002 +#define AUX_WUC_MODCLKEN1_AIODIO0_BITN 1 +#define AUX_WUC_MODCLKEN1_AIODIO0_M 0x00000002 +#define AUX_WUC_MODCLKEN1_AIODIO0_S 1 +#define AUX_WUC_MODCLKEN1_AIODIO0_EN 0x00000002 +#define AUX_WUC_MODCLKEN1_AIODIO0_DIS 0x00000000 // Field: [0] SMPH // @@ -694,12 +694,11 @@ // ENUMs: // EN AUX_SCE has requested clock for SMPH // DIS AUX_SCE has not requested clock for SMPH -#define AUX_WUC_MODCLKEN1_SMPH 0x00000001 -#define AUX_WUC_MODCLKEN1_SMPH_BITN 0 -#define AUX_WUC_MODCLKEN1_SMPH_M 0x00000001 -#define AUX_WUC_MODCLKEN1_SMPH_S 0 -#define AUX_WUC_MODCLKEN1_SMPH_EN 0x00000001 -#define AUX_WUC_MODCLKEN1_SMPH_DIS 0x00000000 - +#define AUX_WUC_MODCLKEN1_SMPH 0x00000001 +#define AUX_WUC_MODCLKEN1_SMPH_BITN 0 +#define AUX_WUC_MODCLKEN1_SMPH_M 0x00000001 +#define AUX_WUC_MODCLKEN1_SMPH_S 0 +#define AUX_WUC_MODCLKEN1_SMPH_EN 0x00000001 +#define AUX_WUC_MODCLKEN1_SMPH_DIS 0x00000000 #endif // __AUX_WUC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ccfg.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ccfg.h index 31b9b2a..4542dc1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ccfg.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ccfg.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_ccfg_h -* Revised: 2017-02-06 19:32:22 +0100 (Mon, 06 Feb 2017) -* Revision: 48408 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_ccfg_h + * Revised: 2017-02-06 19:32:22 +0100 (Mon, 06 Feb 2017) + * Revision: 48408 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CCFG_H__ #define __HW_CCFG_H__ @@ -44,70 +44,70 @@ // //***************************************************************************** // Extern LF clock configuration -#define CCFG_O_EXT_LF_CLK 0x00000FA8 +#define CCFG_O_EXT_LF_CLK 0x00000FA8 // Mode Configuration 1 -#define CCFG_O_MODE_CONF_1 0x00000FAC +#define CCFG_O_MODE_CONF_1 0x00000FAC // CCFG Size and Disable Flags -#define CCFG_O_SIZE_AND_DIS_FLAGS 0x00000FB0 +#define CCFG_O_SIZE_AND_DIS_FLAGS 0x00000FB0 // Mode Configuration 0 -#define CCFG_O_MODE_CONF 0x00000FB4 +#define CCFG_O_MODE_CONF 0x00000FB4 // Voltage Load 0 -#define CCFG_O_VOLT_LOAD_0 0x00000FB8 +#define CCFG_O_VOLT_LOAD_0 0x00000FB8 // Voltage Load 1 -#define CCFG_O_VOLT_LOAD_1 0x00000FBC +#define CCFG_O_VOLT_LOAD_1 0x00000FBC // Real Time Clock Offset -#define CCFG_O_RTC_OFFSET 0x00000FC0 +#define CCFG_O_RTC_OFFSET 0x00000FC0 // Frequency Offset -#define CCFG_O_FREQ_OFFSET 0x00000FC4 +#define CCFG_O_FREQ_OFFSET 0x00000FC4 // IEEE MAC Address 0 -#define CCFG_O_IEEE_MAC_0 0x00000FC8 +#define CCFG_O_IEEE_MAC_0 0x00000FC8 // IEEE MAC Address 1 -#define CCFG_O_IEEE_MAC_1 0x00000FCC +#define CCFG_O_IEEE_MAC_1 0x00000FCC // IEEE BLE Address 0 -#define CCFG_O_IEEE_BLE_0 0x00000FD0 +#define CCFG_O_IEEE_BLE_0 0x00000FD0 // IEEE BLE Address 1 -#define CCFG_O_IEEE_BLE_1 0x00000FD4 +#define CCFG_O_IEEE_BLE_1 0x00000FD4 // Bootloader Configuration -#define CCFG_O_BL_CONFIG 0x00000FD8 +#define CCFG_O_BL_CONFIG 0x00000FD8 // Erase Configuration -#define CCFG_O_ERASE_CONF 0x00000FDC +#define CCFG_O_ERASE_CONF 0x00000FDC // TI Options -#define CCFG_O_CCFG_TI_OPTIONS 0x00000FE0 +#define CCFG_O_CCFG_TI_OPTIONS 0x00000FE0 // Test Access Points Enable 0 -#define CCFG_O_CCFG_TAP_DAP_0 0x00000FE4 +#define CCFG_O_CCFG_TAP_DAP_0 0x00000FE4 // Test Access Points Enable 1 -#define CCFG_O_CCFG_TAP_DAP_1 0x00000FE8 +#define CCFG_O_CCFG_TAP_DAP_1 0x00000FE8 // Image Valid -#define CCFG_O_IMAGE_VALID_CONF 0x00000FEC +#define CCFG_O_IMAGE_VALID_CONF 0x00000FEC // Protect Sectors 0-31 -#define CCFG_O_CCFG_PROT_31_0 0x00000FF0 +#define CCFG_O_CCFG_PROT_31_0 0x00000FF0 // Protect Sectors 32-63 -#define CCFG_O_CCFG_PROT_63_32 0x00000FF4 +#define CCFG_O_CCFG_PROT_63_32 0x00000FF4 // Protect Sectors 64-95 -#define CCFG_O_CCFG_PROT_95_64 0x00000FF8 +#define CCFG_O_CCFG_PROT_95_64 0x00000FF8 // Protect Sectors 96-127 -#define CCFG_O_CCFG_PROT_127_96 0x00000FFC +#define CCFG_O_CCFG_PROT_127_96 0x00000FFC //***************************************************************************** // @@ -120,9 +120,9 @@ // SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL. The selected DIO // will be marked as reserved by the pin driver (TI-RTOS environment) and hence // not selectable for other usage. -#define CCFG_EXT_LF_CLK_DIO_W 8 -#define CCFG_EXT_LF_CLK_DIO_M 0xFF000000 -#define CCFG_EXT_LF_CLK_DIO_S 24 +#define CCFG_EXT_LF_CLK_DIO_W 8 +#define CCFG_EXT_LF_CLK_DIO_M 0xFF000000 +#define CCFG_EXT_LF_CLK_DIO_S 24 // Field: [23:0] RTC_INCREMENT // @@ -130,9 +130,9 @@ // written to AON_RTC:SUBSECINC.VALUEINC. Defined as follows: // EXT_LF_CLK.RTC_INCREMENT = 2^38/InputClockFrequency in Hertz (e.g.: // RTC_INCREMENT=0x800000 for InputClockFrequency=32768 Hz) -#define CCFG_EXT_LF_CLK_RTC_INCREMENT_W 24 -#define CCFG_EXT_LF_CLK_RTC_INCREMENT_M 0x00FFFFFF -#define CCFG_EXT_LF_CLK_RTC_INCREMENT_S 0 +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_W 24 +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_M 0x00FFFFFF +#define CCFG_EXT_LF_CLK_RTC_INCREMENT_S 0 //***************************************************************************** // @@ -153,9 +153,9 @@ // NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must // be called regularly to apply this field (handled automatically if using TI // RTOS!). -#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_W 4 -#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M 0x00F00000 -#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S 20 +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_W 4 +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M 0x00F00000 +#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S 20 // Field: [19] ALT_DCDC_DITHER_EN // @@ -163,10 +163,10 @@ // (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). // 0: Dither disable // 1: Dither enable -#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x00080000 -#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_BITN 19 -#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M 0x00080000 -#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S 19 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x00080000 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_BITN 19 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M 0x00080000 +#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S 19 // Field: [18:16] ALT_DCDC_IPEAK // @@ -179,35 +179,35 @@ // 4: 47mA // ... // 7: 59mA (max) -#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_W 3 -#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M 0x00070000 -#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S 16 +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_W 3 +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M 0x00070000 +#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S 16 // Field: [15:12] DELTA_IBIAS_INIT // // Signed delta value for IBIAS_INIT. Delta value only applies if // SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. // See FCFG1:AMPCOMP_CTRL1.IBIAS_INIT -#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W 4 -#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M 0x0000F000 -#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S 12 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W 4 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M 0x0000F000 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S 12 // Field: [11:8] DELTA_IBIAS_OFFSET // // Signed delta value for IBIAS_OFFSET. Delta value only applies if // SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. // See FCFG1:AMPCOMP_CTRL1.IBIAS_OFFSET -#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W 4 -#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M 0x00000F00 -#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S 8 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W 4 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M 0x00000F00 +#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S 8 // Field: [7:0] XOSC_MAX_START // // Unsigned value of maximum XOSC startup time (worst case) in units of 100us. // Value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. -#define CCFG_MODE_CONF_1_XOSC_MAX_START_W 8 -#define CCFG_MODE_CONF_1_XOSC_MAX_START_M 0x000000FF -#define CCFG_MODE_CONF_1_XOSC_MAX_START_S 0 +#define CCFG_MODE_CONF_1_XOSC_MAX_START_W 8 +#define CCFG_MODE_CONF_1_XOSC_MAX_START_M 0x000000FF +#define CCFG_MODE_CONF_1_XOSC_MAX_START_S 0 //***************************************************************************** // @@ -217,18 +217,18 @@ // Field: [31:16] SIZE_OF_CCFG // // Total size of CCFG in bytes. -#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_W 16 -#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M 0xFFFF0000 -#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S 16 +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_W 16 +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M 0xFFFF0000 +#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S 16 // Field: [15:4] DISABLE_FLAGS // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_W 12 -#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M 0x0000FFF0 -#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S 4 +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_W 12 +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M 0x0000FFF0 +#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S 4 // Field: [3] DIS_TCXO // @@ -237,10 +237,10 @@ // 1: TCXO functionality disabled. // Note: // An external TCXO is required if DIS_TCXO = 0. -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x00000008 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_BITN 3 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M 0x00000008 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S 3 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x00000008 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_BITN 3 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M 0x00000008 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S 3 // Field: [2] DIS_GPRAM // @@ -253,10 +253,10 @@ // enabled. // See: // VIMS:CTL.MODE -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x00000004 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_BITN 2 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M 0x00000004 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S 2 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x00000004 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_BITN 2 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M 0x00000004 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S 2 // Field: [1] DIS_ALT_DCDC_SETTING // @@ -271,10 +271,10 @@ // NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must // be called regularly to apply this field (handled automatically if using TI // RTOS!). -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x00000002 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_BITN 1 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M 0x00000002 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S 1 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x00000002 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_BITN 1 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M 0x00000002 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S 1 // Field: [0] DIS_XOSC_OVR // @@ -285,10 +285,10 @@ // MODE_CONF_1.DELTA_IBIAS_INIT // MODE_CONF_1.DELTA_IBIAS_OFFSET // MODE_CONF_1.XOSC_MAX_START -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x00000001 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_BITN 0 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M 0x00000001 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S 0 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x00000001 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_BITN 0 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M 0x00000001 +#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S 0 //***************************************************************************** // @@ -305,9 +305,9 @@ // 0x0 (0) : Delta = +1 // ... // 0x7 (7) : Delta = +8 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W 4 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M 0xF0000000 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S 28 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W 4 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M 0xF0000000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S 28 // Field: [27] DCDC_RECHARGE // @@ -318,10 +318,10 @@ // NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must // be called regularly to apply this field (handled automatically if using TI // RTOS!). -#define CCFG_MODE_CONF_DCDC_RECHARGE 0x08000000 -#define CCFG_MODE_CONF_DCDC_RECHARGE_BITN 27 -#define CCFG_MODE_CONF_DCDC_RECHARGE_M 0x08000000 -#define CCFG_MODE_CONF_DCDC_RECHARGE_S 27 +#define CCFG_MODE_CONF_DCDC_RECHARGE 0x08000000 +#define CCFG_MODE_CONF_DCDC_RECHARGE_BITN 27 +#define CCFG_MODE_CONF_DCDC_RECHARGE_M 0x08000000 +#define CCFG_MODE_CONF_DCDC_RECHARGE_S 27 // Field: [26] DCDC_ACTIVE // @@ -332,20 +332,20 @@ // NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must // be called regularly to apply this field (handled automatically if using TI // RTOS!). -#define CCFG_MODE_CONF_DCDC_ACTIVE 0x04000000 -#define CCFG_MODE_CONF_DCDC_ACTIVE_BITN 26 -#define CCFG_MODE_CONF_DCDC_ACTIVE_M 0x04000000 -#define CCFG_MODE_CONF_DCDC_ACTIVE_S 26 +#define CCFG_MODE_CONF_DCDC_ACTIVE 0x04000000 +#define CCFG_MODE_CONF_DCDC_ACTIVE_BITN 26 +#define CCFG_MODE_CONF_DCDC_ACTIVE_M 0x04000000 +#define CCFG_MODE_CONF_DCDC_ACTIVE_S 26 // Field: [25] VDDR_EXT_LOAD // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_MODE_CONF_VDDR_EXT_LOAD 0x02000000 -#define CCFG_MODE_CONF_VDDR_EXT_LOAD_BITN 25 -#define CCFG_MODE_CONF_VDDR_EXT_LOAD_M 0x02000000 -#define CCFG_MODE_CONF_VDDR_EXT_LOAD_S 25 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD 0x02000000 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_BITN 25 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_M 0x02000000 +#define CCFG_MODE_CONF_VDDR_EXT_LOAD_S 25 // Field: [24] VDDS_BOD_LEVEL // @@ -353,10 +353,10 @@ // 0: VDDS BOD level is 2.0 V (necessary for maximum PA output power on // CC13x0). // 1: VDDS BOD level is 1.8 V (or 1.7 V for external regulator mode) (default). -#define CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x01000000 -#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_BITN 24 -#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_M 0x01000000 -#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_S 24 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x01000000 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_BITN 24 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_M 0x01000000 +#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_S 24 // Field: [23:22] SCLK_LF_OPTION // @@ -378,13 +378,13 @@ // trimDevice() xxWare boot function). Standby // power mode is not supported when using this // clock source. -#define CCFG_MODE_CONF_SCLK_LF_OPTION_W 2 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_M 0x00C00000 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_S 22 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF 0x00C00000 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF 0x00800000 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF 0x00400000 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF 0x00000000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_W 2 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_M 0x00C00000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_S 22 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF 0x00C00000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF 0x00800000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF 0x00400000 +#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF 0x00000000 // Field: [21] VDDR_TRIM_SLEEP_TC // @@ -398,20 +398,20 @@ // Delta = max (delta, min(8, floor(62-temp)/8)) // Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is the current // temperature in degrees C. -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x00200000 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_BITN 21 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M 0x00200000 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S 21 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x00200000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_BITN 21 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M 0x00200000 +#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S 21 // Field: [20] RTC_COMP // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_MODE_CONF_RTC_COMP 0x00100000 -#define CCFG_MODE_CONF_RTC_COMP_BITN 20 -#define CCFG_MODE_CONF_RTC_COMP_M 0x00100000 -#define CCFG_MODE_CONF_RTC_COMP_S 20 +#define CCFG_MODE_CONF_RTC_COMP 0x00100000 +#define CCFG_MODE_CONF_RTC_COMP_BITN 20 +#define CCFG_MODE_CONF_RTC_COMP_M 0x00100000 +#define CCFG_MODE_CONF_RTC_COMP_S 20 // Field: [19:18] XOSC_FREQ // @@ -422,12 +422,12 @@ // 24M 24 MHz XOSC_HF // 48M 48 MHz XOSC_HF // HPOSC HPOSC -#define CCFG_MODE_CONF_XOSC_FREQ_W 2 -#define CCFG_MODE_CONF_XOSC_FREQ_M 0x000C0000 -#define CCFG_MODE_CONF_XOSC_FREQ_S 18 -#define CCFG_MODE_CONF_XOSC_FREQ_24M 0x000C0000 -#define CCFG_MODE_CONF_XOSC_FREQ_48M 0x00080000 -#define CCFG_MODE_CONF_XOSC_FREQ_HPOSC 0x00040000 +#define CCFG_MODE_CONF_XOSC_FREQ_W 2 +#define CCFG_MODE_CONF_XOSC_FREQ_M 0x000C0000 +#define CCFG_MODE_CONF_XOSC_FREQ_S 18 +#define CCFG_MODE_CONF_XOSC_FREQ_24M 0x000C0000 +#define CCFG_MODE_CONF_XOSC_FREQ_48M 0x00080000 +#define CCFG_MODE_CONF_XOSC_FREQ_HPOSC 0x00040000 // Field: [17] XOSC_CAP_MOD // @@ -435,28 +435,28 @@ // XOSC_CAPARRAY_DELTA. // 0: Apply cap-array delta // 1: Do not apply cap-array delta (default) -#define CCFG_MODE_CONF_XOSC_CAP_MOD 0x00020000 -#define CCFG_MODE_CONF_XOSC_CAP_MOD_BITN 17 -#define CCFG_MODE_CONF_XOSC_CAP_MOD_M 0x00020000 -#define CCFG_MODE_CONF_XOSC_CAP_MOD_S 17 +#define CCFG_MODE_CONF_XOSC_CAP_MOD 0x00020000 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_BITN 17 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_M 0x00020000 +#define CCFG_MODE_CONF_XOSC_CAP_MOD_S 17 // Field: [16] HF_COMP // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_MODE_CONF_HF_COMP 0x00010000 -#define CCFG_MODE_CONF_HF_COMP_BITN 16 -#define CCFG_MODE_CONF_HF_COMP_M 0x00010000 -#define CCFG_MODE_CONF_HF_COMP_S 16 +#define CCFG_MODE_CONF_HF_COMP 0x00010000 +#define CCFG_MODE_CONF_HF_COMP_BITN 16 +#define CCFG_MODE_CONF_HF_COMP_M 0x00010000 +#define CCFG_MODE_CONF_HF_COMP_S 16 // Field: [15:8] XOSC_CAPARRAY_DELTA // // Signed 8-bit value, directly modifying trimmed XOSC cap-array step value. // Enabled by XOSC_CAP_MOD. -#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W 8 -#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M 0x0000FF00 -#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S 8 +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W 8 +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M 0x0000FF00 +#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S 8 // Field: [7:0] VDDR_CAP // @@ -469,9 +469,9 @@ // NOTE! If using the following functions this field must be configured (used // by TI RTOS): // SysCtrlSetRechargeBeforePowerDown() SysCtrlAdjustRechargeAfterPowerDown() -#define CCFG_MODE_CONF_VDDR_CAP_W 8 -#define CCFG_MODE_CONF_VDDR_CAP_M 0x000000FF -#define CCFG_MODE_CONF_VDDR_CAP_S 0 +#define CCFG_MODE_CONF_VDDR_CAP_W 8 +#define CCFG_MODE_CONF_VDDR_CAP_M 0x000000FF +#define CCFG_MODE_CONF_VDDR_CAP_S 0 //***************************************************************************** // @@ -483,36 +483,36 @@ // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_W 8 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M 0xFF000000 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S 24 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M 0xFF000000 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S 24 // Field: [23:16] VDDR_EXT_TP25 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_W 8 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M 0x00FF0000 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S 16 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M 0x00FF0000 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S 16 // Field: [15:8] VDDR_EXT_TP5 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_W 8 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M 0x0000FF00 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M 0x0000FF00 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S 8 // Field: [7:0] VDDR_EXT_TM15 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_W 8 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M 0x000000FF -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S 0 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_W 8 +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M 0x000000FF +#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S 0 //***************************************************************************** // @@ -524,36 +524,36 @@ // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_W 8 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M 0xFF000000 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S 24 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M 0xFF000000 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S 24 // Field: [23:16] VDDR_EXT_TP105 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_W 8 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M 0x00FF0000 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S 16 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M 0x00FF0000 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S 16 // Field: [15:8] VDDR_EXT_TP85 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_W 8 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M 0x0000FF00 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M 0x0000FF00 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S 8 // Field: [7:0] VDDR_EXT_TP65 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_W 8 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M 0x000000FF -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S 0 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_W 8 +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M 0x000000FF +#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S 0 //***************************************************************************** // @@ -565,27 +565,27 @@ // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_RTC_OFFSET_RTC_COMP_P0_W 16 -#define CCFG_RTC_OFFSET_RTC_COMP_P0_M 0xFFFF0000 -#define CCFG_RTC_OFFSET_RTC_COMP_P0_S 16 +#define CCFG_RTC_OFFSET_RTC_COMP_P0_W 16 +#define CCFG_RTC_OFFSET_RTC_COMP_P0_M 0xFFFF0000 +#define CCFG_RTC_OFFSET_RTC_COMP_P0_S 16 // Field: [15:8] RTC_COMP_P1 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_RTC_OFFSET_RTC_COMP_P1_W 8 -#define CCFG_RTC_OFFSET_RTC_COMP_P1_M 0x0000FF00 -#define CCFG_RTC_OFFSET_RTC_COMP_P1_S 8 +#define CCFG_RTC_OFFSET_RTC_COMP_P1_W 8 +#define CCFG_RTC_OFFSET_RTC_COMP_P1_M 0x0000FF00 +#define CCFG_RTC_OFFSET_RTC_COMP_P1_S 8 // Field: [7:0] RTC_COMP_P2 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_RTC_OFFSET_RTC_COMP_P2_W 8 -#define CCFG_RTC_OFFSET_RTC_COMP_P2_M 0x000000FF -#define CCFG_RTC_OFFSET_RTC_COMP_P2_S 0 +#define CCFG_RTC_OFFSET_RTC_COMP_P2_W 8 +#define CCFG_RTC_OFFSET_RTC_COMP_P2_M 0x000000FF +#define CCFG_RTC_OFFSET_RTC_COMP_P2_S 0 //***************************************************************************** // @@ -597,27 +597,27 @@ // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_FREQ_OFFSET_HF_COMP_P0_W 16 -#define CCFG_FREQ_OFFSET_HF_COMP_P0_M 0xFFFF0000 -#define CCFG_FREQ_OFFSET_HF_COMP_P0_S 16 +#define CCFG_FREQ_OFFSET_HF_COMP_P0_W 16 +#define CCFG_FREQ_OFFSET_HF_COMP_P0_M 0xFFFF0000 +#define CCFG_FREQ_OFFSET_HF_COMP_P0_S 16 // Field: [15:8] HF_COMP_P1 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_FREQ_OFFSET_HF_COMP_P1_W 8 -#define CCFG_FREQ_OFFSET_HF_COMP_P1_M 0x0000FF00 -#define CCFG_FREQ_OFFSET_HF_COMP_P1_S 8 +#define CCFG_FREQ_OFFSET_HF_COMP_P1_W 8 +#define CCFG_FREQ_OFFSET_HF_COMP_P1_M 0x0000FF00 +#define CCFG_FREQ_OFFSET_HF_COMP_P1_S 8 // Field: [7:0] HF_COMP_P2 // // Reserved for future use. Software should not rely on the value of a // reserved. Writing any other value than the reset/default value may result in // undefined behavior. -#define CCFG_FREQ_OFFSET_HF_COMP_P2_W 8 -#define CCFG_FREQ_OFFSET_HF_COMP_P2_M 0x000000FF -#define CCFG_FREQ_OFFSET_HF_COMP_P2_S 0 +#define CCFG_FREQ_OFFSET_HF_COMP_P2_W 8 +#define CCFG_FREQ_OFFSET_HF_COMP_P2_M 0x000000FF +#define CCFG_FREQ_OFFSET_HF_COMP_P2_S 0 //***************************************************************************** // @@ -629,9 +629,9 @@ // Bits[31:0] of the 64-bits custom IEEE MAC address. // If different from 0xFFFFFFFF then the value of this field is applied; // otherwise use value from FCFG. -#define CCFG_IEEE_MAC_0_ADDR_W 32 -#define CCFG_IEEE_MAC_0_ADDR_M 0xFFFFFFFF -#define CCFG_IEEE_MAC_0_ADDR_S 0 +#define CCFG_IEEE_MAC_0_ADDR_W 32 +#define CCFG_IEEE_MAC_0_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_MAC_0_ADDR_S 0 //***************************************************************************** // @@ -643,9 +643,9 @@ // Bits[63:32] of the 64-bits custom IEEE MAC address. // If different from 0xFFFFFFFF then the value of this field is applied; // otherwise use value from FCFG. -#define CCFG_IEEE_MAC_1_ADDR_W 32 -#define CCFG_IEEE_MAC_1_ADDR_M 0xFFFFFFFF -#define CCFG_IEEE_MAC_1_ADDR_S 0 +#define CCFG_IEEE_MAC_1_ADDR_W 32 +#define CCFG_IEEE_MAC_1_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_MAC_1_ADDR_S 0 //***************************************************************************** // @@ -657,9 +657,9 @@ // Bits[31:0] of the 64-bits custom IEEE BLE address. // If different from 0xFFFFFFFF then the value of this field is applied; // otherwise use value from FCFG. -#define CCFG_IEEE_BLE_0_ADDR_W 32 -#define CCFG_IEEE_BLE_0_ADDR_M 0xFFFFFFFF -#define CCFG_IEEE_BLE_0_ADDR_S 0 +#define CCFG_IEEE_BLE_0_ADDR_W 32 +#define CCFG_IEEE_BLE_0_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_BLE_0_ADDR_S 0 //***************************************************************************** // @@ -671,9 +671,9 @@ // Bits[63:32] of the 64-bits custom IEEE BLE address. // If different from 0xFFFFFFFF then the value of this field is applied; // otherwise use value from FCFG. -#define CCFG_IEEE_BLE_1_ADDR_W 32 -#define CCFG_IEEE_BLE_1_ADDR_M 0xFFFFFFFF -#define CCFG_IEEE_BLE_1_ADDR_S 0 +#define CCFG_IEEE_BLE_1_ADDR_W 32 +#define CCFG_IEEE_BLE_1_ADDR_M 0xFFFFFFFF +#define CCFG_IEEE_BLE_1_ADDR_S 0 //***************************************************************************** // @@ -687,9 +687,9 @@ // conditions for boot loader backdoor are met). // 0xC5: Boot loader is enabled. // Any other value: Boot loader is disabled. -#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_W 8 -#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M 0xFF000000 -#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S 24 +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_W 8 +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M 0xFF000000 +#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S 24 // Field: [16] BL_LEVEL // @@ -697,18 +697,18 @@ // loader backdoor is enabled by the BL_ENABLE field. // 0: Active low. // 1: Active high. -#define CCFG_BL_CONFIG_BL_LEVEL 0x00010000 -#define CCFG_BL_CONFIG_BL_LEVEL_BITN 16 -#define CCFG_BL_CONFIG_BL_LEVEL_M 0x00010000 -#define CCFG_BL_CONFIG_BL_LEVEL_S 16 +#define CCFG_BL_CONFIG_BL_LEVEL 0x00010000 +#define CCFG_BL_CONFIG_BL_LEVEL_BITN 16 +#define CCFG_BL_CONFIG_BL_LEVEL_M 0x00010000 +#define CCFG_BL_CONFIG_BL_LEVEL_S 16 // Field: [15:8] BL_PIN_NUMBER // // DIO number that is level checked if the boot loader backdoor is enabled by // the BL_ENABLE field. -#define CCFG_BL_CONFIG_BL_PIN_NUMBER_W 8 -#define CCFG_BL_CONFIG_BL_PIN_NUMBER_M 0x0000FF00 -#define CCFG_BL_CONFIG_BL_PIN_NUMBER_S 8 +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_W 8 +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_M 0x0000FF00 +#define CCFG_BL_CONFIG_BL_PIN_NUMBER_S 8 // Field: [7:0] BL_ENABLE // @@ -718,9 +718,9 @@ // // NOTE! Boot loader must be enabled (see BOOTLOADER_ENABLE) if boot loader // backdoor is enabled. -#define CCFG_BL_CONFIG_BL_ENABLE_W 8 -#define CCFG_BL_CONFIG_BL_ENABLE_M 0x000000FF -#define CCFG_BL_CONFIG_BL_ENABLE_S 0 +#define CCFG_BL_CONFIG_BL_ENABLE_W 8 +#define CCFG_BL_CONFIG_BL_ENABLE_M 0x000000FF +#define CCFG_BL_CONFIG_BL_ENABLE_S 0 //***************************************************************************** // @@ -737,10 +737,10 @@ // 0: Disable. Any chip erase request detected during boot will be ignored. // 1: Enable. Any chip erase request detected during boot will be performed by // the boot FW. -#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x00000100 -#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_BITN 8 -#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M 0x00000100 -#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S 8 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x00000100 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_BITN 8 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M 0x00000100 +#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S 8 // Field: [0] BANK_ERASE_DIS_N // @@ -751,10 +751,10 @@ // protected by write protect configuration bits in CCFG. // 0: Disable the boot loader bank erase function. // 1: Enable the boot loader bank erase function. -#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x00000001 -#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_BITN 0 -#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M 0x00000001 -#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S 0 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x00000001 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_BITN 0 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M 0x00000001 +#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S 0 //***************************************************************************** // @@ -768,9 +768,9 @@ // option with the unlock code. // All other values: Disable the functionality of unlocking the TI FA option // with the unlock code. -#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_W 8 -#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M 0x000000FF -#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S 0 +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_W 8 +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M 0x000000FF +#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S 0 //***************************************************************************** // @@ -784,9 +784,9 @@ // boot FW. // Any other value: Main CPU DAP access will remain disabled out of // power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M 0x00FF0000 -#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S 16 +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M 0x00FF0000 +#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S 16 // Field: [15:8] PRCM_TAP_ENABLE // @@ -795,9 +795,9 @@ // if enabled by corresponding configuration value in FCFG1 defined by TI. // Any other value: PRCM TAP access will remain disabled out of // power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_M 0x0000FF00 -#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_S 8 +#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_M 0x0000FF00 +#define CCFG_CCFG_TAP_DAP_0_PRCM_TAP_ENABLE_S 8 // Field: [7:0] TEST_TAP_ENABLE // @@ -806,9 +806,9 @@ // if enabled by corresponding configuration value in FCFG1 defined by TI. // Any other value: TEST TAP access will remain disabled out of // power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M 0x000000FF -#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S 0 +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M 0x000000FF +#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S 0 //***************************************************************************** // @@ -822,9 +822,9 @@ // FW if enabled by corresponding configuration value in FCFG1 defined by TI. // Any other value: PBIST2 TAP access will remain disabled out of // power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M 0x00FF0000 -#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S 16 +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M 0x00FF0000 +#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S 16 // Field: [15:8] PBIST1_TAP_ENABLE // @@ -833,9 +833,9 @@ // FW if enabled by corresponding configuration value in FCFG1 defined by TI. // Any other value: PBIST1 TAP access will remain disabled out of // power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M 0x0000FF00 -#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S 8 +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M 0x0000FF00 +#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S 8 // Field: [7:0] WUC_TAP_ENABLE // @@ -844,9 +844,9 @@ // if enabled by corresponding configuration value in FCFG1 defined by TI. // Any other value: WUC TAP access will remain disabled out of // power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_M 0x000000FF -#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_S 0 +#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_W 8 +#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_M 0x000000FF +#define CCFG_CCFG_TAP_DAP_1_WUC_TAP_ENABLE_S 0 //***************************************************************************** // @@ -867,9 +867,9 @@ // call the boot loader. // Note that if any other legal vector table start address value than 0x0 is // selected the PRCM:WARMRESET.WR_TO_PINRESET must be set to 1. -#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_W 32 -#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_M 0xFFFFFFFF -#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_S 0 +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_W 32 +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_M 0xFFFFFFFF +#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_S 0 //***************************************************************************** // @@ -879,258 +879,258 @@ // Field: [31] WRT_PROT_SEC_31 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31 0x80000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_BITN 31 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_M 0x80000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_S 31 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31 0x80000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_BITN 31 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_M 0x80000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_S 31 // Field: [30] WRT_PROT_SEC_30 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30 0x40000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_BITN 30 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_M 0x40000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_S 30 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30 0x40000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_BITN 30 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_M 0x40000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_S 30 // Field: [29] WRT_PROT_SEC_29 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29 0x20000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_BITN 29 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_M 0x20000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_S 29 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29 0x20000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_BITN 29 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_M 0x20000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_S 29 // Field: [28] WRT_PROT_SEC_28 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28 0x10000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_BITN 28 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_M 0x10000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_S 28 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28 0x10000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_BITN 28 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_M 0x10000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_S 28 // Field: [27] WRT_PROT_SEC_27 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27 0x08000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_BITN 27 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_M 0x08000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_S 27 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27 0x08000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_BITN 27 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_M 0x08000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_S 27 // Field: [26] WRT_PROT_SEC_26 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26 0x04000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_BITN 26 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_M 0x04000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_S 26 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26 0x04000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_BITN 26 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_M 0x04000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_S 26 // Field: [25] WRT_PROT_SEC_25 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25 0x02000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_BITN 25 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_M 0x02000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_S 25 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25 0x02000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_BITN 25 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_M 0x02000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_S 25 // Field: [24] WRT_PROT_SEC_24 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24 0x01000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_BITN 24 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_M 0x01000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_S 24 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24 0x01000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_BITN 24 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_M 0x01000000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_S 24 // Field: [23] WRT_PROT_SEC_23 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23 0x00800000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_BITN 23 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_M 0x00800000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_S 23 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23 0x00800000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_BITN 23 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_M 0x00800000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_S 23 // Field: [22] WRT_PROT_SEC_22 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22 0x00400000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_BITN 22 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_M 0x00400000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_S 22 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22 0x00400000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_BITN 22 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_M 0x00400000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_S 22 // Field: [21] WRT_PROT_SEC_21 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21 0x00200000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_BITN 21 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_M 0x00200000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_S 21 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21 0x00200000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_BITN 21 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_M 0x00200000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_S 21 // Field: [20] WRT_PROT_SEC_20 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20 0x00100000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_BITN 20 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_M 0x00100000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_S 20 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20 0x00100000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_BITN 20 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_M 0x00100000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_S 20 // Field: [19] WRT_PROT_SEC_19 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19 0x00080000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_BITN 19 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_M 0x00080000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_S 19 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19 0x00080000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_BITN 19 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_M 0x00080000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_S 19 // Field: [18] WRT_PROT_SEC_18 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18 0x00040000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_BITN 18 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_M 0x00040000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_S 18 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18 0x00040000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_BITN 18 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_M 0x00040000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_S 18 // Field: [17] WRT_PROT_SEC_17 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17 0x00020000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_BITN 17 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_M 0x00020000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_S 17 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17 0x00020000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_BITN 17 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_M 0x00020000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_S 17 // Field: [16] WRT_PROT_SEC_16 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16 0x00010000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_BITN 16 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_M 0x00010000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_S 16 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16 0x00010000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_BITN 16 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_M 0x00010000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_S 16 // Field: [15] WRT_PROT_SEC_15 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15 0x00008000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_BITN 15 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_M 0x00008000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_S 15 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15 0x00008000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_BITN 15 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_M 0x00008000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_S 15 // Field: [14] WRT_PROT_SEC_14 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14 0x00004000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_BITN 14 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_M 0x00004000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_S 14 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14 0x00004000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_BITN 14 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_M 0x00004000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_S 14 // Field: [13] WRT_PROT_SEC_13 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13 0x00002000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_BITN 13 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_M 0x00002000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_S 13 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13 0x00002000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_BITN 13 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_M 0x00002000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_S 13 // Field: [12] WRT_PROT_SEC_12 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12 0x00001000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_BITN 12 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_M 0x00001000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_S 12 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12 0x00001000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_BITN 12 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_M 0x00001000 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_S 12 // Field: [11] WRT_PROT_SEC_11 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11 0x00000800 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_BITN 11 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_M 0x00000800 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_S 11 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11 0x00000800 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_BITN 11 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_M 0x00000800 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_S 11 // Field: [10] WRT_PROT_SEC_10 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10 0x00000400 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_BITN 10 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_M 0x00000400 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_S 10 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10 0x00000400 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_BITN 10 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_M 0x00000400 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_S 10 // Field: [9] WRT_PROT_SEC_9 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9 0x00000200 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_BITN 9 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_M 0x00000200 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_S 9 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9 0x00000200 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_BITN 9 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_M 0x00000200 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_S 9 // Field: [8] WRT_PROT_SEC_8 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8 0x00000100 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_BITN 8 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_M 0x00000100 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_S 8 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8 0x00000100 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_BITN 8 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_M 0x00000100 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_S 8 // Field: [7] WRT_PROT_SEC_7 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7 0x00000080 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_BITN 7 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_M 0x00000080 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_S 7 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7 0x00000080 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_BITN 7 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_M 0x00000080 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_S 7 // Field: [6] WRT_PROT_SEC_6 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6 0x00000040 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_BITN 6 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_M 0x00000040 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_S 6 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6 0x00000040 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_BITN 6 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_M 0x00000040 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_S 6 // Field: [5] WRT_PROT_SEC_5 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5 0x00000020 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_BITN 5 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_M 0x00000020 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_S 5 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5 0x00000020 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_BITN 5 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_M 0x00000020 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_S 5 // Field: [4] WRT_PROT_SEC_4 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4 0x00000010 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_BITN 4 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_M 0x00000010 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_S 4 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4 0x00000010 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_BITN 4 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_M 0x00000010 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_S 4 // Field: [3] WRT_PROT_SEC_3 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3 0x00000008 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_BITN 3 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_M 0x00000008 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_S 3 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3 0x00000008 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_BITN 3 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_M 0x00000008 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_S 3 // Field: [2] WRT_PROT_SEC_2 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2 0x00000004 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_BITN 2 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_M 0x00000004 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_S 2 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2 0x00000004 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_BITN 2 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_M 0x00000004 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_S 2 // Field: [1] WRT_PROT_SEC_1 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1 0x00000002 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_BITN 1 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_M 0x00000002 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_S 1 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1 0x00000002 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_BITN 1 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_M 0x00000002 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_S 1 // Field: [0] WRT_PROT_SEC_0 // // 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0 0x00000001 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_BITN 0 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_M 0x00000001 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_S 0 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0 0x00000001 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_BITN 0 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_M 0x00000001 +#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_S 0 //***************************************************************************** // @@ -1140,258 +1140,258 @@ // Field: [31] WRT_PROT_SEC_63 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63 0x80000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_BITN 31 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_M 0x80000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_S 31 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63 0x80000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_BITN 31 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_M 0x80000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_S 31 // Field: [30] WRT_PROT_SEC_62 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62 0x40000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_BITN 30 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_M 0x40000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_S 30 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62 0x40000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_BITN 30 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_M 0x40000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_S 30 // Field: [29] WRT_PROT_SEC_61 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61 0x20000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_BITN 29 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_M 0x20000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_S 29 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61 0x20000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_BITN 29 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_M 0x20000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_S 29 // Field: [28] WRT_PROT_SEC_60 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60 0x10000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_BITN 28 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_M 0x10000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_S 28 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60 0x10000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_BITN 28 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_M 0x10000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_S 28 // Field: [27] WRT_PROT_SEC_59 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59 0x08000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_BITN 27 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_M 0x08000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_S 27 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59 0x08000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_BITN 27 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_M 0x08000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_S 27 // Field: [26] WRT_PROT_SEC_58 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58 0x04000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_BITN 26 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_M 0x04000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_S 26 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58 0x04000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_BITN 26 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_M 0x04000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_S 26 // Field: [25] WRT_PROT_SEC_57 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57 0x02000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_BITN 25 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_M 0x02000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_S 25 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57 0x02000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_BITN 25 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_M 0x02000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_S 25 // Field: [24] WRT_PROT_SEC_56 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56 0x01000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_BITN 24 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_M 0x01000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_S 24 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56 0x01000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_BITN 24 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_M 0x01000000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_S 24 // Field: [23] WRT_PROT_SEC_55 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55 0x00800000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_BITN 23 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_M 0x00800000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_S 23 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55 0x00800000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_BITN 23 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_M 0x00800000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_S 23 // Field: [22] WRT_PROT_SEC_54 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54 0x00400000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_BITN 22 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_M 0x00400000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_S 22 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54 0x00400000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_BITN 22 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_M 0x00400000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_S 22 // Field: [21] WRT_PROT_SEC_53 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53 0x00200000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_BITN 21 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_M 0x00200000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_S 21 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53 0x00200000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_BITN 21 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_M 0x00200000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_S 21 // Field: [20] WRT_PROT_SEC_52 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52 0x00100000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_BITN 20 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_M 0x00100000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_S 20 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52 0x00100000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_BITN 20 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_M 0x00100000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_S 20 // Field: [19] WRT_PROT_SEC_51 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51 0x00080000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_BITN 19 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_M 0x00080000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_S 19 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51 0x00080000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_BITN 19 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_M 0x00080000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_S 19 // Field: [18] WRT_PROT_SEC_50 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50 0x00040000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_BITN 18 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_M 0x00040000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_S 18 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50 0x00040000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_BITN 18 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_M 0x00040000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_S 18 // Field: [17] WRT_PROT_SEC_49 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49 0x00020000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_BITN 17 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_M 0x00020000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_S 17 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49 0x00020000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_BITN 17 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_M 0x00020000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_S 17 // Field: [16] WRT_PROT_SEC_48 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48 0x00010000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_BITN 16 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_M 0x00010000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_S 16 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48 0x00010000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_BITN 16 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_M 0x00010000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_S 16 // Field: [15] WRT_PROT_SEC_47 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47 0x00008000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_BITN 15 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_M 0x00008000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_S 15 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47 0x00008000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_BITN 15 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_M 0x00008000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_S 15 // Field: [14] WRT_PROT_SEC_46 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46 0x00004000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_BITN 14 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_M 0x00004000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_S 14 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46 0x00004000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_BITN 14 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_M 0x00004000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_S 14 // Field: [13] WRT_PROT_SEC_45 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45 0x00002000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_BITN 13 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_M 0x00002000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_S 13 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45 0x00002000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_BITN 13 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_M 0x00002000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_S 13 // Field: [12] WRT_PROT_SEC_44 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44 0x00001000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_BITN 12 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_M 0x00001000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_S 12 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44 0x00001000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_BITN 12 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_M 0x00001000 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_S 12 // Field: [11] WRT_PROT_SEC_43 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43 0x00000800 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_BITN 11 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_M 0x00000800 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_S 11 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43 0x00000800 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_BITN 11 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_M 0x00000800 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_S 11 // Field: [10] WRT_PROT_SEC_42 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42 0x00000400 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_BITN 10 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_M 0x00000400 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_S 10 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42 0x00000400 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_BITN 10 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_M 0x00000400 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_S 10 // Field: [9] WRT_PROT_SEC_41 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41 0x00000200 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_BITN 9 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_M 0x00000200 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_S 9 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41 0x00000200 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_BITN 9 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_M 0x00000200 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_S 9 // Field: [8] WRT_PROT_SEC_40 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40 0x00000100 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_BITN 8 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_M 0x00000100 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_S 8 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40 0x00000100 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_BITN 8 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_M 0x00000100 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_S 8 // Field: [7] WRT_PROT_SEC_39 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39 0x00000080 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_BITN 7 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_M 0x00000080 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_S 7 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39 0x00000080 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_BITN 7 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_M 0x00000080 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_S 7 // Field: [6] WRT_PROT_SEC_38 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38 0x00000040 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_BITN 6 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_M 0x00000040 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_S 6 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38 0x00000040 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_BITN 6 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_M 0x00000040 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_S 6 // Field: [5] WRT_PROT_SEC_37 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37 0x00000020 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_BITN 5 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_M 0x00000020 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_S 5 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37 0x00000020 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_BITN 5 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_M 0x00000020 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_S 5 // Field: [4] WRT_PROT_SEC_36 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36 0x00000010 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_BITN 4 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_M 0x00000010 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_S 4 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36 0x00000010 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_BITN 4 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_M 0x00000010 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_S 4 // Field: [3] WRT_PROT_SEC_35 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35 0x00000008 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_BITN 3 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_M 0x00000008 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_S 3 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35 0x00000008 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_BITN 3 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_M 0x00000008 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_S 3 // Field: [2] WRT_PROT_SEC_34 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34 0x00000004 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_BITN 2 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_M 0x00000004 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_S 2 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34 0x00000004 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_BITN 2 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_M 0x00000004 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_S 2 // Field: [1] WRT_PROT_SEC_33 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33 0x00000002 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_BITN 1 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_M 0x00000002 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_S 1 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33 0x00000002 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_BITN 1 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_M 0x00000002 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_S 1 // Field: [0] WRT_PROT_SEC_32 // // 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32 0x00000001 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_BITN 0 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_M 0x00000001 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_S 0 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32 0x00000001 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_BITN 0 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_M 0x00000001 +#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_S 0 //***************************************************************************** // @@ -1401,258 +1401,258 @@ // Field: [31] WRT_PROT_SEC_95 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95 0x80000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_BITN 31 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_M 0x80000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_S 31 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95 0x80000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_BITN 31 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_M 0x80000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_S 31 // Field: [30] WRT_PROT_SEC_94 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94 0x40000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_BITN 30 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_M 0x40000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_S 30 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94 0x40000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_BITN 30 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_M 0x40000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_S 30 // Field: [29] WRT_PROT_SEC_93 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93 0x20000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_BITN 29 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_M 0x20000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_S 29 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93 0x20000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_BITN 29 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_M 0x20000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_S 29 // Field: [28] WRT_PROT_SEC_92 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92 0x10000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_BITN 28 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_M 0x10000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_S 28 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92 0x10000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_BITN 28 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_M 0x10000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_S 28 // Field: [27] WRT_PROT_SEC_91 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91 0x08000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_BITN 27 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_M 0x08000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_S 27 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91 0x08000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_BITN 27 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_M 0x08000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_S 27 // Field: [26] WRT_PROT_SEC_90 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90 0x04000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_BITN 26 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_M 0x04000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_S 26 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90 0x04000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_BITN 26 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_M 0x04000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_S 26 // Field: [25] WRT_PROT_SEC_89 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89 0x02000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_BITN 25 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_M 0x02000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_S 25 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89 0x02000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_BITN 25 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_M 0x02000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_S 25 // Field: [24] WRT_PROT_SEC_88 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88 0x01000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_BITN 24 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_M 0x01000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_S 24 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88 0x01000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_BITN 24 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_M 0x01000000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_S 24 // Field: [23] WRT_PROT_SEC_87 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87 0x00800000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_BITN 23 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_M 0x00800000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_S 23 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87 0x00800000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_BITN 23 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_M 0x00800000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_S 23 // Field: [22] WRT_PROT_SEC_86 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86 0x00400000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_BITN 22 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_M 0x00400000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_S 22 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86 0x00400000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_BITN 22 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_M 0x00400000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_S 22 // Field: [21] WRT_PROT_SEC_85 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85 0x00200000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_BITN 21 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_M 0x00200000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_S 21 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85 0x00200000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_BITN 21 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_M 0x00200000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_S 21 // Field: [20] WRT_PROT_SEC_84 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84 0x00100000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_BITN 20 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_M 0x00100000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_S 20 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84 0x00100000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_BITN 20 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_M 0x00100000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_S 20 // Field: [19] WRT_PROT_SEC_83 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83 0x00080000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_BITN 19 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_M 0x00080000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_S 19 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83 0x00080000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_BITN 19 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_M 0x00080000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_S 19 // Field: [18] WRT_PROT_SEC_82 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82 0x00040000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_BITN 18 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_M 0x00040000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_S 18 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82 0x00040000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_BITN 18 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_M 0x00040000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_S 18 // Field: [17] WRT_PROT_SEC_81 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81 0x00020000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_BITN 17 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_M 0x00020000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_S 17 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81 0x00020000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_BITN 17 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_M 0x00020000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_S 17 // Field: [16] WRT_PROT_SEC_80 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80 0x00010000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_BITN 16 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_M 0x00010000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_S 16 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80 0x00010000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_BITN 16 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_M 0x00010000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_S 16 // Field: [15] WRT_PROT_SEC_79 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79 0x00008000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_BITN 15 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_M 0x00008000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_S 15 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79 0x00008000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_BITN 15 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_M 0x00008000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_S 15 // Field: [14] WRT_PROT_SEC_78 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78 0x00004000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_BITN 14 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_M 0x00004000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_S 14 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78 0x00004000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_BITN 14 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_M 0x00004000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_S 14 // Field: [13] WRT_PROT_SEC_77 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77 0x00002000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_BITN 13 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_M 0x00002000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_S 13 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77 0x00002000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_BITN 13 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_M 0x00002000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_S 13 // Field: [12] WRT_PROT_SEC_76 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76 0x00001000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_BITN 12 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_M 0x00001000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_S 12 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76 0x00001000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_BITN 12 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_M 0x00001000 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_S 12 // Field: [11] WRT_PROT_SEC_75 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75 0x00000800 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_BITN 11 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_M 0x00000800 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_S 11 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75 0x00000800 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_BITN 11 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_M 0x00000800 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_S 11 // Field: [10] WRT_PROT_SEC_74 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74 0x00000400 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_BITN 10 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_M 0x00000400 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_S 10 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74 0x00000400 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_BITN 10 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_M 0x00000400 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_S 10 // Field: [9] WRT_PROT_SEC_73 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73 0x00000200 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_BITN 9 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_M 0x00000200 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_S 9 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73 0x00000200 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_BITN 9 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_M 0x00000200 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_S 9 // Field: [8] WRT_PROT_SEC_72 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72 0x00000100 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_BITN 8 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_M 0x00000100 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_S 8 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72 0x00000100 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_BITN 8 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_M 0x00000100 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_S 8 // Field: [7] WRT_PROT_SEC_71 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71 0x00000080 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_BITN 7 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_M 0x00000080 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_S 7 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71 0x00000080 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_BITN 7 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_M 0x00000080 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_S 7 // Field: [6] WRT_PROT_SEC_70 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70 0x00000040 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_BITN 6 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_M 0x00000040 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_S 6 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70 0x00000040 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_BITN 6 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_M 0x00000040 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_S 6 // Field: [5] WRT_PROT_SEC_69 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69 0x00000020 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_BITN 5 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_M 0x00000020 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_S 5 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69 0x00000020 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_BITN 5 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_M 0x00000020 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_S 5 // Field: [4] WRT_PROT_SEC_68 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68 0x00000010 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_BITN 4 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_M 0x00000010 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_S 4 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68 0x00000010 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_BITN 4 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_M 0x00000010 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_S 4 // Field: [3] WRT_PROT_SEC_67 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67 0x00000008 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_BITN 3 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_M 0x00000008 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_S 3 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67 0x00000008 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_BITN 3 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_M 0x00000008 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_S 3 // Field: [2] WRT_PROT_SEC_66 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66 0x00000004 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_BITN 2 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_M 0x00000004 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_S 2 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66 0x00000004 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_BITN 2 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_M 0x00000004 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_S 2 // Field: [1] WRT_PROT_SEC_65 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65 0x00000002 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_BITN 1 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_M 0x00000002 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_S 1 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65 0x00000002 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_BITN 1 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_M 0x00000002 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_S 1 // Field: [0] WRT_PROT_SEC_64 // // 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64 0x00000001 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_BITN 0 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_M 0x00000001 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_S 0 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64 0x00000001 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_BITN 0 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_M 0x00000001 +#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_S 0 //***************************************************************************** // @@ -1662,258 +1662,257 @@ // Field: [31] WRT_PROT_SEC_127 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127 0x80000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_BITN 31 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_M 0x80000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_S 31 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127 0x80000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_BITN 31 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_M 0x80000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_S 31 // Field: [30] WRT_PROT_SEC_126 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126 0x40000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_BITN 30 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_M 0x40000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_S 30 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126 0x40000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_BITN 30 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_M 0x40000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_S 30 // Field: [29] WRT_PROT_SEC_125 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125 0x20000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_BITN 29 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_M 0x20000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_S 29 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125 0x20000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_BITN 29 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_M 0x20000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_S 29 // Field: [28] WRT_PROT_SEC_124 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124 0x10000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_BITN 28 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_M 0x10000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_S 28 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124 0x10000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_BITN 28 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_M 0x10000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_S 28 // Field: [27] WRT_PROT_SEC_123 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123 0x08000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_BITN 27 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_M 0x08000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_S 27 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123 0x08000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_BITN 27 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_M 0x08000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_S 27 // Field: [26] WRT_PROT_SEC_122 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122 0x04000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_BITN 26 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_M 0x04000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_S 26 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122 0x04000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_BITN 26 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_M 0x04000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_S 26 // Field: [25] WRT_PROT_SEC_121 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121 0x02000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_BITN 25 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_M 0x02000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_S 25 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121 0x02000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_BITN 25 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_M 0x02000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_S 25 // Field: [24] WRT_PROT_SEC_120 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120 0x01000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_BITN 24 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_M 0x01000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_S 24 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120 0x01000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_BITN 24 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_M 0x01000000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_S 24 // Field: [23] WRT_PROT_SEC_119 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119 0x00800000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_BITN 23 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_M 0x00800000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_S 23 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119 0x00800000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_BITN 23 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_M 0x00800000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_S 23 // Field: [22] WRT_PROT_SEC_118 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118 0x00400000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_BITN 22 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_M 0x00400000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_S 22 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118 0x00400000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_BITN 22 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_M 0x00400000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_S 22 // Field: [21] WRT_PROT_SEC_117 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117 0x00200000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_BITN 21 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_M 0x00200000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_S 21 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117 0x00200000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_BITN 21 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_M 0x00200000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_S 21 // Field: [20] WRT_PROT_SEC_116 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116 0x00100000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_BITN 20 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_M 0x00100000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_S 20 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116 0x00100000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_BITN 20 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_M 0x00100000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_S 20 // Field: [19] WRT_PROT_SEC_115 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115 0x00080000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_BITN 19 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_M 0x00080000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_S 19 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115 0x00080000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_BITN 19 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_M 0x00080000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_S 19 // Field: [18] WRT_PROT_SEC_114 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114 0x00040000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_BITN 18 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_M 0x00040000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_S 18 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114 0x00040000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_BITN 18 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_M 0x00040000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_S 18 // Field: [17] WRT_PROT_SEC_113 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113 0x00020000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_BITN 17 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_M 0x00020000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_S 17 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113 0x00020000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_BITN 17 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_M 0x00020000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_S 17 // Field: [16] WRT_PROT_SEC_112 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112 0x00010000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_BITN 16 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_M 0x00010000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_S 16 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112 0x00010000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_BITN 16 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_M 0x00010000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_S 16 // Field: [15] WRT_PROT_SEC_111 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111 0x00008000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_BITN 15 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_M 0x00008000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_S 15 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111 0x00008000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_BITN 15 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_M 0x00008000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_S 15 // Field: [14] WRT_PROT_SEC_110 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110 0x00004000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_BITN 14 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_M 0x00004000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_S 14 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110 0x00004000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_BITN 14 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_M 0x00004000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_S 14 // Field: [13] WRT_PROT_SEC_109 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109 0x00002000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_BITN 13 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_M 0x00002000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_S 13 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109 0x00002000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_BITN 13 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_M 0x00002000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_S 13 // Field: [12] WRT_PROT_SEC_108 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108 0x00001000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_BITN 12 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_M 0x00001000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_S 12 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108 0x00001000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_BITN 12 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_M 0x00001000 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_S 12 // Field: [11] WRT_PROT_SEC_107 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107 0x00000800 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_BITN 11 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_M 0x00000800 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_S 11 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107 0x00000800 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_BITN 11 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_M 0x00000800 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_S 11 // Field: [10] WRT_PROT_SEC_106 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106 0x00000400 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_BITN 10 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_M 0x00000400 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_S 10 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106 0x00000400 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_BITN 10 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_M 0x00000400 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_S 10 // Field: [9] WRT_PROT_SEC_105 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105 0x00000200 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_BITN 9 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_M 0x00000200 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_S 9 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105 0x00000200 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_BITN 9 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_M 0x00000200 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_S 9 // Field: [8] WRT_PROT_SEC_104 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104 0x00000100 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_BITN 8 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_M 0x00000100 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_S 8 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104 0x00000100 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_BITN 8 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_M 0x00000100 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_S 8 // Field: [7] WRT_PROT_SEC_103 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103 0x00000080 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_BITN 7 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_M 0x00000080 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_S 7 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103 0x00000080 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_BITN 7 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_M 0x00000080 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_S 7 // Field: [6] WRT_PROT_SEC_102 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102 0x00000040 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_BITN 6 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_M 0x00000040 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_S 6 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102 0x00000040 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_BITN 6 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_M 0x00000040 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_S 6 // Field: [5] WRT_PROT_SEC_101 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101 0x00000020 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_BITN 5 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_M 0x00000020 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_S 5 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101 0x00000020 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_BITN 5 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_M 0x00000020 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_S 5 // Field: [4] WRT_PROT_SEC_100 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100 0x00000010 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_BITN 4 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_M 0x00000010 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_S 4 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100 0x00000010 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_BITN 4 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_M 0x00000010 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_S 4 // Field: [3] WRT_PROT_SEC_99 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99 0x00000008 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_BITN 3 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_M 0x00000008 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_S 3 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99 0x00000008 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_BITN 3 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_M 0x00000008 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_S 3 // Field: [2] WRT_PROT_SEC_98 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98 0x00000004 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_BITN 2 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_M 0x00000004 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_S 2 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98 0x00000004 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_BITN 2 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_M 0x00000004 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_S 2 // Field: [1] WRT_PROT_SEC_97 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97 0x00000002 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_BITN 1 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_M 0x00000002 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_S 1 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97 0x00000002 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_BITN 1 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_M 0x00000002 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_S 1 // Field: [0] WRT_PROT_SEC_96 // // 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96 0x00000001 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_BITN 0 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_M 0x00000001 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_S 0 - +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96 0x00000001 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_BITN 0 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_M 0x00000001 +#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_S 0 #endif // __CCFG__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ccfg_simple_struct.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ccfg_simple_struct.h index 1a2c740..ea1fc90 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ccfg_simple_struct.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ccfg_simple_struct.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_ccfg_simple_struct_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_ccfg_simple_struct_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CCFG_SIMPLE_STRUCT_H__ #define __HW_CCFG_SIMPLE_STRUCT_H__ @@ -46,29 +46,29 @@ //***************************************************************************** typedef struct { - // Mapped to address - uint32_t CCFG_EXT_LF_CLK ; // 0x50003FA8 - uint32_t CCFG_MODE_CONF_1 ; // 0x50003FAC - uint32_t CCFG_SIZE_AND_DIS_FLAGS ; // 0x50003FB0 - uint32_t CCFG_MODE_CONF ; // 0x50003FB4 - uint32_t CCFG_VOLT_LOAD_0 ; // 0x50003FB8 - uint32_t CCFG_VOLT_LOAD_1 ; // 0x50003FBC - uint32_t CCFG_RTC_OFFSET ; // 0x50003FC0 - uint32_t CCFG_FREQ_OFFSET ; // 0x50003FC4 - uint32_t CCFG_IEEE_MAC_0 ; // 0x50003FC8 - uint32_t CCFG_IEEE_MAC_1 ; // 0x50003FCC - uint32_t CCFG_IEEE_BLE_0 ; // 0x50003FD0 - uint32_t CCFG_IEEE_BLE_1 ; // 0x50003FD4 - uint32_t CCFG_BL_CONFIG ; // 0x50003FD8 - uint32_t CCFG_ERASE_CONF ; // 0x50003FDC - uint32_t CCFG_CCFG_TI_OPTIONS ; // 0x50003FE0 - uint32_t CCFG_CCFG_TAP_DAP_0 ; // 0x50003FE4 - uint32_t CCFG_CCFG_TAP_DAP_1 ; // 0x50003FE8 - uint32_t CCFG_IMAGE_VALID_CONF ; // 0x50003FEC - uint32_t CCFG_CCFG_PROT_31_0 ; // 0x50003FF0 - uint32_t CCFG_CCFG_PROT_63_32 ; // 0x50003FF4 - uint32_t CCFG_CCFG_PROT_95_64 ; // 0x50003FF8 - uint32_t CCFG_CCFG_PROT_127_96 ; // 0x50003FFC + // Mapped to address + uint32_t CCFG_EXT_LF_CLK; // 0x50003FA8 + uint32_t CCFG_MODE_CONF_1; // 0x50003FAC + uint32_t CCFG_SIZE_AND_DIS_FLAGS; // 0x50003FB0 + uint32_t CCFG_MODE_CONF; // 0x50003FB4 + uint32_t CCFG_VOLT_LOAD_0; // 0x50003FB8 + uint32_t CCFG_VOLT_LOAD_1; // 0x50003FBC + uint32_t CCFG_RTC_OFFSET; // 0x50003FC0 + uint32_t CCFG_FREQ_OFFSET; // 0x50003FC4 + uint32_t CCFG_IEEE_MAC_0; // 0x50003FC8 + uint32_t CCFG_IEEE_MAC_1; // 0x50003FCC + uint32_t CCFG_IEEE_BLE_0; // 0x50003FD0 + uint32_t CCFG_IEEE_BLE_1; // 0x50003FD4 + uint32_t CCFG_BL_CONFIG; // 0x50003FD8 + uint32_t CCFG_ERASE_CONF; // 0x50003FDC + uint32_t CCFG_CCFG_TI_OPTIONS; // 0x50003FE0 + uint32_t CCFG_CCFG_TAP_DAP_0; // 0x50003FE4 + uint32_t CCFG_CCFG_TAP_DAP_1; // 0x50003FE8 + uint32_t CCFG_IMAGE_VALID_CONF; // 0x50003FEC + uint32_t CCFG_CCFG_PROT_31_0; // 0x50003FF0 + uint32_t CCFG_CCFG_PROT_63_32; // 0x50003FF4 + uint32_t CCFG_CCFG_PROT_95_64; // 0x50003FF8 + uint32_t CCFG_CCFG_PROT_127_96; // 0x50003FFC } ccfg_t; //***************************************************************************** @@ -78,5 +78,4 @@ typedef struct //***************************************************************************** extern const ccfg_t __ccfg; - #endif // __HW_CCFG_SIMPLE_STRUCT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_chip_def.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_chip_def.h index de21888..d90213e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_chip_def.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_chip_def.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: hw_chip_def.h -* Revised: 2017-06-26 09:33:33 +0200 (Mon, 26 Jun 2017) -* Revision: 49227 -* -* Description: Defines for device properties. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_chip_def.h + * Revised: 2017-06-26 09:33:33 +0200 (Mon, 26 Jun 2017) + * Revision: 49227 + * + * Description: Defines for device properties. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ //***************************************************************************** // @@ -53,8 +53,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif //***************************************************************************** @@ -64,13 +63,13 @@ extern "C" // //***************************************************************************** /* CC2620F128 */ -#if defined(CC2620F128RGZ_R20) || defined(CC2620F128RGZ_R21) +#if defined(CC2620F128RGZ_R20) || defined(CC2620F128RGZ_R21) #define CC_CHIP_ID 0x26200720 #elif defined(CC2620F128RHB_R20) || defined(CC2620F128RHB_R21) #define CC_CHIP_ID 0x26200520 #elif defined(CC2620F128RSM_R20) || defined(CC2620F128RSM_R21) #define CC_CHIP_ID 0x26200420 -#elif defined(CC2620F128_R20) || defined(CC2620F128_R21) +#elif defined(CC2620F128_R20) || defined(CC2620F128_R21) #define CC_CHIP_ID 0x26200020 #elif defined(CC2620F128RGZ_R22) || defined(CC2620F128RGZ) #define CC_CHIP_ID 0x26200722 @@ -78,7 +77,7 @@ extern "C" #define CC_CHIP_ID 0x26200522 #elif defined(CC2620F128RSM_R22) || defined(CC2620F128RSM) #define CC_CHIP_ID 0x26200422 -#elif defined(CC2620F128_R22) || defined(CC2620F128) +#elif defined(CC2620F128_R22) || defined(CC2620F128) #define CC_CHIP_ID 0x26200022 /* CC2630F128 */ #elif defined(CC2630F128RGZ_R20) || defined(CC2630F128RGZ_R21) @@ -87,7 +86,7 @@ extern "C" #define CC_CHIP_ID 0x26300520 #elif defined(CC2630F128RSM_R20) || defined(CC2630F128RSM_R21) #define CC_CHIP_ID 0x26300420 -#elif defined(CC2630F128_R20) || defined(CC2630F128_R21) +#elif defined(CC2630F128_R20) || defined(CC2630F128_R21) #define CC_CHIP_ID 0x26300020 #elif defined(CC2630F128RGZ_R22) || defined(CC2630F128RGZ) #define CC_CHIP_ID 0x26300722 @@ -95,7 +94,7 @@ extern "C" #define CC_CHIP_ID 0x26300522 #elif defined(CC2630F128RSM_R22) || defined(CC2630F128RSM) #define CC_CHIP_ID 0x26300422 -#elif defined(CC2630F128_R22) || defined(CC2630F128) +#elif defined(CC2630F128_R22) || defined(CC2630F128) #define CC_CHIP_ID 0x26300022 /* CC2640F128 */ #elif defined(CC2640F128RGZ_R20) || defined(CC2640F128RGZ_R21) @@ -104,7 +103,7 @@ extern "C" #define CC_CHIP_ID 0x26400520 #elif defined(CC2640F128RSM_R20) || defined(CC2640F128RSM_R21) #define CC_CHIP_ID 0x26400420 -#elif defined(CC2640F128_R20) || defined(CC2640F128_R21) +#elif defined(CC2640F128_R20) || defined(CC2640F128_R21) #define CC_CHIP_ID 0x26400020 #elif defined(CC2640F128RGZ_R22) || defined(CC2640F128RGZ) #define CC_CHIP_ID 0x26400722 @@ -112,7 +111,7 @@ extern "C" #define CC_CHIP_ID 0x26400522 #elif defined(CC2640F128RSM_R22) || defined(CC2640F128RSM) #define CC_CHIP_ID 0x26400422 -#elif defined(CC2640F128_R22) || defined(CC2640F128) +#elif defined(CC2640F128_R22) || defined(CC2640F128) #define CC_CHIP_ID 0x26400022 /* CC2650F128 */ #elif defined(CC2650F128RGZ_R20) || defined(CC2650F128RGZ_R21) @@ -121,7 +120,7 @@ extern "C" #define CC_CHIP_ID 0x26500520 #elif defined(CC2650F128RSM_R20) || defined(CC2650F128RSM_R21) #define CC_CHIP_ID 0x26500420 -#elif defined(CC2650F128_R20) || defined(CC2650F128_R21) +#elif defined(CC2650F128_R20) || defined(CC2650F128_R21) #define CC_CHIP_ID 0x26500020 #elif defined(CC2650F128RGZ_R22) || defined(CC2650F128RGZ) #define CC_CHIP_ID 0x26500722 @@ -129,7 +128,7 @@ extern "C" #define CC_CHIP_ID 0x26500522 #elif defined(CC2650F128RSM_R22) || defined(CC2650F128RSM) #define CC_CHIP_ID 0x26500422 -#elif defined(CC2650F128_R22) || defined(CC2650F128) +#elif defined(CC2650F128_R22) || defined(CC2650F128) #define CC_CHIP_ID 0x26500022 /* CC2650L128 (OTP) */ #elif defined(CC2650L128) @@ -141,7 +140,7 @@ extern "C" #define CC_CHIP_ID 0x13100520 #elif defined(CC1310F128RSM_R20) || defined(CC1310F128RSM) #define CC_CHIP_ID 0x13100420 -#elif defined(CC1310F128_R20) || defined(CC1310F128) +#elif defined(CC1310F128_R20) || defined(CC1310F128) #define CC_CHIP_ID 0x13100020 /* CC1350F128 */ #elif defined(CC1350F128RGZ_R20) || defined(CC1350F128RGZ) @@ -150,7 +149,7 @@ extern "C" #define CC_CHIP_ID 0x13500520 #elif defined(CC1350F128RSM_R20) || defined(CC1350F128RSM) #define CC_CHIP_ID 0x13500420 -#elif defined(CC1350F128_R20) || defined(CC1350F128) +#elif defined(CC1350F128_R20) || defined(CC1350F128) #define CC_CHIP_ID 0x13500020 /* CC2640R2F */ #elif defined(CC2640R2FRGZ_R25) || defined(CC2640R2FRGZ) @@ -159,37 +158,37 @@ extern "C" #define CC_CHIP_ID 0x26401510 #elif defined(CC2640R2FRSM_R25) || defined(CC2640R2FRSM) #define CC_CHIP_ID 0x26401410 -#elif defined(CC2640R2F_R25) || defined(CC2640R2F) +#elif defined(CC2640R2F_R25) || defined(CC2640R2F) #define CC_CHIP_ID 0x26401010 /* CC2652R1F */ #elif defined(CC2652R1FRGZ_R10) || defined(CC2652R1FRGZ) #define CC_CHIP_ID 0x26523710 -#elif defined(CC2652R1F_R10) || defined(CC2652R1F) +#elif defined(CC2652R1F_R10) || defined(CC2652R1F) #define CC_CHIP_ID 0x26523010 /* CC2644R1F */ #elif defined(CC2644R1FRGZ_R10) || defined(CC2644R1FRGZ) #define CC_CHIP_ID 0x26443710 -#elif defined(CC2644R1F_R10) || defined(CC2644R1F) +#elif defined(CC2644R1F_R10) || defined(CC2644R1F) #define CC_CHIP_ID 0x26443010 /* CC2642R1F */ #elif defined(CC2642R1FRGZ_R10) || defined(CC2642R1FRGZ) #define CC_CHIP_ID 0x26423710 -#elif defined(CC2642R1F_R10) || defined(CC2642R1F) +#elif defined(CC2642R1F_R10) || defined(CC2642R1F) #define CC_CHIP_ID 0x26423010 /* CC1354R1F */ #elif defined(CC1354R1FRGZ_R10) || defined(CC1354R1FRGZ) #define CC_CHIP_ID 0x13543710 -#elif defined(CC1354R1F_R10) || defined(CC1354R1F) +#elif defined(CC1354R1F_R10) || defined(CC1354R1F) #define CC_CHIP_ID 0x13543010 /* CC1352R1F */ #elif defined(CC1352R1FRGZ_R10) || defined(CC1352R1FRGZ) #define CC_CHIP_ID 0x13523710 -#elif defined(CC1352R1F_R10) || defined(CC1352R1F) +#elif defined(CC1352R1F_R10) || defined(CC1352R1F) #define CC_CHIP_ID 0x13523010 /* CC1312R1F */ #elif defined(CC1312R1FRGZ_R10) || defined(CC1312R1FRGZ) #define CC_CHIP_ID 0x13123710 -#elif defined(CC1312R1F_R10) || defined(CC1312R1F) +#elif defined(CC1312R1F_R10) || defined(CC1312R1F) #define CC_CHIP_ID 0x13123010 #endif @@ -213,7 +212,7 @@ extern "C" #if (CC_GET_CHIP_OPTION != ((CC_CHIP_ID & 0x0000F000) >> 12)) #error "Specified chip option does not match DriverLib release" #endif -#if (CC_GET_CHIP_HWREV != ((CC_CHIP_ID & 0x000000FF) >> 0)) +#if (CC_GET_CHIP_HWREV != ((CC_CHIP_ID & 0x000000FF) >> 0)) #error "Specified chip hardware revision does not match DriverLib release" #endif #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_dwt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_dwt.h index 1721748..4ae2807 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_dwt.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_dwt.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_cpu_dwt_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_cpu_dwt_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CPU_DWT_H__ #define __HW_CPU_DWT_H__ @@ -44,64 +44,64 @@ // //***************************************************************************** // Control -#define CPU_DWT_O_CTRL 0x00000000 +#define CPU_DWT_O_CTRL 0x00000000 // Current PC Sampler Cycle Count -#define CPU_DWT_O_CYCCNT 0x00000004 +#define CPU_DWT_O_CYCCNT 0x00000004 // CPI Count -#define CPU_DWT_O_CPICNT 0x00000008 +#define CPU_DWT_O_CPICNT 0x00000008 // Exception Overhead Count -#define CPU_DWT_O_EXCCNT 0x0000000C +#define CPU_DWT_O_EXCCNT 0x0000000C // Sleep Count -#define CPU_DWT_O_SLEEPCNT 0x00000010 +#define CPU_DWT_O_SLEEPCNT 0x00000010 // LSU Count -#define CPU_DWT_O_LSUCNT 0x00000014 +#define CPU_DWT_O_LSUCNT 0x00000014 // Fold Count -#define CPU_DWT_O_FOLDCNT 0x00000018 +#define CPU_DWT_O_FOLDCNT 0x00000018 // Program Counter Sample -#define CPU_DWT_O_PCSR 0x0000001C +#define CPU_DWT_O_PCSR 0x0000001C // Comparator 0 -#define CPU_DWT_O_COMP0 0x00000020 +#define CPU_DWT_O_COMP0 0x00000020 // Mask 0 -#define CPU_DWT_O_MASK0 0x00000024 +#define CPU_DWT_O_MASK0 0x00000024 // Function 0 -#define CPU_DWT_O_FUNCTION0 0x00000028 +#define CPU_DWT_O_FUNCTION0 0x00000028 // Comparator 1 -#define CPU_DWT_O_COMP1 0x00000030 +#define CPU_DWT_O_COMP1 0x00000030 // Mask 1 -#define CPU_DWT_O_MASK1 0x00000034 +#define CPU_DWT_O_MASK1 0x00000034 // Function 1 -#define CPU_DWT_O_FUNCTION1 0x00000038 +#define CPU_DWT_O_FUNCTION1 0x00000038 // Comparator 2 -#define CPU_DWT_O_COMP2 0x00000040 +#define CPU_DWT_O_COMP2 0x00000040 // Mask 2 -#define CPU_DWT_O_MASK2 0x00000044 +#define CPU_DWT_O_MASK2 0x00000044 // Function 2 -#define CPU_DWT_O_FUNCTION2 0x00000048 +#define CPU_DWT_O_FUNCTION2 0x00000048 // Comparator 3 -#define CPU_DWT_O_COMP3 0x00000050 +#define CPU_DWT_O_COMP3 0x00000050 // Mask 3 -#define CPU_DWT_O_MASK3 0x00000054 +#define CPU_DWT_O_MASK3 0x00000054 // Function 3 -#define CPU_DWT_O_FUNCTION3 0x00000058 +#define CPU_DWT_O_FUNCTION3 0x00000058 //***************************************************************************** // @@ -111,18 +111,18 @@ // Field: [25] NOCYCCNT // // When set, CYCCNT is not supported. -#define CPU_DWT_CTRL_NOCYCCNT 0x02000000 -#define CPU_DWT_CTRL_NOCYCCNT_BITN 25 -#define CPU_DWT_CTRL_NOCYCCNT_M 0x02000000 -#define CPU_DWT_CTRL_NOCYCCNT_S 25 +#define CPU_DWT_CTRL_NOCYCCNT 0x02000000 +#define CPU_DWT_CTRL_NOCYCCNT_BITN 25 +#define CPU_DWT_CTRL_NOCYCCNT_M 0x02000000 +#define CPU_DWT_CTRL_NOCYCCNT_S 25 // Field: [24] NOPRFCNT // // When set, FOLDCNT, LSUCNT, SLEEPCNT, EXCCNT, and CPICNT are not supported. -#define CPU_DWT_CTRL_NOPRFCNT 0x01000000 -#define CPU_DWT_CTRL_NOPRFCNT_BITN 24 -#define CPU_DWT_CTRL_NOPRFCNT_M 0x01000000 -#define CPU_DWT_CTRL_NOPRFCNT_S 24 +#define CPU_DWT_CTRL_NOPRFCNT 0x01000000 +#define CPU_DWT_CTRL_NOPRFCNT_BITN 24 +#define CPU_DWT_CTRL_NOPRFCNT_M 0x01000000 +#define CPU_DWT_CTRL_NOPRFCNT_S 24 // Field: [22] CYCEVTENA // @@ -132,10 +132,10 @@ // // 0: Cycle count events disabled // 1: Cycle count events enabled -#define CPU_DWT_CTRL_CYCEVTENA 0x00400000 -#define CPU_DWT_CTRL_CYCEVTENA_BITN 22 -#define CPU_DWT_CTRL_CYCEVTENA_M 0x00400000 -#define CPU_DWT_CTRL_CYCEVTENA_S 22 +#define CPU_DWT_CTRL_CYCEVTENA 0x00400000 +#define CPU_DWT_CTRL_CYCEVTENA_BITN 22 +#define CPU_DWT_CTRL_CYCEVTENA_M 0x00400000 +#define CPU_DWT_CTRL_CYCEVTENA_S 22 // Field: [21] FOLDEVTENA // @@ -146,10 +146,10 @@ // // 0: Folded instruction count events disabled. // 1: Folded instruction count events enabled. -#define CPU_DWT_CTRL_FOLDEVTENA 0x00200000 -#define CPU_DWT_CTRL_FOLDEVTENA_BITN 21 -#define CPU_DWT_CTRL_FOLDEVTENA_M 0x00200000 -#define CPU_DWT_CTRL_FOLDEVTENA_S 21 +#define CPU_DWT_CTRL_FOLDEVTENA 0x00200000 +#define CPU_DWT_CTRL_FOLDEVTENA_BITN 21 +#define CPU_DWT_CTRL_FOLDEVTENA_M 0x00200000 +#define CPU_DWT_CTRL_FOLDEVTENA_S 21 // Field: [20] LSUEVTENA // @@ -159,10 +159,10 @@ // // 0: LSU count events disabled. // 1: LSU count events enabled. -#define CPU_DWT_CTRL_LSUEVTENA 0x00100000 -#define CPU_DWT_CTRL_LSUEVTENA_BITN 20 -#define CPU_DWT_CTRL_LSUEVTENA_M 0x00100000 -#define CPU_DWT_CTRL_LSUEVTENA_S 20 +#define CPU_DWT_CTRL_LSUEVTENA 0x00100000 +#define CPU_DWT_CTRL_LSUEVTENA_BITN 20 +#define CPU_DWT_CTRL_LSUEVTENA_M 0x00100000 +#define CPU_DWT_CTRL_LSUEVTENA_S 20 // Field: [19] SLEEPEVTENA // @@ -171,10 +171,10 @@ // // 0: Sleep count events disabled. // 1: Sleep count events enabled. -#define CPU_DWT_CTRL_SLEEPEVTENA 0x00080000 -#define CPU_DWT_CTRL_SLEEPEVTENA_BITN 19 -#define CPU_DWT_CTRL_SLEEPEVTENA_M 0x00080000 -#define CPU_DWT_CTRL_SLEEPEVTENA_S 19 +#define CPU_DWT_CTRL_SLEEPEVTENA 0x00080000 +#define CPU_DWT_CTRL_SLEEPEVTENA_BITN 19 +#define CPU_DWT_CTRL_SLEEPEVTENA_M 0x00080000 +#define CPU_DWT_CTRL_SLEEPEVTENA_S 19 // Field: [18] EXCEVTENA // @@ -183,10 +183,10 @@ // // 0x0: Interrupt overhead event disabled. // 0x1: Interrupt overhead event enabled. -#define CPU_DWT_CTRL_EXCEVTENA 0x00040000 -#define CPU_DWT_CTRL_EXCEVTENA_BITN 18 -#define CPU_DWT_CTRL_EXCEVTENA_M 0x00040000 -#define CPU_DWT_CTRL_EXCEVTENA_S 18 +#define CPU_DWT_CTRL_EXCEVTENA 0x00040000 +#define CPU_DWT_CTRL_EXCEVTENA_BITN 18 +#define CPU_DWT_CTRL_EXCEVTENA_M 0x00040000 +#define CPU_DWT_CTRL_EXCEVTENA_S 18 // Field: [17] CPIEVTENA // @@ -195,10 +195,10 @@ // // 0: CPI counter events disabled. // 1: CPI counter events enabled. -#define CPU_DWT_CTRL_CPIEVTENA 0x00020000 -#define CPU_DWT_CTRL_CPIEVTENA_BITN 17 -#define CPU_DWT_CTRL_CPIEVTENA_M 0x00020000 -#define CPU_DWT_CTRL_CPIEVTENA_S 17 +#define CPU_DWT_CTRL_CPIEVTENA 0x00020000 +#define CPU_DWT_CTRL_CPIEVTENA_BITN 17 +#define CPU_DWT_CTRL_CPIEVTENA_M 0x00020000 +#define CPU_DWT_CTRL_CPIEVTENA_S 17 // Field: [16] EXCTRCENA // @@ -206,10 +206,10 @@ // // 0: Interrupt event trace disabled. // 1: Interrupt event trace enabled. -#define CPU_DWT_CTRL_EXCTRCENA 0x00010000 -#define CPU_DWT_CTRL_EXCTRCENA_BITN 16 -#define CPU_DWT_CTRL_EXCTRCENA_M 0x00010000 -#define CPU_DWT_CTRL_EXCTRCENA_S 16 +#define CPU_DWT_CTRL_EXCTRCENA 0x00010000 +#define CPU_DWT_CTRL_EXCTRCENA_BITN 16 +#define CPU_DWT_CTRL_EXCTRCENA_M 0x00010000 +#define CPU_DWT_CTRL_EXCTRCENA_S 16 // Field: [12] PCSAMPLEENA // @@ -219,10 +219,10 @@ // // 0: PC Sampling event disabled. // 1: Sampling event enabled. -#define CPU_DWT_CTRL_PCSAMPLEENA 0x00001000 -#define CPU_DWT_CTRL_PCSAMPLEENA_BITN 12 -#define CPU_DWT_CTRL_PCSAMPLEENA_M 0x00001000 -#define CPU_DWT_CTRL_PCSAMPLEENA_S 12 +#define CPU_DWT_CTRL_PCSAMPLEENA 0x00001000 +#define CPU_DWT_CTRL_PCSAMPLEENA_BITN 12 +#define CPU_DWT_CTRL_PCSAMPLEENA_M 0x00001000 +#define CPU_DWT_CTRL_PCSAMPLEENA_S 12 // Field: [11:10] SYNCTAP // @@ -235,13 +235,13 @@ // BIT26 Tap at bit 26 of CYCCNT // BIT24 Tap at bit 24 of CYCCNT // DIS Disabled. No synchronization packets -#define CPU_DWT_CTRL_SYNCTAP_W 2 -#define CPU_DWT_CTRL_SYNCTAP_M 0x00000C00 -#define CPU_DWT_CTRL_SYNCTAP_S 10 -#define CPU_DWT_CTRL_SYNCTAP_BIT28 0x00000C00 -#define CPU_DWT_CTRL_SYNCTAP_BIT26 0x00000800 -#define CPU_DWT_CTRL_SYNCTAP_BIT24 0x00000400 -#define CPU_DWT_CTRL_SYNCTAP_DIS 0x00000000 +#define CPU_DWT_CTRL_SYNCTAP_W 2 +#define CPU_DWT_CTRL_SYNCTAP_M 0x00000C00 +#define CPU_DWT_CTRL_SYNCTAP_S 10 +#define CPU_DWT_CTRL_SYNCTAP_BIT28 0x00000C00 +#define CPU_DWT_CTRL_SYNCTAP_BIT26 0x00000800 +#define CPU_DWT_CTRL_SYNCTAP_BIT24 0x00000400 +#define CPU_DWT_CTRL_SYNCTAP_DIS 0x00000000 // Field: [9] CYCTAP // @@ -253,12 +253,12 @@ // ENUMs: // BIT10 Selects bit [10] to tap // BIT6 Selects bit [6] to tap -#define CPU_DWT_CTRL_CYCTAP 0x00000200 -#define CPU_DWT_CTRL_CYCTAP_BITN 9 -#define CPU_DWT_CTRL_CYCTAP_M 0x00000200 -#define CPU_DWT_CTRL_CYCTAP_S 9 -#define CPU_DWT_CTRL_CYCTAP_BIT10 0x00000200 -#define CPU_DWT_CTRL_CYCTAP_BIT6 0x00000000 +#define CPU_DWT_CTRL_CYCTAP 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_BITN 9 +#define CPU_DWT_CTRL_CYCTAP_M 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_S 9 +#define CPU_DWT_CTRL_CYCTAP_BIT10 0x00000200 +#define CPU_DWT_CTRL_CYCTAP_BIT6 0x00000000 // Field: [8:5] POSTCNT // @@ -266,9 +266,9 @@ // to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it // triggers an event for PCSAMPLEENA or CYCEVTENA use. It also reloads with the // value from POSTPRESET. -#define CPU_DWT_CTRL_POSTCNT_W 4 -#define CPU_DWT_CTRL_POSTCNT_M 0x000001E0 -#define CPU_DWT_CTRL_POSTCNT_S 5 +#define CPU_DWT_CTRL_POSTCNT_W 4 +#define CPU_DWT_CTRL_POSTCNT_M 0x000001E0 +#define CPU_DWT_CTRL_POSTCNT_S 5 // Field: [4:1] POSTPRESET // @@ -277,18 +277,18 @@ // a count-down value, to be reloaded into POSTCNT each time it reaches 0. For // example, a value 1 in this register means an event is formed every other tap // change. -#define CPU_DWT_CTRL_POSTPRESET_W 4 -#define CPU_DWT_CTRL_POSTPRESET_M 0x0000001E -#define CPU_DWT_CTRL_POSTPRESET_S 1 +#define CPU_DWT_CTRL_POSTPRESET_W 4 +#define CPU_DWT_CTRL_POSTPRESET_M 0x0000001E +#define CPU_DWT_CTRL_POSTPRESET_S 1 // Field: [0] CYCCNTENA // // Enable CYCCNT, allowing it to increment and generate synchronization and // count events. If NOCYCCNT = 1, this bit reads zero and ignore writes. -#define CPU_DWT_CTRL_CYCCNTENA 0x00000001 -#define CPU_DWT_CTRL_CYCCNTENA_BITN 0 -#define CPU_DWT_CTRL_CYCCNTENA_M 0x00000001 -#define CPU_DWT_CTRL_CYCCNTENA_S 0 +#define CPU_DWT_CTRL_CYCCNTENA 0x00000001 +#define CPU_DWT_CTRL_CYCCNTENA_BITN 0 +#define CPU_DWT_CTRL_CYCCNTENA_M 0x00000001 +#define CPU_DWT_CTRL_CYCCNTENA_S 0 //***************************************************************************** // @@ -303,9 +303,9 @@ // advance in power modes where free-running clock to CPU stops). It wraps // around to 0 on overflow. The debugger must initialize this to 0 when first // enabling. -#define CPU_DWT_CYCCNT_CYCCNT_W 32 -#define CPU_DWT_CYCCNT_CYCCNT_M 0xFFFFFFFF -#define CPU_DWT_CYCCNT_CYCCNT_S 0 +#define CPU_DWT_CYCCNT_CYCCNT_W 32 +#define CPU_DWT_CYCCNT_CYCCNT_M 0xFFFFFFFF +#define CPU_DWT_CYCCNT_CYCCNT_S 0 //***************************************************************************** // @@ -320,9 +320,9 @@ // stalls. If CTRL.CPIEVTENA is set, an event is emitted when the counter // overflows. This counter initializes to 0 when it is enabled using // CTRL.CPIEVTENA. -#define CPU_DWT_CPICNT_CPICNT_W 8 -#define CPU_DWT_CPICNT_CPICNT_M 0x000000FF -#define CPU_DWT_CPICNT_CPICNT_S 0 +#define CPU_DWT_CPICNT_CPICNT_W 8 +#define CPU_DWT_CPICNT_CPICNT_M 0x000000FF +#define CPU_DWT_CPICNT_CPICNT_S 0 //***************************************************************************** // @@ -335,9 +335,9 @@ // interrupt processing (for example entry stacking, return unstacking, // pre-emption). An event is emitted on counter overflow (every 256 cycles). // This counter initializes to 0 when it is enabled using CTRL.EXCEVTENA. -#define CPU_DWT_EXCCNT_EXCCNT_W 8 -#define CPU_DWT_EXCCNT_EXCCNT_M 0x000000FF -#define CPU_DWT_EXCCNT_EXCCNT_S 0 +#define CPU_DWT_EXCCNT_EXCCNT_W 8 +#define CPU_DWT_EXCCNT_EXCCNT_M 0x000000FF +#define CPU_DWT_EXCCNT_EXCCNT_S 0 //***************************************************************************** // @@ -353,9 +353,9 @@ // power modes the free-running clock to CPU is gated to minimize power // consumption. This means that the sleep counter will be invalid in these // power modes. -#define CPU_DWT_SLEEPCNT_SLEEPCNT_W 8 -#define CPU_DWT_SLEEPCNT_SLEEPCNT_M 0x000000FF -#define CPU_DWT_SLEEPCNT_SLEEPCNT_S 0 +#define CPU_DWT_SLEEPCNT_SLEEPCNT_W 8 +#define CPU_DWT_SLEEPCNT_SLEEPCNT_M 0x000000FF +#define CPU_DWT_SLEEPCNT_SLEEPCNT_S 0 //***************************************************************************** // @@ -371,9 +371,9 @@ // cycles (i.e. takes four cycles to execute), increments this counter three // times. An event is emitted on counter overflow (every 256 cycles). This // counter initializes to 0 when it is enabled using CTRL.LSUEVTENA. -#define CPU_DWT_LSUCNT_LSUCNT_W 8 -#define CPU_DWT_LSUCNT_LSUCNT_M 0x000000FF -#define CPU_DWT_LSUCNT_LSUCNT_S 0 +#define CPU_DWT_LSUCNT_LSUCNT_W 8 +#define CPU_DWT_LSUCNT_LSUCNT_M 0x000000FF +#define CPU_DWT_LSUCNT_LSUCNT_S 0 //***************************************************************************** // @@ -384,9 +384,9 @@ // // This counts the total number folded instructions. This counter initializes // to 0 when it is enabled using CTRL.FOLDEVTENA. -#define CPU_DWT_FOLDCNT_FOLDCNT_W 8 -#define CPU_DWT_FOLDCNT_FOLDCNT_M 0x000000FF -#define CPU_DWT_FOLDCNT_FOLDCNT_S 0 +#define CPU_DWT_FOLDCNT_FOLDCNT_W 8 +#define CPU_DWT_FOLDCNT_FOLDCNT_M 0x000000FF +#define CPU_DWT_FOLDCNT_FOLDCNT_S 0 //***************************************************************************** // @@ -396,9 +396,9 @@ // Field: [31:0] EIASAMPLE // // Execution instruction address sample, or 0xFFFFFFFF if the core is halted. -#define CPU_DWT_PCSR_EIASAMPLE_W 32 -#define CPU_DWT_PCSR_EIASAMPLE_M 0xFFFFFFFF -#define CPU_DWT_PCSR_EIASAMPLE_S 0 +#define CPU_DWT_PCSR_EIASAMPLE_W 32 +#define CPU_DWT_PCSR_EIASAMPLE_M 0xFFFFFFFF +#define CPU_DWT_PCSR_EIASAMPLE_S 0 //***************************************************************************** // @@ -410,9 +410,9 @@ // Reference value to compare against PC or the data address as given by // FUNCTION0. Comparator 0 can also compare against the value of the PC Sampler // Counter (CYCCNT). -#define CPU_DWT_COMP0_COMP_W 32 -#define CPU_DWT_COMP0_COMP_M 0xFFFFFFFF -#define CPU_DWT_COMP0_COMP_S 0 +#define CPU_DWT_COMP0_COMP_W 32 +#define CPU_DWT_COMP0_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP0_COMP_S 0 //***************************************************************************** // @@ -427,9 +427,9 @@ // slightly more complex to enable matching an address wherever it appears on a // bus. So, if COMP0 is 3, this matches a word access of 0, because 3 would be // within the word. -#define CPU_DWT_MASK0_MASK_W 4 -#define CPU_DWT_MASK0_MASK_M 0x0000000F -#define CPU_DWT_MASK0_MASK_S 0 +#define CPU_DWT_MASK0_MASK_W 4 +#define CPU_DWT_MASK0_MASK_M 0x0000000F +#define CPU_DWT_MASK0_MASK_S 0 //***************************************************************************** // @@ -441,29 +441,29 @@ // This bit is set when the comparator matches, and indicates that the // operation defined by FUNCTION has occurred since this bit was last read. // This bit is cleared on read. -#define CPU_DWT_FUNCTION0_MATCHED 0x01000000 -#define CPU_DWT_FUNCTION0_MATCHED_BITN 24 -#define CPU_DWT_FUNCTION0_MATCHED_M 0x01000000 -#define CPU_DWT_FUNCTION0_MATCHED_S 24 +#define CPU_DWT_FUNCTION0_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION0_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION0_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION0_MATCHED_S 24 // Field: [7] CYCMATCH // // This bit is only available in comparator 0. When set, COMP0 will compare // against the cycle counter (CYCCNT). -#define CPU_DWT_FUNCTION0_CYCMATCH 0x00000080 -#define CPU_DWT_FUNCTION0_CYCMATCH_BITN 7 -#define CPU_DWT_FUNCTION0_CYCMATCH_M 0x00000080 -#define CPU_DWT_FUNCTION0_CYCMATCH_S 7 +#define CPU_DWT_FUNCTION0_CYCMATCH 0x00000080 +#define CPU_DWT_FUNCTION0_CYCMATCH_BITN 7 +#define CPU_DWT_FUNCTION0_CYCMATCH_M 0x00000080 +#define CPU_DWT_FUNCTION0_CYCMATCH_S 7 // Field: [5] EMITRANGE // // Emit range field. This bit permits emitting offset when range match occurs. // PC sampling is not supported when emit range is enabled. // This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. -#define CPU_DWT_FUNCTION0_EMITRANGE 0x00000020 -#define CPU_DWT_FUNCTION0_EMITRANGE_BITN 5 -#define CPU_DWT_FUNCTION0_EMITRANGE_M 0x00000020 -#define CPU_DWT_FUNCTION0_EMITRANGE_S 5 +#define CPU_DWT_FUNCTION0_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION0_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION0_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION0_EMITRANGE_S 5 // Field: [3:0] FUNCTION // @@ -500,9 +500,9 @@ // sampled for the first address of a burst. // Note 3: PC match is not recommended for watchpoints because it stops after // the instruction. It mainly guards and triggers the ETM. -#define CPU_DWT_FUNCTION0_FUNCTION_W 4 -#define CPU_DWT_FUNCTION0_FUNCTION_M 0x0000000F -#define CPU_DWT_FUNCTION0_FUNCTION_S 0 +#define CPU_DWT_FUNCTION0_FUNCTION_W 4 +#define CPU_DWT_FUNCTION0_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION0_FUNCTION_S 0 //***************************************************************************** // @@ -515,9 +515,9 @@ // FUNCTION1. // Comparator 1 can also compare data values. So this register can contain // reference values for data matching. -#define CPU_DWT_COMP1_COMP_W 32 -#define CPU_DWT_COMP1_COMP_M 0xFFFFFFFF -#define CPU_DWT_COMP1_COMP_S 0 +#define CPU_DWT_COMP1_COMP_W 32 +#define CPU_DWT_COMP1_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP1_COMP_S 0 //***************************************************************************** // @@ -532,9 +532,9 @@ // slightly more complex to enable matching an address wherever it appears on a // bus. So, if COMP1 is 3, this matches a word access of 0, because 3 would be // within the word. -#define CPU_DWT_MASK1_MASK_W 4 -#define CPU_DWT_MASK1_MASK_M 0x0000000F -#define CPU_DWT_MASK1_MASK_S 0 +#define CPU_DWT_MASK1_MASK_W 4 +#define CPU_DWT_MASK1_MASK_M 0x0000000F +#define CPU_DWT_MASK1_MASK_S 0 //***************************************************************************** // @@ -546,26 +546,26 @@ // This bit is set when the comparator matches, and indicates that the // operation defined by FUNCTION has occurred since this bit was last read. // This bit is cleared on read. -#define CPU_DWT_FUNCTION1_MATCHED 0x01000000 -#define CPU_DWT_FUNCTION1_MATCHED_BITN 24 -#define CPU_DWT_FUNCTION1_MATCHED_M 0x01000000 -#define CPU_DWT_FUNCTION1_MATCHED_S 24 +#define CPU_DWT_FUNCTION1_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION1_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION1_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION1_MATCHED_S 24 // Field: [19:16] DATAVADDR1 // // Identity of a second linked address comparator for data value matching when // DATAVMATCH == 1 and LNK1ENA == 1. -#define CPU_DWT_FUNCTION1_DATAVADDR1_W 4 -#define CPU_DWT_FUNCTION1_DATAVADDR1_M 0x000F0000 -#define CPU_DWT_FUNCTION1_DATAVADDR1_S 16 +#define CPU_DWT_FUNCTION1_DATAVADDR1_W 4 +#define CPU_DWT_FUNCTION1_DATAVADDR1_M 0x000F0000 +#define CPU_DWT_FUNCTION1_DATAVADDR1_S 16 // Field: [15:12] DATAVADDR0 // // Identity of a linked address comparator for data value matching when // DATAVMATCH == 1. -#define CPU_DWT_FUNCTION1_DATAVADDR0_W 4 -#define CPU_DWT_FUNCTION1_DATAVADDR0_M 0x0000F000 -#define CPU_DWT_FUNCTION1_DATAVADDR0_S 12 +#define CPU_DWT_FUNCTION1_DATAVADDR0_W 4 +#define CPU_DWT_FUNCTION1_DATAVADDR0_M 0x0000F000 +#define CPU_DWT_FUNCTION1_DATAVADDR0_S 12 // Field: [11:10] DATAVSIZE // @@ -575,9 +575,9 @@ // 0x1: Halfword // 0x2: Word // 0x3: Unpredictable. -#define CPU_DWT_FUNCTION1_DATAVSIZE_W 2 -#define CPU_DWT_FUNCTION1_DATAVSIZE_M 0x00000C00 -#define CPU_DWT_FUNCTION1_DATAVSIZE_S 10 +#define CPU_DWT_FUNCTION1_DATAVSIZE_W 2 +#define CPU_DWT_FUNCTION1_DATAVSIZE_M 0x00000C00 +#define CPU_DWT_FUNCTION1_DATAVSIZE_S 10 // Field: [9] LNK1ENA // @@ -585,10 +585,10 @@ // // 0: DATAVADDR1 not supported // 1: DATAVADDR1 supported (enabled) -#define CPU_DWT_FUNCTION1_LNK1ENA 0x00000200 -#define CPU_DWT_FUNCTION1_LNK1ENA_BITN 9 -#define CPU_DWT_FUNCTION1_LNK1ENA_M 0x00000200 -#define CPU_DWT_FUNCTION1_LNK1ENA_S 9 +#define CPU_DWT_FUNCTION1_LNK1ENA 0x00000200 +#define CPU_DWT_FUNCTION1_LNK1ENA_BITN 9 +#define CPU_DWT_FUNCTION1_LNK1ENA_M 0x00000200 +#define CPU_DWT_FUNCTION1_LNK1ENA_S 9 // Field: [8] DATAVMATCH // @@ -601,20 +601,20 @@ // those comparators only provide the address match for the data comparison. // // This bit is only available in comparator 1. -#define CPU_DWT_FUNCTION1_DATAVMATCH 0x00000100 -#define CPU_DWT_FUNCTION1_DATAVMATCH_BITN 8 -#define CPU_DWT_FUNCTION1_DATAVMATCH_M 0x00000100 -#define CPU_DWT_FUNCTION1_DATAVMATCH_S 8 +#define CPU_DWT_FUNCTION1_DATAVMATCH 0x00000100 +#define CPU_DWT_FUNCTION1_DATAVMATCH_BITN 8 +#define CPU_DWT_FUNCTION1_DATAVMATCH_M 0x00000100 +#define CPU_DWT_FUNCTION1_DATAVMATCH_S 8 // Field: [5] EMITRANGE // // Emit range field. This bit permits emitting offset when range match occurs. // PC sampling is not supported when emit range is enabled. // This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. -#define CPU_DWT_FUNCTION1_EMITRANGE 0x00000020 -#define CPU_DWT_FUNCTION1_EMITRANGE_BITN 5 -#define CPU_DWT_FUNCTION1_EMITRANGE_M 0x00000020 -#define CPU_DWT_FUNCTION1_EMITRANGE_S 5 +#define CPU_DWT_FUNCTION1_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION1_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION1_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION1_EMITRANGE_S 5 // Field: [3:0] FUNCTION // @@ -660,9 +660,9 @@ // reading DATAVMATCH. If it is not settable then data matching is unavailable. // Note 5: PC match is not recommended for watchpoints because it stops after // the instruction. It mainly guards and triggers the ETM. -#define CPU_DWT_FUNCTION1_FUNCTION_W 4 -#define CPU_DWT_FUNCTION1_FUNCTION_M 0x0000000F -#define CPU_DWT_FUNCTION1_FUNCTION_S 0 +#define CPU_DWT_FUNCTION1_FUNCTION_W 4 +#define CPU_DWT_FUNCTION1_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION1_FUNCTION_S 0 //***************************************************************************** // @@ -673,9 +673,9 @@ // // Reference value to compare against PC or the data address as given by // FUNCTION2. -#define CPU_DWT_COMP2_COMP_W 32 -#define CPU_DWT_COMP2_COMP_M 0xFFFFFFFF -#define CPU_DWT_COMP2_COMP_S 0 +#define CPU_DWT_COMP2_COMP_W 32 +#define CPU_DWT_COMP2_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP2_COMP_S 0 //***************************************************************************** // @@ -690,9 +690,9 @@ // slightly more complex to enable matching an address wherever it appears on a // bus. So, if COMP2 is 3, this matches a word access of 0, because 3 would be // within the word. -#define CPU_DWT_MASK2_MASK_W 4 -#define CPU_DWT_MASK2_MASK_M 0x0000000F -#define CPU_DWT_MASK2_MASK_S 0 +#define CPU_DWT_MASK2_MASK_W 4 +#define CPU_DWT_MASK2_MASK_M 0x0000000F +#define CPU_DWT_MASK2_MASK_S 0 //***************************************************************************** // @@ -704,20 +704,20 @@ // This bit is set when the comparator matches, and indicates that the // operation defined by FUNCTION has occurred since this bit was last read. // This bit is cleared on read. -#define CPU_DWT_FUNCTION2_MATCHED 0x01000000 -#define CPU_DWT_FUNCTION2_MATCHED_BITN 24 -#define CPU_DWT_FUNCTION2_MATCHED_M 0x01000000 -#define CPU_DWT_FUNCTION2_MATCHED_S 24 +#define CPU_DWT_FUNCTION2_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION2_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION2_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION2_MATCHED_S 24 // Field: [5] EMITRANGE // // Emit range field. This bit permits emitting offset when range match occurs. // PC sampling is not supported when emit range is enabled. // This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. -#define CPU_DWT_FUNCTION2_EMITRANGE 0x00000020 -#define CPU_DWT_FUNCTION2_EMITRANGE_BITN 5 -#define CPU_DWT_FUNCTION2_EMITRANGE_M 0x00000020 -#define CPU_DWT_FUNCTION2_EMITRANGE_S 5 +#define CPU_DWT_FUNCTION2_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION2_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION2_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION2_EMITRANGE_S 5 // Field: [3:0] FUNCTION // @@ -754,9 +754,9 @@ // sampled for the first address of a burst. // Note 3: PC match is not recommended for watchpoints because it stops after // the instruction. It mainly guards and triggers the ETM. -#define CPU_DWT_FUNCTION2_FUNCTION_W 4 -#define CPU_DWT_FUNCTION2_FUNCTION_M 0x0000000F -#define CPU_DWT_FUNCTION2_FUNCTION_S 0 +#define CPU_DWT_FUNCTION2_FUNCTION_W 4 +#define CPU_DWT_FUNCTION2_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION2_FUNCTION_S 0 //***************************************************************************** // @@ -767,9 +767,9 @@ // // Reference value to compare against PC or the data address as given by // FUNCTION3. -#define CPU_DWT_COMP3_COMP_W 32 -#define CPU_DWT_COMP3_COMP_M 0xFFFFFFFF -#define CPU_DWT_COMP3_COMP_S 0 +#define CPU_DWT_COMP3_COMP_W 32 +#define CPU_DWT_COMP3_COMP_M 0xFFFFFFFF +#define CPU_DWT_COMP3_COMP_S 0 //***************************************************************************** // @@ -784,9 +784,9 @@ // slightly more complex to enable matching an address wherever it appears on a // bus. So, if COMP3 is 3, this matches a word access of 0, because 3 would be // within the word. -#define CPU_DWT_MASK3_MASK_W 4 -#define CPU_DWT_MASK3_MASK_M 0x0000000F -#define CPU_DWT_MASK3_MASK_S 0 +#define CPU_DWT_MASK3_MASK_W 4 +#define CPU_DWT_MASK3_MASK_M 0x0000000F +#define CPU_DWT_MASK3_MASK_S 0 //***************************************************************************** // @@ -798,20 +798,20 @@ // This bit is set when the comparator matches, and indicates that the // operation defined by FUNCTION has occurred since this bit was last read. // This bit is cleared on read. -#define CPU_DWT_FUNCTION3_MATCHED 0x01000000 -#define CPU_DWT_FUNCTION3_MATCHED_BITN 24 -#define CPU_DWT_FUNCTION3_MATCHED_M 0x01000000 -#define CPU_DWT_FUNCTION3_MATCHED_S 24 +#define CPU_DWT_FUNCTION3_MATCHED 0x01000000 +#define CPU_DWT_FUNCTION3_MATCHED_BITN 24 +#define CPU_DWT_FUNCTION3_MATCHED_M 0x01000000 +#define CPU_DWT_FUNCTION3_MATCHED_S 24 // Field: [5] EMITRANGE // // Emit range field. This bit permits emitting offset when range match occurs. // PC sampling is not supported when emit range is enabled. // This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. -#define CPU_DWT_FUNCTION3_EMITRANGE 0x00000020 -#define CPU_DWT_FUNCTION3_EMITRANGE_BITN 5 -#define CPU_DWT_FUNCTION3_EMITRANGE_M 0x00000020 -#define CPU_DWT_FUNCTION3_EMITRANGE_S 5 +#define CPU_DWT_FUNCTION3_EMITRANGE 0x00000020 +#define CPU_DWT_FUNCTION3_EMITRANGE_BITN 5 +#define CPU_DWT_FUNCTION3_EMITRANGE_M 0x00000020 +#define CPU_DWT_FUNCTION3_EMITRANGE_S 5 // Field: [3:0] FUNCTION // @@ -848,9 +848,8 @@ // sampled for the first address of a burst. // Note 3: PC match is not recommended for watchpoints because it stops after // the instruction. It mainly guards and triggers the ETM. -#define CPU_DWT_FUNCTION3_FUNCTION_W 4 -#define CPU_DWT_FUNCTION3_FUNCTION_M 0x0000000F -#define CPU_DWT_FUNCTION3_FUNCTION_S 0 - +#define CPU_DWT_FUNCTION3_FUNCTION_W 4 +#define CPU_DWT_FUNCTION3_FUNCTION_M 0x0000000F +#define CPU_DWT_FUNCTION3_FUNCTION_S 0 #endif // __CPU_DWT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_fpb.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_fpb.h index f70d8bd..712f034 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_fpb.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_fpb.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_cpu_fpb_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_cpu_fpb_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CPU_FPB_H__ #define __HW_CPU_FPB_H__ @@ -44,34 +44,34 @@ // //***************************************************************************** // Control -#define CPU_FPB_O_CTRL 0x00000000 +#define CPU_FPB_O_CTRL 0x00000000 // Remap -#define CPU_FPB_O_REMAP 0x00000004 +#define CPU_FPB_O_REMAP 0x00000004 // Comparator 0 -#define CPU_FPB_O_COMP0 0x00000008 +#define CPU_FPB_O_COMP0 0x00000008 // Comparator 1 -#define CPU_FPB_O_COMP1 0x0000000C +#define CPU_FPB_O_COMP1 0x0000000C // Comparator 2 -#define CPU_FPB_O_COMP2 0x00000010 +#define CPU_FPB_O_COMP2 0x00000010 // Comparator 3 -#define CPU_FPB_O_COMP3 0x00000014 +#define CPU_FPB_O_COMP3 0x00000014 // Comparator 4 -#define CPU_FPB_O_COMP4 0x00000018 +#define CPU_FPB_O_COMP4 0x00000018 // Comparator 5 -#define CPU_FPB_O_COMP5 0x0000001C +#define CPU_FPB_O_COMP5 0x0000001C // Comparator 6 -#define CPU_FPB_O_COMP6 0x00000020 +#define CPU_FPB_O_COMP6 0x00000020 // Comparator 7 -#define CPU_FPB_O_COMP7 0x00000024 +#define CPU_FPB_O_COMP7 0x00000024 //***************************************************************************** // @@ -84,9 +84,9 @@ // Where less than sixteen code comparators are provided, the bank count is // zero, and the number present indicated by NUM_CODE1. This read only field // contains 3'b000 to indicate 0 banks for Cortex-M processor. -#define CPU_FPB_CTRL_NUM_CODE2_W 2 -#define CPU_FPB_CTRL_NUM_CODE2_M 0x00003000 -#define CPU_FPB_CTRL_NUM_CODE2_S 12 +#define CPU_FPB_CTRL_NUM_CODE2_W 2 +#define CPU_FPB_CTRL_NUM_CODE2_M 0x00003000 +#define CPU_FPB_CTRL_NUM_CODE2_S 12 // Field: [11:8] NUM_LIT // @@ -94,9 +94,9 @@ // // 0x0: No literal slots // 0x2: Two literal slots -#define CPU_FPB_CTRL_NUM_LIT_W 4 -#define CPU_FPB_CTRL_NUM_LIT_M 0x00000F00 -#define CPU_FPB_CTRL_NUM_LIT_S 8 +#define CPU_FPB_CTRL_NUM_LIT_W 4 +#define CPU_FPB_CTRL_NUM_LIT_M 0x00000F00 +#define CPU_FPB_CTRL_NUM_LIT_S 8 // Field: [7:4] NUM_CODE1 // @@ -105,18 +105,18 @@ // 0x0: No code slots // 0x2: Two code slots // 0x6: Six code slots -#define CPU_FPB_CTRL_NUM_CODE1_W 4 -#define CPU_FPB_CTRL_NUM_CODE1_M 0x000000F0 -#define CPU_FPB_CTRL_NUM_CODE1_S 4 +#define CPU_FPB_CTRL_NUM_CODE1_W 4 +#define CPU_FPB_CTRL_NUM_CODE1_M 0x000000F0 +#define CPU_FPB_CTRL_NUM_CODE1_S 4 // Field: [1] KEY // // Key field. In order to write to this register, this bit-field must be // written to '1'. This bit always reads 0. -#define CPU_FPB_CTRL_KEY 0x00000002 -#define CPU_FPB_CTRL_KEY_BITN 1 -#define CPU_FPB_CTRL_KEY_M 0x00000002 -#define CPU_FPB_CTRL_KEY_S 1 +#define CPU_FPB_CTRL_KEY 0x00000002 +#define CPU_FPB_CTRL_KEY_BITN 1 +#define CPU_FPB_CTRL_KEY_M 0x00000002 +#define CPU_FPB_CTRL_KEY_S 1 // Field: [0] ENABLE // @@ -124,10 +124,10 @@ // // 0x0: Flash patch unit disabled // 0x1: Flash patch unit enabled -#define CPU_FPB_CTRL_ENABLE 0x00000001 -#define CPU_FPB_CTRL_ENABLE_BITN 0 -#define CPU_FPB_CTRL_ENABLE_M 0x00000001 -#define CPU_FPB_CTRL_ENABLE_S 0 +#define CPU_FPB_CTRL_ENABLE 0x00000001 +#define CPU_FPB_CTRL_ENABLE_BITN 0 +#define CPU_FPB_CTRL_ENABLE_M 0x00000001 +#define CPU_FPB_CTRL_ENABLE_S 0 //***************************************************************************** // @@ -137,9 +137,9 @@ // Field: [28:5] REMAP // // Remap base address field. -#define CPU_FPB_REMAP_REMAP_W 24 -#define CPU_FPB_REMAP_REMAP_M 0x1FFFFFE0 -#define CPU_FPB_REMAP_REMAP_S 5 +#define CPU_FPB_REMAP_REMAP_W 24 +#define CPU_FPB_REMAP_REMAP_M 0x1FFFFFE0 +#define CPU_FPB_REMAP_REMAP_S 5 //***************************************************************************** // @@ -155,16 +155,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP0_REPLACE_W 2 -#define CPU_FPB_COMP0_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP0_REPLACE_S 30 +#define CPU_FPB_COMP0_REPLACE_W 2 +#define CPU_FPB_COMP0_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP0_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP0_COMP_W 27 -#define CPU_FPB_COMP0_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP0_COMP_S 2 +#define CPU_FPB_COMP0_COMP_W 27 +#define CPU_FPB_COMP0_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP0_COMP_S 2 // Field: [0] ENABLE // @@ -173,10 +173,10 @@ // // 0x0: Compare and remap for comparator 0 disabled // 0x1: Compare and remap for comparator 0 enabled -#define CPU_FPB_COMP0_ENABLE 0x00000001 -#define CPU_FPB_COMP0_ENABLE_BITN 0 -#define CPU_FPB_COMP0_ENABLE_M 0x00000001 -#define CPU_FPB_COMP0_ENABLE_S 0 +#define CPU_FPB_COMP0_ENABLE 0x00000001 +#define CPU_FPB_COMP0_ENABLE_BITN 0 +#define CPU_FPB_COMP0_ENABLE_M 0x00000001 +#define CPU_FPB_COMP0_ENABLE_S 0 //***************************************************************************** // @@ -192,16 +192,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP1_REPLACE_W 2 -#define CPU_FPB_COMP1_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP1_REPLACE_S 30 +#define CPU_FPB_COMP1_REPLACE_W 2 +#define CPU_FPB_COMP1_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP1_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP1_COMP_W 27 -#define CPU_FPB_COMP1_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP1_COMP_S 2 +#define CPU_FPB_COMP1_COMP_W 27 +#define CPU_FPB_COMP1_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP1_COMP_S 2 // Field: [0] ENABLE // @@ -210,10 +210,10 @@ // // 0x0: Compare and remap for comparator 1 disabled // 0x1: Compare and remap for comparator 1 enabled -#define CPU_FPB_COMP1_ENABLE 0x00000001 -#define CPU_FPB_COMP1_ENABLE_BITN 0 -#define CPU_FPB_COMP1_ENABLE_M 0x00000001 -#define CPU_FPB_COMP1_ENABLE_S 0 +#define CPU_FPB_COMP1_ENABLE 0x00000001 +#define CPU_FPB_COMP1_ENABLE_BITN 0 +#define CPU_FPB_COMP1_ENABLE_M 0x00000001 +#define CPU_FPB_COMP1_ENABLE_S 0 //***************************************************************************** // @@ -229,16 +229,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP2_REPLACE_W 2 -#define CPU_FPB_COMP2_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP2_REPLACE_S 30 +#define CPU_FPB_COMP2_REPLACE_W 2 +#define CPU_FPB_COMP2_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP2_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP2_COMP_W 27 -#define CPU_FPB_COMP2_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP2_COMP_S 2 +#define CPU_FPB_COMP2_COMP_W 27 +#define CPU_FPB_COMP2_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP2_COMP_S 2 // Field: [0] ENABLE // @@ -247,10 +247,10 @@ // // 0x0: Compare and remap for comparator 2 disabled // 0x1: Compare and remap for comparator 2 enabled -#define CPU_FPB_COMP2_ENABLE 0x00000001 -#define CPU_FPB_COMP2_ENABLE_BITN 0 -#define CPU_FPB_COMP2_ENABLE_M 0x00000001 -#define CPU_FPB_COMP2_ENABLE_S 0 +#define CPU_FPB_COMP2_ENABLE 0x00000001 +#define CPU_FPB_COMP2_ENABLE_BITN 0 +#define CPU_FPB_COMP2_ENABLE_M 0x00000001 +#define CPU_FPB_COMP2_ENABLE_S 0 //***************************************************************************** // @@ -266,16 +266,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP3_REPLACE_W 2 -#define CPU_FPB_COMP3_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP3_REPLACE_S 30 +#define CPU_FPB_COMP3_REPLACE_W 2 +#define CPU_FPB_COMP3_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP3_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP3_COMP_W 27 -#define CPU_FPB_COMP3_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP3_COMP_S 2 +#define CPU_FPB_COMP3_COMP_W 27 +#define CPU_FPB_COMP3_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP3_COMP_S 2 // Field: [0] ENABLE // @@ -284,10 +284,10 @@ // // 0x0: Compare and remap for comparator 3 disabled // 0x1: Compare and remap for comparator 3 enabled -#define CPU_FPB_COMP3_ENABLE 0x00000001 -#define CPU_FPB_COMP3_ENABLE_BITN 0 -#define CPU_FPB_COMP3_ENABLE_M 0x00000001 -#define CPU_FPB_COMP3_ENABLE_S 0 +#define CPU_FPB_COMP3_ENABLE 0x00000001 +#define CPU_FPB_COMP3_ENABLE_BITN 0 +#define CPU_FPB_COMP3_ENABLE_M 0x00000001 +#define CPU_FPB_COMP3_ENABLE_S 0 //***************************************************************************** // @@ -303,16 +303,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP4_REPLACE_W 2 -#define CPU_FPB_COMP4_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP4_REPLACE_S 30 +#define CPU_FPB_COMP4_REPLACE_W 2 +#define CPU_FPB_COMP4_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP4_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP4_COMP_W 27 -#define CPU_FPB_COMP4_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP4_COMP_S 2 +#define CPU_FPB_COMP4_COMP_W 27 +#define CPU_FPB_COMP4_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP4_COMP_S 2 // Field: [0] ENABLE // @@ -321,10 +321,10 @@ // // 0x0: Compare and remap for comparator 4 disabled // 0x1: Compare and remap for comparator 4 enabled -#define CPU_FPB_COMP4_ENABLE 0x00000001 -#define CPU_FPB_COMP4_ENABLE_BITN 0 -#define CPU_FPB_COMP4_ENABLE_M 0x00000001 -#define CPU_FPB_COMP4_ENABLE_S 0 +#define CPU_FPB_COMP4_ENABLE 0x00000001 +#define CPU_FPB_COMP4_ENABLE_BITN 0 +#define CPU_FPB_COMP4_ENABLE_M 0x00000001 +#define CPU_FPB_COMP4_ENABLE_S 0 //***************************************************************************** // @@ -340,16 +340,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP5_REPLACE_W 2 -#define CPU_FPB_COMP5_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP5_REPLACE_S 30 +#define CPU_FPB_COMP5_REPLACE_W 2 +#define CPU_FPB_COMP5_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP5_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP5_COMP_W 27 -#define CPU_FPB_COMP5_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP5_COMP_S 2 +#define CPU_FPB_COMP5_COMP_W 27 +#define CPU_FPB_COMP5_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP5_COMP_S 2 // Field: [0] ENABLE // @@ -358,10 +358,10 @@ // // 0x0: Compare and remap for comparator 5 disabled // 0x1: Compare and remap for comparator 5 enabled -#define CPU_FPB_COMP5_ENABLE 0x00000001 -#define CPU_FPB_COMP5_ENABLE_BITN 0 -#define CPU_FPB_COMP5_ENABLE_M 0x00000001 -#define CPU_FPB_COMP5_ENABLE_S 0 +#define CPU_FPB_COMP5_ENABLE 0x00000001 +#define CPU_FPB_COMP5_ENABLE_BITN 0 +#define CPU_FPB_COMP5_ENABLE_M 0x00000001 +#define CPU_FPB_COMP5_ENABLE_S 0 //***************************************************************************** // @@ -378,16 +378,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP6_REPLACE_W 2 -#define CPU_FPB_COMP6_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP6_REPLACE_S 30 +#define CPU_FPB_COMP6_REPLACE_W 2 +#define CPU_FPB_COMP6_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP6_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP6_COMP_W 27 -#define CPU_FPB_COMP6_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP6_COMP_S 2 +#define CPU_FPB_COMP6_COMP_W 27 +#define CPU_FPB_COMP6_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP6_COMP_S 2 // Field: [0] ENABLE // @@ -396,10 +396,10 @@ // // 0x0: Compare and remap for comparator 6 disabled // 0x1: Compare and remap for comparator 6 enabled -#define CPU_FPB_COMP6_ENABLE 0x00000001 -#define CPU_FPB_COMP6_ENABLE_BITN 0 -#define CPU_FPB_COMP6_ENABLE_M 0x00000001 -#define CPU_FPB_COMP6_ENABLE_S 0 +#define CPU_FPB_COMP6_ENABLE 0x00000001 +#define CPU_FPB_COMP6_ENABLE_BITN 0 +#define CPU_FPB_COMP6_ENABLE_M 0x00000001 +#define CPU_FPB_COMP6_ENABLE_S 0 //***************************************************************************** // @@ -416,16 +416,16 @@ // 0x1: Set BKPT on lower halfword, upper is unaffected // 0x2: Set BKPT on upper halfword, lower is unaffected // 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP7_REPLACE_W 2 -#define CPU_FPB_COMP7_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP7_REPLACE_S 30 +#define CPU_FPB_COMP7_REPLACE_W 2 +#define CPU_FPB_COMP7_REPLACE_M 0xC0000000 +#define CPU_FPB_COMP7_REPLACE_S 30 // Field: [28:2] COMP // // Comparison address. -#define CPU_FPB_COMP7_COMP_W 27 -#define CPU_FPB_COMP7_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP7_COMP_S 2 +#define CPU_FPB_COMP7_COMP_W 27 +#define CPU_FPB_COMP7_COMP_M 0x1FFFFFFC +#define CPU_FPB_COMP7_COMP_S 2 // Field: [0] ENABLE // @@ -434,10 +434,9 @@ // // 0x0: Compare and remap for comparator 7 disabled // 0x1: Compare and remap for comparator 7 enabled -#define CPU_FPB_COMP7_ENABLE 0x00000001 -#define CPU_FPB_COMP7_ENABLE_BITN 0 -#define CPU_FPB_COMP7_ENABLE_M 0x00000001 -#define CPU_FPB_COMP7_ENABLE_S 0 - +#define CPU_FPB_COMP7_ENABLE 0x00000001 +#define CPU_FPB_COMP7_ENABLE_BITN 0 +#define CPU_FPB_COMP7_ENABLE_M 0x00000001 +#define CPU_FPB_COMP7_ENABLE_S 0 #endif // __CPU_FPB__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_itm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_itm.h index 9996da5..d64c35d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_itm.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_itm.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_cpu_itm_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_cpu_itm_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CPU_ITM_H__ #define __HW_CPU_ITM_H__ @@ -44,115 +44,115 @@ // //***************************************************************************** // Stimulus Port 0 -#define CPU_ITM_O_STIM0 0x00000000 +#define CPU_ITM_O_STIM0 0x00000000 // Stimulus Port 1 -#define CPU_ITM_O_STIM1 0x00000004 +#define CPU_ITM_O_STIM1 0x00000004 // Stimulus Port 2 -#define CPU_ITM_O_STIM2 0x00000008 +#define CPU_ITM_O_STIM2 0x00000008 // Stimulus Port 3 -#define CPU_ITM_O_STIM3 0x0000000C +#define CPU_ITM_O_STIM3 0x0000000C // Stimulus Port 4 -#define CPU_ITM_O_STIM4 0x00000010 +#define CPU_ITM_O_STIM4 0x00000010 // Stimulus Port 5 -#define CPU_ITM_O_STIM5 0x00000014 +#define CPU_ITM_O_STIM5 0x00000014 // Stimulus Port 6 -#define CPU_ITM_O_STIM6 0x00000018 +#define CPU_ITM_O_STIM6 0x00000018 // Stimulus Port 7 -#define CPU_ITM_O_STIM7 0x0000001C +#define CPU_ITM_O_STIM7 0x0000001C // Stimulus Port 8 -#define CPU_ITM_O_STIM8 0x00000020 +#define CPU_ITM_O_STIM8 0x00000020 // Stimulus Port 9 -#define CPU_ITM_O_STIM9 0x00000024 +#define CPU_ITM_O_STIM9 0x00000024 // Stimulus Port 10 -#define CPU_ITM_O_STIM10 0x00000028 +#define CPU_ITM_O_STIM10 0x00000028 // Stimulus Port 11 -#define CPU_ITM_O_STIM11 0x0000002C +#define CPU_ITM_O_STIM11 0x0000002C // Stimulus Port 12 -#define CPU_ITM_O_STIM12 0x00000030 +#define CPU_ITM_O_STIM12 0x00000030 // Stimulus Port 13 -#define CPU_ITM_O_STIM13 0x00000034 +#define CPU_ITM_O_STIM13 0x00000034 // Stimulus Port 14 -#define CPU_ITM_O_STIM14 0x00000038 +#define CPU_ITM_O_STIM14 0x00000038 // Stimulus Port 15 -#define CPU_ITM_O_STIM15 0x0000003C +#define CPU_ITM_O_STIM15 0x0000003C // Stimulus Port 16 -#define CPU_ITM_O_STIM16 0x00000040 +#define CPU_ITM_O_STIM16 0x00000040 // Stimulus Port 17 -#define CPU_ITM_O_STIM17 0x00000044 +#define CPU_ITM_O_STIM17 0x00000044 // Stimulus Port 18 -#define CPU_ITM_O_STIM18 0x00000048 +#define CPU_ITM_O_STIM18 0x00000048 // Stimulus Port 19 -#define CPU_ITM_O_STIM19 0x0000004C +#define CPU_ITM_O_STIM19 0x0000004C // Stimulus Port 20 -#define CPU_ITM_O_STIM20 0x00000050 +#define CPU_ITM_O_STIM20 0x00000050 // Stimulus Port 21 -#define CPU_ITM_O_STIM21 0x00000054 +#define CPU_ITM_O_STIM21 0x00000054 // Stimulus Port 22 -#define CPU_ITM_O_STIM22 0x00000058 +#define CPU_ITM_O_STIM22 0x00000058 // Stimulus Port 23 -#define CPU_ITM_O_STIM23 0x0000005C +#define CPU_ITM_O_STIM23 0x0000005C // Stimulus Port 24 -#define CPU_ITM_O_STIM24 0x00000060 +#define CPU_ITM_O_STIM24 0x00000060 // Stimulus Port 25 -#define CPU_ITM_O_STIM25 0x00000064 +#define CPU_ITM_O_STIM25 0x00000064 // Stimulus Port 26 -#define CPU_ITM_O_STIM26 0x00000068 +#define CPU_ITM_O_STIM26 0x00000068 // Stimulus Port 27 -#define CPU_ITM_O_STIM27 0x0000006C +#define CPU_ITM_O_STIM27 0x0000006C // Stimulus Port 28 -#define CPU_ITM_O_STIM28 0x00000070 +#define CPU_ITM_O_STIM28 0x00000070 // Stimulus Port 29 -#define CPU_ITM_O_STIM29 0x00000074 +#define CPU_ITM_O_STIM29 0x00000074 // Stimulus Port 30 -#define CPU_ITM_O_STIM30 0x00000078 +#define CPU_ITM_O_STIM30 0x00000078 // Stimulus Port 31 -#define CPU_ITM_O_STIM31 0x0000007C +#define CPU_ITM_O_STIM31 0x0000007C // Trace Enable -#define CPU_ITM_O_TER 0x00000E00 +#define CPU_ITM_O_TER 0x00000E00 // Trace Privilege -#define CPU_ITM_O_TPR 0x00000E40 +#define CPU_ITM_O_TPR 0x00000E40 // Trace Control -#define CPU_ITM_O_TCR 0x00000E80 +#define CPU_ITM_O_TCR 0x00000E80 // Lock Access -#define CPU_ITM_O_LAR 0x00000FB0 +#define CPU_ITM_O_LAR 0x00000FB0 // Lock Status -#define CPU_ITM_O_LSR 0x00000FB4 +#define CPU_ITM_O_LSR 0x00000FB4 //***************************************************************************** // @@ -167,9 +167,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM0_STIM0_W 32 -#define CPU_ITM_STIM0_STIM0_M 0xFFFFFFFF -#define CPU_ITM_STIM0_STIM0_S 0 +#define CPU_ITM_STIM0_STIM0_W 32 +#define CPU_ITM_STIM0_STIM0_M 0xFFFFFFFF +#define CPU_ITM_STIM0_STIM0_S 0 //***************************************************************************** // @@ -184,9 +184,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM1_STIM1_W 32 -#define CPU_ITM_STIM1_STIM1_M 0xFFFFFFFF -#define CPU_ITM_STIM1_STIM1_S 0 +#define CPU_ITM_STIM1_STIM1_W 32 +#define CPU_ITM_STIM1_STIM1_M 0xFFFFFFFF +#define CPU_ITM_STIM1_STIM1_S 0 //***************************************************************************** // @@ -201,9 +201,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM2_STIM2_W 32 -#define CPU_ITM_STIM2_STIM2_M 0xFFFFFFFF -#define CPU_ITM_STIM2_STIM2_S 0 +#define CPU_ITM_STIM2_STIM2_W 32 +#define CPU_ITM_STIM2_STIM2_M 0xFFFFFFFF +#define CPU_ITM_STIM2_STIM2_S 0 //***************************************************************************** // @@ -218,9 +218,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM3_STIM3_W 32 -#define CPU_ITM_STIM3_STIM3_M 0xFFFFFFFF -#define CPU_ITM_STIM3_STIM3_S 0 +#define CPU_ITM_STIM3_STIM3_W 32 +#define CPU_ITM_STIM3_STIM3_M 0xFFFFFFFF +#define CPU_ITM_STIM3_STIM3_S 0 //***************************************************************************** // @@ -235,9 +235,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM4_STIM4_W 32 -#define CPU_ITM_STIM4_STIM4_M 0xFFFFFFFF -#define CPU_ITM_STIM4_STIM4_S 0 +#define CPU_ITM_STIM4_STIM4_W 32 +#define CPU_ITM_STIM4_STIM4_M 0xFFFFFFFF +#define CPU_ITM_STIM4_STIM4_S 0 //***************************************************************************** // @@ -252,9 +252,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM5_STIM5_W 32 -#define CPU_ITM_STIM5_STIM5_M 0xFFFFFFFF -#define CPU_ITM_STIM5_STIM5_S 0 +#define CPU_ITM_STIM5_STIM5_W 32 +#define CPU_ITM_STIM5_STIM5_M 0xFFFFFFFF +#define CPU_ITM_STIM5_STIM5_S 0 //***************************************************************************** // @@ -269,9 +269,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM6_STIM6_W 32 -#define CPU_ITM_STIM6_STIM6_M 0xFFFFFFFF -#define CPU_ITM_STIM6_STIM6_S 0 +#define CPU_ITM_STIM6_STIM6_W 32 +#define CPU_ITM_STIM6_STIM6_M 0xFFFFFFFF +#define CPU_ITM_STIM6_STIM6_S 0 //***************************************************************************** // @@ -286,9 +286,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM7_STIM7_W 32 -#define CPU_ITM_STIM7_STIM7_M 0xFFFFFFFF -#define CPU_ITM_STIM7_STIM7_S 0 +#define CPU_ITM_STIM7_STIM7_W 32 +#define CPU_ITM_STIM7_STIM7_M 0xFFFFFFFF +#define CPU_ITM_STIM7_STIM7_S 0 //***************************************************************************** // @@ -303,9 +303,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM8_STIM8_W 32 -#define CPU_ITM_STIM8_STIM8_M 0xFFFFFFFF -#define CPU_ITM_STIM8_STIM8_S 0 +#define CPU_ITM_STIM8_STIM8_W 32 +#define CPU_ITM_STIM8_STIM8_M 0xFFFFFFFF +#define CPU_ITM_STIM8_STIM8_S 0 //***************************************************************************** // @@ -320,9 +320,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM9_STIM9_W 32 -#define CPU_ITM_STIM9_STIM9_M 0xFFFFFFFF -#define CPU_ITM_STIM9_STIM9_S 0 +#define CPU_ITM_STIM9_STIM9_W 32 +#define CPU_ITM_STIM9_STIM9_M 0xFFFFFFFF +#define CPU_ITM_STIM9_STIM9_S 0 //***************************************************************************** // @@ -337,9 +337,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM10_STIM10_W 32 -#define CPU_ITM_STIM10_STIM10_M 0xFFFFFFFF -#define CPU_ITM_STIM10_STIM10_S 0 +#define CPU_ITM_STIM10_STIM10_W 32 +#define CPU_ITM_STIM10_STIM10_M 0xFFFFFFFF +#define CPU_ITM_STIM10_STIM10_S 0 //***************************************************************************** // @@ -354,9 +354,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM11_STIM11_W 32 -#define CPU_ITM_STIM11_STIM11_M 0xFFFFFFFF -#define CPU_ITM_STIM11_STIM11_S 0 +#define CPU_ITM_STIM11_STIM11_W 32 +#define CPU_ITM_STIM11_STIM11_M 0xFFFFFFFF +#define CPU_ITM_STIM11_STIM11_S 0 //***************************************************************************** // @@ -371,9 +371,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM12_STIM12_W 32 -#define CPU_ITM_STIM12_STIM12_M 0xFFFFFFFF -#define CPU_ITM_STIM12_STIM12_S 0 +#define CPU_ITM_STIM12_STIM12_W 32 +#define CPU_ITM_STIM12_STIM12_M 0xFFFFFFFF +#define CPU_ITM_STIM12_STIM12_S 0 //***************************************************************************** // @@ -388,9 +388,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM13_STIM13_W 32 -#define CPU_ITM_STIM13_STIM13_M 0xFFFFFFFF -#define CPU_ITM_STIM13_STIM13_S 0 +#define CPU_ITM_STIM13_STIM13_W 32 +#define CPU_ITM_STIM13_STIM13_M 0xFFFFFFFF +#define CPU_ITM_STIM13_STIM13_S 0 //***************************************************************************** // @@ -405,9 +405,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM14_STIM14_W 32 -#define CPU_ITM_STIM14_STIM14_M 0xFFFFFFFF -#define CPU_ITM_STIM14_STIM14_S 0 +#define CPU_ITM_STIM14_STIM14_W 32 +#define CPU_ITM_STIM14_STIM14_M 0xFFFFFFFF +#define CPU_ITM_STIM14_STIM14_S 0 //***************************************************************************** // @@ -422,9 +422,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM15_STIM15_W 32 -#define CPU_ITM_STIM15_STIM15_M 0xFFFFFFFF -#define CPU_ITM_STIM15_STIM15_S 0 +#define CPU_ITM_STIM15_STIM15_W 32 +#define CPU_ITM_STIM15_STIM15_M 0xFFFFFFFF +#define CPU_ITM_STIM15_STIM15_S 0 //***************************************************************************** // @@ -439,9 +439,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM16_STIM16_W 32 -#define CPU_ITM_STIM16_STIM16_M 0xFFFFFFFF -#define CPU_ITM_STIM16_STIM16_S 0 +#define CPU_ITM_STIM16_STIM16_W 32 +#define CPU_ITM_STIM16_STIM16_M 0xFFFFFFFF +#define CPU_ITM_STIM16_STIM16_S 0 //***************************************************************************** // @@ -456,9 +456,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM17_STIM17_W 32 -#define CPU_ITM_STIM17_STIM17_M 0xFFFFFFFF -#define CPU_ITM_STIM17_STIM17_S 0 +#define CPU_ITM_STIM17_STIM17_W 32 +#define CPU_ITM_STIM17_STIM17_M 0xFFFFFFFF +#define CPU_ITM_STIM17_STIM17_S 0 //***************************************************************************** // @@ -473,9 +473,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM18_STIM18_W 32 -#define CPU_ITM_STIM18_STIM18_M 0xFFFFFFFF -#define CPU_ITM_STIM18_STIM18_S 0 +#define CPU_ITM_STIM18_STIM18_W 32 +#define CPU_ITM_STIM18_STIM18_M 0xFFFFFFFF +#define CPU_ITM_STIM18_STIM18_S 0 //***************************************************************************** // @@ -490,9 +490,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM19_STIM19_W 32 -#define CPU_ITM_STIM19_STIM19_M 0xFFFFFFFF -#define CPU_ITM_STIM19_STIM19_S 0 +#define CPU_ITM_STIM19_STIM19_W 32 +#define CPU_ITM_STIM19_STIM19_M 0xFFFFFFFF +#define CPU_ITM_STIM19_STIM19_S 0 //***************************************************************************** // @@ -507,9 +507,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM20_STIM20_W 32 -#define CPU_ITM_STIM20_STIM20_M 0xFFFFFFFF -#define CPU_ITM_STIM20_STIM20_S 0 +#define CPU_ITM_STIM20_STIM20_W 32 +#define CPU_ITM_STIM20_STIM20_M 0xFFFFFFFF +#define CPU_ITM_STIM20_STIM20_S 0 //***************************************************************************** // @@ -524,9 +524,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM21_STIM21_W 32 -#define CPU_ITM_STIM21_STIM21_M 0xFFFFFFFF -#define CPU_ITM_STIM21_STIM21_S 0 +#define CPU_ITM_STIM21_STIM21_W 32 +#define CPU_ITM_STIM21_STIM21_M 0xFFFFFFFF +#define CPU_ITM_STIM21_STIM21_S 0 //***************************************************************************** // @@ -541,9 +541,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM22_STIM22_W 32 -#define CPU_ITM_STIM22_STIM22_M 0xFFFFFFFF -#define CPU_ITM_STIM22_STIM22_S 0 +#define CPU_ITM_STIM22_STIM22_W 32 +#define CPU_ITM_STIM22_STIM22_M 0xFFFFFFFF +#define CPU_ITM_STIM22_STIM22_S 0 //***************************************************************************** // @@ -558,9 +558,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM23_STIM23_W 32 -#define CPU_ITM_STIM23_STIM23_M 0xFFFFFFFF -#define CPU_ITM_STIM23_STIM23_S 0 +#define CPU_ITM_STIM23_STIM23_W 32 +#define CPU_ITM_STIM23_STIM23_M 0xFFFFFFFF +#define CPU_ITM_STIM23_STIM23_S 0 //***************************************************************************** // @@ -575,9 +575,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM24_STIM24_W 32 -#define CPU_ITM_STIM24_STIM24_M 0xFFFFFFFF -#define CPU_ITM_STIM24_STIM24_S 0 +#define CPU_ITM_STIM24_STIM24_W 32 +#define CPU_ITM_STIM24_STIM24_M 0xFFFFFFFF +#define CPU_ITM_STIM24_STIM24_S 0 //***************************************************************************** // @@ -592,9 +592,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM25_STIM25_W 32 -#define CPU_ITM_STIM25_STIM25_M 0xFFFFFFFF -#define CPU_ITM_STIM25_STIM25_S 0 +#define CPU_ITM_STIM25_STIM25_W 32 +#define CPU_ITM_STIM25_STIM25_M 0xFFFFFFFF +#define CPU_ITM_STIM25_STIM25_S 0 //***************************************************************************** // @@ -609,9 +609,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM26_STIM26_W 32 -#define CPU_ITM_STIM26_STIM26_M 0xFFFFFFFF -#define CPU_ITM_STIM26_STIM26_S 0 +#define CPU_ITM_STIM26_STIM26_W 32 +#define CPU_ITM_STIM26_STIM26_M 0xFFFFFFFF +#define CPU_ITM_STIM26_STIM26_S 0 //***************************************************************************** // @@ -626,9 +626,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM27_STIM27_W 32 -#define CPU_ITM_STIM27_STIM27_M 0xFFFFFFFF -#define CPU_ITM_STIM27_STIM27_S 0 +#define CPU_ITM_STIM27_STIM27_W 32 +#define CPU_ITM_STIM27_STIM27_M 0xFFFFFFFF +#define CPU_ITM_STIM27_STIM27_S 0 //***************************************************************************** // @@ -643,9 +643,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM28_STIM28_W 32 -#define CPU_ITM_STIM28_STIM28_M 0xFFFFFFFF -#define CPU_ITM_STIM28_STIM28_S 0 +#define CPU_ITM_STIM28_STIM28_W 32 +#define CPU_ITM_STIM28_STIM28_M 0xFFFFFFFF +#define CPU_ITM_STIM28_STIM28_S 0 //***************************************************************************** // @@ -660,9 +660,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM29_STIM29_W 32 -#define CPU_ITM_STIM29_STIM29_M 0xFFFFFFFF -#define CPU_ITM_STIM29_STIM29_S 0 +#define CPU_ITM_STIM29_STIM29_W 32 +#define CPU_ITM_STIM29_STIM29_M 0xFFFFFFFF +#define CPU_ITM_STIM29_STIM29_S 0 //***************************************************************************** // @@ -677,9 +677,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM30_STIM30_W 32 -#define CPU_ITM_STIM30_STIM30_M 0xFFFFFFFF -#define CPU_ITM_STIM30_STIM30_S 0 +#define CPU_ITM_STIM30_STIM30_W 32 +#define CPU_ITM_STIM30_STIM30_M 0xFFFFFFFF +#define CPU_ITM_STIM30_STIM30_S 0 //***************************************************************************** // @@ -694,9 +694,9 @@ // provide an atomic read-modify-write, so it's users responsibility to ensure // exclusive read-modify-write if this ITM port is used concurrently by // interrupts or other threads. -#define CPU_ITM_STIM31_STIM31_W 32 -#define CPU_ITM_STIM31_STIM31_M 0xFFFFFFFF -#define CPU_ITM_STIM31_STIM31_S 0 +#define CPU_ITM_STIM31_STIM31_W 32 +#define CPU_ITM_STIM31_STIM31_M 0xFFFFFFFF +#define CPU_ITM_STIM31_STIM31_S 0 //***************************************************************************** // @@ -706,258 +706,258 @@ // Field: [31] STIMENA31 // // Bit mask to enable tracing on ITM stimulus port 31. -#define CPU_ITM_TER_STIMENA31 0x80000000 -#define CPU_ITM_TER_STIMENA31_BITN 31 -#define CPU_ITM_TER_STIMENA31_M 0x80000000 -#define CPU_ITM_TER_STIMENA31_S 31 +#define CPU_ITM_TER_STIMENA31 0x80000000 +#define CPU_ITM_TER_STIMENA31_BITN 31 +#define CPU_ITM_TER_STIMENA31_M 0x80000000 +#define CPU_ITM_TER_STIMENA31_S 31 // Field: [30] STIMENA30 // // Bit mask to enable tracing on ITM stimulus port 30. -#define CPU_ITM_TER_STIMENA30 0x40000000 -#define CPU_ITM_TER_STIMENA30_BITN 30 -#define CPU_ITM_TER_STIMENA30_M 0x40000000 -#define CPU_ITM_TER_STIMENA30_S 30 +#define CPU_ITM_TER_STIMENA30 0x40000000 +#define CPU_ITM_TER_STIMENA30_BITN 30 +#define CPU_ITM_TER_STIMENA30_M 0x40000000 +#define CPU_ITM_TER_STIMENA30_S 30 // Field: [29] STIMENA29 // // Bit mask to enable tracing on ITM stimulus port 29. -#define CPU_ITM_TER_STIMENA29 0x20000000 -#define CPU_ITM_TER_STIMENA29_BITN 29 -#define CPU_ITM_TER_STIMENA29_M 0x20000000 -#define CPU_ITM_TER_STIMENA29_S 29 +#define CPU_ITM_TER_STIMENA29 0x20000000 +#define CPU_ITM_TER_STIMENA29_BITN 29 +#define CPU_ITM_TER_STIMENA29_M 0x20000000 +#define CPU_ITM_TER_STIMENA29_S 29 // Field: [28] STIMENA28 // // Bit mask to enable tracing on ITM stimulus port 28. -#define CPU_ITM_TER_STIMENA28 0x10000000 -#define CPU_ITM_TER_STIMENA28_BITN 28 -#define CPU_ITM_TER_STIMENA28_M 0x10000000 -#define CPU_ITM_TER_STIMENA28_S 28 +#define CPU_ITM_TER_STIMENA28 0x10000000 +#define CPU_ITM_TER_STIMENA28_BITN 28 +#define CPU_ITM_TER_STIMENA28_M 0x10000000 +#define CPU_ITM_TER_STIMENA28_S 28 // Field: [27] STIMENA27 // // Bit mask to enable tracing on ITM stimulus port 27. -#define CPU_ITM_TER_STIMENA27 0x08000000 -#define CPU_ITM_TER_STIMENA27_BITN 27 -#define CPU_ITM_TER_STIMENA27_M 0x08000000 -#define CPU_ITM_TER_STIMENA27_S 27 +#define CPU_ITM_TER_STIMENA27 0x08000000 +#define CPU_ITM_TER_STIMENA27_BITN 27 +#define CPU_ITM_TER_STIMENA27_M 0x08000000 +#define CPU_ITM_TER_STIMENA27_S 27 // Field: [26] STIMENA26 // // Bit mask to enable tracing on ITM stimulus port 26. -#define CPU_ITM_TER_STIMENA26 0x04000000 -#define CPU_ITM_TER_STIMENA26_BITN 26 -#define CPU_ITM_TER_STIMENA26_M 0x04000000 -#define CPU_ITM_TER_STIMENA26_S 26 +#define CPU_ITM_TER_STIMENA26 0x04000000 +#define CPU_ITM_TER_STIMENA26_BITN 26 +#define CPU_ITM_TER_STIMENA26_M 0x04000000 +#define CPU_ITM_TER_STIMENA26_S 26 // Field: [25] STIMENA25 // // Bit mask to enable tracing on ITM stimulus port 25. -#define CPU_ITM_TER_STIMENA25 0x02000000 -#define CPU_ITM_TER_STIMENA25_BITN 25 -#define CPU_ITM_TER_STIMENA25_M 0x02000000 -#define CPU_ITM_TER_STIMENA25_S 25 +#define CPU_ITM_TER_STIMENA25 0x02000000 +#define CPU_ITM_TER_STIMENA25_BITN 25 +#define CPU_ITM_TER_STIMENA25_M 0x02000000 +#define CPU_ITM_TER_STIMENA25_S 25 // Field: [24] STIMENA24 // // Bit mask to enable tracing on ITM stimulus port 24. -#define CPU_ITM_TER_STIMENA24 0x01000000 -#define CPU_ITM_TER_STIMENA24_BITN 24 -#define CPU_ITM_TER_STIMENA24_M 0x01000000 -#define CPU_ITM_TER_STIMENA24_S 24 +#define CPU_ITM_TER_STIMENA24 0x01000000 +#define CPU_ITM_TER_STIMENA24_BITN 24 +#define CPU_ITM_TER_STIMENA24_M 0x01000000 +#define CPU_ITM_TER_STIMENA24_S 24 // Field: [23] STIMENA23 // // Bit mask to enable tracing on ITM stimulus port 23. -#define CPU_ITM_TER_STIMENA23 0x00800000 -#define CPU_ITM_TER_STIMENA23_BITN 23 -#define CPU_ITM_TER_STIMENA23_M 0x00800000 -#define CPU_ITM_TER_STIMENA23_S 23 +#define CPU_ITM_TER_STIMENA23 0x00800000 +#define CPU_ITM_TER_STIMENA23_BITN 23 +#define CPU_ITM_TER_STIMENA23_M 0x00800000 +#define CPU_ITM_TER_STIMENA23_S 23 // Field: [22] STIMENA22 // // Bit mask to enable tracing on ITM stimulus port 22. -#define CPU_ITM_TER_STIMENA22 0x00400000 -#define CPU_ITM_TER_STIMENA22_BITN 22 -#define CPU_ITM_TER_STIMENA22_M 0x00400000 -#define CPU_ITM_TER_STIMENA22_S 22 +#define CPU_ITM_TER_STIMENA22 0x00400000 +#define CPU_ITM_TER_STIMENA22_BITN 22 +#define CPU_ITM_TER_STIMENA22_M 0x00400000 +#define CPU_ITM_TER_STIMENA22_S 22 // Field: [21] STIMENA21 // // Bit mask to enable tracing on ITM stimulus port 21. -#define CPU_ITM_TER_STIMENA21 0x00200000 -#define CPU_ITM_TER_STIMENA21_BITN 21 -#define CPU_ITM_TER_STIMENA21_M 0x00200000 -#define CPU_ITM_TER_STIMENA21_S 21 +#define CPU_ITM_TER_STIMENA21 0x00200000 +#define CPU_ITM_TER_STIMENA21_BITN 21 +#define CPU_ITM_TER_STIMENA21_M 0x00200000 +#define CPU_ITM_TER_STIMENA21_S 21 // Field: [20] STIMENA20 // // Bit mask to enable tracing on ITM stimulus port 20. -#define CPU_ITM_TER_STIMENA20 0x00100000 -#define CPU_ITM_TER_STIMENA20_BITN 20 -#define CPU_ITM_TER_STIMENA20_M 0x00100000 -#define CPU_ITM_TER_STIMENA20_S 20 +#define CPU_ITM_TER_STIMENA20 0x00100000 +#define CPU_ITM_TER_STIMENA20_BITN 20 +#define CPU_ITM_TER_STIMENA20_M 0x00100000 +#define CPU_ITM_TER_STIMENA20_S 20 // Field: [19] STIMENA19 // // Bit mask to enable tracing on ITM stimulus port 19. -#define CPU_ITM_TER_STIMENA19 0x00080000 -#define CPU_ITM_TER_STIMENA19_BITN 19 -#define CPU_ITM_TER_STIMENA19_M 0x00080000 -#define CPU_ITM_TER_STIMENA19_S 19 +#define CPU_ITM_TER_STIMENA19 0x00080000 +#define CPU_ITM_TER_STIMENA19_BITN 19 +#define CPU_ITM_TER_STIMENA19_M 0x00080000 +#define CPU_ITM_TER_STIMENA19_S 19 // Field: [18] STIMENA18 // // Bit mask to enable tracing on ITM stimulus port 18. -#define CPU_ITM_TER_STIMENA18 0x00040000 -#define CPU_ITM_TER_STIMENA18_BITN 18 -#define CPU_ITM_TER_STIMENA18_M 0x00040000 -#define CPU_ITM_TER_STIMENA18_S 18 +#define CPU_ITM_TER_STIMENA18 0x00040000 +#define CPU_ITM_TER_STIMENA18_BITN 18 +#define CPU_ITM_TER_STIMENA18_M 0x00040000 +#define CPU_ITM_TER_STIMENA18_S 18 // Field: [17] STIMENA17 // // Bit mask to enable tracing on ITM stimulus port 17. -#define CPU_ITM_TER_STIMENA17 0x00020000 -#define CPU_ITM_TER_STIMENA17_BITN 17 -#define CPU_ITM_TER_STIMENA17_M 0x00020000 -#define CPU_ITM_TER_STIMENA17_S 17 +#define CPU_ITM_TER_STIMENA17 0x00020000 +#define CPU_ITM_TER_STIMENA17_BITN 17 +#define CPU_ITM_TER_STIMENA17_M 0x00020000 +#define CPU_ITM_TER_STIMENA17_S 17 // Field: [16] STIMENA16 // // Bit mask to enable tracing on ITM stimulus port 16. -#define CPU_ITM_TER_STIMENA16 0x00010000 -#define CPU_ITM_TER_STIMENA16_BITN 16 -#define CPU_ITM_TER_STIMENA16_M 0x00010000 -#define CPU_ITM_TER_STIMENA16_S 16 +#define CPU_ITM_TER_STIMENA16 0x00010000 +#define CPU_ITM_TER_STIMENA16_BITN 16 +#define CPU_ITM_TER_STIMENA16_M 0x00010000 +#define CPU_ITM_TER_STIMENA16_S 16 // Field: [15] STIMENA15 // // Bit mask to enable tracing on ITM stimulus port 15. -#define CPU_ITM_TER_STIMENA15 0x00008000 -#define CPU_ITM_TER_STIMENA15_BITN 15 -#define CPU_ITM_TER_STIMENA15_M 0x00008000 -#define CPU_ITM_TER_STIMENA15_S 15 +#define CPU_ITM_TER_STIMENA15 0x00008000 +#define CPU_ITM_TER_STIMENA15_BITN 15 +#define CPU_ITM_TER_STIMENA15_M 0x00008000 +#define CPU_ITM_TER_STIMENA15_S 15 // Field: [14] STIMENA14 // // Bit mask to enable tracing on ITM stimulus port 14. -#define CPU_ITM_TER_STIMENA14 0x00004000 -#define CPU_ITM_TER_STIMENA14_BITN 14 -#define CPU_ITM_TER_STIMENA14_M 0x00004000 -#define CPU_ITM_TER_STIMENA14_S 14 +#define CPU_ITM_TER_STIMENA14 0x00004000 +#define CPU_ITM_TER_STIMENA14_BITN 14 +#define CPU_ITM_TER_STIMENA14_M 0x00004000 +#define CPU_ITM_TER_STIMENA14_S 14 // Field: [13] STIMENA13 // // Bit mask to enable tracing on ITM stimulus port 13. -#define CPU_ITM_TER_STIMENA13 0x00002000 -#define CPU_ITM_TER_STIMENA13_BITN 13 -#define CPU_ITM_TER_STIMENA13_M 0x00002000 -#define CPU_ITM_TER_STIMENA13_S 13 +#define CPU_ITM_TER_STIMENA13 0x00002000 +#define CPU_ITM_TER_STIMENA13_BITN 13 +#define CPU_ITM_TER_STIMENA13_M 0x00002000 +#define CPU_ITM_TER_STIMENA13_S 13 // Field: [12] STIMENA12 // // Bit mask to enable tracing on ITM stimulus port 12. -#define CPU_ITM_TER_STIMENA12 0x00001000 -#define CPU_ITM_TER_STIMENA12_BITN 12 -#define CPU_ITM_TER_STIMENA12_M 0x00001000 -#define CPU_ITM_TER_STIMENA12_S 12 +#define CPU_ITM_TER_STIMENA12 0x00001000 +#define CPU_ITM_TER_STIMENA12_BITN 12 +#define CPU_ITM_TER_STIMENA12_M 0x00001000 +#define CPU_ITM_TER_STIMENA12_S 12 // Field: [11] STIMENA11 // // Bit mask to enable tracing on ITM stimulus port 11. -#define CPU_ITM_TER_STIMENA11 0x00000800 -#define CPU_ITM_TER_STIMENA11_BITN 11 -#define CPU_ITM_TER_STIMENA11_M 0x00000800 -#define CPU_ITM_TER_STIMENA11_S 11 +#define CPU_ITM_TER_STIMENA11 0x00000800 +#define CPU_ITM_TER_STIMENA11_BITN 11 +#define CPU_ITM_TER_STIMENA11_M 0x00000800 +#define CPU_ITM_TER_STIMENA11_S 11 // Field: [10] STIMENA10 // // Bit mask to enable tracing on ITM stimulus port 10. -#define CPU_ITM_TER_STIMENA10 0x00000400 -#define CPU_ITM_TER_STIMENA10_BITN 10 -#define CPU_ITM_TER_STIMENA10_M 0x00000400 -#define CPU_ITM_TER_STIMENA10_S 10 +#define CPU_ITM_TER_STIMENA10 0x00000400 +#define CPU_ITM_TER_STIMENA10_BITN 10 +#define CPU_ITM_TER_STIMENA10_M 0x00000400 +#define CPU_ITM_TER_STIMENA10_S 10 // Field: [9] STIMENA9 // // Bit mask to enable tracing on ITM stimulus port 9. -#define CPU_ITM_TER_STIMENA9 0x00000200 -#define CPU_ITM_TER_STIMENA9_BITN 9 -#define CPU_ITM_TER_STIMENA9_M 0x00000200 -#define CPU_ITM_TER_STIMENA9_S 9 +#define CPU_ITM_TER_STIMENA9 0x00000200 +#define CPU_ITM_TER_STIMENA9_BITN 9 +#define CPU_ITM_TER_STIMENA9_M 0x00000200 +#define CPU_ITM_TER_STIMENA9_S 9 // Field: [8] STIMENA8 // // Bit mask to enable tracing on ITM stimulus port 8. -#define CPU_ITM_TER_STIMENA8 0x00000100 -#define CPU_ITM_TER_STIMENA8_BITN 8 -#define CPU_ITM_TER_STIMENA8_M 0x00000100 -#define CPU_ITM_TER_STIMENA8_S 8 +#define CPU_ITM_TER_STIMENA8 0x00000100 +#define CPU_ITM_TER_STIMENA8_BITN 8 +#define CPU_ITM_TER_STIMENA8_M 0x00000100 +#define CPU_ITM_TER_STIMENA8_S 8 // Field: [7] STIMENA7 // // Bit mask to enable tracing on ITM stimulus port 7. -#define CPU_ITM_TER_STIMENA7 0x00000080 -#define CPU_ITM_TER_STIMENA7_BITN 7 -#define CPU_ITM_TER_STIMENA7_M 0x00000080 -#define CPU_ITM_TER_STIMENA7_S 7 +#define CPU_ITM_TER_STIMENA7 0x00000080 +#define CPU_ITM_TER_STIMENA7_BITN 7 +#define CPU_ITM_TER_STIMENA7_M 0x00000080 +#define CPU_ITM_TER_STIMENA7_S 7 // Field: [6] STIMENA6 // // Bit mask to enable tracing on ITM stimulus port 6. -#define CPU_ITM_TER_STIMENA6 0x00000040 -#define CPU_ITM_TER_STIMENA6_BITN 6 -#define CPU_ITM_TER_STIMENA6_M 0x00000040 -#define CPU_ITM_TER_STIMENA6_S 6 +#define CPU_ITM_TER_STIMENA6 0x00000040 +#define CPU_ITM_TER_STIMENA6_BITN 6 +#define CPU_ITM_TER_STIMENA6_M 0x00000040 +#define CPU_ITM_TER_STIMENA6_S 6 // Field: [5] STIMENA5 // // Bit mask to enable tracing on ITM stimulus port 5. -#define CPU_ITM_TER_STIMENA5 0x00000020 -#define CPU_ITM_TER_STIMENA5_BITN 5 -#define CPU_ITM_TER_STIMENA5_M 0x00000020 -#define CPU_ITM_TER_STIMENA5_S 5 +#define CPU_ITM_TER_STIMENA5 0x00000020 +#define CPU_ITM_TER_STIMENA5_BITN 5 +#define CPU_ITM_TER_STIMENA5_M 0x00000020 +#define CPU_ITM_TER_STIMENA5_S 5 // Field: [4] STIMENA4 // // Bit mask to enable tracing on ITM stimulus port 4. -#define CPU_ITM_TER_STIMENA4 0x00000010 -#define CPU_ITM_TER_STIMENA4_BITN 4 -#define CPU_ITM_TER_STIMENA4_M 0x00000010 -#define CPU_ITM_TER_STIMENA4_S 4 +#define CPU_ITM_TER_STIMENA4 0x00000010 +#define CPU_ITM_TER_STIMENA4_BITN 4 +#define CPU_ITM_TER_STIMENA4_M 0x00000010 +#define CPU_ITM_TER_STIMENA4_S 4 // Field: [3] STIMENA3 // // Bit mask to enable tracing on ITM stimulus port 3. -#define CPU_ITM_TER_STIMENA3 0x00000008 -#define CPU_ITM_TER_STIMENA3_BITN 3 -#define CPU_ITM_TER_STIMENA3_M 0x00000008 -#define CPU_ITM_TER_STIMENA3_S 3 +#define CPU_ITM_TER_STIMENA3 0x00000008 +#define CPU_ITM_TER_STIMENA3_BITN 3 +#define CPU_ITM_TER_STIMENA3_M 0x00000008 +#define CPU_ITM_TER_STIMENA3_S 3 // Field: [2] STIMENA2 // // Bit mask to enable tracing on ITM stimulus port 2. -#define CPU_ITM_TER_STIMENA2 0x00000004 -#define CPU_ITM_TER_STIMENA2_BITN 2 -#define CPU_ITM_TER_STIMENA2_M 0x00000004 -#define CPU_ITM_TER_STIMENA2_S 2 +#define CPU_ITM_TER_STIMENA2 0x00000004 +#define CPU_ITM_TER_STIMENA2_BITN 2 +#define CPU_ITM_TER_STIMENA2_M 0x00000004 +#define CPU_ITM_TER_STIMENA2_S 2 // Field: [1] STIMENA1 // // Bit mask to enable tracing on ITM stimulus port 1. -#define CPU_ITM_TER_STIMENA1 0x00000002 -#define CPU_ITM_TER_STIMENA1_BITN 1 -#define CPU_ITM_TER_STIMENA1_M 0x00000002 -#define CPU_ITM_TER_STIMENA1_S 1 +#define CPU_ITM_TER_STIMENA1 0x00000002 +#define CPU_ITM_TER_STIMENA1_BITN 1 +#define CPU_ITM_TER_STIMENA1_M 0x00000002 +#define CPU_ITM_TER_STIMENA1_S 1 // Field: [0] STIMENA0 // // Bit mask to enable tracing on ITM stimulus port 0. -#define CPU_ITM_TER_STIMENA0 0x00000001 -#define CPU_ITM_TER_STIMENA0_BITN 0 -#define CPU_ITM_TER_STIMENA0_M 0x00000001 -#define CPU_ITM_TER_STIMENA0_S 0 +#define CPU_ITM_TER_STIMENA0 0x00000001 +#define CPU_ITM_TER_STIMENA0_BITN 0 +#define CPU_ITM_TER_STIMENA0_M 0x00000001 +#define CPU_ITM_TER_STIMENA0_S 0 //***************************************************************************** // @@ -975,9 +975,9 @@ // // 0: User access allowed to stimulus ports // 1: Privileged access only to stimulus ports -#define CPU_ITM_TPR_PRIVMASK_W 4 -#define CPU_ITM_TPR_PRIVMASK_M 0x0000000F -#define CPU_ITM_TPR_PRIVMASK_S 0 +#define CPU_ITM_TPR_PRIVMASK_W 4 +#define CPU_ITM_TPR_PRIVMASK_M 0x0000000F +#define CPU_ITM_TPR_PRIVMASK_S 0 //***************************************************************************** // @@ -987,19 +987,19 @@ // Field: [23] BUSY // // Set when ITM events present and being drained. -#define CPU_ITM_TCR_BUSY 0x00800000 -#define CPU_ITM_TCR_BUSY_BITN 23 -#define CPU_ITM_TCR_BUSY_M 0x00800000 -#define CPU_ITM_TCR_BUSY_S 23 +#define CPU_ITM_TCR_BUSY 0x00800000 +#define CPU_ITM_TCR_BUSY_BITN 23 +#define CPU_ITM_TCR_BUSY_M 0x00800000 +#define CPU_ITM_TCR_BUSY_S 23 // Field: [22:16] ATBID // // Trace Bus ID for CoreSight system. Optional identifier for multi-source // trace stream formatting. If multi-source trace is in use, this field must be // written with a non-zero value. -#define CPU_ITM_TCR_ATBID_W 7 -#define CPU_ITM_TCR_ATBID_M 0x007F0000 -#define CPU_ITM_TCR_ATBID_S 16 +#define CPU_ITM_TCR_ATBID_W 7 +#define CPU_ITM_TCR_ATBID_M 0x007F0000 +#define CPU_ITM_TCR_ATBID_S 16 // Field: [9:8] TSPRESCALE // @@ -1009,13 +1009,13 @@ // DIV16 Divide by 16 // DIV4 Divide by 4 // NOPRESCALING No prescaling -#define CPU_ITM_TCR_TSPRESCALE_W 2 -#define CPU_ITM_TCR_TSPRESCALE_M 0x00000300 -#define CPU_ITM_TCR_TSPRESCALE_S 8 -#define CPU_ITM_TCR_TSPRESCALE_DIV64 0x00000300 -#define CPU_ITM_TCR_TSPRESCALE_DIV16 0x00000200 -#define CPU_ITM_TCR_TSPRESCALE_DIV4 0x00000100 -#define CPU_ITM_TCR_TSPRESCALE_NOPRESCALING 0x00000000 +#define CPU_ITM_TCR_TSPRESCALE_W 2 +#define CPU_ITM_TCR_TSPRESCALE_M 0x00000300 +#define CPU_ITM_TCR_TSPRESCALE_S 8 +#define CPU_ITM_TCR_TSPRESCALE_DIV64 0x00000300 +#define CPU_ITM_TCR_TSPRESCALE_DIV16 0x00000200 +#define CPU_ITM_TCR_TSPRESCALE_DIV4 0x00000100 +#define CPU_ITM_TCR_TSPRESCALE_NOPRESCALING 0x00000000 // Field: [4] SWOENA // @@ -1028,29 +1028,29 @@ // 0x1: Timestamp counter uses lineout (data related) clock from TPIU // interface. The timestamp counter is held in reset while the output line is // idle. -#define CPU_ITM_TCR_SWOENA 0x00000010 -#define CPU_ITM_TCR_SWOENA_BITN 4 -#define CPU_ITM_TCR_SWOENA_M 0x00000010 -#define CPU_ITM_TCR_SWOENA_S 4 +#define CPU_ITM_TCR_SWOENA 0x00000010 +#define CPU_ITM_TCR_SWOENA_BITN 4 +#define CPU_ITM_TCR_SWOENA_M 0x00000010 +#define CPU_ITM_TCR_SWOENA_S 4 // Field: [3] DWTENA // // Enables the DWT stimulus (hardware event packet emission to the TPIU from // the DWT) -#define CPU_ITM_TCR_DWTENA 0x00000008 -#define CPU_ITM_TCR_DWTENA_BITN 3 -#define CPU_ITM_TCR_DWTENA_M 0x00000008 -#define CPU_ITM_TCR_DWTENA_S 3 +#define CPU_ITM_TCR_DWTENA 0x00000008 +#define CPU_ITM_TCR_DWTENA_BITN 3 +#define CPU_ITM_TCR_DWTENA_M 0x00000008 +#define CPU_ITM_TCR_DWTENA_S 3 // Field: [2] SYNCENA // // Enables synchronization packet transmission for a synchronous TPIU. // CPU_DWT:CTRL.SYNCTAP must be configured for the correct synchronization // speed. -#define CPU_ITM_TCR_SYNCENA 0x00000004 -#define CPU_ITM_TCR_SYNCENA_BITN 2 -#define CPU_ITM_TCR_SYNCENA_M 0x00000004 -#define CPU_ITM_TCR_SYNCENA_S 2 +#define CPU_ITM_TCR_SYNCENA 0x00000004 +#define CPU_ITM_TCR_SYNCENA_BITN 2 +#define CPU_ITM_TCR_SYNCENA_M 0x00000004 +#define CPU_ITM_TCR_SYNCENA_S 2 // Field: [1] TSENA // @@ -1061,19 +1061,19 @@ // for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps // are triggered by activity on the internal trace bus only. In this case there // is no regular timestamp output when the ITM is idle. -#define CPU_ITM_TCR_TSENA 0x00000002 -#define CPU_ITM_TCR_TSENA_BITN 1 -#define CPU_ITM_TCR_TSENA_M 0x00000002 -#define CPU_ITM_TCR_TSENA_S 1 +#define CPU_ITM_TCR_TSENA 0x00000002 +#define CPU_ITM_TCR_TSENA_BITN 1 +#define CPU_ITM_TCR_TSENA_M 0x00000002 +#define CPU_ITM_TCR_TSENA_S 1 // Field: [0] ITMENA // // Enables ITM. This is the master enable, and must be set before ITM Stimulus // and Trace Enable registers can be written. -#define CPU_ITM_TCR_ITMENA 0x00000001 -#define CPU_ITM_TCR_ITMENA_BITN 0 -#define CPU_ITM_TCR_ITMENA_M 0x00000001 -#define CPU_ITM_TCR_ITMENA_S 0 +#define CPU_ITM_TCR_ITMENA 0x00000001 +#define CPU_ITM_TCR_ITMENA_BITN 0 +#define CPU_ITM_TCR_ITMENA_M 0x00000001 +#define CPU_ITM_TCR_ITMENA_S 0 //***************************************************************************** // @@ -1084,9 +1084,9 @@ // // A privileged write of 0xC5ACCE55 enables more write access to Control // Registers TER, TPR and TCR. An invalid write removes write access. -#define CPU_ITM_LAR_LOCK_ACCESS_W 32 -#define CPU_ITM_LAR_LOCK_ACCESS_M 0xFFFFFFFF -#define CPU_ITM_LAR_LOCK_ACCESS_S 0 +#define CPU_ITM_LAR_LOCK_ACCESS_W 32 +#define CPU_ITM_LAR_LOCK_ACCESS_M 0xFFFFFFFF +#define CPU_ITM_LAR_LOCK_ACCESS_S 0 //***************************************************************************** // @@ -1096,27 +1096,26 @@ // Field: [2] BYTEACC // // Reads 0 which means 8-bit lock access is not be implemented. -#define CPU_ITM_LSR_BYTEACC 0x00000004 -#define CPU_ITM_LSR_BYTEACC_BITN 2 -#define CPU_ITM_LSR_BYTEACC_M 0x00000004 -#define CPU_ITM_LSR_BYTEACC_S 2 +#define CPU_ITM_LSR_BYTEACC 0x00000004 +#define CPU_ITM_LSR_BYTEACC_BITN 2 +#define CPU_ITM_LSR_BYTEACC_M 0x00000004 +#define CPU_ITM_LSR_BYTEACC_S 2 // Field: [1] ACCESS // // Write access to component is blocked. All writes are ignored, reads are // permitted. -#define CPU_ITM_LSR_ACCESS 0x00000002 -#define CPU_ITM_LSR_ACCESS_BITN 1 -#define CPU_ITM_LSR_ACCESS_M 0x00000002 -#define CPU_ITM_LSR_ACCESS_S 1 +#define CPU_ITM_LSR_ACCESS 0x00000002 +#define CPU_ITM_LSR_ACCESS_BITN 1 +#define CPU_ITM_LSR_ACCESS_M 0x00000002 +#define CPU_ITM_LSR_ACCESS_S 1 // Field: [0] PRESENT // // Indicates that a lock mechanism exists for this component. -#define CPU_ITM_LSR_PRESENT 0x00000001 -#define CPU_ITM_LSR_PRESENT_BITN 0 -#define CPU_ITM_LSR_PRESENT_M 0x00000001 -#define CPU_ITM_LSR_PRESENT_S 0 - +#define CPU_ITM_LSR_PRESENT 0x00000001 +#define CPU_ITM_LSR_PRESENT_BITN 0 +#define CPU_ITM_LSR_PRESENT_M 0x00000001 +#define CPU_ITM_LSR_PRESENT_S 0 #endif // __CPU_ITM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_rom_table.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_rom_table.h index 43c9a9f..25fef6f 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_rom_table.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_rom_table.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_cpu_rom_table_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_cpu_rom_table_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CPU_ROM_TABLE_H__ #define __HW_CPU_ROM_TABLE_H__ @@ -44,28 +44,28 @@ // //***************************************************************************** // System Control Space Component -#define CPU_ROM_TABLE_O_SCS 0x00000000 +#define CPU_ROM_TABLE_O_SCS 0x00000000 // Data Watchpoint and Trace Component -#define CPU_ROM_TABLE_O_DWT 0x00000004 +#define CPU_ROM_TABLE_O_DWT 0x00000004 // Flash Patch and Breakpoint Component -#define CPU_ROM_TABLE_O_FPB 0x00000008 +#define CPU_ROM_TABLE_O_FPB 0x00000008 // Instrumentation Trace Component -#define CPU_ROM_TABLE_O_ITM 0x0000000C +#define CPU_ROM_TABLE_O_ITM 0x0000000C // Trace Port Interface Component -#define CPU_ROM_TABLE_O_TPIU 0x00000010 +#define CPU_ROM_TABLE_O_TPIU 0x00000010 // Enhanced Trace Component -#define CPU_ROM_TABLE_O_ETM 0x00000014 +#define CPU_ROM_TABLE_O_ETM 0x00000014 // End Marker -#define CPU_ROM_TABLE_O_END 0x00000018 +#define CPU_ROM_TABLE_O_END 0x00000018 // System Memory Map Access for DAP -#define CPU_ROM_TABLE_O_SYSTEM_ACCESS 0x00000FCC +#define CPU_ROM_TABLE_O_SYSTEM_ACCESS 0x00000FCC //***************************************************************************** // @@ -76,9 +76,9 @@ // // Points to the SCS at 0xE000E000. // (SCS + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE000E000. -#define CPU_ROM_TABLE_SCS_SCS_W 32 -#define CPU_ROM_TABLE_SCS_SCS_M 0xFFFFFFFF -#define CPU_ROM_TABLE_SCS_SCS_S 0 +#define CPU_ROM_TABLE_SCS_SCS_W 32 +#define CPU_ROM_TABLE_SCS_SCS_M 0xFFFFFFFF +#define CPU_ROM_TABLE_SCS_SCS_S 0 //***************************************************************************** // @@ -89,18 +89,18 @@ // // Points to the Data Watchpoint and Trace block at 0xE0001000. // (2*DWT + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0001000. -#define CPU_ROM_TABLE_DWT_DWT_W 31 -#define CPU_ROM_TABLE_DWT_DWT_M 0xFFFFFFFE -#define CPU_ROM_TABLE_DWT_DWT_S 1 +#define CPU_ROM_TABLE_DWT_DWT_W 31 +#define CPU_ROM_TABLE_DWT_DWT_M 0xFFFFFFFE +#define CPU_ROM_TABLE_DWT_DWT_S 1 // Field: [0] DWT_PRESENT // // 0: DWT is not present // 1: DWT is present. -#define CPU_ROM_TABLE_DWT_DWT_PRESENT 0x00000001 -#define CPU_ROM_TABLE_DWT_DWT_PRESENT_BITN 0 -#define CPU_ROM_TABLE_DWT_DWT_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_DWT_DWT_PRESENT_S 0 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT 0x00000001 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_BITN 0 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_DWT_DWT_PRESENT_S 0 //***************************************************************************** // @@ -111,18 +111,18 @@ // // Points to the Flash Patch and Breakpoint block at 0xE0002000. // (2*FPB + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0002000. -#define CPU_ROM_TABLE_FPB_FPB_W 31 -#define CPU_ROM_TABLE_FPB_FPB_M 0xFFFFFFFE -#define CPU_ROM_TABLE_FPB_FPB_S 1 +#define CPU_ROM_TABLE_FPB_FPB_W 31 +#define CPU_ROM_TABLE_FPB_FPB_M 0xFFFFFFFE +#define CPU_ROM_TABLE_FPB_FPB_S 1 // Field: [0] FPB_PRESENT // // 0: FPB is not present // 1: FPB is present. -#define CPU_ROM_TABLE_FPB_FPB_PRESENT 0x00000001 -#define CPU_ROM_TABLE_FPB_FPB_PRESENT_BITN 0 -#define CPU_ROM_TABLE_FPB_FPB_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_FPB_FPB_PRESENT_S 0 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT 0x00000001 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_BITN 0 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_FPB_FPB_PRESENT_S 0 //***************************************************************************** // @@ -133,18 +133,18 @@ // // Points to the Instrumentation Trace block at 0xE0000000. // (2*ITM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0000000. -#define CPU_ROM_TABLE_ITM_ITM_W 31 -#define CPU_ROM_TABLE_ITM_ITM_M 0xFFFFFFFE -#define CPU_ROM_TABLE_ITM_ITM_S 1 +#define CPU_ROM_TABLE_ITM_ITM_W 31 +#define CPU_ROM_TABLE_ITM_ITM_M 0xFFFFFFFE +#define CPU_ROM_TABLE_ITM_ITM_S 1 // Field: [0] ITM_PRESENT // // 0: ITM is not present // 1: ITM is present. -#define CPU_ROM_TABLE_ITM_ITM_PRESENT 0x00000001 -#define CPU_ROM_TABLE_ITM_ITM_PRESENT_BITN 0 -#define CPU_ROM_TABLE_ITM_ITM_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_ITM_ITM_PRESENT_S 0 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT 0x00000001 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_BITN 0 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_ITM_ITM_PRESENT_S 0 //***************************************************************************** // @@ -155,18 +155,18 @@ // // Points to the TPIU. TPIU is at 0xE0040000. // (2*TPIU + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0040000. -#define CPU_ROM_TABLE_TPIU_TPIU_W 31 -#define CPU_ROM_TABLE_TPIU_TPIU_M 0xFFFFFFFE -#define CPU_ROM_TABLE_TPIU_TPIU_S 1 +#define CPU_ROM_TABLE_TPIU_TPIU_W 31 +#define CPU_ROM_TABLE_TPIU_TPIU_M 0xFFFFFFFE +#define CPU_ROM_TABLE_TPIU_TPIU_S 1 // Field: [0] TPIU_PRESENT // // 0: TPIU is not present // 1: TPIU is present. -#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT 0x00000001 -#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_BITN 0 -#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_S 0 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT 0x00000001 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_BITN 0 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_S 0 //***************************************************************************** // @@ -177,18 +177,18 @@ // // Points to the ETM. ETM is at 0xE0041000. // (2*ETM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0041000. -#define CPU_ROM_TABLE_ETM_ETM_W 31 -#define CPU_ROM_TABLE_ETM_ETM_M 0xFFFFFFFE -#define CPU_ROM_TABLE_ETM_ETM_S 1 +#define CPU_ROM_TABLE_ETM_ETM_W 31 +#define CPU_ROM_TABLE_ETM_ETM_M 0xFFFFFFFE +#define CPU_ROM_TABLE_ETM_ETM_S 1 // Field: [0] ETM_PRESENT // // 0: ETM is not present // 1: ETM is present. -#define CPU_ROM_TABLE_ETM_ETM_PRESENT 0x00000001 -#define CPU_ROM_TABLE_ETM_ETM_PRESENT_BITN 0 -#define CPU_ROM_TABLE_ETM_ETM_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_ETM_ETM_PRESENT_S 0 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT 0x00000001 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_BITN 0 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_M 0x00000001 +#define CPU_ROM_TABLE_ETM_ETM_PRESENT_S 0 //***************************************************************************** // @@ -198,9 +198,9 @@ // Field: [31:0] END // // End of the ROM table -#define CPU_ROM_TABLE_END_END_W 32 -#define CPU_ROM_TABLE_END_END_M 0xFFFFFFFF -#define CPU_ROM_TABLE_END_END_S 0 +#define CPU_ROM_TABLE_END_END_W 32 +#define CPU_ROM_TABLE_END_END_M 0xFFFFFFFF +#define CPU_ROM_TABLE_END_END_S 0 //***************************************************************************** // @@ -211,10 +211,9 @@ // // 1: The system memory map is accessible using the DAP // 0: Only debug resources are accessible using the DAP -#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS 0x00000001 -#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_BITN 0 -#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_M 0x00000001 -#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_S 0 - +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS 0x00000001 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_BITN 0 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_M 0x00000001 +#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_S 0 #endif // __CPU_ROM_TABLE__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_scs.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_scs.h index c7fa660..18afd7c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_scs.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_scs.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_cpu_scs_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_cpu_scs_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CPU_SCS_H__ #define __HW_CPU_SCS_H__ @@ -44,184 +44,184 @@ // //***************************************************************************** // Interrupt Control Type -#define CPU_SCS_O_ICTR 0x00000004 +#define CPU_SCS_O_ICTR 0x00000004 // Auxiliary Control -#define CPU_SCS_O_ACTLR 0x00000008 +#define CPU_SCS_O_ACTLR 0x00000008 // SysTick Control and Status -#define CPU_SCS_O_STCSR 0x00000010 +#define CPU_SCS_O_STCSR 0x00000010 // SysTick Reload Value -#define CPU_SCS_O_STRVR 0x00000014 +#define CPU_SCS_O_STRVR 0x00000014 // SysTick Current Value -#define CPU_SCS_O_STCVR 0x00000018 +#define CPU_SCS_O_STCVR 0x00000018 // SysTick Calibration Value -#define CPU_SCS_O_STCR 0x0000001C +#define CPU_SCS_O_STCR 0x0000001C // Irq 0 to 31 Set Enable -#define CPU_SCS_O_NVIC_ISER0 0x00000100 +#define CPU_SCS_O_NVIC_ISER0 0x00000100 // Irq 32 to 63 Set Enable -#define CPU_SCS_O_NVIC_ISER1 0x00000104 +#define CPU_SCS_O_NVIC_ISER1 0x00000104 // Irq 0 to 31 Clear Enable -#define CPU_SCS_O_NVIC_ICER0 0x00000180 +#define CPU_SCS_O_NVIC_ICER0 0x00000180 // Irq 32 to 63 Clear Enable -#define CPU_SCS_O_NVIC_ICER1 0x00000184 +#define CPU_SCS_O_NVIC_ICER1 0x00000184 // Irq 0 to 31 Set Pending -#define CPU_SCS_O_NVIC_ISPR0 0x00000200 +#define CPU_SCS_O_NVIC_ISPR0 0x00000200 // Irq 32 to 63 Set Pending -#define CPU_SCS_O_NVIC_ISPR1 0x00000204 +#define CPU_SCS_O_NVIC_ISPR1 0x00000204 // Irq 0 to 31 Clear Pending -#define CPU_SCS_O_NVIC_ICPR0 0x00000280 +#define CPU_SCS_O_NVIC_ICPR0 0x00000280 // Irq 32 to 63 Clear Pending -#define CPU_SCS_O_NVIC_ICPR1 0x00000284 +#define CPU_SCS_O_NVIC_ICPR1 0x00000284 // Irq 0 to 31 Active Bit -#define CPU_SCS_O_NVIC_IABR0 0x00000300 +#define CPU_SCS_O_NVIC_IABR0 0x00000300 // Irq 32 to 63 Active Bit -#define CPU_SCS_O_NVIC_IABR1 0x00000304 +#define CPU_SCS_O_NVIC_IABR1 0x00000304 // Irq 0 to 3 Priority -#define CPU_SCS_O_NVIC_IPR0 0x00000400 +#define CPU_SCS_O_NVIC_IPR0 0x00000400 // Irq 4 to 7 Priority -#define CPU_SCS_O_NVIC_IPR1 0x00000404 +#define CPU_SCS_O_NVIC_IPR1 0x00000404 // Irq 8 to 11 Priority -#define CPU_SCS_O_NVIC_IPR2 0x00000408 +#define CPU_SCS_O_NVIC_IPR2 0x00000408 // Irq 12 to 15 Priority -#define CPU_SCS_O_NVIC_IPR3 0x0000040C +#define CPU_SCS_O_NVIC_IPR3 0x0000040C // Irq 16 to 19 Priority -#define CPU_SCS_O_NVIC_IPR4 0x00000410 +#define CPU_SCS_O_NVIC_IPR4 0x00000410 // Irq 20 to 23 Priority -#define CPU_SCS_O_NVIC_IPR5 0x00000414 +#define CPU_SCS_O_NVIC_IPR5 0x00000414 // Irq 24 to 27 Priority -#define CPU_SCS_O_NVIC_IPR6 0x00000418 +#define CPU_SCS_O_NVIC_IPR6 0x00000418 // Irq 28 to 31 Priority -#define CPU_SCS_O_NVIC_IPR7 0x0000041C +#define CPU_SCS_O_NVIC_IPR7 0x0000041C // Irq 32 to 35 Priority -#define CPU_SCS_O_NVIC_IPR8 0x00000420 +#define CPU_SCS_O_NVIC_IPR8 0x00000420 // CPUID Base -#define CPU_SCS_O_CPUID 0x00000D00 +#define CPU_SCS_O_CPUID 0x00000D00 // Interrupt Control State -#define CPU_SCS_O_ICSR 0x00000D04 +#define CPU_SCS_O_ICSR 0x00000D04 // Vector Table Offset -#define CPU_SCS_O_VTOR 0x00000D08 +#define CPU_SCS_O_VTOR 0x00000D08 // Application Interrupt/Reset Control -#define CPU_SCS_O_AIRCR 0x00000D0C +#define CPU_SCS_O_AIRCR 0x00000D0C // System Control -#define CPU_SCS_O_SCR 0x00000D10 +#define CPU_SCS_O_SCR 0x00000D10 // Configuration Control -#define CPU_SCS_O_CCR 0x00000D14 +#define CPU_SCS_O_CCR 0x00000D14 // System Handlers 4-7 Priority -#define CPU_SCS_O_SHPR1 0x00000D18 +#define CPU_SCS_O_SHPR1 0x00000D18 // System Handlers 8-11 Priority -#define CPU_SCS_O_SHPR2 0x00000D1C +#define CPU_SCS_O_SHPR2 0x00000D1C // System Handlers 12-15 Priority -#define CPU_SCS_O_SHPR3 0x00000D20 +#define CPU_SCS_O_SHPR3 0x00000D20 // System Handler Control and State -#define CPU_SCS_O_SHCSR 0x00000D24 +#define CPU_SCS_O_SHCSR 0x00000D24 // Configurable Fault Status -#define CPU_SCS_O_CFSR 0x00000D28 +#define CPU_SCS_O_CFSR 0x00000D28 // Hard Fault Status -#define CPU_SCS_O_HFSR 0x00000D2C +#define CPU_SCS_O_HFSR 0x00000D2C // Debug Fault Status -#define CPU_SCS_O_DFSR 0x00000D30 +#define CPU_SCS_O_DFSR 0x00000D30 // Mem Manage Fault Address -#define CPU_SCS_O_MMFAR 0x00000D34 +#define CPU_SCS_O_MMFAR 0x00000D34 // Bus Fault Address -#define CPU_SCS_O_BFAR 0x00000D38 +#define CPU_SCS_O_BFAR 0x00000D38 // Auxiliary Fault Status -#define CPU_SCS_O_AFSR 0x00000D3C +#define CPU_SCS_O_AFSR 0x00000D3C // Processor Feature 0 -#define CPU_SCS_O_ID_PFR0 0x00000D40 +#define CPU_SCS_O_ID_PFR0 0x00000D40 // Processor Feature 1 -#define CPU_SCS_O_ID_PFR1 0x00000D44 +#define CPU_SCS_O_ID_PFR1 0x00000D44 // Debug Feature 0 -#define CPU_SCS_O_ID_DFR0 0x00000D48 +#define CPU_SCS_O_ID_DFR0 0x00000D48 // Auxiliary Feature 0 -#define CPU_SCS_O_ID_AFR0 0x00000D4C +#define CPU_SCS_O_ID_AFR0 0x00000D4C // Memory Model Feature 0 -#define CPU_SCS_O_ID_MMFR0 0x00000D50 +#define CPU_SCS_O_ID_MMFR0 0x00000D50 // Memory Model Feature 1 -#define CPU_SCS_O_ID_MMFR1 0x00000D54 +#define CPU_SCS_O_ID_MMFR1 0x00000D54 // Memory Model Feature 2 -#define CPU_SCS_O_ID_MMFR2 0x00000D58 +#define CPU_SCS_O_ID_MMFR2 0x00000D58 // Memory Model Feature 3 -#define CPU_SCS_O_ID_MMFR3 0x00000D5C +#define CPU_SCS_O_ID_MMFR3 0x00000D5C // ISA Feature 0 -#define CPU_SCS_O_ID_ISAR0 0x00000D60 +#define CPU_SCS_O_ID_ISAR0 0x00000D60 // ISA Feature 1 -#define CPU_SCS_O_ID_ISAR1 0x00000D64 +#define CPU_SCS_O_ID_ISAR1 0x00000D64 // ISA Feature 2 -#define CPU_SCS_O_ID_ISAR2 0x00000D68 +#define CPU_SCS_O_ID_ISAR2 0x00000D68 // ISA Feature 3 -#define CPU_SCS_O_ID_ISAR3 0x00000D6C +#define CPU_SCS_O_ID_ISAR3 0x00000D6C // ISA Feature 4 -#define CPU_SCS_O_ID_ISAR4 0x00000D70 +#define CPU_SCS_O_ID_ISAR4 0x00000D70 // Coprocessor Access Control -#define CPU_SCS_O_CPACR 0x00000D88 +#define CPU_SCS_O_CPACR 0x00000D88 // Debug Halting Control and Status -#define CPU_SCS_O_DHCSR 0x00000DF0 +#define CPU_SCS_O_DHCSR 0x00000DF0 // Deubg Core Register Selector -#define CPU_SCS_O_DCRSR 0x00000DF4 +#define CPU_SCS_O_DCRSR 0x00000DF4 // Debug Core Register Data -#define CPU_SCS_O_DCRDR 0x00000DF8 +#define CPU_SCS_O_DCRDR 0x00000DF8 // Debug Exception and Monitor Control -#define CPU_SCS_O_DEMCR 0x00000DFC +#define CPU_SCS_O_DEMCR 0x00000DFC // Software Trigger Interrupt -#define CPU_SCS_O_STIR 0x00000F00 +#define CPU_SCS_O_STIR 0x00000F00 //***************************************************************************** // @@ -240,9 +240,9 @@ // 5: 161...192 // 6: 193...224 // 7: 225...256 -#define CPU_SCS_ICTR_INTLINESNUM_W 3 -#define CPU_SCS_ICTR_INTLINESNUM_M 0x00000007 -#define CPU_SCS_ICTR_INTLINESNUM_S 0 +#define CPU_SCS_ICTR_INTLINESNUM_W 3 +#define CPU_SCS_ICTR_INTLINESNUM_M 0x00000007 +#define CPU_SCS_ICTR_INTLINESNUM_S 0 //***************************************************************************** // @@ -252,10 +252,10 @@ // Field: [2] DISFOLD // // Disables folding of IT instruction. -#define CPU_SCS_ACTLR_DISFOLD 0x00000004 -#define CPU_SCS_ACTLR_DISFOLD_BITN 2 -#define CPU_SCS_ACTLR_DISFOLD_M 0x00000004 -#define CPU_SCS_ACTLR_DISFOLD_S 2 +#define CPU_SCS_ACTLR_DISFOLD 0x00000004 +#define CPU_SCS_ACTLR_DISFOLD_BITN 2 +#define CPU_SCS_ACTLR_DISFOLD_M 0x00000004 +#define CPU_SCS_ACTLR_DISFOLD_S 2 // Field: [1] DISDEFWBUF // @@ -263,20 +263,20 @@ // all bus faults to be precise bus faults but decreases the performance of the // processor because the stores to memory have to complete before the next // instruction can be executed. -#define CPU_SCS_ACTLR_DISDEFWBUF 0x00000002 -#define CPU_SCS_ACTLR_DISDEFWBUF_BITN 1 -#define CPU_SCS_ACTLR_DISDEFWBUF_M 0x00000002 -#define CPU_SCS_ACTLR_DISDEFWBUF_S 1 +#define CPU_SCS_ACTLR_DISDEFWBUF 0x00000002 +#define CPU_SCS_ACTLR_DISDEFWBUF_BITN 1 +#define CPU_SCS_ACTLR_DISDEFWBUF_M 0x00000002 +#define CPU_SCS_ACTLR_DISDEFWBUF_S 1 // Field: [0] DISMCYCINT // // Disables interruption of multi-cycle instructions. This increases the // interrupt latency of the processor becuase LDM/STM completes before // interrupt stacking occurs. -#define CPU_SCS_ACTLR_DISMCYCINT 0x00000001 -#define CPU_SCS_ACTLR_DISMCYCINT_BITN 0 -#define CPU_SCS_ACTLR_DISMCYCINT_M 0x00000001 -#define CPU_SCS_ACTLR_DISMCYCINT_S 0 +#define CPU_SCS_ACTLR_DISMCYCINT 0x00000001 +#define CPU_SCS_ACTLR_DISMCYCINT_BITN 0 +#define CPU_SCS_ACTLR_DISMCYCINT_M 0x00000001 +#define CPU_SCS_ACTLR_DISMCYCINT_S 0 //***************************************************************************** // @@ -290,10 +290,10 @@ // If read by the debugger using the DAP, this bit is cleared on read-only if // the MasterType bit in the **AHB-AP** Control Register is set to 0. // Otherwise, COUNTFLAG is not changed by the debugger read. -#define CPU_SCS_STCSR_COUNTFLAG 0x00010000 -#define CPU_SCS_STCSR_COUNTFLAG_BITN 16 -#define CPU_SCS_STCSR_COUNTFLAG_M 0x00010000 -#define CPU_SCS_STCSR_COUNTFLAG_S 16 +#define CPU_SCS_STCSR_COUNTFLAG 0x00010000 +#define CPU_SCS_STCSR_COUNTFLAG_BITN 16 +#define CPU_SCS_STCSR_COUNTFLAG_M 0x00010000 +#define CPU_SCS_STCSR_COUNTFLAG_S 16 // Field: [2] CLKSOURCE // @@ -304,20 +304,20 @@ // // External clock is not available in this device. Writes to this field will be // ignored. -#define CPU_SCS_STCSR_CLKSOURCE 0x00000004 -#define CPU_SCS_STCSR_CLKSOURCE_BITN 2 -#define CPU_SCS_STCSR_CLKSOURCE_M 0x00000004 -#define CPU_SCS_STCSR_CLKSOURCE_S 2 +#define CPU_SCS_STCSR_CLKSOURCE 0x00000004 +#define CPU_SCS_STCSR_CLKSOURCE_BITN 2 +#define CPU_SCS_STCSR_CLKSOURCE_M 0x00000004 +#define CPU_SCS_STCSR_CLKSOURCE_S 2 // Field: [1] TICKINT // // 0: Counting down to zero does not pend the SysTick handler. Software can use // COUNTFLAG to determine if the SysTick handler has ever counted to zero. // 1: Counting down to zero pends the SysTick handler. -#define CPU_SCS_STCSR_TICKINT 0x00000002 -#define CPU_SCS_STCSR_TICKINT_BITN 1 -#define CPU_SCS_STCSR_TICKINT_M 0x00000002 -#define CPU_SCS_STCSR_TICKINT_S 1 +#define CPU_SCS_STCSR_TICKINT 0x00000002 +#define CPU_SCS_STCSR_TICKINT_BITN 1 +#define CPU_SCS_STCSR_TICKINT_M 0x00000002 +#define CPU_SCS_STCSR_TICKINT_S 1 // Field: [0] ENABLE // @@ -328,10 +328,10 @@ // Reload value STRVR.RELOAD and then begins counting down. On reaching 0, it // sets COUNTFLAG to 1 and optionally pends the SysTick handler, based on // TICKINT. It then loads STRVR.RELOAD again, and begins counting. -#define CPU_SCS_STCSR_ENABLE 0x00000001 -#define CPU_SCS_STCSR_ENABLE_BITN 0 -#define CPU_SCS_STCSR_ENABLE_M 0x00000001 -#define CPU_SCS_STCSR_ENABLE_S 0 +#define CPU_SCS_STCSR_ENABLE 0x00000001 +#define CPU_SCS_STCSR_ENABLE_BITN 0 +#define CPU_SCS_STCSR_ENABLE_M 0x00000001 +#define CPU_SCS_STCSR_ENABLE_S 0 //***************************************************************************** // @@ -342,9 +342,9 @@ // // Value to load into the SysTick Current Value Register STCVR.CURRENT when the // counter reaches 0. -#define CPU_SCS_STRVR_RELOAD_W 24 -#define CPU_SCS_STRVR_RELOAD_M 0x00FFFFFF -#define CPU_SCS_STRVR_RELOAD_S 0 +#define CPU_SCS_STRVR_RELOAD_W 24 +#define CPU_SCS_STRVR_RELOAD_M 0x00FFFFFF +#define CPU_SCS_STRVR_RELOAD_S 0 //***************************************************************************** // @@ -357,9 +357,9 @@ // protection is provided, so change with care. Writing to it with any value // clears the register to 0. Clearing this register also clears // STCSR.COUNTFLAG. -#define CPU_SCS_STCVR_CURRENT_W 24 -#define CPU_SCS_STCVR_CURRENT_M 0x00FFFFFF -#define CPU_SCS_STCVR_CURRENT_S 0 +#define CPU_SCS_STCVR_CURRENT_W 24 +#define CPU_SCS_STCVR_CURRENT_M 0x00FFFFFF +#define CPU_SCS_STCVR_CURRENT_S 0 //***************************************************************************** // @@ -369,28 +369,28 @@ // Field: [31] NOREF // // Reads as one. Indicates that no separate reference clock is provided. -#define CPU_SCS_STCR_NOREF 0x80000000 -#define CPU_SCS_STCR_NOREF_BITN 31 -#define CPU_SCS_STCR_NOREF_M 0x80000000 -#define CPU_SCS_STCR_NOREF_S 31 +#define CPU_SCS_STCR_NOREF 0x80000000 +#define CPU_SCS_STCR_NOREF_BITN 31 +#define CPU_SCS_STCR_NOREF_M 0x80000000 +#define CPU_SCS_STCR_NOREF_S 31 // Field: [30] SKEW // // Reads as one. The calibration value is not exactly 10ms because of clock // frequency. This could affect its suitability as a software real time clock. -#define CPU_SCS_STCR_SKEW 0x40000000 -#define CPU_SCS_STCR_SKEW_BITN 30 -#define CPU_SCS_STCR_SKEW_M 0x40000000 -#define CPU_SCS_STCR_SKEW_S 30 +#define CPU_SCS_STCR_SKEW 0x40000000 +#define CPU_SCS_STCR_SKEW_BITN 30 +#define CPU_SCS_STCR_SKEW_M 0x40000000 +#define CPU_SCS_STCR_SKEW_S 30 // Field: [23:0] TENMS // // An optional Reload value to be used for 10ms (100Hz) timing, subject to // system clock skew errors. The value read is valid only when core clock is at // 48MHz. -#define CPU_SCS_STCR_TENMS_W 24 -#define CPU_SCS_STCR_TENMS_M 0x00FFFFFF -#define CPU_SCS_STCR_TENMS_S 0 +#define CPU_SCS_STCR_TENMS_W 24 +#define CPU_SCS_STCR_TENMS_M 0x00FFFFFF +#define CPU_SCS_STCR_TENMS_S 0 //***************************************************************************** // @@ -402,320 +402,320 @@ // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA31 0x80000000 -#define CPU_SCS_NVIC_ISER0_SETENA31_BITN 31 -#define CPU_SCS_NVIC_ISER0_SETENA31_M 0x80000000 -#define CPU_SCS_NVIC_ISER0_SETENA31_S 31 +#define CPU_SCS_NVIC_ISER0_SETENA31 0x80000000 +#define CPU_SCS_NVIC_ISER0_SETENA31_BITN 31 +#define CPU_SCS_NVIC_ISER0_SETENA31_M 0x80000000 +#define CPU_SCS_NVIC_ISER0_SETENA31_S 31 // Field: [30] SETENA30 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA30 0x40000000 -#define CPU_SCS_NVIC_ISER0_SETENA30_BITN 30 -#define CPU_SCS_NVIC_ISER0_SETENA30_M 0x40000000 -#define CPU_SCS_NVIC_ISER0_SETENA30_S 30 +#define CPU_SCS_NVIC_ISER0_SETENA30 0x40000000 +#define CPU_SCS_NVIC_ISER0_SETENA30_BITN 30 +#define CPU_SCS_NVIC_ISER0_SETENA30_M 0x40000000 +#define CPU_SCS_NVIC_ISER0_SETENA30_S 30 // Field: [29] SETENA29 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA29 0x20000000 -#define CPU_SCS_NVIC_ISER0_SETENA29_BITN 29 -#define CPU_SCS_NVIC_ISER0_SETENA29_M 0x20000000 -#define CPU_SCS_NVIC_ISER0_SETENA29_S 29 +#define CPU_SCS_NVIC_ISER0_SETENA29 0x20000000 +#define CPU_SCS_NVIC_ISER0_SETENA29_BITN 29 +#define CPU_SCS_NVIC_ISER0_SETENA29_M 0x20000000 +#define CPU_SCS_NVIC_ISER0_SETENA29_S 29 // Field: [28] SETENA28 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA28 0x10000000 -#define CPU_SCS_NVIC_ISER0_SETENA28_BITN 28 -#define CPU_SCS_NVIC_ISER0_SETENA28_M 0x10000000 -#define CPU_SCS_NVIC_ISER0_SETENA28_S 28 +#define CPU_SCS_NVIC_ISER0_SETENA28 0x10000000 +#define CPU_SCS_NVIC_ISER0_SETENA28_BITN 28 +#define CPU_SCS_NVIC_ISER0_SETENA28_M 0x10000000 +#define CPU_SCS_NVIC_ISER0_SETENA28_S 28 // Field: [27] SETENA27 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA27 0x08000000 -#define CPU_SCS_NVIC_ISER0_SETENA27_BITN 27 -#define CPU_SCS_NVIC_ISER0_SETENA27_M 0x08000000 -#define CPU_SCS_NVIC_ISER0_SETENA27_S 27 +#define CPU_SCS_NVIC_ISER0_SETENA27 0x08000000 +#define CPU_SCS_NVIC_ISER0_SETENA27_BITN 27 +#define CPU_SCS_NVIC_ISER0_SETENA27_M 0x08000000 +#define CPU_SCS_NVIC_ISER0_SETENA27_S 27 // Field: [26] SETENA26 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA26 0x04000000 -#define CPU_SCS_NVIC_ISER0_SETENA26_BITN 26 -#define CPU_SCS_NVIC_ISER0_SETENA26_M 0x04000000 -#define CPU_SCS_NVIC_ISER0_SETENA26_S 26 +#define CPU_SCS_NVIC_ISER0_SETENA26 0x04000000 +#define CPU_SCS_NVIC_ISER0_SETENA26_BITN 26 +#define CPU_SCS_NVIC_ISER0_SETENA26_M 0x04000000 +#define CPU_SCS_NVIC_ISER0_SETENA26_S 26 // Field: [25] SETENA25 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA25 0x02000000 -#define CPU_SCS_NVIC_ISER0_SETENA25_BITN 25 -#define CPU_SCS_NVIC_ISER0_SETENA25_M 0x02000000 -#define CPU_SCS_NVIC_ISER0_SETENA25_S 25 +#define CPU_SCS_NVIC_ISER0_SETENA25 0x02000000 +#define CPU_SCS_NVIC_ISER0_SETENA25_BITN 25 +#define CPU_SCS_NVIC_ISER0_SETENA25_M 0x02000000 +#define CPU_SCS_NVIC_ISER0_SETENA25_S 25 // Field: [24] SETENA24 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA24 0x01000000 -#define CPU_SCS_NVIC_ISER0_SETENA24_BITN 24 -#define CPU_SCS_NVIC_ISER0_SETENA24_M 0x01000000 -#define CPU_SCS_NVIC_ISER0_SETENA24_S 24 +#define CPU_SCS_NVIC_ISER0_SETENA24 0x01000000 +#define CPU_SCS_NVIC_ISER0_SETENA24_BITN 24 +#define CPU_SCS_NVIC_ISER0_SETENA24_M 0x01000000 +#define CPU_SCS_NVIC_ISER0_SETENA24_S 24 // Field: [23] SETENA23 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA23 0x00800000 -#define CPU_SCS_NVIC_ISER0_SETENA23_BITN 23 -#define CPU_SCS_NVIC_ISER0_SETENA23_M 0x00800000 -#define CPU_SCS_NVIC_ISER0_SETENA23_S 23 +#define CPU_SCS_NVIC_ISER0_SETENA23 0x00800000 +#define CPU_SCS_NVIC_ISER0_SETENA23_BITN 23 +#define CPU_SCS_NVIC_ISER0_SETENA23_M 0x00800000 +#define CPU_SCS_NVIC_ISER0_SETENA23_S 23 // Field: [22] SETENA22 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA22 0x00400000 -#define CPU_SCS_NVIC_ISER0_SETENA22_BITN 22 -#define CPU_SCS_NVIC_ISER0_SETENA22_M 0x00400000 -#define CPU_SCS_NVIC_ISER0_SETENA22_S 22 +#define CPU_SCS_NVIC_ISER0_SETENA22 0x00400000 +#define CPU_SCS_NVIC_ISER0_SETENA22_BITN 22 +#define CPU_SCS_NVIC_ISER0_SETENA22_M 0x00400000 +#define CPU_SCS_NVIC_ISER0_SETENA22_S 22 // Field: [21] SETENA21 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA21 0x00200000 -#define CPU_SCS_NVIC_ISER0_SETENA21_BITN 21 -#define CPU_SCS_NVIC_ISER0_SETENA21_M 0x00200000 -#define CPU_SCS_NVIC_ISER0_SETENA21_S 21 +#define CPU_SCS_NVIC_ISER0_SETENA21 0x00200000 +#define CPU_SCS_NVIC_ISER0_SETENA21_BITN 21 +#define CPU_SCS_NVIC_ISER0_SETENA21_M 0x00200000 +#define CPU_SCS_NVIC_ISER0_SETENA21_S 21 // Field: [20] SETENA20 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA20 0x00100000 -#define CPU_SCS_NVIC_ISER0_SETENA20_BITN 20 -#define CPU_SCS_NVIC_ISER0_SETENA20_M 0x00100000 -#define CPU_SCS_NVIC_ISER0_SETENA20_S 20 +#define CPU_SCS_NVIC_ISER0_SETENA20 0x00100000 +#define CPU_SCS_NVIC_ISER0_SETENA20_BITN 20 +#define CPU_SCS_NVIC_ISER0_SETENA20_M 0x00100000 +#define CPU_SCS_NVIC_ISER0_SETENA20_S 20 // Field: [19] SETENA19 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA19 0x00080000 -#define CPU_SCS_NVIC_ISER0_SETENA19_BITN 19 -#define CPU_SCS_NVIC_ISER0_SETENA19_M 0x00080000 -#define CPU_SCS_NVIC_ISER0_SETENA19_S 19 +#define CPU_SCS_NVIC_ISER0_SETENA19 0x00080000 +#define CPU_SCS_NVIC_ISER0_SETENA19_BITN 19 +#define CPU_SCS_NVIC_ISER0_SETENA19_M 0x00080000 +#define CPU_SCS_NVIC_ISER0_SETENA19_S 19 // Field: [18] SETENA18 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA18 0x00040000 -#define CPU_SCS_NVIC_ISER0_SETENA18_BITN 18 -#define CPU_SCS_NVIC_ISER0_SETENA18_M 0x00040000 -#define CPU_SCS_NVIC_ISER0_SETENA18_S 18 +#define CPU_SCS_NVIC_ISER0_SETENA18 0x00040000 +#define CPU_SCS_NVIC_ISER0_SETENA18_BITN 18 +#define CPU_SCS_NVIC_ISER0_SETENA18_M 0x00040000 +#define CPU_SCS_NVIC_ISER0_SETENA18_S 18 // Field: [17] SETENA17 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA17 0x00020000 -#define CPU_SCS_NVIC_ISER0_SETENA17_BITN 17 -#define CPU_SCS_NVIC_ISER0_SETENA17_M 0x00020000 -#define CPU_SCS_NVIC_ISER0_SETENA17_S 17 +#define CPU_SCS_NVIC_ISER0_SETENA17 0x00020000 +#define CPU_SCS_NVIC_ISER0_SETENA17_BITN 17 +#define CPU_SCS_NVIC_ISER0_SETENA17_M 0x00020000 +#define CPU_SCS_NVIC_ISER0_SETENA17_S 17 // Field: [16] SETENA16 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA16 0x00010000 -#define CPU_SCS_NVIC_ISER0_SETENA16_BITN 16 -#define CPU_SCS_NVIC_ISER0_SETENA16_M 0x00010000 -#define CPU_SCS_NVIC_ISER0_SETENA16_S 16 +#define CPU_SCS_NVIC_ISER0_SETENA16 0x00010000 +#define CPU_SCS_NVIC_ISER0_SETENA16_BITN 16 +#define CPU_SCS_NVIC_ISER0_SETENA16_M 0x00010000 +#define CPU_SCS_NVIC_ISER0_SETENA16_S 16 // Field: [15] SETENA15 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA15 0x00008000 -#define CPU_SCS_NVIC_ISER0_SETENA15_BITN 15 -#define CPU_SCS_NVIC_ISER0_SETENA15_M 0x00008000 -#define CPU_SCS_NVIC_ISER0_SETENA15_S 15 +#define CPU_SCS_NVIC_ISER0_SETENA15 0x00008000 +#define CPU_SCS_NVIC_ISER0_SETENA15_BITN 15 +#define CPU_SCS_NVIC_ISER0_SETENA15_M 0x00008000 +#define CPU_SCS_NVIC_ISER0_SETENA15_S 15 // Field: [14] SETENA14 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA14 0x00004000 -#define CPU_SCS_NVIC_ISER0_SETENA14_BITN 14 -#define CPU_SCS_NVIC_ISER0_SETENA14_M 0x00004000 -#define CPU_SCS_NVIC_ISER0_SETENA14_S 14 +#define CPU_SCS_NVIC_ISER0_SETENA14 0x00004000 +#define CPU_SCS_NVIC_ISER0_SETENA14_BITN 14 +#define CPU_SCS_NVIC_ISER0_SETENA14_M 0x00004000 +#define CPU_SCS_NVIC_ISER0_SETENA14_S 14 // Field: [13] SETENA13 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA13 0x00002000 -#define CPU_SCS_NVIC_ISER0_SETENA13_BITN 13 -#define CPU_SCS_NVIC_ISER0_SETENA13_M 0x00002000 -#define CPU_SCS_NVIC_ISER0_SETENA13_S 13 +#define CPU_SCS_NVIC_ISER0_SETENA13 0x00002000 +#define CPU_SCS_NVIC_ISER0_SETENA13_BITN 13 +#define CPU_SCS_NVIC_ISER0_SETENA13_M 0x00002000 +#define CPU_SCS_NVIC_ISER0_SETENA13_S 13 // Field: [12] SETENA12 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA12 0x00001000 -#define CPU_SCS_NVIC_ISER0_SETENA12_BITN 12 -#define CPU_SCS_NVIC_ISER0_SETENA12_M 0x00001000 -#define CPU_SCS_NVIC_ISER0_SETENA12_S 12 +#define CPU_SCS_NVIC_ISER0_SETENA12 0x00001000 +#define CPU_SCS_NVIC_ISER0_SETENA12_BITN 12 +#define CPU_SCS_NVIC_ISER0_SETENA12_M 0x00001000 +#define CPU_SCS_NVIC_ISER0_SETENA12_S 12 // Field: [11] SETENA11 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA11 0x00000800 -#define CPU_SCS_NVIC_ISER0_SETENA11_BITN 11 -#define CPU_SCS_NVIC_ISER0_SETENA11_M 0x00000800 -#define CPU_SCS_NVIC_ISER0_SETENA11_S 11 +#define CPU_SCS_NVIC_ISER0_SETENA11 0x00000800 +#define CPU_SCS_NVIC_ISER0_SETENA11_BITN 11 +#define CPU_SCS_NVIC_ISER0_SETENA11_M 0x00000800 +#define CPU_SCS_NVIC_ISER0_SETENA11_S 11 // Field: [10] SETENA10 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA10 0x00000400 -#define CPU_SCS_NVIC_ISER0_SETENA10_BITN 10 -#define CPU_SCS_NVIC_ISER0_SETENA10_M 0x00000400 -#define CPU_SCS_NVIC_ISER0_SETENA10_S 10 +#define CPU_SCS_NVIC_ISER0_SETENA10 0x00000400 +#define CPU_SCS_NVIC_ISER0_SETENA10_BITN 10 +#define CPU_SCS_NVIC_ISER0_SETENA10_M 0x00000400 +#define CPU_SCS_NVIC_ISER0_SETENA10_S 10 // Field: [9] SETENA9 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA9 0x00000200 -#define CPU_SCS_NVIC_ISER0_SETENA9_BITN 9 -#define CPU_SCS_NVIC_ISER0_SETENA9_M 0x00000200 -#define CPU_SCS_NVIC_ISER0_SETENA9_S 9 +#define CPU_SCS_NVIC_ISER0_SETENA9 0x00000200 +#define CPU_SCS_NVIC_ISER0_SETENA9_BITN 9 +#define CPU_SCS_NVIC_ISER0_SETENA9_M 0x00000200 +#define CPU_SCS_NVIC_ISER0_SETENA9_S 9 // Field: [8] SETENA8 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA8 0x00000100 -#define CPU_SCS_NVIC_ISER0_SETENA8_BITN 8 -#define CPU_SCS_NVIC_ISER0_SETENA8_M 0x00000100 -#define CPU_SCS_NVIC_ISER0_SETENA8_S 8 +#define CPU_SCS_NVIC_ISER0_SETENA8 0x00000100 +#define CPU_SCS_NVIC_ISER0_SETENA8_BITN 8 +#define CPU_SCS_NVIC_ISER0_SETENA8_M 0x00000100 +#define CPU_SCS_NVIC_ISER0_SETENA8_S 8 // Field: [7] SETENA7 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA7 0x00000080 -#define CPU_SCS_NVIC_ISER0_SETENA7_BITN 7 -#define CPU_SCS_NVIC_ISER0_SETENA7_M 0x00000080 -#define CPU_SCS_NVIC_ISER0_SETENA7_S 7 +#define CPU_SCS_NVIC_ISER0_SETENA7 0x00000080 +#define CPU_SCS_NVIC_ISER0_SETENA7_BITN 7 +#define CPU_SCS_NVIC_ISER0_SETENA7_M 0x00000080 +#define CPU_SCS_NVIC_ISER0_SETENA7_S 7 // Field: [6] SETENA6 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA6 0x00000040 -#define CPU_SCS_NVIC_ISER0_SETENA6_BITN 6 -#define CPU_SCS_NVIC_ISER0_SETENA6_M 0x00000040 -#define CPU_SCS_NVIC_ISER0_SETENA6_S 6 +#define CPU_SCS_NVIC_ISER0_SETENA6 0x00000040 +#define CPU_SCS_NVIC_ISER0_SETENA6_BITN 6 +#define CPU_SCS_NVIC_ISER0_SETENA6_M 0x00000040 +#define CPU_SCS_NVIC_ISER0_SETENA6_S 6 // Field: [5] SETENA5 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA5 0x00000020 -#define CPU_SCS_NVIC_ISER0_SETENA5_BITN 5 -#define CPU_SCS_NVIC_ISER0_SETENA5_M 0x00000020 -#define CPU_SCS_NVIC_ISER0_SETENA5_S 5 +#define CPU_SCS_NVIC_ISER0_SETENA5 0x00000020 +#define CPU_SCS_NVIC_ISER0_SETENA5_BITN 5 +#define CPU_SCS_NVIC_ISER0_SETENA5_M 0x00000020 +#define CPU_SCS_NVIC_ISER0_SETENA5_S 5 // Field: [4] SETENA4 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA4 0x00000010 -#define CPU_SCS_NVIC_ISER0_SETENA4_BITN 4 -#define CPU_SCS_NVIC_ISER0_SETENA4_M 0x00000010 -#define CPU_SCS_NVIC_ISER0_SETENA4_S 4 +#define CPU_SCS_NVIC_ISER0_SETENA4 0x00000010 +#define CPU_SCS_NVIC_ISER0_SETENA4_BITN 4 +#define CPU_SCS_NVIC_ISER0_SETENA4_M 0x00000010 +#define CPU_SCS_NVIC_ISER0_SETENA4_S 4 // Field: [3] SETENA3 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA3 0x00000008 -#define CPU_SCS_NVIC_ISER0_SETENA3_BITN 3 -#define CPU_SCS_NVIC_ISER0_SETENA3_M 0x00000008 -#define CPU_SCS_NVIC_ISER0_SETENA3_S 3 +#define CPU_SCS_NVIC_ISER0_SETENA3 0x00000008 +#define CPU_SCS_NVIC_ISER0_SETENA3_BITN 3 +#define CPU_SCS_NVIC_ISER0_SETENA3_M 0x00000008 +#define CPU_SCS_NVIC_ISER0_SETENA3_S 3 // Field: [2] SETENA2 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA2 0x00000004 -#define CPU_SCS_NVIC_ISER0_SETENA2_BITN 2 -#define CPU_SCS_NVIC_ISER0_SETENA2_M 0x00000004 -#define CPU_SCS_NVIC_ISER0_SETENA2_S 2 +#define CPU_SCS_NVIC_ISER0_SETENA2 0x00000004 +#define CPU_SCS_NVIC_ISER0_SETENA2_BITN 2 +#define CPU_SCS_NVIC_ISER0_SETENA2_M 0x00000004 +#define CPU_SCS_NVIC_ISER0_SETENA2_S 2 // Field: [1] SETENA1 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA1 0x00000002 -#define CPU_SCS_NVIC_ISER0_SETENA1_BITN 1 -#define CPU_SCS_NVIC_ISER0_SETENA1_M 0x00000002 -#define CPU_SCS_NVIC_ISER0_SETENA1_S 1 +#define CPU_SCS_NVIC_ISER0_SETENA1 0x00000002 +#define CPU_SCS_NVIC_ISER0_SETENA1_BITN 1 +#define CPU_SCS_NVIC_ISER0_SETENA1_M 0x00000002 +#define CPU_SCS_NVIC_ISER0_SETENA1_S 1 // Field: [0] SETENA0 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA0 0x00000001 -#define CPU_SCS_NVIC_ISER0_SETENA0_BITN 0 -#define CPU_SCS_NVIC_ISER0_SETENA0_M 0x00000001 -#define CPU_SCS_NVIC_ISER0_SETENA0_S 0 +#define CPU_SCS_NVIC_ISER0_SETENA0 0x00000001 +#define CPU_SCS_NVIC_ISER0_SETENA0_BITN 0 +#define CPU_SCS_NVIC_ISER0_SETENA0_M 0x00000001 +#define CPU_SCS_NVIC_ISER0_SETENA0_S 0 //***************************************************************************** // @@ -727,20 +727,20 @@ // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER1_SETENA33 0x00000002 -#define CPU_SCS_NVIC_ISER1_SETENA33_BITN 1 -#define CPU_SCS_NVIC_ISER1_SETENA33_M 0x00000002 -#define CPU_SCS_NVIC_ISER1_SETENA33_S 1 +#define CPU_SCS_NVIC_ISER1_SETENA33 0x00000002 +#define CPU_SCS_NVIC_ISER1_SETENA33_BITN 1 +#define CPU_SCS_NVIC_ISER1_SETENA33_M 0x00000002 +#define CPU_SCS_NVIC_ISER1_SETENA33_S 1 // Field: [0] SETENA32 // // Writing 0 to this bit has no effect, writing 1 to this bit enables the // interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ISER1_SETENA32 0x00000001 -#define CPU_SCS_NVIC_ISER1_SETENA32_BITN 0 -#define CPU_SCS_NVIC_ISER1_SETENA32_M 0x00000001 -#define CPU_SCS_NVIC_ISER1_SETENA32_S 0 +#define CPU_SCS_NVIC_ISER1_SETENA32 0x00000001 +#define CPU_SCS_NVIC_ISER1_SETENA32_BITN 0 +#define CPU_SCS_NVIC_ISER1_SETENA32_M 0x00000001 +#define CPU_SCS_NVIC_ISER1_SETENA32_S 0 //***************************************************************************** // @@ -752,320 +752,320 @@ // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA31 0x80000000 -#define CPU_SCS_NVIC_ICER0_CLRENA31_BITN 31 -#define CPU_SCS_NVIC_ICER0_CLRENA31_M 0x80000000 -#define CPU_SCS_NVIC_ICER0_CLRENA31_S 31 +#define CPU_SCS_NVIC_ICER0_CLRENA31 0x80000000 +#define CPU_SCS_NVIC_ICER0_CLRENA31_BITN 31 +#define CPU_SCS_NVIC_ICER0_CLRENA31_M 0x80000000 +#define CPU_SCS_NVIC_ICER0_CLRENA31_S 31 // Field: [30] CLRENA30 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA30 0x40000000 -#define CPU_SCS_NVIC_ICER0_CLRENA30_BITN 30 -#define CPU_SCS_NVIC_ICER0_CLRENA30_M 0x40000000 -#define CPU_SCS_NVIC_ICER0_CLRENA30_S 30 +#define CPU_SCS_NVIC_ICER0_CLRENA30 0x40000000 +#define CPU_SCS_NVIC_ICER0_CLRENA30_BITN 30 +#define CPU_SCS_NVIC_ICER0_CLRENA30_M 0x40000000 +#define CPU_SCS_NVIC_ICER0_CLRENA30_S 30 // Field: [29] CLRENA29 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA29 0x20000000 -#define CPU_SCS_NVIC_ICER0_CLRENA29_BITN 29 -#define CPU_SCS_NVIC_ICER0_CLRENA29_M 0x20000000 -#define CPU_SCS_NVIC_ICER0_CLRENA29_S 29 +#define CPU_SCS_NVIC_ICER0_CLRENA29 0x20000000 +#define CPU_SCS_NVIC_ICER0_CLRENA29_BITN 29 +#define CPU_SCS_NVIC_ICER0_CLRENA29_M 0x20000000 +#define CPU_SCS_NVIC_ICER0_CLRENA29_S 29 // Field: [28] CLRENA28 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA28 0x10000000 -#define CPU_SCS_NVIC_ICER0_CLRENA28_BITN 28 -#define CPU_SCS_NVIC_ICER0_CLRENA28_M 0x10000000 -#define CPU_SCS_NVIC_ICER0_CLRENA28_S 28 +#define CPU_SCS_NVIC_ICER0_CLRENA28 0x10000000 +#define CPU_SCS_NVIC_ICER0_CLRENA28_BITN 28 +#define CPU_SCS_NVIC_ICER0_CLRENA28_M 0x10000000 +#define CPU_SCS_NVIC_ICER0_CLRENA28_S 28 // Field: [27] CLRENA27 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA27 0x08000000 -#define CPU_SCS_NVIC_ICER0_CLRENA27_BITN 27 -#define CPU_SCS_NVIC_ICER0_CLRENA27_M 0x08000000 -#define CPU_SCS_NVIC_ICER0_CLRENA27_S 27 +#define CPU_SCS_NVIC_ICER0_CLRENA27 0x08000000 +#define CPU_SCS_NVIC_ICER0_CLRENA27_BITN 27 +#define CPU_SCS_NVIC_ICER0_CLRENA27_M 0x08000000 +#define CPU_SCS_NVIC_ICER0_CLRENA27_S 27 // Field: [26] CLRENA26 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA26 0x04000000 -#define CPU_SCS_NVIC_ICER0_CLRENA26_BITN 26 -#define CPU_SCS_NVIC_ICER0_CLRENA26_M 0x04000000 -#define CPU_SCS_NVIC_ICER0_CLRENA26_S 26 +#define CPU_SCS_NVIC_ICER0_CLRENA26 0x04000000 +#define CPU_SCS_NVIC_ICER0_CLRENA26_BITN 26 +#define CPU_SCS_NVIC_ICER0_CLRENA26_M 0x04000000 +#define CPU_SCS_NVIC_ICER0_CLRENA26_S 26 // Field: [25] CLRENA25 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA25 0x02000000 -#define CPU_SCS_NVIC_ICER0_CLRENA25_BITN 25 -#define CPU_SCS_NVIC_ICER0_CLRENA25_M 0x02000000 -#define CPU_SCS_NVIC_ICER0_CLRENA25_S 25 +#define CPU_SCS_NVIC_ICER0_CLRENA25 0x02000000 +#define CPU_SCS_NVIC_ICER0_CLRENA25_BITN 25 +#define CPU_SCS_NVIC_ICER0_CLRENA25_M 0x02000000 +#define CPU_SCS_NVIC_ICER0_CLRENA25_S 25 // Field: [24] CLRENA24 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA24 0x01000000 -#define CPU_SCS_NVIC_ICER0_CLRENA24_BITN 24 -#define CPU_SCS_NVIC_ICER0_CLRENA24_M 0x01000000 -#define CPU_SCS_NVIC_ICER0_CLRENA24_S 24 +#define CPU_SCS_NVIC_ICER0_CLRENA24 0x01000000 +#define CPU_SCS_NVIC_ICER0_CLRENA24_BITN 24 +#define CPU_SCS_NVIC_ICER0_CLRENA24_M 0x01000000 +#define CPU_SCS_NVIC_ICER0_CLRENA24_S 24 // Field: [23] CLRENA23 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA23 0x00800000 -#define CPU_SCS_NVIC_ICER0_CLRENA23_BITN 23 -#define CPU_SCS_NVIC_ICER0_CLRENA23_M 0x00800000 -#define CPU_SCS_NVIC_ICER0_CLRENA23_S 23 +#define CPU_SCS_NVIC_ICER0_CLRENA23 0x00800000 +#define CPU_SCS_NVIC_ICER0_CLRENA23_BITN 23 +#define CPU_SCS_NVIC_ICER0_CLRENA23_M 0x00800000 +#define CPU_SCS_NVIC_ICER0_CLRENA23_S 23 // Field: [22] CLRENA22 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA22 0x00400000 -#define CPU_SCS_NVIC_ICER0_CLRENA22_BITN 22 -#define CPU_SCS_NVIC_ICER0_CLRENA22_M 0x00400000 -#define CPU_SCS_NVIC_ICER0_CLRENA22_S 22 +#define CPU_SCS_NVIC_ICER0_CLRENA22 0x00400000 +#define CPU_SCS_NVIC_ICER0_CLRENA22_BITN 22 +#define CPU_SCS_NVIC_ICER0_CLRENA22_M 0x00400000 +#define CPU_SCS_NVIC_ICER0_CLRENA22_S 22 // Field: [21] CLRENA21 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA21 0x00200000 -#define CPU_SCS_NVIC_ICER0_CLRENA21_BITN 21 -#define CPU_SCS_NVIC_ICER0_CLRENA21_M 0x00200000 -#define CPU_SCS_NVIC_ICER0_CLRENA21_S 21 +#define CPU_SCS_NVIC_ICER0_CLRENA21 0x00200000 +#define CPU_SCS_NVIC_ICER0_CLRENA21_BITN 21 +#define CPU_SCS_NVIC_ICER0_CLRENA21_M 0x00200000 +#define CPU_SCS_NVIC_ICER0_CLRENA21_S 21 // Field: [20] CLRENA20 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA20 0x00100000 -#define CPU_SCS_NVIC_ICER0_CLRENA20_BITN 20 -#define CPU_SCS_NVIC_ICER0_CLRENA20_M 0x00100000 -#define CPU_SCS_NVIC_ICER0_CLRENA20_S 20 +#define CPU_SCS_NVIC_ICER0_CLRENA20 0x00100000 +#define CPU_SCS_NVIC_ICER0_CLRENA20_BITN 20 +#define CPU_SCS_NVIC_ICER0_CLRENA20_M 0x00100000 +#define CPU_SCS_NVIC_ICER0_CLRENA20_S 20 // Field: [19] CLRENA19 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA19 0x00080000 -#define CPU_SCS_NVIC_ICER0_CLRENA19_BITN 19 -#define CPU_SCS_NVIC_ICER0_CLRENA19_M 0x00080000 -#define CPU_SCS_NVIC_ICER0_CLRENA19_S 19 +#define CPU_SCS_NVIC_ICER0_CLRENA19 0x00080000 +#define CPU_SCS_NVIC_ICER0_CLRENA19_BITN 19 +#define CPU_SCS_NVIC_ICER0_CLRENA19_M 0x00080000 +#define CPU_SCS_NVIC_ICER0_CLRENA19_S 19 // Field: [18] CLRENA18 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA18 0x00040000 -#define CPU_SCS_NVIC_ICER0_CLRENA18_BITN 18 -#define CPU_SCS_NVIC_ICER0_CLRENA18_M 0x00040000 -#define CPU_SCS_NVIC_ICER0_CLRENA18_S 18 +#define CPU_SCS_NVIC_ICER0_CLRENA18 0x00040000 +#define CPU_SCS_NVIC_ICER0_CLRENA18_BITN 18 +#define CPU_SCS_NVIC_ICER0_CLRENA18_M 0x00040000 +#define CPU_SCS_NVIC_ICER0_CLRENA18_S 18 // Field: [17] CLRENA17 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA17 0x00020000 -#define CPU_SCS_NVIC_ICER0_CLRENA17_BITN 17 -#define CPU_SCS_NVIC_ICER0_CLRENA17_M 0x00020000 -#define CPU_SCS_NVIC_ICER0_CLRENA17_S 17 +#define CPU_SCS_NVIC_ICER0_CLRENA17 0x00020000 +#define CPU_SCS_NVIC_ICER0_CLRENA17_BITN 17 +#define CPU_SCS_NVIC_ICER0_CLRENA17_M 0x00020000 +#define CPU_SCS_NVIC_ICER0_CLRENA17_S 17 // Field: [16] CLRENA16 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA16 0x00010000 -#define CPU_SCS_NVIC_ICER0_CLRENA16_BITN 16 -#define CPU_SCS_NVIC_ICER0_CLRENA16_M 0x00010000 -#define CPU_SCS_NVIC_ICER0_CLRENA16_S 16 +#define CPU_SCS_NVIC_ICER0_CLRENA16 0x00010000 +#define CPU_SCS_NVIC_ICER0_CLRENA16_BITN 16 +#define CPU_SCS_NVIC_ICER0_CLRENA16_M 0x00010000 +#define CPU_SCS_NVIC_ICER0_CLRENA16_S 16 // Field: [15] CLRENA15 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA15 0x00008000 -#define CPU_SCS_NVIC_ICER0_CLRENA15_BITN 15 -#define CPU_SCS_NVIC_ICER0_CLRENA15_M 0x00008000 -#define CPU_SCS_NVIC_ICER0_CLRENA15_S 15 +#define CPU_SCS_NVIC_ICER0_CLRENA15 0x00008000 +#define CPU_SCS_NVIC_ICER0_CLRENA15_BITN 15 +#define CPU_SCS_NVIC_ICER0_CLRENA15_M 0x00008000 +#define CPU_SCS_NVIC_ICER0_CLRENA15_S 15 // Field: [14] CLRENA14 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA14 0x00004000 -#define CPU_SCS_NVIC_ICER0_CLRENA14_BITN 14 -#define CPU_SCS_NVIC_ICER0_CLRENA14_M 0x00004000 -#define CPU_SCS_NVIC_ICER0_CLRENA14_S 14 +#define CPU_SCS_NVIC_ICER0_CLRENA14 0x00004000 +#define CPU_SCS_NVIC_ICER0_CLRENA14_BITN 14 +#define CPU_SCS_NVIC_ICER0_CLRENA14_M 0x00004000 +#define CPU_SCS_NVIC_ICER0_CLRENA14_S 14 // Field: [13] CLRENA13 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA13 0x00002000 -#define CPU_SCS_NVIC_ICER0_CLRENA13_BITN 13 -#define CPU_SCS_NVIC_ICER0_CLRENA13_M 0x00002000 -#define CPU_SCS_NVIC_ICER0_CLRENA13_S 13 +#define CPU_SCS_NVIC_ICER0_CLRENA13 0x00002000 +#define CPU_SCS_NVIC_ICER0_CLRENA13_BITN 13 +#define CPU_SCS_NVIC_ICER0_CLRENA13_M 0x00002000 +#define CPU_SCS_NVIC_ICER0_CLRENA13_S 13 // Field: [12] CLRENA12 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA12 0x00001000 -#define CPU_SCS_NVIC_ICER0_CLRENA12_BITN 12 -#define CPU_SCS_NVIC_ICER0_CLRENA12_M 0x00001000 -#define CPU_SCS_NVIC_ICER0_CLRENA12_S 12 +#define CPU_SCS_NVIC_ICER0_CLRENA12 0x00001000 +#define CPU_SCS_NVIC_ICER0_CLRENA12_BITN 12 +#define CPU_SCS_NVIC_ICER0_CLRENA12_M 0x00001000 +#define CPU_SCS_NVIC_ICER0_CLRENA12_S 12 // Field: [11] CLRENA11 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA11 0x00000800 -#define CPU_SCS_NVIC_ICER0_CLRENA11_BITN 11 -#define CPU_SCS_NVIC_ICER0_CLRENA11_M 0x00000800 -#define CPU_SCS_NVIC_ICER0_CLRENA11_S 11 +#define CPU_SCS_NVIC_ICER0_CLRENA11 0x00000800 +#define CPU_SCS_NVIC_ICER0_CLRENA11_BITN 11 +#define CPU_SCS_NVIC_ICER0_CLRENA11_M 0x00000800 +#define CPU_SCS_NVIC_ICER0_CLRENA11_S 11 // Field: [10] CLRENA10 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA10 0x00000400 -#define CPU_SCS_NVIC_ICER0_CLRENA10_BITN 10 -#define CPU_SCS_NVIC_ICER0_CLRENA10_M 0x00000400 -#define CPU_SCS_NVIC_ICER0_CLRENA10_S 10 +#define CPU_SCS_NVIC_ICER0_CLRENA10 0x00000400 +#define CPU_SCS_NVIC_ICER0_CLRENA10_BITN 10 +#define CPU_SCS_NVIC_ICER0_CLRENA10_M 0x00000400 +#define CPU_SCS_NVIC_ICER0_CLRENA10_S 10 // Field: [9] CLRENA9 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA9 0x00000200 -#define CPU_SCS_NVIC_ICER0_CLRENA9_BITN 9 -#define CPU_SCS_NVIC_ICER0_CLRENA9_M 0x00000200 -#define CPU_SCS_NVIC_ICER0_CLRENA9_S 9 +#define CPU_SCS_NVIC_ICER0_CLRENA9 0x00000200 +#define CPU_SCS_NVIC_ICER0_CLRENA9_BITN 9 +#define CPU_SCS_NVIC_ICER0_CLRENA9_M 0x00000200 +#define CPU_SCS_NVIC_ICER0_CLRENA9_S 9 // Field: [8] CLRENA8 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA8 0x00000100 -#define CPU_SCS_NVIC_ICER0_CLRENA8_BITN 8 -#define CPU_SCS_NVIC_ICER0_CLRENA8_M 0x00000100 -#define CPU_SCS_NVIC_ICER0_CLRENA8_S 8 +#define CPU_SCS_NVIC_ICER0_CLRENA8 0x00000100 +#define CPU_SCS_NVIC_ICER0_CLRENA8_BITN 8 +#define CPU_SCS_NVIC_ICER0_CLRENA8_M 0x00000100 +#define CPU_SCS_NVIC_ICER0_CLRENA8_S 8 // Field: [7] CLRENA7 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA7 0x00000080 -#define CPU_SCS_NVIC_ICER0_CLRENA7_BITN 7 -#define CPU_SCS_NVIC_ICER0_CLRENA7_M 0x00000080 -#define CPU_SCS_NVIC_ICER0_CLRENA7_S 7 +#define CPU_SCS_NVIC_ICER0_CLRENA7 0x00000080 +#define CPU_SCS_NVIC_ICER0_CLRENA7_BITN 7 +#define CPU_SCS_NVIC_ICER0_CLRENA7_M 0x00000080 +#define CPU_SCS_NVIC_ICER0_CLRENA7_S 7 // Field: [6] CLRENA6 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA6 0x00000040 -#define CPU_SCS_NVIC_ICER0_CLRENA6_BITN 6 -#define CPU_SCS_NVIC_ICER0_CLRENA6_M 0x00000040 -#define CPU_SCS_NVIC_ICER0_CLRENA6_S 6 +#define CPU_SCS_NVIC_ICER0_CLRENA6 0x00000040 +#define CPU_SCS_NVIC_ICER0_CLRENA6_BITN 6 +#define CPU_SCS_NVIC_ICER0_CLRENA6_M 0x00000040 +#define CPU_SCS_NVIC_ICER0_CLRENA6_S 6 // Field: [5] CLRENA5 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA5 0x00000020 -#define CPU_SCS_NVIC_ICER0_CLRENA5_BITN 5 -#define CPU_SCS_NVIC_ICER0_CLRENA5_M 0x00000020 -#define CPU_SCS_NVIC_ICER0_CLRENA5_S 5 +#define CPU_SCS_NVIC_ICER0_CLRENA5 0x00000020 +#define CPU_SCS_NVIC_ICER0_CLRENA5_BITN 5 +#define CPU_SCS_NVIC_ICER0_CLRENA5_M 0x00000020 +#define CPU_SCS_NVIC_ICER0_CLRENA5_S 5 // Field: [4] CLRENA4 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA4 0x00000010 -#define CPU_SCS_NVIC_ICER0_CLRENA4_BITN 4 -#define CPU_SCS_NVIC_ICER0_CLRENA4_M 0x00000010 -#define CPU_SCS_NVIC_ICER0_CLRENA4_S 4 +#define CPU_SCS_NVIC_ICER0_CLRENA4 0x00000010 +#define CPU_SCS_NVIC_ICER0_CLRENA4_BITN 4 +#define CPU_SCS_NVIC_ICER0_CLRENA4_M 0x00000010 +#define CPU_SCS_NVIC_ICER0_CLRENA4_S 4 // Field: [3] CLRENA3 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA3 0x00000008 -#define CPU_SCS_NVIC_ICER0_CLRENA3_BITN 3 -#define CPU_SCS_NVIC_ICER0_CLRENA3_M 0x00000008 -#define CPU_SCS_NVIC_ICER0_CLRENA3_S 3 +#define CPU_SCS_NVIC_ICER0_CLRENA3 0x00000008 +#define CPU_SCS_NVIC_ICER0_CLRENA3_BITN 3 +#define CPU_SCS_NVIC_ICER0_CLRENA3_M 0x00000008 +#define CPU_SCS_NVIC_ICER0_CLRENA3_S 3 // Field: [2] CLRENA2 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA2 0x00000004 -#define CPU_SCS_NVIC_ICER0_CLRENA2_BITN 2 -#define CPU_SCS_NVIC_ICER0_CLRENA2_M 0x00000004 -#define CPU_SCS_NVIC_ICER0_CLRENA2_S 2 +#define CPU_SCS_NVIC_ICER0_CLRENA2 0x00000004 +#define CPU_SCS_NVIC_ICER0_CLRENA2_BITN 2 +#define CPU_SCS_NVIC_ICER0_CLRENA2_M 0x00000004 +#define CPU_SCS_NVIC_ICER0_CLRENA2_S 2 // Field: [1] CLRENA1 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA1 0x00000002 -#define CPU_SCS_NVIC_ICER0_CLRENA1_BITN 1 -#define CPU_SCS_NVIC_ICER0_CLRENA1_M 0x00000002 -#define CPU_SCS_NVIC_ICER0_CLRENA1_S 1 +#define CPU_SCS_NVIC_ICER0_CLRENA1 0x00000002 +#define CPU_SCS_NVIC_ICER0_CLRENA1_BITN 1 +#define CPU_SCS_NVIC_ICER0_CLRENA1_M 0x00000002 +#define CPU_SCS_NVIC_ICER0_CLRENA1_S 1 // Field: [0] CLRENA0 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA0 0x00000001 -#define CPU_SCS_NVIC_ICER0_CLRENA0_BITN 0 -#define CPU_SCS_NVIC_ICER0_CLRENA0_M 0x00000001 -#define CPU_SCS_NVIC_ICER0_CLRENA0_S 0 +#define CPU_SCS_NVIC_ICER0_CLRENA0 0x00000001 +#define CPU_SCS_NVIC_ICER0_CLRENA0_BITN 0 +#define CPU_SCS_NVIC_ICER0_CLRENA0_M 0x00000001 +#define CPU_SCS_NVIC_ICER0_CLRENA0_S 0 //***************************************************************************** // @@ -1077,20 +1077,20 @@ // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER1_CLRENA33 0x00000002 -#define CPU_SCS_NVIC_ICER1_CLRENA33_BITN 1 -#define CPU_SCS_NVIC_ICER1_CLRENA33_M 0x00000002 -#define CPU_SCS_NVIC_ICER1_CLRENA33_S 1 +#define CPU_SCS_NVIC_ICER1_CLRENA33 0x00000002 +#define CPU_SCS_NVIC_ICER1_CLRENA33_BITN 1 +#define CPU_SCS_NVIC_ICER1_CLRENA33_M 0x00000002 +#define CPU_SCS_NVIC_ICER1_CLRENA33_S 1 // Field: [0] CLRENA32 // // Writing 0 to this bit has no effect, writing 1 to this bit disables the // interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit // returns its current enable state. -#define CPU_SCS_NVIC_ICER1_CLRENA32 0x00000001 -#define CPU_SCS_NVIC_ICER1_CLRENA32_BITN 0 -#define CPU_SCS_NVIC_ICER1_CLRENA32_M 0x00000001 -#define CPU_SCS_NVIC_ICER1_CLRENA32_S 0 +#define CPU_SCS_NVIC_ICER1_CLRENA32 0x00000001 +#define CPU_SCS_NVIC_ICER1_CLRENA32_BITN 0 +#define CPU_SCS_NVIC_ICER1_CLRENA32_M 0x00000001 +#define CPU_SCS_NVIC_ICER1_CLRENA32_S 0 //***************************************************************************** // @@ -1102,320 +1102,320 @@ // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND31 0x80000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND31_BITN 31 -#define CPU_SCS_NVIC_ISPR0_SETPEND31_M 0x80000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND31_S 31 +#define CPU_SCS_NVIC_ISPR0_SETPEND31 0x80000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_BITN 31 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_M 0x80000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND31_S 31 // Field: [30] SETPEND30 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND30 0x40000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND30_BITN 30 -#define CPU_SCS_NVIC_ISPR0_SETPEND30_M 0x40000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND30_S 30 +#define CPU_SCS_NVIC_ISPR0_SETPEND30 0x40000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_BITN 30 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_M 0x40000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND30_S 30 // Field: [29] SETPEND29 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND29 0x20000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND29_BITN 29 -#define CPU_SCS_NVIC_ISPR0_SETPEND29_M 0x20000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND29_S 29 +#define CPU_SCS_NVIC_ISPR0_SETPEND29 0x20000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_BITN 29 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_M 0x20000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND29_S 29 // Field: [28] SETPEND28 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND28 0x10000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND28_BITN 28 -#define CPU_SCS_NVIC_ISPR0_SETPEND28_M 0x10000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND28_S 28 +#define CPU_SCS_NVIC_ISPR0_SETPEND28 0x10000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_BITN 28 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_M 0x10000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND28_S 28 // Field: [27] SETPEND27 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND27 0x08000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND27_BITN 27 -#define CPU_SCS_NVIC_ISPR0_SETPEND27_M 0x08000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND27_S 27 +#define CPU_SCS_NVIC_ISPR0_SETPEND27 0x08000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_BITN 27 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_M 0x08000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND27_S 27 // Field: [26] SETPEND26 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND26 0x04000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND26_BITN 26 -#define CPU_SCS_NVIC_ISPR0_SETPEND26_M 0x04000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND26_S 26 +#define CPU_SCS_NVIC_ISPR0_SETPEND26 0x04000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_BITN 26 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_M 0x04000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND26_S 26 // Field: [25] SETPEND25 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND25 0x02000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND25_BITN 25 -#define CPU_SCS_NVIC_ISPR0_SETPEND25_M 0x02000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND25_S 25 +#define CPU_SCS_NVIC_ISPR0_SETPEND25 0x02000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_BITN 25 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_M 0x02000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND25_S 25 // Field: [24] SETPEND24 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND24 0x01000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND24_BITN 24 -#define CPU_SCS_NVIC_ISPR0_SETPEND24_M 0x01000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND24_S 24 +#define CPU_SCS_NVIC_ISPR0_SETPEND24 0x01000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_BITN 24 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_M 0x01000000 +#define CPU_SCS_NVIC_ISPR0_SETPEND24_S 24 // Field: [23] SETPEND23 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND23 0x00800000 -#define CPU_SCS_NVIC_ISPR0_SETPEND23_BITN 23 -#define CPU_SCS_NVIC_ISPR0_SETPEND23_M 0x00800000 -#define CPU_SCS_NVIC_ISPR0_SETPEND23_S 23 +#define CPU_SCS_NVIC_ISPR0_SETPEND23 0x00800000 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_BITN 23 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_M 0x00800000 +#define CPU_SCS_NVIC_ISPR0_SETPEND23_S 23 // Field: [22] SETPEND22 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND22 0x00400000 -#define CPU_SCS_NVIC_ISPR0_SETPEND22_BITN 22 -#define CPU_SCS_NVIC_ISPR0_SETPEND22_M 0x00400000 -#define CPU_SCS_NVIC_ISPR0_SETPEND22_S 22 +#define CPU_SCS_NVIC_ISPR0_SETPEND22 0x00400000 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_BITN 22 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_M 0x00400000 +#define CPU_SCS_NVIC_ISPR0_SETPEND22_S 22 // Field: [21] SETPEND21 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND21 0x00200000 -#define CPU_SCS_NVIC_ISPR0_SETPEND21_BITN 21 -#define CPU_SCS_NVIC_ISPR0_SETPEND21_M 0x00200000 -#define CPU_SCS_NVIC_ISPR0_SETPEND21_S 21 +#define CPU_SCS_NVIC_ISPR0_SETPEND21 0x00200000 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_BITN 21 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_M 0x00200000 +#define CPU_SCS_NVIC_ISPR0_SETPEND21_S 21 // Field: [20] SETPEND20 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND20 0x00100000 -#define CPU_SCS_NVIC_ISPR0_SETPEND20_BITN 20 -#define CPU_SCS_NVIC_ISPR0_SETPEND20_M 0x00100000 -#define CPU_SCS_NVIC_ISPR0_SETPEND20_S 20 +#define CPU_SCS_NVIC_ISPR0_SETPEND20 0x00100000 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_BITN 20 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_M 0x00100000 +#define CPU_SCS_NVIC_ISPR0_SETPEND20_S 20 // Field: [19] SETPEND19 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND19 0x00080000 -#define CPU_SCS_NVIC_ISPR0_SETPEND19_BITN 19 -#define CPU_SCS_NVIC_ISPR0_SETPEND19_M 0x00080000 -#define CPU_SCS_NVIC_ISPR0_SETPEND19_S 19 +#define CPU_SCS_NVIC_ISPR0_SETPEND19 0x00080000 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_BITN 19 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_M 0x00080000 +#define CPU_SCS_NVIC_ISPR0_SETPEND19_S 19 // Field: [18] SETPEND18 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND18 0x00040000 -#define CPU_SCS_NVIC_ISPR0_SETPEND18_BITN 18 -#define CPU_SCS_NVIC_ISPR0_SETPEND18_M 0x00040000 -#define CPU_SCS_NVIC_ISPR0_SETPEND18_S 18 +#define CPU_SCS_NVIC_ISPR0_SETPEND18 0x00040000 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_BITN 18 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_M 0x00040000 +#define CPU_SCS_NVIC_ISPR0_SETPEND18_S 18 // Field: [17] SETPEND17 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND17 0x00020000 -#define CPU_SCS_NVIC_ISPR0_SETPEND17_BITN 17 -#define CPU_SCS_NVIC_ISPR0_SETPEND17_M 0x00020000 -#define CPU_SCS_NVIC_ISPR0_SETPEND17_S 17 +#define CPU_SCS_NVIC_ISPR0_SETPEND17 0x00020000 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_BITN 17 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_M 0x00020000 +#define CPU_SCS_NVIC_ISPR0_SETPEND17_S 17 // Field: [16] SETPEND16 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND16 0x00010000 -#define CPU_SCS_NVIC_ISPR0_SETPEND16_BITN 16 -#define CPU_SCS_NVIC_ISPR0_SETPEND16_M 0x00010000 -#define CPU_SCS_NVIC_ISPR0_SETPEND16_S 16 +#define CPU_SCS_NVIC_ISPR0_SETPEND16 0x00010000 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_BITN 16 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_M 0x00010000 +#define CPU_SCS_NVIC_ISPR0_SETPEND16_S 16 // Field: [15] SETPEND15 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND15 0x00008000 -#define CPU_SCS_NVIC_ISPR0_SETPEND15_BITN 15 -#define CPU_SCS_NVIC_ISPR0_SETPEND15_M 0x00008000 -#define CPU_SCS_NVIC_ISPR0_SETPEND15_S 15 +#define CPU_SCS_NVIC_ISPR0_SETPEND15 0x00008000 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_BITN 15 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_M 0x00008000 +#define CPU_SCS_NVIC_ISPR0_SETPEND15_S 15 // Field: [14] SETPEND14 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND14 0x00004000 -#define CPU_SCS_NVIC_ISPR0_SETPEND14_BITN 14 -#define CPU_SCS_NVIC_ISPR0_SETPEND14_M 0x00004000 -#define CPU_SCS_NVIC_ISPR0_SETPEND14_S 14 +#define CPU_SCS_NVIC_ISPR0_SETPEND14 0x00004000 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_BITN 14 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_M 0x00004000 +#define CPU_SCS_NVIC_ISPR0_SETPEND14_S 14 // Field: [13] SETPEND13 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND13 0x00002000 -#define CPU_SCS_NVIC_ISPR0_SETPEND13_BITN 13 -#define CPU_SCS_NVIC_ISPR0_SETPEND13_M 0x00002000 -#define CPU_SCS_NVIC_ISPR0_SETPEND13_S 13 +#define CPU_SCS_NVIC_ISPR0_SETPEND13 0x00002000 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_BITN 13 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_M 0x00002000 +#define CPU_SCS_NVIC_ISPR0_SETPEND13_S 13 // Field: [12] SETPEND12 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND12 0x00001000 -#define CPU_SCS_NVIC_ISPR0_SETPEND12_BITN 12 -#define CPU_SCS_NVIC_ISPR0_SETPEND12_M 0x00001000 -#define CPU_SCS_NVIC_ISPR0_SETPEND12_S 12 +#define CPU_SCS_NVIC_ISPR0_SETPEND12 0x00001000 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_BITN 12 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_M 0x00001000 +#define CPU_SCS_NVIC_ISPR0_SETPEND12_S 12 // Field: [11] SETPEND11 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND11 0x00000800 -#define CPU_SCS_NVIC_ISPR0_SETPEND11_BITN 11 -#define CPU_SCS_NVIC_ISPR0_SETPEND11_M 0x00000800 -#define CPU_SCS_NVIC_ISPR0_SETPEND11_S 11 +#define CPU_SCS_NVIC_ISPR0_SETPEND11 0x00000800 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_BITN 11 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_M 0x00000800 +#define CPU_SCS_NVIC_ISPR0_SETPEND11_S 11 // Field: [10] SETPEND10 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND10 0x00000400 -#define CPU_SCS_NVIC_ISPR0_SETPEND10_BITN 10 -#define CPU_SCS_NVIC_ISPR0_SETPEND10_M 0x00000400 -#define CPU_SCS_NVIC_ISPR0_SETPEND10_S 10 +#define CPU_SCS_NVIC_ISPR0_SETPEND10 0x00000400 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_BITN 10 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_M 0x00000400 +#define CPU_SCS_NVIC_ISPR0_SETPEND10_S 10 // Field: [9] SETPEND9 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND9 0x00000200 -#define CPU_SCS_NVIC_ISPR0_SETPEND9_BITN 9 -#define CPU_SCS_NVIC_ISPR0_SETPEND9_M 0x00000200 -#define CPU_SCS_NVIC_ISPR0_SETPEND9_S 9 +#define CPU_SCS_NVIC_ISPR0_SETPEND9 0x00000200 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_BITN 9 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_M 0x00000200 +#define CPU_SCS_NVIC_ISPR0_SETPEND9_S 9 // Field: [8] SETPEND8 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND8 0x00000100 -#define CPU_SCS_NVIC_ISPR0_SETPEND8_BITN 8 -#define CPU_SCS_NVIC_ISPR0_SETPEND8_M 0x00000100 -#define CPU_SCS_NVIC_ISPR0_SETPEND8_S 8 +#define CPU_SCS_NVIC_ISPR0_SETPEND8 0x00000100 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_BITN 8 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_M 0x00000100 +#define CPU_SCS_NVIC_ISPR0_SETPEND8_S 8 // Field: [7] SETPEND7 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND7 0x00000080 -#define CPU_SCS_NVIC_ISPR0_SETPEND7_BITN 7 -#define CPU_SCS_NVIC_ISPR0_SETPEND7_M 0x00000080 -#define CPU_SCS_NVIC_ISPR0_SETPEND7_S 7 +#define CPU_SCS_NVIC_ISPR0_SETPEND7 0x00000080 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_BITN 7 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_M 0x00000080 +#define CPU_SCS_NVIC_ISPR0_SETPEND7_S 7 // Field: [6] SETPEND6 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND6 0x00000040 -#define CPU_SCS_NVIC_ISPR0_SETPEND6_BITN 6 -#define CPU_SCS_NVIC_ISPR0_SETPEND6_M 0x00000040 -#define CPU_SCS_NVIC_ISPR0_SETPEND6_S 6 +#define CPU_SCS_NVIC_ISPR0_SETPEND6 0x00000040 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_BITN 6 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_M 0x00000040 +#define CPU_SCS_NVIC_ISPR0_SETPEND6_S 6 // Field: [5] SETPEND5 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND5 0x00000020 -#define CPU_SCS_NVIC_ISPR0_SETPEND5_BITN 5 -#define CPU_SCS_NVIC_ISPR0_SETPEND5_M 0x00000020 -#define CPU_SCS_NVIC_ISPR0_SETPEND5_S 5 +#define CPU_SCS_NVIC_ISPR0_SETPEND5 0x00000020 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_BITN 5 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_M 0x00000020 +#define CPU_SCS_NVIC_ISPR0_SETPEND5_S 5 // Field: [4] SETPEND4 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND4 0x00000010 -#define CPU_SCS_NVIC_ISPR0_SETPEND4_BITN 4 -#define CPU_SCS_NVIC_ISPR0_SETPEND4_M 0x00000010 -#define CPU_SCS_NVIC_ISPR0_SETPEND4_S 4 +#define CPU_SCS_NVIC_ISPR0_SETPEND4 0x00000010 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_BITN 4 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_M 0x00000010 +#define CPU_SCS_NVIC_ISPR0_SETPEND4_S 4 // Field: [3] SETPEND3 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND3 0x00000008 -#define CPU_SCS_NVIC_ISPR0_SETPEND3_BITN 3 -#define CPU_SCS_NVIC_ISPR0_SETPEND3_M 0x00000008 -#define CPU_SCS_NVIC_ISPR0_SETPEND3_S 3 +#define CPU_SCS_NVIC_ISPR0_SETPEND3 0x00000008 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_BITN 3 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_M 0x00000008 +#define CPU_SCS_NVIC_ISPR0_SETPEND3_S 3 // Field: [2] SETPEND2 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND2 0x00000004 -#define CPU_SCS_NVIC_ISPR0_SETPEND2_BITN 2 -#define CPU_SCS_NVIC_ISPR0_SETPEND2_M 0x00000004 -#define CPU_SCS_NVIC_ISPR0_SETPEND2_S 2 +#define CPU_SCS_NVIC_ISPR0_SETPEND2 0x00000004 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_BITN 2 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_M 0x00000004 +#define CPU_SCS_NVIC_ISPR0_SETPEND2_S 2 // Field: [1] SETPEND1 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND1 0x00000002 -#define CPU_SCS_NVIC_ISPR0_SETPEND1_BITN 1 -#define CPU_SCS_NVIC_ISPR0_SETPEND1_M 0x00000002 -#define CPU_SCS_NVIC_ISPR0_SETPEND1_S 1 +#define CPU_SCS_NVIC_ISPR0_SETPEND1 0x00000002 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_BITN 1 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_M 0x00000002 +#define CPU_SCS_NVIC_ISPR0_SETPEND1_S 1 // Field: [0] SETPEND0 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND0 0x00000001 -#define CPU_SCS_NVIC_ISPR0_SETPEND0_BITN 0 -#define CPU_SCS_NVIC_ISPR0_SETPEND0_M 0x00000001 -#define CPU_SCS_NVIC_ISPR0_SETPEND0_S 0 +#define CPU_SCS_NVIC_ISPR0_SETPEND0 0x00000001 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_BITN 0 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_M 0x00000001 +#define CPU_SCS_NVIC_ISPR0_SETPEND0_S 0 //***************************************************************************** // @@ -1427,20 +1427,20 @@ // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR1_SETPEND33 0x00000002 -#define CPU_SCS_NVIC_ISPR1_SETPEND33_BITN 1 -#define CPU_SCS_NVIC_ISPR1_SETPEND33_M 0x00000002 -#define CPU_SCS_NVIC_ISPR1_SETPEND33_S 1 +#define CPU_SCS_NVIC_ISPR1_SETPEND33 0x00000002 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_BITN 1 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_M 0x00000002 +#define CPU_SCS_NVIC_ISPR1_SETPEND33_S 1 // Field: [0] SETPEND32 // // Writing 0 to this bit has no effect, writing 1 to this bit pends the // interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit // returns its current state. -#define CPU_SCS_NVIC_ISPR1_SETPEND32 0x00000001 -#define CPU_SCS_NVIC_ISPR1_SETPEND32_BITN 0 -#define CPU_SCS_NVIC_ISPR1_SETPEND32_M 0x00000001 -#define CPU_SCS_NVIC_ISPR1_SETPEND32_S 0 +#define CPU_SCS_NVIC_ISPR1_SETPEND32 0x00000001 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_BITN 0 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_M 0x00000001 +#define CPU_SCS_NVIC_ISPR1_SETPEND32_S 0 //***************************************************************************** // @@ -1452,320 +1452,320 @@ // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND31 0x80000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND31_BITN 31 -#define CPU_SCS_NVIC_ICPR0_CLRPEND31_M 0x80000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND31_S 31 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31 0x80000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_BITN 31 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_M 0x80000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND31_S 31 // Field: [30] CLRPEND30 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND30 0x40000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND30_BITN 30 -#define CPU_SCS_NVIC_ICPR0_CLRPEND30_M 0x40000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND30_S 30 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30 0x40000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_BITN 30 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_M 0x40000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND30_S 30 // Field: [29] CLRPEND29 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND29 0x20000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND29_BITN 29 -#define CPU_SCS_NVIC_ICPR0_CLRPEND29_M 0x20000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND29_S 29 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29 0x20000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_BITN 29 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_M 0x20000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND29_S 29 // Field: [28] CLRPEND28 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND28 0x10000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND28_BITN 28 -#define CPU_SCS_NVIC_ICPR0_CLRPEND28_M 0x10000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND28_S 28 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28 0x10000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_BITN 28 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_M 0x10000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND28_S 28 // Field: [27] CLRPEND27 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND27 0x08000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND27_BITN 27 -#define CPU_SCS_NVIC_ICPR0_CLRPEND27_M 0x08000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND27_S 27 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27 0x08000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_BITN 27 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_M 0x08000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND27_S 27 // Field: [26] CLRPEND26 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND26 0x04000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND26_BITN 26 -#define CPU_SCS_NVIC_ICPR0_CLRPEND26_M 0x04000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND26_S 26 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26 0x04000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_BITN 26 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_M 0x04000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND26_S 26 // Field: [25] CLRPEND25 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND25 0x02000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND25_BITN 25 -#define CPU_SCS_NVIC_ICPR0_CLRPEND25_M 0x02000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND25_S 25 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25 0x02000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_BITN 25 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_M 0x02000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND25_S 25 // Field: [24] CLRPEND24 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND24 0x01000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND24_BITN 24 -#define CPU_SCS_NVIC_ICPR0_CLRPEND24_M 0x01000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND24_S 24 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24 0x01000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_BITN 24 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_M 0x01000000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND24_S 24 // Field: [23] CLRPEND23 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND23 0x00800000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND23_BITN 23 -#define CPU_SCS_NVIC_ICPR0_CLRPEND23_M 0x00800000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND23_S 23 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23 0x00800000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_BITN 23 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_M 0x00800000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND23_S 23 // Field: [22] CLRPEND22 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND22 0x00400000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND22_BITN 22 -#define CPU_SCS_NVIC_ICPR0_CLRPEND22_M 0x00400000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND22_S 22 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22 0x00400000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_BITN 22 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_M 0x00400000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND22_S 22 // Field: [21] CLRPEND21 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND21 0x00200000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND21_BITN 21 -#define CPU_SCS_NVIC_ICPR0_CLRPEND21_M 0x00200000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND21_S 21 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21 0x00200000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_BITN 21 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_M 0x00200000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND21_S 21 // Field: [20] CLRPEND20 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND20 0x00100000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND20_BITN 20 -#define CPU_SCS_NVIC_ICPR0_CLRPEND20_M 0x00100000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND20_S 20 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20 0x00100000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_BITN 20 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_M 0x00100000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND20_S 20 // Field: [19] CLRPEND19 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND19 0x00080000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND19_BITN 19 -#define CPU_SCS_NVIC_ICPR0_CLRPEND19_M 0x00080000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND19_S 19 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19 0x00080000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_BITN 19 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_M 0x00080000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND19_S 19 // Field: [18] CLRPEND18 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND18 0x00040000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND18_BITN 18 -#define CPU_SCS_NVIC_ICPR0_CLRPEND18_M 0x00040000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND18_S 18 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18 0x00040000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_BITN 18 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_M 0x00040000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND18_S 18 // Field: [17] CLRPEND17 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND17 0x00020000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND17_BITN 17 -#define CPU_SCS_NVIC_ICPR0_CLRPEND17_M 0x00020000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND17_S 17 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17 0x00020000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_BITN 17 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_M 0x00020000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND17_S 17 // Field: [16] CLRPEND16 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND16 0x00010000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND16_BITN 16 -#define CPU_SCS_NVIC_ICPR0_CLRPEND16_M 0x00010000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND16_S 16 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16 0x00010000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_BITN 16 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_M 0x00010000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND16_S 16 // Field: [15] CLRPEND15 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND15 0x00008000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND15_BITN 15 -#define CPU_SCS_NVIC_ICPR0_CLRPEND15_M 0x00008000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND15_S 15 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15 0x00008000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_BITN 15 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_M 0x00008000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND15_S 15 // Field: [14] CLRPEND14 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND14 0x00004000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND14_BITN 14 -#define CPU_SCS_NVIC_ICPR0_CLRPEND14_M 0x00004000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND14_S 14 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14 0x00004000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_BITN 14 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_M 0x00004000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND14_S 14 // Field: [13] CLRPEND13 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND13 0x00002000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND13_BITN 13 -#define CPU_SCS_NVIC_ICPR0_CLRPEND13_M 0x00002000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND13_S 13 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13 0x00002000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_BITN 13 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_M 0x00002000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND13_S 13 // Field: [12] CLRPEND12 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND12 0x00001000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND12_BITN 12 -#define CPU_SCS_NVIC_ICPR0_CLRPEND12_M 0x00001000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND12_S 12 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12 0x00001000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_BITN 12 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_M 0x00001000 +#define CPU_SCS_NVIC_ICPR0_CLRPEND12_S 12 // Field: [11] CLRPEND11 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND11 0x00000800 -#define CPU_SCS_NVIC_ICPR0_CLRPEND11_BITN 11 -#define CPU_SCS_NVIC_ICPR0_CLRPEND11_M 0x00000800 -#define CPU_SCS_NVIC_ICPR0_CLRPEND11_S 11 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11 0x00000800 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_BITN 11 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_M 0x00000800 +#define CPU_SCS_NVIC_ICPR0_CLRPEND11_S 11 // Field: [10] CLRPEND10 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND10 0x00000400 -#define CPU_SCS_NVIC_ICPR0_CLRPEND10_BITN 10 -#define CPU_SCS_NVIC_ICPR0_CLRPEND10_M 0x00000400 -#define CPU_SCS_NVIC_ICPR0_CLRPEND10_S 10 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10 0x00000400 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_BITN 10 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_M 0x00000400 +#define CPU_SCS_NVIC_ICPR0_CLRPEND10_S 10 // Field: [9] CLRPEND9 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND9 0x00000200 -#define CPU_SCS_NVIC_ICPR0_CLRPEND9_BITN 9 -#define CPU_SCS_NVIC_ICPR0_CLRPEND9_M 0x00000200 -#define CPU_SCS_NVIC_ICPR0_CLRPEND9_S 9 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9 0x00000200 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_BITN 9 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_M 0x00000200 +#define CPU_SCS_NVIC_ICPR0_CLRPEND9_S 9 // Field: [8] CLRPEND8 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND8 0x00000100 -#define CPU_SCS_NVIC_ICPR0_CLRPEND8_BITN 8 -#define CPU_SCS_NVIC_ICPR0_CLRPEND8_M 0x00000100 -#define CPU_SCS_NVIC_ICPR0_CLRPEND8_S 8 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8 0x00000100 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_BITN 8 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_M 0x00000100 +#define CPU_SCS_NVIC_ICPR0_CLRPEND8_S 8 // Field: [7] CLRPEND7 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND7 0x00000080 -#define CPU_SCS_NVIC_ICPR0_CLRPEND7_BITN 7 -#define CPU_SCS_NVIC_ICPR0_CLRPEND7_M 0x00000080 -#define CPU_SCS_NVIC_ICPR0_CLRPEND7_S 7 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7 0x00000080 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_BITN 7 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_M 0x00000080 +#define CPU_SCS_NVIC_ICPR0_CLRPEND7_S 7 // Field: [6] CLRPEND6 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND6 0x00000040 -#define CPU_SCS_NVIC_ICPR0_CLRPEND6_BITN 6 -#define CPU_SCS_NVIC_ICPR0_CLRPEND6_M 0x00000040 -#define CPU_SCS_NVIC_ICPR0_CLRPEND6_S 6 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6 0x00000040 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_BITN 6 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_M 0x00000040 +#define CPU_SCS_NVIC_ICPR0_CLRPEND6_S 6 // Field: [5] CLRPEND5 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND5 0x00000020 -#define CPU_SCS_NVIC_ICPR0_CLRPEND5_BITN 5 -#define CPU_SCS_NVIC_ICPR0_CLRPEND5_M 0x00000020 -#define CPU_SCS_NVIC_ICPR0_CLRPEND5_S 5 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5 0x00000020 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_BITN 5 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_M 0x00000020 +#define CPU_SCS_NVIC_ICPR0_CLRPEND5_S 5 // Field: [4] CLRPEND4 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND4 0x00000010 -#define CPU_SCS_NVIC_ICPR0_CLRPEND4_BITN 4 -#define CPU_SCS_NVIC_ICPR0_CLRPEND4_M 0x00000010 -#define CPU_SCS_NVIC_ICPR0_CLRPEND4_S 4 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4 0x00000010 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_BITN 4 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_M 0x00000010 +#define CPU_SCS_NVIC_ICPR0_CLRPEND4_S 4 // Field: [3] CLRPEND3 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND3 0x00000008 -#define CPU_SCS_NVIC_ICPR0_CLRPEND3_BITN 3 -#define CPU_SCS_NVIC_ICPR0_CLRPEND3_M 0x00000008 -#define CPU_SCS_NVIC_ICPR0_CLRPEND3_S 3 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3 0x00000008 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_BITN 3 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_M 0x00000008 +#define CPU_SCS_NVIC_ICPR0_CLRPEND3_S 3 // Field: [2] CLRPEND2 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND2 0x00000004 -#define CPU_SCS_NVIC_ICPR0_CLRPEND2_BITN 2 -#define CPU_SCS_NVIC_ICPR0_CLRPEND2_M 0x00000004 -#define CPU_SCS_NVIC_ICPR0_CLRPEND2_S 2 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2 0x00000004 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_BITN 2 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_M 0x00000004 +#define CPU_SCS_NVIC_ICPR0_CLRPEND2_S 2 // Field: [1] CLRPEND1 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND1 0x00000002 -#define CPU_SCS_NVIC_ICPR0_CLRPEND1_BITN 1 -#define CPU_SCS_NVIC_ICPR0_CLRPEND1_M 0x00000002 -#define CPU_SCS_NVIC_ICPR0_CLRPEND1_S 1 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1 0x00000002 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_BITN 1 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_M 0x00000002 +#define CPU_SCS_NVIC_ICPR0_CLRPEND1_S 1 // Field: [0] CLRPEND0 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND0 0x00000001 -#define CPU_SCS_NVIC_ICPR0_CLRPEND0_BITN 0 -#define CPU_SCS_NVIC_ICPR0_CLRPEND0_M 0x00000001 -#define CPU_SCS_NVIC_ICPR0_CLRPEND0_S 0 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0 0x00000001 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_BITN 0 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_M 0x00000001 +#define CPU_SCS_NVIC_ICPR0_CLRPEND0_S 0 //***************************************************************************** // @@ -1777,20 +1777,20 @@ // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR1_CLRPEND33 0x00000002 -#define CPU_SCS_NVIC_ICPR1_CLRPEND33_BITN 1 -#define CPU_SCS_NVIC_ICPR1_CLRPEND33_M 0x00000002 -#define CPU_SCS_NVIC_ICPR1_CLRPEND33_S 1 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33 0x00000002 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_BITN 1 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_M 0x00000002 +#define CPU_SCS_NVIC_ICPR1_CLRPEND33_S 1 // Field: [0] CLRPEND32 // // Writing 0 to this bit has no effect, writing 1 to this bit clears the // corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). // Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR1_CLRPEND32 0x00000001 -#define CPU_SCS_NVIC_ICPR1_CLRPEND32_BITN 0 -#define CPU_SCS_NVIC_ICPR1_CLRPEND32_M 0x00000001 -#define CPU_SCS_NVIC_ICPR1_CLRPEND32_S 0 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32 0x00000001 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_BITN 0 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_M 0x00000001 +#define CPU_SCS_NVIC_ICPR1_CLRPEND32_S 0 //***************************************************************************** // @@ -1802,320 +1802,320 @@ // Reading 0 from this bit implies that interrupt line 31 is not active. // Reading 1 from this bit implies that the interrupt line 31 is active (See // EVENT:CPUIRQSEL31.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE31 0x80000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE31_BITN 31 -#define CPU_SCS_NVIC_IABR0_ACTIVE31_M 0x80000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE31_S 31 +#define CPU_SCS_NVIC_IABR0_ACTIVE31 0x80000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_BITN 31 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_M 0x80000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE31_S 31 // Field: [30] ACTIVE30 // // Reading 0 from this bit implies that interrupt line 30 is not active. // Reading 1 from this bit implies that the interrupt line 30 is active (See // EVENT:CPUIRQSEL30.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE30 0x40000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE30_BITN 30 -#define CPU_SCS_NVIC_IABR0_ACTIVE30_M 0x40000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE30_S 30 +#define CPU_SCS_NVIC_IABR0_ACTIVE30 0x40000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_BITN 30 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_M 0x40000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE30_S 30 // Field: [29] ACTIVE29 // // Reading 0 from this bit implies that interrupt line 29 is not active. // Reading 1 from this bit implies that the interrupt line 29 is active (See // EVENT:CPUIRQSEL29.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE29 0x20000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE29_BITN 29 -#define CPU_SCS_NVIC_IABR0_ACTIVE29_M 0x20000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE29_S 29 +#define CPU_SCS_NVIC_IABR0_ACTIVE29 0x20000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_BITN 29 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_M 0x20000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE29_S 29 // Field: [28] ACTIVE28 // // Reading 0 from this bit implies that interrupt line 28 is not active. // Reading 1 from this bit implies that the interrupt line 28 is active (See // EVENT:CPUIRQSEL28.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE28 0x10000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE28_BITN 28 -#define CPU_SCS_NVIC_IABR0_ACTIVE28_M 0x10000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE28_S 28 +#define CPU_SCS_NVIC_IABR0_ACTIVE28 0x10000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_BITN 28 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_M 0x10000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE28_S 28 // Field: [27] ACTIVE27 // // Reading 0 from this bit implies that interrupt line 27 is not active. // Reading 1 from this bit implies that the interrupt line 27 is active (See // EVENT:CPUIRQSEL27.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE27 0x08000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE27_BITN 27 -#define CPU_SCS_NVIC_IABR0_ACTIVE27_M 0x08000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE27_S 27 +#define CPU_SCS_NVIC_IABR0_ACTIVE27 0x08000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_BITN 27 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_M 0x08000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE27_S 27 // Field: [26] ACTIVE26 // // Reading 0 from this bit implies that interrupt line 26 is not active. // Reading 1 from this bit implies that the interrupt line 26 is active (See // EVENT:CPUIRQSEL26.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE26 0x04000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE26_BITN 26 -#define CPU_SCS_NVIC_IABR0_ACTIVE26_M 0x04000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE26_S 26 +#define CPU_SCS_NVIC_IABR0_ACTIVE26 0x04000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_BITN 26 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_M 0x04000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE26_S 26 // Field: [25] ACTIVE25 // // Reading 0 from this bit implies that interrupt line 25 is not active. // Reading 1 from this bit implies that the interrupt line 25 is active (See // EVENT:CPUIRQSEL25.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE25 0x02000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE25_BITN 25 -#define CPU_SCS_NVIC_IABR0_ACTIVE25_M 0x02000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE25_S 25 +#define CPU_SCS_NVIC_IABR0_ACTIVE25 0x02000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_BITN 25 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_M 0x02000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE25_S 25 // Field: [24] ACTIVE24 // // Reading 0 from this bit implies that interrupt line 24 is not active. // Reading 1 from this bit implies that the interrupt line 24 is active (See // EVENT:CPUIRQSEL24.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE24 0x01000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE24_BITN 24 -#define CPU_SCS_NVIC_IABR0_ACTIVE24_M 0x01000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE24_S 24 +#define CPU_SCS_NVIC_IABR0_ACTIVE24 0x01000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_BITN 24 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_M 0x01000000 +#define CPU_SCS_NVIC_IABR0_ACTIVE24_S 24 // Field: [23] ACTIVE23 // // Reading 0 from this bit implies that interrupt line 23 is not active. // Reading 1 from this bit implies that the interrupt line 23 is active (See // EVENT:CPUIRQSEL23.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE23 0x00800000 -#define CPU_SCS_NVIC_IABR0_ACTIVE23_BITN 23 -#define CPU_SCS_NVIC_IABR0_ACTIVE23_M 0x00800000 -#define CPU_SCS_NVIC_IABR0_ACTIVE23_S 23 +#define CPU_SCS_NVIC_IABR0_ACTIVE23 0x00800000 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_BITN 23 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_M 0x00800000 +#define CPU_SCS_NVIC_IABR0_ACTIVE23_S 23 // Field: [22] ACTIVE22 // // Reading 0 from this bit implies that interrupt line 22 is not active. // Reading 1 from this bit implies that the interrupt line 22 is active (See // EVENT:CPUIRQSEL22.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE22 0x00400000 -#define CPU_SCS_NVIC_IABR0_ACTIVE22_BITN 22 -#define CPU_SCS_NVIC_IABR0_ACTIVE22_M 0x00400000 -#define CPU_SCS_NVIC_IABR0_ACTIVE22_S 22 +#define CPU_SCS_NVIC_IABR0_ACTIVE22 0x00400000 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_BITN 22 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_M 0x00400000 +#define CPU_SCS_NVIC_IABR0_ACTIVE22_S 22 // Field: [21] ACTIVE21 // // Reading 0 from this bit implies that interrupt line 21 is not active. // Reading 1 from this bit implies that the interrupt line 21 is active (See // EVENT:CPUIRQSEL21.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE21 0x00200000 -#define CPU_SCS_NVIC_IABR0_ACTIVE21_BITN 21 -#define CPU_SCS_NVIC_IABR0_ACTIVE21_M 0x00200000 -#define CPU_SCS_NVIC_IABR0_ACTIVE21_S 21 +#define CPU_SCS_NVIC_IABR0_ACTIVE21 0x00200000 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_BITN 21 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_M 0x00200000 +#define CPU_SCS_NVIC_IABR0_ACTIVE21_S 21 // Field: [20] ACTIVE20 // // Reading 0 from this bit implies that interrupt line 20 is not active. // Reading 1 from this bit implies that the interrupt line 20 is active (See // EVENT:CPUIRQSEL20.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE20 0x00100000 -#define CPU_SCS_NVIC_IABR0_ACTIVE20_BITN 20 -#define CPU_SCS_NVIC_IABR0_ACTIVE20_M 0x00100000 -#define CPU_SCS_NVIC_IABR0_ACTIVE20_S 20 +#define CPU_SCS_NVIC_IABR0_ACTIVE20 0x00100000 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_BITN 20 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_M 0x00100000 +#define CPU_SCS_NVIC_IABR0_ACTIVE20_S 20 // Field: [19] ACTIVE19 // // Reading 0 from this bit implies that interrupt line 19 is not active. // Reading 1 from this bit implies that the interrupt line 19 is active (See // EVENT:CPUIRQSEL19.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE19 0x00080000 -#define CPU_SCS_NVIC_IABR0_ACTIVE19_BITN 19 -#define CPU_SCS_NVIC_IABR0_ACTIVE19_M 0x00080000 -#define CPU_SCS_NVIC_IABR0_ACTIVE19_S 19 +#define CPU_SCS_NVIC_IABR0_ACTIVE19 0x00080000 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_BITN 19 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_M 0x00080000 +#define CPU_SCS_NVIC_IABR0_ACTIVE19_S 19 // Field: [18] ACTIVE18 // // Reading 0 from this bit implies that interrupt line 18 is not active. // Reading 1 from this bit implies that the interrupt line 18 is active (See // EVENT:CPUIRQSEL18.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE18 0x00040000 -#define CPU_SCS_NVIC_IABR0_ACTIVE18_BITN 18 -#define CPU_SCS_NVIC_IABR0_ACTIVE18_M 0x00040000 -#define CPU_SCS_NVIC_IABR0_ACTIVE18_S 18 +#define CPU_SCS_NVIC_IABR0_ACTIVE18 0x00040000 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_BITN 18 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_M 0x00040000 +#define CPU_SCS_NVIC_IABR0_ACTIVE18_S 18 // Field: [17] ACTIVE17 // // Reading 0 from this bit implies that interrupt line 17 is not active. // Reading 1 from this bit implies that the interrupt line 17 is active (See // EVENT:CPUIRQSEL17.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE17 0x00020000 -#define CPU_SCS_NVIC_IABR0_ACTIVE17_BITN 17 -#define CPU_SCS_NVIC_IABR0_ACTIVE17_M 0x00020000 -#define CPU_SCS_NVIC_IABR0_ACTIVE17_S 17 +#define CPU_SCS_NVIC_IABR0_ACTIVE17 0x00020000 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_BITN 17 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_M 0x00020000 +#define CPU_SCS_NVIC_IABR0_ACTIVE17_S 17 // Field: [16] ACTIVE16 // // Reading 0 from this bit implies that interrupt line 16 is not active. // Reading 1 from this bit implies that the interrupt line 16 is active (See // EVENT:CPUIRQSEL16.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE16 0x00010000 -#define CPU_SCS_NVIC_IABR0_ACTIVE16_BITN 16 -#define CPU_SCS_NVIC_IABR0_ACTIVE16_M 0x00010000 -#define CPU_SCS_NVIC_IABR0_ACTIVE16_S 16 +#define CPU_SCS_NVIC_IABR0_ACTIVE16 0x00010000 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_BITN 16 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_M 0x00010000 +#define CPU_SCS_NVIC_IABR0_ACTIVE16_S 16 // Field: [15] ACTIVE15 // // Reading 0 from this bit implies that interrupt line 15 is not active. // Reading 1 from this bit implies that the interrupt line 15 is active (See // EVENT:CPUIRQSEL15.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE15 0x00008000 -#define CPU_SCS_NVIC_IABR0_ACTIVE15_BITN 15 -#define CPU_SCS_NVIC_IABR0_ACTIVE15_M 0x00008000 -#define CPU_SCS_NVIC_IABR0_ACTIVE15_S 15 +#define CPU_SCS_NVIC_IABR0_ACTIVE15 0x00008000 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_BITN 15 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_M 0x00008000 +#define CPU_SCS_NVIC_IABR0_ACTIVE15_S 15 // Field: [14] ACTIVE14 // // Reading 0 from this bit implies that interrupt line 14 is not active. // Reading 1 from this bit implies that the interrupt line 14 is active (See // EVENT:CPUIRQSEL14.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE14 0x00004000 -#define CPU_SCS_NVIC_IABR0_ACTIVE14_BITN 14 -#define CPU_SCS_NVIC_IABR0_ACTIVE14_M 0x00004000 -#define CPU_SCS_NVIC_IABR0_ACTIVE14_S 14 +#define CPU_SCS_NVIC_IABR0_ACTIVE14 0x00004000 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_BITN 14 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_M 0x00004000 +#define CPU_SCS_NVIC_IABR0_ACTIVE14_S 14 // Field: [13] ACTIVE13 // // Reading 0 from this bit implies that interrupt line 13 is not active. // Reading 1 from this bit implies that the interrupt line 13 is active (See // EVENT:CPUIRQSEL13.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE13 0x00002000 -#define CPU_SCS_NVIC_IABR0_ACTIVE13_BITN 13 -#define CPU_SCS_NVIC_IABR0_ACTIVE13_M 0x00002000 -#define CPU_SCS_NVIC_IABR0_ACTIVE13_S 13 +#define CPU_SCS_NVIC_IABR0_ACTIVE13 0x00002000 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_BITN 13 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_M 0x00002000 +#define CPU_SCS_NVIC_IABR0_ACTIVE13_S 13 // Field: [12] ACTIVE12 // // Reading 0 from this bit implies that interrupt line 12 is not active. // Reading 1 from this bit implies that the interrupt line 12 is active (See // EVENT:CPUIRQSEL12.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE12 0x00001000 -#define CPU_SCS_NVIC_IABR0_ACTIVE12_BITN 12 -#define CPU_SCS_NVIC_IABR0_ACTIVE12_M 0x00001000 -#define CPU_SCS_NVIC_IABR0_ACTIVE12_S 12 +#define CPU_SCS_NVIC_IABR0_ACTIVE12 0x00001000 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_BITN 12 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_M 0x00001000 +#define CPU_SCS_NVIC_IABR0_ACTIVE12_S 12 // Field: [11] ACTIVE11 // // Reading 0 from this bit implies that interrupt line 11 is not active. // Reading 1 from this bit implies that the interrupt line 11 is active (See // EVENT:CPUIRQSEL11.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE11 0x00000800 -#define CPU_SCS_NVIC_IABR0_ACTIVE11_BITN 11 -#define CPU_SCS_NVIC_IABR0_ACTIVE11_M 0x00000800 -#define CPU_SCS_NVIC_IABR0_ACTIVE11_S 11 +#define CPU_SCS_NVIC_IABR0_ACTIVE11 0x00000800 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_BITN 11 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_M 0x00000800 +#define CPU_SCS_NVIC_IABR0_ACTIVE11_S 11 // Field: [10] ACTIVE10 // // Reading 0 from this bit implies that interrupt line 10 is not active. // Reading 1 from this bit implies that the interrupt line 10 is active (See // EVENT:CPUIRQSEL10.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE10 0x00000400 -#define CPU_SCS_NVIC_IABR0_ACTIVE10_BITN 10 -#define CPU_SCS_NVIC_IABR0_ACTIVE10_M 0x00000400 -#define CPU_SCS_NVIC_IABR0_ACTIVE10_S 10 +#define CPU_SCS_NVIC_IABR0_ACTIVE10 0x00000400 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_BITN 10 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_M 0x00000400 +#define CPU_SCS_NVIC_IABR0_ACTIVE10_S 10 // Field: [9] ACTIVE9 // // Reading 0 from this bit implies that interrupt line 9 is not active. Reading // 1 from this bit implies that the interrupt line 9 is active (See // EVENT:CPUIRQSEL9.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE9 0x00000200 -#define CPU_SCS_NVIC_IABR0_ACTIVE9_BITN 9 -#define CPU_SCS_NVIC_IABR0_ACTIVE9_M 0x00000200 -#define CPU_SCS_NVIC_IABR0_ACTIVE9_S 9 +#define CPU_SCS_NVIC_IABR0_ACTIVE9 0x00000200 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_BITN 9 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_M 0x00000200 +#define CPU_SCS_NVIC_IABR0_ACTIVE9_S 9 // Field: [8] ACTIVE8 // // Reading 0 from this bit implies that interrupt line 8 is not active. Reading // 1 from this bit implies that the interrupt line 8 is active (See // EVENT:CPUIRQSEL8.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE8 0x00000100 -#define CPU_SCS_NVIC_IABR0_ACTIVE8_BITN 8 -#define CPU_SCS_NVIC_IABR0_ACTIVE8_M 0x00000100 -#define CPU_SCS_NVIC_IABR0_ACTIVE8_S 8 +#define CPU_SCS_NVIC_IABR0_ACTIVE8 0x00000100 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_BITN 8 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_M 0x00000100 +#define CPU_SCS_NVIC_IABR0_ACTIVE8_S 8 // Field: [7] ACTIVE7 // // Reading 0 from this bit implies that interrupt line 7 is not active. Reading // 1 from this bit implies that the interrupt line 7 is active (See // EVENT:CPUIRQSEL7.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE7 0x00000080 -#define CPU_SCS_NVIC_IABR0_ACTIVE7_BITN 7 -#define CPU_SCS_NVIC_IABR0_ACTIVE7_M 0x00000080 -#define CPU_SCS_NVIC_IABR0_ACTIVE7_S 7 +#define CPU_SCS_NVIC_IABR0_ACTIVE7 0x00000080 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_BITN 7 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_M 0x00000080 +#define CPU_SCS_NVIC_IABR0_ACTIVE7_S 7 // Field: [6] ACTIVE6 // // Reading 0 from this bit implies that interrupt line 6 is not active. Reading // 1 from this bit implies that the interrupt line 6 is active (See // EVENT:CPUIRQSEL6.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE6 0x00000040 -#define CPU_SCS_NVIC_IABR0_ACTIVE6_BITN 6 -#define CPU_SCS_NVIC_IABR0_ACTIVE6_M 0x00000040 -#define CPU_SCS_NVIC_IABR0_ACTIVE6_S 6 +#define CPU_SCS_NVIC_IABR0_ACTIVE6 0x00000040 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_BITN 6 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_M 0x00000040 +#define CPU_SCS_NVIC_IABR0_ACTIVE6_S 6 // Field: [5] ACTIVE5 // // Reading 0 from this bit implies that interrupt line 5 is not active. Reading // 1 from this bit implies that the interrupt line 5 is active (See // EVENT:CPUIRQSEL5.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE5 0x00000020 -#define CPU_SCS_NVIC_IABR0_ACTIVE5_BITN 5 -#define CPU_SCS_NVIC_IABR0_ACTIVE5_M 0x00000020 -#define CPU_SCS_NVIC_IABR0_ACTIVE5_S 5 +#define CPU_SCS_NVIC_IABR0_ACTIVE5 0x00000020 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_BITN 5 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_M 0x00000020 +#define CPU_SCS_NVIC_IABR0_ACTIVE5_S 5 // Field: [4] ACTIVE4 // // Reading 0 from this bit implies that interrupt line 4 is not active. Reading // 1 from this bit implies that the interrupt line 4 is active (See // EVENT:CPUIRQSEL4.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE4 0x00000010 -#define CPU_SCS_NVIC_IABR0_ACTIVE4_BITN 4 -#define CPU_SCS_NVIC_IABR0_ACTIVE4_M 0x00000010 -#define CPU_SCS_NVIC_IABR0_ACTIVE4_S 4 +#define CPU_SCS_NVIC_IABR0_ACTIVE4 0x00000010 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_BITN 4 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_M 0x00000010 +#define CPU_SCS_NVIC_IABR0_ACTIVE4_S 4 // Field: [3] ACTIVE3 // // Reading 0 from this bit implies that interrupt line 3 is not active. Reading // 1 from this bit implies that the interrupt line 3 is active (See // EVENT:CPUIRQSEL3.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE3 0x00000008 -#define CPU_SCS_NVIC_IABR0_ACTIVE3_BITN 3 -#define CPU_SCS_NVIC_IABR0_ACTIVE3_M 0x00000008 -#define CPU_SCS_NVIC_IABR0_ACTIVE3_S 3 +#define CPU_SCS_NVIC_IABR0_ACTIVE3 0x00000008 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_BITN 3 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_M 0x00000008 +#define CPU_SCS_NVIC_IABR0_ACTIVE3_S 3 // Field: [2] ACTIVE2 // // Reading 0 from this bit implies that interrupt line 2 is not active. Reading // 1 from this bit implies that the interrupt line 2 is active (See // EVENT:CPUIRQSEL2.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE2 0x00000004 -#define CPU_SCS_NVIC_IABR0_ACTIVE2_BITN 2 -#define CPU_SCS_NVIC_IABR0_ACTIVE2_M 0x00000004 -#define CPU_SCS_NVIC_IABR0_ACTIVE2_S 2 +#define CPU_SCS_NVIC_IABR0_ACTIVE2 0x00000004 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_BITN 2 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_M 0x00000004 +#define CPU_SCS_NVIC_IABR0_ACTIVE2_S 2 // Field: [1] ACTIVE1 // // Reading 0 from this bit implies that interrupt line 1 is not active. Reading // 1 from this bit implies that the interrupt line 1 is active (See // EVENT:CPUIRQSEL1.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE1 0x00000002 -#define CPU_SCS_NVIC_IABR0_ACTIVE1_BITN 1 -#define CPU_SCS_NVIC_IABR0_ACTIVE1_M 0x00000002 -#define CPU_SCS_NVIC_IABR0_ACTIVE1_S 1 +#define CPU_SCS_NVIC_IABR0_ACTIVE1 0x00000002 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_BITN 1 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_M 0x00000002 +#define CPU_SCS_NVIC_IABR0_ACTIVE1_S 1 // Field: [0] ACTIVE0 // // Reading 0 from this bit implies that interrupt line 0 is not active. Reading // 1 from this bit implies that the interrupt line 0 is active (See // EVENT:CPUIRQSEL0.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE0 0x00000001 -#define CPU_SCS_NVIC_IABR0_ACTIVE0_BITN 0 -#define CPU_SCS_NVIC_IABR0_ACTIVE0_M 0x00000001 -#define CPU_SCS_NVIC_IABR0_ACTIVE0_S 0 +#define CPU_SCS_NVIC_IABR0_ACTIVE0 0x00000001 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_BITN 0 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_M 0x00000001 +#define CPU_SCS_NVIC_IABR0_ACTIVE0_S 0 //***************************************************************************** // @@ -2127,20 +2127,20 @@ // Reading 0 from this bit implies that interrupt line 33 is not active. // Reading 1 from this bit implies that the interrupt line 33 is active (See // EVENT:CPUIRQSEL33.EV for details). -#define CPU_SCS_NVIC_IABR1_ACTIVE33 0x00000002 -#define CPU_SCS_NVIC_IABR1_ACTIVE33_BITN 1 -#define CPU_SCS_NVIC_IABR1_ACTIVE33_M 0x00000002 -#define CPU_SCS_NVIC_IABR1_ACTIVE33_S 1 +#define CPU_SCS_NVIC_IABR1_ACTIVE33 0x00000002 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_BITN 1 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_M 0x00000002 +#define CPU_SCS_NVIC_IABR1_ACTIVE33_S 1 // Field: [0] ACTIVE32 // // Reading 0 from this bit implies that interrupt line 32 is not active. // Reading 1 from this bit implies that the interrupt line 32 is active (See // EVENT:CPUIRQSEL32.EV for details). -#define CPU_SCS_NVIC_IABR1_ACTIVE32 0x00000001 -#define CPU_SCS_NVIC_IABR1_ACTIVE32_BITN 0 -#define CPU_SCS_NVIC_IABR1_ACTIVE32_M 0x00000001 -#define CPU_SCS_NVIC_IABR1_ACTIVE32_S 0 +#define CPU_SCS_NVIC_IABR1_ACTIVE32 0x00000001 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_BITN 0 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_M 0x00000001 +#define CPU_SCS_NVIC_IABR1_ACTIVE32_S 0 //***************************************************************************** // @@ -2150,30 +2150,30 @@ // Field: [31:24] PRI_3 // // Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). -#define CPU_SCS_NVIC_IPR0_PRI_3_W 8 -#define CPU_SCS_NVIC_IPR0_PRI_3_M 0xFF000000 -#define CPU_SCS_NVIC_IPR0_PRI_3_S 24 +#define CPU_SCS_NVIC_IPR0_PRI_3_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_3_M 0xFF000000 +#define CPU_SCS_NVIC_IPR0_PRI_3_S 24 // Field: [23:16] PRI_2 // // Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). -#define CPU_SCS_NVIC_IPR0_PRI_2_W 8 -#define CPU_SCS_NVIC_IPR0_PRI_2_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR0_PRI_2_S 16 +#define CPU_SCS_NVIC_IPR0_PRI_2_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_2_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR0_PRI_2_S 16 // Field: [15:8] PRI_1 // // Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). -#define CPU_SCS_NVIC_IPR0_PRI_1_W 8 -#define CPU_SCS_NVIC_IPR0_PRI_1_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR0_PRI_1_S 8 +#define CPU_SCS_NVIC_IPR0_PRI_1_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_1_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR0_PRI_1_S 8 // Field: [7:0] PRI_0 // // Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). -#define CPU_SCS_NVIC_IPR0_PRI_0_W 8 -#define CPU_SCS_NVIC_IPR0_PRI_0_M 0x000000FF -#define CPU_SCS_NVIC_IPR0_PRI_0_S 0 +#define CPU_SCS_NVIC_IPR0_PRI_0_W 8 +#define CPU_SCS_NVIC_IPR0_PRI_0_M 0x000000FF +#define CPU_SCS_NVIC_IPR0_PRI_0_S 0 //***************************************************************************** // @@ -2183,30 +2183,30 @@ // Field: [31:24] PRI_7 // // Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). -#define CPU_SCS_NVIC_IPR1_PRI_7_W 8 -#define CPU_SCS_NVIC_IPR1_PRI_7_M 0xFF000000 -#define CPU_SCS_NVIC_IPR1_PRI_7_S 24 +#define CPU_SCS_NVIC_IPR1_PRI_7_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_7_M 0xFF000000 +#define CPU_SCS_NVIC_IPR1_PRI_7_S 24 // Field: [23:16] PRI_6 // // Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). -#define CPU_SCS_NVIC_IPR1_PRI_6_W 8 -#define CPU_SCS_NVIC_IPR1_PRI_6_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR1_PRI_6_S 16 +#define CPU_SCS_NVIC_IPR1_PRI_6_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_6_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR1_PRI_6_S 16 // Field: [15:8] PRI_5 // // Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). -#define CPU_SCS_NVIC_IPR1_PRI_5_W 8 -#define CPU_SCS_NVIC_IPR1_PRI_5_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR1_PRI_5_S 8 +#define CPU_SCS_NVIC_IPR1_PRI_5_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_5_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR1_PRI_5_S 8 // Field: [7:0] PRI_4 // // Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). -#define CPU_SCS_NVIC_IPR1_PRI_4_W 8 -#define CPU_SCS_NVIC_IPR1_PRI_4_M 0x000000FF -#define CPU_SCS_NVIC_IPR1_PRI_4_S 0 +#define CPU_SCS_NVIC_IPR1_PRI_4_W 8 +#define CPU_SCS_NVIC_IPR1_PRI_4_M 0x000000FF +#define CPU_SCS_NVIC_IPR1_PRI_4_S 0 //***************************************************************************** // @@ -2216,30 +2216,30 @@ // Field: [31:24] PRI_11 // // Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). -#define CPU_SCS_NVIC_IPR2_PRI_11_W 8 -#define CPU_SCS_NVIC_IPR2_PRI_11_M 0xFF000000 -#define CPU_SCS_NVIC_IPR2_PRI_11_S 24 +#define CPU_SCS_NVIC_IPR2_PRI_11_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_11_M 0xFF000000 +#define CPU_SCS_NVIC_IPR2_PRI_11_S 24 // Field: [23:16] PRI_10 // // Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). -#define CPU_SCS_NVIC_IPR2_PRI_10_W 8 -#define CPU_SCS_NVIC_IPR2_PRI_10_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR2_PRI_10_S 16 +#define CPU_SCS_NVIC_IPR2_PRI_10_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_10_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR2_PRI_10_S 16 // Field: [15:8] PRI_9 // // Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). -#define CPU_SCS_NVIC_IPR2_PRI_9_W 8 -#define CPU_SCS_NVIC_IPR2_PRI_9_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR2_PRI_9_S 8 +#define CPU_SCS_NVIC_IPR2_PRI_9_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_9_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR2_PRI_9_S 8 // Field: [7:0] PRI_8 // // Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). -#define CPU_SCS_NVIC_IPR2_PRI_8_W 8 -#define CPU_SCS_NVIC_IPR2_PRI_8_M 0x000000FF -#define CPU_SCS_NVIC_IPR2_PRI_8_S 0 +#define CPU_SCS_NVIC_IPR2_PRI_8_W 8 +#define CPU_SCS_NVIC_IPR2_PRI_8_M 0x000000FF +#define CPU_SCS_NVIC_IPR2_PRI_8_S 0 //***************************************************************************** // @@ -2249,30 +2249,30 @@ // Field: [31:24] PRI_15 // // Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). -#define CPU_SCS_NVIC_IPR3_PRI_15_W 8 -#define CPU_SCS_NVIC_IPR3_PRI_15_M 0xFF000000 -#define CPU_SCS_NVIC_IPR3_PRI_15_S 24 +#define CPU_SCS_NVIC_IPR3_PRI_15_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_15_M 0xFF000000 +#define CPU_SCS_NVIC_IPR3_PRI_15_S 24 // Field: [23:16] PRI_14 // // Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). -#define CPU_SCS_NVIC_IPR3_PRI_14_W 8 -#define CPU_SCS_NVIC_IPR3_PRI_14_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR3_PRI_14_S 16 +#define CPU_SCS_NVIC_IPR3_PRI_14_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_14_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR3_PRI_14_S 16 // Field: [15:8] PRI_13 // // Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). -#define CPU_SCS_NVIC_IPR3_PRI_13_W 8 -#define CPU_SCS_NVIC_IPR3_PRI_13_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR3_PRI_13_S 8 +#define CPU_SCS_NVIC_IPR3_PRI_13_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_13_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR3_PRI_13_S 8 // Field: [7:0] PRI_12 // // Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). -#define CPU_SCS_NVIC_IPR3_PRI_12_W 8 -#define CPU_SCS_NVIC_IPR3_PRI_12_M 0x000000FF -#define CPU_SCS_NVIC_IPR3_PRI_12_S 0 +#define CPU_SCS_NVIC_IPR3_PRI_12_W 8 +#define CPU_SCS_NVIC_IPR3_PRI_12_M 0x000000FF +#define CPU_SCS_NVIC_IPR3_PRI_12_S 0 //***************************************************************************** // @@ -2282,30 +2282,30 @@ // Field: [31:24] PRI_19 // // Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). -#define CPU_SCS_NVIC_IPR4_PRI_19_W 8 -#define CPU_SCS_NVIC_IPR4_PRI_19_M 0xFF000000 -#define CPU_SCS_NVIC_IPR4_PRI_19_S 24 +#define CPU_SCS_NVIC_IPR4_PRI_19_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_19_M 0xFF000000 +#define CPU_SCS_NVIC_IPR4_PRI_19_S 24 // Field: [23:16] PRI_18 // // Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). -#define CPU_SCS_NVIC_IPR4_PRI_18_W 8 -#define CPU_SCS_NVIC_IPR4_PRI_18_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR4_PRI_18_S 16 +#define CPU_SCS_NVIC_IPR4_PRI_18_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_18_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR4_PRI_18_S 16 // Field: [15:8] PRI_17 // // Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). -#define CPU_SCS_NVIC_IPR4_PRI_17_W 8 -#define CPU_SCS_NVIC_IPR4_PRI_17_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR4_PRI_17_S 8 +#define CPU_SCS_NVIC_IPR4_PRI_17_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_17_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR4_PRI_17_S 8 // Field: [7:0] PRI_16 // // Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). -#define CPU_SCS_NVIC_IPR4_PRI_16_W 8 -#define CPU_SCS_NVIC_IPR4_PRI_16_M 0x000000FF -#define CPU_SCS_NVIC_IPR4_PRI_16_S 0 +#define CPU_SCS_NVIC_IPR4_PRI_16_W 8 +#define CPU_SCS_NVIC_IPR4_PRI_16_M 0x000000FF +#define CPU_SCS_NVIC_IPR4_PRI_16_S 0 //***************************************************************************** // @@ -2315,30 +2315,30 @@ // Field: [31:24] PRI_23 // // Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). -#define CPU_SCS_NVIC_IPR5_PRI_23_W 8 -#define CPU_SCS_NVIC_IPR5_PRI_23_M 0xFF000000 -#define CPU_SCS_NVIC_IPR5_PRI_23_S 24 +#define CPU_SCS_NVIC_IPR5_PRI_23_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_23_M 0xFF000000 +#define CPU_SCS_NVIC_IPR5_PRI_23_S 24 // Field: [23:16] PRI_22 // // Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). -#define CPU_SCS_NVIC_IPR5_PRI_22_W 8 -#define CPU_SCS_NVIC_IPR5_PRI_22_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR5_PRI_22_S 16 +#define CPU_SCS_NVIC_IPR5_PRI_22_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_22_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR5_PRI_22_S 16 // Field: [15:8] PRI_21 // // Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). -#define CPU_SCS_NVIC_IPR5_PRI_21_W 8 -#define CPU_SCS_NVIC_IPR5_PRI_21_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR5_PRI_21_S 8 +#define CPU_SCS_NVIC_IPR5_PRI_21_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_21_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR5_PRI_21_S 8 // Field: [7:0] PRI_20 // // Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). -#define CPU_SCS_NVIC_IPR5_PRI_20_W 8 -#define CPU_SCS_NVIC_IPR5_PRI_20_M 0x000000FF -#define CPU_SCS_NVIC_IPR5_PRI_20_S 0 +#define CPU_SCS_NVIC_IPR5_PRI_20_W 8 +#define CPU_SCS_NVIC_IPR5_PRI_20_M 0x000000FF +#define CPU_SCS_NVIC_IPR5_PRI_20_S 0 //***************************************************************************** // @@ -2348,30 +2348,30 @@ // Field: [31:24] PRI_27 // // Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). -#define CPU_SCS_NVIC_IPR6_PRI_27_W 8 -#define CPU_SCS_NVIC_IPR6_PRI_27_M 0xFF000000 -#define CPU_SCS_NVIC_IPR6_PRI_27_S 24 +#define CPU_SCS_NVIC_IPR6_PRI_27_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_27_M 0xFF000000 +#define CPU_SCS_NVIC_IPR6_PRI_27_S 24 // Field: [23:16] PRI_26 // // Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). -#define CPU_SCS_NVIC_IPR6_PRI_26_W 8 -#define CPU_SCS_NVIC_IPR6_PRI_26_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR6_PRI_26_S 16 +#define CPU_SCS_NVIC_IPR6_PRI_26_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_26_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR6_PRI_26_S 16 // Field: [15:8] PRI_25 // // Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). -#define CPU_SCS_NVIC_IPR6_PRI_25_W 8 -#define CPU_SCS_NVIC_IPR6_PRI_25_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR6_PRI_25_S 8 +#define CPU_SCS_NVIC_IPR6_PRI_25_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_25_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR6_PRI_25_S 8 // Field: [7:0] PRI_24 // // Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). -#define CPU_SCS_NVIC_IPR6_PRI_24_W 8 -#define CPU_SCS_NVIC_IPR6_PRI_24_M 0x000000FF -#define CPU_SCS_NVIC_IPR6_PRI_24_S 0 +#define CPU_SCS_NVIC_IPR6_PRI_24_W 8 +#define CPU_SCS_NVIC_IPR6_PRI_24_M 0x000000FF +#define CPU_SCS_NVIC_IPR6_PRI_24_S 0 //***************************************************************************** // @@ -2381,30 +2381,30 @@ // Field: [31:24] PRI_31 // // Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). -#define CPU_SCS_NVIC_IPR7_PRI_31_W 8 -#define CPU_SCS_NVIC_IPR7_PRI_31_M 0xFF000000 -#define CPU_SCS_NVIC_IPR7_PRI_31_S 24 +#define CPU_SCS_NVIC_IPR7_PRI_31_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_31_M 0xFF000000 +#define CPU_SCS_NVIC_IPR7_PRI_31_S 24 // Field: [23:16] PRI_30 // // Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). -#define CPU_SCS_NVIC_IPR7_PRI_30_W 8 -#define CPU_SCS_NVIC_IPR7_PRI_30_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR7_PRI_30_S 16 +#define CPU_SCS_NVIC_IPR7_PRI_30_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_30_M 0x00FF0000 +#define CPU_SCS_NVIC_IPR7_PRI_30_S 16 // Field: [15:8] PRI_29 // // Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). -#define CPU_SCS_NVIC_IPR7_PRI_29_W 8 -#define CPU_SCS_NVIC_IPR7_PRI_29_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR7_PRI_29_S 8 +#define CPU_SCS_NVIC_IPR7_PRI_29_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_29_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR7_PRI_29_S 8 // Field: [7:0] PRI_28 // // Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). -#define CPU_SCS_NVIC_IPR7_PRI_28_W 8 -#define CPU_SCS_NVIC_IPR7_PRI_28_M 0x000000FF -#define CPU_SCS_NVIC_IPR7_PRI_28_S 0 +#define CPU_SCS_NVIC_IPR7_PRI_28_W 8 +#define CPU_SCS_NVIC_IPR7_PRI_28_M 0x000000FF +#define CPU_SCS_NVIC_IPR7_PRI_28_S 0 //***************************************************************************** // @@ -2414,16 +2414,16 @@ // Field: [15:8] PRI_33 // // Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). -#define CPU_SCS_NVIC_IPR8_PRI_33_W 8 -#define CPU_SCS_NVIC_IPR8_PRI_33_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR8_PRI_33_S 8 +#define CPU_SCS_NVIC_IPR8_PRI_33_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_33_M 0x0000FF00 +#define CPU_SCS_NVIC_IPR8_PRI_33_S 8 // Field: [7:0] PRI_32 // // Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). -#define CPU_SCS_NVIC_IPR8_PRI_32_W 8 -#define CPU_SCS_NVIC_IPR8_PRI_32_M 0x000000FF -#define CPU_SCS_NVIC_IPR8_PRI_32_S 0 +#define CPU_SCS_NVIC_IPR8_PRI_32_W 8 +#define CPU_SCS_NVIC_IPR8_PRI_32_M 0x000000FF +#define CPU_SCS_NVIC_IPR8_PRI_32_S 0 //***************************************************************************** // @@ -2433,37 +2433,37 @@ // Field: [31:24] IMPLEMENTER // // Implementor code. -#define CPU_SCS_CPUID_IMPLEMENTER_W 8 -#define CPU_SCS_CPUID_IMPLEMENTER_M 0xFF000000 -#define CPU_SCS_CPUID_IMPLEMENTER_S 24 +#define CPU_SCS_CPUID_IMPLEMENTER_W 8 +#define CPU_SCS_CPUID_IMPLEMENTER_M 0xFF000000 +#define CPU_SCS_CPUID_IMPLEMENTER_S 24 // Field: [23:20] VARIANT // // Implementation defined variant number. -#define CPU_SCS_CPUID_VARIANT_W 4 -#define CPU_SCS_CPUID_VARIANT_M 0x00F00000 -#define CPU_SCS_CPUID_VARIANT_S 20 +#define CPU_SCS_CPUID_VARIANT_W 4 +#define CPU_SCS_CPUID_VARIANT_M 0x00F00000 +#define CPU_SCS_CPUID_VARIANT_S 20 // Field: [19:16] CONSTANT // // Reads as 0xF -#define CPU_SCS_CPUID_CONSTANT_W 4 -#define CPU_SCS_CPUID_CONSTANT_M 0x000F0000 -#define CPU_SCS_CPUID_CONSTANT_S 16 +#define CPU_SCS_CPUID_CONSTANT_W 4 +#define CPU_SCS_CPUID_CONSTANT_M 0x000F0000 +#define CPU_SCS_CPUID_CONSTANT_S 16 // Field: [15:4] PARTNO // // Number of processor within family. -#define CPU_SCS_CPUID_PARTNO_W 12 -#define CPU_SCS_CPUID_PARTNO_M 0x0000FFF0 -#define CPU_SCS_CPUID_PARTNO_S 4 +#define CPU_SCS_CPUID_PARTNO_W 12 +#define CPU_SCS_CPUID_PARTNO_M 0x0000FFF0 +#define CPU_SCS_CPUID_PARTNO_S 4 // Field: [3:0] REVISION // // Implementation defined revision number. -#define CPU_SCS_CPUID_REVISION_W 4 -#define CPU_SCS_CPUID_REVISION_M 0x0000000F -#define CPU_SCS_CPUID_REVISION_S 0 +#define CPU_SCS_CPUID_REVISION_W 4 +#define CPU_SCS_CPUID_REVISION_M 0x0000000F +#define CPU_SCS_CPUID_REVISION_S 0 //***************************************************************************** // @@ -2478,10 +2478,10 @@ // // 0: No action // 1: Set pending NMI -#define CPU_SCS_ICSR_NMIPENDSET 0x80000000 -#define CPU_SCS_ICSR_NMIPENDSET_BITN 31 -#define CPU_SCS_ICSR_NMIPENDSET_M 0x80000000 -#define CPU_SCS_ICSR_NMIPENDSET_S 31 +#define CPU_SCS_ICSR_NMIPENDSET 0x80000000 +#define CPU_SCS_ICSR_NMIPENDSET_BITN 31 +#define CPU_SCS_ICSR_NMIPENDSET_M 0x80000000 +#define CPU_SCS_ICSR_NMIPENDSET_S 31 // Field: [28] PENDSVSET // @@ -2489,10 +2489,10 @@ // // 0: No action // 1: Set pending PendSV -#define CPU_SCS_ICSR_PENDSVSET 0x10000000 -#define CPU_SCS_ICSR_PENDSVSET_BITN 28 -#define CPU_SCS_ICSR_PENDSVSET_M 0x10000000 -#define CPU_SCS_ICSR_PENDSVSET_S 28 +#define CPU_SCS_ICSR_PENDSVSET 0x10000000 +#define CPU_SCS_ICSR_PENDSVSET_BITN 28 +#define CPU_SCS_ICSR_PENDSVSET_M 0x10000000 +#define CPU_SCS_ICSR_PENDSVSET_S 28 // Field: [27] PENDSVCLR // @@ -2500,10 +2500,10 @@ // // 0: No action // 1: Clear pending pendSV -#define CPU_SCS_ICSR_PENDSVCLR 0x08000000 -#define CPU_SCS_ICSR_PENDSVCLR_BITN 27 -#define CPU_SCS_ICSR_PENDSVCLR_M 0x08000000 -#define CPU_SCS_ICSR_PENDSVCLR_S 27 +#define CPU_SCS_ICSR_PENDSVCLR 0x08000000 +#define CPU_SCS_ICSR_PENDSVCLR_BITN 27 +#define CPU_SCS_ICSR_PENDSVCLR_M 0x08000000 +#define CPU_SCS_ICSR_PENDSVCLR_S 27 // Field: [26] PENDSTSET // @@ -2511,10 +2511,10 @@ // // 0: No action // 1: Set pending SysTick -#define CPU_SCS_ICSR_PENDSTSET 0x04000000 -#define CPU_SCS_ICSR_PENDSTSET_BITN 26 -#define CPU_SCS_ICSR_PENDSTSET_M 0x04000000 -#define CPU_SCS_ICSR_PENDSTSET_S 26 +#define CPU_SCS_ICSR_PENDSTSET 0x04000000 +#define CPU_SCS_ICSR_PENDSTSET_BITN 26 +#define CPU_SCS_ICSR_PENDSTSET_M 0x04000000 +#define CPU_SCS_ICSR_PENDSTSET_S 26 // Field: [25] PENDSTCLR // @@ -2522,10 +2522,10 @@ // // 0: No action // 1: Clear pending SysTick -#define CPU_SCS_ICSR_PENDSTCLR 0x02000000 -#define CPU_SCS_ICSR_PENDSTCLR_BITN 25 -#define CPU_SCS_ICSR_PENDSTCLR_M 0x02000000 -#define CPU_SCS_ICSR_PENDSTCLR_S 25 +#define CPU_SCS_ICSR_PENDSTCLR 0x02000000 +#define CPU_SCS_ICSR_PENDSTCLR_BITN 25 +#define CPU_SCS_ICSR_PENDSTCLR_M 0x02000000 +#define CPU_SCS_ICSR_PENDSTCLR_S 25 // Field: [23] ISRPREEMPT // @@ -2535,10 +2535,10 @@ // // 0: A pending exception is not serviced. // 1: A pending exception is serviced on exit from the debug halt state -#define CPU_SCS_ICSR_ISRPREEMPT 0x00800000 -#define CPU_SCS_ICSR_ISRPREEMPT_BITN 23 -#define CPU_SCS_ICSR_ISRPREEMPT_M 0x00800000 -#define CPU_SCS_ICSR_ISRPREEMPT_S 23 +#define CPU_SCS_ICSR_ISRPREEMPT 0x00800000 +#define CPU_SCS_ICSR_ISRPREEMPT_BITN 23 +#define CPU_SCS_ICSR_ISRPREEMPT_M 0x00800000 +#define CPU_SCS_ICSR_ISRPREEMPT_S 23 // Field: [22] ISRPENDING // @@ -2546,18 +2546,18 @@ // // 0x0: Interrupt not pending // 0x1: Interrupt pending -#define CPU_SCS_ICSR_ISRPENDING 0x00400000 -#define CPU_SCS_ICSR_ISRPENDING_BITN 22 -#define CPU_SCS_ICSR_ISRPENDING_M 0x00400000 -#define CPU_SCS_ICSR_ISRPENDING_S 22 +#define CPU_SCS_ICSR_ISRPENDING 0x00400000 +#define CPU_SCS_ICSR_ISRPENDING_BITN 22 +#define CPU_SCS_ICSR_ISRPENDING_M 0x00400000 +#define CPU_SCS_ICSR_ISRPENDING_S 22 // Field: [17:12] VECTPENDING // // Pending ISR number field. This field contains the interrupt number of the // highest priority pending ISR. -#define CPU_SCS_ICSR_VECTPENDING_W 6 -#define CPU_SCS_ICSR_VECTPENDING_M 0x0003F000 -#define CPU_SCS_ICSR_VECTPENDING_S 12 +#define CPU_SCS_ICSR_VECTPENDING_W 6 +#define CPU_SCS_ICSR_VECTPENDING_M 0x0003F000 +#define CPU_SCS_ICSR_VECTPENDING_S 12 // Field: [11] RETTOBASE // @@ -2566,17 +2566,17 @@ // 0: There are preempted active exceptions to execute // 1: There are no active exceptions, or the currently-executing exception is // the only active exception. -#define CPU_SCS_ICSR_RETTOBASE 0x00000800 -#define CPU_SCS_ICSR_RETTOBASE_BITN 11 -#define CPU_SCS_ICSR_RETTOBASE_M 0x00000800 -#define CPU_SCS_ICSR_RETTOBASE_S 11 +#define CPU_SCS_ICSR_RETTOBASE 0x00000800 +#define CPU_SCS_ICSR_RETTOBASE_BITN 11 +#define CPU_SCS_ICSR_RETTOBASE_M 0x00000800 +#define CPU_SCS_ICSR_RETTOBASE_S 11 // Field: [8:0] VECTACTIVE // // Active ISR number field. Reset clears this field. -#define CPU_SCS_ICSR_VECTACTIVE_W 9 -#define CPU_SCS_ICSR_VECTACTIVE_M 0x000001FF -#define CPU_SCS_ICSR_VECTACTIVE_S 0 +#define CPU_SCS_ICSR_VECTACTIVE_W 9 +#define CPU_SCS_ICSR_VECTACTIVE_M 0x000001FF +#define CPU_SCS_ICSR_VECTACTIVE_S 0 //***************************************************************************** // @@ -2586,9 +2586,9 @@ // Field: [29:7] TBLOFF // // Bits 29 down to 7 of the vector table base offset. -#define CPU_SCS_VTOR_TBLOFF_W 23 -#define CPU_SCS_VTOR_TBLOFF_M 0x3FFFFF80 -#define CPU_SCS_VTOR_TBLOFF_S 7 +#define CPU_SCS_VTOR_TBLOFF_W 23 +#define CPU_SCS_VTOR_TBLOFF_M 0x3FFFFF80 +#define CPU_SCS_VTOR_TBLOFF_S 7 //***************************************************************************** // @@ -2599,9 +2599,9 @@ // // Register key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. // Otherwise the write value is ignored. Read always returns 0xFA05. -#define CPU_SCS_AIRCR_VECTKEY_W 16 -#define CPU_SCS_AIRCR_VECTKEY_M 0xFFFF0000 -#define CPU_SCS_AIRCR_VECTKEY_S 16 +#define CPU_SCS_AIRCR_VECTKEY_W 16 +#define CPU_SCS_AIRCR_VECTKEY_M 0xFFFF0000 +#define CPU_SCS_AIRCR_VECTKEY_S 16 // Field: [15] ENDIANESS // @@ -2609,12 +2609,12 @@ // ENUMs: // BIG Big endian // LITTLE Little endian -#define CPU_SCS_AIRCR_ENDIANESS 0x00008000 -#define CPU_SCS_AIRCR_ENDIANESS_BITN 15 -#define CPU_SCS_AIRCR_ENDIANESS_M 0x00008000 -#define CPU_SCS_AIRCR_ENDIANESS_S 15 -#define CPU_SCS_AIRCR_ENDIANESS_BIG 0x00008000 -#define CPU_SCS_AIRCR_ENDIANESS_LITTLE 0x00000000 +#define CPU_SCS_AIRCR_ENDIANESS 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_BITN 15 +#define CPU_SCS_AIRCR_ENDIANESS_M 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_S 15 +#define CPU_SCS_AIRCR_ENDIANESS_BIG 0x00008000 +#define CPU_SCS_AIRCR_ENDIANESS_LITTLE 0x00000000 // Field: [10:8] PRIGROUP // @@ -2626,18 +2626,18 @@ // means that the PRIGROUP value represents a point starting at the left of the // Least Significant Bit (LSB). The lowest value might not be 0 depending on // the number of bits allocated for priorities, and implementation choices. -#define CPU_SCS_AIRCR_PRIGROUP_W 3 -#define CPU_SCS_AIRCR_PRIGROUP_M 0x00000700 -#define CPU_SCS_AIRCR_PRIGROUP_S 8 +#define CPU_SCS_AIRCR_PRIGROUP_W 3 +#define CPU_SCS_AIRCR_PRIGROUP_M 0x00000700 +#define CPU_SCS_AIRCR_PRIGROUP_S 8 // Field: [2] SYSRESETREQ // // Requests a warm reset. Setting this bit does not prevent Halting Debug from // running. -#define CPU_SCS_AIRCR_SYSRESETREQ 0x00000004 -#define CPU_SCS_AIRCR_SYSRESETREQ_BITN 2 -#define CPU_SCS_AIRCR_SYSRESETREQ_M 0x00000004 -#define CPU_SCS_AIRCR_SYSRESETREQ_S 2 +#define CPU_SCS_AIRCR_SYSRESETREQ 0x00000004 +#define CPU_SCS_AIRCR_SYSRESETREQ_BITN 2 +#define CPU_SCS_AIRCR_SYSRESETREQ_M 0x00000004 +#define CPU_SCS_AIRCR_SYSRESETREQ_S 2 // Field: [1] VECTCLRACTIVE // @@ -2647,10 +2647,10 @@ // IPSR is not cleared by this operation. So, if used by an application, it // must only be used at the base level of activation, or within a system // handler whose active bit can be set. -#define CPU_SCS_AIRCR_VECTCLRACTIVE 0x00000002 -#define CPU_SCS_AIRCR_VECTCLRACTIVE_BITN 1 -#define CPU_SCS_AIRCR_VECTCLRACTIVE_M 0x00000002 -#define CPU_SCS_AIRCR_VECTCLRACTIVE_S 1 +#define CPU_SCS_AIRCR_VECTCLRACTIVE 0x00000002 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_BITN 1 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_M 0x00000002 +#define CPU_SCS_AIRCR_VECTCLRACTIVE_S 1 // Field: [0] VECTRESET // @@ -2658,10 +2658,10 @@ // This bit is reserved for debug use and can be written to 1 only when the // core is halted. The bit self-clears. Writing this bit to 1 while core is not // halted may result in unpredictable behavior. -#define CPU_SCS_AIRCR_VECTRESET 0x00000001 -#define CPU_SCS_AIRCR_VECTRESET_BITN 0 -#define CPU_SCS_AIRCR_VECTRESET_M 0x00000001 -#define CPU_SCS_AIRCR_VECTRESET_S 0 +#define CPU_SCS_AIRCR_VECTRESET 0x00000001 +#define CPU_SCS_AIRCR_VECTRESET_BITN 0 +#define CPU_SCS_AIRCR_VECTRESET_M 0x00000001 +#define CPU_SCS_AIRCR_VECTRESET_S 0 //***************************************************************************** // @@ -2682,10 +2682,10 @@ // the processor is not waiting for an event, the event is registered and // affects the next WFE. // The processor also wakes up on execution of an SEV instruction. -#define CPU_SCS_SCR_SEVONPEND 0x00000010 -#define CPU_SCS_SCR_SEVONPEND_BITN 4 -#define CPU_SCS_SCR_SEVONPEND_M 0x00000010 -#define CPU_SCS_SCR_SEVONPEND_S 4 +#define CPU_SCS_SCR_SEVONPEND 0x00000010 +#define CPU_SCS_SCR_SEVONPEND_BITN 4 +#define CPU_SCS_SCR_SEVONPEND_M 0x00000010 +#define CPU_SCS_SCR_SEVONPEND_S 4 // Field: [2] SLEEPDEEP // @@ -2694,12 +2694,12 @@ // ENUMs: // DEEPSLEEP Deep sleep // SLEEP Sleep -#define CPU_SCS_SCR_SLEEPDEEP 0x00000004 -#define CPU_SCS_SCR_SLEEPDEEP_BITN 2 -#define CPU_SCS_SCR_SLEEPDEEP_M 0x00000004 -#define CPU_SCS_SCR_SLEEPDEEP_S 2 -#define CPU_SCS_SCR_SLEEPDEEP_DEEPSLEEP 0x00000004 -#define CPU_SCS_SCR_SLEEPDEEP_SLEEP 0x00000000 +#define CPU_SCS_SCR_SLEEPDEEP 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_BITN 2 +#define CPU_SCS_SCR_SLEEPDEEP_M 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_S 2 +#define CPU_SCS_SCR_SLEEPDEEP_DEEPSLEEP 0x00000004 +#define CPU_SCS_SCR_SLEEPDEEP_SLEEP 0x00000000 // Field: [1] SLEEPONEXIT // @@ -2708,10 +2708,10 @@ // // 0: Do not sleep when returning to thread mode // 1: Sleep on ISR exit -#define CPU_SCS_SCR_SLEEPONEXIT 0x00000002 -#define CPU_SCS_SCR_SLEEPONEXIT_BITN 1 -#define CPU_SCS_SCR_SLEEPONEXIT_M 0x00000002 -#define CPU_SCS_SCR_SLEEPONEXIT_S 1 +#define CPU_SCS_SCR_SLEEPONEXIT 0x00000002 +#define CPU_SCS_SCR_SLEEPONEXIT_BITN 1 +#define CPU_SCS_SCR_SLEEPONEXIT_M 0x00000002 +#define CPU_SCS_SCR_SLEEPONEXIT_S 1 //***************************************************************************** // @@ -2727,10 +2727,10 @@ // 1: On exception entry, the SP used prior to the exception is adjusted to be // 8-byte aligned and the context to restore it is saved. The SP is restored on // the associated exception return. -#define CPU_SCS_CCR_STKALIGN 0x00000200 -#define CPU_SCS_CCR_STKALIGN_BITN 9 -#define CPU_SCS_CCR_STKALIGN_M 0x00000200 -#define CPU_SCS_CCR_STKALIGN_S 9 +#define CPU_SCS_CCR_STKALIGN 0x00000200 +#define CPU_SCS_CCR_STKALIGN_BITN 9 +#define CPU_SCS_CCR_STKALIGN_M 0x00000200 +#define CPU_SCS_CCR_STKALIGN_S 9 // Field: [8] BFHFNMIGN // @@ -2744,10 +2744,10 @@ // Set this bit to 1 only when the handler and its data are in absolutely safe // memory. The normal use // of this bit is to probe system devices and bridges to detect problems. -#define CPU_SCS_CCR_BFHFNMIGN 0x00000100 -#define CPU_SCS_CCR_BFHFNMIGN_BITN 8 -#define CPU_SCS_CCR_BFHFNMIGN_M 0x00000100 -#define CPU_SCS_CCR_BFHFNMIGN_S 8 +#define CPU_SCS_CCR_BFHFNMIGN 0x00000100 +#define CPU_SCS_CCR_BFHFNMIGN_BITN 8 +#define CPU_SCS_CCR_BFHFNMIGN_M 0x00000100 +#define CPU_SCS_CCR_BFHFNMIGN_S 8 // Field: [4] DIV_0_TRP // @@ -2758,10 +2758,10 @@ // quotient of 0. // 1: Trap divide by 0. The relevant Usage Fault Status Register bit is // CFSR.DIVBYZERO. -#define CPU_SCS_CCR_DIV_0_TRP 0x00000010 -#define CPU_SCS_CCR_DIV_0_TRP_BITN 4 -#define CPU_SCS_CCR_DIV_0_TRP_M 0x00000010 -#define CPU_SCS_CCR_DIV_0_TRP_S 4 +#define CPU_SCS_CCR_DIV_0_TRP 0x00000010 +#define CPU_SCS_CCR_DIV_0_TRP_BITN 4 +#define CPU_SCS_CCR_DIV_0_TRP_M 0x00000010 +#define CPU_SCS_CCR_DIV_0_TRP_S 4 // Field: [3] UNALIGN_TRP // @@ -2774,10 +2774,10 @@ // If this bit is set to 1, an unaligned access generates a UsageFault. // Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of // the value in UNALIGN_TRP. -#define CPU_SCS_CCR_UNALIGN_TRP 0x00000008 -#define CPU_SCS_CCR_UNALIGN_TRP_BITN 3 -#define CPU_SCS_CCR_UNALIGN_TRP_M 0x00000008 -#define CPU_SCS_CCR_UNALIGN_TRP_S 3 +#define CPU_SCS_CCR_UNALIGN_TRP 0x00000008 +#define CPU_SCS_CCR_UNALIGN_TRP_BITN 3 +#define CPU_SCS_CCR_UNALIGN_TRP_M 0x00000008 +#define CPU_SCS_CCR_UNALIGN_TRP_S 3 // Field: [1] USERSETMPEND // @@ -2788,10 +2788,10 @@ // 1: User code can write the Software Trigger Interrupt register (STIR) to // trigger (pend) a Main exception, which is associated with the Main stack // pointer. -#define CPU_SCS_CCR_USERSETMPEND 0x00000002 -#define CPU_SCS_CCR_USERSETMPEND_BITN 1 -#define CPU_SCS_CCR_USERSETMPEND_M 0x00000002 -#define CPU_SCS_CCR_USERSETMPEND_S 1 +#define CPU_SCS_CCR_USERSETMPEND 0x00000002 +#define CPU_SCS_CCR_USERSETMPEND_BITN 1 +#define CPU_SCS_CCR_USERSETMPEND_M 0x00000002 +#define CPU_SCS_CCR_USERSETMPEND_S 1 // Field: [0] NONBASETHREDENA // @@ -2808,10 +2808,10 @@ // - BX with any register. // The value written to the PC is intercepted and is referred to as the // EXC_RETURN value. -#define CPU_SCS_CCR_NONBASETHREDENA 0x00000001 -#define CPU_SCS_CCR_NONBASETHREDENA_BITN 0 -#define CPU_SCS_CCR_NONBASETHREDENA_M 0x00000001 -#define CPU_SCS_CCR_NONBASETHREDENA_S 0 +#define CPU_SCS_CCR_NONBASETHREDENA 0x00000001 +#define CPU_SCS_CCR_NONBASETHREDENA_BITN 0 +#define CPU_SCS_CCR_NONBASETHREDENA_M 0x00000001 +#define CPU_SCS_CCR_NONBASETHREDENA_S 0 //***************************************************************************** // @@ -2821,23 +2821,23 @@ // Field: [23:16] PRI_6 // // Priority of system handler 6. UsageFault -#define CPU_SCS_SHPR1_PRI_6_W 8 -#define CPU_SCS_SHPR1_PRI_6_M 0x00FF0000 -#define CPU_SCS_SHPR1_PRI_6_S 16 +#define CPU_SCS_SHPR1_PRI_6_W 8 +#define CPU_SCS_SHPR1_PRI_6_M 0x00FF0000 +#define CPU_SCS_SHPR1_PRI_6_S 16 // Field: [15:8] PRI_5 // // Priority of system handler 5: BusFault -#define CPU_SCS_SHPR1_PRI_5_W 8 -#define CPU_SCS_SHPR1_PRI_5_M 0x0000FF00 -#define CPU_SCS_SHPR1_PRI_5_S 8 +#define CPU_SCS_SHPR1_PRI_5_W 8 +#define CPU_SCS_SHPR1_PRI_5_M 0x0000FF00 +#define CPU_SCS_SHPR1_PRI_5_S 8 // Field: [7:0] PRI_4 // // Priority of system handler 4: MemManage -#define CPU_SCS_SHPR1_PRI_4_W 8 -#define CPU_SCS_SHPR1_PRI_4_M 0x000000FF -#define CPU_SCS_SHPR1_PRI_4_S 0 +#define CPU_SCS_SHPR1_PRI_4_W 8 +#define CPU_SCS_SHPR1_PRI_4_M 0x000000FF +#define CPU_SCS_SHPR1_PRI_4_S 0 //***************************************************************************** // @@ -2847,9 +2847,9 @@ // Field: [31:24] PRI_11 // // Priority of system handler 11. SVCall -#define CPU_SCS_SHPR2_PRI_11_W 8 -#define CPU_SCS_SHPR2_PRI_11_M 0xFF000000 -#define CPU_SCS_SHPR2_PRI_11_S 24 +#define CPU_SCS_SHPR2_PRI_11_W 8 +#define CPU_SCS_SHPR2_PRI_11_M 0xFF000000 +#define CPU_SCS_SHPR2_PRI_11_S 24 //***************************************************************************** // @@ -2859,23 +2859,23 @@ // Field: [31:24] PRI_15 // // Priority of system handler 15. SysTick exception -#define CPU_SCS_SHPR3_PRI_15_W 8 -#define CPU_SCS_SHPR3_PRI_15_M 0xFF000000 -#define CPU_SCS_SHPR3_PRI_15_S 24 +#define CPU_SCS_SHPR3_PRI_15_W 8 +#define CPU_SCS_SHPR3_PRI_15_M 0xFF000000 +#define CPU_SCS_SHPR3_PRI_15_S 24 // Field: [23:16] PRI_14 // // Priority of system handler 14. Pend SV -#define CPU_SCS_SHPR3_PRI_14_W 8 -#define CPU_SCS_SHPR3_PRI_14_M 0x00FF0000 -#define CPU_SCS_SHPR3_PRI_14_S 16 +#define CPU_SCS_SHPR3_PRI_14_W 8 +#define CPU_SCS_SHPR3_PRI_14_M 0x00FF0000 +#define CPU_SCS_SHPR3_PRI_14_S 16 // Field: [7:0] PRI_12 // // Priority of system handler 12. Debug Monitor -#define CPU_SCS_SHPR3_PRI_12_W 8 -#define CPU_SCS_SHPR3_PRI_12_M 0x000000FF -#define CPU_SCS_SHPR3_PRI_12_S 0 +#define CPU_SCS_SHPR3_PRI_12_W 8 +#define CPU_SCS_SHPR3_PRI_12_M 0x000000FF +#define CPU_SCS_SHPR3_PRI_12_S 0 //***************************************************************************** // @@ -2888,12 +2888,12 @@ // ENUMs: // EN Exception enabled // DIS Exception disabled -#define CPU_SCS_SHCSR_USGFAULTENA 0x00040000 -#define CPU_SCS_SHCSR_USGFAULTENA_BITN 18 -#define CPU_SCS_SHCSR_USGFAULTENA_M 0x00040000 -#define CPU_SCS_SHCSR_USGFAULTENA_S 18 -#define CPU_SCS_SHCSR_USGFAULTENA_EN 0x00040000 -#define CPU_SCS_SHCSR_USGFAULTENA_DIS 0x00000000 +#define CPU_SCS_SHCSR_USGFAULTENA 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_BITN 18 +#define CPU_SCS_SHCSR_USGFAULTENA_M 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_S 18 +#define CPU_SCS_SHCSR_USGFAULTENA_EN 0x00040000 +#define CPU_SCS_SHCSR_USGFAULTENA_DIS 0x00000000 // Field: [17] BUSFAULTENA // @@ -2901,12 +2901,12 @@ // ENUMs: // EN Exception enabled // DIS Exception disabled -#define CPU_SCS_SHCSR_BUSFAULTENA 0x00020000 -#define CPU_SCS_SHCSR_BUSFAULTENA_BITN 17 -#define CPU_SCS_SHCSR_BUSFAULTENA_M 0x00020000 -#define CPU_SCS_SHCSR_BUSFAULTENA_S 17 -#define CPU_SCS_SHCSR_BUSFAULTENA_EN 0x00020000 -#define CPU_SCS_SHCSR_BUSFAULTENA_DIS 0x00000000 +#define CPU_SCS_SHCSR_BUSFAULTENA 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_BITN 17 +#define CPU_SCS_SHCSR_BUSFAULTENA_M 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_S 17 +#define CPU_SCS_SHCSR_BUSFAULTENA_EN 0x00020000 +#define CPU_SCS_SHCSR_BUSFAULTENA_DIS 0x00000000 // Field: [16] MEMFAULTENA // @@ -2914,12 +2914,12 @@ // ENUMs: // EN Exception enabled // DIS Exception disabled -#define CPU_SCS_SHCSR_MEMFAULTENA 0x00010000 -#define CPU_SCS_SHCSR_MEMFAULTENA_BITN 16 -#define CPU_SCS_SHCSR_MEMFAULTENA_M 0x00010000 -#define CPU_SCS_SHCSR_MEMFAULTENA_S 16 -#define CPU_SCS_SHCSR_MEMFAULTENA_EN 0x00010000 -#define CPU_SCS_SHCSR_MEMFAULTENA_DIS 0x00000000 +#define CPU_SCS_SHCSR_MEMFAULTENA 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_BITN 16 +#define CPU_SCS_SHCSR_MEMFAULTENA_M 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_S 16 +#define CPU_SCS_SHCSR_MEMFAULTENA_EN 0x00010000 +#define CPU_SCS_SHCSR_MEMFAULTENA_DIS 0x00000000 // Field: [15] SVCALLPENDED // @@ -2927,12 +2927,12 @@ // ENUMs: // PENDING Exception is pending. // NOTPENDING Exception is not active -#define CPU_SCS_SHCSR_SVCALLPENDED 0x00008000 -#define CPU_SCS_SHCSR_SVCALLPENDED_BITN 15 -#define CPU_SCS_SHCSR_SVCALLPENDED_M 0x00008000 -#define CPU_SCS_SHCSR_SVCALLPENDED_S 15 -#define CPU_SCS_SHCSR_SVCALLPENDED_PENDING 0x00008000 -#define CPU_SCS_SHCSR_SVCALLPENDED_NOTPENDING 0x00000000 +#define CPU_SCS_SHCSR_SVCALLPENDED 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_BITN 15 +#define CPU_SCS_SHCSR_SVCALLPENDED_M 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_S 15 +#define CPU_SCS_SHCSR_SVCALLPENDED_PENDING 0x00008000 +#define CPU_SCS_SHCSR_SVCALLPENDED_NOTPENDING 0x00000000 // Field: [14] BUSFAULTPENDED // @@ -2940,12 +2940,12 @@ // ENUMs: // PENDING Exception is pending. // NOTPENDING Exception is not active -#define CPU_SCS_SHCSR_BUSFAULTPENDED 0x00004000 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_BITN 14 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_M 0x00004000 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_S 14 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_PENDING 0x00004000 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_NOTPENDING 0x00000000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_BITN 14 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_M 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_S 14 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_PENDING 0x00004000 +#define CPU_SCS_SHCSR_BUSFAULTPENDED_NOTPENDING 0x00000000 // Field: [13] MEMFAULTPENDED // @@ -2953,12 +2953,12 @@ // ENUMs: // PENDING Exception is pending. // NOTPENDING Exception is not active -#define CPU_SCS_SHCSR_MEMFAULTPENDED 0x00002000 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_BITN 13 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_M 0x00002000 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_S 13 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_PENDING 0x00002000 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_NOTPENDING 0x00000000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_BITN 13 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_M 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_S 13 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_PENDING 0x00002000 +#define CPU_SCS_SHCSR_MEMFAULTPENDED_NOTPENDING 0x00000000 // Field: [12] USGFAULTPENDED // @@ -2966,12 +2966,12 @@ // ENUMs: // PENDING Exception is pending. // NOTPENDING Exception is not active -#define CPU_SCS_SHCSR_USGFAULTPENDED 0x00001000 -#define CPU_SCS_SHCSR_USGFAULTPENDED_BITN 12 -#define CPU_SCS_SHCSR_USGFAULTPENDED_M 0x00001000 -#define CPU_SCS_SHCSR_USGFAULTPENDED_S 12 -#define CPU_SCS_SHCSR_USGFAULTPENDED_PENDING 0x00001000 -#define CPU_SCS_SHCSR_USGFAULTPENDED_NOTPENDING 0x00000000 +#define CPU_SCS_SHCSR_USGFAULTPENDED 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_BITN 12 +#define CPU_SCS_SHCSR_USGFAULTPENDED_M 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_S 12 +#define CPU_SCS_SHCSR_USGFAULTPENDED_PENDING 0x00001000 +#define CPU_SCS_SHCSR_USGFAULTPENDED_NOTPENDING 0x00000000 // Field: [11] SYSTICKACT // @@ -2982,12 +2982,12 @@ // ENUMs: // ACTIVE Exception is active // NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_SYSTICKACT 0x00000800 -#define CPU_SCS_SHCSR_SYSTICKACT_BITN 11 -#define CPU_SCS_SHCSR_SYSTICKACT_M 0x00000800 -#define CPU_SCS_SHCSR_SYSTICKACT_S 11 -#define CPU_SCS_SHCSR_SYSTICKACT_ACTIVE 0x00000800 -#define CPU_SCS_SHCSR_SYSTICKACT_NOTACTIVE 0x00000000 +#define CPU_SCS_SHCSR_SYSTICKACT 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_BITN 11 +#define CPU_SCS_SHCSR_SYSTICKACT_M 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_S 11 +#define CPU_SCS_SHCSR_SYSTICKACT_ACTIVE 0x00000800 +#define CPU_SCS_SHCSR_SYSTICKACT_NOTACTIVE 0x00000000 // Field: [10] PENDSVACT // @@ -2995,10 +2995,10 @@ // // 0x0: Not active // 0x1: Active -#define CPU_SCS_SHCSR_PENDSVACT 0x00000400 -#define CPU_SCS_SHCSR_PENDSVACT_BITN 10 -#define CPU_SCS_SHCSR_PENDSVACT_M 0x00000400 -#define CPU_SCS_SHCSR_PENDSVACT_S 10 +#define CPU_SCS_SHCSR_PENDSVACT 0x00000400 +#define CPU_SCS_SHCSR_PENDSVACT_BITN 10 +#define CPU_SCS_SHCSR_PENDSVACT_M 0x00000400 +#define CPU_SCS_SHCSR_PENDSVACT_S 10 // Field: [8] MONITORACT // @@ -3006,12 +3006,12 @@ // ENUMs: // ACTIVE Exception is active // NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_MONITORACT 0x00000100 -#define CPU_SCS_SHCSR_MONITORACT_BITN 8 -#define CPU_SCS_SHCSR_MONITORACT_M 0x00000100 -#define CPU_SCS_SHCSR_MONITORACT_S 8 -#define CPU_SCS_SHCSR_MONITORACT_ACTIVE 0x00000100 -#define CPU_SCS_SHCSR_MONITORACT_NOTACTIVE 0x00000000 +#define CPU_SCS_SHCSR_MONITORACT 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_BITN 8 +#define CPU_SCS_SHCSR_MONITORACT_M 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_S 8 +#define CPU_SCS_SHCSR_MONITORACT_ACTIVE 0x00000100 +#define CPU_SCS_SHCSR_MONITORACT_NOTACTIVE 0x00000000 // Field: [7] SVCALLACT // @@ -3019,12 +3019,12 @@ // ENUMs: // ACTIVE Exception is active // NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_SVCALLACT 0x00000080 -#define CPU_SCS_SHCSR_SVCALLACT_BITN 7 -#define CPU_SCS_SHCSR_SVCALLACT_M 0x00000080 -#define CPU_SCS_SHCSR_SVCALLACT_S 7 -#define CPU_SCS_SHCSR_SVCALLACT_ACTIVE 0x00000080 -#define CPU_SCS_SHCSR_SVCALLACT_NOTACTIVE 0x00000000 +#define CPU_SCS_SHCSR_SVCALLACT 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_BITN 7 +#define CPU_SCS_SHCSR_SVCALLACT_M 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_S 7 +#define CPU_SCS_SHCSR_SVCALLACT_ACTIVE 0x00000080 +#define CPU_SCS_SHCSR_SVCALLACT_NOTACTIVE 0x00000000 // Field: [3] USGFAULTACT // @@ -3032,12 +3032,12 @@ // ENUMs: // ACTIVE Exception is active // NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_USGFAULTACT 0x00000008 -#define CPU_SCS_SHCSR_USGFAULTACT_BITN 3 -#define CPU_SCS_SHCSR_USGFAULTACT_M 0x00000008 -#define CPU_SCS_SHCSR_USGFAULTACT_S 3 -#define CPU_SCS_SHCSR_USGFAULTACT_ACTIVE 0x00000008 -#define CPU_SCS_SHCSR_USGFAULTACT_NOTACTIVE 0x00000000 +#define CPU_SCS_SHCSR_USGFAULTACT 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_BITN 3 +#define CPU_SCS_SHCSR_USGFAULTACT_M 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_S 3 +#define CPU_SCS_SHCSR_USGFAULTACT_ACTIVE 0x00000008 +#define CPU_SCS_SHCSR_USGFAULTACT_NOTACTIVE 0x00000000 // Field: [1] BUSFAULTACT // @@ -3045,12 +3045,12 @@ // ENUMs: // ACTIVE Exception is active // NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_BUSFAULTACT 0x00000002 -#define CPU_SCS_SHCSR_BUSFAULTACT_BITN 1 -#define CPU_SCS_SHCSR_BUSFAULTACT_M 0x00000002 -#define CPU_SCS_SHCSR_BUSFAULTACT_S 1 -#define CPU_SCS_SHCSR_BUSFAULTACT_ACTIVE 0x00000002 -#define CPU_SCS_SHCSR_BUSFAULTACT_NOTACTIVE 0x00000000 +#define CPU_SCS_SHCSR_BUSFAULTACT 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_BITN 1 +#define CPU_SCS_SHCSR_BUSFAULTACT_M 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_S 1 +#define CPU_SCS_SHCSR_BUSFAULTACT_ACTIVE 0x00000002 +#define CPU_SCS_SHCSR_BUSFAULTACT_NOTACTIVE 0x00000000 // Field: [0] MEMFAULTACT // @@ -3058,12 +3058,12 @@ // ENUMs: // ACTIVE Exception is active // NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_MEMFAULTACT 0x00000001 -#define CPU_SCS_SHCSR_MEMFAULTACT_BITN 0 -#define CPU_SCS_SHCSR_MEMFAULTACT_M 0x00000001 -#define CPU_SCS_SHCSR_MEMFAULTACT_S 0 -#define CPU_SCS_SHCSR_MEMFAULTACT_ACTIVE 0x00000001 -#define CPU_SCS_SHCSR_MEMFAULTACT_NOTACTIVE 0x00000000 +#define CPU_SCS_SHCSR_MEMFAULTACT 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_BITN 0 +#define CPU_SCS_SHCSR_MEMFAULTACT_M 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_S 0 +#define CPU_SCS_SHCSR_MEMFAULTACT_ACTIVE 0x00000001 +#define CPU_SCS_SHCSR_MEMFAULTACT_NOTACTIVE 0x00000000 //***************************************************************************** // @@ -3076,39 +3076,39 @@ // enabled and an SDIV or UDIV instruction is used with a divisor of 0, this // fault occurs The instruction is executed and the return PC points to it. If // CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0. -#define CPU_SCS_CFSR_DIVBYZERO 0x02000000 -#define CPU_SCS_CFSR_DIVBYZERO_BITN 25 -#define CPU_SCS_CFSR_DIVBYZERO_M 0x02000000 -#define CPU_SCS_CFSR_DIVBYZERO_S 25 +#define CPU_SCS_CFSR_DIVBYZERO 0x02000000 +#define CPU_SCS_CFSR_DIVBYZERO_BITN 25 +#define CPU_SCS_CFSR_DIVBYZERO_M 0x02000000 +#define CPU_SCS_CFSR_DIVBYZERO_S 25 // Field: [24] UNALIGNED // // When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an // unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD // instructions always fault irrespective of the setting of CCR.UNALIGN_TRP. -#define CPU_SCS_CFSR_UNALIGNED 0x01000000 -#define CPU_SCS_CFSR_UNALIGNED_BITN 24 -#define CPU_SCS_CFSR_UNALIGNED_M 0x01000000 -#define CPU_SCS_CFSR_UNALIGNED_S 24 +#define CPU_SCS_CFSR_UNALIGNED 0x01000000 +#define CPU_SCS_CFSR_UNALIGNED_BITN 24 +#define CPU_SCS_CFSR_UNALIGNED_M 0x01000000 +#define CPU_SCS_CFSR_UNALIGNED_S 24 // Field: [19] NOCP // // Attempt to use a coprocessor instruction. The processor does not support // coprocessor instructions. -#define CPU_SCS_CFSR_NOCP 0x00080000 -#define CPU_SCS_CFSR_NOCP_BITN 19 -#define CPU_SCS_CFSR_NOCP_M 0x00080000 -#define CPU_SCS_CFSR_NOCP_S 19 +#define CPU_SCS_CFSR_NOCP 0x00080000 +#define CPU_SCS_CFSR_NOCP_BITN 19 +#define CPU_SCS_CFSR_NOCP_M 0x00080000 +#define CPU_SCS_CFSR_NOCP_S 19 // Field: [18] INVPC // // Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid // context, invalid value. The return PC points to the instruction that tried // to set the PC. -#define CPU_SCS_CFSR_INVPC 0x00040000 -#define CPU_SCS_CFSR_INVPC_BITN 18 -#define CPU_SCS_CFSR_INVPC_M 0x00040000 -#define CPU_SCS_CFSR_INVPC_S 18 +#define CPU_SCS_CFSR_INVPC 0x00040000 +#define CPU_SCS_CFSR_INVPC_BITN 18 +#define CPU_SCS_CFSR_INVPC_M 0x00040000 +#define CPU_SCS_CFSR_INVPC_S 18 // Field: [17] INVSTATE // @@ -3116,20 +3116,20 @@ // type instruction has changed state). This includes state change after entry // to or return from exception, as well as from inter-working instructions. // Return PC points to faulting instruction, with the invalid state. -#define CPU_SCS_CFSR_INVSTATE 0x00020000 -#define CPU_SCS_CFSR_INVSTATE_BITN 17 -#define CPU_SCS_CFSR_INVSTATE_M 0x00020000 -#define CPU_SCS_CFSR_INVSTATE_S 17 +#define CPU_SCS_CFSR_INVSTATE 0x00020000 +#define CPU_SCS_CFSR_INVSTATE_BITN 17 +#define CPU_SCS_CFSR_INVSTATE_M 0x00020000 +#define CPU_SCS_CFSR_INVSTATE_S 17 // Field: [16] UNDEFINSTR // // This bit is set when the processor attempts to execute an undefined // instruction. This is an instruction that the processor cannot decode. The // return PC points to the undefined instruction. -#define CPU_SCS_CFSR_UNDEFINSTR 0x00010000 -#define CPU_SCS_CFSR_UNDEFINSTR_BITN 16 -#define CPU_SCS_CFSR_UNDEFINSTR_M 0x00010000 -#define CPU_SCS_CFSR_UNDEFINSTR_S 16 +#define CPU_SCS_CFSR_UNDEFINSTR 0x00010000 +#define CPU_SCS_CFSR_UNDEFINSTR_BITN 16 +#define CPU_SCS_CFSR_UNDEFINSTR_M 0x00010000 +#define CPU_SCS_CFSR_UNDEFINSTR_S 16 // Field: [15] BFARVALID // @@ -3139,20 +3139,20 @@ // Bus fault occurs that is escalated to a Hard Fault because of priority, the // Hard Fault handler must clear this bit. This prevents problems if returning // to a stacked active Bus fault handler whose BFAR value has been overwritten. -#define CPU_SCS_CFSR_BFARVALID 0x00008000 -#define CPU_SCS_CFSR_BFARVALID_BITN 15 -#define CPU_SCS_CFSR_BFARVALID_M 0x00008000 -#define CPU_SCS_CFSR_BFARVALID_S 15 +#define CPU_SCS_CFSR_BFARVALID 0x00008000 +#define CPU_SCS_CFSR_BFARVALID_BITN 15 +#define CPU_SCS_CFSR_BFARVALID_M 0x00008000 +#define CPU_SCS_CFSR_BFARVALID_S 15 // Field: [12] STKERR // // Stacking from exception has caused one or more bus faults. The SP is still // adjusted and the values in the context area on the stack might be incorrect. // BFAR is not written. -#define CPU_SCS_CFSR_STKERR 0x00001000 -#define CPU_SCS_CFSR_STKERR_BITN 12 -#define CPU_SCS_CFSR_STKERR_M 0x00001000 -#define CPU_SCS_CFSR_STKERR_S 12 +#define CPU_SCS_CFSR_STKERR 0x00001000 +#define CPU_SCS_CFSR_STKERR_BITN 12 +#define CPU_SCS_CFSR_STKERR_M 0x00001000 +#define CPU_SCS_CFSR_STKERR_S 12 // Field: [11] UNSTKERR // @@ -3160,10 +3160,10 @@ // chained to the handler, so that the original return stack is still present. // SP is not adjusted from failing return and new save is not performed. BFAR // is not written. -#define CPU_SCS_CFSR_UNSTKERR 0x00000800 -#define CPU_SCS_CFSR_UNSTKERR_BITN 11 -#define CPU_SCS_CFSR_UNSTKERR_M 0x00000800 -#define CPU_SCS_CFSR_UNSTKERR_S 11 +#define CPU_SCS_CFSR_UNSTKERR 0x00000800 +#define CPU_SCS_CFSR_UNSTKERR_BITN 11 +#define CPU_SCS_CFSR_UNSTKERR_M 0x00000800 +#define CPU_SCS_CFSR_UNSTKERR_S 11 // Field: [10] IMPRECISERR // @@ -3174,28 +3174,28 @@ // activation. If a precise fault occurs before returning to a lower priority // exception, the handler detects both IMPRECISERR set and one of the precise // fault status bits set at the same time. BFAR is not written. -#define CPU_SCS_CFSR_IMPRECISERR 0x00000400 -#define CPU_SCS_CFSR_IMPRECISERR_BITN 10 -#define CPU_SCS_CFSR_IMPRECISERR_M 0x00000400 -#define CPU_SCS_CFSR_IMPRECISERR_S 10 +#define CPU_SCS_CFSR_IMPRECISERR 0x00000400 +#define CPU_SCS_CFSR_IMPRECISERR_BITN 10 +#define CPU_SCS_CFSR_IMPRECISERR_M 0x00000400 +#define CPU_SCS_CFSR_IMPRECISERR_S 10 // Field: [9] PRECISERR // // Precise data bus error return. -#define CPU_SCS_CFSR_PRECISERR 0x00000200 -#define CPU_SCS_CFSR_PRECISERR_BITN 9 -#define CPU_SCS_CFSR_PRECISERR_M 0x00000200 -#define CPU_SCS_CFSR_PRECISERR_S 9 +#define CPU_SCS_CFSR_PRECISERR 0x00000200 +#define CPU_SCS_CFSR_PRECISERR_BITN 9 +#define CPU_SCS_CFSR_PRECISERR_M 0x00000200 +#define CPU_SCS_CFSR_PRECISERR_S 9 // Field: [8] IBUSERR // // Instruction bus error flag. This flag is set by a prefetch error. The fault // stops on the instruction, so if the error occurs under a branch shadow, no // fault occurs. BFAR is not written. -#define CPU_SCS_CFSR_IBUSERR 0x00000100 -#define CPU_SCS_CFSR_IBUSERR_BITN 8 -#define CPU_SCS_CFSR_IBUSERR_M 0x00000100 -#define CPU_SCS_CFSR_IBUSERR_S 8 +#define CPU_SCS_CFSR_IBUSERR 0x00000100 +#define CPU_SCS_CFSR_IBUSERR_BITN 8 +#define CPU_SCS_CFSR_IBUSERR_M 0x00000100 +#define CPU_SCS_CFSR_IBUSERR_S 8 // Field: [7] MMARVALID // @@ -3204,20 +3204,20 @@ // fault occurs that is escalated to a Hard Fault because of priority, the Hard // Fault handler must clear this bit. This prevents problems on return to a // stacked active MemManage handler whose MMFAR value has been overwritten. -#define CPU_SCS_CFSR_MMARVALID 0x00000080 -#define CPU_SCS_CFSR_MMARVALID_BITN 7 -#define CPU_SCS_CFSR_MMARVALID_M 0x00000080 -#define CPU_SCS_CFSR_MMARVALID_S 7 +#define CPU_SCS_CFSR_MMARVALID 0x00000080 +#define CPU_SCS_CFSR_MMARVALID_BITN 7 +#define CPU_SCS_CFSR_MMARVALID_M 0x00000080 +#define CPU_SCS_CFSR_MMARVALID_S 7 // Field: [4] MSTKERR // // Stacking from exception has caused one or more access violations. The SP is // still adjusted and the values in the context area on the stack might be // incorrect. MMFAR is not written. -#define CPU_SCS_CFSR_MSTKERR 0x00000010 -#define CPU_SCS_CFSR_MSTKERR_BITN 4 -#define CPU_SCS_CFSR_MSTKERR_M 0x00000010 -#define CPU_SCS_CFSR_MSTKERR_S 4 +#define CPU_SCS_CFSR_MSTKERR 0x00000010 +#define CPU_SCS_CFSR_MSTKERR_BITN 4 +#define CPU_SCS_CFSR_MSTKERR_M 0x00000010 +#define CPU_SCS_CFSR_MSTKERR_S 4 // Field: [3] MUNSTKERR // @@ -3225,10 +3225,10 @@ // is chained to the handler, so that the original return stack is still // present. SP is not adjusted from failing return and new save is not // performed. MMFAR is not written. -#define CPU_SCS_CFSR_MUNSTKERR 0x00000008 -#define CPU_SCS_CFSR_MUNSTKERR_BITN 3 -#define CPU_SCS_CFSR_MUNSTKERR_M 0x00000008 -#define CPU_SCS_CFSR_MUNSTKERR_S 3 +#define CPU_SCS_CFSR_MUNSTKERR 0x00000008 +#define CPU_SCS_CFSR_MUNSTKERR_BITN 3 +#define CPU_SCS_CFSR_MUNSTKERR_M 0x00000008 +#define CPU_SCS_CFSR_MUNSTKERR_S 3 // Field: [1] DACCVIOL // @@ -3236,10 +3236,10 @@ // does not permit the operation sets this flag. The return PC points to the // faulting instruction. This error loads MMFAR with the address of the // attempted access. -#define CPU_SCS_CFSR_DACCVIOL 0x00000002 -#define CPU_SCS_CFSR_DACCVIOL_BITN 1 -#define CPU_SCS_CFSR_DACCVIOL_M 0x00000002 -#define CPU_SCS_CFSR_DACCVIOL_S 1 +#define CPU_SCS_CFSR_DACCVIOL 0x00000002 +#define CPU_SCS_CFSR_DACCVIOL_BITN 1 +#define CPU_SCS_CFSR_DACCVIOL_M 0x00000002 +#define CPU_SCS_CFSR_DACCVIOL_S 1 // Field: [0] IACCVIOL // @@ -3247,10 +3247,10 @@ // location that does not permit execution sets this flag. This occurs on any // access to an XN region, even when the MPU is disabled or not present. The // return PC points to the faulting instruction. MMFAR is not written. -#define CPU_SCS_CFSR_IACCVIOL 0x00000001 -#define CPU_SCS_CFSR_IACCVIOL_BITN 0 -#define CPU_SCS_CFSR_IACCVIOL_M 0x00000001 -#define CPU_SCS_CFSR_IACCVIOL_S 0 +#define CPU_SCS_CFSR_IACCVIOL 0x00000001 +#define CPU_SCS_CFSR_IACCVIOL_BITN 0 +#define CPU_SCS_CFSR_IACCVIOL_M 0x00000001 +#define CPU_SCS_CFSR_IACCVIOL_S 0 //***************************************************************************** // @@ -3265,10 +3265,10 @@ // both halting and monitor debug are disabled, it only happens for debug // events that are not ignored (minimally, BKPT). The Debug Fault Status // Register is updated. -#define CPU_SCS_HFSR_DEBUGEVT 0x80000000 -#define CPU_SCS_HFSR_DEBUGEVT_BITN 31 -#define CPU_SCS_HFSR_DEBUGEVT_M 0x80000000 -#define CPU_SCS_HFSR_DEBUGEVT_S 31 +#define CPU_SCS_HFSR_DEBUGEVT 0x80000000 +#define CPU_SCS_HFSR_DEBUGEVT_BITN 31 +#define CPU_SCS_HFSR_DEBUGEVT_M 0x80000000 +#define CPU_SCS_HFSR_DEBUGEVT_S 31 // Field: [30] FORCED // @@ -3276,20 +3276,20 @@ // activate because of priority or because the Configurable Fault is disabled. // The Hard Fault handler then has to read the other fault status registers to // determine cause. -#define CPU_SCS_HFSR_FORCED 0x40000000 -#define CPU_SCS_HFSR_FORCED_BITN 30 -#define CPU_SCS_HFSR_FORCED_M 0x40000000 -#define CPU_SCS_HFSR_FORCED_S 30 +#define CPU_SCS_HFSR_FORCED 0x40000000 +#define CPU_SCS_HFSR_FORCED_BITN 30 +#define CPU_SCS_HFSR_FORCED_M 0x40000000 +#define CPU_SCS_HFSR_FORCED_S 30 // Field: [1] VECTTBL // // This bit is set if there is a fault because of vector table read on // exception processing (Bus Fault). This case is always a Hard Fault. The // return PC points to the pre-empted instruction. -#define CPU_SCS_HFSR_VECTTBL 0x00000002 -#define CPU_SCS_HFSR_VECTTBL_BITN 1 -#define CPU_SCS_HFSR_VECTTBL_M 0x00000002 -#define CPU_SCS_HFSR_VECTTBL_S 1 +#define CPU_SCS_HFSR_VECTTBL 0x00000002 +#define CPU_SCS_HFSR_VECTTBL_BITN 1 +#define CPU_SCS_HFSR_VECTTBL_M 0x00000002 +#define CPU_SCS_HFSR_VECTTBL_S 1 //***************************************************************************** // @@ -3303,10 +3303,10 @@ // // 0x0: External debug request signal not asserted // 0x1: External debug request signal asserted -#define CPU_SCS_DFSR_EXTERNAL 0x00000010 -#define CPU_SCS_DFSR_EXTERNAL_BITN 4 -#define CPU_SCS_DFSR_EXTERNAL_M 0x00000010 -#define CPU_SCS_DFSR_EXTERNAL_S 4 +#define CPU_SCS_DFSR_EXTERNAL 0x00000010 +#define CPU_SCS_DFSR_EXTERNAL_BITN 4 +#define CPU_SCS_DFSR_EXTERNAL_M 0x00000010 +#define CPU_SCS_DFSR_EXTERNAL_S 4 // Field: [3] VCATCH // @@ -3315,10 +3315,10 @@ // // 0x0: No vector catch occurred // 0x1: Vector catch occurred -#define CPU_SCS_DFSR_VCATCH 0x00000008 -#define CPU_SCS_DFSR_VCATCH_BITN 3 -#define CPU_SCS_DFSR_VCATCH_M 0x00000008 -#define CPU_SCS_DFSR_VCATCH_S 3 +#define CPU_SCS_DFSR_VCATCH 0x00000008 +#define CPU_SCS_DFSR_VCATCH_BITN 3 +#define CPU_SCS_DFSR_VCATCH_M 0x00000008 +#define CPU_SCS_DFSR_VCATCH_S 3 // Field: [2] DWTTRAP // @@ -3327,10 +3327,10 @@ // // 0x0: No DWT match // 0x1: DWT match -#define CPU_SCS_DFSR_DWTTRAP 0x00000004 -#define CPU_SCS_DFSR_DWTTRAP_BITN 2 -#define CPU_SCS_DFSR_DWTTRAP_M 0x00000004 -#define CPU_SCS_DFSR_DWTTRAP_S 2 +#define CPU_SCS_DFSR_DWTTRAP 0x00000004 +#define CPU_SCS_DFSR_DWTTRAP_BITN 2 +#define CPU_SCS_DFSR_DWTTRAP_M 0x00000004 +#define CPU_SCS_DFSR_DWTTRAP_S 2 // Field: [1] BKPT // @@ -3340,10 +3340,10 @@ // // 0x0: No BKPT instruction execution // 0x1: BKPT instruction execution -#define CPU_SCS_DFSR_BKPT 0x00000002 -#define CPU_SCS_DFSR_BKPT_BITN 1 -#define CPU_SCS_DFSR_BKPT_M 0x00000002 -#define CPU_SCS_DFSR_BKPT_S 1 +#define CPU_SCS_DFSR_BKPT 0x00000002 +#define CPU_SCS_DFSR_BKPT_BITN 1 +#define CPU_SCS_DFSR_BKPT_M 0x00000002 +#define CPU_SCS_DFSR_BKPT_S 1 // Field: [0] HALTED // @@ -3351,10 +3351,10 @@ // // 0x0: No halt request // 0x1: Halt requested by NVIC, including step -#define CPU_SCS_DFSR_HALTED 0x00000001 -#define CPU_SCS_DFSR_HALTED_BITN 0 -#define CPU_SCS_DFSR_HALTED_M 0x00000001 -#define CPU_SCS_DFSR_HALTED_S 0 +#define CPU_SCS_DFSR_HALTED 0x00000001 +#define CPU_SCS_DFSR_HALTED_BITN 0 +#define CPU_SCS_DFSR_HALTED_M 0x00000001 +#define CPU_SCS_DFSR_HALTED_S 0 //***************************************************************************** // @@ -3370,9 +3370,9 @@ // address can be any offset in the range of the requested size. Flags // CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination // with CFSR.MMARVALIDindicate the cause of the fault. -#define CPU_SCS_MMFAR_ADDRESS_W 32 -#define CPU_SCS_MMFAR_ADDRESS_M 0xFFFFFFFF -#define CPU_SCS_MMFAR_ADDRESS_S 0 +#define CPU_SCS_MMFAR_ADDRESS_W 32 +#define CPU_SCS_MMFAR_ADDRESS_M 0xFFFFFFFF +#define CPU_SCS_MMFAR_ADDRESS_S 0 //***************************************************************************** // @@ -3387,9 +3387,9 @@ // Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and // CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the // fault. -#define CPU_SCS_BFAR_ADDRESS_W 32 -#define CPU_SCS_BFAR_ADDRESS_M 0xFFFFFFFF -#define CPU_SCS_BFAR_ADDRESS_S 0 +#define CPU_SCS_BFAR_ADDRESS_W 32 +#define CPU_SCS_BFAR_ADDRESS_M 0xFFFFFFFF +#define CPU_SCS_BFAR_ADDRESS_S 0 //***************************************************************************** // @@ -3400,9 +3400,9 @@ // // Implementation defined. The bits map directly onto the signal assignment to // the auxiliary fault inputs. Tied to 0 -#define CPU_SCS_AFSR_IMPDEF_W 32 -#define CPU_SCS_AFSR_IMPDEF_M 0xFFFFFFFF -#define CPU_SCS_AFSR_IMPDEF_S 0 +#define CPU_SCS_AFSR_IMPDEF_W 32 +#define CPU_SCS_AFSR_IMPDEF_M 0xFFFFFFFF +#define CPU_SCS_AFSR_IMPDEF_S 0 //***************************************************************************** // @@ -3420,9 +3420,9 @@ // instructions can be added using the appropriate instruction attribute, but // other 32-bit basic instructions cannot.) // 0x3: Thumb-2 encoding with all Thumb-2 basic instructions -#define CPU_SCS_ID_PFR0_STATE1_W 4 -#define CPU_SCS_ID_PFR0_STATE1_M 0x000000F0 -#define CPU_SCS_ID_PFR0_STATE1_S 4 +#define CPU_SCS_ID_PFR0_STATE1_W 4 +#define CPU_SCS_ID_PFR0_STATE1_M 0x000000F0 +#define CPU_SCS_ID_PFR0_STATE1_S 4 // Field: [3:0] STATE0 // @@ -3430,9 +3430,9 @@ // // 0x0: No ARM encoding // 0x1: N/A -#define CPU_SCS_ID_PFR0_STATE0_W 4 -#define CPU_SCS_ID_PFR0_STATE0_M 0x0000000F -#define CPU_SCS_ID_PFR0_STATE0_S 0 +#define CPU_SCS_ID_PFR0_STATE0_W 4 +#define CPU_SCS_ID_PFR0_STATE0_M 0x0000000F +#define CPU_SCS_ID_PFR0_STATE0_S 0 //***************************************************************************** // @@ -3445,9 +3445,9 @@ // // 0x0: Not supported // 0x2: Two-stack support -#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_W 4 -#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M 0x00000F00 -#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_S 8 +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_W 4 +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M 0x00000F00 +#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_S 8 //***************************************************************************** // @@ -3460,9 +3460,9 @@ // // 0x0: Not supported // 0x1: Microcontroller debug v1 (ITMv1 and DWTv1) -#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_W 4 -#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_M 0x00F00000 -#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_S 20 +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_W 4 +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_M 0x00F00000 +#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_S 20 //***************************************************************************** // @@ -3490,10 +3490,10 @@ // // 0x0: Not supported // 0x1: Wait for interrupt supported -#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING 0x01000000 -#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_BITN 24 -#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M 0x01000000 -#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_S 24 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING 0x01000000 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_BITN 24 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M 0x01000000 +#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_S 24 //***************************************************************************** // @@ -3544,10 +3544,10 @@ // reset still). // When writing to this register, 0 must be written this bit-field, otherwise // the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_RESET_ST 0x02000000 -#define CPU_SCS_DHCSR_S_RESET_ST_BITN 25 -#define CPU_SCS_DHCSR_S_RESET_ST_M 0x02000000 -#define CPU_SCS_DHCSR_S_RESET_ST_S 25 +#define CPU_SCS_DHCSR_S_RESET_ST 0x02000000 +#define CPU_SCS_DHCSR_S_RESET_ST_BITN 25 +#define CPU_SCS_DHCSR_S_RESET_ST_M 0x02000000 +#define CPU_SCS_DHCSR_S_RESET_ST_S 25 // Field: [24] S_RETIRE_ST // @@ -3556,10 +3556,10 @@ // load/store or fetch. // When writing to this register, 0 must be written this bit-field, otherwise // the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_RETIRE_ST 0x01000000 -#define CPU_SCS_DHCSR_S_RETIRE_ST_BITN 24 -#define CPU_SCS_DHCSR_S_RETIRE_ST_M 0x01000000 -#define CPU_SCS_DHCSR_S_RETIRE_ST_S 24 +#define CPU_SCS_DHCSR_S_RETIRE_ST 0x01000000 +#define CPU_SCS_DHCSR_S_RETIRE_ST_BITN 24 +#define CPU_SCS_DHCSR_S_RETIRE_ST_M 0x01000000 +#define CPU_SCS_DHCSR_S_RETIRE_ST_S 24 // Field: [19] S_LOCKUP // @@ -3567,10 +3567,10 @@ // present. // When writing to this register, 1 must be written this bit-field, otherwise // the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_LOCKUP 0x00080000 -#define CPU_SCS_DHCSR_S_LOCKUP_BITN 19 -#define CPU_SCS_DHCSR_S_LOCKUP_M 0x00080000 -#define CPU_SCS_DHCSR_S_LOCKUP_S 19 +#define CPU_SCS_DHCSR_S_LOCKUP 0x00080000 +#define CPU_SCS_DHCSR_S_LOCKUP_BITN 19 +#define CPU_SCS_DHCSR_S_LOCKUP_M 0x00080000 +#define CPU_SCS_DHCSR_S_LOCKUP_S 19 // Field: [18] S_SLEEP // @@ -3578,20 +3578,20 @@ // use C_HALT to gain control or wait for interrupt to wake-up. // When writing to this register, 1 must be written this bit-field, otherwise // the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_SLEEP 0x00040000 -#define CPU_SCS_DHCSR_S_SLEEP_BITN 18 -#define CPU_SCS_DHCSR_S_SLEEP_M 0x00040000 -#define CPU_SCS_DHCSR_S_SLEEP_S 18 +#define CPU_SCS_DHCSR_S_SLEEP 0x00040000 +#define CPU_SCS_DHCSR_S_SLEEP_BITN 18 +#define CPU_SCS_DHCSR_S_SLEEP_M 0x00040000 +#define CPU_SCS_DHCSR_S_SLEEP_S 18 // Field: [17] S_HALT // // The core is in debug state when this bit is set. // When writing to this register, 1 must be written this bit-field, otherwise // the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_HALT 0x00020000 -#define CPU_SCS_DHCSR_S_HALT_BITN 17 -#define CPU_SCS_DHCSR_S_HALT_M 0x00020000 -#define CPU_SCS_DHCSR_S_HALT_S 17 +#define CPU_SCS_DHCSR_S_HALT 0x00020000 +#define CPU_SCS_DHCSR_S_HALT_BITN 17 +#define CPU_SCS_DHCSR_S_HALT_M 0x00020000 +#define CPU_SCS_DHCSR_S_HALT_S 17 // Field: [16] S_REGRDY // @@ -3599,10 +3599,10 @@ // available. Last transfer is complete. // When writing to this register, 1 must be written this bit-field, otherwise // the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_REGRDY 0x00010000 -#define CPU_SCS_DHCSR_S_REGRDY_BITN 16 -#define CPU_SCS_DHCSR_S_REGRDY_M 0x00010000 -#define CPU_SCS_DHCSR_S_REGRDY_S 16 +#define CPU_SCS_DHCSR_S_REGRDY 0x00010000 +#define CPU_SCS_DHCSR_S_REGRDY_BITN 16 +#define CPU_SCS_DHCSR_S_REGRDY_M 0x00010000 +#define CPU_SCS_DHCSR_S_REGRDY_S 16 // Field: [5] C_SNAPSTALL // @@ -3612,10 +3612,10 @@ // The core reads S_RETIRE_ST as 0. This indicates that no instruction has // advanced. This prevents misuse. The bus state is Unpredictable when this is // used. S_RETIRE_ST can detect core stalls on load/store operations. -#define CPU_SCS_DHCSR_C_SNAPSTALL 0x00000020 -#define CPU_SCS_DHCSR_C_SNAPSTALL_BITN 5 -#define CPU_SCS_DHCSR_C_SNAPSTALL_M 0x00000020 -#define CPU_SCS_DHCSR_C_SNAPSTALL_S 5 +#define CPU_SCS_DHCSR_C_SNAPSTALL 0x00000020 +#define CPU_SCS_DHCSR_C_SNAPSTALL_BITN 5 +#define CPU_SCS_DHCSR_C_SNAPSTALL_M 0x00000020 +#define CPU_SCS_DHCSR_C_SNAPSTALL_S 5 // Field: [3] C_MASKINTS // @@ -3627,10 +3627,10 @@ // be separate). Modifying C_MASKINTS while the system is running with halting // debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable // behavior. -#define CPU_SCS_DHCSR_C_MASKINTS 0x00000008 -#define CPU_SCS_DHCSR_C_MASKINTS_BITN 3 -#define CPU_SCS_DHCSR_C_MASKINTS_M 0x00000008 -#define CPU_SCS_DHCSR_C_MASKINTS_S 3 +#define CPU_SCS_DHCSR_C_MASKINTS 0x00000008 +#define CPU_SCS_DHCSR_C_MASKINTS_BITN 3 +#define CPU_SCS_DHCSR_C_MASKINTS_M 0x00000008 +#define CPU_SCS_DHCSR_C_MASKINTS_S 3 // Field: [2] C_STEP // @@ -3638,19 +3638,19 @@ // Must only be modified when the processor is halted (S_HALT == 1). // Modifying C_STEP while the system is running with halting debug support // enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior. -#define CPU_SCS_DHCSR_C_STEP 0x00000004 -#define CPU_SCS_DHCSR_C_STEP_BITN 2 -#define CPU_SCS_DHCSR_C_STEP_M 0x00000004 -#define CPU_SCS_DHCSR_C_STEP_S 2 +#define CPU_SCS_DHCSR_C_STEP 0x00000004 +#define CPU_SCS_DHCSR_C_STEP_BITN 2 +#define CPU_SCS_DHCSR_C_STEP_M 0x00000004 +#define CPU_SCS_DHCSR_C_STEP_S 2 // Field: [1] C_HALT // // Halts the core. This bit is set automatically when the core Halts. For // example Breakpoint. This bit clears on core reset. -#define CPU_SCS_DHCSR_C_HALT 0x00000002 -#define CPU_SCS_DHCSR_C_HALT_BITN 1 -#define CPU_SCS_DHCSR_C_HALT_M 0x00000002 -#define CPU_SCS_DHCSR_C_HALT_S 1 +#define CPU_SCS_DHCSR_C_HALT 0x00000002 +#define CPU_SCS_DHCSR_C_HALT_BITN 1 +#define CPU_SCS_DHCSR_C_HALT_M 0x00000002 +#define CPU_SCS_DHCSR_C_HALT_S 1 // Field: [0] C_DEBUGEN // @@ -3660,10 +3660,10 @@ // The values of C_HALT, C_STEP and C_MASKINTS are ignored by hardware when // C_DEBUGEN = 0. The read values for C_HALT, C_STEP and C_MASKINTS fields will // be unknown to software when C_DEBUGEN = 0. -#define CPU_SCS_DHCSR_C_DEBUGEN 0x00000001 -#define CPU_SCS_DHCSR_C_DEBUGEN_BITN 0 -#define CPU_SCS_DHCSR_C_DEBUGEN_M 0x00000001 -#define CPU_SCS_DHCSR_C_DEBUGEN_S 0 +#define CPU_SCS_DHCSR_C_DEBUGEN 0x00000001 +#define CPU_SCS_DHCSR_C_DEBUGEN_BITN 0 +#define CPU_SCS_DHCSR_C_DEBUGEN_M 0x00000001 +#define CPU_SCS_DHCSR_C_DEBUGEN_S 0 //***************************************************************************** // @@ -3674,10 +3674,10 @@ // // 1: Write // 0: Read -#define CPU_SCS_DCRSR_REGWNR 0x00010000 -#define CPU_SCS_DCRSR_REGWNR_BITN 16 -#define CPU_SCS_DCRSR_REGWNR_M 0x00010000 -#define CPU_SCS_DCRSR_REGWNR_S 16 +#define CPU_SCS_DCRSR_REGWNR 0x00010000 +#define CPU_SCS_DCRSR_REGWNR_BITN 16 +#define CPU_SCS_DCRSR_REGWNR_M 0x00010000 +#define CPU_SCS_DCRSR_REGWNR_S 16 // Field: [4:0] REGSEL // @@ -3703,9 +3703,9 @@ // 0x11: MSP (Main SP) // 0x12: PSP (Process SP) // 0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 | PRIMASK -#define CPU_SCS_DCRSR_REGSEL_W 5 -#define CPU_SCS_DCRSR_REGSEL_M 0x0000001F -#define CPU_SCS_DCRSR_REGSEL_S 0 +#define CPU_SCS_DCRSR_REGSEL_W 5 +#define CPU_SCS_DCRSR_REGSEL_M 0x0000001F +#define CPU_SCS_DCRSR_REGSEL_S 0 //***************************************************************************** // @@ -3722,9 +3722,9 @@ // can use this register for communication in non-halting debug. This enables // flags and bits to acknowledge state and indicate if commands have been // accepted to, replied to, or accepted and replied to. -#define CPU_SCS_DCRDR_DCRDR_W 32 -#define CPU_SCS_DCRDR_DCRDR_M 0xFFFFFFFF -#define CPU_SCS_DCRDR_DCRDR_S 0 +#define CPU_SCS_DCRDR_DCRDR_W 32 +#define CPU_SCS_DCRDR_DCRDR_M 0xFFFFFFFF +#define CPU_SCS_DCRDR_DCRDR_S 0 //***************************************************************************** // @@ -3737,10 +3737,10 @@ // ITM, ETM and TPIU. This enables control of power usage unless tracing is // required. The application can enable this, for ITM use, or use by a // debugger. -#define CPU_SCS_DEMCR_TRCENA 0x01000000 -#define CPU_SCS_DEMCR_TRCENA_BITN 24 -#define CPU_SCS_DEMCR_TRCENA_M 0x01000000 -#define CPU_SCS_DEMCR_TRCENA_S 24 +#define CPU_SCS_DEMCR_TRCENA 0x01000000 +#define CPU_SCS_DEMCR_TRCENA_BITN 24 +#define CPU_SCS_DEMCR_TRCENA_M 0x01000000 +#define CPU_SCS_DEMCR_TRCENA_S 24 // Field: [19] MON_REQ // @@ -3749,10 +3749,10 @@ // // 0x0: Woken up by debug exception. // 0x1: Woken up by MON_PEND -#define CPU_SCS_DEMCR_MON_REQ 0x00080000 -#define CPU_SCS_DEMCR_MON_REQ_BITN 19 -#define CPU_SCS_DEMCR_MON_REQ_M 0x00080000 -#define CPU_SCS_DEMCR_MON_REQ_S 19 +#define CPU_SCS_DEMCR_MON_REQ 0x00080000 +#define CPU_SCS_DEMCR_MON_REQ_BITN 19 +#define CPU_SCS_DEMCR_MON_REQ_M 0x00080000 +#define CPU_SCS_DEMCR_MON_REQ_S 19 // Field: [18] MON_STEP // @@ -3760,10 +3760,10 @@ // This is the equivalent to DHCSR.C_STEP. Interrupts are only stepped // according to the priority of the monitor and settings of PRIMASK, FAULTMASK, // or BASEPRI. -#define CPU_SCS_DEMCR_MON_STEP 0x00040000 -#define CPU_SCS_DEMCR_MON_STEP_BITN 18 -#define CPU_SCS_DEMCR_MON_STEP_M 0x00040000 -#define CPU_SCS_DEMCR_MON_STEP_S 18 +#define CPU_SCS_DEMCR_MON_STEP 0x00040000 +#define CPU_SCS_DEMCR_MON_STEP_BITN 18 +#define CPU_SCS_DEMCR_MON_STEP_M 0x00040000 +#define CPU_SCS_DEMCR_MON_STEP_S 18 // Field: [17] MON_PEND // @@ -3772,10 +3772,10 @@ // Monitor debug. This register does not reset on a system reset. It is only // reset by a power-on reset. Software in the reset handler or later, or by the // DAP must enable the debug monitor. -#define CPU_SCS_DEMCR_MON_PEND 0x00020000 -#define CPU_SCS_DEMCR_MON_PEND_BITN 17 -#define CPU_SCS_DEMCR_MON_PEND_M 0x00020000 -#define CPU_SCS_DEMCR_MON_PEND_S 17 +#define CPU_SCS_DEMCR_MON_PEND 0x00020000 +#define CPU_SCS_DEMCR_MON_PEND_BITN 17 +#define CPU_SCS_DEMCR_MON_PEND_M 0x00020000 +#define CPU_SCS_DEMCR_MON_PEND_S 17 // Field: [16] MON_EN // @@ -3792,80 +3792,80 @@ // push. 2. If a late arriving interrupt comes in during vectoring, it is not // taken. That is, an implementation that supports the late arrival // optimization must suppress it in this case. -#define CPU_SCS_DEMCR_MON_EN 0x00010000 -#define CPU_SCS_DEMCR_MON_EN_BITN 16 -#define CPU_SCS_DEMCR_MON_EN_M 0x00010000 -#define CPU_SCS_DEMCR_MON_EN_S 16 +#define CPU_SCS_DEMCR_MON_EN 0x00010000 +#define CPU_SCS_DEMCR_MON_EN_BITN 16 +#define CPU_SCS_DEMCR_MON_EN_M 0x00010000 +#define CPU_SCS_DEMCR_MON_EN_S 16 // Field: [10] VC_HARDERR // // Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_HARDERR 0x00000400 -#define CPU_SCS_DEMCR_VC_HARDERR_BITN 10 -#define CPU_SCS_DEMCR_VC_HARDERR_M 0x00000400 -#define CPU_SCS_DEMCR_VC_HARDERR_S 10 +#define CPU_SCS_DEMCR_VC_HARDERR 0x00000400 +#define CPU_SCS_DEMCR_VC_HARDERR_BITN 10 +#define CPU_SCS_DEMCR_VC_HARDERR_M 0x00000400 +#define CPU_SCS_DEMCR_VC_HARDERR_S 10 // Field: [9] VC_INTERR // // Debug trap on a fault occurring during an exception entry or return // sequence. Ignored when DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_INTERR 0x00000200 -#define CPU_SCS_DEMCR_VC_INTERR_BITN 9 -#define CPU_SCS_DEMCR_VC_INTERR_M 0x00000200 -#define CPU_SCS_DEMCR_VC_INTERR_S 9 +#define CPU_SCS_DEMCR_VC_INTERR 0x00000200 +#define CPU_SCS_DEMCR_VC_INTERR_BITN 9 +#define CPU_SCS_DEMCR_VC_INTERR_M 0x00000200 +#define CPU_SCS_DEMCR_VC_INTERR_S 9 // Field: [8] VC_BUSERR // // Debug Trap on normal Bus error. Ignored when DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_BUSERR 0x00000100 -#define CPU_SCS_DEMCR_VC_BUSERR_BITN 8 -#define CPU_SCS_DEMCR_VC_BUSERR_M 0x00000100 -#define CPU_SCS_DEMCR_VC_BUSERR_S 8 +#define CPU_SCS_DEMCR_VC_BUSERR 0x00000100 +#define CPU_SCS_DEMCR_VC_BUSERR_BITN 8 +#define CPU_SCS_DEMCR_VC_BUSERR_M 0x00000100 +#define CPU_SCS_DEMCR_VC_BUSERR_S 8 // Field: [7] VC_STATERR // // Debug trap on Usage Fault state errors. Ignored when DHCSR.C_DEBUGEN is // cleared. -#define CPU_SCS_DEMCR_VC_STATERR 0x00000080 -#define CPU_SCS_DEMCR_VC_STATERR_BITN 7 -#define CPU_SCS_DEMCR_VC_STATERR_M 0x00000080 -#define CPU_SCS_DEMCR_VC_STATERR_S 7 +#define CPU_SCS_DEMCR_VC_STATERR 0x00000080 +#define CPU_SCS_DEMCR_VC_STATERR_BITN 7 +#define CPU_SCS_DEMCR_VC_STATERR_M 0x00000080 +#define CPU_SCS_DEMCR_VC_STATERR_S 7 // Field: [6] VC_CHKERR // // Debug trap on Usage Fault enabled checking errors. Ignored when // DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_CHKERR 0x00000040 -#define CPU_SCS_DEMCR_VC_CHKERR_BITN 6 -#define CPU_SCS_DEMCR_VC_CHKERR_M 0x00000040 -#define CPU_SCS_DEMCR_VC_CHKERR_S 6 +#define CPU_SCS_DEMCR_VC_CHKERR 0x00000040 +#define CPU_SCS_DEMCR_VC_CHKERR_BITN 6 +#define CPU_SCS_DEMCR_VC_CHKERR_M 0x00000040 +#define CPU_SCS_DEMCR_VC_CHKERR_S 6 // Field: [5] VC_NOCPERR // // Debug trap on a UsageFault access to a Coprocessor. Ignored when // DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_NOCPERR 0x00000020 -#define CPU_SCS_DEMCR_VC_NOCPERR_BITN 5 -#define CPU_SCS_DEMCR_VC_NOCPERR_M 0x00000020 -#define CPU_SCS_DEMCR_VC_NOCPERR_S 5 +#define CPU_SCS_DEMCR_VC_NOCPERR 0x00000020 +#define CPU_SCS_DEMCR_VC_NOCPERR_BITN 5 +#define CPU_SCS_DEMCR_VC_NOCPERR_M 0x00000020 +#define CPU_SCS_DEMCR_VC_NOCPERR_S 5 // Field: [4] VC_MMERR // // Debug trap on Memory Management faults. Ignored when DHCSR.C_DEBUGEN is // cleared. -#define CPU_SCS_DEMCR_VC_MMERR 0x00000010 -#define CPU_SCS_DEMCR_VC_MMERR_BITN 4 -#define CPU_SCS_DEMCR_VC_MMERR_M 0x00000010 -#define CPU_SCS_DEMCR_VC_MMERR_S 4 +#define CPU_SCS_DEMCR_VC_MMERR 0x00000010 +#define CPU_SCS_DEMCR_VC_MMERR_BITN 4 +#define CPU_SCS_DEMCR_VC_MMERR_M 0x00000010 +#define CPU_SCS_DEMCR_VC_MMERR_S 4 // Field: [0] VC_CORERESET // // Reset Vector Catch. Halt running system if Core reset occurs. Ignored when // DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_CORERESET 0x00000001 -#define CPU_SCS_DEMCR_VC_CORERESET_BITN 0 -#define CPU_SCS_DEMCR_VC_CORERESET_M 0x00000001 -#define CPU_SCS_DEMCR_VC_CORERESET_S 0 +#define CPU_SCS_DEMCR_VC_CORERESET 0x00000001 +#define CPU_SCS_DEMCR_VC_CORERESET_BITN 0 +#define CPU_SCS_DEMCR_VC_CORERESET_M 0x00000001 +#define CPU_SCS_DEMCR_VC_CORERESET_S 0 //***************************************************************************** // @@ -3877,9 +3877,8 @@ // Interrupt ID field. Writing a value to this bit-field is the same as // manually pending an interrupt by setting the corresponding interrupt bit in // an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1. -#define CPU_SCS_STIR_INTID_W 9 -#define CPU_SCS_STIR_INTID_M 0x000001FF -#define CPU_SCS_STIR_INTID_S 0 - +#define CPU_SCS_STIR_INTID_W 9 +#define CPU_SCS_STIR_INTID_M 0x000001FF +#define CPU_SCS_STIR_INTID_S 0 #endif // __CPU_SCS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_tiprop.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_tiprop.h index 3b011f7..c9be150 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_tiprop.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_tiprop.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_cpu_tiprop_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_cpu_tiprop_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CPU_TIPROP_H__ #define __HW_CPU_TIPROP_H__ @@ -44,10 +44,10 @@ // //***************************************************************************** // Internal -#define CPU_TIPROP_O_TRACECLKMUX 0x00000FF8 +#define CPU_TIPROP_O_TRACECLKMUX 0x00000FF8 // Internal -#define CPU_TIPROP_O_DYN_CG 0x00000FFC +#define CPU_TIPROP_O_DYN_CG 0x00000FFC //***************************************************************************** // @@ -60,12 +60,12 @@ // ENUMs: // TRACECLK Internal. Only to be used through TI provided API. // SWV Internal. Only to be used through TI provided API. -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV 0x00000001 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_BITN 0 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_M 0x00000001 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_S 0 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_TRACECLK 0x00000001 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_SWV 0x00000000 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_BITN 0 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_M 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_S 0 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_TRACECLK 0x00000001 +#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_SWV 0x00000000 //***************************************************************************** // @@ -75,9 +75,8 @@ // Field: [1:0] DYN_CG // // Internal. Only to be used through TI provided API. -#define CPU_TIPROP_DYN_CG_DYN_CG_W 2 -#define CPU_TIPROP_DYN_CG_DYN_CG_M 0x00000003 -#define CPU_TIPROP_DYN_CG_DYN_CG_S 0 - +#define CPU_TIPROP_DYN_CG_DYN_CG_W 2 +#define CPU_TIPROP_DYN_CG_DYN_CG_M 0x00000003 +#define CPU_TIPROP_DYN_CG_DYN_CG_S 0 #endif // __CPU_TIPROP__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_tpiu.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_tpiu.h index b91c2e8..ed9398b 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_tpiu.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_cpu_tpiu.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_cpu_tpiu_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_cpu_tpiu_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CPU_TPIU_H__ #define __HW_CPU_TPIU_H__ @@ -44,40 +44,40 @@ // //***************************************************************************** // Supported Sync Port Sizes -#define CPU_TPIU_O_SSPSR 0x00000000 +#define CPU_TPIU_O_SSPSR 0x00000000 // Current Sync Port Size -#define CPU_TPIU_O_CSPSR 0x00000004 +#define CPU_TPIU_O_CSPSR 0x00000004 // Async Clock Prescaler -#define CPU_TPIU_O_ACPR 0x00000010 +#define CPU_TPIU_O_ACPR 0x00000010 // Selected Pin Protocol -#define CPU_TPIU_O_SPPR 0x000000F0 +#define CPU_TPIU_O_SPPR 0x000000F0 // Formatter and Flush Status -#define CPU_TPIU_O_FFSR 0x00000300 +#define CPU_TPIU_O_FFSR 0x00000300 // Formatter and Flush Control -#define CPU_TPIU_O_FFCR 0x00000304 +#define CPU_TPIU_O_FFCR 0x00000304 // Formatter Synchronization Counter -#define CPU_TPIU_O_FSCR 0x00000308 +#define CPU_TPIU_O_FSCR 0x00000308 // Claim Tag Mask -#define CPU_TPIU_O_CLAIMMASK 0x00000FA0 +#define CPU_TPIU_O_CLAIMMASK 0x00000FA0 // Claim Tag Set -#define CPU_TPIU_O_CLAIMSET 0x00000FA0 +#define CPU_TPIU_O_CLAIMSET 0x00000FA0 // Current Claim Tag -#define CPU_TPIU_O_CLAIMTAG 0x00000FA4 +#define CPU_TPIU_O_CLAIMTAG 0x00000FA4 // Claim Tag Clear -#define CPU_TPIU_O_CLAIMCLR 0x00000FA4 +#define CPU_TPIU_O_CLAIMCLR 0x00000FA4 // Device ID -#define CPU_TPIU_O_DEVID 0x00000FC8 +#define CPU_TPIU_O_DEVID 0x00000FC8 //***************************************************************************** // @@ -90,10 +90,10 @@ // // 0x0: Not supported // 0x1: Supported -#define CPU_TPIU_SSPSR_FOUR 0x00000008 -#define CPU_TPIU_SSPSR_FOUR_BITN 3 -#define CPU_TPIU_SSPSR_FOUR_M 0x00000008 -#define CPU_TPIU_SSPSR_FOUR_S 3 +#define CPU_TPIU_SSPSR_FOUR 0x00000008 +#define CPU_TPIU_SSPSR_FOUR_BITN 3 +#define CPU_TPIU_SSPSR_FOUR_M 0x00000008 +#define CPU_TPIU_SSPSR_FOUR_S 3 // Field: [2] THREE // @@ -101,10 +101,10 @@ // // 0x0: Not supported // 0x1: Supported -#define CPU_TPIU_SSPSR_THREE 0x00000004 -#define CPU_TPIU_SSPSR_THREE_BITN 2 -#define CPU_TPIU_SSPSR_THREE_M 0x00000004 -#define CPU_TPIU_SSPSR_THREE_S 2 +#define CPU_TPIU_SSPSR_THREE 0x00000004 +#define CPU_TPIU_SSPSR_THREE_BITN 2 +#define CPU_TPIU_SSPSR_THREE_M 0x00000004 +#define CPU_TPIU_SSPSR_THREE_S 2 // Field: [1] TWO // @@ -112,10 +112,10 @@ // // 0x0: Not supported // 0x1: Supported -#define CPU_TPIU_SSPSR_TWO 0x00000002 -#define CPU_TPIU_SSPSR_TWO_BITN 1 -#define CPU_TPIU_SSPSR_TWO_M 0x00000002 -#define CPU_TPIU_SSPSR_TWO_S 1 +#define CPU_TPIU_SSPSR_TWO 0x00000002 +#define CPU_TPIU_SSPSR_TWO_BITN 1 +#define CPU_TPIU_SSPSR_TWO_M 0x00000002 +#define CPU_TPIU_SSPSR_TWO_S 1 // Field: [0] ONE // @@ -123,10 +123,10 @@ // // 0x0: Not supported // 0x1: Supported -#define CPU_TPIU_SSPSR_ONE 0x00000001 -#define CPU_TPIU_SSPSR_ONE_BITN 0 -#define CPU_TPIU_SSPSR_ONE_M 0x00000001 -#define CPU_TPIU_SSPSR_ONE_S 0 +#define CPU_TPIU_SSPSR_ONE 0x00000001 +#define CPU_TPIU_SSPSR_ONE_BITN 0 +#define CPU_TPIU_SSPSR_ONE_M 0x00000001 +#define CPU_TPIU_SSPSR_ONE_S 0 //***************************************************************************** // @@ -138,40 +138,40 @@ // 4-bit port enable // Writing values with more than one bit set in CSPSR, or setting a bit that is // not indicated as supported in SSPSR can cause Unpredictable behavior. -#define CPU_TPIU_CSPSR_FOUR 0x00000008 -#define CPU_TPIU_CSPSR_FOUR_BITN 3 -#define CPU_TPIU_CSPSR_FOUR_M 0x00000008 -#define CPU_TPIU_CSPSR_FOUR_S 3 +#define CPU_TPIU_CSPSR_FOUR 0x00000008 +#define CPU_TPIU_CSPSR_FOUR_BITN 3 +#define CPU_TPIU_CSPSR_FOUR_M 0x00000008 +#define CPU_TPIU_CSPSR_FOUR_S 3 // Field: [2] THREE // // 3-bit port enable // Writing values with more than one bit set in CSPSR, or setting a bit that is // not indicated as supported in SSPSR can cause Unpredictable behavior. -#define CPU_TPIU_CSPSR_THREE 0x00000004 -#define CPU_TPIU_CSPSR_THREE_BITN 2 -#define CPU_TPIU_CSPSR_THREE_M 0x00000004 -#define CPU_TPIU_CSPSR_THREE_S 2 +#define CPU_TPIU_CSPSR_THREE 0x00000004 +#define CPU_TPIU_CSPSR_THREE_BITN 2 +#define CPU_TPIU_CSPSR_THREE_M 0x00000004 +#define CPU_TPIU_CSPSR_THREE_S 2 // Field: [1] TWO // // 2-bit port enable // Writing values with more than one bit set in CSPSR, or setting a bit that is // not indicated as supported in SSPSR can cause Unpredictable behavior. -#define CPU_TPIU_CSPSR_TWO 0x00000002 -#define CPU_TPIU_CSPSR_TWO_BITN 1 -#define CPU_TPIU_CSPSR_TWO_M 0x00000002 -#define CPU_TPIU_CSPSR_TWO_S 1 +#define CPU_TPIU_CSPSR_TWO 0x00000002 +#define CPU_TPIU_CSPSR_TWO_BITN 1 +#define CPU_TPIU_CSPSR_TWO_M 0x00000002 +#define CPU_TPIU_CSPSR_TWO_S 1 // Field: [0] ONE // // 1-bit port enable // Writing values with more than one bit set in CSPSR, or setting a bit that is // not indicated as supported in SSPSR can cause Unpredictable behavior. -#define CPU_TPIU_CSPSR_ONE 0x00000001 -#define CPU_TPIU_CSPSR_ONE_BITN 0 -#define CPU_TPIU_CSPSR_ONE_M 0x00000001 -#define CPU_TPIU_CSPSR_ONE_S 0 +#define CPU_TPIU_CSPSR_ONE 0x00000001 +#define CPU_TPIU_CSPSR_ONE_BITN 0 +#define CPU_TPIU_CSPSR_ONE_M 0x00000001 +#define CPU_TPIU_CSPSR_ONE_S 0 //***************************************************************************** // @@ -181,9 +181,9 @@ // Field: [12:0] PRESCALER // // Divisor for input trace clock is (PRESCALER + 1). -#define CPU_TPIU_ACPR_PRESCALER_W 13 -#define CPU_TPIU_ACPR_PRESCALER_M 0x00001FFF -#define CPU_TPIU_ACPR_PRESCALER_S 0 +#define CPU_TPIU_ACPR_PRESCALER_W 13 +#define CPU_TPIU_ACPR_PRESCALER_M 0x00001FFF +#define CPU_TPIU_ACPR_PRESCALER_S 0 //***************************************************************************** // @@ -198,12 +198,12 @@ // SWO_MANCHESTER SerialWire Output (Manchester). This is the reset // value. // TRACEPORT TracePort mode -#define CPU_TPIU_SPPR_PROTOCOL_W 2 -#define CPU_TPIU_SPPR_PROTOCOL_M 0x00000003 -#define CPU_TPIU_SPPR_PROTOCOL_S 0 -#define CPU_TPIU_SPPR_PROTOCOL_SWO_NRZ 0x00000002 -#define CPU_TPIU_SPPR_PROTOCOL_SWO_MANCHESTER 0x00000001 -#define CPU_TPIU_SPPR_PROTOCOL_TRACEPORT 0x00000000 +#define CPU_TPIU_SPPR_PROTOCOL_W 2 +#define CPU_TPIU_SPPR_PROTOCOL_M 0x00000003 +#define CPU_TPIU_SPPR_PROTOCOL_S 0 +#define CPU_TPIU_SPPR_PROTOCOL_SWO_NRZ 0x00000002 +#define CPU_TPIU_SPPR_PROTOCOL_SWO_MANCHESTER 0x00000001 +#define CPU_TPIU_SPPR_PROTOCOL_TRACEPORT 0x00000000 //***************************************************************************** // @@ -214,10 +214,10 @@ // // 0: Formatter can be stopped // 1: Formatter cannot be stopped -#define CPU_TPIU_FFSR_FTNONSTOP 0x00000008 -#define CPU_TPIU_FFSR_FTNONSTOP_BITN 3 -#define CPU_TPIU_FFSR_FTNONSTOP_M 0x00000008 -#define CPU_TPIU_FFSR_FTNONSTOP_S 3 +#define CPU_TPIU_FFSR_FTNONSTOP 0x00000008 +#define CPU_TPIU_FFSR_FTNONSTOP_BITN 3 +#define CPU_TPIU_FFSR_FTNONSTOP_M 0x00000008 +#define CPU_TPIU_FFSR_FTNONSTOP_S 3 //***************************************************************************** // @@ -227,10 +227,10 @@ // Field: [8] TRIGIN // // Indicates that triggers are inserted when a trigger pin is asserted. -#define CPU_TPIU_FFCR_TRIGIN 0x00000100 -#define CPU_TPIU_FFCR_TRIGIN_BITN 8 -#define CPU_TPIU_FFCR_TRIGIN_M 0x00000100 -#define CPU_TPIU_FFCR_TRIGIN_S 8 +#define CPU_TPIU_FFCR_TRIGIN 0x00000100 +#define CPU_TPIU_FFCR_TRIGIN_BITN 8 +#define CPU_TPIU_FFCR_TRIGIN_M 0x00000100 +#define CPU_TPIU_FFCR_TRIGIN_S 8 // Field: [1] ENFCONT // @@ -238,10 +238,10 @@ // // 0: Continuous formatting disabled // 1: Continuous formatting enabled -#define CPU_TPIU_FFCR_ENFCONT 0x00000002 -#define CPU_TPIU_FFCR_ENFCONT_BITN 1 -#define CPU_TPIU_FFCR_ENFCONT_M 0x00000002 -#define CPU_TPIU_FFCR_ENFCONT_S 1 +#define CPU_TPIU_FFCR_ENFCONT 0x00000002 +#define CPU_TPIU_FFCR_ENFCONT_BITN 1 +#define CPU_TPIU_FFCR_ENFCONT_M 0x00000002 +#define CPU_TPIU_FFCR_ENFCONT_S 1 //***************************************************************************** // @@ -253,9 +253,9 @@ // The global synchronization trigger is generated by the Program Counter (PC) // Sampler block. This means that there is no synchronization counter in the // TPIU. -#define CPU_TPIU_FSCR_FSCR_W 32 -#define CPU_TPIU_FSCR_FSCR_M 0xFFFFFFFF -#define CPU_TPIU_FSCR_FSCR_S 0 +#define CPU_TPIU_FSCR_FSCR_W 32 +#define CPU_TPIU_FSCR_FSCR_M 0xFFFFFFFF +#define CPU_TPIU_FSCR_FSCR_S 0 //***************************************************************************** // @@ -272,9 +272,9 @@ // 1: This claim tag bit is not implemented // // The behavior when writing to this register is described in CLAIMSET. -#define CPU_TPIU_CLAIMMASK_CLAIMMASK_W 32 -#define CPU_TPIU_CLAIMMASK_CLAIMMASK_M 0xFFFFFFFF -#define CPU_TPIU_CLAIMMASK_CLAIMMASK_S 0 +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_W 32 +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMMASK_CLAIMMASK_S 0 //***************************************************************************** // @@ -291,9 +291,9 @@ // 1: Set this bit in the claim tag // // The behavior when reading from this location is described in CLAIMMASK. -#define CPU_TPIU_CLAIMSET_CLAIMSET_W 32 -#define CPU_TPIU_CLAIMSET_CLAIMSET_M 0xFFFFFFFF -#define CPU_TPIU_CLAIMSET_CLAIMSET_S 0 +#define CPU_TPIU_CLAIMSET_CLAIMSET_W 32 +#define CPU_TPIU_CLAIMSET_CLAIMSET_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMSET_CLAIMSET_S 0 //***************************************************************************** // @@ -307,9 +307,9 @@ // Reading CLAIMMASK determines how many bits from this register must be used. // // The behavior when writing to this register is described in CLAIMCLR. -#define CPU_TPIU_CLAIMTAG_CLAIMTAG_W 32 -#define CPU_TPIU_CLAIMTAG_CLAIMTAG_M 0xFFFFFFFF -#define CPU_TPIU_CLAIMTAG_CLAIMTAG_S 0 +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_W 32 +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMTAG_CLAIMTAG_S 0 //***************************************************************************** // @@ -326,9 +326,9 @@ // 1: Clear this bit in the claim tag. // // The behavior when reading from this location is described in CLAIMTAG. -#define CPU_TPIU_CLAIMCLR_CLAIMCLR_W 32 -#define CPU_TPIU_CLAIMCLR_CLAIMCLR_M 0xFFFFFFFF -#define CPU_TPIU_CLAIMCLR_CLAIMCLR_S 0 +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_W 32 +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_M 0xFFFFFFFF +#define CPU_TPIU_CLAIMCLR_CLAIMCLR_S 0 //***************************************************************************** // @@ -339,9 +339,8 @@ // // This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there is no // ETM present. -#define CPU_TPIU_DEVID_DEVID_W 32 -#define CPU_TPIU_DEVID_DEVID_M 0xFFFFFFFF -#define CPU_TPIU_DEVID_DEVID_S 0 - +#define CPU_TPIU_DEVID_DEVID_W 32 +#define CPU_TPIU_DEVID_DEVID_M 0xFFFFFFFF +#define CPU_TPIU_DEVID_DEVID_S 0 #endif // __CPU_TPIU__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_crypto.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_crypto.h index 80bc5fc..4693e95 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_crypto.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_crypto.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_crypto_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_crypto_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_CRYPTO_H__ #define __HW_CRYPTO_H__ @@ -44,160 +44,160 @@ // //***************************************************************************** // DMA Channel 0 Control -#define CRYPTO_O_DMACH0CTL 0x00000000 +#define CRYPTO_O_DMACH0CTL 0x00000000 // DMA Channel 0 External Address -#define CRYPTO_O_DMACH0EXTADDR 0x00000004 +#define CRYPTO_O_DMACH0EXTADDR 0x00000004 // DMA Channel 0 Length -#define CRYPTO_O_DMACH0LEN 0x0000000C +#define CRYPTO_O_DMACH0LEN 0x0000000C // DMA Controller Status -#define CRYPTO_O_DMASTAT 0x00000018 +#define CRYPTO_O_DMASTAT 0x00000018 // DMA Controller Software Reset -#define CRYPTO_O_DMASWRESET 0x0000001C +#define CRYPTO_O_DMASWRESET 0x0000001C // DMA Channel 1 Control -#define CRYPTO_O_DMACH1CTL 0x00000020 +#define CRYPTO_O_DMACH1CTL 0x00000020 // DMA Channel 1 External Address -#define CRYPTO_O_DMACH1EXTADDR 0x00000024 +#define CRYPTO_O_DMACH1EXTADDR 0x00000024 // DMA Channel 1 Length -#define CRYPTO_O_DMACH1LEN 0x0000002C +#define CRYPTO_O_DMACH1LEN 0x0000002C // DMA Controller Master Configuration -#define CRYPTO_O_DMABUSCFG 0x00000078 +#define CRYPTO_O_DMABUSCFG 0x00000078 // DMA Controller Port Error -#define CRYPTO_O_DMAPORTERR 0x0000007C +#define CRYPTO_O_DMAPORTERR 0x0000007C // DMA Controller Version -#define CRYPTO_O_DMAHWVER 0x000000FC +#define CRYPTO_O_DMAHWVER 0x000000FC // Key Write Area -#define CRYPTO_O_KEYWRITEAREA 0x00000400 +#define CRYPTO_O_KEYWRITEAREA 0x00000400 // Key Written Area Status -#define CRYPTO_O_KEYWRITTENAREA 0x00000404 +#define CRYPTO_O_KEYWRITTENAREA 0x00000404 // Key Size -#define CRYPTO_O_KEYSIZE 0x00000408 +#define CRYPTO_O_KEYSIZE 0x00000408 // Key Read Area -#define CRYPTO_O_KEYREADAREA 0x0000040C +#define CRYPTO_O_KEYREADAREA 0x0000040C // Clear AES_KEY2/GHASH Key -#define CRYPTO_O_AESKEY20 0x00000500 +#define CRYPTO_O_AESKEY20 0x00000500 // Clear AES_KEY2/GHASH Key -#define CRYPTO_O_AESKEY21 0x00000504 +#define CRYPTO_O_AESKEY21 0x00000504 // Clear AES_KEY2/GHASH Key -#define CRYPTO_O_AESKEY22 0x00000508 +#define CRYPTO_O_AESKEY22 0x00000508 // Clear AES_KEY2/GHASH Key -#define CRYPTO_O_AESKEY23 0x0000050C +#define CRYPTO_O_AESKEY23 0x0000050C // Clear AES_KEY3 -#define CRYPTO_O_AESKEY30 0x00000510 +#define CRYPTO_O_AESKEY30 0x00000510 // Clear AES_KEY3 -#define CRYPTO_O_AESKEY31 0x00000514 +#define CRYPTO_O_AESKEY31 0x00000514 // Clear AES_KEY3 -#define CRYPTO_O_AESKEY32 0x00000518 +#define CRYPTO_O_AESKEY32 0x00000518 // Clear AES_KEY3 -#define CRYPTO_O_AESKEY33 0x0000051C +#define CRYPTO_O_AESKEY33 0x0000051C // AES Initialization Vector -#define CRYPTO_O_AESIV0 0x00000540 +#define CRYPTO_O_AESIV0 0x00000540 // AES Initialization Vector -#define CRYPTO_O_AESIV1 0x00000544 +#define CRYPTO_O_AESIV1 0x00000544 // AES Initialization Vector -#define CRYPTO_O_AESIV2 0x00000548 +#define CRYPTO_O_AESIV2 0x00000548 // AES Initialization Vector -#define CRYPTO_O_AESIV3 0x0000054C +#define CRYPTO_O_AESIV3 0x0000054C // AES Input/Output Buffer Control -#define CRYPTO_O_AESCTL 0x00000550 +#define CRYPTO_O_AESCTL 0x00000550 // Crypto Data Length LSW -#define CRYPTO_O_AESDATALEN0 0x00000554 +#define CRYPTO_O_AESDATALEN0 0x00000554 // Crypto Data Length MSW -#define CRYPTO_O_AESDATALEN1 0x00000558 +#define CRYPTO_O_AESDATALEN1 0x00000558 // AES Authentication Length -#define CRYPTO_O_AESAUTHLEN 0x0000055C +#define CRYPTO_O_AESAUTHLEN 0x0000055C // Data Input/Output -#define CRYPTO_O_AESDATAOUT0 0x00000560 +#define CRYPTO_O_AESDATAOUT0 0x00000560 // AES Data Input/Output 0 -#define CRYPTO_O_AESDATAIN0 0x00000560 +#define CRYPTO_O_AESDATAIN0 0x00000560 // AES Data Input/Output 3 -#define CRYPTO_O_AESDATAOUT1 0x00000564 +#define CRYPTO_O_AESDATAOUT1 0x00000564 // AES Data Input/Output 1 -#define CRYPTO_O_AESDATAIN1 0x00000564 +#define CRYPTO_O_AESDATAIN1 0x00000564 // AES Data Input/Output 2 -#define CRYPTO_O_AESDATAOUT2 0x00000568 +#define CRYPTO_O_AESDATAOUT2 0x00000568 // AES Data Input/Output 2 -#define CRYPTO_O_AESDATAIN2 0x00000568 +#define CRYPTO_O_AESDATAIN2 0x00000568 // AES Data Input/Output 3 -#define CRYPTO_O_AESDATAOUT3 0x0000056C +#define CRYPTO_O_AESDATAOUT3 0x0000056C // Data Input/Output -#define CRYPTO_O_AESDATAIN3 0x0000056C +#define CRYPTO_O_AESDATAIN3 0x0000056C // AES Tag Output -#define CRYPTO_O_AESTAGOUT0 0x00000570 +#define CRYPTO_O_AESTAGOUT0 0x00000570 // AES Tag Output -#define CRYPTO_O_AESTAGOUT1 0x00000574 +#define CRYPTO_O_AESTAGOUT1 0x00000574 // AES Tag Output -#define CRYPTO_O_AESTAGOUT2 0x00000578 +#define CRYPTO_O_AESTAGOUT2 0x00000578 // AES Tag Output -#define CRYPTO_O_AESTAGOUT3 0x0000057C +#define CRYPTO_O_AESTAGOUT3 0x0000057C // Master Algorithm Select -#define CRYPTO_O_ALGSEL 0x00000700 +#define CRYPTO_O_ALGSEL 0x00000700 // Master Protection Control -#define CRYPTO_O_DMAPROTCTL 0x00000704 +#define CRYPTO_O_DMAPROTCTL 0x00000704 // Software Reset -#define CRYPTO_O_SWRESET 0x00000740 +#define CRYPTO_O_SWRESET 0x00000740 // Control Interrupt Configuration -#define CRYPTO_O_IRQTYPE 0x00000780 +#define CRYPTO_O_IRQTYPE 0x00000780 // Interrupt Enable -#define CRYPTO_O_IRQEN 0x00000784 +#define CRYPTO_O_IRQEN 0x00000784 // Interrupt Clear -#define CRYPTO_O_IRQCLR 0x00000788 +#define CRYPTO_O_IRQCLR 0x00000788 // Interrupt Set -#define CRYPTO_O_IRQSET 0x0000078C +#define CRYPTO_O_IRQSET 0x0000078C // Interrupt Status -#define CRYPTO_O_IRQSTAT 0x00000790 +#define CRYPTO_O_IRQSTAT 0x00000790 // CTRL Module Version -#define CRYPTO_O_HWVER 0x000007FC +#define CRYPTO_O_HWVER 0x000007FC //***************************************************************************** // @@ -215,12 +215,12 @@ // ENUMs: // HIGH Priority high // LOW Priority low -#define CRYPTO_DMACH0CTL_PRIO 0x00000002 -#define CRYPTO_DMACH0CTL_PRIO_BITN 1 -#define CRYPTO_DMACH0CTL_PRIO_M 0x00000002 -#define CRYPTO_DMACH0CTL_PRIO_S 1 -#define CRYPTO_DMACH0CTL_PRIO_HIGH 0x00000002 -#define CRYPTO_DMACH0CTL_PRIO_LOW 0x00000000 +#define CRYPTO_DMACH0CTL_PRIO 0x00000002 +#define CRYPTO_DMACH0CTL_PRIO_BITN 1 +#define CRYPTO_DMACH0CTL_PRIO_M 0x00000002 +#define CRYPTO_DMACH0CTL_PRIO_S 1 +#define CRYPTO_DMACH0CTL_PRIO_HIGH 0x00000002 +#define CRYPTO_DMACH0CTL_PRIO_LOW 0x00000000 // Field: [0] EN // @@ -228,12 +228,12 @@ // ENUMs: // EN Channel enabled // DIS Channel disabled -#define CRYPTO_DMACH0CTL_EN 0x00000001 -#define CRYPTO_DMACH0CTL_EN_BITN 0 -#define CRYPTO_DMACH0CTL_EN_M 0x00000001 -#define CRYPTO_DMACH0CTL_EN_S 0 -#define CRYPTO_DMACH0CTL_EN_EN 0x00000001 -#define CRYPTO_DMACH0CTL_EN_DIS 0x00000000 +#define CRYPTO_DMACH0CTL_EN 0x00000001 +#define CRYPTO_DMACH0CTL_EN_BITN 0 +#define CRYPTO_DMACH0CTL_EN_M 0x00000001 +#define CRYPTO_DMACH0CTL_EN_S 0 +#define CRYPTO_DMACH0CTL_EN_EN 0x00000001 +#define CRYPTO_DMACH0CTL_EN_DIS 0x00000000 //***************************************************************************** // @@ -245,9 +245,9 @@ // Channel external address value. // Holds the last updated external address after being sent to the master // interface. -#define CRYPTO_DMACH0EXTADDR_ADDR_W 32 -#define CRYPTO_DMACH0EXTADDR_ADDR_M 0xFFFFFFFF -#define CRYPTO_DMACH0EXTADDR_ADDR_S 0 +#define CRYPTO_DMACH0EXTADDR_ADDR_W 32 +#define CRYPTO_DMACH0EXTADDR_ADDR_M 0xFFFFFFFF +#define CRYPTO_DMACH0EXTADDR_ADDR_S 0 //***************************************************************************** // @@ -262,9 +262,9 @@ // transfer length after being sent to the master interface. // Note: Writing a non-zero value to this register field starts the transfer if // the channel is enabled by setting DMACH0CTL.EN. -#define CRYPTO_DMACH0LEN_LEN_W 16 -#define CRYPTO_DMACH0LEN_LEN_M 0x0000FFFF -#define CRYPTO_DMACH0LEN_LEN_S 0 +#define CRYPTO_DMACH0LEN_LEN_W 16 +#define CRYPTO_DMACH0LEN_LEN_M 0x0000FFFF +#define CRYPTO_DMACH0LEN_LEN_S 0 //***************************************************************************** // @@ -274,30 +274,30 @@ // Field: [17] PORT_ERR // // Reflects possible transfer errors on the AHB port. -#define CRYPTO_DMASTAT_PORT_ERR 0x00020000 -#define CRYPTO_DMASTAT_PORT_ERR_BITN 17 -#define CRYPTO_DMASTAT_PORT_ERR_M 0x00020000 -#define CRYPTO_DMASTAT_PORT_ERR_S 17 +#define CRYPTO_DMASTAT_PORT_ERR 0x00020000 +#define CRYPTO_DMASTAT_PORT_ERR_BITN 17 +#define CRYPTO_DMASTAT_PORT_ERR_M 0x00020000 +#define CRYPTO_DMASTAT_PORT_ERR_S 17 // Field: [1] CH1_ACTIVE // // This register field indicates if DMA channel 1 is active or not. // 0: Not active // 1: Active -#define CRYPTO_DMASTAT_CH1_ACTIVE 0x00000002 -#define CRYPTO_DMASTAT_CH1_ACTIVE_BITN 1 -#define CRYPTO_DMASTAT_CH1_ACTIVE_M 0x00000002 -#define CRYPTO_DMASTAT_CH1_ACTIVE_S 1 +#define CRYPTO_DMASTAT_CH1_ACTIVE 0x00000002 +#define CRYPTO_DMASTAT_CH1_ACTIVE_BITN 1 +#define CRYPTO_DMASTAT_CH1_ACTIVE_M 0x00000002 +#define CRYPTO_DMASTAT_CH1_ACTIVE_S 1 // Field: [0] CH0_ACTIVE // // This register field indicates if DMA channel 0 is active or not. // 0: Not active // 1: Active -#define CRYPTO_DMASTAT_CH0_ACTIVE 0x00000001 -#define CRYPTO_DMASTAT_CH0_ACTIVE_BITN 0 -#define CRYPTO_DMASTAT_CH0_ACTIVE_M 0x00000001 -#define CRYPTO_DMASTAT_CH0_ACTIVE_S 0 +#define CRYPTO_DMASTAT_CH0_ACTIVE 0x00000001 +#define CRYPTO_DMASTAT_CH0_ACTIVE_BITN 0 +#define CRYPTO_DMASTAT_CH0_ACTIVE_M 0x00000001 +#define CRYPTO_DMASTAT_CH0_ACTIVE_S 0 //***************************************************************************** // @@ -313,10 +313,10 @@ // // Note: Completion of the software reset must be checked in DMASTAT.CH0_ACTIVE // and DMASTAT.CH1_ACTIVE. -#define CRYPTO_DMASWRESET_RESET 0x00000001 -#define CRYPTO_DMASWRESET_RESET_BITN 0 -#define CRYPTO_DMASWRESET_RESET_M 0x00000001 -#define CRYPTO_DMASWRESET_RESET_S 0 +#define CRYPTO_DMASWRESET_RESET 0x00000001 +#define CRYPTO_DMASWRESET_RESET_BITN 0 +#define CRYPTO_DMASWRESET_RESET_M 0x00000001 +#define CRYPTO_DMASWRESET_RESET_S 0 //***************************************************************************** // @@ -334,12 +334,12 @@ // ENUMs: // HIGH Priority high // LOW Priority low -#define CRYPTO_DMACH1CTL_PRIO 0x00000002 -#define CRYPTO_DMACH1CTL_PRIO_BITN 1 -#define CRYPTO_DMACH1CTL_PRIO_M 0x00000002 -#define CRYPTO_DMACH1CTL_PRIO_S 1 -#define CRYPTO_DMACH1CTL_PRIO_HIGH 0x00000002 -#define CRYPTO_DMACH1CTL_PRIO_LOW 0x00000000 +#define CRYPTO_DMACH1CTL_PRIO 0x00000002 +#define CRYPTO_DMACH1CTL_PRIO_BITN 1 +#define CRYPTO_DMACH1CTL_PRIO_M 0x00000002 +#define CRYPTO_DMACH1CTL_PRIO_S 1 +#define CRYPTO_DMACH1CTL_PRIO_HIGH 0x00000002 +#define CRYPTO_DMACH1CTL_PRIO_LOW 0x00000000 // Field: [0] EN // @@ -351,12 +351,12 @@ // ENUMs: // EN Channel enabled // DIS Channel disabled -#define CRYPTO_DMACH1CTL_EN 0x00000001 -#define CRYPTO_DMACH1CTL_EN_BITN 0 -#define CRYPTO_DMACH1CTL_EN_M 0x00000001 -#define CRYPTO_DMACH1CTL_EN_S 0 -#define CRYPTO_DMACH1CTL_EN_EN 0x00000001 -#define CRYPTO_DMACH1CTL_EN_DIS 0x00000000 +#define CRYPTO_DMACH1CTL_EN 0x00000001 +#define CRYPTO_DMACH1CTL_EN_BITN 0 +#define CRYPTO_DMACH1CTL_EN_M 0x00000001 +#define CRYPTO_DMACH1CTL_EN_S 0 +#define CRYPTO_DMACH1CTL_EN_EN 0x00000001 +#define CRYPTO_DMACH1CTL_EN_DIS 0x00000000 //***************************************************************************** // @@ -368,9 +368,9 @@ // Channel external address value. // Holds the last updated external address after being sent to the master // interface. -#define CRYPTO_DMACH1EXTADDR_ADDR_W 32 -#define CRYPTO_DMACH1EXTADDR_ADDR_M 0xFFFFFFFF -#define CRYPTO_DMACH1EXTADDR_ADDR_S 0 +#define CRYPTO_DMACH1EXTADDR_ADDR_W 32 +#define CRYPTO_DMACH1EXTADDR_ADDR_M 0xFFFFFFFF +#define CRYPTO_DMACH1EXTADDR_ADDR_S 0 //***************************************************************************** // @@ -385,9 +385,9 @@ // transfer length after being sent to the master interface. // Note: Writing a non-zero value to this register field starts the transfer if // the channel is enabled by setting DMACH1CTL.EN. -#define CRYPTO_DMACH1LEN_LEN_W 16 -#define CRYPTO_DMACH1LEN_LEN_M 0x0000FFFF -#define CRYPTO_DMACH1LEN_LEN_S 0 +#define CRYPTO_DMACH1LEN_LEN_W 16 +#define CRYPTO_DMACH1LEN_LEN_M 0x0000FFFF +#define CRYPTO_DMACH1LEN_LEN_S 0 //***************************************************************************** // @@ -403,14 +403,14 @@ // 16_BYTE 16 bytes // 8_BYTE 8 bytes // 4_BYTE 4 bytes -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_W 4 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_M 0x0000F000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_S 12 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_64_BYTE 0x00006000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_32_BYTE 0x00005000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_16_BYTE 0x00004000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_8_BYTE 0x00003000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_4_BYTE 0x00002000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_W 4 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_M 0x0000F000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_S 12 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_64_BYTE 0x00006000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_32_BYTE 0x00005000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_16_BYTE 0x00004000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_8_BYTE 0x00003000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_4_BYTE 0x00002000 // Field: [11] AHB_MST1_IDLE_EN // @@ -418,12 +418,12 @@ // ENUMs: // IDLE Idle transfer insertion enabled // NO_IDLE Do not insert idle transfers. -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN 0x00000800 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_BITN 11 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_M 0x00000800 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_S 11 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_IDLE 0x00000800 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_NO_IDLE 0x00000000 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_BITN 11 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_M 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_S 11 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_IDLE 0x00000800 +#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_NO_IDLE 0x00000000 // Field: [10] AHB_MST1_INCR_EN // @@ -431,12 +431,12 @@ // ENUMs: // SPECIFIED Fixed length bursts or single transfers // UNSPECIFIED Unspecified length burst transfers -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN 0x00000400 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_BITN 10 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_M 0x00000400 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_S 10 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_SPECIFIED 0x00000400 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_UNSPECIFIED 0x00000000 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_BITN 10 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_M 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_S 10 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_SPECIFIED 0x00000400 +#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_UNSPECIFIED 0x00000000 // Field: [9] AHB_MST1_LOCK_EN // @@ -444,12 +444,12 @@ // ENUMs: // LOCKED Transfers are locked // NOT_LOCKED Transfers are not locked -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN 0x00000200 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_BITN 9 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_M 0x00000200 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_S 9 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_LOCKED 0x00000200 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_NOT_LOCKED 0x00000000 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_BITN 9 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_M 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_S 9 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_LOCKED 0x00000200 +#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_NOT_LOCKED 0x00000000 // Field: [8] AHB_MST1_BIGEND // @@ -457,12 +457,12 @@ // ENUMs: // BIG_ENDIAN Big Endian // LITTLE_ENDIAN Little Endian -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND 0x00000100 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BITN 8 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_M 0x00000100 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_S 8 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BIG_ENDIAN 0x00000100 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_LITTLE_ENDIAN 0x00000000 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BITN 8 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_M 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_S 8 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BIG_ENDIAN 0x00000100 +#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_LITTLE_ENDIAN 0x00000000 //***************************************************************************** // @@ -472,19 +472,19 @@ // Field: [12] AHB_ERR // // A 1 indicates that the Crypto peripheral has detected an AHB bus error -#define CRYPTO_DMAPORTERR_AHB_ERR 0x00001000 -#define CRYPTO_DMAPORTERR_AHB_ERR_BITN 12 -#define CRYPTO_DMAPORTERR_AHB_ERR_M 0x00001000 -#define CRYPTO_DMAPORTERR_AHB_ERR_S 12 +#define CRYPTO_DMAPORTERR_AHB_ERR 0x00001000 +#define CRYPTO_DMAPORTERR_AHB_ERR_BITN 12 +#define CRYPTO_DMAPORTERR_AHB_ERR_M 0x00001000 +#define CRYPTO_DMAPORTERR_AHB_ERR_S 12 // Field: [9] LAST_CH // // Indicates which channel was serviced last (channel 0 or channel 1) by the // AHB master port. -#define CRYPTO_DMAPORTERR_LAST_CH 0x00000200 -#define CRYPTO_DMAPORTERR_LAST_CH_BITN 9 -#define CRYPTO_DMAPORTERR_LAST_CH_M 0x00000200 -#define CRYPTO_DMAPORTERR_LAST_CH_S 9 +#define CRYPTO_DMAPORTERR_LAST_CH 0x00000200 +#define CRYPTO_DMAPORTERR_LAST_CH_BITN 9 +#define CRYPTO_DMAPORTERR_LAST_CH_M 0x00000200 +#define CRYPTO_DMAPORTERR_LAST_CH_S 9 //***************************************************************************** // @@ -494,37 +494,37 @@ // Field: [27:24] HW_MAJOR_VER // // Major version number -#define CRYPTO_DMAHWVER_HW_MAJOR_VER_W 4 -#define CRYPTO_DMAHWVER_HW_MAJOR_VER_M 0x0F000000 -#define CRYPTO_DMAHWVER_HW_MAJOR_VER_S 24 +#define CRYPTO_DMAHWVER_HW_MAJOR_VER_W 4 +#define CRYPTO_DMAHWVER_HW_MAJOR_VER_M 0x0F000000 +#define CRYPTO_DMAHWVER_HW_MAJOR_VER_S 24 // Field: [23:20] HW_MINOR_VER // // Minor version number -#define CRYPTO_DMAHWVER_HW_MINOR_VER_W 4 -#define CRYPTO_DMAHWVER_HW_MINOR_VER_M 0x00F00000 -#define CRYPTO_DMAHWVER_HW_MINOR_VER_S 20 +#define CRYPTO_DMAHWVER_HW_MINOR_VER_W 4 +#define CRYPTO_DMAHWVER_HW_MINOR_VER_M 0x00F00000 +#define CRYPTO_DMAHWVER_HW_MINOR_VER_S 20 // Field: [19:16] HW_PATCH_LVL // // Patch level. -#define CRYPTO_DMAHWVER_HW_PATCH_LVL_W 4 -#define CRYPTO_DMAHWVER_HW_PATCH_LVL_M 0x000F0000 -#define CRYPTO_DMAHWVER_HW_PATCH_LVL_S 16 +#define CRYPTO_DMAHWVER_HW_PATCH_LVL_W 4 +#define CRYPTO_DMAHWVER_HW_PATCH_LVL_M 0x000F0000 +#define CRYPTO_DMAHWVER_HW_PATCH_LVL_S 16 // Field: [15:8] VER_NUM_COMPL // // Bit-by-bit complement of the VER_NUM field bits. -#define CRYPTO_DMAHWVER_VER_NUM_COMPL_W 8 -#define CRYPTO_DMAHWVER_VER_NUM_COMPL_M 0x0000FF00 -#define CRYPTO_DMAHWVER_VER_NUM_COMPL_S 8 +#define CRYPTO_DMAHWVER_VER_NUM_COMPL_W 8 +#define CRYPTO_DMAHWVER_VER_NUM_COMPL_M 0x0000FF00 +#define CRYPTO_DMAHWVER_VER_NUM_COMPL_S 8 // Field: [7:0] VER_NUM // // Version number of the DMA Controller (209) -#define CRYPTO_DMAHWVER_VER_NUM_W 8 -#define CRYPTO_DMAHWVER_VER_NUM_M 0x000000FF -#define CRYPTO_DMAHWVER_VER_NUM_S 0 +#define CRYPTO_DMAHWVER_VER_NUM_W 8 +#define CRYPTO_DMAHWVER_VER_NUM_M 0x000000FF +#define CRYPTO_DMAHWVER_VER_NUM_S 0 //***************************************************************************** // @@ -541,12 +541,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA7 0x00000080 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_BITN 7 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_M 0x00000080 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_S 7 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_SEL 0x00000080 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_BITN 7 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_M 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_S 7 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_SEL 0x00000080 +#define CRYPTO_KEYWRITEAREA_RAM_AREA7_NOT_SEL 0x00000000 // Field: [6] RAM_AREA6 // @@ -558,12 +558,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA6 0x00000040 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_BITN 6 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_M 0x00000040 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_S 6 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_SEL 0x00000040 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_BITN 6 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_M 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_S 6 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_SEL 0x00000040 +#define CRYPTO_KEYWRITEAREA_RAM_AREA6_NOT_SEL 0x00000000 // Field: [5] RAM_AREA5 // @@ -575,12 +575,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA5 0x00000020 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_BITN 5 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_M 0x00000020 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_S 5 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_SEL 0x00000020 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_BITN 5 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_M 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_S 5 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_SEL 0x00000020 +#define CRYPTO_KEYWRITEAREA_RAM_AREA5_NOT_SEL 0x00000000 // Field: [4] RAM_AREA4 // @@ -592,12 +592,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA4 0x00000010 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_BITN 4 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_M 0x00000010 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_S 4 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_SEL 0x00000010 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_BITN 4 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_M 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_S 4 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_SEL 0x00000010 +#define CRYPTO_KEYWRITEAREA_RAM_AREA4_NOT_SEL 0x00000000 // Field: [3] RAM_AREA3 // @@ -609,12 +609,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA3 0x00000008 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_BITN 3 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_M 0x00000008 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_S 3 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_SEL 0x00000008 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_BITN 3 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_M 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_S 3 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_SEL 0x00000008 +#define CRYPTO_KEYWRITEAREA_RAM_AREA3_NOT_SEL 0x00000000 // Field: [2] RAM_AREA2 // @@ -626,12 +626,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA2 0x00000004 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_BITN 2 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_M 0x00000004 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_S 2 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_SEL 0x00000004 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_BITN 2 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_M 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_S 2 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_SEL 0x00000004 +#define CRYPTO_KEYWRITEAREA_RAM_AREA2_NOT_SEL 0x00000000 // Field: [1] RAM_AREA1 // @@ -643,12 +643,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA1 0x00000002 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_BITN 1 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_M 0x00000002 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_S 1 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_SEL 0x00000002 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_BITN 1 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_M 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_S 1 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_SEL 0x00000002 +#define CRYPTO_KEYWRITEAREA_RAM_AREA1_NOT_SEL 0x00000000 // Field: [0] RAM_AREA0 // @@ -660,12 +660,12 @@ // ENUMs: // SEL This RAM area is selected to be written // NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA0 0x00000001 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_BITN 0 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_M 0x00000001 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_S 0 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_SEL 0x00000001 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_NOT_SEL 0x00000000 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_BITN 0 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_M 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_S 0 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_SEL 0x00000001 +#define CRYPTO_KEYWRITEAREA_RAM_AREA0_NOT_SEL 0x00000000 //***************************************************************************** // @@ -686,12 +686,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7 0x00000080 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_BITN 7 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_M 0x00000080 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_S 7 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_WRITTEN 0x00000080 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_BITN 7 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_M 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_S 7 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_WRITTEN 0x00000080 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_NOT_WRITTEN 0x00000000 // Field: [6] RAM_AREA_WRITTEN6 // @@ -707,12 +707,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6 0x00000040 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_BITN 6 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_M 0x00000040 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_S 6 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_WRITTEN 0x00000040 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_BITN 6 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_M 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_S 6 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_WRITTEN 0x00000040 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_NOT_WRITTEN 0x00000000 // Field: [5] RAM_AREA_WRITTEN5 // @@ -728,12 +728,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5 0x00000020 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_BITN 5 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_M 0x00000020 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_S 5 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_WRITTEN 0x00000020 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_BITN 5 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_M 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_S 5 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_WRITTEN 0x00000020 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_NOT_WRITTEN 0x00000000 // Field: [4] RAM_AREA_WRITTEN4 // @@ -749,12 +749,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4 0x00000010 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_BITN 4 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_M 0x00000010 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_S 4 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_WRITTEN 0x00000010 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_BITN 4 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_M 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_S 4 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_WRITTEN 0x00000010 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_NOT_WRITTEN 0x00000000 // Field: [3] RAM_AREA_WRITTEN3 // @@ -770,12 +770,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3 0x00000008 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_BITN 3 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_M 0x00000008 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_S 3 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_WRITTEN 0x00000008 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_BITN 3 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_M 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_S 3 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_WRITTEN 0x00000008 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_NOT_WRITTEN 0x00000000 // Field: [2] RAM_AREA_WRITTEN2 // @@ -791,12 +791,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2 0x00000004 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_BITN 2 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_M 0x00000004 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_S 2 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_WRITTEN 0x00000004 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_BITN 2 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_M 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_S 2 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_WRITTEN 0x00000004 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_NOT_WRITTEN 0x00000000 // Field: [1] RAM_AREA_WRITTEN1 // @@ -812,12 +812,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1 0x00000002 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_BITN 1 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_M 0x00000002 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_S 1 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_WRITTEN 0x00000002 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_BITN 1 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_M 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_S 1 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_WRITTEN 0x00000002 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_NOT_WRITTEN 0x00000000 // Field: [0] RAM_AREA_WRITTEN0 // @@ -834,12 +834,12 @@ // information // NOT_WRITTEN This RAM area is not written with valid key // information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0 0x00000001 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_BITN 0 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_M 0x00000001 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_S 0 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_WRITTEN 0x00000001 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_NOT_WRITTEN 0x00000000 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0 0x00000001 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_BITN 0 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_M 0x00000001 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_S 0 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_WRITTEN 0x00000001 +#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_NOT_WRITTEN 0x00000000 //***************************************************************************** // @@ -859,12 +859,12 @@ // 256_BIT Not supported // 192_BIT Not supported // 128_BIT 128 bits -#define CRYPTO_KEYSIZE_SIZE_W 2 -#define CRYPTO_KEYSIZE_SIZE_M 0x00000003 -#define CRYPTO_KEYSIZE_SIZE_S 0 -#define CRYPTO_KEYSIZE_SIZE_256_BIT 0x00000003 -#define CRYPTO_KEYSIZE_SIZE_192_BIT 0x00000002 -#define CRYPTO_KEYSIZE_SIZE_128_BIT 0x00000001 +#define CRYPTO_KEYSIZE_SIZE_W 2 +#define CRYPTO_KEYSIZE_SIZE_M 0x00000003 +#define CRYPTO_KEYSIZE_SIZE_S 0 +#define CRYPTO_KEYSIZE_SIZE_256_BIT 0x00000003 +#define CRYPTO_KEYSIZE_SIZE_192_BIT 0x00000002 +#define CRYPTO_KEYSIZE_SIZE_128_BIT 0x00000001 //***************************************************************************** // @@ -877,10 +877,10 @@ // // 0: operation is completed. // 1: operation is not completed and the key store is busy. -#define CRYPTO_KEYREADAREA_BUSY 0x80000000 -#define CRYPTO_KEYREADAREA_BUSY_BITN 31 -#define CRYPTO_KEYREADAREA_BUSY_M 0x80000000 -#define CRYPTO_KEYREADAREA_BUSY_S 31 +#define CRYPTO_KEYREADAREA_BUSY 0x80000000 +#define CRYPTO_KEYREADAREA_BUSY_BITN 31 +#define CRYPTO_KEYREADAREA_BUSY_M 0x80000000 +#define CRYPTO_KEYREADAREA_BUSY_S 31 // Field: [3:0] RAM_AREA // @@ -898,18 +898,18 @@ // RAM_AREA2 RAM Area 2 // RAM_AREA1 RAM Area 1 // RAM_AREA0 RAM Area 0 -#define CRYPTO_KEYREADAREA_RAM_AREA_W 4 -#define CRYPTO_KEYREADAREA_RAM_AREA_M 0x0000000F -#define CRYPTO_KEYREADAREA_RAM_AREA_S 0 -#define CRYPTO_KEYREADAREA_RAM_AREA_NO_RAM 0x00000008 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA7 0x00000007 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA6 0x00000006 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA5 0x00000005 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA4 0x00000004 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA3 0x00000003 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA2 0x00000002 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA1 0x00000001 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA0 0x00000000 +#define CRYPTO_KEYREADAREA_RAM_AREA_W 4 +#define CRYPTO_KEYREADAREA_RAM_AREA_M 0x0000000F +#define CRYPTO_KEYREADAREA_RAM_AREA_S 0 +#define CRYPTO_KEYREADAREA_RAM_AREA_NO_RAM 0x00000008 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA7 0x00000007 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA6 0x00000006 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA5 0x00000005 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA4 0x00000004 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA3 0x00000003 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA2 0x00000002 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA1 0x00000001 +#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA0 0x00000000 //***************************************************************************** // @@ -921,9 +921,9 @@ // AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, // 96 ordered from the LSW entry of this 4-deep register array. // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY20_KEY2_W 32 -#define CRYPTO_AESKEY20_KEY2_M 0xFFFFFFFF -#define CRYPTO_AESKEY20_KEY2_S 0 +#define CRYPTO_AESKEY20_KEY2_W 32 +#define CRYPTO_AESKEY20_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY20_KEY2_S 0 //***************************************************************************** // @@ -935,9 +935,9 @@ // AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, // 96 ordered from the LSW entry of this 4-deep register array. // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY21_KEY2_W 32 -#define CRYPTO_AESKEY21_KEY2_M 0xFFFFFFFF -#define CRYPTO_AESKEY21_KEY2_S 0 +#define CRYPTO_AESKEY21_KEY2_W 32 +#define CRYPTO_AESKEY21_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY21_KEY2_S 0 //***************************************************************************** // @@ -949,9 +949,9 @@ // AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, // 96 ordered from the LSW entry of this 4-deep register array. // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY22_KEY2_W 32 -#define CRYPTO_AESKEY22_KEY2_M 0xFFFFFFFF -#define CRYPTO_AESKEY22_KEY2_S 0 +#define CRYPTO_AESKEY22_KEY2_W 32 +#define CRYPTO_AESKEY22_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY22_KEY2_S 0 //***************************************************************************** // @@ -963,9 +963,9 @@ // AESKEY2.* bits 31+x:0+x or AES_GHASH_H.* bits 31+x:0+x, where x = 0, 32, 64, // 96 ordered from the LSW entry of this 4-deep register array. // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY23_KEY2_W 32 -#define CRYPTO_AESKEY23_KEY2_M 0xFFFFFFFF -#define CRYPTO_AESKEY23_KEY2_S 0 +#define CRYPTO_AESKEY23_KEY2_W 32 +#define CRYPTO_AESKEY23_KEY2_M 0xFFFFFFFF +#define CRYPTO_AESKEY23_KEY2_S 0 //***************************************************************************** // @@ -977,9 +977,9 @@ // AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, // 96 ordered from the LSW entry of this 4-deep register arrary. // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY30_KEY3_W 32 -#define CRYPTO_AESKEY30_KEY3_M 0xFFFFFFFF -#define CRYPTO_AESKEY30_KEY3_S 0 +#define CRYPTO_AESKEY30_KEY3_W 32 +#define CRYPTO_AESKEY30_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY30_KEY3_S 0 //***************************************************************************** // @@ -991,9 +991,9 @@ // AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, // 96 ordered from the LSW entry of this 4-deep register arrary. // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY31_KEY3_W 32 -#define CRYPTO_AESKEY31_KEY3_M 0xFFFFFFFF -#define CRYPTO_AESKEY31_KEY3_S 0 +#define CRYPTO_AESKEY31_KEY3_W 32 +#define CRYPTO_AESKEY31_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY31_KEY3_S 0 //***************************************************************************** // @@ -1005,9 +1005,9 @@ // AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, // 96 ordered from the LSW entry of this 4-deep register arrary. // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY32_KEY3_W 32 -#define CRYPTO_AESKEY32_KEY3_M 0xFFFFFFFF -#define CRYPTO_AESKEY32_KEY3_S 0 +#define CRYPTO_AESKEY32_KEY3_W 32 +#define CRYPTO_AESKEY32_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY32_KEY3_S 0 //***************************************************************************** // @@ -1019,9 +1019,9 @@ // AESKEY3.* bits 31+x:0+x or AESKEY2.* bits 159+x:128+x, where x = 0, 32, 64, // 96 ordered from the LSW entry of this 4-deep register arrary. // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESKEY33_KEY3_W 32 -#define CRYPTO_AESKEY33_KEY3_M 0xFFFFFFFF -#define CRYPTO_AESKEY33_KEY3_S 0 +#define CRYPTO_AESKEY33_KEY3_W 32 +#define CRYPTO_AESKEY33_KEY3_M 0xFFFFFFFF +#define CRYPTO_AESKEY33_KEY3_S 0 //***************************************************************************** // @@ -1031,9 +1031,9 @@ // Field: [31:0] IV // // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESIV0_IV_W 32 -#define CRYPTO_AESIV0_IV_M 0xFFFFFFFF -#define CRYPTO_AESIV0_IV_S 0 +#define CRYPTO_AESIV0_IV_W 32 +#define CRYPTO_AESIV0_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV0_IV_S 0 //***************************************************************************** // @@ -1043,9 +1043,9 @@ // Field: [31:0] IV // // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESIV1_IV_W 32 -#define CRYPTO_AESIV1_IV_M 0xFFFFFFFF -#define CRYPTO_AESIV1_IV_S 0 +#define CRYPTO_AESIV1_IV_W 32 +#define CRYPTO_AESIV1_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV1_IV_S 0 //***************************************************************************** // @@ -1055,9 +1055,9 @@ // Field: [31:0] IV // // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESIV2_IV_W 32 -#define CRYPTO_AESIV2_IV_M 0xFFFFFFFF -#define CRYPTO_AESIV2_IV_S 0 +#define CRYPTO_AESIV2_IV_W 32 +#define CRYPTO_AESIV2_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV2_IV_S 0 //***************************************************************************** // @@ -1067,9 +1067,9 @@ // Field: [31:0] IV // // The interpretation of this field depends on the crypto operation mode. -#define CRYPTO_AESIV3_IV_W 32 -#define CRYPTO_AESIV3_IV_M 0xFFFFFFFF -#define CRYPTO_AESIV3_IV_S 0 +#define CRYPTO_AESIV3_IV_W 32 +#define CRYPTO_AESIV3_IV_M 0xFFFFFFFF +#define CRYPTO_AESIV3_IV_S 0 //***************************************************************************** // @@ -1082,10 +1082,10 @@ // overwritten and the Host is permitted to write the next context. Writing a // context means writing either a mode, the crypto length or // AESDATALEN1.LEN_MSW, AESDATALEN0.LEN_LSW length registers -#define CRYPTO_AESCTL_CONTEXT_RDY 0x80000000 -#define CRYPTO_AESCTL_CONTEXT_RDY_BITN 31 -#define CRYPTO_AESCTL_CONTEXT_RDY_M 0x80000000 -#define CRYPTO_AESCTL_CONTEXT_RDY_S 31 +#define CRYPTO_AESCTL_CONTEXT_RDY 0x80000000 +#define CRYPTO_AESCTL_CONTEXT_RDY_BITN 31 +#define CRYPTO_AESCTL_CONTEXT_RDY_M 0x80000000 +#define CRYPTO_AESCTL_CONTEXT_RDY_S 31 // Field: [30] SAVED_CONTEXT_RDY // @@ -1107,18 +1107,18 @@ // For typical use, this bit does NOT need to be written, but is used for // status reading only. In this case, this status bit is automatically // maintained by the Crypto peripheral. -#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY 0x40000000 -#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_BITN 30 -#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M 0x40000000 -#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_S 30 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY 0x40000000 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_BITN 30 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M 0x40000000 +#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_S 30 // Field: [29] SAVE_CONTEXT // // IV must be read before the AES engine can start a new operation. -#define CRYPTO_AESCTL_SAVE_CONTEXT 0x20000000 -#define CRYPTO_AESCTL_SAVE_CONTEXT_BITN 29 -#define CRYPTO_AESCTL_SAVE_CONTEXT_M 0x20000000 -#define CRYPTO_AESCTL_SAVE_CONTEXT_S 29 +#define CRYPTO_AESCTL_SAVE_CONTEXT 0x20000000 +#define CRYPTO_AESCTL_SAVE_CONTEXT_BITN 29 +#define CRYPTO_AESCTL_SAVE_CONTEXT_M 0x20000000 +#define CRYPTO_AESCTL_SAVE_CONTEXT_S 29 // Field: [24:22] CCM_M // @@ -1127,18 +1127,18 @@ // CCM_M plus one. // Note: The Crypto peripheral always returns a 128-bit authentication field, // of which the M least significant bytes are valid. All values are supported. -#define CRYPTO_AESCTL_CCM_M_W 3 -#define CRYPTO_AESCTL_CCM_M_M 0x01C00000 -#define CRYPTO_AESCTL_CCM_M_S 22 +#define CRYPTO_AESCTL_CCM_M_W 3 +#define CRYPTO_AESCTL_CCM_M_M 0x01C00000 +#define CRYPTO_AESCTL_CCM_M_S 22 // Field: [21:19] CCM_L // // Defines L that indicates the width of the length field for CCM operations; // the length field in bytes equals the value of CMM_L plus one. All values are // supported. -#define CRYPTO_AESCTL_CCM_L_W 3 -#define CRYPTO_AESCTL_CCM_L_M 0x00380000 -#define CRYPTO_AESCTL_CCM_L_S 19 +#define CRYPTO_AESCTL_CCM_L_W 3 +#define CRYPTO_AESCTL_CCM_L_M 0x00380000 +#define CRYPTO_AESCTL_CCM_L_S 19 // Field: [18] CCM // @@ -1149,10 +1149,10 @@ // AESDATALEN0.LEN_LSW after all other registers. // Note: The CTR mode bit in this register must also be set to 1 to enable // AES-CTR; selecting other AES modes than CTR mode is invalid. -#define CRYPTO_AESCTL_CCM 0x00040000 -#define CRYPTO_AESCTL_CCM_BITN 18 -#define CRYPTO_AESCTL_CCM_M 0x00040000 -#define CRYPTO_AESCTL_CCM_S 18 +#define CRYPTO_AESCTL_CCM 0x00040000 +#define CRYPTO_AESCTL_CCM_BITN 18 +#define CRYPTO_AESCTL_CCM_M 0x00040000 +#define CRYPTO_AESCTL_CCM_S 18 // Field: [15] CBC_MAC // @@ -1160,10 +1160,10 @@ // The DIR bit must be set to 1 for this mode. // Selecting this mode requires writing the AESDATALEN1.LEN_MSW and // AESDATALEN0.LEN_LSW registers after all other registers. -#define CRYPTO_AESCTL_CBC_MAC 0x00008000 -#define CRYPTO_AESCTL_CBC_MAC_BITN 15 -#define CRYPTO_AESCTL_CBC_MAC_M 0x00008000 -#define CRYPTO_AESCTL_CBC_MAC_S 15 +#define CRYPTO_AESCTL_CBC_MAC 0x00008000 +#define CRYPTO_AESCTL_CBC_MAC_BITN 15 +#define CRYPTO_AESCTL_CBC_MAC_M 0x00008000 +#define CRYPTO_AESCTL_CBC_MAC_S 15 // Field: [8:7] CTR_WIDTH // @@ -1173,30 +1173,30 @@ // 96_BIT 96 bits // 64_BIT 64 bits // 32_BIT 32 bits -#define CRYPTO_AESCTL_CTR_WIDTH_W 2 -#define CRYPTO_AESCTL_CTR_WIDTH_M 0x00000180 -#define CRYPTO_AESCTL_CTR_WIDTH_S 7 -#define CRYPTO_AESCTL_CTR_WIDTH_128_BIT 0x00000180 -#define CRYPTO_AESCTL_CTR_WIDTH_96_BIT 0x00000100 -#define CRYPTO_AESCTL_CTR_WIDTH_64_BIT 0x00000080 -#define CRYPTO_AESCTL_CTR_WIDTH_32_BIT 0x00000000 +#define CRYPTO_AESCTL_CTR_WIDTH_W 2 +#define CRYPTO_AESCTL_CTR_WIDTH_M 0x00000180 +#define CRYPTO_AESCTL_CTR_WIDTH_S 7 +#define CRYPTO_AESCTL_CTR_WIDTH_128_BIT 0x00000180 +#define CRYPTO_AESCTL_CTR_WIDTH_96_BIT 0x00000100 +#define CRYPTO_AESCTL_CTR_WIDTH_64_BIT 0x00000080 +#define CRYPTO_AESCTL_CTR_WIDTH_32_BIT 0x00000000 // Field: [6] CTR // // AES-CTR mode enable // This bit must also be set for CCM, when encryption/decryption is required. -#define CRYPTO_AESCTL_CTR 0x00000040 -#define CRYPTO_AESCTL_CTR_BITN 6 -#define CRYPTO_AESCTL_CTR_M 0x00000040 -#define CRYPTO_AESCTL_CTR_S 6 +#define CRYPTO_AESCTL_CTR 0x00000040 +#define CRYPTO_AESCTL_CTR_BITN 6 +#define CRYPTO_AESCTL_CTR_M 0x00000040 +#define CRYPTO_AESCTL_CTR_S 6 // Field: [5] CBC // // CBC mode enable -#define CRYPTO_AESCTL_CBC 0x00000020 -#define CRYPTO_AESCTL_CBC_BITN 5 -#define CRYPTO_AESCTL_CBC_M 0x00000020 -#define CRYPTO_AESCTL_CBC_S 5 +#define CRYPTO_AESCTL_CBC 0x00000020 +#define CRYPTO_AESCTL_CBC_BITN 5 +#define CRYPTO_AESCTL_CBC_M 0x00000020 +#define CRYPTO_AESCTL_CBC_S 5 // Field: [4:3] KEY_SIZE // @@ -1208,9 +1208,9 @@ // 10 = N/A - reserved // 11 = N/A - reserved // For the Crypto peripheral this field is fixed to 128 bits. -#define CRYPTO_AESCTL_KEY_SIZE_W 2 -#define CRYPTO_AESCTL_KEY_SIZE_M 0x00000018 -#define CRYPTO_AESCTL_KEY_SIZE_S 3 +#define CRYPTO_AESCTL_KEY_SIZE_W 2 +#define CRYPTO_AESCTL_KEY_SIZE_M 0x00000018 +#define CRYPTO_AESCTL_KEY_SIZE_S 3 // Field: [2] DIR // @@ -1219,10 +1219,10 @@ // 1 : Encrypt operation is performed. // // This bit must be written with a 1 when CBC-MAC is selected. -#define CRYPTO_AESCTL_DIR 0x00000004 -#define CRYPTO_AESCTL_DIR_BITN 2 -#define CRYPTO_AESCTL_DIR_M 0x00000004 -#define CRYPTO_AESCTL_DIR_S 2 +#define CRYPTO_AESCTL_DIR 0x00000004 +#define CRYPTO_AESCTL_DIR_BITN 2 +#define CRYPTO_AESCTL_DIR_M 0x00000004 +#define CRYPTO_AESCTL_DIR_S 2 // Field: [1] INPUT_RDY // @@ -1242,10 +1242,10 @@ // For typical use, this bit does NOT need to be written, but is used for // status reading only. In this case, this status bit is automatically // maintained by the Crypto peripheral. -#define CRYPTO_AESCTL_INPUT_RDY 0x00000002 -#define CRYPTO_AESCTL_INPUT_RDY_BITN 1 -#define CRYPTO_AESCTL_INPUT_RDY_M 0x00000002 -#define CRYPTO_AESCTL_INPUT_RDY_S 1 +#define CRYPTO_AESCTL_INPUT_RDY 0x00000002 +#define CRYPTO_AESCTL_INPUT_RDY_BITN 1 +#define CRYPTO_AESCTL_INPUT_RDY_M 0x00000002 +#define CRYPTO_AESCTL_INPUT_RDY_S 1 // Field: [0] OUTPUT_RDY // @@ -1263,10 +1263,10 @@ // For typical use, this bit does NOT need to be written, but is used for // status reading only. In this case, this status bit is automatically // maintained by the Crypto peripheral. -#define CRYPTO_AESCTL_OUTPUT_RDY 0x00000001 -#define CRYPTO_AESCTL_OUTPUT_RDY_BITN 0 -#define CRYPTO_AESCTL_OUTPUT_RDY_M 0x00000001 -#define CRYPTO_AESCTL_OUTPUT_RDY_S 0 +#define CRYPTO_AESCTL_OUTPUT_RDY 0x00000001 +#define CRYPTO_AESCTL_OUTPUT_RDY_BITN 0 +#define CRYPTO_AESCTL_OUTPUT_RDY_M 0x00000001 +#define CRYPTO_AESCTL_OUTPUT_RDY_S 0 //***************************************************************************** // @@ -1278,9 +1278,9 @@ // Used to write the Length values to the Crypto peripheral. // // This register contains bits [31:0] of the combined data length. -#define CRYPTO_AESDATALEN0_LEN_LSW_W 32 -#define CRYPTO_AESDATALEN0_LEN_LSW_M 0xFFFFFFFF -#define CRYPTO_AESDATALEN0_LEN_LSW_S 0 +#define CRYPTO_AESDATALEN0_LEN_LSW_W 32 +#define CRYPTO_AESDATALEN0_LEN_LSW_M 0xFFFFFFFF +#define CRYPTO_AESDATALEN0_LEN_LSW_S 0 //***************************************************************************** // @@ -1311,9 +1311,9 @@ // data streams are not supported by the Crypto peripheral. For block cipher // modes, the data length must be programmed in multiples of the block cipher // size, 16 bytes. -#define CRYPTO_AESDATALEN1_LEN_MSW_W 29 -#define CRYPTO_AESDATALEN1_LEN_MSW_M 0x1FFFFFFF -#define CRYPTO_AESDATALEN1_LEN_MSW_S 0 +#define CRYPTO_AESDATALEN1_LEN_MSW_W 29 +#define CRYPTO_AESDATALEN1_LEN_MSW_M 0x1FFFFFFF +#define CRYPTO_AESDATALEN1_LEN_MSW_S 0 //***************************************************************************** // @@ -1327,9 +1327,9 @@ // processing with this context is started, this length decrements to zero. // Writing this register triggers the engine to start using this context for // CCM. -#define CRYPTO_AESAUTHLEN_LEN_W 32 -#define CRYPTO_AESAUTHLEN_LEN_M 0xFFFFFFFF -#define CRYPTO_AESAUTHLEN_LEN_S 0 +#define CRYPTO_AESAUTHLEN_LEN_W 32 +#define CRYPTO_AESAUTHLEN_LEN_M 0xFFFFFFFF +#define CRYPTO_AESAUTHLEN_LEN_S 0 //***************************************************************************** // @@ -1356,9 +1356,9 @@ // // Note: The AAD / authentication only data is not copied to the output buffer // but only used for authentication. -#define CRYPTO_AESDATAOUT0_DATA_W 32 -#define CRYPTO_AESDATAOUT0_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAOUT0_DATA_S 0 +#define CRYPTO_AESDATAOUT0_DATA_W 32 +#define CRYPTO_AESDATAOUT0_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT0_DATA_S 0 //***************************************************************************** // @@ -1390,9 +1390,9 @@ // pads or masks misaligned ending data blocks with zeroes for GCM, CCM and // CBC-MAC. For CTR mode, the remaining data in an unaligned data block is // ignored. -#define CRYPTO_AESDATAIN0_DATA_W 32 -#define CRYPTO_AESDATAIN0_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAIN0_DATA_S 0 +#define CRYPTO_AESDATAIN0_DATA_W 32 +#define CRYPTO_AESDATAIN0_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN0_DATA_S 0 //***************************************************************************** // @@ -1419,9 +1419,9 @@ // // Note: The AAD / authentication only data is not copied to the output buffer // but only used for authentication. -#define CRYPTO_AESDATAOUT1_DATA_W 32 -#define CRYPTO_AESDATAOUT1_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAOUT1_DATA_S 0 +#define CRYPTO_AESDATAOUT1_DATA_W 32 +#define CRYPTO_AESDATAOUT1_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT1_DATA_S 0 //***************************************************************************** // @@ -1453,9 +1453,9 @@ // pads or masks misaligned ending data blocks with zeroes for GCM, CCM and // CBC-MAC. For CTR mode, the remaining data in an unaligned data block is // ignored. -#define CRYPTO_AESDATAIN1_DATA_W 32 -#define CRYPTO_AESDATAIN1_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAIN1_DATA_S 0 +#define CRYPTO_AESDATAIN1_DATA_W 32 +#define CRYPTO_AESDATAIN1_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN1_DATA_S 0 //***************************************************************************** // @@ -1482,9 +1482,9 @@ // // Note: The AAD / authentication only data is not copied to the output buffer // but only used for authentication. -#define CRYPTO_AESDATAOUT2_DATA_W 32 -#define CRYPTO_AESDATAOUT2_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAOUT2_DATA_S 0 +#define CRYPTO_AESDATAOUT2_DATA_W 32 +#define CRYPTO_AESDATAOUT2_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT2_DATA_S 0 //***************************************************************************** // @@ -1516,9 +1516,9 @@ // pads or masks misaligned ending data blocks with zeroes for GCM, CCM and // CBC-MAC. For CTR mode, the remaining data in an unaligned data block is // ignored. -#define CRYPTO_AESDATAIN2_DATA_W 32 -#define CRYPTO_AESDATAIN2_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAIN2_DATA_S 0 +#define CRYPTO_AESDATAIN2_DATA_W 32 +#define CRYPTO_AESDATAIN2_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN2_DATA_S 0 //***************************************************************************** // @@ -1545,9 +1545,9 @@ // // Note: The AAD / authentication only data is not copied to the output buffer // but only used for authentication. -#define CRYPTO_AESDATAOUT3_DATA_W 32 -#define CRYPTO_AESDATAOUT3_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAOUT3_DATA_S 0 +#define CRYPTO_AESDATAOUT3_DATA_W 32 +#define CRYPTO_AESDATAOUT3_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAOUT3_DATA_S 0 //***************************************************************************** // @@ -1579,9 +1579,9 @@ // pads or masks misaligned ending data blocks with zeroes for GCM, CCM and // CBC-MAC. For CTR mode, the remaining data in an unaligned data block is // ignored. -#define CRYPTO_AESDATAIN3_DATA_W 32 -#define CRYPTO_AESDATAIN3_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAIN3_DATA_S 0 +#define CRYPTO_AESDATAIN3_DATA_W 32 +#define CRYPTO_AESDATAIN3_DATA_M 0xFFFFFFFF +#define CRYPTO_AESDATAIN3_DATA_S 0 //***************************************************************************** // @@ -1592,9 +1592,9 @@ // // This register contains the authentication TAG for the combined and // authentication-only modes. -#define CRYPTO_AESTAGOUT0_TAG_W 32 -#define CRYPTO_AESTAGOUT0_TAG_M 0xFFFFFFFF -#define CRYPTO_AESTAGOUT0_TAG_S 0 +#define CRYPTO_AESTAGOUT0_TAG_W 32 +#define CRYPTO_AESTAGOUT0_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT0_TAG_S 0 //***************************************************************************** // @@ -1605,9 +1605,9 @@ // // This register contains the authentication TAG for the combined and // authentication-only modes. -#define CRYPTO_AESTAGOUT1_TAG_W 32 -#define CRYPTO_AESTAGOUT1_TAG_M 0xFFFFFFFF -#define CRYPTO_AESTAGOUT1_TAG_S 0 +#define CRYPTO_AESTAGOUT1_TAG_W 32 +#define CRYPTO_AESTAGOUT1_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT1_TAG_S 0 //***************************************************************************** // @@ -1618,9 +1618,9 @@ // // This register contains the authentication TAG for the combined and // authentication-only modes. -#define CRYPTO_AESTAGOUT2_TAG_W 32 -#define CRYPTO_AESTAGOUT2_TAG_M 0xFFFFFFFF -#define CRYPTO_AESTAGOUT2_TAG_S 0 +#define CRYPTO_AESTAGOUT2_TAG_W 32 +#define CRYPTO_AESTAGOUT2_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT2_TAG_S 0 //***************************************************************************** // @@ -1631,9 +1631,9 @@ // // This register contains the authentication TAG for the combined and // authentication-only modes. -#define CRYPTO_AESTAGOUT3_TAG_W 32 -#define CRYPTO_AESTAGOUT3_TAG_M 0xFFFFFFFF -#define CRYPTO_AESTAGOUT3_TAG_S 0 +#define CRYPTO_AESTAGOUT3_TAG_W 32 +#define CRYPTO_AESTAGOUT3_TAG_M 0xFFFFFFFF +#define CRYPTO_AESTAGOUT3_TAG_S 0 //***************************************************************************** // @@ -1645,29 +1645,29 @@ // If this bit is cleared to 0, the DMA operation involves only data. // If this bit is set, the DMA operation includes a TAG (Authentication Result // / Digest). -#define CRYPTO_ALGSEL_TAG 0x80000000 -#define CRYPTO_ALGSEL_TAG_BITN 31 -#define CRYPTO_ALGSEL_TAG_M 0x80000000 -#define CRYPTO_ALGSEL_TAG_S 31 +#define CRYPTO_ALGSEL_TAG 0x80000000 +#define CRYPTO_ALGSEL_TAG_BITN 31 +#define CRYPTO_ALGSEL_TAG_M 0x80000000 +#define CRYPTO_ALGSEL_TAG_S 31 // Field: [1] AES // // If set to 1, the AES data is loaded via DMA // Both Read and Write maximum transfer size to DMA engine is set to 16 bytes -#define CRYPTO_ALGSEL_AES 0x00000002 -#define CRYPTO_ALGSEL_AES_BITN 1 -#define CRYPTO_ALGSEL_AES_M 0x00000002 -#define CRYPTO_ALGSEL_AES_S 1 +#define CRYPTO_ALGSEL_AES 0x00000002 +#define CRYPTO_ALGSEL_AES_BITN 1 +#define CRYPTO_ALGSEL_AES_M 0x00000002 +#define CRYPTO_ALGSEL_AES_S 1 // Field: [0] KEY_STORE // // If set to 1, selects the Key Store to be loaded via DMA. // The maximum transfer size to DMA engine is set to 32 bytes (however // transfers of 16, 24 and 32 bytes are allowed) -#define CRYPTO_ALGSEL_KEY_STORE 0x00000001 -#define CRYPTO_ALGSEL_KEY_STORE_BITN 0 -#define CRYPTO_ALGSEL_KEY_STORE_M 0x00000001 -#define CRYPTO_ALGSEL_KEY_STORE_S 0 +#define CRYPTO_ALGSEL_KEY_STORE 0x00000001 +#define CRYPTO_ALGSEL_KEY_STORE_BITN 0 +#define CRYPTO_ALGSEL_KEY_STORE_M 0x00000001 +#define CRYPTO_ALGSEL_KEY_STORE_S 0 //***************************************************************************** // @@ -1680,10 +1680,10 @@ // area as destination. // 0 : transfers use 'USER' type access. // 1 : transfers use 'PRIVILEGED' type access. -#define CRYPTO_DMAPROTCTL_EN 0x00000001 -#define CRYPTO_DMAPROTCTL_EN_BITN 0 -#define CRYPTO_DMAPROTCTL_EN_M 0x00000001 -#define CRYPTO_DMAPROTCTL_EN_S 0 +#define CRYPTO_DMAPROTCTL_EN 0x00000001 +#define CRYPTO_DMAPROTCTL_EN_BITN 0 +#define CRYPTO_DMAPROTCTL_EN_M 0x00000001 +#define CRYPTO_DMAPROTCTL_EN_S 0 //***************************************************************************** // @@ -1699,10 +1699,10 @@ // flags; therefore the keys must be reloaded to the key store module. // Writing 0 has no effect. // The bit is self cleared after executing the reset. -#define CRYPTO_SWRESET_RESET 0x00000001 -#define CRYPTO_SWRESET_RESET_BITN 0 -#define CRYPTO_SWRESET_RESET_M 0x00000001 -#define CRYPTO_SWRESET_RESET_S 0 +#define CRYPTO_SWRESET_RESET 0x00000001 +#define CRYPTO_SWRESET_RESET_BITN 0 +#define CRYPTO_SWRESET_RESET_M 0x00000001 +#define CRYPTO_SWRESET_RESET_S 0 //***************************************************************************** // @@ -1715,10 +1715,10 @@ // If this bit is set to 1, the interrupt is a level interrupt that must be // cleared by writing the interrupt clear register. // This bit is applicable for both interrupt output signals. -#define CRYPTO_IRQTYPE_LEVEL 0x00000001 -#define CRYPTO_IRQTYPE_LEVEL_BITN 0 -#define CRYPTO_IRQTYPE_LEVEL_M 0x00000001 -#define CRYPTO_IRQTYPE_LEVEL_S 0 +#define CRYPTO_IRQTYPE_LEVEL 0x00000001 +#define CRYPTO_IRQTYPE_LEVEL_BITN 0 +#define CRYPTO_IRQTYPE_LEVEL_M 0x00000001 +#define CRYPTO_IRQTYPE_LEVEL_S 0 //***************************************************************************** // @@ -1728,18 +1728,18 @@ // Field: [1] DMA_IN_DONE // // This bit enables IRQSTAT.DMA_IN_DONE as source for IRQ. -#define CRYPTO_IRQEN_DMA_IN_DONE 0x00000002 -#define CRYPTO_IRQEN_DMA_IN_DONE_BITN 1 -#define CRYPTO_IRQEN_DMA_IN_DONE_M 0x00000002 -#define CRYPTO_IRQEN_DMA_IN_DONE_S 1 +#define CRYPTO_IRQEN_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQEN_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQEN_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQEN_DMA_IN_DONE_S 1 // Field: [0] RESULT_AVAIL // // This bit enables IRQSTAT.RESULT_AVAIL as source for IRQ. -#define CRYPTO_IRQEN_RESULT_AVAIL 0x00000001 -#define CRYPTO_IRQEN_RESULT_AVAIL_BITN 0 -#define CRYPTO_IRQEN_RESULT_AVAIL_M 0x00000001 -#define CRYPTO_IRQEN_RESULT_AVAIL_S 0 +#define CRYPTO_IRQEN_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQEN_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQEN_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQEN_RESULT_AVAIL_S 0 //***************************************************************************** // @@ -1749,42 +1749,42 @@ // Field: [31] DMA_BUS_ERR // // If 1 is written to this bit, IRQSTAT.DMA_BUS_ERR is cleared. -#define CRYPTO_IRQCLR_DMA_BUS_ERR 0x80000000 -#define CRYPTO_IRQCLR_DMA_BUS_ERR_BITN 31 -#define CRYPTO_IRQCLR_DMA_BUS_ERR_M 0x80000000 -#define CRYPTO_IRQCLR_DMA_BUS_ERR_S 31 +#define CRYPTO_IRQCLR_DMA_BUS_ERR 0x80000000 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_BITN 31 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_M 0x80000000 +#define CRYPTO_IRQCLR_DMA_BUS_ERR_S 31 // Field: [30] KEY_ST_WR_ERR // // If 1 is written to this bit, IRQSTAT.KEY_ST_WR_ERR is cleared. -#define CRYPTO_IRQCLR_KEY_ST_WR_ERR 0x40000000 -#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_BITN 30 -#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_M 0x40000000 -#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_S 30 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR 0x40000000 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_BITN 30 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_M 0x40000000 +#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_S 30 // Field: [29] KEY_ST_RD_ERR // // If 1 is written to this bit, IRQSTAT.KEY_ST_RD_ERR is cleared. -#define CRYPTO_IRQCLR_KEY_ST_RD_ERR 0x20000000 -#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_BITN 29 -#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_M 0x20000000 -#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_S 29 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR 0x20000000 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_BITN 29 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_M 0x20000000 +#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_S 29 // Field: [1] DMA_IN_DONE // // If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is cleared. -#define CRYPTO_IRQCLR_DMA_IN_DONE 0x00000002 -#define CRYPTO_IRQCLR_DMA_IN_DONE_BITN 1 -#define CRYPTO_IRQCLR_DMA_IN_DONE_M 0x00000002 -#define CRYPTO_IRQCLR_DMA_IN_DONE_S 1 +#define CRYPTO_IRQCLR_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQCLR_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQCLR_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQCLR_DMA_IN_DONE_S 1 // Field: [0] RESULT_AVAIL // // If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is cleared. -#define CRYPTO_IRQCLR_RESULT_AVAIL 0x00000001 -#define CRYPTO_IRQCLR_RESULT_AVAIL_BITN 0 -#define CRYPTO_IRQCLR_RESULT_AVAIL_M 0x00000001 -#define CRYPTO_IRQCLR_RESULT_AVAIL_S 0 +#define CRYPTO_IRQCLR_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQCLR_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQCLR_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQCLR_RESULT_AVAIL_S 0 //***************************************************************************** // @@ -1795,19 +1795,19 @@ // // If 1 is written to this bit, IRQSTAT.DMA_IN_DONE is set. // Writing 0 has no effect. -#define CRYPTO_IRQSET_DMA_IN_DONE 0x00000002 -#define CRYPTO_IRQSET_DMA_IN_DONE_BITN 1 -#define CRYPTO_IRQSET_DMA_IN_DONE_M 0x00000002 -#define CRYPTO_IRQSET_DMA_IN_DONE_S 1 +#define CRYPTO_IRQSET_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQSET_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQSET_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQSET_DMA_IN_DONE_S 1 // Field: [0] RESULT_AVAIL // // If 1 is written to this bit, IRQSTAT.RESULT_AVAIL is set. // Writing 0 has no effect. -#define CRYPTO_IRQSET_RESULT_AVAIL 0x00000001 -#define CRYPTO_IRQSET_RESULT_AVAIL_BITN 0 -#define CRYPTO_IRQSET_RESULT_AVAIL_M 0x00000001 -#define CRYPTO_IRQSET_RESULT_AVAIL_S 0 +#define CRYPTO_IRQSET_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQSET_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQSET_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQSET_RESULT_AVAIL_S 0 //***************************************************************************** // @@ -1821,10 +1821,10 @@ // Note: This error is asserted if an error is detected on the AHB master // interface during a DMA operation. // Note: This is not an interrupt source. -#define CRYPTO_IRQSTAT_DMA_BUS_ERR 0x80000000 -#define CRYPTO_IRQSTAT_DMA_BUS_ERR_BITN 31 -#define CRYPTO_IRQSTAT_DMA_BUS_ERR_M 0x80000000 -#define CRYPTO_IRQSTAT_DMA_BUS_ERR_S 31 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR 0x80000000 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_BITN 31 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_M 0x80000000 +#define CRYPTO_IRQSTAT_DMA_BUS_ERR_S 31 // Field: [30] KEY_ST_WR_ERR // @@ -1834,10 +1834,10 @@ // Note: This error is asserted if a DMA operation does not cover a full key // area or more areas are written than expected. // Note: This is not an interrupt source. -#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR 0x40000000 -#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_BITN 30 -#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M 0x40000000 -#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_S 30 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR 0x40000000 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_BITN 30 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M 0x40000000 +#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_S 30 // Field: [29] KEY_ST_RD_ERR // @@ -1847,26 +1847,26 @@ // Note: This error is asserted if a key location is selected in the key store // that is not available. // Note: This is not an interrupt source. -#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR 0x20000000 -#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_BITN 29 -#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M 0x20000000 -#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_S 29 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR 0x20000000 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_BITN 29 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M 0x20000000 +#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_S 29 // Field: [1] DMA_IN_DONE // // This bit returns the status of DMA data in done interrupt. -#define CRYPTO_IRQSTAT_DMA_IN_DONE 0x00000002 -#define CRYPTO_IRQSTAT_DMA_IN_DONE_BITN 1 -#define CRYPTO_IRQSTAT_DMA_IN_DONE_M 0x00000002 -#define CRYPTO_IRQSTAT_DMA_IN_DONE_S 1 +#define CRYPTO_IRQSTAT_DMA_IN_DONE 0x00000002 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_BITN 1 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_M 0x00000002 +#define CRYPTO_IRQSTAT_DMA_IN_DONE_S 1 // Field: [0] RESULT_AVAIL // // This bit is set high when the Crypto peripheral has a result available. -#define CRYPTO_IRQSTAT_RESULT_AVAIL 0x00000001 -#define CRYPTO_IRQSTAT_RESULT_AVAIL_BITN 0 -#define CRYPTO_IRQSTAT_RESULT_AVAIL_M 0x00000001 -#define CRYPTO_IRQSTAT_RESULT_AVAIL_S 0 +#define CRYPTO_IRQSTAT_RESULT_AVAIL 0x00000001 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_BITN 0 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_M 0x00000001 +#define CRYPTO_IRQSTAT_RESULT_AVAIL_S 0 //***************************************************************************** // @@ -1876,39 +1876,38 @@ // Field: [27:24] HW_MAJOR_VER // // Major version number -#define CRYPTO_HWVER_HW_MAJOR_VER_W 4 -#define CRYPTO_HWVER_HW_MAJOR_VER_M 0x0F000000 -#define CRYPTO_HWVER_HW_MAJOR_VER_S 24 +#define CRYPTO_HWVER_HW_MAJOR_VER_W 4 +#define CRYPTO_HWVER_HW_MAJOR_VER_M 0x0F000000 +#define CRYPTO_HWVER_HW_MAJOR_VER_S 24 // Field: [23:20] HW_MINOR_VER // // Minor version number -#define CRYPTO_HWVER_HW_MINOR_VER_W 4 -#define CRYPTO_HWVER_HW_MINOR_VER_M 0x00F00000 -#define CRYPTO_HWVER_HW_MINOR_VER_S 20 +#define CRYPTO_HWVER_HW_MINOR_VER_W 4 +#define CRYPTO_HWVER_HW_MINOR_VER_M 0x00F00000 +#define CRYPTO_HWVER_HW_MINOR_VER_S 20 // Field: [19:16] HW_PATCH_LVL // // Patch level, starts at 0 at first delivery of this version. -#define CRYPTO_HWVER_HW_PATCH_LVL_W 4 -#define CRYPTO_HWVER_HW_PATCH_LVL_M 0x000F0000 -#define CRYPTO_HWVER_HW_PATCH_LVL_S 16 +#define CRYPTO_HWVER_HW_PATCH_LVL_W 4 +#define CRYPTO_HWVER_HW_PATCH_LVL_M 0x000F0000 +#define CRYPTO_HWVER_HW_PATCH_LVL_S 16 // Field: [15:8] VER_NUM_COMPL // // These bits simply contain the complement of VER_NUM (0x87), used by a driver // to ascertain that the Crypto peripheral register is indeed read. -#define CRYPTO_HWVER_VER_NUM_COMPL_W 8 -#define CRYPTO_HWVER_VER_NUM_COMPL_M 0x0000FF00 -#define CRYPTO_HWVER_VER_NUM_COMPL_S 8 +#define CRYPTO_HWVER_VER_NUM_COMPL_W 8 +#define CRYPTO_HWVER_VER_NUM_COMPL_M 0x0000FF00 +#define CRYPTO_HWVER_VER_NUM_COMPL_S 8 // Field: [7:0] VER_NUM // // The version number for the Crypto peripheral, this field contains the value // 120 (decimal) or 0x78. -#define CRYPTO_HWVER_VER_NUM_W 8 -#define CRYPTO_HWVER_VER_NUM_M 0x000000FF -#define CRYPTO_HWVER_VER_NUM_S 0 - +#define CRYPTO_HWVER_VER_NUM_W 8 +#define CRYPTO_HWVER_VER_NUM_M 0x000000FF +#define CRYPTO_HWVER_VER_NUM_S 0 #endif // __CRYPTO__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ddi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ddi.h index d81a93a..6113118 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ddi.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ddi.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_ddi.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_ddi.h + * Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) + * Revision: 49096 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_DDI_H__ #define __HW_DDI_H__ @@ -176,22 +176,20 @@ // The following are defines for the DDI master instruction offsets. // //***************************************************************************** -#define DDI_O_DIR 0x00000000 // Offset for the direct access instruction -#define DDI_O_SET 0x00000040 // Offset for 'Set' instruction. -#define DDI_O_CLR 0x00000080 // Offset for 'Clear' instruction. -#define DDI_O_MASK4B 0x00000100 // Offset for 4-bit masked access. +#define DDI_O_DIR 0x00000000 // Offset for the direct access instruction +#define DDI_O_SET 0x00000040 // Offset for 'Set' instruction. +#define DDI_O_CLR 0x00000080 // Offset for 'Clear' instruction. +#define DDI_O_MASK4B 0x00000100 // Offset for 4-bit masked access. // Data bit[n] is written if mask bit[n] is set ('1'). // Bits 7:4 are mask. Bits 3:0 are data. // Requires 'byte' write. -#define DDI_O_MASK8B 0x00000180 // Offset for 8-bit masked access. +#define DDI_O_MASK8B 0x00000180 // Offset for 8-bit masked access. // Data bit[n] is written if mask bit[n] is set ('1'). // Bits 15:8 are mask. Bits 7:0 are data. // Requires 'short' write. -#define DDI_O_MASK16B 0x00000200 // Offset for 16-bit masked access. +#define DDI_O_MASK16B 0x00000200 // Offset for 16-bit masked access. // Data bit[n] is written if mask bit[n] is set ('1'). // Bits 31:16 are mask. Bits 15:0 are data. // Requires 'long' write. - - #endif // __HW_DDI_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ddi_0_osc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ddi_0_osc.h index 9363ec1..78e638b 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ddi_0_osc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ddi_0_osc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_ddi_0_osc_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_ddi_0_osc_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_DDI_0_OSC_H__ #define __HW_DDI_0_OSC_H__ @@ -44,52 +44,52 @@ // //***************************************************************************** // Control 0 -#define DDI_0_OSC_O_CTL0 0x00000000 +#define DDI_0_OSC_O_CTL0 0x00000000 // Control 1 -#define DDI_0_OSC_O_CTL1 0x00000004 +#define DDI_0_OSC_O_CTL1 0x00000004 // RADC External Configuration -#define DDI_0_OSC_O_RADCEXTCFG 0x00000008 +#define DDI_0_OSC_O_RADCEXTCFG 0x00000008 // Amplitude Compensation Control -#define DDI_0_OSC_O_AMPCOMPCTL 0x0000000C +#define DDI_0_OSC_O_AMPCOMPCTL 0x0000000C // Amplitude Compensation Threshold 1 -#define DDI_0_OSC_O_AMPCOMPTH1 0x00000010 +#define DDI_0_OSC_O_AMPCOMPTH1 0x00000010 // Amplitude Compensation Threshold 2 -#define DDI_0_OSC_O_AMPCOMPTH2 0x00000014 +#define DDI_0_OSC_O_AMPCOMPTH2 0x00000014 // Analog Bypass Values 1 -#define DDI_0_OSC_O_ANABYPASSVAL1 0x00000018 +#define DDI_0_OSC_O_ANABYPASSVAL1 0x00000018 // Internal -#define DDI_0_OSC_O_ANABYPASSVAL2 0x0000001C +#define DDI_0_OSC_O_ANABYPASSVAL2 0x0000001C // Analog Test Control -#define DDI_0_OSC_O_ATESTCTL 0x00000020 +#define DDI_0_OSC_O_ATESTCTL 0x00000020 // ADC Doubler Nanoamp Control -#define DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL 0x00000024 +#define DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL 0x00000024 // XOSCHF Control -#define DDI_0_OSC_O_XOSCHFCTL 0x00000028 +#define DDI_0_OSC_O_XOSCHFCTL 0x00000028 // Low Frequency Oscillator Control -#define DDI_0_OSC_O_LFOSCCTL 0x0000002C +#define DDI_0_OSC_O_LFOSCCTL 0x0000002C // RCOSCHF Control -#define DDI_0_OSC_O_RCOSCHFCTL 0x00000030 +#define DDI_0_OSC_O_RCOSCHFCTL 0x00000030 // Status 0 -#define DDI_0_OSC_O_STAT0 0x00000034 +#define DDI_0_OSC_O_STAT0 0x00000034 // Status 1 -#define DDI_0_OSC_O_STAT1 0x00000038 +#define DDI_0_OSC_O_STAT1 0x00000038 // Status 2 -#define DDI_0_OSC_O_STAT2 0x0000003C +#define DDI_0_OSC_O_STAT2 0x0000003C //***************************************************************************** // @@ -102,46 +102,46 @@ // ENUMs: // 24M Internal. Only to be used through TI provided API. // 48M Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000 -#define DDI_0_OSC_CTL0_XTAL_IS_24M_M 0x80000000 -#define DDI_0_OSC_CTL0_XTAL_IS_24M_S 31 -#define DDI_0_OSC_CTL0_XTAL_IS_24M_24M 0x80000000 -#define DDI_0_OSC_CTL0_XTAL_IS_24M_48M 0x00000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_S 31 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_24M 0x80000000 +#define DDI_0_OSC_CTL0_XTAL_IS_24M_48M 0x00000000 // Field: [29] BYPASS_XOSC_LF_CLK_QUAL // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000 -#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M 0x20000000 -#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_S 29 +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000 +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M 0x20000000 +#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_S 29 // Field: [28] BYPASS_RCOSC_LF_CLK_QUAL // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000 -#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M 0x10000000 -#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S 28 +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000 +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M 0x10000000 +#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S 28 // Field: [27:26] DOUBLER_START_DURATION // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_W 2 -#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_M 0x0C000000 -#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_S 26 +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_W 2 +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_M 0x0C000000 +#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_S 26 // Field: [25] DOUBLER_RESET_DURATION // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x02000000 -#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_M 0x02000000 -#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_S 25 +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x02000000 +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_M 0x02000000 +#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_S 25 // Field: [22] FORCE_KICKSTART_EN // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN 0x00400000 -#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN_M 0x00400000 -#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN_S 22 +#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN 0x00400000 +#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN_M 0x00400000 +#define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN_S 22 // Field: [16] ALLOW_SCLK_HF_SWITCHING // @@ -157,30 +157,30 @@ // indicated by STAT0.PENDINGSCLKHFSWITCHING) sclk_hf switching should be // disabled to prevent flash corruption. Switching should not be enabled when // running from flash. -#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING 0x00010000 -#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING_M 0x00010000 -#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING_S 16 +#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING 0x00010000 +#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING_M 0x00010000 +#define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING_S 16 // Field: [14] HPOSC_MODE_EN // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_HPOSC_MODE_EN 0x00004000 -#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_M 0x00004000 -#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_S 14 +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN 0x00004000 +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_M 0x00004000 +#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_S 14 // Field: [12] RCOSC_LF_TRIMMED // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x00001000 -#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_M 0x00001000 -#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_S 12 +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x00001000 +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_M 0x00001000 +#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_S 12 // Field: [11] XOSC_HF_POWER_MODE // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x00000800 -#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_M 0x00000800 -#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_S 11 +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x00000800 +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_M 0x00000800 +#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_S 11 // Field: [10] XOSC_LF_DIG_BYPASS // @@ -203,9 +203,9 @@ // It is recommended that either the rcosc_hf or xosc_hf (whichever is // currently active) be selected as the source in step 1 above. This provides a // faster clock change. -#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x00000400 -#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_M 0x00000400 -#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_S 10 +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x00000400 +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_M 0x00000400 +#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_S 10 // Field: [9] CLK_LOSS_EN // @@ -218,9 +218,9 @@ // Clock loss detection must be disabled when changing the sclk_lf source. // STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf // source has completed. -#define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x00000200 -#define DDI_0_OSC_CTL0_CLK_LOSS_EN_M 0x00000200 -#define DDI_0_OSC_CTL0_CLK_LOSS_EN_S 9 +#define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x00000200 +#define DDI_0_OSC_CTL0_CLK_LOSS_EN_M 0x00000200 +#define DDI_0_OSC_CTL0_CLK_LOSS_EN_S 9 // Field: [8:7] ACLK_TDC_SRC_SEL // @@ -230,9 +230,9 @@ // 01: RCOSC_HF (24MHz) // 10: XOSC_HF (24MHz) // 11: Not used -#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_W 2 -#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M 0x00000180 -#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S 7 +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_W 2 +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M 0x00000180 +#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S 7 // Field: [6:5] ACLK_REF_SRC_SEL // @@ -242,9 +242,9 @@ // 01: XOSC_HF derived (31.25kHz) // 10: RCOSC_LF (32kHz) // 11: XOSC_LF (32.768kHz) -#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_W 2 -#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M 0x00000060 -#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S 5 +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_W 2 +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M 0x00000060 +#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S 5 // Field: [3:2] SCLK_LF_SRC_SEL // @@ -256,13 +256,13 @@ // XOSC // RCOSCHFDLF Low frequency clock derived from High Frequency // RCOSC -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_W 2 -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M 0x0000000C -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S 2 -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCLF 0x0000000C -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCLF 0x00000008 -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF 0x00000004 -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCHFDLF 0x00000000 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_W 2 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M 0x0000000C +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S 2 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCLF 0x0000000C +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCLF 0x00000008 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF 0x00000004 +#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCHFDLF 0x00000000 // Field: [1] SCLK_MF_SRC_SEL // @@ -271,11 +271,11 @@ // XCOSCHFDMF Medium frequency clock derived from high frequency // XOSC. // RCOSCHFDMF Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL 0x00000002 -#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_M 0x00000002 -#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_S 1 -#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_XCOSCHFDMF 0x00000002 -#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_RCOSCHFDMF 0x00000000 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL 0x00000002 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_M 0x00000002 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_S 1 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_XCOSCHFDMF 0x00000002 +#define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL_RCOSCHFDMF 0x00000000 // Field: [0] SCLK_HF_SRC_SEL // @@ -284,11 +284,11 @@ // ENUMs: // XOSC High frequency XOSC clk // RCOSC High frequency RCOSC clock -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL 0x00000001 -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M 0x00000001 -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S 0 -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC 0x00000001 -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC 0x00000000 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S 0 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC 0x00000001 +#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC 0x00000000 //***************************************************************************** // @@ -298,23 +298,23 @@ // Field: [22:18] RCOSCHFCTRIMFRACT // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_W 5 -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_M 0x007C0000 -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_S 18 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_W 5 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_M 0x007C0000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_S 18 // Field: [17] RCOSCHFCTRIMFRACT_EN // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN 0x00020000 -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_M 0x00020000 -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_S 17 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN 0x00020000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_M 0x00020000 +#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_S 17 // Field: [1:0] XOSC_HF_FAST_START // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_W 2 -#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_M 0x00000003 -#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_S 0 +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_W 2 +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_M 0x00000003 +#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_S 0 //***************************************************************************** // @@ -324,37 +324,37 @@ // Field: [31:22] HPM_IBIAS_WAIT_CNT // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_W 10 -#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_M 0xFFC00000 -#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S 22 +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_W 10 +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_M 0xFFC00000 +#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S 22 // Field: [21:16] LPM_IBIAS_WAIT_CNT // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_W 6 -#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_M 0x003F0000 -#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S 16 +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_W 6 +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_M 0x003F0000 +#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S 16 // Field: [15:12] IDAC_STEP // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_W 4 -#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_M 0x0000F000 -#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S 12 +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_W 4 +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_M 0x0000F000 +#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S 12 // Field: [11:6] RADC_DAC_TH // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_W 6 -#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_M 0x00000FC0 -#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_S 6 +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_W 6 +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_M 0x00000FC0 +#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_S 6 // Field: [5] RADC_MODE_IS_SAR // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR 0x00000020 -#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_M 0x00000020 -#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_S 5 +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR 0x00000020 +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_M 0x00000020 +#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_S 5 //***************************************************************************** // @@ -364,9 +364,9 @@ // Field: [30] AMPCOMP_REQ_MODE // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE 0x40000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_M 0x40000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S 30 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE 0x40000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_M 0x40000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S 30 // Field: [29:28] AMPCOMP_FSM_UPDATE_RATE // @@ -376,62 +376,62 @@ // 500KHZ Internal. Only to be used through TI provided API. // 1MHZ Internal. Only to be used through TI provided API. // 2MHZ Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_W 2 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_M 0x30000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_S 28 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_250KHZ 0x30000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_500KHZ 0x20000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_1MHZ 0x10000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_2MHZ 0x00000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_W 2 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_M 0x30000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_S 28 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_250KHZ 0x30000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_500KHZ 0x20000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_1MHZ 0x10000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_2MHZ 0x00000000 // Field: [27] AMPCOMP_SW_CTRL // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL 0x08000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_M 0x08000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_S 27 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL 0x08000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_M 0x08000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_S 27 // Field: [26] AMPCOMP_SW_EN // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN 0x04000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_M 0x04000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_S 26 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN 0x04000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_M 0x04000000 +#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_S 26 // Field: [23:20] IBIAS_OFFSET // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_W 4 -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M 0x00F00000 -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S 20 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M 0x00F00000 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S 20 // Field: [19:16] IBIAS_INIT // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_W 4 -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M 0x000F0000 -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S 16 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M 0x000F0000 +#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S 16 // Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_W 8 -#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 -#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S 8 +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_W 8 +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 +#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S 8 // Field: [7:4] CAP_STEP // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_W 4 -#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_M 0x000000F0 -#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S 4 +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_W 4 +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_M 0x000000F0 +#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S 4 // Field: [3:0] IBIASCAP_HPTOLP_OL_CNT // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_W 4 -#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F -#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S 0 +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_W 4 +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F +#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S 0 //***************************************************************************** // @@ -441,30 +441,30 @@ // Field: [23:18] HPMRAMP3_LTH // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_W 6 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M 0x00FC0000 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S 18 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M 0x00FC0000 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S 18 // Field: [15:10] HPMRAMP3_HTH // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_W 6 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M 0x0000FC00 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S 10 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M 0x0000FC00 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S 10 // Field: [9:6] IBIASCAP_LPTOHP_OL_CNT // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_W 4 -#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 -#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S 6 +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_W 4 +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 +#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S 6 // Field: [5:0] HPMRAMP1_TH // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_W 6 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_M 0x0000003F -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S 0 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_W 6 +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_M 0x0000003F +#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S 0 //***************************************************************************** // @@ -474,30 +474,30 @@ // Field: [31:26] LPMUPDATE_LTH // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_W 6 -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_M 0xFC000000 -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S 26 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_W 6 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_M 0xFC000000 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S 26 // Field: [23:18] LPMUPDATE_HTH // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_W 6 -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_M 0x00FC0000 -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S 18 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_W 6 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_M 0x00FC0000 +#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S 18 // Field: [15:10] ADC_COMP_AMPTH_LPM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_W 6 -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S 10 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_W 6 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S 10 // Field: [7:2] ADC_COMP_AMPTH_HPM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_W 6 -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_M 0x000000FC -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S 2 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_W 6 +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_M 0x000000FC +#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S 2 //***************************************************************************** // @@ -507,16 +507,16 @@ // Field: [19:16] XOSC_HF_ROW_Q12 // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_W 4 -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_M 0x000F0000 -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S 16 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_W 4 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_M 0x000F0000 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S 16 // Field: [15:0] XOSC_HF_COLUMN_Q12 // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_W 16 -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_M 0x0000FFFF -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S 0 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_W 16 +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_M 0x0000FFFF +#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S 0 //***************************************************************************** // @@ -526,9 +526,9 @@ // Field: [13:0] XOSC_HF_IBIASTHERM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_W 14 -#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_M 0x00003FFF -#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S 0 +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_W 14 +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_M 0x00003FFF +#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S 0 //***************************************************************************** // @@ -538,9 +538,9 @@ // Field: [29] SCLK_LF_AUX_EN // // Enable 32 kHz clock to AUX_COMPB. -#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN 0x20000000 -#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_M 0x20000000 -#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_S 29 +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN 0x20000000 +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_M 0x20000000 +#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_S 29 //***************************************************************************** // @@ -550,38 +550,38 @@ // Field: [24] NANOAMP_BIAS_ENABLE // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE 0x01000000 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_M 0x01000000 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_S 24 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE 0x01000000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_M 0x01000000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_S 24 // Field: [23] SPARE23 // // Software should not rely on the value of a reserved. Writing any other value // than the reset value may result in undefined behavior -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23 0x00800000 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_M 0x00800000 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_S 23 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23 0x00800000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_M 0x00800000 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_S 23 // Field: [5] ADC_SH_MODE_EN // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN 0x00000020 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_M 0x00000020 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_S 5 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN 0x00000020 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_M 0x00000020 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_S 5 // Field: [4] ADC_SH_VBUF_EN // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN 0x00000010 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_M 0x00000010 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_S 4 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN 0x00000010 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_M 0x00000010 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_S 4 // Field: [1:0] ADC_IREF_CTRL // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_W 2 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_M 0x00000003 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_S 0 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_W 2 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_M 0x00000003 +#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_S 0 //***************************************************************************** // @@ -591,30 +591,30 @@ // Field: [9:8] PEAK_DET_ITRIM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_W 2 -#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_M 0x00000300 -#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S 8 +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_W 2 +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_M 0x00000300 +#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S 8 // Field: [6] BYPASS // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_XOSCHFCTL_BYPASS 0x00000040 -#define DDI_0_OSC_XOSCHFCTL_BYPASS_M 0x00000040 -#define DDI_0_OSC_XOSCHFCTL_BYPASS_S 6 +#define DDI_0_OSC_XOSCHFCTL_BYPASS 0x00000040 +#define DDI_0_OSC_XOSCHFCTL_BYPASS_M 0x00000040 +#define DDI_0_OSC_XOSCHFCTL_BYPASS_S 6 // Field: [4:2] HP_BUF_ITRIM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_W 3 -#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_M 0x0000001C -#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S 2 +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_W 3 +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_M 0x0000001C +#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S 2 // Field: [1:0] LP_BUF_ITRIM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_W 2 -#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_M 0x00000003 -#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S 0 +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_W 2 +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_M 0x00000003 +#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S 0 //***************************************************************************** // @@ -624,16 +624,16 @@ // Field: [23:22] XOSCLF_REGULATOR_TRIM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_W 2 -#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_M 0x00C00000 -#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_S 22 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_W 2 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_M 0x00C00000 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_S 22 // Field: [21:18] XOSCLF_CMIRRWR_RATIO // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_W 4 -#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_M 0x003C0000 -#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_S 18 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_W 4 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_M 0x003C0000 +#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_S 18 // Field: [9:8] RCOSCLF_RTUNE_TRIM // @@ -643,20 +643,20 @@ // 6P5MEG Internal. Only to be used through TI provided API. // 7P0MEG Internal. Only to be used through TI provided API. // 7P5MEG Internal. Only to be used through TI provided API. -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_W 2 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M 0x00000300 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S 8 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P0MEG 0x00000300 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P5MEG 0x00000200 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P0MEG 0x00000100 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P5MEG 0x00000000 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_W 2 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M 0x00000300 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S 8 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P0MEG 0x00000300 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P5MEG 0x00000200 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P0MEG 0x00000100 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P5MEG 0x00000000 // Field: [7:0] RCOSCLF_CTUNE_TRIM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_W 8 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M 0x000000FF -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S 0 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_W 8 +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M 0x000000FF +#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S 0 //***************************************************************************** // @@ -666,9 +666,9 @@ // Field: [15:8] RCOSCHF_CTRIM // // Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_W 8 -#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M 0x0000FF00 -#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S 8 +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_W 8 +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M 0x0000FF00 +#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S 8 //***************************************************************************** // @@ -685,13 +685,13 @@ // XOSC // RCOSCHFDLF Low frequency clock derived from High Frequency // RCOSC -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_W 2 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_M 0x60000000 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_S 29 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCLF 0x60000000 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCLF 0x40000000 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCHFDLF 0x20000000 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCHFDLF 0x00000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_W 2 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_M 0x60000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_S 29 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCLF 0x60000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCLF 0x40000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCHFDLF 0x20000000 +#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCHFDLF 0x00000000 // Field: [28] SCLK_HF_SRC // @@ -699,67 +699,67 @@ // ENUMs: // XOSC High frequency XOSC // RCOSC High frequency RCOSC clock -#define DDI_0_OSC_STAT0_SCLK_HF_SRC 0x10000000 -#define DDI_0_OSC_STAT0_SCLK_HF_SRC_M 0x10000000 -#define DDI_0_OSC_STAT0_SCLK_HF_SRC_S 28 -#define DDI_0_OSC_STAT0_SCLK_HF_SRC_XOSC 0x10000000 -#define DDI_0_OSC_STAT0_SCLK_HF_SRC_RCOSC 0x00000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_M 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_S 28 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_XOSC 0x10000000 +#define DDI_0_OSC_STAT0_SCLK_HF_SRC_RCOSC 0x00000000 // Field: [22] RCOSC_HF_EN // // RCOSC_HF_EN -#define DDI_0_OSC_STAT0_RCOSC_HF_EN 0x00400000 -#define DDI_0_OSC_STAT0_RCOSC_HF_EN_M 0x00400000 -#define DDI_0_OSC_STAT0_RCOSC_HF_EN_S 22 +#define DDI_0_OSC_STAT0_RCOSC_HF_EN 0x00400000 +#define DDI_0_OSC_STAT0_RCOSC_HF_EN_M 0x00400000 +#define DDI_0_OSC_STAT0_RCOSC_HF_EN_S 22 // Field: [21] RCOSC_LF_EN // // RCOSC_LF_EN -#define DDI_0_OSC_STAT0_RCOSC_LF_EN 0x00200000 -#define DDI_0_OSC_STAT0_RCOSC_LF_EN_M 0x00200000 -#define DDI_0_OSC_STAT0_RCOSC_LF_EN_S 21 +#define DDI_0_OSC_STAT0_RCOSC_LF_EN 0x00200000 +#define DDI_0_OSC_STAT0_RCOSC_LF_EN_M 0x00200000 +#define DDI_0_OSC_STAT0_RCOSC_LF_EN_S 21 // Field: [20] XOSC_LF_EN // // XOSC_LF_EN -#define DDI_0_OSC_STAT0_XOSC_LF_EN 0x00100000 -#define DDI_0_OSC_STAT0_XOSC_LF_EN_M 0x00100000 -#define DDI_0_OSC_STAT0_XOSC_LF_EN_S 20 +#define DDI_0_OSC_STAT0_XOSC_LF_EN 0x00100000 +#define DDI_0_OSC_STAT0_XOSC_LF_EN_M 0x00100000 +#define DDI_0_OSC_STAT0_XOSC_LF_EN_S 20 // Field: [19] CLK_DCDC_RDY // // CLK_DCDC_RDY -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY 0x00080000 -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_M 0x00080000 -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_S 19 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY 0x00080000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_M 0x00080000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_S 19 // Field: [18] CLK_DCDC_RDY_ACK // // CLK_DCDC_RDY_ACK -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK 0x00040000 -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_M 0x00040000 -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_S 18 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK 0x00040000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_M 0x00040000 +#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_S 18 // Field: [17] SCLK_HF_LOSS // // Indicates sclk_hf is lost -#define DDI_0_OSC_STAT0_SCLK_HF_LOSS 0x00020000 -#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_M 0x00020000 -#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_S 17 +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS 0x00020000 +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_M 0x00020000 +#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_S 17 // Field: [16] SCLK_LF_LOSS // // Indicates sclk_lf is lost -#define DDI_0_OSC_STAT0_SCLK_LF_LOSS 0x00010000 -#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_M 0x00010000 -#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_S 16 +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS 0x00010000 +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_M 0x00010000 +#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_S 16 // Field: [15] XOSC_HF_EN // // Indicates that XOSC_HF is enabled. -#define DDI_0_OSC_STAT0_XOSC_HF_EN 0x00008000 -#define DDI_0_OSC_STAT0_XOSC_HF_EN_M 0x00008000 -#define DDI_0_OSC_STAT0_XOSC_HF_EN_S 15 +#define DDI_0_OSC_STAT0_XOSC_HF_EN 0x00008000 +#define DDI_0_OSC_STAT0_XOSC_HF_EN_M 0x00008000 +#define DDI_0_OSC_STAT0_XOSC_HF_EN_S 15 // Field: [13] XB_48M_CLK_EN // @@ -767,51 +767,51 @@ // // It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler // bypass for the 48MHz crystal). -#define DDI_0_OSC_STAT0_XB_48M_CLK_EN 0x00002000 -#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_M 0x00002000 -#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_S 13 +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN 0x00002000 +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_M 0x00002000 +#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_S 13 // Field: [11] XOSC_HF_LP_BUF_EN // // XOSC_HF_LP_BUF_EN -#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN 0x00000800 -#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_M 0x00000800 -#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_S 11 +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN 0x00000800 +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_M 0x00000800 +#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_S 11 // Field: [10] XOSC_HF_HP_BUF_EN // // XOSC_HF_HP_BUF_EN -#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN 0x00000400 -#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_M 0x00000400 -#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_S 10 +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN 0x00000400 +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_M 0x00000400 +#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_S 10 // Field: [8] ADC_THMET // // ADC_THMET -#define DDI_0_OSC_STAT0_ADC_THMET 0x00000100 -#define DDI_0_OSC_STAT0_ADC_THMET_M 0x00000100 -#define DDI_0_OSC_STAT0_ADC_THMET_S 8 +#define DDI_0_OSC_STAT0_ADC_THMET 0x00000100 +#define DDI_0_OSC_STAT0_ADC_THMET_M 0x00000100 +#define DDI_0_OSC_STAT0_ADC_THMET_S 8 // Field: [7] ADC_DATA_READY // // indicates when adc_data is ready. -#define DDI_0_OSC_STAT0_ADC_DATA_READY 0x00000080 -#define DDI_0_OSC_STAT0_ADC_DATA_READY_M 0x00000080 -#define DDI_0_OSC_STAT0_ADC_DATA_READY_S 7 +#define DDI_0_OSC_STAT0_ADC_DATA_READY 0x00000080 +#define DDI_0_OSC_STAT0_ADC_DATA_READY_M 0x00000080 +#define DDI_0_OSC_STAT0_ADC_DATA_READY_S 7 // Field: [6:1] ADC_DATA // // adc_data -#define DDI_0_OSC_STAT0_ADC_DATA_W 6 -#define DDI_0_OSC_STAT0_ADC_DATA_M 0x0000007E -#define DDI_0_OSC_STAT0_ADC_DATA_S 1 +#define DDI_0_OSC_STAT0_ADC_DATA_W 6 +#define DDI_0_OSC_STAT0_ADC_DATA_M 0x0000007E +#define DDI_0_OSC_STAT0_ADC_DATA_S 1 // Field: [0] PENDINGSCLKHFSWITCHING // // Indicates when sclk_hf is ready to be switched -#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING 0x00000001 -#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M 0x00000001 -#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S 0 +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING 0x00000001 +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M 0x00000001 +#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S 0 //***************************************************************************** // @@ -837,24 +837,24 @@ // HPM_RAMP1 HPM_RAMP1 // INITIALIZATION INITIALIZATION // RESET RESET -#define DDI_0_OSC_STAT1_RAMPSTATE_W 4 -#define DDI_0_OSC_STAT1_RAMPSTATE_M 0xF0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_S 28 -#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START_SETTLE 0xE0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START 0xD0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_DUMMY_TO_INIT_1 0xC0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_DEC_W_MEASURE 0xB0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_INC 0xA0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_LPM_UPDATE 0x90000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_DEC_W_MEASURE 0x80000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_CAP_UPDATE 0x70000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_INCREMENT 0x60000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_UPDATE 0x50000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP3 0x40000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP2 0x30000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP1 0x20000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_INITIALIZATION 0x10000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_RESET 0x00000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_W 4 +#define DDI_0_OSC_STAT1_RAMPSTATE_M 0xF0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_S 28 +#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START_SETTLE 0xE0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START 0xD0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_DUMMY_TO_INIT_1 0xC0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_DEC_W_MEASURE 0xB0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_INC 0xA0000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_LPM_UPDATE 0x90000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_DEC_W_MEASURE 0x80000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_CAP_UPDATE 0x70000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_INCREMENT 0x60000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_UPDATE 0x50000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP3 0x40000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP2 0x30000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP1 0x20000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_INITIALIZATION 0x10000000 +#define DDI_0_OSC_STAT1_RAMPSTATE_RESET 0x00000000 // Field: [27:22] HPM_UPDATE_AMP // @@ -865,9 +865,9 @@ // would indicate that the amplitude of the crystal is approximately 480 mV. // To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero // value. -#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_W 6 -#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M 0x0FC00000 -#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S 22 +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_W 6 +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M 0x0FC00000 +#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S 22 // Field: [21:16] LPM_UPDATE_AMP // @@ -878,121 +878,121 @@ // indicate that the amplitude of the crystal is approximately 480 mV. To // enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero // value. -#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_W 6 -#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_M 0x003F0000 -#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_S 16 +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_W 6 +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_M 0x003F0000 +#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_S 16 // Field: [15] FORCE_RCOSC_HF // // force_rcosc_hf -#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF 0x00008000 -#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_M 0x00008000 -#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_S 15 +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF 0x00008000 +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_M 0x00008000 +#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_S 15 // Field: [14] SCLK_HF_EN // // SCLK_HF_EN -#define DDI_0_OSC_STAT1_SCLK_HF_EN 0x00004000 -#define DDI_0_OSC_STAT1_SCLK_HF_EN_M 0x00004000 -#define DDI_0_OSC_STAT1_SCLK_HF_EN_S 14 +#define DDI_0_OSC_STAT1_SCLK_HF_EN 0x00004000 +#define DDI_0_OSC_STAT1_SCLK_HF_EN_M 0x00004000 +#define DDI_0_OSC_STAT1_SCLK_HF_EN_S 14 // Field: [13] SCLK_MF_EN // // SCLK_MF_EN -#define DDI_0_OSC_STAT1_SCLK_MF_EN 0x00002000 -#define DDI_0_OSC_STAT1_SCLK_MF_EN_M 0x00002000 -#define DDI_0_OSC_STAT1_SCLK_MF_EN_S 13 +#define DDI_0_OSC_STAT1_SCLK_MF_EN 0x00002000 +#define DDI_0_OSC_STAT1_SCLK_MF_EN_M 0x00002000 +#define DDI_0_OSC_STAT1_SCLK_MF_EN_S 13 // Field: [12] ACLK_ADC_EN // // ACLK_ADC_EN -#define DDI_0_OSC_STAT1_ACLK_ADC_EN 0x00001000 -#define DDI_0_OSC_STAT1_ACLK_ADC_EN_M 0x00001000 -#define DDI_0_OSC_STAT1_ACLK_ADC_EN_S 12 +#define DDI_0_OSC_STAT1_ACLK_ADC_EN 0x00001000 +#define DDI_0_OSC_STAT1_ACLK_ADC_EN_M 0x00001000 +#define DDI_0_OSC_STAT1_ACLK_ADC_EN_S 12 // Field: [11] ACLK_TDC_EN // // ACLK_TDC_EN -#define DDI_0_OSC_STAT1_ACLK_TDC_EN 0x00000800 -#define DDI_0_OSC_STAT1_ACLK_TDC_EN_M 0x00000800 -#define DDI_0_OSC_STAT1_ACLK_TDC_EN_S 11 +#define DDI_0_OSC_STAT1_ACLK_TDC_EN 0x00000800 +#define DDI_0_OSC_STAT1_ACLK_TDC_EN_M 0x00000800 +#define DDI_0_OSC_STAT1_ACLK_TDC_EN_S 11 // Field: [10] ACLK_REF_EN // // ACLK_REF_EN -#define DDI_0_OSC_STAT1_ACLK_REF_EN 0x00000400 -#define DDI_0_OSC_STAT1_ACLK_REF_EN_M 0x00000400 -#define DDI_0_OSC_STAT1_ACLK_REF_EN_S 10 +#define DDI_0_OSC_STAT1_ACLK_REF_EN 0x00000400 +#define DDI_0_OSC_STAT1_ACLK_REF_EN_M 0x00000400 +#define DDI_0_OSC_STAT1_ACLK_REF_EN_S 10 // Field: [9] CLK_CHP_EN // // CLK_CHP_EN -#define DDI_0_OSC_STAT1_CLK_CHP_EN 0x00000200 -#define DDI_0_OSC_STAT1_CLK_CHP_EN_M 0x00000200 -#define DDI_0_OSC_STAT1_CLK_CHP_EN_S 9 +#define DDI_0_OSC_STAT1_CLK_CHP_EN 0x00000200 +#define DDI_0_OSC_STAT1_CLK_CHP_EN_M 0x00000200 +#define DDI_0_OSC_STAT1_CLK_CHP_EN_S 9 // Field: [8] CLK_DCDC_EN // // CLK_DCDC_EN -#define DDI_0_OSC_STAT1_CLK_DCDC_EN 0x00000100 -#define DDI_0_OSC_STAT1_CLK_DCDC_EN_M 0x00000100 -#define DDI_0_OSC_STAT1_CLK_DCDC_EN_S 8 +#define DDI_0_OSC_STAT1_CLK_DCDC_EN 0x00000100 +#define DDI_0_OSC_STAT1_CLK_DCDC_EN_M 0x00000100 +#define DDI_0_OSC_STAT1_CLK_DCDC_EN_S 8 // Field: [7] SCLK_HF_GOOD // // SCLK_HF_GOOD -#define DDI_0_OSC_STAT1_SCLK_HF_GOOD 0x00000080 -#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_M 0x00000080 -#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_S 7 +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD 0x00000080 +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_M 0x00000080 +#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_S 7 // Field: [6] SCLK_MF_GOOD // // SCLK_MF_GOOD -#define DDI_0_OSC_STAT1_SCLK_MF_GOOD 0x00000040 -#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_M 0x00000040 -#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_S 6 +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD 0x00000040 +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_M 0x00000040 +#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_S 6 // Field: [5] SCLK_LF_GOOD // // SCLK_LF_GOOD -#define DDI_0_OSC_STAT1_SCLK_LF_GOOD 0x00000020 -#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_M 0x00000020 -#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_S 5 +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD 0x00000020 +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_M 0x00000020 +#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_S 5 // Field: [4] ACLK_ADC_GOOD // // ACLK_ADC_GOOD -#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD 0x00000010 -#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_M 0x00000010 -#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_S 4 +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD 0x00000010 +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_M 0x00000010 +#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_S 4 // Field: [3] ACLK_TDC_GOOD // // ACLK_TDC_GOOD -#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD 0x00000008 -#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_M 0x00000008 -#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_S 3 +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD 0x00000008 +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_M 0x00000008 +#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_S 3 // Field: [2] ACLK_REF_GOOD // // ACLK_REF_GOOD -#define DDI_0_OSC_STAT1_ACLK_REF_GOOD 0x00000004 -#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_M 0x00000004 -#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_S 2 +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD 0x00000004 +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_M 0x00000004 +#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_S 2 // Field: [1] CLK_CHP_GOOD // // CLK_CHP_GOOD -#define DDI_0_OSC_STAT1_CLK_CHP_GOOD 0x00000002 -#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_M 0x00000002 -#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_S 1 +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD 0x00000002 +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_M 0x00000002 +#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_S 1 // Field: [0] CLK_DCDC_GOOD // // CLK_DCDC_GOOD -#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD 0x00000001 -#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_M 0x00000001 -#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_S 0 +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD 0x00000001 +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_M 0x00000001 +#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_S 0 //***************************************************************************** // @@ -1003,69 +1003,68 @@ // // DC Bias read by RADC during SAR mode // The value is an unsigned integer. It is used for debug only. -#define DDI_0_OSC_STAT2_ADC_DCBIAS_W 6 -#define DDI_0_OSC_STAT2_ADC_DCBIAS_M 0xFC000000 -#define DDI_0_OSC_STAT2_ADC_DCBIAS_S 26 +#define DDI_0_OSC_STAT2_ADC_DCBIAS_W 6 +#define DDI_0_OSC_STAT2_ADC_DCBIAS_M 0xFC000000 +#define DDI_0_OSC_STAT2_ADC_DCBIAS_S 26 // Field: [25] HPM_RAMP1_THMET // // Indication of threshold is met for hpm_ramp1 -#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET 0x02000000 -#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_M 0x02000000 -#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_S 25 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET 0x02000000 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_M 0x02000000 +#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_S 25 // Field: [24] HPM_RAMP2_THMET // // Indication of threshold is met for hpm_ramp2 -#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET 0x01000000 -#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_M 0x01000000 -#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_S 24 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET 0x01000000 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_M 0x01000000 +#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_S 24 // Field: [23] HPM_RAMP3_THMET // // Indication of threshold is met for hpm_ramp3 -#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET 0x00800000 -#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_M 0x00800000 -#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_S 23 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET 0x00800000 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_M 0x00800000 +#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_S 23 // Field: [15:12] RAMPSTATE // // xosc_hf amplitude compensation FSM // // This is identical to STAT1.RAMPSTATE. See that description for encoding. -#define DDI_0_OSC_STAT2_RAMPSTATE_W 4 -#define DDI_0_OSC_STAT2_RAMPSTATE_M 0x0000F000 -#define DDI_0_OSC_STAT2_RAMPSTATE_S 12 +#define DDI_0_OSC_STAT2_RAMPSTATE_W 4 +#define DDI_0_OSC_STAT2_RAMPSTATE_M 0x0000F000 +#define DDI_0_OSC_STAT2_RAMPSTATE_S 12 // Field: [3] AMPCOMP_REQ // // ampcomp_req -#define DDI_0_OSC_STAT2_AMPCOMP_REQ 0x00000008 -#define DDI_0_OSC_STAT2_AMPCOMP_REQ_M 0x00000008 -#define DDI_0_OSC_STAT2_AMPCOMP_REQ_S 3 +#define DDI_0_OSC_STAT2_AMPCOMP_REQ 0x00000008 +#define DDI_0_OSC_STAT2_AMPCOMP_REQ_M 0x00000008 +#define DDI_0_OSC_STAT2_AMPCOMP_REQ_S 3 // Field: [2] XOSC_HF_AMPGOOD // // amplitude of xosc_hf is within the required threshold (set by DDI). Not used // for anything just for debug/status -#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD 0x00000004 -#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_M 0x00000004 -#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_S 2 +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD 0x00000004 +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_M 0x00000004 +#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_S 2 // Field: [1] XOSC_HF_FREQGOOD // // frequency of xosc_hf is good to use for the digital clocks -#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD 0x00000002 -#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_M 0x00000002 -#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_S 1 +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD 0x00000002 +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_M 0x00000002 +#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_S 1 // Field: [0] XOSC_HF_RF_FREQGOOD // // frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio // operations. Used for SW to start synthesizer. -#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD 0x00000001 -#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_M 0x00000001 -#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_S 0 - +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD 0x00000001 +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_M 0x00000001 +#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_S 0 #endif // __DDI_0_OSC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_device.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_device.h index 7ce61f6..2289d6c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_device.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_device.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_device.h -* Revised: 2017-06-21 10:06:25 +0200 (Wed, 21 Jun 2017) -* Revision: 49177 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_device.h + * Revised: 2017-06-21 10:06:25 +0200 (Wed, 21 Jun 2017) + * Revision: 49177 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_DEVICE_H__ #define __HW_DEVICE_H__ @@ -41,128 +41,128 @@ #ifdef CC_GET_CHIP_PACKAGE - #if ( CC_GET_CHIP_PACKAGE == 0x7 ) - //***************************************************************************** - // - // The following are defines for edge detection on wake up events for the - // CC26xx 7x7 packaged device. - // - //***************************************************************************** - #define AON_EVENT_DIO0 18 - #define AON_EVENT_DIO1 17 - #define AON_EVENT_DIO2 16 - #define AON_EVENT_DIO3 15 - #define AON_EVENT_DIO4 14 - #define AON_EVENT_DIO5 13 - #define AON_EVENT_DIO6 12 - #define AON_EVENT_DIO7 11 - #define AON_EVENT_DIO8 10 - #define AON_EVENT_DIO9 9 - #define AON_EVENT_DIO10 8 - #define AON_EVENT_DIO11 7 - #define AON_EVENT_DIO12 6 - #define AON_EVENT_DIO13 5 - #define AON_EVENT_DIO14 4 - #define AON_EVENT_DIO15 3 - #define AON_EVENT_DIO16 2 - #define AON_EVENT_DIO17 1 - #define AON_EVENT_DIO18 31 - #define AON_EVENT_DIO19 30 - #define AON_EVENT_DIO20 29 - #define AON_EVENT_DIO21 28 - #define AON_EVENT_DIO22 27 - #define AON_EVENT_DIO23 26 - #define AON_EVENT_DIO24 25 - #define AON_EVENT_DIO25 24 - #define AON_EVENT_DIO26 23 - #define AON_EVENT_DIO27 22 - #define AON_EVENT_DIO28 21 - #define AON_EVENT_DIO29 20 - #define AON_EVENT_DIO30 19 - #define AON_EVENT_DIO31 0x3F - #endif // ( CC_GET_CHIP_PACKAGE == 0x7 ) +#if (CC_GET_CHIP_PACKAGE == 0x7) +//***************************************************************************** +// +// The following are defines for edge detection on wake up events for the +// CC26xx 7x7 packaged device. +// +//***************************************************************************** +#define AON_EVENT_DIO0 18 +#define AON_EVENT_DIO1 17 +#define AON_EVENT_DIO2 16 +#define AON_EVENT_DIO3 15 +#define AON_EVENT_DIO4 14 +#define AON_EVENT_DIO5 13 +#define AON_EVENT_DIO6 12 +#define AON_EVENT_DIO7 11 +#define AON_EVENT_DIO8 10 +#define AON_EVENT_DIO9 9 +#define AON_EVENT_DIO10 8 +#define AON_EVENT_DIO11 7 +#define AON_EVENT_DIO12 6 +#define AON_EVENT_DIO13 5 +#define AON_EVENT_DIO14 4 +#define AON_EVENT_DIO15 3 +#define AON_EVENT_DIO16 2 +#define AON_EVENT_DIO17 1 +#define AON_EVENT_DIO18 31 +#define AON_EVENT_DIO19 30 +#define AON_EVENT_DIO20 29 +#define AON_EVENT_DIO21 28 +#define AON_EVENT_DIO22 27 +#define AON_EVENT_DIO23 26 +#define AON_EVENT_DIO24 25 +#define AON_EVENT_DIO25 24 +#define AON_EVENT_DIO26 23 +#define AON_EVENT_DIO27 22 +#define AON_EVENT_DIO28 21 +#define AON_EVENT_DIO29 20 +#define AON_EVENT_DIO30 19 +#define AON_EVENT_DIO31 0x3F +#endif // ( CC_GET_CHIP_PACKAGE == 0x7 ) - #if ( CC_GET_CHIP_PACKAGE == 0x5 ) - //***************************************************************************** - // - // The following are defines for edge detection on wake up events for the - // CC26xx 5x5 packaged device. - // - //***************************************************************************** - #define AON_EVENT_DIO0 15 - #define AON_EVENT_DIO1 14 - #define AON_EVENT_DIO2 13 - #define AON_EVENT_DIO3 12 - #define AON_EVENT_DIO4 11 - #define AON_EVENT_DIO5 2 - #define AON_EVENT_DIO6 1 - #define AON_EVENT_DIO7 26 - #define AON_EVENT_DIO8 25 - #define AON_EVENT_DIO9 23 - #define AON_EVENT_DIO10 24 - #define AON_EVENT_DIO11 22 - #define AON_EVENT_DIO12 21 - #define AON_EVENT_DIO13 20 - #define AON_EVENT_DIO14 19 - #define AON_EVENT_DIO15 0x3F - #define AON_EVENT_DIO16 0x3F - #define AON_EVENT_DIO17 0x3F - #define AON_EVENT_DIO18 0x3F - #define AON_EVENT_DIO19 0x3F - #define AON_EVENT_DIO20 0x3F - #define AON_EVENT_DIO21 0x3F - #define AON_EVENT_DIO22 0x3F - #define AON_EVENT_DIO23 0x3F - #define AON_EVENT_DIO24 0x3F - #define AON_EVENT_DIO25 0x3F - #define AON_EVENT_DIO26 0x3F - #define AON_EVENT_DIO27 0x3F - #define AON_EVENT_DIO28 0x3F - #define AON_EVENT_DIO29 0x3F - #define AON_EVENT_DIO30 0x3F - #define AON_EVENT_DIO31 0x3F - #endif // ( CC_GET_CHIP_PACKAGE == 0x5 ) +#if (CC_GET_CHIP_PACKAGE == 0x5) +//***************************************************************************** +// +// The following are defines for edge detection on wake up events for the +// CC26xx 5x5 packaged device. +// +//***************************************************************************** +#define AON_EVENT_DIO0 15 +#define AON_EVENT_DIO1 14 +#define AON_EVENT_DIO2 13 +#define AON_EVENT_DIO3 12 +#define AON_EVENT_DIO4 11 +#define AON_EVENT_DIO5 2 +#define AON_EVENT_DIO6 1 +#define AON_EVENT_DIO7 26 +#define AON_EVENT_DIO8 25 +#define AON_EVENT_DIO9 23 +#define AON_EVENT_DIO10 24 +#define AON_EVENT_DIO11 22 +#define AON_EVENT_DIO12 21 +#define AON_EVENT_DIO13 20 +#define AON_EVENT_DIO14 19 +#define AON_EVENT_DIO15 0x3F +#define AON_EVENT_DIO16 0x3F +#define AON_EVENT_DIO17 0x3F +#define AON_EVENT_DIO18 0x3F +#define AON_EVENT_DIO19 0x3F +#define AON_EVENT_DIO20 0x3F +#define AON_EVENT_DIO21 0x3F +#define AON_EVENT_DIO22 0x3F +#define AON_EVENT_DIO23 0x3F +#define AON_EVENT_DIO24 0x3F +#define AON_EVENT_DIO25 0x3F +#define AON_EVENT_DIO26 0x3F +#define AON_EVENT_DIO27 0x3F +#define AON_EVENT_DIO28 0x3F +#define AON_EVENT_DIO29 0x3F +#define AON_EVENT_DIO30 0x3F +#define AON_EVENT_DIO31 0x3F +#endif // ( CC_GET_CHIP_PACKAGE == 0x5 ) - #if ( CC_GET_CHIP_PACKAGE == 0x4 ) - //***************************************************************************** - // - // The following are defines for edge detection on wake up events for the - // CC26xx 4x4 packaged device. - // - //***************************************************************************** - #define AON_EVENT_DIO0 13 - #define AON_EVENT_DIO1 12 - #define AON_EVENT_DIO2 11 - #define AON_EVENT_DIO3 2 - #define AON_EVENT_DIO4 1 - #define AON_EVENT_DIO5 26 - #define AON_EVENT_DIO6 25 - #define AON_EVENT_DIO7 24 - #define AON_EVENT_DIO8 23 - #define AON_EVENT_DIO9 22 - #define AON_EVENT_DIO10 0x3F - #define AON_EVENT_DIO11 0x3F - #define AON_EVENT_DIO12 0x3F - #define AON_EVENT_DIO13 0x3F - #define AON_EVENT_DIO14 0x3F - #define AON_EVENT_DIO15 0x3F - #define AON_EVENT_DIO16 0x3F - #define AON_EVENT_DIO17 0x3F - #define AON_EVENT_DIO18 0x3F - #define AON_EVENT_DIO19 0x3F - #define AON_EVENT_DIO20 0x3F - #define AON_EVENT_DIO21 0x3F - #define AON_EVENT_DIO22 0x3F - #define AON_EVENT_DIO23 0x3F - #define AON_EVENT_DIO24 0x3F - #define AON_EVENT_DIO25 0x3F - #define AON_EVENT_DIO26 0x3F - #define AON_EVENT_DIO27 0x3F - #define AON_EVENT_DIO28 0x3F - #define AON_EVENT_DIO29 0x3F - #define AON_EVENT_DIO30 0x3F - #define AON_EVENT_DIO31 0x3F - #endif // ( CC_GET_CHIP_PACKAGE == 0x4 ) +#if (CC_GET_CHIP_PACKAGE == 0x4) +//***************************************************************************** +// +// The following are defines for edge detection on wake up events for the +// CC26xx 4x4 packaged device. +// +//***************************************************************************** +#define AON_EVENT_DIO0 13 +#define AON_EVENT_DIO1 12 +#define AON_EVENT_DIO2 11 +#define AON_EVENT_DIO3 2 +#define AON_EVENT_DIO4 1 +#define AON_EVENT_DIO5 26 +#define AON_EVENT_DIO6 25 +#define AON_EVENT_DIO7 24 +#define AON_EVENT_DIO8 23 +#define AON_EVENT_DIO9 22 +#define AON_EVENT_DIO10 0x3F +#define AON_EVENT_DIO11 0x3F +#define AON_EVENT_DIO12 0x3F +#define AON_EVENT_DIO13 0x3F +#define AON_EVENT_DIO14 0x3F +#define AON_EVENT_DIO15 0x3F +#define AON_EVENT_DIO16 0x3F +#define AON_EVENT_DIO17 0x3F +#define AON_EVENT_DIO18 0x3F +#define AON_EVENT_DIO19 0x3F +#define AON_EVENT_DIO20 0x3F +#define AON_EVENT_DIO21 0x3F +#define AON_EVENT_DIO22 0x3F +#define AON_EVENT_DIO23 0x3F +#define AON_EVENT_DIO24 0x3F +#define AON_EVENT_DIO25 0x3F +#define AON_EVENT_DIO26 0x3F +#define AON_EVENT_DIO27 0x3F +#define AON_EVENT_DIO28 0x3F +#define AON_EVENT_DIO29 0x3F +#define AON_EVENT_DIO30 0x3F +#define AON_EVENT_DIO31 0x3F +#endif // ( CC_GET_CHIP_PACKAGE == 0x4 ) #endif // defined( CC_GET_CHIP_PACKAGE ) #endif // __HW_DEVICE_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_event.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_event.h index 288b54b..8635b19 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_event.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_event.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_event_h -* Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) -* Revision: 48904 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_event_h + * Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) + * Revision: 48904 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_EVENT_H__ #define __HW_EVENT_H__ @@ -44,292 +44,292 @@ // //***************************************************************************** // Output Selection for CPU Interrupt 0 -#define EVENT_O_CPUIRQSEL0 0x00000000 +#define EVENT_O_CPUIRQSEL0 0x00000000 // Output Selection for CPU Interrupt 1 -#define EVENT_O_CPUIRQSEL1 0x00000004 +#define EVENT_O_CPUIRQSEL1 0x00000004 // Output Selection for CPU Interrupt 2 -#define EVENT_O_CPUIRQSEL2 0x00000008 +#define EVENT_O_CPUIRQSEL2 0x00000008 // Output Selection for CPU Interrupt 3 -#define EVENT_O_CPUIRQSEL3 0x0000000C +#define EVENT_O_CPUIRQSEL3 0x0000000C // Output Selection for CPU Interrupt 4 -#define EVENT_O_CPUIRQSEL4 0x00000010 +#define EVENT_O_CPUIRQSEL4 0x00000010 // Output Selection for CPU Interrupt 5 -#define EVENT_O_CPUIRQSEL5 0x00000014 +#define EVENT_O_CPUIRQSEL5 0x00000014 // Output Selection for CPU Interrupt 6 -#define EVENT_O_CPUIRQSEL6 0x00000018 +#define EVENT_O_CPUIRQSEL6 0x00000018 // Output Selection for CPU Interrupt 7 -#define EVENT_O_CPUIRQSEL7 0x0000001C +#define EVENT_O_CPUIRQSEL7 0x0000001C // Output Selection for CPU Interrupt 8 -#define EVENT_O_CPUIRQSEL8 0x00000020 +#define EVENT_O_CPUIRQSEL8 0x00000020 // Output Selection for CPU Interrupt 9 -#define EVENT_O_CPUIRQSEL9 0x00000024 +#define EVENT_O_CPUIRQSEL9 0x00000024 // Output Selection for CPU Interrupt 10 -#define EVENT_O_CPUIRQSEL10 0x00000028 +#define EVENT_O_CPUIRQSEL10 0x00000028 // Output Selection for CPU Interrupt 11 -#define EVENT_O_CPUIRQSEL11 0x0000002C +#define EVENT_O_CPUIRQSEL11 0x0000002C // Output Selection for CPU Interrupt 12 -#define EVENT_O_CPUIRQSEL12 0x00000030 +#define EVENT_O_CPUIRQSEL12 0x00000030 // Output Selection for CPU Interrupt 13 -#define EVENT_O_CPUIRQSEL13 0x00000034 +#define EVENT_O_CPUIRQSEL13 0x00000034 // Output Selection for CPU Interrupt 14 -#define EVENT_O_CPUIRQSEL14 0x00000038 +#define EVENT_O_CPUIRQSEL14 0x00000038 // Output Selection for CPU Interrupt 15 -#define EVENT_O_CPUIRQSEL15 0x0000003C +#define EVENT_O_CPUIRQSEL15 0x0000003C // Output Selection for CPU Interrupt 16 -#define EVENT_O_CPUIRQSEL16 0x00000040 +#define EVENT_O_CPUIRQSEL16 0x00000040 // Output Selection for CPU Interrupt 17 -#define EVENT_O_CPUIRQSEL17 0x00000044 +#define EVENT_O_CPUIRQSEL17 0x00000044 // Output Selection for CPU Interrupt 18 -#define EVENT_O_CPUIRQSEL18 0x00000048 +#define EVENT_O_CPUIRQSEL18 0x00000048 // Output Selection for CPU Interrupt 19 -#define EVENT_O_CPUIRQSEL19 0x0000004C +#define EVENT_O_CPUIRQSEL19 0x0000004C // Output Selection for CPU Interrupt 20 -#define EVENT_O_CPUIRQSEL20 0x00000050 +#define EVENT_O_CPUIRQSEL20 0x00000050 // Output Selection for CPU Interrupt 21 -#define EVENT_O_CPUIRQSEL21 0x00000054 +#define EVENT_O_CPUIRQSEL21 0x00000054 // Output Selection for CPU Interrupt 22 -#define EVENT_O_CPUIRQSEL22 0x00000058 +#define EVENT_O_CPUIRQSEL22 0x00000058 // Output Selection for CPU Interrupt 23 -#define EVENT_O_CPUIRQSEL23 0x0000005C +#define EVENT_O_CPUIRQSEL23 0x0000005C // Output Selection for CPU Interrupt 24 -#define EVENT_O_CPUIRQSEL24 0x00000060 +#define EVENT_O_CPUIRQSEL24 0x00000060 // Output Selection for CPU Interrupt 25 -#define EVENT_O_CPUIRQSEL25 0x00000064 +#define EVENT_O_CPUIRQSEL25 0x00000064 // Output Selection for CPU Interrupt 26 -#define EVENT_O_CPUIRQSEL26 0x00000068 +#define EVENT_O_CPUIRQSEL26 0x00000068 // Output Selection for CPU Interrupt 27 -#define EVENT_O_CPUIRQSEL27 0x0000006C +#define EVENT_O_CPUIRQSEL27 0x0000006C // Output Selection for CPU Interrupt 28 -#define EVENT_O_CPUIRQSEL28 0x00000070 +#define EVENT_O_CPUIRQSEL28 0x00000070 // Output Selection for CPU Interrupt 29 -#define EVENT_O_CPUIRQSEL29 0x00000074 +#define EVENT_O_CPUIRQSEL29 0x00000074 // Output Selection for CPU Interrupt 30 -#define EVENT_O_CPUIRQSEL30 0x00000078 +#define EVENT_O_CPUIRQSEL30 0x00000078 // Output Selection for CPU Interrupt 31 -#define EVENT_O_CPUIRQSEL31 0x0000007C +#define EVENT_O_CPUIRQSEL31 0x0000007C // Output Selection for CPU Interrupt 32 -#define EVENT_O_CPUIRQSEL32 0x00000080 +#define EVENT_O_CPUIRQSEL32 0x00000080 // Output Selection for CPU Interrupt 33 -#define EVENT_O_CPUIRQSEL33 0x00000084 +#define EVENT_O_CPUIRQSEL33 0x00000084 // Output Selection for RFC Event 0 -#define EVENT_O_RFCSEL0 0x00000100 +#define EVENT_O_RFCSEL0 0x00000100 // Output Selection for RFC Event 1 -#define EVENT_O_RFCSEL1 0x00000104 +#define EVENT_O_RFCSEL1 0x00000104 // Output Selection for RFC Event 2 -#define EVENT_O_RFCSEL2 0x00000108 +#define EVENT_O_RFCSEL2 0x00000108 // Output Selection for RFC Event 3 -#define EVENT_O_RFCSEL3 0x0000010C +#define EVENT_O_RFCSEL3 0x0000010C // Output Selection for RFC Event 4 -#define EVENT_O_RFCSEL4 0x00000110 +#define EVENT_O_RFCSEL4 0x00000110 // Output Selection for RFC Event 5 -#define EVENT_O_RFCSEL5 0x00000114 +#define EVENT_O_RFCSEL5 0x00000114 // Output Selection for RFC Event 6 -#define EVENT_O_RFCSEL6 0x00000118 +#define EVENT_O_RFCSEL6 0x00000118 // Output Selection for RFC Event 7 -#define EVENT_O_RFCSEL7 0x0000011C +#define EVENT_O_RFCSEL7 0x0000011C // Output Selection for RFC Event 8 -#define EVENT_O_RFCSEL8 0x00000120 +#define EVENT_O_RFCSEL8 0x00000120 // Output Selection for RFC Event 9 -#define EVENT_O_RFCSEL9 0x00000124 +#define EVENT_O_RFCSEL9 0x00000124 // Output Selection for GPT0 0 -#define EVENT_O_GPT0ACAPTSEL 0x00000200 +#define EVENT_O_GPT0ACAPTSEL 0x00000200 // Output Selection for GPT0 1 -#define EVENT_O_GPT0BCAPTSEL 0x00000204 +#define EVENT_O_GPT0BCAPTSEL 0x00000204 // Output Selection for GPT1 0 -#define EVENT_O_GPT1ACAPTSEL 0x00000300 +#define EVENT_O_GPT1ACAPTSEL 0x00000300 // Output Selection for GPT1 1 -#define EVENT_O_GPT1BCAPTSEL 0x00000304 +#define EVENT_O_GPT1BCAPTSEL 0x00000304 // Output Selection for GPT2 0 -#define EVENT_O_GPT2ACAPTSEL 0x00000400 +#define EVENT_O_GPT2ACAPTSEL 0x00000400 // Output Selection for GPT2 1 -#define EVENT_O_GPT2BCAPTSEL 0x00000404 +#define EVENT_O_GPT2BCAPTSEL 0x00000404 // Output Selection for DMA Channel 1 SREQ -#define EVENT_O_UDMACH1SSEL 0x00000508 +#define EVENT_O_UDMACH1SSEL 0x00000508 // Output Selection for DMA Channel 1 REQ -#define EVENT_O_UDMACH1BSEL 0x0000050C +#define EVENT_O_UDMACH1BSEL 0x0000050C // Output Selection for DMA Channel 2 SREQ -#define EVENT_O_UDMACH2SSEL 0x00000510 +#define EVENT_O_UDMACH2SSEL 0x00000510 // Output Selection for DMA Channel 2 REQ -#define EVENT_O_UDMACH2BSEL 0x00000514 +#define EVENT_O_UDMACH2BSEL 0x00000514 // Output Selection for DMA Channel 3 SREQ -#define EVENT_O_UDMACH3SSEL 0x00000518 +#define EVENT_O_UDMACH3SSEL 0x00000518 // Output Selection for DMA Channel 3 REQ -#define EVENT_O_UDMACH3BSEL 0x0000051C +#define EVENT_O_UDMACH3BSEL 0x0000051C // Output Selection for DMA Channel 4 SREQ -#define EVENT_O_UDMACH4SSEL 0x00000520 +#define EVENT_O_UDMACH4SSEL 0x00000520 // Output Selection for DMA Channel 4 REQ -#define EVENT_O_UDMACH4BSEL 0x00000524 +#define EVENT_O_UDMACH4BSEL 0x00000524 // Output Selection for DMA Channel 5 SREQ -#define EVENT_O_UDMACH5SSEL 0x00000528 +#define EVENT_O_UDMACH5SSEL 0x00000528 // Output Selection for DMA Channel 5 REQ -#define EVENT_O_UDMACH5BSEL 0x0000052C +#define EVENT_O_UDMACH5BSEL 0x0000052C // Output Selection for DMA Channel 6 SREQ -#define EVENT_O_UDMACH6SSEL 0x00000530 +#define EVENT_O_UDMACH6SSEL 0x00000530 // Output Selection for DMA Channel 6 REQ -#define EVENT_O_UDMACH6BSEL 0x00000534 +#define EVENT_O_UDMACH6BSEL 0x00000534 // Output Selection for DMA Channel 7 SREQ -#define EVENT_O_UDMACH7SSEL 0x00000538 +#define EVENT_O_UDMACH7SSEL 0x00000538 // Output Selection for DMA Channel 7 REQ -#define EVENT_O_UDMACH7BSEL 0x0000053C +#define EVENT_O_UDMACH7BSEL 0x0000053C // Output Selection for DMA Channel 8 SREQ -#define EVENT_O_UDMACH8SSEL 0x00000540 +#define EVENT_O_UDMACH8SSEL 0x00000540 // Output Selection for DMA Channel 8 REQ -#define EVENT_O_UDMACH8BSEL 0x00000544 +#define EVENT_O_UDMACH8BSEL 0x00000544 // Output Selection for DMA Channel 9 SREQ -#define EVENT_O_UDMACH9SSEL 0x00000548 +#define EVENT_O_UDMACH9SSEL 0x00000548 // Output Selection for DMA Channel 9 REQ -#define EVENT_O_UDMACH9BSEL 0x0000054C +#define EVENT_O_UDMACH9BSEL 0x0000054C // Output Selection for DMA Channel 10 SREQ -#define EVENT_O_UDMACH10SSEL 0x00000550 +#define EVENT_O_UDMACH10SSEL 0x00000550 // Output Selection for DMA Channel 10 REQ -#define EVENT_O_UDMACH10BSEL 0x00000554 +#define EVENT_O_UDMACH10BSEL 0x00000554 // Output Selection for DMA Channel 11 SREQ -#define EVENT_O_UDMACH11SSEL 0x00000558 +#define EVENT_O_UDMACH11SSEL 0x00000558 // Output Selection for DMA Channel 11 REQ -#define EVENT_O_UDMACH11BSEL 0x0000055C +#define EVENT_O_UDMACH11BSEL 0x0000055C // Output Selection for DMA Channel 12 SREQ -#define EVENT_O_UDMACH12SSEL 0x00000560 +#define EVENT_O_UDMACH12SSEL 0x00000560 // Output Selection for DMA Channel 12 REQ -#define EVENT_O_UDMACH12BSEL 0x00000564 +#define EVENT_O_UDMACH12BSEL 0x00000564 // Output Selection for DMA Channel 13 REQ -#define EVENT_O_UDMACH13BSEL 0x0000056C +#define EVENT_O_UDMACH13BSEL 0x0000056C // Output Selection for DMA Channel 14 REQ -#define EVENT_O_UDMACH14BSEL 0x00000574 +#define EVENT_O_UDMACH14BSEL 0x00000574 // Output Selection for DMA Channel 15 REQ -#define EVENT_O_UDMACH15BSEL 0x0000057C +#define EVENT_O_UDMACH15BSEL 0x0000057C // Output Selection for DMA Channel 16 SREQ -#define EVENT_O_UDMACH16SSEL 0x00000580 +#define EVENT_O_UDMACH16SSEL 0x00000580 // Output Selection for DMA Channel 16 REQ -#define EVENT_O_UDMACH16BSEL 0x00000584 +#define EVENT_O_UDMACH16BSEL 0x00000584 // Output Selection for DMA Channel 17 SREQ -#define EVENT_O_UDMACH17SSEL 0x00000588 +#define EVENT_O_UDMACH17SSEL 0x00000588 // Output Selection for DMA Channel 17 REQ -#define EVENT_O_UDMACH17BSEL 0x0000058C +#define EVENT_O_UDMACH17BSEL 0x0000058C // Output Selection for DMA Channel 21 SREQ -#define EVENT_O_UDMACH21SSEL 0x000005A8 +#define EVENT_O_UDMACH21SSEL 0x000005A8 // Output Selection for DMA Channel 21 REQ -#define EVENT_O_UDMACH21BSEL 0x000005AC +#define EVENT_O_UDMACH21BSEL 0x000005AC // Output Selection for DMA Channel 22 SREQ -#define EVENT_O_UDMACH22SSEL 0x000005B0 +#define EVENT_O_UDMACH22SSEL 0x000005B0 // Output Selection for DMA Channel 22 REQ -#define EVENT_O_UDMACH22BSEL 0x000005B4 +#define EVENT_O_UDMACH22BSEL 0x000005B4 // Output Selection for DMA Channel 23 SREQ -#define EVENT_O_UDMACH23SSEL 0x000005B8 +#define EVENT_O_UDMACH23SSEL 0x000005B8 // Output Selection for DMA Channel 23 REQ -#define EVENT_O_UDMACH23BSEL 0x000005BC +#define EVENT_O_UDMACH23BSEL 0x000005BC // Output Selection for DMA Channel 24 SREQ -#define EVENT_O_UDMACH24SSEL 0x000005C0 +#define EVENT_O_UDMACH24SSEL 0x000005C0 // Output Selection for DMA Channel 24 REQ -#define EVENT_O_UDMACH24BSEL 0x000005C4 +#define EVENT_O_UDMACH24BSEL 0x000005C4 // Output Selection for GPT3 0 -#define EVENT_O_GPT3ACAPTSEL 0x00000600 +#define EVENT_O_GPT3ACAPTSEL 0x00000600 // Output Selection for GPT3 1 -#define EVENT_O_GPT3BCAPTSEL 0x00000604 +#define EVENT_O_GPT3BCAPTSEL 0x00000604 // Output Selection for AUX Subscriber 0 -#define EVENT_O_AUXSEL0 0x00000700 +#define EVENT_O_AUXSEL0 0x00000700 // Output Selection for NMI Subscriber 0 -#define EVENT_O_CM3NMISEL0 0x00000800 +#define EVENT_O_CM3NMISEL0 0x00000800 // Output Selection for I2S Subscriber 0 -#define EVENT_O_I2SSTMPSEL0 0x00000900 +#define EVENT_O_I2SSTMPSEL0 0x00000900 // Output Selection for FRZ Subscriber -#define EVENT_O_FRZSEL0 0x00000A00 +#define EVENT_O_FRZSEL0 0x00000A00 // Set or Clear Software Events -#define EVENT_O_SWEV 0x00000F00 +#define EVENT_O_SWEV 0x00000F00 //***************************************************************************** // @@ -343,10 +343,10 @@ // AON_GPIO_EDGE Edge detect event from IOC. Configureded by the // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings -#define EVENT_CPUIRQSEL0_EV_W 7 -#define EVENT_CPUIRQSEL0_EV_M 0x0000007F -#define EVENT_CPUIRQSEL0_EV_S 0 -#define EVENT_CPUIRQSEL0_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_CPUIRQSEL0_EV_W 7 +#define EVENT_CPUIRQSEL0_EV_M 0x0000007F +#define EVENT_CPUIRQSEL0_EV_S 0 +#define EVENT_CPUIRQSEL0_EV_AON_GPIO_EDGE 0x00000004 //***************************************************************************** // @@ -358,10 +358,10 @@ // Read only selection value // ENUMs: // I2C_IRQ Interrupt event from I2C -#define EVENT_CPUIRQSEL1_EV_W 7 -#define EVENT_CPUIRQSEL1_EV_M 0x0000007F -#define EVENT_CPUIRQSEL1_EV_S 0 -#define EVENT_CPUIRQSEL1_EV_I2C_IRQ 0x00000009 +#define EVENT_CPUIRQSEL1_EV_W 7 +#define EVENT_CPUIRQSEL1_EV_M 0x0000007F +#define EVENT_CPUIRQSEL1_EV_S 0 +#define EVENT_CPUIRQSEL1_EV_I2C_IRQ 0x00000009 //***************************************************************************** // @@ -377,10 +377,10 @@ // RFC_DBELL:RFCPEIFG. Only interrupts selected // with CPE1 in RFC_DBELL:RFCPEIFG can trigger a // RFC_CPE_1 event -#define EVENT_CPUIRQSEL2_EV_W 7 -#define EVENT_CPUIRQSEL2_EV_M 0x0000007F -#define EVENT_CPUIRQSEL2_EV_S 0 -#define EVENT_CPUIRQSEL2_EV_RFC_CPE_1 0x0000001E +#define EVENT_CPUIRQSEL2_EV_W 7 +#define EVENT_CPUIRQSEL2_EV_M 0x0000007F +#define EVENT_CPUIRQSEL2_EV_S 0 +#define EVENT_CPUIRQSEL2_EV_RFC_CPE_1 0x0000001E //***************************************************************************** // @@ -398,10 +398,10 @@ // ENUMs: // AON_RTC_COMB Event from AON_RTC, controlled by the // AON_RTC:CTL.COMB_EV_MASK setting -#define EVENT_CPUIRQSEL4_EV_W 7 -#define EVENT_CPUIRQSEL4_EV_M 0x0000007F -#define EVENT_CPUIRQSEL4_EV_S 0 -#define EVENT_CPUIRQSEL4_EV_AON_RTC_COMB 0x00000007 +#define EVENT_CPUIRQSEL4_EV_W 7 +#define EVENT_CPUIRQSEL4_EV_M 0x0000007F +#define EVENT_CPUIRQSEL4_EV_S 0 +#define EVENT_CPUIRQSEL4_EV_AON_RTC_COMB 0x00000007 //***************************************************************************** // @@ -414,10 +414,10 @@ // ENUMs: // UART0_COMB UART0 combined interrupt, interrupt flags are // found here UART0:MIS -#define EVENT_CPUIRQSEL5_EV_W 7 -#define EVENT_CPUIRQSEL5_EV_M 0x0000007F -#define EVENT_CPUIRQSEL5_EV_S 0 -#define EVENT_CPUIRQSEL5_EV_UART0_COMB 0x00000024 +#define EVENT_CPUIRQSEL5_EV_W 7 +#define EVENT_CPUIRQSEL5_EV_M 0x0000007F +#define EVENT_CPUIRQSEL5_EV_S 0 +#define EVENT_CPUIRQSEL5_EV_UART0_COMB 0x00000024 //***************************************************************************** // @@ -435,10 +435,10 @@ // AON_EVENT:MCUWUSEL // AUX domain wakeup control // AON_EVENT:AUXWUSEL -#define EVENT_CPUIRQSEL6_EV_W 7 -#define EVENT_CPUIRQSEL6_EV_M 0x0000007F -#define EVENT_CPUIRQSEL6_EV_S 0 -#define EVENT_CPUIRQSEL6_EV_AUX_SWEV0 0x0000001C +#define EVENT_CPUIRQSEL6_EV_W 7 +#define EVENT_CPUIRQSEL6_EV_M 0x0000007F +#define EVENT_CPUIRQSEL6_EV_S 0 +#define EVENT_CPUIRQSEL6_EV_AUX_SWEV0 0x0000001C //***************************************************************************** // @@ -451,10 +451,10 @@ // ENUMs: // SSI0_COMB SSI0 combined interrupt, interrupt flags are found // here SSI0:MIS -#define EVENT_CPUIRQSEL7_EV_W 7 -#define EVENT_CPUIRQSEL7_EV_M 0x0000007F -#define EVENT_CPUIRQSEL7_EV_S 0 -#define EVENT_CPUIRQSEL7_EV_SSI0_COMB 0x00000022 +#define EVENT_CPUIRQSEL7_EV_W 7 +#define EVENT_CPUIRQSEL7_EV_M 0x0000007F +#define EVENT_CPUIRQSEL7_EV_S 0 +#define EVENT_CPUIRQSEL7_EV_SSI0_COMB 0x00000022 //***************************************************************************** // @@ -467,10 +467,10 @@ // ENUMs: // SSI1_COMB SSI1 combined interrupt, interrupt flags are found // here SSI1:MIS -#define EVENT_CPUIRQSEL8_EV_W 7 -#define EVENT_CPUIRQSEL8_EV_M 0x0000007F -#define EVENT_CPUIRQSEL8_EV_S 0 -#define EVENT_CPUIRQSEL8_EV_SSI1_COMB 0x00000023 +#define EVENT_CPUIRQSEL8_EV_W 7 +#define EVENT_CPUIRQSEL8_EV_M 0x0000007F +#define EVENT_CPUIRQSEL8_EV_S 0 +#define EVENT_CPUIRQSEL8_EV_SSI1_COMB 0x00000023 //***************************************************************************** // @@ -486,10 +486,10 @@ // RFC_DBELL:RFCPEIFG. Only interrupts selected // with CPE0 in RFC_DBELL:RFCPEIFG can trigger a // RFC_CPE_0 event -#define EVENT_CPUIRQSEL9_EV_W 7 -#define EVENT_CPUIRQSEL9_EV_M 0x0000007F -#define EVENT_CPUIRQSEL9_EV_S 0 -#define EVENT_CPUIRQSEL9_EV_RFC_CPE_0 0x0000001B +#define EVENT_CPUIRQSEL9_EV_W 7 +#define EVENT_CPUIRQSEL9_EV_M 0x0000007F +#define EVENT_CPUIRQSEL9_EV_S 0 +#define EVENT_CPUIRQSEL9_EV_RFC_CPE_0 0x0000001B //***************************************************************************** // @@ -502,10 +502,10 @@ // ENUMs: // RFC_HW_COMB Combined RFC hardware interrupt, corresponding // flag is here RFC_DBELL:RFHWIFG -#define EVENT_CPUIRQSEL10_EV_W 7 -#define EVENT_CPUIRQSEL10_EV_M 0x0000007F -#define EVENT_CPUIRQSEL10_EV_S 0 -#define EVENT_CPUIRQSEL10_EV_RFC_HW_COMB 0x0000001A +#define EVENT_CPUIRQSEL10_EV_W 7 +#define EVENT_CPUIRQSEL10_EV_M 0x0000007F +#define EVENT_CPUIRQSEL10_EV_S 0 +#define EVENT_CPUIRQSEL10_EV_RFC_HW_COMB 0x0000001A //***************************************************************************** // @@ -518,10 +518,10 @@ // ENUMs: // RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, // equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -#define EVENT_CPUIRQSEL11_EV_W 7 -#define EVENT_CPUIRQSEL11_EV_M 0x0000007F -#define EVENT_CPUIRQSEL11_EV_S 0 -#define EVENT_CPUIRQSEL11_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_CPUIRQSEL11_EV_W 7 +#define EVENT_CPUIRQSEL11_EV_M 0x0000007F +#define EVENT_CPUIRQSEL11_EV_S 0 +#define EVENT_CPUIRQSEL11_EV_RFC_CMD_ACK 0x00000019 //***************************************************************************** // @@ -533,10 +533,10 @@ // Read only selection value // ENUMs: // I2S_IRQ Interrupt event from I2S -#define EVENT_CPUIRQSEL12_EV_W 7 -#define EVENT_CPUIRQSEL12_EV_M 0x0000007F -#define EVENT_CPUIRQSEL12_EV_S 0 -#define EVENT_CPUIRQSEL12_EV_I2S_IRQ 0x00000008 +#define EVENT_CPUIRQSEL12_EV_W 7 +#define EVENT_CPUIRQSEL12_EV_M 0x0000007F +#define EVENT_CPUIRQSEL12_EV_S 0 +#define EVENT_CPUIRQSEL12_EV_I2S_IRQ 0x00000008 //***************************************************************************** // @@ -554,10 +554,10 @@ // AON_EVENT:MCUWUSEL // AUX domain wakeup control // AON_EVENT:AUXWUSEL -#define EVENT_CPUIRQSEL13_EV_W 7 -#define EVENT_CPUIRQSEL13_EV_M 0x0000007F -#define EVENT_CPUIRQSEL13_EV_S 0 -#define EVENT_CPUIRQSEL13_EV_AUX_SWEV1 0x0000001D +#define EVENT_CPUIRQSEL13_EV_W 7 +#define EVENT_CPUIRQSEL13_EV_M 0x0000007F +#define EVENT_CPUIRQSEL13_EV_S 0 +#define EVENT_CPUIRQSEL13_EV_AUX_SWEV1 0x0000001D //***************************************************************************** // @@ -570,10 +570,10 @@ // ENUMs: // WDT_IRQ Watchdog interrupt event, controlled by // WDT:CTL.INTEN -#define EVENT_CPUIRQSEL14_EV_W 7 -#define EVENT_CPUIRQSEL14_EV_M 0x0000007F -#define EVENT_CPUIRQSEL14_EV_S 0 -#define EVENT_CPUIRQSEL14_EV_WDT_IRQ 0x00000018 +#define EVENT_CPUIRQSEL14_EV_W 7 +#define EVENT_CPUIRQSEL14_EV_M 0x0000007F +#define EVENT_CPUIRQSEL14_EV_S 0 +#define EVENT_CPUIRQSEL14_EV_WDT_IRQ 0x00000018 //***************************************************************************** // @@ -585,10 +585,10 @@ // Read only selection value // ENUMs: // GPT0A GPT0A interrupt event, controlled by GPT0:TAMR -#define EVENT_CPUIRQSEL15_EV_W 7 -#define EVENT_CPUIRQSEL15_EV_M 0x0000007F -#define EVENT_CPUIRQSEL15_EV_S 0 -#define EVENT_CPUIRQSEL15_EV_GPT0A 0x00000010 +#define EVENT_CPUIRQSEL15_EV_W 7 +#define EVENT_CPUIRQSEL15_EV_M 0x0000007F +#define EVENT_CPUIRQSEL15_EV_S 0 +#define EVENT_CPUIRQSEL15_EV_GPT0A 0x00000010 //***************************************************************************** // @@ -600,10 +600,10 @@ // Read only selection value // ENUMs: // GPT0B GPT0B interrupt event, controlled by GPT0:TBMR -#define EVENT_CPUIRQSEL16_EV_W 7 -#define EVENT_CPUIRQSEL16_EV_M 0x0000007F -#define EVENT_CPUIRQSEL16_EV_S 0 -#define EVENT_CPUIRQSEL16_EV_GPT0B 0x00000011 +#define EVENT_CPUIRQSEL16_EV_W 7 +#define EVENT_CPUIRQSEL16_EV_M 0x0000007F +#define EVENT_CPUIRQSEL16_EV_S 0 +#define EVENT_CPUIRQSEL16_EV_GPT0B 0x00000011 //***************************************************************************** // @@ -615,10 +615,10 @@ // Read only selection value // ENUMs: // GPT1A GPT1A interrupt event, controlled by GPT1:TAMR -#define EVENT_CPUIRQSEL17_EV_W 7 -#define EVENT_CPUIRQSEL17_EV_M 0x0000007F -#define EVENT_CPUIRQSEL17_EV_S 0 -#define EVENT_CPUIRQSEL17_EV_GPT1A 0x00000012 +#define EVENT_CPUIRQSEL17_EV_W 7 +#define EVENT_CPUIRQSEL17_EV_M 0x0000007F +#define EVENT_CPUIRQSEL17_EV_S 0 +#define EVENT_CPUIRQSEL17_EV_GPT1A 0x00000012 //***************************************************************************** // @@ -630,10 +630,10 @@ // Read only selection value // ENUMs: // GPT1B GPT1B interrupt event, controlled by GPT1:TBMR -#define EVENT_CPUIRQSEL18_EV_W 7 -#define EVENT_CPUIRQSEL18_EV_M 0x0000007F -#define EVENT_CPUIRQSEL18_EV_S 0 -#define EVENT_CPUIRQSEL18_EV_GPT1B 0x00000013 +#define EVENT_CPUIRQSEL18_EV_W 7 +#define EVENT_CPUIRQSEL18_EV_M 0x0000007F +#define EVENT_CPUIRQSEL18_EV_S 0 +#define EVENT_CPUIRQSEL18_EV_GPT1B 0x00000013 //***************************************************************************** // @@ -645,10 +645,10 @@ // Read only selection value // ENUMs: // GPT2A GPT2A interrupt event, controlled by GPT2:TAMR -#define EVENT_CPUIRQSEL19_EV_W 7 -#define EVENT_CPUIRQSEL19_EV_M 0x0000007F -#define EVENT_CPUIRQSEL19_EV_S 0 -#define EVENT_CPUIRQSEL19_EV_GPT2A 0x0000000C +#define EVENT_CPUIRQSEL19_EV_W 7 +#define EVENT_CPUIRQSEL19_EV_M 0x0000007F +#define EVENT_CPUIRQSEL19_EV_S 0 +#define EVENT_CPUIRQSEL19_EV_GPT2A 0x0000000C //***************************************************************************** // @@ -660,10 +660,10 @@ // Read only selection value // ENUMs: // GPT2B GPT2B interrupt event, controlled by GPT2:TBMR -#define EVENT_CPUIRQSEL20_EV_W 7 -#define EVENT_CPUIRQSEL20_EV_M 0x0000007F -#define EVENT_CPUIRQSEL20_EV_S 0 -#define EVENT_CPUIRQSEL20_EV_GPT2B 0x0000000D +#define EVENT_CPUIRQSEL20_EV_W 7 +#define EVENT_CPUIRQSEL20_EV_M 0x0000007F +#define EVENT_CPUIRQSEL20_EV_S 0 +#define EVENT_CPUIRQSEL20_EV_GPT2B 0x0000000D //***************************************************************************** // @@ -675,10 +675,10 @@ // Read only selection value // ENUMs: // GPT3A GPT3A interrupt event, controlled by GPT3:TAMR -#define EVENT_CPUIRQSEL21_EV_W 7 -#define EVENT_CPUIRQSEL21_EV_M 0x0000007F -#define EVENT_CPUIRQSEL21_EV_S 0 -#define EVENT_CPUIRQSEL21_EV_GPT3A 0x0000000E +#define EVENT_CPUIRQSEL21_EV_W 7 +#define EVENT_CPUIRQSEL21_EV_M 0x0000007F +#define EVENT_CPUIRQSEL21_EV_S 0 +#define EVENT_CPUIRQSEL21_EV_GPT3A 0x0000000E //***************************************************************************** // @@ -690,10 +690,10 @@ // Read only selection value // ENUMs: // GPT3B GPT3B interrupt event, controlled by GPT3:TBMR -#define EVENT_CPUIRQSEL22_EV_W 7 -#define EVENT_CPUIRQSEL22_EV_M 0x0000007F -#define EVENT_CPUIRQSEL22_EV_S 0 -#define EVENT_CPUIRQSEL22_EV_GPT3B 0x0000000F +#define EVENT_CPUIRQSEL22_EV_W 7 +#define EVENT_CPUIRQSEL22_EV_M 0x0000007F +#define EVENT_CPUIRQSEL22_EV_S 0 +#define EVENT_CPUIRQSEL22_EV_GPT3B 0x0000000F //***************************************************************************** // @@ -708,10 +708,10 @@ // corresponding flag is found here // CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by // CRYPTO:IRQSTAT.RESULT_AVAIL -#define EVENT_CPUIRQSEL23_EV_W 7 -#define EVENT_CPUIRQSEL23_EV_M 0x0000007F -#define EVENT_CPUIRQSEL23_EV_S 0 -#define EVENT_CPUIRQSEL23_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D +#define EVENT_CPUIRQSEL23_EV_W 7 +#define EVENT_CPUIRQSEL23_EV_M 0x0000007F +#define EVENT_CPUIRQSEL23_EV_S 0 +#define EVENT_CPUIRQSEL23_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D //***************************************************************************** // @@ -724,10 +724,10 @@ // ENUMs: // DMA_DONE_COMB Combined DMA done, corresponding flags are here // UDMA0:REQDONE -#define EVENT_CPUIRQSEL24_EV_W 7 -#define EVENT_CPUIRQSEL24_EV_M 0x0000007F -#define EVENT_CPUIRQSEL24_EV_S 0 -#define EVENT_CPUIRQSEL24_EV_DMA_DONE_COMB 0x00000027 +#define EVENT_CPUIRQSEL24_EV_W 7 +#define EVENT_CPUIRQSEL24_EV_M 0x0000007F +#define EVENT_CPUIRQSEL24_EV_S 0 +#define EVENT_CPUIRQSEL24_EV_DMA_DONE_COMB 0x00000027 //***************************************************************************** // @@ -739,10 +739,10 @@ // Read only selection value // ENUMs: // DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS -#define EVENT_CPUIRQSEL25_EV_W 7 -#define EVENT_CPUIRQSEL25_EV_M 0x0000007F -#define EVENT_CPUIRQSEL25_EV_S 0 -#define EVENT_CPUIRQSEL25_EV_DMA_ERR 0x00000026 +#define EVENT_CPUIRQSEL25_EV_W 7 +#define EVENT_CPUIRQSEL25_EV_M 0x0000007F +#define EVENT_CPUIRQSEL25_EV_S 0 +#define EVENT_CPUIRQSEL25_EV_DMA_ERR 0x00000026 //***************************************************************************** // @@ -756,10 +756,10 @@ // FLASH FLASH controller error event, the status flags // are FLASH:FEDACSTAT.FSM_DONE and // FLASH:FEDACSTAT.RVF_INT -#define EVENT_CPUIRQSEL26_EV_W 7 -#define EVENT_CPUIRQSEL26_EV_M 0x0000007F -#define EVENT_CPUIRQSEL26_EV_S 0 -#define EVENT_CPUIRQSEL26_EV_FLASH 0x00000015 +#define EVENT_CPUIRQSEL26_EV_W 7 +#define EVENT_CPUIRQSEL26_EV_M 0x0000007F +#define EVENT_CPUIRQSEL26_EV_S 0 +#define EVENT_CPUIRQSEL26_EV_FLASH 0x00000015 //***************************************************************************** // @@ -771,10 +771,10 @@ // Read only selection value // ENUMs: // SWEV0 Software event 0, triggered by SWEV.SWEV0 -#define EVENT_CPUIRQSEL27_EV_W 7 -#define EVENT_CPUIRQSEL27_EV_M 0x0000007F -#define EVENT_CPUIRQSEL27_EV_S 0 -#define EVENT_CPUIRQSEL27_EV_SWEV0 0x00000064 +#define EVENT_CPUIRQSEL27_EV_W 7 +#define EVENT_CPUIRQSEL27_EV_M 0x0000007F +#define EVENT_CPUIRQSEL27_EV_S 0 +#define EVENT_CPUIRQSEL27_EV_SWEV0 0x00000064 //***************************************************************************** // @@ -787,10 +787,10 @@ // ENUMs: // AUX_COMB AUX combined event, the corresponding flag // register is here AUX_EVCTL:EVTOMCUFLAGS -#define EVENT_CPUIRQSEL28_EV_W 7 -#define EVENT_CPUIRQSEL28_EV_M 0x0000007F -#define EVENT_CPUIRQSEL28_EV_S 0 -#define EVENT_CPUIRQSEL28_EV_AUX_COMB 0x0000000B +#define EVENT_CPUIRQSEL28_EV_W 7 +#define EVENT_CPUIRQSEL28_EV_M 0x0000007F +#define EVENT_CPUIRQSEL28_EV_S 0 +#define EVENT_CPUIRQSEL28_EV_AUX_COMB 0x0000000B //***************************************************************************** // @@ -804,10 +804,10 @@ // AON_PROG0 AON programmable event 0. Event selected by // AON_EVENT MCU event selector, // AON_EVENT:EVTOMCUSEL.AON_PROG0_EV -#define EVENT_CPUIRQSEL29_EV_W 7 -#define EVENT_CPUIRQSEL29_EV_M 0x0000007F -#define EVENT_CPUIRQSEL29_EV_S 0 -#define EVENT_CPUIRQSEL29_EV_AON_PROG0 0x00000001 +#define EVENT_CPUIRQSEL29_EV_W 7 +#define EVENT_CPUIRQSEL29_EV_M 0x0000007F +#define EVENT_CPUIRQSEL29_EV_S 0 +#define EVENT_CPUIRQSEL29_EV_AON_PROG0 0x00000001 //***************************************************************************** // @@ -859,28 +859,28 @@ // AON_EVENT MCU event selector, // AON_EVENT:EVTOMCUSEL.AON_PROG1_EV // NONE Always inactive -#define EVENT_CPUIRQSEL30_EV_W 7 -#define EVENT_CPUIRQSEL30_EV_M 0x0000007F -#define EVENT_CPUIRQSEL30_EV_S 0 -#define EVENT_CPUIRQSEL30_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_CPUIRQSEL30_EV_AON_RTC_UPD 0x00000077 -#define EVENT_CPUIRQSEL30_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_CPUIRQSEL30_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_CPUIRQSEL30_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_CPUIRQSEL30_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_CPUIRQSEL30_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_CPUIRQSEL30_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_CPUIRQSEL30_EV_AUX_COMPB 0x0000006B -#define EVENT_CPUIRQSEL30_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_CPUIRQSEL30_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E -#define EVENT_CPUIRQSEL30_EV_DMA_CH18_DONE 0x00000016 -#define EVENT_CPUIRQSEL30_EV_DMA_CH0_DONE 0x00000014 -#define EVENT_CPUIRQSEL30_EV_AON_AUX_SWEV0 0x0000000A -#define EVENT_CPUIRQSEL30_EV_I2S_IRQ 0x00000008 -#define EVENT_CPUIRQSEL30_EV_AON_PROG2 0x00000003 -#define EVENT_CPUIRQSEL30_EV_AON_PROG1 0x00000002 -#define EVENT_CPUIRQSEL30_EV_NONE 0x00000000 +#define EVENT_CPUIRQSEL30_EV_W 7 +#define EVENT_CPUIRQSEL30_EV_M 0x0000007F +#define EVENT_CPUIRQSEL30_EV_S 0 +#define EVENT_CPUIRQSEL30_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_CPUIRQSEL30_EV_AON_RTC_UPD 0x00000077 +#define EVENT_CPUIRQSEL30_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_CPUIRQSEL30_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_CPUIRQSEL30_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_CPUIRQSEL30_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_CPUIRQSEL30_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_CPUIRQSEL30_EV_AUX_COMPB 0x0000006B +#define EVENT_CPUIRQSEL30_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_CPUIRQSEL30_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E +#define EVENT_CPUIRQSEL30_EV_DMA_CH18_DONE 0x00000016 +#define EVENT_CPUIRQSEL30_EV_DMA_CH0_DONE 0x00000014 +#define EVENT_CPUIRQSEL30_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_CPUIRQSEL30_EV_I2S_IRQ 0x00000008 +#define EVENT_CPUIRQSEL30_EV_AON_PROG2 0x00000003 +#define EVENT_CPUIRQSEL30_EV_AON_PROG1 0x00000002 +#define EVENT_CPUIRQSEL30_EV_NONE 0x00000000 //***************************************************************************** // @@ -893,10 +893,10 @@ // ENUMs: // AUX_COMPA AUX Compare A event, corresponds to // AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -#define EVENT_CPUIRQSEL31_EV_W 7 -#define EVENT_CPUIRQSEL31_EV_M 0x0000007F -#define EVENT_CPUIRQSEL31_EV_S 0 -#define EVENT_CPUIRQSEL31_EV_AUX_COMPA 0x0000006A +#define EVENT_CPUIRQSEL31_EV_W 7 +#define EVENT_CPUIRQSEL31_EV_M 0x0000007F +#define EVENT_CPUIRQSEL31_EV_S 0 +#define EVENT_CPUIRQSEL31_EV_AUX_COMPA 0x0000006A //***************************************************************************** // @@ -910,10 +910,10 @@ // AUX_ADC_IRQ AUX ADC interrupt event, corresponds to // AUX_EVCTL:EVTOMCUFLAGS.ADC_IRQ. Status flags // are found here AUX_EVCTL:EVTOMCUFLAGS -#define EVENT_CPUIRQSEL32_EV_W 7 -#define EVENT_CPUIRQSEL32_EV_M 0x0000007F -#define EVENT_CPUIRQSEL32_EV_S 0 -#define EVENT_CPUIRQSEL32_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_CPUIRQSEL32_EV_W 7 +#define EVENT_CPUIRQSEL32_EV_M 0x0000007F +#define EVENT_CPUIRQSEL32_EV_S 0 +#define EVENT_CPUIRQSEL32_EV_AUX_ADC_IRQ 0x00000073 //***************************************************************************** // @@ -925,10 +925,10 @@ // Read only selection value // ENUMs: // TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN -#define EVENT_CPUIRQSEL33_EV_W 7 -#define EVENT_CPUIRQSEL33_EV_M 0x0000007F -#define EVENT_CPUIRQSEL33_EV_S 0 -#define EVENT_CPUIRQSEL33_EV_TRNG_IRQ 0x00000068 +#define EVENT_CPUIRQSEL33_EV_W 7 +#define EVENT_CPUIRQSEL33_EV_M 0x0000007F +#define EVENT_CPUIRQSEL33_EV_S 0 +#define EVENT_CPUIRQSEL33_EV_TRNG_IRQ 0x00000068 //***************************************************************************** // @@ -940,10 +940,10 @@ // Read only selection value // ENUMs: // GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -#define EVENT_RFCSEL0_EV_W 7 -#define EVENT_RFCSEL0_EV_M 0x0000007F -#define EVENT_RFCSEL0_EV_S 0 -#define EVENT_RFCSEL0_EV_GPT0A_CMP 0x0000003D +#define EVENT_RFCSEL0_EV_W 7 +#define EVENT_RFCSEL0_EV_M 0x0000007F +#define EVENT_RFCSEL0_EV_S 0 +#define EVENT_RFCSEL0_EV_GPT0A_CMP 0x0000003D //***************************************************************************** // @@ -955,10 +955,10 @@ // Read only selection value // ENUMs: // GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -#define EVENT_RFCSEL1_EV_W 7 -#define EVENT_RFCSEL1_EV_M 0x0000007F -#define EVENT_RFCSEL1_EV_S 0 -#define EVENT_RFCSEL1_EV_GPT0B_CMP 0x0000003E +#define EVENT_RFCSEL1_EV_W 7 +#define EVENT_RFCSEL1_EV_M 0x0000007F +#define EVENT_RFCSEL1_EV_S 0 +#define EVENT_RFCSEL1_EV_GPT0B_CMP 0x0000003E //***************************************************************************** // @@ -970,10 +970,10 @@ // Read only selection value // ENUMs: // GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -#define EVENT_RFCSEL2_EV_W 7 -#define EVENT_RFCSEL2_EV_M 0x0000007F -#define EVENT_RFCSEL2_EV_S 0 -#define EVENT_RFCSEL2_EV_GPT1A_CMP 0x0000003F +#define EVENT_RFCSEL2_EV_W 7 +#define EVENT_RFCSEL2_EV_M 0x0000007F +#define EVENT_RFCSEL2_EV_S 0 +#define EVENT_RFCSEL2_EV_GPT1A_CMP 0x0000003F //***************************************************************************** // @@ -985,10 +985,10 @@ // Read only selection value // ENUMs: // GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -#define EVENT_RFCSEL3_EV_W 7 -#define EVENT_RFCSEL3_EV_M 0x0000007F -#define EVENT_RFCSEL3_EV_S 0 -#define EVENT_RFCSEL3_EV_GPT1B_CMP 0x00000040 +#define EVENT_RFCSEL3_EV_W 7 +#define EVENT_RFCSEL3_EV_M 0x0000007F +#define EVENT_RFCSEL3_EV_S 0 +#define EVENT_RFCSEL3_EV_GPT1B_CMP 0x00000040 //***************************************************************************** // @@ -1000,10 +1000,10 @@ // Read only selection value // ENUMs: // GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -#define EVENT_RFCSEL4_EV_W 7 -#define EVENT_RFCSEL4_EV_M 0x0000007F -#define EVENT_RFCSEL4_EV_S 0 -#define EVENT_RFCSEL4_EV_GPT2A_CMP 0x00000041 +#define EVENT_RFCSEL4_EV_W 7 +#define EVENT_RFCSEL4_EV_M 0x0000007F +#define EVENT_RFCSEL4_EV_S 0 +#define EVENT_RFCSEL4_EV_GPT2A_CMP 0x00000041 //***************************************************************************** // @@ -1015,10 +1015,10 @@ // Read only selection value // ENUMs: // GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -#define EVENT_RFCSEL5_EV_W 7 -#define EVENT_RFCSEL5_EV_M 0x0000007F -#define EVENT_RFCSEL5_EV_S 0 -#define EVENT_RFCSEL5_EV_GPT2B_CMP 0x00000042 +#define EVENT_RFCSEL5_EV_W 7 +#define EVENT_RFCSEL5_EV_M 0x0000007F +#define EVENT_RFCSEL5_EV_S 0 +#define EVENT_RFCSEL5_EV_GPT2B_CMP 0x00000042 //***************************************************************************** // @@ -1030,10 +1030,10 @@ // Read only selection value // ENUMs: // GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -#define EVENT_RFCSEL6_EV_W 7 -#define EVENT_RFCSEL6_EV_M 0x0000007F -#define EVENT_RFCSEL6_EV_S 0 -#define EVENT_RFCSEL6_EV_GPT3A_CMP 0x00000043 +#define EVENT_RFCSEL6_EV_W 7 +#define EVENT_RFCSEL6_EV_M 0x0000007F +#define EVENT_RFCSEL6_EV_S 0 +#define EVENT_RFCSEL6_EV_GPT3A_CMP 0x00000043 //***************************************************************************** // @@ -1045,10 +1045,10 @@ // Read only selection value // ENUMs: // GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -#define EVENT_RFCSEL7_EV_W 7 -#define EVENT_RFCSEL7_EV_M 0x0000007F -#define EVENT_RFCSEL7_EV_S 0 -#define EVENT_RFCSEL7_EV_GPT3B_CMP 0x00000044 +#define EVENT_RFCSEL7_EV_W 7 +#define EVENT_RFCSEL7_EV_M 0x0000007F +#define EVENT_RFCSEL7_EV_S 0 +#define EVENT_RFCSEL7_EV_GPT3B_CMP 0x00000044 //***************************************************************************** // @@ -1061,10 +1061,10 @@ // ENUMs: // AON_RTC_UPD RTC periodic event controlled by // AON_RTC:CTL.RTC_UPD_EN -#define EVENT_RFCSEL8_EV_W 7 -#define EVENT_RFCSEL8_EV_M 0x0000007F -#define EVENT_RFCSEL8_EV_S 0 -#define EVENT_RFCSEL8_EV_AON_RTC_UPD 0x00000077 +#define EVENT_RFCSEL8_EV_W 7 +#define EVENT_RFCSEL8_EV_M 0x0000007F +#define EVENT_RFCSEL8_EV_S 0 +#define EVENT_RFCSEL8_EV_AON_RTC_UPD 0x00000077 //***************************************************************************** // @@ -1128,34 +1128,34 @@ // AON_EVENT MCU event selector, // AON_EVENT:EVTOMCUSEL.AON_PROG0_EV // NONE Always inactive -#define EVENT_RFCSEL9_EV_W 7 -#define EVENT_RFCSEL9_EV_M 0x0000007F -#define EVENT_RFCSEL9_EV_S 0 -#define EVENT_RFCSEL9_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_RFCSEL9_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_RFCSEL9_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_RFCSEL9_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_RFCSEL9_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_RFCSEL9_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_RFCSEL9_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_RFCSEL9_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_RFCSEL9_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_RFCSEL9_EV_AUX_COMPB 0x0000006B -#define EVENT_RFCSEL9_EV_AUX_COMPA 0x0000006A -#define EVENT_RFCSEL9_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_RFCSEL9_EV_SWEV1 0x00000065 -#define EVENT_RFCSEL9_EV_SWEV0 0x00000064 -#define EVENT_RFCSEL9_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D -#define EVENT_RFCSEL9_EV_DMA_DONE_COMB 0x00000027 -#define EVENT_RFCSEL9_EV_UART0_COMB 0x00000024 -#define EVENT_RFCSEL9_EV_SSI1_COMB 0x00000023 -#define EVENT_RFCSEL9_EV_SSI0_COMB 0x00000022 -#define EVENT_RFCSEL9_EV_WDT_IRQ 0x00000018 -#define EVENT_RFCSEL9_EV_AON_AUX_SWEV0 0x0000000A -#define EVENT_RFCSEL9_EV_I2S_IRQ 0x00000008 -#define EVENT_RFCSEL9_EV_AON_PROG1 0x00000002 -#define EVENT_RFCSEL9_EV_AON_PROG0 0x00000001 -#define EVENT_RFCSEL9_EV_NONE 0x00000000 +#define EVENT_RFCSEL9_EV_W 7 +#define EVENT_RFCSEL9_EV_M 0x0000007F +#define EVENT_RFCSEL9_EV_S 0 +#define EVENT_RFCSEL9_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_RFCSEL9_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_RFCSEL9_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_RFCSEL9_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_RFCSEL9_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_RFCSEL9_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_RFCSEL9_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_RFCSEL9_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_RFCSEL9_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_RFCSEL9_EV_AUX_COMPB 0x0000006B +#define EVENT_RFCSEL9_EV_AUX_COMPA 0x0000006A +#define EVENT_RFCSEL9_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_RFCSEL9_EV_SWEV1 0x00000065 +#define EVENT_RFCSEL9_EV_SWEV0 0x00000064 +#define EVENT_RFCSEL9_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D +#define EVENT_RFCSEL9_EV_DMA_DONE_COMB 0x00000027 +#define EVENT_RFCSEL9_EV_UART0_COMB 0x00000024 +#define EVENT_RFCSEL9_EV_SSI1_COMB 0x00000023 +#define EVENT_RFCSEL9_EV_SSI0_COMB 0x00000022 +#define EVENT_RFCSEL9_EV_WDT_IRQ 0x00000018 +#define EVENT_RFCSEL9_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_RFCSEL9_EV_I2S_IRQ 0x00000008 +#define EVENT_RFCSEL9_EV_AON_PROG1 0x00000002 +#define EVENT_RFCSEL9_EV_AON_PROG0 0x00000001 +#define EVENT_RFCSEL9_EV_NONE 0x00000000 //***************************************************************************** // @@ -1242,45 +1242,45 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT0ACAPTSEL_EV_W 7 -#define EVENT_GPT0ACAPTSEL_EV_M 0x0000007F -#define EVENT_GPT0ACAPTSEL_EV_S 0 -#define EVENT_GPT0ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT0ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT0ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT0ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT0ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT1 0x00000056 -#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT0 0x00000055 -#define EVENT_GPT0ACAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT0ACAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT0ACAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT0ACAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT0ACAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT0ACAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT0ACAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT0ACAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT0ACAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT0ACAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT0ACAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT0ACAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT0ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT0ACAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT0ACAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT0ACAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT0ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT0ACAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT0ACAPTSEL_EV_W 7 +#define EVENT_GPT0ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT0ACAPTSEL_EV_S 0 +#define EVENT_GPT0ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT0ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT0ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT0ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT0ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_GPT0ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT0ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT0ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT0ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT0ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT0ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT0ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT0ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT0ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT0ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT0ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT0ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT0ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT0ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT0ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT0ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT0ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT0ACAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -1367,45 +1367,45 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT0BCAPTSEL_EV_W 7 -#define EVENT_GPT0BCAPTSEL_EV_M 0x0000007F -#define EVENT_GPT0BCAPTSEL_EV_S 0 -#define EVENT_GPT0BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT0BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT0BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT0BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT0BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT1 0x00000056 -#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT0 0x00000055 -#define EVENT_GPT0BCAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT0BCAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT0BCAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT0BCAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT0BCAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT0BCAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT0BCAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT0BCAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT0BCAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT0BCAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT0BCAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT0BCAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT0BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT0BCAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT0BCAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT0BCAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT0BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT0BCAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT0BCAPTSEL_EV_W 7 +#define EVENT_GPT0BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT0BCAPTSEL_EV_S 0 +#define EVENT_GPT0BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT0BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT0BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT0BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT0BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_GPT0BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT0BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT0BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT0BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT0BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT0BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT0BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT0BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT0BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT0BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT0BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT0BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT0BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT0BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT0BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT0BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT0BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT0BCAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -1492,45 +1492,45 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT1ACAPTSEL_EV_W 7 -#define EVENT_GPT1ACAPTSEL_EV_M 0x0000007F -#define EVENT_GPT1ACAPTSEL_EV_S 0 -#define EVENT_GPT1ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT1ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT1ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT1ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT1ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT3 0x00000058 -#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT2 0x00000057 -#define EVENT_GPT1ACAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT1ACAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT1ACAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT1ACAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT1ACAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT1ACAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT1ACAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT1ACAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT1ACAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT1ACAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT1ACAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT1ACAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT1ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT1ACAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT1ACAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT1ACAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT1ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT1ACAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT1ACAPTSEL_EV_W 7 +#define EVENT_GPT1ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT1ACAPTSEL_EV_S 0 +#define EVENT_GPT1ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT1ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT1ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT1ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT1ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_GPT1ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT1ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT1ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT1ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT1ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT1ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT1ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT1ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT1ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT1ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT1ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT1ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT1ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT1ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT1ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT1ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT1ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT1ACAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -1617,45 +1617,45 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT1BCAPTSEL_EV_W 7 -#define EVENT_GPT1BCAPTSEL_EV_M 0x0000007F -#define EVENT_GPT1BCAPTSEL_EV_S 0 -#define EVENT_GPT1BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT1BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT1BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT1BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT1BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT3 0x00000058 -#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT2 0x00000057 -#define EVENT_GPT1BCAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT1BCAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT1BCAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT1BCAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT1BCAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT1BCAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT1BCAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT1BCAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT1BCAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT1BCAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT1BCAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT1BCAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT1BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT1BCAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT1BCAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT1BCAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT1BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT1BCAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT1BCAPTSEL_EV_W 7 +#define EVENT_GPT1BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT1BCAPTSEL_EV_S 0 +#define EVENT_GPT1BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT1BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT1BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT1BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT1BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_GPT1BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT1BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT1BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT1BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT1BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT1BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT1BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT1BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT1BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT1BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT1BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT1BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT1BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT1BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT1BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT1BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT1BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT1BCAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -1742,45 +1742,45 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT2ACAPTSEL_EV_W 7 -#define EVENT_GPT2ACAPTSEL_EV_M 0x0000007F -#define EVENT_GPT2ACAPTSEL_EV_S 0 -#define EVENT_GPT2ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT2ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT2ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT2ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT2ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT5 0x0000005A -#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT4 0x00000059 -#define EVENT_GPT2ACAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT2ACAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT2ACAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT2ACAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT2ACAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT2ACAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT2ACAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT2ACAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT2ACAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT2ACAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT2ACAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT2ACAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT2ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT2ACAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT2ACAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT2ACAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT2ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT2ACAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT2ACAPTSEL_EV_W 7 +#define EVENT_GPT2ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT2ACAPTSEL_EV_S 0 +#define EVENT_GPT2ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT2ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT2ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT2ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT2ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_GPT2ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT2ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT2ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT2ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT2ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT2ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT2ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT2ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT2ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT2ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT2ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT2ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT2ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT2ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT2ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT2ACAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT2ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT2ACAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -1867,45 +1867,45 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT2BCAPTSEL_EV_W 7 -#define EVENT_GPT2BCAPTSEL_EV_M 0x0000007F -#define EVENT_GPT2BCAPTSEL_EV_S 0 -#define EVENT_GPT2BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT2BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT2BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT2BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT2BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT5 0x0000005A -#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT4 0x00000059 -#define EVENT_GPT2BCAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT2BCAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT2BCAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT2BCAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT2BCAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT2BCAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT2BCAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT2BCAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT2BCAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT2BCAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT2BCAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT2BCAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT2BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT2BCAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT2BCAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT2BCAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT2BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT2BCAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT2BCAPTSEL_EV_W 7 +#define EVENT_GPT2BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT2BCAPTSEL_EV_S 0 +#define EVENT_GPT2BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT2BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT2BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT2BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT2BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_GPT2BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT2BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT2BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT2BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT2BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT2BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT2BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT2BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT2BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT2BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT2BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT2BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT2BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT2BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT2BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT2BCAPTSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT2BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT2BCAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -1918,10 +1918,10 @@ // ENUMs: // UART0_RX_DMASREQ UART0 RX DMA single request, controlled by // UART0:DMACTL.RXDMAE -#define EVENT_UDMACH1SSEL_EV_W 7 -#define EVENT_UDMACH1SSEL_EV_M 0x0000007F -#define EVENT_UDMACH1SSEL_EV_S 0 -#define EVENT_UDMACH1SSEL_EV_UART0_RX_DMASREQ 0x00000031 +#define EVENT_UDMACH1SSEL_EV_W 7 +#define EVENT_UDMACH1SSEL_EV_M 0x0000007F +#define EVENT_UDMACH1SSEL_EV_S 0 +#define EVENT_UDMACH1SSEL_EV_UART0_RX_DMASREQ 0x00000031 //***************************************************************************** // @@ -1934,10 +1934,10 @@ // ENUMs: // UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by // UART0:DMACTL.RXDMAE -#define EVENT_UDMACH1BSEL_EV_W 7 -#define EVENT_UDMACH1BSEL_EV_M 0x0000007F -#define EVENT_UDMACH1BSEL_EV_S 0 -#define EVENT_UDMACH1BSEL_EV_UART0_RX_DMABREQ 0x00000030 +#define EVENT_UDMACH1BSEL_EV_W 7 +#define EVENT_UDMACH1BSEL_EV_M 0x0000007F +#define EVENT_UDMACH1BSEL_EV_S 0 +#define EVENT_UDMACH1BSEL_EV_UART0_RX_DMABREQ 0x00000030 //***************************************************************************** // @@ -1950,10 +1950,10 @@ // ENUMs: // UART0_TX_DMASREQ UART0 TX DMA single request, controlled by // UART0:DMACTL.TXDMAE -#define EVENT_UDMACH2SSEL_EV_W 7 -#define EVENT_UDMACH2SSEL_EV_M 0x0000007F -#define EVENT_UDMACH2SSEL_EV_S 0 -#define EVENT_UDMACH2SSEL_EV_UART0_TX_DMASREQ 0x00000033 +#define EVENT_UDMACH2SSEL_EV_W 7 +#define EVENT_UDMACH2SSEL_EV_M 0x0000007F +#define EVENT_UDMACH2SSEL_EV_S 0 +#define EVENT_UDMACH2SSEL_EV_UART0_TX_DMASREQ 0x00000033 //***************************************************************************** // @@ -1966,10 +1966,10 @@ // ENUMs: // UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by // UART0:DMACTL.TXDMAE -#define EVENT_UDMACH2BSEL_EV_W 7 -#define EVENT_UDMACH2BSEL_EV_M 0x0000007F -#define EVENT_UDMACH2BSEL_EV_S 0 -#define EVENT_UDMACH2BSEL_EV_UART0_TX_DMABREQ 0x00000032 +#define EVENT_UDMACH2BSEL_EV_W 7 +#define EVENT_UDMACH2BSEL_EV_M 0x0000007F +#define EVENT_UDMACH2BSEL_EV_S 0 +#define EVENT_UDMACH2BSEL_EV_UART0_TX_DMABREQ 0x00000032 //***************************************************************************** // @@ -1982,10 +1982,10 @@ // ENUMs: // SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by // SSI0:DMACR.RXDMAE -#define EVENT_UDMACH3SSEL_EV_W 7 -#define EVENT_UDMACH3SSEL_EV_M 0x0000007F -#define EVENT_UDMACH3SSEL_EV_S 0 -#define EVENT_UDMACH3SSEL_EV_SSI0_RX_DMASREQ 0x00000029 +#define EVENT_UDMACH3SSEL_EV_W 7 +#define EVENT_UDMACH3SSEL_EV_M 0x0000007F +#define EVENT_UDMACH3SSEL_EV_S 0 +#define EVENT_UDMACH3SSEL_EV_SSI0_RX_DMASREQ 0x00000029 //***************************************************************************** // @@ -1998,10 +1998,10 @@ // ENUMs: // SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by // SSI0:DMACR.RXDMAE -#define EVENT_UDMACH3BSEL_EV_W 7 -#define EVENT_UDMACH3BSEL_EV_M 0x0000007F -#define EVENT_UDMACH3BSEL_EV_S 0 -#define EVENT_UDMACH3BSEL_EV_SSI0_RX_DMABREQ 0x00000028 +#define EVENT_UDMACH3BSEL_EV_W 7 +#define EVENT_UDMACH3BSEL_EV_M 0x0000007F +#define EVENT_UDMACH3BSEL_EV_S 0 +#define EVENT_UDMACH3BSEL_EV_SSI0_RX_DMABREQ 0x00000028 //***************************************************************************** // @@ -2014,10 +2014,10 @@ // ENUMs: // SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by // SSI0:DMACR.TXDMAE -#define EVENT_UDMACH4SSEL_EV_W 7 -#define EVENT_UDMACH4SSEL_EV_M 0x0000007F -#define EVENT_UDMACH4SSEL_EV_S 0 -#define EVENT_UDMACH4SSEL_EV_SSI0_TX_DMASREQ 0x0000002B +#define EVENT_UDMACH4SSEL_EV_W 7 +#define EVENT_UDMACH4SSEL_EV_M 0x0000007F +#define EVENT_UDMACH4SSEL_EV_S 0 +#define EVENT_UDMACH4SSEL_EV_SSI0_TX_DMASREQ 0x0000002B //***************************************************************************** // @@ -2030,10 +2030,10 @@ // ENUMs: // SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by // SSI0:DMACR.TXDMAE -#define EVENT_UDMACH4BSEL_EV_W 7 -#define EVENT_UDMACH4BSEL_EV_M 0x0000007F -#define EVENT_UDMACH4BSEL_EV_S 0 -#define EVENT_UDMACH4BSEL_EV_SSI0_TX_DMABREQ 0x0000002A +#define EVENT_UDMACH4BSEL_EV_W 7 +#define EVENT_UDMACH4BSEL_EV_M 0x0000007F +#define EVENT_UDMACH4BSEL_EV_S 0 +#define EVENT_UDMACH4BSEL_EV_SSI0_TX_DMABREQ 0x0000002A //***************************************************************************** // @@ -2066,10 +2066,10 @@ // ENUMs: // AUX_DMASREQ DMA single request event from AUX, configured by // AUX_EVCTL:DMACTL -#define EVENT_UDMACH7SSEL_EV_W 7 -#define EVENT_UDMACH7SSEL_EV_M 0x0000007F -#define EVENT_UDMACH7SSEL_EV_S 0 -#define EVENT_UDMACH7SSEL_EV_AUX_DMASREQ 0x00000075 +#define EVENT_UDMACH7SSEL_EV_W 7 +#define EVENT_UDMACH7SSEL_EV_M 0x0000007F +#define EVENT_UDMACH7SSEL_EV_S 0 +#define EVENT_UDMACH7SSEL_EV_AUX_DMASREQ 0x00000075 //***************************************************************************** // @@ -2082,10 +2082,10 @@ // ENUMs: // AUX_DMABREQ DMA burst request event from AUX, configured by // AUX_EVCTL:DMACTL -#define EVENT_UDMACH7BSEL_EV_W 7 -#define EVENT_UDMACH7BSEL_EV_M 0x0000007F -#define EVENT_UDMACH7BSEL_EV_S 0 -#define EVENT_UDMACH7BSEL_EV_AUX_DMABREQ 0x00000076 +#define EVENT_UDMACH7BSEL_EV_W 7 +#define EVENT_UDMACH7BSEL_EV_M 0x0000007F +#define EVENT_UDMACH7BSEL_EV_S 0 +#define EVENT_UDMACH7BSEL_EV_AUX_DMABREQ 0x00000076 //***************************************************************************** // @@ -2098,10 +2098,10 @@ // ENUMs: // AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by // AUX_EVCTL:DMASWREQ.START -#define EVENT_UDMACH8SSEL_EV_W 7 -#define EVENT_UDMACH8SSEL_EV_M 0x0000007F -#define EVENT_UDMACH8SSEL_EV_S 0 -#define EVENT_UDMACH8SSEL_EV_AUX_SW_DMABREQ 0x00000074 +#define EVENT_UDMACH8SSEL_EV_W 7 +#define EVENT_UDMACH8SSEL_EV_M 0x0000007F +#define EVENT_UDMACH8SSEL_EV_S 0 +#define EVENT_UDMACH8SSEL_EV_AUX_SW_DMABREQ 0x00000074 //***************************************************************************** // @@ -2114,10 +2114,10 @@ // ENUMs: // AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by // AUX_EVCTL:DMASWREQ.START -#define EVENT_UDMACH8BSEL_EV_W 7 -#define EVENT_UDMACH8BSEL_EV_M 0x0000007F -#define EVENT_UDMACH8BSEL_EV_S 0 -#define EVENT_UDMACH8BSEL_EV_AUX_SW_DMABREQ 0x00000074 +#define EVENT_UDMACH8BSEL_EV_W 7 +#define EVENT_UDMACH8BSEL_EV_M 0x0000007F +#define EVENT_UDMACH8BSEL_EV_S 0 +#define EVENT_UDMACH8BSEL_EV_AUX_SW_DMABREQ 0x00000074 //***************************************************************************** // @@ -2142,20 +2142,20 @@ // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // TIE_LOW Not used tied to 0 // NONE Always inactive -#define EVENT_UDMACH9SSEL_EV_W 7 -#define EVENT_UDMACH9SSEL_EV_M 0x0000007F -#define EVENT_UDMACH9SSEL_EV_S 0 -#define EVENT_UDMACH9SSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH9SSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH9SSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH9SSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH9SSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH9SSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH9SSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH9SSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH9SSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH9SSEL_EV_TIE_LOW 0x00000045 -#define EVENT_UDMACH9SSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH9SSEL_EV_W 7 +#define EVENT_UDMACH9SSEL_EV_M 0x0000007F +#define EVENT_UDMACH9SSEL_EV_S 0 +#define EVENT_UDMACH9SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH9SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH9SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH9SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH9SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH9SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH9SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH9SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH9SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH9SSEL_EV_TIE_LOW 0x00000045 +#define EVENT_UDMACH9SSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2179,19 +2179,19 @@ // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // NONE Always inactive -#define EVENT_UDMACH9BSEL_EV_W 7 -#define EVENT_UDMACH9BSEL_EV_M 0x0000007F -#define EVENT_UDMACH9BSEL_EV_S 0 -#define EVENT_UDMACH9BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH9BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH9BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH9BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH9BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH9BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH9BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH9BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH9BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH9BSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH9BSEL_EV_W 7 +#define EVENT_UDMACH9BSEL_EV_M 0x0000007F +#define EVENT_UDMACH9BSEL_EV_S 0 +#define EVENT_UDMACH9BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH9BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH9BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH9BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH9BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH9BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH9BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH9BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH9BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH9BSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2216,20 +2216,20 @@ // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // TIE_LOW Not used tied to 0 // NONE Always inactive -#define EVENT_UDMACH10SSEL_EV_W 7 -#define EVENT_UDMACH10SSEL_EV_M 0x0000007F -#define EVENT_UDMACH10SSEL_EV_S 0 -#define EVENT_UDMACH10SSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH10SSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH10SSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH10SSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH10SSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH10SSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH10SSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH10SSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH10SSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH10SSEL_EV_TIE_LOW 0x00000046 -#define EVENT_UDMACH10SSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH10SSEL_EV_W 7 +#define EVENT_UDMACH10SSEL_EV_M 0x0000007F +#define EVENT_UDMACH10SSEL_EV_S 0 +#define EVENT_UDMACH10SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH10SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH10SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH10SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH10SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH10SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH10SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH10SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH10SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH10SSEL_EV_TIE_LOW 0x00000046 +#define EVENT_UDMACH10SSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2253,19 +2253,19 @@ // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // NONE Always inactive -#define EVENT_UDMACH10BSEL_EV_W 7 -#define EVENT_UDMACH10BSEL_EV_M 0x0000007F -#define EVENT_UDMACH10BSEL_EV_S 0 -#define EVENT_UDMACH10BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH10BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH10BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH10BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH10BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH10BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH10BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH10BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH10BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH10BSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH10BSEL_EV_W 7 +#define EVENT_UDMACH10BSEL_EV_M 0x0000007F +#define EVENT_UDMACH10BSEL_EV_S 0 +#define EVENT_UDMACH10BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH10BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH10BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH10BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH10BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH10BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH10BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH10BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH10BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH10BSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2290,20 +2290,20 @@ // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // TIE_LOW Not used tied to 0 // NONE Always inactive -#define EVENT_UDMACH11SSEL_EV_W 7 -#define EVENT_UDMACH11SSEL_EV_M 0x0000007F -#define EVENT_UDMACH11SSEL_EV_S 0 -#define EVENT_UDMACH11SSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH11SSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH11SSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH11SSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH11SSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH11SSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH11SSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH11SSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH11SSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH11SSEL_EV_TIE_LOW 0x00000047 -#define EVENT_UDMACH11SSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH11SSEL_EV_W 7 +#define EVENT_UDMACH11SSEL_EV_M 0x0000007F +#define EVENT_UDMACH11SSEL_EV_S 0 +#define EVENT_UDMACH11SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH11SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH11SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH11SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH11SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH11SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH11SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH11SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH11SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH11SSEL_EV_TIE_LOW 0x00000047 +#define EVENT_UDMACH11SSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2327,19 +2327,19 @@ // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // NONE Always inactive -#define EVENT_UDMACH11BSEL_EV_W 7 -#define EVENT_UDMACH11BSEL_EV_M 0x0000007F -#define EVENT_UDMACH11BSEL_EV_S 0 -#define EVENT_UDMACH11BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH11BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH11BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH11BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH11BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH11BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH11BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH11BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH11BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH11BSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH11BSEL_EV_W 7 +#define EVENT_UDMACH11BSEL_EV_M 0x0000007F +#define EVENT_UDMACH11BSEL_EV_S 0 +#define EVENT_UDMACH11BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH11BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH11BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH11BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH11BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH11BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH11BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH11BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH11BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH11BSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2364,20 +2364,20 @@ // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // TIE_LOW Not used tied to 0 // NONE Always inactive -#define EVENT_UDMACH12SSEL_EV_W 7 -#define EVENT_UDMACH12SSEL_EV_M 0x0000007F -#define EVENT_UDMACH12SSEL_EV_S 0 -#define EVENT_UDMACH12SSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH12SSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH12SSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH12SSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH12SSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH12SSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH12SSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH12SSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH12SSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH12SSEL_EV_TIE_LOW 0x00000048 -#define EVENT_UDMACH12SSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH12SSEL_EV_W 7 +#define EVENT_UDMACH12SSEL_EV_M 0x0000007F +#define EVENT_UDMACH12SSEL_EV_S 0 +#define EVENT_UDMACH12SSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH12SSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH12SSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH12SSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH12SSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH12SSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH12SSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH12SSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH12SSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH12SSEL_EV_TIE_LOW 0x00000048 +#define EVENT_UDMACH12SSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2401,19 +2401,19 @@ // GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV // GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV // NONE Always inactive -#define EVENT_UDMACH12BSEL_EV_W 7 -#define EVENT_UDMACH12BSEL_EV_M 0x0000007F -#define EVENT_UDMACH12BSEL_EV_S 0 -#define EVENT_UDMACH12BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH12BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH12BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH12BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH12BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH12BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH12BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH12BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH12BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH12BSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH12BSEL_EV_W 7 +#define EVENT_UDMACH12BSEL_EV_M 0x0000007F +#define EVENT_UDMACH12BSEL_EV_S 0 +#define EVENT_UDMACH12BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH12BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH12BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH12BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH12BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH12BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH12BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH12BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH12BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH12BSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2427,10 +2427,10 @@ // AON_PROG2 AON programmable event 2. Event selected by // AON_EVENT MCU event selector, // AON_EVENT:EVTOMCUSEL.AON_PROG2_EV -#define EVENT_UDMACH13BSEL_EV_W 7 -#define EVENT_UDMACH13BSEL_EV_M 0x0000007F -#define EVENT_UDMACH13BSEL_EV_S 0 -#define EVENT_UDMACH13BSEL_EV_AON_PROG2 0x00000003 +#define EVENT_UDMACH13BSEL_EV_W 7 +#define EVENT_UDMACH13BSEL_EV_M 0x0000007F +#define EVENT_UDMACH13BSEL_EV_S 0 +#define EVENT_UDMACH13BSEL_EV_AON_PROG2 0x00000003 //***************************************************************************** // @@ -2623,102 +2623,102 @@ // AON_EVENT MCU event selector, // AON_EVENT:EVTOMCUSEL.AON_PROG0_EV // NONE Always inactive -#define EVENT_UDMACH14BSEL_EV_W 7 -#define EVENT_UDMACH14BSEL_EV_M 0x0000007F -#define EVENT_UDMACH14BSEL_EV_S 0 -#define EVENT_UDMACH14BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH14BSEL_EV_CPU_HALTED 0x00000078 -#define EVENT_UDMACH14BSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_UDMACH14BSEL_EV_AUX_DMABREQ 0x00000076 -#define EVENT_UDMACH14BSEL_EV_AUX_DMASREQ 0x00000075 -#define EVENT_UDMACH14BSEL_EV_AUX_SW_DMABREQ 0x00000074 -#define EVENT_UDMACH14BSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_UDMACH14BSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_UDMACH14BSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_UDMACH14BSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_UDMACH14BSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_UDMACH14BSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_UDMACH14BSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_UDMACH14BSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_UDMACH14BSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_UDMACH14BSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_UDMACH14BSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_UDMACH14BSEL_EV_TRNG_IRQ 0x00000068 -#define EVENT_UDMACH14BSEL_EV_SWEV3 0x00000067 -#define EVENT_UDMACH14BSEL_EV_SWEV2 0x00000066 -#define EVENT_UDMACH14BSEL_EV_SWEV1 0x00000065 -#define EVENT_UDMACH14BSEL_EV_SWEV0 0x00000064 -#define EVENT_UDMACH14BSEL_EV_WDT_NMI 0x00000063 -#define EVENT_UDMACH14BSEL_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E -#define EVENT_UDMACH14BSEL_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT7 0x0000005C -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT6 0x0000005B -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT5 0x0000005A -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT4 0x00000059 -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT3 0x00000058 -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT2 0x00000057 -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT1 0x00000056 -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT0 0x00000055 -#define EVENT_UDMACH14BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH14BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH14BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH14BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH14BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH14BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH14BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH14BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH14BSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_UDMACH14BSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_UDMACH14BSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_UDMACH14BSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_UDMACH14BSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_UDMACH14BSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_UDMACH14BSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_UDMACH14BSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMASREQ 0x00000033 -#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMABREQ 0x00000032 -#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMASREQ 0x00000031 -#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMABREQ 0x00000030 -#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMASREQ 0x0000002F -#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMABREQ 0x0000002E -#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMASREQ 0x0000002D -#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMABREQ 0x0000002C -#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMASREQ 0x0000002B -#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMABREQ 0x0000002A -#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMASREQ 0x00000029 -#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMABREQ 0x00000028 -#define EVENT_UDMACH14BSEL_EV_DMA_DONE_COMB 0x00000027 -#define EVENT_UDMACH14BSEL_EV_DMA_ERR 0x00000026 -#define EVENT_UDMACH14BSEL_EV_UART0_COMB 0x00000024 -#define EVENT_UDMACH14BSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_UDMACH14BSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_UDMACH14BSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_UDMACH14BSEL_EV_AUX_SWEV1 0x0000001D -#define EVENT_UDMACH14BSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_UDMACH14BSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_UDMACH14BSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_UDMACH14BSEL_EV_WDT_IRQ 0x00000018 -#define EVENT_UDMACH14BSEL_EV_DMA_CH18_DONE 0x00000016 -#define EVENT_UDMACH14BSEL_EV_FLASH 0x00000015 -#define EVENT_UDMACH14BSEL_EV_DMA_CH0_DONE 0x00000014 -#define EVENT_UDMACH14BSEL_EV_GPT1B 0x00000013 -#define EVENT_UDMACH14BSEL_EV_GPT1A 0x00000012 -#define EVENT_UDMACH14BSEL_EV_GPT0B 0x00000011 -#define EVENT_UDMACH14BSEL_EV_GPT0A 0x00000010 -#define EVENT_UDMACH14BSEL_EV_GPT3B 0x0000000F -#define EVENT_UDMACH14BSEL_EV_GPT3A 0x0000000E -#define EVENT_UDMACH14BSEL_EV_GPT2B 0x0000000D -#define EVENT_UDMACH14BSEL_EV_GPT2A 0x0000000C -#define EVENT_UDMACH14BSEL_EV_AUX_COMB 0x0000000B -#define EVENT_UDMACH14BSEL_EV_AON_AUX_SWEV0 0x0000000A -#define EVENT_UDMACH14BSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_UDMACH14BSEL_EV_I2S_IRQ 0x00000008 -#define EVENT_UDMACH14BSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_UDMACH14BSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_UDMACH14BSEL_EV_AON_PROG2 0x00000003 -#define EVENT_UDMACH14BSEL_EV_AON_PROG1 0x00000002 -#define EVENT_UDMACH14BSEL_EV_AON_PROG0 0x00000001 -#define EVENT_UDMACH14BSEL_EV_NONE 0x00000000 +#define EVENT_UDMACH14BSEL_EV_W 7 +#define EVENT_UDMACH14BSEL_EV_M 0x0000007F +#define EVENT_UDMACH14BSEL_EV_S 0 +#define EVENT_UDMACH14BSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_UDMACH14BSEL_EV_CPU_HALTED 0x00000078 +#define EVENT_UDMACH14BSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_UDMACH14BSEL_EV_AUX_DMABREQ 0x00000076 +#define EVENT_UDMACH14BSEL_EV_AUX_DMASREQ 0x00000075 +#define EVENT_UDMACH14BSEL_EV_AUX_SW_DMABREQ 0x00000074 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_UDMACH14BSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_UDMACH14BSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_UDMACH14BSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_UDMACH14BSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_UDMACH14BSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_UDMACH14BSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_UDMACH14BSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_UDMACH14BSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_UDMACH14BSEL_EV_TRNG_IRQ 0x00000068 +#define EVENT_UDMACH14BSEL_EV_SWEV3 0x00000067 +#define EVENT_UDMACH14BSEL_EV_SWEV2 0x00000066 +#define EVENT_UDMACH14BSEL_EV_SWEV1 0x00000065 +#define EVENT_UDMACH14BSEL_EV_SWEV0 0x00000064 +#define EVENT_UDMACH14BSEL_EV_WDT_NMI 0x00000063 +#define EVENT_UDMACH14BSEL_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E +#define EVENT_UDMACH14BSEL_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT5 0x0000005A +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT4 0x00000059 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT3 0x00000058 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT2 0x00000057 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT1 0x00000056 +#define EVENT_UDMACH14BSEL_EV_PORT_EVENT0 0x00000055 +#define EVENT_UDMACH14BSEL_EV_GPT3B_DMABREQ 0x00000054 +#define EVENT_UDMACH14BSEL_EV_GPT3A_DMABREQ 0x00000053 +#define EVENT_UDMACH14BSEL_EV_GPT2B_DMABREQ 0x00000052 +#define EVENT_UDMACH14BSEL_EV_GPT2A_DMABREQ 0x00000051 +#define EVENT_UDMACH14BSEL_EV_GPT1B_DMABREQ 0x00000050 +#define EVENT_UDMACH14BSEL_EV_GPT1A_DMABREQ 0x0000004F +#define EVENT_UDMACH14BSEL_EV_GPT0B_DMABREQ 0x0000004E +#define EVENT_UDMACH14BSEL_EV_GPT0A_DMABREQ 0x0000004D +#define EVENT_UDMACH14BSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_UDMACH14BSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_UDMACH14BSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_UDMACH14BSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_UDMACH14BSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_UDMACH14BSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_UDMACH14BSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_UDMACH14BSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMASREQ 0x00000033 +#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMABREQ 0x00000032 +#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMASREQ 0x00000031 +#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMABREQ 0x00000030 +#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMASREQ 0x0000002F +#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMABREQ 0x0000002E +#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMASREQ 0x0000002D +#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMABREQ 0x0000002C +#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMASREQ 0x0000002B +#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMABREQ 0x0000002A +#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMASREQ 0x00000029 +#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMABREQ 0x00000028 +#define EVENT_UDMACH14BSEL_EV_DMA_DONE_COMB 0x00000027 +#define EVENT_UDMACH14BSEL_EV_DMA_ERR 0x00000026 +#define EVENT_UDMACH14BSEL_EV_UART0_COMB 0x00000024 +#define EVENT_UDMACH14BSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_UDMACH14BSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_UDMACH14BSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_UDMACH14BSEL_EV_AUX_SWEV1 0x0000001D +#define EVENT_UDMACH14BSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_UDMACH14BSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_UDMACH14BSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_UDMACH14BSEL_EV_WDT_IRQ 0x00000018 +#define EVENT_UDMACH14BSEL_EV_DMA_CH18_DONE 0x00000016 +#define EVENT_UDMACH14BSEL_EV_FLASH 0x00000015 +#define EVENT_UDMACH14BSEL_EV_DMA_CH0_DONE 0x00000014 +#define EVENT_UDMACH14BSEL_EV_GPT1B 0x00000013 +#define EVENT_UDMACH14BSEL_EV_GPT1A 0x00000012 +#define EVENT_UDMACH14BSEL_EV_GPT0B 0x00000011 +#define EVENT_UDMACH14BSEL_EV_GPT0A 0x00000010 +#define EVENT_UDMACH14BSEL_EV_GPT3B 0x0000000F +#define EVENT_UDMACH14BSEL_EV_GPT3A 0x0000000E +#define EVENT_UDMACH14BSEL_EV_GPT2B 0x0000000D +#define EVENT_UDMACH14BSEL_EV_GPT2A 0x0000000C +#define EVENT_UDMACH14BSEL_EV_AUX_COMB 0x0000000B +#define EVENT_UDMACH14BSEL_EV_AON_AUX_SWEV0 0x0000000A +#define EVENT_UDMACH14BSEL_EV_I2C_IRQ 0x00000009 +#define EVENT_UDMACH14BSEL_EV_I2S_IRQ 0x00000008 +#define EVENT_UDMACH14BSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_UDMACH14BSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_UDMACH14BSEL_EV_AON_PROG2 0x00000003 +#define EVENT_UDMACH14BSEL_EV_AON_PROG1 0x00000002 +#define EVENT_UDMACH14BSEL_EV_AON_PROG0 0x00000001 +#define EVENT_UDMACH14BSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -2731,10 +2731,10 @@ // ENUMs: // AON_RTC_COMB Event from AON_RTC, controlled by the // AON_RTC:CTL.COMB_EV_MASK setting -#define EVENT_UDMACH15BSEL_EV_W 7 -#define EVENT_UDMACH15BSEL_EV_M 0x0000007F -#define EVENT_UDMACH15BSEL_EV_S 0 -#define EVENT_UDMACH15BSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_UDMACH15BSEL_EV_W 7 +#define EVENT_UDMACH15BSEL_EV_M 0x0000007F +#define EVENT_UDMACH15BSEL_EV_S 0 +#define EVENT_UDMACH15BSEL_EV_AON_RTC_COMB 0x00000007 //***************************************************************************** // @@ -2747,10 +2747,10 @@ // ENUMs: // SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by // SSI0:DMACR.RXDMAE -#define EVENT_UDMACH16SSEL_EV_W 7 -#define EVENT_UDMACH16SSEL_EV_M 0x0000007F -#define EVENT_UDMACH16SSEL_EV_S 0 -#define EVENT_UDMACH16SSEL_EV_SSI1_RX_DMASREQ 0x0000002D +#define EVENT_UDMACH16SSEL_EV_W 7 +#define EVENT_UDMACH16SSEL_EV_M 0x0000007F +#define EVENT_UDMACH16SSEL_EV_S 0 +#define EVENT_UDMACH16SSEL_EV_SSI1_RX_DMASREQ 0x0000002D //***************************************************************************** // @@ -2763,10 +2763,10 @@ // ENUMs: // SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by // SSI0:DMACR.RXDMAE -#define EVENT_UDMACH16BSEL_EV_W 7 -#define EVENT_UDMACH16BSEL_EV_M 0x0000007F -#define EVENT_UDMACH16BSEL_EV_S 0 -#define EVENT_UDMACH16BSEL_EV_SSI1_RX_DMABREQ 0x0000002C +#define EVENT_UDMACH16BSEL_EV_W 7 +#define EVENT_UDMACH16BSEL_EV_M 0x0000007F +#define EVENT_UDMACH16BSEL_EV_S 0 +#define EVENT_UDMACH16BSEL_EV_SSI1_RX_DMABREQ 0x0000002C //***************************************************************************** // @@ -2779,10 +2779,10 @@ // ENUMs: // SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by // SSI0:DMACR.TXDMAE -#define EVENT_UDMACH17SSEL_EV_W 7 -#define EVENT_UDMACH17SSEL_EV_M 0x0000007F -#define EVENT_UDMACH17SSEL_EV_S 0 -#define EVENT_UDMACH17SSEL_EV_SSI1_TX_DMASREQ 0x0000002F +#define EVENT_UDMACH17SSEL_EV_W 7 +#define EVENT_UDMACH17SSEL_EV_M 0x0000007F +#define EVENT_UDMACH17SSEL_EV_S 0 +#define EVENT_UDMACH17SSEL_EV_SSI1_TX_DMASREQ 0x0000002F //***************************************************************************** // @@ -2795,10 +2795,10 @@ // ENUMs: // SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by // SSI0:DMACR.TXDMAE -#define EVENT_UDMACH17BSEL_EV_W 7 -#define EVENT_UDMACH17BSEL_EV_M 0x0000007F -#define EVENT_UDMACH17BSEL_EV_S 0 -#define EVENT_UDMACH17BSEL_EV_SSI1_TX_DMABREQ 0x0000002E +#define EVENT_UDMACH17BSEL_EV_W 7 +#define EVENT_UDMACH17BSEL_EV_M 0x0000007F +#define EVENT_UDMACH17BSEL_EV_S 0 +#define EVENT_UDMACH17BSEL_EV_SSI1_TX_DMABREQ 0x0000002E //***************************************************************************** // @@ -2810,10 +2810,10 @@ // Read only selection value // ENUMs: // SWEV0 Software event 0, triggered by SWEV.SWEV0 -#define EVENT_UDMACH21SSEL_EV_W 7 -#define EVENT_UDMACH21SSEL_EV_M 0x0000007F -#define EVENT_UDMACH21SSEL_EV_S 0 -#define EVENT_UDMACH21SSEL_EV_SWEV0 0x00000064 +#define EVENT_UDMACH21SSEL_EV_W 7 +#define EVENT_UDMACH21SSEL_EV_M 0x0000007F +#define EVENT_UDMACH21SSEL_EV_S 0 +#define EVENT_UDMACH21SSEL_EV_SWEV0 0x00000064 //***************************************************************************** // @@ -2825,10 +2825,10 @@ // Read only selection value // ENUMs: // SWEV0 Software event 0, triggered by SWEV.SWEV0 -#define EVENT_UDMACH21BSEL_EV_W 7 -#define EVENT_UDMACH21BSEL_EV_M 0x0000007F -#define EVENT_UDMACH21BSEL_EV_S 0 -#define EVENT_UDMACH21BSEL_EV_SWEV0 0x00000064 +#define EVENT_UDMACH21BSEL_EV_W 7 +#define EVENT_UDMACH21BSEL_EV_M 0x0000007F +#define EVENT_UDMACH21BSEL_EV_S 0 +#define EVENT_UDMACH21BSEL_EV_SWEV0 0x00000064 //***************************************************************************** // @@ -2840,10 +2840,10 @@ // Read only selection value // ENUMs: // SWEV1 Software event 1, triggered by SWEV.SWEV1 -#define EVENT_UDMACH22SSEL_EV_W 7 -#define EVENT_UDMACH22SSEL_EV_M 0x0000007F -#define EVENT_UDMACH22SSEL_EV_S 0 -#define EVENT_UDMACH22SSEL_EV_SWEV1 0x00000065 +#define EVENT_UDMACH22SSEL_EV_W 7 +#define EVENT_UDMACH22SSEL_EV_M 0x0000007F +#define EVENT_UDMACH22SSEL_EV_S 0 +#define EVENT_UDMACH22SSEL_EV_SWEV1 0x00000065 //***************************************************************************** // @@ -2855,10 +2855,10 @@ // Read only selection value // ENUMs: // SWEV1 Software event 1, triggered by SWEV.SWEV1 -#define EVENT_UDMACH22BSEL_EV_W 7 -#define EVENT_UDMACH22BSEL_EV_M 0x0000007F -#define EVENT_UDMACH22BSEL_EV_S 0 -#define EVENT_UDMACH22BSEL_EV_SWEV1 0x00000065 +#define EVENT_UDMACH22BSEL_EV_W 7 +#define EVENT_UDMACH22BSEL_EV_M 0x0000007F +#define EVENT_UDMACH22BSEL_EV_S 0 +#define EVENT_UDMACH22BSEL_EV_SWEV1 0x00000065 //***************************************************************************** // @@ -2870,10 +2870,10 @@ // Read only selection value // ENUMs: // SWEV2 Software event 2, triggered by SWEV.SWEV2 -#define EVENT_UDMACH23SSEL_EV_W 7 -#define EVENT_UDMACH23SSEL_EV_M 0x0000007F -#define EVENT_UDMACH23SSEL_EV_S 0 -#define EVENT_UDMACH23SSEL_EV_SWEV2 0x00000066 +#define EVENT_UDMACH23SSEL_EV_W 7 +#define EVENT_UDMACH23SSEL_EV_M 0x0000007F +#define EVENT_UDMACH23SSEL_EV_S 0 +#define EVENT_UDMACH23SSEL_EV_SWEV2 0x00000066 //***************************************************************************** // @@ -2885,10 +2885,10 @@ // Read only selection value // ENUMs: // SWEV2 Software event 2, triggered by SWEV.SWEV2 -#define EVENT_UDMACH23BSEL_EV_W 7 -#define EVENT_UDMACH23BSEL_EV_M 0x0000007F -#define EVENT_UDMACH23BSEL_EV_S 0 -#define EVENT_UDMACH23BSEL_EV_SWEV2 0x00000066 +#define EVENT_UDMACH23BSEL_EV_W 7 +#define EVENT_UDMACH23BSEL_EV_M 0x0000007F +#define EVENT_UDMACH23BSEL_EV_S 0 +#define EVENT_UDMACH23BSEL_EV_SWEV2 0x00000066 //***************************************************************************** // @@ -2900,10 +2900,10 @@ // Read only selection value // ENUMs: // SWEV3 Software event 3, triggered by SWEV.SWEV3 -#define EVENT_UDMACH24SSEL_EV_W 7 -#define EVENT_UDMACH24SSEL_EV_M 0x0000007F -#define EVENT_UDMACH24SSEL_EV_S 0 -#define EVENT_UDMACH24SSEL_EV_SWEV3 0x00000067 +#define EVENT_UDMACH24SSEL_EV_W 7 +#define EVENT_UDMACH24SSEL_EV_M 0x0000007F +#define EVENT_UDMACH24SSEL_EV_S 0 +#define EVENT_UDMACH24SSEL_EV_SWEV3 0x00000067 //***************************************************************************** // @@ -2915,10 +2915,10 @@ // Read only selection value // ENUMs: // SWEV3 Software event 3, triggered by SWEV.SWEV3 -#define EVENT_UDMACH24BSEL_EV_W 7 -#define EVENT_UDMACH24BSEL_EV_M 0x0000007F -#define EVENT_UDMACH24BSEL_EV_S 0 -#define EVENT_UDMACH24BSEL_EV_SWEV3 0x00000067 +#define EVENT_UDMACH24BSEL_EV_W 7 +#define EVENT_UDMACH24BSEL_EV_M 0x0000007F +#define EVENT_UDMACH24BSEL_EV_S 0 +#define EVENT_UDMACH24BSEL_EV_SWEV3 0x00000067 //***************************************************************************** // @@ -3004,44 +3004,44 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT3ACAPTSEL_EV_W 7 -#define EVENT_GPT3ACAPTSEL_EV_M 0x0000007F -#define EVENT_GPT3ACAPTSEL_EV_S 0 -#define EVENT_GPT3ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT3ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT3ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT3ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT3ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT7 0x0000005C -#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT6 0x0000005B -#define EVENT_GPT3ACAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT3ACAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT3ACAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT3ACAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT3ACAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT3ACAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT3ACAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT3ACAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT3ACAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT3ACAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT3ACAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT3ACAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT3ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT3ACAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT3ACAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT3ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT3ACAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT3ACAPTSEL_EV_W 7 +#define EVENT_GPT3ACAPTSEL_EV_M 0x0000007F +#define EVENT_GPT3ACAPTSEL_EV_S 0 +#define EVENT_GPT3ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT3ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT3ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT3ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT3ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_GPT3ACAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT3ACAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT3ACAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT3ACAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT3ACAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT3ACAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT3ACAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT3ACAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT3ACAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT3ACAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT3ACAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT3ACAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT3ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT3ACAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT3ACAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT3ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT3ACAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -3127,44 +3127,44 @@ // IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET // settings // NONE Always inactive -#define EVENT_GPT3BCAPTSEL_EV_W 7 -#define EVENT_GPT3BCAPTSEL_EV_M 0x0000007F -#define EVENT_GPT3BCAPTSEL_EV_S 0 -#define EVENT_GPT3BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT3BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT3BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT3BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT3BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT7 0x0000005C -#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT6 0x0000005B -#define EVENT_GPT3BCAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT3BCAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT3BCAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT3BCAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT3BCAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT3BCAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT3BCAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT3BCAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT3BCAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT3BCAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT3BCAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT3BCAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT3BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT3BCAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT3BCAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT3BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT3BCAPTSEL_EV_NONE 0x00000000 +#define EVENT_GPT3BCAPTSEL_EV_W 7 +#define EVENT_GPT3BCAPTSEL_EV_M 0x0000007F +#define EVENT_GPT3BCAPTSEL_EV_S 0 +#define EVENT_GPT3BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_UPD 0x00000077 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 +#define EVENT_GPT3BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 +#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 +#define EVENT_GPT3BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E +#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D +#define EVENT_GPT3BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPB 0x0000006B +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPA 0x0000006A +#define EVENT_GPT3BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 +#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT7 0x0000005C +#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT6 0x0000005B +#define EVENT_GPT3BCAPTSEL_EV_GPT3B_CMP 0x00000044 +#define EVENT_GPT3BCAPTSEL_EV_GPT3A_CMP 0x00000043 +#define EVENT_GPT3BCAPTSEL_EV_GPT2B_CMP 0x00000042 +#define EVENT_GPT3BCAPTSEL_EV_GPT2A_CMP 0x00000041 +#define EVENT_GPT3BCAPTSEL_EV_GPT1B_CMP 0x00000040 +#define EVENT_GPT3BCAPTSEL_EV_GPT1A_CMP 0x0000003F +#define EVENT_GPT3BCAPTSEL_EV_GPT0B_CMP 0x0000003E +#define EVENT_GPT3BCAPTSEL_EV_GPT0A_CMP 0x0000003D +#define EVENT_GPT3BCAPTSEL_EV_UART0_COMB 0x00000024 +#define EVENT_GPT3BCAPTSEL_EV_SSI1_COMB 0x00000023 +#define EVENT_GPT3BCAPTSEL_EV_SSI0_COMB 0x00000022 +#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_1 0x0000001E +#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_0 0x0000001B +#define EVENT_GPT3BCAPTSEL_EV_RFC_HW_COMB 0x0000001A +#define EVENT_GPT3BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 +#define EVENT_GPT3BCAPTSEL_EV_FLASH 0x00000015 +#define EVENT_GPT3BCAPTSEL_EV_AUX_COMB 0x0000000B +#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_COMB 0x00000007 +#define EVENT_GPT3BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 +#define EVENT_GPT3BCAPTSEL_EV_NONE 0x00000000 //***************************************************************************** // @@ -3188,19 +3188,19 @@ // GPT2B GPT2B interrupt event, controlled by GPT2:TBMR // GPT2A GPT2A interrupt event, controlled by GPT2:TAMR // NONE Always inactive -#define EVENT_AUXSEL0_EV_W 7 -#define EVENT_AUXSEL0_EV_M 0x0000007F -#define EVENT_AUXSEL0_EV_S 0 -#define EVENT_AUXSEL0_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_AUXSEL0_EV_GPT1B 0x00000013 -#define EVENT_AUXSEL0_EV_GPT1A 0x00000012 -#define EVENT_AUXSEL0_EV_GPT0B 0x00000011 -#define EVENT_AUXSEL0_EV_GPT0A 0x00000010 -#define EVENT_AUXSEL0_EV_GPT3B 0x0000000F -#define EVENT_AUXSEL0_EV_GPT3A 0x0000000E -#define EVENT_AUXSEL0_EV_GPT2B 0x0000000D -#define EVENT_AUXSEL0_EV_GPT2A 0x0000000C -#define EVENT_AUXSEL0_EV_NONE 0x00000000 +#define EVENT_AUXSEL0_EV_W 7 +#define EVENT_AUXSEL0_EV_M 0x0000007F +#define EVENT_AUXSEL0_EV_S 0 +#define EVENT_AUXSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_AUXSEL0_EV_GPT1B 0x00000013 +#define EVENT_AUXSEL0_EV_GPT1A 0x00000012 +#define EVENT_AUXSEL0_EV_GPT0B 0x00000011 +#define EVENT_AUXSEL0_EV_GPT0A 0x00000010 +#define EVENT_AUXSEL0_EV_GPT3B 0x0000000F +#define EVENT_AUXSEL0_EV_GPT3A 0x0000000E +#define EVENT_AUXSEL0_EV_GPT2B 0x0000000D +#define EVENT_AUXSEL0_EV_GPT2A 0x0000000C +#define EVENT_AUXSEL0_EV_NONE 0x00000000 //***************************************************************************** // @@ -3213,10 +3213,10 @@ // ENUMs: // WDT_NMI Watchdog non maskable interrupt event, controlled // by WDT:CTL.INTTYPE -#define EVENT_CM3NMISEL0_EV_W 7 -#define EVENT_CM3NMISEL0_EV_M 0x0000007F -#define EVENT_CM3NMISEL0_EV_S 0 -#define EVENT_CM3NMISEL0_EV_WDT_NMI 0x00000063 +#define EVENT_CM3NMISEL0_EV_W 7 +#define EVENT_CM3NMISEL0_EV_M 0x0000007F +#define EVENT_CM3NMISEL0_EV_S 0 +#define EVENT_CM3NMISEL0_EV_WDT_NMI 0x00000063 //***************************************************************************** // @@ -3232,11 +3232,11 @@ // ENUMs: // ALWAYS_ACTIVE Always asserted // NONE Always inactive -#define EVENT_I2SSTMPSEL0_EV_W 7 -#define EVENT_I2SSTMPSEL0_EV_M 0x0000007F -#define EVENT_I2SSTMPSEL0_EV_S 0 -#define EVENT_I2SSTMPSEL0_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_I2SSTMPSEL0_EV_NONE 0x00000000 +#define EVENT_I2SSTMPSEL0_EV_W 7 +#define EVENT_I2SSTMPSEL0_EV_M 0x0000007F +#define EVENT_I2SSTMPSEL0_EV_S 0 +#define EVENT_I2SSTMPSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_I2SSTMPSEL0_EV_NONE 0x00000000 //***************************************************************************** // @@ -3253,12 +3253,12 @@ // ALWAYS_ACTIVE Always asserted // CPU_HALTED CPU halted // NONE Always inactive -#define EVENT_FRZSEL0_EV_W 7 -#define EVENT_FRZSEL0_EV_M 0x0000007F -#define EVENT_FRZSEL0_EV_S 0 -#define EVENT_FRZSEL0_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_FRZSEL0_EV_CPU_HALTED 0x00000078 -#define EVENT_FRZSEL0_EV_NONE 0x00000000 +#define EVENT_FRZSEL0_EV_W 7 +#define EVENT_FRZSEL0_EV_M 0x0000007F +#define EVENT_FRZSEL0_EV_S 0 +#define EVENT_FRZSEL0_EV_ALWAYS_ACTIVE 0x00000079 +#define EVENT_FRZSEL0_EV_CPU_HALTED 0x00000078 +#define EVENT_FRZSEL0_EV_NONE 0x00000000 //***************************************************************************** // @@ -3268,34 +3268,33 @@ // Field: [24] SWEV3 // // Writing "1" to this bit when the value is "0" triggers the Software 3 event. -#define EVENT_SWEV_SWEV3 0x01000000 -#define EVENT_SWEV_SWEV3_BITN 24 -#define EVENT_SWEV_SWEV3_M 0x01000000 -#define EVENT_SWEV_SWEV3_S 24 +#define EVENT_SWEV_SWEV3 0x01000000 +#define EVENT_SWEV_SWEV3_BITN 24 +#define EVENT_SWEV_SWEV3_M 0x01000000 +#define EVENT_SWEV_SWEV3_S 24 // Field: [16] SWEV2 // // Writing "1" to this bit when the value is "0" triggers the Software 2 event. -#define EVENT_SWEV_SWEV2 0x00010000 -#define EVENT_SWEV_SWEV2_BITN 16 -#define EVENT_SWEV_SWEV2_M 0x00010000 -#define EVENT_SWEV_SWEV2_S 16 +#define EVENT_SWEV_SWEV2 0x00010000 +#define EVENT_SWEV_SWEV2_BITN 16 +#define EVENT_SWEV_SWEV2_M 0x00010000 +#define EVENT_SWEV_SWEV2_S 16 // Field: [8] SWEV1 // // Writing "1" to this bit when the value is "0" triggers the Software 1 event. -#define EVENT_SWEV_SWEV1 0x00000100 -#define EVENT_SWEV_SWEV1_BITN 8 -#define EVENT_SWEV_SWEV1_M 0x00000100 -#define EVENT_SWEV_SWEV1_S 8 +#define EVENT_SWEV_SWEV1 0x00000100 +#define EVENT_SWEV_SWEV1_BITN 8 +#define EVENT_SWEV_SWEV1_M 0x00000100 +#define EVENT_SWEV_SWEV1_S 8 // Field: [0] SWEV0 // // Writing "1" to this bit when the value is "0" triggers the Software 0 event. -#define EVENT_SWEV_SWEV0 0x00000001 -#define EVENT_SWEV_SWEV0_BITN 0 -#define EVENT_SWEV_SWEV0_M 0x00000001 -#define EVENT_SWEV_SWEV0_S 0 - +#define EVENT_SWEV_SWEV0 0x00000001 +#define EVENT_SWEV_SWEV0_BITN 0 +#define EVENT_SWEV_SWEV0_M 0x00000001 +#define EVENT_SWEV_SWEV0_S 0 #endif // __EVENT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_fcfg1.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_fcfg1.h index 44459f5..8f2c726 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_fcfg1.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_fcfg1.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_fcfg1_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_fcfg1_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_FCFG1_H__ #define __HW_FCFG1_H__ @@ -44,248 +44,248 @@ // //***************************************************************************** // Misc configurations -#define FCFG1_O_MISC_CONF_1 0x000000A0 +#define FCFG1_O_MISC_CONF_1 0x000000A0 // Internal -#define FCFG1_O_MISC_CONF_2 0x000000A4 +#define FCFG1_O_MISC_CONF_2 0x000000A4 // Internal -#define FCFG1_O_CONFIG_RF_FRONTEND_DIV5 0x000000C4 +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV5 0x000000C4 // Internal -#define FCFG1_O_CONFIG_RF_FRONTEND_DIV6 0x000000C8 +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV6 0x000000C8 // Internal -#define FCFG1_O_CONFIG_RF_FRONTEND_DIV10 0x000000CC +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV10 0x000000CC // Internal -#define FCFG1_O_CONFIG_RF_FRONTEND_DIV12 0x000000D0 +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV12 0x000000D0 // Internal -#define FCFG1_O_CONFIG_RF_FRONTEND_DIV15 0x000000D4 +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV15 0x000000D4 // Internal -#define FCFG1_O_CONFIG_RF_FRONTEND_DIV30 0x000000D8 +#define FCFG1_O_CONFIG_RF_FRONTEND_DIV30 0x000000D8 // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV5 0x000000DC +#define FCFG1_O_CONFIG_SYNTH_DIV5 0x000000DC // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV6 0x000000E0 +#define FCFG1_O_CONFIG_SYNTH_DIV6 0x000000E0 // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV10 0x000000E4 +#define FCFG1_O_CONFIG_SYNTH_DIV10 0x000000E4 // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV12 0x000000E8 +#define FCFG1_O_CONFIG_SYNTH_DIV12 0x000000E8 // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV15 0x000000EC +#define FCFG1_O_CONFIG_SYNTH_DIV15 0x000000EC // Internal -#define FCFG1_O_CONFIG_SYNTH_DIV30 0x000000F0 +#define FCFG1_O_CONFIG_SYNTH_DIV30 0x000000F0 // Internal -#define FCFG1_O_CONFIG_MISC_ADC_DIV5 0x000000F4 +#define FCFG1_O_CONFIG_MISC_ADC_DIV5 0x000000F4 // Internal -#define FCFG1_O_CONFIG_MISC_ADC_DIV6 0x000000F8 +#define FCFG1_O_CONFIG_MISC_ADC_DIV6 0x000000F8 // Internal -#define FCFG1_O_CONFIG_MISC_ADC_DIV10 0x000000FC +#define FCFG1_O_CONFIG_MISC_ADC_DIV10 0x000000FC // Internal -#define FCFG1_O_CONFIG_MISC_ADC_DIV12 0x00000100 +#define FCFG1_O_CONFIG_MISC_ADC_DIV12 0x00000100 // Internal -#define FCFG1_O_CONFIG_MISC_ADC_DIV15 0x00000104 +#define FCFG1_O_CONFIG_MISC_ADC_DIV15 0x00000104 // Internal -#define FCFG1_O_CONFIG_MISC_ADC_DIV30 0x00000108 +#define FCFG1_O_CONFIG_MISC_ADC_DIV30 0x00000108 // Shadow of EFUSE:DIE_ID_0 -#define FCFG1_O_SHDW_DIE_ID_0 0x00000118 +#define FCFG1_O_SHDW_DIE_ID_0 0x00000118 // Shadow of EFUSE:DIE_ID_1 -#define FCFG1_O_SHDW_DIE_ID_1 0x0000011C +#define FCFG1_O_SHDW_DIE_ID_1 0x0000011C // Shadow of EFUSE:DIE_ID_2 -#define FCFG1_O_SHDW_DIE_ID_2 0x00000120 +#define FCFG1_O_SHDW_DIE_ID_2 0x00000120 // Shadow of EFUSE:DIE_ID_3 -#define FCFG1_O_SHDW_DIE_ID_3 0x00000124 +#define FCFG1_O_SHDW_DIE_ID_3 0x00000124 // Internal -#define FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM 0x00000138 +#define FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM 0x00000138 // Internal -#define FCFG1_O_SHDW_ANA_TRIM 0x0000013C +#define FCFG1_O_SHDW_ANA_TRIM 0x0000013C -#define FCFG1_O_FLASH_NUMBER 0x00000164 +#define FCFG1_O_FLASH_NUMBER 0x00000164 -#define FCFG1_O_FLASH_COORDINATE 0x0000016C +#define FCFG1_O_FLASH_COORDINATE 0x0000016C // Internal -#define FCFG1_O_FLASH_E_P 0x00000170 +#define FCFG1_O_FLASH_E_P 0x00000170 // Internal -#define FCFG1_O_FLASH_C_E_P_R 0x00000174 +#define FCFG1_O_FLASH_C_E_P_R 0x00000174 // Internal -#define FCFG1_O_FLASH_P_R_PV 0x00000178 +#define FCFG1_O_FLASH_P_R_PV 0x00000178 // Internal -#define FCFG1_O_FLASH_EH_SEQ 0x0000017C +#define FCFG1_O_FLASH_EH_SEQ 0x0000017C // Internal -#define FCFG1_O_FLASH_VHV_E 0x00000180 +#define FCFG1_O_FLASH_VHV_E 0x00000180 // Internal -#define FCFG1_O_FLASH_PP 0x00000184 +#define FCFG1_O_FLASH_PP 0x00000184 // Internal -#define FCFG1_O_FLASH_PROG_EP 0x00000188 +#define FCFG1_O_FLASH_PROG_EP 0x00000188 // Internal -#define FCFG1_O_FLASH_ERA_PW 0x0000018C +#define FCFG1_O_FLASH_ERA_PW 0x0000018C // Internal -#define FCFG1_O_FLASH_VHV 0x00000190 +#define FCFG1_O_FLASH_VHV 0x00000190 // Internal -#define FCFG1_O_FLASH_VHV_PV 0x00000194 +#define FCFG1_O_FLASH_VHV_PV 0x00000194 // Internal -#define FCFG1_O_FLASH_V 0x00000198 +#define FCFG1_O_FLASH_V 0x00000198 // User Identification. -#define FCFG1_O_USER_ID 0x00000294 +#define FCFG1_O_USER_ID 0x00000294 // Internal -#define FCFG1_O_FLASH_OTP_DATA3 0x000002B0 +#define FCFG1_O_FLASH_OTP_DATA3 0x000002B0 // Internal -#define FCFG1_O_ANA2_TRIM 0x000002B4 +#define FCFG1_O_ANA2_TRIM 0x000002B4 // Internal -#define FCFG1_O_LDO_TRIM 0x000002B8 +#define FCFG1_O_LDO_TRIM 0x000002B8 // Internal -#define FCFG1_O_BAT_RC_LDO_TRIM 0x000002BC +#define FCFG1_O_BAT_RC_LDO_TRIM 0x000002BC // MAC BLE Address 0 -#define FCFG1_O_MAC_BLE_0 0x000002E8 +#define FCFG1_O_MAC_BLE_0 0x000002E8 // MAC BLE Address 1 -#define FCFG1_O_MAC_BLE_1 0x000002EC +#define FCFG1_O_MAC_BLE_1 0x000002EC // MAC IEEE 802.15.4 Address 0 -#define FCFG1_O_MAC_15_4_0 0x000002F0 +#define FCFG1_O_MAC_15_4_0 0x000002F0 // MAC IEEE 802.15.4 Address 1 -#define FCFG1_O_MAC_15_4_1 0x000002F4 +#define FCFG1_O_MAC_15_4_1 0x000002F4 // Internal -#define FCFG1_O_FLASH_OTP_DATA4 0x00000308 +#define FCFG1_O_FLASH_OTP_DATA4 0x00000308 // Miscellaneous Trim Parameters -#define FCFG1_O_MISC_TRIM 0x0000030C +#define FCFG1_O_MISC_TRIM 0x0000030C // Internal -#define FCFG1_O_RCOSC_HF_TEMPCOMP 0x00000310 +#define FCFG1_O_RCOSC_HF_TEMPCOMP 0x00000310 // Internal -#define FCFG1_O_TRIM_CAL_REVISION 0x00000314 +#define FCFG1_O_TRIM_CAL_REVISION 0x00000314 // IcePick Device Identification -#define FCFG1_O_ICEPICK_DEVICE_ID 0x00000318 +#define FCFG1_O_ICEPICK_DEVICE_ID 0x00000318 // Factory Configuration (FCFG1) Revision -#define FCFG1_O_FCFG1_REVISION 0x0000031C +#define FCFG1_O_FCFG1_REVISION 0x0000031C // Misc OTP Data -#define FCFG1_O_MISC_OTP_DATA 0x00000320 +#define FCFG1_O_MISC_OTP_DATA 0x00000320 // IO Configuration -#define FCFG1_O_IOCONF 0x00000344 +#define FCFG1_O_IOCONF 0x00000344 // Internal -#define FCFG1_O_CONFIG_IF_ADC 0x0000034C +#define FCFG1_O_CONFIG_IF_ADC 0x0000034C // Internal -#define FCFG1_O_CONFIG_OSC_TOP 0x00000350 +#define FCFG1_O_CONFIG_OSC_TOP 0x00000350 // Internal -#define FCFG1_O_CONFIG_RF_FRONTEND 0x00000354 +#define FCFG1_O_CONFIG_RF_FRONTEND 0x00000354 // Internal -#define FCFG1_O_CONFIG_SYNTH 0x00000358 +#define FCFG1_O_CONFIG_SYNTH 0x00000358 // AUX_ADC Gain in Absolute Reference Mode -#define FCFG1_O_SOC_ADC_ABS_GAIN 0x0000035C +#define FCFG1_O_SOC_ADC_ABS_GAIN 0x0000035C // AUX_ADC Gain in Relative Reference Mode -#define FCFG1_O_SOC_ADC_REL_GAIN 0x00000360 +#define FCFG1_O_SOC_ADC_REL_GAIN 0x00000360 // AUX_ADC Temperature Offsets in Absolute Reference Mode -#define FCFG1_O_SOC_ADC_OFFSET_INT 0x00000368 +#define FCFG1_O_SOC_ADC_OFFSET_INT 0x00000368 // Internal -#define FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT 0x0000036C +#define FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT 0x0000036C // Internal -#define FCFG1_O_AMPCOMP_TH1 0x00000370 +#define FCFG1_O_AMPCOMP_TH1 0x00000370 // Internal -#define FCFG1_O_AMPCOMP_TH2 0x00000374 +#define FCFG1_O_AMPCOMP_TH2 0x00000374 // Internal -#define FCFG1_O_AMPCOMP_CTRL1 0x00000378 +#define FCFG1_O_AMPCOMP_CTRL1 0x00000378 // Internal -#define FCFG1_O_ANABYPASS_VALUE2 0x0000037C +#define FCFG1_O_ANABYPASS_VALUE2 0x0000037C // Internal -#define FCFG1_O_CONFIG_MISC_ADC 0x00000380 +#define FCFG1_O_CONFIG_MISC_ADC 0x00000380 // Internal -#define FCFG1_O_VOLT_TRIM 0x00000388 +#define FCFG1_O_VOLT_TRIM 0x00000388 // OSC Configuration -#define FCFG1_O_OSC_CONF 0x0000038C +#define FCFG1_O_OSC_CONF 0x0000038C // Internal -#define FCFG1_O_FREQ_OFFSET 0x00000390 +#define FCFG1_O_FREQ_OFFSET 0x00000390 // Internal -#define FCFG1_O_CAP_TRIM 0x00000394 +#define FCFG1_O_CAP_TRIM 0x00000394 // Internal -#define FCFG1_O_MISC_OTP_DATA_1 0x00000398 +#define FCFG1_O_MISC_OTP_DATA_1 0x00000398 // Power Down Current Control 20C -#define FCFG1_O_PWD_CURR_20C 0x0000039C +#define FCFG1_O_PWD_CURR_20C 0x0000039C // Power Down Current Control 35C -#define FCFG1_O_PWD_CURR_35C 0x000003A0 +#define FCFG1_O_PWD_CURR_35C 0x000003A0 // Power Down Current Control 50C -#define FCFG1_O_PWD_CURR_50C 0x000003A4 +#define FCFG1_O_PWD_CURR_50C 0x000003A4 // Power Down Current Control 65C -#define FCFG1_O_PWD_CURR_65C 0x000003A8 +#define FCFG1_O_PWD_CURR_65C 0x000003A8 // Power Down Current Control 80C -#define FCFG1_O_PWD_CURR_80C 0x000003AC +#define FCFG1_O_PWD_CURR_80C 0x000003AC // Power Down Current Control 95C -#define FCFG1_O_PWD_CURR_95C 0x000003B0 +#define FCFG1_O_PWD_CURR_95C 0x000003B0 // Power Down Current Control 110C -#define FCFG1_O_PWD_CURR_110C 0x000003B4 +#define FCFG1_O_PWD_CURR_110C 0x000003B4 // Power Down Current Control 125C -#define FCFG1_O_PWD_CURR_125C 0x000003B8 +#define FCFG1_O_PWD_CURR_125C 0x000003B8 //***************************************************************************** // @@ -298,9 +298,9 @@ // Any test of this field by SW should be implemented as a 'greater or equal' // comparison as signed integer. // Value may change without warning. -#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_W 8 -#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M 0x000000FF -#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S 0 +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_W 8 +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M 0x000000FF +#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S 0 //***************************************************************************** // @@ -310,9 +310,9 @@ // Field: [7:0] HPOSC_COMP_P3 // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W 8 -#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_M 0x000000FF -#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S 0 +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W 8 +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_M 0x000000FF +#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S 0 //***************************************************************************** // @@ -322,37 +322,37 @@ // Field: [31:28] IFAMP_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_S 28 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_IB_S 28 // Field: [27:24] LNA_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_S 24 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_LNA_IB_S 24 // Field: [23:19] IFAMP_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_S 19 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_IFAMP_TRIM_S 19 // Field: [18:14] CTL_PA0_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_S 14 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_CTL_PA0_TRIM_S 14 // Field: [6:0] RFLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_M 0x0000007F -#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV5_RFLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -362,37 +362,37 @@ // Field: [31:28] IFAMP_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_S 28 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_IB_S 28 // Field: [27:24] LNA_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_S 24 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_LNA_IB_S 24 // Field: [23:19] IFAMP_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_S 19 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_IFAMP_TRIM_S 19 // Field: [18:14] CTL_PA0_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_S 14 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_CTL_PA0_TRIM_S 14 // Field: [6:0] RFLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_M 0x0000007F -#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV6_RFLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -402,37 +402,37 @@ // Field: [31:28] IFAMP_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_S 28 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_IB_S 28 // Field: [27:24] LNA_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_S 24 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_LNA_IB_S 24 // Field: [23:19] IFAMP_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_S 19 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_IFAMP_TRIM_S 19 // Field: [18:14] CTL_PA0_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_S 14 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_CTL_PA0_TRIM_S 14 // Field: [6:0] RFLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_M 0x0000007F -#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV10_RFLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -442,37 +442,37 @@ // Field: [31:28] IFAMP_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_S 28 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_IB_S 28 // Field: [27:24] LNA_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_S 24 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_LNA_IB_S 24 // Field: [23:19] IFAMP_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_S 19 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_IFAMP_TRIM_S 19 // Field: [18:14] CTL_PA0_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_S 14 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_CTL_PA0_TRIM_S 14 // Field: [6:0] RFLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_M 0x0000007F -#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV12_RFLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -482,37 +482,37 @@ // Field: [31:28] IFAMP_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_S 28 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_IB_S 28 // Field: [27:24] LNA_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_S 24 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_LNA_IB_S 24 // Field: [23:19] IFAMP_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_S 19 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_IFAMP_TRIM_S 19 // Field: [18:14] CTL_PA0_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_S 14 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_CTL_PA0_TRIM_S 14 // Field: [6:0] RFLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_M 0x0000007F -#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV15_RFLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -522,37 +522,37 @@ // Field: [31:28] IFAMP_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_S 28 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_IB_S 28 // Field: [27:24] LNA_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_S 24 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_LNA_IB_S 24 // Field: [23:19] IFAMP_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_S 19 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_IFAMP_TRIM_S 19 // Field: [18:14] CTL_PA0_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_S 14 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_CTL_PA0_TRIM_S 14 // Field: [6:0] RFLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_M 0x0000007F -#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_DIV30_RFLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -563,23 +563,23 @@ // // Trim value for RF Core. // Value is read by RF Core ROM FW during RF Core initialization. -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5:0] SLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_M 0x0000003F -#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV5_SLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -590,23 +590,23 @@ // // Trim value for RF Core. // Value is read by RF Core ROM FW during RF Core initialization. -#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV6_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV6_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5:0] SLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_M 0x0000003F -#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV6_SLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -617,23 +617,23 @@ // // Trim value for RF Core. // Value is read by RF Core ROM FW during RF Core initialization. -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5:0] SLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_M 0x0000003F -#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV10_SLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -644,23 +644,23 @@ // // Trim value for RF Core. // Value is read by RF Core ROM FW during RF Core initialization. -#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV12_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV12_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5:0] SLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_M 0x0000003F -#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV12_SLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -671,23 +671,23 @@ // // Trim value for RF Core. // Value is read by RF Core ROM FW during RF Core initialization. -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5:0] SLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_M 0x0000003F -#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV15_SLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -698,23 +698,23 @@ // // Trim value for RF Core. // Value is read by RF Core ROM FW during RF Core initialization. -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5:0] SLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_M 0x0000003F -#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_DIV30_SLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -724,23 +724,23 @@ // Field: [16:9] RSSI_OFFSET // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_M 0x0001FE00 -#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_S 9 +#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV5_RSSI_OFFSET_S 9 // Field: [8:6] QUANTCTLTHRES // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_S 6 +#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV5_QUANTCTLTHRES_S 6 // Field: [5:0] DACTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_W 6 -#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_S 0 +#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV5_DACTRIM_S 0 //***************************************************************************** // @@ -750,23 +750,23 @@ // Field: [16:9] RSSI_OFFSET // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_M 0x0001FE00 -#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_S 9 +#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV6_RSSI_OFFSET_S 9 // Field: [8:6] QUANTCTLTHRES // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_S 6 +#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV6_QUANTCTLTHRES_S 6 // Field: [5:0] DACTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_W 6 -#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_S 0 +#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV6_DACTRIM_S 0 //***************************************************************************** // @@ -776,23 +776,23 @@ // Field: [16:9] RSSI_OFFSET // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_M 0x0001FE00 -#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_S 9 +#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV10_RSSI_OFFSET_S 9 // Field: [8:6] QUANTCTLTHRES // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_S 6 +#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV10_QUANTCTLTHRES_S 6 // Field: [5:0] DACTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_W 6 -#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_S 0 +#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV10_DACTRIM_S 0 //***************************************************************************** // @@ -802,23 +802,23 @@ // Field: [16:9] RSSI_OFFSET // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_M 0x0001FE00 -#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_S 9 +#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV12_RSSI_OFFSET_S 9 // Field: [8:6] QUANTCTLTHRES // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_S 6 +#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV12_QUANTCTLTHRES_S 6 // Field: [5:0] DACTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_W 6 -#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_S 0 +#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV12_DACTRIM_S 0 //***************************************************************************** // @@ -828,23 +828,23 @@ // Field: [16:9] RSSI_OFFSET // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_M 0x0001FE00 -#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_S 9 +#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV15_RSSI_OFFSET_S 9 // Field: [8:6] QUANTCTLTHRES // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_S 6 +#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV15_QUANTCTLTHRES_S 6 // Field: [5:0] DACTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_W 6 -#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_S 0 +#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV15_DACTRIM_S 0 //***************************************************************************** // @@ -854,23 +854,23 @@ // Field: [16:9] RSSI_OFFSET // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_M 0x0001FE00 -#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_S 9 +#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_DIV30_RSSI_OFFSET_S 9 // Field: [8:6] QUANTCTLTHRES // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_S 6 +#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_DIV30_QUANTCTLTHRES_S 6 // Field: [5:0] DACTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_W 6 -#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_S 0 +#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DIV30_DACTRIM_S 0 //***************************************************************************** // @@ -880,9 +880,9 @@ // Field: [31:0] ID_31_0 // // Shadow of DIE_ID_0 register in eFuse row number 3 -#define FCFG1_SHDW_DIE_ID_0_ID_31_0_W 32 -#define FCFG1_SHDW_DIE_ID_0_ID_31_0_M 0xFFFFFFFF -#define FCFG1_SHDW_DIE_ID_0_ID_31_0_S 0 +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_W 32 +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_0_ID_31_0_S 0 //***************************************************************************** // @@ -892,9 +892,9 @@ // Field: [31:0] ID_63_32 // // Shadow of DIE_ID_1 register in eFuse row number 4 -#define FCFG1_SHDW_DIE_ID_1_ID_63_32_W 32 -#define FCFG1_SHDW_DIE_ID_1_ID_63_32_M 0xFFFFFFFF -#define FCFG1_SHDW_DIE_ID_1_ID_63_32_S 0 +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_W 32 +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_1_ID_63_32_S 0 //***************************************************************************** // @@ -904,9 +904,9 @@ // Field: [31:0] ID_95_64 // // Shadow of DIE_ID_2 register in eFuse row number 5 -#define FCFG1_SHDW_DIE_ID_2_ID_95_64_W 32 -#define FCFG1_SHDW_DIE_ID_2_ID_95_64_M 0xFFFFFFFF -#define FCFG1_SHDW_DIE_ID_2_ID_95_64_S 0 +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_W 32 +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_2_ID_95_64_S 0 //***************************************************************************** // @@ -916,9 +916,9 @@ // Field: [31:0] ID_127_96 // // Shadow of DIE_ID_3 register in eFuse row number 6 -#define FCFG1_SHDW_DIE_ID_3_ID_127_96_W 32 -#define FCFG1_SHDW_DIE_ID_3_ID_127_96_M 0xFFFFFFFF -#define FCFG1_SHDW_DIE_ID_3_ID_127_96_S 0 +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_W 32 +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_M 0xFFFFFFFF +#define FCFG1_SHDW_DIE_ID_3_ID_127_96_S 0 //***************************************************************************** // @@ -928,54 +928,54 @@ // Field: [28:27] SET_RCOSC_HF_COARSE_RESISTOR // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_W \ +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_W \ 2 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_M \ +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_M \ 0x18000000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_S \ +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_SET_RCOSC_HF_COARSE_RESISTOR_S \ 27 // Field: [26:23] TRIMMAG // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_W 4 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_M 0x07800000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_S 23 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_M 0x07800000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_S 23 // Field: [22:18] TRIMIREF // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_W 5 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_M 0x007C0000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_S 18 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_W 5 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_M 0x007C0000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_S 18 // Field: [17:16] ITRIM_DIG_LDO // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_W 2 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_M 0x00030000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_S 16 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_W 2 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_M 0x00030000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_S 16 // Field: [15:12] VTRIM_DIG // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_W 4 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_M 0x0000F000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_S 12 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_M 0x0000F000 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_S 12 // Field: [11:8] VTRIM_COARSE // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_W 4 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_M 0x00000F00 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_S 8 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_W 4 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_M 0x00000F00 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_S 8 // Field: [7:0] RCOSCHF_CTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_W 8 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M 0x000000FF -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S 0 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_W 8 +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M 0x000000FF +#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S 0 //***************************************************************************** // @@ -985,60 +985,60 @@ // Field: [26:25] BOD_BANDGAP_TRIM_CNF // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_W 2 -#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_M 0x06000000 -#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_S 25 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_W 2 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_M 0x06000000 +#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_S 25 // Field: [24] VDDR_ENABLE_PG1 // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1 0x01000000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_BITN 24 -#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_M 0x01000000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_S 24 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1 0x01000000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_BITN 24 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_M 0x01000000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_S 24 // Field: [23] VDDR_OK_HYS // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS 0x00800000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_BITN 23 -#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_M 0x00800000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_S 23 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS 0x00800000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_BITN 23 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_M 0x00800000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_S 23 // Field: [22:21] IPTAT_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_W 2 -#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_M 0x00600000 -#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_S 21 +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_W 2 +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_M 0x00600000 +#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_S 21 // Field: [20:16] VDDR_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_W 5 -#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M 0x001F0000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S 16 +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_W 5 +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M 0x001F0000 +#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S 16 // Field: [15:11] TRIMBOD_INTMODE // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_W 5 -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_M 0x0000F800 -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_S 11 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_W 5 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_M 0x0000F800 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_S 11 // Field: [10:6] TRIMBOD_EXTMODE // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_W 5 -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_M 0x000007C0 -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_S 6 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_W 5 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_M 0x000007C0 +#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_S 6 // Field: [5:0] TRIMTEMP // // Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W 6 -#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_M 0x0000003F -#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_S 0 +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W 6 +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_M 0x0000003F +#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_S 0 //***************************************************************************** // @@ -1048,9 +1048,9 @@ // Field: [31:0] LOT_NUMBER // // Number of the manufacturing lot that produced this unit. -#define FCFG1_FLASH_NUMBER_LOT_NUMBER_W 32 -#define FCFG1_FLASH_NUMBER_LOT_NUMBER_M 0xFFFFFFFF -#define FCFG1_FLASH_NUMBER_LOT_NUMBER_S 0 +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_W 32 +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_M 0xFFFFFFFF +#define FCFG1_FLASH_NUMBER_LOT_NUMBER_S 0 //***************************************************************************** // @@ -1060,16 +1060,16 @@ // Field: [31:16] XCOORDINATE // // X coordinate of this unit on the wafer. -#define FCFG1_FLASH_COORDINATE_XCOORDINATE_W 16 -#define FCFG1_FLASH_COORDINATE_XCOORDINATE_M 0xFFFF0000 -#define FCFG1_FLASH_COORDINATE_XCOORDINATE_S 16 +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_W 16 +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_M 0xFFFF0000 +#define FCFG1_FLASH_COORDINATE_XCOORDINATE_S 16 // Field: [15:0] YCOORDINATE // // Y coordinate of this unit on the wafer. -#define FCFG1_FLASH_COORDINATE_YCOORDINATE_W 16 -#define FCFG1_FLASH_COORDINATE_YCOORDINATE_M 0x0000FFFF -#define FCFG1_FLASH_COORDINATE_YCOORDINATE_S 0 +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_W 16 +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_M 0x0000FFFF +#define FCFG1_FLASH_COORDINATE_YCOORDINATE_S 0 //***************************************************************************** // @@ -1079,30 +1079,30 @@ // Field: [31:24] PSU // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_E_P_PSU_W 8 -#define FCFG1_FLASH_E_P_PSU_M 0xFF000000 -#define FCFG1_FLASH_E_P_PSU_S 24 +#define FCFG1_FLASH_E_P_PSU_W 8 +#define FCFG1_FLASH_E_P_PSU_M 0xFF000000 +#define FCFG1_FLASH_E_P_PSU_S 24 // Field: [23:16] ESU // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_E_P_ESU_W 8 -#define FCFG1_FLASH_E_P_ESU_M 0x00FF0000 -#define FCFG1_FLASH_E_P_ESU_S 16 +#define FCFG1_FLASH_E_P_ESU_W 8 +#define FCFG1_FLASH_E_P_ESU_M 0x00FF0000 +#define FCFG1_FLASH_E_P_ESU_S 16 // Field: [15:8] PVSU // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_E_P_PVSU_W 8 -#define FCFG1_FLASH_E_P_PVSU_M 0x0000FF00 -#define FCFG1_FLASH_E_P_PVSU_S 8 +#define FCFG1_FLASH_E_P_PVSU_W 8 +#define FCFG1_FLASH_E_P_PVSU_M 0x0000FF00 +#define FCFG1_FLASH_E_P_PVSU_S 8 // Field: [7:0] EVSU // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_E_P_EVSU_W 8 -#define FCFG1_FLASH_E_P_EVSU_M 0x000000FF -#define FCFG1_FLASH_E_P_EVSU_S 0 +#define FCFG1_FLASH_E_P_EVSU_W 8 +#define FCFG1_FLASH_E_P_EVSU_M 0x000000FF +#define FCFG1_FLASH_E_P_EVSU_S 0 //***************************************************************************** // @@ -1112,30 +1112,30 @@ // Field: [31:24] RVSU // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_C_E_P_R_RVSU_W 8 -#define FCFG1_FLASH_C_E_P_R_RVSU_M 0xFF000000 -#define FCFG1_FLASH_C_E_P_R_RVSU_S 24 +#define FCFG1_FLASH_C_E_P_R_RVSU_W 8 +#define FCFG1_FLASH_C_E_P_R_RVSU_M 0xFF000000 +#define FCFG1_FLASH_C_E_P_R_RVSU_S 24 // Field: [23:16] PV_ACCESS // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_W 8 -#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_M 0x00FF0000 -#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_S 16 +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_W 8 +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_M 0x00FF0000 +#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_S 16 // Field: [15:12] A_EXEZ_SETUP // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_W 4 -#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M 0x0000F000 -#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S 12 +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_W 4 +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M 0x0000F000 +#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S 12 // Field: [11:0] CVSU // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_C_E_P_R_CVSU_W 12 -#define FCFG1_FLASH_C_E_P_R_CVSU_M 0x00000FFF -#define FCFG1_FLASH_C_E_P_R_CVSU_S 0 +#define FCFG1_FLASH_C_E_P_R_CVSU_W 12 +#define FCFG1_FLASH_C_E_P_R_CVSU_M 0x00000FFF +#define FCFG1_FLASH_C_E_P_R_CVSU_S 0 //***************************************************************************** // @@ -1145,30 +1145,30 @@ // Field: [31:24] PH // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_P_R_PV_PH_W 8 -#define FCFG1_FLASH_P_R_PV_PH_M 0xFF000000 -#define FCFG1_FLASH_P_R_PV_PH_S 24 +#define FCFG1_FLASH_P_R_PV_PH_W 8 +#define FCFG1_FLASH_P_R_PV_PH_M 0xFF000000 +#define FCFG1_FLASH_P_R_PV_PH_S 24 // Field: [23:16] RH // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_P_R_PV_RH_W 8 -#define FCFG1_FLASH_P_R_PV_RH_M 0x00FF0000 -#define FCFG1_FLASH_P_R_PV_RH_S 16 +#define FCFG1_FLASH_P_R_PV_RH_W 8 +#define FCFG1_FLASH_P_R_PV_RH_M 0x00FF0000 +#define FCFG1_FLASH_P_R_PV_RH_S 16 // Field: [15:8] PVH // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_P_R_PV_PVH_W 8 -#define FCFG1_FLASH_P_R_PV_PVH_M 0x0000FF00 -#define FCFG1_FLASH_P_R_PV_PVH_S 8 +#define FCFG1_FLASH_P_R_PV_PVH_W 8 +#define FCFG1_FLASH_P_R_PV_PVH_M 0x0000FF00 +#define FCFG1_FLASH_P_R_PV_PVH_S 8 // Field: [7:0] PVH2 // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_P_R_PV_PVH2_W 8 -#define FCFG1_FLASH_P_R_PV_PVH2_M 0x000000FF -#define FCFG1_FLASH_P_R_PV_PVH2_S 0 +#define FCFG1_FLASH_P_R_PV_PVH2_W 8 +#define FCFG1_FLASH_P_R_PV_PVH2_M 0x000000FF +#define FCFG1_FLASH_P_R_PV_PVH2_S 0 //***************************************************************************** // @@ -1178,30 +1178,30 @@ // Field: [31:24] EH // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_EH_SEQ_EH_W 8 -#define FCFG1_FLASH_EH_SEQ_EH_M 0xFF000000 -#define FCFG1_FLASH_EH_SEQ_EH_S 24 +#define FCFG1_FLASH_EH_SEQ_EH_W 8 +#define FCFG1_FLASH_EH_SEQ_EH_M 0xFF000000 +#define FCFG1_FLASH_EH_SEQ_EH_S 24 // Field: [23:16] SEQ // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_EH_SEQ_SEQ_W 8 -#define FCFG1_FLASH_EH_SEQ_SEQ_M 0x00FF0000 -#define FCFG1_FLASH_EH_SEQ_SEQ_S 16 +#define FCFG1_FLASH_EH_SEQ_SEQ_W 8 +#define FCFG1_FLASH_EH_SEQ_SEQ_M 0x00FF0000 +#define FCFG1_FLASH_EH_SEQ_SEQ_S 16 // Field: [15:12] VSTAT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_EH_SEQ_VSTAT_W 4 -#define FCFG1_FLASH_EH_SEQ_VSTAT_M 0x0000F000 -#define FCFG1_FLASH_EH_SEQ_VSTAT_S 12 +#define FCFG1_FLASH_EH_SEQ_VSTAT_W 4 +#define FCFG1_FLASH_EH_SEQ_VSTAT_M 0x0000F000 +#define FCFG1_FLASH_EH_SEQ_VSTAT_S 12 // Field: [11:0] SM_FREQUENCY // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_W 12 -#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_M 0x00000FFF -#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_S 0 +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_W 12 +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_M 0x00000FFF +#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_S 0 //***************************************************************************** // @@ -1211,16 +1211,16 @@ // Field: [31:16] VHV_E_START // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_E_VHV_E_START_W 16 -#define FCFG1_FLASH_VHV_E_VHV_E_START_M 0xFFFF0000 -#define FCFG1_FLASH_VHV_E_VHV_E_START_S 16 +#define FCFG1_FLASH_VHV_E_VHV_E_START_W 16 +#define FCFG1_FLASH_VHV_E_VHV_E_START_M 0xFFFF0000 +#define FCFG1_FLASH_VHV_E_VHV_E_START_S 16 // Field: [15:0] VHV_E_STEP_HIGHT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_W 16 -#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M 0x0000FFFF -#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S 0 +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_W 16 +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M 0x0000FFFF +#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S 0 //***************************************************************************** // @@ -1230,16 +1230,16 @@ // Field: [31:24] PUMP_SU // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PP_PUMP_SU_W 8 -#define FCFG1_FLASH_PP_PUMP_SU_M 0xFF000000 -#define FCFG1_FLASH_PP_PUMP_SU_S 24 +#define FCFG1_FLASH_PP_PUMP_SU_W 8 +#define FCFG1_FLASH_PP_PUMP_SU_M 0xFF000000 +#define FCFG1_FLASH_PP_PUMP_SU_S 24 // Field: [15:0] MAX_PP // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PP_MAX_PP_W 16 -#define FCFG1_FLASH_PP_MAX_PP_M 0x0000FFFF -#define FCFG1_FLASH_PP_MAX_PP_S 0 +#define FCFG1_FLASH_PP_MAX_PP_W 16 +#define FCFG1_FLASH_PP_MAX_PP_M 0x0000FFFF +#define FCFG1_FLASH_PP_MAX_PP_S 0 //***************************************************************************** // @@ -1249,16 +1249,16 @@ // Field: [31:16] MAX_EP // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PROG_EP_MAX_EP_W 16 -#define FCFG1_FLASH_PROG_EP_MAX_EP_M 0xFFFF0000 -#define FCFG1_FLASH_PROG_EP_MAX_EP_S 16 +#define FCFG1_FLASH_PROG_EP_MAX_EP_W 16 +#define FCFG1_FLASH_PROG_EP_MAX_EP_M 0xFFFF0000 +#define FCFG1_FLASH_PROG_EP_MAX_EP_S 16 // Field: [15:0] PROGRAM_PW // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_W 16 -#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_M 0x0000FFFF -#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_S 0 +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_W 16 +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_M 0x0000FFFF +#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_S 0 //***************************************************************************** // @@ -1268,9 +1268,9 @@ // Field: [31:0] ERASE_PW // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_ERA_PW_ERASE_PW_W 32 -#define FCFG1_FLASH_ERA_PW_ERASE_PW_M 0xFFFFFFFF -#define FCFG1_FLASH_ERA_PW_ERASE_PW_S 0 +#define FCFG1_FLASH_ERA_PW_ERASE_PW_W 32 +#define FCFG1_FLASH_ERA_PW_ERASE_PW_M 0xFFFFFFFF +#define FCFG1_FLASH_ERA_PW_ERASE_PW_S 0 //***************************************************************************** // @@ -1280,30 +1280,30 @@ // Field: [27:24] TRIM13_P // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_TRIM13_P_W 4 -#define FCFG1_FLASH_VHV_TRIM13_P_M 0x0F000000 -#define FCFG1_FLASH_VHV_TRIM13_P_S 24 +#define FCFG1_FLASH_VHV_TRIM13_P_W 4 +#define FCFG1_FLASH_VHV_TRIM13_P_M 0x0F000000 +#define FCFG1_FLASH_VHV_TRIM13_P_S 24 // Field: [19:16] VHV_P // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_VHV_P_W 4 -#define FCFG1_FLASH_VHV_VHV_P_M 0x000F0000 -#define FCFG1_FLASH_VHV_VHV_P_S 16 +#define FCFG1_FLASH_VHV_VHV_P_W 4 +#define FCFG1_FLASH_VHV_VHV_P_M 0x000F0000 +#define FCFG1_FLASH_VHV_VHV_P_S 16 // Field: [11:8] TRIM13_E // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_TRIM13_E_W 4 -#define FCFG1_FLASH_VHV_TRIM13_E_M 0x00000F00 -#define FCFG1_FLASH_VHV_TRIM13_E_S 8 +#define FCFG1_FLASH_VHV_TRIM13_E_W 4 +#define FCFG1_FLASH_VHV_TRIM13_E_M 0x00000F00 +#define FCFG1_FLASH_VHV_TRIM13_E_S 8 // Field: [3:0] VHV_E // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_VHV_E_W 4 -#define FCFG1_FLASH_VHV_VHV_E_M 0x0000000F -#define FCFG1_FLASH_VHV_VHV_E_S 0 +#define FCFG1_FLASH_VHV_VHV_E_W 4 +#define FCFG1_FLASH_VHV_VHV_E_M 0x0000000F +#define FCFG1_FLASH_VHV_VHV_E_S 0 //***************************************************************************** // @@ -1313,30 +1313,30 @@ // Field: [27:24] TRIM13_PV // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_PV_TRIM13_PV_W 4 -#define FCFG1_FLASH_VHV_PV_TRIM13_PV_M 0x0F000000 -#define FCFG1_FLASH_VHV_PV_TRIM13_PV_S 24 +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_W 4 +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_M 0x0F000000 +#define FCFG1_FLASH_VHV_PV_TRIM13_PV_S 24 // Field: [19:16] VHV_PV // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_PV_VHV_PV_W 4 -#define FCFG1_FLASH_VHV_PV_VHV_PV_M 0x000F0000 -#define FCFG1_FLASH_VHV_PV_VHV_PV_S 16 +#define FCFG1_FLASH_VHV_PV_VHV_PV_W 4 +#define FCFG1_FLASH_VHV_PV_VHV_PV_M 0x000F0000 +#define FCFG1_FLASH_VHV_PV_VHV_PV_S 16 // Field: [15:8] VCG2P5 // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_PV_VCG2P5_W 8 -#define FCFG1_FLASH_VHV_PV_VCG2P5_M 0x0000FF00 -#define FCFG1_FLASH_VHV_PV_VCG2P5_S 8 +#define FCFG1_FLASH_VHV_PV_VCG2P5_W 8 +#define FCFG1_FLASH_VHV_PV_VCG2P5_M 0x0000FF00 +#define FCFG1_FLASH_VHV_PV_VCG2P5_S 8 // Field: [7:0] VINH // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_PV_VINH_W 8 -#define FCFG1_FLASH_VHV_PV_VINH_M 0x000000FF -#define FCFG1_FLASH_VHV_PV_VINH_S 0 +#define FCFG1_FLASH_VHV_PV_VINH_W 8 +#define FCFG1_FLASH_VHV_PV_VINH_M 0x000000FF +#define FCFG1_FLASH_VHV_PV_VINH_S 0 //***************************************************************************** // @@ -1346,23 +1346,23 @@ // Field: [31:24] VSL_P // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_V_VSL_P_W 8 -#define FCFG1_FLASH_V_VSL_P_M 0xFF000000 -#define FCFG1_FLASH_V_VSL_P_S 24 +#define FCFG1_FLASH_V_VSL_P_W 8 +#define FCFG1_FLASH_V_VSL_P_M 0xFF000000 +#define FCFG1_FLASH_V_VSL_P_S 24 // Field: [23:16] VWL_P // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_V_VWL_P_W 8 -#define FCFG1_FLASH_V_VWL_P_M 0x00FF0000 -#define FCFG1_FLASH_V_VWL_P_S 16 +#define FCFG1_FLASH_V_VWL_P_W 8 +#define FCFG1_FLASH_V_VWL_P_M 0x00FF0000 +#define FCFG1_FLASH_V_VWL_P_S 16 // Field: [15:8] V_READ // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_V_V_READ_W 8 -#define FCFG1_FLASH_V_V_READ_M 0x0000FF00 -#define FCFG1_FLASH_V_V_READ_S 8 +#define FCFG1_FLASH_V_V_READ_W 8 +#define FCFG1_FLASH_V_V_READ_M 0x0000FF00 +#define FCFG1_FLASH_V_V_READ_S 8 //***************************************************************************** // @@ -1372,9 +1372,9 @@ // Field: [31:28] PG_REV // // Field used to distinguish revisions of the device. -#define FCFG1_USER_ID_PG_REV_W 4 -#define FCFG1_USER_ID_PG_REV_M 0xF0000000 -#define FCFG1_USER_ID_PG_REV_S 28 +#define FCFG1_USER_ID_PG_REV_W 4 +#define FCFG1_USER_ID_PG_REV_M 0xF0000000 +#define FCFG1_USER_ID_PG_REV_S 28 // Field: [27:26] VER // @@ -1383,9 +1383,9 @@ // 0x0: Bits [25:12] of this register has the stated meaning. // // Any other setting indicate a different encoding of these bits. -#define FCFG1_USER_ID_VER_W 2 -#define FCFG1_USER_ID_VER_M 0x0C000000 -#define FCFG1_USER_ID_VER_S 26 +#define FCFG1_USER_ID_VER_W 2 +#define FCFG1_USER_ID_VER_M 0x0C000000 +#define FCFG1_USER_ID_VER_S 26 // Field: [22:19] SEQUENCE // @@ -1393,9 +1393,9 @@ // // Used to differentiate between marketing/orderable product where other fields // of USER_ID is the same (temp range, flash size, voltage range etc) -#define FCFG1_USER_ID_SEQUENCE_W 4 -#define FCFG1_USER_ID_SEQUENCE_M 0x00780000 -#define FCFG1_USER_ID_SEQUENCE_S 19 +#define FCFG1_USER_ID_SEQUENCE_W 4 +#define FCFG1_USER_ID_SEQUENCE_M 0x00780000 +#define FCFG1_USER_ID_SEQUENCE_S 19 // Field: [18:16] PKG // @@ -1410,9 +1410,9 @@ // // Other values are reserved for future use. // Packages available for a specific device are shown in the device datasheet. -#define FCFG1_USER_ID_PKG_W 3 -#define FCFG1_USER_ID_PKG_M 0x00070000 -#define FCFG1_USER_ID_PKG_S 16 +#define FCFG1_USER_ID_PKG_W 3 +#define FCFG1_USER_ID_PKG_M 0x00070000 +#define FCFG1_USER_ID_PKG_S 16 // Field: [15:12] PROTOCOL // @@ -1425,9 +1425,9 @@ // // More than one protocol can be supported on same device - values above are // then combined. -#define FCFG1_USER_ID_PROTOCOL_W 4 -#define FCFG1_USER_ID_PROTOCOL_M 0x0000F000 -#define FCFG1_USER_ID_PROTOCOL_S 12 +#define FCFG1_USER_ID_PROTOCOL_W 4 +#define FCFG1_USER_ID_PROTOCOL_M 0x0000F000 +#define FCFG1_USER_ID_PROTOCOL_S 12 //***************************************************************************** // @@ -1437,45 +1437,45 @@ // Field: [31:23] EC_STEP_SIZE // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_W 9 -#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M 0xFF800000 -#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S 23 +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_W 9 +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M 0xFF800000 +#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S 23 // Field: [22] DO_PRECOND // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND 0x00400000 -#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_BITN 22 -#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M 0x00400000 -#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S 22 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND 0x00400000 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_BITN 22 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M 0x00400000 +#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S 22 // Field: [21:18] MAX_EC_LEVEL // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_W 4 -#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M 0x003C0000 -#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S 18 +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_W 4 +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M 0x003C0000 +#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S 18 // Field: [17:16] TRIM_1P7 // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_W 2 -#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M 0x00030000 -#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S 16 +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_W 2 +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M 0x00030000 +#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S 16 // Field: [15:8] FLASH_SIZE // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_W 8 -#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_M 0x0000FF00 -#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_S 8 +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_W 8 +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_M 0x0000FF00 +#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_S 8 // Field: [7:0] WAIT_SYSCODE // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_W 8 -#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_M 0x000000FF -#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_S 0 +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_W 8 +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_M 0x000000FF +#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_S 0 //***************************************************************************** // @@ -1485,75 +1485,75 @@ // Field: [31] RCOSCHFCTRIMFRACT_EN // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN 0x80000000 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_BITN 31 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_M 0x80000000 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_S 31 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN 0x80000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_BITN 31 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_M 0x80000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_S 31 // Field: [30:26] RCOSCHFCTRIMFRACT // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_W 5 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_M 0x7C000000 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_S 26 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_W 5 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_M 0x7C000000 +#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_S 26 // Field: [24:23] SET_RCOSC_HF_FINE_RESISTOR // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_W 2 -#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_M 0x01800000 -#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_S 23 +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_W 2 +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_M 0x01800000 +#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_S 23 // Field: [22] ATESTLF_UDIGLDO_IBIAS_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM 0x00400000 -#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_BITN 22 -#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_M 0x00400000 -#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_S 22 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM 0x00400000 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_BITN 22 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_M 0x00400000 +#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_S 22 // Field: [21:16] NANOAMP_RES_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_W 6 -#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_M 0x003F0000 -#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_S 16 +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_W 6 +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_M 0x003F0000 +#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_S 16 // Field: [11] DITHER_EN // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DITHER_EN 0x00000800 -#define FCFG1_ANA2_TRIM_DITHER_EN_BITN 11 -#define FCFG1_ANA2_TRIM_DITHER_EN_M 0x00000800 -#define FCFG1_ANA2_TRIM_DITHER_EN_S 11 +#define FCFG1_ANA2_TRIM_DITHER_EN 0x00000800 +#define FCFG1_ANA2_TRIM_DITHER_EN_BITN 11 +#define FCFG1_ANA2_TRIM_DITHER_EN_M 0x00000800 +#define FCFG1_ANA2_TRIM_DITHER_EN_S 11 // Field: [10:8] DCDC_IPEAK // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DCDC_IPEAK_W 3 -#define FCFG1_ANA2_TRIM_DCDC_IPEAK_M 0x00000700 -#define FCFG1_ANA2_TRIM_DCDC_IPEAK_S 8 +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_W 3 +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_M 0x00000700 +#define FCFG1_ANA2_TRIM_DCDC_IPEAK_S 8 // Field: [7:6] DEAD_TIME_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_W 2 -#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_M 0x000000C0 -#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_S 6 +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_W 2 +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_M 0x000000C0 +#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_S 6 // Field: [5:3] DCDC_LOW_EN_SEL // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_W 3 -#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_M 0x00000038 -#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_S 3 +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_W 3 +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_M 0x00000038 +#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_S 3 // Field: [2:0] DCDC_HIGH_EN_SEL // // Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_W 3 -#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_M 0x00000007 -#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_S 0 +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_W 3 +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_M 0x00000007 +#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_S 0 //***************************************************************************** // @@ -1563,37 +1563,37 @@ // Field: [28:24] VDDR_TRIM_SLEEP // // Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_W 5 -#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M 0x1F000000 -#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S 24 +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_W 5 +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M 0x1F000000 +#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S 24 // Field: [18:16] GLDO_CURSRC // // Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_GLDO_CURSRC_W 3 -#define FCFG1_LDO_TRIM_GLDO_CURSRC_M 0x00070000 -#define FCFG1_LDO_TRIM_GLDO_CURSRC_S 16 +#define FCFG1_LDO_TRIM_GLDO_CURSRC_W 3 +#define FCFG1_LDO_TRIM_GLDO_CURSRC_M 0x00070000 +#define FCFG1_LDO_TRIM_GLDO_CURSRC_S 16 // Field: [12:11] ITRIM_DIGLDO_LOAD // // Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_W 2 -#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_M 0x00001800 -#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_S 11 +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_W 2 +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_M 0x00001800 +#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_S 11 // Field: [10:8] ITRIM_UDIGLDO // // Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_W 3 -#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_M 0x00000700 -#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_S 8 +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_W 3 +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_M 0x00000700 +#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_S 8 // Field: [2:0] VTRIM_DELTA // // Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_VTRIM_DELTA_W 3 -#define FCFG1_LDO_TRIM_VTRIM_DELTA_M 0x00000007 -#define FCFG1_LDO_TRIM_VTRIM_DELTA_S 0 +#define FCFG1_LDO_TRIM_VTRIM_DELTA_W 3 +#define FCFG1_LDO_TRIM_VTRIM_DELTA_M 0x00000007 +#define FCFG1_LDO_TRIM_VTRIM_DELTA_S 0 //***************************************************************************** // @@ -1603,30 +1603,30 @@ // Field: [27:24] VTRIM_BOD // // Internal. Only to be used through TI provided API. -#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_W 4 -#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_M 0x0F000000 -#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_S 24 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_W 4 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_M 0x0F000000 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_S 24 // Field: [19:16] VTRIM_UDIG // // Internal. Only to be used through TI provided API. -#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_W 4 -#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_M 0x000F0000 -#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_S 16 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_W 4 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_M 0x000F0000 +#define FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_S 16 // Field: [11:8] RCOSCHF_ITUNE_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_W 4 -#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_M 0x00000F00 -#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_S 8 +#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_W 4 +#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_M 0x00000F00 +#define FCFG1_BAT_RC_LDO_TRIM_RCOSCHF_ITUNE_TRIM_S 8 // Field: [1:0] MEASUREPER // // Internal. Only to be used through TI provided API. -#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_W 2 -#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_M 0x00000003 -#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_S 0 +#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_W 2 +#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_M 0x00000003 +#define FCFG1_BAT_RC_LDO_TRIM_MEASUREPER_S 0 //***************************************************************************** // @@ -1636,9 +1636,9 @@ // Field: [31:0] ADDR_0_31 // // The first 32-bits of the 64-bit MAC BLE address -#define FCFG1_MAC_BLE_0_ADDR_0_31_W 32 -#define FCFG1_MAC_BLE_0_ADDR_0_31_M 0xFFFFFFFF -#define FCFG1_MAC_BLE_0_ADDR_0_31_S 0 +#define FCFG1_MAC_BLE_0_ADDR_0_31_W 32 +#define FCFG1_MAC_BLE_0_ADDR_0_31_M 0xFFFFFFFF +#define FCFG1_MAC_BLE_0_ADDR_0_31_S 0 //***************************************************************************** // @@ -1648,9 +1648,9 @@ // Field: [31:0] ADDR_32_63 // // The last 32-bits of the 64-bit MAC BLE address -#define FCFG1_MAC_BLE_1_ADDR_32_63_W 32 -#define FCFG1_MAC_BLE_1_ADDR_32_63_M 0xFFFFFFFF -#define FCFG1_MAC_BLE_1_ADDR_32_63_S 0 +#define FCFG1_MAC_BLE_1_ADDR_32_63_W 32 +#define FCFG1_MAC_BLE_1_ADDR_32_63_M 0xFFFFFFFF +#define FCFG1_MAC_BLE_1_ADDR_32_63_S 0 //***************************************************************************** // @@ -1660,9 +1660,9 @@ // Field: [31:0] ADDR_0_31 // // The first 32-bits of the 64-bit MAC 15.4 address -#define FCFG1_MAC_15_4_0_ADDR_0_31_W 32 -#define FCFG1_MAC_15_4_0_ADDR_0_31_M 0xFFFFFFFF -#define FCFG1_MAC_15_4_0_ADDR_0_31_S 0 +#define FCFG1_MAC_15_4_0_ADDR_0_31_W 32 +#define FCFG1_MAC_15_4_0_ADDR_0_31_M 0xFFFFFFFF +#define FCFG1_MAC_15_4_0_ADDR_0_31_S 0 //***************************************************************************** // @@ -1672,9 +1672,9 @@ // Field: [31:0] ADDR_32_63 // // The last 32-bits of the 64-bit MAC 15.4 address -#define FCFG1_MAC_15_4_1_ADDR_32_63_W 32 -#define FCFG1_MAC_15_4_1_ADDR_32_63_M 0xFFFFFFFF -#define FCFG1_MAC_15_4_1_ADDR_32_63_S 0 +#define FCFG1_MAC_15_4_1_ADDR_32_63_W 32 +#define FCFG1_MAC_15_4_1_ADDR_32_63_M 0xFFFFFFFF +#define FCFG1_MAC_15_4_1_ADDR_32_63_S 0 //***************************************************************************** // @@ -1684,154 +1684,154 @@ // Field: [31] STANDBY_MODE_SEL_INT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT 0x80000000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_BITN 31 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M 0x80000000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S 31 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT 0x80000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_BITN 31 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M 0x80000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S 31 // Field: [30:29] STANDBY_PW_SEL_INT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_W 2 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M 0x60000000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S 29 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M 0x60000000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S 29 // Field: [28] DIS_STANDBY_INT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT 0x10000000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_BITN 28 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M 0x10000000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_S 28 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT 0x10000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_BITN 28 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M 0x10000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_S 28 // Field: [27] DIS_IDLE_INT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT 0x08000000 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_BITN 27 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M 0x08000000 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S 27 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT 0x08000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_BITN 27 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M 0x08000000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S 27 // Field: [26:24] VIN_AT_X_INT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_W 3 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M 0x07000000 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S 24 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M 0x07000000 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S 24 // Field: [23] STANDBY_MODE_SEL_EXT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT 0x00800000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_BITN 23 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M 0x00800000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S 23 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT 0x00800000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_BITN 23 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M 0x00800000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S 23 // Field: [22:21] STANDBY_PW_SEL_EXT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_W 2 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M 0x00600000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S 21 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M 0x00600000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S 21 // Field: [20] DIS_STANDBY_EXT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT 0x00100000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_BITN 20 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M 0x00100000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_S 20 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT 0x00100000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_BITN 20 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M 0x00100000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_S 20 // Field: [19] DIS_IDLE_EXT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT 0x00080000 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_BITN 19 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M 0x00080000 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S 19 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT 0x00080000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_BITN 19 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M 0x00080000 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S 19 // Field: [18:16] VIN_AT_X_EXT_WRT // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_W 3 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M 0x00070000 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S 16 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M 0x00070000 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S 16 // Field: [15] STANDBY_MODE_SEL_INT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD 0x00008000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_BITN 15 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M 0x00008000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S 15 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD 0x00008000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_BITN 15 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M 0x00008000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S 15 // Field: [14:13] STANDBY_PW_SEL_INT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_W 2 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M 0x00006000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S 13 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M 0x00006000 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S 13 // Field: [12] DIS_STANDBY_INT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD 0x00001000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_BITN 12 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M 0x00001000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_S 12 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD 0x00001000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_BITN 12 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M 0x00001000 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_S 12 // Field: [11] DIS_IDLE_INT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD 0x00000800 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_BITN 11 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M 0x00000800 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S 11 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD 0x00000800 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_BITN 11 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M 0x00000800 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S 11 // Field: [10:8] VIN_AT_X_INT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_W 3 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M 0x00000700 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S 8 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M 0x00000700 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S 8 // Field: [7] STANDBY_MODE_SEL_EXT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD 0x00000080 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_BITN 7 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M 0x00000080 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S 7 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD 0x00000080 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_BITN 7 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M 0x00000080 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S 7 // Field: [6:5] STANDBY_PW_SEL_EXT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_W 2 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M 0x00000060 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S 5 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_W 2 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M 0x00000060 +#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S 5 // Field: [4] DIS_STANDBY_EXT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD 0x00000010 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_BITN 4 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M 0x00000010 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_S 4 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD 0x00000010 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_BITN 4 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M 0x00000010 +#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_S 4 // Field: [3] DIS_IDLE_EXT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD 0x00000008 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_BITN 3 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M 0x00000008 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S 3 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD 0x00000008 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_BITN 3 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M 0x00000008 +#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S 3 // Field: [2:0] VIN_AT_X_EXT_RD // // Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_W 3 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M 0x00000007 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S 0 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_W 3 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M 0x00000007 +#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S 0 //***************************************************************************** // @@ -1842,9 +1842,9 @@ // // Signed byte value representing the TEMP slope with battery voltage, in // degrees C / V, with four fractional bits. -#define FCFG1_MISC_TRIM_TEMPVSLOPE_W 8 -#define FCFG1_MISC_TRIM_TEMPVSLOPE_M 0x000000FF -#define FCFG1_MISC_TRIM_TEMPVSLOPE_S 0 +#define FCFG1_MISC_TRIM_TEMPVSLOPE_W 8 +#define FCFG1_MISC_TRIM_TEMPVSLOPE_M 0x000000FF +#define FCFG1_MISC_TRIM_TEMPVSLOPE_S 0 //***************************************************************************** // @@ -1854,30 +1854,30 @@ // Field: [31:24] FINE_RESISTOR // // Internal. Only to be used through TI provided API. -#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_W 8 -#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_M 0xFF000000 -#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_S 24 +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_M 0xFF000000 +#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_S 24 // Field: [23:16] CTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_W 8 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_M 0x00FF0000 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_S 16 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_M 0x00FF0000 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_S 16 // Field: [15:8] CTRIMFRACT_QUAD // // Internal. Only to be used through TI provided API. -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_W 8 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_M 0x0000FF00 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_S 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_M 0x0000FF00 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_S 8 // Field: [7:0] CTRIMFRACT_SLOPE // // Internal. Only to be used through TI provided API. -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_W 8 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_M 0x000000FF -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_S 0 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_W 8 +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_M 0x000000FF +#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_S 0 //***************************************************************************** // @@ -1887,16 +1887,16 @@ // Field: [31:16] FT1 // // Internal. Only to be used through TI provided API. -#define FCFG1_TRIM_CAL_REVISION_FT1_W 16 -#define FCFG1_TRIM_CAL_REVISION_FT1_M 0xFFFF0000 -#define FCFG1_TRIM_CAL_REVISION_FT1_S 16 +#define FCFG1_TRIM_CAL_REVISION_FT1_W 16 +#define FCFG1_TRIM_CAL_REVISION_FT1_M 0xFFFF0000 +#define FCFG1_TRIM_CAL_REVISION_FT1_S 16 // Field: [15:0] MP1 // // Internal. Only to be used through TI provided API. -#define FCFG1_TRIM_CAL_REVISION_MP1_W 16 -#define FCFG1_TRIM_CAL_REVISION_MP1_M 0x0000FFFF -#define FCFG1_TRIM_CAL_REVISION_MP1_S 0 +#define FCFG1_TRIM_CAL_REVISION_MP1_W 16 +#define FCFG1_TRIM_CAL_REVISION_MP1_M 0x0000FFFF +#define FCFG1_TRIM_CAL_REVISION_MP1_S 0 //***************************************************************************** // @@ -1906,25 +1906,25 @@ // Field: [31:28] PG_REV // // Field used to distinguish revisions of the device. -#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_W 4 -#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_M 0xF0000000 -#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_S 28 +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_W 4 +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_M 0xF0000000 +#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_S 28 // Field: [27:12] WAFER_ID // // Field used to identify silicon die. -#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_W 16 -#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M 0x0FFFF000 -#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S 12 +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_W 16 +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M 0x0FFFF000 +#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S 12 // Field: [11:0] MANUFACTURER_ID // // Manufacturer code. // // 0x02F: Texas Instruments -#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_W 12 -#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_M 0x00000FFF -#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_S 0 +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_W 12 +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_M 0x00000FFF +#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_S 0 //***************************************************************************** // @@ -1939,9 +1939,9 @@ // to be produced if the FCFG1 layout has changed since the previous production // of devices. // Value migth change without warning. -#define FCFG1_FCFG1_REVISION_REV_W 32 -#define FCFG1_FCFG1_REVISION_REV_M 0xFFFFFFFF -#define FCFG1_FCFG1_REVISION_REV_S 0 +#define FCFG1_FCFG1_REVISION_REV_W 32 +#define FCFG1_FCFG1_REVISION_REV_M 0xFFFFFFFF +#define FCFG1_FCFG1_REVISION_REV_S 0 //***************************************************************************** // @@ -1951,46 +1951,46 @@ // Field: [31:28] RCOSC_HF_ITUNE // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_W 4 -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_M 0xF0000000 -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_S 28 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_W 4 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_M 0xF0000000 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_S 28 // Field: [27:20] RCOSC_HF_CRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_W 8 -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_M 0x0FF00000 -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_S 20 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_W 8 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_M 0x0FF00000 +#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_S 20 // Field: [19:15] PER_M // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_PER_M_W 5 -#define FCFG1_MISC_OTP_DATA_PER_M_M 0x000F8000 -#define FCFG1_MISC_OTP_DATA_PER_M_S 15 +#define FCFG1_MISC_OTP_DATA_PER_M_W 5 +#define FCFG1_MISC_OTP_DATA_PER_M_M 0x000F8000 +#define FCFG1_MISC_OTP_DATA_PER_M_S 15 // Field: [14:12] PER_E // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_PER_E_W 3 -#define FCFG1_MISC_OTP_DATA_PER_E_M 0x00007000 -#define FCFG1_MISC_OTP_DATA_PER_E_S 12 +#define FCFG1_MISC_OTP_DATA_PER_E_W 3 +#define FCFG1_MISC_OTP_DATA_PER_E_M 0x00007000 +#define FCFG1_MISC_OTP_DATA_PER_E_S 12 // Field: [11:8] PO_TAIL_RES_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_PO_TAIL_RES_TRIM_W 4 -#define FCFG1_MISC_OTP_DATA_PO_TAIL_RES_TRIM_M 0x00000F00 -#define FCFG1_MISC_OTP_DATA_PO_TAIL_RES_TRIM_S 8 +#define FCFG1_MISC_OTP_DATA_PO_TAIL_RES_TRIM_W 4 +#define FCFG1_MISC_OTP_DATA_PO_TAIL_RES_TRIM_M 0x00000F00 +#define FCFG1_MISC_OTP_DATA_PO_TAIL_RES_TRIM_S 8 // Field: [7:0] TEST_PROGRAM_REV // // The revision of the test program used in the production process when FCFG1 // was programmed. // Value migth change without warning. -#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_W 8 -#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_M 0x000000FF -#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_S 0 +#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_W 8 +#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_M 0x000000FF +#define FCFG1_MISC_OTP_DATA_TEST_PROGRAM_REV_S 0 //***************************************************************************** // @@ -2000,9 +2000,9 @@ // Field: [6:0] GPIO_CNT // // Number of available DIOs. -#define FCFG1_IOCONF_GPIO_CNT_W 7 -#define FCFG1_IOCONF_GPIO_CNT_M 0x0000007F -#define FCFG1_IOCONF_GPIO_CNT_S 0 +#define FCFG1_IOCONF_GPIO_CNT_W 7 +#define FCFG1_IOCONF_GPIO_CNT_M 0x0000007F +#define FCFG1_IOCONF_GPIO_CNT_S 0 //***************************************************************************** // @@ -2012,58 +2012,58 @@ // Field: [31:28] FF2ADJ // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_FF2ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_FF2ADJ_M 0xF0000000 -#define FCFG1_CONFIG_IF_ADC_FF2ADJ_S 28 +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_M 0xF0000000 +#define FCFG1_CONFIG_IF_ADC_FF2ADJ_S 28 // Field: [27:24] FF3ADJ // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_FF3ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_FF3ADJ_M 0x0F000000 -#define FCFG1_CONFIG_IF_ADC_FF3ADJ_S 24 +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_M 0x0F000000 +#define FCFG1_CONFIG_IF_ADC_FF3ADJ_S 24 // Field: [23:20] INT3ADJ // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_INT3ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_INT3ADJ_M 0x00F00000 -#define FCFG1_CONFIG_IF_ADC_INT3ADJ_S 20 +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_M 0x00F00000 +#define FCFG1_CONFIG_IF_ADC_INT3ADJ_S 20 // Field: [19:16] FF1ADJ // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_FF1ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_FF1ADJ_M 0x000F0000 -#define FCFG1_CONFIG_IF_ADC_FF1ADJ_S 16 +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_M 0x000F0000 +#define FCFG1_CONFIG_IF_ADC_FF1ADJ_S 16 // Field: [15:14] AAFCAP // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_AAFCAP_W 2 -#define FCFG1_CONFIG_IF_ADC_AAFCAP_M 0x0000C000 -#define FCFG1_CONFIG_IF_ADC_AAFCAP_S 14 +#define FCFG1_CONFIG_IF_ADC_AAFCAP_W 2 +#define FCFG1_CONFIG_IF_ADC_AAFCAP_M 0x0000C000 +#define FCFG1_CONFIG_IF_ADC_AAFCAP_S 14 // Field: [13:10] INT2ADJ // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_INT2ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_INT2ADJ_M 0x00003C00 -#define FCFG1_CONFIG_IF_ADC_INT2ADJ_S 10 +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_W 4 +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_M 0x00003C00 +#define FCFG1_CONFIG_IF_ADC_INT2ADJ_S 10 // Field: [9:5] IFDIGLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_W 5 -#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_M 0x000003E0 -#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_S 5 +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_W 5 +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_M 0x000003E0 +#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_S 5 // Field: [4:0] IFANALDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_W 5 -#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_M 0x0000001F -#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_W 5 +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_M 0x0000001F +#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -2073,30 +2073,30 @@ // Field: [29:26] XOSC_HF_ROW_Q12 // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_W 4 -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M 0x3C000000 -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S 26 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_W 4 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M 0x3C000000 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S 26 // Field: [25:10] XOSC_HF_COLUMN_Q12 // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_W 16 -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M 0x03FFFC00 -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S 10 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_W 16 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M 0x03FFFC00 +#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S 10 // Field: [9:2] RCOSCLF_CTUNE_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_W 8 -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M 0x000003FC -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S 2 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_W 8 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M 0x000003FC +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S 2 // Field: [1:0] RCOSCLF_RTUNE_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_W 2 -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M 0x00000003 -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S 0 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_W 2 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M 0x00000003 +#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S 0 //***************************************************************************** // @@ -2106,45 +2106,45 @@ // Field: [31:28] IFAMP_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_S 28 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_M 0xF0000000 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_IB_S 28 // Field: [27:24] LNA_IB // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_W 4 -#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_S 24 +#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_W 4 +#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_M 0x0F000000 +#define FCFG1_CONFIG_RF_FRONTEND_LNA_IB_S 24 // Field: [23:19] IFAMP_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_S 19 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_M 0x00F80000 +#define FCFG1_CONFIG_RF_FRONTEND_IFAMP_TRIM_S 19 // Field: [18:14] CTL_PA0_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_S 14 +#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_W 5 +#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_M 0x0007C000 +#define FCFG1_CONFIG_RF_FRONTEND_CTL_PA0_TRIM_S 14 // Field: [13] PATRIMCOMPLETE_N // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N 0x00002000 -#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_BITN 13 -#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_M 0x00002000 -#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_S 13 +#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N 0x00002000 +#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_BITN 13 +#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_M 0x00002000 +#define FCFG1_CONFIG_RF_FRONTEND_PATRIMCOMPLETE_N_S 13 // Field: [6:0] RFLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_M 0x0000007F -#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_W 7 +#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_M 0x0000007F +#define FCFG1_CONFIG_RF_FRONTEND_RFLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -2154,23 +2154,23 @@ // Field: [27:12] RFC_MDM_DEMIQMC0 // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_S 12 +#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_W 16 +#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_M 0x0FFFF000 +#define FCFG1_CONFIG_SYNTH_RFC_MDM_DEMIQMC0_S 12 // Field: [11:6] LDOVCO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_S 6 +#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 +#define FCFG1_CONFIG_SYNTH_LDOVCO_TRIM_OUTPUT_S 6 // Field: [5:0] SLDO_TRIM_OUTPUT // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_M 0x0000003F -#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_S 0 +#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_W 6 +#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_M 0x0000003F +#define FCFG1_CONFIG_SYNTH_SLDO_TRIM_OUTPUT_S 0 //***************************************************************************** // @@ -2181,9 +2181,9 @@ // // SOC_ADC gain in absolute reference mode at temperature 1 (30C). Calculated // in production test.. -#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_W 16 -#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M 0x0000FFFF -#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S 0 +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_W 16 +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M 0x0000FFFF +#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S 0 //***************************************************************************** // @@ -2194,9 +2194,9 @@ // // SOC_ADC gain in relative reference mode at temperature 1 (30C). Calculated // in production test.. -#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_W 16 -#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M 0x0000FFFF -#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S 0 +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_W 16 +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M 0x0000FFFF +#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S 0 //***************************************************************************** // @@ -2207,17 +2207,17 @@ // // SOC_ADC offset in relative reference mode at temperature 1 (30C). Signed // 8-bit number. Calculated in production test.. -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_W 8 -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_M 0x00FF0000 -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S 16 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_W 8 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_M 0x00FF0000 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S 16 // Field: [7:0] SOC_ADC_ABS_OFFSET_TEMP1 // // SOC_ADC offset in absolute reference mode at temperature 1 (30C). Signed // 8-bit number. Calculated in production test.. -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_W 8 -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_M 0x000000FF -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S 0 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_W 8 +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_M 0x000000FF +#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S 0 //***************************************************************************** // @@ -2242,30 +2242,30 @@ // Field: [23:18] HPMRAMP3_LTH // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_W 6 -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M 0x00FC0000 -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S 18 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M 0x00FC0000 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S 18 // Field: [15:10] HPMRAMP3_HTH // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_W 6 -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M 0x0000FC00 -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S 10 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M 0x0000FC00 +#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S 10 // Field: [9:6] IBIASCAP_LPTOHP_OL_CNT // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_W 4 -#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 -#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S 6 +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_W 4 +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 +#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S 6 // Field: [5:0] HPMRAMP1_TH // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_W 6 -#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M 0x0000003F -#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S 0 +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_W 6 +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M 0x0000003F +#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S 0 //***************************************************************************** // @@ -2275,30 +2275,30 @@ // Field: [31:26] LPMUPDATE_LTH // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_W 6 -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M 0xFC000000 -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S 26 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_W 6 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M 0xFC000000 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S 26 // Field: [23:18] LPMUPDATE_HTM // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_W 6 -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M 0x00FC0000 -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S 18 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_W 6 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M 0x00FC0000 +#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S 18 // Field: [15:10] ADC_COMP_AMPTH_LPM // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_W 6 -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S 10 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_W 6 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S 10 // Field: [7:2] ADC_COMP_AMPTH_HPM // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_W 6 -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M 0x000000FC -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S 2 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_W 6 +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M 0x000000FC +#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S 2 //***************************************************************************** // @@ -2308,45 +2308,45 @@ // Field: [30] AMPCOMP_REQ_MODE // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE 0x40000000 -#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_BITN 30 -#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M 0x40000000 -#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S 30 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE 0x40000000 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_BITN 30 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M 0x40000000 +#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S 30 // Field: [23:20] IBIAS_OFFSET // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_W 4 -#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M 0x00F00000 -#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S 20 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M 0x00F00000 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S 20 // Field: [19:16] IBIAS_INIT // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_W 4 -#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M 0x000F0000 -#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S 16 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M 0x000F0000 +#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S 16 // Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_W 8 -#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 -#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S 8 +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_W 8 +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 +#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S 8 // Field: [7:4] CAP_STEP // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_W 4 -#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_M 0x000000F0 -#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_S 4 +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_W 4 +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_M 0x000000F0 +#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_S 4 // Field: [3:0] IBIASCAP_HPTOLP_OL_CNT // // Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_W 4 -#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F -#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S 0 +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_W 4 +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F +#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S 0 //***************************************************************************** // @@ -2356,9 +2356,9 @@ // Field: [13:0] XOSC_HF_IBIASTHERM // // Internal. Only to be used through TI provided API. -#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_W 14 -#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M 0x00003FFF -#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S 0 +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_W 14 +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M 0x00003FFF +#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S 0 //***************************************************************************** // @@ -2368,31 +2368,31 @@ // Field: [17] RSSITRIMCOMPLETE_N // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N 0x00020000 -#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_BITN 17 -#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_M 0x00020000 -#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_S 17 +#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N 0x00020000 +#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_BITN 17 +#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_M 0x00020000 +#define FCFG1_CONFIG_MISC_ADC_RSSITRIMCOMPLETE_N_S 17 // Field: [16:9] RSSI_OFFSET // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_M 0x0001FE00 -#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_S 9 +#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_W 8 +#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_M 0x0001FE00 +#define FCFG1_CONFIG_MISC_ADC_RSSI_OFFSET_S 9 // Field: [8:6] QUANTCTLTHRES // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_S 6 +#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_W 3 +#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_M 0x000001C0 +#define FCFG1_CONFIG_MISC_ADC_QUANTCTLTHRES_S 6 // Field: [5:0] DACTRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_MISC_ADC_DACTRIM_W 6 -#define FCFG1_CONFIG_MISC_ADC_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_MISC_ADC_DACTRIM_S 0 +#define FCFG1_CONFIG_MISC_ADC_DACTRIM_W 6 +#define FCFG1_CONFIG_MISC_ADC_DACTRIM_M 0x0000003F +#define FCFG1_CONFIG_MISC_ADC_DACTRIM_S 0 //***************************************************************************** // @@ -2402,30 +2402,30 @@ // Field: [28:24] VDDR_TRIM_HH // // Internal. Only to be used through TI provided API. -#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_W 5 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M 0x1F000000 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S 24 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M 0x1F000000 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S 24 // Field: [20:16] VDDR_TRIM_H // // Internal. Only to be used through TI provided API. -#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_W 5 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_M 0x001F0000 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_S 16 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_M 0x001F0000 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_S 16 // Field: [12:8] VDDR_TRIM_SLEEP_H // // Internal. Only to be used through TI provided API. -#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_W 5 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_M 0x00001F00 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_S 8 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_W 5 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_M 0x00001F00 +#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_S 8 // Field: [4:0] TRIMBOD_H // // Internal. Only to be used through TI provided API. -#define FCFG1_VOLT_TRIM_TRIMBOD_H_W 5 -#define FCFG1_VOLT_TRIM_TRIMBOD_H_M 0x0000001F -#define FCFG1_VOLT_TRIM_TRIMBOD_H_S 0 +#define FCFG1_VOLT_TRIM_TRIMBOD_H_W 5 +#define FCFG1_VOLT_TRIM_TRIMBOD_H_M 0x0000001F +#define FCFG1_VOLT_TRIM_TRIMBOD_H_S 0 //***************************************************************************** // @@ -2435,116 +2435,116 @@ // Field: [29] ADC_SH_VBUF_EN // // Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN. -#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN 0x20000000 -#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_BITN 29 -#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M 0x20000000 -#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S 29 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN 0x20000000 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_BITN 29 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M 0x20000000 +#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S 29 // Field: [28] ADC_SH_MODE_EN // // Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN. -#define FCFG1_OSC_CONF_ADC_SH_MODE_EN 0x10000000 -#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_BITN 28 -#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_M 0x10000000 -#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_S 28 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN 0x10000000 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_BITN 28 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_M 0x10000000 +#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_S 28 // Field: [27] ATESTLF_RCOSCLF_IBIAS_TRIM // // Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM. -#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM 0x08000000 -#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_BITN 27 -#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M 0x08000000 -#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S 27 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM 0x08000000 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_BITN 27 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M 0x08000000 +#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S 27 // Field: [26:25] XOSCLF_REGULATOR_TRIM // // Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM. -#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_W 2 -#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M 0x06000000 -#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_S 25 +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_W 2 +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M 0x06000000 +#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_S 25 // Field: [24:21] XOSCLF_CMIRRWR_RATIO // // Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO. -#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_W 4 -#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M 0x01E00000 -#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S 21 +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_W 4 +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M 0x01E00000 +#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S 21 // Field: [20:19] XOSC_HF_FAST_START // // Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START. -#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_W 2 -#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_M 0x00180000 -#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_S 19 +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_W 2 +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_M 0x00180000 +#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_S 19 // Field: [18] XOSC_OPTION // // 0: XOSC_HF unavailable (may not be bonded out) // 1: XOSC_HF available (default) -#define FCFG1_OSC_CONF_XOSC_OPTION 0x00040000 -#define FCFG1_OSC_CONF_XOSC_OPTION_BITN 18 -#define FCFG1_OSC_CONF_XOSC_OPTION_M 0x00040000 -#define FCFG1_OSC_CONF_XOSC_OPTION_S 18 +#define FCFG1_OSC_CONF_XOSC_OPTION 0x00040000 +#define FCFG1_OSC_CONF_XOSC_OPTION_BITN 18 +#define FCFG1_OSC_CONF_XOSC_OPTION_M 0x00040000 +#define FCFG1_OSC_CONF_XOSC_OPTION_S 18 // Field: [17] HPOSC_OPTION // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_OPTION 0x00020000 -#define FCFG1_OSC_CONF_HPOSC_OPTION_BITN 17 -#define FCFG1_OSC_CONF_HPOSC_OPTION_M 0x00020000 -#define FCFG1_OSC_CONF_HPOSC_OPTION_S 17 +#define FCFG1_OSC_CONF_HPOSC_OPTION 0x00020000 +#define FCFG1_OSC_CONF_HPOSC_OPTION_BITN 17 +#define FCFG1_OSC_CONF_HPOSC_OPTION_M 0x00020000 +#define FCFG1_OSC_CONF_HPOSC_OPTION_S 17 // Field: [16] HPOSC_BIAS_HOLD_MODE_EN // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN 0x00010000 -#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_BITN 16 -#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M 0x00010000 -#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S 16 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN 0x00010000 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_BITN 16 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M 0x00010000 +#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S 16 // Field: [15:12] HPOSC_CURRMIRR_RATIO // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_W 4 -#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M 0x0000F000 -#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S 12 +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_W 4 +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M 0x0000F000 +#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S 12 // Field: [11:8] HPOSC_BIAS_RES_SET // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_W 4 -#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M 0x00000F00 -#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S 8 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_W 4 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M 0x00000F00 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S 8 // Field: [7] HPOSC_FILTER_EN // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_FILTER_EN 0x00000080 -#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_BITN 7 -#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_M 0x00000080 -#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_S 7 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN 0x00000080 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_BITN 7 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_M 0x00000080 +#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_S 7 // Field: [6:5] HPOSC_BIAS_RECHARGE_DELAY // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_W 2 -#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M 0x00000060 -#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S 5 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_W 2 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M 0x00000060 +#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S 5 // Field: [2:1] HPOSC_SERIES_CAP // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_W 2 -#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M 0x00000006 -#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S 1 +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_W 2 +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M 0x00000006 +#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S 1 // Field: [0] HPOSC_DIV3_BYPASS // // Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS 0x00000001 -#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_BITN 0 -#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M 0x00000001 -#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S 0 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS 0x00000001 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_BITN 0 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M 0x00000001 +#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S 0 //***************************************************************************** // @@ -2554,23 +2554,23 @@ // Field: [31:16] HPOSC_COMP_P0 // // Internal. Only to be used through TI provided API. -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W 16 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_M 0xFFFF0000 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S 16 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W 16 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_M 0xFFFF0000 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S 16 // Field: [15:8] HPOSC_COMP_P1 // // Internal. Only to be used through TI provided API. -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W 8 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_M 0x0000FF00 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S 8 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W 8 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_M 0x0000FF00 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S 8 // Field: [7:0] HPOSC_COMP_P2 // // Internal. Only to be used through TI provided API. -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W 8 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_M 0x000000FF -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S 0 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W 8 +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_M 0x000000FF +#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S 0 //***************************************************************************** // @@ -2580,16 +2580,16 @@ // Field: [31:16] FLUX_CAP_0P28_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_W 16 -#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_M 0xFFFF0000 -#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_S 16 +#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_W 16 +#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_M 0xFFFF0000 +#define FCFG1_CAP_TRIM_FLUX_CAP_0P28_TRIM_S 16 // Field: [15:0] FLUX_CAP_0P4_TRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_W 16 -#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_M 0x0000FFFF -#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_S 0 +#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_W 16 +#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_M 0x0000FFFF +#define FCFG1_CAP_TRIM_FLUX_CAP_0P4_TRIM_S 0 //***************************************************************************** // @@ -2599,51 +2599,51 @@ // Field: [28:27] PEAK_DET_ITRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_W 2 -#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M 0x18000000 -#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S 27 +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_W 2 +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M 0x18000000 +#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S 27 // Field: [26:24] HP_BUF_ITRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_W 3 -#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M 0x07000000 -#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S 24 +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_W 3 +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M 0x07000000 +#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S 24 // Field: [23:22] LP_BUF_ITRIM // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_W 2 -#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M 0x00C00000 -#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S 22 +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_W 2 +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M 0x00C00000 +#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S 22 // Field: [21:20] DBLR_LOOP_FILTER_RESET_VOLTAGE // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_W 2 -#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M 0x00300000 -#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S 20 +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_W 2 +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M 0x00300000 +#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S 20 // Field: [19:10] HPM_IBIAS_WAIT_CNT // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_W 10 -#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M 0x000FFC00 -#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S 10 +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_W 10 +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M 0x000FFC00 +#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S 10 // Field: [9:4] LPM_IBIAS_WAIT_CNT // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_W 6 -#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M 0x000003F0 -#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S 4 +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_W 6 +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M 0x000003F0 +#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S 4 // Field: [3:0] IDAC_STEP // // Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_W 4 -#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M 0x0000000F -#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S 0 +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_W 4 +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M 0x0000000F +#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S 0 //***************************************************************************** // @@ -2653,31 +2653,31 @@ // Field: [31:24] DELTA_CACHE_REF // // Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_S 24 +#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_20C_DELTA_CACHE_REF_S 24 // Field: [23:16] DELTA_RFMEM_RET // // Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_S 16 +#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_20C_DELTA_RFMEM_RET_S 16 // Field: [15:8] DELTA_XOSC_LPM // // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power // mode -#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_S 8 +#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_20C_DELTA_XOSC_LPM_S 8 // Field: [7:0] BASELINE // // Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_20C_BASELINE_W 8 -#define FCFG1_PWD_CURR_20C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_20C_BASELINE_S 0 +#define FCFG1_PWD_CURR_20C_BASELINE_W 8 +#define FCFG1_PWD_CURR_20C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_20C_BASELINE_S 0 //***************************************************************************** // @@ -2687,31 +2687,31 @@ // Field: [31:24] DELTA_CACHE_REF // // Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_S 24 +#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_35C_DELTA_CACHE_REF_S 24 // Field: [23:16] DELTA_RFMEM_RET // // Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_S 16 +#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_35C_DELTA_RFMEM_RET_S 16 // Field: [15:8] DELTA_XOSC_LPM // // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power // mode -#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_S 8 +#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_35C_DELTA_XOSC_LPM_S 8 // Field: [7:0] BASELINE // // Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_35C_BASELINE_W 8 -#define FCFG1_PWD_CURR_35C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_35C_BASELINE_S 0 +#define FCFG1_PWD_CURR_35C_BASELINE_W 8 +#define FCFG1_PWD_CURR_35C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_35C_BASELINE_S 0 //***************************************************************************** // @@ -2721,31 +2721,31 @@ // Field: [31:24] DELTA_CACHE_REF // // Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_S 24 +#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_50C_DELTA_CACHE_REF_S 24 // Field: [23:16] DELTA_RFMEM_RET // // Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_S 16 +#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_50C_DELTA_RFMEM_RET_S 16 // Field: [15:8] DELTA_XOSC_LPM // // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power // mode -#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_S 8 +#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_50C_DELTA_XOSC_LPM_S 8 // Field: [7:0] BASELINE // // Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_50C_BASELINE_W 8 -#define FCFG1_PWD_CURR_50C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_50C_BASELINE_S 0 +#define FCFG1_PWD_CURR_50C_BASELINE_W 8 +#define FCFG1_PWD_CURR_50C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_50C_BASELINE_S 0 //***************************************************************************** // @@ -2755,31 +2755,31 @@ // Field: [31:24] DELTA_CACHE_REF // // Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_S 24 +#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_65C_DELTA_CACHE_REF_S 24 // Field: [23:16] DELTA_RFMEM_RET // // Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_S 16 +#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_65C_DELTA_RFMEM_RET_S 16 // Field: [15:8] DELTA_XOSC_LPM // // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power // mode -#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_S 8 +#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_65C_DELTA_XOSC_LPM_S 8 // Field: [7:0] BASELINE // // Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_65C_BASELINE_W 8 -#define FCFG1_PWD_CURR_65C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_65C_BASELINE_S 0 +#define FCFG1_PWD_CURR_65C_BASELINE_W 8 +#define FCFG1_PWD_CURR_65C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_65C_BASELINE_S 0 //***************************************************************************** // @@ -2789,31 +2789,31 @@ // Field: [31:24] DELTA_CACHE_REF // // Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_S 24 +#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_80C_DELTA_CACHE_REF_S 24 // Field: [23:16] DELTA_RFMEM_RET // // Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_S 16 +#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_80C_DELTA_RFMEM_RET_S 16 // Field: [15:8] DELTA_XOSC_LPM // // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power // mode -#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_S 8 +#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_80C_DELTA_XOSC_LPM_S 8 // Field: [7:0] BASELINE // // Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_80C_BASELINE_W 8 -#define FCFG1_PWD_CURR_80C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_80C_BASELINE_S 0 +#define FCFG1_PWD_CURR_80C_BASELINE_W 8 +#define FCFG1_PWD_CURR_80C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_80C_BASELINE_S 0 //***************************************************************************** // @@ -2823,31 +2823,31 @@ // Field: [31:24] DELTA_CACHE_REF // // Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_S 24 +#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_95C_DELTA_CACHE_REF_S 24 // Field: [23:16] DELTA_RFMEM_RET // // Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_S 16 +#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_95C_DELTA_RFMEM_RET_S 16 // Field: [15:8] DELTA_XOSC_LPM // // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power // mode -#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_S 8 +#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_95C_DELTA_XOSC_LPM_S 8 // Field: [7:0] BASELINE // // Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_95C_BASELINE_W 8 -#define FCFG1_PWD_CURR_95C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_95C_BASELINE_S 0 +#define FCFG1_PWD_CURR_95C_BASELINE_W 8 +#define FCFG1_PWD_CURR_95C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_95C_BASELINE_S 0 //***************************************************************************** // @@ -2857,31 +2857,31 @@ // Field: [31:24] DELTA_CACHE_REF // // Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_S 24 +#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_110C_DELTA_CACHE_REF_S 24 // Field: [23:16] DELTA_RFMEM_RET // // Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_S 16 +#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_110C_DELTA_RFMEM_RET_S 16 // Field: [15:8] DELTA_XOSC_LPM // // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power // mode -#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_S 8 +#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_110C_DELTA_XOSC_LPM_S 8 // Field: [7:0] BASELINE // // Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_110C_BASELINE_W 8 -#define FCFG1_PWD_CURR_110C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_110C_BASELINE_S 0 +#define FCFG1_PWD_CURR_110C_BASELINE_W 8 +#define FCFG1_PWD_CURR_110C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_110C_BASELINE_S 0 //***************************************************************************** // @@ -2891,31 +2891,30 @@ // Field: [31:24] DELTA_CACHE_REF // // Additional maximum current, in units of 1uA, with cache retention -#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_W 8 -#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_M 0xFF000000 -#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_S 24 +#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_W 8 +#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_M 0xFF000000 +#define FCFG1_PWD_CURR_125C_DELTA_CACHE_REF_S 24 // Field: [23:16] DELTA_RFMEM_RET // // Additional maximum current, in 1uA units, with RF memory retention -#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_W 8 -#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_M 0x00FF0000 -#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_S 16 +#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_W 8 +#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_M 0x00FF0000 +#define FCFG1_PWD_CURR_125C_DELTA_RFMEM_RET_S 16 // Field: [15:8] DELTA_XOSC_LPM // // Additional maximum current, in units of 1uA, with XOSC_HF on in low-power // mode -#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_W 8 -#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_M 0x0000FF00 -#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_S 8 +#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_W 8 +#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_M 0x0000FF00 +#define FCFG1_PWD_CURR_125C_DELTA_XOSC_LPM_S 8 // Field: [7:0] BASELINE // // Worst-case baseline maximum powerdown current, in units of 0.5uA -#define FCFG1_PWD_CURR_125C_BASELINE_W 8 -#define FCFG1_PWD_CURR_125C_BASELINE_M 0x000000FF -#define FCFG1_PWD_CURR_125C_BASELINE_S 0 - +#define FCFG1_PWD_CURR_125C_BASELINE_W 8 +#define FCFG1_PWD_CURR_125C_BASELINE_M 0x000000FF +#define FCFG1_PWD_CURR_125C_BASELINE_S 0 #endif // __FCFG1__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_flash.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_flash.h index 03ce768..dbaa180 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_flash.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_flash.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_flash_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_flash_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_FLASH_H__ #define __HW_FLASH_H__ @@ -44,373 +44,373 @@ // //***************************************************************************** // FMC and Efuse Status -#define FLASH_O_STAT 0x0000001C +#define FLASH_O_STAT 0x0000001C // Internal -#define FLASH_O_CFG 0x00000024 +#define FLASH_O_CFG 0x00000024 // Internal -#define FLASH_O_SYSCODE_START 0x00000028 +#define FLASH_O_SYSCODE_START 0x00000028 // Internal -#define FLASH_O_FLASH_SIZE 0x0000002C +#define FLASH_O_FLASH_SIZE 0x0000002C // Internal -#define FLASH_O_FWLOCK 0x0000003C +#define FLASH_O_FWLOCK 0x0000003C // Internal -#define FLASH_O_FWFLAG 0x00000040 +#define FLASH_O_FWFLAG 0x00000040 // Internal -#define FLASH_O_EFUSE 0x00001000 +#define FLASH_O_EFUSE 0x00001000 // Internal -#define FLASH_O_EFUSEADDR 0x00001004 +#define FLASH_O_EFUSEADDR 0x00001004 // Internal -#define FLASH_O_DATAUPPER 0x00001008 +#define FLASH_O_DATAUPPER 0x00001008 // Internal -#define FLASH_O_DATALOWER 0x0000100C +#define FLASH_O_DATALOWER 0x0000100C // Internal -#define FLASH_O_EFUSECFG 0x00001010 +#define FLASH_O_EFUSECFG 0x00001010 // Internal -#define FLASH_O_EFUSESTAT 0x00001014 +#define FLASH_O_EFUSESTAT 0x00001014 // Internal -#define FLASH_O_ACC 0x00001018 +#define FLASH_O_ACC 0x00001018 // Internal -#define FLASH_O_BOUNDARY 0x0000101C +#define FLASH_O_BOUNDARY 0x0000101C // Internal -#define FLASH_O_EFUSEFLAG 0x00001020 +#define FLASH_O_EFUSEFLAG 0x00001020 // Internal -#define FLASH_O_EFUSEKEY 0x00001024 +#define FLASH_O_EFUSEKEY 0x00001024 // Internal -#define FLASH_O_EFUSERELEASE 0x00001028 +#define FLASH_O_EFUSERELEASE 0x00001028 // Internal -#define FLASH_O_EFUSEPINS 0x0000102C +#define FLASH_O_EFUSEPINS 0x0000102C // Internal -#define FLASH_O_EFUSECRA 0x00001030 +#define FLASH_O_EFUSECRA 0x00001030 // Internal -#define FLASH_O_EFUSEREAD 0x00001034 +#define FLASH_O_EFUSEREAD 0x00001034 // Internal -#define FLASH_O_EFUSEPROGRAM 0x00001038 +#define FLASH_O_EFUSEPROGRAM 0x00001038 // Internal -#define FLASH_O_EFUSEERROR 0x0000103C +#define FLASH_O_EFUSEERROR 0x0000103C // Internal -#define FLASH_O_SINGLEBIT 0x00001040 +#define FLASH_O_SINGLEBIT 0x00001040 // Internal -#define FLASH_O_TWOBIT 0x00001044 +#define FLASH_O_TWOBIT 0x00001044 // Internal -#define FLASH_O_SELFTESTCYC 0x00001048 +#define FLASH_O_SELFTESTCYC 0x00001048 // Internal -#define FLASH_O_SELFTESTSIGN 0x0000104C +#define FLASH_O_SELFTESTSIGN 0x0000104C // Internal -#define FLASH_O_FRDCTL 0x00002000 +#define FLASH_O_FRDCTL 0x00002000 // Internal -#define FLASH_O_FSPRD 0x00002004 +#define FLASH_O_FSPRD 0x00002004 // Internal -#define FLASH_O_FEDACCTL1 0x00002008 +#define FLASH_O_FEDACCTL1 0x00002008 // Internal -#define FLASH_O_FEDACSTAT 0x0000201C +#define FLASH_O_FEDACSTAT 0x0000201C // Internal -#define FLASH_O_FBPROT 0x00002030 +#define FLASH_O_FBPROT 0x00002030 // Internal -#define FLASH_O_FBSE 0x00002034 +#define FLASH_O_FBSE 0x00002034 // Internal -#define FLASH_O_FBBUSY 0x00002038 +#define FLASH_O_FBBUSY 0x00002038 // Internal -#define FLASH_O_FBAC 0x0000203C +#define FLASH_O_FBAC 0x0000203C // Internal -#define FLASH_O_FBFALLBACK 0x00002040 +#define FLASH_O_FBFALLBACK 0x00002040 // Internal -#define FLASH_O_FBPRDY 0x00002044 +#define FLASH_O_FBPRDY 0x00002044 // Internal -#define FLASH_O_FPAC1 0x00002048 +#define FLASH_O_FPAC1 0x00002048 // Internal -#define FLASH_O_FPAC2 0x0000204C +#define FLASH_O_FPAC2 0x0000204C // Internal -#define FLASH_O_FMAC 0x00002050 +#define FLASH_O_FMAC 0x00002050 // Internal -#define FLASH_O_FMSTAT 0x00002054 +#define FLASH_O_FMSTAT 0x00002054 // Internal -#define FLASH_O_FLOCK 0x00002064 +#define FLASH_O_FLOCK 0x00002064 // Internal -#define FLASH_O_FVREADCT 0x00002080 +#define FLASH_O_FVREADCT 0x00002080 // Internal -#define FLASH_O_FVHVCT1 0x00002084 +#define FLASH_O_FVHVCT1 0x00002084 // Internal -#define FLASH_O_FVHVCT2 0x00002088 +#define FLASH_O_FVHVCT2 0x00002088 // Internal -#define FLASH_O_FVHVCT3 0x0000208C +#define FLASH_O_FVHVCT3 0x0000208C // Internal -#define FLASH_O_FVNVCT 0x00002090 +#define FLASH_O_FVNVCT 0x00002090 // Internal -#define FLASH_O_FVSLP 0x00002094 +#define FLASH_O_FVSLP 0x00002094 // Internal -#define FLASH_O_FVWLCT 0x00002098 +#define FLASH_O_FVWLCT 0x00002098 // Internal -#define FLASH_O_FEFUSECTL 0x0000209C +#define FLASH_O_FEFUSECTL 0x0000209C // Internal -#define FLASH_O_FEFUSESTAT 0x000020A0 +#define FLASH_O_FEFUSESTAT 0x000020A0 // Internal -#define FLASH_O_FEFUSEDATA 0x000020A4 +#define FLASH_O_FEFUSEDATA 0x000020A4 // Internal -#define FLASH_O_FSEQPMP 0x000020A8 +#define FLASH_O_FSEQPMP 0x000020A8 // Internal -#define FLASH_O_FBSTROBES 0x00002100 +#define FLASH_O_FBSTROBES 0x00002100 // Internal -#define FLASH_O_FPSTROBES 0x00002104 +#define FLASH_O_FPSTROBES 0x00002104 // Internal -#define FLASH_O_FBMODE 0x00002108 +#define FLASH_O_FBMODE 0x00002108 // Internal -#define FLASH_O_FTCR 0x0000210C +#define FLASH_O_FTCR 0x0000210C // Internal -#define FLASH_O_FADDR 0x00002110 +#define FLASH_O_FADDR 0x00002110 // Internal -#define FLASH_O_FTCTL 0x0000211C +#define FLASH_O_FTCTL 0x0000211C // Internal -#define FLASH_O_FWPWRITE0 0x00002120 +#define FLASH_O_FWPWRITE0 0x00002120 // Internal -#define FLASH_O_FWPWRITE1 0x00002124 +#define FLASH_O_FWPWRITE1 0x00002124 // Internal -#define FLASH_O_FWPWRITE2 0x00002128 +#define FLASH_O_FWPWRITE2 0x00002128 // Internal -#define FLASH_O_FWPWRITE3 0x0000212C +#define FLASH_O_FWPWRITE3 0x0000212C // Internal -#define FLASH_O_FWPWRITE4 0x00002130 +#define FLASH_O_FWPWRITE4 0x00002130 // Internal -#define FLASH_O_FWPWRITE5 0x00002134 +#define FLASH_O_FWPWRITE5 0x00002134 // Internal -#define FLASH_O_FWPWRITE6 0x00002138 +#define FLASH_O_FWPWRITE6 0x00002138 // Internal -#define FLASH_O_FWPWRITE7 0x0000213C +#define FLASH_O_FWPWRITE7 0x0000213C // Internal -#define FLASH_O_FWPWRITE_ECC 0x00002140 +#define FLASH_O_FWPWRITE_ECC 0x00002140 // Internal -#define FLASH_O_FSWSTAT 0x00002144 +#define FLASH_O_FSWSTAT 0x00002144 // Internal -#define FLASH_O_FSM_GLBCTL 0x00002200 +#define FLASH_O_FSM_GLBCTL 0x00002200 // Internal -#define FLASH_O_FSM_STATE 0x00002204 +#define FLASH_O_FSM_STATE 0x00002204 // Internal -#define FLASH_O_FSM_STAT 0x00002208 +#define FLASH_O_FSM_STAT 0x00002208 // Internal -#define FLASH_O_FSM_CMD 0x0000220C +#define FLASH_O_FSM_CMD 0x0000220C // Internal -#define FLASH_O_FSM_PE_OSU 0x00002210 +#define FLASH_O_FSM_PE_OSU 0x00002210 // Internal -#define FLASH_O_FSM_VSTAT 0x00002214 +#define FLASH_O_FSM_VSTAT 0x00002214 // Internal -#define FLASH_O_FSM_PE_VSU 0x00002218 +#define FLASH_O_FSM_PE_VSU 0x00002218 // Internal -#define FLASH_O_FSM_CMP_VSU 0x0000221C +#define FLASH_O_FSM_CMP_VSU 0x0000221C // Internal -#define FLASH_O_FSM_EX_VAL 0x00002220 +#define FLASH_O_FSM_EX_VAL 0x00002220 // Internal -#define FLASH_O_FSM_RD_H 0x00002224 +#define FLASH_O_FSM_RD_H 0x00002224 // Internal -#define FLASH_O_FSM_P_OH 0x00002228 +#define FLASH_O_FSM_P_OH 0x00002228 // Internal -#define FLASH_O_FSM_ERA_OH 0x0000222C +#define FLASH_O_FSM_ERA_OH 0x0000222C // Internal -#define FLASH_O_FSM_SAV_PPUL 0x00002230 +#define FLASH_O_FSM_SAV_PPUL 0x00002230 // Internal -#define FLASH_O_FSM_PE_VH 0x00002234 +#define FLASH_O_FSM_PE_VH 0x00002234 // Internal -#define FLASH_O_FSM_PRG_PW 0x00002240 +#define FLASH_O_FSM_PRG_PW 0x00002240 // Internal -#define FLASH_O_FSM_ERA_PW 0x00002244 +#define FLASH_O_FSM_ERA_PW 0x00002244 // Internal -#define FLASH_O_FSM_SAV_ERA_PUL 0x00002254 +#define FLASH_O_FSM_SAV_ERA_PUL 0x00002254 // Internal -#define FLASH_O_FSM_TIMER 0x00002258 +#define FLASH_O_FSM_TIMER 0x00002258 // Internal -#define FLASH_O_FSM_MODE 0x0000225C +#define FLASH_O_FSM_MODE 0x0000225C // Internal -#define FLASH_O_FSM_PGM 0x00002260 +#define FLASH_O_FSM_PGM 0x00002260 // Internal -#define FLASH_O_FSM_ERA 0x00002264 +#define FLASH_O_FSM_ERA 0x00002264 // Internal -#define FLASH_O_FSM_PRG_PUL 0x00002268 +#define FLASH_O_FSM_PRG_PUL 0x00002268 // Internal -#define FLASH_O_FSM_ERA_PUL 0x0000226C +#define FLASH_O_FSM_ERA_PUL 0x0000226C // Internal -#define FLASH_O_FSM_STEP_SIZE 0x00002270 +#define FLASH_O_FSM_STEP_SIZE 0x00002270 // Internal -#define FLASH_O_FSM_PUL_CNTR 0x00002274 +#define FLASH_O_FSM_PUL_CNTR 0x00002274 // Internal -#define FLASH_O_FSM_EC_STEP_HEIGHT 0x00002278 +#define FLASH_O_FSM_EC_STEP_HEIGHT 0x00002278 // Internal -#define FLASH_O_FSM_ST_MACHINE 0x0000227C +#define FLASH_O_FSM_ST_MACHINE 0x0000227C // Internal -#define FLASH_O_FSM_FLES 0x00002280 +#define FLASH_O_FSM_FLES 0x00002280 // Internal -#define FLASH_O_FSM_WR_ENA 0x00002288 +#define FLASH_O_FSM_WR_ENA 0x00002288 // Internal -#define FLASH_O_FSM_ACC_PP 0x0000228C +#define FLASH_O_FSM_ACC_PP 0x0000228C // Internal -#define FLASH_O_FSM_ACC_EP 0x00002290 +#define FLASH_O_FSM_ACC_EP 0x00002290 // Internal -#define FLASH_O_FSM_ADDR 0x000022A0 +#define FLASH_O_FSM_ADDR 0x000022A0 // Internal -#define FLASH_O_FSM_SECTOR 0x000022A4 +#define FLASH_O_FSM_SECTOR 0x000022A4 // Internal -#define FLASH_O_FMC_REV_ID 0x000022A8 +#define FLASH_O_FMC_REV_ID 0x000022A8 // Internal -#define FLASH_O_FSM_ERR_ADDR 0x000022AC +#define FLASH_O_FSM_ERR_ADDR 0x000022AC // Internal -#define FLASH_O_FSM_PGM_MAXPUL 0x000022B0 +#define FLASH_O_FSM_PGM_MAXPUL 0x000022B0 // Internal -#define FLASH_O_FSM_EXECUTE 0x000022B4 +#define FLASH_O_FSM_EXECUTE 0x000022B4 // Internal -#define FLASH_O_FSM_SECTOR1 0x000022C0 +#define FLASH_O_FSM_SECTOR1 0x000022C0 // Internal -#define FLASH_O_FSM_SECTOR2 0x000022C4 +#define FLASH_O_FSM_SECTOR2 0x000022C4 // Internal -#define FLASH_O_FSM_BSLE0 0x000022E0 +#define FLASH_O_FSM_BSLE0 0x000022E0 // Internal -#define FLASH_O_FSM_BSLE1 0x000022E4 +#define FLASH_O_FSM_BSLE1 0x000022E4 // Internal -#define FLASH_O_FSM_BSLP0 0x000022F0 +#define FLASH_O_FSM_BSLP0 0x000022F0 // Internal -#define FLASH_O_FSM_BSLP1 0x000022F4 +#define FLASH_O_FSM_BSLP1 0x000022F4 // Internal -#define FLASH_O_FCFG_BANK 0x00002400 +#define FLASH_O_FCFG_BANK 0x00002400 // Internal -#define FLASH_O_FCFG_WRAPPER 0x00002404 +#define FLASH_O_FCFG_WRAPPER 0x00002404 // Internal -#define FLASH_O_FCFG_BNK_TYPE 0x00002408 +#define FLASH_O_FCFG_BNK_TYPE 0x00002408 // Internal -#define FLASH_O_FCFG_B0_START 0x00002410 +#define FLASH_O_FCFG_B0_START 0x00002410 // Internal -#define FLASH_O_FCFG_B1_START 0x00002414 +#define FLASH_O_FCFG_B1_START 0x00002414 // Internal -#define FLASH_O_FCFG_B2_START 0x00002418 +#define FLASH_O_FCFG_B2_START 0x00002418 // Internal -#define FLASH_O_FCFG_B3_START 0x0000241C +#define FLASH_O_FCFG_B3_START 0x0000241C // Internal -#define FLASH_O_FCFG_B4_START 0x00002420 +#define FLASH_O_FCFG_B4_START 0x00002420 // Internal -#define FLASH_O_FCFG_B5_START 0x00002424 +#define FLASH_O_FCFG_B5_START 0x00002424 // Internal -#define FLASH_O_FCFG_B6_START 0x00002428 +#define FLASH_O_FCFG_B6_START 0x00002428 // Internal -#define FLASH_O_FCFG_B7_START 0x0000242C +#define FLASH_O_FCFG_B7_START 0x0000242C // Internal -#define FLASH_O_FCFG_B0_SSIZE0 0x00002430 +#define FLASH_O_FCFG_B0_SSIZE0 0x00002430 //***************************************************************************** // @@ -422,37 +422,37 @@ // Efuse scanning detected if fuse ROM is blank: // 0 : Not blank // 1 : Blank -#define FLASH_STAT_EFUSE_BLANK 0x00008000 -#define FLASH_STAT_EFUSE_BLANK_BITN 15 -#define FLASH_STAT_EFUSE_BLANK_M 0x00008000 -#define FLASH_STAT_EFUSE_BLANK_S 15 +#define FLASH_STAT_EFUSE_BLANK 0x00008000 +#define FLASH_STAT_EFUSE_BLANK_BITN 15 +#define FLASH_STAT_EFUSE_BLANK_M 0x00008000 +#define FLASH_STAT_EFUSE_BLANK_S 15 // Field: [14] EFUSE_TIMEOUT // // Efuse scanning resulted in timeout error. // 0 : No Timeout error // 1 : Timeout Error -#define FLASH_STAT_EFUSE_TIMEOUT 0x00004000 -#define FLASH_STAT_EFUSE_TIMEOUT_BITN 14 -#define FLASH_STAT_EFUSE_TIMEOUT_M 0x00004000 -#define FLASH_STAT_EFUSE_TIMEOUT_S 14 +#define FLASH_STAT_EFUSE_TIMEOUT 0x00004000 +#define FLASH_STAT_EFUSE_TIMEOUT_BITN 14 +#define FLASH_STAT_EFUSE_TIMEOUT_M 0x00004000 +#define FLASH_STAT_EFUSE_TIMEOUT_S 14 // Field: [13] EFUSE_CRC_ERROR // // Efuse scanning resulted in scan chain CRC error. // 0 : No CRC error // 1 : CRC Error -#define FLASH_STAT_EFUSE_CRC_ERROR 0x00002000 -#define FLASH_STAT_EFUSE_CRC_ERROR_BITN 13 -#define FLASH_STAT_EFUSE_CRC_ERROR_M 0x00002000 -#define FLASH_STAT_EFUSE_CRC_ERROR_S 13 +#define FLASH_STAT_EFUSE_CRC_ERROR 0x00002000 +#define FLASH_STAT_EFUSE_CRC_ERROR_BITN 13 +#define FLASH_STAT_EFUSE_CRC_ERROR_M 0x00002000 +#define FLASH_STAT_EFUSE_CRC_ERROR_S 13 // Field: [12:8] EFUSE_ERRCODE // // Same as EFUSEERROR.CODE -#define FLASH_STAT_EFUSE_ERRCODE_W 5 -#define FLASH_STAT_EFUSE_ERRCODE_M 0x00001F00 -#define FLASH_STAT_EFUSE_ERRCODE_S 8 +#define FLASH_STAT_EFUSE_ERRCODE_W 5 +#define FLASH_STAT_EFUSE_ERRCODE_M 0x00001F00 +#define FLASH_STAT_EFUSE_ERRCODE_S 8 // Field: [2] SAMHOLD_DIS // @@ -460,10 +460,10 @@ // to 1 some delay after CFG.DIS_IDLE is set to 1. // 0: Not disabled // 1: Sample and hold disabled and stable -#define FLASH_STAT_SAMHOLD_DIS 0x00000004 -#define FLASH_STAT_SAMHOLD_DIS_BITN 2 -#define FLASH_STAT_SAMHOLD_DIS_M 0x00000004 -#define FLASH_STAT_SAMHOLD_DIS_S 2 +#define FLASH_STAT_SAMHOLD_DIS 0x00000004 +#define FLASH_STAT_SAMHOLD_DIS_BITN 2 +#define FLASH_STAT_SAMHOLD_DIS_M 0x00000004 +#define FLASH_STAT_SAMHOLD_DIS_S 2 // Field: [1] BUSY // @@ -472,20 +472,20 @@ // is delayed some cycles) // 0 : Not busy // 1 : Busy -#define FLASH_STAT_BUSY 0x00000002 -#define FLASH_STAT_BUSY_BITN 1 -#define FLASH_STAT_BUSY_M 0x00000002 -#define FLASH_STAT_BUSY_S 1 +#define FLASH_STAT_BUSY 0x00000002 +#define FLASH_STAT_BUSY_BITN 1 +#define FLASH_STAT_BUSY_M 0x00000002 +#define FLASH_STAT_BUSY_S 1 // Field: [0] POWER_MODE // // Power state of the flash sub-system. // 0 : Active // 1 : Low power -#define FLASH_STAT_POWER_MODE 0x00000001 -#define FLASH_STAT_POWER_MODE_BITN 0 -#define FLASH_STAT_POWER_MODE_M 0x00000001 -#define FLASH_STAT_POWER_MODE_S 0 +#define FLASH_STAT_POWER_MODE 0x00000001 +#define FLASH_STAT_POWER_MODE_BITN 0 +#define FLASH_STAT_POWER_MODE_M 0x00000001 +#define FLASH_STAT_POWER_MODE_S 0 //***************************************************************************** // @@ -495,57 +495,57 @@ // Field: [8] STANDBY_MODE_SEL // // Internal. Only to be used through TI provided API. -#define FLASH_CFG_STANDBY_MODE_SEL 0x00000100 -#define FLASH_CFG_STANDBY_MODE_SEL_BITN 8 -#define FLASH_CFG_STANDBY_MODE_SEL_M 0x00000100 -#define FLASH_CFG_STANDBY_MODE_SEL_S 8 +#define FLASH_CFG_STANDBY_MODE_SEL 0x00000100 +#define FLASH_CFG_STANDBY_MODE_SEL_BITN 8 +#define FLASH_CFG_STANDBY_MODE_SEL_M 0x00000100 +#define FLASH_CFG_STANDBY_MODE_SEL_S 8 // Field: [7:6] STANDBY_PW_SEL // // Internal. Only to be used through TI provided API. -#define FLASH_CFG_STANDBY_PW_SEL_W 2 -#define FLASH_CFG_STANDBY_PW_SEL_M 0x000000C0 -#define FLASH_CFG_STANDBY_PW_SEL_S 6 +#define FLASH_CFG_STANDBY_PW_SEL_W 2 +#define FLASH_CFG_STANDBY_PW_SEL_M 0x000000C0 +#define FLASH_CFG_STANDBY_PW_SEL_S 6 // Field: [5] DIS_EFUSECLK // // Internal. Only to be used through TI provided API. -#define FLASH_CFG_DIS_EFUSECLK 0x00000020 -#define FLASH_CFG_DIS_EFUSECLK_BITN 5 -#define FLASH_CFG_DIS_EFUSECLK_M 0x00000020 -#define FLASH_CFG_DIS_EFUSECLK_S 5 +#define FLASH_CFG_DIS_EFUSECLK 0x00000020 +#define FLASH_CFG_DIS_EFUSECLK_BITN 5 +#define FLASH_CFG_DIS_EFUSECLK_M 0x00000020 +#define FLASH_CFG_DIS_EFUSECLK_S 5 // Field: [4] DIS_READACCESS // // Internal. Only to be used through TI provided API. -#define FLASH_CFG_DIS_READACCESS 0x00000010 -#define FLASH_CFG_DIS_READACCESS_BITN 4 -#define FLASH_CFG_DIS_READACCESS_M 0x00000010 -#define FLASH_CFG_DIS_READACCESS_S 4 +#define FLASH_CFG_DIS_READACCESS 0x00000010 +#define FLASH_CFG_DIS_READACCESS_BITN 4 +#define FLASH_CFG_DIS_READACCESS_M 0x00000010 +#define FLASH_CFG_DIS_READACCESS_S 4 // Field: [3] ENABLE_SWINTF // // Internal. Only to be used through TI provided API. -#define FLASH_CFG_ENABLE_SWINTF 0x00000008 -#define FLASH_CFG_ENABLE_SWINTF_BITN 3 -#define FLASH_CFG_ENABLE_SWINTF_M 0x00000008 -#define FLASH_CFG_ENABLE_SWINTF_S 3 +#define FLASH_CFG_ENABLE_SWINTF 0x00000008 +#define FLASH_CFG_ENABLE_SWINTF_BITN 3 +#define FLASH_CFG_ENABLE_SWINTF_M 0x00000008 +#define FLASH_CFG_ENABLE_SWINTF_S 3 // Field: [1] DIS_STANDBY // // Internal. Only to be used through TI provided API. -#define FLASH_CFG_DIS_STANDBY 0x00000002 -#define FLASH_CFG_DIS_STANDBY_BITN 1 -#define FLASH_CFG_DIS_STANDBY_M 0x00000002 -#define FLASH_CFG_DIS_STANDBY_S 1 +#define FLASH_CFG_DIS_STANDBY 0x00000002 +#define FLASH_CFG_DIS_STANDBY_BITN 1 +#define FLASH_CFG_DIS_STANDBY_M 0x00000002 +#define FLASH_CFG_DIS_STANDBY_S 1 // Field: [0] DIS_IDLE // // Internal. Only to be used through TI provided API. -#define FLASH_CFG_DIS_IDLE 0x00000001 -#define FLASH_CFG_DIS_IDLE_BITN 0 -#define FLASH_CFG_DIS_IDLE_M 0x00000001 -#define FLASH_CFG_DIS_IDLE_S 0 +#define FLASH_CFG_DIS_IDLE 0x00000001 +#define FLASH_CFG_DIS_IDLE_BITN 0 +#define FLASH_CFG_DIS_IDLE_M 0x00000001 +#define FLASH_CFG_DIS_IDLE_S 0 //***************************************************************************** // @@ -555,9 +555,9 @@ // Field: [4:0] SYSCODE_START // // Internal. Only to be used through TI provided API. -#define FLASH_SYSCODE_START_SYSCODE_START_W 5 -#define FLASH_SYSCODE_START_SYSCODE_START_M 0x0000001F -#define FLASH_SYSCODE_START_SYSCODE_START_S 0 +#define FLASH_SYSCODE_START_SYSCODE_START_W 5 +#define FLASH_SYSCODE_START_SYSCODE_START_M 0x0000001F +#define FLASH_SYSCODE_START_SYSCODE_START_S 0 //***************************************************************************** // @@ -567,9 +567,9 @@ // Field: [7:0] SECTORS // // Internal. Only to be used through TI provided API. -#define FLASH_FLASH_SIZE_SECTORS_W 8 -#define FLASH_FLASH_SIZE_SECTORS_M 0x000000FF -#define FLASH_FLASH_SIZE_SECTORS_S 0 +#define FLASH_FLASH_SIZE_SECTORS_W 8 +#define FLASH_FLASH_SIZE_SECTORS_M 0x000000FF +#define FLASH_FLASH_SIZE_SECTORS_S 0 //***************************************************************************** // @@ -579,9 +579,9 @@ // Field: [2:0] FWLOCK // // Internal. Only to be used through TI provided API. -#define FLASH_FWLOCK_FWLOCK_W 3 -#define FLASH_FWLOCK_FWLOCK_M 0x00000007 -#define FLASH_FWLOCK_FWLOCK_S 0 +#define FLASH_FWLOCK_FWLOCK_W 3 +#define FLASH_FWLOCK_FWLOCK_M 0x00000007 +#define FLASH_FWLOCK_FWLOCK_S 0 //***************************************************************************** // @@ -591,9 +591,9 @@ // Field: [2:0] FWFLAG // // Internal. Only to be used through TI provided API. -#define FLASH_FWFLAG_FWFLAG_W 3 -#define FLASH_FWFLAG_FWFLAG_M 0x00000007 -#define FLASH_FWFLAG_FWFLAG_S 0 +#define FLASH_FWFLAG_FWFLAG_W 3 +#define FLASH_FWFLAG_FWFLAG_M 0x00000007 +#define FLASH_FWFLAG_FWFLAG_S 0 //***************************************************************************** // @@ -603,16 +603,16 @@ // Field: [28:24] INSTRUCTION // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSE_INSTRUCTION_W 5 -#define FLASH_EFUSE_INSTRUCTION_M 0x1F000000 -#define FLASH_EFUSE_INSTRUCTION_S 24 +#define FLASH_EFUSE_INSTRUCTION_W 5 +#define FLASH_EFUSE_INSTRUCTION_M 0x1F000000 +#define FLASH_EFUSE_INSTRUCTION_S 24 // Field: [15:0] DUMPWORD // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSE_DUMPWORD_W 16 -#define FLASH_EFUSE_DUMPWORD_M 0x0000FFFF -#define FLASH_EFUSE_DUMPWORD_S 0 +#define FLASH_EFUSE_DUMPWORD_W 16 +#define FLASH_EFUSE_DUMPWORD_M 0x0000FFFF +#define FLASH_EFUSE_DUMPWORD_S 0 //***************************************************************************** // @@ -622,16 +622,16 @@ // Field: [15:11] BLOCK // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEADDR_BLOCK_W 5 -#define FLASH_EFUSEADDR_BLOCK_M 0x0000F800 -#define FLASH_EFUSEADDR_BLOCK_S 11 +#define FLASH_EFUSEADDR_BLOCK_W 5 +#define FLASH_EFUSEADDR_BLOCK_M 0x0000F800 +#define FLASH_EFUSEADDR_BLOCK_S 11 // Field: [10:0] ROW // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEADDR_ROW_W 11 -#define FLASH_EFUSEADDR_ROW_M 0x000007FF -#define FLASH_EFUSEADDR_ROW_S 0 +#define FLASH_EFUSEADDR_ROW_W 11 +#define FLASH_EFUSEADDR_ROW_M 0x000007FF +#define FLASH_EFUSEADDR_ROW_S 0 //***************************************************************************** // @@ -641,33 +641,33 @@ // Field: [7:3] SPARE // // Internal. Only to be used through TI provided API. -#define FLASH_DATAUPPER_SPARE_W 5 -#define FLASH_DATAUPPER_SPARE_M 0x000000F8 -#define FLASH_DATAUPPER_SPARE_S 3 +#define FLASH_DATAUPPER_SPARE_W 5 +#define FLASH_DATAUPPER_SPARE_M 0x000000F8 +#define FLASH_DATAUPPER_SPARE_S 3 // Field: [2] P // // Internal. Only to be used through TI provided API. -#define FLASH_DATAUPPER_P 0x00000004 -#define FLASH_DATAUPPER_P_BITN 2 -#define FLASH_DATAUPPER_P_M 0x00000004 -#define FLASH_DATAUPPER_P_S 2 +#define FLASH_DATAUPPER_P 0x00000004 +#define FLASH_DATAUPPER_P_BITN 2 +#define FLASH_DATAUPPER_P_M 0x00000004 +#define FLASH_DATAUPPER_P_S 2 // Field: [1] R // // Internal. Only to be used through TI provided API. -#define FLASH_DATAUPPER_R 0x00000002 -#define FLASH_DATAUPPER_R_BITN 1 -#define FLASH_DATAUPPER_R_M 0x00000002 -#define FLASH_DATAUPPER_R_S 1 +#define FLASH_DATAUPPER_R 0x00000002 +#define FLASH_DATAUPPER_R_BITN 1 +#define FLASH_DATAUPPER_R_M 0x00000002 +#define FLASH_DATAUPPER_R_S 1 // Field: [0] EEN // // Internal. Only to be used through TI provided API. -#define FLASH_DATAUPPER_EEN 0x00000001 -#define FLASH_DATAUPPER_EEN_BITN 0 -#define FLASH_DATAUPPER_EEN_M 0x00000001 -#define FLASH_DATAUPPER_EEN_S 0 +#define FLASH_DATAUPPER_EEN 0x00000001 +#define FLASH_DATAUPPER_EEN_BITN 0 +#define FLASH_DATAUPPER_EEN_M 0x00000001 +#define FLASH_DATAUPPER_EEN_S 0 //***************************************************************************** // @@ -677,9 +677,9 @@ // Field: [31:0] DATA // // Internal. Only to be used through TI provided API. -#define FLASH_DATALOWER_DATA_W 32 -#define FLASH_DATALOWER_DATA_M 0xFFFFFFFF -#define FLASH_DATALOWER_DATA_S 0 +#define FLASH_DATALOWER_DATA_W 32 +#define FLASH_DATALOWER_DATA_M 0xFFFFFFFF +#define FLASH_DATALOWER_DATA_S 0 //***************************************************************************** // @@ -689,25 +689,25 @@ // Field: [8] IDLEGATING // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSECFG_IDLEGATING 0x00000100 -#define FLASH_EFUSECFG_IDLEGATING_BITN 8 -#define FLASH_EFUSECFG_IDLEGATING_M 0x00000100 -#define FLASH_EFUSECFG_IDLEGATING_S 8 +#define FLASH_EFUSECFG_IDLEGATING 0x00000100 +#define FLASH_EFUSECFG_IDLEGATING_BITN 8 +#define FLASH_EFUSECFG_IDLEGATING_M 0x00000100 +#define FLASH_EFUSECFG_IDLEGATING_S 8 // Field: [4:3] SLAVEPOWER // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSECFG_SLAVEPOWER_W 2 -#define FLASH_EFUSECFG_SLAVEPOWER_M 0x00000018 -#define FLASH_EFUSECFG_SLAVEPOWER_S 3 +#define FLASH_EFUSECFG_SLAVEPOWER_W 2 +#define FLASH_EFUSECFG_SLAVEPOWER_M 0x00000018 +#define FLASH_EFUSECFG_SLAVEPOWER_S 3 // Field: [0] GATING // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSECFG_GATING 0x00000001 -#define FLASH_EFUSECFG_GATING_BITN 0 -#define FLASH_EFUSECFG_GATING_M 0x00000001 -#define FLASH_EFUSECFG_GATING_S 0 +#define FLASH_EFUSECFG_GATING 0x00000001 +#define FLASH_EFUSECFG_GATING_BITN 0 +#define FLASH_EFUSECFG_GATING_M 0x00000001 +#define FLASH_EFUSECFG_GATING_S 0 //***************************************************************************** // @@ -717,10 +717,10 @@ // Field: [0] RESETDONE // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSESTAT_RESETDONE 0x00000001 -#define FLASH_EFUSESTAT_RESETDONE_BITN 0 -#define FLASH_EFUSESTAT_RESETDONE_M 0x00000001 -#define FLASH_EFUSESTAT_RESETDONE_S 0 +#define FLASH_EFUSESTAT_RESETDONE 0x00000001 +#define FLASH_EFUSESTAT_RESETDONE_BITN 0 +#define FLASH_EFUSESTAT_RESETDONE_M 0x00000001 +#define FLASH_EFUSESTAT_RESETDONE_S 0 //***************************************************************************** // @@ -730,9 +730,9 @@ // Field: [23:0] ACCUMULATOR // // Internal. Only to be used through TI provided API. -#define FLASH_ACC_ACCUMULATOR_W 24 -#define FLASH_ACC_ACCUMULATOR_M 0x00FFFFFF -#define FLASH_ACC_ACCUMULATOR_S 0 +#define FLASH_ACC_ACCUMULATOR_W 24 +#define FLASH_ACC_ACCUMULATOR_M 0x00FFFFFF +#define FLASH_ACC_ACCUMULATOR_S 0 //***************************************************************************** // @@ -742,110 +742,110 @@ // Field: [23] DISROW0 // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_DISROW0 0x00800000 -#define FLASH_BOUNDARY_DISROW0_BITN 23 -#define FLASH_BOUNDARY_DISROW0_M 0x00800000 -#define FLASH_BOUNDARY_DISROW0_S 23 +#define FLASH_BOUNDARY_DISROW0 0x00800000 +#define FLASH_BOUNDARY_DISROW0_BITN 23 +#define FLASH_BOUNDARY_DISROW0_M 0x00800000 +#define FLASH_BOUNDARY_DISROW0_S 23 // Field: [22] SPARE // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SPARE 0x00400000 -#define FLASH_BOUNDARY_SPARE_BITN 22 -#define FLASH_BOUNDARY_SPARE_M 0x00400000 -#define FLASH_BOUNDARY_SPARE_S 22 +#define FLASH_BOUNDARY_SPARE 0x00400000 +#define FLASH_BOUNDARY_SPARE_BITN 22 +#define FLASH_BOUNDARY_SPARE_M 0x00400000 +#define FLASH_BOUNDARY_SPARE_S 22 // Field: [21] EFC_SELF_TEST_ERROR // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR 0x00200000 -#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_BITN 21 -#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_M 0x00200000 -#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_S 21 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR 0x00200000 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_BITN 21 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_M 0x00200000 +#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_S 21 // Field: [20] EFC_INSTRUCTION_INFO // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO 0x00100000 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_BITN 20 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_M 0x00100000 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_S 20 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO 0x00100000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_BITN 20 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_M 0x00100000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_S 20 // Field: [19] EFC_INSTRUCTION_ERROR // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR 0x00080000 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_BITN 19 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_M 0x00080000 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_S 19 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR 0x00080000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_BITN 19 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_M 0x00080000 +#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_S 19 // Field: [18] EFC_AUTOLOAD_ERROR // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR 0x00040000 -#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_BITN 18 -#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_M 0x00040000 -#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_S 18 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR 0x00040000 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_BITN 18 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_M 0x00040000 +#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_S 18 // Field: [17:14] OUTPUTENABLE // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_OUTPUTENABLE_W 4 -#define FLASH_BOUNDARY_OUTPUTENABLE_M 0x0003C000 -#define FLASH_BOUNDARY_OUTPUTENABLE_S 14 +#define FLASH_BOUNDARY_OUTPUTENABLE_W 4 +#define FLASH_BOUNDARY_OUTPUTENABLE_M 0x0003C000 +#define FLASH_BOUNDARY_OUTPUTENABLE_S 14 // Field: [13] SYS_ECC_SELF_TEST_EN // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN 0x00002000 -#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_BITN 13 -#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_M 0x00002000 -#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_S 13 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN 0x00002000 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_BITN 13 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_M 0x00002000 +#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_S 13 // Field: [12] SYS_ECC_OVERRIDE_EN // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN 0x00001000 -#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_BITN 12 -#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_M 0x00001000 -#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_S 12 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN 0x00001000 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_BITN 12 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_M 0x00001000 +#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_S 12 // Field: [11] EFC_FDI // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_FDI 0x00000800 -#define FLASH_BOUNDARY_EFC_FDI_BITN 11 -#define FLASH_BOUNDARY_EFC_FDI_M 0x00000800 -#define FLASH_BOUNDARY_EFC_FDI_S 11 +#define FLASH_BOUNDARY_EFC_FDI 0x00000800 +#define FLASH_BOUNDARY_EFC_FDI_BITN 11 +#define FLASH_BOUNDARY_EFC_FDI_M 0x00000800 +#define FLASH_BOUNDARY_EFC_FDI_S 11 // Field: [10] SYS_DIEID_AUTOLOAD_EN // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN 0x00000400 -#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_BITN 10 -#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_M 0x00000400 -#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_S 10 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN 0x00000400 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_BITN 10 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_M 0x00000400 +#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_S 10 // Field: [9:8] SYS_REPAIR_EN // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_REPAIR_EN_W 2 -#define FLASH_BOUNDARY_SYS_REPAIR_EN_M 0x00000300 -#define FLASH_BOUNDARY_SYS_REPAIR_EN_S 8 +#define FLASH_BOUNDARY_SYS_REPAIR_EN_W 2 +#define FLASH_BOUNDARY_SYS_REPAIR_EN_M 0x00000300 +#define FLASH_BOUNDARY_SYS_REPAIR_EN_S 8 // Field: [7:4] SYS_WS_READ_STATES // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_WS_READ_STATES_W 4 -#define FLASH_BOUNDARY_SYS_WS_READ_STATES_M 0x000000F0 -#define FLASH_BOUNDARY_SYS_WS_READ_STATES_S 4 +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_W 4 +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_M 0x000000F0 +#define FLASH_BOUNDARY_SYS_WS_READ_STATES_S 4 // Field: [3:0] INPUTENABLE // // Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_INPUTENABLE_W 4 -#define FLASH_BOUNDARY_INPUTENABLE_M 0x0000000F -#define FLASH_BOUNDARY_INPUTENABLE_S 0 +#define FLASH_BOUNDARY_INPUTENABLE_W 4 +#define FLASH_BOUNDARY_INPUTENABLE_M 0x0000000F +#define FLASH_BOUNDARY_INPUTENABLE_S 0 //***************************************************************************** // @@ -855,10 +855,10 @@ // Field: [0] KEY // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEFLAG_KEY 0x00000001 -#define FLASH_EFUSEFLAG_KEY_BITN 0 -#define FLASH_EFUSEFLAG_KEY_M 0x00000001 -#define FLASH_EFUSEFLAG_KEY_S 0 +#define FLASH_EFUSEFLAG_KEY 0x00000001 +#define FLASH_EFUSEFLAG_KEY_BITN 0 +#define FLASH_EFUSEFLAG_KEY_M 0x00000001 +#define FLASH_EFUSEFLAG_KEY_S 0 //***************************************************************************** // @@ -868,9 +868,9 @@ // Field: [31:0] CODE // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEKEY_CODE_W 32 -#define FLASH_EFUSEKEY_CODE_M 0xFFFFFFFF -#define FLASH_EFUSEKEY_CODE_S 0 +#define FLASH_EFUSEKEY_CODE_W 32 +#define FLASH_EFUSEKEY_CODE_M 0xFFFFFFFF +#define FLASH_EFUSEKEY_CODE_S 0 //***************************************************************************** // @@ -880,44 +880,44 @@ // Field: [31:25] ODPYEAR // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_ODPYEAR_W 7 -#define FLASH_EFUSERELEASE_ODPYEAR_M 0xFE000000 -#define FLASH_EFUSERELEASE_ODPYEAR_S 25 +#define FLASH_EFUSERELEASE_ODPYEAR_W 7 +#define FLASH_EFUSERELEASE_ODPYEAR_M 0xFE000000 +#define FLASH_EFUSERELEASE_ODPYEAR_S 25 // Field: [24:21] ODPMONTH // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_ODPMONTH_W 4 -#define FLASH_EFUSERELEASE_ODPMONTH_M 0x01E00000 -#define FLASH_EFUSERELEASE_ODPMONTH_S 21 +#define FLASH_EFUSERELEASE_ODPMONTH_W 4 +#define FLASH_EFUSERELEASE_ODPMONTH_M 0x01E00000 +#define FLASH_EFUSERELEASE_ODPMONTH_S 21 // Field: [20:16] ODPDAY // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_ODPDAY_W 5 -#define FLASH_EFUSERELEASE_ODPDAY_M 0x001F0000 -#define FLASH_EFUSERELEASE_ODPDAY_S 16 +#define FLASH_EFUSERELEASE_ODPDAY_W 5 +#define FLASH_EFUSERELEASE_ODPDAY_M 0x001F0000 +#define FLASH_EFUSERELEASE_ODPDAY_S 16 // Field: [15:9] EFUSEYEAR // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_EFUSEYEAR_W 7 -#define FLASH_EFUSERELEASE_EFUSEYEAR_M 0x0000FE00 -#define FLASH_EFUSERELEASE_EFUSEYEAR_S 9 +#define FLASH_EFUSERELEASE_EFUSEYEAR_W 7 +#define FLASH_EFUSERELEASE_EFUSEYEAR_M 0x0000FE00 +#define FLASH_EFUSERELEASE_EFUSEYEAR_S 9 // Field: [8:5] EFUSEMONTH // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_EFUSEMONTH_W 4 -#define FLASH_EFUSERELEASE_EFUSEMONTH_M 0x000001E0 -#define FLASH_EFUSERELEASE_EFUSEMONTH_S 5 +#define FLASH_EFUSERELEASE_EFUSEMONTH_W 4 +#define FLASH_EFUSERELEASE_EFUSEMONTH_M 0x000001E0 +#define FLASH_EFUSERELEASE_EFUSEMONTH_S 5 // Field: [4:0] EFUSEDAY // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_EFUSEDAY_W 5 -#define FLASH_EFUSERELEASE_EFUSEDAY_M 0x0000001F -#define FLASH_EFUSERELEASE_EFUSEDAY_S 0 +#define FLASH_EFUSERELEASE_EFUSEDAY_W 5 +#define FLASH_EFUSERELEASE_EFUSEDAY_M 0x0000001F +#define FLASH_EFUSERELEASE_EFUSEDAY_S 0 //***************************************************************************** // @@ -927,96 +927,96 @@ // Field: [15] EFC_SELF_TEST_DONE // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE 0x00008000 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_BITN 15 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_M 0x00008000 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_S 15 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE 0x00008000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_BITN 15 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_M 0x00008000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_S 15 // Field: [14] EFC_SELF_TEST_ERROR // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR 0x00004000 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_BITN 14 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_M 0x00004000 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_S 14 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR 0x00004000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_BITN 14 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_M 0x00004000 +#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_S 14 // Field: [13] SYS_ECC_SELF_TEST_EN // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN 0x00002000 -#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_BITN 13 -#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_M 0x00002000 -#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_S 13 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN 0x00002000 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_BITN 13 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_M 0x00002000 +#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_S 13 // Field: [12] EFC_INSTRUCTION_INFO // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO 0x00001000 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_BITN 12 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_M 0x00001000 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_S 12 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO 0x00001000 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_BITN 12 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_M 0x00001000 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_S 12 // Field: [11] EFC_INSTRUCTION_ERROR // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR 0x00000800 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_BITN 11 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_M 0x00000800 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_S 11 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR 0x00000800 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_BITN 11 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_M 0x00000800 +#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_S 11 // Field: [10] EFC_AUTOLOAD_ERROR // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR 0x00000400 -#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_BITN 10 -#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_M 0x00000400 -#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_S 10 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR 0x00000400 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_BITN 10 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_M 0x00000400 +#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_S 10 // Field: [9] SYS_ECC_OVERRIDE_EN // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN 0x00000200 -#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_BITN 9 -#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_M 0x00000200 -#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_S 9 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN 0x00000200 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_BITN 9 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_M 0x00000200 +#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_S 9 // Field: [8] EFC_READY // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_READY 0x00000100 -#define FLASH_EFUSEPINS_EFC_READY_BITN 8 -#define FLASH_EFUSEPINS_EFC_READY_M 0x00000100 -#define FLASH_EFUSEPINS_EFC_READY_S 8 +#define FLASH_EFUSEPINS_EFC_READY 0x00000100 +#define FLASH_EFUSEPINS_EFC_READY_BITN 8 +#define FLASH_EFUSEPINS_EFC_READY_M 0x00000100 +#define FLASH_EFUSEPINS_EFC_READY_S 8 // Field: [7] EFC_FCLRZ // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_FCLRZ 0x00000080 -#define FLASH_EFUSEPINS_EFC_FCLRZ_BITN 7 -#define FLASH_EFUSEPINS_EFC_FCLRZ_M 0x00000080 -#define FLASH_EFUSEPINS_EFC_FCLRZ_S 7 +#define FLASH_EFUSEPINS_EFC_FCLRZ 0x00000080 +#define FLASH_EFUSEPINS_EFC_FCLRZ_BITN 7 +#define FLASH_EFUSEPINS_EFC_FCLRZ_M 0x00000080 +#define FLASH_EFUSEPINS_EFC_FCLRZ_S 7 // Field: [6] SYS_DIEID_AUTOLOAD_EN // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN 0x00000040 -#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_BITN 6 -#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_M 0x00000040 -#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_S 6 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN 0x00000040 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_BITN 6 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_M 0x00000040 +#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_S 6 // Field: [5:4] SYS_REPAIR_EN // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_REPAIR_EN_W 2 -#define FLASH_EFUSEPINS_SYS_REPAIR_EN_M 0x00000030 -#define FLASH_EFUSEPINS_SYS_REPAIR_EN_S 4 +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_W 2 +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_M 0x00000030 +#define FLASH_EFUSEPINS_SYS_REPAIR_EN_S 4 // Field: [3:0] SYS_WS_READ_STATES // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_W 4 -#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_M 0x0000000F -#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_S 0 +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_W 4 +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_M 0x0000000F +#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_S 0 //***************************************************************************** // @@ -1026,9 +1026,9 @@ // Field: [5:0] DATA // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSECRA_DATA_W 6 -#define FLASH_EFUSECRA_DATA_M 0x0000003F -#define FLASH_EFUSECRA_DATA_S 0 +#define FLASH_EFUSECRA_DATA_W 6 +#define FLASH_EFUSECRA_DATA_M 0x0000003F +#define FLASH_EFUSECRA_DATA_S 0 //***************************************************************************** // @@ -1038,39 +1038,39 @@ // Field: [9:8] DATABIT // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_DATABIT_W 2 -#define FLASH_EFUSEREAD_DATABIT_M 0x00000300 -#define FLASH_EFUSEREAD_DATABIT_S 8 +#define FLASH_EFUSEREAD_DATABIT_W 2 +#define FLASH_EFUSEREAD_DATABIT_M 0x00000300 +#define FLASH_EFUSEREAD_DATABIT_S 8 // Field: [7:4] READCLOCK // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_READCLOCK_W 4 -#define FLASH_EFUSEREAD_READCLOCK_M 0x000000F0 -#define FLASH_EFUSEREAD_READCLOCK_S 4 +#define FLASH_EFUSEREAD_READCLOCK_W 4 +#define FLASH_EFUSEREAD_READCLOCK_M 0x000000F0 +#define FLASH_EFUSEREAD_READCLOCK_S 4 // Field: [3] DEBUG // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_DEBUG 0x00000008 -#define FLASH_EFUSEREAD_DEBUG_BITN 3 -#define FLASH_EFUSEREAD_DEBUG_M 0x00000008 -#define FLASH_EFUSEREAD_DEBUG_S 3 +#define FLASH_EFUSEREAD_DEBUG 0x00000008 +#define FLASH_EFUSEREAD_DEBUG_BITN 3 +#define FLASH_EFUSEREAD_DEBUG_M 0x00000008 +#define FLASH_EFUSEREAD_DEBUG_S 3 // Field: [2] SPARE // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_SPARE 0x00000004 -#define FLASH_EFUSEREAD_SPARE_BITN 2 -#define FLASH_EFUSEREAD_SPARE_M 0x00000004 -#define FLASH_EFUSEREAD_SPARE_S 2 +#define FLASH_EFUSEREAD_SPARE 0x00000004 +#define FLASH_EFUSEREAD_SPARE_BITN 2 +#define FLASH_EFUSEREAD_SPARE_M 0x00000004 +#define FLASH_EFUSEREAD_SPARE_S 2 // Field: [1:0] MARGIN // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_MARGIN_W 2 -#define FLASH_EFUSEREAD_MARGIN_M 0x00000003 -#define FLASH_EFUSEREAD_MARGIN_S 0 +#define FLASH_EFUSEREAD_MARGIN_W 2 +#define FLASH_EFUSEREAD_MARGIN_M 0x00000003 +#define FLASH_EFUSEREAD_MARGIN_S 0 //***************************************************************************** // @@ -1080,39 +1080,39 @@ // Field: [30] COMPAREDISABLE // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_COMPAREDISABLE 0x40000000 -#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_BITN 30 -#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_M 0x40000000 -#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_S 30 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE 0x40000000 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_BITN 30 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_M 0x40000000 +#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_S 30 // Field: [29:14] CLOCKSTALL // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_CLOCKSTALL_W 16 -#define FLASH_EFUSEPROGRAM_CLOCKSTALL_M 0x3FFFC000 -#define FLASH_EFUSEPROGRAM_CLOCKSTALL_S 14 +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_W 16 +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_M 0x3FFFC000 +#define FLASH_EFUSEPROGRAM_CLOCKSTALL_S 14 // Field: [13] VPPTOVDD // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_VPPTOVDD 0x00002000 -#define FLASH_EFUSEPROGRAM_VPPTOVDD_BITN 13 -#define FLASH_EFUSEPROGRAM_VPPTOVDD_M 0x00002000 -#define FLASH_EFUSEPROGRAM_VPPTOVDD_S 13 +#define FLASH_EFUSEPROGRAM_VPPTOVDD 0x00002000 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_BITN 13 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_M 0x00002000 +#define FLASH_EFUSEPROGRAM_VPPTOVDD_S 13 // Field: [12:9] ITERATIONS // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_ITERATIONS_W 4 -#define FLASH_EFUSEPROGRAM_ITERATIONS_M 0x00001E00 -#define FLASH_EFUSEPROGRAM_ITERATIONS_S 9 +#define FLASH_EFUSEPROGRAM_ITERATIONS_W 4 +#define FLASH_EFUSEPROGRAM_ITERATIONS_M 0x00001E00 +#define FLASH_EFUSEPROGRAM_ITERATIONS_S 9 // Field: [8:0] WRITECLOCK // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_WRITECLOCK_W 9 -#define FLASH_EFUSEPROGRAM_WRITECLOCK_M 0x000001FF -#define FLASH_EFUSEPROGRAM_WRITECLOCK_S 0 +#define FLASH_EFUSEPROGRAM_WRITECLOCK_W 9 +#define FLASH_EFUSEPROGRAM_WRITECLOCK_M 0x000001FF +#define FLASH_EFUSEPROGRAM_WRITECLOCK_S 0 //***************************************************************************** // @@ -1122,17 +1122,17 @@ // Field: [5] DONE // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEERROR_DONE 0x00000020 -#define FLASH_EFUSEERROR_DONE_BITN 5 -#define FLASH_EFUSEERROR_DONE_M 0x00000020 -#define FLASH_EFUSEERROR_DONE_S 5 +#define FLASH_EFUSEERROR_DONE 0x00000020 +#define FLASH_EFUSEERROR_DONE_BITN 5 +#define FLASH_EFUSEERROR_DONE_M 0x00000020 +#define FLASH_EFUSEERROR_DONE_S 5 // Field: [4:0] CODE // // Internal. Only to be used through TI provided API. -#define FLASH_EFUSEERROR_CODE_W 5 -#define FLASH_EFUSEERROR_CODE_M 0x0000001F -#define FLASH_EFUSEERROR_CODE_S 0 +#define FLASH_EFUSEERROR_CODE_W 5 +#define FLASH_EFUSEERROR_CODE_M 0x0000001F +#define FLASH_EFUSEERROR_CODE_S 0 //***************************************************************************** // @@ -1142,17 +1142,17 @@ // Field: [31:1] FROMN // // Internal. Only to be used through TI provided API. -#define FLASH_SINGLEBIT_FROMN_W 31 -#define FLASH_SINGLEBIT_FROMN_M 0xFFFFFFFE -#define FLASH_SINGLEBIT_FROMN_S 1 +#define FLASH_SINGLEBIT_FROMN_W 31 +#define FLASH_SINGLEBIT_FROMN_M 0xFFFFFFFE +#define FLASH_SINGLEBIT_FROMN_S 1 // Field: [0] FROM0 // // Internal. Only to be used through TI provided API. -#define FLASH_SINGLEBIT_FROM0 0x00000001 -#define FLASH_SINGLEBIT_FROM0_BITN 0 -#define FLASH_SINGLEBIT_FROM0_M 0x00000001 -#define FLASH_SINGLEBIT_FROM0_S 0 +#define FLASH_SINGLEBIT_FROM0 0x00000001 +#define FLASH_SINGLEBIT_FROM0_BITN 0 +#define FLASH_SINGLEBIT_FROM0_M 0x00000001 +#define FLASH_SINGLEBIT_FROM0_S 0 //***************************************************************************** // @@ -1162,17 +1162,17 @@ // Field: [31:1] FROMN // // Internal. Only to be used through TI provided API. -#define FLASH_TWOBIT_FROMN_W 31 -#define FLASH_TWOBIT_FROMN_M 0xFFFFFFFE -#define FLASH_TWOBIT_FROMN_S 1 +#define FLASH_TWOBIT_FROMN_W 31 +#define FLASH_TWOBIT_FROMN_M 0xFFFFFFFE +#define FLASH_TWOBIT_FROMN_S 1 // Field: [0] FROM0 // // Internal. Only to be used through TI provided API. -#define FLASH_TWOBIT_FROM0 0x00000001 -#define FLASH_TWOBIT_FROM0_BITN 0 -#define FLASH_TWOBIT_FROM0_M 0x00000001 -#define FLASH_TWOBIT_FROM0_S 0 +#define FLASH_TWOBIT_FROM0 0x00000001 +#define FLASH_TWOBIT_FROM0_BITN 0 +#define FLASH_TWOBIT_FROM0_M 0x00000001 +#define FLASH_TWOBIT_FROM0_S 0 //***************************************************************************** // @@ -1182,9 +1182,9 @@ // Field: [31:0] CYCLES // // Internal. Only to be used through TI provided API. -#define FLASH_SELFTESTCYC_CYCLES_W 32 -#define FLASH_SELFTESTCYC_CYCLES_M 0xFFFFFFFF -#define FLASH_SELFTESTCYC_CYCLES_S 0 +#define FLASH_SELFTESTCYC_CYCLES_W 32 +#define FLASH_SELFTESTCYC_CYCLES_M 0xFFFFFFFF +#define FLASH_SELFTESTCYC_CYCLES_S 0 //***************************************************************************** // @@ -1194,9 +1194,9 @@ // Field: [31:0] SIGNATURE // // Internal. Only to be used through TI provided API. -#define FLASH_SELFTESTSIGN_SIGNATURE_W 32 -#define FLASH_SELFTESTSIGN_SIGNATURE_M 0xFFFFFFFF -#define FLASH_SELFTESTSIGN_SIGNATURE_S 0 +#define FLASH_SELFTESTSIGN_SIGNATURE_W 32 +#define FLASH_SELFTESTSIGN_SIGNATURE_M 0xFFFFFFFF +#define FLASH_SELFTESTSIGN_SIGNATURE_S 0 //***************************************************************************** // @@ -1206,9 +1206,9 @@ // Field: [11:8] RWAIT // // Internal. Only to be used through TI provided API. -#define FLASH_FRDCTL_RWAIT_W 4 -#define FLASH_FRDCTL_RWAIT_M 0x00000F00 -#define FLASH_FRDCTL_RWAIT_S 8 +#define FLASH_FRDCTL_RWAIT_W 4 +#define FLASH_FRDCTL_RWAIT_M 0x00000F00 +#define FLASH_FRDCTL_RWAIT_S 8 //***************************************************************************** // @@ -1218,25 +1218,25 @@ // Field: [15:8] RMBSEM // // Internal. Only to be used through TI provided API. -#define FLASH_FSPRD_RMBSEM_W 8 -#define FLASH_FSPRD_RMBSEM_M 0x0000FF00 -#define FLASH_FSPRD_RMBSEM_S 8 +#define FLASH_FSPRD_RMBSEM_W 8 +#define FLASH_FSPRD_RMBSEM_M 0x0000FF00 +#define FLASH_FSPRD_RMBSEM_S 8 // Field: [1] RM1 // // Internal. Only to be used through TI provided API. -#define FLASH_FSPRD_RM1 0x00000002 -#define FLASH_FSPRD_RM1_BITN 1 -#define FLASH_FSPRD_RM1_M 0x00000002 -#define FLASH_FSPRD_RM1_S 1 +#define FLASH_FSPRD_RM1 0x00000002 +#define FLASH_FSPRD_RM1_BITN 1 +#define FLASH_FSPRD_RM1_M 0x00000002 +#define FLASH_FSPRD_RM1_S 1 // Field: [0] RM0 // // Internal. Only to be used through TI provided API. -#define FLASH_FSPRD_RM0 0x00000001 -#define FLASH_FSPRD_RM0_BITN 0 -#define FLASH_FSPRD_RM0_M 0x00000001 -#define FLASH_FSPRD_RM0_S 0 +#define FLASH_FSPRD_RM0 0x00000001 +#define FLASH_FSPRD_RM0_BITN 0 +#define FLASH_FSPRD_RM0_M 0x00000001 +#define FLASH_FSPRD_RM0_S 0 //***************************************************************************** // @@ -1246,10 +1246,10 @@ // Field: [24] SUSP_IGNR // // Internal. Only to be used through TI provided API. -#define FLASH_FEDACCTL1_SUSP_IGNR 0x01000000 -#define FLASH_FEDACCTL1_SUSP_IGNR_BITN 24 -#define FLASH_FEDACCTL1_SUSP_IGNR_M 0x01000000 -#define FLASH_FEDACCTL1_SUSP_IGNR_S 24 +#define FLASH_FEDACCTL1_SUSP_IGNR 0x01000000 +#define FLASH_FEDACCTL1_SUSP_IGNR_BITN 24 +#define FLASH_FEDACCTL1_SUSP_IGNR_M 0x01000000 +#define FLASH_FEDACCTL1_SUSP_IGNR_S 24 //***************************************************************************** // @@ -1259,18 +1259,18 @@ // Field: [25] RVF_INT // // Internal. Only to be used through TI provided API. -#define FLASH_FEDACSTAT_RVF_INT 0x02000000 -#define FLASH_FEDACSTAT_RVF_INT_BITN 25 -#define FLASH_FEDACSTAT_RVF_INT_M 0x02000000 -#define FLASH_FEDACSTAT_RVF_INT_S 25 +#define FLASH_FEDACSTAT_RVF_INT 0x02000000 +#define FLASH_FEDACSTAT_RVF_INT_BITN 25 +#define FLASH_FEDACSTAT_RVF_INT_M 0x02000000 +#define FLASH_FEDACSTAT_RVF_INT_S 25 // Field: [24] FSM_DONE // // Internal. Only to be used through TI provided API. -#define FLASH_FEDACSTAT_FSM_DONE 0x01000000 -#define FLASH_FEDACSTAT_FSM_DONE_BITN 24 -#define FLASH_FEDACSTAT_FSM_DONE_M 0x01000000 -#define FLASH_FEDACSTAT_FSM_DONE_S 24 +#define FLASH_FEDACSTAT_FSM_DONE 0x01000000 +#define FLASH_FEDACSTAT_FSM_DONE_BITN 24 +#define FLASH_FEDACSTAT_FSM_DONE_M 0x01000000 +#define FLASH_FEDACSTAT_FSM_DONE_S 24 //***************************************************************************** // @@ -1280,10 +1280,10 @@ // Field: [0] PROTL1DIS // // Internal. Only to be used through TI provided API. -#define FLASH_FBPROT_PROTL1DIS 0x00000001 -#define FLASH_FBPROT_PROTL1DIS_BITN 0 -#define FLASH_FBPROT_PROTL1DIS_M 0x00000001 -#define FLASH_FBPROT_PROTL1DIS_S 0 +#define FLASH_FBPROT_PROTL1DIS 0x00000001 +#define FLASH_FBPROT_PROTL1DIS_BITN 0 +#define FLASH_FBPROT_PROTL1DIS_M 0x00000001 +#define FLASH_FBPROT_PROTL1DIS_S 0 //***************************************************************************** // @@ -1293,9 +1293,9 @@ // Field: [15:0] BSE // // Internal. Only to be used through TI provided API. -#define FLASH_FBSE_BSE_W 16 -#define FLASH_FBSE_BSE_M 0x0000FFFF -#define FLASH_FBSE_BSE_S 0 +#define FLASH_FBSE_BSE_W 16 +#define FLASH_FBSE_BSE_M 0x0000FFFF +#define FLASH_FBSE_BSE_S 0 //***************************************************************************** // @@ -1305,9 +1305,9 @@ // Field: [7:0] BUSY // // Internal. Only to be used through TI provided API. -#define FLASH_FBBUSY_BUSY_W 8 -#define FLASH_FBBUSY_BUSY_M 0x000000FF -#define FLASH_FBBUSY_BUSY_S 0 +#define FLASH_FBBUSY_BUSY_W 8 +#define FLASH_FBBUSY_BUSY_M 0x000000FF +#define FLASH_FBBUSY_BUSY_S 0 //***************************************************************************** // @@ -1317,24 +1317,24 @@ // Field: [16] OTPPROTDIS // // Internal. Only to be used through TI provided API. -#define FLASH_FBAC_OTPPROTDIS 0x00010000 -#define FLASH_FBAC_OTPPROTDIS_BITN 16 -#define FLASH_FBAC_OTPPROTDIS_M 0x00010000 -#define FLASH_FBAC_OTPPROTDIS_S 16 +#define FLASH_FBAC_OTPPROTDIS 0x00010000 +#define FLASH_FBAC_OTPPROTDIS_BITN 16 +#define FLASH_FBAC_OTPPROTDIS_M 0x00010000 +#define FLASH_FBAC_OTPPROTDIS_S 16 // Field: [15:8] BAGP // // Internal. Only to be used through TI provided API. -#define FLASH_FBAC_BAGP_W 8 -#define FLASH_FBAC_BAGP_M 0x0000FF00 -#define FLASH_FBAC_BAGP_S 8 +#define FLASH_FBAC_BAGP_W 8 +#define FLASH_FBAC_BAGP_M 0x0000FF00 +#define FLASH_FBAC_BAGP_S 8 // Field: [7:0] VREADS // // Internal. Only to be used through TI provided API. -#define FLASH_FBAC_VREADS_W 8 -#define FLASH_FBAC_VREADS_M 0x000000FF -#define FLASH_FBAC_VREADS_S 0 +#define FLASH_FBAC_VREADS_W 8 +#define FLASH_FBAC_VREADS_M 0x000000FF +#define FLASH_FBAC_VREADS_S 0 //***************************************************************************** // @@ -1344,72 +1344,72 @@ // Field: [27:24] FSM_PWRSAV // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_FSM_PWRSAV_W 4 -#define FLASH_FBFALLBACK_FSM_PWRSAV_M 0x0F000000 -#define FLASH_FBFALLBACK_FSM_PWRSAV_S 24 +#define FLASH_FBFALLBACK_FSM_PWRSAV_W 4 +#define FLASH_FBFALLBACK_FSM_PWRSAV_M 0x0F000000 +#define FLASH_FBFALLBACK_FSM_PWRSAV_S 24 // Field: [19:16] REG_PWRSAV // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_REG_PWRSAV_W 4 -#define FLASH_FBFALLBACK_REG_PWRSAV_M 0x000F0000 -#define FLASH_FBFALLBACK_REG_PWRSAV_S 16 +#define FLASH_FBFALLBACK_REG_PWRSAV_W 4 +#define FLASH_FBFALLBACK_REG_PWRSAV_M 0x000F0000 +#define FLASH_FBFALLBACK_REG_PWRSAV_S 16 // Field: [15:14] BANKPWR7 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR7_W 2 -#define FLASH_FBFALLBACK_BANKPWR7_M 0x0000C000 -#define FLASH_FBFALLBACK_BANKPWR7_S 14 +#define FLASH_FBFALLBACK_BANKPWR7_W 2 +#define FLASH_FBFALLBACK_BANKPWR7_M 0x0000C000 +#define FLASH_FBFALLBACK_BANKPWR7_S 14 // Field: [13:12] BANKPWR6 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR6_W 2 -#define FLASH_FBFALLBACK_BANKPWR6_M 0x00003000 -#define FLASH_FBFALLBACK_BANKPWR6_S 12 +#define FLASH_FBFALLBACK_BANKPWR6_W 2 +#define FLASH_FBFALLBACK_BANKPWR6_M 0x00003000 +#define FLASH_FBFALLBACK_BANKPWR6_S 12 // Field: [11:10] BANKPWR5 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR5_W 2 -#define FLASH_FBFALLBACK_BANKPWR5_M 0x00000C00 -#define FLASH_FBFALLBACK_BANKPWR5_S 10 +#define FLASH_FBFALLBACK_BANKPWR5_W 2 +#define FLASH_FBFALLBACK_BANKPWR5_M 0x00000C00 +#define FLASH_FBFALLBACK_BANKPWR5_S 10 // Field: [9:8] BANKPWR4 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR4_W 2 -#define FLASH_FBFALLBACK_BANKPWR4_M 0x00000300 -#define FLASH_FBFALLBACK_BANKPWR4_S 8 +#define FLASH_FBFALLBACK_BANKPWR4_W 2 +#define FLASH_FBFALLBACK_BANKPWR4_M 0x00000300 +#define FLASH_FBFALLBACK_BANKPWR4_S 8 // Field: [7:6] BANKPWR3 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR3_W 2 -#define FLASH_FBFALLBACK_BANKPWR3_M 0x000000C0 -#define FLASH_FBFALLBACK_BANKPWR3_S 6 +#define FLASH_FBFALLBACK_BANKPWR3_W 2 +#define FLASH_FBFALLBACK_BANKPWR3_M 0x000000C0 +#define FLASH_FBFALLBACK_BANKPWR3_S 6 // Field: [5:4] BANKPWR2 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR2_W 2 -#define FLASH_FBFALLBACK_BANKPWR2_M 0x00000030 -#define FLASH_FBFALLBACK_BANKPWR2_S 4 +#define FLASH_FBFALLBACK_BANKPWR2_W 2 +#define FLASH_FBFALLBACK_BANKPWR2_M 0x00000030 +#define FLASH_FBFALLBACK_BANKPWR2_S 4 // Field: [3:2] BANKPWR1 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR1_W 2 -#define FLASH_FBFALLBACK_BANKPWR1_M 0x0000000C -#define FLASH_FBFALLBACK_BANKPWR1_S 2 +#define FLASH_FBFALLBACK_BANKPWR1_W 2 +#define FLASH_FBFALLBACK_BANKPWR1_M 0x0000000C +#define FLASH_FBFALLBACK_BANKPWR1_S 2 // Field: [1:0] BANKPWR0 // // Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR0_W 2 -#define FLASH_FBFALLBACK_BANKPWR0_M 0x00000003 -#define FLASH_FBFALLBACK_BANKPWR0_S 0 +#define FLASH_FBFALLBACK_BANKPWR0_W 2 +#define FLASH_FBFALLBACK_BANKPWR0_M 0x00000003 +#define FLASH_FBFALLBACK_BANKPWR0_S 0 //***************************************************************************** // @@ -1419,26 +1419,26 @@ // Field: [16] BANKBUSY // // Internal. Only to be used through TI provided API. -#define FLASH_FBPRDY_BANKBUSY 0x00010000 -#define FLASH_FBPRDY_BANKBUSY_BITN 16 -#define FLASH_FBPRDY_BANKBUSY_M 0x00010000 -#define FLASH_FBPRDY_BANKBUSY_S 16 +#define FLASH_FBPRDY_BANKBUSY 0x00010000 +#define FLASH_FBPRDY_BANKBUSY_BITN 16 +#define FLASH_FBPRDY_BANKBUSY_M 0x00010000 +#define FLASH_FBPRDY_BANKBUSY_S 16 // Field: [15] PUMPRDY // // Internal. Only to be used through TI provided API. -#define FLASH_FBPRDY_PUMPRDY 0x00008000 -#define FLASH_FBPRDY_PUMPRDY_BITN 15 -#define FLASH_FBPRDY_PUMPRDY_M 0x00008000 -#define FLASH_FBPRDY_PUMPRDY_S 15 +#define FLASH_FBPRDY_PUMPRDY 0x00008000 +#define FLASH_FBPRDY_PUMPRDY_BITN 15 +#define FLASH_FBPRDY_PUMPRDY_M 0x00008000 +#define FLASH_FBPRDY_PUMPRDY_S 15 // Field: [0] BANKRDY // // Internal. Only to be used through TI provided API. -#define FLASH_FBPRDY_BANKRDY 0x00000001 -#define FLASH_FBPRDY_BANKRDY_BITN 0 -#define FLASH_FBPRDY_BANKRDY_M 0x00000001 -#define FLASH_FBPRDY_BANKRDY_S 0 +#define FLASH_FBPRDY_BANKRDY 0x00000001 +#define FLASH_FBPRDY_BANKRDY_BITN 0 +#define FLASH_FBPRDY_BANKRDY_M 0x00000001 +#define FLASH_FBPRDY_BANKRDY_S 0 //***************************************************************************** // @@ -1448,23 +1448,23 @@ // Field: [27:16] PSLEEPTDIS // // Internal. Only to be used through TI provided API. -#define FLASH_FPAC1_PSLEEPTDIS_W 12 -#define FLASH_FPAC1_PSLEEPTDIS_M 0x0FFF0000 -#define FLASH_FPAC1_PSLEEPTDIS_S 16 +#define FLASH_FPAC1_PSLEEPTDIS_W 12 +#define FLASH_FPAC1_PSLEEPTDIS_M 0x0FFF0000 +#define FLASH_FPAC1_PSLEEPTDIS_S 16 // Field: [15:4] PUMPRESET_PW // // Internal. Only to be used through TI provided API. -#define FLASH_FPAC1_PUMPRESET_PW_W 12 -#define FLASH_FPAC1_PUMPRESET_PW_M 0x0000FFF0 -#define FLASH_FPAC1_PUMPRESET_PW_S 4 +#define FLASH_FPAC1_PUMPRESET_PW_W 12 +#define FLASH_FPAC1_PUMPRESET_PW_M 0x0000FFF0 +#define FLASH_FPAC1_PUMPRESET_PW_S 4 // Field: [1:0] PUMPPWR // // Internal. Only to be used through TI provided API. -#define FLASH_FPAC1_PUMPPWR_W 2 -#define FLASH_FPAC1_PUMPPWR_M 0x00000003 -#define FLASH_FPAC1_PUMPPWR_S 0 +#define FLASH_FPAC1_PUMPPWR_W 2 +#define FLASH_FPAC1_PUMPPWR_M 0x00000003 +#define FLASH_FPAC1_PUMPPWR_S 0 //***************************************************************************** // @@ -1474,9 +1474,9 @@ // Field: [15:0] PAGP // // Internal. Only to be used through TI provided API. -#define FLASH_FPAC2_PAGP_W 16 -#define FLASH_FPAC2_PAGP_M 0x0000FFFF -#define FLASH_FPAC2_PAGP_S 0 +#define FLASH_FPAC2_PAGP_W 16 +#define FLASH_FPAC2_PAGP_M 0x0000FFFF +#define FLASH_FPAC2_PAGP_S 0 //***************************************************************************** // @@ -1486,9 +1486,9 @@ // Field: [2:0] BANK // // Internal. Only to be used through TI provided API. -#define FLASH_FMAC_BANK_W 3 -#define FLASH_FMAC_BANK_M 0x00000007 -#define FLASH_FMAC_BANK_S 0 +#define FLASH_FMAC_BANK_W 3 +#define FLASH_FMAC_BANK_M 0x00000007 +#define FLASH_FMAC_BANK_S 0 //***************************************************************************** // @@ -1498,146 +1498,146 @@ // Field: [17] RVSUSP // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_RVSUSP 0x00020000 -#define FLASH_FMSTAT_RVSUSP_BITN 17 -#define FLASH_FMSTAT_RVSUSP_M 0x00020000 -#define FLASH_FMSTAT_RVSUSP_S 17 +#define FLASH_FMSTAT_RVSUSP 0x00020000 +#define FLASH_FMSTAT_RVSUSP_BITN 17 +#define FLASH_FMSTAT_RVSUSP_M 0x00020000 +#define FLASH_FMSTAT_RVSUSP_S 17 // Field: [16] RDVER // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_RDVER 0x00010000 -#define FLASH_FMSTAT_RDVER_BITN 16 -#define FLASH_FMSTAT_RDVER_M 0x00010000 -#define FLASH_FMSTAT_RDVER_S 16 +#define FLASH_FMSTAT_RDVER 0x00010000 +#define FLASH_FMSTAT_RDVER_BITN 16 +#define FLASH_FMSTAT_RDVER_M 0x00010000 +#define FLASH_FMSTAT_RDVER_S 16 // Field: [15] RVF // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_RVF 0x00008000 -#define FLASH_FMSTAT_RVF_BITN 15 -#define FLASH_FMSTAT_RVF_M 0x00008000 -#define FLASH_FMSTAT_RVF_S 15 +#define FLASH_FMSTAT_RVF 0x00008000 +#define FLASH_FMSTAT_RVF_BITN 15 +#define FLASH_FMSTAT_RVF_M 0x00008000 +#define FLASH_FMSTAT_RVF_S 15 // Field: [14] ILA // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_ILA 0x00004000 -#define FLASH_FMSTAT_ILA_BITN 14 -#define FLASH_FMSTAT_ILA_M 0x00004000 -#define FLASH_FMSTAT_ILA_S 14 +#define FLASH_FMSTAT_ILA 0x00004000 +#define FLASH_FMSTAT_ILA_BITN 14 +#define FLASH_FMSTAT_ILA_M 0x00004000 +#define FLASH_FMSTAT_ILA_S 14 // Field: [13] DBF // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_DBF 0x00002000 -#define FLASH_FMSTAT_DBF_BITN 13 -#define FLASH_FMSTAT_DBF_M 0x00002000 -#define FLASH_FMSTAT_DBF_S 13 +#define FLASH_FMSTAT_DBF 0x00002000 +#define FLASH_FMSTAT_DBF_BITN 13 +#define FLASH_FMSTAT_DBF_M 0x00002000 +#define FLASH_FMSTAT_DBF_S 13 // Field: [12] PGV // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_PGV 0x00001000 -#define FLASH_FMSTAT_PGV_BITN 12 -#define FLASH_FMSTAT_PGV_M 0x00001000 -#define FLASH_FMSTAT_PGV_S 12 +#define FLASH_FMSTAT_PGV 0x00001000 +#define FLASH_FMSTAT_PGV_BITN 12 +#define FLASH_FMSTAT_PGV_M 0x00001000 +#define FLASH_FMSTAT_PGV_S 12 // Field: [11] PCV // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_PCV 0x00000800 -#define FLASH_FMSTAT_PCV_BITN 11 -#define FLASH_FMSTAT_PCV_M 0x00000800 -#define FLASH_FMSTAT_PCV_S 11 +#define FLASH_FMSTAT_PCV 0x00000800 +#define FLASH_FMSTAT_PCV_BITN 11 +#define FLASH_FMSTAT_PCV_M 0x00000800 +#define FLASH_FMSTAT_PCV_S 11 // Field: [10] EV // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_EV 0x00000400 -#define FLASH_FMSTAT_EV_BITN 10 -#define FLASH_FMSTAT_EV_M 0x00000400 -#define FLASH_FMSTAT_EV_S 10 +#define FLASH_FMSTAT_EV 0x00000400 +#define FLASH_FMSTAT_EV_BITN 10 +#define FLASH_FMSTAT_EV_M 0x00000400 +#define FLASH_FMSTAT_EV_S 10 // Field: [9] CV // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_CV 0x00000200 -#define FLASH_FMSTAT_CV_BITN 9 -#define FLASH_FMSTAT_CV_M 0x00000200 -#define FLASH_FMSTAT_CV_S 9 +#define FLASH_FMSTAT_CV 0x00000200 +#define FLASH_FMSTAT_CV_BITN 9 +#define FLASH_FMSTAT_CV_M 0x00000200 +#define FLASH_FMSTAT_CV_S 9 // Field: [8] BUSY // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_BUSY 0x00000100 -#define FLASH_FMSTAT_BUSY_BITN 8 -#define FLASH_FMSTAT_BUSY_M 0x00000100 -#define FLASH_FMSTAT_BUSY_S 8 +#define FLASH_FMSTAT_BUSY 0x00000100 +#define FLASH_FMSTAT_BUSY_BITN 8 +#define FLASH_FMSTAT_BUSY_M 0x00000100 +#define FLASH_FMSTAT_BUSY_S 8 // Field: [7] ERS // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_ERS 0x00000080 -#define FLASH_FMSTAT_ERS_BITN 7 -#define FLASH_FMSTAT_ERS_M 0x00000080 -#define FLASH_FMSTAT_ERS_S 7 +#define FLASH_FMSTAT_ERS 0x00000080 +#define FLASH_FMSTAT_ERS_BITN 7 +#define FLASH_FMSTAT_ERS_M 0x00000080 +#define FLASH_FMSTAT_ERS_S 7 // Field: [6] PGM // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_PGM 0x00000040 -#define FLASH_FMSTAT_PGM_BITN 6 -#define FLASH_FMSTAT_PGM_M 0x00000040 -#define FLASH_FMSTAT_PGM_S 6 +#define FLASH_FMSTAT_PGM 0x00000040 +#define FLASH_FMSTAT_PGM_BITN 6 +#define FLASH_FMSTAT_PGM_M 0x00000040 +#define FLASH_FMSTAT_PGM_S 6 // Field: [5] INVDAT // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_INVDAT 0x00000020 -#define FLASH_FMSTAT_INVDAT_BITN 5 -#define FLASH_FMSTAT_INVDAT_M 0x00000020 -#define FLASH_FMSTAT_INVDAT_S 5 +#define FLASH_FMSTAT_INVDAT 0x00000020 +#define FLASH_FMSTAT_INVDAT_BITN 5 +#define FLASH_FMSTAT_INVDAT_M 0x00000020 +#define FLASH_FMSTAT_INVDAT_S 5 // Field: [4] CSTAT // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_CSTAT 0x00000010 -#define FLASH_FMSTAT_CSTAT_BITN 4 -#define FLASH_FMSTAT_CSTAT_M 0x00000010 -#define FLASH_FMSTAT_CSTAT_S 4 +#define FLASH_FMSTAT_CSTAT 0x00000010 +#define FLASH_FMSTAT_CSTAT_BITN 4 +#define FLASH_FMSTAT_CSTAT_M 0x00000010 +#define FLASH_FMSTAT_CSTAT_S 4 // Field: [3] VOLSTAT // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_VOLSTAT 0x00000008 -#define FLASH_FMSTAT_VOLSTAT_BITN 3 -#define FLASH_FMSTAT_VOLSTAT_M 0x00000008 -#define FLASH_FMSTAT_VOLSTAT_S 3 +#define FLASH_FMSTAT_VOLSTAT 0x00000008 +#define FLASH_FMSTAT_VOLSTAT_BITN 3 +#define FLASH_FMSTAT_VOLSTAT_M 0x00000008 +#define FLASH_FMSTAT_VOLSTAT_S 3 // Field: [2] ESUSP // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_ESUSP 0x00000004 -#define FLASH_FMSTAT_ESUSP_BITN 2 -#define FLASH_FMSTAT_ESUSP_M 0x00000004 -#define FLASH_FMSTAT_ESUSP_S 2 +#define FLASH_FMSTAT_ESUSP 0x00000004 +#define FLASH_FMSTAT_ESUSP_BITN 2 +#define FLASH_FMSTAT_ESUSP_M 0x00000004 +#define FLASH_FMSTAT_ESUSP_S 2 // Field: [1] PSUSP // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_PSUSP 0x00000002 -#define FLASH_FMSTAT_PSUSP_BITN 1 -#define FLASH_FMSTAT_PSUSP_M 0x00000002 -#define FLASH_FMSTAT_PSUSP_S 1 +#define FLASH_FMSTAT_PSUSP 0x00000002 +#define FLASH_FMSTAT_PSUSP_BITN 1 +#define FLASH_FMSTAT_PSUSP_M 0x00000002 +#define FLASH_FMSTAT_PSUSP_S 1 // Field: [0] SLOCK // // Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_SLOCK 0x00000001 -#define FLASH_FMSTAT_SLOCK_BITN 0 -#define FLASH_FMSTAT_SLOCK_M 0x00000001 -#define FLASH_FMSTAT_SLOCK_S 0 +#define FLASH_FMSTAT_SLOCK 0x00000001 +#define FLASH_FMSTAT_SLOCK_BITN 0 +#define FLASH_FMSTAT_SLOCK_M 0x00000001 +#define FLASH_FMSTAT_SLOCK_S 0 //***************************************************************************** // @@ -1647,9 +1647,9 @@ // Field: [15:0] ENCOM // // Internal. Only to be used through TI provided API. -#define FLASH_FLOCK_ENCOM_W 16 -#define FLASH_FLOCK_ENCOM_M 0x0000FFFF -#define FLASH_FLOCK_ENCOM_S 0 +#define FLASH_FLOCK_ENCOM_W 16 +#define FLASH_FLOCK_ENCOM_M 0x0000FFFF +#define FLASH_FLOCK_ENCOM_S 0 //***************************************************************************** // @@ -1659,9 +1659,9 @@ // Field: [3:0] VREADCT // // Internal. Only to be used through TI provided API. -#define FLASH_FVREADCT_VREADCT_W 4 -#define FLASH_FVREADCT_VREADCT_M 0x0000000F -#define FLASH_FVREADCT_VREADCT_S 0 +#define FLASH_FVREADCT_VREADCT_W 4 +#define FLASH_FVREADCT_VREADCT_M 0x0000000F +#define FLASH_FVREADCT_VREADCT_S 0 //***************************************************************************** // @@ -1671,30 +1671,30 @@ // Field: [23:20] TRIM13_E // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT1_TRIM13_E_W 4 -#define FLASH_FVHVCT1_TRIM13_E_M 0x00F00000 -#define FLASH_FVHVCT1_TRIM13_E_S 20 +#define FLASH_FVHVCT1_TRIM13_E_W 4 +#define FLASH_FVHVCT1_TRIM13_E_M 0x00F00000 +#define FLASH_FVHVCT1_TRIM13_E_S 20 // Field: [19:16] VHVCT_E // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT1_VHVCT_E_W 4 -#define FLASH_FVHVCT1_VHVCT_E_M 0x000F0000 -#define FLASH_FVHVCT1_VHVCT_E_S 16 +#define FLASH_FVHVCT1_VHVCT_E_W 4 +#define FLASH_FVHVCT1_VHVCT_E_M 0x000F0000 +#define FLASH_FVHVCT1_VHVCT_E_S 16 // Field: [7:4] TRIM13_PV // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT1_TRIM13_PV_W 4 -#define FLASH_FVHVCT1_TRIM13_PV_M 0x000000F0 -#define FLASH_FVHVCT1_TRIM13_PV_S 4 +#define FLASH_FVHVCT1_TRIM13_PV_W 4 +#define FLASH_FVHVCT1_TRIM13_PV_M 0x000000F0 +#define FLASH_FVHVCT1_TRIM13_PV_S 4 // Field: [3:0] VHVCT_PV // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT1_VHVCT_PV_W 4 -#define FLASH_FVHVCT1_VHVCT_PV_M 0x0000000F -#define FLASH_FVHVCT1_VHVCT_PV_S 0 +#define FLASH_FVHVCT1_VHVCT_PV_W 4 +#define FLASH_FVHVCT1_VHVCT_PV_M 0x0000000F +#define FLASH_FVHVCT1_VHVCT_PV_S 0 //***************************************************************************** // @@ -1704,16 +1704,16 @@ // Field: [23:20] TRIM13_P // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT2_TRIM13_P_W 4 -#define FLASH_FVHVCT2_TRIM13_P_M 0x00F00000 -#define FLASH_FVHVCT2_TRIM13_P_S 20 +#define FLASH_FVHVCT2_TRIM13_P_W 4 +#define FLASH_FVHVCT2_TRIM13_P_M 0x00F00000 +#define FLASH_FVHVCT2_TRIM13_P_S 20 // Field: [19:16] VHVCT_P // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT2_VHVCT_P_W 4 -#define FLASH_FVHVCT2_VHVCT_P_M 0x000F0000 -#define FLASH_FVHVCT2_VHVCT_P_S 16 +#define FLASH_FVHVCT2_VHVCT_P_W 4 +#define FLASH_FVHVCT2_VHVCT_P_M 0x000F0000 +#define FLASH_FVHVCT2_VHVCT_P_S 16 //***************************************************************************** // @@ -1723,16 +1723,16 @@ // Field: [19:16] WCT // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT3_WCT_W 4 -#define FLASH_FVHVCT3_WCT_M 0x000F0000 -#define FLASH_FVHVCT3_WCT_S 16 +#define FLASH_FVHVCT3_WCT_W 4 +#define FLASH_FVHVCT3_WCT_M 0x000F0000 +#define FLASH_FVHVCT3_WCT_S 16 // Field: [3:0] VHVCT_READ // // Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT3_VHVCT_READ_W 4 -#define FLASH_FVHVCT3_VHVCT_READ_M 0x0000000F -#define FLASH_FVHVCT3_VHVCT_READ_S 0 +#define FLASH_FVHVCT3_VHVCT_READ_W 4 +#define FLASH_FVHVCT3_VHVCT_READ_M 0x0000000F +#define FLASH_FVHVCT3_VHVCT_READ_S 0 //***************************************************************************** // @@ -1742,16 +1742,16 @@ // Field: [12:8] VCG2P5CT // // Internal. Only to be used through TI provided API. -#define FLASH_FVNVCT_VCG2P5CT_W 5 -#define FLASH_FVNVCT_VCG2P5CT_M 0x00001F00 -#define FLASH_FVNVCT_VCG2P5CT_S 8 +#define FLASH_FVNVCT_VCG2P5CT_W 5 +#define FLASH_FVNVCT_VCG2P5CT_M 0x00001F00 +#define FLASH_FVNVCT_VCG2P5CT_S 8 // Field: [4:0] VIN_CT // // Internal. Only to be used through TI provided API. -#define FLASH_FVNVCT_VIN_CT_W 5 -#define FLASH_FVNVCT_VIN_CT_M 0x0000001F -#define FLASH_FVNVCT_VIN_CT_S 0 +#define FLASH_FVNVCT_VIN_CT_W 5 +#define FLASH_FVNVCT_VIN_CT_M 0x0000001F +#define FLASH_FVNVCT_VIN_CT_S 0 //***************************************************************************** // @@ -1761,9 +1761,9 @@ // Field: [15:12] VSL_P // // Internal. Only to be used through TI provided API. -#define FLASH_FVSLP_VSL_P_W 4 -#define FLASH_FVSLP_VSL_P_M 0x0000F000 -#define FLASH_FVSLP_VSL_P_S 12 +#define FLASH_FVSLP_VSL_P_W 4 +#define FLASH_FVSLP_VSL_P_M 0x0000F000 +#define FLASH_FVSLP_VSL_P_S 12 //***************************************************************************** // @@ -1773,9 +1773,9 @@ // Field: [4:0] VWLCT_P // // Internal. Only to be used through TI provided API. -#define FLASH_FVWLCT_VWLCT_P_W 5 -#define FLASH_FVWLCT_VWLCT_P_M 0x0000001F -#define FLASH_FVWLCT_VWLCT_P_S 0 +#define FLASH_FVWLCT_VWLCT_P_W 5 +#define FLASH_FVWLCT_VWLCT_P_M 0x0000001F +#define FLASH_FVWLCT_VWLCT_P_S 0 //***************************************************************************** // @@ -1785,48 +1785,48 @@ // Field: [26:24] CHAIN_SEL // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_CHAIN_SEL_W 3 -#define FLASH_FEFUSECTL_CHAIN_SEL_M 0x07000000 -#define FLASH_FEFUSECTL_CHAIN_SEL_S 24 +#define FLASH_FEFUSECTL_CHAIN_SEL_W 3 +#define FLASH_FEFUSECTL_CHAIN_SEL_M 0x07000000 +#define FLASH_FEFUSECTL_CHAIN_SEL_S 24 // Field: [17] WRITE_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_WRITE_EN 0x00020000 -#define FLASH_FEFUSECTL_WRITE_EN_BITN 17 -#define FLASH_FEFUSECTL_WRITE_EN_M 0x00020000 -#define FLASH_FEFUSECTL_WRITE_EN_S 17 +#define FLASH_FEFUSECTL_WRITE_EN 0x00020000 +#define FLASH_FEFUSECTL_WRITE_EN_BITN 17 +#define FLASH_FEFUSECTL_WRITE_EN_M 0x00020000 +#define FLASH_FEFUSECTL_WRITE_EN_S 17 // Field: [16] BP_SEL // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_BP_SEL 0x00010000 -#define FLASH_FEFUSECTL_BP_SEL_BITN 16 -#define FLASH_FEFUSECTL_BP_SEL_M 0x00010000 -#define FLASH_FEFUSECTL_BP_SEL_S 16 +#define FLASH_FEFUSECTL_BP_SEL 0x00010000 +#define FLASH_FEFUSECTL_BP_SEL_BITN 16 +#define FLASH_FEFUSECTL_BP_SEL_M 0x00010000 +#define FLASH_FEFUSECTL_BP_SEL_S 16 // Field: [8] EF_CLRZ // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_EF_CLRZ 0x00000100 -#define FLASH_FEFUSECTL_EF_CLRZ_BITN 8 -#define FLASH_FEFUSECTL_EF_CLRZ_M 0x00000100 -#define FLASH_FEFUSECTL_EF_CLRZ_S 8 +#define FLASH_FEFUSECTL_EF_CLRZ 0x00000100 +#define FLASH_FEFUSECTL_EF_CLRZ_BITN 8 +#define FLASH_FEFUSECTL_EF_CLRZ_M 0x00000100 +#define FLASH_FEFUSECTL_EF_CLRZ_S 8 // Field: [4] EF_TEST // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_EF_TEST 0x00000010 -#define FLASH_FEFUSECTL_EF_TEST_BITN 4 -#define FLASH_FEFUSECTL_EF_TEST_M 0x00000010 -#define FLASH_FEFUSECTL_EF_TEST_S 4 +#define FLASH_FEFUSECTL_EF_TEST 0x00000010 +#define FLASH_FEFUSECTL_EF_TEST_BITN 4 +#define FLASH_FEFUSECTL_EF_TEST_M 0x00000010 +#define FLASH_FEFUSECTL_EF_TEST_S 4 // Field: [3:0] EFUSE_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_EFUSE_EN_W 4 -#define FLASH_FEFUSECTL_EFUSE_EN_M 0x0000000F -#define FLASH_FEFUSECTL_EFUSE_EN_S 0 +#define FLASH_FEFUSECTL_EFUSE_EN_W 4 +#define FLASH_FEFUSECTL_EFUSE_EN_M 0x0000000F +#define FLASH_FEFUSECTL_EFUSE_EN_S 0 //***************************************************************************** // @@ -1836,10 +1836,10 @@ // Field: [0] SHIFT_DONE // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSESTAT_SHIFT_DONE 0x00000001 -#define FLASH_FEFUSESTAT_SHIFT_DONE_BITN 0 -#define FLASH_FEFUSESTAT_SHIFT_DONE_M 0x00000001 -#define FLASH_FEFUSESTAT_SHIFT_DONE_S 0 +#define FLASH_FEFUSESTAT_SHIFT_DONE 0x00000001 +#define FLASH_FEFUSESTAT_SHIFT_DONE_BITN 0 +#define FLASH_FEFUSESTAT_SHIFT_DONE_M 0x00000001 +#define FLASH_FEFUSESTAT_SHIFT_DONE_S 0 //***************************************************************************** // @@ -1849,9 +1849,9 @@ // Field: [31:0] FEFUSEDATA // // Internal. Only to be used through TI provided API. -#define FLASH_FEFUSEDATA_FEFUSEDATA_W 32 -#define FLASH_FEFUSEDATA_FEFUSEDATA_M 0xFFFFFFFF -#define FLASH_FEFUSEDATA_FEFUSEDATA_S 0 +#define FLASH_FEFUSEDATA_FEFUSEDATA_W 32 +#define FLASH_FEFUSEDATA_FEFUSEDATA_M 0xFFFFFFFF +#define FLASH_FEFUSEDATA_FEFUSEDATA_S 0 //***************************************************************************** // @@ -1861,38 +1861,38 @@ // Field: [27:24] TRIM_3P4 // // Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_TRIM_3P4_W 4 -#define FLASH_FSEQPMP_TRIM_3P4_M 0x0F000000 -#define FLASH_FSEQPMP_TRIM_3P4_S 24 +#define FLASH_FSEQPMP_TRIM_3P4_W 4 +#define FLASH_FSEQPMP_TRIM_3P4_M 0x0F000000 +#define FLASH_FSEQPMP_TRIM_3P4_S 24 // Field: [21:20] TRIM_1P7 // // Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_TRIM_1P7_W 2 -#define FLASH_FSEQPMP_TRIM_1P7_M 0x00300000 -#define FLASH_FSEQPMP_TRIM_1P7_S 20 +#define FLASH_FSEQPMP_TRIM_1P7_W 2 +#define FLASH_FSEQPMP_TRIM_1P7_M 0x00300000 +#define FLASH_FSEQPMP_TRIM_1P7_S 20 // Field: [19:16] TRIM_0P8 // // Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_TRIM_0P8_W 4 -#define FLASH_FSEQPMP_TRIM_0P8_M 0x000F0000 -#define FLASH_FSEQPMP_TRIM_0P8_S 16 +#define FLASH_FSEQPMP_TRIM_0P8_W 4 +#define FLASH_FSEQPMP_TRIM_0P8_M 0x000F0000 +#define FLASH_FSEQPMP_TRIM_0P8_S 16 // Field: [14:12] VIN_AT_X // // Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_VIN_AT_X_W 3 -#define FLASH_FSEQPMP_VIN_AT_X_M 0x00007000 -#define FLASH_FSEQPMP_VIN_AT_X_S 12 +#define FLASH_FSEQPMP_VIN_AT_X_W 3 +#define FLASH_FSEQPMP_VIN_AT_X_M 0x00007000 +#define FLASH_FSEQPMP_VIN_AT_X_S 12 // Field: [8] VIN_BY_PASS // // Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_VIN_BY_PASS 0x00000100 -#define FLASH_FSEQPMP_VIN_BY_PASS_BITN 8 -#define FLASH_FSEQPMP_VIN_BY_PASS_M 0x00000100 -#define FLASH_FSEQPMP_VIN_BY_PASS_S 8 +#define FLASH_FSEQPMP_VIN_BY_PASS 0x00000100 +#define FLASH_FSEQPMP_VIN_BY_PASS_BITN 8 +#define FLASH_FSEQPMP_VIN_BY_PASS_M 0x00000100 +#define FLASH_FSEQPMP_VIN_BY_PASS_S 8 //***************************************************************************** // @@ -1902,82 +1902,82 @@ // Field: [24] ECBIT // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_ECBIT 0x01000000 -#define FLASH_FBSTROBES_ECBIT_BITN 24 -#define FLASH_FBSTROBES_ECBIT_M 0x01000000 -#define FLASH_FBSTROBES_ECBIT_S 24 +#define FLASH_FBSTROBES_ECBIT 0x01000000 +#define FLASH_FBSTROBES_ECBIT_BITN 24 +#define FLASH_FBSTROBES_ECBIT_M 0x01000000 +#define FLASH_FBSTROBES_ECBIT_S 24 // Field: [18] RWAIT2_FLCLK // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_RWAIT2_FLCLK 0x00040000 -#define FLASH_FBSTROBES_RWAIT2_FLCLK_BITN 18 -#define FLASH_FBSTROBES_RWAIT2_FLCLK_M 0x00040000 -#define FLASH_FBSTROBES_RWAIT2_FLCLK_S 18 +#define FLASH_FBSTROBES_RWAIT2_FLCLK 0x00040000 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_BITN 18 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_M 0x00040000 +#define FLASH_FBSTROBES_RWAIT2_FLCLK_S 18 // Field: [17] RWAIT_FLCLK // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_RWAIT_FLCLK 0x00020000 -#define FLASH_FBSTROBES_RWAIT_FLCLK_BITN 17 -#define FLASH_FBSTROBES_RWAIT_FLCLK_M 0x00020000 -#define FLASH_FBSTROBES_RWAIT_FLCLK_S 17 +#define FLASH_FBSTROBES_RWAIT_FLCLK 0x00020000 +#define FLASH_FBSTROBES_RWAIT_FLCLK_BITN 17 +#define FLASH_FBSTROBES_RWAIT_FLCLK_M 0x00020000 +#define FLASH_FBSTROBES_RWAIT_FLCLK_S 17 // Field: [16] FLCLKEN // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_FLCLKEN 0x00010000 -#define FLASH_FBSTROBES_FLCLKEN_BITN 16 -#define FLASH_FBSTROBES_FLCLKEN_M 0x00010000 -#define FLASH_FBSTROBES_FLCLKEN_S 16 +#define FLASH_FBSTROBES_FLCLKEN 0x00010000 +#define FLASH_FBSTROBES_FLCLKEN_BITN 16 +#define FLASH_FBSTROBES_FLCLKEN_M 0x00010000 +#define FLASH_FBSTROBES_FLCLKEN_S 16 // Field: [8] CTRLENZ // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_CTRLENZ 0x00000100 -#define FLASH_FBSTROBES_CTRLENZ_BITN 8 -#define FLASH_FBSTROBES_CTRLENZ_M 0x00000100 -#define FLASH_FBSTROBES_CTRLENZ_S 8 +#define FLASH_FBSTROBES_CTRLENZ 0x00000100 +#define FLASH_FBSTROBES_CTRLENZ_BITN 8 +#define FLASH_FBSTROBES_CTRLENZ_M 0x00000100 +#define FLASH_FBSTROBES_CTRLENZ_S 8 // Field: [6] NOCOLRED // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_NOCOLRED 0x00000040 -#define FLASH_FBSTROBES_NOCOLRED_BITN 6 -#define FLASH_FBSTROBES_NOCOLRED_M 0x00000040 -#define FLASH_FBSTROBES_NOCOLRED_S 6 +#define FLASH_FBSTROBES_NOCOLRED 0x00000040 +#define FLASH_FBSTROBES_NOCOLRED_BITN 6 +#define FLASH_FBSTROBES_NOCOLRED_M 0x00000040 +#define FLASH_FBSTROBES_NOCOLRED_S 6 // Field: [5] PRECOL // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_PRECOL 0x00000020 -#define FLASH_FBSTROBES_PRECOL_BITN 5 -#define FLASH_FBSTROBES_PRECOL_M 0x00000020 -#define FLASH_FBSTROBES_PRECOL_S 5 +#define FLASH_FBSTROBES_PRECOL 0x00000020 +#define FLASH_FBSTROBES_PRECOL_BITN 5 +#define FLASH_FBSTROBES_PRECOL_M 0x00000020 +#define FLASH_FBSTROBES_PRECOL_S 5 // Field: [4] TI_OTP // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_TI_OTP 0x00000010 -#define FLASH_FBSTROBES_TI_OTP_BITN 4 -#define FLASH_FBSTROBES_TI_OTP_M 0x00000010 -#define FLASH_FBSTROBES_TI_OTP_S 4 +#define FLASH_FBSTROBES_TI_OTP 0x00000010 +#define FLASH_FBSTROBES_TI_OTP_BITN 4 +#define FLASH_FBSTROBES_TI_OTP_M 0x00000010 +#define FLASH_FBSTROBES_TI_OTP_S 4 // Field: [3] OTP // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_OTP 0x00000008 -#define FLASH_FBSTROBES_OTP_BITN 3 -#define FLASH_FBSTROBES_OTP_M 0x00000008 -#define FLASH_FBSTROBES_OTP_S 3 +#define FLASH_FBSTROBES_OTP 0x00000008 +#define FLASH_FBSTROBES_OTP_BITN 3 +#define FLASH_FBSTROBES_OTP_M 0x00000008 +#define FLASH_FBSTROBES_OTP_S 3 // Field: [2] TEZ // // Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_TEZ 0x00000004 -#define FLASH_FBSTROBES_TEZ_BITN 2 -#define FLASH_FBSTROBES_TEZ_M 0x00000004 -#define FLASH_FBSTROBES_TEZ_S 2 +#define FLASH_FBSTROBES_TEZ 0x00000004 +#define FLASH_FBSTROBES_TEZ_BITN 2 +#define FLASH_FBSTROBES_TEZ_M 0x00000004 +#define FLASH_FBSTROBES_TEZ_S 2 //***************************************************************************** // @@ -1987,26 +1987,26 @@ // Field: [8] EXECUTEZ // // Internal. Only to be used through TI provided API. -#define FLASH_FPSTROBES_EXECUTEZ 0x00000100 -#define FLASH_FPSTROBES_EXECUTEZ_BITN 8 -#define FLASH_FPSTROBES_EXECUTEZ_M 0x00000100 -#define FLASH_FPSTROBES_EXECUTEZ_S 8 +#define FLASH_FPSTROBES_EXECUTEZ 0x00000100 +#define FLASH_FPSTROBES_EXECUTEZ_BITN 8 +#define FLASH_FPSTROBES_EXECUTEZ_M 0x00000100 +#define FLASH_FPSTROBES_EXECUTEZ_S 8 // Field: [1] V3PWRDNZ // // Internal. Only to be used through TI provided API. -#define FLASH_FPSTROBES_V3PWRDNZ 0x00000002 -#define FLASH_FPSTROBES_V3PWRDNZ_BITN 1 -#define FLASH_FPSTROBES_V3PWRDNZ_M 0x00000002 -#define FLASH_FPSTROBES_V3PWRDNZ_S 1 +#define FLASH_FPSTROBES_V3PWRDNZ 0x00000002 +#define FLASH_FPSTROBES_V3PWRDNZ_BITN 1 +#define FLASH_FPSTROBES_V3PWRDNZ_M 0x00000002 +#define FLASH_FPSTROBES_V3PWRDNZ_S 1 // Field: [0] V5PWRDNZ // // Internal. Only to be used through TI provided API. -#define FLASH_FPSTROBES_V5PWRDNZ 0x00000001 -#define FLASH_FPSTROBES_V5PWRDNZ_BITN 0 -#define FLASH_FPSTROBES_V5PWRDNZ_M 0x00000001 -#define FLASH_FPSTROBES_V5PWRDNZ_S 0 +#define FLASH_FPSTROBES_V5PWRDNZ 0x00000001 +#define FLASH_FPSTROBES_V5PWRDNZ_BITN 0 +#define FLASH_FPSTROBES_V5PWRDNZ_M 0x00000001 +#define FLASH_FPSTROBES_V5PWRDNZ_S 0 //***************************************************************************** // @@ -2016,9 +2016,9 @@ // Field: [2:0] MODE // // Internal. Only to be used through TI provided API. -#define FLASH_FBMODE_MODE_W 3 -#define FLASH_FBMODE_MODE_M 0x00000007 -#define FLASH_FBMODE_MODE_S 0 +#define FLASH_FBMODE_MODE_W 3 +#define FLASH_FBMODE_MODE_M 0x00000007 +#define FLASH_FBMODE_MODE_S 0 //***************************************************************************** // @@ -2028,9 +2028,9 @@ // Field: [6:0] TCR // // Internal. Only to be used through TI provided API. -#define FLASH_FTCR_TCR_W 7 -#define FLASH_FTCR_TCR_M 0x0000007F -#define FLASH_FTCR_TCR_S 0 +#define FLASH_FTCR_TCR_W 7 +#define FLASH_FTCR_TCR_M 0x0000007F +#define FLASH_FTCR_TCR_S 0 //***************************************************************************** // @@ -2040,9 +2040,9 @@ // Field: [31:0] FADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FADDR_FADDR_W 32 -#define FLASH_FADDR_FADDR_M 0xFFFFFFFF -#define FLASH_FADDR_FADDR_S 0 +#define FLASH_FADDR_FADDR_W 32 +#define FLASH_FADDR_FADDR_M 0xFFFFFFFF +#define FLASH_FADDR_FADDR_S 0 //***************************************************************************** // @@ -2052,18 +2052,18 @@ // Field: [16] WDATA_BLK_CLR // // Internal. Only to be used through TI provided API. -#define FLASH_FTCTL_WDATA_BLK_CLR 0x00010000 -#define FLASH_FTCTL_WDATA_BLK_CLR_BITN 16 -#define FLASH_FTCTL_WDATA_BLK_CLR_M 0x00010000 -#define FLASH_FTCTL_WDATA_BLK_CLR_S 16 +#define FLASH_FTCTL_WDATA_BLK_CLR 0x00010000 +#define FLASH_FTCTL_WDATA_BLK_CLR_BITN 16 +#define FLASH_FTCTL_WDATA_BLK_CLR_M 0x00010000 +#define FLASH_FTCTL_WDATA_BLK_CLR_S 16 // Field: [1] TEST_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FTCTL_TEST_EN 0x00000002 -#define FLASH_FTCTL_TEST_EN_BITN 1 -#define FLASH_FTCTL_TEST_EN_M 0x00000002 -#define FLASH_FTCTL_TEST_EN_S 1 +#define FLASH_FTCTL_TEST_EN 0x00000002 +#define FLASH_FTCTL_TEST_EN_BITN 1 +#define FLASH_FTCTL_TEST_EN_M 0x00000002 +#define FLASH_FTCTL_TEST_EN_S 1 //***************************************************************************** // @@ -2073,9 +2073,9 @@ // Field: [31:0] FWPWRITE0 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE0_FWPWRITE0_W 32 -#define FLASH_FWPWRITE0_FWPWRITE0_M 0xFFFFFFFF -#define FLASH_FWPWRITE0_FWPWRITE0_S 0 +#define FLASH_FWPWRITE0_FWPWRITE0_W 32 +#define FLASH_FWPWRITE0_FWPWRITE0_M 0xFFFFFFFF +#define FLASH_FWPWRITE0_FWPWRITE0_S 0 //***************************************************************************** // @@ -2085,9 +2085,9 @@ // Field: [31:0] FWPWRITE1 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE1_FWPWRITE1_W 32 -#define FLASH_FWPWRITE1_FWPWRITE1_M 0xFFFFFFFF -#define FLASH_FWPWRITE1_FWPWRITE1_S 0 +#define FLASH_FWPWRITE1_FWPWRITE1_W 32 +#define FLASH_FWPWRITE1_FWPWRITE1_M 0xFFFFFFFF +#define FLASH_FWPWRITE1_FWPWRITE1_S 0 //***************************************************************************** // @@ -2097,9 +2097,9 @@ // Field: [31:0] FWPWRITE2 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE2_FWPWRITE2_W 32 -#define FLASH_FWPWRITE2_FWPWRITE2_M 0xFFFFFFFF -#define FLASH_FWPWRITE2_FWPWRITE2_S 0 +#define FLASH_FWPWRITE2_FWPWRITE2_W 32 +#define FLASH_FWPWRITE2_FWPWRITE2_M 0xFFFFFFFF +#define FLASH_FWPWRITE2_FWPWRITE2_S 0 //***************************************************************************** // @@ -2109,9 +2109,9 @@ // Field: [31:0] FWPWRITE3 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE3_FWPWRITE3_W 32 -#define FLASH_FWPWRITE3_FWPWRITE3_M 0xFFFFFFFF -#define FLASH_FWPWRITE3_FWPWRITE3_S 0 +#define FLASH_FWPWRITE3_FWPWRITE3_W 32 +#define FLASH_FWPWRITE3_FWPWRITE3_M 0xFFFFFFFF +#define FLASH_FWPWRITE3_FWPWRITE3_S 0 //***************************************************************************** // @@ -2121,9 +2121,9 @@ // Field: [31:0] FWPWRITE4 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE4_FWPWRITE4_W 32 -#define FLASH_FWPWRITE4_FWPWRITE4_M 0xFFFFFFFF -#define FLASH_FWPWRITE4_FWPWRITE4_S 0 +#define FLASH_FWPWRITE4_FWPWRITE4_W 32 +#define FLASH_FWPWRITE4_FWPWRITE4_M 0xFFFFFFFF +#define FLASH_FWPWRITE4_FWPWRITE4_S 0 //***************************************************************************** // @@ -2133,9 +2133,9 @@ // Field: [31:0] FWPWRITE5 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE5_FWPWRITE5_W 32 -#define FLASH_FWPWRITE5_FWPWRITE5_M 0xFFFFFFFF -#define FLASH_FWPWRITE5_FWPWRITE5_S 0 +#define FLASH_FWPWRITE5_FWPWRITE5_W 32 +#define FLASH_FWPWRITE5_FWPWRITE5_M 0xFFFFFFFF +#define FLASH_FWPWRITE5_FWPWRITE5_S 0 //***************************************************************************** // @@ -2145,9 +2145,9 @@ // Field: [31:0] FWPWRITE6 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE6_FWPWRITE6_W 32 -#define FLASH_FWPWRITE6_FWPWRITE6_M 0xFFFFFFFF -#define FLASH_FWPWRITE6_FWPWRITE6_S 0 +#define FLASH_FWPWRITE6_FWPWRITE6_W 32 +#define FLASH_FWPWRITE6_FWPWRITE6_M 0xFFFFFFFF +#define FLASH_FWPWRITE6_FWPWRITE6_S 0 //***************************************************************************** // @@ -2157,9 +2157,9 @@ // Field: [31:0] FWPWRITE7 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE7_FWPWRITE7_W 32 -#define FLASH_FWPWRITE7_FWPWRITE7_M 0xFFFFFFFF -#define FLASH_FWPWRITE7_FWPWRITE7_S 0 +#define FLASH_FWPWRITE7_FWPWRITE7_W 32 +#define FLASH_FWPWRITE7_FWPWRITE7_M 0xFFFFFFFF +#define FLASH_FWPWRITE7_FWPWRITE7_S 0 //***************************************************************************** // @@ -2169,30 +2169,30 @@ // Field: [31:24] ECCBYTES07_00 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_W 8 -#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_M 0xFF000000 -#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_S 24 +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_M 0xFF000000 +#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_S 24 // Field: [23:16] ECCBYTES15_08 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_W 8 -#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_M 0x00FF0000 -#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_S 16 +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_M 0x00FF0000 +#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_S 16 // Field: [15:8] ECCBYTES23_16 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_W 8 -#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_M 0x0000FF00 -#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_S 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_M 0x0000FF00 +#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_S 8 // Field: [7:0] ECCBYTES31_24 // // Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_W 8 -#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_M 0x000000FF -#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_S 0 +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_W 8 +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_M 0x000000FF +#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_S 0 //***************************************************************************** // @@ -2202,10 +2202,10 @@ // Field: [0] SAFELV // // Internal. Only to be used through TI provided API. -#define FLASH_FSWSTAT_SAFELV 0x00000001 -#define FLASH_FSWSTAT_SAFELV_BITN 0 -#define FLASH_FSWSTAT_SAFELV_M 0x00000001 -#define FLASH_FSWSTAT_SAFELV_S 0 +#define FLASH_FSWSTAT_SAFELV 0x00000001 +#define FLASH_FSWSTAT_SAFELV_BITN 0 +#define FLASH_FSWSTAT_SAFELV_M 0x00000001 +#define FLASH_FSWSTAT_SAFELV_S 0 //***************************************************************************** // @@ -2215,10 +2215,10 @@ // Field: [0] CLKSEL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_GLBCTL_CLKSEL 0x00000001 -#define FLASH_FSM_GLBCTL_CLKSEL_BITN 0 -#define FLASH_FSM_GLBCTL_CLKSEL_M 0x00000001 -#define FLASH_FSM_GLBCTL_CLKSEL_S 0 +#define FLASH_FSM_GLBCTL_CLKSEL 0x00000001 +#define FLASH_FSM_GLBCTL_CLKSEL_BITN 0 +#define FLASH_FSM_GLBCTL_CLKSEL_M 0x00000001 +#define FLASH_FSM_GLBCTL_CLKSEL_S 0 //***************************************************************************** // @@ -2228,42 +2228,42 @@ // Field: [11] CTRLENZ // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_CTRLENZ 0x00000800 -#define FLASH_FSM_STATE_CTRLENZ_BITN 11 -#define FLASH_FSM_STATE_CTRLENZ_M 0x00000800 -#define FLASH_FSM_STATE_CTRLENZ_S 11 +#define FLASH_FSM_STATE_CTRLENZ 0x00000800 +#define FLASH_FSM_STATE_CTRLENZ_BITN 11 +#define FLASH_FSM_STATE_CTRLENZ_M 0x00000800 +#define FLASH_FSM_STATE_CTRLENZ_S 11 // Field: [10] EXECUTEZ // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_EXECUTEZ 0x00000400 -#define FLASH_FSM_STATE_EXECUTEZ_BITN 10 -#define FLASH_FSM_STATE_EXECUTEZ_M 0x00000400 -#define FLASH_FSM_STATE_EXECUTEZ_S 10 +#define FLASH_FSM_STATE_EXECUTEZ 0x00000400 +#define FLASH_FSM_STATE_EXECUTEZ_BITN 10 +#define FLASH_FSM_STATE_EXECUTEZ_M 0x00000400 +#define FLASH_FSM_STATE_EXECUTEZ_S 10 // Field: [8] FSM_ACT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_FSM_ACT 0x00000100 -#define FLASH_FSM_STATE_FSM_ACT_BITN 8 -#define FLASH_FSM_STATE_FSM_ACT_M 0x00000100 -#define FLASH_FSM_STATE_FSM_ACT_S 8 +#define FLASH_FSM_STATE_FSM_ACT 0x00000100 +#define FLASH_FSM_STATE_FSM_ACT_BITN 8 +#define FLASH_FSM_STATE_FSM_ACT_M 0x00000100 +#define FLASH_FSM_STATE_FSM_ACT_S 8 // Field: [7] TIOTP_ACT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_TIOTP_ACT 0x00000080 -#define FLASH_FSM_STATE_TIOTP_ACT_BITN 7 -#define FLASH_FSM_STATE_TIOTP_ACT_M 0x00000080 -#define FLASH_FSM_STATE_TIOTP_ACT_S 7 +#define FLASH_FSM_STATE_TIOTP_ACT 0x00000080 +#define FLASH_FSM_STATE_TIOTP_ACT_BITN 7 +#define FLASH_FSM_STATE_TIOTP_ACT_M 0x00000080 +#define FLASH_FSM_STATE_TIOTP_ACT_S 7 // Field: [6] OTP_ACT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_OTP_ACT 0x00000040 -#define FLASH_FSM_STATE_OTP_ACT_BITN 6 -#define FLASH_FSM_STATE_OTP_ACT_M 0x00000040 -#define FLASH_FSM_STATE_OTP_ACT_S 6 +#define FLASH_FSM_STATE_OTP_ACT 0x00000040 +#define FLASH_FSM_STATE_OTP_ACT_BITN 6 +#define FLASH_FSM_STATE_OTP_ACT_M 0x00000040 +#define FLASH_FSM_STATE_OTP_ACT_S 6 //***************************************************************************** // @@ -2273,26 +2273,26 @@ // Field: [2] NON_OP // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STAT_NON_OP 0x00000004 -#define FLASH_FSM_STAT_NON_OP_BITN 2 -#define FLASH_FSM_STAT_NON_OP_M 0x00000004 -#define FLASH_FSM_STAT_NON_OP_S 2 +#define FLASH_FSM_STAT_NON_OP 0x00000004 +#define FLASH_FSM_STAT_NON_OP_BITN 2 +#define FLASH_FSM_STAT_NON_OP_M 0x00000004 +#define FLASH_FSM_STAT_NON_OP_S 2 // Field: [1] OVR_PUL_CNT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STAT_OVR_PUL_CNT 0x00000002 -#define FLASH_FSM_STAT_OVR_PUL_CNT_BITN 1 -#define FLASH_FSM_STAT_OVR_PUL_CNT_M 0x00000002 -#define FLASH_FSM_STAT_OVR_PUL_CNT_S 1 +#define FLASH_FSM_STAT_OVR_PUL_CNT 0x00000002 +#define FLASH_FSM_STAT_OVR_PUL_CNT_BITN 1 +#define FLASH_FSM_STAT_OVR_PUL_CNT_M 0x00000002 +#define FLASH_FSM_STAT_OVR_PUL_CNT_S 1 // Field: [0] INV_DAT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STAT_INV_DAT 0x00000001 -#define FLASH_FSM_STAT_INV_DAT_BITN 0 -#define FLASH_FSM_STAT_INV_DAT_M 0x00000001 -#define FLASH_FSM_STAT_INV_DAT_S 0 +#define FLASH_FSM_STAT_INV_DAT 0x00000001 +#define FLASH_FSM_STAT_INV_DAT_BITN 0 +#define FLASH_FSM_STAT_INV_DAT_M 0x00000001 +#define FLASH_FSM_STAT_INV_DAT_S 0 //***************************************************************************** // @@ -2302,9 +2302,9 @@ // Field: [5:0] FSMCMD // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_CMD_FSMCMD_W 6 -#define FLASH_FSM_CMD_FSMCMD_M 0x0000003F -#define FLASH_FSM_CMD_FSMCMD_S 0 +#define FLASH_FSM_CMD_FSMCMD_W 6 +#define FLASH_FSM_CMD_FSMCMD_M 0x0000003F +#define FLASH_FSM_CMD_FSMCMD_S 0 //***************************************************************************** // @@ -2314,16 +2314,16 @@ // Field: [15:8] PGM_OSU // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_OSU_PGM_OSU_W 8 -#define FLASH_FSM_PE_OSU_PGM_OSU_M 0x0000FF00 -#define FLASH_FSM_PE_OSU_PGM_OSU_S 8 +#define FLASH_FSM_PE_OSU_PGM_OSU_W 8 +#define FLASH_FSM_PE_OSU_PGM_OSU_M 0x0000FF00 +#define FLASH_FSM_PE_OSU_PGM_OSU_S 8 // Field: [7:0] ERA_OSU // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_OSU_ERA_OSU_W 8 -#define FLASH_FSM_PE_OSU_ERA_OSU_M 0x000000FF -#define FLASH_FSM_PE_OSU_ERA_OSU_S 0 +#define FLASH_FSM_PE_OSU_ERA_OSU_W 8 +#define FLASH_FSM_PE_OSU_ERA_OSU_M 0x000000FF +#define FLASH_FSM_PE_OSU_ERA_OSU_S 0 //***************************************************************************** // @@ -2333,9 +2333,9 @@ // Field: [15:12] VSTAT_CNT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_VSTAT_VSTAT_CNT_W 4 -#define FLASH_FSM_VSTAT_VSTAT_CNT_M 0x0000F000 -#define FLASH_FSM_VSTAT_VSTAT_CNT_S 12 +#define FLASH_FSM_VSTAT_VSTAT_CNT_W 4 +#define FLASH_FSM_VSTAT_VSTAT_CNT_M 0x0000F000 +#define FLASH_FSM_VSTAT_VSTAT_CNT_S 12 //***************************************************************************** // @@ -2345,16 +2345,16 @@ // Field: [15:8] PGM_VSU // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_VSU_PGM_VSU_W 8 -#define FLASH_FSM_PE_VSU_PGM_VSU_M 0x0000FF00 -#define FLASH_FSM_PE_VSU_PGM_VSU_S 8 +#define FLASH_FSM_PE_VSU_PGM_VSU_W 8 +#define FLASH_FSM_PE_VSU_PGM_VSU_M 0x0000FF00 +#define FLASH_FSM_PE_VSU_PGM_VSU_S 8 // Field: [7:0] ERA_VSU // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_VSU_ERA_VSU_W 8 -#define FLASH_FSM_PE_VSU_ERA_VSU_M 0x000000FF -#define FLASH_FSM_PE_VSU_ERA_VSU_S 0 +#define FLASH_FSM_PE_VSU_ERA_VSU_W 8 +#define FLASH_FSM_PE_VSU_ERA_VSU_M 0x000000FF +#define FLASH_FSM_PE_VSU_ERA_VSU_S 0 //***************************************************************************** // @@ -2364,9 +2364,9 @@ // Field: [15:12] ADD_EXZ // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_CMP_VSU_ADD_EXZ_W 4 -#define FLASH_FSM_CMP_VSU_ADD_EXZ_M 0x0000F000 -#define FLASH_FSM_CMP_VSU_ADD_EXZ_S 12 +#define FLASH_FSM_CMP_VSU_ADD_EXZ_W 4 +#define FLASH_FSM_CMP_VSU_ADD_EXZ_M 0x0000F000 +#define FLASH_FSM_CMP_VSU_ADD_EXZ_S 12 //***************************************************************************** // @@ -2376,16 +2376,16 @@ // Field: [15:8] REP_VSU // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_EX_VAL_REP_VSU_W 8 -#define FLASH_FSM_EX_VAL_REP_VSU_M 0x0000FF00 -#define FLASH_FSM_EX_VAL_REP_VSU_S 8 +#define FLASH_FSM_EX_VAL_REP_VSU_W 8 +#define FLASH_FSM_EX_VAL_REP_VSU_M 0x0000FF00 +#define FLASH_FSM_EX_VAL_REP_VSU_S 8 // Field: [7:0] EXE_VALD // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_EX_VAL_EXE_VALD_W 8 -#define FLASH_FSM_EX_VAL_EXE_VALD_M 0x000000FF -#define FLASH_FSM_EX_VAL_EXE_VALD_S 0 +#define FLASH_FSM_EX_VAL_EXE_VALD_W 8 +#define FLASH_FSM_EX_VAL_EXE_VALD_M 0x000000FF +#define FLASH_FSM_EX_VAL_EXE_VALD_S 0 //***************************************************************************** // @@ -2395,9 +2395,9 @@ // Field: [7:0] RD_H // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_RD_H_RD_H_W 8 -#define FLASH_FSM_RD_H_RD_H_M 0x000000FF -#define FLASH_FSM_RD_H_RD_H_S 0 +#define FLASH_FSM_RD_H_RD_H_W 8 +#define FLASH_FSM_RD_H_RD_H_M 0x000000FF +#define FLASH_FSM_RD_H_RD_H_S 0 //***************************************************************************** // @@ -2407,9 +2407,9 @@ // Field: [15:8] PGM_OH // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_P_OH_PGM_OH_W 8 -#define FLASH_FSM_P_OH_PGM_OH_M 0x0000FF00 -#define FLASH_FSM_P_OH_PGM_OH_S 8 +#define FLASH_FSM_P_OH_PGM_OH_W 8 +#define FLASH_FSM_P_OH_PGM_OH_M 0x0000FF00 +#define FLASH_FSM_P_OH_PGM_OH_S 8 //***************************************************************************** // @@ -2419,9 +2419,9 @@ // Field: [15:0] ERA_OH // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_OH_ERA_OH_W 16 -#define FLASH_FSM_ERA_OH_ERA_OH_M 0x0000FFFF -#define FLASH_FSM_ERA_OH_ERA_OH_S 0 +#define FLASH_FSM_ERA_OH_ERA_OH_W 16 +#define FLASH_FSM_ERA_OH_ERA_OH_M 0x0000FFFF +#define FLASH_FSM_ERA_OH_ERA_OH_S 0 //***************************************************************************** // @@ -2431,9 +2431,9 @@ // Field: [11:0] SAV_P_PUL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_W 12 -#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_M 0x00000FFF -#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_S 0 +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_W 12 +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_M 0x00000FFF +#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_S 0 //***************************************************************************** // @@ -2443,9 +2443,9 @@ // Field: [15:8] PGM_VH // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_VH_PGM_VH_W 8 -#define FLASH_FSM_PE_VH_PGM_VH_M 0x0000FF00 -#define FLASH_FSM_PE_VH_PGM_VH_S 8 +#define FLASH_FSM_PE_VH_PGM_VH_W 8 +#define FLASH_FSM_PE_VH_PGM_VH_M 0x0000FF00 +#define FLASH_FSM_PE_VH_PGM_VH_S 8 //***************************************************************************** // @@ -2455,9 +2455,9 @@ // Field: [15:0] PROG_PUL_WIDTH // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_W 16 -#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M 0x0000FFFF -#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S 0 +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_W 16 +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M 0x0000FFFF +#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S 0 //***************************************************************************** // @@ -2467,9 +2467,9 @@ // Field: [31:0] FSM_ERA_PW // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_PW_FSM_ERA_PW_W 32 -#define FLASH_FSM_ERA_PW_FSM_ERA_PW_M 0xFFFFFFFF -#define FLASH_FSM_ERA_PW_FSM_ERA_PW_S 0 +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_W 32 +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_M 0xFFFFFFFF +#define FLASH_FSM_ERA_PW_FSM_ERA_PW_S 0 //***************************************************************************** // @@ -2479,9 +2479,9 @@ // Field: [11:0] SAV_ERA_PUL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_W 12 -#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_M 0x00000FFF -#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_S 0 +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_W 12 +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_M 0x00000FFF +#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_S 0 //***************************************************************************** // @@ -2491,9 +2491,9 @@ // Field: [31:0] FSM_TIMER // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_TIMER_FSM_TIMER_W 32 -#define FLASH_FSM_TIMER_FSM_TIMER_M 0xFFFFFFFF -#define FLASH_FSM_TIMER_FSM_TIMER_S 0 +#define FLASH_FSM_TIMER_FSM_TIMER_W 32 +#define FLASH_FSM_TIMER_FSM_TIMER_M 0xFFFFFFFF +#define FLASH_FSM_TIMER_FSM_TIMER_S 0 //***************************************************************************** // @@ -2503,58 +2503,58 @@ // Field: [19:18] RDV_SUBMODE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_RDV_SUBMODE_W 2 -#define FLASH_FSM_MODE_RDV_SUBMODE_M 0x000C0000 -#define FLASH_FSM_MODE_RDV_SUBMODE_S 18 +#define FLASH_FSM_MODE_RDV_SUBMODE_W 2 +#define FLASH_FSM_MODE_RDV_SUBMODE_M 0x000C0000 +#define FLASH_FSM_MODE_RDV_SUBMODE_S 18 // Field: [17:16] PGM_SUBMODE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_PGM_SUBMODE_W 2 -#define FLASH_FSM_MODE_PGM_SUBMODE_M 0x00030000 -#define FLASH_FSM_MODE_PGM_SUBMODE_S 16 +#define FLASH_FSM_MODE_PGM_SUBMODE_W 2 +#define FLASH_FSM_MODE_PGM_SUBMODE_M 0x00030000 +#define FLASH_FSM_MODE_PGM_SUBMODE_S 16 // Field: [15:14] ERA_SUBMODE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_ERA_SUBMODE_W 2 -#define FLASH_FSM_MODE_ERA_SUBMODE_M 0x0000C000 -#define FLASH_FSM_MODE_ERA_SUBMODE_S 14 +#define FLASH_FSM_MODE_ERA_SUBMODE_W 2 +#define FLASH_FSM_MODE_ERA_SUBMODE_M 0x0000C000 +#define FLASH_FSM_MODE_ERA_SUBMODE_S 14 // Field: [13:12] SUBMODE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_SUBMODE_W 2 -#define FLASH_FSM_MODE_SUBMODE_M 0x00003000 -#define FLASH_FSM_MODE_SUBMODE_S 12 +#define FLASH_FSM_MODE_SUBMODE_W 2 +#define FLASH_FSM_MODE_SUBMODE_M 0x00003000 +#define FLASH_FSM_MODE_SUBMODE_S 12 // Field: [11:9] SAV_PGM_CMD // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_SAV_PGM_CMD_W 3 -#define FLASH_FSM_MODE_SAV_PGM_CMD_M 0x00000E00 -#define FLASH_FSM_MODE_SAV_PGM_CMD_S 9 +#define FLASH_FSM_MODE_SAV_PGM_CMD_W 3 +#define FLASH_FSM_MODE_SAV_PGM_CMD_M 0x00000E00 +#define FLASH_FSM_MODE_SAV_PGM_CMD_S 9 // Field: [8:6] SAV_ERA_MODE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_SAV_ERA_MODE_W 3 -#define FLASH_FSM_MODE_SAV_ERA_MODE_M 0x000001C0 -#define FLASH_FSM_MODE_SAV_ERA_MODE_S 6 +#define FLASH_FSM_MODE_SAV_ERA_MODE_W 3 +#define FLASH_FSM_MODE_SAV_ERA_MODE_M 0x000001C0 +#define FLASH_FSM_MODE_SAV_ERA_MODE_S 6 // Field: [5:3] MODE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_MODE_W 3 -#define FLASH_FSM_MODE_MODE_M 0x00000038 -#define FLASH_FSM_MODE_MODE_S 3 +#define FLASH_FSM_MODE_MODE_W 3 +#define FLASH_FSM_MODE_MODE_M 0x00000038 +#define FLASH_FSM_MODE_MODE_S 3 // Field: [2:0] CMD // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_CMD_W 3 -#define FLASH_FSM_MODE_CMD_M 0x00000007 -#define FLASH_FSM_MODE_CMD_S 0 +#define FLASH_FSM_MODE_CMD_W 3 +#define FLASH_FSM_MODE_CMD_M 0x00000007 +#define FLASH_FSM_MODE_CMD_S 0 //***************************************************************************** // @@ -2564,16 +2564,16 @@ // Field: [25:23] PGM_BANK // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PGM_PGM_BANK_W 3 -#define FLASH_FSM_PGM_PGM_BANK_M 0x03800000 -#define FLASH_FSM_PGM_PGM_BANK_S 23 +#define FLASH_FSM_PGM_PGM_BANK_W 3 +#define FLASH_FSM_PGM_PGM_BANK_M 0x03800000 +#define FLASH_FSM_PGM_PGM_BANK_S 23 // Field: [22:0] PGM_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PGM_PGM_ADDR_W 23 -#define FLASH_FSM_PGM_PGM_ADDR_M 0x007FFFFF -#define FLASH_FSM_PGM_PGM_ADDR_S 0 +#define FLASH_FSM_PGM_PGM_ADDR_W 23 +#define FLASH_FSM_PGM_PGM_ADDR_M 0x007FFFFF +#define FLASH_FSM_PGM_PGM_ADDR_S 0 //***************************************************************************** // @@ -2583,16 +2583,16 @@ // Field: [25:23] ERA_BANK // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_ERA_BANK_W 3 -#define FLASH_FSM_ERA_ERA_BANK_M 0x03800000 -#define FLASH_FSM_ERA_ERA_BANK_S 23 +#define FLASH_FSM_ERA_ERA_BANK_W 3 +#define FLASH_FSM_ERA_ERA_BANK_M 0x03800000 +#define FLASH_FSM_ERA_ERA_BANK_S 23 // Field: [22:0] ERA_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_ERA_ADDR_W 23 -#define FLASH_FSM_ERA_ERA_ADDR_M 0x007FFFFF -#define FLASH_FSM_ERA_ERA_ADDR_S 0 +#define FLASH_FSM_ERA_ERA_ADDR_W 23 +#define FLASH_FSM_ERA_ERA_ADDR_M 0x007FFFFF +#define FLASH_FSM_ERA_ERA_ADDR_S 0 //***************************************************************************** // @@ -2602,16 +2602,16 @@ // Field: [19:16] BEG_EC_LEVEL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_W 4 -#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M 0x000F0000 -#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S 16 +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_W 4 +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M 0x000F0000 +#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S 16 // Field: [11:0] MAX_PRG_PUL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_W 12 -#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M 0x00000FFF -#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S 0 +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_W 12 +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M 0x00000FFF +#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S 0 //***************************************************************************** // @@ -2621,16 +2621,16 @@ // Field: [19:16] MAX_EC_LEVEL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_W 4 -#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M 0x000F0000 -#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S 16 +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_W 4 +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M 0x000F0000 +#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S 16 // Field: [11:0] MAX_ERA_PUL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_W 12 -#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M 0x00000FFF -#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S 0 +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_W 12 +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M 0x00000FFF +#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S 0 //***************************************************************************** // @@ -2640,9 +2640,9 @@ // Field: [24:16] EC_STEP_SIZE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_W 9 -#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M 0x01FF0000 -#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S 16 +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_W 9 +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M 0x01FF0000 +#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S 16 //***************************************************************************** // @@ -2652,16 +2652,16 @@ // Field: [24:16] CUR_EC_LEVEL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_W 9 -#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_M 0x01FF0000 -#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_S 16 +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_W 9 +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_M 0x01FF0000 +#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_S 16 // Field: [11:0] PUL_CNTR // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PUL_CNTR_PUL_CNTR_W 12 -#define FLASH_FSM_PUL_CNTR_PUL_CNTR_M 0x00000FFF -#define FLASH_FSM_PUL_CNTR_PUL_CNTR_S 0 +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_W 12 +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_M 0x00000FFF +#define FLASH_FSM_PUL_CNTR_PUL_CNTR_S 0 //***************************************************************************** // @@ -2671,9 +2671,9 @@ // Field: [3:0] EC_STEP_HEIGHT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_W 4 -#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M 0x0000000F -#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_S 0 +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_W 4 +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M 0x0000000F +#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_S 0 //***************************************************************************** // @@ -2683,137 +2683,137 @@ // Field: [23] DO_PRECOND // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_DO_PRECOND 0x00800000 -#define FLASH_FSM_ST_MACHINE_DO_PRECOND_BITN 23 -#define FLASH_FSM_ST_MACHINE_DO_PRECOND_M 0x00800000 -#define FLASH_FSM_ST_MACHINE_DO_PRECOND_S 23 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND 0x00800000 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_BITN 23 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_M 0x00800000 +#define FLASH_FSM_ST_MACHINE_DO_PRECOND_S 23 // Field: [22] FSM_INT_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_FSM_INT_EN 0x00400000 -#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_BITN 22 -#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_M 0x00400000 -#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_S 22 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN 0x00400000 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_BITN 22 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_M 0x00400000 +#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_S 22 // Field: [21] ALL_BANKS // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_ALL_BANKS 0x00200000 -#define FLASH_FSM_ST_MACHINE_ALL_BANKS_BITN 21 -#define FLASH_FSM_ST_MACHINE_ALL_BANKS_M 0x00200000 -#define FLASH_FSM_ST_MACHINE_ALL_BANKS_S 21 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS 0x00200000 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_BITN 21 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_M 0x00200000 +#define FLASH_FSM_ST_MACHINE_ALL_BANKS_S 21 // Field: [20] CMPV_ALLOWED // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED 0x00100000 -#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_BITN 20 -#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_M 0x00100000 -#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_S 20 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED 0x00100000 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_BITN 20 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_M 0x00100000 +#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_S 20 // Field: [19] RANDOM // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_RANDOM 0x00080000 -#define FLASH_FSM_ST_MACHINE_RANDOM_BITN 19 -#define FLASH_FSM_ST_MACHINE_RANDOM_M 0x00080000 -#define FLASH_FSM_ST_MACHINE_RANDOM_S 19 +#define FLASH_FSM_ST_MACHINE_RANDOM 0x00080000 +#define FLASH_FSM_ST_MACHINE_RANDOM_BITN 19 +#define FLASH_FSM_ST_MACHINE_RANDOM_M 0x00080000 +#define FLASH_FSM_ST_MACHINE_RANDOM_S 19 // Field: [18] RV_SEC_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_RV_SEC_EN 0x00040000 -#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_BITN 18 -#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_M 0x00040000 -#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_S 18 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN 0x00040000 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_BITN 18 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_M 0x00040000 +#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_S 18 // Field: [17] RV_RES // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_RV_RES 0x00020000 -#define FLASH_FSM_ST_MACHINE_RV_RES_BITN 17 -#define FLASH_FSM_ST_MACHINE_RV_RES_M 0x00020000 -#define FLASH_FSM_ST_MACHINE_RV_RES_S 17 +#define FLASH_FSM_ST_MACHINE_RV_RES 0x00020000 +#define FLASH_FSM_ST_MACHINE_RV_RES_BITN 17 +#define FLASH_FSM_ST_MACHINE_RV_RES_M 0x00020000 +#define FLASH_FSM_ST_MACHINE_RV_RES_S 17 // Field: [16] RV_INT_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_RV_INT_EN 0x00010000 -#define FLASH_FSM_ST_MACHINE_RV_INT_EN_BITN 16 -#define FLASH_FSM_ST_MACHINE_RV_INT_EN_M 0x00010000 -#define FLASH_FSM_ST_MACHINE_RV_INT_EN_S 16 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN 0x00010000 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_BITN 16 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_M 0x00010000 +#define FLASH_FSM_ST_MACHINE_RV_INT_EN_S 16 // Field: [14] ONE_TIME_GOOD // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD 0x00004000 -#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_BITN 14 -#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_M 0x00004000 -#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_S 14 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD 0x00004000 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_BITN 14 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_M 0x00004000 +#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_S 14 // Field: [11] DO_REDU_COL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_DO_REDU_COL 0x00000800 -#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_BITN 11 -#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_M 0x00000800 -#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_S 11 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL 0x00000800 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_BITN 11 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_M 0x00000800 +#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_S 11 // Field: [10:7] DBG_SHORT_ROW // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_W 4 -#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_M 0x00000780 -#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_S 7 +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_W 4 +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_M 0x00000780 +#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_S 7 // Field: [5] PGM_SEC_COF_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN 0x00000020 -#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_BITN 5 -#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_M 0x00000020 -#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_S 5 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN 0x00000020 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_BITN 5 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_M 0x00000020 +#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_S 5 // Field: [4] PREC_STOP_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN 0x00000010 -#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_BITN 4 -#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_M 0x00000010 -#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_S 4 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN 0x00000010 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_BITN 4 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_M 0x00000010 +#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_S 4 // Field: [3] DIS_TST_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_DIS_TST_EN 0x00000008 -#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_BITN 3 -#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_M 0x00000008 -#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_S 3 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN 0x00000008 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_BITN 3 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_M 0x00000008 +#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_S 3 // Field: [2] CMD_EN // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_CMD_EN 0x00000004 -#define FLASH_FSM_ST_MACHINE_CMD_EN_BITN 2 -#define FLASH_FSM_ST_MACHINE_CMD_EN_M 0x00000004 -#define FLASH_FSM_ST_MACHINE_CMD_EN_S 2 +#define FLASH_FSM_ST_MACHINE_CMD_EN 0x00000004 +#define FLASH_FSM_ST_MACHINE_CMD_EN_BITN 2 +#define FLASH_FSM_ST_MACHINE_CMD_EN_M 0x00000004 +#define FLASH_FSM_ST_MACHINE_CMD_EN_S 2 // Field: [1] INV_DATA // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_INV_DATA 0x00000002 -#define FLASH_FSM_ST_MACHINE_INV_DATA_BITN 1 -#define FLASH_FSM_ST_MACHINE_INV_DATA_M 0x00000002 -#define FLASH_FSM_ST_MACHINE_INV_DATA_S 1 +#define FLASH_FSM_ST_MACHINE_INV_DATA 0x00000002 +#define FLASH_FSM_ST_MACHINE_INV_DATA_BITN 1 +#define FLASH_FSM_ST_MACHINE_INV_DATA_M 0x00000002 +#define FLASH_FSM_ST_MACHINE_INV_DATA_S 1 // Field: [0] OVERRIDE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_OVERRIDE 0x00000001 -#define FLASH_FSM_ST_MACHINE_OVERRIDE_BITN 0 -#define FLASH_FSM_ST_MACHINE_OVERRIDE_M 0x00000001 -#define FLASH_FSM_ST_MACHINE_OVERRIDE_S 0 +#define FLASH_FSM_ST_MACHINE_OVERRIDE 0x00000001 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_BITN 0 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_M 0x00000001 +#define FLASH_FSM_ST_MACHINE_OVERRIDE_S 0 //***************************************************************************** // @@ -2823,16 +2823,16 @@ // Field: [11:8] BLK_TIOTP // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_FLES_BLK_TIOTP_W 4 -#define FLASH_FSM_FLES_BLK_TIOTP_M 0x00000F00 -#define FLASH_FSM_FLES_BLK_TIOTP_S 8 +#define FLASH_FSM_FLES_BLK_TIOTP_W 4 +#define FLASH_FSM_FLES_BLK_TIOTP_M 0x00000F00 +#define FLASH_FSM_FLES_BLK_TIOTP_S 8 // Field: [7:0] BLK_OTP // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_FLES_BLK_OTP_W 8 -#define FLASH_FSM_FLES_BLK_OTP_M 0x000000FF -#define FLASH_FSM_FLES_BLK_OTP_S 0 +#define FLASH_FSM_FLES_BLK_OTP_W 8 +#define FLASH_FSM_FLES_BLK_OTP_M 0x000000FF +#define FLASH_FSM_FLES_BLK_OTP_S 0 //***************************************************************************** // @@ -2842,9 +2842,9 @@ // Field: [2:0] WR_ENA // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_WR_ENA_WR_ENA_W 3 -#define FLASH_FSM_WR_ENA_WR_ENA_M 0x00000007 -#define FLASH_FSM_WR_ENA_WR_ENA_S 0 +#define FLASH_FSM_WR_ENA_WR_ENA_W 3 +#define FLASH_FSM_WR_ENA_WR_ENA_M 0x00000007 +#define FLASH_FSM_WR_ENA_WR_ENA_S 0 //***************************************************************************** // @@ -2854,9 +2854,9 @@ // Field: [31:0] FSM_ACC_PP // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ACC_PP_FSM_ACC_PP_W 32 -#define FLASH_FSM_ACC_PP_FSM_ACC_PP_M 0xFFFFFFFF -#define FLASH_FSM_ACC_PP_FSM_ACC_PP_S 0 +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_W 32 +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_M 0xFFFFFFFF +#define FLASH_FSM_ACC_PP_FSM_ACC_PP_S 0 //***************************************************************************** // @@ -2866,9 +2866,9 @@ // Field: [15:0] ACC_EP // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ACC_EP_ACC_EP_W 16 -#define FLASH_FSM_ACC_EP_ACC_EP_M 0x0000FFFF -#define FLASH_FSM_ACC_EP_ACC_EP_S 0 +#define FLASH_FSM_ACC_EP_ACC_EP_W 16 +#define FLASH_FSM_ACC_EP_ACC_EP_M 0x0000FFFF +#define FLASH_FSM_ACC_EP_ACC_EP_S 0 //***************************************************************************** // @@ -2878,16 +2878,16 @@ // Field: [30:28] BANK // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ADDR_BANK_W 3 -#define FLASH_FSM_ADDR_BANK_M 0x70000000 -#define FLASH_FSM_ADDR_BANK_S 28 +#define FLASH_FSM_ADDR_BANK_W 3 +#define FLASH_FSM_ADDR_BANK_M 0x70000000 +#define FLASH_FSM_ADDR_BANK_S 28 // Field: [27:0] CUR_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ADDR_CUR_ADDR_W 28 -#define FLASH_FSM_ADDR_CUR_ADDR_M 0x0FFFFFFF -#define FLASH_FSM_ADDR_CUR_ADDR_S 0 +#define FLASH_FSM_ADDR_CUR_ADDR_W 28 +#define FLASH_FSM_ADDR_CUR_ADDR_M 0x0FFFFFFF +#define FLASH_FSM_ADDR_CUR_ADDR_S 0 //***************************************************************************** // @@ -2897,30 +2897,30 @@ // Field: [31:16] SECT_ERASED // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR_SECT_ERASED_W 16 -#define FLASH_FSM_SECTOR_SECT_ERASED_M 0xFFFF0000 -#define FLASH_FSM_SECTOR_SECT_ERASED_S 16 +#define FLASH_FSM_SECTOR_SECT_ERASED_W 16 +#define FLASH_FSM_SECTOR_SECT_ERASED_M 0xFFFF0000 +#define FLASH_FSM_SECTOR_SECT_ERASED_S 16 // Field: [15:8] FSM_SECTOR_EXTENSION // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_W 8 -#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_M 0x0000FF00 -#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_S 8 +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_W 8 +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_M 0x0000FF00 +#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_S 8 // Field: [7:4] SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR_SECTOR_W 4 -#define FLASH_FSM_SECTOR_SECTOR_M 0x000000F0 -#define FLASH_FSM_SECTOR_SECTOR_S 4 +#define FLASH_FSM_SECTOR_SECTOR_W 4 +#define FLASH_FSM_SECTOR_SECTOR_M 0x000000F0 +#define FLASH_FSM_SECTOR_SECTOR_S 4 // Field: [3:0] SEC_OUT // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR_SEC_OUT_W 4 -#define FLASH_FSM_SECTOR_SEC_OUT_M 0x0000000F -#define FLASH_FSM_SECTOR_SEC_OUT_S 0 +#define FLASH_FSM_SECTOR_SEC_OUT_W 4 +#define FLASH_FSM_SECTOR_SEC_OUT_M 0x0000000F +#define FLASH_FSM_SECTOR_SEC_OUT_S 0 //***************************************************************************** // @@ -2930,16 +2930,16 @@ // Field: [31:12] MOD_VERSION // // Internal. Only to be used through TI provided API. -#define FLASH_FMC_REV_ID_MOD_VERSION_W 20 -#define FLASH_FMC_REV_ID_MOD_VERSION_M 0xFFFFF000 -#define FLASH_FMC_REV_ID_MOD_VERSION_S 12 +#define FLASH_FMC_REV_ID_MOD_VERSION_W 20 +#define FLASH_FMC_REV_ID_MOD_VERSION_M 0xFFFFF000 +#define FLASH_FMC_REV_ID_MOD_VERSION_S 12 // Field: [11:0] CONFIG_CRC // // Internal. Only to be used through TI provided API. -#define FLASH_FMC_REV_ID_CONFIG_CRC_W 12 -#define FLASH_FMC_REV_ID_CONFIG_CRC_M 0x00000FFF -#define FLASH_FMC_REV_ID_CONFIG_CRC_S 0 +#define FLASH_FMC_REV_ID_CONFIG_CRC_W 12 +#define FLASH_FMC_REV_ID_CONFIG_CRC_M 0x00000FFF +#define FLASH_FMC_REV_ID_CONFIG_CRC_S 0 //***************************************************************************** // @@ -2949,16 +2949,16 @@ // Field: [31:8] FSM_ERR_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_W 24 -#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_M 0xFFFFFF00 -#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_S 8 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_W 24 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_M 0xFFFFFF00 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_S 8 // Field: [3:0] FSM_ERR_BANK // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_W 4 -#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_M 0x0000000F -#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_S 0 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_W 4 +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_M 0x0000000F +#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_S 0 //***************************************************************************** // @@ -2968,9 +2968,9 @@ // Field: [11:0] FSM_PGM_MAXPUL // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_W 12 -#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_M 0x00000FFF -#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_S 0 +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_W 12 +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_M 0x00000FFF +#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_S 0 //***************************************************************************** // @@ -2980,16 +2980,16 @@ // Field: [19:16] SUSPEND_NOW // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_EXECUTE_SUSPEND_NOW_W 4 -#define FLASH_FSM_EXECUTE_SUSPEND_NOW_M 0x000F0000 -#define FLASH_FSM_EXECUTE_SUSPEND_NOW_S 16 +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_W 4 +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_M 0x000F0000 +#define FLASH_FSM_EXECUTE_SUSPEND_NOW_S 16 // Field: [4:0] FSMEXECUTE // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_EXECUTE_FSMEXECUTE_W 5 -#define FLASH_FSM_EXECUTE_FSMEXECUTE_M 0x0000001F -#define FLASH_FSM_EXECUTE_FSMEXECUTE_S 0 +#define FLASH_FSM_EXECUTE_FSMEXECUTE_W 5 +#define FLASH_FSM_EXECUTE_FSMEXECUTE_M 0x0000001F +#define FLASH_FSM_EXECUTE_FSMEXECUTE_S 0 //***************************************************************************** // @@ -2999,9 +2999,9 @@ // Field: [31:0] FSM_SECTOR1 // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR1_FSM_SECTOR1_W 32 -#define FLASH_FSM_SECTOR1_FSM_SECTOR1_M 0xFFFFFFFF -#define FLASH_FSM_SECTOR1_FSM_SECTOR1_S 0 +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_W 32 +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_M 0xFFFFFFFF +#define FLASH_FSM_SECTOR1_FSM_SECTOR1_S 0 //***************************************************************************** // @@ -3011,9 +3011,9 @@ // Field: [31:0] FSM_SECTOR2 // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR2_FSM_SECTOR2_W 32 -#define FLASH_FSM_SECTOR2_FSM_SECTOR2_M 0xFFFFFFFF -#define FLASH_FSM_SECTOR2_FSM_SECTOR2_S 0 +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_W 32 +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_M 0xFFFFFFFF +#define FLASH_FSM_SECTOR2_FSM_SECTOR2_S 0 //***************************************************************************** // @@ -3023,9 +3023,9 @@ // Field: [31:0] FSM_BSLE0 // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_BSLE0_FSM_BSLE0_W 32 -#define FLASH_FSM_BSLE0_FSM_BSLE0_M 0xFFFFFFFF -#define FLASH_FSM_BSLE0_FSM_BSLE0_S 0 +#define FLASH_FSM_BSLE0_FSM_BSLE0_W 32 +#define FLASH_FSM_BSLE0_FSM_BSLE0_M 0xFFFFFFFF +#define FLASH_FSM_BSLE0_FSM_BSLE0_S 0 //***************************************************************************** // @@ -3035,9 +3035,9 @@ // Field: [31:0] FSM_BSL1 // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_BSLE1_FSM_BSL1_W 32 -#define FLASH_FSM_BSLE1_FSM_BSL1_M 0xFFFFFFFF -#define FLASH_FSM_BSLE1_FSM_BSL1_S 0 +#define FLASH_FSM_BSLE1_FSM_BSL1_W 32 +#define FLASH_FSM_BSLE1_FSM_BSL1_M 0xFFFFFFFF +#define FLASH_FSM_BSLE1_FSM_BSL1_S 0 //***************************************************************************** // @@ -3047,9 +3047,9 @@ // Field: [31:0] FSM_BSLP0 // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_BSLP0_FSM_BSLP0_W 32 -#define FLASH_FSM_BSLP0_FSM_BSLP0_M 0xFFFFFFFF -#define FLASH_FSM_BSLP0_FSM_BSLP0_S 0 +#define FLASH_FSM_BSLP0_FSM_BSLP0_W 32 +#define FLASH_FSM_BSLP0_FSM_BSLP0_M 0xFFFFFFFF +#define FLASH_FSM_BSLP0_FSM_BSLP0_S 0 //***************************************************************************** // @@ -3059,9 +3059,9 @@ // Field: [31:0] FSM_BSL1 // // Internal. Only to be used through TI provided API. -#define FLASH_FSM_BSLP1_FSM_BSL1_W 32 -#define FLASH_FSM_BSLP1_FSM_BSL1_M 0xFFFFFFFF -#define FLASH_FSM_BSLP1_FSM_BSL1_S 0 +#define FLASH_FSM_BSLP1_FSM_BSL1_W 32 +#define FLASH_FSM_BSLP1_FSM_BSL1_M 0xFFFFFFFF +#define FLASH_FSM_BSLP1_FSM_BSL1_S 0 //***************************************************************************** // @@ -3071,30 +3071,30 @@ // Field: [31:20] EE_BANK_WIDTH // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BANK_EE_BANK_WIDTH_W 12 -#define FLASH_FCFG_BANK_EE_BANK_WIDTH_M 0xFFF00000 -#define FLASH_FCFG_BANK_EE_BANK_WIDTH_S 20 +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_W 12 +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_M 0xFFF00000 +#define FLASH_FCFG_BANK_EE_BANK_WIDTH_S 20 // Field: [19:16] EE_NUM_BANK // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BANK_EE_NUM_BANK_W 4 -#define FLASH_FCFG_BANK_EE_NUM_BANK_M 0x000F0000 -#define FLASH_FCFG_BANK_EE_NUM_BANK_S 16 +#define FLASH_FCFG_BANK_EE_NUM_BANK_W 4 +#define FLASH_FCFG_BANK_EE_NUM_BANK_M 0x000F0000 +#define FLASH_FCFG_BANK_EE_NUM_BANK_S 16 // Field: [15:4] MAIN_BANK_WIDTH // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_W 12 -#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M 0x0000FFF0 -#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S 4 +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_W 12 +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M 0x0000FFF0 +#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S 4 // Field: [3:0] MAIN_NUM_BANK // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BANK_MAIN_NUM_BANK_W 4 -#define FLASH_FCFG_BANK_MAIN_NUM_BANK_M 0x0000000F -#define FLASH_FCFG_BANK_MAIN_NUM_BANK_S 0 +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_W 4 +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_M 0x0000000F +#define FLASH_FCFG_BANK_MAIN_NUM_BANK_S 0 //***************************************************************************** // @@ -3104,84 +3104,84 @@ // Field: [31:24] FAMILY_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_W 8 -#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_M 0xFF000000 -#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_S 24 +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_W 8 +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_M 0xFF000000 +#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_S 24 // Field: [20] MEM_MAP // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_MEM_MAP 0x00100000 -#define FLASH_FCFG_WRAPPER_MEM_MAP_BITN 20 -#define FLASH_FCFG_WRAPPER_MEM_MAP_M 0x00100000 -#define FLASH_FCFG_WRAPPER_MEM_MAP_S 20 +#define FLASH_FCFG_WRAPPER_MEM_MAP 0x00100000 +#define FLASH_FCFG_WRAPPER_MEM_MAP_BITN 20 +#define FLASH_FCFG_WRAPPER_MEM_MAP_M 0x00100000 +#define FLASH_FCFG_WRAPPER_MEM_MAP_S 20 // Field: [19:16] CPU2 // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_CPU2_W 4 -#define FLASH_FCFG_WRAPPER_CPU2_M 0x000F0000 -#define FLASH_FCFG_WRAPPER_CPU2_S 16 +#define FLASH_FCFG_WRAPPER_CPU2_W 4 +#define FLASH_FCFG_WRAPPER_CPU2_M 0x000F0000 +#define FLASH_FCFG_WRAPPER_CPU2_S 16 // Field: [15:12] EE_IN_MAIN // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_W 4 -#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_M 0x0000F000 -#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_S 12 +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_W 4 +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_M 0x0000F000 +#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_S 12 // Field: [11] ROM // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_ROM 0x00000800 -#define FLASH_FCFG_WRAPPER_ROM_BITN 11 -#define FLASH_FCFG_WRAPPER_ROM_M 0x00000800 -#define FLASH_FCFG_WRAPPER_ROM_S 11 +#define FLASH_FCFG_WRAPPER_ROM 0x00000800 +#define FLASH_FCFG_WRAPPER_ROM_BITN 11 +#define FLASH_FCFG_WRAPPER_ROM_M 0x00000800 +#define FLASH_FCFG_WRAPPER_ROM_S 11 // Field: [10] IFLUSH // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_IFLUSH 0x00000400 -#define FLASH_FCFG_WRAPPER_IFLUSH_BITN 10 -#define FLASH_FCFG_WRAPPER_IFLUSH_M 0x00000400 -#define FLASH_FCFG_WRAPPER_IFLUSH_S 10 +#define FLASH_FCFG_WRAPPER_IFLUSH 0x00000400 +#define FLASH_FCFG_WRAPPER_IFLUSH_BITN 10 +#define FLASH_FCFG_WRAPPER_IFLUSH_M 0x00000400 +#define FLASH_FCFG_WRAPPER_IFLUSH_S 10 // Field: [9] SIL3 // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_SIL3 0x00000200 -#define FLASH_FCFG_WRAPPER_SIL3_BITN 9 -#define FLASH_FCFG_WRAPPER_SIL3_M 0x00000200 -#define FLASH_FCFG_WRAPPER_SIL3_S 9 +#define FLASH_FCFG_WRAPPER_SIL3 0x00000200 +#define FLASH_FCFG_WRAPPER_SIL3_BITN 9 +#define FLASH_FCFG_WRAPPER_SIL3_M 0x00000200 +#define FLASH_FCFG_WRAPPER_SIL3_S 9 // Field: [8] ECCA // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_ECCA 0x00000100 -#define FLASH_FCFG_WRAPPER_ECCA_BITN 8 -#define FLASH_FCFG_WRAPPER_ECCA_M 0x00000100 -#define FLASH_FCFG_WRAPPER_ECCA_S 8 +#define FLASH_FCFG_WRAPPER_ECCA 0x00000100 +#define FLASH_FCFG_WRAPPER_ECCA_BITN 8 +#define FLASH_FCFG_WRAPPER_ECCA_M 0x00000100 +#define FLASH_FCFG_WRAPPER_ECCA_S 8 // Field: [7:6] AUTO_SUSP // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_AUTO_SUSP_W 2 -#define FLASH_FCFG_WRAPPER_AUTO_SUSP_M 0x000000C0 -#define FLASH_FCFG_WRAPPER_AUTO_SUSP_S 6 +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_W 2 +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_M 0x000000C0 +#define FLASH_FCFG_WRAPPER_AUTO_SUSP_S 6 // Field: [5:4] UERR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_UERR_W 2 -#define FLASH_FCFG_WRAPPER_UERR_M 0x00000030 -#define FLASH_FCFG_WRAPPER_UERR_S 4 +#define FLASH_FCFG_WRAPPER_UERR_W 2 +#define FLASH_FCFG_WRAPPER_UERR_M 0x00000030 +#define FLASH_FCFG_WRAPPER_UERR_S 4 // Field: [3:0] CPU_TYPE1 // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_CPU_TYPE1_W 4 -#define FLASH_FCFG_WRAPPER_CPU_TYPE1_M 0x0000000F -#define FLASH_FCFG_WRAPPER_CPU_TYPE1_S 0 +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_W 4 +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_M 0x0000000F +#define FLASH_FCFG_WRAPPER_CPU_TYPE1_S 0 //***************************************************************************** // @@ -3191,58 +3191,58 @@ // Field: [31:28] B7_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B7_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B7_TYPE_M 0xF0000000 -#define FLASH_FCFG_BNK_TYPE_B7_TYPE_S 28 +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_M 0xF0000000 +#define FLASH_FCFG_BNK_TYPE_B7_TYPE_S 28 // Field: [27:24] B6_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B6_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B6_TYPE_M 0x0F000000 -#define FLASH_FCFG_BNK_TYPE_B6_TYPE_S 24 +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_M 0x0F000000 +#define FLASH_FCFG_BNK_TYPE_B6_TYPE_S 24 // Field: [23:20] B5_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B5_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B5_TYPE_M 0x00F00000 -#define FLASH_FCFG_BNK_TYPE_B5_TYPE_S 20 +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_M 0x00F00000 +#define FLASH_FCFG_BNK_TYPE_B5_TYPE_S 20 // Field: [19:16] B4_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B4_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B4_TYPE_M 0x000F0000 -#define FLASH_FCFG_BNK_TYPE_B4_TYPE_S 16 +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_M 0x000F0000 +#define FLASH_FCFG_BNK_TYPE_B4_TYPE_S 16 // Field: [15:12] B3_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B3_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B3_TYPE_M 0x0000F000 -#define FLASH_FCFG_BNK_TYPE_B3_TYPE_S 12 +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_M 0x0000F000 +#define FLASH_FCFG_BNK_TYPE_B3_TYPE_S 12 // Field: [11:8] B2_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B2_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B2_TYPE_M 0x00000F00 -#define FLASH_FCFG_BNK_TYPE_B2_TYPE_S 8 +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_M 0x00000F00 +#define FLASH_FCFG_BNK_TYPE_B2_TYPE_S 8 // Field: [7:4] B1_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B1_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B1_TYPE_M 0x000000F0 -#define FLASH_FCFG_BNK_TYPE_B1_TYPE_S 4 +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_M 0x000000F0 +#define FLASH_FCFG_BNK_TYPE_B1_TYPE_S 4 // Field: [3:0] B0_TYPE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B0_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B0_TYPE_M 0x0000000F -#define FLASH_FCFG_BNK_TYPE_B0_TYPE_S 0 +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_W 4 +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_M 0x0000000F +#define FLASH_FCFG_BNK_TYPE_B0_TYPE_S 0 //***************************************************************************** // @@ -3252,23 +3252,23 @@ // Field: [31:28] B0_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_W 4 -#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_S 28 +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_W 4 +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_S 28 // Field: [27:24] B0_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_W 4 -#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_S 24 +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_W 4 +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_S 24 // Field: [23:0] B0_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_START_B0_START_ADDR_W 24 -#define FLASH_FCFG_B0_START_B0_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B0_START_B0_START_ADDR_S 0 +#define FLASH_FCFG_B0_START_B0_START_ADDR_W 24 +#define FLASH_FCFG_B0_START_B0_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B0_START_B0_START_ADDR_S 0 //***************************************************************************** // @@ -3278,23 +3278,23 @@ // Field: [31:28] B1_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_W 4 -#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_S 28 +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_W 4 +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_S 28 // Field: [27:24] B1_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_W 4 -#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_S 24 +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_W 4 +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_S 24 // Field: [23:0] B1_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B1_START_B1_START_ADDR_W 24 -#define FLASH_FCFG_B1_START_B1_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B1_START_B1_START_ADDR_S 0 +#define FLASH_FCFG_B1_START_B1_START_ADDR_W 24 +#define FLASH_FCFG_B1_START_B1_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B1_START_B1_START_ADDR_S 0 //***************************************************************************** // @@ -3304,23 +3304,23 @@ // Field: [31:28] B2_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_W 4 -#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_S 28 +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_W 4 +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_S 28 // Field: [27:24] B2_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_W 4 -#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_S 24 +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_W 4 +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_S 24 // Field: [23:0] B2_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B2_START_B2_START_ADDR_W 24 -#define FLASH_FCFG_B2_START_B2_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B2_START_B2_START_ADDR_S 0 +#define FLASH_FCFG_B2_START_B2_START_ADDR_W 24 +#define FLASH_FCFG_B2_START_B2_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B2_START_B2_START_ADDR_S 0 //***************************************************************************** // @@ -3330,23 +3330,23 @@ // Field: [31:28] B3_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_W 4 -#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_S 28 +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_W 4 +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_S 28 // Field: [27:24] B3_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_W 4 -#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_S 24 +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_W 4 +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_S 24 // Field: [23:0] B3_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B3_START_B3_START_ADDR_W 24 -#define FLASH_FCFG_B3_START_B3_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B3_START_B3_START_ADDR_S 0 +#define FLASH_FCFG_B3_START_B3_START_ADDR_W 24 +#define FLASH_FCFG_B3_START_B3_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B3_START_B3_START_ADDR_S 0 //***************************************************************************** // @@ -3356,23 +3356,23 @@ // Field: [31:28] B4_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_W 4 -#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_S 28 +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_W 4 +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_S 28 // Field: [27:24] B4_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_W 4 -#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_S 24 +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_W 4 +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_S 24 // Field: [23:0] B4_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B4_START_B4_START_ADDR_W 24 -#define FLASH_FCFG_B4_START_B4_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B4_START_B4_START_ADDR_S 0 +#define FLASH_FCFG_B4_START_B4_START_ADDR_W 24 +#define FLASH_FCFG_B4_START_B4_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B4_START_B4_START_ADDR_S 0 //***************************************************************************** // @@ -3382,23 +3382,23 @@ // Field: [31:28] B5_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_W 4 -#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_S 28 +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_W 4 +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_S 28 // Field: [27:24] B5_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_W 4 -#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_S 24 +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_W 4 +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_S 24 // Field: [23:0] B5_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B5_START_B5_START_ADDR_W 24 -#define FLASH_FCFG_B5_START_B5_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B5_START_B5_START_ADDR_S 0 +#define FLASH_FCFG_B5_START_B5_START_ADDR_W 24 +#define FLASH_FCFG_B5_START_B5_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B5_START_B5_START_ADDR_S 0 //***************************************************************************** // @@ -3408,23 +3408,23 @@ // Field: [31:28] B6_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_W 4 -#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_S 28 +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_W 4 +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_S 28 // Field: [27:24] B6_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_W 4 -#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_S 24 +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_W 4 +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_S 24 // Field: [23:0] B6_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B6_START_B6_START_ADDR_W 24 -#define FLASH_FCFG_B6_START_B6_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B6_START_B6_START_ADDR_S 0 +#define FLASH_FCFG_B6_START_B6_START_ADDR_W 24 +#define FLASH_FCFG_B6_START_B6_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B6_START_B6_START_ADDR_S 0 //***************************************************************************** // @@ -3434,23 +3434,23 @@ // Field: [31:28] B7_MAX_SECTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_W 4 -#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_S 28 +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_W 4 +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_M 0xF0000000 +#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_S 28 // Field: [27:24] B7_MUX_FACTOR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_W 4 -#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_S 24 +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_W 4 +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_M 0x0F000000 +#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_S 24 // Field: [23:0] B7_START_ADDR // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B7_START_B7_START_ADDR_W 24 -#define FLASH_FCFG_B7_START_B7_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B7_START_B7_START_ADDR_S 0 +#define FLASH_FCFG_B7_START_B7_START_ADDR_W 24 +#define FLASH_FCFG_B7_START_B7_START_ADDR_M 0x00FFFFFF +#define FLASH_FCFG_B7_START_B7_START_ADDR_S 0 //***************************************************************************** // @@ -3460,16 +3460,15 @@ // Field: [27:16] B0_NUM_SECTORS // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_W 12 -#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_M 0x0FFF0000 -#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_S 16 +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_W 12 +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_M 0x0FFF0000 +#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_S 16 // Field: [3:0] B0_SECT_SIZE // // Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_W 4 -#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M 0x0000000F -#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S 0 - +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_W 4 +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M 0x0000000F +#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S 0 #endif // __FLASH__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_gpio.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_gpio.h index 98f51c9..e0603f1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_gpio.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_gpio.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_gpio_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_gpio_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_GPIO_H__ #define __HW_GPIO_H__ @@ -44,49 +44,49 @@ // //***************************************************************************** // Data Out 0 to 3 -#define GPIO_O_DOUT3_0 0x00000000 +#define GPIO_O_DOUT3_0 0x00000000 // Data Out 4 to 7 -#define GPIO_O_DOUT7_4 0x00000004 +#define GPIO_O_DOUT7_4 0x00000004 // Data Out 8 to 11 -#define GPIO_O_DOUT11_8 0x00000008 +#define GPIO_O_DOUT11_8 0x00000008 // Data Out 12 to 15 -#define GPIO_O_DOUT15_12 0x0000000C +#define GPIO_O_DOUT15_12 0x0000000C // Data Out 16 to 19 -#define GPIO_O_DOUT19_16 0x00000010 +#define GPIO_O_DOUT19_16 0x00000010 // Data Out 20 to 23 -#define GPIO_O_DOUT23_20 0x00000014 +#define GPIO_O_DOUT23_20 0x00000014 // Data Out 24 to 27 -#define GPIO_O_DOUT27_24 0x00000018 +#define GPIO_O_DOUT27_24 0x00000018 // Data Out 28 to 31 -#define GPIO_O_DOUT31_28 0x0000001C +#define GPIO_O_DOUT31_28 0x0000001C // Data Output for DIO 0 to 31 -#define GPIO_O_DOUT31_0 0x00000080 +#define GPIO_O_DOUT31_0 0x00000080 // Data Out Set -#define GPIO_O_DOUTSET31_0 0x00000090 +#define GPIO_O_DOUTSET31_0 0x00000090 // Data Out Clear -#define GPIO_O_DOUTCLR31_0 0x000000A0 +#define GPIO_O_DOUTCLR31_0 0x000000A0 // Data Out Toggle -#define GPIO_O_DOUTTGL31_0 0x000000B0 +#define GPIO_O_DOUTTGL31_0 0x000000B0 // Data Input from DIO 0 to 31 -#define GPIO_O_DIN31_0 0x000000C0 +#define GPIO_O_DIN31_0 0x000000C0 // Data Output Enable for DIO 0 to 31 -#define GPIO_O_DOE31_0 0x000000D0 +#define GPIO_O_DOE31_0 0x000000D0 // Event Register for DIO 0 to 31 -#define GPIO_O_EVFLAGS31_0 0x000000E0 +#define GPIO_O_EVFLAGS31_0 0x000000E0 //***************************************************************************** // @@ -97,37 +97,37 @@ // // Sets the state of the pin that is configured as DIO#3, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT3_0_DIO3 0x01000000 -#define GPIO_DOUT3_0_DIO3_BITN 24 -#define GPIO_DOUT3_0_DIO3_M 0x01000000 -#define GPIO_DOUT3_0_DIO3_S 24 +#define GPIO_DOUT3_0_DIO3 0x01000000 +#define GPIO_DOUT3_0_DIO3_BITN 24 +#define GPIO_DOUT3_0_DIO3_M 0x01000000 +#define GPIO_DOUT3_0_DIO3_S 24 // Field: [16] DIO2 // // Sets the state of the pin that is configured as DIO#2, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT3_0_DIO2 0x00010000 -#define GPIO_DOUT3_0_DIO2_BITN 16 -#define GPIO_DOUT3_0_DIO2_M 0x00010000 -#define GPIO_DOUT3_0_DIO2_S 16 +#define GPIO_DOUT3_0_DIO2 0x00010000 +#define GPIO_DOUT3_0_DIO2_BITN 16 +#define GPIO_DOUT3_0_DIO2_M 0x00010000 +#define GPIO_DOUT3_0_DIO2_S 16 // Field: [8] DIO1 // // Sets the state of the pin that is configured as DIO#1, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT3_0_DIO1 0x00000100 -#define GPIO_DOUT3_0_DIO1_BITN 8 -#define GPIO_DOUT3_0_DIO1_M 0x00000100 -#define GPIO_DOUT3_0_DIO1_S 8 +#define GPIO_DOUT3_0_DIO1 0x00000100 +#define GPIO_DOUT3_0_DIO1_BITN 8 +#define GPIO_DOUT3_0_DIO1_M 0x00000100 +#define GPIO_DOUT3_0_DIO1_S 8 // Field: [0] DIO0 // // Sets the state of the pin that is configured as DIO#0, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT3_0_DIO0 0x00000001 -#define GPIO_DOUT3_0_DIO0_BITN 0 -#define GPIO_DOUT3_0_DIO0_M 0x00000001 -#define GPIO_DOUT3_0_DIO0_S 0 +#define GPIO_DOUT3_0_DIO0 0x00000001 +#define GPIO_DOUT3_0_DIO0_BITN 0 +#define GPIO_DOUT3_0_DIO0_M 0x00000001 +#define GPIO_DOUT3_0_DIO0_S 0 //***************************************************************************** // @@ -138,37 +138,37 @@ // // Sets the state of the pin that is configured as DIO#7, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT7_4_DIO7 0x01000000 -#define GPIO_DOUT7_4_DIO7_BITN 24 -#define GPIO_DOUT7_4_DIO7_M 0x01000000 -#define GPIO_DOUT7_4_DIO7_S 24 +#define GPIO_DOUT7_4_DIO7 0x01000000 +#define GPIO_DOUT7_4_DIO7_BITN 24 +#define GPIO_DOUT7_4_DIO7_M 0x01000000 +#define GPIO_DOUT7_4_DIO7_S 24 // Field: [16] DIO6 // // Sets the state of the pin that is configured as DIO#6, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT7_4_DIO6 0x00010000 -#define GPIO_DOUT7_4_DIO6_BITN 16 -#define GPIO_DOUT7_4_DIO6_M 0x00010000 -#define GPIO_DOUT7_4_DIO6_S 16 +#define GPIO_DOUT7_4_DIO6 0x00010000 +#define GPIO_DOUT7_4_DIO6_BITN 16 +#define GPIO_DOUT7_4_DIO6_M 0x00010000 +#define GPIO_DOUT7_4_DIO6_S 16 // Field: [8] DIO5 // // Sets the state of the pin that is configured as DIO#5, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT7_4_DIO5 0x00000100 -#define GPIO_DOUT7_4_DIO5_BITN 8 -#define GPIO_DOUT7_4_DIO5_M 0x00000100 -#define GPIO_DOUT7_4_DIO5_S 8 +#define GPIO_DOUT7_4_DIO5 0x00000100 +#define GPIO_DOUT7_4_DIO5_BITN 8 +#define GPIO_DOUT7_4_DIO5_M 0x00000100 +#define GPIO_DOUT7_4_DIO5_S 8 // Field: [0] DIO4 // // Sets the state of the pin that is configured as DIO#4, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT7_4_DIO4 0x00000001 -#define GPIO_DOUT7_4_DIO4_BITN 0 -#define GPIO_DOUT7_4_DIO4_M 0x00000001 -#define GPIO_DOUT7_4_DIO4_S 0 +#define GPIO_DOUT7_4_DIO4 0x00000001 +#define GPIO_DOUT7_4_DIO4_BITN 0 +#define GPIO_DOUT7_4_DIO4_M 0x00000001 +#define GPIO_DOUT7_4_DIO4_S 0 //***************************************************************************** // @@ -179,37 +179,37 @@ // // Sets the state of the pin that is configured as DIO#11, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT11_8_DIO11 0x01000000 -#define GPIO_DOUT11_8_DIO11_BITN 24 -#define GPIO_DOUT11_8_DIO11_M 0x01000000 -#define GPIO_DOUT11_8_DIO11_S 24 +#define GPIO_DOUT11_8_DIO11 0x01000000 +#define GPIO_DOUT11_8_DIO11_BITN 24 +#define GPIO_DOUT11_8_DIO11_M 0x01000000 +#define GPIO_DOUT11_8_DIO11_S 24 // Field: [16] DIO10 // // Sets the state of the pin that is configured as DIO#10, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT11_8_DIO10 0x00010000 -#define GPIO_DOUT11_8_DIO10_BITN 16 -#define GPIO_DOUT11_8_DIO10_M 0x00010000 -#define GPIO_DOUT11_8_DIO10_S 16 +#define GPIO_DOUT11_8_DIO10 0x00010000 +#define GPIO_DOUT11_8_DIO10_BITN 16 +#define GPIO_DOUT11_8_DIO10_M 0x00010000 +#define GPIO_DOUT11_8_DIO10_S 16 // Field: [8] DIO9 // // Sets the state of the pin that is configured as DIO#9, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT11_8_DIO9 0x00000100 -#define GPIO_DOUT11_8_DIO9_BITN 8 -#define GPIO_DOUT11_8_DIO9_M 0x00000100 -#define GPIO_DOUT11_8_DIO9_S 8 +#define GPIO_DOUT11_8_DIO9 0x00000100 +#define GPIO_DOUT11_8_DIO9_BITN 8 +#define GPIO_DOUT11_8_DIO9_M 0x00000100 +#define GPIO_DOUT11_8_DIO9_S 8 // Field: [0] DIO8 // // Sets the state of the pin that is configured as DIO#8, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT11_8_DIO8 0x00000001 -#define GPIO_DOUT11_8_DIO8_BITN 0 -#define GPIO_DOUT11_8_DIO8_M 0x00000001 -#define GPIO_DOUT11_8_DIO8_S 0 +#define GPIO_DOUT11_8_DIO8 0x00000001 +#define GPIO_DOUT11_8_DIO8_BITN 0 +#define GPIO_DOUT11_8_DIO8_M 0x00000001 +#define GPIO_DOUT11_8_DIO8_S 0 //***************************************************************************** // @@ -220,37 +220,37 @@ // // Sets the state of the pin that is configured as DIO#15, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT15_12_DIO15 0x01000000 -#define GPIO_DOUT15_12_DIO15_BITN 24 -#define GPIO_DOUT15_12_DIO15_M 0x01000000 -#define GPIO_DOUT15_12_DIO15_S 24 +#define GPIO_DOUT15_12_DIO15 0x01000000 +#define GPIO_DOUT15_12_DIO15_BITN 24 +#define GPIO_DOUT15_12_DIO15_M 0x01000000 +#define GPIO_DOUT15_12_DIO15_S 24 // Field: [16] DIO14 // // Sets the state of the pin that is configured as DIO#14, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT15_12_DIO14 0x00010000 -#define GPIO_DOUT15_12_DIO14_BITN 16 -#define GPIO_DOUT15_12_DIO14_M 0x00010000 -#define GPIO_DOUT15_12_DIO14_S 16 +#define GPIO_DOUT15_12_DIO14 0x00010000 +#define GPIO_DOUT15_12_DIO14_BITN 16 +#define GPIO_DOUT15_12_DIO14_M 0x00010000 +#define GPIO_DOUT15_12_DIO14_S 16 // Field: [8] DIO13 // // Sets the state of the pin that is configured as DIO#13, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT15_12_DIO13 0x00000100 -#define GPIO_DOUT15_12_DIO13_BITN 8 -#define GPIO_DOUT15_12_DIO13_M 0x00000100 -#define GPIO_DOUT15_12_DIO13_S 8 +#define GPIO_DOUT15_12_DIO13 0x00000100 +#define GPIO_DOUT15_12_DIO13_BITN 8 +#define GPIO_DOUT15_12_DIO13_M 0x00000100 +#define GPIO_DOUT15_12_DIO13_S 8 // Field: [0] DIO12 // // Sets the state of the pin that is configured as DIO#12, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT15_12_DIO12 0x00000001 -#define GPIO_DOUT15_12_DIO12_BITN 0 -#define GPIO_DOUT15_12_DIO12_M 0x00000001 -#define GPIO_DOUT15_12_DIO12_S 0 +#define GPIO_DOUT15_12_DIO12 0x00000001 +#define GPIO_DOUT15_12_DIO12_BITN 0 +#define GPIO_DOUT15_12_DIO12_M 0x00000001 +#define GPIO_DOUT15_12_DIO12_S 0 //***************************************************************************** // @@ -261,37 +261,37 @@ // // Sets the state of the pin that is configured as DIO#19, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT19_16_DIO19 0x01000000 -#define GPIO_DOUT19_16_DIO19_BITN 24 -#define GPIO_DOUT19_16_DIO19_M 0x01000000 -#define GPIO_DOUT19_16_DIO19_S 24 +#define GPIO_DOUT19_16_DIO19 0x01000000 +#define GPIO_DOUT19_16_DIO19_BITN 24 +#define GPIO_DOUT19_16_DIO19_M 0x01000000 +#define GPIO_DOUT19_16_DIO19_S 24 // Field: [16] DIO18 // // Sets the state of the pin that is configured as DIO#18, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT19_16_DIO18 0x00010000 -#define GPIO_DOUT19_16_DIO18_BITN 16 -#define GPIO_DOUT19_16_DIO18_M 0x00010000 -#define GPIO_DOUT19_16_DIO18_S 16 +#define GPIO_DOUT19_16_DIO18 0x00010000 +#define GPIO_DOUT19_16_DIO18_BITN 16 +#define GPIO_DOUT19_16_DIO18_M 0x00010000 +#define GPIO_DOUT19_16_DIO18_S 16 // Field: [8] DIO17 // // Sets the state of the pin that is configured as DIO#17, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT19_16_DIO17 0x00000100 -#define GPIO_DOUT19_16_DIO17_BITN 8 -#define GPIO_DOUT19_16_DIO17_M 0x00000100 -#define GPIO_DOUT19_16_DIO17_S 8 +#define GPIO_DOUT19_16_DIO17 0x00000100 +#define GPIO_DOUT19_16_DIO17_BITN 8 +#define GPIO_DOUT19_16_DIO17_M 0x00000100 +#define GPIO_DOUT19_16_DIO17_S 8 // Field: [0] DIO16 // // Sets the state of the pin that is configured as DIO#16, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT19_16_DIO16 0x00000001 -#define GPIO_DOUT19_16_DIO16_BITN 0 -#define GPIO_DOUT19_16_DIO16_M 0x00000001 -#define GPIO_DOUT19_16_DIO16_S 0 +#define GPIO_DOUT19_16_DIO16 0x00000001 +#define GPIO_DOUT19_16_DIO16_BITN 0 +#define GPIO_DOUT19_16_DIO16_M 0x00000001 +#define GPIO_DOUT19_16_DIO16_S 0 //***************************************************************************** // @@ -302,37 +302,37 @@ // // Sets the state of the pin that is configured as DIO#23, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT23_20_DIO23 0x01000000 -#define GPIO_DOUT23_20_DIO23_BITN 24 -#define GPIO_DOUT23_20_DIO23_M 0x01000000 -#define GPIO_DOUT23_20_DIO23_S 24 +#define GPIO_DOUT23_20_DIO23 0x01000000 +#define GPIO_DOUT23_20_DIO23_BITN 24 +#define GPIO_DOUT23_20_DIO23_M 0x01000000 +#define GPIO_DOUT23_20_DIO23_S 24 // Field: [16] DIO22 // // Sets the state of the pin that is configured as DIO#22, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT23_20_DIO22 0x00010000 -#define GPIO_DOUT23_20_DIO22_BITN 16 -#define GPIO_DOUT23_20_DIO22_M 0x00010000 -#define GPIO_DOUT23_20_DIO22_S 16 +#define GPIO_DOUT23_20_DIO22 0x00010000 +#define GPIO_DOUT23_20_DIO22_BITN 16 +#define GPIO_DOUT23_20_DIO22_M 0x00010000 +#define GPIO_DOUT23_20_DIO22_S 16 // Field: [8] DIO21 // // Sets the state of the pin that is configured as DIO#21, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT23_20_DIO21 0x00000100 -#define GPIO_DOUT23_20_DIO21_BITN 8 -#define GPIO_DOUT23_20_DIO21_M 0x00000100 -#define GPIO_DOUT23_20_DIO21_S 8 +#define GPIO_DOUT23_20_DIO21 0x00000100 +#define GPIO_DOUT23_20_DIO21_BITN 8 +#define GPIO_DOUT23_20_DIO21_M 0x00000100 +#define GPIO_DOUT23_20_DIO21_S 8 // Field: [0] DIO20 // // Sets the state of the pin that is configured as DIO#20, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT23_20_DIO20 0x00000001 -#define GPIO_DOUT23_20_DIO20_BITN 0 -#define GPIO_DOUT23_20_DIO20_M 0x00000001 -#define GPIO_DOUT23_20_DIO20_S 0 +#define GPIO_DOUT23_20_DIO20 0x00000001 +#define GPIO_DOUT23_20_DIO20_BITN 0 +#define GPIO_DOUT23_20_DIO20_M 0x00000001 +#define GPIO_DOUT23_20_DIO20_S 0 //***************************************************************************** // @@ -343,37 +343,37 @@ // // Sets the state of the pin that is configured as DIO#27, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT27_24_DIO27 0x01000000 -#define GPIO_DOUT27_24_DIO27_BITN 24 -#define GPIO_DOUT27_24_DIO27_M 0x01000000 -#define GPIO_DOUT27_24_DIO27_S 24 +#define GPIO_DOUT27_24_DIO27 0x01000000 +#define GPIO_DOUT27_24_DIO27_BITN 24 +#define GPIO_DOUT27_24_DIO27_M 0x01000000 +#define GPIO_DOUT27_24_DIO27_S 24 // Field: [16] DIO26 // // Sets the state of the pin that is configured as DIO#26, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT27_24_DIO26 0x00010000 -#define GPIO_DOUT27_24_DIO26_BITN 16 -#define GPIO_DOUT27_24_DIO26_M 0x00010000 -#define GPIO_DOUT27_24_DIO26_S 16 +#define GPIO_DOUT27_24_DIO26 0x00010000 +#define GPIO_DOUT27_24_DIO26_BITN 16 +#define GPIO_DOUT27_24_DIO26_M 0x00010000 +#define GPIO_DOUT27_24_DIO26_S 16 // Field: [8] DIO25 // // Sets the state of the pin that is configured as DIO#25, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT27_24_DIO25 0x00000100 -#define GPIO_DOUT27_24_DIO25_BITN 8 -#define GPIO_DOUT27_24_DIO25_M 0x00000100 -#define GPIO_DOUT27_24_DIO25_S 8 +#define GPIO_DOUT27_24_DIO25 0x00000100 +#define GPIO_DOUT27_24_DIO25_BITN 8 +#define GPIO_DOUT27_24_DIO25_M 0x00000100 +#define GPIO_DOUT27_24_DIO25_S 8 // Field: [0] DIO24 // // Sets the state of the pin that is configured as DIO#24, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT27_24_DIO24 0x00000001 -#define GPIO_DOUT27_24_DIO24_BITN 0 -#define GPIO_DOUT27_24_DIO24_M 0x00000001 -#define GPIO_DOUT27_24_DIO24_S 0 +#define GPIO_DOUT27_24_DIO24 0x00000001 +#define GPIO_DOUT27_24_DIO24_BITN 0 +#define GPIO_DOUT27_24_DIO24_M 0x00000001 +#define GPIO_DOUT27_24_DIO24_S 0 //***************************************************************************** // @@ -384,37 +384,37 @@ // // Sets the state of the pin that is configured as DIO#31, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT31_28_DIO31 0x01000000 -#define GPIO_DOUT31_28_DIO31_BITN 24 -#define GPIO_DOUT31_28_DIO31_M 0x01000000 -#define GPIO_DOUT31_28_DIO31_S 24 +#define GPIO_DOUT31_28_DIO31 0x01000000 +#define GPIO_DOUT31_28_DIO31_BITN 24 +#define GPIO_DOUT31_28_DIO31_M 0x01000000 +#define GPIO_DOUT31_28_DIO31_S 24 // Field: [16] DIO30 // // Sets the state of the pin that is configured as DIO#30, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT31_28_DIO30 0x00010000 -#define GPIO_DOUT31_28_DIO30_BITN 16 -#define GPIO_DOUT31_28_DIO30_M 0x00010000 -#define GPIO_DOUT31_28_DIO30_S 16 +#define GPIO_DOUT31_28_DIO30 0x00010000 +#define GPIO_DOUT31_28_DIO30_BITN 16 +#define GPIO_DOUT31_28_DIO30_M 0x00010000 +#define GPIO_DOUT31_28_DIO30_S 16 // Field: [8] DIO29 // // Sets the state of the pin that is configured as DIO#29, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT31_28_DIO29 0x00000100 -#define GPIO_DOUT31_28_DIO29_BITN 8 -#define GPIO_DOUT31_28_DIO29_M 0x00000100 -#define GPIO_DOUT31_28_DIO29_S 8 +#define GPIO_DOUT31_28_DIO29 0x00000100 +#define GPIO_DOUT31_28_DIO29_BITN 8 +#define GPIO_DOUT31_28_DIO29_M 0x00000100 +#define GPIO_DOUT31_28_DIO29_S 8 // Field: [0] DIO28 // // Sets the state of the pin that is configured as DIO#28, if the corresponding // DOE31_0 bitfield is set. -#define GPIO_DOUT31_28_DIO28 0x00000001 -#define GPIO_DOUT31_28_DIO28_BITN 0 -#define GPIO_DOUT31_28_DIO28_M 0x00000001 -#define GPIO_DOUT31_28_DIO28_S 0 +#define GPIO_DOUT31_28_DIO28 0x00000001 +#define GPIO_DOUT31_28_DIO28_BITN 0 +#define GPIO_DOUT31_28_DIO28_M 0x00000001 +#define GPIO_DOUT31_28_DIO28_S 0 //***************************************************************************** // @@ -424,258 +424,258 @@ // Field: [31] DIO31 // // Data output for DIO 31 -#define GPIO_DOUT31_0_DIO31 0x80000000 -#define GPIO_DOUT31_0_DIO31_BITN 31 -#define GPIO_DOUT31_0_DIO31_M 0x80000000 -#define GPIO_DOUT31_0_DIO31_S 31 +#define GPIO_DOUT31_0_DIO31 0x80000000 +#define GPIO_DOUT31_0_DIO31_BITN 31 +#define GPIO_DOUT31_0_DIO31_M 0x80000000 +#define GPIO_DOUT31_0_DIO31_S 31 // Field: [30] DIO30 // // Data output for DIO 30 -#define GPIO_DOUT31_0_DIO30 0x40000000 -#define GPIO_DOUT31_0_DIO30_BITN 30 -#define GPIO_DOUT31_0_DIO30_M 0x40000000 -#define GPIO_DOUT31_0_DIO30_S 30 +#define GPIO_DOUT31_0_DIO30 0x40000000 +#define GPIO_DOUT31_0_DIO30_BITN 30 +#define GPIO_DOUT31_0_DIO30_M 0x40000000 +#define GPIO_DOUT31_0_DIO30_S 30 // Field: [29] DIO29 // // Data output for DIO 29 -#define GPIO_DOUT31_0_DIO29 0x20000000 -#define GPIO_DOUT31_0_DIO29_BITN 29 -#define GPIO_DOUT31_0_DIO29_M 0x20000000 -#define GPIO_DOUT31_0_DIO29_S 29 +#define GPIO_DOUT31_0_DIO29 0x20000000 +#define GPIO_DOUT31_0_DIO29_BITN 29 +#define GPIO_DOUT31_0_DIO29_M 0x20000000 +#define GPIO_DOUT31_0_DIO29_S 29 // Field: [28] DIO28 // // Data output for DIO 28 -#define GPIO_DOUT31_0_DIO28 0x10000000 -#define GPIO_DOUT31_0_DIO28_BITN 28 -#define GPIO_DOUT31_0_DIO28_M 0x10000000 -#define GPIO_DOUT31_0_DIO28_S 28 +#define GPIO_DOUT31_0_DIO28 0x10000000 +#define GPIO_DOUT31_0_DIO28_BITN 28 +#define GPIO_DOUT31_0_DIO28_M 0x10000000 +#define GPIO_DOUT31_0_DIO28_S 28 // Field: [27] DIO27 // // Data output for DIO 27 -#define GPIO_DOUT31_0_DIO27 0x08000000 -#define GPIO_DOUT31_0_DIO27_BITN 27 -#define GPIO_DOUT31_0_DIO27_M 0x08000000 -#define GPIO_DOUT31_0_DIO27_S 27 +#define GPIO_DOUT31_0_DIO27 0x08000000 +#define GPIO_DOUT31_0_DIO27_BITN 27 +#define GPIO_DOUT31_0_DIO27_M 0x08000000 +#define GPIO_DOUT31_0_DIO27_S 27 // Field: [26] DIO26 // // Data output for DIO 26 -#define GPIO_DOUT31_0_DIO26 0x04000000 -#define GPIO_DOUT31_0_DIO26_BITN 26 -#define GPIO_DOUT31_0_DIO26_M 0x04000000 -#define GPIO_DOUT31_0_DIO26_S 26 +#define GPIO_DOUT31_0_DIO26 0x04000000 +#define GPIO_DOUT31_0_DIO26_BITN 26 +#define GPIO_DOUT31_0_DIO26_M 0x04000000 +#define GPIO_DOUT31_0_DIO26_S 26 // Field: [25] DIO25 // // Data output for DIO 25 -#define GPIO_DOUT31_0_DIO25 0x02000000 -#define GPIO_DOUT31_0_DIO25_BITN 25 -#define GPIO_DOUT31_0_DIO25_M 0x02000000 -#define GPIO_DOUT31_0_DIO25_S 25 +#define GPIO_DOUT31_0_DIO25 0x02000000 +#define GPIO_DOUT31_0_DIO25_BITN 25 +#define GPIO_DOUT31_0_DIO25_M 0x02000000 +#define GPIO_DOUT31_0_DIO25_S 25 // Field: [24] DIO24 // // Data output for DIO 24 -#define GPIO_DOUT31_0_DIO24 0x01000000 -#define GPIO_DOUT31_0_DIO24_BITN 24 -#define GPIO_DOUT31_0_DIO24_M 0x01000000 -#define GPIO_DOUT31_0_DIO24_S 24 +#define GPIO_DOUT31_0_DIO24 0x01000000 +#define GPIO_DOUT31_0_DIO24_BITN 24 +#define GPIO_DOUT31_0_DIO24_M 0x01000000 +#define GPIO_DOUT31_0_DIO24_S 24 // Field: [23] DIO23 // // Data output for DIO 23 -#define GPIO_DOUT31_0_DIO23 0x00800000 -#define GPIO_DOUT31_0_DIO23_BITN 23 -#define GPIO_DOUT31_0_DIO23_M 0x00800000 -#define GPIO_DOUT31_0_DIO23_S 23 +#define GPIO_DOUT31_0_DIO23 0x00800000 +#define GPIO_DOUT31_0_DIO23_BITN 23 +#define GPIO_DOUT31_0_DIO23_M 0x00800000 +#define GPIO_DOUT31_0_DIO23_S 23 // Field: [22] DIO22 // // Data output for DIO 22 -#define GPIO_DOUT31_0_DIO22 0x00400000 -#define GPIO_DOUT31_0_DIO22_BITN 22 -#define GPIO_DOUT31_0_DIO22_M 0x00400000 -#define GPIO_DOUT31_0_DIO22_S 22 +#define GPIO_DOUT31_0_DIO22 0x00400000 +#define GPIO_DOUT31_0_DIO22_BITN 22 +#define GPIO_DOUT31_0_DIO22_M 0x00400000 +#define GPIO_DOUT31_0_DIO22_S 22 // Field: [21] DIO21 // // Data output for DIO 21 -#define GPIO_DOUT31_0_DIO21 0x00200000 -#define GPIO_DOUT31_0_DIO21_BITN 21 -#define GPIO_DOUT31_0_DIO21_M 0x00200000 -#define GPIO_DOUT31_0_DIO21_S 21 +#define GPIO_DOUT31_0_DIO21 0x00200000 +#define GPIO_DOUT31_0_DIO21_BITN 21 +#define GPIO_DOUT31_0_DIO21_M 0x00200000 +#define GPIO_DOUT31_0_DIO21_S 21 // Field: [20] DIO20 // // Data output for DIO 20 -#define GPIO_DOUT31_0_DIO20 0x00100000 -#define GPIO_DOUT31_0_DIO20_BITN 20 -#define GPIO_DOUT31_0_DIO20_M 0x00100000 -#define GPIO_DOUT31_0_DIO20_S 20 +#define GPIO_DOUT31_0_DIO20 0x00100000 +#define GPIO_DOUT31_0_DIO20_BITN 20 +#define GPIO_DOUT31_0_DIO20_M 0x00100000 +#define GPIO_DOUT31_0_DIO20_S 20 // Field: [19] DIO19 // // Data output for DIO 19 -#define GPIO_DOUT31_0_DIO19 0x00080000 -#define GPIO_DOUT31_0_DIO19_BITN 19 -#define GPIO_DOUT31_0_DIO19_M 0x00080000 -#define GPIO_DOUT31_0_DIO19_S 19 +#define GPIO_DOUT31_0_DIO19 0x00080000 +#define GPIO_DOUT31_0_DIO19_BITN 19 +#define GPIO_DOUT31_0_DIO19_M 0x00080000 +#define GPIO_DOUT31_0_DIO19_S 19 // Field: [18] DIO18 // // Data output for DIO 18 -#define GPIO_DOUT31_0_DIO18 0x00040000 -#define GPIO_DOUT31_0_DIO18_BITN 18 -#define GPIO_DOUT31_0_DIO18_M 0x00040000 -#define GPIO_DOUT31_0_DIO18_S 18 +#define GPIO_DOUT31_0_DIO18 0x00040000 +#define GPIO_DOUT31_0_DIO18_BITN 18 +#define GPIO_DOUT31_0_DIO18_M 0x00040000 +#define GPIO_DOUT31_0_DIO18_S 18 // Field: [17] DIO17 // // Data output for DIO 17 -#define GPIO_DOUT31_0_DIO17 0x00020000 -#define GPIO_DOUT31_0_DIO17_BITN 17 -#define GPIO_DOUT31_0_DIO17_M 0x00020000 -#define GPIO_DOUT31_0_DIO17_S 17 +#define GPIO_DOUT31_0_DIO17 0x00020000 +#define GPIO_DOUT31_0_DIO17_BITN 17 +#define GPIO_DOUT31_0_DIO17_M 0x00020000 +#define GPIO_DOUT31_0_DIO17_S 17 // Field: [16] DIO16 // // Data output for DIO 16 -#define GPIO_DOUT31_0_DIO16 0x00010000 -#define GPIO_DOUT31_0_DIO16_BITN 16 -#define GPIO_DOUT31_0_DIO16_M 0x00010000 -#define GPIO_DOUT31_0_DIO16_S 16 +#define GPIO_DOUT31_0_DIO16 0x00010000 +#define GPIO_DOUT31_0_DIO16_BITN 16 +#define GPIO_DOUT31_0_DIO16_M 0x00010000 +#define GPIO_DOUT31_0_DIO16_S 16 // Field: [15] DIO15 // // Data output for DIO 15 -#define GPIO_DOUT31_0_DIO15 0x00008000 -#define GPIO_DOUT31_0_DIO15_BITN 15 -#define GPIO_DOUT31_0_DIO15_M 0x00008000 -#define GPIO_DOUT31_0_DIO15_S 15 +#define GPIO_DOUT31_0_DIO15 0x00008000 +#define GPIO_DOUT31_0_DIO15_BITN 15 +#define GPIO_DOUT31_0_DIO15_M 0x00008000 +#define GPIO_DOUT31_0_DIO15_S 15 // Field: [14] DIO14 // // Data output for DIO 14 -#define GPIO_DOUT31_0_DIO14 0x00004000 -#define GPIO_DOUT31_0_DIO14_BITN 14 -#define GPIO_DOUT31_0_DIO14_M 0x00004000 -#define GPIO_DOUT31_0_DIO14_S 14 +#define GPIO_DOUT31_0_DIO14 0x00004000 +#define GPIO_DOUT31_0_DIO14_BITN 14 +#define GPIO_DOUT31_0_DIO14_M 0x00004000 +#define GPIO_DOUT31_0_DIO14_S 14 // Field: [13] DIO13 // // Data output for DIO 13 -#define GPIO_DOUT31_0_DIO13 0x00002000 -#define GPIO_DOUT31_0_DIO13_BITN 13 -#define GPIO_DOUT31_0_DIO13_M 0x00002000 -#define GPIO_DOUT31_0_DIO13_S 13 +#define GPIO_DOUT31_0_DIO13 0x00002000 +#define GPIO_DOUT31_0_DIO13_BITN 13 +#define GPIO_DOUT31_0_DIO13_M 0x00002000 +#define GPIO_DOUT31_0_DIO13_S 13 // Field: [12] DIO12 // // Data output for DIO 12 -#define GPIO_DOUT31_0_DIO12 0x00001000 -#define GPIO_DOUT31_0_DIO12_BITN 12 -#define GPIO_DOUT31_0_DIO12_M 0x00001000 -#define GPIO_DOUT31_0_DIO12_S 12 +#define GPIO_DOUT31_0_DIO12 0x00001000 +#define GPIO_DOUT31_0_DIO12_BITN 12 +#define GPIO_DOUT31_0_DIO12_M 0x00001000 +#define GPIO_DOUT31_0_DIO12_S 12 // Field: [11] DIO11 // // Data output for DIO 11 -#define GPIO_DOUT31_0_DIO11 0x00000800 -#define GPIO_DOUT31_0_DIO11_BITN 11 -#define GPIO_DOUT31_0_DIO11_M 0x00000800 -#define GPIO_DOUT31_0_DIO11_S 11 +#define GPIO_DOUT31_0_DIO11 0x00000800 +#define GPIO_DOUT31_0_DIO11_BITN 11 +#define GPIO_DOUT31_0_DIO11_M 0x00000800 +#define GPIO_DOUT31_0_DIO11_S 11 // Field: [10] DIO10 // // Data output for DIO 10 -#define GPIO_DOUT31_0_DIO10 0x00000400 -#define GPIO_DOUT31_0_DIO10_BITN 10 -#define GPIO_DOUT31_0_DIO10_M 0x00000400 -#define GPIO_DOUT31_0_DIO10_S 10 +#define GPIO_DOUT31_0_DIO10 0x00000400 +#define GPIO_DOUT31_0_DIO10_BITN 10 +#define GPIO_DOUT31_0_DIO10_M 0x00000400 +#define GPIO_DOUT31_0_DIO10_S 10 // Field: [9] DIO9 // // Data output for DIO 9 -#define GPIO_DOUT31_0_DIO9 0x00000200 -#define GPIO_DOUT31_0_DIO9_BITN 9 -#define GPIO_DOUT31_0_DIO9_M 0x00000200 -#define GPIO_DOUT31_0_DIO9_S 9 +#define GPIO_DOUT31_0_DIO9 0x00000200 +#define GPIO_DOUT31_0_DIO9_BITN 9 +#define GPIO_DOUT31_0_DIO9_M 0x00000200 +#define GPIO_DOUT31_0_DIO9_S 9 // Field: [8] DIO8 // // Data output for DIO 8 -#define GPIO_DOUT31_0_DIO8 0x00000100 -#define GPIO_DOUT31_0_DIO8_BITN 8 -#define GPIO_DOUT31_0_DIO8_M 0x00000100 -#define GPIO_DOUT31_0_DIO8_S 8 +#define GPIO_DOUT31_0_DIO8 0x00000100 +#define GPIO_DOUT31_0_DIO8_BITN 8 +#define GPIO_DOUT31_0_DIO8_M 0x00000100 +#define GPIO_DOUT31_0_DIO8_S 8 // Field: [7] DIO7 // // Data output for DIO 7 -#define GPIO_DOUT31_0_DIO7 0x00000080 -#define GPIO_DOUT31_0_DIO7_BITN 7 -#define GPIO_DOUT31_0_DIO7_M 0x00000080 -#define GPIO_DOUT31_0_DIO7_S 7 +#define GPIO_DOUT31_0_DIO7 0x00000080 +#define GPIO_DOUT31_0_DIO7_BITN 7 +#define GPIO_DOUT31_0_DIO7_M 0x00000080 +#define GPIO_DOUT31_0_DIO7_S 7 // Field: [6] DIO6 // // Data output for DIO 6 -#define GPIO_DOUT31_0_DIO6 0x00000040 -#define GPIO_DOUT31_0_DIO6_BITN 6 -#define GPIO_DOUT31_0_DIO6_M 0x00000040 -#define GPIO_DOUT31_0_DIO6_S 6 +#define GPIO_DOUT31_0_DIO6 0x00000040 +#define GPIO_DOUT31_0_DIO6_BITN 6 +#define GPIO_DOUT31_0_DIO6_M 0x00000040 +#define GPIO_DOUT31_0_DIO6_S 6 // Field: [5] DIO5 // // Data output for DIO 5 -#define GPIO_DOUT31_0_DIO5 0x00000020 -#define GPIO_DOUT31_0_DIO5_BITN 5 -#define GPIO_DOUT31_0_DIO5_M 0x00000020 -#define GPIO_DOUT31_0_DIO5_S 5 +#define GPIO_DOUT31_0_DIO5 0x00000020 +#define GPIO_DOUT31_0_DIO5_BITN 5 +#define GPIO_DOUT31_0_DIO5_M 0x00000020 +#define GPIO_DOUT31_0_DIO5_S 5 // Field: [4] DIO4 // // Data output for DIO 4 -#define GPIO_DOUT31_0_DIO4 0x00000010 -#define GPIO_DOUT31_0_DIO4_BITN 4 -#define GPIO_DOUT31_0_DIO4_M 0x00000010 -#define GPIO_DOUT31_0_DIO4_S 4 +#define GPIO_DOUT31_0_DIO4 0x00000010 +#define GPIO_DOUT31_0_DIO4_BITN 4 +#define GPIO_DOUT31_0_DIO4_M 0x00000010 +#define GPIO_DOUT31_0_DIO4_S 4 // Field: [3] DIO3 // // Data output for DIO 3 -#define GPIO_DOUT31_0_DIO3 0x00000008 -#define GPIO_DOUT31_0_DIO3_BITN 3 -#define GPIO_DOUT31_0_DIO3_M 0x00000008 -#define GPIO_DOUT31_0_DIO3_S 3 +#define GPIO_DOUT31_0_DIO3 0x00000008 +#define GPIO_DOUT31_0_DIO3_BITN 3 +#define GPIO_DOUT31_0_DIO3_M 0x00000008 +#define GPIO_DOUT31_0_DIO3_S 3 // Field: [2] DIO2 // // Data output for DIO 2 -#define GPIO_DOUT31_0_DIO2 0x00000004 -#define GPIO_DOUT31_0_DIO2_BITN 2 -#define GPIO_DOUT31_0_DIO2_M 0x00000004 -#define GPIO_DOUT31_0_DIO2_S 2 +#define GPIO_DOUT31_0_DIO2 0x00000004 +#define GPIO_DOUT31_0_DIO2_BITN 2 +#define GPIO_DOUT31_0_DIO2_M 0x00000004 +#define GPIO_DOUT31_0_DIO2_S 2 // Field: [1] DIO1 // // Data output for DIO 1 -#define GPIO_DOUT31_0_DIO1 0x00000002 -#define GPIO_DOUT31_0_DIO1_BITN 1 -#define GPIO_DOUT31_0_DIO1_M 0x00000002 -#define GPIO_DOUT31_0_DIO1_S 1 +#define GPIO_DOUT31_0_DIO1 0x00000002 +#define GPIO_DOUT31_0_DIO1_BITN 1 +#define GPIO_DOUT31_0_DIO1_M 0x00000002 +#define GPIO_DOUT31_0_DIO1_S 1 // Field: [0] DIO0 // // Data output for DIO 0 -#define GPIO_DOUT31_0_DIO0 0x00000001 -#define GPIO_DOUT31_0_DIO0_BITN 0 -#define GPIO_DOUT31_0_DIO0_M 0x00000001 -#define GPIO_DOUT31_0_DIO0_S 0 +#define GPIO_DOUT31_0_DIO0 0x00000001 +#define GPIO_DOUT31_0_DIO0_BITN 0 +#define GPIO_DOUT31_0_DIO0_M 0x00000001 +#define GPIO_DOUT31_0_DIO0_S 0 //***************************************************************************** // @@ -685,258 +685,258 @@ // Field: [31] DIO31 // // Set bit 31 -#define GPIO_DOUTSET31_0_DIO31 0x80000000 -#define GPIO_DOUTSET31_0_DIO31_BITN 31 -#define GPIO_DOUTSET31_0_DIO31_M 0x80000000 -#define GPIO_DOUTSET31_0_DIO31_S 31 +#define GPIO_DOUTSET31_0_DIO31 0x80000000 +#define GPIO_DOUTSET31_0_DIO31_BITN 31 +#define GPIO_DOUTSET31_0_DIO31_M 0x80000000 +#define GPIO_DOUTSET31_0_DIO31_S 31 // Field: [30] DIO30 // // Set bit 30 -#define GPIO_DOUTSET31_0_DIO30 0x40000000 -#define GPIO_DOUTSET31_0_DIO30_BITN 30 -#define GPIO_DOUTSET31_0_DIO30_M 0x40000000 -#define GPIO_DOUTSET31_0_DIO30_S 30 +#define GPIO_DOUTSET31_0_DIO30 0x40000000 +#define GPIO_DOUTSET31_0_DIO30_BITN 30 +#define GPIO_DOUTSET31_0_DIO30_M 0x40000000 +#define GPIO_DOUTSET31_0_DIO30_S 30 // Field: [29] DIO29 // // Set bit 29 -#define GPIO_DOUTSET31_0_DIO29 0x20000000 -#define GPIO_DOUTSET31_0_DIO29_BITN 29 -#define GPIO_DOUTSET31_0_DIO29_M 0x20000000 -#define GPIO_DOUTSET31_0_DIO29_S 29 +#define GPIO_DOUTSET31_0_DIO29 0x20000000 +#define GPIO_DOUTSET31_0_DIO29_BITN 29 +#define GPIO_DOUTSET31_0_DIO29_M 0x20000000 +#define GPIO_DOUTSET31_0_DIO29_S 29 // Field: [28] DIO28 // // Set bit 28 -#define GPIO_DOUTSET31_0_DIO28 0x10000000 -#define GPIO_DOUTSET31_0_DIO28_BITN 28 -#define GPIO_DOUTSET31_0_DIO28_M 0x10000000 -#define GPIO_DOUTSET31_0_DIO28_S 28 +#define GPIO_DOUTSET31_0_DIO28 0x10000000 +#define GPIO_DOUTSET31_0_DIO28_BITN 28 +#define GPIO_DOUTSET31_0_DIO28_M 0x10000000 +#define GPIO_DOUTSET31_0_DIO28_S 28 // Field: [27] DIO27 // // Set bit 27 -#define GPIO_DOUTSET31_0_DIO27 0x08000000 -#define GPIO_DOUTSET31_0_DIO27_BITN 27 -#define GPIO_DOUTSET31_0_DIO27_M 0x08000000 -#define GPIO_DOUTSET31_0_DIO27_S 27 +#define GPIO_DOUTSET31_0_DIO27 0x08000000 +#define GPIO_DOUTSET31_0_DIO27_BITN 27 +#define GPIO_DOUTSET31_0_DIO27_M 0x08000000 +#define GPIO_DOUTSET31_0_DIO27_S 27 // Field: [26] DIO26 // // Set bit 26 -#define GPIO_DOUTSET31_0_DIO26 0x04000000 -#define GPIO_DOUTSET31_0_DIO26_BITN 26 -#define GPIO_DOUTSET31_0_DIO26_M 0x04000000 -#define GPIO_DOUTSET31_0_DIO26_S 26 +#define GPIO_DOUTSET31_0_DIO26 0x04000000 +#define GPIO_DOUTSET31_0_DIO26_BITN 26 +#define GPIO_DOUTSET31_0_DIO26_M 0x04000000 +#define GPIO_DOUTSET31_0_DIO26_S 26 // Field: [25] DIO25 // // Set bit 25 -#define GPIO_DOUTSET31_0_DIO25 0x02000000 -#define GPIO_DOUTSET31_0_DIO25_BITN 25 -#define GPIO_DOUTSET31_0_DIO25_M 0x02000000 -#define GPIO_DOUTSET31_0_DIO25_S 25 +#define GPIO_DOUTSET31_0_DIO25 0x02000000 +#define GPIO_DOUTSET31_0_DIO25_BITN 25 +#define GPIO_DOUTSET31_0_DIO25_M 0x02000000 +#define GPIO_DOUTSET31_0_DIO25_S 25 // Field: [24] DIO24 // // Set bit 24 -#define GPIO_DOUTSET31_0_DIO24 0x01000000 -#define GPIO_DOUTSET31_0_DIO24_BITN 24 -#define GPIO_DOUTSET31_0_DIO24_M 0x01000000 -#define GPIO_DOUTSET31_0_DIO24_S 24 +#define GPIO_DOUTSET31_0_DIO24 0x01000000 +#define GPIO_DOUTSET31_0_DIO24_BITN 24 +#define GPIO_DOUTSET31_0_DIO24_M 0x01000000 +#define GPIO_DOUTSET31_0_DIO24_S 24 // Field: [23] DIO23 // // Set bit 23 -#define GPIO_DOUTSET31_0_DIO23 0x00800000 -#define GPIO_DOUTSET31_0_DIO23_BITN 23 -#define GPIO_DOUTSET31_0_DIO23_M 0x00800000 -#define GPIO_DOUTSET31_0_DIO23_S 23 +#define GPIO_DOUTSET31_0_DIO23 0x00800000 +#define GPIO_DOUTSET31_0_DIO23_BITN 23 +#define GPIO_DOUTSET31_0_DIO23_M 0x00800000 +#define GPIO_DOUTSET31_0_DIO23_S 23 // Field: [22] DIO22 // // Set bit 22 -#define GPIO_DOUTSET31_0_DIO22 0x00400000 -#define GPIO_DOUTSET31_0_DIO22_BITN 22 -#define GPIO_DOUTSET31_0_DIO22_M 0x00400000 -#define GPIO_DOUTSET31_0_DIO22_S 22 +#define GPIO_DOUTSET31_0_DIO22 0x00400000 +#define GPIO_DOUTSET31_0_DIO22_BITN 22 +#define GPIO_DOUTSET31_0_DIO22_M 0x00400000 +#define GPIO_DOUTSET31_0_DIO22_S 22 // Field: [21] DIO21 // // Set bit 21 -#define GPIO_DOUTSET31_0_DIO21 0x00200000 -#define GPIO_DOUTSET31_0_DIO21_BITN 21 -#define GPIO_DOUTSET31_0_DIO21_M 0x00200000 -#define GPIO_DOUTSET31_0_DIO21_S 21 +#define GPIO_DOUTSET31_0_DIO21 0x00200000 +#define GPIO_DOUTSET31_0_DIO21_BITN 21 +#define GPIO_DOUTSET31_0_DIO21_M 0x00200000 +#define GPIO_DOUTSET31_0_DIO21_S 21 // Field: [20] DIO20 // // Set bit 20 -#define GPIO_DOUTSET31_0_DIO20 0x00100000 -#define GPIO_DOUTSET31_0_DIO20_BITN 20 -#define GPIO_DOUTSET31_0_DIO20_M 0x00100000 -#define GPIO_DOUTSET31_0_DIO20_S 20 +#define GPIO_DOUTSET31_0_DIO20 0x00100000 +#define GPIO_DOUTSET31_0_DIO20_BITN 20 +#define GPIO_DOUTSET31_0_DIO20_M 0x00100000 +#define GPIO_DOUTSET31_0_DIO20_S 20 // Field: [19] DIO19 // // Set bit 19 -#define GPIO_DOUTSET31_0_DIO19 0x00080000 -#define GPIO_DOUTSET31_0_DIO19_BITN 19 -#define GPIO_DOUTSET31_0_DIO19_M 0x00080000 -#define GPIO_DOUTSET31_0_DIO19_S 19 +#define GPIO_DOUTSET31_0_DIO19 0x00080000 +#define GPIO_DOUTSET31_0_DIO19_BITN 19 +#define GPIO_DOUTSET31_0_DIO19_M 0x00080000 +#define GPIO_DOUTSET31_0_DIO19_S 19 // Field: [18] DIO18 // // Set bit 18 -#define GPIO_DOUTSET31_0_DIO18 0x00040000 -#define GPIO_DOUTSET31_0_DIO18_BITN 18 -#define GPIO_DOUTSET31_0_DIO18_M 0x00040000 -#define GPIO_DOUTSET31_0_DIO18_S 18 +#define GPIO_DOUTSET31_0_DIO18 0x00040000 +#define GPIO_DOUTSET31_0_DIO18_BITN 18 +#define GPIO_DOUTSET31_0_DIO18_M 0x00040000 +#define GPIO_DOUTSET31_0_DIO18_S 18 // Field: [17] DIO17 // // Set bit 17 -#define GPIO_DOUTSET31_0_DIO17 0x00020000 -#define GPIO_DOUTSET31_0_DIO17_BITN 17 -#define GPIO_DOUTSET31_0_DIO17_M 0x00020000 -#define GPIO_DOUTSET31_0_DIO17_S 17 +#define GPIO_DOUTSET31_0_DIO17 0x00020000 +#define GPIO_DOUTSET31_0_DIO17_BITN 17 +#define GPIO_DOUTSET31_0_DIO17_M 0x00020000 +#define GPIO_DOUTSET31_0_DIO17_S 17 // Field: [16] DIO16 // // Set bit 16 -#define GPIO_DOUTSET31_0_DIO16 0x00010000 -#define GPIO_DOUTSET31_0_DIO16_BITN 16 -#define GPIO_DOUTSET31_0_DIO16_M 0x00010000 -#define GPIO_DOUTSET31_0_DIO16_S 16 +#define GPIO_DOUTSET31_0_DIO16 0x00010000 +#define GPIO_DOUTSET31_0_DIO16_BITN 16 +#define GPIO_DOUTSET31_0_DIO16_M 0x00010000 +#define GPIO_DOUTSET31_0_DIO16_S 16 // Field: [15] DIO15 // // Set bit 15 -#define GPIO_DOUTSET31_0_DIO15 0x00008000 -#define GPIO_DOUTSET31_0_DIO15_BITN 15 -#define GPIO_DOUTSET31_0_DIO15_M 0x00008000 -#define GPIO_DOUTSET31_0_DIO15_S 15 +#define GPIO_DOUTSET31_0_DIO15 0x00008000 +#define GPIO_DOUTSET31_0_DIO15_BITN 15 +#define GPIO_DOUTSET31_0_DIO15_M 0x00008000 +#define GPIO_DOUTSET31_0_DIO15_S 15 // Field: [14] DIO14 // // Set bit 14 -#define GPIO_DOUTSET31_0_DIO14 0x00004000 -#define GPIO_DOUTSET31_0_DIO14_BITN 14 -#define GPIO_DOUTSET31_0_DIO14_M 0x00004000 -#define GPIO_DOUTSET31_0_DIO14_S 14 +#define GPIO_DOUTSET31_0_DIO14 0x00004000 +#define GPIO_DOUTSET31_0_DIO14_BITN 14 +#define GPIO_DOUTSET31_0_DIO14_M 0x00004000 +#define GPIO_DOUTSET31_0_DIO14_S 14 // Field: [13] DIO13 // // Set bit 13 -#define GPIO_DOUTSET31_0_DIO13 0x00002000 -#define GPIO_DOUTSET31_0_DIO13_BITN 13 -#define GPIO_DOUTSET31_0_DIO13_M 0x00002000 -#define GPIO_DOUTSET31_0_DIO13_S 13 +#define GPIO_DOUTSET31_0_DIO13 0x00002000 +#define GPIO_DOUTSET31_0_DIO13_BITN 13 +#define GPIO_DOUTSET31_0_DIO13_M 0x00002000 +#define GPIO_DOUTSET31_0_DIO13_S 13 // Field: [12] DIO12 // // Set bit 12 -#define GPIO_DOUTSET31_0_DIO12 0x00001000 -#define GPIO_DOUTSET31_0_DIO12_BITN 12 -#define GPIO_DOUTSET31_0_DIO12_M 0x00001000 -#define GPIO_DOUTSET31_0_DIO12_S 12 +#define GPIO_DOUTSET31_0_DIO12 0x00001000 +#define GPIO_DOUTSET31_0_DIO12_BITN 12 +#define GPIO_DOUTSET31_0_DIO12_M 0x00001000 +#define GPIO_DOUTSET31_0_DIO12_S 12 // Field: [11] DIO11 // // Set bit 11 -#define GPIO_DOUTSET31_0_DIO11 0x00000800 -#define GPIO_DOUTSET31_0_DIO11_BITN 11 -#define GPIO_DOUTSET31_0_DIO11_M 0x00000800 -#define GPIO_DOUTSET31_0_DIO11_S 11 +#define GPIO_DOUTSET31_0_DIO11 0x00000800 +#define GPIO_DOUTSET31_0_DIO11_BITN 11 +#define GPIO_DOUTSET31_0_DIO11_M 0x00000800 +#define GPIO_DOUTSET31_0_DIO11_S 11 // Field: [10] DIO10 // // Set bit 10 -#define GPIO_DOUTSET31_0_DIO10 0x00000400 -#define GPIO_DOUTSET31_0_DIO10_BITN 10 -#define GPIO_DOUTSET31_0_DIO10_M 0x00000400 -#define GPIO_DOUTSET31_0_DIO10_S 10 +#define GPIO_DOUTSET31_0_DIO10 0x00000400 +#define GPIO_DOUTSET31_0_DIO10_BITN 10 +#define GPIO_DOUTSET31_0_DIO10_M 0x00000400 +#define GPIO_DOUTSET31_0_DIO10_S 10 // Field: [9] DIO9 // // Set bit 9 -#define GPIO_DOUTSET31_0_DIO9 0x00000200 -#define GPIO_DOUTSET31_0_DIO9_BITN 9 -#define GPIO_DOUTSET31_0_DIO9_M 0x00000200 -#define GPIO_DOUTSET31_0_DIO9_S 9 +#define GPIO_DOUTSET31_0_DIO9 0x00000200 +#define GPIO_DOUTSET31_0_DIO9_BITN 9 +#define GPIO_DOUTSET31_0_DIO9_M 0x00000200 +#define GPIO_DOUTSET31_0_DIO9_S 9 // Field: [8] DIO8 // // Set bit 8 -#define GPIO_DOUTSET31_0_DIO8 0x00000100 -#define GPIO_DOUTSET31_0_DIO8_BITN 8 -#define GPIO_DOUTSET31_0_DIO8_M 0x00000100 -#define GPIO_DOUTSET31_0_DIO8_S 8 +#define GPIO_DOUTSET31_0_DIO8 0x00000100 +#define GPIO_DOUTSET31_0_DIO8_BITN 8 +#define GPIO_DOUTSET31_0_DIO8_M 0x00000100 +#define GPIO_DOUTSET31_0_DIO8_S 8 // Field: [7] DIO7 // // Set bit 7 -#define GPIO_DOUTSET31_0_DIO7 0x00000080 -#define GPIO_DOUTSET31_0_DIO7_BITN 7 -#define GPIO_DOUTSET31_0_DIO7_M 0x00000080 -#define GPIO_DOUTSET31_0_DIO7_S 7 +#define GPIO_DOUTSET31_0_DIO7 0x00000080 +#define GPIO_DOUTSET31_0_DIO7_BITN 7 +#define GPIO_DOUTSET31_0_DIO7_M 0x00000080 +#define GPIO_DOUTSET31_0_DIO7_S 7 // Field: [6] DIO6 // // Set bit 6 -#define GPIO_DOUTSET31_0_DIO6 0x00000040 -#define GPIO_DOUTSET31_0_DIO6_BITN 6 -#define GPIO_DOUTSET31_0_DIO6_M 0x00000040 -#define GPIO_DOUTSET31_0_DIO6_S 6 +#define GPIO_DOUTSET31_0_DIO6 0x00000040 +#define GPIO_DOUTSET31_0_DIO6_BITN 6 +#define GPIO_DOUTSET31_0_DIO6_M 0x00000040 +#define GPIO_DOUTSET31_0_DIO6_S 6 // Field: [5] DIO5 // // Set bit 5 -#define GPIO_DOUTSET31_0_DIO5 0x00000020 -#define GPIO_DOUTSET31_0_DIO5_BITN 5 -#define GPIO_DOUTSET31_0_DIO5_M 0x00000020 -#define GPIO_DOUTSET31_0_DIO5_S 5 +#define GPIO_DOUTSET31_0_DIO5 0x00000020 +#define GPIO_DOUTSET31_0_DIO5_BITN 5 +#define GPIO_DOUTSET31_0_DIO5_M 0x00000020 +#define GPIO_DOUTSET31_0_DIO5_S 5 // Field: [4] DIO4 // // Set bit 4 -#define GPIO_DOUTSET31_0_DIO4 0x00000010 -#define GPIO_DOUTSET31_0_DIO4_BITN 4 -#define GPIO_DOUTSET31_0_DIO4_M 0x00000010 -#define GPIO_DOUTSET31_0_DIO4_S 4 +#define GPIO_DOUTSET31_0_DIO4 0x00000010 +#define GPIO_DOUTSET31_0_DIO4_BITN 4 +#define GPIO_DOUTSET31_0_DIO4_M 0x00000010 +#define GPIO_DOUTSET31_0_DIO4_S 4 // Field: [3] DIO3 // // Set bit 3 -#define GPIO_DOUTSET31_0_DIO3 0x00000008 -#define GPIO_DOUTSET31_0_DIO3_BITN 3 -#define GPIO_DOUTSET31_0_DIO3_M 0x00000008 -#define GPIO_DOUTSET31_0_DIO3_S 3 +#define GPIO_DOUTSET31_0_DIO3 0x00000008 +#define GPIO_DOUTSET31_0_DIO3_BITN 3 +#define GPIO_DOUTSET31_0_DIO3_M 0x00000008 +#define GPIO_DOUTSET31_0_DIO3_S 3 // Field: [2] DIO2 // // Set bit 2 -#define GPIO_DOUTSET31_0_DIO2 0x00000004 -#define GPIO_DOUTSET31_0_DIO2_BITN 2 -#define GPIO_DOUTSET31_0_DIO2_M 0x00000004 -#define GPIO_DOUTSET31_0_DIO2_S 2 +#define GPIO_DOUTSET31_0_DIO2 0x00000004 +#define GPIO_DOUTSET31_0_DIO2_BITN 2 +#define GPIO_DOUTSET31_0_DIO2_M 0x00000004 +#define GPIO_DOUTSET31_0_DIO2_S 2 // Field: [1] DIO1 // // Set bit 1 -#define GPIO_DOUTSET31_0_DIO1 0x00000002 -#define GPIO_DOUTSET31_0_DIO1_BITN 1 -#define GPIO_DOUTSET31_0_DIO1_M 0x00000002 -#define GPIO_DOUTSET31_0_DIO1_S 1 +#define GPIO_DOUTSET31_0_DIO1 0x00000002 +#define GPIO_DOUTSET31_0_DIO1_BITN 1 +#define GPIO_DOUTSET31_0_DIO1_M 0x00000002 +#define GPIO_DOUTSET31_0_DIO1_S 1 // Field: [0] DIO0 // // Set bit 0 -#define GPIO_DOUTSET31_0_DIO0 0x00000001 -#define GPIO_DOUTSET31_0_DIO0_BITN 0 -#define GPIO_DOUTSET31_0_DIO0_M 0x00000001 -#define GPIO_DOUTSET31_0_DIO0_S 0 +#define GPIO_DOUTSET31_0_DIO0 0x00000001 +#define GPIO_DOUTSET31_0_DIO0_BITN 0 +#define GPIO_DOUTSET31_0_DIO0_M 0x00000001 +#define GPIO_DOUTSET31_0_DIO0_S 0 //***************************************************************************** // @@ -946,258 +946,258 @@ // Field: [31] DIO31 // // Clears bit 31 -#define GPIO_DOUTCLR31_0_DIO31 0x80000000 -#define GPIO_DOUTCLR31_0_DIO31_BITN 31 -#define GPIO_DOUTCLR31_0_DIO31_M 0x80000000 -#define GPIO_DOUTCLR31_0_DIO31_S 31 +#define GPIO_DOUTCLR31_0_DIO31 0x80000000 +#define GPIO_DOUTCLR31_0_DIO31_BITN 31 +#define GPIO_DOUTCLR31_0_DIO31_M 0x80000000 +#define GPIO_DOUTCLR31_0_DIO31_S 31 // Field: [30] DIO30 // // Clears bit 30 -#define GPIO_DOUTCLR31_0_DIO30 0x40000000 -#define GPIO_DOUTCLR31_0_DIO30_BITN 30 -#define GPIO_DOUTCLR31_0_DIO30_M 0x40000000 -#define GPIO_DOUTCLR31_0_DIO30_S 30 +#define GPIO_DOUTCLR31_0_DIO30 0x40000000 +#define GPIO_DOUTCLR31_0_DIO30_BITN 30 +#define GPIO_DOUTCLR31_0_DIO30_M 0x40000000 +#define GPIO_DOUTCLR31_0_DIO30_S 30 // Field: [29] DIO29 // // Clears bit 29 -#define GPIO_DOUTCLR31_0_DIO29 0x20000000 -#define GPIO_DOUTCLR31_0_DIO29_BITN 29 -#define GPIO_DOUTCLR31_0_DIO29_M 0x20000000 -#define GPIO_DOUTCLR31_0_DIO29_S 29 +#define GPIO_DOUTCLR31_0_DIO29 0x20000000 +#define GPIO_DOUTCLR31_0_DIO29_BITN 29 +#define GPIO_DOUTCLR31_0_DIO29_M 0x20000000 +#define GPIO_DOUTCLR31_0_DIO29_S 29 // Field: [28] DIO28 // // Clears bit 28 -#define GPIO_DOUTCLR31_0_DIO28 0x10000000 -#define GPIO_DOUTCLR31_0_DIO28_BITN 28 -#define GPIO_DOUTCLR31_0_DIO28_M 0x10000000 -#define GPIO_DOUTCLR31_0_DIO28_S 28 +#define GPIO_DOUTCLR31_0_DIO28 0x10000000 +#define GPIO_DOUTCLR31_0_DIO28_BITN 28 +#define GPIO_DOUTCLR31_0_DIO28_M 0x10000000 +#define GPIO_DOUTCLR31_0_DIO28_S 28 // Field: [27] DIO27 // // Clears bit 27 -#define GPIO_DOUTCLR31_0_DIO27 0x08000000 -#define GPIO_DOUTCLR31_0_DIO27_BITN 27 -#define GPIO_DOUTCLR31_0_DIO27_M 0x08000000 -#define GPIO_DOUTCLR31_0_DIO27_S 27 +#define GPIO_DOUTCLR31_0_DIO27 0x08000000 +#define GPIO_DOUTCLR31_0_DIO27_BITN 27 +#define GPIO_DOUTCLR31_0_DIO27_M 0x08000000 +#define GPIO_DOUTCLR31_0_DIO27_S 27 // Field: [26] DIO26 // // Clears bit 26 -#define GPIO_DOUTCLR31_0_DIO26 0x04000000 -#define GPIO_DOUTCLR31_0_DIO26_BITN 26 -#define GPIO_DOUTCLR31_0_DIO26_M 0x04000000 -#define GPIO_DOUTCLR31_0_DIO26_S 26 +#define GPIO_DOUTCLR31_0_DIO26 0x04000000 +#define GPIO_DOUTCLR31_0_DIO26_BITN 26 +#define GPIO_DOUTCLR31_0_DIO26_M 0x04000000 +#define GPIO_DOUTCLR31_0_DIO26_S 26 // Field: [25] DIO25 // // Clears bit 25 -#define GPIO_DOUTCLR31_0_DIO25 0x02000000 -#define GPIO_DOUTCLR31_0_DIO25_BITN 25 -#define GPIO_DOUTCLR31_0_DIO25_M 0x02000000 -#define GPIO_DOUTCLR31_0_DIO25_S 25 +#define GPIO_DOUTCLR31_0_DIO25 0x02000000 +#define GPIO_DOUTCLR31_0_DIO25_BITN 25 +#define GPIO_DOUTCLR31_0_DIO25_M 0x02000000 +#define GPIO_DOUTCLR31_0_DIO25_S 25 // Field: [24] DIO24 // // Clears bit 24 -#define GPIO_DOUTCLR31_0_DIO24 0x01000000 -#define GPIO_DOUTCLR31_0_DIO24_BITN 24 -#define GPIO_DOUTCLR31_0_DIO24_M 0x01000000 -#define GPIO_DOUTCLR31_0_DIO24_S 24 +#define GPIO_DOUTCLR31_0_DIO24 0x01000000 +#define GPIO_DOUTCLR31_0_DIO24_BITN 24 +#define GPIO_DOUTCLR31_0_DIO24_M 0x01000000 +#define GPIO_DOUTCLR31_0_DIO24_S 24 // Field: [23] DIO23 // // Clears bit 23 -#define GPIO_DOUTCLR31_0_DIO23 0x00800000 -#define GPIO_DOUTCLR31_0_DIO23_BITN 23 -#define GPIO_DOUTCLR31_0_DIO23_M 0x00800000 -#define GPIO_DOUTCLR31_0_DIO23_S 23 +#define GPIO_DOUTCLR31_0_DIO23 0x00800000 +#define GPIO_DOUTCLR31_0_DIO23_BITN 23 +#define GPIO_DOUTCLR31_0_DIO23_M 0x00800000 +#define GPIO_DOUTCLR31_0_DIO23_S 23 // Field: [22] DIO22 // // Clears bit 22 -#define GPIO_DOUTCLR31_0_DIO22 0x00400000 -#define GPIO_DOUTCLR31_0_DIO22_BITN 22 -#define GPIO_DOUTCLR31_0_DIO22_M 0x00400000 -#define GPIO_DOUTCLR31_0_DIO22_S 22 +#define GPIO_DOUTCLR31_0_DIO22 0x00400000 +#define GPIO_DOUTCLR31_0_DIO22_BITN 22 +#define GPIO_DOUTCLR31_0_DIO22_M 0x00400000 +#define GPIO_DOUTCLR31_0_DIO22_S 22 // Field: [21] DIO21 // // Clears bit 21 -#define GPIO_DOUTCLR31_0_DIO21 0x00200000 -#define GPIO_DOUTCLR31_0_DIO21_BITN 21 -#define GPIO_DOUTCLR31_0_DIO21_M 0x00200000 -#define GPIO_DOUTCLR31_0_DIO21_S 21 +#define GPIO_DOUTCLR31_0_DIO21 0x00200000 +#define GPIO_DOUTCLR31_0_DIO21_BITN 21 +#define GPIO_DOUTCLR31_0_DIO21_M 0x00200000 +#define GPIO_DOUTCLR31_0_DIO21_S 21 // Field: [20] DIO20 // // Clears bit 20 -#define GPIO_DOUTCLR31_0_DIO20 0x00100000 -#define GPIO_DOUTCLR31_0_DIO20_BITN 20 -#define GPIO_DOUTCLR31_0_DIO20_M 0x00100000 -#define GPIO_DOUTCLR31_0_DIO20_S 20 +#define GPIO_DOUTCLR31_0_DIO20 0x00100000 +#define GPIO_DOUTCLR31_0_DIO20_BITN 20 +#define GPIO_DOUTCLR31_0_DIO20_M 0x00100000 +#define GPIO_DOUTCLR31_0_DIO20_S 20 // Field: [19] DIO19 // // Clears bit 19 -#define GPIO_DOUTCLR31_0_DIO19 0x00080000 -#define GPIO_DOUTCLR31_0_DIO19_BITN 19 -#define GPIO_DOUTCLR31_0_DIO19_M 0x00080000 -#define GPIO_DOUTCLR31_0_DIO19_S 19 +#define GPIO_DOUTCLR31_0_DIO19 0x00080000 +#define GPIO_DOUTCLR31_0_DIO19_BITN 19 +#define GPIO_DOUTCLR31_0_DIO19_M 0x00080000 +#define GPIO_DOUTCLR31_0_DIO19_S 19 // Field: [18] DIO18 // // Clears bit 18 -#define GPIO_DOUTCLR31_0_DIO18 0x00040000 -#define GPIO_DOUTCLR31_0_DIO18_BITN 18 -#define GPIO_DOUTCLR31_0_DIO18_M 0x00040000 -#define GPIO_DOUTCLR31_0_DIO18_S 18 +#define GPIO_DOUTCLR31_0_DIO18 0x00040000 +#define GPIO_DOUTCLR31_0_DIO18_BITN 18 +#define GPIO_DOUTCLR31_0_DIO18_M 0x00040000 +#define GPIO_DOUTCLR31_0_DIO18_S 18 // Field: [17] DIO17 // // Clears bit 17 -#define GPIO_DOUTCLR31_0_DIO17 0x00020000 -#define GPIO_DOUTCLR31_0_DIO17_BITN 17 -#define GPIO_DOUTCLR31_0_DIO17_M 0x00020000 -#define GPIO_DOUTCLR31_0_DIO17_S 17 +#define GPIO_DOUTCLR31_0_DIO17 0x00020000 +#define GPIO_DOUTCLR31_0_DIO17_BITN 17 +#define GPIO_DOUTCLR31_0_DIO17_M 0x00020000 +#define GPIO_DOUTCLR31_0_DIO17_S 17 // Field: [16] DIO16 // // Clears bit 16 -#define GPIO_DOUTCLR31_0_DIO16 0x00010000 -#define GPIO_DOUTCLR31_0_DIO16_BITN 16 -#define GPIO_DOUTCLR31_0_DIO16_M 0x00010000 -#define GPIO_DOUTCLR31_0_DIO16_S 16 +#define GPIO_DOUTCLR31_0_DIO16 0x00010000 +#define GPIO_DOUTCLR31_0_DIO16_BITN 16 +#define GPIO_DOUTCLR31_0_DIO16_M 0x00010000 +#define GPIO_DOUTCLR31_0_DIO16_S 16 // Field: [15] DIO15 // // Clears bit 15 -#define GPIO_DOUTCLR31_0_DIO15 0x00008000 -#define GPIO_DOUTCLR31_0_DIO15_BITN 15 -#define GPIO_DOUTCLR31_0_DIO15_M 0x00008000 -#define GPIO_DOUTCLR31_0_DIO15_S 15 +#define GPIO_DOUTCLR31_0_DIO15 0x00008000 +#define GPIO_DOUTCLR31_0_DIO15_BITN 15 +#define GPIO_DOUTCLR31_0_DIO15_M 0x00008000 +#define GPIO_DOUTCLR31_0_DIO15_S 15 // Field: [14] DIO14 // // Clears bit 14 -#define GPIO_DOUTCLR31_0_DIO14 0x00004000 -#define GPIO_DOUTCLR31_0_DIO14_BITN 14 -#define GPIO_DOUTCLR31_0_DIO14_M 0x00004000 -#define GPIO_DOUTCLR31_0_DIO14_S 14 +#define GPIO_DOUTCLR31_0_DIO14 0x00004000 +#define GPIO_DOUTCLR31_0_DIO14_BITN 14 +#define GPIO_DOUTCLR31_0_DIO14_M 0x00004000 +#define GPIO_DOUTCLR31_0_DIO14_S 14 // Field: [13] DIO13 // // Clears bit 13 -#define GPIO_DOUTCLR31_0_DIO13 0x00002000 -#define GPIO_DOUTCLR31_0_DIO13_BITN 13 -#define GPIO_DOUTCLR31_0_DIO13_M 0x00002000 -#define GPIO_DOUTCLR31_0_DIO13_S 13 +#define GPIO_DOUTCLR31_0_DIO13 0x00002000 +#define GPIO_DOUTCLR31_0_DIO13_BITN 13 +#define GPIO_DOUTCLR31_0_DIO13_M 0x00002000 +#define GPIO_DOUTCLR31_0_DIO13_S 13 // Field: [12] DIO12 // // Clears bit 12 -#define GPIO_DOUTCLR31_0_DIO12 0x00001000 -#define GPIO_DOUTCLR31_0_DIO12_BITN 12 -#define GPIO_DOUTCLR31_0_DIO12_M 0x00001000 -#define GPIO_DOUTCLR31_0_DIO12_S 12 +#define GPIO_DOUTCLR31_0_DIO12 0x00001000 +#define GPIO_DOUTCLR31_0_DIO12_BITN 12 +#define GPIO_DOUTCLR31_0_DIO12_M 0x00001000 +#define GPIO_DOUTCLR31_0_DIO12_S 12 // Field: [11] DIO11 // // Clears bit 11 -#define GPIO_DOUTCLR31_0_DIO11 0x00000800 -#define GPIO_DOUTCLR31_0_DIO11_BITN 11 -#define GPIO_DOUTCLR31_0_DIO11_M 0x00000800 -#define GPIO_DOUTCLR31_0_DIO11_S 11 +#define GPIO_DOUTCLR31_0_DIO11 0x00000800 +#define GPIO_DOUTCLR31_0_DIO11_BITN 11 +#define GPIO_DOUTCLR31_0_DIO11_M 0x00000800 +#define GPIO_DOUTCLR31_0_DIO11_S 11 // Field: [10] DIO10 // // Clears bit 10 -#define GPIO_DOUTCLR31_0_DIO10 0x00000400 -#define GPIO_DOUTCLR31_0_DIO10_BITN 10 -#define GPIO_DOUTCLR31_0_DIO10_M 0x00000400 -#define GPIO_DOUTCLR31_0_DIO10_S 10 +#define GPIO_DOUTCLR31_0_DIO10 0x00000400 +#define GPIO_DOUTCLR31_0_DIO10_BITN 10 +#define GPIO_DOUTCLR31_0_DIO10_M 0x00000400 +#define GPIO_DOUTCLR31_0_DIO10_S 10 // Field: [9] DIO9 // // Clears bit 9 -#define GPIO_DOUTCLR31_0_DIO9 0x00000200 -#define GPIO_DOUTCLR31_0_DIO9_BITN 9 -#define GPIO_DOUTCLR31_0_DIO9_M 0x00000200 -#define GPIO_DOUTCLR31_0_DIO9_S 9 +#define GPIO_DOUTCLR31_0_DIO9 0x00000200 +#define GPIO_DOUTCLR31_0_DIO9_BITN 9 +#define GPIO_DOUTCLR31_0_DIO9_M 0x00000200 +#define GPIO_DOUTCLR31_0_DIO9_S 9 // Field: [8] DIO8 // // Clears bit 8 -#define GPIO_DOUTCLR31_0_DIO8 0x00000100 -#define GPIO_DOUTCLR31_0_DIO8_BITN 8 -#define GPIO_DOUTCLR31_0_DIO8_M 0x00000100 -#define GPIO_DOUTCLR31_0_DIO8_S 8 +#define GPIO_DOUTCLR31_0_DIO8 0x00000100 +#define GPIO_DOUTCLR31_0_DIO8_BITN 8 +#define GPIO_DOUTCLR31_0_DIO8_M 0x00000100 +#define GPIO_DOUTCLR31_0_DIO8_S 8 // Field: [7] DIO7 // // Clears bit 7 -#define GPIO_DOUTCLR31_0_DIO7 0x00000080 -#define GPIO_DOUTCLR31_0_DIO7_BITN 7 -#define GPIO_DOUTCLR31_0_DIO7_M 0x00000080 -#define GPIO_DOUTCLR31_0_DIO7_S 7 +#define GPIO_DOUTCLR31_0_DIO7 0x00000080 +#define GPIO_DOUTCLR31_0_DIO7_BITN 7 +#define GPIO_DOUTCLR31_0_DIO7_M 0x00000080 +#define GPIO_DOUTCLR31_0_DIO7_S 7 // Field: [6] DIO6 // // Clears bit 6 -#define GPIO_DOUTCLR31_0_DIO6 0x00000040 -#define GPIO_DOUTCLR31_0_DIO6_BITN 6 -#define GPIO_DOUTCLR31_0_DIO6_M 0x00000040 -#define GPIO_DOUTCLR31_0_DIO6_S 6 +#define GPIO_DOUTCLR31_0_DIO6 0x00000040 +#define GPIO_DOUTCLR31_0_DIO6_BITN 6 +#define GPIO_DOUTCLR31_0_DIO6_M 0x00000040 +#define GPIO_DOUTCLR31_0_DIO6_S 6 // Field: [5] DIO5 // // Clears bit 5 -#define GPIO_DOUTCLR31_0_DIO5 0x00000020 -#define GPIO_DOUTCLR31_0_DIO5_BITN 5 -#define GPIO_DOUTCLR31_0_DIO5_M 0x00000020 -#define GPIO_DOUTCLR31_0_DIO5_S 5 +#define GPIO_DOUTCLR31_0_DIO5 0x00000020 +#define GPIO_DOUTCLR31_0_DIO5_BITN 5 +#define GPIO_DOUTCLR31_0_DIO5_M 0x00000020 +#define GPIO_DOUTCLR31_0_DIO5_S 5 // Field: [4] DIO4 // // Clears bit 4 -#define GPIO_DOUTCLR31_0_DIO4 0x00000010 -#define GPIO_DOUTCLR31_0_DIO4_BITN 4 -#define GPIO_DOUTCLR31_0_DIO4_M 0x00000010 -#define GPIO_DOUTCLR31_0_DIO4_S 4 +#define GPIO_DOUTCLR31_0_DIO4 0x00000010 +#define GPIO_DOUTCLR31_0_DIO4_BITN 4 +#define GPIO_DOUTCLR31_0_DIO4_M 0x00000010 +#define GPIO_DOUTCLR31_0_DIO4_S 4 // Field: [3] DIO3 // // Clears bit 3 -#define GPIO_DOUTCLR31_0_DIO3 0x00000008 -#define GPIO_DOUTCLR31_0_DIO3_BITN 3 -#define GPIO_DOUTCLR31_0_DIO3_M 0x00000008 -#define GPIO_DOUTCLR31_0_DIO3_S 3 +#define GPIO_DOUTCLR31_0_DIO3 0x00000008 +#define GPIO_DOUTCLR31_0_DIO3_BITN 3 +#define GPIO_DOUTCLR31_0_DIO3_M 0x00000008 +#define GPIO_DOUTCLR31_0_DIO3_S 3 // Field: [2] DIO2 // // Clears bit 2 -#define GPIO_DOUTCLR31_0_DIO2 0x00000004 -#define GPIO_DOUTCLR31_0_DIO2_BITN 2 -#define GPIO_DOUTCLR31_0_DIO2_M 0x00000004 -#define GPIO_DOUTCLR31_0_DIO2_S 2 +#define GPIO_DOUTCLR31_0_DIO2 0x00000004 +#define GPIO_DOUTCLR31_0_DIO2_BITN 2 +#define GPIO_DOUTCLR31_0_DIO2_M 0x00000004 +#define GPIO_DOUTCLR31_0_DIO2_S 2 // Field: [1] DIO1 // // Clears bit 1 -#define GPIO_DOUTCLR31_0_DIO1 0x00000002 -#define GPIO_DOUTCLR31_0_DIO1_BITN 1 -#define GPIO_DOUTCLR31_0_DIO1_M 0x00000002 -#define GPIO_DOUTCLR31_0_DIO1_S 1 +#define GPIO_DOUTCLR31_0_DIO1 0x00000002 +#define GPIO_DOUTCLR31_0_DIO1_BITN 1 +#define GPIO_DOUTCLR31_0_DIO1_M 0x00000002 +#define GPIO_DOUTCLR31_0_DIO1_S 1 // Field: [0] DIO0 // // Clears bit 0 -#define GPIO_DOUTCLR31_0_DIO0 0x00000001 -#define GPIO_DOUTCLR31_0_DIO0_BITN 0 -#define GPIO_DOUTCLR31_0_DIO0_M 0x00000001 -#define GPIO_DOUTCLR31_0_DIO0_S 0 +#define GPIO_DOUTCLR31_0_DIO0 0x00000001 +#define GPIO_DOUTCLR31_0_DIO0_BITN 0 +#define GPIO_DOUTCLR31_0_DIO0_M 0x00000001 +#define GPIO_DOUTCLR31_0_DIO0_S 0 //***************************************************************************** // @@ -1207,258 +1207,258 @@ // Field: [31] DIO31 // // Toggles bit 31 -#define GPIO_DOUTTGL31_0_DIO31 0x80000000 -#define GPIO_DOUTTGL31_0_DIO31_BITN 31 -#define GPIO_DOUTTGL31_0_DIO31_M 0x80000000 -#define GPIO_DOUTTGL31_0_DIO31_S 31 +#define GPIO_DOUTTGL31_0_DIO31 0x80000000 +#define GPIO_DOUTTGL31_0_DIO31_BITN 31 +#define GPIO_DOUTTGL31_0_DIO31_M 0x80000000 +#define GPIO_DOUTTGL31_0_DIO31_S 31 // Field: [30] DIO30 // // Toggles bit 30 -#define GPIO_DOUTTGL31_0_DIO30 0x40000000 -#define GPIO_DOUTTGL31_0_DIO30_BITN 30 -#define GPIO_DOUTTGL31_0_DIO30_M 0x40000000 -#define GPIO_DOUTTGL31_0_DIO30_S 30 +#define GPIO_DOUTTGL31_0_DIO30 0x40000000 +#define GPIO_DOUTTGL31_0_DIO30_BITN 30 +#define GPIO_DOUTTGL31_0_DIO30_M 0x40000000 +#define GPIO_DOUTTGL31_0_DIO30_S 30 // Field: [29] DIO29 // // Toggles bit 29 -#define GPIO_DOUTTGL31_0_DIO29 0x20000000 -#define GPIO_DOUTTGL31_0_DIO29_BITN 29 -#define GPIO_DOUTTGL31_0_DIO29_M 0x20000000 -#define GPIO_DOUTTGL31_0_DIO29_S 29 +#define GPIO_DOUTTGL31_0_DIO29 0x20000000 +#define GPIO_DOUTTGL31_0_DIO29_BITN 29 +#define GPIO_DOUTTGL31_0_DIO29_M 0x20000000 +#define GPIO_DOUTTGL31_0_DIO29_S 29 // Field: [28] DIO28 // // Toggles bit 28 -#define GPIO_DOUTTGL31_0_DIO28 0x10000000 -#define GPIO_DOUTTGL31_0_DIO28_BITN 28 -#define GPIO_DOUTTGL31_0_DIO28_M 0x10000000 -#define GPIO_DOUTTGL31_0_DIO28_S 28 +#define GPIO_DOUTTGL31_0_DIO28 0x10000000 +#define GPIO_DOUTTGL31_0_DIO28_BITN 28 +#define GPIO_DOUTTGL31_0_DIO28_M 0x10000000 +#define GPIO_DOUTTGL31_0_DIO28_S 28 // Field: [27] DIO27 // // Toggles bit 27 -#define GPIO_DOUTTGL31_0_DIO27 0x08000000 -#define GPIO_DOUTTGL31_0_DIO27_BITN 27 -#define GPIO_DOUTTGL31_0_DIO27_M 0x08000000 -#define GPIO_DOUTTGL31_0_DIO27_S 27 +#define GPIO_DOUTTGL31_0_DIO27 0x08000000 +#define GPIO_DOUTTGL31_0_DIO27_BITN 27 +#define GPIO_DOUTTGL31_0_DIO27_M 0x08000000 +#define GPIO_DOUTTGL31_0_DIO27_S 27 // Field: [26] DIO26 // // Toggles bit 26 -#define GPIO_DOUTTGL31_0_DIO26 0x04000000 -#define GPIO_DOUTTGL31_0_DIO26_BITN 26 -#define GPIO_DOUTTGL31_0_DIO26_M 0x04000000 -#define GPIO_DOUTTGL31_0_DIO26_S 26 +#define GPIO_DOUTTGL31_0_DIO26 0x04000000 +#define GPIO_DOUTTGL31_0_DIO26_BITN 26 +#define GPIO_DOUTTGL31_0_DIO26_M 0x04000000 +#define GPIO_DOUTTGL31_0_DIO26_S 26 // Field: [25] DIO25 // // Toggles bit 25 -#define GPIO_DOUTTGL31_0_DIO25 0x02000000 -#define GPIO_DOUTTGL31_0_DIO25_BITN 25 -#define GPIO_DOUTTGL31_0_DIO25_M 0x02000000 -#define GPIO_DOUTTGL31_0_DIO25_S 25 +#define GPIO_DOUTTGL31_0_DIO25 0x02000000 +#define GPIO_DOUTTGL31_0_DIO25_BITN 25 +#define GPIO_DOUTTGL31_0_DIO25_M 0x02000000 +#define GPIO_DOUTTGL31_0_DIO25_S 25 // Field: [24] DIO24 // // Toggles bit 24 -#define GPIO_DOUTTGL31_0_DIO24 0x01000000 -#define GPIO_DOUTTGL31_0_DIO24_BITN 24 -#define GPIO_DOUTTGL31_0_DIO24_M 0x01000000 -#define GPIO_DOUTTGL31_0_DIO24_S 24 +#define GPIO_DOUTTGL31_0_DIO24 0x01000000 +#define GPIO_DOUTTGL31_0_DIO24_BITN 24 +#define GPIO_DOUTTGL31_0_DIO24_M 0x01000000 +#define GPIO_DOUTTGL31_0_DIO24_S 24 // Field: [23] DIO23 // // Toggles bit 23 -#define GPIO_DOUTTGL31_0_DIO23 0x00800000 -#define GPIO_DOUTTGL31_0_DIO23_BITN 23 -#define GPIO_DOUTTGL31_0_DIO23_M 0x00800000 -#define GPIO_DOUTTGL31_0_DIO23_S 23 +#define GPIO_DOUTTGL31_0_DIO23 0x00800000 +#define GPIO_DOUTTGL31_0_DIO23_BITN 23 +#define GPIO_DOUTTGL31_0_DIO23_M 0x00800000 +#define GPIO_DOUTTGL31_0_DIO23_S 23 // Field: [22] DIO22 // // Toggles bit 22 -#define GPIO_DOUTTGL31_0_DIO22 0x00400000 -#define GPIO_DOUTTGL31_0_DIO22_BITN 22 -#define GPIO_DOUTTGL31_0_DIO22_M 0x00400000 -#define GPIO_DOUTTGL31_0_DIO22_S 22 +#define GPIO_DOUTTGL31_0_DIO22 0x00400000 +#define GPIO_DOUTTGL31_0_DIO22_BITN 22 +#define GPIO_DOUTTGL31_0_DIO22_M 0x00400000 +#define GPIO_DOUTTGL31_0_DIO22_S 22 // Field: [21] DIO21 // // Toggles bit 21 -#define GPIO_DOUTTGL31_0_DIO21 0x00200000 -#define GPIO_DOUTTGL31_0_DIO21_BITN 21 -#define GPIO_DOUTTGL31_0_DIO21_M 0x00200000 -#define GPIO_DOUTTGL31_0_DIO21_S 21 +#define GPIO_DOUTTGL31_0_DIO21 0x00200000 +#define GPIO_DOUTTGL31_0_DIO21_BITN 21 +#define GPIO_DOUTTGL31_0_DIO21_M 0x00200000 +#define GPIO_DOUTTGL31_0_DIO21_S 21 // Field: [20] DIO20 // // Toggles bit 20 -#define GPIO_DOUTTGL31_0_DIO20 0x00100000 -#define GPIO_DOUTTGL31_0_DIO20_BITN 20 -#define GPIO_DOUTTGL31_0_DIO20_M 0x00100000 -#define GPIO_DOUTTGL31_0_DIO20_S 20 +#define GPIO_DOUTTGL31_0_DIO20 0x00100000 +#define GPIO_DOUTTGL31_0_DIO20_BITN 20 +#define GPIO_DOUTTGL31_0_DIO20_M 0x00100000 +#define GPIO_DOUTTGL31_0_DIO20_S 20 // Field: [19] DIO19 // // Toggles bit 19 -#define GPIO_DOUTTGL31_0_DIO19 0x00080000 -#define GPIO_DOUTTGL31_0_DIO19_BITN 19 -#define GPIO_DOUTTGL31_0_DIO19_M 0x00080000 -#define GPIO_DOUTTGL31_0_DIO19_S 19 +#define GPIO_DOUTTGL31_0_DIO19 0x00080000 +#define GPIO_DOUTTGL31_0_DIO19_BITN 19 +#define GPIO_DOUTTGL31_0_DIO19_M 0x00080000 +#define GPIO_DOUTTGL31_0_DIO19_S 19 // Field: [18] DIO18 // // Toggles bit 18 -#define GPIO_DOUTTGL31_0_DIO18 0x00040000 -#define GPIO_DOUTTGL31_0_DIO18_BITN 18 -#define GPIO_DOUTTGL31_0_DIO18_M 0x00040000 -#define GPIO_DOUTTGL31_0_DIO18_S 18 +#define GPIO_DOUTTGL31_0_DIO18 0x00040000 +#define GPIO_DOUTTGL31_0_DIO18_BITN 18 +#define GPIO_DOUTTGL31_0_DIO18_M 0x00040000 +#define GPIO_DOUTTGL31_0_DIO18_S 18 // Field: [17] DIO17 // // Toggles bit 17 -#define GPIO_DOUTTGL31_0_DIO17 0x00020000 -#define GPIO_DOUTTGL31_0_DIO17_BITN 17 -#define GPIO_DOUTTGL31_0_DIO17_M 0x00020000 -#define GPIO_DOUTTGL31_0_DIO17_S 17 +#define GPIO_DOUTTGL31_0_DIO17 0x00020000 +#define GPIO_DOUTTGL31_0_DIO17_BITN 17 +#define GPIO_DOUTTGL31_0_DIO17_M 0x00020000 +#define GPIO_DOUTTGL31_0_DIO17_S 17 // Field: [16] DIO16 // // Toggles bit 16 -#define GPIO_DOUTTGL31_0_DIO16 0x00010000 -#define GPIO_DOUTTGL31_0_DIO16_BITN 16 -#define GPIO_DOUTTGL31_0_DIO16_M 0x00010000 -#define GPIO_DOUTTGL31_0_DIO16_S 16 +#define GPIO_DOUTTGL31_0_DIO16 0x00010000 +#define GPIO_DOUTTGL31_0_DIO16_BITN 16 +#define GPIO_DOUTTGL31_0_DIO16_M 0x00010000 +#define GPIO_DOUTTGL31_0_DIO16_S 16 // Field: [15] DIO15 // // Toggles bit 15 -#define GPIO_DOUTTGL31_0_DIO15 0x00008000 -#define GPIO_DOUTTGL31_0_DIO15_BITN 15 -#define GPIO_DOUTTGL31_0_DIO15_M 0x00008000 -#define GPIO_DOUTTGL31_0_DIO15_S 15 +#define GPIO_DOUTTGL31_0_DIO15 0x00008000 +#define GPIO_DOUTTGL31_0_DIO15_BITN 15 +#define GPIO_DOUTTGL31_0_DIO15_M 0x00008000 +#define GPIO_DOUTTGL31_0_DIO15_S 15 // Field: [14] DIO14 // // Toggles bit 14 -#define GPIO_DOUTTGL31_0_DIO14 0x00004000 -#define GPIO_DOUTTGL31_0_DIO14_BITN 14 -#define GPIO_DOUTTGL31_0_DIO14_M 0x00004000 -#define GPIO_DOUTTGL31_0_DIO14_S 14 +#define GPIO_DOUTTGL31_0_DIO14 0x00004000 +#define GPIO_DOUTTGL31_0_DIO14_BITN 14 +#define GPIO_DOUTTGL31_0_DIO14_M 0x00004000 +#define GPIO_DOUTTGL31_0_DIO14_S 14 // Field: [13] DIO13 // // Toggles bit 13 -#define GPIO_DOUTTGL31_0_DIO13 0x00002000 -#define GPIO_DOUTTGL31_0_DIO13_BITN 13 -#define GPIO_DOUTTGL31_0_DIO13_M 0x00002000 -#define GPIO_DOUTTGL31_0_DIO13_S 13 +#define GPIO_DOUTTGL31_0_DIO13 0x00002000 +#define GPIO_DOUTTGL31_0_DIO13_BITN 13 +#define GPIO_DOUTTGL31_0_DIO13_M 0x00002000 +#define GPIO_DOUTTGL31_0_DIO13_S 13 // Field: [12] DIO12 // // Toggles bit 12 -#define GPIO_DOUTTGL31_0_DIO12 0x00001000 -#define GPIO_DOUTTGL31_0_DIO12_BITN 12 -#define GPIO_DOUTTGL31_0_DIO12_M 0x00001000 -#define GPIO_DOUTTGL31_0_DIO12_S 12 +#define GPIO_DOUTTGL31_0_DIO12 0x00001000 +#define GPIO_DOUTTGL31_0_DIO12_BITN 12 +#define GPIO_DOUTTGL31_0_DIO12_M 0x00001000 +#define GPIO_DOUTTGL31_0_DIO12_S 12 // Field: [11] DIO11 // // Toggles bit 11 -#define GPIO_DOUTTGL31_0_DIO11 0x00000800 -#define GPIO_DOUTTGL31_0_DIO11_BITN 11 -#define GPIO_DOUTTGL31_0_DIO11_M 0x00000800 -#define GPIO_DOUTTGL31_0_DIO11_S 11 +#define GPIO_DOUTTGL31_0_DIO11 0x00000800 +#define GPIO_DOUTTGL31_0_DIO11_BITN 11 +#define GPIO_DOUTTGL31_0_DIO11_M 0x00000800 +#define GPIO_DOUTTGL31_0_DIO11_S 11 // Field: [10] DIO10 // // Toggles bit 10 -#define GPIO_DOUTTGL31_0_DIO10 0x00000400 -#define GPIO_DOUTTGL31_0_DIO10_BITN 10 -#define GPIO_DOUTTGL31_0_DIO10_M 0x00000400 -#define GPIO_DOUTTGL31_0_DIO10_S 10 +#define GPIO_DOUTTGL31_0_DIO10 0x00000400 +#define GPIO_DOUTTGL31_0_DIO10_BITN 10 +#define GPIO_DOUTTGL31_0_DIO10_M 0x00000400 +#define GPIO_DOUTTGL31_0_DIO10_S 10 // Field: [9] DIO9 // // Toggles bit 9 -#define GPIO_DOUTTGL31_0_DIO9 0x00000200 -#define GPIO_DOUTTGL31_0_DIO9_BITN 9 -#define GPIO_DOUTTGL31_0_DIO9_M 0x00000200 -#define GPIO_DOUTTGL31_0_DIO9_S 9 +#define GPIO_DOUTTGL31_0_DIO9 0x00000200 +#define GPIO_DOUTTGL31_0_DIO9_BITN 9 +#define GPIO_DOUTTGL31_0_DIO9_M 0x00000200 +#define GPIO_DOUTTGL31_0_DIO9_S 9 // Field: [8] DIO8 // // Toggles bit 8 -#define GPIO_DOUTTGL31_0_DIO8 0x00000100 -#define GPIO_DOUTTGL31_0_DIO8_BITN 8 -#define GPIO_DOUTTGL31_0_DIO8_M 0x00000100 -#define GPIO_DOUTTGL31_0_DIO8_S 8 +#define GPIO_DOUTTGL31_0_DIO8 0x00000100 +#define GPIO_DOUTTGL31_0_DIO8_BITN 8 +#define GPIO_DOUTTGL31_0_DIO8_M 0x00000100 +#define GPIO_DOUTTGL31_0_DIO8_S 8 // Field: [7] DIO7 // // Toggles bit 7 -#define GPIO_DOUTTGL31_0_DIO7 0x00000080 -#define GPIO_DOUTTGL31_0_DIO7_BITN 7 -#define GPIO_DOUTTGL31_0_DIO7_M 0x00000080 -#define GPIO_DOUTTGL31_0_DIO7_S 7 +#define GPIO_DOUTTGL31_0_DIO7 0x00000080 +#define GPIO_DOUTTGL31_0_DIO7_BITN 7 +#define GPIO_DOUTTGL31_0_DIO7_M 0x00000080 +#define GPIO_DOUTTGL31_0_DIO7_S 7 // Field: [6] DIO6 // // Toggles bit 6 -#define GPIO_DOUTTGL31_0_DIO6 0x00000040 -#define GPIO_DOUTTGL31_0_DIO6_BITN 6 -#define GPIO_DOUTTGL31_0_DIO6_M 0x00000040 -#define GPIO_DOUTTGL31_0_DIO6_S 6 +#define GPIO_DOUTTGL31_0_DIO6 0x00000040 +#define GPIO_DOUTTGL31_0_DIO6_BITN 6 +#define GPIO_DOUTTGL31_0_DIO6_M 0x00000040 +#define GPIO_DOUTTGL31_0_DIO6_S 6 // Field: [5] DIO5 // // Toggles bit 5 -#define GPIO_DOUTTGL31_0_DIO5 0x00000020 -#define GPIO_DOUTTGL31_0_DIO5_BITN 5 -#define GPIO_DOUTTGL31_0_DIO5_M 0x00000020 -#define GPIO_DOUTTGL31_0_DIO5_S 5 +#define GPIO_DOUTTGL31_0_DIO5 0x00000020 +#define GPIO_DOUTTGL31_0_DIO5_BITN 5 +#define GPIO_DOUTTGL31_0_DIO5_M 0x00000020 +#define GPIO_DOUTTGL31_0_DIO5_S 5 // Field: [4] DIO4 // // Toggles bit 4 -#define GPIO_DOUTTGL31_0_DIO4 0x00000010 -#define GPIO_DOUTTGL31_0_DIO4_BITN 4 -#define GPIO_DOUTTGL31_0_DIO4_M 0x00000010 -#define GPIO_DOUTTGL31_0_DIO4_S 4 +#define GPIO_DOUTTGL31_0_DIO4 0x00000010 +#define GPIO_DOUTTGL31_0_DIO4_BITN 4 +#define GPIO_DOUTTGL31_0_DIO4_M 0x00000010 +#define GPIO_DOUTTGL31_0_DIO4_S 4 // Field: [3] DIO3 // // Toggles bit 3 -#define GPIO_DOUTTGL31_0_DIO3 0x00000008 -#define GPIO_DOUTTGL31_0_DIO3_BITN 3 -#define GPIO_DOUTTGL31_0_DIO3_M 0x00000008 -#define GPIO_DOUTTGL31_0_DIO3_S 3 +#define GPIO_DOUTTGL31_0_DIO3 0x00000008 +#define GPIO_DOUTTGL31_0_DIO3_BITN 3 +#define GPIO_DOUTTGL31_0_DIO3_M 0x00000008 +#define GPIO_DOUTTGL31_0_DIO3_S 3 // Field: [2] DIO2 // // Toggles bit 2 -#define GPIO_DOUTTGL31_0_DIO2 0x00000004 -#define GPIO_DOUTTGL31_0_DIO2_BITN 2 -#define GPIO_DOUTTGL31_0_DIO2_M 0x00000004 -#define GPIO_DOUTTGL31_0_DIO2_S 2 +#define GPIO_DOUTTGL31_0_DIO2 0x00000004 +#define GPIO_DOUTTGL31_0_DIO2_BITN 2 +#define GPIO_DOUTTGL31_0_DIO2_M 0x00000004 +#define GPIO_DOUTTGL31_0_DIO2_S 2 // Field: [1] DIO1 // // Toggles bit 1 -#define GPIO_DOUTTGL31_0_DIO1 0x00000002 -#define GPIO_DOUTTGL31_0_DIO1_BITN 1 -#define GPIO_DOUTTGL31_0_DIO1_M 0x00000002 -#define GPIO_DOUTTGL31_0_DIO1_S 1 +#define GPIO_DOUTTGL31_0_DIO1 0x00000002 +#define GPIO_DOUTTGL31_0_DIO1_BITN 1 +#define GPIO_DOUTTGL31_0_DIO1_M 0x00000002 +#define GPIO_DOUTTGL31_0_DIO1_S 1 // Field: [0] DIO0 // // Toggles bit 0 -#define GPIO_DOUTTGL31_0_DIO0 0x00000001 -#define GPIO_DOUTTGL31_0_DIO0_BITN 0 -#define GPIO_DOUTTGL31_0_DIO0_M 0x00000001 -#define GPIO_DOUTTGL31_0_DIO0_S 0 +#define GPIO_DOUTTGL31_0_DIO0 0x00000001 +#define GPIO_DOUTTGL31_0_DIO0_BITN 0 +#define GPIO_DOUTTGL31_0_DIO0_M 0x00000001 +#define GPIO_DOUTTGL31_0_DIO0_S 0 //***************************************************************************** // @@ -1468,258 +1468,258 @@ // Field: [31] DIO31 // // Data input from DIO 31 -#define GPIO_DIN31_0_DIO31 0x80000000 -#define GPIO_DIN31_0_DIO31_BITN 31 -#define GPIO_DIN31_0_DIO31_M 0x80000000 -#define GPIO_DIN31_0_DIO31_S 31 +#define GPIO_DIN31_0_DIO31 0x80000000 +#define GPIO_DIN31_0_DIO31_BITN 31 +#define GPIO_DIN31_0_DIO31_M 0x80000000 +#define GPIO_DIN31_0_DIO31_S 31 // Field: [30] DIO30 // // Data input from DIO 30 -#define GPIO_DIN31_0_DIO30 0x40000000 -#define GPIO_DIN31_0_DIO30_BITN 30 -#define GPIO_DIN31_0_DIO30_M 0x40000000 -#define GPIO_DIN31_0_DIO30_S 30 +#define GPIO_DIN31_0_DIO30 0x40000000 +#define GPIO_DIN31_0_DIO30_BITN 30 +#define GPIO_DIN31_0_DIO30_M 0x40000000 +#define GPIO_DIN31_0_DIO30_S 30 // Field: [29] DIO29 // // Data input from DIO 29 -#define GPIO_DIN31_0_DIO29 0x20000000 -#define GPIO_DIN31_0_DIO29_BITN 29 -#define GPIO_DIN31_0_DIO29_M 0x20000000 -#define GPIO_DIN31_0_DIO29_S 29 +#define GPIO_DIN31_0_DIO29 0x20000000 +#define GPIO_DIN31_0_DIO29_BITN 29 +#define GPIO_DIN31_0_DIO29_M 0x20000000 +#define GPIO_DIN31_0_DIO29_S 29 // Field: [28] DIO28 // // Data input from DIO 28 -#define GPIO_DIN31_0_DIO28 0x10000000 -#define GPIO_DIN31_0_DIO28_BITN 28 -#define GPIO_DIN31_0_DIO28_M 0x10000000 -#define GPIO_DIN31_0_DIO28_S 28 +#define GPIO_DIN31_0_DIO28 0x10000000 +#define GPIO_DIN31_0_DIO28_BITN 28 +#define GPIO_DIN31_0_DIO28_M 0x10000000 +#define GPIO_DIN31_0_DIO28_S 28 // Field: [27] DIO27 // // Data input from DIO 27 -#define GPIO_DIN31_0_DIO27 0x08000000 -#define GPIO_DIN31_0_DIO27_BITN 27 -#define GPIO_DIN31_0_DIO27_M 0x08000000 -#define GPIO_DIN31_0_DIO27_S 27 +#define GPIO_DIN31_0_DIO27 0x08000000 +#define GPIO_DIN31_0_DIO27_BITN 27 +#define GPIO_DIN31_0_DIO27_M 0x08000000 +#define GPIO_DIN31_0_DIO27_S 27 // Field: [26] DIO26 // // Data input from DIO 26 -#define GPIO_DIN31_0_DIO26 0x04000000 -#define GPIO_DIN31_0_DIO26_BITN 26 -#define GPIO_DIN31_0_DIO26_M 0x04000000 -#define GPIO_DIN31_0_DIO26_S 26 +#define GPIO_DIN31_0_DIO26 0x04000000 +#define GPIO_DIN31_0_DIO26_BITN 26 +#define GPIO_DIN31_0_DIO26_M 0x04000000 +#define GPIO_DIN31_0_DIO26_S 26 // Field: [25] DIO25 // // Data input from DIO 25 -#define GPIO_DIN31_0_DIO25 0x02000000 -#define GPIO_DIN31_0_DIO25_BITN 25 -#define GPIO_DIN31_0_DIO25_M 0x02000000 -#define GPIO_DIN31_0_DIO25_S 25 +#define GPIO_DIN31_0_DIO25 0x02000000 +#define GPIO_DIN31_0_DIO25_BITN 25 +#define GPIO_DIN31_0_DIO25_M 0x02000000 +#define GPIO_DIN31_0_DIO25_S 25 // Field: [24] DIO24 // // Data input from DIO 24 -#define GPIO_DIN31_0_DIO24 0x01000000 -#define GPIO_DIN31_0_DIO24_BITN 24 -#define GPIO_DIN31_0_DIO24_M 0x01000000 -#define GPIO_DIN31_0_DIO24_S 24 +#define GPIO_DIN31_0_DIO24 0x01000000 +#define GPIO_DIN31_0_DIO24_BITN 24 +#define GPIO_DIN31_0_DIO24_M 0x01000000 +#define GPIO_DIN31_0_DIO24_S 24 // Field: [23] DIO23 // // Data input from DIO 23 -#define GPIO_DIN31_0_DIO23 0x00800000 -#define GPIO_DIN31_0_DIO23_BITN 23 -#define GPIO_DIN31_0_DIO23_M 0x00800000 -#define GPIO_DIN31_0_DIO23_S 23 +#define GPIO_DIN31_0_DIO23 0x00800000 +#define GPIO_DIN31_0_DIO23_BITN 23 +#define GPIO_DIN31_0_DIO23_M 0x00800000 +#define GPIO_DIN31_0_DIO23_S 23 // Field: [22] DIO22 // // Data input from DIO 22 -#define GPIO_DIN31_0_DIO22 0x00400000 -#define GPIO_DIN31_0_DIO22_BITN 22 -#define GPIO_DIN31_0_DIO22_M 0x00400000 -#define GPIO_DIN31_0_DIO22_S 22 +#define GPIO_DIN31_0_DIO22 0x00400000 +#define GPIO_DIN31_0_DIO22_BITN 22 +#define GPIO_DIN31_0_DIO22_M 0x00400000 +#define GPIO_DIN31_0_DIO22_S 22 // Field: [21] DIO21 // // Data input from DIO 21 -#define GPIO_DIN31_0_DIO21 0x00200000 -#define GPIO_DIN31_0_DIO21_BITN 21 -#define GPIO_DIN31_0_DIO21_M 0x00200000 -#define GPIO_DIN31_0_DIO21_S 21 +#define GPIO_DIN31_0_DIO21 0x00200000 +#define GPIO_DIN31_0_DIO21_BITN 21 +#define GPIO_DIN31_0_DIO21_M 0x00200000 +#define GPIO_DIN31_0_DIO21_S 21 // Field: [20] DIO20 // // Data input from DIO 20 -#define GPIO_DIN31_0_DIO20 0x00100000 -#define GPIO_DIN31_0_DIO20_BITN 20 -#define GPIO_DIN31_0_DIO20_M 0x00100000 -#define GPIO_DIN31_0_DIO20_S 20 +#define GPIO_DIN31_0_DIO20 0x00100000 +#define GPIO_DIN31_0_DIO20_BITN 20 +#define GPIO_DIN31_0_DIO20_M 0x00100000 +#define GPIO_DIN31_0_DIO20_S 20 // Field: [19] DIO19 // // Data input from DIO 19 -#define GPIO_DIN31_0_DIO19 0x00080000 -#define GPIO_DIN31_0_DIO19_BITN 19 -#define GPIO_DIN31_0_DIO19_M 0x00080000 -#define GPIO_DIN31_0_DIO19_S 19 +#define GPIO_DIN31_0_DIO19 0x00080000 +#define GPIO_DIN31_0_DIO19_BITN 19 +#define GPIO_DIN31_0_DIO19_M 0x00080000 +#define GPIO_DIN31_0_DIO19_S 19 // Field: [18] DIO18 // // Data input from DIO 18 -#define GPIO_DIN31_0_DIO18 0x00040000 -#define GPIO_DIN31_0_DIO18_BITN 18 -#define GPIO_DIN31_0_DIO18_M 0x00040000 -#define GPIO_DIN31_0_DIO18_S 18 +#define GPIO_DIN31_0_DIO18 0x00040000 +#define GPIO_DIN31_0_DIO18_BITN 18 +#define GPIO_DIN31_0_DIO18_M 0x00040000 +#define GPIO_DIN31_0_DIO18_S 18 // Field: [17] DIO17 // // Data input from DIO 17 -#define GPIO_DIN31_0_DIO17 0x00020000 -#define GPIO_DIN31_0_DIO17_BITN 17 -#define GPIO_DIN31_0_DIO17_M 0x00020000 -#define GPIO_DIN31_0_DIO17_S 17 +#define GPIO_DIN31_0_DIO17 0x00020000 +#define GPIO_DIN31_0_DIO17_BITN 17 +#define GPIO_DIN31_0_DIO17_M 0x00020000 +#define GPIO_DIN31_0_DIO17_S 17 // Field: [16] DIO16 // // Data input from DIO 16 -#define GPIO_DIN31_0_DIO16 0x00010000 -#define GPIO_DIN31_0_DIO16_BITN 16 -#define GPIO_DIN31_0_DIO16_M 0x00010000 -#define GPIO_DIN31_0_DIO16_S 16 +#define GPIO_DIN31_0_DIO16 0x00010000 +#define GPIO_DIN31_0_DIO16_BITN 16 +#define GPIO_DIN31_0_DIO16_M 0x00010000 +#define GPIO_DIN31_0_DIO16_S 16 // Field: [15] DIO15 // // Data input from DIO 15 -#define GPIO_DIN31_0_DIO15 0x00008000 -#define GPIO_DIN31_0_DIO15_BITN 15 -#define GPIO_DIN31_0_DIO15_M 0x00008000 -#define GPIO_DIN31_0_DIO15_S 15 +#define GPIO_DIN31_0_DIO15 0x00008000 +#define GPIO_DIN31_0_DIO15_BITN 15 +#define GPIO_DIN31_0_DIO15_M 0x00008000 +#define GPIO_DIN31_0_DIO15_S 15 // Field: [14] DIO14 // // Data input from DIO 14 -#define GPIO_DIN31_0_DIO14 0x00004000 -#define GPIO_DIN31_0_DIO14_BITN 14 -#define GPIO_DIN31_0_DIO14_M 0x00004000 -#define GPIO_DIN31_0_DIO14_S 14 +#define GPIO_DIN31_0_DIO14 0x00004000 +#define GPIO_DIN31_0_DIO14_BITN 14 +#define GPIO_DIN31_0_DIO14_M 0x00004000 +#define GPIO_DIN31_0_DIO14_S 14 // Field: [13] DIO13 // // Data input from DIO 13 -#define GPIO_DIN31_0_DIO13 0x00002000 -#define GPIO_DIN31_0_DIO13_BITN 13 -#define GPIO_DIN31_0_DIO13_M 0x00002000 -#define GPIO_DIN31_0_DIO13_S 13 +#define GPIO_DIN31_0_DIO13 0x00002000 +#define GPIO_DIN31_0_DIO13_BITN 13 +#define GPIO_DIN31_0_DIO13_M 0x00002000 +#define GPIO_DIN31_0_DIO13_S 13 // Field: [12] DIO12 // // Data input from DIO 12 -#define GPIO_DIN31_0_DIO12 0x00001000 -#define GPIO_DIN31_0_DIO12_BITN 12 -#define GPIO_DIN31_0_DIO12_M 0x00001000 -#define GPIO_DIN31_0_DIO12_S 12 +#define GPIO_DIN31_0_DIO12 0x00001000 +#define GPIO_DIN31_0_DIO12_BITN 12 +#define GPIO_DIN31_0_DIO12_M 0x00001000 +#define GPIO_DIN31_0_DIO12_S 12 // Field: [11] DIO11 // // Data input from DIO 11 -#define GPIO_DIN31_0_DIO11 0x00000800 -#define GPIO_DIN31_0_DIO11_BITN 11 -#define GPIO_DIN31_0_DIO11_M 0x00000800 -#define GPIO_DIN31_0_DIO11_S 11 +#define GPIO_DIN31_0_DIO11 0x00000800 +#define GPIO_DIN31_0_DIO11_BITN 11 +#define GPIO_DIN31_0_DIO11_M 0x00000800 +#define GPIO_DIN31_0_DIO11_S 11 // Field: [10] DIO10 // // Data input from DIO 10 -#define GPIO_DIN31_0_DIO10 0x00000400 -#define GPIO_DIN31_0_DIO10_BITN 10 -#define GPIO_DIN31_0_DIO10_M 0x00000400 -#define GPIO_DIN31_0_DIO10_S 10 +#define GPIO_DIN31_0_DIO10 0x00000400 +#define GPIO_DIN31_0_DIO10_BITN 10 +#define GPIO_DIN31_0_DIO10_M 0x00000400 +#define GPIO_DIN31_0_DIO10_S 10 // Field: [9] DIO9 // // Data input from DIO 9 -#define GPIO_DIN31_0_DIO9 0x00000200 -#define GPIO_DIN31_0_DIO9_BITN 9 -#define GPIO_DIN31_0_DIO9_M 0x00000200 -#define GPIO_DIN31_0_DIO9_S 9 +#define GPIO_DIN31_0_DIO9 0x00000200 +#define GPIO_DIN31_0_DIO9_BITN 9 +#define GPIO_DIN31_0_DIO9_M 0x00000200 +#define GPIO_DIN31_0_DIO9_S 9 // Field: [8] DIO8 // // Data input from DIO 8 -#define GPIO_DIN31_0_DIO8 0x00000100 -#define GPIO_DIN31_0_DIO8_BITN 8 -#define GPIO_DIN31_0_DIO8_M 0x00000100 -#define GPIO_DIN31_0_DIO8_S 8 +#define GPIO_DIN31_0_DIO8 0x00000100 +#define GPIO_DIN31_0_DIO8_BITN 8 +#define GPIO_DIN31_0_DIO8_M 0x00000100 +#define GPIO_DIN31_0_DIO8_S 8 // Field: [7] DIO7 // // Data input from DIO 7 -#define GPIO_DIN31_0_DIO7 0x00000080 -#define GPIO_DIN31_0_DIO7_BITN 7 -#define GPIO_DIN31_0_DIO7_M 0x00000080 -#define GPIO_DIN31_0_DIO7_S 7 +#define GPIO_DIN31_0_DIO7 0x00000080 +#define GPIO_DIN31_0_DIO7_BITN 7 +#define GPIO_DIN31_0_DIO7_M 0x00000080 +#define GPIO_DIN31_0_DIO7_S 7 // Field: [6] DIO6 // // Data input from DIO 6 -#define GPIO_DIN31_0_DIO6 0x00000040 -#define GPIO_DIN31_0_DIO6_BITN 6 -#define GPIO_DIN31_0_DIO6_M 0x00000040 -#define GPIO_DIN31_0_DIO6_S 6 +#define GPIO_DIN31_0_DIO6 0x00000040 +#define GPIO_DIN31_0_DIO6_BITN 6 +#define GPIO_DIN31_0_DIO6_M 0x00000040 +#define GPIO_DIN31_0_DIO6_S 6 // Field: [5] DIO5 // // Data input from DIO 5 -#define GPIO_DIN31_0_DIO5 0x00000020 -#define GPIO_DIN31_0_DIO5_BITN 5 -#define GPIO_DIN31_0_DIO5_M 0x00000020 -#define GPIO_DIN31_0_DIO5_S 5 +#define GPIO_DIN31_0_DIO5 0x00000020 +#define GPIO_DIN31_0_DIO5_BITN 5 +#define GPIO_DIN31_0_DIO5_M 0x00000020 +#define GPIO_DIN31_0_DIO5_S 5 // Field: [4] DIO4 // // Data input from DIO 4 -#define GPIO_DIN31_0_DIO4 0x00000010 -#define GPIO_DIN31_0_DIO4_BITN 4 -#define GPIO_DIN31_0_DIO4_M 0x00000010 -#define GPIO_DIN31_0_DIO4_S 4 +#define GPIO_DIN31_0_DIO4 0x00000010 +#define GPIO_DIN31_0_DIO4_BITN 4 +#define GPIO_DIN31_0_DIO4_M 0x00000010 +#define GPIO_DIN31_0_DIO4_S 4 // Field: [3] DIO3 // // Data input from DIO 3 -#define GPIO_DIN31_0_DIO3 0x00000008 -#define GPIO_DIN31_0_DIO3_BITN 3 -#define GPIO_DIN31_0_DIO3_M 0x00000008 -#define GPIO_DIN31_0_DIO3_S 3 +#define GPIO_DIN31_0_DIO3 0x00000008 +#define GPIO_DIN31_0_DIO3_BITN 3 +#define GPIO_DIN31_0_DIO3_M 0x00000008 +#define GPIO_DIN31_0_DIO3_S 3 // Field: [2] DIO2 // // Data input from DIO 2 -#define GPIO_DIN31_0_DIO2 0x00000004 -#define GPIO_DIN31_0_DIO2_BITN 2 -#define GPIO_DIN31_0_DIO2_M 0x00000004 -#define GPIO_DIN31_0_DIO2_S 2 +#define GPIO_DIN31_0_DIO2 0x00000004 +#define GPIO_DIN31_0_DIO2_BITN 2 +#define GPIO_DIN31_0_DIO2_M 0x00000004 +#define GPIO_DIN31_0_DIO2_S 2 // Field: [1] DIO1 // // Data input from DIO 1 -#define GPIO_DIN31_0_DIO1 0x00000002 -#define GPIO_DIN31_0_DIO1_BITN 1 -#define GPIO_DIN31_0_DIO1_M 0x00000002 -#define GPIO_DIN31_0_DIO1_S 1 +#define GPIO_DIN31_0_DIO1 0x00000002 +#define GPIO_DIN31_0_DIO1_BITN 1 +#define GPIO_DIN31_0_DIO1_M 0x00000002 +#define GPIO_DIN31_0_DIO1_S 1 // Field: [0] DIO0 // // Data input from DIO 0 -#define GPIO_DIN31_0_DIO0 0x00000001 -#define GPIO_DIN31_0_DIO0_BITN 0 -#define GPIO_DIN31_0_DIO0_M 0x00000001 -#define GPIO_DIN31_0_DIO0_S 0 +#define GPIO_DIN31_0_DIO0 0x00000001 +#define GPIO_DIN31_0_DIO0_BITN 0 +#define GPIO_DIN31_0_DIO0_M 0x00000001 +#define GPIO_DIN31_0_DIO0_S 0 //***************************************************************************** // @@ -1729,258 +1729,258 @@ // Field: [31] DIO31 // // Data output enable for DIO 31 -#define GPIO_DOE31_0_DIO31 0x80000000 -#define GPIO_DOE31_0_DIO31_BITN 31 -#define GPIO_DOE31_0_DIO31_M 0x80000000 -#define GPIO_DOE31_0_DIO31_S 31 +#define GPIO_DOE31_0_DIO31 0x80000000 +#define GPIO_DOE31_0_DIO31_BITN 31 +#define GPIO_DOE31_0_DIO31_M 0x80000000 +#define GPIO_DOE31_0_DIO31_S 31 // Field: [30] DIO30 // // Data output enable for DIO 30 -#define GPIO_DOE31_0_DIO30 0x40000000 -#define GPIO_DOE31_0_DIO30_BITN 30 -#define GPIO_DOE31_0_DIO30_M 0x40000000 -#define GPIO_DOE31_0_DIO30_S 30 +#define GPIO_DOE31_0_DIO30 0x40000000 +#define GPIO_DOE31_0_DIO30_BITN 30 +#define GPIO_DOE31_0_DIO30_M 0x40000000 +#define GPIO_DOE31_0_DIO30_S 30 // Field: [29] DIO29 // // Data output enable for DIO 29 -#define GPIO_DOE31_0_DIO29 0x20000000 -#define GPIO_DOE31_0_DIO29_BITN 29 -#define GPIO_DOE31_0_DIO29_M 0x20000000 -#define GPIO_DOE31_0_DIO29_S 29 +#define GPIO_DOE31_0_DIO29 0x20000000 +#define GPIO_DOE31_0_DIO29_BITN 29 +#define GPIO_DOE31_0_DIO29_M 0x20000000 +#define GPIO_DOE31_0_DIO29_S 29 // Field: [28] DIO28 // // Data output enable for DIO 28 -#define GPIO_DOE31_0_DIO28 0x10000000 -#define GPIO_DOE31_0_DIO28_BITN 28 -#define GPIO_DOE31_0_DIO28_M 0x10000000 -#define GPIO_DOE31_0_DIO28_S 28 +#define GPIO_DOE31_0_DIO28 0x10000000 +#define GPIO_DOE31_0_DIO28_BITN 28 +#define GPIO_DOE31_0_DIO28_M 0x10000000 +#define GPIO_DOE31_0_DIO28_S 28 // Field: [27] DIO27 // // Data output enable for DIO 27 -#define GPIO_DOE31_0_DIO27 0x08000000 -#define GPIO_DOE31_0_DIO27_BITN 27 -#define GPIO_DOE31_0_DIO27_M 0x08000000 -#define GPIO_DOE31_0_DIO27_S 27 +#define GPIO_DOE31_0_DIO27 0x08000000 +#define GPIO_DOE31_0_DIO27_BITN 27 +#define GPIO_DOE31_0_DIO27_M 0x08000000 +#define GPIO_DOE31_0_DIO27_S 27 // Field: [26] DIO26 // // Data output enable for DIO 26 -#define GPIO_DOE31_0_DIO26 0x04000000 -#define GPIO_DOE31_0_DIO26_BITN 26 -#define GPIO_DOE31_0_DIO26_M 0x04000000 -#define GPIO_DOE31_0_DIO26_S 26 +#define GPIO_DOE31_0_DIO26 0x04000000 +#define GPIO_DOE31_0_DIO26_BITN 26 +#define GPIO_DOE31_0_DIO26_M 0x04000000 +#define GPIO_DOE31_0_DIO26_S 26 // Field: [25] DIO25 // // Data output enable for DIO 25 -#define GPIO_DOE31_0_DIO25 0x02000000 -#define GPIO_DOE31_0_DIO25_BITN 25 -#define GPIO_DOE31_0_DIO25_M 0x02000000 -#define GPIO_DOE31_0_DIO25_S 25 +#define GPIO_DOE31_0_DIO25 0x02000000 +#define GPIO_DOE31_0_DIO25_BITN 25 +#define GPIO_DOE31_0_DIO25_M 0x02000000 +#define GPIO_DOE31_0_DIO25_S 25 // Field: [24] DIO24 // // Data output enable for DIO 24 -#define GPIO_DOE31_0_DIO24 0x01000000 -#define GPIO_DOE31_0_DIO24_BITN 24 -#define GPIO_DOE31_0_DIO24_M 0x01000000 -#define GPIO_DOE31_0_DIO24_S 24 +#define GPIO_DOE31_0_DIO24 0x01000000 +#define GPIO_DOE31_0_DIO24_BITN 24 +#define GPIO_DOE31_0_DIO24_M 0x01000000 +#define GPIO_DOE31_0_DIO24_S 24 // Field: [23] DIO23 // // Data output enable for DIO 23 -#define GPIO_DOE31_0_DIO23 0x00800000 -#define GPIO_DOE31_0_DIO23_BITN 23 -#define GPIO_DOE31_0_DIO23_M 0x00800000 -#define GPIO_DOE31_0_DIO23_S 23 +#define GPIO_DOE31_0_DIO23 0x00800000 +#define GPIO_DOE31_0_DIO23_BITN 23 +#define GPIO_DOE31_0_DIO23_M 0x00800000 +#define GPIO_DOE31_0_DIO23_S 23 // Field: [22] DIO22 // // Data output enable for DIO 22 -#define GPIO_DOE31_0_DIO22 0x00400000 -#define GPIO_DOE31_0_DIO22_BITN 22 -#define GPIO_DOE31_0_DIO22_M 0x00400000 -#define GPIO_DOE31_0_DIO22_S 22 +#define GPIO_DOE31_0_DIO22 0x00400000 +#define GPIO_DOE31_0_DIO22_BITN 22 +#define GPIO_DOE31_0_DIO22_M 0x00400000 +#define GPIO_DOE31_0_DIO22_S 22 // Field: [21] DIO21 // // Data output enable for DIO 21 -#define GPIO_DOE31_0_DIO21 0x00200000 -#define GPIO_DOE31_0_DIO21_BITN 21 -#define GPIO_DOE31_0_DIO21_M 0x00200000 -#define GPIO_DOE31_0_DIO21_S 21 +#define GPIO_DOE31_0_DIO21 0x00200000 +#define GPIO_DOE31_0_DIO21_BITN 21 +#define GPIO_DOE31_0_DIO21_M 0x00200000 +#define GPIO_DOE31_0_DIO21_S 21 // Field: [20] DIO20 // // Data output enable for DIO 20 -#define GPIO_DOE31_0_DIO20 0x00100000 -#define GPIO_DOE31_0_DIO20_BITN 20 -#define GPIO_DOE31_0_DIO20_M 0x00100000 -#define GPIO_DOE31_0_DIO20_S 20 +#define GPIO_DOE31_0_DIO20 0x00100000 +#define GPIO_DOE31_0_DIO20_BITN 20 +#define GPIO_DOE31_0_DIO20_M 0x00100000 +#define GPIO_DOE31_0_DIO20_S 20 // Field: [19] DIO19 // // Data output enable for DIO 19 -#define GPIO_DOE31_0_DIO19 0x00080000 -#define GPIO_DOE31_0_DIO19_BITN 19 -#define GPIO_DOE31_0_DIO19_M 0x00080000 -#define GPIO_DOE31_0_DIO19_S 19 +#define GPIO_DOE31_0_DIO19 0x00080000 +#define GPIO_DOE31_0_DIO19_BITN 19 +#define GPIO_DOE31_0_DIO19_M 0x00080000 +#define GPIO_DOE31_0_DIO19_S 19 // Field: [18] DIO18 // // Data output enable for DIO 18 -#define GPIO_DOE31_0_DIO18 0x00040000 -#define GPIO_DOE31_0_DIO18_BITN 18 -#define GPIO_DOE31_0_DIO18_M 0x00040000 -#define GPIO_DOE31_0_DIO18_S 18 +#define GPIO_DOE31_0_DIO18 0x00040000 +#define GPIO_DOE31_0_DIO18_BITN 18 +#define GPIO_DOE31_0_DIO18_M 0x00040000 +#define GPIO_DOE31_0_DIO18_S 18 // Field: [17] DIO17 // // Data output enable for DIO 17 -#define GPIO_DOE31_0_DIO17 0x00020000 -#define GPIO_DOE31_0_DIO17_BITN 17 -#define GPIO_DOE31_0_DIO17_M 0x00020000 -#define GPIO_DOE31_0_DIO17_S 17 +#define GPIO_DOE31_0_DIO17 0x00020000 +#define GPIO_DOE31_0_DIO17_BITN 17 +#define GPIO_DOE31_0_DIO17_M 0x00020000 +#define GPIO_DOE31_0_DIO17_S 17 // Field: [16] DIO16 // // Data output enable for DIO 16 -#define GPIO_DOE31_0_DIO16 0x00010000 -#define GPIO_DOE31_0_DIO16_BITN 16 -#define GPIO_DOE31_0_DIO16_M 0x00010000 -#define GPIO_DOE31_0_DIO16_S 16 +#define GPIO_DOE31_0_DIO16 0x00010000 +#define GPIO_DOE31_0_DIO16_BITN 16 +#define GPIO_DOE31_0_DIO16_M 0x00010000 +#define GPIO_DOE31_0_DIO16_S 16 // Field: [15] DIO15 // // Data output enable for DIO 15 -#define GPIO_DOE31_0_DIO15 0x00008000 -#define GPIO_DOE31_0_DIO15_BITN 15 -#define GPIO_DOE31_0_DIO15_M 0x00008000 -#define GPIO_DOE31_0_DIO15_S 15 +#define GPIO_DOE31_0_DIO15 0x00008000 +#define GPIO_DOE31_0_DIO15_BITN 15 +#define GPIO_DOE31_0_DIO15_M 0x00008000 +#define GPIO_DOE31_0_DIO15_S 15 // Field: [14] DIO14 // // Data output enable for DIO 14 -#define GPIO_DOE31_0_DIO14 0x00004000 -#define GPIO_DOE31_0_DIO14_BITN 14 -#define GPIO_DOE31_0_DIO14_M 0x00004000 -#define GPIO_DOE31_0_DIO14_S 14 +#define GPIO_DOE31_0_DIO14 0x00004000 +#define GPIO_DOE31_0_DIO14_BITN 14 +#define GPIO_DOE31_0_DIO14_M 0x00004000 +#define GPIO_DOE31_0_DIO14_S 14 // Field: [13] DIO13 // // Data output enable for DIO 13 -#define GPIO_DOE31_0_DIO13 0x00002000 -#define GPIO_DOE31_0_DIO13_BITN 13 -#define GPIO_DOE31_0_DIO13_M 0x00002000 -#define GPIO_DOE31_0_DIO13_S 13 +#define GPIO_DOE31_0_DIO13 0x00002000 +#define GPIO_DOE31_0_DIO13_BITN 13 +#define GPIO_DOE31_0_DIO13_M 0x00002000 +#define GPIO_DOE31_0_DIO13_S 13 // Field: [12] DIO12 // // Data output enable for DIO 12 -#define GPIO_DOE31_0_DIO12 0x00001000 -#define GPIO_DOE31_0_DIO12_BITN 12 -#define GPIO_DOE31_0_DIO12_M 0x00001000 -#define GPIO_DOE31_0_DIO12_S 12 +#define GPIO_DOE31_0_DIO12 0x00001000 +#define GPIO_DOE31_0_DIO12_BITN 12 +#define GPIO_DOE31_0_DIO12_M 0x00001000 +#define GPIO_DOE31_0_DIO12_S 12 // Field: [11] DIO11 // // Data output enable for DIO 11 -#define GPIO_DOE31_0_DIO11 0x00000800 -#define GPIO_DOE31_0_DIO11_BITN 11 -#define GPIO_DOE31_0_DIO11_M 0x00000800 -#define GPIO_DOE31_0_DIO11_S 11 +#define GPIO_DOE31_0_DIO11 0x00000800 +#define GPIO_DOE31_0_DIO11_BITN 11 +#define GPIO_DOE31_0_DIO11_M 0x00000800 +#define GPIO_DOE31_0_DIO11_S 11 // Field: [10] DIO10 // // Data output enable for DIO 10 -#define GPIO_DOE31_0_DIO10 0x00000400 -#define GPIO_DOE31_0_DIO10_BITN 10 -#define GPIO_DOE31_0_DIO10_M 0x00000400 -#define GPIO_DOE31_0_DIO10_S 10 +#define GPIO_DOE31_0_DIO10 0x00000400 +#define GPIO_DOE31_0_DIO10_BITN 10 +#define GPIO_DOE31_0_DIO10_M 0x00000400 +#define GPIO_DOE31_0_DIO10_S 10 // Field: [9] DIO9 // // Data output enable for DIO 9 -#define GPIO_DOE31_0_DIO9 0x00000200 -#define GPIO_DOE31_0_DIO9_BITN 9 -#define GPIO_DOE31_0_DIO9_M 0x00000200 -#define GPIO_DOE31_0_DIO9_S 9 +#define GPIO_DOE31_0_DIO9 0x00000200 +#define GPIO_DOE31_0_DIO9_BITN 9 +#define GPIO_DOE31_0_DIO9_M 0x00000200 +#define GPIO_DOE31_0_DIO9_S 9 // Field: [8] DIO8 // // Data output enable for DIO 8 -#define GPIO_DOE31_0_DIO8 0x00000100 -#define GPIO_DOE31_0_DIO8_BITN 8 -#define GPIO_DOE31_0_DIO8_M 0x00000100 -#define GPIO_DOE31_0_DIO8_S 8 +#define GPIO_DOE31_0_DIO8 0x00000100 +#define GPIO_DOE31_0_DIO8_BITN 8 +#define GPIO_DOE31_0_DIO8_M 0x00000100 +#define GPIO_DOE31_0_DIO8_S 8 // Field: [7] DIO7 // // Data output enable for DIO 7 -#define GPIO_DOE31_0_DIO7 0x00000080 -#define GPIO_DOE31_0_DIO7_BITN 7 -#define GPIO_DOE31_0_DIO7_M 0x00000080 -#define GPIO_DOE31_0_DIO7_S 7 +#define GPIO_DOE31_0_DIO7 0x00000080 +#define GPIO_DOE31_0_DIO7_BITN 7 +#define GPIO_DOE31_0_DIO7_M 0x00000080 +#define GPIO_DOE31_0_DIO7_S 7 // Field: [6] DIO6 // // Data output enable for DIO 6 -#define GPIO_DOE31_0_DIO6 0x00000040 -#define GPIO_DOE31_0_DIO6_BITN 6 -#define GPIO_DOE31_0_DIO6_M 0x00000040 -#define GPIO_DOE31_0_DIO6_S 6 +#define GPIO_DOE31_0_DIO6 0x00000040 +#define GPIO_DOE31_0_DIO6_BITN 6 +#define GPIO_DOE31_0_DIO6_M 0x00000040 +#define GPIO_DOE31_0_DIO6_S 6 // Field: [5] DIO5 // // Data output enable for DIO 5 -#define GPIO_DOE31_0_DIO5 0x00000020 -#define GPIO_DOE31_0_DIO5_BITN 5 -#define GPIO_DOE31_0_DIO5_M 0x00000020 -#define GPIO_DOE31_0_DIO5_S 5 +#define GPIO_DOE31_0_DIO5 0x00000020 +#define GPIO_DOE31_0_DIO5_BITN 5 +#define GPIO_DOE31_0_DIO5_M 0x00000020 +#define GPIO_DOE31_0_DIO5_S 5 // Field: [4] DIO4 // // Data output enable for DIO 4 -#define GPIO_DOE31_0_DIO4 0x00000010 -#define GPIO_DOE31_0_DIO4_BITN 4 -#define GPIO_DOE31_0_DIO4_M 0x00000010 -#define GPIO_DOE31_0_DIO4_S 4 +#define GPIO_DOE31_0_DIO4 0x00000010 +#define GPIO_DOE31_0_DIO4_BITN 4 +#define GPIO_DOE31_0_DIO4_M 0x00000010 +#define GPIO_DOE31_0_DIO4_S 4 // Field: [3] DIO3 // // Data output enable for DIO 3 -#define GPIO_DOE31_0_DIO3 0x00000008 -#define GPIO_DOE31_0_DIO3_BITN 3 -#define GPIO_DOE31_0_DIO3_M 0x00000008 -#define GPIO_DOE31_0_DIO3_S 3 +#define GPIO_DOE31_0_DIO3 0x00000008 +#define GPIO_DOE31_0_DIO3_BITN 3 +#define GPIO_DOE31_0_DIO3_M 0x00000008 +#define GPIO_DOE31_0_DIO3_S 3 // Field: [2] DIO2 // // Data output enable for DIO 2 -#define GPIO_DOE31_0_DIO2 0x00000004 -#define GPIO_DOE31_0_DIO2_BITN 2 -#define GPIO_DOE31_0_DIO2_M 0x00000004 -#define GPIO_DOE31_0_DIO2_S 2 +#define GPIO_DOE31_0_DIO2 0x00000004 +#define GPIO_DOE31_0_DIO2_BITN 2 +#define GPIO_DOE31_0_DIO2_M 0x00000004 +#define GPIO_DOE31_0_DIO2_S 2 // Field: [1] DIO1 // // Data output enable for DIO 1 -#define GPIO_DOE31_0_DIO1 0x00000002 -#define GPIO_DOE31_0_DIO1_BITN 1 -#define GPIO_DOE31_0_DIO1_M 0x00000002 -#define GPIO_DOE31_0_DIO1_S 1 +#define GPIO_DOE31_0_DIO1 0x00000002 +#define GPIO_DOE31_0_DIO1_BITN 1 +#define GPIO_DOE31_0_DIO1_M 0x00000002 +#define GPIO_DOE31_0_DIO1_S 1 // Field: [0] DIO0 // // Data output enable for DIO 0 -#define GPIO_DOE31_0_DIO0 0x00000001 -#define GPIO_DOE31_0_DIO0_BITN 0 -#define GPIO_DOE31_0_DIO0_M 0x00000001 -#define GPIO_DOE31_0_DIO0_S 0 +#define GPIO_DOE31_0_DIO0 0x00000001 +#define GPIO_DOE31_0_DIO0_BITN 0 +#define GPIO_DOE31_0_DIO0_M 0x00000001 +#define GPIO_DOE31_0_DIO0_S 0 //***************************************************************************** // @@ -1990,258 +1990,257 @@ // Field: [31] DIO31 // // Event for DIO 31 -#define GPIO_EVFLAGS31_0_DIO31 0x80000000 -#define GPIO_EVFLAGS31_0_DIO31_BITN 31 -#define GPIO_EVFLAGS31_0_DIO31_M 0x80000000 -#define GPIO_EVFLAGS31_0_DIO31_S 31 +#define GPIO_EVFLAGS31_0_DIO31 0x80000000 +#define GPIO_EVFLAGS31_0_DIO31_BITN 31 +#define GPIO_EVFLAGS31_0_DIO31_M 0x80000000 +#define GPIO_EVFLAGS31_0_DIO31_S 31 // Field: [30] DIO30 // // Event for DIO 30 -#define GPIO_EVFLAGS31_0_DIO30 0x40000000 -#define GPIO_EVFLAGS31_0_DIO30_BITN 30 -#define GPIO_EVFLAGS31_0_DIO30_M 0x40000000 -#define GPIO_EVFLAGS31_0_DIO30_S 30 +#define GPIO_EVFLAGS31_0_DIO30 0x40000000 +#define GPIO_EVFLAGS31_0_DIO30_BITN 30 +#define GPIO_EVFLAGS31_0_DIO30_M 0x40000000 +#define GPIO_EVFLAGS31_0_DIO30_S 30 // Field: [29] DIO29 // // Event for DIO 29 -#define GPIO_EVFLAGS31_0_DIO29 0x20000000 -#define GPIO_EVFLAGS31_0_DIO29_BITN 29 -#define GPIO_EVFLAGS31_0_DIO29_M 0x20000000 -#define GPIO_EVFLAGS31_0_DIO29_S 29 +#define GPIO_EVFLAGS31_0_DIO29 0x20000000 +#define GPIO_EVFLAGS31_0_DIO29_BITN 29 +#define GPIO_EVFLAGS31_0_DIO29_M 0x20000000 +#define GPIO_EVFLAGS31_0_DIO29_S 29 // Field: [28] DIO28 // // Event for DIO 28 -#define GPIO_EVFLAGS31_0_DIO28 0x10000000 -#define GPIO_EVFLAGS31_0_DIO28_BITN 28 -#define GPIO_EVFLAGS31_0_DIO28_M 0x10000000 -#define GPIO_EVFLAGS31_0_DIO28_S 28 +#define GPIO_EVFLAGS31_0_DIO28 0x10000000 +#define GPIO_EVFLAGS31_0_DIO28_BITN 28 +#define GPIO_EVFLAGS31_0_DIO28_M 0x10000000 +#define GPIO_EVFLAGS31_0_DIO28_S 28 // Field: [27] DIO27 // // Event for DIO 27 -#define GPIO_EVFLAGS31_0_DIO27 0x08000000 -#define GPIO_EVFLAGS31_0_DIO27_BITN 27 -#define GPIO_EVFLAGS31_0_DIO27_M 0x08000000 -#define GPIO_EVFLAGS31_0_DIO27_S 27 +#define GPIO_EVFLAGS31_0_DIO27 0x08000000 +#define GPIO_EVFLAGS31_0_DIO27_BITN 27 +#define GPIO_EVFLAGS31_0_DIO27_M 0x08000000 +#define GPIO_EVFLAGS31_0_DIO27_S 27 // Field: [26] DIO26 // // Event for DIO 26 -#define GPIO_EVFLAGS31_0_DIO26 0x04000000 -#define GPIO_EVFLAGS31_0_DIO26_BITN 26 -#define GPIO_EVFLAGS31_0_DIO26_M 0x04000000 -#define GPIO_EVFLAGS31_0_DIO26_S 26 +#define GPIO_EVFLAGS31_0_DIO26 0x04000000 +#define GPIO_EVFLAGS31_0_DIO26_BITN 26 +#define GPIO_EVFLAGS31_0_DIO26_M 0x04000000 +#define GPIO_EVFLAGS31_0_DIO26_S 26 // Field: [25] DIO25 // // Event for DIO 25 -#define GPIO_EVFLAGS31_0_DIO25 0x02000000 -#define GPIO_EVFLAGS31_0_DIO25_BITN 25 -#define GPIO_EVFLAGS31_0_DIO25_M 0x02000000 -#define GPIO_EVFLAGS31_0_DIO25_S 25 +#define GPIO_EVFLAGS31_0_DIO25 0x02000000 +#define GPIO_EVFLAGS31_0_DIO25_BITN 25 +#define GPIO_EVFLAGS31_0_DIO25_M 0x02000000 +#define GPIO_EVFLAGS31_0_DIO25_S 25 // Field: [24] DIO24 // // Event for DIO 24 -#define GPIO_EVFLAGS31_0_DIO24 0x01000000 -#define GPIO_EVFLAGS31_0_DIO24_BITN 24 -#define GPIO_EVFLAGS31_0_DIO24_M 0x01000000 -#define GPIO_EVFLAGS31_0_DIO24_S 24 +#define GPIO_EVFLAGS31_0_DIO24 0x01000000 +#define GPIO_EVFLAGS31_0_DIO24_BITN 24 +#define GPIO_EVFLAGS31_0_DIO24_M 0x01000000 +#define GPIO_EVFLAGS31_0_DIO24_S 24 // Field: [23] DIO23 // // Event for DIO 23 -#define GPIO_EVFLAGS31_0_DIO23 0x00800000 -#define GPIO_EVFLAGS31_0_DIO23_BITN 23 -#define GPIO_EVFLAGS31_0_DIO23_M 0x00800000 -#define GPIO_EVFLAGS31_0_DIO23_S 23 +#define GPIO_EVFLAGS31_0_DIO23 0x00800000 +#define GPIO_EVFLAGS31_0_DIO23_BITN 23 +#define GPIO_EVFLAGS31_0_DIO23_M 0x00800000 +#define GPIO_EVFLAGS31_0_DIO23_S 23 // Field: [22] DIO22 // // Event for DIO 22 -#define GPIO_EVFLAGS31_0_DIO22 0x00400000 -#define GPIO_EVFLAGS31_0_DIO22_BITN 22 -#define GPIO_EVFLAGS31_0_DIO22_M 0x00400000 -#define GPIO_EVFLAGS31_0_DIO22_S 22 +#define GPIO_EVFLAGS31_0_DIO22 0x00400000 +#define GPIO_EVFLAGS31_0_DIO22_BITN 22 +#define GPIO_EVFLAGS31_0_DIO22_M 0x00400000 +#define GPIO_EVFLAGS31_0_DIO22_S 22 // Field: [21] DIO21 // // Event for DIO 21 -#define GPIO_EVFLAGS31_0_DIO21 0x00200000 -#define GPIO_EVFLAGS31_0_DIO21_BITN 21 -#define GPIO_EVFLAGS31_0_DIO21_M 0x00200000 -#define GPIO_EVFLAGS31_0_DIO21_S 21 +#define GPIO_EVFLAGS31_0_DIO21 0x00200000 +#define GPIO_EVFLAGS31_0_DIO21_BITN 21 +#define GPIO_EVFLAGS31_0_DIO21_M 0x00200000 +#define GPIO_EVFLAGS31_0_DIO21_S 21 // Field: [20] DIO20 // // Event for DIO 20 -#define GPIO_EVFLAGS31_0_DIO20 0x00100000 -#define GPIO_EVFLAGS31_0_DIO20_BITN 20 -#define GPIO_EVFLAGS31_0_DIO20_M 0x00100000 -#define GPIO_EVFLAGS31_0_DIO20_S 20 +#define GPIO_EVFLAGS31_0_DIO20 0x00100000 +#define GPIO_EVFLAGS31_0_DIO20_BITN 20 +#define GPIO_EVFLAGS31_0_DIO20_M 0x00100000 +#define GPIO_EVFLAGS31_0_DIO20_S 20 // Field: [19] DIO19 // // Event for DIO 19 -#define GPIO_EVFLAGS31_0_DIO19 0x00080000 -#define GPIO_EVFLAGS31_0_DIO19_BITN 19 -#define GPIO_EVFLAGS31_0_DIO19_M 0x00080000 -#define GPIO_EVFLAGS31_0_DIO19_S 19 +#define GPIO_EVFLAGS31_0_DIO19 0x00080000 +#define GPIO_EVFLAGS31_0_DIO19_BITN 19 +#define GPIO_EVFLAGS31_0_DIO19_M 0x00080000 +#define GPIO_EVFLAGS31_0_DIO19_S 19 // Field: [18] DIO18 // // Event for DIO 18 -#define GPIO_EVFLAGS31_0_DIO18 0x00040000 -#define GPIO_EVFLAGS31_0_DIO18_BITN 18 -#define GPIO_EVFLAGS31_0_DIO18_M 0x00040000 -#define GPIO_EVFLAGS31_0_DIO18_S 18 +#define GPIO_EVFLAGS31_0_DIO18 0x00040000 +#define GPIO_EVFLAGS31_0_DIO18_BITN 18 +#define GPIO_EVFLAGS31_0_DIO18_M 0x00040000 +#define GPIO_EVFLAGS31_0_DIO18_S 18 // Field: [17] DIO17 // // Event for DIO 17 -#define GPIO_EVFLAGS31_0_DIO17 0x00020000 -#define GPIO_EVFLAGS31_0_DIO17_BITN 17 -#define GPIO_EVFLAGS31_0_DIO17_M 0x00020000 -#define GPIO_EVFLAGS31_0_DIO17_S 17 +#define GPIO_EVFLAGS31_0_DIO17 0x00020000 +#define GPIO_EVFLAGS31_0_DIO17_BITN 17 +#define GPIO_EVFLAGS31_0_DIO17_M 0x00020000 +#define GPIO_EVFLAGS31_0_DIO17_S 17 // Field: [16] DIO16 // // Event for DIO 16 -#define GPIO_EVFLAGS31_0_DIO16 0x00010000 -#define GPIO_EVFLAGS31_0_DIO16_BITN 16 -#define GPIO_EVFLAGS31_0_DIO16_M 0x00010000 -#define GPIO_EVFLAGS31_0_DIO16_S 16 +#define GPIO_EVFLAGS31_0_DIO16 0x00010000 +#define GPIO_EVFLAGS31_0_DIO16_BITN 16 +#define GPIO_EVFLAGS31_0_DIO16_M 0x00010000 +#define GPIO_EVFLAGS31_0_DIO16_S 16 // Field: [15] DIO15 // // Event for DIO 15 -#define GPIO_EVFLAGS31_0_DIO15 0x00008000 -#define GPIO_EVFLAGS31_0_DIO15_BITN 15 -#define GPIO_EVFLAGS31_0_DIO15_M 0x00008000 -#define GPIO_EVFLAGS31_0_DIO15_S 15 +#define GPIO_EVFLAGS31_0_DIO15 0x00008000 +#define GPIO_EVFLAGS31_0_DIO15_BITN 15 +#define GPIO_EVFLAGS31_0_DIO15_M 0x00008000 +#define GPIO_EVFLAGS31_0_DIO15_S 15 // Field: [14] DIO14 // // Event for DIO 14 -#define GPIO_EVFLAGS31_0_DIO14 0x00004000 -#define GPIO_EVFLAGS31_0_DIO14_BITN 14 -#define GPIO_EVFLAGS31_0_DIO14_M 0x00004000 -#define GPIO_EVFLAGS31_0_DIO14_S 14 +#define GPIO_EVFLAGS31_0_DIO14 0x00004000 +#define GPIO_EVFLAGS31_0_DIO14_BITN 14 +#define GPIO_EVFLAGS31_0_DIO14_M 0x00004000 +#define GPIO_EVFLAGS31_0_DIO14_S 14 // Field: [13] DIO13 // // Event for DIO 13 -#define GPIO_EVFLAGS31_0_DIO13 0x00002000 -#define GPIO_EVFLAGS31_0_DIO13_BITN 13 -#define GPIO_EVFLAGS31_0_DIO13_M 0x00002000 -#define GPIO_EVFLAGS31_0_DIO13_S 13 +#define GPIO_EVFLAGS31_0_DIO13 0x00002000 +#define GPIO_EVFLAGS31_0_DIO13_BITN 13 +#define GPIO_EVFLAGS31_0_DIO13_M 0x00002000 +#define GPIO_EVFLAGS31_0_DIO13_S 13 // Field: [12] DIO12 // // Event for DIO 12 -#define GPIO_EVFLAGS31_0_DIO12 0x00001000 -#define GPIO_EVFLAGS31_0_DIO12_BITN 12 -#define GPIO_EVFLAGS31_0_DIO12_M 0x00001000 -#define GPIO_EVFLAGS31_0_DIO12_S 12 +#define GPIO_EVFLAGS31_0_DIO12 0x00001000 +#define GPIO_EVFLAGS31_0_DIO12_BITN 12 +#define GPIO_EVFLAGS31_0_DIO12_M 0x00001000 +#define GPIO_EVFLAGS31_0_DIO12_S 12 // Field: [11] DIO11 // // Event for DIO 11 -#define GPIO_EVFLAGS31_0_DIO11 0x00000800 -#define GPIO_EVFLAGS31_0_DIO11_BITN 11 -#define GPIO_EVFLAGS31_0_DIO11_M 0x00000800 -#define GPIO_EVFLAGS31_0_DIO11_S 11 +#define GPIO_EVFLAGS31_0_DIO11 0x00000800 +#define GPIO_EVFLAGS31_0_DIO11_BITN 11 +#define GPIO_EVFLAGS31_0_DIO11_M 0x00000800 +#define GPIO_EVFLAGS31_0_DIO11_S 11 // Field: [10] DIO10 // // Event for DIO 10 -#define GPIO_EVFLAGS31_0_DIO10 0x00000400 -#define GPIO_EVFLAGS31_0_DIO10_BITN 10 -#define GPIO_EVFLAGS31_0_DIO10_M 0x00000400 -#define GPIO_EVFLAGS31_0_DIO10_S 10 +#define GPIO_EVFLAGS31_0_DIO10 0x00000400 +#define GPIO_EVFLAGS31_0_DIO10_BITN 10 +#define GPIO_EVFLAGS31_0_DIO10_M 0x00000400 +#define GPIO_EVFLAGS31_0_DIO10_S 10 // Field: [9] DIO9 // // Event for DIO 9 -#define GPIO_EVFLAGS31_0_DIO9 0x00000200 -#define GPIO_EVFLAGS31_0_DIO9_BITN 9 -#define GPIO_EVFLAGS31_0_DIO9_M 0x00000200 -#define GPIO_EVFLAGS31_0_DIO9_S 9 +#define GPIO_EVFLAGS31_0_DIO9 0x00000200 +#define GPIO_EVFLAGS31_0_DIO9_BITN 9 +#define GPIO_EVFLAGS31_0_DIO9_M 0x00000200 +#define GPIO_EVFLAGS31_0_DIO9_S 9 // Field: [8] DIO8 // // Event for DIO 8 -#define GPIO_EVFLAGS31_0_DIO8 0x00000100 -#define GPIO_EVFLAGS31_0_DIO8_BITN 8 -#define GPIO_EVFLAGS31_0_DIO8_M 0x00000100 -#define GPIO_EVFLAGS31_0_DIO8_S 8 +#define GPIO_EVFLAGS31_0_DIO8 0x00000100 +#define GPIO_EVFLAGS31_0_DIO8_BITN 8 +#define GPIO_EVFLAGS31_0_DIO8_M 0x00000100 +#define GPIO_EVFLAGS31_0_DIO8_S 8 // Field: [7] DIO7 // // Event for DIO 7 -#define GPIO_EVFLAGS31_0_DIO7 0x00000080 -#define GPIO_EVFLAGS31_0_DIO7_BITN 7 -#define GPIO_EVFLAGS31_0_DIO7_M 0x00000080 -#define GPIO_EVFLAGS31_0_DIO7_S 7 +#define GPIO_EVFLAGS31_0_DIO7 0x00000080 +#define GPIO_EVFLAGS31_0_DIO7_BITN 7 +#define GPIO_EVFLAGS31_0_DIO7_M 0x00000080 +#define GPIO_EVFLAGS31_0_DIO7_S 7 // Field: [6] DIO6 // // Event for DIO 6 -#define GPIO_EVFLAGS31_0_DIO6 0x00000040 -#define GPIO_EVFLAGS31_0_DIO6_BITN 6 -#define GPIO_EVFLAGS31_0_DIO6_M 0x00000040 -#define GPIO_EVFLAGS31_0_DIO6_S 6 +#define GPIO_EVFLAGS31_0_DIO6 0x00000040 +#define GPIO_EVFLAGS31_0_DIO6_BITN 6 +#define GPIO_EVFLAGS31_0_DIO6_M 0x00000040 +#define GPIO_EVFLAGS31_0_DIO6_S 6 // Field: [5] DIO5 // // Event for DIO 5 -#define GPIO_EVFLAGS31_0_DIO5 0x00000020 -#define GPIO_EVFLAGS31_0_DIO5_BITN 5 -#define GPIO_EVFLAGS31_0_DIO5_M 0x00000020 -#define GPIO_EVFLAGS31_0_DIO5_S 5 +#define GPIO_EVFLAGS31_0_DIO5 0x00000020 +#define GPIO_EVFLAGS31_0_DIO5_BITN 5 +#define GPIO_EVFLAGS31_0_DIO5_M 0x00000020 +#define GPIO_EVFLAGS31_0_DIO5_S 5 // Field: [4] DIO4 // // Event for DIO 4 -#define GPIO_EVFLAGS31_0_DIO4 0x00000010 -#define GPIO_EVFLAGS31_0_DIO4_BITN 4 -#define GPIO_EVFLAGS31_0_DIO4_M 0x00000010 -#define GPIO_EVFLAGS31_0_DIO4_S 4 +#define GPIO_EVFLAGS31_0_DIO4 0x00000010 +#define GPIO_EVFLAGS31_0_DIO4_BITN 4 +#define GPIO_EVFLAGS31_0_DIO4_M 0x00000010 +#define GPIO_EVFLAGS31_0_DIO4_S 4 // Field: [3] DIO3 // // Event for DIO 3 -#define GPIO_EVFLAGS31_0_DIO3 0x00000008 -#define GPIO_EVFLAGS31_0_DIO3_BITN 3 -#define GPIO_EVFLAGS31_0_DIO3_M 0x00000008 -#define GPIO_EVFLAGS31_0_DIO3_S 3 +#define GPIO_EVFLAGS31_0_DIO3 0x00000008 +#define GPIO_EVFLAGS31_0_DIO3_BITN 3 +#define GPIO_EVFLAGS31_0_DIO3_M 0x00000008 +#define GPIO_EVFLAGS31_0_DIO3_S 3 // Field: [2] DIO2 // // Event for DIO 2 -#define GPIO_EVFLAGS31_0_DIO2 0x00000004 -#define GPIO_EVFLAGS31_0_DIO2_BITN 2 -#define GPIO_EVFLAGS31_0_DIO2_M 0x00000004 -#define GPIO_EVFLAGS31_0_DIO2_S 2 +#define GPIO_EVFLAGS31_0_DIO2 0x00000004 +#define GPIO_EVFLAGS31_0_DIO2_BITN 2 +#define GPIO_EVFLAGS31_0_DIO2_M 0x00000004 +#define GPIO_EVFLAGS31_0_DIO2_S 2 // Field: [1] DIO1 // // Event for DIO 1 -#define GPIO_EVFLAGS31_0_DIO1 0x00000002 -#define GPIO_EVFLAGS31_0_DIO1_BITN 1 -#define GPIO_EVFLAGS31_0_DIO1_M 0x00000002 -#define GPIO_EVFLAGS31_0_DIO1_S 1 +#define GPIO_EVFLAGS31_0_DIO1 0x00000002 +#define GPIO_EVFLAGS31_0_DIO1_BITN 1 +#define GPIO_EVFLAGS31_0_DIO1_M 0x00000002 +#define GPIO_EVFLAGS31_0_DIO1_S 1 // Field: [0] DIO0 // // Event for DIO 0 -#define GPIO_EVFLAGS31_0_DIO0 0x00000001 -#define GPIO_EVFLAGS31_0_DIO0_BITN 0 -#define GPIO_EVFLAGS31_0_DIO0_M 0x00000001 -#define GPIO_EVFLAGS31_0_DIO0_S 0 - +#define GPIO_EVFLAGS31_0_DIO0 0x00000001 +#define GPIO_EVFLAGS31_0_DIO0_BITN 0 +#define GPIO_EVFLAGS31_0_DIO0_M 0x00000001 +#define GPIO_EVFLAGS31_0_DIO0_S 0 #endif // __GPIO__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_gpt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_gpt.h index 710edd8..4836c50 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_gpt.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_gpt.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_gpt_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_gpt_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_GPT_H__ #define __HW_GPT_H__ @@ -44,88 +44,88 @@ // //***************************************************************************** // Configuration -#define GPT_O_CFG 0x00000000 +#define GPT_O_CFG 0x00000000 // Timer A Mode -#define GPT_O_TAMR 0x00000004 +#define GPT_O_TAMR 0x00000004 // Timer B Mode -#define GPT_O_TBMR 0x00000008 +#define GPT_O_TBMR 0x00000008 // Control -#define GPT_O_CTL 0x0000000C +#define GPT_O_CTL 0x0000000C // Synch Register -#define GPT_O_SYNC 0x00000010 +#define GPT_O_SYNC 0x00000010 // Interrupt Mask -#define GPT_O_IMR 0x00000018 +#define GPT_O_IMR 0x00000018 // Raw Interrupt Status -#define GPT_O_RIS 0x0000001C +#define GPT_O_RIS 0x0000001C // Masked Interrupt Status -#define GPT_O_MIS 0x00000020 +#define GPT_O_MIS 0x00000020 // Interrupt Clear -#define GPT_O_ICLR 0x00000024 +#define GPT_O_ICLR 0x00000024 // Timer A Interval Load Register -#define GPT_O_TAILR 0x00000028 +#define GPT_O_TAILR 0x00000028 // Timer B Interval Load Register -#define GPT_O_TBILR 0x0000002C +#define GPT_O_TBILR 0x0000002C // Timer A Match Register -#define GPT_O_TAMATCHR 0x00000030 +#define GPT_O_TAMATCHR 0x00000030 // Timer B Match Register -#define GPT_O_TBMATCHR 0x00000034 +#define GPT_O_TBMATCHR 0x00000034 // Timer A Pre-scale -#define GPT_O_TAPR 0x00000038 +#define GPT_O_TAPR 0x00000038 // Timer B Pre-scale -#define GPT_O_TBPR 0x0000003C +#define GPT_O_TBPR 0x0000003C // Timer A Pre-scale Match -#define GPT_O_TAPMR 0x00000040 +#define GPT_O_TAPMR 0x00000040 // Timer B Pre-scale Match -#define GPT_O_TBPMR 0x00000044 +#define GPT_O_TBPMR 0x00000044 // Timer A Register -#define GPT_O_TAR 0x00000048 +#define GPT_O_TAR 0x00000048 // Timer B Register -#define GPT_O_TBR 0x0000004C +#define GPT_O_TBR 0x0000004C // Timer A Value -#define GPT_O_TAV 0x00000050 +#define GPT_O_TAV 0x00000050 // Timer B Value -#define GPT_O_TBV 0x00000054 +#define GPT_O_TBV 0x00000054 // Timer A Pre-scale Snap-shot -#define GPT_O_TAPS 0x0000005C +#define GPT_O_TAPS 0x0000005C // Timer B Pre-scale Snap-shot -#define GPT_O_TBPS 0x00000060 +#define GPT_O_TBPS 0x00000060 // Timer A Pre-scale Value -#define GPT_O_TAPV 0x00000064 +#define GPT_O_TAPV 0x00000064 // Timer B Pre-scale Value -#define GPT_O_TBPV 0x00000068 +#define GPT_O_TBPV 0x00000068 // DMA Event -#define GPT_O_DMAEV 0x0000006C +#define GPT_O_DMAEV 0x0000006C // Peripheral Version -#define GPT_O_VERSION 0x00000FB0 +#define GPT_O_VERSION 0x00000FB0 // Combined CCP Output -#define GPT_O_ANDCCP 0x00000FB4 +#define GPT_O_ANDCCP 0x00000FB4 //***************************************************************************** // @@ -144,11 +144,11 @@ // Also see TAMR.TAMR and // TBMR.TBMR. // 32BIT_TIMER 32-bit timer configuration -#define GPT_CFG_CFG_W 3 -#define GPT_CFG_CFG_M 0x00000007 -#define GPT_CFG_CFG_S 0 -#define GPT_CFG_CFG_16BIT_TIMER 0x00000004 -#define GPT_CFG_CFG_32BIT_TIMER 0x00000000 +#define GPT_CFG_CFG_W 3 +#define GPT_CFG_CFG_M 0x00000007 +#define GPT_CFG_CFG_S 0 +#define GPT_CFG_CFG_16BIT_TIMER 0x00000004 +#define GPT_CFG_CFG_32BIT_TIMER 0x00000000 //***************************************************************************** // @@ -171,17 +171,17 @@ // CLR_ON_TO Clear CCP output pin on Time-Out // TOG_ON_TO Toggle State on Time-Out // DIS_CMP Disable compare operations -#define GPT_TAMR_TCACT_W 3 -#define GPT_TAMR_TCACT_M 0x0000E000 -#define GPT_TAMR_TCACT_S 13 -#define GPT_TAMR_TCACT_CLRSET_ON_TO 0x0000E000 -#define GPT_TAMR_TCACT_SETCLR_ON_TO 0x0000C000 -#define GPT_TAMR_TCACT_CLRTOG_ON_TO 0x0000A000 -#define GPT_TAMR_TCACT_SETTOG_ON_TO 0x00008000 -#define GPT_TAMR_TCACT_SET_ON_TO 0x00006000 -#define GPT_TAMR_TCACT_CLR_ON_TO 0x00004000 -#define GPT_TAMR_TCACT_TOG_ON_TO 0x00002000 -#define GPT_TAMR_TCACT_DIS_CMP 0x00000000 +#define GPT_TAMR_TCACT_W 3 +#define GPT_TAMR_TCACT_M 0x0000E000 +#define GPT_TAMR_TCACT_S 13 +#define GPT_TAMR_TCACT_CLRSET_ON_TO 0x0000E000 +#define GPT_TAMR_TCACT_SETCLR_ON_TO 0x0000C000 +#define GPT_TAMR_TCACT_CLRTOG_ON_TO 0x0000A000 +#define GPT_TAMR_TCACT_SETTOG_ON_TO 0x00008000 +#define GPT_TAMR_TCACT_SET_ON_TO 0x00006000 +#define GPT_TAMR_TCACT_CLR_ON_TO 0x00004000 +#define GPT_TAMR_TCACT_TOG_ON_TO 0x00002000 +#define GPT_TAMR_TCACT_DIS_CMP 0x00000000 // Field: [12] TACINTD // @@ -189,12 +189,12 @@ // ENUMs: // DIS_TO_INTR Time-out interrupt are disabled // EN_TO_INTR Time-out interrupt function as normal -#define GPT_TAMR_TACINTD 0x00001000 -#define GPT_TAMR_TACINTD_BITN 12 -#define GPT_TAMR_TACINTD_M 0x00001000 -#define GPT_TAMR_TACINTD_S 12 -#define GPT_TAMR_TACINTD_DIS_TO_INTR 0x00001000 -#define GPT_TAMR_TACINTD_EN_TO_INTR 0x00000000 +#define GPT_TAMR_TACINTD 0x00001000 +#define GPT_TAMR_TACINTD_BITN 12 +#define GPT_TAMR_TACINTD_M 0x00001000 +#define GPT_TAMR_TACINTD_S 12 +#define GPT_TAMR_TACINTD_DIS_TO_INTR 0x00001000 +#define GPT_TAMR_TACINTD_EN_TO_INTR 0x00000000 // Field: [11] TAPLO // @@ -210,12 +210,12 @@ // ENUMs: // CCP_ON_TO CCP output pin is set to 1 on time-out // LEGACY Legacy operation -#define GPT_TAMR_TAPLO 0x00000800 -#define GPT_TAMR_TAPLO_BITN 11 -#define GPT_TAMR_TAPLO_M 0x00000800 -#define GPT_TAMR_TAPLO_S 11 -#define GPT_TAMR_TAPLO_CCP_ON_TO 0x00000800 -#define GPT_TAMR_TAPLO_LEGACY 0x00000000 +#define GPT_TAMR_TAPLO 0x00000800 +#define GPT_TAMR_TAPLO_BITN 11 +#define GPT_TAMR_TAPLO_M 0x00000800 +#define GPT_TAMR_TAPLO_S 11 +#define GPT_TAMR_TAPLO_CCP_ON_TO 0x00000800 +#define GPT_TAMR_TAPLO_LEGACY 0x00000000 // Field: [10] TAMRSU // @@ -232,12 +232,12 @@ // time-out. // CYCLEUPDATE Update TAMATCHR and TAPR, if used, on the next // cycle. -#define GPT_TAMR_TAMRSU 0x00000400 -#define GPT_TAMR_TAMRSU_BITN 10 -#define GPT_TAMR_TAMRSU_M 0x00000400 -#define GPT_TAMR_TAMRSU_S 10 -#define GPT_TAMR_TAMRSU_TOUPDATE 0x00000400 -#define GPT_TAMR_TAMRSU_CYCLEUPDATE 0x00000000 +#define GPT_TAMR_TAMRSU 0x00000400 +#define GPT_TAMR_TAMRSU_BITN 10 +#define GPT_TAMR_TAMRSU_M 0x00000400 +#define GPT_TAMR_TAMRSU_S 10 +#define GPT_TAMR_TAMRSU_TOUPDATE 0x00000400 +#define GPT_TAMR_TAMRSU_CYCLEUPDATE 0x00000000 // Field: [9] TAPWMIE // @@ -256,12 +256,12 @@ // EN Interrupt is enabled. This bit is only valid in // PWM mode. // DIS Interrupt is disabled. -#define GPT_TAMR_TAPWMIE 0x00000200 -#define GPT_TAMR_TAPWMIE_BITN 9 -#define GPT_TAMR_TAPWMIE_M 0x00000200 -#define GPT_TAMR_TAPWMIE_S 9 -#define GPT_TAMR_TAPWMIE_EN 0x00000200 -#define GPT_TAMR_TAPWMIE_DIS 0x00000000 +#define GPT_TAMR_TAPWMIE 0x00000200 +#define GPT_TAMR_TAPWMIE_BITN 9 +#define GPT_TAMR_TAPWMIE_M 0x00000200 +#define GPT_TAMR_TAPWMIE_S 9 +#define GPT_TAMR_TAPWMIE_EN 0x00000200 +#define GPT_TAMR_TAPWMIE_DIS 0x00000000 // Field: [8] TAILD // @@ -277,12 +277,12 @@ // pre-scaler is used, update the TAPS register // with the value in the TAPR register on the next // clock cycle. -#define GPT_TAMR_TAILD 0x00000100 -#define GPT_TAMR_TAILD_BITN 8 -#define GPT_TAMR_TAILD_M 0x00000100 -#define GPT_TAMR_TAILD_S 8 -#define GPT_TAMR_TAILD_TOUPDATE 0x00000100 -#define GPT_TAMR_TAILD_CYCLEUPDATE 0x00000000 +#define GPT_TAMR_TAILD 0x00000100 +#define GPT_TAMR_TAILD_BITN 8 +#define GPT_TAMR_TAILD_M 0x00000100 +#define GPT_TAMR_TAILD_S 8 +#define GPT_TAMR_TAILD_TOUPDATE 0x00000100 +#define GPT_TAMR_TAILD_CYCLEUPDATE 0x00000000 // Field: [7] TASNAPS // @@ -293,12 +293,12 @@ // at the time-out event into the GPT Timer A // (TAR) register. // DIS Snap-shot mode is disabled. -#define GPT_TAMR_TASNAPS 0x00000080 -#define GPT_TAMR_TASNAPS_BITN 7 -#define GPT_TAMR_TASNAPS_M 0x00000080 -#define GPT_TAMR_TASNAPS_S 7 -#define GPT_TAMR_TASNAPS_EN 0x00000080 -#define GPT_TAMR_TASNAPS_DIS 0x00000000 +#define GPT_TAMR_TASNAPS 0x00000080 +#define GPT_TAMR_TASNAPS_BITN 7 +#define GPT_TAMR_TASNAPS_M 0x00000080 +#define GPT_TAMR_TASNAPS_S 7 +#define GPT_TAMR_TASNAPS_EN 0x00000080 +#define GPT_TAMR_TASNAPS_DIS 0x00000000 // Field: [6] TAWOT // @@ -311,12 +311,12 @@ // Module 0, Timer A. This function is valid for // one-shot, periodic, and PWM modes // NOWAIT Timer A begins counting as soon as it is enabled. -#define GPT_TAMR_TAWOT 0x00000040 -#define GPT_TAMR_TAWOT_BITN 6 -#define GPT_TAMR_TAWOT_M 0x00000040 -#define GPT_TAMR_TAWOT_S 6 -#define GPT_TAMR_TAWOT_WAIT 0x00000040 -#define GPT_TAMR_TAWOT_NOWAIT 0x00000000 +#define GPT_TAMR_TAWOT 0x00000040 +#define GPT_TAMR_TAWOT_BITN 6 +#define GPT_TAMR_TAWOT_M 0x00000040 +#define GPT_TAMR_TAWOT_S 6 +#define GPT_TAMR_TAWOT_WAIT 0x00000040 +#define GPT_TAMR_TAWOT_NOWAIT 0x00000000 // Field: [5] TAMIE // @@ -328,12 +328,12 @@ // DIS The match interrupt is disabled for match events. // Additionally, output triggers on match events // are prevented. -#define GPT_TAMR_TAMIE 0x00000020 -#define GPT_TAMR_TAMIE_BITN 5 -#define GPT_TAMR_TAMIE_M 0x00000020 -#define GPT_TAMR_TAMIE_S 5 -#define GPT_TAMR_TAMIE_EN 0x00000020 -#define GPT_TAMR_TAMIE_DIS 0x00000000 +#define GPT_TAMR_TAMIE 0x00000020 +#define GPT_TAMR_TAMIE_BITN 5 +#define GPT_TAMR_TAMIE_M 0x00000020 +#define GPT_TAMR_TAMIE_S 5 +#define GPT_TAMR_TAMIE_EN 0x00000020 +#define GPT_TAMR_TAMIE_DIS 0x00000000 // Field: [4] TACDIR // @@ -342,12 +342,12 @@ // UP The timer counts up. When counting up, the timer // starts from a value of 0x0. // DOWN The timer counts down. -#define GPT_TAMR_TACDIR 0x00000010 -#define GPT_TAMR_TACDIR_BITN 4 -#define GPT_TAMR_TACDIR_M 0x00000010 -#define GPT_TAMR_TACDIR_S 4 -#define GPT_TAMR_TACDIR_UP 0x00000010 -#define GPT_TAMR_TACDIR_DOWN 0x00000000 +#define GPT_TAMR_TACDIR 0x00000010 +#define GPT_TAMR_TACDIR_BITN 4 +#define GPT_TAMR_TACDIR_M 0x00000010 +#define GPT_TAMR_TACDIR_S 4 +#define GPT_TAMR_TACDIR_UP 0x00000010 +#define GPT_TAMR_TACDIR_DOWN 0x00000000 // Field: [3] TAAMS // @@ -358,12 +358,12 @@ // ENUMs: // PWM PWM mode is enabled // CAP_COMP Capture/Compare mode is enabled. -#define GPT_TAMR_TAAMS 0x00000008 -#define GPT_TAMR_TAAMS_BITN 3 -#define GPT_TAMR_TAAMS_M 0x00000008 -#define GPT_TAMR_TAAMS_S 3 -#define GPT_TAMR_TAAMS_PWM 0x00000008 -#define GPT_TAMR_TAAMS_CAP_COMP 0x00000000 +#define GPT_TAMR_TAAMS 0x00000008 +#define GPT_TAMR_TAAMS_BITN 3 +#define GPT_TAMR_TAAMS_M 0x00000008 +#define GPT_TAMR_TAAMS_S 3 +#define GPT_TAMR_TAAMS_PWM 0x00000008 +#define GPT_TAMR_TAAMS_CAP_COMP 0x00000000 // Field: [2] TACM // @@ -371,12 +371,12 @@ // ENUMs: // EDGTIME Edge-Time mode // EDGCNT Edge-Count mode -#define GPT_TAMR_TACM 0x00000004 -#define GPT_TAMR_TACM_BITN 2 -#define GPT_TAMR_TACM_M 0x00000004 -#define GPT_TAMR_TACM_S 2 -#define GPT_TAMR_TACM_EDGTIME 0x00000004 -#define GPT_TAMR_TACM_EDGCNT 0x00000000 +#define GPT_TAMR_TACM 0x00000004 +#define GPT_TAMR_TACM_BITN 2 +#define GPT_TAMR_TACM_M 0x00000004 +#define GPT_TAMR_TACM_S 2 +#define GPT_TAMR_TACM_EDGTIME 0x00000004 +#define GPT_TAMR_TACM_EDGCNT 0x00000000 // Field: [1:0] TAMR // @@ -392,12 +392,12 @@ // CAPTURE Capture mode // PERIODIC Periodic Timer mode // ONE_SHOT One-Shot Timer mode -#define GPT_TAMR_TAMR_W 2 -#define GPT_TAMR_TAMR_M 0x00000003 -#define GPT_TAMR_TAMR_S 0 -#define GPT_TAMR_TAMR_CAPTURE 0x00000003 -#define GPT_TAMR_TAMR_PERIODIC 0x00000002 -#define GPT_TAMR_TAMR_ONE_SHOT 0x00000001 +#define GPT_TAMR_TAMR_W 2 +#define GPT_TAMR_TAMR_M 0x00000003 +#define GPT_TAMR_TAMR_S 0 +#define GPT_TAMR_TAMR_CAPTURE 0x00000003 +#define GPT_TAMR_TAMR_PERIODIC 0x00000002 +#define GPT_TAMR_TAMR_ONE_SHOT 0x00000001 //***************************************************************************** // @@ -420,17 +420,17 @@ // CLR_ON_TO Clear CCP output pin on Time-Out // TOG_ON_TO Toggle State on Time-Out // DIS_CMP Disable compare operations -#define GPT_TBMR_TCACT_W 3 -#define GPT_TBMR_TCACT_M 0x0000E000 -#define GPT_TBMR_TCACT_S 13 -#define GPT_TBMR_TCACT_CLRSET_ON_TO 0x0000E000 -#define GPT_TBMR_TCACT_SETCLR_ON_TO 0x0000C000 -#define GPT_TBMR_TCACT_CLRTOG_ON_TO 0x0000A000 -#define GPT_TBMR_TCACT_SETTOG_ON_TO 0x00008000 -#define GPT_TBMR_TCACT_SET_ON_TO 0x00006000 -#define GPT_TBMR_TCACT_CLR_ON_TO 0x00004000 -#define GPT_TBMR_TCACT_TOG_ON_TO 0x00002000 -#define GPT_TBMR_TCACT_DIS_CMP 0x00000000 +#define GPT_TBMR_TCACT_W 3 +#define GPT_TBMR_TCACT_M 0x0000E000 +#define GPT_TBMR_TCACT_S 13 +#define GPT_TBMR_TCACT_CLRSET_ON_TO 0x0000E000 +#define GPT_TBMR_TCACT_SETCLR_ON_TO 0x0000C000 +#define GPT_TBMR_TCACT_CLRTOG_ON_TO 0x0000A000 +#define GPT_TBMR_TCACT_SETTOG_ON_TO 0x00008000 +#define GPT_TBMR_TCACT_SET_ON_TO 0x00006000 +#define GPT_TBMR_TCACT_CLR_ON_TO 0x00004000 +#define GPT_TBMR_TCACT_TOG_ON_TO 0x00002000 +#define GPT_TBMR_TCACT_DIS_CMP 0x00000000 // Field: [12] TBCINTD // @@ -438,12 +438,12 @@ // ENUMs: // DIS_TO_INTR Mask Time-Out Interrupt // EN_TO_INTR Normal Time-Out Interrupt -#define GPT_TBMR_TBCINTD 0x00001000 -#define GPT_TBMR_TBCINTD_BITN 12 -#define GPT_TBMR_TBCINTD_M 0x00001000 -#define GPT_TBMR_TBCINTD_S 12 -#define GPT_TBMR_TBCINTD_DIS_TO_INTR 0x00001000 -#define GPT_TBMR_TBCINTD_EN_TO_INTR 0x00000000 +#define GPT_TBMR_TBCINTD 0x00001000 +#define GPT_TBMR_TBCINTD_BITN 12 +#define GPT_TBMR_TBCINTD_M 0x00001000 +#define GPT_TBMR_TBCINTD_S 12 +#define GPT_TBMR_TBCINTD_DIS_TO_INTR 0x00001000 +#define GPT_TBMR_TBCINTD_EN_TO_INTR 0x00000000 // Field: [11] TBPLO // @@ -459,12 +459,12 @@ // ENUMs: // CCP_ON_TO CCP output pin is set to 1 on time-out // LEGACY Legacy operation -#define GPT_TBMR_TBPLO 0x00000800 -#define GPT_TBMR_TBPLO_BITN 11 -#define GPT_TBMR_TBPLO_M 0x00000800 -#define GPT_TBMR_TBPLO_S 11 -#define GPT_TBMR_TBPLO_CCP_ON_TO 0x00000800 -#define GPT_TBMR_TBPLO_LEGACY 0x00000000 +#define GPT_TBMR_TBPLO 0x00000800 +#define GPT_TBMR_TBPLO_BITN 11 +#define GPT_TBMR_TBPLO_M 0x00000800 +#define GPT_TBMR_TBPLO_S 11 +#define GPT_TBMR_TBPLO_CCP_ON_TO 0x00000800 +#define GPT_TBMR_TBPLO_LEGACY 0x00000000 // Field: [10] TBMRSU // @@ -481,12 +481,12 @@ // time-out. // CYCLEUPDATE Update TBMATCHR and TBPR, if used, on the next // cycle. -#define GPT_TBMR_TBMRSU 0x00000400 -#define GPT_TBMR_TBMRSU_BITN 10 -#define GPT_TBMR_TBMRSU_M 0x00000400 -#define GPT_TBMR_TBMRSU_S 10 -#define GPT_TBMR_TBMRSU_TOUPDATE 0x00000400 -#define GPT_TBMR_TBMRSU_CYCLEUPDATE 0x00000000 +#define GPT_TBMR_TBMRSU 0x00000400 +#define GPT_TBMR_TBMRSU_BITN 10 +#define GPT_TBMR_TBMRSU_M 0x00000400 +#define GPT_TBMR_TBMRSU_S 10 +#define GPT_TBMR_TBMRSU_TOUPDATE 0x00000400 +#define GPT_TBMR_TBMRSU_CYCLEUPDATE 0x00000000 // Field: [9] TBPWMIE // @@ -505,12 +505,12 @@ // EN Interrupt is enabled. This bit is only valid in // PWM mode. // DIS Interrupt is disabled. -#define GPT_TBMR_TBPWMIE 0x00000200 -#define GPT_TBMR_TBPWMIE_BITN 9 -#define GPT_TBMR_TBPWMIE_M 0x00000200 -#define GPT_TBMR_TBPWMIE_S 9 -#define GPT_TBMR_TBPWMIE_EN 0x00000200 -#define GPT_TBMR_TBPWMIE_DIS 0x00000000 +#define GPT_TBMR_TBPWMIE 0x00000200 +#define GPT_TBMR_TBPWMIE_BITN 9 +#define GPT_TBMR_TBPWMIE_M 0x00000200 +#define GPT_TBMR_TBPWMIE_S 9 +#define GPT_TBMR_TBPWMIE_EN 0x00000200 +#define GPT_TBMR_TBPWMIE_DIS 0x00000000 // Field: [8] TBILD // @@ -526,12 +526,12 @@ // pre-scaler is used, update the TBPS register // with the value in the TBPR register on the next // clock cycle. -#define GPT_TBMR_TBILD 0x00000100 -#define GPT_TBMR_TBILD_BITN 8 -#define GPT_TBMR_TBILD_M 0x00000100 -#define GPT_TBMR_TBILD_S 8 -#define GPT_TBMR_TBILD_TOUPDATE 0x00000100 -#define GPT_TBMR_TBILD_CYCLEUPDATE 0x00000000 +#define GPT_TBMR_TBILD 0x00000100 +#define GPT_TBMR_TBILD_BITN 8 +#define GPT_TBMR_TBILD_M 0x00000100 +#define GPT_TBMR_TBILD_S 8 +#define GPT_TBMR_TBILD_TOUPDATE 0x00000100 +#define GPT_TBMR_TBILD_CYCLEUPDATE 0x00000000 // Field: [7] TBSNAPS // @@ -539,12 +539,12 @@ // ENUMs: // EN If Timer B is configured in the periodic mode // DIS Snap-shot mode is disabled. -#define GPT_TBMR_TBSNAPS 0x00000080 -#define GPT_TBMR_TBSNAPS_BITN 7 -#define GPT_TBMR_TBSNAPS_M 0x00000080 -#define GPT_TBMR_TBSNAPS_S 7 -#define GPT_TBMR_TBSNAPS_EN 0x00000080 -#define GPT_TBMR_TBSNAPS_DIS 0x00000000 +#define GPT_TBMR_TBSNAPS 0x00000080 +#define GPT_TBMR_TBSNAPS_BITN 7 +#define GPT_TBMR_TBSNAPS_M 0x00000080 +#define GPT_TBMR_TBSNAPS_S 7 +#define GPT_TBMR_TBSNAPS_EN 0x00000080 +#define GPT_TBMR_TBSNAPS_DIS 0x00000000 // Field: [6] TBWOT // @@ -556,12 +556,12 @@ // in the daisy chain. This function is valid for // one-shot, periodic, and PWM modes // NOWAIT Timer B begins counting as soon as it is enabled. -#define GPT_TBMR_TBWOT 0x00000040 -#define GPT_TBMR_TBWOT_BITN 6 -#define GPT_TBMR_TBWOT_M 0x00000040 -#define GPT_TBMR_TBWOT_S 6 -#define GPT_TBMR_TBWOT_WAIT 0x00000040 -#define GPT_TBMR_TBWOT_NOWAIT 0x00000000 +#define GPT_TBMR_TBWOT 0x00000040 +#define GPT_TBMR_TBWOT_BITN 6 +#define GPT_TBMR_TBWOT_M 0x00000040 +#define GPT_TBMR_TBWOT_S 6 +#define GPT_TBMR_TBWOT_WAIT 0x00000040 +#define GPT_TBMR_TBWOT_NOWAIT 0x00000000 // Field: [5] TBMIE // @@ -573,12 +573,12 @@ // DIS The match interrupt is disabled for match events. // Additionally, output triggers on match events // are prevented. -#define GPT_TBMR_TBMIE 0x00000020 -#define GPT_TBMR_TBMIE_BITN 5 -#define GPT_TBMR_TBMIE_M 0x00000020 -#define GPT_TBMR_TBMIE_S 5 -#define GPT_TBMR_TBMIE_EN 0x00000020 -#define GPT_TBMR_TBMIE_DIS 0x00000000 +#define GPT_TBMR_TBMIE 0x00000020 +#define GPT_TBMR_TBMIE_BITN 5 +#define GPT_TBMR_TBMIE_M 0x00000020 +#define GPT_TBMR_TBMIE_S 5 +#define GPT_TBMR_TBMIE_EN 0x00000020 +#define GPT_TBMR_TBMIE_DIS 0x00000000 // Field: [4] TBCDIR // @@ -587,12 +587,12 @@ // UP The timer counts up. When counting up, the timer // starts from a value of 0x0. // DOWN The timer counts down. -#define GPT_TBMR_TBCDIR 0x00000010 -#define GPT_TBMR_TBCDIR_BITN 4 -#define GPT_TBMR_TBCDIR_M 0x00000010 -#define GPT_TBMR_TBCDIR_S 4 -#define GPT_TBMR_TBCDIR_UP 0x00000010 -#define GPT_TBMR_TBCDIR_DOWN 0x00000000 +#define GPT_TBMR_TBCDIR 0x00000010 +#define GPT_TBMR_TBCDIR_BITN 4 +#define GPT_TBMR_TBCDIR_M 0x00000010 +#define GPT_TBMR_TBCDIR_S 4 +#define GPT_TBMR_TBCDIR_UP 0x00000010 +#define GPT_TBMR_TBCDIR_DOWN 0x00000000 // Field: [3] TBAMS // @@ -603,12 +603,12 @@ // ENUMs: // PWM PWM mode is enabled // CAP_COMP Capture/Compare mode is enabled. -#define GPT_TBMR_TBAMS 0x00000008 -#define GPT_TBMR_TBAMS_BITN 3 -#define GPT_TBMR_TBAMS_M 0x00000008 -#define GPT_TBMR_TBAMS_S 3 -#define GPT_TBMR_TBAMS_PWM 0x00000008 -#define GPT_TBMR_TBAMS_CAP_COMP 0x00000000 +#define GPT_TBMR_TBAMS 0x00000008 +#define GPT_TBMR_TBAMS_BITN 3 +#define GPT_TBMR_TBAMS_M 0x00000008 +#define GPT_TBMR_TBAMS_S 3 +#define GPT_TBMR_TBAMS_PWM 0x00000008 +#define GPT_TBMR_TBAMS_CAP_COMP 0x00000000 // Field: [2] TBCM // @@ -616,12 +616,12 @@ // ENUMs: // EDGTIME Edge-Time mode // EDGCNT Edge-Count mode -#define GPT_TBMR_TBCM 0x00000004 -#define GPT_TBMR_TBCM_BITN 2 -#define GPT_TBMR_TBCM_M 0x00000004 -#define GPT_TBMR_TBCM_S 2 -#define GPT_TBMR_TBCM_EDGTIME 0x00000004 -#define GPT_TBMR_TBCM_EDGCNT 0x00000000 +#define GPT_TBMR_TBCM 0x00000004 +#define GPT_TBMR_TBCM_BITN 2 +#define GPT_TBMR_TBCM_M 0x00000004 +#define GPT_TBMR_TBCM_S 2 +#define GPT_TBMR_TBCM_EDGTIME 0x00000004 +#define GPT_TBMR_TBCM_EDGCNT 0x00000000 // Field: [1:0] TBMR // @@ -637,12 +637,12 @@ // CAPTURE Capture mode // PERIODIC Periodic Timer mode // ONE_SHOT One-Shot Timer mode -#define GPT_TBMR_TBMR_W 2 -#define GPT_TBMR_TBMR_M 0x00000003 -#define GPT_TBMR_TBMR_S 0 -#define GPT_TBMR_TBMR_CAPTURE 0x00000003 -#define GPT_TBMR_TBMR_PERIODIC 0x00000002 -#define GPT_TBMR_TBMR_ONE_SHOT 0x00000001 +#define GPT_TBMR_TBMR_W 2 +#define GPT_TBMR_TBMR_M 0x00000003 +#define GPT_TBMR_TBMR_S 0 +#define GPT_TBMR_TBMR_CAPTURE 0x00000003 +#define GPT_TBMR_TBMR_PERIODIC 0x00000002 +#define GPT_TBMR_TBMR_ONE_SHOT 0x00000001 //***************************************************************************** // @@ -658,12 +658,12 @@ // ENUMs: // INVERTED Inverted // NORMAL Not inverted -#define GPT_CTL_TBPWML 0x00004000 -#define GPT_CTL_TBPWML_BITN 14 -#define GPT_CTL_TBPWML_M 0x00004000 -#define GPT_CTL_TBPWML_S 14 -#define GPT_CTL_TBPWML_INVERTED 0x00004000 -#define GPT_CTL_TBPWML_NORMAL 0x00000000 +#define GPT_CTL_TBPWML 0x00004000 +#define GPT_CTL_TBPWML_BITN 14 +#define GPT_CTL_TBPWML_M 0x00004000 +#define GPT_CTL_TBPWML_S 14 +#define GPT_CTL_TBPWML_INVERTED 0x00004000 +#define GPT_CTL_TBPWML_NORMAL 0x00000000 // Field: [11:10] TBEVENT // @@ -684,12 +684,12 @@ // BOTH Both edges // NEG Negative edge // POS Positive edge -#define GPT_CTL_TBEVENT_W 2 -#define GPT_CTL_TBEVENT_M 0x00000C00 -#define GPT_CTL_TBEVENT_S 10 -#define GPT_CTL_TBEVENT_BOTH 0x00000C00 -#define GPT_CTL_TBEVENT_NEG 0x00000400 -#define GPT_CTL_TBEVENT_POS 0x00000000 +#define GPT_CTL_TBEVENT_W 2 +#define GPT_CTL_TBEVENT_M 0x00000C00 +#define GPT_CTL_TBEVENT_S 10 +#define GPT_CTL_TBEVENT_BOTH 0x00000C00 +#define GPT_CTL_TBEVENT_NEG 0x00000400 +#define GPT_CTL_TBEVENT_POS 0x00000000 // Field: [9] TBSTALL // @@ -699,12 +699,12 @@ // halted by the debugger. // DIS Timer B continues counting while the processor is // halted by the debugger. -#define GPT_CTL_TBSTALL 0x00000200 -#define GPT_CTL_TBSTALL_BITN 9 -#define GPT_CTL_TBSTALL_M 0x00000200 -#define GPT_CTL_TBSTALL_S 9 -#define GPT_CTL_TBSTALL_EN 0x00000200 -#define GPT_CTL_TBSTALL_DIS 0x00000000 +#define GPT_CTL_TBSTALL 0x00000200 +#define GPT_CTL_TBSTALL_BITN 9 +#define GPT_CTL_TBSTALL_M 0x00000200 +#define GPT_CTL_TBSTALL_S 9 +#define GPT_CTL_TBSTALL_EN 0x00000200 +#define GPT_CTL_TBSTALL_DIS 0x00000000 // Field: [8] TBEN // @@ -713,12 +713,12 @@ // EN Timer B is enabled and begins counting or the // capture logic is enabled based on CFG register. // DIS Timer B is disabled. -#define GPT_CTL_TBEN 0x00000100 -#define GPT_CTL_TBEN_BITN 8 -#define GPT_CTL_TBEN_M 0x00000100 -#define GPT_CTL_TBEN_S 8 -#define GPT_CTL_TBEN_EN 0x00000100 -#define GPT_CTL_TBEN_DIS 0x00000000 +#define GPT_CTL_TBEN 0x00000100 +#define GPT_CTL_TBEN_BITN 8 +#define GPT_CTL_TBEN_M 0x00000100 +#define GPT_CTL_TBEN_S 8 +#define GPT_CTL_TBEN_EN 0x00000100 +#define GPT_CTL_TBEN_DIS 0x00000000 // Field: [6] TAPWML // @@ -726,12 +726,12 @@ // ENUMs: // INVERTED Inverted // NORMAL Not inverted -#define GPT_CTL_TAPWML 0x00000040 -#define GPT_CTL_TAPWML_BITN 6 -#define GPT_CTL_TAPWML_M 0x00000040 -#define GPT_CTL_TAPWML_S 6 -#define GPT_CTL_TAPWML_INVERTED 0x00000040 -#define GPT_CTL_TAPWML_NORMAL 0x00000000 +#define GPT_CTL_TAPWML 0x00000040 +#define GPT_CTL_TAPWML_BITN 6 +#define GPT_CTL_TAPWML_M 0x00000040 +#define GPT_CTL_TAPWML_S 6 +#define GPT_CTL_TAPWML_INVERTED 0x00000040 +#define GPT_CTL_TAPWML_NORMAL 0x00000000 // Field: [3:2] TAEVENT // @@ -752,12 +752,12 @@ // BOTH Both edges // NEG Negative edge // POS Positive edge -#define GPT_CTL_TAEVENT_W 2 -#define GPT_CTL_TAEVENT_M 0x0000000C -#define GPT_CTL_TAEVENT_S 2 -#define GPT_CTL_TAEVENT_BOTH 0x0000000C -#define GPT_CTL_TAEVENT_NEG 0x00000004 -#define GPT_CTL_TAEVENT_POS 0x00000000 +#define GPT_CTL_TAEVENT_W 2 +#define GPT_CTL_TAEVENT_M 0x0000000C +#define GPT_CTL_TAEVENT_S 2 +#define GPT_CTL_TAEVENT_BOTH 0x0000000C +#define GPT_CTL_TAEVENT_NEG 0x00000004 +#define GPT_CTL_TAEVENT_POS 0x00000000 // Field: [1] TASTALL // @@ -767,12 +767,12 @@ // halted by the debugger. // DIS Timer A continues counting while the processor is // halted by the debugger. -#define GPT_CTL_TASTALL 0x00000002 -#define GPT_CTL_TASTALL_BITN 1 -#define GPT_CTL_TASTALL_M 0x00000002 -#define GPT_CTL_TASTALL_S 1 -#define GPT_CTL_TASTALL_EN 0x00000002 -#define GPT_CTL_TASTALL_DIS 0x00000000 +#define GPT_CTL_TASTALL 0x00000002 +#define GPT_CTL_TASTALL_BITN 1 +#define GPT_CTL_TASTALL_M 0x00000002 +#define GPT_CTL_TASTALL_S 1 +#define GPT_CTL_TASTALL_EN 0x00000002 +#define GPT_CTL_TASTALL_DIS 0x00000000 // Field: [0] TAEN // @@ -782,12 +782,12 @@ // capture logic is enabled based on the CFG // register. // DIS Timer A is disabled. -#define GPT_CTL_TAEN 0x00000001 -#define GPT_CTL_TAEN_BITN 0 -#define GPT_CTL_TAEN_M 0x00000001 -#define GPT_CTL_TAEN_S 0 -#define GPT_CTL_TAEN_EN 0x00000001 -#define GPT_CTL_TAEN_DIS 0x00000000 +#define GPT_CTL_TAEN 0x00000001 +#define GPT_CTL_TAEN_BITN 0 +#define GPT_CTL_TAEN_M 0x00000001 +#define GPT_CTL_TAEN_S 0 +#define GPT_CTL_TAEN_EN 0x00000001 +#define GPT_CTL_TAEN_DIS 0x00000000 //***************************************************************************** // @@ -803,13 +803,13 @@ // TIMERB A timeout event for Timer B of GPT3 is triggered // TIMERA A timeout event for Timer A of GPT3 is triggered // NOSYNC No Sync. GPT3 is not affected. -#define GPT_SYNC_SYNC3_W 2 -#define GPT_SYNC_SYNC3_M 0x000000C0 -#define GPT_SYNC_SYNC3_S 6 -#define GPT_SYNC_SYNC3_BOTH 0x000000C0 -#define GPT_SYNC_SYNC3_TIMERB 0x00000080 -#define GPT_SYNC_SYNC3_TIMERA 0x00000040 -#define GPT_SYNC_SYNC3_NOSYNC 0x00000000 +#define GPT_SYNC_SYNC3_W 2 +#define GPT_SYNC_SYNC3_M 0x000000C0 +#define GPT_SYNC_SYNC3_S 6 +#define GPT_SYNC_SYNC3_BOTH 0x000000C0 +#define GPT_SYNC_SYNC3_TIMERB 0x00000080 +#define GPT_SYNC_SYNC3_TIMERA 0x00000040 +#define GPT_SYNC_SYNC3_NOSYNC 0x00000000 // Field: [5:4] SYNC2 // @@ -820,13 +820,13 @@ // TIMERB A timeout event for Timer B of GPT2 is triggered // TIMERA A timeout event for Timer A of GPT2 is triggered // NOSYNC No Sync. GPT2 is not affected. -#define GPT_SYNC_SYNC2_W 2 -#define GPT_SYNC_SYNC2_M 0x00000030 -#define GPT_SYNC_SYNC2_S 4 -#define GPT_SYNC_SYNC2_BOTH 0x00000030 -#define GPT_SYNC_SYNC2_TIMERB 0x00000020 -#define GPT_SYNC_SYNC2_TIMERA 0x00000010 -#define GPT_SYNC_SYNC2_NOSYNC 0x00000000 +#define GPT_SYNC_SYNC2_W 2 +#define GPT_SYNC_SYNC2_M 0x00000030 +#define GPT_SYNC_SYNC2_S 4 +#define GPT_SYNC_SYNC2_BOTH 0x00000030 +#define GPT_SYNC_SYNC2_TIMERB 0x00000020 +#define GPT_SYNC_SYNC2_TIMERA 0x00000010 +#define GPT_SYNC_SYNC2_NOSYNC 0x00000000 // Field: [3:2] SYNC1 // @@ -837,13 +837,13 @@ // TIMERB A timeout event for Timer B of GPT1 is triggered // TIMERA A timeout event for Timer A of GPT1 is triggered // NOSYNC No Sync. GPT1 is not affected. -#define GPT_SYNC_SYNC1_W 2 -#define GPT_SYNC_SYNC1_M 0x0000000C -#define GPT_SYNC_SYNC1_S 2 -#define GPT_SYNC_SYNC1_BOTH 0x0000000C -#define GPT_SYNC_SYNC1_TIMERB 0x00000008 -#define GPT_SYNC_SYNC1_TIMERA 0x00000004 -#define GPT_SYNC_SYNC1_NOSYNC 0x00000000 +#define GPT_SYNC_SYNC1_W 2 +#define GPT_SYNC_SYNC1_M 0x0000000C +#define GPT_SYNC_SYNC1_S 2 +#define GPT_SYNC_SYNC1_BOTH 0x0000000C +#define GPT_SYNC_SYNC1_TIMERB 0x00000008 +#define GPT_SYNC_SYNC1_TIMERA 0x00000004 +#define GPT_SYNC_SYNC1_NOSYNC 0x00000000 // Field: [1:0] SYNC0 // @@ -854,13 +854,13 @@ // TIMERB A timeout event for Timer B of GPT0 is triggered // TIMERA A timeout event for Timer A of GPT0 is triggered // NOSYNC No Sync. GPT0 is not affected. -#define GPT_SYNC_SYNC0_W 2 -#define GPT_SYNC_SYNC0_M 0x00000003 -#define GPT_SYNC_SYNC0_S 0 -#define GPT_SYNC_SYNC0_BOTH 0x00000003 -#define GPT_SYNC_SYNC0_TIMERB 0x00000002 -#define GPT_SYNC_SYNC0_TIMERA 0x00000001 -#define GPT_SYNC_SYNC0_NOSYNC 0x00000000 +#define GPT_SYNC_SYNC0_W 2 +#define GPT_SYNC_SYNC0_M 0x00000003 +#define GPT_SYNC_SYNC0_S 0 +#define GPT_SYNC_SYNC0_BOTH 0x00000003 +#define GPT_SYNC_SYNC0_TIMERB 0x00000002 +#define GPT_SYNC_SYNC0_TIMERA 0x00000001 +#define GPT_SYNC_SYNC0_NOSYNC 0x00000000 //***************************************************************************** // @@ -874,12 +874,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_DMABIM 0x00002000 -#define GPT_IMR_DMABIM_BITN 13 -#define GPT_IMR_DMABIM_M 0x00002000 -#define GPT_IMR_DMABIM_S 13 -#define GPT_IMR_DMABIM_EN 0x00002000 -#define GPT_IMR_DMABIM_DIS 0x00000000 +#define GPT_IMR_DMABIM 0x00002000 +#define GPT_IMR_DMABIM_BITN 13 +#define GPT_IMR_DMABIM_M 0x00002000 +#define GPT_IMR_DMABIM_S 13 +#define GPT_IMR_DMABIM_EN 0x00002000 +#define GPT_IMR_DMABIM_DIS 0x00000000 // Field: [11] TBMIM // @@ -887,12 +887,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_TBMIM 0x00000800 -#define GPT_IMR_TBMIM_BITN 11 -#define GPT_IMR_TBMIM_M 0x00000800 -#define GPT_IMR_TBMIM_S 11 -#define GPT_IMR_TBMIM_EN 0x00000800 -#define GPT_IMR_TBMIM_DIS 0x00000000 +#define GPT_IMR_TBMIM 0x00000800 +#define GPT_IMR_TBMIM_BITN 11 +#define GPT_IMR_TBMIM_M 0x00000800 +#define GPT_IMR_TBMIM_S 11 +#define GPT_IMR_TBMIM_EN 0x00000800 +#define GPT_IMR_TBMIM_DIS 0x00000000 // Field: [10] CBEIM // @@ -900,12 +900,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_CBEIM 0x00000400 -#define GPT_IMR_CBEIM_BITN 10 -#define GPT_IMR_CBEIM_M 0x00000400 -#define GPT_IMR_CBEIM_S 10 -#define GPT_IMR_CBEIM_EN 0x00000400 -#define GPT_IMR_CBEIM_DIS 0x00000000 +#define GPT_IMR_CBEIM 0x00000400 +#define GPT_IMR_CBEIM_BITN 10 +#define GPT_IMR_CBEIM_M 0x00000400 +#define GPT_IMR_CBEIM_S 10 +#define GPT_IMR_CBEIM_EN 0x00000400 +#define GPT_IMR_CBEIM_DIS 0x00000000 // Field: [9] CBMIM // @@ -913,12 +913,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_CBMIM 0x00000200 -#define GPT_IMR_CBMIM_BITN 9 -#define GPT_IMR_CBMIM_M 0x00000200 -#define GPT_IMR_CBMIM_S 9 -#define GPT_IMR_CBMIM_EN 0x00000200 -#define GPT_IMR_CBMIM_DIS 0x00000000 +#define GPT_IMR_CBMIM 0x00000200 +#define GPT_IMR_CBMIM_BITN 9 +#define GPT_IMR_CBMIM_M 0x00000200 +#define GPT_IMR_CBMIM_S 9 +#define GPT_IMR_CBMIM_EN 0x00000200 +#define GPT_IMR_CBMIM_DIS 0x00000000 // Field: [8] TBTOIM // @@ -927,12 +927,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_TBTOIM 0x00000100 -#define GPT_IMR_TBTOIM_BITN 8 -#define GPT_IMR_TBTOIM_M 0x00000100 -#define GPT_IMR_TBTOIM_S 8 -#define GPT_IMR_TBTOIM_EN 0x00000100 -#define GPT_IMR_TBTOIM_DIS 0x00000000 +#define GPT_IMR_TBTOIM 0x00000100 +#define GPT_IMR_TBTOIM_BITN 8 +#define GPT_IMR_TBTOIM_M 0x00000100 +#define GPT_IMR_TBTOIM_S 8 +#define GPT_IMR_TBTOIM_EN 0x00000100 +#define GPT_IMR_TBTOIM_DIS 0x00000000 // Field: [5] DMAAIM // @@ -941,12 +941,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_DMAAIM 0x00000020 -#define GPT_IMR_DMAAIM_BITN 5 -#define GPT_IMR_DMAAIM_M 0x00000020 -#define GPT_IMR_DMAAIM_S 5 -#define GPT_IMR_DMAAIM_EN 0x00000020 -#define GPT_IMR_DMAAIM_DIS 0x00000000 +#define GPT_IMR_DMAAIM 0x00000020 +#define GPT_IMR_DMAAIM_BITN 5 +#define GPT_IMR_DMAAIM_M 0x00000020 +#define GPT_IMR_DMAAIM_S 5 +#define GPT_IMR_DMAAIM_EN 0x00000020 +#define GPT_IMR_DMAAIM_DIS 0x00000000 // Field: [4] TAMIM // @@ -954,12 +954,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_TAMIM 0x00000010 -#define GPT_IMR_TAMIM_BITN 4 -#define GPT_IMR_TAMIM_M 0x00000010 -#define GPT_IMR_TAMIM_S 4 -#define GPT_IMR_TAMIM_EN 0x00000010 -#define GPT_IMR_TAMIM_DIS 0x00000000 +#define GPT_IMR_TAMIM 0x00000010 +#define GPT_IMR_TAMIM_BITN 4 +#define GPT_IMR_TAMIM_M 0x00000010 +#define GPT_IMR_TAMIM_S 4 +#define GPT_IMR_TAMIM_EN 0x00000010 +#define GPT_IMR_TAMIM_DIS 0x00000000 // Field: [2] CAEIM // @@ -967,12 +967,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_CAEIM 0x00000004 -#define GPT_IMR_CAEIM_BITN 2 -#define GPT_IMR_CAEIM_M 0x00000004 -#define GPT_IMR_CAEIM_S 2 -#define GPT_IMR_CAEIM_EN 0x00000004 -#define GPT_IMR_CAEIM_DIS 0x00000000 +#define GPT_IMR_CAEIM 0x00000004 +#define GPT_IMR_CAEIM_BITN 2 +#define GPT_IMR_CAEIM_M 0x00000004 +#define GPT_IMR_CAEIM_S 2 +#define GPT_IMR_CAEIM_EN 0x00000004 +#define GPT_IMR_CAEIM_DIS 0x00000000 // Field: [1] CAMIM // @@ -980,12 +980,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_CAMIM 0x00000002 -#define GPT_IMR_CAMIM_BITN 1 -#define GPT_IMR_CAMIM_M 0x00000002 -#define GPT_IMR_CAMIM_S 1 -#define GPT_IMR_CAMIM_EN 0x00000002 -#define GPT_IMR_CAMIM_DIS 0x00000000 +#define GPT_IMR_CAMIM 0x00000002 +#define GPT_IMR_CAMIM_BITN 1 +#define GPT_IMR_CAMIM_M 0x00000002 +#define GPT_IMR_CAMIM_S 1 +#define GPT_IMR_CAMIM_EN 0x00000002 +#define GPT_IMR_CAMIM_DIS 0x00000000 // Field: [0] TATOIM // @@ -994,12 +994,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define GPT_IMR_TATOIM 0x00000001 -#define GPT_IMR_TATOIM_BITN 0 -#define GPT_IMR_TATOIM_M 0x00000001 -#define GPT_IMR_TATOIM_S 0 -#define GPT_IMR_TATOIM_EN 0x00000001 -#define GPT_IMR_TATOIM_DIS 0x00000000 +#define GPT_IMR_TATOIM 0x00000001 +#define GPT_IMR_TATOIM_BITN 0 +#define GPT_IMR_TATOIM_M 0x00000001 +#define GPT_IMR_TATOIM_S 0 +#define GPT_IMR_TATOIM_EN 0x00000001 +#define GPT_IMR_TATOIM_DIS 0x00000000 //***************************************************************************** // @@ -1012,10 +1012,10 @@ // // 0: Transfer has not completed // 1: Transfer has completed -#define GPT_RIS_DMABRIS 0x00002000 -#define GPT_RIS_DMABRIS_BITN 13 -#define GPT_RIS_DMABRIS_M 0x00002000 -#define GPT_RIS_DMABRIS_S 13 +#define GPT_RIS_DMABRIS 0x00002000 +#define GPT_RIS_DMABRIS_BITN 13 +#define GPT_RIS_DMABRIS_M 0x00002000 +#define GPT_RIS_DMABRIS_S 13 // Field: [11] TBMRIS // @@ -1026,10 +1026,10 @@ // // TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR // have been reached when configured in one-shot or periodic mode. -#define GPT_RIS_TBMRIS 0x00000800 -#define GPT_RIS_TBMRIS_BITN 11 -#define GPT_RIS_TBMRIS_M 0x00000800 -#define GPT_RIS_TBMRIS_S 11 +#define GPT_RIS_TBMRIS 0x00000800 +#define GPT_RIS_TBMRIS_BITN 11 +#define GPT_RIS_TBMRIS_M 0x00000800 +#define GPT_RIS_TBMRIS_S 11 // Field: [10] CBERIS // @@ -1040,10 +1040,10 @@ // // This interrupt asserts when the subtimer is configured in Input Edge-Time // mode -#define GPT_RIS_CBERIS 0x00000400 -#define GPT_RIS_CBERIS_BITN 10 -#define GPT_RIS_CBERIS_M 0x00000400 -#define GPT_RIS_CBERIS_S 10 +#define GPT_RIS_CBERIS 0x00000400 +#define GPT_RIS_CBERIS_BITN 10 +#define GPT_RIS_CBERIS_M 0x00000400 +#define GPT_RIS_CBERIS_S 10 // Field: [9] CBMRIS // @@ -1056,10 +1056,10 @@ // when configured in Input Edge-Time mode. // // This bit is cleared by writing a 1 to the ICLR.CBMCINT bit. -#define GPT_RIS_CBMRIS 0x00000200 -#define GPT_RIS_CBMRIS_BITN 9 -#define GPT_RIS_CBMRIS_M 0x00000200 -#define GPT_RIS_CBMRIS_S 9 +#define GPT_RIS_CBMRIS 0x00000200 +#define GPT_RIS_CBMRIS_BITN 9 +#define GPT_RIS_CBMRIS_M 0x00000200 +#define GPT_RIS_CBMRIS_S 9 // Field: [8] TBTORIS // @@ -1071,10 +1071,10 @@ // This interrupt is asserted when a one-shot or periodic mode timer reaches // its count limit. The count limit is 0 or the value loaded into TBILR, // depending on the count direction. -#define GPT_RIS_TBTORIS 0x00000100 -#define GPT_RIS_TBTORIS_BITN 8 -#define GPT_RIS_TBTORIS_M 0x00000100 -#define GPT_RIS_TBTORIS_S 8 +#define GPT_RIS_TBTORIS 0x00000100 +#define GPT_RIS_TBTORIS_BITN 8 +#define GPT_RIS_TBTORIS_M 0x00000100 +#define GPT_RIS_TBTORIS_S 8 // Field: [5] DMAARIS // @@ -1082,10 +1082,10 @@ // // 0: Transfer has not completed // 1: Transfer has completed -#define GPT_RIS_DMAARIS 0x00000020 -#define GPT_RIS_DMAARIS_BITN 5 -#define GPT_RIS_DMAARIS_M 0x00000020 -#define GPT_RIS_DMAARIS_S 5 +#define GPT_RIS_DMAARIS 0x00000020 +#define GPT_RIS_DMAARIS_BITN 5 +#define GPT_RIS_DMAARIS_M 0x00000020 +#define GPT_RIS_DMAARIS_S 5 // Field: [4] TAMRIS // @@ -1096,10 +1096,10 @@ // // TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR // have been reached when configured in one-shot or periodic mode. -#define GPT_RIS_TAMRIS 0x00000010 -#define GPT_RIS_TAMRIS_BITN 4 -#define GPT_RIS_TAMRIS_M 0x00000010 -#define GPT_RIS_TAMRIS_S 4 +#define GPT_RIS_TAMRIS 0x00000010 +#define GPT_RIS_TAMRIS_BITN 4 +#define GPT_RIS_TAMRIS_M 0x00000010 +#define GPT_RIS_TAMRIS_S 4 // Field: [2] CAERIS // @@ -1110,10 +1110,10 @@ // // This interrupt asserts when the subtimer is configured in Input Edge-Time // mode -#define GPT_RIS_CAERIS 0x00000004 -#define GPT_RIS_CAERIS_BITN 2 -#define GPT_RIS_CAERIS_M 0x00000004 -#define GPT_RIS_CAERIS_S 2 +#define GPT_RIS_CAERIS 0x00000004 +#define GPT_RIS_CAERIS_BITN 2 +#define GPT_RIS_CAERIS_M 0x00000004 +#define GPT_RIS_CAERIS_S 2 // Field: [1] CAMRIS // @@ -1126,10 +1126,10 @@ // when configured in Input Edge-Time mode. // // This bit is cleared by writing a 1 to the ICLR.CAMCINT bit. -#define GPT_RIS_CAMRIS 0x00000002 -#define GPT_RIS_CAMRIS_BITN 1 -#define GPT_RIS_CAMRIS_M 0x00000002 -#define GPT_RIS_CAMRIS_S 1 +#define GPT_RIS_CAMRIS 0x00000002 +#define GPT_RIS_CAMRIS_BITN 1 +#define GPT_RIS_CAMRIS_M 0x00000002 +#define GPT_RIS_CAMRIS_S 1 // Field: [0] TATORIS // @@ -1141,10 +1141,10 @@ // This interrupt is asserted when a one-shot or periodic mode timer reaches // its count limit. The count limit is 0 or the value loaded into TAILR, // depending on the count direction. -#define GPT_RIS_TATORIS 0x00000001 -#define GPT_RIS_TATORIS_BITN 0 -#define GPT_RIS_TATORIS_M 0x00000001 -#define GPT_RIS_TATORIS_S 0 +#define GPT_RIS_TATORIS 0x00000001 +#define GPT_RIS_TATORIS_BITN 0 +#define GPT_RIS_TATORIS_M 0x00000001 +#define GPT_RIS_TATORIS_S 0 //***************************************************************************** // @@ -1155,91 +1155,91 @@ // // 0: No interrupt or interrupt not enabled // 1: RIS.DMABRIS = 1 && IMR.DMABIM = 1 -#define GPT_MIS_DMABMIS 0x00002000 -#define GPT_MIS_DMABMIS_BITN 13 -#define GPT_MIS_DMABMIS_M 0x00002000 -#define GPT_MIS_DMABMIS_S 13 +#define GPT_MIS_DMABMIS 0x00002000 +#define GPT_MIS_DMABMIS_BITN 13 +#define GPT_MIS_DMABMIS_M 0x00002000 +#define GPT_MIS_DMABMIS_S 13 // Field: [11] TBMMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.TBMRIS = 1 && IMR.TBMIM = 1 -#define GPT_MIS_TBMMIS 0x00000800 -#define GPT_MIS_TBMMIS_BITN 11 -#define GPT_MIS_TBMMIS_M 0x00000800 -#define GPT_MIS_TBMMIS_S 11 +#define GPT_MIS_TBMMIS 0x00000800 +#define GPT_MIS_TBMMIS_BITN 11 +#define GPT_MIS_TBMMIS_M 0x00000800 +#define GPT_MIS_TBMMIS_S 11 // Field: [10] CBEMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.CBERIS = 1 && IMR.CBEIM = 1 -#define GPT_MIS_CBEMIS 0x00000400 -#define GPT_MIS_CBEMIS_BITN 10 -#define GPT_MIS_CBEMIS_M 0x00000400 -#define GPT_MIS_CBEMIS_S 10 +#define GPT_MIS_CBEMIS 0x00000400 +#define GPT_MIS_CBEMIS_BITN 10 +#define GPT_MIS_CBEMIS_M 0x00000400 +#define GPT_MIS_CBEMIS_S 10 // Field: [9] CBMMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.CBMRIS = 1 && IMR.CBMIM = 1 -#define GPT_MIS_CBMMIS 0x00000200 -#define GPT_MIS_CBMMIS_BITN 9 -#define GPT_MIS_CBMMIS_M 0x00000200 -#define GPT_MIS_CBMMIS_S 9 +#define GPT_MIS_CBMMIS 0x00000200 +#define GPT_MIS_CBMMIS_BITN 9 +#define GPT_MIS_CBMMIS_M 0x00000200 +#define GPT_MIS_CBMMIS_S 9 // Field: [8] TBTOMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1 -#define GPT_MIS_TBTOMIS 0x00000100 -#define GPT_MIS_TBTOMIS_BITN 8 -#define GPT_MIS_TBTOMIS_M 0x00000100 -#define GPT_MIS_TBTOMIS_S 8 +#define GPT_MIS_TBTOMIS 0x00000100 +#define GPT_MIS_TBTOMIS_BITN 8 +#define GPT_MIS_TBTOMIS_M 0x00000100 +#define GPT_MIS_TBTOMIS_S 8 // Field: [5] DMAAMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1 -#define GPT_MIS_DMAAMIS 0x00000020 -#define GPT_MIS_DMAAMIS_BITN 5 -#define GPT_MIS_DMAAMIS_M 0x00000020 -#define GPT_MIS_DMAAMIS_S 5 +#define GPT_MIS_DMAAMIS 0x00000020 +#define GPT_MIS_DMAAMIS_BITN 5 +#define GPT_MIS_DMAAMIS_M 0x00000020 +#define GPT_MIS_DMAAMIS_S 5 // Field: [4] TAMMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.TAMRIS = 1 && IMR.TAMIM = 1 -#define GPT_MIS_TAMMIS 0x00000010 -#define GPT_MIS_TAMMIS_BITN 4 -#define GPT_MIS_TAMMIS_M 0x00000010 -#define GPT_MIS_TAMMIS_S 4 +#define GPT_MIS_TAMMIS 0x00000010 +#define GPT_MIS_TAMMIS_BITN 4 +#define GPT_MIS_TAMMIS_M 0x00000010 +#define GPT_MIS_TAMMIS_S 4 // Field: [2] CAEMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.CAERIS = 1 && IMR.CAEIM = 1 -#define GPT_MIS_CAEMIS 0x00000004 -#define GPT_MIS_CAEMIS_BITN 2 -#define GPT_MIS_CAEMIS_M 0x00000004 -#define GPT_MIS_CAEMIS_S 2 +#define GPT_MIS_CAEMIS 0x00000004 +#define GPT_MIS_CAEMIS_BITN 2 +#define GPT_MIS_CAEMIS_M 0x00000004 +#define GPT_MIS_CAEMIS_S 2 // Field: [1] CAMMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.CAMRIS = 1 && IMR.CAMIM = 1 -#define GPT_MIS_CAMMIS 0x00000002 -#define GPT_MIS_CAMMIS_BITN 1 -#define GPT_MIS_CAMMIS_M 0x00000002 -#define GPT_MIS_CAMMIS_S 1 +#define GPT_MIS_CAMMIS 0x00000002 +#define GPT_MIS_CAMMIS_BITN 1 +#define GPT_MIS_CAMMIS_M 0x00000002 +#define GPT_MIS_CAMMIS_S 1 // Field: [0] TATOMIS // // 0: No interrupt or interrupt not enabled // 1: RIS.TATORIS = 1 && IMR.TATOIM = 1 -#define GPT_MIS_TATOMIS 0x00000001 -#define GPT_MIS_TATOMIS_BITN 0 -#define GPT_MIS_TATOMIS_M 0x00000001 -#define GPT_MIS_TATOMIS_S 0 +#define GPT_MIS_TATOMIS 0x00000001 +#define GPT_MIS_TATOMIS_BITN 0 +#define GPT_MIS_TATOMIS_M 0x00000001 +#define GPT_MIS_TATOMIS_S 0 //***************************************************************************** // @@ -1250,91 +1250,91 @@ // // 0: Do nothing. // 1: Clear RIS.DMABRIS and MIS.DMABMIS -#define GPT_ICLR_DMABINT 0x00002000 -#define GPT_ICLR_DMABINT_BITN 13 -#define GPT_ICLR_DMABINT_M 0x00002000 -#define GPT_ICLR_DMABINT_S 13 +#define GPT_ICLR_DMABINT 0x00002000 +#define GPT_ICLR_DMABINT_BITN 13 +#define GPT_ICLR_DMABINT_M 0x00002000 +#define GPT_ICLR_DMABINT_S 13 // Field: [11] TBMCINT // // 0: Do nothing. // 1: Clear RIS.TBMRIS and MIS.TBMMIS -#define GPT_ICLR_TBMCINT 0x00000800 -#define GPT_ICLR_TBMCINT_BITN 11 -#define GPT_ICLR_TBMCINT_M 0x00000800 -#define GPT_ICLR_TBMCINT_S 11 +#define GPT_ICLR_TBMCINT 0x00000800 +#define GPT_ICLR_TBMCINT_BITN 11 +#define GPT_ICLR_TBMCINT_M 0x00000800 +#define GPT_ICLR_TBMCINT_S 11 // Field: [10] CBECINT // // 0: Do nothing. // 1: Clear RIS.CBERIS and MIS.CBEMIS -#define GPT_ICLR_CBECINT 0x00000400 -#define GPT_ICLR_CBECINT_BITN 10 -#define GPT_ICLR_CBECINT_M 0x00000400 -#define GPT_ICLR_CBECINT_S 10 +#define GPT_ICLR_CBECINT 0x00000400 +#define GPT_ICLR_CBECINT_BITN 10 +#define GPT_ICLR_CBECINT_M 0x00000400 +#define GPT_ICLR_CBECINT_S 10 // Field: [9] CBMCINT // // 0: Do nothing. // 1: Clear RIS.CBMRIS and MIS.CBMMIS -#define GPT_ICLR_CBMCINT 0x00000200 -#define GPT_ICLR_CBMCINT_BITN 9 -#define GPT_ICLR_CBMCINT_M 0x00000200 -#define GPT_ICLR_CBMCINT_S 9 +#define GPT_ICLR_CBMCINT 0x00000200 +#define GPT_ICLR_CBMCINT_BITN 9 +#define GPT_ICLR_CBMCINT_M 0x00000200 +#define GPT_ICLR_CBMCINT_S 9 // Field: [8] TBTOCINT // // 0: Do nothing. // 1: Clear RIS.TBTORIS and MIS.TBTOMIS -#define GPT_ICLR_TBTOCINT 0x00000100 -#define GPT_ICLR_TBTOCINT_BITN 8 -#define GPT_ICLR_TBTOCINT_M 0x00000100 -#define GPT_ICLR_TBTOCINT_S 8 +#define GPT_ICLR_TBTOCINT 0x00000100 +#define GPT_ICLR_TBTOCINT_BITN 8 +#define GPT_ICLR_TBTOCINT_M 0x00000100 +#define GPT_ICLR_TBTOCINT_S 8 // Field: [5] DMAAINT // // 0: Do nothing. // 1: Clear RIS.DMAARIS and MIS.DMAAMIS -#define GPT_ICLR_DMAAINT 0x00000020 -#define GPT_ICLR_DMAAINT_BITN 5 -#define GPT_ICLR_DMAAINT_M 0x00000020 -#define GPT_ICLR_DMAAINT_S 5 +#define GPT_ICLR_DMAAINT 0x00000020 +#define GPT_ICLR_DMAAINT_BITN 5 +#define GPT_ICLR_DMAAINT_M 0x00000020 +#define GPT_ICLR_DMAAINT_S 5 // Field: [4] TAMCINT // // 0: Do nothing. // 1: Clear RIS.TAMRIS and MIS.TAMMIS -#define GPT_ICLR_TAMCINT 0x00000010 -#define GPT_ICLR_TAMCINT_BITN 4 -#define GPT_ICLR_TAMCINT_M 0x00000010 -#define GPT_ICLR_TAMCINT_S 4 +#define GPT_ICLR_TAMCINT 0x00000010 +#define GPT_ICLR_TAMCINT_BITN 4 +#define GPT_ICLR_TAMCINT_M 0x00000010 +#define GPT_ICLR_TAMCINT_S 4 // Field: [2] CAECINT // // 0: Do nothing. // 1: Clear RIS.CAERIS and MIS.CAEMIS -#define GPT_ICLR_CAECINT 0x00000004 -#define GPT_ICLR_CAECINT_BITN 2 -#define GPT_ICLR_CAECINT_M 0x00000004 -#define GPT_ICLR_CAECINT_S 2 +#define GPT_ICLR_CAECINT 0x00000004 +#define GPT_ICLR_CAECINT_BITN 2 +#define GPT_ICLR_CAECINT_M 0x00000004 +#define GPT_ICLR_CAECINT_S 2 // Field: [1] CAMCINT // // 0: Do nothing. // 1: Clear RIS.CAMRIS and MIS.CAMMIS -#define GPT_ICLR_CAMCINT 0x00000002 -#define GPT_ICLR_CAMCINT_BITN 1 -#define GPT_ICLR_CAMCINT_M 0x00000002 -#define GPT_ICLR_CAMCINT_S 1 +#define GPT_ICLR_CAMCINT 0x00000002 +#define GPT_ICLR_CAMCINT_BITN 1 +#define GPT_ICLR_CAMCINT_M 0x00000002 +#define GPT_ICLR_CAMCINT_S 1 // Field: [0] TATOCINT // // 0: Do nothing. // 1: Clear RIS.TATORIS and MIS.TATOMIS -#define GPT_ICLR_TATOCINT 0x00000001 -#define GPT_ICLR_TATOCINT_BITN 0 -#define GPT_ICLR_TATOCINT_M 0x00000001 -#define GPT_ICLR_TATOCINT_S 0 +#define GPT_ICLR_TATOCINT 0x00000001 +#define GPT_ICLR_TATOCINT_BITN 0 +#define GPT_ICLR_TATOCINT_M 0x00000001 +#define GPT_ICLR_TATOCINT_S 0 //***************************************************************************** // @@ -1347,9 +1347,9 @@ // // Writing this field loads the counter for Timer A. A read returns the current // value of TAILR. -#define GPT_TAILR_TAILR_W 32 -#define GPT_TAILR_TAILR_M 0xFFFFFFFF -#define GPT_TAILR_TAILR_S 0 +#define GPT_TAILR_TAILR_W 32 +#define GPT_TAILR_TAILR_M 0xFFFFFFFF +#define GPT_TAILR_TAILR_S 0 //***************************************************************************** // @@ -1362,9 +1362,9 @@ // // Writing this field loads the counter for Timer B. A read returns the current // value of TBILR. -#define GPT_TBILR_TBILR_W 32 -#define GPT_TBILR_TBILR_M 0xFFFFFFFF -#define GPT_TBILR_TBILR_S 0 +#define GPT_TBILR_TBILR_W 32 +#define GPT_TBILR_TBILR_M 0xFFFFFFFF +#define GPT_TBILR_TBILR_S 0 //***************************************************************************** // @@ -1374,9 +1374,9 @@ // Field: [31:0] TAMATCHR // // GPT Timer A Match Register -#define GPT_TAMATCHR_TAMATCHR_W 32 -#define GPT_TAMATCHR_TAMATCHR_M 0xFFFFFFFF -#define GPT_TAMATCHR_TAMATCHR_S 0 +#define GPT_TAMATCHR_TAMATCHR_W 32 +#define GPT_TAMATCHR_TAMATCHR_M 0xFFFFFFFF +#define GPT_TAMATCHR_TAMATCHR_S 0 //***************************************************************************** // @@ -1386,9 +1386,9 @@ // Field: [15:0] TBMATCHR // // GPT Timer B Match Register -#define GPT_TBMATCHR_TBMATCHR_W 16 -#define GPT_TBMATCHR_TBMATCHR_M 0x0000FFFF -#define GPT_TBMATCHR_TBMATCHR_S 0 +#define GPT_TBMATCHR_TBMATCHR_W 16 +#define GPT_TBMATCHR_TBMATCHR_M 0x0000FFFF +#define GPT_TBMATCHR_TBMATCHR_S 0 //***************************************************************************** // @@ -1406,9 +1406,9 @@ // 2: Prescaler ratio = 3 // ... // 255: Prescaler ratio = 256 -#define GPT_TAPR_TAPSR_W 8 -#define GPT_TAPR_TAPSR_M 0x000000FF -#define GPT_TAPR_TAPSR_S 0 +#define GPT_TAPR_TAPSR_W 8 +#define GPT_TAPR_TAPSR_M 0x000000FF +#define GPT_TAPR_TAPSR_S 0 //***************************************************************************** // @@ -1426,9 +1426,9 @@ // 2: Prescaler ratio = 3 // ... // 255: Prescaler ratio = 256 -#define GPT_TBPR_TBPSR_W 8 -#define GPT_TBPR_TBPSR_M 0x000000FF -#define GPT_TBPR_TBPSR_S 0 +#define GPT_TBPR_TBPSR_W 8 +#define GPT_TBPR_TBPSR_M 0x000000FF +#define GPT_TBPR_TBPSR_S 0 //***************************************************************************** // @@ -1438,9 +1438,9 @@ // Field: [7:0] TAPSMR // // GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16. -#define GPT_TAPMR_TAPSMR_W 8 -#define GPT_TAPMR_TAPSMR_M 0x000000FF -#define GPT_TAPMR_TAPSMR_S 0 +#define GPT_TAPMR_TAPSMR_W 8 +#define GPT_TAPMR_TAPSMR_M 0x000000FF +#define GPT_TAPMR_TAPSMR_S 0 //***************************************************************************** // @@ -1451,9 +1451,9 @@ // // GPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits // 23 to 16. -#define GPT_TBPMR_TBPSMR_W 8 -#define GPT_TBPMR_TBPSMR_M 0x000000FF -#define GPT_TBPMR_TBPSMR_S 0 +#define GPT_TBPMR_TBPSMR_W 8 +#define GPT_TBPMR_TBPSMR_M 0x000000FF +#define GPT_TBPMR_TBPSMR_S 0 //***************************************************************************** // @@ -1473,9 +1473,9 @@ // In the Input Edge Count Mode, this register contains the number of edges // that have occurred. In the Input Edge Time mode, this register contains the // time at which the last edge event took place. -#define GPT_TAR_TAR_W 32 -#define GPT_TAR_TAR_M 0xFFFFFFFF -#define GPT_TAR_TAR_S 0 +#define GPT_TAR_TAR_W 32 +#define GPT_TAR_TAR_M 0xFFFFFFFF +#define GPT_TAR_TAR_S 0 //***************************************************************************** // @@ -1495,9 +1495,9 @@ // In the Input Edge Count Mode, this register contains the number of edges // that have occurred. In the Input Edge Time mode, this register contains the // time at which the last edge event took place. -#define GPT_TBR_TBR_W 32 -#define GPT_TBR_TBR_M 0xFFFFFFFF -#define GPT_TBR_TBR_S 0 +#define GPT_TBR_TBR_W 32 +#define GPT_TBR_TBR_M 0xFFFFFFFF +#define GPT_TBR_TBR_S 0 //***************************************************************************** // @@ -1513,9 +1513,9 @@ // Note: In 16-bit mode, only the lower 16-bits of this // register can be written with a new value. Writes to the prescaler bits have // no effect -#define GPT_TAV_TAV_W 32 -#define GPT_TAV_TAV_M 0xFFFFFFFF -#define GPT_TAV_TAV_S 0 +#define GPT_TAV_TAV_W 32 +#define GPT_TAV_TAV_M 0xFFFFFFFF +#define GPT_TAV_TAV_S 0 //***************************************************************************** // @@ -1531,9 +1531,9 @@ // Note: In 16-bit mode, only the lower 16-bits of this // register can be written with a new value. Writes to the prescaler bits have // no effect -#define GPT_TBV_TBV_W 32 -#define GPT_TBV_TBV_M 0xFFFFFFFF -#define GPT_TBV_TBV_S 0 +#define GPT_TBV_TBV_W 32 +#define GPT_TBV_TBV_M 0xFFFFFFFF +#define GPT_TBV_TBV_S 0 //***************************************************************************** // @@ -1543,9 +1543,9 @@ // Field: [7:0] PSS // // GPT Timer A Pre-scaler -#define GPT_TAPS_PSS_W 8 -#define GPT_TAPS_PSS_M 0x000000FF -#define GPT_TAPS_PSS_S 0 +#define GPT_TAPS_PSS_W 8 +#define GPT_TAPS_PSS_M 0x000000FF +#define GPT_TAPS_PSS_S 0 //***************************************************************************** // @@ -1555,9 +1555,9 @@ // Field: [7:0] PSS // // GPT Timer B Pre-scaler -#define GPT_TBPS_PSS_W 8 -#define GPT_TBPS_PSS_M 0x000000FF -#define GPT_TBPS_PSS_S 0 +#define GPT_TBPS_PSS_W 8 +#define GPT_TBPS_PSS_M 0x000000FF +#define GPT_TBPS_PSS_S 0 //***************************************************************************** // @@ -1567,9 +1567,9 @@ // Field: [7:0] PSV // // GPT Timer A Pre-scaler Value -#define GPT_TAPV_PSV_W 8 -#define GPT_TAPV_PSV_M 0x000000FF -#define GPT_TAPV_PSV_S 0 +#define GPT_TAPV_PSV_W 8 +#define GPT_TAPV_PSV_M 0x000000FF +#define GPT_TAPV_PSV_S 0 //***************************************************************************** // @@ -1579,9 +1579,9 @@ // Field: [7:0] PSV // // GPT Timer B Pre-scaler Value -#define GPT_TBPV_PSV_W 8 -#define GPT_TBPV_PSV_M 0x000000FF -#define GPT_TBPV_PSV_S 0 +#define GPT_TBPV_PSV_W 8 +#define GPT_TBPV_PSV_M 0x000000FF +#define GPT_TBPV_PSV_S 0 //***************************************************************************** // @@ -1591,66 +1591,66 @@ // Field: [11] TBMDMAEN // // GPT Timer B Match DMA Trigger Enable -#define GPT_DMAEV_TBMDMAEN 0x00000800 -#define GPT_DMAEV_TBMDMAEN_BITN 11 -#define GPT_DMAEV_TBMDMAEN_M 0x00000800 -#define GPT_DMAEV_TBMDMAEN_S 11 +#define GPT_DMAEV_TBMDMAEN 0x00000800 +#define GPT_DMAEV_TBMDMAEN_BITN 11 +#define GPT_DMAEV_TBMDMAEN_M 0x00000800 +#define GPT_DMAEV_TBMDMAEN_S 11 // Field: [10] CBEDMAEN // // GPT Timer B Capture Event DMA Trigger Enable -#define GPT_DMAEV_CBEDMAEN 0x00000400 -#define GPT_DMAEV_CBEDMAEN_BITN 10 -#define GPT_DMAEV_CBEDMAEN_M 0x00000400 -#define GPT_DMAEV_CBEDMAEN_S 10 +#define GPT_DMAEV_CBEDMAEN 0x00000400 +#define GPT_DMAEV_CBEDMAEN_BITN 10 +#define GPT_DMAEV_CBEDMAEN_M 0x00000400 +#define GPT_DMAEV_CBEDMAEN_S 10 // Field: [9] CBMDMAEN // // GPT Timer B Capture Match DMA Trigger Enable -#define GPT_DMAEV_CBMDMAEN 0x00000200 -#define GPT_DMAEV_CBMDMAEN_BITN 9 -#define GPT_DMAEV_CBMDMAEN_M 0x00000200 -#define GPT_DMAEV_CBMDMAEN_S 9 +#define GPT_DMAEV_CBMDMAEN 0x00000200 +#define GPT_DMAEV_CBMDMAEN_BITN 9 +#define GPT_DMAEV_CBMDMAEN_M 0x00000200 +#define GPT_DMAEV_CBMDMAEN_S 9 // Field: [8] TBTODMAEN // // GPT Timer B Time-Out DMA Trigger Enable -#define GPT_DMAEV_TBTODMAEN 0x00000100 -#define GPT_DMAEV_TBTODMAEN_BITN 8 -#define GPT_DMAEV_TBTODMAEN_M 0x00000100 -#define GPT_DMAEV_TBTODMAEN_S 8 +#define GPT_DMAEV_TBTODMAEN 0x00000100 +#define GPT_DMAEV_TBTODMAEN_BITN 8 +#define GPT_DMAEV_TBTODMAEN_M 0x00000100 +#define GPT_DMAEV_TBTODMAEN_S 8 // Field: [4] TAMDMAEN // // GPT Timer A Match DMA Trigger Enable -#define GPT_DMAEV_TAMDMAEN 0x00000010 -#define GPT_DMAEV_TAMDMAEN_BITN 4 -#define GPT_DMAEV_TAMDMAEN_M 0x00000010 -#define GPT_DMAEV_TAMDMAEN_S 4 +#define GPT_DMAEV_TAMDMAEN 0x00000010 +#define GPT_DMAEV_TAMDMAEN_BITN 4 +#define GPT_DMAEV_TAMDMAEN_M 0x00000010 +#define GPT_DMAEV_TAMDMAEN_S 4 // Field: [2] CAEDMAEN // // GPT Timer A Capture Event DMA Trigger Enable -#define GPT_DMAEV_CAEDMAEN 0x00000004 -#define GPT_DMAEV_CAEDMAEN_BITN 2 -#define GPT_DMAEV_CAEDMAEN_M 0x00000004 -#define GPT_DMAEV_CAEDMAEN_S 2 +#define GPT_DMAEV_CAEDMAEN 0x00000004 +#define GPT_DMAEV_CAEDMAEN_BITN 2 +#define GPT_DMAEV_CAEDMAEN_M 0x00000004 +#define GPT_DMAEV_CAEDMAEN_S 2 // Field: [1] CAMDMAEN // // GPT Timer A Capture Match DMA Trigger Enable -#define GPT_DMAEV_CAMDMAEN 0x00000002 -#define GPT_DMAEV_CAMDMAEN_BITN 1 -#define GPT_DMAEV_CAMDMAEN_M 0x00000002 -#define GPT_DMAEV_CAMDMAEN_S 1 +#define GPT_DMAEV_CAMDMAEN 0x00000002 +#define GPT_DMAEV_CAMDMAEN_BITN 1 +#define GPT_DMAEV_CAMDMAEN_M 0x00000002 +#define GPT_DMAEV_CAMDMAEN_S 1 // Field: [0] TATODMAEN // // GPT Timer A Time-Out DMA Trigger Enable -#define GPT_DMAEV_TATODMAEN 0x00000001 -#define GPT_DMAEV_TATODMAEN_BITN 0 -#define GPT_DMAEV_TATODMAEN_M 0x00000001 -#define GPT_DMAEV_TATODMAEN_S 0 +#define GPT_DMAEV_TATODMAEN 0x00000001 +#define GPT_DMAEV_TATODMAEN_BITN 0 +#define GPT_DMAEV_TATODMAEN_M 0x00000001 +#define GPT_DMAEV_TATODMAEN_S 0 //***************************************************************************** // @@ -1660,9 +1660,9 @@ // Field: [31:0] VERSION // // Timer Revision. -#define GPT_VERSION_VERSION_W 32 -#define GPT_VERSION_VERSION_M 0xFFFFFFFF -#define GPT_VERSION_VERSION_S 0 +#define GPT_VERSION_VERSION_W 32 +#define GPT_VERSION_VERSION_M 0xFFFFFFFF +#define GPT_VERSION_VERSION_S 0 //***************************************************************************** // @@ -1677,10 +1677,9 @@ // signals of the respective timers. // 1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM // signals and Timer B PWM ouput is Timer B PWM signal only. -#define GPT_ANDCCP_CCP_AND_EN 0x00000001 -#define GPT_ANDCCP_CCP_AND_EN_BITN 0 -#define GPT_ANDCCP_CCP_AND_EN_M 0x00000001 -#define GPT_ANDCCP_CCP_AND_EN_S 0 - +#define GPT_ANDCCP_CCP_AND_EN 0x00000001 +#define GPT_ANDCCP_CCP_AND_EN_BITN 0 +#define GPT_ANDCCP_CCP_AND_EN_M 0x00000001 +#define GPT_ANDCCP_CCP_AND_EN_S 0 #endif // __GPT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_i2c.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_i2c.h index 9d0d30e..d37b80d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_i2c.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_i2c.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_i2c_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_i2c_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_I2C_H__ #define __HW_I2C_H__ @@ -44,58 +44,58 @@ // //***************************************************************************** // Slave Own Address -#define I2C_O_SOAR 0x00000000 +#define I2C_O_SOAR 0x00000000 // Slave Status -#define I2C_O_SSTAT 0x00000004 +#define I2C_O_SSTAT 0x00000004 // Slave Control -#define I2C_O_SCTL 0x00000004 +#define I2C_O_SCTL 0x00000004 // Slave Data -#define I2C_O_SDR 0x00000008 +#define I2C_O_SDR 0x00000008 // Slave Interrupt Mask -#define I2C_O_SIMR 0x0000000C +#define I2C_O_SIMR 0x0000000C // Slave Raw Interrupt Status -#define I2C_O_SRIS 0x00000010 +#define I2C_O_SRIS 0x00000010 // Slave Masked Interrupt Status -#define I2C_O_SMIS 0x00000014 +#define I2C_O_SMIS 0x00000014 // Slave Interrupt Clear -#define I2C_O_SICR 0x00000018 +#define I2C_O_SICR 0x00000018 // Master Salve Address -#define I2C_O_MSA 0x00000800 +#define I2C_O_MSA 0x00000800 // Master Status -#define I2C_O_MSTAT 0x00000804 +#define I2C_O_MSTAT 0x00000804 // Master Control -#define I2C_O_MCTRL 0x00000804 +#define I2C_O_MCTRL 0x00000804 // Master Data -#define I2C_O_MDR 0x00000808 +#define I2C_O_MDR 0x00000808 // I2C Master Timer Period -#define I2C_O_MTPR 0x0000080C +#define I2C_O_MTPR 0x0000080C // Master Interrupt Mask -#define I2C_O_MIMR 0x00000810 +#define I2C_O_MIMR 0x00000810 // Master Raw Interrupt Status -#define I2C_O_MRIS 0x00000814 +#define I2C_O_MRIS 0x00000814 // Master Masked Interrupt Status -#define I2C_O_MMIS 0x00000818 +#define I2C_O_MMIS 0x00000818 // Master Interrupt Clear -#define I2C_O_MICR 0x0000081C +#define I2C_O_MICR 0x0000081C // Master Configuration -#define I2C_O_MCR 0x00000820 +#define I2C_O_MCR 0x00000820 //***************************************************************************** // @@ -106,9 +106,9 @@ // // I2C slave own address // This field specifies bits a6 through a0 of the slave address. -#define I2C_SOAR_OAR_W 7 -#define I2C_SOAR_OAR_M 0x0000007F -#define I2C_SOAR_OAR_S 0 +#define I2C_SOAR_OAR_W 7 +#define I2C_SOAR_OAR_M 0x0000007F +#define I2C_SOAR_OAR_S 0 //***************************************************************************** // @@ -125,10 +125,10 @@ // This bit is only valid when the RREQ bit is set and is automatically cleared // when data has been read from the SDR register. // Note: This bit is not used for slave transmit operations. -#define I2C_SSTAT_FBR 0x00000004 -#define I2C_SSTAT_FBR_BITN 2 -#define I2C_SSTAT_FBR_M 0x00000004 -#define I2C_SSTAT_FBR_S 2 +#define I2C_SSTAT_FBR 0x00000004 +#define I2C_SSTAT_FBR_BITN 2 +#define I2C_SSTAT_FBR_M 0x00000004 +#define I2C_SSTAT_FBR_S 2 // Field: [1] TREQ // @@ -138,10 +138,10 @@ // 1: The I2C controller has been addressed as a slave transmitter and is using // clock stretching to delay the master until data has been written to the SDR // register. -#define I2C_SSTAT_TREQ 0x00000002 -#define I2C_SSTAT_TREQ_BITN 1 -#define I2C_SSTAT_TREQ_M 0x00000002 -#define I2C_SSTAT_TREQ_S 1 +#define I2C_SSTAT_TREQ 0x00000002 +#define I2C_SSTAT_TREQ_BITN 1 +#define I2C_SSTAT_TREQ_M 0x00000002 +#define I2C_SSTAT_TREQ_S 1 // Field: [0] RREQ // @@ -151,10 +151,10 @@ // 1: The I2C controller has outstanding receive data from the I2C master and // is using clock stretching to delay the master until data has been read from // the SDR register. -#define I2C_SSTAT_RREQ 0x00000001 -#define I2C_SSTAT_RREQ_BITN 0 -#define I2C_SSTAT_RREQ_M 0x00000001 -#define I2C_SSTAT_RREQ_S 0 +#define I2C_SSTAT_RREQ 0x00000001 +#define I2C_SSTAT_RREQ_BITN 0 +#define I2C_SSTAT_RREQ_M 0x00000001 +#define I2C_SSTAT_RREQ_S 0 //***************************************************************************** // @@ -167,10 +167,10 @@ // // 0: Disables the I2C slave operation // 1: Enables the I2C slave operation -#define I2C_SCTL_DA 0x00000001 -#define I2C_SCTL_DA_BITN 0 -#define I2C_SCTL_DA_M 0x00000001 -#define I2C_SCTL_DA_S 0 +#define I2C_SCTL_DA 0x00000001 +#define I2C_SCTL_DA_BITN 0 +#define I2C_SCTL_DA_M 0x00000001 +#define I2C_SCTL_DA_S 0 //***************************************************************************** // @@ -185,9 +185,9 @@ // read, this register returns the last data received. // Data is stored until next update, either by a system write for transmit or // by an external master for receive. -#define I2C_SDR_DATA_W 8 -#define I2C_SDR_DATA_M 0x000000FF -#define I2C_SDR_DATA_S 0 +#define I2C_SDR_DATA_W 8 +#define I2C_SDR_DATA_M 0x000000FF +#define I2C_SDR_DATA_S 0 //***************************************************************************** // @@ -205,12 +205,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define I2C_SIMR_STOPIM 0x00000004 -#define I2C_SIMR_STOPIM_BITN 2 -#define I2C_SIMR_STOPIM_M 0x00000004 -#define I2C_SIMR_STOPIM_S 2 -#define I2C_SIMR_STOPIM_EN 0x00000004 -#define I2C_SIMR_STOPIM_DIS 0x00000000 +#define I2C_SIMR_STOPIM 0x00000004 +#define I2C_SIMR_STOPIM_BITN 2 +#define I2C_SIMR_STOPIM_M 0x00000004 +#define I2C_SIMR_STOPIM_S 2 +#define I2C_SIMR_STOPIM_EN 0x00000004 +#define I2C_SIMR_STOPIM_DIS 0x00000000 // Field: [1] STARTIM // @@ -223,12 +223,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define I2C_SIMR_STARTIM 0x00000002 -#define I2C_SIMR_STARTIM_BITN 1 -#define I2C_SIMR_STARTIM_M 0x00000002 -#define I2C_SIMR_STARTIM_S 1 -#define I2C_SIMR_STARTIM_EN 0x00000002 -#define I2C_SIMR_STARTIM_DIS 0x00000000 +#define I2C_SIMR_STARTIM 0x00000002 +#define I2C_SIMR_STARTIM_BITN 1 +#define I2C_SIMR_STARTIM_M 0x00000002 +#define I2C_SIMR_STARTIM_S 1 +#define I2C_SIMR_STARTIM_EN 0x00000002 +#define I2C_SIMR_STARTIM_DIS 0x00000000 // Field: [0] DATAIM // @@ -238,10 +238,10 @@ // controller. // 1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt // controller. -#define I2C_SIMR_DATAIM 0x00000001 -#define I2C_SIMR_DATAIM_BITN 0 -#define I2C_SIMR_DATAIM_M 0x00000001 -#define I2C_SIMR_DATAIM_S 0 +#define I2C_SIMR_DATAIM 0x00000001 +#define I2C_SIMR_DATAIM_BITN 0 +#define I2C_SIMR_DATAIM_M 0x00000001 +#define I2C_SIMR_DATAIM_S 0 //***************************************************************************** // @@ -256,10 +256,10 @@ // 1: A Stop condition interrupt is pending. // // This bit is cleared by writing a 1 to SICR.STOPIC. -#define I2C_SRIS_STOPRIS 0x00000004 -#define I2C_SRIS_STOPRIS_BITN 2 -#define I2C_SRIS_STOPRIS_M 0x00000004 -#define I2C_SRIS_STOPRIS_S 2 +#define I2C_SRIS_STOPRIS 0x00000004 +#define I2C_SRIS_STOPRIS_BITN 2 +#define I2C_SRIS_STOPRIS_M 0x00000004 +#define I2C_SRIS_STOPRIS_S 2 // Field: [1] STARTRIS // @@ -269,10 +269,10 @@ // 1: A Start condition interrupt is pending. // // This bit is cleared by writing a 1 to SICR.STARTIC. -#define I2C_SRIS_STARTRIS 0x00000002 -#define I2C_SRIS_STARTRIS_BITN 1 -#define I2C_SRIS_STARTRIS_M 0x00000002 -#define I2C_SRIS_STARTRIS_S 1 +#define I2C_SRIS_STARTRIS 0x00000002 +#define I2C_SRIS_STARTRIS_BITN 1 +#define I2C_SRIS_STARTRIS_M 0x00000002 +#define I2C_SRIS_STARTRIS_S 1 // Field: [0] DATARIS // @@ -282,10 +282,10 @@ // 1: A data received or data requested interrupt is pending. // // This bit is cleared by writing a 1 to the SICR.DATAIC. -#define I2C_SRIS_DATARIS 0x00000001 -#define I2C_SRIS_DATARIS_BITN 0 -#define I2C_SRIS_DATARIS_M 0x00000001 -#define I2C_SRIS_DATARIS_S 0 +#define I2C_SRIS_DATARIS 0x00000001 +#define I2C_SRIS_DATARIS_BITN 0 +#define I2C_SRIS_DATARIS_M 0x00000001 +#define I2C_SRIS_DATARIS_S 0 //***************************************************************************** // @@ -300,10 +300,10 @@ // 1: An unmasked Stop condition interrupt is pending. // // This bit is cleared by writing a 1 to the SICR.STOPIC. -#define I2C_SMIS_STOPMIS 0x00000004 -#define I2C_SMIS_STOPMIS_BITN 2 -#define I2C_SMIS_STOPMIS_M 0x00000004 -#define I2C_SMIS_STOPMIS_S 2 +#define I2C_SMIS_STOPMIS 0x00000004 +#define I2C_SMIS_STOPMIS_BITN 2 +#define I2C_SMIS_STOPMIS_M 0x00000004 +#define I2C_SMIS_STOPMIS_S 2 // Field: [1] STARTMIS // @@ -313,10 +313,10 @@ // 1: An unmasked Start condition interrupt is pending. // // This bit is cleared by writing a 1 to the SICR.STARTIC. -#define I2C_SMIS_STARTMIS 0x00000002 -#define I2C_SMIS_STARTMIS_BITN 1 -#define I2C_SMIS_STARTMIS_M 0x00000002 -#define I2C_SMIS_STARTMIS_S 1 +#define I2C_SMIS_STARTMIS 0x00000002 +#define I2C_SMIS_STARTMIS_BITN 1 +#define I2C_SMIS_STARTMIS_M 0x00000002 +#define I2C_SMIS_STARTMIS_S 1 // Field: [0] DATAMIS // @@ -326,10 +326,10 @@ // 1: An unmasked data received or data requested interrupt is pending. // // This bit is cleared by writing a 1 to the SICR.DATAIC. -#define I2C_SMIS_DATAMIS 0x00000001 -#define I2C_SMIS_DATAMIS_BITN 0 -#define I2C_SMIS_DATAMIS_M 0x00000001 -#define I2C_SMIS_DATAMIS_S 0 +#define I2C_SMIS_DATAMIS 0x00000001 +#define I2C_SMIS_DATAMIS_BITN 0 +#define I2C_SMIS_DATAMIS_M 0x00000001 +#define I2C_SMIS_DATAMIS_S 0 //***************************************************************************** // @@ -341,30 +341,30 @@ // Stop condition interrupt clear // // Writing 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS. -#define I2C_SICR_STOPIC 0x00000004 -#define I2C_SICR_STOPIC_BITN 2 -#define I2C_SICR_STOPIC_M 0x00000004 -#define I2C_SICR_STOPIC_S 2 +#define I2C_SICR_STOPIC 0x00000004 +#define I2C_SICR_STOPIC_BITN 2 +#define I2C_SICR_STOPIC_M 0x00000004 +#define I2C_SICR_STOPIC_S 2 // Field: [1] STARTIC // // Start condition interrupt clear // // Writing 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS. -#define I2C_SICR_STARTIC 0x00000002 -#define I2C_SICR_STARTIC_BITN 1 -#define I2C_SICR_STARTIC_M 0x00000002 -#define I2C_SICR_STARTIC_S 1 +#define I2C_SICR_STARTIC 0x00000002 +#define I2C_SICR_STARTIC_BITN 1 +#define I2C_SICR_STARTIC_M 0x00000002 +#define I2C_SICR_STARTIC_S 1 // Field: [0] DATAIC // // Data interrupt clear // // Writing 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS. -#define I2C_SICR_DATAIC 0x00000001 -#define I2C_SICR_DATAIC_BITN 0 -#define I2C_SICR_DATAIC_M 0x00000001 -#define I2C_SICR_DATAIC_S 0 +#define I2C_SICR_DATAIC 0x00000001 +#define I2C_SICR_DATAIC_BITN 0 +#define I2C_SICR_DATAIC_M 0x00000001 +#define I2C_SICR_DATAIC_S 0 //***************************************************************************** // @@ -375,9 +375,9 @@ // // I2C master slave address // Defines which slave is addressed for the transaction in master mode -#define I2C_MSA_SA_W 7 -#define I2C_MSA_SA_M 0x000000FE -#define I2C_MSA_SA_S 1 +#define I2C_MSA_SA_W 7 +#define I2C_MSA_SA_M 0x000000FE +#define I2C_MSA_SA_S 1 // Field: [0] RS // @@ -387,12 +387,12 @@ // ENUMs: // RX Receive data from slave // TX Transmit/send data to slave -#define I2C_MSA_RS 0x00000001 -#define I2C_MSA_RS_BITN 0 -#define I2C_MSA_RS_M 0x00000001 -#define I2C_MSA_RS_S 0 -#define I2C_MSA_RS_RX 0x00000001 -#define I2C_MSA_RS_TX 0x00000000 +#define I2C_MSA_RS 0x00000001 +#define I2C_MSA_RS_BITN 0 +#define I2C_MSA_RS_M 0x00000001 +#define I2C_MSA_RS_S 0 +#define I2C_MSA_RS_RX 0x00000001 +#define I2C_MSA_RS_TX 0x00000000 //***************************************************************************** // @@ -407,10 +407,10 @@ // 1: The I2C bus is busy. // // The bit changes based on the MCTRL.START and MCTRL.STOP conditions. -#define I2C_MSTAT_BUSBSY 0x00000040 -#define I2C_MSTAT_BUSBSY_BITN 6 -#define I2C_MSTAT_BUSBSY_M 0x00000040 -#define I2C_MSTAT_BUSBSY_S 6 +#define I2C_MSTAT_BUSBSY 0x00000040 +#define I2C_MSTAT_BUSBSY_BITN 6 +#define I2C_MSTAT_BUSBSY_M 0x00000040 +#define I2C_MSTAT_BUSBSY_S 6 // Field: [5] IDLE // @@ -418,10 +418,10 @@ // // 0: The I2C controller is not idle. // 1: The I2C controller is idle. -#define I2C_MSTAT_IDLE 0x00000020 -#define I2C_MSTAT_IDLE_BITN 5 -#define I2C_MSTAT_IDLE_M 0x00000020 -#define I2C_MSTAT_IDLE_S 5 +#define I2C_MSTAT_IDLE 0x00000020 +#define I2C_MSTAT_IDLE_BITN 5 +#define I2C_MSTAT_IDLE_M 0x00000020 +#define I2C_MSTAT_IDLE_S 5 // Field: [4] ARBLST // @@ -429,10 +429,10 @@ // // 0: The I2C controller won arbitration. // 1: The I2C controller lost arbitration. -#define I2C_MSTAT_ARBLST 0x00000010 -#define I2C_MSTAT_ARBLST_BITN 4 -#define I2C_MSTAT_ARBLST_M 0x00000010 -#define I2C_MSTAT_ARBLST_S 4 +#define I2C_MSTAT_ARBLST 0x00000010 +#define I2C_MSTAT_ARBLST_BITN 4 +#define I2C_MSTAT_ARBLST_M 0x00000010 +#define I2C_MSTAT_ARBLST_S 4 // Field: [3] DATACK_N // @@ -440,10 +440,10 @@ // // 0: The transmitted data was acknowledged. // 1: The transmitted data was not acknowledged. -#define I2C_MSTAT_DATACK_N 0x00000008 -#define I2C_MSTAT_DATACK_N_BITN 3 -#define I2C_MSTAT_DATACK_N_M 0x00000008 -#define I2C_MSTAT_DATACK_N_S 3 +#define I2C_MSTAT_DATACK_N 0x00000008 +#define I2C_MSTAT_DATACK_N_BITN 3 +#define I2C_MSTAT_DATACK_N_M 0x00000008 +#define I2C_MSTAT_DATACK_N_S 3 // Field: [2] ADRACK_N // @@ -451,10 +451,10 @@ // // 0: The transmitted address was acknowledged. // 1: The transmitted address was not acknowledged. -#define I2C_MSTAT_ADRACK_N 0x00000004 -#define I2C_MSTAT_ADRACK_N_BITN 2 -#define I2C_MSTAT_ADRACK_N_M 0x00000004 -#define I2C_MSTAT_ADRACK_N_S 2 +#define I2C_MSTAT_ADRACK_N 0x00000004 +#define I2C_MSTAT_ADRACK_N_BITN 2 +#define I2C_MSTAT_ADRACK_N_M 0x00000004 +#define I2C_MSTAT_ADRACK_N_S 2 // Field: [1] ERR // @@ -462,10 +462,10 @@ // // 0: No error was detected on the last operation. // 1: An error occurred on the last operation. -#define I2C_MSTAT_ERR 0x00000002 -#define I2C_MSTAT_ERR_BITN 1 -#define I2C_MSTAT_ERR_M 0x00000002 -#define I2C_MSTAT_ERR_S 1 +#define I2C_MSTAT_ERR 0x00000002 +#define I2C_MSTAT_ERR_BITN 1 +#define I2C_MSTAT_ERR_M 0x00000002 +#define I2C_MSTAT_ERR_S 1 // Field: [0] BUSY // @@ -483,10 +483,10 @@ // four SYSBUS clock cycles before issuing a controller status inquiry through // MSTAT register. // Any prior inquiry would result in wrong status being reported. -#define I2C_MSTAT_BUSY 0x00000001 -#define I2C_MSTAT_BUSY_BITN 0 -#define I2C_MSTAT_BUSY_M 0x00000001 -#define I2C_MSTAT_BUSY_S 0 +#define I2C_MSTAT_BUSY 0x00000001 +#define I2C_MSTAT_BUSY_BITN 0 +#define I2C_MSTAT_BUSY_M 0x00000001 +#define I2C_MSTAT_BUSY_S 0 //***************************************************************************** // @@ -505,12 +505,12 @@ // ENUMs: // EN Enable acknowledge // DIS Disable acknowledge -#define I2C_MCTRL_ACK 0x00000008 -#define I2C_MCTRL_ACK_BITN 3 -#define I2C_MCTRL_ACK_M 0x00000008 -#define I2C_MCTRL_ACK_S 3 -#define I2C_MCTRL_ACK_EN 0x00000008 -#define I2C_MCTRL_ACK_DIS 0x00000000 +#define I2C_MCTRL_ACK 0x00000008 +#define I2C_MCTRL_ACK_BITN 3 +#define I2C_MCTRL_ACK_M 0x00000008 +#define I2C_MCTRL_ACK_S 3 +#define I2C_MCTRL_ACK_EN 0x00000008 +#define I2C_MCTRL_ACK_DIS 0x00000000 // Field: [2] STOP // @@ -522,12 +522,12 @@ // ENUMs: // EN Enable STOP // DIS Disable STOP -#define I2C_MCTRL_STOP 0x00000004 -#define I2C_MCTRL_STOP_BITN 2 -#define I2C_MCTRL_STOP_M 0x00000004 -#define I2C_MCTRL_STOP_S 2 -#define I2C_MCTRL_STOP_EN 0x00000004 -#define I2C_MCTRL_STOP_DIS 0x00000000 +#define I2C_MCTRL_STOP 0x00000004 +#define I2C_MCTRL_STOP_BITN 2 +#define I2C_MCTRL_STOP_M 0x00000004 +#define I2C_MCTRL_STOP_S 2 +#define I2C_MCTRL_STOP_EN 0x00000004 +#define I2C_MCTRL_STOP_DIS 0x00000000 // Field: [1] START // @@ -538,12 +538,12 @@ // ENUMs: // EN Enable START // DIS Disable START -#define I2C_MCTRL_START 0x00000002 -#define I2C_MCTRL_START_BITN 1 -#define I2C_MCTRL_START_M 0x00000002 -#define I2C_MCTRL_START_S 1 -#define I2C_MCTRL_START_EN 0x00000002 -#define I2C_MCTRL_START_DIS 0x00000000 +#define I2C_MCTRL_START 0x00000002 +#define I2C_MCTRL_START_BITN 1 +#define I2C_MCTRL_START_M 0x00000002 +#define I2C_MCTRL_START_S 1 +#define I2C_MCTRL_START_EN 0x00000002 +#define I2C_MCTRL_START_DIS 0x00000000 // Field: [0] RUN // @@ -554,12 +554,12 @@ // ENUMs: // EN Enable Master // DIS Disable Master -#define I2C_MCTRL_RUN 0x00000001 -#define I2C_MCTRL_RUN_BITN 0 -#define I2C_MCTRL_RUN_M 0x00000001 -#define I2C_MCTRL_RUN_S 0 -#define I2C_MCTRL_RUN_EN 0x00000001 -#define I2C_MCTRL_RUN_DIS 0x00000000 +#define I2C_MCTRL_RUN 0x00000001 +#define I2C_MCTRL_RUN_BITN 0 +#define I2C_MCTRL_RUN_M 0x00000001 +#define I2C_MCTRL_RUN_S 0 +#define I2C_MCTRL_RUN_EN 0x00000001 +#define I2C_MCTRL_RUN_DIS 0x00000000 //***************************************************************************** // @@ -570,9 +570,9 @@ // // When Read: Last RX Data is returned // When Written: Data is transferred during TX transaction -#define I2C_MDR_DATA_W 8 -#define I2C_MDR_DATA_M 0x000000FF -#define I2C_MDR_DATA_S 0 +#define I2C_MDR_DATA_W 8 +#define I2C_MDR_DATA_M 0x000000FF +#define I2C_MDR_DATA_S 0 //***************************************************************************** // @@ -582,10 +582,10 @@ // Field: [7] TPR_7 // // Must be set to 0 to set TPR. If set to 1, a write to TPR will be ignored. -#define I2C_MTPR_TPR_7 0x00000080 -#define I2C_MTPR_TPR_7_BITN 7 -#define I2C_MTPR_TPR_7_M 0x00000080 -#define I2C_MTPR_TPR_7_S 7 +#define I2C_MTPR_TPR_7 0x00000080 +#define I2C_MTPR_TPR_7_BITN 7 +#define I2C_MTPR_TPR_7_M 0x00000080 +#define I2C_MTPR_TPR_7_S 7 // Field: [6:0] TPR // @@ -598,9 +598,9 @@ // SCL_LP is the SCL low period (fixed at 6). // SCL_HP is the SCL high period (fixed at 4). // CLK_PRD is the system clock period in ns. -#define I2C_MTPR_TPR_W 7 -#define I2C_MTPR_TPR_M 0x0000007F -#define I2C_MTPR_TPR_S 0 +#define I2C_MTPR_TPR_W 7 +#define I2C_MTPR_TPR_M 0x0000007F +#define I2C_MTPR_TPR_S 0 //***************************************************************************** // @@ -618,12 +618,12 @@ // ENUMs: // EN Enable Interrupt // DIS Disable Interrupt -#define I2C_MIMR_IM 0x00000001 -#define I2C_MIMR_IM_BITN 0 -#define I2C_MIMR_IM_M 0x00000001 -#define I2C_MIMR_IM_S 0 -#define I2C_MIMR_IM_EN 0x00000001 -#define I2C_MIMR_IM_DIS 0x00000000 +#define I2C_MIMR_IM 0x00000001 +#define I2C_MIMR_IM_BITN 0 +#define I2C_MIMR_IM_M 0x00000001 +#define I2C_MIMR_IM_S 0 +#define I2C_MIMR_IM_EN 0x00000001 +#define I2C_MIMR_IM_DIS 0x00000000 //***************************************************************************** // @@ -638,10 +638,10 @@ // 1: A master interrupt is pending. // // This bit is cleared by writing 1 to the MICR.IC bit . -#define I2C_MRIS_RIS 0x00000001 -#define I2C_MRIS_RIS_BITN 0 -#define I2C_MRIS_RIS_M 0x00000001 -#define I2C_MRIS_RIS_S 0 +#define I2C_MRIS_RIS 0x00000001 +#define I2C_MRIS_RIS_BITN 0 +#define I2C_MRIS_RIS_M 0x00000001 +#define I2C_MRIS_RIS_S 0 //***************************************************************************** // @@ -656,10 +656,10 @@ // 1: A master interrupt is pending. // // This bit is cleared by writing 1 to the MICR.IC bit . -#define I2C_MMIS_MIS 0x00000001 -#define I2C_MMIS_MIS_BITN 0 -#define I2C_MMIS_MIS_M 0x00000001 -#define I2C_MMIS_MIS_S 0 +#define I2C_MMIS_MIS 0x00000001 +#define I2C_MMIS_MIS_BITN 0 +#define I2C_MMIS_MIS_M 0x00000001 +#define I2C_MMIS_MIS_S 0 //***************************************************************************** // @@ -672,10 +672,10 @@ // Writing 1 to this bit clears MRIS.RIS and MMIS.MIS . // // Reading this register returns no meaningful data. -#define I2C_MICR_IC 0x00000001 -#define I2C_MICR_IC_BITN 0 -#define I2C_MICR_IC_M 0x00000001 -#define I2C_MICR_IC_S 0 +#define I2C_MICR_IC 0x00000001 +#define I2C_MICR_IC_BITN 0 +#define I2C_MICR_IC_M 0x00000001 +#define I2C_MICR_IC_S 0 //***************************************************************************** // @@ -688,12 +688,12 @@ // ENUMs: // EN Slave mode is enabled. // DIS Slave mode is disabled. -#define I2C_MCR_SFE 0x00000020 -#define I2C_MCR_SFE_BITN 5 -#define I2C_MCR_SFE_M 0x00000020 -#define I2C_MCR_SFE_S 5 -#define I2C_MCR_SFE_EN 0x00000020 -#define I2C_MCR_SFE_DIS 0x00000000 +#define I2C_MCR_SFE 0x00000020 +#define I2C_MCR_SFE_BITN 5 +#define I2C_MCR_SFE_M 0x00000020 +#define I2C_MCR_SFE_S 5 +#define I2C_MCR_SFE_EN 0x00000020 +#define I2C_MCR_SFE_DIS 0x00000000 // Field: [4] MFE // @@ -701,12 +701,12 @@ // ENUMs: // EN Master mode is enabled. // DIS Master mode is disabled. -#define I2C_MCR_MFE 0x00000010 -#define I2C_MCR_MFE_BITN 4 -#define I2C_MCR_MFE_M 0x00000010 -#define I2C_MCR_MFE_S 4 -#define I2C_MCR_MFE_EN 0x00000010 -#define I2C_MCR_MFE_DIS 0x00000000 +#define I2C_MCR_MFE 0x00000010 +#define I2C_MCR_MFE_BITN 4 +#define I2C_MCR_MFE_M 0x00000010 +#define I2C_MCR_MFE_S 4 +#define I2C_MCR_MFE_EN 0x00000010 +#define I2C_MCR_MFE_DIS 0x00000000 // Field: [0] LPBK // @@ -717,12 +717,11 @@ // ENUMs: // EN Enable Test Mode // DIS Disable Test Mode -#define I2C_MCR_LPBK 0x00000001 -#define I2C_MCR_LPBK_BITN 0 -#define I2C_MCR_LPBK_M 0x00000001 -#define I2C_MCR_LPBK_S 0 -#define I2C_MCR_LPBK_EN 0x00000001 -#define I2C_MCR_LPBK_DIS 0x00000000 - +#define I2C_MCR_LPBK 0x00000001 +#define I2C_MCR_LPBK_BITN 0 +#define I2C_MCR_LPBK_M 0x00000001 +#define I2C_MCR_LPBK_S 0 +#define I2C_MCR_LPBK_EN 0x00000001 +#define I2C_MCR_LPBK_DIS 0x00000000 #endif // __I2C__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_i2s.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_i2s.h index ee850c7..7d5d7da 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_i2s.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_i2s.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_i2s_h -* Revised: 2017-11-02 10:21:28 +0100 (Thu, 02 Nov 2017) -* Revision: 50141 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_i2s_h + * Revised: 2017-11-02 10:21:28 +0100 (Thu, 02 Nov 2017) + * Revision: 50141 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_I2S_H__ #define __HW_I2S_H__ @@ -44,91 +44,91 @@ // //***************************************************************************** // WCLK Source Selection -#define I2S_O_AIFWCLKSRC 0x00000000 +#define I2S_O_AIFWCLKSRC 0x00000000 // DMA Buffer Size Configuration -#define I2S_O_AIFDMACFG 0x00000004 +#define I2S_O_AIFDMACFG 0x00000004 // Pin Direction -#define I2S_O_AIFDIRCFG 0x00000008 +#define I2S_O_AIFDIRCFG 0x00000008 // Serial Interface Format Configuration -#define I2S_O_AIFFMTCFG 0x0000000C +#define I2S_O_AIFFMTCFG 0x0000000C // Word Selection Bit Mask for Pin 0 -#define I2S_O_AIFWMASK0 0x00000010 +#define I2S_O_AIFWMASK0 0x00000010 // Word Selection Bit Mask for Pin 1 -#define I2S_O_AIFWMASK1 0x00000014 +#define I2S_O_AIFWMASK1 0x00000014 // Audio Interface PWM Debug Value -#define I2S_O_AIFPWMVALUE 0x0000001C +#define I2S_O_AIFPWMVALUE 0x0000001C // DMA Input Buffer Next Pointer -#define I2S_O_AIFINPTRNEXT 0x00000020 +#define I2S_O_AIFINPTRNEXT 0x00000020 // DMA Input Buffer Current Pointer -#define I2S_O_AIFINPTR 0x00000024 +#define I2S_O_AIFINPTR 0x00000024 // DMA Output Buffer Next Pointer -#define I2S_O_AIFOUTPTRNEXT 0x00000028 +#define I2S_O_AIFOUTPTRNEXT 0x00000028 // DMA Output Buffer Current Pointer -#define I2S_O_AIFOUTPTR 0x0000002C +#define I2S_O_AIFOUTPTR 0x0000002C // Samplestamp Generator Control Register -#define I2S_O_STMPCTL 0x00000034 +#define I2S_O_STMPCTL 0x00000034 // Captured XOSC Counter Value, Capture Channel 0 -#define I2S_O_STMPXCNTCAPT0 0x00000038 +#define I2S_O_STMPXCNTCAPT0 0x00000038 // XOSC Period Value -#define I2S_O_STMPXPER 0x0000003C +#define I2S_O_STMPXPER 0x0000003C // Captured WCLK Counter Value, Capture Channel 0 -#define I2S_O_STMPWCNTCAPT0 0x00000040 +#define I2S_O_STMPWCNTCAPT0 0x00000040 // WCLK Counter Period Value -#define I2S_O_STMPWPER 0x00000044 +#define I2S_O_STMPWPER 0x00000044 // WCLK Counter Trigger Value for Input Pins -#define I2S_O_STMPINTRIG 0x00000048 +#define I2S_O_STMPINTRIG 0x00000048 // WCLK Counter Trigger Value for Output Pins -#define I2S_O_STMPOUTTRIG 0x0000004C +#define I2S_O_STMPOUTTRIG 0x0000004C // WCLK Counter Set Operation -#define I2S_O_STMPWSET 0x00000050 +#define I2S_O_STMPWSET 0x00000050 // WCLK Counter Add Operation -#define I2S_O_STMPWADD 0x00000054 +#define I2S_O_STMPWADD 0x00000054 // XOSC Minimum Period Value -#define I2S_O_STMPXPERMIN 0x00000058 +#define I2S_O_STMPXPERMIN 0x00000058 // Current Value of WCNT -#define I2S_O_STMPWCNT 0x0000005C +#define I2S_O_STMPWCNT 0x0000005C // Current Value of XCNT -#define I2S_O_STMPXCNT 0x00000060 +#define I2S_O_STMPXCNT 0x00000060 // Internal -#define I2S_O_STMPXCNTCAPT1 0x00000064 +#define I2S_O_STMPXCNTCAPT1 0x00000064 // Internal -#define I2S_O_STMPWCNTCAPT1 0x00000068 +#define I2S_O_STMPWCNTCAPT1 0x00000068 // Interrupt Mask Register -#define I2S_O_IRQMASK 0x00000070 +#define I2S_O_IRQMASK 0x00000070 // Raw Interrupt Status Register -#define I2S_O_IRQFLAGS 0x00000074 +#define I2S_O_IRQFLAGS 0x00000074 // Interrupt Set Register -#define I2S_O_IRQSET 0x00000078 +#define I2S_O_IRQSET 0x00000078 // Interrupt Clear Register -#define I2S_O_IRQCLR 0x0000007C +#define I2S_O_IRQCLR 0x0000007C //***************************************************************************** // @@ -141,10 +141,10 @@ // // 0: Not inverted // 1: Inverted -#define I2S_AIFWCLKSRC_WCLK_INV 0x00000004 -#define I2S_AIFWCLKSRC_WCLK_INV_BITN 2 -#define I2S_AIFWCLKSRC_WCLK_INV_M 0x00000004 -#define I2S_AIFWCLKSRC_WCLK_INV_S 2 +#define I2S_AIFWCLKSRC_WCLK_INV 0x00000004 +#define I2S_AIFWCLKSRC_WCLK_INV_BITN 2 +#define I2S_AIFWCLKSRC_WCLK_INV_M 0x00000004 +#define I2S_AIFWCLKSRC_WCLK_INV_S 2 // Field: [1:0] WCLK_SRC // @@ -156,13 +156,13 @@ // INT Internal WCLK generator, from module PRCM // EXT External WCLK generator, from pad // NONE None ('0') -#define I2S_AIFWCLKSRC_WCLK_SRC_W 2 -#define I2S_AIFWCLKSRC_WCLK_SRC_M 0x00000003 -#define I2S_AIFWCLKSRC_WCLK_SRC_S 0 -#define I2S_AIFWCLKSRC_WCLK_SRC_RESERVED 0x00000003 -#define I2S_AIFWCLKSRC_WCLK_SRC_INT 0x00000002 -#define I2S_AIFWCLKSRC_WCLK_SRC_EXT 0x00000001 -#define I2S_AIFWCLKSRC_WCLK_SRC_NONE 0x00000000 +#define I2S_AIFWCLKSRC_WCLK_SRC_W 2 +#define I2S_AIFWCLKSRC_WCLK_SRC_M 0x00000003 +#define I2S_AIFWCLKSRC_WCLK_SRC_S 0 +#define I2S_AIFWCLKSRC_WCLK_SRC_RESERVED 0x00000003 +#define I2S_AIFWCLKSRC_WCLK_SRC_INT 0x00000002 +#define I2S_AIFWCLKSRC_WCLK_SRC_EXT 0x00000001 +#define I2S_AIFWCLKSRC_WCLK_SRC_NONE 0x00000000 //***************************************************************************** // @@ -175,9 +175,9 @@ // register field enables and initializes AIF. Note that before doing so, all // other configuration must have been done, and AIFINPTRNEXT/AIFOUTPTRNEXT must // have been loaded. -#define I2S_AIFDMACFG_END_FRAME_IDX_W 8 -#define I2S_AIFDMACFG_END_FRAME_IDX_M 0x000000FF -#define I2S_AIFDMACFG_END_FRAME_IDX_S 0 +#define I2S_AIFDMACFG_END_FRAME_IDX_W 8 +#define I2S_AIFDMACFG_END_FRAME_IDX_M 0x000000FF +#define I2S_AIFDMACFG_END_FRAME_IDX_S 0 //***************************************************************************** // @@ -193,12 +193,12 @@ // OUT Output mode // IN Input mode // DIS Not in use (disabled) -#define I2S_AIFDIRCFG_AD1_W 2 -#define I2S_AIFDIRCFG_AD1_M 0x00000030 -#define I2S_AIFDIRCFG_AD1_S 4 -#define I2S_AIFDIRCFG_AD1_OUT 0x00000020 -#define I2S_AIFDIRCFG_AD1_IN 0x00000010 -#define I2S_AIFDIRCFG_AD1_DIS 0x00000000 +#define I2S_AIFDIRCFG_AD1_W 2 +#define I2S_AIFDIRCFG_AD1_M 0x00000030 +#define I2S_AIFDIRCFG_AD1_S 4 +#define I2S_AIFDIRCFG_AD1_OUT 0x00000020 +#define I2S_AIFDIRCFG_AD1_IN 0x00000010 +#define I2S_AIFDIRCFG_AD1_DIS 0x00000000 // Field: [1:0] AD0 // @@ -209,12 +209,12 @@ // OUT Output mode // IN Input mode // DIS Not in use (disabled) -#define I2S_AIFDIRCFG_AD0_W 2 -#define I2S_AIFDIRCFG_AD0_M 0x00000003 -#define I2S_AIFDIRCFG_AD0_S 0 -#define I2S_AIFDIRCFG_AD0_OUT 0x00000002 -#define I2S_AIFDIRCFG_AD0_IN 0x00000001 -#define I2S_AIFDIRCFG_AD0_DIS 0x00000000 +#define I2S_AIFDIRCFG_AD0_W 2 +#define I2S_AIFDIRCFG_AD0_M 0x00000003 +#define I2S_AIFDIRCFG_AD0_S 0 +#define I2S_AIFDIRCFG_AD0_OUT 0x00000002 +#define I2S_AIFDIRCFG_AD0_IN 0x00000001 +#define I2S_AIFDIRCFG_AD0_DIS 0x00000000 //***************************************************************************** // @@ -235,9 +235,9 @@ // Note: When 0, MSB of the next word will be output in the idle period between // LSB of the previous word and the start of the next word. Otherwise logical 0 // will be output until the data delay has expired. -#define I2S_AIFFMTCFG_DATA_DELAY_W 8 -#define I2S_AIFFMTCFG_DATA_DELAY_M 0x0000FF00 -#define I2S_AIFFMTCFG_DATA_DELAY_S 8 +#define I2S_AIFFMTCFG_DATA_DELAY_W 8 +#define I2S_AIFFMTCFG_DATA_DELAY_M 0x0000FF00 +#define I2S_AIFFMTCFG_DATA_DELAY_S 8 // Field: [7] MEM_LEN_24 // @@ -246,12 +246,12 @@ // 24BIT 24-bit (one 8 bit and one 16 bit locked access per // sample) // 16BIT 16-bit (one 16 bit access per sample) -#define I2S_AIFFMTCFG_MEM_LEN_24 0x00000080 -#define I2S_AIFFMTCFG_MEM_LEN_24_BITN 7 -#define I2S_AIFFMTCFG_MEM_LEN_24_M 0x00000080 -#define I2S_AIFFMTCFG_MEM_LEN_24_S 7 -#define I2S_AIFFMTCFG_MEM_LEN_24_24BIT 0x00000080 -#define I2S_AIFFMTCFG_MEM_LEN_24_16BIT 0x00000000 +#define I2S_AIFFMTCFG_MEM_LEN_24 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_BITN 7 +#define I2S_AIFFMTCFG_MEM_LEN_24_M 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_S 7 +#define I2S_AIFFMTCFG_MEM_LEN_24_24BIT 0x00000080 +#define I2S_AIFFMTCFG_MEM_LEN_24_16BIT 0x00000000 // Field: [6] SMPL_EDGE // @@ -262,12 +262,12 @@ // out on the negative edge. // NEG Data is sampled on the negative edge and clocked // out on the positive edge. -#define I2S_AIFFMTCFG_SMPL_EDGE 0x00000040 -#define I2S_AIFFMTCFG_SMPL_EDGE_BITN 6 -#define I2S_AIFFMTCFG_SMPL_EDGE_M 0x00000040 -#define I2S_AIFFMTCFG_SMPL_EDGE_S 6 -#define I2S_AIFFMTCFG_SMPL_EDGE_POS 0x00000040 -#define I2S_AIFFMTCFG_SMPL_EDGE_NEG 0x00000000 +#define I2S_AIFFMTCFG_SMPL_EDGE 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_BITN 6 +#define I2S_AIFFMTCFG_SMPL_EDGE_M 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_S 6 +#define I2S_AIFFMTCFG_SMPL_EDGE_POS 0x00000040 +#define I2S_AIFFMTCFG_SMPL_EDGE_NEG 0x00000000 // Field: [5] DUAL_PHASE // @@ -275,10 +275,10 @@ // // 0: Single-phase: DSP format // 1: Dual-phase: I2S, LJF and RJF formats -#define I2S_AIFFMTCFG_DUAL_PHASE 0x00000020 -#define I2S_AIFFMTCFG_DUAL_PHASE_BITN 5 -#define I2S_AIFFMTCFG_DUAL_PHASE_M 0x00000020 -#define I2S_AIFFMTCFG_DUAL_PHASE_S 5 +#define I2S_AIFFMTCFG_DUAL_PHASE 0x00000020 +#define I2S_AIFFMTCFG_DUAL_PHASE_BITN 5 +#define I2S_AIFFMTCFG_DUAL_PHASE_M 0x00000020 +#define I2S_AIFFMTCFG_DUAL_PHASE_S 5 // Field: [4:0] WORD_LEN // @@ -289,9 +289,9 @@ // Values below 8 and above 24 give undefined behavior. Data written to memory // is always aligned to 16 or 24 bits as defined by MEM_LEN_24. Bit widths that // differ from this alignment will either be truncated or zero padded. -#define I2S_AIFFMTCFG_WORD_LEN_W 5 -#define I2S_AIFFMTCFG_WORD_LEN_M 0x0000001F -#define I2S_AIFFMTCFG_WORD_LEN_S 0 +#define I2S_AIFFMTCFG_WORD_LEN_W 5 +#define I2S_AIFFMTCFG_WORD_LEN_M 0x0000001F +#define I2S_AIFFMTCFG_WORD_LEN_S 0 //***************************************************************************** // @@ -318,9 +318,9 @@ // If all bits are zero, no input words will be stored to memory, and the // output data lines will be constant '0'. This can be utilized when PWM debug // output is desired without any actively used output pins. -#define I2S_AIFWMASK0_MASK_W 8 -#define I2S_AIFWMASK0_MASK_M 0x000000FF -#define I2S_AIFWMASK0_MASK_S 0 +#define I2S_AIFWMASK0_MASK_W 8 +#define I2S_AIFWMASK0_MASK_M 0x000000FF +#define I2S_AIFWMASK0_MASK_S 0 //***************************************************************************** // @@ -347,9 +347,9 @@ // If all bits are zero, no input words will be stored to memory, and the // output data lines will be constant '0'. This can be utilized when PWM debug // output is desired without any actively used output pins. -#define I2S_AIFWMASK1_MASK_W 8 -#define I2S_AIFWMASK1_MASK_M 0x000000FF -#define I2S_AIFWMASK1_MASK_S 0 +#define I2S_AIFWMASK1_MASK_W 8 +#define I2S_AIFWMASK1_MASK_M 0x000000FF +#define I2S_AIFWMASK1_MASK_S 0 //***************************************************************************** // @@ -367,9 +367,9 @@ // ... // 0xFFFE: Width of the pulse (number of BCLK cycles, here 65534). // 0xFFFF: Constant high -#define I2S_AIFPWMVALUE_PULSE_WIDTH_W 16 -#define I2S_AIFPWMVALUE_PULSE_WIDTH_M 0x0000FFFF -#define I2S_AIFPWMVALUE_PULSE_WIDTH_S 0 +#define I2S_AIFPWMVALUE_PULSE_WIDTH_W 16 +#define I2S_AIFPWMVALUE_PULSE_WIDTH_M 0x0000FFFF +#define I2S_AIFPWMVALUE_PULSE_WIDTH_S 0 //***************************************************************************** // @@ -391,9 +391,9 @@ // The next pointer must be written to this register while the DMA function // uses the previously written pointer. If not written in time, // IRQFLAGS.PTR_ERR will be raised and all input pins will be disabled. -#define I2S_AIFINPTRNEXT_PTR_W 32 -#define I2S_AIFINPTRNEXT_PTR_M 0xFFFFFFFF -#define I2S_AIFINPTRNEXT_PTR_S 0 +#define I2S_AIFINPTRNEXT_PTR_W 32 +#define I2S_AIFINPTRNEXT_PTR_M 0xFFFFFFFF +#define I2S_AIFINPTRNEXT_PTR_S 0 //***************************************************************************** // @@ -404,9 +404,9 @@ // // Value of the DMA input buffer pointer currently used by the DMA controller. // Incremented by 1 (byte) or 2 (word) for each AHB access. -#define I2S_AIFINPTR_PTR_W 32 -#define I2S_AIFINPTR_PTR_M 0xFFFFFFFF -#define I2S_AIFINPTR_PTR_S 0 +#define I2S_AIFINPTR_PTR_W 32 +#define I2S_AIFINPTR_PTR_M 0xFFFFFFFF +#define I2S_AIFINPTR_PTR_S 0 //***************************************************************************** // @@ -429,9 +429,9 @@ // The next pointer must be written to this register while the DMA function // uses the previously written pointer. If not written in time, // IRQFLAGS.PTR_ERR will be raised and all output pins will be disabled. -#define I2S_AIFOUTPTRNEXT_PTR_W 32 -#define I2S_AIFOUTPTRNEXT_PTR_M 0xFFFFFFFF -#define I2S_AIFOUTPTRNEXT_PTR_S 0 +#define I2S_AIFOUTPTRNEXT_PTR_W 32 +#define I2S_AIFOUTPTRNEXT_PTR_M 0xFFFFFFFF +#define I2S_AIFOUTPTRNEXT_PTR_S 0 //***************************************************************************** // @@ -442,9 +442,9 @@ // // Value of the DMA output buffer pointer currently used by the DMA controller // Incremented by 1 (byte) or 2 (word) for each AHB access. -#define I2S_AIFOUTPTR_PTR_W 32 -#define I2S_AIFOUTPTR_PTR_M 0xFFFFFFFF -#define I2S_AIFOUTPTR_PTR_S 0 +#define I2S_AIFOUTPTR_PTR_W 32 +#define I2S_AIFOUTPTR_PTR_M 0xFFFFFFFF +#define I2S_AIFOUTPTR_PTR_S 0 //***************************************************************************** // @@ -456,20 +456,20 @@ // Low until the output pins are ready to be started by the samplestamp // generator. When started (that is STMPOUTTRIG equals the WCLK counter) the // bit goes back low. -#define I2S_STMPCTL_OUT_RDY 0x00000004 -#define I2S_STMPCTL_OUT_RDY_BITN 2 -#define I2S_STMPCTL_OUT_RDY_M 0x00000004 -#define I2S_STMPCTL_OUT_RDY_S 2 +#define I2S_STMPCTL_OUT_RDY 0x00000004 +#define I2S_STMPCTL_OUT_RDY_BITN 2 +#define I2S_STMPCTL_OUT_RDY_M 0x00000004 +#define I2S_STMPCTL_OUT_RDY_S 2 // Field: [1] IN_RDY // // Low until the input pins are ready to be started by the samplestamp // generator. When started (that is STMPINTRIG equals the WCLK counter) the bit // goes back low. -#define I2S_STMPCTL_IN_RDY 0x00000002 -#define I2S_STMPCTL_IN_RDY_BITN 1 -#define I2S_STMPCTL_IN_RDY_M 0x00000002 -#define I2S_STMPCTL_IN_RDY_S 1 +#define I2S_STMPCTL_IN_RDY 0x00000002 +#define I2S_STMPCTL_IN_RDY_BITN 1 +#define I2S_STMPCTL_IN_RDY_M 0x00000002 +#define I2S_STMPCTL_IN_RDY_S 1 // Field: [0] STMP_EN // @@ -477,10 +477,10 @@ // enabled after it has been properly configured. // When cleared, all samplestamp generator counters and capture values are // cleared. -#define I2S_STMPCTL_STMP_EN 0x00000001 -#define I2S_STMPCTL_STMP_EN_BITN 0 -#define I2S_STMPCTL_STMP_EN_M 0x00000001 -#define I2S_STMPCTL_STMP_EN_S 0 +#define I2S_STMPCTL_STMP_EN 0x00000001 +#define I2S_STMPCTL_STMP_EN_BITN 0 +#define I2S_STMPCTL_STMP_EN_M 0x00000001 +#define I2S_STMPCTL_STMP_EN_S 0 //***************************************************************************** // @@ -498,9 +498,9 @@ // number of BCLK periods and clk periods. // Note: When calculating the fractional part of the sample stamp, STMPXPER may // be less than this bit field. -#define I2S_STMPXCNTCAPT0_CAPT_VALUE_W 16 -#define I2S_STMPXCNTCAPT0_CAPT_VALUE_M 0x0000FFFF -#define I2S_STMPXCNTCAPT0_CAPT_VALUE_S 0 +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_W 16 +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPXCNTCAPT0_CAPT_VALUE_S 0 //***************************************************************************** // @@ -513,9 +513,9 @@ // the next value of the XOSC counter at the positive WCLK edge, had it not // been reset to 0). // The value is cleared when STMPCTL.STMP_EN = 0. -#define I2S_STMPXPER_VALUE_W 16 -#define I2S_STMPXPER_VALUE_M 0x0000FFFF -#define I2S_STMPXPER_VALUE_S 0 +#define I2S_STMPXPER_VALUE_W 16 +#define I2S_STMPXPER_VALUE_M 0x0000FFFF +#define I2S_STMPXPER_VALUE_S 0 //***************************************************************************** // @@ -530,9 +530,9 @@ // samplestamp generator was enabled (not taking modification through // STMPWADD/STMPWSET into account). // The value is cleared when STMPCTL.STMP_EN = 0. -#define I2S_STMPWCNTCAPT0_CAPT_VALUE_W 16 -#define I2S_STMPWCNTCAPT0_CAPT_VALUE_M 0x0000FFFF -#define I2S_STMPWCNTCAPT0_CAPT_VALUE_S 0 +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_W 16 +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPWCNTCAPT0_CAPT_VALUE_S 0 //***************************************************************************** // @@ -545,9 +545,9 @@ // found for the size of the sample buffer. This is thus a modulo value for the // WCLK counter. This number must correspond to the size of the sample buffer // used by the system (that is the index of the last sample plus 1). -#define I2S_STMPWPER_VALUE_W 16 -#define I2S_STMPWPER_VALUE_M 0x0000FFFF -#define I2S_STMPWPER_VALUE_S 0 +#define I2S_STMPWPER_VALUE_W 16 +#define I2S_STMPWPER_VALUE_M 0x0000FFFF +#define I2S_STMPWPER_VALUE_S 0 //***************************************************************************** // @@ -569,9 +569,9 @@ // // Note: To avoid false triggers, this bit field should be set higher than // STMPWPER.VALUE. -#define I2S_STMPINTRIG_IN_START_WCNT_W 16 -#define I2S_STMPINTRIG_IN_START_WCNT_M 0x0000FFFF -#define I2S_STMPINTRIG_IN_START_WCNT_S 0 +#define I2S_STMPINTRIG_IN_START_WCNT_W 16 +#define I2S_STMPINTRIG_IN_START_WCNT_M 0x0000FFFF +#define I2S_STMPINTRIG_IN_START_WCNT_S 0 //***************************************************************************** // @@ -598,9 +598,9 @@ // // Note: To avoid false triggers, this bit field should be set higher than // STMPWPER.VALUE. -#define I2S_STMPOUTTRIG_OUT_START_WCNT_W 16 -#define I2S_STMPOUTTRIG_OUT_START_WCNT_M 0x0000FFFF -#define I2S_STMPOUTTRIG_OUT_START_WCNT_S 0 +#define I2S_STMPOUTTRIG_OUT_START_WCNT_W 16 +#define I2S_STMPOUTTRIG_OUT_START_WCNT_M 0x0000FFFF +#define I2S_STMPOUTTRIG_OUT_START_WCNT_S 0 //***************************************************************************** // @@ -611,9 +611,9 @@ // // WCLK counter modification: Sets the running WCLK counter equal to the // written value. -#define I2S_STMPWSET_VALUE_W 16 -#define I2S_STMPWSET_VALUE_M 0x0000FFFF -#define I2S_STMPWSET_VALUE_S 0 +#define I2S_STMPWSET_VALUE_W 16 +#define I2S_STMPWSET_VALUE_M 0x0000FFFF +#define I2S_STMPWSET_VALUE_S 0 //***************************************************************************** // @@ -627,9 +627,9 @@ // operation, this will be taken into account. // To add a negative value, write "STMPWPER.VALUE - value". // -#define I2S_STMPWADD_VALUE_INC_W 16 -#define I2S_STMPWADD_VALUE_INC_M 0x0000FFFF -#define I2S_STMPWADD_VALUE_INC_S 0 +#define I2S_STMPWADD_VALUE_INC_W 16 +#define I2S_STMPWADD_VALUE_INC_M 0x0000FFFF +#define I2S_STMPWADD_VALUE_INC_S 0 //***************************************************************************** // @@ -644,9 +644,9 @@ // value written. // The minimum value can be used to detect extra WCLK pulses (this registers // value will be significantly smaller than STMPXPER.VALUE). -#define I2S_STMPXPERMIN_VALUE_W 16 -#define I2S_STMPXPERMIN_VALUE_M 0x0000FFFF -#define I2S_STMPXPERMIN_VALUE_S 0 +#define I2S_STMPXPERMIN_VALUE_W 16 +#define I2S_STMPXPERMIN_VALUE_M 0x0000FFFF +#define I2S_STMPXPERMIN_VALUE_S 0 //***************************************************************************** // @@ -656,9 +656,9 @@ // Field: [15:0] CURR_VALUE // // Current value of the WCLK counter -#define I2S_STMPWCNT_CURR_VALUE_W 16 -#define I2S_STMPWCNT_CURR_VALUE_M 0x0000FFFF -#define I2S_STMPWCNT_CURR_VALUE_S 0 +#define I2S_STMPWCNT_CURR_VALUE_W 16 +#define I2S_STMPWCNT_CURR_VALUE_M 0x0000FFFF +#define I2S_STMPWCNT_CURR_VALUE_S 0 //***************************************************************************** // @@ -668,9 +668,9 @@ // Field: [15:0] CURR_VALUE // // Current value of the XOSC counter, latched when reading STMPWCNT. -#define I2S_STMPXCNT_CURR_VALUE_W 16 -#define I2S_STMPXCNT_CURR_VALUE_M 0x0000FFFF -#define I2S_STMPXCNT_CURR_VALUE_S 0 +#define I2S_STMPXCNT_CURR_VALUE_W 16 +#define I2S_STMPXCNT_CURR_VALUE_M 0x0000FFFF +#define I2S_STMPXCNT_CURR_VALUE_S 0 //***************************************************************************** // @@ -680,9 +680,9 @@ // Field: [15:0] CAPT_VALUE // // Internal. Only to be used through TI provided API. -#define I2S_STMPXCNTCAPT1_CAPT_VALUE_W 16 -#define I2S_STMPXCNTCAPT1_CAPT_VALUE_M 0x0000FFFF -#define I2S_STMPXCNTCAPT1_CAPT_VALUE_S 0 +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_W 16 +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPXCNTCAPT1_CAPT_VALUE_S 0 //***************************************************************************** // @@ -692,9 +692,9 @@ // Field: [15:0] CAPT_VALUE // // Internal. Only to be used through TI provided API. -#define I2S_STMPWCNTCAPT1_CAPT_VALUE_W 16 -#define I2S_STMPWCNTCAPT1_CAPT_VALUE_M 0x0000FFFF -#define I2S_STMPWCNTCAPT1_CAPT_VALUE_S 0 +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_W 16 +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_M 0x0000FFFF +#define I2S_STMPWCNTCAPT1_CAPT_VALUE_S 0 //***************************************************************************** // @@ -707,10 +707,10 @@ // // 0: Disable // 1: Enable -#define I2S_IRQMASK_AIF_DMA_IN 0x00000020 -#define I2S_IRQMASK_AIF_DMA_IN_BITN 5 -#define I2S_IRQMASK_AIF_DMA_IN_M 0x00000020 -#define I2S_IRQMASK_AIF_DMA_IN_S 5 +#define I2S_IRQMASK_AIF_DMA_IN 0x00000020 +#define I2S_IRQMASK_AIF_DMA_IN_BITN 5 +#define I2S_IRQMASK_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQMASK_AIF_DMA_IN_S 5 // Field: [4] AIF_DMA_OUT // @@ -718,10 +718,10 @@ // // 0: Disable // 1: Enable -#define I2S_IRQMASK_AIF_DMA_OUT 0x00000010 -#define I2S_IRQMASK_AIF_DMA_OUT_BITN 4 -#define I2S_IRQMASK_AIF_DMA_OUT_M 0x00000010 -#define I2S_IRQMASK_AIF_DMA_OUT_S 4 +#define I2S_IRQMASK_AIF_DMA_OUT 0x00000010 +#define I2S_IRQMASK_AIF_DMA_OUT_BITN 4 +#define I2S_IRQMASK_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQMASK_AIF_DMA_OUT_S 4 // Field: [3] WCLK_TIMEOUT // @@ -729,10 +729,10 @@ // // 0: Disable // 1: Enable -#define I2S_IRQMASK_WCLK_TIMEOUT 0x00000008 -#define I2S_IRQMASK_WCLK_TIMEOUT_BITN 3 -#define I2S_IRQMASK_WCLK_TIMEOUT_M 0x00000008 -#define I2S_IRQMASK_WCLK_TIMEOUT_S 3 +#define I2S_IRQMASK_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQMASK_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQMASK_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQMASK_WCLK_TIMEOUT_S 3 // Field: [2] BUS_ERR // @@ -740,10 +740,10 @@ // // 0: Disable // 1: Enable -#define I2S_IRQMASK_BUS_ERR 0x00000004 -#define I2S_IRQMASK_BUS_ERR_BITN 2 -#define I2S_IRQMASK_BUS_ERR_M 0x00000004 -#define I2S_IRQMASK_BUS_ERR_S 2 +#define I2S_IRQMASK_BUS_ERR 0x00000004 +#define I2S_IRQMASK_BUS_ERR_BITN 2 +#define I2S_IRQMASK_BUS_ERR_M 0x00000004 +#define I2S_IRQMASK_BUS_ERR_S 2 // Field: [1] WCLK_ERR // @@ -751,10 +751,10 @@ // // 0: Disable // 1: Enable -#define I2S_IRQMASK_WCLK_ERR 0x00000002 -#define I2S_IRQMASK_WCLK_ERR_BITN 1 -#define I2S_IRQMASK_WCLK_ERR_M 0x00000002 -#define I2S_IRQMASK_WCLK_ERR_S 1 +#define I2S_IRQMASK_WCLK_ERR 0x00000002 +#define I2S_IRQMASK_WCLK_ERR_BITN 1 +#define I2S_IRQMASK_WCLK_ERR_M 0x00000002 +#define I2S_IRQMASK_WCLK_ERR_S 1 // Field: [0] PTR_ERR // @@ -762,10 +762,10 @@ // // 0: Disable // 1: Enable -#define I2S_IRQMASK_PTR_ERR 0x00000001 -#define I2S_IRQMASK_PTR_ERR_BITN 0 -#define I2S_IRQMASK_PTR_ERR_M 0x00000001 -#define I2S_IRQMASK_PTR_ERR_S 0 +#define I2S_IRQMASK_PTR_ERR 0x00000001 +#define I2S_IRQMASK_PTR_ERR_BITN 0 +#define I2S_IRQMASK_PTR_ERR_M 0x00000001 +#define I2S_IRQMASK_PTR_ERR_S 0 //***************************************************************************** // @@ -777,20 +777,20 @@ // Set when condition for this bit field event occurs (auto cleared when input // pointer is updated - AIFINPTRNEXT), see description of AIFINPTRNEXT register // for details. -#define I2S_IRQFLAGS_AIF_DMA_IN 0x00000020 -#define I2S_IRQFLAGS_AIF_DMA_IN_BITN 5 -#define I2S_IRQFLAGS_AIF_DMA_IN_M 0x00000020 -#define I2S_IRQFLAGS_AIF_DMA_IN_S 5 +#define I2S_IRQFLAGS_AIF_DMA_IN 0x00000020 +#define I2S_IRQFLAGS_AIF_DMA_IN_BITN 5 +#define I2S_IRQFLAGS_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQFLAGS_AIF_DMA_IN_S 5 // Field: [4] AIF_DMA_OUT // // Set when condition for this bit field event occurs (auto cleared when output // pointer is updated - AIFOUTPTRNEXT), see description of AIFOUTPTRNEXT // register for details -#define I2S_IRQFLAGS_AIF_DMA_OUT 0x00000010 -#define I2S_IRQFLAGS_AIF_DMA_OUT_BITN 4 -#define I2S_IRQFLAGS_AIF_DMA_OUT_M 0x00000010 -#define I2S_IRQFLAGS_AIF_DMA_OUT_S 4 +#define I2S_IRQFLAGS_AIF_DMA_OUT 0x00000010 +#define I2S_IRQFLAGS_AIF_DMA_OUT_BITN 4 +#define I2S_IRQFLAGS_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQFLAGS_AIF_DMA_OUT_S 4 // Field: [3] WCLK_TIMEOUT // @@ -800,10 +800,10 @@ // // The bit is sticky and may only be cleared by software (by writing '1' to // IRQCLR.WCLK_TIMEOUT). -#define I2S_IRQFLAGS_WCLK_TIMEOUT 0x00000008 -#define I2S_IRQFLAGS_WCLK_TIMEOUT_BITN 3 -#define I2S_IRQFLAGS_WCLK_TIMEOUT_M 0x00000008 -#define I2S_IRQFLAGS_WCLK_TIMEOUT_S 3 +#define I2S_IRQFLAGS_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQFLAGS_WCLK_TIMEOUT_S 3 // Field: [2] BUS_ERR // @@ -815,10 +815,10 @@ // // Note that DMA initiated transactions to illegal addresses will not trigger // an interrupt. The response to such transactions is undefined. -#define I2S_IRQFLAGS_BUS_ERR 0x00000004 -#define I2S_IRQFLAGS_BUS_ERR_BITN 2 -#define I2S_IRQFLAGS_BUS_ERR_M 0x00000004 -#define I2S_IRQFLAGS_BUS_ERR_S 2 +#define I2S_IRQFLAGS_BUS_ERR 0x00000004 +#define I2S_IRQFLAGS_BUS_ERR_BITN 2 +#define I2S_IRQFLAGS_BUS_ERR_M 0x00000004 +#define I2S_IRQFLAGS_BUS_ERR_S 2 // Field: [1] WCLK_ERR // @@ -832,10 +832,10 @@ // This error requires a complete restart since word synchronization has been // lost. The bit is sticky and may only be cleared by software (by writing '1' // to IRQCLR.WCLK_ERR). -#define I2S_IRQFLAGS_WCLK_ERR 0x00000002 -#define I2S_IRQFLAGS_WCLK_ERR_BITN 1 -#define I2S_IRQFLAGS_WCLK_ERR_M 0x00000002 -#define I2S_IRQFLAGS_WCLK_ERR_S 1 +#define I2S_IRQFLAGS_WCLK_ERR 0x00000002 +#define I2S_IRQFLAGS_WCLK_ERR_BITN 1 +#define I2S_IRQFLAGS_WCLK_ERR_M 0x00000002 +#define I2S_IRQFLAGS_WCLK_ERR_S 1 // Field: [0] PTR_ERR // @@ -844,10 +844,10 @@ // This error requires a complete restart since word synchronization has been // lost. The bit is sticky and may only be cleared by software (by writing '1' // to IRQCLR.PTR_ERR). -#define I2S_IRQFLAGS_PTR_ERR 0x00000001 -#define I2S_IRQFLAGS_PTR_ERR_BITN 0 -#define I2S_IRQFLAGS_PTR_ERR_M 0x00000001 -#define I2S_IRQFLAGS_PTR_ERR_S 0 +#define I2S_IRQFLAGS_PTR_ERR 0x00000001 +#define I2S_IRQFLAGS_PTR_ERR_BITN 0 +#define I2S_IRQFLAGS_PTR_ERR_M 0x00000001 +#define I2S_IRQFLAGS_PTR_ERR_S 0 //***************************************************************************** // @@ -858,51 +858,51 @@ // // 1: Sets the interrupt of IRQFLAGS.AIF_DMA_IN (unless a auto clear criteria // was given at the same time, in which the set will be ignored) -#define I2S_IRQSET_AIF_DMA_IN 0x00000020 -#define I2S_IRQSET_AIF_DMA_IN_BITN 5 -#define I2S_IRQSET_AIF_DMA_IN_M 0x00000020 -#define I2S_IRQSET_AIF_DMA_IN_S 5 +#define I2S_IRQSET_AIF_DMA_IN 0x00000020 +#define I2S_IRQSET_AIF_DMA_IN_BITN 5 +#define I2S_IRQSET_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQSET_AIF_DMA_IN_S 5 // Field: [4] AIF_DMA_OUT // // 1: Sets the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a auto clear criteria // was given at the same time, in which the set will be ignored) -#define I2S_IRQSET_AIF_DMA_OUT 0x00000010 -#define I2S_IRQSET_AIF_DMA_OUT_BITN 4 -#define I2S_IRQSET_AIF_DMA_OUT_M 0x00000010 -#define I2S_IRQSET_AIF_DMA_OUT_S 4 +#define I2S_IRQSET_AIF_DMA_OUT 0x00000010 +#define I2S_IRQSET_AIF_DMA_OUT_BITN 4 +#define I2S_IRQSET_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQSET_AIF_DMA_OUT_S 4 // Field: [3] WCLK_TIMEOUT // // 1: Sets the interrupt of IRQFLAGS.WCLK_TIMEOUT -#define I2S_IRQSET_WCLK_TIMEOUT 0x00000008 -#define I2S_IRQSET_WCLK_TIMEOUT_BITN 3 -#define I2S_IRQSET_WCLK_TIMEOUT_M 0x00000008 -#define I2S_IRQSET_WCLK_TIMEOUT_S 3 +#define I2S_IRQSET_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQSET_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQSET_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQSET_WCLK_TIMEOUT_S 3 // Field: [2] BUS_ERR // // 1: Sets the interrupt of IRQFLAGS.BUS_ERR -#define I2S_IRQSET_BUS_ERR 0x00000004 -#define I2S_IRQSET_BUS_ERR_BITN 2 -#define I2S_IRQSET_BUS_ERR_M 0x00000004 -#define I2S_IRQSET_BUS_ERR_S 2 +#define I2S_IRQSET_BUS_ERR 0x00000004 +#define I2S_IRQSET_BUS_ERR_BITN 2 +#define I2S_IRQSET_BUS_ERR_M 0x00000004 +#define I2S_IRQSET_BUS_ERR_S 2 // Field: [1] WCLK_ERR // // 1: Sets the interrupt of IRQFLAGS.WCLK_ERR -#define I2S_IRQSET_WCLK_ERR 0x00000002 -#define I2S_IRQSET_WCLK_ERR_BITN 1 -#define I2S_IRQSET_WCLK_ERR_M 0x00000002 -#define I2S_IRQSET_WCLK_ERR_S 1 +#define I2S_IRQSET_WCLK_ERR 0x00000002 +#define I2S_IRQSET_WCLK_ERR_BITN 1 +#define I2S_IRQSET_WCLK_ERR_M 0x00000002 +#define I2S_IRQSET_WCLK_ERR_S 1 // Field: [0] PTR_ERR // // 1: Sets the interrupt of IRQFLAGS.PTR_ERR -#define I2S_IRQSET_PTR_ERR 0x00000001 -#define I2S_IRQSET_PTR_ERR_BITN 0 -#define I2S_IRQSET_PTR_ERR_M 0x00000001 -#define I2S_IRQSET_PTR_ERR_S 0 +#define I2S_IRQSET_PTR_ERR 0x00000001 +#define I2S_IRQSET_PTR_ERR_BITN 0 +#define I2S_IRQSET_PTR_ERR_M 0x00000001 +#define I2S_IRQSET_PTR_ERR_S 0 //***************************************************************************** // @@ -913,55 +913,54 @@ // // 1: Clears the interrupt of IRQFLAGS.AIF_DMA_IN (unless a set criteria was // given at the same time in which the clear will be ignored) -#define I2S_IRQCLR_AIF_DMA_IN 0x00000020 -#define I2S_IRQCLR_AIF_DMA_IN_BITN 5 -#define I2S_IRQCLR_AIF_DMA_IN_M 0x00000020 -#define I2S_IRQCLR_AIF_DMA_IN_S 5 +#define I2S_IRQCLR_AIF_DMA_IN 0x00000020 +#define I2S_IRQCLR_AIF_DMA_IN_BITN 5 +#define I2S_IRQCLR_AIF_DMA_IN_M 0x00000020 +#define I2S_IRQCLR_AIF_DMA_IN_S 5 // Field: [4] AIF_DMA_OUT // // 1: Clears the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a set criteria was // given at the same time in which the clear will be ignored) -#define I2S_IRQCLR_AIF_DMA_OUT 0x00000010 -#define I2S_IRQCLR_AIF_DMA_OUT_BITN 4 -#define I2S_IRQCLR_AIF_DMA_OUT_M 0x00000010 -#define I2S_IRQCLR_AIF_DMA_OUT_S 4 +#define I2S_IRQCLR_AIF_DMA_OUT 0x00000010 +#define I2S_IRQCLR_AIF_DMA_OUT_BITN 4 +#define I2S_IRQCLR_AIF_DMA_OUT_M 0x00000010 +#define I2S_IRQCLR_AIF_DMA_OUT_S 4 // Field: [3] WCLK_TIMEOUT // // 1: Clears the interrupt of IRQFLAGS.WCLK_TIMEOUT (unless a set criteria was // given at the same time in which the clear will be ignored) -#define I2S_IRQCLR_WCLK_TIMEOUT 0x00000008 -#define I2S_IRQCLR_WCLK_TIMEOUT_BITN 3 -#define I2S_IRQCLR_WCLK_TIMEOUT_M 0x00000008 -#define I2S_IRQCLR_WCLK_TIMEOUT_S 3 +#define I2S_IRQCLR_WCLK_TIMEOUT 0x00000008 +#define I2S_IRQCLR_WCLK_TIMEOUT_BITN 3 +#define I2S_IRQCLR_WCLK_TIMEOUT_M 0x00000008 +#define I2S_IRQCLR_WCLK_TIMEOUT_S 3 // Field: [2] BUS_ERR // // 1: Clears the interrupt of IRQFLAGS.BUS_ERR (unless a set criteria was given // at the same time in which the clear will be ignored) -#define I2S_IRQCLR_BUS_ERR 0x00000004 -#define I2S_IRQCLR_BUS_ERR_BITN 2 -#define I2S_IRQCLR_BUS_ERR_M 0x00000004 -#define I2S_IRQCLR_BUS_ERR_S 2 +#define I2S_IRQCLR_BUS_ERR 0x00000004 +#define I2S_IRQCLR_BUS_ERR_BITN 2 +#define I2S_IRQCLR_BUS_ERR_M 0x00000004 +#define I2S_IRQCLR_BUS_ERR_S 2 // Field: [1] WCLK_ERR // // 1: Clears the interrupt of IRQFLAGS.WCLK_ERR (unless a set criteria was // given at the same time in which the clear will be ignored) -#define I2S_IRQCLR_WCLK_ERR 0x00000002 -#define I2S_IRQCLR_WCLK_ERR_BITN 1 -#define I2S_IRQCLR_WCLK_ERR_M 0x00000002 -#define I2S_IRQCLR_WCLK_ERR_S 1 +#define I2S_IRQCLR_WCLK_ERR 0x00000002 +#define I2S_IRQCLR_WCLK_ERR_BITN 1 +#define I2S_IRQCLR_WCLK_ERR_M 0x00000002 +#define I2S_IRQCLR_WCLK_ERR_S 1 // Field: [0] PTR_ERR // // 1: Clears the interrupt of IRQFLAGS.PTR_ERR (unless a set criteria was given // at the same time in which the clear will be ignored) -#define I2S_IRQCLR_PTR_ERR 0x00000001 -#define I2S_IRQCLR_PTR_ERR_BITN 0 -#define I2S_IRQCLR_PTR_ERR_M 0x00000001 -#define I2S_IRQCLR_PTR_ERR_S 0 - +#define I2S_IRQCLR_PTR_ERR 0x00000001 +#define I2S_IRQCLR_PTR_ERR_BITN 0 +#define I2S_IRQCLR_PTR_ERR_M 0x00000001 +#define I2S_IRQCLR_PTR_ERR_S 0 #endif // __I2S__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ints.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ints.h index 8fc6fdd..e494299 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ints.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ints.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_ints_h -* Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) -* Revision: 48904 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_ints_h + * Revised: 2017-05-04 21:56:26 +0200 (Thu, 04 May 2017) + * Revision: 48904 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_INTS_H__ #define __HW_INTS_H__ @@ -42,64 +42,63 @@ // The following are defines for the interrupt assignments. // //***************************************************************************** -#define INT_NMI_FAULT 2 // NMI Fault -#define INT_HARD_FAULT 3 // Hard Fault -#define INT_MEMMANAGE_FAULT 4 // Memory Management (MemManage) +#define INT_NMI_FAULT 2 // NMI Fault +#define INT_HARD_FAULT 3 // Hard Fault +#define INT_MEMMANAGE_FAULT 4 // Memory Management (MemManage) // Fault -#define INT_BUS_FAULT 5 // Bus Fault -#define INT_USAGE_FAULT 6 // Usage Fault -#define INT_SVCALL 11 // Supervisor Call (SVCall) -#define INT_DEBUG 12 // Debug Monitor -#define INT_PENDSV 14 // Pending Service Call (PendSV) -#define INT_SYSTICK 15 // SysTick Interrupt from the +#define INT_BUS_FAULT 5 // Bus Fault +#define INT_USAGE_FAULT 6 // Usage Fault +#define INT_SVCALL 11 // Supervisor Call (SVCall) +#define INT_DEBUG 12 // Debug Monitor +#define INT_PENDSV 14 // Pending Service Call (PendSV) +#define INT_SYSTICK 15 // SysTick Interrupt from the // System Timer in NVIC. -#define INT_AON_GPIO_EDGE 16 // Edge detect event from IOC -#define INT_I2C_IRQ 17 // Interrupt event from I2C -#define INT_RFC_CPE_1 18 // Combined Interrupt for CPE +#define INT_AON_GPIO_EDGE 16 // Edge detect event from IOC +#define INT_I2C_IRQ 17 // Interrupt event from I2C +#define INT_RFC_CPE_1 18 // Combined Interrupt for CPE // Generated events -#define INT_AON_RTC_COMB 20 // Event from AON_RTC -#define INT_UART0_COMB 21 // UART0 combined interrupt -#define INT_AUX_SWEV0 22 // AUX software event 0 -#define INT_SSI0_COMB 23 // SSI0 combined interrupt -#define INT_SSI1_COMB 24 // SSI1 combined interrupt -#define INT_RFC_CPE_0 25 // Combined Interrupt for CPE +#define INT_AON_RTC_COMB 20 // Event from AON_RTC +#define INT_UART0_COMB 21 // UART0 combined interrupt +#define INT_AUX_SWEV0 22 // AUX software event 0 +#define INT_SSI0_COMB 23 // SSI0 combined interrupt +#define INT_SSI1_COMB 24 // SSI1 combined interrupt +#define INT_RFC_CPE_0 25 // Combined Interrupt for CPE // Generated events -#define INT_RFC_HW_COMB 26 // Combined RFC hardware interrupt -#define INT_RFC_CMD_ACK 27 // RFC Doorbell Command +#define INT_RFC_HW_COMB 26 // Combined RFC hardware interrupt +#define INT_RFC_CMD_ACK 27 // RFC Doorbell Command // Acknowledgement Interrupt -#define INT_I2S_IRQ 28 // Interrupt event from I2S -#define INT_AUX_SWEV1 29 // AUX software event 1 -#define INT_WDT_IRQ 30 // Watchdog interrupt event -#define INT_GPT0A 31 // GPT0A interrupt event -#define INT_GPT0B 32 // GPT0B interrupt event -#define INT_GPT1A 33 // GPT1A interrupt event -#define INT_GPT1B 34 // GPT1B interrupt event -#define INT_GPT2A 35 // GPT2A interrupt event -#define INT_GPT2B 36 // GPT2B interrupt event -#define INT_GPT3A 37 // GPT3A interrupt event -#define INT_GPT3B 38 // GPT3B interrupt event -#define INT_CRYPTO_RESULT_AVAIL_IRQ 39 // CRYPTO result available interupt +#define INT_I2S_IRQ 28 // Interrupt event from I2S +#define INT_AUX_SWEV1 29 // AUX software event 1 +#define INT_WDT_IRQ 30 // Watchdog interrupt event +#define INT_GPT0A 31 // GPT0A interrupt event +#define INT_GPT0B 32 // GPT0B interrupt event +#define INT_GPT1A 33 // GPT1A interrupt event +#define INT_GPT1B 34 // GPT1B interrupt event +#define INT_GPT2A 35 // GPT2A interrupt event +#define INT_GPT2B 36 // GPT2B interrupt event +#define INT_GPT3A 37 // GPT3A interrupt event +#define INT_GPT3B 38 // GPT3B interrupt event +#define INT_CRYPTO_RESULT_AVAIL_IRQ 39 // CRYPTO result available interupt // event -#define INT_DMA_DONE_COMB 40 // Combined DMA done -#define INT_DMA_ERR 41 // DMA bus error -#define INT_FLASH 42 // FLASH controller error event -#define INT_SWEV0 43 // Software event 0 -#define INT_AUX_COMB 44 // AUX combined event -#define INT_AON_PROG0 45 // AON programmable event 0 -#define INT_PROG0 46 // Programmable Interrupt 0 -#define INT_AUX_COMPA 47 // AUX Compare A event -#define INT_AUX_ADC_IRQ 48 // AUX ADC interrupt event -#define INT_TRNG_IRQ 49 // TRNG Interrupt event +#define INT_DMA_DONE_COMB 40 // Combined DMA done +#define INT_DMA_ERR 41 // DMA bus error +#define INT_FLASH 42 // FLASH controller error event +#define INT_SWEV0 43 // Software event 0 +#define INT_AUX_COMB 44 // AUX combined event +#define INT_AON_PROG0 45 // AON programmable event 0 +#define INT_PROG0 46 // Programmable Interrupt 0 +#define INT_AUX_COMPA 47 // AUX Compare A event +#define INT_AUX_ADC_IRQ 48 // AUX ADC interrupt event +#define INT_TRNG_IRQ 49 // TRNG Interrupt event //***************************************************************************** // // The following are defines for number of interrupts and priority levels. // //***************************************************************************** -#define NUM_INTERRUPTS 50 // Number of interrupts -#define NUM_PRIORITY_BITS 3 // Number of Priority bits -#define NUM_PRIORITY 8 // Number of priority levels - +#define NUM_INTERRUPTS 50 // Number of interrupts +#define NUM_PRIORITY_BITS 3 // Number of Priority bits +#define NUM_PRIORITY 8 // Number of priority levels //***************************************************************************** // @@ -107,7 +106,7 @@ // //***************************************************************************** -#define INT_AON_AUX_SWEV0 INT_AUX_SWEV0 -#define INT_AON_AUX_SWEV1 INT_AUX_SWEV1 +#define INT_AON_AUX_SWEV0 INT_AUX_SWEV0 +#define INT_AON_AUX_SWEV1 INT_AUX_SWEV1 #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ioc.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ioc.h index 16a800a..edf2a14 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ioc.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ioc.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_ioc_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_ioc_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_IOC_H__ #define __HW_IOC_H__ @@ -44,100 +44,100 @@ // //***************************************************************************** // Configuration of DIO0 -#define IOC_O_IOCFG0 0x00000000 +#define IOC_O_IOCFG0 0x00000000 // Configuration of DIO1 -#define IOC_O_IOCFG1 0x00000004 +#define IOC_O_IOCFG1 0x00000004 // Configuration of DIO2 -#define IOC_O_IOCFG2 0x00000008 +#define IOC_O_IOCFG2 0x00000008 // Configuration of DIO3 -#define IOC_O_IOCFG3 0x0000000C +#define IOC_O_IOCFG3 0x0000000C // Configuration of DIO4 -#define IOC_O_IOCFG4 0x00000010 +#define IOC_O_IOCFG4 0x00000010 // Configuration of DIO5 -#define IOC_O_IOCFG5 0x00000014 +#define IOC_O_IOCFG5 0x00000014 // Configuration of DIO6 -#define IOC_O_IOCFG6 0x00000018 +#define IOC_O_IOCFG6 0x00000018 // Configuration of DIO7 -#define IOC_O_IOCFG7 0x0000001C +#define IOC_O_IOCFG7 0x0000001C // Configuration of DIO8 -#define IOC_O_IOCFG8 0x00000020 +#define IOC_O_IOCFG8 0x00000020 // Configuration of DIO9 -#define IOC_O_IOCFG9 0x00000024 +#define IOC_O_IOCFG9 0x00000024 // Configuration of DIO10 -#define IOC_O_IOCFG10 0x00000028 +#define IOC_O_IOCFG10 0x00000028 // Configuration of DIO11 -#define IOC_O_IOCFG11 0x0000002C +#define IOC_O_IOCFG11 0x0000002C // Configuration of DIO12 -#define IOC_O_IOCFG12 0x00000030 +#define IOC_O_IOCFG12 0x00000030 // Configuration of DIO13 -#define IOC_O_IOCFG13 0x00000034 +#define IOC_O_IOCFG13 0x00000034 // Configuration of DIO14 -#define IOC_O_IOCFG14 0x00000038 +#define IOC_O_IOCFG14 0x00000038 // Configuration of DIO15 -#define IOC_O_IOCFG15 0x0000003C +#define IOC_O_IOCFG15 0x0000003C // Configuration of DIO16 -#define IOC_O_IOCFG16 0x00000040 +#define IOC_O_IOCFG16 0x00000040 // Configuration of DIO17 -#define IOC_O_IOCFG17 0x00000044 +#define IOC_O_IOCFG17 0x00000044 // Configuration of DIO18 -#define IOC_O_IOCFG18 0x00000048 +#define IOC_O_IOCFG18 0x00000048 // Configuration of DIO19 -#define IOC_O_IOCFG19 0x0000004C +#define IOC_O_IOCFG19 0x0000004C // Configuration of DIO20 -#define IOC_O_IOCFG20 0x00000050 +#define IOC_O_IOCFG20 0x00000050 // Configuration of DIO21 -#define IOC_O_IOCFG21 0x00000054 +#define IOC_O_IOCFG21 0x00000054 // Configuration of DIO22 -#define IOC_O_IOCFG22 0x00000058 +#define IOC_O_IOCFG22 0x00000058 // Configuration of DIO23 -#define IOC_O_IOCFG23 0x0000005C +#define IOC_O_IOCFG23 0x0000005C // Configuration of DIO24 -#define IOC_O_IOCFG24 0x00000060 +#define IOC_O_IOCFG24 0x00000060 // Configuration of DIO25 -#define IOC_O_IOCFG25 0x00000064 +#define IOC_O_IOCFG25 0x00000064 // Configuration of DIO26 -#define IOC_O_IOCFG26 0x00000068 +#define IOC_O_IOCFG26 0x00000068 // Configuration of DIO27 -#define IOC_O_IOCFG27 0x0000006C +#define IOC_O_IOCFG27 0x0000006C // Configuration of DIO28 -#define IOC_O_IOCFG28 0x00000070 +#define IOC_O_IOCFG28 0x00000070 // Configuration of DIO29 -#define IOC_O_IOCFG29 0x00000074 +#define IOC_O_IOCFG29 0x00000074 // Configuration of DIO30 -#define IOC_O_IOCFG30 0x00000078 +#define IOC_O_IOCFG30 0x00000078 // Configuration of DIO31 -#define IOC_O_IOCFG31 0x0000007C +#define IOC_O_IOCFG31 0x0000007C //***************************************************************************** // @@ -148,10 +148,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG0_HYST_EN 0x40000000 -#define IOC_IOCFG0_HYST_EN_BITN 30 -#define IOC_IOCFG0_HYST_EN_M 0x40000000 -#define IOC_IOCFG0_HYST_EN_S 30 +#define IOC_IOCFG0_HYST_EN 0x40000000 +#define IOC_IOCFG0_HYST_EN_BITN 30 +#define IOC_IOCFG0_HYST_EN_M 0x40000000 +#define IOC_IOCFG0_HYST_EN_S 30 // Field: [29] IE // @@ -160,10 +160,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG0_IE 0x20000000 -#define IOC_IOCFG0_IE_BITN 29 -#define IOC_IOCFG0_IE_M 0x20000000 -#define IOC_IOCFG0_IE_S 29 +#define IOC_IOCFG0_IE 0x20000000 +#define IOC_IOCFG0_IE_BITN 29 +#define IOC_IOCFG0_IE_M 0x20000000 +#define IOC_IOCFG0_IE_S 29 // Field: [28:27] WU_CFG // @@ -185,9 +185,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG0_WU_CFG_W 2 -#define IOC_IOCFG0_WU_CFG_M 0x18000000 -#define IOC_IOCFG0_WU_CFG_S 27 +#define IOC_IOCFG0_WU_CFG_W 2 +#define IOC_IOCFG0_WU_CFG_M 0x18000000 +#define IOC_IOCFG0_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -208,25 +208,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG0_IOMODE_W 3 -#define IOC_IOCFG0_IOMODE_M 0x07000000 -#define IOC_IOCFG0_IOMODE_S 24 -#define IOC_IOCFG0_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG0_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG0_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG0_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG0_IOMODE_INV 0x01000000 -#define IOC_IOCFG0_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG0_IOMODE_W 3 +#define IOC_IOCFG0_IOMODE_M 0x07000000 +#define IOC_IOCFG0_IOMODE_S 24 +#define IOC_IOCFG0_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG0_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG0_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG0_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG0_IOMODE_INV 0x01000000 +#define IOC_IOCFG0_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG0_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG0_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG0_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG0_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG0_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG0_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG0_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG0_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -236,13 +236,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG0_EDGE_DET_W 2 -#define IOC_IOCFG0_EDGE_DET_M 0x00030000 -#define IOC_IOCFG0_EDGE_DET_S 16 -#define IOC_IOCFG0_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG0_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG0_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG0_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG0_EDGE_DET_W 2 +#define IOC_IOCFG0_EDGE_DET_M 0x00030000 +#define IOC_IOCFG0_EDGE_DET_S 16 +#define IOC_IOCFG0_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG0_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG0_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG0_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -251,21 +251,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG0_PULL_CTL_W 2 -#define IOC_IOCFG0_PULL_CTL_M 0x00006000 -#define IOC_IOCFG0_PULL_CTL_S 13 -#define IOC_IOCFG0_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG0_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG0_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG0_PULL_CTL_W 2 +#define IOC_IOCFG0_PULL_CTL_M 0x00006000 +#define IOC_IOCFG0_PULL_CTL_S 13 +#define IOC_IOCFG0_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG0_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG0_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG0_SLEW_RED 0x00001000 -#define IOC_IOCFG0_SLEW_RED_BITN 12 -#define IOC_IOCFG0_SLEW_RED_M 0x00001000 -#define IOC_IOCFG0_SLEW_RED_S 12 +#define IOC_IOCFG0_SLEW_RED 0x00001000 +#define IOC_IOCFG0_SLEW_RED_BITN 12 +#define IOC_IOCFG0_SLEW_RED_M 0x00001000 +#define IOC_IOCFG0_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -278,12 +278,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG0_IOCURR_W 2 -#define IOC_IOCFG0_IOCURR_M 0x00000C00 -#define IOC_IOCFG0_IOCURR_S 10 -#define IOC_IOCFG0_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG0_IOCURR_4MA 0x00000400 -#define IOC_IOCFG0_IOCURR_2MA 0x00000000 +#define IOC_IOCFG0_IOCURR_W 2 +#define IOC_IOCFG0_IOCURR_M 0x00000C00 +#define IOC_IOCFG0_IOCURR_S 10 +#define IOC_IOCFG0_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG0_IOCURR_4MA 0x00000400 +#define IOC_IOCFG0_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -302,13 +302,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG0_IOSTR_W 2 -#define IOC_IOCFG0_IOSTR_M 0x00000300 -#define IOC_IOCFG0_IOSTR_S 8 -#define IOC_IOCFG0_IOSTR_MAX 0x00000300 -#define IOC_IOCFG0_IOSTR_MED 0x00000200 -#define IOC_IOCFG0_IOSTR_MIN 0x00000100 -#define IOC_IOCFG0_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG0_IOSTR_W 2 +#define IOC_IOCFG0_IOSTR_M 0x00000300 +#define IOC_IOCFG0_IOSTR_S 8 +#define IOC_IOCFG0_IOSTR_MAX 0x00000300 +#define IOC_IOCFG0_IOSTR_MED 0x00000200 +#define IOC_IOCFG0_IOSTR_MIN 0x00000100 +#define IOC_IOCFG0_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -396,51 +396,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG0_PORT_ID_W 6 -#define IOC_IOCFG0_PORT_ID_M 0x0000003F -#define IOC_IOCFG0_PORT_ID_S 0 -#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG0_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG0_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG0_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG0_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG0_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG0_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG0_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG0_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG0_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG0_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG0_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG0_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG0_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG0_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG0_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG0_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG0_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG0_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG0_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG0_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG0_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG0_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG0_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG0_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG0_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG0_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG0_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG0_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG0_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG0_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG0_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG0_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG0_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG0_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG0_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG0_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG0_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG0_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG0_PORT_ID_W 6 +#define IOC_IOCFG0_PORT_ID_M 0x0000003F +#define IOC_IOCFG0_PORT_ID_S 0 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG0_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG0_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG0_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG0_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG0_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG0_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG0_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG0_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG0_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG0_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG0_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG0_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG0_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG0_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG0_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG0_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG0_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG0_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG0_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG0_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG0_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG0_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG0_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG0_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG0_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG0_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG0_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG0_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG0_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG0_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG0_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG0_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG0_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG0_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG0_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG0_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -451,10 +451,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG1_HYST_EN 0x40000000 -#define IOC_IOCFG1_HYST_EN_BITN 30 -#define IOC_IOCFG1_HYST_EN_M 0x40000000 -#define IOC_IOCFG1_HYST_EN_S 30 +#define IOC_IOCFG1_HYST_EN 0x40000000 +#define IOC_IOCFG1_HYST_EN_BITN 30 +#define IOC_IOCFG1_HYST_EN_M 0x40000000 +#define IOC_IOCFG1_HYST_EN_S 30 // Field: [29] IE // @@ -463,10 +463,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG1_IE 0x20000000 -#define IOC_IOCFG1_IE_BITN 29 -#define IOC_IOCFG1_IE_M 0x20000000 -#define IOC_IOCFG1_IE_S 29 +#define IOC_IOCFG1_IE 0x20000000 +#define IOC_IOCFG1_IE_BITN 29 +#define IOC_IOCFG1_IE_M 0x20000000 +#define IOC_IOCFG1_IE_S 29 // Field: [28:27] WU_CFG // @@ -488,9 +488,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG1_WU_CFG_W 2 -#define IOC_IOCFG1_WU_CFG_M 0x18000000 -#define IOC_IOCFG1_WU_CFG_S 27 +#define IOC_IOCFG1_WU_CFG_W 2 +#define IOC_IOCFG1_WU_CFG_M 0x18000000 +#define IOC_IOCFG1_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -511,25 +511,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG1_IOMODE_W 3 -#define IOC_IOCFG1_IOMODE_M 0x07000000 -#define IOC_IOCFG1_IOMODE_S 24 -#define IOC_IOCFG1_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG1_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG1_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG1_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG1_IOMODE_INV 0x01000000 -#define IOC_IOCFG1_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG1_IOMODE_W 3 +#define IOC_IOCFG1_IOMODE_M 0x07000000 +#define IOC_IOCFG1_IOMODE_S 24 +#define IOC_IOCFG1_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG1_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG1_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG1_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG1_IOMODE_INV 0x01000000 +#define IOC_IOCFG1_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG1_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG1_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG1_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG1_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG1_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG1_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG1_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG1_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -539,13 +539,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG1_EDGE_DET_W 2 -#define IOC_IOCFG1_EDGE_DET_M 0x00030000 -#define IOC_IOCFG1_EDGE_DET_S 16 -#define IOC_IOCFG1_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG1_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG1_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG1_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG1_EDGE_DET_W 2 +#define IOC_IOCFG1_EDGE_DET_M 0x00030000 +#define IOC_IOCFG1_EDGE_DET_S 16 +#define IOC_IOCFG1_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG1_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG1_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG1_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -554,21 +554,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG1_PULL_CTL_W 2 -#define IOC_IOCFG1_PULL_CTL_M 0x00006000 -#define IOC_IOCFG1_PULL_CTL_S 13 -#define IOC_IOCFG1_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG1_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG1_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG1_PULL_CTL_W 2 +#define IOC_IOCFG1_PULL_CTL_M 0x00006000 +#define IOC_IOCFG1_PULL_CTL_S 13 +#define IOC_IOCFG1_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG1_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG1_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG1_SLEW_RED 0x00001000 -#define IOC_IOCFG1_SLEW_RED_BITN 12 -#define IOC_IOCFG1_SLEW_RED_M 0x00001000 -#define IOC_IOCFG1_SLEW_RED_S 12 +#define IOC_IOCFG1_SLEW_RED 0x00001000 +#define IOC_IOCFG1_SLEW_RED_BITN 12 +#define IOC_IOCFG1_SLEW_RED_M 0x00001000 +#define IOC_IOCFG1_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -581,12 +581,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG1_IOCURR_W 2 -#define IOC_IOCFG1_IOCURR_M 0x00000C00 -#define IOC_IOCFG1_IOCURR_S 10 -#define IOC_IOCFG1_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG1_IOCURR_4MA 0x00000400 -#define IOC_IOCFG1_IOCURR_2MA 0x00000000 +#define IOC_IOCFG1_IOCURR_W 2 +#define IOC_IOCFG1_IOCURR_M 0x00000C00 +#define IOC_IOCFG1_IOCURR_S 10 +#define IOC_IOCFG1_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG1_IOCURR_4MA 0x00000400 +#define IOC_IOCFG1_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -605,13 +605,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG1_IOSTR_W 2 -#define IOC_IOCFG1_IOSTR_M 0x00000300 -#define IOC_IOCFG1_IOSTR_S 8 -#define IOC_IOCFG1_IOSTR_MAX 0x00000300 -#define IOC_IOCFG1_IOSTR_MED 0x00000200 -#define IOC_IOCFG1_IOSTR_MIN 0x00000100 -#define IOC_IOCFG1_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG1_IOSTR_W 2 +#define IOC_IOCFG1_IOSTR_M 0x00000300 +#define IOC_IOCFG1_IOSTR_S 8 +#define IOC_IOCFG1_IOSTR_MAX 0x00000300 +#define IOC_IOCFG1_IOSTR_MED 0x00000200 +#define IOC_IOCFG1_IOSTR_MIN 0x00000100 +#define IOC_IOCFG1_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -699,51 +699,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG1_PORT_ID_W 6 -#define IOC_IOCFG1_PORT_ID_M 0x0000003F -#define IOC_IOCFG1_PORT_ID_S 0 -#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG1_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG1_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG1_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG1_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG1_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG1_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG1_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG1_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG1_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG1_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG1_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG1_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG1_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG1_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG1_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG1_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG1_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG1_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG1_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG1_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG1_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG1_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG1_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG1_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG1_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG1_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG1_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG1_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG1_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG1_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG1_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG1_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG1_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG1_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG1_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG1_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG1_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG1_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG1_PORT_ID_W 6 +#define IOC_IOCFG1_PORT_ID_M 0x0000003F +#define IOC_IOCFG1_PORT_ID_S 0 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG1_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG1_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG1_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG1_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG1_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG1_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG1_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG1_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG1_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG1_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG1_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG1_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG1_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG1_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG1_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG1_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG1_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG1_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG1_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG1_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG1_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG1_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG1_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG1_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG1_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG1_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG1_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG1_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG1_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG1_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG1_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG1_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG1_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG1_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG1_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG1_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -754,10 +754,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG2_HYST_EN 0x40000000 -#define IOC_IOCFG2_HYST_EN_BITN 30 -#define IOC_IOCFG2_HYST_EN_M 0x40000000 -#define IOC_IOCFG2_HYST_EN_S 30 +#define IOC_IOCFG2_HYST_EN 0x40000000 +#define IOC_IOCFG2_HYST_EN_BITN 30 +#define IOC_IOCFG2_HYST_EN_M 0x40000000 +#define IOC_IOCFG2_HYST_EN_S 30 // Field: [29] IE // @@ -766,10 +766,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG2_IE 0x20000000 -#define IOC_IOCFG2_IE_BITN 29 -#define IOC_IOCFG2_IE_M 0x20000000 -#define IOC_IOCFG2_IE_S 29 +#define IOC_IOCFG2_IE 0x20000000 +#define IOC_IOCFG2_IE_BITN 29 +#define IOC_IOCFG2_IE_M 0x20000000 +#define IOC_IOCFG2_IE_S 29 // Field: [28:27] WU_CFG // @@ -791,9 +791,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG2_WU_CFG_W 2 -#define IOC_IOCFG2_WU_CFG_M 0x18000000 -#define IOC_IOCFG2_WU_CFG_S 27 +#define IOC_IOCFG2_WU_CFG_W 2 +#define IOC_IOCFG2_WU_CFG_M 0x18000000 +#define IOC_IOCFG2_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -814,25 +814,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG2_IOMODE_W 3 -#define IOC_IOCFG2_IOMODE_M 0x07000000 -#define IOC_IOCFG2_IOMODE_S 24 -#define IOC_IOCFG2_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG2_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG2_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG2_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG2_IOMODE_INV 0x01000000 -#define IOC_IOCFG2_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG2_IOMODE_W 3 +#define IOC_IOCFG2_IOMODE_M 0x07000000 +#define IOC_IOCFG2_IOMODE_S 24 +#define IOC_IOCFG2_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG2_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG2_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG2_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG2_IOMODE_INV 0x01000000 +#define IOC_IOCFG2_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG2_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG2_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG2_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG2_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG2_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG2_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG2_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG2_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -842,13 +842,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG2_EDGE_DET_W 2 -#define IOC_IOCFG2_EDGE_DET_M 0x00030000 -#define IOC_IOCFG2_EDGE_DET_S 16 -#define IOC_IOCFG2_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG2_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG2_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG2_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG2_EDGE_DET_W 2 +#define IOC_IOCFG2_EDGE_DET_M 0x00030000 +#define IOC_IOCFG2_EDGE_DET_S 16 +#define IOC_IOCFG2_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG2_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG2_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG2_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -857,21 +857,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG2_PULL_CTL_W 2 -#define IOC_IOCFG2_PULL_CTL_M 0x00006000 -#define IOC_IOCFG2_PULL_CTL_S 13 -#define IOC_IOCFG2_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG2_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG2_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG2_PULL_CTL_W 2 +#define IOC_IOCFG2_PULL_CTL_M 0x00006000 +#define IOC_IOCFG2_PULL_CTL_S 13 +#define IOC_IOCFG2_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG2_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG2_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG2_SLEW_RED 0x00001000 -#define IOC_IOCFG2_SLEW_RED_BITN 12 -#define IOC_IOCFG2_SLEW_RED_M 0x00001000 -#define IOC_IOCFG2_SLEW_RED_S 12 +#define IOC_IOCFG2_SLEW_RED 0x00001000 +#define IOC_IOCFG2_SLEW_RED_BITN 12 +#define IOC_IOCFG2_SLEW_RED_M 0x00001000 +#define IOC_IOCFG2_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -884,12 +884,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG2_IOCURR_W 2 -#define IOC_IOCFG2_IOCURR_M 0x00000C00 -#define IOC_IOCFG2_IOCURR_S 10 -#define IOC_IOCFG2_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG2_IOCURR_4MA 0x00000400 -#define IOC_IOCFG2_IOCURR_2MA 0x00000000 +#define IOC_IOCFG2_IOCURR_W 2 +#define IOC_IOCFG2_IOCURR_M 0x00000C00 +#define IOC_IOCFG2_IOCURR_S 10 +#define IOC_IOCFG2_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG2_IOCURR_4MA 0x00000400 +#define IOC_IOCFG2_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -908,13 +908,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG2_IOSTR_W 2 -#define IOC_IOCFG2_IOSTR_M 0x00000300 -#define IOC_IOCFG2_IOSTR_S 8 -#define IOC_IOCFG2_IOSTR_MAX 0x00000300 -#define IOC_IOCFG2_IOSTR_MED 0x00000200 -#define IOC_IOCFG2_IOSTR_MIN 0x00000100 -#define IOC_IOCFG2_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG2_IOSTR_W 2 +#define IOC_IOCFG2_IOSTR_M 0x00000300 +#define IOC_IOCFG2_IOSTR_S 8 +#define IOC_IOCFG2_IOSTR_MAX 0x00000300 +#define IOC_IOCFG2_IOSTR_MED 0x00000200 +#define IOC_IOCFG2_IOSTR_MIN 0x00000100 +#define IOC_IOCFG2_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -1002,51 +1002,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG2_PORT_ID_W 6 -#define IOC_IOCFG2_PORT_ID_M 0x0000003F -#define IOC_IOCFG2_PORT_ID_S 0 -#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG2_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG2_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG2_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG2_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG2_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG2_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG2_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG2_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG2_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG2_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG2_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG2_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG2_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG2_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG2_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG2_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG2_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG2_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG2_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG2_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG2_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG2_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG2_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG2_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG2_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG2_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG2_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG2_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG2_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG2_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG2_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG2_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG2_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG2_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG2_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG2_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG2_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG2_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG2_PORT_ID_W 6 +#define IOC_IOCFG2_PORT_ID_M 0x0000003F +#define IOC_IOCFG2_PORT_ID_S 0 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG2_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG2_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG2_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG2_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG2_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG2_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG2_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG2_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG2_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG2_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG2_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG2_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG2_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG2_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG2_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG2_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG2_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG2_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG2_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG2_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG2_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG2_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG2_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG2_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG2_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG2_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG2_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG2_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG2_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG2_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG2_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG2_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG2_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG2_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG2_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG2_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -1057,10 +1057,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG3_HYST_EN 0x40000000 -#define IOC_IOCFG3_HYST_EN_BITN 30 -#define IOC_IOCFG3_HYST_EN_M 0x40000000 -#define IOC_IOCFG3_HYST_EN_S 30 +#define IOC_IOCFG3_HYST_EN 0x40000000 +#define IOC_IOCFG3_HYST_EN_BITN 30 +#define IOC_IOCFG3_HYST_EN_M 0x40000000 +#define IOC_IOCFG3_HYST_EN_S 30 // Field: [29] IE // @@ -1069,10 +1069,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG3_IE 0x20000000 -#define IOC_IOCFG3_IE_BITN 29 -#define IOC_IOCFG3_IE_M 0x20000000 -#define IOC_IOCFG3_IE_S 29 +#define IOC_IOCFG3_IE 0x20000000 +#define IOC_IOCFG3_IE_BITN 29 +#define IOC_IOCFG3_IE_M 0x20000000 +#define IOC_IOCFG3_IE_S 29 // Field: [28:27] WU_CFG // @@ -1094,9 +1094,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG3_WU_CFG_W 2 -#define IOC_IOCFG3_WU_CFG_M 0x18000000 -#define IOC_IOCFG3_WU_CFG_S 27 +#define IOC_IOCFG3_WU_CFG_W 2 +#define IOC_IOCFG3_WU_CFG_M 0x18000000 +#define IOC_IOCFG3_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -1117,25 +1117,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG3_IOMODE_W 3 -#define IOC_IOCFG3_IOMODE_M 0x07000000 -#define IOC_IOCFG3_IOMODE_S 24 -#define IOC_IOCFG3_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG3_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG3_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG3_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG3_IOMODE_INV 0x01000000 -#define IOC_IOCFG3_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG3_IOMODE_W 3 +#define IOC_IOCFG3_IOMODE_M 0x07000000 +#define IOC_IOCFG3_IOMODE_S 24 +#define IOC_IOCFG3_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG3_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG3_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG3_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG3_IOMODE_INV 0x01000000 +#define IOC_IOCFG3_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG3_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG3_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG3_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG3_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG3_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG3_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG3_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG3_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -1145,13 +1145,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG3_EDGE_DET_W 2 -#define IOC_IOCFG3_EDGE_DET_M 0x00030000 -#define IOC_IOCFG3_EDGE_DET_S 16 -#define IOC_IOCFG3_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG3_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG3_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG3_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG3_EDGE_DET_W 2 +#define IOC_IOCFG3_EDGE_DET_M 0x00030000 +#define IOC_IOCFG3_EDGE_DET_S 16 +#define IOC_IOCFG3_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG3_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG3_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG3_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -1160,21 +1160,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG3_PULL_CTL_W 2 -#define IOC_IOCFG3_PULL_CTL_M 0x00006000 -#define IOC_IOCFG3_PULL_CTL_S 13 -#define IOC_IOCFG3_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG3_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG3_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG3_PULL_CTL_W 2 +#define IOC_IOCFG3_PULL_CTL_M 0x00006000 +#define IOC_IOCFG3_PULL_CTL_S 13 +#define IOC_IOCFG3_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG3_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG3_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG3_SLEW_RED 0x00001000 -#define IOC_IOCFG3_SLEW_RED_BITN 12 -#define IOC_IOCFG3_SLEW_RED_M 0x00001000 -#define IOC_IOCFG3_SLEW_RED_S 12 +#define IOC_IOCFG3_SLEW_RED 0x00001000 +#define IOC_IOCFG3_SLEW_RED_BITN 12 +#define IOC_IOCFG3_SLEW_RED_M 0x00001000 +#define IOC_IOCFG3_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -1187,12 +1187,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG3_IOCURR_W 2 -#define IOC_IOCFG3_IOCURR_M 0x00000C00 -#define IOC_IOCFG3_IOCURR_S 10 -#define IOC_IOCFG3_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG3_IOCURR_4MA 0x00000400 -#define IOC_IOCFG3_IOCURR_2MA 0x00000000 +#define IOC_IOCFG3_IOCURR_W 2 +#define IOC_IOCFG3_IOCURR_M 0x00000C00 +#define IOC_IOCFG3_IOCURR_S 10 +#define IOC_IOCFG3_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG3_IOCURR_4MA 0x00000400 +#define IOC_IOCFG3_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -1211,13 +1211,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG3_IOSTR_W 2 -#define IOC_IOCFG3_IOSTR_M 0x00000300 -#define IOC_IOCFG3_IOSTR_S 8 -#define IOC_IOCFG3_IOSTR_MAX 0x00000300 -#define IOC_IOCFG3_IOSTR_MED 0x00000200 -#define IOC_IOCFG3_IOSTR_MIN 0x00000100 -#define IOC_IOCFG3_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG3_IOSTR_W 2 +#define IOC_IOCFG3_IOSTR_M 0x00000300 +#define IOC_IOCFG3_IOSTR_S 8 +#define IOC_IOCFG3_IOSTR_MAX 0x00000300 +#define IOC_IOCFG3_IOSTR_MED 0x00000200 +#define IOC_IOCFG3_IOSTR_MIN 0x00000100 +#define IOC_IOCFG3_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -1305,51 +1305,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG3_PORT_ID_W 6 -#define IOC_IOCFG3_PORT_ID_M 0x0000003F -#define IOC_IOCFG3_PORT_ID_S 0 -#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG3_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG3_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG3_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG3_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG3_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG3_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG3_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG3_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG3_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG3_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG3_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG3_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG3_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG3_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG3_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG3_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG3_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG3_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG3_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG3_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG3_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG3_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG3_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG3_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG3_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG3_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG3_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG3_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG3_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG3_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG3_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG3_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG3_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG3_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG3_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG3_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG3_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG3_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG3_PORT_ID_W 6 +#define IOC_IOCFG3_PORT_ID_M 0x0000003F +#define IOC_IOCFG3_PORT_ID_S 0 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG3_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG3_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG3_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG3_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG3_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG3_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG3_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG3_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG3_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG3_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG3_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG3_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG3_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG3_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG3_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG3_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG3_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG3_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG3_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG3_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG3_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG3_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG3_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG3_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG3_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG3_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG3_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG3_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG3_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG3_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG3_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG3_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG3_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG3_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG3_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG3_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -1360,10 +1360,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG4_HYST_EN 0x40000000 -#define IOC_IOCFG4_HYST_EN_BITN 30 -#define IOC_IOCFG4_HYST_EN_M 0x40000000 -#define IOC_IOCFG4_HYST_EN_S 30 +#define IOC_IOCFG4_HYST_EN 0x40000000 +#define IOC_IOCFG4_HYST_EN_BITN 30 +#define IOC_IOCFG4_HYST_EN_M 0x40000000 +#define IOC_IOCFG4_HYST_EN_S 30 // Field: [29] IE // @@ -1372,10 +1372,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG4_IE 0x20000000 -#define IOC_IOCFG4_IE_BITN 29 -#define IOC_IOCFG4_IE_M 0x20000000 -#define IOC_IOCFG4_IE_S 29 +#define IOC_IOCFG4_IE 0x20000000 +#define IOC_IOCFG4_IE_BITN 29 +#define IOC_IOCFG4_IE_M 0x20000000 +#define IOC_IOCFG4_IE_S 29 // Field: [28:27] WU_CFG // @@ -1397,9 +1397,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG4_WU_CFG_W 2 -#define IOC_IOCFG4_WU_CFG_M 0x18000000 -#define IOC_IOCFG4_WU_CFG_S 27 +#define IOC_IOCFG4_WU_CFG_W 2 +#define IOC_IOCFG4_WU_CFG_M 0x18000000 +#define IOC_IOCFG4_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -1420,25 +1420,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG4_IOMODE_W 3 -#define IOC_IOCFG4_IOMODE_M 0x07000000 -#define IOC_IOCFG4_IOMODE_S 24 -#define IOC_IOCFG4_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG4_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG4_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG4_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG4_IOMODE_INV 0x01000000 -#define IOC_IOCFG4_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG4_IOMODE_W 3 +#define IOC_IOCFG4_IOMODE_M 0x07000000 +#define IOC_IOCFG4_IOMODE_S 24 +#define IOC_IOCFG4_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG4_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG4_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG4_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG4_IOMODE_INV 0x01000000 +#define IOC_IOCFG4_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG4_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG4_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG4_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG4_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG4_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG4_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG4_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG4_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -1448,13 +1448,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG4_EDGE_DET_W 2 -#define IOC_IOCFG4_EDGE_DET_M 0x00030000 -#define IOC_IOCFG4_EDGE_DET_S 16 -#define IOC_IOCFG4_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG4_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG4_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG4_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG4_EDGE_DET_W 2 +#define IOC_IOCFG4_EDGE_DET_M 0x00030000 +#define IOC_IOCFG4_EDGE_DET_S 16 +#define IOC_IOCFG4_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG4_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG4_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG4_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -1463,21 +1463,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG4_PULL_CTL_W 2 -#define IOC_IOCFG4_PULL_CTL_M 0x00006000 -#define IOC_IOCFG4_PULL_CTL_S 13 -#define IOC_IOCFG4_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG4_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG4_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG4_PULL_CTL_W 2 +#define IOC_IOCFG4_PULL_CTL_M 0x00006000 +#define IOC_IOCFG4_PULL_CTL_S 13 +#define IOC_IOCFG4_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG4_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG4_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG4_SLEW_RED 0x00001000 -#define IOC_IOCFG4_SLEW_RED_BITN 12 -#define IOC_IOCFG4_SLEW_RED_M 0x00001000 -#define IOC_IOCFG4_SLEW_RED_S 12 +#define IOC_IOCFG4_SLEW_RED 0x00001000 +#define IOC_IOCFG4_SLEW_RED_BITN 12 +#define IOC_IOCFG4_SLEW_RED_M 0x00001000 +#define IOC_IOCFG4_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -1490,12 +1490,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG4_IOCURR_W 2 -#define IOC_IOCFG4_IOCURR_M 0x00000C00 -#define IOC_IOCFG4_IOCURR_S 10 -#define IOC_IOCFG4_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG4_IOCURR_4MA 0x00000400 -#define IOC_IOCFG4_IOCURR_2MA 0x00000000 +#define IOC_IOCFG4_IOCURR_W 2 +#define IOC_IOCFG4_IOCURR_M 0x00000C00 +#define IOC_IOCFG4_IOCURR_S 10 +#define IOC_IOCFG4_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG4_IOCURR_4MA 0x00000400 +#define IOC_IOCFG4_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -1514,13 +1514,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG4_IOSTR_W 2 -#define IOC_IOCFG4_IOSTR_M 0x00000300 -#define IOC_IOCFG4_IOSTR_S 8 -#define IOC_IOCFG4_IOSTR_MAX 0x00000300 -#define IOC_IOCFG4_IOSTR_MED 0x00000200 -#define IOC_IOCFG4_IOSTR_MIN 0x00000100 -#define IOC_IOCFG4_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG4_IOSTR_W 2 +#define IOC_IOCFG4_IOSTR_M 0x00000300 +#define IOC_IOCFG4_IOSTR_S 8 +#define IOC_IOCFG4_IOSTR_MAX 0x00000300 +#define IOC_IOCFG4_IOSTR_MED 0x00000200 +#define IOC_IOCFG4_IOSTR_MIN 0x00000100 +#define IOC_IOCFG4_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -1608,51 +1608,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG4_PORT_ID_W 6 -#define IOC_IOCFG4_PORT_ID_M 0x0000003F -#define IOC_IOCFG4_PORT_ID_S 0 -#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG4_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG4_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG4_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG4_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG4_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG4_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG4_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG4_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG4_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG4_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG4_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG4_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG4_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG4_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG4_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG4_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG4_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG4_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG4_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG4_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG4_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG4_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG4_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG4_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG4_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG4_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG4_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG4_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG4_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG4_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG4_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG4_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG4_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG4_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG4_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG4_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG4_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG4_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG4_PORT_ID_W 6 +#define IOC_IOCFG4_PORT_ID_M 0x0000003F +#define IOC_IOCFG4_PORT_ID_S 0 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG4_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG4_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG4_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG4_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG4_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG4_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG4_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG4_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG4_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG4_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG4_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG4_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG4_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG4_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG4_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG4_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG4_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG4_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG4_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG4_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG4_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG4_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG4_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG4_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG4_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG4_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG4_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG4_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG4_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG4_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG4_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG4_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG4_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG4_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG4_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG4_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -1663,10 +1663,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG5_HYST_EN 0x40000000 -#define IOC_IOCFG5_HYST_EN_BITN 30 -#define IOC_IOCFG5_HYST_EN_M 0x40000000 -#define IOC_IOCFG5_HYST_EN_S 30 +#define IOC_IOCFG5_HYST_EN 0x40000000 +#define IOC_IOCFG5_HYST_EN_BITN 30 +#define IOC_IOCFG5_HYST_EN_M 0x40000000 +#define IOC_IOCFG5_HYST_EN_S 30 // Field: [29] IE // @@ -1675,10 +1675,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG5_IE 0x20000000 -#define IOC_IOCFG5_IE_BITN 29 -#define IOC_IOCFG5_IE_M 0x20000000 -#define IOC_IOCFG5_IE_S 29 +#define IOC_IOCFG5_IE 0x20000000 +#define IOC_IOCFG5_IE_BITN 29 +#define IOC_IOCFG5_IE_M 0x20000000 +#define IOC_IOCFG5_IE_S 29 // Field: [28:27] WU_CFG // @@ -1700,9 +1700,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG5_WU_CFG_W 2 -#define IOC_IOCFG5_WU_CFG_M 0x18000000 -#define IOC_IOCFG5_WU_CFG_S 27 +#define IOC_IOCFG5_WU_CFG_W 2 +#define IOC_IOCFG5_WU_CFG_M 0x18000000 +#define IOC_IOCFG5_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -1723,25 +1723,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG5_IOMODE_W 3 -#define IOC_IOCFG5_IOMODE_M 0x07000000 -#define IOC_IOCFG5_IOMODE_S 24 -#define IOC_IOCFG5_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG5_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG5_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG5_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG5_IOMODE_INV 0x01000000 -#define IOC_IOCFG5_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG5_IOMODE_W 3 +#define IOC_IOCFG5_IOMODE_M 0x07000000 +#define IOC_IOCFG5_IOMODE_S 24 +#define IOC_IOCFG5_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG5_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG5_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG5_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG5_IOMODE_INV 0x01000000 +#define IOC_IOCFG5_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG5_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG5_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG5_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG5_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG5_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG5_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG5_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG5_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -1751,13 +1751,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG5_EDGE_DET_W 2 -#define IOC_IOCFG5_EDGE_DET_M 0x00030000 -#define IOC_IOCFG5_EDGE_DET_S 16 -#define IOC_IOCFG5_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG5_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG5_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG5_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG5_EDGE_DET_W 2 +#define IOC_IOCFG5_EDGE_DET_M 0x00030000 +#define IOC_IOCFG5_EDGE_DET_S 16 +#define IOC_IOCFG5_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG5_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG5_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG5_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -1766,21 +1766,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG5_PULL_CTL_W 2 -#define IOC_IOCFG5_PULL_CTL_M 0x00006000 -#define IOC_IOCFG5_PULL_CTL_S 13 -#define IOC_IOCFG5_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG5_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG5_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG5_PULL_CTL_W 2 +#define IOC_IOCFG5_PULL_CTL_M 0x00006000 +#define IOC_IOCFG5_PULL_CTL_S 13 +#define IOC_IOCFG5_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG5_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG5_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG5_SLEW_RED 0x00001000 -#define IOC_IOCFG5_SLEW_RED_BITN 12 -#define IOC_IOCFG5_SLEW_RED_M 0x00001000 -#define IOC_IOCFG5_SLEW_RED_S 12 +#define IOC_IOCFG5_SLEW_RED 0x00001000 +#define IOC_IOCFG5_SLEW_RED_BITN 12 +#define IOC_IOCFG5_SLEW_RED_M 0x00001000 +#define IOC_IOCFG5_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -1793,12 +1793,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG5_IOCURR_W 2 -#define IOC_IOCFG5_IOCURR_M 0x00000C00 -#define IOC_IOCFG5_IOCURR_S 10 -#define IOC_IOCFG5_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG5_IOCURR_4MA 0x00000400 -#define IOC_IOCFG5_IOCURR_2MA 0x00000000 +#define IOC_IOCFG5_IOCURR_W 2 +#define IOC_IOCFG5_IOCURR_M 0x00000C00 +#define IOC_IOCFG5_IOCURR_S 10 +#define IOC_IOCFG5_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG5_IOCURR_4MA 0x00000400 +#define IOC_IOCFG5_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -1817,13 +1817,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG5_IOSTR_W 2 -#define IOC_IOCFG5_IOSTR_M 0x00000300 -#define IOC_IOCFG5_IOSTR_S 8 -#define IOC_IOCFG5_IOSTR_MAX 0x00000300 -#define IOC_IOCFG5_IOSTR_MED 0x00000200 -#define IOC_IOCFG5_IOSTR_MIN 0x00000100 -#define IOC_IOCFG5_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG5_IOSTR_W 2 +#define IOC_IOCFG5_IOSTR_M 0x00000300 +#define IOC_IOCFG5_IOSTR_S 8 +#define IOC_IOCFG5_IOSTR_MAX 0x00000300 +#define IOC_IOCFG5_IOSTR_MED 0x00000200 +#define IOC_IOCFG5_IOSTR_MIN 0x00000100 +#define IOC_IOCFG5_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -1911,51 +1911,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG5_PORT_ID_W 6 -#define IOC_IOCFG5_PORT_ID_M 0x0000003F -#define IOC_IOCFG5_PORT_ID_S 0 -#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG5_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG5_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG5_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG5_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG5_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG5_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG5_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG5_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG5_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG5_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG5_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG5_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG5_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG5_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG5_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG5_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG5_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG5_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG5_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG5_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG5_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG5_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG5_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG5_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG5_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG5_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG5_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG5_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG5_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG5_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG5_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG5_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG5_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG5_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG5_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG5_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG5_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG5_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG5_PORT_ID_W 6 +#define IOC_IOCFG5_PORT_ID_M 0x0000003F +#define IOC_IOCFG5_PORT_ID_S 0 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG5_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG5_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG5_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG5_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG5_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG5_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG5_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG5_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG5_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG5_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG5_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG5_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG5_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG5_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG5_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG5_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG5_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG5_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG5_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG5_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG5_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG5_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG5_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG5_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG5_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG5_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG5_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG5_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG5_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG5_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG5_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG5_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG5_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG5_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG5_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG5_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -1966,10 +1966,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG6_HYST_EN 0x40000000 -#define IOC_IOCFG6_HYST_EN_BITN 30 -#define IOC_IOCFG6_HYST_EN_M 0x40000000 -#define IOC_IOCFG6_HYST_EN_S 30 +#define IOC_IOCFG6_HYST_EN 0x40000000 +#define IOC_IOCFG6_HYST_EN_BITN 30 +#define IOC_IOCFG6_HYST_EN_M 0x40000000 +#define IOC_IOCFG6_HYST_EN_S 30 // Field: [29] IE // @@ -1978,10 +1978,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG6_IE 0x20000000 -#define IOC_IOCFG6_IE_BITN 29 -#define IOC_IOCFG6_IE_M 0x20000000 -#define IOC_IOCFG6_IE_S 29 +#define IOC_IOCFG6_IE 0x20000000 +#define IOC_IOCFG6_IE_BITN 29 +#define IOC_IOCFG6_IE_M 0x20000000 +#define IOC_IOCFG6_IE_S 29 // Field: [28:27] WU_CFG // @@ -2003,9 +2003,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG6_WU_CFG_W 2 -#define IOC_IOCFG6_WU_CFG_M 0x18000000 -#define IOC_IOCFG6_WU_CFG_S 27 +#define IOC_IOCFG6_WU_CFG_W 2 +#define IOC_IOCFG6_WU_CFG_M 0x18000000 +#define IOC_IOCFG6_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -2026,25 +2026,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG6_IOMODE_W 3 -#define IOC_IOCFG6_IOMODE_M 0x07000000 -#define IOC_IOCFG6_IOMODE_S 24 -#define IOC_IOCFG6_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG6_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG6_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG6_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG6_IOMODE_INV 0x01000000 -#define IOC_IOCFG6_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG6_IOMODE_W 3 +#define IOC_IOCFG6_IOMODE_M 0x07000000 +#define IOC_IOCFG6_IOMODE_S 24 +#define IOC_IOCFG6_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG6_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG6_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG6_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG6_IOMODE_INV 0x01000000 +#define IOC_IOCFG6_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG6_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG6_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG6_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG6_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG6_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG6_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG6_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG6_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -2054,13 +2054,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG6_EDGE_DET_W 2 -#define IOC_IOCFG6_EDGE_DET_M 0x00030000 -#define IOC_IOCFG6_EDGE_DET_S 16 -#define IOC_IOCFG6_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG6_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG6_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG6_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG6_EDGE_DET_W 2 +#define IOC_IOCFG6_EDGE_DET_M 0x00030000 +#define IOC_IOCFG6_EDGE_DET_S 16 +#define IOC_IOCFG6_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG6_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG6_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG6_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -2069,21 +2069,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG6_PULL_CTL_W 2 -#define IOC_IOCFG6_PULL_CTL_M 0x00006000 -#define IOC_IOCFG6_PULL_CTL_S 13 -#define IOC_IOCFG6_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG6_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG6_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG6_PULL_CTL_W 2 +#define IOC_IOCFG6_PULL_CTL_M 0x00006000 +#define IOC_IOCFG6_PULL_CTL_S 13 +#define IOC_IOCFG6_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG6_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG6_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG6_SLEW_RED 0x00001000 -#define IOC_IOCFG6_SLEW_RED_BITN 12 -#define IOC_IOCFG6_SLEW_RED_M 0x00001000 -#define IOC_IOCFG6_SLEW_RED_S 12 +#define IOC_IOCFG6_SLEW_RED 0x00001000 +#define IOC_IOCFG6_SLEW_RED_BITN 12 +#define IOC_IOCFG6_SLEW_RED_M 0x00001000 +#define IOC_IOCFG6_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -2096,12 +2096,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG6_IOCURR_W 2 -#define IOC_IOCFG6_IOCURR_M 0x00000C00 -#define IOC_IOCFG6_IOCURR_S 10 -#define IOC_IOCFG6_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG6_IOCURR_4MA 0x00000400 -#define IOC_IOCFG6_IOCURR_2MA 0x00000000 +#define IOC_IOCFG6_IOCURR_W 2 +#define IOC_IOCFG6_IOCURR_M 0x00000C00 +#define IOC_IOCFG6_IOCURR_S 10 +#define IOC_IOCFG6_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG6_IOCURR_4MA 0x00000400 +#define IOC_IOCFG6_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -2120,13 +2120,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG6_IOSTR_W 2 -#define IOC_IOCFG6_IOSTR_M 0x00000300 -#define IOC_IOCFG6_IOSTR_S 8 -#define IOC_IOCFG6_IOSTR_MAX 0x00000300 -#define IOC_IOCFG6_IOSTR_MED 0x00000200 -#define IOC_IOCFG6_IOSTR_MIN 0x00000100 -#define IOC_IOCFG6_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG6_IOSTR_W 2 +#define IOC_IOCFG6_IOSTR_M 0x00000300 +#define IOC_IOCFG6_IOSTR_S 8 +#define IOC_IOCFG6_IOSTR_MAX 0x00000300 +#define IOC_IOCFG6_IOSTR_MED 0x00000200 +#define IOC_IOCFG6_IOSTR_MIN 0x00000100 +#define IOC_IOCFG6_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -2214,51 +2214,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG6_PORT_ID_W 6 -#define IOC_IOCFG6_PORT_ID_M 0x0000003F -#define IOC_IOCFG6_PORT_ID_S 0 -#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG6_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG6_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG6_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG6_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG6_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG6_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG6_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG6_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG6_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG6_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG6_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG6_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG6_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG6_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG6_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG6_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG6_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG6_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG6_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG6_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG6_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG6_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG6_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG6_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG6_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG6_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG6_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG6_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG6_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG6_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG6_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG6_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG6_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG6_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG6_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG6_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG6_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG6_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG6_PORT_ID_W 6 +#define IOC_IOCFG6_PORT_ID_M 0x0000003F +#define IOC_IOCFG6_PORT_ID_S 0 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG6_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG6_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG6_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG6_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG6_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG6_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG6_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG6_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG6_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG6_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG6_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG6_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG6_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG6_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG6_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG6_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG6_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG6_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG6_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG6_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG6_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG6_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG6_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG6_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG6_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG6_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG6_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG6_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG6_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG6_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG6_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG6_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG6_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG6_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG6_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG6_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -2269,10 +2269,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG7_HYST_EN 0x40000000 -#define IOC_IOCFG7_HYST_EN_BITN 30 -#define IOC_IOCFG7_HYST_EN_M 0x40000000 -#define IOC_IOCFG7_HYST_EN_S 30 +#define IOC_IOCFG7_HYST_EN 0x40000000 +#define IOC_IOCFG7_HYST_EN_BITN 30 +#define IOC_IOCFG7_HYST_EN_M 0x40000000 +#define IOC_IOCFG7_HYST_EN_S 30 // Field: [29] IE // @@ -2281,10 +2281,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG7_IE 0x20000000 -#define IOC_IOCFG7_IE_BITN 29 -#define IOC_IOCFG7_IE_M 0x20000000 -#define IOC_IOCFG7_IE_S 29 +#define IOC_IOCFG7_IE 0x20000000 +#define IOC_IOCFG7_IE_BITN 29 +#define IOC_IOCFG7_IE_M 0x20000000 +#define IOC_IOCFG7_IE_S 29 // Field: [28:27] WU_CFG // @@ -2306,9 +2306,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG7_WU_CFG_W 2 -#define IOC_IOCFG7_WU_CFG_M 0x18000000 -#define IOC_IOCFG7_WU_CFG_S 27 +#define IOC_IOCFG7_WU_CFG_W 2 +#define IOC_IOCFG7_WU_CFG_M 0x18000000 +#define IOC_IOCFG7_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -2329,25 +2329,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG7_IOMODE_W 3 -#define IOC_IOCFG7_IOMODE_M 0x07000000 -#define IOC_IOCFG7_IOMODE_S 24 -#define IOC_IOCFG7_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG7_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG7_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG7_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG7_IOMODE_INV 0x01000000 -#define IOC_IOCFG7_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG7_IOMODE_W 3 +#define IOC_IOCFG7_IOMODE_M 0x07000000 +#define IOC_IOCFG7_IOMODE_S 24 +#define IOC_IOCFG7_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG7_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG7_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG7_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG7_IOMODE_INV 0x01000000 +#define IOC_IOCFG7_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG7_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG7_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG7_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG7_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG7_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG7_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG7_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG7_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -2357,13 +2357,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG7_EDGE_DET_W 2 -#define IOC_IOCFG7_EDGE_DET_M 0x00030000 -#define IOC_IOCFG7_EDGE_DET_S 16 -#define IOC_IOCFG7_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG7_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG7_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG7_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG7_EDGE_DET_W 2 +#define IOC_IOCFG7_EDGE_DET_M 0x00030000 +#define IOC_IOCFG7_EDGE_DET_S 16 +#define IOC_IOCFG7_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG7_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG7_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG7_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -2372,21 +2372,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG7_PULL_CTL_W 2 -#define IOC_IOCFG7_PULL_CTL_M 0x00006000 -#define IOC_IOCFG7_PULL_CTL_S 13 -#define IOC_IOCFG7_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG7_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG7_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG7_PULL_CTL_W 2 +#define IOC_IOCFG7_PULL_CTL_M 0x00006000 +#define IOC_IOCFG7_PULL_CTL_S 13 +#define IOC_IOCFG7_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG7_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG7_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG7_SLEW_RED 0x00001000 -#define IOC_IOCFG7_SLEW_RED_BITN 12 -#define IOC_IOCFG7_SLEW_RED_M 0x00001000 -#define IOC_IOCFG7_SLEW_RED_S 12 +#define IOC_IOCFG7_SLEW_RED 0x00001000 +#define IOC_IOCFG7_SLEW_RED_BITN 12 +#define IOC_IOCFG7_SLEW_RED_M 0x00001000 +#define IOC_IOCFG7_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -2399,12 +2399,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG7_IOCURR_W 2 -#define IOC_IOCFG7_IOCURR_M 0x00000C00 -#define IOC_IOCFG7_IOCURR_S 10 -#define IOC_IOCFG7_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG7_IOCURR_4MA 0x00000400 -#define IOC_IOCFG7_IOCURR_2MA 0x00000000 +#define IOC_IOCFG7_IOCURR_W 2 +#define IOC_IOCFG7_IOCURR_M 0x00000C00 +#define IOC_IOCFG7_IOCURR_S 10 +#define IOC_IOCFG7_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG7_IOCURR_4MA 0x00000400 +#define IOC_IOCFG7_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -2423,13 +2423,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG7_IOSTR_W 2 -#define IOC_IOCFG7_IOSTR_M 0x00000300 -#define IOC_IOCFG7_IOSTR_S 8 -#define IOC_IOCFG7_IOSTR_MAX 0x00000300 -#define IOC_IOCFG7_IOSTR_MED 0x00000200 -#define IOC_IOCFG7_IOSTR_MIN 0x00000100 -#define IOC_IOCFG7_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG7_IOSTR_W 2 +#define IOC_IOCFG7_IOSTR_M 0x00000300 +#define IOC_IOCFG7_IOSTR_S 8 +#define IOC_IOCFG7_IOSTR_MAX 0x00000300 +#define IOC_IOCFG7_IOSTR_MED 0x00000200 +#define IOC_IOCFG7_IOSTR_MIN 0x00000100 +#define IOC_IOCFG7_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -2517,51 +2517,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG7_PORT_ID_W 6 -#define IOC_IOCFG7_PORT_ID_M 0x0000003F -#define IOC_IOCFG7_PORT_ID_S 0 -#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG7_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG7_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG7_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG7_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG7_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG7_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG7_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG7_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG7_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG7_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG7_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG7_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG7_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG7_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG7_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG7_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG7_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG7_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG7_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG7_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG7_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG7_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG7_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG7_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG7_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG7_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG7_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG7_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG7_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG7_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG7_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG7_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG7_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG7_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG7_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG7_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG7_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG7_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG7_PORT_ID_W 6 +#define IOC_IOCFG7_PORT_ID_M 0x0000003F +#define IOC_IOCFG7_PORT_ID_S 0 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG7_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG7_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG7_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG7_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG7_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG7_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG7_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG7_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG7_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG7_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG7_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG7_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG7_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG7_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG7_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG7_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG7_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG7_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG7_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG7_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG7_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG7_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG7_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG7_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG7_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG7_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG7_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG7_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG7_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG7_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG7_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG7_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG7_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG7_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG7_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG7_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -2572,10 +2572,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG8_HYST_EN 0x40000000 -#define IOC_IOCFG8_HYST_EN_BITN 30 -#define IOC_IOCFG8_HYST_EN_M 0x40000000 -#define IOC_IOCFG8_HYST_EN_S 30 +#define IOC_IOCFG8_HYST_EN 0x40000000 +#define IOC_IOCFG8_HYST_EN_BITN 30 +#define IOC_IOCFG8_HYST_EN_M 0x40000000 +#define IOC_IOCFG8_HYST_EN_S 30 // Field: [29] IE // @@ -2584,10 +2584,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG8_IE 0x20000000 -#define IOC_IOCFG8_IE_BITN 29 -#define IOC_IOCFG8_IE_M 0x20000000 -#define IOC_IOCFG8_IE_S 29 +#define IOC_IOCFG8_IE 0x20000000 +#define IOC_IOCFG8_IE_BITN 29 +#define IOC_IOCFG8_IE_M 0x20000000 +#define IOC_IOCFG8_IE_S 29 // Field: [28:27] WU_CFG // @@ -2609,9 +2609,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG8_WU_CFG_W 2 -#define IOC_IOCFG8_WU_CFG_M 0x18000000 -#define IOC_IOCFG8_WU_CFG_S 27 +#define IOC_IOCFG8_WU_CFG_W 2 +#define IOC_IOCFG8_WU_CFG_M 0x18000000 +#define IOC_IOCFG8_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -2632,25 +2632,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG8_IOMODE_W 3 -#define IOC_IOCFG8_IOMODE_M 0x07000000 -#define IOC_IOCFG8_IOMODE_S 24 -#define IOC_IOCFG8_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG8_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG8_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG8_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG8_IOMODE_INV 0x01000000 -#define IOC_IOCFG8_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG8_IOMODE_W 3 +#define IOC_IOCFG8_IOMODE_M 0x07000000 +#define IOC_IOCFG8_IOMODE_S 24 +#define IOC_IOCFG8_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG8_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG8_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG8_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG8_IOMODE_INV 0x01000000 +#define IOC_IOCFG8_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG8_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG8_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG8_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG8_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG8_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG8_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG8_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG8_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -2660,13 +2660,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG8_EDGE_DET_W 2 -#define IOC_IOCFG8_EDGE_DET_M 0x00030000 -#define IOC_IOCFG8_EDGE_DET_S 16 -#define IOC_IOCFG8_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG8_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG8_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG8_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG8_EDGE_DET_W 2 +#define IOC_IOCFG8_EDGE_DET_M 0x00030000 +#define IOC_IOCFG8_EDGE_DET_S 16 +#define IOC_IOCFG8_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG8_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG8_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG8_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -2675,21 +2675,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG8_PULL_CTL_W 2 -#define IOC_IOCFG8_PULL_CTL_M 0x00006000 -#define IOC_IOCFG8_PULL_CTL_S 13 -#define IOC_IOCFG8_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG8_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG8_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG8_PULL_CTL_W 2 +#define IOC_IOCFG8_PULL_CTL_M 0x00006000 +#define IOC_IOCFG8_PULL_CTL_S 13 +#define IOC_IOCFG8_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG8_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG8_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG8_SLEW_RED 0x00001000 -#define IOC_IOCFG8_SLEW_RED_BITN 12 -#define IOC_IOCFG8_SLEW_RED_M 0x00001000 -#define IOC_IOCFG8_SLEW_RED_S 12 +#define IOC_IOCFG8_SLEW_RED 0x00001000 +#define IOC_IOCFG8_SLEW_RED_BITN 12 +#define IOC_IOCFG8_SLEW_RED_M 0x00001000 +#define IOC_IOCFG8_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -2702,12 +2702,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG8_IOCURR_W 2 -#define IOC_IOCFG8_IOCURR_M 0x00000C00 -#define IOC_IOCFG8_IOCURR_S 10 -#define IOC_IOCFG8_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG8_IOCURR_4MA 0x00000400 -#define IOC_IOCFG8_IOCURR_2MA 0x00000000 +#define IOC_IOCFG8_IOCURR_W 2 +#define IOC_IOCFG8_IOCURR_M 0x00000C00 +#define IOC_IOCFG8_IOCURR_S 10 +#define IOC_IOCFG8_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG8_IOCURR_4MA 0x00000400 +#define IOC_IOCFG8_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -2726,13 +2726,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG8_IOSTR_W 2 -#define IOC_IOCFG8_IOSTR_M 0x00000300 -#define IOC_IOCFG8_IOSTR_S 8 -#define IOC_IOCFG8_IOSTR_MAX 0x00000300 -#define IOC_IOCFG8_IOSTR_MED 0x00000200 -#define IOC_IOCFG8_IOSTR_MIN 0x00000100 -#define IOC_IOCFG8_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG8_IOSTR_W 2 +#define IOC_IOCFG8_IOSTR_M 0x00000300 +#define IOC_IOCFG8_IOSTR_S 8 +#define IOC_IOCFG8_IOSTR_MAX 0x00000300 +#define IOC_IOCFG8_IOSTR_MED 0x00000200 +#define IOC_IOCFG8_IOSTR_MIN 0x00000100 +#define IOC_IOCFG8_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -2820,51 +2820,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG8_PORT_ID_W 6 -#define IOC_IOCFG8_PORT_ID_M 0x0000003F -#define IOC_IOCFG8_PORT_ID_S 0 -#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG8_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG8_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG8_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG8_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG8_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG8_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG8_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG8_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG8_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG8_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG8_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG8_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG8_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG8_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG8_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG8_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG8_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG8_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG8_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG8_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG8_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG8_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG8_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG8_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG8_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG8_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG8_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG8_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG8_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG8_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG8_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG8_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG8_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG8_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG8_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG8_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG8_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG8_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG8_PORT_ID_W 6 +#define IOC_IOCFG8_PORT_ID_M 0x0000003F +#define IOC_IOCFG8_PORT_ID_S 0 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG8_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG8_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG8_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG8_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG8_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG8_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG8_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG8_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG8_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG8_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG8_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG8_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG8_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG8_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG8_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG8_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG8_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG8_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG8_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG8_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG8_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG8_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG8_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG8_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG8_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG8_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG8_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG8_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG8_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG8_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG8_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG8_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG8_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG8_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG8_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG8_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -2875,10 +2875,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG9_HYST_EN 0x40000000 -#define IOC_IOCFG9_HYST_EN_BITN 30 -#define IOC_IOCFG9_HYST_EN_M 0x40000000 -#define IOC_IOCFG9_HYST_EN_S 30 +#define IOC_IOCFG9_HYST_EN 0x40000000 +#define IOC_IOCFG9_HYST_EN_BITN 30 +#define IOC_IOCFG9_HYST_EN_M 0x40000000 +#define IOC_IOCFG9_HYST_EN_S 30 // Field: [29] IE // @@ -2887,10 +2887,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG9_IE 0x20000000 -#define IOC_IOCFG9_IE_BITN 29 -#define IOC_IOCFG9_IE_M 0x20000000 -#define IOC_IOCFG9_IE_S 29 +#define IOC_IOCFG9_IE 0x20000000 +#define IOC_IOCFG9_IE_BITN 29 +#define IOC_IOCFG9_IE_M 0x20000000 +#define IOC_IOCFG9_IE_S 29 // Field: [28:27] WU_CFG // @@ -2912,9 +2912,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG9_WU_CFG_W 2 -#define IOC_IOCFG9_WU_CFG_M 0x18000000 -#define IOC_IOCFG9_WU_CFG_S 27 +#define IOC_IOCFG9_WU_CFG_W 2 +#define IOC_IOCFG9_WU_CFG_M 0x18000000 +#define IOC_IOCFG9_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -2935,25 +2935,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG9_IOMODE_W 3 -#define IOC_IOCFG9_IOMODE_M 0x07000000 -#define IOC_IOCFG9_IOMODE_S 24 -#define IOC_IOCFG9_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG9_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG9_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG9_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG9_IOMODE_INV 0x01000000 -#define IOC_IOCFG9_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG9_IOMODE_W 3 +#define IOC_IOCFG9_IOMODE_M 0x07000000 +#define IOC_IOCFG9_IOMODE_S 24 +#define IOC_IOCFG9_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG9_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG9_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG9_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG9_IOMODE_INV 0x01000000 +#define IOC_IOCFG9_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG9_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG9_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG9_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG9_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG9_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG9_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG9_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG9_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -2963,13 +2963,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG9_EDGE_DET_W 2 -#define IOC_IOCFG9_EDGE_DET_M 0x00030000 -#define IOC_IOCFG9_EDGE_DET_S 16 -#define IOC_IOCFG9_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG9_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG9_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG9_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG9_EDGE_DET_W 2 +#define IOC_IOCFG9_EDGE_DET_M 0x00030000 +#define IOC_IOCFG9_EDGE_DET_S 16 +#define IOC_IOCFG9_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG9_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG9_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG9_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -2978,21 +2978,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG9_PULL_CTL_W 2 -#define IOC_IOCFG9_PULL_CTL_M 0x00006000 -#define IOC_IOCFG9_PULL_CTL_S 13 -#define IOC_IOCFG9_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG9_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG9_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG9_PULL_CTL_W 2 +#define IOC_IOCFG9_PULL_CTL_M 0x00006000 +#define IOC_IOCFG9_PULL_CTL_S 13 +#define IOC_IOCFG9_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG9_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG9_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG9_SLEW_RED 0x00001000 -#define IOC_IOCFG9_SLEW_RED_BITN 12 -#define IOC_IOCFG9_SLEW_RED_M 0x00001000 -#define IOC_IOCFG9_SLEW_RED_S 12 +#define IOC_IOCFG9_SLEW_RED 0x00001000 +#define IOC_IOCFG9_SLEW_RED_BITN 12 +#define IOC_IOCFG9_SLEW_RED_M 0x00001000 +#define IOC_IOCFG9_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -3005,12 +3005,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG9_IOCURR_W 2 -#define IOC_IOCFG9_IOCURR_M 0x00000C00 -#define IOC_IOCFG9_IOCURR_S 10 -#define IOC_IOCFG9_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG9_IOCURR_4MA 0x00000400 -#define IOC_IOCFG9_IOCURR_2MA 0x00000000 +#define IOC_IOCFG9_IOCURR_W 2 +#define IOC_IOCFG9_IOCURR_M 0x00000C00 +#define IOC_IOCFG9_IOCURR_S 10 +#define IOC_IOCFG9_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG9_IOCURR_4MA 0x00000400 +#define IOC_IOCFG9_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -3029,13 +3029,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG9_IOSTR_W 2 -#define IOC_IOCFG9_IOSTR_M 0x00000300 -#define IOC_IOCFG9_IOSTR_S 8 -#define IOC_IOCFG9_IOSTR_MAX 0x00000300 -#define IOC_IOCFG9_IOSTR_MED 0x00000200 -#define IOC_IOCFG9_IOSTR_MIN 0x00000100 -#define IOC_IOCFG9_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG9_IOSTR_W 2 +#define IOC_IOCFG9_IOSTR_M 0x00000300 +#define IOC_IOCFG9_IOSTR_S 8 +#define IOC_IOCFG9_IOSTR_MAX 0x00000300 +#define IOC_IOCFG9_IOSTR_MED 0x00000200 +#define IOC_IOCFG9_IOSTR_MIN 0x00000100 +#define IOC_IOCFG9_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -3123,51 +3123,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG9_PORT_ID_W 6 -#define IOC_IOCFG9_PORT_ID_M 0x0000003F -#define IOC_IOCFG9_PORT_ID_S 0 -#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG9_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG9_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG9_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG9_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG9_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG9_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG9_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG9_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG9_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG9_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG9_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG9_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG9_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG9_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG9_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG9_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG9_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG9_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG9_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG9_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG9_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG9_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG9_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG9_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG9_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG9_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG9_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG9_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG9_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG9_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG9_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG9_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG9_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG9_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG9_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG9_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG9_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG9_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG9_PORT_ID_W 6 +#define IOC_IOCFG9_PORT_ID_M 0x0000003F +#define IOC_IOCFG9_PORT_ID_S 0 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG9_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG9_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG9_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG9_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG9_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG9_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG9_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG9_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG9_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG9_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG9_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG9_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG9_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG9_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG9_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG9_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG9_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG9_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG9_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG9_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG9_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG9_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG9_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG9_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG9_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG9_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG9_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG9_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG9_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG9_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG9_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG9_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG9_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG9_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG9_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG9_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -3178,10 +3178,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG10_HYST_EN 0x40000000 -#define IOC_IOCFG10_HYST_EN_BITN 30 -#define IOC_IOCFG10_HYST_EN_M 0x40000000 -#define IOC_IOCFG10_HYST_EN_S 30 +#define IOC_IOCFG10_HYST_EN 0x40000000 +#define IOC_IOCFG10_HYST_EN_BITN 30 +#define IOC_IOCFG10_HYST_EN_M 0x40000000 +#define IOC_IOCFG10_HYST_EN_S 30 // Field: [29] IE // @@ -3190,10 +3190,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG10_IE 0x20000000 -#define IOC_IOCFG10_IE_BITN 29 -#define IOC_IOCFG10_IE_M 0x20000000 -#define IOC_IOCFG10_IE_S 29 +#define IOC_IOCFG10_IE 0x20000000 +#define IOC_IOCFG10_IE_BITN 29 +#define IOC_IOCFG10_IE_M 0x20000000 +#define IOC_IOCFG10_IE_S 29 // Field: [28:27] WU_CFG // @@ -3215,9 +3215,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG10_WU_CFG_W 2 -#define IOC_IOCFG10_WU_CFG_M 0x18000000 -#define IOC_IOCFG10_WU_CFG_S 27 +#define IOC_IOCFG10_WU_CFG_W 2 +#define IOC_IOCFG10_WU_CFG_M 0x18000000 +#define IOC_IOCFG10_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -3238,25 +3238,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG10_IOMODE_W 3 -#define IOC_IOCFG10_IOMODE_M 0x07000000 -#define IOC_IOCFG10_IOMODE_S 24 -#define IOC_IOCFG10_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG10_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG10_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG10_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG10_IOMODE_INV 0x01000000 -#define IOC_IOCFG10_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG10_IOMODE_W 3 +#define IOC_IOCFG10_IOMODE_M 0x07000000 +#define IOC_IOCFG10_IOMODE_S 24 +#define IOC_IOCFG10_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG10_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG10_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG10_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG10_IOMODE_INV 0x01000000 +#define IOC_IOCFG10_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG10_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG10_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG10_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG10_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG10_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG10_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG10_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG10_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -3266,13 +3266,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG10_EDGE_DET_W 2 -#define IOC_IOCFG10_EDGE_DET_M 0x00030000 -#define IOC_IOCFG10_EDGE_DET_S 16 -#define IOC_IOCFG10_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG10_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG10_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG10_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG10_EDGE_DET_W 2 +#define IOC_IOCFG10_EDGE_DET_M 0x00030000 +#define IOC_IOCFG10_EDGE_DET_S 16 +#define IOC_IOCFG10_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG10_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG10_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG10_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -3281,21 +3281,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG10_PULL_CTL_W 2 -#define IOC_IOCFG10_PULL_CTL_M 0x00006000 -#define IOC_IOCFG10_PULL_CTL_S 13 -#define IOC_IOCFG10_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG10_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG10_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG10_PULL_CTL_W 2 +#define IOC_IOCFG10_PULL_CTL_M 0x00006000 +#define IOC_IOCFG10_PULL_CTL_S 13 +#define IOC_IOCFG10_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG10_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG10_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG10_SLEW_RED 0x00001000 -#define IOC_IOCFG10_SLEW_RED_BITN 12 -#define IOC_IOCFG10_SLEW_RED_M 0x00001000 -#define IOC_IOCFG10_SLEW_RED_S 12 +#define IOC_IOCFG10_SLEW_RED 0x00001000 +#define IOC_IOCFG10_SLEW_RED_BITN 12 +#define IOC_IOCFG10_SLEW_RED_M 0x00001000 +#define IOC_IOCFG10_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -3308,12 +3308,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG10_IOCURR_W 2 -#define IOC_IOCFG10_IOCURR_M 0x00000C00 -#define IOC_IOCFG10_IOCURR_S 10 -#define IOC_IOCFG10_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG10_IOCURR_4MA 0x00000400 -#define IOC_IOCFG10_IOCURR_2MA 0x00000000 +#define IOC_IOCFG10_IOCURR_W 2 +#define IOC_IOCFG10_IOCURR_M 0x00000C00 +#define IOC_IOCFG10_IOCURR_S 10 +#define IOC_IOCFG10_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG10_IOCURR_4MA 0x00000400 +#define IOC_IOCFG10_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -3332,13 +3332,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG10_IOSTR_W 2 -#define IOC_IOCFG10_IOSTR_M 0x00000300 -#define IOC_IOCFG10_IOSTR_S 8 -#define IOC_IOCFG10_IOSTR_MAX 0x00000300 -#define IOC_IOCFG10_IOSTR_MED 0x00000200 -#define IOC_IOCFG10_IOSTR_MIN 0x00000100 -#define IOC_IOCFG10_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG10_IOSTR_W 2 +#define IOC_IOCFG10_IOSTR_M 0x00000300 +#define IOC_IOCFG10_IOSTR_S 8 +#define IOC_IOCFG10_IOSTR_MAX 0x00000300 +#define IOC_IOCFG10_IOSTR_MED 0x00000200 +#define IOC_IOCFG10_IOSTR_MIN 0x00000100 +#define IOC_IOCFG10_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -3426,51 +3426,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG10_PORT_ID_W 6 -#define IOC_IOCFG10_PORT_ID_M 0x0000003F -#define IOC_IOCFG10_PORT_ID_S 0 -#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG10_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG10_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG10_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG10_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG10_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG10_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG10_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG10_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG10_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG10_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG10_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG10_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG10_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG10_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG10_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG10_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG10_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG10_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG10_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG10_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG10_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG10_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG10_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG10_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG10_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG10_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG10_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG10_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG10_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG10_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG10_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG10_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG10_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG10_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG10_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG10_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG10_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG10_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG10_PORT_ID_W 6 +#define IOC_IOCFG10_PORT_ID_M 0x0000003F +#define IOC_IOCFG10_PORT_ID_S 0 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG10_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG10_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG10_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG10_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG10_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG10_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG10_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG10_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG10_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG10_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG10_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG10_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG10_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG10_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG10_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG10_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG10_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG10_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG10_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG10_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG10_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG10_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG10_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG10_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG10_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG10_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG10_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG10_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG10_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG10_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG10_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG10_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG10_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG10_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG10_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG10_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -3481,10 +3481,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG11_HYST_EN 0x40000000 -#define IOC_IOCFG11_HYST_EN_BITN 30 -#define IOC_IOCFG11_HYST_EN_M 0x40000000 -#define IOC_IOCFG11_HYST_EN_S 30 +#define IOC_IOCFG11_HYST_EN 0x40000000 +#define IOC_IOCFG11_HYST_EN_BITN 30 +#define IOC_IOCFG11_HYST_EN_M 0x40000000 +#define IOC_IOCFG11_HYST_EN_S 30 // Field: [29] IE // @@ -3493,10 +3493,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG11_IE 0x20000000 -#define IOC_IOCFG11_IE_BITN 29 -#define IOC_IOCFG11_IE_M 0x20000000 -#define IOC_IOCFG11_IE_S 29 +#define IOC_IOCFG11_IE 0x20000000 +#define IOC_IOCFG11_IE_BITN 29 +#define IOC_IOCFG11_IE_M 0x20000000 +#define IOC_IOCFG11_IE_S 29 // Field: [28:27] WU_CFG // @@ -3518,9 +3518,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG11_WU_CFG_W 2 -#define IOC_IOCFG11_WU_CFG_M 0x18000000 -#define IOC_IOCFG11_WU_CFG_S 27 +#define IOC_IOCFG11_WU_CFG_W 2 +#define IOC_IOCFG11_WU_CFG_M 0x18000000 +#define IOC_IOCFG11_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -3541,25 +3541,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG11_IOMODE_W 3 -#define IOC_IOCFG11_IOMODE_M 0x07000000 -#define IOC_IOCFG11_IOMODE_S 24 -#define IOC_IOCFG11_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG11_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG11_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG11_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG11_IOMODE_INV 0x01000000 -#define IOC_IOCFG11_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG11_IOMODE_W 3 +#define IOC_IOCFG11_IOMODE_M 0x07000000 +#define IOC_IOCFG11_IOMODE_S 24 +#define IOC_IOCFG11_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG11_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG11_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG11_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG11_IOMODE_INV 0x01000000 +#define IOC_IOCFG11_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG11_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG11_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG11_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG11_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG11_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG11_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG11_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG11_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -3569,13 +3569,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG11_EDGE_DET_W 2 -#define IOC_IOCFG11_EDGE_DET_M 0x00030000 -#define IOC_IOCFG11_EDGE_DET_S 16 -#define IOC_IOCFG11_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG11_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG11_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG11_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG11_EDGE_DET_W 2 +#define IOC_IOCFG11_EDGE_DET_M 0x00030000 +#define IOC_IOCFG11_EDGE_DET_S 16 +#define IOC_IOCFG11_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG11_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG11_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG11_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -3584,21 +3584,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG11_PULL_CTL_W 2 -#define IOC_IOCFG11_PULL_CTL_M 0x00006000 -#define IOC_IOCFG11_PULL_CTL_S 13 -#define IOC_IOCFG11_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG11_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG11_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG11_PULL_CTL_W 2 +#define IOC_IOCFG11_PULL_CTL_M 0x00006000 +#define IOC_IOCFG11_PULL_CTL_S 13 +#define IOC_IOCFG11_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG11_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG11_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG11_SLEW_RED 0x00001000 -#define IOC_IOCFG11_SLEW_RED_BITN 12 -#define IOC_IOCFG11_SLEW_RED_M 0x00001000 -#define IOC_IOCFG11_SLEW_RED_S 12 +#define IOC_IOCFG11_SLEW_RED 0x00001000 +#define IOC_IOCFG11_SLEW_RED_BITN 12 +#define IOC_IOCFG11_SLEW_RED_M 0x00001000 +#define IOC_IOCFG11_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -3611,12 +3611,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG11_IOCURR_W 2 -#define IOC_IOCFG11_IOCURR_M 0x00000C00 -#define IOC_IOCFG11_IOCURR_S 10 -#define IOC_IOCFG11_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG11_IOCURR_4MA 0x00000400 -#define IOC_IOCFG11_IOCURR_2MA 0x00000000 +#define IOC_IOCFG11_IOCURR_W 2 +#define IOC_IOCFG11_IOCURR_M 0x00000C00 +#define IOC_IOCFG11_IOCURR_S 10 +#define IOC_IOCFG11_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG11_IOCURR_4MA 0x00000400 +#define IOC_IOCFG11_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -3635,13 +3635,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG11_IOSTR_W 2 -#define IOC_IOCFG11_IOSTR_M 0x00000300 -#define IOC_IOCFG11_IOSTR_S 8 -#define IOC_IOCFG11_IOSTR_MAX 0x00000300 -#define IOC_IOCFG11_IOSTR_MED 0x00000200 -#define IOC_IOCFG11_IOSTR_MIN 0x00000100 -#define IOC_IOCFG11_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG11_IOSTR_W 2 +#define IOC_IOCFG11_IOSTR_M 0x00000300 +#define IOC_IOCFG11_IOSTR_S 8 +#define IOC_IOCFG11_IOSTR_MAX 0x00000300 +#define IOC_IOCFG11_IOSTR_MED 0x00000200 +#define IOC_IOCFG11_IOSTR_MIN 0x00000100 +#define IOC_IOCFG11_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -3729,51 +3729,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG11_PORT_ID_W 6 -#define IOC_IOCFG11_PORT_ID_M 0x0000003F -#define IOC_IOCFG11_PORT_ID_S 0 -#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG11_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG11_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG11_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG11_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG11_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG11_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG11_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG11_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG11_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG11_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG11_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG11_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG11_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG11_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG11_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG11_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG11_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG11_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG11_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG11_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG11_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG11_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG11_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG11_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG11_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG11_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG11_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG11_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG11_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG11_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG11_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG11_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG11_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG11_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG11_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG11_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG11_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG11_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG11_PORT_ID_W 6 +#define IOC_IOCFG11_PORT_ID_M 0x0000003F +#define IOC_IOCFG11_PORT_ID_S 0 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG11_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG11_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG11_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG11_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG11_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG11_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG11_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG11_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG11_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG11_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG11_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG11_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG11_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG11_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG11_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG11_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG11_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG11_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG11_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG11_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG11_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG11_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG11_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG11_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG11_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG11_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG11_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG11_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG11_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG11_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG11_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG11_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG11_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG11_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG11_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG11_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -3784,10 +3784,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG12_HYST_EN 0x40000000 -#define IOC_IOCFG12_HYST_EN_BITN 30 -#define IOC_IOCFG12_HYST_EN_M 0x40000000 -#define IOC_IOCFG12_HYST_EN_S 30 +#define IOC_IOCFG12_HYST_EN 0x40000000 +#define IOC_IOCFG12_HYST_EN_BITN 30 +#define IOC_IOCFG12_HYST_EN_M 0x40000000 +#define IOC_IOCFG12_HYST_EN_S 30 // Field: [29] IE // @@ -3796,10 +3796,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG12_IE 0x20000000 -#define IOC_IOCFG12_IE_BITN 29 -#define IOC_IOCFG12_IE_M 0x20000000 -#define IOC_IOCFG12_IE_S 29 +#define IOC_IOCFG12_IE 0x20000000 +#define IOC_IOCFG12_IE_BITN 29 +#define IOC_IOCFG12_IE_M 0x20000000 +#define IOC_IOCFG12_IE_S 29 // Field: [28:27] WU_CFG // @@ -3821,9 +3821,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG12_WU_CFG_W 2 -#define IOC_IOCFG12_WU_CFG_M 0x18000000 -#define IOC_IOCFG12_WU_CFG_S 27 +#define IOC_IOCFG12_WU_CFG_W 2 +#define IOC_IOCFG12_WU_CFG_M 0x18000000 +#define IOC_IOCFG12_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -3844,25 +3844,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG12_IOMODE_W 3 -#define IOC_IOCFG12_IOMODE_M 0x07000000 -#define IOC_IOCFG12_IOMODE_S 24 -#define IOC_IOCFG12_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG12_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG12_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG12_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG12_IOMODE_INV 0x01000000 -#define IOC_IOCFG12_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG12_IOMODE_W 3 +#define IOC_IOCFG12_IOMODE_M 0x07000000 +#define IOC_IOCFG12_IOMODE_S 24 +#define IOC_IOCFG12_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG12_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG12_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG12_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG12_IOMODE_INV 0x01000000 +#define IOC_IOCFG12_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG12_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG12_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG12_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG12_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG12_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG12_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG12_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG12_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -3872,13 +3872,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG12_EDGE_DET_W 2 -#define IOC_IOCFG12_EDGE_DET_M 0x00030000 -#define IOC_IOCFG12_EDGE_DET_S 16 -#define IOC_IOCFG12_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG12_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG12_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG12_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG12_EDGE_DET_W 2 +#define IOC_IOCFG12_EDGE_DET_M 0x00030000 +#define IOC_IOCFG12_EDGE_DET_S 16 +#define IOC_IOCFG12_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG12_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG12_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG12_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -3887,21 +3887,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG12_PULL_CTL_W 2 -#define IOC_IOCFG12_PULL_CTL_M 0x00006000 -#define IOC_IOCFG12_PULL_CTL_S 13 -#define IOC_IOCFG12_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG12_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG12_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG12_PULL_CTL_W 2 +#define IOC_IOCFG12_PULL_CTL_M 0x00006000 +#define IOC_IOCFG12_PULL_CTL_S 13 +#define IOC_IOCFG12_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG12_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG12_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG12_SLEW_RED 0x00001000 -#define IOC_IOCFG12_SLEW_RED_BITN 12 -#define IOC_IOCFG12_SLEW_RED_M 0x00001000 -#define IOC_IOCFG12_SLEW_RED_S 12 +#define IOC_IOCFG12_SLEW_RED 0x00001000 +#define IOC_IOCFG12_SLEW_RED_BITN 12 +#define IOC_IOCFG12_SLEW_RED_M 0x00001000 +#define IOC_IOCFG12_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -3914,12 +3914,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG12_IOCURR_W 2 -#define IOC_IOCFG12_IOCURR_M 0x00000C00 -#define IOC_IOCFG12_IOCURR_S 10 -#define IOC_IOCFG12_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG12_IOCURR_4MA 0x00000400 -#define IOC_IOCFG12_IOCURR_2MA 0x00000000 +#define IOC_IOCFG12_IOCURR_W 2 +#define IOC_IOCFG12_IOCURR_M 0x00000C00 +#define IOC_IOCFG12_IOCURR_S 10 +#define IOC_IOCFG12_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG12_IOCURR_4MA 0x00000400 +#define IOC_IOCFG12_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -3938,13 +3938,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG12_IOSTR_W 2 -#define IOC_IOCFG12_IOSTR_M 0x00000300 -#define IOC_IOCFG12_IOSTR_S 8 -#define IOC_IOCFG12_IOSTR_MAX 0x00000300 -#define IOC_IOCFG12_IOSTR_MED 0x00000200 -#define IOC_IOCFG12_IOSTR_MIN 0x00000100 -#define IOC_IOCFG12_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG12_IOSTR_W 2 +#define IOC_IOCFG12_IOSTR_M 0x00000300 +#define IOC_IOCFG12_IOSTR_S 8 +#define IOC_IOCFG12_IOSTR_MAX 0x00000300 +#define IOC_IOCFG12_IOSTR_MED 0x00000200 +#define IOC_IOCFG12_IOSTR_MIN 0x00000100 +#define IOC_IOCFG12_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -4032,51 +4032,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG12_PORT_ID_W 6 -#define IOC_IOCFG12_PORT_ID_M 0x0000003F -#define IOC_IOCFG12_PORT_ID_S 0 -#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG12_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG12_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG12_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG12_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG12_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG12_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG12_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG12_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG12_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG12_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG12_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG12_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG12_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG12_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG12_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG12_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG12_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG12_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG12_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG12_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG12_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG12_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG12_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG12_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG12_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG12_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG12_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG12_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG12_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG12_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG12_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG12_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG12_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG12_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG12_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG12_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG12_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG12_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG12_PORT_ID_W 6 +#define IOC_IOCFG12_PORT_ID_M 0x0000003F +#define IOC_IOCFG12_PORT_ID_S 0 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG12_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG12_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG12_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG12_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG12_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG12_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG12_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG12_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG12_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG12_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG12_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG12_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG12_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG12_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG12_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG12_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG12_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG12_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG12_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG12_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG12_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG12_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG12_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG12_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG12_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG12_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG12_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG12_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG12_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG12_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG12_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG12_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG12_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG12_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG12_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG12_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -4087,10 +4087,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG13_HYST_EN 0x40000000 -#define IOC_IOCFG13_HYST_EN_BITN 30 -#define IOC_IOCFG13_HYST_EN_M 0x40000000 -#define IOC_IOCFG13_HYST_EN_S 30 +#define IOC_IOCFG13_HYST_EN 0x40000000 +#define IOC_IOCFG13_HYST_EN_BITN 30 +#define IOC_IOCFG13_HYST_EN_M 0x40000000 +#define IOC_IOCFG13_HYST_EN_S 30 // Field: [29] IE // @@ -4099,10 +4099,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG13_IE 0x20000000 -#define IOC_IOCFG13_IE_BITN 29 -#define IOC_IOCFG13_IE_M 0x20000000 -#define IOC_IOCFG13_IE_S 29 +#define IOC_IOCFG13_IE 0x20000000 +#define IOC_IOCFG13_IE_BITN 29 +#define IOC_IOCFG13_IE_M 0x20000000 +#define IOC_IOCFG13_IE_S 29 // Field: [28:27] WU_CFG // @@ -4124,9 +4124,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG13_WU_CFG_W 2 -#define IOC_IOCFG13_WU_CFG_M 0x18000000 -#define IOC_IOCFG13_WU_CFG_S 27 +#define IOC_IOCFG13_WU_CFG_W 2 +#define IOC_IOCFG13_WU_CFG_M 0x18000000 +#define IOC_IOCFG13_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -4147,25 +4147,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG13_IOMODE_W 3 -#define IOC_IOCFG13_IOMODE_M 0x07000000 -#define IOC_IOCFG13_IOMODE_S 24 -#define IOC_IOCFG13_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG13_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG13_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG13_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG13_IOMODE_INV 0x01000000 -#define IOC_IOCFG13_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG13_IOMODE_W 3 +#define IOC_IOCFG13_IOMODE_M 0x07000000 +#define IOC_IOCFG13_IOMODE_S 24 +#define IOC_IOCFG13_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG13_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG13_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG13_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG13_IOMODE_INV 0x01000000 +#define IOC_IOCFG13_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG13_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG13_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG13_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG13_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG13_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG13_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG13_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG13_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -4175,13 +4175,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG13_EDGE_DET_W 2 -#define IOC_IOCFG13_EDGE_DET_M 0x00030000 -#define IOC_IOCFG13_EDGE_DET_S 16 -#define IOC_IOCFG13_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG13_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG13_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG13_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG13_EDGE_DET_W 2 +#define IOC_IOCFG13_EDGE_DET_M 0x00030000 +#define IOC_IOCFG13_EDGE_DET_S 16 +#define IOC_IOCFG13_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG13_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG13_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG13_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -4190,21 +4190,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG13_PULL_CTL_W 2 -#define IOC_IOCFG13_PULL_CTL_M 0x00006000 -#define IOC_IOCFG13_PULL_CTL_S 13 -#define IOC_IOCFG13_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG13_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG13_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG13_PULL_CTL_W 2 +#define IOC_IOCFG13_PULL_CTL_M 0x00006000 +#define IOC_IOCFG13_PULL_CTL_S 13 +#define IOC_IOCFG13_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG13_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG13_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG13_SLEW_RED 0x00001000 -#define IOC_IOCFG13_SLEW_RED_BITN 12 -#define IOC_IOCFG13_SLEW_RED_M 0x00001000 -#define IOC_IOCFG13_SLEW_RED_S 12 +#define IOC_IOCFG13_SLEW_RED 0x00001000 +#define IOC_IOCFG13_SLEW_RED_BITN 12 +#define IOC_IOCFG13_SLEW_RED_M 0x00001000 +#define IOC_IOCFG13_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -4217,12 +4217,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG13_IOCURR_W 2 -#define IOC_IOCFG13_IOCURR_M 0x00000C00 -#define IOC_IOCFG13_IOCURR_S 10 -#define IOC_IOCFG13_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG13_IOCURR_4MA 0x00000400 -#define IOC_IOCFG13_IOCURR_2MA 0x00000000 +#define IOC_IOCFG13_IOCURR_W 2 +#define IOC_IOCFG13_IOCURR_M 0x00000C00 +#define IOC_IOCFG13_IOCURR_S 10 +#define IOC_IOCFG13_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG13_IOCURR_4MA 0x00000400 +#define IOC_IOCFG13_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -4241,13 +4241,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG13_IOSTR_W 2 -#define IOC_IOCFG13_IOSTR_M 0x00000300 -#define IOC_IOCFG13_IOSTR_S 8 -#define IOC_IOCFG13_IOSTR_MAX 0x00000300 -#define IOC_IOCFG13_IOSTR_MED 0x00000200 -#define IOC_IOCFG13_IOSTR_MIN 0x00000100 -#define IOC_IOCFG13_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG13_IOSTR_W 2 +#define IOC_IOCFG13_IOSTR_M 0x00000300 +#define IOC_IOCFG13_IOSTR_S 8 +#define IOC_IOCFG13_IOSTR_MAX 0x00000300 +#define IOC_IOCFG13_IOSTR_MED 0x00000200 +#define IOC_IOCFG13_IOSTR_MIN 0x00000100 +#define IOC_IOCFG13_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -4335,51 +4335,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG13_PORT_ID_W 6 -#define IOC_IOCFG13_PORT_ID_M 0x0000003F -#define IOC_IOCFG13_PORT_ID_S 0 -#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG13_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG13_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG13_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG13_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG13_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG13_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG13_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG13_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG13_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG13_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG13_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG13_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG13_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG13_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG13_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG13_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG13_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG13_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG13_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG13_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG13_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG13_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG13_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG13_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG13_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG13_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG13_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG13_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG13_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG13_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG13_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG13_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG13_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG13_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG13_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG13_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG13_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG13_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG13_PORT_ID_W 6 +#define IOC_IOCFG13_PORT_ID_M 0x0000003F +#define IOC_IOCFG13_PORT_ID_S 0 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG13_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG13_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG13_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG13_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG13_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG13_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG13_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG13_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG13_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG13_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG13_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG13_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG13_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG13_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG13_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG13_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG13_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG13_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG13_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG13_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG13_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG13_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG13_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG13_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG13_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG13_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG13_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG13_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG13_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG13_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG13_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG13_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG13_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG13_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG13_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG13_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -4390,10 +4390,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG14_HYST_EN 0x40000000 -#define IOC_IOCFG14_HYST_EN_BITN 30 -#define IOC_IOCFG14_HYST_EN_M 0x40000000 -#define IOC_IOCFG14_HYST_EN_S 30 +#define IOC_IOCFG14_HYST_EN 0x40000000 +#define IOC_IOCFG14_HYST_EN_BITN 30 +#define IOC_IOCFG14_HYST_EN_M 0x40000000 +#define IOC_IOCFG14_HYST_EN_S 30 // Field: [29] IE // @@ -4402,10 +4402,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG14_IE 0x20000000 -#define IOC_IOCFG14_IE_BITN 29 -#define IOC_IOCFG14_IE_M 0x20000000 -#define IOC_IOCFG14_IE_S 29 +#define IOC_IOCFG14_IE 0x20000000 +#define IOC_IOCFG14_IE_BITN 29 +#define IOC_IOCFG14_IE_M 0x20000000 +#define IOC_IOCFG14_IE_S 29 // Field: [28:27] WU_CFG // @@ -4427,9 +4427,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG14_WU_CFG_W 2 -#define IOC_IOCFG14_WU_CFG_M 0x18000000 -#define IOC_IOCFG14_WU_CFG_S 27 +#define IOC_IOCFG14_WU_CFG_W 2 +#define IOC_IOCFG14_WU_CFG_M 0x18000000 +#define IOC_IOCFG14_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -4450,25 +4450,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG14_IOMODE_W 3 -#define IOC_IOCFG14_IOMODE_M 0x07000000 -#define IOC_IOCFG14_IOMODE_S 24 -#define IOC_IOCFG14_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG14_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG14_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG14_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG14_IOMODE_INV 0x01000000 -#define IOC_IOCFG14_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG14_IOMODE_W 3 +#define IOC_IOCFG14_IOMODE_M 0x07000000 +#define IOC_IOCFG14_IOMODE_S 24 +#define IOC_IOCFG14_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG14_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG14_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG14_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG14_IOMODE_INV 0x01000000 +#define IOC_IOCFG14_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG14_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG14_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG14_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG14_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG14_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG14_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG14_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG14_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -4478,13 +4478,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG14_EDGE_DET_W 2 -#define IOC_IOCFG14_EDGE_DET_M 0x00030000 -#define IOC_IOCFG14_EDGE_DET_S 16 -#define IOC_IOCFG14_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG14_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG14_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG14_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG14_EDGE_DET_W 2 +#define IOC_IOCFG14_EDGE_DET_M 0x00030000 +#define IOC_IOCFG14_EDGE_DET_S 16 +#define IOC_IOCFG14_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG14_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG14_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG14_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -4493,21 +4493,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG14_PULL_CTL_W 2 -#define IOC_IOCFG14_PULL_CTL_M 0x00006000 -#define IOC_IOCFG14_PULL_CTL_S 13 -#define IOC_IOCFG14_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG14_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG14_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG14_PULL_CTL_W 2 +#define IOC_IOCFG14_PULL_CTL_M 0x00006000 +#define IOC_IOCFG14_PULL_CTL_S 13 +#define IOC_IOCFG14_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG14_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG14_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG14_SLEW_RED 0x00001000 -#define IOC_IOCFG14_SLEW_RED_BITN 12 -#define IOC_IOCFG14_SLEW_RED_M 0x00001000 -#define IOC_IOCFG14_SLEW_RED_S 12 +#define IOC_IOCFG14_SLEW_RED 0x00001000 +#define IOC_IOCFG14_SLEW_RED_BITN 12 +#define IOC_IOCFG14_SLEW_RED_M 0x00001000 +#define IOC_IOCFG14_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -4520,12 +4520,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG14_IOCURR_W 2 -#define IOC_IOCFG14_IOCURR_M 0x00000C00 -#define IOC_IOCFG14_IOCURR_S 10 -#define IOC_IOCFG14_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG14_IOCURR_4MA 0x00000400 -#define IOC_IOCFG14_IOCURR_2MA 0x00000000 +#define IOC_IOCFG14_IOCURR_W 2 +#define IOC_IOCFG14_IOCURR_M 0x00000C00 +#define IOC_IOCFG14_IOCURR_S 10 +#define IOC_IOCFG14_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG14_IOCURR_4MA 0x00000400 +#define IOC_IOCFG14_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -4544,13 +4544,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG14_IOSTR_W 2 -#define IOC_IOCFG14_IOSTR_M 0x00000300 -#define IOC_IOCFG14_IOSTR_S 8 -#define IOC_IOCFG14_IOSTR_MAX 0x00000300 -#define IOC_IOCFG14_IOSTR_MED 0x00000200 -#define IOC_IOCFG14_IOSTR_MIN 0x00000100 -#define IOC_IOCFG14_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG14_IOSTR_W 2 +#define IOC_IOCFG14_IOSTR_M 0x00000300 +#define IOC_IOCFG14_IOSTR_S 8 +#define IOC_IOCFG14_IOSTR_MAX 0x00000300 +#define IOC_IOCFG14_IOSTR_MED 0x00000200 +#define IOC_IOCFG14_IOSTR_MIN 0x00000100 +#define IOC_IOCFG14_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -4638,51 +4638,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG14_PORT_ID_W 6 -#define IOC_IOCFG14_PORT_ID_M 0x0000003F -#define IOC_IOCFG14_PORT_ID_S 0 -#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG14_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG14_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG14_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG14_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG14_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG14_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG14_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG14_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG14_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG14_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG14_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG14_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG14_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG14_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG14_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG14_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG14_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG14_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG14_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG14_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG14_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG14_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG14_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG14_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG14_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG14_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG14_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG14_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG14_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG14_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG14_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG14_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG14_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG14_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG14_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG14_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG14_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG14_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG14_PORT_ID_W 6 +#define IOC_IOCFG14_PORT_ID_M 0x0000003F +#define IOC_IOCFG14_PORT_ID_S 0 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG14_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG14_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG14_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG14_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG14_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG14_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG14_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG14_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG14_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG14_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG14_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG14_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG14_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG14_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG14_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG14_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG14_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG14_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG14_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG14_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG14_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG14_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG14_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG14_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG14_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG14_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG14_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG14_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG14_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG14_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG14_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG14_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG14_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG14_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG14_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG14_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -4693,10 +4693,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG15_HYST_EN 0x40000000 -#define IOC_IOCFG15_HYST_EN_BITN 30 -#define IOC_IOCFG15_HYST_EN_M 0x40000000 -#define IOC_IOCFG15_HYST_EN_S 30 +#define IOC_IOCFG15_HYST_EN 0x40000000 +#define IOC_IOCFG15_HYST_EN_BITN 30 +#define IOC_IOCFG15_HYST_EN_M 0x40000000 +#define IOC_IOCFG15_HYST_EN_S 30 // Field: [29] IE // @@ -4705,10 +4705,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG15_IE 0x20000000 -#define IOC_IOCFG15_IE_BITN 29 -#define IOC_IOCFG15_IE_M 0x20000000 -#define IOC_IOCFG15_IE_S 29 +#define IOC_IOCFG15_IE 0x20000000 +#define IOC_IOCFG15_IE_BITN 29 +#define IOC_IOCFG15_IE_M 0x20000000 +#define IOC_IOCFG15_IE_S 29 // Field: [28:27] WU_CFG // @@ -4730,9 +4730,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG15_WU_CFG_W 2 -#define IOC_IOCFG15_WU_CFG_M 0x18000000 -#define IOC_IOCFG15_WU_CFG_S 27 +#define IOC_IOCFG15_WU_CFG_W 2 +#define IOC_IOCFG15_WU_CFG_M 0x18000000 +#define IOC_IOCFG15_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -4753,25 +4753,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG15_IOMODE_W 3 -#define IOC_IOCFG15_IOMODE_M 0x07000000 -#define IOC_IOCFG15_IOMODE_S 24 -#define IOC_IOCFG15_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG15_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG15_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG15_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG15_IOMODE_INV 0x01000000 -#define IOC_IOCFG15_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG15_IOMODE_W 3 +#define IOC_IOCFG15_IOMODE_M 0x07000000 +#define IOC_IOCFG15_IOMODE_S 24 +#define IOC_IOCFG15_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG15_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG15_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG15_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG15_IOMODE_INV 0x01000000 +#define IOC_IOCFG15_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG15_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG15_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG15_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG15_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG15_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG15_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG15_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG15_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -4781,13 +4781,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG15_EDGE_DET_W 2 -#define IOC_IOCFG15_EDGE_DET_M 0x00030000 -#define IOC_IOCFG15_EDGE_DET_S 16 -#define IOC_IOCFG15_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG15_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG15_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG15_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG15_EDGE_DET_W 2 +#define IOC_IOCFG15_EDGE_DET_M 0x00030000 +#define IOC_IOCFG15_EDGE_DET_S 16 +#define IOC_IOCFG15_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG15_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG15_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG15_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -4796,21 +4796,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG15_PULL_CTL_W 2 -#define IOC_IOCFG15_PULL_CTL_M 0x00006000 -#define IOC_IOCFG15_PULL_CTL_S 13 -#define IOC_IOCFG15_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG15_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG15_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG15_PULL_CTL_W 2 +#define IOC_IOCFG15_PULL_CTL_M 0x00006000 +#define IOC_IOCFG15_PULL_CTL_S 13 +#define IOC_IOCFG15_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG15_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG15_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG15_SLEW_RED 0x00001000 -#define IOC_IOCFG15_SLEW_RED_BITN 12 -#define IOC_IOCFG15_SLEW_RED_M 0x00001000 -#define IOC_IOCFG15_SLEW_RED_S 12 +#define IOC_IOCFG15_SLEW_RED 0x00001000 +#define IOC_IOCFG15_SLEW_RED_BITN 12 +#define IOC_IOCFG15_SLEW_RED_M 0x00001000 +#define IOC_IOCFG15_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -4823,12 +4823,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG15_IOCURR_W 2 -#define IOC_IOCFG15_IOCURR_M 0x00000C00 -#define IOC_IOCFG15_IOCURR_S 10 -#define IOC_IOCFG15_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG15_IOCURR_4MA 0x00000400 -#define IOC_IOCFG15_IOCURR_2MA 0x00000000 +#define IOC_IOCFG15_IOCURR_W 2 +#define IOC_IOCFG15_IOCURR_M 0x00000C00 +#define IOC_IOCFG15_IOCURR_S 10 +#define IOC_IOCFG15_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG15_IOCURR_4MA 0x00000400 +#define IOC_IOCFG15_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -4847,13 +4847,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG15_IOSTR_W 2 -#define IOC_IOCFG15_IOSTR_M 0x00000300 -#define IOC_IOCFG15_IOSTR_S 8 -#define IOC_IOCFG15_IOSTR_MAX 0x00000300 -#define IOC_IOCFG15_IOSTR_MED 0x00000200 -#define IOC_IOCFG15_IOSTR_MIN 0x00000100 -#define IOC_IOCFG15_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG15_IOSTR_W 2 +#define IOC_IOCFG15_IOSTR_M 0x00000300 +#define IOC_IOCFG15_IOSTR_S 8 +#define IOC_IOCFG15_IOSTR_MAX 0x00000300 +#define IOC_IOCFG15_IOSTR_MED 0x00000200 +#define IOC_IOCFG15_IOSTR_MIN 0x00000100 +#define IOC_IOCFG15_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -4941,51 +4941,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG15_PORT_ID_W 6 -#define IOC_IOCFG15_PORT_ID_M 0x0000003F -#define IOC_IOCFG15_PORT_ID_S 0 -#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG15_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG15_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG15_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG15_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG15_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG15_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG15_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG15_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG15_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG15_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG15_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG15_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG15_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG15_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG15_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG15_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG15_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG15_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG15_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG15_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG15_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG15_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG15_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG15_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG15_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG15_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG15_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG15_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG15_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG15_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG15_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG15_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG15_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG15_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG15_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG15_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG15_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG15_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG15_PORT_ID_W 6 +#define IOC_IOCFG15_PORT_ID_M 0x0000003F +#define IOC_IOCFG15_PORT_ID_S 0 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG15_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG15_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG15_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG15_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG15_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG15_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG15_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG15_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG15_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG15_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG15_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG15_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG15_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG15_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG15_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG15_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG15_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG15_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG15_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG15_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG15_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG15_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG15_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG15_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG15_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG15_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG15_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG15_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG15_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG15_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG15_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG15_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG15_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG15_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG15_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG15_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -4996,10 +4996,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG16_HYST_EN 0x40000000 -#define IOC_IOCFG16_HYST_EN_BITN 30 -#define IOC_IOCFG16_HYST_EN_M 0x40000000 -#define IOC_IOCFG16_HYST_EN_S 30 +#define IOC_IOCFG16_HYST_EN 0x40000000 +#define IOC_IOCFG16_HYST_EN_BITN 30 +#define IOC_IOCFG16_HYST_EN_M 0x40000000 +#define IOC_IOCFG16_HYST_EN_S 30 // Field: [29] IE // @@ -5008,10 +5008,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG16_IE 0x20000000 -#define IOC_IOCFG16_IE_BITN 29 -#define IOC_IOCFG16_IE_M 0x20000000 -#define IOC_IOCFG16_IE_S 29 +#define IOC_IOCFG16_IE 0x20000000 +#define IOC_IOCFG16_IE_BITN 29 +#define IOC_IOCFG16_IE_M 0x20000000 +#define IOC_IOCFG16_IE_S 29 // Field: [28:27] WU_CFG // @@ -5033,9 +5033,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG16_WU_CFG_W 2 -#define IOC_IOCFG16_WU_CFG_M 0x18000000 -#define IOC_IOCFG16_WU_CFG_S 27 +#define IOC_IOCFG16_WU_CFG_W 2 +#define IOC_IOCFG16_WU_CFG_M 0x18000000 +#define IOC_IOCFG16_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -5056,25 +5056,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG16_IOMODE_W 3 -#define IOC_IOCFG16_IOMODE_M 0x07000000 -#define IOC_IOCFG16_IOMODE_S 24 -#define IOC_IOCFG16_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG16_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG16_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG16_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG16_IOMODE_INV 0x01000000 -#define IOC_IOCFG16_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG16_IOMODE_W 3 +#define IOC_IOCFG16_IOMODE_M 0x07000000 +#define IOC_IOCFG16_IOMODE_S 24 +#define IOC_IOCFG16_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG16_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG16_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG16_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG16_IOMODE_INV 0x01000000 +#define IOC_IOCFG16_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG16_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG16_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG16_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG16_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG16_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG16_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG16_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG16_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -5084,13 +5084,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG16_EDGE_DET_W 2 -#define IOC_IOCFG16_EDGE_DET_M 0x00030000 -#define IOC_IOCFG16_EDGE_DET_S 16 -#define IOC_IOCFG16_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG16_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG16_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG16_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG16_EDGE_DET_W 2 +#define IOC_IOCFG16_EDGE_DET_M 0x00030000 +#define IOC_IOCFG16_EDGE_DET_S 16 +#define IOC_IOCFG16_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG16_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG16_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG16_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -5099,21 +5099,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG16_PULL_CTL_W 2 -#define IOC_IOCFG16_PULL_CTL_M 0x00006000 -#define IOC_IOCFG16_PULL_CTL_S 13 -#define IOC_IOCFG16_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG16_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG16_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG16_PULL_CTL_W 2 +#define IOC_IOCFG16_PULL_CTL_M 0x00006000 +#define IOC_IOCFG16_PULL_CTL_S 13 +#define IOC_IOCFG16_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG16_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG16_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG16_SLEW_RED 0x00001000 -#define IOC_IOCFG16_SLEW_RED_BITN 12 -#define IOC_IOCFG16_SLEW_RED_M 0x00001000 -#define IOC_IOCFG16_SLEW_RED_S 12 +#define IOC_IOCFG16_SLEW_RED 0x00001000 +#define IOC_IOCFG16_SLEW_RED_BITN 12 +#define IOC_IOCFG16_SLEW_RED_M 0x00001000 +#define IOC_IOCFG16_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -5126,12 +5126,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG16_IOCURR_W 2 -#define IOC_IOCFG16_IOCURR_M 0x00000C00 -#define IOC_IOCFG16_IOCURR_S 10 -#define IOC_IOCFG16_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG16_IOCURR_4MA 0x00000400 -#define IOC_IOCFG16_IOCURR_2MA 0x00000000 +#define IOC_IOCFG16_IOCURR_W 2 +#define IOC_IOCFG16_IOCURR_M 0x00000C00 +#define IOC_IOCFG16_IOCURR_S 10 +#define IOC_IOCFG16_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG16_IOCURR_4MA 0x00000400 +#define IOC_IOCFG16_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -5150,13 +5150,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG16_IOSTR_W 2 -#define IOC_IOCFG16_IOSTR_M 0x00000300 -#define IOC_IOCFG16_IOSTR_S 8 -#define IOC_IOCFG16_IOSTR_MAX 0x00000300 -#define IOC_IOCFG16_IOSTR_MED 0x00000200 -#define IOC_IOCFG16_IOSTR_MIN 0x00000100 -#define IOC_IOCFG16_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG16_IOSTR_W 2 +#define IOC_IOCFG16_IOSTR_M 0x00000300 +#define IOC_IOCFG16_IOSTR_S 8 +#define IOC_IOCFG16_IOSTR_MAX 0x00000300 +#define IOC_IOCFG16_IOSTR_MED 0x00000200 +#define IOC_IOCFG16_IOSTR_MIN 0x00000100 +#define IOC_IOCFG16_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -5244,51 +5244,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG16_PORT_ID_W 6 -#define IOC_IOCFG16_PORT_ID_M 0x0000003F -#define IOC_IOCFG16_PORT_ID_S 0 -#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG16_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG16_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG16_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG16_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG16_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG16_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG16_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG16_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG16_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG16_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG16_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG16_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG16_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG16_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG16_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG16_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG16_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG16_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG16_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG16_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG16_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG16_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG16_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG16_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG16_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG16_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG16_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG16_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG16_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG16_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG16_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG16_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG16_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG16_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG16_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG16_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG16_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG16_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG16_PORT_ID_W 6 +#define IOC_IOCFG16_PORT_ID_M 0x0000003F +#define IOC_IOCFG16_PORT_ID_S 0 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG16_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG16_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG16_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG16_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG16_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG16_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG16_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG16_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG16_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG16_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG16_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG16_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG16_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG16_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG16_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG16_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG16_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG16_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG16_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG16_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG16_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG16_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG16_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG16_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG16_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG16_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG16_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG16_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG16_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG16_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG16_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG16_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG16_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG16_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG16_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG16_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -5299,10 +5299,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG17_HYST_EN 0x40000000 -#define IOC_IOCFG17_HYST_EN_BITN 30 -#define IOC_IOCFG17_HYST_EN_M 0x40000000 -#define IOC_IOCFG17_HYST_EN_S 30 +#define IOC_IOCFG17_HYST_EN 0x40000000 +#define IOC_IOCFG17_HYST_EN_BITN 30 +#define IOC_IOCFG17_HYST_EN_M 0x40000000 +#define IOC_IOCFG17_HYST_EN_S 30 // Field: [29] IE // @@ -5311,10 +5311,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG17_IE 0x20000000 -#define IOC_IOCFG17_IE_BITN 29 -#define IOC_IOCFG17_IE_M 0x20000000 -#define IOC_IOCFG17_IE_S 29 +#define IOC_IOCFG17_IE 0x20000000 +#define IOC_IOCFG17_IE_BITN 29 +#define IOC_IOCFG17_IE_M 0x20000000 +#define IOC_IOCFG17_IE_S 29 // Field: [28:27] WU_CFG // @@ -5336,9 +5336,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG17_WU_CFG_W 2 -#define IOC_IOCFG17_WU_CFG_M 0x18000000 -#define IOC_IOCFG17_WU_CFG_S 27 +#define IOC_IOCFG17_WU_CFG_W 2 +#define IOC_IOCFG17_WU_CFG_M 0x18000000 +#define IOC_IOCFG17_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -5359,25 +5359,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG17_IOMODE_W 3 -#define IOC_IOCFG17_IOMODE_M 0x07000000 -#define IOC_IOCFG17_IOMODE_S 24 -#define IOC_IOCFG17_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG17_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG17_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG17_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG17_IOMODE_INV 0x01000000 -#define IOC_IOCFG17_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG17_IOMODE_W 3 +#define IOC_IOCFG17_IOMODE_M 0x07000000 +#define IOC_IOCFG17_IOMODE_S 24 +#define IOC_IOCFG17_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG17_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG17_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG17_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG17_IOMODE_INV 0x01000000 +#define IOC_IOCFG17_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG17_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG17_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG17_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG17_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG17_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG17_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG17_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG17_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -5387,13 +5387,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG17_EDGE_DET_W 2 -#define IOC_IOCFG17_EDGE_DET_M 0x00030000 -#define IOC_IOCFG17_EDGE_DET_S 16 -#define IOC_IOCFG17_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG17_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG17_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG17_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG17_EDGE_DET_W 2 +#define IOC_IOCFG17_EDGE_DET_M 0x00030000 +#define IOC_IOCFG17_EDGE_DET_S 16 +#define IOC_IOCFG17_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG17_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG17_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG17_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -5402,21 +5402,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG17_PULL_CTL_W 2 -#define IOC_IOCFG17_PULL_CTL_M 0x00006000 -#define IOC_IOCFG17_PULL_CTL_S 13 -#define IOC_IOCFG17_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG17_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG17_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG17_PULL_CTL_W 2 +#define IOC_IOCFG17_PULL_CTL_M 0x00006000 +#define IOC_IOCFG17_PULL_CTL_S 13 +#define IOC_IOCFG17_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG17_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG17_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG17_SLEW_RED 0x00001000 -#define IOC_IOCFG17_SLEW_RED_BITN 12 -#define IOC_IOCFG17_SLEW_RED_M 0x00001000 -#define IOC_IOCFG17_SLEW_RED_S 12 +#define IOC_IOCFG17_SLEW_RED 0x00001000 +#define IOC_IOCFG17_SLEW_RED_BITN 12 +#define IOC_IOCFG17_SLEW_RED_M 0x00001000 +#define IOC_IOCFG17_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -5429,12 +5429,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG17_IOCURR_W 2 -#define IOC_IOCFG17_IOCURR_M 0x00000C00 -#define IOC_IOCFG17_IOCURR_S 10 -#define IOC_IOCFG17_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG17_IOCURR_4MA 0x00000400 -#define IOC_IOCFG17_IOCURR_2MA 0x00000000 +#define IOC_IOCFG17_IOCURR_W 2 +#define IOC_IOCFG17_IOCURR_M 0x00000C00 +#define IOC_IOCFG17_IOCURR_S 10 +#define IOC_IOCFG17_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG17_IOCURR_4MA 0x00000400 +#define IOC_IOCFG17_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -5453,13 +5453,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG17_IOSTR_W 2 -#define IOC_IOCFG17_IOSTR_M 0x00000300 -#define IOC_IOCFG17_IOSTR_S 8 -#define IOC_IOCFG17_IOSTR_MAX 0x00000300 -#define IOC_IOCFG17_IOSTR_MED 0x00000200 -#define IOC_IOCFG17_IOSTR_MIN 0x00000100 -#define IOC_IOCFG17_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG17_IOSTR_W 2 +#define IOC_IOCFG17_IOSTR_M 0x00000300 +#define IOC_IOCFG17_IOSTR_S 8 +#define IOC_IOCFG17_IOSTR_MAX 0x00000300 +#define IOC_IOCFG17_IOSTR_MED 0x00000200 +#define IOC_IOCFG17_IOSTR_MIN 0x00000100 +#define IOC_IOCFG17_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -5547,51 +5547,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG17_PORT_ID_W 6 -#define IOC_IOCFG17_PORT_ID_M 0x0000003F -#define IOC_IOCFG17_PORT_ID_S 0 -#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG17_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG17_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG17_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG17_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG17_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG17_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG17_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG17_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG17_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG17_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG17_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG17_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG17_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG17_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG17_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG17_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG17_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG17_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG17_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG17_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG17_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG17_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG17_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG17_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG17_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG17_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG17_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG17_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG17_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG17_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG17_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG17_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG17_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG17_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG17_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG17_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG17_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG17_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG17_PORT_ID_W 6 +#define IOC_IOCFG17_PORT_ID_M 0x0000003F +#define IOC_IOCFG17_PORT_ID_S 0 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG17_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG17_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG17_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG17_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG17_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG17_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG17_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG17_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG17_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG17_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG17_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG17_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG17_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG17_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG17_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG17_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG17_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG17_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG17_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG17_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG17_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG17_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG17_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG17_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG17_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG17_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG17_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG17_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG17_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG17_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG17_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG17_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG17_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG17_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG17_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG17_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -5602,10 +5602,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG18_HYST_EN 0x40000000 -#define IOC_IOCFG18_HYST_EN_BITN 30 -#define IOC_IOCFG18_HYST_EN_M 0x40000000 -#define IOC_IOCFG18_HYST_EN_S 30 +#define IOC_IOCFG18_HYST_EN 0x40000000 +#define IOC_IOCFG18_HYST_EN_BITN 30 +#define IOC_IOCFG18_HYST_EN_M 0x40000000 +#define IOC_IOCFG18_HYST_EN_S 30 // Field: [29] IE // @@ -5614,10 +5614,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG18_IE 0x20000000 -#define IOC_IOCFG18_IE_BITN 29 -#define IOC_IOCFG18_IE_M 0x20000000 -#define IOC_IOCFG18_IE_S 29 +#define IOC_IOCFG18_IE 0x20000000 +#define IOC_IOCFG18_IE_BITN 29 +#define IOC_IOCFG18_IE_M 0x20000000 +#define IOC_IOCFG18_IE_S 29 // Field: [28:27] WU_CFG // @@ -5639,9 +5639,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG18_WU_CFG_W 2 -#define IOC_IOCFG18_WU_CFG_M 0x18000000 -#define IOC_IOCFG18_WU_CFG_S 27 +#define IOC_IOCFG18_WU_CFG_W 2 +#define IOC_IOCFG18_WU_CFG_M 0x18000000 +#define IOC_IOCFG18_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -5662,25 +5662,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG18_IOMODE_W 3 -#define IOC_IOCFG18_IOMODE_M 0x07000000 -#define IOC_IOCFG18_IOMODE_S 24 -#define IOC_IOCFG18_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG18_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG18_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG18_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG18_IOMODE_INV 0x01000000 -#define IOC_IOCFG18_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG18_IOMODE_W 3 +#define IOC_IOCFG18_IOMODE_M 0x07000000 +#define IOC_IOCFG18_IOMODE_S 24 +#define IOC_IOCFG18_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG18_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG18_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG18_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG18_IOMODE_INV 0x01000000 +#define IOC_IOCFG18_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG18_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG18_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG18_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG18_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG18_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG18_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG18_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG18_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -5690,13 +5690,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG18_EDGE_DET_W 2 -#define IOC_IOCFG18_EDGE_DET_M 0x00030000 -#define IOC_IOCFG18_EDGE_DET_S 16 -#define IOC_IOCFG18_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG18_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG18_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG18_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG18_EDGE_DET_W 2 +#define IOC_IOCFG18_EDGE_DET_M 0x00030000 +#define IOC_IOCFG18_EDGE_DET_S 16 +#define IOC_IOCFG18_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG18_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG18_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG18_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -5705,21 +5705,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG18_PULL_CTL_W 2 -#define IOC_IOCFG18_PULL_CTL_M 0x00006000 -#define IOC_IOCFG18_PULL_CTL_S 13 -#define IOC_IOCFG18_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG18_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG18_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG18_PULL_CTL_W 2 +#define IOC_IOCFG18_PULL_CTL_M 0x00006000 +#define IOC_IOCFG18_PULL_CTL_S 13 +#define IOC_IOCFG18_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG18_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG18_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG18_SLEW_RED 0x00001000 -#define IOC_IOCFG18_SLEW_RED_BITN 12 -#define IOC_IOCFG18_SLEW_RED_M 0x00001000 -#define IOC_IOCFG18_SLEW_RED_S 12 +#define IOC_IOCFG18_SLEW_RED 0x00001000 +#define IOC_IOCFG18_SLEW_RED_BITN 12 +#define IOC_IOCFG18_SLEW_RED_M 0x00001000 +#define IOC_IOCFG18_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -5732,12 +5732,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG18_IOCURR_W 2 -#define IOC_IOCFG18_IOCURR_M 0x00000C00 -#define IOC_IOCFG18_IOCURR_S 10 -#define IOC_IOCFG18_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG18_IOCURR_4MA 0x00000400 -#define IOC_IOCFG18_IOCURR_2MA 0x00000000 +#define IOC_IOCFG18_IOCURR_W 2 +#define IOC_IOCFG18_IOCURR_M 0x00000C00 +#define IOC_IOCFG18_IOCURR_S 10 +#define IOC_IOCFG18_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG18_IOCURR_4MA 0x00000400 +#define IOC_IOCFG18_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -5756,13 +5756,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG18_IOSTR_W 2 -#define IOC_IOCFG18_IOSTR_M 0x00000300 -#define IOC_IOCFG18_IOSTR_S 8 -#define IOC_IOCFG18_IOSTR_MAX 0x00000300 -#define IOC_IOCFG18_IOSTR_MED 0x00000200 -#define IOC_IOCFG18_IOSTR_MIN 0x00000100 -#define IOC_IOCFG18_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG18_IOSTR_W 2 +#define IOC_IOCFG18_IOSTR_M 0x00000300 +#define IOC_IOCFG18_IOSTR_S 8 +#define IOC_IOCFG18_IOSTR_MAX 0x00000300 +#define IOC_IOCFG18_IOSTR_MED 0x00000200 +#define IOC_IOCFG18_IOSTR_MIN 0x00000100 +#define IOC_IOCFG18_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -5850,51 +5850,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG18_PORT_ID_W 6 -#define IOC_IOCFG18_PORT_ID_M 0x0000003F -#define IOC_IOCFG18_PORT_ID_S 0 -#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG18_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG18_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG18_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG18_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG18_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG18_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG18_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG18_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG18_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG18_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG18_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG18_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG18_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG18_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG18_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG18_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG18_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG18_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG18_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG18_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG18_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG18_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG18_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG18_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG18_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG18_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG18_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG18_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG18_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG18_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG18_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG18_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG18_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG18_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG18_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG18_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG18_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG18_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG18_PORT_ID_W 6 +#define IOC_IOCFG18_PORT_ID_M 0x0000003F +#define IOC_IOCFG18_PORT_ID_S 0 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG18_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG18_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG18_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG18_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG18_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG18_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG18_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG18_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG18_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG18_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG18_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG18_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG18_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG18_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG18_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG18_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG18_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG18_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG18_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG18_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG18_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG18_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG18_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG18_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG18_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG18_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG18_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG18_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG18_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG18_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG18_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG18_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG18_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG18_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG18_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG18_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -5905,10 +5905,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG19_HYST_EN 0x40000000 -#define IOC_IOCFG19_HYST_EN_BITN 30 -#define IOC_IOCFG19_HYST_EN_M 0x40000000 -#define IOC_IOCFG19_HYST_EN_S 30 +#define IOC_IOCFG19_HYST_EN 0x40000000 +#define IOC_IOCFG19_HYST_EN_BITN 30 +#define IOC_IOCFG19_HYST_EN_M 0x40000000 +#define IOC_IOCFG19_HYST_EN_S 30 // Field: [29] IE // @@ -5917,10 +5917,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG19_IE 0x20000000 -#define IOC_IOCFG19_IE_BITN 29 -#define IOC_IOCFG19_IE_M 0x20000000 -#define IOC_IOCFG19_IE_S 29 +#define IOC_IOCFG19_IE 0x20000000 +#define IOC_IOCFG19_IE_BITN 29 +#define IOC_IOCFG19_IE_M 0x20000000 +#define IOC_IOCFG19_IE_S 29 // Field: [28:27] WU_CFG // @@ -5942,9 +5942,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG19_WU_CFG_W 2 -#define IOC_IOCFG19_WU_CFG_M 0x18000000 -#define IOC_IOCFG19_WU_CFG_S 27 +#define IOC_IOCFG19_WU_CFG_W 2 +#define IOC_IOCFG19_WU_CFG_M 0x18000000 +#define IOC_IOCFG19_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -5965,25 +5965,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG19_IOMODE_W 3 -#define IOC_IOCFG19_IOMODE_M 0x07000000 -#define IOC_IOCFG19_IOMODE_S 24 -#define IOC_IOCFG19_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG19_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG19_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG19_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG19_IOMODE_INV 0x01000000 -#define IOC_IOCFG19_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG19_IOMODE_W 3 +#define IOC_IOCFG19_IOMODE_M 0x07000000 +#define IOC_IOCFG19_IOMODE_S 24 +#define IOC_IOCFG19_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG19_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG19_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG19_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG19_IOMODE_INV 0x01000000 +#define IOC_IOCFG19_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG19_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG19_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG19_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG19_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG19_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG19_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG19_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG19_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -5993,13 +5993,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG19_EDGE_DET_W 2 -#define IOC_IOCFG19_EDGE_DET_M 0x00030000 -#define IOC_IOCFG19_EDGE_DET_S 16 -#define IOC_IOCFG19_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG19_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG19_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG19_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG19_EDGE_DET_W 2 +#define IOC_IOCFG19_EDGE_DET_M 0x00030000 +#define IOC_IOCFG19_EDGE_DET_S 16 +#define IOC_IOCFG19_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG19_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG19_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG19_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -6008,21 +6008,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG19_PULL_CTL_W 2 -#define IOC_IOCFG19_PULL_CTL_M 0x00006000 -#define IOC_IOCFG19_PULL_CTL_S 13 -#define IOC_IOCFG19_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG19_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG19_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG19_PULL_CTL_W 2 +#define IOC_IOCFG19_PULL_CTL_M 0x00006000 +#define IOC_IOCFG19_PULL_CTL_S 13 +#define IOC_IOCFG19_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG19_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG19_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG19_SLEW_RED 0x00001000 -#define IOC_IOCFG19_SLEW_RED_BITN 12 -#define IOC_IOCFG19_SLEW_RED_M 0x00001000 -#define IOC_IOCFG19_SLEW_RED_S 12 +#define IOC_IOCFG19_SLEW_RED 0x00001000 +#define IOC_IOCFG19_SLEW_RED_BITN 12 +#define IOC_IOCFG19_SLEW_RED_M 0x00001000 +#define IOC_IOCFG19_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -6035,12 +6035,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG19_IOCURR_W 2 -#define IOC_IOCFG19_IOCURR_M 0x00000C00 -#define IOC_IOCFG19_IOCURR_S 10 -#define IOC_IOCFG19_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG19_IOCURR_4MA 0x00000400 -#define IOC_IOCFG19_IOCURR_2MA 0x00000000 +#define IOC_IOCFG19_IOCURR_W 2 +#define IOC_IOCFG19_IOCURR_M 0x00000C00 +#define IOC_IOCFG19_IOCURR_S 10 +#define IOC_IOCFG19_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG19_IOCURR_4MA 0x00000400 +#define IOC_IOCFG19_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -6059,13 +6059,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG19_IOSTR_W 2 -#define IOC_IOCFG19_IOSTR_M 0x00000300 -#define IOC_IOCFG19_IOSTR_S 8 -#define IOC_IOCFG19_IOSTR_MAX 0x00000300 -#define IOC_IOCFG19_IOSTR_MED 0x00000200 -#define IOC_IOCFG19_IOSTR_MIN 0x00000100 -#define IOC_IOCFG19_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG19_IOSTR_W 2 +#define IOC_IOCFG19_IOSTR_M 0x00000300 +#define IOC_IOCFG19_IOSTR_S 8 +#define IOC_IOCFG19_IOSTR_MAX 0x00000300 +#define IOC_IOCFG19_IOSTR_MED 0x00000200 +#define IOC_IOCFG19_IOSTR_MIN 0x00000100 +#define IOC_IOCFG19_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -6153,51 +6153,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG19_PORT_ID_W 6 -#define IOC_IOCFG19_PORT_ID_M 0x0000003F -#define IOC_IOCFG19_PORT_ID_S 0 -#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG19_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG19_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG19_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG19_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG19_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG19_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG19_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG19_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG19_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG19_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG19_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG19_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG19_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG19_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG19_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG19_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG19_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG19_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG19_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG19_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG19_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG19_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG19_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG19_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG19_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG19_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG19_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG19_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG19_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG19_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG19_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG19_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG19_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG19_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG19_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG19_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG19_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG19_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG19_PORT_ID_W 6 +#define IOC_IOCFG19_PORT_ID_M 0x0000003F +#define IOC_IOCFG19_PORT_ID_S 0 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG19_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG19_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG19_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG19_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG19_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG19_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG19_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG19_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG19_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG19_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG19_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG19_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG19_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG19_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG19_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG19_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG19_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG19_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG19_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG19_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG19_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG19_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG19_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG19_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG19_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG19_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG19_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG19_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG19_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG19_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG19_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG19_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG19_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG19_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG19_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG19_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -6208,10 +6208,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG20_HYST_EN 0x40000000 -#define IOC_IOCFG20_HYST_EN_BITN 30 -#define IOC_IOCFG20_HYST_EN_M 0x40000000 -#define IOC_IOCFG20_HYST_EN_S 30 +#define IOC_IOCFG20_HYST_EN 0x40000000 +#define IOC_IOCFG20_HYST_EN_BITN 30 +#define IOC_IOCFG20_HYST_EN_M 0x40000000 +#define IOC_IOCFG20_HYST_EN_S 30 // Field: [29] IE // @@ -6220,10 +6220,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG20_IE 0x20000000 -#define IOC_IOCFG20_IE_BITN 29 -#define IOC_IOCFG20_IE_M 0x20000000 -#define IOC_IOCFG20_IE_S 29 +#define IOC_IOCFG20_IE 0x20000000 +#define IOC_IOCFG20_IE_BITN 29 +#define IOC_IOCFG20_IE_M 0x20000000 +#define IOC_IOCFG20_IE_S 29 // Field: [28:27] WU_CFG // @@ -6245,9 +6245,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG20_WU_CFG_W 2 -#define IOC_IOCFG20_WU_CFG_M 0x18000000 -#define IOC_IOCFG20_WU_CFG_S 27 +#define IOC_IOCFG20_WU_CFG_W 2 +#define IOC_IOCFG20_WU_CFG_M 0x18000000 +#define IOC_IOCFG20_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -6268,25 +6268,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG20_IOMODE_W 3 -#define IOC_IOCFG20_IOMODE_M 0x07000000 -#define IOC_IOCFG20_IOMODE_S 24 -#define IOC_IOCFG20_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG20_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG20_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG20_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG20_IOMODE_INV 0x01000000 -#define IOC_IOCFG20_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG20_IOMODE_W 3 +#define IOC_IOCFG20_IOMODE_M 0x07000000 +#define IOC_IOCFG20_IOMODE_S 24 +#define IOC_IOCFG20_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG20_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG20_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG20_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG20_IOMODE_INV 0x01000000 +#define IOC_IOCFG20_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG20_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG20_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG20_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG20_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG20_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG20_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG20_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG20_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -6296,13 +6296,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG20_EDGE_DET_W 2 -#define IOC_IOCFG20_EDGE_DET_M 0x00030000 -#define IOC_IOCFG20_EDGE_DET_S 16 -#define IOC_IOCFG20_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG20_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG20_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG20_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG20_EDGE_DET_W 2 +#define IOC_IOCFG20_EDGE_DET_M 0x00030000 +#define IOC_IOCFG20_EDGE_DET_S 16 +#define IOC_IOCFG20_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG20_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG20_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG20_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -6311,21 +6311,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG20_PULL_CTL_W 2 -#define IOC_IOCFG20_PULL_CTL_M 0x00006000 -#define IOC_IOCFG20_PULL_CTL_S 13 -#define IOC_IOCFG20_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG20_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG20_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG20_PULL_CTL_W 2 +#define IOC_IOCFG20_PULL_CTL_M 0x00006000 +#define IOC_IOCFG20_PULL_CTL_S 13 +#define IOC_IOCFG20_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG20_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG20_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG20_SLEW_RED 0x00001000 -#define IOC_IOCFG20_SLEW_RED_BITN 12 -#define IOC_IOCFG20_SLEW_RED_M 0x00001000 -#define IOC_IOCFG20_SLEW_RED_S 12 +#define IOC_IOCFG20_SLEW_RED 0x00001000 +#define IOC_IOCFG20_SLEW_RED_BITN 12 +#define IOC_IOCFG20_SLEW_RED_M 0x00001000 +#define IOC_IOCFG20_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -6338,12 +6338,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG20_IOCURR_W 2 -#define IOC_IOCFG20_IOCURR_M 0x00000C00 -#define IOC_IOCFG20_IOCURR_S 10 -#define IOC_IOCFG20_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG20_IOCURR_4MA 0x00000400 -#define IOC_IOCFG20_IOCURR_2MA 0x00000000 +#define IOC_IOCFG20_IOCURR_W 2 +#define IOC_IOCFG20_IOCURR_M 0x00000C00 +#define IOC_IOCFG20_IOCURR_S 10 +#define IOC_IOCFG20_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG20_IOCURR_4MA 0x00000400 +#define IOC_IOCFG20_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -6362,13 +6362,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG20_IOSTR_W 2 -#define IOC_IOCFG20_IOSTR_M 0x00000300 -#define IOC_IOCFG20_IOSTR_S 8 -#define IOC_IOCFG20_IOSTR_MAX 0x00000300 -#define IOC_IOCFG20_IOSTR_MED 0x00000200 -#define IOC_IOCFG20_IOSTR_MIN 0x00000100 -#define IOC_IOCFG20_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG20_IOSTR_W 2 +#define IOC_IOCFG20_IOSTR_M 0x00000300 +#define IOC_IOCFG20_IOSTR_S 8 +#define IOC_IOCFG20_IOSTR_MAX 0x00000300 +#define IOC_IOCFG20_IOSTR_MED 0x00000200 +#define IOC_IOCFG20_IOSTR_MIN 0x00000100 +#define IOC_IOCFG20_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -6456,51 +6456,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG20_PORT_ID_W 6 -#define IOC_IOCFG20_PORT_ID_M 0x0000003F -#define IOC_IOCFG20_PORT_ID_S 0 -#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG20_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG20_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG20_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG20_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG20_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG20_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG20_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG20_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG20_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG20_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG20_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG20_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG20_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG20_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG20_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG20_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG20_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG20_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG20_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG20_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG20_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG20_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG20_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG20_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG20_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG20_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG20_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG20_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG20_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG20_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG20_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG20_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG20_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG20_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG20_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG20_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG20_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG20_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG20_PORT_ID_W 6 +#define IOC_IOCFG20_PORT_ID_M 0x0000003F +#define IOC_IOCFG20_PORT_ID_S 0 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG20_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG20_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG20_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG20_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG20_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG20_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG20_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG20_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG20_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG20_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG20_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG20_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG20_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG20_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG20_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG20_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG20_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG20_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG20_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG20_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG20_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG20_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG20_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG20_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG20_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG20_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG20_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG20_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG20_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG20_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG20_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG20_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG20_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG20_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG20_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG20_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -6511,10 +6511,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG21_HYST_EN 0x40000000 -#define IOC_IOCFG21_HYST_EN_BITN 30 -#define IOC_IOCFG21_HYST_EN_M 0x40000000 -#define IOC_IOCFG21_HYST_EN_S 30 +#define IOC_IOCFG21_HYST_EN 0x40000000 +#define IOC_IOCFG21_HYST_EN_BITN 30 +#define IOC_IOCFG21_HYST_EN_M 0x40000000 +#define IOC_IOCFG21_HYST_EN_S 30 // Field: [29] IE // @@ -6523,10 +6523,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG21_IE 0x20000000 -#define IOC_IOCFG21_IE_BITN 29 -#define IOC_IOCFG21_IE_M 0x20000000 -#define IOC_IOCFG21_IE_S 29 +#define IOC_IOCFG21_IE 0x20000000 +#define IOC_IOCFG21_IE_BITN 29 +#define IOC_IOCFG21_IE_M 0x20000000 +#define IOC_IOCFG21_IE_S 29 // Field: [28:27] WU_CFG // @@ -6548,9 +6548,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG21_WU_CFG_W 2 -#define IOC_IOCFG21_WU_CFG_M 0x18000000 -#define IOC_IOCFG21_WU_CFG_S 27 +#define IOC_IOCFG21_WU_CFG_W 2 +#define IOC_IOCFG21_WU_CFG_M 0x18000000 +#define IOC_IOCFG21_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -6571,25 +6571,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG21_IOMODE_W 3 -#define IOC_IOCFG21_IOMODE_M 0x07000000 -#define IOC_IOCFG21_IOMODE_S 24 -#define IOC_IOCFG21_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG21_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG21_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG21_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG21_IOMODE_INV 0x01000000 -#define IOC_IOCFG21_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG21_IOMODE_W 3 +#define IOC_IOCFG21_IOMODE_M 0x07000000 +#define IOC_IOCFG21_IOMODE_S 24 +#define IOC_IOCFG21_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG21_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG21_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG21_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG21_IOMODE_INV 0x01000000 +#define IOC_IOCFG21_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG21_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG21_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG21_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG21_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG21_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG21_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG21_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG21_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -6599,13 +6599,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG21_EDGE_DET_W 2 -#define IOC_IOCFG21_EDGE_DET_M 0x00030000 -#define IOC_IOCFG21_EDGE_DET_S 16 -#define IOC_IOCFG21_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG21_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG21_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG21_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG21_EDGE_DET_W 2 +#define IOC_IOCFG21_EDGE_DET_M 0x00030000 +#define IOC_IOCFG21_EDGE_DET_S 16 +#define IOC_IOCFG21_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG21_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG21_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG21_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -6614,21 +6614,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG21_PULL_CTL_W 2 -#define IOC_IOCFG21_PULL_CTL_M 0x00006000 -#define IOC_IOCFG21_PULL_CTL_S 13 -#define IOC_IOCFG21_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG21_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG21_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG21_PULL_CTL_W 2 +#define IOC_IOCFG21_PULL_CTL_M 0x00006000 +#define IOC_IOCFG21_PULL_CTL_S 13 +#define IOC_IOCFG21_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG21_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG21_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG21_SLEW_RED 0x00001000 -#define IOC_IOCFG21_SLEW_RED_BITN 12 -#define IOC_IOCFG21_SLEW_RED_M 0x00001000 -#define IOC_IOCFG21_SLEW_RED_S 12 +#define IOC_IOCFG21_SLEW_RED 0x00001000 +#define IOC_IOCFG21_SLEW_RED_BITN 12 +#define IOC_IOCFG21_SLEW_RED_M 0x00001000 +#define IOC_IOCFG21_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -6641,12 +6641,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG21_IOCURR_W 2 -#define IOC_IOCFG21_IOCURR_M 0x00000C00 -#define IOC_IOCFG21_IOCURR_S 10 -#define IOC_IOCFG21_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG21_IOCURR_4MA 0x00000400 -#define IOC_IOCFG21_IOCURR_2MA 0x00000000 +#define IOC_IOCFG21_IOCURR_W 2 +#define IOC_IOCFG21_IOCURR_M 0x00000C00 +#define IOC_IOCFG21_IOCURR_S 10 +#define IOC_IOCFG21_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG21_IOCURR_4MA 0x00000400 +#define IOC_IOCFG21_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -6665,13 +6665,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG21_IOSTR_W 2 -#define IOC_IOCFG21_IOSTR_M 0x00000300 -#define IOC_IOCFG21_IOSTR_S 8 -#define IOC_IOCFG21_IOSTR_MAX 0x00000300 -#define IOC_IOCFG21_IOSTR_MED 0x00000200 -#define IOC_IOCFG21_IOSTR_MIN 0x00000100 -#define IOC_IOCFG21_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG21_IOSTR_W 2 +#define IOC_IOCFG21_IOSTR_M 0x00000300 +#define IOC_IOCFG21_IOSTR_S 8 +#define IOC_IOCFG21_IOSTR_MAX 0x00000300 +#define IOC_IOCFG21_IOSTR_MED 0x00000200 +#define IOC_IOCFG21_IOSTR_MIN 0x00000100 +#define IOC_IOCFG21_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -6759,51 +6759,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG21_PORT_ID_W 6 -#define IOC_IOCFG21_PORT_ID_M 0x0000003F -#define IOC_IOCFG21_PORT_ID_S 0 -#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG21_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG21_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG21_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG21_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG21_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG21_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG21_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG21_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG21_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG21_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG21_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG21_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG21_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG21_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG21_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG21_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG21_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG21_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG21_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG21_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG21_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG21_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG21_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG21_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG21_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG21_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG21_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG21_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG21_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG21_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG21_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG21_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG21_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG21_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG21_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG21_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG21_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG21_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG21_PORT_ID_W 6 +#define IOC_IOCFG21_PORT_ID_M 0x0000003F +#define IOC_IOCFG21_PORT_ID_S 0 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG21_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG21_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG21_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG21_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG21_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG21_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG21_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG21_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG21_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG21_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG21_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG21_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG21_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG21_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG21_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG21_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG21_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG21_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG21_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG21_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG21_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG21_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG21_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG21_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG21_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG21_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG21_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG21_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG21_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG21_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG21_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG21_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG21_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG21_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG21_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG21_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -6814,10 +6814,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG22_HYST_EN 0x40000000 -#define IOC_IOCFG22_HYST_EN_BITN 30 -#define IOC_IOCFG22_HYST_EN_M 0x40000000 -#define IOC_IOCFG22_HYST_EN_S 30 +#define IOC_IOCFG22_HYST_EN 0x40000000 +#define IOC_IOCFG22_HYST_EN_BITN 30 +#define IOC_IOCFG22_HYST_EN_M 0x40000000 +#define IOC_IOCFG22_HYST_EN_S 30 // Field: [29] IE // @@ -6826,10 +6826,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG22_IE 0x20000000 -#define IOC_IOCFG22_IE_BITN 29 -#define IOC_IOCFG22_IE_M 0x20000000 -#define IOC_IOCFG22_IE_S 29 +#define IOC_IOCFG22_IE 0x20000000 +#define IOC_IOCFG22_IE_BITN 29 +#define IOC_IOCFG22_IE_M 0x20000000 +#define IOC_IOCFG22_IE_S 29 // Field: [28:27] WU_CFG // @@ -6851,9 +6851,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG22_WU_CFG_W 2 -#define IOC_IOCFG22_WU_CFG_M 0x18000000 -#define IOC_IOCFG22_WU_CFG_S 27 +#define IOC_IOCFG22_WU_CFG_W 2 +#define IOC_IOCFG22_WU_CFG_M 0x18000000 +#define IOC_IOCFG22_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -6874,25 +6874,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG22_IOMODE_W 3 -#define IOC_IOCFG22_IOMODE_M 0x07000000 -#define IOC_IOCFG22_IOMODE_S 24 -#define IOC_IOCFG22_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG22_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG22_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG22_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG22_IOMODE_INV 0x01000000 -#define IOC_IOCFG22_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG22_IOMODE_W 3 +#define IOC_IOCFG22_IOMODE_M 0x07000000 +#define IOC_IOCFG22_IOMODE_S 24 +#define IOC_IOCFG22_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG22_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG22_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG22_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG22_IOMODE_INV 0x01000000 +#define IOC_IOCFG22_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG22_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG22_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG22_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG22_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG22_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG22_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG22_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG22_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -6902,13 +6902,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG22_EDGE_DET_W 2 -#define IOC_IOCFG22_EDGE_DET_M 0x00030000 -#define IOC_IOCFG22_EDGE_DET_S 16 -#define IOC_IOCFG22_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG22_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG22_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG22_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG22_EDGE_DET_W 2 +#define IOC_IOCFG22_EDGE_DET_M 0x00030000 +#define IOC_IOCFG22_EDGE_DET_S 16 +#define IOC_IOCFG22_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG22_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG22_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG22_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -6917,21 +6917,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG22_PULL_CTL_W 2 -#define IOC_IOCFG22_PULL_CTL_M 0x00006000 -#define IOC_IOCFG22_PULL_CTL_S 13 -#define IOC_IOCFG22_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG22_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG22_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG22_PULL_CTL_W 2 +#define IOC_IOCFG22_PULL_CTL_M 0x00006000 +#define IOC_IOCFG22_PULL_CTL_S 13 +#define IOC_IOCFG22_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG22_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG22_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG22_SLEW_RED 0x00001000 -#define IOC_IOCFG22_SLEW_RED_BITN 12 -#define IOC_IOCFG22_SLEW_RED_M 0x00001000 -#define IOC_IOCFG22_SLEW_RED_S 12 +#define IOC_IOCFG22_SLEW_RED 0x00001000 +#define IOC_IOCFG22_SLEW_RED_BITN 12 +#define IOC_IOCFG22_SLEW_RED_M 0x00001000 +#define IOC_IOCFG22_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -6944,12 +6944,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG22_IOCURR_W 2 -#define IOC_IOCFG22_IOCURR_M 0x00000C00 -#define IOC_IOCFG22_IOCURR_S 10 -#define IOC_IOCFG22_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG22_IOCURR_4MA 0x00000400 -#define IOC_IOCFG22_IOCURR_2MA 0x00000000 +#define IOC_IOCFG22_IOCURR_W 2 +#define IOC_IOCFG22_IOCURR_M 0x00000C00 +#define IOC_IOCFG22_IOCURR_S 10 +#define IOC_IOCFG22_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG22_IOCURR_4MA 0x00000400 +#define IOC_IOCFG22_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -6968,13 +6968,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG22_IOSTR_W 2 -#define IOC_IOCFG22_IOSTR_M 0x00000300 -#define IOC_IOCFG22_IOSTR_S 8 -#define IOC_IOCFG22_IOSTR_MAX 0x00000300 -#define IOC_IOCFG22_IOSTR_MED 0x00000200 -#define IOC_IOCFG22_IOSTR_MIN 0x00000100 -#define IOC_IOCFG22_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG22_IOSTR_W 2 +#define IOC_IOCFG22_IOSTR_M 0x00000300 +#define IOC_IOCFG22_IOSTR_S 8 +#define IOC_IOCFG22_IOSTR_MAX 0x00000300 +#define IOC_IOCFG22_IOSTR_MED 0x00000200 +#define IOC_IOCFG22_IOSTR_MIN 0x00000100 +#define IOC_IOCFG22_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -7062,51 +7062,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG22_PORT_ID_W 6 -#define IOC_IOCFG22_PORT_ID_M 0x0000003F -#define IOC_IOCFG22_PORT_ID_S 0 -#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG22_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG22_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG22_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG22_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG22_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG22_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG22_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG22_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG22_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG22_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG22_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG22_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG22_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG22_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG22_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG22_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG22_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG22_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG22_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG22_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG22_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG22_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG22_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG22_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG22_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG22_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG22_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG22_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG22_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG22_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG22_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG22_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG22_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG22_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG22_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG22_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG22_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG22_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG22_PORT_ID_W 6 +#define IOC_IOCFG22_PORT_ID_M 0x0000003F +#define IOC_IOCFG22_PORT_ID_S 0 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG22_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG22_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG22_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG22_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG22_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG22_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG22_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG22_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG22_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG22_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG22_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG22_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG22_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG22_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG22_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG22_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG22_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG22_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG22_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG22_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG22_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG22_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG22_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG22_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG22_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG22_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG22_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG22_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG22_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG22_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG22_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG22_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG22_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG22_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG22_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG22_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -7117,10 +7117,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG23_HYST_EN 0x40000000 -#define IOC_IOCFG23_HYST_EN_BITN 30 -#define IOC_IOCFG23_HYST_EN_M 0x40000000 -#define IOC_IOCFG23_HYST_EN_S 30 +#define IOC_IOCFG23_HYST_EN 0x40000000 +#define IOC_IOCFG23_HYST_EN_BITN 30 +#define IOC_IOCFG23_HYST_EN_M 0x40000000 +#define IOC_IOCFG23_HYST_EN_S 30 // Field: [29] IE // @@ -7129,10 +7129,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG23_IE 0x20000000 -#define IOC_IOCFG23_IE_BITN 29 -#define IOC_IOCFG23_IE_M 0x20000000 -#define IOC_IOCFG23_IE_S 29 +#define IOC_IOCFG23_IE 0x20000000 +#define IOC_IOCFG23_IE_BITN 29 +#define IOC_IOCFG23_IE_M 0x20000000 +#define IOC_IOCFG23_IE_S 29 // Field: [28:27] WU_CFG // @@ -7154,9 +7154,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG23_WU_CFG_W 2 -#define IOC_IOCFG23_WU_CFG_M 0x18000000 -#define IOC_IOCFG23_WU_CFG_S 27 +#define IOC_IOCFG23_WU_CFG_W 2 +#define IOC_IOCFG23_WU_CFG_M 0x18000000 +#define IOC_IOCFG23_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -7177,25 +7177,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG23_IOMODE_W 3 -#define IOC_IOCFG23_IOMODE_M 0x07000000 -#define IOC_IOCFG23_IOMODE_S 24 -#define IOC_IOCFG23_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG23_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG23_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG23_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG23_IOMODE_INV 0x01000000 -#define IOC_IOCFG23_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG23_IOMODE_W 3 +#define IOC_IOCFG23_IOMODE_M 0x07000000 +#define IOC_IOCFG23_IOMODE_S 24 +#define IOC_IOCFG23_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG23_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG23_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG23_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG23_IOMODE_INV 0x01000000 +#define IOC_IOCFG23_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG23_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG23_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG23_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG23_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG23_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG23_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG23_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG23_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -7205,13 +7205,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG23_EDGE_DET_W 2 -#define IOC_IOCFG23_EDGE_DET_M 0x00030000 -#define IOC_IOCFG23_EDGE_DET_S 16 -#define IOC_IOCFG23_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG23_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG23_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG23_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG23_EDGE_DET_W 2 +#define IOC_IOCFG23_EDGE_DET_M 0x00030000 +#define IOC_IOCFG23_EDGE_DET_S 16 +#define IOC_IOCFG23_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG23_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG23_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG23_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -7220,21 +7220,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG23_PULL_CTL_W 2 -#define IOC_IOCFG23_PULL_CTL_M 0x00006000 -#define IOC_IOCFG23_PULL_CTL_S 13 -#define IOC_IOCFG23_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG23_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG23_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG23_PULL_CTL_W 2 +#define IOC_IOCFG23_PULL_CTL_M 0x00006000 +#define IOC_IOCFG23_PULL_CTL_S 13 +#define IOC_IOCFG23_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG23_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG23_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG23_SLEW_RED 0x00001000 -#define IOC_IOCFG23_SLEW_RED_BITN 12 -#define IOC_IOCFG23_SLEW_RED_M 0x00001000 -#define IOC_IOCFG23_SLEW_RED_S 12 +#define IOC_IOCFG23_SLEW_RED 0x00001000 +#define IOC_IOCFG23_SLEW_RED_BITN 12 +#define IOC_IOCFG23_SLEW_RED_M 0x00001000 +#define IOC_IOCFG23_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -7247,12 +7247,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG23_IOCURR_W 2 -#define IOC_IOCFG23_IOCURR_M 0x00000C00 -#define IOC_IOCFG23_IOCURR_S 10 -#define IOC_IOCFG23_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG23_IOCURR_4MA 0x00000400 -#define IOC_IOCFG23_IOCURR_2MA 0x00000000 +#define IOC_IOCFG23_IOCURR_W 2 +#define IOC_IOCFG23_IOCURR_M 0x00000C00 +#define IOC_IOCFG23_IOCURR_S 10 +#define IOC_IOCFG23_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG23_IOCURR_4MA 0x00000400 +#define IOC_IOCFG23_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -7271,13 +7271,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG23_IOSTR_W 2 -#define IOC_IOCFG23_IOSTR_M 0x00000300 -#define IOC_IOCFG23_IOSTR_S 8 -#define IOC_IOCFG23_IOSTR_MAX 0x00000300 -#define IOC_IOCFG23_IOSTR_MED 0x00000200 -#define IOC_IOCFG23_IOSTR_MIN 0x00000100 -#define IOC_IOCFG23_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG23_IOSTR_W 2 +#define IOC_IOCFG23_IOSTR_M 0x00000300 +#define IOC_IOCFG23_IOSTR_S 8 +#define IOC_IOCFG23_IOSTR_MAX 0x00000300 +#define IOC_IOCFG23_IOSTR_MED 0x00000200 +#define IOC_IOCFG23_IOSTR_MIN 0x00000100 +#define IOC_IOCFG23_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -7365,51 +7365,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG23_PORT_ID_W 6 -#define IOC_IOCFG23_PORT_ID_M 0x0000003F -#define IOC_IOCFG23_PORT_ID_S 0 -#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG23_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG23_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG23_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG23_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG23_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG23_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG23_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG23_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG23_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG23_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG23_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG23_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG23_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG23_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG23_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG23_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG23_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG23_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG23_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG23_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG23_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG23_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG23_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG23_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG23_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG23_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG23_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG23_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG23_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG23_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG23_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG23_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG23_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG23_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG23_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG23_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG23_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG23_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG23_PORT_ID_W 6 +#define IOC_IOCFG23_PORT_ID_M 0x0000003F +#define IOC_IOCFG23_PORT_ID_S 0 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG23_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG23_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG23_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG23_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG23_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG23_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG23_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG23_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG23_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG23_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG23_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG23_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG23_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG23_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG23_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG23_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG23_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG23_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG23_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG23_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG23_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG23_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG23_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG23_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG23_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG23_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG23_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG23_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG23_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG23_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG23_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG23_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG23_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG23_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG23_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG23_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -7420,10 +7420,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG24_HYST_EN 0x40000000 -#define IOC_IOCFG24_HYST_EN_BITN 30 -#define IOC_IOCFG24_HYST_EN_M 0x40000000 -#define IOC_IOCFG24_HYST_EN_S 30 +#define IOC_IOCFG24_HYST_EN 0x40000000 +#define IOC_IOCFG24_HYST_EN_BITN 30 +#define IOC_IOCFG24_HYST_EN_M 0x40000000 +#define IOC_IOCFG24_HYST_EN_S 30 // Field: [29] IE // @@ -7432,10 +7432,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG24_IE 0x20000000 -#define IOC_IOCFG24_IE_BITN 29 -#define IOC_IOCFG24_IE_M 0x20000000 -#define IOC_IOCFG24_IE_S 29 +#define IOC_IOCFG24_IE 0x20000000 +#define IOC_IOCFG24_IE_BITN 29 +#define IOC_IOCFG24_IE_M 0x20000000 +#define IOC_IOCFG24_IE_S 29 // Field: [28:27] WU_CFG // @@ -7457,9 +7457,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG24_WU_CFG_W 2 -#define IOC_IOCFG24_WU_CFG_M 0x18000000 -#define IOC_IOCFG24_WU_CFG_S 27 +#define IOC_IOCFG24_WU_CFG_W 2 +#define IOC_IOCFG24_WU_CFG_M 0x18000000 +#define IOC_IOCFG24_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -7480,25 +7480,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG24_IOMODE_W 3 -#define IOC_IOCFG24_IOMODE_M 0x07000000 -#define IOC_IOCFG24_IOMODE_S 24 -#define IOC_IOCFG24_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG24_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG24_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG24_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG24_IOMODE_INV 0x01000000 -#define IOC_IOCFG24_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG24_IOMODE_W 3 +#define IOC_IOCFG24_IOMODE_M 0x07000000 +#define IOC_IOCFG24_IOMODE_S 24 +#define IOC_IOCFG24_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG24_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG24_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG24_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG24_IOMODE_INV 0x01000000 +#define IOC_IOCFG24_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG24_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG24_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG24_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG24_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG24_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG24_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG24_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG24_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -7508,13 +7508,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG24_EDGE_DET_W 2 -#define IOC_IOCFG24_EDGE_DET_M 0x00030000 -#define IOC_IOCFG24_EDGE_DET_S 16 -#define IOC_IOCFG24_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG24_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG24_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG24_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG24_EDGE_DET_W 2 +#define IOC_IOCFG24_EDGE_DET_M 0x00030000 +#define IOC_IOCFG24_EDGE_DET_S 16 +#define IOC_IOCFG24_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG24_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG24_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG24_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -7523,21 +7523,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG24_PULL_CTL_W 2 -#define IOC_IOCFG24_PULL_CTL_M 0x00006000 -#define IOC_IOCFG24_PULL_CTL_S 13 -#define IOC_IOCFG24_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG24_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG24_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG24_PULL_CTL_W 2 +#define IOC_IOCFG24_PULL_CTL_M 0x00006000 +#define IOC_IOCFG24_PULL_CTL_S 13 +#define IOC_IOCFG24_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG24_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG24_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG24_SLEW_RED 0x00001000 -#define IOC_IOCFG24_SLEW_RED_BITN 12 -#define IOC_IOCFG24_SLEW_RED_M 0x00001000 -#define IOC_IOCFG24_SLEW_RED_S 12 +#define IOC_IOCFG24_SLEW_RED 0x00001000 +#define IOC_IOCFG24_SLEW_RED_BITN 12 +#define IOC_IOCFG24_SLEW_RED_M 0x00001000 +#define IOC_IOCFG24_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -7550,12 +7550,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG24_IOCURR_W 2 -#define IOC_IOCFG24_IOCURR_M 0x00000C00 -#define IOC_IOCFG24_IOCURR_S 10 -#define IOC_IOCFG24_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG24_IOCURR_4MA 0x00000400 -#define IOC_IOCFG24_IOCURR_2MA 0x00000000 +#define IOC_IOCFG24_IOCURR_W 2 +#define IOC_IOCFG24_IOCURR_M 0x00000C00 +#define IOC_IOCFG24_IOCURR_S 10 +#define IOC_IOCFG24_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG24_IOCURR_4MA 0x00000400 +#define IOC_IOCFG24_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -7574,13 +7574,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG24_IOSTR_W 2 -#define IOC_IOCFG24_IOSTR_M 0x00000300 -#define IOC_IOCFG24_IOSTR_S 8 -#define IOC_IOCFG24_IOSTR_MAX 0x00000300 -#define IOC_IOCFG24_IOSTR_MED 0x00000200 -#define IOC_IOCFG24_IOSTR_MIN 0x00000100 -#define IOC_IOCFG24_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG24_IOSTR_W 2 +#define IOC_IOCFG24_IOSTR_M 0x00000300 +#define IOC_IOCFG24_IOSTR_S 8 +#define IOC_IOCFG24_IOSTR_MAX 0x00000300 +#define IOC_IOCFG24_IOSTR_MED 0x00000200 +#define IOC_IOCFG24_IOSTR_MIN 0x00000100 +#define IOC_IOCFG24_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -7668,51 +7668,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG24_PORT_ID_W 6 -#define IOC_IOCFG24_PORT_ID_M 0x0000003F -#define IOC_IOCFG24_PORT_ID_S 0 -#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG24_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG24_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG24_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG24_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG24_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG24_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG24_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG24_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG24_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG24_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG24_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG24_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG24_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG24_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG24_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG24_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG24_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG24_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG24_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG24_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG24_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG24_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG24_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG24_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG24_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG24_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG24_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG24_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG24_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG24_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG24_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG24_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG24_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG24_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG24_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG24_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG24_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG24_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG24_PORT_ID_W 6 +#define IOC_IOCFG24_PORT_ID_M 0x0000003F +#define IOC_IOCFG24_PORT_ID_S 0 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG24_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG24_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG24_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG24_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG24_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG24_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG24_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG24_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG24_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG24_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG24_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG24_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG24_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG24_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG24_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG24_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG24_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG24_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG24_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG24_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG24_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG24_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG24_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG24_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG24_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG24_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG24_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG24_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG24_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG24_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG24_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG24_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG24_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG24_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG24_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG24_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -7723,10 +7723,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG25_HYST_EN 0x40000000 -#define IOC_IOCFG25_HYST_EN_BITN 30 -#define IOC_IOCFG25_HYST_EN_M 0x40000000 -#define IOC_IOCFG25_HYST_EN_S 30 +#define IOC_IOCFG25_HYST_EN 0x40000000 +#define IOC_IOCFG25_HYST_EN_BITN 30 +#define IOC_IOCFG25_HYST_EN_M 0x40000000 +#define IOC_IOCFG25_HYST_EN_S 30 // Field: [29] IE // @@ -7735,10 +7735,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG25_IE 0x20000000 -#define IOC_IOCFG25_IE_BITN 29 -#define IOC_IOCFG25_IE_M 0x20000000 -#define IOC_IOCFG25_IE_S 29 +#define IOC_IOCFG25_IE 0x20000000 +#define IOC_IOCFG25_IE_BITN 29 +#define IOC_IOCFG25_IE_M 0x20000000 +#define IOC_IOCFG25_IE_S 29 // Field: [28:27] WU_CFG // @@ -7760,9 +7760,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG25_WU_CFG_W 2 -#define IOC_IOCFG25_WU_CFG_M 0x18000000 -#define IOC_IOCFG25_WU_CFG_S 27 +#define IOC_IOCFG25_WU_CFG_W 2 +#define IOC_IOCFG25_WU_CFG_M 0x18000000 +#define IOC_IOCFG25_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -7783,25 +7783,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG25_IOMODE_W 3 -#define IOC_IOCFG25_IOMODE_M 0x07000000 -#define IOC_IOCFG25_IOMODE_S 24 -#define IOC_IOCFG25_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG25_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG25_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG25_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG25_IOMODE_INV 0x01000000 -#define IOC_IOCFG25_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG25_IOMODE_W 3 +#define IOC_IOCFG25_IOMODE_M 0x07000000 +#define IOC_IOCFG25_IOMODE_S 24 +#define IOC_IOCFG25_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG25_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG25_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG25_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG25_IOMODE_INV 0x01000000 +#define IOC_IOCFG25_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG25_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG25_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG25_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG25_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG25_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG25_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG25_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG25_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -7811,13 +7811,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG25_EDGE_DET_W 2 -#define IOC_IOCFG25_EDGE_DET_M 0x00030000 -#define IOC_IOCFG25_EDGE_DET_S 16 -#define IOC_IOCFG25_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG25_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG25_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG25_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG25_EDGE_DET_W 2 +#define IOC_IOCFG25_EDGE_DET_M 0x00030000 +#define IOC_IOCFG25_EDGE_DET_S 16 +#define IOC_IOCFG25_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG25_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG25_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG25_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -7826,21 +7826,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG25_PULL_CTL_W 2 -#define IOC_IOCFG25_PULL_CTL_M 0x00006000 -#define IOC_IOCFG25_PULL_CTL_S 13 -#define IOC_IOCFG25_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG25_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG25_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG25_PULL_CTL_W 2 +#define IOC_IOCFG25_PULL_CTL_M 0x00006000 +#define IOC_IOCFG25_PULL_CTL_S 13 +#define IOC_IOCFG25_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG25_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG25_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG25_SLEW_RED 0x00001000 -#define IOC_IOCFG25_SLEW_RED_BITN 12 -#define IOC_IOCFG25_SLEW_RED_M 0x00001000 -#define IOC_IOCFG25_SLEW_RED_S 12 +#define IOC_IOCFG25_SLEW_RED 0x00001000 +#define IOC_IOCFG25_SLEW_RED_BITN 12 +#define IOC_IOCFG25_SLEW_RED_M 0x00001000 +#define IOC_IOCFG25_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -7853,12 +7853,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG25_IOCURR_W 2 -#define IOC_IOCFG25_IOCURR_M 0x00000C00 -#define IOC_IOCFG25_IOCURR_S 10 -#define IOC_IOCFG25_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG25_IOCURR_4MA 0x00000400 -#define IOC_IOCFG25_IOCURR_2MA 0x00000000 +#define IOC_IOCFG25_IOCURR_W 2 +#define IOC_IOCFG25_IOCURR_M 0x00000C00 +#define IOC_IOCFG25_IOCURR_S 10 +#define IOC_IOCFG25_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG25_IOCURR_4MA 0x00000400 +#define IOC_IOCFG25_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -7877,13 +7877,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG25_IOSTR_W 2 -#define IOC_IOCFG25_IOSTR_M 0x00000300 -#define IOC_IOCFG25_IOSTR_S 8 -#define IOC_IOCFG25_IOSTR_MAX 0x00000300 -#define IOC_IOCFG25_IOSTR_MED 0x00000200 -#define IOC_IOCFG25_IOSTR_MIN 0x00000100 -#define IOC_IOCFG25_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG25_IOSTR_W 2 +#define IOC_IOCFG25_IOSTR_M 0x00000300 +#define IOC_IOCFG25_IOSTR_S 8 +#define IOC_IOCFG25_IOSTR_MAX 0x00000300 +#define IOC_IOCFG25_IOSTR_MED 0x00000200 +#define IOC_IOCFG25_IOSTR_MIN 0x00000100 +#define IOC_IOCFG25_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -7971,51 +7971,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG25_PORT_ID_W 6 -#define IOC_IOCFG25_PORT_ID_M 0x0000003F -#define IOC_IOCFG25_PORT_ID_S 0 -#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG25_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG25_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG25_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG25_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG25_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG25_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG25_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG25_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG25_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG25_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG25_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG25_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG25_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG25_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG25_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG25_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG25_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG25_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG25_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG25_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG25_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG25_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG25_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG25_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG25_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG25_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG25_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG25_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG25_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG25_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG25_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG25_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG25_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG25_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG25_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG25_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG25_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG25_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG25_PORT_ID_W 6 +#define IOC_IOCFG25_PORT_ID_M 0x0000003F +#define IOC_IOCFG25_PORT_ID_S 0 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG25_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG25_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG25_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG25_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG25_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG25_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG25_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG25_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG25_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG25_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG25_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG25_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG25_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG25_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG25_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG25_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG25_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG25_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG25_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG25_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG25_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG25_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG25_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG25_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG25_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG25_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG25_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG25_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG25_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG25_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG25_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG25_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG25_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG25_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG25_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG25_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -8026,10 +8026,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG26_HYST_EN 0x40000000 -#define IOC_IOCFG26_HYST_EN_BITN 30 -#define IOC_IOCFG26_HYST_EN_M 0x40000000 -#define IOC_IOCFG26_HYST_EN_S 30 +#define IOC_IOCFG26_HYST_EN 0x40000000 +#define IOC_IOCFG26_HYST_EN_BITN 30 +#define IOC_IOCFG26_HYST_EN_M 0x40000000 +#define IOC_IOCFG26_HYST_EN_S 30 // Field: [29] IE // @@ -8038,10 +8038,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG26_IE 0x20000000 -#define IOC_IOCFG26_IE_BITN 29 -#define IOC_IOCFG26_IE_M 0x20000000 -#define IOC_IOCFG26_IE_S 29 +#define IOC_IOCFG26_IE 0x20000000 +#define IOC_IOCFG26_IE_BITN 29 +#define IOC_IOCFG26_IE_M 0x20000000 +#define IOC_IOCFG26_IE_S 29 // Field: [28:27] WU_CFG // @@ -8063,9 +8063,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG26_WU_CFG_W 2 -#define IOC_IOCFG26_WU_CFG_M 0x18000000 -#define IOC_IOCFG26_WU_CFG_S 27 +#define IOC_IOCFG26_WU_CFG_W 2 +#define IOC_IOCFG26_WU_CFG_M 0x18000000 +#define IOC_IOCFG26_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -8086,25 +8086,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG26_IOMODE_W 3 -#define IOC_IOCFG26_IOMODE_M 0x07000000 -#define IOC_IOCFG26_IOMODE_S 24 -#define IOC_IOCFG26_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG26_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG26_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG26_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG26_IOMODE_INV 0x01000000 -#define IOC_IOCFG26_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG26_IOMODE_W 3 +#define IOC_IOCFG26_IOMODE_M 0x07000000 +#define IOC_IOCFG26_IOMODE_S 24 +#define IOC_IOCFG26_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG26_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG26_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG26_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG26_IOMODE_INV 0x01000000 +#define IOC_IOCFG26_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG26_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG26_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG26_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG26_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG26_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG26_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG26_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG26_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -8114,13 +8114,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG26_EDGE_DET_W 2 -#define IOC_IOCFG26_EDGE_DET_M 0x00030000 -#define IOC_IOCFG26_EDGE_DET_S 16 -#define IOC_IOCFG26_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG26_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG26_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG26_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG26_EDGE_DET_W 2 +#define IOC_IOCFG26_EDGE_DET_M 0x00030000 +#define IOC_IOCFG26_EDGE_DET_S 16 +#define IOC_IOCFG26_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG26_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG26_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG26_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -8129,21 +8129,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG26_PULL_CTL_W 2 -#define IOC_IOCFG26_PULL_CTL_M 0x00006000 -#define IOC_IOCFG26_PULL_CTL_S 13 -#define IOC_IOCFG26_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG26_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG26_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG26_PULL_CTL_W 2 +#define IOC_IOCFG26_PULL_CTL_M 0x00006000 +#define IOC_IOCFG26_PULL_CTL_S 13 +#define IOC_IOCFG26_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG26_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG26_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG26_SLEW_RED 0x00001000 -#define IOC_IOCFG26_SLEW_RED_BITN 12 -#define IOC_IOCFG26_SLEW_RED_M 0x00001000 -#define IOC_IOCFG26_SLEW_RED_S 12 +#define IOC_IOCFG26_SLEW_RED 0x00001000 +#define IOC_IOCFG26_SLEW_RED_BITN 12 +#define IOC_IOCFG26_SLEW_RED_M 0x00001000 +#define IOC_IOCFG26_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -8156,12 +8156,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG26_IOCURR_W 2 -#define IOC_IOCFG26_IOCURR_M 0x00000C00 -#define IOC_IOCFG26_IOCURR_S 10 -#define IOC_IOCFG26_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG26_IOCURR_4MA 0x00000400 -#define IOC_IOCFG26_IOCURR_2MA 0x00000000 +#define IOC_IOCFG26_IOCURR_W 2 +#define IOC_IOCFG26_IOCURR_M 0x00000C00 +#define IOC_IOCFG26_IOCURR_S 10 +#define IOC_IOCFG26_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG26_IOCURR_4MA 0x00000400 +#define IOC_IOCFG26_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -8180,13 +8180,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG26_IOSTR_W 2 -#define IOC_IOCFG26_IOSTR_M 0x00000300 -#define IOC_IOCFG26_IOSTR_S 8 -#define IOC_IOCFG26_IOSTR_MAX 0x00000300 -#define IOC_IOCFG26_IOSTR_MED 0x00000200 -#define IOC_IOCFG26_IOSTR_MIN 0x00000100 -#define IOC_IOCFG26_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG26_IOSTR_W 2 +#define IOC_IOCFG26_IOSTR_M 0x00000300 +#define IOC_IOCFG26_IOSTR_S 8 +#define IOC_IOCFG26_IOSTR_MAX 0x00000300 +#define IOC_IOCFG26_IOSTR_MED 0x00000200 +#define IOC_IOCFG26_IOSTR_MIN 0x00000100 +#define IOC_IOCFG26_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -8274,51 +8274,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG26_PORT_ID_W 6 -#define IOC_IOCFG26_PORT_ID_M 0x0000003F -#define IOC_IOCFG26_PORT_ID_S 0 -#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG26_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG26_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG26_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG26_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG26_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG26_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG26_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG26_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG26_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG26_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG26_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG26_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG26_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG26_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG26_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG26_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG26_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG26_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG26_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG26_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG26_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG26_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG26_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG26_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG26_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG26_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG26_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG26_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG26_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG26_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG26_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG26_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG26_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG26_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG26_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG26_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG26_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG26_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG26_PORT_ID_W 6 +#define IOC_IOCFG26_PORT_ID_M 0x0000003F +#define IOC_IOCFG26_PORT_ID_S 0 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG26_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG26_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG26_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG26_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG26_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG26_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG26_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG26_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG26_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG26_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG26_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG26_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG26_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG26_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG26_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG26_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG26_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG26_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG26_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG26_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG26_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG26_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG26_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG26_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG26_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG26_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG26_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG26_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG26_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG26_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG26_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG26_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG26_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG26_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG26_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG26_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -8329,10 +8329,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG27_HYST_EN 0x40000000 -#define IOC_IOCFG27_HYST_EN_BITN 30 -#define IOC_IOCFG27_HYST_EN_M 0x40000000 -#define IOC_IOCFG27_HYST_EN_S 30 +#define IOC_IOCFG27_HYST_EN 0x40000000 +#define IOC_IOCFG27_HYST_EN_BITN 30 +#define IOC_IOCFG27_HYST_EN_M 0x40000000 +#define IOC_IOCFG27_HYST_EN_S 30 // Field: [29] IE // @@ -8341,10 +8341,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG27_IE 0x20000000 -#define IOC_IOCFG27_IE_BITN 29 -#define IOC_IOCFG27_IE_M 0x20000000 -#define IOC_IOCFG27_IE_S 29 +#define IOC_IOCFG27_IE 0x20000000 +#define IOC_IOCFG27_IE_BITN 29 +#define IOC_IOCFG27_IE_M 0x20000000 +#define IOC_IOCFG27_IE_S 29 // Field: [28:27] WU_CFG // @@ -8366,9 +8366,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG27_WU_CFG_W 2 -#define IOC_IOCFG27_WU_CFG_M 0x18000000 -#define IOC_IOCFG27_WU_CFG_S 27 +#define IOC_IOCFG27_WU_CFG_W 2 +#define IOC_IOCFG27_WU_CFG_M 0x18000000 +#define IOC_IOCFG27_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -8389,25 +8389,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG27_IOMODE_W 3 -#define IOC_IOCFG27_IOMODE_M 0x07000000 -#define IOC_IOCFG27_IOMODE_S 24 -#define IOC_IOCFG27_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG27_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG27_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG27_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG27_IOMODE_INV 0x01000000 -#define IOC_IOCFG27_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG27_IOMODE_W 3 +#define IOC_IOCFG27_IOMODE_M 0x07000000 +#define IOC_IOCFG27_IOMODE_S 24 +#define IOC_IOCFG27_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG27_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG27_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG27_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG27_IOMODE_INV 0x01000000 +#define IOC_IOCFG27_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG27_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG27_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG27_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG27_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG27_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG27_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG27_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG27_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -8417,13 +8417,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG27_EDGE_DET_W 2 -#define IOC_IOCFG27_EDGE_DET_M 0x00030000 -#define IOC_IOCFG27_EDGE_DET_S 16 -#define IOC_IOCFG27_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG27_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG27_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG27_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG27_EDGE_DET_W 2 +#define IOC_IOCFG27_EDGE_DET_M 0x00030000 +#define IOC_IOCFG27_EDGE_DET_S 16 +#define IOC_IOCFG27_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG27_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG27_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG27_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -8432,21 +8432,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG27_PULL_CTL_W 2 -#define IOC_IOCFG27_PULL_CTL_M 0x00006000 -#define IOC_IOCFG27_PULL_CTL_S 13 -#define IOC_IOCFG27_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG27_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG27_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG27_PULL_CTL_W 2 +#define IOC_IOCFG27_PULL_CTL_M 0x00006000 +#define IOC_IOCFG27_PULL_CTL_S 13 +#define IOC_IOCFG27_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG27_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG27_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG27_SLEW_RED 0x00001000 -#define IOC_IOCFG27_SLEW_RED_BITN 12 -#define IOC_IOCFG27_SLEW_RED_M 0x00001000 -#define IOC_IOCFG27_SLEW_RED_S 12 +#define IOC_IOCFG27_SLEW_RED 0x00001000 +#define IOC_IOCFG27_SLEW_RED_BITN 12 +#define IOC_IOCFG27_SLEW_RED_M 0x00001000 +#define IOC_IOCFG27_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -8459,12 +8459,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG27_IOCURR_W 2 -#define IOC_IOCFG27_IOCURR_M 0x00000C00 -#define IOC_IOCFG27_IOCURR_S 10 -#define IOC_IOCFG27_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG27_IOCURR_4MA 0x00000400 -#define IOC_IOCFG27_IOCURR_2MA 0x00000000 +#define IOC_IOCFG27_IOCURR_W 2 +#define IOC_IOCFG27_IOCURR_M 0x00000C00 +#define IOC_IOCFG27_IOCURR_S 10 +#define IOC_IOCFG27_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG27_IOCURR_4MA 0x00000400 +#define IOC_IOCFG27_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -8483,13 +8483,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG27_IOSTR_W 2 -#define IOC_IOCFG27_IOSTR_M 0x00000300 -#define IOC_IOCFG27_IOSTR_S 8 -#define IOC_IOCFG27_IOSTR_MAX 0x00000300 -#define IOC_IOCFG27_IOSTR_MED 0x00000200 -#define IOC_IOCFG27_IOSTR_MIN 0x00000100 -#define IOC_IOCFG27_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG27_IOSTR_W 2 +#define IOC_IOCFG27_IOSTR_M 0x00000300 +#define IOC_IOCFG27_IOSTR_S 8 +#define IOC_IOCFG27_IOSTR_MAX 0x00000300 +#define IOC_IOCFG27_IOSTR_MED 0x00000200 +#define IOC_IOCFG27_IOSTR_MIN 0x00000100 +#define IOC_IOCFG27_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -8577,51 +8577,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG27_PORT_ID_W 6 -#define IOC_IOCFG27_PORT_ID_M 0x0000003F -#define IOC_IOCFG27_PORT_ID_S 0 -#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG27_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG27_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG27_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG27_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG27_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG27_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG27_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG27_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG27_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG27_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG27_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG27_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG27_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG27_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG27_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG27_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG27_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG27_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG27_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG27_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG27_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG27_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG27_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG27_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG27_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG27_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG27_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG27_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG27_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG27_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG27_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG27_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG27_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG27_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG27_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG27_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG27_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG27_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG27_PORT_ID_W 6 +#define IOC_IOCFG27_PORT_ID_M 0x0000003F +#define IOC_IOCFG27_PORT_ID_S 0 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG27_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG27_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG27_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG27_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG27_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG27_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG27_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG27_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG27_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG27_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG27_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG27_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG27_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG27_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG27_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG27_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG27_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG27_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG27_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG27_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG27_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG27_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG27_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG27_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG27_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG27_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG27_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG27_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG27_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG27_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG27_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG27_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG27_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG27_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG27_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG27_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -8632,10 +8632,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG28_HYST_EN 0x40000000 -#define IOC_IOCFG28_HYST_EN_BITN 30 -#define IOC_IOCFG28_HYST_EN_M 0x40000000 -#define IOC_IOCFG28_HYST_EN_S 30 +#define IOC_IOCFG28_HYST_EN 0x40000000 +#define IOC_IOCFG28_HYST_EN_BITN 30 +#define IOC_IOCFG28_HYST_EN_M 0x40000000 +#define IOC_IOCFG28_HYST_EN_S 30 // Field: [29] IE // @@ -8644,10 +8644,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG28_IE 0x20000000 -#define IOC_IOCFG28_IE_BITN 29 -#define IOC_IOCFG28_IE_M 0x20000000 -#define IOC_IOCFG28_IE_S 29 +#define IOC_IOCFG28_IE 0x20000000 +#define IOC_IOCFG28_IE_BITN 29 +#define IOC_IOCFG28_IE_M 0x20000000 +#define IOC_IOCFG28_IE_S 29 // Field: [28:27] WU_CFG // @@ -8669,9 +8669,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG28_WU_CFG_W 2 -#define IOC_IOCFG28_WU_CFG_M 0x18000000 -#define IOC_IOCFG28_WU_CFG_S 27 +#define IOC_IOCFG28_WU_CFG_W 2 +#define IOC_IOCFG28_WU_CFG_M 0x18000000 +#define IOC_IOCFG28_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -8692,25 +8692,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG28_IOMODE_W 3 -#define IOC_IOCFG28_IOMODE_M 0x07000000 -#define IOC_IOCFG28_IOMODE_S 24 -#define IOC_IOCFG28_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG28_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG28_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG28_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG28_IOMODE_INV 0x01000000 -#define IOC_IOCFG28_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG28_IOMODE_W 3 +#define IOC_IOCFG28_IOMODE_M 0x07000000 +#define IOC_IOCFG28_IOMODE_S 24 +#define IOC_IOCFG28_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG28_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG28_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG28_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG28_IOMODE_INV 0x01000000 +#define IOC_IOCFG28_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG28_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG28_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG28_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG28_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG28_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG28_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG28_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG28_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -8720,13 +8720,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG28_EDGE_DET_W 2 -#define IOC_IOCFG28_EDGE_DET_M 0x00030000 -#define IOC_IOCFG28_EDGE_DET_S 16 -#define IOC_IOCFG28_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG28_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG28_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG28_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG28_EDGE_DET_W 2 +#define IOC_IOCFG28_EDGE_DET_M 0x00030000 +#define IOC_IOCFG28_EDGE_DET_S 16 +#define IOC_IOCFG28_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG28_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG28_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG28_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -8735,21 +8735,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG28_PULL_CTL_W 2 -#define IOC_IOCFG28_PULL_CTL_M 0x00006000 -#define IOC_IOCFG28_PULL_CTL_S 13 -#define IOC_IOCFG28_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG28_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG28_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG28_PULL_CTL_W 2 +#define IOC_IOCFG28_PULL_CTL_M 0x00006000 +#define IOC_IOCFG28_PULL_CTL_S 13 +#define IOC_IOCFG28_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG28_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG28_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG28_SLEW_RED 0x00001000 -#define IOC_IOCFG28_SLEW_RED_BITN 12 -#define IOC_IOCFG28_SLEW_RED_M 0x00001000 -#define IOC_IOCFG28_SLEW_RED_S 12 +#define IOC_IOCFG28_SLEW_RED 0x00001000 +#define IOC_IOCFG28_SLEW_RED_BITN 12 +#define IOC_IOCFG28_SLEW_RED_M 0x00001000 +#define IOC_IOCFG28_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -8762,12 +8762,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG28_IOCURR_W 2 -#define IOC_IOCFG28_IOCURR_M 0x00000C00 -#define IOC_IOCFG28_IOCURR_S 10 -#define IOC_IOCFG28_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG28_IOCURR_4MA 0x00000400 -#define IOC_IOCFG28_IOCURR_2MA 0x00000000 +#define IOC_IOCFG28_IOCURR_W 2 +#define IOC_IOCFG28_IOCURR_M 0x00000C00 +#define IOC_IOCFG28_IOCURR_S 10 +#define IOC_IOCFG28_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG28_IOCURR_4MA 0x00000400 +#define IOC_IOCFG28_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -8786,13 +8786,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG28_IOSTR_W 2 -#define IOC_IOCFG28_IOSTR_M 0x00000300 -#define IOC_IOCFG28_IOSTR_S 8 -#define IOC_IOCFG28_IOSTR_MAX 0x00000300 -#define IOC_IOCFG28_IOSTR_MED 0x00000200 -#define IOC_IOCFG28_IOSTR_MIN 0x00000100 -#define IOC_IOCFG28_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG28_IOSTR_W 2 +#define IOC_IOCFG28_IOSTR_M 0x00000300 +#define IOC_IOCFG28_IOSTR_S 8 +#define IOC_IOCFG28_IOSTR_MAX 0x00000300 +#define IOC_IOCFG28_IOSTR_MED 0x00000200 +#define IOC_IOCFG28_IOSTR_MIN 0x00000100 +#define IOC_IOCFG28_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -8880,51 +8880,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG28_PORT_ID_W 6 -#define IOC_IOCFG28_PORT_ID_M 0x0000003F -#define IOC_IOCFG28_PORT_ID_S 0 -#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG28_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG28_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG28_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG28_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG28_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG28_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG28_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG28_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG28_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG28_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG28_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG28_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG28_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG28_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG28_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG28_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG28_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG28_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG28_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG28_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG28_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG28_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG28_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG28_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG28_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG28_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG28_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG28_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG28_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG28_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG28_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG28_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG28_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG28_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG28_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG28_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG28_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG28_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG28_PORT_ID_W 6 +#define IOC_IOCFG28_PORT_ID_M 0x0000003F +#define IOC_IOCFG28_PORT_ID_S 0 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG28_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG28_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG28_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG28_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG28_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG28_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG28_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG28_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG28_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG28_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG28_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG28_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG28_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG28_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG28_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG28_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG28_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG28_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG28_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG28_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG28_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG28_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG28_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG28_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG28_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG28_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG28_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG28_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG28_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG28_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG28_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG28_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG28_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG28_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG28_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG28_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -8935,10 +8935,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG29_HYST_EN 0x40000000 -#define IOC_IOCFG29_HYST_EN_BITN 30 -#define IOC_IOCFG29_HYST_EN_M 0x40000000 -#define IOC_IOCFG29_HYST_EN_S 30 +#define IOC_IOCFG29_HYST_EN 0x40000000 +#define IOC_IOCFG29_HYST_EN_BITN 30 +#define IOC_IOCFG29_HYST_EN_M 0x40000000 +#define IOC_IOCFG29_HYST_EN_S 30 // Field: [29] IE // @@ -8947,10 +8947,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG29_IE 0x20000000 -#define IOC_IOCFG29_IE_BITN 29 -#define IOC_IOCFG29_IE_M 0x20000000 -#define IOC_IOCFG29_IE_S 29 +#define IOC_IOCFG29_IE 0x20000000 +#define IOC_IOCFG29_IE_BITN 29 +#define IOC_IOCFG29_IE_M 0x20000000 +#define IOC_IOCFG29_IE_S 29 // Field: [28:27] WU_CFG // @@ -8972,9 +8972,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG29_WU_CFG_W 2 -#define IOC_IOCFG29_WU_CFG_M 0x18000000 -#define IOC_IOCFG29_WU_CFG_S 27 +#define IOC_IOCFG29_WU_CFG_W 2 +#define IOC_IOCFG29_WU_CFG_M 0x18000000 +#define IOC_IOCFG29_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -8995,25 +8995,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG29_IOMODE_W 3 -#define IOC_IOCFG29_IOMODE_M 0x07000000 -#define IOC_IOCFG29_IOMODE_S 24 -#define IOC_IOCFG29_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG29_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG29_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG29_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG29_IOMODE_INV 0x01000000 -#define IOC_IOCFG29_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG29_IOMODE_W 3 +#define IOC_IOCFG29_IOMODE_M 0x07000000 +#define IOC_IOCFG29_IOMODE_S 24 +#define IOC_IOCFG29_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG29_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG29_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG29_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG29_IOMODE_INV 0x01000000 +#define IOC_IOCFG29_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG29_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG29_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG29_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG29_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG29_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG29_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG29_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG29_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -9023,13 +9023,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG29_EDGE_DET_W 2 -#define IOC_IOCFG29_EDGE_DET_M 0x00030000 -#define IOC_IOCFG29_EDGE_DET_S 16 -#define IOC_IOCFG29_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG29_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG29_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG29_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG29_EDGE_DET_W 2 +#define IOC_IOCFG29_EDGE_DET_M 0x00030000 +#define IOC_IOCFG29_EDGE_DET_S 16 +#define IOC_IOCFG29_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG29_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG29_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG29_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -9038,21 +9038,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG29_PULL_CTL_W 2 -#define IOC_IOCFG29_PULL_CTL_M 0x00006000 -#define IOC_IOCFG29_PULL_CTL_S 13 -#define IOC_IOCFG29_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG29_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG29_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG29_PULL_CTL_W 2 +#define IOC_IOCFG29_PULL_CTL_M 0x00006000 +#define IOC_IOCFG29_PULL_CTL_S 13 +#define IOC_IOCFG29_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG29_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG29_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG29_SLEW_RED 0x00001000 -#define IOC_IOCFG29_SLEW_RED_BITN 12 -#define IOC_IOCFG29_SLEW_RED_M 0x00001000 -#define IOC_IOCFG29_SLEW_RED_S 12 +#define IOC_IOCFG29_SLEW_RED 0x00001000 +#define IOC_IOCFG29_SLEW_RED_BITN 12 +#define IOC_IOCFG29_SLEW_RED_M 0x00001000 +#define IOC_IOCFG29_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -9065,12 +9065,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG29_IOCURR_W 2 -#define IOC_IOCFG29_IOCURR_M 0x00000C00 -#define IOC_IOCFG29_IOCURR_S 10 -#define IOC_IOCFG29_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG29_IOCURR_4MA 0x00000400 -#define IOC_IOCFG29_IOCURR_2MA 0x00000000 +#define IOC_IOCFG29_IOCURR_W 2 +#define IOC_IOCFG29_IOCURR_M 0x00000C00 +#define IOC_IOCFG29_IOCURR_S 10 +#define IOC_IOCFG29_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG29_IOCURR_4MA 0x00000400 +#define IOC_IOCFG29_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -9089,13 +9089,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG29_IOSTR_W 2 -#define IOC_IOCFG29_IOSTR_M 0x00000300 -#define IOC_IOCFG29_IOSTR_S 8 -#define IOC_IOCFG29_IOSTR_MAX 0x00000300 -#define IOC_IOCFG29_IOSTR_MED 0x00000200 -#define IOC_IOCFG29_IOSTR_MIN 0x00000100 -#define IOC_IOCFG29_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG29_IOSTR_W 2 +#define IOC_IOCFG29_IOSTR_M 0x00000300 +#define IOC_IOCFG29_IOSTR_S 8 +#define IOC_IOCFG29_IOSTR_MAX 0x00000300 +#define IOC_IOCFG29_IOSTR_MED 0x00000200 +#define IOC_IOCFG29_IOSTR_MIN 0x00000100 +#define IOC_IOCFG29_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -9183,51 +9183,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG29_PORT_ID_W 6 -#define IOC_IOCFG29_PORT_ID_M 0x0000003F -#define IOC_IOCFG29_PORT_ID_S 0 -#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG29_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG29_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG29_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG29_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG29_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG29_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG29_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG29_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG29_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG29_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG29_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG29_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG29_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG29_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG29_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG29_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG29_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG29_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG29_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG29_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG29_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG29_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG29_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG29_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG29_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG29_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG29_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG29_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG29_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG29_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG29_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG29_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG29_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG29_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG29_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG29_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG29_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG29_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG29_PORT_ID_W 6 +#define IOC_IOCFG29_PORT_ID_M 0x0000003F +#define IOC_IOCFG29_PORT_ID_S 0 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG29_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG29_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG29_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG29_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG29_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG29_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG29_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG29_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG29_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG29_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG29_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG29_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG29_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG29_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG29_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG29_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG29_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG29_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG29_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG29_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG29_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG29_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG29_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG29_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG29_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG29_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG29_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG29_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG29_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG29_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG29_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG29_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG29_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG29_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG29_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG29_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -9238,10 +9238,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG30_HYST_EN 0x40000000 -#define IOC_IOCFG30_HYST_EN_BITN 30 -#define IOC_IOCFG30_HYST_EN_M 0x40000000 -#define IOC_IOCFG30_HYST_EN_S 30 +#define IOC_IOCFG30_HYST_EN 0x40000000 +#define IOC_IOCFG30_HYST_EN_BITN 30 +#define IOC_IOCFG30_HYST_EN_M 0x40000000 +#define IOC_IOCFG30_HYST_EN_S 30 // Field: [29] IE // @@ -9250,10 +9250,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG30_IE 0x20000000 -#define IOC_IOCFG30_IE_BITN 29 -#define IOC_IOCFG30_IE_M 0x20000000 -#define IOC_IOCFG30_IE_S 29 +#define IOC_IOCFG30_IE 0x20000000 +#define IOC_IOCFG30_IE_BITN 29 +#define IOC_IOCFG30_IE_M 0x20000000 +#define IOC_IOCFG30_IE_S 29 // Field: [28:27] WU_CFG // @@ -9275,9 +9275,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG30_WU_CFG_W 2 -#define IOC_IOCFG30_WU_CFG_M 0x18000000 -#define IOC_IOCFG30_WU_CFG_S 27 +#define IOC_IOCFG30_WU_CFG_W 2 +#define IOC_IOCFG30_WU_CFG_M 0x18000000 +#define IOC_IOCFG30_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -9298,25 +9298,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG30_IOMODE_W 3 -#define IOC_IOCFG30_IOMODE_M 0x07000000 -#define IOC_IOCFG30_IOMODE_S 24 -#define IOC_IOCFG30_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG30_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG30_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG30_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG30_IOMODE_INV 0x01000000 -#define IOC_IOCFG30_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG30_IOMODE_W 3 +#define IOC_IOCFG30_IOMODE_M 0x07000000 +#define IOC_IOCFG30_IOMODE_S 24 +#define IOC_IOCFG30_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG30_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG30_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG30_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG30_IOMODE_INV 0x01000000 +#define IOC_IOCFG30_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG30_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG30_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG30_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG30_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG30_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG30_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG30_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG30_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -9326,13 +9326,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG30_EDGE_DET_W 2 -#define IOC_IOCFG30_EDGE_DET_M 0x00030000 -#define IOC_IOCFG30_EDGE_DET_S 16 -#define IOC_IOCFG30_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG30_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG30_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG30_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG30_EDGE_DET_W 2 +#define IOC_IOCFG30_EDGE_DET_M 0x00030000 +#define IOC_IOCFG30_EDGE_DET_S 16 +#define IOC_IOCFG30_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG30_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG30_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG30_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -9341,21 +9341,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG30_PULL_CTL_W 2 -#define IOC_IOCFG30_PULL_CTL_M 0x00006000 -#define IOC_IOCFG30_PULL_CTL_S 13 -#define IOC_IOCFG30_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG30_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG30_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG30_PULL_CTL_W 2 +#define IOC_IOCFG30_PULL_CTL_M 0x00006000 +#define IOC_IOCFG30_PULL_CTL_S 13 +#define IOC_IOCFG30_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG30_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG30_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG30_SLEW_RED 0x00001000 -#define IOC_IOCFG30_SLEW_RED_BITN 12 -#define IOC_IOCFG30_SLEW_RED_M 0x00001000 -#define IOC_IOCFG30_SLEW_RED_S 12 +#define IOC_IOCFG30_SLEW_RED 0x00001000 +#define IOC_IOCFG30_SLEW_RED_BITN 12 +#define IOC_IOCFG30_SLEW_RED_M 0x00001000 +#define IOC_IOCFG30_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -9368,12 +9368,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG30_IOCURR_W 2 -#define IOC_IOCFG30_IOCURR_M 0x00000C00 -#define IOC_IOCFG30_IOCURR_S 10 -#define IOC_IOCFG30_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG30_IOCURR_4MA 0x00000400 -#define IOC_IOCFG30_IOCURR_2MA 0x00000000 +#define IOC_IOCFG30_IOCURR_W 2 +#define IOC_IOCFG30_IOCURR_M 0x00000C00 +#define IOC_IOCFG30_IOCURR_S 10 +#define IOC_IOCFG30_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG30_IOCURR_4MA 0x00000400 +#define IOC_IOCFG30_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -9392,13 +9392,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG30_IOSTR_W 2 -#define IOC_IOCFG30_IOSTR_M 0x00000300 -#define IOC_IOCFG30_IOSTR_S 8 -#define IOC_IOCFG30_IOSTR_MAX 0x00000300 -#define IOC_IOCFG30_IOSTR_MED 0x00000200 -#define IOC_IOCFG30_IOSTR_MIN 0x00000100 -#define IOC_IOCFG30_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG30_IOSTR_W 2 +#define IOC_IOCFG30_IOSTR_M 0x00000300 +#define IOC_IOCFG30_IOSTR_S 8 +#define IOC_IOCFG30_IOSTR_MAX 0x00000300 +#define IOC_IOCFG30_IOSTR_MED 0x00000200 +#define IOC_IOCFG30_IOSTR_MIN 0x00000100 +#define IOC_IOCFG30_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -9486,51 +9486,51 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG30_PORT_ID_W 6 -#define IOC_IOCFG30_PORT_ID_M 0x0000003F -#define IOC_IOCFG30_PORT_ID_S 0 -#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG30_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG30_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG30_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG30_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG30_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG30_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG30_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG30_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG30_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG30_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG30_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG30_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG30_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG30_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG30_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG30_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG30_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG30_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG30_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG30_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG30_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG30_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG30_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG30_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG30_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG30_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG30_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG30_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG30_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG30_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG30_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG30_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG30_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG30_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG30_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG30_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG30_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG30_PORT_ID_GPIO 0x00000000 +#define IOC_IOCFG30_PORT_ID_W 6 +#define IOC_IOCFG30_PORT_ID_M 0x0000003F +#define IOC_IOCFG30_PORT_ID_S 0 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG30_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG30_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG30_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG30_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG30_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG30_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG30_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG30_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG30_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG30_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG30_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG30_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG30_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG30_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG30_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG30_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG30_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG30_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG30_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG30_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG30_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG30_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG30_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG30_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG30_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG30_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG30_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG30_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG30_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG30_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG30_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG30_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG30_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG30_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG30_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG30_PORT_ID_GPIO 0x00000000 //***************************************************************************** // @@ -9541,10 +9541,10 @@ // // 0: Input hysteresis disable // 1: Input hysteresis enable -#define IOC_IOCFG31_HYST_EN 0x40000000 -#define IOC_IOCFG31_HYST_EN_BITN 30 -#define IOC_IOCFG31_HYST_EN_M 0x40000000 -#define IOC_IOCFG31_HYST_EN_S 30 +#define IOC_IOCFG31_HYST_EN 0x40000000 +#define IOC_IOCFG31_HYST_EN_BITN 30 +#define IOC_IOCFG31_HYST_EN_M 0x40000000 +#define IOC_IOCFG31_HYST_EN_S 30 // Field: [29] IE // @@ -9553,10 +9553,10 @@ // // Note: If IO is configured for AUX ie. PORT_ID = 0x08, the enable will be // ignored. -#define IOC_IOCFG31_IE 0x20000000 -#define IOC_IOCFG31_IE_BITN 29 -#define IOC_IOCFG31_IE_M 0x20000000 -#define IOC_IOCFG31_IE_S 29 +#define IOC_IOCFG31_IE 0x20000000 +#define IOC_IOCFG31_IE_BITN 29 +#define IOC_IOCFG31_IE_M 0x20000000 +#define IOC_IOCFG31_IE_S 29 // Field: [28:27] WU_CFG // @@ -9578,9 +9578,9 @@ // // Note:When the MSB is set, the IOC will deactivate the output enable for the // DIO. -#define IOC_IOCFG31_WU_CFG_W 2 -#define IOC_IOCFG31_WU_CFG_M 0x18000000 -#define IOC_IOCFG31_WU_CFG_S 27 +#define IOC_IOCFG31_WU_CFG_W 2 +#define IOC_IOCFG31_WU_CFG_M 0x18000000 +#define IOC_IOCFG31_WU_CFG_S 27 // Field: [26:24] IOMODE // @@ -9601,25 +9601,25 @@ // Normal input / output // INV Inverted input / ouput // NORMAL Normal input / output -#define IOC_IOCFG31_IOMODE_W 3 -#define IOC_IOCFG31_IOMODE_M 0x07000000 -#define IOC_IOCFG31_IOMODE_S 24 -#define IOC_IOCFG31_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG31_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG31_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG31_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG31_IOMODE_INV 0x01000000 -#define IOC_IOCFG31_IOMODE_NORMAL 0x00000000 +#define IOC_IOCFG31_IOMODE_W 3 +#define IOC_IOCFG31_IOMODE_M 0x07000000 +#define IOC_IOCFG31_IOMODE_S 24 +#define IOC_IOCFG31_IOMODE_OPENSRC_INV 0x07000000 +#define IOC_IOCFG31_IOMODE_OPENSRC 0x06000000 +#define IOC_IOCFG31_IOMODE_OPENDR_INV 0x05000000 +#define IOC_IOCFG31_IOMODE_OPENDR 0x04000000 +#define IOC_IOCFG31_IOMODE_INV 0x01000000 +#define IOC_IOCFG31_IOMODE_NORMAL 0x00000000 // Field: [18] EDGE_IRQ_EN // // 0: No interrupt generation // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is // enabled) -#define IOC_IOCFG31_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG31_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG31_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG31_EDGE_IRQ_EN_S 18 +#define IOC_IOCFG31_EDGE_IRQ_EN 0x00040000 +#define IOC_IOCFG31_EDGE_IRQ_EN_BITN 18 +#define IOC_IOCFG31_EDGE_IRQ_EN_M 0x00040000 +#define IOC_IOCFG31_EDGE_IRQ_EN_S 18 // Field: [17:16] EDGE_DET // @@ -9629,13 +9629,13 @@ // POS Positive edge detection // NEG Negative edge detection // NONE No edge detection -#define IOC_IOCFG31_EDGE_DET_W 2 -#define IOC_IOCFG31_EDGE_DET_M 0x00030000 -#define IOC_IOCFG31_EDGE_DET_S 16 -#define IOC_IOCFG31_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG31_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG31_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG31_EDGE_DET_NONE 0x00000000 +#define IOC_IOCFG31_EDGE_DET_W 2 +#define IOC_IOCFG31_EDGE_DET_M 0x00030000 +#define IOC_IOCFG31_EDGE_DET_S 16 +#define IOC_IOCFG31_EDGE_DET_BOTH 0x00030000 +#define IOC_IOCFG31_EDGE_DET_POS 0x00020000 +#define IOC_IOCFG31_EDGE_DET_NEG 0x00010000 +#define IOC_IOCFG31_EDGE_DET_NONE 0x00000000 // Field: [14:13] PULL_CTL // @@ -9644,21 +9644,21 @@ // DIS No pull // UP Pull up // DWN Pull down -#define IOC_IOCFG31_PULL_CTL_W 2 -#define IOC_IOCFG31_PULL_CTL_M 0x00006000 -#define IOC_IOCFG31_PULL_CTL_S 13 -#define IOC_IOCFG31_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG31_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG31_PULL_CTL_DWN 0x00002000 +#define IOC_IOCFG31_PULL_CTL_W 2 +#define IOC_IOCFG31_PULL_CTL_M 0x00006000 +#define IOC_IOCFG31_PULL_CTL_S 13 +#define IOC_IOCFG31_PULL_CTL_DIS 0x00006000 +#define IOC_IOCFG31_PULL_CTL_UP 0x00004000 +#define IOC_IOCFG31_PULL_CTL_DWN 0x00002000 // Field: [12] SLEW_RED // // 0: Normal slew rate // 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG31_SLEW_RED 0x00001000 -#define IOC_IOCFG31_SLEW_RED_BITN 12 -#define IOC_IOCFG31_SLEW_RED_M 0x00001000 -#define IOC_IOCFG31_SLEW_RED_S 12 +#define IOC_IOCFG31_SLEW_RED 0x00001000 +#define IOC_IOCFG31_SLEW_RED_BITN 12 +#define IOC_IOCFG31_SLEW_RED_M 0x00001000 +#define IOC_IOCFG31_SLEW_RED_S 12 // Field: [11:10] IOCURR // @@ -9671,12 +9671,12 @@ // to AUTO // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set // to AUTO -#define IOC_IOCFG31_IOCURR_W 2 -#define IOC_IOCFG31_IOCURR_M 0x00000C00 -#define IOC_IOCFG31_IOCURR_S 10 -#define IOC_IOCFG31_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG31_IOCURR_4MA 0x00000400 -#define IOC_IOCFG31_IOCURR_2MA 0x00000000 +#define IOC_IOCFG31_IOCURR_W 2 +#define IOC_IOCFG31_IOCURR_M 0x00000C00 +#define IOC_IOCFG31_IOCURR_S 10 +#define IOC_IOCFG31_IOCURR_4_8MA 0x00000800 +#define IOC_IOCFG31_IOCURR_4MA 0x00000400 +#define IOC_IOCFG31_IOCURR_2MA 0x00000000 // Field: [9:8] IOSTR // @@ -9695,13 +9695,13 @@ // values) // AUTO Automatic drive strength, controlled by AON BATMON // based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG31_IOSTR_W 2 -#define IOC_IOCFG31_IOSTR_M 0x00000300 -#define IOC_IOCFG31_IOSTR_S 8 -#define IOC_IOCFG31_IOSTR_MAX 0x00000300 -#define IOC_IOCFG31_IOSTR_MED 0x00000200 -#define IOC_IOCFG31_IOSTR_MIN 0x00000100 -#define IOC_IOCFG31_IOSTR_AUTO 0x00000000 +#define IOC_IOCFG31_IOSTR_W 2 +#define IOC_IOCFG31_IOSTR_M 0x00000300 +#define IOC_IOCFG31_IOSTR_S 8 +#define IOC_IOCFG31_IOSTR_MAX 0x00000300 +#define IOC_IOCFG31_IOSTR_MED 0x00000200 +#define IOC_IOCFG31_IOSTR_MIN 0x00000100 +#define IOC_IOCFG31_IOSTR_AUTO 0x00000000 // Field: [5:0] PORT_ID // @@ -9789,51 +9789,50 @@ // AUX_IO AUX IO // AON_CLK32K AON 32 KHz clock (SCLK_LF) // GPIO General Purpose IO -#define IOC_IOCFG31_PORT_ID_W 6 -#define IOC_IOCFG31_PORT_ID_M 0x0000003F -#define IOC_IOCFG31_PORT_ID_S 0 -#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG31_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG31_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG31_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG31_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG31_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG31_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG31_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG31_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG31_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG31_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG31_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG31_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG31_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG31_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG31_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG31_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG31_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG31_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG31_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG31_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG31_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG31_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG31_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG31_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG31_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG31_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG31_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG31_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG31_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG31_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG31_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG31_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG31_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG31_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG31_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG31_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG31_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG31_PORT_ID_GPIO 0x00000000 - +#define IOC_IOCFG31_PORT_ID_W 6 +#define IOC_IOCFG31_PORT_ID_M 0x0000003F +#define IOC_IOCFG31_PORT_ID_S 0 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_IN 0x00000038 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_OUT 0x00000037 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_IN 0x00000036 +#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_OUT 0x00000035 +#define IOC_IOCFG31_PORT_ID_RFC_GPI1 0x00000034 +#define IOC_IOCFG31_PORT_ID_RFC_GPI0 0x00000033 +#define IOC_IOCFG31_PORT_ID_RFC_GPO3 0x00000032 +#define IOC_IOCFG31_PORT_ID_RFC_GPO2 0x00000031 +#define IOC_IOCFG31_PORT_ID_RFC_GPO1 0x00000030 +#define IOC_IOCFG31_PORT_ID_RFC_GPO0 0x0000002F +#define IOC_IOCFG31_PORT_ID_RFC_TRC 0x0000002E +#define IOC_IOCFG31_PORT_ID_I2S_MCLK 0x00000029 +#define IOC_IOCFG31_PORT_ID_I2S_BCLK 0x00000028 +#define IOC_IOCFG31_PORT_ID_I2S_WCLK 0x00000027 +#define IOC_IOCFG31_PORT_ID_I2S_AD1 0x00000026 +#define IOC_IOCFG31_PORT_ID_I2S_AD0 0x00000025 +#define IOC_IOCFG31_PORT_ID_SSI1_CLK 0x00000024 +#define IOC_IOCFG31_PORT_ID_SSI1_FSS 0x00000023 +#define IOC_IOCFG31_PORT_ID_SSI1_TX 0x00000022 +#define IOC_IOCFG31_PORT_ID_SSI1_RX 0x00000021 +#define IOC_IOCFG31_PORT_ID_CPU_SWV 0x00000020 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT7 0x0000001E +#define IOC_IOCFG31_PORT_ID_PORT_EVENT6 0x0000001D +#define IOC_IOCFG31_PORT_ID_PORT_EVENT5 0x0000001C +#define IOC_IOCFG31_PORT_ID_PORT_EVENT4 0x0000001B +#define IOC_IOCFG31_PORT_ID_PORT_EVENT3 0x0000001A +#define IOC_IOCFG31_PORT_ID_PORT_EVENT2 0x00000019 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT1 0x00000018 +#define IOC_IOCFG31_PORT_ID_PORT_EVENT0 0x00000017 +#define IOC_IOCFG31_PORT_ID_UART0_RTS 0x00000012 +#define IOC_IOCFG31_PORT_ID_UART0_CTS 0x00000011 +#define IOC_IOCFG31_PORT_ID_UART0_TX 0x00000010 +#define IOC_IOCFG31_PORT_ID_UART0_RX 0x0000000F +#define IOC_IOCFG31_PORT_ID_I2C_MSSCL 0x0000000E +#define IOC_IOCFG31_PORT_ID_I2C_MSSDA 0x0000000D +#define IOC_IOCFG31_PORT_ID_SSI0_CLK 0x0000000C +#define IOC_IOCFG31_PORT_ID_SSI0_FSS 0x0000000B +#define IOC_IOCFG31_PORT_ID_SSI0_TX 0x0000000A +#define IOC_IOCFG31_PORT_ID_SSI0_RX 0x00000009 +#define IOC_IOCFG31_PORT_ID_AUX_IO 0x00000008 +#define IOC_IOCFG31_PORT_ID_AON_CLK32K 0x00000007 +#define IOC_IOCFG31_PORT_ID_GPIO 0x00000000 #endif // __IOC__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_memmap.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_memmap.h index cfad06d..ef94ddc 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_memmap.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_memmap.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_memmap_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_memmap_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_MEMMAP_H__ #define __HW_MEMMAP_H__ @@ -43,116 +43,116 @@ // peripherals on the CPU_MMAP interface // //***************************************************************************** -#define FLASHMEM_BASE 0x00000000 // FLASHMEM -#define BROM_BASE 0x10000000 // BROM -#define GPRAM_BASE 0x11000000 // GPRAM -#define SRAM_BASE 0x20000000 // SRAM -#define RFC_RAM_BASE 0x21000000 // RFC_RAM -#define SSI0_BASE 0x40000000 // SSI -#define UART0_BASE 0x40001000 // UART -#define I2C0_BASE 0x40002000 // I2C -#define SSI1_BASE 0x40008000 // SSI -#define GPT0_BASE 0x40010000 // GPT -#define GPT1_BASE 0x40011000 // GPT -#define GPT2_BASE 0x40012000 // GPT -#define GPT3_BASE 0x40013000 // GPT -#define UDMA0_BASE 0x40020000 // UDMA -#define I2S0_BASE 0x40021000 // I2S -#define GPIO_BASE 0x40022000 // GPIO -#define CRYPTO_BASE 0x40024000 // CRYPTO -#define TRNG_BASE 0x40028000 // TRNG -#define FLASH_BASE 0x40030000 // FLASH -#define VIMS_BASE 0x40034000 // VIMS -#define RFC_PWR_BASE 0x40040000 // RFC_PWR -#define RFC_DBELL_BASE 0x40041000 // RFC_DBELL -#define RFC_RAT_BASE 0x40043000 // RFC_RAT -#define RFC_FSCA_BASE 0x40044000 // RFC_FSCA -#define WDT_BASE 0x40080000 // WDT -#define IOC_BASE 0x40081000 // IOC -#define PRCM_BASE 0x40082000 // PRCM -#define EVENT_BASE 0x40083000 // EVENT -#define SMPH_BASE 0x40084000 // SMPH -#define ADI2_BASE 0x40086000 // ADI -#define ADI3_BASE 0x40086200 // ADI -#define AON_SYSCTL_BASE 0x40090000 // AON_SYSCTL -#define AON_WUC_BASE 0x40091000 // AON_WUC -#define AON_RTC_BASE 0x40092000 // AON_RTC -#define AON_EVENT_BASE 0x40093000 // AON_EVENT -#define AON_IOC_BASE 0x40094000 // AON_IOC -#define AON_BATMON_BASE 0x40095000 // AON_BATMON -#define AUX_AIODIO0_BASE 0x400C1000 // AUX_AIODIO -#define AUX_AIODIO1_BASE 0x400C2000 // AUX_AIODIO -#define AUX_TDC_BASE 0x400C4000 // AUX_TDC -#define AUX_EVCTL_BASE 0x400C5000 // AUX_EVCTL -#define AUX_WUC_BASE 0x400C6000 // AUX_WUC -#define AUX_TIMER_BASE 0x400C7000 // AUX_TIMER -#define AUX_SMPH_BASE 0x400C8000 // AUX_SMPH -#define AUX_ANAIF_BASE 0x400C9000 // AUX_ANAIF -#define AUX_DDI0_OSC_BASE 0x400CA000 // DDI -#define AUX_ADI4_BASE 0x400CB000 // ADI -#define AUX_RAM_BASE 0x400E0000 // AUX_RAM -#define AUX_SCE_BASE 0x400E1000 // AUX_SCE -#define FLASH_CFG_BASE 0x50000000 // CC26_DUMMY_COMP -#define FCFG1_BASE 0x50001000 // FCFG1 -#define FCFG2_BASE 0x50002000 // FCFG2 +#define FLASHMEM_BASE 0x00000000 // FLASHMEM +#define BROM_BASE 0x10000000 // BROM +#define GPRAM_BASE 0x11000000 // GPRAM +#define SRAM_BASE 0x20000000 // SRAM +#define RFC_RAM_BASE 0x21000000 // RFC_RAM +#define SSI0_BASE 0x40000000 // SSI +#define UART0_BASE 0x40001000 // UART +#define I2C0_BASE 0x40002000 // I2C +#define SSI1_BASE 0x40008000 // SSI +#define GPT0_BASE 0x40010000 // GPT +#define GPT1_BASE 0x40011000 // GPT +#define GPT2_BASE 0x40012000 // GPT +#define GPT3_BASE 0x40013000 // GPT +#define UDMA0_BASE 0x40020000 // UDMA +#define I2S0_BASE 0x40021000 // I2S +#define GPIO_BASE 0x40022000 // GPIO +#define CRYPTO_BASE 0x40024000 // CRYPTO +#define TRNG_BASE 0x40028000 // TRNG +#define FLASH_BASE 0x40030000 // FLASH +#define VIMS_BASE 0x40034000 // VIMS +#define RFC_PWR_BASE 0x40040000 // RFC_PWR +#define RFC_DBELL_BASE 0x40041000 // RFC_DBELL +#define RFC_RAT_BASE 0x40043000 // RFC_RAT +#define RFC_FSCA_BASE 0x40044000 // RFC_FSCA +#define WDT_BASE 0x40080000 // WDT +#define IOC_BASE 0x40081000 // IOC +#define PRCM_BASE 0x40082000 // PRCM +#define EVENT_BASE 0x40083000 // EVENT +#define SMPH_BASE 0x40084000 // SMPH +#define ADI2_BASE 0x40086000 // ADI +#define ADI3_BASE 0x40086200 // ADI +#define AON_SYSCTL_BASE 0x40090000 // AON_SYSCTL +#define AON_WUC_BASE 0x40091000 // AON_WUC +#define AON_RTC_BASE 0x40092000 // AON_RTC +#define AON_EVENT_BASE 0x40093000 // AON_EVENT +#define AON_IOC_BASE 0x40094000 // AON_IOC +#define AON_BATMON_BASE 0x40095000 // AON_BATMON +#define AUX_AIODIO0_BASE 0x400C1000 // AUX_AIODIO +#define AUX_AIODIO1_BASE 0x400C2000 // AUX_AIODIO +#define AUX_TDC_BASE 0x400C4000 // AUX_TDC +#define AUX_EVCTL_BASE 0x400C5000 // AUX_EVCTL +#define AUX_WUC_BASE 0x400C6000 // AUX_WUC +#define AUX_TIMER_BASE 0x400C7000 // AUX_TIMER +#define AUX_SMPH_BASE 0x400C8000 // AUX_SMPH +#define AUX_ANAIF_BASE 0x400C9000 // AUX_ANAIF +#define AUX_DDI0_OSC_BASE 0x400CA000 // DDI +#define AUX_ADI4_BASE 0x400CB000 // ADI +#define AUX_RAM_BASE 0x400E0000 // AUX_RAM +#define AUX_SCE_BASE 0x400E1000 // AUX_SCE +#define FLASH_CFG_BASE 0x50000000 // CC26_DUMMY_COMP +#define FCFG1_BASE 0x50001000 // FCFG1 +#define FCFG2_BASE 0x50002000 // FCFG2 #ifndef CCFG_BASE - #define CCFG_BASE 0x50003000 // CCFG +#define CCFG_BASE 0x50003000 // CCFG #endif -#define CCFG_BASE_DEFAULT 0x50003000 // CCFG -#define SSI0_NONBUF_BASE 0x60000000 // SSI CPU nonbuf base -#define UART0_NONBUF_BASE 0x60001000 // UART CPU nonbuf base -#define I2C0_NONBUF_BASE 0x60002000 // I2C CPU nonbuf base -#define SSI1_NONBUF_BASE 0x60008000 // SSI CPU nonbuf base -#define GPT0_NONBUF_BASE 0x60010000 // GPT CPU nonbuf base -#define GPT1_NONBUF_BASE 0x60011000 // GPT CPU nonbuf base -#define GPT2_NONBUF_BASE 0x60012000 // GPT CPU nonbuf base -#define GPT3_NONBUF_BASE 0x60013000 // GPT CPU nonbuf base -#define UDMA0_NONBUF_BASE 0x60020000 // UDMA CPU nonbuf base -#define I2S0_NONBUF_BASE 0x60021000 // I2S CPU nonbuf base -#define GPIO_NONBUF_BASE 0x60022000 // GPIO CPU nonbuf base -#define CRYPTO_NONBUF_BASE 0x60024000 // CRYPTO CPU nonbuf base -#define TRNG_NONBUF_BASE 0x60028000 // TRNG CPU nonbuf base -#define FLASH_NONBUF_BASE 0x60030000 // FLASH CPU nonbuf base -#define VIMS_NONBUF_BASE 0x60034000 // VIMS CPU nonbuf base -#define RFC_PWR_NONBUF_BASE 0x60040000 // RFC_PWR CPU nonbuf base -#define RFC_DBELL_NONBUF_BASE 0x60041000 // RFC_DBELL CPU nonbuf base -#define RFC_RAT_NONBUF_BASE 0x60043000 // RFC_RAT CPU nonbuf base -#define RFC_FSCA_NONBUF_BASE 0x60044000 // RFC_FSCA CPU nonbuf base -#define WDT_NONBUF_BASE 0x60080000 // WDT CPU nonbuf base -#define IOC_NONBUF_BASE 0x60081000 // IOC CPU nonbuf base -#define PRCM_NONBUF_BASE 0x60082000 // PRCM CPU nonbuf base -#define EVENT_NONBUF_BASE 0x60083000 // EVENT CPU nonbuf base -#define SMPH_NONBUF_BASE 0x60084000 // SMPH CPU nonbuf base -#define ADI2_NONBUF_BASE 0x60086000 // ADI CPU nonbuf base -#define ADI3_NONBUF_BASE 0x60086200 // ADI CPU nonbuf base -#define AON_SYSCTL_NONBUF_BASE 0x60090000 // AON_SYSCTL CPU nonbuf base -#define AON_WUC_NONBUF_BASE 0x60091000 // AON_WUC CPU nonbuf base -#define AON_RTC_NONBUF_BASE 0x60092000 // AON_RTC CPU nonbuf base -#define AON_EVENT_NONBUF_BASE 0x60093000 // AON_EVENT CPU nonbuf base -#define AON_IOC_NONBUF_BASE 0x60094000 // AON_IOC CPU nonbuf base -#define AON_BATMON_NONBUF_BASE 0x60095000 // AON_BATMON CPU nonbuf base +#define CCFG_BASE_DEFAULT 0x50003000 // CCFG +#define SSI0_NONBUF_BASE 0x60000000 // SSI CPU nonbuf base +#define UART0_NONBUF_BASE 0x60001000 // UART CPU nonbuf base +#define I2C0_NONBUF_BASE 0x60002000 // I2C CPU nonbuf base +#define SSI1_NONBUF_BASE 0x60008000 // SSI CPU nonbuf base +#define GPT0_NONBUF_BASE 0x60010000 // GPT CPU nonbuf base +#define GPT1_NONBUF_BASE 0x60011000 // GPT CPU nonbuf base +#define GPT2_NONBUF_BASE 0x60012000 // GPT CPU nonbuf base +#define GPT3_NONBUF_BASE 0x60013000 // GPT CPU nonbuf base +#define UDMA0_NONBUF_BASE 0x60020000 // UDMA CPU nonbuf base +#define I2S0_NONBUF_BASE 0x60021000 // I2S CPU nonbuf base +#define GPIO_NONBUF_BASE 0x60022000 // GPIO CPU nonbuf base +#define CRYPTO_NONBUF_BASE 0x60024000 // CRYPTO CPU nonbuf base +#define TRNG_NONBUF_BASE 0x60028000 // TRNG CPU nonbuf base +#define FLASH_NONBUF_BASE 0x60030000 // FLASH CPU nonbuf base +#define VIMS_NONBUF_BASE 0x60034000 // VIMS CPU nonbuf base +#define RFC_PWR_NONBUF_BASE 0x60040000 // RFC_PWR CPU nonbuf base +#define RFC_DBELL_NONBUF_BASE 0x60041000 // RFC_DBELL CPU nonbuf base +#define RFC_RAT_NONBUF_BASE 0x60043000 // RFC_RAT CPU nonbuf base +#define RFC_FSCA_NONBUF_BASE 0x60044000 // RFC_FSCA CPU nonbuf base +#define WDT_NONBUF_BASE 0x60080000 // WDT CPU nonbuf base +#define IOC_NONBUF_BASE 0x60081000 // IOC CPU nonbuf base +#define PRCM_NONBUF_BASE 0x60082000 // PRCM CPU nonbuf base +#define EVENT_NONBUF_BASE 0x60083000 // EVENT CPU nonbuf base +#define SMPH_NONBUF_BASE 0x60084000 // SMPH CPU nonbuf base +#define ADI2_NONBUF_BASE 0x60086000 // ADI CPU nonbuf base +#define ADI3_NONBUF_BASE 0x60086200 // ADI CPU nonbuf base +#define AON_SYSCTL_NONBUF_BASE 0x60090000 // AON_SYSCTL CPU nonbuf base +#define AON_WUC_NONBUF_BASE 0x60091000 // AON_WUC CPU nonbuf base +#define AON_RTC_NONBUF_BASE 0x60092000 // AON_RTC CPU nonbuf base +#define AON_EVENT_NONBUF_BASE 0x60093000 // AON_EVENT CPU nonbuf base +#define AON_IOC_NONBUF_BASE 0x60094000 // AON_IOC CPU nonbuf base +#define AON_BATMON_NONBUF_BASE 0x60095000 // AON_BATMON CPU nonbuf base #define AUX_AIODIO0_NONBUF_BASE \ 0x600C1000 // AUX_AIODIO CPU nonbuf base #define AUX_AIODIO1_NONBUF_BASE \ - 0x600C2000 // AUX_AIODIO CPU nonbuf base -#define AUX_TDC_NONBUF_BASE 0x600C4000 // AUX_TDC CPU nonbuf base -#define AUX_EVCTL_NONBUF_BASE 0x600C5000 // AUX_EVCTL CPU nonbuf base -#define AUX_WUC_NONBUF_BASE 0x600C6000 // AUX_WUC CPU nonbuf base -#define AUX_TIMER_NONBUF_BASE 0x600C7000 // AUX_TIMER CPU nonbuf base -#define AUX_SMPH_NONBUF_BASE 0x600C8000 // AUX_SMPH CPU nonbuf base -#define AUX_ANAIF_NONBUF_BASE 0x600C9000 // AUX_ANAIF CPU nonbuf base + 0x600C2000 // AUX_AIODIO CPU nonbuf base +#define AUX_TDC_NONBUF_BASE 0x600C4000 // AUX_TDC CPU nonbuf base +#define AUX_EVCTL_NONBUF_BASE 0x600C5000 // AUX_EVCTL CPU nonbuf base +#define AUX_WUC_NONBUF_BASE 0x600C6000 // AUX_WUC CPU nonbuf base +#define AUX_TIMER_NONBUF_BASE 0x600C7000 // AUX_TIMER CPU nonbuf base +#define AUX_SMPH_NONBUF_BASE 0x600C8000 // AUX_SMPH CPU nonbuf base +#define AUX_ANAIF_NONBUF_BASE 0x600C9000 // AUX_ANAIF CPU nonbuf base #define AUX_DDI0_OSC_NONBUF_BASE \ - 0x600CA000 // DDI CPU nonbuf base -#define AUX_ADI4_NONBUF_BASE 0x600CB000 // ADI CPU nonbuf base -#define AUX_RAM_NONBUF_BASE 0x600E0000 // AUX_RAM CPU nonbuf base -#define AUX_SCE_NONBUF_BASE 0x600E1000 // AUX_SCE CPU nonbuf base -#define FLASHMEM_ALIAS_BASE 0xA0000000 // FLASHMEM Alias base -#define CPU_ITM_BASE 0xE0000000 // CPU_ITM -#define CPU_DWT_BASE 0xE0001000 // CPU_DWT -#define CPU_FPB_BASE 0xE0002000 // CPU_FPB -#define CPU_SCS_BASE 0xE000E000 // CPU_SCS -#define CPU_TPIU_BASE 0xE0040000 // CPU_TPIU -#define CPU_TIPROP_BASE 0xE00FE000 // CPU_TIPROP -#define CPU_ROM_TABLE_BASE 0xE00FF000 // CPU_ROM_TABLE + 0x600CA000 // DDI CPU nonbuf base +#define AUX_ADI4_NONBUF_BASE 0x600CB000 // ADI CPU nonbuf base +#define AUX_RAM_NONBUF_BASE 0x600E0000 // AUX_RAM CPU nonbuf base +#define AUX_SCE_NONBUF_BASE 0x600E1000 // AUX_SCE CPU nonbuf base +#define FLASHMEM_ALIAS_BASE 0xA0000000 // FLASHMEM Alias base +#define CPU_ITM_BASE 0xE0000000 // CPU_ITM +#define CPU_DWT_BASE 0xE0001000 // CPU_DWT +#define CPU_FPB_BASE 0xE0002000 // CPU_FPB +#define CPU_SCS_BASE 0xE000E000 // CPU_SCS +#define CPU_TPIU_BASE 0xE0040000 // CPU_TPIU +#define CPU_TIPROP_BASE 0xE00FE000 // CPU_TIPROP +#define CPU_ROM_TABLE_BASE 0xE00FF000 // CPU_ROM_TABLE #endif // __HW_MEMMAP__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_nvic.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_nvic.h index 6f1f2d0..4ee246d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_nvic.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_nvic.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_nvic.h -* Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) -* Revision: 42365 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_nvic.h + * Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) + * Revision: 42365 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_NVIC_H__ #define __HW_NVIC_H__ @@ -42,89 +42,89 @@ // The following are defines for the NVIC register addresses. // //***************************************************************************** -#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg -#define NVIC_ACTLR 0xE000E008 // Auxiliary Control -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg +#define NVIC_ACTLR 0xE000E008 // Auxiliary Control +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status // Register -#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register -#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register -#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg -#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable -#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable -#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable -#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable -#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending -#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending -#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending -#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending -#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit -#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit -#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority -#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority -#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority -#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority -#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority -#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority -#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority -#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority -#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority -#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority -#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority -#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority -#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority -#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority -#define NVIC_CPUID 0xE000ED00 // CPU ID Base -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset -#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg +#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable +#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable +#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable +#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable +#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending +#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending +#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending +#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending +#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit +#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit +#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority +#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority +#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority +#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority +#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority +#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority +#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority +#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority +#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority +#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority +#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority +#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority +#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority +#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority +#define NVIC_CPUID 0xE000ED00 // CPU ID Base +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset +#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset // Control -#define NVIC_SYS_CTRL 0xE000ED10 // System Control -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control -#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 -#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 -#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 -#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status -#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size -#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 -#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size +#define NVIC_SYS_CTRL 0xE000ED10 // System Control +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control +#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 +#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 +#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size +#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 +#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size // Alias 1 -#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 -#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size +#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 +#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size // Alias 2 -#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 -#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size +#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 +#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size // Alias 3 -#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg -#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select -#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data -#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt //***************************************************************************** // // The following are defines for the bit fields in the NVIC_INT_TYPE register. // //***************************************************************************** -#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) -#define NVIC_INT_TYPE_LINES_S 0 +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_ACTLR register. // //***************************************************************************** -#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding -#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer -#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple // Cycle Instructions //***************************************************************************** @@ -132,18 +132,18 @@ // The following are defines for the bit fields in the NVIC_ST_CTRL register. // //***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable //***************************************************************************** // // The following are defines for the bit fields in the NVIC_ST_RELOAD register. // //***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value -#define NVIC_ST_RELOAD_S 0 +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value +#define NVIC_ST_RELOAD_S 0 //***************************************************************************** // @@ -151,609 +151,609 @@ // register. // //***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value -#define NVIC_ST_CURRENT_S 0 +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value +#define NVIC_ST_CURRENT_S 0 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_ST_CAL register. // //***************************************************************************** -#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock -#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew -#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value -#define NVIC_ST_CAL_ONEMS_S 0 +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_EN0 register. // //***************************************************************************** -#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable -#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable //***************************************************************************** // // The following are defines for the bit fields in the NVIC_EN1 register. // //***************************************************************************** -#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable -#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable -#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable -#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable -#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable -#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable -#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable -#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable -#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable -#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable -#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable -#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable -#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable -#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable -#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable -#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable -#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable -#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable -#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable -#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable -#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable -#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable -#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable -#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable +#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable +#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable +#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable +#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable +#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable +#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable +#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable +#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable +#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable +#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable +#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable +#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable +#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable +#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable +#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable +#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable +#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable +#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable +#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable +#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable +#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable +#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable +#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable +#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable //***************************************************************************** // // The following are defines for the bit fields in the NVIC_DIS0 register. // //***************************************************************************** -#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable -#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable //***************************************************************************** // // The following are defines for the bit fields in the NVIC_DIS1 register. // //***************************************************************************** -#define NVIC_DIS1_INT_M 0x007FFFFF // Interrupt Disable -#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable -#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable -#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable -#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable -#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable -#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable -#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable -#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable -#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable -#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable -#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable -#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable -#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable -#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable -#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable -#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable -#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable -#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable -#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable -#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable -#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable -#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable -#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable +#define NVIC_DIS1_INT_M 0x007FFFFF // Interrupt Disable +#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable +#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable +#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable +#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable +#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable +#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable +#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable +#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable +#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable +#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable +#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable +#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable +#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable +#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable +#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable +#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable +#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable +#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable +#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable +#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable +#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable +#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable +#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PEND0 register. // //***************************************************************************** -#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending -#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PEND1 register. // //***************************************************************************** -#define NVIC_PEND1_INT_M 0x007FFFFF // Interrupt Set Pending -#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend -#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend -#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend -#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend -#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend -#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend -#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend -#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend -#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend -#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend -#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend -#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend -#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend -#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend -#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend -#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend -#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend -#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend -#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend -#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend -#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend -#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend -#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend +#define NVIC_PEND1_INT_M 0x007FFFFF // Interrupt Set Pending +#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend +#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend +#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend +#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend +#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend +#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend +#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend +#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend +#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend +#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend +#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend +#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend +#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend +#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend +#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend +#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend +#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend +#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend +#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend +#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend +#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend +#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend +#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend //***************************************************************************** // // The following are defines for the bit fields in the NVIC_UNPEND0 register. // //***************************************************************************** -#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending -#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend //***************************************************************************** // // The following are defines for the bit fields in the NVIC_UNPEND1 register. // //***************************************************************************** -#define NVIC_UNPEND1_INT_M 0x007FFFFF // Interrupt Clear Pending -#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend -#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend -#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend -#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend -#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend -#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend -#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend -#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend -#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend -#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend -#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend -#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend -#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend -#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend -#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend -#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend -#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend -#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend -#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend -#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend -#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend -#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend -#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend +#define NVIC_UNPEND1_INT_M 0x007FFFFF // Interrupt Clear Pending +#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend +#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend +#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend +#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend +#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend +#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend +#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend +#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend +#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend +#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend +#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend +#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend +#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend +#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend +#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend +#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend +#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend +#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend +#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend +#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend +#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend +#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend +#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend //***************************************************************************** // // The following are defines for the bit fields in the NVIC_ACTIVE0 register. // //***************************************************************************** -#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active -#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active //***************************************************************************** // // The following are defines for the bit fields in the NVIC_ACTIVE1 register. // //***************************************************************************** -#define NVIC_ACTIVE1_INT_M 0x007FFFFF // Interrupt Active -#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active -#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active -#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active -#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active -#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active -#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active -#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active -#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active -#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active -#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active -#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active -#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active -#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active -#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active -#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active -#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active -#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active -#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active -#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active -#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active -#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active -#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active -#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active +#define NVIC_ACTIVE1_INT_M 0x007FFFFF // Interrupt Active +#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active +#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active +#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active +#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active +#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active +#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active +#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active +#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active +#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active +#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active +#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active +#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active +#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active +#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active +#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active +#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active +#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active +#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active +#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active +#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active +#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active +#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active +#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI0 register. // //***************************************************************************** -#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask -#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask -#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask -#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask -#define NVIC_PRI0_INT3_S 29 -#define NVIC_PRI0_INT2_S 21 -#define NVIC_PRI0_INT1_S 13 -#define NVIC_PRI0_INT0_S 5 +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI1 register. // //***************************************************************************** -#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask -#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask -#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask -#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask -#define NVIC_PRI1_INT7_S 29 -#define NVIC_PRI1_INT6_S 21 -#define NVIC_PRI1_INT5_S 13 -#define NVIC_PRI1_INT4_S 5 +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI2 register. // //***************************************************************************** -#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask -#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask -#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask -#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask -#define NVIC_PRI2_INT11_S 29 -#define NVIC_PRI2_INT10_S 21 -#define NVIC_PRI2_INT9_S 13 -#define NVIC_PRI2_INT8_S 5 +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI3 register. // //***************************************************************************** -#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask -#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask -#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask -#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask -#define NVIC_PRI3_INT15_S 29 -#define NVIC_PRI3_INT14_S 21 -#define NVIC_PRI3_INT13_S 13 -#define NVIC_PRI3_INT12_S 5 +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI4 register. // //***************************************************************************** -#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask -#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask -#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask -#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask -#define NVIC_PRI4_INT19_S 29 -#define NVIC_PRI4_INT18_S 21 -#define NVIC_PRI4_INT17_S 13 -#define NVIC_PRI4_INT16_S 5 +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI5 register. // //***************************************************************************** -#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask -#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask -#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask -#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask -#define NVIC_PRI5_INT23_S 29 -#define NVIC_PRI5_INT22_S 21 -#define NVIC_PRI5_INT21_S 13 -#define NVIC_PRI5_INT20_S 5 +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI6 register. // //***************************************************************************** -#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask -#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask -#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask -#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask -#define NVIC_PRI6_INT27_S 29 -#define NVIC_PRI6_INT26_S 21 -#define NVIC_PRI6_INT25_S 13 -#define NVIC_PRI6_INT24_S 5 +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI7 register. // //***************************************************************************** -#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask -#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask -#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask -#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask -#define NVIC_PRI7_INT31_S 29 -#define NVIC_PRI7_INT30_S 21 -#define NVIC_PRI7_INT29_S 13 -#define NVIC_PRI7_INT28_S 5 +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI8 register. // //***************************************************************************** -#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask -#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask -#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask -#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask -#define NVIC_PRI8_INT35_S 29 -#define NVIC_PRI8_INT34_S 21 -#define NVIC_PRI8_INT33_S 13 -#define NVIC_PRI8_INT32_S 5 +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI9 register. // //***************************************************************************** -#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask -#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask -#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask -#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask -#define NVIC_PRI9_INT39_S 29 -#define NVIC_PRI9_INT38_S 21 -#define NVIC_PRI9_INT37_S 13 -#define NVIC_PRI9_INT36_S 5 +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI10 register. // //***************************************************************************** -#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask -#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask -#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask -#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask -#define NVIC_PRI10_INT43_S 29 -#define NVIC_PRI10_INT42_S 21 -#define NVIC_PRI10_INT41_S 13 -#define NVIC_PRI10_INT40_S 5 +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI11 register. // //***************************************************************************** -#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask -#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask -#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask -#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask -#define NVIC_PRI11_INT47_S 29 -#define NVIC_PRI11_INT46_S 21 -#define NVIC_PRI11_INT45_S 13 -#define NVIC_PRI11_INT44_S 5 +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI12 register. // //***************************************************************************** -#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask -#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask -#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask -#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask -#define NVIC_PRI12_INT51_S 29 -#define NVIC_PRI12_INT50_S 21 -#define NVIC_PRI12_INT49_S 13 -#define NVIC_PRI12_INT48_S 5 +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_PRI13 register. // //***************************************************************************** -#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask -#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask -#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask -#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask -#define NVIC_PRI13_INT55_S 29 -#define NVIC_PRI13_INT54_S 21 -#define NVIC_PRI13_INT53_S 13 -#define NVIC_PRI13_INT52_S 5 +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_CPUID register. // //***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code -#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number -#define NVIC_CPUID_CON_M 0x000F0000 // Constant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number -#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor -#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor -#define NVIC_CPUID_REV_M 0x0000000F // Revision Number +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number //***************************************************************************** // // The following are defines for the bit fields in the NVIC_INT_CTRL register. // //***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending -#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending -#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number #undef NVIC_INT_CTRL_VEC_PEN_M -#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number #define NVIC_INT_CTRL_VEC_PEN_NMI \ - 0x00002000 // NMI + 0x00002000 // NMI #define NVIC_INT_CTRL_VEC_PEN_HARD \ - 0x00003000 // Hard fault + 0x00003000 // Hard fault #define NVIC_INT_CTRL_VEC_PEN_MEM \ - 0x00004000 // Memory management fault + 0x00004000 // Memory management fault #define NVIC_INT_CTRL_VEC_PEN_BUS \ - 0x00005000 // Bus fault + 0x00005000 // Bus fault #define NVIC_INT_CTRL_VEC_PEN_USG \ - 0x00006000 // Usage fault + 0x00006000 // Usage fault #define NVIC_INT_CTRL_VEC_PEN_SVC \ - 0x0000B000 // SVCall + 0x0000B000 // SVCall #define NVIC_INT_CTRL_VEC_PEN_PNDSV \ - 0x0000E000 // PendSV + 0x0000E000 // PendSV #define NVIC_INT_CTRL_VEC_PEN_TICK \ - 0x0000F000 // SysTick -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base -#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number #undef NVIC_INT_CTRL_VEC_ACT_M -#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number #define NVIC_INT_CTRL_VEC_PEN_S 12 #define NVIC_INT_CTRL_VEC_ACT_S 0 @@ -762,89 +762,89 @@ // The following are defines for the bit fields in the NVIC_VTABLE register. // //***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset +#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset #undef NVIC_VTABLE_OFFSET_M -#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset -#define NVIC_VTABLE_OFFSET_S 9 +#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset +#define NVIC_VTABLE_OFFSET_S 9 #undef NVIC_VTABLE_OFFSET_S -#define NVIC_VTABLE_OFFSET_S 10 +#define NVIC_VTABLE_OFFSET_S 10 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_APINT register. // //***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault -#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset //***************************************************************************** // // The following are defines for the bit fields in the NVIC_SYS_CTRL register. // //***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit //***************************************************************************** // // The following are defines for the bit fields in the NVIC_CFG_CTRL register. // //***************************************************************************** -#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception // Entry -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and // Fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control //***************************************************************************** // // The following are defines for the bit fields in the NVIC_SYS_PRI1 register. // //***************************************************************************** -#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority -#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority -#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority -#define NVIC_SYS_PRI1_USAGE_S 21 -#define NVIC_SYS_PRI1_BUS_S 13 -#define NVIC_SYS_PRI1_MEM_S 5 +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_SYS_PRI2 register. // //***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority -#define NVIC_SYS_PRI2_SVC_S 29 +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_SYS_PRI3 register. // //***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority -#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority -#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority -#define NVIC_SYS_PRI3_TICK_S 29 -#define NVIC_SYS_PRI3_PENDSV_S 21 -#define NVIC_SYS_PRI3_DEBUG_S 5 +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 //***************************************************************************** // @@ -852,21 +852,21 @@ // register. // //***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending -#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending #define NVIC_SYS_HND_CTRL_USAGEP \ - 0x00001000 // Usage Fault Pending -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active //***************************************************************************** // @@ -874,30 +874,30 @@ // register. // //***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage // Fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid -#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy // State Preservation -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error -#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address // Register Valid -#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on // Floating-Point Lazy State // Preservation -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation //***************************************************************************** // @@ -905,9 +905,9 @@ // register. // //***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault //***************************************************************************** // @@ -915,19 +915,19 @@ // register. // //***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request //***************************************************************************** // // The following are defines for the bit fields in the NVIC_MM_ADDR register. // //***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_MM_ADDR_S 0 +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_MM_ADDR_S 0 //***************************************************************************** // @@ -935,92 +935,92 @@ // register. // //***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_FAULT_ADDR_S 0 +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_FAULT_ADDR_S 0 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_DBG_CTRL register. // //***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key #define NVIC_DBG_CTRL_S_RESET_ST \ - 0x02000000 // Core has reset since last read + 0x02000000 // Core has reset since last read #define NVIC_DBG_CTRL_S_RETIRE_ST \ - 0x01000000 // Core has executed insruction + 0x01000000 // Core has executed insruction // since last read -#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up -#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available #define NVIC_DBG_CTRL_C_SNAPSTALL \ - 0x00000020 // Breaks a stalled load/store -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug //***************************************************************************** // // The following are defines for the bit fields in the NVIC_DBG_XFER register. // //***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask //***************************************************************************** // // The following are defines for the bit fields in the NVIC_DBG_DATA register. // //***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 //***************************************************************************** // // The following are defines for the bit fields in the NVIC_DBG_INT register. // //***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch //***************************************************************************** // // The following are defines for the bit fields in the NVIC_SW_TRIG register. // //***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID -#define NVIC_SW_TRIG_INTID_S 0 +#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID +#define NVIC_SW_TRIG_INTID_S 0 #endif // __HW_NVIC_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_prcm.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_prcm.h index 7974ad0..535f69d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_prcm.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_prcm.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_prcm_h -* Revised: 2017-09-14 10:33:07 +0200 (Thu, 14 Sep 2017) -* Revision: 49733 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_prcm_h + * Revised: 2017-09-14 10:33:07 +0200 (Thu, 14 Sep 2017) + * Revision: 49733 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_PRCM_H__ #define __HW_PRCM_H__ @@ -44,181 +44,181 @@ // //***************************************************************************** // Infrastructure Clock Division Factor For Run Mode -#define PRCM_O_INFRCLKDIVR 0x00000000 +#define PRCM_O_INFRCLKDIVR 0x00000000 // Infrastructure Clock Division Factor For Sleep Mode -#define PRCM_O_INFRCLKDIVS 0x00000004 +#define PRCM_O_INFRCLKDIVS 0x00000004 // Infrastructure Clock Division Factor For DeepSleep Mode -#define PRCM_O_INFRCLKDIVDS 0x00000008 +#define PRCM_O_INFRCLKDIVDS 0x00000008 // MCU Voltage Domain Control -#define PRCM_O_VDCTL 0x0000000C +#define PRCM_O_VDCTL 0x0000000C // Load PRCM Settings To CLKCTRL Power Domain -#define PRCM_O_CLKLOADCTL 0x00000028 +#define PRCM_O_CLKLOADCTL 0x00000028 // RFC Clock Gate -#define PRCM_O_RFCCLKG 0x0000002C +#define PRCM_O_RFCCLKG 0x0000002C // VIMS Clock Gate -#define PRCM_O_VIMSCLKG 0x00000030 +#define PRCM_O_VIMSCLKG 0x00000030 // TRNG, CRYPTO And UDMA Clock Gate For Run Mode -#define PRCM_O_SECDMACLKGR 0x0000003C +#define PRCM_O_SECDMACLKGR 0x0000003C // TRNG, CRYPTO And UDMA Clock Gate For Sleep Mode -#define PRCM_O_SECDMACLKGS 0x00000040 +#define PRCM_O_SECDMACLKGS 0x00000040 // TRNG, CRYPTO And UDMA Clock Gate For Deep Sleep Mode -#define PRCM_O_SECDMACLKGDS 0x00000044 +#define PRCM_O_SECDMACLKGDS 0x00000044 // GPIO Clock Gate For Run Mode -#define PRCM_O_GPIOCLKGR 0x00000048 +#define PRCM_O_GPIOCLKGR 0x00000048 // GPIO Clock Gate For Sleep Mode -#define PRCM_O_GPIOCLKGS 0x0000004C +#define PRCM_O_GPIOCLKGS 0x0000004C // GPIO Clock Gate For Deep Sleep Mode -#define PRCM_O_GPIOCLKGDS 0x00000050 +#define PRCM_O_GPIOCLKGDS 0x00000050 // GPT Clock Gate For Run Mode -#define PRCM_O_GPTCLKGR 0x00000054 +#define PRCM_O_GPTCLKGR 0x00000054 // GPT Clock Gate For Sleep Mode -#define PRCM_O_GPTCLKGS 0x00000058 +#define PRCM_O_GPTCLKGS 0x00000058 // GPT Clock Gate For Deep Sleep Mode -#define PRCM_O_GPTCLKGDS 0x0000005C +#define PRCM_O_GPTCLKGDS 0x0000005C // I2C Clock Gate For Run Mode -#define PRCM_O_I2CCLKGR 0x00000060 +#define PRCM_O_I2CCLKGR 0x00000060 // I2C Clock Gate For Sleep Mode -#define PRCM_O_I2CCLKGS 0x00000064 +#define PRCM_O_I2CCLKGS 0x00000064 // I2C Clock Gate For Deep Sleep Mode -#define PRCM_O_I2CCLKGDS 0x00000068 +#define PRCM_O_I2CCLKGDS 0x00000068 // UART Clock Gate For Run Mode -#define PRCM_O_UARTCLKGR 0x0000006C +#define PRCM_O_UARTCLKGR 0x0000006C // UART Clock Gate For Sleep Mode -#define PRCM_O_UARTCLKGS 0x00000070 +#define PRCM_O_UARTCLKGS 0x00000070 // UART Clock Gate For Deep Sleep Mode -#define PRCM_O_UARTCLKGDS 0x00000074 +#define PRCM_O_UARTCLKGDS 0x00000074 // SSI Clock Gate For Run Mode -#define PRCM_O_SSICLKGR 0x00000078 +#define PRCM_O_SSICLKGR 0x00000078 // SSI Clock Gate For Sleep Mode -#define PRCM_O_SSICLKGS 0x0000007C +#define PRCM_O_SSICLKGS 0x0000007C // SSI Clock Gate For Deep Sleep Mode -#define PRCM_O_SSICLKGDS 0x00000080 +#define PRCM_O_SSICLKGDS 0x00000080 // I2S Clock Gate For Run Mode -#define PRCM_O_I2SCLKGR 0x00000084 +#define PRCM_O_I2SCLKGR 0x00000084 // I2S Clock Gate For Sleep Mode -#define PRCM_O_I2SCLKGS 0x00000088 +#define PRCM_O_I2SCLKGS 0x00000088 // I2S Clock Gate For Deep Sleep Mode -#define PRCM_O_I2SCLKGDS 0x0000008C +#define PRCM_O_I2SCLKGDS 0x0000008C // Internal -#define PRCM_O_CPUCLKDIV 0x000000B8 +#define PRCM_O_CPUCLKDIV 0x000000B8 // I2S Clock Control -#define PRCM_O_I2SBCLKSEL 0x000000C8 +#define PRCM_O_I2SBCLKSEL 0x000000C8 // GPT Scalar -#define PRCM_O_GPTCLKDIV 0x000000CC +#define PRCM_O_GPTCLKDIV 0x000000CC // I2S Clock Control -#define PRCM_O_I2SCLKCTL 0x000000D0 +#define PRCM_O_I2SCLKCTL 0x000000D0 // MCLK Division Ratio -#define PRCM_O_I2SMCLKDIV 0x000000D4 +#define PRCM_O_I2SMCLKDIV 0x000000D4 // BCLK Division Ratio -#define PRCM_O_I2SBCLKDIV 0x000000D8 +#define PRCM_O_I2SBCLKDIV 0x000000D8 // WCLK Division Ratio -#define PRCM_O_I2SWCLKDIV 0x000000DC +#define PRCM_O_I2SWCLKDIV 0x000000DC // SW Initiated Resets -#define PRCM_O_SWRESET 0x0000010C +#define PRCM_O_SWRESET 0x0000010C // WARM Reset Control And Status -#define PRCM_O_WARMRESET 0x00000110 +#define PRCM_O_WARMRESET 0x00000110 // Power Domain Control -#define PRCM_O_PDCTL0 0x0000012C +#define PRCM_O_PDCTL0 0x0000012C // RFC Power Domain Control -#define PRCM_O_PDCTL0RFC 0x00000130 +#define PRCM_O_PDCTL0RFC 0x00000130 // SERIAL Power Domain Control -#define PRCM_O_PDCTL0SERIAL 0x00000134 +#define PRCM_O_PDCTL0SERIAL 0x00000134 // PERIPH Power Domain Control -#define PRCM_O_PDCTL0PERIPH 0x00000138 +#define PRCM_O_PDCTL0PERIPH 0x00000138 // Power Domain Status -#define PRCM_O_PDSTAT0 0x00000140 +#define PRCM_O_PDSTAT0 0x00000140 // RFC Power Domain Status -#define PRCM_O_PDSTAT0RFC 0x00000144 +#define PRCM_O_PDSTAT0RFC 0x00000144 // SERIAL Power Domain Status -#define PRCM_O_PDSTAT0SERIAL 0x00000148 +#define PRCM_O_PDSTAT0SERIAL 0x00000148 // PERIPH Power Domain Status -#define PRCM_O_PDSTAT0PERIPH 0x0000014C +#define PRCM_O_PDSTAT0PERIPH 0x0000014C // Power Domain Control -#define PRCM_O_PDCTL1 0x0000017C +#define PRCM_O_PDCTL1 0x0000017C // CPU Power Domain Direct Control -#define PRCM_O_PDCTL1CPU 0x00000184 +#define PRCM_O_PDCTL1CPU 0x00000184 // RFC Power Domain Direct Control -#define PRCM_O_PDCTL1RFC 0x00000188 +#define PRCM_O_PDCTL1RFC 0x00000188 // VIMS Mode Direct Control -#define PRCM_O_PDCTL1VIMS 0x0000018C +#define PRCM_O_PDCTL1VIMS 0x0000018C // Power Manager Status -#define PRCM_O_PDSTAT1 0x00000194 +#define PRCM_O_PDSTAT1 0x00000194 // BUS Power Domain Direct Read Status -#define PRCM_O_PDSTAT1BUS 0x00000198 +#define PRCM_O_PDSTAT1BUS 0x00000198 // RFC Power Domain Direct Read Status -#define PRCM_O_PDSTAT1RFC 0x0000019C +#define PRCM_O_PDSTAT1RFC 0x0000019C // CPU Power Domain Direct Read Status -#define PRCM_O_PDSTAT1CPU 0x000001A0 +#define PRCM_O_PDSTAT1CPU 0x000001A0 // VIMS Mode Direct Read Status -#define PRCM_O_PDSTAT1VIMS 0x000001A4 +#define PRCM_O_PDSTAT1VIMS 0x000001A4 // Control To RFC -#define PRCM_O_RFCBITS 0x000001CC +#define PRCM_O_RFCBITS 0x000001CC // Selected RFC Mode -#define PRCM_O_RFCMODESEL 0x000001D0 +#define PRCM_O_RFCMODESEL 0x000001D0 // Allowed RFC Modes -#define PRCM_O_RFCMODEHWOPT 0x000001D4 +#define PRCM_O_RFCMODEHWOPT 0x000001D4 // Power Profiler Register -#define PRCM_O_PWRPROFSTAT 0x000001E0 +#define PRCM_O_PWRPROFSTAT 0x000001E0 // Memory Retention Control -#define PRCM_O_RAMRETEN 0x00000224 +#define PRCM_O_RAMRETEN 0x00000224 //***************************************************************************** // @@ -235,13 +235,13 @@ // DIV8 Divide by 8 // DIV2 Divide by 2 // DIV1 Divide by 1 -#define PRCM_INFRCLKDIVR_RATIO_W 2 -#define PRCM_INFRCLKDIVR_RATIO_M 0x00000003 -#define PRCM_INFRCLKDIVR_RATIO_S 0 -#define PRCM_INFRCLKDIVR_RATIO_DIV32 0x00000003 -#define PRCM_INFRCLKDIVR_RATIO_DIV8 0x00000002 -#define PRCM_INFRCLKDIVR_RATIO_DIV2 0x00000001 -#define PRCM_INFRCLKDIVR_RATIO_DIV1 0x00000000 +#define PRCM_INFRCLKDIVR_RATIO_W 2 +#define PRCM_INFRCLKDIVR_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVR_RATIO_S 0 +#define PRCM_INFRCLKDIVR_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVR_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVR_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVR_RATIO_DIV1 0x00000000 //***************************************************************************** // @@ -258,13 +258,13 @@ // DIV8 Divide by 8 // DIV2 Divide by 2 // DIV1 Divide by 1 -#define PRCM_INFRCLKDIVS_RATIO_W 2 -#define PRCM_INFRCLKDIVS_RATIO_M 0x00000003 -#define PRCM_INFRCLKDIVS_RATIO_S 0 -#define PRCM_INFRCLKDIVS_RATIO_DIV32 0x00000003 -#define PRCM_INFRCLKDIVS_RATIO_DIV8 0x00000002 -#define PRCM_INFRCLKDIVS_RATIO_DIV2 0x00000001 -#define PRCM_INFRCLKDIVS_RATIO_DIV1 0x00000000 +#define PRCM_INFRCLKDIVS_RATIO_W 2 +#define PRCM_INFRCLKDIVS_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVS_RATIO_S 0 +#define PRCM_INFRCLKDIVS_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVS_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVS_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVS_RATIO_DIV1 0x00000000 //***************************************************************************** // @@ -281,13 +281,13 @@ // DIV8 Divide by 8 // DIV2 Divide by 2 // DIV1 Divide by 1 -#define PRCM_INFRCLKDIVDS_RATIO_W 2 -#define PRCM_INFRCLKDIVDS_RATIO_M 0x00000003 -#define PRCM_INFRCLKDIVDS_RATIO_S 0 -#define PRCM_INFRCLKDIVDS_RATIO_DIV32 0x00000003 -#define PRCM_INFRCLKDIVDS_RATIO_DIV8 0x00000002 -#define PRCM_INFRCLKDIVDS_RATIO_DIV2 0x00000001 -#define PRCM_INFRCLKDIVDS_RATIO_DIV1 0x00000000 +#define PRCM_INFRCLKDIVDS_RATIO_W 2 +#define PRCM_INFRCLKDIVDS_RATIO_M 0x00000003 +#define PRCM_INFRCLKDIVDS_RATIO_S 0 +#define PRCM_INFRCLKDIVDS_RATIO_DIV32 0x00000003 +#define PRCM_INFRCLKDIVDS_RATIO_DIV8 0x00000002 +#define PRCM_INFRCLKDIVDS_RATIO_DIV2 0x00000001 +#define PRCM_INFRCLKDIVDS_RATIO_DIV1 0x00000000 //***************************************************************************** // @@ -311,10 +311,10 @@ // CLKLOADCTL.LOAD) // 5. RFC do no request access to BUS // 6. System CPU in deepsleep -#define PRCM_VDCTL_MCU_VD 0x00000004 -#define PRCM_VDCTL_MCU_VD_BITN 2 -#define PRCM_VDCTL_MCU_VD_M 0x00000004 -#define PRCM_VDCTL_MCU_VD_S 2 +#define PRCM_VDCTL_MCU_VD 0x00000004 +#define PRCM_VDCTL_MCU_VD_BITN 2 +#define PRCM_VDCTL_MCU_VD_M 0x00000004 +#define PRCM_VDCTL_MCU_VD_S 2 // Field: [0] ULDO // @@ -332,10 +332,10 @@ // CLKLOADCTL.LOAD) // 5. RFC do no request access to BUS // 6. System CPU in deepsleep -#define PRCM_VDCTL_ULDO 0x00000001 -#define PRCM_VDCTL_ULDO_BITN 0 -#define PRCM_VDCTL_ULDO_M 0x00000001 -#define PRCM_VDCTL_ULDO_S 0 +#define PRCM_VDCTL_ULDO 0x00000001 +#define PRCM_VDCTL_ULDO_BITN 0 +#define PRCM_VDCTL_ULDO_M 0x00000001 +#define PRCM_VDCTL_ULDO_S 0 //***************************************************************************** // @@ -352,10 +352,10 @@ // // 0 : One or more registers have been write accessed after last LOAD // 1 : No registers are write accessed after last LOAD -#define PRCM_CLKLOADCTL_LOAD_DONE 0x00000002 -#define PRCM_CLKLOADCTL_LOAD_DONE_BITN 1 -#define PRCM_CLKLOADCTL_LOAD_DONE_M 0x00000002 -#define PRCM_CLKLOADCTL_LOAD_DONE_S 1 +#define PRCM_CLKLOADCTL_LOAD_DONE 0x00000002 +#define PRCM_CLKLOADCTL_LOAD_DONE_BITN 1 +#define PRCM_CLKLOADCTL_LOAD_DONE_M 0x00000002 +#define PRCM_CLKLOADCTL_LOAD_DONE_S 1 // Field: [0] LOAD // @@ -397,10 +397,10 @@ // - I2SMCLKDIV // - I2SBCLKDIV // - I2SWCLKDIV -#define PRCM_CLKLOADCTL_LOAD 0x00000001 -#define PRCM_CLKLOADCTL_LOAD_BITN 0 -#define PRCM_CLKLOADCTL_LOAD_M 0x00000001 -#define PRCM_CLKLOADCTL_LOAD_S 0 +#define PRCM_CLKLOADCTL_LOAD 0x00000001 +#define PRCM_CLKLOADCTL_LOAD_BITN 0 +#define PRCM_CLKLOADCTL_LOAD_M 0x00000001 +#define PRCM_CLKLOADCTL_LOAD_S 0 //***************************************************************************** // @@ -414,10 +414,10 @@ // 1: Enable clock if RFC power domain is on // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_RFCCLKG_CLK_EN 0x00000001 -#define PRCM_RFCCLKG_CLK_EN_BITN 0 -#define PRCM_RFCCLKG_CLK_EN_M 0x00000001 -#define PRCM_RFCCLKG_CLK_EN_S 0 +#define PRCM_RFCCLKG_CLK_EN 0x00000001 +#define PRCM_RFCCLKG_CLK_EN_BITN 0 +#define PRCM_RFCCLKG_CLK_EN_M 0x00000001 +#define PRCM_RFCCLKG_CLK_EN_S 0 //***************************************************************************** // @@ -432,9 +432,9 @@ // 11: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_VIMSCLKG_CLK_EN_W 2 -#define PRCM_VIMSCLKG_CLK_EN_M 0x00000003 -#define PRCM_VIMSCLKG_CLK_EN_S 0 +#define PRCM_VIMSCLKG_CLK_EN_W 2 +#define PRCM_VIMSCLKG_CLK_EN_M 0x00000003 +#define PRCM_VIMSCLKG_CLK_EN_S 0 //***************************************************************************** // @@ -448,10 +448,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_DMA_CLK_EN 0x00000100 -#define PRCM_SECDMACLKGR_DMA_CLK_EN_BITN 8 -#define PRCM_SECDMACLKGR_DMA_CLK_EN_M 0x00000100 -#define PRCM_SECDMACLKGR_DMA_CLK_EN_S 8 +#define PRCM_SECDMACLKGR_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGR_DMA_CLK_EN_S 8 // Field: [1] TRNG_CLK_EN // @@ -460,10 +460,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_TRNG_CLK_EN 0x00000002 -#define PRCM_SECDMACLKGR_TRNG_CLK_EN_BITN 1 -#define PRCM_SECDMACLKGR_TRNG_CLK_EN_M 0x00000002 -#define PRCM_SECDMACLKGR_TRNG_CLK_EN_S 1 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGR_TRNG_CLK_EN_S 1 // Field: [0] CRYPTO_CLK_EN // @@ -472,10 +472,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN 0x00000001 -#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_BITN 0 -#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_M 0x00000001 -#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S 0 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S 0 //***************************************************************************** // @@ -489,10 +489,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGS_DMA_CLK_EN 0x00000100 -#define PRCM_SECDMACLKGS_DMA_CLK_EN_BITN 8 -#define PRCM_SECDMACLKGS_DMA_CLK_EN_M 0x00000100 -#define PRCM_SECDMACLKGS_DMA_CLK_EN_S 8 +#define PRCM_SECDMACLKGS_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGS_DMA_CLK_EN_S 8 // Field: [1] TRNG_CLK_EN // @@ -501,10 +501,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGS_TRNG_CLK_EN 0x00000002 -#define PRCM_SECDMACLKGS_TRNG_CLK_EN_BITN 1 -#define PRCM_SECDMACLKGS_TRNG_CLK_EN_M 0x00000002 -#define PRCM_SECDMACLKGS_TRNG_CLK_EN_S 1 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGS_TRNG_CLK_EN_S 1 // Field: [0] CRYPTO_CLK_EN // @@ -513,10 +513,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN 0x00000001 -#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_BITN 0 -#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_M 0x00000001 -#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_S 0 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_S 0 //***************************************************************************** // @@ -530,10 +530,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGDS_DMA_CLK_EN 0x00000100 -#define PRCM_SECDMACLKGDS_DMA_CLK_EN_BITN 8 -#define PRCM_SECDMACLKGDS_DMA_CLK_EN_M 0x00000100 -#define PRCM_SECDMACLKGDS_DMA_CLK_EN_S 8 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN 0x00000100 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_BITN 8 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_M 0x00000100 +#define PRCM_SECDMACLKGDS_DMA_CLK_EN_S 8 // Field: [1] TRNG_CLK_EN // @@ -542,10 +542,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGDS_TRNG_CLK_EN 0x00000002 -#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_BITN 1 -#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_M 0x00000002 -#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_S 1 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN 0x00000002 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_BITN 1 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_M 0x00000002 +#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_S 1 // Field: [0] CRYPTO_CLK_EN // @@ -554,10 +554,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN 0x00000001 -#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_BITN 0 -#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_M 0x00000001 -#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_S 0 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN 0x00000001 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_BITN 0 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_M 0x00000001 +#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_S 0 //***************************************************************************** // @@ -571,10 +571,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_GPIOCLKGR_CLK_EN 0x00000001 -#define PRCM_GPIOCLKGR_CLK_EN_BITN 0 -#define PRCM_GPIOCLKGR_CLK_EN_M 0x00000001 -#define PRCM_GPIOCLKGR_CLK_EN_S 0 +#define PRCM_GPIOCLKGR_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGR_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGR_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGR_CLK_EN_S 0 //***************************************************************************** // @@ -588,10 +588,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_GPIOCLKGS_CLK_EN 0x00000001 -#define PRCM_GPIOCLKGS_CLK_EN_BITN 0 -#define PRCM_GPIOCLKGS_CLK_EN_M 0x00000001 -#define PRCM_GPIOCLKGS_CLK_EN_S 0 +#define PRCM_GPIOCLKGS_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGS_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGS_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGS_CLK_EN_S 0 //***************************************************************************** // @@ -605,10 +605,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_GPIOCLKGDS_CLK_EN 0x00000001 -#define PRCM_GPIOCLKGDS_CLK_EN_BITN 0 -#define PRCM_GPIOCLKGDS_CLK_EN_M 0x00000001 -#define PRCM_GPIOCLKGDS_CLK_EN_S 0 +#define PRCM_GPIOCLKGDS_CLK_EN 0x00000001 +#define PRCM_GPIOCLKGDS_CLK_EN_BITN 0 +#define PRCM_GPIOCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_GPIOCLKGDS_CLK_EN_S 0 //***************************************************************************** // @@ -629,13 +629,13 @@ // GPT2 Enable clock for GPT2 // GPT1 Enable clock for GPT1 // GPT0 Enable clock for GPT0 -#define PRCM_GPTCLKGR_CLK_EN_W 4 -#define PRCM_GPTCLKGR_CLK_EN_M 0x0000000F -#define PRCM_GPTCLKGR_CLK_EN_S 0 -#define PRCM_GPTCLKGR_CLK_EN_GPT3 0x00000008 -#define PRCM_GPTCLKGR_CLK_EN_GPT2 0x00000004 -#define PRCM_GPTCLKGR_CLK_EN_GPT1 0x00000002 -#define PRCM_GPTCLKGR_CLK_EN_GPT0 0x00000001 +#define PRCM_GPTCLKGR_CLK_EN_W 4 +#define PRCM_GPTCLKGR_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGR_CLK_EN_S 0 +#define PRCM_GPTCLKGR_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGR_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGR_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGR_CLK_EN_GPT0 0x00000001 //***************************************************************************** // @@ -656,13 +656,13 @@ // GPT2 Enable clock for GPT2 // GPT1 Enable clock for GPT1 // GPT0 Enable clock for GPT0 -#define PRCM_GPTCLKGS_CLK_EN_W 4 -#define PRCM_GPTCLKGS_CLK_EN_M 0x0000000F -#define PRCM_GPTCLKGS_CLK_EN_S 0 -#define PRCM_GPTCLKGS_CLK_EN_GPT3 0x00000008 -#define PRCM_GPTCLKGS_CLK_EN_GPT2 0x00000004 -#define PRCM_GPTCLKGS_CLK_EN_GPT1 0x00000002 -#define PRCM_GPTCLKGS_CLK_EN_GPT0 0x00000001 +#define PRCM_GPTCLKGS_CLK_EN_W 4 +#define PRCM_GPTCLKGS_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGS_CLK_EN_S 0 +#define PRCM_GPTCLKGS_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGS_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGS_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGS_CLK_EN_GPT0 0x00000001 //***************************************************************************** // @@ -683,13 +683,13 @@ // GPT2 Enable clock for GPT2 // GPT1 Enable clock for GPT1 // GPT0 Enable clock for GPT0 -#define PRCM_GPTCLKGDS_CLK_EN_W 4 -#define PRCM_GPTCLKGDS_CLK_EN_M 0x0000000F -#define PRCM_GPTCLKGDS_CLK_EN_S 0 -#define PRCM_GPTCLKGDS_CLK_EN_GPT3 0x00000008 -#define PRCM_GPTCLKGDS_CLK_EN_GPT2 0x00000004 -#define PRCM_GPTCLKGDS_CLK_EN_GPT1 0x00000002 -#define PRCM_GPTCLKGDS_CLK_EN_GPT0 0x00000001 +#define PRCM_GPTCLKGDS_CLK_EN_W 4 +#define PRCM_GPTCLKGDS_CLK_EN_M 0x0000000F +#define PRCM_GPTCLKGDS_CLK_EN_S 0 +#define PRCM_GPTCLKGDS_CLK_EN_GPT3 0x00000008 +#define PRCM_GPTCLKGDS_CLK_EN_GPT2 0x00000004 +#define PRCM_GPTCLKGDS_CLK_EN_GPT1 0x00000002 +#define PRCM_GPTCLKGDS_CLK_EN_GPT0 0x00000001 //***************************************************************************** // @@ -703,10 +703,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2CCLKGR_CLK_EN 0x00000001 -#define PRCM_I2CCLKGR_CLK_EN_BITN 0 -#define PRCM_I2CCLKGR_CLK_EN_M 0x00000001 -#define PRCM_I2CCLKGR_CLK_EN_S 0 +#define PRCM_I2CCLKGR_CLK_EN 0x00000001 +#define PRCM_I2CCLKGR_CLK_EN_BITN 0 +#define PRCM_I2CCLKGR_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGR_CLK_EN_S 0 //***************************************************************************** // @@ -720,10 +720,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2CCLKGS_CLK_EN 0x00000001 -#define PRCM_I2CCLKGS_CLK_EN_BITN 0 -#define PRCM_I2CCLKGS_CLK_EN_M 0x00000001 -#define PRCM_I2CCLKGS_CLK_EN_S 0 +#define PRCM_I2CCLKGS_CLK_EN 0x00000001 +#define PRCM_I2CCLKGS_CLK_EN_BITN 0 +#define PRCM_I2CCLKGS_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGS_CLK_EN_S 0 //***************************************************************************** // @@ -737,10 +737,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2CCLKGDS_CLK_EN 0x00000001 -#define PRCM_I2CCLKGDS_CLK_EN_BITN 0 -#define PRCM_I2CCLKGDS_CLK_EN_M 0x00000001 -#define PRCM_I2CCLKGDS_CLK_EN_S 0 +#define PRCM_I2CCLKGDS_CLK_EN 0x00000001 +#define PRCM_I2CCLKGDS_CLK_EN_BITN 0 +#define PRCM_I2CCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_I2CCLKGDS_CLK_EN_S 0 //***************************************************************************** // @@ -754,10 +754,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_UARTCLKGR_CLK_EN 0x00000001 -#define PRCM_UARTCLKGR_CLK_EN_BITN 0 -#define PRCM_UARTCLKGR_CLK_EN_M 0x00000001 -#define PRCM_UARTCLKGR_CLK_EN_S 0 +#define PRCM_UARTCLKGR_CLK_EN 0x00000001 +#define PRCM_UARTCLKGR_CLK_EN_BITN 0 +#define PRCM_UARTCLKGR_CLK_EN_M 0x00000001 +#define PRCM_UARTCLKGR_CLK_EN_S 0 //***************************************************************************** // @@ -771,10 +771,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_UARTCLKGS_CLK_EN 0x00000001 -#define PRCM_UARTCLKGS_CLK_EN_BITN 0 -#define PRCM_UARTCLKGS_CLK_EN_M 0x00000001 -#define PRCM_UARTCLKGS_CLK_EN_S 0 +#define PRCM_UARTCLKGS_CLK_EN 0x00000001 +#define PRCM_UARTCLKGS_CLK_EN_BITN 0 +#define PRCM_UARTCLKGS_CLK_EN_M 0x00000001 +#define PRCM_UARTCLKGS_CLK_EN_S 0 //***************************************************************************** // @@ -788,10 +788,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_UARTCLKGDS_CLK_EN 0x00000001 -#define PRCM_UARTCLKGDS_CLK_EN_BITN 0 -#define PRCM_UARTCLKGDS_CLK_EN_M 0x00000001 -#define PRCM_UARTCLKGDS_CLK_EN_S 0 +#define PRCM_UARTCLKGDS_CLK_EN 0x00000001 +#define PRCM_UARTCLKGDS_CLK_EN_BITN 0 +#define PRCM_UARTCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_UARTCLKGDS_CLK_EN_S 0 //***************************************************************************** // @@ -808,11 +808,11 @@ // ENUMs: // SSI1 Enable clock for SSI1 // SSI0 Enable clock for SSI0 -#define PRCM_SSICLKGR_CLK_EN_W 2 -#define PRCM_SSICLKGR_CLK_EN_M 0x00000003 -#define PRCM_SSICLKGR_CLK_EN_S 0 -#define PRCM_SSICLKGR_CLK_EN_SSI1 0x00000002 -#define PRCM_SSICLKGR_CLK_EN_SSI0 0x00000001 +#define PRCM_SSICLKGR_CLK_EN_W 2 +#define PRCM_SSICLKGR_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGR_CLK_EN_S 0 +#define PRCM_SSICLKGR_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGR_CLK_EN_SSI0 0x00000001 //***************************************************************************** // @@ -829,11 +829,11 @@ // ENUMs: // SSI1 Enable clock for SSI1 // SSI0 Enable clock for SSI0 -#define PRCM_SSICLKGS_CLK_EN_W 2 -#define PRCM_SSICLKGS_CLK_EN_M 0x00000003 -#define PRCM_SSICLKGS_CLK_EN_S 0 -#define PRCM_SSICLKGS_CLK_EN_SSI1 0x00000002 -#define PRCM_SSICLKGS_CLK_EN_SSI0 0x00000001 +#define PRCM_SSICLKGS_CLK_EN_W 2 +#define PRCM_SSICLKGS_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGS_CLK_EN_S 0 +#define PRCM_SSICLKGS_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGS_CLK_EN_SSI0 0x00000001 //***************************************************************************** // @@ -850,11 +850,11 @@ // ENUMs: // SSI1 Enable clock for SSI1 // SSI0 Enable clock for SSI0 -#define PRCM_SSICLKGDS_CLK_EN_W 2 -#define PRCM_SSICLKGDS_CLK_EN_M 0x00000003 -#define PRCM_SSICLKGDS_CLK_EN_S 0 -#define PRCM_SSICLKGDS_CLK_EN_SSI1 0x00000002 -#define PRCM_SSICLKGDS_CLK_EN_SSI0 0x00000001 +#define PRCM_SSICLKGDS_CLK_EN_W 2 +#define PRCM_SSICLKGDS_CLK_EN_M 0x00000003 +#define PRCM_SSICLKGDS_CLK_EN_S 0 +#define PRCM_SSICLKGDS_CLK_EN_SSI1 0x00000002 +#define PRCM_SSICLKGDS_CLK_EN_SSI0 0x00000001 //***************************************************************************** // @@ -868,10 +868,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKGR_CLK_EN 0x00000001 -#define PRCM_I2SCLKGR_CLK_EN_BITN 0 -#define PRCM_I2SCLKGR_CLK_EN_M 0x00000001 -#define PRCM_I2SCLKGR_CLK_EN_S 0 +#define PRCM_I2SCLKGR_CLK_EN 0x00000001 +#define PRCM_I2SCLKGR_CLK_EN_BITN 0 +#define PRCM_I2SCLKGR_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGR_CLK_EN_S 0 //***************************************************************************** // @@ -885,10 +885,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKGS_CLK_EN 0x00000001 -#define PRCM_I2SCLKGS_CLK_EN_BITN 0 -#define PRCM_I2SCLKGS_CLK_EN_M 0x00000001 -#define PRCM_I2SCLKGS_CLK_EN_S 0 +#define PRCM_I2SCLKGS_CLK_EN 0x00000001 +#define PRCM_I2SCLKGS_CLK_EN_BITN 0 +#define PRCM_I2SCLKGS_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGS_CLK_EN_S 0 //***************************************************************************** // @@ -902,10 +902,10 @@ // 1: Enable clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKGDS_CLK_EN 0x00000001 -#define PRCM_I2SCLKGDS_CLK_EN_BITN 0 -#define PRCM_I2SCLKGDS_CLK_EN_M 0x00000001 -#define PRCM_I2SCLKGDS_CLK_EN_S 0 +#define PRCM_I2SCLKGDS_CLK_EN 0x00000001 +#define PRCM_I2SCLKGDS_CLK_EN_BITN 0 +#define PRCM_I2SCLKGDS_CLK_EN_M 0x00000001 +#define PRCM_I2SCLKGDS_CLK_EN_S 0 //***************************************************************************** // @@ -918,12 +918,12 @@ // ENUMs: // DIV2 Internal. Only to be used through TI provided API. // DIV1 Internal. Only to be used through TI provided API. -#define PRCM_CPUCLKDIV_RATIO 0x00000001 -#define PRCM_CPUCLKDIV_RATIO_BITN 0 -#define PRCM_CPUCLKDIV_RATIO_M 0x00000001 -#define PRCM_CPUCLKDIV_RATIO_S 0 -#define PRCM_CPUCLKDIV_RATIO_DIV2 0x00000001 -#define PRCM_CPUCLKDIV_RATIO_DIV1 0x00000000 +#define PRCM_CPUCLKDIV_RATIO 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_BITN 0 +#define PRCM_CPUCLKDIV_RATIO_M 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_S 0 +#define PRCM_CPUCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_CPUCLKDIV_RATIO_DIV1 0x00000000 //***************************************************************************** // @@ -938,10 +938,10 @@ // 1: Use internally generated clock // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SBCLKSEL_SRC 0x00000001 -#define PRCM_I2SBCLKSEL_SRC_BITN 0 -#define PRCM_I2SBCLKSEL_SRC_M 0x00000001 -#define PRCM_I2SBCLKSEL_SRC_S 0 +#define PRCM_I2SBCLKSEL_SRC 0x00000001 +#define PRCM_I2SBCLKSEL_SRC_BITN 0 +#define PRCM_I2SBCLKSEL_SRC_M 0x00000001 +#define PRCM_I2SBCLKSEL_SRC_S 0 //***************************************************************************** // @@ -965,18 +965,18 @@ // DIV4 Divide by 4 // DIV2 Divide by 2 // DIV1 Divide by 1 -#define PRCM_GPTCLKDIV_RATIO_W 4 -#define PRCM_GPTCLKDIV_RATIO_M 0x0000000F -#define PRCM_GPTCLKDIV_RATIO_S 0 -#define PRCM_GPTCLKDIV_RATIO_DIV256 0x00000008 -#define PRCM_GPTCLKDIV_RATIO_DIV128 0x00000007 -#define PRCM_GPTCLKDIV_RATIO_DIV64 0x00000006 -#define PRCM_GPTCLKDIV_RATIO_DIV32 0x00000005 -#define PRCM_GPTCLKDIV_RATIO_DIV16 0x00000004 -#define PRCM_GPTCLKDIV_RATIO_DIV8 0x00000003 -#define PRCM_GPTCLKDIV_RATIO_DIV4 0x00000002 -#define PRCM_GPTCLKDIV_RATIO_DIV2 0x00000001 -#define PRCM_GPTCLKDIV_RATIO_DIV1 0x00000000 +#define PRCM_GPTCLKDIV_RATIO_W 4 +#define PRCM_GPTCLKDIV_RATIO_M 0x0000000F +#define PRCM_GPTCLKDIV_RATIO_S 0 +#define PRCM_GPTCLKDIV_RATIO_DIV256 0x00000008 +#define PRCM_GPTCLKDIV_RATIO_DIV128 0x00000007 +#define PRCM_GPTCLKDIV_RATIO_DIV64 0x00000006 +#define PRCM_GPTCLKDIV_RATIO_DIV32 0x00000005 +#define PRCM_GPTCLKDIV_RATIO_DIV16 0x00000004 +#define PRCM_GPTCLKDIV_RATIO_DIV8 0x00000003 +#define PRCM_GPTCLKDIV_RATIO_DIV4 0x00000002 +#define PRCM_GPTCLKDIV_RATIO_DIV2 0x00000001 +#define PRCM_GPTCLKDIV_RATIO_DIV1 0x00000000 //***************************************************************************** // @@ -994,10 +994,10 @@ // negative edge. // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE 0x00000008 -#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_BITN 3 -#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M 0x00000008 -#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S 3 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE 0x00000008 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_BITN 3 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M 0x00000008 +#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S 3 // Field: [2:1] WCLK_PHASE // @@ -1010,9 +1010,9 @@ // 3: Reserved/Undefined // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKCTL_WCLK_PHASE_W 2 -#define PRCM_I2SCLKCTL_WCLK_PHASE_M 0x00000006 -#define PRCM_I2SCLKCTL_WCLK_PHASE_S 1 +#define PRCM_I2SCLKCTL_WCLK_PHASE_W 2 +#define PRCM_I2SCLKCTL_WCLK_PHASE_M 0x00000006 +#define PRCM_I2SCLKCTL_WCLK_PHASE_S 1 // Field: [0] EN // @@ -1021,10 +1021,10 @@ // 1: Enables the generation of MCLK, BCLK and WCLK // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKCTL_EN 0x00000001 -#define PRCM_I2SCLKCTL_EN_BITN 0 -#define PRCM_I2SCLKCTL_EN_M 0x00000001 -#define PRCM_I2SCLKCTL_EN_S 0 +#define PRCM_I2SCLKCTL_EN 0x00000001 +#define PRCM_I2SCLKCTL_EN_BITN 0 +#define PRCM_I2SCLKCTL_EN_M 0x00000001 +#define PRCM_I2SCLKCTL_EN_S 0 //***************************************************************************** // @@ -1045,9 +1045,9 @@ // the high phase. // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SMCLKDIV_MDIV_W 10 -#define PRCM_I2SMCLKDIV_MDIV_M 0x000003FF -#define PRCM_I2SMCLKDIV_MDIV_S 0 +#define PRCM_I2SMCLKDIV_MDIV_W 10 +#define PRCM_I2SMCLKDIV_MDIV_M 0x000003FF +#define PRCM_I2SMCLKDIV_MDIV_S 0 //***************************************************************************** // @@ -1070,9 +1070,9 @@ // clock is one MCUCLK period longer than the low phase. // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SBCLKDIV_BDIV_W 10 -#define PRCM_I2SBCLKDIV_BDIV_M 0x000003FF -#define PRCM_I2SBCLKDIV_BDIV_S 0 +#define PRCM_I2SBCLKDIV_BDIV_W 10 +#define PRCM_I2SBCLKDIV_BDIV_M 0x000003FF +#define PRCM_I2SBCLKDIV_BDIV_S 0 //***************************************************************************** // @@ -1102,9 +1102,9 @@ // WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz] // // For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SWCLKDIV_WDIV_W 16 -#define PRCM_I2SWCLKDIV_WDIV_M 0x0000FFFF -#define PRCM_I2SWCLKDIV_WDIV_S 0 +#define PRCM_I2SWCLKDIV_WDIV_W 16 +#define PRCM_I2SWCLKDIV_WDIV_M 0x0000FFFF +#define PRCM_I2SWCLKDIV_WDIV_S 0 //***************************************************************************** // @@ -1114,10 +1114,10 @@ // Field: [2] MCU // // Internal. Only to be used through TI provided API. -#define PRCM_SWRESET_MCU 0x00000004 -#define PRCM_SWRESET_MCU_BITN 2 -#define PRCM_SWRESET_MCU_M 0x00000004 -#define PRCM_SWRESET_MCU_S 2 +#define PRCM_SWRESET_MCU 0x00000004 +#define PRCM_SWRESET_MCU_BITN 2 +#define PRCM_SWRESET_MCU_M 0x00000004 +#define PRCM_SWRESET_MCU_S 2 //***************************************************************************** // @@ -1143,10 +1143,10 @@ // reset resulting in a full power up sequence. WARMRESET in this register is // set in the scenario that WR_TO_PINRESET=1 and one of the above listed // sources is triggered. -#define PRCM_WARMRESET_WR_TO_PINRESET 0x00000004 -#define PRCM_WARMRESET_WR_TO_PINRESET_BITN 2 -#define PRCM_WARMRESET_WR_TO_PINRESET_M 0x00000004 -#define PRCM_WARMRESET_WR_TO_PINRESET_S 2 +#define PRCM_WARMRESET_WR_TO_PINRESET 0x00000004 +#define PRCM_WARMRESET_WR_TO_PINRESET_BITN 2 +#define PRCM_WARMRESET_WR_TO_PINRESET_M 0x00000004 +#define PRCM_WARMRESET_WR_TO_PINRESET_S 2 // Field: [1] LOCKUP_STAT // @@ -1156,10 +1156,10 @@ // register. // // A read of this register clears both WDT_STAT and LOCKUP_STAT. -#define PRCM_WARMRESET_LOCKUP_STAT 0x00000002 -#define PRCM_WARMRESET_LOCKUP_STAT_BITN 1 -#define PRCM_WARMRESET_LOCKUP_STAT_M 0x00000002 -#define PRCM_WARMRESET_LOCKUP_STAT_S 1 +#define PRCM_WARMRESET_LOCKUP_STAT 0x00000002 +#define PRCM_WARMRESET_LOCKUP_STAT_BITN 1 +#define PRCM_WARMRESET_LOCKUP_STAT_M 0x00000002 +#define PRCM_WARMRESET_LOCKUP_STAT_S 1 // Field: [0] WDT_STAT // @@ -1168,10 +1168,10 @@ // 1: A WDT event has occured since last SW clear of the register. // // A read of this register clears both WDT_STAT and LOCKUP_STAT. -#define PRCM_WARMRESET_WDT_STAT 0x00000001 -#define PRCM_WARMRESET_WDT_STAT_BITN 0 -#define PRCM_WARMRESET_WDT_STAT_M 0x00000001 -#define PRCM_WARMRESET_WDT_STAT_S 0 +#define PRCM_WARMRESET_WDT_STAT 0x00000001 +#define PRCM_WARMRESET_WDT_STAT_BITN 0 +#define PRCM_WARMRESET_WDT_STAT_M 0x00000001 +#define PRCM_WARMRESET_WDT_STAT_S 0 //***************************************************************************** // @@ -1184,10 +1184,10 @@ // // 0: PERIPH power domain is powered down // 1: PERIPH power domain is powered up -#define PRCM_PDCTL0_PERIPH_ON 0x00000004 -#define PRCM_PDCTL0_PERIPH_ON_BITN 2 -#define PRCM_PDCTL0_PERIPH_ON_M 0x00000004 -#define PRCM_PDCTL0_PERIPH_ON_S 2 +#define PRCM_PDCTL0_PERIPH_ON 0x00000004 +#define PRCM_PDCTL0_PERIPH_ON_BITN 2 +#define PRCM_PDCTL0_PERIPH_ON_M 0x00000004 +#define PRCM_PDCTL0_PERIPH_ON_S 2 // Field: [1] SERIAL_ON // @@ -1195,20 +1195,20 @@ // // 0: SERIAL power domain is powered down // 1: SERIAL power domain is powered up -#define PRCM_PDCTL0_SERIAL_ON 0x00000002 -#define PRCM_PDCTL0_SERIAL_ON_BITN 1 -#define PRCM_PDCTL0_SERIAL_ON_M 0x00000002 -#define PRCM_PDCTL0_SERIAL_ON_S 1 +#define PRCM_PDCTL0_SERIAL_ON 0x00000002 +#define PRCM_PDCTL0_SERIAL_ON_BITN 1 +#define PRCM_PDCTL0_SERIAL_ON_M 0x00000002 +#define PRCM_PDCTL0_SERIAL_ON_S 1 // Field: [0] RFC_ON // // // 0: RFC power domain powered off if also PDCTL1.RFC_ON = 0 // 1: RFC power domain powered on -#define PRCM_PDCTL0_RFC_ON 0x00000001 -#define PRCM_PDCTL0_RFC_ON_BITN 0 -#define PRCM_PDCTL0_RFC_ON_M 0x00000001 -#define PRCM_PDCTL0_RFC_ON_S 0 +#define PRCM_PDCTL0_RFC_ON 0x00000001 +#define PRCM_PDCTL0_RFC_ON_BITN 0 +#define PRCM_PDCTL0_RFC_ON_M 0x00000001 +#define PRCM_PDCTL0_RFC_ON_S 0 //***************************************************************************** // @@ -1218,10 +1218,10 @@ // Field: [0] ON // // Alias for PDCTL0.RFC_ON -#define PRCM_PDCTL0RFC_ON 0x00000001 -#define PRCM_PDCTL0RFC_ON_BITN 0 -#define PRCM_PDCTL0RFC_ON_M 0x00000001 -#define PRCM_PDCTL0RFC_ON_S 0 +#define PRCM_PDCTL0RFC_ON 0x00000001 +#define PRCM_PDCTL0RFC_ON_BITN 0 +#define PRCM_PDCTL0RFC_ON_M 0x00000001 +#define PRCM_PDCTL0RFC_ON_S 0 //***************************************************************************** // @@ -1231,10 +1231,10 @@ // Field: [0] ON // // Alias for PDCTL0.SERIAL_ON -#define PRCM_PDCTL0SERIAL_ON 0x00000001 -#define PRCM_PDCTL0SERIAL_ON_BITN 0 -#define PRCM_PDCTL0SERIAL_ON_M 0x00000001 -#define PRCM_PDCTL0SERIAL_ON_S 0 +#define PRCM_PDCTL0SERIAL_ON 0x00000001 +#define PRCM_PDCTL0SERIAL_ON_BITN 0 +#define PRCM_PDCTL0SERIAL_ON_M 0x00000001 +#define PRCM_PDCTL0SERIAL_ON_S 0 //***************************************************************************** // @@ -1244,10 +1244,10 @@ // Field: [0] ON // // Alias for PDCTL0.PERIPH_ON -#define PRCM_PDCTL0PERIPH_ON 0x00000001 -#define PRCM_PDCTL0PERIPH_ON_BITN 0 -#define PRCM_PDCTL0PERIPH_ON_M 0x00000001 -#define PRCM_PDCTL0PERIPH_ON_S 0 +#define PRCM_PDCTL0PERIPH_ON 0x00000001 +#define PRCM_PDCTL0PERIPH_ON_BITN 0 +#define PRCM_PDCTL0PERIPH_ON_M 0x00000001 +#define PRCM_PDCTL0PERIPH_ON_S 0 //***************************************************************************** // @@ -1260,10 +1260,10 @@ // // 0: Domain may be powered down // 1: Domain powered up (guaranteed) -#define PRCM_PDSTAT0_PERIPH_ON 0x00000004 -#define PRCM_PDSTAT0_PERIPH_ON_BITN 2 -#define PRCM_PDSTAT0_PERIPH_ON_M 0x00000004 -#define PRCM_PDSTAT0_PERIPH_ON_S 2 +#define PRCM_PDSTAT0_PERIPH_ON 0x00000004 +#define PRCM_PDSTAT0_PERIPH_ON_BITN 2 +#define PRCM_PDSTAT0_PERIPH_ON_M 0x00000004 +#define PRCM_PDSTAT0_PERIPH_ON_S 2 // Field: [1] SERIAL_ON // @@ -1271,10 +1271,10 @@ // // 0: Domain may be powered down // 1: Domain powered up (guaranteed) -#define PRCM_PDSTAT0_SERIAL_ON 0x00000002 -#define PRCM_PDSTAT0_SERIAL_ON_BITN 1 -#define PRCM_PDSTAT0_SERIAL_ON_M 0x00000002 -#define PRCM_PDSTAT0_SERIAL_ON_S 1 +#define PRCM_PDSTAT0_SERIAL_ON 0x00000002 +#define PRCM_PDSTAT0_SERIAL_ON_BITN 1 +#define PRCM_PDSTAT0_SERIAL_ON_M 0x00000002 +#define PRCM_PDSTAT0_SERIAL_ON_S 1 // Field: [0] RFC_ON // @@ -1282,10 +1282,10 @@ // // 0: Domain may be powered down // 1: Domain powered up (guaranteed) -#define PRCM_PDSTAT0_RFC_ON 0x00000001 -#define PRCM_PDSTAT0_RFC_ON_BITN 0 -#define PRCM_PDSTAT0_RFC_ON_M 0x00000001 -#define PRCM_PDSTAT0_RFC_ON_S 0 +#define PRCM_PDSTAT0_RFC_ON 0x00000001 +#define PRCM_PDSTAT0_RFC_ON_BITN 0 +#define PRCM_PDSTAT0_RFC_ON_M 0x00000001 +#define PRCM_PDSTAT0_RFC_ON_S 0 //***************************************************************************** // @@ -1295,10 +1295,10 @@ // Field: [0] ON // // Alias for PDSTAT0.RFC_ON -#define PRCM_PDSTAT0RFC_ON 0x00000001 -#define PRCM_PDSTAT0RFC_ON_BITN 0 -#define PRCM_PDSTAT0RFC_ON_M 0x00000001 -#define PRCM_PDSTAT0RFC_ON_S 0 +#define PRCM_PDSTAT0RFC_ON 0x00000001 +#define PRCM_PDSTAT0RFC_ON_BITN 0 +#define PRCM_PDSTAT0RFC_ON_M 0x00000001 +#define PRCM_PDSTAT0RFC_ON_S 0 //***************************************************************************** // @@ -1308,10 +1308,10 @@ // Field: [0] ON // // Alias for PDSTAT0.SERIAL_ON -#define PRCM_PDSTAT0SERIAL_ON 0x00000001 -#define PRCM_PDSTAT0SERIAL_ON_BITN 0 -#define PRCM_PDSTAT0SERIAL_ON_M 0x00000001 -#define PRCM_PDSTAT0SERIAL_ON_S 0 +#define PRCM_PDSTAT0SERIAL_ON 0x00000001 +#define PRCM_PDSTAT0SERIAL_ON_BITN 0 +#define PRCM_PDSTAT0SERIAL_ON_M 0x00000001 +#define PRCM_PDSTAT0SERIAL_ON_S 0 //***************************************************************************** // @@ -1321,10 +1321,10 @@ // Field: [0] ON // // Alias for PDSTAT0.PERIPH_ON -#define PRCM_PDSTAT0PERIPH_ON 0x00000001 -#define PRCM_PDSTAT0PERIPH_ON_BITN 0 -#define PRCM_PDSTAT0PERIPH_ON_M 0x00000001 -#define PRCM_PDSTAT0PERIPH_ON_S 0 +#define PRCM_PDSTAT0PERIPH_ON 0x00000001 +#define PRCM_PDSTAT0PERIPH_ON_BITN 0 +#define PRCM_PDSTAT0PERIPH_ON_M 0x00000001 +#define PRCM_PDSTAT0PERIPH_ON_S 0 //***************************************************************************** // @@ -1336,10 +1336,10 @@ // // 0: VIMS power domain is only powered when CPU power domain is powered. // 1: VIMS power domain is powered whenever the BUS power domain is powered. -#define PRCM_PDCTL1_VIMS_MODE 0x00000008 -#define PRCM_PDCTL1_VIMS_MODE_BITN 3 -#define PRCM_PDCTL1_VIMS_MODE_M 0x00000008 -#define PRCM_PDCTL1_VIMS_MODE_S 3 +#define PRCM_PDCTL1_VIMS_MODE 0x00000008 +#define PRCM_PDCTL1_VIMS_MODE_BITN 3 +#define PRCM_PDCTL1_VIMS_MODE_M 0x00000008 +#define PRCM_PDCTL1_VIMS_MODE_S 3 // Field: [2] RFC_ON // @@ -1349,10 +1349,10 @@ // // Bit shall be used by RFC in autonomus mode but there is no HW restrictions // fom system CPU to access the bit. -#define PRCM_PDCTL1_RFC_ON 0x00000004 -#define PRCM_PDCTL1_RFC_ON_BITN 2 -#define PRCM_PDCTL1_RFC_ON_M 0x00000004 -#define PRCM_PDCTL1_RFC_ON_S 2 +#define PRCM_PDCTL1_RFC_ON 0x00000004 +#define PRCM_PDCTL1_RFC_ON_BITN 2 +#define PRCM_PDCTL1_RFC_ON_M 0x00000004 +#define PRCM_PDCTL1_RFC_ON_S 2 // Field: [1] CPU_ON // @@ -1362,10 +1362,10 @@ // 1: Initiates power-on of the CPU power domain. // // This bit is automatically set by a WIC power-on event. -#define PRCM_PDCTL1_CPU_ON 0x00000002 -#define PRCM_PDCTL1_CPU_ON_BITN 1 -#define PRCM_PDCTL1_CPU_ON_M 0x00000002 -#define PRCM_PDCTL1_CPU_ON_S 1 +#define PRCM_PDCTL1_CPU_ON 0x00000002 +#define PRCM_PDCTL1_CPU_ON_BITN 1 +#define PRCM_PDCTL1_CPU_ON_M 0x00000002 +#define PRCM_PDCTL1_CPU_ON_S 1 //***************************************************************************** // @@ -1375,10 +1375,10 @@ // Field: [0] ON // // This is an alias for PDCTL1.CPU_ON -#define PRCM_PDCTL1CPU_ON 0x00000001 -#define PRCM_PDCTL1CPU_ON_BITN 0 -#define PRCM_PDCTL1CPU_ON_M 0x00000001 -#define PRCM_PDCTL1CPU_ON_S 0 +#define PRCM_PDCTL1CPU_ON 0x00000001 +#define PRCM_PDCTL1CPU_ON_BITN 0 +#define PRCM_PDCTL1CPU_ON_M 0x00000001 +#define PRCM_PDCTL1CPU_ON_S 0 //***************************************************************************** // @@ -1388,10 +1388,10 @@ // Field: [0] ON // // This is an alias for PDCTL1.RFC_ON -#define PRCM_PDCTL1RFC_ON 0x00000001 -#define PRCM_PDCTL1RFC_ON_BITN 0 -#define PRCM_PDCTL1RFC_ON_M 0x00000001 -#define PRCM_PDCTL1RFC_ON_S 0 +#define PRCM_PDCTL1RFC_ON 0x00000001 +#define PRCM_PDCTL1RFC_ON_BITN 0 +#define PRCM_PDCTL1RFC_ON_M 0x00000001 +#define PRCM_PDCTL1RFC_ON_S 0 //***************************************************************************** // @@ -1401,10 +1401,10 @@ // Field: [0] ON // // This is an alias for PDCTL1.VIMS_MODE -#define PRCM_PDCTL1VIMS_ON 0x00000001 -#define PRCM_PDCTL1VIMS_ON_BITN 0 -#define PRCM_PDCTL1VIMS_ON_M 0x00000001 -#define PRCM_PDCTL1VIMS_ON_S 0 +#define PRCM_PDCTL1VIMS_ON 0x00000001 +#define PRCM_PDCTL1VIMS_ON_BITN 0 +#define PRCM_PDCTL1VIMS_ON_M 0x00000001 +#define PRCM_PDCTL1VIMS_ON_S 0 //***************************************************************************** // @@ -1416,40 +1416,40 @@ // // 0: BUS domain not accessible // 1: BUS domain is currently accessible -#define PRCM_PDSTAT1_BUS_ON 0x00000010 -#define PRCM_PDSTAT1_BUS_ON_BITN 4 -#define PRCM_PDSTAT1_BUS_ON_M 0x00000010 -#define PRCM_PDSTAT1_BUS_ON_S 4 +#define PRCM_PDSTAT1_BUS_ON 0x00000010 +#define PRCM_PDSTAT1_BUS_ON_BITN 4 +#define PRCM_PDSTAT1_BUS_ON_M 0x00000010 +#define PRCM_PDSTAT1_BUS_ON_S 4 // Field: [3] VIMS_MODE // // // 0: VIMS domain not accessible // 1: VIMS domain is currently accessible -#define PRCM_PDSTAT1_VIMS_MODE 0x00000008 -#define PRCM_PDSTAT1_VIMS_MODE_BITN 3 -#define PRCM_PDSTAT1_VIMS_MODE_M 0x00000008 -#define PRCM_PDSTAT1_VIMS_MODE_S 3 +#define PRCM_PDSTAT1_VIMS_MODE 0x00000008 +#define PRCM_PDSTAT1_VIMS_MODE_BITN 3 +#define PRCM_PDSTAT1_VIMS_MODE_M 0x00000008 +#define PRCM_PDSTAT1_VIMS_MODE_S 3 // Field: [2] RFC_ON // // // 0: RFC domain not accessible // 1: RFC domain is currently accessible -#define PRCM_PDSTAT1_RFC_ON 0x00000004 -#define PRCM_PDSTAT1_RFC_ON_BITN 2 -#define PRCM_PDSTAT1_RFC_ON_M 0x00000004 -#define PRCM_PDSTAT1_RFC_ON_S 2 +#define PRCM_PDSTAT1_RFC_ON 0x00000004 +#define PRCM_PDSTAT1_RFC_ON_BITN 2 +#define PRCM_PDSTAT1_RFC_ON_M 0x00000004 +#define PRCM_PDSTAT1_RFC_ON_S 2 // Field: [1] CPU_ON // // // 0: CPU and BUS domain not accessible // 1: CPU and BUS domains are both currently accessible -#define PRCM_PDSTAT1_CPU_ON 0x00000002 -#define PRCM_PDSTAT1_CPU_ON_BITN 1 -#define PRCM_PDSTAT1_CPU_ON_M 0x00000002 -#define PRCM_PDSTAT1_CPU_ON_S 1 +#define PRCM_PDSTAT1_CPU_ON 0x00000002 +#define PRCM_PDSTAT1_CPU_ON_BITN 1 +#define PRCM_PDSTAT1_CPU_ON_M 0x00000002 +#define PRCM_PDSTAT1_CPU_ON_S 1 //***************************************************************************** // @@ -1459,10 +1459,10 @@ // Field: [0] ON // // This is an alias for PDSTAT1.BUS_ON -#define PRCM_PDSTAT1BUS_ON 0x00000001 -#define PRCM_PDSTAT1BUS_ON_BITN 0 -#define PRCM_PDSTAT1BUS_ON_M 0x00000001 -#define PRCM_PDSTAT1BUS_ON_S 0 +#define PRCM_PDSTAT1BUS_ON 0x00000001 +#define PRCM_PDSTAT1BUS_ON_BITN 0 +#define PRCM_PDSTAT1BUS_ON_M 0x00000001 +#define PRCM_PDSTAT1BUS_ON_S 0 //***************************************************************************** // @@ -1472,10 +1472,10 @@ // Field: [0] ON // // This is an alias for PDSTAT1.RFC_ON -#define PRCM_PDSTAT1RFC_ON 0x00000001 -#define PRCM_PDSTAT1RFC_ON_BITN 0 -#define PRCM_PDSTAT1RFC_ON_M 0x00000001 -#define PRCM_PDSTAT1RFC_ON_S 0 +#define PRCM_PDSTAT1RFC_ON 0x00000001 +#define PRCM_PDSTAT1RFC_ON_BITN 0 +#define PRCM_PDSTAT1RFC_ON_M 0x00000001 +#define PRCM_PDSTAT1RFC_ON_S 0 //***************************************************************************** // @@ -1485,10 +1485,10 @@ // Field: [0] ON // // This is an alias for PDSTAT1.CPU_ON -#define PRCM_PDSTAT1CPU_ON 0x00000001 -#define PRCM_PDSTAT1CPU_ON_BITN 0 -#define PRCM_PDSTAT1CPU_ON_M 0x00000001 -#define PRCM_PDSTAT1CPU_ON_S 0 +#define PRCM_PDSTAT1CPU_ON 0x00000001 +#define PRCM_PDSTAT1CPU_ON_BITN 0 +#define PRCM_PDSTAT1CPU_ON_M 0x00000001 +#define PRCM_PDSTAT1CPU_ON_S 0 //***************************************************************************** // @@ -1498,10 +1498,10 @@ // Field: [0] ON // // This is an alias for PDSTAT1.VIMS_MODE -#define PRCM_PDSTAT1VIMS_ON 0x00000001 -#define PRCM_PDSTAT1VIMS_ON_BITN 0 -#define PRCM_PDSTAT1VIMS_ON_M 0x00000001 -#define PRCM_PDSTAT1VIMS_ON_S 0 +#define PRCM_PDSTAT1VIMS_ON 0x00000001 +#define PRCM_PDSTAT1VIMS_ON_BITN 0 +#define PRCM_PDSTAT1VIMS_ON_M 0x00000001 +#define PRCM_PDSTAT1VIMS_ON_S 0 //***************************************************************************** // @@ -1515,9 +1515,9 @@ // to perform some tasks at its start-up. The supported functionality is // ROM-defined and may vary. See the technical reference manual for more // details. -#define PRCM_RFCBITS_READ_W 32 -#define PRCM_RFCBITS_READ_M 0xFFFFFFFF -#define PRCM_RFCBITS_READ_S 0 +#define PRCM_RFCBITS_READ_W 32 +#define PRCM_RFCBITS_READ_M 0xFFFFFFFF +#define PRCM_RFCBITS_READ_S 0 //***************************************************************************** // @@ -1538,17 +1538,17 @@ // MODE2 Select Mode 2 // MODE1 Select Mode 1 // MODE0 Select Mode 0 -#define PRCM_RFCMODESEL_CURR_W 3 -#define PRCM_RFCMODESEL_CURR_M 0x00000007 -#define PRCM_RFCMODESEL_CURR_S 0 -#define PRCM_RFCMODESEL_CURR_MODE7 0x00000007 -#define PRCM_RFCMODESEL_CURR_MODE6 0x00000006 -#define PRCM_RFCMODESEL_CURR_MODE5 0x00000005 -#define PRCM_RFCMODESEL_CURR_MODE4 0x00000004 -#define PRCM_RFCMODESEL_CURR_MODE3 0x00000003 -#define PRCM_RFCMODESEL_CURR_MODE2 0x00000002 -#define PRCM_RFCMODESEL_CURR_MODE1 0x00000001 -#define PRCM_RFCMODESEL_CURR_MODE0 0x00000000 +#define PRCM_RFCMODESEL_CURR_W 3 +#define PRCM_RFCMODESEL_CURR_M 0x00000007 +#define PRCM_RFCMODESEL_CURR_S 0 +#define PRCM_RFCMODESEL_CURR_MODE7 0x00000007 +#define PRCM_RFCMODESEL_CURR_MODE6 0x00000006 +#define PRCM_RFCMODESEL_CURR_MODE5 0x00000005 +#define PRCM_RFCMODESEL_CURR_MODE4 0x00000004 +#define PRCM_RFCMODESEL_CURR_MODE3 0x00000003 +#define PRCM_RFCMODESEL_CURR_MODE2 0x00000002 +#define PRCM_RFCMODESEL_CURR_MODE1 0x00000001 +#define PRCM_RFCMODESEL_CURR_MODE0 0x00000000 //***************************************************************************** // @@ -1567,17 +1567,17 @@ // MODE2 Mode 2 permitted // MODE1 Mode 1 permitted // MODE0 Mode 0 permitted -#define PRCM_RFCMODEHWOPT_AVAIL_W 8 -#define PRCM_RFCMODEHWOPT_AVAIL_M 0x000000FF -#define PRCM_RFCMODEHWOPT_AVAIL_S 0 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE7 0x00000080 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE6 0x00000040 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE5 0x00000020 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE4 0x00000010 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE3 0x00000008 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE2 0x00000004 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE1 0x00000002 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE0 0x00000001 +#define PRCM_RFCMODEHWOPT_AVAIL_W 8 +#define PRCM_RFCMODEHWOPT_AVAIL_M 0x000000FF +#define PRCM_RFCMODEHWOPT_AVAIL_S 0 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE7 0x00000080 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE6 0x00000040 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE5 0x00000020 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE4 0x00000010 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE3 0x00000008 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE2 0x00000004 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE1 0x00000002 +#define PRCM_RFCMODEHWOPT_AVAIL_MODE0 0x00000001 //***************************************************************************** // @@ -1589,9 +1589,9 @@ // SW can use these bits to timestamp the application. These bits are also // available through the testtap and can thus be used by the emulator to // profile in real time. -#define PRCM_PWRPROFSTAT_VALUE_W 8 -#define PRCM_PWRPROFSTAT_VALUE_M 0x000000FF -#define PRCM_PWRPROFSTAT_VALUE_S 0 +#define PRCM_PWRPROFSTAT_VALUE_W 8 +#define PRCM_PWRPROFSTAT_VALUE_M 0x000000FF +#define PRCM_PWRPROFSTAT_VALUE_S 0 //***************************************************************************** // @@ -1605,10 +1605,10 @@ // 1: Retention for RFC SRAM enabled // // Memories controlled: CPERAM MCERAM RFERAM -#define PRCM_RAMRETEN_RFC 0x00000004 -#define PRCM_RAMRETEN_RFC_BITN 2 -#define PRCM_RAMRETEN_RFC_M 0x00000004 -#define PRCM_RAMRETEN_RFC_S 2 +#define PRCM_RAMRETEN_RFC 0x00000004 +#define PRCM_RAMRETEN_RFC_BITN 2 +#define PRCM_RAMRETEN_RFC_M 0x00000004 +#define PRCM_RAMRETEN_RFC_S 2 // Field: [1:0] VIMS // @@ -1628,9 +1628,8 @@ // or SPILT mode. // 10: Illegal mode // 11: No restrictions -#define PRCM_RAMRETEN_VIMS_W 2 -#define PRCM_RAMRETEN_VIMS_M 0x00000003 -#define PRCM_RAMRETEN_VIMS_S 0 - +#define PRCM_RAMRETEN_VIMS_W 2 +#define PRCM_RAMRETEN_VIMS_M 0x00000003 +#define PRCM_RAMRETEN_VIMS_S 0 #endif // __PRCM__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_rfc_dbell.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_rfc_dbell.h index 9ac876c..52a2cf0 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_rfc_dbell.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_rfc_dbell.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_rfc_dbell_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_rfc_dbell_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_RFC_DBELL_H__ #define __HW_RFC_DBELL_H__ @@ -44,32 +44,32 @@ // //***************************************************************************** // Doorbell Command Register -#define RFC_DBELL_O_CMDR 0x00000000 +#define RFC_DBELL_O_CMDR 0x00000000 // Doorbell Command Status Register -#define RFC_DBELL_O_CMDSTA 0x00000004 +#define RFC_DBELL_O_CMDSTA 0x00000004 // Interrupt Flags From RF Hardware Modules -#define RFC_DBELL_O_RFHWIFG 0x00000008 +#define RFC_DBELL_O_RFHWIFG 0x00000008 // Interrupt Enable For RF Hardware Modules -#define RFC_DBELL_O_RFHWIEN 0x0000000C +#define RFC_DBELL_O_RFHWIEN 0x0000000C // Interrupt Flags For Command and Packet Engine Generated Interrupts -#define RFC_DBELL_O_RFCPEIFG 0x00000010 +#define RFC_DBELL_O_RFCPEIFG 0x00000010 // Interrupt Enable For Command and Packet Engine Generated Interrupts -#define RFC_DBELL_O_RFCPEIEN 0x00000014 +#define RFC_DBELL_O_RFCPEIEN 0x00000014 // Interrupt Vector Selection For Command and Packet Engine Generated // Interrupts -#define RFC_DBELL_O_RFCPEISL 0x00000018 +#define RFC_DBELL_O_RFCPEISL 0x00000018 // Doorbell Command Acknowledgement Interrupt Flag -#define RFC_DBELL_O_RFACKIFG 0x0000001C +#define RFC_DBELL_O_RFACKIFG 0x0000001C // RF Core General Purpose Output Control -#define RFC_DBELL_O_SYSGPOCTL 0x00000020 +#define RFC_DBELL_O_SYSGPOCTL 0x00000020 //***************************************************************************** // @@ -80,9 +80,9 @@ // // Command register. Raises an interrupt to the Command and packet engine (CPE) // upon write. -#define RFC_DBELL_CMDR_CMD_W 32 -#define RFC_DBELL_CMDR_CMD_M 0xFFFFFFFF -#define RFC_DBELL_CMDR_CMD_S 0 +#define RFC_DBELL_CMDR_CMD_W 32 +#define RFC_DBELL_CMDR_CMD_M 0xFFFFFFFF +#define RFC_DBELL_CMDR_CMD_S 0 //***************************************************************************** // @@ -92,9 +92,9 @@ // Field: [31:0] STAT // // Status of the last command used -#define RFC_DBELL_CMDSTA_STAT_W 32 -#define RFC_DBELL_CMDSTA_STAT_M 0xFFFFFFFF -#define RFC_DBELL_CMDSTA_STAT_S 0 +#define RFC_DBELL_CMDSTA_STAT_W 32 +#define RFC_DBELL_CMDSTA_STAT_M 0xFFFFFFFF +#define RFC_DBELL_CMDSTA_STAT_S 0 //***************************************************************************** // @@ -105,118 +105,118 @@ // // Radio timer channel 7 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH7 0x00080000 -#define RFC_DBELL_RFHWIFG_RATCH7_BITN 19 -#define RFC_DBELL_RFHWIFG_RATCH7_M 0x00080000 -#define RFC_DBELL_RFHWIFG_RATCH7_S 19 +#define RFC_DBELL_RFHWIFG_RATCH7 0x00080000 +#define RFC_DBELL_RFHWIFG_RATCH7_BITN 19 +#define RFC_DBELL_RFHWIFG_RATCH7_M 0x00080000 +#define RFC_DBELL_RFHWIFG_RATCH7_S 19 // Field: [18] RATCH6 // // Radio timer channel 6 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH6 0x00040000 -#define RFC_DBELL_RFHWIFG_RATCH6_BITN 18 -#define RFC_DBELL_RFHWIFG_RATCH6_M 0x00040000 -#define RFC_DBELL_RFHWIFG_RATCH6_S 18 +#define RFC_DBELL_RFHWIFG_RATCH6 0x00040000 +#define RFC_DBELL_RFHWIFG_RATCH6_BITN 18 +#define RFC_DBELL_RFHWIFG_RATCH6_M 0x00040000 +#define RFC_DBELL_RFHWIFG_RATCH6_S 18 // Field: [17] RATCH5 // // Radio timer channel 5 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH5 0x00020000 -#define RFC_DBELL_RFHWIFG_RATCH5_BITN 17 -#define RFC_DBELL_RFHWIFG_RATCH5_M 0x00020000 -#define RFC_DBELL_RFHWIFG_RATCH5_S 17 +#define RFC_DBELL_RFHWIFG_RATCH5 0x00020000 +#define RFC_DBELL_RFHWIFG_RATCH5_BITN 17 +#define RFC_DBELL_RFHWIFG_RATCH5_M 0x00020000 +#define RFC_DBELL_RFHWIFG_RATCH5_S 17 // Field: [16] RATCH4 // // Radio timer channel 4 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH4 0x00010000 -#define RFC_DBELL_RFHWIFG_RATCH4_BITN 16 -#define RFC_DBELL_RFHWIFG_RATCH4_M 0x00010000 -#define RFC_DBELL_RFHWIFG_RATCH4_S 16 +#define RFC_DBELL_RFHWIFG_RATCH4 0x00010000 +#define RFC_DBELL_RFHWIFG_RATCH4_BITN 16 +#define RFC_DBELL_RFHWIFG_RATCH4_M 0x00010000 +#define RFC_DBELL_RFHWIFG_RATCH4_S 16 // Field: [15] RATCH3 // // Radio timer channel 3 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH3 0x00008000 -#define RFC_DBELL_RFHWIFG_RATCH3_BITN 15 -#define RFC_DBELL_RFHWIFG_RATCH3_M 0x00008000 -#define RFC_DBELL_RFHWIFG_RATCH3_S 15 +#define RFC_DBELL_RFHWIFG_RATCH3 0x00008000 +#define RFC_DBELL_RFHWIFG_RATCH3_BITN 15 +#define RFC_DBELL_RFHWIFG_RATCH3_M 0x00008000 +#define RFC_DBELL_RFHWIFG_RATCH3_S 15 // Field: [14] RATCH2 // // Radio timer channel 2 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH2 0x00004000 -#define RFC_DBELL_RFHWIFG_RATCH2_BITN 14 -#define RFC_DBELL_RFHWIFG_RATCH2_M 0x00004000 -#define RFC_DBELL_RFHWIFG_RATCH2_S 14 +#define RFC_DBELL_RFHWIFG_RATCH2 0x00004000 +#define RFC_DBELL_RFHWIFG_RATCH2_BITN 14 +#define RFC_DBELL_RFHWIFG_RATCH2_M 0x00004000 +#define RFC_DBELL_RFHWIFG_RATCH2_S 14 // Field: [13] RATCH1 // // Radio timer channel 1 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH1 0x00002000 -#define RFC_DBELL_RFHWIFG_RATCH1_BITN 13 -#define RFC_DBELL_RFHWIFG_RATCH1_M 0x00002000 -#define RFC_DBELL_RFHWIFG_RATCH1_S 13 +#define RFC_DBELL_RFHWIFG_RATCH1 0x00002000 +#define RFC_DBELL_RFHWIFG_RATCH1_BITN 13 +#define RFC_DBELL_RFHWIFG_RATCH1_M 0x00002000 +#define RFC_DBELL_RFHWIFG_RATCH1_S 13 // Field: [12] RATCH0 // // Radio timer channel 0 interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_RATCH0 0x00001000 -#define RFC_DBELL_RFHWIFG_RATCH0_BITN 12 -#define RFC_DBELL_RFHWIFG_RATCH0_M 0x00001000 -#define RFC_DBELL_RFHWIFG_RATCH0_S 12 +#define RFC_DBELL_RFHWIFG_RATCH0 0x00001000 +#define RFC_DBELL_RFHWIFG_RATCH0_BITN 12 +#define RFC_DBELL_RFHWIFG_RATCH0_M 0x00001000 +#define RFC_DBELL_RFHWIFG_RATCH0_S 12 // Field: [11] RFESOFT2 // // RF engine software defined interrupt 2 flag. Write zero to clear flag. Write // to one has no effect. -#define RFC_DBELL_RFHWIFG_RFESOFT2 0x00000800 -#define RFC_DBELL_RFHWIFG_RFESOFT2_BITN 11 -#define RFC_DBELL_RFHWIFG_RFESOFT2_M 0x00000800 -#define RFC_DBELL_RFHWIFG_RFESOFT2_S 11 +#define RFC_DBELL_RFHWIFG_RFESOFT2 0x00000800 +#define RFC_DBELL_RFHWIFG_RFESOFT2_BITN 11 +#define RFC_DBELL_RFHWIFG_RFESOFT2_M 0x00000800 +#define RFC_DBELL_RFHWIFG_RFESOFT2_S 11 // Field: [10] RFESOFT1 // // RF engine software defined interrupt 1 flag. Write zero to clear flag. Write // to one has no effect. -#define RFC_DBELL_RFHWIFG_RFESOFT1 0x00000400 -#define RFC_DBELL_RFHWIFG_RFESOFT1_BITN 10 -#define RFC_DBELL_RFHWIFG_RFESOFT1_M 0x00000400 -#define RFC_DBELL_RFHWIFG_RFESOFT1_S 10 +#define RFC_DBELL_RFHWIFG_RFESOFT1 0x00000400 +#define RFC_DBELL_RFHWIFG_RFESOFT1_BITN 10 +#define RFC_DBELL_RFHWIFG_RFESOFT1_M 0x00000400 +#define RFC_DBELL_RFHWIFG_RFESOFT1_S 10 // Field: [9] RFESOFT0 // // RF engine software defined interrupt 0 flag. Write zero to clear flag. Write // to one has no effect. -#define RFC_DBELL_RFHWIFG_RFESOFT0 0x00000200 -#define RFC_DBELL_RFHWIFG_RFESOFT0_BITN 9 -#define RFC_DBELL_RFHWIFG_RFESOFT0_M 0x00000200 -#define RFC_DBELL_RFHWIFG_RFESOFT0_S 9 +#define RFC_DBELL_RFHWIFG_RFESOFT0 0x00000200 +#define RFC_DBELL_RFHWIFG_RFESOFT0_BITN 9 +#define RFC_DBELL_RFHWIFG_RFESOFT0_M 0x00000200 +#define RFC_DBELL_RFHWIFG_RFESOFT0_S 9 // Field: [8] RFEDONE // // RF engine command done interrupt flag. Write zero to clear flag. Write to // one has no effect. -#define RFC_DBELL_RFHWIFG_RFEDONE 0x00000100 -#define RFC_DBELL_RFHWIFG_RFEDONE_BITN 8 -#define RFC_DBELL_RFHWIFG_RFEDONE_M 0x00000100 -#define RFC_DBELL_RFHWIFG_RFEDONE_S 8 +#define RFC_DBELL_RFHWIFG_RFEDONE 0x00000100 +#define RFC_DBELL_RFHWIFG_RFEDONE_BITN 8 +#define RFC_DBELL_RFHWIFG_RFEDONE_M 0x00000100 +#define RFC_DBELL_RFHWIFG_RFEDONE_S 8 // Field: [6] TRCTK // // Debug tracer system tick interrupt flag. Write zero to clear flag. Write to // one has no effect. -#define RFC_DBELL_RFHWIFG_TRCTK 0x00000040 -#define RFC_DBELL_RFHWIFG_TRCTK_BITN 6 -#define RFC_DBELL_RFHWIFG_TRCTK_M 0x00000040 -#define RFC_DBELL_RFHWIFG_TRCTK_S 6 +#define RFC_DBELL_RFHWIFG_TRCTK 0x00000040 +#define RFC_DBELL_RFHWIFG_TRCTK_BITN 6 +#define RFC_DBELL_RFHWIFG_TRCTK_M 0x00000040 +#define RFC_DBELL_RFHWIFG_TRCTK_S 6 // Field: [5] MDMSOFT // @@ -224,46 +224,46 @@ // raised by modem when the synchronization word is received. The CPE may // decide to reject the packet based on its header (protocol specific). Write // zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFHWIFG_MDMSOFT 0x00000020 -#define RFC_DBELL_RFHWIFG_MDMSOFT_BITN 5 -#define RFC_DBELL_RFHWIFG_MDMSOFT_M 0x00000020 -#define RFC_DBELL_RFHWIFG_MDMSOFT_S 5 +#define RFC_DBELL_RFHWIFG_MDMSOFT 0x00000020 +#define RFC_DBELL_RFHWIFG_MDMSOFT_BITN 5 +#define RFC_DBELL_RFHWIFG_MDMSOFT_M 0x00000020 +#define RFC_DBELL_RFHWIFG_MDMSOFT_S 5 // Field: [4] MDMOUT // // Modem FIFO output interrupt flag. Write zero to clear flag. Write to one has // no effect. -#define RFC_DBELL_RFHWIFG_MDMOUT 0x00000010 -#define RFC_DBELL_RFHWIFG_MDMOUT_BITN 4 -#define RFC_DBELL_RFHWIFG_MDMOUT_M 0x00000010 -#define RFC_DBELL_RFHWIFG_MDMOUT_S 4 +#define RFC_DBELL_RFHWIFG_MDMOUT 0x00000010 +#define RFC_DBELL_RFHWIFG_MDMOUT_BITN 4 +#define RFC_DBELL_RFHWIFG_MDMOUT_M 0x00000010 +#define RFC_DBELL_RFHWIFG_MDMOUT_S 4 // Field: [3] MDMIN // // Modem FIFO input interrupt flag. Write zero to clear flag. Write to one has // no effect. -#define RFC_DBELL_RFHWIFG_MDMIN 0x00000008 -#define RFC_DBELL_RFHWIFG_MDMIN_BITN 3 -#define RFC_DBELL_RFHWIFG_MDMIN_M 0x00000008 -#define RFC_DBELL_RFHWIFG_MDMIN_S 3 +#define RFC_DBELL_RFHWIFG_MDMIN 0x00000008 +#define RFC_DBELL_RFHWIFG_MDMIN_BITN 3 +#define RFC_DBELL_RFHWIFG_MDMIN_M 0x00000008 +#define RFC_DBELL_RFHWIFG_MDMIN_S 3 // Field: [2] MDMDONE // // Modem command done interrupt flag. Write zero to clear flag. Write to one // has no effect. -#define RFC_DBELL_RFHWIFG_MDMDONE 0x00000004 -#define RFC_DBELL_RFHWIFG_MDMDONE_BITN 2 -#define RFC_DBELL_RFHWIFG_MDMDONE_M 0x00000004 -#define RFC_DBELL_RFHWIFG_MDMDONE_S 2 +#define RFC_DBELL_RFHWIFG_MDMDONE 0x00000004 +#define RFC_DBELL_RFHWIFG_MDMDONE_BITN 2 +#define RFC_DBELL_RFHWIFG_MDMDONE_M 0x00000004 +#define RFC_DBELL_RFHWIFG_MDMDONE_S 2 // Field: [1] FSCA // // Frequency synthesizer calibration accelerator interrupt flag. Write zero to // clear flag. Write to one has no effect. -#define RFC_DBELL_RFHWIFG_FSCA 0x00000002 -#define RFC_DBELL_RFHWIFG_FSCA_BITN 1 -#define RFC_DBELL_RFHWIFG_FSCA_M 0x00000002 -#define RFC_DBELL_RFHWIFG_FSCA_S 1 +#define RFC_DBELL_RFHWIFG_FSCA 0x00000002 +#define RFC_DBELL_RFHWIFG_FSCA_BITN 1 +#define RFC_DBELL_RFHWIFG_FSCA_M 0x00000002 +#define RFC_DBELL_RFHWIFG_FSCA_S 1 //***************************************************************************** // @@ -273,146 +273,146 @@ // Field: [19] RATCH7 // // Interrupt enable for RFHWIFG.RATCH7. -#define RFC_DBELL_RFHWIEN_RATCH7 0x00080000 -#define RFC_DBELL_RFHWIEN_RATCH7_BITN 19 -#define RFC_DBELL_RFHWIEN_RATCH7_M 0x00080000 -#define RFC_DBELL_RFHWIEN_RATCH7_S 19 +#define RFC_DBELL_RFHWIEN_RATCH7 0x00080000 +#define RFC_DBELL_RFHWIEN_RATCH7_BITN 19 +#define RFC_DBELL_RFHWIEN_RATCH7_M 0x00080000 +#define RFC_DBELL_RFHWIEN_RATCH7_S 19 // Field: [18] RATCH6 // // Interrupt enable for RFHWIFG.RATCH6. -#define RFC_DBELL_RFHWIEN_RATCH6 0x00040000 -#define RFC_DBELL_RFHWIEN_RATCH6_BITN 18 -#define RFC_DBELL_RFHWIEN_RATCH6_M 0x00040000 -#define RFC_DBELL_RFHWIEN_RATCH6_S 18 +#define RFC_DBELL_RFHWIEN_RATCH6 0x00040000 +#define RFC_DBELL_RFHWIEN_RATCH6_BITN 18 +#define RFC_DBELL_RFHWIEN_RATCH6_M 0x00040000 +#define RFC_DBELL_RFHWIEN_RATCH6_S 18 // Field: [17] RATCH5 // // Interrupt enable for RFHWIFG.RATCH5. -#define RFC_DBELL_RFHWIEN_RATCH5 0x00020000 -#define RFC_DBELL_RFHWIEN_RATCH5_BITN 17 -#define RFC_DBELL_RFHWIEN_RATCH5_M 0x00020000 -#define RFC_DBELL_RFHWIEN_RATCH5_S 17 +#define RFC_DBELL_RFHWIEN_RATCH5 0x00020000 +#define RFC_DBELL_RFHWIEN_RATCH5_BITN 17 +#define RFC_DBELL_RFHWIEN_RATCH5_M 0x00020000 +#define RFC_DBELL_RFHWIEN_RATCH5_S 17 // Field: [16] RATCH4 // // Interrupt enable for RFHWIFG.RATCH4. -#define RFC_DBELL_RFHWIEN_RATCH4 0x00010000 -#define RFC_DBELL_RFHWIEN_RATCH4_BITN 16 -#define RFC_DBELL_RFHWIEN_RATCH4_M 0x00010000 -#define RFC_DBELL_RFHWIEN_RATCH4_S 16 +#define RFC_DBELL_RFHWIEN_RATCH4 0x00010000 +#define RFC_DBELL_RFHWIEN_RATCH4_BITN 16 +#define RFC_DBELL_RFHWIEN_RATCH4_M 0x00010000 +#define RFC_DBELL_RFHWIEN_RATCH4_S 16 // Field: [15] RATCH3 // // Interrupt enable for RFHWIFG.RATCH3. -#define RFC_DBELL_RFHWIEN_RATCH3 0x00008000 -#define RFC_DBELL_RFHWIEN_RATCH3_BITN 15 -#define RFC_DBELL_RFHWIEN_RATCH3_M 0x00008000 -#define RFC_DBELL_RFHWIEN_RATCH3_S 15 +#define RFC_DBELL_RFHWIEN_RATCH3 0x00008000 +#define RFC_DBELL_RFHWIEN_RATCH3_BITN 15 +#define RFC_DBELL_RFHWIEN_RATCH3_M 0x00008000 +#define RFC_DBELL_RFHWIEN_RATCH3_S 15 // Field: [14] RATCH2 // // Interrupt enable for RFHWIFG.RATCH2. -#define RFC_DBELL_RFHWIEN_RATCH2 0x00004000 -#define RFC_DBELL_RFHWIEN_RATCH2_BITN 14 -#define RFC_DBELL_RFHWIEN_RATCH2_M 0x00004000 -#define RFC_DBELL_RFHWIEN_RATCH2_S 14 +#define RFC_DBELL_RFHWIEN_RATCH2 0x00004000 +#define RFC_DBELL_RFHWIEN_RATCH2_BITN 14 +#define RFC_DBELL_RFHWIEN_RATCH2_M 0x00004000 +#define RFC_DBELL_RFHWIEN_RATCH2_S 14 // Field: [13] RATCH1 // // Interrupt enable for RFHWIFG.RATCH1. -#define RFC_DBELL_RFHWIEN_RATCH1 0x00002000 -#define RFC_DBELL_RFHWIEN_RATCH1_BITN 13 -#define RFC_DBELL_RFHWIEN_RATCH1_M 0x00002000 -#define RFC_DBELL_RFHWIEN_RATCH1_S 13 +#define RFC_DBELL_RFHWIEN_RATCH1 0x00002000 +#define RFC_DBELL_RFHWIEN_RATCH1_BITN 13 +#define RFC_DBELL_RFHWIEN_RATCH1_M 0x00002000 +#define RFC_DBELL_RFHWIEN_RATCH1_S 13 // Field: [12] RATCH0 // // Interrupt enable for RFHWIFG.RATCH0. -#define RFC_DBELL_RFHWIEN_RATCH0 0x00001000 -#define RFC_DBELL_RFHWIEN_RATCH0_BITN 12 -#define RFC_DBELL_RFHWIEN_RATCH0_M 0x00001000 -#define RFC_DBELL_RFHWIEN_RATCH0_S 12 +#define RFC_DBELL_RFHWIEN_RATCH0 0x00001000 +#define RFC_DBELL_RFHWIEN_RATCH0_BITN 12 +#define RFC_DBELL_RFHWIEN_RATCH0_M 0x00001000 +#define RFC_DBELL_RFHWIEN_RATCH0_S 12 // Field: [11] RFESOFT2 // // Interrupt enable for RFHWIFG.RFESOFT2. -#define RFC_DBELL_RFHWIEN_RFESOFT2 0x00000800 -#define RFC_DBELL_RFHWIEN_RFESOFT2_BITN 11 -#define RFC_DBELL_RFHWIEN_RFESOFT2_M 0x00000800 -#define RFC_DBELL_RFHWIEN_RFESOFT2_S 11 +#define RFC_DBELL_RFHWIEN_RFESOFT2 0x00000800 +#define RFC_DBELL_RFHWIEN_RFESOFT2_BITN 11 +#define RFC_DBELL_RFHWIEN_RFESOFT2_M 0x00000800 +#define RFC_DBELL_RFHWIEN_RFESOFT2_S 11 // Field: [10] RFESOFT1 // // Interrupt enable for RFHWIFG.RFESOFT1. -#define RFC_DBELL_RFHWIEN_RFESOFT1 0x00000400 -#define RFC_DBELL_RFHWIEN_RFESOFT1_BITN 10 -#define RFC_DBELL_RFHWIEN_RFESOFT1_M 0x00000400 -#define RFC_DBELL_RFHWIEN_RFESOFT1_S 10 +#define RFC_DBELL_RFHWIEN_RFESOFT1 0x00000400 +#define RFC_DBELL_RFHWIEN_RFESOFT1_BITN 10 +#define RFC_DBELL_RFHWIEN_RFESOFT1_M 0x00000400 +#define RFC_DBELL_RFHWIEN_RFESOFT1_S 10 // Field: [9] RFESOFT0 // // Interrupt enable for RFHWIFG.RFESOFT0. -#define RFC_DBELL_RFHWIEN_RFESOFT0 0x00000200 -#define RFC_DBELL_RFHWIEN_RFESOFT0_BITN 9 -#define RFC_DBELL_RFHWIEN_RFESOFT0_M 0x00000200 -#define RFC_DBELL_RFHWIEN_RFESOFT0_S 9 +#define RFC_DBELL_RFHWIEN_RFESOFT0 0x00000200 +#define RFC_DBELL_RFHWIEN_RFESOFT0_BITN 9 +#define RFC_DBELL_RFHWIEN_RFESOFT0_M 0x00000200 +#define RFC_DBELL_RFHWIEN_RFESOFT0_S 9 // Field: [8] RFEDONE // // Interrupt enable for RFHWIFG.RFEDONE. -#define RFC_DBELL_RFHWIEN_RFEDONE 0x00000100 -#define RFC_DBELL_RFHWIEN_RFEDONE_BITN 8 -#define RFC_DBELL_RFHWIEN_RFEDONE_M 0x00000100 -#define RFC_DBELL_RFHWIEN_RFEDONE_S 8 +#define RFC_DBELL_RFHWIEN_RFEDONE 0x00000100 +#define RFC_DBELL_RFHWIEN_RFEDONE_BITN 8 +#define RFC_DBELL_RFHWIEN_RFEDONE_M 0x00000100 +#define RFC_DBELL_RFHWIEN_RFEDONE_S 8 // Field: [6] TRCTK // // Interrupt enable for RFHWIFG.TRCTK. -#define RFC_DBELL_RFHWIEN_TRCTK 0x00000040 -#define RFC_DBELL_RFHWIEN_TRCTK_BITN 6 -#define RFC_DBELL_RFHWIEN_TRCTK_M 0x00000040 -#define RFC_DBELL_RFHWIEN_TRCTK_S 6 +#define RFC_DBELL_RFHWIEN_TRCTK 0x00000040 +#define RFC_DBELL_RFHWIEN_TRCTK_BITN 6 +#define RFC_DBELL_RFHWIEN_TRCTK_M 0x00000040 +#define RFC_DBELL_RFHWIEN_TRCTK_S 6 // Field: [5] MDMSOFT // // Interrupt enable for RFHWIFG.MDMSOFT. -#define RFC_DBELL_RFHWIEN_MDMSOFT 0x00000020 -#define RFC_DBELL_RFHWIEN_MDMSOFT_BITN 5 -#define RFC_DBELL_RFHWIEN_MDMSOFT_M 0x00000020 -#define RFC_DBELL_RFHWIEN_MDMSOFT_S 5 +#define RFC_DBELL_RFHWIEN_MDMSOFT 0x00000020 +#define RFC_DBELL_RFHWIEN_MDMSOFT_BITN 5 +#define RFC_DBELL_RFHWIEN_MDMSOFT_M 0x00000020 +#define RFC_DBELL_RFHWIEN_MDMSOFT_S 5 // Field: [4] MDMOUT // // Interrupt enable for RFHWIFG.MDMOUT. -#define RFC_DBELL_RFHWIEN_MDMOUT 0x00000010 -#define RFC_DBELL_RFHWIEN_MDMOUT_BITN 4 -#define RFC_DBELL_RFHWIEN_MDMOUT_M 0x00000010 -#define RFC_DBELL_RFHWIEN_MDMOUT_S 4 +#define RFC_DBELL_RFHWIEN_MDMOUT 0x00000010 +#define RFC_DBELL_RFHWIEN_MDMOUT_BITN 4 +#define RFC_DBELL_RFHWIEN_MDMOUT_M 0x00000010 +#define RFC_DBELL_RFHWIEN_MDMOUT_S 4 // Field: [3] MDMIN // // Interrupt enable for RFHWIFG.MDMIN. -#define RFC_DBELL_RFHWIEN_MDMIN 0x00000008 -#define RFC_DBELL_RFHWIEN_MDMIN_BITN 3 -#define RFC_DBELL_RFHWIEN_MDMIN_M 0x00000008 -#define RFC_DBELL_RFHWIEN_MDMIN_S 3 +#define RFC_DBELL_RFHWIEN_MDMIN 0x00000008 +#define RFC_DBELL_RFHWIEN_MDMIN_BITN 3 +#define RFC_DBELL_RFHWIEN_MDMIN_M 0x00000008 +#define RFC_DBELL_RFHWIEN_MDMIN_S 3 // Field: [2] MDMDONE // // Interrupt enable for RFHWIFG.MDMDONE. -#define RFC_DBELL_RFHWIEN_MDMDONE 0x00000004 -#define RFC_DBELL_RFHWIEN_MDMDONE_BITN 2 -#define RFC_DBELL_RFHWIEN_MDMDONE_M 0x00000004 -#define RFC_DBELL_RFHWIEN_MDMDONE_S 2 +#define RFC_DBELL_RFHWIEN_MDMDONE 0x00000004 +#define RFC_DBELL_RFHWIEN_MDMDONE_BITN 2 +#define RFC_DBELL_RFHWIEN_MDMDONE_M 0x00000004 +#define RFC_DBELL_RFHWIEN_MDMDONE_S 2 // Field: [1] FSCA // // Interrupt enable for RFHWIFG.FSCA. -#define RFC_DBELL_RFHWIEN_FSCA 0x00000002 -#define RFC_DBELL_RFHWIEN_FSCA_BITN 1 -#define RFC_DBELL_RFHWIEN_FSCA_M 0x00000002 -#define RFC_DBELL_RFHWIEN_FSCA_S 1 +#define RFC_DBELL_RFHWIEN_FSCA 0x00000002 +#define RFC_DBELL_RFHWIEN_FSCA_BITN 1 +#define RFC_DBELL_RFHWIEN_FSCA_M 0x00000002 +#define RFC_DBELL_RFHWIEN_FSCA_S 1 //***************************************************************************** // @@ -425,82 +425,82 @@ // unexpected error. A reset of the CPE is needed. This can be done by // switching the RF Core power domain off and on in PRCM:PDCTL1RFC. Write zero // to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR 0x80000000 -#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_BITN 31 -#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_M 0x80000000 -#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_S 31 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_S 31 // Field: [30] BOOT_DONE // // Interrupt flag 30. The command and packet engine (CPE) boot is finished. // Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_BOOT_DONE 0x40000000 -#define RFC_DBELL_RFCPEIFG_BOOT_DONE_BITN 30 -#define RFC_DBELL_RFCPEIFG_BOOT_DONE_M 0x40000000 -#define RFC_DBELL_RFCPEIFG_BOOT_DONE_S 30 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEIFG_BOOT_DONE_S 30 // Field: [29] MODULES_UNLOCKED // // Interrupt flag 29. As part of command and packet engine (CPE) boot process, // it has opened access to RF Core modules and memories. Write zero to clear // flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED 0x20000000 -#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_BITN 29 -#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_M 0x20000000 -#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_S 29 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_S 29 // Field: [28] SYNTH_NO_LOCK // // Interrupt flag 28. The phase-locked loop in frequency synthesizer has // reported loss of lock. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK 0x10000000 -#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_BITN 28 -#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_M 0x10000000 -#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_S 28 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_S 28 // Field: [27] IRQ27 // // Interrupt flag 27. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_IRQ27 0x08000000 -#define RFC_DBELL_RFCPEIFG_IRQ27_BITN 27 -#define RFC_DBELL_RFCPEIFG_IRQ27_M 0x08000000 -#define RFC_DBELL_RFCPEIFG_IRQ27_S 27 +#define RFC_DBELL_RFCPEIFG_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEIFG_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEIFG_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEIFG_IRQ27_S 27 // Field: [26] RX_ABORTED // // Interrupt flag 26. Packet reception stopped before packet was done. Write // zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_ABORTED 0x04000000 -#define RFC_DBELL_RFCPEIFG_RX_ABORTED_BITN 26 -#define RFC_DBELL_RFCPEIFG_RX_ABORTED_M 0x04000000 -#define RFC_DBELL_RFCPEIFG_RX_ABORTED_S 26 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEIFG_RX_ABORTED_S 26 // Field: [25] RX_N_DATA_WRITTEN // // Interrupt flag 25. Specified number of bytes written to partial read Rx // buffer. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN 0x02000000 -#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_BITN 25 -#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_M 0x02000000 -#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_S 25 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_S 25 // Field: [24] RX_DATA_WRITTEN // // Interrupt flag 24. Data written to partial read Rx buffer. Write zero to // clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN 0x01000000 -#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_BITN 24 -#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_M 0x01000000 -#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_S 24 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_S 24 // Field: [23] RX_ENTRY_DONE // // Interrupt flag 23. Rx queue data entry changing state to finished. Write // zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE 0x00800000 -#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_BITN 23 -#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_M 0x00800000 -#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_S 23 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_S 23 // Field: [22] RX_BUF_FULL // @@ -508,194 +508,194 @@ // Packet received that did not fit in the Rx queue. IEEE 802.15.4 mode: Frame // received that did not fit in the Rx queue. Write zero to clear flag. Write // to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL 0x00400000 -#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_BITN 22 -#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_M 0x00400000 -#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_S 22 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_S 22 // Field: [21] RX_CTRL_ACK // // Interrupt flag 21. BLE mode only: LL control packet received with CRC OK, // not to be ignored, then acknowledgement sent. Write zero to clear flag. // Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK 0x00200000 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_BITN 21 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_M 0x00200000 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_S 21 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_S 21 // Field: [20] RX_CTRL // // Interrupt flag 20. BLE mode only: LL control packet received with CRC OK, // not to be ignored. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_CTRL 0x00100000 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_BITN 20 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_M 0x00100000 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_S 20 +#define RFC_DBELL_RFCPEIFG_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEIFG_RX_CTRL_S 20 // Field: [19] RX_EMPTY // // Interrupt flag 19. BLE mode only: Packet received with CRC OK, not to be // ignored, no payload. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_EMPTY 0x00080000 -#define RFC_DBELL_RFCPEIFG_RX_EMPTY_BITN 19 -#define RFC_DBELL_RFCPEIFG_RX_EMPTY_M 0x00080000 -#define RFC_DBELL_RFCPEIFG_RX_EMPTY_S 19 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEIFG_RX_EMPTY_S 19 // Field: [18] RX_IGNORED // // Interrupt flag 18. Packet received, but can be ignored. BLE mode: Packet // received with CRC OK, but to be ignored. IEEE 802.15.4 mode: Frame received // with ignore flag set. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_IGNORED 0x00040000 -#define RFC_DBELL_RFCPEIFG_RX_IGNORED_BITN 18 -#define RFC_DBELL_RFCPEIFG_RX_IGNORED_M 0x00040000 -#define RFC_DBELL_RFCPEIFG_RX_IGNORED_S 18 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEIFG_RX_IGNORED_S 18 // Field: [17] RX_NOK // // Interrupt flag 17. Packet received with CRC error. BLE mode: Packet received // with CRC error. IEEE 802.15.4 mode: Frame received with CRC error. Write // zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_NOK 0x00020000 -#define RFC_DBELL_RFCPEIFG_RX_NOK_BITN 17 -#define RFC_DBELL_RFCPEIFG_RX_NOK_M 0x00020000 -#define RFC_DBELL_RFCPEIFG_RX_NOK_S 17 +#define RFC_DBELL_RFCPEIFG_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEIFG_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEIFG_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEIFG_RX_NOK_S 17 // Field: [16] RX_OK // // Interrupt flag 16. Packet received correctly. BLE mode: Packet received with // CRC OK, payload, and not to be ignored. IEEE 802.15.4 mode: Frame received // with CRC OK. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_OK 0x00010000 -#define RFC_DBELL_RFCPEIFG_RX_OK_BITN 16 -#define RFC_DBELL_RFCPEIFG_RX_OK_M 0x00010000 -#define RFC_DBELL_RFCPEIFG_RX_OK_S 16 +#define RFC_DBELL_RFCPEIFG_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEIFG_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEIFG_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEIFG_RX_OK_S 16 // Field: [15] IRQ15 // // Interrupt flag 15. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_IRQ15 0x00008000 -#define RFC_DBELL_RFCPEIFG_IRQ15_BITN 15 -#define RFC_DBELL_RFCPEIFG_IRQ15_M 0x00008000 -#define RFC_DBELL_RFCPEIFG_IRQ15_S 15 +#define RFC_DBELL_RFCPEIFG_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEIFG_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEIFG_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEIFG_IRQ15_S 15 // Field: [14] IRQ14 // // Interrupt flag 14. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_IRQ14 0x00004000 -#define RFC_DBELL_RFCPEIFG_IRQ14_BITN 14 -#define RFC_DBELL_RFCPEIFG_IRQ14_M 0x00004000 -#define RFC_DBELL_RFCPEIFG_IRQ14_S 14 +#define RFC_DBELL_RFCPEIFG_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEIFG_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEIFG_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEIFG_IRQ14_S 14 // Field: [13] IRQ13 // // Interrupt flag 13. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_IRQ13 0x00002000 -#define RFC_DBELL_RFCPEIFG_IRQ13_BITN 13 -#define RFC_DBELL_RFCPEIFG_IRQ13_M 0x00002000 -#define RFC_DBELL_RFCPEIFG_IRQ13_S 13 +#define RFC_DBELL_RFCPEIFG_IRQ13 0x00002000 +#define RFC_DBELL_RFCPEIFG_IRQ13_BITN 13 +#define RFC_DBELL_RFCPEIFG_IRQ13_M 0x00002000 +#define RFC_DBELL_RFCPEIFG_IRQ13_S 13 // Field: [12] IRQ12 // // Interrupt flag 12. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_IRQ12 0x00001000 -#define RFC_DBELL_RFCPEIFG_IRQ12_BITN 12 -#define RFC_DBELL_RFCPEIFG_IRQ12_M 0x00001000 -#define RFC_DBELL_RFCPEIFG_IRQ12_S 12 +#define RFC_DBELL_RFCPEIFG_IRQ12 0x00001000 +#define RFC_DBELL_RFCPEIFG_IRQ12_BITN 12 +#define RFC_DBELL_RFCPEIFG_IRQ12_M 0x00001000 +#define RFC_DBELL_RFCPEIFG_IRQ12_S 12 // Field: [11] TX_BUFFER_CHANGED // // Interrupt flag 11. BLE mode only: A buffer change is complete after // CMD_BLE_ADV_PAYLOAD. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED 0x00000800 -#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_BITN 11 -#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_M 0x00000800 -#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_S 11 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_S 11 // Field: [10] TX_ENTRY_DONE // // Interrupt flag 10. Tx queue data entry state changed to finished. Write zero // to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE 0x00000400 -#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_BITN 10 -#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_M 0x00000400 -#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_S 10 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_S 10 // Field: [9] TX_RETRANS // // Interrupt flag 9. BLE mode only: Packet retransmitted. Write zero to clear // flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_RETRANS 0x00000200 -#define RFC_DBELL_RFCPEIFG_TX_RETRANS_BITN 9 -#define RFC_DBELL_RFCPEIFG_TX_RETRANS_M 0x00000200 -#define RFC_DBELL_RFCPEIFG_TX_RETRANS_S 9 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEIFG_TX_RETRANS_S 9 // Field: [8] TX_CTRL_ACK_ACK // // Interrupt flag 8. BLE mode only: Acknowledgement received on a transmitted // LL control packet, and acknowledgement transmitted for that packet. Write // zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK 0x00000100 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_BITN 8 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_M 0x00000100 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_S 8 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_S 8 // Field: [7] TX_CTRL_ACK // // Interrupt flag 7. BLE mode: Acknowledgement received on a transmitted LL // control packet. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK 0x00000080 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_BITN 7 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_M 0x00000080 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_S 7 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_S 7 // Field: [6] TX_CTRL // // Interrupt flag 6. BLE mode: Transmitted LL control packet. Write zero to // clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_CTRL 0x00000040 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_BITN 6 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_M 0x00000040 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_S 6 +#define RFC_DBELL_RFCPEIFG_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEIFG_TX_CTRL_S 6 // Field: [5] TX_ACK // // Interrupt flag 5. BLE mode: Acknowledgement received on a transmitted // packet. IEEE 802.15.4 mode: Transmitted automatic ACK frame. Write zero to // clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_ACK 0x00000020 -#define RFC_DBELL_RFCPEIFG_TX_ACK_BITN 5 -#define RFC_DBELL_RFCPEIFG_TX_ACK_M 0x00000020 -#define RFC_DBELL_RFCPEIFG_TX_ACK_S 5 +#define RFC_DBELL_RFCPEIFG_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEIFG_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEIFG_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEIFG_TX_ACK_S 5 // Field: [4] TX_DONE // // Interrupt flag 4. Packet transmitted. (BLE mode: A packet has been // transmitted.) (IEEE 802.15.4 mode: A frame has been transmitted). Write zero // to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_DONE 0x00000010 -#define RFC_DBELL_RFCPEIFG_TX_DONE_BITN 4 -#define RFC_DBELL_RFCPEIFG_TX_DONE_M 0x00000010 -#define RFC_DBELL_RFCPEIFG_TX_DONE_S 4 +#define RFC_DBELL_RFCPEIFG_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEIFG_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEIFG_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEIFG_TX_DONE_S 4 // Field: [3] LAST_FG_COMMAND_DONE // // Interrupt flag 3. IEEE 802.15.4 mode only: The last foreground radio // operation command in a chain of commands has finished. Write zero to clear // flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE 0x00000008 -#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_BITN 3 -#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M 0x00000008 -#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_S 3 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_S 3 // Field: [2] FG_COMMAND_DONE // // Interrupt flag 2. IEEE 802.15.4 mode only: A foreground radio operation // command has finished. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE 0x00000004 -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_BITN 2 -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_M 0x00000004 -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_S 2 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_S 2 // Field: [1] LAST_COMMAND_DONE // @@ -703,20 +703,20 @@ // has finished. (IEEE 802.15.4 mode: The last background level radio operation // command in a chain of commands has finished.) Write zero to clear flag. // Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE 0x00000002 -#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_BITN 1 -#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M 0x00000002 -#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_S 1 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_S 1 // Field: [0] COMMAND_DONE // // Interrupt flag 0. A radio operation has finished. (IEEE 802.15.4 mode: A // background level radio operation command has finished.) Write zero to clear // flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_COMMAND_DONE 0x00000001 -#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_BITN 0 -#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_M 0x00000001 -#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_S 0 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_S 0 //***************************************************************************** // @@ -726,258 +726,258 @@ // Field: [31] INTERNAL_ERROR // // Interrupt enable for RFCPEIFG.INTERNAL_ERROR. -#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR 0x80000000 -#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_BITN 31 -#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_M 0x80000000 -#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_S 31 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_S 31 // Field: [30] BOOT_DONE // // Interrupt enable for RFCPEIFG.BOOT_DONE. -#define RFC_DBELL_RFCPEIEN_BOOT_DONE 0x40000000 -#define RFC_DBELL_RFCPEIEN_BOOT_DONE_BITN 30 -#define RFC_DBELL_RFCPEIEN_BOOT_DONE_M 0x40000000 -#define RFC_DBELL_RFCPEIEN_BOOT_DONE_S 30 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEIEN_BOOT_DONE_S 30 // Field: [29] MODULES_UNLOCKED // // Interrupt enable for RFCPEIFG.MODULES_UNLOCKED. -#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED 0x20000000 -#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_BITN 29 -#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_M 0x20000000 -#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_S 29 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_S 29 // Field: [28] SYNTH_NO_LOCK // // Interrupt enable for RFCPEIFG.SYNTH_NO_LOCK. -#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK 0x10000000 -#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_BITN 28 -#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_M 0x10000000 -#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_S 28 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_S 28 // Field: [27] IRQ27 // // Interrupt enable for RFCPEIFG.IRQ27. -#define RFC_DBELL_RFCPEIEN_IRQ27 0x08000000 -#define RFC_DBELL_RFCPEIEN_IRQ27_BITN 27 -#define RFC_DBELL_RFCPEIEN_IRQ27_M 0x08000000 -#define RFC_DBELL_RFCPEIEN_IRQ27_S 27 +#define RFC_DBELL_RFCPEIEN_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEIEN_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEIEN_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEIEN_IRQ27_S 27 // Field: [26] RX_ABORTED // // Interrupt enable for RFCPEIFG.RX_ABORTED. -#define RFC_DBELL_RFCPEIEN_RX_ABORTED 0x04000000 -#define RFC_DBELL_RFCPEIEN_RX_ABORTED_BITN 26 -#define RFC_DBELL_RFCPEIEN_RX_ABORTED_M 0x04000000 -#define RFC_DBELL_RFCPEIEN_RX_ABORTED_S 26 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEIEN_RX_ABORTED_S 26 // Field: [25] RX_N_DATA_WRITTEN // // Interrupt enable for RFCPEIFG.RX_N_DATA_WRITTEN. -#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN 0x02000000 -#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_BITN 25 -#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_M 0x02000000 -#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_S 25 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_S 25 // Field: [24] RX_DATA_WRITTEN // // Interrupt enable for RFCPEIFG.RX_DATA_WRITTEN. -#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN 0x01000000 -#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_BITN 24 -#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_M 0x01000000 -#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_S 24 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_S 24 // Field: [23] RX_ENTRY_DONE // // Interrupt enable for RFCPEIFG.RX_ENTRY_DONE. -#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE 0x00800000 -#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_BITN 23 -#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_M 0x00800000 -#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_S 23 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_S 23 // Field: [22] RX_BUF_FULL // // Interrupt enable for RFCPEIFG.RX_BUF_FULL. -#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL 0x00400000 -#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_BITN 22 -#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_M 0x00400000 -#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_S 22 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_S 22 // Field: [21] RX_CTRL_ACK // // Interrupt enable for RFCPEIFG.RX_CTRL_ACK. -#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK 0x00200000 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_BITN 21 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_M 0x00200000 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_S 21 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_S 21 // Field: [20] RX_CTRL // // Interrupt enable for RFCPEIFG.RX_CTRL. -#define RFC_DBELL_RFCPEIEN_RX_CTRL 0x00100000 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_BITN 20 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_M 0x00100000 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_S 20 +#define RFC_DBELL_RFCPEIEN_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEIEN_RX_CTRL_S 20 // Field: [19] RX_EMPTY // // Interrupt enable for RFCPEIFG.RX_EMPTY. -#define RFC_DBELL_RFCPEIEN_RX_EMPTY 0x00080000 -#define RFC_DBELL_RFCPEIEN_RX_EMPTY_BITN 19 -#define RFC_DBELL_RFCPEIEN_RX_EMPTY_M 0x00080000 -#define RFC_DBELL_RFCPEIEN_RX_EMPTY_S 19 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEIEN_RX_EMPTY_S 19 // Field: [18] RX_IGNORED // // Interrupt enable for RFCPEIFG.RX_IGNORED. -#define RFC_DBELL_RFCPEIEN_RX_IGNORED 0x00040000 -#define RFC_DBELL_RFCPEIEN_RX_IGNORED_BITN 18 -#define RFC_DBELL_RFCPEIEN_RX_IGNORED_M 0x00040000 -#define RFC_DBELL_RFCPEIEN_RX_IGNORED_S 18 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEIEN_RX_IGNORED_S 18 // Field: [17] RX_NOK // // Interrupt enable for RFCPEIFG.RX_NOK. -#define RFC_DBELL_RFCPEIEN_RX_NOK 0x00020000 -#define RFC_DBELL_RFCPEIEN_RX_NOK_BITN 17 -#define RFC_DBELL_RFCPEIEN_RX_NOK_M 0x00020000 -#define RFC_DBELL_RFCPEIEN_RX_NOK_S 17 +#define RFC_DBELL_RFCPEIEN_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEIEN_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEIEN_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEIEN_RX_NOK_S 17 // Field: [16] RX_OK // // Interrupt enable for RFCPEIFG.RX_OK. -#define RFC_DBELL_RFCPEIEN_RX_OK 0x00010000 -#define RFC_DBELL_RFCPEIEN_RX_OK_BITN 16 -#define RFC_DBELL_RFCPEIEN_RX_OK_M 0x00010000 -#define RFC_DBELL_RFCPEIEN_RX_OK_S 16 +#define RFC_DBELL_RFCPEIEN_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEIEN_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEIEN_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEIEN_RX_OK_S 16 // Field: [15] IRQ15 // // Interrupt enable for RFCPEIFG.IRQ15. -#define RFC_DBELL_RFCPEIEN_IRQ15 0x00008000 -#define RFC_DBELL_RFCPEIEN_IRQ15_BITN 15 -#define RFC_DBELL_RFCPEIEN_IRQ15_M 0x00008000 -#define RFC_DBELL_RFCPEIEN_IRQ15_S 15 +#define RFC_DBELL_RFCPEIEN_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEIEN_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEIEN_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEIEN_IRQ15_S 15 // Field: [14] IRQ14 // // Interrupt enable for RFCPEIFG.IRQ14. -#define RFC_DBELL_RFCPEIEN_IRQ14 0x00004000 -#define RFC_DBELL_RFCPEIEN_IRQ14_BITN 14 -#define RFC_DBELL_RFCPEIEN_IRQ14_M 0x00004000 -#define RFC_DBELL_RFCPEIEN_IRQ14_S 14 +#define RFC_DBELL_RFCPEIEN_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEIEN_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEIEN_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEIEN_IRQ14_S 14 // Field: [13] IRQ13 // // Interrupt enable for RFCPEIFG.IRQ13. -#define RFC_DBELL_RFCPEIEN_IRQ13 0x00002000 -#define RFC_DBELL_RFCPEIEN_IRQ13_BITN 13 -#define RFC_DBELL_RFCPEIEN_IRQ13_M 0x00002000 -#define RFC_DBELL_RFCPEIEN_IRQ13_S 13 +#define RFC_DBELL_RFCPEIEN_IRQ13 0x00002000 +#define RFC_DBELL_RFCPEIEN_IRQ13_BITN 13 +#define RFC_DBELL_RFCPEIEN_IRQ13_M 0x00002000 +#define RFC_DBELL_RFCPEIEN_IRQ13_S 13 // Field: [12] IRQ12 // // Interrupt enable for RFCPEIFG.IRQ12. -#define RFC_DBELL_RFCPEIEN_IRQ12 0x00001000 -#define RFC_DBELL_RFCPEIEN_IRQ12_BITN 12 -#define RFC_DBELL_RFCPEIEN_IRQ12_M 0x00001000 -#define RFC_DBELL_RFCPEIEN_IRQ12_S 12 +#define RFC_DBELL_RFCPEIEN_IRQ12 0x00001000 +#define RFC_DBELL_RFCPEIEN_IRQ12_BITN 12 +#define RFC_DBELL_RFCPEIEN_IRQ12_M 0x00001000 +#define RFC_DBELL_RFCPEIEN_IRQ12_S 12 // Field: [11] TX_BUFFER_CHANGED // // Interrupt enable for RFCPEIFG.TX_BUFFER_CHANGED. -#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED 0x00000800 -#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_BITN 11 -#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_M 0x00000800 -#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_S 11 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_S 11 // Field: [10] TX_ENTRY_DONE // // Interrupt enable for RFCPEIFG.TX_ENTRY_DONE. -#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE 0x00000400 -#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_BITN 10 -#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_M 0x00000400 -#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_S 10 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_S 10 // Field: [9] TX_RETRANS // // Interrupt enable for RFCPEIFG.TX_RETRANS. -#define RFC_DBELL_RFCPEIEN_TX_RETRANS 0x00000200 -#define RFC_DBELL_RFCPEIEN_TX_RETRANS_BITN 9 -#define RFC_DBELL_RFCPEIEN_TX_RETRANS_M 0x00000200 -#define RFC_DBELL_RFCPEIEN_TX_RETRANS_S 9 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEIEN_TX_RETRANS_S 9 // Field: [8] TX_CTRL_ACK_ACK // // Interrupt enable for RFCPEIFG.TX_CTRL_ACK_ACK. -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK 0x00000100 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_BITN 8 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_M 0x00000100 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_S 8 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_S 8 // Field: [7] TX_CTRL_ACK // // Interrupt enable for RFCPEIFG.TX_CTRL_ACK. -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK 0x00000080 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_BITN 7 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_M 0x00000080 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_S 7 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_S 7 // Field: [6] TX_CTRL // // Interrupt enable for RFCPEIFG.TX_CTRL. -#define RFC_DBELL_RFCPEIEN_TX_CTRL 0x00000040 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_BITN 6 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_M 0x00000040 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_S 6 +#define RFC_DBELL_RFCPEIEN_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEIEN_TX_CTRL_S 6 // Field: [5] TX_ACK // // Interrupt enable for RFCPEIFG.TX_ACK. -#define RFC_DBELL_RFCPEIEN_TX_ACK 0x00000020 -#define RFC_DBELL_RFCPEIEN_TX_ACK_BITN 5 -#define RFC_DBELL_RFCPEIEN_TX_ACK_M 0x00000020 -#define RFC_DBELL_RFCPEIEN_TX_ACK_S 5 +#define RFC_DBELL_RFCPEIEN_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEIEN_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEIEN_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEIEN_TX_ACK_S 5 // Field: [4] TX_DONE // // Interrupt enable for RFCPEIFG.TX_DONE. -#define RFC_DBELL_RFCPEIEN_TX_DONE 0x00000010 -#define RFC_DBELL_RFCPEIEN_TX_DONE_BITN 4 -#define RFC_DBELL_RFCPEIEN_TX_DONE_M 0x00000010 -#define RFC_DBELL_RFCPEIEN_TX_DONE_S 4 +#define RFC_DBELL_RFCPEIEN_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEIEN_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEIEN_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEIEN_TX_DONE_S 4 // Field: [3] LAST_FG_COMMAND_DONE // // Interrupt enable for RFCPEIFG.LAST_FG_COMMAND_DONE. -#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE 0x00000008 -#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_BITN 3 -#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_M 0x00000008 -#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_S 3 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_S 3 // Field: [2] FG_COMMAND_DONE // // Interrupt enable for RFCPEIFG.FG_COMMAND_DONE. -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE 0x00000004 -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_BITN 2 -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_M 0x00000004 -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_S 2 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_S 2 // Field: [1] LAST_COMMAND_DONE // // Interrupt enable for RFCPEIFG.LAST_COMMAND_DONE. -#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE 0x00000002 -#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_BITN 1 -#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_M 0x00000002 -#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_S 1 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_S 1 // Field: [0] COMMAND_DONE // // Interrupt enable for RFCPEIFG.COMMAND_DONE. -#define RFC_DBELL_RFCPEIEN_COMMAND_DONE 0x00000001 -#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_BITN 0 -#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_M 0x00000001 -#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_S 0 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_S 0 //***************************************************************************** // @@ -993,12 +993,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR 0x80000000 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_BITN 31 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_M 0x80000000 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_S 31 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE1 0x80000000 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_BITN 31 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_M 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_S 31 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE1 0x80000000 +#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE0 0x00000000 // Field: [30] BOOT_DONE // @@ -1009,12 +1009,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_BOOT_DONE 0x40000000 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_BITN 30 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_M 0x40000000 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_S 30 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE1 0x40000000 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_BITN 30 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_M 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_S 30 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE1 0x40000000 +#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE0 0x00000000 // Field: [29] MODULES_UNLOCKED // @@ -1025,12 +1025,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED 0x20000000 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_BITN 29 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_M 0x20000000 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_S 29 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE1 0x20000000 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_BITN 29 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_M 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_S 29 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE1 0x20000000 +#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE0 0x00000000 // Field: [28] SYNTH_NO_LOCK // @@ -1041,12 +1041,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK 0x10000000 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_BITN 28 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_M 0x10000000 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_S 28 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE1 0x10000000 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_BITN 28 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_M 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_S 28 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE1 0x10000000 +#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE0 0x00000000 // Field: [27] IRQ27 // @@ -1056,12 +1056,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_IRQ27 0x08000000 -#define RFC_DBELL_RFCPEISL_IRQ27_BITN 27 -#define RFC_DBELL_RFCPEISL_IRQ27_M 0x08000000 -#define RFC_DBELL_RFCPEISL_IRQ27_S 27 -#define RFC_DBELL_RFCPEISL_IRQ27_CPE1 0x08000000 -#define RFC_DBELL_RFCPEISL_IRQ27_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_IRQ27 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_BITN 27 +#define RFC_DBELL_RFCPEISL_IRQ27_M 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_S 27 +#define RFC_DBELL_RFCPEISL_IRQ27_CPE1 0x08000000 +#define RFC_DBELL_RFCPEISL_IRQ27_CPE0 0x00000000 // Field: [26] RX_ABORTED // @@ -1072,12 +1072,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_ABORTED 0x04000000 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_BITN 26 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_M 0x04000000 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_S 26 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE1 0x04000000 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_BITN 26 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_M 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_S 26 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE1 0x04000000 +#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE0 0x00000000 // Field: [25] RX_N_DATA_WRITTEN // @@ -1088,12 +1088,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN 0x02000000 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_BITN 25 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_M 0x02000000 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_S 25 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE1 0x02000000 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_BITN 25 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_M 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_S 25 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE1 0x02000000 +#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE0 0x00000000 // Field: [24] RX_DATA_WRITTEN // @@ -1104,12 +1104,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN 0x01000000 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_BITN 24 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_M 0x01000000 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_S 24 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE1 0x01000000 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_BITN 24 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_M 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_S 24 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE1 0x01000000 +#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE0 0x00000000 // Field: [23] RX_ENTRY_DONE // @@ -1120,12 +1120,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE 0x00800000 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_BITN 23 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_M 0x00800000 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_S 23 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE1 0x00800000 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_BITN 23 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_M 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_S 23 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE1 0x00800000 +#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE0 0x00000000 // Field: [22] RX_BUF_FULL // @@ -1136,12 +1136,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL 0x00400000 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_BITN 22 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_M 0x00400000 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_S 22 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE1 0x00400000 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_BITN 22 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_M 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_S 22 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE1 0x00400000 +#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE0 0x00000000 // Field: [21] RX_CTRL_ACK // @@ -1152,12 +1152,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK 0x00200000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_BITN 21 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_M 0x00200000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_S 21 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE1 0x00200000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_BITN 21 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_M 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_S 21 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE1 0x00200000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE0 0x00000000 // Field: [20] RX_CTRL // @@ -1167,12 +1167,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_CTRL 0x00100000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_BITN 20 -#define RFC_DBELL_RFCPEISL_RX_CTRL_M 0x00100000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_S 20 -#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE1 0x00100000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_CTRL 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_BITN 20 +#define RFC_DBELL_RFCPEISL_RX_CTRL_M 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_S 20 +#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE1 0x00100000 +#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE0 0x00000000 // Field: [19] RX_EMPTY // @@ -1183,12 +1183,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_EMPTY 0x00080000 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_BITN 19 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_M 0x00080000 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_S 19 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE1 0x00080000 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_BITN 19 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_M 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_S 19 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE1 0x00080000 +#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE0 0x00000000 // Field: [18] RX_IGNORED // @@ -1199,12 +1199,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_IGNORED 0x00040000 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_BITN 18 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_M 0x00040000 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_S 18 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE1 0x00040000 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_BITN 18 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_M 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_S 18 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE1 0x00040000 +#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE0 0x00000000 // Field: [17] RX_NOK // @@ -1214,12 +1214,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_NOK 0x00020000 -#define RFC_DBELL_RFCPEISL_RX_NOK_BITN 17 -#define RFC_DBELL_RFCPEISL_RX_NOK_M 0x00020000 -#define RFC_DBELL_RFCPEISL_RX_NOK_S 17 -#define RFC_DBELL_RFCPEISL_RX_NOK_CPE1 0x00020000 -#define RFC_DBELL_RFCPEISL_RX_NOK_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_NOK 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_BITN 17 +#define RFC_DBELL_RFCPEISL_RX_NOK_M 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_S 17 +#define RFC_DBELL_RFCPEISL_RX_NOK_CPE1 0x00020000 +#define RFC_DBELL_RFCPEISL_RX_NOK_CPE0 0x00000000 // Field: [16] RX_OK // @@ -1229,12 +1229,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_RX_OK 0x00010000 -#define RFC_DBELL_RFCPEISL_RX_OK_BITN 16 -#define RFC_DBELL_RFCPEISL_RX_OK_M 0x00010000 -#define RFC_DBELL_RFCPEISL_RX_OK_S 16 -#define RFC_DBELL_RFCPEISL_RX_OK_CPE1 0x00010000 -#define RFC_DBELL_RFCPEISL_RX_OK_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_RX_OK 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_BITN 16 +#define RFC_DBELL_RFCPEISL_RX_OK_M 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_S 16 +#define RFC_DBELL_RFCPEISL_RX_OK_CPE1 0x00010000 +#define RFC_DBELL_RFCPEISL_RX_OK_CPE0 0x00000000 // Field: [15] IRQ15 // @@ -1244,12 +1244,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_IRQ15 0x00008000 -#define RFC_DBELL_RFCPEISL_IRQ15_BITN 15 -#define RFC_DBELL_RFCPEISL_IRQ15_M 0x00008000 -#define RFC_DBELL_RFCPEISL_IRQ15_S 15 -#define RFC_DBELL_RFCPEISL_IRQ15_CPE1 0x00008000 -#define RFC_DBELL_RFCPEISL_IRQ15_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_IRQ15 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_BITN 15 +#define RFC_DBELL_RFCPEISL_IRQ15_M 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_S 15 +#define RFC_DBELL_RFCPEISL_IRQ15_CPE1 0x00008000 +#define RFC_DBELL_RFCPEISL_IRQ15_CPE0 0x00000000 // Field: [14] IRQ14 // @@ -1259,12 +1259,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_IRQ14 0x00004000 -#define RFC_DBELL_RFCPEISL_IRQ14_BITN 14 -#define RFC_DBELL_RFCPEISL_IRQ14_M 0x00004000 -#define RFC_DBELL_RFCPEISL_IRQ14_S 14 -#define RFC_DBELL_RFCPEISL_IRQ14_CPE1 0x00004000 -#define RFC_DBELL_RFCPEISL_IRQ14_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_IRQ14 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_BITN 14 +#define RFC_DBELL_RFCPEISL_IRQ14_M 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_S 14 +#define RFC_DBELL_RFCPEISL_IRQ14_CPE1 0x00004000 +#define RFC_DBELL_RFCPEISL_IRQ14_CPE0 0x00000000 // Field: [13] IRQ13 // @@ -1274,12 +1274,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_IRQ13 0x00002000 -#define RFC_DBELL_RFCPEISL_IRQ13_BITN 13 -#define RFC_DBELL_RFCPEISL_IRQ13_M 0x00002000 -#define RFC_DBELL_RFCPEISL_IRQ13_S 13 -#define RFC_DBELL_RFCPEISL_IRQ13_CPE1 0x00002000 -#define RFC_DBELL_RFCPEISL_IRQ13_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_IRQ13 0x00002000 +#define RFC_DBELL_RFCPEISL_IRQ13_BITN 13 +#define RFC_DBELL_RFCPEISL_IRQ13_M 0x00002000 +#define RFC_DBELL_RFCPEISL_IRQ13_S 13 +#define RFC_DBELL_RFCPEISL_IRQ13_CPE1 0x00002000 +#define RFC_DBELL_RFCPEISL_IRQ13_CPE0 0x00000000 // Field: [12] IRQ12 // @@ -1289,12 +1289,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_IRQ12 0x00001000 -#define RFC_DBELL_RFCPEISL_IRQ12_BITN 12 -#define RFC_DBELL_RFCPEISL_IRQ12_M 0x00001000 -#define RFC_DBELL_RFCPEISL_IRQ12_S 12 -#define RFC_DBELL_RFCPEISL_IRQ12_CPE1 0x00001000 -#define RFC_DBELL_RFCPEISL_IRQ12_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_IRQ12 0x00001000 +#define RFC_DBELL_RFCPEISL_IRQ12_BITN 12 +#define RFC_DBELL_RFCPEISL_IRQ12_M 0x00001000 +#define RFC_DBELL_RFCPEISL_IRQ12_S 12 +#define RFC_DBELL_RFCPEISL_IRQ12_CPE1 0x00001000 +#define RFC_DBELL_RFCPEISL_IRQ12_CPE0 0x00000000 // Field: [11] TX_BUFFER_CHANGED // @@ -1305,12 +1305,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED 0x00000800 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_BITN 11 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_M 0x00000800 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_S 11 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE1 0x00000800 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_BITN 11 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_M 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_S 11 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE1 0x00000800 +#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE0 0x00000000 // Field: [10] TX_ENTRY_DONE // @@ -1321,12 +1321,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE 0x00000400 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_BITN 10 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_M 0x00000400 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_S 10 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE1 0x00000400 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_BITN 10 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_M 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_S 10 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE1 0x00000400 +#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE0 0x00000000 // Field: [9] TX_RETRANS // @@ -1337,12 +1337,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_RETRANS 0x00000200 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_BITN 9 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_M 0x00000200 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_S 9 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE1 0x00000200 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_RETRANS 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_BITN 9 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_M 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_S 9 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE1 0x00000200 +#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE0 0x00000000 // Field: [8] TX_CTRL_ACK_ACK // @@ -1353,12 +1353,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK 0x00000100 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_BITN 8 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_M 0x00000100 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_S 8 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE1 0x00000100 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_BITN 8 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_M 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_S 8 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE1 0x00000100 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE0 0x00000000 // Field: [7] TX_CTRL_ACK // @@ -1369,12 +1369,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK 0x00000080 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_BITN 7 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_M 0x00000080 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_S 7 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE1 0x00000080 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_BITN 7 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_M 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_S 7 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE1 0x00000080 +#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE0 0x00000000 // Field: [6] TX_CTRL // @@ -1384,12 +1384,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_CTRL 0x00000040 -#define RFC_DBELL_RFCPEISL_TX_CTRL_BITN 6 -#define RFC_DBELL_RFCPEISL_TX_CTRL_M 0x00000040 -#define RFC_DBELL_RFCPEISL_TX_CTRL_S 6 -#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE1 0x00000040 -#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_CTRL 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_BITN 6 +#define RFC_DBELL_RFCPEISL_TX_CTRL_M 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_S 6 +#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE1 0x00000040 +#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE0 0x00000000 // Field: [5] TX_ACK // @@ -1399,12 +1399,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_ACK 0x00000020 -#define RFC_DBELL_RFCPEISL_TX_ACK_BITN 5 -#define RFC_DBELL_RFCPEISL_TX_ACK_M 0x00000020 -#define RFC_DBELL_RFCPEISL_TX_ACK_S 5 -#define RFC_DBELL_RFCPEISL_TX_ACK_CPE1 0x00000020 -#define RFC_DBELL_RFCPEISL_TX_ACK_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_ACK 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_BITN 5 +#define RFC_DBELL_RFCPEISL_TX_ACK_M 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_S 5 +#define RFC_DBELL_RFCPEISL_TX_ACK_CPE1 0x00000020 +#define RFC_DBELL_RFCPEISL_TX_ACK_CPE0 0x00000000 // Field: [4] TX_DONE // @@ -1414,12 +1414,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_TX_DONE 0x00000010 -#define RFC_DBELL_RFCPEISL_TX_DONE_BITN 4 -#define RFC_DBELL_RFCPEISL_TX_DONE_M 0x00000010 -#define RFC_DBELL_RFCPEISL_TX_DONE_S 4 -#define RFC_DBELL_RFCPEISL_TX_DONE_CPE1 0x00000010 -#define RFC_DBELL_RFCPEISL_TX_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_TX_DONE 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_BITN 4 +#define RFC_DBELL_RFCPEISL_TX_DONE_M 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_S 4 +#define RFC_DBELL_RFCPEISL_TX_DONE_CPE1 0x00000010 +#define RFC_DBELL_RFCPEISL_TX_DONE_CPE0 0x00000000 // Field: [3] LAST_FG_COMMAND_DONE // @@ -1430,12 +1430,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE 0x00000008 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_BITN 3 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_M 0x00000008 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_S 3 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE1 0x00000008 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_BITN 3 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_M 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_S 3 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE1 0x00000008 +#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE0 0x00000000 // Field: [2] FG_COMMAND_DONE // @@ -1446,12 +1446,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE 0x00000004 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_BITN 2 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_M 0x00000004 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_S 2 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE1 0x00000004 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_BITN 2 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_M 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_S 2 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE1 0x00000004 +#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE0 0x00000000 // Field: [1] LAST_COMMAND_DONE // @@ -1462,12 +1462,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE 0x00000002 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_BITN 1 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_M 0x00000002 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_S 1 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE1 0x00000002 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_BITN 1 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_M 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_S 1 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE1 0x00000002 +#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE0 0x00000000 // Field: [0] COMMAND_DONE // @@ -1478,12 +1478,12 @@ // interrupt vector // CPE0 Associate this interrupt line with INT_RF_CPE0 // interrupt vector -#define RFC_DBELL_RFCPEISL_COMMAND_DONE 0x00000001 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_BITN 0 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_M 0x00000001 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_S 0 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE1 0x00000001 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE0 0x00000000 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_BITN 0 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_M 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_S 0 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE1 0x00000001 +#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE0 0x00000000 //***************************************************************************** // @@ -1493,10 +1493,10 @@ // Field: [0] ACKFLAG // // Interrupt flag for Command ACK -#define RFC_DBELL_RFACKIFG_ACKFLAG 0x00000001 -#define RFC_DBELL_RFACKIFG_ACKFLAG_BITN 0 -#define RFC_DBELL_RFACKIFG_ACKFLAG_M 0x00000001 -#define RFC_DBELL_RFACKIFG_ACKFLAG_S 0 +#define RFC_DBELL_RFACKIFG_ACKFLAG 0x00000001 +#define RFC_DBELL_RFACKIFG_ACKFLAG_BITN 0 +#define RFC_DBELL_RFACKIFG_ACKFLAG_M 0x00000001 +#define RFC_DBELL_RFACKIFG_ACKFLAG_S 0 //***************************************************************************** // @@ -1524,25 +1524,25 @@ // CPEGPO2 CPE GPO line 2 // CPEGPO1 CPE GPO line 1 // CPEGPO0 CPE GPO line 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_W 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_M 0x0000F000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_S 12 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO3 0x0000F000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO2 0x0000E000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO1 0x0000D000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO0 0x0000C000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO3 0x0000B000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO2 0x0000A000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO1 0x00009000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO0 0x00008000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO3 0x00007000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO2 0x00006000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO1 0x00005000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO0 0x00004000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO3 0x00003000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO2 0x00002000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO1 0x00001000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO0 0x00000000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_M 0x0000F000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_S 12 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO3 0x0000F000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO2 0x0000E000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO1 0x0000D000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO0 0x0000C000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO3 0x0000B000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO2 0x0000A000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO1 0x00009000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO0 0x00008000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO3 0x00007000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO2 0x00006000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO1 0x00005000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO0 0x00004000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO3 0x00003000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO2 0x00002000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO1 0x00001000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO0 0x00000000 // Field: [11:8] GPOCTL2 // @@ -1565,25 +1565,25 @@ // CPEGPO2 CPE GPO line 2 // CPEGPO1 CPE GPO line 1 // CPEGPO0 CPE GPO line 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_W 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_M 0x00000F00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_S 8 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO3 0x00000F00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO2 0x00000E00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO1 0x00000D00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO0 0x00000C00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO3 0x00000B00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO2 0x00000A00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO1 0x00000900 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO0 0x00000800 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO3 0x00000700 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO2 0x00000600 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO1 0x00000500 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO0 0x00000400 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO3 0x00000300 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO2 0x00000200 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO1 0x00000100 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO0 0x00000000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_M 0x00000F00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_S 8 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO3 0x00000F00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO2 0x00000E00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO1 0x00000D00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO0 0x00000C00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO3 0x00000B00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO2 0x00000A00 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO1 0x00000900 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO0 0x00000800 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO3 0x00000700 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO2 0x00000600 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO1 0x00000500 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO0 0x00000400 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO3 0x00000300 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO2 0x00000200 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO1 0x00000100 +#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO0 0x00000000 // Field: [7:4] GPOCTL1 // @@ -1606,25 +1606,25 @@ // CPEGPO2 CPE GPO line 2 // CPEGPO1 CPE GPO line 1 // CPEGPO0 CPE GPO line 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_W 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_M 0x000000F0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_S 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO3 0x000000F0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO2 0x000000E0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO1 0x000000D0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO0 0x000000C0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO3 0x000000B0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO2 0x000000A0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO1 0x00000090 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO0 0x00000080 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO3 0x00000070 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO2 0x00000060 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO1 0x00000050 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO0 0x00000040 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO3 0x00000030 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO2 0x00000020 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO1 0x00000010 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO0 0x00000000 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_M 0x000000F0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_S 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO3 0x000000F0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO2 0x000000E0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO1 0x000000D0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO0 0x000000C0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO3 0x000000B0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO2 0x000000A0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO1 0x00000090 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO0 0x00000080 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO3 0x00000070 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO2 0x00000060 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO1 0x00000050 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO0 0x00000040 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO3 0x00000030 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO2 0x00000020 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO1 0x00000010 +#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO0 0x00000000 // Field: [3:0] GPOCTL0 // @@ -1647,25 +1647,24 @@ // CPEGPO2 CPE GPO line 2 // CPEGPO1 CPE GPO line 1 // CPEGPO0 CPE GPO line 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_W 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_M 0x0000000F -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_S 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO3 0x0000000F -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO2 0x0000000E -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO1 0x0000000D -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO0 0x0000000C -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO3 0x0000000B -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO2 0x0000000A -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO1 0x00000009 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO0 0x00000008 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO3 0x00000007 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO2 0x00000006 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO1 0x00000005 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO0 0x00000004 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO3 0x00000003 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO2 0x00000002 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO1 0x00000001 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO0 0x00000000 - +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_W 4 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_M 0x0000000F +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_S 0 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO3 0x0000000F +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO2 0x0000000E +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO1 0x0000000D +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO0 0x0000000C +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO3 0x0000000B +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO2 0x0000000A +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO1 0x00000009 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO0 0x00000008 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO3 0x00000007 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO2 0x00000006 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO1 0x00000005 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO0 0x00000004 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO3 0x00000003 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO2 0x00000002 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO1 0x00000001 +#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO0 0x00000000 #endif // __RFC_DBELL__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_rfc_pwr.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_rfc_pwr.h index ad91fb3..1856b2e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_rfc_pwr.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_rfc_pwr.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_rfc_pwr_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_rfc_pwr_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_RFC_PWR_H__ #define __HW_RFC_PWR_H__ @@ -44,7 +44,7 @@ // //***************************************************************************** // RF Core Power Management and Clock Enable -#define RFC_PWR_O_PWMCLKEN 0x00000000 +#define RFC_PWR_O_PWMCLKEN 0x00000000 //***************************************************************************** // @@ -54,87 +54,87 @@ // Field: [10] RFCTRC // // Enable clock to the RF Core Tracer (RFCTRC) module. -#define RFC_PWR_PWMCLKEN_RFCTRC 0x00000400 -#define RFC_PWR_PWMCLKEN_RFCTRC_BITN 10 -#define RFC_PWR_PWMCLKEN_RFCTRC_M 0x00000400 -#define RFC_PWR_PWMCLKEN_RFCTRC_S 10 +#define RFC_PWR_PWMCLKEN_RFCTRC 0x00000400 +#define RFC_PWR_PWMCLKEN_RFCTRC_BITN 10 +#define RFC_PWR_PWMCLKEN_RFCTRC_M 0x00000400 +#define RFC_PWR_PWMCLKEN_RFCTRC_S 10 // Field: [9] FSCA // // Enable clock to the Frequency Synthesizer Calibration Accelerator (FSCA) // module. -#define RFC_PWR_PWMCLKEN_FSCA 0x00000200 -#define RFC_PWR_PWMCLKEN_FSCA_BITN 9 -#define RFC_PWR_PWMCLKEN_FSCA_M 0x00000200 -#define RFC_PWR_PWMCLKEN_FSCA_S 9 +#define RFC_PWR_PWMCLKEN_FSCA 0x00000200 +#define RFC_PWR_PWMCLKEN_FSCA_BITN 9 +#define RFC_PWR_PWMCLKEN_FSCA_M 0x00000200 +#define RFC_PWR_PWMCLKEN_FSCA_S 9 // Field: [8] PHA // // Enable clock to the Packet Handling Accelerator (PHA) module. -#define RFC_PWR_PWMCLKEN_PHA 0x00000100 -#define RFC_PWR_PWMCLKEN_PHA_BITN 8 -#define RFC_PWR_PWMCLKEN_PHA_M 0x00000100 -#define RFC_PWR_PWMCLKEN_PHA_S 8 +#define RFC_PWR_PWMCLKEN_PHA 0x00000100 +#define RFC_PWR_PWMCLKEN_PHA_BITN 8 +#define RFC_PWR_PWMCLKEN_PHA_M 0x00000100 +#define RFC_PWR_PWMCLKEN_PHA_S 8 // Field: [7] RAT // // Enable clock to the Radio Timer (RAT) module. -#define RFC_PWR_PWMCLKEN_RAT 0x00000080 -#define RFC_PWR_PWMCLKEN_RAT_BITN 7 -#define RFC_PWR_PWMCLKEN_RAT_M 0x00000080 -#define RFC_PWR_PWMCLKEN_RAT_S 7 +#define RFC_PWR_PWMCLKEN_RAT 0x00000080 +#define RFC_PWR_PWMCLKEN_RAT_BITN 7 +#define RFC_PWR_PWMCLKEN_RAT_M 0x00000080 +#define RFC_PWR_PWMCLKEN_RAT_S 7 // Field: [6] RFERAM // // Enable clock to the RF Engine RAM module. -#define RFC_PWR_PWMCLKEN_RFERAM 0x00000040 -#define RFC_PWR_PWMCLKEN_RFERAM_BITN 6 -#define RFC_PWR_PWMCLKEN_RFERAM_M 0x00000040 -#define RFC_PWR_PWMCLKEN_RFERAM_S 6 +#define RFC_PWR_PWMCLKEN_RFERAM 0x00000040 +#define RFC_PWR_PWMCLKEN_RFERAM_BITN 6 +#define RFC_PWR_PWMCLKEN_RFERAM_M 0x00000040 +#define RFC_PWR_PWMCLKEN_RFERAM_S 6 // Field: [5] RFE // // Enable clock to the RF Engine (RFE) module. -#define RFC_PWR_PWMCLKEN_RFE 0x00000020 -#define RFC_PWR_PWMCLKEN_RFE_BITN 5 -#define RFC_PWR_PWMCLKEN_RFE_M 0x00000020 -#define RFC_PWR_PWMCLKEN_RFE_S 5 +#define RFC_PWR_PWMCLKEN_RFE 0x00000020 +#define RFC_PWR_PWMCLKEN_RFE_BITN 5 +#define RFC_PWR_PWMCLKEN_RFE_M 0x00000020 +#define RFC_PWR_PWMCLKEN_RFE_S 5 // Field: [4] MDMRAM // // Enable clock to the Modem RAM module. -#define RFC_PWR_PWMCLKEN_MDMRAM 0x00000010 -#define RFC_PWR_PWMCLKEN_MDMRAM_BITN 4 -#define RFC_PWR_PWMCLKEN_MDMRAM_M 0x00000010 -#define RFC_PWR_PWMCLKEN_MDMRAM_S 4 +#define RFC_PWR_PWMCLKEN_MDMRAM 0x00000010 +#define RFC_PWR_PWMCLKEN_MDMRAM_BITN 4 +#define RFC_PWR_PWMCLKEN_MDMRAM_M 0x00000010 +#define RFC_PWR_PWMCLKEN_MDMRAM_S 4 // Field: [3] MDM // // Enable clock to the Modem (MDM) module. -#define RFC_PWR_PWMCLKEN_MDM 0x00000008 -#define RFC_PWR_PWMCLKEN_MDM_BITN 3 -#define RFC_PWR_PWMCLKEN_MDM_M 0x00000008 -#define RFC_PWR_PWMCLKEN_MDM_S 3 +#define RFC_PWR_PWMCLKEN_MDM 0x00000008 +#define RFC_PWR_PWMCLKEN_MDM_BITN 3 +#define RFC_PWR_PWMCLKEN_MDM_M 0x00000008 +#define RFC_PWR_PWMCLKEN_MDM_S 3 // Field: [2] CPERAM // // Enable clock to the Command and Packet Engine (CPE) RAM module. As part of // RF Core initialization, set this bit together with CPE bit to enable CPE to // boot. -#define RFC_PWR_PWMCLKEN_CPERAM 0x00000004 -#define RFC_PWR_PWMCLKEN_CPERAM_BITN 2 -#define RFC_PWR_PWMCLKEN_CPERAM_M 0x00000004 -#define RFC_PWR_PWMCLKEN_CPERAM_S 2 +#define RFC_PWR_PWMCLKEN_CPERAM 0x00000004 +#define RFC_PWR_PWMCLKEN_CPERAM_BITN 2 +#define RFC_PWR_PWMCLKEN_CPERAM_M 0x00000004 +#define RFC_PWR_PWMCLKEN_CPERAM_S 2 // Field: [1] CPE // // Enable processor clock (hclk) to the Command and Packet Engine (CPE). As // part of RF Core initialization, set this bit together with CPERAM bit to // enable CPE to boot. -#define RFC_PWR_PWMCLKEN_CPE 0x00000002 -#define RFC_PWR_PWMCLKEN_CPE_BITN 1 -#define RFC_PWR_PWMCLKEN_CPE_M 0x00000002 -#define RFC_PWR_PWMCLKEN_CPE_S 1 +#define RFC_PWR_PWMCLKEN_CPE 0x00000002 +#define RFC_PWR_PWMCLKEN_CPE_BITN 1 +#define RFC_PWR_PWMCLKEN_CPE_M 0x00000002 +#define RFC_PWR_PWMCLKEN_CPE_S 1 // Field: [0] RFC // @@ -144,10 +144,9 @@ // remove possibility of locking yourself out from the RF Core, this bit can // not be cleared. If you need to disable all clocks to the RF Core, see the // PRCM:RFCCLKG.CLK_EN register. -#define RFC_PWR_PWMCLKEN_RFC 0x00000001 -#define RFC_PWR_PWMCLKEN_RFC_BITN 0 -#define RFC_PWR_PWMCLKEN_RFC_M 0x00000001 -#define RFC_PWR_PWMCLKEN_RFC_S 0 - +#define RFC_PWR_PWMCLKEN_RFC 0x00000001 +#define RFC_PWR_PWMCLKEN_RFC_BITN 0 +#define RFC_PWR_PWMCLKEN_RFC_M 0x00000001 +#define RFC_PWR_PWMCLKEN_RFC_S 0 #endif // __RFC_PWR__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_rfc_rat.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_rfc_rat.h index 83f131c..35e8f17 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_rfc_rat.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_rfc_rat.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_rfc_rat_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_rfc_rat_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_RFC_RAT_H__ #define __HW_RFC_RAT_H__ @@ -44,31 +44,31 @@ // //***************************************************************************** // Radio Timer Counter Value -#define RFC_RAT_O_RATCNT 0x00000004 +#define RFC_RAT_O_RATCNT 0x00000004 // Timer Channel 0 Capture/Compare Register -#define RFC_RAT_O_RATCH0VAL 0x00000080 +#define RFC_RAT_O_RATCH0VAL 0x00000080 // Timer Channel 1 Capture/Compare Register -#define RFC_RAT_O_RATCH1VAL 0x00000084 +#define RFC_RAT_O_RATCH1VAL 0x00000084 // Timer Channel 2 Capture/Compare Register -#define RFC_RAT_O_RATCH2VAL 0x00000088 +#define RFC_RAT_O_RATCH2VAL 0x00000088 // Timer Channel 3 Capture/Compare Register -#define RFC_RAT_O_RATCH3VAL 0x0000008C +#define RFC_RAT_O_RATCH3VAL 0x0000008C // Timer Channel 4 Capture/Compare Register -#define RFC_RAT_O_RATCH4VAL 0x00000090 +#define RFC_RAT_O_RATCH4VAL 0x00000090 // Timer Channel 5 Capture/Compare Register -#define RFC_RAT_O_RATCH5VAL 0x00000094 +#define RFC_RAT_O_RATCH5VAL 0x00000094 // Timer Channel 6 Capture/Compare Register -#define RFC_RAT_O_RATCH6VAL 0x00000098 +#define RFC_RAT_O_RATCH6VAL 0x00000098 // Timer Channel 7 Capture/Compare Register -#define RFC_RAT_O_RATCH7VAL 0x0000009C +#define RFC_RAT_O_RATCH7VAL 0x0000009C //***************************************************************************** // @@ -78,9 +78,9 @@ // Field: [31:0] CNT // // Counter value. This is not writable while radio timer counter is enabled. -#define RFC_RAT_RATCNT_CNT_W 32 -#define RFC_RAT_RATCNT_CNT_M 0xFFFFFFFF -#define RFC_RAT_RATCNT_CNT_S 0 +#define RFC_RAT_RATCNT_CNT_W 32 +#define RFC_RAT_RATCNT_CNT_M 0xFFFFFFFF +#define RFC_RAT_RATCNT_CNT_S 0 //***************************************************************************** // @@ -91,9 +91,9 @@ // // Capture/compare value. The system CPU can safely read this register, but it // is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH0VAL_VAL_W 32 -#define RFC_RAT_RATCH0VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH0VAL_VAL_S 0 +#define RFC_RAT_RATCH0VAL_VAL_W 32 +#define RFC_RAT_RATCH0VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH0VAL_VAL_S 0 //***************************************************************************** // @@ -104,9 +104,9 @@ // // Capture/compare value. The system CPU can safely read this register, but it // is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH1VAL_VAL_W 32 -#define RFC_RAT_RATCH1VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH1VAL_VAL_S 0 +#define RFC_RAT_RATCH1VAL_VAL_W 32 +#define RFC_RAT_RATCH1VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH1VAL_VAL_S 0 //***************************************************************************** // @@ -117,9 +117,9 @@ // // Capture/compare value. The system CPU can safely read this register, but it // is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH2VAL_VAL_W 32 -#define RFC_RAT_RATCH2VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH2VAL_VAL_S 0 +#define RFC_RAT_RATCH2VAL_VAL_W 32 +#define RFC_RAT_RATCH2VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH2VAL_VAL_S 0 //***************************************************************************** // @@ -130,9 +130,9 @@ // // Capture/compare value. The system CPU can safely read this register, but it // is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH3VAL_VAL_W 32 -#define RFC_RAT_RATCH3VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH3VAL_VAL_S 0 +#define RFC_RAT_RATCH3VAL_VAL_W 32 +#define RFC_RAT_RATCH3VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH3VAL_VAL_S 0 //***************************************************************************** // @@ -143,9 +143,9 @@ // // Capture/compare value. The system CPU can safely read this register, but it // is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH4VAL_VAL_W 32 -#define RFC_RAT_RATCH4VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH4VAL_VAL_S 0 +#define RFC_RAT_RATCH4VAL_VAL_W 32 +#define RFC_RAT_RATCH4VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH4VAL_VAL_S 0 //***************************************************************************** // @@ -156,9 +156,9 @@ // // Capture/compare value. The system CPU can safely read this register, but it // is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH5VAL_VAL_W 32 -#define RFC_RAT_RATCH5VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH5VAL_VAL_S 0 +#define RFC_RAT_RATCH5VAL_VAL_W 32 +#define RFC_RAT_RATCH5VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH5VAL_VAL_S 0 //***************************************************************************** // @@ -169,9 +169,9 @@ // // Capture/compare value. The system CPU can safely read this register, but it // is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH6VAL_VAL_W 32 -#define RFC_RAT_RATCH6VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH6VAL_VAL_S 0 +#define RFC_RAT_RATCH6VAL_VAL_W 32 +#define RFC_RAT_RATCH6VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH6VAL_VAL_S 0 //***************************************************************************** // @@ -182,9 +182,8 @@ // // Capture/compare value. The system CPU can safely read this register, but it // is recommended to use the CPE API commands to configure it for compare mode. -#define RFC_RAT_RATCH7VAL_VAL_W 32 -#define RFC_RAT_RATCH7VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH7VAL_VAL_S 0 - +#define RFC_RAT_RATCH7VAL_VAL_W 32 +#define RFC_RAT_RATCH7VAL_VAL_M 0xFFFFFFFF +#define RFC_RAT_RATCH7VAL_VAL_S 0 #endif // __RFC_RAT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_smph.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_smph.h index 669eb26..38487b4 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_smph.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_smph.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_smph_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_smph_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_SMPH_H__ #define __HW_SMPH_H__ @@ -44,196 +44,196 @@ // //***************************************************************************** // MCU SEMAPHORE 0 -#define SMPH_O_SMPH0 0x00000000 +#define SMPH_O_SMPH0 0x00000000 // MCU SEMAPHORE 1 -#define SMPH_O_SMPH1 0x00000004 +#define SMPH_O_SMPH1 0x00000004 // MCU SEMAPHORE 2 -#define SMPH_O_SMPH2 0x00000008 +#define SMPH_O_SMPH2 0x00000008 // MCU SEMAPHORE 3 -#define SMPH_O_SMPH3 0x0000000C +#define SMPH_O_SMPH3 0x0000000C // MCU SEMAPHORE 4 -#define SMPH_O_SMPH4 0x00000010 +#define SMPH_O_SMPH4 0x00000010 // MCU SEMAPHORE 5 -#define SMPH_O_SMPH5 0x00000014 +#define SMPH_O_SMPH5 0x00000014 // MCU SEMAPHORE 6 -#define SMPH_O_SMPH6 0x00000018 +#define SMPH_O_SMPH6 0x00000018 // MCU SEMAPHORE 7 -#define SMPH_O_SMPH7 0x0000001C +#define SMPH_O_SMPH7 0x0000001C // MCU SEMAPHORE 8 -#define SMPH_O_SMPH8 0x00000020 +#define SMPH_O_SMPH8 0x00000020 // MCU SEMAPHORE 9 -#define SMPH_O_SMPH9 0x00000024 +#define SMPH_O_SMPH9 0x00000024 // MCU SEMAPHORE 10 -#define SMPH_O_SMPH10 0x00000028 +#define SMPH_O_SMPH10 0x00000028 // MCU SEMAPHORE 11 -#define SMPH_O_SMPH11 0x0000002C +#define SMPH_O_SMPH11 0x0000002C // MCU SEMAPHORE 12 -#define SMPH_O_SMPH12 0x00000030 +#define SMPH_O_SMPH12 0x00000030 // MCU SEMAPHORE 13 -#define SMPH_O_SMPH13 0x00000034 +#define SMPH_O_SMPH13 0x00000034 // MCU SEMAPHORE 14 -#define SMPH_O_SMPH14 0x00000038 +#define SMPH_O_SMPH14 0x00000038 // MCU SEMAPHORE 15 -#define SMPH_O_SMPH15 0x0000003C +#define SMPH_O_SMPH15 0x0000003C // MCU SEMAPHORE 16 -#define SMPH_O_SMPH16 0x00000040 +#define SMPH_O_SMPH16 0x00000040 // MCU SEMAPHORE 17 -#define SMPH_O_SMPH17 0x00000044 +#define SMPH_O_SMPH17 0x00000044 // MCU SEMAPHORE 18 -#define SMPH_O_SMPH18 0x00000048 +#define SMPH_O_SMPH18 0x00000048 // MCU SEMAPHORE 19 -#define SMPH_O_SMPH19 0x0000004C +#define SMPH_O_SMPH19 0x0000004C // MCU SEMAPHORE 20 -#define SMPH_O_SMPH20 0x00000050 +#define SMPH_O_SMPH20 0x00000050 // MCU SEMAPHORE 21 -#define SMPH_O_SMPH21 0x00000054 +#define SMPH_O_SMPH21 0x00000054 // MCU SEMAPHORE 22 -#define SMPH_O_SMPH22 0x00000058 +#define SMPH_O_SMPH22 0x00000058 // MCU SEMAPHORE 23 -#define SMPH_O_SMPH23 0x0000005C +#define SMPH_O_SMPH23 0x0000005C // MCU SEMAPHORE 24 -#define SMPH_O_SMPH24 0x00000060 +#define SMPH_O_SMPH24 0x00000060 // MCU SEMAPHORE 25 -#define SMPH_O_SMPH25 0x00000064 +#define SMPH_O_SMPH25 0x00000064 // MCU SEMAPHORE 26 -#define SMPH_O_SMPH26 0x00000068 +#define SMPH_O_SMPH26 0x00000068 // MCU SEMAPHORE 27 -#define SMPH_O_SMPH27 0x0000006C +#define SMPH_O_SMPH27 0x0000006C // MCU SEMAPHORE 28 -#define SMPH_O_SMPH28 0x00000070 +#define SMPH_O_SMPH28 0x00000070 // MCU SEMAPHORE 29 -#define SMPH_O_SMPH29 0x00000074 +#define SMPH_O_SMPH29 0x00000074 // MCU SEMAPHORE 30 -#define SMPH_O_SMPH30 0x00000078 +#define SMPH_O_SMPH30 0x00000078 // MCU SEMAPHORE 31 -#define SMPH_O_SMPH31 0x0000007C +#define SMPH_O_SMPH31 0x0000007C // MCU SEMAPHORE 0 ALIAS -#define SMPH_O_PEEK0 0x00000800 +#define SMPH_O_PEEK0 0x00000800 // MCU SEMAPHORE 1 ALIAS -#define SMPH_O_PEEK1 0x00000804 +#define SMPH_O_PEEK1 0x00000804 // MCU SEMAPHORE 2 ALIAS -#define SMPH_O_PEEK2 0x00000808 +#define SMPH_O_PEEK2 0x00000808 // MCU SEMAPHORE 3 ALIAS -#define SMPH_O_PEEK3 0x0000080C +#define SMPH_O_PEEK3 0x0000080C // MCU SEMAPHORE 4 ALIAS -#define SMPH_O_PEEK4 0x00000810 +#define SMPH_O_PEEK4 0x00000810 // MCU SEMAPHORE 5 ALIAS -#define SMPH_O_PEEK5 0x00000814 +#define SMPH_O_PEEK5 0x00000814 // MCU SEMAPHORE 6 ALIAS -#define SMPH_O_PEEK6 0x00000818 +#define SMPH_O_PEEK6 0x00000818 // MCU SEMAPHORE 7 ALIAS -#define SMPH_O_PEEK7 0x0000081C +#define SMPH_O_PEEK7 0x0000081C // MCU SEMAPHORE 8 ALIAS -#define SMPH_O_PEEK8 0x00000820 +#define SMPH_O_PEEK8 0x00000820 // MCU SEMAPHORE 9 ALIAS -#define SMPH_O_PEEK9 0x00000824 +#define SMPH_O_PEEK9 0x00000824 // MCU SEMAPHORE 10 ALIAS -#define SMPH_O_PEEK10 0x00000828 +#define SMPH_O_PEEK10 0x00000828 // MCU SEMAPHORE 11 ALIAS -#define SMPH_O_PEEK11 0x0000082C +#define SMPH_O_PEEK11 0x0000082C // MCU SEMAPHORE 12 ALIAS -#define SMPH_O_PEEK12 0x00000830 +#define SMPH_O_PEEK12 0x00000830 // MCU SEMAPHORE 13 ALIAS -#define SMPH_O_PEEK13 0x00000834 +#define SMPH_O_PEEK13 0x00000834 // MCU SEMAPHORE 14 ALIAS -#define SMPH_O_PEEK14 0x00000838 +#define SMPH_O_PEEK14 0x00000838 // MCU SEMAPHORE 15 ALIAS -#define SMPH_O_PEEK15 0x0000083C +#define SMPH_O_PEEK15 0x0000083C // MCU SEMAPHORE 16 ALIAS -#define SMPH_O_PEEK16 0x00000840 +#define SMPH_O_PEEK16 0x00000840 // MCU SEMAPHORE 17 ALIAS -#define SMPH_O_PEEK17 0x00000844 +#define SMPH_O_PEEK17 0x00000844 // MCU SEMAPHORE 18 ALIAS -#define SMPH_O_PEEK18 0x00000848 +#define SMPH_O_PEEK18 0x00000848 // MCU SEMAPHORE 19 ALIAS -#define SMPH_O_PEEK19 0x0000084C +#define SMPH_O_PEEK19 0x0000084C // MCU SEMAPHORE 20 ALIAS -#define SMPH_O_PEEK20 0x00000850 +#define SMPH_O_PEEK20 0x00000850 // MCU SEMAPHORE 21 ALIAS -#define SMPH_O_PEEK21 0x00000854 +#define SMPH_O_PEEK21 0x00000854 // MCU SEMAPHORE 22 ALIAS -#define SMPH_O_PEEK22 0x00000858 +#define SMPH_O_PEEK22 0x00000858 // MCU SEMAPHORE 23 ALIAS -#define SMPH_O_PEEK23 0x0000085C +#define SMPH_O_PEEK23 0x0000085C // MCU SEMAPHORE 24 ALIAS -#define SMPH_O_PEEK24 0x00000860 +#define SMPH_O_PEEK24 0x00000860 // MCU SEMAPHORE 25 ALIAS -#define SMPH_O_PEEK25 0x00000864 +#define SMPH_O_PEEK25 0x00000864 // MCU SEMAPHORE 26 ALIAS -#define SMPH_O_PEEK26 0x00000868 +#define SMPH_O_PEEK26 0x00000868 // MCU SEMAPHORE 27 ALIAS -#define SMPH_O_PEEK27 0x0000086C +#define SMPH_O_PEEK27 0x0000086C // MCU SEMAPHORE 28 ALIAS -#define SMPH_O_PEEK28 0x00000870 +#define SMPH_O_PEEK28 0x00000870 // MCU SEMAPHORE 29 ALIAS -#define SMPH_O_PEEK29 0x00000874 +#define SMPH_O_PEEK29 0x00000874 // MCU SEMAPHORE 30 ALIAS -#define SMPH_O_PEEK30 0x00000878 +#define SMPH_O_PEEK30 0x00000878 // MCU SEMAPHORE 31 ALIAS -#define SMPH_O_PEEK31 0x0000087C +#define SMPH_O_PEEK31 0x0000087C //***************************************************************************** // @@ -249,10 +249,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH0_STAT 0x00000001 -#define SMPH_SMPH0_STAT_BITN 0 -#define SMPH_SMPH0_STAT_M 0x00000001 -#define SMPH_SMPH0_STAT_S 0 +#define SMPH_SMPH0_STAT 0x00000001 +#define SMPH_SMPH0_STAT_BITN 0 +#define SMPH_SMPH0_STAT_M 0x00000001 +#define SMPH_SMPH0_STAT_S 0 //***************************************************************************** // @@ -268,10 +268,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH1_STAT 0x00000001 -#define SMPH_SMPH1_STAT_BITN 0 -#define SMPH_SMPH1_STAT_M 0x00000001 -#define SMPH_SMPH1_STAT_S 0 +#define SMPH_SMPH1_STAT 0x00000001 +#define SMPH_SMPH1_STAT_BITN 0 +#define SMPH_SMPH1_STAT_M 0x00000001 +#define SMPH_SMPH1_STAT_S 0 //***************************************************************************** // @@ -287,10 +287,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH2_STAT 0x00000001 -#define SMPH_SMPH2_STAT_BITN 0 -#define SMPH_SMPH2_STAT_M 0x00000001 -#define SMPH_SMPH2_STAT_S 0 +#define SMPH_SMPH2_STAT 0x00000001 +#define SMPH_SMPH2_STAT_BITN 0 +#define SMPH_SMPH2_STAT_M 0x00000001 +#define SMPH_SMPH2_STAT_S 0 //***************************************************************************** // @@ -306,10 +306,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH3_STAT 0x00000001 -#define SMPH_SMPH3_STAT_BITN 0 -#define SMPH_SMPH3_STAT_M 0x00000001 -#define SMPH_SMPH3_STAT_S 0 +#define SMPH_SMPH3_STAT 0x00000001 +#define SMPH_SMPH3_STAT_BITN 0 +#define SMPH_SMPH3_STAT_M 0x00000001 +#define SMPH_SMPH3_STAT_S 0 //***************************************************************************** // @@ -325,10 +325,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH4_STAT 0x00000001 -#define SMPH_SMPH4_STAT_BITN 0 -#define SMPH_SMPH4_STAT_M 0x00000001 -#define SMPH_SMPH4_STAT_S 0 +#define SMPH_SMPH4_STAT 0x00000001 +#define SMPH_SMPH4_STAT_BITN 0 +#define SMPH_SMPH4_STAT_M 0x00000001 +#define SMPH_SMPH4_STAT_S 0 //***************************************************************************** // @@ -344,10 +344,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH5_STAT 0x00000001 -#define SMPH_SMPH5_STAT_BITN 0 -#define SMPH_SMPH5_STAT_M 0x00000001 -#define SMPH_SMPH5_STAT_S 0 +#define SMPH_SMPH5_STAT 0x00000001 +#define SMPH_SMPH5_STAT_BITN 0 +#define SMPH_SMPH5_STAT_M 0x00000001 +#define SMPH_SMPH5_STAT_S 0 //***************************************************************************** // @@ -363,10 +363,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH6_STAT 0x00000001 -#define SMPH_SMPH6_STAT_BITN 0 -#define SMPH_SMPH6_STAT_M 0x00000001 -#define SMPH_SMPH6_STAT_S 0 +#define SMPH_SMPH6_STAT 0x00000001 +#define SMPH_SMPH6_STAT_BITN 0 +#define SMPH_SMPH6_STAT_M 0x00000001 +#define SMPH_SMPH6_STAT_S 0 //***************************************************************************** // @@ -382,10 +382,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH7_STAT 0x00000001 -#define SMPH_SMPH7_STAT_BITN 0 -#define SMPH_SMPH7_STAT_M 0x00000001 -#define SMPH_SMPH7_STAT_S 0 +#define SMPH_SMPH7_STAT 0x00000001 +#define SMPH_SMPH7_STAT_BITN 0 +#define SMPH_SMPH7_STAT_M 0x00000001 +#define SMPH_SMPH7_STAT_S 0 //***************************************************************************** // @@ -401,10 +401,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH8_STAT 0x00000001 -#define SMPH_SMPH8_STAT_BITN 0 -#define SMPH_SMPH8_STAT_M 0x00000001 -#define SMPH_SMPH8_STAT_S 0 +#define SMPH_SMPH8_STAT 0x00000001 +#define SMPH_SMPH8_STAT_BITN 0 +#define SMPH_SMPH8_STAT_M 0x00000001 +#define SMPH_SMPH8_STAT_S 0 //***************************************************************************** // @@ -420,10 +420,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH9_STAT 0x00000001 -#define SMPH_SMPH9_STAT_BITN 0 -#define SMPH_SMPH9_STAT_M 0x00000001 -#define SMPH_SMPH9_STAT_S 0 +#define SMPH_SMPH9_STAT 0x00000001 +#define SMPH_SMPH9_STAT_BITN 0 +#define SMPH_SMPH9_STAT_M 0x00000001 +#define SMPH_SMPH9_STAT_S 0 //***************************************************************************** // @@ -439,10 +439,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH10_STAT 0x00000001 -#define SMPH_SMPH10_STAT_BITN 0 -#define SMPH_SMPH10_STAT_M 0x00000001 -#define SMPH_SMPH10_STAT_S 0 +#define SMPH_SMPH10_STAT 0x00000001 +#define SMPH_SMPH10_STAT_BITN 0 +#define SMPH_SMPH10_STAT_M 0x00000001 +#define SMPH_SMPH10_STAT_S 0 //***************************************************************************** // @@ -458,10 +458,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH11_STAT 0x00000001 -#define SMPH_SMPH11_STAT_BITN 0 -#define SMPH_SMPH11_STAT_M 0x00000001 -#define SMPH_SMPH11_STAT_S 0 +#define SMPH_SMPH11_STAT 0x00000001 +#define SMPH_SMPH11_STAT_BITN 0 +#define SMPH_SMPH11_STAT_M 0x00000001 +#define SMPH_SMPH11_STAT_S 0 //***************************************************************************** // @@ -477,10 +477,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH12_STAT 0x00000001 -#define SMPH_SMPH12_STAT_BITN 0 -#define SMPH_SMPH12_STAT_M 0x00000001 -#define SMPH_SMPH12_STAT_S 0 +#define SMPH_SMPH12_STAT 0x00000001 +#define SMPH_SMPH12_STAT_BITN 0 +#define SMPH_SMPH12_STAT_M 0x00000001 +#define SMPH_SMPH12_STAT_S 0 //***************************************************************************** // @@ -496,10 +496,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH13_STAT 0x00000001 -#define SMPH_SMPH13_STAT_BITN 0 -#define SMPH_SMPH13_STAT_M 0x00000001 -#define SMPH_SMPH13_STAT_S 0 +#define SMPH_SMPH13_STAT 0x00000001 +#define SMPH_SMPH13_STAT_BITN 0 +#define SMPH_SMPH13_STAT_M 0x00000001 +#define SMPH_SMPH13_STAT_S 0 //***************************************************************************** // @@ -515,10 +515,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH14_STAT 0x00000001 -#define SMPH_SMPH14_STAT_BITN 0 -#define SMPH_SMPH14_STAT_M 0x00000001 -#define SMPH_SMPH14_STAT_S 0 +#define SMPH_SMPH14_STAT 0x00000001 +#define SMPH_SMPH14_STAT_BITN 0 +#define SMPH_SMPH14_STAT_M 0x00000001 +#define SMPH_SMPH14_STAT_S 0 //***************************************************************************** // @@ -534,10 +534,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH15_STAT 0x00000001 -#define SMPH_SMPH15_STAT_BITN 0 -#define SMPH_SMPH15_STAT_M 0x00000001 -#define SMPH_SMPH15_STAT_S 0 +#define SMPH_SMPH15_STAT 0x00000001 +#define SMPH_SMPH15_STAT_BITN 0 +#define SMPH_SMPH15_STAT_M 0x00000001 +#define SMPH_SMPH15_STAT_S 0 //***************************************************************************** // @@ -553,10 +553,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH16_STAT 0x00000001 -#define SMPH_SMPH16_STAT_BITN 0 -#define SMPH_SMPH16_STAT_M 0x00000001 -#define SMPH_SMPH16_STAT_S 0 +#define SMPH_SMPH16_STAT 0x00000001 +#define SMPH_SMPH16_STAT_BITN 0 +#define SMPH_SMPH16_STAT_M 0x00000001 +#define SMPH_SMPH16_STAT_S 0 //***************************************************************************** // @@ -572,10 +572,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH17_STAT 0x00000001 -#define SMPH_SMPH17_STAT_BITN 0 -#define SMPH_SMPH17_STAT_M 0x00000001 -#define SMPH_SMPH17_STAT_S 0 +#define SMPH_SMPH17_STAT 0x00000001 +#define SMPH_SMPH17_STAT_BITN 0 +#define SMPH_SMPH17_STAT_M 0x00000001 +#define SMPH_SMPH17_STAT_S 0 //***************************************************************************** // @@ -591,10 +591,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH18_STAT 0x00000001 -#define SMPH_SMPH18_STAT_BITN 0 -#define SMPH_SMPH18_STAT_M 0x00000001 -#define SMPH_SMPH18_STAT_S 0 +#define SMPH_SMPH18_STAT 0x00000001 +#define SMPH_SMPH18_STAT_BITN 0 +#define SMPH_SMPH18_STAT_M 0x00000001 +#define SMPH_SMPH18_STAT_S 0 //***************************************************************************** // @@ -610,10 +610,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH19_STAT 0x00000001 -#define SMPH_SMPH19_STAT_BITN 0 -#define SMPH_SMPH19_STAT_M 0x00000001 -#define SMPH_SMPH19_STAT_S 0 +#define SMPH_SMPH19_STAT 0x00000001 +#define SMPH_SMPH19_STAT_BITN 0 +#define SMPH_SMPH19_STAT_M 0x00000001 +#define SMPH_SMPH19_STAT_S 0 //***************************************************************************** // @@ -629,10 +629,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH20_STAT 0x00000001 -#define SMPH_SMPH20_STAT_BITN 0 -#define SMPH_SMPH20_STAT_M 0x00000001 -#define SMPH_SMPH20_STAT_S 0 +#define SMPH_SMPH20_STAT 0x00000001 +#define SMPH_SMPH20_STAT_BITN 0 +#define SMPH_SMPH20_STAT_M 0x00000001 +#define SMPH_SMPH20_STAT_S 0 //***************************************************************************** // @@ -648,10 +648,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH21_STAT 0x00000001 -#define SMPH_SMPH21_STAT_BITN 0 -#define SMPH_SMPH21_STAT_M 0x00000001 -#define SMPH_SMPH21_STAT_S 0 +#define SMPH_SMPH21_STAT 0x00000001 +#define SMPH_SMPH21_STAT_BITN 0 +#define SMPH_SMPH21_STAT_M 0x00000001 +#define SMPH_SMPH21_STAT_S 0 //***************************************************************************** // @@ -667,10 +667,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH22_STAT 0x00000001 -#define SMPH_SMPH22_STAT_BITN 0 -#define SMPH_SMPH22_STAT_M 0x00000001 -#define SMPH_SMPH22_STAT_S 0 +#define SMPH_SMPH22_STAT 0x00000001 +#define SMPH_SMPH22_STAT_BITN 0 +#define SMPH_SMPH22_STAT_M 0x00000001 +#define SMPH_SMPH22_STAT_S 0 //***************************************************************************** // @@ -686,10 +686,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH23_STAT 0x00000001 -#define SMPH_SMPH23_STAT_BITN 0 -#define SMPH_SMPH23_STAT_M 0x00000001 -#define SMPH_SMPH23_STAT_S 0 +#define SMPH_SMPH23_STAT 0x00000001 +#define SMPH_SMPH23_STAT_BITN 0 +#define SMPH_SMPH23_STAT_M 0x00000001 +#define SMPH_SMPH23_STAT_S 0 //***************************************************************************** // @@ -705,10 +705,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH24_STAT 0x00000001 -#define SMPH_SMPH24_STAT_BITN 0 -#define SMPH_SMPH24_STAT_M 0x00000001 -#define SMPH_SMPH24_STAT_S 0 +#define SMPH_SMPH24_STAT 0x00000001 +#define SMPH_SMPH24_STAT_BITN 0 +#define SMPH_SMPH24_STAT_M 0x00000001 +#define SMPH_SMPH24_STAT_S 0 //***************************************************************************** // @@ -724,10 +724,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH25_STAT 0x00000001 -#define SMPH_SMPH25_STAT_BITN 0 -#define SMPH_SMPH25_STAT_M 0x00000001 -#define SMPH_SMPH25_STAT_S 0 +#define SMPH_SMPH25_STAT 0x00000001 +#define SMPH_SMPH25_STAT_BITN 0 +#define SMPH_SMPH25_STAT_M 0x00000001 +#define SMPH_SMPH25_STAT_S 0 //***************************************************************************** // @@ -743,10 +743,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH26_STAT 0x00000001 -#define SMPH_SMPH26_STAT_BITN 0 -#define SMPH_SMPH26_STAT_M 0x00000001 -#define SMPH_SMPH26_STAT_S 0 +#define SMPH_SMPH26_STAT 0x00000001 +#define SMPH_SMPH26_STAT_BITN 0 +#define SMPH_SMPH26_STAT_M 0x00000001 +#define SMPH_SMPH26_STAT_S 0 //***************************************************************************** // @@ -762,10 +762,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH27_STAT 0x00000001 -#define SMPH_SMPH27_STAT_BITN 0 -#define SMPH_SMPH27_STAT_M 0x00000001 -#define SMPH_SMPH27_STAT_S 0 +#define SMPH_SMPH27_STAT 0x00000001 +#define SMPH_SMPH27_STAT_BITN 0 +#define SMPH_SMPH27_STAT_M 0x00000001 +#define SMPH_SMPH27_STAT_S 0 //***************************************************************************** // @@ -781,10 +781,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH28_STAT 0x00000001 -#define SMPH_SMPH28_STAT_BITN 0 -#define SMPH_SMPH28_STAT_M 0x00000001 -#define SMPH_SMPH28_STAT_S 0 +#define SMPH_SMPH28_STAT 0x00000001 +#define SMPH_SMPH28_STAT_BITN 0 +#define SMPH_SMPH28_STAT_M 0x00000001 +#define SMPH_SMPH28_STAT_S 0 //***************************************************************************** // @@ -800,10 +800,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH29_STAT 0x00000001 -#define SMPH_SMPH29_STAT_BITN 0 -#define SMPH_SMPH29_STAT_M 0x00000001 -#define SMPH_SMPH29_STAT_S 0 +#define SMPH_SMPH29_STAT 0x00000001 +#define SMPH_SMPH29_STAT_BITN 0 +#define SMPH_SMPH29_STAT_M 0x00000001 +#define SMPH_SMPH29_STAT_S 0 //***************************************************************************** // @@ -819,10 +819,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH30_STAT 0x00000001 -#define SMPH_SMPH30_STAT_BITN 0 -#define SMPH_SMPH30_STAT_M 0x00000001 -#define SMPH_SMPH30_STAT_S 0 +#define SMPH_SMPH30_STAT 0x00000001 +#define SMPH_SMPH30_STAT_BITN 0 +#define SMPH_SMPH30_STAT_M 0x00000001 +#define SMPH_SMPH30_STAT_S 0 //***************************************************************************** // @@ -838,10 +838,10 @@ // // Reading the register causes it to change value to 0. Releasing the semaphore // is done by writing 1. -#define SMPH_SMPH31_STAT 0x00000001 -#define SMPH_SMPH31_STAT_BITN 0 -#define SMPH_SMPH31_STAT_M 0x00000001 -#define SMPH_SMPH31_STAT_S 0 +#define SMPH_SMPH31_STAT 0x00000001 +#define SMPH_SMPH31_STAT_BITN 0 +#define SMPH_SMPH31_STAT_M 0x00000001 +#define SMPH_SMPH31_STAT_S 0 //***************************************************************************** // @@ -857,10 +857,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK0_STAT 0x00000001 -#define SMPH_PEEK0_STAT_BITN 0 -#define SMPH_PEEK0_STAT_M 0x00000001 -#define SMPH_PEEK0_STAT_S 0 +#define SMPH_PEEK0_STAT 0x00000001 +#define SMPH_PEEK0_STAT_BITN 0 +#define SMPH_PEEK0_STAT_M 0x00000001 +#define SMPH_PEEK0_STAT_S 0 //***************************************************************************** // @@ -876,10 +876,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK1_STAT 0x00000001 -#define SMPH_PEEK1_STAT_BITN 0 -#define SMPH_PEEK1_STAT_M 0x00000001 -#define SMPH_PEEK1_STAT_S 0 +#define SMPH_PEEK1_STAT 0x00000001 +#define SMPH_PEEK1_STAT_BITN 0 +#define SMPH_PEEK1_STAT_M 0x00000001 +#define SMPH_PEEK1_STAT_S 0 //***************************************************************************** // @@ -895,10 +895,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK2_STAT 0x00000001 -#define SMPH_PEEK2_STAT_BITN 0 -#define SMPH_PEEK2_STAT_M 0x00000001 -#define SMPH_PEEK2_STAT_S 0 +#define SMPH_PEEK2_STAT 0x00000001 +#define SMPH_PEEK2_STAT_BITN 0 +#define SMPH_PEEK2_STAT_M 0x00000001 +#define SMPH_PEEK2_STAT_S 0 //***************************************************************************** // @@ -914,10 +914,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK3_STAT 0x00000001 -#define SMPH_PEEK3_STAT_BITN 0 -#define SMPH_PEEK3_STAT_M 0x00000001 -#define SMPH_PEEK3_STAT_S 0 +#define SMPH_PEEK3_STAT 0x00000001 +#define SMPH_PEEK3_STAT_BITN 0 +#define SMPH_PEEK3_STAT_M 0x00000001 +#define SMPH_PEEK3_STAT_S 0 //***************************************************************************** // @@ -933,10 +933,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK4_STAT 0x00000001 -#define SMPH_PEEK4_STAT_BITN 0 -#define SMPH_PEEK4_STAT_M 0x00000001 -#define SMPH_PEEK4_STAT_S 0 +#define SMPH_PEEK4_STAT 0x00000001 +#define SMPH_PEEK4_STAT_BITN 0 +#define SMPH_PEEK4_STAT_M 0x00000001 +#define SMPH_PEEK4_STAT_S 0 //***************************************************************************** // @@ -952,10 +952,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK5_STAT 0x00000001 -#define SMPH_PEEK5_STAT_BITN 0 -#define SMPH_PEEK5_STAT_M 0x00000001 -#define SMPH_PEEK5_STAT_S 0 +#define SMPH_PEEK5_STAT 0x00000001 +#define SMPH_PEEK5_STAT_BITN 0 +#define SMPH_PEEK5_STAT_M 0x00000001 +#define SMPH_PEEK5_STAT_S 0 //***************************************************************************** // @@ -971,10 +971,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK6_STAT 0x00000001 -#define SMPH_PEEK6_STAT_BITN 0 -#define SMPH_PEEK6_STAT_M 0x00000001 -#define SMPH_PEEK6_STAT_S 0 +#define SMPH_PEEK6_STAT 0x00000001 +#define SMPH_PEEK6_STAT_BITN 0 +#define SMPH_PEEK6_STAT_M 0x00000001 +#define SMPH_PEEK6_STAT_S 0 //***************************************************************************** // @@ -990,10 +990,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK7_STAT 0x00000001 -#define SMPH_PEEK7_STAT_BITN 0 -#define SMPH_PEEK7_STAT_M 0x00000001 -#define SMPH_PEEK7_STAT_S 0 +#define SMPH_PEEK7_STAT 0x00000001 +#define SMPH_PEEK7_STAT_BITN 0 +#define SMPH_PEEK7_STAT_M 0x00000001 +#define SMPH_PEEK7_STAT_S 0 //***************************************************************************** // @@ -1009,10 +1009,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK8_STAT 0x00000001 -#define SMPH_PEEK8_STAT_BITN 0 -#define SMPH_PEEK8_STAT_M 0x00000001 -#define SMPH_PEEK8_STAT_S 0 +#define SMPH_PEEK8_STAT 0x00000001 +#define SMPH_PEEK8_STAT_BITN 0 +#define SMPH_PEEK8_STAT_M 0x00000001 +#define SMPH_PEEK8_STAT_S 0 //***************************************************************************** // @@ -1028,10 +1028,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK9_STAT 0x00000001 -#define SMPH_PEEK9_STAT_BITN 0 -#define SMPH_PEEK9_STAT_M 0x00000001 -#define SMPH_PEEK9_STAT_S 0 +#define SMPH_PEEK9_STAT 0x00000001 +#define SMPH_PEEK9_STAT_BITN 0 +#define SMPH_PEEK9_STAT_M 0x00000001 +#define SMPH_PEEK9_STAT_S 0 //***************************************************************************** // @@ -1047,10 +1047,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK10_STAT 0x00000001 -#define SMPH_PEEK10_STAT_BITN 0 -#define SMPH_PEEK10_STAT_M 0x00000001 -#define SMPH_PEEK10_STAT_S 0 +#define SMPH_PEEK10_STAT 0x00000001 +#define SMPH_PEEK10_STAT_BITN 0 +#define SMPH_PEEK10_STAT_M 0x00000001 +#define SMPH_PEEK10_STAT_S 0 //***************************************************************************** // @@ -1066,10 +1066,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK11_STAT 0x00000001 -#define SMPH_PEEK11_STAT_BITN 0 -#define SMPH_PEEK11_STAT_M 0x00000001 -#define SMPH_PEEK11_STAT_S 0 +#define SMPH_PEEK11_STAT 0x00000001 +#define SMPH_PEEK11_STAT_BITN 0 +#define SMPH_PEEK11_STAT_M 0x00000001 +#define SMPH_PEEK11_STAT_S 0 //***************************************************************************** // @@ -1085,10 +1085,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK12_STAT 0x00000001 -#define SMPH_PEEK12_STAT_BITN 0 -#define SMPH_PEEK12_STAT_M 0x00000001 -#define SMPH_PEEK12_STAT_S 0 +#define SMPH_PEEK12_STAT 0x00000001 +#define SMPH_PEEK12_STAT_BITN 0 +#define SMPH_PEEK12_STAT_M 0x00000001 +#define SMPH_PEEK12_STAT_S 0 //***************************************************************************** // @@ -1104,10 +1104,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK13_STAT 0x00000001 -#define SMPH_PEEK13_STAT_BITN 0 -#define SMPH_PEEK13_STAT_M 0x00000001 -#define SMPH_PEEK13_STAT_S 0 +#define SMPH_PEEK13_STAT 0x00000001 +#define SMPH_PEEK13_STAT_BITN 0 +#define SMPH_PEEK13_STAT_M 0x00000001 +#define SMPH_PEEK13_STAT_S 0 //***************************************************************************** // @@ -1123,10 +1123,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK14_STAT 0x00000001 -#define SMPH_PEEK14_STAT_BITN 0 -#define SMPH_PEEK14_STAT_M 0x00000001 -#define SMPH_PEEK14_STAT_S 0 +#define SMPH_PEEK14_STAT 0x00000001 +#define SMPH_PEEK14_STAT_BITN 0 +#define SMPH_PEEK14_STAT_M 0x00000001 +#define SMPH_PEEK14_STAT_S 0 //***************************************************************************** // @@ -1142,10 +1142,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK15_STAT 0x00000001 -#define SMPH_PEEK15_STAT_BITN 0 -#define SMPH_PEEK15_STAT_M 0x00000001 -#define SMPH_PEEK15_STAT_S 0 +#define SMPH_PEEK15_STAT 0x00000001 +#define SMPH_PEEK15_STAT_BITN 0 +#define SMPH_PEEK15_STAT_M 0x00000001 +#define SMPH_PEEK15_STAT_S 0 //***************************************************************************** // @@ -1161,10 +1161,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK16_STAT 0x00000001 -#define SMPH_PEEK16_STAT_BITN 0 -#define SMPH_PEEK16_STAT_M 0x00000001 -#define SMPH_PEEK16_STAT_S 0 +#define SMPH_PEEK16_STAT 0x00000001 +#define SMPH_PEEK16_STAT_BITN 0 +#define SMPH_PEEK16_STAT_M 0x00000001 +#define SMPH_PEEK16_STAT_S 0 //***************************************************************************** // @@ -1180,10 +1180,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK17_STAT 0x00000001 -#define SMPH_PEEK17_STAT_BITN 0 -#define SMPH_PEEK17_STAT_M 0x00000001 -#define SMPH_PEEK17_STAT_S 0 +#define SMPH_PEEK17_STAT 0x00000001 +#define SMPH_PEEK17_STAT_BITN 0 +#define SMPH_PEEK17_STAT_M 0x00000001 +#define SMPH_PEEK17_STAT_S 0 //***************************************************************************** // @@ -1199,10 +1199,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK18_STAT 0x00000001 -#define SMPH_PEEK18_STAT_BITN 0 -#define SMPH_PEEK18_STAT_M 0x00000001 -#define SMPH_PEEK18_STAT_S 0 +#define SMPH_PEEK18_STAT 0x00000001 +#define SMPH_PEEK18_STAT_BITN 0 +#define SMPH_PEEK18_STAT_M 0x00000001 +#define SMPH_PEEK18_STAT_S 0 //***************************************************************************** // @@ -1218,10 +1218,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK19_STAT 0x00000001 -#define SMPH_PEEK19_STAT_BITN 0 -#define SMPH_PEEK19_STAT_M 0x00000001 -#define SMPH_PEEK19_STAT_S 0 +#define SMPH_PEEK19_STAT 0x00000001 +#define SMPH_PEEK19_STAT_BITN 0 +#define SMPH_PEEK19_STAT_M 0x00000001 +#define SMPH_PEEK19_STAT_S 0 //***************************************************************************** // @@ -1237,10 +1237,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK20_STAT 0x00000001 -#define SMPH_PEEK20_STAT_BITN 0 -#define SMPH_PEEK20_STAT_M 0x00000001 -#define SMPH_PEEK20_STAT_S 0 +#define SMPH_PEEK20_STAT 0x00000001 +#define SMPH_PEEK20_STAT_BITN 0 +#define SMPH_PEEK20_STAT_M 0x00000001 +#define SMPH_PEEK20_STAT_S 0 //***************************************************************************** // @@ -1256,10 +1256,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK21_STAT 0x00000001 -#define SMPH_PEEK21_STAT_BITN 0 -#define SMPH_PEEK21_STAT_M 0x00000001 -#define SMPH_PEEK21_STAT_S 0 +#define SMPH_PEEK21_STAT 0x00000001 +#define SMPH_PEEK21_STAT_BITN 0 +#define SMPH_PEEK21_STAT_M 0x00000001 +#define SMPH_PEEK21_STAT_S 0 //***************************************************************************** // @@ -1275,10 +1275,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK22_STAT 0x00000001 -#define SMPH_PEEK22_STAT_BITN 0 -#define SMPH_PEEK22_STAT_M 0x00000001 -#define SMPH_PEEK22_STAT_S 0 +#define SMPH_PEEK22_STAT 0x00000001 +#define SMPH_PEEK22_STAT_BITN 0 +#define SMPH_PEEK22_STAT_M 0x00000001 +#define SMPH_PEEK22_STAT_S 0 //***************************************************************************** // @@ -1294,10 +1294,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK23_STAT 0x00000001 -#define SMPH_PEEK23_STAT_BITN 0 -#define SMPH_PEEK23_STAT_M 0x00000001 -#define SMPH_PEEK23_STAT_S 0 +#define SMPH_PEEK23_STAT 0x00000001 +#define SMPH_PEEK23_STAT_BITN 0 +#define SMPH_PEEK23_STAT_M 0x00000001 +#define SMPH_PEEK23_STAT_S 0 //***************************************************************************** // @@ -1313,10 +1313,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK24_STAT 0x00000001 -#define SMPH_PEEK24_STAT_BITN 0 -#define SMPH_PEEK24_STAT_M 0x00000001 -#define SMPH_PEEK24_STAT_S 0 +#define SMPH_PEEK24_STAT 0x00000001 +#define SMPH_PEEK24_STAT_BITN 0 +#define SMPH_PEEK24_STAT_M 0x00000001 +#define SMPH_PEEK24_STAT_S 0 //***************************************************************************** // @@ -1332,10 +1332,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK25_STAT 0x00000001 -#define SMPH_PEEK25_STAT_BITN 0 -#define SMPH_PEEK25_STAT_M 0x00000001 -#define SMPH_PEEK25_STAT_S 0 +#define SMPH_PEEK25_STAT 0x00000001 +#define SMPH_PEEK25_STAT_BITN 0 +#define SMPH_PEEK25_STAT_M 0x00000001 +#define SMPH_PEEK25_STAT_S 0 //***************************************************************************** // @@ -1351,10 +1351,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK26_STAT 0x00000001 -#define SMPH_PEEK26_STAT_BITN 0 -#define SMPH_PEEK26_STAT_M 0x00000001 -#define SMPH_PEEK26_STAT_S 0 +#define SMPH_PEEK26_STAT 0x00000001 +#define SMPH_PEEK26_STAT_BITN 0 +#define SMPH_PEEK26_STAT_M 0x00000001 +#define SMPH_PEEK26_STAT_S 0 //***************************************************************************** // @@ -1370,10 +1370,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK27_STAT 0x00000001 -#define SMPH_PEEK27_STAT_BITN 0 -#define SMPH_PEEK27_STAT_M 0x00000001 -#define SMPH_PEEK27_STAT_S 0 +#define SMPH_PEEK27_STAT 0x00000001 +#define SMPH_PEEK27_STAT_BITN 0 +#define SMPH_PEEK27_STAT_M 0x00000001 +#define SMPH_PEEK27_STAT_S 0 //***************************************************************************** // @@ -1389,10 +1389,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK28_STAT 0x00000001 -#define SMPH_PEEK28_STAT_BITN 0 -#define SMPH_PEEK28_STAT_M 0x00000001 -#define SMPH_PEEK28_STAT_S 0 +#define SMPH_PEEK28_STAT 0x00000001 +#define SMPH_PEEK28_STAT_BITN 0 +#define SMPH_PEEK28_STAT_M 0x00000001 +#define SMPH_PEEK28_STAT_S 0 //***************************************************************************** // @@ -1408,10 +1408,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK29_STAT 0x00000001 -#define SMPH_PEEK29_STAT_BITN 0 -#define SMPH_PEEK29_STAT_M 0x00000001 -#define SMPH_PEEK29_STAT_S 0 +#define SMPH_PEEK29_STAT 0x00000001 +#define SMPH_PEEK29_STAT_BITN 0 +#define SMPH_PEEK29_STAT_M 0x00000001 +#define SMPH_PEEK29_STAT_S 0 //***************************************************************************** // @@ -1427,10 +1427,10 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK30_STAT 0x00000001 -#define SMPH_PEEK30_STAT_BITN 0 -#define SMPH_PEEK30_STAT_M 0x00000001 -#define SMPH_PEEK30_STAT_S 0 +#define SMPH_PEEK30_STAT 0x00000001 +#define SMPH_PEEK30_STAT_BITN 0 +#define SMPH_PEEK30_STAT_M 0x00000001 +#define SMPH_PEEK30_STAT_S 0 //***************************************************************************** // @@ -1446,10 +1446,9 @@ // // Used for semaphore debugging. A read operation will not change register // value. Register writing is not possible. -#define SMPH_PEEK31_STAT 0x00000001 -#define SMPH_PEEK31_STAT_BITN 0 -#define SMPH_PEEK31_STAT_M 0x00000001 -#define SMPH_PEEK31_STAT_S 0 - +#define SMPH_PEEK31_STAT 0x00000001 +#define SMPH_PEEK31_STAT_BITN 0 +#define SMPH_PEEK31_STAT_M 0x00000001 +#define SMPH_PEEK31_STAT_S 0 #endif // __SMPH__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ssi.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ssi.h index a83b856..3d617c7 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ssi.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_ssi.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_ssi_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_ssi_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_SSI_H__ #define __HW_SSI_H__ @@ -44,34 +44,34 @@ // //***************************************************************************** // Control 0 -#define SSI_O_CR0 0x00000000 +#define SSI_O_CR0 0x00000000 // Control 1 -#define SSI_O_CR1 0x00000004 +#define SSI_O_CR1 0x00000004 // Data -#define SSI_O_DR 0x00000008 +#define SSI_O_DR 0x00000008 // Status -#define SSI_O_SR 0x0000000C +#define SSI_O_SR 0x0000000C // Clock Prescale -#define SSI_O_CPSR 0x00000010 +#define SSI_O_CPSR 0x00000010 // Interrupt Mask Set and Clear -#define SSI_O_IMSC 0x00000014 +#define SSI_O_IMSC 0x00000014 // Raw Interrupt Status -#define SSI_O_RIS 0x00000018 +#define SSI_O_RIS 0x00000018 // Masked Interrupt Status -#define SSI_O_MIS 0x0000001C +#define SSI_O_MIS 0x0000001C // Interrupt Clear -#define SSI_O_ICR 0x00000020 +#define SSI_O_ICR 0x00000020 // DMA Control -#define SSI_O_DMACR 0x00000024 +#define SSI_O_DMACR 0x00000024 //***************************************************************************** // @@ -85,9 +85,9 @@ // bit rate is // (SSI's clock frequency)/((SCR+1)*CPSR.CPSDVSR). // SCR is a value from 0-255. -#define SSI_CR0_SCR_W 8 -#define SSI_CR0_SCR_M 0x0000FF00 -#define SSI_CR0_SCR_S 8 +#define SSI_CR0_SCR_W 8 +#define SSI_CR0_SCR_M 0x0000FF00 +#define SSI_CR0_SCR_S 8 // Field: [7] SPH // @@ -101,12 +101,12 @@ // transition. // 1ST_CLK_EDGE Data is captured on the first clock edge // transition. -#define SSI_CR0_SPH 0x00000080 -#define SSI_CR0_SPH_BITN 7 -#define SSI_CR0_SPH_M 0x00000080 -#define SSI_CR0_SPH_S 7 -#define SSI_CR0_SPH_2ND_CLK_EDGE 0x00000080 -#define SSI_CR0_SPH_1ST_CLK_EDGE 0x00000000 +#define SSI_CR0_SPH 0x00000080 +#define SSI_CR0_SPH_BITN 7 +#define SSI_CR0_SPH_M 0x00000080 +#define SSI_CR0_SPH_S 7 +#define SSI_CR0_SPH_2ND_CLK_EDGE 0x00000080 +#define SSI_CR0_SPH_1ST_CLK_EDGE 0x00000000 // Field: [6] SPO // @@ -117,12 +117,12 @@ // LOW SSI produces a steady state LOW value on the // CLKOUT pin when data is // not being transferred. -#define SSI_CR0_SPO 0x00000040 -#define SSI_CR0_SPO_BITN 6 -#define SSI_CR0_SPO_M 0x00000040 -#define SSI_CR0_SPO_S 6 -#define SSI_CR0_SPO_HIGH 0x00000040 -#define SSI_CR0_SPO_LOW 0x00000000 +#define SSI_CR0_SPO 0x00000040 +#define SSI_CR0_SPO_BITN 6 +#define SSI_CR0_SPO_M 0x00000040 +#define SSI_CR0_SPO_S 6 +#define SSI_CR0_SPO_HIGH 0x00000040 +#define SSI_CR0_SPO_LOW 0x00000000 // Field: [5:4] FRF // @@ -134,12 +134,12 @@ // NATIONAL_MICROWIRE National Microwire frame format // TI_SYNC_SERIAL TI synchronous serial frame format // MOTOROLA_SPI Motorola SPI frame format -#define SSI_CR0_FRF_W 2 -#define SSI_CR0_FRF_M 0x00000030 -#define SSI_CR0_FRF_S 4 -#define SSI_CR0_FRF_NATIONAL_MICROWIRE 0x00000020 -#define SSI_CR0_FRF_TI_SYNC_SERIAL 0x00000010 -#define SSI_CR0_FRF_MOTOROLA_SPI 0x00000000 +#define SSI_CR0_FRF_W 2 +#define SSI_CR0_FRF_M 0x00000030 +#define SSI_CR0_FRF_S 4 +#define SSI_CR0_FRF_NATIONAL_MICROWIRE 0x00000020 +#define SSI_CR0_FRF_TI_SYNC_SERIAL 0x00000010 +#define SSI_CR0_FRF_MOTOROLA_SPI 0x00000000 // Field: [3:0] DSS // @@ -159,22 +159,22 @@ // 6_BIT 6-bit data // 5_BIT 5-bit data // 4_BIT 4-bit data -#define SSI_CR0_DSS_W 4 -#define SSI_CR0_DSS_M 0x0000000F -#define SSI_CR0_DSS_S 0 -#define SSI_CR0_DSS_16_BIT 0x0000000F -#define SSI_CR0_DSS_15_BIT 0x0000000E -#define SSI_CR0_DSS_14_BIT 0x0000000D -#define SSI_CR0_DSS_13_BIT 0x0000000C -#define SSI_CR0_DSS_12_BIT 0x0000000B -#define SSI_CR0_DSS_11_BIT 0x0000000A -#define SSI_CR0_DSS_10_BIT 0x00000009 -#define SSI_CR0_DSS_9_BIT 0x00000008 -#define SSI_CR0_DSS_8_BIT 0x00000007 -#define SSI_CR0_DSS_7_BIT 0x00000006 -#define SSI_CR0_DSS_6_BIT 0x00000005 -#define SSI_CR0_DSS_5_BIT 0x00000004 -#define SSI_CR0_DSS_4_BIT 0x00000003 +#define SSI_CR0_DSS_W 4 +#define SSI_CR0_DSS_M 0x0000000F +#define SSI_CR0_DSS_S 0 +#define SSI_CR0_DSS_16_BIT 0x0000000F +#define SSI_CR0_DSS_15_BIT 0x0000000E +#define SSI_CR0_DSS_14_BIT 0x0000000D +#define SSI_CR0_DSS_13_BIT 0x0000000C +#define SSI_CR0_DSS_12_BIT 0x0000000B +#define SSI_CR0_DSS_11_BIT 0x0000000A +#define SSI_CR0_DSS_10_BIT 0x00000009 +#define SSI_CR0_DSS_9_BIT 0x00000008 +#define SSI_CR0_DSS_8_BIT 0x00000007 +#define SSI_CR0_DSS_7_BIT 0x00000006 +#define SSI_CR0_DSS_6_BIT 0x00000005 +#define SSI_CR0_DSS_5_BIT 0x00000004 +#define SSI_CR0_DSS_4_BIT 0x00000003 //***************************************************************************** // @@ -193,10 +193,10 @@ // // 0: SSI can drive the TXD output in slave mode. // 1: SSI cannot drive the TXD output in slave mode. -#define SSI_CR1_SOD 0x00000008 -#define SSI_CR1_SOD_BITN 3 -#define SSI_CR1_SOD_M 0x00000008 -#define SSI_CR1_SOD_S 3 +#define SSI_CR1_SOD 0x00000008 +#define SSI_CR1_SOD_BITN 3 +#define SSI_CR1_SOD_M 0x00000008 +#define SSI_CR1_SOD_S 3 // Field: [2] MS // @@ -205,12 +205,12 @@ // ENUMs: // SLAVE Device configured as slave // MASTER Device configured as master -#define SSI_CR1_MS 0x00000004 -#define SSI_CR1_MS_BITN 2 -#define SSI_CR1_MS_M 0x00000004 -#define SSI_CR1_MS_S 2 -#define SSI_CR1_MS_SLAVE 0x00000004 -#define SSI_CR1_MS_MASTER 0x00000000 +#define SSI_CR1_MS 0x00000004 +#define SSI_CR1_MS_BITN 2 +#define SSI_CR1_MS_M 0x00000004 +#define SSI_CR1_MS_S 2 +#define SSI_CR1_MS_SLAVE 0x00000004 +#define SSI_CR1_MS_MASTER 0x00000000 // Field: [1] SSE // @@ -218,12 +218,12 @@ // ENUMs: // SSI_ENABLED Operation enabled // SSI_DISABLED Operation disabled -#define SSI_CR1_SSE 0x00000002 -#define SSI_CR1_SSE_BITN 1 -#define SSI_CR1_SSE_M 0x00000002 -#define SSI_CR1_SSE_S 1 -#define SSI_CR1_SSE_SSI_ENABLED 0x00000002 -#define SSI_CR1_SSE_SSI_DISABLED 0x00000000 +#define SSI_CR1_SSE 0x00000002 +#define SSI_CR1_SSE_BITN 1 +#define SSI_CR1_SSE_M 0x00000002 +#define SSI_CR1_SSE_S 1 +#define SSI_CR1_SSE_SSI_ENABLED 0x00000002 +#define SSI_CR1_SSE_SSI_DISABLED 0x00000000 // Field: [0] LBM // @@ -232,10 +232,10 @@ // 0: Normal serial port operation enabled. // 1: Output of transmit serial shifter is connected to input of receive serial // shifter internally. -#define SSI_CR1_LBM 0x00000001 -#define SSI_CR1_LBM_BITN 0 -#define SSI_CR1_LBM_M 0x00000001 -#define SSI_CR1_LBM_S 0 +#define SSI_CR1_LBM 0x00000001 +#define SSI_CR1_LBM_BITN 0 +#define SSI_CR1_LBM_M 0x00000001 +#define SSI_CR1_LBM_S 0 //***************************************************************************** // @@ -249,9 +249,9 @@ // right-justified when SSI is programmed for a data size that is less than 16 // bits (CR0.DSS != 0b1111). Unused bits at the top are ignored by transmit // logic. The receive logic automatically right-justifies. -#define SSI_DR_DATA_W 16 -#define SSI_DR_DATA_M 0x0000FFFF -#define SSI_DR_DATA_S 0 +#define SSI_DR_DATA_W 16 +#define SSI_DR_DATA_M 0x0000FFFF +#define SSI_DR_DATA_S 0 //***************************************************************************** // @@ -265,10 +265,10 @@ // 0: SSI is idle // 1: SSI is currently transmitting and/or receiving a frame or the transmit // FIFO is not empty. -#define SSI_SR_BSY 0x00000010 -#define SSI_SR_BSY_BITN 4 -#define SSI_SR_BSY_M 0x00000010 -#define SSI_SR_BSY_S 4 +#define SSI_SR_BSY 0x00000010 +#define SSI_SR_BSY_BITN 4 +#define SSI_SR_BSY_M 0x00000010 +#define SSI_SR_BSY_S 4 // Field: [3] RFF // @@ -276,10 +276,10 @@ // // 0: Receive FIFO is not full. // 1: Receive FIFO is full. -#define SSI_SR_RFF 0x00000008 -#define SSI_SR_RFF_BITN 3 -#define SSI_SR_RFF_M 0x00000008 -#define SSI_SR_RFF_S 3 +#define SSI_SR_RFF 0x00000008 +#define SSI_SR_RFF_BITN 3 +#define SSI_SR_RFF_M 0x00000008 +#define SSI_SR_RFF_S 3 // Field: [2] RNE // @@ -287,10 +287,10 @@ // // 0: Receive FIFO is empty. // 1: Receive FIFO is not empty. -#define SSI_SR_RNE 0x00000004 -#define SSI_SR_RNE_BITN 2 -#define SSI_SR_RNE_M 0x00000004 -#define SSI_SR_RNE_S 2 +#define SSI_SR_RNE 0x00000004 +#define SSI_SR_RNE_BITN 2 +#define SSI_SR_RNE_M 0x00000004 +#define SSI_SR_RNE_S 2 // Field: [1] TNF // @@ -298,10 +298,10 @@ // // 0: Transmit FIFO is full. // 1: Transmit FIFO is not full. -#define SSI_SR_TNF 0x00000002 -#define SSI_SR_TNF_BITN 1 -#define SSI_SR_TNF_M 0x00000002 -#define SSI_SR_TNF_S 1 +#define SSI_SR_TNF 0x00000002 +#define SSI_SR_TNF_BITN 1 +#define SSI_SR_TNF_M 0x00000002 +#define SSI_SR_TNF_S 1 // Field: [0] TFE // @@ -309,10 +309,10 @@ // // 0: Transmit FIFO is not empty. // 1: Transmit FIFO is empty. -#define SSI_SR_TFE 0x00000001 -#define SSI_SR_TFE_BITN 0 -#define SSI_SR_TFE_M 0x00000001 -#define SSI_SR_TFE_S 0 +#define SSI_SR_TFE 0x00000001 +#define SSI_SR_TFE_BITN 0 +#define SSI_SR_TFE_M 0x00000001 +#define SSI_SR_TFE_S 0 //***************************************************************************** // @@ -328,9 +328,9 @@ // (2-254). The least significant bit of the programmed number is hard-coded to // zero. If an odd number is written to this register, data read back from // this register has the least significant bit as zero. -#define SSI_CPSR_CPSDVSR_W 8 -#define SSI_CPSR_CPSDVSR_M 0x000000FF -#define SSI_CPSR_CPSDVSR_S 0 +#define SSI_CPSR_CPSDVSR_W 8 +#define SSI_CPSR_CPSDVSR_M 0x000000FF +#define SSI_CPSR_CPSDVSR_S 0 //***************************************************************************** // @@ -344,10 +344,10 @@ // 1, the mask for transmit FIFO interrupt is set which means the interrupt // state will be reflected in MIS.TXMIS. A write of 0 clears the mask which // means MIS.TXMIS will not reflect the interrupt. -#define SSI_IMSC_TXIM 0x00000008 -#define SSI_IMSC_TXIM_BITN 3 -#define SSI_IMSC_TXIM_M 0x00000008 -#define SSI_IMSC_TXIM_S 3 +#define SSI_IMSC_TXIM 0x00000008 +#define SSI_IMSC_TXIM_BITN 3 +#define SSI_IMSC_TXIM_M 0x00000008 +#define SSI_IMSC_TXIM_S 3 // Field: [2] RXIM // @@ -356,10 +356,10 @@ // the mask for receive FIFO interrupt is set which means the interrupt state // will be reflected in MIS.RXMIS. A write of 0 clears the mask which means // MIS.RXMIS will not reflect the interrupt. -#define SSI_IMSC_RXIM 0x00000004 -#define SSI_IMSC_RXIM_BITN 2 -#define SSI_IMSC_RXIM_M 0x00000004 -#define SSI_IMSC_RXIM_S 2 +#define SSI_IMSC_RXIM 0x00000004 +#define SSI_IMSC_RXIM_BITN 2 +#define SSI_IMSC_RXIM_M 0x00000004 +#define SSI_IMSC_RXIM_S 2 // Field: [1] RTIM // @@ -368,10 +368,10 @@ // 1, the mask for receive timeout interrupt is set which means the interrupt // state will be reflected in MIS.RTMIS. A write of 0 clears the mask which // means MIS.RTMIS will not reflect the interrupt. -#define SSI_IMSC_RTIM 0x00000002 -#define SSI_IMSC_RTIM_BITN 1 -#define SSI_IMSC_RTIM_M 0x00000002 -#define SSI_IMSC_RTIM_S 1 +#define SSI_IMSC_RTIM 0x00000002 +#define SSI_IMSC_RTIM_BITN 1 +#define SSI_IMSC_RTIM_M 0x00000002 +#define SSI_IMSC_RTIM_S 1 // Field: [0] RORIM // @@ -380,10 +380,10 @@ // 1, the mask for receive overrun interrupt is set which means the interrupt // state will be reflected in MIS.RORMIS. A write of 0 clears the mask which // means MIS.RORMIS will not reflect the interrupt. -#define SSI_IMSC_RORIM 0x00000001 -#define SSI_IMSC_RORIM_BITN 0 -#define SSI_IMSC_RORIM_M 0x00000001 -#define SSI_IMSC_RORIM_S 0 +#define SSI_IMSC_RORIM 0x00000001 +#define SSI_IMSC_RORIM_BITN 0 +#define SSI_IMSC_RORIM_M 0x00000001 +#define SSI_IMSC_RORIM_S 0 //***************************************************************************** // @@ -401,20 +401,20 @@ // interrupts. // - SSI and interrupts can be enabled so that data can be written to the // transmit FIFO by an interrupt service routine. -#define SSI_RIS_TXRIS 0x00000008 -#define SSI_RIS_TXRIS_BITN 3 -#define SSI_RIS_TXRIS_M 0x00000008 -#define SSI_RIS_TXRIS_S 3 +#define SSI_RIS_TXRIS 0x00000008 +#define SSI_RIS_TXRIS_BITN 3 +#define SSI_RIS_TXRIS_M 0x00000008 +#define SSI_RIS_TXRIS_S 3 // Field: [2] RXRIS // // Raw interrupt state of receive FIFO interrupt: // The receive interrupt is asserted when there are four or more valid entries // in the receive FIFO. -#define SSI_RIS_RXRIS 0x00000004 -#define SSI_RIS_RXRIS_BITN 2 -#define SSI_RIS_RXRIS_M 0x00000004 -#define SSI_RIS_RXRIS_S 2 +#define SSI_RIS_RXRIS 0x00000004 +#define SSI_RIS_RXRIS_BITN 2 +#define SSI_RIS_RXRIS_M 0x00000004 +#define SSI_RIS_RXRIS_S 2 // Field: [1] RTRIS // @@ -425,10 +425,10 @@ // requires servicing. This interrupt is deasserted if the receive FIFO becomes // empty by subsequent reads, or if new data is received on RXD. // It can also be cleared by writing to ICR.RTIC. -#define SSI_RIS_RTRIS 0x00000002 -#define SSI_RIS_RTRIS_BITN 1 -#define SSI_RIS_RTRIS_M 0x00000002 -#define SSI_RIS_RTRIS_S 1 +#define SSI_RIS_RTRIS 0x00000002 +#define SSI_RIS_RTRIS_BITN 1 +#define SSI_RIS_RTRIS_M 0x00000002 +#define SSI_RIS_RTRIS_S 1 // Field: [0] RORRIS // @@ -438,10 +438,10 @@ // is over-written in the // receive shift register, but not the FIFO so the FIFO contents stay valid. // It can also be cleared by writing to ICR.RORIC. -#define SSI_RIS_RORRIS 0x00000001 -#define SSI_RIS_RORRIS_BITN 0 -#define SSI_RIS_RORRIS_M 0x00000001 -#define SSI_RIS_RORRIS_S 0 +#define SSI_RIS_RORRIS 0x00000001 +#define SSI_RIS_RORRIS_BITN 0 +#define SSI_RIS_RORRIS_M 0x00000001 +#define SSI_RIS_RORRIS_S 0 //***************************************************************************** // @@ -454,10 +454,10 @@ // This field returns the masked interrupt state of transmit FIFO interrupt // which is the AND product of raw interrupt state RIS.TXRIS and the mask // setting IMSC.TXIM. -#define SSI_MIS_TXMIS 0x00000008 -#define SSI_MIS_TXMIS_BITN 3 -#define SSI_MIS_TXMIS_M 0x00000008 -#define SSI_MIS_TXMIS_S 3 +#define SSI_MIS_TXMIS 0x00000008 +#define SSI_MIS_TXMIS_BITN 3 +#define SSI_MIS_TXMIS_M 0x00000008 +#define SSI_MIS_TXMIS_S 3 // Field: [2] RXMIS // @@ -465,10 +465,10 @@ // This field returns the masked interrupt state of receive FIFO interrupt // which is the AND product of raw interrupt state RIS.RXRIS and the mask // setting IMSC.RXIM. -#define SSI_MIS_RXMIS 0x00000004 -#define SSI_MIS_RXMIS_BITN 2 -#define SSI_MIS_RXMIS_M 0x00000004 -#define SSI_MIS_RXMIS_S 2 +#define SSI_MIS_RXMIS 0x00000004 +#define SSI_MIS_RXMIS_BITN 2 +#define SSI_MIS_RXMIS_M 0x00000004 +#define SSI_MIS_RXMIS_S 2 // Field: [1] RTMIS // @@ -476,10 +476,10 @@ // This field returns the masked interrupt state of receive timeout interrupt // which is the AND product of raw interrupt state RIS.RTRIS and the mask // setting IMSC.RTIM. -#define SSI_MIS_RTMIS 0x00000002 -#define SSI_MIS_RTMIS_BITN 1 -#define SSI_MIS_RTMIS_M 0x00000002 -#define SSI_MIS_RTMIS_S 1 +#define SSI_MIS_RTMIS 0x00000002 +#define SSI_MIS_RTMIS_BITN 1 +#define SSI_MIS_RTMIS_M 0x00000002 +#define SSI_MIS_RTMIS_S 1 // Field: [0] RORMIS // @@ -487,10 +487,10 @@ // This field returns the masked interrupt state of receive overrun interrupt // which is the AND product of raw interrupt state RIS.RORRIS and the mask // setting IMSC.RORIM. -#define SSI_MIS_RORMIS 0x00000001 -#define SSI_MIS_RORMIS_BITN 0 -#define SSI_MIS_RORMIS_M 0x00000001 -#define SSI_MIS_RORMIS_S 0 +#define SSI_MIS_RORMIS 0x00000001 +#define SSI_MIS_RORMIS_BITN 0 +#define SSI_MIS_RORMIS_M 0x00000001 +#define SSI_MIS_RORMIS_S 0 //***************************************************************************** // @@ -502,20 +502,20 @@ // Clear the receive timeout interrupt: // Writing 1 to this field clears the timeout interrupt (RIS.RTRIS). Writing 0 // has no effect. -#define SSI_ICR_RTIC 0x00000002 -#define SSI_ICR_RTIC_BITN 1 -#define SSI_ICR_RTIC_M 0x00000002 -#define SSI_ICR_RTIC_S 1 +#define SSI_ICR_RTIC 0x00000002 +#define SSI_ICR_RTIC_BITN 1 +#define SSI_ICR_RTIC_M 0x00000002 +#define SSI_ICR_RTIC_S 1 // Field: [0] RORIC // // Clear the receive overrun interrupt: // Writing 1 to this field clears the overrun error interrupt (RIS.RORRIS). // Writing 0 has no effect. -#define SSI_ICR_RORIC 0x00000001 -#define SSI_ICR_RORIC_BITN 0 -#define SSI_ICR_RORIC_M 0x00000001 -#define SSI_ICR_RORIC_S 0 +#define SSI_ICR_RORIC 0x00000001 +#define SSI_ICR_RORIC_BITN 0 +#define SSI_ICR_RORIC_M 0x00000001 +#define SSI_ICR_RORIC_S 0 //***************************************************************************** // @@ -526,19 +526,18 @@ // // Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is // enabled. -#define SSI_DMACR_TXDMAE 0x00000002 -#define SSI_DMACR_TXDMAE_BITN 1 -#define SSI_DMACR_TXDMAE_M 0x00000002 -#define SSI_DMACR_TXDMAE_S 1 +#define SSI_DMACR_TXDMAE 0x00000002 +#define SSI_DMACR_TXDMAE_BITN 1 +#define SSI_DMACR_TXDMAE_M 0x00000002 +#define SSI_DMACR_TXDMAE_S 1 // Field: [0] RXDMAE // // Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is // enabled. -#define SSI_DMACR_RXDMAE 0x00000001 -#define SSI_DMACR_RXDMAE_BITN 0 -#define SSI_DMACR_RXDMAE_M 0x00000001 -#define SSI_DMACR_RXDMAE_S 0 - +#define SSI_DMACR_RXDMAE 0x00000001 +#define SSI_DMACR_RXDMAE_BITN 0 +#define SSI_DMACR_RXDMAE_M 0x00000001 +#define SSI_DMACR_RXDMAE_S 0 #endif // __SSI__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_sysctl.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_sysctl.h index 1ddd6bb..9a8fada 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_sysctl.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_sysctl.h @@ -1,49 +1,47 @@ /****************************************************************************** -* Filename: hw_sysctl.h -* Revised: 2015-03-16 14:43:45 +0100 (Mon, 16 Mar 2015) -* Revision: 42989 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_sysctl.h + * Revised: 2015-03-16 14:43:45 +0100 (Mon, 16 Mar 2015) + * Revision: 42989 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_SYSCTL_H__ #define __HW_SYSCTL_H__ - //***************************************************************************** // // The following are initial defines for the MCU clock // //***************************************************************************** -#define GET_MCU_CLOCK 48000000 - +#define GET_MCU_CLOCK 48000000 #endif // __HW_SYSCTL_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_trng.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_trng.h index 21aa93c..8f07c40 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_trng.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_trng.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_trng_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_trng_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_TRNG_H__ #define __HW_TRNG_H__ @@ -44,70 +44,70 @@ // //***************************************************************************** // Random Number Lower Word Readout Value -#define TRNG_O_OUT0 0x00000000 +#define TRNG_O_OUT0 0x00000000 // Random Number Upper Word Readout Value -#define TRNG_O_OUT1 0x00000004 +#define TRNG_O_OUT1 0x00000004 // Interrupt Status -#define TRNG_O_IRQFLAGSTAT 0x00000008 +#define TRNG_O_IRQFLAGSTAT 0x00000008 // Interrupt Mask -#define TRNG_O_IRQFLAGMASK 0x0000000C +#define TRNG_O_IRQFLAGMASK 0x0000000C // Interrupt Flag Clear -#define TRNG_O_IRQFLAGCLR 0x00000010 +#define TRNG_O_IRQFLAGCLR 0x00000010 // Control -#define TRNG_O_CTL 0x00000014 +#define TRNG_O_CTL 0x00000014 // Configuration 0 -#define TRNG_O_CFG0 0x00000018 +#define TRNG_O_CFG0 0x00000018 // Alarm Control -#define TRNG_O_ALARMCNT 0x0000001C +#define TRNG_O_ALARMCNT 0x0000001C // FRO Enable -#define TRNG_O_FROEN 0x00000020 +#define TRNG_O_FROEN 0x00000020 // FRO De-tune Bit -#define TRNG_O_FRODETUNE 0x00000024 +#define TRNG_O_FRODETUNE 0x00000024 // Alarm Event -#define TRNG_O_ALARMMASK 0x00000028 +#define TRNG_O_ALARMMASK 0x00000028 // Alarm Shutdown -#define TRNG_O_ALARMSTOP 0x0000002C +#define TRNG_O_ALARMSTOP 0x0000002C // LFSR Readout Value -#define TRNG_O_LFSR0 0x00000030 +#define TRNG_O_LFSR0 0x00000030 // LFSR Readout Value -#define TRNG_O_LFSR1 0x00000034 +#define TRNG_O_LFSR1 0x00000034 // LFSR Readout Value -#define TRNG_O_LFSR2 0x00000038 +#define TRNG_O_LFSR2 0x00000038 // TRNG Engine Options Information -#define TRNG_O_HWOPT 0x00000078 +#define TRNG_O_HWOPT 0x00000078 // HW Version 0 -#define TRNG_O_HWVER0 0x0000007C +#define TRNG_O_HWVER0 0x0000007C // Interrupt Status After Masking -#define TRNG_O_IRQSTATMASK 0x00001FD8 +#define TRNG_O_IRQSTATMASK 0x00001FD8 // HW Version 1 -#define TRNG_O_HWVER1 0x00001FE0 +#define TRNG_O_HWVER1 0x00001FE0 // Interrupt Set -#define TRNG_O_IRQSET 0x00001FEC +#define TRNG_O_IRQSET 0x00001FEC // SW Reset Control -#define TRNG_O_SWRESET 0x00001FF0 +#define TRNG_O_SWRESET 0x00001FF0 // Interrupt Status -#define TRNG_O_IRQSTAT 0x00001FF8 +#define TRNG_O_IRQSTAT 0x00001FF8 //***************************************************************************** // @@ -117,9 +117,9 @@ // Field: [31:0] VALUE_31_0 // // LSW of 64- bit random value. New value ready when IRQFLAGSTAT.RDY = 1. -#define TRNG_OUT0_VALUE_31_0_W 32 -#define TRNG_OUT0_VALUE_31_0_M 0xFFFFFFFF -#define TRNG_OUT0_VALUE_31_0_S 0 +#define TRNG_OUT0_VALUE_31_0_W 32 +#define TRNG_OUT0_VALUE_31_0_M 0xFFFFFFFF +#define TRNG_OUT0_VALUE_31_0_S 0 //***************************************************************************** // @@ -129,9 +129,9 @@ // Field: [31:0] VALUE_63_32 // // MSW of 64-bit random value. New value ready when IRQFLAGSTAT.RDY = 1. -#define TRNG_OUT1_VALUE_63_32_W 32 -#define TRNG_OUT1_VALUE_63_32_M 0xFFFFFFFF -#define TRNG_OUT1_VALUE_63_32_S 0 +#define TRNG_OUT1_VALUE_63_32_W 32 +#define TRNG_OUT1_VALUE_63_32_M 0xFFFFFFFF +#define TRNG_OUT1_VALUE_63_32_S 0 //***************************************************************************** // @@ -144,10 +144,10 @@ // test modes - clocks may not be turned off and the power supply voltage must // be kept stable. // 0: TRNG is idle and can be shut down -#define TRNG_IRQFLAGSTAT_NEED_CLOCK 0x80000000 -#define TRNG_IRQFLAGSTAT_NEED_CLOCK_BITN 31 -#define TRNG_IRQFLAGSTAT_NEED_CLOCK_M 0x80000000 -#define TRNG_IRQFLAGSTAT_NEED_CLOCK_S 31 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK 0x80000000 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_BITN 31 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_M 0x80000000 +#define TRNG_IRQFLAGSTAT_NEED_CLOCK_S 31 // Field: [1] SHUTDOWN_OVF // @@ -155,10 +155,10 @@ // ALARMSTOP register) has exceeded the threshold set by ALARMCNT.SHUTDOWN_THR // // Writing '1' to IRQFLAGCLR.SHUTDOWN_OVF clears this bit to '0' again. -#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF 0x00000002 -#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_BITN 1 -#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_M 0x00000002 -#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_S 1 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_S 1 // Field: [0] RDY // @@ -169,10 +169,10 @@ // If a new number is already available in the internal register of the TRNG, // the number is directly clocked into the result register. In this case the // status bit is asserted again, after one clock cycle. -#define TRNG_IRQFLAGSTAT_RDY 0x00000001 -#define TRNG_IRQFLAGSTAT_RDY_BITN 0 -#define TRNG_IRQFLAGSTAT_RDY_M 0x00000001 -#define TRNG_IRQFLAGSTAT_RDY_S 0 +#define TRNG_IRQFLAGSTAT_RDY 0x00000001 +#define TRNG_IRQFLAGSTAT_RDY_BITN 0 +#define TRNG_IRQFLAGSTAT_RDY_M 0x00000001 +#define TRNG_IRQFLAGSTAT_RDY_S 0 //***************************************************************************** // @@ -183,18 +183,18 @@ // // 1: Allow IRQFLAGSTAT.SHUTDOWN_OVF to activate the interrupt from this // module. -#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF 0x00000002 -#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_BITN 1 -#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_M 0x00000002 -#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_S 1 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_S 1 // Field: [0] RDY // // 1: Allow IRQFLAGSTAT.RDY to activate the interrupt from this module. -#define TRNG_IRQFLAGMASK_RDY 0x00000001 -#define TRNG_IRQFLAGMASK_RDY_BITN 0 -#define TRNG_IRQFLAGMASK_RDY_M 0x00000001 -#define TRNG_IRQFLAGMASK_RDY_S 0 +#define TRNG_IRQFLAGMASK_RDY 0x00000001 +#define TRNG_IRQFLAGMASK_RDY_BITN 0 +#define TRNG_IRQFLAGMASK_RDY_M 0x00000001 +#define TRNG_IRQFLAGMASK_RDY_S 0 //***************************************************************************** // @@ -204,18 +204,18 @@ // Field: [1] SHUTDOWN_OVF // // 1: Clear IRQFLAGSTAT.SHUTDOWN_OVF. -#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF 0x00000002 -#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_BITN 1 -#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_M 0x00000002 -#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_S 1 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_S 1 // Field: [0] RDY // // 1: Clear IRQFLAGSTAT.RDY. -#define TRNG_IRQFLAGCLR_RDY 0x00000001 -#define TRNG_IRQFLAGCLR_RDY_BITN 0 -#define TRNG_IRQFLAGCLR_RDY_M 0x00000001 -#define TRNG_IRQFLAGCLR_RDY_S 0 +#define TRNG_IRQFLAGCLR_RDY 0x00000001 +#define TRNG_IRQFLAGCLR_RDY_BITN 0 +#define TRNG_IRQFLAGCLR_RDY_M 0x00000001 +#define TRNG_IRQFLAGCLR_RDY_S 0 //***************************************************************************** // @@ -241,19 +241,19 @@ // // This field can only be modified while TRNG_EN is 0. If 1 an update will be // ignored. -#define TRNG_CTL_STARTUP_CYCLES_W 16 -#define TRNG_CTL_STARTUP_CYCLES_M 0xFFFF0000 -#define TRNG_CTL_STARTUP_CYCLES_S 16 +#define TRNG_CTL_STARTUP_CYCLES_W 16 +#define TRNG_CTL_STARTUP_CYCLES_M 0xFFFF0000 +#define TRNG_CTL_STARTUP_CYCLES_S 16 // Field: [10] TRNG_EN // // 0: Forces all TRNG logic back into the idle state immediately. // 1: Starts TRNG, gathering entropy from the FROs for the number of samples // determined by STARTUP_CYCLES. -#define TRNG_CTL_TRNG_EN 0x00000400 -#define TRNG_CTL_TRNG_EN_BITN 10 -#define TRNG_CTL_TRNG_EN_M 0x00000400 -#define TRNG_CTL_TRNG_EN_S 10 +#define TRNG_CTL_TRNG_EN 0x00000400 +#define TRNG_CTL_TRNG_EN_BITN 10 +#define TRNG_CTL_TRNG_EN_M 0x00000400 +#define TRNG_CTL_TRNG_EN_S 10 // Field: [2] NO_LFSR_FB // @@ -263,10 +263,10 @@ // // This bit can only be set to '1' when TEST_MODE is also set to '1' and should // not be used for other than test purposes -#define TRNG_CTL_NO_LFSR_FB 0x00000004 -#define TRNG_CTL_NO_LFSR_FB_BITN 2 -#define TRNG_CTL_NO_LFSR_FB_M 0x00000004 -#define TRNG_CTL_NO_LFSR_FB_S 2 +#define TRNG_CTL_NO_LFSR_FB 0x00000004 +#define TRNG_CTL_NO_LFSR_FB_BITN 2 +#define TRNG_CTL_NO_LFSR_FB_M 0x00000004 +#define TRNG_CTL_NO_LFSR_FB_S 2 // Field: [1] TEST_MODE // @@ -277,10 +277,10 @@ // This bit shall not be used unless you need to change the LFSR seed prior to // creating a new random value. All other testing is done external to register // control. -#define TRNG_CTL_TEST_MODE 0x00000002 -#define TRNG_CTL_TEST_MODE_BITN 1 -#define TRNG_CTL_TEST_MODE_M 0x00000002 -#define TRNG_CTL_TEST_MODE_S 1 +#define TRNG_CTL_TEST_MODE 0x00000002 +#define TRNG_CTL_TEST_MODE_BITN 1 +#define TRNG_CTL_TEST_MODE_M 0x00000002 +#define TRNG_CTL_TEST_MODE_S 1 //***************************************************************************** // @@ -306,9 +306,9 @@ // 0xFFFF: 65535*2^8 samples // // This field can only be modified while CTL.TRNG_EN is 0. -#define TRNG_CFG0_MAX_REFILL_CYCLES_W 16 -#define TRNG_CFG0_MAX_REFILL_CYCLES_M 0xFFFF0000 -#define TRNG_CFG0_MAX_REFILL_CYCLES_S 16 +#define TRNG_CFG0_MAX_REFILL_CYCLES_W 16 +#define TRNG_CFG0_MAX_REFILL_CYCLES_M 0xFFFF0000 +#define TRNG_CFG0_MAX_REFILL_CYCLES_S 16 // Field: [11:8] SMPL_DIV // @@ -321,9 +321,9 @@ // conditions) has a cycle time less than twice the sample period. // // This field can only be modified while CTL.TRNG_EN is '0'. -#define TRNG_CFG0_SMPL_DIV_W 4 -#define TRNG_CFG0_SMPL_DIV_M 0x00000F00 -#define TRNG_CFG0_SMPL_DIV_S 8 +#define TRNG_CFG0_SMPL_DIV_W 4 +#define TRNG_CFG0_SMPL_DIV_M 0x00000F00 +#define TRNG_CFG0_SMPL_DIV_S 8 // Field: [7:0] MIN_REFILL_CYCLES // @@ -345,9 +345,9 @@ // 0x02: 2*2^6 samples // ... // 0xFF: 255*2^6 samples -#define TRNG_CFG0_MIN_REFILL_CYCLES_W 8 -#define TRNG_CFG0_MIN_REFILL_CYCLES_M 0x000000FF -#define TRNG_CFG0_MIN_REFILL_CYCLES_S 0 +#define TRNG_CFG0_MIN_REFILL_CYCLES_W 8 +#define TRNG_CFG0_MIN_REFILL_CYCLES_M 0x000000FF +#define TRNG_CFG0_MIN_REFILL_CYCLES_S 0 //***************************************************************************** // @@ -358,17 +358,17 @@ // // Read-only, indicates the number of '1' bits in ALARMSTOP register. // The maximum value equals the number of FROs. -#define TRNG_ALARMCNT_SHUTDOWN_CNT_W 6 -#define TRNG_ALARMCNT_SHUTDOWN_CNT_M 0x3F000000 -#define TRNG_ALARMCNT_SHUTDOWN_CNT_S 24 +#define TRNG_ALARMCNT_SHUTDOWN_CNT_W 6 +#define TRNG_ALARMCNT_SHUTDOWN_CNT_M 0x3F000000 +#define TRNG_ALARMCNT_SHUTDOWN_CNT_S 24 // Field: [20:16] SHUTDOWN_THR // // Threshold setting for generating IRQFLAGSTAT.SHUTDOWN_OVF interrupt. The // interrupt is triggered when SHUTDOWN_CNT value exceeds this bit field. -#define TRNG_ALARMCNT_SHUTDOWN_THR_W 5 -#define TRNG_ALARMCNT_SHUTDOWN_THR_M 0x001F0000 -#define TRNG_ALARMCNT_SHUTDOWN_THR_S 16 +#define TRNG_ALARMCNT_SHUTDOWN_THR_W 5 +#define TRNG_ALARMCNT_SHUTDOWN_THR_M 0x001F0000 +#define TRNG_ALARMCNT_SHUTDOWN_THR_S 16 // Field: [7:0] ALARM_THR // @@ -377,9 +377,9 @@ // samples length) is detected continuously for the number of samples defined // by this field's value. Reset value 0xFF should keep the number of 'alarm // events' to a manageable level. -#define TRNG_ALARMCNT_ALARM_THR_W 8 -#define TRNG_ALARMCNT_ALARM_THR_M 0x000000FF -#define TRNG_ALARMCNT_ALARM_THR_S 0 +#define TRNG_ALARMCNT_ALARM_THR_W 8 +#define TRNG_ALARMCNT_ALARM_THR_M 0x000000FF +#define TRNG_ALARMCNT_ALARM_THR_S 0 //***************************************************************************** // @@ -394,9 +394,9 @@ // // Bits are automatically forced to '0' here (and cannot be written to '1') // while the corresponding bit in ALARMSTOP.FRO_FLAGS has value '1'. -#define TRNG_FROEN_FRO_MASK_W 24 -#define TRNG_FROEN_FRO_MASK_M 0x00FFFFFF -#define TRNG_FROEN_FRO_MASK_S 0 +#define TRNG_FROEN_FRO_MASK_W 24 +#define TRNG_FROEN_FRO_MASK_M 0x00FFFFFF +#define TRNG_FROEN_FRO_MASK_S 0 //***************************************************************************** // @@ -410,9 +410,9 @@ // while the corresponding FRO is turned off (by temporarily writing a '0' in // the corresponding // bit of the FROEN.FRO_MASK register). -#define TRNG_FRODETUNE_FRO_MASK_W 24 -#define TRNG_FRODETUNE_FRO_MASK_M 0x00FFFFFF -#define TRNG_FRODETUNE_FRO_MASK_S 0 +#define TRNG_FRODETUNE_FRO_MASK_W 24 +#define TRNG_FRODETUNE_FRO_MASK_M 0x00FFFFFF +#define TRNG_FRODETUNE_FRO_MASK_S 0 //***************************************************************************** // @@ -423,9 +423,9 @@ // // Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] // indicates FRO 'n' experienced an 'alarm event'. -#define TRNG_ALARMMASK_FRO_MASK_W 24 -#define TRNG_ALARMMASK_FRO_MASK_M 0x00FFFFFF -#define TRNG_ALARMMASK_FRO_MASK_S 0 +#define TRNG_ALARMMASK_FRO_MASK_W 24 +#define TRNG_ALARMMASK_FRO_MASK_M 0x00FFFFFF +#define TRNG_ALARMMASK_FRO_MASK_S 0 //***************************************************************************** // @@ -438,9 +438,9 @@ // indicates FRO 'n' experienced more than one 'alarm event' in quick // succession and has been turned off. A '1' in this field forces the // corresponding bit in FROEN.FRO_MASK to '0'. -#define TRNG_ALARMSTOP_FRO_FLAGS_W 24 -#define TRNG_ALARMSTOP_FRO_FLAGS_M 0x00FFFFFF -#define TRNG_ALARMSTOP_FRO_FLAGS_S 0 +#define TRNG_ALARMSTOP_FRO_FLAGS_W 24 +#define TRNG_ALARMSTOP_FRO_FLAGS_M 0x00FFFFFF +#define TRNG_ALARMSTOP_FRO_FLAGS_S 0 //***************************************************************************** // @@ -452,9 +452,9 @@ // Bits [31:0] of the main entropy accumulation LFSR. Register can only be // accessed when CTL.TEST_MODE = 1. // Register contents will be cleared to zero before access is enabled. -#define TRNG_LFSR0_LFSR_31_0_W 32 -#define TRNG_LFSR0_LFSR_31_0_M 0xFFFFFFFF -#define TRNG_LFSR0_LFSR_31_0_S 0 +#define TRNG_LFSR0_LFSR_31_0_W 32 +#define TRNG_LFSR0_LFSR_31_0_M 0xFFFFFFFF +#define TRNG_LFSR0_LFSR_31_0_S 0 //***************************************************************************** // @@ -466,9 +466,9 @@ // Bits [63:32] of the main entropy accumulation LFSR. Register can only be // accessed when CTL.TEST_MODE = 1. // Register contents will be cleared to zero before access is enabled. -#define TRNG_LFSR1_LFSR_63_32_W 32 -#define TRNG_LFSR1_LFSR_63_32_M 0xFFFFFFFF -#define TRNG_LFSR1_LFSR_63_32_S 0 +#define TRNG_LFSR1_LFSR_63_32_W 32 +#define TRNG_LFSR1_LFSR_63_32_M 0xFFFFFFFF +#define TRNG_LFSR1_LFSR_63_32_S 0 //***************************************************************************** // @@ -480,9 +480,9 @@ // Bits [80:64] of the main entropy accumulation LFSR. Register can only be // accessed when CTL.TEST_MODE = 1. // Register contents will be cleared to zero before access is enabled. -#define TRNG_LFSR2_LFSR_80_64_W 17 -#define TRNG_LFSR2_LFSR_80_64_M 0x0001FFFF -#define TRNG_LFSR2_LFSR_80_64_S 0 +#define TRNG_LFSR2_LFSR_80_64_W 17 +#define TRNG_LFSR2_LFSR_80_64_M 0x0001FFFF +#define TRNG_LFSR2_LFSR_80_64_S 0 //***************************************************************************** // @@ -492,9 +492,9 @@ // Field: [11:6] NR_OF_FROS // // Number of FROs implemented in this TRNG, value 24 (decimal). -#define TRNG_HWOPT_NR_OF_FROS_W 6 -#define TRNG_HWOPT_NR_OF_FROS_M 0x00000FC0 -#define TRNG_HWOPT_NR_OF_FROS_S 6 +#define TRNG_HWOPT_NR_OF_FROS_W 6 +#define TRNG_HWOPT_NR_OF_FROS_M 0x00000FC0 +#define TRNG_HWOPT_NR_OF_FROS_S 6 //***************************************************************************** // @@ -504,38 +504,38 @@ // Field: [27:24] HW_MAJOR_VER // // 4 bits binary encoding of the major hardware revision number. -#define TRNG_HWVER0_HW_MAJOR_VER_W 4 -#define TRNG_HWVER0_HW_MAJOR_VER_M 0x0F000000 -#define TRNG_HWVER0_HW_MAJOR_VER_S 24 +#define TRNG_HWVER0_HW_MAJOR_VER_W 4 +#define TRNG_HWVER0_HW_MAJOR_VER_M 0x0F000000 +#define TRNG_HWVER0_HW_MAJOR_VER_S 24 // Field: [23:20] HW_MINOR_VER // // 4 bits binary encoding of the minor hardware revision number. -#define TRNG_HWVER0_HW_MINOR_VER_W 4 -#define TRNG_HWVER0_HW_MINOR_VER_M 0x00F00000 -#define TRNG_HWVER0_HW_MINOR_VER_S 20 +#define TRNG_HWVER0_HW_MINOR_VER_W 4 +#define TRNG_HWVER0_HW_MINOR_VER_M 0x00F00000 +#define TRNG_HWVER0_HW_MINOR_VER_S 20 // Field: [19:16] HW_PATCH_LVL // // 4 bits binary encoding of the hardware patch level, initial release will // carry value zero. -#define TRNG_HWVER0_HW_PATCH_LVL_W 4 -#define TRNG_HWVER0_HW_PATCH_LVL_M 0x000F0000 -#define TRNG_HWVER0_HW_PATCH_LVL_S 16 +#define TRNG_HWVER0_HW_PATCH_LVL_W 4 +#define TRNG_HWVER0_HW_PATCH_LVL_M 0x000F0000 +#define TRNG_HWVER0_HW_PATCH_LVL_S 16 // Field: [15:8] EIP_NUM_COMPL // // Bit-by-bit logic complement of bits [7:0]. This TRNG gives 0xB4. -#define TRNG_HWVER0_EIP_NUM_COMPL_W 8 -#define TRNG_HWVER0_EIP_NUM_COMPL_M 0x0000FF00 -#define TRNG_HWVER0_EIP_NUM_COMPL_S 8 +#define TRNG_HWVER0_EIP_NUM_COMPL_W 8 +#define TRNG_HWVER0_EIP_NUM_COMPL_M 0x0000FF00 +#define TRNG_HWVER0_EIP_NUM_COMPL_S 8 // Field: [7:0] EIP_NUM // // 8 bits binary encoding of the module number. This TRNG gives 0x4B. -#define TRNG_HWVER0_EIP_NUM_W 8 -#define TRNG_HWVER0_EIP_NUM_M 0x000000FF -#define TRNG_HWVER0_EIP_NUM_S 0 +#define TRNG_HWVER0_EIP_NUM_W 8 +#define TRNG_HWVER0_EIP_NUM_M 0x000000FF +#define TRNG_HWVER0_EIP_NUM_S 0 //***************************************************************************** // @@ -546,19 +546,19 @@ // // Shutdown Overflow (result of IRQFLAGSTAT.SHUTDOWN_OVF AND'ed with // IRQFLAGMASK.SHUTDOWN_OVF) -#define TRNG_IRQSTATMASK_SHUTDOWN_OVF 0x00000002 -#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_BITN 1 -#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_M 0x00000002 -#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_S 1 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF 0x00000002 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_BITN 1 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_M 0x00000002 +#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_S 1 // Field: [0] RDY // // New random value available (result of IRQFLAGSTAT.RDY AND'ed with // IRQFLAGMASK.RDY) -#define TRNG_IRQSTATMASK_RDY 0x00000001 -#define TRNG_IRQSTATMASK_RDY_BITN 0 -#define TRNG_IRQSTATMASK_RDY_M 0x00000001 -#define TRNG_IRQSTATMASK_RDY_S 0 +#define TRNG_IRQSTATMASK_RDY 0x00000001 +#define TRNG_IRQSTATMASK_RDY_BITN 0 +#define TRNG_IRQSTATMASK_RDY_M 0x00000001 +#define TRNG_IRQSTATMASK_RDY_S 0 //***************************************************************************** // @@ -568,9 +568,9 @@ // Field: [7:0] REV // // The revision number of this module is Rev 2.0. -#define TRNG_HWVER1_REV_W 8 -#define TRNG_HWVER1_REV_M 0x000000FF -#define TRNG_HWVER1_REV_S 0 +#define TRNG_HWVER1_REV_W 8 +#define TRNG_HWVER1_REV_M 0x000000FF +#define TRNG_HWVER1_REV_S 0 //***************************************************************************** // @@ -586,10 +586,10 @@ // // Write '1' to soft reset , reset will be low for 4-5 clock cycles. Poll to 0 // for reset to be completed. -#define TRNG_SWRESET_RESET 0x00000001 -#define TRNG_SWRESET_RESET_BITN 0 -#define TRNG_SWRESET_RESET_M 0x00000001 -#define TRNG_SWRESET_RESET_S 0 +#define TRNG_SWRESET_RESET 0x00000001 +#define TRNG_SWRESET_RESET_BITN 0 +#define TRNG_SWRESET_RESET_M 0x00000001 +#define TRNG_SWRESET_RESET_S 0 //***************************************************************************** // @@ -600,10 +600,9 @@ // // TRNG Interrupt status. OR'ed version of IRQFLAGSTAT.SHUTDOWN_OVF and // IRQFLAGSTAT.RDY -#define TRNG_IRQSTAT_STAT 0x00000001 -#define TRNG_IRQSTAT_STAT_BITN 0 -#define TRNG_IRQSTAT_STAT_M 0x00000001 -#define TRNG_IRQSTAT_STAT_S 0 - +#define TRNG_IRQSTAT_STAT 0x00000001 +#define TRNG_IRQSTAT_STAT_BITN 0 +#define TRNG_IRQSTAT_STAT_M 0x00000001 +#define TRNG_IRQSTAT_STAT_S 0 #endif // __TRNG__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_types.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_types.h index 142601b..c92d027 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_types.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_types.h @@ -1,55 +1,55 @@ /****************************************************************************** -* Filename: hw_types.h -* Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) -* Revision: 47152 -* -* Description: Common types and macros. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_types.h + * Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) + * Revision: 47152 + * + * Description: Common types and macros. + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_TYPES_H__ #define __HW_TYPES_H__ -#include -#include #include "../inc/hw_chip_def.h" +#include +#include //***************************************************************************** // // Common driverlib types // //***************************************************************************** -typedef void (* FPTR_VOID_VOID_T) (void); -typedef void (* FPTR_VOID_UINT8_T) (uint8_t); +typedef void (*FPTR_VOID_VOID_T)(void); +typedef void (*FPTR_VOID_UINT8_T)(uint8_t); //***************************************************************************** // @@ -58,7 +58,7 @@ typedef void (* FPTR_VOID_UINT8_T) (uint8_t); // //***************************************************************************** #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline +#define __STATIC_INLINE static inline #endif //***************************************************************************** @@ -66,7 +66,7 @@ typedef void (* FPTR_VOID_UINT8_T) (uint8_t); // C99 types only allows bitfield defintions on certain datatypes. // //***************************************************************************** -typedef unsigned int __UINT32; +typedef unsigned int __UINT32; //***************************************************************************** // @@ -79,19 +79,19 @@ typedef unsigned int __UINT32; // Word (32 bit) access to address x // Read example : my32BitVar = HWREG(base_addr + offset) ; // Write example : HWREG(base_addr + offset) = my32BitVar ; -#define HWREG(x) \ +#define HWREG(x) \ (*((volatile unsigned long *)(x))) // Half word (16 bit) access to address x // Read example : my16BitVar = HWREGH(base_addr + offset) ; // Write example : HWREGH(base_addr + offset) = my16BitVar ; -#define HWREGH(x) \ +#define HWREGH(x) \ (*((volatile unsigned short *)(x))) // Byte (8 bit) access to address x // Read example : my8BitVar = HWREGB(base_addr + offset) ; // Write example : HWREGB(base_addr + offset) = my8BitVar ; -#define HWREGB(x) \ +#define HWREGB(x) \ (*((volatile unsigned char *)(x))) //***************************************************************************** @@ -105,19 +105,18 @@ typedef unsigned int __UINT32; // //***************************************************************************** // Bit-band access to address x bit number b using word access (32 bit) -#define HWREGBITW(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) // Bit-band access to address x bit number b using half word access (16 bit) -#define HWREGBITH(x, b) \ - HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) // Bit-band access to address x bit number b using byte access (8 bit) -#define HWREGBITB(x, b) \ - HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - #endif // __HW_TYPES_H__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_uart.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_uart.h index 05c49a7..69e23ff 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_uart.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_uart.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_uart_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_uart_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_UART_H__ #define __HW_UART_H__ @@ -44,46 +44,46 @@ // //***************************************************************************** // Data -#define UART_O_DR 0x00000000 +#define UART_O_DR 0x00000000 // Status -#define UART_O_RSR 0x00000004 +#define UART_O_RSR 0x00000004 // Error Clear -#define UART_O_ECR 0x00000004 +#define UART_O_ECR 0x00000004 // Flag -#define UART_O_FR 0x00000018 +#define UART_O_FR 0x00000018 // Integer Baud-Rate Divisor -#define UART_O_IBRD 0x00000024 +#define UART_O_IBRD 0x00000024 // Fractional Baud-Rate Divisor -#define UART_O_FBRD 0x00000028 +#define UART_O_FBRD 0x00000028 // Line Control -#define UART_O_LCRH 0x0000002C +#define UART_O_LCRH 0x0000002C // Control -#define UART_O_CTL 0x00000030 +#define UART_O_CTL 0x00000030 // Interrupt FIFO Level Select -#define UART_O_IFLS 0x00000034 +#define UART_O_IFLS 0x00000034 // Interrupt Mask Set/Clear -#define UART_O_IMSC 0x00000038 +#define UART_O_IMSC 0x00000038 // Raw Interrupt Status -#define UART_O_RIS 0x0000003C +#define UART_O_RIS 0x0000003C // Masked Interrupt Status -#define UART_O_MIS 0x00000040 +#define UART_O_MIS 0x00000040 // Interrupt Clear -#define UART_O_ICR 0x00000044 +#define UART_O_ICR 0x00000044 // DMA Control -#define UART_O_DMACTL 0x00000048 +#define UART_O_DMACTL 0x00000048 //***************************************************************************** // @@ -98,10 +98,10 @@ // the FIFO is full, , only the contents of the shift register are overwritten. // This is cleared to 0 once there is an empty space in the FIFO and a new // character can be written to it. -#define UART_DR_OE 0x00000800 -#define UART_DR_OE_BITN 11 -#define UART_DR_OE_M 0x00000800 -#define UART_DR_OE_S 11 +#define UART_DR_OE 0x00000800 +#define UART_DR_OE_BITN 11 +#define UART_DR_OE_M 0x00000800 +#define UART_DR_OE_S 11 // Field: [10] BE // @@ -114,10 +114,10 @@ // break occurs, a 0 character is loaded into the FIFO. The next character is // enabled after the receive data input (UARTRXD input pin) goes to a 1 // (marking state), and the next valid start bit is received. -#define UART_DR_BE 0x00000400 -#define UART_DR_BE_BITN 10 -#define UART_DR_BE_M 0x00000400 -#define UART_DR_BE_S 10 +#define UART_DR_BE 0x00000400 +#define UART_DR_BE_BITN 10 +#define UART_DR_BE_M 0x00000400 +#define UART_DR_BE_S 10 // Field: [9] PE // @@ -126,10 +126,10 @@ // does not match the parity that the LCRH.EPS and LCRH.SPS select. // In FIFO mode, this error is associated with the character at the top of the // FIFO (i.e., the oldest received data character since last read). -#define UART_DR_PE 0x00000200 -#define UART_DR_PE_BITN 9 -#define UART_DR_PE_M 0x00000200 -#define UART_DR_PE_S 9 +#define UART_DR_PE 0x00000200 +#define UART_DR_PE_BITN 9 +#define UART_DR_PE_M 0x00000200 +#define UART_DR_PE_S 9 // Field: [8] FE // @@ -138,10 +138,10 @@ // stop bit (a valid stop bit is 1). // In FIFO mode, this error is associated with the character at the top of the // FIFO (i.e., the oldest received data character since last read). -#define UART_DR_FE 0x00000100 -#define UART_DR_FE_BITN 8 -#define UART_DR_FE_M 0x00000100 -#define UART_DR_FE_S 8 +#define UART_DR_FE 0x00000100 +#define UART_DR_FE_BITN 8 +#define UART_DR_FE_M 0x00000100 +#define UART_DR_FE_S 8 // Field: [7:0] DATA // @@ -149,9 +149,9 @@ // On writes, the transmit data character is pushed into the FIFO. // On reads, the oldest received data character since the last read is // returned. -#define UART_DR_DATA_W 8 -#define UART_DR_DATA_M 0x000000FF -#define UART_DR_DATA_S 0 +#define UART_DR_DATA_W 8 +#define UART_DR_DATA_M 0x000000FF +#define UART_DR_DATA_S 0 //***************************************************************************** // @@ -166,10 +166,10 @@ // the FIFO is full, , only the contents of the shift register are overwritten. // This is cleared to 0 once there is an empty space in the FIFO and a new // character can be written to it. -#define UART_RSR_OE 0x00000008 -#define UART_RSR_OE_BITN 3 -#define UART_RSR_OE_M 0x00000008 -#define UART_RSR_OE_S 3 +#define UART_RSR_OE 0x00000008 +#define UART_RSR_OE_BITN 3 +#define UART_RSR_OE_M 0x00000008 +#define UART_RSR_OE_S 3 // Field: [2] BE // @@ -180,30 +180,30 @@ // When a break occurs, a 0 character is loaded into the FIFO. The next // character is enabled after the receive data input (UARTRXD input pin) goes // to a 1 (marking state), and the next valid start bit is received. -#define UART_RSR_BE 0x00000004 -#define UART_RSR_BE_BITN 2 -#define UART_RSR_BE_M 0x00000004 -#define UART_RSR_BE_S 2 +#define UART_RSR_BE 0x00000004 +#define UART_RSR_BE_BITN 2 +#define UART_RSR_BE_M 0x00000004 +#define UART_RSR_BE_S 2 // Field: [1] PE // // UART Parity Error: // When set to 1, it indicates that the parity of the received data character // does not match the parity that the LCRH.EPS and LCRH.SPS select. -#define UART_RSR_PE 0x00000002 -#define UART_RSR_PE_BITN 1 -#define UART_RSR_PE_M 0x00000002 -#define UART_RSR_PE_S 1 +#define UART_RSR_PE 0x00000002 +#define UART_RSR_PE_BITN 1 +#define UART_RSR_PE_M 0x00000002 +#define UART_RSR_PE_S 1 // Field: [0] FE // // UART Framing Error: // When set to 1, it indicates that the received character did not have a valid // stop bit (a valid stop bit is 1). -#define UART_RSR_FE 0x00000001 -#define UART_RSR_FE_BITN 0 -#define UART_RSR_FE_M 0x00000001 -#define UART_RSR_FE_S 0 +#define UART_RSR_FE 0x00000001 +#define UART_RSR_FE_BITN 0 +#define UART_RSR_FE_M 0x00000001 +#define UART_RSR_FE_S 0 //***************************************************************************** // @@ -214,37 +214,37 @@ // // The framing (FE), parity (PE), break (BE) and overrun (OE) errors are // cleared to 0 by any write to this register. -#define UART_ECR_OE 0x00000008 -#define UART_ECR_OE_BITN 3 -#define UART_ECR_OE_M 0x00000008 -#define UART_ECR_OE_S 3 +#define UART_ECR_OE 0x00000008 +#define UART_ECR_OE_BITN 3 +#define UART_ECR_OE_M 0x00000008 +#define UART_ECR_OE_S 3 // Field: [2] BE // // The framing (FE), parity (PE), break (BE) and overrun (OE) errors are // cleared to 0 by any write to this register. -#define UART_ECR_BE 0x00000004 -#define UART_ECR_BE_BITN 2 -#define UART_ECR_BE_M 0x00000004 -#define UART_ECR_BE_S 2 +#define UART_ECR_BE 0x00000004 +#define UART_ECR_BE_BITN 2 +#define UART_ECR_BE_M 0x00000004 +#define UART_ECR_BE_S 2 // Field: [1] PE // // The framing (FE), parity (PE), break (BE) and overrun (OE) errors are // cleared to 0 by any write to this register. -#define UART_ECR_PE 0x00000002 -#define UART_ECR_PE_BITN 1 -#define UART_ECR_PE_M 0x00000002 -#define UART_ECR_PE_S 1 +#define UART_ECR_PE 0x00000002 +#define UART_ECR_PE_BITN 1 +#define UART_ECR_PE_M 0x00000002 +#define UART_ECR_PE_S 1 // Field: [0] FE // // The framing (FE), parity (PE), break (BE) and overrun (OE) errors are // cleared to 0 by any write to this register. -#define UART_ECR_FE 0x00000001 -#define UART_ECR_FE_BITN 0 -#define UART_ECR_FE_M 0x00000001 -#define UART_ECR_FE_S 0 +#define UART_ECR_FE 0x00000001 +#define UART_ECR_FE_BITN 0 +#define UART_ECR_FE_M 0x00000001 +#define UART_ECR_FE_S 0 //***************************************************************************** // @@ -259,10 +259,10 @@ // register is empty. // - If the FIFO is enabled, this bit is set when the transmit FIFO is empty. // This bit does not indicate if there is data in the transmit shift register. -#define UART_FR_TXFE 0x00000080 -#define UART_FR_TXFE_BITN 7 -#define UART_FR_TXFE_M 0x00000080 -#define UART_FR_TXFE_S 7 +#define UART_FR_TXFE 0x00000080 +#define UART_FR_TXFE_BITN 7 +#define UART_FR_TXFE_M 0x00000080 +#define UART_FR_TXFE_S 7 // Field: [6] RXFF // @@ -271,10 +271,10 @@ // - If the FIFO is disabled, this bit is set when the receive holding // register is full. // - If the FIFO is enabled, this bit is set when the receive FIFO is full. -#define UART_FR_RXFF 0x00000040 -#define UART_FR_RXFF_BITN 6 -#define UART_FR_RXFF_M 0x00000040 -#define UART_FR_RXFF_S 6 +#define UART_FR_RXFF 0x00000040 +#define UART_FR_RXFF_BITN 6 +#define UART_FR_RXFF_M 0x00000040 +#define UART_FR_RXFF_S 6 // Field: [5] TXFF // @@ -284,10 +284,10 @@ // - If the FIFO is disabled, this bit is set when the transmit holding // register is full. // - If the FIFO is enabled, this bit is set when the transmit FIFO is full. -#define UART_FR_TXFF 0x00000020 -#define UART_FR_TXFF_BITN 5 -#define UART_FR_TXFF_M 0x00000020 -#define UART_FR_TXFF_S 5 +#define UART_FR_TXFF 0x00000020 +#define UART_FR_TXFF_BITN 5 +#define UART_FR_TXFF_M 0x00000020 +#define UART_FR_TXFF_S 5 // Field: [4] RXFE // @@ -297,10 +297,10 @@ // - If the FIFO is disabled, this bit is set when the receive holding // register is empty. // - If the FIFO is enabled, this bit is set when the receive FIFO is empty. -#define UART_FR_RXFE 0x00000010 -#define UART_FR_RXFE_BITN 4 -#define UART_FR_RXFE_M 0x00000010 -#define UART_FR_RXFE_S 4 +#define UART_FR_RXFE 0x00000010 +#define UART_FR_RXFE_BITN 4 +#define UART_FR_RXFE_M 0x00000010 +#define UART_FR_RXFE_S 4 // Field: [3] BUSY // @@ -310,20 +310,20 @@ // sent from the shift register. // This bit is set as soon as the transmit FIFO becomes non-empty, regardless // of whether the UART is enabled or not. -#define UART_FR_BUSY 0x00000008 -#define UART_FR_BUSY_BITN 3 -#define UART_FR_BUSY_M 0x00000008 -#define UART_FR_BUSY_S 3 +#define UART_FR_BUSY 0x00000008 +#define UART_FR_BUSY_BITN 3 +#define UART_FR_BUSY_M 0x00000008 +#define UART_FR_BUSY_S 3 // Field: [0] CTS // // Clear To Send: // This bit is the complement of the active-low UART CTS input pin. // That is, the bit is 1 when CTS input pin is LOW. -#define UART_FR_CTS 0x00000001 -#define UART_FR_CTS_BITN 0 -#define UART_FR_CTS_M 0x00000001 -#define UART_FR_CTS_S 0 +#define UART_FR_CTS 0x00000001 +#define UART_FR_CTS_BITN 0 +#define UART_FR_CTS_M 0x00000001 +#define UART_FR_CTS_S 0 //***************************************************************************** // @@ -341,9 +341,9 @@ // illegal. // A valid value must be written to this field before the UART can be used for // RX or TX operations. -#define UART_IBRD_DIVINT_W 16 -#define UART_IBRD_DIVINT_M 0x0000FFFF -#define UART_IBRD_DIVINT_S 0 +#define UART_IBRD_DIVINT_W 16 +#define UART_IBRD_DIVINT_M 0x0000FFFF +#define UART_IBRD_DIVINT_S 0 //***************************************************************************** // @@ -361,9 +361,9 @@ // illegal. // A valid value must be written to this field before the UART can be used for // RX or TX operations. -#define UART_FBRD_DIVFRAC_W 6 -#define UART_FBRD_DIVFRAC_M 0x0000003F -#define UART_FBRD_DIVFRAC_S 0 +#define UART_FBRD_DIVFRAC_W 6 +#define UART_FBRD_DIVFRAC_M 0x0000003F +#define UART_FBRD_DIVFRAC_S 0 //***************************************************************************** // @@ -379,10 +379,10 @@ // the parity bit is transmitted and checked as 1 when EPS = 0). // // This bit has no effect when PEN disables parity checking and generation. -#define UART_LCRH_SPS 0x00000080 -#define UART_LCRH_SPS_BITN 7 -#define UART_LCRH_SPS_M 0x00000080 -#define UART_LCRH_SPS_S 7 +#define UART_LCRH_SPS 0x00000080 +#define UART_LCRH_SPS_BITN 7 +#define UART_LCRH_SPS_M 0x00000080 +#define UART_LCRH_SPS_S 7 // Field: [6:5] WLEN // @@ -394,13 +394,13 @@ // 7 Word Length 7 bits // 6 Word Length 6 bits // 5 Word Length 5 bits -#define UART_LCRH_WLEN_W 2 -#define UART_LCRH_WLEN_M 0x00000060 -#define UART_LCRH_WLEN_S 5 -#define UART_LCRH_WLEN_8 0x00000060 -#define UART_LCRH_WLEN_7 0x00000040 -#define UART_LCRH_WLEN_6 0x00000020 -#define UART_LCRH_WLEN_5 0x00000000 +#define UART_LCRH_WLEN_W 2 +#define UART_LCRH_WLEN_M 0x00000060 +#define UART_LCRH_WLEN_S 5 +#define UART_LCRH_WLEN_8 0x00000060 +#define UART_LCRH_WLEN_7 0x00000040 +#define UART_LCRH_WLEN_6 0x00000020 +#define UART_LCRH_WLEN_5 0x00000000 // Field: [4] FEN // @@ -410,22 +410,22 @@ // (FIFO mode) // DIS FIFOs are disabled (character mode) that is, the // FIFOs become 1-byte-deep holding registers. -#define UART_LCRH_FEN 0x00000010 -#define UART_LCRH_FEN_BITN 4 -#define UART_LCRH_FEN_M 0x00000010 -#define UART_LCRH_FEN_S 4 -#define UART_LCRH_FEN_EN 0x00000010 -#define UART_LCRH_FEN_DIS 0x00000000 +#define UART_LCRH_FEN 0x00000010 +#define UART_LCRH_FEN_BITN 4 +#define UART_LCRH_FEN_M 0x00000010 +#define UART_LCRH_FEN_S 4 +#define UART_LCRH_FEN_EN 0x00000010 +#define UART_LCRH_FEN_DIS 0x00000000 // Field: [3] STP2 // // UART Two Stop Bits Select: // If this bit is set to 1, two stop bits are transmitted at the end of the // frame. The receive logic does not check for two stop bits being received. -#define UART_LCRH_STP2 0x00000008 -#define UART_LCRH_STP2_BITN 3 -#define UART_LCRH_STP2_M 0x00000008 -#define UART_LCRH_STP2_S 3 +#define UART_LCRH_STP2 0x00000008 +#define UART_LCRH_STP2_BITN 3 +#define UART_LCRH_STP2_M 0x00000008 +#define UART_LCRH_STP2_S 3 // Field: [2] EPS // @@ -435,12 +435,12 @@ // even number of 1s in the data and parity bits. // ODD Odd parity: The UART generates or checks for an // odd number of 1s in the data and parity bits. -#define UART_LCRH_EPS 0x00000004 -#define UART_LCRH_EPS_BITN 2 -#define UART_LCRH_EPS_M 0x00000004 -#define UART_LCRH_EPS_S 2 -#define UART_LCRH_EPS_EVEN 0x00000004 -#define UART_LCRH_EPS_ODD 0x00000000 +#define UART_LCRH_EPS 0x00000004 +#define UART_LCRH_EPS_BITN 2 +#define UART_LCRH_EPS_M 0x00000004 +#define UART_LCRH_EPS_S 2 +#define UART_LCRH_EPS_EVEN 0x00000004 +#define UART_LCRH_EPS_ODD 0x00000000 // Field: [1] PEN // @@ -450,12 +450,12 @@ // EN Parity checking and generation is enabled. // DIS Parity is disabled and no parity bit is added to // the data frame -#define UART_LCRH_PEN 0x00000002 -#define UART_LCRH_PEN_BITN 1 -#define UART_LCRH_PEN_M 0x00000002 -#define UART_LCRH_PEN_S 1 -#define UART_LCRH_PEN_EN 0x00000002 -#define UART_LCRH_PEN_DIS 0x00000000 +#define UART_LCRH_PEN 0x00000002 +#define UART_LCRH_PEN_BITN 1 +#define UART_LCRH_PEN_M 0x00000002 +#define UART_LCRH_PEN_S 1 +#define UART_LCRH_PEN_EN 0x00000002 +#define UART_LCRH_PEN_DIS 0x00000000 // Field: [0] BRK // @@ -465,10 +465,10 @@ // proper execution of the break command, the // software must set this bit for at least two complete frames. For normal use, // this bit must be cleared to 0. -#define UART_LCRH_BRK 0x00000001 -#define UART_LCRH_BRK_BITN 0 -#define UART_LCRH_BRK_M 0x00000001 -#define UART_LCRH_BRK_S 0 +#define UART_LCRH_BRK 0x00000001 +#define UART_LCRH_BRK_BITN 0 +#define UART_LCRH_BRK_M 0x00000001 +#define UART_LCRH_BRK_S 0 //***************************************************************************** // @@ -481,12 +481,12 @@ // ENUMs: // EN CTS hardware flow control enabled // DIS CTS hardware flow control disabled -#define UART_CTL_CTSEN 0x00008000 -#define UART_CTL_CTSEN_BITN 15 -#define UART_CTL_CTSEN_M 0x00008000 -#define UART_CTL_CTSEN_S 15 -#define UART_CTL_CTSEN_EN 0x00008000 -#define UART_CTL_CTSEN_DIS 0x00000000 +#define UART_CTL_CTSEN 0x00008000 +#define UART_CTL_CTSEN_BITN 15 +#define UART_CTL_CTSEN_M 0x00008000 +#define UART_CTL_CTSEN_S 15 +#define UART_CTL_CTSEN_EN 0x00008000 +#define UART_CTL_CTSEN_DIS 0x00000000 // Field: [14] RTSEN // @@ -494,22 +494,22 @@ // ENUMs: // EN RTS hardware flow control enabled // DIS RTS hardware flow control disabled -#define UART_CTL_RTSEN 0x00004000 -#define UART_CTL_RTSEN_BITN 14 -#define UART_CTL_RTSEN_M 0x00004000 -#define UART_CTL_RTSEN_S 14 -#define UART_CTL_RTSEN_EN 0x00004000 -#define UART_CTL_RTSEN_DIS 0x00000000 +#define UART_CTL_RTSEN 0x00004000 +#define UART_CTL_RTSEN_BITN 14 +#define UART_CTL_RTSEN_M 0x00004000 +#define UART_CTL_RTSEN_S 14 +#define UART_CTL_RTSEN_EN 0x00004000 +#define UART_CTL_RTSEN_DIS 0x00000000 // Field: [11] RTS // // Request to Send // This bit is the complement of the active-low UART RTS output. That is, when // the bit is programmed to a 1 then RTS output on the pins is LOW. -#define UART_CTL_RTS 0x00000800 -#define UART_CTL_RTS_BITN 11 -#define UART_CTL_RTS_M 0x00000800 -#define UART_CTL_RTS_S 11 +#define UART_CTL_RTS 0x00000800 +#define UART_CTL_RTS_BITN 11 +#define UART_CTL_RTS_M 0x00000800 +#define UART_CTL_RTS_S 11 // Field: [9] RXE // @@ -519,12 +519,12 @@ // ENUMs: // EN UART Receive enabled // DIS UART Receive disabled -#define UART_CTL_RXE 0x00000200 -#define UART_CTL_RXE_BITN 9 -#define UART_CTL_RXE_M 0x00000200 -#define UART_CTL_RXE_S 9 -#define UART_CTL_RXE_EN 0x00000200 -#define UART_CTL_RXE_DIS 0x00000000 +#define UART_CTL_RXE 0x00000200 +#define UART_CTL_RXE_BITN 9 +#define UART_CTL_RXE_M 0x00000200 +#define UART_CTL_RXE_S 9 +#define UART_CTL_RXE_EN 0x00000200 +#define UART_CTL_RXE_DIS 0x00000000 // Field: [8] TXE // @@ -534,12 +534,12 @@ // ENUMs: // EN UART Transmit enabled // DIS UART Transmit disabled -#define UART_CTL_TXE 0x00000100 -#define UART_CTL_TXE_BITN 8 -#define UART_CTL_TXE_M 0x00000100 -#define UART_CTL_TXE_S 8 -#define UART_CTL_TXE_EN 0x00000100 -#define UART_CTL_TXE_DIS 0x00000000 +#define UART_CTL_TXE 0x00000100 +#define UART_CTL_TXE_BITN 8 +#define UART_CTL_TXE_M 0x00000100 +#define UART_CTL_TXE_S 8 +#define UART_CTL_TXE_EN 0x00000100 +#define UART_CTL_TXE_DIS 0x00000000 // Field: [7] LBE // @@ -549,12 +549,12 @@ // ENUMs: // EN Loop Back enabled // DIS Loop Back disabled -#define UART_CTL_LBE 0x00000080 -#define UART_CTL_LBE_BITN 7 -#define UART_CTL_LBE_M 0x00000080 -#define UART_CTL_LBE_S 7 -#define UART_CTL_LBE_EN 0x00000080 -#define UART_CTL_LBE_DIS 0x00000000 +#define UART_CTL_LBE 0x00000080 +#define UART_CTL_LBE_BITN 7 +#define UART_CTL_LBE_M 0x00000080 +#define UART_CTL_LBE_S 7 +#define UART_CTL_LBE_EN 0x00000080 +#define UART_CTL_LBE_DIS 0x00000000 // Field: [0] UARTEN // @@ -562,12 +562,12 @@ // ENUMs: // EN UART enabled // DIS UART disabled -#define UART_CTL_UARTEN 0x00000001 -#define UART_CTL_UARTEN_BITN 0 -#define UART_CTL_UARTEN_M 0x00000001 -#define UART_CTL_UARTEN_S 0 -#define UART_CTL_UARTEN_EN 0x00000001 -#define UART_CTL_UARTEN_DIS 0x00000000 +#define UART_CTL_UARTEN 0x00000001 +#define UART_CTL_UARTEN_BITN 0 +#define UART_CTL_UARTEN_M 0x00000001 +#define UART_CTL_UARTEN_S 0 +#define UART_CTL_UARTEN_EN 0x00000001 +#define UART_CTL_UARTEN_DIS 0x00000000 //***************************************************************************** // @@ -585,14 +585,14 @@ // 4_8 Receive FIFO becomes >= 1/2 full // 2_8 Receive FIFO becomes >= 1/4 full // 1_8 Receive FIFO becomes >= 1/8 full -#define UART_IFLS_RXSEL_W 3 -#define UART_IFLS_RXSEL_M 0x00000038 -#define UART_IFLS_RXSEL_S 3 -#define UART_IFLS_RXSEL_7_8 0x00000020 -#define UART_IFLS_RXSEL_6_8 0x00000018 -#define UART_IFLS_RXSEL_4_8 0x00000010 -#define UART_IFLS_RXSEL_2_8 0x00000008 -#define UART_IFLS_RXSEL_1_8 0x00000000 +#define UART_IFLS_RXSEL_W 3 +#define UART_IFLS_RXSEL_M 0x00000038 +#define UART_IFLS_RXSEL_S 3 +#define UART_IFLS_RXSEL_7_8 0x00000020 +#define UART_IFLS_RXSEL_6_8 0x00000018 +#define UART_IFLS_RXSEL_4_8 0x00000010 +#define UART_IFLS_RXSEL_2_8 0x00000008 +#define UART_IFLS_RXSEL_1_8 0x00000000 // Field: [2:0] TXSEL // @@ -605,14 +605,14 @@ // 4_8 Transmit FIFO becomes <= 1/2 full // 2_8 Transmit FIFO becomes <= 1/4 full // 1_8 Transmit FIFO becomes <= 1/8 full -#define UART_IFLS_TXSEL_W 3 -#define UART_IFLS_TXSEL_M 0x00000007 -#define UART_IFLS_TXSEL_S 0 -#define UART_IFLS_TXSEL_7_8 0x00000004 -#define UART_IFLS_TXSEL_6_8 0x00000003 -#define UART_IFLS_TXSEL_4_8 0x00000002 -#define UART_IFLS_TXSEL_2_8 0x00000001 -#define UART_IFLS_TXSEL_1_8 0x00000000 +#define UART_IFLS_TXSEL_W 3 +#define UART_IFLS_TXSEL_M 0x00000007 +#define UART_IFLS_TXSEL_S 0 +#define UART_IFLS_TXSEL_7_8 0x00000004 +#define UART_IFLS_TXSEL_6_8 0x00000003 +#define UART_IFLS_TXSEL_4_8 0x00000002 +#define UART_IFLS_TXSEL_2_8 0x00000001 +#define UART_IFLS_TXSEL_1_8 0x00000000 //***************************************************************************** // @@ -626,10 +626,10 @@ // interrupt is set which means the interrupt state will be reflected in // MIS.OEMIS. A write of 0 clears the mask which means MIS.OEMIS will not // reflect the interrupt. -#define UART_IMSC_OEIM 0x00000400 -#define UART_IMSC_OEIM_BITN 10 -#define UART_IMSC_OEIM_M 0x00000400 -#define UART_IMSC_OEIM_S 10 +#define UART_IMSC_OEIM 0x00000400 +#define UART_IMSC_OEIM_BITN 10 +#define UART_IMSC_OEIM_M 0x00000400 +#define UART_IMSC_OEIM_S 10 // Field: [9] BEIM // @@ -637,10 +637,10 @@ // error interrupt. On a write of 1, the mask of the overrun error interrupt is // set which means the interrupt state will be reflected in MIS.BEMIS. A write // of 0 clears the mask which means MIS.BEMIS will not reflect the interrupt. -#define UART_IMSC_BEIM 0x00000200 -#define UART_IMSC_BEIM_BITN 9 -#define UART_IMSC_BEIM_M 0x00000200 -#define UART_IMSC_BEIM_S 9 +#define UART_IMSC_BEIM 0x00000200 +#define UART_IMSC_BEIM_BITN 9 +#define UART_IMSC_BEIM_M 0x00000200 +#define UART_IMSC_BEIM_S 9 // Field: [8] PEIM // @@ -649,10 +649,10 @@ // interrupt is set which means the interrupt state will be reflected in // MIS.PEMIS. A write of 0 clears the mask which means MIS.PEMIS will not // reflect the interrupt. -#define UART_IMSC_PEIM 0x00000100 -#define UART_IMSC_PEIM_BITN 8 -#define UART_IMSC_PEIM_M 0x00000100 -#define UART_IMSC_PEIM_S 8 +#define UART_IMSC_PEIM 0x00000100 +#define UART_IMSC_PEIM_BITN 8 +#define UART_IMSC_PEIM_M 0x00000100 +#define UART_IMSC_PEIM_S 8 // Field: [7] FEIM // @@ -661,10 +661,10 @@ // interrupt is set which means the interrupt state will be reflected in // MIS.FEMIS. A write of 0 clears the mask which means MIS.FEMIS will not // reflect the interrupt. -#define UART_IMSC_FEIM 0x00000080 -#define UART_IMSC_FEIM_BITN 7 -#define UART_IMSC_FEIM_M 0x00000080 -#define UART_IMSC_FEIM_S 7 +#define UART_IMSC_FEIM 0x00000080 +#define UART_IMSC_FEIM_BITN 7 +#define UART_IMSC_FEIM_M 0x00000080 +#define UART_IMSC_FEIM_S 7 // Field: [6] RTIM // @@ -676,10 +676,10 @@ // The raw interrupt for receive timeout RIS.RTRIS cannot be set unless the // mask is set (RTIM = 1). This is because the mask acts as an enable for power // saving. That is, the same status can be read from MIS.RTMIS and RIS.RTRIS. -#define UART_IMSC_RTIM 0x00000040 -#define UART_IMSC_RTIM_BITN 6 -#define UART_IMSC_RTIM_M 0x00000040 -#define UART_IMSC_RTIM_S 6 +#define UART_IMSC_RTIM 0x00000040 +#define UART_IMSC_RTIM_BITN 6 +#define UART_IMSC_RTIM_M 0x00000040 +#define UART_IMSC_RTIM_S 6 // Field: [5] TXIM // @@ -687,10 +687,10 @@ // interrupt. On a write of 1, the mask of the overrun error interrupt is set // which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 // clears the mask which means MIS.TXMIS will not reflect the interrupt. -#define UART_IMSC_TXIM 0x00000020 -#define UART_IMSC_TXIM_BITN 5 -#define UART_IMSC_TXIM_M 0x00000020 -#define UART_IMSC_TXIM_S 5 +#define UART_IMSC_TXIM 0x00000020 +#define UART_IMSC_TXIM_BITN 5 +#define UART_IMSC_TXIM_M 0x00000020 +#define UART_IMSC_TXIM_S 5 // Field: [4] RXIM // @@ -698,10 +698,10 @@ // interrupt. On a write of 1, the mask of the overrun error interrupt is set // which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 // clears the mask which means MIS.RXMIS will not reflect the interrupt. -#define UART_IMSC_RXIM 0x00000010 -#define UART_IMSC_RXIM_BITN 4 -#define UART_IMSC_RXIM_M 0x00000010 -#define UART_IMSC_RXIM_S 4 +#define UART_IMSC_RXIM 0x00000010 +#define UART_IMSC_RXIM_BITN 4 +#define UART_IMSC_RXIM_M 0x00000010 +#define UART_IMSC_RXIM_S 4 // Field: [1] CTSMIM // @@ -710,10 +710,10 @@ // error interrupt is set which means the interrupt state will be reflected in // MIS.CTSMMIS. A write of 0 clears the mask which means MIS.CTSMMIS will not // reflect the interrupt. -#define UART_IMSC_CTSMIM 0x00000002 -#define UART_IMSC_CTSMIM_BITN 1 -#define UART_IMSC_CTSMIM_M 0x00000002 -#define UART_IMSC_CTSMIM_S 1 +#define UART_IMSC_CTSMIM 0x00000002 +#define UART_IMSC_CTSMIM_BITN 1 +#define UART_IMSC_CTSMIM_M 0x00000002 +#define UART_IMSC_CTSMIM_S 1 //***************************************************************************** // @@ -726,10 +726,10 @@ // This field returns the raw interrupt state of UART's overrun error // interrupt. Overrun error occurs if data is received and the receive FIFO is // full. -#define UART_RIS_OERIS 0x00000400 -#define UART_RIS_OERIS_BITN 10 -#define UART_RIS_OERIS_M 0x00000400 -#define UART_RIS_OERIS_S 10 +#define UART_RIS_OERIS 0x00000400 +#define UART_RIS_OERIS_BITN 10 +#define UART_RIS_OERIS_M 0x00000400 +#define UART_RIS_OERIS_S 10 // Field: [9] BERIS // @@ -738,10 +738,10 @@ // Break error is set when a break condition is detected, indicating that the // received data input (UARTRXD input pin) was held LOW for longer than a // full-word transmission time (defined as start, data, parity and stop bits). -#define UART_RIS_BERIS 0x00000200 -#define UART_RIS_BERIS_BITN 9 -#define UART_RIS_BERIS_M 0x00000200 -#define UART_RIS_BERIS_S 9 +#define UART_RIS_BERIS 0x00000200 +#define UART_RIS_BERIS_BITN 9 +#define UART_RIS_BERIS_M 0x00000200 +#define UART_RIS_BERIS_S 9 // Field: [8] PERIS // @@ -749,10 +749,10 @@ // This field returns the raw interrupt state of UART's parity error interrupt. // Parity error is set if the parity of the received data character does not // match the parity that the LCRH.EPS and LCRH.SPS select. -#define UART_RIS_PERIS 0x00000100 -#define UART_RIS_PERIS_BITN 8 -#define UART_RIS_PERIS_M 0x00000100 -#define UART_RIS_PERIS_S 8 +#define UART_RIS_PERIS 0x00000100 +#define UART_RIS_PERIS_BITN 8 +#define UART_RIS_PERIS_M 0x00000100 +#define UART_RIS_PERIS_S 8 // Field: [7] FERIS // @@ -760,10 +760,10 @@ // This field returns the raw interrupt state of UART's framing error // interrupt. Framing error is set if the received character does not have a // valid stop bit (a valid stop bit is 1). -#define UART_RIS_FERIS 0x00000080 -#define UART_RIS_FERIS_BITN 7 -#define UART_RIS_FERIS_M 0x00000080 -#define UART_RIS_FERIS_S 7 +#define UART_RIS_FERIS 0x00000080 +#define UART_RIS_FERIS_BITN 7 +#define UART_RIS_FERIS_M 0x00000080 +#define UART_RIS_FERIS_S 7 // Field: [6] RTRIS // @@ -776,10 +776,10 @@ // The raw interrupt for receive timeout cannot be set unless the mask is set // (IMSC.RTIM = 1). This is because the mask acts as an enable for power // saving. That is, the same status can be read from MIS.RTMIS and RTRIS. -#define UART_RIS_RTRIS 0x00000040 -#define UART_RIS_RTRIS_BITN 6 -#define UART_RIS_RTRIS_M 0x00000040 -#define UART_RIS_RTRIS_S 6 +#define UART_RIS_RTRIS 0x00000040 +#define UART_RIS_RTRIS_BITN 6 +#define UART_RIS_RTRIS_M 0x00000040 +#define UART_RIS_RTRIS_S 6 // Field: [5] TXRIS // @@ -794,10 +794,10 @@ // location, the transmit interrupt is asserted if there is no data present in // the transmitters single location. It is cleared by performing a single write // to the transmit FIFO, or by clearing the interrupt through ICR.TXIC. -#define UART_RIS_TXRIS 0x00000020 -#define UART_RIS_TXRIS_BITN 5 -#define UART_RIS_TXRIS_M 0x00000020 -#define UART_RIS_TXRIS_S 5 +#define UART_RIS_TXRIS 0x00000020 +#define UART_RIS_TXRIS_BITN 5 +#define UART_RIS_TXRIS_M 0x00000020 +#define UART_RIS_TXRIS_S 5 // Field: [4] RXRIS // @@ -813,20 +813,20 @@ // thereby filling the location. The receive interrupt is cleared by performing // a single read of the receive FIFO, or by clearing the interrupt through // ICR.RXIC. -#define UART_RIS_RXRIS 0x00000010 -#define UART_RIS_RXRIS_BITN 4 -#define UART_RIS_RXRIS_M 0x00000010 -#define UART_RIS_RXRIS_S 4 +#define UART_RIS_RXRIS 0x00000010 +#define UART_RIS_RXRIS_BITN 4 +#define UART_RIS_RXRIS_M 0x00000010 +#define UART_RIS_RXRIS_S 4 // Field: [1] CTSRMIS // // Clear to Send (CTS) modem interrupt status: // This field returns the raw interrupt state of UART's clear to send // interrupt. -#define UART_RIS_CTSRMIS 0x00000002 -#define UART_RIS_CTSRMIS_BITN 1 -#define UART_RIS_CTSRMIS_M 0x00000002 -#define UART_RIS_CTSRMIS_S 1 +#define UART_RIS_CTSRMIS 0x00000002 +#define UART_RIS_CTSRMIS_BITN 1 +#define UART_RIS_CTSRMIS_M 0x00000002 +#define UART_RIS_CTSRMIS_S 1 //***************************************************************************** // @@ -839,10 +839,10 @@ // This field returns the masked interrupt state of the overrun interrupt which // is the AND product of raw interrupt state RIS.OERIS and the mask setting // IMSC.OEIM. -#define UART_MIS_OEMIS 0x00000400 -#define UART_MIS_OEMIS_BITN 10 -#define UART_MIS_OEMIS_M 0x00000400 -#define UART_MIS_OEMIS_S 10 +#define UART_MIS_OEMIS 0x00000400 +#define UART_MIS_OEMIS_BITN 10 +#define UART_MIS_OEMIS_M 0x00000400 +#define UART_MIS_OEMIS_S 10 // Field: [9] BEMIS // @@ -850,10 +850,10 @@ // This field returns the masked interrupt state of the break error interrupt // which is the AND product of raw interrupt state RIS.BERIS and the mask // setting IMSC.BEIM. -#define UART_MIS_BEMIS 0x00000200 -#define UART_MIS_BEMIS_BITN 9 -#define UART_MIS_BEMIS_M 0x00000200 -#define UART_MIS_BEMIS_S 9 +#define UART_MIS_BEMIS 0x00000200 +#define UART_MIS_BEMIS_BITN 9 +#define UART_MIS_BEMIS_M 0x00000200 +#define UART_MIS_BEMIS_S 9 // Field: [8] PEMIS // @@ -861,20 +861,20 @@ // This field returns the masked interrupt state of the parity error interrupt // which is the AND product of raw interrupt state RIS.PERIS and the mask // setting IMSC.PEIM. -#define UART_MIS_PEMIS 0x00000100 -#define UART_MIS_PEMIS_BITN 8 -#define UART_MIS_PEMIS_M 0x00000100 -#define UART_MIS_PEMIS_S 8 +#define UART_MIS_PEMIS 0x00000100 +#define UART_MIS_PEMIS_BITN 8 +#define UART_MIS_PEMIS_M 0x00000100 +#define UART_MIS_PEMIS_S 8 // Field: [7] FEMIS // // Framing error masked interrupt status: Returns the masked interrupt state of // the framing error interrupt which is the AND product of raw interrupt state // RIS.FERIS and the mask setting IMSC.FEIM. -#define UART_MIS_FEMIS 0x00000080 -#define UART_MIS_FEMIS_BITN 7 -#define UART_MIS_FEMIS_M 0x00000080 -#define UART_MIS_FEMIS_S 7 +#define UART_MIS_FEMIS 0x00000080 +#define UART_MIS_FEMIS_BITN 7 +#define UART_MIS_FEMIS_M 0x00000080 +#define UART_MIS_FEMIS_S 7 // Field: [6] RTMIS // @@ -883,10 +883,10 @@ // The raw interrupt for receive timeout cannot be set unless the mask is set // (IMSC.RTIM = 1). This is because the mask acts as an enable for power // saving. That is, the same status can be read from RTMIS and RIS.RTRIS. -#define UART_MIS_RTMIS 0x00000040 -#define UART_MIS_RTMIS_BITN 6 -#define UART_MIS_RTMIS_M 0x00000040 -#define UART_MIS_RTMIS_S 6 +#define UART_MIS_RTMIS 0x00000040 +#define UART_MIS_RTMIS_BITN 6 +#define UART_MIS_RTMIS_M 0x00000040 +#define UART_MIS_RTMIS_S 6 // Field: [5] TXMIS // @@ -894,10 +894,10 @@ // This field returns the masked interrupt state of the transmit interrupt // which is the AND product of raw interrupt state RIS.TXRIS and the mask // setting IMSC.TXIM. -#define UART_MIS_TXMIS 0x00000020 -#define UART_MIS_TXMIS_BITN 5 -#define UART_MIS_TXMIS_M 0x00000020 -#define UART_MIS_TXMIS_S 5 +#define UART_MIS_TXMIS 0x00000020 +#define UART_MIS_TXMIS_BITN 5 +#define UART_MIS_TXMIS_M 0x00000020 +#define UART_MIS_TXMIS_S 5 // Field: [4] RXMIS // @@ -905,10 +905,10 @@ // This field returns the masked interrupt state of the receive interrupt // which is the AND product of raw interrupt state RIS.RXRIS and the mask // setting IMSC.RXIM. -#define UART_MIS_RXMIS 0x00000010 -#define UART_MIS_RXMIS_BITN 4 -#define UART_MIS_RXMIS_M 0x00000010 -#define UART_MIS_RXMIS_S 4 +#define UART_MIS_RXMIS 0x00000010 +#define UART_MIS_RXMIS_BITN 4 +#define UART_MIS_RXMIS_M 0x00000010 +#define UART_MIS_RXMIS_S 4 // Field: [1] CTSMMIS // @@ -916,10 +916,10 @@ // This field returns the masked interrupt state of the clear to send interrupt // which is the AND product of raw interrupt state RIS.CTSRMIS and the mask // setting IMSC.CTSMIM. -#define UART_MIS_CTSMMIS 0x00000002 -#define UART_MIS_CTSMMIS_BITN 1 -#define UART_MIS_CTSMMIS_M 0x00000002 -#define UART_MIS_CTSMMIS_S 1 +#define UART_MIS_CTSMMIS 0x00000002 +#define UART_MIS_CTSMMIS_BITN 1 +#define UART_MIS_CTSMMIS_M 0x00000002 +#define UART_MIS_CTSMMIS_S 1 //***************************************************************************** // @@ -931,80 +931,80 @@ // Overrun error interrupt clear: // Writing 1 to this field clears the overrun error interrupt (RIS.OERIS). // Writing 0 has no effect. -#define UART_ICR_OEIC 0x00000400 -#define UART_ICR_OEIC_BITN 10 -#define UART_ICR_OEIC_M 0x00000400 -#define UART_ICR_OEIC_S 10 +#define UART_ICR_OEIC 0x00000400 +#define UART_ICR_OEIC_BITN 10 +#define UART_ICR_OEIC_M 0x00000400 +#define UART_ICR_OEIC_S 10 // Field: [9] BEIC // // Break error interrupt clear: // Writing 1 to this field clears the break error interrupt (RIS.BERIS). // Writing 0 has no effect. -#define UART_ICR_BEIC 0x00000200 -#define UART_ICR_BEIC_BITN 9 -#define UART_ICR_BEIC_M 0x00000200 -#define UART_ICR_BEIC_S 9 +#define UART_ICR_BEIC 0x00000200 +#define UART_ICR_BEIC_BITN 9 +#define UART_ICR_BEIC_M 0x00000200 +#define UART_ICR_BEIC_S 9 // Field: [8] PEIC // // Parity error interrupt clear: // Writing 1 to this field clears the parity error interrupt (RIS.PERIS). // Writing 0 has no effect. -#define UART_ICR_PEIC 0x00000100 -#define UART_ICR_PEIC_BITN 8 -#define UART_ICR_PEIC_M 0x00000100 -#define UART_ICR_PEIC_S 8 +#define UART_ICR_PEIC 0x00000100 +#define UART_ICR_PEIC_BITN 8 +#define UART_ICR_PEIC_M 0x00000100 +#define UART_ICR_PEIC_S 8 // Field: [7] FEIC // // Framing error interrupt clear: // Writing 1 to this field clears the framing error interrupt (RIS.FERIS). // Writing 0 has no effect. -#define UART_ICR_FEIC 0x00000080 -#define UART_ICR_FEIC_BITN 7 -#define UART_ICR_FEIC_M 0x00000080 -#define UART_ICR_FEIC_S 7 +#define UART_ICR_FEIC 0x00000080 +#define UART_ICR_FEIC_BITN 7 +#define UART_ICR_FEIC_M 0x00000080 +#define UART_ICR_FEIC_S 7 // Field: [6] RTIC // // Receive timeout interrupt clear: // Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS). // Writing 0 has no effect. -#define UART_ICR_RTIC 0x00000040 -#define UART_ICR_RTIC_BITN 6 -#define UART_ICR_RTIC_M 0x00000040 -#define UART_ICR_RTIC_S 6 +#define UART_ICR_RTIC 0x00000040 +#define UART_ICR_RTIC_BITN 6 +#define UART_ICR_RTIC_M 0x00000040 +#define UART_ICR_RTIC_S 6 // Field: [5] TXIC // // Transmit interrupt clear: // Writing 1 to this field clears the transmit interrupt (RIS.TXRIS). Writing 0 // has no effect. -#define UART_ICR_TXIC 0x00000020 -#define UART_ICR_TXIC_BITN 5 -#define UART_ICR_TXIC_M 0x00000020 -#define UART_ICR_TXIC_S 5 +#define UART_ICR_TXIC 0x00000020 +#define UART_ICR_TXIC_BITN 5 +#define UART_ICR_TXIC_M 0x00000020 +#define UART_ICR_TXIC_S 5 // Field: [4] RXIC // // Receive interrupt clear: // Writing 1 to this field clears the receive interrupt (RIS.RXRIS). Writing 0 // has no effect. -#define UART_ICR_RXIC 0x00000010 -#define UART_ICR_RXIC_BITN 4 -#define UART_ICR_RXIC_M 0x00000010 -#define UART_ICR_RXIC_S 4 +#define UART_ICR_RXIC 0x00000010 +#define UART_ICR_RXIC_BITN 4 +#define UART_ICR_RXIC_M 0x00000010 +#define UART_ICR_RXIC_S 4 // Field: [1] CTSMIC // // Clear to Send (CTS) modem interrupt clear: // Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS). // Writing 0 has no effect. -#define UART_ICR_CTSMIC 0x00000002 -#define UART_ICR_CTSMIC_BITN 1 -#define UART_ICR_CTSMIC_M 0x00000002 -#define UART_ICR_CTSMIC_S 1 +#define UART_ICR_CTSMIC 0x00000002 +#define UART_ICR_CTSMIC_BITN 1 +#define UART_ICR_CTSMIC_M 0x00000002 +#define UART_ICR_CTSMIC_S 1 //***************************************************************************** // @@ -1017,28 +1017,27 @@ // single and burst requests) are disabled when the UART error interrupt is // asserted (more specifically if any of the error interrupts RIS.PERIS, // RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted). -#define UART_DMACTL_DMAONERR 0x00000004 -#define UART_DMACTL_DMAONERR_BITN 2 -#define UART_DMACTL_DMAONERR_M 0x00000004 -#define UART_DMACTL_DMAONERR_S 2 +#define UART_DMACTL_DMAONERR 0x00000004 +#define UART_DMACTL_DMAONERR_BITN 2 +#define UART_DMACTL_DMAONERR_M 0x00000004 +#define UART_DMACTL_DMAONERR_S 2 // Field: [1] TXDMAE // // Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is // enabled. -#define UART_DMACTL_TXDMAE 0x00000002 -#define UART_DMACTL_TXDMAE_BITN 1 -#define UART_DMACTL_TXDMAE_M 0x00000002 -#define UART_DMACTL_TXDMAE_S 1 +#define UART_DMACTL_TXDMAE 0x00000002 +#define UART_DMACTL_TXDMAE_BITN 1 +#define UART_DMACTL_TXDMAE_M 0x00000002 +#define UART_DMACTL_TXDMAE_S 1 // Field: [0] RXDMAE // // Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is // enabled. -#define UART_DMACTL_RXDMAE 0x00000001 -#define UART_DMACTL_RXDMAE_BITN 0 -#define UART_DMACTL_RXDMAE_M 0x00000001 -#define UART_DMACTL_RXDMAE_S 0 - +#define UART_DMACTL_RXDMAE 0x00000001 +#define UART_DMACTL_RXDMAE_BITN 0 +#define UART_DMACTL_RXDMAE_M 0x00000001 +#define UART_DMACTL_RXDMAE_S 0 #endif // __UART__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_udma.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_udma.h index 63d0a54..84ebe4d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_udma.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_udma.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_udma_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_udma_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_UDMA_H__ #define __HW_UDMA_H__ @@ -44,61 +44,61 @@ // //***************************************************************************** // Status -#define UDMA_O_STATUS 0x00000000 +#define UDMA_O_STATUS 0x00000000 // Configuration -#define UDMA_O_CFG 0x00000004 +#define UDMA_O_CFG 0x00000004 // Channel Control Data Base Pointer -#define UDMA_O_CTRL 0x00000008 +#define UDMA_O_CTRL 0x00000008 // Channel Alternate Control Data Base Pointer -#define UDMA_O_ALTCTRL 0x0000000C +#define UDMA_O_ALTCTRL 0x0000000C // Channel Wait On Request Status -#define UDMA_O_WAITONREQ 0x00000010 +#define UDMA_O_WAITONREQ 0x00000010 // Channel Software Request -#define UDMA_O_SOFTREQ 0x00000014 +#define UDMA_O_SOFTREQ 0x00000014 // Channel Set UseBurst -#define UDMA_O_SETBURST 0x00000018 +#define UDMA_O_SETBURST 0x00000018 // Channel Clear UseBurst -#define UDMA_O_CLEARBURST 0x0000001C +#define UDMA_O_CLEARBURST 0x0000001C // Channel Set Request Mask -#define UDMA_O_SETREQMASK 0x00000020 +#define UDMA_O_SETREQMASK 0x00000020 // Clear Channel Request Mask -#define UDMA_O_CLEARREQMASK 0x00000024 +#define UDMA_O_CLEARREQMASK 0x00000024 // Set Channel Enable -#define UDMA_O_SETCHANNELEN 0x00000028 +#define UDMA_O_SETCHANNELEN 0x00000028 // Clear Channel Enable -#define UDMA_O_CLEARCHANNELEN 0x0000002C +#define UDMA_O_CLEARCHANNELEN 0x0000002C // Channel Set Primary-Alternate -#define UDMA_O_SETCHNLPRIALT 0x00000030 +#define UDMA_O_SETCHNLPRIALT 0x00000030 // Channel Clear Primary-Alternate -#define UDMA_O_CLEARCHNLPRIALT 0x00000034 +#define UDMA_O_CLEARCHNLPRIALT 0x00000034 // Set Channel Priority -#define UDMA_O_SETCHNLPRIORITY 0x00000038 +#define UDMA_O_SETCHNLPRIORITY 0x00000038 // Clear Channel Priority -#define UDMA_O_CLEARCHNLPRIORITY 0x0000003C +#define UDMA_O_CLEARCHNLPRIORITY 0x0000003C // Error Status and Clear -#define UDMA_O_ERROR 0x0000004C +#define UDMA_O_ERROR 0x0000004C // Channel Request Done -#define UDMA_O_REQDONE 0x00000504 +#define UDMA_O_REQDONE 0x00000504 // Channel Request Done Mask -#define UDMA_O_DONEMASK 0x00000520 +#define UDMA_O_DONEMASK 0x00000520 //***************************************************************************** // @@ -113,9 +113,9 @@ // 0x2: Undefined // ... // 0xF: Undefined -#define UDMA_STATUS_TEST_W 4 -#define UDMA_STATUS_TEST_M 0xF0000000 -#define UDMA_STATUS_TEST_S 28 +#define UDMA_STATUS_TEST_W 4 +#define UDMA_STATUS_TEST_M 0xF0000000 +#define UDMA_STATUS_TEST_S 28 // Field: [20:16] TOTALCHANNELS // @@ -127,9 +127,9 @@ // ... // 0x1F: Shows that the controller is configured to use 32 uDMA channels // (32-1=31=0x1F) -#define UDMA_STATUS_TOTALCHANNELS_W 5 -#define UDMA_STATUS_TOTALCHANNELS_M 0x001F0000 -#define UDMA_STATUS_TOTALCHANNELS_S 16 +#define UDMA_STATUS_TOTALCHANNELS_W 5 +#define UDMA_STATUS_TOTALCHANNELS_M 0x001F0000 +#define UDMA_STATUS_TOTALCHANNELS_S 16 // Field: [7:4] STATE // @@ -150,9 +150,9 @@ // 0xB: Undefined // ... // 0xF: Undefined. -#define UDMA_STATUS_STATE_W 4 -#define UDMA_STATUS_STATE_M 0x000000F0 -#define UDMA_STATUS_STATE_S 4 +#define UDMA_STATUS_STATE_W 4 +#define UDMA_STATUS_STATE_M 0x000000F0 +#define UDMA_STATUS_STATE_S 4 // Field: [0] MASTERENABLE // @@ -160,10 +160,10 @@ // // 0: Controller is disabled // 1: Controller is enabled -#define UDMA_STATUS_MASTERENABLE 0x00000001 -#define UDMA_STATUS_MASTERENABLE_BITN 0 -#define UDMA_STATUS_MASTERENABLE_M 0x00000001 -#define UDMA_STATUS_MASTERENABLE_S 0 +#define UDMA_STATUS_MASTERENABLE 0x00000001 +#define UDMA_STATUS_MASTERENABLE_BITN 0 +#define UDMA_STATUS_MASTERENABLE_M 0x00000001 +#define UDMA_STATUS_MASTERENABLE_S 0 //***************************************************************************** // @@ -188,9 +188,9 @@ // - the write to the address indicated by destination address pointer // HProt[3:1] for these two exceptions can be controlled by dedicated fields in // the channel configutation descriptor. -#define UDMA_CFG_PRTOCTRL_W 3 -#define UDMA_CFG_PRTOCTRL_M 0x000000E0 -#define UDMA_CFG_PRTOCTRL_S 5 +#define UDMA_CFG_PRTOCTRL_W 3 +#define UDMA_CFG_PRTOCTRL_M 0x000000E0 +#define UDMA_CFG_PRTOCTRL_S 5 // Field: [0] MASTERENABLE // @@ -198,10 +198,10 @@ // // 0: Disables the controller // 1: Enables the controller -#define UDMA_CFG_MASTERENABLE 0x00000001 -#define UDMA_CFG_MASTERENABLE_BITN 0 -#define UDMA_CFG_MASTERENABLE_M 0x00000001 -#define UDMA_CFG_MASTERENABLE_S 0 +#define UDMA_CFG_MASTERENABLE 0x00000001 +#define UDMA_CFG_MASTERENABLE_BITN 0 +#define UDMA_CFG_MASTERENABLE_M 0x00000001 +#define UDMA_CFG_MASTERENABLE_S 0 //***************************************************************************** // @@ -213,9 +213,9 @@ // This register point to the base address for the primary data structures of // each DMA channel. This is not stored in module, but in system memory, thus // space must be allocated for this usage when DMA is in usage -#define UDMA_CTRL_BASEPTR_W 22 -#define UDMA_CTRL_BASEPTR_M 0xFFFFFC00 -#define UDMA_CTRL_BASEPTR_S 10 +#define UDMA_CTRL_BASEPTR_W 22 +#define UDMA_CTRL_BASEPTR_M 0xFFFFFC00 +#define UDMA_CTRL_BASEPTR_S 10 //***************************************************************************** // @@ -226,9 +226,9 @@ // // This register shows the base address for the alternate data structures and // is calculated by module, thus read only -#define UDMA_ALTCTRL_BASEPTR_W 32 -#define UDMA_ALTCTRL_BASEPTR_M 0xFFFFFFFF -#define UDMA_ALTCTRL_BASEPTR_S 0 +#define UDMA_ALTCTRL_BASEPTR_W 32 +#define UDMA_ALTCTRL_BASEPTR_M 0xFFFFFFFF +#define UDMA_ALTCTRL_BASEPTR_S 0 //***************************************************************************** // @@ -245,9 +245,9 @@ // keeps channel Ch in active state until the requests are deasserted. This // handshake is necessary for channels where the requester is in an // asynchronous domain or can run at slower clock speed than uDMA -#define UDMA_WAITONREQ_CHNLSTATUS_W 32 -#define UDMA_WAITONREQ_CHNLSTATUS_M 0xFFFFFFFF -#define UDMA_WAITONREQ_CHNLSTATUS_S 0 +#define UDMA_WAITONREQ_CHNLSTATUS_W 32 +#define UDMA_WAITONREQ_CHNLSTATUS_M 0xFFFFFFFF +#define UDMA_WAITONREQ_CHNLSTATUS_S 0 //***************************************************************************** // @@ -264,9 +264,9 @@ // // Writing to a bit where a uDMA channel is not implemented does not create a // uDMA request for that channel -#define UDMA_SOFTREQ_CHNLS_W 32 -#define UDMA_SOFTREQ_CHNLS_M 0xFFFFFFFF -#define UDMA_SOFTREQ_CHNLS_S 0 +#define UDMA_SOFTREQ_CHNLS_W 32 +#define UDMA_SOFTREQ_CHNLS_M 0xFFFFFFFF +#define UDMA_SOFTREQ_CHNLS_S 0 //***************************************************************************** // @@ -294,9 +294,9 @@ // controller performs 2^R transfers for burst requests. // // Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_SETBURST_CHNLS_W 32 -#define UDMA_SETBURST_CHNLS_M 0xFFFFFFFF -#define UDMA_SETBURST_CHNLS_S 0 +#define UDMA_SETBURST_CHNLS_W 32 +#define UDMA_SETBURST_CHNLS_M 0xFFFFFFFF +#define UDMA_SETBURST_CHNLS_S 0 //***************************************************************************** // @@ -315,9 +315,9 @@ // Bit [Ch] = 1: Enables single transfer requests on channel Ch. // // Writing to a bit where a DMA channel is not implemented has no effect. -#define UDMA_CLEARBURST_CHNLS_W 32 -#define UDMA_CLEARBURST_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARBURST_CHNLS_S 0 +#define UDMA_CLEARBURST_CHNLS_W 32 +#define UDMA_CLEARBURST_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARBURST_CHNLS_S 0 //***************************************************************************** // @@ -339,9 +339,9 @@ // request channel [C] input from generating uDMA requests. // // Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_SETREQMASK_CHNLS_W 32 -#define UDMA_SETREQMASK_CHNLS_M 0xFFFFFFFF -#define UDMA_SETREQMASK_CHNLS_S 0 +#define UDMA_SETREQMASK_CHNLS_W 32 +#define UDMA_SETREQMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_SETREQMASK_CHNLS_S 0 //***************************************************************************** // @@ -358,9 +358,9 @@ // Bit [Ch] = 1: Enables channel [C] to generate DMA requests. // // Writing to a bit where a DMA channel is not implemented has no effect. -#define UDMA_CLEARREQMASK_CHNLS_W 32 -#define UDMA_CLEARREQMASK_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARREQMASK_CHNLS_S 0 +#define UDMA_CLEARREQMASK_CHNLS_W 32 +#define UDMA_CLEARREQMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARREQMASK_CHNLS_S 0 //***************************************************************************** // @@ -381,9 +381,9 @@ // Bit [Ch] = 1: Enables channel Ch // // Writing to a bit where a DMA channel is not implemented has no effect -#define UDMA_SETCHANNELEN_CHNLS_W 32 -#define UDMA_SETCHANNELEN_CHNLS_M 0xFFFFFFFF -#define UDMA_SETCHANNELEN_CHNLS_S 0 +#define UDMA_SETCHANNELEN_CHNLS_W 32 +#define UDMA_SETCHANNELEN_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHANNELEN_CHNLS_S 0 //***************************************************************************** // @@ -399,9 +399,9 @@ // Bit [Ch] = 1: Disables channel Ch // // Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_CLEARCHANNELEN_CHNLS_W 32 -#define UDMA_CLEARCHANNELEN_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARCHANNELEN_CHNLS_S 0 +#define UDMA_CLEARCHANNELEN_CHNLS_W 32 +#define UDMA_CLEARCHANNELEN_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHANNELEN_CHNLS_S 0 //***************************************************************************** // @@ -422,9 +422,9 @@ // Bit [Ch] = 1: Selects the alternate data structure for channel Ch // // Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_SETCHNLPRIALT_CHNLS_W 32 -#define UDMA_SETCHNLPRIALT_CHNLS_M 0xFFFFFFFF -#define UDMA_SETCHNLPRIALT_CHNLS_S 0 +#define UDMA_SETCHNLPRIALT_CHNLS_W 32 +#define UDMA_SETCHNLPRIALT_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHNLPRIALT_CHNLS_S 0 //***************************************************************************** // @@ -442,9 +442,9 @@ // Bit [Ch] = 1: Selects the primary data structure for channel Ch. // // Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_CLEARCHNLPRIALT_CHNLS_W 32 -#define UDMA_CLEARCHNLPRIALT_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARCHNLPRIALT_CHNLS_S 0 +#define UDMA_CLEARCHNLPRIALT_CHNLS_W 32 +#define UDMA_CLEARCHNLPRIALT_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHNLPRIALT_CHNLS_S 0 //***************************************************************************** // @@ -466,9 +466,9 @@ // Bit [Ch] = 1: Channel Ch uses the high priority level. // // Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_SETCHNLPRIORITY_CHNLS_W 32 -#define UDMA_SETCHNLPRIORITY_CHNLS_M 0xFFFFFFFF -#define UDMA_SETCHNLPRIORITY_CHNLS_S 0 +#define UDMA_SETCHNLPRIORITY_CHNLS_W 32 +#define UDMA_SETCHNLPRIORITY_CHNLS_M 0xFFFFFFFF +#define UDMA_SETCHNLPRIORITY_CHNLS_S 0 //***************************************************************************** // @@ -486,9 +486,9 @@ // Bit [Ch] = 1: Channel Ch uses the default priority level. // // Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_CLEARCHNLPRIORITY_CHNLS_W 32 -#define UDMA_CLEARCHNLPRIORITY_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARCHNLPRIORITY_CHNLS_S 0 +#define UDMA_CLEARCHNLPRIORITY_CHNLS_W 32 +#define UDMA_CLEARCHNLPRIORITY_CHNLS_M 0xFFFFFFFF +#define UDMA_CLEARCHNLPRIORITY_CHNLS_S 0 //***************************************************************************** // @@ -508,10 +508,10 @@ // // 0: No effect, status of bus error flag is unchanged. // 1: Clears the bus error flag. -#define UDMA_ERROR_STATUS 0x00000001 -#define UDMA_ERROR_STATUS_BITN 0 -#define UDMA_ERROR_STATUS_M 0x00000001 -#define UDMA_ERROR_STATUS_S 0 +#define UDMA_ERROR_STATUS 0x00000001 +#define UDMA_ERROR_STATUS_BITN 0 +#define UDMA_ERROR_STATUS_M 0x00000001 +#define UDMA_ERROR_STATUS_S 0 //***************************************************************************** // @@ -532,9 +532,9 @@ // Write as: // Bit [Ch] = 0: No effect. // Bit [Ch] = 1: The corresponding [Ch] bit is cleared and is set to 0 -#define UDMA_REQDONE_CHNLS_W 32 -#define UDMA_REQDONE_CHNLS_M 0xFFFFFFFF -#define UDMA_REQDONE_CHNLS_S 0 +#define UDMA_REQDONE_CHNLS_W 32 +#define UDMA_REQDONE_CHNLS_M 0xFFFFFFFF +#define UDMA_REQDONE_CHNLS_S 0 //***************************************************************************** // @@ -567,9 +567,8 @@ // peripherals. // Note that this enables uDMA done for channel [Ch] to contribute to // generation of combined uDMA done signal. -#define UDMA_DONEMASK_CHNLS_W 32 -#define UDMA_DONEMASK_CHNLS_M 0xFFFFFFFF -#define UDMA_DONEMASK_CHNLS_S 0 - +#define UDMA_DONEMASK_CHNLS_W 32 +#define UDMA_DONEMASK_CHNLS_M 0xFFFFFFFF +#define UDMA_DONEMASK_CHNLS_S 0 #endif // __UDMA__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_vims.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_vims.h index 8ba5b60..a36fbae 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_vims.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_vims.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_vims_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_vims_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_VIMS_H__ #define __HW_VIMS_H__ @@ -44,10 +44,10 @@ // //***************************************************************************** // Status -#define VIMS_O_STAT 0x00000000 +#define VIMS_O_STAT 0x00000000 // Control -#define VIMS_O_CTL 0x00000004 +#define VIMS_O_CTL 0x00000004 //***************************************************************************** // @@ -60,10 +60,10 @@ // // 0: Enabled or in transition to disabled // 1: Disabled and flushed -#define VIMS_STAT_IDCODE_LB_DIS 0x00000020 -#define VIMS_STAT_IDCODE_LB_DIS_BITN 5 -#define VIMS_STAT_IDCODE_LB_DIS_M 0x00000020 -#define VIMS_STAT_IDCODE_LB_DIS_S 5 +#define VIMS_STAT_IDCODE_LB_DIS 0x00000020 +#define VIMS_STAT_IDCODE_LB_DIS_BITN 5 +#define VIMS_STAT_IDCODE_LB_DIS_M 0x00000020 +#define VIMS_STAT_IDCODE_LB_DIS_S 5 // Field: [4] SYSBUS_LB_DIS // @@ -71,10 +71,10 @@ // // 0: Enabled or in transition to disabled // 1: Disabled and flushed -#define VIMS_STAT_SYSBUS_LB_DIS 0x00000010 -#define VIMS_STAT_SYSBUS_LB_DIS_BITN 4 -#define VIMS_STAT_SYSBUS_LB_DIS_M 0x00000010 -#define VIMS_STAT_SYSBUS_LB_DIS_S 4 +#define VIMS_STAT_SYSBUS_LB_DIS 0x00000010 +#define VIMS_STAT_SYSBUS_LB_DIS_BITN 4 +#define VIMS_STAT_SYSBUS_LB_DIS_M 0x00000010 +#define VIMS_STAT_SYSBUS_LB_DIS_S 4 // Field: [3] MODE_CHANGING // @@ -82,18 +82,18 @@ // // 0: VIMS is in the mode defined by MODE // 1: VIMS is in the process of changing to the mode given in CTL.MODE -#define VIMS_STAT_MODE_CHANGING 0x00000008 -#define VIMS_STAT_MODE_CHANGING_BITN 3 -#define VIMS_STAT_MODE_CHANGING_M 0x00000008 -#define VIMS_STAT_MODE_CHANGING_S 3 +#define VIMS_STAT_MODE_CHANGING 0x00000008 +#define VIMS_STAT_MODE_CHANGING_BITN 3 +#define VIMS_STAT_MODE_CHANGING_M 0x00000008 +#define VIMS_STAT_MODE_CHANGING_S 3 // Field: [2] INV // // This bit is set when invalidation of the cache memory is active / ongoing -#define VIMS_STAT_INV 0x00000004 -#define VIMS_STAT_INV_BITN 2 -#define VIMS_STAT_INV_M 0x00000004 -#define VIMS_STAT_INV_S 2 +#define VIMS_STAT_INV 0x00000004 +#define VIMS_STAT_INV_BITN 2 +#define VIMS_STAT_INV_M 0x00000004 +#define VIMS_STAT_INV_S 2 // Field: [1:0] MODE // @@ -102,12 +102,12 @@ // OFF VIMS Off mode // CACHE VIMS Cache mode // GPRAM VIMS GPRAM mode -#define VIMS_STAT_MODE_W 2 -#define VIMS_STAT_MODE_M 0x00000003 -#define VIMS_STAT_MODE_S 0 -#define VIMS_STAT_MODE_OFF 0x00000003 -#define VIMS_STAT_MODE_CACHE 0x00000001 -#define VIMS_STAT_MODE_GPRAM 0x00000000 +#define VIMS_STAT_MODE_W 2 +#define VIMS_STAT_MODE_M 0x00000003 +#define VIMS_STAT_MODE_S 0 +#define VIMS_STAT_MODE_OFF 0x00000003 +#define VIMS_STAT_MODE_CACHE 0x00000001 +#define VIMS_STAT_MODE_GPRAM 0x00000000 //***************************************************************************** // @@ -117,28 +117,28 @@ // Field: [31] STATS_CLR // // Set this bit to clear statistic counters. -#define VIMS_CTL_STATS_CLR 0x80000000 -#define VIMS_CTL_STATS_CLR_BITN 31 -#define VIMS_CTL_STATS_CLR_M 0x80000000 -#define VIMS_CTL_STATS_CLR_S 31 +#define VIMS_CTL_STATS_CLR 0x80000000 +#define VIMS_CTL_STATS_CLR_BITN 31 +#define VIMS_CTL_STATS_CLR_M 0x80000000 +#define VIMS_CTL_STATS_CLR_S 31 // Field: [30] STATS_EN // // Set this bit to enable statistic counters. -#define VIMS_CTL_STATS_EN 0x40000000 -#define VIMS_CTL_STATS_EN_BITN 30 -#define VIMS_CTL_STATS_EN_M 0x40000000 -#define VIMS_CTL_STATS_EN_S 30 +#define VIMS_CTL_STATS_EN 0x40000000 +#define VIMS_CTL_STATS_EN_BITN 30 +#define VIMS_CTL_STATS_EN_M 0x40000000 +#define VIMS_CTL_STATS_EN_S 30 // Field: [29] DYN_CG_EN // // 0: The in-built clock gate functionality is bypassed. // 1: The in-built clock gate functionality is enabled, automatically gating // the clock when not needed. -#define VIMS_CTL_DYN_CG_EN 0x20000000 -#define VIMS_CTL_DYN_CG_EN_BITN 29 -#define VIMS_CTL_DYN_CG_EN_M 0x20000000 -#define VIMS_CTL_DYN_CG_EN_S 29 +#define VIMS_CTL_DYN_CG_EN 0x20000000 +#define VIMS_CTL_DYN_CG_EN_BITN 29 +#define VIMS_CTL_DYN_CG_EN_M 0x20000000 +#define VIMS_CTL_DYN_CG_EN_S 29 // Field: [5] IDCODE_LB_DIS // @@ -146,10 +146,10 @@ // // 0: Enable // 1: Disable -#define VIMS_CTL_IDCODE_LB_DIS 0x00000020 -#define VIMS_CTL_IDCODE_LB_DIS_BITN 5 -#define VIMS_CTL_IDCODE_LB_DIS_M 0x00000020 -#define VIMS_CTL_IDCODE_LB_DIS_S 5 +#define VIMS_CTL_IDCODE_LB_DIS 0x00000020 +#define VIMS_CTL_IDCODE_LB_DIS_BITN 5 +#define VIMS_CTL_IDCODE_LB_DIS_M 0x00000020 +#define VIMS_CTL_IDCODE_LB_DIS_S 5 // Field: [4] SYSBUS_LB_DIS // @@ -157,10 +157,10 @@ // // 0: Enable // 1: Disable -#define VIMS_CTL_SYSBUS_LB_DIS 0x00000010 -#define VIMS_CTL_SYSBUS_LB_DIS_BITN 4 -#define VIMS_CTL_SYSBUS_LB_DIS_M 0x00000010 -#define VIMS_CTL_SYSBUS_LB_DIS_S 4 +#define VIMS_CTL_SYSBUS_LB_DIS 0x00000010 +#define VIMS_CTL_SYSBUS_LB_DIS_BITN 4 +#define VIMS_CTL_SYSBUS_LB_DIS_M 0x00000010 +#define VIMS_CTL_SYSBUS_LB_DIS_S 4 // Field: [3] ARB_CFG // @@ -168,10 +168,10 @@ // // 0: Static arbitration (icode/docde > sysbus) // 1: Round-robin arbitration -#define VIMS_CTL_ARB_CFG 0x00000008 -#define VIMS_CTL_ARB_CFG_BITN 3 -#define VIMS_CTL_ARB_CFG_M 0x00000008 -#define VIMS_CTL_ARB_CFG_S 3 +#define VIMS_CTL_ARB_CFG 0x00000008 +#define VIMS_CTL_ARB_CFG_BITN 3 +#define VIMS_CTL_ARB_CFG_M 0x00000008 +#define VIMS_CTL_ARB_CFG_S 3 // Field: [2] PREF_EN // @@ -179,10 +179,10 @@ // // 0: Disabled // 1: Enabled -#define VIMS_CTL_PREF_EN 0x00000004 -#define VIMS_CTL_PREF_EN_BITN 2 -#define VIMS_CTL_PREF_EN_M 0x00000004 -#define VIMS_CTL_PREF_EN_S 2 +#define VIMS_CTL_PREF_EN 0x00000004 +#define VIMS_CTL_PREF_EN_BITN 2 +#define VIMS_CTL_PREF_EN_M 0x00000004 +#define VIMS_CTL_PREF_EN_S 2 // Field: [1:0] MODE // @@ -195,12 +195,11 @@ // OFF VIMS Off mode // CACHE VIMS Cache mode // GPRAM VIMS GPRAM mode -#define VIMS_CTL_MODE_W 2 -#define VIMS_CTL_MODE_M 0x00000003 -#define VIMS_CTL_MODE_S 0 -#define VIMS_CTL_MODE_OFF 0x00000003 -#define VIMS_CTL_MODE_CACHE 0x00000001 -#define VIMS_CTL_MODE_GPRAM 0x00000000 - +#define VIMS_CTL_MODE_W 2 +#define VIMS_CTL_MODE_M 0x00000003 +#define VIMS_CTL_MODE_S 0 +#define VIMS_CTL_MODE_OFF 0x00000003 +#define VIMS_CTL_MODE_CACHE 0x00000001 +#define VIMS_CTL_MODE_GPRAM 0x00000000 #endif // __VIMS__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_wdt.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_wdt.h index 3a67579..3d678d8 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_wdt.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/inc/hw_wdt.h @@ -1,38 +1,38 @@ /****************************************************************************** -* Filename: hw_wdt_h -* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) -* Revision: 48345 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: hw_wdt_h + * Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017) + * Revision: 48345 + * + * Copyright (c) 2015 - 2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef __HW_WDT_H__ #define __HW_WDT_H__ @@ -44,31 +44,31 @@ // //***************************************************************************** // Configuration -#define WDT_O_LOAD 0x00000000 +#define WDT_O_LOAD 0x00000000 // Current Count Value -#define WDT_O_VALUE 0x00000004 +#define WDT_O_VALUE 0x00000004 // Control -#define WDT_O_CTL 0x00000008 +#define WDT_O_CTL 0x00000008 // Interrupt Clear -#define WDT_O_ICR 0x0000000C +#define WDT_O_ICR 0x0000000C // Raw Interrupt Status -#define WDT_O_RIS 0x00000010 +#define WDT_O_RIS 0x00000010 // Masked Interrupt Status -#define WDT_O_MIS 0x00000014 +#define WDT_O_MIS 0x00000014 // Test Mode -#define WDT_O_TEST 0x00000418 +#define WDT_O_TEST 0x00000418 // Interrupt Cause Test Mode -#define WDT_O_INT_CAUS 0x0000041C +#define WDT_O_INT_CAUS 0x0000041C // Lock -#define WDT_O_LOCK 0x00000C00 +#define WDT_O_LOCK 0x00000C00 //***************************************************************************** // @@ -81,9 +81,9 @@ // this register is written, the value is immediately loaded and the counter is // restarted to count down from the new value. If this register is loaded with // 0x0000.0000, an interrupt is immediately generated. -#define WDT_LOAD_WDTLOAD_W 32 -#define WDT_LOAD_WDTLOAD_M 0xFFFFFFFF -#define WDT_LOAD_WDTLOAD_S 0 +#define WDT_LOAD_WDTLOAD_W 32 +#define WDT_LOAD_WDTLOAD_M 0xFFFFFFFF +#define WDT_LOAD_WDTLOAD_S 0 //***************************************************************************** // @@ -93,9 +93,9 @@ // Field: [31:0] WDTVALUE // // This register contains the current count value of the timer. -#define WDT_VALUE_WDTVALUE_W 32 -#define WDT_VALUE_WDTVALUE_M 0xFFFFFFFF -#define WDT_VALUE_WDTVALUE_S 0 +#define WDT_VALUE_WDTVALUE_W 32 +#define WDT_VALUE_WDTVALUE_M 0xFFFFFFFF +#define WDT_VALUE_WDTVALUE_S 0 //***************************************************************************** // @@ -111,12 +111,12 @@ // ENUMs: // NONMASKABLE Non-maskable interrupt // MASKABLE Maskable interrupt -#define WDT_CTL_INTTYPE 0x00000004 -#define WDT_CTL_INTTYPE_BITN 2 -#define WDT_CTL_INTTYPE_M 0x00000004 -#define WDT_CTL_INTTYPE_S 2 -#define WDT_CTL_INTTYPE_NONMASKABLE 0x00000004 -#define WDT_CTL_INTTYPE_MASKABLE 0x00000000 +#define WDT_CTL_INTTYPE 0x00000004 +#define WDT_CTL_INTTYPE_BITN 2 +#define WDT_CTL_INTTYPE_M 0x00000004 +#define WDT_CTL_INTTYPE_S 2 +#define WDT_CTL_INTTYPE_NONMASKABLE 0x00000004 +#define WDT_CTL_INTTYPE_MASKABLE 0x00000000 // Field: [1] RESEN // @@ -128,12 +128,12 @@ // ENUMs: // EN Reset output Enabled // DIS Reset output Disabled -#define WDT_CTL_RESEN 0x00000002 -#define WDT_CTL_RESEN_BITN 1 -#define WDT_CTL_RESEN_M 0x00000002 -#define WDT_CTL_RESEN_S 1 -#define WDT_CTL_RESEN_EN 0x00000002 -#define WDT_CTL_RESEN_DIS 0x00000000 +#define WDT_CTL_RESEN 0x00000002 +#define WDT_CTL_RESEN_BITN 1 +#define WDT_CTL_RESEN_M 0x00000002 +#define WDT_CTL_RESEN_S 1 +#define WDT_CTL_RESEN_EN 0x00000002 +#define WDT_CTL_RESEN_DIS 0x00000000 // Field: [0] INTEN // @@ -145,12 +145,12 @@ // ENUMs: // EN Interrupt Enabled // DIS Interrupt Disabled -#define WDT_CTL_INTEN 0x00000001 -#define WDT_CTL_INTEN_BITN 0 -#define WDT_CTL_INTEN_M 0x00000001 -#define WDT_CTL_INTEN_S 0 -#define WDT_CTL_INTEN_EN 0x00000001 -#define WDT_CTL_INTEN_DIS 0x00000000 +#define WDT_CTL_INTEN 0x00000001 +#define WDT_CTL_INTEN_BITN 0 +#define WDT_CTL_INTEN_M 0x00000001 +#define WDT_CTL_INTEN_S 0 +#define WDT_CTL_INTEN_EN 0x00000001 +#define WDT_CTL_INTEN_DIS 0x00000000 //***************************************************************************** // @@ -162,9 +162,9 @@ // This register is the interrupt clear register. A write of any value to this // register clears the WDT interrupt and reloads the 32-bit counter from the // LOAD register. -#define WDT_ICR_WDTICR_W 32 -#define WDT_ICR_WDTICR_M 0xFFFFFFFF -#define WDT_ICR_WDTICR_S 0 +#define WDT_ICR_WDTICR_W 32 +#define WDT_ICR_WDTICR_M 0xFFFFFFFF +#define WDT_ICR_WDTICR_S 0 //***************************************************************************** // @@ -181,10 +181,10 @@ // 0: The WDT has not timed out // 1: A WDT time-out event has occurred // -#define WDT_RIS_WDTRIS 0x00000001 -#define WDT_RIS_WDTRIS_BITN 0 -#define WDT_RIS_WDTRIS_M 0x00000001 -#define WDT_RIS_WDTRIS_S 0 +#define WDT_RIS_WDTRIS 0x00000001 +#define WDT_RIS_WDTRIS_BITN 0 +#define WDT_RIS_WDTRIS_M 0x00000001 +#define WDT_RIS_WDTRIS_S 0 //***************************************************************************** // @@ -201,10 +201,10 @@ // // 0: The WDT has not timed out or is masked. // 1: An unmasked WDT time-out event has occurred. -#define WDT_MIS_WDTMIS 0x00000001 -#define WDT_MIS_WDTMIS_BITN 0 -#define WDT_MIS_WDTMIS_M 0x00000001 -#define WDT_MIS_WDTMIS_S 0 +#define WDT_MIS_WDTMIS 0x00000001 +#define WDT_MIS_WDTMIS_BITN 0 +#define WDT_MIS_WDTMIS_M 0x00000001 +#define WDT_MIS_WDTMIS_S 0 //***************************************************************************** // @@ -221,12 +221,12 @@ // ENUMs: // EN Enable STALL // DIS Disable STALL -#define WDT_TEST_STALL 0x00000100 -#define WDT_TEST_STALL_BITN 8 -#define WDT_TEST_STALL_M 0x00000100 -#define WDT_TEST_STALL_S 8 -#define WDT_TEST_STALL_EN 0x00000100 -#define WDT_TEST_STALL_DIS 0x00000000 +#define WDT_TEST_STALL 0x00000100 +#define WDT_TEST_STALL_BITN 8 +#define WDT_TEST_STALL_M 0x00000100 +#define WDT_TEST_STALL_S 8 +#define WDT_TEST_STALL_EN 0x00000100 +#define WDT_TEST_STALL_DIS 0x00000000 // Field: [0] TEST_EN // @@ -238,12 +238,12 @@ // ENUMs: // EN Test mode Enabled // DIS Test mode Disabled -#define WDT_TEST_TEST_EN 0x00000001 -#define WDT_TEST_TEST_EN_BITN 0 -#define WDT_TEST_TEST_EN_M 0x00000001 -#define WDT_TEST_TEST_EN_S 0 -#define WDT_TEST_TEST_EN_EN 0x00000001 -#define WDT_TEST_TEST_EN_DIS 0x00000000 +#define WDT_TEST_TEST_EN 0x00000001 +#define WDT_TEST_TEST_EN_BITN 0 +#define WDT_TEST_TEST_EN_M 0x00000001 +#define WDT_TEST_TEST_EN_S 0 +#define WDT_TEST_TEST_EN_EN 0x00000001 +#define WDT_TEST_TEST_EN_DIS 0x00000000 //***************************************************************************** // @@ -254,18 +254,18 @@ // // Indicates that the cause of an interrupt was a reset generated but blocked // due to TEST.TEST_EN (only possible when TEST.TEST_EN is set). -#define WDT_INT_CAUS_CAUSE_RESET 0x00000002 -#define WDT_INT_CAUS_CAUSE_RESET_BITN 1 -#define WDT_INT_CAUS_CAUSE_RESET_M 0x00000002 -#define WDT_INT_CAUS_CAUSE_RESET_S 1 +#define WDT_INT_CAUS_CAUSE_RESET 0x00000002 +#define WDT_INT_CAUS_CAUSE_RESET_BITN 1 +#define WDT_INT_CAUS_CAUSE_RESET_M 0x00000002 +#define WDT_INT_CAUS_CAUSE_RESET_S 1 // Field: [0] CAUSE_INTR // // Replica of RIS.WDTRIS -#define WDT_INT_CAUS_CAUSE_INTR 0x00000001 -#define WDT_INT_CAUS_CAUSE_INTR_BITN 0 -#define WDT_INT_CAUS_CAUSE_INTR_M 0x00000001 -#define WDT_INT_CAUS_CAUSE_INTR_S 0 +#define WDT_INT_CAUS_CAUSE_INTR 0x00000001 +#define WDT_INT_CAUS_CAUSE_INTR_BITN 0 +#define WDT_INT_CAUS_CAUSE_INTR_M 0x00000001 +#define WDT_INT_CAUS_CAUSE_INTR_S 0 //***************************************************************************** // @@ -282,9 +282,8 @@ // // 0x0000.0000: Unlocked // 0x0000.0001: Locked -#define WDT_LOCK_WDTLOCK_W 32 -#define WDT_LOCK_WDTLOCK_M 0xFFFFFFFF -#define WDT_LOCK_WDTLOCK_S 0 - +#define WDT_LOCK_WDTLOCK_W 32 +#define WDT_LOCK_WDTLOCK_M 0xFFFFFFFF +#define WDT_LOCK_WDTLOCK_S 0 #endif // __WDT__ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ble.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ble.h index 4a50576..5806d86 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ble.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ble.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_patch_cpe_ble.h -* Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ -* Revision: $Revision: 18438 $ -* -* Description: RF Core patch file for CC26x0 -* -* Copyright (c) 2015, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_cpe_ble.h + * Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ + * Revision: $Revision: 18438 $ + * + * Description: RF Core patch file for CC26x0 + * + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_CPE_BLE_H #define _RF_PATCH_CPE_BLE_H @@ -46,8 +46,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include @@ -69,116 +68,115 @@ extern "C" #define _APPLY_PATCH_TAB #endif - CPE_PATCH_TYPE patchImageBle[] = -{ - 0x210004b9, - 0x21000539, - 0x2100047d, - 0x2100058f, - 0x4c17b5f0, - 0x18612140, - 0x280278c8, - 0x4809d005, - 0x60012100, - 0x47884908, - 0x6e25bdf0, - 0x60354e07, - 0x43280760, - 0x68276620, - 0x480e6024, - 0x60274780, - 0xbdf06035, - 0x4004112c, - 0x000065a5, - 0x40044028, - 0x4c07b510, - 0x29007da1, - 0x2101d105, - 0x024875a1, - 0x393e4904, - 0x68204788, - 0xd0002800, - 0xbd104780, - 0x21000254, - 0x0000398b, - 0x4905b510, - 0xb6724a05, - 0x280178c8, - 0x2001dc02, - 0x1d127048, - 0x4710b662, - 0x21000294, - 0x0000476d, - 0x4605b5ff, - 0x4c03b085, - 0xb5ff4720, - 0x01dfb085, - 0x47204c01, - 0x00003d5b, - 0x00003f23, - 0x4e1ab5f8, - 0x6b314605, - 0x09cc4819, - 0x2d0001e4, - 0x4918d011, - 0x29027809, - 0x7b00d00f, - 0xb6724304, - 0x4f152001, - 0x47b80240, - 0x38204811, - 0x09c18800, - 0xd00407c9, - 0x7ac0e016, - 0x7b40e7f0, - 0x490fe7ee, - 0x61cc6334, - 0x07c00a40, - 0x2001d00c, - 0x6af10380, - 0xd0012d00, - 0xe0004301, - 0x46084381, - 0x490762f1, - 0x63483940, - 0x47b82000, - 0xbdf8b662, - 0x21000280, - 0x21000088, - 0x21000296, - 0x00003cdf, - 0x40044040, - 0x28004907, - 0x2004d000, - 0xb6724a06, - 0x07c97809, - 0x5810d001, - 0x2080e000, - 0xb240b662, - 0x00004770, - 0x2100026b, - 0x40046058, - 0x2041b510, - 0x00c0490e, - 0x490e4788, - 0x6b884602, - 0x24906b49, - 0x04c1014b, - 0x430b0ec9, - 0x4363490a, - 0x43597c49, - 0x689b4b09, - 0xff8df7ff, - 0xb510bd10, - 0xff84f7ff, - 0xd1010004, - 0xffe2f7ff, - 0xbd104620, - 0x00003a39, - 0x40045080, - 0x21000280, - 0x40044000, + { + 0x210004b9, + 0x21000539, + 0x2100047d, + 0x2100058f, + 0x4c17b5f0, + 0x18612140, + 0x280278c8, + 0x4809d005, + 0x60012100, + 0x47884908, + 0x6e25bdf0, + 0x60354e07, + 0x43280760, + 0x68276620, + 0x480e6024, + 0x60274780, + 0xbdf06035, + 0x4004112c, + 0x000065a5, + 0x40044028, + 0x4c07b510, + 0x29007da1, + 0x2101d105, + 0x024875a1, + 0x393e4904, + 0x68204788, + 0xd0002800, + 0xbd104780, + 0x21000254, + 0x0000398b, + 0x4905b510, + 0xb6724a05, + 0x280178c8, + 0x2001dc02, + 0x1d127048, + 0x4710b662, + 0x21000294, + 0x0000476d, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01dfb085, + 0x47204c01, + 0x00003d5b, + 0x00003f23, + 0x4e1ab5f8, + 0x6b314605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6334, + 0x07c00a40, + 0x2001d00c, + 0x6af10380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x490762f1, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x21000296, + 0x00003cdf, + 0x40044040, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597c49, + 0x689b4b09, + 0xff8df7ff, + 0xb510bd10, + 0xff84f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003a39, + 0x40045080, + 0x21000280, + 0x40044000, }; #define _NWORD_PATCHIMAGE_BLE 107 @@ -187,7 +185,6 @@ CPE_PATCH_TYPE patchImageBle[] = #define _IRQ_PATCH_0 0x21000415 #define _IRQ_PATCH_1 0x21000455 - #ifndef _BLE_SYSRAM_START #define _BLE_SYSRAM_START 0x20000000 #endif @@ -206,7 +203,7 @@ CPE_PATCH_TYPE patchImageBle[] = PATCH_FUN_SPEC void enterBleCpePatch(void) { #if (_NWORD_PATCHIMAGE_BLE > 0) - uint32_t* pPatchVec = (uint32_t*) (_BLE_CPERAM_START + _BLE_PATCH_VEC_OFFSET); + uint32_t* pPatchVec = (uint32_t*)(_BLE_CPERAM_START + _BLE_PATCH_VEC_OFFSET); memcpy(pPatchVec, patchImageBle, sizeof(patchImageBle)); #endif @@ -218,9 +215,8 @@ PATCH_FUN_SPEC void enterBleSysPatch(void) PATCH_FUN_SPEC void configureBlePatch(void) { - uint8_t* pPatchTab = (uint8_t*) (_BLE_CPERAM_START + _BLE_PATCH_TAB_OFFSET); - uint32_t* pIrqPatch = (uint32_t*) (_BLE_CPERAM_START + _BLE_IRQPATCH_OFFSET); - + uint8_t* pPatchTab = (uint8_t*)(_BLE_CPERAM_START + _BLE_PATCH_TAB_OFFSET); + uint32_t* pIrqPatch = (uint32_t*)(_BLE_CPERAM_START + _BLE_IRQPATCH_OFFSET); pPatchTab[103] = 0; pPatchTab[60] = 1; @@ -262,4 +258,3 @@ PATCH_FUN_SPEC void rf_patch_cpe_ble(void) #endif #endif // _RF_PATCH_CPE_BLE_H - diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ble_priv_1_2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ble_priv_1_2.h index e1897c9..616935e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ble_priv_1_2.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ble_priv_1_2.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_patch_cpe_ble_priv_1_2.h -* Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ -* Revision: $Revision: 18438 $ -* -* Description: RF Core patch file for CC26x0 Bluetooth Low Energy with privacy 1.2 support -* -* Copyright (c) 2015, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_cpe_ble_priv_1_2.h + * Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ + * Revision: $Revision: 18438 $ + * + * Description: RF Core patch file for CC26x0 Bluetooth Low Energy with privacy 1.2 support + * + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_CPE_BLE_PRIV_1_2_H #define _RF_PATCH_CPE_BLE_PRIV_1_2_H @@ -46,8 +46,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include @@ -69,210 +68,209 @@ extern "C" #define _APPLY_PATCH_TAB #endif - CPE_PATCH_TYPE patchImageBlePriv12[] = -{ - 0x210005e5, - 0x21000631, - 0x210006b1, - 0x21000481, - 0x21000707, - 0x4c17b5f0, - 0x18612140, - 0x280278c8, - 0x4809d005, - 0x60012100, - 0x47884908, - 0x6e25bdf0, - 0x60354e07, - 0x43280760, - 0x68276620, - 0x480e6024, - 0x60274780, - 0xbdf06035, - 0x4004112c, - 0x000065a5, - 0x40044028, - 0x4c07b510, - 0x29007da1, - 0x2101d105, - 0x024875a1, - 0x393e4904, - 0x68204788, - 0xd0002800, - 0xbd104780, - 0x21000254, - 0x0000398b, - 0x4905b510, - 0xb6724a05, - 0x280178c8, - 0x2001dc02, - 0x1d127048, - 0x4710b662, - 0x21000294, - 0x0000476d, - 0x4605b5ff, - 0x4c03b085, - 0xb5ff4720, - 0x01dfb085, - 0x47204c01, - 0x00003d5b, - 0x00003f23, - 0x4d53b5fe, - 0x462c4628, - 0x90003040, - 0x7e014627, - 0x78383760, - 0xd0022900, - 0xd10707c0, - 0x09c1e050, - 0x07c0d04e, - 0x7d20d14c, - 0xd5490640, - 0x31724629, - 0x20064a48, - 0x98004790, - 0x28007e00, - 0x7d20d007, - 0xd5010640, - 0xe0002003, - 0x26132001, - 0x6f68e008, - 0x28010f80, - 0x2006d002, - 0xe0014606, - 0x26072003, - 0x02312201, - 0x1a890412, - 0x02008a7a, - 0x43020412, - 0x35806f6b, - 0x68a89501, - 0x47a84d37, - 0x2e062201, - 0x2e07d002, - 0xe007d002, - 0xe00543c0, - 0x70797839, - 0x70394311, - 0x61089901, - 0xda012800, - 0x55022039, - 0x7e809800, - 0xd0022800, - 0x201e2106, - 0x6a61e002, - 0x201f1f89, - 0x6ca162a1, - 0x64e04788, - 0xbdfe2000, - 0x47804826, - 0x4822bdfe, - 0x78413060, - 0xd0022900, - 0x21007001, - 0x48217041, - 0x470038b0, - 0x4e1cb5f8, - 0x4635481f, - 0x7fec3540, - 0x09e14637, - 0x6db1d01a, - 0xd0172901, - 0x29007f69, - 0x07a1d002, - 0xe011d502, - 0xd10f07e1, - 0x06497d39, - 0x2103d50c, - 0x77e94321, - 0x6f314780, - 0x29010f89, - 0x2100d002, - 0x76793720, - 0xbdf877ec, - 0xbdf84780, - 0x31404909, - 0x28157508, - 0x281bd008, - 0x281dd008, - 0x490ad008, - 0x18400080, - 0x47706980, - 0x47704808, - 0x47704808, - 0x47704808, - 0x21000144, - 0x0000b8af, - 0x0000a001, - 0x0000be03, - 0x0000b98d, - 0x0000ccc0, - 0x21000599, - 0x21000583, - 0x210004bd, - 0x4e1ab5f8, - 0x6b314605, - 0x09cc4819, - 0x2d0001e4, - 0x4918d011, - 0x29027809, - 0x7b00d00f, - 0xb6724304, - 0x4f152001, - 0x47b80240, - 0x38204811, - 0x09c18800, - 0xd00407c9, - 0x7ac0e016, - 0x7b40e7f0, - 0x490fe7ee, - 0x61cc6334, - 0x07c00a40, - 0x2001d00c, - 0x6af10380, - 0xd0012d00, - 0xe0004301, - 0x46084381, - 0x490762f1, - 0x63483940, - 0x47b82000, - 0xbdf8b662, - 0x21000280, - 0x21000088, - 0x21000296, - 0x00003cdf, - 0x40044040, - 0x28004907, - 0x2004d000, - 0xb6724a06, - 0x07c97809, - 0x5810d001, - 0x2080e000, - 0xb240b662, - 0x00004770, - 0x2100026b, - 0x40046058, - 0x2041b510, - 0x00c0490e, - 0x490e4788, - 0x6b884602, - 0x24906b49, - 0x04c1014b, - 0x430b0ec9, - 0x4363490a, - 0x43597c49, - 0x689b4b09, - 0xfed3f7ff, - 0xb510bd10, - 0xfecaf7ff, - 0xd1010004, - 0xffe2f7ff, - 0xbd104620, - 0x00003a39, - 0x40045080, - 0x21000280, - 0x40044000, + { + 0x210005e5, + 0x21000631, + 0x210006b1, + 0x21000481, + 0x21000707, + 0x4c17b5f0, + 0x18612140, + 0x280278c8, + 0x4809d005, + 0x60012100, + 0x47884908, + 0x6e25bdf0, + 0x60354e07, + 0x43280760, + 0x68276620, + 0x480e6024, + 0x60274780, + 0xbdf06035, + 0x4004112c, + 0x000065a5, + 0x40044028, + 0x4c07b510, + 0x29007da1, + 0x2101d105, + 0x024875a1, + 0x393e4904, + 0x68204788, + 0xd0002800, + 0xbd104780, + 0x21000254, + 0x0000398b, + 0x4905b510, + 0xb6724a05, + 0x280178c8, + 0x2001dc02, + 0x1d127048, + 0x4710b662, + 0x21000294, + 0x0000476d, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01dfb085, + 0x47204c01, + 0x00003d5b, + 0x00003f23, + 0x4d53b5fe, + 0x462c4628, + 0x90003040, + 0x7e014627, + 0x78383760, + 0xd0022900, + 0xd10707c0, + 0x09c1e050, + 0x07c0d04e, + 0x7d20d14c, + 0xd5490640, + 0x31724629, + 0x20064a48, + 0x98004790, + 0x28007e00, + 0x7d20d007, + 0xd5010640, + 0xe0002003, + 0x26132001, + 0x6f68e008, + 0x28010f80, + 0x2006d002, + 0xe0014606, + 0x26072003, + 0x02312201, + 0x1a890412, + 0x02008a7a, + 0x43020412, + 0x35806f6b, + 0x68a89501, + 0x47a84d37, + 0x2e062201, + 0x2e07d002, + 0xe007d002, + 0xe00543c0, + 0x70797839, + 0x70394311, + 0x61089901, + 0xda012800, + 0x55022039, + 0x7e809800, + 0xd0022800, + 0x201e2106, + 0x6a61e002, + 0x201f1f89, + 0x6ca162a1, + 0x64e04788, + 0xbdfe2000, + 0x47804826, + 0x4822bdfe, + 0x78413060, + 0xd0022900, + 0x21007001, + 0x48217041, + 0x470038b0, + 0x4e1cb5f8, + 0x4635481f, + 0x7fec3540, + 0x09e14637, + 0x6db1d01a, + 0xd0172901, + 0x29007f69, + 0x07a1d002, + 0xe011d502, + 0xd10f07e1, + 0x06497d39, + 0x2103d50c, + 0x77e94321, + 0x6f314780, + 0x29010f89, + 0x2100d002, + 0x76793720, + 0xbdf877ec, + 0xbdf84780, + 0x31404909, + 0x28157508, + 0x281bd008, + 0x281dd008, + 0x490ad008, + 0x18400080, + 0x47706980, + 0x47704808, + 0x47704808, + 0x47704808, + 0x21000144, + 0x0000b8af, + 0x0000a001, + 0x0000be03, + 0x0000b98d, + 0x0000ccc0, + 0x21000599, + 0x21000583, + 0x210004bd, + 0x4e1ab5f8, + 0x6b314605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6334, + 0x07c00a40, + 0x2001d00c, + 0x6af10380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x490762f1, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x21000296, + 0x00003cdf, + 0x40044040, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597c49, + 0x689b4b09, + 0xfed3f7ff, + 0xb510bd10, + 0xfecaf7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003a39, + 0x40045080, + 0x21000280, + 0x40044000, }; #define _NWORD_PATCHIMAGE_BLE_PRIV_1_2 201 @@ -281,7 +279,6 @@ CPE_PATCH_TYPE patchImageBlePriv12[] = #define _IRQ_PATCH_0 0x21000419 #define _IRQ_PATCH_1 0x21000459 - #ifndef _BLE_PRIV_1_2_SYSRAM_START #define _BLE_PRIV_1_2_SYSRAM_START 0x20000000 #endif @@ -300,7 +297,7 @@ CPE_PATCH_TYPE patchImageBlePriv12[] = PATCH_FUN_SPEC void enterBlePriv12CpePatch(void) { #if (_NWORD_PATCHIMAGE_BLE_PRIV_1_2 > 0) - uint32_t* pPatchVec = (uint32_t*) (_BLE_PRIV_1_2_CPERAM_START + _BLE_PRIV_1_2_PATCH_VEC_OFFSET); + uint32_t* pPatchVec = (uint32_t*)(_BLE_PRIV_1_2_CPERAM_START + _BLE_PRIV_1_2_PATCH_VEC_OFFSET); memcpy(pPatchVec, patchImageBlePriv12, sizeof(patchImageBlePriv12)); #endif @@ -312,9 +309,8 @@ PATCH_FUN_SPEC void enterBlePriv12SysPatch(void) PATCH_FUN_SPEC void configureBlePriv12Patch(void) { - uint8_t* pPatchTab = (uint8_t*) (_BLE_PRIV_1_2_CPERAM_START + _BLE_PRIV_1_2_PATCH_TAB_OFFSET); - uint32_t* pIrqPatch = (uint32_t*) (_BLE_PRIV_1_2_CPERAM_START + _BLE_PRIV_1_2_IRQPATCH_OFFSET); - + uint8_t* pPatchTab = (uint8_t*)(_BLE_PRIV_1_2_CPERAM_START + _BLE_PRIV_1_2_PATCH_TAB_OFFSET); + uint32_t* pIrqPatch = (uint32_t*)(_BLE_PRIV_1_2_CPERAM_START + _BLE_PRIV_1_2_IRQPATCH_OFFSET); pPatchTab[1] = 0; pPatchTab[103] = 1; @@ -357,4 +353,3 @@ PATCH_FUN_SPEC void rf_patch_cpe_ble_priv_1_2(void) #endif #endif // _RF_PATCH_CPE_BLE_PRIV_1_2_H - diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_genfsk.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_genfsk.h index a07b879..3c4dad2 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_genfsk.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_genfsk.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_patch_cpe_genfsk.h -* Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ -* Revision: $Revision: 18438 $ -* -* Description: RF core patch for CC26x0 Generic FSK -* -* Copyright (c) 2015, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_cpe_genfsk.h + * Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ + * Revision: $Revision: 18438 $ + * + * Description: RF core patch for CC26x0 Generic FSK + * + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_CPE_GENFSK_H #define _RF_PATCH_CPE_GENFSK_H @@ -46,8 +46,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include @@ -69,107 +68,106 @@ extern "C" #define _APPLY_PATCH_TAB #endif - CPE_PATCH_TYPE patchImageGenfsk[] = -{ - 0x21000495, - 0x21000515, - 0x2100056b, - 0x4c17b5f0, - 0x18612140, - 0x280278c8, - 0x4809d005, - 0x60012100, - 0x47884908, - 0x6e25bdf0, - 0x60354e07, - 0x43280760, - 0x68276620, - 0x480e6024, - 0x60274780, - 0xbdf06035, - 0x4004112c, - 0x000065a5, - 0x40044028, - 0x4c07b510, - 0x29007da1, - 0x2101d105, - 0x024875a1, - 0x393e4904, - 0x68204788, - 0xd0002800, - 0xbd104780, - 0x21000254, - 0x0000398b, - 0x4605b5ff, - 0x4c03b085, - 0xb5ff4720, - 0x01dfb085, - 0x47204c01, - 0x00003d5b, - 0x00003f23, - 0x4e1ab5f8, - 0x6b314605, - 0x09cc4819, - 0x2d0001e4, - 0x4918d011, - 0x29027809, - 0x7b00d00f, - 0xb6724304, - 0x4f152001, - 0x47b80240, - 0x38204811, - 0x09c18800, - 0xd00407c9, - 0x7ac0e016, - 0x7b40e7f0, - 0x490fe7ee, - 0x61cc6334, - 0x07c00a40, - 0x2001d00c, - 0x6af10380, - 0xd0012d00, - 0xe0004301, - 0x46084381, - 0x490762f1, - 0x63483940, - 0x47b82000, - 0xbdf8b662, - 0x21000280, - 0x21000088, - 0x21000296, - 0x00003cdf, - 0x40044040, - 0x28004907, - 0x2004d000, - 0xb6724a06, - 0x07c97809, - 0x5810d001, - 0x2080e000, - 0xb240b662, - 0x00004770, - 0x2100026b, - 0x40046058, - 0x2041b510, - 0x00c0490e, - 0x490e4788, - 0x6b884602, - 0x24906b49, - 0x04c1014b, - 0x430b0ec9, - 0x4363490a, - 0x43597c49, - 0x689b4b09, - 0xff8df7ff, - 0xb510bd10, - 0xff84f7ff, - 0xd1010004, - 0xffe2f7ff, - 0xbd104620, - 0x00003a39, - 0x40045080, - 0x21000280, - 0x40044000, + { + 0x21000495, + 0x21000515, + 0x2100056b, + 0x4c17b5f0, + 0x18612140, + 0x280278c8, + 0x4809d005, + 0x60012100, + 0x47884908, + 0x6e25bdf0, + 0x60354e07, + 0x43280760, + 0x68276620, + 0x480e6024, + 0x60274780, + 0xbdf06035, + 0x4004112c, + 0x000065a5, + 0x40044028, + 0x4c07b510, + 0x29007da1, + 0x2101d105, + 0x024875a1, + 0x393e4904, + 0x68204788, + 0xd0002800, + 0xbd104780, + 0x21000254, + 0x0000398b, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01dfb085, + 0x47204c01, + 0x00003d5b, + 0x00003f23, + 0x4e1ab5f8, + 0x6b314605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6334, + 0x07c00a40, + 0x2001d00c, + 0x6af10380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x490762f1, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x21000296, + 0x00003cdf, + 0x40044040, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597c49, + 0x689b4b09, + 0xff8df7ff, + 0xb510bd10, + 0xff84f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003a39, + 0x40045080, + 0x21000280, + 0x40044000, }; #define _NWORD_PATCHIMAGE_GENFSK 98 @@ -178,7 +176,6 @@ CPE_PATCH_TYPE patchImageGenfsk[] = #define _IRQ_PATCH_0 0x21000411 #define _IRQ_PATCH_1 0x21000451 - #ifndef _GENFSK_SYSRAM_START #define _GENFSK_SYSRAM_START 0x20000000 #endif @@ -197,7 +194,7 @@ CPE_PATCH_TYPE patchImageGenfsk[] = PATCH_FUN_SPEC void enterGenfskCpePatch(void) { #if (_NWORD_PATCHIMAGE_GENFSK > 0) - uint32_t* pPatchVec = (uint32_t*) (_GENFSK_CPERAM_START + _GENFSK_PATCH_VEC_OFFSET); + uint32_t* pPatchVec = (uint32_t*)(_GENFSK_CPERAM_START + _GENFSK_PATCH_VEC_OFFSET); memcpy(pPatchVec, patchImageGenfsk, sizeof(patchImageGenfsk)); #endif @@ -209,9 +206,8 @@ PATCH_FUN_SPEC void enterGenfskSysPatch(void) PATCH_FUN_SPEC void configureGenfskPatch(void) { - uint8_t* pPatchTab = (uint8_t*) (_GENFSK_CPERAM_START + _GENFSK_PATCH_TAB_OFFSET); - uint32_t* pIrqPatch = (uint32_t*) (_GENFSK_CPERAM_START + _GENFSK_IRQPATCH_OFFSET); - + uint8_t* pPatchTab = (uint8_t*)(_GENFSK_CPERAM_START + _GENFSK_PATCH_TAB_OFFSET); + uint32_t* pIrqPatch = (uint32_t*)(_GENFSK_CPERAM_START + _GENFSK_IRQPATCH_OFFSET); pPatchTab[103] = 0; pPatchTab[60] = 1; @@ -252,4 +248,3 @@ PATCH_FUN_SPEC void rf_patch_cpe_genfsk(void) #endif #endif // _RF_PATCH_CPE_GENFSK_H - diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ieee.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ieee.h index fdf1a22..64b64eb 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ieee.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_cpe_ieee.h @@ -1,40 +1,40 @@ /****************************************************************************** -* Filename: rf_patch_cpe_ieee.h -* Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ -* Revision: $Revision: 18438 $ -* -* Description: RF Core patch file for CC26x0 IEEE 802.15.4 PHY -* -* Copyright (c) 2015, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_cpe_ieee.h + * Revised: $Date: 2018-05-07 15:02:01 +0200 (ma, 07 mai 2018) $ + * Revision: $Revision: 18438 $ + * + * Description: RF Core patch file for CC26x0 IEEE 802.15.4 PHY + * + * Copyright (c) 2015, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_CPE_IEEE_H #define _RF_PATCH_CPE_IEEE_H @@ -46,8 +46,7 @@ // //***************************************************************************** #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include @@ -69,148 +68,147 @@ extern "C" #define _APPLY_PATCH_TAB #endif - CPE_PATCH_TYPE patchImageIeee[] = -{ - 0x2100050f, - 0x2100041d, - 0x21000539, - 0x210005b9, - 0x210004b5, - 0x2100060f, - 0x22024823, - 0x421a7dc3, - 0xd0034472, - 0x1dc04678, - 0xb5f84686, - 0x4c1f4710, - 0x200834ae, - 0x490347a0, - 0x60082008, - 0x3cec6008, - 0xbdf847a0, - 0x40045004, - 0x4c17b5f0, - 0x18612140, - 0x280278c8, - 0x4809d005, - 0x60012100, - 0x47884908, - 0x6e25bdf0, - 0x60354e07, - 0x43280760, - 0x68276620, - 0x480e6024, - 0x60274780, - 0xbdf06035, - 0x4004112c, - 0x000065a5, - 0x40044028, - 0x4c07b510, - 0x29007da1, - 0x2101d105, - 0x024875a1, - 0x393e4904, - 0x68204788, - 0xd0002800, - 0xbd104780, - 0x21000254, - 0x0000398b, - 0x6a034807, - 0x46784907, - 0x46861dc0, - 0x4788b5f8, - 0x009b089b, - 0x6a014802, - 0xd10007c9, - 0xbdf86203, - 0x40045040, - 0x0000f1ab, - 0x4605b5ff, - 0x4c03b085, - 0xb5ff4720, - 0x01dfb085, - 0x47204c01, - 0x00003d5b, - 0x00003f23, - 0x6a00480b, - 0xd00407c0, - 0x2201480a, - 0x43117801, - 0x48097001, - 0x72c84700, - 0xd006280d, - 0x00802285, - 0x18800252, - 0x60486840, - 0x48044770, - 0x0000e7fb, - 0x40045040, - 0x21000268, - 0x0000ff39, - 0x210004f9, - 0x4e1ab5f8, - 0x6b314605, - 0x09cc4819, - 0x2d0001e4, - 0x4918d011, - 0x29027809, - 0x7b00d00f, - 0xb6724304, - 0x4f152001, - 0x47b80240, - 0x38204811, - 0x09c18800, - 0xd00407c9, - 0x7ac0e016, - 0x7b40e7f0, - 0x490fe7ee, - 0x61cc6334, - 0x07c00a40, - 0x2001d00c, - 0x6af10380, - 0xd0012d00, - 0xe0004301, - 0x46084381, - 0x490762f1, - 0x63483940, - 0x47b82000, - 0xbdf8b662, - 0x21000280, - 0x21000088, - 0x21000296, - 0x00003cdf, - 0x40044040, - 0x28004907, - 0x2004d000, - 0xb6724a06, - 0x07c97809, - 0x5810d001, - 0x2080e000, - 0xb240b662, - 0x00004770, - 0x2100026b, - 0x40046058, - 0x2041b510, - 0x00c0490e, - 0x490e4788, - 0x6b884602, - 0x24906b49, - 0x04c1014b, - 0x430b0ec9, - 0x4363490a, - 0x43597c49, - 0x689b4b09, - 0xff6df7ff, - 0xb510bd10, - 0xff64f7ff, - 0xd1010004, - 0xffe2f7ff, - 0xbd104620, - 0x00003a39, - 0x40045080, - 0x21000280, - 0x40044000, + { + 0x2100050f, + 0x2100041d, + 0x21000539, + 0x210005b9, + 0x210004b5, + 0x2100060f, + 0x22024823, + 0x421a7dc3, + 0xd0034472, + 0x1dc04678, + 0xb5f84686, + 0x4c1f4710, + 0x200834ae, + 0x490347a0, + 0x60082008, + 0x3cec6008, + 0xbdf847a0, + 0x40045004, + 0x4c17b5f0, + 0x18612140, + 0x280278c8, + 0x4809d005, + 0x60012100, + 0x47884908, + 0x6e25bdf0, + 0x60354e07, + 0x43280760, + 0x68276620, + 0x480e6024, + 0x60274780, + 0xbdf06035, + 0x4004112c, + 0x000065a5, + 0x40044028, + 0x4c07b510, + 0x29007da1, + 0x2101d105, + 0x024875a1, + 0x393e4904, + 0x68204788, + 0xd0002800, + 0xbd104780, + 0x21000254, + 0x0000398b, + 0x6a034807, + 0x46784907, + 0x46861dc0, + 0x4788b5f8, + 0x009b089b, + 0x6a014802, + 0xd10007c9, + 0xbdf86203, + 0x40045040, + 0x0000f1ab, + 0x4605b5ff, + 0x4c03b085, + 0xb5ff4720, + 0x01dfb085, + 0x47204c01, + 0x00003d5b, + 0x00003f23, + 0x6a00480b, + 0xd00407c0, + 0x2201480a, + 0x43117801, + 0x48097001, + 0x72c84700, + 0xd006280d, + 0x00802285, + 0x18800252, + 0x60486840, + 0x48044770, + 0x0000e7fb, + 0x40045040, + 0x21000268, + 0x0000ff39, + 0x210004f9, + 0x4e1ab5f8, + 0x6b314605, + 0x09cc4819, + 0x2d0001e4, + 0x4918d011, + 0x29027809, + 0x7b00d00f, + 0xb6724304, + 0x4f152001, + 0x47b80240, + 0x38204811, + 0x09c18800, + 0xd00407c9, + 0x7ac0e016, + 0x7b40e7f0, + 0x490fe7ee, + 0x61cc6334, + 0x07c00a40, + 0x2001d00c, + 0x6af10380, + 0xd0012d00, + 0xe0004301, + 0x46084381, + 0x490762f1, + 0x63483940, + 0x47b82000, + 0xbdf8b662, + 0x21000280, + 0x21000088, + 0x21000296, + 0x00003cdf, + 0x40044040, + 0x28004907, + 0x2004d000, + 0xb6724a06, + 0x07c97809, + 0x5810d001, + 0x2080e000, + 0xb240b662, + 0x00004770, + 0x2100026b, + 0x40046058, + 0x2041b510, + 0x00c0490e, + 0x490e4788, + 0x6b884602, + 0x24906b49, + 0x04c1014b, + 0x430b0ec9, + 0x4363490a, + 0x43597c49, + 0x689b4b09, + 0xff6df7ff, + 0xb510bd10, + 0xff64f7ff, + 0xd1010004, + 0xffe2f7ff, + 0xbd104620, + 0x00003a39, + 0x40045080, + 0x21000280, + 0x40044000, }; #define _NWORD_PATCHIMAGE_IEEE 139 @@ -219,7 +217,6 @@ CPE_PATCH_TYPE patchImageIeee[] = #define _IRQ_PATCH_0 0x2100044d #define _IRQ_PATCH_1 0x2100048d - #ifndef _IEEE_SYSRAM_START #define _IEEE_SYSRAM_START 0x20000000 #endif @@ -238,7 +235,7 @@ CPE_PATCH_TYPE patchImageIeee[] = PATCH_FUN_SPEC void enterIeeeCpePatch(void) { #if (_NWORD_PATCHIMAGE_IEEE > 0) - uint32_t* pPatchVec = (uint32_t*) (_IEEE_CPERAM_START + _IEEE_PATCH_VEC_OFFSET); + uint32_t* pPatchVec = (uint32_t*)(_IEEE_CPERAM_START + _IEEE_PATCH_VEC_OFFSET); memcpy(pPatchVec, patchImageIeee, sizeof(patchImageIeee)); #endif @@ -250,9 +247,8 @@ PATCH_FUN_SPEC void enterIeeeSysPatch(void) PATCH_FUN_SPEC void configureIeeePatch(void) { - uint8_t* pPatchTab = (uint8_t*) (_IEEE_CPERAM_START + _IEEE_PATCH_TAB_OFFSET); - uint32_t* pIrqPatch = (uint32_t*) (_IEEE_CPERAM_START + _IEEE_IRQPATCH_OFFSET); - + uint8_t* pPatchTab = (uint8_t*)(_IEEE_CPERAM_START + _IEEE_PATCH_TAB_OFFSET); + uint32_t* pIrqPatch = (uint32_t*)(_IEEE_CPERAM_START + _IEEE_IRQPATCH_OFFSET); pPatchTab[5] = 0; pPatchTab[52] = 1; @@ -296,4 +292,3 @@ PATCH_FUN_SPEC void rf_patch_cpe_ieee(void) #endif #endif // _RF_PATCH_CPE_IEEE_H - diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_mce_genfsk.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_mce_genfsk.h index e2e5dd5..4e1d511 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_mce_genfsk.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_mce_genfsk.h @@ -1,526 +1,525 @@ /****************************************************************************** -* Filename: rf_patch_mce_genfsk.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC26x0 Generic FSK -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_mce_genfsk.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC26x0 Generic FSK + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_MCE_GENFSK_H #define _RF_PATCH_MCE_GENFSK_H -#include #include "../inc/hw_types.h" +#include #ifndef MCE_PATCH_TYPE - #define MCE_PATCH_TYPE static const uint32_t +#define MCE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_MCERAM_BASE - #define RFC_MCERAM_BASE 0x21008000 +#define RFC_MCERAM_BASE 0x21008000 #endif #ifndef MCE_PATCH_MODE - #define MCE_PATCH_MODE 0 +#define MCE_PATCH_MODE 0 #endif MCE_PATCH_TYPE patchGenfskMce[460] = -{ - 0x2fcf603c, - 0x030c3f9d, - 0x070c680a, - 0x003f0387, - 0x00fffff0, - 0x0000ff00, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00070003, - 0x00003d1f, - 0x04000000, - 0x0000000f, - 0x000b0387, - 0x004340f4, - 0x80828000, - 0x00000670, - 0x0510091e, - 0x00050054, - 0x3e100200, - 0x00000061, - 0x3030002f, - 0x0000027f, - 0x00000000, - 0x0000aa00, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x72487220, - 0x7303a32d, - 0x72037305, - 0x73067304, - 0x73767204, - 0xc7c07276, - 0x00018001, - 0x90109001, - 0x90010801, - 0x720d720c, - 0xb0c0720e, - 0xb0f07100, - 0x7218a0c0, - 0x10208132, - 0x06703952, - 0x16300020, - 0x14011101, - 0x60796c01, - 0x60ec607b, - 0x60796352, - 0x60796079, - 0x6079607a, - 0x60ec607b, - 0x60796352, - 0x60796079, - 0x1210607a, - 0x730f7220, - 0x73117310, - 0x00108181, - 0xb0709180, - 0x606f6051, - 0xc030606f, - 0xc1416791, - 0xc470c282, - 0x6f131820, - 0x16116e23, - 0x68811612, - 0x9ab07830, - 0x9ac07840, - 0x9ad07850, - 0x9ae07860, - 0xc5a0c482, - 0x40961820, - 0x6e231203, - 0x68931612, - 0x8160606f, - 0x81409490, - 0x2a703980, - 0x16111001, - 0x84448432, - 0xc0f5c0f3, - 0x1c01c200, - 0xc10040bb, - 0x40b11c10, - 0x10134cb3, - 0x18301803, - 0x1a101a13, - 0x68ae3912, - 0x13f360bb, - 0x13f360bb, - 0xc1001015, - 0x1a151850, - 0x39141a10, - 0xb0d868b9, - 0xb1087100, - 0xb200a0d8, - 0xb003b480, - 0xb002b013, - 0x7229b012, - 0x7100b0d0, - 0x8140b100, - 0x71009290, - 0x8140b100, - 0x44cb22f0, - 0x1c0313f0, - 0x929340d7, - 0x71009492, - 0x9295b100, - 0x71009494, - 0xb0d0b100, - 0x7000a480, - 0xc030a0d1, - 0xc0409760, - 0xb0f19780, - 0x7100b0c1, - 0xa0c1b0f1, - 0xa0037276, - 0x7000a002, - 0x7310730f, - 0x6791c040, - 0x91c0c100, - 0xb4836497, - 0xb0c3b0f3, - 0xa0c37100, - 0x606f64de, - 0xb016b006, - 0xb014b004, - 0xb012b002, - 0x78728400, - 0x81430420, - 0x2a733983, - 0xc1f29473, - 0x31621832, - 0x31511021, - 0x00200012, - 0x10309400, - 0x10011610, - 0x39303121, - 0x41172210, - 0x31501220, - 0x31801003, - 0x16300010, - 0x12029350, - 0x22731204, - 0x8430412a, - 0x87d297c0, - 0x84501a82, - 0x87d497c0, - 0x612c1a84, - 0x41372263, - 0x97c08440, - 0x1a8087d0, - 0x84601402, - 0x87d097c0, - 0x14041a80, - 0x84406143, - 0x041078a1, - 0x87d297c0, - 0x84601a42, - 0x041078a1, - 0x87d497c0, - 0x31521a44, - 0x39633154, - 0x16130633, - 0x38343832, - 0x39823182, - 0x00423184, - 0x78109572, - 0x90509030, - 0x90407820, - 0xb2059060, - 0x83038ae2, - 0xc00c9302, - 0x8140c00b, - 0x39803180, - 0x81413940, - 0x0431c0f3, - 0x1441c014, - 0x1412c002, - 0x31226965, - 0xc010847d, - 0x312d140d, - 0x8ace142d, - 0x311e318e, - 0x8ac9397e, - 0x39793149, - 0x31293949, - 0xb072109a, - 0xb06ea04e, - 0xb06cb011, - 0x7276978a, - 0xa764b764, - 0x9762c662, - 0x66d3c04f, - 0x22f18ab1, - 0x8ad1458b, - 0x458b22f1, - 0x71006231, - 0xb760b073, - 0x220780b7, - 0xa76045c2, - 0x22f18ab1, - 0x2237419c, - 0xb113419c, - 0x223080b0, - 0x61aa4597, - 0x41af22e1, - 0x22508090, - 0xb0f541af, - 0x22208210, - 0x9789418b, - 0xa764b764, - 0x618bb0f6, - 0xb764978d, - 0xb0f6a764, - 0x8ad0618b, - 0x41bb22f0, - 0x41bb2237, - 0xb113b075, - 0x223080b0, - 0xb08745b5, - 0x22d1618b, - 0x80904316, - 0x43162220, - 0x618b6699, - 0xc7f3978f, - 0x31808410, - 0x31833980, - 0x94100030, - 0xa0e3b087, - 0xa0c2b0f2, - 0xa0c5b0f5, - 0xb0c1b0f1, - 0xb110a0c6, - 0x80b0b113, - 0x45d32200, - 0x45d32230, - 0x12607100, - 0xb0f19780, - 0x8961b88f, - 0x18018570, - 0x8a609551, - 0xa4888a71, - 0xc022a487, - 0x1c211801, - 0x14124df3, - 0x61f449f1, - 0x41f41c01, - 0xb4874df3, - 0xb48861f4, - 0xb061b041, - 0x22e08ad0, - 0x821041fc, - 0x45772220, - 0xb04e7100, - 0x80b1b06e, - 0x468b2201, - 0x468b2231, - 0xb0f67276, - 0x31218471, - 0x1410c260, - 0xc7e09780, - 0xc6f09760, - 0xb0f69760, - 0xa0c1b0c6, - 0x8a63b7b0, - 0x8a838a74, - 0x71008a94, - 0x220180b1, - 0x2231468b, - 0x8ab0468b, - 0x462322c0, - 0x22018991, - 0x81c14177, - 0x91c0c000, - 0x81a28470, - 0x91c16a27, - 0x9070c300, - 0xa0e0b201, - 0xa044a0e3, - 0x71007000, - 0xb760b073, - 0x220780b7, - 0x22374650, - 0xa760466e, - 0x22e18ab1, - 0x80904249, - 0x42492250, - 0x8210b0f5, - 0x42312220, - 0xb764978d, - 0xb0f6a764, - 0x22d16231, - 0x80904316, - 0x43162220, - 0x62316699, - 0xb0f2978f, - 0xb0f5a0c2, - 0xb0f1a0c5, - 0xa0c6b0c1, - 0xb113b110, - 0x220080b0, - 0x22304658, - 0x71004658, - 0x97801260, - 0xb88fb0f1, - 0x85708961, - 0x3d803180, - 0x95511801, - 0x8a718a60, - 0x61e5a182, - 0xb0f2978f, - 0xb0f5a0c2, - 0xb0f1a0c5, - 0xa0c6b0c1, - 0xb113b110, - 0x220080b0, - 0x22304676, - 0x71004676, - 0x97801260, - 0xb88fb0f1, - 0x85708961, - 0x18013d80, - 0x8a809551, - 0xb1828a91, - 0xb07361e5, - 0xb760a760, - 0xb072a7b0, - 0xb06ea04e, - 0x8ab0b011, - 0x45c222f0, - 0x46502201, - 0x8ab0626e, - 0x469f22b0, - 0x46d11e3b, - 0x1e7b62a1, - 0xc00b46d1, - 0x8940b889, - 0x3d803180, - 0x3d301610, - 0x80b0140c, - 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0x31808410, + 0x31833980, + 0x94100030, + 0x31508400, + 0x8ad33950, + 0x06f33983, + 0x1834c1f4, + 0x31343184, + 0x94000040, + 0x22e2b089, + 0x8aca4311, + 0x398a394a, + 0x978a312a, + 0xb0c6b0c5, + 0x8ab2b763, + 0x431522d2, + 0x7000b0c2, + 0xa0e0b20f, + 0x978ea0e3, + 0xa764b764, + 0xb110b0f6, + 0x8210b113, + 0x431f22f0, + 0x8002b0f5, + 0xa006a004, + 0x7203a001, + 0xc0507204, + 0x71006791, + 0xb0f6b764, + 0xa20fb0c5, + 0xb0f57100, + 0x7810a0c5, + 0x90029030, + 0x90407820, + 0xb0729060, + 0x66d3a20f, + 0xa764978a, + 0x6184b0f6, + 0x8180b88c, + 0x392489a4, + 0x00043184, + 0xc0609184, + 0x73766791, + 0x72487276, + 0x72027206, + 0x73057204, + 0x606f7306, + 0x91b01300, + 0xc070b32d, + 0xb0f86791, + 0x120064fa, + 0x97801a10, + 0x9760c380, + 0x9760c280, + 0xb0c6a0c1, + 0x22008090, + 0x81544451, + 0x43621e04, + 0xb0f69784, + 0xd0808552, + 0x67919862, + 0x22118991, + 0x8a824378, + 0xe0908a93, + 0x98739862, + 0x637e6791, + 0x8a738a62, + 0x9862e0a0, + 0x67919873, + 0x87818790, + 0x4b8e1c01, + 0x1ef11801, + 0x87814b8c, + 0x97811af1, + 0xb0f67100, + 0x978116f1, + 0x7100a205, + 0xa0c6b0f6, + 0x98506340, + 0x22008840, + 0xb8304792, + 0x00007000}; PATCH_FUN_SPEC void rf_patch_mce_genfsk(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_mce_ieee_s.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_mce_ieee_s.h index c2d32cd..5ba40f8 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_mce_ieee_s.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_mce_ieee_s.h @@ -1,322 +1,321 @@ /****************************************************************************** -* Filename: rf_patch_mce_ieee_s.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC26x0 IEEE 802.15.4 Single Ended Output -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ + * Filename: rf_patch_mce_ieee_s.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC26x0 IEEE 802.15.4 Single Ended Output + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_MCE_IEEE_S_H #define _RF_PATCH_MCE_IEEE_S_H -#include #include "../inc/hw_types.h" +#include #ifndef MCE_PATCH_TYPE - #define MCE_PATCH_TYPE static const uint32_t +#define MCE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_MCERAM_BASE - #define RFC_MCERAM_BASE 0x21008000 +#define RFC_MCERAM_BASE 0x21008000 #endif #ifndef MCE_PATCH_MODE - #define MCE_PATCH_MODE 0 +#define MCE_PATCH_MODE 0 #endif MCE_PATCH_TYPE patchZigbeeXsIsMce[256] = -{ - 0xf703605f, - 0x70399b3a, - 0x039bb3af, - 0x39b33af7, - 0x9b3aaf70, - 0xb3aff703, - 0x3af77039, - 0xaf70039b, - 0x08fcb9b3, - 0x8fc664c5, - 0xfc644c50, - 0xc64cc508, - 0x64c5508f, - 0x4c5008fc, - 0xc5088fc6, - 0x508ffc64, - 0x0fcfc64c, - 0x7f7f079c, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000003, - 0x0000001f, - 0x80000000, - 0x0004000c, - 0x000114c4, - 0x00000009, - 0x00008000, - 0x002b0670, - 0x0a11121d, - 0x0b600000, - 0x40100000, - 0x00000040, - 0x1e1e0006, - 0x0000001e, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x72200000, - 0x720d720c, - 0x7248720e, - 0x7203a32d, - 0x73057204, - 0x73767306, - 0xc7c07276, - 0xb0c09010, - 0xa0c07100, - 0x7218b0f0, - 0x10208132, - 0x06703952, - 0x16300020, - 0x14011101, - 0x609b6c01, - 0x60c860a9, - 0x6147612c, - 0x609b609b, - 0x609b609c, - 0x609b609b, - 0x609b609b, - 0x609b609b, - 0x609b609c, - 0x609b609b, - 0x609b609b, - 0x609b609b, - 0x609b609c, - 0x609b609b, - 0x609b609b, - 0x609b609b, - 0x60a0609c, - 0x60a0664e, - 0x60a11220, - 0x730f1210, - 0x73117310, - 0x00108181, - 0xb0709180, - 0xc301606d, - 0xc420c282, - 0x6f131820, - 0x16116e23, - 0x68ad1612, - 0xc810c482, - 0x40ba1820, - 0x6e231203, - 0x68b71612, - 0x60a072ab, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xc1307276, - 0xb0f391c0, - 0xb0d8b108, - 0xb1087100, - 0xb200a0d8, - 0x1e008ab0, - 0xb76040da, - 0xb0f19780, - 0x7100b0c1, - 0xb013b483, - 0xb012b003, - 0xb0f1b002, - 0x7276a0c1, - 0x7100b0c3, - 0xa0c3b0f3, - 0xc0301000, - 0xc0209760, - 0xb0c19780, - 0xb0f17100, - 0x7276a0c1, - 0xa0037248, - 0x7248a002, - 0x73067305, - 0x72767376, - 0x9010c7c0, - 0x000060a0, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xc0307276, - 0xb00291b0, - 0xb006b004, - 0x90507a10, - 0x7a209030, - 0x90409060, - 0x94507810, - 0x94607820, - 0xc0f18160, - 0xc0120410, - 0x14023110, - 0x94306f20, - 0x6f201612, - 0x84209440, - 0x84213180, - 0x39813181, - 0x94100010, - 0xb2051200, - 0x31858165, - 0x39853145, - 0x120e3945, - 0x12061217, - 0x940012f0, - 0x9400c190, - 0xb119b011, - 0xa0ecb0e9, - 0x7100b089, - 0xa0e9b119, - 0xb0ecb11c, - 0x7100a404, - 0x659bb11c, - 0x417e1e76, - 0x45471eaf, - 0x1c90c140, - 0x12054d47, - 0x12761202, - 0x9070c300, - 0xc070b200, - 0xc0c065fa, - 0x7a309400, - 0x61859410, - 0x919f1647, - 0x1e008150, - 0x1c704185, - 0x7100498a, - 0x22008090, - 0x61684470, - 0x7276a205, - 0x72047203, - 0x73067305, - 0xa004a002, - 0x7248a006, - 0x73067305, - 0x72767376, - 0x9010c7c0, - 0x120960a0, - 0xc0cc120a, - 0xb88e120d, - 0x1c898928, - 0x1c8a49a6, - 0x61b34dac, - 0x12001089, - 0x100a1880, - 0x61b310db, - 0x1200108a, - 0x10091880, - 0x168b10db, - 0x161d61b3, - 0x41b81e8d, - 0x619f908c, - 0x1e8210bf, - 0x149541c3, - 0x1e821612, - 0x312545c3, - 0x00058180, - 0x1e8b9185, - 0x1a8b49c6, - 0x18b0c070, - 0x11011630, - 0x6c011401, - 0x908c908c, - 0x908c908c, - 0x908c908c, - 0x908c908c, - 0x1000b082, - 0x8923b88e, - 0xb083b083, - 0xb88e1000, - 0x1e8f8924, - 0x1ca349e4, - 0x1ca449e9, - 0x700049eb, - 0x4de91c93, - 0x4deb1c94, - 0x1a1e7000, - 0x161e61ed, - 0xc04061ed, - 0x49f41ce0, - 0x164010e0, - 0x700049f7, - 0xb085c00e, - 0xc00e7000, - 0x7000b084, - 0x88409850, - 0x45fb2200, - 0x7000b830 -}; + { + 0xf703605f, + 0x70399b3a, + 0x039bb3af, + 0x39b33af7, + 0x9b3aaf70, + 0xb3aff703, + 0x3af77039, + 0xaf70039b, + 0x08fcb9b3, + 0x8fc664c5, + 0xfc644c50, + 0xc64cc508, + 0x64c5508f, + 0x4c5008fc, + 0xc5088fc6, + 0x508ffc64, + 0x0fcfc64c, + 0x7f7f079c, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000003, + 0x0000001f, + 0x80000000, + 0x0004000c, + 0x000114c4, + 0x00000009, + 0x00008000, + 0x002b0670, + 0x0a11121d, + 0x0b600000, + 0x40100000, + 0x00000040, + 0x1e1e0006, + 0x0000001e, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x72200000, + 0x720d720c, + 0x7248720e, + 0x7203a32d, + 0x73057204, + 0x73767306, + 0xc7c07276, + 0xb0c09010, + 0xa0c07100, + 0x7218b0f0, + 0x10208132, + 0x06703952, + 0x16300020, + 0x14011101, + 0x609b6c01, + 0x60c860a9, + 0x6147612c, + 0x609b609b, + 0x609b609c, + 0x609b609b, + 0x609b609b, + 0x609b609b, + 0x609b609c, + 0x609b609b, + 0x609b609b, + 0x609b609b, + 0x609b609c, + 0x609b609b, + 0x609b609b, + 0x609b609b, + 0x60a0609c, + 0x60a0664e, + 0x60a11220, + 0x730f1210, + 0x73117310, + 0x00108181, + 0xb0709180, + 0xc301606d, + 0xc420c282, + 0x6f131820, + 0x16116e23, + 0x68ad1612, + 0xc810c482, + 0x40ba1820, + 0x6e231203, + 0x68b71612, + 0x60a072ab, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc1307276, + 0xb0f391c0, + 0xb0d8b108, + 0xb1087100, + 0xb200a0d8, + 0x1e008ab0, + 0xb76040da, + 0xb0f19780, + 0x7100b0c1, + 0xb013b483, + 0xb012b003, + 0xb0f1b002, + 0x7276a0c1, + 0x7100b0c3, + 0xa0c3b0f3, + 0xc0301000, + 0xc0209760, + 0xb0c19780, + 0xb0f17100, + 0x7276a0c1, + 0xa0037248, + 0x7248a002, + 0x73067305, + 0x72767376, + 0x9010c7c0, + 0x000060a0, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0xc0307276, + 0xb00291b0, + 0xb006b004, + 0x90507a10, + 0x7a209030, + 0x90409060, + 0x94507810, + 0x94607820, + 0xc0f18160, + 0xc0120410, + 0x14023110, + 0x94306f20, + 0x6f201612, + 0x84209440, + 0x84213180, + 0x39813181, + 0x94100010, + 0xb2051200, + 0x31858165, + 0x39853145, + 0x120e3945, + 0x12061217, + 0x940012f0, + 0x9400c190, + 0xb119b011, + 0xa0ecb0e9, + 0x7100b089, + 0xa0e9b119, + 0xb0ecb11c, + 0x7100a404, + 0x659bb11c, + 0x417e1e76, + 0x45471eaf, + 0x1c90c140, + 0x12054d47, + 0x12761202, + 0x9070c300, + 0xc070b200, + 0xc0c065fa, + 0x7a309400, + 0x61859410, + 0x919f1647, + 0x1e008150, + 0x1c704185, + 0x7100498a, + 0x22008090, + 0x61684470, + 0x7276a205, + 0x72047203, + 0x73067305, + 0xa004a002, + 0x7248a006, + 0x73067305, + 0x72767376, + 0x9010c7c0, + 0x120960a0, + 0xc0cc120a, + 0xb88e120d, + 0x1c898928, + 0x1c8a49a6, + 0x61b34dac, + 0x12001089, + 0x100a1880, + 0x61b310db, + 0x1200108a, + 0x10091880, + 0x168b10db, + 0x161d61b3, + 0x41b81e8d, + 0x619f908c, + 0x1e8210bf, + 0x149541c3, + 0x1e821612, + 0x312545c3, + 0x00058180, + 0x1e8b9185, + 0x1a8b49c6, + 0x18b0c070, + 0x11011630, + 0x6c011401, + 0x908c908c, + 0x908c908c, + 0x908c908c, + 0x908c908c, + 0x1000b082, + 0x8923b88e, + 0xb083b083, + 0xb88e1000, + 0x1e8f8924, + 0x1ca349e4, + 0x1ca449e9, + 0x700049eb, + 0x4de91c93, + 0x4deb1c94, + 0x1a1e7000, + 0x161e61ed, + 0xc04061ed, + 0x49f41ce0, + 0x164010e0, + 0x700049f7, + 0xb085c00e, + 0xc00e7000, + 0x7000b084, + 0x88409850, + 0x45fb2200, + 0x7000b830}; PATCH_FUN_SPEC void rf_patch_mce_ieee_s(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ble.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ble.h index 8cf7230..db16099 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ble.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ble.h @@ -1,382 +1,380 @@ /****************************************************************************** -* Filename: rf_patch_rfe_ble.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC26x0 BLE -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - + * Filename: rf_patch_rfe_ble.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC26x0 BLE + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_RFE_BLE_H #define _RF_PATCH_RFE_BLE_H -#include #include "../inc/hw_types.h" +#include #ifndef RFE_PATCH_TYPE - #define RFE_PATCH_TYPE static const uint32_t +#define RFE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_RFERAM_BASE - #define RFC_RFERAM_BASE 0x2100C000 +#define RFC_RFERAM_BASE 0x2100C000 #endif #ifndef RFE_PATCH_MODE - #define RFE_PATCH_MODE 0 +#define RFE_PATCH_MODE 0 #endif RFE_PATCH_TYPE patchBleRfe[315] = -{ - 0x00006154, - 0x0002147f, - 0x00050006, - 0x0008000f, - 0x00520048, - 0x003fff80, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x43cf41cf, - 0x4fcf47cf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x00000000, - 0x00000000, - 0x000f0000, - 0x00000008, - 0x0000003f, - 0x003f0040, - 0x00040000, - 0x000e0068, - 0x000600dc, - 0x001a0043, - 0x00000005, - 0x00020000, - 0x00000000, - 0x00000000, - 0x00c00004, - 0x00040000, - 0x000000c0, - 0x00000007, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x9100c050, - 0xc0707000, - 0x70009100, - 0x00213182, - 0xb1109131, - 0x81017000, - 0xa100b101, - 0x91323182, - 0x9101b110, - 0x81411011, - 0x40632241, - 0x700006f1, - 0x9101c051, - 0x39101830, - 0xd0083183, - 0x6f413118, - 0x91310031, - 0x1483b110, - 0x686f1614, - 0x10257000, - 0x9100c050, - 0xc140c3f4, - 0x6f031420, - 0x04411031, - 0x22f08250, - 0x26514084, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0x04411031, - 0x3182c082, - 0x91310021, - 0x3963b110, - 0xc0a21031, - 0x00213182, - 0xb1109131, - 0x31151050, - 0x92051405, - 0x64537000, - 0x1031c052, - 0x31610631, - 0x645602c1, - 0x1031c112, - 0x06713921, - 0x02e13151, - 0x70006456, - 0x9101c051, - 0xc0e2cc01, - 0x64536456, - 0xc0c2c111, - 0xb0546456, - 0xa0547100, - 0x80f0b064, - 0x40b52200, - 0x90b01240, - 0xc2f0b032, - 0xc11168c0, - 0x6456c122, - 0x68c5c0b0, - 0x9101c051, - 0x3182c0e2, - 0x00028260, - 0xb1109132, - 0x39538253, - 0x649d3953, - 0x68d3c050, - 0x12800000, - 0xb03290b0, - 0x64537000, - 0xc122c101, - 0xc1016456, - 0x6456c0c2, - 0x649d8253, - 0x90b012c0, - 0x7000b032, - 0xc2726453, - 0x6456c081, - 0xc111c122, - 0xc0026456, - 0x6456c111, - 0xc331c062, - 0xc3626456, - 0x6456c111, - 0xc111c302, - 0x82536456, - 0x649d3953, - 0x645bc3e2, - 0x40fc2211, - 0xc881c242, - 0xc2526456, - 0x6456c111, - 0xcee1c272, - 0xc2026456, - 0x6456c881, - 0xc801c202, - 0xc0b06456, - 0x70006910, - 0xc2426453, - 0x6456c801, - 0xc011c252, - 0xc2726456, - 0x6456c0e1, - 0xc101c002, - 0xc0626456, - 0x6456c301, - 0xc101c122, - 0xc3626456, - 0x6456c101, - 0xc101c302, - 0x82536456, - 0x7000649d, - 0x3162c102, - 0x80a0c001, - 0x41361e00, - 0x61381a10, - 0x1a101020, - 0x6e236f13, - 0x16121611, - 0x70006938, - 0x82d092e0, - 0x453f2200, - 0x7000b2c0, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x72057306, - 0x720e720b, - 0x7100b050, - 0xb0608081, - 0x8092a050, - 0x92f1eff0, - 0x653e9302, - 0x45782241, - 0xc1f18080, - 0x16300410, - 0x14011101, - 0x618b6c01, - 0x618d618c, - 0x618f618e, - 0x61916190, - 0x61956193, - 0x61996197, - 0x62736270, - 0xc0f28091, - 0x31210421, - 0x2a428082, - 0x16321412, - 0x14211101, - 0x61a66c01, - 0x61ac61c7, - 0x61a66273, - 0x61ac61c7, - 0x619b6273, - 0x619b619b, - 0x619b619b, - 0x64ac619b, - 0x64d9619b, - 0x64e6619b, - 0x6512619b, - 0x652e619b, - 0x8082619b, - 0x92f2dfe0, - 0xb0b0653e, - 0xb0b161a2, - 0x72057306, - 0x6158b030, - 0x653ecfd0, - 0xc003c284, - 0x6468c3c0, - 0x91507890, - 0x31107860, - 0x14107861, - 0x78509200, - 0x78613140, - 0x31400010, - 0x00107871, - 0x78b09210, - 0x78819260, - 0x78309221, - 0x78413140, - 0x92300010, - 0x91f0c010, - 0xa054619b, - 0x225080f0, - 0x804045cf, - 0x46662200, - 0xc80061c7, - 0x81599160, - 0x8091b050, - 0x462e2241, - 0x653ecfc0, - 0x31828212, - 0x39423982, - 0x64771028, - 0x12f18212, - 0x102f0412, - 0x142f311f, - 0x1420c140, - 0x396d6f0d, - 0xc3f410de, - 0xc082044e, - 0x002e3182, - 0xc0a2396d, - 0x002d3182, - 0x398a821a, - 0x31808220, - 0xc00b3980, - 0x78ac180b, - 0x39408230, - 0xc0111002, - 0xc0103001, - 0x18021801, - 0x00213182, - 0x919126c1, - 0xb013b003, - 0xb053b063, - 0x14398203, - 0x22018041, - 0x81b44666, - 0x81d591c4, - 0x1cb51895, - 0x1cc54e1c, - 0x91654a54, - 0x221080f0, - 0x622c420c, - 0xb110913d, - 0xb110913e, - 0x920f9165, - 0x14f98159, - 0x10bc18ab, - 0x225080f0, - 0x221041c7, - 0x620c462c, - 0x653ecfb0, - 0x8230b063, - 0xc0f21000, - 0x10020420, - 0x3001c011, - 0x1801c010, - 0x31821802, - 0x26c10021, - 0x91919191, - 0xb003b013, - 0xb053b063, - 0xb054b064, - 0x80417100, - 0x46662201, - 0xb064b063, - 0x225080f0, - 0x81b141c7, - 0x81d191c1, - 0x91611891, - 0x6244b031, - 0x31828212, - 0x39423982, - 0x64771028, - 0x82058159, - 0x82201459, - 0x180bc00b, - 0xc08078ac, - 0xb0637100, - 0x620c6a62, - 0x81628201, - 0x3d823182, - 0x92f1efa0, - 0x653e9302, - 0x619ba003, - 0x647780a2, - 0xb050619b, - 0x619b7100 -}; + { + 0x00006154, + 0x0002147f, + 0x00050006, + 0x0008000f, + 0x00520048, + 0x003fff80, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x00000000, + 0x000f0000, + 0x00000008, + 0x0000003f, + 0x003f0040, + 0x00040000, + 0x000e0068, + 0x000600dc, + 0x001a0043, + 0x00000005, + 0x00020000, + 0x00000000, + 0x00000000, + 0x00c00004, + 0x00040000, + 0x000000c0, + 0x00000007, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x40632241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x686f1614, + 0x10257000, + 0x9100c050, + 0xc140c3f4, + 0x6f031420, + 0x04411031, + 0x22f08250, + 0x26514084, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x64537000, + 0x1031c052, + 0x31610631, + 0x645602c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006456, + 0x9101c051, + 0xc0e2cc01, + 0x64536456, + 0xc0c2c111, + 0xb0546456, + 0xa0547100, + 0x80f0b064, + 0x40b52200, + 0x90b01240, + 0xc2f0b032, + 0xc11168c0, + 0x6456c122, + 0x68c5c0b0, + 0x9101c051, + 0x3182c0e2, + 0x00028260, + 0xb1109132, + 0x39538253, + 0x649d3953, + 0x68d3c050, + 0x12800000, + 0xb03290b0, + 0x64537000, + 0xc122c101, + 0xc1016456, + 0x6456c0c2, + 0x649d8253, + 0x90b012c0, + 0x7000b032, + 0xc2726453, + 0x6456c081, + 0xc111c122, + 0xc0026456, + 0x6456c111, + 0xc331c062, + 0xc3626456, + 0x6456c111, + 0xc111c302, + 0x82536456, + 0x649d3953, + 0x645bc3e2, + 0x40fc2211, + 0xc881c242, + 0xc2526456, + 0x6456c111, + 0xcee1c272, + 0xc2026456, + 0x6456c881, + 0xc801c202, + 0xc0b06456, + 0x70006910, + 0xc2426453, + 0x6456c801, + 0xc011c252, + 0xc2726456, + 0x6456c0e1, + 0xc101c002, + 0xc0626456, + 0x6456c301, + 0xc101c122, + 0xc3626456, + 0x6456c101, + 0xc101c302, + 0x82536456, + 0x7000649d, + 0x3162c102, + 0x80a0c001, + 0x41361e00, + 0x61381a10, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006938, + 0x82d092e0, + 0x453f2200, + 0x7000b2c0, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x72057306, + 0x720e720b, + 0x7100b050, + 0xb0608081, + 0x8092a050, + 0x92f1eff0, + 0x653e9302, + 0x45782241, + 0xc1f18080, + 0x16300410, + 0x14011101, + 0x618b6c01, + 0x618d618c, + 0x618f618e, + 0x61916190, + 0x61956193, + 0x61996197, + 0x62736270, + 0xc0f28091, + 0x31210421, + 0x2a428082, + 0x16321412, + 0x14211101, + 0x61a66c01, + 0x61ac61c7, + 0x61a66273, + 0x61ac61c7, + 0x619b6273, + 0x619b619b, + 0x619b619b, + 0x64ac619b, + 0x64d9619b, + 0x64e6619b, + 0x6512619b, + 0x652e619b, + 0x8082619b, + 0x92f2dfe0, + 0xb0b0653e, + 0xb0b161a2, + 0x72057306, + 0x6158b030, + 0x653ecfd0, + 0xc003c284, + 0x6468c3c0, + 0x91507890, + 0x31107860, + 0x14107861, + 0x78509200, + 0x78613140, + 0x31400010, + 0x00107871, + 0x78b09210, + 0x78819260, + 0x78309221, + 0x78413140, + 0x92300010, + 0x91f0c010, + 0xa054619b, + 0x225080f0, + 0x804045cf, + 0x46662200, + 0xc80061c7, + 0x81599160, + 0x8091b050, + 0x462e2241, + 0x653ecfc0, + 0x31828212, + 0x39423982, + 0x64771028, + 0x12f18212, + 0x102f0412, + 0x142f311f, + 0x1420c140, + 0x396d6f0d, + 0xc3f410de, + 0xc082044e, + 0x002e3182, + 0xc0a2396d, + 0x002d3182, + 0x398a821a, + 0x31808220, + 0xc00b3980, + 0x78ac180b, + 0x39408230, + 0xc0111002, + 0xc0103001, + 0x18021801, + 0x00213182, + 0x919126c1, + 0xb013b003, + 0xb053b063, + 0x14398203, + 0x22018041, + 0x81b44666, + 0x81d591c4, + 0x1cb51895, + 0x1cc54e1c, + 0x91654a54, + 0x221080f0, + 0x622c420c, + 0xb110913d, + 0xb110913e, + 0x920f9165, + 0x14f98159, + 0x10bc18ab, + 0x225080f0, + 0x221041c7, + 0x620c462c, + 0x653ecfb0, + 0x8230b063, + 0xc0f21000, + 0x10020420, + 0x3001c011, + 0x1801c010, + 0x31821802, + 0x26c10021, + 0x91919191, + 0xb003b013, + 0xb053b063, + 0xb054b064, + 0x80417100, + 0x46662201, + 0xb064b063, + 0x225080f0, + 0x81b141c7, + 0x81d191c1, + 0x91611891, + 0x6244b031, + 0x31828212, + 0x39423982, + 0x64771028, + 0x82058159, + 0x82201459, + 0x180bc00b, + 0xc08078ac, + 0xb0637100, + 0x620c6a62, + 0x81628201, + 0x3d823182, + 0x92f1efa0, + 0x653e9302, + 0x619ba003, + 0x647780a2, + 0xb050619b, + 0x619b7100}; PATCH_FUN_SPEC void rf_patch_rfe_ble(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_genfsk.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_genfsk.h index ff6ed56..c99c97b 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_genfsk.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_genfsk.h @@ -1,498 +1,496 @@ /****************************************************************************** -* Filename: rf_patch_rfe_genfsk.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC26x0 Generic FSK -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - + * Filename: rf_patch_rfe_genfsk.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC26x0 Generic FSK + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_RFE_GENFSK_H #define _RF_PATCH_RFE_GENFSK_H -#include #include "../inc/hw_types.h" +#include #ifndef RFE_PATCH_TYPE - #define RFE_PATCH_TYPE static const uint32_t +#define RFE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_RFERAM_BASE - #define RFC_RFERAM_BASE 0x2100C000 +#define RFC_RFERAM_BASE 0x2100C000 #endif #ifndef RFE_PATCH_MODE - #define RFE_PATCH_MODE 0 +#define RFE_PATCH_MODE 0 #endif RFE_PATCH_TYPE patchGenfskRfe[431] = -{ - 0x000061a9, - 0x1307147f, - 0x00080053, - 0x1f2e24f1, - 0x0ab03f13, - 0xff07003f, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x43cf41cf, - 0x4fcf47cf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x00000000, - 0x0008000f, - 0x003f0000, - 0x00400000, - 0x0000003f, - 0x00680004, - 0x00dc000e, - 0x00430006, - 0x0005001a, - 0x00000000, - 0x00000002, - 0x0000003f, - 0x00040000, - 0x000000c0, - 0x00c00004, - 0x00070000, - 0x9100c050, - 0xc0707000, - 0x70009100, - 0x00213182, - 0xb1109131, - 0x81017000, - 0xa100b101, - 0x91323182, - 0x9101b110, - 0x81411011, - 0x404f2241, - 0x700006f1, - 0x9101c051, - 0x39101830, - 0xd0083183, - 0x6f413118, - 0x91310031, - 0x1483b110, - 0x685b1614, - 0x10257000, - 0x9100c050, - 0xc0c0c3f4, - 0x6f031420, - 0x04411031, - 0x22f08250, - 0x26514070, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0x04411031, - 0x3182c082, - 0x91310021, - 0x3963b110, - 0xc0a21031, - 0x00213182, - 0xb1109131, - 0x31151050, - 0x92051405, - 0x643f7000, - 0x1031c052, - 0x31610631, - 0x644202c1, - 0x1031c112, - 0x06713921, - 0x02e13151, - 0x70006442, - 0x659d658e, - 0x8220c088, - 0x39803950, - 0x40a31e00, - 0x3001c041, - 0x1a181418, - 0x8230c089, - 0x39803960, - 0x40ad1e00, - 0x3001c041, - 0x1a191419, - 0x9136643c, - 0x9134b110, - 0xb054b110, - 0xa0547100, - 0x80f0b064, - 0x40b32200, - 0x90b01240, - 0x8253b032, - 0x39533953, - 0x643f6489, - 0xc122c111, - 0xc1706442, - 0xc11168c6, - 0x6442c0c2, - 0x68cbc170, - 0x9100c050, - 0x92987227, - 0x16141615, - 0x10531042, - 0x8221c1f0, - 0x39313131, - 0x31313981, - 0xb270b051, - 0x72276576, - 0xb2709299, - 0x10731062, - 0x8231c3f0, - 0x39213121, - 0x101b3981, - 0xc0e26576, - 0x82603182, - 0x39803180, - 0xb0610002, - 0x91327100, - 0xa051b110, - 0x7227b061, - 0x68f7c230, - 0x12800000, - 0xb03290b0, - 0xc0507000, - 0x72279100, - 0x10629299, - 0xc3f01073, - 0x31218231, - 0x39813921, - 0xb270b051, - 0x72276582, - 0xb2709298, - 0x10531042, - 0x8221c1f0, - 0x39313131, - 0x31313981, - 0x6582101a, - 0xb061a051, - 0xc0b07227, - 0x643f691c, - 0xc122c101, - 0xc1016442, - 0x6442c0c2, - 0x643c1a15, - 0xb1109135, - 0x64898253, - 0x90b012c0, - 0x7000b032, - 0xc272643f, - 0x6442c081, - 0xc111c122, - 0xc0026442, - 0x6442c111, - 0xc331c062, - 0xc3626442, - 0x6442c111, - 0xc111c302, - 0x82536442, - 0x64893953, - 0x6447c3e2, - 0x41442211, - 0xc881c242, - 0xc2526442, - 0x6442c111, - 0xcee1c272, - 0xc2026442, - 0x6442c881, - 0xc801c202, - 0xc0b06442, - 0x70006958, - 0xc242643f, - 0x6442c801, - 0xc011c252, - 0xc2726442, - 0x6442c0e1, - 0xc101c002, - 0xc0626442, - 0x6442c301, - 0xc101c122, - 0xc3626442, - 0x6442c101, - 0xc101c302, - 0x82536442, - 0x70006489, - 0x7100b061, - 0x1c231412, - 0x91334d7e, - 0x7000b110, - 0xb1109132, - 0x70006976, - 0x7100b061, - 0x1c321813, - 0x9132498a, - 0x7000b110, - 0xb1109133, - 0x70006982, - 0x6447c0c2, - 0xc0c21015, - 0x64471612, - 0x14153141, - 0x3180c0c0, - 0x10541405, - 0x040478b0, - 0xc0e67000, - 0x82613186, - 0x0401cc00, - 0x10671416, - 0xc3f08261, - 0x14170401, - 0x73067000, - 0x720b7205, - 0xb050720e, - 0x80817100, - 0xa050b060, - 0x22418092, - 0x808045c9, - 0x0410c1f1, - 0x11011630, - 0x6c011401, - 0x61dd61dc, - 0x61df61de, - 0x61e161e0, - 0x61e461e2, - 0x61e861e6, - 0x633961ea, - 0x8091633c, - 0x0421c0f2, - 0x80823121, - 0x14122a42, - 0x11011632, - 0x6c011421, - 0x621161f3, - 0x633c61f9, - 0x621161f3, - 0x633c61f9, - 0x61eb61eb, - 0x61eb61eb, - 0x61eb61eb, - 0x61eb6498, - 0x61eb64fd, - 0x61eb652e, - 0x61eb655a, - 0x121061eb, - 0x720e90b0, - 0x72057306, - 0x90301210, - 0xcff061ad, - 0xc1d4673f, - 0xc3c0c003, - 0x78406454, - 0x78609150, - 0x78709210, - 0x78809220, - 0x78909230, - 0x78a09240, - 0x78509260, - 0x783091f0, - 0x82109190, - 0x06f03940, - 0x31101001, - 0x92001410, - 0xa0bc61eb, - 0xa054a0e2, - 0x225080f0, - 0x8040461b, - 0x472e2200, - 0xa0406213, - 0x318d822d, - 0x8210398d, - 0x0410c0f1, - 0x821a1009, - 0x041a394a, - 0x39808210, - 0x100e0410, - 0x10bc10ab, - 0x646310c2, - 0xcfe07229, - 0xb013673f, - 0x66cdb003, - 0xb050b053, - 0xb064b054, - 0x66abb013, - 0x22e08210, - 0x66b4463e, - 0x80417100, - 0x472e2201, - 0x221080f0, - 0x22f04651, - 0xb064471b, - 0x423e2231, - 0x66d3b063, - 0x22e08210, - 0x6676463e, - 0xb064623e, - 0x318f816f, - 0xdfd03d8f, - 0x673f92ff, - 0x80417100, - 0x472e2201, - 0x80f0b064, - 0x426b2250, - 0x8211b063, - 0x466622c1, - 0x670866d3, - 0x22d18211, - 0x66764658, - 0x81616258, - 0x31818172, - 0x31823d81, - 0xefc03d82, - 0x930292f1, - 0x6211673f, - 0x91c081b0, - 0x829781d3, - 0x18d3a290, - 0x0bf34e85, - 0x1ce31613, - 0x91c34aaa, - 0x143b81e3, - 0x1cba6296, - 0x1e234691, - 0x1ce34a91, - 0xb2904e91, - 0x42912207, - 0x1a1ba290, - 0x1ce3629c, - 0x91c34aaa, - 0x183b81e3, - 0x4ea61cab, - 0x4aa81c9b, - 0x42aa1cbc, - 0x821010b2, - 0x42a322d0, - 0x221080f0, - 0x646346aa, - 0x62aa66ab, - 0x629a10ab, - 0x629a109b, - 0x82307000, - 0x0410c0f1, - 0x7100b063, - 0x10bc6aae, - 0x7000b0e0, - 0x91c281b2, - 0x820181d2, - 0x81511812, - 0x82411812, - 0x3d813181, - 0x4ac41c12, - 0xb032b0e2, - 0x673fcfb0, - 0x1421c7f1, - 0xc8124ec8, - 0x91729162, - 0xb0e1b031, - 0x12087000, - 0xc800c006, - 0x91709160, - 0x82017000, - 0x91c081b0, - 0x181081d0, - 0x18108151, - 0x80e11406, - 0x31828242, - 0x1c203d82, - 0xb0e24ae7, - 0x46eb2221, - 0xcfa0b032, - 0x2221673f, - 0xa0e242eb, - 0x8231b032, - 0xc0f03941, - 0x1e010401, - 0x161842f9, - 0x3010c010, - 0x47071c08, - 0x3c101060, - 0xc7f11006, - 0x4efd1461, - 0x9166c816, - 0x31818171, - 0x1c163d81, - 0x91764b04, - 0xc006b031, - 0x70001208, - 0x31818161, - 0x82403d81, - 0x18013980, - 0x4b1a1cf1, - 0x80b01401, - 0x471a22c0, - 0xb033b0bc, - 0x92f1ef90, - 0x673f930f, - 0xa0037000, - 0xb064b063, - 0x655ab0ef, - 0x80407100, - 0x472e2200, - 0x652eb064, - 0x7100a0ef, - 0x22008040, - 0xb064472e, - 0x623eb003, - 0x81628201, - 0x3d823182, - 0x92f1ef80, - 0x673f9302, - 0x655aa003, - 0x80a261eb, - 0x61eb6463, - 0x7100b050, - 0x92e061eb, - 0x220082d0, - 0xb2c04740, - 0x80a07000, - 0x435c22f0, - 0xc102b030, - 0xc0013162, - 0x1e0080a0, - 0x22f04355, - 0xf5d04356, - 0x39603160, - 0x10206356, - 0x6f131a10, - 0x16116e23, - 0x6b571612, - 0x00007000 -}; + { + 0x000061a9, + 0x1307147f, + 0x00080053, + 0x1f2e24f1, + 0x0ab03f13, + 0xff07003f, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x0008000f, + 0x003f0000, + 0x00400000, + 0x0000003f, + 0x00680004, + 0x00dc000e, + 0x00430006, + 0x0005001a, + 0x00000000, + 0x00000002, + 0x0000003f, + 0x00040000, + 0x000000c0, + 0x00c00004, + 0x00070000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x404f2241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x685b1614, + 0x10257000, + 0x9100c050, + 0xc0c0c3f4, + 0x6f031420, + 0x04411031, + 0x22f08250, + 0x26514070, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x643f7000, + 0x1031c052, + 0x31610631, + 0x644202c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006442, + 0x659d658e, + 0x8220c088, + 0x39803950, + 0x40a31e00, + 0x3001c041, + 0x1a181418, + 0x8230c089, + 0x39803960, + 0x40ad1e00, + 0x3001c041, + 0x1a191419, + 0x9136643c, + 0x9134b110, + 0xb054b110, + 0xa0547100, + 0x80f0b064, + 0x40b32200, + 0x90b01240, + 0x8253b032, + 0x39533953, + 0x643f6489, + 0xc122c111, + 0xc1706442, + 0xc11168c6, + 0x6442c0c2, + 0x68cbc170, + 0x9100c050, + 0x92987227, + 0x16141615, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0xb270b051, + 0x72276576, + 0xb2709299, + 0x10731062, + 0x8231c3f0, + 0x39213121, + 0x101b3981, + 0xc0e26576, + 0x82603182, + 0x39803180, + 0xb0610002, + 0x91327100, + 0xa051b110, + 0x7227b061, + 0x68f7c230, + 0x12800000, + 0xb03290b0, + 0xc0507000, + 0x72279100, + 0x10629299, + 0xc3f01073, + 0x31218231, + 0x39813921, + 0xb270b051, + 0x72276582, + 0xb2709298, + 0x10531042, + 0x8221c1f0, + 0x39313131, + 0x31313981, + 0x6582101a, + 0xb061a051, + 0xc0b07227, + 0x643f691c, + 0xc122c101, + 0xc1016442, + 0x6442c0c2, + 0x643c1a15, + 0xb1109135, + 0x64898253, + 0x90b012c0, + 0x7000b032, + 0xc272643f, + 0x6442c081, + 0xc111c122, + 0xc0026442, + 0x6442c111, + 0xc331c062, + 0xc3626442, + 0x6442c111, + 0xc111c302, + 0x82536442, + 0x64893953, + 0x6447c3e2, + 0x41442211, + 0xc881c242, + 0xc2526442, + 0x6442c111, + 0xcee1c272, + 0xc2026442, + 0x6442c881, + 0xc801c202, + 0xc0b06442, + 0x70006958, + 0xc242643f, + 0x6442c801, + 0xc011c252, + 0xc2726442, + 0x6442c0e1, + 0xc101c002, + 0xc0626442, + 0x6442c301, + 0xc101c122, + 0xc3626442, + 0x6442c101, + 0xc101c302, + 0x82536442, + 0x70006489, + 0x7100b061, + 0x1c231412, + 0x91334d7e, + 0x7000b110, + 0xb1109132, + 0x70006976, + 0x7100b061, + 0x1c321813, + 0x9132498a, + 0x7000b110, + 0xb1109133, + 0x70006982, + 0x6447c0c2, + 0xc0c21015, + 0x64471612, + 0x14153141, + 0x3180c0c0, + 0x10541405, + 0x040478b0, + 0xc0e67000, + 0x82613186, + 0x0401cc00, + 0x10671416, + 0xc3f08261, + 0x14170401, + 0x73067000, + 0x720b7205, + 0xb050720e, + 0x80817100, + 0xa050b060, + 0x22418092, + 0x808045c9, + 0x0410c1f1, + 0x11011630, + 0x6c011401, + 0x61dd61dc, + 0x61df61de, + 0x61e161e0, + 0x61e461e2, + 0x61e861e6, + 0x633961ea, + 0x8091633c, + 0x0421c0f2, + 0x80823121, + 0x14122a42, + 0x11011632, + 0x6c011421, + 0x621161f3, + 0x633c61f9, + 0x621161f3, + 0x633c61f9, + 0x61eb61eb, + 0x61eb61eb, + 0x61eb61eb, + 0x61eb6498, + 0x61eb64fd, + 0x61eb652e, + 0x61eb655a, + 0x121061eb, + 0x720e90b0, + 0x72057306, + 0x90301210, + 0xcff061ad, + 0xc1d4673f, + 0xc3c0c003, + 0x78406454, + 0x78609150, + 0x78709210, + 0x78809220, + 0x78909230, + 0x78a09240, + 0x78509260, + 0x783091f0, + 0x82109190, + 0x06f03940, + 0x31101001, + 0x92001410, + 0xa0bc61eb, + 0xa054a0e2, + 0x225080f0, + 0x8040461b, + 0x472e2200, + 0xa0406213, + 0x318d822d, + 0x8210398d, + 0x0410c0f1, + 0x821a1009, + 0x041a394a, + 0x39808210, + 0x100e0410, + 0x10bc10ab, + 0x646310c2, + 0xcfe07229, + 0xb013673f, + 0x66cdb003, + 0xb050b053, + 0xb064b054, + 0x66abb013, + 0x22e08210, + 0x66b4463e, + 0x80417100, + 0x472e2201, + 0x221080f0, + 0x22f04651, + 0xb064471b, + 0x423e2231, + 0x66d3b063, + 0x22e08210, + 0x6676463e, + 0xb064623e, + 0x318f816f, + 0xdfd03d8f, + 0x673f92ff, + 0x80417100, + 0x472e2201, + 0x80f0b064, + 0x426b2250, + 0x8211b063, + 0x466622c1, + 0x670866d3, + 0x22d18211, + 0x66764658, + 0x81616258, + 0x31818172, + 0x31823d81, + 0xefc03d82, + 0x930292f1, + 0x6211673f, + 0x91c081b0, + 0x829781d3, + 0x18d3a290, + 0x0bf34e85, + 0x1ce31613, + 0x91c34aaa, + 0x143b81e3, + 0x1cba6296, + 0x1e234691, + 0x1ce34a91, + 0xb2904e91, + 0x42912207, + 0x1a1ba290, + 0x1ce3629c, + 0x91c34aaa, + 0x183b81e3, + 0x4ea61cab, + 0x4aa81c9b, + 0x42aa1cbc, + 0x821010b2, + 0x42a322d0, + 0x221080f0, + 0x646346aa, + 0x62aa66ab, + 0x629a10ab, + 0x629a109b, + 0x82307000, + 0x0410c0f1, + 0x7100b063, + 0x10bc6aae, + 0x7000b0e0, + 0x91c281b2, + 0x820181d2, + 0x81511812, + 0x82411812, + 0x3d813181, + 0x4ac41c12, + 0xb032b0e2, + 0x673fcfb0, + 0x1421c7f1, + 0xc8124ec8, + 0x91729162, + 0xb0e1b031, + 0x12087000, + 0xc800c006, + 0x91709160, + 0x82017000, + 0x91c081b0, + 0x181081d0, + 0x18108151, + 0x80e11406, + 0x31828242, + 0x1c203d82, + 0xb0e24ae7, + 0x46eb2221, + 0xcfa0b032, + 0x2221673f, + 0xa0e242eb, + 0x8231b032, + 0xc0f03941, + 0x1e010401, + 0x161842f9, + 0x3010c010, + 0x47071c08, + 0x3c101060, + 0xc7f11006, + 0x4efd1461, + 0x9166c816, + 0x31818171, + 0x1c163d81, + 0x91764b04, + 0xc006b031, + 0x70001208, + 0x31818161, + 0x82403d81, + 0x18013980, + 0x4b1a1cf1, + 0x80b01401, + 0x471a22c0, + 0xb033b0bc, + 0x92f1ef90, + 0x673f930f, + 0xa0037000, + 0xb064b063, + 0x655ab0ef, + 0x80407100, + 0x472e2200, + 0x652eb064, + 0x7100a0ef, + 0x22008040, + 0xb064472e, + 0x623eb003, + 0x81628201, + 0x3d823182, + 0x92f1ef80, + 0x673f9302, + 0x655aa003, + 0x80a261eb, + 0x61eb6463, + 0x7100b050, + 0x92e061eb, + 0x220082d0, + 0xb2c04740, + 0x80a07000, + 0x435c22f0, + 0xc102b030, + 0xc0013162, + 0x1e0080a0, + 0x22f04355, + 0xf5d04356, + 0x39603160, + 0x10206356, + 0x6f131a10, + 0x16116e23, + 0x6b571612, + 0x00007000}; PATCH_FUN_SPEC void rf_patch_rfe_genfsk(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ieee.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ieee.h index 21381f5..ddbb6c1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ieee.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ieee.h @@ -1,371 +1,369 @@ /****************************************************************************** -* Filename: rf_patch_rfe_ieee.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC26x0 IEEE 802.15.4. Contains fix to correct RSSIMAXVAL calculation. -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - + * Filename: rf_patch_rfe_ieee.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC26x0 IEEE 802.15.4. Contains fix to correct RSSIMAXVAL calculation. + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_RFE_IEEE_H #define _RF_PATCH_RFE_IEEE_H -#include #include "../inc/hw_types.h" +#include #ifndef RFE_PATCH_TYPE - #define RFE_PATCH_TYPE static const uint32_t +#define RFE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_RFERAM_BASE - #define RFC_RFERAM_BASE 0x2100C000 +#define RFC_RFERAM_BASE 0x2100C000 #endif #ifndef RFE_PATCH_MODE - #define RFE_PATCH_MODE 0 +#define RFE_PATCH_MODE 0 #endif RFE_PATCH_TYPE patchZigbeeXsIsRfe[304] = -{ - 0x00006154, - 0x07f7177f, - 0x004507ff, - 0x0000000f, - 0x002e0004, - 0x0000003f, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x43cf41cf, - 0x4fcf47cf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x00000000, - 0x00000000, - 0x000f0000, - 0x00000008, - 0x0000003f, - 0x003f0040, - 0x00040000, - 0x000e0068, - 0x000600dc, - 0x001a0043, - 0x00000005, - 0x00020000, - 0x00000000, - 0x00000000, - 0x00c00004, - 0x00040000, - 0x000000c0, - 0x00000007, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x9100c050, - 0xc0707000, - 0x70009100, - 0x00213182, - 0xb1109131, - 0x81017000, - 0xa100b101, - 0x91323182, - 0x9101b110, - 0x81411011, - 0x40632241, - 0x700006f1, - 0x9101c051, - 0x39101830, - 0xd0083183, - 0x6f413118, - 0x91310031, - 0x1483b110, - 0x686f1614, - 0x10257000, - 0x9100c050, - 0xc140c3f4, - 0x6f031420, - 0x04411031, - 0x22f08250, - 0x26514084, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0x04411031, - 0x3182c082, - 0x91310021, - 0x3963b110, - 0xc0a21031, - 0x00213182, - 0xb1109131, - 0x31151050, - 0x92051405, - 0x64537000, - 0x1031c052, - 0x31610631, - 0x645602c1, - 0x1031c112, - 0x06713921, - 0x02e13151, - 0x70006456, - 0x9101c051, - 0xc0e2cc01, - 0x64536456, - 0xc0c2c111, - 0xb0546456, - 0xa0547100, - 0x80f0b064, - 0x40b52200, - 0xc122c111, - 0xc0516456, - 0xc0e29101, - 0x82603182, - 0x91320002, - 0xc300b110, - 0x645368c8, - 0x90b01240, - 0xc300b032, - 0xc24068ce, - 0x128068d0, - 0xb03290b0, - 0x64537000, - 0xc122c101, - 0xc1016456, - 0x6456c0c2, - 0x649d8253, - 0x90b012c0, - 0x7000b032, - 0xc2726453, - 0x6456c081, - 0xc111c122, - 0xc0026456, - 0x6456c111, - 0xc331c062, - 0xc3626456, - 0x6456c111, - 0xc111c302, - 0x82536456, - 0x649d3953, - 0x645bc3e2, - 0x40f82211, - 0xc881c242, - 0xc2526456, - 0x6456c111, - 0xcee1c272, - 0xc2026456, - 0x6456c881, - 0xc801c202, - 0xc0b06456, - 0x7000690c, - 0xc2426453, - 0x6456c801, - 0xc011c252, - 0xc2726456, - 0x6456c0e1, - 0xc101c002, - 0xc0626456, - 0x6456c301, - 0xc101c122, - 0xc3626456, - 0x6456c101, - 0xc101c302, - 0x82536456, - 0x7000649d, - 0x3162c102, - 0x80a0c001, - 0x41321e00, - 0x61341a10, - 0x1a101020, - 0x6e236f13, - 0x16121611, - 0x70006934, - 0x82d092e0, - 0x453b2200, - 0x7000b2c0, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x72057306, - 0x720e720b, - 0x7100b050, - 0xb0608081, - 0x8092a050, - 0x92f1ef90, - 0x653a9302, - 0x45782241, - 0xc1f18080, - 0x16300410, - 0x14011101, - 0x61896c01, - 0x618b618a, - 0x618d618c, - 0x618f618e, - 0x61936191, - 0x61976195, - 0x625d625a, - 0x31218091, - 0x2a428082, - 0x16321412, - 0x14211101, - 0x61a76c01, - 0x61ad61c1, - 0x61a7625d, - 0x61ad61c1, - 0x6199625d, - 0x61996199, - 0x61996199, - 0x64ac6199, - 0x64d56199, - 0x64e26199, - 0x650e6199, - 0x652a6199, - 0x80826199, - 0x92f2df80, - 0x1210653a, - 0x61a290b0, - 0x90b01220, - 0x72057306, - 0x90301210, - 0xcf706158, - 0xc284653a, - 0xc3c0c003, - 0x78506468, - 0x78609150, - 0x78613110, - 0x92001410, - 0x31407880, - 0x00107861, - 0x78713140, - 0x92100010, - 0x92207890, - 0x926078a0, - 0xa0546199, - 0x225080f0, - 0x804045c9, - 0x46502200, - 0xcf6061c1, - 0x821e653a, - 0x06f910e9, - 0x10ea394e, - 0x10ac06fa, - 0x06fe394e, - 0x647710c2, - 0x10cb822d, - 0x91907820, - 0xb013661b, - 0xb063b053, - 0xb054b050, - 0xb003b064, - 0x225080f0, - 0x710041c1, - 0x22018041, - 0x22414650, - 0xb06441ec, - 0x81b0b063, - 0x81df91c0, - 0x220080f0, - 0x8090464e, - 0x464e2240, - 0x18d310f3, - 0x0bf34e01, - 0x1ce31613, - 0x91c34a4e, - 0x143b81e3, - 0x1ce36206, - 0x91c34a4e, - 0x183b81e3, - 0x4e171cab, - 0x4a191c9b, - 0x424e1cbc, - 0x10b210bc, - 0x662b6477, - 0xb063662b, - 0xb0637100, - 0xb0637100, - 0x10ab61e2, - 0x109b620a, - 0x7837620a, - 0x18707840, - 0xc0011a10, - 0x16176e71, - 0x78376a20, - 0xc0061208, - 0x9160c800, - 0x10007000, - 0x10f01000, - 0x18108201, - 0x6d716d71, - 0x14061816, - 0x16176e70, - 0x1c177841, - 0x78374638, - 0x1e881618, - 0x1060464b, - 0x81513d30, - 0x80f11810, - 0x41c12251, - 0x81719160, - 0x3d813181, - 0x4a491c10, - 0xb0319170, - 0x70001278, - 0x10001000, - 0x61e2662b, - 0x81628201, - 0x3d823182, - 0x92f1ef50, - 0x653a9302, - 0x6199a003, - 0x647780a2, - 0xb0506199, - 0x61997100 -}; + { + 0x00006154, + 0x07f7177f, + 0x004507ff, + 0x0000000f, + 0x002e0004, + 0x0000003f, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x00000000, + 0x000f0000, + 0x00000008, + 0x0000003f, + 0x003f0040, + 0x00040000, + 0x000e0068, + 0x000600dc, + 0x001a0043, + 0x00000005, + 0x00020000, + 0x00000000, + 0x00000000, + 0x00c00004, + 0x00040000, + 0x000000c0, + 0x00000007, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x40632241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x686f1614, + 0x10257000, + 0x9100c050, + 0xc140c3f4, + 0x6f031420, + 0x04411031, + 0x22f08250, + 0x26514084, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x64537000, + 0x1031c052, + 0x31610631, + 0x645602c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006456, + 0x9101c051, + 0xc0e2cc01, + 0x64536456, + 0xc0c2c111, + 0xb0546456, + 0xa0547100, + 0x80f0b064, + 0x40b52200, + 0xc122c111, + 0xc0516456, + 0xc0e29101, + 0x82603182, + 0x91320002, + 0xc300b110, + 0x645368c8, + 0x90b01240, + 0xc300b032, + 0xc24068ce, + 0x128068d0, + 0xb03290b0, + 0x64537000, + 0xc122c101, + 0xc1016456, + 0x6456c0c2, + 0x649d8253, + 0x90b012c0, + 0x7000b032, + 0xc2726453, + 0x6456c081, + 0xc111c122, + 0xc0026456, + 0x6456c111, + 0xc331c062, + 0xc3626456, + 0x6456c111, + 0xc111c302, + 0x82536456, + 0x649d3953, + 0x645bc3e2, + 0x40f82211, + 0xc881c242, + 0xc2526456, + 0x6456c111, + 0xcee1c272, + 0xc2026456, + 0x6456c881, + 0xc801c202, + 0xc0b06456, + 0x7000690c, + 0xc2426453, + 0x6456c801, + 0xc011c252, + 0xc2726456, + 0x6456c0e1, + 0xc101c002, + 0xc0626456, + 0x6456c301, + 0xc101c122, + 0xc3626456, + 0x6456c101, + 0xc101c302, + 0x82536456, + 0x7000649d, + 0x3162c102, + 0x80a0c001, + 0x41321e00, + 0x61341a10, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006934, + 0x82d092e0, + 0x453b2200, + 0x7000b2c0, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x72057306, + 0x720e720b, + 0x7100b050, + 0xb0608081, + 0x8092a050, + 0x92f1ef90, + 0x653a9302, + 0x45782241, + 0xc1f18080, + 0x16300410, + 0x14011101, + 0x61896c01, + 0x618b618a, + 0x618d618c, + 0x618f618e, + 0x61936191, + 0x61976195, + 0x625d625a, + 0x31218091, + 0x2a428082, + 0x16321412, + 0x14211101, + 0x61a76c01, + 0x61ad61c1, + 0x61a7625d, + 0x61ad61c1, + 0x6199625d, + 0x61996199, + 0x61996199, + 0x64ac6199, + 0x64d56199, + 0x64e26199, + 0x650e6199, + 0x652a6199, + 0x80826199, + 0x92f2df80, + 0x1210653a, + 0x61a290b0, + 0x90b01220, + 0x72057306, + 0x90301210, + 0xcf706158, + 0xc284653a, + 0xc3c0c003, + 0x78506468, + 0x78609150, + 0x78613110, + 0x92001410, + 0x31407880, + 0x00107861, + 0x78713140, + 0x92100010, + 0x92207890, + 0x926078a0, + 0xa0546199, + 0x225080f0, + 0x804045c9, + 0x46502200, + 0xcf6061c1, + 0x821e653a, + 0x06f910e9, + 0x10ea394e, + 0x10ac06fa, + 0x06fe394e, + 0x647710c2, + 0x10cb822d, + 0x91907820, + 0xb013661b, + 0xb063b053, + 0xb054b050, + 0xb003b064, + 0x225080f0, + 0x710041c1, + 0x22018041, + 0x22414650, + 0xb06441ec, + 0x81b0b063, + 0x81df91c0, + 0x220080f0, + 0x8090464e, + 0x464e2240, + 0x18d310f3, + 0x0bf34e01, + 0x1ce31613, + 0x91c34a4e, + 0x143b81e3, + 0x1ce36206, + 0x91c34a4e, + 0x183b81e3, + 0x4e171cab, + 0x4a191c9b, + 0x424e1cbc, + 0x10b210bc, + 0x662b6477, + 0xb063662b, + 0xb0637100, + 0xb0637100, + 0x10ab61e2, + 0x109b620a, + 0x7837620a, + 0x18707840, + 0xc0011a10, + 0x16176e71, + 0x78376a20, + 0xc0061208, + 0x9160c800, + 0x10007000, + 0x10f01000, + 0x18108201, + 0x6d716d71, + 0x14061816, + 0x16176e70, + 0x1c177841, + 0x78374638, + 0x1e881618, + 0x1060464b, + 0x81513d30, + 0x80f11810, + 0x41c12251, + 0x81719160, + 0x3d813181, + 0x4a491c10, + 0xb0319170, + 0x70001278, + 0x10001000, + 0x61e2662b, + 0x81628201, + 0x3d823182, + 0x92f1ef50, + 0x653a9302, + 0x6199a003, + 0x647780a2, + 0xb0506199, + 0x61997100}; PATCH_FUN_SPEC void rf_patch_rfe_ieee(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ieee_s.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ieee_s.h index 0522370..f3bc903 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ieee_s.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/devices/cc26x0/rf_patches/rf_patch_rfe_ieee_s.h @@ -1,371 +1,369 @@ /****************************************************************************** -* Filename: rf_patch_rfe_ieee_s.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for CC26x0 IEEE 802.15.4 Single Ended Output -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - + * Filename: rf_patch_rfe_ieee_s.h + * Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ + * Revision: $Revision: 18842 $ + * + * Description: RF core patch for CC26x0 IEEE 802.15.4 Single Ended Output + * + * Copyright (c) 2015-2019, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1) Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2) Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3) Neither the name of the ORGANIZATION nor the names of its contributors may + * be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ******************************************************************************/ #ifndef _RF_PATCH_RFE_IEEE_S_H #define _RF_PATCH_RFE_IEEE_S_H -#include #include "../inc/hw_types.h" +#include #ifndef RFE_PATCH_TYPE - #define RFE_PATCH_TYPE static const uint32_t +#define RFE_PATCH_TYPE static const uint32_t #endif #ifndef PATCH_FUN_SPEC - #define PATCH_FUN_SPEC static inline +#define PATCH_FUN_SPEC static inline #endif #ifndef RFC_RFERAM_BASE - #define RFC_RFERAM_BASE 0x2100C000 +#define RFC_RFERAM_BASE 0x2100C000 #endif #ifndef RFE_PATCH_MODE - #define RFE_PATCH_MODE 0 +#define RFE_PATCH_MODE 0 #endif RFE_PATCH_TYPE patchZigbeeXsIsRfe[304] = -{ - 0x00006154, - 0x07f7177f, - 0x004507ff, - 0x0000000f, - 0x002e0004, - 0x0000003f, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x43cf41cf, - 0x4fcf47cf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x00000000, - 0x00000000, - 0x000f0000, - 0x00000008, - 0x0000003f, - 0x003f0040, - 0x00040000, - 0x000e0068, - 0x000600dc, - 0x001a0043, - 0x00000005, - 0x00020000, - 0x00000000, - 0x00000000, - 0x00c00004, - 0x00040000, - 0x000000c0, - 0x00000007, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x9100c050, - 0xc0707000, - 0x70009100, - 0x00213182, - 0xb1109131, - 0x81017000, - 0xa100b101, - 0x91323182, - 0x9101b110, - 0x81411011, - 0x40632241, - 0x700006f1, - 0x9101c051, - 0x39101830, - 0xd0083183, - 0x6f413118, - 0x91310031, - 0x1483b110, - 0x686f1614, - 0x10257000, - 0x9100c050, - 0xc140c3f4, - 0x6f031420, - 0x04411031, - 0x22f08250, - 0x26514084, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0x04411031, - 0x3182c082, - 0x91310021, - 0x3963b110, - 0xc0a21031, - 0x00213182, - 0xb1109131, - 0x31151050, - 0x92051405, - 0x64537000, - 0x1031c052, - 0x31610631, - 0x645602c1, - 0x1031c112, - 0x06713921, - 0x02e13151, - 0x70006456, - 0x9101c051, - 0xc0e2cc01, - 0x64536456, - 0xc0c2c111, - 0xb0546456, - 0xa0547100, - 0x80f0b064, - 0x40b52200, - 0xc122c111, - 0xc0516456, - 0xc0e29101, - 0x82603182, - 0x91320002, - 0xc300b110, - 0x645368c8, - 0x90b01240, - 0xc300b032, - 0xc24068ce, - 0x128068d0, - 0xb03290b0, - 0x64537000, - 0xc122c101, - 0xc1016456, - 0x6456c0c2, - 0x649d8253, - 0x90b012c0, - 0x7000b032, - 0xc2726453, - 0x6456c081, - 0xc111c122, - 0xc0026456, - 0x6456c111, - 0xc331c062, - 0xc3626456, - 0x6456c111, - 0xc111c302, - 0x82536456, - 0x649d3953, - 0x645bc3e2, - 0x40f82211, - 0xc881c242, - 0xc2526456, - 0x6456c111, - 0xcee1c272, - 0xc2026456, - 0x6456c881, - 0xc801c202, - 0xc0b06456, - 0x7000690c, - 0xc2426453, - 0x6456c801, - 0xc011c252, - 0xc2726456, - 0x6456c0e1, - 0xc101c002, - 0xc0626456, - 0x6456c301, - 0xc101c122, - 0xc3626456, - 0x6456c101, - 0xc101c302, - 0x82536456, - 0x7000649d, - 0x3162c102, - 0x80a0c001, - 0x41321e00, - 0x61341a10, - 0x1a101020, - 0x6e236f13, - 0x16121611, - 0x70006934, - 0x82d092e0, - 0x453b2200, - 0x7000b2c0, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x72057306, - 0x720e720b, - 0x7100b050, - 0xb0608081, - 0x8092a050, - 0x92f1ef90, - 0x653a9302, - 0x45782241, - 0xc1f18080, - 0x16300410, - 0x14011101, - 0x61896c01, - 0x618b618a, - 0x618d618c, - 0x618f618e, - 0x61936191, - 0x61976195, - 0x625d625a, - 0x31218091, - 0x2a428082, - 0x16321412, - 0x14211101, - 0x61a76c01, - 0x61ad61c1, - 0x61a7625d, - 0x61ad61c1, - 0x6199625d, - 0x61996199, - 0x61996199, - 0x64ac6199, - 0x64d56199, - 0x64e26199, - 0x650e6199, - 0x652a6199, - 0x80826199, - 0x92f2df80, - 0x1210653a, - 0x61a290b0, - 0x90b01220, - 0x72057306, - 0x90301210, - 0xcf706158, - 0xc284653a, - 0xc3c0c003, - 0x78506468, - 0x78609150, - 0x78613110, - 0x92001410, - 0x31407880, - 0x00107861, - 0x78713140, - 0x92100010, - 0x92207890, - 0x926078a0, - 0xa0546199, - 0x225080f0, - 0x804045c9, - 0x46502200, - 0xcf6061c1, - 0x821e653a, - 0x06f910e9, - 0x10ea394e, - 0x10ac06fa, - 0x06fe394e, - 0x647710c2, - 0x10cb822d, - 0x91907820, - 0xb013661b, - 0xb063b053, - 0xb054b050, - 0xb003b064, - 0x225080f0, - 0x710041c1, - 0x22018041, - 0x22414650, - 0xb06441ec, - 0x81b0b063, - 0x81df91c0, - 0x220080f0, - 0x8090464e, - 0x464e2240, - 0x18d310f3, - 0x0bf34e01, - 0x1ce31613, - 0x91c34a4e, - 0x143b81e3, - 0x1ce36206, - 0x91c34a4e, - 0x183b81e3, - 0x4e171cab, - 0x4a191c9b, - 0x424e1cbc, - 0x10b210bc, - 0x662b6477, - 0xb063662b, - 0xb0637100, - 0xb0637100, - 0x10ab61e2, - 0x109b620a, - 0x7837620a, - 0x18707840, - 0xc0011a10, - 0x16176e71, - 0x78376a20, - 0xc0061208, - 0x9160c800, - 0x10007000, - 0x10f01000, - 0x18108201, - 0x6d716d71, - 0x14061816, - 0x16176e70, - 0x1c177841, - 0x78374638, - 0x1e881618, - 0x1060464b, - 0x81513d30, - 0x80f11810, - 0x41c12251, - 0x81719160, - 0x3d813181, - 0x4a491c10, - 0xb0319170, - 0x70001278, - 0x10001000, - 0x61e2662b, - 0x81628201, - 0x3d823182, - 0x92f1ef50, - 0x653a9302, - 0x6199a003, - 0x647780a2, - 0xb0506199, - 0x61997100 -}; + { + 0x00006154, + 0x07f7177f, + 0x004507ff, + 0x0000000f, + 0x002e0004, + 0x0000003f, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x40004030, + 0x40034001, + 0x400f4007, + 0x40cf404f, + 0x43cf41cf, + 0x4fcf47cf, + 0x2fcf3fcf, + 0x0fcf1fcf, + 0x00000000, + 0x00000000, + 0x000f0000, + 0x00000008, + 0x0000003f, + 0x003f0040, + 0x00040000, + 0x000e0068, + 0x000600dc, + 0x001a0043, + 0x00000005, + 0x00020000, + 0x00000000, + 0x00000000, + 0x00c00004, + 0x00040000, + 0x000000c0, + 0x00000007, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x9100c050, + 0xc0707000, + 0x70009100, + 0x00213182, + 0xb1109131, + 0x81017000, + 0xa100b101, + 0x91323182, + 0x9101b110, + 0x81411011, + 0x40632241, + 0x700006f1, + 0x9101c051, + 0x39101830, + 0xd0083183, + 0x6f413118, + 0x91310031, + 0x1483b110, + 0x686f1614, + 0x10257000, + 0x9100c050, + 0xc140c3f4, + 0x6f031420, + 0x04411031, + 0x22f08250, + 0x26514084, + 0x3182c022, + 0x91310021, + 0x3963b110, + 0x04411031, + 0x3182c082, + 0x91310021, + 0x3963b110, + 0xc0a21031, + 0x00213182, + 0xb1109131, + 0x31151050, + 0x92051405, + 0x64537000, + 0x1031c052, + 0x31610631, + 0x645602c1, + 0x1031c112, + 0x06713921, + 0x02e13151, + 0x70006456, + 0x9101c051, + 0xc0e2cc01, + 0x64536456, + 0xc0c2c111, + 0xb0546456, + 0xa0547100, + 0x80f0b064, + 0x40b52200, + 0xc122c111, + 0xc0516456, + 0xc0e29101, + 0x82603182, + 0x91320002, + 0xc300b110, + 0x645368c8, + 0x90b01240, + 0xc300b032, + 0xc24068ce, + 0x128068d0, + 0xb03290b0, + 0x64537000, + 0xc122c101, + 0xc1016456, + 0x6456c0c2, + 0x649d8253, + 0x90b012c0, + 0x7000b032, + 0xc2726453, + 0x6456c081, + 0xc111c122, + 0xc0026456, + 0x6456c111, + 0xc331c062, + 0xc3626456, + 0x6456c111, + 0xc111c302, + 0x82536456, + 0x649d3953, + 0x645bc3e2, + 0x40f82211, + 0xc881c242, + 0xc2526456, + 0x6456c111, + 0xcee1c272, + 0xc2026456, + 0x6456c881, + 0xc801c202, + 0xc0b06456, + 0x7000690c, + 0xc2426453, + 0x6456c801, + 0xc011c252, + 0xc2726456, + 0x6456c0e1, + 0xc101c002, + 0xc0626456, + 0x6456c301, + 0xc101c122, + 0xc3626456, + 0x6456c101, + 0xc101c302, + 0x82536456, + 0x7000649d, + 0x3162c102, + 0x80a0c001, + 0x41321e00, + 0x61341a10, + 0x1a101020, + 0x6e236f13, + 0x16121611, + 0x70006934, + 0x82d092e0, + 0x453b2200, + 0x7000b2c0, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x72057306, + 0x720e720b, + 0x7100b050, + 0xb0608081, + 0x8092a050, + 0x92f1ef90, + 0x653a9302, + 0x45782241, + 0xc1f18080, + 0x16300410, + 0x14011101, + 0x61896c01, + 0x618b618a, + 0x618d618c, + 0x618f618e, + 0x61936191, + 0x61976195, + 0x625d625a, + 0x31218091, + 0x2a428082, + 0x16321412, + 0x14211101, + 0x61a76c01, + 0x61ad61c1, + 0x61a7625d, + 0x61ad61c1, + 0x6199625d, + 0x61996199, + 0x61996199, + 0x64ac6199, + 0x64d56199, + 0x64e26199, + 0x650e6199, + 0x652a6199, + 0x80826199, + 0x92f2df80, + 0x1210653a, + 0x61a290b0, + 0x90b01220, + 0x72057306, + 0x90301210, + 0xcf706158, + 0xc284653a, + 0xc3c0c003, + 0x78506468, + 0x78609150, + 0x78613110, + 0x92001410, + 0x31407880, + 0x00107861, + 0x78713140, + 0x92100010, + 0x92207890, + 0x926078a0, + 0xa0546199, + 0x225080f0, + 0x804045c9, + 0x46502200, + 0xcf6061c1, + 0x821e653a, + 0x06f910e9, + 0x10ea394e, + 0x10ac06fa, + 0x06fe394e, + 0x647710c2, + 0x10cb822d, + 0x91907820, + 0xb013661b, + 0xb063b053, + 0xb054b050, + 0xb003b064, + 0x225080f0, + 0x710041c1, + 0x22018041, + 0x22414650, + 0xb06441ec, + 0x81b0b063, + 0x81df91c0, + 0x220080f0, + 0x8090464e, + 0x464e2240, + 0x18d310f3, + 0x0bf34e01, + 0x1ce31613, + 0x91c34a4e, + 0x143b81e3, + 0x1ce36206, + 0x91c34a4e, + 0x183b81e3, + 0x4e171cab, + 0x4a191c9b, + 0x424e1cbc, + 0x10b210bc, + 0x662b6477, + 0xb063662b, + 0xb0637100, + 0xb0637100, + 0x10ab61e2, + 0x109b620a, + 0x7837620a, + 0x18707840, + 0xc0011a10, + 0x16176e71, + 0x78376a20, + 0xc0061208, + 0x9160c800, + 0x10007000, + 0x10f01000, + 0x18108201, + 0x6d716d71, + 0x14061816, + 0x16176e70, + 0x1c177841, + 0x78374638, + 0x1e881618, + 0x1060464b, + 0x81513d30, + 0x80f11810, + 0x41c12251, + 0x81719160, + 0x3d813181, + 0x4a491c10, + 0xb0319170, + 0x70001278, + 0x10001000, + 0x61e2662b, + 0x81628201, + 0x3d823182, + 0x92f1ef50, + 0x653a9302, + 0x6199a003, + 0x647780a2, + 0xb0506199, + 0x61997100}; PATCH_FUN_SPEC void rf_patch_rfe_ieee_s(void) { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ADC.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ADC.h index 0de5a18..4dc9fe3 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ADC.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ADC.h @@ -183,7 +183,7 @@ extern "C" { * #define ADCXYZ_CMD_COMMAND1 ADC_CMD_RESERVED + 1 * @endcode */ -#define ADC_CMD_RESERVED (32) +#define ADC_CMD_RESERVED (32) /*! * @hideinitializer @@ -198,7 +198,7 @@ extern "C" { * #define ADCXYZ_STATUS_ERROR2 ADC_STATUS_RESERVED - 2 * @endcode */ -#define ADC_STATUS_RESERVED (-32) +#define ADC_STATUS_RESERVED (-32) /*! * @brief Successful status code returned by ADC_control(). @@ -208,7 +208,7 @@ extern "C" { * @{ * @ingroup ADC_CONTROL */ -#define ADC_STATUS_SUCCESS (0) +#define ADC_STATUS_SUCCESS (0) /*! * @brief Generic error status code returned by ADC_control(). @@ -216,7 +216,7 @@ extern "C" { * ADC_control() returns ADC_STATUS_ERROR if the control code was not executed * successfully. */ -#define ADC_STATUS_ERROR (-1) +#define ADC_STATUS_ERROR (-1) /*! * @brief An error status code returned by ADC_control() for undefined @@ -225,7 +225,7 @@ extern "C" { * ADC_control() returns ADC_STATUS_UNDEFINEDCMD if the control code is not * recognized by the driver implementation. */ -#define ADC_STATUS_UNDEFINEDCMD (-2) +#define ADC_STATUS_UNDEFINEDCMD (-2) /** @}*/ /** @@ -245,7 +245,7 @@ extern "C" { /*! * @brief A handle that is returned from an ADC_open() call. */ -typedef struct ADC_Config* ADC_Handle; +typedef struct ADC_Config* ADC_Handle; /*! * @brief ADC Parameters used with ADC_open(). @@ -257,15 +257,15 @@ typedef struct ADC_Config* ADC_Handle; */ typedef struct { - void* custom; /*!< Custom argument used by driver - implementation */ - bool isProtected; /*!< By default ADC uses a semaphore - to guarantee thread safety. Setting - this parameter to 'false' will eliminate - the usage of a semaphore for thread - safety. The user is then responsible - for ensuring that parallel invocations - of ADC_convert() are thread safe. */ + void* custom; /*!< Custom argument used by driver + implementation */ + bool isProtected; /*!< By default ADC uses a semaphore + to guarantee thread safety. Setting + this parameter to 'false' will eliminate + the usage of a semaphore for thread + safety. The user is then responsible + for ensuring that parallel invocations + of ADC_convert() are thread safe. */ } ADC_Params; /*! @@ -273,44 +273,44 @@ typedef struct * @brief A function pointer to a driver specific implementation of * ADC_close(). */ -typedef void (*ADC_CloseFxn) (ADC_Handle handle); +typedef void (*ADC_CloseFxn)(ADC_Handle handle); /*! * @private * @brief A function pointer to a driver specific implementation of * ADC_control(). */ -typedef int_fast16_t (*ADC_ControlFxn) (ADC_Handle handle, uint_fast16_t cmd, - void* arg); +typedef int_fast16_t (*ADC_ControlFxn)(ADC_Handle handle, uint_fast16_t cmd, + void* arg); /*! * @private * @brief A function pointer to a driver specific implementation of * ADC_ConvertFxn(). */ -typedef int_fast16_t (*ADC_ConvertFxn) (ADC_Handle handle, uint16_t* value); +typedef int_fast16_t (*ADC_ConvertFxn)(ADC_Handle handle, uint16_t* value); /*! * @private * @brief A function pointer to a driver specific implementation of * ADC_convertToMicroVolts(). */ -typedef uint32_t (*ADC_ConvertToMicroVoltsFxn) (ADC_Handle handle, - uint16_t adcValue); +typedef uint32_t (*ADC_ConvertToMicroVoltsFxn)(ADC_Handle handle, + uint16_t adcValue); /*! * @private * @brief A function pointer to a driver specific implementation of * ADC_init(). */ -typedef void (*ADC_InitFxn) (ADC_Handle handle); +typedef void (*ADC_InitFxn)(ADC_Handle handle); /*! * @private * @brief A function pointer to a driver specific implementation of * ADC_open(). */ -typedef ADC_Handle (*ADC_OpenFxn) (ADC_Handle handle, ADC_Params* params); +typedef ADC_Handle (*ADC_OpenFxn)(ADC_Handle handle, ADC_Params* params); /*! * @brief The definition of an ADC function table that contains the @@ -319,23 +319,23 @@ typedef ADC_Handle (*ADC_OpenFxn) (ADC_Handle handle, ADC_Params* params); */ typedef struct { - /*! Function to close the specified peripheral */ - ADC_CloseFxn closeFxn; + /*! Function to close the specified peripheral */ + ADC_CloseFxn closeFxn; - /*! Function to perform implementation specific features */ - ADC_ControlFxn controlFxn; + /*! Function to perform implementation specific features */ + ADC_ControlFxn controlFxn; - /*! Function to initiate an ADC single channel conversion */ - ADC_ConvertFxn convertFxn; + /*! Function to initiate an ADC single channel conversion */ + ADC_ConvertFxn convertFxn; - /*! Function to convert ADC result to microvolts */ - ADC_ConvertToMicroVoltsFxn convertToMicroVolts; + /*! Function to convert ADC result to microvolts */ + ADC_ConvertToMicroVoltsFxn convertToMicroVolts; - /*! Function to initialize the given data object */ - ADC_InitFxn initFxn; + /*! Function to initialize the given data object */ + ADC_InitFxn initFxn; - /*! Function to open the specified peripheral */ - ADC_OpenFxn openFxn; + /*! Function to open the specified peripheral */ + ADC_OpenFxn openFxn; } ADC_FxnTable; /*! @@ -347,16 +347,16 @@ typedef struct */ typedef struct ADC_Config { - /*! Pointer to a @ref driver_function_table "function pointer table" - * with driver-specific implementations of ADC APIs */ - ADC_FxnTable const* fxnTablePtr; + /*! Pointer to a @ref driver_function_table "function pointer table" + * with driver-specific implementations of ADC APIs */ + ADC_FxnTable const* fxnTablePtr; - /*! Pointer to a driver specific @ref driver_objects "data object". */ - void* object; + /*! Pointer to a driver specific @ref driver_objects "data object". */ + void* object; - /*! Pointer to a driver specific @ref driver_hardware_attributes - * "hardware attributes structure". */ - void const* hwAttrs; + /*! Pointer to a driver specific @ref driver_hardware_attributes + * "hardware attributes structure". */ + void const* hwAttrs; } ADC_Config; /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ADCBuf.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ADCBuf.h index cdaa881..a82064a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ADCBuf.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ADCBuf.h @@ -234,7 +234,7 @@ extern "C" { * #define ADCXYZ_COMMAND1 ADCBuf_CMD_RESERVED + 1 * @endcode */ -#define ADCBuf_CMD_RESERVED (32) +#define ADCBuf_CMD_RESERVED (32) /*! * Common ADCBuf_control status code reservation offset. @@ -248,7 +248,7 @@ extern "C" { * #define ADCXYZ_STATUS_ERROR2 ADCBuf_STATUS_RESERVED - 2 * @endcode */ -#define ADCBuf_STATUS_RESERVED (-32) +#define ADCBuf_STATUS_RESERVED (-32) /*! * @brief Success status code returned by: @@ -259,7 +259,7 @@ extern "C" { * @{ * @ingroup ADCBuf_CONTROL */ -#define ADCBuf_STATUS_SUCCESS (0) +#define ADCBuf_STATUS_SUCCESS (0) /*! * @brief Generic error status code returned by ADCBuf_control(). @@ -267,7 +267,7 @@ extern "C" { * ADCBuf_control() returns #ADCBuf_STATUS_ERROR if the control code was * not executed successfully. */ -#define ADCBuf_STATUS_ERROR (-1) +#define ADCBuf_STATUS_ERROR (-1) /*! * @brief An error status code returned by ADCBuf_control() for undefined @@ -276,13 +276,13 @@ extern "C" { * ADCBuf_control() returns ADCBuf_STATUS_UNDEFINEDCMD if the control code is * not recognized by the driver implementation. */ -#define ADCBuf_STATUS_UNDEFINEDCMD (-2) +#define ADCBuf_STATUS_UNDEFINEDCMD (-2) /*! * @brief An error status code returned if the function is not supported * by a particular driver implementation. */ -#define ADCBuf_STATUS_UNSUPPORTED (-3) +#define ADCBuf_STATUS_UNSUPPORTED (-3) /** @}*/ /** @@ -299,11 +299,10 @@ extern "C" { /** @}*/ - /*! * @brief A handle that is returned from an ADCBuf_open() call. */ -typedef struct ADCBuf_Config* ADCBuf_Handle; +typedef struct ADCBuf_Config* ADCBuf_Handle; /*! * @brief Defines a conversion to be used with ADCBuf_convert(). @@ -314,50 +313,50 @@ typedef struct ADCBuf_Config* ADCBuf_Handle; */ typedef struct { - /*! - * Defines the number of samples to be performed on the - * ADCBuf_Conversion.channel. The application buffers provided by - * #ADCBuf_Conversion.sampleBuffer and #ADCBuf_Conversion.sampleBufferTwo - * must be large enough to hold @p samplesRequestedCount samples. - */ - uint16_t samplesRequestedCount; + /*! + * Defines the number of samples to be performed on the + * ADCBuf_Conversion.channel. The application buffers provided by + * #ADCBuf_Conversion.sampleBuffer and #ADCBuf_Conversion.sampleBufferTwo + * must be large enough to hold @p samplesRequestedCount samples. + */ + uint16_t samplesRequestedCount; - /*! - * Buffer to store ADCBuf conversion results. This buffer must be at least - * (#ADCBuf_Conversion.samplesRequestedCount * 2) bytes. When using - * #ADCBuf_RECURRENCE_MODE_ONE_SHOT, only this buffer is used. - */ - void* sampleBuffer; + /*! + * Buffer to store ADCBuf conversion results. This buffer must be at least + * (#ADCBuf_Conversion.samplesRequestedCount * 2) bytes. When using + * #ADCBuf_RECURRENCE_MODE_ONE_SHOT, only this buffer is used. + */ + void* sampleBuffer; - /*! - * Buffer to store ADCBuf conversion results. This buffer must be at least - * (#ADCBuf_Conversion.samplesRequestedCount * 2) bytes. When using - * #ADCBuf_RECURRENCE_MODE_ONE_SHOT, this buffer is not used. When - * using #ADCBuf_RECURRENCE_MODE_CONTINUOUS, this must point to - * a valid buffer. - * - * @sa #ADCBuf_RECURRENCE_MODE_CONTINUOUS - */ - void* sampleBufferTwo; + /*! + * Buffer to store ADCBuf conversion results. This buffer must be at least + * (#ADCBuf_Conversion.samplesRequestedCount * 2) bytes. When using + * #ADCBuf_RECURRENCE_MODE_ONE_SHOT, this buffer is not used. When + * using #ADCBuf_RECURRENCE_MODE_CONTINUOUS, this must point to + * a valid buffer. + * + * @sa #ADCBuf_RECURRENCE_MODE_CONTINUOUS + */ + void* sampleBufferTwo; - /*! - * Pointer to a custom argument to be passed to the #ADCBuf_Callback - * function via the #ADCBuf_Conversion structure. - * - * @note The #ADCBuf_Callback function is only called when operating in - * #ADCBuf_RETURN_MODE_CALLBACK. - * - * @sa #ADCBuf_RETURN_MODE_CALLBACK - * @sa #ADCBuf_Callback - */ - void* arg; + /*! + * Pointer to a custom argument to be passed to the #ADCBuf_Callback + * function via the #ADCBuf_Conversion structure. + * + * @note The #ADCBuf_Callback function is only called when operating in + * #ADCBuf_RETURN_MODE_CALLBACK. + * + * @sa #ADCBuf_RETURN_MODE_CALLBACK + * @sa #ADCBuf_Callback + */ + void* arg; - /*! - * ADCBuf channel to perform conversions on. Mapping of channel to pin or - * internal signal is device specific. Refer to the device specific - * implementation. - */ - uint32_t adcChannel; + /*! + * ADCBuf channel to perform conversions on. Mapping of channel to pin or + * internal signal is device specific. Refer to the device specific + * implementation. + */ + uint32_t adcChannel; } ADCBuf_Conversion; /*! @@ -388,10 +387,10 @@ typedef struct * @sa ADCBuf_Recurrence_Mode * @sa ADCBuf_RETURN_MODE_CALLBACK */ -typedef void (*ADCBuf_Callback) (ADCBuf_Handle handle, - ADCBuf_Conversion* conversion, - void* completedADCBuffer, - uint32_t completedChannel); +typedef void (*ADCBuf_Callback)(ADCBuf_Handle handle, + ADCBuf_Conversion* conversion, + void* completedADCBuffer, + uint32_t completedChannel); /*! * @brief Recurrence behavior of a #ADCBuf_Conversion specified in the @@ -404,14 +403,14 @@ typedef void (*ADCBuf_Callback) (ADCBuf_Handle handle, typedef enum { /*! - * When operating in #ADCBuf_RECURRENCE_MODE_ONE_SHOT, calls to - * ADCBuf_convert() will pend on a semaphore until - * #ADCBuf_Conversion.samplesRequestedCount samples are completed or - * after a duration of #ADCBuf_Params.blockingTimeout. - * - * @note When using #ADCBuf_RECURRENCE_MODE_ONE_SHOT, ADCBuf_convert() - * must be called from a thread context. #ADCBuf_RECURRENCE_MODE_ONE_SHOT - * can only be used in combination with #ADCBuf_RETURN_MODE_BLOCKING. + * When operating in #ADCBuf_RECURRENCE_MODE_ONE_SHOT, calls to + * ADCBuf_convert() will pend on a semaphore until + * #ADCBuf_Conversion.samplesRequestedCount samples are completed or + * after a duration of #ADCBuf_Params.blockingTimeout. + * + * @note When using #ADCBuf_RECURRENCE_MODE_ONE_SHOT, ADCBuf_convert() + * must be called from a thread context. #ADCBuf_RECURRENCE_MODE_ONE_SHOT + * can only be used in combination with #ADCBuf_RETURN_MODE_BLOCKING. */ ADCBuf_RECURRENCE_MODE_ONE_SHOT, @@ -446,15 +445,15 @@ typedef enum typedef enum { /*! - * When operating in #ADCBuf_RETURN_MODE_BLOCKING, calls to - * ADCBuf_convert() will pend on a semaphore until - * #ADCBuf_Conversion.samplesRequestedCount samples are completed or - * after a duration of #ADCBuf_Params.blockingTimeout. - * - * @note When using #ADCBuf_RETURN_MODE_BLOCKING, ADCBuf_convert() - * must be called from a thread context. #ADCBuf_RETURN_MODE_BLOCKING - * can only be used in combination with #ADCBuf_RECURRENCE_MODE_ONE_SHOT. - */ + * When operating in #ADCBuf_RETURN_MODE_BLOCKING, calls to + * ADCBuf_convert() will pend on a semaphore until + * #ADCBuf_Conversion.samplesRequestedCount samples are completed or + * after a duration of #ADCBuf_Params.blockingTimeout. + * + * @note When using #ADCBuf_RETURN_MODE_BLOCKING, ADCBuf_convert() + * must be called from a thread context. #ADCBuf_RETURN_MODE_BLOCKING + * can only be used in combination with #ADCBuf_RECURRENCE_MODE_ONE_SHOT. + */ ADCBuf_RETURN_MODE_BLOCKING, /*! @@ -481,41 +480,41 @@ typedef enum */ typedef struct { - /*! - * Timeout in system clock ticks. This value is only valid when using - * #ADCBuf_RETURN_MODE_BLOCKING. A call to ADCBuf_convert() will block - * for a duration up to @p blockingTimeout ticks. The call to - * ADCBuf_convert() will return prior if the requested number of samples - * in #ADCBuf_Conversion.samplesRequestedCount are completed. The - * @p blockingTimeout should be large enough to allow for - * #ADCBuf_Conversion.samplesRequestedCount samples to be collected - * given the #ADCBuf_Params.samplingFrequency. - * - * @sa #ADCBuf_RETURN_MODE_BLOCKING - */ - uint32_t blockingTimeout; + /*! + * Timeout in system clock ticks. This value is only valid when using + * #ADCBuf_RETURN_MODE_BLOCKING. A call to ADCBuf_convert() will block + * for a duration up to @p blockingTimeout ticks. The call to + * ADCBuf_convert() will return prior if the requested number of samples + * in #ADCBuf_Conversion.samplesRequestedCount are completed. The + * @p blockingTimeout should be large enough to allow for + * #ADCBuf_Conversion.samplesRequestedCount samples to be collected + * given the #ADCBuf_Params.samplingFrequency. + * + * @sa #ADCBuf_RETURN_MODE_BLOCKING + */ + uint32_t blockingTimeout; - /*! - * The frequency at which the ADC will sample in Hertz (Hz). After a - * call to ADCBuf_convert(), the ADC will perform @p samplingFrequency - * samples per second. - */ - uint32_t samplingFrequency; + /*! + * The frequency at which the ADC will sample in Hertz (Hz). After a + * call to ADCBuf_convert(), the ADC will perform @p samplingFrequency + * samples per second. + */ + uint32_t samplingFrequency; - /*! #ADCBuf_Return_Mode for all conversions. */ - ADCBuf_Return_Mode returnMode; + /*! #ADCBuf_Return_Mode for all conversions. */ + ADCBuf_Return_Mode returnMode; - /*! - * Pointer to a #ADCBuf_Callback function to be invoked after a - * conversion completes when operating in #ADCBuf_RETURN_MODE_CALLBACK. - */ - ADCBuf_Callback callbackFxn; + /*! + * Pointer to a #ADCBuf_Callback function to be invoked after a + * conversion completes when operating in #ADCBuf_RETURN_MODE_CALLBACK. + */ + ADCBuf_Callback callbackFxn; - /*! #ADCBuf_Recurrence_Mode for all conversions. */ - ADCBuf_Recurrence_Mode recurrenceMode; + /*! #ADCBuf_Recurrence_Mode for all conversions. */ + ADCBuf_Recurrence_Mode recurrenceMode; - /*! Pointer to a device specific extension of the #ADCBuf_Params */ - void* custom; + /*! Pointer to a device specific extension of the #ADCBuf_Params */ + void* custom; } ADCBuf_Params; /*! @@ -523,39 +522,39 @@ typedef struct * @brief A function pointer to a driver specific implementation of * ADCBuf_close(). */ -typedef void (*ADCBuf_CloseFxn) (ADCBuf_Handle handle); +typedef void (*ADCBuf_CloseFxn)(ADCBuf_Handle handle); /*! * @private * @brief A function pointer to a driver specific implementation of * ADCBuf_open(). */ -typedef ADCBuf_Handle (*ADCBuf_OpenFxn) (ADCBuf_Handle handle, - const ADCBuf_Params* params); +typedef ADCBuf_Handle (*ADCBuf_OpenFxn)(ADCBuf_Handle handle, + const ADCBuf_Params* params); /*! * @private * @brief A function pointer to a driver specific implementation of * ADCBuf_control(). */ -typedef int_fast16_t (*ADCBuf_ControlFxn) (ADCBuf_Handle handle, - uint_fast8_t cmd, - void* arg); +typedef int_fast16_t (*ADCBuf_ControlFxn)(ADCBuf_Handle handle, + uint_fast8_t cmd, + void* arg); /*! * @private * @brief A function pointer to a driver specific implementation of * ADCBuf_init(). */ -typedef void (*ADCBuf_InitFxn) (ADCBuf_Handle handle); +typedef void (*ADCBuf_InitFxn)(ADCBuf_Handle handle); /*! * @private * @brief A function pointer to a driver specific implementation of * ADCBuf_convert(). */ -typedef int_fast16_t (*ADCBuf_ConvertFxn) (ADCBuf_Handle handle, - ADCBuf_Conversion conversions[], - uint_fast8_t channelCount); +typedef int_fast16_t (*ADCBuf_ConvertFxn)(ADCBuf_Handle handle, + ADCBuf_Conversion conversions[], + uint_fast8_t channelCount); /*! * @private * @brief A function pointer to a driver specific implementation of @@ -568,7 +567,7 @@ typedef int_fast16_t (*ADCBuf_ConvertCancelFxn)(ADCBuf_Handle handle); * @brief A function pointer to a driver specific implementation of * ADCBuf_GetResolution(); */ -typedef uint_fast8_t (*ADCBuf_GetResolutionFxn) (ADCBuf_Handle handle); +typedef uint_fast8_t (*ADCBuf_GetResolutionFxn)(ADCBuf_Handle handle); /*! * @private @@ -576,16 +575,16 @@ typedef uint_fast8_t (*ADCBuf_GetResolutionFxn) (ADCBuf_Handle handle); * ADCBuf_adjustRawValues(); */ typedef int_fast16_t (*ADCBuf_adjustRawValuesFxn)(ADCBuf_Handle handle, - void* sampleBuffer, - uint_fast16_t sampleCount, - uint32_t adcChannel); + void* sampleBuffer, + uint_fast16_t sampleCount, + uint32_t adcChannel); /*! * @private * @brief A function pointer to a driver specific implementation of * ADCBuf_convertAdjustedToMicroVolts(); */ -typedef int_fast16_t (*ADCBuf_convertAdjustedToMicroVoltsFxn) ( +typedef int_fast16_t (*ADCBuf_convertAdjustedToMicroVoltsFxn)( ADCBuf_Handle handle, uint32_t adcChannel, void* adjustedSampleBuffer, @@ -599,26 +598,26 @@ typedef int_fast16_t (*ADCBuf_convertAdjustedToMicroVoltsFxn) ( */ typedef struct { - /*! Function to close the specified peripheral */ - ADCBuf_CloseFxn closeFxn; - /*! Function to driver implementation specific control function */ - ADCBuf_ControlFxn controlFxn; - /*! Function to initialize the given data object */ - ADCBuf_InitFxn initFxn; - /*! Function to open the specified peripheral */ - ADCBuf_OpenFxn openFxn; - /*! Function to start an ADC conversion with the specified peripheral */ - ADCBuf_ConvertFxn convertFxn; - /*! Function to abort a conversion being carried out by the specified - peripheral */ - ADCBuf_ConvertCancelFxn convertCancelFxn; - /*! Function to get the resolution in bits of the ADC */ - ADCBuf_GetResolutionFxn getResolutionFxn; - /*! Function to adjust raw ADC return bit values to values comparable - between devices of the same type */ - ADCBuf_adjustRawValuesFxn adjustRawValuesFxn; - /*! Function to convert adjusted ADC values to microvolts */ - ADCBuf_convertAdjustedToMicroVoltsFxn convertAdjustedToMicroVoltsFxn; + /*! Function to close the specified peripheral */ + ADCBuf_CloseFxn closeFxn; + /*! Function to driver implementation specific control function */ + ADCBuf_ControlFxn controlFxn; + /*! Function to initialize the given data object */ + ADCBuf_InitFxn initFxn; + /*! Function to open the specified peripheral */ + ADCBuf_OpenFxn openFxn; + /*! Function to start an ADC conversion with the specified peripheral */ + ADCBuf_ConvertFxn convertFxn; + /*! Function to abort a conversion being carried out by the specified + peripheral */ + ADCBuf_ConvertCancelFxn convertCancelFxn; + /*! Function to get the resolution in bits of the ADC */ + ADCBuf_GetResolutionFxn getResolutionFxn; + /*! Function to adjust raw ADC return bit values to values comparable + between devices of the same type */ + ADCBuf_adjustRawValuesFxn adjustRawValuesFxn; + /*! Function to convert adjusted ADC values to microvolts */ + ADCBuf_convertAdjustedToMicroVoltsFxn convertAdjustedToMicroVoltsFxn; } ADCBuf_FxnTable; /*! @@ -630,16 +629,16 @@ typedef struct */ typedef struct ADCBuf_Config { - /*! Pointer to a @ref driver_function_table "function pointer table" - * with driver-specific implementations of ADC APIs */ - const ADCBuf_FxnTable* fxnTablePtr; + /*! Pointer to a @ref driver_function_table "function pointer table" + * with driver-specific implementations of ADC APIs */ + const ADCBuf_FxnTable* fxnTablePtr; - /*! Pointer to a driver specific @ref driver_objects "data object". */ - void* object; + /*! Pointer to a driver specific @ref driver_objects "data object". */ + void* object; - /*! Pointer to a driver specific @ref driver_hardware_attributes - * "hardware attributes structure". */ - void const* hwAttrs; + /*! Pointer to a driver specific @ref driver_hardware_attributes + * "hardware attributes structure". */ + void const* hwAttrs; } ADCBuf_Config; /*! @@ -772,55 +771,55 @@ extern int_fast16_t ADCBuf_convertCancel(ADCBuf_Handle handle); extern uint_fast8_t ADCBuf_getResolution(ADCBuf_Handle handle); /*! -* @brief Adjust a raw ADC output buffer. The function does -* the adjustment in-place. -* -* @param[in] handle An ADCBuf_Handle returned from ADCBuf_open(). -* -* @param[in,out] sampleBuf A buffer full of raw sample values. -* -* @param[in] sampleCount The number of samples to adjust. -* -* @param[in] adcChan The channel the buffer was sampled on. -* -* @retval #ADCBuf_STATUS_SUCCESS The operation was successful. -* @p sampleBuf contains valid values. -* -* @retval #ADCBuf_STATUS_ERROR if an error occurred. -* -* @retval #ADCBuf_STATUS_UNSUPPORTED The function is not supported by the -* device specific implementation. -* -* @pre ADCBuf_convert() must have returned a valid buffer with samples. -*/ + * @brief Adjust a raw ADC output buffer. The function does + * the adjustment in-place. + * + * @param[in] handle An ADCBuf_Handle returned from ADCBuf_open(). + * + * @param[in,out] sampleBuf A buffer full of raw sample values. + * + * @param[in] sampleCount The number of samples to adjust. + * + * @param[in] adcChan The channel the buffer was sampled on. + * + * @retval #ADCBuf_STATUS_SUCCESS The operation was successful. + * @p sampleBuf contains valid values. + * + * @retval #ADCBuf_STATUS_ERROR if an error occurred. + * + * @retval #ADCBuf_STATUS_UNSUPPORTED The function is not supported by the + * device specific implementation. + * + * @pre ADCBuf_convert() must have returned a valid buffer with samples. + */ extern int_fast16_t ADCBuf_adjustRawValues(ADCBuf_Handle handle, - void* sampleBuf, - uint_fast16_t sampleCount, - uint32_t adcChan); + void* sampleBuf, + uint_fast16_t sampleCount, + uint32_t adcChan); /*! -* @brief Convert an adjusted ADC output buffer to microvolts. -* -* @param[in] handle An ADCBuf_Handle returned from ADCBuf_open() -* -* @param[in] adcChan The ADC channel the samples were performed on. -* -* @param[in] adjustedSampleBuffer A buffer full of adjusted samples. -* -* @param[in,out] outputMicroVoltBuffer The output buffer. -* -* @param[in] sampleCount The number of samples to convert. -* -* @retval #ADCBuf_STATUS_SUCCESS The operation was successful. -* @p outputMicroVoltBuffer contains valid values. -* -* @retval #ADCBuf_STATUS_ERROR The operation failed. -* -* @pre ADCBuf_adjustRawValues() must be called on @p adjustedSampleBuffer. -*/ + * @brief Convert an adjusted ADC output buffer to microvolts. + * + * @param[in] handle An ADCBuf_Handle returned from ADCBuf_open() + * + * @param[in] adcChan The ADC channel the samples were performed on. + * + * @param[in] adjustedSampleBuffer A buffer full of adjusted samples. + * + * @param[in,out] outputMicroVoltBuffer The output buffer. + * + * @param[in] sampleCount The number of samples to convert. + * + * @retval #ADCBuf_STATUS_SUCCESS The operation was successful. + * @p outputMicroVoltBuffer contains valid values. + * + * @retval #ADCBuf_STATUS_ERROR The operation failed. + * + * @pre ADCBuf_adjustRawValues() must be called on @p adjustedSampleBuffer. + */ extern int_fast16_t ADCBuf_convertAdjustedToMicroVolts( ADCBuf_Handle handle, - uint32_t adcChan, + uint32_t adcChan, void* adjustedSampleBuffer, uint32_t outputMicroVoltBuffer[], uint_fast16_t sampleCount); diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCBC.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCBC.h index 8fbdc31..2472677 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCBC.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCBC.h @@ -328,7 +328,7 @@ extern "C" { * #define AESCBCXYZ_STATUS_ERROR2 AESCBC_STATUS_RESERVED - 2 * @endcode */ -#define AESCBC_STATUS_RESERVED (-32) +#define AESCBC_STATUS_RESERVED (-32) /*! * @brief Successful status code. @@ -336,7 +336,7 @@ extern "C" { * Functions return #AESCBC_STATUS_SUCCESS if the function was executed * successfully. */ -#define AESCBC_STATUS_SUCCESS (0) +#define AESCBC_STATUS_SUCCESS (0) /*! * @brief Generic error status code. @@ -344,7 +344,7 @@ extern "C" { * Functions return #AESCBC_STATUS_ERROR if the function was not executed * successfully and no more pertinent error code could be returned. */ -#define AESCBC_STATUS_ERROR (-1) +#define AESCBC_STATUS_ERROR (-1) /*! * @brief An error status code returned if the hardware or software resource @@ -361,11 +361,10 @@ extern "C" { */ #define AESCBC_STATUS_CANCELED (-3) - /*! * @brief A handle that is returned from an #AESCBC_open() call. */ -typedef struct AESCBC_Config* AESCBC_Handle; +typedef struct AESCBC_Config* AESCBC_Handle; /*! * @brief The way in which CBC function calls return after performing an @@ -390,20 +389,20 @@ typedef struct AESCBC_Config* AESCBC_Handle; */ typedef enum { - AESCBC_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the - * CBC operation goes on in the background. The registered - * callback function is called after the operation completes. - * The context the callback function is called (task, HWI, SWI) - * is implementation-dependent. - */ - AESCBC_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while the CBC operation goes - * on in the background. CBC operation results are available - * after the function returns. - */ - AESCBC_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while CBC - * operation goes on in the background. CBC operation results - * are available after the function returns. - */ + AESCBC_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * CBC operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AESCBC_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while the CBC operation goes + * on in the background. CBC operation results are available + * after the function returns. + */ + AESCBC_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while CBC + * operation goes on in the background. CBC operation results + * are available after the function returns. + */ } AESCBC_ReturnBehavior; /*! @@ -421,29 +420,29 @@ typedef enum */ typedef struct { - CryptoKey* key; /*!< A previously initialized CryptoKey. */ - const uint8_t* input; /*!< - * - Encryption: The plaintext buffer to be - * encrypted in the CBC operation. - * - Decryption: The ciphertext to be decrypted. - */ - uint8_t* output; /*!< - * - Encryption: The output ciphertext buffer that - * the encrypted plaintext is copied to. - * - Decryption: The plaintext derived from the - * decrypted ciphertext is copied here. - */ - uint8_t* iv; /*!< A buffer containing an IV. IVs must be unique to - * each CBC operation and may not be reused. If - * ivInternallyGenerated is set, the iv will be - * generated by this function call and copied to - * this buffer. - */ - size_t inputLength; /*!< Length of the input and output in bytes. */ - bool ivInternallyGenerated; /*!< When true, the iv buffer passed into #AESCBC_oneStepEncrypt() functions - * will be overwritten with a randomly generated iv. - * Not supported by all implementations. - */ + CryptoKey* key; /*!< A previously initialized CryptoKey. */ + const uint8_t* input; /*!< + * - Encryption: The plaintext buffer to be + * encrypted in the CBC operation. + * - Decryption: The ciphertext to be decrypted. + */ + uint8_t* output; /*!< + * - Encryption: The output ciphertext buffer that + * the encrypted plaintext is copied to. + * - Decryption: The plaintext derived from the + * decrypted ciphertext is copied here. + */ + uint8_t* iv; /*!< A buffer containing an IV. IVs must be unique to + * each CBC operation and may not be reused. If + * ivInternallyGenerated is set, the iv will be + * generated by this function call and copied to + * this buffer. + */ + size_t inputLength; /*!< Length of the input and output in bytes. */ + bool ivInternallyGenerated; /*!< When true, the iv buffer passed into #AESCBC_oneStepEncrypt() functions + * will be overwritten with a randomly generated iv. + * Not supported by all implementations. + */ } AESCBC_Operation; /*! @@ -468,11 +467,11 @@ typedef enum */ typedef struct AESCBC_Config { - /*! Pointer to a driver specific data object */ - void* object; + /*! Pointer to a driver specific data object */ + void* object; - /*! Pointer to a driver specific hardware attributes structure */ - void const* hwAttrs; + /*! Pointer to a driver specific hardware attributes structure */ + void const* hwAttrs; } AESCBC_Config; /*! @@ -490,10 +489,10 @@ typedef struct AESCBC_Config * @param operationType This parameter determines which operation the * callback refers to. */ -typedef void (*AESCBC_CallbackFxn) (AESCBC_Handle handle, - int_fast16_t returnValue, - AESCBC_Operation* operation, - AESCBC_OperationType operationType); +typedef void (*AESCBC_CallbackFxn)(AESCBC_Handle handle, + int_fast16_t returnValue, + AESCBC_Operation* operation, + AESCBC_OperationType operationType); /*! * @brief CBC Parameters @@ -505,14 +504,14 @@ typedef void (*AESCBC_CallbackFxn) (AESCBC_Handle handle, */ typedef struct { - AESCBC_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ - AESCBC_CallbackFxn callbackFxn; /*!< Callback function pointer */ - uint32_t timeout; /*!< Timeout before the driver returns an error in - * ::AESCBC_RETURN_BEHAVIOR_BLOCKING - */ - void* custom; /*!< Custom argument used by driver - * implementation - */ + AESCBC_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + AESCBC_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::AESCBC_RETURN_BEHAVIOR_BLOCKING + */ + void* custom; /*!< Custom argument used by driver + * implementation + */ } AESCBC_Params; /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCCM.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCCM.h index 543e5c2..3aa992c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCCM.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCCM.h @@ -346,7 +346,7 @@ extern "C" { * #define AESCCMXYZ_STATUS_ERROR2 AESCCM_STATUS_RESERVED - 2 * @endcode */ -#define AESCCM_STATUS_RESERVED (-32) +#define AESCCM_STATUS_RESERVED (-32) /*! * @brief Successful status code. @@ -354,7 +354,7 @@ extern "C" { * Functions return AESCCM_STATUS_SUCCESS if the function was executed * successfully. */ -#define AESCCM_STATUS_SUCCESS (0) +#define AESCCM_STATUS_SUCCESS (0) /*! * @brief Generic error status code. @@ -362,7 +362,7 @@ extern "C" { * Functions return AESCCM_STATUS_ERROR if the function was not executed * successfully and no more pertinent error code could be returned. */ -#define AESCCM_STATUS_ERROR (-1) +#define AESCCM_STATUS_ERROR (-1) /*! * @brief An error status code returned if the hardware or software resource @@ -391,7 +391,7 @@ extern "C" { /*! * @brief A handle that is returned from an AESCCM_open() call. */ -typedef struct AESCCM_Config* AESCCM_Handle; +typedef struct AESCCM_Config* AESCCM_Handle; /*! * @brief The way in which CCM function calls return after performing an @@ -416,20 +416,20 @@ typedef struct AESCCM_Config* AESCCM_Handle; */ typedef enum { - AESCCM_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the - * CCM operation goes on in the background. The registered - * callback function is called after the operation completes. - * The context the callback function is called (task, HWI, SWI) - * is implementation-dependent. - */ - AESCCM_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while the CCM operation goes - * on in the background. CCM operation results are available - * after the function returns. - */ - AESCCM_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while CCM - * operation goes on in the background. CCM operation results - * are available after the function returns. - */ + AESCCM_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * CCM operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AESCCM_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while the CCM operation goes + * on in the background. CCM operation results are available + * after the function returns. + */ + AESCCM_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while CCM + * operation goes on in the background. CCM operation results + * are available after the function returns. + */ } AESCCM_ReturnBehavior; /*! @@ -447,54 +447,54 @@ typedef enum */ typedef struct { - CryptoKey* key; /*!< A previously initialized CryptoKey */ - uint8_t* aad; /*!< A buffer of length \c aadLength containing additional - * authentication data to be authenticated/verified but not - * encrypted/decrypted. - */ - uint8_t* input; /*!< - * - Encryption: The plaintext buffer to be encrypted and authenticated - * in the CCM operation. - * - Decryption: The ciphertext to be decrypted and verified. - */ - uint8_t* output; /*!< - * - Encryption: The output ciphertext buffer that the encrypted plaintext - * is copied to. - * - Decryption: The plaintext derived from the decrypted and verified - * ciphertext is copied here. - */ - uint8_t* nonce; /*!< A buffer containing a nonce. Nonces must be unique to - * each CCM operation and may not be reused. If - * nonceInternallyGenerated is set the nonce will be - * generated by this function call and copied to - * this buffer. - */ - uint8_t* mac; /*!< - * - Encryption: The buffer where the message authentication - * code is copied. - * - Decryption: The buffer containing the received message - * authentication code. - */ - size_t aadLength; /*!< Length of \c aad in bytes. Either \c aadLength or - * \c plaintextLength must benon-zero. - * encrypted. - */ - size_t inputLength; /*!< Length of the input and output in bytes. Either \c aadLength or - * \c inputLength must be - * non-zero. - */ - uint8_t nonceLength; /*!< Length of \c nonce in bytes. - * Valid nonce lengths are [7, 8, ... 13]. - */ - uint8_t macLength; /*!< Length of \c mac in bytes. - * Valid MAC lengths are [0, 4, 6, 8, 10, 12, 14, 16]. - * A length of 0 disables authentication and verification. This is - * only permitted when using CCM*. - */ - bool nonceInternallyGenerated; /*!< When true, the nonce buffer passed into the AESCCM_setupEncrypt() - * and AESCCM_oneStepEncrypt() functions will be overwritten with a - * randomly generated nonce. Not supported by all implementations. - */ + CryptoKey* key; /*!< A previously initialized CryptoKey */ + uint8_t* aad; /*!< A buffer of length \c aadLength containing additional + * authentication data to be authenticated/verified but not + * encrypted/decrypted. + */ + uint8_t* input; /*!< + * - Encryption: The plaintext buffer to be encrypted and authenticated + * in the CCM operation. + * - Decryption: The ciphertext to be decrypted and verified. + */ + uint8_t* output; /*!< + * - Encryption: The output ciphertext buffer that the encrypted plaintext + * is copied to. + * - Decryption: The plaintext derived from the decrypted and verified + * ciphertext is copied here. + */ + uint8_t* nonce; /*!< A buffer containing a nonce. Nonces must be unique to + * each CCM operation and may not be reused. If + * nonceInternallyGenerated is set the nonce will be + * generated by this function call and copied to + * this buffer. + */ + uint8_t* mac; /*!< + * - Encryption: The buffer where the message authentication + * code is copied. + * - Decryption: The buffer containing the received message + * authentication code. + */ + size_t aadLength; /*!< Length of \c aad in bytes. Either \c aadLength or + * \c plaintextLength must benon-zero. + * encrypted. + */ + size_t inputLength; /*!< Length of the input and output in bytes. Either \c aadLength or + * \c inputLength must be + * non-zero. + */ + uint8_t nonceLength; /*!< Length of \c nonce in bytes. + * Valid nonce lengths are [7, 8, ... 13]. + */ + uint8_t macLength; /*!< Length of \c mac in bytes. + * Valid MAC lengths are [0, 4, 6, 8, 10, 12, 14, 16]. + * A length of 0 disables authentication and verification. This is + * only permitted when using CCM*. + */ + bool nonceInternallyGenerated; /*!< When true, the nonce buffer passed into the AESCCM_setupEncrypt() + * and AESCCM_oneStepEncrypt() functions will be overwritten with a + * randomly generated nonce. Not supported by all implementations. + */ } AESCCM_Operation; /*! @@ -519,11 +519,11 @@ typedef enum */ typedef struct AESCCM_Config { - /*! Pointer to a driver specific data object */ - void* object; + /*! Pointer to a driver specific data object */ + void* object; - /*! Pointer to a driver specific hardware attributes structure */ - void const* hwAttrs; + /*! Pointer to a driver specific hardware attributes structure */ + void const* hwAttrs; } AESCCM_Config; /*! @@ -541,10 +541,10 @@ typedef struct AESCCM_Config * @param operationType This parameter determines which operation the * callback refers to. */ -typedef void (*AESCCM_CallbackFxn) (AESCCM_Handle handle, - int_fast16_t returnValue, - AESCCM_Operation* operation, - AESCCM_OperationType operationType); +typedef void (*AESCCM_CallbackFxn)(AESCCM_Handle handle, + int_fast16_t returnValue, + AESCCM_Operation* operation, + AESCCM_OperationType operationType); /*! * @brief CCM Parameters @@ -556,14 +556,14 @@ typedef void (*AESCCM_CallbackFxn) (AESCCM_Handle handle, */ typedef struct { - AESCCM_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ - AESCCM_CallbackFxn callbackFxn; /*!< Callback function pointer */ - uint32_t timeout; /*!< Timeout before the driver returns an error in - * ::AESCCM_RETURN_BEHAVIOR_BLOCKING - */ - void* custom; /*!< Custom argument used by driver - * implementation - */ + AESCCM_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + AESCCM_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::AESCCM_RETURN_BEHAVIOR_BLOCKING + */ + void* custom; /*!< Custom argument used by driver + * implementation + */ } AESCCM_Params; /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCTR.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCTR.h index e16c07d..574a25b 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCTR.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCTR.h @@ -309,7 +309,6 @@ extern "C" { #endif - /*! * Common AESCTR status code reservation offset. * AESCTR driver implementations should offset status codes with @@ -322,7 +321,7 @@ extern "C" { * #define AESCTRXYZ_STATUS_ERROR2 AESCTR_STATUS_RESERVED - 2 * @endcode */ -#define AESCTR_STATUS_RESERVED (-32) +#define AESCTR_STATUS_RESERVED (-32) /*! * @brief Successful status code. @@ -330,7 +329,7 @@ extern "C" { * Functions return #AESCTR_STATUS_SUCCESS if the function was executed * successfully. */ -#define AESCTR_STATUS_SUCCESS (0) +#define AESCTR_STATUS_SUCCESS (0) /*! * @brief Generic error status code. @@ -338,7 +337,7 @@ extern "C" { * Functions return #AESCTR_STATUS_ERROR if the function was not executed * successfully and no more pertinent error code could be returned. */ -#define AESCTR_STATUS_ERROR (-1) +#define AESCTR_STATUS_ERROR (-1) /*! * @brief An error status code returned if the hardware or software resource @@ -355,7 +354,6 @@ extern "C" { */ #define AESCTR_STATUS_CANCELED (-3) - /*! * @brief The way in which CTR function calls return after performing an * encryption or decryption operation. @@ -379,20 +377,20 @@ extern "C" { */ typedef enum { - AESCTR_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the - * CTR operation goes on in the background. The registered - * callback function is called after the operation completes. - * The context the callback function is called (task, HWI, SWI) - * is implementation-dependent. - */ - AESCTR_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while the CTR operation goes - * on in the background. CTR operation results are available - * after the function returns. - */ - AESCTR_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while CTR - * operation goes on in the background. CTR operation results - * are available after the function returns. - */ + AESCTR_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * CTR operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AESCTR_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while the CTR operation goes + * on in the background. CTR operation results are available + * after the function returns. + */ + AESCTR_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while CTR + * operation goes on in the background. CTR operation results + * are available after the function returns. + */ } AESCTR_ReturnBehavior; /*! @@ -413,24 +411,24 @@ typedef enum */ typedef struct { - const CryptoKey* key; /*!< A previously initialized CryptoKey. */ - const uint8_t* input; /*!< - * - Encryption: The plaintext buffer to be - * encrypted in the CTR operation. - * - Decryption: The ciphertext to be decrypted. - */ - uint8_t* output; /*!< - * - Encryption: The output ciphertext buffer that - * the encrypted plaintext is copied to. - * - Decryption: The plaintext derived from the - * decrypted ciphertext is copied here. - */ - const uint8_t* initialCounter; /*!< A buffer containing an initial counter. Under - * the same key, each counter value may only be - * used to encrypt or decrypt a single input - * block. - */ - size_t inputLength; /*!< Length of the input and output in bytes. */ + const CryptoKey* key; /*!< A previously initialized CryptoKey. */ + const uint8_t* input; /*!< + * - Encryption: The plaintext buffer to be + * encrypted in the CTR operation. + * - Decryption: The ciphertext to be decrypted. + */ + uint8_t* output; /*!< + * - Encryption: The output ciphertext buffer that + * the encrypted plaintext is copied to. + * - Decryption: The plaintext derived from the + * decrypted ciphertext is copied here. + */ + const uint8_t* initialCounter; /*!< A buffer containing an initial counter. Under + * the same key, each counter value may only be + * used to encrypt or decrypt a single input + * block. + */ + size_t inputLength; /*!< Length of the input and output in bytes. */ } AESCTR_Operation; /*! @@ -455,11 +453,11 @@ typedef enum */ typedef struct AESCTR_Config { - /*! Pointer to a driver specific data object */ - void* object; + /*! Pointer to a driver specific data object */ + void* object; - /*! Pointer to a driver specific hardware attributes structure */ - void const* hwAttrs; + /*! Pointer to a driver specific hardware attributes structure */ + void const* hwAttrs; } AESCTR_Config; /*! @@ -482,10 +480,10 @@ typedef AESCTR_Config* AESCTR_Handle; * @param operationType This parameter determines which operation the * callback refers to. */ -typedef void (*AESCTR_CallbackFxn) (AESCTR_Handle handle, - int_fast16_t returnValue, - AESCTR_Operation* operation, - AESCTR_OperationType operationType); +typedef void (*AESCTR_CallbackFxn)(AESCTR_Handle handle, + int_fast16_t returnValue, + AESCTR_Operation* operation, + AESCTR_OperationType operationType); /*! * @brief CTR Parameters @@ -497,14 +495,14 @@ typedef void (*AESCTR_CallbackFxn) (AESCTR_Handle handle, */ typedef struct { - AESCTR_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ - AESCTR_CallbackFxn callbackFxn; /*!< Callback function pointer */ - uint32_t timeout; /*!< Timeout before the driver returns an error in - * ::AESCTR_RETURN_BEHAVIOR_BLOCKING - */ - void* custom; /*!< Custom argument used by driver - * implementation - */ + AESCTR_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + AESCTR_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::AESCTR_RETURN_BEHAVIOR_BLOCKING + */ + void* custom; /*!< Custom argument used by driver + * implementation + */ } AESCTR_Params; /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCTRDRBG.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCTRDRBG.h index c276f13..f74beef 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCTRDRBG.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESCTRDRBG.h @@ -246,7 +246,6 @@ extern "C" { #endif - /*! * Common AESCTRDRBG status code reservation offset. * AESCTRDRBG driver implementations should offset status codes with @@ -259,7 +258,7 @@ extern "C" { * #define AESCTRDRBGXYZ_STATUS_ERROR2 AESCTRDRBG_STATUS_RESERVED - 2 * @endcode */ -#define AESCTRDRBG_STATUS_RESERVED (-32) +#define AESCTRDRBG_STATUS_RESERVED (-32) /*! * @brief Successful status code. @@ -267,7 +266,7 @@ extern "C" { * Functions return #AESCTRDRBG_STATUS_SUCCESS if the function was executed * successfully. */ -#define AESCTRDRBG_STATUS_SUCCESS (0) +#define AESCTRDRBG_STATUS_SUCCESS (0) /*! * @brief Generic error status code. @@ -275,7 +274,7 @@ extern "C" { * Functions return #AESCTRDRBG_STATUS_ERROR if the function was not executed * successfully and no more pertinent error code could be returned. */ -#define AESCTRDRBG_STATUS_ERROR (-1) +#define AESCTRDRBG_STATUS_ERROR (-1) /*! * @brief An error status code returned if the hardware or software resource @@ -349,7 +348,7 @@ typedef enum AESCTRDRBG_ReturnBehavior_ * operation goes on in the background. AESCTRDRBG operation results * are available after the function returns. */ - AESCTRDRBG_RETURN_BEHAVIOR_POLLING = AESCTR_RETURN_BEHAVIOR_POLLING, + AESCTRDRBG_RETURN_BEHAVIOR_POLLING = AESCTR_RETURN_BEHAVIOR_POLLING, } AESCTRDRBG_ReturnBehavior; /*! @@ -365,11 +364,11 @@ typedef enum AESCTRDRBG_ReturnBehavior_ */ typedef struct { - /*! Pointer to a driver specific data object */ - void* object; + /*! Pointer to a driver specific data object */ + void* object; - /*! Pointer to a driver specific hardware attributes structure */ - void const* hwAttrs; + /*! Pointer to a driver specific hardware attributes structure */ + void const* hwAttrs; } AESCTRDRBG_Config; /*! @@ -387,36 +386,36 @@ typedef AESCTRDRBG_Config* AESCTRDRBG_Handle; */ typedef struct { - AESCTRDRBG_AES_KEY_LENGTH keyLength; /*!< Length of the internal AES key - * of the driver instance. - */ - uint32_t reseedInterval; /*!< Number of random number generation - * requests before the application is - * required to reseed the driver. - */ - const void* seed; /*!< Entropy used to seed the internal - * state of the driver. Must be one of - * #AESCTRDRBG_SEED_LENGTH long depending - * on \c keyLength. - */ - const void* personalizationData; /*!< Optional non-secret personalization - * data to mix into the driver's internal - * state. - */ - size_t personalizationDataLength; /*!< Length of the optional - * \c personalizationData. Must satisfy - * 0 <= \c personalizationDataLength <= seed length. - */ - AESCTRDRBG_ReturnBehavior returnBehavior; /*!< Return behavior of the driver instance. - * #AESCTRDRBG_RETURN_BEHAVIOR_POLLING is - * strongly recommended unless requests - * for > 500 bytes with AES-256 or - * 1250 bytes for AES-128 will be common - * usecases for this driver instance. - */ - void* custom; /*!< Custom argument used by driver - * implementation - */ + AESCTRDRBG_AES_KEY_LENGTH keyLength; /*!< Length of the internal AES key + * of the driver instance. + */ + uint32_t reseedInterval; /*!< Number of random number generation + * requests before the application is + * required to reseed the driver. + */ + const void* seed; /*!< Entropy used to seed the internal + * state of the driver. Must be one of + * #AESCTRDRBG_SEED_LENGTH long depending + * on \c keyLength. + */ + const void* personalizationData; /*!< Optional non-secret personalization + * data to mix into the driver's internal + * state. + */ + size_t personalizationDataLength; /*!< Length of the optional + * \c personalizationData. Must satisfy + * 0 <= \c personalizationDataLength <= seed length. + */ + AESCTRDRBG_ReturnBehavior returnBehavior; /*!< Return behavior of the driver instance. + * #AESCTRDRBG_RETURN_BEHAVIOR_POLLING is + * strongly recommended unless requests + * for > 500 bytes with AES-256 or + * 1250 bytes for AES-128 will be common + * usecases for this driver instance. + */ + void* custom; /*!< Custom argument used by driver + * implementation + */ } AESCTRDRBG_Params; /*! @@ -512,8 +511,6 @@ int_fast16_t AESCTRDRBG_reseed(AESCTRDRBG_Handle handle, const void* additionalData, size_t additionalDataLength); - - #ifdef __cplusplus } #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESECB.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESECB.h index bf7c700..d2b6950 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESECB.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESECB.h @@ -271,7 +271,7 @@ extern "C" { * #define AESECBXYZ_STATUS_ERROR2 AESECB_STATUS_RESERVED - 2 * @endcode */ -#define AESECB_STATUS_RESERVED (-32) +#define AESECB_STATUS_RESERVED (-32) /*! * @brief Successful status code. @@ -279,7 +279,7 @@ extern "C" { * Functions return AESECB_STATUS_SUCCESS if the function was executed * successfully. */ -#define AESECB_STATUS_SUCCESS (0) +#define AESECB_STATUS_SUCCESS (0) /*! * @brief Generic error status code. @@ -287,7 +287,7 @@ extern "C" { * Functions return AESECB_STATUS_ERROR if the function was not executed * successfully and no more pertinent error code could be returned. */ -#define AESECB_STATUS_ERROR (-1) +#define AESECB_STATUS_ERROR (-1) /*! * @brief An error status code returned if the hardware or software resource @@ -307,7 +307,7 @@ extern "C" { /*! * @brief A handle that is returned from an AESECB_open() call. */ -typedef struct AESECB_Config* AESECB_Handle; +typedef struct AESECB_Config* AESECB_Handle; /*! * @brief The way in which ECB function calls return after performing an @@ -332,20 +332,20 @@ typedef struct AESECB_Config* AESECB_Handle; */ typedef enum { - AESECB_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the - * ECB operation goes on in the background. The registered - * callback function is called after the operation completes. - * The context the callback function is called (task, HWI, SWI) - * is implementation-dependent. - */ - AESECB_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while ECB operation goes - * on in the background. ECB operation results are available - * after the function returns. - */ - AESECB_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while ECB - * operation goes on in the background. ECB operation results - * are available after the function returns. - */ + AESECB_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * ECB operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AESECB_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while ECB operation goes + * on in the background. ECB operation results are available + * after the function returns. + */ + AESECB_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while ECB + * operation goes on in the background. ECB operation results + * are available after the function returns. + */ } AESECB_ReturnBehavior; /*! @@ -363,21 +363,21 @@ typedef enum */ typedef struct { - CryptoKey* key; /*!< A previously initialized CryptoKey */ - uint8_t* input; /*!< - * - Encryption: The plaintext buffer to be encrypted - * in the ECB operation. - * - Decryption: The ciphertext to be decrypted. - */ - uint8_t* output; /*!< - * - Encryption: The output ciphertext buffer that the encrypted plaintext - * is copied to. - * - Decryption: The plaintext derived from the decrypted - * ciphertext is copied here. - */ - size_t inputLength; /*!< Length of the input and output in bytes. Must be a multiple of the - * AES block size (16 bytes) - */ + CryptoKey* key; /*!< A previously initialized CryptoKey */ + uint8_t* input; /*!< + * - Encryption: The plaintext buffer to be encrypted + * in the ECB operation. + * - Decryption: The ciphertext to be decrypted. + */ + uint8_t* output; /*!< + * - Encryption: The output ciphertext buffer that the encrypted plaintext + * is copied to. + * - Decryption: The plaintext derived from the decrypted + * ciphertext is copied here. + */ + size_t inputLength; /*!< Length of the input and output in bytes. Must be a multiple of the + * AES block size (16 bytes) + */ } AESECB_Operation; /*! @@ -402,11 +402,11 @@ typedef enum */ typedef struct AESECB_Config { - /*! Pointer to a driver specific data object */ - void* object; + /*! Pointer to a driver specific data object */ + void* object; - /*! Pointer to a driver specific hardware attributes structure */ - void const* hwAttrs; + /*! Pointer to a driver specific hardware attributes structure */ + void const* hwAttrs; } AESECB_Config; /*! @@ -424,10 +424,10 @@ typedef struct AESECB_Config * @param operationType This parameter determines which operation the * callback refers to. */ -typedef void (*AESECB_CallbackFxn) (AESECB_Handle handle, - int_fast16_t returnValue, - AESECB_Operation* operation, - AESECB_OperationType operationType); +typedef void (*AESECB_CallbackFxn)(AESECB_Handle handle, + int_fast16_t returnValue, + AESECB_Operation* operation, + AESECB_OperationType operationType); /*! * @brief ECB Parameters @@ -439,14 +439,14 @@ typedef void (*AESECB_CallbackFxn) (AESECB_Handle handle, */ typedef struct { - AESECB_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ - AESECB_CallbackFxn callbackFxn; /*!< Callback function pointer */ - uint32_t timeout; /*!< Timeout before the driver returns an error in - * ::AESECB_RETURN_BEHAVIOR_BLOCKING - */ - void* custom; /*!< Custom argument used by driver - * implementation - */ + AESECB_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + AESECB_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::AESECB_RETURN_BEHAVIOR_BLOCKING + */ + void* custom; /*!< Custom argument used by driver + * implementation + */ } AESECB_Params; /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESGCM.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESGCM.h index 5e82902..8129f2c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESGCM.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/AESGCM.h @@ -328,7 +328,7 @@ extern "C" { * #define AESGCMXYZ_STATUS_ERROR2 AESGCM_STATUS_RESERVED - 2 * @endcode */ -#define AESGCM_STATUS_RESERVED (-32) +#define AESGCM_STATUS_RESERVED (-32) /*! * @brief Successful status code. @@ -336,7 +336,7 @@ extern "C" { * Functions return AESGCM_STATUS_SUCCESS if the function was executed * successfully. */ -#define AESGCM_STATUS_SUCCESS (0) +#define AESGCM_STATUS_SUCCESS (0) /*! * @brief Generic error status code. @@ -344,7 +344,7 @@ extern "C" { * Functions return AESGCM_STATUS_ERROR if the function was not executed * successfully and no more pertinent error code could be returned. */ -#define AESGCM_STATUS_ERROR (-1) +#define AESGCM_STATUS_ERROR (-1) /*! * @brief An error status code returned if the hardware or software resource @@ -373,7 +373,7 @@ extern "C" { /*! * @brief A handle that is returned from an AESGCM_open() call. */ -typedef struct AESGCM_Config* AESGCM_Handle; +typedef struct AESGCM_Config* AESGCM_Handle; /*! * @brief The way in which GCM function calls return after performing an @@ -398,20 +398,20 @@ typedef struct AESGCM_Config* AESGCM_Handle; */ typedef enum { - AESGCM_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the - * GCM operation goes on in the background. The registered - * callback function is called after the operation completes. - * The context the callback function is called (task, HWI, SWI) - * is implementation-dependent. - */ - AESGCM_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while the GCM operation goes - * on in the background. GCM operation results are available - * after the function returns. - */ - AESGCM_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while GCM - * operation goes on in the background. GCM operation results - * are available after the function returns. - */ + AESGCM_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * GCM operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + AESGCM_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while the GCM operation goes + * on in the background. GCM operation results are available + * after the function returns. + */ + AESGCM_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while GCM + * operation goes on in the background. GCM operation results + * are available after the function returns. + */ } AESGCM_ReturnBehavior; /*! @@ -429,52 +429,52 @@ typedef enum */ typedef struct { - CryptoKey* key; /*!< A previously initialized CryptoKey */ - uint8_t* aad; /*!< A buffer of length \c aadLength containing additional - * authentication data to be authenticated/verified but not - * encrypted/decrypted. - */ - uint8_t* input; /*!< - * - Encryption: The plaintext buffer to be encrypted and authenticated - * in the GCM operation. - * - Decryption: The ciphertext to be decrypted and verified. - */ - uint8_t* output; /*!< - * - Encryption: The output ciphertext buffer that the encrypted plaintext - * is copied to. - * - Decryption: The plaintext derived from the decrypted and verified - * ciphertext is copied here. - */ - uint8_t* iv; /*!< A buffer containing an IV. IVs must be unique to - * each GCM operation and may not be reused. If - * ivInternallyGenerated is set, the IV will be - * generated by this function call and copied to - * this buffer. - */ - uint8_t* mac; /*!< - * - Encryption: The buffer where the message authentication - * code is copied. - * - Decryption: The buffer containing the received message - * authentication code. - */ - size_t aadLength; /*!< Length of \c aad in bytes. Either \c aadLength or - * \c plaintextLength must benon-zero. - * encrypted. - */ - size_t inputLength; /*!< Length of the input and output in bytes. Either \c aadLength or - * \c inputLength must be - * non-zero. - */ - uint8_t ivLength; /*!< Length of \c IV in bytes. - * The only currently supported IV length is 12 bytes. - */ - uint8_t macLength; /*!< Length of \c mac in bytes. - * Valid MAC lengths are [4, 8, 12, 13, 14, 15, 16]. - */ - bool ivInternallyGenerated; /*!< When true, the IV buffer passed into the AESGCM_setupEncrypt() - * and AESGCM_oneStepEncrypt() functions will be overwritten with a - * randomly generated IV. Not supported by all implementations. - */ + CryptoKey* key; /*!< A previously initialized CryptoKey */ + uint8_t* aad; /*!< A buffer of length \c aadLength containing additional + * authentication data to be authenticated/verified but not + * encrypted/decrypted. + */ + uint8_t* input; /*!< + * - Encryption: The plaintext buffer to be encrypted and authenticated + * in the GCM operation. + * - Decryption: The ciphertext to be decrypted and verified. + */ + uint8_t* output; /*!< + * - Encryption: The output ciphertext buffer that the encrypted plaintext + * is copied to. + * - Decryption: The plaintext derived from the decrypted and verified + * ciphertext is copied here. + */ + uint8_t* iv; /*!< A buffer containing an IV. IVs must be unique to + * each GCM operation and may not be reused. If + * ivInternallyGenerated is set, the IV will be + * generated by this function call and copied to + * this buffer. + */ + uint8_t* mac; /*!< + * - Encryption: The buffer where the message authentication + * code is copied. + * - Decryption: The buffer containing the received message + * authentication code. + */ + size_t aadLength; /*!< Length of \c aad in bytes. Either \c aadLength or + * \c plaintextLength must benon-zero. + * encrypted. + */ + size_t inputLength; /*!< Length of the input and output in bytes. Either \c aadLength or + * \c inputLength must be + * non-zero. + */ + uint8_t ivLength; /*!< Length of \c IV in bytes. + * The only currently supported IV length is 12 bytes. + */ + uint8_t macLength; /*!< Length of \c mac in bytes. + * Valid MAC lengths are [4, 8, 12, 13, 14, 15, 16]. + */ + bool ivInternallyGenerated; /*!< When true, the IV buffer passed into the AESGCM_setupEncrypt() + * and AESGCM_oneStepEncrypt() functions will be overwritten with a + * randomly generated IV. Not supported by all implementations. + */ } AESGCM_Operation; /*! @@ -499,11 +499,11 @@ typedef enum */ typedef struct AESGCM_Config { - /*! Pointer to a driver specific data object */ - void* object; + /*! Pointer to a driver specific data object */ + void* object; - /*! Pointer to a driver specific hardware attributes structure */ - void const* hwAttrs; + /*! Pointer to a driver specific hardware attributes structure */ + void const* hwAttrs; } AESGCM_Config; /*! @@ -521,10 +521,10 @@ typedef struct AESGCM_Config * @param operationType This parameter determines which operation the * callback refers to. */ -typedef void (*AESGCM_CallbackFxn) (AESGCM_Handle handle, - int_fast16_t returnValue, - AESGCM_Operation* operation, - AESGCM_OperationType operationType); +typedef void (*AESGCM_CallbackFxn)(AESGCM_Handle handle, + int_fast16_t returnValue, + AESGCM_Operation* operation, + AESGCM_OperationType operationType); /*! * @brief GCM Parameters @@ -536,14 +536,14 @@ typedef void (*AESGCM_CallbackFxn) (AESGCM_Handle handle, */ typedef struct { - AESGCM_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ - AESGCM_CallbackFxn callbackFxn; /*!< Callback function pointer */ - uint32_t timeout; /*!< Timeout before the driver returns an error in - * ::AESGCM_RETURN_BEHAVIOR_BLOCKING - */ - void* custom; /*!< Custom argument used by driver - * implementation - */ + AESGCM_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + AESGCM_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::AESGCM_RETURN_BEHAVIOR_BLOCKING + */ + void* custom; /*!< Custom argument used by driver + * implementation + */ } AESGCM_Params; /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECDH.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECDH.h index 28571e8..355e4ec 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECDH.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECDH.h @@ -297,7 +297,6 @@ * */ - #ifndef ti_drivers_ECDH__include #define ti_drivers_ECDH__include @@ -324,7 +323,7 @@ extern "C" { * #define ECCXYZ_STATUS_ERROR2 ECDH_STATUS_RESERVED - 2 * @endcode */ -#define ECDH_STATUS_RESERVED (-32) +#define ECDH_STATUS_RESERVED (-32) /*! * @brief Successful status code. @@ -332,7 +331,7 @@ extern "C" { * Functions return ECDH_STATUS_SUCCESS if the function was executed * successfully. */ -#define ECDH_STATUS_SUCCESS (0) +#define ECDH_STATUS_SUCCESS (0) /*! * @brief Generic error status code. @@ -340,7 +339,7 @@ extern "C" { * Functions return ECDH_STATUS_ERROR if the function was not executed * successfully. */ -#define ECDH_STATUS_ERROR (-1) +#define ECDH_STATUS_ERROR (-1) /*! * @brief An error status code returned if the hardware or software resource @@ -401,7 +400,7 @@ extern "C" { /*! * @brief A handle that is returned from an ECDH_open() call. */ -typedef struct ECDH_Config* ECDH_Handle; +typedef struct ECDH_Config* ECDH_Handle; /*! * @brief The way in which ECC function calls return after performing an @@ -426,23 +425,22 @@ typedef struct ECDH_Config* ECDH_Handle; */ typedef enum { - ECDH_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the - * ECC operation goes on in the background. The registered - * callback function is called after the operation completes. - * The context the callback function is called (task, HWI, SWI) - * is implementation-dependent. - */ - ECDH_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while ECC operation goes - * on in the background. ECC operation results are available - * after the function returns. - */ - ECDH_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while ECC - * operation goes on in the background. ECC operation results - * are available after the function returns. - */ + ECDH_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * ECC operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + ECDH_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while ECC operation goes + * on in the background. ECC operation results are available + * after the function returns. + */ + ECDH_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while ECC + * operation goes on in the background. ECC operation results + * are available after the function returns. + */ } ECDH_ReturnBehavior; - /*! * @brief ECC Global configuration * @@ -456,11 +454,11 @@ typedef enum */ typedef struct ECDH_Config { - /*! Pointer to a driver specific data object */ - void* object; + /*! Pointer to a driver specific data object */ + void* object; - /*! Pointer to a driver specific hardware attributes structure */ - void const* hwAttrs; + /*! Pointer to a driver specific hardware attributes structure */ + void const* hwAttrs; } ECDH_Config; /*! @@ -468,13 +466,13 @@ typedef struct ECDH_Config */ typedef struct { - const ECCParams_CurveParams* curve; /*!< A pointer to the elliptic curve parameters for myPrivateKey */ - const CryptoKey* myPrivateKey; /*!< A pointer to the private ECC key from which the new public - * key will be generated. (maybe your static key) - */ - CryptoKey* myPublicKey; /*!< A pointer to a public ECC key which has been initialized blank. - * Newly generated key will be placed in this location. - */ + const ECCParams_CurveParams* curve; /*!< A pointer to the elliptic curve parameters for myPrivateKey */ + const CryptoKey* myPrivateKey; /*!< A pointer to the private ECC key from which the new public + * key will be generated. (maybe your static key) + */ + CryptoKey* myPublicKey; /*!< A pointer to a public ECC key which has been initialized blank. + * Newly generated key will be placed in this location. + */ } ECDH_OperationGeneratePublicKey; /*! @@ -482,18 +480,18 @@ typedef struct */ typedef struct { - const ECCParams_CurveParams* curve; /*!< A pointer to the elliptic curve parameters for myPrivateKey. - * If ECDH_generateKey() was used, this should be the same private key. - */ - const CryptoKey* myPrivateKey; /*!< A pointer to the private ECC key which will be used in to - * compute the shared secret. - */ - const CryptoKey* theirPublicKey; /*!< A pointer to the public key of the party with whom the - * shared secret will be generated. - */ - CryptoKey* sharedSecret; /*!< A pointer to a CryptoKey which has been initialized blank. - * The shared secret will be placed here. - */ + const ECCParams_CurveParams* curve; /*!< A pointer to the elliptic curve parameters for myPrivateKey. + * If ECDH_generateKey() was used, this should be the same private key. + */ + const CryptoKey* myPrivateKey; /*!< A pointer to the private ECC key which will be used in to + * compute the shared secret. + */ + const CryptoKey* theirPublicKey; /*!< A pointer to the public key of the party with whom the + * shared secret will be generated. + */ + CryptoKey* sharedSecret; /*!< A pointer to a CryptoKey which has been initialized blank. + * The shared secret will be placed here. + */ } ECDH_OperationComputeSharedSecret; /*! @@ -501,8 +499,8 @@ typedef struct */ typedef union { - ECDH_OperationGeneratePublicKey* generatePublicKey; /*!< A pointer to an ECDH_OperationGeneratePublicKey struct */ - ECDH_OperationComputeSharedSecret* computeSharedSecret; /*!< A pointer to an ECDH_OperationGeneratePublicKey struct */ + ECDH_OperationGeneratePublicKey* generatePublicKey; /*!< A pointer to an ECDH_OperationGeneratePublicKey struct */ + ECDH_OperationComputeSharedSecret* computeSharedSecret; /*!< A pointer to an ECDH_OperationGeneratePublicKey struct */ } ECDH_Operation; /*! @@ -532,10 +530,10 @@ typedef enum * @param operationType This parameter determined which operation the * callback refers to and which type to access through /c operation. */ -typedef void (*ECDH_CallbackFxn) (ECDH_Handle handle, - int_fast16_t returnStatus, - ECDH_Operation operation, - ECDH_OperationType operationType); +typedef void (*ECDH_CallbackFxn)(ECDH_Handle handle, + int_fast16_t returnStatus, + ECDH_Operation operation, + ECDH_OperationType operationType); /*! * @brief ECC Parameters @@ -547,12 +545,12 @@ typedef void (*ECDH_CallbackFxn) (ECDH_Handle handle, */ typedef struct { - ECDH_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ - ECDH_CallbackFxn callbackFxn; /*!< Callback function pointer */ - uint32_t timeout; /*!< Timeout of the operation */ - void* custom; /*!< Custom argument used by driver - * implementation - */ + ECDH_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + ECDH_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout of the operation */ + void* custom; /*!< Custom argument used by driver + * implementation + */ } ECDH_Params; /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECDSA.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECDSA.h index eed1f9b..3372e31 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECDSA.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECDSA.h @@ -336,7 +336,6 @@ * */ - #ifndef ti_drivers_ECDSA__include #define ti_drivers_ECDSA__include @@ -363,7 +362,7 @@ extern "C" { * #define ECDSAXYZ_STATUS_ERROR2 ECDSA_STATUS_RESERVED - 2 * @endcode */ -#define ECDSA_STATUS_RESERVED (-32) +#define ECDSA_STATUS_RESERVED (-32) /*! * @brief Successful status code. @@ -371,7 +370,7 @@ extern "C" { * Functions return ECDSA_STATUS_SUCCESS if the function was executed * successfully. */ -#define ECDSA_STATUS_SUCCESS (0) +#define ECDSA_STATUS_SUCCESS (0) /*! * @brief Generic error status code. @@ -379,7 +378,7 @@ extern "C" { * Functions return ECDSA_STATUS_ERROR if the function was not executed * successfully. */ -#define ECDSA_STATUS_ERROR (-1) +#define ECDSA_STATUS_ERROR (-1) /*! * @brief An error status code returned if the hardware or software resource @@ -472,20 +471,20 @@ typedef struct ECDSA_Config* ECDSA_Handle; */ typedef enum { - ECDSA_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the - * ECDSA operation goes on in the background. The registered - * callback function is called after the operation completes. - * The context the callback function is called (task, HWI, SWI) - * is implementation-dependent. - */ - ECDSA_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while ECDSA operation goes - * on in the background. ECDSA operation results are available - * after the function returns. - */ - ECDSA_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while ECDSA - * operation goes on in the background. ECDSA operation results - * are available after the function returns. - */ + ECDSA_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * ECDSA operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + ECDSA_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while ECDSA operation goes + * on in the background. ECDSA operation results are available + * after the function returns. + */ + ECDSA_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while ECDSA + * operation goes on in the background. ECDSA operation results + * are available after the function returns. + */ } ECDSA_ReturnBehavior; /*! @@ -501,11 +500,11 @@ typedef enum */ typedef struct ECDSA_Config { - /*! Pointer to a driver specific data object */ - void* object; + /*! Pointer to a driver specific data object */ + void* object; - /*! Pointer to a driver specific hardware attributes structure */ - void const* hwAttrs; + /*! Pointer to a driver specific hardware attributes structure */ + void const* hwAttrs; } ECDSA_Config; /*! @@ -513,29 +512,29 @@ typedef struct ECDSA_Config */ typedef struct { - const ECCParams_CurveParams* curve; /*!< A pointer to the elliptic curve parameters */ - const CryptoKey* myPrivateKey; /*!< A pointer to the private ECC key that will - * sign the hash of the message - */ - const CryptoKey* pmsn; /*!< A pointer to a per message secret number (PMSN). - * The number must be provided by the - * application and be (0 < PMSN < curve order). - * Must be of the same length as - * other params of the curve used. - */ - const uint8_t* hash; /*!< A pointer to the hash of the message. - * Must be the same length as the other curve parameters. - */ - uint8_t* r; /*!< A pointer to the buffer the r component of - * the signature will be written to. - * Must be of the same length as other - * params of the curve used. - */ - uint8_t* s; /*!< A pointer to the buffer the s component of - * the signature will be written to. - * Must be of the same length as other - * params of the curve used. - */ + const ECCParams_CurveParams* curve; /*!< A pointer to the elliptic curve parameters */ + const CryptoKey* myPrivateKey; /*!< A pointer to the private ECC key that will + * sign the hash of the message + */ + const CryptoKey* pmsn; /*!< A pointer to a per message secret number (PMSN). + * The number must be provided by the + * application and be (0 < PMSN < curve order). + * Must be of the same length as + * other params of the curve used. + */ + const uint8_t* hash; /*!< A pointer to the hash of the message. + * Must be the same length as the other curve parameters. + */ + uint8_t* r; /*!< A pointer to the buffer the r component of + * the signature will be written to. + * Must be of the same length as other + * params of the curve used. + */ + uint8_t* s; /*!< A pointer to the buffer the s component of + * the signature will be written to. + * Must be of the same length as other + * params of the curve used. + */ } ECDSA_OperationSign; /*! @@ -543,21 +542,21 @@ typedef struct */ typedef struct { - const ECCParams_CurveParams* curve; /*!< A pointer to the elliptic curve parameters */ - const CryptoKey* theirPublicKey; /*!< A pointer to the public key of the party - * that signed the hash of the message - */ - const uint8_t* hash; /*!< A pointer to the hash of the message. - * Must be the same length as the other curve parameters. - */ - const uint8_t* r; /*!< A pointer to the r component of the received - * signature. Must be of the same length - * as other params of the curve used. - */ - const uint8_t* s; /*!< A pointer to the s component of the received - * signature. Must be of the same length - * as other params of the curve used. - */ + const ECCParams_CurveParams* curve; /*!< A pointer to the elliptic curve parameters */ + const CryptoKey* theirPublicKey; /*!< A pointer to the public key of the party + * that signed the hash of the message + */ + const uint8_t* hash; /*!< A pointer to the hash of the message. + * Must be the same length as the other curve parameters. + */ + const uint8_t* r; /*!< A pointer to the r component of the received + * signature. Must be of the same length + * as other params of the curve used. + */ + const uint8_t* s; /*!< A pointer to the s component of the received + * signature. Must be of the same length + * as other params of the curve used. + */ } ECDSA_OperationVerify; /*! @@ -565,8 +564,8 @@ typedef struct */ typedef union { - ECDSA_OperationSign* sign; /*!< A pointer to an ECDSA_OperationSign struct */ - ECDSA_OperationVerify* verify; /*!< A pointer to an ECDSA_OperationVerify struct */ + ECDSA_OperationSign* sign; /*!< A pointer to an ECDSA_OperationSign struct */ + ECDSA_OperationVerify* verify; /*!< A pointer to an ECDSA_OperationVerify struct */ } ECDSA_Operation; /*! @@ -596,10 +595,10 @@ typedef enum * @param operationType This parameter determined which operation the * callback refers to and which type to access through /c operation. */ -typedef void (*ECDSA_CallbackFxn) (ECDSA_Handle handle, - int_fast16_t returnStatus, - ECDSA_Operation operation, - ECDSA_OperationType operationType); +typedef void (*ECDSA_CallbackFxn)(ECDSA_Handle handle, + int_fast16_t returnStatus, + ECDSA_Operation operation, + ECDSA_OperationType operationType); /*! * @brief ECDSA Parameters @@ -611,14 +610,14 @@ typedef void (*ECDSA_CallbackFxn) (ECDSA_Handle handle, */ typedef struct { - ECDSA_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ - ECDSA_CallbackFxn callbackFxn; /*!< Callback function pointer */ - uint32_t timeout; /*!< Timeout in system ticks before the operation fails - * and returns - */ - void* custom; /*!< Custom argument used by driver - * implementation - */ + ECDSA_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + ECDSA_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout in system ticks before the operation fails + * and returns + */ + void* custom; /*!< Custom argument used by driver + * implementation + */ } ECDSA_Params; /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECJPAKE.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECJPAKE.h index eba5ed6..a17324c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECJPAKE.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ECJPAKE.h @@ -629,7 +629,6 @@ * */ - #ifndef ti_drivers_ECJPAKE__include #define ti_drivers_ECJPAKE__include @@ -656,7 +655,7 @@ extern "C" { * #define ECJPAKEXYZ_STATUS_ERROR2 ECJPAKE_STATUS_RESERVED - 2 * @endcode */ -#define ECJPAKE_STATUS_RESERVED (-32) +#define ECJPAKE_STATUS_RESERVED (-32) /*! * @brief Successful status code. @@ -664,7 +663,7 @@ extern "C" { * Functions return ECJPAKE_STATUS_SUCCESS if the function was executed * successfully. */ -#define ECJPAKE_STATUS_SUCCESS (0) +#define ECJPAKE_STATUS_SUCCESS (0) /*! * @brief Generic error status code. @@ -672,7 +671,7 @@ extern "C" { * Functions return ECJPAKE_STATUS_ERROR if the function was not executed * successfully. */ -#define ECJPAKE_STATUS_ERROR (-1) +#define ECJPAKE_STATUS_ERROR (-1) /*! * @brief An error status code returned if the hardware or software resource @@ -740,7 +739,7 @@ extern "C" { /*! * @brief A handle that is returned from an ECJPAKE_open() call. */ -typedef struct ECJPAKE_Config* ECJPAKE_Handle; +typedef struct ECJPAKE_Config* ECJPAKE_Handle; /*! * @brief The way in which ECJPAKE function calls return after performing an @@ -765,20 +764,20 @@ typedef struct ECJPAKE_Config* ECJPAKE_Handle; */ typedef enum { - ECJPAKE_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the - * ECJPAKE operation goes on in the background. The registered - * callback function is called after the operation completes. - * The context the callback function is called (task, HWI, SWI) - * is implementation-dependent. - */ - ECJPAKE_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while ECJPAKE operation goes - * on in the background. ECJPAKE operation results are available - * after the function returns. - */ - ECJPAKE_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while ECJPAKE - * operation goes on in the background. ECJPAKE operation results - * are available after the function returns. - */ + ECJPAKE_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * ECJPAKE operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + ECJPAKE_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while ECJPAKE operation goes + * on in the background. ECJPAKE operation results are available + * after the function returns. + */ + ECJPAKE_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while ECJPAKE + * operation goes on in the background. ECJPAKE operation results + * are available after the function returns. + */ } ECJPAKE_ReturnBehavior; /*! @@ -794,11 +793,11 @@ typedef enum */ typedef struct ECJPAKE_Config { - /*! Pointer to a driver specific data object */ - void* object; + /*! Pointer to a driver specific data object */ + void* object; - /*! Pointer to a driver specific hardware attributes structure */ - void const* hwAttrs; + /*! Pointer to a driver specific hardware attributes structure */ + void const* hwAttrs; } ECJPAKE_Config; /*! @@ -806,59 +805,59 @@ typedef struct ECJPAKE_Config */ typedef struct { - const ECCParams_CurveParams* curve; /*!< A pointer to the elliptic curve parameters - * used in the operation. - */ - CryptoKey* myPrivateKey1; /*!< A pointer to a private ECC key. Must - * be of the same length as other params - * of the curve used. - */ - CryptoKey* myPrivateKey2; /*!< A pointer to a private ECC key. Must - * be of the same length as other params - * of the curve used. - */ - CryptoKey* myPublicKey1; /*!< A pointer to the blank public key of \c - * myPrivateKey1. The keying material will be - * written to the buffer specified in the - * CryptoKey. - */ - CryptoKey* myPublicKey2; /*!< A pointer to the blank public key of \c - * myPrivateKey2. The keying material will be - * written to the buffer specified in the - * CryptoKey. - */ - CryptoKey* myPrivateV1; /*!< A pointer to a private ECC key used in the - * first Schnorr ZKP. - * Must be of the same length as other params - * of the curve used. The CryptoKey and keying material - * may be deleted or go out of scope after - * generating the ZKP. - */ - CryptoKey* myPrivateV2; /*!< A pointer to a private ECC key used in the - * second Schnorr ZKP. - * Must be of the same length as other params - * of the curve used. The CryptoKey and keying material - * may be deleted or go out of scope after - * generating the ZKP. - */ - CryptoKey* myPublicV1; /*!< A pointer to the blank public key of \c - * myPrivateV1. The keying material will be - * written to the buffer specified in the - * CryptoKey. The CryptoKey and keying material - * may be deleted or go out of scope after - * generating the hash and sending \c myPublicV2 - * to the other party with the rest of the - * parameters. - */ - CryptoKey* myPublicV2; /*!< A pointer to the blank public key of \c - * myPrivateV2. The keying material will be - * written to the buffer specified in the - * CryptoKey. The CryptoKey and keying material - * may be deleted or go out of scope after - * generating the hash and sending \c myPublicV2 - * to the other party with the rest of the - * parameters. - */ + const ECCParams_CurveParams* curve; /*!< A pointer to the elliptic curve parameters + * used in the operation. + */ + CryptoKey* myPrivateKey1; /*!< A pointer to a private ECC key. Must + * be of the same length as other params + * of the curve used. + */ + CryptoKey* myPrivateKey2; /*!< A pointer to a private ECC key. Must + * be of the same length as other params + * of the curve used. + */ + CryptoKey* myPublicKey1; /*!< A pointer to the blank public key of \c + * myPrivateKey1. The keying material will be + * written to the buffer specified in the + * CryptoKey. + */ + CryptoKey* myPublicKey2; /*!< A pointer to the blank public key of \c + * myPrivateKey2. The keying material will be + * written to the buffer specified in the + * CryptoKey. + */ + CryptoKey* myPrivateV1; /*!< A pointer to a private ECC key used in the + * first Schnorr ZKP. + * Must be of the same length as other params + * of the curve used. The CryptoKey and keying material + * may be deleted or go out of scope after + * generating the ZKP. + */ + CryptoKey* myPrivateV2; /*!< A pointer to a private ECC key used in the + * second Schnorr ZKP. + * Must be of the same length as other params + * of the curve used. The CryptoKey and keying material + * may be deleted or go out of scope after + * generating the ZKP. + */ + CryptoKey* myPublicV1; /*!< A pointer to the blank public key of \c + * myPrivateV1. The keying material will be + * written to the buffer specified in the + * CryptoKey. The CryptoKey and keying material + * may be deleted or go out of scope after + * generating the hash and sending \c myPublicV2 + * to the other party with the rest of the + * parameters. + */ + CryptoKey* myPublicV2; /*!< A pointer to the blank public key of \c + * myPrivateV2. The keying material will be + * written to the buffer specified in the + * CryptoKey. The CryptoKey and keying material + * may be deleted or go out of scope after + * generating the hash and sending \c myPublicV2 + * to the other party with the rest of the + * parameters. + */ } ECJPAKE_OperationRoundOneGenerateKeys; /*! @@ -866,25 +865,25 @@ typedef struct */ typedef struct { - const ECCParams_CurveParams* curve; /*!< A pointer to the elliptic curve parameters - * used in the operation. - */ - const CryptoKey* myPrivateKey; /*!< A pointer to a private ECC key to be signed. Must - * be of the same length as other params - * of the curve used. - */ - const CryptoKey* myPrivateV; /*!< A pointer to a private ECC key that will be - * used only to generate a ZKP signature. - * Must be of the same length as other params - * of the curve used. - */ - const uint8_t* hash; /*!< A pointer to the hash of the message. - * Must be of the same length as other params - * of the curve used. - */ - uint8_t* r; /*!< A pointer to where the r component of the - * ZKP will be written to. - */ + const ECCParams_CurveParams* curve; /*!< A pointer to the elliptic curve parameters + * used in the operation. + */ + const CryptoKey* myPrivateKey; /*!< A pointer to a private ECC key to be signed. Must + * be of the same length as other params + * of the curve used. + */ + const CryptoKey* myPrivateV; /*!< A pointer to a private ECC key that will be + * used only to generate a ZKP signature. + * Must be of the same length as other params + * of the curve used. + */ + const uint8_t* hash; /*!< A pointer to the hash of the message. + * Must be of the same length as other params + * of the curve used. + */ + uint8_t* r; /*!< A pointer to where the r component of the + * ZKP will be written to. + */ } ECJPAKE_OperationGenerateZKP; /*! @@ -892,28 +891,28 @@ typedef struct */ typedef struct { - const ECCParams_CurveParams* curve; /*!< A pointer to the elliptic curve parameters - * used in the operation. - */ - const CryptoKey* theirGenerator; /*!< A CryptoKey describing the generator point - * to be used. In the first round, this will - * be the default generator of the curve. - * In the second round, this parameter is - * computed by ECJPAKE_roundTwoGenerateKeys(). - */ - const CryptoKey* theirPublicKey; /*!< A CryptoKey describing the public key - * received from the other party that the - * ZKP to be verified supposedly signed. - */ - const CryptoKey* theirPublicV; /*!< A CryptoKey describing the public V of the - * ZKP. Received from the other party. - */ - const uint8_t* hash; /*!< The hash of the ZKP generated as the - * other party generated it to compute r. - */ - const uint8_t* r; /*!< R component of the ZKP signature. Received - * from the other party. - */ + const ECCParams_CurveParams* curve; /*!< A pointer to the elliptic curve parameters + * used in the operation. + */ + const CryptoKey* theirGenerator; /*!< A CryptoKey describing the generator point + * to be used. In the first round, this will + * be the default generator of the curve. + * In the second round, this parameter is + * computed by ECJPAKE_roundTwoGenerateKeys(). + */ + const CryptoKey* theirPublicKey; /*!< A CryptoKey describing the public key + * received from the other party that the + * ZKP to be verified supposedly signed. + */ + const CryptoKey* theirPublicV; /*!< A CryptoKey describing the public V of the + * ZKP. Received from the other party. + */ + const uint8_t* hash; /*!< The hash of the ZKP generated as the + * other party generated it to compute r. + */ + const uint8_t* r; /*!< R component of the ZKP signature. Received + * from the other party. + */ } ECJPAKE_OperationVerifyZKP; /*! @@ -921,70 +920,70 @@ typedef struct */ typedef struct { - const ECCParams_CurveParams* curve; /*!< A pointer to the elliptic curve parameters - * used in the operation. - */ - const CryptoKey* myPrivateKey2; /*!< A pointer to a private ECC key. Must - * be of the same length as other params - * of the curve used. Generated in round one. - */ - const CryptoKey* myPublicKey1; /*!< A pointer to the public key of - * myPrivateKey1. Generated in round one. - */ - const CryptoKey* myPublicKey2; /*!< A pointer to the second public key. - * Generated in round one. - */ - const CryptoKey* theirPublicKey1; /*!< A CryptoKey describing the first public key - * received from the other party. - */ - const CryptoKey* theirPublicKey2; /*!< A CryptoKey describing the second public key - * received from the other party. - */ - const CryptoKey* preSharedSecret; /*!< A CryptoKey describing the secret shared between - * the two parties prior to starting the scheme. - * This exchange would have happened through some - * offline commissioning scheme most likely. - * The driver expects an integer of the same length - * as the curve parameters of the curve in use as - * keying material even if the original pre-shared - * secret is shorter than this length. - */ - CryptoKey* theirNewGenerator; /*!< A blank CryptoKey describing the generator point - * used by the other party in the second round. - * After it is computed, the keying material will - * be written to the location described in the - * CryptoKey. - */ - CryptoKey* myNewGenerator; /*!< A blank CryptoKey describing the generator point - * used by the application in the second round. - * After it is computed, the keying material will - * be written to the location described in the - * CryptoKey. - */ - CryptoKey* myCombinedPrivateKey; /*!< A pointer to a public ECC key. Must - * be of the same length as other params - * of the curve used. Result of multiplying - * \c myCombinedPrivateKey by \c myNewGenerator. - */ - CryptoKey* myCombinedPublicKey; /*!< A pointer to a public ECC key. Result of multiplying - * \c myCombinedPrivateKey by \c myNewGenerator. - */ - CryptoKey* myPrivateV; /*!< A pointer to a private ECC key used in the - * only second-round Schnorr ZKP. - * Must be of the same length as other params - * of the curve used. The CryptoKey and keying material - * may be deleted or go out of scope after - * generating the ZKP. - */ - CryptoKey* myPublicV; /*!< A pointer to the blank public key of \c - * myPrivateV. The keying material will be - * written to the buffer specified in the - * CryptoKey. The CryptoKey and keying material - * may be deleted or go out of scope after - * generating the hash and sending \c myPublicV2 - * to the other party with the rest of the - * parameters. - */ + const ECCParams_CurveParams* curve; /*!< A pointer to the elliptic curve parameters + * used in the operation. + */ + const CryptoKey* myPrivateKey2; /*!< A pointer to a private ECC key. Must + * be of the same length as other params + * of the curve used. Generated in round one. + */ + const CryptoKey* myPublicKey1; /*!< A pointer to the public key of + * myPrivateKey1. Generated in round one. + */ + const CryptoKey* myPublicKey2; /*!< A pointer to the second public key. + * Generated in round one. + */ + const CryptoKey* theirPublicKey1; /*!< A CryptoKey describing the first public key + * received from the other party. + */ + const CryptoKey* theirPublicKey2; /*!< A CryptoKey describing the second public key + * received from the other party. + */ + const CryptoKey* preSharedSecret; /*!< A CryptoKey describing the secret shared between + * the two parties prior to starting the scheme. + * This exchange would have happened through some + * offline commissioning scheme most likely. + * The driver expects an integer of the same length + * as the curve parameters of the curve in use as + * keying material even if the original pre-shared + * secret is shorter than this length. + */ + CryptoKey* theirNewGenerator; /*!< A blank CryptoKey describing the generator point + * used by the other party in the second round. + * After it is computed, the keying material will + * be written to the location described in the + * CryptoKey. + */ + CryptoKey* myNewGenerator; /*!< A blank CryptoKey describing the generator point + * used by the application in the second round. + * After it is computed, the keying material will + * be written to the location described in the + * CryptoKey. + */ + CryptoKey* myCombinedPrivateKey; /*!< A pointer to a public ECC key. Must + * be of the same length as other params + * of the curve used. Result of multiplying + * \c myCombinedPrivateKey by \c myNewGenerator. + */ + CryptoKey* myCombinedPublicKey; /*!< A pointer to a public ECC key. Result of multiplying + * \c myCombinedPrivateKey by \c myNewGenerator. + */ + CryptoKey* myPrivateV; /*!< A pointer to a private ECC key used in the + * only second-round Schnorr ZKP. + * Must be of the same length as other params + * of the curve used. The CryptoKey and keying material + * may be deleted or go out of scope after + * generating the ZKP. + */ + CryptoKey* myPublicV; /*!< A pointer to the blank public key of \c + * myPrivateV. The keying material will be + * written to the buffer specified in the + * CryptoKey. The CryptoKey and keying material + * may be deleted or go out of scope after + * generating the hash and sending \c myPublicV2 + * to the other party with the rest of the + * parameters. + */ } ECJPAKE_OperationRoundTwoGenerateKeys; /*! @@ -992,41 +991,40 @@ typedef struct */ typedef struct { - const ECCParams_CurveParams* curve; /*!< A pointer to the elliptic curve parameters - * used in the operation. - */ - const CryptoKey* myCombinedPrivateKey; /*!< A pointer to a private ECC key. Must - * be of the same length as other params - * of the curve used. Generated in round one. - */ - const CryptoKey* theirCombinedPublicKey; /*!< A CryptoKey describing the second public key - * received from the other party. - */ - const CryptoKey* theirPublicKey2; /*!< A pointer to a private ECC key. Must - * be of the same length as other params - * of the curve used. Result of multiplying - * \c myPrivateKey2 by \c preSharedSecret. - */ - const CryptoKey* myPrivateKey2; /*!< Combined public key received in the second - * round and verified by the application against - * the second round ZKP signature. - */ - CryptoKey* sharedSecret; /*!< The shared secret that is identical between both - * parties. - */ + const ECCParams_CurveParams* curve; /*!< A pointer to the elliptic curve parameters + * used in the operation. + */ + const CryptoKey* myCombinedPrivateKey; /*!< A pointer to a private ECC key. Must + * be of the same length as other params + * of the curve used. Generated in round one. + */ + const CryptoKey* theirCombinedPublicKey; /*!< A CryptoKey describing the second public key + * received from the other party. + */ + const CryptoKey* theirPublicKey2; /*!< A pointer to a private ECC key. Must + * be of the same length as other params + * of the curve used. Result of multiplying + * \c myPrivateKey2 by \c preSharedSecret. + */ + const CryptoKey* myPrivateKey2; /*!< Combined public key received in the second + * round and verified by the application against + * the second round ZKP signature. + */ + CryptoKey* sharedSecret; /*!< The shared secret that is identical between both + * parties. + */ } ECJPAKE_OperationComputeSharedSecret; - /*! * @brief Union containing pointers to all supported operation structs. */ typedef union { - ECJPAKE_OperationRoundOneGenerateKeys* generateRoundOneKeys; /*!< A pointer to an ECJPAKE_OperationRoundOneGenerateKeys struct */ - ECJPAKE_OperationGenerateZKP* generateZKP; /*!< A pointer to an ECJPAKE_OperationGenerateZKP struct */ - ECJPAKE_OperationVerifyZKP* verifyZKP; /*!< A pointer to an ECJPAKE_OperationVerifyZKP struct */ - ECJPAKE_OperationRoundTwoGenerateKeys* generateRoundTwoKeys; /*!< A pointer to an ECJPAKE_OperationRoundTwoGenerateKeys struct */ - ECJPAKE_OperationComputeSharedSecret* computeSharedSecret; /*!< A pointer to an ECJPAKE_OperationComputeSharedSecret struct */ + ECJPAKE_OperationRoundOneGenerateKeys* generateRoundOneKeys; /*!< A pointer to an ECJPAKE_OperationRoundOneGenerateKeys struct */ + ECJPAKE_OperationGenerateZKP* generateZKP; /*!< A pointer to an ECJPAKE_OperationGenerateZKP struct */ + ECJPAKE_OperationVerifyZKP* verifyZKP; /*!< A pointer to an ECJPAKE_OperationVerifyZKP struct */ + ECJPAKE_OperationRoundTwoGenerateKeys* generateRoundTwoKeys; /*!< A pointer to an ECJPAKE_OperationRoundTwoGenerateKeys struct */ + ECJPAKE_OperationComputeSharedSecret* computeSharedSecret; /*!< A pointer to an ECJPAKE_OperationComputeSharedSecret struct */ } ECJPAKE_Operation; /*! @@ -1059,10 +1057,10 @@ typedef enum * @param operationType This parameter determined which operation the * callback refers to and which type to access through /c operation. */ -typedef void (*ECJPAKE_CallbackFxn) (ECJPAKE_Handle handle, - int_fast16_t returnStatus, - ECJPAKE_Operation operation, - ECJPAKE_OperationType operationType); +typedef void (*ECJPAKE_CallbackFxn)(ECJPAKE_Handle handle, + int_fast16_t returnStatus, + ECJPAKE_Operation operation, + ECJPAKE_OperationType operationType); /*! * @brief ECJPAKE Parameters @@ -1074,14 +1072,14 @@ typedef void (*ECJPAKE_CallbackFxn) (ECJPAKE_Handle handle, */ typedef struct { - ECJPAKE_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ - ECJPAKE_CallbackFxn callbackFxn; /*!< Callback function pointer */ - uint32_t timeout; /*!< Timeout in system ticks before the operation fails - * and returns - */ - void* custom; /*!< Custom argument used by driver - * implementation - */ + ECJPAKE_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + ECJPAKE_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout in system ticks before the operation fails + * and returns + */ + void* custom; /*!< Custom argument used by driver + * implementation + */ } ECJPAKE_Params; /*! @@ -1134,7 +1132,6 @@ void ECJPAKE_OperationVerifyZKP_init(ECJPAKE_OperationVerifyZKP* operation); */ void ECJPAKE_OperationRoundTwoGenerateKeys_init(ECJPAKE_OperationRoundTwoGenerateKeys* operation); - /*! * @brief Function to initialize an ECJPAKE_OperationComputeSharedSecret struct to its defaults * @@ -1251,28 +1248,28 @@ int_fast16_t ECJPAKE_roundOneGenerateKeys(ECJPAKE_Handle handle, ECJPAKE_Operati int_fast16_t ECJPAKE_generateZKP(ECJPAKE_Handle handle, ECJPAKE_OperationGenerateZKP* operation); /*! -* @brief Verifies a Schnorr Zero-Knowledge Proof (ZKP) signature. -* -* This function computes if a received Schnorr ZKP correctly verifies -* a received public key. -* -* @param [in] handle An ECJPAKE handle returned from ECJPAKE_open() -* -* @param [in] operation A pointer to a struct containing the requisite -* parameters to execute the function. -* -* @pre Receive the relevant ZKP signature parameters. Compute the hash. -* If in the second round, compute the generator first by calling -* ECJPAKE_roundTwoGenerateKeys(). -* Call ECJPAKE_OperationVerifyZKP_init() on /c operation. -* -* @retval #ECJPAKE_STATUS_SUCCESS The operation succeeded. -* @retval #ECJPAKE_STATUS_ERROR The operation failed. Signature did not verify correctly. -* @retval #ECJPAKE_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. -* @retval #ECJPAKE_STATUS_CANCELED The operation was canceled. -* @retval #ECJPAKE_STATUS_PUBLIC_KEY_NOT_ON_CURVE The public key of the other party does not lie upon the curve. -* @retval #ECJPAKE_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME A coordinate of the public key of the other party is too large. -*/ + * @brief Verifies a Schnorr Zero-Knowledge Proof (ZKP) signature. + * + * This function computes if a received Schnorr ZKP correctly verifies + * a received public key. + * + * @param [in] handle An ECJPAKE handle returned from ECJPAKE_open() + * + * @param [in] operation A pointer to a struct containing the requisite + * parameters to execute the function. + * + * @pre Receive the relevant ZKP signature parameters. Compute the hash. + * If in the second round, compute the generator first by calling + * ECJPAKE_roundTwoGenerateKeys(). + * Call ECJPAKE_OperationVerifyZKP_init() on /c operation. + * + * @retval #ECJPAKE_STATUS_SUCCESS The operation succeeded. + * @retval #ECJPAKE_STATUS_ERROR The operation failed. Signature did not verify correctly. + * @retval #ECJPAKE_STATUS_RESOURCE_UNAVAILABLE The required hardware resource was not available. Try again later. + * @retval #ECJPAKE_STATUS_CANCELED The operation was canceled. + * @retval #ECJPAKE_STATUS_PUBLIC_KEY_NOT_ON_CURVE The public key of the other party does not lie upon the curve. + * @retval #ECJPAKE_STATUS_PUBLIC_KEY_LARGER_THAN_PRIME A coordinate of the public key of the other party is too large. + */ int_fast16_t ECJPAKE_verifyZKP(ECJPAKE_Handle handle, ECJPAKE_OperationVerifyZKP* operation); /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/GPIO.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/GPIO.h index 486b22c..bd1e730 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/GPIO.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/GPIO.h @@ -303,7 +303,7 @@ extern "C" { * #define GPIOTXYZ_STATUS_ERROR2 GPIO_STATUS_RESERVED - 2 * @endcode */ -#define GPIO_STATUS_RESERVED (-32) +#define GPIO_STATUS_RESERVED (-32) /*! * @brief Successful status code returned by GPI_setConfig(). @@ -311,7 +311,7 @@ extern "C" { * GPI_setConfig() returns GPIO_STATUS_SUCCESS if the API was executed * successfully. */ -#define GPIO_STATUS_SUCCESS (0) +#define GPIO_STATUS_SUCCESS (0) /*! * @brief Generic error status code returned by GPI_setConfig(). @@ -319,7 +319,7 @@ extern "C" { * GPI_setConfig() returns GPIO_STATUS_ERROR if the API was not executed * successfully. */ -#define GPIO_STATUS_ERROR (-1) +#define GPIO_STATUS_ERROR (-1) /** @}*/ /*! @@ -337,17 +337,17 @@ typedef uint32_t GPIO_PinConfig; * @cond NODOC * Internally used configuration bit access macros. */ -#define GPIO_CFG_IO_MASK 0x00ff0000 -#define GPIO_CFG_IO_LSB 16 -#define GPIO_CFG_OUT_TYPE_MASK 0x00060000 -#define GPIO_CFG_OUT_TYPE_LSB 17 -#define GPIO_CFG_IN_TYPE_MASK 0x00060000 -#define GPIO_CFG_IN_TYPE_LSB 17 +#define GPIO_CFG_IO_MASK 0x00ff0000 +#define GPIO_CFG_IO_LSB 16 +#define GPIO_CFG_OUT_TYPE_MASK 0x00060000 +#define GPIO_CFG_OUT_TYPE_LSB 17 +#define GPIO_CFG_IN_TYPE_MASK 0x00060000 +#define GPIO_CFG_IN_TYPE_LSB 17 #define GPIO_CFG_OUT_STRENGTH_MASK 0x00f00000 -#define GPIO_CFG_OUT_STRENGTH_LSB 20 -#define GPIO_CFG_INT_MASK 0x07000000 -#define GPIO_CFG_INT_LSB 24 -#define GPIO_CFG_OUT_BIT 19 +#define GPIO_CFG_OUT_STRENGTH_LSB 20 +#define GPIO_CFG_INT_MASK 0x07000000 +#define GPIO_CFG_INT_LSB 24 +#define GPIO_CFG_OUT_BIT 19 /*! @endcond */ /*! @@ -357,38 +357,38 @@ typedef uint32_t GPIO_PinConfig; /** @name GPIO_PinConfig output pin configuration macros * @{ */ -#define GPIO_CFG_OUTPUT (((uint32_t) 0) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Pin is an output. */ -#define GPIO_CFG_OUT_STD (((uint32_t) 0) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is actively driven high and low */ -#define GPIO_CFG_OUT_OD_NOPULL (((uint32_t) 2) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is Open Drain */ -#define GPIO_CFG_OUT_OD_PU (((uint32_t) 4) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is Open Drain w/ pull up */ -#define GPIO_CFG_OUT_OD_PD (((uint32_t) 6) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is Open Drain w/ pull dn */ +#define GPIO_CFG_OUTPUT (((uint32_t)0) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Pin is an output. */ +#define GPIO_CFG_OUT_STD (((uint32_t)0) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is actively driven high and low */ +#define GPIO_CFG_OUT_OD_NOPULL (((uint32_t)2) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is Open Drain */ +#define GPIO_CFG_OUT_OD_PU (((uint32_t)4) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is Open Drain w/ pull up */ +#define GPIO_CFG_OUT_OD_PD (((uint32_t)6) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is Open Drain w/ pull dn */ -#define GPIO_CFG_OUT_STR_LOW (((uint32_t) 0) << GPIO_CFG_OUT_STRENGTH_LSB) /*!< @hideinitializer Set output pin strength to low */ -#define GPIO_CFG_OUT_STR_MED (((uint32_t) 1) << GPIO_CFG_OUT_STRENGTH_LSB) /*!< @hideinitializer Set output pin strength to medium */ -#define GPIO_CFG_OUT_STR_HIGH (((uint32_t) 2) << GPIO_CFG_OUT_STRENGTH_LSB) /*!< @hideinitializer Set output pin strength to high */ +#define GPIO_CFG_OUT_STR_LOW (((uint32_t)0) << GPIO_CFG_OUT_STRENGTH_LSB) /*!< @hideinitializer Set output pin strength to low */ +#define GPIO_CFG_OUT_STR_MED (((uint32_t)1) << GPIO_CFG_OUT_STRENGTH_LSB) /*!< @hideinitializer Set output pin strength to medium */ +#define GPIO_CFG_OUT_STR_HIGH (((uint32_t)2) << GPIO_CFG_OUT_STRENGTH_LSB) /*!< @hideinitializer Set output pin strength to high */ -#define GPIO_CFG_OUT_HIGH (((uint32_t) 1) << GPIO_CFG_OUT_BIT) /*!< @hideinitializer Set pin's output to 1. */ -#define GPIO_CFG_OUT_LOW (((uint32_t) 0) << GPIO_CFG_OUT_BIT) /*!< @hideinitializer Set pin's output to 0. */ +#define GPIO_CFG_OUT_HIGH (((uint32_t)1) << GPIO_CFG_OUT_BIT) /*!< @hideinitializer Set pin's output to 1. */ +#define GPIO_CFG_OUT_LOW (((uint32_t)0) << GPIO_CFG_OUT_BIT) /*!< @hideinitializer Set pin's output to 0. */ /** @} */ /** @name GPIO_PinConfig input pin configuration macros * @{ */ -#define GPIO_CFG_INPUT (((uint32_t) 1) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Pin is an input. */ -#define GPIO_CFG_IN_NOPULL (((uint32_t) 1) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Input pin with no internal PU/PD */ -#define GPIO_CFG_IN_PU (((uint32_t) 3) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Input pin with internal PU */ -#define GPIO_CFG_IN_PD (((uint32_t) 5) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Input pin with internal PD */ +#define GPIO_CFG_INPUT (((uint32_t)1) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Pin is an input. */ +#define GPIO_CFG_IN_NOPULL (((uint32_t)1) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Input pin with no internal PU/PD */ +#define GPIO_CFG_IN_PU (((uint32_t)3) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Input pin with internal PU */ +#define GPIO_CFG_IN_PD (((uint32_t)5) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Input pin with internal PD */ /** @} */ /** @name GPIO_PinConfig interrupt configuration macros * @{ */ -#define GPIO_CFG_IN_INT_NONE (((uint32_t) 0) << GPIO_CFG_INT_LSB) /*!< @hideinitializer No Interrupt */ -#define GPIO_CFG_IN_INT_FALLING (((uint32_t) 1) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on falling edge */ -#define GPIO_CFG_IN_INT_RISING (((uint32_t) 2) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on rising edge */ -#define GPIO_CFG_IN_INT_BOTH_EDGES (((uint32_t) 3) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on both edges */ -#define GPIO_CFG_IN_INT_LOW (((uint32_t) 4) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on low level */ -#define GPIO_CFG_IN_INT_HIGH (((uint32_t) 5) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on high level */ +#define GPIO_CFG_IN_INT_NONE (((uint32_t)0) << GPIO_CFG_INT_LSB) /*!< @hideinitializer No Interrupt */ +#define GPIO_CFG_IN_INT_FALLING (((uint32_t)1) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on falling edge */ +#define GPIO_CFG_IN_INT_RISING (((uint32_t)2) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on rising edge */ +#define GPIO_CFG_IN_INT_BOTH_EDGES (((uint32_t)3) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on both edges */ +#define GPIO_CFG_IN_INT_LOW (((uint32_t)4) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on low level */ +#define GPIO_CFG_IN_INT_HIGH (((uint32_t)5) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on high level */ /** @} */ /** @name Special GPIO_PinConfig configuration macros @@ -399,13 +399,13 @@ typedef uint32_t GPIO_PinConfig; * @brief 'Or' in this @ref GPIO_PinConfig definition to inform GPIO_setConfig() * to only configure the interrupt attributes of a GPIO input pin. */ -#define GPIO_CFG_IN_INT_ONLY (((uint32_t) 1) << 27) /*!< @hideinitializer configure interrupt only */ +#define GPIO_CFG_IN_INT_ONLY (((uint32_t)1) << 27) /*!< @hideinitializer configure interrupt only */ /*! * @brief Use this @ref GPIO_PinConfig definition to inform GPIO_init() * NOT to configure the corresponding pin */ -#define GPIO_DO_NOT_CONFIG 0x40000000 /*!< @hideinitializer Do not configure this Pin */ +#define GPIO_DO_NOT_CONFIG 0x40000000 /*!< @hideinitializer Do not configure this Pin */ /** @} */ /** @} end of GPIO_PinConfigSettings group */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/I2C.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/I2C.h index 0f5d837..0f58f30 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/I2C.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/I2C.h @@ -302,7 +302,7 @@ extern "C" { * #define I2CXYZ_CMD_COMMAND1 I2C_CMD_RESERVED + 1 * @endcode */ -#define I2C_CMD_RESERVED (32) +#define I2C_CMD_RESERVED (32) /*! * @private @@ -317,7 +317,7 @@ extern "C" { * #define I2CXYZ_STATUS_ERROR2 I2C_STATUS_RESERVED - 2 * @endcode */ -#define I2C_STATUS_RESERVED (-32) +#define I2C_STATUS_RESERVED (-32) /*! @endcond */ /** @@ -333,7 +333,7 @@ extern "C" { * I2C_control() returns #I2C_STATUS_SUCCESS if the control code was executed * successfully. */ -#define I2C_STATUS_SUCCESS (0) +#define I2C_STATUS_SUCCESS (0) /*! * @brief Generic error status code returned by I2C_control(). @@ -341,7 +341,7 @@ extern "C" { * I2C_control() returns #I2C_STATUS_ERROR if the control code was not executed * successfully. */ -#define I2C_STATUS_ERROR (-1) +#define I2C_STATUS_ERROR (-1) /*! * @brief An error status code returned by I2C_control() for undefined @@ -350,7 +350,7 @@ extern "C" { * I2C_control() returns #I2C_STATUS_UNDEFINEDCMD if the control code is not * recognized by the driver implementation. */ -#define I2C_STATUS_UNDEFINEDCMD (-2) +#define I2C_STATUS_UNDEFINEDCMD (-2) /** @}*/ /** @@ -379,73 +379,73 @@ typedef struct I2C_Config_* I2C_Handle; */ typedef struct { - /*! - * Pointer to a buffer of at least #I2C_Transaction.writeCount bytes. - * If #I2C_Transaction.writeCount is 0, this pointer is not used. - */ - void* writeBuf; + /*! + * Pointer to a buffer of at least #I2C_Transaction.writeCount bytes. + * If #I2C_Transaction.writeCount is 0, this pointer is not used. + */ + void* writeBuf; - /*! - * Number of bytes to write to the I2C slave device. A value of 0 - * indicates no data will be written to the slave device and only a read - * will occur. If this value - * is not 0, the driver will always perform the write transfer first. - * The data written to the I2C bus is preceded by the - * #I2C_Transaction.slaveAddress with the write bit set. If - * @p writeCount bytes are successfully sent and - * acknowledged, the transfer will complete or perform a read--depending - * on #I2C_Transaction.readCount. - * - * @note Both #I2C_Transaction.writeCount and #I2C_Transaction.readCount - * can not be 0. - */ - size_t writeCount; + /*! + * Number of bytes to write to the I2C slave device. A value of 0 + * indicates no data will be written to the slave device and only a read + * will occur. If this value + * is not 0, the driver will always perform the write transfer first. + * The data written to the I2C bus is preceded by the + * #I2C_Transaction.slaveAddress with the write bit set. If + * @p writeCount bytes are successfully sent and + * acknowledged, the transfer will complete or perform a read--depending + * on #I2C_Transaction.readCount. + * + * @note Both #I2C_Transaction.writeCount and #I2C_Transaction.readCount + * can not be 0. + */ + size_t writeCount; - /*! - * Pointer to a buffer of at least #I2C_Transaction.readCount bytes. - * If #I2C_Transaction.readCount is 0, this pointer is not used. - */ - void* readBuf; + /*! + * Pointer to a buffer of at least #I2C_Transaction.readCount bytes. + * If #I2C_Transaction.readCount is 0, this pointer is not used. + */ + void* readBuf; - /*! - * Number of bytes to read from the I2C slave device. A value of 0 - * indicates no data will be read and only a write will occur. If - * #I2C_Transaction.writeCount is not 0, this driver will perform the - * write first, followed by the read. The data read from the bus is - * preceded by the #I2C_Transaction.slaveAddress with the read bit set. - * After @p readCount bytes are successfully read, the transfer will - * complete. - * - * @note Both #I2C_Transaction.writeCount and #I2C_Transaction.readCount - * can not be 0. - */ - size_t readCount; + /*! + * Number of bytes to read from the I2C slave device. A value of 0 + * indicates no data will be read and only a write will occur. If + * #I2C_Transaction.writeCount is not 0, this driver will perform the + * write first, followed by the read. The data read from the bus is + * preceded by the #I2C_Transaction.slaveAddress with the read bit set. + * After @p readCount bytes are successfully read, the transfer will + * complete. + * + * @note Both #I2C_Transaction.writeCount and #I2C_Transaction.readCount + * can not be 0. + */ + size_t readCount; - /*! - * I2C slave address used for the transaction. The slave address is - * the first byte transmitted during an I2C transfer. The read/write bit - * is automatically set based upon the #I2C_Transaction.writeCount and - * #I2C_Transaction.readCount. - */ - uint_least8_t slaveAddress; + /*! + * I2C slave address used for the transaction. The slave address is + * the first byte transmitted during an I2C transfer. The read/write bit + * is automatically set based upon the #I2C_Transaction.writeCount and + * #I2C_Transaction.readCount. + */ + uint_least8_t slaveAddress; - /*! - * Pointer to a custom argument to be passed to the #I2C_CallbackFxn - * function via the #I2C_Transaction structure. - * - * @note The #I2C_CallbackFxn function is only called when operating in - * #I2C_MODE_CALLBACK. - * - * @sa #I2C_MODE_CALLBACK - * @sa #I2C_CallbackFxn - */ - void* arg; + /*! + * Pointer to a custom argument to be passed to the #I2C_CallbackFxn + * function via the #I2C_Transaction structure. + * + * @note The #I2C_CallbackFxn function is only called when operating in + * #I2C_MODE_CALLBACK. + * + * @sa #I2C_MODE_CALLBACK + * @sa #I2C_CallbackFxn + */ + void* arg; - /*! - * @private This is reserved for use by the driver and must never be - * modified by the application. - */ - void* nextPtr; + /*! + * @private This is reserved for use by the driver and must never be + * modified by the application. + */ + void* nextPtr; } I2C_Transaction; /*! @@ -519,11 +519,11 @@ typedef void (*I2C_CallbackFxn)(I2C_Handle handle, I2C_Transaction* transaction, */ typedef enum { - I2C_100kHz = 0, /*!< I2C Standard-mode. Up to 100 kbit/s. */ - I2C_400kHz = 1, /*!< I2C Fast-mode. Up to 400 kbit/s. */ - I2C_1000kHz = 2, /*!< I2C Fast-mode Plus. Up to 1Mbit/s. */ - I2C_3330kHz = 3, /*!< I2C High-speed mode. Up to 3.4Mbit/s. */ - I2C_3400kHz = 3, /*!< I2C High-speed mode. Up to 3.4Mbit/s. */ + I2C_100kHz = 0, /*!< I2C Standard-mode. Up to 100 kbit/s. */ + I2C_400kHz = 1, /*!< I2C Fast-mode. Up to 400 kbit/s. */ + I2C_1000kHz = 2, /*!< I2C Fast-mode Plus. Up to 1Mbit/s. */ + I2C_3330kHz = 3, /*!< I2C High-speed mode. Up to 3.4Mbit/s. */ + I2C_3400kHz = 3, /*!< I2C High-speed mode. Up to 3.4Mbit/s. */ } I2C_BitRate; /*! @@ -536,23 +536,23 @@ typedef enum */ typedef struct { - /*! #I2C_TransferMode for all I2C transfers. */ - I2C_TransferMode transferMode; + /*! #I2C_TransferMode for all I2C transfers. */ + I2C_TransferMode transferMode; - /*! - * Pointer to a #I2C_CallbackFxn to be invoked after a - * I2C_transfer() completes when operating in #I2C_MODE_CALLBACK. - */ - I2C_CallbackFxn transferCallbackFxn; + /*! + * Pointer to a #I2C_CallbackFxn to be invoked after a + * I2C_transfer() completes when operating in #I2C_MODE_CALLBACK. + */ + I2C_CallbackFxn transferCallbackFxn; - /*! - * A #I2C_BitRate specifying the frequency at which the I2C peripheral - * will transmit data during a I2C_transfer(). - */ - I2C_BitRate bitRate; + /*! + * A #I2C_BitRate specifying the frequency at which the I2C peripheral + * will transmit data during a I2C_transfer(). + */ + I2C_BitRate bitRate; - /*! Pointer to a device specific extension of the #I2C_Params */ - void* custom; + /*! Pointer to a device specific extension of the #I2C_Params */ + void* custom; } I2C_Params; /*! @@ -560,44 +560,44 @@ typedef struct * @brief A function pointer to a driver-specific implementation of * I2C_cancel(). */ -typedef void (*I2C_CancelFxn) (I2C_Handle handle); +typedef void (*I2C_CancelFxn)(I2C_Handle handle); /*! * @private * @brief A function pointer to a driver-specific implementation of * I2C_close(). */ -typedef void (*I2C_CloseFxn) (I2C_Handle handle); +typedef void (*I2C_CloseFxn)(I2C_Handle handle); /*! * @private * @brief A function pointer to a driver-specific implementation of * I2C_control(). */ -typedef int_fast16_t (*I2C_ControlFxn) (I2C_Handle handle, uint_fast16_t cmd, - void* controlArg); +typedef int_fast16_t (*I2C_ControlFxn)(I2C_Handle handle, uint_fast16_t cmd, + void* controlArg); /*! * @private * @brief A function pointer to a driver-specific implementation of * I2C_init(). */ -typedef void (*I2C_InitFxn) (I2C_Handle handle); +typedef void (*I2C_InitFxn)(I2C_Handle handle); /*! * @private * @brief A function pointer to a driver-specific implementation of * I2C_open(). */ -typedef I2C_Handle (*I2C_OpenFxn) (I2C_Handle handle, I2C_Params* params); +typedef I2C_Handle (*I2C_OpenFxn)(I2C_Handle handle, I2C_Params* params); /*! * @private * @brief A function pointer to a driver-specific implementation of * I2C_transfer(). */ -typedef bool (*I2C_TransferFxn) (I2C_Handle handle, - I2C_Transaction* transaction); +typedef bool (*I2C_TransferFxn)(I2C_Handle handle, + I2C_Transaction* transaction); /*! * @brief The definition of an I2C function table that contains the @@ -606,12 +606,12 @@ typedef bool (*I2C_TransferFxn) (I2C_Handle handle, */ typedef struct I2C_FxnTable_ { - I2C_CancelFxn cancelFxn; - I2C_CloseFxn closeFxn; - I2C_ControlFxn controlFxn; - I2C_InitFxn initFxn; - I2C_OpenFxn openFxn; - I2C_TransferFxn transferFxn; + I2C_CancelFxn cancelFxn; + I2C_CloseFxn closeFxn; + I2C_ControlFxn controlFxn; + I2C_InitFxn initFxn; + I2C_OpenFxn openFxn; + I2C_TransferFxn transferFxn; } I2C_FxnTable; /*! @@ -623,16 +623,16 @@ typedef struct I2C_FxnTable_ */ typedef struct I2C_Config_ { - /*! Pointer to a @ref driver_function_table "function pointer table" - * with driver-specific implementations of I2C APIs */ - I2C_FxnTable const* fxnTablePtr; + /*! Pointer to a @ref driver_function_table "function pointer table" + * with driver-specific implementations of I2C APIs */ + I2C_FxnTable const* fxnTablePtr; - /*! Pointer to a driver specific @ref driver_objects "data object". */ - void* object; + /*! Pointer to a driver specific @ref driver_objects "data object". */ + void* object; - /*! Pointer to a driver specific @ref driver_hardware_attributes - * "hardware attributes structure". */ - void const* hwAttrs; + /*! Pointer to a driver specific @ref driver_hardware_attributes + * "hardware attributes structure". */ + void const* hwAttrs; } I2C_Config; /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/I2S.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/I2S.h index c775067..0f141da 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/I2S.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/I2S.h @@ -567,13 +567,12 @@ #ifndef ti_drivers_I2S__include #define ti_drivers_I2S__include -#include #include +#include #include #include - #ifdef __cplusplus extern "C" { #endif @@ -591,7 +590,7 @@ extern "C" { * I2S driver functions return I2S_ALL_TRANSACTION_SUCCESS if ALL the queued transactions * were executed successfully. */ -#define I2S_ALL_TRANSACTIONS_SUCCESS (0x0001U) +#define I2S_ALL_TRANSACTIONS_SUCCESS (0x0001U) /*! * @brief Successful status code returned by I2S driver functions. @@ -599,7 +598,7 @@ extern "C" { * I2S driver functions return I2S_TRANSACTION_SUCCESS if ONE queued transaction * was executed successfully. */ -#define I2S_TRANSACTION_SUCCESS (0x0002U) +#define I2S_TRANSACTION_SUCCESS (0x0002U) /*! * @brief Error status code returned by I2S driver functions. @@ -607,7 +606,7 @@ extern "C" { * I2S driver functions return I2S_TIMEOUT_ERROR if I2S module lost the audio clock. * If this error has been raised, I2S module must be reseted and restarted. */ -#define I2S_TIMEOUT_ERROR (0x0100U) +#define I2S_TIMEOUT_ERROR (0x0100U) /*! * @brief Error status code returned by I2S driver functions. @@ -616,7 +615,7 @@ extern "C" { * bus (DMA transfer not completed in time). * If this error has been raised, I2S module must be reseted and restarted. */ -#define I2S_BUS_ERROR (0x0200U) +#define I2S_BUS_ERROR (0x0200U) /*! * @brief Error status code returned by I2S driver functions. @@ -624,7 +623,7 @@ extern "C" { * I2S driver functions return I2S_WS_ERROR if I2S module detect noise on the WS signal. * If this error has been raised, I2S module must be reseted and restarted. */ -#define I2S_WS_ERROR (0x0400U) +#define I2S_WS_ERROR (0x0400U) /*! * @brief Error status code returned by I2S driver functions. @@ -633,7 +632,7 @@ extern "C" { * on the read interface (DMA pointer not loaded in time). * If this error has been raised, I2S module must be reseted and restarted. */ -#define I2S_PTR_READ_ERROR (0x0800U) +#define I2S_PTR_READ_ERROR (0x0800U) /*! * @brief Error status code returned by I2S driver functions. @@ -642,7 +641,7 @@ extern "C" { * on the write interface (DMA pointer not loaded in time). * If this error has been raised, I2S module must be reseted and restarted. */ -#define I2S_PTR_WRITE_ERROR (0x1000U) +#define I2S_PTR_WRITE_ERROR (0x1000U) /** @}*/ /*! @@ -655,20 +654,20 @@ typedef struct I2S_Config_* I2S_Handle; */ typedef struct I2S_Transaction_ { - /*! Used internally to link descriptors together */ - List_Elem queueElement; - /*! Pointer to the buffer */ - void* bufPtr; - /*! Size of the buffer. */ - size_t bufSize; - /*! Internal use only. Number of bytes written to or read from the buffer. */ - size_t bytesTransferred; - /*! Number of non-transfered bytes at transaction's end. */ - size_t untransferredBytes; - /*! Parameter incremented each time the transaction is completed. */ - uint16_t numberOfCompletions; - /*! Internal argument. Application must not modify this element. */ - uintptr_t arg; + /*! Used internally to link descriptors together */ + List_Elem queueElement; + /*! Pointer to the buffer */ + void* bufPtr; + /*! Size of the buffer. */ + size_t bufSize; + /*! Internal use only. Number of bytes written to or read from the buffer. */ + size_t bytesTransferred; + /*! Number of non-transfered bytes at transaction's end. */ + size_t untransferredBytes; + /*! Parameter incremented each time the transaction is completed. */ + uint16_t numberOfCompletions; + /*! Internal argument. Application must not modify this element. */ + uintptr_t arg; } I2S_Transaction; /*! @@ -705,10 +704,10 @@ typedef void (*I2S_RegUpdate)(uint32_t ui32Base, uint32_t ui32NextPointer); typedef enum I2S_MemoryLength_ { - I2S_MEMORY_LENGTH_8BITS = 8U, /*!< Buffer used is 8 bits length. Not available for CC26XX. */ - I2S_MEMORY_LENGTH_16BITS = 16U, /*!< Buffer used is 16 bits length. */ - I2S_MEMORY_LENGTH_24BITS = 24U, /*!< Buffer used is 24 bits length. */ - I2S_MEMORY_LENGTH_32BITS = 32U /*!< Buffer used is 32 bits length. Not available for CC26XX. */ + I2S_MEMORY_LENGTH_8BITS = 8U, /*!< Buffer used is 8 bits length. Not available for CC26XX. */ + I2S_MEMORY_LENGTH_16BITS = 16U, /*!< Buffer used is 16 bits length. */ + I2S_MEMORY_LENGTH_24BITS = 24U, /*!< Buffer used is 24 bits length. */ + I2S_MEMORY_LENGTH_32BITS = 32U /*!< Buffer used is 32 bits length. Not available for CC26XX. */ } I2S_MemoryLength; @@ -721,8 +720,8 @@ typedef enum I2S_MemoryLength_ typedef enum I2S_Role_ { - I2S_SLAVE = 0, /*!< Module is a slave, clocks are externally generated. */ - I2S_MASTER = 1 /*!< Module is a master, clocks are internally generated. */ + I2S_SLAVE = 0, /*!< Module is a slave, clocks are externally generated. */ + I2S_MASTER = 1 /*!< Module is a master, clocks are internally generated. */ } I2S_Role; @@ -734,8 +733,8 @@ typedef enum I2S_Role_ typedef enum I2S_SamplingEdge_ { - I2S_SAMPLING_EDGE_FALLING = 0, /*!< Sampling on falling edges. */ - I2S_SAMPLING_EDGE_RISING = 1 /*!< Sampling on rising edges. */ + I2S_SAMPLING_EDGE_FALLING = 0, /*!< Sampling on falling edges. */ + I2S_SAMPLING_EDGE_RISING = 1 /*!< Sampling on rising edges. */ } I2S_SamplingEdge; @@ -747,8 +746,8 @@ typedef enum I2S_SamplingEdge_ typedef enum I2S_PhaseType_ { - I2S_PHASE_TYPE_SINGLE = 0U, /*!< Single phase */ - I2S_PHASE_TYPE_DUAL = 1U, /*!< Dual phase */ + I2S_PHASE_TYPE_SINGLE = 0U, /*!< Single phase */ + I2S_PHASE_TYPE_DUAL = 1U, /*!< Dual phase */ } I2S_PhaseType; @@ -760,12 +759,12 @@ typedef enum I2S_PhaseType_ typedef enum I2S_DataInterfaceUse_ { - I2S_SD0_DISABLED = 0x00U, /*!< SD0 is disabled */ - I2S_SD0_INPUT = 0x01U, /*!< SD0 is an input */ - I2S_SD0_OUTPUT = 0x02U, /*!< SD0 is an output */ - I2S_SD1_DISABLED = 0x00U, /*!< SD1 is disabled */ - I2S_SD1_INPUT = 0x10U, /*!< SD1 is an input */ - I2S_SD1_OUTPUT = 0x20U /*!< SD1 is an output */ + I2S_SD0_DISABLED = 0x00U, /*!< SD0 is disabled */ + I2S_SD0_INPUT = 0x01U, /*!< SD0 is an input */ + I2S_SD0_OUTPUT = 0x02U, /*!< SD0 is an output */ + I2S_SD1_DISABLED = 0x00U, /*!< SD1 is disabled */ + I2S_SD1_INPUT = 0x10U, /*!< SD1 is an input */ + I2S_SD1_OUTPUT = 0x20U /*!< SD1 is an output */ } I2S_DataInterfaceUse; @@ -777,19 +776,19 @@ typedef enum I2S_DataInterfaceUse_ typedef enum I2S_ChannelConfig_ { - I2S_CHANNELS_NONE = 0x00U, /*!< No channel activated */ - I2S_CHANNELS_MONO = 0x01U, /*!< MONO: only channel one is activated */ - I2S_CHANNELS_MONO_INV = 0x02U, /*!< MONO INVERERTED: only channel two is activated */ - I2S_CHANNELS_STEREO = 0x03U, /*!< STEREO: channels one and two are activated */ - I2S_1_CHANNEL = 0x01U, /*!< 1 channel is activated */ - I2S_2_CHANNELS = 0x03U, /*!< 2 channels are activated */ - I2S_3_CHANNELS = 0x07U, /*!< 3 channels are activated */ - I2S_4_CHANNELS = 0x0FU, /*!< 4 channels are activated */ - I2S_5_CHANNELS = 0x1FU, /*!< 5 channels are activated */ - I2S_6_CHANNELS = 0x3FU, /*!< 6 channels are activated */ - I2S_7_CHANNELS = 0x7FU, /*!< 7 channels are activated */ - I2S_8_CHANNELS = 0xFFU, /*!< 8 channels are activated */ - I2S_CHANNELS_ALL = 0xFFU /*!< All the eight channels are activated */ + I2S_CHANNELS_NONE = 0x00U, /*!< No channel activated */ + I2S_CHANNELS_MONO = 0x01U, /*!< MONO: only channel one is activated */ + I2S_CHANNELS_MONO_INV = 0x02U, /*!< MONO INVERERTED: only channel two is activated */ + I2S_CHANNELS_STEREO = 0x03U, /*!< STEREO: channels one and two are activated */ + I2S_1_CHANNEL = 0x01U, /*!< 1 channel is activated */ + I2S_2_CHANNELS = 0x03U, /*!< 2 channels are activated */ + I2S_3_CHANNELS = 0x07U, /*!< 3 channels are activated */ + I2S_4_CHANNELS = 0x0FU, /*!< 4 channels are activated */ + I2S_5_CHANNELS = 0x1FU, /*!< 5 channels are activated */ + I2S_6_CHANNELS = 0x3FU, /*!< 6 channels are activated */ + I2S_7_CHANNELS = 0x7FU, /*!< 7 channels are activated */ + I2S_8_CHANNELS = 0xFFU, /*!< 8 channels are activated */ + I2S_CHANNELS_ALL = 0xFFU /*!< All the eight channels are activated */ } I2S_ChannelConfig; @@ -804,140 +803,140 @@ typedef enum I2S_ChannelConfig_ typedef struct I2S_Params_ { - bool invertWS; - /*!< WS must be internally inverted when using I2S data format. - * false: The WS signal is not internally inverted. - * true: The WS signal is internally inverted. */ + bool invertWS; + /*!< WS must be internally inverted when using I2S data format. + * false: The WS signal is not internally inverted. + * true: The WS signal is internally inverted. */ - bool isMSBFirst; - /*!< Endianness selection. Not available on CC26XX. - * false: The samples are transmitted LSB first. - * true: The samples are transmitted MSB first. */ + bool isMSBFirst; + /*!< Endianness selection. Not available on CC26XX. + * false: The samples are transmitted LSB first. + * true: The samples are transmitted MSB first. */ - bool isDMAUnused; - /*!< Selection between DMA transmissions and CPU transmissions. - * false: Transmission are performed by DMA. - * true: Transmission are performed by CPU. - * Not available for CC26XX: all transmissions are performed by CPU. */ + bool isDMAUnused; + /*!< Selection between DMA transmissions and CPU transmissions. + * false: Transmission are performed by DMA. + * true: Transmission are performed by CPU. + * Not available for CC26XX: all transmissions are performed by CPU. */ - I2S_MemoryLength memorySlotLength; - /*!< Memory buffer used. - * #I2S_MEMORY_LENGTH_8BITS: Memory length is 8 bits (not available for CC26XX). - * #I2S_MEMORY_LENGTH_16BITS: Memory length is 16 bits. - * #I2S_MEMORY_LENGTH_24BITS: Memory length is 24 bits. - * #I2S_MEMORY_LENGTH_32BITS: Memory length is 32 bits (not available for CC26XX).*/ + I2S_MemoryLength memorySlotLength; + /*!< Memory buffer used. + * #I2S_MEMORY_LENGTH_8BITS: Memory length is 8 bits (not available for CC26XX). + * #I2S_MEMORY_LENGTH_16BITS: Memory length is 16 bits. + * #I2S_MEMORY_LENGTH_24BITS: Memory length is 24 bits. + * #I2S_MEMORY_LENGTH_32BITS: Memory length is 32 bits (not available for CC26XX).*/ - uint8_t beforeWordPadding; - /*!< Number of SCK periods between the first WS edge and the MSB of the first audio channel data transferred during the phase.*/ + uint8_t beforeWordPadding; + /*!< Number of SCK periods between the first WS edge and the MSB of the first audio channel data transferred during the phase.*/ - uint8_t afterWordPadding; - /*!< Number of SCK periods between the first WS edge and the MSB of the first audio channel data transferred during the phase.*/ + uint8_t afterWordPadding; + /*!< Number of SCK periods between the first WS edge and the MSB of the first audio channel data transferred during the phase.*/ - uint8_t bitsPerWord; - /*!< Bits per sample (Word length): must be between 8 and 24 bits. */ + uint8_t bitsPerWord; + /*!< Bits per sample (Word length): must be between 8 and 24 bits. */ - I2S_Role moduleRole; - /*!< Select if the I2S module is a Slave or a Master. - * - #I2S_SLAVE: The device is a slave (clocks are generated externally). - * - #I2S_MASTER: The device is a master (clocks are generated internally). */ + I2S_Role moduleRole; + /*!< Select if the I2S module is a Slave or a Master. + * - #I2S_SLAVE: The device is a slave (clocks are generated externally). + * - #I2S_MASTER: The device is a master (clocks are generated internally). */ - I2S_SamplingEdge samplingEdge; - /*!< Select edge sampling type. - * - #I2S_SAMPLING_EDGE_FALLING: Sampling on falling edges (for DSP data format). - * - #I2S_SAMPLING_EDGE_RISING: Sampling on rising edges (for I2S, LJF and RJF data formats). */ + I2S_SamplingEdge samplingEdge; + /*!< Select edge sampling type. + * - #I2S_SAMPLING_EDGE_FALLING: Sampling on falling edges (for DSP data format). + * - #I2S_SAMPLING_EDGE_RISING: Sampling on rising edges (for I2S, LJF and RJF data formats). */ - I2S_DataInterfaceUse SD0Use; - /*!< Select if SD0 is an input, an output or disabled. - * - #I2S_SD0_DISABLED: Disabled. - * - #I2S_SD0_INPUT: Input. - * - #I2S_SD0_OUTPUT: Output. */ + I2S_DataInterfaceUse SD0Use; + /*!< Select if SD0 is an input, an output or disabled. + * - #I2S_SD0_DISABLED: Disabled. + * - #I2S_SD0_INPUT: Input. + * - #I2S_SD0_OUTPUT: Output. */ - I2S_DataInterfaceUse SD1Use; - /*!< Select if SD1 is an input, an output or disabled. - * - #I2S_SD1_DISABLED: Disabled. - * - #I2S_SD1_INPUT: Input. - * - #I2S_SD1_OUTPUT: Output. */ + I2S_DataInterfaceUse SD1Use; + /*!< Select if SD1 is an input, an output or disabled. + * - #I2S_SD1_DISABLED: Disabled. + * - #I2S_SD1_INPUT: Input. + * - #I2S_SD1_OUTPUT: Output. */ - I2S_ChannelConfig SD0Channels; - /*!< This parameter is a bit mask indicating which channels are valid on SD0. - * If phase type is "dual", maximum channels number is two. - * Valid channels on SD1 and SD0 can be different. - * For dual phase mode: - * - #I2S_CHANNELS_NONE: No channel activated: - * read -> I2S does not receive anything (no buffer consumption) - * write -> I2S does not send anything (no buffer consumption) - * - #I2S_CHANNELS_MONO: Only channel 1 is activated: - * read -> I2S only reads channel 1 - * write -> I2S transmits the data on channel 1 and duplicates it on channel 2 - * - #I2S_CHANNELS_MONO_INV: Only channel 2 is activated: - * read -> I2S only reads channel 2 - * write -> I2S transmits the data on channel 2 and duplicates it on the channel 1 of the next word - * - #I2S_CHANNELS_STEREO: STEREO: - * read -> I2S reads both channel 1 and channel 2 - * write -> I2S transmits data both on channel 1 and channel 2 - * . - * For single phase mode: - * - Various number of channels can be activated using: #I2S_1_CHANNEL, #I2S_2_CHANNELS, #I2S_3_CHANNELS, #I2S_4_CHANNELS, - * #I2S_5_CHANNELS, #I2S_6_CHANNELS, #I2S_7_CHANNELS, #I2S_8_CHANNELS. - * - #I2S_CHANNELS_ALL: The eight channels are activated */ + I2S_ChannelConfig SD0Channels; + /*!< This parameter is a bit mask indicating which channels are valid on SD0. + * If phase type is "dual", maximum channels number is two. + * Valid channels on SD1 and SD0 can be different. + * For dual phase mode: + * - #I2S_CHANNELS_NONE: No channel activated: + * read -> I2S does not receive anything (no buffer consumption) + * write -> I2S does not send anything (no buffer consumption) + * - #I2S_CHANNELS_MONO: Only channel 1 is activated: + * read -> I2S only reads channel 1 + * write -> I2S transmits the data on channel 1 and duplicates it on channel 2 + * - #I2S_CHANNELS_MONO_INV: Only channel 2 is activated: + * read -> I2S only reads channel 2 + * write -> I2S transmits the data on channel 2 and duplicates it on the channel 1 of the next word + * - #I2S_CHANNELS_STEREO: STEREO: + * read -> I2S reads both channel 1 and channel 2 + * write -> I2S transmits data both on channel 1 and channel 2 + * . + * For single phase mode: + * - Various number of channels can be activated using: #I2S_1_CHANNEL, #I2S_2_CHANNELS, #I2S_3_CHANNELS, #I2S_4_CHANNELS, + * #I2S_5_CHANNELS, #I2S_6_CHANNELS, #I2S_7_CHANNELS, #I2S_8_CHANNELS. + * - #I2S_CHANNELS_ALL: The eight channels are activated */ - I2S_ChannelConfig SD1Channels; - /*!< This parameter is a bit mask indicating which channels are valid on SD1. - * If phase type is "dual", maximum channels number is two. - * Valid channels on SD1 and SD0 can be different. - * For dual phase mode: - * - #I2S_CHANNELS_NONE: No channel activated: - * read -> I2S does not receive anything (no buffer consumption) - * write -> I2S does not send anything (no buffer consumption) - * - #I2S_CHANNELS_MONO: Only channel 1 is activated: - * read -> I2S only reads channel 1 - * write -> I2S transmits the data on channel 1 and duplicates it on channel 2 - * - #I2S_CHANNELS_MONO_INV: Only channel 2 is activated: - * read -> I2S only reads channel 2 - * write -> I2S transmits the data on channel 2 and duplicates it on the channel 1 of the next word - * - #I2S_CHANNELS_STEREO: STEREO: - * read -> I2S reads both channel 1 and channel 2 - * write -> I2S transmits data both on channel 1 and channel 2 - * . - * For single phase mode: - * - Various number of channels can be activated using: #I2S_1_CHANNEL, #I2S_2_CHANNELS, #I2S_3_CHANNELS, #I2S_4_CHANNELS, - * #I2S_5_CHANNELS, #I2S_6_CHANNELS, #I2S_7_CHANNELS, #I2S_8_CHANNELS. - * - #I2S_CHANNELS_ALL: The eight channels are activated */ + I2S_ChannelConfig SD1Channels; + /*!< This parameter is a bit mask indicating which channels are valid on SD1. + * If phase type is "dual", maximum channels number is two. + * Valid channels on SD1 and SD0 can be different. + * For dual phase mode: + * - #I2S_CHANNELS_NONE: No channel activated: + * read -> I2S does not receive anything (no buffer consumption) + * write -> I2S does not send anything (no buffer consumption) + * - #I2S_CHANNELS_MONO: Only channel 1 is activated: + * read -> I2S only reads channel 1 + * write -> I2S transmits the data on channel 1 and duplicates it on channel 2 + * - #I2S_CHANNELS_MONO_INV: Only channel 2 is activated: + * read -> I2S only reads channel 2 + * write -> I2S transmits the data on channel 2 and duplicates it on the channel 1 of the next word + * - #I2S_CHANNELS_STEREO: STEREO: + * read -> I2S reads both channel 1 and channel 2 + * write -> I2S transmits data both on channel 1 and channel 2 + * . + * For single phase mode: + * - Various number of channels can be activated using: #I2S_1_CHANNEL, #I2S_2_CHANNELS, #I2S_3_CHANNELS, #I2S_4_CHANNELS, + * #I2S_5_CHANNELS, #I2S_6_CHANNELS, #I2S_7_CHANNELS, #I2S_8_CHANNELS. + * - #I2S_CHANNELS_ALL: The eight channels are activated */ - I2S_PhaseType phaseType; - /*!< Select phase type. - * - #I2S_PHASE_TYPE_SINGLE: Single phase (for DSP format): up to eight channels are usable. - * - #I2S_PHASE_TYPE_DUAL: Dual phase (for I2S, LJF and RJF data formats): up to two channels are usable. - * . - * This parameter must not be considered on CC32XX. This chip only allows dual phase formats.*/ + I2S_PhaseType phaseType; + /*!< Select phase type. + * - #I2S_PHASE_TYPE_SINGLE: Single phase (for DSP format): up to eight channels are usable. + * - #I2S_PHASE_TYPE_DUAL: Dual phase (for I2S, LJF and RJF data formats): up to two channels are usable. + * . + * This parameter must not be considered on CC32XX. This chip only allows dual phase formats.*/ - uint16_t fixedBufferLength; - /*!< Number of consecutive bytes of the samples buffers. This field must be set to a value x different from 0. - * All the data buffers used (both for input and output) must contain N*x bytes (with N an integer verifying N>0). */ + uint16_t fixedBufferLength; + /*!< Number of consecutive bytes of the samples buffers. This field must be set to a value x different from 0. + * All the data buffers used (both for input and output) must contain N*x bytes (with N an integer verifying N>0). */ - uint16_t startUpDelay; - /*!< Time (in number of WS cycles) to wait before the first transfer. */ + uint16_t startUpDelay; + /*!< Time (in number of WS cycles) to wait before the first transfer. */ - uint16_t MCLKDivider; - /*!< Select the frequency divider for MCLK signal. Final value of MCLK is 48MHz/MCLKDivider. Value must be selected between 2 and 1024. */ + uint16_t MCLKDivider; + /*!< Select the frequency divider for MCLK signal. Final value of MCLK is 48MHz/MCLKDivider. Value must be selected between 2 and 1024. */ - uint32_t samplingFrequency; - /*!< I2S sampling frequency configuration in samples/second. - * SCK frequency limits: - *- For CC26XX, SCK frequency should be between 47 kHz and 4 MHz. - *- For CC32XX, SCK frequency should be between 57 Hz and 8 MHz. */ + uint32_t samplingFrequency; + /*!< I2S sampling frequency configuration in samples/second. + * SCK frequency limits: + *- For CC26XX, SCK frequency should be between 47 kHz and 4 MHz. + *- For CC32XX, SCK frequency should be between 57 Hz and 8 MHz. */ - I2S_Callback readCallback; - /*!< Pointer to read callback. Cannot be NULL if a read interface is activated. */ + I2S_Callback readCallback; + /*!< Pointer to read callback. Cannot be NULL if a read interface is activated. */ - I2S_Callback writeCallback; - /*!< Pointer to write callback. Cannot be NULL if a write interface is activated. */ + I2S_Callback writeCallback; + /*!< Pointer to write callback. Cannot be NULL if a write interface is activated. */ - I2S_Callback errorCallback; - /*!< Pointer to error callback. Cannot be NULL. */ + I2S_Callback errorCallback; + /*!< Pointer to error callback. Cannot be NULL. */ - void* custom; - /*!< Pointer to device specific custom params */ + void* custom; + /*!< Pointer to device specific custom params */ } I2S_Params; /*! @@ -959,11 +958,11 @@ extern const I2S_Params I2S_defaultParams; */ typedef struct I2S_Config_ { - /*! Pointer to a driver specific data object */ - void* object; + /*! Pointer to a driver specific data object */ + void* object; - /*! Pointer to a driver specific hardware attributes structure */ - void const* hwAttrs; + /*! Pointer to a driver specific hardware attributes structure */ + void const* hwAttrs; } I2S_Config; /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/NVS.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/NVS.h index 19b98d1..9ee6684 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/NVS.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/NVS.h @@ -263,7 +263,7 @@ #include #include -#if defined (__cplusplus) +#if defined(__cplusplus) extern "C" { #endif @@ -284,7 +284,7 @@ extern "C" { * #define NVSXYZ_CMD_COMMAND1 NVS_CMD_RESERVED + 1 * @endcode */ -#define NVS_CMD_RESERVED (32) +#define NVS_CMD_RESERVED (32) /*! * Common NVS_control status code reservation offset. @@ -298,7 +298,7 @@ extern "C" { * #define NVSXYZ_STATUS_ERROR2 NVS_STATUS_RESERVED - 2 * @endcode */ -#define NVS_STATUS_RESERVED (-32) +#define NVS_STATUS_RESERVED (-32) /** * @defgroup NVS_STATUS Status Codes @@ -315,7 +315,7 @@ extern "C" { * APIs returns NVS_STATUS_SUCCESS if the API was executed * successfully. */ -#define NVS_STATUS_SUCCESS (0) +#define NVS_STATUS_SUCCESS (0) /*! * @brief Generic error status code returned by: @@ -324,7 +324,7 @@ extern "C" { * APIs return NVS_STATUS_ERROR if the API was not executed * successfully. */ -#define NVS_STATUS_ERROR (-1) +#define NVS_STATUS_ERROR (-1) /*! * @brief An error status code returned by NVS_control() for undefined @@ -333,14 +333,14 @@ extern "C" { * NVS_control() returns #NVS_STATUS_UNDEFINEDCMD if the control code is not * recognized by the driver implementation. */ -#define NVS_STATUS_UNDEFINEDCMD (-2) +#define NVS_STATUS_UNDEFINEDCMD (-2) /*! * @brief An error status code returned by NVS_lock() * * NVS_lock() will return this value if the @p timeout has expired */ -#define NVS_STATUS_TIMEOUT (-3) +#define NVS_STATUS_TIMEOUT (-3) /*! * @brief An error status code returned by NVS_read(), NVS_write(), or @@ -349,7 +349,7 @@ extern "C" { * Error status code returned if the @p offset argument is invalid * (e.g., when offset + bufferSize exceeds the size of the region). */ -#define NVS_STATUS_INV_OFFSET (-4) +#define NVS_STATUS_INV_OFFSET (-4) /*! * @brief An error status code @@ -357,7 +357,7 @@ extern "C" { * Error status code returned by NVS_erase() if the @p offset argument is * not aligned on a flash sector address. */ -#define NVS_STATUS_INV_ALIGNMENT (-5) +#define NVS_STATUS_INV_ALIGNMENT (-5) /*! * @brief An error status code returned by NVS_erase() and NVS_write() @@ -366,7 +366,7 @@ extern "C" { * not a multiple of the flash sector size, or if @p offset + @p size * extends past the end of the region. */ -#define NVS_STATUS_INV_SIZE (-6) +#define NVS_STATUS_INV_SIZE (-6) /*! * @brief An error status code returned by NVS_write() @@ -375,7 +375,7 @@ extern "C" { * requested and a flash location can not be changed to the value * desired. */ -#define NVS_STATUS_INV_WRITE (-7) +#define NVS_STATUS_INV_WRITE (-7) /** @}*/ @@ -393,7 +393,6 @@ extern "C" { /** @} end NVS_CONTROL group */ - /*! * @brief NVS write flags * @@ -409,7 +408,7 @@ extern "C" { * affected destination flash sectors will be erased prior to the * start of the write operation. */ -#define NVS_WRITE_ERASE (0x1) +#define NVS_WRITE_ERASE (0x1) /*! * @brief Validate write flag. @@ -419,7 +418,7 @@ extern "C" { * data can be successfully written. If #NVS_WRITE_ERASE is also requested in * the write flags, then the #NVS_WRITE_PRE_VERIFY modifier is ignored. */ -#define NVS_WRITE_PRE_VERIFY (0x2) +#define NVS_WRITE_PRE_VERIFY (0x2) /*! * @brief Validate write flag. @@ -428,7 +427,7 @@ extern "C" { * destination address range will be tested after the write is finished to * verify that the write operation was completed successfully. */ -#define NVS_WRITE_POST_VERIFY (0x4) +#define NVS_WRITE_POST_VERIFY (0x4) /** @} */ @@ -438,14 +437,14 @@ extern "C" { */ /*! -* @brief NVS_lock() Wait forever define -*/ -#define NVS_LOCK_WAIT_FOREVER (~(0U)) + * @brief NVS_lock() Wait forever define + */ +#define NVS_LOCK_WAIT_FOREVER (~(0U)) /*! * @brief NVS_lock() No wait define */ -#define NVS_LOCK_NO_WAIT (0U) +#define NVS_LOCK_NO_WAIT (0U) /** @} */ @@ -455,13 +454,13 @@ extern "C" { */ /*! -* @brief This region is not directly addressable (e.g.,: SPI flash region) -* -* The NVS_Attrs.regionBase field returned by NVS_getAttrs() is set to this -* value by the NVSSPI driver to indicate that the region is not directly -* addressable. -*/ -#define NVS_REGION_NOT_ADDRESSABLE ((void *)(~(0U))) + * @brief This region is not directly addressable (e.g.,: SPI flash region) + * + * The NVS_Attrs.regionBase field returned by NVS_getAttrs() is set to this + * value by the NVSSPI driver to indicate that the region is not directly + * addressable. + */ +#define NVS_REGION_NOT_ADDRESSABLE ((void*)(~(0U))) /** @} */ @@ -475,7 +474,7 @@ extern "C" { */ typedef struct { - void* custom; /*!< Custom argument used by driver implementation */ + void* custom; /*!< Custom argument used by driver implementation */ } NVS_Params; /*! @@ -487,13 +486,13 @@ typedef struct */ typedef struct { - void* regionBase; /*!< Base address of the NVS region. If the NVS - region is not directly accessible by the MCU - (such as SPI flash), this field will be set to - #NVS_REGION_NOT_ADDRESSABLE. */ - size_t regionSize; /*!< NVS region size in bytes. */ - size_t sectorSize; /*!< Erase sector size in bytes. This attribute is - device specific. */ + void* regionBase; /*!< Base address of the NVS region. If the NVS + region is not directly accessible by the MCU + (such as SPI flash), this field will be set to + #NVS_REGION_NOT_ADDRESSABLE. */ + size_t regionSize; /*!< NVS region size in bytes. */ + size_t sectorSize; /*!< Erase sector size in bytes. This attribute is + device specific. */ } NVS_Attrs; /*! @@ -505,66 +504,66 @@ typedef struct NVS_Config_* NVS_Handle; * @brief A function pointer to a driver specific implementation of * NVS_close(). */ -typedef void (*NVS_CloseFxn) (NVS_Handle handle); +typedef void (*NVS_CloseFxn)(NVS_Handle handle); /*! * @brief A function pointer to a driver specific implementation of * NVS_control(). */ -typedef int_fast16_t (*NVS_ControlFxn) (NVS_Handle handle, uint_fast16_t cmd, - uintptr_t arg); +typedef int_fast16_t (*NVS_ControlFxn)(NVS_Handle handle, uint_fast16_t cmd, + uintptr_t arg); /*! * @brief A function pointer to a driver specific implementation of * NVS_erase(). */ -typedef int_fast16_t (*NVS_EraseFxn) (NVS_Handle handle, size_t offset, - size_t size); +typedef int_fast16_t (*NVS_EraseFxn)(NVS_Handle handle, size_t offset, + size_t size); /*! * @brief A function pointer to a driver specific implementation of * NVS_getAttrs(). */ -typedef void (*NVS_GetAttrsFxn) (NVS_Handle handle, NVS_Attrs* attrs); +typedef void (*NVS_GetAttrsFxn)(NVS_Handle handle, NVS_Attrs* attrs); /*! * @brief A function pointer to a driver specific implementation of * NVS_init(). */ -typedef void (*NVS_InitFxn) (void); +typedef void (*NVS_InitFxn)(void); /*! * @brief A function pointer to a driver specific implementation of * NVS_open(). */ -typedef NVS_Handle (*NVS_OpenFxn) (uint_least8_t index, NVS_Params* params); +typedef NVS_Handle (*NVS_OpenFxn)(uint_least8_t index, NVS_Params* params); /*! * @brief A function pointer to a driver specific implementation of * NVS_read(). */ -typedef int_fast16_t (*NVS_ReadFxn) (NVS_Handle handle, size_t offset, - void* buffer, size_t bufferSize); +typedef int_fast16_t (*NVS_ReadFxn)(NVS_Handle handle, size_t offset, + void* buffer, size_t bufferSize); /*! * @brief A function pointer to a driver specific implementation of * NVS_write(). */ -typedef int_fast16_t (*NVS_WriteFxn) (NVS_Handle handle, size_t offset, - void* buffer, size_t bufferSize, - uint_fast16_t flags); +typedef int_fast16_t (*NVS_WriteFxn)(NVS_Handle handle, size_t offset, + void* buffer, size_t bufferSize, + uint_fast16_t flags); /*! * @brief A function pointer to a driver specific implementation of * NVS_lock(). */ -typedef int_fast16_t (*NVS_LockFxn) (NVS_Handle handle, uint32_t timeout); +typedef int_fast16_t (*NVS_LockFxn)(NVS_Handle handle, uint32_t timeout); /*! * @brief A function pointer to a driver specific implementation of * NVS_unlock(). */ -typedef void (*NVS_UnlockFxn) (NVS_Handle handle); +typedef void (*NVS_UnlockFxn)(NVS_Handle handle); /*! * @brief The definition of an NVS function table that contains the @@ -573,35 +572,35 @@ typedef void (*NVS_UnlockFxn) (NVS_Handle handle); */ typedef struct { - /*! Function to close the specified NVS region */ - NVS_CloseFxn closeFxn; + /*! Function to close the specified NVS region */ + NVS_CloseFxn closeFxn; - /*! Function to apply control command to the specified NVS region */ - NVS_ControlFxn controlFxn; + /*! Function to apply control command to the specified NVS region */ + NVS_ControlFxn controlFxn; - /*! Function to erase a portion of the specified NVS region */ - NVS_EraseFxn eraseFxn; + /*! Function to erase a portion of the specified NVS region */ + NVS_EraseFxn eraseFxn; - /*! Function to get the NVS device-specific attributes */ - NVS_GetAttrsFxn getAttrsFxn; + /*! Function to get the NVS device-specific attributes */ + NVS_GetAttrsFxn getAttrsFxn; - /*! Function to initialize the NVS module */ - NVS_InitFxn initFxn; + /*! Function to initialize the NVS module */ + NVS_InitFxn initFxn; - /*! Function to lock the specified NVS flash region */ - NVS_LockFxn lockFxn; + /*! Function to lock the specified NVS flash region */ + NVS_LockFxn lockFxn; - /*! Function to open an NVS region */ - NVS_OpenFxn openFxn; + /*! Function to open an NVS region */ + NVS_OpenFxn openFxn; - /*! Function to read from the specified NVS region */ - NVS_ReadFxn readFxn; + /*! Function to read from the specified NVS region */ + NVS_ReadFxn readFxn; - /*! Function to unlock the specified NVS flash region */ - NVS_UnlockFxn unlockFxn; + /*! Function to unlock the specified NVS flash region */ + NVS_UnlockFxn unlockFxn; - /*! Function to write to the specified NVS region */ - NVS_WriteFxn writeFxn; + /*! Function to write to the specified NVS region */ + NVS_WriteFxn writeFxn; } NVS_FxnTable; /*! @@ -617,14 +616,14 @@ typedef struct */ typedef struct NVS_Config_ { - /*! Pointer to a table of driver-specific implementations of NVS APIs */ - NVS_FxnTable const* fxnTablePtr; + /*! Pointer to a table of driver-specific implementations of NVS APIs */ + NVS_FxnTable const* fxnTablePtr; - /*! Pointer to a driver specific data object */ - void* object; + /*! Pointer to a driver specific data object */ + void* object; - /*! Pointer to a driver specific hardware attributes structure */ - void const* hwAttrs; + /*! Pointer to a driver specific hardware attributes structure */ + void const* hwAttrs; } NVS_Config; /*! @@ -835,7 +834,7 @@ extern void NVS_unlock(NVS_Handle handle); extern int_fast16_t NVS_write(NVS_Handle handle, size_t offset, void* buffer, size_t bufferSize, uint_fast16_t flags); -#if defined (__cplusplus) +#if defined(__cplusplus) } #endif /* defined (__cplusplus) */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/PIN.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/PIN.h index 3668d5c..b34aa76 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/PIN.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/PIN.h @@ -299,7 +299,7 @@ * |#PIN_DRVSTR_MAX |#PIN_BM_DRVSTR | Both | Output buffer uses max drive | * | |#PIN_BM_OUTPUT_MODE | | Mask for all output mode options | * - * ### Misc Options ### + * ### Misc Options ### * | Option | Option bitmask | HW/GPIO | Description | * |-------------------|------------------|---------|----------------------------------| * |#PIN_INV_INOUT |#PIN_BM_INV_INOUT | Both | Invert input/output | @@ -577,9 +577,9 @@ extern "C" { typedef uint8_t PIN_Id; /// Pin ID used to indicate no pin -#define PIN_UNASSIGNED 0xFF +#define PIN_UNASSIGNED 0xFF /// Pin ID used to terminate a list of PIN_Id or PIN_Config entries -#define PIN_TERMINATE 0xFE +#define PIN_TERMINATE 0xFE /** @brief Pin configuration data type with embedded pin identifier * @@ -606,8 +606,7 @@ typedef uint32_t PIN_Config; * PIN_setOutputValue(hPins, PIN_ID(pinCfg), 1); * @endcode */ -#define PIN_ID(x) ((x)&0xFF) - +#define PIN_ID(x) ((x) & 0xFF) /** @anchor PIN_GENERIC_FLAGS * @name Generic PIN_Config flags/fields @@ -625,57 +624,56 @@ typedef uint32_t PIN_Config; * supplied. * \{ */ -#define PIN_GEN (((uint32_t)1) << 31) ///< Flags that generic options are used +#define PIN_GEN (((uint32_t)1) << 31) ///< Flags that generic options are used -#define PIN_INPUT_EN (PIN_GEN | (0 << 29)) ///< (*) Enable input buffer -#define PIN_INPUT_DIS (PIN_GEN | (1 << 29)) ///< Disable input buffer -#define PIN_HYSTERESIS (PIN_GEN | (1 << 30)) ///< Enable input buffer hysteresis -#define PIN_NOPULL (PIN_GEN | (0 << 13)) ///< (*) No pull-up or pull-down resistor -#define PIN_PULLUP (PIN_GEN | (1 << 13)) ///< Pull-up resistor enabled -#define PIN_PULLDOWN (PIN_GEN | (2 << 13)) ///< Pull-down resistor enabled -#define PIN_BM_INPUT_EN (1 << 29) ///< Bitmask for input enable option -#define PIN_BM_HYSTERESIS (1 << 30) ///< Bitmask input hysteresis option -#define PIN_BM_PULLING (0x3 << 13) ///< Bitmask for pull-up/pull-down options +#define PIN_INPUT_EN (PIN_GEN | (0 << 29)) ///< (*) Enable input buffer +#define PIN_INPUT_DIS (PIN_GEN | (1 << 29)) ///< Disable input buffer +#define PIN_HYSTERESIS (PIN_GEN | (1 << 30)) ///< Enable input buffer hysteresis +#define PIN_NOPULL (PIN_GEN | (0 << 13)) ///< (*) No pull-up or pull-down resistor +#define PIN_PULLUP (PIN_GEN | (1 << 13)) ///< Pull-up resistor enabled +#define PIN_PULLDOWN (PIN_GEN | (2 << 13)) ///< Pull-down resistor enabled +#define PIN_BM_INPUT_EN (1 << 29) ///< Bitmask for input enable option +#define PIN_BM_HYSTERESIS (1 << 30) ///< Bitmask input hysteresis option +#define PIN_BM_PULLING (0x3 << 13) ///< Bitmask for pull-up/pull-down options /// Bitmask for all input mode options -#define PIN_BM_INPUT_MODE (PIN_BM_INPUT_EN|PIN_BM_HYSTERESIS|PIN_BM_PULLING) +#define PIN_BM_INPUT_MODE (PIN_BM_INPUT_EN | PIN_BM_HYSTERESIS | PIN_BM_PULLING) -#define PIN_GPIO_OUTPUT_DIS (PIN_GEN | (0 << 23)) ///< (*) Disable output buffer when GPIO -#define PIN_GPIO_OUTPUT_EN (PIN_GEN | (1 << 23)) ///< Enable output buffer when GPIO -#define PIN_GPIO_LOW (PIN_GEN | (0 << 22)) ///< Output buffer drives to VSS when GPIO -#define PIN_GPIO_HIGH (PIN_GEN | (1 << 22)) ///< Output buffer drives to VDD when GPIO -#define PIN_PUSHPULL (PIN_GEN | (0 << 25)) ///< (*) Output buffer mode: push/pull -#define PIN_OPENDRAIN (PIN_GEN | (2 << 25)) ///< Output buffer mode: open drain -#define PIN_OPENSOURCE (PIN_GEN | (3 << 25)) ///< Output buffer mode: open source -#define PIN_SLEWCTRL (PIN_GEN | (1 << 12)) ///< Enable output buffer slew control -#define PIN_DRVSTR_MIN (PIN_GEN | (0x0 << 8)) ///< (*) Lowest drive strength -#define PIN_DRVSTR_MED (PIN_GEN | (0x4 << 8)) ///< Medium drive strength -#define PIN_DRVSTR_MAX (PIN_GEN | (0x8 << 8)) ///< Highest drive strength -#define PIN_BM_GPIO_OUTPUT_EN (1 << 23) ///< Bitmask for output enable option -#define PIN_BM_GPIO_OUTPUT_VAL (1 << 22) ///< Bitmask for output value option -#define PIN_BM_OUTPUT_BUF (0x3 << 25) ///< Bitmask for output buffer options -#define PIN_BM_SLEWCTRL (0x1 << 12) ///< Bitmask for slew control options -#define PIN_BM_DRVSTR (0xF << 8) ///< Bitmask for drive strength options +#define PIN_GPIO_OUTPUT_DIS (PIN_GEN | (0 << 23)) ///< (*) Disable output buffer when GPIO +#define PIN_GPIO_OUTPUT_EN (PIN_GEN | (1 << 23)) ///< Enable output buffer when GPIO +#define PIN_GPIO_LOW (PIN_GEN | (0 << 22)) ///< Output buffer drives to VSS when GPIO +#define PIN_GPIO_HIGH (PIN_GEN | (1 << 22)) ///< Output buffer drives to VDD when GPIO +#define PIN_PUSHPULL (PIN_GEN | (0 << 25)) ///< (*) Output buffer mode: push/pull +#define PIN_OPENDRAIN (PIN_GEN | (2 << 25)) ///< Output buffer mode: open drain +#define PIN_OPENSOURCE (PIN_GEN | (3 << 25)) ///< Output buffer mode: open source +#define PIN_SLEWCTRL (PIN_GEN | (1 << 12)) ///< Enable output buffer slew control +#define PIN_DRVSTR_MIN (PIN_GEN | (0x0 << 8)) ///< (*) Lowest drive strength +#define PIN_DRVSTR_MED (PIN_GEN | (0x4 << 8)) ///< Medium drive strength +#define PIN_DRVSTR_MAX (PIN_GEN | (0x8 << 8)) ///< Highest drive strength +#define PIN_BM_GPIO_OUTPUT_EN (1 << 23) ///< Bitmask for output enable option +#define PIN_BM_GPIO_OUTPUT_VAL (1 << 22) ///< Bitmask for output value option +#define PIN_BM_OUTPUT_BUF (0x3 << 25) ///< Bitmask for output buffer options +#define PIN_BM_SLEWCTRL (0x1 << 12) ///< Bitmask for slew control options +#define PIN_BM_DRVSTR (0xF << 8) ///< Bitmask for drive strength options /// Bitmask for all output mode options -#define PIN_BM_OUTPUT_MODE (PIN_BM_GPIO_OUTPUT_VAL | PIN_BM_GPIO_OUTPUT_EN | \ - PIN_BM_OUTPUT_BUF | PIN_BM_SLEWCTRL | PIN_BM_DRVSTR) +#define PIN_BM_OUTPUT_MODE (PIN_BM_GPIO_OUTPUT_VAL | PIN_BM_GPIO_OUTPUT_EN | \ + PIN_BM_OUTPUT_BUF | PIN_BM_SLEWCTRL | PIN_BM_DRVSTR) -#define PIN_INV_INOUT (PIN_GEN | (1 << 24)) ///< Logically invert input and output -#define PIN_BM_INV_INOUT (1 << 24) ///< Bitmask for input/output inversion option +#define PIN_INV_INOUT (PIN_GEN | (1 << 24)) ///< Logically invert input and output +#define PIN_BM_INV_INOUT (1 << 24) ///< Bitmask for input/output inversion option -#define PIN_IRQ_DIS (PIN_GEN | (0x0 << 16)) ///< (*) Disable IRQ on pin -#define PIN_IRQ_NEGEDGE (PIN_GEN | (0x5 << 16)) ///< Enable IRQ on negative edge -#define PIN_IRQ_POSEDGE (PIN_GEN | (0x6 << 16)) ///< Enable IRQ on positive edge -#define PIN_IRQ_BOTHEDGES (PIN_GEN | (0x7 << 16)) ///< Enable IRQ on both edges -#define PIN_BM_IRQ (0x7 << 16) ///< Bitmask for pin interrupt option +#define PIN_IRQ_DIS (PIN_GEN | (0x0 << 16)) ///< (*) Disable IRQ on pin +#define PIN_IRQ_NEGEDGE (PIN_GEN | (0x5 << 16)) ///< Enable IRQ on negative edge +#define PIN_IRQ_POSEDGE (PIN_GEN | (0x6 << 16)) ///< Enable IRQ on positive edge +#define PIN_IRQ_BOTHEDGES (PIN_GEN | (0x7 << 16)) ///< Enable IRQ on both edges +#define PIN_BM_IRQ (0x7 << 16) ///< Bitmask for pin interrupt option /// Bitmask for all options at once -#define PIN_BM_ALL (PIN_BM_INPUT_MODE | PIN_BM_OUTPUT_MODE | PIN_BM_INV_INOUT | PIN_BM_IRQ) +#define PIN_BM_ALL (PIN_BM_INPUT_MODE | PIN_BM_OUTPUT_MODE | PIN_BM_INV_INOUT | PIN_BM_IRQ) /** \} (PIN_GENERIC_FLAGS) */ - /** @brief Struct used to store PIN client state * Pointer to a PIN_State is used as handles (#PIN_Handle) in interactions with * the I/O driver @@ -684,13 +682,11 @@ typedef uint32_t PIN_Config; */ typedef struct PIN_State_s PIN_State; - /** @brief A handle that is returned from a PIN_open() call * Used for further PIN client interaction with the PIN driver */ typedef PIN_State* PIN_Handle; - /** @brief I/O Interrupt callback function pointer type * One PIN Interrupt callback can be registered by each PIN client and it * will be called when one of the pins allocated by the client has an interrupt @@ -702,27 +698,25 @@ typedef PIN_State* PIN_Handle; */ typedef void (*PIN_IntCb)(PIN_Handle handle, PIN_Id pinId); - /** @brief underlying data structure for type #PIN_State */ struct PIN_State_s { - PIN_IntCb callbackFxn; ///< Pointer to interrupt callback function - uint32_t portMask; ///< Bitmask for pins allocated in port - uintptr_t userArg; ///< User argument for whole handle - // TODO: add driver-specific field for extensions? + PIN_IntCb callbackFxn; ///< Pointer to interrupt callback function + uint32_t portMask; ///< Bitmask for pins allocated in port + uintptr_t userArg; ///< User argument for whole handle + // TODO: add driver-specific field for extensions? }; /// @brief Return value for many functions in the PIN driver interface typedef enum { - PIN_SUCCESS = 0, ///< Operation succeeded - PIN_ALREADY_ALLOCATED = 1, ///< Operation failed, some pin already allocated - PIN_NO_ACCESS = 2, ///< Operation failed, client does not have access to pin - PIN_UNSUPPORTED = 3 ///< Operation not supported + PIN_SUCCESS = 0, ///< Operation succeeded + PIN_ALREADY_ALLOCATED = 1, ///< Operation failed, some pin already allocated + PIN_NO_ACCESS = 2, ///< Operation failed, client does not have access to pin + PIN_UNSUPPORTED = 3 ///< Operation not supported } PIN_Status; - /** @brief PIN module initialization * * Must be called early in the boot sequence to ensure that I/O pins have safe @@ -740,7 +734,6 @@ typedef enum */ extern PIN_Status PIN_init(const PIN_Config aPinCfg[]); - /** @brief Allocate one or more pins for a driver or an application * * Allows a PIN client (driver or application) to allocate a set of pins, thus @@ -758,7 +751,6 @@ extern PIN_Status PIN_init(const PIN_Config aPinCfg[]); */ extern PIN_Handle PIN_open(PIN_State* state, const PIN_Config pinList[]); - /** @brief Add pin to pin set for open PIN handle * * If the requested pin is unallocated it will be added, else an error code @@ -769,7 +761,6 @@ extern PIN_Handle PIN_open(PIN_State* state, const PIN_Config pinList[]); */ extern PIN_Status PIN_add(PIN_Handle handle, PIN_Config pinCfg); - /** @brief Removes pin from pin set foropen PIN handle * * If the requested pin is allocated to handle it will be removed from the pin @@ -780,7 +771,6 @@ extern PIN_Status PIN_add(PIN_Handle handle, PIN_Config pinCfg); */ extern PIN_Status PIN_remove(PIN_Handle handle, PIN_Id pinId); - /** @brief Deallocate all pins previously allocated with a call to PIN_open(). * * Deallocate pins allocated to handle and restore these pins to the @@ -790,7 +780,6 @@ extern PIN_Status PIN_remove(PIN_Handle handle, PIN_Id pinId); */ extern void PIN_close(PIN_Handle handle); - /** @brief Sets a user argument associated with the handle * * Allows the application to store some data, for example a pointer to some @@ -806,7 +795,6 @@ static inline void PIN_setUserArg(PIN_Handle handle, uintptr_t arg) } } - /** @brief Gets a user argument associated with the handle * * Allows the application to store some data, for example a pointer to some @@ -819,7 +807,6 @@ static inline uintptr_t PIN_getUserArg(PIN_Handle handle) return handle->userArg; } - /** @name Pin Manipulation/Configuration Functions * Functions that are used to manipulate the configuration of I/O pins and to * get input values and set output values. @@ -840,7 +827,6 @@ static inline uintptr_t PIN_getUserArg(PIN_Handle handle) */ extern uint32_t PIN_getInputValue(PIN_Id pinId); - /** @brief Control output enable for GPIO pin * * @param handle Handle provided by previous call to PIN_open() @@ -859,7 +845,6 @@ extern uint32_t PIN_getInputValue(PIN_Id pinId); */ extern PIN_Status PIN_setOutputEnable(PIN_Handle handle, PIN_Id pinId, bool outputEnable); - /** @brief Control output value for GPIO pin * * @param handle Handle provided by previous call to PIN_open() @@ -875,7 +860,6 @@ extern PIN_Status PIN_setOutputEnable(PIN_Handle handle, PIN_Id pinId, bool outp */ extern PIN_Status PIN_setOutputValue(PIN_Handle handle, PIN_Id pinId, uint32_t val); - /** @brief Get value of GPIO pin output buffer * * Output values of all pins are available to everyone so no handle required @@ -890,7 +874,6 @@ extern PIN_Status PIN_setOutputValue(PIN_Handle handle, PIN_Id pinId, uint32_t v */ extern uint32_t PIN_getOutputValue(PIN_Id pinId); - /** @brief Control interrupt enable and edge for pin * * @param handle Handle provided by previous call to PIN_open() @@ -910,7 +893,6 @@ extern uint32_t PIN_getOutputValue(PIN_Id pinId); */ extern PIN_Status PIN_setInterrupt(PIN_Handle handle, PIN_Config pinCfg); - /** @brief Clear pending interrupt for pin, if any * * @param handle Handle provided by previous call to PIN_open() @@ -923,7 +905,6 @@ extern PIN_Status PIN_setInterrupt(PIN_Handle handle, PIN_Config pinCfg); */ extern PIN_Status PIN_clrPendInterrupt(PIN_Handle handle, PIN_Id pinId); - /** @brief Register callback function for a set of pins * * Registers a callback function (see #PIN_IntCb for details) for the client @@ -946,8 +927,6 @@ extern PIN_Status PIN_clrPendInterrupt(PIN_Handle handle, PIN_Id pinId); */ extern PIN_Status PIN_registerIntCb(PIN_Handle handle, PIN_IntCb callbackFxn); - - /** @brief Returns pin configuration * * @param pinId Pin ID @@ -969,7 +948,6 @@ extern PIN_Status PIN_registerIntCb(PIN_Handle handle, PIN_IntCb callbackFxn); */ extern PIN_Config PIN_getConfig(PIN_Id pinId); - /** @brief Sets complete pin configuration * * @param handle Handle provided by previous call to PIN_open() @@ -985,11 +963,9 @@ extern PIN_Config PIN_getConfig(PIN_Id pinId); */ extern PIN_Status PIN_setConfig(PIN_Handle handle, PIN_Config updateMask, PIN_Config pinCfg); - /** \} (IO Manipulation/Configuration Functions) */ - /** @name IO Port Functions * Functions used to get input values for, set ouput values for and set output * enables for multiple pins at a time. The size of so-called I/O ports that @@ -999,7 +975,6 @@ extern PIN_Status PIN_setConfig(PIN_Handle handle, PIN_Config updateMask, PIN_Co * \{ */ - /** @brief Returns bitmask indicating pins allocated to client in GPIO port * * @param handle Handle provided by previous call to PIN_open() @@ -1010,7 +985,6 @@ extern PIN_Status PIN_setConfig(PIN_Handle handle, PIN_Config updateMask, PIN_Co */ extern uint32_t PIN_getPortMask(PIN_Handle handle); - /** @brief Read input value of whole GPIO port * * @param handle Handle provided by previous call to PIN_open() @@ -1022,7 +996,6 @@ extern uint32_t PIN_getPortMask(PIN_Handle handle); */ extern uint32_t PIN_getPortInputValue(PIN_Handle handle); - /** @brief Returns value of whole GPIO port's output buffers * * The I/O port is identified by the pins allocated by client in a previous @@ -1035,7 +1008,6 @@ extern uint32_t PIN_getPortInputValue(PIN_Handle handle); */ extern uint32_t PIN_getPortOutputValue(PIN_Handle handle); - /** @brief Simultaneous write output buffer values of all allocated pins in GPIO port * * @param handle Handle provided by previous call to PIN_open() @@ -1054,7 +1026,6 @@ extern uint32_t PIN_getPortOutputValue(PIN_Handle handle); */ extern PIN_Status PIN_setPortOutputValue(PIN_Handle handle, uint32_t outputValueMask); - /** @brief Set output enable for all pins allocated to client in GPIO port * * @param handle Handle provided by previous call to PIN_open() @@ -1074,7 +1045,6 @@ extern PIN_Status PIN_setPortOutputValue(PIN_Handle handle, uint32_t outputValue */ extern PIN_Status PIN_setPortOutputEnable(PIN_Handle handle, uint32_t outputEnableMask); - /** \} (IO Port Functions) */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/PWM.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/PWM.h index a832966..53aaf7c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/PWM.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/PWM.h @@ -208,12 +208,11 @@ extern "C" { #endif - /*! * @brief Maximum duty (100%) when configuring duty cycle as a fraction of * period. */ -#define PWM_DUTY_FRACTION_MAX ((uint32_t) ~0) +#define PWM_DUTY_FRACTION_MAX ((uint32_t)~0) /*! * Common PWM_control command code reservation offset. @@ -226,7 +225,7 @@ extern "C" { * #define PWMXYZ_COMMAND1 (PWM_CMD_RESERVED + 1) * @endcode */ -#define PWM_CMD_RESERVED (32) +#define PWM_CMD_RESERVED (32) /*! * Common PWM_control status code reservation offset. @@ -240,7 +239,7 @@ extern "C" { * #define PWMXYZ_STATUS_ERROR2 (PWM_STATUS_RESERVED - 2) * @endcode */ -#define PWM_STATUS_RESERVED (-32) +#define PWM_STATUS_RESERVED (-32) /*! * @brief Success status code returned by: @@ -249,7 +248,7 @@ extern "C" { * Functions return #PWM_STATUS_SUCCESS if the call was executed * successfully. */ -#define PWM_STATUS_SUCCESS (0) +#define PWM_STATUS_SUCCESS (0) /*! * @brief Generic error status code returned by #PWM_control(). @@ -257,7 +256,7 @@ extern "C" { * #PWM_control() returns #PWM_STATUS_ERROR if the control code was not executed * successfully. */ -#define PWM_STATUS_ERROR (-1) +#define PWM_STATUS_ERROR (-1) /*! * @brief An error status code returned by #PWM_control() for undefined @@ -266,7 +265,7 @@ extern "C" { * #PWM_control() returns #PWM_STATUS_UNDEFINEDCMD if the control code is not * recognized by the driver implementation. */ -#define PWM_STATUS_UNDEFINEDCMD (-2) +#define PWM_STATUS_UNDEFINEDCMD (-2) /*! * @brief An error status code returned by #PWM_setPeriod(). @@ -274,7 +273,7 @@ extern "C" { * #PWM_setPeriod() returns #PWM_STATUS_INVALID_PERIOD if the period argument is * invalid for the current configuration. */ -#define PWM_STATUS_INVALID_PERIOD (-3) +#define PWM_STATUS_INVALID_PERIOD (-3) /*! * @brief An error status code returned by #PWM_setDuty(). @@ -282,7 +281,7 @@ extern "C" { * #PWM_setDuty() returns #PWM_STATUS_INVALID_DUTY if the duty cycle argument is * invalid for the current configuration. */ -#define PWM_STATUS_INVALID_DUTY (-4) +#define PWM_STATUS_INVALID_DUTY (-4) /*! * @brief PWM period unit definitions. Refer to device specific @@ -315,7 +314,7 @@ typedef enum */ typedef enum { - PWM_IDLE_LOW = 0, + PWM_IDLE_LOW = 0, PWM_IDLE_HIGH = 1, } PWM_IdleLevel; @@ -329,13 +328,13 @@ typedef enum */ typedef struct { - PWM_Period_Units periodUnits; /*!< Units in which the period is specified */ - uint32_t periodValue; /*!< PWM initial period */ - PWM_Duty_Units dutyUnits; /*!< Units in which the duty is specified */ - uint32_t dutyValue; /*!< PWM initial duty */ - PWM_IdleLevel idleLevel; /*!< Pin output when PWM is stopped. */ - void* custom; /*!< Custom argument used by driver - implementation */ + PWM_Period_Units periodUnits; /*!< Units in which the period is specified */ + uint32_t periodValue; /*!< PWM initial period */ + PWM_Duty_Units dutyUnits; /*!< Units in which the duty is specified */ + uint32_t dutyValue; /*!< PWM initial duty */ + PWM_IdleLevel idleLevel; /*!< Pin output when PWM is stopped. */ + void* custom; /*!< Custom argument used by driver + implementation */ } PWM_Params; /*! @@ -347,58 +346,58 @@ typedef struct PWM_Config_* PWM_Handle; * @brief A function pointer to a driver specific implementation of * PWM_close(). */ -typedef void (*PWM_CloseFxn) (PWM_Handle handle); +typedef void (*PWM_CloseFxn)(PWM_Handle handle); /*! * @brief A function pointer to a driver specific implementation of * PWM_control(). */ -typedef int_fast16_t (*PWM_ControlFxn) (PWM_Handle handle, uint_fast16_t cmd, - void* arg); +typedef int_fast16_t (*PWM_ControlFxn)(PWM_Handle handle, uint_fast16_t cmd, + void* arg); /*! * @brief A function pointer to a driver specific implementation of * PWM_init(). */ -typedef void (*PWM_InitFxn) (PWM_Handle handle); +typedef void (*PWM_InitFxn)(PWM_Handle handle); /*! * @brief A function pointer to a driver specific implementation of * PWM_open(). */ -typedef PWM_Handle (*PWM_OpenFxn) (PWM_Handle handle, PWM_Params* params); +typedef PWM_Handle (*PWM_OpenFxn)(PWM_Handle handle, PWM_Params* params); /*! * @brief A function pointer to a driver specific implementation of * PWM_setDuty(). */ -typedef int_fast16_t (*PWM_SetDutyFxn) (PWM_Handle handle, - uint32_t duty); +typedef int_fast16_t (*PWM_SetDutyFxn)(PWM_Handle handle, + uint32_t duty); /*! * @brief A function pointer to a driver specific implementation of * PWM_setPeriod(). */ -typedef int_fast16_t (*PWM_SetPeriodFxn) (PWM_Handle handle, - uint32_t period); +typedef int_fast16_t (*PWM_SetPeriodFxn)(PWM_Handle handle, + uint32_t period); /*! * @brief A function pointer to a driver specific implementation of * PWM_setDutyAndPeriod(). */ -typedef int_fast16_t (*PWM_SetDutyAndPeriodFxn) (PWM_Handle handle, - uint32_t duty, uint32_t period); +typedef int_fast16_t (*PWM_SetDutyAndPeriodFxn)(PWM_Handle handle, + uint32_t duty, uint32_t period); /*! * @brief A function pointer to a driver specific implementation of * PWM_start(). */ -typedef void (*PWM_StartFxn) (PWM_Handle handle); +typedef void (*PWM_StartFxn)(PWM_Handle handle); /*! * @brief A function pointer to a driver specific implementation of * PWM_stop(). */ -typedef void (*PWM_StopFxn) (PWM_Handle handle); +typedef void (*PWM_StopFxn)(PWM_Handle handle); /*! * @brief The definition of a PWM function table that contains the @@ -407,24 +406,24 @@ typedef void (*PWM_StopFxn) (PWM_Handle handle); */ typedef struct PWM_FxnTable_ { - /*! Function to close the specified instance */ - PWM_CloseFxn closeFxn; - /*! Function to driver implementation specific control function */ - PWM_ControlFxn controlFxn; - /*! Function to initialize the given data object */ - PWM_InitFxn initFxn; - /*! Function to open the specified instance */ - PWM_OpenFxn openFxn; - /*! Function to set the duty cycle for a specific instance */ - PWM_SetDutyFxn setDutyFxn; - /*! Function to set the period for a specific instance */ - PWM_SetPeriodFxn setPeriodFxn; - /*! Function to set the duty and the period for a specific instance */ - PWM_SetDutyAndPeriodFxn setDutyAndPeriodFxn; - /*! Function to start the PWM output for a specific instance */ - PWM_StartFxn startFxn; - /*! Function to stop the PWM output for a specific instance */ - PWM_StopFxn stopFxn; + /*! Function to close the specified instance */ + PWM_CloseFxn closeFxn; + /*! Function to driver implementation specific control function */ + PWM_ControlFxn controlFxn; + /*! Function to initialize the given data object */ + PWM_InitFxn initFxn; + /*! Function to open the specified instance */ + PWM_OpenFxn openFxn; + /*! Function to set the duty cycle for a specific instance */ + PWM_SetDutyFxn setDutyFxn; + /*! Function to set the period for a specific instance */ + PWM_SetPeriodFxn setPeriodFxn; + /*! Function to set the duty and the period for a specific instance */ + PWM_SetDutyAndPeriodFxn setDutyAndPeriodFxn; + /*! Function to start the PWM output for a specific instance */ + PWM_StartFxn startFxn; + /*! Function to stop the PWM output for a specific instance */ + PWM_StopFxn stopFxn; } PWM_FxnTable; /*! @@ -436,12 +435,12 @@ typedef struct PWM_FxnTable_ */ typedef struct PWM_Config_ { - /*! Pointer to a table of driver-specific implementations of PWM APIs */ - PWM_FxnTable const* fxnTablePtr; - /*! Pointer to a driver specific data object */ - void* object; - /*! Pointer to a driver specific hardware attributes structure */ - void const* hwAttrs; + /*! Pointer to a table of driver-specific implementations of PWM APIs */ + PWM_FxnTable const* fxnTablePtr; + /*! Pointer to a driver specific data object */ + void* object; + /*! Pointer to a driver specific hardware attributes structure */ + void const* hwAttrs; } PWM_Config; /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/Power.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/Power.h index cde0060..3c3e679 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/Power.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/Power.h @@ -364,36 +364,36 @@ extern "C" { /*! @addtogroup Power_Latency_Type * @{ */ -#define Power_TOTAL (1U) /*!< total latency */ -#define Power_RESUME (2U) /*!< resume latency */ +#define Power_TOTAL (1U) /*!< total latency */ +#define Power_RESUME (2U) /*!< resume latency */ /*! @}*/ /*! @addtogroup Power_Notify_Response * @{ */ -#define Power_NOTIFYDONE (0) /*!< OK, notify completed */ -#define Power_NOTIFYERROR (-1) /*!< an error occurred during notify */ +#define Power_NOTIFYDONE (0) /*!< OK, notify completed */ +#define Power_NOTIFYERROR (-1) /*!< an error occurred during notify */ /*! @}*/ /*! @addtogroup Power_Status * @{ */ -#define Power_SOK (0) /*!< OK, operation succeeded */ -#define Power_EFAIL (-1) /*!< general failure */ -#define Power_EINVALIDINPUT (-2) /*!< invalid data value */ -#define Power_EINVALIDPOINTER (-3) /*!< invalid pointer */ -#define Power_ECHANGE_NOT_ALLOWED (-4) /*!< change is not allowed */ -#define Power_EBUSY (-5) /*!< busy with another transition */ +#define Power_SOK (0) /*!< OK, operation succeeded */ +#define Power_EFAIL (-1) /*!< general failure */ +#define Power_EINVALIDINPUT (-2) /*!< invalid data value */ +#define Power_EINVALIDPOINTER (-3) /*!< invalid pointer */ +#define Power_ECHANGE_NOT_ALLOWED (-4) /*!< change is not allowed */ +#define Power_EBUSY (-5) /*!< busy with another transition */ /*! @}*/ /*! @addtogroup Power_Transition_State * @{ */ -#define Power_ACTIVE (1U) /*!< normal active state */ -#define Power_ENTERING_SLEEP (2U) /*!< entering a sleep state */ -#define Power_EXITING_SLEEP (3U) /*!< exiting a sleep state */ -#define Power_ENTERING_SHUTDOWN (4U) /*!< entering a shutdown state */ -#define Power_CHANGING_PERF_LEVEL (5U) /*!< moving to new performance level */ +#define Power_ACTIVE (1U) /*!< normal active state */ +#define Power_ENTERING_SLEEP (2U) /*!< entering a sleep state */ +#define Power_EXITING_SLEEP (3U) /*!< exiting a sleep state */ +#define Power_ENTERING_SHUTDOWN (4U) /*!< entering a shutdown state */ +#define Power_CHANGING_PERF_LEVEL (5U) /*!< moving to new performance level */ /*! @}*/ /*! @@ -442,10 +442,10 @@ typedef int_fast16_t (*Power_NotifyFxn)(uint_fast16_t eventType, */ typedef struct { - List_Elem link; /*!< for placing on the notify list */ - uint_fast16_t eventTypes; /*!< the event type */ - Power_NotifyFxn notifyFxn; /*!< notification function */ - uintptr_t clientArg; /*!< argument provided by client */ + List_Elem link; /*!< for placing on the notify list */ + uint_fast16_t eventTypes; /*!< the event type */ + Power_NotifyFxn notifyFxn; /*!< notification function */ + uintptr_t clientArg; /*!< argument provided by client */ } Power_NotifyObj; /*! @@ -574,7 +574,7 @@ uint_fast16_t Power_getPerformanceLevel(void); * @sa @ref ti_drivers_Power_Examples_transistion "Power transitions" */ uint_fast32_t Power_getTransitionLatency(uint_fast16_t sleepState, - uint_fast16_t type); + uint_fast16_t type); /*! * @brief Get the current transition state of the Power Manager diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SD.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SD.h index 057499f..03dd46f 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SD.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SD.h @@ -128,7 +128,7 @@ extern "C" { * #define SDXYZ_CMD_COMMAND1 (SD_CMD_RESERVED + 1) * @endcode */ -#define SD_CMD_RESERVED (32) +#define SD_CMD_RESERVED (32) /*! * Common SD_control status code reservation offset. @@ -142,7 +142,7 @@ extern "C" { * #define SDXYZ_STATUS_ERROR2 (SD_STATUS_RESERVED - 2) * @endcode */ -#define SD_STATUS_RESERVED (-32) +#define SD_STATUS_RESERVED (-32) /** * @defgroup SD_STATUS Status Codes @@ -157,7 +157,7 @@ extern "C" { * SD_control() returns SD_STATUS_SUCCESS if the control code was executed * successfully. */ -#define SD_STATUS_SUCCESS (0) +#define SD_STATUS_SUCCESS (0) /*! * @brief Generic error status code returned by SD_control(). @@ -165,7 +165,7 @@ extern "C" { * SD_control() returns SD_STATUS_ERROR if the control code * was not executed successfully. */ -#define SD_STATUS_ERROR (-1) +#define SD_STATUS_ERROR (-1) /*! * @brief An error status code returned by SD_control() for @@ -174,7 +174,7 @@ extern "C" { * SD_control() returns SD_STATUS_UNDEFINEDCMD if the * control code is not recognized by the driver implementation. */ -#define SD_STATUS_UNDEFINEDCMD (-2) +#define SD_STATUS_UNDEFINEDCMD (-2) /** @}*/ /** @@ -219,65 +219,65 @@ typedef struct SD_Config_* SD_Handle; /* SD Parameters */ typedef struct SD_Params_ { - void* custom; /*!< Custom argument used by driver implementation */ + void* custom; /*!< Custom argument used by driver implementation */ } SD_Params; /*! * @brief A function pointer to a driver specific implementation of * SD_CloseFxn(). */ -typedef void (*SD_CloseFxn) (SD_Handle handle); +typedef void (*SD_CloseFxn)(SD_Handle handle); /*! * @brief A function pointer to a driver specific implementation of * SD_controlFxn(). */ -typedef int_fast16_t (*SD_ControlFxn) (SD_Handle handle, - uint_fast16_t cmd, void* arg); +typedef int_fast16_t (*SD_ControlFxn)(SD_Handle handle, + uint_fast16_t cmd, void* arg); /*! * @brief A function pointer to a driver specific implementation of * SD_getNumSectorsFxn(). */ -typedef uint_fast32_t (*SD_getNumSectorsFxn) (SD_Handle handle); +typedef uint_fast32_t (*SD_getNumSectorsFxn)(SD_Handle handle); /*! * @brief A function pointer to a driver specific implementation of * SD_getSectorSizeFxn(). */ -typedef uint_fast32_t (*SD_getSectorSizeFxn) (SD_Handle handle); +typedef uint_fast32_t (*SD_getSectorSizeFxn)(SD_Handle handle); /*! * @brief A function pointer to a driver specific implementation of * SD_InitFxn(). */ -typedef void (*SD_InitFxn) (SD_Handle handle); +typedef void (*SD_InitFxn)(SD_Handle handle); /*! * @brief A function pointer to a driver specific implementation of * SD_initializeFxn(). */ -typedef int_fast16_t (*SD_InitializeFxn) (SD_Handle handle); +typedef int_fast16_t (*SD_InitializeFxn)(SD_Handle handle); /*! * @brief A function pointer to a driver specific implementation of * SD_OpenFxn(). */ -typedef SD_Handle (*SD_OpenFxn) (SD_Handle handle, SD_Params* params); +typedef SD_Handle (*SD_OpenFxn)(SD_Handle handle, SD_Params* params); /*! * @brief A function pointer to a driver specific implementation of * SD_readFxn(). */ -typedef int_fast16_t (*SD_ReadFxn) (SD_Handle handle, void* buf, - int_fast32_t sector, uint_fast32_t secCount); +typedef int_fast16_t (*SD_ReadFxn)(SD_Handle handle, void* buf, + int_fast32_t sector, uint_fast32_t secCount); /*! * @brief A function pointer to a driver specific implementation of * SD_writeFxn(). */ -typedef int_fast16_t (*SD_WriteFxn) (SD_Handle handle, const void* buf, - int_fast32_t sector, uint_fast32_t secCount); +typedef int_fast16_t (*SD_WriteFxn)(SD_Handle handle, const void* buf, + int_fast32_t sector, uint_fast32_t secCount); /*! * @brief The definition of a SD function table that contains the @@ -286,24 +286,24 @@ typedef int_fast16_t (*SD_WriteFxn) (SD_Handle handle, const void* buf, */ typedef struct SD_FxnTable_ { - /*! Function to close the specified peripheral */ - SD_CloseFxn closeFxn; - /*! Function to implementation specific control function */ - SD_ControlFxn controlFxn; - /*! Function to return the total number of sectors on the SD card */ - SD_getNumSectorsFxn getNumSectorsFxn; - /*! Function to return the sector size used to address the SD card */ - SD_getSectorSizeFxn getSectorSizeFxn; - /*! Function to initialize the given data object */ - SD_InitFxn initFxn; - /*! Function to initialize the SD card */ - SD_InitializeFxn initializeFxn; - /*! Function to open the specified peripheral */ - SD_OpenFxn openFxn; - /*! Function to read from the SD card */ - SD_ReadFxn readFxn; - /*! Function to write to the SD card */ - SD_WriteFxn writeFxn; + /*! Function to close the specified peripheral */ + SD_CloseFxn closeFxn; + /*! Function to implementation specific control function */ + SD_ControlFxn controlFxn; + /*! Function to return the total number of sectors on the SD card */ + SD_getNumSectorsFxn getNumSectorsFxn; + /*! Function to return the sector size used to address the SD card */ + SD_getSectorSizeFxn getSectorSizeFxn; + /*! Function to initialize the given data object */ + SD_InitFxn initFxn; + /*! Function to initialize the SD card */ + SD_InitializeFxn initializeFxn; + /*! Function to open the specified peripheral */ + SD_OpenFxn openFxn; + /*! Function to read from the SD card */ + SD_ReadFxn readFxn; + /*! Function to write to the SD card */ + SD_WriteFxn writeFxn; } SD_FxnTable; /*! @@ -319,14 +319,14 @@ typedef struct SD_FxnTable_ */ typedef struct SD_Config_ { - /*! Pointer to a table of driver-specific implementations of SD APIs */ - SD_FxnTable const* fxnTablePtr; + /*! Pointer to a table of driver-specific implementations of SD APIs */ + SD_FxnTable const* fxnTablePtr; - /*! Pointer to a driver specific data object */ - void* object; + /*! Pointer to a driver specific data object */ + void* object; - /*! Pointer to a driver specific hardware attributes structure */ - void const* hwAttrs; + /*! Pointer to a driver specific hardware attributes structure */ + void const* hwAttrs; } SD_Config; /*! @@ -427,16 +427,16 @@ extern void SD_init(void); extern void SD_Params_init(SD_Params* params); /*! -* @brief A function pointer to a driver specific implementation of -* SD_initialize(). -* -* @pre SD controller has been opened by calling SD_open(). -* -* @param handle A #SD_Handle returned from SD_open(). -* -* @return #SD_STATUS_SUCCESS if no errors occurred during the initialization, -* #SD_STATUS_ERROR otherwise. -*/ + * @brief A function pointer to a driver specific implementation of + * SD_initialize(). + * + * @pre SD controller has been opened by calling SD_open(). + * + * @param handle A #SD_Handle returned from SD_open(). + * + * @return #SD_STATUS_SUCCESS if no errors occurred during the initialization, + * #SD_STATUS_ERROR otherwise. + */ extern int_fast16_t SD_initialize(SD_Handle handle); /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SDFatFS.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SDFatFS.h index 14e49cb..d7d2063 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SDFatFS.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SDFatFS.h @@ -91,8 +91,8 @@ extern "C" { #include -#include #include +#include /*! * @brief SDFatFS Object @@ -100,17 +100,16 @@ extern "C" { */ typedef struct SDFatFS_Object_ { - uint_fast32_t driveNum; - DSTATUS diskState; - FATFS filesystem; /* FATFS data object */ - SD_Handle sdHandle; + uint_fast32_t driveNum; + DSTATUS diskState; + FATFS filesystem; /* FATFS data object */ + SD_Handle sdHandle; } SDFatFS_Object; /*! * @brief A handle that is returned from a SDFatFS_open() call. */ -typedef struct SDFatFS_Config_* SDFatFS_Handle; - +typedef struct SDFatFS_Config_* SDFatFS_Handle; /*! * @brief SDFatFS Global configuration @@ -125,8 +124,8 @@ typedef struct SDFatFS_Config_* SDFatFS_Handle; */ typedef struct SDFatFS_Config_ { - /*! Pointer to a SDFatFS object */ - void* object; + /*! Pointer to a SDFatFS object */ + void* object; } SDFatFS_Config; /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SHA2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SHA2.h index 2251f53..acfd5d7 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SHA2.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SHA2.h @@ -227,7 +227,7 @@ extern "C" { * #define SHA2XYZ_STATUS_ERROR2 SHA2_STATUS_RESERVED - 2 * @endcode */ -#define SHA2_STATUS_RESERVED (-32) +#define SHA2_STATUS_RESERVED (-32) /*! * @brief Successful status code. @@ -235,7 +235,7 @@ extern "C" { * Functions return SHA2_STATUS_SUCCESS if the function was executed * successfully. */ -#define SHA2_STATUS_SUCCESS (0) +#define SHA2_STATUS_SUCCESS (0) /*! * @brief Generic error status code. @@ -243,7 +243,7 @@ extern "C" { * Functions return SHA2_STATUS_ERROR if the function was not executed * successfully and no more specific error is applicable. */ -#define SHA2_STATUS_ERROR (-1) +#define SHA2_STATUS_ERROR (-1) /*! * @brief An error status code returned if the hardware or software resource @@ -283,20 +283,20 @@ extern "C" { */ typedef enum { - SHA2_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the - * SHA2 operation goes on in the background. The registered - * callback function is called after the operation completes. - * The context the callback function is called (task, HWI, SWI) - * is implementation-dependent. - */ - SHA2_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while the SHA2 operation goes - * on in the background. SHA2 operation results are available - * after the function returns. - */ - SHA2_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while the SHA2 - * operation goes on in the background. SHA2 operation results - * are available after the function returns. - */ + SHA2_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * SHA2 operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + SHA2_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while the SHA2 operation goes + * on in the background. SHA2 operation results are available + * after the function returns. + */ + SHA2_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while the SHA2 + * operation goes on in the background. SHA2 operation results + * are available after the function returns. + */ } SHA2_ReturnBehavior; /*! @@ -355,11 +355,11 @@ typedef enum */ typedef struct SHA2_Config { - /*! Pointer to a driver specific data object */ - void* object; + /*! Pointer to a driver specific data object */ + void* object; - /*! Pointer to a driver specific hardware attributes structure */ - void const* hwAttrs; + /*! Pointer to a driver specific hardware attributes structure */ + void const* hwAttrs; } SHA2_Config; /*! @@ -377,7 +377,7 @@ typedef SHA2_Config* SHA2_Handle; * Informs the application of why the callback function was * called. */ -typedef void (*SHA2_CallbackFxn) (SHA2_Handle handle, int_fast16_t returnStatus); +typedef void (*SHA2_CallbackFxn)(SHA2_Handle handle, int_fast16_t returnStatus); /*! * @brief SHA2 Parameters @@ -389,14 +389,14 @@ typedef void (*SHA2_CallbackFxn) (SHA2_Handle handle, int_fast16_t returnStatus) */ typedef struct { - SHA2_HashType hashType; /*!< SHA2 variant to use. This determines the output digest - * length. - */ - SHA2_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ - SHA2_CallbackFxn callbackFxn; /*!< Callback function pointer */ - uint32_t timeout; /*!< Timeout before the driver returns an error in - * ::SHA2_RETURN_BEHAVIOR_BLOCKING - */ + SHA2_HashType hashType; /*!< SHA2 variant to use. This determines the output digest + * length. + */ + SHA2_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + SHA2_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::SHA2_RETURN_BEHAVIOR_BLOCKING + */ } SHA2_Params; /*! @@ -425,7 +425,6 @@ extern const uint_least8_t SHA2_count; */ extern const SHA2_Params SHA2_defaultParams; - /*! * @brief Initializes the SHA2 driver module. * @@ -610,7 +609,6 @@ int_fast16_t SHA2_cancelOperation(SHA2_Handle handle); */ int_fast16_t SHA2_setHashType(SHA2_Handle handle, SHA2_HashType type); - #ifdef __cplusplus } #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SPI.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SPI.h index c72c817..1eef801 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SPI.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/SPI.h @@ -464,7 +464,7 @@ extern "C" { * #define SPIXYZ_CMD_COMMAND1 SPI_CMD_RESERVED + 1 * @endcode */ -#define SPI_CMD_RESERVED (32) +#define SPI_CMD_RESERVED (32) /*! * Common SPI_control status code reservation offset. @@ -478,7 +478,7 @@ extern "C" { * #define SPIXYZ_STATUS_ERROR2 SPI_STATUS_RESERVED - 2 * @endcode */ -#define SPI_STATUS_RESERVED (-32) +#define SPI_STATUS_RESERVED (-32) /** * @defgroup SPI_STATUS Status Codes @@ -493,7 +493,7 @@ extern "C" { * This value is returned from SPI_control() if the control code was executed * successfully. */ -#define SPI_STATUS_SUCCESS (0) +#define SPI_STATUS_SUCCESS (0) /*! * @brief Generic error status code returned by SPI_control(). @@ -501,7 +501,7 @@ extern "C" { * This value is returned from SPI_control() if the control code was not * executed successfully. */ -#define SPI_STATUS_ERROR (-1) +#define SPI_STATUS_ERROR (-1) /*! * @brief An error status code returned by SPI_control() for undefined @@ -510,7 +510,7 @@ extern "C" { * This value is returned from SPI_control() if the control code is not * recognized by the driver implementation. */ -#define SPI_STATUS_UNDEFINEDCMD (-2) +#define SPI_STATUS_UNDEFINEDCMD (-2) /** @}*/ /** @@ -530,27 +530,27 @@ extern "C" { /*! * @brief Wait forever define used to specify timeouts. */ -#define SPI_WAIT_FOREVER (~(0U)) +#define SPI_WAIT_FOREVER (~(0U)) /*! * @brief A handle that is returned from a SPI_open() call. */ -typedef struct SPI_Config_* SPI_Handle; +typedef struct SPI_Config_* SPI_Handle; /*! * @brief Status codes that are set by the SPI driver. */ typedef enum { - SPI_TRANSFER_COMPLETED = 0, /*!< SPI transfer completed */ - SPI_TRANSFER_STARTED, /*!< SPI transfer started and in progress */ - SPI_TRANSFER_CANCELED, /*!< SPI transfer was canceled */ - SPI_TRANSFER_FAILED, /*!< SPI transfer failed */ - SPI_TRANSFER_CSN_DEASSERT, /*!< SPI chip select was de-asserted (only - applicable in return partial mode) */ - SPI_TRANSFER_PEND_CSN_ASSERT, /*!< SPI transfer is pending until the chip - select is asserted */ - SPI_TRANSFER_QUEUED /*!< SPI transfer added to transaction queue */ + SPI_TRANSFER_COMPLETED = 0, /*!< SPI transfer completed */ + SPI_TRANSFER_STARTED, /*!< SPI transfer started and in progress */ + SPI_TRANSFER_CANCELED, /*!< SPI transfer was canceled */ + SPI_TRANSFER_FAILED, /*!< SPI transfer failed */ + SPI_TRANSFER_CSN_DEASSERT, /*!< SPI chip select was de-asserted (only + applicable in return partial mode) */ + SPI_TRANSFER_PEND_CSN_ASSERT, /*!< SPI transfer is pending until the chip + select is asserted */ + SPI_TRANSFER_QUEUED /*!< SPI transfer added to transaction queue */ } SPI_Status; /*! @@ -563,17 +563,17 @@ typedef enum */ typedef struct { - /* User input (write-only) fields */ - size_t count; /*!< Number of frames for this transaction */ - void* txBuf; /*!< void * to a buffer with data to be transmitted */ - void* rxBuf; /*!< void * to a buffer to receive data */ - void* arg; /*!< Argument to be passed to the callback function */ + /* User input (write-only) fields */ + size_t count; /*!< Number of frames for this transaction */ + void* txBuf; /*!< void * to a buffer with data to be transmitted */ + void* rxBuf; /*!< void * to a buffer to receive data */ + void* arg; /*!< Argument to be passed to the callback function */ - /* User output (read-only) fields */ - SPI_Status status; /*!< #SPI_Status code set by SPI_transfer */ + /* User output (read-only) fields */ + SPI_Status status; /*!< #SPI_Status code set by SPI_transfer */ - void* nextPtr; /*!< Field used internally by the driver and must - never be accessed by the application. */ + void* nextPtr; /*!< Field used internally by the driver and must + never be accessed by the application. */ } SPI_Transaction; /*! @@ -583,16 +583,16 @@ typedef struct * @param SPI_Handle A #SPI_Handle * @param SPI_Transaction* Pointer to a #SPI_Transaction */ -typedef void (*SPI_CallbackFxn) (SPI_Handle handle, - SPI_Transaction* transaction); +typedef void (*SPI_CallbackFxn)(SPI_Handle handle, + SPI_Transaction* transaction); /*! * @brief * Definitions for various SPI modes of operation. */ typedef enum { - SPI_MASTER = 0, /*!< SPI in master mode */ - SPI_SLAVE = 1 /*!< SPI in slave mode */ + SPI_MASTER = 0, /*!< SPI in master mode */ + SPI_SLAVE = 1 /*!< SPI in slave mode */ } SPI_Mode; /*! @@ -601,14 +601,14 @@ typedef enum */ typedef enum { - SPI_POL0_PHA0 = 0, /*!< SPI mode Polarity 0 Phase 0 */ - SPI_POL0_PHA1 = 1, /*!< SPI mode Polarity 0 Phase 1 */ - SPI_POL1_PHA0 = 2, /*!< SPI mode Polarity 1 Phase 0 */ - SPI_POL1_PHA1 = 3, /*!< SPI mode Polarity 1 Phase 1 */ - SPI_TI = 4, /*!< TI mode (not supported on all - implementations) */ - SPI_MW = 5 /*!< Micro-wire mode (not supported on all - implementations) */ + SPI_POL0_PHA0 = 0, /*!< SPI mode Polarity 0 Phase 0 */ + SPI_POL0_PHA1 = 1, /*!< SPI mode Polarity 0 Phase 1 */ + SPI_POL1_PHA0 = 2, /*!< SPI mode Polarity 1 Phase 0 */ + SPI_POL1_PHA1 = 3, /*!< SPI mode Polarity 1 Phase 1 */ + SPI_TI = 4, /*!< TI mode (not supported on all + implementations) */ + SPI_MW = 5 /*!< Micro-wire mode (not supported on all + implementations) */ } SPI_FrameFormat; /*! @@ -646,68 +646,68 @@ typedef enum */ typedef struct { - SPI_TransferMode transferMode; /*!< Blocking or Callback mode */ - uint32_t transferTimeout; /*!< Transfer timeout in system - ticks */ - SPI_CallbackFxn transferCallbackFxn;/*!< Callback function pointer */ - SPI_Mode mode; /*!< Master or Slave mode */ - /*! @brief SPI bit rate in Hz - * - * Maximum bit rates supported by hardware: - * Device Family | Slave Max (MHz) | Master Max (MHz) | - * ------------- | ------------------ | ---------------- | - * MSP432P4 | 16 MHz | 24 MHz | - * MSP432E4 | 10 MHz | 60 MHz | - * CC13XX/CC26XX | 4 MHz | 12 MHz | - * CC32XX | 20 MHz | 20 MHz | - * - * Please note that depending on the specific use case, the driver may not - * support the hardware's maximum bit rate. - */ - uint32_t bitRate; - uint32_t dataSize; /*!< SPI data frame size in bits */ - SPI_FrameFormat frameFormat; /*!< SPI frame format */ - void* custom; /*!< Custom argument used by driver - implementation */ + SPI_TransferMode transferMode; /*!< Blocking or Callback mode */ + uint32_t transferTimeout; /*!< Transfer timeout in system + ticks */ + SPI_CallbackFxn transferCallbackFxn; /*!< Callback function pointer */ + SPI_Mode mode; /*!< Master or Slave mode */ + /*! @brief SPI bit rate in Hz + * + * Maximum bit rates supported by hardware: + * Device Family | Slave Max (MHz) | Master Max (MHz) | + * ------------- | ------------------ | ---------------- | + * MSP432P4 | 16 MHz | 24 MHz | + * MSP432E4 | 10 MHz | 60 MHz | + * CC13XX/CC26XX | 4 MHz | 12 MHz | + * CC32XX | 20 MHz | 20 MHz | + * + * Please note that depending on the specific use case, the driver may not + * support the hardware's maximum bit rate. + */ + uint32_t bitRate; + uint32_t dataSize; /*!< SPI data frame size in bits */ + SPI_FrameFormat frameFormat; /*!< SPI frame format */ + void* custom; /*!< Custom argument used by driver + implementation */ } SPI_Params; /*! * @brief A function pointer to a driver specific implementation of * SPI_close(). */ -typedef void (*SPI_CloseFxn) (SPI_Handle handle); +typedef void (*SPI_CloseFxn)(SPI_Handle handle); /*! * @brief A function pointer to a driver specific implementation of * SPI_control(). */ -typedef int_fast16_t (*SPI_ControlFxn) (SPI_Handle handle, uint_fast16_t cmd, - void* arg); +typedef int_fast16_t (*SPI_ControlFxn)(SPI_Handle handle, uint_fast16_t cmd, + void* arg); /*! * @brief A function pointer to a driver specific implementation of * SPI_init(). */ -typedef void (*SPI_InitFxn) (SPI_Handle handle); +typedef void (*SPI_InitFxn)(SPI_Handle handle); /*! * @brief A function pointer to a driver specific implementation of * SPI_open(). */ -typedef SPI_Handle (*SPI_OpenFxn) (SPI_Handle handle, SPI_Params* params); +typedef SPI_Handle (*SPI_OpenFxn)(SPI_Handle handle, SPI_Params* params); /*! * @brief A function pointer to a driver specific implementation of * SPI_transfer(). */ -typedef bool (*SPI_TransferFxn) (SPI_Handle handle, - SPI_Transaction* transaction); +typedef bool (*SPI_TransferFxn)(SPI_Handle handle, + SPI_Transaction* transaction); /*! * @brief A function pointer to a driver specific implementation of * SPI_transferCancel(). */ -typedef void (*SPI_TransferCancelFxn) (SPI_Handle handle); +typedef void (*SPI_TransferCancelFxn)(SPI_Handle handle); /*! * @brief The definition of a SPI function table that contains the @@ -716,23 +716,23 @@ typedef void (*SPI_TransferCancelFxn) (SPI_Handle handle); */ typedef struct { - /*! Function to close the specified peripheral */ - SPI_CloseFxn closeFxn; + /*! Function to close the specified peripheral */ + SPI_CloseFxn closeFxn; - /*! Function to implementation specific control function */ - SPI_ControlFxn controlFxn; + /*! Function to implementation specific control function */ + SPI_ControlFxn controlFxn; - /*! Function to initialize the given data object */ - SPI_InitFxn initFxn; + /*! Function to initialize the given data object */ + SPI_InitFxn initFxn; - /*! Function to open the specified peripheral */ - SPI_OpenFxn openFxn; + /*! Function to open the specified peripheral */ + SPI_OpenFxn openFxn; - /*! Function to initiate a SPI data transfer */ - SPI_TransferFxn transferFxn; + /*! Function to initiate a SPI data transfer */ + SPI_TransferFxn transferFxn; - /*! Function to cancel SPI data transfer */ - SPI_TransferCancelFxn transferCancelFxn; + /*! Function to cancel SPI data transfer */ + SPI_TransferCancelFxn transferCancelFxn; } SPI_FxnTable; /*! @@ -748,14 +748,14 @@ typedef struct */ typedef struct SPI_Config_ { - /*! Pointer to a table of driver-specific implementations of SPI APIs */ - SPI_FxnTable const* fxnTablePtr; + /*! Pointer to a table of driver-specific implementations of SPI APIs */ + SPI_FxnTable const* fxnTablePtr; - /*! Pointer to a driver specific data object */ - void* object; + /*! Pointer to a driver specific data object */ + void* object; - /*! Pointer to a driver specific hardware attributes structure */ - void const* hwAttrs; + /*! Pointer to a driver specific hardware attributes structure */ + void const* hwAttrs; } SPI_Config; /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/TRNG.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/TRNG.h index 876271b..1a80b04 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/TRNG.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/TRNG.h @@ -231,7 +231,7 @@ extern "C" { * #define TRNGXYZ_STATUS_ERROR2 TRNG_STATUS_RESERVED - 2 * @endcode */ -#define TRNG_STATUS_RESERVED (-32) +#define TRNG_STATUS_RESERVED (-32) /*! * @brief Successful status code. @@ -239,7 +239,7 @@ extern "C" { * Functions return TRNG_STATUS_SUCCESS if the function was executed * successfully. */ -#define TRNG_STATUS_SUCCESS (0) +#define TRNG_STATUS_SUCCESS (0) /*! * @brief Generic error status code. @@ -247,7 +247,7 @@ extern "C" { * Functions return TRNG_STATUS_ERROR if the function was not executed * successfully. */ -#define TRNG_STATUS_ERROR (-1) +#define TRNG_STATUS_ERROR (-1) /*! * @brief An error status code returned if the hardware or software resource @@ -262,7 +262,7 @@ extern "C" { /*! * @brief A handle that is returned from a TRNG_open() call. */ -typedef struct TRNG_Config* TRNG_Handle; +typedef struct TRNG_Config* TRNG_Handle; /*! * @brief The way in which TRNG function calls return after generating @@ -287,20 +287,20 @@ typedef struct TRNG_Config* TRNG_Handle; */ typedef enum { - TRNG_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the - * TRNG operation goes on in the background. The registered - * callback function is called after the operation completes. - * The context the callback function is called (task, HWI, SWI) - * is implementation-dependent. - */ - TRNG_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while TRNG operation goes - * on in the background. TRNG operation results are available - * after the function returns. - */ - TRNG_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while TRNG - * operation goes on in the background. TRNG operation results - * are available after the function returns. - */ + TRNG_RETURN_BEHAVIOR_CALLBACK = 1, /*!< The function call will return immediately while the + * TRNG operation goes on in the background. The registered + * callback function is called after the operation completes. + * The context the callback function is called (task, HWI, SWI) + * is implementation-dependent. + */ + TRNG_RETURN_BEHAVIOR_BLOCKING = 2, /*!< The function call will block while TRNG operation goes + * on in the background. TRNG operation results are available + * after the function returns. + */ + TRNG_RETURN_BEHAVIOR_POLLING = 4, /*!< The function call will continuously poll a flag while TRNG + * operation goes on in the background. TRNG operation results + * are available after the function returns. + */ } TRNG_ReturnBehavior; /*! @@ -316,11 +316,11 @@ typedef enum */ typedef struct TRNG_Config { - /*! Pointer to a driver specific data object */ - void* object; + /*! Pointer to a driver specific data object */ + void* object; - /*! Pointer to a driver specific hardware attributes structure */ - void const* hwAttrs; + /*! Pointer to a driver specific hardware attributes structure */ + void const* hwAttrs; } TRNG_Config; /*! @@ -334,9 +334,9 @@ typedef struct TRNG_Config * @param entropy The CryptoKey that describes the location the generated * entropy will be copied to. */ -typedef void (*TRNG_CallbackFxn) (TRNG_Handle handle, - int_fast16_t returnValue, - CryptoKey* entropy); +typedef void (*TRNG_CallbackFxn)(TRNG_Handle handle, + int_fast16_t returnValue, + CryptoKey* entropy); /*! * @brief TRNG Parameters @@ -348,14 +348,14 @@ typedef void (*TRNG_CallbackFxn) (TRNG_Handle handle, */ typedef struct { - TRNG_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ - TRNG_CallbackFxn callbackFxn; /*!< Callback function pointer */ - uint32_t timeout; /*!< Timeout before the driver returns an error in - * ::TRNG_RETURN_BEHAVIOR_BLOCKING - */ - void* custom; /*!< Custom argument used by driver - * implementation - */ + TRNG_ReturnBehavior returnBehavior; /*!< Blocking, callback, or polling return behavior */ + TRNG_CallbackFxn callbackFxn; /*!< Callback function pointer */ + uint32_t timeout; /*!< Timeout before the driver returns an error in + * ::TRNG_RETURN_BEHAVIOR_BLOCKING + */ + void* custom; /*!< Custom argument used by driver + * implementation + */ } TRNG_Params; /*! @@ -440,9 +440,6 @@ void TRNG_close(TRNG_Handle handle); */ int_fast16_t TRNG_generateEntropy(TRNG_Handle handle, CryptoKey* entropy); - - - #ifdef __cplusplus } #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/UART.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/UART.h index 48983cd..bf74fda 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/UART.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/UART.h @@ -278,7 +278,7 @@ extern "C" { * #define UARTXYZ_CMD_COMMAND1 UART_CMD_RESERVED + 1 * @endcode */ -#define UART_CMD_RESERVED (32) +#define UART_CMD_RESERVED (32) /*! * Common UART_control status code reservation offset. @@ -292,7 +292,7 @@ extern "C" { * #define UARTXYZ_STATUS_ERROR2 UART_STATUS_RESERVED - 2 * @endcode */ -#define UART_STATUS_RESERVED (-32) +#define UART_STATUS_RESERVED (-32) /** * @defgroup UART_STATUS Status Codes @@ -307,7 +307,7 @@ extern "C" { * UART_control() returns UART_STATUS_SUCCESS if the control code was executed * successfully. */ -#define UART_STATUS_SUCCESS (0) +#define UART_STATUS_SUCCESS (0) /*! * @brief Generic error status code returned by UART_control(). @@ -315,7 +315,7 @@ extern "C" { * UART_control() returns UART_STATUS_ERROR if the control code was not executed * successfully. */ -#define UART_STATUS_ERROR (-1) +#define UART_STATUS_ERROR (-1) /*! * @brief An error status code returned by UART_control() for undefined @@ -324,7 +324,7 @@ extern "C" { * UART_control() returns UART_STATUS_UNDEFINEDCMD if the control code is not * recognized by the driver implementation. */ -#define UART_STATUS_UNDEFINEDCMD (-2) +#define UART_STATUS_UNDEFINEDCMD (-2) /** @}*/ /** @@ -343,7 +343,7 @@ extern "C" { * integer. @b *arg contains the next @c unsigned @c char read if data is * present, else @b *arg is set to #UART_STATUS_ERROR. */ -#define UART_CMD_PEEK (0) +#define UART_CMD_PEEK (0) /*! * @brief Command code used by UART_control() to determine if the read buffer @@ -354,7 +354,7 @@ extern "C" { * code, @b arg is a pointer to a @c bool. @b *arg contains @c true if data is * available, else @c false. */ -#define UART_CMD_ISAVAILABLE (1) +#define UART_CMD_ISAVAILABLE (1) /*! * @brief Command code used by UART_control() to determine how many unsigned @@ -365,7 +365,7 @@ extern "C" { * code, @b arg is a pointer to an @a integer. @b *arg contains the number of * @c unsigned @c chars available to read. */ -#define UART_CMD_GETRXCOUNT (2) +#define UART_CMD_GETRXCOUNT (2) /*! * @brief Command code used by UART_control() to enable data receive by the @@ -377,7 +377,7 @@ extern "C" { * while receive is enabled. UART_open() will always have this option * enabled. With this command code, @b arg is @a don't @a care. */ -#define UART_CMD_RXENABLE (3) +#define UART_CMD_RXENABLE (3) /*! * @brief Command code used by UART_control() to disable data received by the @@ -390,22 +390,22 @@ extern "C" { * * @warning A call to UART_read() does @b NOT re-enable receive. */ -#define UART_CMD_RXDISABLE (4) +#define UART_CMD_RXDISABLE (4) /** @}*/ /** @}*/ -#define UART_ERROR (UART_STATUS_ERROR) +#define UART_ERROR (UART_STATUS_ERROR) /*! * @brief Wait forever define */ -#define UART_WAIT_FOREVER (~(0U)) +#define UART_WAIT_FOREVER (~(0U)) /*! * @brief A handle that is returned from a UART_open() call. */ -typedef struct UART_Config_* UART_Handle; +typedef struct UART_Config_* UART_Handle; /*! * @brief The definition of a callback function used by the UART driver @@ -418,7 +418,7 @@ typedef struct UART_Config_* UART_Handle; * * @param count Number of elements read/written */ -typedef void (*UART_Callback) (UART_Handle handle, void* buf, size_t count); +typedef void (*UART_Callback)(UART_Handle handle, void* buf, size_t count); /*! * @brief UART mode settings @@ -428,16 +428,16 @@ typedef void (*UART_Callback) (UART_Handle handle, void* buf, size_t count); typedef enum UART_Mode_ { /*! - * Uses a semaphore to block while data is being sent. Context of the call - * must be a Task. - */ + * Uses a semaphore to block while data is being sent. Context of the call + * must be a Task. + */ UART_MODE_BLOCKING, /*! - * Non-blocking and will return immediately. When UART_write() or - * UART_read() has finished, the callback function is called from either - * the caller's context or from an interrupt context. - */ + * Non-blocking and will return immediately. When UART_write() or + * UART_read() has finished, the callback function is called from either + * the caller's context or from an interrupt context. + */ UART_MODE_CALLBACK } UART_Mode; @@ -503,8 +503,8 @@ typedef enum UART_DataMode_ */ typedef enum UART_Echo_ { - UART_ECHO_OFF = 0, /*!< Data is not echoed */ - UART_ECHO_ON = 1 /*!< Data is echoed */ + UART_ECHO_OFF = 0, /*!< Data is not echoed */ + UART_ECHO_ON = 1 /*!< Data is echoed */ } UART_Echo; /*! @@ -514,10 +514,10 @@ typedef enum UART_Echo_ */ typedef enum UART_LEN_ { - UART_LEN_5 = 0, /*!< Data length is 5 bits */ - UART_LEN_6 = 1, /*!< Data length is 6 bits */ - UART_LEN_7 = 2, /*!< Data length is 7 bits */ - UART_LEN_8 = 3 /*!< Data length is 8 bits */ + UART_LEN_5 = 0, /*!< Data length is 5 bits */ + UART_LEN_6 = 1, /*!< Data length is 6 bits */ + UART_LEN_7 = 2, /*!< Data length is 7 bits */ + UART_LEN_8 = 3 /*!< Data length is 8 bits */ } UART_LEN; /*! @@ -527,8 +527,8 @@ typedef enum UART_LEN_ */ typedef enum UART_STOP_ { - UART_STOP_ONE = 0, /*!< One stop bit */ - UART_STOP_TWO = 1 /*!< Two stop bits */ + UART_STOP_ONE = 0, /*!< One stop bit */ + UART_STOP_TWO = 1 /*!< Two stop bits */ } UART_STOP; /*! @@ -538,11 +538,11 @@ typedef enum UART_STOP_ */ typedef enum UART_PAR_ { - UART_PAR_NONE = 0, /*!< No parity */ - UART_PAR_EVEN = 1, /*!< Parity bit is even */ - UART_PAR_ODD = 2, /*!< Parity bit is odd */ - UART_PAR_ZERO = 3, /*!< Parity bit is always zero */ - UART_PAR_ONE = 4 /*!< Parity bit is always one */ + UART_PAR_NONE = 0, /*!< No parity */ + UART_PAR_EVEN = 1, /*!< Parity bit is even */ + UART_PAR_ODD = 2, /*!< Parity bit is odd */ + UART_PAR_ZERO = 3, /*!< Parity bit is always zero */ + UART_PAR_ONE = 4 /*!< Parity bit is always one */ } UART_PAR; /*! @@ -555,85 +555,85 @@ typedef enum UART_PAR_ */ typedef struct UART_Params_ { - UART_Mode readMode; /*!< Mode for all read calls */ - UART_Mode writeMode; /*!< Mode for all write calls */ - uint32_t readTimeout; /*!< Timeout for read calls in blocking mode. */ - uint32_t writeTimeout; /*!< Timeout for write calls in blocking mode. */ - UART_Callback readCallback; /*!< Pointer to read callback function for callback mode. */ - UART_Callback writeCallback; /*!< Pointer to write callback function for callback mode. */ - UART_ReturnMode readReturnMode; /*!< Receive return mode */ - UART_DataMode readDataMode; /*!< Type of data being read */ - UART_DataMode writeDataMode; /*!< Type of data being written */ - UART_Echo readEcho; /*!< Echo received data back */ - uint32_t baudRate; /*!< Baud rate for UART */ - UART_LEN dataLength; /*!< Data length for UART */ - UART_STOP stopBits; /*!< Stop bits for UART */ - UART_PAR parityType; /*!< Parity bit type for UART */ - void* custom; /*!< Custom argument used by driver implementation */ + UART_Mode readMode; /*!< Mode for all read calls */ + UART_Mode writeMode; /*!< Mode for all write calls */ + uint32_t readTimeout; /*!< Timeout for read calls in blocking mode. */ + uint32_t writeTimeout; /*!< Timeout for write calls in blocking mode. */ + UART_Callback readCallback; /*!< Pointer to read callback function for callback mode. */ + UART_Callback writeCallback; /*!< Pointer to write callback function for callback mode. */ + UART_ReturnMode readReturnMode; /*!< Receive return mode */ + UART_DataMode readDataMode; /*!< Type of data being read */ + UART_DataMode writeDataMode; /*!< Type of data being written */ + UART_Echo readEcho; /*!< Echo received data back */ + uint32_t baudRate; /*!< Baud rate for UART */ + UART_LEN dataLength; /*!< Data length for UART */ + UART_STOP stopBits; /*!< Stop bits for UART */ + UART_PAR parityType; /*!< Parity bit type for UART */ + void* custom; /*!< Custom argument used by driver implementation */ } UART_Params; /*! * @brief A function pointer to a driver specific implementation of * UART_CloseFxn(). */ -typedef void (*UART_CloseFxn) (UART_Handle handle); +typedef void (*UART_CloseFxn)(UART_Handle handle); /*! * @brief A function pointer to a driver specific implementation of * UART_ControlFxn(). */ -typedef int_fast16_t (*UART_ControlFxn) (UART_Handle handle, uint_fast16_t cmd, void* arg); +typedef int_fast16_t (*UART_ControlFxn)(UART_Handle handle, uint_fast16_t cmd, void* arg); /*! * @brief A function pointer to a driver specific implementation of * UART_InitFxn(). */ -typedef void (*UART_InitFxn) (UART_Handle handle); +typedef void (*UART_InitFxn)(UART_Handle handle); /*! * @brief A function pointer to a driver specific implementation of * UART_OpenFxn(). */ -typedef UART_Handle (*UART_OpenFxn) (UART_Handle handle, UART_Params* params); +typedef UART_Handle (*UART_OpenFxn)(UART_Handle handle, UART_Params* params); /*! * @brief A function pointer to a driver specific implementation of * UART_ReadFxn(). */ -typedef int_fast32_t (*UART_ReadFxn) (UART_Handle handle, void* buffer, - size_t size); +typedef int_fast32_t (*UART_ReadFxn)(UART_Handle handle, void* buffer, + size_t size); /*! * @brief A function pointer to a driver specific implementation of * UART_ReadPollingFxn(). */ -typedef int_fast32_t (*UART_ReadPollingFxn) (UART_Handle handle, void* buffer, - size_t size); +typedef int_fast32_t (*UART_ReadPollingFxn)(UART_Handle handle, void* buffer, + size_t size); /*! * @brief A function pointer to a driver specific implementation of * UART_ReadCancelFxn(). */ -typedef void (*UART_ReadCancelFxn) (UART_Handle handle); +typedef void (*UART_ReadCancelFxn)(UART_Handle handle); /*! * @brief A function pointer to a driver specific implementation of * UART_WriteFxn(). */ -typedef int_fast32_t (*UART_WriteFxn) (UART_Handle handle, const void* buffer, - size_t size); +typedef int_fast32_t (*UART_WriteFxn)(UART_Handle handle, const void* buffer, + size_t size); /*! * @brief A function pointer to a driver specific implementation of * UART_WritePollingFxn(). */ -typedef int_fast32_t (*UART_WritePollingFxn) (UART_Handle handle, - const void* buffer, size_t size); +typedef int_fast32_t (*UART_WritePollingFxn)(UART_Handle handle, + const void* buffer, size_t size); /*! * @brief A function pointer to a driver specific implementation of * UART_WriteCancelFxn(). */ -typedef void (*UART_WriteCancelFxn) (UART_Handle handle); +typedef void (*UART_WriteCancelFxn)(UART_Handle handle); /*! * @brief The definition of a UART function table that contains the @@ -642,35 +642,35 @@ typedef void (*UART_WriteCancelFxn) (UART_Handle handle); */ typedef struct UART_FxnTable_ { - /*! Function to close the specified peripheral */ - UART_CloseFxn closeFxn; + /*! Function to close the specified peripheral */ + UART_CloseFxn closeFxn; - /*! Function to implementation specific control function */ - UART_ControlFxn controlFxn; + /*! Function to implementation specific control function */ + UART_ControlFxn controlFxn; - /*! Function to initialize the given data object */ - UART_InitFxn initFxn; + /*! Function to initialize the given data object */ + UART_InitFxn initFxn; - /*! Function to open the specified peripheral */ - UART_OpenFxn openFxn; + /*! Function to open the specified peripheral */ + UART_OpenFxn openFxn; - /*! Function to read from the specified peripheral */ - UART_ReadFxn readFxn; + /*! Function to read from the specified peripheral */ + UART_ReadFxn readFxn; - /*! Function to read via polling from the specified peripheral */ - UART_ReadPollingFxn readPollingFxn; + /*! Function to read via polling from the specified peripheral */ + UART_ReadPollingFxn readPollingFxn; - /*! Function to cancel a read from the specified peripheral */ - UART_ReadCancelFxn readCancelFxn; + /*! Function to cancel a read from the specified peripheral */ + UART_ReadCancelFxn readCancelFxn; - /*! Function to write from the specified peripheral */ - UART_WriteFxn writeFxn; + /*! Function to write from the specified peripheral */ + UART_WriteFxn writeFxn; - /*! Function to write via polling from the specified peripheral */ - UART_WritePollingFxn writePollingFxn; + /*! Function to write via polling from the specified peripheral */ + UART_WritePollingFxn writePollingFxn; - /*! Function to cancel a write from the specified peripheral */ - UART_WriteCancelFxn writeCancelFxn; + /*! Function to cancel a write from the specified peripheral */ + UART_WriteCancelFxn writeCancelFxn; } UART_FxnTable; /*! @@ -686,14 +686,14 @@ typedef struct UART_FxnTable_ */ typedef struct UART_Config_ { - /*! Pointer to a table of driver-specific implementations of UART APIs */ - UART_FxnTable const* fxnTablePtr; + /*! Pointer to a table of driver-specific implementations of UART APIs */ + UART_FxnTable const* fxnTablePtr; - /*! Pointer to a driver specific data object */ - void* object; + /*! Pointer to a driver specific data object */ + void* object; - /*! Pointer to a driver specific hardware attributes structure */ - void const* hwAttrs; + /*! Pointer to a driver specific hardware attributes structure */ + void const* hwAttrs; } UART_Config; /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/Watchdog.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/Watchdog.h index 0d00645..229c2d8 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/Watchdog.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/Watchdog.h @@ -176,7 +176,7 @@ extern "C" { * #define WatchdogXYZ_CMD_COMMAND1 Watchdog_CMD_RESERVED + 1 * @endcode */ -#define Watchdog_CMD_RESERVED (32) +#define Watchdog_CMD_RESERVED (32) /*! * Common Watchdog_control status code reservation offset. @@ -190,7 +190,7 @@ extern "C" { * #define WatchdogXYZ_STATUS_ERROR2 Watchdog_STATUS_RESERVED - 2 * @endcode */ -#define Watchdog_STATUS_RESERVED (-32) +#define Watchdog_STATUS_RESERVED (-32) /** * @defgroup Watchdog_STATUS Status Codes @@ -205,7 +205,7 @@ extern "C" { * Watchdog_control() returns Watchdog_STATUS_SUCCESS if the control code was * executed successfully. */ -#define Watchdog_STATUS_SUCCESS (0) +#define Watchdog_STATUS_SUCCESS (0) /*! * @brief Generic error status code returned by Watchdog_control(). @@ -213,7 +213,7 @@ extern "C" { * Watchdog_control() returns Watchdog_STATUS_ERROR if the control code was not * executed successfully. */ -#define Watchdog_STATUS_ERROR (-1) +#define Watchdog_STATUS_ERROR (-1) /*! * @brief An error status code returned by Watchdog_control() for undefined @@ -222,7 +222,7 @@ extern "C" { * Watchdog_control() returns Watchdog_STATUS_UNDEFINEDCMD if the control code * is not recognized by the driver implementation. */ -#define Watchdog_STATUS_UNDEFINEDCMD (-2) +#define Watchdog_STATUS_UNDEFINEDCMD (-2) /*! * @brief An error status code returned by Watchdog_setReload() for drivers @@ -231,7 +231,7 @@ extern "C" { * Watchdog_setReload() returns Watchdog_STATUS_UNSUPPORTED if the driver * implementation does not support the aforementioned API. */ -#define Watchdog_STATUS_UNSUPPORTED (-3) +#define Watchdog_STATUS_UNSUPPORTED (-3) /** @}*/ /** @@ -249,8 +249,8 @@ extern "C" { /** @}*/ /*! -* @brief Watchdog Handle -*/ + * @brief Watchdog Handle + */ typedef struct Watchdog_Config_* Watchdog_Handle; /*! @@ -300,62 +300,62 @@ typedef void (*Watchdog_Callback)(uintptr_t handle); */ typedef struct Watchdog_Params_ { - Watchdog_Callback callbackFxn; /*!< Pointer to callback. Not supported - on all targets. */ - Watchdog_ResetMode resetMode; /*!< Mode to enable resets. - Not supported on all targets. */ - Watchdog_DebugMode debugStallMode; /*!< Mode to stall WDT at breakpoints. - Not supported on all targets. */ - void* custom; /*!< Custom argument used by driver - implementation */ + Watchdog_Callback callbackFxn; /*!< Pointer to callback. Not supported + on all targets. */ + Watchdog_ResetMode resetMode; /*!< Mode to enable resets. + Not supported on all targets. */ + Watchdog_DebugMode debugStallMode; /*!< Mode to stall WDT at breakpoints. + Not supported on all targets. */ + void* custom; /*!< Custom argument used by driver + implementation */ } Watchdog_Params; /*! * @brief A function pointer to a driver specific implementation of * Watchdog_clear(). */ -typedef void (*Watchdog_ClearFxn) (Watchdog_Handle handle); +typedef void (*Watchdog_ClearFxn)(Watchdog_Handle handle); /*! * @brief A function pointer to a driver specific implementation of * Watchdog_close(). */ -typedef void (*Watchdog_CloseFxn) (Watchdog_Handle handle); +typedef void (*Watchdog_CloseFxn)(Watchdog_Handle handle); /*! * @brief A function pointer to a driver specific implementation of * Watchdog_control(). */ -typedef int_fast16_t (*Watchdog_ControlFxn) (Watchdog_Handle handle, - uint_fast16_t cmd, - void* arg); +typedef int_fast16_t (*Watchdog_ControlFxn)(Watchdog_Handle handle, + uint_fast16_t cmd, + void* arg); /*! * @brief A function pointer to a driver specific implementation of * Watchdog_init(). */ -typedef void (*Watchdog_InitFxn) (Watchdog_Handle handle); +typedef void (*Watchdog_InitFxn)(Watchdog_Handle handle); /*! * @brief A function pointer to a driver specific implementation of * Watchdog_open(). */ -typedef Watchdog_Handle (*Watchdog_OpenFxn) (Watchdog_Handle handle, - Watchdog_Params* params); +typedef Watchdog_Handle (*Watchdog_OpenFxn)(Watchdog_Handle handle, + Watchdog_Params* params); /*! * @brief A function pointer to a driver specific implementation of * Watchdog_setReload(). */ typedef int_fast16_t (*Watchdog_SetReloadFxn)(Watchdog_Handle handle, - uint32_t ticks); + uint32_t ticks); /*! * @brief A function pointer to a driver specific implementation of * Watchdog_ConvertMsToTicksFxn(). */ -typedef uint32_t (*Watchdog_ConvertMsToTicksFxn) (Watchdog_Handle handle, - uint32_t milliseconds); +typedef uint32_t (*Watchdog_ConvertMsToTicksFxn)(Watchdog_Handle handle, + uint32_t milliseconds); /*! * @brief The definition of a Watchdog function table that contains the @@ -364,13 +364,13 @@ typedef uint32_t (*Watchdog_ConvertMsToTicksFxn) (Watchdog_Handle handle, */ typedef struct Watchdog_FxnTable_ { - Watchdog_ClearFxn watchdogClear; - Watchdog_CloseFxn watchdogClose; - Watchdog_ControlFxn watchdogControl; - Watchdog_InitFxn watchdogInit; - Watchdog_OpenFxn watchdogOpen; - Watchdog_SetReloadFxn watchdogSetReload; - Watchdog_ConvertMsToTicksFxn watchdogConvertMsToTicks; + Watchdog_ClearFxn watchdogClear; + Watchdog_CloseFxn watchdogClose; + Watchdog_ControlFxn watchdogControl; + Watchdog_InitFxn watchdogInit; + Watchdog_OpenFxn watchdogOpen; + Watchdog_SetReloadFxn watchdogSetReload; + Watchdog_ConvertMsToTicksFxn watchdogConvertMsToTicks; } Watchdog_FxnTable; /*! @@ -386,16 +386,16 @@ typedef struct Watchdog_FxnTable_ */ typedef struct Watchdog_Config_ { - /*! - * Pointer to a table of driver-specific implementations of Watchdog APIs - */ - Watchdog_FxnTable const* fxnTablePtr; + /*! + * Pointer to a table of driver-specific implementations of Watchdog APIs + */ + Watchdog_FxnTable const* fxnTablePtr; - /*! Pointer to a driver specific data object */ - void* object; + /*! Pointer to a driver specific data object */ + void* object; - /*! Pointer to a driver specific hardware attributes structure */ - void const* hwAttrs; + /*! Pointer to a driver specific hardware attributes structure */ + void const* hwAttrs; } Watchdog_Config; /*! @@ -551,7 +551,7 @@ extern int_fast16_t Watchdog_setReload(Watchdog_Handle handle, uint32_t ticks); * @sa Watchdog_setReload() */ extern uint32_t Watchdog_convertMsToTicks(Watchdog_Handle handle, - uint32_t milliseconds); + uint32_t milliseconds); #ifdef __cplusplus } diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adc/ADCCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adc/ADCCC26XX.h index 47f1398..768dd70 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adc/ADCCC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adc/ADCCC26XX.h @@ -43,17 +43,17 @@ #ifndef ti_drivers_adc_ADCCC26XX__include #define ti_drivers_adc_ADCCC26XX__include -#include #include +#include #include #include -#include #include +#include #include #include -#include DeviceFamily_constructPath(driverlib/aux_adc.h) +#include DeviceFamily_constructPath(driverlib / aux_adc.h) #ifdef __cplusplus extern "C" { @@ -70,19 +70,19 @@ extern "C" { */ typedef enum ADCCC26XX_Sampling_Duration { - ADCCC26XX_SAMPLING_DURATION_2P7_US = AUXADC_SAMPLE_TIME_2P7_US, - ADCCC26XX_SAMPLING_DURATION_5P3_US = AUXADC_SAMPLE_TIME_5P3_US, - ADCCC26XX_SAMPLING_DURATION_10P6_US = AUXADC_SAMPLE_TIME_10P6_US, - ADCCC26XX_SAMPLING_DURATION_21P3_US = AUXADC_SAMPLE_TIME_21P3_US, - ADCCC26XX_SAMPLING_DURATION_42P6_US = AUXADC_SAMPLE_TIME_42P6_US, - ADCCC26XX_SAMPLING_DURATION_85P3_US = AUXADC_SAMPLE_TIME_85P3_US, - ADCCC26XX_SAMPLING_DURATION_170_US = AUXADC_SAMPLE_TIME_170_US, - ADCCC26XX_SAMPLING_DURATION_341_US = AUXADC_SAMPLE_TIME_341_US, - ADCCC26XX_SAMPLING_DURATION_682_US = AUXADC_SAMPLE_TIME_682_US, - ADCCC26XX_SAMPLING_DURATION_1P37_MS = AUXADC_SAMPLE_TIME_1P37_MS, - ADCCC26XX_SAMPLING_DURATION_2P73_MS = AUXADC_SAMPLE_TIME_2P73_MS, - ADCCC26XX_SAMPLING_DURATION_5P46_MS = AUXADC_SAMPLE_TIME_5P46_MS, - ADCCC26XX_SAMPLING_DURATION_10P9_MS = AUXADC_SAMPLE_TIME_10P9_MS + ADCCC26XX_SAMPLING_DURATION_2P7_US = AUXADC_SAMPLE_TIME_2P7_US, + ADCCC26XX_SAMPLING_DURATION_5P3_US = AUXADC_SAMPLE_TIME_5P3_US, + ADCCC26XX_SAMPLING_DURATION_10P6_US = AUXADC_SAMPLE_TIME_10P6_US, + ADCCC26XX_SAMPLING_DURATION_21P3_US = AUXADC_SAMPLE_TIME_21P3_US, + ADCCC26XX_SAMPLING_DURATION_42P6_US = AUXADC_SAMPLE_TIME_42P6_US, + ADCCC26XX_SAMPLING_DURATION_85P3_US = AUXADC_SAMPLE_TIME_85P3_US, + ADCCC26XX_SAMPLING_DURATION_170_US = AUXADC_SAMPLE_TIME_170_US, + ADCCC26XX_SAMPLING_DURATION_341_US = AUXADC_SAMPLE_TIME_341_US, + ADCCC26XX_SAMPLING_DURATION_682_US = AUXADC_SAMPLE_TIME_682_US, + ADCCC26XX_SAMPLING_DURATION_1P37_MS = AUXADC_SAMPLE_TIME_1P37_MS, + ADCCC26XX_SAMPLING_DURATION_2P73_MS = AUXADC_SAMPLE_TIME_2P73_MS, + ADCCC26XX_SAMPLING_DURATION_5P46_MS = AUXADC_SAMPLE_TIME_5P46_MS, + ADCCC26XX_SAMPLING_DURATION_10P9_MS = AUXADC_SAMPLE_TIME_10P9_MS } ADCCC26XX_Sampling_Duration; /*! @@ -107,8 +107,8 @@ typedef enum ADCCC26XX_Sampling_Duration */ typedef enum ADCCC26XX_Reference_Source { - ADCCC26XX_FIXED_REFERENCE = AUXADC_REF_FIXED, - ADCCC26XX_VDDS_REFERENCE = AUXADC_REF_VDDS_REL + ADCCC26XX_FIXED_REFERENCE = AUXADC_REF_FIXED, + ADCCC26XX_VDDS_REFERENCE = AUXADC_REF_VDDS_REL } ADCCC26XX_Reference_Source; /*! @@ -119,7 +119,7 @@ typedef enum ADCCC26XX_Reference_Source */ typedef enum ADCCC26XX_Trigger_Source { - ADCCC26XX_TRIGGER_MANUAL = AUXADC_TRIGGER_MANUAL, + ADCCC26XX_TRIGGER_MANUAL = AUXADC_TRIGGER_MANUAL, } ADCCC26XX_Trigger_Source; /* ADC function table pointer */ @@ -133,13 +133,13 @@ extern const ADC_FxnTable ADCCC26XX_fxnTable; */ typedef struct ADCCC26XX_HWAttrs { - uint8_t adcDIO; /*!< DIO that the ADC is routed to */ - uint8_t adcCompBInput; /*!< Internal signal routed to comparator B */ - bool returnAdjustedVal; /*!< Should the raw output be trimmed before returning it */ - bool inputScalingEnabled; /*!< Is input scaling enabled */ - ADCCC26XX_Reference_Source refSource; /*!< Reference source for the ADC to use */ - ADCCC26XX_Sampling_Duration samplingDuration; /*!< Time the ADC spends sampling. This is load dependent */ - ADCCC26XX_Trigger_Source triggerSource; /*!< Source that the ADC triggers off of. Currently only supports AUXADC_TRIGGER_MANUAL */ + uint8_t adcDIO; /*!< DIO that the ADC is routed to */ + uint8_t adcCompBInput; /*!< Internal signal routed to comparator B */ + bool returnAdjustedVal; /*!< Should the raw output be trimmed before returning it */ + bool inputScalingEnabled; /*!< Is input scaling enabled */ + ADCCC26XX_Reference_Source refSource; /*!< Reference source for the ADC to use */ + ADCCC26XX_Sampling_Duration samplingDuration; /*!< Time the ADC spends sampling. This is load dependent */ + ADCCC26XX_Trigger_Source triggerSource; /*!< Source that the ADC triggers off of. Currently only supports AUXADC_TRIGGER_MANUAL */ } ADCCC26XX_HWAttrs; /*! @@ -149,14 +149,12 @@ typedef struct ADCCC26XX_HWAttrs */ typedef struct ADCCC26XX_Object { - PIN_State pinState; /*!< Pin state object */ - PIN_Handle pinHandle; /*!< Pin handle */ - bool isOpen; /*!< Flag if the instance is in use */ - bool isProtected; /*!< Flag to indicate if thread safety is ensured by the driver */ + PIN_State pinState; /*!< Pin state object */ + PIN_Handle pinHandle; /*!< Pin handle */ + bool isOpen; /*!< Flag if the instance is in use */ + bool isProtected; /*!< Flag to indicate if thread safety is ensured by the driver */ } ADCCC26XX_Object; - - #ifdef __cplusplus } #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adcbuf/ADCBufCC26X2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adcbuf/ADCBufCC26X2.h index 2cf7818..7654277 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adcbuf/ADCBufCC26X2.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adcbuf/ADCBufCC26X2.h @@ -199,7 +199,7 @@ * * ADCBuf_Params_init(&adcBufParams); * adcBufHandle = ADCBuf_open(Board_ADCBuf0, &adcBufParams); - * if (adcBufHandle == NULL) { + * if (adcBufHandle == NULL) { * // handle error * } * @@ -272,22 +272,22 @@ extern "C" { #endif -#include #include +#include #include #include -#include -#include -#include #include +#include +#include #include +#include #include -#include DeviceFamily_constructPath(driverlib/aux_adc.h) +#include DeviceFamily_constructPath(driverlib / aux_adc.h) -#include #include +#include #include #include @@ -356,9 +356,9 @@ extern "C" { /*! * @brief Resolution in bits of the CC26X2 ADC */ -#define ADCBufCC26X2_RESOLUTION 12 +#define ADCBufCC26X2_RESOLUTION 12 -#define ADCBufCC26X2_BYTES_PER_SAMPLE 2 +#define ADCBufCC26X2_BYTES_PER_SAMPLE 2 /* * ============================================================================= @@ -369,7 +369,6 @@ extern "C" { /* ADCBuf function table pointer */ extern const ADCBuf_FxnTable ADCBufCC26X2_fxnTable; - /* * ============================================================================= * Enumerations @@ -402,22 +401,21 @@ typedef enum ADCBufCC26X2_Sampling_Mode */ typedef enum ADCBufCC26X2_Sampling_Duration { - ADCBufCC26X2_SAMPLING_DURATION_2P7_US = AUXADC_SAMPLE_TIME_2P7_US, - ADCBufCC26X2_SAMPLING_DURATION_5P3_US = AUXADC_SAMPLE_TIME_5P3_US, - ADCBufCC26X2_SAMPLING_DURATION_10P6_US = AUXADC_SAMPLE_TIME_10P6_US, - ADCBufCC26X2_SAMPLING_DURATION_21P3_US = AUXADC_SAMPLE_TIME_21P3_US, - ADCBufCC26X2_SAMPLING_DURATION_42P6_US = AUXADC_SAMPLE_TIME_42P6_US, - ADCBufCC26X2_SAMPLING_DURATION_85P3_US = AUXADC_SAMPLE_TIME_85P3_US, - ADCBufCC26X2_SAMPLING_DURATION_170_US = AUXADC_SAMPLE_TIME_170_US, - ADCBufCC26X2_SAMPLING_DURATION_341_US = AUXADC_SAMPLE_TIME_341_US, - ADCBufCC26X2_SAMPLING_DURATION_682_US = AUXADC_SAMPLE_TIME_682_US, - ADCBufCC26X2_SAMPLING_DURATION_1P37_MS = AUXADC_SAMPLE_TIME_1P37_MS, - ADCBufCC26X2_SAMPLING_DURATION_2P73_MS = AUXADC_SAMPLE_TIME_2P73_MS, - ADCBufCC26X2_SAMPLING_DURATION_5P46_MS = AUXADC_SAMPLE_TIME_5P46_MS, - ADCBufCC26X2_SAMPLING_DURATION_10P9_MS = AUXADC_SAMPLE_TIME_10P9_MS + ADCBufCC26X2_SAMPLING_DURATION_2P7_US = AUXADC_SAMPLE_TIME_2P7_US, + ADCBufCC26X2_SAMPLING_DURATION_5P3_US = AUXADC_SAMPLE_TIME_5P3_US, + ADCBufCC26X2_SAMPLING_DURATION_10P6_US = AUXADC_SAMPLE_TIME_10P6_US, + ADCBufCC26X2_SAMPLING_DURATION_21P3_US = AUXADC_SAMPLE_TIME_21P3_US, + ADCBufCC26X2_SAMPLING_DURATION_42P6_US = AUXADC_SAMPLE_TIME_42P6_US, + ADCBufCC26X2_SAMPLING_DURATION_85P3_US = AUXADC_SAMPLE_TIME_85P3_US, + ADCBufCC26X2_SAMPLING_DURATION_170_US = AUXADC_SAMPLE_TIME_170_US, + ADCBufCC26X2_SAMPLING_DURATION_341_US = AUXADC_SAMPLE_TIME_341_US, + ADCBufCC26X2_SAMPLING_DURATION_682_US = AUXADC_SAMPLE_TIME_682_US, + ADCBufCC26X2_SAMPLING_DURATION_1P37_MS = AUXADC_SAMPLE_TIME_1P37_MS, + ADCBufCC26X2_SAMPLING_DURATION_2P73_MS = AUXADC_SAMPLE_TIME_2P73_MS, + ADCBufCC26X2_SAMPLING_DURATION_5P46_MS = AUXADC_SAMPLE_TIME_5P46_MS, + ADCBufCC26X2_SAMPLING_DURATION_10P9_MS = AUXADC_SAMPLE_TIME_10P9_MS } ADCBufCC26X2_Sampling_Duration; - /*! * @brief Specifies whether the internal reference of the ADC is sourced from the battery voltage or a fixed internal source. * @@ -440,12 +438,10 @@ typedef enum ADCBufCC26X2_Sampling_Duration */ typedef enum ADCBufCC26X2_Reference_Source { - ADCBufCC26X2_FIXED_REFERENCE = AUXADC_REF_FIXED, - ADCBufCC26X2_VDDS_REFERENCE = AUXADC_REF_VDDS_REL + ADCBufCC26X2_FIXED_REFERENCE = AUXADC_REF_FIXED, + ADCBufCC26X2_VDDS_REFERENCE = AUXADC_REF_VDDS_REL } ADCBufCC26X2_Reference_Source; - - /* * ============================================================================= * Structs @@ -453,15 +449,15 @@ typedef enum ADCBufCC26X2_Reference_Source */ /*! -* @brief Table entry that maps a virtual adc channel to a dio and its corresponding internal analogue signal -* -* Non-dio signals can be used as well. To do this, compBInput is set to the driverlib define corresponding to the -* desired non-dio signal and dio is set to PIN_UNASSIGNED. -*/ + * @brief Table entry that maps a virtual adc channel to a dio and its corresponding internal analogue signal + * + * Non-dio signals can be used as well. To do this, compBInput is set to the driverlib define corresponding to the + * desired non-dio signal and dio is set to PIN_UNASSIGNED. + */ typedef struct ADCBufCC26X2_AdcChannelLutEntry { - uint8_t dio; /*!< DIO that this virtual channel is mapped to */ - uint8_t compBInput; /*!< CompBInput that this virtual channel is mapped to */ + uint8_t dio; /*!< DIO that this virtual channel is mapped to */ + uint8_t compBInput; /*!< CompBInput that this virtual channel is mapped to */ } ADCBufCC26X2_AdcChannelLutEntry; /*! @@ -473,28 +469,28 @@ typedef struct ADCBufCC26X2_AdcChannelLutEntry */ typedef struct ADCBufCC26X2_ParamsExtension { - /*! Amount of time the ADC spends sampling the analogue input */ - ADCBufCC26X2_Sampling_Duration samplingDuration; - /*! Specifies whether the ADC spends a fixed amount of time sampling or the entire time since the last conversion */ - ADCBufCC26X2_Sampling_Mode samplingMode; - /*! Specifies whether the internal reference of the ADC is sourced from the battery voltage or a fixed internal source */ - ADCBufCC26X2_Reference_Source refSource; - /*! - * Disable input scaling. Input scaling scales an external analogue - * signal between 0 and 4.3V to an internal signal of 0 to ~1.4785V. - * Since the largest permissible input to any pin is VDDS, the maximum - * range of the ADC is effectively less than 3.8V and continues to shrink - * as the battery voltage drops. - * With input scaling disabled, the external analogue signal is passed - * on directly to the internal electronics. Signals larger than ~1.4785V - * will damage the device with input scaling disabled. - * - * | Input scaling status | Maximum permissible ADC input voltage | - * |---------------------------|---------------------------------------| - * | Enabled | VDDS (Battery voltage level) | - * | Disabled | 1.4785V | - */ - bool inputScalingEnabled; + /*! Amount of time the ADC spends sampling the analogue input */ + ADCBufCC26X2_Sampling_Duration samplingDuration; + /*! Specifies whether the ADC spends a fixed amount of time sampling or the entire time since the last conversion */ + ADCBufCC26X2_Sampling_Mode samplingMode; + /*! Specifies whether the internal reference of the ADC is sourced from the battery voltage or a fixed internal source */ + ADCBufCC26X2_Reference_Source refSource; + /*! + * Disable input scaling. Input scaling scales an external analogue + * signal between 0 and 4.3V to an internal signal of 0 to ~1.4785V. + * Since the largest permissible input to any pin is VDDS, the maximum + * range of the ADC is effectively less than 3.8V and continues to shrink + * as the battery voltage drops. + * With input scaling disabled, the external analogue signal is passed + * on directly to the internal electronics. Signals larger than ~1.4785V + * will damage the device with input scaling disabled. + * + * | Input scaling status | Maximum permissible ADC input voltage | + * |---------------------------|---------------------------------------| + * | Enabled | VDDS (Battery voltage level) | + * | Disabled | 1.4785V | + */ + bool inputScalingEnabled; } ADCBufCC26X2_ParamsExtension; /*! @@ -517,34 +513,32 @@ typedef struct ADCBufCC26X2_ParamsExtension */ typedef struct ADCBufCC26X2_HWAttrs { - /*! @brief ADC SWI priority. - The higher the number, the higher the priority. - The minimum is 0 and the maximum is 15 by default. - The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. - */ - uint32_t swiPriority; - /*! @brief ADC peripheral's interrupt priority. + /*! @brief ADC SWI priority. + The higher the number, the higher the priority. + The minimum is 0 and the maximum is 15 by default. + The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. + */ + uint32_t swiPriority; + /*! @brief ADC peripheral's interrupt priority. - The CC26xx uses three of the priority bits, - meaning ~0 has the same effect as (7 << 5). + The CC26xx uses three of the priority bits, + meaning ~0 has the same effect as (7 << 5). - (7 << 5) will apply the lowest priority. + (7 << 5) will apply the lowest priority. - (1 << 5) will apply the highest priority. + (1 << 5) will apply the highest priority. - Setting the priority to 0 is not supported by this driver. + Setting the priority to 0 is not supported by this driver. - HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. - */ - uint8_t intPriority; - /*! Pointer to a table of ADCBufCC26X2_AdcChannelLutEntry's mapping internal CompBInput to DIO */ - ADCBufCC26X2_AdcChannelLutEntry const* adcChannelLut; - /*! GPTimer unit index (0A, 0B, 1A..). Currently only the 0A unit index is supported. */ - uint8_t gpTimerUnit; + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! Pointer to a table of ADCBufCC26X2_AdcChannelLutEntry's mapping internal CompBInput to DIO */ + ADCBufCC26X2_AdcChannelLutEntry const* adcChannelLut; + /*! GPTimer unit index (0A, 0B, 1A..). Currently only the 0A unit index is supported. */ + uint8_t gpTimerUnit; } ADCBufCC26X2_HWAttrs; - - /*! * @brief ADCBufCC26X2 Object * @@ -552,40 +546,40 @@ typedef struct ADCBufCC26X2_HWAttrs */ typedef struct ADCBufCC26X2_Object { - /* ADC control variables */ - bool isOpen; /*!< Has the obj been opened */ - bool conversionInProgress; /*!< Is the ADC currently doing conversions */ - bool inputScalingEnabled; /*!< Is the analogue input scaled */ - bool keepADCSemaphore; /*!< Should the driver keep the ADC semaphore after a conversion */ - bool adcSemaphoreInPossession; /*!< Does the driver currently possess the ADC semaphore */ - uint8_t currentChannel; /*!< The current virtual channel the ADCBuf driver is sampling on */ - ADCBufCC26X2_Reference_Source refSource; /*!< Reference source for the ADC to use */ - ADCBufCC26X2_Sampling_Mode samplingMode; /*!< Synchronous or asynchronous sampling mode */ - ADCBufCC26X2_Sampling_Duration samplingDuration; /*!< Time the ADC spends sampling in ADCBufCC26X2_SAMPING_MODE_SYNCHRONOUS */ - ADCBuf_Callback callbackFxn; /*!< Pointer to callback function */ - ADCBuf_Recurrence_Mode recurrenceMode; /*!< Should we convert continuously or one-shot */ - ADCBuf_Return_Mode returnMode; /*!< Mode for all conversions */ - uint16_t* activeSampleBuffer; /*!< The last complete sample buffer used by the DMA */ + /* ADC control variables */ + bool isOpen; /*!< Has the obj been opened */ + bool conversionInProgress; /*!< Is the ADC currently doing conversions */ + bool inputScalingEnabled; /*!< Is the analogue input scaled */ + bool keepADCSemaphore; /*!< Should the driver keep the ADC semaphore after a conversion */ + bool adcSemaphoreInPossession; /*!< Does the driver currently possess the ADC semaphore */ + uint8_t currentChannel; /*!< The current virtual channel the ADCBuf driver is sampling on */ + ADCBufCC26X2_Reference_Source refSource; /*!< Reference source for the ADC to use */ + ADCBufCC26X2_Sampling_Mode samplingMode; /*!< Synchronous or asynchronous sampling mode */ + ADCBufCC26X2_Sampling_Duration samplingDuration; /*!< Time the ADC spends sampling in ADCBufCC26X2_SAMPING_MODE_SYNCHRONOUS */ + ADCBuf_Callback callbackFxn; /*!< Pointer to callback function */ + ADCBuf_Recurrence_Mode recurrenceMode; /*!< Should we convert continuously or one-shot */ + ADCBuf_Return_Mode returnMode; /*!< Mode for all conversions */ + uint16_t* activeSampleBuffer; /*!< The last complete sample buffer used by the DMA */ - /* ADC SYS/BIOS objects */ - HwiP_Struct hwi; /*!< Hwi object */ - SwiP_Struct swi; /*!< Swi object */ - SemaphoreP_Struct conversionComplete; /*!< ADC semaphore */ + /* ADC SYS/BIOS objects */ + HwiP_Struct hwi; /*!< Hwi object */ + SwiP_Struct swi; /*!< Swi object */ + SemaphoreP_Struct conversionComplete; /*!< ADC semaphore */ - ADCBuf_Conversion* currentConversion; /*!< Pointer to the current conversion struct */ + ADCBuf_Conversion* currentConversion; /*!< Pointer to the current conversion struct */ - /* PIN driver state object and handle */ - PIN_State pinState; /*!< Pin state object */ - PIN_Handle pinHandle; /*!< Pin handle */ + /* PIN driver state object and handle */ + PIN_State pinState; /*!< Pin state object */ + PIN_Handle pinHandle; /*!< Pin handle */ - /* UDMA driver handle */ - UDMACC26XX_Handle udmaHandle; /*!< UDMA handle */ + /* UDMA driver handle */ + UDMACC26XX_Handle udmaHandle; /*!< UDMA handle */ - /* GPTimer driver handle */ - GPTimerCC26XX_Handle timerHandle; /*!< Handle to underlying GPTimer peripheral */ + /* GPTimer driver handle */ + GPTimerCC26XX_Handle timerHandle; /*!< Handle to underlying GPTimer peripheral */ - uint32_t semaphoreTimeout; /*!< Timeout for read semaphore in ::ADCBuf_RETURN_MODE_BLOCKING */ - uint32_t samplingFrequency; /*!< Frequency in Hz at which the ADC is triggered */ + uint32_t semaphoreTimeout; /*!< Timeout for read semaphore in ::ADCBuf_RETURN_MODE_BLOCKING */ + uint32_t samplingFrequency; /*!< Frequency in Hz at which the ADC is triggered */ } ADCBufCC26X2_Object, *ADCBufCC26X2_Handle; /* @@ -594,7 +588,6 @@ typedef struct ADCBufCC26X2_Object * ============================================================================= */ - #ifdef __cplusplus } #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adcbuf/ADCBufCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adcbuf/ADCBufCC26XX.h index 8295f5c..84ed725 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adcbuf/ADCBufCC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/adcbuf/ADCBufCC26XX.h @@ -273,22 +273,22 @@ extern "C" { #endif -#include #include +#include #include #include -#include -#include -#include #include +#include +#include #include +#include #include -#include DeviceFamily_constructPath(driverlib/aux_adc.h) +#include DeviceFamily_constructPath(driverlib / aux_adc.h) -#include #include +#include #include #include @@ -357,9 +357,9 @@ extern "C" { /*! * @brief Resolution in bits of the CC26XX ADC */ -#define ADCBufCC26XX_RESOLUTION 12 +#define ADCBufCC26XX_RESOLUTION 12 -#define ADCBufCC26XX_BYTES_PER_SAMPLE 2 +#define ADCBufCC26XX_BYTES_PER_SAMPLE 2 /* * ============================================================================= @@ -370,7 +370,6 @@ extern "C" { /* ADCBuf function table pointer */ extern const ADCBuf_FxnTable ADCBufCC26XX_fxnTable; - /* * ============================================================================= * Enumerations @@ -403,22 +402,21 @@ typedef enum ADCBufCC26XX_Sampling_Mode */ typedef enum ADCBufCC26XX_Sampling_Duration { - ADCBufCC26XX_SAMPLING_DURATION_2P7_US = AUXADC_SAMPLE_TIME_2P7_US, - ADCBufCC26XX_SAMPLING_DURATION_5P3_US = AUXADC_SAMPLE_TIME_5P3_US, - ADCBufCC26XX_SAMPLING_DURATION_10P6_US = AUXADC_SAMPLE_TIME_10P6_US, - ADCBufCC26XX_SAMPLING_DURATION_21P3_US = AUXADC_SAMPLE_TIME_21P3_US, - ADCBufCC26XX_SAMPLING_DURATION_42P6_US = AUXADC_SAMPLE_TIME_42P6_US, - ADCBufCC26XX_SAMPLING_DURATION_85P3_US = AUXADC_SAMPLE_TIME_85P3_US, - ADCBufCC26XX_SAMPLING_DURATION_170_US = AUXADC_SAMPLE_TIME_170_US, - ADCBufCC26XX_SAMPLING_DURATION_341_US = AUXADC_SAMPLE_TIME_341_US, - ADCBufCC26XX_SAMPLING_DURATION_682_US = AUXADC_SAMPLE_TIME_682_US, - ADCBufCC26XX_SAMPLING_DURATION_1P37_MS = AUXADC_SAMPLE_TIME_1P37_MS, - ADCBufCC26XX_SAMPLING_DURATION_2P73_MS = AUXADC_SAMPLE_TIME_2P73_MS, - ADCBufCC26XX_SAMPLING_DURATION_5P46_MS = AUXADC_SAMPLE_TIME_5P46_MS, - ADCBufCC26XX_SAMPLING_DURATION_10P9_MS = AUXADC_SAMPLE_TIME_10P9_MS + ADCBufCC26XX_SAMPLING_DURATION_2P7_US = AUXADC_SAMPLE_TIME_2P7_US, + ADCBufCC26XX_SAMPLING_DURATION_5P3_US = AUXADC_SAMPLE_TIME_5P3_US, + ADCBufCC26XX_SAMPLING_DURATION_10P6_US = AUXADC_SAMPLE_TIME_10P6_US, + ADCBufCC26XX_SAMPLING_DURATION_21P3_US = AUXADC_SAMPLE_TIME_21P3_US, + ADCBufCC26XX_SAMPLING_DURATION_42P6_US = AUXADC_SAMPLE_TIME_42P6_US, + ADCBufCC26XX_SAMPLING_DURATION_85P3_US = AUXADC_SAMPLE_TIME_85P3_US, + ADCBufCC26XX_SAMPLING_DURATION_170_US = AUXADC_SAMPLE_TIME_170_US, + ADCBufCC26XX_SAMPLING_DURATION_341_US = AUXADC_SAMPLE_TIME_341_US, + ADCBufCC26XX_SAMPLING_DURATION_682_US = AUXADC_SAMPLE_TIME_682_US, + ADCBufCC26XX_SAMPLING_DURATION_1P37_MS = AUXADC_SAMPLE_TIME_1P37_MS, + ADCBufCC26XX_SAMPLING_DURATION_2P73_MS = AUXADC_SAMPLE_TIME_2P73_MS, + ADCBufCC26XX_SAMPLING_DURATION_5P46_MS = AUXADC_SAMPLE_TIME_5P46_MS, + ADCBufCC26XX_SAMPLING_DURATION_10P9_MS = AUXADC_SAMPLE_TIME_10P9_MS } ADCBufCC26XX_Sampling_Duration; - /*! * @brief Specifies whether the internal reference of the ADC is sourced from the battery voltage or a fixed internal source. * @@ -441,12 +439,10 @@ typedef enum ADCBufCC26XX_Sampling_Duration */ typedef enum ADCBufCC26XX_Reference_Source { - ADCBufCC26XX_FIXED_REFERENCE = AUXADC_REF_FIXED, - ADCBufCC26XX_VDDS_REFERENCE = AUXADC_REF_VDDS_REL + ADCBufCC26XX_FIXED_REFERENCE = AUXADC_REF_FIXED, + ADCBufCC26XX_VDDS_REFERENCE = AUXADC_REF_VDDS_REL } ADCBufCC26XX_Reference_Source; - - /* * ============================================================================= * Structs @@ -454,15 +450,15 @@ typedef enum ADCBufCC26XX_Reference_Source */ /*! -* @brief Table entry that maps a virtual adc channel to a dio and its corresponding internal analogue signal -* -* Non-dio signals can be used as well. To do this, compBInput is set to the driverlib define corresponding to the -* desired non-dio signal and dio is set to PIN_UNASSIGNED. -*/ + * @brief Table entry that maps a virtual adc channel to a dio and its corresponding internal analogue signal + * + * Non-dio signals can be used as well. To do this, compBInput is set to the driverlib define corresponding to the + * desired non-dio signal and dio is set to PIN_UNASSIGNED. + */ typedef struct ADCBufCC26XX_AdcChannelLutEntry { - uint8_t dio; /*!< DIO that this virtual channel is mapped to */ - uint8_t compBInput; /*!< CompBInput that this virtual channel is mapped to */ + uint8_t dio; /*!< DIO that this virtual channel is mapped to */ + uint8_t compBInput; /*!< CompBInput that this virtual channel is mapped to */ } ADCBufCC26XX_AdcChannelLutEntry; /*! @@ -474,28 +470,28 @@ typedef struct ADCBufCC26XX_AdcChannelLutEntry */ typedef struct ADCBufCC26XX_ParamsExtension { - /*! Amount of time the ADC spends sampling the analogue input */ - ADCBufCC26XX_Sampling_Duration samplingDuration; - /*! Specifies whether the ADC spends a fixed amount of time sampling or the entire time since the last conversion */ - ADCBufCC26XX_Sampling_Mode samplingMode; - /*! Specifies whether the internal reference of the ADC is sourced from the battery voltage or a fixed internal source */ - ADCBufCC26XX_Reference_Source refSource; - /*! - * Disable input scaling. Input scaling scales an external analogue - * signal between 0 and 4.3V to an internal signal of 0 to ~1.4785V. - * Since the largest permissible input to any pin is VDDS, the maximum - * range of the ADC is effectively less than 3.8V and continues to shrink - * as the battery voltage drops. - * With input scaling disabled, the external analogue signal is passed - * on directly to the internal electronics. Signals larger than ~1.4785V - * will damage the device with input scaling disabled. - * - * | Input scaling status | Maximum permissible ADC input voltage | - * |---------------------------|---------------------------------------| - * | Enabled | VDDS (Battery voltage level) | - * | Disabled | 1.4785V | - */ - bool inputScalingEnabled; + /*! Amount of time the ADC spends sampling the analogue input */ + ADCBufCC26XX_Sampling_Duration samplingDuration; + /*! Specifies whether the ADC spends a fixed amount of time sampling or the entire time since the last conversion */ + ADCBufCC26XX_Sampling_Mode samplingMode; + /*! Specifies whether the internal reference of the ADC is sourced from the battery voltage or a fixed internal source */ + ADCBufCC26XX_Reference_Source refSource; + /*! + * Disable input scaling. Input scaling scales an external analogue + * signal between 0 and 4.3V to an internal signal of 0 to ~1.4785V. + * Since the largest permissible input to any pin is VDDS, the maximum + * range of the ADC is effectively less than 3.8V and continues to shrink + * as the battery voltage drops. + * With input scaling disabled, the external analogue signal is passed + * on directly to the internal electronics. Signals larger than ~1.4785V + * will damage the device with input scaling disabled. + * + * | Input scaling status | Maximum permissible ADC input voltage | + * |---------------------------|---------------------------------------| + * | Enabled | VDDS (Battery voltage level) | + * | Disabled | 1.4785V | + */ + bool inputScalingEnabled; } ADCBufCC26XX_ParamsExtension; /*! @@ -520,32 +516,30 @@ typedef struct ADCBufCC26XX_ParamsExtension */ typedef struct ADCBufCC26XX_HWAttrs { - /*! @brief ADC SWI priority. - The higher the number, the higher the priority. - The minimum is 0 and the maximum is 15 by default. - The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. - */ - uint32_t swiPriority; - /*! @brief ADC peripheral's interrupt priority. + /*! @brief ADC SWI priority. + The higher the number, the higher the priority. + The minimum is 0 and the maximum is 15 by default. + The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. + */ + uint32_t swiPriority; + /*! @brief ADC peripheral's interrupt priority. - The CC26xx uses three of the priority bits, - meaning ~0 has the same effect as (7 << 5). + The CC26xx uses three of the priority bits, + meaning ~0 has the same effect as (7 << 5). - (7 << 5) will apply the lowest priority. + (7 << 5) will apply the lowest priority. - (1 << 5) will apply the highest priority. + (1 << 5) will apply the highest priority. - Setting the priority to 0 is not supported by this driver. + Setting the priority to 0 is not supported by this driver. - HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. - */ - uint8_t intPriority; - /*! Pointer to a table of ADCBufCC26XX_AdcChannelLutEntry's mapping internal CompBInput to DIO */ - ADCBufCC26XX_AdcChannelLutEntry const* adcChannelLut; + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! Pointer to a table of ADCBufCC26XX_AdcChannelLutEntry's mapping internal CompBInput to DIO */ + ADCBufCC26XX_AdcChannelLutEntry const* adcChannelLut; } ADCBufCC26XX_HWAttrs; - - /*! * @brief ADCBufCC26XX Object * @@ -553,40 +547,40 @@ typedef struct ADCBufCC26XX_HWAttrs */ typedef struct ADCBufCC26XX_Object { - /* ADC control variables */ - bool isOpen; /*!< Has the obj been opened */ - bool conversionInProgress; /*!< Is the ADC currently doing conversions */ - bool inputScalingEnabled; /*!< Is the analogue input scaled */ - bool keepADCSemaphore; /*!< Should the driver keep the ADC semaphore after a conversion */ - bool adcSemaphoreInPossession; /*!< Does the driver currently possess the ADC semaphore */ - uint8_t currentChannel; /*!< The current virtual channel the ADCBuf driver is sampling on */ - ADCBufCC26XX_Reference_Source refSource; /*!< Reference source for the ADC to use */ - ADCBufCC26XX_Sampling_Mode samplingMode; /*!< Synchronous or asynchronous sampling mode */ - ADCBufCC26XX_Sampling_Duration samplingDuration; /*!< Time the ADC spends sampling in ADCBufCC26XX_SAMPING_MODE_SYNCHRONOUS */ - ADCBuf_Callback callbackFxn; /*!< Pointer to callback function */ - ADCBuf_Recurrence_Mode recurrenceMode; /*!< Should we convert continuously or one-shot */ - ADCBuf_Return_Mode returnMode; /*!< Mode for all conversions */ - uint16_t* activeSampleBuffer; /*!< The last complete sample buffer used by the DMA */ + /* ADC control variables */ + bool isOpen; /*!< Has the obj been opened */ + bool conversionInProgress; /*!< Is the ADC currently doing conversions */ + bool inputScalingEnabled; /*!< Is the analogue input scaled */ + bool keepADCSemaphore; /*!< Should the driver keep the ADC semaphore after a conversion */ + bool adcSemaphoreInPossession; /*!< Does the driver currently possess the ADC semaphore */ + uint8_t currentChannel; /*!< The current virtual channel the ADCBuf driver is sampling on */ + ADCBufCC26XX_Reference_Source refSource; /*!< Reference source for the ADC to use */ + ADCBufCC26XX_Sampling_Mode samplingMode; /*!< Synchronous or asynchronous sampling mode */ + ADCBufCC26XX_Sampling_Duration samplingDuration; /*!< Time the ADC spends sampling in ADCBufCC26XX_SAMPING_MODE_SYNCHRONOUS */ + ADCBuf_Callback callbackFxn; /*!< Pointer to callback function */ + ADCBuf_Recurrence_Mode recurrenceMode; /*!< Should we convert continuously or one-shot */ + ADCBuf_Return_Mode returnMode; /*!< Mode for all conversions */ + uint16_t* activeSampleBuffer; /*!< The last complete sample buffer used by the DMA */ - /* ADC SYS/BIOS objects */ - HwiP_Struct hwi; /*!< Hwi object */ - SwiP_Struct swi; /*!< Swi object */ - SemaphoreP_Struct conversionComplete; /*!< ADC semaphore */ + /* ADC SYS/BIOS objects */ + HwiP_Struct hwi; /*!< Hwi object */ + SwiP_Struct swi; /*!< Swi object */ + SemaphoreP_Struct conversionComplete; /*!< ADC semaphore */ - ADCBuf_Conversion* currentConversion; /*!< Pointer to the current conversion struct */ + ADCBuf_Conversion* currentConversion; /*!< Pointer to the current conversion struct */ - /* PIN driver state object and handle */ - PIN_State pinState; /*!< Pin state object */ - PIN_Handle pinHandle; /*!< Pin handle */ + /* PIN driver state object and handle */ + PIN_State pinState; /*!< Pin state object */ + PIN_Handle pinHandle; /*!< Pin handle */ - /* UDMA driver handle */ - UDMACC26XX_Handle udmaHandle; /*!< UDMA handle */ + /* UDMA driver handle */ + UDMACC26XX_Handle udmaHandle; /*!< UDMA handle */ - /* GPTimer driver handle */ - GPTimerCC26XX_Handle timerHandle; /*!< Handle to underlying GPTimer peripheral */ + /* GPTimer driver handle */ + GPTimerCC26XX_Handle timerHandle; /*!< Handle to underlying GPTimer peripheral */ - uint32_t semaphoreTimeout; /*!< Timeout for read semaphore in ::ADCBuf_RETURN_MODE_BLOCKING */ - uint32_t samplingFrequency; /*!< Frequency in Hz at which the ADC is triggered */ + uint32_t semaphoreTimeout; /*!< Timeout for read semaphore in ::ADCBuf_RETURN_MODE_BLOCKING */ + uint32_t samplingFrequency; /*!< Frequency in Hz at which the ADC is triggered */ } ADCBufCC26XX_Object, *ADCBufCC26XX_Handle; /* @@ -595,7 +589,6 @@ typedef struct ADCBufCC26XX_Object * ============================================================================= */ - #ifdef __cplusplus } #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aescbc/AESCBCCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aescbc/AESCBCCC26XX.h index ddf18d1..be7bd37 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aescbc/AESCBCCC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aescbc/AESCBCCC26XX.h @@ -76,8 +76,8 @@ extern "C" { #endif -#include #include +#include #include @@ -91,19 +91,19 @@ extern "C" { */ typedef struct AESCBCCC26XX_HWAttrs { - /*! @brief Crypto Peripheral's interrupt priority. + /*! @brief Crypto Peripheral's interrupt priority. - The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). - (7 << 5) will apply the lowest priority. + (7 << 5) will apply the lowest priority. - (1 << 5) will apply the highest priority. + (1 << 5) will apply the highest priority. - Setting the priority to 0 is not supported by this driver. + Setting the priority to 0 is not supported by this driver. - HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. - */ - uint8_t intPriority; + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; } AESCBCCC26XX_HWAttrs; /*! @@ -113,15 +113,15 @@ typedef struct AESCBCCC26XX_HWAttrs */ typedef struct AESCBCCC26XX_Object { - bool isOpen; - bool operationInProgress; - bool operationCanceled; - int_fast16_t returnStatus; - AESCBC_ReturnBehavior returnBehavior; - AESCBC_OperationType operationType; - uint32_t semaphoreTimeout; - AESCBC_CallbackFxn callbackFxn; - AESCBC_Operation* operation; + bool isOpen; + bool operationInProgress; + bool operationCanceled; + int_fast16_t returnStatus; + AESCBC_ReturnBehavior returnBehavior; + AESCBC_OperationType operationType; + uint32_t semaphoreTimeout; + AESCBC_CallbackFxn callbackFxn; + AESCBC_Operation* operation; } AESCBCCC26XX_Object; #ifdef __cplusplus diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesccm/AESCCMCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesccm/AESCCMCC26XX.h index 94399dc..23c6504 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesccm/AESCCMCC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesccm/AESCCMCC26XX.h @@ -76,16 +76,16 @@ extern "C" { #endif -#include #include +#include -#include #include +#include #include #include -#include #include +#include /*! * @brief AESCCMCC26XX Hardware Attributes @@ -95,19 +95,19 @@ extern "C" { */ typedef struct AESCCMCC26XX_HWAttrs { - /*! @brief Crypto Peripheral's interrupt priority. + /*! @brief Crypto Peripheral's interrupt priority. - The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). - (7 << 5) will apply the lowest priority. + (7 << 5) will apply the lowest priority. - (1 << 5) will apply the highest priority. + (1 << 5) will apply the highest priority. - Setting the priority to 0 is not supported by this driver. + Setting the priority to 0 is not supported by this driver. - HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. - */ - uint8_t intPriority; + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; } AESCCMCC26XX_HWAttrs; /*! @@ -117,15 +117,15 @@ typedef struct AESCCMCC26XX_HWAttrs */ typedef struct AESCCMCC26XX_Object { - bool isOpen; - bool operationInProgress; - bool operationCanceled; - int_fast16_t returnStatus; - AESCCM_ReturnBehavior returnBehavior; - AESCCM_OperationType operationType; - uint32_t semaphoreTimeout; - AESCCM_CallbackFxn callbackFxn; - AESCCM_Operation* operation; + bool isOpen; + bool operationInProgress; + bool operationCanceled; + int_fast16_t returnStatus; + AESCCM_ReturnBehavior returnBehavior; + AESCCM_OperationType operationType; + uint32_t semaphoreTimeout; + AESCCM_CallbackFxn callbackFxn; + AESCCM_Operation* operation; } AESCCMCC26XX_Object; #ifdef __cplusplus diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesctr/AESCTRCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesctr/AESCTRCC26XX.h index b6b17b4..44ec66a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesctr/AESCTRCC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesctr/AESCTRCC26XX.h @@ -75,8 +75,8 @@ extern "C" { #endif -#include #include +#include #include @@ -88,19 +88,19 @@ extern "C" { */ typedef struct { - /*! @brief Crypto Peripheral's interrupt priority. + /*! @brief Crypto Peripheral's interrupt priority. - The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). - (7 << 5) will apply the lowest priority. + (7 << 5) will apply the lowest priority. - (1 << 5) will apply the highest priority. + (1 << 5) will apply the highest priority. - Setting the priority to 0 is not supported by this driver. + Setting the priority to 0 is not supported by this driver. - HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. - */ - uint8_t intPriority; + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; } AESCTRCC26XX_HWAttrs; /*! @@ -110,16 +110,16 @@ typedef struct */ typedef struct { - bool isOpen; - bool operationInProgress; - bool operationCanceled; - bool threadSafe; - int_fast16_t returnStatus; - AESCTR_ReturnBehavior returnBehavior; - AESCTR_OperationType operationType; - uint32_t semaphoreTimeout; - AESCTR_CallbackFxn callbackFxn; - AESCTR_Operation* operation; + bool isOpen; + bool operationInProgress; + bool operationCanceled; + bool threadSafe; + int_fast16_t returnStatus; + AESCTR_ReturnBehavior returnBehavior; + AESCTR_OperationType operationType; + uint32_t semaphoreTimeout; + AESCTR_CallbackFxn callbackFxn; + AESCTR_Operation* operation; } AESCTRCC26XX_Object; #ifdef __cplusplus diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.h index 0c30edd..7ae6e6a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesctrdrbg/AESCTRDRBGXX.h @@ -59,8 +59,8 @@ #ifndef ti_drivers_aesctrdrbg_AESCTRDRBGXX__include #define ti_drivers_aesctrdrbg_AESCTRDRBGXX__include -#include #include +#include #include @@ -92,7 +92,7 @@ extern "C" { */ typedef struct { - uint_least8_t aesctrIndex; /*! Index into AESCTR_config array */ + uint_least8_t aesctrIndex; /*! Index into AESCTR_config array */ } AESCTRDRBGXX_HWAttrs; /*! @@ -102,15 +102,15 @@ typedef struct */ typedef struct { - uint8_t keyingMaterial[AESCTRDRBG_AES_KEY_LENGTH_256]; - uint8_t counter[AESCTRDRBG_AES_BLOCK_SIZE_BYTES]; - CryptoKey key; - AESCTR_Handle ctrHandle; - size_t seedLength; - uint32_t reseedCounter; - uint32_t reseedInterval; - int_fast16_t returnStatus; - bool isOpen; + uint8_t keyingMaterial[AESCTRDRBG_AES_KEY_LENGTH_256]; + uint8_t counter[AESCTRDRBG_AES_BLOCK_SIZE_BYTES]; + CryptoKey key; + AESCTR_Handle ctrHandle; + size_t seedLength; + uint32_t reseedCounter; + uint32_t reseedInterval; + int_fast16_t returnStatus; + bool isOpen; } AESCTRDRBGXX_Object; #ifdef __cplusplus diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesecb/AESECBCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesecb/AESECBCC26XX.h index 1f9c085..980d75f 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesecb/AESECBCC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesecb/AESECBCC26XX.h @@ -76,16 +76,16 @@ extern "C" { #endif -#include #include +#include -#include #include +#include #include #include -#include #include +#include /*! * @brief AESECBCC26XX Hardware Attributes @@ -95,19 +95,19 @@ extern "C" { */ typedef struct AESECBCC26XX_HWAttrs { - /*! @brief Crypto Peripheral's interrupt priority. + /*! @brief Crypto Peripheral's interrupt priority. - The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). - (7 << 5) will apply the lowest priority. + (7 << 5) will apply the lowest priority. - (1 << 5) will apply the highest priority. + (1 << 5) will apply the highest priority. - Setting the priority to 0 is not supported by this driver. + Setting the priority to 0 is not supported by this driver. - HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. - */ - uint8_t intPriority; + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; } AESECBCC26XX_HWAttrs; /*! @@ -117,15 +117,15 @@ typedef struct AESECBCC26XX_HWAttrs */ typedef struct AESECBCC26XX_Object { - bool isOpen; - bool operationInProgress; - bool operationCanceled; - int_fast16_t returnStatus; - AESECB_ReturnBehavior returnBehavior; - AESECB_OperationType operationType; - uint32_t semaphoreTimeout; - AESECB_CallbackFxn callbackFxn; - AESECB_Operation* operation; + bool isOpen; + bool operationInProgress; + bool operationCanceled; + int_fast16_t returnStatus; + AESECB_ReturnBehavior returnBehavior; + AESECB_OperationType operationType; + uint32_t semaphoreTimeout; + AESECB_CallbackFxn callbackFxn; + AESECB_Operation* operation; } AESECBCC26XX_Object; #ifdef __cplusplus diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesgcm/AESGCMCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesgcm/AESGCMCC26XX.h index fca5a1a..a7637b5 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesgcm/AESGCMCC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/aesgcm/AESGCMCC26XX.h @@ -76,16 +76,16 @@ extern "C" { #endif -#include #include +#include -#include #include +#include #include #include -#include #include +#include /*! * @brief AESGCMCC26XX Hardware Attributes @@ -95,19 +95,19 @@ extern "C" { */ typedef struct AESGCMCC26XX_HWAttrs { - /*! @brief Crypto Peripheral's interrupt priority. + /*! @brief Crypto Peripheral's interrupt priority. - The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). - (7 << 5) will apply the lowest priority. + (7 << 5) will apply the lowest priority. - (1 << 5) will apply the highest priority. + (1 << 5) will apply the highest priority. - Setting the priority to 0 is not supported by this driver. + Setting the priority to 0 is not supported by this driver. - HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. - */ - uint8_t intPriority; + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; } AESGCMCC26XX_HWAttrs; /*! @@ -117,15 +117,15 @@ typedef struct AESGCMCC26XX_HWAttrs */ typedef struct AESGCMCC26XX_Object { - bool isOpen; - bool operationInProgress; - bool operationCanceled; - int_fast16_t returnStatus; - AESGCM_ReturnBehavior returnBehavior; - AESGCM_OperationType operationType; - uint32_t semaphoreTimeout; - AESGCM_CallbackFxn callbackFxn; - AESGCM_Operation* operation; + bool isOpen; + bool operationInProgress; + bool operationCanceled; + int_fast16_t returnStatus; + AESGCM_ReturnBehavior returnBehavior; + AESGCM_OperationType operationType; + uint32_t semaphoreTimeout; + AESGCM_CallbackFxn callbackFxn; + AESGCM_Operation* operation; } AESGCMCC26XX_Object; #ifdef __cplusplus diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/crypto/CryptoCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/crypto/CryptoCC26XX.h index 02009b2..363818c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/crypto/CryptoCC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/crypto/CryptoCC26XX.h @@ -409,13 +409,13 @@ extern "C" { #endif -#include #include +#include #include #include -#include DeviceFamily_constructPath(driverlib/crypto.h) +#include DeviceFamily_constructPath(driverlib / crypto.h) #if DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2 #warning "This driver is deprecated for the CC26x2 and CC13x2 families.\ @@ -452,27 +452,26 @@ It is superceded by AESECB and AESCCM." #define CRYPTOCC26XX_TIMEOUT 20 /*!< Timeout Return Code */ -#define CRYPTOCC26XX_STATUS_SUCCESS 0 /*!< Success Return Code */ -#define CRYPTOCC26XX_STATUS_ERROR -1 /*!< Error Return Code */ -#define CRYPTOCC26XX_STATUS_UNDEFINEDCMD -2 /*!< Command Undefined Return Code */ +#define CRYPTOCC26XX_STATUS_SUCCESS 0 /*!< Success Return Code */ +#define CRYPTOCC26XX_STATUS_ERROR -1 /*!< Error Return Code */ +#define CRYPTOCC26XX_STATUS_UNDEFINEDCMD -2 /*!< Command Undefined Return Code */ -#define CRYPTOCC26XX_OP_AES_CCM_ENCRYPT 0 /*!< AES-CCM encryption of both AAD and plain text */ -#define CRYPTOCC26XX_OP_AES_CCM_ENCRYPT_AAD_ONLY 1 /*!< AES-CCM authentication of ADD only */ -#define CRYPTOCC26XX_OP_AES_CCM_DECRYPT 2 /*!< AES-CCM decryption of both AAD and plain text and verification of both */ -#define CRYPTOCC26XX_OP_AES_CCM_DECRYPT_AAD_ONLY 3 /*!< AES-CCM verification of ADD only */ -#define CRYPTOCC26XX_OP_AES_ECB_ENCRYPT 4 /*!< AES-ECB encryption */ -#define CRYPTOCC26XX_OP_AES_ECB_DECRYPT 5 /*!< AES-ECB decryption */ -#define CRYPTOCC26XX_OP_AES_CBC_ENCRYPT 6 /*!< AES-CBC encryption */ -#define CRYPTOCC26XX_OP_AES_CBC_DECRYPT 7 /*!< AES-CBC decryption */ +#define CRYPTOCC26XX_OP_AES_CCM_ENCRYPT 0 /*!< AES-CCM encryption of both AAD and plain text */ +#define CRYPTOCC26XX_OP_AES_CCM_ENCRYPT_AAD_ONLY 1 /*!< AES-CCM authentication of ADD only */ +#define CRYPTOCC26XX_OP_AES_CCM_DECRYPT 2 /*!< AES-CCM decryption of both AAD and plain text and verification of both */ +#define CRYPTOCC26XX_OP_AES_CCM_DECRYPT_AAD_ONLY 3 /*!< AES-CCM verification of ADD only */ +#define CRYPTOCC26XX_OP_AES_ECB_ENCRYPT 4 /*!< AES-ECB encryption */ +#define CRYPTOCC26XX_OP_AES_ECB_DECRYPT 5 /*!< AES-ECB decryption */ +#define CRYPTOCC26XX_OP_AES_CBC_ENCRYPT 6 /*!< AES-CBC encryption */ +#define CRYPTOCC26XX_OP_AES_CBC_DECRYPT 7 /*!< AES-CBC decryption */ /* Deprecated operation mode names */ -#define CRYPTOCC26XX_OP_AES_CCM CRYPTOCC26XX_OP_AES_CCM_ENCRYPT -#define CRYPTOCC26XX_OP_AES_CCM_NOCRYPT CRYPTOCC26XX_OP_AES_CCM_ENCRYPT_AAD_ONLY -#define CRYPTOCC26XX_OP_AES_CCMINV CRYPTOCC26XX_OP_AES_CCM_DECRYPT -#define CRYPTOCC26XX_OP_AES_CCMINV_NOCRYPT CRYPTOCC26XX_OP_AES_CCM_DECRYPT_AAD_ONLY -#define CRYPTOCC26XX_OP_AES_ECB CRYPTOCC26XX_OP_AES_ECB_ENCRYPT -#define CRYPTOCC26XX_OP_AES_ECB_NOCRYPT CRYPTOCC26XX_OP_AES_ECB_DECRYPT - +#define CRYPTOCC26XX_OP_AES_CCM CRYPTOCC26XX_OP_AES_CCM_ENCRYPT +#define CRYPTOCC26XX_OP_AES_CCM_NOCRYPT CRYPTOCC26XX_OP_AES_CCM_ENCRYPT_AAD_ONLY +#define CRYPTOCC26XX_OP_AES_CCMINV CRYPTOCC26XX_OP_AES_CCM_DECRYPT +#define CRYPTOCC26XX_OP_AES_CCMINV_NOCRYPT CRYPTOCC26XX_OP_AES_CCM_DECRYPT_AAD_ONLY +#define CRYPTOCC26XX_OP_AES_ECB CRYPTOCC26XX_OP_AES_ECB_ENCRYPT +#define CRYPTOCC26XX_OP_AES_ECB_NOCRYPT CRYPTOCC26XX_OP_AES_ECB_DECRYPT #include #include @@ -480,7 +479,7 @@ It is superceded by AESECB and AESCCM." /*! * @brief A handle that is returned from a CryptoCC26XX_open() call. */ -typedef struct CryptoCC26XX_Config* CryptoCC26XX_Handle; +typedef struct CryptoCC26XX_Config* CryptoCC26XX_Handle; /*! * @brief CryptoCC26XX Mode Settings @@ -491,15 +490,15 @@ typedef struct CryptoCC26XX_Config* CryptoCC26XX_Handle; typedef enum CryptoCC26XX_Mode { /*! - * Uses a semaphore to block while data is being sent. Context of the call - * must be a Task. - */ + * Uses a semaphore to block while data is being sent. Context of the call + * must be a Task. + */ CRYPTOCC26XX_MODE_BLOCKING, /*! - * Will return when the operation has finished. Call can be made from - * hwi and swi context. - */ + * Will return when the operation has finished. Call can be made from + * hwi and swi context. + */ CRYPTOCC26XX_MODE_POLLING } CryptoCC26XX_Mode; @@ -542,7 +541,7 @@ typedef enum CryptoCC26XX_KeyLocation */ typedef struct CryptoCC26XX_Params { - uint32_t timeout; /*!< Timeout for read semaphore */ + uint32_t timeout; /*!< Timeout for read semaphore */ } CryptoCC26XX_Params; /*! @@ -563,9 +562,9 @@ typedef uint8_t CryptoCC26XX_KeyStore; */ typedef struct CryptoCC26XX_Transaction { - CryptoCC26XX_Operation opType; /*!< The type of the crypto operation */ - CryptoCC26XX_Mode mode; /*!< The mode of current transaction */ - uint8_t data[]; /*!< A void pointer to rest of transaction (transac. specific) */ + CryptoCC26XX_Operation opType; /*!< The type of the crypto operation */ + CryptoCC26XX_Mode mode; /*!< The mode of current transaction */ + uint8_t data[]; /*!< A void pointer to rest of transaction (transac. specific) */ } CryptoCC26XX_Transaction; /*! @@ -620,55 +619,55 @@ typedef struct CryptoCC26XX_Transaction */ typedef struct CryptoCC26XX_AESCCM_Transaction { - CryptoCC26XX_Operation opType; /*!< The type of the crypto operation */ - CryptoCC26XX_Mode mode; /*!< The mode of current transaction. Set by transact function. */ - uint8_t keyIndex; /*!< The key store index to be used */ - uint8_t authLength; /*!< Is the the length of the authentication field */ - /*!< 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets. */ - char* nonce; /*!< A pointer to a nonce. It must satisfy the equation 15 = q + n, - * where q is the fieldLength and n is the length of the nonce. - * - * The minimum size of the array containing the nonce is 12 bytes. - * When using nonces of length < 12 bytes, the nonce must be zero-padded - * to 12 bytes. The driverlib implementation in ROM was written - * with 12 and 13-byte nonces in mind. It constructs the IV's - * internally and hence copies either 12 or 13 bytes into another buffer. - * Providing a nonce buffer with less than 12 bytes would result in - * whatever is after the nonce in memory being incorrectly copied - * into the IV's. - * - * As long as the correct fieldLength is set for the < 12-bytes nonce, - * the correct nonce-length will be used. - * - * Valid nonce lengths are {7, 8, 9, 10, 11, 12, 13}. - */ - char* msgIn; /*!< - * - Encryption: A pointer to the octet string input message and after the transaction, - * the location of the encrypted cleartext. The cleatext is encrypted in place. - * - Decryption: A pointer to the encrypted ciphertext composed of the encrypted cleartext - * concatenated with the encrypted message authentication code. - */ - char* header; /*!< The Additional Authentication Data (AAD). This header is authenticated but not encrypted. */ - void* msgOut; /*!< A pointer to where the encrypted CBC-MAC shall be written to. - * - Encryption: It is recommended to set this to msgIn + msgInLength. The cyphertext sent out - * must be the concatenation of the encrypted message and encrypted MAC anyway. - * - Decyption: Do NOT set msgOut to the same location as the received MAC in the - * cyphertext within msgIn! Doing this effectively disables verification. - */ - uint8_t fieldLength; /*!< This parameter specifies the size in bytes of the message length field. - * (Not the length of the message itself!) - * - * It sets the maximum length of the message - * according to p < 2^(8*q) where p is the message length and q is the fieldLength. - * - * It must satisfy the equation 15 = q + n where q is the fieldLength and n is the - * length of the nonce. - * - * Valid values are {2, 3, 4, 5, 6, 7, 8}. - */ - uint16_t msgInLength; /*!< - Encryption: The length of the cleartext. - - Decryption: The length of the ciphertext. */ - uint16_t headerLength; /*!< The length of the header in octets */ + CryptoCC26XX_Operation opType; /*!< The type of the crypto operation */ + CryptoCC26XX_Mode mode; /*!< The mode of current transaction. Set by transact function. */ + uint8_t keyIndex; /*!< The key store index to be used */ + uint8_t authLength; /*!< Is the the length of the authentication field */ + /*!< 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets. */ + char* nonce; /*!< A pointer to a nonce. It must satisfy the equation 15 = q + n, + * where q is the fieldLength and n is the length of the nonce. + * + * The minimum size of the array containing the nonce is 12 bytes. + * When using nonces of length < 12 bytes, the nonce must be zero-padded + * to 12 bytes. The driverlib implementation in ROM was written + * with 12 and 13-byte nonces in mind. It constructs the IV's + * internally and hence copies either 12 or 13 bytes into another buffer. + * Providing a nonce buffer with less than 12 bytes would result in + * whatever is after the nonce in memory being incorrectly copied + * into the IV's. + * + * As long as the correct fieldLength is set for the < 12-bytes nonce, + * the correct nonce-length will be used. + * + * Valid nonce lengths are {7, 8, 9, 10, 11, 12, 13}. + */ + char* msgIn; /*!< + * - Encryption: A pointer to the octet string input message and after the transaction, + * the location of the encrypted cleartext. The cleatext is encrypted in place. + * - Decryption: A pointer to the encrypted ciphertext composed of the encrypted cleartext + * concatenated with the encrypted message authentication code. + */ + char* header; /*!< The Additional Authentication Data (AAD). This header is authenticated but not encrypted. */ + void* msgOut; /*!< A pointer to where the encrypted CBC-MAC shall be written to. + * - Encryption: It is recommended to set this to msgIn + msgInLength. The cyphertext sent out + * must be the concatenation of the encrypted message and encrypted MAC anyway. + * - Decyption: Do NOT set msgOut to the same location as the received MAC in the + * cyphertext within msgIn! Doing this effectively disables verification. + */ + uint8_t fieldLength; /*!< This parameter specifies the size in bytes of the message length field. + * (Not the length of the message itself!) + * + * It sets the maximum length of the message + * according to p < 2^(8*q) where p is the message length and q is the fieldLength. + * + * It must satisfy the equation 15 = q + n where q is the fieldLength and n is the + * length of the nonce. + * + * Valid values are {2, 3, 4, 5, 6, 7, 8}. + */ + uint16_t msgInLength; /*!< - Encryption: The length of the cleartext. + - Decryption: The length of the ciphertext. */ + uint16_t headerLength; /*!< The length of the header in octets */ } CryptoCC26XX_AESCCM_Transaction; /*! @@ -679,13 +678,13 @@ typedef struct CryptoCC26XX_AESCCM_Transaction */ typedef struct CryptoCC26XX_AESCBC_Transaction { - CryptoCC26XX_Operation opType; /*!< The type of the crypto operation */ - CryptoCC26XX_Mode mode; /*!< The mode of current transaction. Set by transact function. */ - uint8_t keyIndex; /*!< The key store index to be used */ - void* nonce; /*!< A pointer to 16 byte Nonce. */ - void* msgIn; /*!< A pointer to the octet string input message */ - void* msgOut; /*!< A pointer to the output message location */ - uint16_t msgInLength; /*!< The length of the message */ + CryptoCC26XX_Operation opType; /*!< The type of the crypto operation */ + CryptoCC26XX_Mode mode; /*!< The mode of current transaction. Set by transact function. */ + uint8_t keyIndex; /*!< The key store index to be used */ + void* nonce; /*!< A pointer to 16 byte Nonce. */ + void* msgIn; /*!< A pointer to the octet string input message */ + void* msgOut; /*!< A pointer to the output message location */ + uint16_t msgInLength; /*!< The length of the message */ } CryptoCC26XX_AESCBC_Transaction; /*! @@ -696,11 +695,11 @@ typedef struct CryptoCC26XX_AESCBC_Transaction */ typedef struct CryptoCC26XX_AESECB_Transaction { - CryptoCC26XX_Operation opType; /*!< The type of the crypto operation */ - CryptoCC26XX_Mode mode; /*!< The mode of current transaction. Set by transact function. */ - uint8_t keyIndex; /*!< The key store index to be used. */ - void* msgIn; /*!< A poiner to the octet string input message */ - void* msgOut; /*!< A pointer to the output message location */ + CryptoCC26XX_Operation opType; /*!< The type of the crypto operation */ + CryptoCC26XX_Mode mode; /*!< The mode of current transaction. Set by transact function. */ + uint8_t keyIndex; /*!< The key store index to be used. */ + void* msgIn; /*!< A poiner to the octet string input message */ + void* msgOut; /*!< A pointer to the output message location */ } CryptoCC26XX_AESECB_Transaction; /*! @@ -734,25 +733,25 @@ typedef struct CryptoCC26XX_AESECB_Transaction */ typedef struct CryptoCC26XX_HWAttrs { - /*! Crypto Peripheral's base address */ - uint32_t baseAddr; - /*! Crypto Peripheral's power manager ID */ - int powerMngrId; - /*! Crypto Peripheral's interrupt vector */ - int intNum; - /*! @brief Crypto Peripheral's interrupt priority. + /*! Crypto Peripheral's base address */ + uint32_t baseAddr; + /*! Crypto Peripheral's power manager ID */ + int powerMngrId; + /*! Crypto Peripheral's interrupt vector */ + int intNum; + /*! @brief Crypto Peripheral's interrupt priority. - The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). - (7 << 5) will apply the lowest priority. + (7 << 5) will apply the lowest priority. - (1 << 5) will apply the highest priority. + (1 << 5) will apply the highest priority. - Setting the priority to 0 is not supported by this driver. + Setting the priority to 0 is not supported by this driver. - HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. - */ - uint8_t intPriority; + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; } CryptoCC26XX_HWAttrs; /*! @@ -762,27 +761,27 @@ typedef struct CryptoCC26XX_HWAttrs */ typedef struct CryptoCC26XX_Object { - /* CryptoCC26XX control variables */ - int openCnt; /*!< Counting number of clients */ - uint32_t timeout; /*!< Timeout for encrypt/decrypt operation */ - CryptoCC26XX_KeyStore keyStore; /*!< Key store for Crypto */ - CryptoCC26XX_Transaction* currentTransact; /*!< Pointer to ongoing transaction */ + /* CryptoCC26XX control variables */ + int openCnt; /*!< Counting number of clients */ + uint32_t timeout; /*!< Timeout for encrypt/decrypt operation */ + CryptoCC26XX_KeyStore keyStore; /*!< Key store for Crypto */ + CryptoCC26XX_Transaction* currentTransact; /*!< Pointer to ongoing transaction */ - /*! Crypto notification object */ - Power_NotifyObj cryptoNotiObj; + /*! Crypto notification object */ + Power_NotifyObj cryptoNotiObj; - /* CryptoCC26XX SYS/BIOS objects */ - HwiP_Struct hwi; /*!< Hwi object */ + /* CryptoCC26XX SYS/BIOS objects */ + HwiP_Struct hwi; /*!< Hwi object */ } CryptoCC26XX_Object; /*! @brief CryptoCC26XX Global Configuration */ typedef struct CryptoCC26XX_Config { - /*! Pointer to a driver specific data object */ - void* object; + /*! Pointer to a driver specific data object */ + void* object; - /*! Pointer to a driver specific hardware attributes structure */ - void const* hwAttrs; + /*! Pointer to a driver specific hardware attributes structure */ + void const* hwAttrs; } CryptoCC26XX_Config; /*! @@ -892,7 +891,6 @@ void CryptoCC26XX_Transac_init(CryptoCC26XX_Transaction* trans, CryptoCC26XX_Ope */ int CryptoCC26XX_allocateKey(CryptoCC26XX_Handle handle, CryptoCC26XX_KeyLocation keyLocation, const uint32_t* keySrc); - /*! * @brief Function that writes a given key into a key store * diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.h index fd4e51f..ac16be0 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/cryptokey/CryptoKey.h @@ -88,19 +88,18 @@ extern "C" { #endif -#include #include +#include /*! */ /** -* @defgroup CryptoKey_CONTROL Status codes -* These CryptoKey macros are reservations for CryptoKey.h -* @{ -*/ - + * @defgroup CryptoKey_CONTROL Status codes + * These CryptoKey macros are reservations for CryptoKey.h + * @{ + */ /*! * Common CryptoKey_control status code reservation offset. @@ -114,7 +113,7 @@ extern "C" { * #define CryptoKeyXYZ_STATUS_ERROR2 CryptoKey_STATUS_RESERVED - 2 * @endcode */ -#define CryptoKey_STATUS_RESERVED (-32) +#define CryptoKey_STATUS_RESERVED (-32) /** * @defgroup CryptoKey_STATUS Status Codes @@ -129,7 +128,7 @@ extern "C" { * CryptoKey_control() returns CryptoKey_STATUS_SUCCESS if the control code was executed * successfully. */ -#define CryptoKey_STATUS_SUCCESS (0) +#define CryptoKey_STATUS_SUCCESS (0) /*! * @brief Generic error status code @@ -137,7 +136,7 @@ extern "C" { * CryptoKey_control() returns CryptoKey_STATUS_ERROR if the control code was not executed * successfully. */ -#define CryptoKey_STATUS_ERROR (-1) +#define CryptoKey_STATUS_ERROR (-1) /*! * @brief Returned if the encoding of a CryptoKey is not a CryptoKey_Encoding value @@ -145,8 +144,7 @@ extern "C" { * CryptoKey_control() returns CryptoKey_STATUS_ERROR if the control code was not executed * successfully. */ -#define CryptoKey_STATUS_UNDEFINED_ENCODING (-2) - +#define CryptoKey_STATUS_UNDEFINED_ENCODING (-2) /** @}*/ @@ -158,12 +156,12 @@ extern "C" { */ typedef enum CryptoKey_Encoding_ { - CryptoKey_PLAINTEXT = 1 << 1, - CryptoKey_BLANK_PLAINTEXT = 1 << 2, - CryptoKey_KEYSTORE = 1 << 3, - CryptoKey_BLANK_KEYSTORE = 1 << 4, - CryptoKey_KEYBLOB = 1 << 5, - CryptoKey_BLANK_KEYBLOB = 1 << 6, + CryptoKey_PLAINTEXT = 1 << 1, + CryptoKey_BLANK_PLAINTEXT = 1 << 2, + CryptoKey_KEYSTORE = 1 << 3, + CryptoKey_BLANK_KEYSTORE = 1 << 4, + CryptoKey_KEYBLOB = 1 << 5, + CryptoKey_BLANK_KEYBLOB = 1 << 6, } CryptoKey_Encoding; /*! @@ -174,8 +172,8 @@ typedef enum CryptoKey_Encoding_ */ typedef struct CryptoKey_Plaintext_ { - uint8_t* keyMaterial; - uint16_t keyLength; + uint8_t* keyMaterial; + uint16_t keyLength; } CryptoKey_Plaintext; /*! @@ -186,9 +184,9 @@ typedef struct CryptoKey_Plaintext_ */ typedef struct CryptoKey_KeyStore_ { - void* keyStore; - uint16_t keyLength; - uint32_t keyIndex; + void* keyStore; + uint16_t keyLength; + uint32_t keyIndex; } CryptoKey_KeyStore; /*! @@ -199,8 +197,8 @@ typedef struct CryptoKey_KeyStore_ */ typedef struct CryptoKey_KeyBlob_ { - uint8_t* keyBlob; - uint32_t keyBlobLength; + uint8_t* keyBlob; + uint32_t keyBlobLength; } CryptoKey_KeyBlob; /*! @@ -213,16 +211,15 @@ typedef struct CryptoKey_KeyBlob_ */ typedef struct CryptoKey_ { - CryptoKey_Encoding encoding; - union - { - CryptoKey_Plaintext plaintext; - CryptoKey_KeyStore keyStore; - CryptoKey_KeyBlob keyBlob; - } u; + CryptoKey_Encoding encoding; + union + { + CryptoKey_Plaintext plaintext; + CryptoKey_KeyStore keyStore; + CryptoKey_KeyBlob keyBlob; + } u; } CryptoKey; - /*! * @brief Structure that specifies the restrictions on a CryptoKey * diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.h index a63864d..7c2396d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/cryptokey/CryptoKeyPlaintext.h @@ -65,9 +65,9 @@ #ifndef ti_drivers_cryptoutils_cyptokey_CryptoKeyPlaintext__include #define ti_drivers_cryptoutils_cyptokey_CryptoKeyPlaintext__include +#include #include #include -#include #include @@ -88,7 +88,6 @@ extern "C" { */ int_fast16_t CryptoKeyPlaintext_initKey(CryptoKey* keyHandle, uint8_t* key, size_t keyLength); - /*! * @brief Initializes an empty plaintext CryptoKey type * @@ -128,7 +127,6 @@ int_fast16_t CryptoKeyPlaintext_getKeyLength(CryptoKey* keyHandle, size_t* lengt */ int_fast16_t CryptoKeyPlaintext_setKeyLocation(CryptoKey* keyHandle, uint8_t* location); - /*! * @brief Gets the length of a plaintext key * diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/ecc/ECCParams.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/ecc/ECCParams.h index 5e7217d..27a9167 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/ecc/ECCParams.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/ecc/ECCParams.h @@ -43,8 +43,8 @@ extern "C" { #endif -#include #include +#include #include @@ -56,7 +56,7 @@ extern "C" { * Function return ECCParams_STATUS_SUCCESS if the control code was executed * successfully. */ -#define ECCParams_STATUS_SUCCESS (0) +#define ECCParams_STATUS_SUCCESS (0) /*! * @brief Generic error status code. @@ -64,7 +64,7 @@ extern "C" { * Functions return ECCParams_STATUS_ERROR if the control code was not executed * successfully. */ -#define ECCParams_STATUS_ERROR (-1) +#define ECCParams_STATUS_ERROR (-1) /*! * @brief Enumeration of curve equations supported. @@ -111,18 +111,15 @@ typedef enum ECCParams_CurveType_ */ typedef struct ECCParams_CurveParams_ { - const ECCParams_CurveType curveType; - const size_t length; //!< Length of the curve in bytes. All other buffers have this length. - const uint8_t* prime; //!< The prime that defines the field of the curve. - const uint8_t* order; //!< Order of the curve. - const uint8_t* a; //!< Coefficient a of the equation. - const uint8_t* b; //!< Coefficient b of the equation. - const uint8_t* generatorX; //!< X coordinate of the generator point of the curve. - const uint8_t* generatorY; //!< Y coordinate of the generator point of the curve. -} -ECCParams_CurveParams; - - + const ECCParams_CurveType curveType; + const size_t length; //!< Length of the curve in bytes. All other buffers have this length. + const uint8_t* prime; //!< The prime that defines the field of the curve. + const uint8_t* order; //!< Order of the curve. + const uint8_t* a; //!< Coefficient a of the equation. + const uint8_t* b; //!< Coefficient b of the equation. + const uint8_t* generatorX; //!< X coordinate of the generator point of the curve. + const uint8_t* generatorY; //!< Y coordinate of the generator point of the curve. +} ECCParams_CurveParams; /* Short Weierstrass curves */ @@ -175,8 +172,6 @@ extern const ECCParams_CurveParams ECCParams_BrainpoolP384R1; */ extern const ECCParams_CurveParams ECCParams_BrainpoolP512R1; - - /* Montgomery curves */ /*! @@ -186,8 +181,6 @@ extern const ECCParams_CurveParams ECCParams_BrainpoolP512R1; */ extern const ECCParams_CurveParams ECCParams_Curve25519; - - /* Edwards curves */ /* Utility functions */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceCC26XX.h index 466516b..db2ce4d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceCC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/sharedresources/CryptoResourceCC26XX.h @@ -43,20 +43,18 @@ extern "C" { #endif -#include #include +#include #include /* Crypto driver semaphore used to synchronize accesses to the keyStore, AES, and SHA2 engine */ -extern SemaphoreP_Struct CryptoResourceCC26XX_accessSemaphore; -extern SemaphoreP_Struct CryptoResourceCC26XX_operationSemaphore; - -extern volatile bool CryptoResourceCC26XX_pollingFlag; - -extern HwiP_Struct CryptoResourceCC26XX_hwi; +extern SemaphoreP_Struct CryptoResourceCC26XX_accessSemaphore; +extern SemaphoreP_Struct CryptoResourceCC26XX_operationSemaphore; +extern volatile bool CryptoResourceCC26XX_pollingFlag; +extern HwiP_Struct CryptoResourceCC26XX_hwi; void CryptoResourceCC26XX_constructRTOSObjects(void); void CryptoResourceCC26XX_destructRTOSObjects(void); diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/sharedresources/PKAResourceCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/sharedresources/PKAResourceCC26XX.h index e8f1b07..bede1f4 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/sharedresources/PKAResourceCC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/cryptoutils/sharedresources/PKAResourceCC26XX.h @@ -43,20 +43,18 @@ extern "C" { #endif -#include #include +#include #include /* PKA driver semaphore used to synchronize accesses to the PKA engine */ -extern SemaphoreP_Struct PKAResourceCC26XX_accessSemaphore; -extern SemaphoreP_Struct PKAResourceCC26XX_operationSemaphore; - -extern volatile bool PKAResourceCC26XX_pollingFlag; - -extern HwiP_Struct PKAResourceCC26XX_hwi; +extern SemaphoreP_Struct PKAResourceCC26XX_accessSemaphore; +extern SemaphoreP_Struct PKAResourceCC26XX_operationSemaphore; +extern volatile bool PKAResourceCC26XX_pollingFlag; +extern HwiP_Struct PKAResourceCC26XX_hwi; void PKAResourceCC26XX_constructRTOSObjects(void); void PKAResourceCC26XX_destructRTOSObjects(void); diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dma/UDMACC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dma/UDMACC26XX.h index 92db1f8..84f630f 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dma/UDMACC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dma/UDMACC26XX.h @@ -115,15 +115,15 @@ extern "C" { #endif -#include #include +#include #include #include #include -#include DeviceFamily_constructPath(inc/hw_types.h) -#include DeviceFamily_constructPath(driverlib/udma.h) +#include DeviceFamily_constructPath(inc / hw_types.h) +#include DeviceFamily_constructPath(driverlib / udma.h) /** * @addtogroup DMA_STATUS @@ -161,28 +161,29 @@ extern "C" { #endif /*! Make sure DMA control table base address is 1024 bytes aligned */ -#if(UDMACC26XX_CONFIG_BASE & 0x3FF) +#if (UDMACC26XX_CONFIG_BASE & 0x3FF) #error "Base address for DMA control table 'UDMACC26XX_CONFIG_BASE' must be 1024 bytes aligned." #endif /*! Compiler specific macros to allocate DMA control table entries */ #if defined(__IAR_SYSTEMS_ICC__) #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \ - __no_init static volatile tDMAControlTable ENTRY_NAME @ UDMACC26XX_CONFIG_BASE + CHANNEL_INDEX * sizeof(tDMAControlTable) + __no_init static volatile tDMAControlTable ENTRY_NAME @UDMACC26XX_CONFIG_BASE + CHANNEL_INDEX * sizeof(tDMAControlTable) #elif defined(__TI_COMPILER_VERSION__) -#define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \ - PRAGMA(LOCATION( ENTRY_NAME , UDMACC26XX_CONFIG_BASE + CHANNEL_INDEX * sizeof(tDMAControlTable) );)\ +#define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \ + PRAGMA(LOCATION(ENTRY_NAME, UDMACC26XX_CONFIG_BASE + CHANNEL_INDEX * sizeof(tDMAControlTable));) \ static volatile tDMAControlTable ENTRY_NAME #define PRAGMA(x) _Pragma(#x) #elif defined(__GNUC__) #define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \ - extern int UDMACC26XX_ ## ENTRY_NAME ## _is_placed; __attribute__ ((section("."#ENTRY_NAME))) static volatile tDMAControlTable ENTRY_NAME = {&UDMACC26XX_ ## ENTRY_NAME ## _is_placed} + extern int UDMACC26XX_##ENTRY_NAME##_is_placed; \ + __attribute__((section("." #ENTRY_NAME))) static volatile tDMAControlTable ENTRY_NAME = {&UDMACC26XX_##ENTRY_NAME##_is_placed} #else #error "don't know how to define ALLOCATE_CONTROL_TABLE_ENTRY for this toolchain" #endif /*! Sets the DMA transfer size in number of items */ -#define UDMACC26XX_SET_TRANSFER_SIZE(SIZE) (((SIZE - 1) << UDMA_XFER_SIZE_S) & UDMA_XFER_SIZE_M) +#define UDMACC26XX_SET_TRANSFER_SIZE(SIZE) (((SIZE - 1) << UDMA_XFER_SIZE_S) & UDMA_XFER_SIZE_M) /*! Gets the DMA transfer size in number of items*/ #define UDMACC26XX_GET_TRANSFER_SIZE(CONTROL) (((CONTROL & UDMA_XFER_SIZE_M) >> UDMA_XFER_SIZE_S) + 1) @@ -191,8 +192,8 @@ extern "C" { */ typedef struct UDMACC26XX_Object { - bool isOpen; /*!< Flag for open/close status */ - HwiP_Struct hwi; /*!< Embedded Hwi Object */ + bool isOpen; /*!< Flag for open/close status */ + HwiP_Struct hwi; /*!< Embedded Hwi Object */ } UDMACC26XX_Object; /*! @@ -200,31 +201,31 @@ typedef struct UDMACC26XX_Object */ typedef struct UDMACC26XX_HWAttrs { - uint32_t baseAddr; /*!< Base adddress for UDMACC26XX */ - PowerCC26XX_Resource powerMngrId; /*!< UDMACC26XX Peripheral's power manager ID */ - uint8_t intNum; /*!< UDMACC26XX error interrupt number */ - /*! @brief UDMACC26XX error interrupt priority. - * intPriority is the DMA peripheral's interrupt priority, as - * defined by the underlying OS. It is passed unmodified to the - * underlying OS's interrupt handler creation code, so you need to - * refer to the OS documentation for usage. If the - * driver uses the ti.dpl interface instead of making OS - * calls directly, then the HwiP port handles the interrupt priority - * in an OS specific way. In the case of the SYS/BIOS port, - * intPriority is passed unmodified to Hwi_create(). - * - * The CC26xx uses three of the priority bits, - * meaning ~0 has the same effect as (7 << 5). - * - * (7 << 5) will apply the lowest priority. - * - * (1 << 5) will apply the highest priority. - * - * Setting the priority to 0 is not supported by this driver. - * - * HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. - */ - uint8_t intPriority; + uint32_t baseAddr; /*!< Base adddress for UDMACC26XX */ + PowerCC26XX_Resource powerMngrId; /*!< UDMACC26XX Peripheral's power manager ID */ + uint8_t intNum; /*!< UDMACC26XX error interrupt number */ + /*! @brief UDMACC26XX error interrupt priority. + * intPriority is the DMA peripheral's interrupt priority, as + * defined by the underlying OS. It is passed unmodified to the + * underlying OS's interrupt handler creation code, so you need to + * refer to the OS documentation for usage. If the + * driver uses the ti.dpl interface instead of making OS + * calls directly, then the HwiP port handles the interrupt priority + * in an OS specific way. In the case of the SYS/BIOS port, + * intPriority is passed unmodified to Hwi_create(). + * + * The CC26xx uses three of the priority bits, + * meaning ~0 has the same effect as (7 << 5). + * + * (7 << 5) will apply the lowest priority. + * + * (1 << 5) will apply the highest priority. + * + * Setting the priority to 0 is not supported by this driver. + * + * HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; } UDMACC26XX_HWAttrs; /*! @@ -232,14 +233,14 @@ typedef struct UDMACC26XX_HWAttrs */ typedef struct UDMACC26XX_Config { - void* object; /*!< Pointer to UDMACC26XX object */ - void const* hwAttrs; /*!< Pointer to hardware attribute */ + void* object; /*!< Pointer to UDMACC26XX object */ + void const* hwAttrs; /*!< Pointer to hardware attribute */ } UDMACC26XX_Config; /*! * @brief A handle that is returned from a UDMACC26XX_open() call. */ -typedef struct UDMACC26XX_Config* UDMACC26XX_Handle; +typedef struct UDMACC26XX_Config* UDMACC26XX_Handle; /* Extern'd hwiIntFxn */ extern void UDMACC26XX_hwiIntFxn(uintptr_t callbacks); @@ -258,7 +259,7 @@ extern void UDMACC26XX_hwiIntFxn(uintptr_t callbacks); */ __STATIC_INLINE void UDMACC26XX_init(UDMACC26XX_Handle handle) { - UDMACC26XX_Object* object; + UDMACC26XX_Object* object; /* Get the pointer to the object */ object = (UDMACC26XX_Object*)(handle->object); @@ -410,9 +411,9 @@ __STATIC_INLINE void UDMACC26XX_channelDisable(UDMACC26XX_Handle handle, uint32_ * @sa UDMACC26XX_channelEnable */ __STATIC_INLINE void UDMACC26XX_disableAttribute(UDMACC26XX_Handle handle, - uint32_t channelNum, uint32_t attr) + uint32_t channelNum, uint32_t attr) { - UDMACC26XX_HWAttrs const* hwAttrs = (UDMACC26XX_HWAttrs*) handle->hwAttrs; + UDMACC26XX_HWAttrs const* hwAttrs = (UDMACC26XX_HWAttrs*)handle->hwAttrs; uDMAChannelAttributeDisable(hwAttrs->baseAddr, channelNum, attr); } diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/ClockP.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/ClockP.h index 0ef2d6a..f720b85 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/ClockP.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/ClockP.h @@ -61,9 +61,9 @@ extern "C" { #endif -#include #include #include +#include /*! * @brief Number of bytes greater than or equal to the size of any RTOS @@ -72,7 +72,7 @@ extern "C" { * nortos: 32 (biggest of the HW-specific ClockP instance structs) * SysBIOS: 36 */ -#define ClockP_STRUCT_SIZE (36) +#define ClockP_STRUCT_SIZE (36) /*! * @brief ClockP structure. @@ -82,8 +82,8 @@ extern "C" { */ typedef union ClockP_Struct { - uint32_t dummy; /*!< Align object */ - char data[ClockP_STRUCT_SIZE]; + uint32_t dummy; /*!< Align object */ + char data[ClockP_STRUCT_SIZE]; } ClockP_Struct; /*! @@ -91,8 +91,8 @@ typedef union ClockP_Struct */ typedef struct ClockP_FreqHz { - uint32_t hi; /*!< most significant 32-bits of frequency */ - uint32_t lo; /*!< least significant 32-bits of frequency */ + uint32_t hi; /*!< most significant 32-bits of frequency */ + uint32_t lo; /*!< least significant 32-bits of frequency */ } ClockP_FreqHz; /*! @@ -111,7 +111,7 @@ typedef enum ClockP_Status * and then is used in the other instance based functions (e.g. ::ClockP_start, * ::ClockP_stop, etc.). */ -typedef void* ClockP_Handle; +typedef void* ClockP_Handle; #define ClockP_handle(x) ((ClockP_Handle)(x)) @@ -142,12 +142,11 @@ typedef void (*ClockP_Fxn)(uintptr_t arg); */ typedef struct ClockP_Params { - bool startFlag; /*!< Start immediately after instance is created. */ - uint32_t period; /*!< Period of clock object. */ - uintptr_t arg; /*!< Argument passed into the clock function. */ + bool startFlag; /*!< Start immediately after instance is created. */ + uint32_t period; /*!< Period of clock object. */ + uintptr_t arg; /*!< Argument passed into the clock function. */ } ClockP_Params; - /*! * @brief Function to construct a clock object. * @@ -319,7 +318,6 @@ extern void ClockP_usleep(uint32_t usec); */ extern void ClockP_sleep(uint32_t sec); - #ifdef __cplusplus } #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/DebugP.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/DebugP.h index 1ab4e66..5bf6e1f 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/DebugP.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/DebugP.h @@ -66,16 +66,16 @@ extern "C" { #endif -#include #include #include +#include #ifndef DebugP_ASSERT_ENABLED #define DebugP_ASSERT_ENABLED 0 #endif #ifndef DebugP_LOG_ENABLED -#define DebugP_LOG_ENABLED 0 +#define DebugP_LOG_ENABLED 0 #endif #if DebugP_ASSERT_ENABLED @@ -89,8 +89,8 @@ extern void _DebugP_assert(int expression, const char* file, int line); * * @param expression Expression to evaluate */ -#define DebugP_assert(expression) (_DebugP_assert(expression, \ - __FILE__, __LINE__)) +#define DebugP_assert(expression) (_DebugP_assert(expression, \ + __FILE__, __LINE__)) #else #define DebugP_assert(expression) #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/HwiP.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/HwiP.h index c6764f6..13d36f0 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/HwiP.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/HwiP.h @@ -54,9 +54,9 @@ extern "C" { #endif -#include #include #include +#include /*! * @brief Number of bytes greater than or equal to the size of any RTOS @@ -65,7 +65,7 @@ extern "C" { * nortos: 12 * SysBIOS: 28 */ -#define HwiP_STRUCT_SIZE (28) +#define HwiP_STRUCT_SIZE (28) /*! * @brief HwiP structure. @@ -75,8 +75,8 @@ extern "C" { */ typedef union HwiP_Struct { - uint32_t dummy; /*!< Align object */ - char data[HwiP_STRUCT_SIZE]; + uint32_t dummy; /*!< Align object */ + char data[HwiP_STRUCT_SIZE]; } HwiP_Struct; /*! @@ -84,7 +84,7 @@ typedef union HwiP_Struct * * A HwiP_Handle returned from the ::HwiP_create represents that instance. */ -typedef void* HwiP_Handle; +typedef void* HwiP_Handle; /*! * @brief Status codes for HwiP APIs @@ -114,9 +114,9 @@ typedef void (*HwiP_Fxn)(uintptr_t arg); */ typedef struct HwiP_Params { - uintptr_t arg; /*!< Argument passed into the Hwi function. */ - uint32_t priority; /*!< Device specific priority. */ - bool enableInt; /*!< Enable interrupt on creation. */ + uintptr_t arg; /*!< Argument passed into the Hwi function. */ + uint32_t priority; /*!< Device specific priority. */ + bool enableInt; /*!< Enable interrupt on creation. */ } HwiP_Params; /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/MutexP.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/MutexP.h index 76100aa..1b9c2d3 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/MutexP.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/MutexP.h @@ -59,9 +59,9 @@ extern "C" { #endif -#include #include #include +#include /*! * @brief Number of bytes greater than or equal to the size of any RTOS @@ -70,7 +70,7 @@ extern "C" { * nortos: 12 * SysBIOS: 40 */ -#define MutexP_STRUCT_SIZE (40) +#define MutexP_STRUCT_SIZE (40) /*! * @brief MutexP structure. @@ -80,8 +80,8 @@ extern "C" { */ typedef union MutexP_Struct { - uint32_t dummy; /*!< Align object */ - char data[MutexP_STRUCT_SIZE]; + uint32_t dummy; /*!< Align object */ + char data[MutexP_STRUCT_SIZE]; } MutexP_Struct; /*! @@ -115,10 +115,9 @@ typedef void* MutexP_Handle; */ typedef struct MutexP_Params { - void (*callback)(void); /*!< Callback while waiting for mutex unlock */ + void (*callback)(void); /*!< Callback while waiting for mutex unlock */ } MutexP_Params; - /*! * @brief Function to construct a mutex. * diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/SemaphoreP.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/SemaphoreP.h index b4b6200..bd31106 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/SemaphoreP.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/SemaphoreP.h @@ -60,9 +60,9 @@ extern "C" { #endif -#include #include #include +#include /*! * @brief Number of bytes greater than or equal to the size of any RTOS @@ -71,7 +71,7 @@ extern "C" { * nortos: 16 * SysBIOS: 28 */ -#define SemaphoreP_STRUCT_SIZE (28) +#define SemaphoreP_STRUCT_SIZE (28) /*! * @brief SemaphoreP structure. @@ -81,8 +81,8 @@ extern "C" { */ typedef union SemaphoreP_Struct { - uint32_t dummy; /*!< Align object */ - char data[SemaphoreP_STRUCT_SIZE]; + uint32_t dummy; /*!< Align object */ + char data[SemaphoreP_STRUCT_SIZE]; } SemaphoreP_Struct; /*! @@ -93,7 +93,7 @@ typedef union SemaphoreP_Struct /*! * @brief No wait define */ -#define SemaphoreP_NO_WAIT (0) +#define SemaphoreP_NO_WAIT (0) /*! * @brief Status codes for SemaphoreP APIs (for backwards compatibility) @@ -113,7 +113,7 @@ typedef enum SemaphoreP_Status * instance and is used in the other instance based functions (e.g. * ::SemaphoreP_post or ::SemaphoreP_pend, etc.). */ -typedef void* SemaphoreP_Handle; +typedef void* SemaphoreP_Handle; /*! * @brief Mode of the semaphore @@ -121,7 +121,7 @@ typedef void* SemaphoreP_Handle; typedef enum SemaphoreP_Mode { SemaphoreP_Mode_COUNTING = 0x0, - SemaphoreP_Mode_BINARY = 0x1 + SemaphoreP_Mode_BINARY = 0x1 } SemaphoreP_Mode; /*! @@ -135,8 +135,8 @@ typedef enum SemaphoreP_Mode */ typedef struct SemaphoreP_Params { - SemaphoreP_Mode mode; /*!< Mode for the semaphore */ - void (*callback)(void); /*!< Callback while pending for semaphore post */ + SemaphoreP_Mode mode; /*!< Mode for the semaphore */ + void (*callback)(void); /*!< Callback while pending for semaphore post */ } SemaphoreP_Params; /*! @@ -156,17 +156,16 @@ typedef struct SemaphoreP_Params */ extern SemaphoreP_Params SemaphoreP_defaultParams; - /* * SemaphoreP construct APIs can only be used if one of the OS's * is defined. For FreeRTOS, configSUPPORT_STATIC_ALLOCATION also * has to be set to 1 in FreeRTOSConfig.h. */ extern SemaphoreP_Handle SemaphoreP_construct(SemaphoreP_Struct* handle, - unsigned int count, SemaphoreP_Params* params); + unsigned int count, SemaphoreP_Params* params); extern SemaphoreP_Handle SemaphoreP_constructBinary(SemaphoreP_Struct* handle, - unsigned int count); + unsigned int count); extern void SemaphoreP_destruct(SemaphoreP_Struct* semP); @@ -183,7 +182,7 @@ extern void SemaphoreP_destruct(SemaphoreP_Struct* semP); * @return A SemaphoreP_Handle on success or a NULL on an error */ extern SemaphoreP_Handle SemaphoreP_create(unsigned int count, - SemaphoreP_Params* params); + SemaphoreP_Params* params); /*! * @brief Function to create a binary semaphore. @@ -210,7 +209,7 @@ extern SemaphoreP_Handle SemaphoreP_createBinary(unsigned int count); * @return A SemaphoreP_Handle on success or a NULL on an error */ extern SemaphoreP_Handle SemaphoreP_createBinaryCallback(unsigned int count, - void (*callback)(void)); + void (*callback)(void)); /*! * @brief Function to delete a semaphore. @@ -243,7 +242,7 @@ extern void SemaphoreP_Params_init(SemaphoreP_Params* params); * - SemaphoreP_TIMEOUT: Timed out. Semaphore was not obtained. */ extern SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, - uint32_t timeout); + uint32_t timeout); /*! * @brief Function to post (signal) a semaphore from task of ISR context. diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/SwiP.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/SwiP.h index 6ba94d2..1e312f2 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/SwiP.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/SwiP.h @@ -53,7 +53,7 @@ extern "C" { * nortos: 40 * SysBIOS: 52 */ -#define SwiP_STRUCT_SIZE (52) +#define SwiP_STRUCT_SIZE (52) /*! * @brief SemaphoreP structure. @@ -63,20 +63,20 @@ extern "C" { */ typedef union SwiP_Struct { - uint32_t dummy; /*!< Align object */ - char data[SwiP_STRUCT_SIZE]; + uint32_t dummy; /*!< Align object */ + char data[SwiP_STRUCT_SIZE]; } SwiP_Struct; -#include #include #include +#include /*! * @brief Opaque client reference to an instance of a SwiP * * A SwiP_Handle returned from the ::SwiP_create represents that instance. */ -typedef void* SwiP_Handle; +typedef void* SwiP_Handle; /*! * @brief Status codes for SwiP APIs @@ -113,10 +113,10 @@ typedef void (*SwiP_Fxn)(uintptr_t arg0, uintptr_t arg1); */ typedef struct SwiP_Params { - uintptr_t arg0; /*!< Argument passed into the SwiP function. */ - uintptr_t arg1; /*!< Argument passed into the SwiP function. */ - uint32_t priority; /*!< priority, 0 is min, 1, 2, ..., ~0 for max */ - uint32_t trigger; /*!< Initial SwiP trigger value. */ + uintptr_t arg0; /*!< Argument passed into the SwiP function. */ + uintptr_t arg1; /*!< Argument passed into the SwiP function. */ + uint32_t priority; /*!< priority, 0 is min, 1, 2, ..., ~0 for max */ + uint32_t trigger; /*!< Initial SwiP trigger value. */ } SwiP_Params; /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/SystemP.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/SystemP.h index e1c5a9a..4c6b81e 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/SystemP.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/dpl/SystemP.h @@ -42,8 +42,8 @@ #ifndef ti_dpl_SystemP__include #define ti_dpl_SystemP__include -#include #include +#include #ifdef __cplusplus extern "C" { diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecdh/ECDHCC26X2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecdh/ECDHCC26X2.h index 46149bf..dc1d96f 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecdh/ECDHCC26X2.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecdh/ECDHCC26X2.h @@ -110,25 +110,25 @@ extern "C" { #endif -#include #include +#include -#include #include -#include +#include #include +#include #include -#include DeviceFamily_constructPath(driverlib/pka.h) +#include DeviceFamily_constructPath(driverlib / pka.h) #include -#include #include +#include /* Exit the SWI and wait until an HWI call posts the SWI again */ -#define ECDHCC26X2_STATUS_FSM_RUN_PKA_OP ECDH_STATUS_RESERVED - 0 +#define ECDHCC26X2_STATUS_FSM_RUN_PKA_OP ECDH_STATUS_RESERVED - 0 /* Execute the next FSM state immediately without waiting for the next HWI */ -#define ECDHCC26X2_STATUS_FSM_RUN_FSM ECDH_STATUS_RESERVED - 1 +#define ECDHCC26X2_STATUS_FSM_RUN_FSM ECDH_STATUS_RESERVED - 1 /*! * @brief ECDHCC26X2 states @@ -171,19 +171,19 @@ typedef enum ECDHCC26X2_FsmState_ */ typedef struct ECDHCC26X2_HWAttrs_ { - /*! @brief Crypto Peripheral's interrupt priority. + /*! @brief Crypto Peripheral's interrupt priority. - The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). - (7 << 5) will apply the lowest priority. + (7 << 5) will apply the lowest priority. - (1 << 5) will apply the highest priority. + (1 << 5) will apply the highest priority. - Setting the priority to 0 is not supported by this driver. + Setting the priority to 0 is not supported by this driver. - HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. - */ - uint8_t intPriority; + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; } ECDHCC26X2_HWAttrs; /*! @@ -193,17 +193,17 @@ typedef struct ECDHCC26X2_HWAttrs_ */ typedef struct ECDHCC26X2_Object_ { - bool isOpen; - bool operationInProgress; - bool operationCanceled; - int_fast16_t operationStatus; - ECDH_CallbackFxn callbackFxn; - ECDH_ReturnBehavior returnBehavior; - ECDH_Operation operation; - ECDH_OperationType operationType; - ECDHCC26X2_FsmState fsmState; - uint32_t semaphoreTimeout; - uint32_t resultAddress; + bool isOpen; + bool operationInProgress; + bool operationCanceled; + int_fast16_t operationStatus; + ECDH_CallbackFxn callbackFxn; + ECDH_ReturnBehavior returnBehavior; + ECDH_Operation operation; + ECDH_OperationType operationType; + ECDHCC26X2_FsmState fsmState; + uint32_t semaphoreTimeout; + uint32_t resultAddress; } ECDHCC26X2_Object; #ifdef __cplusplus diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecdsa/ECDSACC26X2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecdsa/ECDSACC26X2.h index b691e8d..0e33ea6 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecdsa/ECDSACC26X2.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecdsa/ECDSACC26X2.h @@ -91,22 +91,22 @@ extern "C" { #endif -#include #include +#include -#include #include -#include +#include #include +#include #include -#include #include +#include /* Exit the SWI and wait until an HWI call posts the SWI again */ -#define ECDSACC26X2_STATUS_FSM_RUN_PKA_OP ECDSA_STATUS_RESERVED - 0 +#define ECDSACC26X2_STATUS_FSM_RUN_PKA_OP ECDSA_STATUS_RESERVED - 0 /* Execute the next FSM state immediately without waiting for the next HWI */ -#define ECDSACC26X2_STATUS_FSM_RUN_FSM ECDSA_STATUS_RESERVED - 1 +#define ECDSACC26X2_STATUS_FSM_RUN_FSM ECDSA_STATUS_RESERVED - 1 /*! * @brief ECDSACC26X2 Sign and Verify states @@ -169,7 +169,7 @@ typedef enum ECDSACC26X2_FsmState_ * pointer is stored in the object at the beginning of the transaction. * This way, unused state machines are removed at link time. */ -typedef int_fast16_t (*ECDSACC26X2_stateMachineFxn) (ECDSA_Handle handle); +typedef int_fast16_t (*ECDSACC26X2_stateMachineFxn)(ECDSA_Handle handle); /*! * @brief ECDSACC26X2 Hardware Attributes @@ -179,19 +179,19 @@ typedef int_fast16_t (*ECDSACC26X2_stateMachineFxn) (ECDSA_Handle handle); */ typedef struct ECDSACC26X2_HWAttrs_ { - /*! @brief PKA Peripheral's interrupt priority. + /*! @brief PKA Peripheral's interrupt priority. - The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). - (7 << 5) will apply the lowest priority. + (7 << 5) will apply the lowest priority. - (1 << 5) will apply the highest priority. + (1 << 5) will apply the highest priority. - Setting the priority to 0 is not supported by this driver. + Setting the priority to 0 is not supported by this driver. - HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. - */ - uint8_t intPriority; + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; } ECDSACC26X2_HWAttrs; /*! @@ -201,20 +201,20 @@ typedef struct ECDSACC26X2_HWAttrs_ */ typedef struct ECDSACC26X2_Object_ { - bool isOpen; - bool operationInProgress; - bool operationCanceled; - int_fast16_t operationStatus; - ECDSA_Operation operation; - ECDSA_OperationType operationType; - ECDSA_CallbackFxn callbackFxn; - ECDSACC26X2_stateMachineFxn fsmFxn; - ECDSA_ReturnBehavior returnBehavior; - ECDSACC26X2_FsmState fsmState; - uint32_t semaphoreTimeout; - uint32_t resultAddress; - uint32_t* scratchNumber1; - uint32_t* scratchNumber2; + bool isOpen; + bool operationInProgress; + bool operationCanceled; + int_fast16_t operationStatus; + ECDSA_Operation operation; + ECDSA_OperationType operationType; + ECDSA_CallbackFxn callbackFxn; + ECDSACC26X2_stateMachineFxn fsmFxn; + ECDSA_ReturnBehavior returnBehavior; + ECDSACC26X2_FsmState fsmState; + uint32_t semaphoreTimeout; + uint32_t resultAddress; + uint32_t* scratchNumber1; + uint32_t* scratchNumber2; } ECDSACC26X2_Object; #ifdef __cplusplus diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecjpake/ECJPAKECC26X2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecjpake/ECJPAKECC26X2.h index 0c8b81f..9c68267 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecjpake/ECJPAKECC26X2.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/ecjpake/ECJPAKECC26X2.h @@ -92,22 +92,22 @@ extern "C" { #endif -#include #include +#include -#include #include -#include +#include #include +#include #include -#include #include +#include /* Exit the SWI and wait until an HWI call posts the SWI again */ -#define ECJPAKECC26X2_STATUS_FSM_RUN_PKA_OP ECJPAKE_STATUS_RESERVED - 0 +#define ECJPAKECC26X2_STATUS_FSM_RUN_PKA_OP ECJPAKE_STATUS_RESERVED - 0 /* Execute the next FSM state immediately without waiting for the next HWI */ -#define ECJPAKECC26X2_STATUS_FSM_RUN_FSM ECJPAKE_STATUS_RESERVED - 1 +#define ECJPAKECC26X2_STATUS_FSM_RUN_FSM ECJPAKE_STATUS_RESERVED - 1 /*! * @brief ECJPAKECC26X2 states @@ -196,19 +196,19 @@ typedef enum ECJPAKECC26X2_FsmState_ */ typedef struct ECJPAKECC26X2_HWAttrs_ { - /*! @brief PKA Peripheral's interrupt priority. + /*! @brief PKA Peripheral's interrupt priority. - The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). - (7 << 5) will apply the lowest priority. + (7 << 5) will apply the lowest priority. - (1 << 5) will apply the highest priority. + (1 << 5) will apply the highest priority. - Setting the priority to 0 is not supported by this driver. + Setting the priority to 0 is not supported by this driver. - HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. - */ - uint8_t intPriority; + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; } ECJPAKECC26X2_HWAttrs; /*! @@ -218,17 +218,17 @@ typedef struct ECJPAKECC26X2_HWAttrs_ */ typedef struct ECJPAKECC26X2_Object_ { - bool isOpen; - bool operationInProgress; - bool operationCanceled; - int_fast16_t operationStatus; - ECJPAKE_CallbackFxn callbackFxn; - ECJPAKE_ReturnBehavior returnBehavior; - ECJPAKECC26X2_FsmState fsmState; - ECJPAKE_Operation operation; - ECJPAKE_OperationType operationType; - uint32_t semaphoreTimeout; - uint32_t resultAddress; + bool isOpen; + bool operationInProgress; + bool operationCanceled; + int_fast16_t operationStatus; + ECJPAKE_CallbackFxn callbackFxn; + ECJPAKE_ReturnBehavior returnBehavior; + ECJPAKECC26X2_FsmState fsmState; + ECJPAKE_Operation operation; + ECJPAKE_OperationType operationType; + uint32_t semaphoreTimeout; + uint32_t resultAddress; } ECJPAKECC26X2_Object; #ifdef __cplusplus diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/gpio/GPIOCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/gpio/GPIOCC26XX.h index fcbbfaa..cf9c418 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/gpio/GPIOCC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/gpio/GPIOCC26XX.h @@ -143,12 +143,10 @@ extern "C" { #include -#include #include +#include -#include DeviceFamily_constructPath(driverlib/ioc.h) - - +#include DeviceFamily_constructPath(driverlib / ioc.h) /*! * @brief GPIO device specific driver configuration structure @@ -176,32 +174,32 @@ extern "C" { */ typedef struct GPIOCC26XX_Config { - /*! Pointer to the board's GPIO_PinConfig array */ - GPIO_PinConfig* pinConfigs; + /*! Pointer to the board's GPIO_PinConfig array */ + GPIO_PinConfig* pinConfigs; - /*! Pointer to the board's GPIO_CallbackFxn array */ - GPIO_CallbackFxn* callbacks; + /*! Pointer to the board's GPIO_CallbackFxn array */ + GPIO_CallbackFxn* callbacks; - /*! Number of GPIO_PinConfigs defined */ - uint32_t numberOfPinConfigs; + /*! Number of GPIO_PinConfigs defined */ + uint32_t numberOfPinConfigs; - /*! Number of GPIO_Callbacks defined */ - uint32_t numberOfCallbacks; + /*! Number of GPIO_Callbacks defined */ + uint32_t numberOfCallbacks; - /*! - * Interrupt priority used for call back interrupts. - * - * intPriority is the interrupt priority, as defined by the - * underlying OS. It is passed unmodified to the underlying OS's - * interrupt handler creation code, so you need to refer to the OS - * documentation for usage. If the driver uses the ti.dpl - * interface instead of making OS calls directly, then the HwiP port - * handles the interrupt priority in an OS specific way. In the case - * of the SYS/BIOS port, intPriority is passed unmodified to Hwi_create(). - * - * Setting ~0 will configure the lowest possible priority - */ - uint32_t intPriority; + /*! + * Interrupt priority used for call back interrupts. + * + * intPriority is the interrupt priority, as defined by the + * underlying OS. It is passed unmodified to the underlying OS's + * interrupt handler creation code, so you need to refer to the OS + * documentation for usage. If the driver uses the ti.dpl + * interface instead of making OS calls directly, then the HwiP port + * handles the interrupt priority in an OS specific way. In the case + * of the SYS/BIOS port, intPriority is passed unmodified to Hwi_create(). + * + * Setting ~0 will configure the lowest possible priority + */ + uint32_t intPriority; } GPIOCC26XX_Config; /*! @@ -211,44 +209,44 @@ typedef struct GPIOCC26XX_Config /** * @name Device specific GPIO port/pin identifiers to be used within the board's GPIO_PinConfig table. * @{ -*/ -#define GPIOCC26XX_EMPTY_PIN 0xffff /*!< @hideinitializer */ + */ +#define GPIOCC26XX_EMPTY_PIN 0xffff /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_00 IOID_0 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_01 IOID_1 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_02 IOID_2 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_03 IOID_3 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_04 IOID_4 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_05 IOID_5 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_06 IOID_6 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_07 IOID_7 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_00 IOID_0 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_01 IOID_1 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_02 IOID_2 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_03 IOID_3 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_04 IOID_4 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_05 IOID_5 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_06 IOID_6 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_07 IOID_7 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_08 IOID_8 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_09 IOID_9 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_10 IOID_10 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_11 IOID_11 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_12 IOID_12 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_13 IOID_13 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_14 IOID_14 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_15 IOID_15 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_08 IOID_8 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_09 IOID_9 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_10 IOID_10 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_11 IOID_11 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_12 IOID_12 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_13 IOID_13 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_14 IOID_14 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_15 IOID_15 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_16 IOID_16 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_17 IOID_17 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_18 IOID_18 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_19 IOID_19 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_20 IOID_20 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_21 IOID_21 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_22 IOID_22 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_23 IOID_23 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_16 IOID_16 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_17 IOID_17 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_18 IOID_18 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_19 IOID_19 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_20 IOID_20 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_21 IOID_21 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_22 IOID_22 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_23 IOID_23 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_24 IOID_24 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_25 IOID_25 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_26 IOID_26 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_27 IOID_27 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_28 IOID_28 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_29 IOID_29 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_30 IOID_30 /*!< @hideinitializer */ -#define GPIOCC26XX_DIO_31 IOID_31 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_24 IOID_24 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_25 IOID_25 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_26 IOID_26 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_27 IOID_27 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_28 IOID_28 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_29 IOID_29 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_30 IOID_30 /*!< @hideinitializer */ +#define GPIOCC26XX_DIO_31 IOID_31 /*!< @hideinitializer */ /** @} */ /** @} end of GPIOCC26XX_PinConfigIds group */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/i2c/I2CCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/i2c/I2CCC26XX.h index 8981200..b708031 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/i2c/I2CCC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/i2c/I2CCC26XX.h @@ -309,15 +309,15 @@ extern "C" { #endif -#include #include +#include #include -#include #include +#include #include -#include #include +#include /** * @addtogroup I2C_STATUS @@ -348,9 +348,9 @@ extern "C" { /** @}*/ /*! I2C Base Address type.*/ -typedef unsigned long I2CBaseAddrType; +typedef unsigned long I2CBaseAddrType; /* \cond */ -typedef unsigned long I2CDataType; +typedef unsigned long I2CDataType; /* \endcond */ /*! @internal @brief I2C function table pointer */ @@ -379,8 +379,8 @@ extern const I2C_FxnTable I2CCC26XX_fxnTable; */ typedef struct I2CCC26XX_I2CPinCfg { - uint8_t pinSDA; - uint8_t pinSCL; + uint8_t pinSDA; + uint8_t pinSCL; } I2CCC26XX_I2CPinCfg; /*! @@ -392,11 +392,11 @@ typedef struct I2CCC26XX_I2CPinCfg */ typedef enum I2CCC26XX_Mode { - I2CCC26XX_IDLE_MODE = 0, /* I2C is not performing a transaction */ - I2CCC26XX_WRITE_MODE, /* I2C is currently performing write operations */ - I2CCC26XX_READ_MODE, /* I2C is currently performing read operations */ - I2CCC26XX_BUSBUSY_MODE, /* I2C Bus is currently busy */ - I2CCC26XX_ERROR = 0xFF /* I2C error has occurred, exit gracefully */ + I2CCC26XX_IDLE_MODE = 0, /* I2C is not performing a transaction */ + I2CCC26XX_WRITE_MODE, /* I2C is currently performing write operations */ + I2CCC26XX_READ_MODE, /* I2C is currently performing read operations */ + I2CCC26XX_BUSBUSY_MODE, /* I2C Bus is currently busy */ + I2CCC26XX_ERROR = 0xFF /* I2C error has occurred, exit gracefully */ } I2CCC26XX_Mode; /*! @endcond */ @@ -441,36 +441,36 @@ typedef enum I2CCC26XX_Mode */ typedef struct I2CCC26XX_HWAttrsV1 { - /*! I2C peripheral's base address */ - I2CBaseAddrType baseAddr; - /*! I2C peripheral's Power driver ID */ - unsigned long powerMngrId; - /*! I2C peripheral's interrupt number */ - int intNum; - /*! @brief I2C Peripheral's interrupt priority. + /*! I2C peripheral's base address */ + I2CBaseAddrType baseAddr; + /*! I2C peripheral's Power driver ID */ + unsigned long powerMngrId; + /*! I2C peripheral's interrupt number */ + int intNum; + /*! @brief I2C Peripheral's interrupt priority. - The CC26xx uses three of the priority bits, - meaning ~0 has the same effect as (7 << 5). + The CC26xx uses three of the priority bits, + meaning ~0 has the same effect as (7 << 5). - (7 << 5) will apply the lowest priority. + (7 << 5) will apply the lowest priority. - (1 << 5) will apply the highest priority. + (1 << 5) will apply the highest priority. - Setting the priority to 0 is not supported by this driver. + Setting the priority to 0 is not supported by this driver. - Hwi's with priority 0 ignore the Hwi dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. - */ - uint8_t intPriority; - /*! @brief I2C Swi priority. - The higher the number, the higher the priority. - The minimum is 0 and the maximum is 15 by default. - The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. - */ - uint32_t swiPriority; - /*! I2C SDA pin mapping */ - uint8_t sdaPin; - /*! I2C SCL pin mapping */ - uint8_t sclPin; + Hwi's with priority 0 ignore the Hwi dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! @brief I2C Swi priority. + The higher the number, the higher the priority. + The minimum is 0 and the maximum is 15 by default. + The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. + */ + uint32_t swiPriority; + /*! I2C SDA pin mapping */ + uint8_t sdaPin; + /*! I2C SCL pin mapping */ + uint8_t sclPin; } I2CCC26XX_HWAttrsV1; /*! @@ -480,38 +480,38 @@ typedef struct I2CCC26XX_HWAttrsV1 */ typedef struct I2CCC26XX_Object { - /* I2C control variables */ - I2C_TransferMode transferMode; /*!< Blocking or Callback mode */ - I2C_CallbackFxn transferCallbackFxn; /*!< Callback function pointer */ - volatile I2CCC26XX_Mode mode; /*!< Stores the I2C state */ - uint32_t bitRate; /*!< Bitrate of the I2C module */ + /* I2C control variables */ + I2C_TransferMode transferMode; /*!< Blocking or Callback mode */ + I2C_CallbackFxn transferCallbackFxn; /*!< Callback function pointer */ + volatile I2CCC26XX_Mode mode; /*!< Stores the I2C state */ + uint32_t bitRate; /*!< Bitrate of the I2C module */ - /* I2C SYS/BIOS objects */ - HwiP_Struct hwi;/*!< Hwi object handle */ - SwiP_Struct swi; /*!< Swi object */ - SemaphoreP_Struct mutex; /*!< Grants exclusive access to I2C */ - SemaphoreP_Struct transferComplete; /*!< Signal I2C transfer complete */ + /* I2C SYS/BIOS objects */ + HwiP_Struct hwi; /*!< Hwi object handle */ + SwiP_Struct swi; /*!< Swi object */ + SemaphoreP_Struct mutex; /*!< Grants exclusive access to I2C */ + SemaphoreP_Struct transferComplete; /*!< Signal I2C transfer complete */ - /* PIN driver state object and handle */ - PIN_State pinState; - PIN_Handle hPin; + /* PIN driver state object and handle */ + PIN_State pinState; + PIN_Handle hPin; - /* I2C current transaction */ - I2C_Transaction* currentTransaction; /*!< Ptr to current I2C transaction */ - uint8_t* writeBufIdx; /*!< Internal inc. writeBuf index */ - unsigned int writeCountIdx; /*!< Internal dec. writeCounter */ - uint8_t* readBufIdx; /*!< Internal inc. readBuf index */ - unsigned int readCountIdx; /*!< Internal dec. readCounter */ + /* I2C current transaction */ + I2C_Transaction* currentTransaction; /*!< Ptr to current I2C transaction */ + uint8_t* writeBufIdx; /*!< Internal inc. writeBuf index */ + unsigned int writeCountIdx; /*!< Internal dec. writeCounter */ + uint8_t* readBufIdx; /*!< Internal inc. readBuf index */ + unsigned int readCountIdx; /*!< Internal dec. readCounter */ - /* I2C transaction pointers for I2C_MODE_CALLBACK */ - I2C_Transaction* headPtr; /*!< Head ptr for queued transactions */ - I2C_Transaction* tailPtr; /*!< Tail ptr for queued transactions */ + /* I2C transaction pointers for I2C_MODE_CALLBACK */ + I2C_Transaction* headPtr; /*!< Head ptr for queued transactions */ + I2C_Transaction* tailPtr; /*!< Tail ptr for queued transactions */ - /* I2C power notification */ - void* i2cPostFxn; /*!< I2C post-notification Function pointer */ - Power_NotifyObj i2cPostObj; /*!< I2C post-notification object */ + /* I2C power notification */ + void* i2cPostFxn; /*!< I2C post-notification Function pointer */ + Power_NotifyObj i2cPostObj; /*!< I2C post-notification object */ - bool isOpen; /*!< flag to indicate module is open */ + bool isOpen; /*!< flag to indicate module is open */ } I2CCC26XX_Object; /*! @endcond */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/i2s/I2SCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/i2s/I2SCC26XX.h index 7ad4245..2465df1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/i2s/I2SCC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/i2s/I2SCC26XX.h @@ -40,11 +40,11 @@ #define ti_drivers_i2s_I2SCC26XX__include #include -#include -#include #include -#include #include +#include +#include +#include #ifdef __cplusplus extern "C" { @@ -76,12 +76,12 @@ extern "C" { */ typedef struct I2SCC26XX_HWAttrs_ { - PIN_Id pinSD1; /*!< Pin used for SD1 signal. */ - PIN_Id pinSD0; /*!< Pin used for SD0 signal. */ - PIN_Id pinSCK; /*!< Pin used for SCK signal. */ - PIN_Id pinMCLK; /*!< Pin used for MCLK signal. Non used in most of the applications. */ - PIN_Id pinWS; /*!< Pin used for WS signal. */ - uint8_t intPriority; /*!< I2S Peripheral's interrupt priority. */ + PIN_Id pinSD1; /*!< Pin used for SD1 signal. */ + PIN_Id pinSD0; /*!< Pin used for SD0 signal. */ + PIN_Id pinSCK; /*!< Pin used for SCK signal. */ + PIN_Id pinMCLK; /*!< Pin used for MCLK signal. Non used in most of the applications. */ + PIN_Id pinWS; /*!< Pin used for WS signal. */ + uint8_t intPriority; /*!< I2S Peripheral's interrupt priority. */ } I2SCC26XX_HWAttrs; @@ -94,9 +94,9 @@ typedef struct I2SCC26XX_HWAttrs_ */ typedef struct I2SCC26XX_DataInterface_ { - uint8_t numberOfChannelsUsed; /*!< Number of channels used on SDx. */ - I2S_ChannelConfig channelsUsed; /*!< List of the used channels. */ - I2S_DataInterfaceUse interfaceConfig; /*!< IN / OUT / UNUSED */ + uint8_t numberOfChannelsUsed; /*!< Number of channels used on SDx. */ + I2S_ChannelConfig channelsUsed; /*!< List of the used channels. */ + I2S_DataInterfaceUse interfaceConfig; /*!< IN / OUT / UNUSED */ } I2SCC26XX_DataInterface; /*! @endcond */ @@ -109,11 +109,11 @@ typedef struct I2SCC26XX_DataInterface_ */ typedef struct I2SCC26XX_Interface_ { - uint16_t memoryStep; /*!< Size of the memory step to access the following sample */ - uint16_t delay; /*!< Number of WS cycles to wait before starting the first transfer. This value is mostly used when performing constant latency transfers. */ - I2S_Callback callback; /*!< Pointer to callback */ - I2S_RegUpdate pointerSet; /*!< Pointer on the function used to update PTR-NEXT */ - I2S_Transaction* activeTransfer; /*!< Pointer on the ongoing transfer */ + uint16_t memoryStep; /*!< Size of the memory step to access the following sample */ + uint16_t delay; /*!< Number of WS cycles to wait before starting the first transfer. This value is mostly used when performing constant latency transfers. */ + I2S_Callback callback; /*!< Pointer to callback */ + I2S_RegUpdate pointerSet; /*!< Pointer on the function used to update PTR-NEXT */ + I2S_Transaction* activeTransfer; /*!< Pointer on the ongoing transfer */ } I2SCC26XX_Interface; /*! @endcond */ @@ -136,50 +136,50 @@ typedef void (*I2SCC26XX_PtrUpdate)(I2S_Handle handle, I2SCC26XX_Interface* inte typedef struct I2SCC26XX_Object_ { - bool isOpen; /*!< To avoid multiple openings of the I2S. */ - bool invertWS; /*!< WS inversion. - false: The WS signal is not internally inverted. - true: The WS signal is internally inverted. */ - uint8_t memorySlotLength; /*!< Select the size of the memory used. The two options are 16 bits and 24 bits. Any value can be selected, whatever the value of ::i2sBitsPerWord. - I2S_MEMORY_LENGTH_16BITS_CC26XX: Memory length is 16 bits. - I2S_MEMORY_LENGTH_24BITS_CC26XX: Memory length is 24 bits.*/ - uint8_t bitsPerWord; /*!< Number of bits per word (must be between 8 and 24 bits). */ - uint8_t beforeWordPadding; /*!< Number of SCK periods between the first WS edge and the MSB of the first audio channel data transferred during the phase.*/ - uint8_t afterWordPadding; /*!< Number of SCK periods between the LSB of the last audio channel data transferred during the phase and the following WS edge.*/ - uint8_t dmaBuffSizeConfig; /*!< Number of consecutive bytes of the samples buffers. This field must be set to a value x between 1 and 255. All the data buffers used must contain N*x bytes (with N an intger verifying N>0). */ - I2S_SamplingEdge samplingEdge; /*!< Select edge sampling type. - I2S_SAMPLING_EDGE_FALLING: Sampling on falling edges. - I2S_SAMPLING_EDGE_RISING: Sampling on raising edges. */ - I2S_Role moduleRole; /*!< Select if the current device is a Slave or a Master. - I2S_SLAVE: The device is a slave (clocks are generated externally). - I2S_MASTER: The device is a master (clocks are generated internally). */ - I2S_PhaseType phaseType; /*!< Select phase type. - I2S_PHASE_TYPE_SINGLE: Single phase. - I2S_PHASE_TYPE_DUAL: Dual phase.*/ - uint16_t MCLKDivider; /*!< Frequency divider for the MCLK signal. */ - uint16_t SCKDivider; /*!< Frequency divider for the SCK signal. */ - uint16_t WSDivider; /*!< Frequency divider for the WS signal. */ - uint16_t startUpDelay; /*!< Time (in number of WS cycles) to wait before the first transfer. */ - I2SCC26XX_DataInterface dataInterfaceSD0; /*!< Structure to describe the SD0 interface */ - I2SCC26XX_DataInterface dataInterfaceSD1; /*!< Structure to describe the SD1 interface */ + bool isOpen; /*!< To avoid multiple openings of the I2S. */ + bool invertWS; /*!< WS inversion. + false: The WS signal is not internally inverted. + true: The WS signal is internally inverted. */ + uint8_t memorySlotLength; /*!< Select the size of the memory used. The two options are 16 bits and 24 bits. Any value can be selected, whatever the value of ::i2sBitsPerWord. + I2S_MEMORY_LENGTH_16BITS_CC26XX: Memory length is 16 bits. + I2S_MEMORY_LENGTH_24BITS_CC26XX: Memory length is 24 bits.*/ + uint8_t bitsPerWord; /*!< Number of bits per word (must be between 8 and 24 bits). */ + uint8_t beforeWordPadding; /*!< Number of SCK periods between the first WS edge and the MSB of the first audio channel data transferred during the phase.*/ + uint8_t afterWordPadding; /*!< Number of SCK periods between the LSB of the last audio channel data transferred during the phase and the following WS edge.*/ + uint8_t dmaBuffSizeConfig; /*!< Number of consecutive bytes of the samples buffers. This field must be set to a value x between 1 and 255. All the data buffers used must contain N*x bytes (with N an intger verifying N>0). */ + I2S_SamplingEdge samplingEdge; /*!< Select edge sampling type. + I2S_SAMPLING_EDGE_FALLING: Sampling on falling edges. + I2S_SAMPLING_EDGE_RISING: Sampling on raising edges. */ + I2S_Role moduleRole; /*!< Select if the current device is a Slave or a Master. + I2S_SLAVE: The device is a slave (clocks are generated externally). + I2S_MASTER: The device is a master (clocks are generated internally). */ + I2S_PhaseType phaseType; /*!< Select phase type. + I2S_PHASE_TYPE_SINGLE: Single phase. + I2S_PHASE_TYPE_DUAL: Dual phase.*/ + uint16_t MCLKDivider; /*!< Frequency divider for the MCLK signal. */ + uint16_t SCKDivider; /*!< Frequency divider for the SCK signal. */ + uint16_t WSDivider; /*!< Frequency divider for the WS signal. */ + uint16_t startUpDelay; /*!< Time (in number of WS cycles) to wait before the first transfer. */ + I2SCC26XX_DataInterface dataInterfaceSD0; /*!< Structure to describe the SD0 interface */ + I2SCC26XX_DataInterface dataInterfaceSD1; /*!< Structure to describe the SD1 interface */ - /* PIN driver state object and handle */ - PIN_State pinState; /*!< Pin state for the used pins */ - PIN_Handle hPin; /*!< Handle on the used pins */ + /* PIN driver state object and handle */ + PIN_State pinState; /*!< Pin state for the used pins */ + PIN_Handle hPin; /*!< Handle on the used pins */ - /* I2S SYS/BIOS objects */ - HwiP_Struct hwi; /*!< Hwi object for interrupts */ - I2SCC26XX_PtrUpdate ptrUpdateFxn; /*!< Pointer on the function used to update IN and OUT PTR-NEXT */ - I2SCC26XX_Interface read; /*!< Structure to describe the read (in) interface */ - I2SCC26XX_Interface write; /*!< Structure to describe the write (out) interface */ - I2S_Callback errorCallback; /*!< Pointer to error callback */ + /* I2S SYS/BIOS objects */ + HwiP_Struct hwi; /*!< Hwi object for interrupts */ + I2SCC26XX_PtrUpdate ptrUpdateFxn; /*!< Pointer on the function used to update IN and OUT PTR-NEXT */ + I2SCC26XX_Interface read; /*!< Structure to describe the read (in) interface */ + I2SCC26XX_Interface write; /*!< Structure to describe the write (out) interface */ + I2S_Callback errorCallback; /*!< Pointer to error callback */ - /* I2S pre and post notification functions */ - void* i2sPreFxn; /*!< I2S pre-notification function pointer */ - void* i2sPostFxn; /*!< I2S post-notification function pointer */ - Power_NotifyObj i2sPreObj; /*!< I2S pre-notification object */ - Power_NotifyObj i2sPostObj; /*!< I2S post-notification object */ - volatile bool i2sPowerConstraint; /*!< I2S power constraint flag, guard to avoid power constraints getting out of sync */ + /* I2S pre and post notification functions */ + void* i2sPreFxn; /*!< I2S pre-notification function pointer */ + void* i2sPostFxn; /*!< I2S post-notification function pointer */ + Power_NotifyObj i2sPreObj; /*!< I2S pre-notification object */ + Power_NotifyObj i2sPostObj; /*!< I2S post-notification object */ + volatile bool i2sPowerConstraint; /*!< I2S power constraint flag, guard to avoid power constraints getting out of sync */ } I2SCC26XX_Object; /*! @endcond */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSCC26XX.h index 31f8b50..d4095fe 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSCC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSCC26XX.h @@ -104,10 +104,10 @@ #ifndef ti_drivers_nvs_NVSCC26XX__include #define ti_drivers_nvs_NVSCC26XX__include -#include #include +#include -#if defined (__cplusplus) +#if defined(__cplusplus) extern "C" { #endif @@ -117,7 +117,7 @@ extern "C" { * This error status is returned if the system voltage is too low to safely * perform the flash operation. Voltage must be 1.5V or greater. */ -#define NVSCC26XX_STATUS_LOW_VOLTAGE (NVS_STATUS_RESERVED - 1) +#define NVSCC26XX_STATUS_LOW_VOLTAGE (NVS_STATUS_RESERVED - 1) /*! * @internal @brief NVS function pointer table @@ -295,28 +295,28 @@ extern const NVS_FxnTable NVSCC26XX_fxnTable; */ typedef struct { - void* regionBase; /*!< The regionBase field specifies the base - address of the on-chip flash memory to be - managed. The regionBase must be aligned - to the flash sector size. This memory - cannot be shared and must be for exclusive - use by one NVS driver instance. */ + void* regionBase; /*!< The regionBase field specifies the base + address of the on-chip flash memory to be + managed. The regionBase must be aligned + to the flash sector size. This memory + cannot be shared and must be for exclusive + use by one NVS driver instance. */ - size_t regionSize; /*!< The regionSize field specifies the - overall size of the on-chip flash memory - to be managed. The regionSize must be at - least 1 flash sector size AND an integer - multiple of the flash sector size. For most - CC26XX/CC13XX devices, the flash sector - size is 4096 bytes. The NVSCC26XX driver - will determine the device's actual sector - size by reading internal system - configuration registers. */ + size_t regionSize; /*!< The regionSize field specifies the + overall size of the on-chip flash memory + to be managed. The regionSize must be at + least 1 flash sector size AND an integer + multiple of the flash sector size. For most + CC26XX/CC13XX devices, the flash sector + size is 4096 bytes. The NVSCC26XX driver + will determine the device's actual sector + size by reading internal system + configuration registers. */ #if defined(NVSCC26XX_INSTRUMENTED) - uint8_t* scoreboard; /*!< Pointer to scoreboard */ - size_t scoreboardSize; /*!< Scoreboard size in bytes */ - uint32_t flashPageSize; /*!< Size of a memory page in bytes */ + uint8_t* scoreboard; /*!< Pointer to scoreboard */ + size_t scoreboardSize; /*!< Scoreboard size in bytes */ + uint32_t flashPageSize; /*!< Size of a memory page in bytes */ #endif } NVSCC26XX_HWAttrs; @@ -327,7 +327,7 @@ typedef struct */ typedef struct { - bool opened; /* Has this region been opened */ + bool opened; /* Has this region been opened */ } NVSCC26XX_Object; /*! @@ -335,23 +335,23 @@ typedef struct * NVSCC26XX driver public APIs */ -extern void NVSCC26XX_close(NVS_Handle handle); +extern void NVSCC26XX_close(NVS_Handle handle); extern int_fast16_t NVSCC26XX_control(NVS_Handle handle, uint_fast16_t cmd, uintptr_t arg); extern int_fast16_t NVSCC26XX_erase(NVS_Handle handle, size_t offset, size_t size); -extern void NVSCC26XX_getAttrs(NVS_Handle handle, NVS_Attrs* attrs); -extern void NVSCC26XX_init(); +extern void NVSCC26XX_getAttrs(NVS_Handle handle, NVS_Attrs* attrs); +extern void NVSCC26XX_init(); extern int_fast16_t NVSCC26XX_lock(NVS_Handle handle, uint32_t timeout); -extern NVS_Handle NVSCC26XX_open(uint_least8_t index, NVS_Params* params); +extern NVS_Handle NVSCC26XX_open(uint_least8_t index, NVS_Params* params); extern int_fast16_t NVSCC26XX_read(NVS_Handle handle, size_t offset, void* buffer, size_t bufferSize); -extern void NVSCC26XX_unlock(NVS_Handle handle); +extern void NVSCC26XX_unlock(NVS_Handle handle); extern int_fast16_t NVSCC26XX_write(NVS_Handle handle, size_t offset, void* buffer, size_t bufferSize, uint_fast16_t flags); /*! @endcond */ -#if defined (__cplusplus) +#if defined(__cplusplus) } #endif /* defined (__cplusplus) */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSRAM.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSRAM.h index 682de22..4bfdd18 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSRAM.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSRAM.h @@ -50,10 +50,10 @@ #ifndef ti_drivers_nvs_NVSRAM__include #define ti_drivers_nvs_NVSRAM__include -#include #include +#include -#if defined (__cplusplus) +#if defined(__cplusplus) extern "C" { #endif @@ -130,9 +130,9 @@ extern const NVS_FxnTable NVSRAM_fxnTable; */ typedef struct { - void* regionBase; /*!< Base address of RAM region */ - size_t regionSize; /*!< The size of the region in bytes */ - size_t sectorSize; /*!< Sector size in bytes */ + void* regionBase; /*!< Base address of RAM region */ + size_t regionSize; /*!< The size of the region in bytes */ + size_t sectorSize; /*!< Sector size in bytes */ } NVSRAM_HWAttrs; /* @@ -142,8 +142,8 @@ typedef struct */ typedef struct { - size_t sectorBaseMask; - bool isOpen; + size_t sectorBaseMask; + bool isOpen; } NVSRAM_Object; /* @@ -168,7 +168,7 @@ extern int_fast16_t NVSRAM_write(NVS_Handle handle, size_t offset, /*! @endcond */ -#if defined (__cplusplus) +#if defined(__cplusplus) } #endif /* defined (__cplusplus) */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSSPI25X.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSSPI25X.h index 874c76e..ea8ddb2 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSSPI25X.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/nvs/NVSSPI25X.h @@ -191,12 +191,12 @@ #ifndef ti_drivers_nvs_NVSSPI25X__include #define ti_drivers_nvs_NVSSPI25X__include -#include #include +#include #include -#if defined (__cplusplus) +#if defined(__cplusplus) extern "C" { #endif @@ -209,7 +209,7 @@ extern "C" { * * Mass Erase is the only control command supported. */ -#define NVSSPI25X_CMD_MASS_ERASE (NVS_CMD_RESERVED + 0) +#define NVSSPI25X_CMD_MASS_ERASE (NVS_CMD_RESERVED + 0) /*! * @brief Disable internal management of SPI chip select @@ -221,7 +221,7 @@ extern "C" { * that the SPI peripheral used by the NVS driver is configured * to manage its own chip select signal. */ -#define NVSSPI25X_SPI_MANAGES_CS ((uint16_t)(~0)) +#define NVSSPI25X_SPI_MANAGES_CS ((uint16_t)(~0)) /*! * @internal @brief NVS function pointer table @@ -294,30 +294,30 @@ extern const NVS_FxnTable NVSSPI25X_fxnTable; */ typedef struct { - size_t regionBaseOffset; /*!< Offset from base of SPI flash */ - size_t regionSize; /*!< The size of the region in bytes */ - size_t sectorSize; /*!< Erase sector size */ - uint8_t* verifyBuf; /*!< Write Pre/Post verify buffer */ - size_t verifyBufSize; /*!< Write Pre/Post verify buffer size */ - SPI_Handle* spiHandle; /*!< ptr to SPI handle if provided by user. */ - uint16_t spiIndex; /*!< SPI instance index from Board file */ - uint32_t spiBitRate; /*!< SPI bit rate in Hz */ - /*! @brief SPI Flash Chip Select GPIO index + size_t regionBaseOffset; /*!< Offset from base of SPI flash */ + size_t regionSize; /*!< The size of the region in bytes */ + size_t sectorSize; /*!< Erase sector size */ + uint8_t* verifyBuf; /*!< Write Pre/Post verify buffer */ + size_t verifyBufSize; /*!< Write Pre/Post verify buffer size */ + SPI_Handle* spiHandle; /*!< ptr to SPI handle if provided by user. */ + uint16_t spiIndex; /*!< SPI instance index from Board file */ + uint32_t spiBitRate; /*!< SPI bit rate in Hz */ + /*! @brief SPI Flash Chip Select GPIO index - This field should be set to either an index within the - GPIO driver's GPIO_Config table, or to #NVSSPI25X_SPI_MANAGES_CS. - see [SPI Flash Chip Select Management] (@ref SPI_CS_MGMT) for more - details. - */ - uint16_t spiCsnGpioIndex; - /*! @brief External Flash Status Poll Delay - * - * This field determines how many microseconds the driver waits after - * querying the external flash status. Increasing this value can help - * mitigate CPU starvation if the external flash is busy for long periods - * of time, but may also result in increased latency. - */ - uint32_t statusPollDelayUs; + This field should be set to either an index within the + GPIO driver's GPIO_Config table, or to #NVSSPI25X_SPI_MANAGES_CS. + see [SPI Flash Chip Select Management] (@ref SPI_CS_MGMT) for more + details. + */ + uint16_t spiCsnGpioIndex; + /*! @brief External Flash Status Poll Delay + * + * This field determines how many microseconds the driver waits after + * querying the external flash status. Increasing this value can help + * mitigate CPU starvation if the external flash is busy for long periods + * of time, but may also result in increased latency. + */ + uint32_t statusPollDelayUs; } NVSSPI25X_HWAttrs; /* @@ -327,9 +327,9 @@ typedef struct */ typedef struct { - bool opened; /* Has this region been opened */ - SPI_Handle spiHandle; - size_t sectorBaseMask; + bool opened; /* Has this region been opened */ + SPI_Handle spiHandle; + size_t sectorBaseMask; } NVSSPI25X_Object; /* @@ -337,31 +337,31 @@ typedef struct * NVSSPI25X driver public APIs */ -extern void NVSSPI25X_close(NVS_Handle handle); +extern void NVSSPI25X_close(NVS_Handle handle); extern int_fast16_t NVSSPI25X_control(NVS_Handle handle, uint_fast16_t cmd, uintptr_t arg); extern int_fast16_t NVSSPI25X_erase(NVS_Handle handle, size_t offset, size_t size); -extern void NVSSPI25X_getAttrs(NVS_Handle handle, NVS_Attrs* attrs); -extern void NVSSPI25X_init(); +extern void NVSSPI25X_getAttrs(NVS_Handle handle, NVS_Attrs* attrs); +extern void NVSSPI25X_init(); extern int_fast16_t NVSSPI25X_lock(NVS_Handle handle, uint32_t timeout); -extern NVS_Handle NVSSPI25X_open(uint_least8_t index, NVS_Params* params); +extern NVS_Handle NVSSPI25X_open(uint_least8_t index, NVS_Params* params); extern int_fast16_t NVSSPI25X_read(NVS_Handle handle, size_t offset, void* buffer, size_t bufferSize); -extern void NVSSPI25X_unlock(NVS_Handle handle); +extern void NVSSPI25X_unlock(NVS_Handle handle); extern int_fast16_t NVSSPI25X_write(NVS_Handle handle, size_t offset, void* buffer, size_t bufferSize, uint_fast16_t flags); /* * Weakly defined APIs that can be overridden by the user */ -extern void NVSSPI25X_initSpiCs(NVS_Handle spiHandle, uint16_t csId); -extern void NVSSPI25X_deinitSpiCs(NVS_Handle spiHandle, uint16_t csId); -extern void NVSSPI25X_assertSpiCs(NVS_Handle spiHandle, uint16_t csId); -extern void NVSSPI25X_deassertSpiCs(NVS_Handle spiHandle, uint16_t csId); +extern void NVSSPI25X_initSpiCs(NVS_Handle spiHandle, uint16_t csId); +extern void NVSSPI25X_deinitSpiCs(NVS_Handle spiHandle, uint16_t csId); +extern void NVSSPI25X_assertSpiCs(NVS_Handle spiHandle, uint16_t csId); +extern void NVSSPI25X_deassertSpiCs(NVS_Handle spiHandle, uint16_t csId); /*! @endcond */ -#if defined (__cplusplus) +#if defined(__cplusplus) } #endif /* defined (__cplusplus) */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/pin/PINCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/pin/PINCC26XX.h index dc48f9c..3c604d3 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/pin/PINCC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/pin/PINCC26XX.h @@ -49,16 +49,16 @@ extern "C" { #endif -#include #include +#include #include #include #include -#include DeviceFamily_constructPath(driverlib/ioc.h) -#include DeviceFamily_constructPath(driverlib/gpio.h) +#include DeviceFamily_constructPath(driverlib / ioc.h) +#include DeviceFamily_constructPath(driverlib / gpio.h) //------------------------------------------------------------------------------ // Internal function used to find the index of the rightmost set bit in @@ -100,58 +100,58 @@ __STATIC_INLINE uint32_t PIN_ctz(uint32_t x) * used in the @c IOCFG hardware registers for efficiency. May not be mixed * with @ref PIN_GENERIC_FLAGS "device-independent I/O options". */ -#define PINCC26XX_INPUT_EN (1 << 29) ///< Enable input buffer -#define PINCC26XX_HYSTERESIS (1 << 30) ///< Enable input buffer hysteresis -#define PINCC26XX_NOPULL (0x3 << 13) ///< No pull-up or pull-down resistor -#define PINCC26XX_PULLUP (0x2 << 13) ///< ~20k pull-up resistor enabled -#define PINCC26XX_PULLDOWN (0x1 << 13) ///< ~20k pull-down resistor enabled -#define PINCC26XX_BM_INPUT_EN (0x01 << 29) ///< Bitmask for input enable option -#define PINCC26XX_BM_HYSTERESIS (0x01 << 30) ///< Bitmask for all input mode options -#define PINCC26XX_BM_PULLING (0x03 << 13) ///< Bitmask for pull-up/pull-down options +#define PINCC26XX_INPUT_EN (1 << 29) ///< Enable input buffer +#define PINCC26XX_HYSTERESIS (1 << 30) ///< Enable input buffer hysteresis +#define PINCC26XX_NOPULL (0x3 << 13) ///< No pull-up or pull-down resistor +#define PINCC26XX_PULLUP (0x2 << 13) ///< ~20k pull-up resistor enabled +#define PINCC26XX_PULLDOWN (0x1 << 13) ///< ~20k pull-down resistor enabled +#define PINCC26XX_BM_INPUT_EN (0x01 << 29) ///< Bitmask for input enable option +#define PINCC26XX_BM_HYSTERESIS (0x01 << 30) ///< Bitmask for all input mode options +#define PINCC26XX_BM_PULLING (0x03 << 13) ///< Bitmask for pull-up/pull-down options /// Bitmask for all input mode options -#define PINCC26XX_BM_INPUT_MODE (PINCC26XX_BM_INPUT_EN | PINCC26XX_BM_HYSTERESIS | \ - PINCC26XX_BM_PULLING) +#define PINCC26XX_BM_INPUT_MODE (PINCC26XX_BM_INPUT_EN | PINCC26XX_BM_HYSTERESIS | \ + PINCC26XX_BM_PULLING) -#define PINCC26XX_GPIO_OUTPUT_EN (1 << 23) ///< Enable output buffer when GPIO -#define PINCC26XX_GPIO_LOW (0 << 22) ///< Output buffer drives to VSS when GPIO -#define PINCC26XX_GPIO_HIGH (1 << 22) ///< Output buffer drives to VDD when GPIO -#define PINCC26XX_PUSHPULL (0x0 << 25) ///< Output buffer mode: push/pull -#define PINCC26XX_OPENDRAIN (0x2 << 25) ///< Output buffer mode: open drain -#define PINCC26XX_OPENSOURCE (0x3 << 25) ///< Output buffer mode: open source -#define PINCC26XX_SLEWCTRL (1 << 12) ///< Enable output buffer slew control -#define PINCC26XX_DRVSTR_MIN (0x0 << 8) ///< Drive strength is 2/2 mA -#define PINCC26XX_DRVSTR_MED (0x4 << 8) ///< Drive strength is 4/4 mA -#define PINCC26XX_DRVSTR_MAX (0x8 << 8) ///< Drive strength is 4/8 mA -#define PINCC26XX_BM_GPIO_OUTPUT_EN (1 << 23) ///< Bitmask for output enable option -#define PINCC26XX_BM_GPIO_OUTPUT_VAL (1 << 22) ///< Bitmask for output value option -#define PINCC26XX_BM_OUTPUT_BUF (3 << 25) ///< Bitmask for output buffer options -#define PINCC26XX_BM_SLEWCTRL (1 << 12) ///< Bitmask for slew control options -#define PINCC26XX_BM_DRVSTR (0xF << 8) ///< Bitmask for drive strength options +#define PINCC26XX_GPIO_OUTPUT_EN (1 << 23) ///< Enable output buffer when GPIO +#define PINCC26XX_GPIO_LOW (0 << 22) ///< Output buffer drives to VSS when GPIO +#define PINCC26XX_GPIO_HIGH (1 << 22) ///< Output buffer drives to VDD when GPIO +#define PINCC26XX_PUSHPULL (0x0 << 25) ///< Output buffer mode: push/pull +#define PINCC26XX_OPENDRAIN (0x2 << 25) ///< Output buffer mode: open drain +#define PINCC26XX_OPENSOURCE (0x3 << 25) ///< Output buffer mode: open source +#define PINCC26XX_SLEWCTRL (1 << 12) ///< Enable output buffer slew control +#define PINCC26XX_DRVSTR_MIN (0x0 << 8) ///< Drive strength is 2/2 mA +#define PINCC26XX_DRVSTR_MED (0x4 << 8) ///< Drive strength is 4/4 mA +#define PINCC26XX_DRVSTR_MAX (0x8 << 8) ///< Drive strength is 4/8 mA +#define PINCC26XX_BM_GPIO_OUTPUT_EN (1 << 23) ///< Bitmask for output enable option +#define PINCC26XX_BM_GPIO_OUTPUT_VAL (1 << 22) ///< Bitmask for output value option +#define PINCC26XX_BM_OUTPUT_BUF (3 << 25) ///< Bitmask for output buffer options +#define PINCC26XX_BM_SLEWCTRL (1 << 12) ///< Bitmask for slew control options +#define PINCC26XX_BM_DRVSTR (0xF << 8) ///< Bitmask for drive strength options /// Bitmask for all GPIO output mode options #define PINCC26XX_BM_GPIO_OUTPUT_MODE (PINCC26XX_BM_GPIO_OUTPUT_EN | PINCC26XX_BM_GPIO_OUTPUT_VAL) /// Bitmask for all output mode options -#define PINCC26XX_BM_OUTPUT_MODE (PINCC26XX_BM_GPIO_OUTPUT_MODE | PINCC26XX_BM_OUTPUT_BUF | \ - PINCC26XX_BM_SLEWCTRL | PINCC26XX_BM_DRVSTR) +#define PINCC26XX_BM_OUTPUT_MODE (PINCC26XX_BM_GPIO_OUTPUT_MODE | PINCC26XX_BM_OUTPUT_BUF | \ + PINCC26XX_BM_SLEWCTRL | PINCC26XX_BM_DRVSTR) -#define PINCC26XX_INV_INOUT (1 << 24) ///< Logically invert input and output -#define PINCC26XX_IRQ_DIS (0x0 << 16) ///< Enable IRQ on pin -#define PINCC26XX_IRQ_NEGEDGE (0x5 << 16) ///< IRQ on negative edge -#define PINCC26XX_IRQ_POSEDGE (0x6 << 16) ///< IRQ on positive edge -#define PINCC26XX_IRQ_BOTHEDGES (0x7 << 16) ///< IRQ on both edges -#define PINCC26XX_BM_INV_INOUT (1 << 24) ///< Bitmask for input/output inversion option -#define PINCC26XX_BM_IRQ (0x7 << 16) ///< Bitmask for pin interrupt option +#define PINCC26XX_INV_INOUT (1 << 24) ///< Logically invert input and output +#define PINCC26XX_IRQ_DIS (0x0 << 16) ///< Enable IRQ on pin +#define PINCC26XX_IRQ_NEGEDGE (0x5 << 16) ///< IRQ on negative edge +#define PINCC26XX_IRQ_POSEDGE (0x6 << 16) ///< IRQ on positive edge +#define PINCC26XX_IRQ_BOTHEDGES (0x7 << 16) ///< IRQ on both edges +#define PINCC26XX_BM_INV_INOUT (1 << 24) ///< Bitmask for input/output inversion option +#define PINCC26XX_BM_IRQ (0x7 << 16) ///< Bitmask for pin interrupt option -#define PINCC26XX_NO_WAKEUP (0 << 27) ///< No wakeup from shutdown for this pin -#define PINCC26XX_WAKEUP_POSEDGE (3 << 27) ///< Wakeup from shutdown on positive edge -#define PINCC26XX_WAKEUP_NEGEDGE (2 << 27) ///< Wakeup from shutdown on negative edge -#define PINCC26XX_BM_WAKEUP (3 << 27) ///< Bitmask for pin wakeup from shutdown option +#define PINCC26XX_NO_WAKEUP (0 << 27) ///< No wakeup from shutdown for this pin +#define PINCC26XX_WAKEUP_POSEDGE (3 << 27) ///< Wakeup from shutdown on positive edge +#define PINCC26XX_WAKEUP_NEGEDGE (2 << 27) ///< Wakeup from shutdown on negative edge +#define PINCC26XX_BM_WAKEUP (3 << 27) ///< Bitmask for pin wakeup from shutdown option /// Bitmask for all pin options in IOCFG register -#define PINCC26XX_BM_IOCFG (PINCC26XX_BM_INPUT_MODE|PINCC26XX_BM_OUTPUT_BUF | \ - PINCC26XX_BM_SLEWCTRL | PINCC26XX_BM_DRVSTR | \ - PINCC26XX_BM_INV_INOUT | PINCC26XX_BM_IRQ | PINCC26XX_BM_WAKEUP) +#define PINCC26XX_BM_IOCFG (PINCC26XX_BM_INPUT_MODE | PINCC26XX_BM_OUTPUT_BUF | \ + PINCC26XX_BM_SLEWCTRL | PINCC26XX_BM_DRVSTR | \ + PINCC26XX_BM_INV_INOUT | PINCC26XX_BM_IRQ | PINCC26XX_BM_WAKEUP) /// Bitmask for all pin options -#define PINCC26XX_BM_ALL (PINCC26XX_BM_IOCFG | PINCC26XX_BM_GPIO_OUTPUT_MODE) +#define PINCC26XX_BM_ALL (PINCC26XX_BM_IOCFG | PINCC26XX_BM_GPIO_OUTPUT_MODE) /** \} (PINCC26XX_FLAGS) */ @@ -164,38 +164,38 @@ __STATIC_INLINE uint32_t PIN_ctz(uint32_t x) * PIN_ID(5). For convenience and readability aliases are defined below for * all DIOs. */ -#define PINCC26XX_DIO0 0 -#define PINCC26XX_DIO1 1 -#define PINCC26XX_DIO2 2 -#define PINCC26XX_DIO3 3 -#define PINCC26XX_DIO4 4 -#define PINCC26XX_DIO5 5 -#define PINCC26XX_DIO6 6 -#define PINCC26XX_DIO7 7 -#define PINCC26XX_DIO8 8 -#define PINCC26XX_DIO9 9 -#define PINCC26XX_DIO10 10 -#define PINCC26XX_DIO11 11 -#define PINCC26XX_DIO12 12 -#define PINCC26XX_DIO13 13 -#define PINCC26XX_DIO14 14 -#define PINCC26XX_DIO15 15 -#define PINCC26XX_DIO16 16 -#define PINCC26XX_DIO17 17 -#define PINCC26XX_DIO18 18 -#define PINCC26XX_DIO19 19 -#define PINCC26XX_DIO20 20 -#define PINCC26XX_DIO21 21 -#define PINCC26XX_DIO22 22 -#define PINCC26XX_DIO23 23 -#define PINCC26XX_DIO24 24 -#define PINCC26XX_DIO25 25 -#define PINCC26XX_DIO26 26 -#define PINCC26XX_DIO27 27 -#define PINCC26XX_DIO28 28 -#define PINCC26XX_DIO29 29 -#define PINCC26XX_DIO30 30 -#define PINCC26XX_DIO31 31 +#define PINCC26XX_DIO0 0 +#define PINCC26XX_DIO1 1 +#define PINCC26XX_DIO2 2 +#define PINCC26XX_DIO3 3 +#define PINCC26XX_DIO4 4 +#define PINCC26XX_DIO5 5 +#define PINCC26XX_DIO6 6 +#define PINCC26XX_DIO7 7 +#define PINCC26XX_DIO8 8 +#define PINCC26XX_DIO9 9 +#define PINCC26XX_DIO10 10 +#define PINCC26XX_DIO11 11 +#define PINCC26XX_DIO12 12 +#define PINCC26XX_DIO13 13 +#define PINCC26XX_DIO14 14 +#define PINCC26XX_DIO15 15 +#define PINCC26XX_DIO16 16 +#define PINCC26XX_DIO17 17 +#define PINCC26XX_DIO18 18 +#define PINCC26XX_DIO19 19 +#define PINCC26XX_DIO20 20 +#define PINCC26XX_DIO21 21 +#define PINCC26XX_DIO22 22 +#define PINCC26XX_DIO23 23 +#define PINCC26XX_DIO24 24 +#define PINCC26XX_DIO25 25 +#define PINCC26XX_DIO26 26 +#define PINCC26XX_DIO27 27 +#define PINCC26XX_DIO28 28 +#define PINCC26XX_DIO29 29 +#define PINCC26XX_DIO30 30 +#define PINCC26XX_DIO31 31 /** \} (PINCC26XX_IONAMES) */ @@ -205,7 +205,6 @@ __STATIC_INLINE uint32_t PINCC26XX_getInputValue(PIN_Id pinId) return (HWREG(GPIO_BASE + GPIO_O_DIN31_0) >> pinId) & 1; } - /* @brief Fast/efficient version of #PIN_setOutputEnable() * @note Does not include any checks on handle for efficiency reasons, * use #PIN_setOutputEnable() for checked version @@ -218,7 +217,6 @@ __STATIC_INLINE void PINCC26XX_setOutputEnable(PIN_Id pinId, bool outputEnable) HwiP_restore(key); } - /* @brief Fast/efficient version of #PIN_setOutputValue() * @note Does not include any checks on handle for efficiency reasons, * use #PIN_setOutputValue() for checked version @@ -228,20 +226,17 @@ __STATIC_INLINE void PINCC26XX_setOutputValue(PIN_Id pinId, uint32_t val) HWREGB(GPIO_BASE + GPIO_O_DOUT3_0 + pinId) = (val) ? 1 : 0; } - /// @brief Fast/efficient version of #PIN_getOutputValue() __STATIC_INLINE uint32_t PINCC26XX_getOutputValue(PIN_Id pinId) { return (HWREG(GPIO_BASE + GPIO_O_DOUT31_0) >> pinId) & 1; } - __STATIC_INLINE void PINCC26XX_clrPendInterrupt(PIN_Id pinId) { HWREG(GPIO_NONBUF_BASE + GPIO_O_EVFLAGS31_0) = (1 << pinId); } - /// @brief Fast/efficient version of #PIN_getPortInputValue() __STATIC_INLINE uint32_t PINCC26XX_getPortInputValue(PIN_Handle handle) { @@ -249,7 +244,6 @@ __STATIC_INLINE uint32_t PINCC26XX_getPortInputValue(PIN_Handle handle) return HWREG(GPIO_BASE + GPIO_O_DIN31_0); } - /// @brief Fast/efficient version of #PIN_getPortOutputValue() __STATIC_INLINE uint32_t PINCC26XX_getPortOutputValue(PIN_Handle handle) { @@ -257,7 +251,6 @@ __STATIC_INLINE uint32_t PINCC26XX_getPortOutputValue(PIN_Handle handle) return HWREG(GPIO_BASE + GPIO_O_DOUT31_0); } - /* @brief Fast/efficient version of #PIN_setPortOutputValue() * @note Does not include any checks on handle for efficiency reasons, * use #PIN_setPortOutputValue() for checked version @@ -269,7 +262,6 @@ __STATIC_INLINE void PINCC26XX_setPortOutputValue(PIN_Handle handle, uint32_t ou (HWREG(GPIO_BASE + GPIO_O_DOUT31_0) ^ outputValueMask) & handle->portMask; } - /* @brief Fast/efficient version of #PIN_setPortOutputEnable() * @note Does not include any checks on handle for efficiency reasons, * use #PIN_setPortOutputEnable() for checked version @@ -283,7 +275,6 @@ __STATIC_INLINE void PINCC26XX_setPortOutputEnable(PIN_Handle handle, uint32_t o HwiP_restore(key); } - /** @brief Returns CC26xx device-specific pin configuration * * @param pinId Pin ID @@ -293,7 +284,6 @@ __STATIC_INLINE void PINCC26XX_setPortOutputEnable(PIN_Handle handle, uint32_t o */ extern PIN_Config PINCC26XX_getConfig(PIN_Id pinId); - /** @brief Configure wakeup (from shutdown) on pins * * @param aPinCfg #PIN_Config list identifying pin ID and relevant pin @@ -316,7 +306,6 @@ extern PIN_Config PINCC26XX_getConfig(PIN_Id pinId); */ extern PIN_Status PINCC26XX_setWakeup(const PIN_Config aPinCfg[]); - /** @brief Get device-specific pin mapping to GPIO, HW peripheral or HW signal * * @param pinId Pin ID @@ -373,26 +362,26 @@ extern PIN_Status PINCC26XX_setMux(PIN_Handle handle, PIN_Id pinId, int32_t nMux */ typedef struct PINCC26XX_HWAttrs { - /*! @brief SPI CC26XXDMA Peripheral's interrupt priority. + /*! @brief SPI CC26XXDMA Peripheral's interrupt priority. - The CC26xx uses three of the priority bits, - meaning ~0 has the same effect as (7 << 5). + The CC26xx uses three of the priority bits, + meaning ~0 has the same effect as (7 << 5). - (7 << 5) will apply the lowest priority. + (7 << 5) will apply the lowest priority. - (1 << 5) will apply the highest priority. + (1 << 5) will apply the highest priority. - Setting the priority to 0 is not supported by this driver. + Setting the priority to 0 is not supported by this driver. - HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. - */ - uint8_t intPriority; - /*! @brief SPI SWI priority. - The higher the number, the higher the priority. - The minimum is 0 and the maximum is 15 by default. - The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. - */ - uint32_t swiPriority; + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! @brief SPI SWI priority. + The higher the number, the higher the priority. + The minimum is 0 and the maximum is 15 by default. + The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. + */ + uint32_t swiPriority; } PINCC26XX_HWAttrs; /** @anchor PINCC26XX_MUX_VALS @@ -402,52 +391,51 @@ typedef struct PINCC26XX_HWAttrs * CC26XX-specific mux vakues used in conjunction with #PINCC26XX_setMux() to * map hardware peripheral ports, GPIO or observation signals to pins. */ -#define PINCC26XX_MUX_GPIO IOC_PORT_GPIO // Default general purpose IO usage -#define PINCC26XX_MUX_AON_CLK32K IOC_PORT_AON_CLK32K // AON External 32kHz clock -#define PINCC26XX_MUX_AUX_IO IOC_PORT_AUX_IO // AUX IO Pin -#define PINCC26XX_MUX_MCU_SSI0_RX IOC_PORT_MCU_SSI0_RX // MCU SSI0 Receive Pin -#define PINCC26XX_MUX_MCU_SSI0_TX IOC_PORT_MCU_SSI0_TX // MCU SSI0 Transmit Pin -#define PINCC26XX_MUX_MCU_SSI0_FSS IOC_PORT_MCU_SSI0_FSS // MCU SSI0 FSS Pin -#define PINCC26XX_MUX_MCU_SSI0_CLK IOC_PORT_MCU_SSI0_CLK // MCU SSI0 Clock Pin -#define PINCC26XX_MUX_MCU_I2C_MSSDA IOC_PORT_MCU_I2C_MSSDA // MCU I2C Data Pin -#define PINCC26XX_MUX_MCU_I2C_MSSCL IOC_PORT_MCU_I2C_MSSCL // MCU I2C Clock Pin -#define PINCC26XX_MUX_MCU_UART0_RX IOC_PORT_MCU_UART0_RX // MCU UART0 Receive Pin -#define PINCC26XX_MUX_MCU_UART0_TX IOC_PORT_MCU_UART0_TX // MCU UART0 Transmit Pin -#define PINCC26XX_MUX_MCU_UART0_CTS IOC_PORT_MCU_UART0_CTS // MCU UART0 Clear To Send Pin -#define PINCC26XX_MUX_MCU_UART0_RTS IOC_PORT_MCU_UART0_RTS // MCU UART0 Request To Send Pin -#define PINCC26XX_MUX_MCU_PORT_EV_0 IOC_PORT_MCU_PORT_EVENT0 // MCU power event 0 -#define PINCC26XX_MUX_MCU_PORT_EV_1 IOC_PORT_MCU_PORT_EVENT1 // MCU power event 1 -#define PINCC26XX_MUX_MCU_PORT_EV_2 IOC_PORT_MCU_PORT_EVENT2 // MCU power event 2 -#define PINCC26XX_MUX_MCU_PORT_EV_3 IOC_PORT_MCU_PORT_EVENT3 // MCU power event 3 -#define PINCC26XX_MUX_MCU_PORT_EV_4 IOC_PORT_MCU_PORT_EVENT4 // MCU power event 4 -#define PINCC26XX_MUX_MCU_PORT_EV_5 IOC_PORT_MCU_PORT_EVENT5 // MCU power event 5 -#define PINCC26XX_MUX_MCU_PORT_EV_6 IOC_PORT_MCU_PORT_EVENT6 // MCU power event 6 -#define PINCC26XX_MUX_MCU_PORT_EV_7 IOC_PORT_MCU_PORT_EVENT7 // MCU power event 7 -#define PINCC26XX_MUX_SWV IOC_PORT_MCU_SWV // MCU serial wire viewer -#define PINCC26XX_MUX_MCU_SSI1_RX IOC_PORT_MCU_SSI1_RX // MCU SSI1 Receive Pin -#define PINCC26XX_MUX_MCU_SSI1_TX IOC_PORT_MCU_SSI1_TX // MCU SSI1 Transmit Pin -#define PINCC26XX_MUX_MCU_SSI1_FSS IOC_PORT_MCU_SSI1_FSS // MCU SSI1 FSS Pin -#define PINCC26XX_MUX_MCU_SSI1_CLK IOC_PORT_MCU_SSI1_CLK // MCU SSI1 Clock Pin -#define PINCC26XX_MUX_MCU_I2S_AD0 IOC_PORT_MCU_I2S_AD0 // MCU I2S Data Pin 0 -#define PINCC26XX_MUX_MCU_I2S_AD1 IOC_PORT_MCU_I2S_AD1 // MCU I2S Data Pin 1 -#define PINCC26XX_MUX_MCU_I2S_WCLK IOC_PORT_MCU_I2S_WCLK // MCU I2S Frame/Word Clock -#define PINCC26XX_MUX_MCU_I2S_BCLK IOC_PORT_MCU_I2S_BCLK // MCU I2S Bit Clock -#define PINCC26XX_MUX_MCU_I2S_MCLK IOC_PORT_MCU_I2S_MCLK // MCU I2S Master clock 2 -#define PINCC26XX_MUX_RFC_TRC IOC_PORT_RFC_TRC // RF Core Tracer -#define PINCC26XX_MUX_RFC_GPO0 IOC_PORT_RFC_GPO0 // RC Core Data Out Pin 0 -#define PINCC26XX_MUX_RFC_GPO1 IOC_PORT_RFC_GPO1 // RC Core Data Out Pin 1 -#define PINCC26XX_MUX_RFC_GPO2 IOC_PORT_RFC_GPO2 // RC Core Data Out Pin 2 -#define PINCC26XX_MUX_RFC_GPO3 IOC_PORT_RFC_GPO3 // RC Core Data Out Pin 3 -#define PINCC26XX_MUX_RFC_GPI0 IOC_PORT_RFC_GPI0 // RC Core Data In Pin 0 -#define PINCC26XX_MUX_RFC_GPI1 IOC_PORT_RFC_GPI1 // RC Core Data In Pin 1 -#define PINCC26XX_MUX_RFC_SMI_DL_OUT IOC_PORT_RFC_SMI_DL_OUT // RF Core SMI Data Link Out -#define PINCC26XX_MUX_RFC_SMI_DL_IN IOC_PORT_RFC_SMI_DL_IN // RF Core SMI Data Link in -#define PINCC26XX_MUX_RFC_SMI_CL_OUT IOC_PORT_RFC_SMI_CL_OUT // RF Core SMI Command Link Out -#define PINCC26XX_MUX_RFC_SMI_CL_IN IOC_PORT_RFC_SMI_CL_IN // RF Core SMI Command Link In +#define PINCC26XX_MUX_GPIO IOC_PORT_GPIO // Default general purpose IO usage +#define PINCC26XX_MUX_AON_CLK32K IOC_PORT_AON_CLK32K // AON External 32kHz clock +#define PINCC26XX_MUX_AUX_IO IOC_PORT_AUX_IO // AUX IO Pin +#define PINCC26XX_MUX_MCU_SSI0_RX IOC_PORT_MCU_SSI0_RX // MCU SSI0 Receive Pin +#define PINCC26XX_MUX_MCU_SSI0_TX IOC_PORT_MCU_SSI0_TX // MCU SSI0 Transmit Pin +#define PINCC26XX_MUX_MCU_SSI0_FSS IOC_PORT_MCU_SSI0_FSS // MCU SSI0 FSS Pin +#define PINCC26XX_MUX_MCU_SSI0_CLK IOC_PORT_MCU_SSI0_CLK // MCU SSI0 Clock Pin +#define PINCC26XX_MUX_MCU_I2C_MSSDA IOC_PORT_MCU_I2C_MSSDA // MCU I2C Data Pin +#define PINCC26XX_MUX_MCU_I2C_MSSCL IOC_PORT_MCU_I2C_MSSCL // MCU I2C Clock Pin +#define PINCC26XX_MUX_MCU_UART0_RX IOC_PORT_MCU_UART0_RX // MCU UART0 Receive Pin +#define PINCC26XX_MUX_MCU_UART0_TX IOC_PORT_MCU_UART0_TX // MCU UART0 Transmit Pin +#define PINCC26XX_MUX_MCU_UART0_CTS IOC_PORT_MCU_UART0_CTS // MCU UART0 Clear To Send Pin +#define PINCC26XX_MUX_MCU_UART0_RTS IOC_PORT_MCU_UART0_RTS // MCU UART0 Request To Send Pin +#define PINCC26XX_MUX_MCU_PORT_EV_0 IOC_PORT_MCU_PORT_EVENT0 // MCU power event 0 +#define PINCC26XX_MUX_MCU_PORT_EV_1 IOC_PORT_MCU_PORT_EVENT1 // MCU power event 1 +#define PINCC26XX_MUX_MCU_PORT_EV_2 IOC_PORT_MCU_PORT_EVENT2 // MCU power event 2 +#define PINCC26XX_MUX_MCU_PORT_EV_3 IOC_PORT_MCU_PORT_EVENT3 // MCU power event 3 +#define PINCC26XX_MUX_MCU_PORT_EV_4 IOC_PORT_MCU_PORT_EVENT4 // MCU power event 4 +#define PINCC26XX_MUX_MCU_PORT_EV_5 IOC_PORT_MCU_PORT_EVENT5 // MCU power event 5 +#define PINCC26XX_MUX_MCU_PORT_EV_6 IOC_PORT_MCU_PORT_EVENT6 // MCU power event 6 +#define PINCC26XX_MUX_MCU_PORT_EV_7 IOC_PORT_MCU_PORT_EVENT7 // MCU power event 7 +#define PINCC26XX_MUX_SWV IOC_PORT_MCU_SWV // MCU serial wire viewer +#define PINCC26XX_MUX_MCU_SSI1_RX IOC_PORT_MCU_SSI1_RX // MCU SSI1 Receive Pin +#define PINCC26XX_MUX_MCU_SSI1_TX IOC_PORT_MCU_SSI1_TX // MCU SSI1 Transmit Pin +#define PINCC26XX_MUX_MCU_SSI1_FSS IOC_PORT_MCU_SSI1_FSS // MCU SSI1 FSS Pin +#define PINCC26XX_MUX_MCU_SSI1_CLK IOC_PORT_MCU_SSI1_CLK // MCU SSI1 Clock Pin +#define PINCC26XX_MUX_MCU_I2S_AD0 IOC_PORT_MCU_I2S_AD0 // MCU I2S Data Pin 0 +#define PINCC26XX_MUX_MCU_I2S_AD1 IOC_PORT_MCU_I2S_AD1 // MCU I2S Data Pin 1 +#define PINCC26XX_MUX_MCU_I2S_WCLK IOC_PORT_MCU_I2S_WCLK // MCU I2S Frame/Word Clock +#define PINCC26XX_MUX_MCU_I2S_BCLK IOC_PORT_MCU_I2S_BCLK // MCU I2S Bit Clock +#define PINCC26XX_MUX_MCU_I2S_MCLK IOC_PORT_MCU_I2S_MCLK // MCU I2S Master clock 2 +#define PINCC26XX_MUX_RFC_TRC IOC_PORT_RFC_TRC // RF Core Tracer +#define PINCC26XX_MUX_RFC_GPO0 IOC_PORT_RFC_GPO0 // RC Core Data Out Pin 0 +#define PINCC26XX_MUX_RFC_GPO1 IOC_PORT_RFC_GPO1 // RC Core Data Out Pin 1 +#define PINCC26XX_MUX_RFC_GPO2 IOC_PORT_RFC_GPO2 // RC Core Data Out Pin 2 +#define PINCC26XX_MUX_RFC_GPO3 IOC_PORT_RFC_GPO3 // RC Core Data Out Pin 3 +#define PINCC26XX_MUX_RFC_GPI0 IOC_PORT_RFC_GPI0 // RC Core Data In Pin 0 +#define PINCC26XX_MUX_RFC_GPI1 IOC_PORT_RFC_GPI1 // RC Core Data In Pin 1 +#define PINCC26XX_MUX_RFC_SMI_DL_OUT IOC_PORT_RFC_SMI_DL_OUT // RF Core SMI Data Link Out +#define PINCC26XX_MUX_RFC_SMI_DL_IN IOC_PORT_RFC_SMI_DL_IN // RF Core SMI Data Link in +#define PINCC26XX_MUX_RFC_SMI_CL_OUT IOC_PORT_RFC_SMI_CL_OUT // RF Core SMI Command Link Out +#define PINCC26XX_MUX_RFC_SMI_CL_IN IOC_PORT_RFC_SMI_CL_IN // RF Core SMI Command Link In /** \} (PINCC26XX_MUX_VALS) */ - #ifdef __cplusplus } #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26X2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26X2.h index 5ab068f..bf45727 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26X2.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26X2.h @@ -56,44 +56,44 @@ extern "C" { #endif -#include -#include #include +#include +#include #include /*! The latency to reserve for resume from STANDBY (usec). */ -#define PowerCC26X2_RESUMETIMESTANDBY 750 +#define PowerCC26X2_RESUMETIMESTANDBY 750 /*! The total latency to reserve for entry to and exit from STANDBY (usec). */ -#define PowerCC26X2_TOTALTIMESTANDBY 1000 +#define PowerCC26X2_TOTALTIMESTANDBY 1000 /*! The initial delay when waking from STANDBY (usec). */ -#define PowerCC26X2_WAKEDELAYSTANDBY 240 +#define PowerCC26X2_WAKEDELAYSTANDBY 240 /*! The initial wait time (usec) before checking if RCOSC_LF is stable. */ #define PowerCC26X2_INITIALWAITRCOSC_LF 1000 /*! The retry wait time (usec) when checking to see if RCOSC_LF is stable. */ -#define PowerCC26X2_RETRYWAITRCOSC_LF 1000 +#define PowerCC26X2_RETRYWAITRCOSC_LF 1000 /*! The initial wait time (usec) before checking if XOSC_HF is stable. */ -#define PowerCC26X2_INITIALWAITXOSC_HF 50 +#define PowerCC26X2_INITIALWAITXOSC_HF 50 /*! The retry wait time (usec) when checking to see if XOSC_HF is stable. */ -#define PowerCC26X2_RETRYWAITXOSC_HF 50 +#define PowerCC26X2_RETRYWAITXOSC_HF 50 /*! The initial wait time (usec) before checking if XOSC_LF is stable. */ -#define PowerCC26X2_INITIALWAITXOSC_LF 10000 +#define PowerCC26X2_INITIALWAITXOSC_LF 10000 /*! The retry wait time (usec) when checking to see if XOSC_LF is stable. */ -#define PowerCC26X2_RETRYWAITXOSC_LF 5000 +#define PowerCC26X2_RETRYWAITXOSC_LF 5000 -#define PowerCC26X2_PERIPH_PKA PowerCC26XX_NUMRESOURCES /*!< Resource ID: PKA Module */ +#define PowerCC26X2_PERIPH_PKA PowerCC26XX_NUMRESOURCES /*!< Resource ID: PKA Module */ -#define PowerCC26X2_PERIPH_UART1 PowerCC26XX_NUMRESOURCES + 1 /*!< Resource ID: UART1 */ +#define PowerCC26X2_PERIPH_UART1 PowerCC26XX_NUMRESOURCES + 1 /*!< Resource ID: UART1 */ /* \cond */ -#define PowerCC26X2_NUMRESOURCES (PowerCC26XX_NUMRESOURCES + 2) /* Number of resources in database */ +#define PowerCC26X2_NUMRESOURCES (PowerCC26XX_NUMRESOURCES + 2) /* Number of resources in database */ /* \endcond */ /* \cond */ @@ -104,87 +104,86 @@ extern "C" { /* * Calibration stages */ -#define PowerCC26X2_SETUP_CALIBRATE 1 -#define PowerCC26X2_INITIATE_CALIBRATE 2 -#define PowerCC26X2_DO_CALIBRATE 3 +#define PowerCC26X2_SETUP_CALIBRATE 1 +#define PowerCC26X2_INITIATE_CALIBRATE 2 +#define PowerCC26X2_DO_CALIBRATE 3 /* \endcond */ - /*! @brief Global configuration structure */ typedef struct PowerCC26X2_Config { - /*! - * @brief The Power Policy's initialization function - * - * If the policy does not have an initialization function, 'NULL' - * should be specified. - */ - Power_PolicyInitFxn policyInitFxn; - /*! - * @brief The Power Policy function - * - * When enabled, this function is invoked in the idle loop, to - * opportunistically select and activate sleep states. - * - * Two reference policies are provided: - * - * PowerCC26X2_doWFI() - a simple policy that invokes CPU wait for - * interrupt (WFI) - * - * PowerCC26X2_standbyPolicy() - an agressive policy that considers - * constraints, time until next scheduled work, and sleep state - * latencies, and optionally puts the device into the STANDBY state, - * the IDLE state, or as a minimum, WFI. - * - * Custom policies can be written, and specified via this function pointer. - * - * In addition to this static selection, the Power Policy can be - * dynamically changed at runtime, via the Power_setPolicy() API. - */ - Power_PolicyFxn policyFxn; - /*! - * @brief The function to be used for activating RC Oscillator (RCOSC) - * calibration - * - * Calibration is normally enabled, via specification of the function - * PowerCC26X2_calibrate(). This enables high accuracy operation, and - * faster high frequency crystal oscillator (XOSC_HF) startups. - * - * To disable RCOSC calibration, the function PowerCC26X2_noCalibrate() - * should be specified. - */ - bool (*calibrateFxn)(unsigned int); - /*! - * @brief Boolean specifying if the Power Policy function is enabled - * - * If 'true', the policy function will be invoked once for each pass - * of the idle loop. - * - * If 'false', the policy will not be invoked. - * - * In addition to this static setting, the power policy can be dynamically - * enabled and disabled at runtime, via the Power_enablePolicy() and - * Power_disablePolicy() functions, respectively. - */ - bool enablePolicy; - /*! - * @brief Boolean specifying whether the low frequency RC oscillator - * (RCOSC_LF) should be calibrated. - * - * If RCOSC calibration is enabled (above, via specification of - * an appropriate calibrateFxn), this Boolean specifies whether - * RCOSC_LF should be calibrated. - */ - bool calibrateRCOSC_LF; - /*! - * @brief Boolean specifying whether the high frequency RC oscillator - * (RCOSC_HF) should be calibrated. - * - * If RCOSC calibration is enabled (above, via specification of - * an appropriate calibrateFxn), this Boolean specifies whether - * RCOSC_HF should be calibrated. - */ - bool calibrateRCOSC_HF; + /*! + * @brief The Power Policy's initialization function + * + * If the policy does not have an initialization function, 'NULL' + * should be specified. + */ + Power_PolicyInitFxn policyInitFxn; + /*! + * @brief The Power Policy function + * + * When enabled, this function is invoked in the idle loop, to + * opportunistically select and activate sleep states. + * + * Two reference policies are provided: + * + * PowerCC26X2_doWFI() - a simple policy that invokes CPU wait for + * interrupt (WFI) + * + * PowerCC26X2_standbyPolicy() - an agressive policy that considers + * constraints, time until next scheduled work, and sleep state + * latencies, and optionally puts the device into the STANDBY state, + * the IDLE state, or as a minimum, WFI. + * + * Custom policies can be written, and specified via this function pointer. + * + * In addition to this static selection, the Power Policy can be + * dynamically changed at runtime, via the Power_setPolicy() API. + */ + Power_PolicyFxn policyFxn; + /*! + * @brief The function to be used for activating RC Oscillator (RCOSC) + * calibration + * + * Calibration is normally enabled, via specification of the function + * PowerCC26X2_calibrate(). This enables high accuracy operation, and + * faster high frequency crystal oscillator (XOSC_HF) startups. + * + * To disable RCOSC calibration, the function PowerCC26X2_noCalibrate() + * should be specified. + */ + bool (*calibrateFxn)(unsigned int); + /*! + * @brief Boolean specifying if the Power Policy function is enabled + * + * If 'true', the policy function will be invoked once for each pass + * of the idle loop. + * + * If 'false', the policy will not be invoked. + * + * In addition to this static setting, the power policy can be dynamically + * enabled and disabled at runtime, via the Power_enablePolicy() and + * Power_disablePolicy() functions, respectively. + */ + bool enablePolicy; + /*! + * @brief Boolean specifying whether the low frequency RC oscillator + * (RCOSC_LF) should be calibrated. + * + * If RCOSC calibration is enabled (above, via specification of + * an appropriate calibrateFxn), this Boolean specifies whether + * RCOSC_LF should be calibrated. + */ + bool calibrateRCOSC_LF; + /*! + * @brief Boolean specifying whether the high frequency RC oscillator + * (RCOSC_HF) should be calibrated. + * + * If RCOSC calibration is enabled (above, via specification of + * an appropriate calibrateFxn), this Boolean specifies whether + * RCOSC_HF should be calibrated. + */ + bool calibrateRCOSC_HF; } PowerCC26X2_Config; /*! @@ -195,40 +194,39 @@ typedef struct PowerCC26X2_Config */ typedef struct PowerCC26X2_ModuleState { - List_List notifyList; /*!< Event notification list */ - uint32_t constraintMask; /*!< Aggregate constraints mask */ - ClockP_Struct clockObj; /*!< Clock object for scheduling wakeups */ - ClockP_Struct calibrationClock; /*!< Clock object for scheduling wakeups */ - HwiP_Struct oscHwi; /*!< Hwi object for oscillator stabilisation */ - HwiP_Struct tdcHwi; /*!< Hwi object for RCOSC calibration */ - int32_t nDeltaFreqCurr; /*!< RCOSC calibration variable */ - int32_t nCtrimCurr; /*!< RCOSC calibration variable */ - int32_t nCtrimFractCurr; /*!< RCOSC calibration variable */ - int32_t nCtrimNew; /*!< RCOSC calibration variable */ - int32_t nCtrimFractNew; /*!< RCOSC calibration variable */ - int32_t nRtrimNew; /*!< RCOSC calibration variable */ - int32_t nRtrimCurr; /*!< RCOSC calibration variable */ - int32_t nDeltaFreqNew; /*!< RCOSC calibration variable */ - bool bRefine; /*!< RCOSC calibration variable */ - uint32_t state; /*!< Current transition state */ - bool xoscPending; /*!< Is XOSC_HF activation in progress? */ - bool calLF; /*!< Calibrate RCOSC_LF? */ - uint8_t auxHwiState; /*!< The AUX ISR calibration state */ - bool busyCal; /*!< Already busy calibrating? */ - uint32_t calStep; /*!< The current calibration step */ - bool firstLF; /*!< Is this the first LF calibration? */ - bool enablePolicy; /*!< Is the Power policy enabled? */ - bool initialized; /*!< Has Power_init() been called? */ - uint8_t constraintCounts[PowerCC26X2_NUMCONSTRAINTS]; - /*!< Array to maintain constraint reference counts */ - uint8_t resourceCounts[PowerCC26X2_NUMRESOURCES]; - /*!< Array to maintain resource dependency reference counts */ - unsigned int (*resourceHandlers[3])(unsigned int); - /*!< Array of special dependency handler functions */ - Power_PolicyFxn policyFxn; /*!< The Power policy function */ + List_List notifyList; /*!< Event notification list */ + uint32_t constraintMask; /*!< Aggregate constraints mask */ + ClockP_Struct clockObj; /*!< Clock object for scheduling wakeups */ + ClockP_Struct calibrationClock; /*!< Clock object for scheduling wakeups */ + HwiP_Struct oscHwi; /*!< Hwi object for oscillator stabilisation */ + HwiP_Struct tdcHwi; /*!< Hwi object for RCOSC calibration */ + int32_t nDeltaFreqCurr; /*!< RCOSC calibration variable */ + int32_t nCtrimCurr; /*!< RCOSC calibration variable */ + int32_t nCtrimFractCurr; /*!< RCOSC calibration variable */ + int32_t nCtrimNew; /*!< RCOSC calibration variable */ + int32_t nCtrimFractNew; /*!< RCOSC calibration variable */ + int32_t nRtrimNew; /*!< RCOSC calibration variable */ + int32_t nRtrimCurr; /*!< RCOSC calibration variable */ + int32_t nDeltaFreqNew; /*!< RCOSC calibration variable */ + bool bRefine; /*!< RCOSC calibration variable */ + uint32_t state; /*!< Current transition state */ + bool xoscPending; /*!< Is XOSC_HF activation in progress? */ + bool calLF; /*!< Calibrate RCOSC_LF? */ + uint8_t auxHwiState; /*!< The AUX ISR calibration state */ + bool busyCal; /*!< Already busy calibrating? */ + uint32_t calStep; /*!< The current calibration step */ + bool firstLF; /*!< Is this the first LF calibration? */ + bool enablePolicy; /*!< Is the Power policy enabled? */ + bool initialized; /*!< Has Power_init() been called? */ + uint8_t constraintCounts[PowerCC26X2_NUMCONSTRAINTS]; + /*!< Array to maintain constraint reference counts */ + uint8_t resourceCounts[PowerCC26X2_NUMRESOURCES]; + /*!< Array to maintain resource dependency reference counts */ + unsigned int (*resourceHandlers[3])(unsigned int); + /*!< Array of special dependency handler functions */ + Power_PolicyFxn policyFxn; /*!< The Power policy function */ } PowerCC26X2_ModuleState; - #ifdef __cplusplus } #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26XX.h index 7ed560d..bf2175d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/power/PowerCC26XX.h @@ -56,126 +56,126 @@ extern "C" { #endif -#include -#include #include +#include +#include /* \cond */ typedef uint8_t PowerCC26XX_Resource; /* Resource identifier */ /* \endcond */ /*! The latency to reserve for resume from STANDBY (usec). */ -#define PowerCC26XX_RESUMETIMESTANDBY 750 +#define PowerCC26XX_RESUMETIMESTANDBY 750 /*! The total latency to reserve for entry to and exit from STANDBY (usec). */ -#define PowerCC26XX_TOTALTIMESTANDBY 1000 +#define PowerCC26XX_TOTALTIMESTANDBY 1000 /*! The initial delay when waking from STANDBY (usec). */ -#define PowerCC26XX_WAKEDELAYSTANDBY 240 +#define PowerCC26XX_WAKEDELAYSTANDBY 240 /*! The initial wait time (usec) before checking if RCOSC_LF is stable. */ #define PowerCC26XX_INITIALWAITRCOSC_LF 1000 /*! The retry wait time (usec) when checking to see if RCOSC_LF is stable. */ -#define PowerCC26XX_RETRYWAITRCOSC_LF 1000 +#define PowerCC26XX_RETRYWAITRCOSC_LF 1000 /*! The initial wait time (usec) before checking if XOSC_HF is stable. */ -#define PowerCC26XX_INITIALWAITXOSC_HF 50 +#define PowerCC26XX_INITIALWAITXOSC_HF 50 /*! The retry wait time (usec) when checking to see if XOSC_HF is stable. */ -#define PowerCC26XX_RETRYWAITXOSC_HF 50 +#define PowerCC26XX_RETRYWAITXOSC_HF 50 /*! The initial wait time (usec) before checking if XOSC_LF is stable. */ -#define PowerCC26XX_INITIALWAITXOSC_LF 10000 +#define PowerCC26XX_INITIALWAITXOSC_LF 10000 /*! The retry wait time (usec) when checking to see if XOSC_LF is stable. */ -#define PowerCC26XX_RETRYWAITXOSC_LF 5000 +#define PowerCC26XX_RETRYWAITXOSC_LF 5000 /* resource IDs */ -#define PowerCC26XX_PERIPH_GPT0 0 +#define PowerCC26XX_PERIPH_GPT0 0 /*!< Resource ID: General Purpose Timer 0 */ -#define PowerCC26XX_PERIPH_GPT1 1 +#define PowerCC26XX_PERIPH_GPT1 1 /*!< Resource ID: General Purpose Timer 1 */ -#define PowerCC26XX_PERIPH_GPT2 2 +#define PowerCC26XX_PERIPH_GPT2 2 /*!< Resource ID: General Purpose Timer 2 */ -#define PowerCC26XX_PERIPH_GPT3 3 +#define PowerCC26XX_PERIPH_GPT3 3 /*!< Resource ID: General Purpose Timer 3 */ -#define PowerCC26XX_PERIPH_SSI0 4 +#define PowerCC26XX_PERIPH_SSI0 4 /*!< Resource ID: Synchronous Serial Interface 0 */ -#define PowerCC26XX_PERIPH_SSI1 5 +#define PowerCC26XX_PERIPH_SSI1 5 /*!< Resource ID: Synchronous Serial Interface 1 */ -#define PowerCC26XX_PERIPH_UART0 6 /*!< Resource ID: UART 0 */ +#define PowerCC26XX_PERIPH_UART0 6 /*!< Resource ID: UART 0 */ -#define PowerCC26XX_PERIPH_I2C0 7 /*!< Resource ID: I2C 0 */ +#define PowerCC26XX_PERIPH_I2C0 7 /*!< Resource ID: I2C 0 */ -#define PowerCC26XX_PERIPH_TRNG 8 +#define PowerCC26XX_PERIPH_TRNG 8 /*!< Resource ID: True Random Number Generator */ -#define PowerCC26XX_PERIPH_GPIO 9 /*!< Resource ID: General Purpose I/Os */ +#define PowerCC26XX_PERIPH_GPIO 9 /*!< Resource ID: General Purpose I/Os */ -#define PowerCC26XX_PERIPH_UDMA 10 /*!< Resource ID: uDMA Controller */ +#define PowerCC26XX_PERIPH_UDMA 10 /*!< Resource ID: uDMA Controller */ -#define PowerCC26XX_PERIPH_CRYPTO 11 /*!< Resource ID: AES Security Module */ +#define PowerCC26XX_PERIPH_CRYPTO 11 /*!< Resource ID: AES Security Module */ -#define PowerCC26XX_PERIPH_I2S 12 /*!< Resource ID: I2S */ +#define PowerCC26XX_PERIPH_I2S 12 /*!< Resource ID: I2S */ -#define PowerCC26XX_PERIPH_RFCORE 13 /*!< Resource ID: RF Core Module */ +#define PowerCC26XX_PERIPH_RFCORE 13 /*!< Resource ID: RF Core Module */ -#define PowerCC26XX_XOSC_HF 14 +#define PowerCC26XX_XOSC_HF 14 /*!< Resource ID: High Frequency Crystal Oscillator */ -#define PowerCC26XX_DOMAIN_PERIPH 15 +#define PowerCC26XX_DOMAIN_PERIPH 15 /*!< Resource ID: Peripheral Power Domain */ -#define PowerCC26XX_DOMAIN_SERIAL 16 +#define PowerCC26XX_DOMAIN_SERIAL 16 /*!< Resource ID: Serial Power Domain */ -#define PowerCC26XX_DOMAIN_RFCORE 17 +#define PowerCC26XX_DOMAIN_RFCORE 17 /*!< Resource ID: RF Core Power Domain */ -#define PowerCC26XX_DOMAIN_SYSBUS 18 +#define PowerCC26XX_DOMAIN_SYSBUS 18 /*!< Resource ID: System Bus Power Domain */ /* \cond */ -#define PowerCC26XX_NUMRESOURCES 19 /* Number of resources in database */ +#define PowerCC26XX_NUMRESOURCES 19 /* Number of resources in database */ /* \endcond */ /* \cond */ /* resource record bitmasks */ -#define PowerCC26XX_PERIPH 0x80 /* resource is a peripheral */ -#define PowerCC26XX_SPECIAL 0x40 /* resource requires special handler */ -#define PowerCC26XX_DOMAIN 0x00 /* resource is a domain */ -#define PowerCC26XX_PARENTMASK 0x3F /* parent resource mask */ -#define PowerCC26XX_NOPARENT 0x3F /* if resource has no parent */ +#define PowerCC26XX_PERIPH 0x80 /* resource is a peripheral */ +#define PowerCC26XX_SPECIAL 0x40 /* resource requires special handler */ +#define PowerCC26XX_DOMAIN 0x00 /* resource is a domain */ +#define PowerCC26XX_PARENTMASK 0x3F /* parent resource mask */ +#define PowerCC26XX_NOPARENT 0x3F /* if resource has no parent */ /* \endcond */ -#define PowerCC26XX_STANDBY 0x1 /*!< The STANDBY sleep state */ +#define PowerCC26XX_STANDBY 0x1 /*!< The STANDBY sleep state */ /* \cond */ /* internal flags for enabling/disabling resources */ -#define PowerCC26XX_ENABLE 1 -#define PowerCC26XX_DISABLE 0 +#define PowerCC26XX_ENABLE 1 +#define PowerCC26XX_DISABLE 0 /* \endcond */ /* constraints */ -#define PowerCC26XX_RETAIN_VIMS_CACHE_IN_STANDBY 0 +#define PowerCC26XX_RETAIN_VIMS_CACHE_IN_STANDBY 0 /*!< Constraint: VIMS RAM must be retained while in STANDBY */ -#define PowerCC26XX_DISALLOW_SHUTDOWN 1 +#define PowerCC26XX_DISALLOW_SHUTDOWN 1 /*!< Constraint: Disallow a transition to the SHUTDOWN state */ -#define PowerCC26XX_DISALLOW_STANDBY 2 +#define PowerCC26XX_DISALLOW_STANDBY 2 /*!< Constraint: Disallow a transition to the STANDBY sleep state */ -#define PowerCC26XX_DISALLOW_IDLE 3 +#define PowerCC26XX_DISALLOW_IDLE 3 /*!< Constraint: Disallow a transition to the IDLE sleep state */ -#define PowerCC26XX_NEED_FLASH_IN_IDLE 4 +#define PowerCC26XX_NEED_FLASH_IN_IDLE 4 /*!< Constraint: Flash memory needs to enabled during IDLE */ #define PowerCC26XX_SWITCH_XOSC_HF_MANUALLY 5 @@ -201,14 +201,14 @@ typedef uint8_t PowerCC26XX_Resource; /* Resource identifier */ */ /* \cond */ -#define PowerCC26XX_NUMCONSTRAINTS 7 /* Number of constraints supported */ +#define PowerCC26XX_NUMCONSTRAINTS 7 /* Number of constraints supported */ /* \endcond */ /* \cond */ /* Deprecated constraint names */ -#define PowerCC26XX_SD_DISALLOW PowerCC26XX_DISALLOW_SHUTDOWN -#define PowerCC26XX_SB_DISALLOW PowerCC26XX_DISALLOW_STANDBY -#define PowerCC26XX_IDLE_PD_DISALLOW PowerCC26XX_DISALLOW_IDLE +#define PowerCC26XX_SD_DISALLOW PowerCC26XX_DISALLOW_SHUTDOWN +#define PowerCC26XX_SB_DISALLOW PowerCC26XX_DISALLOW_STANDBY +#define PowerCC26XX_IDLE_PD_DISALLOW PowerCC26XX_DISALLOW_IDLE #define PowerCC26XX_XOSC_HF_SWITCHING_DISALLOW PowerCC26XX_DISALLOW_XOSC_HF_SWITCHING #define PowerCC26XX_SB_VIMS_CACHE_RETAIN PowerCC26XX_RETAIN_VIMS_CACHE_IN_STANDBY /* \endcond */ @@ -219,22 +219,22 @@ typedef uint8_t PowerCC26XX_Resource; /* Resource identifier */ * Each event must be a power of two and must be sequential * without any gaps. */ -#define PowerCC26XX_ENTERING_STANDBY 0x1 +#define PowerCC26XX_ENTERING_STANDBY 0x1 /*!< Power event: The device is entering the STANDBY sleep state */ -#define PowerCC26XX_ENTERING_SHUTDOWN 0x2 +#define PowerCC26XX_ENTERING_SHUTDOWN 0x2 /*!< Power event: The device is entering the SHUTDOWN state */ -#define PowerCC26XX_AWAKE_STANDBY 0x4 +#define PowerCC26XX_AWAKE_STANDBY 0x4 /*!< Power event: The device is waking up from the STANDBY sleep state */ -#define PowerCC26XX_AWAKE_STANDBY_LATE 0x8 +#define PowerCC26XX_AWAKE_STANDBY_LATE 0x8 /*!< Power event: The device is waking up from STANDBY (this event is sent later during wakeup, after interrupts are re-enabled) */ -#define PowerCC26XX_XOSC_HF_SWITCHED 0x10 +#define PowerCC26XX_XOSC_HF_SWITCHED 0x10 /*!< Power event: The high frequency (HF) clock source has been switched to XOSC_HF */ -#define PowerCC26XX_JTAG_PD_TURNED_ON 0x20 +#define PowerCC26XX_JTAG_PD_TURNED_ON 0x20 /*!< \warning Note that this power event is only supported by the CC2640R2 device! * * The JTAG subsystem on the CC26xx devices is automatically enabled after receiving @@ -303,161 +303,160 @@ typedef uint8_t PowerCC26XX_Resource; /* Resource identifier */ * @endcode */ - /* \cond */ -#define PowerCC26XX_NUMEVENTS 6 /* Number of events supported */ +#define PowerCC26XX_NUMEVENTS 6 /* Number of events supported */ /* \endcond */ /* \cond */ /* * Calibration stages */ -#define PowerCC26XX_SETUP_CALIBRATE 1 -#define PowerCC26XX_INITIATE_CALIBRATE 2 -#define PowerCC26XX_DO_CALIBRATE 3 +#define PowerCC26XX_SETUP_CALIBRATE 1 +#define PowerCC26XX_INITIATE_CALIBRATE 2 +#define PowerCC26XX_DO_CALIBRATE 3 /* \endcond */ /* \cond */ /*! @brief Power resource database record format */ typedef struct PowerCC26XX_ResourceRecord { - uint8_t flags; /* resource type | first parent */ - uint16_t driverlibID; /* corresponding driverlib ID for this resource */ + uint8_t flags; /* resource type | first parent */ + uint16_t driverlibID; /* corresponding driverlib ID for this resource */ } PowerCC26XX_ResourceRecord; /* \endcond */ /*! @brief Global configuration structure */ typedef struct PowerCC26XX_Config { - /*! - * @brief The Power Policy's initialization function - * - * If the policy does not have an initialization function, 'NULL' - * should be specified. - */ - Power_PolicyInitFxn policyInitFxn; - /*! - * @brief The Power Policy function - * - * When enabled, this function is invoked in the idle loop, to - * opportunistically select and activate sleep states. - * - * Two reference policies are provided: - * - * PowerCC26XX_doWFI() - a simple policy that invokes CPU wait for - * interrupt (WFI) - * - * PowerCC26XX_standbyPolicy() - an agressive policy that considers - * constraints, time until next scheduled work, and sleep state - * latencies, and optionally puts the device into the STANDBY state, - * the IDLE state, or as a minimum, WFI. - * - * Custom policies can be written, and specified via this function pointer. - * - * In addition to this static selection, the Power Policy can be - * dynamically changed at runtime, via the Power_setPolicy() API. - */ - Power_PolicyFxn policyFxn; - /*! - * @brief The function to be used for activating RC Oscillator (RCOSC) - * calibration - * - * Calibration is normally enabled, via specification of the function - * PowerCC26XX_calibrate(). This enables high accuracy operation, and - * faster high frequency crystal oscillator (XOSC_HF) startups. - * - * To disable RCOSC calibration, the function PowerCC26XX_noCalibrate() - * should be specified. - */ - bool (*calibrateFxn)(unsigned int); - /*! - * @brief Time in system ticks that specifies the maximum duration the device - * may spend in standby. - * - * When the power driver tries to put the device into standby and determines - * the next wakeup should usually be further into the future than - * maxStandbyDuration system ticks, the power driver will schedule a wakeup - * maxStandbyDuration into the future. When the device wakes up after - * being in standby for maxStandbyDuration ticks, the power driver will - * repeat this process and go back into standby if the state of the system - * allows it. - * - * Inserting such periodic wakeups can be used to automatically calibrate - * the RCOSC with a maximum period between calibrations or to force the - * recalculation of the initial VDDR recharge period. This assumes that - * the constraint to prohibit standby is not set and that periods of - * inactivity are long enough for the power driver to put the device - * into standby. - * - * The value 0 is invalid. When PowerCC26XX_Config.enableMaxStandbyDuration is - * set to false, any value (including 0) is ignored and the feature is - * disabled. - * This feature should not be used to disallow entering standby; - * the PowerCC26XX_DISALLOW_STANDBY constraint should be used for - * this purpose. - */ - uint32_t maxStandbyDuration; - /*! - * @brief Margin in SCLK_LF periods subtracted from previous longest - * VDDR recharge period. - * - * As the device comes out of standby, it updated its previous initial - * VDDR recharge period to be closer to the longest recharge period - * experienced during the time spent in standby before waking up. - * - * vddrRechargeMargin is subtracted from the longest VDDR recharge - * period in SysCtrlAdjustRechargeAfterPowerDown to ensure there is - * some margin between the new initial and converged VDDR recharge - * period. The converged recharge period at a certain temperature - * is board and device dependent. - * - * The default value of 0 disables this feature. - */ - uint16_t vddrRechargeMargin; - /*! - * @brief Boolean that enables limiting the duration spent in standby - * - * If false, the power driver will put the device into standby as - * appropriate without duration restrictions. - * - * If true, the the power driver will force a wakeup every - * PowerCC26XX_Config.maxStandbyDuration system ticks before reevaluating - * the state of the system. - * - * This is set to false by default. - */ - bool enableMaxStandbyDuration; - /*! - * @brief Boolean specifying if the Power Policy function is enabled - * - * If 'true', the policy function will be invoked once for each pass - * of the idle loop. - * - * If 'false', the policy will not be invoked. - * - * In addition to this static setting, the power policy can be dynamically - * enabled and disabled at runtime, via the Power_enablePolicy() and - * Power_disablePolicy() functions, respectively. - */ - bool enablePolicy; - /*! - * @brief Boolean specifying whether the low frequency RC oscillator - * (RCOSC_LF) should be calibrated. - * - * If RCOSC calibration is enabled (above, via specification of - * an appropriate calibrateFxn), this Boolean specifies whether - * RCOSC_LF should be calibrated. - */ - bool calibrateRCOSC_LF; - /*! - * @brief Boolean specifying whether the high frequency RC oscillator - * (RCOSC_HF) should be calibrated. - * - * If RCOSC calibration is enabled (above, via specification of - * an appropriate calibrateFxn), this Boolean specifies whether - * RCOSC_HF should be calibrated. - */ - bool calibrateRCOSC_HF; + /*! + * @brief The Power Policy's initialization function + * + * If the policy does not have an initialization function, 'NULL' + * should be specified. + */ + Power_PolicyInitFxn policyInitFxn; + /*! + * @brief The Power Policy function + * + * When enabled, this function is invoked in the idle loop, to + * opportunistically select and activate sleep states. + * + * Two reference policies are provided: + * + * PowerCC26XX_doWFI() - a simple policy that invokes CPU wait for + * interrupt (WFI) + * + * PowerCC26XX_standbyPolicy() - an agressive policy that considers + * constraints, time until next scheduled work, and sleep state + * latencies, and optionally puts the device into the STANDBY state, + * the IDLE state, or as a minimum, WFI. + * + * Custom policies can be written, and specified via this function pointer. + * + * In addition to this static selection, the Power Policy can be + * dynamically changed at runtime, via the Power_setPolicy() API. + */ + Power_PolicyFxn policyFxn; + /*! + * @brief The function to be used for activating RC Oscillator (RCOSC) + * calibration + * + * Calibration is normally enabled, via specification of the function + * PowerCC26XX_calibrate(). This enables high accuracy operation, and + * faster high frequency crystal oscillator (XOSC_HF) startups. + * + * To disable RCOSC calibration, the function PowerCC26XX_noCalibrate() + * should be specified. + */ + bool (*calibrateFxn)(unsigned int); + /*! + * @brief Time in system ticks that specifies the maximum duration the device + * may spend in standby. + * + * When the power driver tries to put the device into standby and determines + * the next wakeup should usually be further into the future than + * maxStandbyDuration system ticks, the power driver will schedule a wakeup + * maxStandbyDuration into the future. When the device wakes up after + * being in standby for maxStandbyDuration ticks, the power driver will + * repeat this process and go back into standby if the state of the system + * allows it. + * + * Inserting such periodic wakeups can be used to automatically calibrate + * the RCOSC with a maximum period between calibrations or to force the + * recalculation of the initial VDDR recharge period. This assumes that + * the constraint to prohibit standby is not set and that periods of + * inactivity are long enough for the power driver to put the device + * into standby. + * + * The value 0 is invalid. When PowerCC26XX_Config.enableMaxStandbyDuration is + * set to false, any value (including 0) is ignored and the feature is + * disabled. + * This feature should not be used to disallow entering standby; + * the PowerCC26XX_DISALLOW_STANDBY constraint should be used for + * this purpose. + */ + uint32_t maxStandbyDuration; + /*! + * @brief Margin in SCLK_LF periods subtracted from previous longest + * VDDR recharge period. + * + * As the device comes out of standby, it updated its previous initial + * VDDR recharge period to be closer to the longest recharge period + * experienced during the time spent in standby before waking up. + * + * vddrRechargeMargin is subtracted from the longest VDDR recharge + * period in SysCtrlAdjustRechargeAfterPowerDown to ensure there is + * some margin between the new initial and converged VDDR recharge + * period. The converged recharge period at a certain temperature + * is board and device dependent. + * + * The default value of 0 disables this feature. + */ + uint16_t vddrRechargeMargin; + /*! + * @brief Boolean that enables limiting the duration spent in standby + * + * If false, the power driver will put the device into standby as + * appropriate without duration restrictions. + * + * If true, the the power driver will force a wakeup every + * PowerCC26XX_Config.maxStandbyDuration system ticks before reevaluating + * the state of the system. + * + * This is set to false by default. + */ + bool enableMaxStandbyDuration; + /*! + * @brief Boolean specifying if the Power Policy function is enabled + * + * If 'true', the policy function will be invoked once for each pass + * of the idle loop. + * + * If 'false', the policy will not be invoked. + * + * In addition to this static setting, the power policy can be dynamically + * enabled and disabled at runtime, via the Power_enablePolicy() and + * Power_disablePolicy() functions, respectively. + */ + bool enablePolicy; + /*! + * @brief Boolean specifying whether the low frequency RC oscillator + * (RCOSC_LF) should be calibrated. + * + * If RCOSC calibration is enabled (above, via specification of + * an appropriate calibrateFxn), this Boolean specifies whether + * RCOSC_LF should be calibrated. + */ + bool calibrateRCOSC_LF; + /*! + * @brief Boolean specifying whether the high frequency RC oscillator + * (RCOSC_HF) should be calibrated. + * + * If RCOSC calibration is enabled (above, via specification of + * an appropriate calibrateFxn), this Boolean specifies whether + * RCOSC_HF should be calibrated. + */ + bool calibrateRCOSC_HF; } PowerCC26XX_Config; /*! @@ -468,41 +467,41 @@ typedef struct PowerCC26XX_Config */ typedef struct PowerCC26XX_ModuleState { - List_List notifyList; /*!< Event notification list */ - uint32_t constraintMask; /*!< Aggregate constraints mask */ - ClockP_Struct clockObj; /*!< Clock object for scheduling wakeups */ - ClockP_Struct xoscClockObj; /*!< Clock object for XOSC_HF switching */ - ClockP_Struct lfClockObj; /*!< Clock object for LF clock checking */ - ClockP_Struct calClockStruct; /*!< Clock object for RCOSC calibration */ - HwiP_Struct hwiStruct; /*!< Hwi object for RCOSC calibration */ - int32_t nDeltaFreqCurr; /*!< RCOSC calibration variable */ - int32_t nCtrimCurr; /*!< RCOSC calibration variable */ - int32_t nCtrimFractCurr; /*!< RCOSC calibration variable */ - int32_t nCtrimNew; /*!< RCOSC calibration variable */ - int32_t nCtrimFractNew; /*!< RCOSC calibration variable */ - int32_t nRtrimNew; /*!< RCOSC calibration variable */ - int32_t nRtrimCurr; /*!< RCOSC calibration variable */ - int32_t nDeltaFreqNew; /*!< RCOSC calibration variable */ - bool bRefine; /*!< RCOSC calibration variable */ - uint32_t state; /*!< Current transition state */ - bool xoscPending; /*!< Is XOSC_HF activation in progress? */ - bool calLF; /*!< Calibrate RCOSC_LF? */ - uint8_t hwiState; /*!< The AUX ISR calibration state */ - bool busyCal; /*!< Already busy calibrating? */ - uint8_t calStep; /*!< The current calibration step */ - bool firstLF; /*!< Is this the first LF calibration? */ - bool enablePolicy; /*!< Is the Power policy enabled? */ - bool initialized; /*!< Has Power_init() been called? */ + List_List notifyList; /*!< Event notification list */ + uint32_t constraintMask; /*!< Aggregate constraints mask */ + ClockP_Struct clockObj; /*!< Clock object for scheduling wakeups */ + ClockP_Struct xoscClockObj; /*!< Clock object for XOSC_HF switching */ + ClockP_Struct lfClockObj; /*!< Clock object for LF clock checking */ + ClockP_Struct calClockStruct; /*!< Clock object for RCOSC calibration */ + HwiP_Struct hwiStruct; /*!< Hwi object for RCOSC calibration */ + int32_t nDeltaFreqCurr; /*!< RCOSC calibration variable */ + int32_t nCtrimCurr; /*!< RCOSC calibration variable */ + int32_t nCtrimFractCurr; /*!< RCOSC calibration variable */ + int32_t nCtrimNew; /*!< RCOSC calibration variable */ + int32_t nCtrimFractNew; /*!< RCOSC calibration variable */ + int32_t nRtrimNew; /*!< RCOSC calibration variable */ + int32_t nRtrimCurr; /*!< RCOSC calibration variable */ + int32_t nDeltaFreqNew; /*!< RCOSC calibration variable */ + bool bRefine; /*!< RCOSC calibration variable */ + uint32_t state; /*!< Current transition state */ + bool xoscPending; /*!< Is XOSC_HF activation in progress? */ + bool calLF; /*!< Calibrate RCOSC_LF? */ + uint8_t hwiState; /*!< The AUX ISR calibration state */ + bool busyCal; /*!< Already busy calibrating? */ + uint8_t calStep; /*!< The current calibration step */ + bool firstLF; /*!< Is this the first LF calibration? */ + bool enablePolicy; /*!< Is the Power policy enabled? */ + bool initialized; /*!< Has Power_init() been called? */ #if defined(DeviceFamily_CC26X0R2) - bool emulatorAttached; /*!< Was an emulator detected during boot? */ + bool emulatorAttached; /*!< Was an emulator detected during boot? */ #endif - uint8_t constraintCounts[PowerCC26XX_NUMCONSTRAINTS]; - /*!< Array to maintain constraint reference counts */ - uint8_t resourceCounts[PowerCC26XX_NUMRESOURCES]; - /*!< Array to maintain resource dependency reference counts */ - unsigned int (*resourceHandlers[3])(unsigned int); - /*!< Array of special dependency handler functions */ - Power_PolicyFxn policyFxn; /*!< The Power policy function */ + uint8_t constraintCounts[PowerCC26XX_NUMCONSTRAINTS]; + /*!< Array to maintain constraint reference counts */ + uint8_t resourceCounts[PowerCC26XX_NUMRESOURCES]; + /*!< Array to maintain resource dependency reference counts */ + unsigned int (*resourceHandlers[3])(unsigned int); + /*!< Array of special dependency handler functions */ + Power_PolicyFxn policyFxn; /*!< The Power policy function */ } PowerCC26XX_ModuleState; /*! @@ -643,8 +642,8 @@ void PowerCC26XX_standbyPolicy(void); void PowerCC26XX_schedulerDisable(void); void PowerCC26XX_schedulerRestore(void); -#define Power_getPerformanceLevel(void) 0 -#define Power_setPerformanceLevel(level) Power_EFAIL +#define Power_getPerformanceLevel(void) 0 +#define Power_setPerformanceLevel(level) Power_EFAIL #ifdef __cplusplus } diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/pwm/PWMTimerCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/pwm/PWMTimerCC26XX.h index 08b74e9..07e1089 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/pwm/PWMTimerCC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/pwm/PWMTimerCC26XX.h @@ -132,29 +132,28 @@ extern "C" { #endif -#include #include +#include #include #include #include - /*! * @name PWMTimerCC26XX specific control commands and arguments * @{ -*/ + */ /*! Timer debug stall mode (stop PWM output debugger halts CPU) When enabled, PWM output will be HIGH when CPU is halted */ -#define PWMTimerCC26XX_CMD_DEBUG_STALL PWM_CMD_RESERVED + 0 /*!< @hideinitializer */ +#define PWMTimerCC26XX_CMD_DEBUG_STALL PWM_CMD_RESERVED + 0 /*!< @hideinitializer */ /*! * @name Arguments for PWMTimerCC26XX_CMD_DEBUG_STALL * @{ */ -#define CMD_ARG_DEBUG_STALL_OFF (uint32_t)GPTimerCC26XX_DEBUG_STALL_OFF /*!< @hideinitializer */ -#define CMD_ARG_DEBUG_STALL_ON (uint32_t)GPTimerCC26XX_DEBUG_STALL_ON /*!< @hideinitializer */ +#define CMD_ARG_DEBUG_STALL_OFF (uint32_t) GPTimerCC26XX_DEBUG_STALL_OFF /*!< @hideinitializer */ +#define CMD_ARG_DEBUG_STALL_ON (uint32_t) GPTimerCC26XX_DEBUG_STALL_ON /*!< @hideinitializer */ /* @} */ /* @} */ @@ -184,8 +183,8 @@ extern const PWM_FxnTable PWMTimerCC26XX_fxnTable; */ typedef struct PWMTimerCC26XX_HwAttrs { - PIN_Id pwmPin; /*!< PIN to output PWM signal on */ - uint8_t gpTimerUnit; /*!< GPTimer unit index (0A, 0B, 1A..) */ + PIN_Id pwmPin; /*!< PIN to output PWM signal on */ + uint8_t gpTimerUnit; /*!< GPTimer unit index (0A, 0B, 1A..) */ } PWMTimerCC26XX_HwAttrs; /*! @@ -204,16 +203,16 @@ typedef struct PWMTimerCC26XX_HwAttrs */ typedef struct PWMTimerCC26XX_Object { - bool isOpen; /*!< open flag used to check if PWM is opened */ - bool isRunning; /*!< running flag, set if the output is active */ - PWM_Period_Units periodUnit; /*!< Current period unit */ - uint32_t periodValue; /*!< Current period value in unit */ - uint32_t periodCounts; /*!< Current period in raw timer counts */ - PWM_Duty_Units dutyUnit; /*!< Current duty cycle unit */ - uint32_t dutyValue; /*!< Current duty cycle value in unit */ - uint32_t dutyCounts; /*!< Current duty in raw timer counts */ - PWM_IdleLevel idleLevel; /*!< PWM idle level when stopped / not started */ - GPTimerCC26XX_Handle hTimer; /*!< Handle to underlying GPTimer peripheral */ + bool isOpen; /*!< open flag used to check if PWM is opened */ + bool isRunning; /*!< running flag, set if the output is active */ + PWM_Period_Units periodUnit; /*!< Current period unit */ + uint32_t periodValue; /*!< Current period value in unit */ + uint32_t periodCounts; /*!< Current period in raw timer counts */ + PWM_Duty_Units dutyUnit; /*!< Current duty cycle unit */ + uint32_t dutyValue; /*!< Current duty cycle value in unit */ + uint32_t dutyCounts; /*!< Current duty in raw timer counts */ + PWM_IdleLevel idleLevel; /*!< PWM idle level when stopped / not started */ + GPTimerCC26XX_Handle hTimer; /*!< Handle to underlying GPTimer peripheral */ } PWMTimerCC26XX_Object; #ifdef __cplusplus diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/RF.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/RF.h index 63ecc3d..ce3a13a 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/RF.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/rf/RF.h @@ -664,17 +664,17 @@ assert (rssi != RF_GET_RSSI_ERROR_VAL); // Could not read the RSSI extern "C" { #endif -#include #include +#include #include #include #include #include -#include DeviceFamily_constructPath(driverlib/rf_common_cmd.h) -#include DeviceFamily_constructPath(driverlib/rf_prop_cmd.h) -#include DeviceFamily_constructPath(driverlib/rf_ble_cmd.h) +#include DeviceFamily_constructPath(driverlib / rf_common_cmd.h) +#include DeviceFamily_constructPath(driverlib / rf_prop_cmd.h) +#include DeviceFamily_constructPath(driverlib / rf_ble_cmd.h) /** * @name RF Core Events @@ -687,34 +687,34 @@ extern "C" { * @sa RF_postCmd(), RF_pendCmd(), RF_runCmd() * @{ */ -#define RF_EventCmdDone (1 << 0) ///< A radio operation command in a chain finished. -#define RF_EventLastCmdDone (1 << 1) ///< A stand-alone radio operation command or the last radio operation command in a chain finished. -#define RF_EventFGCmdDone (1 << 2) ///< A IEEE-mode radio operation command in a chain finished. -#define RF_EventLastFGCmdDone (1 << 3) ///< A stand-alone IEEE-mode radio operation command or the last command in a chain finished. -#define RF_EventTxDone (1 << 4) ///< Packet transmitted -#define RF_EventTXAck (1 << 5) ///< ACK packet transmitted -#define RF_EventTxCtrl (1 << 6) ///< Control packet transmitted -#define RF_EventTxCtrlAck (1 << 7) ///< Acknowledgement received on a transmitted control packet -#define RF_EventTxCtrlAckAck (1 << 8) ///< Acknowledgement received on a transmitted control packet, and acknowledgement transmitted for that packet -#define RF_EventTxRetrans (1 << 9) ///< Packet retransmitted -#define RF_EventTxEntryDone (1 << 10) ///< Tx queue data entry state changed to Finished -#define RF_EventTxBufferChange (1 << 11) ///< A buffer change is complete -#define RF_EventPaChanged (1 << 14) ///< The PA was reconfigured on the fly. -#define RF_EventRxOk (1 << 16) ///< Packet received with CRC OK, payload, and not to be ignored -#define RF_EventRxNOk (1 << 17) ///< Packet received with CRC error -#define RF_EventRxIgnored (1 << 18) ///< Packet received with CRC OK, but to be ignored -#define RF_EventRxEmpty (1 << 19) ///< Packet received with CRC OK, not to be ignored, no payload -#define RF_EventRxCtrl (1 << 20) ///< Control packet received with CRC OK, not to be ignored -#define RF_EventRxCtrlAck (1 << 21) ///< Control packet received with CRC OK, not to be ignored, then ACK sent -#define RF_EventRxBufFull (1 << 22) ///< Packet received that did not fit in the Rx queue -#define RF_EventRxEntryDone (1 << 23) ///< Rx queue data entry changing state to Finished -#define RF_EventDataWritten (1 << 24) ///< Data written to partial read Rx buffer -#define RF_EventNDataWritten (1 << 25) ///< Specified number of bytes written to partial read Rx buffer -#define RF_EventRxAborted (1 << 26) ///< Packet reception stopped before packet was done -#define RF_EventRxCollisionDetected (1 << 27) ///< A collision was indicated during packet reception -#define RF_EventModulesUnlocked (1 << 29) ///< As part of the boot process, the CM0 has opened access to RF core modules and memories -#define RF_EventInternalError (uint32_t)(1 << 31) ///< Internal error observed -#define RF_EventMdmSoft 0x0000002000000000 ///< Synchronization word detected (MDMSOFT interrupt flag) +#define RF_EventCmdDone (1 << 0) ///< A radio operation command in a chain finished. +#define RF_EventLastCmdDone (1 << 1) ///< A stand-alone radio operation command or the last radio operation command in a chain finished. +#define RF_EventFGCmdDone (1 << 2) ///< A IEEE-mode radio operation command in a chain finished. +#define RF_EventLastFGCmdDone (1 << 3) ///< A stand-alone IEEE-mode radio operation command or the last command in a chain finished. +#define RF_EventTxDone (1 << 4) ///< Packet transmitted +#define RF_EventTXAck (1 << 5) ///< ACK packet transmitted +#define RF_EventTxCtrl (1 << 6) ///< Control packet transmitted +#define RF_EventTxCtrlAck (1 << 7) ///< Acknowledgement received on a transmitted control packet +#define RF_EventTxCtrlAckAck (1 << 8) ///< Acknowledgement received on a transmitted control packet, and acknowledgement transmitted for that packet +#define RF_EventTxRetrans (1 << 9) ///< Packet retransmitted +#define RF_EventTxEntryDone (1 << 10) ///< Tx queue data entry state changed to Finished +#define RF_EventTxBufferChange (1 << 11) ///< A buffer change is complete +#define RF_EventPaChanged (1 << 14) ///< The PA was reconfigured on the fly. +#define RF_EventRxOk (1 << 16) ///< Packet received with CRC OK, payload, and not to be ignored +#define RF_EventRxNOk (1 << 17) ///< Packet received with CRC error +#define RF_EventRxIgnored (1 << 18) ///< Packet received with CRC OK, but to be ignored +#define RF_EventRxEmpty (1 << 19) ///< Packet received with CRC OK, not to be ignored, no payload +#define RF_EventRxCtrl (1 << 20) ///< Control packet received with CRC OK, not to be ignored +#define RF_EventRxCtrlAck (1 << 21) ///< Control packet received with CRC OK, not to be ignored, then ACK sent +#define RF_EventRxBufFull (1 << 22) ///< Packet received that did not fit in the Rx queue +#define RF_EventRxEntryDone (1 << 23) ///< Rx queue data entry changing state to Finished +#define RF_EventDataWritten (1 << 24) ///< Data written to partial read Rx buffer +#define RF_EventNDataWritten (1 << 25) ///< Specified number of bytes written to partial read Rx buffer +#define RF_EventRxAborted (1 << 26) ///< Packet reception stopped before packet was done +#define RF_EventRxCollisionDetected (1 << 27) ///< A collision was indicated during packet reception +#define RF_EventModulesUnlocked (1 << 29) ///< As part of the boot process, the CM0 has opened access to RF core modules and memories +#define RF_EventInternalError (uint32_t)(1 << 31) ///< Internal error observed +#define RF_EventMdmSoft 0x0000002000000000 ///< Synchronization word detected (MDMSOFT interrupt flag) /** @}*/ /** @@ -724,13 +724,13 @@ extern "C" { * Event flags generated by the RF Driver. * @{ */ -#define RF_EventCmdCancelled 0x1000000000000000 ///< Command canceled before it was started. -#define RF_EventCmdAborted 0x2000000000000000 ///< Abrupt command termination caused by RF_cancelCmd() or RF_flushCmd(). -#define RF_EventCmdStopped 0x4000000000000000 ///< Graceful command termination caused by RF_cancelCmd() or RF_flushCmd(). -#define RF_EventRatCh 0x0800000000000000 ///< A user-programmable RAT channel triggered an event. -#define RF_EventPowerUp 0x0400000000000000 ///< RF power up event. \deprecated This event is deprecated. Use #RF_ClientEventPowerUpFinished instead. -#define RF_EventError 0x0200000000000000 ///< Event flag used for error callback functions to indicate an error. See RF_Params::pErrCb. -#define RF_EventCmdPreempted 0x0100000000000000 ///< Command preempted by another command with higher priority. Applies only to multi-client applications. +#define RF_EventCmdCancelled 0x1000000000000000 ///< Command canceled before it was started. +#define RF_EventCmdAborted 0x2000000000000000 ///< Abrupt command termination caused by RF_cancelCmd() or RF_flushCmd(). +#define RF_EventCmdStopped 0x4000000000000000 ///< Graceful command termination caused by RF_cancelCmd() or RF_flushCmd(). +#define RF_EventRatCh 0x0800000000000000 ///< A user-programmable RAT channel triggered an event. +#define RF_EventPowerUp 0x0400000000000000 ///< RF power up event. \deprecated This event is deprecated. Use #RF_ClientEventPowerUpFinished instead. +#define RF_EventError 0x0200000000000000 ///< Event flag used for error callback functions to indicate an error. See RF_Params::pErrCb. +#define RF_EventCmdPreempted 0x0100000000000000 ///< Command preempted by another command with higher priority. Applies only to multi-client applications. /** @}*/ /** @@ -749,7 +749,7 @@ extern "C" { * command after a specified timeout period (in us) * With this control code @b arg is a pointer to the timeout variable and returns RF_StatSuccess. */ -#define RF_CTRL_SET_INACTIVITY_TIMEOUT 0 +#define RF_CTRL_SET_INACTIVITY_TIMEOUT 0 /*! * @brief Control code used by RF_control to update setup command * @@ -759,13 +759,13 @@ extern "C" { * setup command. Prior to updating the setup command, user should make sure all pending commands * have completed. */ -#define RF_CTRL_UPDATE_SETUP_CMD 1 +#define RF_CTRL_UPDATE_SETUP_CMD 1 /*! * @brief Control code used by RF_control to set powerup duration margin * * Setting this control updates the powerup duration margin. Default is RF_DEFAULT_POWER_UP_MARGIN. */ -#define RF_CTRL_SET_POWERUP_DURATION_MARGIN 2 +#define RF_CTRL_SET_POWERUP_DURATION_MARGIN 2 /*! * @brief Control code used by RF_control to set the phy switching margin * @@ -773,7 +773,7 @@ extern "C" { * run-time conflicts shall be evaluated in case of colliding radio operations issued from two * different clients. Default is RF_DEFAULT_PHY_SWITCHING_MARGIN. */ -#define RF_CTRL_SET_PHYSWITCHING_DURATION_MARGIN 3 +#define RF_CTRL_SET_PHYSWITCHING_DURATION_MARGIN 3 /*! * @brief Control code used by RF_control to set max error tolerance for RAT/RTC * @@ -781,7 +781,7 @@ extern "C" { * Default is RF_DEFAULT_RAT_RTC_ERR_TOL_IN_US (5 us) * Client is recommeneded to change this setting before sending any commands. */ -#define RF_CTRL_SET_RAT_RTC_ERR_TOL_VAL 4 +#define RF_CTRL_SET_RAT_RTC_ERR_TOL_VAL 4 /*! * @brief Control code used by RF_control to set power management * @@ -793,7 +793,7 @@ extern "C" { * This control is valid for dual-mode code only. Setting this control when using single-mode code has no effect * (power management always enabled). */ -#define RF_CTRL_SET_POWER_MGMT 5 +#define RF_CTRL_SET_POWER_MGMT 5 /*! * @brief Control code used by RF_control to set the hardware interrupt priority level of the RF driver. * @@ -815,7 +815,7 @@ extern "C" { * RF_control(rfHandle, RF_CTRL_SET_HWI_PRIORITY, &hwiPriority); * @endcode */ -#define RF_CTRL_SET_HWI_PRIORITY 6 +#define RF_CTRL_SET_HWI_PRIORITY 6 /*! * @brief Control code used by RF_control to set the software interrupt priority level of the RF driver. * @@ -837,7 +837,7 @@ extern "C" { * RF_control(rfHandle, RF_CTRL_SET_SWI_PRIORITY, &swiPriority); * @endcode */ -#define RF_CTRL_SET_SWI_PRIORITY 7 +#define RF_CTRL_SET_SWI_PRIORITY 7 /*! * @brief Control code used by RF_control to mask the available RAT channels manually. * @@ -847,7 +847,7 @@ extern "C" { * between the automatic channel allocation through #RF_ratCompare()/#RF_ratCapture() and the direct * configuration through #RF_postCmd(). */ -#define RF_CTRL_SET_AVAILABLE_RAT_CHANNELS_MASK 8 +#define RF_CTRL_SET_AVAILABLE_RAT_CHANNELS_MASK 8 /** @}*/ /** @@ -861,7 +861,7 @@ extern "C" { * * \sa #RF_TxPowerTable_findValue() */ -#define RF_TxPowerTable_MIN_DBM -128 +#define RF_TxPowerTable_MIN_DBM -128 /** * Refers to the the maximum available power in dBm when accessing a power @@ -869,14 +869,14 @@ extern "C" { * * \sa #RF_TxPowerTable_findValue() */ -#define RF_TxPowerTable_MAX_DBM 126 +#define RF_TxPowerTable_MAX_DBM 126 /** * Refers to an invalid power level in a TX power table. * * \sa #RF_TxPowerTable_findPowerLevel() */ -#define RF_TxPowerTable_INVALID_DBM 127 +#define RF_TxPowerTable_INVALID_DBM 127 /** * Refers to an invalid power value in a TX power table. @@ -912,8 +912,11 @@ extern "C" { * }; * @endcode */ -#define RF_TxPowerTable_TERMINATION_ENTRY \ - { .power = RF_TxPowerTable_INVALID_DBM, .value = { .rawValue = RF_TxPowerTable_INVALID_VALUE, .paType = RF_TxPowerTable_DefaultPA } } +#define RF_TxPowerTable_TERMINATION_ENTRY \ + { \ + .power = RF_TxPowerTable_INVALID_DBM, .value = {.rawValue = RF_TxPowerTable_INVALID_VALUE, \ + .paType = RF_TxPowerTable_DefaultPA } \ + } /** * Creates a TX power table entry for the default PA. @@ -921,8 +924,10 @@ extern "C" { * The values for \a bias, \a gain, \a boost and \a coefficient are usually measured by Texas Instruments * for a specific front-end configuration. They can then be obtained from SmartRFStudio. */ -#define RF_TxPowerTable_DEFAULT_PA_ENTRY(bias, gain, boost, coefficient) \ - { .rawValue = ((bias) << 0) | ((gain) << 6) | ((boost) << 8) | ((coefficient) << 9), .paType = RF_TxPowerTable_DefaultPA } +#define RF_TxPowerTable_DEFAULT_PA_ENTRY(bias, gain, boost, coefficient) \ + { \ + .rawValue = ((bias) << 0) | ((gain) << 6) | ((boost) << 8) | ((coefficient) << 9), .paType = RF_TxPowerTable_DefaultPA \ + } /** * Creates a TX power table entry for the High-power PA. @@ -930,9 +935,10 @@ extern "C" { * The values for \a bias, \a ibboost, \a boost, \a coefficient and \a ldoTrim are usually measured by Texas Instruments * for a specific front-end configuration. They can then be obtained from SmartRFStudio. */ -#define RF_TxPowerTable_HIGH_PA_ENTRY(bias, ibboost, boost, coefficient, ldotrim) \ - { .rawValue = ((bias) << 0) | ((ibboost) << 6) | ((boost) << 8) | ((coefficient) << 9) | ((ldotrim) << 16), .paType = RF_TxPowerTable_HighPA } - +#define RF_TxPowerTable_HIGH_PA_ENTRY(bias, ibboost, boost, coefficient, ldotrim) \ + { \ + .rawValue = ((bias) << 0) | ((ibboost) << 6) | ((boost) << 8) | ((coefficient) << 9) | ((ldotrim) << 16), .paType = RF_TxPowerTable_HighPA \ + } /** @} */ @@ -940,29 +946,29 @@ extern "C" { * @name Other defines * @{ */ -#define RF_GET_RSSI_ERROR_VAL (-128) ///< Error return value for RF_getRssi() -#define RF_CMDHANDLE_FLUSH_ALL (-1) ///< RF command handle to flush all RF commands -#define RF_ALLOC_ERROR (-2) ///< RF command or RAT channel allocation error -#define RF_SCHEDULE_CMD_ERROR (-3) ///< RF command schedule error -#define RF_ERROR_RAT_PROG (-255) ///< A rat channel could not be programmed. -#define RF_ERROR_INVALID_RFMODE (-256) ///< Invalid RF_Mode. Used in error callback. -#define RF_ERROR_CMDFS_SYNTH_PROG (-257) ///< Synthesizer error with CMD_FS. Used in error callback. If this error occurred in error callback, user needs to resend CMD_FS to recover. See the device's errata for more details. +#define RF_GET_RSSI_ERROR_VAL (-128) ///< Error return value for RF_getRssi() +#define RF_CMDHANDLE_FLUSH_ALL (-1) ///< RF command handle to flush all RF commands +#define RF_ALLOC_ERROR (-2) ///< RF command or RAT channel allocation error +#define RF_SCHEDULE_CMD_ERROR (-3) ///< RF command schedule error +#define RF_ERROR_RAT_PROG (-255) ///< A rat channel could not be programmed. +#define RF_ERROR_INVALID_RFMODE (-256) ///< Invalid RF_Mode. Used in error callback. +#define RF_ERROR_CMDFS_SYNTH_PROG (-257) ///< Synthesizer error with CMD_FS. Used in error callback. If this error occurred in error callback, user needs to resend CMD_FS to recover. See the device's errata for more details. -#define RF_NUM_SCHEDULE_ACCESS_ENTRIES 2 ///< Number of access request entries -#define RF_NUM_SCHEDULE_COMMAND_ENTRIES 8 ///< Number of scheduled command entries -#define RF_NUM_SCHEDULE_MAP_ENTRIES (RF_NUM_SCHEDULE_ACCESS_ENTRIES + RF_NUM_SCHEDULE_COMMAND_ENTRIES) ///< Number of schedule map entries. This is the sum of access request and scheduled command entries -#define RF_SCH_MAP_CURRENT_CMD_OFFSET RF_NUM_SCHEDULE_ACCESS_ENTRIES ///< Offset of the current command entry in the schedule map -#define RF_SCH_MAP_PENDING_CMD_OFFSET (RF_SCH_MAP_CURRENT_CMD_OFFSET + 2) ///< Offset of the first pending command entry in the schedule map +#define RF_NUM_SCHEDULE_ACCESS_ENTRIES 2 ///< Number of access request entries +#define RF_NUM_SCHEDULE_COMMAND_ENTRIES 8 ///< Number of scheduled command entries +#define RF_NUM_SCHEDULE_MAP_ENTRIES (RF_NUM_SCHEDULE_ACCESS_ENTRIES + RF_NUM_SCHEDULE_COMMAND_ENTRIES) ///< Number of schedule map entries. This is the sum of access request and scheduled command entries +#define RF_SCH_MAP_CURRENT_CMD_OFFSET RF_NUM_SCHEDULE_ACCESS_ENTRIES ///< Offset of the current command entry in the schedule map +#define RF_SCH_MAP_PENDING_CMD_OFFSET (RF_SCH_MAP_CURRENT_CMD_OFFSET + 2) ///< Offset of the first pending command entry in the schedule map -#define RF_ABORT_PREEMPTION (1<<2) ///< Used with RF_cancelCmd() to provoke subscription to RadioFreeCallback -#define RF_ABORT_GRACEFULLY (1<<0) ///< Used with RF_cancelCmd() for graceful command termination +#define RF_ABORT_PREEMPTION (1 << 2) ///< Used with RF_cancelCmd() to provoke subscription to RadioFreeCallback +#define RF_ABORT_GRACEFULLY (1 << 0) ///< Used with RF_cancelCmd() for graceful command termination -#define RF_SCH_CMD_EXECUTION_TIME_UNKNOWN 0 ///< For unknown execution time for RF scheduler +#define RF_SCH_CMD_EXECUTION_TIME_UNKNOWN 0 ///< For unknown execution time for RF scheduler -#define RF_RAT_ANY_CHANNEL (-1) ///< To be used within the channel configuration structure. Allocate any of the available channels. -#define RF_RAT_TICKS_PER_US 4 ///< Radio timer (RAT) ticks per microsecond. +#define RF_RAT_ANY_CHANNEL (-1) ///< To be used within the channel configuration structure. Allocate any of the available channels. +#define RF_RAT_TICKS_PER_US 4 ///< Radio timer (RAT) ticks per microsecond. -#define RF_LODIVIDER_MASK 0x7F ///< Mask to be used to determine the effective value of the setup command's loDivider field. +#define RF_LODIVIDER_MASK 0x7F ///< Mask to be used to determine the effective value of the setup command's loDivider field. /*! \brief Converts a duration given in \a microseconds into radio timer (RAT) ticks. @@ -988,10 +994,8 @@ extern "C" { #define RF_convertRatTicksToMs(ticks) \ ((ticks) / (1000 * (RF_RAT_TICKS_PER_US))) - /** @}*/ - /** * \brief PA configuration value for a certain power level. * @@ -1002,15 +1006,15 @@ extern "C" { */ typedef struct { - uint32_t rawValue: 22; ///< Hardware configuration value. - ///< - ///< - \c [15:0] used for default PA, - ///< - \c [21:0] used for High-power PA - uint32_t __dummy: 9; - uint32_t paType: 1; ///< Selects the PA type to be used. - ///< - ///< - 0: #RF_TxPowerTable_DefaultPA - ///< - 1: #RF_TxPowerTable_HighPA + uint32_t rawValue : 22; ///< Hardware configuration value. + ///< + ///< - \c [15:0] used for default PA, + ///< - \c [21:0] used for High-power PA + uint32_t __dummy : 9; + uint32_t paType : 1; ///< Selects the PA type to be used. + ///< + ///< - 0: #RF_TxPowerTable_DefaultPA + ///< - 1: #RF_TxPowerTable_HighPA } RF_TxPowerTable_Value; /** @@ -1033,13 +1037,12 @@ typedef struct */ typedef struct { - int8_t power; ///< Human readable power value representing - ///< the output in dBm. + int8_t power; ///< Human readable power value representing + ///< the output in dBm. - RF_TxPowerTable_Value value; ///< PA hardware configuration for that power level. + RF_TxPowerTable_Value value; ///< PA hardware configuration for that power level. } __attribute__((packed)) RF_TxPowerTable_Entry; - /** * \brief Selects a power amplifier path in a TX power value. * @@ -1052,7 +1055,6 @@ typedef enum RF_TxPowerTable_HighPA = 1, ///< High-power PA } RF_TxPowerTable_PAType; - /** @brief Base type for all radio operation commands. * * All radio operation commands share a common part. @@ -1068,7 +1070,6 @@ typedef enum */ typedef rfc_radioOp_t RF_Op; - /** @brief Specifies a RF core firmware configuration. * * %RF_Mode selects a mode of operation and points to firmware patches for the RF core. @@ -1079,10 +1080,10 @@ typedef rfc_radioOp_t RF_Op; */ typedef struct { - uint8_t rfMode; ///< Specifies which PHY modes should be activated. Must be set to RF_MODE_MULTIPLE for dual-mode operation. - void (*cpePatchFxn)(void); ///< Pointer to CPE patch function - void (*mcePatchFxn)(void); ///< Pointer to MCE patch function - void (*rfePatchFxn)(void); ///< Pointer to RFE patch function + uint8_t rfMode; ///< Specifies which PHY modes should be activated. Must be set to RF_MODE_MULTIPLE for dual-mode operation. + void (*cpePatchFxn)(void); ///< Pointer to CPE patch function + void (*mcePatchFxn)(void); ///< Pointer to MCE patch function + void (*rfePatchFxn)(void); ///< Pointer to RFE patch function } RF_Mode; /** @brief Scheduling priority of RF operation commands. @@ -1098,8 +1099,8 @@ typedef struct typedef enum { RF_PriorityHighest = 2, ///< Highest priority. Only use this for urgent commands. - RF_PriorityHigh = 1, ///< High priority. Use this for time-critical commands in synchronous protocols. - RF_PriorityNormal = 0, ///< Default priority. Use this in single-client applications. + RF_PriorityHigh = 1, ///< High priority. Use this for time-critical commands in synchronous protocols. + RF_PriorityNormal = 0, ///< Default priority. Use this in single-client applications. } RF_Priority; /** @brief Status codes for various RF driver functions. @@ -1117,7 +1118,7 @@ typedef enum RF_StatCmdDoneError, ///< Command finished with an error. RF_StatInvalidParamsError, ///< Function was called with an invalid parameter. RF_StatCmdEnded, ///< Cmd is found in the pool but was already ended. - RF_StatError = 0x80, ///< General error specifier. + RF_StatError = 0x80, ///< General error specifier. RF_StatCmdDoneSuccess, ///< Command finished with success. RF_StatCmdSch, ///< Command successfully scheduled for execution. RF_StatSuccess ///< Function finished with success. @@ -1140,18 +1141,18 @@ typedef uint64_t RF_EventMask; */ typedef union { - rfc_command_t commandId; ///< Generic command identifier. This is the first field - ///< in every radio operation command. - rfc_CMD_RADIO_SETUP_t common; ///< Radio setup command for BLE and IEEE modes - rfc_CMD_BLE5_RADIO_SETUP_t ble5; ///< Radio setup command for BLE5 mode - rfc_CMD_PROP_RADIO_SETUP_t prop; ///< Radio setup command for PROPRIETARY mode on 2.4 GHz - rfc_CMD_PROP_RADIO_DIV_SETUP_t prop_div; ///< Radio setup command for PROPRIETARY mode on Sub-1 Ghz + rfc_command_t commandId; ///< Generic command identifier. This is the first field + ///< in every radio operation command. + rfc_CMD_RADIO_SETUP_t common; ///< Radio setup command for BLE and IEEE modes + rfc_CMD_BLE5_RADIO_SETUP_t ble5; ///< Radio setup command for BLE5 mode + rfc_CMD_PROP_RADIO_SETUP_t prop; ///< Radio setup command for PROPRIETARY mode on 2.4 GHz + rfc_CMD_PROP_RADIO_DIV_SETUP_t prop_div; ///< Radio setup command for PROPRIETARY mode on Sub-1 Ghz #if (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2) - rfc_CMD_RADIO_SETUP_PA_t common_pa; ///< Radio setup command for BLE and IEEE modes with High Gain PA - rfc_CMD_BLE5_RADIO_SETUP_PA_t ble5_pa; ///< Radio setup command for BLE5 mode with High Gain PA - rfc_CMD_PROP_RADIO_SETUP_PA_t prop_pa; ///< Radio setup command for PROPRIETARY mode on 2.4 GHz with High Gain PA - rfc_CMD_PROP_RADIO_DIV_SETUP_PA_t prop_div_pa; ///< Radio setup command for PROPRIETARY mode on Sub-1 Ghz with High Gain PA + rfc_CMD_RADIO_SETUP_PA_t common_pa; ///< Radio setup command for BLE and IEEE modes with High Gain PA + rfc_CMD_BLE5_RADIO_SETUP_PA_t ble5_pa; ///< Radio setup command for BLE5 mode with High Gain PA + rfc_CMD_PROP_RADIO_SETUP_PA_t prop_pa; ///< Radio setup command for PROPRIETARY mode on 2.4 GHz with High Gain PA + rfc_CMD_PROP_RADIO_DIV_SETUP_PA_t prop_div_pa; ///< Radio setup command for PROPRIETARY mode on Sub-1 Ghz with High Gain PA #endif } RF_RadioSetup; @@ -1185,12 +1186,12 @@ typedef union */ typedef enum { - RF_ClientEventPowerUpFinished = (1 << 0), ///< The RF core has been powered up the radio setup has been finished. - RF_ClientEventRadioFree = (1 << 1), ///< Radio becomes free after a command has been preempted by a high-priority command of another client. + RF_ClientEventPowerUpFinished = (1 << 0), ///< The RF core has been powered up the radio setup has been finished. + RF_ClientEventRadioFree = (1 << 1), ///< Radio becomes free after a command has been preempted by a high-priority command of another client. ///< This event is only triggered on a client that has been preempted. ///< Clients may use this event to retry running their low-priority RF operation. - RF_ClientEventSwitchClientEntered = (1 << 2) ///< Signals the client that the RF driver is about to switch over from another client. + RF_ClientEventSwitchClientEntered = (1 << 2) ///< Signals the client that the RF driver is about to switch over from another client. } RF_ClientEvent; /** @brief Global RF driver events. @@ -1232,16 +1233,15 @@ typedef enum */ typedef enum { - RF_GlobalEventRadioSetup = (1 << 0), ///< The RF core is being reconfigured through a setup command. + RF_GlobalEventRadioSetup = (1 << 0), ///< The RF core is being reconfigured through a setup command. ///< The \a arg argument is a pointer to the setup command. ///< HWI context. - RF_GlobalEventRadioPowerDown = (1 << 1), ///< The RF core is being powered down. + RF_GlobalEventRadioPowerDown = (1 << 1), ///< The RF core is being powered down. ///< The \a arg argument is empty. ///< SWI context. } RF_GlobalEvent; - /** @brief Event mask for combining #RF_ClientEvent event flags in #RF_Params::nClientEventMask. * */ @@ -1283,13 +1283,12 @@ typedef int16_t RF_CmdHandle; * any field in %RF_Object is forbidden. */ - /** @cond */ -#if defined (RF_SINGLEMODE) -typedef struct RF_ObjectSingleMode RF_Object; +#if defined(RF_SINGLEMODE) +typedef struct RF_ObjectSingleMode RF_Object; #else -typedef struct RF_ObjectMultiMode RF_Object; +typedef struct RF_ObjectMultiMode RF_Object; #endif /* Definition of the RF_Object structure for single-mode applications. @@ -1297,32 +1296,32 @@ typedef struct RF_ObjectMultiMode RF_Object; */ struct RF_ObjectSingleMode { - /// Configuration - struct - { - uint32_t nInactivityTimeout; ///< Inactivity timeout in us. - RF_Mode* pRfMode; ///< Mode of operation. - RF_RadioSetup* pRadioSetup; ///< Pointer to the setup command to be executed at power up. - uint32_t nPowerUpDuration; ///< Radio power up time to be used to calculate future wake-up events. - bool bMeasurePowerUpDuration; ///< Indicates if nPowerUpDuration holds a fix value or being measured and updated at every power up. - bool bUpdateSetup; ///< Indicates if an analog configuration update should be performed at the next setup command execution. - uint16_t nPowerUpDurationMargin; ///< Power up duration margin in us. - void* pPowerCb; ///< \deprecated Power up callback, will go away in future versions, see clientConfig::pClienteventCb instead. - void* pErrCb; ///< Error callback. - } clientConfig; - /// State & variables - struct - { + /// Configuration struct { - rfc_CMD_FS_t cmdFs; ///< FS command to be executed when the radio is powered up. - } mode_state; ///< (Mode-specific) state structure - SemaphoreP_Struct semSync; ///< Semaphore used by RF_runCmd(), RF_pendCmd() and power down sequence. - RF_EventMask volatile eventSync; ///< Event mask/value used by RF_runCmd() and RF_pendCmd(). - void* pCbSync; ///< Internal storage of user callbacks when RF_runCmd() is used. - RF_EventMask unpendCause; ///< Internal storage of the return value of RF_pendCmd(). - bool bYielded; ///< Flag indicates that the radio can be powered down at the earliest convenience. - } state; + uint32_t nInactivityTimeout; ///< Inactivity timeout in us. + RF_Mode* pRfMode; ///< Mode of operation. + RF_RadioSetup* pRadioSetup; ///< Pointer to the setup command to be executed at power up. + uint32_t nPowerUpDuration; ///< Radio power up time to be used to calculate future wake-up events. + bool bMeasurePowerUpDuration; ///< Indicates if nPowerUpDuration holds a fix value or being measured and updated at every power up. + bool bUpdateSetup; ///< Indicates if an analog configuration update should be performed at the next setup command execution. + uint16_t nPowerUpDurationMargin; ///< Power up duration margin in us. + void* pPowerCb; ///< \deprecated Power up callback, will go away in future versions, see clientConfig::pClienteventCb instead. + void* pErrCb; ///< Error callback. + } clientConfig; + /// State & variables + struct + { + struct + { + rfc_CMD_FS_t cmdFs; ///< FS command to be executed when the radio is powered up. + } mode_state; ///< (Mode-specific) state structure + SemaphoreP_Struct semSync; ///< Semaphore used by RF_runCmd(), RF_pendCmd() and power down sequence. + RF_EventMask volatile eventSync; ///< Event mask/value used by RF_runCmd() and RF_pendCmd(). + void* pCbSync; ///< Internal storage of user callbacks when RF_runCmd() is used. + RF_EventMask unpendCause; ///< Internal storage of the return value of RF_pendCmd(). + bool bYielded; ///< Flag indicates that the radio can be powered down at the earliest convenience. + } state; }; /** Definition of the RF_Object structure for multi mode applications. @@ -1330,37 +1329,37 @@ struct RF_ObjectSingleMode */ struct RF_ObjectMultiMode { - /// Configuration - struct - { - uint32_t nInactivityTimeout; ///< Inactivity timeout in us. - RF_Mode* pRfMode; ///< Mode of operation. - RF_RadioSetup* pRadioSetup; ///< Pointer to the setup command to be executed at power up. - uint32_t nPhySwitchingDuration; ///< Radio reconfiguration time to this client's phy and protocol. - uint32_t nPowerUpDuration; ///< Radio power up time to be used to calculate future wake-up events. - bool bMeasurePowerUpDuration; ///< Indicates if nPowerUpDuration holds a fix value or being measured and updated at every power up. - bool bUpdateSetup; ///< Indicates if an analog configuration update should be performed at the next setup command execution. - uint16_t nPowerUpDurationMargin; ///< Power up duration margin in us. - void* pPowerCb; ///< \deprecated Power up callback, will go away in future versions, see clientConfig::pClienteventCb instead - void* pErrCb; ///< Error callback. - void* pClientEventCb; ///< Client event callback. - RF_ClientEventMask nClientEventMask; ///< Client event mask to activate client event callback. - uint16_t nPhySwitchingDurationMargin; ///< Phy switching duration margin in us. It is used to calculate when run-time conflicts shall be resolved. - } clientConfig; - /// State & variables - struct - { + /// Configuration struct { - rfc_CMD_FS_t cmdFs; ///< FS command to be executed when the radio is powered up. - } mode_state; ///< (Mode-specific) state structure - SemaphoreP_Struct semSync; ///< Semaphore used by RF_runCmd(), RF_pendCmd() and power down sequence. - RF_EventMask volatile eventSync; ///< Event mask/value used by RF_runCmd() and RF_pendCmd(). - void* pCbSync; ///< Internal storage of user callbacks when RF_runCmd() is used. - RF_EventMask unpendCause; ///< Internal storage of the return value of RF_pendCmd(). - ClockP_Struct clkReqAccess; ///< Clock used for request access timeout. - bool bYielded; ///< Flag indicates that the radio can be powered down at the earliest convenience. - } state; + uint32_t nInactivityTimeout; ///< Inactivity timeout in us. + RF_Mode* pRfMode; ///< Mode of operation. + RF_RadioSetup* pRadioSetup; ///< Pointer to the setup command to be executed at power up. + uint32_t nPhySwitchingDuration; ///< Radio reconfiguration time to this client's phy and protocol. + uint32_t nPowerUpDuration; ///< Radio power up time to be used to calculate future wake-up events. + bool bMeasurePowerUpDuration; ///< Indicates if nPowerUpDuration holds a fix value or being measured and updated at every power up. + bool bUpdateSetup; ///< Indicates if an analog configuration update should be performed at the next setup command execution. + uint16_t nPowerUpDurationMargin; ///< Power up duration margin in us. + void* pPowerCb; ///< \deprecated Power up callback, will go away in future versions, see clientConfig::pClienteventCb instead + void* pErrCb; ///< Error callback. + void* pClientEventCb; ///< Client event callback. + RF_ClientEventMask nClientEventMask; ///< Client event mask to activate client event callback. + uint16_t nPhySwitchingDurationMargin; ///< Phy switching duration margin in us. It is used to calculate when run-time conflicts shall be resolved. + } clientConfig; + /// State & variables + struct + { + struct + { + rfc_CMD_FS_t cmdFs; ///< FS command to be executed when the radio is powered up. + } mode_state; ///< (Mode-specific) state structure + SemaphoreP_Struct semSync; ///< Semaphore used by RF_runCmd(), RF_pendCmd() and power down sequence. + RF_EventMask volatile eventSync; ///< Event mask/value used by RF_runCmd() and RF_pendCmd(). + void* pCbSync; ///< Internal storage of user callbacks when RF_runCmd() is used. + RF_EventMask unpendCause; ///< Internal storage of the return value of RF_pendCmd(). + ClockP_Struct clkReqAccess; ///< Clock used for request access timeout. + bool bYielded; ///< Flag indicates that the radio can be powered down at the earliest convenience. + } state; }; /** @endcond */ @@ -1372,7 +1371,6 @@ struct RF_ObjectMultiMode */ typedef RF_Object* RF_Handle; - /** @brief RAT handle that is returned by RF_ratCompare() or RF_ratCapture(). * * An %RF_RatHandle is an integer number with value greater than or equal to zero and identifies @@ -1388,12 +1386,12 @@ typedef int8_t RF_RatHandle; */ typedef enum { - RF_GET_CURR_CMD, ///< Retrieve a command handle of the current command. - RF_GET_AVAIL_RAT_CH, ///< Create a bitmask showing available RAT channels. - RF_GET_RADIO_STATE, ///< Show the current RF core power state. 0: Radio OFF, 1: Radio ON. - RF_GET_SCHEDULE_MAP, ///< Provide a timetable of all scheduled commands. - RF_GET_CLIENT_LIST, ///< Provide the client list. - RF_GET_CLIENT_SWITCHING_TIME, ///< Provide the client to client switching times + RF_GET_CURR_CMD, ///< Retrieve a command handle of the current command. + RF_GET_AVAIL_RAT_CH, ///< Create a bitmask showing available RAT channels. + RF_GET_RADIO_STATE, ///< Show the current RF core power state. 0: Radio OFF, 1: Radio ON. + RF_GET_SCHEDULE_MAP, ///< Provide a timetable of all scheduled commands. + RF_GET_CLIENT_LIST, ///< Provide the client list. + RF_GET_CLIENT_SWITCHING_TIME, ///< Provide the client to client switching times } RF_InfoType; /** @brief Stores output parameters for RF_getInfo(). @@ -1403,12 +1401,12 @@ typedef enum */ typedef union { - RF_CmdHandle ch; ///< Command handle (#RF_GET_CURR_CMD). - uint16_t availRatCh; ///< Available RAT channels (RF_GET_AVAIL_RAT_CH). - bool bRadioState; ///< Current RF core power state (#RF_GET_RADIO_STATE). - RF_Handle pClientList[2]; ///< Client pointer list, [0]: client 1, [1]: client 2. - uint32_t phySwitchingTimeInUs[2]; ///< Phy switching time 0: client 1 -> 2, 1 : client 2 -> 1. - void* pScheduleMap; ///< Pointer to scheduling map (#RF_GET_SCHEDULE_MAP). + RF_CmdHandle ch; ///< Command handle (#RF_GET_CURR_CMD). + uint16_t availRatCh; ///< Available RAT channels (RF_GET_AVAIL_RAT_CH). + bool bRadioState; ///< Current RF core power state (#RF_GET_RADIO_STATE). + RF_Handle pClientList[2]; ///< Client pointer list, [0]: client 1, [1]: client 2. + uint32_t phySwitchingTimeInUs[2]; ///< Phy switching time 0: client 1 -> 2, 1 : client 2 -> 1. + void* pScheduleMap; ///< Pointer to scheduling map (#RF_GET_SCHEDULE_MAP). } RF_InfoVal; /** @brief RF schedule map entry structure. @@ -1416,11 +1414,11 @@ typedef union */ typedef struct { - RF_CmdHandle ch; ///< Command handle - RF_Handle pClient; ///< Pointer to client object - uint32_t startTime; ///< Start time (in RAT tick) of the command or access request - uint32_t endTime; ///< End time (in RAT tick) of the command or access request - RF_Priority priority; ///< Priority of the command or access request + RF_CmdHandle ch; ///< Command handle + RF_Handle pClient; ///< Pointer to client object + uint32_t startTime; ///< Start time (in RAT tick) of the command or access request + uint32_t endTime; ///< End time (in RAT tick) of the command or access request + RF_Priority priority; ///< Priority of the command or access request } RF_ScheduleMapElement; /** @brief RF schedule map structure. @@ -1428,8 +1426,8 @@ typedef struct */ typedef struct { - RF_ScheduleMapElement accessMap[RF_NUM_SCHEDULE_ACCESS_ENTRIES]; ///< Access request schedule map - RF_ScheduleMapElement commandMap[RF_NUM_SCHEDULE_COMMAND_ENTRIES]; ///< Command schedule map + RF_ScheduleMapElement accessMap[RF_NUM_SCHEDULE_ACCESS_ENTRIES]; ///< Access request schedule map + RF_ScheduleMapElement commandMap[RF_NUM_SCHEDULE_COMMAND_ENTRIES]; ///< Command schedule map } RF_ScheduleMap; /** @brief Handles events related to RF command execution. @@ -1516,30 +1514,30 @@ typedef void (*RF_GlobalCallback)(RF_Handle h, RF_GlobalEvent event, void* arg); */ typedef struct { - uint32_t nInactivityTimeout; ///< Inactivity timeout in microseconds. - ///< The default value is 0xFFFFFFFF (infinite). + uint32_t nInactivityTimeout; ///< Inactivity timeout in microseconds. + ///< The default value is 0xFFFFFFFF (infinite). - uint32_t nPowerUpDuration; ///< A custom power-up duration in microseconds. - ///< If 0, the RF driver will start with a conservative value and measure the actual time during the first power-up. - ///< The default value is 0. + uint32_t nPowerUpDuration; ///< A custom power-up duration in microseconds. + ///< If 0, the RF driver will start with a conservative value and measure the actual time during the first power-up. + ///< The default value is 0. - RF_Callback pPowerCb; ///< \deprecated Power up callback, will be removed future versions, see RF_Params::pClienteventCb instead. - ///< The default value is NULL. + RF_Callback pPowerCb; ///< \deprecated Power up callback, will be removed future versions, see RF_Params::pClienteventCb instead. + ///< The default value is NULL. - RF_Callback pErrCb; ///< \deprecated Callback function for driver error events. + RF_Callback pErrCb; ///< \deprecated Callback function for driver error events. - uint16_t nPowerUpDurationMargin; ///< An additional safety margin to be added to #RF_Params::nPowerUpDuration. - ///< This is necessary because of other hardware and software interrupts - ///< preempting the RF driver interrupt handlers and state machine. - ///< The default value is platform-dependent. + uint16_t nPowerUpDurationMargin; ///< An additional safety margin to be added to #RF_Params::nPowerUpDuration. + ///< This is necessary because of other hardware and software interrupts + ///< preempting the RF driver interrupt handlers and state machine. + ///< The default value is platform-dependent. - uint16_t nPhySwitchingDurationMargin; ///< An additional safety margin to be used to calculate when conflicts shall be evaluated run-time. + uint16_t nPhySwitchingDurationMargin; ///< An additional safety margin to be used to calculate when conflicts shall be evaluated run-time. - RF_ClientCallback pClientEventCb; ///< Callback function for client-related events. - ///< The default value is NULL. + RF_ClientCallback pClientEventCb; ///< Callback function for client-related events. + ///< The default value is NULL. - RF_ClientEventMask nClientEventMask; ///< Event mask used to subscribe certain client events. - ///< The purpose is to keep the number of callback executions small. + RF_ClientEventMask nClientEventMask; ///< Event mask used to subscribe certain client events. + ///< The purpose is to keep the number of callback executions small. } RF_Params; /* RF command. */ @@ -1548,19 +1546,19 @@ typedef struct RF_Cmd_s RF_Cmd; /* RF command . */ struct RF_Cmd_s { - List_Elem _elem; /* Pointer to next and previous elements. */ - RF_Callback volatile pCb; /* Pointer to callback function */ - RF_Op* pOp; /* Pointer to (chain of) RF operations(s) */ - RF_Object* pClient; /* Pointer to client */ - RF_EventMask bmEvent; /* Enable mask for interrupts from the command */ - RF_EventMask pastifg; /* Accumulated value of events happened within a command chain */ - RF_EventMask rfifg; /* Return value for callback 0:31 - RF_CPE0_INT, 32:63 - RF_HW_INT */ - uint32_t startTime; /* Command start time (in RAT ticks) */ - uint32_t endTime; /* Command end time (in RAT ticks) */ - uint32_t allowDelay; /* Delay allowed if the start time cannot be met. */ - RF_CmdHandle ch; /* Command handle */ - RF_Priority ePri; /* Priority of RF command */ - uint8_t volatile flags; /* [0: Aborted, 1: Stopped, 2: canceled] */ + List_Elem _elem; /* Pointer to next and previous elements. */ + RF_Callback volatile pCb; /* Pointer to callback function */ + RF_Op* pOp; /* Pointer to (chain of) RF operations(s) */ + RF_Object* pClient; /* Pointer to client */ + RF_EventMask bmEvent; /* Enable mask for interrupts from the command */ + RF_EventMask pastifg; /* Accumulated value of events happened within a command chain */ + RF_EventMask rfifg; /* Return value for callback 0:31 - RF_CPE0_INT, 32:63 - RF_HW_INT */ + uint32_t startTime; /* Command start time (in RAT ticks) */ + uint32_t endTime; /* Command end time (in RAT ticks) */ + uint32_t allowDelay; /* Delay allowed if the start time cannot be met. */ + RF_CmdHandle ch; /* Command handle */ + RF_Priority ePri; /* Priority of RF command */ + uint8_t volatile flags; /* [0: Aborted, 1: Stopped, 2: canceled] */ }; /** @brief RF Hardware attributes. @@ -1570,11 +1568,11 @@ struct RF_Cmd_s */ typedef struct { - uint8_t hwiPriority; ///< Priority for HWIs belong to the RF driver. - uint8_t swiPriority; ///< Priority for SWIs belong to the RF driver. - bool xoscHfAlwaysNeeded; ///< Indicate that the XOSC HF should be turned on by the power driver - RF_GlobalCallback globalCallback; ///< Pointer to a callback function serving client independent events listed in #RF_GlobalEvent. - RF_GlobalEventMask globalEventMask; ///< Event mask which the globalCallback is invoked upon. + uint8_t hwiPriority; ///< Priority for HWIs belong to the RF driver. + uint8_t swiPriority; ///< Priority for SWIs belong to the RF driver. + bool xoscHfAlwaysNeeded; ///< Indicate that the XOSC HF should be turned on by the power driver + RF_GlobalCallback globalCallback; ///< Pointer to a callback function serving client independent events listed in #RF_GlobalEvent. + RF_GlobalEventMask globalEventMask; ///< Event mask which the globalCallback is invoked upon. } RFCC26XX_HWAttrsV2; /** @brief Controls the behavior of the state machine of the RF driver when a conflict is identified @@ -1583,20 +1581,20 @@ typedef struct */ typedef enum { - RF_ConflictNone = 0, + RF_ConflictNone = 0, RF_ConflictReject = 1, - RF_ConflictAbort = 2, + RF_ConflictAbort = 2, } RF_Conflict; /** @brief Describes the location within the pend queue where the new command was inserted by the scheduler. */ typedef enum { - RF_ScheduleStatusError = -3, - RF_ScheduleStatusNone = 0, - RF_ScheduleStatusTop = 1, - RF_ScheduleStatusMiddle = 2, - RF_ScheduleStatusTail = 4, + RF_ScheduleStatusError = -3, + RF_ScheduleStatusNone = 0, + RF_ScheduleStatusTop = 1, + RF_ScheduleStatusMiddle = 2, + RF_ScheduleStatusTail = 4, RF_ScheduleStatusPreempt = 8 } RF_ScheduleStatus; @@ -1641,8 +1639,8 @@ typedef RF_Conflict (*RF_ConflictHook)(RF_Cmd* pCmdBg, RF_Cmd* pCmdFg, List_List */ typedef struct { - RF_SubmitHook submitHook; ///< Function hook implements the scheduling policy to be executed at the time of RF_scheduleCmd API call. - RF_ConflictHook conflictHook; ///< Function hook implements the runtime conflict resolution, if any identified at the start time of next command. + RF_SubmitHook submitHook; ///< Function hook implements the scheduling policy to be executed at the time of RF_scheduleCmd API call. + RF_ConflictHook conflictHook; ///< Function hook implements the runtime conflict resolution, if any identified at the start time of next command. } RFCC26XX_SchedulerPolicy; /** @brief Controls the behavior of the RF_scheduleCmd() API. @@ -1651,7 +1649,7 @@ typedef struct typedef enum { RF_AllowDelayNone = 0, - RF_AllowDelayAny = UINT32_MAX + RF_AllowDelayAny = UINT32_MAX } RF_AllowDelay; /* @brief RF schedule command parameter struct @@ -1660,12 +1658,12 @@ typedef enum */ typedef struct { - uint32_t endTime; ///< End time in RAT Ticks for the radio command - RF_Priority priority; ///< Intra client priority - uint32_t allowDelay; ///< Control word to define the policy of the scheduler if the timing of a command cannot be met. - ///< Only applicable on CC13x2 and CC26x2 devices. - ///< RF_AllowDelayNone: Reject the command. - ///< RF_AllowDelayAny: Append the command to the end of the queue. + uint32_t endTime; ///< End time in RAT Ticks for the radio command + RF_Priority priority; ///< Intra client priority + uint32_t allowDelay; ///< Control word to define the policy of the scheduler if the timing of a command cannot be met. + ///< Only applicable on CC13x2 and CC26x2 devices. + ///< RF_AllowDelayNone: Reject the command. + ///< RF_AllowDelayAny: Append the command to the end of the queue. } RF_ScheduleCmdParams; /** @brief RF request access parameter struct @@ -1674,9 +1672,9 @@ typedef struct */ typedef struct { - uint32_t duration; ///< Radio access duration in RAT Ticks requested by the client - uint32_t startTime; ///< Start time window in RAT Time for radio access - RF_Priority priority; ///< Access priority + uint32_t duration; ///< Radio access duration in RAT Ticks requested by the client + uint32_t startTime; ///< Start time window in RAT Time for radio access + RF_Priority priority; ///< Access priority } RF_AccessParams; /** @brief Select the preferred RAT channel through the configuration of #RF_ratCompare() or #RF_ratCapture(). @@ -1687,10 +1685,10 @@ typedef struct */ typedef enum { - RF_RatChannelAny = -1, ///< Chose the first available channel. - RF_RatChannel0 = 0, ///< Use RAT user channel 0. - RF_RatChannel1 = 1, ///< Use RAT user channel 1. - RF_RatChannel2 = 2, ///< Use RAT user channel 2. + RF_RatChannelAny = -1, ///< Chose the first available channel. + RF_RatChannel0 = 0, ///< Use RAT user channel 0. + RF_RatChannel1 = 1, ///< Use RAT user channel 1. + RF_RatChannel2 = 2, ///< Use RAT user channel 2. } RF_RatSelectChannel; /** @brief Selects the source signal for #RF_ratCapture(). @@ -1700,14 +1698,14 @@ typedef enum */ typedef enum { - RF_RatCaptureSourceRtcUpdate = 20, ///< Selects the RTC update signal source. + RF_RatCaptureSourceRtcUpdate = 20, ///< Selects the RTC update signal source. RF_RatCaptureSourceEventGeneric = 21, ///< Selects the Generic event of Event Fabric as source. - RF_RatCaptureSourceRfcGpi0 = 22, ///< Selects the RFC_GPI[0] as source. This can be used i.e. + RF_RatCaptureSourceRfcGpi0 = 22, ///< Selects the RFC_GPI[0] as source. This can be used i.e. ///< to capture events on a GPIO. This requires that the GPIO ///< is connected to RFC_GPO[0] from the GPIO driver. - RF_RatCaptureSourceRfcGpi1 = 23 ///< Selects the RFC_GPO[1] as source. This can be used i.e. - ///< to capture events on a GPIO. This requires that the GPIO - ///< is connected to RFC_GPO[1] from the GPIO driver. + RF_RatCaptureSourceRfcGpi1 = 23 ///< Selects the RFC_GPO[1] as source. This can be used i.e. + ///< to capture events on a GPIO. This requires that the GPIO + ///< is connected to RFC_GPO[1] from the GPIO driver. } RF_RatCaptureSource; /** @brief Selects the mode of #RF_ratCapture(). @@ -1717,10 +1715,10 @@ typedef enum */ typedef enum { - RF_RatCaptureModeRising = 0, ///< Rising edge of the selected source will trigger a capture event. - RF_RatCaptureModeFalling = 1, ///< Falling edge of the selected source will trigger a capture event. - RF_RatCaptureModeBoth = 2 ///< Both rising and falling edges of the selected source will generate - ///< capture events. + RF_RatCaptureModeRising = 0, ///< Rising edge of the selected source will trigger a capture event. + RF_RatCaptureModeFalling = 1, ///< Falling edge of the selected source will trigger a capture event. + RF_RatCaptureModeBoth = 2 ///< Both rising and falling edges of the selected source will generate + ///< capture events. } RF_RatCaptureMode; /** @brief Selects the repetition of #RF_ratCapture(). @@ -1731,8 +1729,8 @@ typedef enum */ typedef enum { - RF_RatCaptureSingle = 0, ///< Free the channel after the first capture event. - RF_RatCaptureRepeat = 1 ///< Rearm the channel after each capture events. + RF_RatCaptureSingle = 0, ///< Free the channel after the first capture event. + RF_RatCaptureRepeat = 1 ///< Rearm the channel after each capture events. } RF_RatCaptureRepetition; /** @brief Selects the mode of the RAT_GPO[x] for #RF_ratCompare() or #RF_ratCapture(). @@ -1751,12 +1749,12 @@ typedef enum */ typedef enum { - RF_RatOutputModePulse = 0, ///< Generates a one-clock period width pulse. - RF_RatOutputModeSet = 1, ///< Sets the output high on a RAT event. - RF_RatOutputModeClear = 2, ///< Sets the output low on a RAT event. - RF_RatOutputModeToggle = 3, ///< Inverts the polarity of the output. - RF_RatOutputModeAlwaysZero = 4, ///< Sets the output low independently of any RAT events. - RF_RatOutputModeAlwaysOne = 5, ///< Sets the output high independently of any RAT events. + RF_RatOutputModePulse = 0, ///< Generates a one-clock period width pulse. + RF_RatOutputModeSet = 1, ///< Sets the output high on a RAT event. + RF_RatOutputModeClear = 2, ///< Sets the output low on a RAT event. + RF_RatOutputModeToggle = 3, ///< Inverts the polarity of the output. + RF_RatOutputModeAlwaysZero = 4, ///< Sets the output low independently of any RAT events. + RF_RatOutputModeAlwaysOne = 5, ///< Sets the output high independently of any RAT events. } RF_RatOutputMode; /** @brief Selects GPO to be used with #RF_ratCompare() or #RF_ratCapture(). @@ -1770,13 +1768,13 @@ typedef enum */ typedef enum { - RF_RatOutputSelectRatGpo1 = 1, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[1] - RF_RatOutputSelectRatGpo2 = 2, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[2] - RF_RatOutputSelectRatGpo3 = 3, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[3] - RF_RatOutputSelectRatGpo4 = 4, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[4] - RF_RatOutputSelectRatGpo5 = 5, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[5] - RF_RatOutputSelectRatGpo6 = 6, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[6] - RF_RatOutputSelectRatGpo7 = 7, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[7] + RF_RatOutputSelectRatGpo1 = 1, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[1] + RF_RatOutputSelectRatGpo2 = 2, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[2] + RF_RatOutputSelectRatGpo3 = 3, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[3] + RF_RatOutputSelectRatGpo4 = 4, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[4] + RF_RatOutputSelectRatGpo5 = 5, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[5] + RF_RatOutputSelectRatGpo6 = 6, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[6] + RF_RatOutputSelectRatGpo7 = 7, ///< Configure RAT_CHANNEL[x] to interface with RAT_GPO[7] } RF_RatOutputSelect; /** @brief RF_ratCapture parameter structure. @@ -1785,11 +1783,11 @@ typedef enum */ typedef struct { - RF_RatCallback callback; ///< Callback function to be invoked upon a capture event (optional). - RF_RatHandle channel; ///< RF_RatHandle identifies the channel to be allocated. - RF_RatCaptureSource source; ///< Configuration of the event source to cause a capture event. - RF_RatCaptureMode captureMode; ///< Configuration of the mode of event to cause a capture event. - RF_RatCaptureRepetition repeat; ///< Configuration of the channel to be used in single or repeated mode. + RF_RatCallback callback; ///< Callback function to be invoked upon a capture event (optional). + RF_RatHandle channel; ///< RF_RatHandle identifies the channel to be allocated. + RF_RatCaptureSource source; ///< Configuration of the event source to cause a capture event. + RF_RatCaptureMode captureMode; ///< Configuration of the mode of event to cause a capture event. + RF_RatCaptureRepetition repeat; ///< Configuration of the channel to be used in single or repeated mode. } RF_RatConfigCapture; /** @brief RF_ratCompare parameter structure. @@ -1798,10 +1796,10 @@ typedef struct */ typedef struct { - RF_RatCallback callback; ///< Callback function to be invoked upon a capture event (optional). - RF_RatHandle channel; ///< RF_RatHandle identifies the channel to be allocated. - uint32_t timeout; ///< Timeout value in RAT ticks to be programmed in the timer as the - ///< trigger of compare event. + RF_RatCallback callback; ///< Callback function to be invoked upon a capture event (optional). + RF_RatHandle channel; ///< RF_RatHandle identifies the channel to be allocated. + uint32_t timeout; ///< Timeout value in RAT ticks to be programmed in the timer as the + ///< trigger of compare event. } RF_RatConfigCompare; /** @brief RAT related IO parameter structure. @@ -1810,8 +1808,8 @@ typedef struct */ typedef struct { - RF_RatOutputMode mode; ///< The mode the GPO should operate in. - RF_RatOutputSelect select; ///< The signal which shall be connected to the GPO. + RF_RatOutputMode mode; ///< The mode the GPO should operate in. + RF_RatOutputSelect select; ///< The signal which shall be connected to the GPO. } RF_RatConfigOutput; /** @brief Creates a a new client instance of the RF driver. @@ -1951,7 +1949,6 @@ extern RF_ScheduleStatus RF_defaultSubmitPolicy(RF_Cmd* pCmdNew, RF_Cmd* pCmdBg, */ extern RF_Conflict RF_defaultConflictPolicy(RF_Cmd* pCmdBg, RF_Cmd* pCmdFg, List_List* pPendQueue, List_List* pDoneQueue); - /** * @brief Initialize the configuration structure to default values to be used with the RF_scheduleCmd() API. * @@ -2486,7 +2483,6 @@ extern int8_t RF_TxPowerTable_findPowerLevel(RF_TxPowerTable_Entry table[], RF_T */ extern RF_TxPowerTable_Value RF_TxPowerTable_findValue(RF_TxPowerTable_Entry table[], int8_t powerLevel); - #ifdef __cplusplus } #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/sd/SDSPI.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/sd/SDSPI.h index 7719325..dc7982f 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/sd/SDSPI.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/sd/SDSPI.h @@ -71,9 +71,9 @@ extern "C" { #endif #include -#include #include #include +#include /* SDSPI function table */ extern const SD_FxnTable SDSPI_fxnTable; @@ -103,8 +103,8 @@ extern const SD_FxnTable SDSPI_fxnTable; */ typedef struct SDSPI_HWAttrs_ { - uint_least8_t spiIndex; - uint16_t spiCsGpioIndex; + uint_least8_t spiIndex; + uint16_t spiCsGpioIndex; } SDSPI_HWAttrs; /*! @@ -114,10 +114,10 @@ typedef struct SDSPI_HWAttrs_ */ typedef struct SDSPI_Object_ { - SemaphoreP_Handle lockSem; - SPI_Handle spiHandle; - SD_CardType cardType; - bool isOpen; + SemaphoreP_Handle lockSem; + SPI_Handle spiHandle; + SD_CardType cardType; + bool isOpen; } SDSPI_Object; #ifdef __cplusplus diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/sha2/SHA2CC26X2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/sha2/SHA2CC26X2.h index e82603b..a710c05 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/sha2/SHA2CC26X2.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/sha2/SHA2CC26X2.h @@ -56,8 +56,8 @@ #ifndef ti_drivers_sha2_SHA2CC26X2__include #define ti_drivers_sha2_SHA2CC26X2__include -#include #include +#include #include @@ -65,7 +65,6 @@ extern "C" { #endif - /*! * @brief Hardware-specific configuration attributes * @@ -74,26 +73,25 @@ extern "C" { */ typedef struct { - uint8_t intPriority; /*!< Hardware interrupt priority of the Hash accelerator. - * - * The CC26XX provides 8 interrupt priority levels encoded in three bits: - * - * Value | Description - * ------------ | ----------------------- - * (~0) | Special value: always lowest priority across all OS kernels. - * (7 << 5) | Priority level 7: lowest, but rather use ~0 instead. - * .. | .. - * (0 << 5) | Priority level 0: highest, not supported by this driver - * - * Hardware interrupts with priority level 0 ignore the hardware interrupt dispatcher - * for minimum latency. This is not supported by this driver. - */ + uint8_t intPriority; /*!< Hardware interrupt priority of the Hash accelerator. + * + * The CC26XX provides 8 interrupt priority levels encoded in three bits: + * + * Value | Description + * ------------ | ----------------------- + * (~0) | Special value: always lowest priority across all OS kernels. + * (7 << 5) | Priority level 7: lowest, but rather use ~0 instead. + * .. | .. + * (0 << 5) | Priority level 0: highest, not supported by this driver + * + * Hardware interrupts with priority level 0 ignore the hardware interrupt dispatcher + * for minimum latency. This is not supported by this driver. + */ } SHA2CC26X2_HWAttrs; - /*! \cond Internal APIs */ -#define SHA2CC26X2_MAX_BLOCK_SIZE_BYTES (SHA2_BLOCK_SIZE_BYTES_512) +#define SHA2CC26X2_MAX_BLOCK_SIZE_BYTES (SHA2_BLOCK_SIZE_BYTES_512) #define SHA2CC26X2_MAX_DIGEST_LENGTH_BYTES (SHA2_DIGEST_LENGTH_BYTES_512) /* @@ -103,18 +101,18 @@ typedef struct */ typedef struct { - bool isOpen; - volatile bool operationInProgress; - bool operationCanceled; - SHA2_ReturnBehavior returnBehavior; - int_fast16_t returnStatus; - uint32_t accessTimeout; - SHA2_CallbackFxn callbackFxn; - SHA2_HashType hashType; - uint16_t bytesInBuffer; - uint32_t bytesProcessed; - uint8_t buffer[SHA2CC26X2_MAX_BLOCK_SIZE_BYTES]; - uint32_t digest[SHA2CC26X2_MAX_DIGEST_LENGTH_BYTES / 4]; + bool isOpen; + volatile bool operationInProgress; + bool operationCanceled; + SHA2_ReturnBehavior returnBehavior; + int_fast16_t returnStatus; + uint32_t accessTimeout; + SHA2_CallbackFxn callbackFxn; + SHA2_HashType hashType; + uint16_t bytesInBuffer; + uint32_t bytesProcessed; + uint8_t buffer[SHA2CC26X2_MAX_BLOCK_SIZE_BYTES]; + uint32_t digest[SHA2CC26X2_MAX_DIGEST_LENGTH_BYTES / 4]; } SHA2CC26X2_Object; /* diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/spi/SPICC26X2DMA.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/spi/SPICC26X2DMA.h index 56c3331..a030188 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/spi/SPICC26X2DMA.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/spi/SPICC26X2DMA.h @@ -696,10 +696,10 @@ extern "C" { #endif #include -#include -#include -#include #include +#include +#include +#include #include #include @@ -737,7 +737,7 @@ extern "C" { * reception is inactive for a given 32-bit period. With this command @b arg * is @a don't @a care and it returns #SPI_STATUS_SUCCESS. */ -#define SPICC26X2DMA_CMD_RETURN_PARTIAL_ENABLE (SPI_CMD_RESERVED + 0) +#define SPICC26X2DMA_CMD_RETURN_PARTIAL_ENABLE (SPI_CMD_RESERVED + 0) /*! * @brief Command used by SPI_control() to disable partial return @@ -755,7 +755,7 @@ extern "C" { * With this command @b arg is of type @c PIN_Id and it return * #SPI_STATUS_SUCCESS */ -#define SPICC26X2DMA_CMD_SET_CSN_PIN (SPI_CMD_RESERVED + 2) +#define SPICC26X2DMA_CMD_SET_CSN_PIN (SPI_CMD_RESERVED + 2) /*! * @brief Command used by SPI_control() to enable manual start mode @@ -770,7 +770,7 @@ extern "C" { * * Returns #SPI_STATUS_SUCCESS or #SPI_STATUS_ERROR. */ -#define SPICC26X2DMA_CMD_SET_MANUAL (SPI_CMD_RESERVED + 3) +#define SPICC26X2DMA_CMD_SET_MANUAL (SPI_CMD_RESERVED + 3) /*! * @brief Command used by SPI_control() to disable manual start mode @@ -781,7 +781,7 @@ extern "C" { * Returns #SPI_STATUS_SUCCESS or #SPI_STATUS_ERROR. * */ -#define SPICC26X2DMA_CMD_CLR_MANUAL (SPI_CMD_RESERVED + 4) +#define SPICC26X2DMA_CMD_CLR_MANUAL (SPI_CMD_RESERVED + 4) /*! * @brief Command used by SPI_control() to enable manual start mode @@ -793,14 +793,14 @@ extern "C" { * * Returns #SPI_STATUS_SUCCESS or #SPI_STATUS_ERROR. */ -#define SPICC26X2DMA_CMD_MANUAL_START (SPI_CMD_RESERVED + 5) +#define SPICC26X2DMA_CMD_MANUAL_START (SPI_CMD_RESERVED + 5) /** @}*/ /* BACKWARDS COMPATIBILITY */ -#define SPICC26X2DMA_RETURN_PARTIAL_ENABLE SPICC26X2DMA_CMD_RETURN_PARTIAL_ENABLE -#define SPICC26X2DMA_RETURN_PARTIAL_DISABLE SPICC26X2DMA_CMD_RETURN_PARTIAL_DISABLE -#define SPICC26X2DMA_SET_CSN_PIN SPICC26X2DMA_CMD_SET_CSN_PIN +#define SPICC26X2DMA_RETURN_PARTIAL_ENABLE SPICC26X2DMA_CMD_RETURN_PARTIAL_ENABLE +#define SPICC26X2DMA_RETURN_PARTIAL_DISABLE SPICC26X2DMA_CMD_RETURN_PARTIAL_DISABLE +#define SPICC26X2DMA_SET_CSN_PIN SPICC26X2DMA_CMD_SET_CSN_PIN /* END BACKWARDS COMPATIBILITY */ /*! @@ -821,7 +821,7 @@ extern const SPI_FxnTable SPICC26X2DMA_fxnTable; */ typedef enum SPICC26X2DMA_FrameSize { - SPICC26X2DMA_8bit = 0, + SPICC26X2DMA_8bit = 0, SPICC26X2DMA_16bit = 1 } SPICC26X2DMA_FrameSize; @@ -834,7 +834,7 @@ typedef enum SPICC26X2DMA_FrameSize */ typedef enum SPICC26X2DMA_ReturnPartial { - SPICC26X2DMA_retPartDisabled = 0, + SPICC26X2DMA_retPartDisabled = 0, SPICC26X2DMA_retPartEnabledIntNotSet = 1, SPICC26X2DMA_retPartEnabledIntSet = 2 } SPICC26X2DMA_ReturnPartial; @@ -895,51 +895,51 @@ typedef enum SPICC26X2DMA_ReturnPartial */ typedef struct SPICC26X2DMA_HWAttrs { - /*! @brief SPI Peripheral's base address */ - uint32_t baseAddr; - /*! SPI CC26XXDMA Peripheral's interrupt vector */ - uint8_t intNum; - /*! @brief SPI CC26XXDMA Peripheral's interrupt priority. + /*! @brief SPI Peripheral's base address */ + uint32_t baseAddr; + /*! SPI CC26XXDMA Peripheral's interrupt vector */ + uint8_t intNum; + /*! @brief SPI CC26XXDMA Peripheral's interrupt priority. - The CC26xx uses three of the priority bits, - meaning ~0 has the same effect as (7 << 5). + The CC26xx uses three of the priority bits, + meaning ~0 has the same effect as (7 << 5). - (7 << 5) will apply the lowest priority. + (7 << 5) will apply the lowest priority. - (1 << 5) will apply the highest priority. + (1 << 5) will apply the highest priority. - Setting the priority to 0 is not supported by this driver. + Setting the priority to 0 is not supported by this driver. - HWI's with priority 0 ignore the HWI dispatcher to support zero-latency - interrupts, thus invalidating the critical sections in this driver. - */ - uint8_t intPriority; - /*! @brief SPI SWI priority. - The higher the number, the higher the priority. - The minimum is 0 and the maximum is 15 by default. - The maximum can be reduced to save RAM by adding or modifying - Swi.numPriorities in the kernel configuration file. - */ - uint32_t swiPriority; - /*! SPI Peripheral's power manager ID */ - PowerCC26XX_Resource powerMngrId; - /*! Default TX value if txBuf == NULL */ - uint16_t defaultTxBufValue; - /*! uDMA controlTable channel index */ - uint32_t rxChannelBitMask; - /*! uDMA controlTable channel index */ - uint32_t txChannelBitMask; - /*! SPI MOSI pin */ - PIN_Id mosiPin; - /*! SPI MISO pin */ - PIN_Id misoPin; - /*! SPI CLK pin */ - PIN_Id clkPin; - /*! SPI CSN pin */ - PIN_Id csnPin; + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency + interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! @brief SPI SWI priority. + The higher the number, the higher the priority. + The minimum is 0 and the maximum is 15 by default. + The maximum can be reduced to save RAM by adding or modifying + Swi.numPriorities in the kernel configuration file. + */ + uint32_t swiPriority; + /*! SPI Peripheral's power manager ID */ + PowerCC26XX_Resource powerMngrId; + /*! Default TX value if txBuf == NULL */ + uint16_t defaultTxBufValue; + /*! uDMA controlTable channel index */ + uint32_t rxChannelBitMask; + /*! uDMA controlTable channel index */ + uint32_t txChannelBitMask; + /*! SPI MOSI pin */ + PIN_Id mosiPin; + /*! SPI MISO pin */ + PIN_Id misoPin; + /*! SPI CLK pin */ + PIN_Id clkPin; + /*! SPI CSN pin */ + PIN_Id csnPin; - /*! Minimum transfer size for DMA based transfer */ - uint32_t minDmaTransferSize; + /*! Minimum transfer size for DMA based transfer */ + uint32_t minDmaTransferSize; } SPICC26X2DMA_HWAttrs; /*! @@ -949,40 +949,40 @@ typedef struct SPICC26X2DMA_HWAttrs */ typedef struct SPICC26X2DMA_Object { - HwiP_Struct hwi; - PIN_Handle pinHandle; - PIN_State pinState; - Power_NotifyObj spiPostObj; - SwiP_Struct swi; - SemaphoreP_Struct transferComplete; + HwiP_Struct hwi; + PIN_Handle pinHandle; + PIN_State pinState; + Power_NotifyObj spiPostObj; + SwiP_Struct swi; + SemaphoreP_Struct transferComplete; - SPI_CallbackFxn transferCallbackFxn; - SPI_Transaction* headPtr; - SPI_Transaction* tailPtr; - SPI_Transaction* completedTransfers; - UDMACC26XX_Handle udmaHandle; + SPI_CallbackFxn transferCallbackFxn; + SPI_Transaction* headPtr; + SPI_Transaction* tailPtr; + SPI_Transaction* completedTransfers; + UDMACC26XX_Handle udmaHandle; - size_t framesQueued; - size_t framesTransferred; - size_t priTransferSize; - size_t altTransferSize; + size_t framesQueued; + size_t framesTransferred; + size_t priTransferSize; + size_t altTransferSize; - uint32_t activeChannel; - uint32_t bitRate; - uint32_t dataSize; - uint32_t transferTimeout; - uint32_t busyBit; + uint32_t activeChannel; + uint32_t bitRate; + uint32_t dataSize; + uint32_t transferTimeout; + uint32_t busyBit; - uint16_t rxScratchBuf; - uint16_t txScratchBuf; + uint16_t rxScratchBuf; + uint16_t txScratchBuf; - SPI_TransferMode transferMode; - SPI_Mode mode; - uint8_t format; - PIN_Id csnPin; - SPICC26X2DMA_ReturnPartial returnPartial; - bool isOpen; - bool manualStart; + SPI_TransferMode transferMode; + SPI_Mode mode; + uint8_t format; + PIN_Id csnPin; + SPICC26X2DMA_ReturnPartial returnPartial; + bool isOpen; + bool manualStart; } SPICC26X2DMA_Object; #ifdef __cplusplus diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/spi/SPICC26XXDMA.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/spi/SPICC26XXDMA.h index 54a60fa..486c607 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/spi/SPICC26XXDMA.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/spi/SPICC26XXDMA.h @@ -611,10 +611,10 @@ extern "C" { #endif #include -#include -#include -#include #include +#include +#include +#include #include #include @@ -652,7 +652,7 @@ extern "C" { * reception is inactive for a given 32-bit period. With this command @b arg * is @a don't @a care and it returns SPI_STATUS_SUCCESS. */ -#define SPICC26XXDMA_CMD_RETURN_PARTIAL_ENABLE (SPI_CMD_RESERVED + 0) +#define SPICC26XXDMA_CMD_RETURN_PARTIAL_ENABLE (SPI_CMD_RESERVED + 0) /*! * @brief Command used by SPI_control to disable partial return @@ -669,13 +669,13 @@ extern "C" { * This command specifies a chip select pin * With this command @b arg is of type @c PIN_Id and it return SPI_STATUS_SUCCESS */ -#define SPICC26XXDMA_CMD_SET_CSN_PIN (SPI_CMD_RESERVED + 2) +#define SPICC26XXDMA_CMD_SET_CSN_PIN (SPI_CMD_RESERVED + 2) /** @}*/ /* BACKWARDS COMPATIBILITY */ -#define SPICC26XXDMA_RETURN_PARTIAL_ENABLE SPICC26XXDMA_CMD_RETURN_PARTIAL_ENABLE -#define SPICC26XXDMA_RETURN_PARTIAL_DISABLE SPICC26XXDMA_CMD_RETURN_PARTIAL_DISABLE -#define SPICC26XXDMA_SET_CSN_PIN SPICC26XXDMA_CMD_SET_CSN_PIN +#define SPICC26XXDMA_RETURN_PARTIAL_ENABLE SPICC26XXDMA_CMD_RETURN_PARTIAL_ENABLE +#define SPICC26XXDMA_RETURN_PARTIAL_DISABLE SPICC26XXDMA_CMD_RETURN_PARTIAL_DISABLE +#define SPICC26XXDMA_SET_CSN_PIN SPICC26XXDMA_CMD_SET_CSN_PIN /* END BACKWARDS COMPATIBILITY */ /*! @@ -696,7 +696,7 @@ extern const SPI_FxnTable SPICC26XXDMA_fxnTable; */ typedef enum SPICC26XXDMA_FrameSize { - SPICC26XXDMA_8bit = 0, + SPICC26XXDMA_8bit = 0, SPICC26XXDMA_16bit = 1 } SPICC26XXDMA_FrameSize; @@ -756,49 +756,49 @@ typedef enum SPICC26XXDMA_FrameSize */ typedef struct SPICC26XXDMA_HWAttrsV1 { - /*! SPI Peripheral's base address */ - uint32_t baseAddr; - /*! SPI CC26XXDMA Peripheral's interrupt vector */ - uint8_t intNum; - /*! @brief SPI CC26XXDMA Peripheral's interrupt priority. + /*! SPI Peripheral's base address */ + uint32_t baseAddr; + /*! SPI CC26XXDMA Peripheral's interrupt vector */ + uint8_t intNum; + /*! @brief SPI CC26XXDMA Peripheral's interrupt priority. - The CC26xx uses three of the priority bits, - meaning ~0 has the same effect as (7 << 5). + The CC26xx uses three of the priority bits, + meaning ~0 has the same effect as (7 << 5). - (7 << 5) will apply the lowest priority. + (7 << 5) will apply the lowest priority. - (1 << 5) will apply the highest priority. + (1 << 5) will apply the highest priority. - Setting the priority to 0 is not supported by this driver. + Setting the priority to 0 is not supported by this driver. - HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. - */ - uint8_t intPriority; - /*! @brief SPI SWI priority. - The higher the number, the higher the priority. - The minimum is 0 and the maximum is 15 by default. - The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. - */ - uint32_t swiPriority; - /*! SPI Peripheral's power manager ID */ - PowerCC26XX_Resource powerMngrId; - /*! Default TX value if txBuf == NULL */ - uint16_t defaultTxBufValue; - /*! uDMA controlTable channel index */ - uint32_t rxChannelBitMask; - /*! uDMA controlTable channel index */ - uint32_t txChannelBitMask; - /*! SPI MOSI pin */ - PIN_Id mosiPin; - /*! SPI MISO pin */ - PIN_Id misoPin; - /*! SPI CLK pin */ - PIN_Id clkPin; - /*! SPI CSN pin */ - PIN_Id csnPin; + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! @brief SPI SWI priority. + The higher the number, the higher the priority. + The minimum is 0 and the maximum is 15 by default. + The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. + */ + uint32_t swiPriority; + /*! SPI Peripheral's power manager ID */ + PowerCC26XX_Resource powerMngrId; + /*! Default TX value if txBuf == NULL */ + uint16_t defaultTxBufValue; + /*! uDMA controlTable channel index */ + uint32_t rxChannelBitMask; + /*! uDMA controlTable channel index */ + uint32_t txChannelBitMask; + /*! SPI MOSI pin */ + PIN_Id mosiPin; + /*! SPI MISO pin */ + PIN_Id misoPin; + /*! SPI CLK pin */ + PIN_Id clkPin; + /*! SPI CSN pin */ + PIN_Id csnPin; - /*! Minimum transfer size for DMA based transfer */ - uint32_t minDmaTransferSize; + /*! Minimum transfer size for DMA based transfer */ + uint32_t minDmaTransferSize; } SPICC26XXDMA_HWAttrsV1; /*! @@ -808,62 +808,59 @@ typedef struct SPICC26XXDMA_HWAttrsV1 */ typedef struct SPICC26XXDMA_Object { - /* SPI control variables */ - SPI_TransferMode transferMode; /*!< Blocking or Callback mode */ - unsigned int transferTimeout; /*!< Timeout for the transfer when in blocking mode */ - SPI_CallbackFxn transferCallbackFxn; /*!< Callback function pointer */ - SPI_Mode mode; /*!< Master or Slave mode */ - /*! @brief SPI bit rate in Hz. - * - * When the SPI is configured as SPI slave, the maximum bitrate is 4MHz. - * - * When the SPI is configured as SPI master, the maximum bitrate is 12MHz. - */ - unsigned int bitRate; - unsigned int dataSize; /*!< SPI data frame size in bits */ - SPI_FrameFormat frameFormat; /*!< SPI frame format */ + /* SPI control variables */ + SPI_TransferMode transferMode; /*!< Blocking or Callback mode */ + unsigned int transferTimeout; /*!< Timeout for the transfer when in blocking mode */ + SPI_CallbackFxn transferCallbackFxn; /*!< Callback function pointer */ + SPI_Mode mode; /*!< Master or Slave mode */ + /*! @brief SPI bit rate in Hz. + * + * When the SPI is configured as SPI slave, the maximum bitrate is 4MHz. + * + * When the SPI is configured as SPI master, the maximum bitrate is 12MHz. + */ + unsigned int bitRate; + unsigned int dataSize; /*!< SPI data frame size in bits */ + SPI_FrameFormat frameFormat; /*!< SPI frame format */ - /* SPI SYS/BIOS objects */ - HwiP_Struct hwi; /*!< Hwi object handle */ - SwiP_Struct swi; /*!< Swi object */ - SemaphoreP_Struct transferComplete; /*!< Notify finished SPICC26XXDMA transfer */ + /* SPI SYS/BIOS objects */ + HwiP_Struct hwi; /*!< Hwi object handle */ + SwiP_Struct swi; /*!< Swi object */ + SemaphoreP_Struct transferComplete; /*!< Notify finished SPICC26XXDMA transfer */ - /* SPI current transaction */ - SPI_Transaction* currentTransaction; /*!< Ptr to the current transaction*/ - size_t amtDataXferred; /*!< Number of frames transferred */ - size_t currentXferAmt; /*!< Size of current DMA transfer */ - SPICC26XXDMA_FrameSize frameSize; /*!< Data frame size variable */ + /* SPI current transaction */ + SPI_Transaction* currentTransaction; /*!< Ptr to the current transaction*/ + size_t amtDataXferred; /*!< Number of frames transferred */ + size_t currentXferAmt; /*!< Size of current DMA transfer */ + SPICC26XXDMA_FrameSize frameSize; /*!< Data frame size variable */ - /* Support for dynamic CSN pin allocation */ - PIN_Id csnPin; /*!< SPI CSN pin */ + /* Support for dynamic CSN pin allocation */ + PIN_Id csnPin; /*!< SPI CSN pin */ - /* PIN driver state object and handle */ - PIN_State pinState; - PIN_Handle pinHandle; + /* PIN driver state object and handle */ + PIN_State pinState; + PIN_Handle pinHandle; - /* UDMA driver handle */ - UDMACC26XX_Handle udmaHandle; + /* UDMA driver handle */ + UDMACC26XX_Handle udmaHandle; - /* Optional slave mode features */ - bool returnPartial; /*!< Optional slave mode return partial on CSN deassert */ + /* Optional slave mode features */ + bool returnPartial; /*!< Optional slave mode return partial on CSN deassert */ - /* Scratch buffer of size uint32_t */ - uint16_t scratchBuf; + /* Scratch buffer of size uint32_t */ + uint16_t scratchBuf; - /* SPI pre- and post notification functions */ - void* spiPreFxn; /*!< SPI pre-notification function pointer */ - void* spiPostFxn; /*!< SPI post-notification function pointer */ - Power_NotifyObj spiPreObj; /*!< SPI pre-notification object */ - Power_NotifyObj spiPostObj; /*!< SPI post-notification object */ + /* SPI pre- and post notification functions */ + void* spiPreFxn; /*!< SPI pre-notification function pointer */ + void* spiPostFxn; /*!< SPI post-notification function pointer */ + Power_NotifyObj spiPreObj; /*!< SPI pre-notification object */ + Power_NotifyObj spiPostObj; /*!< SPI post-notification object */ - volatile bool spiPowerConstraint; /*!< SPI power constraint flag, guard to avoid power constraints getting out of sync */ + volatile bool spiPowerConstraint; /*!< SPI power constraint flag, guard to avoid power constraints getting out of sync */ - bool isOpen; /*!< Has the object been opened */ + bool isOpen; /*!< Has the object been opened */ } SPICC26XXDMA_Object, *SPICC26XXDMA_Handle; - - - #ifdef __cplusplus } #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/timer/GPTimerCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/timer/GPTimerCC26XX.h index d496ef6..6753590 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/timer/GPTimerCC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/timer/GPTimerCC26XX.h @@ -147,17 +147,17 @@ extern "C" { #endif -#include #include #include +#include #include #include -#include DeviceFamily_constructPath(inc/hw_gpt.h) -#include DeviceFamily_constructPath(driverlib/event.h) -#include DeviceFamily_constructPath(driverlib/ioc.h) -#include DeviceFamily_constructPath(driverlib/timer.h) +#include DeviceFamily_constructPath(inc / hw_gpt.h) +#include DeviceFamily_constructPath(driverlib / event.h) +#include DeviceFamily_constructPath(driverlib / ioc.h) +#include DeviceFamily_constructPath(driverlib / timer.h) /* Backwards compatibility - old timer modes. New behaviour is count-up by default but configurable. */ #define GPT_MODE_ONESHOT_UP GPT_MODE_ONESHOT @@ -186,18 +186,18 @@ typedef enum GPTimerCC26XX_Width typedef enum GPTimerCC26XX_Mode { /* One shot mode counting upwards */ - GPT_MODE_ONESHOT = GPT_TAMR_TAMR_ONE_SHOT | GPT_TAMR_TAMIE, + GPT_MODE_ONESHOT = GPT_TAMR_TAMR_ONE_SHOT | GPT_TAMR_TAMIE, /* Periodic mode counting upwards */ - GPT_MODE_PERIODIC = GPT_TAMR_TAMR_PERIODIC | GPT_TAMR_TAMIE, + GPT_MODE_PERIODIC = GPT_TAMR_TAMR_PERIODIC | GPT_TAMR_TAMIE, /* Edge count mode counting upwards */ - GPT_MODE_EDGE_COUNT = GPT_TAMR_TAMR_CAPTURE | GPT_TAMR_TACM_EDGCNT, + GPT_MODE_EDGE_COUNT = GPT_TAMR_TAMR_CAPTURE | GPT_TAMR_TACM_EDGCNT, /* Edge count mode counting upwards */ - GPT_MODE_EDGE_TIME = GPT_TAMR_TAMR_CAPTURE | GPT_TAMR_TACM_EDGTIME, + GPT_MODE_EDGE_TIME = GPT_TAMR_TAMR_CAPTURE | GPT_TAMR_TACM_EDGTIME, /* PWM mode counting downwards. This specific configuration is used by the PWM2TimerCC26XX driver */ - GPT_MODE_PWM = GPT_TAMR_TAMR_PERIODIC | GPT_TAMR_TAPWMIE_EN | \ - GPT_TAMR_TAAMS_PWM | GPT_TAMR_TACM_EDGCNT | \ - GPT_TAMR_TAPLO_CCP_ON_TO, + GPT_MODE_PWM = GPT_TAMR_TAMR_PERIODIC | GPT_TAMR_TAPWMIE_EN | + GPT_TAMR_TAAMS_PWM | GPT_TAMR_TACM_EDGCNT | + GPT_TAMR_TAPLO_CCP_ON_TO, } GPTimerCC26XX_Mode; /*! @@ -208,14 +208,14 @@ typedef enum GPTimerCC26XX_Mode */ typedef enum GPTimerCC26XX_Interrupt { - GPT_INT_TIMEOUT = 1 << 0, + GPT_INT_TIMEOUT = 1 << 0, GPT_INT_CAPTURE_MATCH = 1 << 1, - GPT_INT_CAPTURE = 1 << 2, - GPT_INT_MATCH = 1 << 3, + GPT_INT_CAPTURE = 1 << 2, + GPT_INT_MATCH = 1 << 3, } GPTimerCC26XX_Interrupt; /* Number of entries in GPTimerCC26XX_Interrupt */ -#define GPT_NUM_INTS 4 +#define GPT_NUM_INTS 4 /*! * @brief @@ -294,26 +294,25 @@ typedef enum GPTimerCC26XX_SetMatchTiming */ typedef enum GPTimerCC26XX_Edge { - GPTimerCC26XX_POS_EDGE = GPT_CTL_TAEVENT_POS, - GPTimerCC26XX_NEG_EDGE = GPT_CTL_TAEVENT_NEG, + GPTimerCC26XX_POS_EDGE = GPT_CTL_TAEVENT_POS, + GPTimerCC26XX_NEG_EDGE = GPT_CTL_TAEVENT_NEG, GPTimerCC26XX_BOTH_EDGES = GPT_CTL_TAEVENT_BOTH, } GPTimerCC26XX_Edge; - /* Forward declaration of GPTimer configuration */ -typedef struct GPTimerCC26XX_Config GPTimerCC26XX_Config; +typedef struct GPTimerCC26XX_Config GPTimerCC26XX_Config; /* GPTimer handle is pointer to configuration structure */ -typedef GPTimerCC26XX_Config* GPTimerCC26XX_Handle; +typedef GPTimerCC26XX_Config* GPTimerCC26XX_Handle; /* Interrupt bit vector. See GPTimerCC26XX_Interrupt for available interrupts */ -typedef uint16_t GPTimerCC26XX_IntMask; +typedef uint16_t GPTimerCC26XX_IntMask; /* Timer value */ -typedef uint32_t GPTimerCC26XX_Value; +typedef uint32_t GPTimerCC26XX_Value; /* Function prototype for interrupt callbacks */ -typedef void (*GPTimerCC26XX_HwiFxn) (GPTimerCC26XX_Handle handle, GPTimerCC26XX_IntMask interruptMask); +typedef void (*GPTimerCC26XX_HwiFxn)(GPTimerCC26XX_Handle handle, GPTimerCC26XX_IntMask interruptMask); /*! * @brief GPTimer26XX Hardware attributes @@ -337,26 +336,26 @@ typedef void (*GPTimerCC26XX_HwiFxn) (GPTimerCC26XX_Handle handle, GPTimerCC26XX */ typedef struct GPTimerCC26XX_HWAttrs { - /*! GPTimer peripheral base address */ - uint32_t baseAddr; - /*! GPTimer peripheral interrupt vector */ - uint8_t intNum; - /*! GPTimer peripheral's interrupt priority. - The CC26xx uses three of the priority bits, - meaning ~0 has the same effect as (7 << 5). - (7 << 5) will apply the lowest priority. - (1 << 5) will apply the highest priority. - Setting the priority to 0 is not supported by this driver. - HWI's with priority 0 ignore the HWI dispatcher to support zero-latency - interrupts, thus invalidating the critical sections in this driver. - */ - uint8_t intPriority; - /*! GPTimer peripheral's power manager ID */ - uint8_t powerMngrId; - /*! GPTimer half timer unit */ - GPTimerCC26XX_Part timer; - /*! PIN driver MUX */ - GPTimerCC26XX_PinMux pinMux; + /*! GPTimer peripheral base address */ + uint32_t baseAddr; + /*! GPTimer peripheral interrupt vector */ + uint8_t intNum; + /*! GPTimer peripheral's interrupt priority. + The CC26xx uses three of the priority bits, + meaning ~0 has the same effect as (7 << 5). + (7 << 5) will apply the lowest priority. + (1 << 5) will apply the highest priority. + Setting the priority to 0 is not supported by this driver. + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency + interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! GPTimer peripheral's power manager ID */ + uint8_t powerMngrId; + /*! GPTimer half timer unit */ + GPTimerCC26XX_Part timer; + /*! PIN driver MUX */ + GPTimerCC26XX_PinMux pinMux; } GPTimerCC26XX_HWAttrs; /*! @@ -375,14 +374,13 @@ typedef struct GPTimerCC26XX_HWAttrs */ typedef struct GPTimerCC26XX_Object { - GPTimerCC26XX_Width width; /*!< Timer width configuration (16/32bit)*/ - bool isOpen[GPT_PARTS_COUNT]; /*!< Object is opened flag */ - HwiP_Struct hwi[GPT_PARTS_COUNT]; /*!< Hardware interrupt struct */ - GPTimerCC26XX_HwiFxn hwiCallbackFxn[GPT_PARTS_COUNT]; /*!< Hardware interrupt callback function */ - volatile bool powerConstraint[GPT_PARTS_COUNT]; /*!< Standby power constraint flag */ + GPTimerCC26XX_Width width; /*!< Timer width configuration (16/32bit)*/ + bool isOpen[GPT_PARTS_COUNT]; /*!< Object is opened flag */ + HwiP_Struct hwi[GPT_PARTS_COUNT]; /*!< Hardware interrupt struct */ + GPTimerCC26XX_HwiFxn hwiCallbackFxn[GPT_PARTS_COUNT]; /*!< Hardware interrupt callback function */ + volatile bool powerConstraint[GPT_PARTS_COUNT]; /*!< Standby power constraint flag */ } GPTimerCC26XX_Object; - /*! * @brief GPTimer Global configuration * @@ -405,9 +403,9 @@ typedef struct GPTimerCC26XX_Object */ struct GPTimerCC26XX_Config { - GPTimerCC26XX_Object* object; - const GPTimerCC26XX_HWAttrs* hwAttrs; - GPTimerCC26XX_Part timerPart; + GPTimerCC26XX_Object* object; + const GPTimerCC26XX_HWAttrs* hwAttrs; + GPTimerCC26XX_Part timerPart; }; /*! @@ -420,14 +418,13 @@ struct GPTimerCC26XX_Config */ typedef struct GPTimerCC26XX_Params { - GPTimerCC26XX_Width width; /*!< Timer configuration (32/16-bit) */ - GPTimerCC26XX_Mode mode; /*!< Timer mode */ - GPTimerCC26XX_SetMatchTiming matchTiming; /*!< Set new match values on next timeout or next cycle */ - GPTimerCC26XX_Direction direction; /*!< Count up or down */ - GPTimerCC26XX_DebugMode debugStallMode; /*!< Timer debug stall mode */ + GPTimerCC26XX_Width width; /*!< Timer configuration (32/16-bit) */ + GPTimerCC26XX_Mode mode; /*!< Timer mode */ + GPTimerCC26XX_SetMatchTiming matchTiming; /*!< Set new match values on next timeout or next cycle */ + GPTimerCC26XX_Direction direction; /*!< Count up or down */ + GPTimerCC26XX_DebugMode debugStallMode; /*!< Timer debug stall mode */ } GPTimerCC26XX_Params; - /*! * @brief Function to initialize the GPTimerCC26XX_Params struct to * its default values @@ -525,7 +522,6 @@ extern void GPTimerCC26XX_setLoadValue(GPTimerCC26XX_Handle handle, GPTimerCC26X */ extern void GPTimerCC26XX_setMatchValue(GPTimerCC26XX_Handle handle, GPTimerCC26XX_Value matchValue); - /*! * @brief Function to set which input edge the GPTimer capture should * use. Applies to edge-count and edge-time modes @@ -572,7 +568,6 @@ extern GPTimerCC26XX_Value GPTimerCC26XX_getFreeRunValue(GPTimerCC26XX_Handle ha */ extern GPTimerCC26XX_Value GPTimerCC26XX_getValue(GPTimerCC26XX_Handle handle); - /*! * @brief Function to register a CPU interrupt for a given timer handle and * enable a set of timer interrupt sources. The interrupt to the CPU @@ -679,7 +674,6 @@ static inline GPTimerCC26XX_PinMux GPTimerCC26XX_getPinMux(GPTimerCC26XX_Handle return handle->hwAttrs->pinMux; } - #ifdef __cplusplus } #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/trng/TRNGCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/trng/TRNGCC26XX.h index abb17c8..602e0b2 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/trng/TRNGCC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/trng/TRNGCC26XX.h @@ -59,25 +59,25 @@ extern "C" { #endif -#include #include +#include #include #include #include #include -#include #include +#include /*! @brief Minimum random samples for each entropy generation call */ -#define TRNGCC26XX_SAMPLES_PER_CYCLE_MIN 256 +#define TRNGCC26XX_SAMPLES_PER_CYCLE_MIN 256 /*! @brief Default random samples for each entropy generation call * * Set to generate 64 bits of randomness in 5ms with all FROs active. */ -#define TRNGCC26XX_SAMPLES_PER_CYCLE_DEFAULT 240000 +#define TRNGCC26XX_SAMPLES_PER_CYCLE_DEFAULT 240000 /*! @brief Maximum random samples for each entropy generation call */ -#define TRNGCC26XX_SAMPLES_PER_CYCLE_MAX 16777216 +#define TRNGCC26XX_SAMPLES_PER_CYCLE_MAX 16777216 /*! @brief Minimum number of bytes provided by the TRNG hardware * in one go. Smaller amounts can by requested in driver * calls but the full number will always be generated. @@ -85,7 +85,7 @@ extern "C" { * back to the target buffer if the requested length is not * a multiple of TRNGCC26XX_MIN_BYTES_PER_ISR. */ -#define TRNGCC26XX_MIN_BYTES_PER_ITERATION 8 +#define TRNGCC26XX_MIN_BYTES_PER_ITERATION 8 /*! * @brief TRNGCC26XX Hardware Attributes @@ -95,31 +95,31 @@ extern "C" { */ typedef struct TRNGCC26XX_HWAttrs { - /*! @brief Crypto Peripheral's interrupt priority. + /*! @brief Crypto Peripheral's interrupt priority. - The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). - (7 << 5) will apply the lowest priority. + (7 << 5) will apply the lowest priority. - (1 << 5) will apply the highest priority. + (1 << 5) will apply the highest priority. - Setting the priority to 0 is not supported by this driver. + Setting the priority to 0 is not supported by this driver. - HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. - */ - uint8_t intPriority; - /*! @brief TRNG SWI priority. - The higher the number, the higher the priority. - The minimum is 0 and the maximum is 15 by default. - The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. - */ - uint32_t swiPriority; - /*! @brief TRNG Maximum Samples per Cycle. - Changes the maximum number of randomness samples in each entropy generation cycle before dump and interrupt. - The minimum is 2^8 (256) and the maximum is 2^24 (16777216). - The default is 240000 - enough to generate 64 bits of randomness at 5MHz. - */ - uint32_t samplesPerCycle; + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! @brief TRNG SWI priority. + The higher the number, the higher the priority. + The minimum is 0 and the maximum is 15 by default. + The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. + */ + uint32_t swiPriority; + /*! @brief TRNG Maximum Samples per Cycle. + Changes the maximum number of randomness samples in each entropy generation cycle before dump and interrupt. + The minimum is 2^8 (256) and the maximum is 2^24 (16777216). + The default is 240000 - enough to generate 64 bits of randomness at 5MHz. + */ + uint32_t samplesPerCycle; } TRNGCC26XX_HWAttrs; /*! @@ -129,16 +129,16 @@ typedef struct TRNGCC26XX_HWAttrs */ typedef struct TRNGCC26XX_Object { - bool isOpen; - TRNG_ReturnBehavior returnBehavior; - int_fast16_t returnStatus; - size_t entropyGenerated; - size_t entropyRequested; - uint32_t semaphoreTimeout; - uint8_t* entropyBuffer; - CryptoKey* entropyKey; - uint32_t samplesPerCycle; - TRNG_CallbackFxn callbackFxn; + bool isOpen; + TRNG_ReturnBehavior returnBehavior; + int_fast16_t returnStatus; + size_t entropyGenerated; + size_t entropyRequested; + uint32_t semaphoreTimeout; + uint8_t* entropyBuffer; + CryptoKey* entropyKey; + uint32_t samplesPerCycle; + TRNG_CallbackFxn callbackFxn; } TRNGCC26XX_Object; /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26X0.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26X0.h index ea1c7e4..7029a90 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26X0.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26X0.h @@ -344,20 +344,18 @@ extern "C" { #endif -#include #include +#include +#include +#include #include #include #include #include -#include -#include #include #include - - /*! * @brief No hardware flow control */ @@ -399,7 +397,7 @@ extern "C" { * reception is inactive for a given 32-bit period. With this command @b arg * is @a don't @a care and it returns UART_STATUS_SUCCESS. */ -#define UARTCC26X0_CMD_RETURN_PARTIAL_ENABLE (UART_CMD_RESERVED + 0) +#define UARTCC26X0_CMD_RETURN_PARTIAL_ENABLE (UART_CMD_RESERVED + 0) /*! * @brief Command used by UART_control to disable partial return @@ -408,7 +406,7 @@ extern "C" { * behavior where UART_read blocks until all data bytes were received. With * this comand @b arg is @a don't @a care and it returns UART_STATUS_SUCCESS. */ -#define UARTCC26X0_CMD_RETURN_PARTIAL_DISABLE (UART_CMD_RESERVED + 1) +#define UARTCC26X0_CMD_RETURN_PARTIAL_DISABLE (UART_CMD_RESERVED + 1) /*! * @brief Command used by UART_control to flush the RX FIFO @@ -416,8 +414,7 @@ extern "C" { * This control command flushes any contents in the RX FIFO. With this command * @b arg is @a don't @a care and it returns UART_STATUS_SUCCESS. */ -#define UARTCC26X0_CMD_RX_FIFO_FLUSH (UART_CMD_RESERVED + 2) - +#define UARTCC26X0_CMD_RX_FIFO_FLUSH (UART_CMD_RESERVED + 2) /** @}*/ @@ -455,7 +452,7 @@ typedef enum UARTCC26X0_FifoThreshold * @param error The current value of the receive * status register. */ -typedef void (*UARTCC26X0_ErrorCallback) (UART_Handle handle, uint32_t error); +typedef void (*UARTCC26X0_ErrorCallback)(UART_Handle handle, uint32_t error); /* UART function table pointer */ extern const UART_FxnTable UARTCC26X0_fxnTable; @@ -516,38 +513,38 @@ extern const UART_FxnTable UARTCC26X0_fxnTable; */ typedef struct UARTCC26X0_HWAttrs { - /*! UART Peripheral's base address */ - uint32_t baseAddr; - /*! UART Peripheral's interrupt vector */ - int intNum; - /*! UART Peripheral's interrupt priority */ - uint8_t intPriority; - /*! - * @brief Swi priority. - * The higher the number, the higher the priority. The minimum - * priority is 0 and the maximum is defined by the underlying OS. - */ - uint32_t swiPriority; - /*! Hardware flow control setting */ - uint32_t flowControl; - /*! Pointer to an application ring buffer */ - unsigned char* ringBufPtr; - /*! Size of ringBufPtr */ - size_t ringBufSize; - /*! UART RX pin assignment */ - uint8_t rxPin; - /*! UART TX pin assignment */ - uint8_t txPin; - /*! UART clear to send (CTS) pin assignment */ - uint8_t ctsPin; - /*! UART request to send (RTS) pin assignment */ - uint8_t rtsPin; - /*! UART TX interrupt FIFO threshold select */ - UARTCC26X0_FifoThreshold txIntFifoThr; - /*! UART RX interrupt FIFO threshold select */ - UARTCC26X0_FifoThreshold rxIntFifoThr; - /*! Application error function to be called on receive errors */ - UARTCC26X0_ErrorCallback errorFxn; + /*! UART Peripheral's base address */ + uint32_t baseAddr; + /*! UART Peripheral's interrupt vector */ + int intNum; + /*! UART Peripheral's interrupt priority */ + uint8_t intPriority; + /*! + * @brief Swi priority. + * The higher the number, the higher the priority. The minimum + * priority is 0 and the maximum is defined by the underlying OS. + */ + uint32_t swiPriority; + /*! Hardware flow control setting */ + uint32_t flowControl; + /*! Pointer to an application ring buffer */ + unsigned char* ringBufPtr; + /*! Size of ringBufPtr */ + size_t ringBufSize; + /*! UART RX pin assignment */ + uint8_t rxPin; + /*! UART TX pin assignment */ + uint8_t txPin; + /*! UART clear to send (CTS) pin assignment */ + uint8_t ctsPin; + /*! UART request to send (RTS) pin assignment */ + uint8_t rtsPin; + /*! UART TX interrupt FIFO threshold select */ + UARTCC26X0_FifoThreshold txIntFifoThr; + /*! UART RX interrupt FIFO threshold select */ + UARTCC26X0_FifoThreshold rxIntFifoThr; + /*! Application error function to be called on receive errors */ + UARTCC26X0_ErrorCallback errorFxn; } UARTCC26X0_HWAttrs; /*! @@ -557,74 +554,74 @@ typedef struct UARTCC26X0_HWAttrs */ typedef struct UARTCC26X0_Object { - /* UART state variable */ - struct - { - bool opened: 1; /* Has the obj been opened */ - UART_Mode readMode: 1; /* Mode for all read calls */ - UART_Mode writeMode: 1; /* Mode for all write calls */ - UART_DataMode readDataMode: 1; /* Type of data being read */ - UART_DataMode writeDataMode: 1; /* Type of data being written */ - UART_ReturnMode readReturnMode: 1; /* Receive return mode */ - UART_Echo readEcho: 1; /* Echo received data back */ - /* - * Flag to determine if a timeout has occurred when the user called - * UART_read(). This flag is set by the timeoutClk clock object. - */ - bool bufTimeout: 1; - /* - * Flag to determine when an ISR needs to perform a callback; in both - * UART_MODE_BLOCKING or UART_MODE_CALLBACK - */ - bool callCallback: 1; - /* - * Flag to determine if the ISR is in control draining the ring buffer - * when in UART_MODE_CALLBACK - */ - bool drainByISR: 1; - /* Keep track of RX enabled state set by app with UART_control() */ - bool ctrlRxEnabled: 1; - /* Flag to keep the state of the read Power constraints */ - bool rxEnabled: 1; - /* Flag to keep the state of the write Power constraints */ - bool txEnabled: 1; - } state; + /* UART state variable */ + struct + { + bool opened : 1; /* Has the obj been opened */ + UART_Mode readMode : 1; /* Mode for all read calls */ + UART_Mode writeMode : 1; /* Mode for all write calls */ + UART_DataMode readDataMode : 1; /* Type of data being read */ + UART_DataMode writeDataMode : 1; /* Type of data being written */ + UART_ReturnMode readReturnMode : 1; /* Receive return mode */ + UART_Echo readEcho : 1; /* Echo received data back */ + /* + * Flag to determine if a timeout has occurred when the user called + * UART_read(). This flag is set by the timeoutClk clock object. + */ + bool bufTimeout : 1; + /* + * Flag to determine when an ISR needs to perform a callback; in both + * UART_MODE_BLOCKING or UART_MODE_CALLBACK + */ + bool callCallback : 1; + /* + * Flag to determine if the ISR is in control draining the ring buffer + * when in UART_MODE_CALLBACK + */ + bool drainByISR : 1; + /* Keep track of RX enabled state set by app with UART_control() */ + bool ctrlRxEnabled : 1; + /* Flag to keep the state of the read Power constraints */ + bool rxEnabled : 1; + /* Flag to keep the state of the write Power constraints */ + bool txEnabled : 1; + } state; - HwiP_Struct hwi; /* Hwi object for interrupts */ - SwiP_Struct swi; /* Swi for read/write callbacks */ - ClockP_Struct timeoutClk; /* Clock object to for timeouts */ - ClockP_Struct txFifoEmptyClk; /* UART TX FIFO empty clock */ - uint32_t baudRate; /* Baud rate for UART */ - UART_LEN dataLength; /* Data length for UART */ - UART_STOP stopBits; /* Stop bits for UART */ - UART_PAR parityType; /* Parity bit type for UART */ - uint32_t status; /* RX status */ + HwiP_Struct hwi; /* Hwi object for interrupts */ + SwiP_Struct swi; /* Swi for read/write callbacks */ + ClockP_Struct timeoutClk; /* Clock object to for timeouts */ + ClockP_Struct txFifoEmptyClk; /* UART TX FIFO empty clock */ + uint32_t baudRate; /* Baud rate for UART */ + UART_LEN dataLength; /* Data length for UART */ + UART_STOP stopBits; /* Stop bits for UART */ + UART_PAR parityType; /* Parity bit type for UART */ + uint32_t status; /* RX status */ - /* UART read variables */ - RingBuf_Object ringBuffer; /* local circular buffer object */ - unsigned char* readBuf; /* Buffer data pointer */ - size_t readSize; /* Desired number of bytes to read */ - size_t readCount; /* Number of bytes left to read */ - SemaphoreP_Struct readSem; /* UART read semaphore */ - unsigned int readTimeout; /* Timeout for read semaphore */ - UART_Callback readCallback; /* Pointer to read callback */ - bool readRetPartial; /* Return partial RX data if timeout occurs */ + /* UART read variables */ + RingBuf_Object ringBuffer; /* local circular buffer object */ + unsigned char* readBuf; /* Buffer data pointer */ + size_t readSize; /* Desired number of bytes to read */ + size_t readCount; /* Number of bytes left to read */ + SemaphoreP_Struct readSem; /* UART read semaphore */ + unsigned int readTimeout; /* Timeout for read semaphore */ + UART_Callback readCallback; /* Pointer to read callback */ + bool readRetPartial; /* Return partial RX data if timeout occurs */ - /* UART write variables */ - const unsigned char* writeBuf; /* Buffer data pointer */ - size_t writeSize; /* Desired number of bytes to write*/ - size_t writeCount; /* Number of bytes left to write */ - SemaphoreP_Struct writeSem; /* UART write semaphore*/ - unsigned int writeTimeout; /* Timeout for write semaphore */ - UART_Callback writeCallback; /* Pointer to write callback */ - unsigned int writeEmptyClkTimeout; /* TX FIFO timeout tick count */ + /* UART write variables */ + const unsigned char* writeBuf; /* Buffer data pointer */ + size_t writeSize; /* Desired number of bytes to write*/ + size_t writeCount; /* Number of bytes left to write */ + SemaphoreP_Struct writeSem; /* UART write semaphore*/ + unsigned int writeTimeout; /* Timeout for write semaphore */ + UART_Callback writeCallback; /* Pointer to write callback */ + unsigned int writeEmptyClkTimeout; /* TX FIFO timeout tick count */ - /* PIN driver state object and handle */ - PIN_State pinState; - PIN_Handle hPin; + /* PIN driver state object and handle */ + PIN_State pinState; + PIN_Handle hPin; - /* For Power management */ - Power_NotifyObj postNotify; + /* For Power management */ + Power_NotifyObj postNotify; } UARTCC26X0_Object, *UARTCC26X0_Handle; #ifdef __cplusplus diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26X2.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26X2.h index b128e44..a34b7a7 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26X2.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26X2.h @@ -345,20 +345,18 @@ extern "C" { #endif -#include #include +#include +#include +#include #include #include #include #include -#include -#include #include #include - - /*! * @brief No hardware flow control */ @@ -400,7 +398,7 @@ extern "C" { * reception is inactive for a given 32-bit period. With this command @b arg * is @a don't @a care and it returns UART_STATUS_SUCCESS. */ -#define UARTCC26X2_CMD_RETURN_PARTIAL_ENABLE (UART_CMD_RESERVED + 0) +#define UARTCC26X2_CMD_RETURN_PARTIAL_ENABLE (UART_CMD_RESERVED + 0) /*! * @brief Command used by UART_control to disable partial return @@ -409,7 +407,7 @@ extern "C" { * behavior where UART_read blocks until all data bytes were received. With * this comand @b arg is @a don't @a care and it returns UART_STATUS_SUCCESS. */ -#define UARTCC26X2_CMD_RETURN_PARTIAL_DISABLE (UART_CMD_RESERVED + 1) +#define UARTCC26X2_CMD_RETURN_PARTIAL_DISABLE (UART_CMD_RESERVED + 1) /*! * @brief Command used by UART_control to flush the RX FIFO @@ -417,8 +415,7 @@ extern "C" { * This control command flushes any contents in the RX FIFO. With this command * @b arg is @a don't @a care and it returns UART_STATUS_SUCCESS. */ -#define UARTCC26X2_CMD_RX_FIFO_FLUSH (UART_CMD_RESERVED + 2) - +#define UARTCC26X2_CMD_RX_FIFO_FLUSH (UART_CMD_RESERVED + 2) /** @}*/ @@ -456,7 +453,7 @@ typedef enum UARTCC26X2_FifoThreshold * @param error The current value of the receive * status register. */ -typedef void (*UARTCC26X2_ErrorCallback) (UART_Handle handle, uint32_t error); +typedef void (*UARTCC26X2_ErrorCallback)(UART_Handle handle, uint32_t error); /* UART function table pointer */ extern const UART_FxnTable UARTCC26X2_fxnTable; @@ -535,38 +532,38 @@ extern const UART_FxnTable UARTCC26X2_fxnTable; */ typedef struct UARTCC26X2_HWAttrs { - /*! UART Peripheral's base address */ - uint32_t baseAddr; - /*! UART Peripheral's interrupt vector */ - int intNum; - /*! UART Peripheral's interrupt priority */ - uint8_t intPriority; - /*! - * @brief Swi priority. - * The higher the number, the higher the priority. The minimum - * priority is 0 and the maximum is defined by the underlying OS. - */ - uint32_t swiPriority; - /*! Hardware flow control setting */ - uint32_t flowControl; - /*! Pointer to an application ring buffer */ - unsigned char* ringBufPtr; - /*! Size of ringBufPtr */ - size_t ringBufSize; - /*! UART RX pin assignment */ - uint8_t rxPin; - /*! UART TX pin assignment */ - uint8_t txPin; - /*! UART clear to send (CTS) pin assignment */ - uint8_t ctsPin; - /*! UART request to send (RTS) pin assignment */ - uint8_t rtsPin; - /*! UART TX interrupt FIFO threshold select */ - UARTCC26X2_FifoThreshold txIntFifoThr; - /*! UART RX interrupt FIFO threshold select */ - UARTCC26X2_FifoThreshold rxIntFifoThr; - /*! Application error function to be called on receive errors */ - UARTCC26X2_ErrorCallback errorFxn; + /*! UART Peripheral's base address */ + uint32_t baseAddr; + /*! UART Peripheral's interrupt vector */ + int intNum; + /*! UART Peripheral's interrupt priority */ + uint8_t intPriority; + /*! + * @brief Swi priority. + * The higher the number, the higher the priority. The minimum + * priority is 0 and the maximum is defined by the underlying OS. + */ + uint32_t swiPriority; + /*! Hardware flow control setting */ + uint32_t flowControl; + /*! Pointer to an application ring buffer */ + unsigned char* ringBufPtr; + /*! Size of ringBufPtr */ + size_t ringBufSize; + /*! UART RX pin assignment */ + uint8_t rxPin; + /*! UART TX pin assignment */ + uint8_t txPin; + /*! UART clear to send (CTS) pin assignment */ + uint8_t ctsPin; + /*! UART request to send (RTS) pin assignment */ + uint8_t rtsPin; + /*! UART TX interrupt FIFO threshold select */ + UARTCC26X2_FifoThreshold txIntFifoThr; + /*! UART RX interrupt FIFO threshold select */ + UARTCC26X2_FifoThreshold rxIntFifoThr; + /*! Application error function to be called on receive errors */ + UARTCC26X2_ErrorCallback errorFxn; } UARTCC26X2_HWAttrs; /*! @@ -576,74 +573,74 @@ typedef struct UARTCC26X2_HWAttrs */ typedef struct UARTCC26X2_Object { - /* UART state variable */ - struct - { - bool opened: 1; /* Has the obj been opened */ - UART_Mode readMode: 1; /* Mode for all read calls */ - UART_Mode writeMode: 1; /* Mode for all write calls */ - UART_DataMode readDataMode: 1; /* Type of data being read */ - UART_DataMode writeDataMode: 1; /* Type of data being written */ - UART_ReturnMode readReturnMode: 1; /* Receive return mode */ - UART_Echo readEcho: 1; /* Echo received data back */ - /* - * Flag to determine if a timeout has occurred when the user called - * UART_read(). This flag is set by the timeoutClk clock object. - */ - bool bufTimeout: 1; - /* - * Flag to determine when an ISR needs to perform a callback; in both - * UART_MODE_BLOCKING or UART_MODE_CALLBACK - */ - bool callCallback: 1; - /* - * Flag to determine if the ISR is in control draining the ring buffer - * when in UART_MODE_CALLBACK - */ - bool drainByISR: 1; - /* Keep track of RX enabled state set by app with UART_control() */ - bool ctrlRxEnabled: 1; - /* Flag to keep the state of the read Power constraints */ - bool rxEnabled: 1; - /* Flag to keep the state of the write Power constraints */ - bool txEnabled: 1; - } state; + /* UART state variable */ + struct + { + bool opened : 1; /* Has the obj been opened */ + UART_Mode readMode : 1; /* Mode for all read calls */ + UART_Mode writeMode : 1; /* Mode for all write calls */ + UART_DataMode readDataMode : 1; /* Type of data being read */ + UART_DataMode writeDataMode : 1; /* Type of data being written */ + UART_ReturnMode readReturnMode : 1; /* Receive return mode */ + UART_Echo readEcho : 1; /* Echo received data back */ + /* + * Flag to determine if a timeout has occurred when the user called + * UART_read(). This flag is set by the timeoutClk clock object. + */ + bool bufTimeout : 1; + /* + * Flag to determine when an ISR needs to perform a callback; in both + * UART_MODE_BLOCKING or UART_MODE_CALLBACK + */ + bool callCallback : 1; + /* + * Flag to determine if the ISR is in control draining the ring buffer + * when in UART_MODE_CALLBACK + */ + bool drainByISR : 1; + /* Keep track of RX enabled state set by app with UART_control() */ + bool ctrlRxEnabled : 1; + /* Flag to keep the state of the read Power constraints */ + bool rxEnabled : 1; + /* Flag to keep the state of the write Power constraints */ + bool txEnabled : 1; + } state; - HwiP_Struct hwi; /* Hwi object for interrupts */ - SwiP_Struct readSwi; /* Swi for read callbacks */ - SwiP_Struct writeSwi; /* Swi for write callbacks */ - ClockP_Struct timeoutClk; /* Clock object to for timeouts */ - uint32_t baudRate; /* Baud rate for UART */ - UART_LEN dataLength; /* Data length for UART */ - UART_STOP stopBits; /* Stop bits for UART */ - UART_PAR parityType; /* Parity bit type for UART */ - uint32_t status; /* RX status */ + HwiP_Struct hwi; /* Hwi object for interrupts */ + SwiP_Struct readSwi; /* Swi for read callbacks */ + SwiP_Struct writeSwi; /* Swi for write callbacks */ + ClockP_Struct timeoutClk; /* Clock object to for timeouts */ + uint32_t baudRate; /* Baud rate for UART */ + UART_LEN dataLength; /* Data length for UART */ + UART_STOP stopBits; /* Stop bits for UART */ + UART_PAR parityType; /* Parity bit type for UART */ + uint32_t status; /* RX status */ - /* UART read variables */ - RingBuf_Object ringBuffer; /* local circular buffer object */ - unsigned char* readBuf; /* Buffer data pointer */ - size_t readSize; /* Desired number of bytes to read */ - size_t readCount; /* Number of bytes left to read */ - SemaphoreP_Struct readSem; /* UART read semaphore */ - unsigned int readTimeout; /* Timeout for read semaphore */ - UART_Callback readCallback; /* Pointer to read callback */ - bool readRetPartial; /* Return partial RX data if timeout occurs */ + /* UART read variables */ + RingBuf_Object ringBuffer; /* local circular buffer object */ + unsigned char* readBuf; /* Buffer data pointer */ + size_t readSize; /* Desired number of bytes to read */ + size_t readCount; /* Number of bytes left to read */ + SemaphoreP_Struct readSem; /* UART read semaphore */ + unsigned int readTimeout; /* Timeout for read semaphore */ + UART_Callback readCallback; /* Pointer to read callback */ + bool readRetPartial; /* Return partial RX data if timeout occurs */ - /* UART write variables */ - const unsigned char* writeBuf; /* Buffer data pointer */ - size_t writeSize; /* Desired number of bytes to write*/ - size_t writeCount; /* Number of bytes left to write */ - SemaphoreP_Struct writeSem; /* UART write semaphore*/ - unsigned int writeTimeout; /* Timeout for write semaphore */ - UART_Callback writeCallback; /* Pointer to write callback */ + /* UART write variables */ + const unsigned char* writeBuf; /* Buffer data pointer */ + size_t writeSize; /* Desired number of bytes to write*/ + size_t writeCount; /* Number of bytes left to write */ + SemaphoreP_Struct writeSem; /* UART write semaphore*/ + unsigned int writeTimeout; /* Timeout for write semaphore */ + UART_Callback writeCallback; /* Pointer to write callback */ - /* PIN driver state object and handle */ - PIN_State pinState; - PIN_Handle hPin; + /* PIN driver state object and handle */ + PIN_State pinState; + PIN_Handle hPin; - /* For Power management */ - Power_NotifyObj postNotify; - unsigned int powerMgrId; /* Determined from base address */ + /* For Power management */ + Power_NotifyObj postNotify; + unsigned int powerMgrId; /* Determined from base address */ } UARTCC26X2_Object, *UARTCC26X2_Handle; #ifdef __cplusplus diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26XX.h index 501eb15..26ac2b2 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/uart/UARTCC26XX.h @@ -375,21 +375,21 @@ extern "C" { #endif -#include #include +#include +#include #include #include -#include #include #include -#include DeviceFamily_constructPath(driverlib/uart.h) +#include DeviceFamily_constructPath(driverlib / uart.h) -#include -#include #include +#include #include +#include /** * @addtogroup UART_STATUS @@ -422,7 +422,7 @@ extern "C" { * reception is inactive for a given 32-bit period. With this command @b arg * is @a don't @a care and it returns UART_STATUS_SUCCESS. */ -#define UARTCC26XX_CMD_RETURN_PARTIAL_ENABLE (UART_CMD_RESERVED + 0) +#define UARTCC26XX_CMD_RETURN_PARTIAL_ENABLE (UART_CMD_RESERVED + 0) /*! * @brief Command used by UART_control to disable partial return @@ -431,7 +431,7 @@ extern "C" { * behavior where UART_read blocks until all data bytes were received. With * this comand @b arg is @a don't @a care and it returns UART_STATUS_SUCCESS. */ -#define UARTCC26XX_CMD_RETURN_PARTIAL_DISABLE (UART_CMD_RESERVED + 1) +#define UARTCC26XX_CMD_RETURN_PARTIAL_DISABLE (UART_CMD_RESERVED + 1) /*! * @brief Command used by UART_control to flush the RX FIFO @@ -439,7 +439,7 @@ extern "C" { * This control command flushes any contents in the RX FIFO. With this command * @b arg is @a don't @a care and it returns UART_STATUS_SUCCESS. */ -#define UARTCC26XX_CMD_RX_FIFO_FLUSH (UART_CMD_RESERVED + 2) +#define UARTCC26XX_CMD_RX_FIFO_FLUSH (UART_CMD_RESERVED + 2) /** @}*/ /*! Size of the TX and RX FIFOs is 32 items */ @@ -465,8 +465,8 @@ typedef enum UARTCC26XX_FifoThreshold } UARTCC26XX_FifoThreshold; /* BACKWARDS COMPATIBILITY */ -#define UARTCC26XX_RETURN_PARTIAL_ENABLE UARTCC26XX_CMD_RETURN_PARTIAL_ENABLE -#define UARTCC26XX_RETURN_PARTIAL_DISABLE UARTCC26XX_CMD_RETURN_PARTIAL_DISABLE +#define UARTCC26XX_RETURN_PARTIAL_ENABLE UARTCC26XX_CMD_RETURN_PARTIAL_ENABLE +#define UARTCC26XX_RETURN_PARTIAL_DISABLE UARTCC26XX_CMD_RETURN_PARTIAL_DISABLE /* END BACKWARDS COMPATIBILITY */ /*! @@ -479,7 +479,7 @@ typedef enum UARTCC26XX_FifoThreshold * @param error The current value of the receive * status register. */ -typedef void (*UARTCC26XX_ErrorCallback) (UART_Handle handle, uint32_t error); +typedef void (*UARTCC26XX_ErrorCallback)(UART_Handle handle, uint32_t error); /* UART function table pointer */ extern const UART_FxnTable UARTCC26XX_fxnTable; @@ -529,38 +529,38 @@ extern const UART_FxnTable UARTCC26XX_fxnTable; */ typedef struct UARTCC26XX_HWAttrsV2 { - uint32_t baseAddr; /*!< UART Peripheral's base address */ - uint32_t powerMngrId; /*!< UART Peripheral's power manager ID */ - int intNum; /*!< UART Peripheral's interrupt vector */ - /*! @brief UART Peripheral's interrupt priority. + uint32_t baseAddr; /*!< UART Peripheral's base address */ + uint32_t powerMngrId; /*!< UART Peripheral's power manager ID */ + int intNum; /*!< UART Peripheral's interrupt vector */ + /*! @brief UART Peripheral's interrupt priority. - The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). + The CC26xx uses three of the priority bits, meaning ~0 has the same effect as (7 << 5). - (7 << 5) will apply the lowest priority. + (7 << 5) will apply the lowest priority. - (1 << 5) will apply the highest priority. + (1 << 5) will apply the highest priority. - Setting the priority to 0 is not supported by this driver. + Setting the priority to 0 is not supported by this driver. - HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. - */ - uint8_t intPriority; - /*! @brief SPI SWI priority. - The higher the number, the higher the priority. - The minimum is 0 and the maximum is 15 by default. - The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. - */ - uint32_t swiPriority; - uint8_t txPin; /*!< UART TX pin */ - uint8_t rxPin; /*!< UART RX pin */ - uint8_t ctsPin; /*!< UART CTS pin */ - uint8_t rtsPin; /*!< UART RTS pin */ - unsigned char* ringBufPtr; /*!< Pointer to an application ring buffer */ - size_t ringBufSize; /*!< Size of ringBufPtr */ - UARTCC26XX_FifoThreshold txIntFifoThr; /*!< UART TX interrupt FIFO threshold select */ - UARTCC26XX_FifoThreshold rxIntFifoThr; /*!< UART RX interrupt FIFO threshold select */ - /*! Application error function to be called on receive errors */ - UARTCC26XX_ErrorCallback errorFxn; + HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver. + */ + uint8_t intPriority; + /*! @brief SPI SWI priority. + The higher the number, the higher the priority. + The minimum is 0 and the maximum is 15 by default. + The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. + */ + uint32_t swiPriority; + uint8_t txPin; /*!< UART TX pin */ + uint8_t rxPin; /*!< UART RX pin */ + uint8_t ctsPin; /*!< UART CTS pin */ + uint8_t rtsPin; /*!< UART RTS pin */ + unsigned char* ringBufPtr; /*!< Pointer to an application ring buffer */ + size_t ringBufSize; /*!< Size of ringBufPtr */ + UARTCC26XX_FifoThreshold txIntFifoThr; /*!< UART TX interrupt FIFO threshold select */ + UARTCC26XX_FifoThreshold rxIntFifoThr; /*!< UART RX interrupt FIFO threshold select */ + /*! Application error function to be called on receive errors */ + UARTCC26XX_ErrorCallback errorFxn; } UARTCC26XX_HWAttrsV2; /*! @@ -570,12 +570,12 @@ typedef struct UARTCC26XX_HWAttrsV2 */ typedef enum UART_Status { - UART_TIMED_OUT = 0x10, /*!< UART timed out */ - UART_PARITY_ERROR = UART_RXERROR_PARITY, /*!< UART Parity error */ - UART_BRAKE_ERROR = UART_RXERROR_BREAK, /*!< UART Break error */ + UART_TIMED_OUT = 0x10, /*!< UART timed out */ + UART_PARITY_ERROR = UART_RXERROR_PARITY, /*!< UART Parity error */ + UART_BRAKE_ERROR = UART_RXERROR_BREAK, /*!< UART Break error */ UART_OVERRUN_ERROR = UART_RXERROR_OVERRUN, /*!< UART overrun error */ UART_FRAMING_ERROR = UART_RXERROR_FRAMING, /*!< UART Framing error */ - UART_OK = 0x0 /*!< UART OK */ + UART_OK = 0x0 /*!< UART OK */ } UART_Status; /*! @@ -585,61 +585,61 @@ typedef enum UART_Status */ typedef struct UARTCC26XX_Object { - /* UART control variables */ - bool opened; /*!< Has the obj been opened */ - UART_Mode readMode; /*!< Mode for all read calls */ - UART_Mode writeMode; /*!< Mode for all write calls */ - unsigned int readTimeout; /*!< Timeout for read semaphore in BLOCKING mode*/ - unsigned int writeTimeout; /*!< Timeout for write semaphore in BLOCKING mode*/ - UART_Callback readCallback; /*!< Pointer to read callback */ - UART_Callback writeCallback; /*!< Pointer to write callback */ - UART_ReturnMode readReturnMode; /*!< Receive return mode */ - UART_DataMode readDataMode; /*!< Type of data being read */ - UART_DataMode writeDataMode; /*!< Type of data being written */ - /*! @brief Baud rate for CC26xx UART - * - * The CC26xx driver supports baud rates up to 3Mbaud. - * However, when receiving more than 32 bytes back-to-back the baud - * rate is limited to approx. 2Mbaud. - * The throughput is also dependent on the user application. - */ - uint32_t baudRate; - UART_LEN dataLength; /*!< Data length for UART */ - UART_STOP stopBits; /*!< Stop bits for UART */ - UART_PAR parityType; /*!< Parity bit type for UART */ - UART_Status status; /*!< Status variable */ + /* UART control variables */ + bool opened; /*!< Has the obj been opened */ + UART_Mode readMode; /*!< Mode for all read calls */ + UART_Mode writeMode; /*!< Mode for all write calls */ + unsigned int readTimeout; /*!< Timeout for read semaphore in BLOCKING mode*/ + unsigned int writeTimeout; /*!< Timeout for write semaphore in BLOCKING mode*/ + UART_Callback readCallback; /*!< Pointer to read callback */ + UART_Callback writeCallback; /*!< Pointer to write callback */ + UART_ReturnMode readReturnMode; /*!< Receive return mode */ + UART_DataMode readDataMode; /*!< Type of data being read */ + UART_DataMode writeDataMode; /*!< Type of data being written */ + /*! @brief Baud rate for CC26xx UART + * + * The CC26xx driver supports baud rates up to 3Mbaud. + * However, when receiving more than 32 bytes back-to-back the baud + * rate is limited to approx. 2Mbaud. + * The throughput is also dependent on the user application. + */ + uint32_t baudRate; + UART_LEN dataLength; /*!< Data length for UART */ + UART_STOP stopBits; /*!< Stop bits for UART */ + UART_PAR parityType; /*!< Parity bit type for UART */ + UART_Status status; /*!< Status variable */ - /* UART write variables */ - const void* writeBuf; /*!< Buffer data pointer */ - size_t writeCount; /*!< Number of Chars sent */ - size_t writeSize; /*!< Chars remaining in buffer */ - bool writeCR; /*!< Write a return character */ + /* UART write variables */ + const void* writeBuf; /*!< Buffer data pointer */ + size_t writeCount; /*!< Number of Chars sent */ + size_t writeSize; /*!< Chars remaining in buffer */ + bool writeCR; /*!< Write a return character */ - /* UART receive variables */ - bool readRetPartial; /*!< Return partial RX data if timeout occurs */ - void* readBuf; /*!< Buffer data pointer */ - size_t readCount; /*!< Number of Chars read */ - size_t readSize; /*!< Chars remaining in buffer */ - RingBuf_Object ringBuffer; /*!< local circular buffer object */ + /* UART receive variables */ + bool readRetPartial; /*!< Return partial RX data if timeout occurs */ + void* readBuf; /*!< Buffer data pointer */ + size_t readCount; /*!< Number of Chars read */ + size_t readSize; /*!< Chars remaining in buffer */ + RingBuf_Object ringBuffer; /*!< local circular buffer object */ - /* PIN driver state object and handle */ - PIN_State pinState; - PIN_Handle hPin; + /* PIN driver state object and handle */ + PIN_State pinState; + PIN_Handle hPin; - /*! UART post-notification function pointer */ - void* uartPostFxn; - /*! UART post-notification object */ - Power_NotifyObj uartPostObj; + /*! UART post-notification function pointer */ + void* uartPostFxn; + /*! UART post-notification object */ + Power_NotifyObj uartPostObj; - /* UART SYS/BIOS objects */ - HwiP_Struct hwi; /*!< Hwi object */ - SwiP_Struct swi; /*!< Swi object */ - SemaphoreP_Struct writeSem; /*!< UART write semaphore*/ - SemaphoreP_Struct readSem; /*!< UART read semaphore */ - ClockP_Struct txFifoEmptyClk; /*!< UART TX FIFO empty clock */ + /* UART SYS/BIOS objects */ + HwiP_Struct hwi; /*!< Hwi object */ + SwiP_Struct swi; /*!< Swi object */ + SemaphoreP_Struct writeSem; /*!< UART write semaphore*/ + SemaphoreP_Struct readSem; /*!< UART read semaphore */ + ClockP_Struct txFifoEmptyClk; /*!< UART TX FIFO empty clock */ - bool uartRxPowerConstraint; - bool uartTxPowerConstraint; + bool uartRxPowerConstraint; + bool uartTxPowerConstraint; } UARTCC26XX_Object, *UARTCC26XX_Handle; #ifdef __cplusplus diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/List.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/List.h index 8d80a54..00ed572 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/List.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/List.h @@ -119,20 +119,20 @@ extern "C" { #endif -#include #include #include +#include typedef struct List_Elem { - struct List_Elem* next; - struct List_Elem* prev; + struct List_Elem* next; + struct List_Elem* prev; } List_Elem; typedef struct List_List { - List_Elem* head; - List_Elem* tail; + List_Elem* head; + List_Elem* tail; } List_List; /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/Random.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/Random.h index 384dd3f..b3c26ef 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/Random.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/Random.h @@ -79,12 +79,12 @@ extern "C" { #endif -#include #include #include +#include -#define Random_STATUS_SUCCESS (0) -#define Random_STATUS_ERROR (-1) +#define Random_STATUS_SUCCESS (0) +#define Random_STATUS_ERROR (-1) /*! @brief Length of the seed in bytes */ #define Random_SEED_LENGTH (20) @@ -162,7 +162,6 @@ extern uint32_t Random_getNumber(void); */ extern void Random_getBytes(void* buffer, size_t bufferSize); - #ifdef __cplusplus } #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/RingBuf.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/RingBuf.h index 8bce543..8495561 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/RingBuf.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/utils/RingBuf.h @@ -37,18 +37,18 @@ extern "C" { #endif -#include -#include #include +#include +#include typedef struct RingBuf_Object { - unsigned char* buffer; - size_t length; - size_t count; - size_t head; - size_t tail; - size_t maxCount; + unsigned char* buffer; + size_t length; + size_t count; + size_t head; + size_t tail; + size_t maxCount; } RingBuf_Object, *RingBuf_Handle; /*! diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/watchdog/WatchdogCC26XX.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/watchdog/WatchdogCC26XX.h index 8d2f84b..5a1e3b7 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/watchdog/WatchdogCC26XX.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/drivers/watchdog/WatchdogCC26XX.h @@ -178,8 +178,8 @@ extern "C" { #endif -#include #include +#include #include /** @@ -220,8 +220,8 @@ extern const Watchdog_FxnTable WatchdogCC26XX_fxnTable; */ typedef struct WatchdogCC26XX_HWAttrs { - unsigned int baseAddr; /*!< Base adddress for Watchdog */ - unsigned long reloadValue; /*!< Reload value in milliseconds for Watchdog */ + unsigned int baseAddr; /*!< Base adddress for Watchdog */ + unsigned long reloadValue; /*!< Reload value in milliseconds for Watchdog */ } WatchdogCC26XX_HWAttrs; /*! @@ -231,15 +231,15 @@ typedef struct WatchdogCC26XX_HWAttrs */ typedef struct WatchdogCC26XX_Object { - bool isOpen; /* Flag for open/close status */ - Watchdog_Callback callbackFxn; /* Pointer to callback. Not supported - on all targets. */ - Watchdog_ResetMode resetMode; /* Mode to enable resets. - Not supported on all targets. */ - Watchdog_DebugMode debugStallMode; /* Mode to stall Watchdog at breakpoints. - Not supported on all targets. */ - /* Watchdog SYS/BIOS objects */ - HwiP_Struct hwi; /* Hwi object */ + bool isOpen; /* Flag for open/close status */ + Watchdog_Callback callbackFxn; /* Pointer to callback. Not supported + on all targets. */ + Watchdog_ResetMode resetMode; /* Mode to enable resets. + Not supported on all targets. */ + Watchdog_DebugMode debugStallMode; /* Mode to stall Watchdog at breakpoints. + Not supported on all targets. */ + /* Watchdog SYS/BIOS objects */ + HwiP_Struct hwi; /* Hwi object */ } WatchdogCC26XX_Object; #ifdef __cplusplus diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/errno.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/errno.h index 231b90a..9eb18ab 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/errno.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/errno.h @@ -39,7 +39,7 @@ /* compiler vendor check */ #ifndef __GNUC__ - #error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. +#error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. #endif /* include toolchain's header file */ @@ -50,7 +50,7 @@ extern "C" { #endif /* custom error codes */ -#define EFREERTOS 2001 /* FreeRTOS function failure */ +#define EFREERTOS 2001 /* FreeRTOS function failure */ #ifdef __cplusplus } diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/mqueue.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/mqueue.h index d85aab3..24c5908 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/mqueue.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/mqueue.h @@ -39,14 +39,14 @@ /* compiler vendor check */ #ifndef __GNUC__ - #error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. +#error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. #endif #include #include -#include "time.h" #include "sys/types.h" +#include "time.h" #ifdef __cplusplus extern "C" { @@ -60,11 +60,11 @@ typedef void* mqd_t; */ struct mq_attr { - long mq_flags; /* Message queue description flags: 0 or O_NONBLOCK. + long mq_flags; /* Message queue description flags: 0 or O_NONBLOCK. Initialized from oflag argument of mq_open(). */ - long mq_maxmsg; /* Maximum number of messages on queue. */ - long mq_msgsize; /* Maximum message size. */ - long mq_curmsgs; /* Number of messages currently queued. */ + long mq_maxmsg; /* Maximum number of messages on queue. */ + long mq_msgsize; /* Maximum message size. */ + long mq_curmsgs; /* Number of messages currently queued. */ }; /* Deprecated. This typedef is for compatibility with old SDKs. It is @@ -74,14 +74,14 @@ struct mq_attr typedef struct mq_attr mq_attr; /* For mq_open() */ -#define O_CREAT 0x200 /* TODO: sys/fcntl.h? */ -#define O_EXCL 0x0800 /* Error on open if queue exists */ -#define O_RDONLY 0 -#define O_WRONLY 1 -#define O_RDWR 2 -#define O_NONBLOCK 0x4000 /* Fail with EAGAIN if resources unavailable */ +#define O_CREAT 0x200 /* TODO: sys/fcntl.h? */ +#define O_EXCL 0x0800 /* Error on open if queue exists */ +#define O_RDONLY 0 +#define O_WRONLY 1 +#define O_RDWR 2 +#define O_NONBLOCK 0x4000 /* Fail with EAGAIN if resources unavailable */ -typedef uint32_t mode_t; /* TODO: sys/stat.h? */ +typedef uint32_t mode_t; /* TODO: sys/stat.h? */ extern int mq_close(mqd_t mqdes); extern int mq_getattr(mqd_t mqdes, struct mq_attr* mqstat); diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/pthread.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/pthread.h index e1a47e8..cc3eeb2 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/pthread.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/pthread.h @@ -39,14 +39,14 @@ /* compiler vendor check */ #ifndef __GNUC__ - #error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. +#error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. #endif #include +#include "sched.h" #include "sys/types.h" #include "time.h" -#include "sched.h" #ifdef __cplusplus extern "C" { @@ -54,13 +54,13 @@ extern "C" { #define PTHREAD_BARRIER_SERIAL_THREAD -1 -#define PTHREAD_CREATE_JOINABLE 0 -#define PTHREAD_CREATE_DETACHED 1 +#define PTHREAD_CREATE_JOINABLE 0 +#define PTHREAD_CREATE_DETACHED 1 /* PThread cancellation */ -#define PTHREAD_CANCEL_ENABLE 0 -#define PTHREAD_CANCEL_DISABLE 1 -#define PTHREAD_CANCELED ((void *) -1) +#define PTHREAD_CANCEL_ENABLE 0 +#define PTHREAD_CANCEL_DISABLE 1 +#define PTHREAD_CANCELED ((void*)-1) /* * Mutex attributes - type @@ -72,10 +72,10 @@ extern "C" { * error is returned. * */ -#define PTHREAD_MUTEX_NORMAL 0 -#define PTHREAD_MUTEX_RECURSIVE 1 -#define PTHREAD_MUTEX_ERRORCHECK 2 -#define PTHREAD_MUTEX_DEFAULT PTHREAD_MUTEX_NORMAL +#define PTHREAD_MUTEX_NORMAL 0 +#define PTHREAD_MUTEX_RECURSIVE 1 +#define PTHREAD_MUTEX_ERRORCHECK 2 +#define PTHREAD_MUTEX_DEFAULT PTHREAD_MUTEX_NORMAL /* Passed to pthread_once() */ #define PTHREAD_ONCE_INIT 0 @@ -91,11 +91,11 @@ extern "C" { * owned (regardless of whether or not other threads are blocked on * any of these mutexes). */ -#define PTHREAD_PRIO_NONE 0 -#define PTHREAD_PRIO_INHERIT 1 -#define PTHREAD_PRIO_PROTECT 2 +#define PTHREAD_PRIO_NONE 0 +#define PTHREAD_PRIO_INHERIT 1 +#define PTHREAD_PRIO_PROTECT 2 -#define PTHREAD_PROCESS_PRIVATE 0 +#define PTHREAD_PROCESS_PRIVATE 0 /* ************************************************************************* @@ -140,147 +140,149 @@ extern void _pthread_cleanup_pop(struct _pthread_cleanup_context* context, extern void _pthread_cleanup_push(struct _pthread_cleanup_context* context, void (*fxn)(void*), void* arg); -#define pthread_cleanup_push(fxn, arg) \ - do { \ +#define pthread_cleanup_push(fxn, arg) \ + do \ + { \ struct _pthread_cleanup_context _pthread_clup_ctx; \ - _pthread_cleanup_push(&_pthread_clup_ctx, (fxn), (arg)) + _pthread_cleanup_push(&_pthread_clup_ctx, (fxn), (arg)) -#define pthread_cleanup_pop(execute) \ +#define pthread_cleanup_pop(execute) \ _pthread_cleanup_pop(&_pthread_clup_ctx, (execute)); \ - } while (0) + } \ + while (0) - extern int pthread_create(pthread_t* newthread, const pthread_attr_t* attr, - void* (*startroutine)(void*), void* arg); - extern int pthread_detach(pthread_t pthread); - extern int pthread_equal(pthread_t pt1, pthread_t pt2); - extern void pthread_exit(void* ptr); - extern int pthread_getschedparam(pthread_t thread, int* policy, - struct sched_param* param); - extern int pthread_join(pthread_t th, void** thread_return); - extern int pthread_once(pthread_once_t* once, void (*initFxn)(void)); - extern pthread_t pthread_self(void); - extern int pthread_setcancelstate(int state, int* oldstate); - extern int pthread_setschedparam(pthread_t pthread, int policy, - const struct sched_param* param); +extern int pthread_create(pthread_t* newthread, const pthread_attr_t* attr, + void* (*startroutine)(void*), void* arg); +extern int pthread_detach(pthread_t pthread); +extern int pthread_equal(pthread_t pt1, pthread_t pt2); +extern void pthread_exit(void* ptr); +extern int pthread_getschedparam(pthread_t thread, int* policy, + struct sched_param* param); +extern int pthread_join(pthread_t th, void** thread_return); +extern int pthread_once(pthread_once_t* once, void (*initFxn)(void)); +extern pthread_t pthread_self(void); +extern int pthread_setcancelstate(int state, int* oldstate); +extern int pthread_setschedparam(pthread_t pthread, int policy, + const struct sched_param* param); - /* - ************************************************************************* - * pthread_barrierattr - ************************************************************************* - */ - extern int pthread_barrierattr_destroy(pthread_barrierattr_t* attr); - extern int pthread_barrierattr_init(pthread_barrierattr_t* attr); +/* + ************************************************************************* + * pthread_barrierattr + ************************************************************************* + */ +extern int pthread_barrierattr_destroy(pthread_barrierattr_t* attr); +extern int pthread_barrierattr_init(pthread_barrierattr_t* attr); - /* - ************************************************************************* - * pthread_barrier - ************************************************************************* - */ - extern int pthread_barrier_destroy(pthread_barrier_t* barrier); - extern int pthread_barrier_init(pthread_barrier_t* barrier, - const pthread_barrierattr_t* attr, unsigned count); - extern int pthread_barrier_wait(pthread_barrier_t* barrier); +/* + ************************************************************************* + * pthread_barrier + ************************************************************************* + */ +extern int pthread_barrier_destroy(pthread_barrier_t* barrier); +extern int pthread_barrier_init(pthread_barrier_t* barrier, + const pthread_barrierattr_t* attr, unsigned count); +extern int pthread_barrier_wait(pthread_barrier_t* barrier); - /* - ************************************************************************* - * pthread_condattr - ************************************************************************* - */ - extern int pthread_condattr_destroy(pthread_condattr_t* attr); - extern int pthread_condattr_getclock(const pthread_condattr_t* attr, - clockid_t* clock_id); - extern int pthread_condattr_init(pthread_condattr_t* attr); - extern int pthread_condattr_setclock(pthread_condattr_t* attr, - clockid_t clock_id); +/* + ************************************************************************* + * pthread_condattr + ************************************************************************* + */ +extern int pthread_condattr_destroy(pthread_condattr_t* attr); +extern int pthread_condattr_getclock(const pthread_condattr_t* attr, + clockid_t* clock_id); +extern int pthread_condattr_init(pthread_condattr_t* attr); +extern int pthread_condattr_setclock(pthread_condattr_t* attr, + clockid_t clock_id); - /* - ************************************************************************* - * pthread_cond - ************************************************************************* - */ - extern int pthread_cond_broadcast(pthread_cond_t* cond); - extern int pthread_cond_destroy(pthread_cond_t* cond); - extern int pthread_cond_init(pthread_cond_t* cond, - const pthread_condattr_t* attr); - extern int pthread_cond_signal(pthread_cond_t* cond); - extern int pthread_cond_timedwait(pthread_cond_t* cond, pthread_mutex_t* mutex, - const struct timespec* abstime); - extern int pthread_cond_wait(pthread_cond_t* cond, pthread_mutex_t* mutex); +/* + ************************************************************************* + * pthread_cond + ************************************************************************* + */ +extern int pthread_cond_broadcast(pthread_cond_t* cond); +extern int pthread_cond_destroy(pthread_cond_t* cond); +extern int pthread_cond_init(pthread_cond_t* cond, + const pthread_condattr_t* attr); +extern int pthread_cond_signal(pthread_cond_t* cond); +extern int pthread_cond_timedwait(pthread_cond_t* cond, pthread_mutex_t* mutex, + const struct timespec* abstime); +extern int pthread_cond_wait(pthread_cond_t* cond, pthread_mutex_t* mutex); - /* - ************************************************************************* - * pthread_key - ************************************************************************* - */ - extern int pthread_key_create(pthread_key_t* key, void (*destructor)(void*)); - extern int pthread_key_delete(pthread_key_t key); - extern void* pthread_getspecific(pthread_key_t key); - extern int pthread_setspecific(pthread_key_t key, const void* value); +/* + ************************************************************************* + * pthread_key + ************************************************************************* + */ +extern int pthread_key_create(pthread_key_t* key, void (*destructor)(void*)); +extern int pthread_key_delete(pthread_key_t key); +extern void* pthread_getspecific(pthread_key_t key); +extern int pthread_setspecific(pthread_key_t key, const void* value); - /* - ************************************************************************* - * pthread_mutexattr - ************************************************************************* - */ - extern int pthread_mutexattr_destroy(pthread_mutexattr_t* attr); - extern int pthread_mutexattr_gettype(const pthread_mutexattr_t* attr, - int* type); - extern int pthread_mutexattr_getprioceiling(const pthread_mutexattr_t* attr, - int* prioceiling); - extern int pthread_mutexattr_getprotocol(const pthread_mutexattr_t* attr, - int* protocol); - extern int pthread_mutexattr_init(pthread_mutexattr_t* attr); - extern int pthread_mutexattr_setprioceiling(pthread_mutexattr_t* attr, - int prioceiling); - extern int pthread_mutexattr_setprotocol(pthread_mutexattr_t* attr, - int protocol); - extern int pthread_mutexattr_settype(pthread_mutexattr_t* attr, int type); - - /* - ************************************************************************* - * pthread_mutex - ************************************************************************* - */ - extern int pthread_mutex_destroy(pthread_mutex_t* mutex); - extern int pthread_mutex_getprioceiling(const pthread_mutex_t* mutex, +/* + ************************************************************************* + * pthread_mutexattr + ************************************************************************* + */ +extern int pthread_mutexattr_destroy(pthread_mutexattr_t* attr); +extern int pthread_mutexattr_gettype(const pthread_mutexattr_t* attr, + int* type); +extern int pthread_mutexattr_getprioceiling(const pthread_mutexattr_t* attr, int* prioceiling); - extern int pthread_mutex_init(pthread_mutex_t* mutex, - const pthread_mutexattr_t* attr); - extern int pthread_mutex_lock(pthread_mutex_t* mutex); - extern int pthread_mutex_setprioceiling(pthread_mutex_t* mutex, - int prioceiling, int* oldceiling); - extern int pthread_mutex_timedlock(pthread_mutex_t* mutex, - const struct timespec* abstime); - extern int pthread_mutex_trylock(pthread_mutex_t* mutex); +extern int pthread_mutexattr_getprotocol(const pthread_mutexattr_t* attr, + int* protocol); +extern int pthread_mutexattr_init(pthread_mutexattr_t* attr); +extern int pthread_mutexattr_setprioceiling(pthread_mutexattr_t* attr, + int prioceiling); +extern int pthread_mutexattr_setprotocol(pthread_mutexattr_t* attr, + int protocol); +extern int pthread_mutexattr_settype(pthread_mutexattr_t* attr, int type); - extern int pthread_mutex_unlock(pthread_mutex_t* mutex); +/* + ************************************************************************* + * pthread_mutex + ************************************************************************* + */ +extern int pthread_mutex_destroy(pthread_mutex_t* mutex); +extern int pthread_mutex_getprioceiling(const pthread_mutex_t* mutex, + int* prioceiling); +extern int pthread_mutex_init(pthread_mutex_t* mutex, + const pthread_mutexattr_t* attr); +extern int pthread_mutex_lock(pthread_mutex_t* mutex); +extern int pthread_mutex_setprioceiling(pthread_mutex_t* mutex, + int prioceiling, int* oldceiling); +extern int pthread_mutex_timedlock(pthread_mutex_t* mutex, + const struct timespec* abstime); +extern int pthread_mutex_trylock(pthread_mutex_t* mutex); - /* - ************************************************************************* - * pthread_rwlockattr - ************************************************************************* - */ - extern int pthread_rwlockattr_destroy(pthread_rwlockattr_t* attr); - extern int pthread_rwlockattr_init(pthread_rwlockattr_t* attr); +extern int pthread_mutex_unlock(pthread_mutex_t* mutex); - /* - ************************************************************************* - * pthread_rwlock - ************************************************************************* - */ - extern int pthread_rwlock_destroy(pthread_rwlock_t* rwlock); - extern int pthread_rwlock_init(pthread_rwlock_t* rwlock, - const pthread_rwlockattr_t* attr); +/* + ************************************************************************* + * pthread_rwlockattr + ************************************************************************* + */ +extern int pthread_rwlockattr_destroy(pthread_rwlockattr_t* attr); +extern int pthread_rwlockattr_init(pthread_rwlockattr_t* attr); - extern int pthread_rwlock_rdlock(pthread_rwlock_t* rwlock); - extern int pthread_rwlock_timedrdlock(pthread_rwlock_t* rwlock, - const struct timespec* abstime); - extern int pthread_rwlock_timedwrlock(pthread_rwlock_t* rwlock, - const struct timespec* abstime); - extern int pthread_rwlock_tryrdlock(pthread_rwlock_t* rwlock); - extern int pthread_rwlock_trywrlock(pthread_rwlock_t* rwlock); - extern int pthread_rwlock_unlock(pthread_rwlock_t* rwlock); - extern int pthread_rwlock_wrlock(pthread_rwlock_t* rwlock); +/* + ************************************************************************* + * pthread_rwlock + ************************************************************************* + */ +extern int pthread_rwlock_destroy(pthread_rwlock_t* rwlock); +extern int pthread_rwlock_init(pthread_rwlock_t* rwlock, + const pthread_rwlockattr_t* attr); + +extern int pthread_rwlock_rdlock(pthread_rwlock_t* rwlock); +extern int pthread_rwlock_timedrdlock(pthread_rwlock_t* rwlock, + const struct timespec* abstime); +extern int pthread_rwlock_timedwrlock(pthread_rwlock_t* rwlock, + const struct timespec* abstime); +extern int pthread_rwlock_tryrdlock(pthread_rwlock_t* rwlock); +extern int pthread_rwlock_trywrlock(pthread_rwlock_t* rwlock); +extern int pthread_rwlock_unlock(pthread_rwlock_t* rwlock); +extern int pthread_rwlock_wrlock(pthread_rwlock_t* rwlock); #ifdef __cplusplus } diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/sched.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/sched.h index 13e8262..d1740f0 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/sched.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/sched.h @@ -39,7 +39,7 @@ /* compiler vendor check */ #ifndef __GNUC__ - #error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. +#error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. #endif #include @@ -70,7 +70,7 @@ extern "C" { */ struct sched_param { - int sched_priority; /* Thread execution priority */ + int sched_priority; /* Thread execution priority */ }; /* diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/semaphore.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/semaphore.h index ea8b62d..ddec0ee 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/semaphore.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/semaphore.h @@ -39,11 +39,11 @@ /* compiler vendor check */ #ifndef __GNUC__ - #error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. +#error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. #endif -#include #include "sys/_internal.h" +#include /* * Include definitions of timespec and clockid_t that would @@ -59,17 +59,17 @@ extern "C" { typedef union { - struct sysbios_Semaphore sysbios; - struct freertos_Semaphore freertos; + struct sysbios_Semaphore sysbios; + struct freertos_Semaphore freertos; } sem_t; -int sem_destroy(sem_t* sem); -int sem_getvalue(sem_t* sem, int* value); -int sem_init(sem_t* sem, int pshared, unsigned value); -int sem_post(sem_t* sem); -int sem_timedwait(sem_t* sem, const struct timespec* abstime); -int sem_trywait(sem_t* sem); -int sem_wait(sem_t* sem); +int sem_destroy(sem_t* sem); +int sem_getvalue(sem_t* sem, int* value); +int sem_init(sem_t* sem, int pshared, unsigned value); +int sem_post(sem_t* sem); +int sem_timedwait(sem_t* sem, const struct timespec* abstime); +int sem_trywait(sem_t* sem); +int sem_wait(sem_t* sem); #ifdef __cplusplus } diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/signal.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/signal.h index 2c7892e..6caf559 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/signal.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/signal.h @@ -39,7 +39,7 @@ /* compiler vendor check */ #ifndef __GNUC__ - #error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. +#error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. #endif #include "sys/types.h" @@ -63,7 +63,6 @@ extern "C" { #define SIGEV_THREAD 3 #endif - /* ************************************************************************* * signal types @@ -75,8 +74,8 @@ extern "C" { */ union sigval { - int sival_int; /* integer signal value */ - void* sival_ptr; /* pointer signal value */ + int sival_int; /* integer signal value */ + void* sival_ptr; /* pointer signal value */ }; /* Deprecated. This typedef is for compatibility with old SDKs. It is @@ -90,12 +89,12 @@ typedef union sigval sigval; */ struct sigevent { - int sigev_notify; /* notification type */ - int sigev_signo; /* signal number */ - union sigval sigev_value; /* signal value */ + int sigev_notify; /* notification type */ + int sigev_signo; /* signal number */ + union sigval sigev_value; /* signal value */ - void (*sigev_notify_function)(union sigval val); /* notify function */ - pthread_attr_t* sigev_notify_attributes; /* notify attributes */ + void (*sigev_notify_function)(union sigval val); /* notify function */ + pthread_attr_t* sigev_notify_attributes; /* notify attributes */ }; /* Deprecated. This typedef is for compatibility with old SDKs. It is @@ -104,7 +103,6 @@ struct sigevent */ typedef struct sigevent sigevent; - #ifdef __cplusplus } #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/sys/_internal.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/sys/_internal.h index 0e75ed8..60d3993 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/sys/_internal.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/sys/_internal.h @@ -40,10 +40,10 @@ /* compiler vendor check */ #ifndef __GNUC__ - #error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. +#error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. #endif -#include /* C99 standard integer types */ +#include /* C99 standard integer types */ #ifdef __cplusplus extern "C" { @@ -66,94 +66,93 @@ struct Opaque_Struct__; struct Opaque_QueueElem { - struct Opaque_QueueElem* volatile next; - struct Opaque_QueueElem* volatile prev; + struct Opaque_QueueElem* volatile next; + struct Opaque_QueueElem* volatile prev; }; struct Opaque_QueueStruct { - struct Opaque_QueueElem __f0; - struct Opaque_Struct__* __f1; + struct Opaque_QueueElem __f0; + struct Opaque_Struct__* __f1; }; struct sysbios_Semaphore { - struct Opaque_Struct__* __f0; - unsigned int __f1; - enum Opaque_Mode __f2; - volatile uint_least16_t __f3; - struct Opaque_QueueStruct __f4; - struct Opaque_Struct__* __f5; + struct Opaque_Struct__* __f0; + unsigned int __f1; + enum Opaque_Mode __f2; + volatile uint_least16_t __f3; + struct Opaque_QueueStruct __f4; + struct Opaque_Struct__* __f5; }; struct freertos_Semaphore { - void* __f0; + void* __f0; }; struct sysbios_Barrier { - struct sysbios_Semaphore sem; - int count; - int pendCount; + struct sysbios_Semaphore sem; + int count; + int pendCount; }; struct freertos_Barrier { - int count; - int pendCount; - struct Opaque_Struct__* waitList; - struct Opaque_Struct__* last; + int count; + int pendCount; + struct Opaque_Struct__* waitList; + struct Opaque_Struct__* last; }; struct sysbios_Mutex { - struct Opaque_Struct__* owner; - int lockCnt; - int type; - struct sysbios_Semaphore sem; - struct Opaque_Struct__* mpo; + struct Opaque_Struct__* owner; + int lockCnt; + int type; + struct sysbios_Semaphore sem; + struct Opaque_Struct__* mpo; }; struct freertos_Mutex { - int protocol; - void* owner; - int type; - void* sem; /* struct freertos_Semaphore */ + int protocol; + void* owner; + int type; + void* sem; /* struct freertos_Semaphore */ }; struct sysbios_RWLock { - struct sysbios_Semaphore sem; - struct sysbios_Semaphore readSem; - int activeReaderCnt; - int blockedReaderCnt; - void* owner; + struct sysbios_Semaphore sem; + struct sysbios_Semaphore readSem; + int activeReaderCnt; + int blockedReaderCnt; + void* owner; }; struct freertos_RWLock { - struct freertos_Semaphore sem; - struct freertos_Semaphore readSem; - int activeReaderCnt; - int blockedReaderCnt; - void* owner; + struct freertos_Semaphore sem; + struct freertos_Semaphore readSem; + int activeReaderCnt; + int blockedReaderCnt; + void* owner; }; struct sysbios_Cond { - struct Opaque_QueueStruct waitList; - uint32_t clockId; + struct Opaque_QueueStruct waitList; + uint32_t clockId; }; struct freertos_Cond { - struct Opaque_QueueElem waitList; - uint32_t clockId; + struct Opaque_QueueElem waitList; + uint32_t clockId; }; - #ifdef __cplusplus } #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/sys/types.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/sys/types.h index 03e3363..0373f2d 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/sys/types.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/sys/types.h @@ -39,12 +39,12 @@ /* compiler vendor check */ #ifndef __GNUC__ - #error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. +#error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. #endif +#include "_internal.h" #include #include -#include "_internal.h" /* include compiler sys/types.h */ #include <../include/sys/types.h> @@ -84,11 +84,11 @@ extern "C" { */ typedef struct pthread_attr_t { - int priority; - void* stack; - size_t stacksize; - size_t guardsize; - int detachstate; + int priority; + void* stack; + size_t stacksize; + size_t guardsize; + int detachstate; } pthread_attr_t; typedef uint32_t pthread_barrierattr_t; @@ -98,9 +98,9 @@ typedef void* pthread_key_t; typedef struct pthread_mutexattr_t { - int type; - int protocol; - int prioceiling; + int type; + int protocol; + int prioceiling; } pthread_mutexattr_t; typedef uint32_t pthread_rwlockattr_t; @@ -109,37 +109,37 @@ typedef void* pthread_t; typedef union { - struct sysbios_Barrier sysbios; - struct freertos_Barrier freertos; + struct sysbios_Barrier sysbios; + struct freertos_Barrier freertos; } pthread_barrier_t; typedef union { - struct sysbios_Cond sysbios; - struct freertos_Cond freertos; + struct sysbios_Cond sysbios; + struct freertos_Cond freertos; } pthread_cond_t; typedef union { - struct sysbios_Mutex sysbios; - struct freertos_Mutex freertos; + struct sysbios_Mutex sysbios; + struct freertos_Mutex freertos; } pthread_mutex_t; typedef uint32_t pthread_once_t; typedef union { - struct sysbios_RWLock sysbios; - struct freertos_RWLock freertos; + struct sysbios_RWLock sysbios; + struct freertos_RWLock freertos; } pthread_rwlock_t; struct _pthread_cleanup_context { - pthread_t thread; - void (*fxn)(void*); - void* arg; - int cancelType; - struct _pthread_cleanup_context* next; + pthread_t thread; + void (*fxn)(void*); + void* arg; + int cancelType; + struct _pthread_cleanup_context* next; }; #ifdef __cplusplus diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/time.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/time.h index acb38b1..2ff6f5b 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/time.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/time.h @@ -39,7 +39,7 @@ /* compiler vendor check */ #ifndef __GNUC__ - #error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. +#error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. #endif #include diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/unistd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/unistd.h index 697ba9d..90053f1 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/unistd.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/gcc/unistd.h @@ -39,7 +39,7 @@ /* compiler vendor check */ #ifndef __GNUC__ - #error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. +#error Incompatible compiler: use this include path (.../ti/posix/gcc) only with a GNU compiler. You appear to be using a different compiler. #endif /* include compiler unistd.h */ diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/errno.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/errno.h index 9750662..a1cb185 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/errno.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/errno.h @@ -39,14 +39,14 @@ /* compiler vendor check */ #ifndef __IAR_SYSTEMS_ICC__ - #error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. #endif /* include toolchain's header file */ #if defined(__430_CORE__) || defined(__430X_CORE__) - #include <../inc/dlib/c/errno.h> +#include <../inc/dlib/c/errno.h> #else - #include <../inc/c/errno.h> +#include <../inc/c/errno.h> #endif #ifdef __cplusplus @@ -56,139 +56,139 @@ extern "C" { /* These are missing from errno.h Values match GNU ARM compiler. */ #ifndef EACCES -#define EACCES 13 +#define EACCES 13 #endif #ifndef EAGAIN -#define EAGAIN 11 +#define EAGAIN 11 #endif #ifndef EBADF -#define EBADF 9 +#define EBADF 9 #endif #ifndef EBUSY -#define EBUSY 16 +#define EBUSY 16 #endif #ifndef EDEADLK -#define EDEADLK 45 +#define EDEADLK 45 #endif #ifndef EEXIST -#define EEXIST 17 +#define EEXIST 17 #endif #ifndef EFAULT -#define EFAULT 14 +#define EFAULT 14 #endif #ifndef EINVAL -#define EINVAL 22 +#define EINVAL 22 #endif #ifndef EMSGSIZE -#define EMSGSIZE 122 +#define EMSGSIZE 122 #endif #ifndef ENFILE -#define ENFILE 23 +#define ENFILE 23 #endif #ifndef ENOMEM -#define ENOMEM 12 +#define ENOMEM 12 #endif #ifndef ENOENT -#define ENOENT 2 +#define ENOENT 2 #endif #ifndef ENOSPC -#define ENOSPC 28 +#define ENOSPC 28 #endif #ifndef ENOSYS -#define ENOSYS 89 +#define ENOSYS 89 #endif #ifndef ENOTSUP -#define ENOTSUP 48 +#define ENOTSUP 48 #endif #ifndef EPERM -#define EPERM 1 +#define EPERM 1 #endif #ifndef ETIMEDOUT -#define ETIMEDOUT 145 +#define ETIMEDOUT 145 #endif #ifndef EADDRINUSE -#define EADDRINUSE 112 +#define EADDRINUSE 112 #endif #ifndef EADDRNOTAVAIL -#define EADDRNOTAVAIL 125 +#define EADDRNOTAVAIL 125 #endif #ifndef EAFNOSUPPORT -#define EAFNOSUPPORT 106 +#define EAFNOSUPPORT 106 #endif #ifndef ECONNREFUSED -#define ECONNREFUSED 111 +#define ECONNREFUSED 111 #endif #ifndef EDESTADDRREQ -#define EDESTADDRREQ 121 +#define EDESTADDRREQ 121 #endif #ifndef EISCONN -#define EISCONN 127 +#define EISCONN 127 #endif #ifndef ENETDOWN -#define ENETDOWN 115 +#define ENETDOWN 115 #endif #ifndef ENETUNREACH -#define ENETUNREACH 114 +#define ENETUNREACH 114 #endif #ifndef ENOBUFS -#define ENOBUFS 105 +#define ENOBUFS 105 #endif #ifndef ENOPROTOOPT -#define ENOPROTOOPT 109 +#define ENOPROTOOPT 109 #endif #ifndef ENOTCONN -#define ENOTCONN 128 +#define ENOTCONN 128 #endif #ifndef EOPNOTSUPP -#define EOPNOTSUPP 95 +#define EOPNOTSUPP 95 #endif #ifndef EOVERFLOW -#define EOVERFLOW 139 +#define EOVERFLOW 139 #endif #ifndef EPROTONOSUPPORT -#define EPROTONOSUPPORT 123 +#define EPROTONOSUPPORT 123 #endif #ifndef EPROTOTYPE -#define EPROTOTYPE 107 +#define EPROTOTYPE 107 #endif #ifndef EWOULDBLOCK -#define EWOULDBLOCK EAGAIN +#define EWOULDBLOCK EAGAIN #endif /* custom error codes */ -#define EFREERTOS 2001 /* FreeRTOS function failure */ +#define EFREERTOS 2001 /* FreeRTOS function failure */ #ifdef __cplusplus } diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/mqueue.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/mqueue.h index 649c864..6f2886b 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/mqueue.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/mqueue.h @@ -39,14 +39,14 @@ /* compiler vendor check */ #ifndef __IAR_SYSTEMS_ICC__ - #error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. #endif #include #include -#include "time.h" #include "sys/types.h" +#include "time.h" #ifdef __cplusplus extern "C" { @@ -60,11 +60,11 @@ typedef void* mqd_t; */ struct mq_attr { - long mq_flags; /* Message queue description flags: 0 or O_NONBLOCK. + long mq_flags; /* Message queue description flags: 0 or O_NONBLOCK. Initialized from oflag argument of mq_open(). */ - long mq_maxmsg; /* Maximum number of messages on queue. */ - long mq_msgsize; /* Maximum message size. */ - long mq_curmsgs; /* Number of messages currently queued. */ + long mq_maxmsg; /* Maximum number of messages on queue. */ + long mq_msgsize; /* Maximum message size. */ + long mq_curmsgs; /* Number of messages currently queued. */ }; /* Deprecated. This typedef is for compatibility with old SDKs. It is @@ -74,14 +74,14 @@ struct mq_attr typedef struct mq_attr mq_attr; /* For mq_open() */ -#define O_CREAT 0x200 /* TODO: sys/fcntl.h? */ -#define O_EXCL 0x0800 /* Error on open if queue exists */ -#define O_RDONLY 0 -#define O_WRONLY 1 -#define O_RDWR 2 -#define O_NONBLOCK 0x4000 /* Fail with EAGAIN if resources unavailable */ +#define O_CREAT 0x200 /* TODO: sys/fcntl.h? */ +#define O_EXCL 0x0800 /* Error on open if queue exists */ +#define O_RDONLY 0 +#define O_WRONLY 1 +#define O_RDWR 2 +#define O_NONBLOCK 0x4000 /* Fail with EAGAIN if resources unavailable */ -typedef uint32_t mode_t; /* TODO: sys/stat.h? */ +typedef uint32_t mode_t; /* TODO: sys/stat.h? */ extern int mq_close(mqd_t mqdes); extern int mq_getattr(mqd_t mqdes, struct mq_attr* mqstat); diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/pthread.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/pthread.h index 5114626..8408905 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/pthread.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/pthread.h @@ -39,14 +39,14 @@ /* compiler vendor check */ #ifndef __IAR_SYSTEMS_ICC__ - #error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. #endif #include +#include "sched.h" #include "sys/types.h" #include "time.h" -#include "sched.h" #ifdef __cplusplus extern "C" { @@ -54,13 +54,13 @@ extern "C" { #define PTHREAD_BARRIER_SERIAL_THREAD -1 -#define PTHREAD_CREATE_JOINABLE 0 -#define PTHREAD_CREATE_DETACHED 1 +#define PTHREAD_CREATE_JOINABLE 0 +#define PTHREAD_CREATE_DETACHED 1 /* PThread cancellation */ -#define PTHREAD_CANCEL_ENABLE 0 -#define PTHREAD_CANCEL_DISABLE 1 -#define PTHREAD_CANCELED ((void *) -1) +#define PTHREAD_CANCEL_ENABLE 0 +#define PTHREAD_CANCEL_DISABLE 1 +#define PTHREAD_CANCELED ((void*)-1) /* * Mutex attributes - type @@ -72,10 +72,10 @@ extern "C" { * error is returned. * */ -#define PTHREAD_MUTEX_NORMAL 0 -#define PTHREAD_MUTEX_RECURSIVE 1 -#define PTHREAD_MUTEX_ERRORCHECK 2 -#define PTHREAD_MUTEX_DEFAULT PTHREAD_MUTEX_NORMAL +#define PTHREAD_MUTEX_NORMAL 0 +#define PTHREAD_MUTEX_RECURSIVE 1 +#define PTHREAD_MUTEX_ERRORCHECK 2 +#define PTHREAD_MUTEX_DEFAULT PTHREAD_MUTEX_NORMAL /* Passed to pthread_once() */ #define PTHREAD_ONCE_INIT 0 @@ -91,11 +91,11 @@ extern "C" { * owned (regardless of whether or not other threads are blocked on * any of these mutexes). */ -#define PTHREAD_PRIO_NONE 0 -#define PTHREAD_PRIO_INHERIT 1 -#define PTHREAD_PRIO_PROTECT 2 +#define PTHREAD_PRIO_NONE 0 +#define PTHREAD_PRIO_INHERIT 1 +#define PTHREAD_PRIO_PROTECT 2 -#define PTHREAD_PROCESS_PRIVATE 0 +#define PTHREAD_PROCESS_PRIVATE 0 /* ************************************************************************* @@ -140,147 +140,149 @@ extern void _pthread_cleanup_pop(struct _pthread_cleanup_context* context, extern void _pthread_cleanup_push(struct _pthread_cleanup_context* context, void (*fxn)(void*), void* arg); -#define pthread_cleanup_push(fxn, arg) \ - do { \ +#define pthread_cleanup_push(fxn, arg) \ + do \ + { \ struct _pthread_cleanup_context _pthread_clup_ctx; \ - _pthread_cleanup_push(&_pthread_clup_ctx, (fxn), (arg)) + _pthread_cleanup_push(&_pthread_clup_ctx, (fxn), (arg)) -#define pthread_cleanup_pop(execute) \ +#define pthread_cleanup_pop(execute) \ _pthread_cleanup_pop(&_pthread_clup_ctx, (execute)); \ - } while (0) + } \ + while (0) - extern int pthread_create(pthread_t* newthread, const pthread_attr_t* attr, - void* (*startroutine)(void*), void* arg); - extern int pthread_detach(pthread_t pthread); - extern int pthread_equal(pthread_t pt1, pthread_t pt2); - extern void pthread_exit(void* ptr); - extern int pthread_getschedparam(pthread_t thread, int* policy, - struct sched_param* param); - extern int pthread_join(pthread_t th, void** thread_return); - extern int pthread_once(pthread_once_t* once, void (*initFxn)(void)); - extern pthread_t pthread_self(void); - extern int pthread_setcancelstate(int state, int* oldstate); - extern int pthread_setschedparam(pthread_t pthread, int policy, - const struct sched_param* param); +extern int pthread_create(pthread_t* newthread, const pthread_attr_t* attr, + void* (*startroutine)(void*), void* arg); +extern int pthread_detach(pthread_t pthread); +extern int pthread_equal(pthread_t pt1, pthread_t pt2); +extern void pthread_exit(void* ptr); +extern int pthread_getschedparam(pthread_t thread, int* policy, + struct sched_param* param); +extern int pthread_join(pthread_t th, void** thread_return); +extern int pthread_once(pthread_once_t* once, void (*initFxn)(void)); +extern pthread_t pthread_self(void); +extern int pthread_setcancelstate(int state, int* oldstate); +extern int pthread_setschedparam(pthread_t pthread, int policy, + const struct sched_param* param); - /* - ************************************************************************* - * pthread_barrierattr - ************************************************************************* - */ - extern int pthread_barrierattr_destroy(pthread_barrierattr_t* attr); - extern int pthread_barrierattr_init(pthread_barrierattr_t* attr); +/* + ************************************************************************* + * pthread_barrierattr + ************************************************************************* + */ +extern int pthread_barrierattr_destroy(pthread_barrierattr_t* attr); +extern int pthread_barrierattr_init(pthread_barrierattr_t* attr); - /* - ************************************************************************* - * pthread_barrier - ************************************************************************* - */ - extern int pthread_barrier_destroy(pthread_barrier_t* barrier); - extern int pthread_barrier_init(pthread_barrier_t* barrier, - const pthread_barrierattr_t* attr, unsigned count); - extern int pthread_barrier_wait(pthread_barrier_t* barrier); +/* + ************************************************************************* + * pthread_barrier + ************************************************************************* + */ +extern int pthread_barrier_destroy(pthread_barrier_t* barrier); +extern int pthread_barrier_init(pthread_barrier_t* barrier, + const pthread_barrierattr_t* attr, unsigned count); +extern int pthread_barrier_wait(pthread_barrier_t* barrier); - /* - ************************************************************************* - * pthread_condattr - ************************************************************************* - */ - extern int pthread_condattr_destroy(pthread_condattr_t* attr); - extern int pthread_condattr_getclock(const pthread_condattr_t* attr, - clockid_t* clock_id); - extern int pthread_condattr_init(pthread_condattr_t* attr); - extern int pthread_condattr_setclock(pthread_condattr_t* attr, - clockid_t clock_id); +/* + ************************************************************************* + * pthread_condattr + ************************************************************************* + */ +extern int pthread_condattr_destroy(pthread_condattr_t* attr); +extern int pthread_condattr_getclock(const pthread_condattr_t* attr, + clockid_t* clock_id); +extern int pthread_condattr_init(pthread_condattr_t* attr); +extern int pthread_condattr_setclock(pthread_condattr_t* attr, + clockid_t clock_id); - /* - ************************************************************************* - * pthread_cond - ************************************************************************* - */ - extern int pthread_cond_broadcast(pthread_cond_t* cond); - extern int pthread_cond_destroy(pthread_cond_t* cond); - extern int pthread_cond_init(pthread_cond_t* cond, - const pthread_condattr_t* attr); - extern int pthread_cond_signal(pthread_cond_t* cond); - extern int pthread_cond_timedwait(pthread_cond_t* cond, pthread_mutex_t* mutex, - const struct timespec* abstime); - extern int pthread_cond_wait(pthread_cond_t* cond, pthread_mutex_t* mutex); +/* + ************************************************************************* + * pthread_cond + ************************************************************************* + */ +extern int pthread_cond_broadcast(pthread_cond_t* cond); +extern int pthread_cond_destroy(pthread_cond_t* cond); +extern int pthread_cond_init(pthread_cond_t* cond, + const pthread_condattr_t* attr); +extern int pthread_cond_signal(pthread_cond_t* cond); +extern int pthread_cond_timedwait(pthread_cond_t* cond, pthread_mutex_t* mutex, + const struct timespec* abstime); +extern int pthread_cond_wait(pthread_cond_t* cond, pthread_mutex_t* mutex); - /* - ************************************************************************* - * pthread_key - ************************************************************************* - */ - extern int pthread_key_create(pthread_key_t* key, void (*destructor)(void*)); - extern int pthread_key_delete(pthread_key_t key); - extern void* pthread_getspecific(pthread_key_t key); - extern int pthread_setspecific(pthread_key_t key, const void* value); +/* + ************************************************************************* + * pthread_key + ************************************************************************* + */ +extern int pthread_key_create(pthread_key_t* key, void (*destructor)(void*)); +extern int pthread_key_delete(pthread_key_t key); +extern void* pthread_getspecific(pthread_key_t key); +extern int pthread_setspecific(pthread_key_t key, const void* value); - /* - ************************************************************************* - * pthread_mutexattr - ************************************************************************* - */ - extern int pthread_mutexattr_destroy(pthread_mutexattr_t* attr); - extern int pthread_mutexattr_gettype(const pthread_mutexattr_t* attr, - int* type); - extern int pthread_mutexattr_getprioceiling(const pthread_mutexattr_t* attr, - int* prioceiling); - extern int pthread_mutexattr_getprotocol(const pthread_mutexattr_t* attr, - int* protocol); - extern int pthread_mutexattr_init(pthread_mutexattr_t* attr); - extern int pthread_mutexattr_setprioceiling(pthread_mutexattr_t* attr, - int prioceiling); - extern int pthread_mutexattr_setprotocol(pthread_mutexattr_t* attr, - int protocol); - extern int pthread_mutexattr_settype(pthread_mutexattr_t* attr, int type); - - /* - ************************************************************************* - * pthread_mutex - ************************************************************************* - */ - extern int pthread_mutex_destroy(pthread_mutex_t* mutex); - extern int pthread_mutex_getprioceiling(const pthread_mutex_t* mutex, +/* + ************************************************************************* + * pthread_mutexattr + ************************************************************************* + */ +extern int pthread_mutexattr_destroy(pthread_mutexattr_t* attr); +extern int pthread_mutexattr_gettype(const pthread_mutexattr_t* attr, + int* type); +extern int pthread_mutexattr_getprioceiling(const pthread_mutexattr_t* attr, int* prioceiling); - extern int pthread_mutex_init(pthread_mutex_t* mutex, - const pthread_mutexattr_t* attr); - extern int pthread_mutex_lock(pthread_mutex_t* mutex); - extern int pthread_mutex_setprioceiling(pthread_mutex_t* mutex, - int prioceiling, int* oldceiling); - extern int pthread_mutex_timedlock(pthread_mutex_t* mutex, - const struct timespec* abstime); - extern int pthread_mutex_trylock(pthread_mutex_t* mutex); +extern int pthread_mutexattr_getprotocol(const pthread_mutexattr_t* attr, + int* protocol); +extern int pthread_mutexattr_init(pthread_mutexattr_t* attr); +extern int pthread_mutexattr_setprioceiling(pthread_mutexattr_t* attr, + int prioceiling); +extern int pthread_mutexattr_setprotocol(pthread_mutexattr_t* attr, + int protocol); +extern int pthread_mutexattr_settype(pthread_mutexattr_t* attr, int type); - extern int pthread_mutex_unlock(pthread_mutex_t* mutex); +/* + ************************************************************************* + * pthread_mutex + ************************************************************************* + */ +extern int pthread_mutex_destroy(pthread_mutex_t* mutex); +extern int pthread_mutex_getprioceiling(const pthread_mutex_t* mutex, + int* prioceiling); +extern int pthread_mutex_init(pthread_mutex_t* mutex, + const pthread_mutexattr_t* attr); +extern int pthread_mutex_lock(pthread_mutex_t* mutex); +extern int pthread_mutex_setprioceiling(pthread_mutex_t* mutex, + int prioceiling, int* oldceiling); +extern int pthread_mutex_timedlock(pthread_mutex_t* mutex, + const struct timespec* abstime); +extern int pthread_mutex_trylock(pthread_mutex_t* mutex); - /* - ************************************************************************* - * pthread_rwlockattr - ************************************************************************* - */ - extern int pthread_rwlockattr_destroy(pthread_rwlockattr_t* attr); - extern int pthread_rwlockattr_init(pthread_rwlockattr_t* attr); +extern int pthread_mutex_unlock(pthread_mutex_t* mutex); - /* - ************************************************************************* - * pthread_rwlock - ************************************************************************* - */ - extern int pthread_rwlock_destroy(pthread_rwlock_t* rwlock); - extern int pthread_rwlock_init(pthread_rwlock_t* rwlock, - const pthread_rwlockattr_t* attr); +/* + ************************************************************************* + * pthread_rwlockattr + ************************************************************************* + */ +extern int pthread_rwlockattr_destroy(pthread_rwlockattr_t* attr); +extern int pthread_rwlockattr_init(pthread_rwlockattr_t* attr); - extern int pthread_rwlock_rdlock(pthread_rwlock_t* rwlock); - extern int pthread_rwlock_timedrdlock(pthread_rwlock_t* rwlock, - const struct timespec* abstime); - extern int pthread_rwlock_timedwrlock(pthread_rwlock_t* rwlock, - const struct timespec* abstime); - extern int pthread_rwlock_tryrdlock(pthread_rwlock_t* rwlock); - extern int pthread_rwlock_trywrlock(pthread_rwlock_t* rwlock); - extern int pthread_rwlock_unlock(pthread_rwlock_t* rwlock); - extern int pthread_rwlock_wrlock(pthread_rwlock_t* rwlock); +/* + ************************************************************************* + * pthread_rwlock + ************************************************************************* + */ +extern int pthread_rwlock_destroy(pthread_rwlock_t* rwlock); +extern int pthread_rwlock_init(pthread_rwlock_t* rwlock, + const pthread_rwlockattr_t* attr); + +extern int pthread_rwlock_rdlock(pthread_rwlock_t* rwlock); +extern int pthread_rwlock_timedrdlock(pthread_rwlock_t* rwlock, + const struct timespec* abstime); +extern int pthread_rwlock_timedwrlock(pthread_rwlock_t* rwlock, + const struct timespec* abstime); +extern int pthread_rwlock_tryrdlock(pthread_rwlock_t* rwlock); +extern int pthread_rwlock_trywrlock(pthread_rwlock_t* rwlock); +extern int pthread_rwlock_unlock(pthread_rwlock_t* rwlock); +extern int pthread_rwlock_wrlock(pthread_rwlock_t* rwlock); #ifdef __cplusplus } diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sched.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sched.h index 7e70879..b1dc865 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sched.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sched.h @@ -39,7 +39,7 @@ /* compiler vendor check */ #ifndef __IAR_SYSTEMS_ICC__ - #error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. #endif #include @@ -70,7 +70,7 @@ extern "C" { */ struct sched_param { - int sched_priority; /* Thread execution priority */ + int sched_priority; /* Thread execution priority */ }; /* diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/semaphore.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/semaphore.h index 8ea735b..f341a5c 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/semaphore.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/semaphore.h @@ -39,11 +39,11 @@ /* compiler vendor check */ #ifndef __IAR_SYSTEMS_ICC__ - #error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. #endif -#include #include "sys/_internal.h" +#include /* * Include definitions of timespec and clockid_t that would @@ -59,17 +59,17 @@ extern "C" { typedef union { - struct sysbios_Semaphore sysbios; - struct freertos_Semaphore freertos; + struct sysbios_Semaphore sysbios; + struct freertos_Semaphore freertos; } sem_t; -int sem_destroy(sem_t* sem); -int sem_getvalue(sem_t* sem, int* value); -int sem_init(sem_t* sem, int pshared, unsigned value); -int sem_post(sem_t* sem); -int sem_timedwait(sem_t* sem, const struct timespec* abstime); -int sem_trywait(sem_t* sem); -int sem_wait(sem_t* sem); +int sem_destroy(sem_t* sem); +int sem_getvalue(sem_t* sem, int* value); +int sem_init(sem_t* sem, int pshared, unsigned value); +int sem_post(sem_t* sem); +int sem_timedwait(sem_t* sem, const struct timespec* abstime); +int sem_trywait(sem_t* sem); +int sem_wait(sem_t* sem); #ifdef __cplusplus } diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/signal.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/signal.h index ffc954d..c56ef08 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/signal.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/signal.h @@ -39,16 +39,16 @@ /* compiler vendor check */ #ifndef __IAR_SYSTEMS_ICC__ - #error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. #endif #include "sys/types.h" /* include toolchain's header file */ #if defined(__430_CORE__) || defined(__430X_CORE__) - #include <../inc/dlib/c/signal.h> +#include <../inc/dlib/c/signal.h> #else - #include <../inc/c/signal.h> +#include <../inc/c/signal.h> #endif #ifdef __cplusplus @@ -67,7 +67,6 @@ extern "C" { #define SIGEV_THREAD 3 #endif - /* ************************************************************************* * signal types @@ -79,8 +78,8 @@ extern "C" { */ union sigval { - int sival_int; /* integer signal value */ - void* sival_ptr; /* pointer signal value */ + int sival_int; /* integer signal value */ + void* sival_ptr; /* pointer signal value */ }; /* Deprecated. This typedef is for compatibility with old SDKs. It is @@ -94,12 +93,12 @@ typedef union sigval sigval; */ struct sigevent { - int sigev_notify; /* notification type */ - int sigev_signo; /* signal number */ - union sigval sigev_value; /* signal value */ + int sigev_notify; /* notification type */ + int sigev_signo; /* signal number */ + union sigval sigev_value; /* signal value */ - void (*sigev_notify_function)(union sigval val); /* notify function */ - pthread_attr_t* sigev_notify_attributes; /* notify attributes */ + void (*sigev_notify_function)(union sigval val); /* notify function */ + pthread_attr_t* sigev_notify_attributes; /* notify attributes */ }; /* Deprecated. This typedef is for compatibility with old SDKs. It is @@ -108,7 +107,6 @@ struct sigevent */ typedef struct sigevent sigevent; - #ifdef __cplusplus } #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sys/_internal.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sys/_internal.h index 004673a..c8ce153 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sys/_internal.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sys/_internal.h @@ -40,10 +40,10 @@ /* compiler vendor check */ #ifndef __IAR_SYSTEMS_ICC__ - #error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. #endif -#include /* C99 standard integer types */ +#include /* C99 standard integer types */ #ifdef __cplusplus extern "C" { @@ -66,94 +66,93 @@ struct Opaque_Struct__; struct Opaque_QueueElem { - struct Opaque_QueueElem* volatile next; - struct Opaque_QueueElem* volatile prev; + struct Opaque_QueueElem* volatile next; + struct Opaque_QueueElem* volatile prev; }; struct Opaque_QueueStruct { - struct Opaque_QueueElem __f0; - struct Opaque_Struct__* __f1; + struct Opaque_QueueElem __f0; + struct Opaque_Struct__* __f1; }; struct sysbios_Semaphore { - struct Opaque_Struct__* __f0; - unsigned int __f1; - enum Opaque_Mode __f2; - volatile uint_least16_t __f3; - struct Opaque_QueueStruct __f4; - struct Opaque_Struct__* __f5; + struct Opaque_Struct__* __f0; + unsigned int __f1; + enum Opaque_Mode __f2; + volatile uint_least16_t __f3; + struct Opaque_QueueStruct __f4; + struct Opaque_Struct__* __f5; }; struct freertos_Semaphore { - void* __f0; + void* __f0; }; struct sysbios_Barrier { - struct sysbios_Semaphore sem; - int count; - int pendCount; + struct sysbios_Semaphore sem; + int count; + int pendCount; }; struct freertos_Barrier { - int count; - int pendCount; - struct Opaque_Struct__* waitList; - struct Opaque_Struct__* last; + int count; + int pendCount; + struct Opaque_Struct__* waitList; + struct Opaque_Struct__* last; }; struct sysbios_Mutex { - struct Opaque_Struct__* owner; - int lockCnt; - int type; - struct sysbios_Semaphore sem; - struct Opaque_Struct__* mpo; + struct Opaque_Struct__* owner; + int lockCnt; + int type; + struct sysbios_Semaphore sem; + struct Opaque_Struct__* mpo; }; struct freertos_Mutex { - int protocol; - void* owner; - int type; - void* sem; /* struct freertos_Semaphore */ + int protocol; + void* owner; + int type; + void* sem; /* struct freertos_Semaphore */ }; struct sysbios_RWLock { - struct sysbios_Semaphore sem; - struct sysbios_Semaphore readSem; - int activeReaderCnt; - int blockedReaderCnt; - void* owner; + struct sysbios_Semaphore sem; + struct sysbios_Semaphore readSem; + int activeReaderCnt; + int blockedReaderCnt; + void* owner; }; struct freertos_RWLock { - struct freertos_Semaphore sem; - struct freertos_Semaphore readSem; - int activeReaderCnt; - int blockedReaderCnt; - void* owner; + struct freertos_Semaphore sem; + struct freertos_Semaphore readSem; + int activeReaderCnt; + int blockedReaderCnt; + void* owner; }; struct sysbios_Cond { - struct Opaque_QueueStruct waitList; - uint32_t clockId; + struct Opaque_QueueStruct waitList; + uint32_t clockId; }; struct freertos_Cond { - struct Opaque_QueueElem waitList; - uint32_t clockId; + struct Opaque_QueueElem waitList; + uint32_t clockId; }; - #ifdef __cplusplus } #endif diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sys/time.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sys/time.h index 373154a..cd659fb 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sys/time.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sys/time.h @@ -39,17 +39,17 @@ /* compiler vendor check */ #ifndef __IAR_SYSTEMS_ICC__ - #error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. #endif -#include #include +#include /* include compiler time.h */ #if defined(__430_CORE__) || defined(__430X_CORE__) - #include <../inc/dlib/c/time.h> +#include <../inc/dlib/c/time.h> #else - #include <../inc/c/time.h> +#include <../inc/c/time.h> #endif #include "types.h" @@ -60,8 +60,8 @@ extern "C" { struct timeval { - time_t tv_sec; - suseconds_t tv_usec; + time_t tv_sec; + suseconds_t tv_usec; }; #ifdef __cplusplus diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sys/types.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sys/types.h index 36ff4c8..ee23963 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sys/types.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/sys/types.h @@ -39,12 +39,12 @@ /* compiler vendor check */ #ifndef __IAR_SYSTEMS_ICC__ - #error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. #endif +#include "_internal.h" #include #include -#include "_internal.h" #ifdef __cplusplus extern "C" { @@ -80,7 +80,6 @@ typedef unsigned short uid_t; #include <../inc/c/time.h> #endif - /* ************************************************************************* * posix types @@ -92,11 +91,11 @@ typedef unsigned short uid_t; */ typedef struct pthread_attr_t { - int priority; - void* stack; - size_t stacksize; - size_t guardsize; - int detachstate; + int priority; + void* stack; + size_t stacksize; + size_t guardsize; + int detachstate; } pthread_attr_t; typedef uint32_t pthread_barrierattr_t; @@ -106,9 +105,9 @@ typedef void* pthread_key_t; typedef struct pthread_mutexattr_t { - int type; - int protocol; - int prioceiling; + int type; + int protocol; + int prioceiling; } pthread_mutexattr_t; typedef uint32_t pthread_rwlockattr_t; @@ -117,37 +116,37 @@ typedef void* pthread_t; typedef union { - struct sysbios_Barrier sysbios; - struct freertos_Barrier freertos; + struct sysbios_Barrier sysbios; + struct freertos_Barrier freertos; } pthread_barrier_t; typedef union { - struct sysbios_Cond sysbios; - struct freertos_Cond freertos; + struct sysbios_Cond sysbios; + struct freertos_Cond freertos; } pthread_cond_t; typedef union { - struct sysbios_Mutex sysbios; - struct freertos_Mutex freertos; + struct sysbios_Mutex sysbios; + struct freertos_Mutex freertos; } pthread_mutex_t; typedef uint32_t pthread_once_t; typedef union { - struct sysbios_RWLock sysbios; - struct freertos_RWLock freertos; + struct sysbios_RWLock sysbios; + struct freertos_RWLock freertos; } pthread_rwlock_t; struct _pthread_cleanup_context { - pthread_t thread; - void (*fxn)(void*); - void* arg; - int cancelType; - struct _pthread_cleanup_context* next; + pthread_t thread; + void (*fxn)(void*); + void* arg; + int cancelType; + struct _pthread_cleanup_context* next; }; #ifdef __cplusplus diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/time.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/time.h index 9b73564..bbf0134 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/time.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/time.h @@ -39,7 +39,7 @@ /* compiler vendor check */ #ifndef __IAR_SYSTEMS_ICC__ - #error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. #endif #include @@ -47,12 +47,12 @@ /* include compiler time.h */ #if defined(__430_CORE__) || defined(__430X_CORE__) - #include <../inc/dlib/c/time.h> +#include <../inc/dlib/c/time.h> #else - /* disable IAR inline definition of time() */ - #define _NO_DEFINITIONS_IN_HEADER_FILES 1 - #include <../inc/c/time.h> +/* disable IAR inline definition of time() */ +#define _NO_DEFINITIONS_IN_HEADER_FILES 1 +#include <../inc/c/time.h> #endif #include "signal.h" @@ -90,8 +90,8 @@ extern "C" { struct itimerspec { - struct timespec it_interval; /* Timer interval */ - struct timespec it_value; /* Timer expiration */ + struct timespec it_interval; /* Timer interval */ + struct timespec it_value; /* Timer expiration */ }; /* diff --git a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/unistd.h b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/unistd.h index ebcfc93..a1766c0 100644 --- a/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/unistd.h +++ b/examples/knx-cc1310/coresdk_cc13xx_cc26xx/source/ti/posix/iar/unistd.h @@ -39,7 +39,7 @@ /* compiler vendor check */ #ifndef __IAR_SYSTEMS_ICC__ - #error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. +#error Incompatible compiler: use this include path (.../ti/posix/iar) only with an IAR compiler. You appear to be using a different compiler. #endif #include "sys/types.h" diff --git a/examples/knx-cc1310/smartrf_settings/smartrf_settings.h b/examples/knx-cc1310/smartrf_settings/smartrf_settings.h index c13c568..4a8938a 100644 --- a/examples/knx-cc1310/smartrf_settings/smartrf_settings.h +++ b/examples/knx-cc1310/smartrf_settings/smartrf_settings.h @@ -9,9 +9,9 @@ //********************************************************************************* #include -#include DeviceFamily_constructPath(driverlib/rf_mailbox.h) -#include DeviceFamily_constructPath(driverlib/rf_common_cmd.h) -#include DeviceFamily_constructPath(driverlib/rf_prop_cmd.h) +#include DeviceFamily_constructPath(driverlib / rf_mailbox.h) +#include DeviceFamily_constructPath(driverlib / rf_common_cmd.h) +#include DeviceFamily_constructPath(driverlib / rf_prop_cmd.h) #include // RF Core TX power diff --git a/examples/knx-linux-coupler/fdsk.cpp b/examples/knx-linux-coupler/fdsk.cpp index d732995..158ea6f 100644 --- a/examples/knx-linux-coupler/fdsk.cpp +++ b/examples/knx-linux-coupler/fdsk.cpp @@ -4,10 +4,9 @@ // CRC-4 generator polynom: 10011 (x^4+x+1) const uint8_t FdskCalculator::crc4_tab[16] = -{ - 0x0, 0x3, 0x6, 0x5, 0xc, 0xf, 0xa, 0x9, - 0xb, 0x8, 0xd, 0xe, 0x7, 0x4, 0x1, 0x2 -}; + { + 0x0, 0x3, 0x6, 0x5, 0xc, 0xf, 0xa, 0x9, + 0xb, 0x8, 0xd, 0xe, 0x7, 0x4, 0x1, 0x2}; int FdskCalculator::snprintFdsk(char* str, int strSize, uint8_t* serialNumber, uint8_t* key) { @@ -132,7 +131,7 @@ int FdskCalculator::toBase32(uint8_t* in, long length, uint8_t*& out, bool usePa out = new uint8_t[result]; memcpy(out, temp, result); - delete [] temp; + delete[] temp; return result; } @@ -168,7 +167,6 @@ int FdskCalculator::fromBase32(uint8_t* in, long length, uint8_t*& out) ch = 0x42; } - // look up one base32 symbols: from 'A' to 'Z' or from 'a' to 'z' or from '2' to '7' if ((ch >= 0x41 && ch <= 0x5A) || (ch >= 0x61 && ch <= 0x7A)) { @@ -180,7 +178,7 @@ int FdskCalculator::fromBase32(uint8_t* in, long length, uint8_t*& out) } else { - delete [] temp; + delete[] temp; return 0; } @@ -198,8 +196,7 @@ int FdskCalculator::fromBase32(uint8_t* in, long length, uint8_t*& out) out = new uint8_t[result]; memcpy(out, temp, result); - delete [] temp; + delete[] temp; return result; } - diff --git a/examples/knx-linux-coupler/main.cpp b/examples/knx-linux-coupler/main.cpp index 33b644e..7b3a2cb 100644 --- a/examples/knx-linux-coupler/main.cpp +++ b/examples/knx-linux-coupler/main.cpp @@ -4,13 +4,13 @@ #include "knx/coupler/bau2920.h" #include "knx/bits.h" -#include -#include -#include -#include -#include #include +#include +#include +#include +#include #include +#include #include "fdsk.h" @@ -35,11 +35,11 @@ bool isSendHidReportPossible() } #if MASK_VERSION == 0x091A - KnxFacade knx; // IP/TP1 coupler +KnxFacade knx; // IP/TP1 coupler #elif MASK_VERSION == 0x2920 - KnxFacade knx; // TP1/RF coupler +KnxFacade knx; // TP1/RF coupler #else - #error Mask version not supported yet! +#error Mask version not supported yet! #endif void appLoop() @@ -70,8 +70,8 @@ int main(int argc, char** argv) { printf("main() start.\n"); - uint8_t serialNumber[] = { 0x00, 0xFA, 0x01, 0x02, 0x03, 0x04}; - uint8_t key[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F}; + uint8_t serialNumber[] = {0x00, 0xFA, 0x01, 0x02, 0x03, 0x04}; + uint8_t key[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F}; FdskCalculator calc; char fdskString[42]; // 6 * 6 chars + 5 dashes + nullbyte = 42 diff --git a/examples/knx-linux/fdsk.cpp b/examples/knx-linux/fdsk.cpp index d732995..158ea6f 100644 --- a/examples/knx-linux/fdsk.cpp +++ b/examples/knx-linux/fdsk.cpp @@ -4,10 +4,9 @@ // CRC-4 generator polynom: 10011 (x^4+x+1) const uint8_t FdskCalculator::crc4_tab[16] = -{ - 0x0, 0x3, 0x6, 0x5, 0xc, 0xf, 0xa, 0x9, - 0xb, 0x8, 0xd, 0xe, 0x7, 0x4, 0x1, 0x2 -}; + { + 0x0, 0x3, 0x6, 0x5, 0xc, 0xf, 0xa, 0x9, + 0xb, 0x8, 0xd, 0xe, 0x7, 0x4, 0x1, 0x2}; int FdskCalculator::snprintFdsk(char* str, int strSize, uint8_t* serialNumber, uint8_t* key) { @@ -132,7 +131,7 @@ int FdskCalculator::toBase32(uint8_t* in, long length, uint8_t*& out, bool usePa out = new uint8_t[result]; memcpy(out, temp, result); - delete [] temp; + delete[] temp; return result; } @@ -168,7 +167,6 @@ int FdskCalculator::fromBase32(uint8_t* in, long length, uint8_t*& out) ch = 0x42; } - // look up one base32 symbols: from 'A' to 'Z' or from 'a' to 'z' or from '2' to '7' if ((ch >= 0x41 && ch <= 0x5A) || (ch >= 0x61 && ch <= 0x7A)) { @@ -180,7 +178,7 @@ int FdskCalculator::fromBase32(uint8_t* in, long length, uint8_t*& out) } else { - delete [] temp; + delete[] temp; return 0; } @@ -198,8 +196,7 @@ int FdskCalculator::fromBase32(uint8_t* in, long length, uint8_t*& out) out = new uint8_t[result]; memcpy(out, temp, result); - delete [] temp; + delete[] temp; return result; } - diff --git a/examples/knx-linux/main.cpp b/examples/knx-linux/main.cpp index ffd2cd5..66d7b0c 100644 --- a/examples/knx-linux/main.cpp +++ b/examples/knx-linux/main.cpp @@ -4,17 +4,17 @@ #include "knx/rf/bau27B0.h" #include "knx/tp/bau07B0.h" -#include "knx/interface_object/group_object_table_object.h" #include "knx/bits.h" #include "knx/group_object/dpt/dpts.h" +#include "knx/interface_object/group_object_table_object.h" -#include -#include -#include -#include -#include #include +#include +#include +#include +#include #include +#include #include "fdsk.h" @@ -39,13 +39,13 @@ bool isSendHidReportPossible() } #if MASK_VERSION == 0x57B0 - KnxFacade knx; +KnxFacade knx; #elif MASK_VERSION == 0x27B0 - KnxFacade knx; +KnxFacade knx; #elif MASK_VERSION == 0x07B0 - KnxFacade knx; +KnxFacade knx; #else - #error Mask version not supported yet! +#error Mask version not supported yet! #endif long lastsend = 0; @@ -74,7 +74,6 @@ void measureTemp() float max = GO_MAX.value(); - if (currentValue > max) GO_MAX.value(currentValue); @@ -133,8 +132,8 @@ int main(int argc, char** argv) { LOGGER.info("main() start."); - uint8_t serialNumber[] = { 0x00, 0xFA, 0x01, 0x02, 0x03, 0x04}; - uint8_t key[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F}; + uint8_t serialNumber[] = {0x00, 0xFA, 0x01, 0x02, 0x03, 0x04}; + uint8_t key[] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F}; FdskCalculator calc; char fdskString[42]; // 6 * 6 chars + 5 dashes + nullbyte = 42 diff --git a/examples/knx-usb/src/main.cpp b/examples/knx-usb/src/main.cpp index 767aab7..c119891 100644 --- a/examples/knx-usb/src/main.cpp +++ b/examples/knx-usb/src/main.cpp @@ -1,17 +1,17 @@ -#include #include +#include #include /* * USB stuff -*/ + */ #define STRINGIFY(s) XSTRINGIFY(s) #define XSTRINGIFY(s) #s -#pragma message ("USB_VID=" STRINGIFY(USB_VID)) -#pragma message ("USB_PID=" STRINGIFY(USB_PID)) -#pragma message ("USB_MANUFACTURER=" STRINGIFY(USB_MANUFACTURER)) -#pragma message ("USB_PRODUCT=" STRINGIFY(USB_PRODUCT)) +#pragma message("USB_VID=" STRINGIFY(USB_VID)) +#pragma message("USB_PID=" STRINGIFY(USB_PID)) +#pragma message("USB_MANUFACTURER=" STRINGIFY(USB_MANUFACTURER)) +#pragma message("USB_PRODUCT=" STRINGIFY(USB_PRODUCT)) Adafruit_USBD_HID usb_hid; @@ -20,8 +20,8 @@ Adafruit_USBD_HID usb_hid; void setReportCallback(uint8_t report_id, hid_report_type_t report_type, uint8_t const* data, uint16_t bufSize) { // we don't use multiple report and report ID - (void) report_id; - (void) report_type; + (void)report_id; + (void)report_type; UsbTunnelInterface::receiveHidReport(data, bufSize); } @@ -39,7 +39,7 @@ bool isSendHidReportPossible() /* * KNX stuff -*/ + */ // create macros easy access to group objects #define goTemperature knx.getGroupObject(1) @@ -53,7 +53,7 @@ long lastsend = 0; /* * setup() -*/ + */ void setup(void) { Serial1.begin(115200); @@ -68,7 +68,7 @@ void setup(void) usb_hid.begin(); // wait until device mounted - while ( !USBDevice.mounted() ) + while (!USBDevice.mounted()) delay(1); println("KNX USB Interface enabled."); @@ -79,7 +79,6 @@ void setup(void) if (knx.individualAddress() == 0) knx.progMode(true); - if (knx.configured()) { cyclSend = knx.paramInt(0); @@ -93,7 +92,7 @@ void setup(void) /* * loop() -*/ + */ void loop(void) { // don't delay here to much. Otherwise you might lose packages or mess up the timing with ETS @@ -124,5 +123,4 @@ void loop(void) goTemperature.value(temp); goHumidity.value(humi); } - } diff --git a/examples/knxPython/knxmodule.cpp b/examples/knxPython/knxmodule.cpp index 5221617..78bfd80 100644 --- a/examples/knxPython/knxmodule.cpp +++ b/examples/knxPython/knxmodule.cpp @@ -1,23 +1,23 @@ -#include -#include #include +#include #include +#include namespace py = pybind11; #include +#include +#include #include -#include #include #include -#include +#include #include -#include #include -#include -#include #include +#include +#include #include #define LOGGER Logger::logger("knxmodule") @@ -44,10 +44,10 @@ static std::vector argv; struct StdStringCStrFunctor { - const char* operator() (const std::string& str) - { - return str.c_str(); - } + const char* operator()(const std::string& str) + { + return str.c_str(); + } }; static void init() @@ -72,7 +72,6 @@ static void init() platform = new LinuxPlatform(); platform->cmdLineArgs(argv.size(), const_cast(argv.data())); bau = new Bau57B0(*platform); - } static void Destroy() @@ -145,34 +144,30 @@ static bool Configured() return bau->configured(); } - PYBIND11_MODULE(knx, m) { - m.doc() = "wrapper for knx device lib"; // optional module docstring + m.doc() = "wrapper for knx device lib"; // optional module docstring m.def("Start", &Start, "Start knx handling thread."); m.def("Stop", &Stop, "Stop knx handling thread."); m.def("Destroy", &Destroy, "Free object allocated objects."); - m.def("ProgramMode", (bool(*)())&ProgramMode, "get programing mode active."); - m.def("ProgramMode", (bool(*)(bool))&ProgramMode, "Activate / deactivate programing mode."); - m.def("Configured", (bool(*)())&Configured, "get configured status."); + m.def("ProgramMode", (bool (*)()) & ProgramMode, "get programing mode active."); + m.def("ProgramMode", (bool (*)(bool)) & ProgramMode, "Activate / deactivate programing mode."); + m.def("Configured", (bool (*)()) & Configured, "get configured status."); m.def("ReadMemory", &ReadMemory, "read memory from flash file"); - m.def("FlashFilePath", []() - { + m.def("FlashFilePath", []() { if (!platform) init(); return platform->flashFilePath(); }); - m.def("FlashFilePath", [](std::string path) - { + m.def("FlashFilePath", [](std::string path) { if (!platform) init(); platform->flashFilePath(path); }); - m.def("GetGroupObject", [](uint16_t goNr) - { + m.def("GetGroupObject", [](uint16_t goNr) { LOGGER.info("GetGroupObject arg %d", goNr); LOGGER.info("GetGroupObject entrycount %d", bau->groupObjectTable().entryCount()); @@ -182,14 +177,11 @@ PYBIND11_MODULE(knx, m) if (goNr > bau->groupObjectTable().entryCount()) return (GroupObject*)nullptr; - return &bau->groupObjectTable().get(goNr); - }, py::return_value_policy::reference); - m.def("Callback", [](GroupObjectUpdatedHandler handler) - { + return &bau->groupObjectTable().get(goNr); }, py::return_value_policy::reference); + m.def("Callback", [](GroupObjectUpdatedHandler handler) { GroupObject::classCallback(handler); }); - m.def("Parameters", []() - { + m.def("Parameters", []() { uint8_t* data = bau->parameters().data(); if (data == nullptr) @@ -199,17 +191,10 @@ PYBIND11_MODULE(knx, m) }); py::class_(m, "GroupObject", py::dynamic_attr()) - .def(py::init()) - .def("asap", &GroupObject::asap) - .def("size", &GroupObject::valueSize) - .def_property("value", - [](GroupObject & go) - { - - return py::bytes((const char*)go.valueRef(), go.valueSize()); - }, - [](GroupObject & go, py::bytes bytesValue) - { + .def(py::init()) + .def("asap", &GroupObject::asap) + .def("size", &GroupObject::valueSize) + .def_property("value", [](GroupObject& go) { return py::bytes((const char*)go.valueRef(), go.valueSize()); }, [](GroupObject& go, py::bytes bytesValue) { const auto value = static_cast(bytesValue); if (value.length() != go.valueSize()) @@ -217,7 +202,5 @@ PYBIND11_MODULE(knx, m) auto valueRef = go.valueRef(); memcpy(valueRef, value.c_str(), go.valueSize()); - go.objectWritten(); - }); - + go.objectWritten(); }); } diff --git a/examples/knxPython/pybind11/tests/test_class.cpp b/examples/knxPython/pybind11/tests/test_class.cpp index 9001d86..eb89303 100644 --- a/examples/knxPython/pybind11/tests/test_class.cpp +++ b/examples/knxPython/pybind11/tests/test_class.cpp @@ -403,7 +403,7 @@ TEST_SUBMODULE(class_, m) { // [workaround(intel)] = default does not work here // Removing or defaulting this destructor results in linking errors with the Intel compiler // (in Debug builds only, tested with icpc (ICC) 2021.1 Beta 20200827) - ~PublicistB() override {}; // NOLINT(modernize-use-equals-default) + ~PublicistB() override{}; // NOLINT(modernize-use-equals-default) using ProtectedB::foo; using ProtectedB::get_self; using ProtectedB::void_foo; diff --git a/examples/knxPython/pybind11/tests/test_numpy_dtypes.cpp b/examples/knxPython/pybind11/tests/test_numpy_dtypes.cpp index 596d902..164821e 100644 --- a/examples/knxPython/pybind11/tests/test_numpy_dtypes.cpp +++ b/examples/knxPython/pybind11/tests/test_numpy_dtypes.cpp @@ -350,7 +350,7 @@ TEST_SUBMODULE(numpy_dtypes, m) { // is not a POD type struct NotPOD { std::string v; - NotPOD() : v("hi") {}; + NotPOD() : v("hi"){}; }; PYBIND11_NUMPY_DTYPE(NotPOD, v); #endif diff --git a/examples/knxPython/pybind11/tests/test_stl.cpp b/examples/knxPython/pybind11/tests/test_stl.cpp index e7db8aa..954767c 100644 --- a/examples/knxPython/pybind11/tests/test_stl.cpp +++ b/examples/knxPython/pybind11/tests/test_stl.cpp @@ -78,7 +78,7 @@ struct hash { template